1984_M10_Hitachi_IC_Memories_Data_Book 1984 M10 Hitachi IC Memories Data Book
User Manual: 1984_M10_Hitachi_IC_Memories_Data_Book
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.HITACHI
A World Leader in Technology
HITACHI IC MEMORIES
DATA BOOK
•
HITACHI
INDEX
•
•
•
•
•
•
•
•
•
•
2
QUICK REFERENCE GUIDE TO HITACHI IC MEMORIES ......... 8
• MOS RAM ....................... :.................. 8
• MOS ROM .......................•.................. 10
.• MOS Memories of Wide Operating Temperature Range ............. 10
• Bipolar RAM ......................................... 11
• Bipolar PROM ........................................ 12
PACKAGE INFORMATION ..............•.................. 13
RELIABILITY OF HITACHI IC MEMORIES .•.................. 18
PRECAUTIONS FOR HANDLING IC MEMORIES ................ 26
QUALITY ASSURANCE OF IC MEMORIES .•.................. 29
OUTLINE OF TESTING METHOD ........•.................. 35
APPLICATION OF DYNAMIC RAMS ......................... 38
PROGRAMMING & ERASING OF PROMS ...................... 40
• Programming & Erasing of EPROM ....... , .................. 40
• Programming of Bipolar PROM ............................. 44
MASK ROM PROGRAMMING INSTRUCTION ................... 47
DATA SHEETS ......................................... 51
• MOS STATIC RAM .................................... 51
HM4334-3
1024-word x 4-bit RAM (CMOS) ............. 52
HM4334-4
1024-word x 4-bit RAM (CMOS) ............. 52
HM4334P-3
1024-word x 4-bit RAM (CMOS) ............. 52
HM4334P-4
1024-word x 4-bit RAM (CMOS) ............. 52
HM6148
1024-word x 4-bit RAM (CMOS) ............. 58
HM6148-6
1024-word x 4-bit RAM (CMOS) ............. 58
HM6148P
1024-word x 4-bit RAM (CMOS) ............. 58
HM6148P-6
1024-word x 4-bit RAM (CMOS) ............. 58
HM6148LP
1024-word x 4-bit RAM (CMOS) ............. 64
1024-word x 4-bit RAM (CMOS) ............. 64
HM6148LP-6
1024-word x 4-bit RAM (CMOS) ............. 70
HM6148H-35
HM6148H-45
1024-word x 4-bit RAM (CMOS) ............. 70
HM6148H-55
1024-word x 4-bit RAM (CMOS) ............. 70
HM6148HP-35
1024-word x 4-bit RAM (CMOS) ............. 70
HM6148HP-45
1024-word x 4-bit RAM (CMOS) ............. 70
HM6148HP-55
1024-word x 4-bit RAM (CMOS) ............. 70
HM6148HLP-35 1024-word x 4-bit RAM (CMOS) ............. 74
HM6148HLP-45 1024-word x 4-bit RAM (CMOS) ............. 74
HM6148HLP-55 1024-word x 4-bit RAM (CMOS) ............. 74
4096-word x 1-bit RAM (CMOS) ............. 79
HM6147
HM6147-3
4096-word x 1-bit RAM (CMOS) ............. 79
4096-word x 1-bit RAM (CMOS) ............. 79
HM6147P
HM6147P-3
4096-word x 1-bit RAM (CMOS) ............. 79
HM6147LP
4096-word x 1-bit RAM (CMOS) ............. 83
HM6147LP-3
4096-word x 1-bit RAM (CMOS) ............. 83
HM6147H-35
4096-word x 1-bit RAM (CMOS) ............. 87
4096-word x 1-bit RAM (CMOS) ............. 87
HM6147H-45
HM6147H-55
4096-word x 1-bit RAM (CMOS) .......... '... 87
4096-word x 1-bit RAM (CMOS) ............. 87
HM6147HP-35
HM6147HP-45
4096-word x 1-bit RAM (CMOS) ............. 87
4096-word x 1-bit RAM (CMOS) ............. 87
HM6147HP-55
•
HITACHI
HM6147HLP-35
HM6147HLP-45
HM6147HLP-55
HM6116-2
HM6116-3
HM6116-4
HM61161-2
HM61161-3
HM61161-4
HM6116P-2
HM6116P-3
HM6116P-4
HM6116PI-2
HM6116PI-3
HM6116PI-4
HM6116FP-2
HM6116FP-3
HM6116FP-4
HM6116CG-2
HM6116CG-3
HM6116CG-4
HM6116L-2
HM6116L-3
HM6116L-4
HM6116L1-2
HM6116L1-3
HM6116L1-4
HM6116LP-2
HM6116LP-3
HM6116LP-4
HM6116LPI-2
HM6116LPI-3
HM6116LPI-4
HM6116LFP-2
HM6116LFP-3
HM6116LFP-4
HM6116K-3
HM6116K-4
HM6116AP-10
HM6116AP-12
HM6116AP-15
HM6116AP-20
HM6116ASP-10
HM6116ASP-12
HM6116ASP-15
HM6116ASP-20
HM6116ALP-10
HM6116ALP-12
HM6116ALP-15
HM6116ALP-20
HM6116ALSP-10
HM6116ALSP-12
HM6116ALSP-15
HM6116ALSP-20
4096-word
4096-word
4096-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
2048-word
•
x 1-bit RAM
x 1-bit RAM
x 1-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8·bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
x 8-bit RAM
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
(CMOS)
HITACHI
............. 93
............. 93
... _ ...... _ .. 93
. . . . . . . . . . . .. 97
. . . . . . . . . . . .. 97
. . . . . . . . . . . .. 97
. . . . . . . . . . . .. 97
. . . . . . . . . . . .. 97
. . . . . . . . . . . .. 97
............. 103
............. 103
............. 103
............. 107
............. 107
_ ... _ ........ 107
............. 111
..... _ ....... 111
............. 111
............. 116
............. 116
............. 116
............. 120
............. 120
............. 120
............. 127
............. 127
............. 127
............. 131
............. 131
......... _ .. -131
............. 138
............. 138
............. 138
...... _ ...... 142
............. 142
............. 142
............. 146
............. 146
............. 150
- ............ 150
- ............ 150
....... _ ....• 150
............. 150
............. 150
............. 150
......•...... 150
............. 154
............. 154
............. 154
............. 154
............. 154
............. 154
............. 154
............. 154
3
•
4
HM6117P-3
2048-word x 8-bit RAM (CMOS) ............. 158
HM6117P-4
2048-word x 8-bit RAM (CMOS) ............. 158
HM6l17FP-3
2048-word x 8-bit RAM (CMOS) ............. 163
HM6117FP-4
2048-word x 8-bit RAM (CMOS) ............. 163
HM6117LP-3
2048-word x 8-bit RAM (CMOS) ............. 168
2048-word x 8-bit RAM (CMOS) ............. 168
HM6117LP-4
HM6117LFP-3
2048-word x 8-bit RAM (CMOS) ............. 174
2048-word x 8-bit RAM (CMOS) ............. 174
HM6117LFP-4
HM6168H-45
4096-word x 4-bit RAM (CMOS) ............. 180
HM6168H-55
4096·word x 4-bit RAM (CMOS) ............. 180
HM6168H-70
4096·word x 4-bit RAM (CMOS) ............. 180
HM6l68Hp·45
4096·word x 4-bit RAM (CMOS) ............. 180
HM6168HP-55
4096-word x 4-bit RAM (CMOS) ............. 180
HM6168HP-70
4096-word x 4-bit RAM (CMOS) ............. 180
HM6l68HLP-45 4096-word x 4-bit RAM (CMOS) ............. 181
HM6168HLP-55 4096-word x 4-bit RAM (CMOS) ............. 181
HM6168HLP-70 4096-word x 4-bit RAM (CMOS) ............. 181
HM6167
16384-word x l-bit RAM (CMOS) ............ 182
HM6167-6
16384-word x l-bit RAM (CMOS) ............ 182
HM6167-8
l6384-word x l-bit RAM (CMOS) ............ 182
HM6167P
16384-word x l-bit RAM (CMOS) ............ 182
H M6167P-6
16384-word x l-bit RAM (CMOS) ............ 182
HM6167P-8
16384-word x l-bit RAM (CMOS) ............ 182
HM6167LP
16384-word x l-bit RAM (CMOS) ............ 188
HM6167LP-6
16384-word x l-bit RAM (CMOS) ............ 188
HM6l67LP-8
l6384-word x l-bit RAM (CMOS) ............ 188
HM6l67H-45
16384-word x l-bit RAM (CMOS) ............ 192
HM6167H-55
16384-word x l-bit RAM (CMOS) ............ 192
HM6167HP-45
l6384-word x l-bit RAM (CMOS) ............ 192
HM6167HP-55
l6384-word x l-bit RAM (CMOS) ............ 192
HM6167HCG-45 16384-word x l-bit RAM (CMOS) ............ 199
HM6167HCG-55 16384-word x 1-bit RAM (CMOS) ............ 199
HM6l67HLP-45 16384-word x l-bit RAM (CMOS) ............ 203
HM6167HLP-55 16384-word x l-bit RAM (CMOS) ............ 203
HM6264P-l0
8192-word x 8-bit RAM (CMOS) ............. 207
HM6264P-12
8192-word x 8-bit RAM (CMOS) ............. 207
HM6264P-15
8192-word x 8-bit RAM (CMOS) ............. 207
HM6264LP-l0
8192-word x 8-bit RAM (CMOS) ............. 211
HM6264LP-12
8192-word x 8-bit RAM (CMOS) ............. 211
HM6264LP-15
81 92-word x 8-bit RAM (CMOS) ............. 211
MOS DYNAMIC RAM ............... _ .................. 217
I:lM4716A-l
16384-word x l-bit RAM (NMOS) ............ 218
HM4716A-2
16384-word x l-bit RAM (NMOS) ......... ,' .. 218
HM47l6A-3
16384-word x l·bit RAM (NMOS) ............ 218
HM4716A-4
16384-word x l-bit RAM (NMOS) ............ 218
HM4716AP-l
16384-word x l-bit RAM (NMOS) ............ 218
HM4716AP-2
16384-word x l-bit RAM (NMOS) ............ 218
HM4716AP-3
l6384-word x l-bit RAM (NMOS) ............ 218
HM4716AP-4
16384-word x l-bit RAM (NMOS) ............ 218
HM4816A-3
16384-word x l-bit RAM (NMOS) ............ 229
HM4816A-3E
16384-word x l-bit RAM (NMOS) ............ 229
HM48l6A-4
16384-word x l-bit RAM (NMOS) ............ 229
HM4816A-7
16384-word x l-bit RAM (NMOS) ............ 229
HM4816AP-3
16384-word x l-bit RAM (NMOS) ............ 229
•
HITACHI
HM4816AP·3E
16384·word x Hit RAM (NMOS) •••••••..•.. 229
HM4816AP·4
16384·word x 1·bit RAM (NMOS) .•.•........ 229
HM4816AP·7
16384·word x 1·bit RAM (NMOS) •........... 229
HM4864-2
65536-word x 1·bit RAM (NMOS) ......••.••. 237
HM4B64·3
65536-word x 1·bit RAM (NMOS) ....•....•.. 237
HM4864p·2
65536·word x 1·bit RAM (NMOS) ....••..••.• 237
HM4B64p·3
65536·word x 1·bit RAM (NMOS) .........•.. 237
HM4864CC·2
65536·word x 1-bit RAM (NMOS) .....•...•.. 247
HM4B64CC·3
65536·word x 1·bit RAM (NMOS) .....••..•.. 247
HM48641·2
65536-word x 1-bit RAM (NMOS) .....•...•.. 252
HM4B641·3
66536·word x 1·bit RAM (NMOS) •.•...••.•.• 252
HM4864K·2
65536·word x 1·bit RAM (NMOS) •........•.• 262
HM4864K·3
65536-word x 1·bit RAM (NMOS) .........•.. 262
HM4864A·12
65536·word x Hit RAM (NMOS) ............ 256
HM4864A·15
65536·word x 1·bit RAM (NMOS) ..•....•.... 256
HM4864A·20
65536-word x 1·bit RAM (NMOS) .....••..... 256
HM4864AP-12
66536·word x 1-bit RAM (NMOS) •.•.....•... 256
HM4864AP-15
65536·word x 1·bit RAM (NMOS) .....•...•.. 256
HM4864AP-20
65536·word x 1·bit RAM (NMOS) ............ 256
HM4864ACG·12 65536·word x 1·bit RAM (NMOS) •........•.. 261
HM4864ACG·15 65536·word x 1·bit RAM (NMOS) •........... 261
HM4864ACG·20 66536·word x 1·bit RAM (NMOS) ............ 261
HM4865Ap·12
65536·word x 1·bit RAM (NMOS) ...•.•.•••.. 266
HM4865AP·15
65536·word x 1·bit RAM (NMOS) •....•.•.•.. 266
HM4865AP·20
65536·word x 1·bit RAM (NMOS) .........•.. 266
HM50256·12
262144·word x 1·bit RAM (NMOS) ........... 273
HM50256·15
262144·word x 1·bit RAM (NMOS) .•...••••.. 273
HM50256·20
262144·word x 1·bit RAM (NMOS) ....•...•.. 273
HM50257·12
262144·word x 1·bit RAM (NMOS) ..••..•.... 280
HM50257·15
262144·word x 1·bit RAM (NMOS) ....•...... 280
HM50257·20
262144·word x 1·bit RAM (NMOS) .•......... 280
• MOS Mask ROM ..........•.............•.••.....•..... 287
HN61364P
8192·word x 8·bit ROM (CMOS) •..•..••.••.. 288
HN61364FP
8192·word x 8·bit ROM (CMOS) ............. 288
HN61365P
8192·word x 8·bit ROM (CMOS) •.........•.. 290
HN61366P
8192-word x 8·bit ROM (CMOS) .•........•.. 292
HN43128P
16384·word x B-bit or
32768·word x 4·bit ROM (CMOS) ..•..•...... 294
HN613128P
16384-word x 8·bit ROM (CMOS) ............ 296
HN613128FP
16384·word x B-bit ROM (CMOS) ..•......... 296
HN61256P
3276B-word x B-bit or
65536·word x 4·bit ROM (CMOS) ..•......••. 298
HN61256FP
32768·word x B-bit or
65536·word x 4·bit ROM (CMOS) .........•.. 298
HN613256P
32768·word x B-bit ROM (CMOS) •.....•..••. 300
HN613256FP
3276B-word x B-bit ROM (CMOS) .••....•.••. 300
HN62301P
131072·word x 8·bit ROM (CMOS) ........... 302
• MOS PROM .....................••.........•.....•.• 305
HN462716
2048·word x 8·bit U.V. Erasable &
Electrically PROM (NMOS) •............... 306
HN462716G
204B-word x 8·bit U.V. Erasable &
Electrically PROM (NMOS) ........•....... 306
HN462532
4096·word x 8·bit U.V. Erasable &
Electrically PROM (NMOS) .........••..... 310
eHITACHI
5
HN462532G
HN462532P
HN462732
HN462732G
HN462732P
HN462732GI
HN482732AG-20
HN482732AG-25
HN482732AG-30
HN482764
HN482764-3
HN482764-4
HN482764G
HN482764G-3
HN482764G-4
HN27C64G-20
HN27C64G-25
HN27C64G-30
HN4827128G-25
HN4827128G-30
HN4827128G-45
HN48016P
4096-word x 8-bit U.V. Erasable &
Electrically PROM (NMOS) .••..••.•••••.••••.•••. 310
4096-word x 8-bit U.V. Erasable &
Electrically PROM (NMOS) ••......•.•.•.•..•••.•. 310
4096-word x 8-bit U.V. Erasable &
Electrically PROM (NMOS) ..•••••••••.••••..•..•• 314
4096-word x 8-bit U.V. Erasable &
Electrically PROM (NMOS) •••••••••.•••.••••..••• 314
4096-word x 8-bit U.V. Erasable &
Electrically PROM (NMOS) •••.••.••••••••••••.••. 314
4096-word x 8-bit U.V. Erasable &
Electrically PROM (NMOS) •••••••.•••...••••.•••• 318
4096-word x 8-bit U.V. Erasable &
Electrically PROM (NMOS) ••••..•.••••.••..•..••. 321
4096-word x 8-bit U.V. Erasable &
Electrically PROM (NMOS) ....................... 321
4096-word x 8-bit U.V. Erasable &
Electrically PROM (NMOS) .•.•..•.••••..•..•...•. 321
8192-word x 8-bit U.V. Erasable &
Electrically PROM (NMOS) •••.•••.•••••••.••••••. 324
8192-word x 8-bit U.V. Erasable &
Electrically PROM (NMOS) •••.••.•••••.•••••..•.. 324
8192-word x 8-bit U.V. Erasable &
Electrically PROM (NMOS) ••••••...•.••...••.•••• 324
8192-word x 8-bit U.V. Erasable &
Electrically PROM (NMOS) •••••••••••••••••.••..• 324
8192-word x 8-bit U.V. Erasable &
Electrically PROM (NMOS) ••.••••.•.•••.••••••••• 324
8192-word x 8-bit U.V. Erasable &
Electrically PROM (NMOS) ••••••••••.••••.•••...• 324
8192-word x 8-bit U.V. Erasable &
Electrically PROM (NMOS) ..••.. : ••••.•••.•.•••.• 329
8192-word x 8-bit u.v. Erasable &
Electrically PROM (NMOS) •••••••••••••••.•.••.•. 329
8192-word x 8-bit U.V. Erasable &
Electrically PROM (NMOS) •••••.•.••••.•.••..•••• 329
816384-word x 8-bit U.V. Erasable &
Electrically PROM (NMOS) •••••.•••••••••.••••••• 332
816384-word x 8-bit U.V. Erasable &
Electrically PROM (NMOS) •••••.•..••••••..•..••. 332
816384-word x 8-bit U.V. Erasable &
Electrically PROM (NMOS) ••••••••••..•••...••••. 332
2048-word x 8-bit Electrically Erasable &
PROM (NMOS) •..•.•.••... ; •.•••••...•..••.•••. 336
• Bipolar RAM .••..•••••••••.••••••.•...•.•••••••.••... 341
HM10414
256-word x 1-bit RAM (ECl 10K) ••••••....•. 342
HM10414-1
256-word'x 1-bit RAM (Eel 10K) ••..••.••... 342
HM2110
1024-word x 1·bit RAM (Eel 10K) .••..•••..• 346
HM2110·1
1024·word x Hit RAM (Eel 10K) ••.•.••.... 346
HM2112
1024-word x 1·bit RAM (Eel 10K) •.••.•••..• 350
HM2112·1
1024·word x 1·bit RAM (Eel 10K) •••••..•••. 350
HM10422
256-word x 4·bit RAM (Eel 10K) • . . . • . . • • .. 355
HM10422·7
256·word x 4·bit RAM (Eel 10K) .•.•••.•••.• 360
6
eHITACHI
HM10470
4096-word x 1-bit RAM (ECl 10K) _ - ......... 363
HM10470-1
4096-word x 1-bit RAM (ECl 10K) .....•..... 363
HM10470F
4096-word x 1-bit RAM (ECl 10K) ........... 363
HM10470-15
4096-Wordx 1-bit RAM (ECl 10K) _ .......... 368
4096-word x 1-bit RAM (ECl 10K) _ .......... 371
HM2142
HM10474
1024-word x 4-bit RAM (ECl 10K) _ .......... 374
HM10474-15
1024-word x4-bit RAM (ECl 10K) ........ , .. 374
HM10480
16384-word x 1-bit RAM (ECl 10K) .......... 379
HM10480F
16384-word x 1-bit RAM (ECl 10K) .......... 379
HM100415
1024-word x 1-bit RAM (ECl 1ooK) .......... 382
HM100415CC
1024-word x 1-bit RAM (ECl 1OOK) .........• 382
HM1OO422
256-word x 4-bit RAM (ECl 100K) ........... 385
HM100422F
256-word x 4-bit RAM (ECl 100K) _ .......... 385
HM1oo422CC
256-word x 4-bit RAM (ECl 100K) ........... 385
HM100470
4096-word x 1-bit RAM (ECl 100K) .......... 388
HM1oo470-15
4096-word x 1-bit RAM (ECl 100K) .......... 388
HM 100474
1024-word x 4-bit RAM (ECl 100K) .......... 391
HM100474-15
1024-word x 4-bit RAM (ECl 1ooK) .......... 391
HM100474F
1024-word x 4-bit RAM (ECl 1OOK) .......... 391
HM100474F-15
1024-word x 4-bit RAM (ECl 1OOK) .......... 391
HM 100480
16384-word x 1-bit RAM (ECl 1ooK) ......... 396
HM100480F
16384-word x 1-bit RAM (ECl 100K) ......... 396
HM2504
256-word x 1-bit RAM (TTL) ............... 399
HM2504-1
256-word x 1-bit RAM (TTL) ............... 399
HM2510
1024-word x 1-bit RAM (TTL) .............. 403
HM2510-1
1024-word x 1-bit RAM (TTL) .............. 403
HM2510-2
1024-wrod x 1-bit RAM (TTL) .............. 403
HM2511
1024-word x 1-bit RAM (TTL) .............. 407
HM2511-1
1024-word x 1-bit RAM (TTL) .............. 407
• Bipolar PROM ........................................ 411
HN25044
1024-word x 4-bit PROM (TTL) ............. 414
1024-word x 4-bit PROM (TTL) ............. 414
HN25045
HN25084
2048-word x 4-bit PROM (TTL) ............. 419
HN25085
2048-word x 4-bit PROM (TTL) ............. 419
HN25084S
2048-word x 4-bit PROM (TTL) ............. 422
2048-word x 4-bit PROM (TTL) ............. 422
HN25085S
HN25088
1024·word x 8-bit PROM (TTL) ............. 425
1024-word x 8-bit PROM (TTL) ............. 425
HN25089
HN25088S
1024-word x 8-bit PROM (TTL) ............. 428
HN25089S
1024-word x 8-bit PROM (TTL) ............. 428
HN25088l
1024·word x 8-bit PROM (TTL) ............. 431
HN25089l
1024-word x 8-bit PROM (TTL) ............. 431
HN25168S
2048-word x 8-bit PROM (TTL) ............. 434
2048-word x 8-bit PROM (TTL) ............. 434
HN25169S
• Memory Support Circuits ........................... : ..... 437
HD2912
Quadruple TTl-to-MOS Clock Drivers ......... 438
HD2916
Quadruple TTl·to-MOS Clock Drivers ......... 441
HD2923
Quadruple ECl-to-TTl Drivers .............. 444
NOTICE
The example of an applied circuit or combination with other equipment shown
herein indicates characteristics and performance of a semiconductor-applied
products. The company shall assume no responsibility for any problem involving
a patent caused when applying the descriptions in the example.
eHITACHI
7
.QUICK REFERENCE GUIDE TO HITACHI IC MEMORIES
.MOS RAM
Mode
Total
Bit
Type No.
ProcesS'
Organization
(word)
Xbit
HM4334-3
HM4334-4
HM6148
HM6148-6
HM6148L
1024X4
HM6148L-6
HM6148H-35"
HM6148H-45"
HM6148H-55"
HM6148HL-35"
4k-bit
HM6148HL-45"
HM6148HL-55··
HM6147
HM6147-3
HM6147L
HM6147L-3
HM6147H-35
4096 X1
HM6147H-45
HM6147H-55
Static
CMOS
HM6147HL-35
HM6147HL-45
HM6147HL-55
HM6116-2
HM6116-3
HM6116-4
HM6116L-2
HM6116L-3
HM6116L-4
HM6116A-I0
HM6116A-12
HM6116A-15
16k-bit
2048x8
HM6116A-20
HM6116AL-I0
HM6116AL-12
HM6116AL-15
HM6116AL-20
HM6117-3
HM6117-4
HM6117L-3
HM6117L-4
Access
Time
(ns)
max
300
450
70
85
70
85
35
45
55
35
45
55
70
55
70
55
35
45
55
35
45
55
120
150
200
120
150
200
100
120
150
200
100
120
150
200
150
200
150
200
Cycle Supply
Time Voltage
(ns)
min
pation
~OO
150
200
(W)
(V)
460
640
70
85
70
85
35
45
55
35
45
55
70
55
70
55
35
45
55
35
45
55
120
150
200
120
150
200
100
120
150
200
100
120
150
200
150
Power
Dissi-
Package·
Pin
No. CC CG G
•
•
•
•
101'/20m
0.1m10.2
51'/0.2
•
•
•
0.1m10.2
51'/0.3
18
•
•
0.1m175m
51'/75m
•
+5
r---
0
-
51'/0.15
0.1m10.18
20~/0.16
0.1m115m
24
51'/10m
0.lm/0.2
101'/0.18
•
ment
HM-6514-9
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
••
••
•
•
•
•••
•••
•••
••
••
0.lm/0.15
Replace-
P FP SP
Page
52
52
2148
2148-6
2148-45
2148-55
2147
2147H-l
2147H-2
•
•
•
•
•••
•
•
•
•
•
•
•
•
••
••
••
••
•
•
•
•
•
•
•
•
•
58
58
64
64
70
70
70
74
74
74
79
79
83
83
87
87
87
93
93
93
97
97
97
120
120
120
150
150
150
150
154
154
154
154
158
158
168
168
(to be continued)
8
eHITACHI
Mode
Total
Bit
16k-bit
SRAM
Type No.
Organization
Process
(word)
Xbit
HM6168H-45'
HM6168H-55'
HM6168H-70'
4096 X4
HM6168HL-45'
HM6168HL-55'
HM6168HL-70'
HM6167
HM6167-6
HM6167-8
HM6167L
HM6167L-6
(;MOS 16384 X 1
HM6167L-8
HM6167H-45
HM6167H-55
HM6167HL-45
HM6167HL-55
HM6264-10
HM6264-12
HM6264-15
8182x8
HM6264L-I0
HM6264L-12
HM6264L-15
HM4716A-l
HM4716A-2
HM4716A-3
HM4716A-4
16384 X1
HM4816A-3 (
HM4816A-3E
HM4816A-4
HM4816A-7
HM4864-2
HM4864-3
NMOS
HM4864A-12
HM4864A-15
65536 X1
HM4864A-20
HM4865A-12"
HM4865A-15"
HM4865A-20"
HM50256-12 ••
HM50256-15 ••
HM50256-20 ••
262144 X I
HM50257-12 ••
HM50257-15 ••
HM50257-20"
I
64k-bit
16k-bit
DRAM
64k-bit
256k-bit
Access Cycle Supply
Time Time Voltage
(ns)
max
45 .
55
70
45
55
70
70
85
100
70
85
100
45
55
45
55
100
120
150
100
120
150
120
150
200
250
100
105
120
150
150
200
120
150
200
l20
150
200
120
150
200
120
ISO
200
Power
Dissipation
Pin
(W)
No.
(ns)
min
45
55
70
45
55
70
70
85
100
70
85
100
45
55
45
55
100
l20
150
100
120
150
320
320
375
410
235
200
270
320
270
335
230
260
330
230
260
330
220
260
330
220
260
330
(V)
Package·"
ce CG
••
•
•
•
••
••
51'/0.25
20
••
•
•
•
•••
•••
•
•
•
•
•
•
•
51'/0.15
+5
0.1m/0.2
51'/0.2
0.lm/0.2
28
101'/0.2
+12,
+5,
-5,
20m/0.46
llm/0.15
•
20m/0.33
20m/0.275
+5
20m/0.275
20m/0.35
20m/0.35
Replacement
2168
••
••
0.1m/0.25
25m/0.15
G P FP SP
•
16
•
•
•
•
•
•
•
•
•
•
••
••
••
•
•
•
•
•
•
•
•
•
2167
2167-6
2167-8
IMS1400
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
MK4116-2
MK4116-3
MK4116-4
2l18-3
2118-4
2118-7
Page
ISO
ISO
ISO
181
181
181
182
182
182
188
188
188
192
192
203
203
207
207
207
211
211
211
218
218
218
218
229
229
229
229
237
237
256
256
256
266
266
266
273
273
273
280
2SO
2SO
• Under development
Preliminary
AHM6116LP Series: lOpW
The package codes of CC. CG, p, FP and SP are applied to the package materials as follows.
CC : Side~brazed Ceramic Leadless Chip Carrier. CG : Glass-sealed Ceramic Leadless Chip Carrier, G: Cerdip, P: Plastic DIP,
FP : Small Sized Plastic Flat Package(SOP), SP: Sktnny Type Plastic DIP
.*.*.
•
HITACHI
9
.MOS ROM
Total
Bit
Program
Type No.
Process
Organization
(word)
xbit
(ns)
max
8192X8
250
f--250
HN61364
64k-bit HN61365
HN61366
Mask
128k-bit
HN43128
CMOS
HN61256
(V)
Package"·
Pin
C
No.
r-6500
16384X8
250
32168X8
65536X4
3500
1.5m
28
+S
3m
28
5p/0.05
28
32768x8
250
1M-bit HN62301··
131072x8
350
5m/60m
28
16k-bit HN462716
2048X8
450
0.555
24
4096X8
HN482732A-25
HN482732A-30
HN482764
-
250
+5
0.555
-
~
HN27C64G-25
28
300
HN4827128-25··
250
NMOS
16384x8
HN4821128-45··
r-300
r--
0.554
28
•
450
NMOS
16384 X8
350
+S
0.16
24
*** The package codes of C, G, P and FP are apphed to the package materials as follows.
* Under development
*. Preliminary
C:
Side~brazed
•
•
• •
• •
• •
•
Page
meRt
288
290
292
294
296
--
298
300
302
2716
306
TMS2532
310
2732
2732A-2
314
321
2732A
321
2732A-3
321
2764
324
2764-3
324
2764
329
2764
329
324
•
•
•
•
40mW
250
r--
HN27C64G-30
24
0.788
8192x8 r - -
HN27C64G-20
16k-bit HN48016
250
- 300
450
HN482764-4
128k-bit HN4827128-30"
200
----aoo
NMOS
HN482164-3
64k-bit
-
0.788
--
~
32k-bit HN482732A-20
U. V. Erasable
& Electrically
-
450
HN462732
•
• •
• •
• •
•
•
•
• •
••
• •
•
0.858
Replace-
P FP
• •
•
24
16384x8
32168x4
HN462532
G
28
5p/0.05
- 5p/75m
HN613256
Electrically Erasable
Power
Dissipation
(W)
250
HN613128
256k-bit
Access Supply
Time Voltage
2764
329
382
332
332
•
386
Ceramic DIP. G : Cerdip, P: Plastie DIP, FP: Plastic Flat Package
.MOS MEMORIES OF WIDE OPERATING TEMPERATURE RANGE
Mode
Total
Bit
Type No.
Operating
Temperature
Access
Organization
Time
Power
Dissipation
(wordXbit)
Range
(ns)
max
(W)
ee)
HM61161-2
120
HM61161-3
150
HM61161-4
Static RAM
16k-bit
HM6116Ll-2
HM6116Ll-3
-40 to +85
2048 X8
-55 to +125
HM6116K-4
HM48641-2
64k-bit
HM48641-3
HM4864K-2
65536 X1
32k-bit
HN4627321
4096X8
-40 to +85
A HM6116LPI Series: lOp\\'
10
•
150
200
150
-40 to +85 f - - - 200
-55 to +85
HM4864K-3
EPROM
120
20p6/0.16
HITACHI
150
24
0.lm/0.18
Page
G
•
•
•
•
•
103
•
•
•
•
•
•
•
103
103
127
127
127
16
0.1/0.788
24
146
·
252
•
252
:
15m/0.3
200
450
P
• •
0.1m/0.18
200
HM6116K-3
Dynamic RAM
Pin No.
200
150
HM6116Ll-4
Package···
146
• I 252
.! 252
•
318
• BIPOLAR RAM
Level
Total
Bit
256-bit
lk-bit
Type No.
HMI0414
HMI0414-1
25
25
HMI0470-1
15
4k-bit
256-bit
Open
Emitter
15
10
24
18
0.2
24
16384 x 1
25
0.03
20
1024 X I
10
0.6
16
HMI00422
256X4
10
0.8
24
HMI00470-15
HMI00474
HMI00480'
HM2504
HM2504-1
4096 X I
15
HM2510-2
HM2511-1
-4.5
25
1024X4
15
16384 X 1
25
55
256Xl
0.2
24
0.05
20
70
45
1024X 1
+5
0.5
35
3-state
18
1.8
45
Open
Collector
0.2
70
45
0.5
16
•
•
•
• •
• •
• •
•
•
•
• •
• •
• •
• •
• • •
•
•
• •
• •
• •
•
•
•
•
•
•
•
Page
CC
FI0414
FlO415
FI0415A
•
0.3
25
G
•
HMI00415
HM2511
*
**
1.0
0.2
15
HM2510-1
Ik-bit
16
25
1024X4
HM2510
TTL
0.8
-5.2
Replacement
F
•
HMI0480
HMI00474-15
16k-bit
4096 x 1
HM2142
HMI00470
ECL
lOOk
7
Pin
No.
0.8
10
HMI0470
HMI0474-15
0.5
8
256x4
(mW/bit)
Package··
2.8
10
HM2112-1
HMI0474
lk-bit
1024 x 1
Power
Dissipation
(V)
8
35
HM2112
Supply
Voltage
10
256Xl
HM2110-1
HMI0470-15
16k-bit
Time
(ns)
max
HM2110
HMI0422-7
4k-bit
Access
Output
(word)
xbit
HMI0422
ECL
10k
Organization
FI0422
FI0470
342
342
346
346
350
350
355
360
363
363
368
371
FlO0415
374
374
379
382
FlO0422
385
FlO0470
388
FlO0474
388
391
391
Fl0474
Fl0480
FlO0480
93411
93411A
396
399
399
403
93415
93415A
93425
403
403
407
407
Preliminary
The package codes of F. G and CC are applied to the package material as follows.
F : Flat Package, C: Cerdip, CC: Side-brazed Ceramic Leadless Chip Carrier
•
HITACHI
11
• BIPOLAR PROM
Total
Bit
Level
4k-bit
Type No.
8k-bit
HN25044
HN25045
Time
(ns)
max
1024X4
ole
ole
HN25085
3-8
2048 X 4
3-8
HN25088
ole
HN25089
3-s
HN250898
1024X8
ole
3-s
HN251688
HN251698
2048 X 8
60
18
18
+5
600
50
Ole
3-0
350
60
600
G: Cerdip
•
24
100
• The p.ekage code of G is applied to the material as follows.
12
500
550
3-s
HN25089L
(mW)
Pin
No.
pation
(V)
Package'
50
ole
HN25088L
Power
Dissi-
60
ole
HN2S0858
8upply
Voltage
50
3-s
HN25084
HN250888
16k-bit
Access
Output
(word)
Xbit
HN250848
TTL
Organization
HITACHI
24
Replacement
F
G
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Page
P
828190
414
414
419
419
422
422
425
425
428
428
431
431
434
828191
434
828136
828137
828184
828185
828180
828181
• PACKAGE INFORMATION (Dimensions in mm)
.Dual-in-line Plastic
.--------------------------------------------------------------~
eDP-16
r---------------------------------------------------------------------------~
eOP-20
eOP-24
, !·~m;'i·~
-=8
;;
I
~'I
13
12
II
5O&na12S4mln
W
o.-,s'.Jl\~~OZ(H3tI
eOP-24A
eOP-28
,,
10
o.o".Rooo"
20
Applicable les
DP-16
HM4716AP-l, HM4716AP-2, HM4716AP-3, HM4716AP-4, HM4816AP-3, HM4816AP-3E, HM4816AP-4,
HM4816AP-7, HM4864P-2, HM4864P-3, HM4864AP-12, HM4864AP-15, HM4864AP-20, HM4865AP-12,
HM4865AP-15, HM4865AP-20
DP-18
HM4334P-3, HM4334P-4, HM4334P-3L, HM4334P-4L, HM6148P. HM6148P-6, HM6148LP, HM6148LP-6,
HM6148HP-35, HM6148HP-45,' HM6148HP-55, HM6148HLP-35, HM6148HLP-45, HM6148HLP-55, HM6147P,
HM6147P-3, HM6147LP, HM6147LP-3, HM6147HP-35, HM6147HP-45, HM6147HP-55, HM6147HLP-35,
HM6147HLP-45, HM6147HLP-55
DP-20
HM6168HP-45, HM6168HP-55, HM6168HP-70, HM6168HLP-45, HM6168HLP-55, HM6168HLP-70, HM6167P,
HM6167P-6, HM6167P-8, HM6167LP, HM6167LP-6, HM6167LP-8, HM6167HP-45, HM6167HP-55,
HM6167HLP-45, HM6167HLP-55
DP-24
HM6116P-2, HM6116P-3, HM6116P-4, HM6116LP-2, HM6116LP-3, HM6116LP-4, HM6116AP-I0,
HM6116AP-12, HM6116AP-15, HM6116AP-20, HM6116ALP-I0, HM6116ALP-12, HM6116ALP-15,
HM6116ALP-20, HM6117P-3, HM6117P-4, HM6117LP-3, HM6117LP-4, HN61365P, HN61366P, HN48016P,
HM6116PI-2, HM6116PI-3, HM6116PI-4, HM6116LPI-2, HM6116LPI-3, HM6116LPI-4
~
HM6116ASP-I0, HM6116ASP-12, HM6116ASP-15, HM6116ASP-20, HM6116ALSP-I0, HM6116ALSP-12,
DP-24A HM6116ALSP-15, H~11"'6-'-'A-"L"'S'-P_'-2"'O_________________________________________________
DP-28_~H_M_6_2_64_P~-~10_,_H_M~6_2~64_P~-_12_,
__
HM~6~2~64_P_-_1_5,~H~M~62_6_4L~P_-~1~O,__H_M_62_6_4L_P_-_1_2,__H_M_62_6_4L_P_-_1_5,__H_N_61_3_64_,_________
HN43128P, HN613128P, HN61256P, HN613256P, HN62301P
•
HITACHI
13
Package Information - - - - - - - - - - - - - - - - - - - - - - - - - - - - .CEROIP
eOG·16A
eOG·16
l;i
~f\
0" - 15"
~'
12
11
10
9
OJO-O.36~
~~l~-\~
•
0.20 -0.38
eOG·16B
eOG·18
1,1..,
1.1;
.
~
•
~ 5
::::
1.
l:i
12
I"
t-
11
1"
eOG·20
eOG·24A
~
10
11
12,-_+-_..f.
15.24
I ~~i""
~
5.•9",,2.5Im;,
(}''''IJ~-------r-1o-II.36
14
•
HITACHI
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - P a c k a g e Information
eOG-28
~
59..,
0'-15·r-l0.20-U6
Applicable ICs
DG-16
DG-16A
DG-16B
DG-18
DG-20
DG-24
DG-24A
HMI0414, HMI0414-I, HM2504, HM2504-I, HD2912
HM4716A-I, HM4716A-2, HM4716A-3, HM4716A-4, HM2110, HM2110-I, HM2112, HM2112-I, HMIOO415. HM2510,
HM2510-1, HM2510-2. HM2511, HM2511-I, HD2916, HD2923
HM4816A-3, HM4816A-3E, HM4816A-4, HM4816A-7, HM4864-2, HM4864-3, HM4864A-12. HM4864A-15,
HM4864A-20, HMS0256-12, HMS0256-15, HM50256-20, HMS0257-12, HMS0257-15, HMS0257-20, HM46641-2,
HM48641-3, HM4864K-2, HM4864K-3
HM4334-3, HM4334-4, HM6148, HM6148-6, HM6148H-35, HM6148H-45, HM6148H-55, HM6147, HM6147-3,
HM6147H-35, HM6147H-45, HM6147H-55, HMI0470, HMI0470-1, HMI0470-15, HM2142, HMIOO470,
HMI00470-15, HN25044, HN25045, HN25084, HN25085, HN25084S, HN25085S
HM6168H-45, HM6168H"55, HM6168H-70, HM6167, HM6167-6, HM6167-8, HM6167H-45, HM6167H-55,
HMl0480, HMIOO480
HM6116-2, HM6116-3, HM6116-4, HM6116L-2, HM6116L-3, HM6116L-4, HM61161-2, HM61161-3, HM61161-4,
HM6116LI-2, HM6116LI-3, HM6116LI-4, HM6116K-3, HM6116K-4, HN25088, HN25089, HN25088S, HN25089S,
HN25088L, HN25089L, HN25168S, HN25169S
HMI0422, HMI0422-7, HMI0474, HMI0474-15, HMlOO422, HMlOO474, HMIOO474-15
DG-24B
HN462716G, HN462532G, HN462732G, HN482732AG-20, HN482732AG-25, HN482732AG-OO, HN462732GI
DG-28
HN482764G, HN482764G-3, HN482764G-4, HN4827128G-25, HN4827128G-30, HN4827128G-45
• Side- brazed CeramIc DIP
eOC-24C
1493
1<1>
2
3
4
5
6
7
•
9
"I
2
I
I
I
2
I
2
2
20
I
I
1
I
I
I
I
--tI
!
I
1493
I ••
2
28
3
4
5
6
7
8
c-- _.
9
0
I
i
I2
I3
I4
15.24!
508m.. 2.54.1,
,~
O'''I~
I
..
eOC-28B
2
8
O'-ldJ
10,20"'0.36
I
27
26
25
2
2
2
2
I
I
I
I
I5
5J8..,
I
2.541l1n
10.26-0.36
Applicable IC.
DC-24C HN462716, HN462532, HN462732'
DC-28B HN482764, HN482764 -3, HN482764-4
_HITACHI
15
Package Information - - - - - - - - - - - - - - - - - - - - - - - - - - - - e Flat Package.
eFp·54
eFP·24
2.50max
eFG·20
eFG·18
~r~-----~
;;t;a
~
.FG·24
.Appllcable les
HM6116FP-2, HM6116FP-3, HM6116FP-4,
HM6116LFP-2, HM6116LFP-3, HM6116LFP-4,
HM6117FP-3, HM6117FP-4, HM6117LFP-3,
HM6117LFP-4
HN61364FP, HN613128FP, HN61256FP,
FP-54
HN613256FP
FG-18 HMI0470F
FP-24
HMI04~qF, HMI00480F
HMI0422F, HMI0422F-7, HMI0474F,
FG-24 HMI0474F-15, HMI00422F, HMI00474F,
HMI00474F-15
FO-20
16
•
HITACHI
--------------------------------------------------------------Package Information
• Leadless Chip Carrier
.CC-18
.CC-24
~ I ,,~,=
1
~1
'-;
•
3·I{o.3
~,i
... i,t!/! _).Hft
3~::~'.
~I~
':W
HIl.'
.94
.
~I
I HHHHHHH I
~~
I-CO.5
.CG-18
.CG-20
_
lQ.M()±U.•ltll
_
~!D\II'",1±1I'3"
f13
!.i:
,':
lJj
:< i{1l.:<
~
~
:i.Ur! _).Mb"1
jO-'-IW"
';;J _
;5,:
I
:.1'
',10
-.
1~C(J.5
... !!.l,lij..l '.2
.Applicable ICs
.CG-32
1."
CC-18
I
CC-24 .HMI00415CC, HMI00422CC
HM4864ACG-12, HM4864ACG-15
CG-18 HM4864ACG-20
t---~-
~::l
__ v
-·-f--Iv
y
HM4864CC-2, HM4864CC-3
CG-20
HM6167HCG-45, HM6167HCG-55
CG-32
HM6116CG-2, HM6116CG-3,
HM6116CG-4
1
•
HITACHI
17
• RELIABILITY OF HITACHI IC MEMORIES
1. STRUCTURE
IC memories are classified into Bipolar and MOS
structural types. with unique. respective characteristics. Bipolar characteristics are high speed and small
cepacity. while MOS features large capacity.
and degree of integration. stable product reliability is
achieved in the manufacturing process by incorporating past achievements in single cell deSign. and the
proven reliability of each respective technology. Unified production standards are applied in design. manufacture. and inspection stages. and reliability is
guaranteed by using TEG (Test Element Group) evaluation. Examples of Bipolar and MOS memory cell
circuits are shown in Table 1.
Produced with the most advanced semiconductor
manufacturing technologies. the LSI memory is integrated in high density by unit patterns celled "cells."
Despite differences in circuit deSign. pattern layout.
• Table 1 Example. of Ba.ic Cen Circuit of IC Memories
Bipolar memory
Classification
(RAM)
Main memory of computer.
microcomputer memory
Microcomputer
control use
Application
NMOS memory
(PROM)
NMOS memory
(Dynamic RAM)
Bipolar memory
(PROM)
For
microcomputer
control
Example of
basic cell
circuit
IC memory chips are produced in Ceramic. Cerdip. and
Plastic packages. Leadless Chip Carriers (LCC's) for
high package density. and Small Outline (SO) packages are currently being developed.
Hermetically sealed Ceramic and Cerdip packaging is
suitable for high reliability equipment. Plastic. the
leading semiconductor package. is used in a wide
variety of applications. Hitachi's improved Plastic
package provides a reliability level nearly that of the
hermeticelly sealed Ceramic and Cerdip packages.
Table 2 shows examples of IC memory package
outlines.
• Table 2 Examples of Ie Memory Package Outlines
• Ceramic DIP
Pin
.,6
.24 Pin
. ";.-......
~
......"
18
.,'
•
HITACHI
.28 Pin
___________________________ Reliability of Hitachi
Ie Memories
• Cerdip
.24 Pin
.20 Pin
.18 Pin
.16 Pin
• 28 Pin with Lid
• 24 Pin with Lid
• Plastic DIP
.16Pin
.18Pin
.20Pin
~"
2. RELIABILITY DATA
assured in all device types. Results have further indicated that the greater the device capacity, the higher
the reliability per bit.
2.1 Reliability test data on Bipolar memories
Reliability test data is shown in Tables 3 and 4. Since
unified design and quality control standards are applied in the manufacturing process, reliability is
• Table 3 Results on Bipolar Memory Reliability Tests (1)
HMl00422(Chip Carrier)
HMI0470 (Cerdip)
Test item
Total
Test condition
sam-
pIes
component
Fan·
Failure
Sam·
ures
rate'
pies
hours
Ta-12S'C
V" - -S.2V(HMI0470)
HiPtemperature
(Operating)
~.-S.SV(HN2S089)
C.H.
l/hr
Total
component
hours
-
-
3,4XIO·'
40
4XIO'
125
4.0 X10'
0
2.3xlO'·
80
2.7xI0·
0
HN25089(Cerdip)
Total
Fail·
Failure
Sam-
ures
rate'
pies
-
-
0
2.3XIO'·
Fail·
Failure
ures
rate •
component
hours
C.H.
l/hr
36
3.6XIO·
0
2.6XIO-·
10
1.0XIO·
0
9.2xIO"
Ta-ISO'C
V" - -S.2V(HMI0470)
V,,- -5 .OV(HMlOO422)
Vcc-S,SVf
(HN2S089)
' m -IPs
Hightemperature
storage
T.-200·C
27
2.7XIO'
0
3.4XIO'·
40
4XIO'
0
2.3xIO"
IS
1.5XIO·
0
6.lxIO'·
T.-29S'C
20
2.0xlO'
0
UXIO"
40
4xIO'
0
2.3xIO'·
IS
1.5xIO·
0
6.lxI0'·
•
HITACHI
* Estimated failare ratE" with confidence level 60 %
19
Reliability of Hitachi
Ie M e m o r i e s - - - - - - - - - - - - - - - - - - - - - - - -
• Table 4 Results on Bipolar Memory Reliability Tests (2)
HMI0470(Cerdip)
Test condition
Test item
HMl00422 (Chip c.. rier)
Samples
Failures
Samples
Failures
HN25089 (Cerdip)
Samples
Failures
Temperature cycling
-65'C-+150'C, 10 cycles
120
0
40
0
45
0
Soldering heat
260 'c, 10 seconds
22
0
-
-
22
0
Thermal shock
0'C-+I00'C, 10 cycles
36
0
20
0
22
0
30
0
60
0
22
0
40
0
60
0
22
0
40
0
60
0
22
0
1500G, 0.5 ms,
Mechanical shock
Three times each for X, Y and Z
l00-2000Hz, 20G
Variable frequency
Three times each for X, Y and Z
Constant -acceleration
20000G, 1 minute, each for X, Y and Z
~
HM6116P 16K SRAM, HM6147P 4K SRAM,
HN462732 and HN462532 32K EPROMs, and
HN462716 16K EPROM.
2.2 Reliability test date on MOS memories
Tables 5, 6, and 7 depict reliability test data on a
representative group of MOS memory typesHM4864 64K DRAM, HM4716AP 16K DRAM,
• Tllble 5 Results on MOS Memory Reliability Tests (1)
Test item
Test
condition
HM4864 Ceramic)
com·
Failure
Sam- Total
ponent Fail·
pies
ures
rate*
hours
High·
C.H.
temperature Ta=12S·C
1872 3.33xI0' 3'"
VCC=S.SV
dynamic
tcyc=3l's
operation
High·
temperature Ta=20ifC
20
4.0xI0'
0
storage
High·
temperature Ta=2S9"C
storage
High.
temperature Ta=29S"C
storage
EstImated failure rate WIth confidence level 60%
-
..
Test item
C.H.
1.0xI0'
0
9.2xl0'6
2.3xI0"
140
1.4xI0'
0
6.6xl0'6
-
-
-
100
S.OxlO'
0
1.8x10"
-
-
-
100
4.2xI0'
1*'
4.8x10· 5
HM4716AP (Plastic)
comFailure
Sam- Total
ponent Failpies
ures
rate"
hours
Remarks
*' Oxide
failure x 2
Unknown x I
*, Data
disappearance
.
HM6116P/HM6147P (plastic)
com·
Failure
Sam· Total
ponent Failpies
ures
rate*
hours
Ta=12f.C
High·
Vpp=13.2V
C.H.
C.H.
l/hr
(NMOS)
temperature
dynamic . VCC=S.SV 2330 3.46x10' 6*' 2.12x10" 1216 1.90xl0'6 3'"
operation
(CMOS)
tcYc=3l's
High·
temperature Ta=ISifC
4S 4.SxlO' 0
2.0xlO"
20 2.0xlO' 0
storage
Ta=8S·C
High·
temperature RH=8S%'
VDP=12V
and high.
3081 6.2xlO' 19*' 3.bl0-' 630 1.3x10' 4'"
(NMOS)
humidity
bias
V~c=S'i~
CMOS
.. Estimated failure rate with confidence level 60%.
20
I/hr
l/hl"
1.2SxI0·' 100
• Table 6 Results on MOS Memory Reliability Tests (2)
Test
condition
HN462S32/HN462732 (Cerdip)
com Fail·
Failure
Sam· Total
ponent
pies
ures
rate*
hours
_HITACHI
l/hr
2.19xlO·'
Remarks
*, Oxide
failure x 6
*' Oxide
failure xl
Electrostatic
ti~:xxll
4.6x 10"
••
4.0xlO'"
Aluminium
corrosion x 17
Unknown x 2
*, Aluminium
corrosion x 3
Unknown x 1
- - - - - - - - - - - - - - - - - - - - - - - - - - R e l i a b l l i t y of Hitachi IC Memories
• Table 7 Results on MOS Memory Reliability Tests (3)
Test item
Tem'perature
cyclfitg
Tem'perature
cyclmg
Tem'perature
cycbng
(~::~~~
Test condition
-~S"'C- RT-1SO"C
10 cycles
0
260
0
SO
0
-
-
-
-
-
310
0
7892
0
2080
0
0
100
0
SO
0
600
0
-
164
1000 cycles
!!~61l6t'
HM6147P
FailSampies
ures
HM4716AP
FailSampies
ures
1208
1 !!ycles
l~U-C
EPR9,M
(Cerdiii"l
FailSampies
ures
Failures
-~SoC-RT-1SO"C
-55:(.;_ -
~M4~~t
Cerdi
FailSampies
ures
Sampies
-
-
72
0
190
0
-
0
197
22
0
0
138
128
0
0
60
60
0
0
38
0
38
0
-
-
-
0
38
0
38
0
-
-
-
0
38
0
38
0
-
-
-
-
Thermal shock
i~S;~i;s ISO"C
22
0
60
Thermal shoC;k
Soldering heat
J\1.echanical
shock
Variable
frequency
g:C - 10lrC
15 cycles
261r C 10 seconds
.-
-
-
-
22
0
22
1,5000,0.Sms
22
0
20- 2,000Hz, 200
22
~gc~~~~:ion
20,0000
22
0
-
tics. Bipolar access time test data is given in Fig. 1.
Dynamic operation test data on 64K DRAM is shown
in Fig. 2 and 3.
2.3 Reliability of IC memory electrical characteristics
Internal elements of Ie memory device types are
designed to assure stability of electrical characteris-
Fig. 1 ElC8mple of Change in Blpol.r Memory Char•••rlltl..
Example
Example of time change in access time for Bipoliu: memory
Device name
HM10410
Test condition
Ta=12SoC, VEE=-S.2V
Failure criteria
tAA =2Sns
Failure mechanism
Surface degradation
Measuring Condition
35
-
Results:
Access time (tAA> is stabilized and is within the failure
criteria.
~
Maximum
Average
Minimum
Marching Pattern
30
I I I I
25
.:l
20
15
1,000
500
Time (hr)
0
6
I
2,000
HM4864-3 N=50pc'
_ _ _ _ _ _ _ _ _ _ _ _".,.:SpeeifiCilioo
-!+---I---- .....-. Y
Axis of Oscilloscope
From Comparator Circuit
X Axis of Oscilloscope
(bl VBB= -O.IV X Address
Fig. 5 Example of Dependency of Fail Bit Map on VBB
Fig. 3 Fail Bit Map Displav Circuit
The output of the H074161 is input to the 01 A converter, and the output of 01 A converter is connected
to the oscilloscope to display A X-V matrix. The output
ofthe comparator circuit is connected to the Z axis and
performs luminous intensity modulation. In this way,
the bit map can be displayed on the CRT.
Fig. 5 shows an example ot a voltage margin check. By
changing Vee, the increase and decrease of failed bits
can be seen. The complicated operation of the
memory can be seen dynamically by CRT display,
rather than by pulse waveform observed with an ordi-
36
eHITACHI
X Address
Fig. 6 Example of 1 bit solid fail
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - O u t l i n e of Testing Method
nary oscilloscope. The bit map as shown in Fig. 5 is
extremely useful in observing Ie memory operation.
4. Failure Mode
70-90% of failure at user end is called a solid
failure-a mode which has no relation to access time,
voltage margin and timing. In this failure mode, the
memory is not capable of reading from or writing to
certain specified bits, which are fixed at "0" or "1 ". An
example of single bit solid failure is shown in Fig. 6.
The convenient tester previously described can detect
such failures. Except for special cases, it is rarely
necessary to perform high-precision measurements
such as those made by Ie memory manufacturers.
Full inspection of Ie memories under adverse conditions, performed by Hitachi, guarantees voltage and
timing conditions listed in the data sheet.
An extremely accurate memory tester is required for
performing high-precision inspection with 1ns accuracy. Hitachi is developing testers to supply newer
high-efficiency memories with excellent characteristics and quality.
_HITACHI
37
• APPLICATION OF DYNAMIC RAMS
1. Power On
OReadeye!e
Write cycle __ _
When power is applied to a semiconductor memory.
power-on current varies with Vee and clock conditions. as shown in Fig. 1.lfthe rise time of Vee is in the
10ps range. the RAM does not operate dynamically.
causing a surge of Icc current. This Icc current surge
may be avoided by insuring that Vee rise time is longer
than 1oo1lS.
I
~ 10
I
I
I
I
"R~~.c~s_lv~s
I
I
I
f'....
V
o
10
I
20
30
40
Vee Rise Time=lOJ.ls
Time (tis)
Fig. 1
50
----,
Din
00111
====~
-<====
o 1fAS only
~l o
I
I
--t-- ~. ~2v"
5
refresh eyel"
WE
I
DOli!
-'\
r "\,'
\
t
---0--0--
Add""
::x&X=====
0",,1
10. =~V"
I
~
o
Addres5~
100 200 300
400 500
Vee Rise Time=100tls
Time (tis)
(1) Read-Cycle:
First decide the X address of the memory cell
chosen. and start with trailing of RAS. When theX
address is held by the internal circuitry. change to
Y address. Then trail CAS to take in the Y address.
If the WE pin is at high. the output will appear on
the Dout pin.
(2) Write Cycle:
The input at Din is written in the memory cell
when WE turns to low before CAS.
(3) Read/Modify/Write Cycle:
During this cycle. CAS and WE are trailed down to
low. so that data is read out from. and written in.
the same address in the same memory cycle.
(4) Page Mode Cycle:
In this cycle. CAS is cyclically moved after taking in
the X address through RAS. to scan only the Y
address. This permits reading out and writing in
only one column of data at high speed.
$
Fig.2
Operating modes of Dynamic RAMs
2. Data Output
Relationship between standard value
of Icc and V cc during power- up
2. Operation Modes (See Fig. 2)
38
'1..._____
m
m~
I
5
I
AS. :;xs~ Vee
RAS
m ,'--_ _ _ __
0
15
OHead modify write cycle
Dout is a TIL-compatible. three-state output with two
TIL-load fan out. The output is controlled by the CAS
signals. In the early write cycle. the output reaches
high impedance to permit use as a common I/O
terminal.
3. Refresh Cycle
Refresh is a process of periodical rewriting to offset
the leakage of charge in the cell. and is implemented
in the RAS only refresh cycle. and ordinary read cycle.
Whether 16K- or 64K-bit. all bits can be refreshed by
giving a 128-cycle scanning to only the X addresses
between AO and A6. Each cycle refreshes 128 bits for
the 16K-bit DRAM. and 512 bits for the 64K-bit RAM.
The RAS only refresh cycle permits a power-efficient
refresh that calls for approximately 75% of current
consumed by the read cycle. With CAS fixed at high.
the output reaches high impedance.
The HM4816A has a special function called hidden
refresh which allows holding the output by turning
CAS to low during RAS only refresh.
There are two methods of refreshing:
(1) Concentrated-giving a 128-cycle refresh after
HITACHI
- - - - - - - - - - - - - - - - - - - - - - - - - - - - Application of Dynamic RAMs
operating the memory for a period of 2ms
maximum.
(2) Deconcentrated-which repeats a refresh cycle
every 16ps, following the initial16p memory operation (=2ms/128).
4. Operating Current in Dynamic RAMs
Fig. 3 shows the waveforms of current applied in
various operating modes for HM4864. The mean
operating current in each mode equals the value
obtained by dividing the integrated result of each
waveform by the cycle time. The first peak in each
mode appears during memory access. On the other
hand, the peak during standby appears due to the
precharging operation in each circuit.
mICAS Cycle
Lon. RAS/CAS Cycle
'R'AS
Only Cycle
Page Mode Cycle
'WI~~~~~~~~~~~~~~~~~~~
] I:
~
5. Noise
Noise can be classified into power source noise, and
input signal noise. The power source noise can be
further classified as low- or high-frequency noise as
shown in Fig. 5. To assure stable memory operation,
peak-to-peak power supply voltage, in the presence of
low- or high-frequency noise, should be held below
10% of standard level. To prevent power source noise,
we recommend a condenser of 0.1 pF for each one or
two devices.
Input signal noise can be classified overshoot or
undershoot. Overshoot should be held below the
highest input level specified. To prevent inputundershoot-induced parasitic transistor effects, a -5V
Vee is used (three supply designs) or a built-in VBB bias
circuit is included on chip.
DeSign should provide that the input undershoot does
not exceed the minimum specified for VIL. Overshoot
and undershoot in DRAMS can be reduced by
inserting a damping resistance of several tens of
ohm_s_._______________________
60
40
20
o Note:
High-frequency noise:
Not more than 10% of standard
power supply voltage.
Vcr=5.0V. To=20'C
--t
1--50no$
Fig.3
Power supply Yoltage (HM4864)
DRAMs show different current peaks, depending
upon RAS and CAS timing. The largest peak appears
when both X and Y operate simultaneously. The maximum current peak for HM4864 is approximately
100mA. Current consumed during standby IS expressed as a function of cycle time dependency in Fig.
4. During standby, with a once-in-every16psrefresh,
HM4864 consumes approximately 3mA current.
"'
E
20
0
o
I~
supply voltage.
Total of low-and high-frequency'
Not more than +10% of standard power
supply voltage.
Fig.5 Power source noise
40
30
G
~i~1
Low-frequency noise:
Not more than 10% of standard power
0
1\
\
'\
I....... r-
200n 500n l.u 2#
5# lOp
20p
Cycle Time (tHel
Fig.4 Cycle time dependence of RAS only
refresh current (HM4864)
_HITACHI
39
• PROGRAMMING & ERASING OF PROMS
1. PROGRAMMING AND
ERASING EPROMs
Logic ~l ~
Logic "O~
IDS
1.1 Programming
Information is programmed into the memory cell of an
EPROM by applying a high voltage to its drain and gate
(Fig. 1 and 2). High voltage at the drain increases the
energy of the electrons in the channel area. which
become "hot electrons" capable of jumping across the
oxide film. Pulled by high voltage at the gate. the hot
electrons are admitted into the floating gate. The
charge entering the floating gate changes the threshold voltage in the memory element. thereby storing
new information.
VDS
V.S
Readout Vos
Flg.3 Re,dlnll out stored Information
K
L
,,, .'"
~
i
When reading out. voltage is applied as in Fig. 3. and
"1" and "0" are identified by checking whether or not
current flows. Since the drain voltage for read-out is
set at 3V. no erroneous writing takes place.
1/
.,
I
~
,,~
[>-'
Write :
JV
Read:
-'"
~'c:c=5\".
~"1'=5\'
rl'I'=2S\"
I
5
When shipped. all EPROM bits are held at logic "1"
with all charge released (no programmed data). In
changing "1" to "0" by applying the specified waveform and voltage. data is programmed. The higher the
Vpp voltage. and the longer the program pulse width
tpW. the greater the quantity of electrons programmed
in. as shown in Fig. 4.
'I
,to
3
.m
2"
1"
Program Pulse Width tp., (ms)
/1
If Vpp exceeds the rated value. as in overshoot. the
memory's p-njunction may yield to permanent breakdown. To avoid this. checkVpp overshoot of the PROM
programmer. Also check negative-voltage-induced
noise at other terminals. which can create a parasitia
transistor effect and reduce apparent yield.
K
1n
Write: Vcc=5V
I. Iv
'"
I ,'j
t;.-~.
V
Read:
r,.,,=S\'
Drain
Fig. 1 Memory transistor
circuit symbols
20
22
24
26
28
Program V pp (V)
Fig. 2 Cross section of
memory transistor
40
'j
./
I
'\ II
Gate
Source
./
I
Flg.4 Typical Programming Characteristics
of EPROMs.
_HITACHI
- - - - - - - - - - - - - - - - - - - - - - - - - - - Programming & Erasing of PROMs
1.2 Erasing
Hitachi's EPROMs are usually capable of being
written and erased more than 100 times. Data stored
in the EPROM is erased by exposing the chip to ultraviolet light. which releases the electric charge from
the floating gate. Electrons in the floating gate receive
ultraviolet energy. become hot electrons again and
jump into the control gate or substrate. This process
erases the stored data.
Wavelength and minimum exposure of ultraviolet
light are specified as 2.537A. and 15W sec/cm2
respectively. Erasure occurs by exposing a device to
an ultraviolet lamp of 12.ooopW/cm2 at a distance of
1.2 - 3cm for approximately 20 minutes. The ultraviolet light transmission rate of the transparent lid is
about 70%. Contamination or foreign material on the
surface-which lowers transmission and prolongs
erase time-should be eliminated by the use of
alcohol or other solvent that will not damage the
package. Fig. 5 shows typical EPROM erasure
characteristics.
1.3 Data Retention
A.s a result of writing in. <,poroximately 0.5 to 2.0 x
10"3 coulomb of electrons are accumulated at the
floating gate. With the elapse of time. these electrons
decrease. which can result in inversion of stored data.
The mechanisms of electron dissipation are explained
as follows:
(1) Data Dissipation by Heat
The accumulation of electrons at the floating gate
is an unbalanced state. so the dissipation of thermally excited electrons is unavoidable. Data
holding time is closely related to temperature. Fig.
6 shows typical data retention characteristics.
(2) Data Dissipation by Ultraviolet Light
Ultraviolet rays at a wavelength of not greater
than 3.000- 4.oooAwili release the charge stored
in EPROMs. Prolonged exposure to fluorescent
light and sunlight. which contain some ultraviolet
rays. can cause data corruption. Fig. 7 shows
examples of data retention time using ultraviolet.
sunlight. and fluorescent light sources.
10
·
·
9
I,...,
10
L....
J§ ~
~
I~ ~
7t:: E8
5
AJO'
..
f--
-
- ALL(- f-I
\ §§§
~ §§
\§ ~ V
~
4
,/
10
300
~ ~ ~~
200
150
100
Storage Temperature (t)
Flg.6
Typical Data Retention Characteristics
106
- -
UV-Irr&hation
Flg.5
/
·,
10
/M1st Hard-to-Erase Bit
1'Ai:i:'~'\ §§ ~ ~
~~
V
10
I./Most Ersy-tr,Erase Bit
§§ ~ ,./
6
J
V
,
~~
(W'sec/cm2 )
40W Fluorescent Lamp
I~~
10'
Typical Erasing Characteristics
Ultraviolet Eraser
at 2,357A,6mW/cm 2
Fig.7
•
HITACHI
EPROM's data retention time
41
Programming" Erasing of P R O M s - - - - - - - - - - - - - - - - - - - - - - - - - -
9,
(3) Data dissipation by voltage'
This type of dissipation occurs while information is
being written in. High voltage at other memory
cells lying on the same word or data line as the cell
being programmed, can cause dissipation of
stored electric charge. Such defects are eliminated by inspection atthe factory. The programing
voltage and pulse width should always be kept
within specified limits.
1.4 EPROM Programmer
An EPROM Programmer stores program data from a
source in its internal RAM. and writes the program
data into an EPROM. A minimum of 3 functions are
necessary to accomplish this: the Blank check function prior to programming. the Programming function,
and the Verify function. As shown in the drawing.
programmers also are provided with a reverse insertion checking function. or pin contact checking function, prior to the Blank Check. The diagram is outlined
as follows:
(a) Pin contact check
Checking is performed by detecting the forward
current of each EPROM pin. This forward biased
resistance differs between product manufacturers.
(b) Reverse insertion check
This check detects reverse insertion of the device,
places the equipment in reset mode, and protects
the device and equipment.
(c) Blank Check
This function is performed prior to programming
to determine whether the EPROM is erased, or to
prevent EPROM reprogramming. With output data
in the erased condition at "1" (high). check
whether or not data inthe EPROM isalsoat"1." It
will failstop, if any "0" is detected. Normally, a
lamp or buzzer provides warning.
(d) Programming
Normal programming flow is shown below. An
EPROM data word will be read out prior to programming, and compared with programming
data. If they coincide, programming will be
skipped; and if they differ, programming will be
performed. Read out will be again compared with
programming data. and if they coincide, it will
progress to the next address.
42
,/
,/
""
....
....
....
.... ....
( ' Check Pi n Contact "
....
.... ....
,/
.... .... ,
,/
,/
,/
,/
(e) Verify
This function after programming completion,
checks that the programming is correct when
compared with data in the internal RAM of the
programmer. It performs fail-stop when data does
not coincide. lighting the fail lamp, and displaying
the address and data.
eHITACHI
- - - - - - - - - - - - - - - - - - - - - - - - - - - - P r o g r a m m l n g & Erasing of PROMs
(f) How to input the program
The following methods are given to input program
data to the internal RAM of the programmer.
Paper tape input and teletypewriter input are usually options.
Method
Copy input
Manual input
Content
Input by copying the master ROM.
Input by the keyswitch of the fron t
panel Used for correction or
revision of program
Paper tape input
Read the paper tape furnished
from the host system with the
tape reader
Teletypewriter
input
Input with the teletypewriter.
Preparation, correction and list
preparation of the program can be
made.
1.5 Handling EPROMs
Contact with a charged human body. plastics. or dry
cloth causes the glass window of an EPROM to generate static electricity which could cause device malfunction. Typical malfunctions are faulty blanking and
write margin setting. which give the impression that
information has been correctly written in. This malfunction is due to prolonged retention of electric
charge on the glass window. resulting from the static
electricity. It can be eliminated by neutralizing the
charges through short exposure to ultraviolet rays-a
procedure recommended before reprogramming. as it
also reduces charges in the floating gate. To prevent
charging of the window. use the following methods:
1.6 Shielding Labels
When using EPROMs in environments where ultraviolet exposure can occur. put a shield label over the
glass window to absorb ultraviolet light. Specially prepared labels are marketed. and metal-loaded types are
particularly effective. Few shielding labels meet all
environmental requirements established for EPROMs.
A suitable label must be chosen for each application
by considering the following label characteristics:
(1) Adhesive Strength
Avoid repeated attaching and dusting which may
reduce adhesive strength. Ultraviolet erasure and
reprogramming are recommended after stripping
off an attached label. If labels must be changed.
attach the new label over the old. since peeling
may develop a static charge.
(2) Temperature Range
Use a shielding label in an environment where
temperature falls within the specified allowable
range. Beyond this range. label paste may harden.
or remain on the window glass even after the label
is removed.
(3) Humidity Range
Use a shielding label where humidity does not
exceed the specified allowable range.
(1) Use a grounding system for the operator handling
EPROMs. and avoid use of gloves that may
develop a static charge.
(2) Refrain from rubbing the glass window with plastics and other substances that may develop a
charge.
(3) Avoid use of coolant sprays which contain ions.
(4) Use shielding labels with conductive substances
that can evenly distribute the established charge .
•
HITACHI
43
Programming
a
Erasing of P R O M s - - - - - - - - - - - - - - - - -_ _ _ _ _ _ __
2. PROGRAMMING BIPOLAR PROMS
2.1 Programming System
Bipolar PROM storage systems are classified as blown
diode type. and fuse type. In the blown diode system.
the Emitter-Base junction is short-circuited by A1.
which has penetrated into the Base because of a
current pulse applied to the E-B junction (Fig. 6).
Hitachi devices use the blown diode system. which is
considered to be more reliable.
Bit Line
Word Line
Fig.' Blown diodesyst_
In the fuse system (Fig. 5). the metal fuse is burned off
by current. and a grow back phenomenon. or migration and recombination of the metal. can occur.
C
. . . __S_T..,..AR_T_ _ _)
Open in
Programming
Bit Line
'.-
"...
I
Word Line
2.2 Programming Method
Programming is executed with conventional equipment (PROM writer). using a personality board suited
to the product.
"...1,
.....
"..."'" System Check ..... .....
check pin contact etc.) .......
<. . .(
" ,
"...'" "...""
Apply Program Pulse
A Blank check is first performed. Next write the
pattern you want to program. bit by bit. At every application of current pulse. confirm program by sensing
the output level. This process should be performed for
all bits into which you want to write. When programming is completed. Verify is performed.
At Blank Check. Sense and Verify. high OutpUt pin
level (non-programmed). or low level (programmed) is
checked by the sense current (Is). Vs -Is characteristics for normal series and S series is shown in Fig. 8
and 9. respectively. Specified value of Is for both series
is 20mA. and voltage reference level is 7.5V.
Fig. 10 and 11 show the relationship between program current and program pulse number for 1 bit to be
written. Program current is specified at 130mA in
normal series. and at 90mA in S series.
FIg.7 Progremming FI_ of PROM
- - - - - - - - - - - - - - - - - - - - - - - - - - P r o g r a m m i n g & Erasing of PROMs
12
>
~10
~
!
'0
>.,
---~===l
Decocler
_GND
Memory Matrix
64X64
o---~===l
A.o----t:;~=t_.J
A.
(OP-III
.PlN ARRANGEMENT
.ABSOLUTE MAXIMUM RATINGS
Symbol
Itein
Terminal Voltage-
VT
Power Dissipation
PT
Operating Temperature
Storage Temperature (Plastic)
Storage Temperature (Cerdip)
Storage Temperature··
T...
T.t •
• with respect to GND.
•• Under Bias •
.6.
T."
T.,.<6,u)
Value
-O.s.>to +7.0
1.0
o to +70
-55 to +125
-65 to +150
Unit
V
W
·C
·C
(Top View)
'c
'c
-10 to +85
-1. OV (Pulse Width S SOn8)
• TRUTH TABLE
CS
H
L
L
58
WE
X
H
L
Vee Current
Mode
Not Selected
Read
Write
Iss,
lee
Icc
$
lUI
HITACHI
I/O Pin
High Z
Dout
Din
Reference Cycle
Read Cycle
Write Cycle
---------------------------------------HM6148,HM6148-6,HM6148P,HM6148P-6
.RECOMt.t:NDED DC OPERATING CONDITIONS (Ta-O to +70'C)
Symbol
Item
Supply Voltage
GND
\.'I.
Input Voltage
typ
max
Unit
4.5
5.0
5.5
V
0
0
0
V
2.4
-0.3·
3.5
6.0
V
-
0.8
V
min
Vee
V'L
• V,L mln--1.0V(Plilse wldth$SOna)
.DC AND OPERATING CHARACTERISTICS (Vcc -5V±lO%, GND-OV, Ta=O to +10'C)
Item
Symbol
Test Condition
Vee-5.5V, V;.-GND to Vee
Input Leakage Current
IILlI
Output Leakage Current
Ihol
lee
CS-\.'IL, I,/O-OmA
Operating Power Supply Current
Average Operating Current
Standby Power Supply Current
Output Voltage
Notes)
leci
CS- \.'IL, Minimum Cycle, Duty-l00%, I"o=OmA
Cycle-150ns, Duty =50%, I"o-OmA
Is.
CS-\.'IH
CS;;: Vee-0.2V, V..;;;0.2V or
VOL
VOH
* Typical hmlts are at
** 'Reference only.
typO
max
-
-
2.0
-
-
2.0
JAA
35
80
mA
-
40
80
mA
35
-
mA
-
5
12
mA
-
20
800
JAA
-
0.4
V
-
V
CS-\.'I., V"o-GND to Vee
leez··
Issl
min
V..~ Vee-0.2V
I OL-8mA
1o.--3.2mA
2.4
Unit
JAA •
Vcc-S.OV. To-2S"C and specified loaclina.
• CAPACITANCE (Ta-25'C, f-lMHz)
min
max
Unit
Input Capacitance
Symbol
C..
V.. -OV
-
5
pF
Input/Output Capacitance
C,/O
\.'I,o-OV
-
12
pF
Item
Test Condition
Note) ThiS parameter is sampled and not 100% tested•
• AC CHARACTERISTICS (Vcc=5V±lO%, Ta=O to +10'C, unless otherwise noted)
eAC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
'nput Rise and Fall Times. . . . . . . . . • . . . . . . . . . . . . . . ..
Input and Output Timing Reference Levels······· .. .. ..
Output Load .•. '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Load Circuit (A)
GND to 3.0V
IOns
1.5V
See Figure 1
~cc
SIOII
SlOQ
0...
• ineludes probe and
jil capacitance
U~to-----~----~
33011
:q
Load Circuit (8)
v«
,330Q
3OpF*
S.F
Fig. 1
.READ CYCLE
Parameter
Read Cycle Time
Symbol
Address Access Time
IBe
t ..
Chip Select Access Time
tACS
HM6148/P-6
HM6148/P
min
max
Unit
max
min
70
-
85
-
n.
-
70
70
-
85
85
ns
ns
Output Hold from Address Change
to.
5
ILz
10
-
10
-
ns
Chip Selection to Output in Low Z·
Chip Deselection to Output in High Z·
1Hz
0
40
0
40
ns
Chip Selection to Power Up Time
tpv
0
-
0
-
ns
Chip Deseleelion to Power Down Time
I'D
40
ns
-
40
5
-
ns
• Translhon IS measured ±50lhnV from hl,h uJlpedanc:e volt. With Load B. This parameter IS sampled and not 100% tested.
_HITACHI
59
HM6148, HM6148-6, HM6148P, H M 6 1 4 8 P - 6 - - - - - - - - - - - - - - - - - - _TIMING WAVEFORM OF READ CYCLE NO.1
Addre8S
Data out
(1)(2)
=*t-----~_.
_,oc-=~_
previous
Data valid
data valkl.
-TIMING WAVEFORM OF READ CYCLE NO.2")(')
Data valid
Data out
Vee supply
current
NOTES) 1. "WE" is high for Read Cycle.
2. Device is continuously selected,~= Va
3. Address Valid prior to or coincident with t:S' transition low .
• WRITE CYCLE
Parameter
HM6148/P
Symbol
min
HM6148/P-6
max
min
Write Cycle Time
Iwe
70
Chip Selection to End of Write
lew
50
-
60
Address Valid to End of Write
I.w
65
-
80
Addres. Setup Time
I. .
15
tWPl
50
Iwl'l
'65
Write Pulse Width·
Write Recovery Time
60
-
-
35
0
45
low
0
-
0
-
* When the CS low transition occurs simultaneou.ly with the WE low transition or after the WE transition. 110 pina remain in a hip
*.
slate. In this case '''1'1. in the other case lwp. (-'.,.+IDW).
Transition is measured ±6QOm:V from hiBh impedance voltqe with Load B. This plrameter is .ampled and not 100% tested.
•
HITACHI
ns
DS
0
Output Active from End of Write··
ns
ns
Iwz
Write Enabled to Output iD High Z..
ns.
DS
5
30
I ••
ns
5
35
I.w
Data Hold Time
ns
-
5
Data Valid to End of Write
Unit
80
-
5
60
-
15
-
-
Iwo
Notes)
-
85
max
DS
DS
DS
impedance
---------------------------------------HM6148,HM6148·6,HM6148P,HM6148P.6
-TIMING WAVEFORM OF WRITE CYClE NO.1(WE CONTROLLED)
-
(I)
/Wc
Addrels_
IT
I~
~----------~w'----------1,~~~-r~~~~
~N
/ /// ///
J.--'-,·-..",----'Ii2'I---I!-----....!!!."""L......-...!!.
___..:..I-.....".;.:..--!-.d.......
.-. r:~_tDw- ID~ I ~
)lex
..2Y'f-twz
««««
J
~IOW~
171
HlshImpedanee
~
-TIMING WAVEFORM OF WRITE CYClE NO.2(CS CONTROLLED)'!)
-
-
Iwc
Address - - /
I,w
!---tAS
Icw
-
..,·1'1-
tll'l'l·[~l_
/7// ///
"""""""
XXXX
~DW
XX
1'1
XXxx
10.
YX
X
)()(
High Impedance
Dout
Notes)
1. CS and WIT are paced in the WRITE state during low level period
(tw)·
2. A write occurs during the overlap of a low CS and a low "WE: (twp)
3. t WR is measured from the earlier of CS or WE" going high to the end
of write cycle.
4. During this period, I/O pins are in the output state so that the input
signals of opposite phase to the outputs must not be applied.
5. If the CS" low transition occurs simultaneously with the "WE low
transition or after the WE transition, the output buffers remain in a
high impedance state.
6. IfCS"is low during this period,'1/O pins are in the output state.
Then the data input signals of opposite phase to the outputs must
not be applied to them.
7. Dout is the same phase of write data of this write cycle .
•
HITACHI
61
HM6148, HM6148-6, HM6148P, HM6148P-6--~:----------------ACCESS TIME
VB.
ACCESS TIME VI. Ta
Vee
1.2
1.2
Vcc-sv
TIl=2S-c
~
I
;::
L
1
1
1.0
~
-..............
9
4.75
5.25
5.0
V
V
~
9
0.8
0.8
4.5
/"
(}
5.5
o
.0
20
60
.,o\mbiPhl Temper.lurt'
Supply Voltage Vce tV)
Ta
80
,'C,
SUPPLY CURRENT VB. Vee
SUPPLY CURRENT VI. Vee
8
0
TII-25"(
r.=25"e
6
0
~
V-
~
~
...,...,.~
2
0
10
'.5
~
•
5.0
'.75
5.25
5.5
'.5
'.75
~
5.0
5.25
Supply \'oltagp ft"{,
Supply Voltagt' Vee (V,
SUPPLY CURRENT
SUPPLY CURRENT VI. Ta
VB.
5.5
~\,\
Ta
(}
~'cc=5V
Vcc=5V
-~ .'
.
j
0
6
.::
o
t:-------..
t-
-t---
t--- t----
t-
t---I -
O
0
20
'0
0
60
80
Ambient Temperature To ("e)
62
20
.u
Ambient Tpmperalure
_HITACHI
60
Til
!l:)
00
---------------------------------------HM6148.HM6148-6.HM6148P.HM6148P-6
SUPPLY CURRENT vs. Vee
(STANDBY)
SUPPLY CURRENT vs. Ta
(STANDBY)
0
0
To=25'C
/
Vcc=5V
5
5
V"
./
0
/
o. 5
/
0
/"
/
~ o. 5
,I
o
>.
/
J
o. I
o. I
3.0
5.0
Supply Voltage
6.0
20
.0
60
80
Ambient Temperature Ta (OC)
V('C (V)
eHITACHI
63
HM6148LP, HM6148LP-6
1024·wordX4-blt High Speed Static CMOS RAM
.FEATURES
• Single 5V Supply
• Fast Access Time •.•.•.....•.• HM6148LP 70 ns (max.)
HM6148LP-6 85 ns (max.)
• Low Power Standby and Low Power Operation;
Standby: 5J,IW(typ)
Operation: 200mW (typ)
• Completely Static RAM; No Clock or Timing Strobe Required
• No Peak Power-On Current
• No Change of t ACS with Short Deselected Time
• Equal Access and Cycle Times
• Directly TTL Compatible; All Inputs and Outputs
• Three State Output
• Common Data Input and Output
• Capability of Battery Back Up Operation
• Pin-Out Compatible with Intel 2148
(DP-18)
.PlN ARRANGEMENT
.BLOCK DIAGRAM
A.~.---t:~==1
A.~---C~=~
A,~-:..--C~==I
- - 0 Vee
Row
l)ecucier
---0
Memor" Matrix
GNiJ
64)(.04
A.o---~==t
.A.o---~==t_-.J
(Top View)
.ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Unit
Terminal Voltalle'
VT
-0.5.to +1.0
V
Power Di.sipation
PT
1.0
W
Operating Temperature
T."
o to
+10
Storage Temperature
T.,.
-55 to +125
·c
·c
-10 to +85
·C
Storage Temperature··
• with , ...... to GND.
•• Under Bias
64
T. .. t ••• .,
'" -1.OV (Pulse Width" 50 .. )
•
HITACHI
---------------------------------------------------HM6148LP,HM6148LP·6
.TRUTH TABLE
CS
WE
Mode
H
X
Not Selected
L
H
Read
L
L
Write
Vee Current
Iss,
Reference Cycle
I/O Pin
High Z
ISBJ
Icc
Icc
Dout
Read Cycle
Din
Write Cycle
.RECOMMENDED DC OPERATING CONDITIONS (Ta=O to +70·C)
Item
max
Unit
5.0
5.5
V
0
0
0
V
V,H
2.4
3.5
6.0
V
V,L
-0.3"
-
0.8
V
min
Vee
Supply Voltage
GND
Input Voltage
• v" min--1.0V(Pulse
typ
4.5
Symbol
widch~50ns)
.DC AND OPERATING CHARACTERISTICS (Vcc =5V±lO%. GND=OV, Ta=O to +70·C)
Symbol
Item
Input Leakage Current
Output Leakage Current
Operating Power Supply Current
Average Operating Current
Standby Power Supply Current
Output Voltage
Notes)
* Typical limits are at
** Ref(lrence only,
Test Condition
liL.1
I lLU I
CS- V,H. V, o-GND to Vee
Vce -5.5V.
\r.~=GND
min
typ·
max
-
-
2.0
pA
-
2.0
pA
35
80
rnA
40
80
rnA
to Vee
Unit
Icc
CS- V,L, ho-OmA
IcCi
CS- V,L. Minimum Cycle. Duty-l00%>. I,,,,-OmA
-
Ic:C2 ••
Cycle -150ns. Duty-50%. I"o-OmA
-
35
-
rnA
Is.
CS- V,H
5
12
rnA
Iss I
CS;;: Vee-0.2V, V..:i>0.2V or
1
100
pA
VOL
I",.-8mA
-
-
0.4
V
VOH
Inu- -3.2mA
2.4
-
-
V
v..;;: Vce-0.2V
Vec-5.0\', Ta-2S'C and specifiHl loading.
.CAPACITANCE (Ta=25·C. /=lMHz)
Symbol
min
max
Unit
Input Capacitance
Item
C..
v..=OV
-
5
pF
Input/Output Capacitance
C,~
v"o-OV
-
12
pF
~otf')
This parameter is sampled and
nt)t
100%
Test Condition
tpsted •
• AC CHARACTERISTICS (Vcc -5V±lO%. Ta=O to +70·C. unless otherwise noted)
eAC TEST CONDITIONS
Input Pulse l.evels ................................. GND to 3.0V
Input Rise and Fall Times ........................... 10ns
Input and Output Timing Reference Levels .....•. , ...... 1.SV
Output Load .•...•..•..•.............•........... See Figure
:q
Load Circuit (8)
Load Circuit (A)
II<,
Vee
SlUll
[),
0 .... o---~--4
..
Sloa
330a
330Q
S.F
• includes probe and
jil capacitance.
eH1TACHI
65
HM6148LP,HM6148LP·6--------------------------------------------------READ CYCLE
Read Cycle Time
Address Aceess Time
Chip Select Access Time
Output Hold from Address Change
Chip Selection to Output in Low Zo
Chip Deselection to Output in High zo
Chip Selection to Power Up Time
Chip Deselection to Power Down Time
HM6148LP-6
max
HM6148LP
Symbol
Parameter
min
max
min
I ftC
70
-
85
-
I"
-
70
70
-
85
85
tACS
Ipu
5
10
0
0
IPD
-
10.
ILz
I.z
-
-
-
5
10
0
0
-
40
-
40
-
-
40
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
• Transition is measured ±500mV from hiBh impedance voltage with Load B. This parameter is sampled and not 100% tested.
-TIMING WAVEFORM OF READ CYCLE NO.1
(1)(2)
v=
I-----------..c--------~'"i
Address
=t-toH--'-AA:::::'~'-1
-----
previous
Data out
---
Oata valid
data vafid
_TIMING WAVEFORM OF READ CYCLE NO.2'"<3l
Data valid
Data out
Vee supply
current
NOTES) 1. "WI! is high for Read Cycle••
2. Device is continuously selected,<::s" = VIL
3. Address Valid prior to or coincident with ~ transition low.
-WRITE CYCLE
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Symbol.
Iwe
lew
lAW
lAS
tWl"
O
Write Recovery Time
Data Valid to End of Write
Data Hold Time
Write Enabled to Output in High Z..
Output Active from End of Write"
IwPl
Iw.
IDW
ID'
Iwz
low
min
HM6148LP
. max
70
50
65
15
50
65
5
30
5
0
0
-
-
-
35
-
HM6148LP-6
max
min
85
60
80
15
60
80
5
35
-
-
5
-
0
0
45
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes} • When the CS low transit.ion occurs simultaneously with the WE low transition or after the WE transition. 1/0 pins remain in a high impedance
atate. In this ease '''PI. in the other ca.e t",.1 (-tlfz+IDIf) .
Transition is measured ±SOOmV from high impedance voltage with Load 8. This parameoter i. iampled and not 100% tested.
•*
66
_HITACHI
---------------------------------------------------HM6148LP,HM6148LP·6
eTIMING WAVEFORM OF WRITE CYCLE NO.1(WE CONTROLLED)'l)
I.,
'1'-________________-"li'-_ _
Addreu _ _
1------tc·'-----t~~"7'"7'"...._r'7""7
I ••
0 ..
twz(t]
00 ..
eTIMING WAVEFORM OF WRITE CYCLE NO.2(CS CONTROLLED)")
--
/w,
A,ddreu
-
I ••
,.
~tAS
cs
_tw"l!l....'''P\-(Z}_
'\.'\.'\.'\.'\.'\.'\.
////
•
~DIV
XXXXXXXXXXXJI\.
)l(XXX
I
(s)
///
I ..
xxx
Hllh Impedance
Notes)
1. "CS and WE" are paced in the WRITE state during low level period
(tW)·
2. A write occurs during the overlap of a low (;S" and a low WE: (twp)
3. tWR is measured from the earlier of ~ or
going high to the end
of write cycle.
4. During this period, I/O pins are in the output state so that the input
signals of opposite phase to the outputs must not be applied.
S. If the 3 low transition occurs simultaneously with the -wE low
transition, the output buffers remain in a
transition or after the
high impedance state.
6. If 3 is low during this period, 1/0 pins are in the output state.
Then the data input signals of opposite phase to the outputs must
not be applied to them.
7. Dout is the same phase of write data of this write cycle .
wr
wr
• LOW Vee DATA RETENTION CHARACTERISTICS (Ta-O to +70'C)
Symbol
Parameter
Vee for Data Retention
YD.
Data Retention Current
IccDR.
Chip Deselect to Data Retention Time
tCDR
Operation Recovery Time
I.
*
Test Condition
v..;;: Vcc-0.2V or V..:>0.2V
Vcc=2.0V, cs;;: 1. 8V. V..=1.8V or V..:>0.2V
CS;;: Vcc-O.2V.
See Retention Waveform·
min
typ
2.0
-
Unit
V
40
fAA
0
-
-
ns
he·
-
-
ns
-
max·
hr - Read Cycle Time
e LOW Vee DATA RETENTION WAVEFORM
Data Retention Mode
~,--------~I~----~~==~=-----~,-------4.SY - - - - - - ---
CS;;; Vcc-O.2V
cs----J
OY--- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
•
HITACHI
67
HM6148LP,HM6148LP·6-------------------------------------------------ACCESS TIME VI. Ta
ACCESS TIME VI. V«
1.2
Vcc=5V
r.-25"C
]
I
.1
~
1.0
j
o.9
~
JI'
I .1
V
!
'"'"
I
;:
~
~
j
./
1.
°V
:: o.9
~
0.8
0.8
4.5
4.75
5.0
5.25
5.5
o
40
60
Ambient Temperature Ta rC)
20
Supply Volt. .e Vee (V)
SUPPLY CURRENT VI. V"
SUPPLY CURRENT VI. Vee
0
8
r.=25"e
r.=25"e
0
e
6
30
~
8
1V
~
V
10
4.5
~
4
V-
~
2
0
4.75
5.0
4.7f
5.5
5.0
5.25
5.5
Supply Voltale Vee (V)
SUPPLY CURRENT VI. Ta
SUPPLY CURRENT VI. Ta
8
0
Vcc=5V
Vcc=5V
6
0
r---
-r--
r-- t----
I--
0
68
~
0
5.25
Supply Volta,e Vee (V)
10
80
2
o
--
0
40
60
Ambient Temperature To COC)
20
80
20
40
r-
60
Ambient Temperature Ta (t)
eHITACHI
80
---------------------------------------------------HM6148LP,HM6148LP-6
SUPPLY CURRENT vs. Ta
(STANDBY)
SUPPLY CURRENT vs. Vee
(STANDBY)
0
0
T4=25'C
0
o. 5
o. 1
/
VC'c=5V
5
5
~
V
V
./
/
;: o. 5
~
v
.I
o. I
3.0
/
0
5.0
6.0
V
20
,0
60
80
Ambient Tt>mper&lurt' Ttl ('e,
Supply Voltage V('c (Vl
eHITACHI
69
HM6148H-35, HM6148H-45,
HM6148H-55, HM6148HP-35,
HM6148HP-45, HM6148HP-55
Prelimina ry
1024-word x 4-bit High Speed Static CMOS RAM
• FEATURES
• Fast Access Time ........•.••...... 35/45/55n5 (max)
• Low Power Standby and Low Power Operation;
Standby: 100 IlW (typ.), Operation: 200mW (typ.)
• Single 5V Supply
• Completaly Static RAM: No Clock or Timing Strobe Required
• No Peak Power-On Current
• No Change of tACS with Short Deselected Time
• Equal Access and Cycle Times
• Directly TTL Compatible; All Inputs and Outputs
• Common Data Input and Output; Three-State Outputs
• Pin-Out Compatible with Intel 2148H
HM6148H Series
(DG-lS)
HM6148HP Series
• BLOCK DIAGRAM
Ao 0----1::(=:]"1
A.o----1t::c=:::I
Ao o----1OC=:J Row
- - 0 Vee
Memory Matrix
64x64·
o----{::L=:::t Docodo,
Ao o----{::L=:::t
A.
--.oCND
1/0.0--.......1">---1
110. o--rt+i>--~
(DP-lS)
110.0--.+++11">---1
• PIN ARRANGEMENT
110. o-tltffil>---L_~
.
.ABSOLUTE MAXIMUM RATINGS
Symbol
Item
Terminal Voltage-
VT
Power Dissipation
PT
Operating Temperature
T.,.
Ratings
Unit
-0.5 to +7.0
V
1.0
W
o to
+70
Storage Temperature (Plastic)
T.,.
-55 to +125
Storage Temperature (Ceramic)
T"6
-65 to +150
Storage Temperature··
T" ..
-10 to +85
·C
·c
·c
·c
V" ... --3.5V (Pulse wuth-20ns)
• with respect to GND.
e. under bi••
(Top View)
• TRUTH TABLE
Mode
Vee Current
Reference Cycle
WE
H
X
Not selected
ISSt
L
H
Read
Icc
Dout
Read Cycle 1. 2
L
L
Write
Icc
Din
Write Cycle I, 2
Issl
Note) The specificationa of this device are subject to change !Nithout notice.
Please contact your nearest Hitachi's Sales Dept. regardiD8' specific.tiona.
70
I/O Pin
CS
_HITACHI
High Z
- - - - - - - - - - - - - - - - - - - - H M 6 1 4 8 H - 3 5 , HM6148H-45, HM6148H-55,
HM6148HP-35, HM6148HP-45, HM6148HP-55
• RECOMMENDED DC OPERATING CONDITIONS (Ta=O to +70'C)
Symbol
Item
min
typ
max
4.5
5.0
5.5
V
0
0
0
V
V,.
2.2
-
6.0
V
VIL
-0.5·
-
O.S
V
Vee
Supply Voltage
GND
Input Vol tage
Unit
• -3.0V (Pol.. width 2On.)
.DC AND OPERATING CHARACTERISTICS[1] (Ta=O-70·C. Vcc-5V±IO%.GND=OV)
Symbol
min
typ
max
Unit
Vee-max, V..-GND to Vee
-
}fA
~- VI., VI/~-GND to Vee
2.0
}fA
Operating Power Supply Current
Icc
<::S -
-
-
2.0
Output Leakage Current
IlL. I
IlLol
35
80
mA
Operating Power Supply Current: AC
IccI
min. cycle, ~-V,L,Il/o-OmA
-
50
100
mA
Standby Power Supply Current: DC
Iss
<::S- VI.
-
5
20
mA
Standby Power Supply Current(l): DC
Issl
<::S~Vee-0.2V, VI.;:OO.2V or
-
20
800
}fA
-
0.4
V
-
V
Parameter'
Input Leakage Current
Test Conditions
VI L, 11/ 0 - OmA
VI.s: Vee-0.2V
Output Low Voltage
VOL
IOL-SmA
Output High Voltage
Vo.
Io.--4.0mA
2.4
Notes
(2)
Notes} 1. Typical limits are at Vcc-5.0V. Ta-+2S"C and specified loadina:.
2. l20mA ..... for HM6148HP-35
.CAPACITANCE (Ta=2S·C. j=lMHz)
typ
max
Unit
Input Capacitance
C"
V,,-OV
3
5
pF
Input/Output Capacitance
el/o
VI/O-OV
5
7
pF
Symbol
Item
Test Conditions
Note) This parameter is sampled and not 100 % tested.
• AC CHARACTERISTICS (Vcc-SV±10%, Ta-O to +70'C)
.RISE FALL TIME
min
typ
max
Input Rise Time
I,
-
5
100
ns
Input Fan Time
1/
-
5
100
ns
Symbol
Item
Unit
.AC TEST CONDITIONS
Input pulse levels: GND to 3.0V
Input rise and fall times: 5ns
Input and Output timing reference levels: I. 5V
Output load: See Figure
5\'
lJout-...,..--i
5\'
3L ______
~--"""\,
Dout
255Q
ov
t.
Output Load (A)
Output Load (B)
(for hz. tu. 'wz, toW')
• Including scope &: j
t~-tl-5ns
Input Pulse Waveform
i,.
•
HITACHI
71
H~6148H-35, HM6148H-45, HM6148H-55, - - - - - - - - - - - - - - - - - - - HM6148HP-35, HM6148HP-45, HM6148HP-55
.AC CHARACTERISTICS (Ta=O to 70'C, Vcc =5V±10%, unless otherwise noted.)
eREAD CYCLE
Item
HM6148HP-35
HM6148HP-45
min
max
min
max
HM6148HP-55
Symbol
min
max
Unit
Read Cycle Time
he
35
-
45
-
55
-
ns
Address Access Time
I.A
35
-
55
ns
lACS
-
45
Chip Select Access Time
-
45
-
55
ns
Output Hold from Address Change
ION
5
Chip Selection to Output iii Low Z
lLz·
10
Chip Deselection to Output in High Z
tHZ·
Chip Selection to Power Up Time
Ipu
Chip Deselection to Power Down Time
35
-
10
0
20
0
-
-
IPD
-
5
-
ns
10
-
ns
0
20
0
20
ns
0
-
0
-
ns
30
ns
5
-
30
-
30
* At
Transition is measured ±500mV from high impedance voltage with Load(B). This parameter is sampled and not 100% tested.
any temperature and voltage condition 1HZ max is less than fa min.
eTIMING WAVEFORM ~F READ CYCLE NO.1
."
~
Address
(1)(2)
~
."
'0'
'ON
:tXX
DOllt
Data
r--'--
Valid
eTIMING WAVEFORM OF READ CYCLE NO.2(1)(3)
."
.,.
."
INz
Dala \"Illid
High Impedance
Oout
Vee supply
---- -
Impedance
------Ir-------------------,.+
50%
current
In
Notes) 1. WE is High for Read Cycle.
2. Device is continuously selected. CS- V"..
3. Address Valid prior to or coincident with
72
•
CS transition Low.
HITACHI
- - - - - - - - - - - - - - - - - - - - H M 6 1 4 8 H - 3 5 , HM6148H-45, HM6148H-55,
HM6148HP-35, HM6148HP-45, I1M6148HP-55
• WRITE CYCLE
Item
HM6148H/P-35
HM6148H /P-45
min
max
min
max
HM6148H /P-55
min
max
45
-
55
-
••
40
-
50
-
n.
ns
Unit
Symbol
Write Cycle Time
Iwe
35
Chip Selection to End of Write
lew
30
Address Valid to End of Write
t.w
30
-
40
-
50
-
Address Setup Time
t ..
0
-
0
-
0
-
Write Pulse Width
twP
30
-
35
-
40
-
ns
--ns
Write Recovery Time
tWR
5
-
5
-
5
t.w
20
-
20
-
20
-
ns
Data Valid to End of Write
Data Hold Time
IOH
0
-
0
-
0
-
n.
0
15
0
20
n.
0
-
0
-
n.
Write Enabled to Output in High Z·
Iwz
Output Active from End of Write *
* Transition is measured ± SOOmV from
This parameter
is sampled and not
tow
0
10
0
-
ns
high impedance voltage with Load B.
100 % tested.
• TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE Controlled)
Address
..,
--..
"""
1<.
N.
I••
-'''--l
"'''
D,.
(')
Do ..
«««
- ..z~
( (
• TIMING WAVEFORM OF WRITE CYCLE NO.2
Addre ••
v---
1-
-
t",.·~
/j// ///
_
...!!L.-
. . . . ..1-:=1s._Is.~~
--1f..
xx
-...~
Hilh Impedance
(CS
Controlled)
..c
I••
f--t"
1<.
r--....
~)-
,.,.(1)_
."-,, "
Din
" " ""
////
.I::::::!'"
XXXXXXXXXXXX
///
Is.
XXXX
xXX
Hilb. Impedance(4)
Do..
NOTES of
1.
2.
3.
Timina Waveform of Write
A write occurs during the overlap of a low CS and a low WE. (h,.)
t IVII is measured from the earlier of CS or WE' goiDg hiBb to tbe end of write cycle.
During this period.
pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
4. If the 'CS' low transition oceurs simultaneously with the 'WE low transition or after the WE transition. the output buffers remain
in a high impedanee state.
5. If C! is low during this period. VO pins are in the output state. Then the data input signals of opposite phase to the outputs
must not be applied to them.
6. Dout is the same phase of write data of this
•
wr;', cycle.
0
va
HITACHI
73
HM6148HLP-35, HM6148HLP-45;
HM6148HLP-55
Preliminary
1024-word x 4-bit High Speed Static CMOS RAM
• FEATURES
• Low Power Standby and Low Power Operation;
Standby: 5p.W (typ.). Operation: 300mW (typ.)
• Fast Access Time: 35/45/55ns (max)
• Capability of Battery Back Up Operation
• Single 5V Supply
• Completely Static RAM: No Clock or Timing Strobe
Required
• No Peak Power-On Current
• No Change of tACS with Short Deselected Time
• Equal Access and Cycle Time
• Directly TTL Compatible: All Inputs and Outputs
• Three State Output
• Pin-Out Compatible with Intel 2148H
(OP-IS)
• PIN ARRANGEMENT
• BLOCK DIAGRAM
A.o---OC==li
A. ---l:::C=:::::l
A. ---l:::C=:::::l Row
A. __-l:::C=:::::llleeod"
Memory Matrix
--OGND
64X64
A.o---l:::C=:::::l
A. o---~===L.-.J
1/0. --~r>---I
110. o-~tHl>---I
I/O. o--rl++-1I>---I
1/0• ......t+ttHl>---L_-.J
(Top View)
• ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Ratings
pnit
Terminal Voltage·
VT
-0.5 to +7.0
V
Power Dissipation
PT
1.0
W
Operating Temperature
T"PF
o to
+70
·C
Storage Temperature
Tit.
-55 to +125
·C
Storage Temperature··
T6/u
-10 to +85
·C
V" ... --3.5V (Pulse width-20ns)
• with respect to GND•
•• under bias.
• TRUTH TABLE
CS
WE
H
X
Not selected
IsB.
L
H
Read
Icc
Dout
Read Cycle 1. 2
L
L
Write
Icc
Din
Write Cycle I. 2
Mode
Nqte) The specifications of this device are subject to challP, ,vithout notice.
Please contact your nearest Hitachi's Sales Dept. regarding specifications .
74
I/O Pin
Vee Current
ISBI
•
HITACHI
Reference Cycle
High Z
- - - - - - - - - - - - - - - - - H M 6 1 4 8 H L P · 3 5 , HM6148HLP·45, HM6148HLP·55
.REC·OMMENDED DC OPERATING CONDITIONS (Ta-O to +70'C)
Item
Symbol
Supply Voltage
typ
max
Unit
4.5
5.0
5.5
V
0
0
0
V
min
Vee
GND
Input Voltage
*
V,.
2.2
VIL
-0.5
*
-
6.0
V
-
O.B
V
-3.0V (Pulse width 20ns)
.DC AND OPERATING CHARACTERISTICS[1] (Ta-O-70'C, Vcc -5V±lO%,GND-OV)
Symbol
Parameter
Input Leakage Current
Test Conditions
I
Vee-max, V..-GND to Vee
Ihol
IILl
Operating Power Supply Current: DC
Icc
C"S- Vi., Vi,o-GND to Vee
C"S- ViL, Il/o-OmA
Operating Power Supply Current: AC
1eci
min. cycle, ~ -
Standby Power Supply Current: DC
Is.
~-ViH
Standby Power Supply Current(l): DC
lsal
Output Leakage Current
v,-;., I//o-OmA
Vi.;;: Vee-O. 2V
VOL
IOL-BmA
Output High Voltage
VO H
IOH--4.0mA
typ
max
Unit
-
-
2.0
/lA
2.0
/lA
35
80
rnA
50
100
rnA
5
20
rnA
-
C"S;0.2V or
Output Low Voltage
min
2.4
1
50
/lA
-
0.4
V
-
-
V
Notes
(2)
Notes) 1. Typical limits are at Vcc -5.0V, Ts- +ZS"C and specified loading'.
2. l20mA max. lor HM6148HLP-35
• CAPACITANCE (Ta=25'C, f=IMHz)
typ
max
Unit
Input Capacitance
C..
V .. -OV
3
5
pF
Input /Output Capacitance
el/o
VI/O-OV
5
7
pF
Symbol
Item
Test Conditions
Note} This parameter is sampled and not 100% tested.
• AC CHARACTERISTICS (Vcc=5V±1O%, Ta-O to +70'C)
eRISE FALL TIME
Symbol
Item
Input Rise Time
I.
Input Fan Time
I,
Unit
min
typ
max
-
5
100
ns
5
100
ns
.AC TEST CONDITIONS
Input pulse levels: GND to 3.0V
Input rise and fall times: 5ns
Input and Output timing reference levels: 1.5V
Output load: See Figure
5\"
Dou,-..,..--1
5\"
31.:.. ______.r-_ _ _... ,
Dout
2552
ov
Output Load (A)
Output Load
(8)
(for tHz,tu,hrz.low)
*
..
t.-f,-Sns
Input Pulse Waveform
Including scope & jig.
•
HITACHI
75
HM6148HLP·35, HM6148HLP·45, H M 6 1 4 8 H L P . 5 5 - - - - - - - - - - - - - - - - .AC CHARACTERISTICS (Ta=O to 70'C, Vcc =5V±10%, unless otherwise noted.)
_READ CYCLE
HM6148HLP-35
HM6148HLP-55
Unit
max
min
Read Cycle Time
!Re
Address Access Time
!AA
~hip
HM6148HLP-45
Symbol
Item
Select Access Time
tACS
min
max
min
max
35
-
45
-
55
-
ns
-
35
-
45
-
55
ns
45
-
55
ns
35
Chip Selection to Output in Low Z
fLz*
10
-
10
--
10
-
Chip Deselection to Output in High Z
tHZ·
-0
20
0
20
0
20
ns
Chip Selection to Power Up Time
!PU
0
-
0
-
0
-
ns
30
ns
Output Hold from Address Change
5
!OR
Chip Deselection to Power Down Time
!PD
* Transition is measured ±500mV from bigh impedance voltage with Load(B).
At any temperature and voltage condition
1HZ
5
-
30
5
-
ns
ns
-
30
This parameter is sampled and not 100% tested.
max is less than I£z min.
eTlMING WAVEFORM OF READ CYCLE NO.1
(1)(2)
,,,
~
Address
,,,
~
'ON
ioN
~ XX
Oout
-TIMING WAVEFORM OF READ CYCLE
V--
Data Valid
~
NO.2(t)(S)
,,,
".
IN.
tACS
High Impedance
1"
Vee supply
-----
current
Dala Valid
''"
-----ir----------------.:.--"""\+
50%
1..
Note.) 1. WE is High for Read Cycle.
2. Device is continuously selected. CS- VIt..
3. Address Valid prior to or coincident with
76
High
Impedance
•
CS
transition Low .
HITACHI
--------------------------------~HM8148HLP-35.HM8148HLP-45.HM8148HLP-55
• WRITE CYCLE
HM6148HLP-35
Item
HM6148HLP-45
HM6148HLP-55
Symbol
Unit
min
max
min
max
min
max
45
-
55
-
ns
40
-
50
-
ns
ns
Write Cycle Time
Iwe
35
Chip Selection to End of Write
10K
30
-
Address Valil to End of Write
I",
30
-
40
-
50
Address Setup Time
I...
0
-
0
-
0
-
Write Pulse Width
Iwp
30
-
35
-
40
-
ns
Write Recovery Time
I...
5
-
5
-
5
-
ns
Data Valid to End of Write
low
20
20
-
ns
I..
0
0
-
20
Data Hold Time
-
0
-
ns
Write Enabled to Output in High Z'
Iw.
0
10
0
15
0
20
ns
Output Active from End of Write'
low
0
-
0
-
0
-
ns
ns
• Transition i. mea.ured :I: SOOmV from high impedance voltage with Load B.
This parameter is sampled and not 100 % tested.
AU inputs ,~. 1/ (rise and faU time) are less than lOOns.
• TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE Controlled)
Addreal
-
,
In
//// ///
... ....-2l....- I---""l!l...-
~~
--1
- 1..
~
..:c
.1:=....-
XX
Din
.1
00.1
( ( ( (
( ( (
(
(3)
wz~
'j()(
~I:-~
Hiib Impedance
.TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS Chntrolled)
Adclrest
-
I -
I,.
~,
Ie.
,.,.(1)_
-
.... (2)-
////
" " " " " ""
Din
-
we
xxxxxxxx
XX~
///
to.
YXXX
XXX
High Impedance (tl
Notes of Tming Waveform of Write :
1. A write occurs during the over"pf~ .. low "C"S" and a low W. (tn)
2. hR is measured from the earlier of ~ or WE'" ping high to the end of write cycle.
3. During this period. I/O pins are in the output state so that the input sip." of opposite phase to the outputs must not be applied.
,. If the 'C'S DW transition occurs simultaneously with the WE low transition or after the 'WE' transition, the output buffers remain in a high impedance state.
s. 1t"C"S'" is low during this period. I/O pins are in the output state. Then the data input signals of opposite' phase to the outputs must not be applied to them.
6. Dout is the same phase of write data'of this write cycle.
•
HITACHI
77
HM6148HLP-35,HM6148HLP-45,HM6148HLP-55----------------------------------.LOW Vee DATA RETENTION CHARACTERISTICS (O'C:;;Ta:;;70'C)
Symbol
Parameter
Test Conditions
VD.
Vee for Data Retention
~;;;Vee-0.2V
Data Retention Current
IccDR
Chip Deselect to Data Retention Time
tCDR.
Operation Recovery Time
h
Note) 1. he-Read Cycle Time.
•
.*
v..;;; Vee-O. 2V
or
min
typ
2.0
-
-
0
0";:;; Vi.;;;;0.2V
hC(I)
max
-
-
-
ns
-
-
n8
-LOW Vee DATA RETENTION WAVEFORM
~-------
4.SV---------
ir---"'--\ ______ J~ __
_____ _
;;:: VDa -O.2V
cs ___--'
ov-----------~-------------------------------
78
•
HITACHI
V
30·
20"
Vcc-3.0V
Vcc-2.0V
vcc-------""\ 1-_ _ _ _-"D"'A....TA""R"'E...T""Ell.NT!..iIO"'N'-'M""O"'D"'E~_ _ ___I
Unit
JlA
HM8147, HM8147-3
HM8147P, HM8147P-3
4096-word x 1-bit High Speed Static CMOS RAM
.FEATURES
• Single 5V Supply and High Density 18 Pin Package
• High Speed: Fast Access Time 55ns/70ns Max.
• Low Power Standby and Low Power Operation,
Standby:100IlW typ., Operation: 75mW typo
• Completely Static Memory - No Clock nor Timing Strobe
Required
• No Peak Power-On Current
• No Change of t ACS with Short Chip Deselect Time
• Equal Access and Cycle Time
• Directly TTL Compatible - All Input and Output
• Separate Data Input and Output: Three State Output
• Pin·out Compatible with Intel 2147 NMOS STATIC RAM
HM6147. HM6147-3
( ))(;-18)
HM6147P. HM6147P-3
.BLOCK DIAGRAM
A.
- - - - 0 Vcr
Memory Matrix
Row
Decoder
64X64
- - - - 0 GND
Ao
A.
A,
HI >---0
Din
00"
.PIN ARRANGEMENT
cs
WE
.ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Rating
Voltage on Any Pin relative to GND·
Vr
-0.5 to +7.0
V
Power Dissipation
PT
1.0
W
Operating Temperature
7;".
+70
·c
o to
Unit
Storage Temperature(Ceramic)
T. ..
-65 to +150
·C
Storage Temperature(Plastic)
T. ,•
-55 to +125
·c
•
V/.''I
min - -1.0V (Pulse Width
~
(Top View)
20n.)
.RECOMMENDED DC OPERATING CONDITIONS (O'C::;;Ta::;;70'C)
Parameter
Supply Voltage
Input High (logic 1) Voltage
Input Low (logic 0) Voltage
*
Symbol
Vee
GND
Vi.
Vi.
typ
max
4.5
5.0
5.5
V
0
0
0
V
2.2
3.5
6.0
V
-
0.8
V
min
-0.3·
Unit
V'L min--l.OV(Puise width£2Onsl
_HITACHI
79
HM6147, HM6147·3, HM6147P, HM6147p·3 - - - - - - - - - - - - - - - - - -
.DC AND OPERATING CHARACTERISTICS (O·C:iOTa:i070·C. Vcc -5V±lO%, GND-OV)
Parameter
Symbol
Input Leakage Current
I ILl I
Output Leakage Current
11.01
Operating Power Supply Current (1) DC
Icc
Operating Power Supply Current (2) DC
IccI
Average Operating Current (3)
/CC2
Standby Power Supply Current(l) DC
Is.
Standby Power Supply Current (2) DC
Issl
Output Low Voltage
Vo£
VON
Output High Voltage
min
typ
max
Unit
-
-
2.0
p.A
-
-
2.0
15
35
p.A
mA
12
-
mA
(2)
Cycle 150ns, duty 50%
-
14
-
-
5
12
mA
mA
(2)
CS-ViN
20
800
pA
-
0.40
Test Conditions
Vee-5.5V, GND to Vee
CS-ViN, Vn,-O-Vee
CS-Vi£, Output open
CS- Vi£, VIN~0.2V or
Vi.;o; Vee-0.2V
CS~
Vee-0.2V,
or Vi.;o; Vee-0.2V
Vi.~0.2V
-
I o£-12mA
I ON--8.0mA
2.4
-
Notes
V
V
Note) I. Typical limits are at Vcc-S.OV. To-25"C and specified loadinl.
2. Reference only
.AC TEST CONDITIONS
•
•
•
•
S"'"
Input pulse levels: GND to 3.5V
Input rise and fall times: 10 ns
Input and output timing reference levels: 1.5V
Output load: See Figure 1
UUUlo---..,...---+
• Including scope &: iii capacitance
FillUre 1 Output Load
.CAPACITANCE (Ta-25'C, f-l.OMHz)
Item
Input Capacitance
Note) This Plrameter
IS
Unit
5
pF
v... -OV
7
pF
Conditions
Coo
Cn,
Output Capacitance
max
v..-OV
Symbol
.ampled and not 100% tested.
• AC CHARACTERISTICS (Ta-O'C to 70'C, Vcc =5V±lO%, unless otherwise noted.)
-READ CVa..E
Parameter
HM6147/P-3
Symbol
Read Cycle Time
he
Addr••s Access Time
I ..
HM6147/P
min
max
55
-
Unit
max
-
min
70
-
n.
55
-
70
ns
55
-
Chip Select Acc••s Time
lACS
70
ns
Output Hold from Addres. Change
to.
5
-
5
-
ns
Chip Selection to Output in Low Z
t£z
10
-
10
-
ns
Chip Deselection to Output in High Z
1HZ
0
40
0
40
ns
Chip Selection to Power Up Time
tp.
0
-
0
-
ns
Chip Deselection to Power Down Time
tPD
30
ns
-
30
-
- WRITE CVa..E
Parameter
HM6147/P-3
min
max
Symbol
HM6147/P
min
max
Unit
W rite Cycle Time
twe
55
-
70
-
ns
Chip Selection to End of Write
tel'
45
-
55
-
n.
Address Valid to End of Write
t."
45
55
t.s
0
Write Pulse Width
t"p
35
40
-
ns
Address Setup Time
W rite Recovery Time
tWI
10
-
15
-
ns
Data Valid to End of Write
25
-
30
-
n.
Data Hold Time
to"
to.
10
-
10
-
ns
Write Enabled to Output in High Z
twz
0
0
35
ns
Output Active from End of Write
to"
0
0
-
ns
80
•
HITACHI
~
-
0
ns
ns
---------------------------------------HM6147,HM6147-3,HM6147P,HM6147P-3
-------- ("---------1*
r
~~-W-H------I.-.::::::,~I--------~ ------
eTIMING WAVEFORM OF READ CYCLE
NO.1")("
tH
f.-
Address
preVIl)US
Uat.l)ut
Data val id
data valid
enMING WAVEFORM OF READ CYCLE
NO. 2
(1)(3)
cs
DU.oul
Vee supply
Notes: 1. WE is high for READ Cycle.
2. ~is low for READ Cycle.
3. Addresses valid prior to or coincident with CS
transition low.
e nMING WAVEFORM OF WRITE CYCLE
1 - - - - - - - - .,----------1
1
Address
Data .n
Data oul
Oat •• n valid
/W'l'"---------t""=C
Cu. undef.ned
_ _ _ _ _ _ _ _ _ _ _ _ _- '
•
~-
HITACHI
H'R'h Impedance
81
HM6147,HM6147-3,HM6147P,HM6147-3 - - - - - - - - - - - - - - - - - - - - SUPPLY CURRENT
VB. SUPPLY VOLTAGE
SUPPLY CURRENT
VB. AMBIENT TEMPERATURE
0
0
r.=25'C
5
Vcc=S.oV
5
0
0
leS--::: :::;:::::-
5
o~
5~
I
/eer
~
-
I(C2
0
5
5
0
0
4.75
5.0
40
20
5.25
Supply Voltage Vee (V)
60
ACCESS TIME
SUPPLY VOLTAGE
80
("C I
Ambient Temperature To
ACCESS TIME
VB. AMBIENT TEMPERATURE
VB.
I.3
1.3
Vee = S.oV
r.=25'c
I.2
.2
.Ir--1.0
--
t---
tAA, lACS
o.9
0.8
O.7
I. I
1.0
r---
~
~
~
I--
P
0.9
0.8
4.75
4.5
5.25
5.0
Supply Voltage
o.7
5.5
o
Vee (V)
Ambient Temperature
ACCESS TIME
LOAD CAPACITANCE
80
60
40
20
Ta ("C 1
SUPPLY CURRENT
VB. FREQUENCY
VB.
I~
IS0nl
70nl
55ns
0
L_
Tca=25"'C
.,/"V
Vcc=MIN
0
/
V
100
..--
V
~
Ta=2S"C
~
O~
200
300
A
400
Load Capacitance CL (pF)
82
1.0
10
Frequency / (MHz)
•
HITACHI
15
20
HM6147LP, HM614 7LP-3
4096-word x 1-bit High Speed Static CMOS RAM
.FEATURES
• Single 5V Supply and High Density 18 Pin Package
• High Speed: Fast Access Time 55ns/70ns Max.
• Low Power Standby and Low Power Operation,
Standby: 5jJ.W typo Operation: 75mW typo
• Completely Static Memory - No Clock nor Timing Strobe
Required
• No Peak Power-On Current
• No Change of tACS with Short Chip Deselect Time
• Equal Access and Cycle Time
• Directly TTL Compatible - All Input and Output
• Separate Data Input and Outpu,t: Three State Output
• Capability of Battery Back up Operation
• Pin·out Compatible with Intel 2147 NMOS STATIC RAM
.BLOCK DIAGRAM
(OP-IS)
h_-D:=::1
AJ
A,
---0
Row
o-----iIL:::J
De('.xler
i'rt'
.PIN ARRANGEMENT
Memury Malrlx
64x64
""o----1l:::E=:J
hO----1I:::E=:J
D"UI
Din
AJ At As At Au All
(Top View)
.ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Rating
Voltage on Any Pin relative to GND"
Vr
-0.5 to +7.0
V
Power Dissipation
PT
1.0
W
Operating Temperature
T.",
o to
+70
·C
Storage Temperature
T. r•
-55 to +125
·C
*
Unit
VI/.. Mm--l.OV (Pulse Wldth:li ZOns)
.RECOMMENDED DC OPERATING CONDITIONS (O·C ~ Ta~70·C)
Parameter
Supply Voltage
Symbol
Vee
typ
max
Unit
4.5
5.0
5.5
V
0
0
0
V
3.5
6.0
V
-
0.8
V
min
GND
•
Input High (logic 1) Voltage
ViN
2.2
Input Low (logic 0) Voltage
Vi.
-0.3"
Vll. min- -1.0V (Pulse width:iii2Ons.)
•
HITACHI
83
HM6147LP,HM6147LP-3 - - - - - - - - - - - - - - - - - - - - - - - - - - -
.DC AND OPERATING CHARACTERISTICS (O'C:;aTIJ:;a10'C, Vcc -5V±10%, GND-OV)
Parameter
Input Leakage Current
Output Leakase Current
Operating Power Supply Current II) DC
Operating Power Supply Current 12) DC
min
typ
max
Unit
Vcc -5.5V, GND to Vee
-
2.0
pA
Symbol
IILlI
11£01
• Icc
Icci
Test Condition
Notes
CS-VIH, y'.,-O-Vcc
-
-
2.0
pA
CS-VIL, Output open
-
15
35
mA
CS-VJL, V1N::iOO.2Vor
VJN;o; Vee-0.2V
-
12
-
mA
(2)
(2)
Average Operating Current 13)
lccz
Cycle lOOns, duty 50%
-
14
-
mA
Standby Power Supply Current Il) DC
I ..
CS-ViH
-
5
12
mA
-
1
100
pA
-
-
0.40
V
2.4
-
-
V
CSo: Vee-0.2V,
Standby Power Supply Current 12) DC
1ss1
Output Low Voltage
VOL
IOL-12mA
Output High Voltage
VOH
IOH--8.0mA
ViN:iOO.2V or
ViN;o; Vee-0.2V
Note) 1. Typical Ii.it. are at Vcc-S.OV, To-25°C and apeeified loading_
2. Reference only.
~
r,·
.AC TEST CONDITIONS
• Input pulse levels: GND to 3.5V
• Input rise and fall times: 10 ns
• Input and output timing reference levels: 1.5V
• Output load: See Figure 1
I)IIUlo---t--~
:toou
* Including scope
&;
jig capacitance
Fipre 1 Output Load
.CAPACITANCE (TIJ-25'C, f-1.aMHz)
Item
Symbol
max
Unit
Input Capacitance
C..
V1N-OV
Condition
5
pF
Output Capacitance
Cn ,
Vn,-OV
7
pF
Note) This parameter is sampled and not 100% tested.
• AC CHARACTERISTICS (TIJ-O'C to 70'C, Vcc=5V±10%, unless otherwise noted.)
eREAD CYCLE
HM6147LP-3
Parameter
HM6147LP
Symbol
Unit
min
max
min
max
Read Cycle Time
he
55
-
70
-
ns
Address Access Time
IAA
-
55
-
70
ns
Chip Select Access Time
fACS
-
55
-
10
ns
Output Hold from Address Change
10H
5
-
5
ns
Chip Selection to Output in Low Z
fLz
10
-
10
-
Chip Deselection to Output in High Z
1HZ
0
40
0
40
ns
Chip Selection to Power Up Time
Ipu
0
-
0
-
ns
Chip Deselection to Power Down Time
IPD
30
ns
84
-
•
HITACHI
30
-
ns
--------------------------HM6147LP,HM6147LP-3
-WRITE CYCLE
HM6147LP-3
HM6147LP
Symbol
Parameter
Unit
min
max
min
max
Write Cycle Time
Iwe
55
-
70
-
ns
Chip Selection to End of Write
lew
45
-
55
-
ns
Address Valid to End of Write
lAw
45
-
55
-
ns
Addres. Setup Time
I ..
0
-
0
-
ns
Write Pulse Width
Iwp
35
-
40
-
ns
W rite Recovery Time
Iwo
10
-
15
n.
Data Valid to End of Write
low
25
-
30
Data Hold Time
ION
10
-
10
-
Write Enabled to Output in High Z
twz
0
35
ns
0
-
ns
Output Active from End of Write
low
0
30
0
-
.
n.
ns
-TIMING WAVEFORM OF READ CYCLE NO.1'''(2)
'""v:--------,.,,--------*-i
=t.
.wdreslO
-'o-._--w-:.-:.-=--=--=---i----- ---
preVlnu!lo
Oata out
Uala valid
data valid
-TIMING WAVEFORM OF READ CYCLE NO.2(1)(3)
Dala valld
Oala out
Vee supply
--''C
NOTES: 1. WE is high for READ Cycle.
2. CS is low for READ Cycle.
3. Addresses valid prior to or coincident with ~ transition low.
eHITACHI
85
HM6147LP,HM6147LP-3 - - - - - - - - - - - - - - - - - - - - - - - - - • TIMING WAVEFORM OF WRITE CYCLE
Add.....
Data in
0.,.
out
.LOW Vee RETENTION CHARACTERISTICS (Ta=O'C to 70'C)
Parameter
Symbol
Test Condition
Vee for Data Retention
VD•
CS~ Vee-O.2V.
Data Retention Current
IceDI
Vee-2.0V. CS~1.8V.
Chip Deselect to Data Retention Time
I CDR.
Operation Recovery Time
t.
v..~
Vee-0.2V or :;;0.2V
v. ••a.8V or
:;;0.2V
min
typ
max
2.0
-
40
pA
-
-
ns
0
lac·
• '.tc-RNCI Cycle Time
• LOW Vee RETENTION CHARACTERISTICS
Vcr _ _ _ _ _ _ _......
. Data Retention. Mode
I-------------------1,...
_______
v..
r-----\ _________
______ _
~
~:it
VDR-O.2V
C"S _ _ _..J
a---- ______________________________________ _
86
•
HITACHI
Unit
V
ns
HM6147H-36, HM6147H-45,
HM6147H-55, HM6147HP-35,
HM6147HP-45, HM6147HP-55
4096-wordX1-bit High Speed Static CMOS RAM
• FEATURES
• Single 5V Supply and High Density 18 Pin Package
• High Speed: Fast Access Time 35ns/45ns/55ns Max.
• Low Power Standby and Low Power Operation,
Standby: 100pW typ., Operation: 150mW typo
• Completely Static Memory - No Clock nor Timing·Strobe
Required
• No Peak Power-On Current
• No Change of tA cs with Short Chip Deselect Time
• Equal Access and Cycle Time
• Directly TTL Compatible - All Input and Output
• Separate Data Input and Output: Three State Output
• Plug-In Replacement with Intel 2147H NMOS STATIC RAM
HM6147H -35. HM6147H -45,
HM6147H-55
IDG-18)
HM6147HP-35, HM6147HP-45,
HM6147HP-55
.BLOCK DIAGRAM
---0
-I._-tt=-1
.... - - { I : : = j
l'ft"
Memory Matrix
64 " 64
GNU
,\-_-tt""J
,,,&--~---1
Aoc>--t£:::::l
(DP-18)
O,n
U"ul
.PIN ARRANGEMENT
.ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Rating
Unit
V
rnA
Voltage on Any Pin relative to GND
VT
DC Output Current
I.
Power Dissipation
PT
Operating Temperature
Storage Temperature (Ceramic)
4,.
1:,.\6,.,1
T.r6
-65 to +150
·c
·c
Storage Temperature (Plastic)
T.,•
--55 to +125
··C
Storage Temperature (under bias)
* Pulse Width 20ns,
- 3.5· to +7.0
20
1.0
o to
+70
-10 to +85
W
·C
(Top View}
DC: -O.5V
•
HITACHI
87
HM6147H-35,HM6147H-45,HM6147H-55,HM6147HP-35,HM6147HP-45,HM6147HP-55 - - - - - - -
.RECOMMENDED DC OPERATING CONDITIONS (O'C:O;Ta:O;70'C)
Parameter
min
Symbol
Vee
Supply Voltage
4.5
GND
Input High (Iogi, 1) Voltage
\.IN
Input Low (logic 0) Voltage
\.IL
* Pul.. Width 20....
0
2.0
-3.0·
typ
max
Unit
5.0
0
S.5
V
0
V
3.0
6.0
O.S
V
V
-
llC: -O.SV
.DC AND OPERATING CHARACTERISTICS (O·C;:;;Ta:O;70'C. Vcc-5V±lO%. GND=OV)
Parameter
Symhol
Test Condition
Input Leakage Current
IILlI
Vec-S.SV. GND to Vee
Output Leakage Current
lito I
CS-V'N.
Operating Power Supply Current(J) DC
Icc
CS-\.IL. Output open
Operating Power Supply Current (2) DC
/CCl
CS-\.IL. Minimum Cycle
Standby Power Supply Current (J) DC
I ..
CS-\.I•• Vee-Min to Max
v... -OV-Vee
CSo: Vee-0.2V.
Standby Power Supply Current (2) DC
ISiI
Output Low Voltage
VOL
10L-SmA
Output High Voltage
VON
ION--4mA
\.IN:OO.2Vor V'N<:Vee-0.2V
min
typ
max
Unit
-
-
10
pA
-
10
pA
30
80
mA
40
80
mA
8
20
mA
20
800
pA
-
-
0.40
V
2.4
-
-
V
-
Note) 1. The operating ambient temperature rall8'e is para.teed with transverse air flow exceeding 400 linear feet minute.
2. Typical limits are at Vcc-5.0V. Ta-2S"C and specified loadina:.
• AC TEST CONDITIONS
•
•
•
•
•
51011
Input p!Jlse lewis: GNO to 3.0V
I nput rise and fall times: 5 ns
I nput timing reference levels: 1.5V
Output load: See Figure
Output timing reference levels:
1.5V (HM6147H/P·35)
O.S to 2.0V (HM6147H/P-45/55)
Output Load A U~ut
3OpF'
3300
:g
• Including scope &. jil capacitance'
rrr
"IIII!
0....
Output Load B
3311s.!
5pF
.CAPACITANCE (Ta-25'C. f-l.OMHz)
item
Input Capacitance
Output Capaeilanee
max
Unit
V,,-OV
5
pF
V.,-OV
6
pF
Symbol
C"
Cn ,
Conditions
Note) This parameter is s.ampled and not 100% tested.
88
.HITAOHI
- - - - - - - HM6147H-35.HM6147H-45.HM6147H-55.HM6147HP-35.HM6147HP-45.HM6147HP-55
.AC CHARACTERISTICS (Ta-O·C to 70·C, Vcc-5V±10%, unless otherwise noted.)
eREAD CYCLE
HM6147H/P-35
HM6147H /P -45
HM6147H/P-55
min
max
min
min
Symbol
Parameter
Unit
max
Notes
max
Read Cycle Time
IRe
35
-
45
-
55
-
ns
Address Access Time
lAA
-
35
-
45
-
55
ns
Chip Select Access Time
t.~cs
-
35
-
45
-
55
ns
Output Hold from Address Change
10.
5
-
5
-
5
-
ns
Chip Selection to Output in Low Z
hz
5
-
5
-
5
-
ns
(2). (3), (1)
Chip Deselection to Output in High Z
1Hz
0
30
0
30
0
30
ns
(2), (3), (1)
Chip Selection to Power Up Time
Ipu
0
-
0
-
0
-
ns
Chip Deselection to Power Down Time
IPD
20
ns
-
20
-
20
-
(I)
eTiMING WAVEFORM OF READ CYCLE NO.1 ")(5)
Address
Data Valid
Data Out
eTiMING WAVEFORM OF READ CYCLE NO.2"'(6)
Data Valid
Data Out
l'et Supply
Current
-------h------------,
I"
50~Q
Iss
Notes: 1. All Read Cycle timings are referenced from last valid address to the
first transitioning address.
2. At any given temperature and voltage condition, 'HZ max. is less than
, LZ min. both for a given device and from device to device.
3. Transition is measured ±SOOmV from steady state voltage with
~cified loading in Load B.
4. WE is high for READ Cycle.
5. Device is continuously selected, CS'=VIL'
6. Addresses valid prior to or coincident with CS transition low.
7. Thi~ parameter is sampled and not 100% tested •
•
HITACHI
89
HM6147H-35, HM6147H-45, HM6147H-55, HM6147HP-35, HM6147HP-45, HM6147HP-55----
e WRITE CYCLE
Symbol
Parameter
HM6147H/P-35
HM6147H/P-45
min
max
min
max
min
max
45
55
ns
45
-
45
-
45
0
0
25
-
30
0
-
0
HM6147H/P-55
Unit
Notes
Write Cycle Time
twe
35
Chip Selection to End of Write
tew
35
Address Valid to End of Write
tRW
35
Address Setup Time
t ..
0
Write Pulse Width
twp
20
Write Recovery Time
tWR
0
-
Data Valid to End of Write
tDW
20
-
25
-
25
Data Hold Time
tD.
10
-
10
-
10
-
Write Enabled to Output in High Z
twz
0
20
0
25
0
30
ns
(3), (4)
Output Active from End of Write
tow
0
-
0
-
0
-
ns
(3), (4)
45
(2)
ns
ns
ns
ns
ns
ns
ns
eTIMING WAVEFORM OF WRITE CYCLE (WE CONTROLLED)
'"'
Addre ..
'ow
...
,,,
Dat. I"
Oata (Nt
DUI Undefined
eTiMING WAVEFORM OF WRITE CYCLE (CS CONTROLLED)
Addrul
'"
---'\
--I
t::::::.-1
,,,
'(
t ..
\ \ \ \ \
I
,,,
,.,
...
...
/ / /
Oataln
Dati In Valid
to,
.1
Dt.tt.()qt
HIJllh Impedance
Oat. Undefined
Note J Cs or
Notes: 1.
2.
3.
4.
90
*
WE are
Hilh for Address Transition
If CS" goes high simultaneously with WE high, the output remains In a high impedance states.
AU Write Cycle timings are referenced from the last valid address to the first transitioning address.
Transition is measured tSOOmV from steady state voltage with specified loading In Load B.
This parameter is sampled and not 100% tested.
•
HITACHI
----HM6147H·35, HM6147H·45, HM6147H·55, HM6147HP·35, HM6147HP·45, HM6147HP·55
ACCESS TIME VS. SUPPLY VOLTAGE
ACCESS TIME VS. AMBIENT TEMPERATURE
1.3
1. 3
Ta=2S"C
Vcc=S.OV
1. 2
1.
1. 2
1____.
1.0
~
f:;
O.9
.l!
0.8
0.7 4.5
1. 1
---- --......r---
V
J,/
o.
o.8
4.75
5.0
o. 7
5.5
5.25
1.3
1.6
1.2
O~
I-'"
./
~
~•
------
1.1
~
1.0
0
~
Ta=2S'C
Vcc=MIN
0.9
<3
~
"i
~
o.8
0.6 100
300
200
80
SUPPLY CURRENT VS. FREQUENCY
1.8
/
60
40
20
Ambient Temperature Ta COC)
ACCESS TIME VS. LOAD CAPACITANCE
1.
./
1.0
Supply Voltage Vee (V)
1. 2
.....V
500
400
0.8
0.7 0
10
15
25
20
INPUT LOW VOLTAGE VS. SUPPLY VOLTAGE
INPUT HIGH VOLTAGE VS. SUPPLY VOLTAGE
I.3
.3
Ta=25t
Ta=25"C
1. 2
.2
--
1.1
o. 9
..
oS
30
Frequency / (MHz)
Load Capacitance Ct. (pFl
I.0
f-
l--- ~
I
l--0
~
9
.!
o.8
O. 7 4.5
4.75
5.0
5.25
----
j..--
5.5
J.---
o.8
O. 7
4.5
4.75
5.0
5.25
5.5
Supply Voltage Vce (V)
Supply Voltage Vee (V)
eHITACHI
91
HM6147H-35,HM6147H-45,HM6147H-55,HM6147HP-35,HM6147HP-45,HM6147HP-55 - - - - - - -
OUTPUT CURRENT VS. OUTPUT VOLTAGE
OUTPUT CURRENT VS. OUTPUT VOLTAGE
1.6
1. 6
\
I.4
E
1
2
\
\
\
0
0.8
0.6
I
I.4
\
1. 2
d
r.=2;"C
Vcc""5V
~
e
~
u
1.0
o.8
/
j
o.6
\
o.4 0
.
1.4
.
j
10-
~
,
10~ I
V
o
z
L
"'"
/V
~
0.8
~
0.2V
Vee -3.0V, CS;;:2.8V
VIN0iI;2.8V or VIN:ii0.2V
min
typ
msx
2.0
-
-
-
-
50
pA
0
-
-
ns
he·
-
-
ns
See Retention Waveform
Operation Recovery Time
fA
• h, - Read Cycle Time.
e LOW Vtc DATA RETENTION WAVEFORM
Vee -
nata Retention" Mode
_ _ _ _ _ _-,.
~--_.J
w----------------- _________________________ _
96
•
HITACHI
Unit
V
HM6116-2, HM6116-3, HM6116-4
HM6116P-2, HM6116P-3, HM6116P-4
2048-word x 8-blt High Speed Static CMOS RAM
.FEATURES
• Single 5V Supply and High Density 24 Pin Package
• High speed: Fast Access Time
120ns/150ns/200ns (max.)
• Low Power Standby and
Standby:
100pW (typ.)
Low Power Operation
Operation: 180mW (typ.)
• Completely Static RAM:
No clock or Timing Strobe Required
• Directly TTL Compatible: All Input and Output
• Pin Out Compatible with Standard 16K EPROM/MASK ROM
• Equal Access and Cycle Time
HM6ll6-2, HM6ll6-3.
HM6ll6-.
.FUNCTIONAL BLOCK DIAGRAM
(OG'24)
- - 0 Vee
HM6ll6P-2, HM6ll6P-3.
HM6ll6P-.
---OCND
1/0,0--......-1
1/0. 0--"-+-4
IvJ
'"
(OP-24)
AI,
'"
.PIN ARRANGEMENT
YiEo-----.
.ABSOLUTE MAXIMUM RATINGS
Item
Voltage on Any Pin Relative to GND
Symbol
Vr
Operating Temperature
T.,r
Storage Temperature (Plastic)
T.,•
Storage Temperature (Ceramic)
Temperature Under Bias
Power Dissipation
T.t.
T...
Pr
* Pulse Width SOns: -1.5 V
Rating
Unit
-0.5· to +7.0
o to +70
-55 to +125
-65 to +150
-10 to +85
1.0
V
·C
·C
·C
·C
W
.TRUTH TABLE
OE
WE
X
Mode
Not Selected
Vee Current
X
L
H
H
L
Read
Write
Icc
Dout
L
Icc
Din
L
L
L
Write
Icc
Din
CS
H
L
•
Iss,
IS81
HITACHI
[/0 Pin
Ref. Cycle
High Z
Read Cycle (1)-(3)
Write Cycle (I)
W rite Cycle (2)
97
HM6116-2,HM6116-3,HM6116-4,HM6116P-2,HM6116P-3,HM6116P-4 - - - - - - - - - - - -
.RECOMMENDED DC OPERATING CONDITIONS (Ta=O to +70'C)
typ
max
Unit
4.5
5.0
5.5
V
0
0
0
V
ViH
2.2
3.5
6.0
V
VIL
-1.0·
-
0.8
V
Symbol
Item
min
Vee
Supply Voltage
GND
Input Voltage
• Pulse Width: SOns. DC: V/L min- -O.3V
.DC AND OPERATING CHARACTERiSTICS (Vcc=5V±10%, GNO-OV, Ta=O to +70'C)
Symbol
Item
Input Leakage Current
Output Leakage Current
Operating Power Supply
Current
Average Operating Current
Standby Power Supply
Current
Unit
typO
max
min
typO
max
10
-
-
10
JlA
-
10
JlA
-
-
-
-
10
-
Icc
CS-!-iL, lr",-OmA
-
40
80
-
35
70
mA
IccI"'''
ViH-3.5V, !-iL-0.6V,
lr.",-OmA
-
35
-
-
30
-
mA
Ihol
Vec-5.5V, V..-GND to Vee
cs- V/H
lecI
Min. cycle, duty-l00%
-
40
80
70
mA
CS-VIH
-
5
15
-
35
Iss
5
15
rnA
lssl
CS<:Vec-0.2V. !-i.;o;Vee
-0.2V or V..:O>O.2V
-
0.02
2
-
0.02
2
rnA
10L-4mA
-
0.4
-
-
-
0.4
V
-
2.4
-
-
V
VOH
*
**
HM6116/P-3/-4
min
or OE= VIH,
!-i",-GND to Vee
Ihll
VOL
Output Voltage
HM6116/P-2
Test Conditions
10L-2.1mA
10H--1.0rnA
-
2.4
-
V
V,·c-5V. To-2S·C
Reference Only
.AC CHARACTERISTICS (Vcc =5V±10%. Ta=O to +70'C)
.AC TEST CONDITIONS
Input Pulse Levels: 0.8 to 2.4V
Input Rise and Fall Times: 10 ns
Input and Output Timing Reference Levels: 1.5V
Output Load: lTTL Gate and CL = 100pF Oncluding scope and jig)
.READ CYCLE
Item
HM6116/P-2
Symbol
min
HM6116/P-3
max
min
HM6116/P-4
max
min
max
Unit
Read Cycle Time
he
120
-
150
-
200
-
ns
Address Access Time
t ..
120
-
200
ns
tACS
120
-
150
Chip Select Access Time
-
150
-
200
ns
Chip Seleciion to Output in Low Z
tcLZ
10
-
15
-
15
-
ns
Output Enable to Output Valid
10E
-
80
-
100
-
120
ns
10
Output Enable to Output in Low Z
tOLZ
Chip Ueselecti"n to Output in High Z
teHZ
Chip Disable to Output in High Z
tOHZ
Output Hold from Address Change
tOH
98
•
-
15
-
15
-
ns
1)-
40
0
50
0-
60
os
0
40
0
50
0
60
ns
10
-
15
-
15
-
ns
HITACHI
------------HM6116-2,HM6116-3,HM6116-4,HM6116P-2,HM6116P-3,HM6116P-4
eWRITE CVQ.E
Item
HM6116/P-2
Symbol
min
!M6ll6/P-3
max
max
min
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Iwc
120
-
150
lew
70
105
-
90
120
Address Set Up Time
lAS
20
-
20
Write Pulse Width
Write Recovery Time
Output Disable to Output in High Z
Iwp
70
90
IWR
5
0
0
-
lAW
10HZ
Write to Output in High Z
Data to Write Time Overlap
tWHZ
10.
35
5
low
5
low
Data Hold from Write Time
Output Active from End of Write
40
50
-
-
-
10
0
50
60
0
40
-
10
10
HM6116/P-4
min
max
200
-
Unit
20
120
-
ns
ns
ns
ns
-
ns
10
0
-
ns
ns
ns
ns
120
140
0
60
10
10
60
60
-
-
ns
ns
.CAPACITANCE (J-IMHz, Ta-2S"C)
Symbol
Item
Input Capacitance
Input/Output Capacitance
C ••
CI;O
Test Conditions
v..-OV
v,,.,-OV
typ
max
3
5
7
5
Unit
pF
pF
Note) This pe.rameter is sampled and not 100% te8ted.
• TIMING WAVEFORM
eREAD CVQ.E (1)(1)
Addrelll
()nul
eREAD CVQ.E (2) (1)(2) (4)
Address
DOUI
eREAD CVQ.E(3)(I)(3)(')
1=
~'A of a low CS and a lowWE.
2. tWR is measured from the earlier of CS-or W glting high to the end
of write cycle.
3. During this period, 1/0 pins are in the output state so that the input
signals of opposite phase to the outputs must not be applied.
4. If the cs- low transition occurs simultaneously with the 'WE low
transitions or after the WJ:: transition, output remain in a high impedance state.
S. 'Ulris continuously low. (UE = V/L)
6. Dout is tlte same phase of write data of this write cycle.
7. DO.ll.Lis the read data of next address.
8. If CS is Low during this period, 1/0 pins are in the output state.
Then the data input signals of opposite phase to the outputs must
not be applied to them .
100
•
HITACHI
- - - - - - - - - - - - - HM6116-2,HM6116-3,HM6116-4,HM6116P-2,HM6116P-3,HM6116P-4
SUPPLY CURRENT
VB. SUPPLY VOLTAGE
SUPPLY CURRENT
VB. AMBIENT TEMPERATURE
1.6
1.6
Vcc=5.0V
T.-25"C
1.4
]
i
!C
1.2
~
1.0
./
~
.!i
i!
d
..,..,.V-'
0.8
/"
i"'"
~
J
6
0.6
0.4
0,4
4.15
U
5.0
5.5
5.25
--- ----o
20
40
ACCESS TIME
SUPPLY VOLTAGE
80
60
Ambient Tl'mparature Ta
Supply Voltage Vcc (V)
r--
(oe'
ACCESS TIME
AMBIENT TEMPERATURE
VB.
VB.
1.3
1.3
Vcc=S.ov
r.=25'C
1.2
I~
~
0.9
i
0.8
"./
............
~
--..........
1.0
r'--...
~
0.7
4.15
5.0
Supply Voltage
i
!
~
j
=
j
.l1
0.8
5.5
5.25
VC('
/
~
o
(V)
20
40
SUPPLY CURRENT
VB. FREQUENCY
1.8
1.3
/
1A
1.0
200a.
150n.
120ns
".
1.6
1.2
80
60
i\mbient Temperature Til (OCl
ACCESS TIME
VB. LOAD CAPACITANCE
I
;:;
0.9
0.7
U
]
;:;
/'"
V
L
V
----
'"
r.=25'C
Vcc-MIN
0.8
0.8
0.6
0.7
100
200
300
400
500
o
10
Frequency
Load Capacitance Q. (pFJ
•
HITACHI
J
(MHz)
101
HM6116-2,HM6116-3,HM6116-4,HM6116P·2,HM6116P·3,HM6116P-4 - - - - - - - - - - - - LOW INPUT VOLTAGE
va. SUPPLY VOLTAGE
HIGH INPUT VOLTAGE
va. SUPPLY VOLTAGE
1.3
.3
r.=25'C
Ta=25"C
.2
1.2
]
-
1
t
1.0
~
i o.9
-
•
~
•
J.
~
O.1
4.5
1.0
~
O.8
~
~
9
O.1
5.0
4.15
5.25
4.5
5.5
8
O.6
I.6
TII=2S-c
,
Vcc=5V
1.4
/
]
\
~
1.2
~
\
~
1.0
E
d o.8
\
it
.§
0.6
/
\
O. 4
0.4
Output Volt.le
102
5.5
OUTPUT CURRENT
vs. OUTPUT VOLTAGE
1.6
1.0
5.25
5.0
4.15
Supply Voltage Vee (V)
OUTPUT CURRENT
va. OUTPUT VOLTAGE
1.2
~
0.8
Supply Volt_Ie, Vee (V)
1.4
--
1.1
1 o.
..s
.!l
~
:!
VOH
(V)
o
0.2
/
/
V
T.=25'C
Vcc=5V
•
HITACHI
0.6
0.4
Output Voltage
VOl.
(V)
0.8
HM61161-2, HM61161-3,
HM61161-4
--Wide Operating Temperature Range2048-word x 8-blt High Speed Static CMOS RAM
.FEATURES
• Wide Operating Temperature Range. . • . . . . . . .. -40-+85°C
• Single 5V Supply and High Density 24 Pin Package
• High speed: Fast Access Time
120ns/150ns/200ns (max.)
• Low Power Standby and
Standby:
100llW (typ.)
Low Power Operation
Operation: 180mW (typ.)
• Completely Static RAM:
No clock or Timing Strobe Required
• Directly TTL Compatible: All Input and Output
• Pin Out Compatible with Standard 16K EPROM/MASK ROM
• Equal Access and Cycle Time
.FUNCTIONAL BLOCK DIAGRAM
IOG·24)
----OVe(.·
\
Memor, Matrix
Row
Decoder
.PIN ARRANGEMENT
--oGND
•
128X128
•
110.0--......-1
Colu" 1/0
Data
Control
1/0. o----H--I
iYEo--___
.ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Rating
Voltage on Any Pin Relative to GND
VT
-0.5* to +7.0
V
Operating Temperature
T..pr
Storage Temperature
T.,•
PT
- 40 to +85
-65 to +150
·c
·c
1.0
W
Power Dissipation
Unit
• Pulse Width 50ns : -1.5 V
eHITACHI
103
HM61161-2, HM61161-3, HM61161-4 - - - - - - - - - - - - - - - - - - - - - - - -
.TRUTH TABLE
CS
Ref. Cycle
Mode
Vee Current
I/O Pin
Not Selected
IS8, Is81
High Z
H
Read
Icc
Dout
L
Write
Din
W rite Cycle 111
L
Write
Icc
Icc
Din
Write Cycle 121
DE
x
WE
x
L
L
L
H
L
L
H
Read Cycle (1)-131
.RECOMMENDED DC OPERATING CONDITIONS (Ta=-40 to +a5'C)
Item
Symbol
typ
max
4.5
5.0
5.5
V
0
0
0
V
lOH
2.2
3.5
6.0
V
lOL
-l.0·
-
0.8
V
min
Vee
Supply Voltage
GND
Input Voltage
* Pulse
Width: SOns, DC: V/L min- -O.3V
.DC AND OPERATING CHARACTERISTICS (Vcc=5V±lO%, GND=OV, Ta=-40
Symbol
Item
Test Conditions
Output Leakage Current
I ILl I
I lUI I
CS~
Operating Power Supply
Icc
CS~lOL,
Current
fecI··
V,H~3.5V,
Average Operating Current
/cel
Standby Power Supply
Input Leakage Current
Current
Output Voltage
*
*.
Unit
min
to
+85'C)
typ·
max
Unit
-
-
10
p.A
-
-
10
p.A
-
35
90
-
30
-
~
I rnA
Min. cycle. duty= 100%
-
35
90
rnA
ISB
CS~
-
4
20
rnA
I S81
CS~ Vee-O. 2V, v..~ Vee -0.2V or
-
0.02
2
rnA
-
0.4
V
2.4
-
-
V
Vec~5.5V,
V.. ~GND to Vee
Vm or OE- VIH,
V/~~GND
to Vee
II",~OmA
lOL~0.6V.
1//o=OmA
VIH '
VOL
IOL-2.lmA
VOH
IOH~
v.. ";0.2V
-l.OmA
Vr:r=5V. Ta-25C
Reference Only
.AC CHARACTERISTICS (Vcc =5V±10%, Ta=-40 to +85'C)
-AC TEST CONDITIONS
Input Pulse Levels: 0.8 to 2.4V
Input Rise and Fall Times: 10 ns
Input and Output Timing Reference Levels: 1.5V
Output Load: 1TTL Gate and CL = 100pF (including scope and jig)
-READ CYCLE
Item
Symbol
HM6116I-2
min
HM61161-3
max
min
HM6116I-4
max
min
max
Unit
IRe
120
-
150
-
200
-
ns
Address Access Time
I"
-
120
-
150
-
200
ns
Chip Select Access Time
tACS
-
120
-
150
-
200
ns
Chip Selection to Output in Low Z
tCI.Z
10
-
10
-
10
-
ns
Output Enable to Output Valid
log
-
80
-
100
-
120
ns
Output Enable to Output in Low Z
tOI.Z
10
-
10
-
10
-
ns
Chip Deselection to Output in High Z
tCHZ
0
40
0
50
0
60
ns
Chip Disable to Output in High Z
tOHZ
0
40
0
50
0
.60
ns
Output Hold from Address Change
IOH
10
-
10
-
10
-
ns
Read Cycle Time
104
eHITACHI
HM61161-2, HM61161-3, HM61161-4
eWRITE CYCLE
Item
Symbol
HM6116 1-2
HM6116 1-3
HM6116 1-4
Unit
min
max
min
max
min
max
ns
Write Cycle Time
Iwe
120
-
ISO
-
200
Chip Selection to End of Write
lew
70
-
90
-
120
Address Valid to End of Write
'AW
105
-
120
140
Address Set Up Time
lAS
20
20
Write Pulse Width
Iwp
70
90
-
120
Write Recovery Time
IWR
5
-
-
-
10
-
10
-
ns
Output Disable to Output in High Z
10HZ
0
40
0
50
0
60
ns
Write to Output in High Z
twHZ
0
50
0
60
0
60
ns
Data to Write Time Overlap
low
35
-
40
-
60
-
ns
Data Hold from Write Time
10.
5
-
10
10
-
ns
Output Active from End of Write
low
5
-
-
10
-
10
-
ns
20
ns
ns
ns
ns
.CAPACITANCE (J-IMHz, Ta-25'C)
Item
Symbol
Input Capacitance
Input/Output Capacitanc.
e,.
e,,,,
typ
max
Unit
V,.-OV
3
5
pF
v,,,,-OV
5
7
pF
Test Conditions
Note) Thll parameter is sampled and not 100% tested.
• TIMING WAVEFORM
eREAD CYCLE(1)(I>,<5l
:\ddrplC!C
'"//
f-----tAl ~---+--_i
"'.t
UnUI
eREAD CYCLE (2)(1)(2)(4)
eREAD CYCLE (3)(1)(3)(4)
Doul
l.u~__l_'.1-
NOTES: l."Wlris High for Read Cycle.
2. Device is continuously selected, N = VIL.
3. Address Valid prior to or coincident with 'CS""transition Low.
4. '0£"= !JJ..
eHITACHI
105
HM6116'!-2, HM61161-3, H M 6 1 1 6 1 - 4 , - - - - - - - - - - - - - - - - - WRITE CYClE(1)
t--------,.c--------~
Address
fAil'
1-----,,;'-'11"-)_ _~
OOUI
Uin
eWRITE CYCLE(2)(5)
--------~~~-'·'---'"l~x~x~x
t--------,,·c-------oi
Address
Do.,
tONi
(8)
VOOO<
Din
NOTES: 1. A' write occurs during the overlap (tJ!P) of a low CS and a low WE
2. tWR is measured from the earlier of cs-or "WE goinghigh to the end
of write cycle.
3. During this period, I/O pins are in the output state so that the input
signals of opposite phase to the outputs must not be applied.
4. If the CS" low transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
S. "OE"is continuously low. (UP: = V/L)
6. Dout is tlte salJ1e phase of write data of this write cycle.
7. DO.lll..is the read data of next address.
8. If CS is Low during this period, I/O pins are in the output state.
Then the data input signals of opposite phase to the outputs must
. not \)eapplied to them.
106
eHITACHI
HM6116PI-2, HM6116PI-3,
HM6116PI-4 -Wide Operating Temperature Range2048-word x 8-bit High Speed Static CMOS RAM
.FEATURES
• Wide Operating Temperature Range. . . . . . . . . .. -40-+BSoC
• Single SV Supply and High Density 24 Pin Package
• High speed: Fast Access Time
120ns/150ns/200ns (max.)
• Low Power Standby and
Standby:
100llW (typ.)
Low Power Operation
Operation: 1BOmW (typ.)
• Completely Static RAM:
No clock or Timing Strobe Required
• Directly TTL Compatible: All Input and Output
• Pin Out Compatible with Standard 16K EPROM/MASK ROM
• Equal Access and Cycle Time
.FUNCTIONAL BLOCK DIAGRAM
(Dp·241
A, o----t~_ _I
\
A.
---<)Vcr
Memory Matrix
Row
Decoder
~GND
_
128X128
.PIN ARRANGEMENT
o---C:~=I
I/O,o--_~
lIOt O--ori--i
.ABSOLUTE MAXIMUM RATINGS
Item
Voltage on Any Pin Relative to GND
Symbol
Vr
Operating Temperature
'fo,r
Storage Temperature
Td •
Pr
Power Dissipation
* Pulse Width SOns. -1. 5V
Rating
Unit
-0.5° to +7.0
-40 to +85
-55 to +125
V
·C
·C
1.0
W
•
HITACHI
107
HM6116PI-2, HM6116PI·3, H M 6 1 1 6 P I - 4 - - - - - - - - - - - - - - - - - - - - - -
.TRUTH TABLE
CS
OE
WE
Mode
H
L
L
X
X
L
H
L
H
L
L
Not Selected
Read
Write
L
Vee Current
ISB9
lUI
I/O Pin
High Z
Ref. Cycle
Dout
Din
Read Cycle (IH3)
Write Cycle (1)
Din
Write Cycle (2)
Icc
Icc
Icc
Write
.RECOMMENDED DC OPERATING CONDITIONS (Ta=-40 to +8S'C)
typ
max
Unit
4.5
5.0
5.5
V
0
0
0
V
V,H
2.2
3.5
6.0
V
V/L
-1.9·
-
0.8
V
Symbol
Item
min
Vee
Supply Voltage
GND
"'put Voltage
• Pulse Width: SOns. DC:
v,,,
min- -O.3V
.DC AND OPERATING CHARACTERISTICS (Vcc -SV±10%. GNO-OV. Ta- -- 40 to +8S'C)
Symbol
Item
Test Conditions
Unit
min
typO
max
-
10
pA
10
pA
35
90
mA
30
-
mA
mA
Operating Power Supply
Icc
CS-V,L, I,,,,-OmA
Current
Ic cl "
V,H-3.5V, V,L-0.6V, I,,,,-OmA
-
Average Operating Current
IccI
Min. cycle, duty-l00%
-
35
90
Standby Power Supply
Is.
CS-V,H
-
4
20
mA
Current
Iss 1
CS;;: Vce-0.2V,
0.02
2
mA
-
0.4
V
-
V
Input Leakage Current
11.,1
Vee-5.5V, V.. -GND to Vee
Output Leakage Current
IlLol
CS- V,H or OE- V,H, V,,,,-GND to Vee
Output Voltage
•
VOL
IOL-2.1mA
VOH
IOH--1.0mA
v..;;: Vee
-0.2V or
-
v.. :.i0.2V
2.4
V(-c-5V, Ta-2S'C
•• Reference- Only
.AC CHARACTERISTICS (Vcc=SV±10%. Ta=-40 to +as'C)
eAC TEST CONDITIONS
Input Pulse Levels: O.S to 2.4V
Input Rise and Fall Times: 10 ns
I nput and Output Timing Reference Levels: 1.5V
Output Load: 1TTL Gate and CL = 100pF (including scope and jig)
eREAD CYCLE
Item
Symbol
HM6116PI-2
HM6116PI-3
min
max
min
he
120
-
t ..
-
120
tACS
-
120
Chip Selection to Output in Low Z
leLi
10
-
Output Enable to Output Valid
to.
-
80
Output Enable to Output in Low Z
tOLz
10
-
Read Cycle Time
Address
Access Time
.. .. ..
...
Chip Select Acces. Time
HM6116PI-4
Unit
max
min
150
-
200
-
-
150
-
200
ns
200
ns
150
max
ns
-
10
-
ns
100
-
120
10
-
10
-
n'
ns
10
-
Chip Deselection to Output in High Z
tCHZ
0
40
0
50
0
60
ns
Chip Disable to Output in High Z
tOHZ
0
40
0
50
0
60
ns
Output Hold from Address Chang.
tOH
10
-
10
-
10
-
ns
108
_HITACHI
- - - - - - - - - - - - - - - - - - - - - - HM6116PI-2, HM6116PI-3, HM6116PI-4
-WRITE CYCLE
Item
HM6116P[-2
Symbol
Write Cycle Time
Chip Selection to End of Write
Iwe
lew
H'd6116P[-3
HM6116P[-4
Unit
min
max
min
max
min
max
120
70
-
150
90
120
20
-
200
120
140
-
20
-
ns
90
-
-
120
10
-
0
0
60
60
60
ns
ns
ns
ns
-
ns
10
-
10
-
ns
ns
Address Valid to End of Write
Address Set Up Time
lAW
lAS
105
20
Write Pulse Width
Iwp
70
Write Recovery Time
Iwo
Output Disable to Output in High Z
Write to Output in High Z
tOHZ
5
0
0
50
Data to Write Time Overlap
Data Hold from Write Time
IDW
-
IDN
35
5
10
0
0
40
--
10
Output Active from End of Write
low
5
-
10
tWHZ
40
50
60
-
-
ns
ns
ns
.CAPACITANCE (J-IMHz, Ta-2S'C)
Symbol
Item
Input Capacitance
Input/Output Capacitance
Note) This parameter
IS
Test Ccnditions
v..-OV
v,,,,-OV
C••
CI/O
typ
max
3
5
5
7
Unit
pF
pF
sampled and not 100% tested.
• TIMNG WAVEFORM
-READ CYCLE (1)(1)
1--------'''-------01
Address
tM.
1-----to4o----+--o1
OOUI
41 READ
____t:::::::~"~"::::::::~~
,--~--~~~~~I
CYCLE (2) (1)(2) ( ' )
Address
Do.I
-READ CYCLE (3) (t)(3)(')
Dout
NOTES: 1.
2.
3_
4.
WE is High for Read Cycle.
Device is continuously selected, CS"= VILAddress Valid prior to or coincident with Ntransition Low.
UE"=!:'ll,-
•
HITACHI
109
HM6116PI-2. HM6116PI-3. HM6116PI-4 - - - - - - - - - - - - - - - -
WRITE CYCLE(1)
1--------•.< - - - - - - - - 1
Address
t----.co----i
1--_ _ _ ",."'0:.<..)- - - - I
OOUI
Oin
eWRITE CYCLE (2) (5)
Addre..
Dout
Din
NOTES: 1. A write occurs during the overlap (t~ of a low 'Nand a low~
2. tWR is measured from the earlier of cs-or 'WE" going high to the end
of write cycle.
3. During this period, 1/0 pins are in the output state so that the input
signals of opposite phase to the outputs must not be applied.
4. If the rn-low transition occurs simultaneously with the 'WE" low
transitions or after the WE transition, output remain in a high impedance state.
S. 'Ulris continuously low. (lm =VIL)
6. Dout is tlte same phase of write data of this write cycle.
7. DQJl1..is the read data of next address.
8. If CS is Low during this period, 1/0 pins are in the output state.
Then the data input signals of opposite phase to the outputs must
" - -- .
-- ..
not be 'applied to 'them.
110
•
HITACHI
HM6116FP-2, HM6116FP-3,
HM6116FP-4
2048-word x 8-bit High Speed Static CMOS RAM
.FEATURES
• High Density Small-Sized Package
• Projection Area Redueced to One-Thirds of Conventional DIP
• Thickness Reduced to a Half of Conventional DIP
• Single 5V Supply
• High Speed: Fast Access Time
120ns/150ns/200ns (max.)
• Low Power Standby
Standby:
10~W (typ.)
• Low Power Operation;
Operation: 180mW (typ.)
• Completely Static RAM:
No clock nor Timing Strobe Required
• Directly TTL Compatible: All Input and Output
• Equal Access and Cycle Time
.FUNCTIONAL BLOCK DIAGRAM
A,o----c:~=1
\
----OVec
Memory Matrix
Row
Decoder
( FP-24)
.PIN ARRANGEMENT
--<)CND
•
128X128
A,o----D~=I
Column 110
110,0---.,-1
Input
Data
Control
1/0.0--"-+-1
iVEo-----,
.ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Rating
Voltage on Any Pin Relative to GND
Vr
-0.5· to +7.0
Operating Temperature
T..,
Storage Temperature
T.~
Temperature Under Bias
'nu.
Power Dissipation
Pr
o to
Unit
V
-10 to +85
·c
·c
·c
1.0
W
+70
-55 to +125
III V,\ min - -1.5V (Pulse Wldth:i! 50ns)
.TRUTH TABLE
CS
OE
WE
Mode
Vee Current
I/O Pin
H
X
X
Not Selected
I SB, Issl
High Z
Ref. Cycle
L
L
H
Read
lee
Dout
Read Cyclell)-13)
L
H
L
Write
lee
Din
Write Cyclell)
L
L
L
Write
lee
Din
Write Cycle (2)
•
HITACHI
111
HM6116FP·2,HM6116FP-3,HM6116FP-4 - - : - - - - - - - - - - - - - - - - - - - - -
.RECOMMENDED DC OPERATING CONDITIONS (Ta-O to +70'C)
typ
max
Unit
4.5
5.0
5;5
V
0
0
0
V
V,.
2.2
3.5
6.0
V
V,L
-1.0'
-
O.S
V
Symbol
Item
min
Vee
Supply Voltqe
GND
Input Voltqe
., Pulse Width: 5Ons. DC: l'tL min--O.3V
.DC AND OPERATING CHARACTERISTICS (Vcc-5V±10%, GND-OV, Ta-O to +70'C)
Symbol
Item
Input Leakage Current
Output Leakage Current
Operating Power Supply
Current
Average Operatin, Current
Standby Power Supply
Current
IILlI
11.01
Vee-5.5V. V..-GND to Vee
CS- V,.
or OE-~.
~A>-GND
to Vee
HM6116FP-3/-4
Unit
min
typO
max
min
typO
max
-
-
10
-
-
10
pA
-
-
10
-
-
10
pA
Icc
CS- ViL. 1,,0-OmA
-
40
80
-
35
70
mA
lecl"
Vi.-3.5V, V'L-0.6V.
I",,-OmA
-
35
-
-
30
-
mA
40
SO
-
35
70
5
15
-
5
15
mA
-mA
0.02
2
-
0.02
2
mA
1ec2
Min. eyele. duty-100%
1..
CS-~N
I'll
CS;;:Vee-0.2V. ~.;;:Vec
-0.2V or V,.=>0.2V
VOL
Output Voltage
HM6116FP-2
Test Conditions
VON
-
IoL -4mA
IoL -2:1mA
IoN --1.0mA
-
-
0.4
-
-
-
V
-
0.4
V
2.4
-
-
2.4
-
-
V
., Vcc"SV. Ta-25-C
*.
Reference Onl,
.AC CHARACTERISTICS (Vcc-5V±10%, Ta-O to +70'C)
.AC TEST CONDITIONS
Input Pulse Levels: 0.8 to 2.4V
Input Rise and Fall Times: 10 ns
Input and Output Timing Reference Levels: 1.5V
Output Load: 1TTL Gate and CL ,. 100pF (including scope and jig)
.READ CYCLE
Item
Symbol
HM6116F;P-2
HM6116FP-3
min
max
min
HM6116FP-4
max
min
max
Unit
Read Cyele Time
he
120
-
150
-
200
-
I"
-
"s
Address Aeees. Time
120
150
ns
lACS
-
120
150
-
200
Chip Seleet Aee••s Time
-
200
ns
tCLZ
10
15
-
15
-
ns
Output Enable to Output Valid
10E
-
80
100
-
120
ns
Output Enable to Output in Low Z
... _-"
.. Chip Deseleetion to Output in High Z
tOLZ
10
-
15
-
15
-
ns
'CHZ
0
40
0
50
0
60
ns
Chip Disable to Output in High Z
10HZ
0
40
0
50
0
60
ns
Output Hold from Addres. Change
ION
10
-
15
-
15
-
ns
Chip
112
S.le~tion
to Output in Low Z
•
HITACHI
- - - - - - - - - - - - - - - - - - - - - - - HM6116FP-2,HM6116FP-3,HM6116FP-4
-WRITE CYCLE
Item
HM6116FP-2
Symbol
HM6116FP-3
HM6116FP-4
Unit
min
max
min
max
min
max
200
ns
20
-
ns
W rite Cycle Time
Iwe
120
-
150
Chip Selection to End of Write
lew
70
90
Address Valid to End of Write
I,w
105
120
Address Set Up Time
I"
20
-
20
-
Write Pulse Width
Iwp
70
-
90
-
120
-
W rite Recovery Time
IWR
5
-
10
-
10
-
ns
Output Disable to Output in High Z
tOHZ
0
40
0
50
0
60
ns
W rite to Output in High Z
tWHZ
0
50
0
60
0
60
ns
Data to Write Time Overlap
low
35
-
40
60
IDH
5
-
10
10
-
ns
Data Hold from Write Time
Output Active from End of Write
low
5
-
10
-
10
-
ns
120
140
ns
ns
ns
ns
.CAPACITANCE (J~lMHz, Ta~25'C)
typ
max
Unit
Input Capacitance
Symbol
C..
v..-OV
3
5
pF
Input/Output Capacitance
C,Xl
v,,,,-OV
5
7
pF
Item
Test Conditions
Note} This parameter is sampled and not 100% tested .
• TIMING WAVEFORM
-READ CYCLE (1)(1)
~-------"'--------1
,\ddrl'u
/fIIl
f-----I((,---+---1
!>(IUI
______t:::::::~"~"::::::::~
r--~------~~~~
-READ CYCLE(2)"'(2)(4)
A.ddrt'ss
I)oul
-READ CYCLE (3)(1)(3)(4)
Dout
NOTES: 1."WIris High for Read Cycle.
2. Device is continuously selected, <::s- = V/L.
3. Address Valid prior to or coincident with "C'S"trarisition Low.
4. or= V/L.
•
HITACHI
113
HM6116FP·2,HM6116FP-3,HM6116FP-4 - - - - - - - - - - - - - - - - - - - - - -
.TIMING WAVEFORM
eWRlTE CYa.E(1)(I)
t--------- •.c - - - - - - - . . . . . . j
Acldrtss
t----.,'.'----l
1-_ _ _ .",;.:(1"-)_ _01
UnUI
Usn
eWRITE CYa.E(2)'5)
!--------lu"'-------l
Address
Dout
Din
NOTES: 1. A write occurs during the overlap (tM) of a low CS' and a 10w"WE
2. tWR is measured from the earlier of CS or WE" going high to the end
of write cycle.
3. During this period, I/O pins are in the output state so that the input
signals of opposite phase to the outputs must not be applied.
4. If the 'CS'" low transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high
impedance state.
S. 'OE"is continuously low. (OE"= VIL)
6. Dout is the same phase of write data of this write cycle.
7. Do.ll1..is the read data of next address.
B. If CS -is. Low during this period, 1/0 pins.are in.the output state.
Then the data input signals of opposite phase to the outputs must
not be applied to them •
114
•
HITACHI
---------------------HM6116FP-2,HM6116FP-3,HM6116FP-4
SUPPLY CURRENT
VB. SUPPLY VOLTAGE
SUPPLY CURRENT
VB. AMBIENT TEMPERATURE
1~
1.6
T.=25'C
Vcc=5.0V
1A
]
~
./
1.2
1.0
~
,/"""
0.8
~
/
I.4
~
1.2
~
1.0
z
'"
o.6
--- --r---
6
o.4
4.5
4.75
5.0
o.4
5.5
5.25
20
40
60
ACCESS TIME
ACCESS TIME
VB. AMBIENT TEMPERATURE
vs. SUPPLY VOLTAGE
1.3
1.3
Vcc=S.ov
T«=25'C
1.2
2
..... /
1
..............
1.0
~
~
0.9
-<
0.8
,,/"
...............
..............
...............
I----
~
.
;:
0.9
<
0.8
0.7
0.7
4.5
4.75
5.0
5.5
5.25
Supply Voltage Vee (V)
V
o
20
60
40
Ambient Temperature
ACCESS TIME
VB. LOAD CAPACITANCE
SUPPLY CURRENT
VB. FREQUENCY
1.8
1.3
200nl
]
~
:l!
1A
~
;:
L
1~
1.2
1.0
80
Ambient Temperature T. ("Cl
Supply Voltage Vee (V)
/
/
V
./
80
Ta ('C)
ISOn,
120nl
1.2
/
1
T.=25'C
Vcc=MIN
9
-'!
0.8
----
0.8
o.7
O~
100
200
300
10
500
400
Frequency
Load CapacItance Q (pFl
•
HITACHI
f
(MHz)
115
HM6116CG-2, HM6116CG-3,
HM6116CG-4
2048-word x 8-bit High Speed Static CMOS RAM
• FEATURES
• Single 5V Supply and High Density 32 pin-Leadles5-Chip Carrier
• High speed. Fast Access Time
120n5/150ns/200ns (max.)
• Low Power Standby and
Standby: 100J.lW (typ.)
Operation: 180mW (tyP.)
Low Power Operation
• Completely Static RAM:
No Clock or Timing Strobe Required
• Directly TTL Compatible: All Input and Output
• Equal Access and Cycle Time
• FUNCTIONAL BLOCK DIAGRAM
(CG-32)
--oVec
\
\
Row
Decoder
•
MaInOr, Matrix
• PIN ARRANGEMENT
Ai
---OGND
•
128Xl28
•
110,0--......-1
Collum I/O
~(' ~c
t4J L~
t2j
XC
V('(
NC NC
:q 2~
~~ p~
<\II
:~:
,,"
~~
:il1
:::il!.
...
....
:n
~~!
sc
.'" :€:
[~6
WE
1m
:~~
'" 111]
~:!~
~~1
AIO
JI:
ri~
CS
Input
A,
Da..
;"
NC I~J
Control
t~i .\11
~~I I'(\.
1/0. o--t+--I
I 'ill li(hGND NC I/(l! I/f15I'(\.
(Top View)
• ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Rating
Unit
Voltege on Any Pin Relative to GND
VT
-0.5° to +7.0
Operating Temperature
Topr
o to +70
V
·C
Storage Temperature
T.,.
-65 to +150
·C
Power Dissipation
PT
1.0
W
.TRUTH TABLE
CS
H
L
L
L
116
OE
WE
X
X
L
H
L
1/0 Pin
High Z
Ref. Cycle
Dout
Din
Read Cycle (1)-(3)
Icc
Icc
Din
Mode
Not Selected
Vee Current
H
Read
Icc
L
L
Write
Write
1$8 lssl
9
_HITACHI
Write Cycle (1)
Write Cycle (2)
---------------------HM6116CG-2,HM6116CG-3,HM6116CG-4
.RECOMMENDED DC OPERATING CONDITIONS (Ta=O to +70'C)
Item
typ
max
Unit
4.5
5.0
5.5
V
0
0
0
V
Vi.
2.2
3.5
6.0
V
V/L
,-1.0'
-
0.8
V
Symbol
min
Vee
Supply Voltage
GND
Input Voltage
* Pulse Width: SOns.
DC: Vn min- -O.3V
.DC AND OPERATING CHARACTERISTICS (Vcc =5V±10%, GND-OV, Ta-O to +70'C)
Item
Input Leakage Current
Output Leakage Current
I ILl I
Ihol
Icc
HM61I6CG-2
Test Conditions
Symbol
Iccl"·
Average Operating Current
max
min
typO
max
-
-
10
-
-
10
JlA
-
-
10
-
-
10
JlA
Ve e -5.5V, V..-GND to Vee
CS- Vi. or OE- V,.,
V, ..,-GND to Vi,e
-
CS- ViL, /"'o-OmA
40
80
-
35
10
mA
-
35
-
-
30
-
I"o-OmA
mA
Min. cy.le, duty-l00%
-
40
80
-
35
10
mA
Is.
CS-V'H
-
5
15
-
5
15
mA
-
0.02
2
-
0.02
2
mA
CS<::Vcc-0.2V,
ISBI
VOL
Output Voltage
Vi.-3.5V. ViL-0.6V,
Icc!
Standby Power Supply
Current
VOH
-0.2V or
V.II~ Vee
v.. ;;OO.2V
-
-
0.4
-
V
-
-
-
-
0.4
V
2.4
-
-
2.4
-
-
V
I U I.-4mA
IOI.-2.1mA
10 , - -1.0mA
* V(,f·-SV.
.*
Unit
typO
Operating Power Supply
Current
HM61I6CG-3/-4
min
Ta-2S·C
Refennte Only
.AC CHARACTERISTICS (Vcc-5V±lO%, Ta-O to +70'C)
eAC TEST CONDITIONS
Input Pulse Levels: O.S to 2.4V
Input Rise and Fall Times: 10 ns
I "put and Output Timing Reference Levels: 1.5V
Output Load: lTTL Gate and CL = l00pF (including scope and jig)
eREAD CYCLE
Item
HM61I6CG-2
Symbol
HM61I6CG-3
max
min
120
120
min
HM61I6CG-4
max
Unit
max
min
150
-
200
-
ns
-
150
-
200
ns
120
-
15(1
-
200
ns
Read Cycle Time
hc'
Address Ac('ess Time
/AA
Chip Select Access Time
lACS
-
Chip Selection to Output in Low Z
tCLZ
10
-
15
-
15
-
ns
Output Enable to Output Valid
tOE
-
80
-
100
120
ns
Output Enable to Output in Low Z
tOLZ
10
-
15
-
15
-
ns
Chip Deselection to Output' in High Z
leHZ
0
40
0
50
0
60
ns
Chip Disable to Output in High Z
tOHZ
0
40
0
50
0
60
ns
Output Hold f rom Address Change
/0'
10
-
15
-
15
-
ns
•
HITACHI
117
HM6116CG-2,HM6116CG-3,HM6116CG-4 - - - - - - - - - - - - - - - - - - - - WRITE CYClE
Symbol
Item
Write Cycle Time
Chip Selection to End of Write
Addre.s Valid to End of Write
Address Set Up Time
Write Pulse Width
Write Recovery Time
Output Disable to Output in High Z
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
twe
tew
t.w
t.s
t ...
I ...
10HZ
tWHZ
!DIN
10.
low
HM6116CG-2
HM6116CG-3
max
min
max
min
120
70
105
20
70
5
0
0
35
5
5
-
ISO
40
50
-
-
90
120
20
90
10
0
0
40
10
10
50
60
-
HM6116CG-4
min
max
200
120
140
20
120
10
60
0
60
0
60
10
10
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
.CAPACITANCE (J-IMHz, Ta-2S'C)
Symbol
Item
Input Capacitance
Input/Output Capacitance
C..
C""
Test Conditions
VI.-OV
VI,.-OV
typ
3
5
Note) This parameter .s sampled and not 100% tested.
• TIMNG WAVEFORM
-READ CYClE (1)(1)
t--------'''-------i
Addrus
Do"
-READ CYClE (2)(1)(2) (A)
Address
Do,.
-READ CYClE (3)(I)(3)W
Oout
NOTES: 1. W1! is High for Read Cycle.
2. Device is continuously selected, 'CS'"=VIL'
3. Address Valid prior to or coincident with Ntransition Low.
4.~" VIL'
118
_HITACHI
max
5
7
Unit
pF
pF
----------------------HM6116L-2,HM6116L-3,HM6116L-4
WRITE CVQ..E(1)'1)
1--------1.'<---------1
Addu ..
1----1<0'----1
(2)
I - - - -.. P-'--~-I
UOUI
Uin
_ ________ ~l-···---··H~~~~
~
Ql
eWRITE CVQ..E(2)(5)
I--------I.'<---------t
Address
lAS
Do••
tD"~
(8)
VOOO<
Din
NOTES: 1. A write occurs during the overlap (tM> of a low 'CS and a low'WE
2. tWR is measured from the earlier ofCS-or "'WE" going high to the end
of write cycle.
3. During this period, I/O pins are in the output state 80 that the input
signals of opposite phase to the outputs must not be applied.
4. If the CS' low transition occurs simultaneously with the WE" low
transitions or after the WE transition, output remain in a high impedance state.
S. UJris continuously low. (UE =VIL)
6. Dout is t"e same phase of write data of this write cycle.
7. Dl.• ~
PT
-!O to +85
·C_
1.0
W
Item
Voltage on Any. Pin Relative to GND
Power Dissipation
*
Unit
+70
Pulse Width 50ns. -1.5V
.TRUTH TABLE
CS
OE
WE
H
X
X
L
L
L
H
L
L
L
120
I/O Pin
High Z
Ref. Cycle
Dout
Din
Read Cycle (1)-(31
Icc
Icc
Din
Write Cycle (21
Mode
Not Selected
Vee Current
H
Read
Icc
L
Write
Write
$
ISB,lssl
HITACHI
Write Cycle (11
---------------------HM6116CG-2,HM6116CG-3,HM6116CG-4
• RECOMMENDED DC OPERATING CONDITIONS (Ta-O to +70'C)
Symbol
Item
typ
max
4.5
5.0
5.5
V
0
0
0
V
V,.
2.2
3.5
6.0
V
V"
-1.0'
-
O.S
V
min
Vee
Supply Voltage
GND
Input Voltage
Unit
.. Pulse Widtb:50na, DC: V'L min--O.3V
.DC AND OPERATING CHARACTERISTICS (Vcc-5V ±10%, GND-OV, Ta-O to +70'C)
Symbol
Item
HM6116L/P-2
Test Conditions
typo
min
HM6116L1P-3/-4
max
Unit
min
typO
-
2
pA
-
2
pA
30
60
mA
25
-
mA
max
Input Leakage Current
I ILl I
Vee-5.5V, V.. -GND to Vee
-
-
2
Output Leakage Current
I fLo I
CS - V,. or OE - V,.,
V"o-GND to Vee
-
-
2
lee
~-VIL, I"o-OmA
-
35
70
lecl"
V,.-3.5V, V,,-0.6V,
ho-OmA
-
30
-
min. cycle, duty -100%
-
35
70
-
30
60
mA
4
12
-
4
12
mA
4
100
-
4
100
pA
Io,-4mA
-
-
0.4
Io,-2.1mA
-
-
-
-
Operating Power Supply
Current
Average Operating Current
Standby Power Supply
Current
Icc
2
I.B
lssl
Vo,
Output Voltage
Vo.
CS-VI.
~;;;;Vee -0.2V,
V.. Ol:Vee0.2Vor V•• :iOO.2V
Io.--1.0mA
2.4
-
-
2.4
V
0.4
-
V·
• : Vcc-5V. TII-25"C
• • : Reference Only
.AC CHARACTERISTICS (Vcc=5V ±10%, Ta=O to +70'C)
.AC TEST CONDITIONS
Input Pulse Levels: O.S to 2.4V
Input Rise and Fall Times: 10 ns
Input and Output Timing Reference Levels: 1.5V
Output Load: 1TTL Gate and CL = 100pF (including scope and jig)
.READ CYCLE
Item
HM6116L-2
Symbol
min
HM61i'6L-3
HM6116L-4
Unit
max
min
max
min
200
-
ns
-
200
ns
-
200
ns
max
Read Cycle Time
he
120
-
Address Access Time
t ..
-
120
ISO
-
Chip Select Access Time
tACS
-
120
-
ISO
ISO
Chip Selection to Output in Low Z
teLZ
10
-
15
-
15
-
ns
Output Enable to Output Valid
to.
-
SO
-
100
-
120
ns
Output Enable to Output in' Low Z
tOLZ
10
-
15
-
15
-
ns
Chip deselection to Output in High Z
tCHZ
0
40
0
50
0
60
ns
Chip Disable to Output in' High Z
10HZ
0
40
0
0
60
n.
Output Hold from Address Change
to.
10
-
15
SO
-
15
-
ns
•
HITACHI
121
HM6116L-2,HM6116L-3,HM6116L-4 - - - - - - - - - - - - - - - - - - - - - - eWRITE CYCLE
HM6116L-2
Symbol
Item
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write'
lwe
lew
',w
Addre.s Set Up Time
Write Pulse Width
Write Recovery Time
max
-
70
105
-
20
I"
Iwp
70
5
lwo
Output Disable to Output in High Z
Write to Output in High Z
min
120
HM6116L-3
HM6116L-4
Unit
min
max
min
max
150
90
120
-
200
ns
-
120
10
-"
-
20
90
10
-
120
140
20
ns
ris
ns
ns
n.
10HZ
0
40
0
50
0
60
ns
tWHZ
50
0
40
60
0
60
60
ns
ns
Data to Write Time Overlap
low
0
35
Data Hold from Write Time
lOR
5
Output Active from End of Write
low
5
-
-
10
10
-
-
10
10
ns
ns
.CAPACITANCE (j=lMHz, Ta-2S"C)
typ
max
Unit
Input Capacitance
Symbol
C ••
V•• -OV
3
5
pF
Input/Output Capacitance
C,,,O
Vl/o=OV
5
7
pF
Item
Test Conditions
Note} This parameter is sampled and not 100% tested.
• TIMING WAVEFORM
e Read Cycle (1)
(1)
Adelrt'slt
1101"
(1), (2), (of)
eRead Cycle (2)
Address
DOUI
eRead Cycle (3)
(I ), (3), (4)
Dout
f=."~-"_l_~".~
NOTES: 1. WE is High for Read Cycle.
2. Device is continuously selected, CS V lL.
3. Address Valid prior to or coincident with CS transition Low.
4. OE= V/L.
=
122
•
HITACHI
-----------------------HM6116L-2,HM6116L-3,HM6116L-4
eWrite Cycle (1)
~-------~.~------~
(I)
Addr •••
,.. (2)
-1
.... ,.;0"-)_ _
Do..
Din
(5)
eWrite Cycle (2)
Addresl
Do..
·=='.~I~(8)
~
2K>000<
_ _ _-----ir==I.
K::
Din
NOTES: 1. A write occurs during the overlap (twp) of a
low CS and a low WE.
2. tWR is measured from the earlier of CS or WE
going high to the end of write cycle.
3. During this period, I/O pins are in the output
state so that the input signals of opposite
phase ~ the outputs must not be applied.
4. If the CS low transition occurs simultaneously
with the WE low transitions. or after the WE
transition, output remain in a high impedance
state.
s. OE is continuously low. (OE =VIL)
6. Dout is the same phase of write data of this
wri te cycle.
7. D0.2V
Vee for Data Retention
VOl
Data Retention Current
IceD"·- Vcc-3.0V, CS"'2.8V, V•• ~2.8Vor V.. ::OO.2V
Chip Deselect to Data Retention Time
,.
Operation Recovery Time
•
tCDR
See Retention Waveform
min
typ
2.0
-
-
-
-
50
pA
-
ns
0
tRC··
-
max
Unit
V
ns
VIL--O.3V min.
• • IRe -
Read Cycle Time.
e Low Vee Data Retention Waveform
~,
__--__--------~~------~~~h~~~..~"'~ion~~~d.~---~r-----------___
w------------------------------------------eHITACHI
123
·HM6116L-2,HM6116L-3,HM6116L-4
SUPPLY CURRENT
SUPPLY VOLTAGE
--------------------------t"
SUPPLY CURRENT VB.
AMBIENT TEMPERATURE
VB.
1.6
1.6
Vcc=S.OV
r.=25"C
4
.--'
0.8
~
~
V
-""
--
r---d
0.8
~
"i:
~
0.6
0.6
0.4
OA
4.5
5.0
'.75
525
:---t--
5.5
o
20
.0
60
Ambient Temperature Ta
Supply Voltage Vee (V)
ACCESS TIME VB.
AMBIENT TEMPERATURE
ACCESS TIME VS.
SUPPLY VOLTAGE
3,..--
1.3
1.
Vcc=S.ov
r.=25·C
]
"ic;
z
1.2
1.1 .....
c
5
--.....
1.0
.
~
~
-............
0.9
./
r--
I
f:;
o.7
0.7
• .5
•. 75
5.0
5.5
5.25
~
20
60
40
SUPPLY CURRENT
FREQUENCY
ACCESS TIME VB.
LOAD- CAPACITANCE
1.8
VB.
200nl
.-""
/
V
V
ISOnl
120nl
\.21--~---t--+--_I_-_l
V
1A
80
Ambient Temperature Ta ("e)
Supply Voltage Vee (V)
1.0
o.9
V
0.8
0.8
1.2
V
1
~
E::
80
eel
./
I.ll--~---t--+--_I_-_l
c
~
<3
r.=25"C
Vcc=MIN
.!>
l,o'r--~--_+--~-~d.-~
L_I---ir---ij...--"
0.9'r--~--_+--~--+-~
It
Jl
0.8r--~--_+--~--+-~
0.8
o.6
0.7';;0--+---7----l-----!:--...,JI0
100
200
300
.00
500
Frequency
Load Capacitance Q. (pF)
124
•
HITACHI
I
(MHz)
-----------------------HM6116L-2,HM6116L-3,HM6116L-4
LOW INPUT VOLTAGE
SUPPLY VOLTAGE
HIGH INPUT VOLTAGE
SUPPLY VOLTAGE
VS.
1.3
VS.
1. 3
TII=25"C
T.=25"e
]
t
1.0
i
O. 9
~
~
"I
-
1
-
~
1.2
1. 1
~
t
II
1.0
~
j
o.9
~
.!i
•
.3
--
o. 7
0.7
'.5
4.75
'.5
5.5
5.25
5.0
OUTPUT CURRENT
OUTPUT VOLTAGE
Supply Voltage Vt"
OUTPUT CURRENT
OUTPUT VOLTAGE
VS.
1.2
\
~
1.0
~
d
0.1
T4=25"C
Vcc=SV
,
•
1.
··
(V I
VB.
.6
1. 6
..=:
d
o.6
..
J
/
2
\
0
\
•
o.
/
o.6
~
Output Voltage
•o
VOH
I
~
T4=25"C
Vcc=5V
V
o.
1
(V)
0.'
0.2
0.6
·
..
10·
STANDBY CURRENT
SUPPLY VOLTAGE
VB.
Vcc=3V
Cs=2.8V
.2
]
·
·
V
~
V
L
V
1.0
/
:z
V
•
.::: u.
V
/
//
b
,/'
1'a =25'("
f=~'n -n.tV
'V"
,
,
o
0.8
Output Voltage VOl. (V)
STANDBY CURRENT VS.
AMBIENT TEMPERATURE
10·
5.5
5.25
5.0
4.15
Supply Voltage Vcr (V)
~
~
o.8
0.8
]
~
II.
20
.0
60
80
.,
Supply Voltage Vee (V)
Ambient Temperaturt> Ta ('C i
•
HITACHI
125
HM6116L-2,HM6116L-3,HM6116L-4 - - - - - - - - - - - - - - - - - - - - - - STANDBY CURRENT vs.
INPUT VOLTAGE
0
Ta=2S"C
Vcc=5.0V
~=4.8V
8
6
4
2
0
0
.' -\1\
....
"-
Input Voltage V,. (V)
126
•
HITACHI
HM6116LI-2, HM6116LI-3,
HM6116LI-4
-Wide Operating Temperature Range2048-word x 8-bit High Speed Static CMOS RAM
• FEATURES
• Wide Operating Temperature Range. . . . • . . . . .. -40-+8SoC
• Single SV Supply and High Density 24 Pin Package
• High Speed: Fast Access Time
120ns/1S0ns/20Ons (max.)
• Low Power Standby and
Standby:
2Oj.tW (typ.)
Low Power Operation;
Operation: 160m W (typ.)
• Completely Static RAM:
No clock nor Timing Strobe Required
• Directly TTL Compatible: All Input and Output
• Pin Out Compatible with Standard 16K EPROM/MASK ROM
• Equal Access and Cycle Time
• Capability of Battery Back up Operation
(DG-241
• FUNCTIONAL BLOCK DIAGRAM
----<> Vcr
\
lIo,
MemDr)'
Row
~('uder
---OG~D
MatriX
•
lZ8X1211
• PIN ARRANGEMENT
o--t+--I
YiEo----,----.!±::1
.ABSOLUTE MAXIMUM RATINGS
Item
Voltage on Any Pin Relative to GND
Vr
Operating Temperature
T...
Storage Temperature
Td.
Pr
Power Dissipation
•
Symbol
Rating
-0.5· to +7.0
-40 to +85
-65 to +150
1.0
Unit
V
·c
·C
W
Pulse Width SOns. - 1.5 V
•
HITACHI
127
HM6116L1-2, HM6116LI-3,
HM6116LI-4---~----------------
• TRUTH TABLE
CS
H
OE
WE
Mode
Vee Current
X
Not Selected
ISB t /SSI
I/O Pin
High Z
Ref. Cycle
X
L
L
L
L
H
H
L
L
Read
Icc
Dout
Write
Icc
Din
Write
Icc
Din
Read Cycle 111-131
Write Cycle 111
Write Cycle (2)
L
• RECOMMENDED DC OPERATING CONDITIONS (Ta- -40 to +8S'C)
Item
Symbol
typ
max
4.5
5.0
5.5
V
0
0
0
V
V'N
2.2
3.5
6.0
V
VIL
-1.0·
-
0.8
V
min
Vee
Supply Voltage
GND
Input Voltage
•
Unit
Pulse Width:50na, DC: Va min--O.3V
.DC AND OPERATING CHARACTERISTICS (Vcc-SV ±1O%. GND-OV. Ta=-40 to +8S'C)
Symbol
Item
Test Conditions
min
typO
max
Unit
Input Leakage Current
I lu I
Vee-5.5V. V •• -GND to Vee
-
-
2
fAA
Output Leakage Current
I fLo I
CS-V'N or OE-V'N.
V,~o-GND to Vee
-
-
2
fAA
Icc
CS-VIL.
-
35
90
mA
-
30
-
rnA
-
35
90
mA
4
20
mA
4
200
fAA
Operating Power Supply
Current
[cc,··
Average Operating Current
Icc
Standby Power Supply
Current
Output Voltage
* : Vcc-5V.
Ta-25'"C
2
1,~o-OmA
V,. -3.5V. VIL-0.6V.
l,~o-OmA
min. cycle. duty -100%
Iss
CS- V'N
IS81
CS;;;'Vec -0.2V.
V •• ;;;, Vee - 0.2V or V .. :i>0.2V
-
VOL
IOL-2.lmA
-
VON
ION--1.0mA
-
2.4
0.4
V
-
V
• • : Reference Only!
.AC CHARACTERISTICS (Vcc=SV ±10%. Ta= -40 to +8S'C)
eAC TEST CONDITIONS
Input Pulse Levels: 0.8 to 2.4V
Input Rise and Fall Times: 10 ns
Input and Output Timing Reference Levels: 1.5V
Output Load: lTTL Gate and CL = 100pF (including scope and jig)
eREAD CYCLE
HM6116Li-2
Item
Symbol
HM61f6Li-3
150
-
200
-
ns
ISO
-
200
ns
120
-
200
ns
120
120
Read Cycle Time
he
I"
Chip Select Access Time
lACS
-
leLZ
10
-
10
10E
-
80
-
Output Enable to Output in Low Z
tou
10
-
Chip deselection to Output in High Z
tCHZ
0
40
Chip Disable to Output in High Z
toHZ
0
Output Hold from Address Change
10.
10
Selection~
to {)utput ~in "Low Z
Output Enable to Output Valid
128
•
150
~
~
""
-
W~
max
Unit
min
min
Address Access Time
Ckip
HM6116Ll-4
max
max
min
-
ns
120
ns
100
-
10
-
10
-
ns
0
50
0
60
ns
40
0
50
0
80
ns
-
10
-
10
-
ns
HITACHI
- - - - - - - - - - - - - - - - - - - - H M 6 1 1 6 L I - 2 . HM6116LI-3. HM6116L1-4
e WRITE CYCLE
Item
HM6116L1-2
Symbol
min
max
HM6116Ll-3
HM6116L1··4
min
max
min
max
-
200
-
Write Cycle Time
twe
120
-
150
Chip Selection to End of Write
leo
70
90
-
120
Address Valid to End of Write
I,.
-
105
120
-
140
Address Set Up Time
t,u
20
-
-
20
-
20
-
Write Pulse Width
lop
70
-
90
-
120
Write Recovery Time
lOR
5
-
10
-
Output Disable to Output in High Z
tOH~
0
40
0
Write to Output in High Z
tWH~
0
50
Data to Write Time Overlap
IDW
35
Data Hold from Write Time
I.H
5
-
Output Active from End of Write
tow
5
-
Unit
ns
ns
ns
ns
ns
10.
-
50
0
60
ns
0
60
0
60
ns
40
60
10
-
ns
10
-
10
-
10
-
ns
ns
ns
.CAPACITANCE (j=lMHz. Ta=2S'C)
Sy';bol
typ
max
Unit
Input Capacitance
Item
Co.
V.. -OV
3
5
pF
Input / Output Capacitance
C,/O
V, o-OV
5
7
pF
Note) This parameter
18
Test Conditions
sampled and not 100% tested.
• TIMING WAVEFORM
eRead Cycle (1)
0),
(5)
U<>1I1
eRead Cycle (2)
(1 h
Adduu
DaY1
(2), (4)
=F
".~ _-_-_-_-_%=~3
t::=".~,-"",
-_-_-_-_---=4=~~=
eRead Cycle (3)
Uout
~~__l_:"3NOTES: 1. WE is High for Read Cycle.
2. Device is continuously selected, CS = V/L.
3. Address Valid prior to or coincident with CS transition Low.
4. OE= VIL .
•
HITACHI
129
HM6116L1-2, HM6116L1-3, H M 6 1 1 6 U - 4 - - - - - - - - - - - - - - - - - - - -
1'-------1.'-------1
• Write Cycle (1)
Address
,•• ( l)
DOUI
Din
.Write Cycle (2)
---_--«~f=='··:;--,··]~XXX<...lL..>.
I'-------Iw'
(5)
Address
_~I'
___________-J!
--+""""'""""''"'",r--.• ( 1 ) - - - j / - t - - - - - - p
(3)
I••
Dout
Dm
_________~~~··=·=='=··~1(~8)~~
C
]OOOO(
NOTES: 1. A write occurs during the overlap (twp) of a
low CS and a low WE.
2. tWR is measured from the earlier of CS or WE
going high to the end of write cycle.
3. During this period, 1/0 pins are in the output
state so that the input signals of opposite
phase to the outputs must not be applied.
4. If the CS low transition occurs simultaneously
'With the WE low transitions or after the WE
transition, output remain in a high impedance
state.
S. OE is continuously low. (OE = VlL)
6. Dout is the same phase of write data of this
write cycle.
7. DO..\!1.is the read data of next address.
8. If CS is Low during this period, 1/0 pins are
in the output state. Then the data input
signals of opposite phase to the outputs must
not be applied to them .
• LOW Vee DATA RETENTION CHARACTERISTICS (Ta=-40 to +85·C)
Symbol
Item
Vee for Data Retention
VD.
Data Retention Current
1CCDR·
Chip Deselect to Data Retention Time
tCDR
Operation Recovery Time
I.
• VIL--O.3V min.
•
*
Test Conditions
CS<:Vcc -O.2V, V.. <: Vcc -0.2V or V.. :>O.2V
Vee-3.0V, CS<:2.8V,
V.. <:2.8Vor -0.3V:;;;V.. :iOO.2V
IRe-Read Cycle Tune.
.
See Retention Waveform
min
2.0
typ
max
-
-
-
100
0
-
IRe ••
-
-
-
• Low Vee Data Retention Waveform
Data Retention Mode
Vee
--------'""ll--------="-"====-------I , - - - - - - - -
Vo,
CS-----'
w------------------------------------------130
eHITACHI
Unit
V
JlA
n'
ns
HM6116LP-2, HM6116LP-3,
HM6116LP-4
2048-word x 8-bit High Speed Static CMOS RAM
• FEATURES
• Single 5V Supply and High Density 24 Pin Package
• High Speed: Fast Access Time
120ns/150ns/200ns (max.)
• Low Power Standby and
Standby:
10~W (typ.)
Low Power Operation;
Operation: 160mW (typ.)
• Completely Static RAM:
No clock nor Timing Strobe Required
• Directly TTL Compatible: All Input and Output
• Pin Out Compatible with Standard 16K EPROM/MASK ROM
• Equal Access and Cycle Time
• Capability of Battery Back up Operation
(Dp.24)
• FUNCTIONAL BLOCK DIAGRAM
A,
o----D~:::)
\
----0 Vee
Memory Matrix
Row
Decoder
.PIN ARRANGEMENT
---OGND
•
128X128
1/0,0---...-1
Co I UIIUII/O
Input
Data
Control
I/o.o--rl-l
WEV---"'-----=::I
.ABSOLUTE MAXIMUM RATINGS
Item
Voltage on Any Pin Relative to GND
Operating Temperature
Storage Temperature
Symbol
Rating
Unit
VT
T.,.
-0.5· to +7.0
V
·C
o to
+70
-55 to +125
T.1 6
T....
PT
Temperature Under Bias
Power Dissipation
-10 to +85
1.0
·C
·C
W
* Pulse Width 50ns: -1.5V
.TRUTH TABLE
Ref. Cycle
CS
H
OE
WE
Mode
Vee Current
X
X
Not Selected
/s8.1ssl
I/O Pin
High Z
L
L
L
H
H
L
Read
Write
lee
Do"t
Read Cycle (1)-13)
lee
Din
L
L
L
Write
lee
Din
Write Cycle 11)
Write Cycle (2)
•
HITACHI
131
HM6116LP·2,HM6116LP-3,HM6116LP-4 - - - - - - - - - - - - - - - - - - - - - -
• RECOMMENDED DC OPERATING CONDITIONS (Ta-O to +70'C)
typ
max
4.5
5.0
5.5
V
0
0
0
V
VIH
2.2
3.5
6.0
V
VIL
-1.0'
-
0.8
V
Symbol
Item
min
Vee
Supply Voltage
GND
Input Voltage
Unit
• Pulse Width: 50ns. DC: VI/. min - -O.3V
.DC AND OPERATING CHARACTERISTICS (Vcc-5V ±lO%. GND-OV. Ta-O to +70'C)
Item
Symbol
Input Leakage Current
Output Leakage Current
Vec-5.5V. V•• -GND to Vee
I fLo I
CS - VIH or OE - VIH.
VI,o-GND to Vee
Icc
CS-VIL. II'Q-OmA
Current
Icc)··
Average Operating Current
Standby Power Supply
Current
Icc
2
IUL-4mA
-
IOL-2.1mA
VI~-3.5V. VIL-0.6V.
Ilo-OmA
min. cyde. duty -100%
CS-VIH
/S81
CS;S:Vee -0.2V. V.. ~Vee0.2Vor V.. =OO.2V
VOH
: V(t
-
I SB
VOL
Output Voltage
typO
min
I ILl I
Operating Power Supply
•
HM6116LP-2
Test Conditions
IOH--1.0mA
HM6116LP-3/-4
max
min
typO
Unit
max
-
2
-
-
2
/lA
-
2
-
-
2
/lA
-
30
60
mA
25
-
mA
30
60
mA
4
12
mA
50
/lA
35
70
30
-
35
70
4
12
-
-
0.4
-
-
-
-
-
-
-
-
0.4
2.4
-
-
2.4
-
2
50
2
V
-
V
-5V. T.-25"(:
• • : Reference On.ly
• AC CHARACTERISTICS (Vcc-5V ±lO%. Ta-O to +70'C)
• AC TEST CONDITIONS
Input Pulse Levels: 0.8 to 2.4V
Input Rise and Fall Times: 10 ns
Input and Output Timing Reference Levels: 1.5V
Output Load: 1TTL Gate and CL = 100pF (including scope and jig)
.READ CYCLE
HM6116LP-2
Item
Symbol
min
HM6116LP-3
HM6116LP-4
Unit
max
min
150
-
200
-
ns
150
200
na
150
-
200
na
max
min
max
Read Cycle Time
IRe
120
-
Address Acceaa Time
fAA
-
120
Chip Select Access Time
lACS
-
120
-
Chip Selection to Output in Low Z
tCLZ
10
-
15
-
15
-
ns
Output Enable to Output Valid
tOE
-
80
-
100
-
120
ns
Output Enable to Output in Low Z
tOLZ
10
-
15
-
15
-
ns
Chip Deselection to Output in High Z
tCHZ
0
40
0
50
0
60
Chip Disable ~o Output. in II igh Z
-10HZ
0
40
{).
-50
Output Hold f rom Address Change
to.
III
-
132
•
HITACHI
15
-
0--' 15
-
60
-
ns
-
--
ris·-
ns
----------------------HM6116LP-2,HM6116LP-3,HM6116LP-4
eWRITE CYCLE
HM6116LP-2
Symbol
Item
max
min
-
150
Write Cycle Time
Chip Selection to End of Write
Iwe
120
lew
Addre •• Valid to End of Write
Addre.s Set Up Time
I"
70
105
20
I,w
Write Pulse Width
Iwp
Write Recovery Time
Output Disable to Output in High Z
IWR
tOHZ
Write to Output in High Z
tWHZ
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
HM6116LP-3
min
70
5
"
0
0
40
50
IDW
35
ID.
5
low
5
-
max
-
90
120
20
90
10
HM6116LP-4
max
200
-
ns
ns
60
60
ns
-
ns
120
140
20
120
10
0
50
0
0
60
40
-
0
60
10
10
Unit
min
10
10
ns
ns
ns
ns
ns
ns
ns
.CAPACITANCE {j-lMHz. Ta-2S"C)
Symbol
Item
C..
C, 0
Input Capacitance
Input/Output Capacitance
typ
max
Unit
V .. ~OV
3
5
pF
V,
5
7
pF
Test Conditions
0 ~OV
Note) This parameter is sampled and not 100% tested.
• TIMING WAVEFORM
eRead Cycle (1)
(I)
l)oUI
eRead Cycle (2)
(1), (21, (4)
Address
DOUI
eRead Cycle (3)
Uout
t",~__l_-3NOTES: 1.
2.
3.
4.
WE is High for Read Cycle.
Device is continuously selected, CS = VfL.
Address Valid prior to or coincident with CS transition Low.
OE= VfL.
eHITACHI
133
HM6116LP-2,HM6116LP-3,HM6116LP-4 - - - - - - - - - - - - - - - - - - - - - ~-------------,.,~--------------
e Write Cycle (1)
AcWr...
Do..
VI,
,S)
e Write Cycle (2)
Din
_______
NOTES: 1. A write occurs during the overlap (twp) of a
low CS and a low WE.
2. tWR is measured from the earlier ofCS or WE
going high to the end of write cycle.
3. During this period, I/O pins are in the output
state so that the input signals of opposite
phase!Q.. the outputs must not be applied.
4. if the CS low transition occurs simultane0!!!!x.
with the WE low transitions or after the WE
~~=~=.==~·I~(8~)~
C
S.
6.
7.
8.
%>000<
transition, output remain in a high impedance
state.
OE is continuously low. (OJ:: = VlL)
D out is the same phase of write data of this
write cycle.
D oJU. is the read data of nex t address.
If CS is Low during this period, I/O pins are
in the output state. Then the data input
signals of opposite phase to the outputs must
not be applied to them •
• LOW Vee DATA RETENTION CHARACTERISTICS (Ta-O to +70'C)
Test Conditions
min
typ
max
Vee for Data Retention
YD.
~Oi:Vee -O.ZV, V.. Oi:Vee -O.ZV or V.. liOO.2V
2.0
-
Data Retention Current
lccu*
Vee-3.0V, CS0i:2.8V, V.. 0i:2.8V or V.. liOO.2V
-
30
pA
0
-
-
ns
tile··
-
-
ns
Symbol
Item
Chip Deaele.t to Dati Retention Time
teDlt
Operation Recovery Time
II
•
See Retention Waveform
10pA max at Td-O~ to +40'C. VI/. min --O.3V
* * lit! -Read Cycle Time.
eLow Vee Data RetentIon Waveform
v" _________--. 1-________--""""'' ' 'Ro'' .' '.' ' .I'' '.,'-'Mod='________-1 ,..-_ _ _ _ __
~-------------------------------------------
134
eHITACHI
Unit
V
----------------------HM6116LP-2,HM6116LP-3,HM6116LP-4
SUPPLY CURRENT va.
AMBIENT TEMPERATURE
SUPPlY CURRENT va.
SUPPLY VOLTAGE
1.6
Vee
r.=25'C
=S.ov
1A
~
1.2
1.0
........... ~
0.8
~
V
--
r--aE 0.8
r-- r--
~
J
0.6
0.6
0.4
4.75
5.25
5.0
5.5
o
20
40
ACCESS TIME vs.
AMBIENT TEMPERATURE
ACCESS TIME vs.
SUPPLY VOLTAGE
1.3
1.3
Vcc=S.ov
r.=25'C
-
]
'iC;
1.2
2
1.1
1
..............
~
;:
3
1.0
I"........
I
.
;:
0.9
--...... r--.
1.0
I
.
f::
~
~
0.8
I
0.7
4.5
5.0
4.75
O.9
V
./
0.8
o.7
20
5.5
5.2\
-I
1.2
~
/
;:
V
.
;:
~
80
.3
1.6
~
60
SUPPLY CURRENT va.
FREQUENCY
1.8
1A
40
Ambient Temperature Til (OC)
ACCESS TIME vs.
LOAD CAPACITANCE
~
V
~
Supply Voltage Vee (V)
]
80
60
Ambient Temperature Ta (Oe)
Supply Volt_Be Vee (V)
I-""
./
200ns
IS0n.
-
I----
120n.
L2
./
.1
r.=25'C
Vcc=MIN
1.0
9
0.8
0.8
r-
o.7
0.6
100
200
300
400
10
500
Frequency
Load Capacitance CL (pF)
•
HITACHI
J
(MH~)
135
HM6116LP-2,HM6116LP-3,HM6116LP-4 - - - - - - - - - - - - - - - - - - - - - LOW INPUT VOLTAGE va.
SUPPLY VOLTAGE
HIGH INPUT VOLTAGE va.
SUPPLY VOLTAGE
1.3
1.3
T.-25"C
T,1=25"C
1.2
2
-
1
1.0
i
~
~
;
~
j
~
j
O. 9
O.9
~
O.8
O.7
4.S
us
S.o
--Supply Voha,e
va.
,
]
TII-2S"C
Vcc-Sv
]
~
1.2
\
1.0
0.8
I o.
I
1.4
E
d
i
1.2
.:
1.0
!
\
6
~
d 0.8
\
I o.
~
O.4
Output Volta.1
6
I
o.4
o
1
VOB
(V)
/
/
0.2
/
V
T.*2S-c
Vcc=5V
0.4
0.6
STANDBY CURRENT
SUPPLY VOLTAGE
.
va.
1.4
Vc:c-3V
CS=2.8V
1.2
]
----
--~
(l
~
]
~
I
~
.
10-
,
10-
/
o
_.
-
----
/'
V
~
"7
]
60
11.4
0.2
80
V"
'/
2
Supply Volt.,. Vee (V)
•
HITACHI
/
/
/V
d 0.6
~
40
/
-
0.8
i
V
20
1.0
!
Ambient Temperature To ("C)
136
0.8
Output Volta,e VaL (V)
STANDBY CURRENT va.
AMBIENT TEMPERATURE
~ W
S.S
(V)
1.6
1.4
!
.s
Vl"C
OUTPUT CURRENT v••
OUTPUT VOLTAGE
1.6
i
us
S.O
4.7S
Supply Volta,. Vee (V)
OUTPUT CURRENT
OUTPUT VOLTAGE
~
0.8
0.7
4.S
S.S
S.2S
--
1
la=25"C
S-Vcc-U.2V
-----------------------HM6116LP.2,HM6116LP.3,HM6116LP-4
STANDBY CURRENT vs.
INPUT VOLTAGE
10
Ta=2S'C
Vcc=S.OV
N=4.8V
6
2
o
o
\
"'"
......
Input Voltage V,. (V)
eHITACHI
137
HM6116LPI-2, HM6116LPI-3,
HM6116LPI-4 -Wide Operating Temperature Range2048·word x 8·bit High Speed Static CMOS RAM
.FEATURES
• Wide Operating Temperature Range ...'. . . . . . .. -40-+85°C
• Single 5V Supply and High Density 24 Pin Package
• High Speed: Fast Access Time
120ns/150ns/20Ons (max.)
• Low Power Standby and
Standby:
10~W (typ.)
Low Power Operation;
Operation: 160mW (typ.)
• Completely Static RAM: No clock nor Timing Strobe Required
• Directly TTL Compatible: All Input and Output
• Pin Out Compatible with Standard 16K EPROM/MASK ROM
• Equal Access and Cycle Time
• Capability of Battery Back up Operation
(Op·24j
• FUNCTIONAL BLOCK DIAGRAM
----0 Vee
\
Row
Decoder
Memorv Matrix
•
110,0--....-;
• PIN ARRANGEMENT
--<)GND
IZ8XIZ8
Column I/O
Input
0. ..
Control
I/o.o--H-;
.ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Voltage on Any Pin Relative to GND
VT
T...
Operating Temperature
Storage Temperature
Power Dissipation
T."
PT
Rating
-0.5* to +7.0
-40 to +85
-55 to +125
1.0
Unit
V
·c
·C
W
* Pul.~ Width 50ns : -1.5 V
138
•
HITACHI
----------------------HM6116LPI-2.HM6116LPI-3.HM6116LP1-4
• TRUTH TABLE
CS
OE
WE
H
X
X
L
L
L
L
H
H
L
L
L
Mode
Not Selected
Vee Current
Read
Icc
Icc
Icc
Isa.1sBI
Write
Write
I/O Pin
High Z
Ref. Cycle
Dout
Read Cycle (I)-13)
Din
Write Cycle 11)
Write Cycle (2)
Din
• RECOMMENDED DC OPERATING CONDITIONS (Ta- -40 to +8S'C)
Symbol
typ
max
4.5
5.0
5.5
V
0
0
0
V
V'H
2.2
3.5
6.0
V
V"
-1.0·
-
0.8
V
Item
Supply Voltage
GND
Input Voltage
•
min
Vee
Unit
Pulse Width: SOns, DC: V/L min - -O.3V
.DC AND OPERATING CHARACTERISTICS (Vcc-SV ±1O%. GNO-OV. Ta=-40 to +8S'C)
Symbol
Item
Input Leakage Current
Output Leakage Current
Test Conditions
min
typO
Vee-5.5V. V .. -GND to Vee
-
-
I ILl I
I fLo I
CS-V'H or OE-V,H. V"o-GND to Vee
Icc
CS- V". I"o-OmA
Operating Power Supply
Current
[CCI"
V'H -3.5V. V,,-0.6V. I"o-OmA
Average Operating Current
Icc
min. cycle. duty -100%
Standby Power Supply
Is.
Current
Output Voltage
* : Vc(-5V.
2
Issl
CS-V'H
CS;'; Vee -0.2V. V.. ", Vee -0.2V or V .. :S;0.2V
VOL
IOL-2.lmA
VOH
IOH--1.0mA
max
Unit
2
pA
2
pA
90
rnA
rnA
-
35
-
30
-
35
90
mA
4
20
mA
2
100
pA
0.4
V
-
V
2.4
-
Ta-2S·C
• * : Reference Only
.AC CHARACTERISTICS (Vcc=5V ±10%. Ta--40 to +85'C)
eAC TEST CONDITIONS
Input Pulse Levels: O.B to 2.4V
Input Rise and Fall Times: 10 ns
Input and Output Timing Reference Levels: 1.SV
Output Load: 1TTL Gate and CL = 100pF !including scope and jig)
eREAD CYCLE
HM6II6LPI -2
Item
Symbol
min
HM6II6LPI -3
max
min
HM6II6LPI-4
max
min
max
Unit
Read Cycle Time
he
120
-
150
-
200
-
ns
Address Access Time
/AA
-
120
150
ns
tACS
-
120
150
-
200
Chip Select Access T i';'e
-
200
ns
Chip Selection to Output in Low Z
feLZ
10
-
10
-
10
-
n.
Output En'able to Output Valid
tOE
-
80
-
100
-
120
ns
Output Enable to Output in Low Z
tOLZ
10
-
10
-
10
-
n.
Chip Deselection to Output in High Z
tCHZ
0
40
0
50
0
80
ns
Chip Disable to Output in High Z
10HZ
0
40
0
50
0
60
ns
Output Hold from Address Change
/OH
10
-
10
-
10
-
ns
•
HITACHI
139
HM6116LPI-2,HM6116LPI-3,HM6116LPI-4 - - - - - - - - - - - - - - - - - - - - eWRITE CYCLE
HM6116LPI-2
max
Symbol
Item
Write Cycle Time
Iwe
min
120
Chip Selection to End of Write
lew
70
Address Valid to End of Write
Address Set Up Time
IA.
105
lAS
20
Write Pulle Width
Write Recovery Time
Iwp
70
5
Output Disable to Output in High Z
tOHZ
Iwo
0
Write to Output in High Z
tWHZ
Dota to Write Time Overlap
IDw
35
Dota Hold from Write Time
IDN
Output Actiye from End of Write
low
5
5
0
-
-
40
50
-
HM6116LPI-3
min
max
-
ISO
90
120
-
20
90
HM6116LPI-4
min
200
20
-
SO
0
0
60
0
60
10
10
10
-
10
-
120
10
0
-
-
-
120
140
10
40
max
60
60
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
.CAPACITANCE (J-IMHz. Ta-2S·C)
typ
max
Unit
Input Capacitance
C..
V•• -OV
3
5
pF
Input/Output Capacitance
C'"O
V/,o-OV
5
7
pF
Symbol
Item
Test Conditions
Note} This parameter i, eampled and not 100% tested•
• TIMING WAVEFORM
eRead Cycle (1)
(I)
Addrf'1III
Unul
(I>t (2), (4)
eRead Cycle (2)
Dou.
eRead Cycle (3)
=E;. ~_t~I.'~
(I), (3), (4'
OOUI
L".~__l_"1NOTES: 1. WE is High for Read Cycle.
2. Device is continuously selected, CS = V/L.
3. Address Valid prior to or coincident with CS transition Low.
4. OE= V/L.
140
•
HITACHI
- - - - - - - - - - - - - - - - - - - - H M 6 1 1 6 L P I - 2 , HM6116LPI-3, HM6116LPI-4
t-------I.C'-------i
• Write Cycle (1)
Address
liE
cs
WE
Do.,
Din
_______________ ~J:~'"-.----'••-~~~~
0.2V
-
4
12
-
4
12
rnA
rnA
-
2
SO
-
2
50
J'A
0.4
-
-
-
-
0.4
2.4
-
-
CS-VII., It II-OmA
V'H-3.5V, V/L-0.6V,
[, o-OmA
VOL
IOL-2.1mA
VON
-
3S
70
-
30
-
-
1cn=4mA
*' : Vrr-5V.
min
/('('2
Issl
Output Voltage
HM6116LFP-3/-4
max
[S8
Icc,··
Current
min
-
lee
Current
Average Operating Current
HM6116LFP-2
Test Conditions
IOIl--l.OmA
2.4
-
-
V
V
Ta-2S"C
• • : Reference Onl)'
.AC CHARACTERISTICS (Vcc=5V±10%. Ta=O to +70'C)
.AC TEST CONDITIONS
Input Pulse Levels: 0.8 to 2.4V
Input Rise and Fall Times: 10 ns
Input and Output Timing Reference Levels: 1.5V
Output Load: 1TTL Gate and CL = 100pF !including scope and jig)
.READ CYCLE
HM6116LFP-2
Symbol
Item
min
max
HM6116LFp..3
HM61\6LFP-4
max
min
max
-
200
-
ns
Unit
Read Cycle Time
he
120
-
min
150
Address Access Time
lAA
-
120
-
150
200
ns
Chip Select Access Time
lACS
-
120
-
-
150
-
200
ns
tCLZ
10
-
15
-
15
-
n.
Output Enable to Output Valid
10£
-
80
-
100
120
ns
Output Enable to Output in Low Z
tOLZ
10
-
15
-
15
-
ns
Chip deselection to Output in High Z
ICHZ
0
40
0
50
0
60
ns
Chip Disable to Output in High Z
10HZ
0
40
0
50
0
60
ns
Output Hold from Address Change
ION
10
-
15
-
15
-
ns
Chip Selection to Output in
Lo~'
Z
•
HITACHI
-
143
HM6116LFP·2,HM6116LFP-3,HM6116LFP-4 - - - - - - - - - - - - - - - - - - - eWRITE CYCLE
HM6116LFP-2
Symbol
Item
Write Cycle Time
Iwe
Chip Selection to End of Write
Address Valid to End of Write
lew
Address Set Up Time
Write Pulse Width
lAS
Iwp
20
70
Write Recovery Time
Output Disable to Output in High Z
Iwo
5
0
0
35
10HZ
Write to Output in High Z
Data to Write Time Overlap
tWHZ
low
10.
Data Hold from Write Time
Output Active from End of Write
-
70
105
lAW
5
5
low
HM6116LFP-3
min
max
max
min
120
-
150
90
HM6116LFP-4
Unit
min
max
200
120
-
ns
ns
ns
ns
ns
ns
-
120
20
-
-
90
10
-
40
50
0
0
50
60
0
0
60
60
-
40
10
-
60
10
10
-
10
-
140
20
120
10
ns
ns
ns
ns
ns
.CAPACITANCE (J-IMHz, Ta-2S"C)
Input Capacitance
Symbol
Cin
Test Conditions
Vin-OV
Input/Output Capacitance
e,
V, o-OV
Item
0
typ
max
3
5
5
7
Note) This parameter is sampled and not 100% tested.
.TIMING WAVEFORM
e READ CYCLE (1)(\)
Addr, ..
1M.
till I
t - - - - - t u ,---+---1
I.r---~----~~~~~I
______t:::::::~"~"::::::::~
UuUI
e READ CYCLE (3)(1)(3"4)
Address
DoU!
eREAD CYCLE (2}(I)(2)W
~-~.tA(.'
.,-------------------_
(t( . ~.
. .t:=tl'l.Z
DOllt
----
NOTES: 1. W£ is High for Read Cycle
2. Device is continuously selected,
~ VIL
3. Address Valid prior to or coincident with CS
transition Low.
cs
4.00=
144
VIL'
•
HITACHI
Unit
pF
pF
-------------------------------------HM6116LFP-2.HM6116LFP-3.HM6116LFP-4
eWRITE CYCLE (1)
....
D.
'"
eWRITE CYCLE (2)
Iw<
Addr...
I ..
I,•
....
_(_(________________~r_-.W-----'-..-~~('l~~~~
K...
¥>()(
Om
NOTES: 1. A write occurs during the overlap (twp)' of a
low CS and a low WE.
2. tWR is measured from the earlier of CS or WE
going high to the end of write cycle.
3. During this period, I/O pins are in the output
state so that the input signals of opposite
phase to the outputs must not be applied.
4. If the CS low transition occurs simultaneously
with the WE low transitions or after the WE
transition, ou tpu t remain in a high impedance
state.
S. OE is continuously low. (OE = VIL)
6. Dout is the same phase of write data of this
write cycle.
7. DOJli is the read data of next address.
8. If CS is Low during this period, 1/0 pins are·
in the output state. Then the data input
signals of opposite phase to the outputs must
not be applied to them.
.LOW Vee DATA RETENTION CHARACTERISTICS (Ta-O to +70'C)
Item
Vee for Data Retention
Symbol
V.R
Data Retention Current
IccDR
Chip Deselect to Data Retention Time
tCDR
Operation Recovery Time
h
Test Conditions
CS;;:Vee-0.2V
V,N;;: Vee-0.2V or VIN:iOO.2V
.
Vce-3.0V. C'S;;:2.8V
VIN:i<2.8V or V'N:<:0.2V
See Retention Waveform
typ
max
2.0
-
-
-
-
30
pA
-
ns
min
0
··lRc
-
-
Unit
V
n8
• V,I. min--O.3V, 10pA max (at Ta-O to +40'"C)
IRe-Read Cycle Time.
**
eLow Vee DATA RETENTION WAVEFORM
v" _ _ _ _ _ _ _...., f-~____~O'e!.."'Re"'."''"''',;'''''"'''M~,''''d.'___ _ _---I
~tt
r--------
VD.-O.2V
cs ___...J
w- _________________________________________ _
•
HITACHI
145
HM6116K-3, HM6116K-4
2048-word x 8-bit High Speed Static CMOS RAM
• FEATURES
• Industrial Temperature Range . . . . . . . . . . . . . . 55 to +125°C
• Single 5V Supply and High Density 24 Pin Package
• High speed: Fast Access Time 150ns/200ns (max.)
• Low Power Standby and
Standby: 100/lW (type.)
Low Power Operation
Operation: 180mW (typ.)
• Completely Static RAM: No clock or Timing Strobe Required
• Directly TTL Compatible: All Input and Output
• Pin Out Compatible with Standard 16K EPROM/MASK ROM
• Equal Access and Cycle Time
(DG-24)
• FUNCTIONAL BLOCK DIAGRAM
• PIN ARRANGEMENT
- - 0 Vee
\
Row
Decoder
•
Memory Matrix
----OCND
•
128X!28
•
•
110,0--....,.-;
Column 110
Input
Dat.
Control
i/O.
o--rl-;
".
".
".
At.
(Top View)
WE o---"L-!:±::t
.ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Rating
Voltage on Any Pin Relative to GND
VT
-0.5· to +7.0
V
Operating Temperature
T."
-55 to +125
·C
Storage Temperature
T".
-65 to +150
·C
Power Dissipation
PT
1.0
W
Unit
• Pulse Width 50ns: -1.5V
.TRUTH TABLE
CS
OE
WE
Mode
H
X
X
Not Selected
L
L
H
Read
Icc
Dout
L
H
L
Write
Icc
Din
Write Cycle (1)
L
L
L
Write
Icc
Din
Write Cycle (21
146
Vee Current
Is B•
•
1881
HITACHI
I/O Pin
Ref. Cycle
High Z
Read Cycle (11-(31
---------------------------------------------------HM6116K-3,HM6116K-4
• RECOMMENDED DC OPERATING CONDITIONS (Ta= 0 to +70·C)
Item
Symbol
typ
max
Unit
4.5
5.0
5.S
V
0
0
0
V
Vi.
2.2
3.5
6.0
V
V,.
-1.0'
-
0.8
V
min
Vee
Supply Voltage
GND
Input Voltage
.. Pulse Width: SOns, DC: V/L ••• --O.3V
.DC AND OPERATING CHARACTERISTICS (Vcc=5V±10%, GND-OV, Ta=-55-+125·C)
min
typO
max
Unit
I ILl I
Vee-5.5V, V..-GND to Vee
-
-
10
pA
I ho I
CS- V,. or OE- V,.,
Vi/o-GND to Vee
-
-
10
,.,A
Icc
CS-V'L, Il/o-OmA
-
35
90
mA
Vi.-3.5V, V,.-0.6V,
-
30
-
mA
Symbol
Item
Input Leakage Current
Output Leakage Current
Test Conditions
Operating Power Supply
Current
Iccl"
Average Operating Current
Il/o-OmA
lecl
Min. cyele, duty-l00%
-
35
90
mA
IS8
CS-V'H
-
4
20
mA
1SBI
CS;;;:Vee-0.2V, Vi .. ;;;:; Vee
-0.2V or V,.::;;0.2V
-
0.02
2
mA
VOL
I oL-2.1mA
-
-
0.4
V
VOH
I oH --1.0mA
2.4
-
-
V
Standby Power Supply
Current
Output Voltage
.. Vcc -5V. To-2S·C
*.
Reference Only
.AC CHARACTERISTICS (Vcc -5V±10%, Ta=-55 to +125·C)
• AC TEST CONDITIONS
Input Pulse Levels: O,S to 2.4V
Input Rise and Fall Times: 10 ns
Input and Output Timing Reference Levels: 1.5V
Output Load: 1TTL Gate and CL = 100pF (including scope and fig)
.READ CYCLE
HM6116K-3
HM6116K-4
Symbol
Item
Unit
min
max
min
max
-
200
-
ns
Read Cycle Time
he
150
Address Access Time
I ..
-
150
-
200
n.
Chip Select Access Time
lACS
-
150
-
200
n.
leu
10
-
10
-
n.
Output Enable to Output Valid
10E
-
100
-
120
n.
Output Enable to Output in Low Z
lou
10
-
10
-
n.
Chip De.election to Output in High Z
tCHZ
0
50
0
60
n.
Chip Disable to Output in High Z
tOHZ
0
50
0
60
n.
Output Hold from Address Change
ION
10
-
10
-
ns
Chip Selection to Output in Low
'z
•
HITACHI
147
HM6116K-3,HM6116K-4 - - - - - - - - - - - - - - - - - - - - - - - - - - - WRITE CYCLE
HM6116K-3
Symbol
Item
HM6116K-4
min
max
min
max
Unit
W rite Cycle Time
Iwe
150
-
ns
tew
90
-
200
Chip Selection to End of Write
120
-
ns
Address Valid to End of Write
tAW
120
-
140
-
ns
Address Set Up Time
lAS
20
20
-
ns
Write Pulse Width
twp
90
120
-
ns
W rite Recovery Time
IWR
10
-
10
-
ns
Output Disable to Output in High Z
tOHZ
0
50
0
60
ns
W ri te to Output in High Z
tWHZ
0
60
0
60
ns
Data to Write Time Overlap
tDW
40
-
60
ns
Data Hold from Write Time
IDR
10
-
10
Output Active from End of Write
tDW
10
-
10
-
ns
ns
.CAPACITANCE (f-lMHz, Ta-25'C)
Symbol
Item
Input Capacitance
C..
Input/Output Capacitance
Cl/ D
Test Conditions
v..-OV
v,,,,-OV
typ
max
3
5
7
5
Note) This parameter is sampled and not 100% tested.
• TIMING WAVEFORM
-READ CYCLE (1)(1)
,-\ddrE'ss
I'lt
If"~
r-----tAO---+---l
______t:::::::~"~"::::::::~
r----~----~~~~
-READ CYCLE (2)(1)(2) (')
Address
Dout
~."=:a-_l_'"1-
NOTES: 1.
2.
3.
4.
148
WE is High for Read Cycle.
Device is continuously selected, CS"= VlL.
Address Valid prior to or coincident with ~t~ansition Low.
'OE= V/L'
eHITACHI
Unit
pF
pF
--------------------------HM6116K-3,HM6116K-4
WRITE CYCLE(1)
~-------------I.'~--------------~
Address
1-------".----1
t-___ ".''-U''-J_ _-i
Uin
eWRITE CYCLE(2)'"
Addre..
Dout
Din
NOTES: 1. A write occurs during the overlap (tJl!.f) of a low Nand a low"w'
2. tWR is measured from the earlier of cror W going high to the end
of write cycle.
3. During this period, I/O pins are in the output state so that the input
signals of opposite phase to the outputs must not be applied.
4. If the CS' low transition occurs simultaneously with the W low
transitions or after the WE transition, output remain in a high impedance state.
S. tlE"is continuously low. (OF: VIL)
6. Dout is t1:le same phase of write data of this write cycle.
7. Dc128
(DP-24A)
I/O, o--ff'[)--~
.PIN ARRANGEMENT
I/O'-r--j-+-£>+--L_
A.
I
24
Vee
13
110.
B--~~=t~~---------,
wr---H~~
O£--~~:=LJ--~
.ABSOLUTE MAXIMUM RATINGS
Item
Voltage on Any Pin Relative to GND
Symbol
Rati",
Unit
V,
-0.5· to +7.0
o to +70
-55 to +125
-10 to +85
\.0
V
·C
Operating Temperature
T.,.
Storage Temperature
T...
Temperature Under Bias
T.".
Power Dissipation
p,
·C
·c
W
(Top View)
• Pullf' Width SOns: -1.5V
.TRUTH TABLE
150
CS
OE
WE
--
-Mode
H
X
x
Not Selected
L
L
L
L
H
L
H
L
L
Write
Write
Vee Current
Read
•
Iss. 1511
ler
1/0 Pin
High Z
Ref. Cycle
Dout
Read Cycle 1\)-131
icc
Din
Write Cycle 111
Icc
Din
W rite Cycle 121
HITACHI
----------------HM6116AP-10,HM6116AP-12,HM6116AP-15,HM6116AP-20
HM6116ASP-10,HM6116ASP-12,HM6116ASP-15,HM6116ASP-20
.RECOMMENDED DC OPERATING CONDITIONS (To-O to +70'C)
Item
Symbol
typ
max
Unit
4.5
5.0
5.5
V
0
0
0
V
11,.
2.2
3.5
6.0
V
V"
-\.0·
-
0.8
V
min
Vee
Supply Volta,.
GND
Input Volta,.
•
Pul.~
Wldlh : SOna. DC: V,L nun -
O. 3V
.DC AND OPERATING CHARACTERISTICS (Vcc =5V±10%. GND-OV. To-O to +70'C)
Item
Symbol
Test Conditions
HM6116AP/ASp·IO
HM6116AP/ASP·12
HM6116AP/ASP·IS
HM6116AP/ASP-20
min
typ·
max
min
typ·
max
min
typ·
max
min
typ·
max
Unit
Input Leakage
Current
I ILl I
Vc c=5.5V, Vin=GND
to Vcc
-
-
2
-
-
2
-
-
2
-
-
2
p.A
Output Leak...
Current
Ihol
CS= V1H or OE= V1H•
VIIO=GND to Vcc
-
-
2
-
-
2
-
-
2
-
-
2
p.A
Icc
CS= VIL.ll/o=OmA
Yin= VIR or Va
-
5
IS
-
5
15
-
5
IS
-
5
IS
rnA
Icci
VIH=VCC. VIL=OV,
CS=VIL •
Il/o=OmA,f=IMHz
-
3
6
-
3
6
-
3
6
-
3
6
rnA
min. cycle, duty=IOO%
-
40
70
-
35
60
-
25
45
-
20
35
rnA
-
I
4
-
I
4
-
I
4
-
I
4
rnA
ISBI
tcs;vlH
CS~ Vcc -0.2V
0,02
2
2
-
0.02
2
-
0.02
2
rnA
IOL=4mA
-
0.4
-
0.02
VOL
VOH
-
-
0.4
-
-
0.4
-
-
0.4
V
IOH=-1.0mA
2.4
-
-
2.4
-
-
2.4
-
-
2.4
-
-
V
Operating Power
Supply Current
Average Operating
Current
ICC2
ISB
Standby Power
Supply Current
Output Voltage
*
.'
VCC=5V, Ta=25°C
.AC CHARACTERISTICS (Vcc -5V±10%. Ta=O to +70'C)
.AC TEST CONDITIONS
Input Pulse Levels: 0.8 to 2.4V
Input Rise and Fall Times: 10 ns
Input and Output Timing Reference Levels: 1.5V
Output Load: lTTL Gate and CL = 100pF (including scope and jig)
.READ CYClE
1Iem
Symbol
H~li.~rJ
min
H~li.W/
max
min
HMlli.W'
max
min
HM6116APJ
ASP·20
max
min
max
Unit
Read Cycle Time
tRC
100
-
120
-
150
-
200
-
ns
Address Access Time
tAA
-
-
-
ISO
ISO
-
200
200
ns
tACS
120
120
-
Chip Select Access Time
100
100
Chip Selection to Output in Low Z
tCLZ
10
-
ns
Output Enable to Output Valid
Output Enable to Output in Low Z
tOE
tOLZ
ns
ns
Chip Deselection to Output in High Z
tCHZ
Chip
Di~able
to Output in High Z
Output Hold from Address Change
tOHZ
tOH
•
-
-
10
-
10
-
55
-
60
-
70
10
0
0
10
-
10
0
0
15
-
10
0
0
20
-
-
10
-
50
10
0
0
10
40
40
-
-
HITACHI
40
40
-
SO
50
-
ns
60
60
ns
-
ns
ns
151
HM6116AP·10,HM6116AP·12,HM6116AP·15,HM6116AP·20 - - - - - - - - - - - - - - - - - ' - HM6116ASP·10,HM6116ASp·12,HM6116ASp·15,HM6116ASP·20
eWRlTE CYCLE
HM6116AP/
ASP-IO
Symbol
Item
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Set Up Time
Write Pulse Width
Write Recovery Time
Output Disable to Output in High Z
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
twe
tew
tAW
tAS
twp
tWR
tOHZ
tWHZ
tDW
tDH
tow
max
min
100
6S
80
0
60
0
0
0
30
0
10
-
120
70
lOS
0
70
0
0
0
3S
0
10
-
-
40
30
-
-
H~Ji.ftPI
HM6116AP/
ASN2
min
HM6116AP/
ASP-20
max
min
max
min
max
-
ISO
90
120
0
80
0
0
0
40
0
10
-
200
120
140
0
100
0
0
0
SO
0
10
-
-
-
-
40
3S
-
-
-
-
SO
40
-
-
-
-
60
SO
-
-
.CAPACITANCE (J-IMHz, Ta-25·C)
Symbol
Item
Input Capacitance
Input/Output Capacitance
C,.
C"O
Test Conditions
I
I v..-OV .
I v,,,,-OV
typ
3
5
max
5
7
Note} This parameter is sampled and not 100% tested.
.TIMING WAVEFORM
eREAD CYCLE (1)(1)
Address
~------tAes----~--~
Dout
_ __-1====~t£eL~Z~==~
r-~--~~~~
eREAD CYCLE(2)(I)(2"')
tRe
----.1
Address
-JI\
E-
,
~tOH
tA
I = *:
~tOH3<
Dout
eREAD CYCLE(3)(I)(3",)
NOTES: I. W£"is High for Read Cycle.
2. Device is continuously selected, N .. VIL.
3. Address Valid prior to or coincident with Ntransition Low.
4. mr.. VIL.
152
•
HITACHI
Unit
pF
pF
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
- - - - - - - - - - - - - - - - HM811 8AP·10,HM8118AP·12,HM8118AP·15,HM811 8AP·20
HM811 8ASp·1 O,HM6116ASP·12,HM611 8ASP·15,HM6116ASP·20
-WRITE CYCLE(1)
Address
twp·!,.ll--,I---I
Dout
_____________
Din
~-1:+r_tD_w--_t_D_H_~~~~~
twe
Address
....-~""~~~I----tew---t:=;~!,.-~~~~
CS
-J~~::~~~~~(.~)~::::::::::~4-1I~~-L-L~~-
Din
-------------------~
GOO<
NOTES: I. A write occurs during the overlap (t..ll'.f) of a low ~ and a 10w"WE".
2. t WR is measured from the earlier of cr or WE' going high to the end
of wri te cycle.
3. During this period, 1/0 pins are in the output state so that the input
signals of opposite phase to the outputs must not be applied.
4. If the CS" low transition occurs simultaneously with the WE' low
transitions or after the WE transition, output remain in a high impedance state.
S. UE'is continuously low. (OE = VIL)
6. Dout is tlte same phase of write data of this write cycle.
7. DCUIl.is the read data of next address.
8. If CS is Low during this period, 1/0 pins are in the output state.
Then the data input signals of opposite phase to the outputs must
not be applied to them .
•
HITACHI
153
HM6116ALP-10, HM6116ALP-12,
HM6116ALP-15, HM6116ALP-20,
HM6116ALSP-10, HM6116ALSP-12,
HM6116ALSP-15, HM6116ALSP-20
2048-word x 8-blt High Speed Static CMOS RAM
• FEATURES
HM6116ALPSeries
• High Speed: Fast Access Time 100ns/120ns/150ns/200ns (max.)
• Low Power Standby and
Standby:
5jJ.W (typ.)
10mW (typ.) (f = 1MHz)
Low Power Operation;
Operation:
• Capability pf Battery Back up Operation
• Single 5V Supply and High Density 24 Pin Package
• Completely Static RAM: No clock nor Timing Strobe Required
• Directly TTL Compatible: All Input and Output
• Pin Out Compatible with Standard 16K EPROM/MASK ROM
(DP-Z4l
• Equal Access and Cycle Time
HM6116ALSP Series
• FUNCTIONAL BLOCK DIAGRAM
··-~=rl
)
,,, <>---t-~=:::::J
(DP-24M
I/O •. <>---rl-.[)---i
• PIN ARRANGEMENT
~~c-~=t--t:----------------~
M
)i
I
24
Vee
I
WE <>---+11)1--1
0E.~----~---4-r-----
.ABSOLUTE MAXIMUM RATINGS
Item
Volt ... on Any Pin Relative to GND
Oper.tinl Temperature
Stor..e Temperature
Temperature Under Bia.
Power Di.sipation
Symbol
Ratilll
·-0.5· to +7.0
Vr
o to +70
-55 to +125
-10 to +85
1.0
T•••
T..,
T....
Pr
Unit
V
·c
·c
·c
W
(Top View)
• Pul.. Wid'" SO .. : -1.5V
..• TRUTH
TABLE------
154
-.-~-
-_
DE
WE
x
x
L
L
L
L
H
L
H
L
L
CS
H
..
~
.....
- ---
Mode
Not Selected
Read
Write
Write
•
Vee Current
111,1,,1
Icc
Icc
Icc
HITACHI
I/O Pin
Hip Z
Ref. Cycle
Dout
Din
Din
Read Cycle (1)-(3)
Write Cycle (l)
Write Cycle (2)
- - - - - - - - - - - - - - - H M 6 1 1 6 A L P - 1 O,HM6116ALP-12,HM6116ALP-15,HM6116ALP-20
HM6116ALSP-1 O,HM6116ALSP-12,HM6116ALSP-15,HM6116ALSP-20
.RECOMMENDED DC OPERATING CONDITIONS (Ta-O to +70·C)
typ
max
Unit
4.5
5.0
5.5
V
0
0
0
V
V,.
2.2
3.5
6.0
V
V"
-1.0·
-
0.8
V
Symbol
Item
min
Vee
Supply Voltage
GND
Input Voltage
• Pulse Width: SOns. DC: VlL min - -O.3V
.DC AND OPERATING CHARACTERISTICS (Vcc=5V ±10%. GND=OV. Ta-O to +70·C)
Symbol
Item
HM6116ALPI
ALSP·)O
min typO max
Test Conditions
Hr.~m:,w'
H~mw'
min
typO
max
min
typO
max
HM6116ALPI
ALSP-20
min typO max
Unit
Inpu t Leakage
Current
I ILl I
Vcc=S.SV. Vln=GND
to Vcc
-
-
2
-
-
2
-
-
2
-
-
2
I'A
Ou tput Leakage
Current
IILOI
CS= VIH or OE= VIH.
Vl/o=GND to Vcc
-
-
2
-
-
2
-
-
2
-
-
2
!AA
Icc
CS=VIL. hIO=OmA
V'n=VIH or V/L
-
4
12
-
4
12
-
4
12
-
4
12
rnA
ICCI
VIH=VCC. VIL=OV.
CS=V6L •
hlO= mA.f=IMHz
-
2
5
-
2
5
-
2
5
-
2
5
rnA
ICC2
min. cycle, duty=IOO% -
35
60
-
30
50
-
20
40
-
IS
30
rnA
ISB
CS= VIH
3
3
3
3
rnA
I
50
I
50
-
0.5
SO
-
0.5
I
-
0.5
CS ~ Vcc -0.2V
-
0.5
ISB]
1
SO
/loA
VOL
IOL=4mA
-
0.4
-
-
-
0.4
-
-
0.4
V
IOH=-1.0mA
-
2.4
-
0.4
VOH
-
-
2.4
-
-
2.4
-
-
V
Operating Power
Supply Current
Average Operating
Current
Standby Power
Supply Current
Output Voltage
2.4
* : VcC=5V, To=25°C
.AC CHARACTERISTICS (Vcc=5V ±10%. To-O to +70·C)
e AC TEST CONDITIONS
Input Pulse Levels: 0.8 to 2.4V
Input Rise and Fall Times: 10 ns
Input and Output Timing Reference Levels: 1.5V
Output Load: 1TTL Gate and CL - 100pF (including scope and jig)
eREAD CYCLE
Item
Symbol
HM6116ALPI
ALSP·)O
max
min
100
100
HM6116ALPI
ALSP-12
min
max
HM6116ALPI
ALSP-IS
HM6116ALPI
ALSP-20
min
max
min
120
150
150
150
60
-
200
-
ns
-
200
200
ns
Read Cycle Time
IRC
Address Access Time
tAA
100
-
Chip Select Access Time
tACS
-
Chip Selection to Output in Low Z
tCLZ
10
-
10
Output Enable to Output Valid
tOE
-
-
Output Enable to Output in Low Z
tOLZ
Chip Deselection to Output in High Z
tCHz
Chip Disable to Output in High Z
tOHZ
10
0
0
Output Hold from Address Change
tOH
10
0
0
10
50
40
40
120
120
55
40
40
-
10
-
•
-
HITACHI
10
10
0
0
15
SO
SO
-
Unit
max
ns
10
-
ns
-
70
ns
10
0
0
20
-
ns
60
60
ns
-
ns
ns
155
HM6116ALP·10,HM6116ALP·12,HM6116ALP·15,HM6116ALP·20 - - - - - - - - - - - - - HM6116ALSP·10,HM6116ALSP·12,HM6116ALSp·15,HM6116ALSP·20
.WRITE CYCLE
Item
Symbol
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Set Up Time
Write Pulse Widtk
Write RecoverY Time
Output Disable to Output in High Z
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
twe
tew
tAW
'AS
twp
tWR
tOHz
tWHZ
tDW
tDH
tow
HM6116ALPI
ALSP-lS
HM6116ALPI
ALSP·20
max
min
max
min
max
-
-
-
200
120
140
0
100
0
0
'0
50
0
-
-
ISO
90
120
0
80
0
0
0
40
0
-
10
-
10
HM6116ALPI
ALSP-I0
HM6116ALPI
ALSP-12
min
max
min
100
6S
80
0
60
0
0
0
30
0
-
-
120
70
lOS
0
70
0
0
0
35
0
-
10
10
-
40
30
-
-
-
40
35
-
-
SO
40
-
-
60
SO
-
.CAPACITANCE {J-IMHz. Ta-2S'C)
Item
Symbol
typ
max
l'nil
Input Capaeitanee
C ••
V.• -OV
3
5
pF
Input I Output Capaeitanee
C,.O
V, o-OV
5
1
pF
Test Conditions
Note} This parameter is sampled and not 100% tested.
• TIMING WAVEFORM
• Read Cycle (1)
(1]
~---------tRe----------~
Address
~-----tAes----r-~
Dout
___-1====~t£eL~Z~===4~
r--~--~~~~
.Read Cycle (2)
(11. (21, (41
.Read Cycle (3)
(11, (31, (4)
m
NOTES: 1.
is High for Read Cycle.
2. Device is continuously selected. CS = V/L.
3. Address Valid prior to or coincident with CS transition Low.
4. OE= VIL'
156
•
HITACHI
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
--------------HM6116ALP-10,HM6116ALP-12,HM6116ALP-15,HM6116ALP-20
HM6116ALSP-1 O,HM6116ALSP-12,HM6116ALSP-15,HM6116ALSP-20
eWrite Cycle (1)
twe
Address
t--
OE
L..L.t
es
\.\. ,\. \. \. \.'!J4)
tAW
tAs :-::::1
tewWE
(;fDW
Din
----,.
Address
'//////
I-twp[l)-
Dout
(5)
--
/
IIIIII
,tet [1)
'\. '\ '\ '\ ~
WP 1 -
WE -
I-tA
tWH~(3)
Dout
I--tOH@
f-tow-t
w"l2!-
ktDW+--tDH~8)
-
)OOO(
Din
NOTES:
ZZZ
tWR [2]
tew
\ \ \ \ \.(4)
-
tDH$;
twe
-
es \ '\
,""
\.\.\.\.\.
tOHZ 1-[3.1::1
eWrite Cycle (2)
tWR(2)
1. A write occurs during the overlap (twp) of a
low es and a low WE.
2. tWR is measured from the earlier of es or WE
going high to the end of write cycle.
3. During this period, 1/0 pins are in the output
state so that the input signals of opposite
phase!2.. the outputs must not be applied.
4. If the es low transition occurs simultaneously
with the WE low transitions or after the WE
5.
6.
7.
8.
transition, output remain in a high impedance
state.
OE is continuously low. (TIE = VIL)
D out is the same phase of write data of this
write cycle.
DO.ll1.is the read data of next address.
If es is Low during this period, 1/0 pins are
in the output state. Thim the data input
signals of opposite phase to the outputs must
not be applied to them .
• LOW Vee DATA RETENTION CHARACTERISTICS (Ta=O to +70'C)
Item
Symbol
Test Conditions
Vee for Data Retention
VDR
CS;;: Vee -0.2V
Data Retention Current
IceD"-
Vee-3.0V, CS;;:2,8V
Chip Deselect to Data Retention Time
,.
See Retention Waveform
Operation Recovery Time
• IO,uA max at Ta-Ot: to +40't. V"
h, "" Read Cycle Time.
**
fCDR
min
typ
max
Unit
2.0
-
-
--
3D
V
pA
-
-
0
tII:c··
ns
ns
min - -O.3V
eLow Vee Data Retention Waveform,
eHITACHI
157
HM6117P-3, HM6117P-4---204S-wordxS-bit High Speed Static CMOS RAM
.FEATURES
•
•
•
Single 5V Supply and High Density 24 pin Package.
High Speed: Fast Access Time
150ns/200ns (max.)
Low Power Standby and
Standby:
100~W (typ.)
Low Power Operation:
Operation: 200mW (tyP.)
Completely Static RAM:
No clock nor Timing Strobe Required
Directly TTL Compatible: All Input and Output
Equal Access and Cycle Time
•
•
•
.FUNCTIONAL BLOCK DIAGRAM
(DP-24)
__ vcc
Memory Matrix
Row
Decoder
_ _ GND
.PIN ARRANGEMENT
128Xl28
Input
Da..
Control
~2.-~~==r--r----11--------------"l
~l---+-o"""
WE
_---=t~.:::I;iD----..J
(Top View)
.ABSOLUTE MAXIMUM RATINGS
Item
Voltage on Any Pin Relative to GND
Symbol
VT
Power Dissipation
Pr
Operating Temperature
T.,.
Storage Temperature
T.t6
Temperature Under Bia.
T....
Rating
Unit.
'-0.5 to +7.0
1.0
o to +70
-55 to +125
-10 to +85
V
W
·c
·C
·c
* Pulle width SOn.: -1.5V
.TRUTH TABLE
CEI
H
WE
X
x
x
Noi" Selected
I~CLI
Not Selected
fccL2
High Z
High Z
H
Read
Write
Icc
Dout
Icc
Din
x
H
L
L
L
L
158
va
CEo
--
L
Mode
Vee Current
- .._..
Pin
_._ ..
eHITACHI
---------------------------HM6117P-3,HM6117P-4
(O"C~Ta~70"C)
.RECOMMENDED DC OPERATING CONDITIONS
Item
Vee
Supply Voltage
* Pulse width: SOns.
4.5
0
GND
Input High (logic 1) Voltage
Input Low (logic 0) Voltage
DC:
VIL"'~-
typ
max
Unit
5.0
0
3.5
5.5
V
0
V
V
V
min
Symbol
VIH
2.2
-1.0-
VII.
6.0
0.8
-
-O,3V
.DC AND OPERATING CHARACTERISTICS (Ta=Ot! to HOt!, Vcc=SV±10%. GND=OV)
Item
Input Leakage Current
Symbol
Output Leakage Current
I ho I
Operating Power Supply
Current: DC
Average Operating Current
Standby Power Supply
Ihll
Icc
leci
leeLl·
Current ill : DC
Standby Power Supply
Current 121 : DC
Output low Voltage
Output High Voltage
CE, -
CE". - VII.. II.o-OmA
Min cycle. duty-l00%
CE,-VIL. CE,-VIL
CE,"'Vee-0.2V.
VINE!; Vee-0.2V or VI,v$0.2V
feel.!·
eE''''Vcc-0.2V
VOL
V.H
IOL-2.1mA
ION-.,..l.OmA
typ
max
Unit
-
-
10
"A
-
-
10
"A
-
40
80
mA
-
40
80
mA
-
0.02
2
rnA
-
0.02
2
mA
min
Test Conditions
V.. -GND to Vee
eE, - VIN or CE, - VIN
VI, o-GND to Vee
-
-
0.4
V
-
V
-
2.4
Notes: 1) Typical limits are at Vcc-S.OV. Ta-+2S-c
21 • : V" ••• --O.3V
.CAPACITANCE (Ta-2S"C. f-1.0MHz)
Item
Input Capacitance
Input/Output Capacitance
Symbol
Test Conditions
typ
max
Unit
CIN
VIN-OV
V, o-OV
3
5
5
pF
pF
C"U
7
Note} This parameter is .ampled and not 100% tested •
• AC CHARACTERISTICS (Ta-Ot! to +70t!. Vcc -5V±10% unless otherwise noted)
e AC TEST CONDITIONS
Input Pulse Levels: 0.8 to 2.4V
Input Rise and Fall Times: 10 ns
Input and Output Timing Reference Levels: l.SV
Output Load: 1 TIL Gate and CL=100pF (including scope and jig)
eREAD CYCLE
Item
Symbol
HM6117P-3
max
min
HM61l7P-4
min
max
Unit
Read Cycle Time
lac
150
-
ns
IAA
150
200
n.
tCQI
150
-
200
Chip Enable (CE.) to Output
tCOI
-
-
-
Address Acces. Time
Chip Enable (CE,) to Output
150
-
200
n.
ns
Chip Enable (CE,) to Output in Low Z
Chip Enable (C&) to Output in Low Z
Chip Disable (eE,) to Output in High Z
Chip Disable (CE,) to Output in High Z
Output Hold from Address Change
lUI
tua
tH~1
tHZ!
to.
•
10
10
0
0
15
HITACHI
-
70
70
-
200
10
-
10
0
0
15
80
80
-
n.
ns
n.
ns
ns
159
HM6117P-3,HM6117P-4 - - - - - - - - - - - - - - - - - - - - - - - - - eTIMING WAVEFORM OF READ CYCLE
(Notes 1)
IftC
Adclre81
CEI
Dout
Data Valid
NOTES: 1. WE is High for Read Cycle.
eWRITE CYCLE
Write Cycle Time
Chip Enable ("CE,) to End of Write
Chip Enable ("CE,) to End of Write
Addre.. Set Up Time
Addre •• Valid to End of Write
Write Pul •• Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Dat, Hold from Write Time
Outpui Active from End of Write
HM6117P-4
max
200
120
130
20
150
120
15
70
0
60
20
10
HM6117P-3
min
max
150
100
110
20
130
100
15
0
60
50
20
10
-
Symbol
Item
Iwe
lewl
Ie ..
lAS
!"w
Iwp
IWR
tWHZ
min
-
-
low
ID'
low
Unit
n.
n.
n.
n.
n.
n.
n.
n.
n.
n.
n.
eTIMING WAVEFORM OF WRITE CYCLE
-
lwe
Acldre..
---,.
.
---.J
EE,
\\\\\\ l\\\~
"r3'r-
I•
I
(5)
Ie..
\\\\\' l\\\
I ••
fwp(l}
f..,(2)
\\\\\\
~,
~
"'~l~
DOllt
I ••
I ••
_f
\fX
Din
NOTES: 1 A write occurs during the
- 1lVerlap- -llivpr of -low- CE , ,
~2 andWJ::.
2. t AS is measured from the
address changes to the bigin.
ning of the write.
3. tWR is measured from the
earlier of (;£" ~, or WE
going high to the end/of
write cycle.
160
l(S)
Data In V.lid
4. During this period, I/O pins
- are' in- the- -output -state- ~o
that the input signals of
opposite phase to the out·
puts must not be applied.
S. If the CEI or CE. low transi·
tion occurs simultaneously
with the WE low transitions or
after the W! transitions, out·
ISut remain in a high im·
pedance state.
•
HITACHI
'V.YV.:::....
6. Dout is the same phase of
write --data-- ~f-- this --write
cycle.
7. Dout is the read jlata of next
address.
8. If eE, and CE; are low
during this period, I/.O pins
are in the output state. Then
the data input signals of opposite phase to the outputs
must not be applied to them.
------------------------------------------------------HM6117p~,HM6117P~
SUPPLY CURRENT
VS. SUPPLY VOLTAGE
SUPPLY CURRENT
VS. AMBIENT TEMPERATURE
1.6
1.6
Vcc=s.ov
r.=25'C
1A
.....
1.2
1.0
~
~
0.8
V
]
i
~
1.2
- ---
'" t---~
1.0
a
0.8
.
-----
~
]:
~
0.6
OA
4.5
1.4
4.15
5.0
5.5
525
0.6
OA
o
20
Supply Voltage Vee (V)
40
re)
ACCESS TIME
VS. AMBIENT TEMPERATURE
1.3
1.3
Vee = S.oV
To=2S"C
2
2
It-..
...............
~
e::
80
60
Ambient Temperature To
ACCESS TIME
VS. SUPPLY VOLTAGE
r--
V
1
~
--........
o.9
1.0
r.............
9
V
/'
~
0.8
O.1
O.1
4.5
4.15
5.5
525
5.0
20
Supply Voltage Vee (V)
60
40
Ambient Temperature Ta
ACCESS TIME
vs. LOAD CAPACITANCE
SUPPLY CURRENT
VS. FREQUENCY
1.8
1.3
200ns
1~
A
12
1.0
/
~
~
/'
V
.....
80
(Oe)
150n5
120n5
12
1.1
1.0
r.=25'C
Vcc=MIN
9
- --
0.8
.8
O.1
.6
100
200
300
400
10
500
Frequency
Load Capac Itance CL (pFJ
eHITACHI
f
(MHz)
161
HM6117P-3,HM6117P-4 - - - - - - - - - - - - - - - - - - - - - - - - - - INPUT HIGH VOLTAGE
VB. SUPPLY VOLTAGE
INPUT LOW VOLTAGE
VB. SUPPLY VOLTAGE
.3
1.3
T.=25'C
Th=25'C
1.2
1. 2
j
t
~
~
g
•
.3
1
-
1
1.0
t--
~
;
~
I
o.9
~
0.8
0:
4.75
5.5
5.25
5.0
1.0
~
4.5
5.25
5.0
5.5
OUTPUT LOW CURRENT
vs. OUTPUT LOW VOLTAGE
1.6
1.6
T.-25'C
Vcc=5V
,
1.4
]
\
1.0
0.6
0.4
I
1.4
]
1\
1.2
0.8
I
:i
~
\
1.2
1.0
E
c3
\
0.8
/
il.
d
0.&
~
Output. Voltale
VOR
I
/
T.=25'C
'Vcc-SV
eHITACHI
0.6
0.4
(Aatput Volt.ge
(V)
/
1/
0.2
1
162
4.75
Supply Volta,e Vee (V)
OUTPUT HIGH CURRENT
VB. OUTPUT HIGH VOLTAGE
~
l.--
0.8
Supply Voltage Vee (V)
I
---
~
o.9
o.7
0.7
4.5
1. 1
:l!
VOL
(V)
0.8
HM6117FP-3, HM6117FP-4--204S-wordXS-bit High Speed Static CMOS RAM
.FEATURES
• High Density Small Sized Package
• Projection Area Reduced to One-Thirds of Conventional DIP
• Thickness Reduced to a Half of Conventional DIP
• Single 5V Supply and High Density 24 pin Package.
• High Speed: Fast Access Time
150n5/2oons (max.)
• Low Power Standby and
Standby:
100/lW (typ.)
Low Power Operation:
Operation: 200mW (typ.)
• Completely Static RAM:
No clock nor Timing Strobe Required
• Directly TTL Compatible: All Input and Output
• Equal Access and Cycle Time
(FP-24)
.PIN ARRANGEMENT
.FUNCTIONAL BLOCK DIAGRAM
AI
AJ
AJ
A.
,..AA
A7
!~
- - - 0 Vee
Memory Matrix
Row
DeeocIer
- - - 0 GND
128Xl28
---tl:;C==1
Input
Data
Control
cr2_~~==j--i----t----------------.
(Top View)
crl---+-D...-.4
iVE_----lt>--=[;i[r----'
.ABSOLUTE MAXIMUM RATINGS
Item
Voltage on Any Pin Relative to GND
Power Dissipation
Symbol
Rating
VT
'-0.5 to +7.0
PT
Operating Temperature
To.r
Storage Temperature
T.,.
1.0
o to +70
-55 to +125
Temperature Under Bias
T•• u
-10 to +85
Unit
V
W
·C
·C
·C
• Pulse width SOns: -l.SV
.TRUTH TABLE
CEI
H
CEo
WE
Mode
Vee Current
X
X
[ceLl
X
feeL!
I/O Pin
High Z
High Z
L
H
L
Not Selected
Not Selected
H
Icc
Dout
L
L
L
Read
Write
Icc
Din
X
eHITACHI
163
HM6117FP~,HM6117FP4---------------------------------------------------
.RECOMMENDED DC OPERATING CONDITIONS (O'C~Ta~70'C)
Item
typ
max
4.5
5.0
5.5
V
0
2.2
-1.0-
0
3.5
0
6.0
0.8
V
Symbol
min
Vee
Supply Voltage
GND
V,.
Input High (logic 1) Voltage
Input low (logic 0) Voltage
V'L
-
Unit
V
V
• Pulse width: 5On.. DC: V".... --O.3V
.DC AND OPERATING CHARACTERISTICS (Ta-O'C to +70'C. Vcc-SV±10%. GND=OV)
Item
Input Leakage Current
Symbol
Output Leakage Current
I ILo I
Operating Power Supply
Current: DC
Icc
Average Operating Current
1cci
Standby Power Supply
I ILl I
leeL!-
Current !II : DC
Standby Power Supply
Current (21 : DC
Output low Voltage
Output High Voltage
typ
max
Unit
-
-
10
IlA
-
-
10
IlA
-eE,-CJ;;,-V'L. I, o-OmA
-
40
80
mA
Min cycle, duty-l00%
-
40
80
mA
-
0.02
2
mA
Test Conditions
min
V•• -GND to Vee
-eE,-V,. or CE.-V,.
V"o-GND to Vee
a:;, - VIL. a:;, - V'L
CEI~Vee-0.2V.
V,.<:Vee -0.2Vor VI..S:0.2V
feeu·
CE.;;;:Vee-0.2V
-
0.02
2
mA
VOL
VO.
IOL-2.1mA
I o.--1.0mA
-
-
0.4
V
2.4
-
-
V
Notes: 1) Typical limits are at Vcc-S.OV. TII- +2S-C
2) • : V,Loo .• - -O.3V
.CAPACITANCE (Ta-2S'C. /-1.0MHz)
Item
Input Capacitance
Input/Output Capacitance
Symbol
Test Conditions
typ
max
C'N
C,o
VIN-OV
V, o-OV
3
5
5
Unit
pF
7
pF
Note} This parameter is sampled and not 100% tested.
• AC CHARACTERISTICS (Ta-O'C to +70'C. Vcc =5V±10% unless otherwise noted)
e AC TEST CONDITIONS
Input Pulse Levels: 0.8 to 2.4V
Input Rise and Fall Times: IOns
Input and Output Timing Reference Levels: l.SV
Output Load: ITTL Gate and CL = 100pF (including scope and jig)
eREAD CYCLE
Item
Symbol
HM6117P-4
HM6117P-3
max
min
max
min
Read Cycle Time
he
150
-
200
-
Address Access Time
t"
-
150
-
200
Chip Enabl.~. (CE,) to Output
Chip Enable (CE.) to Output
t.C.o1 _
-
_.-
teot
-
Chip Enable (CE,) to Output in Low Z
tLZI
Chip Enable (CE.) to Output in Low Z
Chip Disable (CE,) to Output in High Z
Chip Disable (CE.) to Output in High Z
IHZ2
Output Hold from Address Chang.
to.
164
•
-.
._150 ..
-
~
..
-200-·
150
-
200
10
-
10
lLZ2
10
-
10
-
IHzl
0
0
15
70
0
0
15
HITACHI
70
-
Unit
ns
ns
--- -ns-
ns
ns
ns
80
ns
80
ns
ns
-
- - - - - - - - - - - - - - - - - - - - - - - - - - HM6117FP-3,HM6117FP-4
eTIMING WAVEFORM OF READ CYCLE
(Notes 1)
IRC
Address
CEI
Dout
Oua Valid
NOTES: 1.
WE is High for Read Cycle.
eWRITE CYCLE
Item
HM61l7P-3
Symbol
HM6117P-4
min
rna.
-
200
-
-
120
-
130
-
n'
20
-
n'
150
-
n'
15
-
W rite Cycle Time
twc
Chip Enable (CE') to End of Write
lewl
100
Chip Enable (CE.) to End of Write
tCWI
110
Address Set Up Time
t ..
20
Address Valid to End of Wri te
t.w
130
Write Pulse Width
100
Write Recovery Time
'two
I"
-
120
15
W rite to Output in High Z
tWHZ
0
60
0
70
Data to W rite Time Overlap
tow
50
60
Data Hold from W rite Time
Output Active from End of Write
10.
20
tow
10
-
-
eTIMING WAVEFORM OF WRITE CYCLE
Unit
max
min
150
20
10
o'
n'
n'
ns
n'
ns
n'
ns
,.,
Address
,.,
---'
\\\\"0 \\\\\'\
terr,
..
\\\\\ l\\\
tu(2)
,
\\\\\\
r...,.o)
~
1'.."Z(4)1
~(7)
,'\I
Dout
@.
Din
NOTES: I. A 'write occurs during the
overlap J!Ji!p) of low CE"
CE, and WE.
2. t A.S is measured from the address changes to the biginning
of the write.
3. tWR is measured from the
earlier of CE " CEo or WE
going high to the end/of
write cycle.
".
HITACHI
IDN
'V.Y\t.::>..
(8)
D,t, In. Valid
4. During this period, I/O pins
are in the output state so
that the input signals of
opposite phase to the outputs must not be applied.
S. If the CE , or CE, low transition occurs simultaneously
with the WE low transitions or
after the WE transitions, output remain in a high im-
•
f'm-
WI
I
(5)
pedance state.
6. Dout is the same phase of
write data of this write
cycle.
7. Dout is the read ,data of next
address.
8. If CE , and CEo are low
during this period, I/O pins
are in the output state. Then
the data inpu t signals of opposite phase to the outputs
must not be applied to them .
165
HM6117FP·3,HM6117FP-4 - - - - - - - - - - - - - - - - - - - - - - - - SUPPLY CURRENT
ya. SUPPLY VOLTAGE
SUPPLY CURRENT
Ya. AMBIENT TEMPERATURE
To=-251:
Vee = 5.0V
".
~
...,....... ~
V
r--
---r---
c
~
d 0.8
I--
~
j
0.4
4.5
4.75
004
525
5.0
0.6
5.5
o
20
Su.pply Volta,e Vee (V)
40
ACCESS TIME
Ya. SUPPLY VOLTAGE
eel
ACCESS TIME
YS. AMBIENT TEMPERATURE
1.3
1.3
Vcc-s.ov
r.=25'C
1
i
1.2
I" .............
~ I.
~
.f
1.0
]
i
~
I
j::
80
60
Ambient Temperature To
O.9
"'--r----
1.2
~
I.
~
1.0
V
I
V
L
~
j
0.8
0.8
o.7
4.5
4.75
5.0
o.7
5.5
5.25
Supply Volta,_ Vee (V)
80
ACCESS TIME
ya. LOAD CAPACITANCE
SUPPLY CURRENT
ya. FREQUENCY
1.8
1.3,-,.--r--r-r"7:-T.!.:--,
200ns
150na
lZ0n.
/
V
/
1.2r--~----+----~----~--~
V
To=2S"C
.0/
.
Vcc-MIN
0.8~--~-----+----~----+_--~
.8
.6
100
200
300
400
O.7'::-O----+----~--~~-_!;--~10
soo
~requency
Load Capacitance Ct. (pF)
166
60
40
Ambient Temperature Ta (-C)
,.
~
20
•
HITACHI
J
(MHz)
--------------------------HM6117FP.3,HM6117FP-4
INPUT LOW VOLTAGE
va. SUPPL Y VOLTAGE
INPUT HIGH VOLTAGE
VI. SUPPLY VOLTAGE
1.3
1.3
r.=25"e
TII=25"(;
1.2
1.2
j
~
;
!
•
oS
]
-
1
1.0
~
!
1.1
}
j
\. 0
:!!
~
O. 9
} o.9
I-----
~
~
~
~
O.ll
'"
O. 1
4.5
4.15
5.0
5.25
0.lI
O.1
4.5
5.5
4.15
Supply Voltage, Vee (V)
5.25
5.0
OUTPUT HIGH CURRENT
va. OUTPUT HIGH VOLTAGE
OUTPUT LOW CURRENT
VS. OUTPUT LOW VOLTAGE
1.6
.6
Ta=2S"C
Vcc .... sv
,
1.4
2
.4
\
0
O.6
O. 4
5.5
Supply Volt.le Vee (V)
.2
\
.0
\
8
0.6
~
0..
1
o
..i.
L
V
L
L
Ta=25"C
Vcc=5V
II
0.2
0.'
0.6
0.8
Output Volt.,e VOlt' (V)
•
HITACHI
167
HM6117LP-3, HM6117LP-4--204S-wordXS-bit High Speed Static CMOS RAM
.FEATURES
• Single 5V Supply and High Density 24 Pin Package.
• High Speed: Fast Access Time
150ns/200ns max.
• Low Power Standby and Low Power Operation;
Standby: 10J..lW (typ.) Two Chip Enable Input for Battery Back up
Operation: 180mW (typ.)
• Completely Static RAM:
No clock nor Timing Strobe Required
• Directly TTL Compatible: All Input and Output
• Equal Access and Cycle Time
• Capability of Battery Back up Operation
(DP-24)
.FUNCTIONAL BLOCK DIAGRAM
A,
AI
AI
d
A.
As
At.
A,
-oVcc
Memory Matrix
Row
Decoder
.PIN ARRANGEMENT
-OGND
128X128
CE:t---+-D~
WE
_--.:c>-..::::r;D----'
(Top View)
.ABSOLUTE MAXIMUM RATINGS
Item
Voltage on Any Pin Relative to GND
Symbol
Operating Temperature
T."
Storage Temperature
T~lw
Temperature Under Bias
T6 ...
Power Dissipation
PT
* Pulse width SOns:
Rating
Unit
·-0.5 to +7.0
o to +70
-55 to +125
-10 to +85
1.0
VT
V
·c
·C
·c
W
-l.SV
.TRUTH TABLE
CE,
-Il-
168
X
L
H
L
L
L
X
WE
CEo
-~
.. -
~-~~~X
X
H
L
~-
-~Not-
Mode
Selectea ~
Not Selected
Read
Write
Vee Current
~~
.. -,-
lcc-Ll'~-
1/0 Pin
High Z-
/CCLZ
High Z
Icc
Icc
Dout
eHITACHI
Din
----------------------------------------------------HM6117Lp~.HM6117LP~
.RECOMMENDED DC OPERATING CONDITIONS (Ta-O'C to+70'C)
Symbol
Item
Vee
Supply Voltage
GND
Input High (logic 1) Voltage
Input low (logic 0) Voltage
*
min
typ
max
4.5
0
5.0
5.5
V
0
6.0
0.8
V
V
V
V,H
2.2
0
3.5
VIL
-1.0·
-
Unit
Pulse Width: SOns. DC: VII. •.• --O.3V .
• DC AND OPERATING CHARACTERISTICS (Ta-O'C to+70'C, Vee-SV±10%, GND-OV)
Item
Symbol
Input Leakage Current
I ILl I
Output Leakage Current
I hoi
Operating Power Supply
Current: DC
Icc
max
Unit
VIN-GND to Vee
Test Conditions
-
-
2
",A
CE,-VI• or CE.-VIH
-
-
2
",A
CE,-CE.-VIL. 1I,o-OmA
-
35
70
mA
Min cycle. duty-lOO%
CEI-VIL, C£'z-VtL
'CE, ~ Vee-0.2V
-
35
70
mA
-
2
50
pA
-
2
50
",A
0.4
V
V
VI,o-GND to Vee
Average Operating Current
IccI
Standby Power Supply
Current (1) : DC
ICCLI·
Standby Power Supply
Current (21 : DC
feeL!·
CE.~Vee-0.2V
VOL
Io L-2.1mA
IOH--1.0mA
Output low Voltage
Output High Voltage
VOH
typ
min
VIN;;: Vee-0.2V or VI.::>0.2V
-
2.4
-
Notes: 1) Typical limits are at Vcc-S.OV. Ta-+2S"C
2) • : Vn..... --O.3V
.CAPACITANCE (Ta=2S'C, f-1.0MHz)
Symbol
Test Conditions
typ
Input Capacitance
CIN
VIN-OV
Input/Output Capacitance
C,/o
VI/O-OV
3
5
Item
I
I
I
max
Unit
pF
pF
5
7
Note:--O This parameter is sampled and not 100% teated.
• AC CHARACTERISTICS (Ta-O'C to +70'C, Vee =SV±10% unless otherwise noted)
• AC TEST CONDITIONS
Input Pulse Levels •.•...................
Input Rise and Fall Times .....•..........
Input and Output Timing Reference Levels ..•
Output Load ..........................
O.SV to 2.4V
10n8
1.SV
1 TTL Gate and CL = 100pF (Including Scope & Jig)
eREAD CYCLE
Item
Symbol
Read Cycle Time
Address Access Time
Chip Enable (CE, ) to Output
Chip Enable (CE,) to Output.
min
he
150
-
200
-
I"
-
ISO
-
200
-
150
150
-
200
200
10
10
-
10
-
0
0
70
70
10
0
15
-
tCOI
iLZl
fLzz
tHZl
Chip Disable (CEo) to Output in High Z
tHZ!
Output Hold from Address Change
to.
$
HM6117LP-4
max
max
teo!
Chip Enable (eE,) to Output in Low Z
Chip Enable (CE,) to Output in Low Z
Chip Disable (CE:/) to Output in High Z
HM6117LP-3
min
HITACHI
-
-
Unit
ns
ns
ns
ns
ns
80
ns
ns
0
80
ns
15
-
ns
169
HM6117LP-3,HM6117LP-4 - - - - - - - - - - - - - - - - - - - - - - - - - eTIMING WAVEFORM OF READ CYCLE
(Notes 1)
Address
Dout
Data Valid
NOTES: 1.
WE is High for Read Cycle.
_
eWRITE CYCLE
Write Cycle Time
Chip Enable (eE,) to End of Write
Iwe
150
-
few1
100
110
20
-
Chip Eo.ble (CE.) to End of Write
Address Set Up Time
lew2
Address Valid to End of Write
Write Pulse Width
tAw
lAS
IWR
tWHZ
Data to Write Time Overlap
Data Hold from Write Time
10.
Output Active from End of Write
low
low
min
200
120
130
20
150
120
15
0
60
20
10
-
-
130
100
15
Iwp
Write Recovery Time
Write to Output in High Z
HM6117LP-4
max
HM6117LP-3
min
max
Symbol
Item
-
0
60
50
20
10
-
-
-
-
Unit
ns
ns
-
ns
ns
-
n'
n'
ns
70
n.
-
n'
ns
n.
eTlMING WAVEFORM OF WRITE CYCLE
I.,
Address
(5)
terr.
,.u(2)
DOdl
ID"
'''11
(8)
Din
NOTES: 1 A write occurs during the
~r1ap ~p) of low eE"
CEo and WE.
2. t AS is measured from the
address changes to the biginning of the write.
3. tWR is measured from the
earlier of CE" CE. or WE
going high to the end/of
write cycle.
170
Data In Valid
4. During this period, I/O pins
are in the output state so
that the input signals of
opposite phase to the outputs must not be applied.
S. If the <:£, or CE. low transition occurs simultaneously
with the WE low transitions or
after the WE transitions, output remain in a high impedance state.
$
HITACHI
6. Dout is the same phase of
write data of this write
cycle.
7. Dout is the read aata of next
address.
8. If CE, and CEo are low
during this period, I/O pins
are in the output state. Then
the data input signals of opposite phase to the outputs
must not be applied to them.
--------------------------HM6117LP·3,HM6117LP-4
.LOW Vee DATA RETENTION CHARACTERISTICS (Ta-O'Cto +70'C)
Symbol
Item
Test Conditions
min
Vee for Data Retention
VD.U
CE, :i:Vee -O.2V,
VIN;;:; Vee -0. 2V or VlN :OO.2V
Vee for Data Retention
VOltl
CE,;;:;Vee-O.2V
Data Retention Current
fcc DR I
Vee -3.0V, cr-;;;:;2.8V,
V,N:i:2.8V or V,N=>0.2V
Vee -3.0V, CE,;;:;Vcc-O.2V
Data Retention Current
[CCDa!
Chip Deselect to Data Retention Time
teDa
Operation Recovery Time
t.
See Retention Waveform
2.0
2.0
-
typ
max
-
-
V
-
V
30·
pA
30·
pA
-
-
°
-
tRC"
Unit
ns
ns
• lOpA max at T.-Q"C to +40"C. VtL min--O.3V
I.e-Read Cycle Time
**
-LOW Vee DATA RETENTION WAVEFORM
Data Retention Mode
~,----------------"'~----------------------------------~r----------------
~
_ _ _.J
ov--- ______________________________________ _
NOTE:
1. ~ cont~Address buffer, WE buffer, CE , buffer and DIN
buffer. If CEo con trois data retention mode, VIN level (address,
(WE,
01/0) can be in the high impedance state. If CE,
controls data retention mode, VIN level (address, WE, DE"
01/0) must be VIN ~ Vee-O.2Vor VIN ;l; O.2V.
cr.,
SUPPLY CURRENT
VB. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
1.6
1.6
Vcc=s.ov
Ta-25"C
1A
./
12
1.0
...........
0.8
~
~
V
~
1.0
~
0.8
""
d
--- -
r---- r--
0.6
0,4
4.5
4.75
5.0
o.4
5.5
5.25
Supply Voltage Vee (V)
20
40
60
80
Ambient Temparature To ("C)
•
HITACHI
171
HM6117LP·3, H M 6 1 1 7 L P . 4 - - - - - - - - - - - - - - - - - - - - - - - - ACCESS TIME VS.
SUPPLY VOLTAGE
ACCESS TIME VS.
AMBIENT TEMPERATURE
1.3
1.3
Vee = s.oV
r.=25"(;
1.2
j
~
1.1
1
1.0
............
:!
~
-.............
;l
I
j:;
0.9
J
0.8
/
I
1.0
I'-...
I
.
.li
f.:
o.9
/
~
0.8
o.7
0.7
4.5
4.15
5.0
5.25
20
5.5
Supply Voltase Vee (V)
1.3
IA
~
1.2
3
I
;:
S·
.li
..,,-
1.6
!
1.G
./
V
./
60
2oon,
150ft.
I. I
V
1.0
~~
TII=25"C
Vcc=MIN
0.9
0.8
0.8
o.7
100
200
300
400
10
500
Frequency
Load Capacitance Cr. (pF)
INPUT LOW VOLTAGE VS.
SUPPLY VOLTAGE
I
(MHz)
INPUT HIGH VOLTAGE VS.
SUPPLY VOLTAGE
.3
1.3
Ta=25'C
To=25"C
I.2
I.2
-
I
~
==
..s-
•
oS
1.0
!---"
i
1.0
~
; o.9
..s-
o.8
:t:
~
4..75
S.O
S.2S
--
I
o.9
O. 7
4.5
O.8
------
O.7
4.S
S.5
Supply Voltage Vee (V)
172
120ft.
1.2
V
0.6
i
80
SUPPLY CURRENT VS.
FREQUENCY
1.8
~
40
Ambient Temperature Ta I·e)
ACCESS TIME VS.
LOAD CAPACITANCE
j
/'
4.75
S.O
Supply Voltage Vee (V)
•
HITACHI
~
S.25
S.S
--------------------------HM6117LP-3,HM6117LP-4
OUTPUT HIGH CURRENT
VB. OUTPUT HIGH VOLTAGE
OUTPUT LOW CURRENT
va. OUTPUT LOW VOLTAGE
I.6
I.4
1
!
!
:;
I.6
,
I.2
,
Vcc-5V
I.
0.8
!
I.2
~
1.0
c3
0.8
:;
!
\
j
o.6
!
\
I
~
-'-
/
]
\
I.D
I
d
r.-2S-c
/
o.6
I
TCI=25"C
Vcc=SV
o.4
VOII
(V)
Output Voltage
STAND-BY CURRENT va.
AMBIENT TEMPERATURE
0.6
0.4
0.2
Output Volta,e
VOL
STAND-BY CURRENT va.
SUPPLY VOLTAGE
,
·
I.
Vcc=3V
CEo=2.8V
2
~
·
0
;; lO'
.::
V
E
(l
~
1u;
·
lO'
L
o.8
./
V
V
V
O.
'V
V
5'=
Ta=2S"C
Vee-O.2V
O. 2
20
40
60
2
Ambient Temperature Til t"C!
Supply Voltage Vee (V)
STAND-BY CURRENT va.
INPUT VOLTAGE
STAND- BY CURRENT va.
INPUT VOLTAGE
0
TII=251:
Vcc .. sv
CEI-4.8V
"
8
6
6
4
,
2
2
~
\
To=25"<:
Vcc=SV
~=4.8V
8
0
/
~
.IV
6
,
10'
o
0.8
(V)
0
Input Volta,e Y,N (V)
Input Yoltage V.. (V)
_HITACHI
173
HM6117LFP-3, HM6117LFP-4-204S-wordXS-bit High Speed Static CMOS RAM
.FEATURES
• High Density Small·sized Pack~ged
• Projection Area Reduced to One·Thirds of Conventional DIP
• Thickness Reduced to a Half of Conventional DIP
• Single 5V Supply
• High Speed: Fast Access Time
150ns/200ns max.
• Low Power Standby and Low Power Operation;
Standby: 10",W (typ.) Two Chip Enable Input for Battery Back up
Operation: 18OmW(typ.)
• Completely Static RAM:
No clock nor Timing Strobe Required
• Directly TTL Compatible: All Input and Output
• Equal Access and Cycle Time
• Capability of Battery Back up Operation
(FP-24)
.PIN ARRANGEMENT
.FUNCTIONAL BLOCK DIAGRAM
AI
At
At
At
AI
At
A.
i~
---+-i:j(=::::J
--Vee
Memory Mattix
Row
D.......
_ _ GND
128Xl28
IIOI---ri-Oh--t
(Top View)
CEl---fo00.4
WE _ _
-=t~.::r;;o-_..J
.ABSOLUTE MAXIMUM RATINGS
Item
Voltage on Any Pin Relative to GND
Symbol
VT
Rating
0-0.5 to +7.0
Unit
V
Operating Temperature
T."r
Storage Temperature
T.,.
o to +70
-55 to +125
·C
·C
Temperature Under Bias
Power Dissipation
T....
PT
-10 to +85
1.0
·c
W
• Pulse width 5Ons: -1.5V
.TRUTH TABLE
CEI
CE.
WE
H
X
X
174
X
H
X
L
L
H
L
L
L
Mode
Not Selected
Not Selected
Vee Current
Read
Write
$
/ceLl
I/O Pin
High Z
ICCLZ
High Z
Icc
Dout
Icc
Din
HITACHI
-------------------------------------------------HHM6117LFP·3,HM6117LFP·4
.RECOMMENDED DC OPERATING CONDITIONS (Ta-O'C to+70't!)
Item
min
typ
max
Vee
4.5
GND
0
2.2
-1.0·
5.0
0
5.5
0
3.5
6.0
0.8
Symbol
Supply Voltage
Input High (logic I) Voltage
Input low (logic 0) Voltage
VI.
Vn
-
Unit
V
V
V
V
vll.... --O.3V .
• Pul.. Width:50na, DC:
• DC AND OPERATING CHARACTERISTICS (Ta=O'C to +70'C, Vee-SV±10%, GND-OV)
Item
• Input Leakage Current
Output Leakage Current
Operating Power Supply
Current: DC
Average Operating Current
Standby Power Supply
Current III : DC
Standby Power Supply
Current 121 : DC
Output low Voltage
Output High Voltage
min
-
typ
max
2
Unit
-
-
-
2
JlA
eE,-CE,-V,L, 1,·o-OmA
-
35
70
mA
Min cycle, duty-lOO%
-
35
70
mA
-
2
50
JlA
-
2
50
JlA
V
V
Symbol
I ILl I
I fLo I
Icc
lccl
feeu·
Test Conditions
VIN-GND to Vee
CE,-VIH or CE,-VIH
VI,o-GND to Vee
CE,-Vn, eE,-V'L
CE,01:Vee -0.2V
VI .• ~ Vee-0.2V or V/NS:0.2V
feeu-
eE.~Vee-0.2V
VOL
IOL-2.lmA
IOH--1.0mA
VOH
-
-
0.4
2.4
-
-
JlA
Notes: 1) Typical limits are at Vee-S.O\'. T.-+2S"C
2) • : V".... --O.3V
.CAPACITANCE (Ta-2S'C, /-1.0MHz)
Item
Input Capacitance
Input/Output Capacitance
Symbol
typ
Test Conditions
VIN-OV
V, o-(lV
Cu;
Cl,O
3
max
5
5
7
Unit
pF
pF
Note: 1) This parameter ia sampled and not 100% tested .
• AC CHARACTERISTICS (Ta=O'C to +70'C, Vee -SV±10% unless otherwise noted)
• AC TEST CONDITIONS
Input Pulse Levels· .....................
Input Rise and Fall Times· ...............
Input and Output Timing Reference Levels· ..
Output Load ..•..................•....
O.SV to 2.4V
10ns
1.SV
1 TTL Gate and CL ~ 100pF (Including Scope & Jig)
eREAD CYCLE
Item
Symbol
HM6117LFP-3
min
HM6117LFP-4
max
min
200
max
Unit
-
ns
-
200
-
200
200
n.
n.
10
-
n.
ns
10
-
10
-
ns
0
70
0
80
0
IS
70
0
IS
80
n.
n.
-
n.
Read Cycle Time
he
ISO
-
Address Access Time
Chip Enable (CE,) to Output
Chip Enable (CE.) to Output
I ••
-
tCOI
-
tC02
-
ISO
ISO
ISO
Chip Enable (CE,) to Output in Low Z
tLZI
10
Chip Enable (eE.) to Output in Low Z
Chip Disable (eE,) to Output in High Z
Itzz
IHzl
Chip Disable (a~',) to Output in High Z
IHzz
Output Hold from Address Change
to.
_HITACHI
-
175
HM6117LFP-3,HM6117LFP-4------------------------------------------------eTIMING WAVEFORM OF READ CYCLE
(Notes 1)
'oe
Address
'08
Dout
Data Valid
NOTES: 1. WE is High for Read Cycle.
eWRITE CYCLE
HM6117LFP-3
Symbol
Item
Write Cycle Time
Iwe
Chip Enable (CE",) to End of Write
Chip Enable (CE".) to End of Write
tewl
Address Set Up Time
I ..
Address Valid to End of Write
Write Pulse Vlldth
I,w
W rite Recovery Time
Iw.
Write to Output in High Z
tWHZ
Data to W rite Time Overlap
low
Data Hold from W rite Time
10.
Output Active Irom End of Write
low
min
ISO
100
110
20
130
100
IS
0
50
20
10
fewz
I_p
max
HM6117LFP-4
min
max
200
ns
ns
120
130
60
Unit
ns
20
ISO
ns
120
ns
ns
IS
0
60
20
10
ns
70
ns
ns
ns
ns
eTIMING WAVEFORM OF WRITE CYCLE
1o,
Address
CEI
tu(2)
Dout
Din
NOTES: 1 A write occurs during the
overlap Qwp} of low CE
"
~o and WE.
2. t.AS is measured from the
address changes to the biginning of the write.
3. tWR is measured from the
earlier of CE " ~. or 'WE
going high to the end/of
write cycle.
176
Data In Valid
4. During this period, I/O pins
are in the output state so
that the input signals of
opposite phase to the outputs must not be applied.
S. If the ~, or 'CEo low transition occurs simultaneously
with the"ft low transitions or
after the WE transitions, output remain in a high im-
eHITACHI
pedance state.
6. Dout is the same phase of
write data of this write
cycle.
7. Dout is the read .data of next
address.
8. If CE, and CE; are low
during this period, I/O pins
are in the output state. Then
the data input signals of opposite phase to the outputs
must not be applied to them.
HM6117LFP·3, HM6117LFP·4
.LOW Vee DATA RETENTION CHARACTERISTICS (Ta~O'Cto +70'C)
Item
Symbol
Vee for Data Retention
VD"I
Vee for Data Retention
VDJU
Data Retention Current
IceDR I
Data Retention Current
/CCDRZ
Chip Deselect to Data Retention Time
teDit
Operation Recovery Time
t.
*.
*
typ
max
-
V
-
V
0
-
tile"
-
min
Test Condition
CE1~VCC-0.2V,
2.0
V'N<:Ve e-0.2Vor V/N:>0.2V
CE,~Vee-0.2V
2.0
Vee-3.0V,
CE.' O:2.8V,
V,N~2.8V
or V,N::OO.2V
Vee-3.0V,
-
CE,~Vce-0.2V
See Retention Waveform
Unit
30·
pA
30'
pA
-
ns
-
ns
IGpA max. at Ta-O·C to +4ffC. V,L min- -O.3V
i.e - Read Cycle Time
-LOW Vee DATA RETENTION WAVEFORM
Vee - - - - - - _ " " ' " '
Data
1-------==.::..:==:....:::=.-----.,
, ________
Retention Mode
a.-___J
ov _________________________________________ •
NOTE:
1. CEO controls Address buffer,.WE buffer, CE , buffer and DIN
buffo:!:Jf C£; controls data retention mode, VIN level J!cidress,
WE, CE, , 01/0) can be in the high impedance state. If CE; con·
trois data retention mode, VIN level (address, WE, CE" 0,,0)
must be VIN ~ Vcx::-O.2V or VIN ~ O.2V.
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
1.6
Vcc=S.OV
To-25"C
]
IA
1
1.2
z
~
.,g
1.0
I
0.8
u
./
~
~
.........
./
~
1.2
~
0.6
o.4
1.4
?
j
'"
]
4.5
us
5.25
5.5
~
r--
0.6
o.4
5.0
--- -20
40
60
80
Amb,t>nr Temparalure Ta /'C)
Supply Voltage Vee l V)
•
HITACHI
177
HM6117LFP-3, H M 6 1 1 7 L F P - 4 - - - - - - - - - - - - - - - - - - - - - - - ACCESS TIME VS.
SUPPLY VOLTAGE
ACCESS TIME VS.
AMBIENT TEMPERATURE
1.3
1.3
Vcc=S.ov
r.=25'C
1.2
1.2
]
1
~
i
""
............
~
1.1
~
1.0
!
f=
o.9
V
:1!
~
-..............
0.9
r---.....
,,-/
V
E
~
0.8
o.1
4.75
0.8
.7
5.0
5.25
20
5.5
Supply Voltage Vee (V)
SUPPLY CURRENT VS.
FREQUENCY
1.8
1A
~
1.2
;:;
1.0
~
1.3
I
./V
./
150ns
--
r---
V
V
1
r.=25'C
Vee = MIN
9
]
0.8
0.8
0.6
100
200
300
soo
400
o.7
10
load Capacitance CL (pF)
Frequency / (MHz)
INPUT LOW VOLTAGE VS.
SUPPLY VOLTAGE
1.3:,-----.---.,.----,-----,
INPUT HIGH VOLTAGE VS.
'SUPPLY VOLTAGE
1.3
Ta=2S'C
]
~
1.21----+---+----+----1
1.1
~
;;:
i
~
i!.
1.0
0.9
..!i
.3•
-
-
T(I=25~
1.2
.1
.0
~
.9
0.8
0.7
4.5
--
~
----
.8
4.75
5.0
5.25
5.5
Supply Voltage Vee (V)
178
120ft.
200ns
./
1.6
~
80
60
40
Ambient Temperall1re Ta ('e,
ACCESS TIME vs.
LOAD CAPACITANCE
]
V
o.7
4.5
4.15
5.0
Supply Voltage Vee (V)
eHITACHI
5.25
5.5
HM6117lFP-3, HM6117lFP-4
OUTPUT HIGH CURRENT
VB. OUTPUT HIGH VOLTAGE
OUTPUT LOW CURRENT
VB. OUTPUT LOW VOLTAGE
.6
I.6
•
I.
TII=25·C
,
2
Vcc=SV
\
0
.
]
~
1. 2
~
]
\
O.6
=
d
I
\
1.0
0.8
0..
Output Voltage
VON
~
<3
10'
V
to-
o
0.'
0.2
0.8
0.6
VOL
STAND-BY CURRENT
SUPPLY VOLTAGE
(V)
VB.
1.4
j
~
V
~
V
1.2
1.0
L
;;
-=
0.8
f
<3
./
V
O.
L
~
V
=
6
O.
'V
,
O
Ta=2S1:
Vcc=5V
Vcc=3V
ct,=2.8V
·
·
~
]
/
Output Voltage
·
to-
/
/
V
(V)
STAND-BY CURRENT VB.
AMBIENT TEMPERATURE
.
/
O.ll
1\
•
O•
~
1
V
Ta=Z5"C
c:r =
Vee -0.2V
O. 2
20
40
60
80
2
Supply Volt.,e Vee (VJ
Ambient Temperature Ta (-C)
STAND-BY CURRENT va.
INPUT VOLTAGE
STAND-BY CURRENT
INPUT VOLTAGE
VB.
0
0
T.=25'C
r.. =25"(
Vcc=5V
Vcc=SV
CE.=UV
CE.=uv
8
8
6
6
4
•
2
o
o
~
\
0
Input Voltage
Input Voltage V,/W (V)
_HITACHI
v..
(V)
179
HM616SH-4S,HM6168H-SS'-~=I~pment
HM616SH-70,HM616SHP-4S,
HM616SHP-SS,HM616SHP-70
4096-wordX4-bit High Speed Static CMOS RAM
.FEATURES
• High Speed: Fast Access Time 45/55/70 ns (max.)
• Single +5V Supply and High Density 20 Pin Package
• Low Power Standby and Low Power Operation;
1001tW typo (Standby), 250mW typo (Operation)
• Completely Static Memory
No Clock or Timing Strobe Required
• Equal Access and Cycle Times
• Directly TTL Compatible - All Inputs and Outputs
HM6168H-45/55/70
.FUNCTIONAL BLOCK DIAGRAM
(DG-20)
A.~--~c=c=~----'
HM6168HP-45/55/70
A·o---Dt=:=I
A.o---ca:=::::::!
I{tlW
A,o---Dt=:=I Uocnder
A. o---~=::::!
A.o---C:O;:=:::::l
A·o----t(a==L__-1
Memory Matrix
GNP
128X 128
Column VO
Column UeC'oder
(DP-20)
.PIN ARRANGEMENT
~~~LJ~----------------------------~
.ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Rating
Voltage on Any Pin Relative to GND
V,N
-3.5' to +7.0
V
Power Dissipation
PT
1.0
W
Unit
Operating Temperature
Top,
o to
+70
·C
Storage Temperature (Ceramie)
T.,•
-65 to +150
·C
Storage Temperature (Plastic)
T.,•
-55 to +125
·C
Temperature under Bias
T....
-10 to +85
·C
* Pulse Width 2On&, OC--O.5V
Note} The specifications of thi" device are subiec:t to eha. without notice.
Please contact your nearest Hitachis Sales Dept. reqarding specifications .
180
•
HITACHI
(Top View)
HM6168HLP-45,HM6168HLP-55,
HM6168HLP-70
Under Development
4096-word x 4-bit High Speed Static CMOS RAM
.FEATURES
• High Speed: Fast Access Time 45/55/70ns(max.)
• Single +5V Supply and High Density 20 Pin Package
• Low Power Standby and Low Power Operation;
5JJ,W typo (Standby). 250mW typo (Operation)
• Completely Static Memory
No Clock or Timing Strobe Required
• Equal Access and Cycle Times
• Directly TTL Compatible-All Inputs and Outputs
• Capable of Battery back up Operation
(DP-20)
.FUNCTIONAL BLOCK DIAGRAM
,-\0
o----t;:a:===r--"l
.PIN ARRANGEMENT
A, o---;';;~==I
A. o----[~==1
Vee
Memury Matrix
o----l.::c:::=:::1
A. O----l.::c:::=:::1
A.
GND
128X 128
A, o----[~==1
A.
o-----l;cI===1._-.-J
Column
Input
Data
VO
Column De('oder
Cnntrnl
1/1l! o--~+t::H---1
(Top View)
~~~L-r-r-------------------~~
.ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Rating
Voltage on Any Pin Relative to GND
VIN
-3.5· to +7.0
V
Power Dissipation
PT
1.0
W
+70
·c
o to
Unit
Operating Temperature
Top,
Storage Temperature
Td •
-55 to +125
·C
Temperature under Bias
T~iu
-10 to
·c
* Pulse Width 20n8,
+85
DC--O.SV
Note} The llpecifications of this device are subject to ehange without notice.
Please contact your nearest Hitachi's Sales Dept. reprdina 5pecifications .
•
HITACHI
181
HM6167,HM6167-6,HM6167-S,
HM6167P,HM6167P-6,HM6167P-S
16384-word x1-bit High Speed Static CMOS RAM
.FEATURES
• Single +5V Supply and High Density 20 Pin Package
• Fast Access Time - 70ns/85ns1100ns
• Low Power Stand-by and Low Power Operation
Stand-by 25mW Typ. and Operating 150mW Typ.
• Completely Static Memory . • . • . No Clock nor Refresh Required
• Fully TTL Compatible - All Inputs and Output
• Separate Data Input and Output • ........ Three State Output
• Pin.Qut Compatible with Intel 2167 Series
.BLOCK DIAGRAM
HM6161. HM6161-6,
HM6161-8
(DC-20)
""--[:;:0
~Vee
~GND
HM6167P, HM6167P-6,
HM6167P-8
Memory Array
128X 128
Row
Select
Dout
Din
(DP-20)
.PIN ARRANGEMENT
.ABSOLUTE MAXIMUM RATINGS
Symbol
Item
Rating
Unit
Terminal Voltage with Respect to GND
VT
-0.5 to +1.0
V
Power Dissipation
PT
1.0
W
Operating Temperature
ToJlr
o to
+10
·C
Storage Temperature(Plastic)
h,,.
-55 to +125
·C
Storage Temperature ( Ceramic)
he.
-65 to +150
·C
.RECOMMENDED DC OPERATING CONDITIONS
( O'C~Ta~70'C)
Item
Supply Voltage
Input High Voltage
Input Low Voltage
182
Symbol
Vee
GND
"'.
"'L
min
4.5
typ
max
Unit
5.0
5.5
V
0
V
2.2
-
6.0
V
-0.5
-
0.8
V
0
0
eHITACHI
(Top View)
HM6167, HM6167-6, HM6167-8, HM6167P, HM6167P-6, HM6167P-8
.TRUTH TABLE
CS
WE
Mode
Vee Current
Output Pin
H
X
Not Selected
ISB, /S81
High Z
L
H
Read
Icc
Dout
Read Cycle I, 2
L
L
Write
Icc
High Z
Write Cycle I, 2
Reference Cycle
.DC AND OPERATING CHARACTERISTICS (Vcc-5V±10%, Ta=O'C to +70'C)
min
typ
max
Unit
Input Leakage Current
I ILl I
Vee-5.5V, ViN-OV-Vee
-
-
2
JlA
Output Leakage Current
Ihol
CS- ViH, VOUT-OV- Vee
-
-
2
JlA
Operating Power Supply Current
Icc
CS- ViL, Output Open
-
30
60
mA
Iss
CS- ViH
-
5
20
rnA
-
0.02
2
rnA
-
-
0.4
V
2.4
-
-
V
Item
Symbol
Standby Power Supply Current
Test Conditions
CS-Vee-0.2V
Issl
ViN::iOO.2Vor
Output Low Vohage
VOL
IOL-8mA
Output High Vol tage
VOH
IOH=-4mA
~Vee-0.2V
Note) Typical limits are at Vcc-S.OV. Tu-2S-C and specified loading.
.AC TEST CONDITIONS
Output Load A
Input pulse levels: GND to 3.0V
Input rise and fall times: 5 ns
Input timing reference levels: 1.5V
Output reference levels: 1.5V
Output load: See Figure
Output Load B
(for
+sv
~
'80Q
Do"
2550
.
tHZ.
hz, twz & tow)
+sv
."~:,,
3.,F'
* Including scope and jig•
• CAPACITANCE (Ta= 2S'C, f
Item
=
Symbol
1. OMHz)
max
Unit
Input Capacitance
C'N
5
pF
ViN-OV
Output Capacitance
COlJT
6
pF
VOUT=OV
Conditions
Note) This parameter is sampled and not 100% tested.
• AC CHARACTERISTICS (Vcc-SV±10%, Ta=O'C to 70'C, unless otherwise noted.)
eREAD CYCLE
HM6l61, HM6l61P
Item
HM6l61-6, HM6l61P-6
HM6l67-8, HM6l61P-8
Symbol
min
max
min
max
min
Unit
max
Read Cycle Time
toe
10
-
85
-
100
-
ns
Addres. Access Time
I"
-
70
85
-
100
ns
Chip Select Access Time
tACS
-
70
-
85
-
100
ns
Output Hold from Address Change
tOH
n.
n.
Chip Selection to Output in Low Z
ILz
5
-
5
-
5
-
Chip Deselection to Output in High Z
1Hz
0
30
0
40
0
40
Chip Selection to Power Up Time
tpu
0
-
0
-
0
-
ns
Chip Deselection to Power Down Time
tPD
45
ns
-
5
-
35
eHITACHI
-
5
-
40
5
-
ns
183
HM6167. HM6167-6. HM6167-8. HM6167P. HM6167P-6. H M 6 1 6 7 P - 8 - - - - - - - - - e WRITE CYCLE
HM6167. HM6167P
Item
Symbol
min
HM6167-6. HM6167P-6 HM6167-8. HM6167P-8
max
min
max
min
max
-
85
100
65
0
-
55
-
35
-
0
Write Cycle Time
Iwe
70
Chip Selection to End of Write
lew
55
Address Valid to End of Write
lAW
55
Address Setup Time
lAS
0
Write Pulse Width
Iwp
40
Write Recovery Time
IWA
0
Data Valid to End of Write
low
30
Data Hold Time
10.
0
-
Write Enable to Output in High Z
Iw.
0
30
0
Output Active from End of Write
low
0
-
0
65
0
45
0
80
80
ns
3.4
-
0
-
ns
3.4
0.." V.lhI
V.lid
NOTES: 1. WE is high and ~is low' for READ cycle.
2. Addresses valid prior to or coincident with ~ transition low.
3. Transition is measured ± 500mV from steady state voltage with
specified loading in Load B.
_HITACHI
ns
40
... s....,
184
ns
0
1).2)
Dati
ns
40
eTIMING WAVEFORM OF READ CYCLE NO.2 1).3)
Qui
2
-
Addre ••
Data
ns
ns
0
40
a.
Data Out
Notes
-
0
Notes) 1. If CS goes high sirnultaneouly with ·WE high. the output remains in a high impedance state.
All Write Cycle timings are referenced from the last valid address to the first transitioning address.
3. Transition is measured ±500mV from steady state voltarre with specified loading in Load B.
4. This parameter is sampled and not 100% tested.
eTIMING WAVEFORM OF READ CYCLE NO.1
Unit
ns
ns
ns
- - - - - - - - - - - - H M 6 1 6 7 , HM6167-6, HM6167-8, HM6167P, HM6167P-6, HM6167P-8
eTIMING WAVEFORM OF WRITE CYCLE NO.1 (WE Controlled)
D...... I..
D.,. Undehned
Data Out
NOTE:
1. Transition is measured :tSOOmV from steady state voltage with
specified loading in Load B.
eTIMING WAVEFORM OF WRITE CYCLE No.2 (CS Controlled)
'.e
Address
~
)
----./
'"
I
Ie.
'\
."
-""'-"'" -"'" -"'" -"'"
I
~
/11
...
...
X
Data In
'"
lop
X
Data In Valid
'"
Data Oul
High Impedance
Data Undefined
Note}
Transition is measured ±500mV from steady state voltage with specified loading in Load B.
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. AMBIENT TEMPERATURE
1.6
1.6
Vcc=S.ov
T.=25"C
..]~
z
1.4
1.2
G
~ 1.0
g
...........V-
0.8
~
.....-
./
1.0
"
~
<3
<3
-----
r--
0.8
~
~
~
0.6
'"
0.6
r--
o.4
OA
4.5
4.15
5.0
5.25
20
5.5
40
60
80
Ambient Temperature Ta ("C)
Supply Voltage Vee (V)
•
HITACHI
185
HM6167, HM6167·6, HM6167·8, HM6167P, HM6167p·6, H M 6 1 6 7 P · 8 - - - - - - - - - - ACCESS TIME vs.
AMBIENT TEMPERATURE
ACCESS TIME vs.
SUPPLY VOLTAGE
1.3
.3
Vcc-s.ov
r.-25"(;
1.2
.2
]
V
...
:i•
~
.
1.1 ....
•
1.0
~
0.9
J
0.8
~
1.1
~
1.0
-......... r--
0.9
./
~
0.8
0.7
0.7
4.5
4.75
5.0
5.5
5.25
o
20
1.8
1.4
~
1.2
3
I
1.3
;:::
1.0
j
0.8
......
V
./
C
.!l
T/J-25\:
Vcc-MIN
300
120ns
1
./
200
400
-
1.0
e
d 0.9
I--
o.7
500
10
Load Capacitance Q. (pFJ
Frequency
J
(MHz)
INPUT HIGH VOLTAGE vs.
'SUPPLY VOLTAGE
INPUT LOW VOLTAGE vs.
SUPPLY VOLTAGE
.3
.3
r.:25'C
...
.
To:=2S·C
.2
E
1.1
S
1.0
2
-
02
j
~
.
s
1
1.0
t l..---
:: o.9
~ o.9
1 o.
j
.;
4.5
----
~
~
~
8
o. 1
4.15
5.0
5.25
5.5
o.8
O. 1
4.5
Supply Voltage Vee (V)
186
80
1.2
.7
0.6
100
150ns
200ft.
,.
1.6
:i
60
SUPPLY CURRENT vs.
FREQUENCY
ACCESS TIME vs.
LOAD CAPACITANCE
t
40
Ambient Temperature Til (OC)
Supply Voltage Vee (V)
1
V
4.75
5.0
Supply Voltage
eHITACHI
5.25
Vec (V)
5.5
_ _ _ _ _ _ _ _ _ _ _ HM6167. HM6167-6. HM6167-8. HM6167P. HM6167P-6. HM6167P-8
OUTPUT LOW CURRENT vs.
OUTPUT LOW VOLTAGE
OUTPUT HIGH CURRENT vs.
OUTPUT HIGH VOLTAGE
.s
.6
,
.4
.2
.0
1
<3
~
0, 8
:;;
..
.0
!I:
..'l
fr
6
~
o. 4
Output High Voltage
"
II.
0,6
V
,
n.
VOH
/
,
I
V
Ta;2S'C
r(C'=5V
tl.4
0.8
0.6
Output Low Voltage
(V)
VOl.
(V)
STANDBY CURRENT vs.
SUPPLY VOLTAGE
STANDBY CURRENT vs.
AMBIENT TEMPERATURE
10
/
~
<3
'\
.s
j
.2
\
'\
~
~
Ta=25"C
Vcc=5V
..
"'
l-cc=3V
CS=2.8V
.2
.,
.11
.
V
V
10" 1
b
V
V
0
.,.V
c
~
/'
u
i
u.b
n.
'l./
V
7=
1iJ=25'C
~cc-O.2V
n. 2
,0
20
/
" ."
~
V
/
80
60
Supply Voltage Vee (V)
Ambient Temperature Ta ("C)
STANDBY CURRENT vs.
INPUT VOLTAGE
0
Ta=2S'C
Vcc=S.OV
CS=4.8V
8
;;
6
~
\
•
1\......
2
U
'"
Input Voltage
v..
(V)
•
HITACHI
187
HM6167LP, HM6167LP-6,
HM6167LP-8
16384-word x 1-bit High Speed Static CMOS RAM
.FEATURES
• Single +5V Supply and High Density 20 Pin Package
• Fast Access Time ..•••••••••.•..••...• 70ns/85ns/1 OOns
• Low Power Stand·by and Low Power Operation
Stand-by 5IJ.W (typ) and Operating 150mW (tyP.)
• Completely Static Memory .•.••. No Clock or Refresh Required
• Fully TTL Compatible .••.•.•.•.••.. All Inputs and Output
• Separate Data Input and Output .••..•••• Three State Output
• Capable of Battery Back up Operation
.BLOCK DIAGRAM
(DP-ZO)
~Vee
~GNO
Row
Memory Array
Decoder
I28XI28
.PIN ARRANGEMENT
0...,
Din
.ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Rating
Unit
Terminal Voltage with Respect to GND
Vr
-0.5 to +7.0
V
Power Dissipation
Pr
1.0
W
+70
·c
·c
Operating Temperature
To"
Storage Temperature
hr•
o to
-55 to, +125
(Top View)
• RECOMMENDED DC OPERATING CONDITIONS (O·C;>;Ta;>;70·C)
Item
Symbol
min
4.5
Vee
Supply Voltage
GND
typ
max
Unit
5.0
5.5
V
0
V
Input High Voltage
V,H
2.2
-
6.0
V
Input Low Voltage
V,L
-0.5
-
0.8
V
188
0
•
HITACHI
0
-----------------------------------------HM6167LP,HM6167LP-6,HM6167LP-8
.TRUTH TABLE
CS
WE
Mode
H
X
Not Selected
L
H
Read
Icc
Dout
L
L
Write
Icc
High Z
Vee Current
Iss,
Output Pin
Reference.Cycle
High Z
ISBI
Read Cycle 1. 2
Write Cycle
i. 2
.DC AND OPERATING CHARACTERISTICS (Vcc-5V±10%, Ta=O-+70·C)
Symbol
Item
Test Conditions
min
typ
max
Unit
V,N-OV- Vee
-
-
2
pA
-
-
2
pA
30
60
mA
-
5
20
mA
-
1
50
pA
0.4
V
-
V
Input Leakage Current
Output Leakage Current
I ILl I
Ihol
CS-V,H. Il.,-OV-Vce
Operating Power Supply Current
Icc
CS -
Is.
CS-V,H
Standby Power Supply Current
Vee-5.5V
v, ••
Output Open
CS-Vce-0.2V
lssl
V,_lOO.2V or '" Vee-0.2V
-
Output Low Voltage
Yo.
Io.-8mA
Output High Voltage
VOH
IOH--4mA
2.4
-
Note) Typical limits are at Vcc -5.0V. Ta-2S"C and specified JoadiRl'•
• AC TEST CONDITIONS
Output Load A
Input pulse levels: GND to 3.0V
Input rise and fall times: 5 ns
Input timing reference levels: 1.5V
Output reference levals: 1.5V
Output load: See Figure
Output Load B
(for
+5V
tHZ.
tu. twz & tow)
-~: ~'-=d:.
+5V
• Including scope and iii.
• CAPACITANCE (Ta=25·C,j=1.0MHz)
Symbol
max
Unit
Input Capacitance
Item
CI_
5
pF
V,N-OV
Output Capacitance
COUT
6
pF
VOVT-OV
Conditions
Note) This parameter is sampled and not 100% tested.
• AC CHARACTERISTICS (Ta=O·C to +70·C. Vee = 5V±10%, unless otherwise noted.)
eREAD CYCLE
Item
Symbol
HM6167LP-6
HM6167LP-8
min
HM6167LP
max
min
max
min
70
-
85
-
100
-
ns
-
70
-
85
-
100
ns
85
-
100
ns
ns
max
Unit
'Read Cycle Time
IRe
Address Access Time
I ••
Chip Select Access Time
tACS
Output Hold from Address Change
10H
5
-
5
-
5
Chip Selection to Output in Low Z
Itz
5
-
5
-
5
-
Chip Deselection to Output in High Z
1HZ
0
30
0
40
0
40
ns
Chip Selection to Power Up Time
Ipv
0
-
0
-
0
-
ns
Chip Deselection to Power Down Time
I ..
45
ns
-
•
70
35
HITACHI
-
40
-
ns
189
HM6167LP,HM6167LP·6,HM6167LP·S-----------------------------------------eTIMING WAVEFORM OF READ CYCLE NO.1
1),2)
Mdresa
Dlta Out
Data V.lid
eTIMING WAVEFORM OF READ CYCLE NO.2 1),3)
Data V.lid
Dna Oat
Cnrant
NOTES: 1.
WE is high and CS" is low for READ Cycle,
2. Addresses valid prior to or coincident with cs transition low.
3. Transition is measured
specified loading B.
±soOmV
from steady state voltage with
eWRITE CYCLE
Symbol
Item
HM6161LP-6
HM6161LP
min
max
min
HM6167LP-8
max
min
max
Unit
Notes
2
Write Cycle Time
Iwe
70
-
85
-
100
-
ns
Chip Selection to End of Write
lew
55
65
-
80
-
ns
Address Valid to End of Write
lAW
55
-
Address Setup Time
lAS
0
-
0
Write Pulse Width
Iwp
40
-
45
Write Recovery Time
Iw.
0
0
Data Valid to End of Write
low
30
-
35
-
Data Hold Time
10.
0
-
0
Write Enable to Output in High Z
Iwz
0
30
Output Active from End of Write
low
0
-
-
ns
:!...
ns
55
-
ns
0
-
ns
40
-
ns
-
0
-
ns
0
40
0
40
ns
3,4
0
-
0
-
ns
3,4
65
.
Notes) 1. If CS goes high simultaneouly with WE high. the output remains in a high impedance state.
2. All Write Cycle timings are referenced from the last valid address to the first transitioning address.
3. Transition is measured ±500mV from steady state voltage with specified loading in Load B.
4. This parameter is sampled and not 100% tested.
..,
eTIMING WAVEFORM OF WRITE CYCLE NO.1 (WE Controlled)
Addr•••
.,.
."
Data In
Data Out
190
Data Undefined
•
HITACHI
80
0
- - - - - - - - - - - - - - - - - - - - H M 8 1 8 7 L P , HM8187LP-8, HM8187LP-8
eTIMING WAVEFORM OF WRITE CYCLE No.2 (CS Controlled)
Add,. ..
,.,
--.,
---'
...
l::::::::-l
\
I ••
I,.
I.
\ \ \ \ \
...
I
*
na,. Out
DUI
III
I ..
J.
Ot,a'JLV.11cl
_I
I ••
~
Undefined
HI.h .,..tlfte.
.LOW Vee DATA RETENTION CHARACTERISTICS (Ta-O'C to 70·C)
Parameter
Symbol
Vee for Oat. Retention
Telt Condition
V••
2.0
-
CSOi: Vcc-0.2V
O.ta Retention Current
IccD"
Chip Deselect to O.t. Retention Time
tCDR
Operation Recovery Time
II
min
v..Oi: Vcc-0.2V or
OV:iO V..:iOO.2V
0
hc6
.0..
be-Rod Cyele Time
typ
max
Unit
-
-
V
-
-
20·
pA
30··
-
n.
n.
•
*.
Vcc-Z.OV
Vcc",.OV
.LOW Vee DATA RETENTION WAVEFORM
Vrc------_,
4.5V---------
nata Retention Mode
--- ------ ----- -- - - - - - - ---
-----.---
Ci 2' v(·(·-n.2\,
e1 _ _ _.1
ov _______________________________________ ~ ____ _
•
HITACHI
191
HM6167H-45, HM6167H-55,
HM6167HP-45, HM6167HP-55
16384-word x l-bit' High Speed Static CMOS RAM
• FEATURES
45ns (max)
• Fast Access Time ••.....••.• HM6167H/P·45
55ns (max)
HM6167H/P·55
• Low Power Standby and Low Power Operation
Standby 100~W (typ). Operating 200mW (typ)
• Single +5V Supply and High Density 20 Pin Package
• Completely Static Memory .•.. No Clock nor Refresh Required
• Fully TTL Compatible .•.••.• AII Inputs and Output
• Separate Data Input and Output ••••••.•. Three State Output
HM6167H-4S, HM6167H-SS
(00-20)
• BLOCK DIAGRAM
HM6167HP·4S, HM6167Hp·SS
~vcc
~GND
A.--[::::d
A,
Memorv Array
128X 128
A. ---{::t:I
An
Au
DOlI'
Din
(DP-20)
• PIN ARRANGEMENT
• ABSOLUTE MAXIMUM RATINGS
Item
Terminal Voltage with respect to GND
Power Dissipation
Operating Temperature
Storage Temperature (Plastic)
Storage Temperature (Ceramic)
Storage Temperature (under bias)
Symbol
Rating
-3.5* to +7.0
VT
1.0
I'T
o to +70
TOl'r
-55 to +125
Totti
-65 to +150
Totti
-10 to +85
Tbi...
Unit
V
W
·C
·C
·C
·C
• Pulse Width 2Ons, DC: -O.S?,
• RECOMMENDED DC OPERATING CONDITIONS (Ta
Item
Supply Voltage
Input Voltage
Symbol
Vee
GND
VIH
VIL
• Pulse Width: 20ns, DC: VIL (mm)
192
min
4.5
0
2.2
-3.0·
typ
5.0
0
-
max
5.5
0
6.0
0.8
=0 to +70oC)
Unit
V
V
V
V
=-O.SV
_HITACHI
- - - - - - - - - - - - - - H M 6 1 6 7 H - 4 5 , HM6167H-55, HM6167HP-45, HM6167HP-55
• TRUTH TABLE
Ref. Cycle
CS
WE
Mode
Vee Current
Dout Pin
H
X
Not selected
/S8, IS81
High-Z
L
H
Read
Icc
Dout
Read Cycle
L
Write
Icc
High-Z
Write Cycle
L
.DC AND OPERATING CHARACTERISTICS (Vcc-5V±10%, TIJ-O't') to +70't')
Symbol
Item
Test Conditions
Unit
2
,.A
-
2
,.A
CS- V,L, Output Open
40
80
mA
CS- V,H
-
10
20
mA
-
0.02
2
mA
-
-
0.4
V
-
V
Output Leakage Current
CS-ViH, VOVT-OV- Vee
Operating Power Supply Current
Icc
I ..
CS ~Vee-0.2V
Standby Power Supply Current
max
-
I ILl I
11.01
Input Leakage Current
typ
min
Vee-5.5V, Vi.-OV-Vcc
lUI
V,."0.2V or 0: Vee-0.2V
Output Low Voltale
VOL
IOL-8mA
Output High Voltage
VOH
IOH--4mA
2.4
Note) Typical limits are at Vcc -5.0V. Ta-25t .nd specified loadi....
• AC TEST CONDITIONS
Output Load B
Output Load A
Input pulse levels: GND to 3.0V
Input rise and fall times: 5 ns
Input timing reference levels: 1.5V
Output reference levels: 1.5V
Output load: See Figure
( for 1HZ, hz, Iw. & low)
+5V
~.~.:,.
• Includina scope and
ii,.
+5V
Do ..
~
255Q
80g
5pF·
• Inchllllilll' scope .nd iii.
• CAPACITANCE (TIJ=2S'C, J-1.0MHz)
typ
max
Unit
Input Capscitance
C,.
3
5
pF
v,.-OV
Output Capacitance
COUT
5
7
pF
VOVT-OV
Item
Symbol
Conditions
Note) This parameter i. sampled and not 100% tested.
•
HITACHI
193
HM6167H-45. HM6167H-55, HM6167HP-45. H M 6 1 6 7 H P - 5 5 - - - - - - - - - - - - - - -
.AC CHARACTERISTICS (Vcc=5V±10%. Ta=O·C
to 70·C. unless otherwise noted.)
-READ CYCLE
Item
Symbol
HM6167H/P-45
min
HM6167Hp·55
max
min
max
Unit
Notes
(I)
Read Cycle Time
IRC
45
-
55
-
ns
Address Access Time
IAA
-
45
-
55
ns
Chip Select Access Time
lACS
-
45
-
55
ns
Output Hold from Address Change
IOH
5
-
5
ns
Chip Selection to Output in Low Z
ILZ
5
-
5
-
ns
(2) (3) (7)
Chip Deselection to Ou!pu t in High Z
1HZ
0
30
0
30
ns
(2) (3) (7)
Chip Selection to Power Up Time
IPU
0
-
0
-
ns
Chip Deselection to Power Down Time
IPD
30
-
30
ns
-
NOTES: 1. All Read Cylce timing are referenced from last valid address to the first transitioning address.
2. At any given temperature and voltage condition, tHZ max. is less than t LZ min. both for a given device and
from device to device.
3. Transition is measured ±500mV from steady state voltage with specified loading in Load B.
4. WE is High for READ cycle.
5. Device is continuously selected, CS = VlL. _
6. Addresses valid prior to or coincident with CS transition low.
7. This parameter is sampled and not 100% tested.
-TIMING WAVEFORM OF READ CYCLE NO.1 4 ), 5)
Address
~
'.C-----l~r-
t---
~
tOH
Data Out
Previous Data
Valid
Data Valid
-TIMING WAVEFORM OF READ CYCLE NO.2 4 ),6)
~-----tRC------~r_-----
CS
Data Valid
Data Out
v" Supply
Current
194
ISB
eHITACHI
- - - - - - - - - - - - - - H M 6 1 6 7 H - 4 5 . HM6167H-55. HM6167HP-45. HM6167HP-55
• WRITE CYCLE
HM6167H/P-45
Symbol
Item
min
HM6167H/P·55
max
min
max
Unit
Notes
ns
(2)
twc
tcw
tAW
45
-
55
40
-
50
tAS
twp
0
0
25
-
-
35
-
ns
0
-
0
-
ns
25
-
25
-
ns
0
-
0
-
ns
Write Enable to Output in High Z
tDH
twz
0
25
0
2S
ns
(3)(4)
Output Active from End of Write
tow
0
-
0
-
ns
(3) (4)
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
tWR
tDW
Data Valid to End of Write
Data Hold Time
NOTES: 1.
2.
3.
4.
40
50
ns
ns
ns
If Cs goes high simultaneously with WE high, the output remains in a high impedance states.
All write cycle timings are referenced from the last valid address to the flISt transitioning address.
Transition is measured ±SOOmV from steady state voltage with specified loading in Load B.
This parameter is sampled and not 100% tested.
eTIMING WAVEFORM OF WRITE CYCLE (WE Controled)
~---------,twc----------~
Address
Data In
tow~r--
WZj
Data Out
_D_a_ta_U_n_d_e_fm
__
ed________..J) High Impedance~
• TIMING WAVEFORM OF WRITE CYCLE
(CS Controled)
twc
Address
----.
~
1'---
--..J
~
tcw
'\
tWR
tAW
r-----twP
/ / /
\ \ \ \ \
I
Data In
Data Out
*
Data Undefined
•
tDH
tDW
Data In Valid
)(
twz
,I
High Impedance
HITACHI
195
HM6167H-45, HM6167H-55, HM6167HP-45, H M 6 1 6 7 H P - 5 5 - - - - - - - - - - - - - SUPPLY CURRENT
SUPPLY VOLTAGE
SUPPLY CURRENT VS.
AMBIENT TEMPERATURE
VS.
.6
6
\-h=5.0V
Ta=2S'C
1.4
1.4
2
1.0
.........
O. 8
~
v---
V
./
2
Or-o
r----
0, 8
~
~
J
Jj
o. 6
O. 4
4.5
4.75
5.0
0, 6
o.40
5.5
5.25
-
20
40
60
ACCESS TIME vs.
SUPPLY VOLTAGE
ACCESS TIME VS.
AMBIENT TEMPERATURE
3
1. 3
Vcc=5.QV
Ta::=2S'C
1.2
2
1. 1
1. 1
0
r---1'---
--
O. 9
~
o~
r--
~
~
o. 9
o. 8
O.8
O. 7
80
Ambient Temperature Ta ('C)
Supply Voltage Vee (V)
4.5
5.25
5.0
4.75
o. 7
5.5
0
20
Supply Voltage Vee (V)
60
40
80
Ambient Temperature Ta rC)
ACCESS TIME VS.
LOAD CAPACITANCE
SUPPLY CURRENT
FREQUENCY
1.8
200
.1
VS.
100
66
50
lOOns 85ns
./
1. 6
.0
V
.4
/
.2
V
./
.9
~
]
100
200
300
Load Capacitance Q
196
0 .7
.6
400
500
(pFJ
O. 50
/
10
Frequency
eHITACHI
L
L
/
(3
.8
.6
/
.8
.0/
V
V
40
700s
15
f
(MHz)
20
25
- - - - - - - - - - - - - HM8187H-45, HM8187H-55, HM8187HP-45, HM8187HP-55
v•.
INPUT LOW VOLTAGE
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE
SUPPLY VOLTAGE
v•.
1.3
1.3
To-25"C
T,=25'C
1.2
.2
1
1. 1
0
o.9
~
---
I..--"
l---
1.0
o.8
o.8
O. 7
4.5
5,0
4.75
OUTPUT CURRENT
OUTPUT VOLTAGE
1~
1. 2
..,::
o.8
1
o.6
v•.
5.0
5.5
5.25
Vcr (V)
.
OUTPUT CURRENT VI.
OUTPUT VOLTAGE
.6
T,=25'C
)
V('c=5V
.4
/
2
\
1.0
\
o.8
\
/
0.6
0.4
Output High Voltage
VtIH
I
V
T,-25'C
Vrc=5V
V
\
O. 4 1
0.2
O.~
0.4
0.8
Output Low Volta.e VtJl. (V)
(V)
STANDBY CURRENT w.
SUPPLY VOLTAGE
STANDBY CURRENT v•.
AMBIENT TEMPERATURE
10'
4.75
Supply Volta,e
~
0
-- --
(VI
,
1.6
1.4
VCl'
O. 7 4.5
5.5
5.25
Supply Volt'liCe
]
~
o.9
~
.
.4
Vcc=3V
a:=2.8V
.2
,
.0
.
V~
./
V
V
o. 8
o.6
o.
,
10
2"
40
/
/
T,=2S'C
9=VC/'-0.2V
O. 2,
80
60
4V
V
./
V
V
/
Supp Iy Voltage \i'l' (V)
Ambient Temperature Ta ("C)
•
HITACHI
197
HM6167H·45, HM6167H·55, HM6167HP·45, H M 6 1 6 7 H P · 5 5 - - - - - - - - - - - - - STANDBY CURRENT vs.
INPUT VOLTAGE
0
Ta=25'C
~=5.0V
=4.8V
8
..
6
\
4
2
1\
\
~ ..........
Input Vo Itage
198
v,.
(V)
•
HITACHI
HM6167HCG-46,HM6167HCG-6616384-word x 1-bit High Speed Static CMOS RAM
.FEATURES
• High Density 20 pin Leadless Chip Carrier
• High Speed: Fast Access Time 45/55ns Max.
• Low Power Standby and Low Power Operation
Standby: 100llW typ., Operation: 200mW typo
• Completely Static Memory;
No Clock or Timing Strobe Required
• Equal Access and Cycle Times
• Directly TTL Compatible; All Inputs and Output
~
~
.BLOCK DIAGRAM
(CG-ZO)
A.
~V('r
A,
~GND
A.
A,
Huw
A.
Uf'coder
.PIN ARRANGEMENT
Memorv Arrav
12RXl2R
Au
An
Din
DOUl
CS
(Bottom View)
.ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
Voltage on Any Pin·
V,
-0.5 to +7.0
V
Power Dissipation
p,
1.0
W
Operating Temperature
Item
Unit
Top.
o to
+70
·C
Storage Temperature
Td •
-65 to +150
·C
Temperature Under Bias
Til, ..
-10 to +85
·C
VIN min--3.SV (Pulse width 2Ons)
• with respect to GND•
• TRUTH TABLE
CS
WE
Mode
Vee Current
Oout Pin
H
X
Not selected
1S8, ISBI
High-Z
Ref. Cycle
L
H
Read
lee
Dout
Read Cycle
L
L
Write
lee
High-Z
Write Cycle
•
HITACHI
199
HM6167HCG·45,HM6167HCG·55 - - - - - - - - - - - - - - - - - - - - - -
..
• RECOMMENDED DC OPERATING CONDITIONS (Ta=O to +70·C)
Item
Symbol
Vee
Supply Voltage
-:nin
typ
max
4.5
5.0
5.5
V
0
0
0
V
GND
Input Voltage
*
Unit
V'H
2.2
-
6.0
V
VfL
-0.5'
-
O.S
V
-S.OV (Pulse width 200s)
.DC AND OPERATING CHARACTERISTICS (Vcc=5V ±10%. Ta=O w +70·C)
Item
Symbol
Test Conditions
2
JlA
-
2
JlA
40
SO
mA
10
20
mA
Unit
CS - VfL• Output Open
ISBl
CS<:Vee-0.2V. VfN:;;0.2V or V{N;;;Vee-0.2V
-
20
2000
JlA
VOL
IoL-SmA
-
-
0.4
V
VOH
IOH--4mA
2.4
-
-
V
I ho I
CS- V'H. VOUT-OV to Vee
Note) • : Typical limits are at Vcc-S.OV.
max
CS- VfH
Output Leakage Current
Output Voltage
-
Icc
Vee~5.5V.
Standby Power Supply Current
typ·
Iss
I ILl I
Operating Power Supply Current
min
-
Input Leakage Current
TIJ-25~
V'N-OV to Vee
and specified loading .
• CAPACITANCE (Ta=25·C. /=lMHz)
typ
max
Unit
Input Capacitance
C"
v..-OV
3
5
pF
Output Capacitance
Co..,
v... -OV
5
7
pF
Item
Note)
Symbol
Test Conditions
'{his parameter is sampled and not 100% tested.
• AC CHARACTERISTICS (Vcc =5V ±10%. Ta=O to +70·C)
Output Load A
.AC TEST CONDITIONS
Input Pulse Levels: GND to 3.0V
Input Rise and Fall Times: 5 ns
Output Reference Levels: 1.5V
Output Load B
( for
+5V
~'~:'
tHZ.
tLz. twz & tow)
+5V
~,~:"
* Including scope and jig.
• READ CYCLE
Item
HM6167HCG-45
HM6167HCG-55
min
max
min
Symbol
Unit
Notes
1
max
Read Cycle Time
tRe
45
-
55
-
ns
Address Access Time
tAA
-
45
-
55
ns
Chip Select Access Time
tACS
-
45
-
55
ns
Output Hold from Address Change
tOH
5
-
5
-
ns
Chip Selection to Output in Low Z
tLZ
5
-
5
-
ns
2.3.4
Chip Deselection to Output in High Z
1HZ
0
30
0
30
ns
2.3.4
Chip Selection to Power Up Time
Ipu
0
-
0
-
ns
Chip Deselection to Power Down Time
IPD
30
ns
Notes) 1.
2.
3.
4.
200
-
30
-
All Read Cycle timings are referenced from last valid address to the first transitioning address.
At any given temperature and voltage condition. lHZ max is less than hz min both for a given devicE' and from device to device.
Transition is measured ±SOOmV from steady state voltage with specified loading in Load B.
This parameter is sampled and not 100% tested.
•
HITACHI
- - - - - - - - - - - - - - - - - - - - - - H M 6 1 6 7 H C G - 4 5 , HM6167HCG-55
eRead Cycle-1 (Notes 1,2)
'/IC
Address
'AA
'.N
Previous
Data Valid
Data Out
Data Valid
eRead Cycle-2 (Notes 1,3)
Ie
~
J
\.
lACS
tHr31
tu,l3I
V
HiRh Impedance
Data Out
"
Vee Supply
Curr.nt
'V
'"
J
1"---'f
~
Data V.11d
J
I
Hish Impedance
I
"0
I..
Notes) 1., WE is high for Read Cycle.
2. Address valid prior to or coincident with CS transition low.
3. Transition i. mea.ured ±500mV from ,teady atate volta.e with specified loadina: in Load B.
eWRITE CYCLE
HM6167HCG-45
Item
Notes
-
ns
2
-
ns
50
-
ns
0
-
ns
35
ns
max
min
max
-
55
50
-
Write Cycle Time
twe
.45
tew
40
Address Valid to End of Write
tAW
40
Address Setup Time
t ..
0
Write Pulse Width
twp
25
Write Recovery Time
two
0
Data Valid to End of Write
tow
25
Data Hold Time
to.
Write Enable to Output in High Z
Output Active from End of Write
-
Unit
min
Chip Selection to End of Write
Notes} 1.
2.
3.
4.
HM6167HCG-55
Symbol
25
0
-
0
-
twz
0
25
0
25
ns
3,4
tow
0
-
0
-
ns
3,4
-
0
ns
ns
ns
If CS goes high simultaneouly with WE high. the output remains in a higb impedance state.
All Write Cycle timings are referenced from the last valid address to the first transitioning address.
Transition is measured ±500mV from steady state voltage with specified loading in Load 8.
This parameter is sampled and not 100% tested.
•
HITACHI
201
HM6167HCG-45. H M 6 1 6 7 H C G - 5 5 - - - - - - - - - - - - - - - - - - - - - - - - '
..,
eWrite Cycle-1 (WE Controlled)
..
Address
...
'AS
Data In
Data Out
Data Undefined.
eWrite Cycle-2 (CS
Address
Control:~d)
..,
----""'\
----'
'"
I
."
I
\.
...
tAli'
""'\
'"
I II
\ \ \
I
...
tD.'
t
Data In
Data In Valid
.
h'z
Data
Out
Data Undefined
202
Hi",h Impedance
_HITACHI
:(
HM6167HLP-45, HM6167HLP-55x 1-bit High Speed Static CMOS RAM
16384-word
• FEATURES
• Fast Access Time •..•..•.... HM6167HLP·45 45ns (max)
HM6167HLP-55 55ns (max)
• Low Power Standby and Low Power Operation
Standby 51lW (typ) and Operating 200mW (typ)
• Capable of Battery Back-up Operation
• Single +5V Supply and High Density 20 Pin Package
• Completely static Memory
No Clock or Timing Strobe Required
• Equal Access and Cycle Times
• Directly TTL Compatible ..... AII Inputs and Output
(DP-20)
• BLOCK DIAGRAM
"'--[;0
~vcc
A,-----...o-o
~GNO
A.-----.........
Al--I:xl
A,
• PIN ARRANGEMENT
Row
Memorv Arrav
Selecl
128X 128
Oou.
Dm
• ABSOLUTE MAXIMUM RATINGS
Item
Tenninal Voltage with respect to GND
Power Dissipation
Operating Temperature
Storage Temperature
Storage Temperature Under Bias
* Pulse Width 2Ons, DC: -O.SV
Symbol
VT
PT
Topr
T,t/l
TblOl
• RECOMMENDED DC OPERATING CONDITIONS (Ta
Item
Supply Voltage
Input Voltage
* Pulse Width 20ns, DC:
Symbol
Vee
GND
V,H
VIL
min
4.5
0
2.2
-3.0·
typ
5.0
0
-
-
Unit
V
W
·C
·C
·C
Rating
-3.5· to +7.0
1.0
oto +70
-55 to +125
-10 to +85
max
5.5
0
6.0
0.8
=0 to +70°C)
Unit
V
V
V
V
VIL min = -0.5V
•
HITACHI
203
HM6167HLP-45, H M 6 1 6 7 H I . P - 5 5 - - - - - - - - - - - - - - - - - - - - - -
• TRUTH TABLE
cs
WE
Mode
H
X
Not selected
lSI,
Ref. Cyete
Dout Pin
Vee Current
High-Z
IS81
L
H
Read
lee
Dout
Read Cycle
L
L
Write
lee
High-Z
Write Cycle
_x
.DC AND OPERATING CHARACTERISTICS (Vee-SV±lO%, Ta-O-+70'C)
Symbol
Item
Te.t Conditions
min
typ
-
-
2
2
pA
pA
40
10
80
mA
20
mA
1
50
pA
0.4
V
-
V
Input Leakqe Current
Output Leakage Current
liL,l
liLol
Operating Power Supply Current
lee
CS-V,L. Output Open
-
I ..
CS-V,.
--
Standby Power Supply Current
Vee-5.5V
v,.-OV-Vee
CS-v, •• V.. -OV-Vee
CS-Vee-0.2V
lUI
V,.liOO.2V or Oi: Vee-0.2V
-
Output Low Voltage
VOL
IOL-8mA
Output High Voltage
VOH
lo.--4mA
Unit
-
2.4
Note) Typical limita are at Vee-I.OV. T.-25·C and apec:ified loadlnc.
• AC TEST CONDITIONS
Output Load A
Input pulse levels: GND to 3.0V
Input rise and fall times: 5 ns
Input timing raference levels: 1.5V
Output reference levell: 1.5V
Output load: See Figure
Output Load B
+sv
(for 'liZ, tLZ, h,z I: tow)
+sv
~,~:"
Do ..
~
25SQ
* Including scope and jig.
80g
SpF'
• Including scope and jig.
_x
• CAPACITANCE (Ta-2S·C,J-l.OMHz)
Symbol
typo
Input Capacitance
item
C,.
3
5
pF
v,.-OV
Output Capacitance
COUT
5
7
pF
VOUT-OV
Note) Thil parameter is ....pled and not 100%
Unit
Conditions
t ••ted •
• AC CHARACTERISTICS (Ta-O'C to +70'C, Vee - SV±lO~, unless otherwise noted.)
eREAD CYCLE
Item
Symbol
HM6167HLP-45
HM6167HLP-55
min
max
mb!
Read Cycle Time
IRC
45
-
55
Address Access Time
tAA
-
45
-
Chip Select Access Time
lACS
45
-
Output Hold from Address Change
IOH
5
Chip Selection to Output b! Low Z
tLZ
Chip Selection to Output in High Z
-
Unit
Notes
-
ns
(I)
55
ns
max
55
ns
5
-
ns
5
-
5
-
ns
(2)(3) (7)
1HZ
0
30
0
30
ns
(2)(3)(7)
Chip Selection to Power Up Time
tpu
0
-
0
-
ns
Chip Deselection to Power Down Time
tPD
30
-
30
ns
-
NOTES: 1. All Read Cylce timing are referenced from last valid address to the first transitioning address.
2. At any given temperature and voltage condition, 'HZ max. is less than tLZ min. both for a given device and
from device to device.
3. Transition is measured ±SOOm V from steady state voltage with specified loading in Load B.
4. WE is High for READ cycle.
5. Device is continuously selected, CS = VlL .
6. Addresses valid prior to or coincident with CS transition low.
7. This parameter is sampled and not 100% tested .
204
•
HITACHI
-----------------------------------------------HM6167HLP-45,HM6167HLP-55
eTIMING WAVEFORM OF READ CYCLE NO.1
4) 5)
------------tRe----------~j~
-:-----/iL~
tru:
Address
t AA------J
,.--------
Previous Data
Valid
Data Out
Data Valid
eTIMING WAVEFORM OF READ CYCLE NO.2 4)
6)
Data Out
Data Valid
Vee Supply
Current
e
WRITE CYCLE
HM6167HLP-45
Symbol
Item
HM6167HLP-55
min
max
min
-
55
max
Unit
Notes
ns
(2)
Address Valid to End of Write
tAW
40
-
50
-
Address Setup Time
tAS
0
-
0
-
ns
Write Pulse Width
twp
25
-
35
ns
Write Recovery Time
tWR
0
-
0
-
Oat. Valid to End of Write
tDW
25
25
tDH
0
0
-
ns
Data Hold Time
-
Write En.ble to Output in High Z
twz
0
2S
0
2S
ns
(3) (4)
Output Active from End of Write
tow
0
-
0
-
ns
(3) (4)
Write Cycle Time
twc
45
Chip Selection to End of Write
tcw
40
50
ns
ns
ns
ns
NOTES: 1. If CS goes high simultaneously with WE high, the output remains in a high impedance states.
2. All Write Cycle timings are referenced from the last valid address to the fust transitions address.
3. Transition is measured ±50OmV from steady state voltage with specified loading in Load B.
4. This parameter is sampled and not 100% tested.
e TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE Controlled)
twe
Address ~V
W
j
-J.
tew
L
CS
1
f-----tAs_
tAW
__ twR __
twp
\\\
j
EDWtam
~d
Din
-twz
.e:.r
DH
)K
I---tow
-----------j
High Impedance
"1----Dout
..AJ----:;;..~---i(~_ _
•
HITACHI
205
HM6167HLP·4S, H M 6 1 6 7 H L P · S S - - - - - - - - - - - - - - - - - - - - - -
e TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS ControUed)
~----------------twe----------------~~
.
-- ~--j''---AW
tAS-
-tWR
,
CS
tew
1\
twp
\
WE
-tDwDin
tDH
Data in Valid
-----------------------~~~----~~~p--------twz
Dout
. hIm edance
.LOW Vee DATA RETENTION CHARACTERISTICS (Ta=O·C to 70·C)
Parameter
Vee for Data Retention
Data
Reten~ion
Symbol
Test Condition
VD•
CS~
Current
Chip De.elect to Data Retention Time
tCDR.
Operation Recovery Time
t.
typ
max
Unit
2.0
-
-
V
-
20·
-
30"
0
-
hell.
-
-
Vcc-O.2V
-
Vcc-0.2V or
-
IceDs
v,.~
min
OVS V,.SO.2V
6.
he - Read Cycle Time
eLOW Vee DATA RETENTION WAVEFORM
Data Retention Mode
vee------------~I
4.SV--------- -------------------------
---------
2.2V------
VDR -----
CS!1; Vee-O.2V
CS------.J
OV---------------------------------------------
206
•
HITACHI
pA
n.
n.
•
VCt -2.0V
•• Vcc-3.0V
HM6264P-10, HM6264P-12,
HM6264P-15
8192·word x 8-bit High Speed Static CMOS RAM
• FEATURES
1OOns/120nsl150ns (max.)
• Fast access Time
Standby:
O.1mW (typ.)
• Low Power Standby
Low Power Operation
Operating: 200mW (typ.)
• Single +5V Supply
• Completely Static Memory ..•.. No clock or Timing Strobe Required
• Equal Access and Cycle Time
• Common Data Input and Output, Three State Output
• Directly TTL Compatible: All Input and Output
• Standard 28pin Package Configuration
• Pin Out Compatible with 64K EPROM HN482764
(DP·28)
• BLOCK DIAGRAM
• PIN ARRANGEMENT
,,<>----t:£==~-,
...
MelllOr, M.trill
--oCND
NC
2~X256
Detoder
VCC
A,.
11<> c>--?H:.-f--I
A3
CSI
A.
~~---'------,-------~
A,
,,,0-----------..1
• ABSOLUTE MAXIMUM RATINGS
Item
Terminal Voltage *
Power DiSsipation
Operating Temperature
Storage Temperature
Storage Temperature (Under Bias)
.. With respect to GND.
• TRUTH TABLE
WE CS, CS. OE
X
H
X
X
X
XL
X
H
H
L
L
L
L
L
L
H
H
H
H
H
L
H
L
Symbol
VT
PT
Top.
Tata
Rating
-0.5 ... to +1.0
1.0
o to +10
-55 to +125
-10 to +85
Thlas
.. Pulse width SOns: -3.0V
Mode
Not Selected
Unit
V
W
(Po~rDown)
Write
1/0,
°c
°c
°c
(Top View)
I/O Pin
High Z
HighZ
High Z
Dout
Din
Din
Output Disabled
Read
1/0.
Vee Current
/8B,/8Bl
/8B,/8B2
/CC'/CCI
/CC,ICCl
/CC'/CCI
/CC,ICCl
Note
Write Cycle (1)
Write Cycle (2)
x : Don'l care.
•
HITACHI
207
HM8284P·10, HM8264P·12, H M 6 2 8 4 P · 1 5 - - - - - - - - - - - - - - - - - -
• RECOMMENDED DC OPERATING CONDITIONS (To = 0 to +70°C)
Symbol
Vee
OND
V,H
Input Voltage
VIL
• Pulse Width SOns: -3.0V
Item
typ
5.0
0
min
4.5
0
2.2
-0.3*.
Supply Voltage
max
5.5
0
6.0
0.8
-
Unit
V
V
V
V
• DC AND OPERATING CHARACTERISTICS (Vee = SV± 10%, GND = OV, To = 0 to +70°C)
Test Condition
Symbol
Item
Input LeaJcage Current
Output Leakage Current
min
Ihll
Vln-OND to Vce
-
Ihol
CSl"V,H or CS2==V,L or OE"VIH, V,/o*OND
to Vee
-
Operating Power Supply Current
Icc
CSI-VIL, CS2-V,H,II/O-OmA
Average Operating Current
lecl
Min. cycle, duty-l00%, CSi-V,L. CS2=W'H
ISB
CSI"V,H or CS2"V,L,II/O-OmA
ISBI··
CSI~Vec-0.2V, CS~Vee-0.2Vor CS2~0.2V
ISBZ'"
CS2~0.2V
Standby Power Supply Current
VOL
Ou tput Volt8jle
VOH
IOL"2.lmA
--
IOH"-1.OmA
-
2.4
typ* max
-
2
Unit
/loA
2
/loA
40
80
mA
60
110
mA
I
3
2
mA
mA
2
mA
0.02
0,02
-
0.4
- -
V
V
• Typical limits are at Vee-S.OV, Ta-2S·C and specified loading.
•• V'L mln--0.3V
• CAPACITANCE (f= IMHz, To = 25°C)
typ
Symbol Test Condition
Item
Input Capacitance
V'n" OV
e'n
Input/Output Capacitance
ello
VI/o" OV
Note) This parameter is sampled and not 100% tested.
-
max
6
8
Unit
pF
pF
• AC CHARACTERISTICS (Vee" 5V±10%. Ta" 0 to +70°C)
• AC TEST CONDITIONS
I nput Pulse Levels: 0.8 to 2.4V
Input Rise and Fall Times: 10n.
Input and Output Timing Reference Level: 1.6V
Output Load: 1TTL Gate and CL • 100pF (Including scope and jig)
• READ CYCLE
Item
Symbol
HM6264P-10
min
max
100
-
HM6264P.12
HM6264P.IS
min
max
min
max
Unit
120
ISO
-
-
-
-
100
-
ISO
ns
ns
ns
-
-
150
-
-
'cOZ
tOE
100
100
SO
120
120
tLZI
10
-
10
tLZZ
10
tOLZ
5
-
10
5
-
5
-
ns
CSI
tHZI
0
35
0
40
0
SO
ns
I CS2
Output Disable to Output in High Z.
tHZ2
0
35
0
40
0
50
ns
tOHZ
35
0
40
0
SO
ns
Output Hold from Address Change
tOH
0
10
-
10
-
15
-
ns
Read Cycle Time
tRC
Address Access Time
tAA
Chip Selection to Output
I
CSI
CS2
Output Enable to Output Valid
CSI
CS2
Output Enable to Output in Low Z
Chip Selection to
Output in Low Z
Chip Deselection to
Output In High Z
I
I
tCOI
-
-
120
60
-
-
150
ns
-
70
ns
15
-
15
-
ns
ns
NOTES: I 'HZ and tOHZ are defined II the tim. at which the outputs achieve the open circuit condition and are not referred
to output voltage levell.
2 At any given temperature and voltage condition, 1HZ max is less than tLZ min both for a given device and from
device to device.
•
.
208
HITACHI
- - - - - - - - - - - - - - - - - - - - H M 6 2 6 4 P - 1 0 , HM6264P-12, HM6264P-15
• READ CYCLE
~-------------------tRe---------
.t
CS2
Dout~~------
__________________________--(
NOTE: I) WE is high for Read Cycle
• WRITE CYCLE
Symbol
Item
HM6264p·1O
HM6264P·12
HM6264P·15
min
max
min
max
min
max
ISO
Unit
Write Cycle Time
twe
100
..
120
Chip Selection to End of Write
tew
80
85
-
100
Address Setup Time
tAS
0
0
-
0
-
Address Valid to End of Write
tAW
80
-
85
-
100
-
ns
Write Pulse Width
twp
60
-
70
-
90
-
ns
tWRl
5
-
10
-
os
IS
-
5
tWR2
IS
-
15
-
ns
Write Recovery Time
I CSI, WE
I
CS2
ns
tWHZ
0
0
50
os
Data to Write Time Overlap
tDW
40
-
50
-
60
Data Hold from Write Time
tDH
0
-
0
-
0
-
ns
ot to Output in High Z
tOHZ
0
35
0
40
0
50
ns
Output Active from End of Write
tow
5
-
5
-
10
-
os
HITACHI
0
40
ns
Write to Output in High Z
•
35
ns
os
209
HM6264P·10, HM6264P·12, H M 6 2 6 4 p · 1 5 - - - - - - - - - - - - - - - - - - _
• WRITE CYCLE 111 (OE clockl
=,,'''-____
Addrt'ss _ _ _.../1'-_ _ _ _ _ _ _ _
%xx\
• WRIT!: CYCLE (21 (OE Low Fixl
Address
Dr"
----1~====_=;_;;::====;:-:~'r'\..---I~\\
i /11111 ["i
----------(2nk==~=~ttt:t~~
NOTES: I) A write occurs during the overlap of a low CSI, a 3h CS2 and a low
WE. A write begins at the latest transition among CSI going low, CS2
going h~ and WE going low. A write ends at the earliest transition
among CSI going high, CS2 going low and WE going high. twp is
measured from the beginninng of write to the end of write.
2) tew is measured from the later of CSI going low or CS2 going high to
the end of write.
3) t AS is measured from the address valid to the beginning of write.
4) tWR is measured from the end of write to the address change.
tWRl applies in case a write ends at CSI or WE going high.
tWR2 applies in case a write ends at CS2 going low.
S) During this period, I/O pins are in the output state, therefore the input
signals of opposite phase to the outputs must not be applied.
6) If CSI goes low simultaneously with WE going low or after WE going
low, the outputs remain in high impedance state.
7) Dout is in the same phase of written data of this cycle.
8) Dout is the read data of the new address.
9) If CSI is low and CS2 is high during this period, I/O pins are in the
output state. Therefore, the input signals of opposite phase to the
outputs must not be applied to them.
210
eHITACHI
HM6264LP-10, HM6264LP-12HM6264LP-15
8192-word x 8-bit High Speed Static CMOS RAM
• F'EATURES
• Fast access Time
100ns/120ns/150ns (max.)
• Low Power Standby
Standby: 0.01mW(typ.)
Low Power Operation
Operating: 200mW (typ.)
• Capability of Battery Back-up Operation
• Single +5V Supply
• Completely Static Memory ..... No clock or Timing Strobe Required
• Equal Access and Cycle Time
• Common Data Input and Output, Three State Output
• Directly TTL Compatible: All Input and Output
• Standard 28pin Package Configuration
• Pin Out Compatible with 64K EPROM HN482764
(DP-28)
• BLOCK DIAGRAM
• PIN ARRANGEMENT
"o----cc=::ri
---0
--QliNJ)
M~m"ry Matrl.
~!ili
>(
~il
256
"o---H::;(=:::::J
CSI
W. ~---,,--_ _-,-_ _ _ _.J
,,,0-------'
• ABSOLUTE MAXIMUM RATINGS
Item
Terminal Voltage ..
Power Dissipation
Operating Temperature
Storage Temperature
Storage Temperature (Under Bias)
• With respect to GND.
Symbol
VT
PT
Topr
Tsta
1blas
•• Pulse width
50n~:
Rating
to +7.0
1.0
o to +70
-55 to +125
-IOto +85
-0.5
*.
Unit
V
W
·C
·C
·C
-
(Top View)
-3.0V
• TRUTH TABLE
WE
X
X
H
H
L
L
CS,
H
X
L
L
L
L
CS,
X
L
H
H
H
H
bE
X
X
H
L
H
L
Mode
Not Selected
(Power Down)
I/O Pin
High Z
HighZ
High Z
Dout
Din
Din
Output Disabled
Read
Write
Vee Current
ISB,lSBl
ISB,ISB2
Icc, Icc 1
lee,leel
lee,leel
lee,leCl
Note
Write Cycle .(1)
Write Cycle (2)
,I
x : Dun't care.
•
HITACHI
211
HM6264LP·10, HM6264LP·12, H M 6 2 6 4 L P · 1 5 - - - - - - - - - - - - - - - - - - -
• RECOMMENDED DC OPERATING CONDITIONS (To = 0 to +70°C}
Symbol
Item
Supply Voltage
Vee
GND
Input Voltage
VIH
VlL
typ
5.0
0
min
4.5
0
2.2
-0.3·
max
5.5
0
6.0
0.8
-
Unit
V
V
V
V
-
• Pulse Width SOns: -3.0V
• DC AND OPERATING CHARACTERISTICS (VCC = SV±IO%, GND = OV, To = 0 to +70°C)
Symbol
Item
Input Leakage Current
Test Condition
min
typ·
-
-
-
IILlI
Vin=GND to Vee
Output Leakage Current
IlLol
CSI=VIH or CS2=VIL or OE=VIH, VI/o=GND
to Vee
Operating Power Supply Current
Icc
Average Operating Current
leel
Min. cycle, duty=IOO%, CS1=VIL, CS2=VIH
ISB
CSI=VIH or CS2=VIL,/l/o=OmA
/SBI"
CSI~Vee-0.2V, CS2~Vee-0.2Vor CS2~0.2V
ISB2"
CS2~0.2V
-
VOL
IOL=2.1mA
VOH
/o~-1.OmA
Standby Power Supply Current
Output Voltage
,
max
Unit
2
/JA
2
/JA
40
80
rnA
60
110
rnA
I
3
rnA
2
100
/JA
2
100
/J A
-
-
0.4
V
2.4
-
-
V
CSI=VIL, CS2=VIH,II/o=OmA
• Typical limits are at Vec=5.0V, T,,=25°C and specified loading.
•• VIL min=-0.3V
• CAPACITANCE (f= IMHz, To = 25°C)
typ
Symbol Test Condition
Vin =OV
Cin
VI/O =OV
ClIO
Item
Inpu t Capacitance
Input/Output Capacitance
-
max
6
8
Unit
pF
pF
Note) This parameter is sampled and not 100% tested.
• AC CHARACTERISTICS (Vcc = 5V±10%, Ta = 0 to +70o C)
• AC TEST CONDITIONS
Input Pulse Levels: 0.8 to 2.4V
Input Rise and Fall Times: 10ns
Input and Output Timing Reference Level: 1.5V
Output Load: lTTL Gate and CL =10:lpF !including scope and jig)
• READ CYCLE
Symbol
Item
Read Cycle Time
tRe
Address Access Time
tAA
HM6264LP-I0
HM6264LP-12
HM6264LP-15
min
max
min
max
min
100
-
120
-
150
-
ns
100
-
120
150
ns
100
120
150
ns
100
-
-
120
-
150
ns
max
Unit
CSI
teol
CS2
teo2
-
tOE
-
50
-
60
-
70
ns
CSI
tLZI
10
-
10
-
15
ns
CS2
tLz2
10
-
10
-
15
tOLZ
5
-
5
-
5
-
CSI
tHZl
0
35
0
40
0
SO
ns
CS2
tHZ2
0
35
0
40
0
SO
ns
Output Disable to Output in High Z
tOHZ
0
35
0
40
0
50
ns
Output Hold from Address Change
tOH
10
-
10
-
15
-
ns
Chip Selection to Ou tpu t
i
Output Enable to Output Valid
Chip Selection to
Output in Low Z
I
I
Output Enable to Output in Low Z
Chip Deselection to
Output in High Z
l
I
ns
ns
NOTES: I tHZ and tOHZ are defined as the time af which the outputs achieve the open circuit condition and are not referred
to output voltage levels.
2 At any given temperature and voltage condition, tHZ max is less than tLz min both for a given device and from
device to device.
212
eHITACHI
- - - - - - - - - - - - - - - - - - - H M 6 2 6 4 L P · 1 0 , HM6264LP·12, HM6264Lp·15
• READ CYCLE
r----------tRc----------~
Dout----------------------------------~
NOTE: 1) WE is high for Read Cycle
• WRITE CYCLE
Symbol
Item
HM6264LP·10
HM6264LP·12
HM6264LP·15
min
max
min
max
min
max
Unit
Write Cycle Time
twc
100
-
120
-
150
-
Chip Selection to End of Write
tcw
80
-
85
-
100
-
ns
Address Setup Time
tAS
0
0
-
0
-
ns
Address Valid to End of Write
tAW
twp
80
-
85
-
100
-
ns
60
-
70
-
90
-
ns
tWRI
5
-
5
-
10
ns
-
15
-
15
50
ns
Write Pulse Width
Write Recovery Time
I CS1, WE
I
CS2
ns
tWRZ
15
Write to Output in High Z
tWHZ
0
35
0
Data to Write Time Overlap
tDW
40
-.
50
-
60
-
ns
Data Hold from Write Time
tDH
0
-
0
-
0
-
ns
OE to Output in High Z
tOHZ
0
35
0
40
0
50
ns
tow
5
-
5
-
-
ns
Output Active from End of Write
•
HITACHI
40
0
10
ns
213
HM6264Lp·10, HM6264LP·12, H M 6 2 6 4 L P · 1 5 - - - - - - - - - - - - - - - - - • WRITE CYCLE 111 10i clack 1
---.. _. -twc .
..
---
CS2 .....'"'""~'"""....:..'fo.'.JI·
,,,tAs(3) -tAw~'::iwp"l~t,..W'...RW.{....:..:...::.....:..l..:..
rt&&
WE
Dout
.~sr
» )» » ))))))
[1)
l.«iV/Wffi
tDW-'- - ; - - - - tDH
r TCELQV.
13. These parameters are reference to CE leading edge in
early write cycles and to W leading edge in delayed
write or read-modify-write cycles.
14. lWLCEL, TCELWL and TRELWL are not restrictive
operating parameters. They are included in the data
sheet as electrical characteristics only: If lWLCEL =
lWLCEL (min), the cycle is an early write and the
data out pin will remain open circuit (high Impedance)
throughout the entire cycle; i( TCELWL TCELWL
(min) and TRELWL will contain data read from the
selected cell; if neither of the above sets of conditions
is satisfied the condition of the data out (at access
time) is indeterminate.
IS. Capacitance measured with Boonton Meter or effective capacltance measuring methods.)
16.
= VIHC to disable Q.
=
a
eHITACHI
- - - - - - - - - · - - - - - - - - H M 4 7 1 8 A · 1 , HM4718A·2, HM4718A·3, HM4718A·4,
HM4718AP·1, HM4718Ap·2, HM4718AP·3, HM4718AP·4
• ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Ta-O to +70·C. VDD -12V±10%, Vcc-5V±10%. Vss-OV. VB.--5V±10%)
HM4716A-l
HM4716A-2
Old
New
min
min
hc
TRELREL
320
Read·Write Cycle Time
"'wc
.TRELREL
320
Page Mode Cycle Time
Ipc
TCELCEL
160
Symbol
Parameter
Random Read or Write
Cycle Time
rna.
-
320
320
170
HM4716A-4
HM4716A-3
max
-
max
min
375
-
410
-
ns
515
-
n.
275
-
ns
375
225
200
250
ns
8.10
135
165
ns
9.10
0
70
ns
50
3
50
ns
120
-
150
-
ns
200
10000
250
10000
n.
TRELQV
120
tCAe'
TCELQV
80
-
tOFF
TCEHQZ
0
35
0
50
0
60
IT
TT
3
35
3
35
3
100
-
150
10000
Transition Time
(Rise and Fall)
jffi"" Precharge Time
lAP
TREHREL
100
RE Pulse Widlh
I ... ,
TRELREH
120
1m" Hold
hSH
TCELREH
80
-
100
CE Pulse Width
tCAS
TCELCEH
80
10000
CE Hold Time
Ic ..
TRELCEH
120
-
100
RE to CE Delay Time
IReD
TRELCEL
15
40
CE 10 RE
leap
TCEHREL
0
Time
Precharge Time
10000
-
150
25
-20
10000
-
50
-
135
135
200
30
-20
10000
165
-
165
10000
250
-
n.
65
40
85
ns
-20
-
tAsa
TAVREL
0
0
0
0
ns
tRotH
TRELAX
Column Address Sel.up Time
t.4SC
TAVCEL
15
-5
20
-5
25
-5
·35
-5
ns
ns
Column Address Hold Time
ICAH
TCELAX
40
R.ference 10 RE
IAR
TRELA1(
80
Read Command Sel·up Time
hes
TWHCEL
0
Reid Command Hold Time
IReN
TCEHWL
0
Write Command Hold Time
tweN
TCELWH
40
'welt
TRELWH
80
Iwp
TWLWH
I",,,
45
95
0
20
95
40
-
TWLREH
50
-
60
leWI.
TWLCEH
50
Data·in Set·up Time
'0'
TDVCEL
0
Data·in Hold Time
ION
TCELDX
40
Write Command Hold Time
Reference RE
Wrile Command Pulse Width
Write Command 10 RE
Lead Time
Write Command to CE
Lead Time
Data·in Hold Time
-
45
45
60
0
-
45
55
120
0
20
-
75
160
0
120
-
160
55
-
75
80
-
100
0
ns
ns
75
55
ns
ns
-
-
ns
20
55
80
-
100
0
-
75
12
ns
Row Addre •• Sel.up Time
-
7
ns
-
11
ns
Row Addre .. Hold Time
Column Address Hold Time
8
100
hAC
Acce .. Time From CE
Delay
max
150
Acce .. Time From RE
Output Buffer Turn·oll
Unit Notes
min
ns
ns
ns
n.
ns
13
ns
13
tDHH
TRELDX
80
-
95
-
120
-
160
-
Icp
TCEHCEL
60
-
60
-
80
-
100
-
ns
Refresh Period
IRE'
TRVRV
-
2
-
2
-
2
-
2
ms
W Command
twes
TWLCEL
0
-20
-20
-20
ns
ICWD
TCELWL
60
95
125
ns
14
IRWO
TRELWL
100
-
70
120
ns
14
lopc
TREHCEL
0
-
0
Referenced RE
CE Precharge Time (for
Page·mode Cycle Only)
Set·up Time
CE to RE Delay
RE to W Delay
RE Prechar,e .to
CEHoid Time
-
160
-
200
0
-
0
-
ns
14
ns
• AC ELECTRICAL CHARACTERISTICS
Parameter
Input Capacitance (Ao-A •• D)
Input Capacitance
RE.
CE, W
Output Capacitance (Q)
Symbol
typ
rna.
Unit
Not.s
CII
-
5
pF
15
10
pF
15
7
pF
15, 16
Cit
C.
•
-
-
HITACHI
221
HM4716A-1, HM4716A-2, HM4716A-3, H M 4 7 1 6 A - 4 - - - - - - - - - - - - - - - - HM4716AP-1, HM4716AP-2, HM4716AP-3, HM4716AP-4
.TIMING WAVEFORMS
.READ CYCLE
>-------TRELREL-------!
V I H C - -.....' - -
1~=:Tmc;;;::=:::j:=====iil
VlL
VIL
AUDItESSES
vm
",
VlHC
VI
VIL
TR£LQV~ J ~TC~
--------'OPEN--t::ID--
.WRITE CYCLE (EARLY WRITE)
\'IHC
____u:==~~~~~TRE"LR~E:.L::::::1:======~
TREt-AX
TRELRF.II-
VIL
yIHC-----H--...,~
1\..4~'-----_+-rJ
VIL
VON _ _ _ _ _ _ _ _ _ _-.
/"-~,"","-..J.
,",.,.,.rrt..,..,.,,.,...
'--"''''''"'-Jj
•
HITACHI
223
HM4716A-1, HM4716A-2, HM4716A-3, H M 4 7 1 6 A - 4 - - - - - - - - - - - - - - -_ _
HM4716AP-1, HM4716AP-2, HM4716AP-3, HM4716AP-4
• TYPICAL CHARACTERISTICS
ACCESS TIME (NORMARIZEO) vs. VDD
ACCESS TIME (NORMARIZEO) vs. V..
1.2
1.2
T}=50'C
Tr=50'C
1. 1
1.1
~
'"
0.9
j
.~
~
1.0
7-
:>
ij
'-
'"
f-
0.9
o.8
0.8
10
11
12
14
13
3
-5
Supply Voltage VDD (V)
ACCESS TIME (NORMARIZEO) vs. T;
]
.~
1.0
7-
30r-------,-------,--------r-------,
>
0-J
::!
f0.9
/
V
v
V
25~-------r--~~~r_------1_------_i
'0 1-------+-----::::....1F-------t--------;
151-------~
__--__~~~~
10 l ' " O - - - - 1 L . . 1 - - - - - I 1 ' - - - - - ' U - - - - I " "
0.8
-10
20
80
50
110
Junction Temperature TJ ('C)
Supply Voltage VIlI) \ \'}
1001 vs. T
1001 vs. CYCLE RATE
0
30
VDD=13.2V
T~REL=375ns
VDD=13.2V
TJ=50'C
I
'5
0
TRE~EL=5Il(Jns
0
'0
./
10
-10
/'
L
/
V
0
5
TRELREL 800ns
,0
1
so
5"
Junctlun TemperatufP
224
-7
IDOl vs. VD•
1.2
1.1
-6
Supply Voltage VSS (V)
{}
110
Cycle Rate (I/TRELRELl (MHz)
TJ ("C)
~HITACHI
- - - - - - - - - - - - - - - - - H M 4 7 1 6 A - 1 . HM4716A-2. HM4716A-3. HM4716A-4
HM4716AP-1. HM4716AP-2. HM4716AP-3. HM4716AP-4
1002 (STANDBY)
VB.
V••
1002 (STANDBY)
T, =50'C
i
:;;
l
0.8
.:l
1
fon
/
V
~
-...
1.0
~
~
-
~
0.8
0.6
on
10
11
0.'
I.
13
12
-10
20
1003 ( RE ONLY CYCLE)
VB.
1003 (RE ONLY CYCLE)
V••
20
0
15
5
T,
1Il
0
11
!lI
12
13
I.
[L=500",
-
"-
I~
JELREL=315ns
-
~
10
I
TRELREL=800ns
r--
20
1004 (PAGE-MODE CYCLE)
50
110
80
Junction Temperature T, (Oe)
Supply Voltage VbO (V)
VB.
1004 (PAGE-MODE CYCLE)
V..
VB.
T,
25r-------~------_r------_r-------,
25
VOIl=13.2V
T,=SO'C
~
VB.
-
TRELREL=375ns
;;:
lIO
5
T,=50"C
:§
80
50
Junction Temperature T/ (Oe)
25
'"'
J.
--
~
Supply Voltage VOD' (V)
~
"-........~
u
0.6
0.'
<.
T,
VOD=13.2V
1.0
~
VB.
1.2
1.2
TRELREL=225ns
20
i
15
.:l
20~------r-----~f=---~~-----;
E
"
.:l
15~-------r------~f=~--. .~~-----i
or.
I
;:,
TRELREL=500ns
10~-------r------~r-------~-------i
10
~
10
II
12
13
I'
-10
20
50
JunctIon Temperature
Supply Vollage VIII) \ V)
eHITACHI
80
110
T, ('C)
225
HM4716A-1, HM4716A-2,HM4116A-3,HM4716A-4--------------------------------HM4716AP-1, HM4716AP-2, HM4716AP-3, HM4716AP-4
CLOCK INPUT LEVELS vs. V."
2. 5
_.
I
T,=50·C
-
>
~
Cl
I. 5
I
VIHC{MIN:
5
VII.C(il:\X)
VILC(MAXI
I. 0
Il
o. 5
tl. 5
HI
12
II
13
-4.5
-4.0
Il
CLOCK INPUT LEVELS vs. T,
Vi
I
V80::::-Sr
2.0
2.5
I
2.1 I
..
:-
~
1.5
\'IW
I'JI,.IMI~I
-- ----
TI=fiO'C
VRB=-5V
;,
!
-6.tI
ADDRESS AND DATA INPUT
LEVELS vs. V••
V'HcJ~
Vuu-=12\'
-5.;
-5.1l
Supply \tohaRE" VBB. \' I
SupplY r"ltaRt' Vun ;\',
~
Cl
I
T,=50'C
VOD=12\'
2.0
-
!
2..5
VIJIMINI
VFl8=-SV
2.11
CLOCK INPUT LEVELSvs. V..
1.5
j
~AXI
1.1 I
I,(J
~
--
VII..M.ata
J<'--------
- - - - - - - - - - - - - - - - - - H M 4 8 6 4 - 2 , HM4864-3, HM4864P-2, HM4864P-3
."RAS-ONLY" REFRESH CYCLE
Mcl.rell
_ _ _ _ _ _ _ _ _ _ _ Open _ _ _ _ _ _ _ _ _ _ __
Do..
• PAGE MODE READ CYCLE
1---------------,,,.-----------------1
f----------'''''---------RAS
v"'
'"
\"1.
CAS
WE
V,.
t'n
V,H
VI/.
V,.
Vt/
10"
Daul
.PAGE MODE WRITE CYCLE
ill
v,.
v"
CAs
v,.
v"
Address
WE
Din
v"
VII.
V,.
V"
V,.
V"
•
HITACHI
241
HM4864-2, HM4864-3, HM4864P-2, H M 4 8 6 4 P - 3 - - - - - - - - - - - - - - - - -
• TYPICAL CHARACTERISTICS
AE:CESS TIME
ACCESS TIME
va. SUPPLY VOLTAGE
va. AMBIENT TEMPERATURE
Ta=20*C
]
\..
1.1
"-
~
}
Vcc=5.5V
1.0
~
;:
~
•.9
'.0
I
'"
~
5.0
'.5
0
.
'-.....
~
6.0
5.5
~
---
o.9
-20
AmbIent Templ!'ratl.lre
SUPPLY CURRENT
va. SUPPLY VOLTAGE
"
,,,
Til =211"C
.0
30
~
.1..:27.',
-
-
3311
0
500
::
(J
I
ltlu
(OC)
-
0
~
.g
,,,
Ta
trc=5.5V
<
~
V
SUPPLY CURRENT
va. AMBIENT TEMPERATURE
511
.!
,.
III
Supply Voltage Vee (V)
~
10
-
0
2"
4.•
5.•
'.5
5.5
-l,OIlIl
I0
b.O
-20
SUPPLY CURRENT
va. CYCLE RATE
Inn
40
ItJ
Ambient Temperature
Supply Voltage Vee (VJ
Ta
("C)
SUPPLY CURRENT
va. SUPPLY VOLTAGE
50
rcr=5.5V
1',,=20'C
0
/
0
/
V
L
/
--I
II
Cycle Rate{ 1/ tIel (MHz)
242
I
m.rn:!'"
To:=20"C
1I.p=JOOns
V
.;,,)
.........
~
.1.0
"
Supply Voltage Vee IV)
•
HITACHI
b,lI
- - - - - - - - - - - - - - - - - H M 4 8 6 4 - 2 , HM4864-3, HM4864P-2, HM4864P-3
SUPPLY CURRENT
VB. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
50..-----.----......---.------.
TII=20'C
i
~
3~----~------~------~----__1
~ ~o~-----4------~------4_----__1
ti
~
~
~
hc==270n5
30~-----4------~-----=~~--~
~
3311
<3
>.
1
1~-----4------~------~----__1
J!
I,OIlIl
IOL-____~~~__-L______~____~
II L.____....J._ _ _ _..1..______~-------I
-2.)
10
4n
70
u
IUU
u
Ambient Temperature Ta (tl
Supply Voltage Vee (V)
SUPPLY CURRENT
SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
vs. CYCLE RATE
..------,------,-------"T""----,
511
:)1)
\,( =5.1\
TII=2u'C
Vcc=5.5V
]
~
40~----~------~------~----~
.
--
30
10
-
tiu-27tJns-
--
20
~
.l:
~
~
I-.
-50fl
411
70
III
IOU
Cycle Rate (l/tllc\(MHzl
SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
5()~-----.----..,..----~---~
5CJ
Til
=2U'C
;;:
-!
:£
~
",
~
"'I------4------+------4_----~
i
l'.
:!:
~
311
""
~
V
V
/
..,/
Ta ("e)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
~
<3
];
J!
:!u
];
J!
_1.0flO
Ambient Temperature
C
'10
g:,
---:no
10
-2f1
..
,II
ti
ti
~
iRl'=ifIUns
3111---_--+------I------l------~
"
"'
:?25
1:
20
<3
5111,
--
211~....:=~==::::!:===-_L_= 225
J
111 L.___....J"-___...,L-______-,L___---::'
~
u
u
u
u
-
tl" -liUnll
-!iIlU
111 L.____---'______..1..______..I.._ _---J
-20
IU
HI
Ambient Temperature
Supply Voltage \h IVI
eHITACHI
in
lUll
1'.,: 't
243
HM4864-2, HM4864-3, HM4864P-2, H M 4 8 6 4 P - 3 - - - - - - - - - - - - - - - - -
INPUT LEVEL
va. SUPPLY VOLTAGE
SUPPLY CURRENT
va. CYCLE RATE
,
511
r({ =5.:W
!
T,,=:!u\
TII=-:!U\'
fl"
-'''UII~
~ ,U
P
"
j
Ii
~
",
'ill
.l!
<3
.!u
.----- ~ ---
~
1:
Jl
-~
."...
~
L--'"
~
---
k
----
"
u, ",
I"
V
. ..
,
I
'• .11
5.5
Supply Voltage Vcc (V I
Cycle Rate IlIlpc) (MHz)
CLOCK INPUT LEVEL
VB. SUPPLY VOLTAGE
INPUT LEVEL
va. AMBIENT TEMPERATURE
,,''---"'""T""--T"""
['I-=:!U't'
:1.11
~
-----::::---
]
f
15
I."
I.n
I.'
=
~
;;:
,
V
~
-+__....J
II.; L-_ _...J.._ _ _I.-_ _
-.!U
10
~j)
Ambient Temperature Ta
70
4.11
Ilin
CLOCK INPUT LEVEL
va. AMBIENT TEMPERATURE
III
=:;.lJ\"
2.11
E
~
~
1.1
-
'IL
U
lou
u,~':",,...,--...J...I"---'J...,,--......,;~"---::!IO'll
Ambient Temperature Ta (OC)
244
.I,ll
Supply Voltage Vcr tV)
("C)
$
HITACHI
h.O
- - - - - - - - - - - - - - - - - H M 4 8 6 4 - 2 , HM4864-3, HM4864P-2, HM4864p-3
h
h
t2
-
l.un. RAS/CAS Cyct.
RASICAS I:),el.
RAS
''a,r Mod. C,cl.
RAS Onl)' Cycle
/ " ~h
rh
L-.J
•
'00
1 '"
"
•,
·
II
II",
JI
'v
J
I
JI
II
n
V'
\.
\...-...J
J
u
(
ft
/1/\
/'
\.,..JU
\
J
Ir
(
"-T
J
-u(
-,-,,~
.APPLICATION INFORMATION
epOWER ON
l l/1
An initial pause of 500 lAS Is required after power·up and a
minimum of eight (8) initialization cycle,(any combination of
cycles containing a RAS clock such as 'AAS-only refresh) must
follow an initial pause.
The Vcc current (Icc) requirement of the HM4864 during
power on is, however, dependent upon the input levels (RAS,
CAS) and the rise time of Vcc, asshown In Fig. 1.
,,
,
eREAD CYCLE
A read cycle begins with addresses stable and a negative going
transition of RAS. The time delay between the stable address
and the start of RAS·on is controlled by parameter tASR .
Following the time when RAS reaches its low level, the row
address must be held stable long enough to be captured. This
controlling parameter is tRAH' Following this interval, the
address can be changed from row address to column address.
When the column address is stable,CAS can be turned on. The
leading edge of CAS" is controlled by parameter tRCD. The
basic limit on the CAS leading edge is that CAS can not start
until the column address is stable, and this is controlled by
parameter tASC. The column address must be held stable long
enough to be captured. The controlling parameter is tCAH'
Note that tRCD (max) is not an operating limit of the
HM4864 though its specification is listed on the data sheets. If
CAS becomes on later than tRCD (max), the access time from
RAS will be increased by the time which tRCD exceeds tRCD
(max).
Following the time when CAS reaches its low level, the
data-out pin remains in a high impedance state until a valid
data appears. This parameter is tCAC ·access time from CAS.
The access time from RAS-tRAC-is the time from RAS·on
to valid Dout.
The minimum value of tRAC is derived as the sum of tRCD
(max) and tCAC'
The selected output data is held valid internally until CAS
becomes high, and then Dout pin becomes high impedance.
This parameter is tOFF·
•
HITACHI
I,
11\
"
w.rn .. r~s
'-
j
V
lli.clcii~ ~'('I'
r-........
'"
211
."
3U
1'ImI' 1/,,1
1,1 \'n' du' 1IIIlI""'IU,,,
l/1
15
""R'A'S.cA'Smvu
~
10
.f
~
100
RAS,m",~·,.(
200
;jun
40U
"11~(",1
I.! \'((' rIle cime,"IOO,ll.
Flg.1 I cc va. Vee during power up.
245
500
HM4864-2, HM4864-3,HM4864P-2,HM4864P-3----------------------------------• WRITE CYCLE
A write cycle is performed by bringing WE low
before or during CAS-on_
Two different write cycles can be defined as;
Write cycle-Write data are available at the beginning
of the CAS-on so that the write operation starts at
the beginning_ In this mode, Dout and WE signal
times are not in any critical path for determining
cycle time_
Following the time when WE" reaches its low level,
Wi: must be held stable long enough to be captured_
This WE-on pulse deration is called twp- The time
required to capture write data in a latch is called
tDH. This cycle is called an "early write".
Read Write cycle-This cycle starts as a read cycle,
but as soon as the device specification is met, a
write cycle is initiated.
WE and Din are delayed until after Dout. This cycle
is called a "delayed write". A "Read-modify-write"
cycle is a variation of this operation. In this mode,
Din and WE become critical path signals for
determining cycle time.
• REFRESH
Refresh of the HM4864 is accomplished by performing a memory cycle at each of the 128 row
addresses within each two millisecond time interval.
AD to A6 are refresh address pin compatible with
standard 16K RAM (HM4716A, HM4816A). During
refresh, either V'l or V'H is permitted for A7_ Any
cycle in which RAS signal occurs refreshes the
entire selected row_ ~-only refresl1 results in
substantial reduction in operating power_ This reduction in power is reflected in the 1CC3 specification_
• PAGE MODE
Page mode operation allows faster successive memory operations at multiple column locations of the
same row address with increased speed_
This is done by strobing the row address into the
chip and maintaining RAS at a logic low throughout
all successive CAS memory cycles in which the row
address is latched_ As the time normally required for
strobing a new row address is eliminated, access and
cycle times can be descreaded and the operating
power is reduced_ These are specifications.
• CLOCK-OFF TIMING
RAS and CAS must stay on for Dout sta~ilized to
valid data. In the case of CAS, this is controlled by
parameter tCAS (min).
In the case of RAS, this is controlled by parameter
tCAS (min). Following the end of RAS, CAS must
stay off long enough to precharge internal circuits.
The only parameter of concern is tRP. Normally
CAS is not required to be off for minimum time of
tCRP. However, in a page mode memory operation,
there is a tcp (min) specification to control the
CAS-off time .
• DATA OUTPUT
Dout is three-state TTL compatible with a fan-out
of two standard TTL loads.
When CAS is high, Dout is in a high impedance
state. When CAS is low, valid data appears after
tCAe at a read cycle, and Dout is not valid as an
early-write cycle.
246
$
HITACHI
HM4864CC-2,
HM4864CC-3
65536-word x 1-bit Dynamic Random Access Memory
• FEATURES
• 18-pin Leadless Chip Carrier
• 150ns access time, 270ns cycle (HM4864CC-2)
200ns access time, 335ns cycle (HM4864CC-3)
• Single power supply of 5V ± 10% with a built-in Vss generator
• Low power: 330mW active, 20mW standby (max)
• The inputs TTL compatible, low capacitance, and protected against
static charge_
• Output data controlled by CAS and unlatched at end of cycle to
allow two dimensional chip selection and extended page boundary.
• Common I/O capability using "early write" operation
• Read-Modify-Write, HAS-only Refresh, and Page-mode capability
128 refresh cycle
(CC-18)
• PIN ARRANGEMENT
.FUNCTIONAL BLOCK DIAGRAM
Din
Doul
.,
~
Mem"ry
,hray
Ruw Dec.
Memnry
..\rray
!
£
---I
VIIS
Generator
I
Memor)
."'rray
A.-A,
• ABSOLUTE MAXIMUM RATINGS
Voltage on any pin relative
to Vss . __ .•. __ .• _ ... _. -1.0 to +7V
Operating Temperature, Ta
(Ambient) ... _ ... ___ . _ . _ 0 to +70°C
Storage Temperature
(Ambient) .... _ .. _ .... _. -65 to +150°C
Short-circuit Output Current . 50 mA
Power Dissipation .. __ •. _ _ _ 1 W
•
HITACHI
CAS
Address Inputs
Column Address Strobe
Din
Data In
Dout
RAS
Data Out
Row Address Strobe
WE
Vee
Read/Write Input
Power (+5V)
V:.:s
Ground
Ao-A~
Refresh Address Input
247
HM4864CC-2,HM4864CC-3------------------------------------------------• RECOMMENDED DC OPERATING CONDITIONS (Ta= 0 to +70'C)
Symbol
Parameter
Supply Voltage
min
Vee
4.5
Vss
0
Input High. Voltage
V,II
Input Low Voltage
Vi,
typ
max
Unit
5.0
5.5
0
V
-
6.5
V
1
-
0.8
V
I
2.4
-1.0
0
Notes
1
V
• DC ELECTRICAL CHARACTERISTICS (Ta=O to +70·C. Vcc=5V±10%, Vss=OV)
min
max
Unit
Notes
IcC!
-
60
mA
2,4
lcc2
-
3.5
mA
2
leca
-
45
mA
2,4
In 4
-
45
mA
2,4
INPUT LEAKAGE
Input Leak~ge Current, any Input (V.. -0 to +6.SV, all other pins not
under test -OV)
lu
-10
10
"A
OUTPUT LEAKAGE
Output Leakage Current (Dout is disabled, V••• -0 to +5.SV)
Iw
-10
10
I'A
2.4
0
Vee
0.4
V
V
Symbol
Parameter
OPERATING CURRENT
Average Power Supply Operating Current (RAS,CAS Cycling;IRc-min.)
STANDBY CURRENT
Power Supply Standby Current (RAS - V1I4 Dout ~High Impedance)
REFRESH CURRENT
Average Power Supply Current, Refresh Mode
(RAS Cycling, CAS - VlH;IRc-min.)
PAGE MODE CURRENT
Average Power Supply Current, Page-mode Operation
(RAS-VII,CAS Cycling;tpc=min.)
OUTPUT LEVELS
Output High (Logic 1) Voltage (I••• - -SmA)
Output Low (Logic 0) Voltage (IQ' -4.2mA)
VOH
VOL
3
NOTES
1. All voltages referenced to V ss.
2. ICC depends on output loading condition when the device is selected. ICC max. is specified at the output open condition.
3. lLO consists of leakage current only.
4, Current depends on cycle rate: maximum current is measured at the fastest cycle rate .
• AC ELECTRICAL CHARACTERISTICS
Symbol
typ
rna.
Unit
Input Capacitance (A,-A" Din)
C .. ,
-
7
pF
Input Capacitance (RAS,CAS,WE)
C.. ,
-
10
pF
1
1
Output Capacitance (Dout)
Co.. ,
-
7
pF
1,2
Parameter
NOTES
1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = V/H to disable DOUT'
248
eHITACHI
Notes
-----------------------------------------------HM4864CC-2,HM4864CC-3
• ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Ta-O to +70'C, Vcc=5V±10%, VSS-OV)
Symbol
Parameter
HM4864CC-2
HM4864CC-3
min
max
min
335
max
Unit
1).2)
Notes
IRC
270
Read· Write Cycle Time
'IRWC
270
-
335
-
ns
Page Mode Cycle Time
Ipc
170
-
225
-
ns
t RAC
-
150
200
ns
4.6
Access Time from CAS
tCAe
-
100
-
135
ns
Output Buffer Turn·off Delay
t"FF
0
40
0
50
ns
5.6
7
Transition Time (Ris~ and Fall)
IT
3
35
3
50
ns
3
RAS Precharge Time
I"
100
120
-
ns
RAS Pulse Width
IRAS
150
200
10000
ns
RAS Hold Time
lUll
100
CAS Pulse Width
t(',u
100
CAS Hold Time
/cSH
150
-
200
-
ns
RAS to CAS Delay Time
iRCD
20
50
25
65
ns
CAS to RAS Precharge Time
tCRP
-20
-
-20
n.
0
-
-
Random Read or Write Cycle Time
Access Time from
R'AS
10000
-
135
Row Address Set·up Time
IASR
hAH
Column Address Set·up Time
lAse
20
'-10
Column Address Hold Time
ICAH
45
Column Address Hold Time referenced to RAS
IAR
95
Read Command Set-up Time
iRes
0
Read Command Hold Time
tH.CH
0
Write Command Hold Time
tWC'H
45
-
55
Write Command Hold Time referenced to RAS
t WCR
95
-
120
-
55
Iwp
45
Write Command to RAS Lead Time
tRIttI.
45
Write Command to CAS Lead Time
fewl.
45
Data-in Set-up Time
tD:>
Data·in Hold Time
' 0•
Data·in Hold Time referenced to RAS
tDHM
CAS Precharge Time (for Page·mode Cycle Only)
Icp
0
25
-10
55
120
0
0
55
-
55
45
-
55
95
-
120
-
80
-
0
0
Refresh Period
tREF
60
-
Write Command Set-up Time
twrs
-20
CAS to WE Delay
leWD
60
RAS to WE Delay
"WD
110
RAS Precharge to CAS Hold Time
tRl'C
0
-
135
Row Address Hold Time
Write Command Pulse Width
ns
2
~
-20
80
145
0
ns
ns
-
-
-
ns
ns
ns
ns
n.
ns
ns
n.
ns
ns
ns
ns
ns
9
ns
9
ns
-
ns
2
m.
-
8
os
10
ns
10
ns
10
ns
NOTES
1. AC measurements assume tT = Sns.
2. 8 cycles are required after power-on or prolonged
periods (greater than 2ms) of RAS inactivity before
proper device operation is achieved. Any 8 cycles
which perform refresh are adequate for this purpose.
3. VIH (min) and VIL (max) are reference levels for
measuring timing of input signals. Also, transition
times are measured between VIH and ViL:
4. Assumes that tRCD ~ tRCD (max). If tRCD is greater
than the maximum recommended value shown in this
table tRAC exceeds the value shown.
S. Assumes that tRCD ~ tRCD (max).
6. Measured with a load circuit equivalent to 2TTL loads
and 100 pF.
7. tOFF (max) defines the time at which the output
achieves the open circuit condition and is not referenced to output voltage levels.
8. Operation with the tRCD (max) limit insures that
•
tRAC (max) can be met. tRCD (max) is specified as a
reference point only; if tRCD is greater than the
specified tRCD (max) limit, then access time is
controlled exclusively be tCAC' __
9. These parameters are reference to CAS leading edge in
early write cycles and to WE leading edge in delayed
write or read-modify-write cycles.
10. twcs tCWD and tR WD are not restrictive operating
parameters. They are included in the data sheet as
electrical characteristics only: if twcs ~ twcs (min),
the cycle is an early write cycle and the data out pin
will remain open circuit (high impedance) throughout
the entire cycle; if tCWD ~ tCWD (min) and tR WD ~
tRWD (min) the cycle is a read/write and the data
output will contain data read from the selected cell; if
neither of the above sets of conditions is satislied the
condition of the data out (at access time) is indeterminate.
HITACHI
249
HM4864CC·~,HM4864CC·3------------------------------------------------
.TlMING WAVEFORMS
eREAD CYCLE
f----------,oc----------..;
t--------k·SH'---------t
V,R
W
V"
V,.
CiS
V"
A44re.. VII
V"
WE
V"
V"
0",
VOl
V"
eWRITE CYCLE
til'
feSN
m
-,,,
V"
CAS
V,R
V"
V..
AtW.rell
tASII~
i-t'AH-j
Ius
,,,
V,M
tlSH-
l
I~CA~
IASC'
Column Address
Row Address
V"
,
~
~.. CJ
..
,
V.lid 0."
IX:
~:--------------------~."'---------------------------
VIN
v"
h.
Address
V"
V"
fn
0",
0"
250
".-
tell,
m v"tit
'ViE
"-
"'-V
e READ· WRITE/READ· MODIFY· WRITE CYCLE
ITs
f---lIp-
I--II"H-
~ 1--...-
0",
IX.
~
t,l,
X
Din
teAS
V..
V"
V"
V"
$
HITACHI
------------------------------------------------HM4864CC-2,HM4864CC-3
."RAS-ONLY" REFRESH CYCLE
Addreu
_ _ _ _ _ _ _ _ _ _ _ _ 0'0. _ _ _ _ _ _ _ _ _ _ _ __
Do_,
.PAGE MODE READ CYCLE
I--------------"c-----------------j
ill
VIN
CAS
VIB
v"
\"L
MIm,
WE
~I'H
v"
VIB
r~,
OF'
Do"
v••
VOL
.PAGE MODE WRITE CYCLE
~----------_<.c----------------~
RAS
v,.
v"
CAS
VIN
Address
WE
Din
v"
VIN
VII.
VIN
VIN
V"
_HITACHI
251
HM48641-2, HM48641-3,
HM4864K-2, HM4864K-3
Wide Operating Temperature Range
65536-word x 1-bit Dynamic Random Access Memory
The HM4864 is a 65,536-words by 1-bit, MOS random access
memory circuit fabricated with HITACHI's double-poly N-channel
silicon gate process for high performance and high functional
density_ The HM4864 uses a single transistor dynamic storage cell
and dynamic control circuitry to achieve high speed and low power
dissipation_
Multiplexed address inputs permit the HM4864 to be packaged in a
standard 16 pin DIP on 0_3 inch centers_
This package size provides high system bit densities and is
compatible with widely available automated testing and insertion
equipment_ System oriented features include single power supply of
+5V with ±10% tolerance, direct interfacing capability with high
performance logic families such as Schottky TTL, maximum input
noise immunity to minimize "false triggering" of the inputs, on-chip
address and data registers which eliminate the need for interface
registers, and two chip select methods to allow the user to determine
the appropriate speed/power characteristics of this memory system_
The HM4864 also incorporates several flexible timing/operating
modes_
In addition to the usual read,write, and read-modify-write cycles, the
HM4864 is capable of delayed write cycles, page-mode operation
and RAS-only refresh_
Proper control of the clock inputs (RAS, CAS, and WE) allows
common I/O capability, two dimensional chip selection, and
extended page boundaries (when operating in page mode)_
(DG-16B)
• PIN ARRANGEMENT
• FEATURES
• Wide Operating Temperature Range
(Top View)
HM48641-2/-3
HM4864K-2/-3
•
•
•
•
•
•
Recognized industry standard 16-pin configuration
150ns access time, 270ns cycle time (HM48641-2, HM4864K-2)
200ns access time, 335ns cycle time (HM48641-3, HM4864K-3)
Single power supply of +5V±10% with a built-in Vss generator
Low Power; 330 mW active_ 22 mW standby (max)
The inputs TTL compatible, low capacitance, and protected
against static charge
• Output data controlled by CAS and unlatched at end of cycle to
allow two aimensional chip selection and extended page boundary
• Common I/O capability using "early write" operation
• Read-Modify-Write, RAS-only refresh, and Page-mode capability
• 128 refresh cycle
252
eHITACHI
Ao-A7
Address Inputs
CAS
Column Address Strobe
Din
Data In
Dout
Data Out
RAS
Row Address Strobe
WE
Read/Write Input
Vee
Power (+5V)
Vss
Ground
A.-A.
Refresh Address Input
- - - - - - - - - - - - - - - - - H M 4 8 6 4 1 . 2 , HM48641·3, HM4864K·2, HM4864K·3
.FUNCTIONAL BLOCK DIAGRAM
,------iR/W Swi".I---.,
Din
• ABSOLUTE MAXIMUM RATINGS
Voltage on any pin relative
toVss ...............• -1.0to+7V
Operating Temperature, Ta
(Ambient) .. -40 to +85°C (HM48641 Series)
0....
---0
Row Dec.
Memory
Array
--1
Row Dec.
~
~
Vee
Vo Generator
I
Memory
Array
-55 to +85°C (HM4864K Series)
Storage Temperature
(Ambient) .............. -65 to +150°C
Short-circuit Output Current . 50 mA
Power Dissipation • . . . . . . .. 1 W
• RECOMMENDED DC OPERATING CONDITIONS (Ta= -40 to +as'C)*
Parameter
Symbol
-
Supply Voltage
Input High Voltage
.
Input Low Voltage
*·HM4864KSenes;Ta =
min
4.5
Vee
Vss
0
V,H
2.4
V"
-1.0
typ
max
Unit
5.0
5.5
V
0
-
-
Notes
1
0
V
6.5
V
1
0.8
V
1
55 to +85 C
.DC ELECTRICAL CHARACTERISTICS (Ta=-40 to +8S'C:Vcc=5V±lO%. Vss=OV)
min
max
Unit
Notes
Icc I
-
60
mA
2.4
Icc!
-
4
mA
2
lccl
-
45
mA
2.4
PAGE MODE CURRENT
Average Power Supply Current, Page-mode Operation
(RAS-V'L,CAS Cycling;/pc=min.)
feet
-
45
mA
2.4-
,
INPUT LEAKAGE
Input Leakage Current. any Input (V.. - 0 to +6.5V. all other pins not
under test -OV)
Iu
-10
10
I'A
OUTPUT LEAKAGE
Output Leakage Current (Dout is disabled,
/w
-10
10
I'A
VaH
VOL
2.4
0
Vee
0.4
V
V
Parameter
Symbol
OPERATING CURRENT
Average Power Supply Operating Current (RAS.CAS Cycling; IRe-min.)
STANDBY CURRENT
Power Supply Standby Current (RAS - V'II, Dout - High Impedance)
REFRESH CURRENT
Average Power Supply Current, Refresh 'Mode
(RAS Cycling. CAS - V,H; IRe-min.)
V~k'
= 0 to +S.5V)
OUTPUT LEVELS
Output High (Logic 1) Voltage (I ... = -SmA)
Output Low (Logic 0) Voltage (In' -4.2mA)
3
NOTES
1. All voltages referenced to Vss.
2. ICC depends on output loading condition when the device is selected. lee max. is specified at the output open condition.
3. fLO consists of leakage current only.
4. Current depends on cycle rate: maximum current is measured at the fastest cycle rate.
5. .: HM4864K Series; Ta = - S5 to +85'C
.AC ELECTRICAL CHARACTERISTICS (Vcc=5V±10%. Ta=25'C)
Parameter
Input Capacitance (A,-A,. Din)
Input Capacitance
(RAS. CAS. WE )
Output Capacitance (Oout)
Symbol
typ
max
Unit
C... I
-
7
pF
CIII:
-
10
pF
1
7
pF
1.2
C... ,
-
Notes
1
NOTES
I. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = V/H to disable DOUT.
_HITACHI
253
HM48641-2. HM48641-3. HM4864K-2. H M 4 8 6 4 K - 3 - - - - - - - - - - - - - - - - -
• ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Ta--40 to +8S·C·, Vcc-SV±lO%, VSS-OV)
Parameter
Symbol
HM48641/K-2
HM4864I1K -3
max
min
335
-
Random Read or Write Cycle Time
',e
Read-Write Cycle Time
IllWe
min
270
270
Page Mode Cycle Time
Ipc
170
Aec ... Time Irom HAS
IMC
-
150
Access Time Irom CAS
'CAe
-
100
Output Buffer Turn-off Delay
II)""
0
40
Transition Time (Rise and Fall)
IT
3
35
RAS Precharge Time
lop
HAS Pulse Width
tH.U
150
RAS Hold Time
ttuN
100
-
leAS
100
tCSH
150
RAS to CAS Delay Time
heD
CAS to RAS Precharge Time
tCRP
Row Address Set-up Time
tMIt
0
Row Address Hold Time
tRAH
Column Address Set-up Time
20
-20
-
335
n.
ns
200
ns
4.6
135
ns
0
50
ns
5,6
7
3
50
ns
3
-
ns
10000
200
10000
ns
-
135
-
ns
-
200
-
ns
50
25
65
ns
135
-
ns
-20
20
-
lAse
-5
-
-5
Column Address Hold Time
tCAH
45
55
Column Address Hold Time relerenced to HAS
I ..
95
-
120
-
ns
Read Command Set-up Time
IRCS
0
-
0
-
ns
Read Command Hold Time
tRCH
0
0
-
n.
Write Command Hold Time
tW(,H
45
55
-
ns
Write Command Hold Time relerenced to HAS
twelt
95
120
ns
Write Command Pulse Width
Iwp
45
-
Write Command to RAS Lead Time
tRW/"
45
Write Command to CAS Lead Time
lew/..
45
Data-in Set-up Time
IDS
0
Data-in Hold Time
'0_
45
-
55
Data-in Hold Time relerenced to RAS
lDHR
95
-
120
CAS Prech,rge Time (lor Page-mode Cycle Only)
lep
60
-
Relresh Period
Write Command Set -up Time
IREF
-
2
twes
-10
CAS to WE Delay
leWD
60
IOWD
HO
tRPC
0
RAS to
WE"
Delay
RAS Prech,rge to CAS Hold Time
-
-
-
Notes
ns
225
-
Unit
120
100
CAS Pulse Width
CAS Hold Time
max
1), 2)
0
25
55
-
55
-
0
-
55
80
-
-10
80
2
-
8
ns
ns
ns
n.
ns
ns
ns
ns
ns
9
ns
9
ns
ns
ms
ns
lO
ns
10
10
145
-
ns
0
-
ns
NOTES
1. AC measurements assume tT =Sns.
2. 8 cycles are required after power-on or prolonged
periods (greater than 2ms) of RAS inactivity before
proper device operation is achieved. Any 8 cycles
which perform refresh are adequate for this purpose.
3. V1H (min) and VIL (max) are reference levels for
measuring timing of input signals. Also, transition
times are measured between VIH and VIL'
4. Assumes that tRCD ~ tRCD (max). If tRCD is greater
than the maximum recommended value shown in this
table tRAC exceeds the value shown.
S. Assumes that tRCD ~ tRCD (max).
6. Measured with a load circuit equivalent to 2TTL loads
and 100 pF.
7. tOFF (max) defines the time at which the output
achieves the open circuit condition and is not referenced to output voltage levels.
8. Operation with the tRCD (max) limit insures that
254
tRAC (max) can be met, tReD (max) is specified as a
reference point only; if tReD is greater than the
specified tReD (max) limit, then access time is
controlled exclusively be tCAe. _ _
9. These parameters are reference to CAS leading edge in
early write cycles and to Wf leading edge in delayed
write or read-modify-write cycles.
10. twes tCWD and tR WD are not restrictive operating
parameters. They are included in the data sheet as
electrical characteristics only: If twcs ~ twcs (min),
the cycle is an early write cycle and the data out pin
will remain open circuit (high impedance) throughout
the entire cycle; If tewD ~ tewD (min) and tR WD ~
tR WD (min) the cycle is a read/write and the data
output will contain data read from the selected cell; If
neither of the above sets of conditions is satisfied the
Condition of the da~ out (at access time) is indeterminate.
11. *: HM4864K Series; Ta=-SS to +8S·C
eHITACHI
- - - - - - - - - - - - - - - - - H M 4 8 6 4 1 · 2 , HM48641·3, HM4864K·2, HM4864K·3
• TIMING WAVEFORMS
• READ CYCLE
• "RAS·ONLY" REFRESH CYCLE
-----,,,------
_ _ _ _ _ _ _ _ _ '()pen _ _ _ _ _ _ _ __
I)nlll
• WRITE CYCLE
• PAGE MODE READ CYCLE
",
ii"B \~:'I
ro
,,-tlll'l
~~,~
IItSH--
I('.-Is-
tUR.!;;:
fl.!!!:L'AS('---t
-\ddrt'ssrlH XRow. dreulX
\'11 ~I'
-II'AH-
X o n:l.IWrell
-~/I'"
-=;;;/~~.
~ t""~
~
111('
!lm
\"H
\'11.
1-------'"<'________-1
It .~H
INA ~
~
to.
.x
-
r-'HI'- "~kRIJ_
~
CAS ~;~~,
lAS.
Address
~~~~.5f¥l~~rc~t~~c~~~c:t====
l)c~1I
g:~:-------i:
!IIH
\tI id Hala
~-IIJ//HIlpt·n
.READ·WRITE/READ·MODIFY·WRITE CYCLE
• PAGE MODE WRITE CYCLE
...-------,,,---------,
c,-\s
r',~
,.\ddress
~:::':)j~~~K;;~;:J~~=t=:::~~~=1t===
tAU
•
HITACHI
255
HM4864A-12, HM4864A-1l5,=-----HM4864A-20, HM4864AP-12,
,HM4864AP-1l5, HM4864AP-20
65536-word x 1-blt Dynamic Random Access Memory
• FEATURES
• Industry standard 16- Pin DIP (plastic, Cerdip)
• Single 5V (±10%)
• On ch ip substrate bias generator
• Low Power: 250mW active, 18mW standby
• High speed: Access Time 120ns / 150ns /200ns
• Common I/O capability using early write operation
• Page mode capability
• Output data controlled by CAS
• TTL compatible
• 128 refresh cycles - (2ms)
• Hidden refresh capability
HM4864A-12, HM4864A-15,
HM4864A-20
~
.... ..
,.,
,.,.":,,,
~I'
(DG-IIB)
• BLOCK DIAGRAM
HM4864AP-12, HM4864AP-15,
HM4864AP-20
Din
Memory
Ar'tll
Row Do..
!~ i
j dj
~
g
1
~
MollO',
~
Array
Memory
Do..
~
Array
1
_Vce
Row Doc. ~
tol, ... "
--0
.,1 --I
v..
V.. aenerator
I
(DP-II)
Array
• PIN ARRANGEMENT
.ABSOLUTE MAXIMUM RATINGS
Voltage on any pin relative to Vss " " " " " ' , '
Operating temperature, Ta (Amblant) " " " ' , "
Storage temperature (Cerdlp) , , , , , , , , , , , , , , , "
Storage temperature (Plastic) " ••.• " ••• , •• ,,'
Power dissipation ••••••••• "', ••• ,,.,.,.,.,'
Short circuit output current, ••••••••••••••• ,.
-tV to 7V
oOe to 70°C
_66°C to 150°C
-66°C to 125°C
1W
50 mA
• RECOMMENDED DC OPERATING CONDITIONS (Ta- 0 to 70'C)
min.
typo
Supply Voltag.
V.e
4.5
5.0
Input High Volta,e
V,.
2.4
Input Low Volta,';
VEL
-1.0
Parameter
Symbol
-
max.
Unit
Note.
5.5
V
1
6.5
V
1
0.8
V
1
Not.es : 1. All voltaps referenced to V u
(Top View)
AO-A7
00
Din
Dout
RAS
WE
Vee
Vss
AO-A6
256
•
HITACHI
Address Inputs
Column Address Strobe
Data In
Data Output
Row Address Strobe
ReadlWrite Input
Power (+5V)
Ground
Refresh Address Inputs
- - - - - - - - - - - - - - - - - - - - H M 4 8 6 4 A - 1 2 , HM4864A-15, HM4864A-20,
HM4864AP-12, HM4864AP-15, HM4864AP-20
.DC ELECTRICAL CHARACTERISTICS (Ta-O to 70'C, Vcc-SV±lO%, Vss-OV)
Parameter
Symbol
Operati., CurrentCRAS;'CAS Cycli.,:he-min)
Standby CnrrentCRXS"- V,., Dout-High Impedance)
Refresh CurrentCRAS" Cyeli.,,~- V,., he-min)
Standby CurrentCRXS"- V,.,Dout Enable)
Page Mode Current(KAS- V,£,CAS Cyeling:lpe-min)
Input Leakage(0..
~
Ilh
},.
It",.. Addl'f'~\~
'--
,,,
I
IhH
tlp.n
I-~
-
10H
V,lldOa'.
V"L
DlJun',Ca""
eWRITE CYCLE (EARLY WRITE)
Ri\':~
1-----
r,ft
,,,
"
11IA\
I'u
,
t.en
l'1:C;
v"
"'n
v"
WffSltl
~
n tA~r"1
,.....,. t-
Wi:
\',.
I'lL
r'll
~'IL
258
IU'L
I
1/lilL
I
.=-1t-t/J!I~
Valid 0.11
J
0",
1'"
rOL
•
~
tel'''
X
b(
0
Jt
l\--
,,,
~
,E ,., D.¥
:k
0".
"""'
Ie ...
V.tf
T
IIIT/l ,
0"
I
Row .o\ddrl'ss..J<.......)q CDlulIIII MlffU
\'IL
--n
tits,.
HITACHI
------------------------------------~--HM4864A.12,HM4864A·15,HM4864A·20,
I1M4864AP·12, HM4864AP·15, HM4864Ap·20
.READ·WRITEIREAD·MODIFY·WRITE CYCLE
."
V"
1m
V"
."."5.
bCD
V..
CAS
V"
V..
AddRlR.
V"
V..
WE
V"
V~
Doo.
V"
V..
Om
V"
.",
'.
----------------."~.~~---
--------------~. . . --=--o
Don'(Care
."RAS·ONLY" REFRESH CYCLE
"'N
RA.'i
~'n
V"
t::\.<;
V"
V"
Addrenrl
I'll
V",
~.,
V"
DDon'ICare
.PAGE MODE READ CYCLE
V"
RAs
CAs
v"
v"
v"
IAU
Mllre.lII.
00..
iii:
v"
v"
v~
v"
v"
l'n
CJDan'IC.n!
•
HITACHI
259
HM4864A-12,HM4864A-15,HM4864A-20---------------------------------------HM4864AP-12, HM4864AP-15, HM4864AP-20
.PAGE MODE WRITE CYCLE
o
Don't Care
• HIDDEN REFRESH CYCLE
m
v,s
\'/1,
v"
CAs
v"
~'11r
Address"
v"
WE
v"
v"
v"
Doo'
Vo<
Dnon'tCare
260
•
HITACHI
HM4864ACG-12, HM4864ACG-15,
HM4864ACG-20
Preliminary
65536-word x 1-bit Dynamic Random Access Memory
•
•
•
•
•
•
•
•
•
•
•
•
FEATURES
t8-pin Leadless Chip Carrier
Single SV (±10%)
On chip substrate bias generator
Low Power: 2S0mW active, 18mW standby
High speed: Access Time 120/150/2oons (max)
Common I/O capability using early write operation
Page mode capability
Output data controlled by CAS
TTL compatible
128 refresh cyclesl2ms
Hidden refresh capability
(eG-IS)
.PIN ARRANGEMENT
.BLOCK DIAGRAM
WE
R/W SWIIC/t
Utn
RAS
Memory
CAS
Array
....!
<
i
i
.= ~ .
~ 8
S
0
Memory
Doul
- Row Dec.
;,
Row Dec.
Array
Memory
Array
~
~
8
--aVec
--0
~
Memorv
Arrav
Vss
VltB Gen~ralor
I
(Bottom View)
AO-A7
CAS
• ABSOLUTE MAXIMUM RATINGS
Voltage on any pin relative to Vss ...••......•.... -tV to +7V
Operating temperature, Ta (Ambient) .•.......•... O°C to +70 oC
Storage temperature .................•.•• -6SoC to +150°C
Power Dissipation ••.......••........•.•........••• 1W
Short circuit output current .....••.•.....•.••...•.. SOmA
Din
Dout
RAS
WE
Vee
Vss
AO-A6
Address Inputs
Column Address Strobe
Data In
Data Output
Row Address Strobe
Read/Write Input
Power (+5V)
Ground
Refresh Address Inputs
.RECOMMENDED DC OPERATING CONDITIONS(Ta=O to 70'C)
Parameter
min.
typo
max.
Unit
Supply Voltage
Vel.:
4.5
5.0
5.5
V
1
Input High Voltage
Y,N,
2.4
-
6.5
V
1
Input Low Voltage
V,L
-1.0
-
0.8
V
1
Symbol
Notes
Notes: 1. All \'ul tases referenced to V ~.,
XuteJ The speeifit-ations of this df"\'ice are subjl"ct to changl" without noliee'.
Pleasr ('0018("1 your nearest Hitachi's Sales lliopt. regarding specifications .
•
HITACHI
261
HM4864ACG-12,HM4864ACG-15,HM4864ACG-20-----------------------------------
.
.DC ELECTRICAL CHARACTERISTICS (Ta=O to 70'C Vcc -5V±10% , Vss-OV)
Symbol
Parameter
Operating Current(RAS";"CAS Cycling:IHc-min)
Standby Cnrrent(RAS- V,N,Dout-High Impedance)
Refresh Current(R"AS Cycling,C'AS- V,N,IRe-min)
Standby Current(RAS"- V,N, Dout Enable)
Page Mode Current(RA."S- V,L,CA5 Cyeling;lpe-min)
Input Leakage(O < V.. , <6. 5V)
Output Leakage(Dout is disabled,OBut
Array
How l)er.
ROll\- Dec.
\tl'mutv
Mem"ry
~
- - 0 V~~
-1
\If>lfI(,ry
\rra~
\rrdV
Cent-ralnf
rill!
I
U
(Top View)
RFSH
A.-A,
.ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Voltage on any pin
VT
-1.0 to +7.0
V
Supply Voltage
Vee
-1.0 to +7.0
V
Short Circuit Output Current
101lt
50
mA
Item
CAS
Din
Unit
Power· Dissipation
PT
1.0
W
Operating Temperature
Top,
o to +70
Storage Temperature
Tdl'
-55 to +125
·c
·c
Dout
RAS
WE
Vee
V••
A.-A.
Refresh
Address Inputs
Column Address Strobe
Data In
Data Out
Row Address Strobe
Read/W rite Input
Power (+5V)
Ground
Refresh Address Inputs
* with respect to Vs s
.RECOMMENDED DC OPERATING CONDITIONS (Ta=O to +70'C)
Item
Supply Voltage
Input Voltage
typ
max
Vee
4.5
5.0
5.5·
V
Vss
0
0
0
V
Symbol
min
V,.
2.4
-
6.5
V
ViL
-1.0
-
0.8
V
Note) All voltages referenced to Vss.
266
Unit
•
HITACHI
- - - - - - - - - - - - - - - - - - - - - H M 4 8 6 5 A P - 1 2 , HM4865AP·15, HM4865AP-20
• DC ELECTRICAL CHARACTERISTICS (Ta=O to 70'C, Vcc=SV±lO%, Vss-OV)
Operating Current(RAS";1::AS Cycling:hc-min)
Standby Cnrrent(RA"S- V,H,Dout-High Impedance)
Refresh Current(RAS" Cycling,CAS - V,H,hc-min)
Standby Current(RAS'- V,H,Dout Enable)
Page Mode Current(RAS- VIL,CAS Cycling;lpc-min)
Auto Refresh Current (RFSH -Cycle, RAS ~ ViH)
Input Leakage( 0 < V ••• <6. 5V)
Output Leakage(Dout is disabled,0<)
Address
>-
t-----IH"j+--+------t
_ _ _ _+-___~,tL.ICS.f-- _ t I I C H _
'\l
""-11
.. _
i-----tOHB+--+---__o...j
_,
Din
Hi Z
Dnul
• READ MODIFY WRITE CYCLE
r----------
--!
I• WC - - - - - - -_ _
Address
Din
Dout
276
'''=1:-----..
->-----
$
HITACHI
- - - - - - - - - - - - - - - - - - - - - H M 5 0 2 5 6 - 1 2 , HM50256-15, HM50256-20
• RAS ONLY REFRESH CYCLE
!-------CRAS----_-!
~ ~--~--+_--------------------------v_--------------------
Address
•
REFRESH ADDRESS Ao-A7(AX.-AX,)
• HIDDEN REFRESH CYCLE
CAS
---I-+--,l
Address
WRITE
-----~~----~~--------------------------r---------
Dout
• CAS BEFORE RAS REFRESH CYCLE
CAS ----------l
Addl'ess
Don't care
•
HITACHI
277
HM50256-12, HM50256-15, H M 5 0 2 5 6 - 2 0 - - - - - - - - - - - - - - - - - - - • COUNTER TEST
. CAS ....................~L
Address
"Wl!I'i'E ___________________________ ///'''\.:
-----7
,,
<
,----
.PAGE MODE CHARACTERISTICS (Ta-O to +70'C, Vcc~5V±10%, Vss-OV)
HM50256-12
Symbol
Parameter
Page Mode Supply Current
Icc?
Ipc
Page Mode Read or Write Cycle
CAS Precharge Time. Page Cycle
Page Mode .Read Modify Write Cycle
Icp
IFCM
HM50256-15
HM50256-20
max
min
max
min
max
-
57
-
48
mA
120
50
165
-
-
37
145
60
195
-
-
n.
n.
n.
-
-
,
-
190
80
250
• PAGE MODE READ CYCLE
t--------tRAs----------I
CAS
----+~~---~
fitCH
WRITE------------~~~r_------~_d---1r__r----------~~--------
278
•
Unit
min
HITACHI
- - - - - - - - - - - - - - - - - - - - - - H M 5 0 2 5 6 - 1 2 , HM50256-15, HM50256·20
• PAGE MODE WRITE CYCLE
"RAS
Address
Din
Hi Z
Oout
\
•
HITACHI
279
HM50257-12, HM50257-15, -Preliminary
HM50257-20
262144-word x 1-blt Dynamic Random Access Memory
•
•
•
•
•
•
•
•
•
•
•
•
FEATURES
Industry standardt6-pin DIP
Single 5V (±10%)
On chip substrate bias IJ8nerator
Low Power: 350mW active, 20mW standby
High speed: Access Time 120ns/150ns/200ns (max_)
Common I/O capability using early write operation
Nibble mode capability
Indifinite Dout hold using ~ control
TTL compatible
256 refresh cycles ..... (4ms)
3 Variations of refresh; RAS only refresh, CAS befor RAS
refresh, Hidden refresh
(DG-I88)
• PIN ARRANGEMENT
• BLOCK DIAGRAM
(Top View)
A.-A,
CAS"
Din
Dout
~
WE'
Vee
V ••
A.-A,
• ABSOLUTE MAXIMUM RATINGS
Voltage on any pin relative to Vss . _ .. _ ...•. _ ... -tV to +7V
Operating temperature, Ta (Ambient) .. : ....... O°C to +70°C
Storage temperature .... _ • . . . . . . . . . . . . . _65°C 'to +150°C
Power dissipation . _ ..... _ .... _ . . . . . . . . . . . . . . . . . 1W
Short circuit output current . . . . . . . . . . _ •......... 50mA
Address Inputs
Column Address Strobe
D.ta In
Data Out
Row Address Strobe
Read/Write Input
Power (+5V)
Ground
Refresh Address Inputs
.RECOMMENDED DC OPERATING CONDITIONS (Ta-O to +70·C)
Parameter
Symbol
Supply Voltage
Vee
Input High Voltage ... VIH
"--,---- r---:-'
Input Low Voltage
Vn
min
typ
4.5
2.4
-1.0
5.0
-
max
5.5
6.5
0.8
Note 1) AU voltages referenced to V 8&
280
•
HITACHI
Unit
V
V
V
Note
1
1
1
Not.e)
The specifications of thle device are subject to
eha. without notice.
Please contact your nearest Hitachis Sales
Dept, regardl .... specifications.
- - - - - - - - - - - - - - . - - - - - - I H M 5 0 2 5 7 - 1 2 . HM50257-15. HM50257-20
.DC ELECTRICAL CHARACTERISTICS (Ta=O to +70'C. Vcc=5V±lO%. Vss=OV)
HM50257-12
Parameter
Symbol
Operating Current (RAS, CAS Cycling: he-min)
Stand by Current (RAS-V,H, Dout~High Impedance)
Refresh Current (RAS only Refresh, IRe-min)
Standby Current (RAS- V,H, Dout Enable)
Ic ci
min
-
Icc!
Refresh Current( CAS before RAS Refresh, iRe- min)
Icc6
Input 1eakage (0 < V•• , < 7V)
Output leakage (0< V.. , < 7V)
Output levels High U.. ,- -SmA)
Output levels Low U..,-4.2mA)
ILl
HM50257-15
max
min
max
-
83
4.5
70
4.5
feea
-
62
Ices
-
10
-
69
10
10
Vee
0.4
-
fLo
-10
-10
VOH
VOL
2.4
0
-10
-10
2.4
0
HM50257-20
min
max
53
-
10
-
42
10
58
10
10
Vee
-
45
-10
-10
2.4
10
10
Vee
0
0.4
0.4
55
4.5
Unit
Notes
mA
1
mA
mA
mA
1
mA
pA
pA
V
V
Notes) 1. Ict' depends on output loading condition when the device is selected Icc max, is specified at the output open condition .
• CAPACITANCE (Vcc =5V±lO%. Ta=25'C)
Parameter
Symbol
typ
max
e"
-
5
C"
-
7
I Address, Data-In
I Clocks, Data-Out
Input Capacitance
Unit
Notes
pF
I
I, 2
Notes) 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS- V,N to disable Dout .
• ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Ta=O to +70'C. Vcc=5V±lO%. Vss=OV)
Parameter
Access Time from RAS
Access Time from CAS
Symbol
tRAe
tCAe
HM50257-12
min
-
max
HM50257-15
min
max
120
-
ISO
60
30
50
-
75
40
50
-
HM50257-20
min
-
max
2,3
3,4
50
50
ns
ns
ns
-
ns
ns
tOFF
Transition Time (Rise and Fall)
IT
Random Read or Write Cycle Time
RAS Precharge Time
toe
toP
RAS Pulse Width
RAS Pulse Width
RAS to CAS Delay Time
hAS
90
120
60
10000
10000
150
tCAS
RAS Hold Time
tasH
25
60
60
-
-
tCSH
120
-
200
-
ICRP
10
0
-
25
75
ISO
100
30
100
10
-
-
0
15
10
0
-
CAS Hold Time
CAS to RAS Precharge Time
tRCD
-
3
260
100
75
Row Address Set-up Time
RolV Address Hold Time
1,45R
Column Address Set-up Time
Column Address Hold Time
lAse
tCAH
15
0
20
-
0
25
Column Address Hold Time referenced to RAS
IAR
80
-
WE Command Set-up Time
Write Command Hold Time
twes
0
40
100
40
40
40
-
Write Command Hold Time referenced to RAS
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Set-up Time
hAN
'weN
tweB
Iwp
hWL
tCWL
IDS
0
Data-in Hold Time
IDH
Data-in Hold Time referenced to RAS
tDHR
40
100
Read Command Set-up Time
tRCS
Read Command Hold Time referenced to CAS
tacH
0
0
Read Command Hold Time referenced to RAS
tRRH
10
Refresh Period
tRET:
-
-
3
330
120
10000
10000
75
-
200
-
20
0
100
-
30
130
-
0
-
-
45
120
45
45
45
-
0
55
ISS
-
0
45
-
-
ns
ns
-
-
-
0
10
-
0
0
-
10
-
ns
ns
ns
8
ns
ns
ns
ns
-
-
0
7
ns
ns
ns
-
-
ns
ns
-
-
5
6
ns
ns
-
0
120
4
100
55
155
-
-
ns
-
-
4
10000
10000
55
55
55
-
Notes
ns
200
100
Output Buffer Turn-off Delay
3
220
Unit
ns
ns
9
8,9
ns
ns
ns
-
ns
4
ns
(to be continued )
eHITACHI
281
HM50257-12, HM50257-15, H M 5 0 2 5 7 - 2 0 , - - - - - - - - - - - - - - - - - - - HM50257-12
Symbol
Parameter
max
min
max
265
60
-
-
teu
120
50
10
310
75
150
-
60
10
teRR
120
-
150
tape
0
-
0
Read-Write Cycle Time
tawc
CAS to WE Delay
RAS to WE Delay
CAS Prech.rge Time
leWD
taWD
tCPN
CAS Setup Time
CAS Hold Time(CAS before RAS Refresh}
RAS Precharge to CAS Hold Time
HM50257-15
min
Notes
1. AC measurements assume tT =5ns.
2. Assumes that tRCD s: tRCD (max). If tRCD is-greater
than the maximum recommended value shown in this
table, tRA C exceeds the value shown.
3. Measured with a load circuit equivalent to 2ITL loads
and 100pF.
4. Assumes that tRCD ~ tRCD (max).
5. tOFF (max) defines the time at which the output
achieves the open circuit condition and is not reference to output voltage levels.
6. VIH (min) and VIL (max) are reference levels for
measuring timing of input signals. Also, transition
times are measured between VIH and VIL'
7. Operation with the tRCD (max) limit insures that
tRAC (max) can be met, tRCD (max) is specified as a
reference point only, if tRCD is greater than the
specified tRCD (max) limit, then access time is
controlled exclusively by tCAC'
HM50257-20
min
max
Unit
-
ns
-
200
80
-
ns
ns
ns
-
10
-
200
0
-
390
100
-
ns
twcs, tCWD and tR WD are not restrictive operating
parameters.
They are included in the data sheet as electrical
characteristics only; if twcs f; twcs (min), the cycle
is an early write cycle and the data output pin will
remain open circuit (high impedance) throughout the
entire cycle; if tCWD f; tCWD (min) and tRWD ~
tR WD (min) the cycle is a read-write and the data
output will contain data read from the selected cell; if '
neither of the above sets of conditions is, satisfied the
condition of the data out (at access time) is indeterminate.
9. There parameters are referenced to CAS'leading edge
in early write cycles and to WE leading edge is delayed
write or read-modify-write cycles.
10. An initial pause of 100"s is required after power-up
followed by a minimum of 8 initialization cycles.
II. Minimum of 8 CAS before RAS refresh cycle is required before using internal refresh counter .
8.
eREAD CYCLE
I----------"c-----------I
tRAS _ _ _ _ _~
i------tRcD
I -_ _ _ _
Address
'RSH
,,,_--+_t:=::r-----Jf"
-:-""±-+--t---,hr_-~±--+-+_--..t__,r----+----------
tReN
WRITE
Dout
282
8
ns
ns
• TIMING WAVEFORMS
"'fiAs
Notes
------+-----------~---+--------------~~-------------
_'_RAC_""~.10----""1eHITACHI
HM50257-12, HM50257-15, HM50257-20
• WRITE CYCLE
f------------,.c----------t
CAS
-
tAIII
Address
~
t~
'"
f - - - - - ....
-----lv
ICAN
to-
X}
}
t-----, ..Cjr--t------t
_ _ _ _+-___,---,"" _1---"'''_
'\J
WRITE
'O'P_ /
t-----lnHR+-+---~--I
I---'DHDin
Hi Z
Dout " _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
• READ MODIFY WRITE CYCLE
I----------,.wc------------I
Address
Din
----tRAc
r.
1.
Dout
•
""=1-----..>>---HITACHI
283
HM50257 -12, HM50257 -15, HM50257-20 - - - - - - - - - - - - - - - - - - - • RAS ONLY REFRESH CYCLE
i------tRAS---_---l
Unn', care
284
_HITACHI
HM50257-12, HM50257-15, HM50257-20
• COUNTER TEST
CAS ------------~
--:II--:...--------.l--r----------
Add,... - - - - - - - - - - - - - - " - - - - - - - . . - - , - - - - - - - -....
.NIBBLE MODE CHARACTERISTICS (Ta-O to +70·C, Vcc=5V±10%, Vss=OV)
Parameter
HM50257-12
min
max
Symbol
Nibble Mode Supply Current
Icci
Nibble Mode Access Time
Nibble Mode RAS Cycle Time
'NAC
-
390
290
tNRC
Nibble Mode RAS Pulse Width
Nibble Mode Cycle Time
tNITA
Nibble Mode <::AS Precbarge Time
Nibble Mode <::AS Pulse Width
Nibble Mode HAS Hold Time
tNep
50
20
INC
20
40
INCA
tNlCSH
HM50257-15
min
HM50257-20
min
max
37
35
mA
-
ns
ns
57
20
-
48
25
-
-
460
350
-
590
460
60
25
25
45
-
80
-
35
-
-
-
Unit
max
-
-
ns
-
ns
ns
35.
-
55
-
ns
ns
• NIBBLE MODE READ CYCLE
C'AS
--+--+----..I
Address
~ ------------,----------+-----r-----------------------------~--~
Dout
•
HITACHI
285
HM50257 -12, HM50257-15, HM50257 -20 - - - - - - - - - - - - - - - - - - - -
• NIBBLE MODE WRITE CYCLE
Address
WlITi'E - - - - - " "
Din
Dnul
286
Hi Z
_HITACHI
MOS
•
HITACHI
110M
287
HN61364P, HN61364FP
8192-word x 8-bit Mask Programmable Read Only Memory
HN61364P
The HN61364P/FP is a mask-programmable, byte-organized memory
designed for use in bus-organized systems.
To facilitate use, the device operates from a single power supply, has
compatibility with TTL, and requires no clocks or refreshing because of
static operation_
The active level of the CS, OEo - OE 2 inputs and the memory content
are defined by the user. The Chip Select input deselects the output and
puts the chip in a powerdown mode.
•
•
•
•
•
•
•
•
•
FEATURES
Fully Static Operation
Automatic Power Down
Single +5V Power Supply
Three-state Data Output for OR-ties
Mask Programmable Chip Select and Output Enable
TTL Compatible
Maximum Access Time; 250ns
Low Power Standby and Low Power Operation; Standby 5/lW (typ),
Operation 50mW (typ)
• Pin Compatible with EPROM
• BLOCK DIAGRAM
' - - _ " ' - - - " 1 - _ - - ' - -___
(DP-28)
HN61364FP
(FP-S41
• PIN ARRANGEMENT
• HN61364P
1).
01
D2
Memory
I)'
Matrix
(8192 x 8)
0'
DS
DO
r - - ' -_ _r--~_ _~D7
*Ac:tive level defined by the user.
• ABSOLUTE MAXIMUM RATINGS
Item
Supply Voltage.
Input Voltage*
Operating Temperatlire
Storage Temperature
Bias Storage Temperature
Symbol
Value
-0.3 to +7.0
-0.3 to +7.0
-20 to +75
-55 to +125
-20 to +85
Vee
Vin
Top,
Tn.
Tbiaa
Unit
V
V
·c
·c
·c
* with respect to Vss
•
(Top View)
RECOMMENDED DC OPERATING CONDITIONS
Item
Supply Voltage *
Input Voltage *
Operating Temperature
* with relpect
Symbol
Vee
. VIL
VIH
Top,
min
4.5
-0.3
2.2
-20
typ
5.0
-
max
5.5
0.8
-
Vee
75
•
HITACHI
Unit
V
V
V
• HN61364FP
·c
to Vas
Top View)
288
----------------------------------------------------HN61364~HN61364FP
ELECTRICAL CHARAGTERISTICS (Vee
•
. Item
Input High-level Voltage
Input Low-level Voltage
Output High-level Voltage
Output Low-level Voltage
Input Leakage Current
Output High-level Leakage Current
Output Low-level Leakage Current
Supply Current
= SV±10%. Vss = OV. Ta = -20 to +7SoC
Symbol
Active
II Standby
Input Capacitance
Output Capacitance
Test Condition
flH
V 1L
V OH
VOL
IOH=-205jJA
IOL=3.2mA
Vln=O to 5.5V
lin
hOH V out='2.4V. CS=0.8V. CS=2.2V
hOL Vout=0.4V. CS=0.8V. CS=2.2V
Icc '" V cc=5.5V. Iout=OmA
V cc=5.5V. CS~Vcc-0.2V. CS;;!!0.2V
ISB
Gin
Vln=OV.f=IMHz. T,,=25°C
Gou.t
min
2.2
-0.3
2.4
typ
-
-
-
-
-
10
max
Vcc
0.8
-
-
-
0.4
2.5
10
10
25
30
10
-
-
IS
1
Unit
V
V
V
V
jJA
jJA
jJA
rnA
jJA
pI'
pF
* steady state cu rrent
•
RECOMMENDED AC OPERATING CONDITIONS (READ SEQUENCE)
(Vcc-5V±10%. Vss-OV. Ta--20 to +75"C, t.=t,=20ns)
Symbol
txc
tAA
tACS
tCLZ
tOE
tOLZ
tCHz
tOHZ
tOH
Item
Read Cycle Time
Address Access Time
O1ip Select Access Time
O1ip Selection to Output in Low Z
Output Enable to Output Valid
Output Enable to Output in Low Z
O1ip Deselection to Output in High Z
O1ip Disable to Output in High Z
Output Hold from Address O1ange
min
250
-
max
250
250
-
10
100
10
0
0
10
100
11)0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
e AC TEST LOAD
m
·OV(V CC)
RL =2.4kn
Test Point
130pF
llkn
• TIMING WAVEFORM
~
e Read Cycle (11
Address_..J~---------'I'----
':;'
Notes) 1. t~-tl-20ns
2. CL ineludes jiB capacitance.
3. All diodes are lS2074((1).
NOTES:
Dou.
_-.J::::==:!~E=t~C=::::):IDl
1. Device is continuously selected.
2. Address Vaild prior to or coincident
with l:5 transition low.
L-______________________________________________~·3.
e Read Cycle (21 Notes 1 • 3
oe=v~
====:;j*_
i--tOH=
~
AddreSStA~L
Dou,
t()I1~~
~tRC
____
~w_
e Read Cvcle (31 Notes 2, 3
eHITACHI
289
HN61365P
8192-wordX8-bit Mask Programmable Read Only Memory
The HN61365P is a mask-programmable, byte-organized memory
designed for use in bus-organized systems_
To facilitate use, the device operates from a single power supply,
has compatibility with TTL, and requires no clocks or refreshing
because of static operation.
The active level of the CS input and the memory content are defined by the user. The chip select input deselects the output and
puts the chip in a power-down mode .
• FEATURES
•
•
•
•
•
•
•
•
Fully Static Operation
Automatic Power Down
Single +5 Volt Power Supply
Three-State Data Output for OR-Ties
Mask Programmable Chip Select
TTL Compatible
Maximum Access Time; 250ns
Low Power Standby and Low Power Operation; Standby 5#lW
(typ.), Operation 50mW (typ.)
• Pin Compatible with EPROM
(DP-24)
.PIN ARRANGEMENT
.BLOCK DIAGRAM
A.
AI
A.
A,
A.
A.
A.
A,
A.
A.
A"
All
All
r-I--_Oo
Address
Decoder
Memory
3-State
Matrix
Output
r--O.
r--o.
L-.-J---O.
Buffers
(S192XS)
1---00
Vn=Pin 24
Vss=Pin 12
*CS
* Active level
r:---Ol
1---0.
1---0,
defined by the user.
• ABSOLUTE MAXIMUM RATINGS
Value
Unit
Supply Voltage·
Vee
-0.3 to +7.0
V
Input Voltage·
V"
Top,
-0.3 to +7.0
V
-20 to +75
T.r.
T....
-55 to +125
·c
·c
·c
Item
Operating Temperature
Storage Temperature
Storage Temperature (under bias)
* with respect to
290
Symbol
-20 to +85
VB B
•
HITACHI
(Top View)
-------------------------------------------------------------HN61365P
.RECOMMENDED DC OPERATING CONDITIONS
Item
Supply Voltage·
Symbol
min
typ
max
Vee
4.S
-0.3
S.O
S.5
0.8
V'L
V,.
T..,
Input Voltage·
Operating Temperature
2.2
-20
-
Unit
V
V
V
·C
Vee
15
-
\\' ith respect to Vss
•
.ELECTRICAL CHARACTERISTICS (Vcc=5V ±10%. Vss=OV. Ta=-20 to +75'C)
Symbol
Item
Test Conditions
min
typ
max
Unit
2.2
-0.3
-
Vee
0.8
V
V
V
Input Voltage
V'H
V/L
Output Voltage
VON
VOL
ION--20S}lA
IOL-3.2mA
-
Input Leakage Current
h,
V'N-O-S.SV
-
Active Supply Current
hOL
Icc·
Stand by Supply Current
Is.
Input Capacitance
C..
Output Capacitance
C....I
*
2.4
-
I V... -2.4V
-
0.4
2.S
V
}lA
10
10
}lA
}lA
2S
30
rnA
}lA
-
10
-
IS
pF
pF
-
-
Vee-S.SV, hour-OmA
-
10
CS~Vee-0.2V,
-
1
hOH
Output Leakage Current
-
I V,.,-0.4V
CS-0.8V, CS-2.2V
CS::>0.2V, Vee-S.5V
-
V,.-OV, /-lMHz, Ta-2S'C
Steady state current
.RECOMMENDED AC OPERATING CHARACTERISTICS
eREAD SEQUENCE (Vcc -5V±10%. Vss-OV. Ta=-20 to +75'C. t.-t,-20ns)
Item
Read Cycle Time
Symbol
min
max
I.e
2S0
-
Unit
n.
2S0
2S0
ns
ns
Address Access Time
lAA
Chip Select Access Time
tACS
-
Chip Selection to Output in Low Z
tCLZ
10
-
0
10
100
ns
n.
-
ns
Chip d.s.lection to Output in High Z
Output Hold from Address Change
tCHZ
ION
• AC TEST LOAD
e READ CYCLE (1)
iFi
S.OV
Vee
5.0
Input Voltage"
V/L
V,.
4.5
-0.3
Operating Temprature
T.,.
Item
2.2
-20
• With respect to VS$
292
•
HITACHI
-
-
max
5.5
0.8
Vee
75
Unit
V
V
V
·c
-----------------------------------------------------------IHN61366P
.ELECTRICAL CHARACTE,RISTICS (Vcc-5V±lO%. Vss-OV. Ta--20 to +75'C)
Item
T •• t Conditions
Symbol
V'H
V,.
VOH
Va.
Input Voltage
Output Voltage
I.,
Input Leakag. Current
hON
Output Leakag. Current
IoH --20SJ'A
Io.-3.2mA
V'N-O-S.SV
typ
2.2
-0.3
-
ma.
Vee
0.8
-
0.4
2.5
10
10
2S
10
15
-
-
-
-
2.4
-
OE-0.8V, OE-2.2V
hal..
Operating Supply Current
Input Capacitanc.
Output Capacitance
min
I VouT -2.4V
I VouT-0.4V
Icc·
Vec-S.SV, IouT-OmA
C,.
C.. ,
V,.-OV, I-1MHz, T,,-2S'C
-
-
10
Unit
V
V
V
V
J'A
J'A
J'A
mA
pF
pF
• Steady atate eurreftt
.RECOMMENDED AC OPERATING CONDITIONS
eREAD CYCLE (Vcc -5V±lO%, Vss-OV, Ta--20-+75'C, t,-t,-20ns)
Item
Read Cycle Time
Address Access Time
Output Enable to Output Valid
Output Enable to Output in Low Z
Output Disable to Output in High Z
Output Hold from Address Change
Symbol
min
toe
2S0
-
-
2S0
100
Unit
ns
ns
ns
10
0
10
-
n.
100
ns
na
IAA
10E
tol.Z
tOHZ
10H
max
-
e LOAD CIRCUIT
5.0V( Vee)
Rt.-Z.4kQ
.....-I4-~
Teu pl)int o-~,"""
30pt'
IIkQ
Notes) 1. '.-I,-2OD.
2. CL ineludes jil capacitance-,
3. All dlod•• ore ISZ074i1ll .
• TIMING WAVEFORM
eREAD CYCLE (1)
Addr•••
Do ••
eREAD CYCLE (2) Note
1)
Addreu
Ilo ..
Note} 1.
O'E- V,/.
•
HITACHI
293
HN43128P---------16384 x 8-bit or 32768 x 4-bit CMOS Mask Programmable Read Only Memory
The Hitachi HN43128P is a mask programmable, 16384x8-bit or
32786x4-bit CMOS read only memory. It operates from a single
power supply and is compatible with TTL and OTL. Low power consumption makes this memory well-suited for battery-operation or
hand-held personal computers. Memory expansion can be implemented through two chip select inputs. Either active "High" or active
"Low" of chip select inputs and a chip enable input is defined at mask
level. The organization of 8 bit or 4 bit is designed by the user .
•
•
•
•
FEATURES
Mask-programmable for either 4-bit or 8-bit organization.
Three-state outputs, can be wired-OR.
Two mask programmable chip select terminals facilitate memory
expansion.
A single 5V power supply (±10%).
Low power consumption: Operation 3mW (typ.),
Standby 3p.W (typ.)
TTL compatible
Access time: 6.5p.s (max)
•
•
•
•
•
• BLOCK DIAGRAM
Ilt
'2
1
cs.
'1
'1
I
1
Au
""{ (Au)
CE
CS Lollie
..i
t
Latch
~
r-
CS Contrul
Memory Array
X Decoder
r-
';Z--
I
131072 bit.
t
I
'1
,
,,
V-Decoder
~.~
Timin. Generator
J
*1 Active level defined at mask level.
*2 Mask programmable selection of either 4-bit or
8-bit organization.
In 4-bit organization. data outputs are Do to 03.
294
•
I-
t
T
I
• PIN ARRANGEMENT
-------u,
3-State BuffIn
cs,
(DP-28)
HITACHI
II-
(Top View)
*The most significant address in 4-bi t organization.
r-
-------------------------------------------------------------HN43128P
• ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Rating
Unit
Supply Voltage·
Input Voltage·
Operatinl Temperature Range
Storage Temperature
Vee
Vi.
V
V
Bia. Storage Temperatore
T'I ••
-0.3-+7.0
-0.3-+7.0
-20-+75
-55-+125
-20-+85
Note.
T."
T.,.
* Refereneed to VIS.
'c
'c
'c
• ELECTRICAL CHARACTERISTICS (Vcc=SV± 10%. Vss- OV. To- - 20- +7S'C)
Item
Symbol
Input .. High" Le.el Voltage
Input "Low" Le.el Voltage
Output "High" Le.el Voltage
Output "Low" Le.el Voltage
Input Leakage Current
Output "High" Le.el Leakage Current
Output "Low" Le.el Leakage Current
Supply Current
min
typ
max
Unit
ViN
Te.t Condition
2.4
-
V'L
VON
VOL
I..
0
2.4
-
Vee
0.8
V
V
V
V
pA
pA
pA
pA
IOH--I00pA
lLOL
I"L-1.6mA
-O-5.5V
CE-0.8V
CE-2.4V
I In stand·by
Is.
l;§-= Vee-O.IV
CS4li:V.. +O.2V
lIn operation
Icc·
Isc-7.5Ps
v..
hOH
C;.
Input Capacitance
Output Capacitance
4 ..
* Steady state current
-
-
V... -2.4V
-
-
Vo •• -0.4V
Vee-5.5V
-
0.6
V.. -OV.f-IMHz, Ta-25'C
-
-
1
0.4
2.5
5
5
30
1.5
10
12.5
mA
pF
pF
• AC OPERATING CHARACTERISTICS
.READ SEQUENCE (Vcc -SV±10%. Vss=OV. To--20 to +7S'C. t,-tr20ns)
Symbol
Item
Read Cycle Time
Address Access Time
Chip Enable Acce.s Time
Data Hold Time from Addre.s
Addre •• Set·up Time
Addre.. Hold Time
Chip Enable ON Time
Chip Enable OFF Time
I
i·
:
I
IIIC
min
max
7.5
-
ps
P.
-
6.5
6.0
0.5
-
IAAcc
'SACC
tff
0.05
0.5
0
6.0
leE
1.0
IOF
lAS
IAN
-
-
-
~;..~--I.!------T"~
,....!!.
~ I.
----~I:~~:
In
_I
Ie.
I~
i~
I
.1
Unit
ps
P.
P.
ps
p.
P.
• LOAD CIRCUIT
5.0V( I'>-"H1=Z--I
I
1:
UACe "I
1
t.u,C(l
"--
Notes: 1. t.-ll-ZOna.
2. C" include. iii capacitance.
3. AU diode. are IS2074 ® .
•
HITACHI
295
HN613128P, HN613128FP
16384-wordX8-bit Mask Programmable Read Only Memory
.-------------------~
The HN613128P/FP is a mask-programmable, byte-organized
memory designed for use in bus-organized systems. To facilitate use,
the device operates from a single power supply, has compatibility
with TTL, and requires no clocks or refreshing because of static operation. The active level of the CS, OE o, OE I input and the memory
content are defined by the user. The Chip Select input deselects the
output and puts the chip in a power-down mode .
HN613128P
• FEATURES
(DP-28)
•
•
•
•
•
•
•
•
Fully Static Operation
Automatic Power Down
Single +5-Volt Power Supply
Three-State Data Output for OR-Ties
Mask Programmable Chip Select, Output Enable
TTL Compatible
Maximum Access Time; 250ns
Low Power Standby and Low Power Operation;
Standby:
5p.W (typ.)
50mW (typ.)
Operation:
•
Pin Compatible with EPROM
HN613128FP
(FP-54)
.PIN ARRANGEMENT
.HN613128P
• BLOCK DIAGRAM
Nl
Al
A4
AS
PI>
A7
A1
02
A.
As
III
D5
As
A.
A.
A3
OEo"
AIO
01
A3
Address
3-State
Output
Memory
Matrix
063S.XS)
os
Buffers
lleCude
D6
D7
AS
A'
All
AI2
AI3
• CS--~~~------------------------~
* Active level defined by the user.
.ABSOLUTE MAXIMUM RATINGS
Symbol
Item
Supply Voltage"
Input Voltage"
Vee
V..
-0.3 to +7.0
V
Operating Temperature Range
T."
-20 to +75
-55 to+125
-20 to +85
·c
·c
·c
Storage Temperature Range
T. 16
Storage Temperature Range (under bias)
T....
Unit
V
With respect toVss.
• RECOMMENDED DC OPERATING CONDITIONS
Item
Supply Voltage"
Input Yoltage"
Operating Temperature
*
SY'l'bol
min.
typo
max.
Unit
Vee
Va
V,H
4.5
-0.3
2.2
-20
5.0
-
V
V
-
5.5
0.8
Vee
-
75
·c
T"pr
V
With respect to Vss .
296
CS"
Ao
07
Do
D.
01
05
02
D.
Vss
03
(Top View)
Value
-0.3 to +7.0
*
All
A2
Al
Alq
• OEo
• Ot.
Vee
OEI'
AJ3
DO
A2
NC
Al2
•
HITACHI
.HN613128FP
---------------------------------------------------HN613128~HN613128FP
• ELECTRICAL CHARACTERISTICS (Vcc=S.OV±IO%, Vss-OV, Ta- -20 to +7~'C)
Item
Symbol
Test Condition
Input High·level Voltage
Input Low·level Voltage
Output High·level Voltage
VIN
VON
IOH- -20SI'A
Output Low·level Voltage
VOL
IOL-3.2mA
V/L
min
typ
max
2.2
-0.3
-
Vee
-
2.4
-
Input Leakage Current
I ..
V. -0 to S.SV
Output High·level Leakage Current
lLoH
V••• -2.4V,CS -0.8V,CS - 2.2V
Output Low·level Leakage Current
ll.ol.
V••• -0.4V,CS -0.8V,CS - 2.2V
Supply Current (Active IStandby)
Icc*! I ••
Vee - S. SV,lDoor-OmA ICS;;: Vcc-0.2V,CSSO.2V
Input Capacitance
C••
V.. -OV,f-l.OMHz, Ta-2S'C
-
Output Capacitance
c...
V.. -OV,f-l.OMHz, Ta-2S'C
-
Unit
V
V
0.8
-
-
-
0.4
-
-
2.S
10
-
10
V
V
I'A
I'A
I'A
2S/3O
10
lOll
-
-
mAII'A
pF
pF
IS
If! Steady state current
• RECOMMENDED AC OPERATING CONDITIONS (READ SEQUENCE)
(Vcc=S.OV±lO%, Vss=OV, Ta=-20 to +7S'C,AII timing with 1.-11-20n8)
HN613128P
Symbol
Item
Unit
max
min
Read Cycle Time
he
2S0
-
Address Access Time
t"
Chip Select Access Time
'AC:'
-
2S0
2S0
leLZ
10
-
-
100
-
Chip Selection to Output in Low Z
Output Enable to Output Valid
Output Enable to Output in Low Z
tOE
Chip deselect ion to Output in High Z
kHZ
10
0
Chip Disable to Output in High Z
Output Hold from Address Change
10HZ
0
100
100
10
-
IOLZ
tON
ns
ns
ns
ns
ns
ns
ns
ns
ns
• TIMING WAVEFORM
eREAD CYCLE(1)
Address
/oE
• AC TEST LOAD
/ou
1F!
'ACS
.ovevCC)
teu
R L =2.4kn
Test Point
eREAD CYCLE(2) l1'\ote. 1.31
Address
,,,
.
l30pF
Ilkn
~
-.J
J
,,,
~
-:;-
/0.
/0.
%XXX
Dout
V
/l\
eREAD CYCLE (3) (~ote. 2,3\
CS~~_-----,{
L-_--'=_'~A.C_iskZik~------------IC-.-Z~J_
'm
_' .
.
r
D,",
Notes) 1. l.-f,-20ns.
2. CL includes jig capacitance.
3. All diodes are lS2074@.
NOTES:
:1.: Device
continuously
selected.
AddressisValid
prior to or
coincident
with CS transition low.
---------i
OE = VIL •
•
HITACHI
297
HN612t56P, HN612t56PP
32768X8-bit or 65536X4-bit CMOS Mask Programmable Read Only Memory
The Hitachi HN61256P/FP is a mask programmable 32768 x 8-bit or
HN61256P
65536x4-bit CMOS read only memory_ It operates from a single
power supply and Is compatible with TTL. Low power consumption
makes this memory well-suited 'for battery-operation or hand-held
personal computers. Memory expansion can be implemented through
one chip select input. Either active "High" or active "Low" or chip
select input and a chip enable input are defined at mask level. The
organization of 8 bit or 4 bit is defined by the user.
.FEATURES
e Mask-programmable selection of either 4-bit or 8-bit organization
e Three-state outputs, can be wire-ORed.
• One mask programmable chip select terminal facilitates memory
expansion.
• A single 5V power supply (±10%)
• Low power consumption: Operation 7.5mW (typ.),
Standby 5p.W (typ.)
e TTL compatible
e Access time: 3.5p.s (max)
• BLOCK DIAGRAM
u.
(DP-28)
HN61256FP
(FP-54)
.PIN ARRANGEMENT
eHN61256P
-------u,
cs
I
""{
CS Cl)ntrol
Au
(Au)
CE
X Uecoder
•
2
'1
Thllin. Genetatur
*1 Active level defined at mau \evel.
.2 Mask progr....m.abl4! selection of either 4-bit or
8-bit organization.
In 4-bit orp,nization.data output. are Do to D•.
(Top View)
eHN61256FP
IldlC"Ddll
•
NC
.'"
NC
• NC
,
,
,
u
'-."".,r.rr.rr.;r-==..r
(Top View)
298
•
HITACHI
'"
NC
''""
NC
----------------------------------------------------HN61256~HN61256FP
• ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
Unit
Supply Voltage·
Vee
-0.3-+7.0
V
Input Voltage·
Operating Temperature Range
v..
V
·C
T. ..
-0.3-+7.0
0-+75
-55-+125
T'i ..
-20-+85
·C
Item
T..,
Storage Temperature Range
Bias Storage Temperature Range
Note:
* Referenced to Vu.
·C
III! ELECTRICAL
CHARACTERISTICS
(Vcc=SV±lO%. Vss=OV. Ta=O-+7S'C)
Item
Symbol
Input .. High" Level Voltage
Input "Low" Level Voltage
Output "High" Level Voltage
Output "Low" Level Voltage
Input Leakage Current
Output "High" Level Leakage Current
Output "Low" Level Leakage Current
I In
Supply Current
Test Condition
Vi.
ViL
VON
VOL
I ..
hON
ION--IOO/IA
IOL-1.6mA
lIn operation
(:,.
Output Capacitanee
c...
max
Unit
-
Vee
0
-
0.8
V
V
-
0.4
2.5
-
-
V.. -O-S.SV
V... -2.4V
v... -0.4V
~lEt:~~+U\t
I,.
Icc·
Input Capacitance
typ
2.4
2.4
CE-0.8V
CE-2.4V
hOL
stand·by
min
Vcc-S.SV
1",,-4.0/ls
V.. -OV,j-IMHz, T.-2S·C
-
1
-
1.5
-
-
/lA
/lA
/lA
/lA
5
-
-
V
V
5
30
3.0
-
mA
pF
10
12.5
pF
* Steady state eurrent
• AC OPERATING CONDITION AND CHARACTERISTICS
_READ SEQUENCE (Vcc =5V±lO%. Vss=OV. Ta=O-+75'C. t,=tr20ns)
mo.
min
Symbol
Item
Read Cyeie Time
loe
Address Aeeess Time
!Allce
Chip Enable Aeeess Time
Data Hold Time from Address
tBACC
IDF
0.05
Address Set·up Time
lAS
0.5
Address Hold Time
IA'
0
Chip Enable ON Time
I""
3.0
Chip Enable OFF Time
ICE
0.5
4.0
-
Md~e;.~!
/IS
3.5
ps
3.0
0.5
/IS
-
/Is
ps
~
: -+I---------.,...t5..H~
~
~
I
:"
'}A~C
I
I
1·
u"..
ICl
I.
I I
I
• I
I.
piI
reI
Unit
-
/IS
ps
ps
_ LOAD CIRCUIT
5.0V( Vccl
R.r,_2.4kQ
Test pl)iat
o--t--1--M.......
30pF
frAce
•
t
PI
@(
}f~I
'DF
I
b
JJ.>Ut Valid
llkQ
'HI Z
Notes: 1.I.-I,-20RI.
2. CL includes AI capacitance.
3.AD diode..... IS20741!l> .
•
HITACHI
299
HN613256P, HN613256FP
32768-word x 8-bit Mask Programmable Read Only Memory
The HN613256P/FP is a mask-programmable, byte-organized memory designed for use in bus-organized system.
To facilitate use, the device operates from a single power supply, has
compatibility with TTL, and requires no clocks nor refreshing
because of static operation.
The active level of the CS and OE input, and the memory content
are defined by the user. The Chip Select input deselects the output
and puts the chip in a power-down mode.
HN613256FP .
•
•
•
•
•
•
•
•
•
FEATURES
Fully Static Operation
Automatic Power Down
Single +5V Power Supply
Three-state Data Output for OR-ties
Mask Programmable Chip Select and Output Enable
TTL Compatible
Maximum Access Time: 250ns
Low Power Standby and Low Power Operation;
Standby 5/lW (typ.), Operation 50mW (typ.)
• Pin Compatible with EPROM
(FP-S4)
• PIN ARRANGEMENT
• HN613266P
• BLOCK DIAGRAM'
AO1Al -
A2: -
A31 -
A4f ASI A6i A7,AS; A9,-
Memory
Ou~ut
Bu fer
Address
Decoder
3-State
Output
Buffer
'32,768x8!
,-
I--00
I--01
I--02
r-- 03
I-- 04
I--05
r-- 06
I--07
A10
All -
,-
Al2
,-
Al3
Al4, -
·CS
·OE
..
(Top View)
i
• Active level defined by the user.
* Active level
can be defined by the custom~r.
• HN613266FP
• ABSOLUTE MAXIMUM RATINGS
Item
Supply Voltage*
Input Voltage*
Operating Temperature Range
Storage Temperature Range
Storage Temperature Range (Under Bias)
Symbol
Value
-0.3 to +7.0
-0.3 to +7.0
-20 to +75
-55 to +125
-20 to +85
Vee
ViR
Topr
T.t/I
Tb/M
Unit
V
V
·c
·C
·C
*With respect to Vss
• RECOMMENDED DC OPERATING CONDITIONS
Item
Supply Voltage"
Input Voltage"
Operating Temperature
• With
300
Symbol
min.
typo
max.
Unit
Vee
4.5
-0.3
2.2
-20
5.0
5.5
0.8
V
VIL
VIH
T...
-
-
V
Vee
V
75
·C
re-sJlf't't to V~~.
•
HITACHI
(Top View)
* Acti ve level can be defined by the customer.
---------------------------------------------------HN613256~HN613256FP
• ELECTRICAL CHARACTERISTICS (Vee =S.OV±lO%. Vss =OV. Til = -20-+7S 0 C)
Symbol
Item
Test Condition
VlH
Input Voltage
10H=
VOL
10L- 3.2 rnA
Input Leakage Current
lin
V'n = 0 - S.SV
Output Leakage Current
hOH
CS = 0.8V, CS
=2.2V I
I
Vout = 2.4V
Vout= 0.4V
CS
ISB
V ce = S.SV,
qn
eout
V'n = OV,!= 1
~ Vee - 0.2V, CS S; 0.2V
MHz, To= 2S·C
-
-
- - -
-
Vee = 5.5V,/ou t = 0 rnA
Icc·
Standby
Input Capacitance
Output Capacitance
/AA
/AA
-
hOL
II Active
.
2.S
-
-20S IIA
VOH
Supply Current
Unit
V
V
V
V
~
V1L
Output Voltage
min typ max
2.2
Vee
-0.3
0.8
2.4 0.4
-
10
10
30
30
10
IS
-
10
1
-
IIA
rnA
/AA
pF
pF
• Steady state current
• RECOMMENDED AC OPERATING CONDITIONS (READ SEQUENCE)
(Vcc-5V±10%, Vss-OV, Ta--20-+7S"C, t,=t,-20ns)
Item
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Selection to Output in Low Z
Output Enable to Output Valid
Output Enable to Output in Low Z
Chip Deselection to Ou tpu t in High Z
Chip Disable to Output in High Z
Output Hold from Address Change
Symbol
min
2S0
max
tACS
-
250
250
teLz
10
-
tOE
-
100
tOLZ
10
0
0
10
100
100
tllC
tAA
teHz
tOHZ
tOH
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
• TIMING WAVEFORM
- READ CYCLE (11
Be
eLOAD CIRCUIT
)It
Address
'"
'"
~
cS~
·'CO
'cu
DOllt
~
--.x..
~
'OHZ
'eH1/.
:X
§
I~·::;;=C~.
-===:::::::::::==;-:::~~~-~=~.===5==~~
.
DOllt
---1J,~~r~
// //
L
L._____
-RE~~~CYCLE
I
15.OY!1tt)
'/ / / / /
OE '\ '\ '\ '\ '\'\ '\\.
~
(31 (Notes 2, 3)
"C!a'_____ . . .
·c... ,
r
-
.
•
1_,,","-,-:.
__---1.
HITACHI
I
2. CL inehades jil c.,.citance
'
NO~~: diodes a.. IS2074181
I. Device is continllously selected.
2. Address Valid prior to or coincident
with ~ transition low.
3. OE- VIL •
301
Preliminary-
HN62301P
131,072-wordXB-blt Mask Programmable Read Only Memory
The HN62301 P is a mask·programmable, byte-organized memory
designed for use in bus-organized systems. To facilitate use, the
device operates from a single power supply, has compatibility with
TTL, and requires no clocks or refreshing because of static operation. The Chip Enable and the memory content are defined by the
user. The Chip Enable input deselects the 'output and puts the chip
in a power-down mode .
• FEATURES
•
•
•
•
•
•
•
Static Operation
Automatic Power Down
Single +5-Volt Power Supply
Three-State Data Output for OR-Ties
TTL Compatible
'
Maximum Access Time-350ns
Lower Power Standby and Low Power Operation;
Standby': 2mW (typ.), Operation: 75mW (typ.)
(DP-28)
.PIN ARRANGEMENT
28 Vee
.BLOCK DIAGRAM
A.
AI
A,
.----'----D.
DI
D,
D,
D.
A,
A.
A,
A.
A,
A.
A,
A"
All
A2-AII
Memory Malrix
(32.768 X32)
D,
D.
Addren
Decoder
D,
A"
A"
A"
A"
A,,_'--_-'
.CE--~~--------------------~-------'
(Top View)
.ABSOLUTE MAXIMUM RATINGS
Item
Supply Voltage·
Input VoltageOperating Temperature Range
Storage Temperature Range
Bias Storage Temperature Range
•
Symbol
Vee
V"
Top,
T.,•
T6i ..
Value
-0.3 to +7.0
-0.3 to +7.0
o to +70
-55 to +125
-20 to +85
Unit
V
V
·c
·c
·C
With respect to V'S
Note) The apeclfications of this device are 8ubject to
change without notice.
Plea.e contact your neareat Hitachis Sales
Dept, regarding apecific.tions.
302
•
HITACHI
-------------------------------------------------------------HN62301P
.RECOMMENDED DC OPERATING CONDITIONS (Ta=O to 70'C)
Item
Symbol
Supply Voltage·
Input Voltage·
typ
max
Unit
S.O
S.S
V
-0.3
-
0.8
V
2.2
-
Vee
V
min
Vee
4.S
V,L
v,.
* with respect Vss
.ELECTRICAL CHARACTERISTICS (Vcc=5V±10%. Vss=OV, Ta=O to +70'C)
Symbol
Item
1II0rmai Operating Current
Test Conditions
tacl-min, Vee-S.SV, I •• ,-OmA
Nibble Operating Current
I ccl Icc:.·
Stand by Current
Is.
eE'Oi: Vee-0.2V, Vcc-S.SV
Input Leakage Current
ILl
v,.-O to S.SV, other OV
Output Leakage Current
her-min, Vee-S.SV, I .. ,-OmA
I v,.. -2.4V
I V,.,-0.4V
hON
CE-2.2V
hOL
VON
I n ,--20SpA
VOL
I .. ,-3.2mA
Output Voltage
min
typ
max
Unit
-
IS
SO"
mA
IS
SO"
mA
0.4
10
mA
-10
-
10
pA
-
-
10
pA
10
pA
2.4
-
-
V
-
-
0.4
V
•
Steady state current
• • TBD
.CAPACITANCE (Vcc=5V±10%. Ta=25·C.IMHz V;.=OV)
Symbol
typ
max
Unit
Input Capacitance (A.-A .. , eE')
C/.
TBD
10
pF
Output Capacitance (0.-0,)
COlli
TBD
IS
pF
Item
.AC CHARACTERISTICS (Vcc=5V±10%, Vss=OV. Ta=O to +70'C, t.=t,=20ns)
Symbol
min
max
Unit
hel
3S0
-
ns
Address Aceess Time
IAAI
-
3S0
ns
Mode
Item
Cycle Time
Normal
CE operation
Nibble operation
Data Hold Time
10.
10
-
ns
eE' Access Time
tACE
-
350
ns
eE' Enable Pulse Width
ICE
3S0
-
ns
eE' Disable Pulse Width
lCi
15··
-
ns
Address Set up Time
I ..
0
-
ns
Data Hold Time from eE'
tCHZ
10"
-
ns
Data Set Time from CE
leLZ
10
-
ns
Nibble Address Access Time·
tAAI
-
50
ns
Nibble Cycle Time
her
SO
-
ns
IT
-
40
ns
Turn-on & Turn·off Time
•
Nibble Address Aa,A,
• • TBD
•
HITACHI
303
HNB2301P----------------------------------------------------------.TIMMING CHART
eNORMAL CYCLE (CE-Low)
tl-------..
"RC.-------<~1IOj
Aclelre ••
Dnut
==--t~-0-\\\?-~-,~~:j=
Prevlnu. Dm
1\\\\~\~
Valid Data
eCE CYCLE
1-11--------1"-------+--.......-
Addre ..
Dout
e NIBBLE CYCLE
At-AI.
A..A.
Previoul Dati
OOllt
• AC TEST LOAD
vi
·OV(VCCl
R£"2.4kn
Test Point
130pF
Ilkn
T
,
Note,) 1. "~',-lOftI
t. C. 1..1_ II• ......11.....
S." All il'" .ro 1910'148.
304
•
HITACHI
~
I
•
HITACHI
MOSP
305
HN462716, HN462716G---2048-word x a-bit U. V. Erasable and Electrically Programmable Read Only Memory
The HN462716 is a 2048 word by 8 bit erasable and electrically
programmable ROMs. This device is packaged in a' 24-pin, dual-inline package with transparent lid. The transparent lid allows the user
to expose the chip to ultraviolet light to erase the bit pattern,
whereby a new pattern can then be written into the device.
• Single Power Supply· ... +5V ±5%
• Simple Programming' ... Program Voltage:
+25V DC
Programs with One 50ms Pulse
• Static ............... No Clocks Required
• Inputs and Outputs TTL Compatible During Both Read and
Program Modes
• Fully Decoded-on Chip Address Decode
• Access Time ......... 450ns Max.
• Low Power Dissipation" 555mW Max. Active Power
161mW Max. Standby Power
• Three State Output· .... OR- Tie Capability
• Interchangeable with Intel 2716
HN462716
(DC-24C)
HN462716G
• BLOCK DIAGRAM
(DG-24B)
• PIN ARRANGEMENT
• PROGRAMMING OPERATION
~
CE
Read
Deselect
Power Down
Program
Program Verify
OE
(I8)
(20)
V"
Don't Care
V,.
V"
VIH
Mode
Pulsed
VIL
to
V"
VIL
Program Inhibit
VIH
Don't Care
V,.
V"
V,.
Vpp
Vee
Outputs
(21) (24) (9-11,13-17l
+5 +5
Dout
+5 +5
High Z
+5 +5
High Z
1-25 +5
Din
+25 +5
Dout
+25 +5
High Z
• ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Operating Temperature Range
T.,.
Storage Temperature Range
All Input and Output Voltages·
T."
V" Supply Voltage'
Vr
Vpp
Valu.
o to +70
-65 to +125
-0.3 to +7
-0.3 to +28
Unit
·c
·c
V
V
• With respect to Ground
306
•
HITACHI
(Top View)
----------------------------------------------------HN462716.HN462716G
• READ OPERATION
eDC AND OPERATING CHARACTERISTICS (Ta=O to +70·C, Vcc=5V±5%, VPP-VcC±O.6V)
Item
Symbol
Test Condition
fpPI
VIN-5.25V
VovT-5.25V/0.4V
Vpp-5.85V
Vee Current (Standby)
Icc I
CE - V", OE - Vn
Vee Current (Active)
Icc!
OE-CE-Vn
Input Low Voltage
Vn
V,.
Va.
Va.
ILl
ho
Input Leakage Current
Output Leakage Current
Vpp
Current
Input High Voltage
Output Low Voltage
Output High Vol tage
min.
max.
Unit
10
10
pA
pA
5
25
mA
13
56
mA
-0.1
-
100
V
2.0
-
0.8
Vcc+1
0.4
V
-
V
-
-
-
-
Io.'"2.1mA
10,- -400pA
typo
-
2.4
-
mA
V
Note: V(.(. must be applied sanuhaneously or before V,.,. and removed simultaneously or after V"".
eAC CHARACTERISTICS (Ta=O to +70·C, Vcc=SV±S%, Vpp=VcC±O.6V)
Symbol
Parameter
Test Condition
Address to Output Delay
tAce
OE-CE-V,.
CE to Output Delay
ICE
OE to Output Delay
10E
OE High to Output Float·
10'
Address to Output Hold
10.
OE-Vn
CE-V,.
CE-Vn
OE-CE-Vn
* . llIJ" deflhes the tune at
min.
0
0
..
typo
max.
Unit
-
450
ns
450
ns
120
n.
100
-
ns
n.
typo
max.
Unit
-
6
pF
-
12
pF
-
whICh the output achieves the open CirCUit conditIOn and IS not referenced to output vokaae levels .
eCAPACITANCE (Ta=2S·C,f=lMHz)
Item
Input
Symbol
Test Condition
C..
Capacitanc~
Output Capacitance
VIoV-OV
VQVT-OV
COIOI
eSWITCHING CHARACTERISTICS
Test Conditions
0.8V to2.2V
Input Pulse Levels:
Input Rise and Fall Times:
"20 ns
Output Load:
lTTL Gate + 100 pF
1V and 2V
Reference Level for Measuring Timing: Inputs
Outputs 0.8V and 2V
READ MODE (CE = VIL)
Aelehtss
"'.
Data 0 , , 1 - - - - - - - ( 1
Oata
QUI
Valid
'1<--------""
STANDBY MODE (OE - VIL)
Addrpss
CE
Stanclb:-o Mode
Da'a 01,11---------------{
+ . .,.,
!
i-t..-
\1--'."-
I,.,
f",
eERASE
Erasure of HN462716 is performed bV exposure to ultra·
violet light with a wavelength of 2537A, and all the output
data are changed to "1" after this erasure procedure.
The minimum integrated close (i.e., UV intensity x exposure time) for erasure is 15W • sec/em"
.DEVICE OPERATION
• READ MODE
Dataout is available 450ns (t'ACe) from addresses
with OE low or 120ns (tOE) from OE with addresses stable.
• DESELECT MODE
The outputs may be OR-tied together with the
other HN462716s. When HN462716s are deselected, the O'E inputs must be at high TTL level.
The addresses and inputs are at TTL levels.
After the address and data setup, a 50 ms, active
high program pulse is applied to the CE input. The
CE is at TTL level.
The HN462716 must not be programmed with a DC
signal applied to the CE input.
• POWER DOWN MODE
Power down is achieved with CE high TTL level. In
this mode the outputs are in a high impedance state.
• PROGRAM VERIFY
The HN462716 has a program verify mode. A verify
should be performed on the programmed bits to
determine that they were correctly programmed. In
this mode Vpp is at 25V.
• PROGRAMMING
Initially, and after each erasure, all bits of the
HN462716 are in the "High" state (Output High).
Data is introduced by selectively programming
"low" into the desired bit locations. In the programming mode, Vpp power supply is at 25V and DE'
input is at high TTL level. Data to be programmed
are presented 8-bits in parallel, to the data output
lines (00 to 07).
• PROGRAM INHIBIT
Programming of multiple HN462716s in parallel
with different data is easily accomplished by using
this mode. Except for CE, all like inputs of the
parallel HN462716s may be common.
A TTL program pulse applied to a HN462716's CE
input will program that HN462716. A low level CE
inhibits the other HN462716s from being programmed.
_HITACHI
309
HN462532, HN462532G,--HN462532P
4096-word
x a-bit
U. V. Erasable and Programmable Read Only Memory
The HN46~532 is a 4096 word by 8 bit erasable and electrically
programmable ROM. This device is packaged in a 24-pin, dual-in-line
package with transparent lid. 1;I1e transparent lid allows the user to
expose the chip to ultraviolet light to erase the bit pattern, whereby
a new pattern can then be written into the devica.
The HN462632P is a 4096 word by 8 bit, onetime programmable ROM.
This device is packaged in a 24-pin, dual-in-line plastic package.
• FEATURES
• Single Power Supply. • • • •• +5V ±5%
• Simple Programming ••••• Program Voltage: +25V D.C.
Program with One 50ms Pulse
• Static ••••••••••••••••• No Clocks Required
• Inputs and Outputs TTL Compatible During Both Read and
Program Modes
• Fully Decoded On-Chip Address Decode
• Access Time •••••••••••• 460ns (max.)
• Low Power Dissipation • • •• 858mW (max) Active Power
201mW (max) Standby Power
• Three Stste Output. • • • • •• OR-Tie Capability
• Compatible with TMS2532
HN462532
(DC-2tC)
HN462532G
• BLOCK DIAGRAM
PQwerdown &:
• PIN ARRANGEMENT
Output
Proc. LOSic
HufferR
•••
••
OIJ:"oder
Y Gatinl
•
A.-All
X
32768 bil
EPkOM M,.trix
Llecodfr
••
•
• MODE SELECTION
~.
Mode
Read
Stand by
Program
Program Inhibit
310
CE
(20)
Vpp
(21)
Vee
(24)
VIL
V,N
+5
+5
+5
Dout
+5
High Z
Pulsed V,N to VIL
V,N
+25
+25
+5
+5
Din
High Z
$
Output.
(9 to 11. 13 to 17)
HITACHI
(Top View)
- - - - - - - - - - - - - - - - - - - - HN462632. HN462532G. HN462532P
• ABSOLUTE MAXIMUM RATINGS
Item
Symbol
All Input and Output Voltages·
VT
Vpp
Vpp Voltage·
Operating Temperature Range
Storage Temperature Range
* With respect
10
Value
V
-0.3 to +28
+70
V
·C
-65 to +125
·C
o to
T."r
T~t.
Unit
-0.3 to +7
GND •
• READ OPERATION
- DC AM) OPERATING CHARACTERISTICS (Ta-O to +70·C. Vcc -5V±5%. Vp p- Vcc±O.6V)
Parameter
Iu
Output Leakage Current
fLo
Vpp
Test Condition
Symbol
Input Leakage Current
Current
Icci
Vee Current (Active)
lcci
Input Low Voltage
YrL
VI.
VOL
V..
Input High Voltage
Output Low Voltage
Output High Voltage
-
V... -S.2SV /0.4V
Vpp-S.85V
CE-VI•
CE-Vn
/PPI
Vee Current (Standby)
min
v.. -S.2SV
-0.1
2.0
-
IOL-2.1mA
Io.--400pA
2.4
typ
-
-
max
Unit
10
,.,A
10
,.,A
12
mA
25
mA
150
mA
0.8
V
Vcc+l
V
0.4
V
-
V
Note . VI~' must be apphed unultaneoualy or before V", and removed simultaneously or .fter V"",
.
.
eAC CHARACTERISTICS(Ta-O to +70'C Vcc-5V±5% Vpp-Vcc±O 6V)
Test Condition
Symbol
Parameter
CE'-Vn
min
typ
-
0
-
0
-
Address to Output Delay
lAce
CE to Output Delay
ICE
-
CE' High
IDF
to Output Float·
Address to Output Hold
<:lr- VIL
10.
• : t l!t' defines the tine at which the output achieves the
max
(hit
450
ns
450
ns
100
ns
-
ns
max
Unit
6
pF
12
pF
open circuit condition and is not referenced to output voltap levels.
_ SWITCHING CHARACTERISTICS
Test Conditions
Input Pulse Levels:
Input Rise and Fall Times:
Output Load:
Reference Level fOf Measuring Timing:
O.8V to 2.2V
<20 ns
1TTL Gate + 100pF
Inputs; 1V and 2V.
Outputs; O.SV and 2V
Address
Standby Mode
Oat. Out - - - - - - - - - - - - - - - - {
_CAPACITANCE (Ta-25·C.J-IMHz)
Parameter
Test Condition
Symbol
Input Capacitance
C•• '
Output Capacitance
e...
V.. -OV
Vn. -OV
•
HITACHI
min
typ
-
-
311
HN462532.HN462532G.HN462532P----------------------------------------• PROGRAMMING OPERATION
eDC PROGRAMMING CHARACTERISTICS(Ta-2S'C±S'C. Vcc-SV±S%, Vpp=2SV±lV)
Symbol
Parameter
Test Condition
min
Input Leakage Current
Iu
v.. -5.25V /O.4V
-
VppSupply Current During Programminl!
11'1'2
CE-VIL
-
Vee Supply Current
Icc
Input Low Level
Input High Level
VIL
VI.
-0.1
2.0
typ
-
max
Unit
10
pA
30
150
mA
mA
0.8
Vee + 1
V
V
eAC PROGRAMMING CHARACTERISTICS (Ta=2S'C±S'C, Vcc=5V±S%, Vpp-2SV±lV)
min
typ
max
Unit
Addre .. Setup Time
lAS
2
-
-
ps
nata Setup Time
Address Hold Time
los
2
IA.
2
-
nata Hold Time
10.
2
tvPps
0
0
0
-
-
50
55
-
Symbol
Parameter
Setup Time from
Vpp
Test Condition
Program Puis. Hold Time
Vpp Hold Time
tPRH
Program Pul.e Width
Program Pulse Time
II'W
tPRT
45
5
Program Pulse Time
tPFT
5
tVPPH
ps
-
Note. VCC' must be applied unultaneously or before VPI' and removed slIIIukaneously or .fter V,.,..
e SWITCHING CHARACTERISTICS
Test Conditions
Inpu~ Pulse Level:
Input Rise and Fall Timas:
Output Load:
Reference Level for Measuring Timing:
0.8Vto 2.2V
.;; 20ns
1TTL Gate + 100pF
Inputs; 1V and 2V,
Outputs; 0.8V anI! 2V
Addren
IJ&ll
25V'\7'i7Vornr------------.".
5V
~--------eERASE
Erasure of HN462532 is performed by exposure to ultraviolet light with a wavelength of 2537 A, and all the output
data are changed to "1" after this erasure procedure.
The minimum integrated close (i.e., UV intensity x exposure time) for erasure is 15W • sec/cm' .
NOTE THAT THE HN462543P CANNOT BE ERASED.
312
_HITACHI
-
ps
ps
ns
ns
ns
ms
ns
ns
------------------------------------------HN462532.HN462532G.HN462532P
ACCESS TIME va. AMBIENT TEMPERAlURE
ACCESS TIME va. SUPPLY VOLTAGE
1.000
1.000
800
800
!
~
400
...... ~
200
--
600
400
to-
t200
o3
20
40
SUPPLY CURRENT va. SUPPLY VOLTAGE
SUPPLY CURRENT va. AMBIENT TEMPERAlURE
100
100
80
1
~
.....
l- I -
~
_b::::
80
60
1 6o
0
0
20
80
60
T. ('C)
Vee (V)
ICCI
I.- 1=
-
l - t--
~ ft-
20
ICCI
0
20
40
60
80
T. ('C)
Vee (V)
•
HITACHI
313
HN462732, HN462732G,--HN462732P
4096-word x a-bit U. V. Erasable and Programmable Read Only Memory
The HN462732 is a 4096 word by 8 bit erasable and electrically
programmable ROM. This device is packaged in a 24-pin, dual-in-line
package with transparent lid. The transparent lid allows the user to
expose the chip to ultraviolet light to erase the bit pattern, whereby
a new pattern can then be written into the device.
The HN462532P is a 4096 word by 8 bit, one time programmable ROM.
This device is packaged in a 24-pin, dual-in-line plastic package.
• FEATURES
• Single Power Supply
+5V ±5%
• Simple Programming .....• Program Voltage: +25V D.C.
Program with One 50ms Pulse
• Static •••...•........•.. No Clocks Required
• Inputs and Outputs TTL Compatible During Both Read and
Program Modes
• Fully Decoded On-Chip Address Decode
• Access Time ............ 450ns (max)
• Low Power Dissipation •... 150mA (max) Active Currents
30m A (max) Standby Current
• Three State Output ....... OR·Tie·Capability
• Compatible with INTEL 2732
HN462732
(DC·24C)
• BLOCK DIAGRAM
(DP-24)
Pnwerdown &
Output
Prog.l.uRit-
• PIN ARRANGEMENT
Hulfers
••
Y Galin,
•
••
Decoder
•
3216~
bit
EPROM Matrix
•
••
• MODE SELECTION
:::-------:s
Mode
CE
OE/Vpp
(18)
(20)
Read
Stand by
Program
V,L .
V,L
Program Verify
Program Inhibit
314
V,.
Va
V,L
V,.
Don't Care
Vpp
V,L
Vpp
Vee
(24)
+S
+S
+S
+S
+S
•
Outputs
(9-11, 13-17)
Dout
High Z
Din
Dout
High Z
HITACHI
(Top View)
-------------------------------------------HN462732.HN462732G.HN462732P
• ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Storage Temperature Range
T.,.,
T.,.
All Input and Output Voltage·
Vr
Operating Temperature Range
Vpp
Voltage-
* With respect
Value'
Unit
·c
o to
+70
-65 to +125
-0.3 to +7
-0.3 to +28
OE/V"
·C
V
V
to GND
• READ OPERATION
e DC AND OPERATING CHARACTERISTICS (Ta=O to +70'C, Vcc=5V±5%, Vpp - Vcc±O.6V)
Symbol
Parameter
min.
Test Condition
-
Input Leakage Current (Except OE/V,,)
lUI
V'N-5.25V
OE /V" Input Leakage Current
fLu
Output Leakage Current
fLo
V'N-5.25V
V•• , -5.25V
Vee Current (Standby)
Icc I
CE - V,H, OE - V/L
OE-CE-ViL
Vee Current (Active)
Iccz
Input Low Voltage
Input High Voltage
VIL
Output Low Voltage
Output High Voltage
VOL
IUL-2.1mA
VOH
IOH--400pA
typo
max.
Unit
-
10
pA
10
10
pA
30
mA
mA
V
-
-
-
-0.1
-
2.0
-
V,H
2.4
150
0.8
pA
0.45
V
V
-
V
Vee + 1
eAC CHARACTERISTICS (Ta=O to +70'C, Vcc=5V±5%, Vpp= Vcc ±G.6V)
min
typ
max
Unit
Address to Output Delay
tAce
cr-UE"-V/L
cr to Output
-
-
teE
UE"-V/L
-
Output Enable to Output Delay
tOE
"Ce-V/L
-
450
450
ns
ns
• ns
Output Enable High to Output Float·
tOF
"Ce-V/L
Address to Output Hold
tOH
"Ce-OE""-VIL
Symbol
Parameter
*t
DF
Delay
Test Condition
0
0
-
120
100
-
ns
ns
defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
eSWITCHING CHARACTERISTICS
Test Condition
Input Pulse Levels:
Input Rise and Fall Times:
Output Load:
Reference Level for Measuring Timing:
O.8V to 2.2V
$20ns
1TTL Gate + 100pF
Inputs 1 V and 2V
Outputs 0.8V and 2V
Address
_-..Jx'--__
Standby Mode
Data Out
eCAPACITANCE (Ta=25'C,J=lMHz)
Parameter
Symbol
Test Condition
Input Capacitance (Exeept OE/V,,)
CNI
V'N-OV
01f/V" Input Capacitanee
CN.
V'N-OV
Output Capacitance
c."
Vn' -OV
eHITACHI
min.
-
typo
-
max.
Unit
6
20
12
pF
pF
pF
315
HN462732.HN462732G.HN462732P------------_____________________________
• PROGRAMMING OPERATION
eDC PROGRAMMING CHARACTERISTICS(Vcc-5V±5%, Vpp-25V±lV, Ta~25'C±5'C)
Parameter
Symbol
Test Condition
Input Leakage Current
Output Low Voltage During Verify
/u
V'N-5.25V 10.4V
VOL
/QI.-2.imA
Output High Voltage During Verify
VOH
/QIl--400pA
Vee Supply Current
Icc
Input Low Level
Input High Level (All Input Except OE IVpp)
Vpp Supply Current
VLL
V,H
/pp
min.
--
typo
-
-
-0.1
2.0
-
2.4
-
CE"-VLL,OE-Vpp
-
-
max.
Unit
10
0.4
pA
150
0.8
mA
-
Vce+1
V
V
V
V
30
mA
max.
Unit
-
"sps
eAC PROGRAMMING CHARACTERISTICS (Vcc=5V±5%, Vpp-2SV±lV, Ta-2S'C±S'C)
Parameter
Symbol
Test Condition
min.
2
Address Setup Time
OE Setup Time
Data Setup Time
tOES
Address Hold Time
I'H
OE" Hold
to£H
2
2
0
2
IOH
2
10'
0
tA~
IDS
Time
Data Hold Time
Chip Enable to Output Float Delay·
Data Valid from CE
CE Pulse Width During Programming
OE Pulse Rise Time During Programming
Vpp
*t
Recovery Time
OJ
IDV
CE-VLL,OE-VLL
45
50
2
I""
tPIfT
I"
-
..
defmes the tune at whICh the output achieves the open Circuit conditIOn and IS not referenced to output voltap levels •
e SWITCHING CHARACTERISTICS
Test Conditions
Input Pulse Level:
Input Rise and Fall Times:
Output Load:
Reference Level for Measuring Timing:
O.8V to 2.2V
~ 20ns
1TTL Gate + 100pF
Inputs; 1V and 2V,
Outputs; O.SV and 2V
Protram
Address
O.la
eERASE
Erasure of HN462732 is performed by exposure to Ultra·
violet light of 2537 A. and all the output data are changed
to "1" after this prosedure.
The minimum integrated elose (i.e .• UV Intensity x exposure time) for erasure is 15W • sec/em' .
NOTE THAT THE HN462743P CANNOT BE ERASED.
316
•
HITACHI
PrOlram Vttlf),
typo
-
-
50
-
-
120
1
55
-
ps
ps
ps
ps
ns
ps
ms
ns
ps
-----------------------------------------HN462732.HN462732G.HN462732P
SUPPLY CURRENT va. SUPPLY VOLTAGE
100
SUPPLY CURRENT va. AMBIENT TEMPERATURE
- -
100
f-
~
80
!
I-"'"
i"'-- r--....
BO
!
60
r--. r--...
1m
......... .....
60
.!!
.!!
40
0
20
r- i-'
zo
ICCI
o
lee.
zo
0
3
ACCESS TIME va. SUPPLY VOLTAGE
1.000
800
800
200
,\.
---- -
BO
ACCESS TIME va. AMBIENT TEMPERATURE
1.000
.......... I'--.
60
40
r. ('C)
Vee (V)
400
r-r-
400
~
,..-
I-
200
0
0
Vee (V)
zo
60
40
r.
_HITACHI
80
('C)
317
HN462732GI
-----Wi·de Operating Temperature Range
4096-word x a-bit U. V. Erasable and Programmable Read Only Memory
The HN462732GI is a 4096 word by 8 bit erasable and electrically
programmable ROM. This device is packaged in a 24-pin, dual-In-line
package with transparent lid. The transparent lid allows the user to
expose the "Chip to ultraviolet light to erase the bit pattern, whereby
a new pattern can then be written into the device .
•
•
•
•
•
•
•
•
•
•
FEATURES
Extended Operating Temperature Range ....... -40 - +85°C
Single Power Supply ...... +5V ±5%
Simple Programming ...... Program Voltage: +25V D.C.
Program with One 50ms Pulse
Static.................. No Clocks Required
Inputs and Outputs TTL Compatible During Both Read and
Program Modes
Fully Decoded On-Chip Address Decode
Access Time ............ 450ns (max)
Low Power Dissipation .... 150mA (max) Active Currents
30mA (max) Standby Current
Three State Output ....... OR-Tie·Capability
(DG-24B)
• PIN ARRANGEMENT
• BLOCK DIAGRAM
Powt'rdnwn
I:
nYlput
t'roc.l.OII:ir
Buffen
•••
••
y
lHcodt'r
Y Calin,
•
X
(Top View)
327611 bil
f:PROM Mllrix
Oecncl.r
••
•
• MODE SELECTION
::::------.:.
CE
OE/V,.
Mode
(18)
(20)
Read
Stand by
V,.
PrOlram
V,L
Procram Verib
PrOlram ln6ibit
VIL
V,.
318
V,L
V,L
Don't Cere
V,.
V,L
V,.
Vee
(24)
Outputs
(9-11. 13-17)
+5
+5
+5
+5
+5
Dout
Hich Z
Din
Dout
Hilh Z
•
HITACHI
---------------------------------------------------------HN462732GI
• ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Operating Temperature Range
T.,.
Storale Telhperature Ranle
T. ••
VT
OEIV..
All Input and Output Voltage·
V.. Voltage·
Value
Unit
·C
-40 to +85
-65 to +125
-0.3 to +7
-0.3 to +28
·c
V
V
• With respect to GND
• READ OPERATION
• DC AND OPERATING CHARACTERISTICS (Ta = -40 to + 85°C, V cc=5V ±5%,)
Symbol
Parameter
Test Condition
Input Leakage Current (Except OE IV.. )
OE IV.. Input Leakage Current
hll
Output Leakage Current
1.0
V,.-5.25V
V,.-5.25V
Vout = 5.25V/0.45V
Vee' Current (Standby)
Icc I
CE - V,.,OE- V..
Vee Current (Active)
Icc2
OE-CE-V..
Input· Low Volta,e
Input High Voltage
Output Low Voltage
Output High Voltage
V"
V,.
lUI
typo
min.
-
-
-
-
-0.1
2.0
-
IOL-2.lmA
IOH--400pA
VOL
Va.
2.4
max.
Unit
10
10
10
30
150
0.8
Vee + 1
0.45
pA
pA
pA
-
mA
mA
V
V
V
V
• AC CHARACtERISTICS (Ta = -40 to + 85° C, Vec = 5V ± 5%)
Symbol
Parameter
Address to Ou tpu t Delay
CE to Output Delay
Output Enable to Output Delay
Output Enable High to Output Float*
Address to Output Hold
Test Condition
min.
-
(;E=OE=VIL
OE= V1L
CE= VIL
CE= VIL
CE=OE= VIL
tAce
tCE
tOE
tDF
tOH
-
HN462732GI
typo
max.
450
450
0
0
..
-
ISO
-
130
-
Unit
ns
ns
ns
ns
ns
• 10,. defines the tim. at which the output ach.ves the open eftuit conditlOft and • not referenced to output yoltap levels.
• SWITCHING CHARACTERISTICS
Test Condition
Input Pulse Levels: O.8V to 2.2V
Input Rise and Fall Times:.s; 20ns
Output Load: 1TTL Gate + 100pF
Reference Level for Measuring Timing: Inputs 1 V and 2V
Outputs O.8V and 2V
Address
_-.Jx'--__
Standby Mode
Data Out
.CAPAOTANCE (Ta-2S'C,J-1MHz)
Par....eter
Symbol
Input Capaeitanee (£.eept <>EIV,,)
1m"IV.. Iftput tapaei"nce
Output Capacitance
•
Te.t Condition
CNI
V'H-OV
V, .... OV
c...
V"' -OV
CNI
HITACHI
min.
-
-
typo
-
-
max.
6
20
12
Unit
pF
pF
pF
319
HN462732GI-----------------------------------------------------------• PROGRAMMING OPERATION
eDC PROGRAMMING
CHARACTERISTICS (Vcc-SV±S%. l'pp-2SV±lV. Ta-2S·C±S·C)
Symbol
Parameter
Input Leakage Current
Output Low Voltage -During Verify
Output High Voltage During Verify
Vee Supply
Input Low
Input High
Vpp Supply
Current
Level
Level (All Input Except
OE"IVpp)
Current
eAC PROGRAMMING
Test Condition
VOL
Vo.
Icc
VIL
V,N
Ipp
min.
-
V'N-5.25V 10.4V
IOL-2.lmA
10H- -4001'A
lu
-
typo
max.
Unit
-
10
0.4
I'A
V
V
-
-
-
-0.1
-
2.0
-
2.4
-
CE- VIL. OE - Vpp
-
150
0.8
Vcc+1
mA
V
V
30
mA
~yp.
max.
Unit
-
-
CHARACTERISTICS (Vcc-SV±S%. Vpp-2SV±lV. Ta-2S·C±S·C)
Parameter
Address Setup Time
OE Setup Time
Symbol
Test Condition
toES
Data Setup Time
Addres. Hold Time
min.
2
2
lAS
I.,
2
I,N
-
-
-
-
I's
I's
1'"
tOEH
0
2
Data Hold Time
I ••
2
Chip Enable to Output Float Delay·
Data Valid from CE
I.,
0
-
-
120
I
CE Pulse Width During Programming
lew
45
50
55
OE Pulse Rise Time During Programming
tPIIT
50
2
-
-
m"
ns
-
-
I's
OE" Hold
Vpp
Time
Recovery Time
* ,," defmes the
tlllle at whICh
I.v
I"
the output achIeVes the open
CE- VIL. OE- VIL
.
- and IS not referenced
CirCuit. conditIOn
e SWITCHING CHARACTERISTICS
Test Conditions
Input Pulse Levels: OBV to 2.2V
Input Rise and Fall Times: ~20ns
Output Load: 1TTL Gate + 100pF
Reference Level for Measuring Timing: Input; 1 V and 2V
Outputs; OBV and 2V
Address
eERASE
Erasure of HN462732 is performed by exposure to Ultra·
violet light of 2537 A, and all the output data are changed
to "1" after this prosedure.
The minimum integrated close (j.e., UV intensity x expo·
sure time) for erasure is 15W • sec/em' .
320
•
HITACHI
to output yoltap levels .
-
1'"
1'"
I's
ns
I's-
HN482732AG-20,
HN482732AG-25,
HN482732AG-30
4096-word x S-blt U. V. Erasable and Programmable Read Only Memory
The HN482732A is a 4096·word by 8·bit erasable and electrically
programmable ROM. This'device is packaged in a 24 pin dual·in·line
package with transparent lid.
The transparent lid on the package allow the memory content to be
erased with ultraviolet light.
• FEATURES
• Single Power Supply . . . . .. +5V ±5%
• Simple Programming ...... Program Voltage: +21V D.C
Program with one 50ms Pulse
• Static.................. No clocks Required
• Inputs and Outputs TIL Compatible During Both Read and
Program Mode
• Access Time ........... . HN482732AG-20 200ns (max)
HN482732AG-25 250ns (max)
HN482732AG-30 300ns (max)
• Absolute Max. Rating of Vpp Pin .•. 26.5V
• Low Stand·by Current ........... 35mA (max)
• Compatible with Intel 2732A
(DG-24B)
.PIN ARRANGEMENT
• BLOCK DIAGRAM
1m/v"
cr
Powerdown
&
Output
Prog. LOfI:ic
8uffers
•••
y
Decoder
•
••
Ao-AII
X
(Top View)
Y Cating
3276R hi!
EPHOM Matrix
Decoder
•
••
• MODE SELECTION
~s
MODE
CE
(18)
OE IVpp
(20)
Outputs
Vee
(24)
(S-ll. 13-17)
Read
VIL
VIL
+5
D.~
Sland by
VIN
Don't Care
+5
High Z
Program
VlL
Vpp
Program Verify
VlL
VlL
0",
Program Inhibit
VIN
Vpp
+5
+5
'+5
•
0,.
High Z
HITACHI
321
HN482732AG.20, HN482732AG·25, H N 4 8 2 7 3 2 A G · 3 0 - - - - - - - - - - - - - - • ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Operating Temperature Range
Top,
Storage Temperature Range
All Input and Oulput Voltages'
T. t•
Value
Unit
·C
o to
+70
-65 to +125
V pp Vollage'
VIII, Vo,,'
OE/Vpp
Vee Voltage'
Vee
·C
-0.3 to +7
-0.3 to +26.5
-0.3 to +7
V
V
V
• with respeet to GND
• READ OPERATION
• D.C. AND OPERATING CHARACTERISTICS (Ta-O to 70'C, Vc c-5V±5%)
Parameter
Inpul Leakage Current
Symbol
Iu
VIN-S.2SV
Output ~eakage Current
Vee Current (Standby)
1.0
V... -5.2SV
Icc I
-eE- V,., tiE"- Vn
Vee Current (Active)
Input Low Voltage
Input High Voltage
Icc.
Vn
nE"-'CJr-Vn
V'N
Va.
VON
Output Low Voltage
Output High Voltage
min
Test Conditions
-
-
-0.1
2.0
-
Io.-2.1mA
ION--400l'A
2.4
typ
max
-
10
10
-
35
150
0.8
Vee+1
-
-
0.45
-
Unit
I'A
I'A
mA
rnA
V
V
V
V
.AC CHARACTERISTICS (Ta=O to 70'C, Vcc-5V±5%)
Symbol
Parameter
Address to Output Delay
lAce
CE" to Output Delay
leE
1:lE" to Output Delay
10E
OE High to Output Float
Addres. to Output Hold
ID'
ION
Test Conditions
HN482732AG -20
min
max
-
a-"OE"-V,.
OE'-V,.
a-v,.
a-V,.
CE-1:lE"-vn
HN482732AG -25
min
max
-
HN482732AG ·30
min
max
-
200
200
-
2S0
2S0
-
10
90
10
100
10
0
0
so
-
0
0
90
0
0
-
Unit
300
ns
300
It.
150
130
n.
-
n.
n.
• SWITCHING CHARACTERISTICS
Test Conditions
Input Pulse Level: •.•••.•..••.•.••.• O.SV to 2.2V
Input Rise and Fall Times: • . • • • . • . . . • • • . •. :;;; 20ns
Output Load: ..•....••.•.•.• 1 TTL Gate + 100PF
Reference Level for Measuring Timing ••.•.••.••• Inputs, 1V and 2V, Outputs; O.SV and 2V
Address
Standby Mode
Data Out
.CAPACITANCE (Ta=25'C, f-lMHz)
Parameter
Input Capacitance (Except ~/Vpp)
OE IV pp Input Capacitance
Output Capacitance
322
Symbol
-
Test Condilions
C1NI
V,.-OV
CINa
V,.-OV
CII'"
V ... -OV
•
HITACHI
min
-
-
typ
max
-
6
-
20
12
Unit
pF
pF
pF
--------------------------------HN482732AG-20,HN482732AG-25, HN482732AG-30
• PROGRAMMING OPERATION
.DC PROGRAMMING CHARACTERISTICS (Ta-2S'C±S'C, Vcc-SV±S%, Vpp=21V±O.SV)
Parameter
Input Leakage Current
Output Low Voltage During Verify
Output High Voltage During Verify
Vee Supply Current
Input Low Level
Input HiP Level (AB lapulJ E...pt l!i"lv Pr)
V pp Supply Current
Symbol
Test Condition
Iu
VOL
V ..
Icc
VIL
min
VIN- Vn or V,N
-
IOL-2.1mA
IOH--400JlA
Unit
-
10
0.4
2.4
-
-
-
-
150
mA
0.8
Vcc+1
V
V
30
mA
2.0
<:E"- V'L,
max
-
-0.1
V'H
IFF
typ
-
{jE'- V FF
-
-
JlA
V
V
.AC PROGRAMMING CHARACTERISTICS (Ta-2S'C±S'C. Vcc=SV±S%, Vpp-21V±O.SV)
Parameter
Symbol
Address Setup Time
I ..
C»f Setup
I ...
Time
Data Setup Time
10.
Test Conditions
min
typ
max
Unit
2
2
2
-
-
JlS
-
-
JlS
-
-
JlS
-
-
-
JlS
-
ns
-
-
130
JlS
50
1
55
-
-
ms
ns
-
'Jls
Address Hold Time
IA.
0
(j£" Hold Time
fOIH
Data Hold Time
Chip Enable to Output Float Delay·
I ..
2
2
lop
0
"Clr
IDV
Data Valid from
W
"Clr- VIL,
{jE'- V,L
Pulse Width During Programming
Ipw
45
(j£" Pulse Rise Time During Programming
Recovery Time
I,..,
50
2
V,.,.
•
J
D' defines
Iv.
-
-
JlS
JlS
the time at whieh the output achieves the open circuit condition and is not referenced to output voltage levels.
• SWITCHING CHARACTERISTICS
Test Condition
Input Pulse Level ., ... , .... , ...• ,.. 0.8V to 2.2V
Input Rise and Fall Time .......... , ..... ' :;; 20n5
Reference Level for Measuring Timing: . , ...... , .. , . Inputs 1V and 2V; Outputs O.8V and 2V
Adclrus
0...
• ERASE
Erasure of HN482732A is performed by exposure to
ultraviolet light of 2537 A and all the output data are
changed to "1" after this erasure procedure. The
minimum integrated dose (i.e. UV intensity x ex·
posure time) for erasure is 15W-sec/cm2
•
HITACHI
323
HN482764, HN482764-3,
HN482764-4, HN482764G,
HN482764G-3, HN482764G-4
8192-word x 8-bit U. V. Erasable and Programmable Read Only Memory
The HN482764 is a 8192 word by 8 bit erasable and electrically
programmable ROM. This device is packaged in a 28 pin dual-in-line
package with transparent lid. The transparent lid on the package
allows the memory content to be erased with ultraviolet light•
• FEATURES
• Single Power Supply ••••.••.•••. _ •.•..••.•• +5V ± 5%
• Simple Programming ..••••••.• Program Voltage: +21V D.C.
Program with one 50ms Pulse
• Static •••.•.••••..•••••.•.••.••• No Clocks Required
• Inputs and Outputs TTL Compatible During Both Read and Program Mode.
• Access Time ..•......••..••• HN482764/G 250n5 max
HN482764/G-3 300ns max
HN482764/G·4 450ns max
•
•
•
HN482764, HN482764-3, HN482764-4
(DC-ZSBI
HN482764G, HN482764G-3,
HN482764G-4
High Performance Programming Available
Low Standby Current • • . . . • • . • • . . • . . . ..•• 35mAmax.
Compatible with Intel 2764
• BLOCK DIAGRAM
PQ;i
P,)wer Uown
BE
Prog.IAlic
a:
Output
I:Mfers
(DG-ZSJ
V-Galing
Y-lJecooer
.PIN ARRANGMENT
Ao
65536 bit
X-Uecoder
Au
Memory Matrix
.MODE SELECTION
~
Mode
Read
Stand-by
Vpp
CE
(20)
OE
(22)
PGM
(27)
(1)
Vee
(28)
VIL
VIL
VIH
Vee
Vee
VIH
X
X
Vee
Outputs
(1l-13. 15-19)
.
Dout
High Z
Program
VIL
X
VIL
Vee
Vpp
Vee
Din
Program Verify
VIL
VIL
VIH
Vpp
Vee
Dout
Program Inhibit
V,H
X
X
Vpp
Vee
High Z
x . don t care
.ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Operating Temperature Range
Item
Top.
o to
Storage Temperature Range
T'I,
+70
-65 to +125
·C
·C
All Input and Output Voltage'
VT
Vpp
-0.3 to +7
-0.3 to +26.5·
V
Vpp
Voltage
* . with respect
324
to GND
•
V
HITACHI
-------------------------------------------HN482764,HN482764-3,HN482764-4,
HN482764G,HN482764G-3,HN482764G-4
• READ OPERATION
e DC AND OPERATING CHARACTERISTICS (Ta=O to +70'C, Vcc-SV±S%, Vpp- Vcc±O.6V)
Param~ter
Symbol
Input Leakage Current
Output Leakage Current
typ
Unit
-
rna'
-
10
-
-
pA
pA
1f'1'1
Vrc-S.2SV, V•• -S.2SV
Vee-S.2SV. V••• -S.2SV /0.4V
Vpp-Vee+0.6V
-
Icc I
CE-V,.
-
-
Iccr
CE-OE-V'L
lu
fLo
VI'P Current
Vee Current (Standby)
Vee Current (Active)
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
ViL
Vi.
VOL
VOH
Test Condition
min
-
100
-
-0.1
2.0
-
IOL-2.1mA
10.--4oopA
10
15
rnA
35
rnA
150
mA
V
V
0.8
Vee+l
V
0.45
-
2.4
V
eAC CHARACTERISTICS(Ta-O to +70'C, Vcc=SV±S%, Vpp=Vcc±O.6V)
Symbol
Parameter
HN482764/G
min
max
Test Cmditions
Address to Output Delay
fAce
CE~OE-VIL
CE to
feE
OE-Vn
-
tOE
CE'"- VIL
CE'"- VIL
CE'"~OE -
10
0
0
Output Delay
DE to Output Delay
DE High to Output Float
tDF
Address to Output Hold
too
Note.
'OF
defmes tht' tme at whK'h the output achieves the open
VIL
o.
Circuit COndition
and
IS
250
250
100
90
-
HN 482764 /G-3
min
max
-
300
10
0
0
HN482764/G -4
min
max
-
300
150
10
130
0
0
-
Unit
450
ns
450
150
130
ns
-
ns
ns
ns
not referenced to output voltage levels.
e SWITCHING CHARACTERISTICS
Test Condition
Input Pulse Levels:
Input Rise and Fall Time:
Output Load:
Reference Level for Measuring Timing:
O.8V to 2.2V
~20ns
lTTL Gate + l00pF
Inpu1s; 1 V and 2V
Output; O.8V and 2.0V
Address
Standby Mode
l.tce
Data Out
eCAPACITANCE (Ta-2S'C,J=lMHz)
Parameter
Test Condition
Symbol
Input Capacitance
Coo
v..-OV
Output Capac itanee
COMI
v.•. -OV
•
HITACHI
min
-
typ
max
Unit
4
6
12
pF
8
pF
325
HN482764.HN482764·3.HN482764·4~.~---------------------------------------
HN482764G. HN482764G·3. HN482764G·4
• PROGRAMMING OPERATION
e DC PROGRAMMING CHARACTERISTICS (Ta-25'C±5'C. Vcc-5V
Symbol
Parameter
Input Leakage Current
Output Low Voltage During Verify
Test Condition
V.. -5.25V
[oL-2.lmA
[OH--400pA
lu
VOL
VOH
Output High Voltage During Verify
Vee Current (Active)
Input Low Level
Input High Level
Vpp Supply Current
±5%. Vpp=21V±O.5V)
typ
max
Unit
-
-
10
0.45
pA
2.4
-
ISO
mA
V
min
-
Icc!
-0.1
V/L
V,H
2.0
ar- PGM -
[pp
eAC PROGRAMMING
-
VIL
-
-
0.8
Vee + I
30
V
V
V
mA
CHARACTERISTICS (Ta-25'C±5'C. Vcc-5V±5%. Vpp-21V±il.5V)
min
typ
max
Unit
-
-
Pa
tOES
2
2
Data Setup Time
Addre.s Hold Time
10'
2
Data Hold Time
tON
0
2
-
Addre.s Setup Time
lAS
OE Setup Time
IAH
OE to Output Float Delay
Vpp
Setup Time
PGM
Test Condition
Symbol
Parameter
-
2
-
-
Ip.
50
55
I's
m.
-
ISO
I's
ns
tCES
IDE
-
defines the time at whu:h the output achIeves the open
e SWITCHING CHARACTERISTICS
Test Condition
Input Pulse Level:
Input Rise and Fall Time:
Reference Level for Measuring Timing:
Circuit
..
condition and
IS
not referenced to output voltage levels.
O.8Vto 2.2V
~20ns
Input; 1 V and 2V
Output; O.8V and 2V
Address
Data
• ERASE
Erasure of HN482764 is performed by exposure to Ultra·
violet Iight of 2537 A. and all the output data are changed
to "1" aftar this erasure procedure. The minimum inte·
grated dose (i.e. UV intensity x exposure time) for erasure
is 15W • seclem'
326
I's
I's
ns
0
Data Valid from OE
tDY
-
tD'
ar Setup Time
Note.
I's
1'.
tv,
45
2
Pulse Width During Programming
-
eHITACHI
130
-------------------------------------------HN482764,HN482764-3,HN482764-4,
HN482784G,HN482764G-3,HN482764G-4
• HIGH PERFOMANCE PROGRAMMING
This device can be applied the High Performance Programming algorithm shown in following flowchart.
This algorithm allows to obtain faster programming
time without any voltage stress to the device nor
deterioration in reliability of programmed data.
SET PROG'/VERIFY MODE
Vpp=21±0.5V Vcc=6.0±0.25V
Address + I ..... Address
S=10.11 ... ·15
FAIL
High Performance Programming Flowchart
_HITACHI
327
HN482784, HN482784·3, HN482784·4, - - - - - - - - - - - - - - - - - - - HN482784G,HN482784G·3.HN482784G·4
eAC PROGRAMMING CHARACTERISTICS (Ta-2S·C;U·C. Vcc-SV±O.25V. Vpp-21V±O.5V)'
Parameter
Addre •• Setup Time
Symbol
Test Condition
min
typ
max
tA'
PI
ito..
O'E" Setup Time
Unit
ps
Data Setup Time
Addre •• Hold Time
to,
tA.
o
~
Data Hold Time
tDR
2
1'8
_~ to Output Float Delay'
Vpp Setup Time
Vee Setup Time
..,.:,;:::",:..::..:.=-=~-----
.____
. __
~o.tes)
.t:..:O::..F_ _
:
--+________ __-1'--__~0_+-_ __+-...:1:.:3..:.0-+_-"nl-_
tvps
-
------- _.---;---. tve,----f:
0.95
t",
tCES
t~
1.0
3.8
to""
ps
III £Dr defines the time at which the I)utput achie\'es the open eircuit condition and is not referenced to output \'oltllAe le\"els.
r ""II is defined aa mentioned in flort chart.
* It
•
1.05
ms
~3
m8
_.+-________+-_~_j---_t-~_+-~p..:.s-UO
M
e SWITCHING CHARACTERISTICS
Test Condition
Input Pulse Level:
0.8Vto 2.2V
:::;; 20 ns
Input Rise and Fall Time:
Reference Level for Measuring Timing: Input; 1V and 2V
Output; 0.8V and 2V
328
i
---- -----t----_j--'---
---.-----
.-------+---....:..:=-_+-_______+--:-~_f__:---'---:--:-::-_f_..:.p--=s__
PGM Pulse Width during Initial Program
PGM Pulse Width during Over Program"
Setup Time
Data Valid from OE"
a
-i-__
pi
HITACHI
----------------HN27C64G-20
HN27C64G-25, HN27C64G-30
8192-word X 8-blt UV Erasable and Programmable Read Only Memory
The HN27C64G is a 8192 word by 8-bit erasable and electrically programmable ROM. This device is packaged in a 28 pin dual-in-line
package with transparent lid. The transparent lid on the package allows
the memory content to be erased with ultraviolet light.
HN27C64G-20,
HN27C64G-2S. HN27C64G-30
• FEATURES
• Single Power Supply ........................................ +5V ± 5%
• Simple Programming .................... Program Voltage: +21V D.C .
. Program with one 50ms Pulse
• Static ............................................. No clocks Required
• Inputs and Outputs TTL Compatible During Both Read and
Program Mode.
200ns Max.
• Access Time ............................ HN27C64G-20
HN27C64G-25
250ns Max.
HN27C64G-30
300ns Max.
• High Performance Programming Available
• Low Power Dissipation .................... 40mW/MHz (Active Mode)
525pW Max. (Stand-by Mode)
(DG-28)
• BLOCK DIAGRAM
"'''III ....
~ -(.11, ...
• PIN ARRANGEMENT
• MODE SELECTION
~.
Mode
Read
Staod.by
Pr08lllm
Pr08lllm Verify
Program Inhibit
(20)
OE
(22)
PGM
(27)
v"
(I)
(28)
V,L
V,L
V,H
Vee
Vee
V,H
X
X
Vee
Vee
CE
Outputs
(11-13, 15-19)
Vee
Dout
High Z
VtL
X
V,L
Din
V,L
V,H
V"
Vpp
Vee
V,L
Vee
V,H
X
X
V"
Vee
Dout
High Z
X: don.. care
• ABSOLUTE MAXIMUM RATINGS
Item
Operating Temperatu", Range
Storage Temperatu", Range
All Input and Output Voltage·
V" Voltage
Vee Voltage·
Value
Unit
o to +70
-6510 +125
-0.610 +7.0
-0.6 to +25
-0.6 to +7.0
·c
·c
Symbol
T."..
hll
Yin, You,
V"
Vee
V
V
V
• : with respect to GND
•
HITACHI
329
HN27C64G-20, HN27C64G-25, HN27C64G-30
• READ OPERATION
• DC AND OPERATING CHARACTERISTICS (10=0 to +70"C, Vee=SVtS%, Vpp= veetO.6V)
Parameter
Input Leakage Current
Test Condition
Symbol
ILl
Vce=5.25V, V..=GND to Vee
Output Leakage Current
lip, Current
fLo
Vcc=5.25V, V... =GND to Vee
Vee Current (Standby-I)
ISBI
VPP= Vce+0.6V
/PPI
ISB2
CE= VeetO.3V
Vee Current (Active-I)
Icc!
CE=VII.. V~,=OmA
Vee Current (Active-2)
Iccz
f=5MHz.loul=OmA
typ
max
Unit
-
-
"A
"A
-
CE=VIN
Vee Current (Standby-2)
min
I
2
2
100
-
I
I
100
30
30
0.8
Input Low Voltage
VIL
Input High Voltage
VIH
2.0
-
Output Low Voltage
Output High Voltage
VOL
10I.=2.lmA
-
-
0.45
VON
ION=-400"A
2.4
-
-
-
-0.1
"A
rnA
Vee+0.3V
"A
rnA
rnA
V
V
V
V
• AC CHARACTERISTICS (Ta=O to +70"C, V,·,=SVtS%, Vpp= VeetO.6V)
Parameter
Symbol
Address to Output Delay
lAce
CE to Output Delay
teE
OE to Output
tOE
OE
Delay
High to Output Float
Address to Output Hold
Note;
t OF defines
Test Conditions
CE=OE=VIL
'P<'Thl = VIH
OE=VIL
PGM=VIH
CE=VII.
HN27C64-20
max
200
min
HN27C64-25
min
max
250
-
HN27C64-30
max
300
min
Unit
ns
-
200
-
250
-
300
ns
10
70
10
100
10
ISO
ns
tDF
CE=VII.
0
60
0
90
0
130
ns
tON
~OE='VII.
P M= VIH
0
-
0
-
0
-
ns
the time at which the output achieves the open
• SWITCHING CHARACTERISTICS
Test Condition
Input Pulse Levels:
Input Rise and Fall Time:
Output Load:
Reference Level for Measuring Timing:
CircUit
condition and is not referenced to output voltage levels.
O.BV to 2.2V
~20 ns
1TTL Gate + 100pF
Input; 1V and 2V
Output; O.BV and 2V
Standby Mude
iiE
Oat. Out
• CAPACITANCE (Ta=2S o C,J=lMHz)
Parameter
Input Capacitance
Output Capacitance
330
Test Condition
Vm=OV
pF
pF
VQUI=OV
•
Unit
HITACHI
-------------~----
HN27C64G-20. HN27C64G-25, HN27C64G-30
• PROGRAMMING OPERATION
• DC PROGRAMMING CHARACTERISTICS (Ta=25°Ct 5° C. Vee=5Vt5%. Vpp=2IVt0.5V)
min
typ
rna.
Unit
2
0.45
p.A
2.4
-
feel
-
-
rnA
Input Low Level
VII.
-0.1
Input High Level
V/H
2.0
Vpp Supply Current
Ipp
-
30
0.8
Ycc+O.3
30
rnA
Parameter
Input Leakage Current
Output Low Voltage During Verify
Output High Voltage During Verify
Vee Current (Active)
Symbol
Test Condition
ILl
V.. =5.25V jO.45V
VOL
IOL=2.lmA
VOH
IOH=-400 p.A
CE=PGM=VII.
-
-
-
V
V
V
V
NOTE:
I. Vee must be applied before VPP and removed after VPP.
2. Vpp must not exceed 25V including overshoot.
3. An influence may be had upon device reliability if the device is installed or removed while Vpp=2IV.
4. Do not alter Vpp either V,L to 21V or 21V to VII. when CE=PGM=Low.
• AC PROGRAMMING CHARACTERISTICS (Th=25°C±5° C. Vee=5V±5%. Vpp=2IV±O.5V)
Parameter
Symbol
Address Setup Time
lAS
OE Setup Time
lo£s
Test Condition
min
typ
rna.
Unit
2
2
2
-
-
p.'
p.s
Data Setup Time
IDS
Address Hold Time
IAH
Data Hold Time
IDH
0
2
OE to Output Float Delay·
/oF
-
Vpp Setup .;rime
IVS
PGM:::
IPW
Pulse Width During Programmin
CE Setup Time
Data Valid from
OE
ICES
2
25
2
10E
-
-
-
130
50
55
-
ISO
-
-
p.s
p.s
p..
n,
p..
m,
p.s
ns
Note: t DF defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
• SWITCHING CHARACTERISTICS
Test Condition
Input Pulse Level:
O.8V to 2.2V
Input Rise and Fall Time:
~20 ns
Reference Level for Measuring Timing: Input; 1V and 2V
Output; O.8V and 2V
Program
Program
\'l'tI'y
Address
011. Out
V,lId
InStable
• ERASE
Erasure of HN27C64G is performed by exposure to
Ultraviolet light of 2537A. and all the output data are
changed to "1" after this erasure procedure. The minimum
integrated dose (i.e. UV intensity x exposure time) for
erasure is 15W • sec/cm'
_HITACHI
.,
331
HN4827128G-25,----Preliminary-HN4827128G-30,
HN4827128G-45
16384-Word x 8-bit UV Erasable and Programmable Read Only Mempry
The HN4827128 is a 16384 word by 8 bit erasable and electrically
programmable ROM. This device is packaged in a dual-in-line
package with transparent lid_ The transparent lid allows the user to
expose the chip to ultraviolet light to erase the bit pattern, whereby
a new pattern can then be written into the device .
• FEATURES
• Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . +5V ± 5%
• Simple Programming . . . . . . . . . . . Program Voltage: +21V DC
Program with One 50ms Pulse
• Static...................... .... No Clocks Required
Inputs and Outputs TTL Compatible During Both Read and
Program Mode.
• Access Time . . . . . . . . . . . . . . . . . . . . . 250ns/300ns/450ns
• Absolute Max. Rating of Vpp Pin . . . . . . . . . . . . . . . . 26.5V
• Low Stand-by Current . . . . . . . . . . . . . . . . . . . . . . . . 35mA
• High Performance Programming Available
• Compatible with INTEL 27128
(DG-28)
.PIN ARRANGEMENT
.BLOCK DIAGRAM
POWERDOWN &
PROGRAM LOGlC
OUTPUT
BUFFERS
Y DECODER
Y GATING
X DECODER
131072 bit
MEMORY MATRIX
A.
I
An
• MODE SELECTION
~s
MODE
Read
Stand by
Program
Program Verify
Program Inhibit
CE
(20)
OE
(22)
PGM
(27)
V,,
(1)
V,L
Vi.
Vi.
ViL
Vi.
V/L
Vi.
X
X
Vee
Vee
X
V,.
V/L
V,.
V"
V,p
X
X
V"
Vee
(28)
Outputs
(11-13. 15-19)
Vee
Vee
Vee
Vee
Vee
Note) The specifications of this device are subject to change without notice.
Please contact your nearest Hitachi's Sales Dept. regarding specifications.
332
_HITACHI
Dout
High Z
Din
Dout
High Z
- - - - - - - - - - - - - - - - - - H N 4 8 2 7 1 2 8 G - 2 5 , HN4827128G-30, HN4827128G-45
.ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Unit
·C
o to +70
Top,
Operating Temperature Range
Storage Tempet'ature Range
T.,.
All Input and Output Voltages'
Vpp Voltage·
Y,N, Vn.
Vpp
Vee Voltage-
Vee
·C
-65 to +125
-0.3 to +7
V
-0.3 to +26.5
V
-0.3 to +1
V
• with respect to GND
• READ OPERATION
eDC AND OPERATING CHARACTERISTICS (Ta-O to +70'C, Vcc-5V±5%, Vpp = VcC±O.6V)
Parameter-
Symbol
hi
Vee -5.25V, l-1N-S.25V
Output Leakage Current
h.
Vcc-S.2SV,
VPP~
Icci
CE-l-1N
fecI
CE-OE-l-1L
Input Low Voltage
VIL
VIN
VOL
VOH
Output Low Voltage
Output High Voltage
-
Vec+0.6V
/PPI
Vee Current (Standby)
Vee Current (Active)
Input High Voltage
-
V.•• -S.2SV/0.4V
Vpp Current
typ
min
Test Conditions
Input Leakage Current
2.0
2.4
Unit
10
,.,A
-
10
,.,A
5
mA
3S
60
100
Vee+1
mA
mA
V
V
0.4S
V
-
-0.1
IOL-2.1mA
IOH--400,.,A
max
-
-
0.8
-
-
V
eAC CHARACTERISTICS (Ta-O to 70'C, Vcc =5V±5%, Vpp = Vcc±O.6V)
Symbol
Parameter
Address to Output Delay
tAce
CE to Output Delay
leE
OE to Output Delay
10.
OE High to Output Float
IDF
ION
Address to Output Hold
* 'D' defU1eS the tune at
Test Condition
HN4827128G- 25 HN4827128G- 30 HN4827128G-45
max
min
max
250
-
300
-
4S0
ns
2S0
-
300
4S0
ns
100
-
120
150
ns
max
-
CE-OE-VIL
OE-VIL
CE-l-1L
CE-VIL
CE=OE-l-1L
Unit
min
min
-
0
85
0
105
0
130
ns
0
-
0
-
0
-
ns
whICh the output achieves the open CirCUit coruiltlOn and 18 not referenced to output voltage levels.
e SWITCHING CHARACTERISTICS
Test Condition
Input Pulse Levels:
Input Rise and Fall Time:
Output Load:
Reference Level for Measuring Timing:
O.SV to 2.2V
:::;20 ns
1 TTL Gate + 100 pF
Inputs; 1V and 2V
Outputs; O.SV and 2.0V
o•• ,()q,
eCAPACITANCE (Ta-2S'C, f= 1 MHz)
Parameter
Symbol
Input Capacitance
G.
Output Capacitance
en.
Test Condition
V..-OV
V••• -OV
•
HITACHI
min
-
typ
max
Unit
4
6
pF
8
12
pF
333
HN4827128G-25, HN4827128G-30, H N 4 8 2 7 1 2 8 G - 4 5 - - - - - - - - - - - - - - - - -
.PROGRAMMING OPERATIQN
eDC PROGRAMMING CHARACTERISTICS (TIJ-25"C±5"C. Vcc -5V±5%. Vpp -21V±O.5V)
Parameter
Input Leakage Current
Output Low Voltage During Verify
Output High Voltage During Verify
Vee Current (Active)
Input Low Level
Input High Level
Vpp Supply Current
Symbol
I.,
VOL
VON
Icc.
V/L
V,.
Ipp
Te.t Condition
V,N -5.25V
IoL-2.1mA
ION- -400pA
min
-
2.4
-0.1
2.0
-
CE-PGM-V,L
typ
-
max
-
Unit
pA
V
V
100
mA
0.8
Vcc+l
V
V
30
mA
10
0.45
eAC PROGRAMMING CHARACTERISTICS (TIJ-25"C±5"C. Vcc-5V±5%. Vpp -21V±O.5V)
Parameter
Addre •• Setup Time
OE Setup Time
Data Setup Time
Addre.s Hold Time
Data Hold Time
OE to Output Float Delay
Vpp Setup Time
PGM Pulse Width During Programming
CE Setup Time
Data Valid from OE
Symbol
Test Condition
min
2
2
2
0
2
0
2
45
2
I ..
tOIS
los
IA'
IDR
10,
Iv.
I,.,
teEs
-
I ..
Note. b, define. the tuae at which the output achieves the open Circuit condition and i. not referenced to output voltqe levell.
e SWITCHING CHARACTERISTICS
Test Condition
Input Pulse Level:
0.8V to 2.2V
Input Rise and Fall Time:
:5;20 ns
Reference Level for Measuring Timing: Input; 1V and 2V
Output; 0.8V and 2V
Pro,ram
Address
Do..
In Stabl.
tClS
eERASE
Erasure of HN4827128 is performed by exposure
to ultraviolet light of 2537A and all the output data
are ehanglld to "1" after this erasure procedure.
The minimum integrated dose (i.e. UV intensity x
exposure time) for erasure is 15 Wosee/em 2 •
334
•
HITACHI
typ
max
-
-
-
-
130
-
50
55
-
-
-
150
Unit
p.
p.
p.
p.
p.
n.
p.
m.
p.
n.
- - - - - - - - - - - - - - - - - - H N 4 8 2 7 1 2 8 G - 2 5 , HN4827128G-30, HN4827128G-45
.HIGH PERFORMANCE PROGRAMMING
This device can be applied the High Performance Programming algorithm shown in following flow chart.
This algorithm allows to obtain faster programming
time without any voltege strass to tha device nor
deterioration in raliability of programmed data.
High Performance Prolrammihg Flowchart
eAC PROGRAMMING CHARACTERISTICS (Ta-2S·C±S·C, Vcc-6V±O.25V, Vpp -21V±O.SV)
Parameter
Acldr••• Setup Time
OE Setup Time
Data Setup Time
Address Hold Time
Symbol
Test Condition
min
I ..
2
100S
los
2
2
typ
max
-
-
Unit
ps
-
ps
ps
-
I,.
0
Data Hold Time
OE to Output Float Delay·
10.
2
IoF
0
V" Setup Time
Vee Setup Time
PGM Pulse Width during Initial Program
PGM Pulse Width during O.er Prngram··
tvps
loes
2
2
-
I",
0.95
1.0
CE Setup Time
Data Valid from OE
les.
3.8
2
lOB
-
10FW
-
-
-
ps
130
ps
ns
ps
-
ps
63
ms
ms
150
ps
ns
1.05
-
• tD" defines the time at whleh the output achieves the open circuit conditions and is not referenced to output voltap levels.
• * lop... i. defined a. mentioned In now chart.
e SWITCHING CHARACTERISnCS
Test Condition
Input Pulse Level:
O.8V to 2.2V
::; 20 ns
Input Rise and Fall Time:
Reference Level for Measuring Timing: Input; 1V and 2V
Output; 0.8V and 2V
_HITACHI
335
HN48016P---------2048-word x 8-bit Electrically Erasable and Programmable ROM
This device operates from a single power supply and features fast
single address location programming. All the words are erased by one
TTL level pulse. Erasing the bit pattern and programming new
pattern can be made within 42 seconds .
• FEATURES
• Single Power Supply . . . . .. +5V ±5%
• Simple Programming. . . . .. Program voltage: +25V D.C.
Program with one 20ms pulse.
• Electrically Erasing. . . . . .. Erase Voltage: +25V D.C.
Erase all words with one 200ms pulse.
• Fully Static. . . . • . . . . . . .. No clocks required.
• Inputs and Outputs TTL compative during read, program and
erase mode.
• Fully Decoded .........• On-Chip Address Decode.
• Access Time ....•.....•• 350ns Max.
• Low Power Dissipation . . .. 300mW Max.
• Three State Output. . . . . .. OR-Tie Capability
• Pin-out Compatible with Intel 2716 .
I DP-241
• PIN. ARRANGEMENT
• BLOCK DIAGRAM
CS.
Prog. &
Erase l.alit'
\'""
--.._------'
Otltptn Bufft'fS
·••
X' Decoder
(Top View)
•
163RI bil
EEPROM Matrix
•
• MODE SELECTION
~s
Mode
Read
Deselect
CS
Vpp
(20)
(21)
Vee
(24)
Vn
V,L
Don't Care
V,H
+5
+5
+25
+25
+25
+25
+5
+5
+5
+5
+5
+5
PGM
(I8)
Pulsed V,L 10 V,H
V,H
Program Verify
VIL
V,L
Program Inhibil
V,L
V,H
Pulsed Vn to V, H
V,L
.Program
Erase
336
•
HITACHI
Outputs
(8-11.13-17)
Doul
High Z
Din
Doul
High Z
High Z
_____________________________________________________________ HN48016P
• ABSOLUTE MAXIMUM RATINGS
Symbol
Item
YIN, VO.. I ..
Vee
VPP
All Input and Output Voltage
Vee Voltage
Vpp
Voltage
Operating Temperature Range
T.,p
Storage Temperature Range
T., •
Rating
Unit
-0.3 to Vee +0.3 or Vpp +0.3
V
-0.3 to +7.0
V
-0.3 to +28
+70
V
·C
-55 to +125
'C
o to
• READ OPERATION
eDC AND OPERATING CHARACTERISTICS (Vcc=5V±5%. Vpp=Vcc±O.6V.* Ta=O to +70'C)
Symbol
Parameter
-
lu
VIN-5.25V
Output Leakage Current
h.
VouT-5.25V
Vee Current
/CCl
CS - VIH/Vi.
Current
/PPI
Vpp-5.85V
Vpp
Input Voltage
Output Voltage
* The tolerance of O.6V allows the use of
min
Test Condition
Input Leakage Current
-
typ
max
Unit
-
10
pA
-
-
VIH
2.0
-
-
VON
10H- -100 pA
a drIVer circuit for switehmg the VPI'supply pin from Va:
mA
7
mA
0.8
V
4
-0.1
Io.-1.6mA
pA
50
32
Vn
VOL
10
-
-
V
0.4
V
-
V
2.4
In
read to 25V for prosrammllll.
eAC CHARACTERISTICS (Vcc=5V±5%. Vpp=Vcc±O.6V, Ta=O to +70'C)
Symbol
Parameter
Test Condition
Address to Output Delay
tAce
PGM-CS-Vn
Chip Select to Output Delay
leo
PGM-Vn
Chip Deselect to Output Float
tOF
Address to Output Hold
tOH
PGM-CS-Vn
typ
max
Unit
200
350
ns
70
150
ns
0
40
ns
10
-
100
-
ns
min
-
e TEST CONDITION
Input pulse levels:
Input rise and fall time:
Output loed:
Reference level for Measuring Timing:
O.8V to 2.0V
~20ns
- lTTL Gate + 100 pF
Inputs 1 V and 1.SV
Outputs O.SV and 2.0V
Address
11I.nput
eCAPACITANCE (Ta=25'C,j=lMHz)
typ
max
Unit
Input Capacitance
C••
v..-OV
-
7.5
pF
Output Capacitance
C•••
V... -OV
-
15
pF
Parameter
Test Condition
Symbol
•
HITACHI
337
HN48016P-------------------------------------------------------------
• PROGRAM OPERATION
.DC PROGRAMMING CHARACTERISTICS (Vcc=5V±5%. Vpp-25V±lV. Ta=O to +70'C)
Symbol
Parameter
Input Leakage Current
lu
Supply Current
Supply Current
Icc3
Vee
Vpp
Test Condition
-
/PP2
Input Voltage
typ
min
max
Vi.-5.Z5V
VIL
-0.1
Vi.
Z.O
32
10
-
Unit
10
pA
50
ZO
mA
mA
0.8
V
V
-
.AC PROGRAMMING CHARACTERISTICS (Vcc=5V±5%. Vpp=25V±lV. Ta=O to +70'C)
Symbol
Parameter
Test Condition
min
Address Setup Time
lAS
2
CS Setup Time
tess
2
Data Setup Time
Address Hold Time
CS Hold Time
IDS
2
IAH
tCSH
Z'
7
Data Hold Time
ID'
2
Chip Deselect to Output Float Delay
IDF
Chip Select to Output Delay
Program Pulse Width
leo
0
-
tPRT
15
5
tPFT
5
tpit'
Program Pulse Rise Time
Program Pulse Fan Time
Vpp Setup Time
Ips
10
Ip.
10
~to
Ivs
10
V pp
Iv.
10
Vpp
Hold Time
Program Mode Time
Read Mode Time
typ
max
Unit
-
-
I'S
-
20
Reod
Addres.
Data
PCIot
t,.t
tpn
+25V
+5V _ _ _ _ _ _ _J
338
eHITACHI
.,.
".
ns
150
25
ns
ms
-
ns
ns
ps
ps
-
Procram
Verify
100
-
O.8V to 2.0V
20ns (10% to 90%)
Input; 1V and 1.SV
Output: O.SV and 2.0V
Procram
ps
ps
-
t\~,
-
-
+ tn •.
ps
ps
ps
-
-
• TEST CONDITION
Reod
-
40
70
-
• If the mode chances from program mode to prolram verify mode sequentiaUy (in the same address), I"" must be larger than
Test Condition
Input pulse levels:
Input rise and fall time:
Reference level for Measuring Timing:
-
ps
ps
-------------------------------------------------------------HN48016P
• ERASE OPERATION
eDC ERASING CHARACTERISTICS (Vcc-5V±5%. Vpp-25V±lV. Ta- 0 to +70'C)
Parameter
Symbol
Input Leakage Current
ILl
Vee Supply Current
Icc3
Vpp Supply Current
fpP3
Input Voltage
V,.
V,H
Test Condition
min.
-
V'N-5.25V
-
-
typo
max.
Unit
-
10
32
50
I'A
mA
10
20
mA
-0.1
-
0.8
V
2.0
-
-
V
eAC ERASING CHARACTERISTICS (Vcc=5V±5%. Vpp=25V±lV. Ta= 0 to +70'C)
Parameter
typo
max.
Unit
C S Setup Time
Symbol
tECSS
2
-
-
I'S
PG M to Output Delay
lEO
7
-
-
Erase Pulse \\'idth
I,..
200
210
min.
Test Condition
Erase Pulse Rise Time
fERT
190
5
Erase Pulse Fall Time
lEFT
5
Vpp Hold Time
IES
I£H
10
Erase Program Time t£P
IEP
10
Program Enase Time t p£
lPE
10
Vpp
Setup Time
10
I'S
ms
-
-
-
ns
ns
-
-
-
I'S
-
I'S
-
I's
-
I'S
e TEST CONDITION
Test Condition
Input pulse levels:
Input rise and fall time:
Reference level for Measuring Timing:
OBVto 2.0V
20ns (10% to 90%)
Input; 1 V and 1.BV
Output; O.BV and 2.0V
• POWER SUPPLY SEQUENCE PRECAUTIONS
To protect the written data, power supply to the
HN48016P should be turned on and off in the following order:
e Power On-Off Order and Input Level Limitation
for ~ and PGM Terminals
Table 1 shows the relationship between the order in
which power supply for the HN4801.6P should be
turned on and off and the input levels of the ~ and
PGM terminals.
(1) For the 5V Vpp and Vcc, there is no limitation
as to the order in which power is turned on and
off the state of the input terminals ~ and
PGM.
(2) When turning on and off power supply for the
25V Vpp, keep Vcc at between 4.5V and 7V,
and PGM at "Low."
(3) When turning on and off power supply for the
5V Vee while Vpp equals 25V ± 1V (this being
a rare case for the HN48016P), make sure to
keep PGM at "Low."
Fig. 1 shows the timing order in which power is
turned on and off.
eTable 1. Power On-Off Order for HN48016P
Power On-Off
Input Level
PGM
CS
VIL
VIL
VrL
V,.
V,.
VrH
VIL
V,.
5V- VPP" Vee
Possible
Possible
25V-Vpp
Possible only when
Vee-4.5-7V·'
impossible*·
Note 1. If Power for the 25V Vpp were turned on or off
while VCC = -O.3V to +4.5V, the data holding
characteristic would probablv deteriorate.
Note 2. If the 25V Vpp were operated to choose a "write"
or "erase" mode while PGM a "VIH," contents of
ROM would probably change.
eHITACHI
339
HN48016P-------------------------------------------------------------• Example of Standard Power Supply Sequence
The following is an example of standard power
supply sequence:
(I) Power On
(2)
Pow., Off
Turn on 5V Vpp, Vee( SWO
Fix PGM at "'Low" (SW3)
Fix PGM at ·Low" (SW3)
Turn off 25V-Vpp(SWZ)
Turn on 25V
Vpp{
5
SW2)
Turn off 5V- Vpp, Vee( SWO
SW3
SWI
5V-/
PGM
\lpp
VCC
SW2
25V-/
• Inter-mode Timing
The HN48016P has six operating modes, 5V Vpp readout, non-selected, 25V Vpp write, write check, write
inhibit, and erase. To protect the written data, keep the
terminal PGM at "Low" for a period of lOllS before and
after turning the terminal Vpp from 5V to 25V and
vice versa.
The following describes the inter-mode timing for a
system that uses the HN48016P.
• Readout ... Write ... Readout
Before turning the terminal Vpp to 25V, keep the
terminal PGM at "Low" for a period of 10jJs minimum
(as indicated by tvsl. After the terminal Vpp has been
turned to 25V, keep the terminal CS at "Low" for a
period of 10Ils minimum (as indicated by tpsl. Before
turning the terminal Vpp to 5V, keep the terminal CS at
"Low" for a period of lOllS minimum (as indicated by
tpHI. After the terminal Vpp has been turned to 5V,
keep the terminal PGM at "Low" for a period of lOllS
minimum (as indicated by tVHI.
Input level of the tlflllinal ~ ma, be either -Low·
or "Hip· Ivs=lr:s"'fKH=lv,,~IO.u8
Fig. 1. Power on-off timing sequence.
Fig. 2. "Readout-Wrlte-Readout" timing
• Readout ... Erase ... Readout
This, timing sequence is shown in Fig. 3. After turning
the terminal Vpp to 25V, keep the terminal PGM at
"Low" for a period of 10jJs minimum (as indicated by
tEsI. Keep the terminal PGM at "Low" for a period of
10jJs minimum (as indicated by tEH I before turning the
terminal Vpp to 5V, as well.
• Erase ... Write ... Erase
This timing sequence is shown in Fig. 4. Before turning
the terminal CS to "High (write model," keep the
terminal.
PGM at "Low" for a period of lOllS minimum (as
indicated by tEPI. Before turning from "write" to
"erase," keep the terminal CS at "Low" for a period of
lOlls minimum (as indicated by tpE I.
Fig. 3. "Readout-Erase-Readout" timing.
Add"..
Do,' eml
,Add.... V.UdX Add""r'"dX~' Can
Data
PGM
v"
340
$
HITACHI
Fig. 4. "Erase-Write-Erase" timing.
IIPOlAI HA
•
HITACHI
341
HM10414, HM10414-1-----256-word x 1-blt Fully Decoded Random Access Memory
The HM10414 is ECl 10K compatible, 256·word x l·bit, read write,
random access memory developed for high speed systems such as
scratch pad and control/buffer storages.
The fabrication process uses the Hitachi's low capacitance, oxide
isolation method with double metalization.
The HM10414 is encapsulated in cerdip-16pin package, compatible
with Fairchild's F10414.
• Fully compatible with 10K ECl level
• Address access time:
HM 10414: 10ns (max.)
HM10414·1: ans (max.)
• Write pulse width: 6ns (min.)
• Three chip select pins
• Output obtainable by wired.QR (open emitter)
(OG'\6)
• PIN ARRANGEMENT
• TRUTH TABLE
Input
WE
CS
Output
Mode
Din
L
L
Not Selected
Write "0"
anyone H
X
X
all
L
L
L
all
L
L
H
L
all
L
H
X
Dout"
Write "I"
Read
')( : Don't care
* : Read out non-inverted
• BLOCK DIAGRAM
(Top View)
Do..
'----"...-~
r--......J>--rr.
D..
• ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Supply Voltage
Input Voltage
V ..
Output Current
[aul
Storage Temperature
Storage Temperature
*
VEE
to Vee
Td,
T.,,(Bias)·
Rating
Unit
+0.5 to -7.0
V
+0.5 to VEE
-30
mA
-65 to +150
-55 to +125
'c
·c
V
Under Bias
342
eHITACHI
- - - - - - - - - - - - - - - - - - - - - - - - - - - HM10414, HM10414·1
• ELECTRICAL CHARACTERISTICS
.DC CHARACTERISTICS(V££--S.2V,RL -Son to -2.0V, Ta-O to +7S'C,air flow exceeding 2m/sec)
Item
-
Symbol
Test Condition
+2S'C
+7S'C
VON
Output Voltage
VIN- VIHA or VII."
O'C
VOL
VClH('
Output Threshold Voltage
Vt . . -
or
VINB
+7S'C
O'C
Input Voltage
Guaranteed Input Voltage
Input Current
Low for All Inputs
[,N
V,N- VIHA
III
CS
Other
o to
I
o to
V'N- VILa
It.;F
-1830
-980
-920
-
-1105
-1045
-1850
+7S'C
-1830
+7S'C
O'C
Test Pin 8
-
-1645
mV
-1630
-1605
-840
-810
-720
-1490
mV
-1475
-1450
220
170
-
-130
-180
mV
-
-
0.5
-50
Unit
-1650
-1625
-
-
+7S'C
-1665
-
-1870
+2S'C
-840
-810
-720
-
-1145
+7S'C
All Input and Output Open.
Supply Current
-1020
+2S'C
High for All Inputs
VIL
O'C
+2S'C
+2S'C
+7S'C
O·C
Guaranteed Input Voltage
-900
-1870
-1850
max IAI
-
-1000
-960
+2S'C
+7S'C
+7S'C
O·C
VI/A
Vm,c
V,N
typ
min 181
O'C
-140
p.A
mA
• AC CHARACTERISTICS
(V££--S.2V±S%. To-O to +75'C,air flow exceeding 2m/sec, see test circuit and waveforms)
1. READ MODE
Item
Symbol
Test Condition
min
Chip Select Access Time
tAr'1I
-
Chip Select Recovery Time
IRes
-
Address Access Time
tAA
-
HMI0414
typ
3
3
7
HMI0414-1
ma.
6
min
6
-
10
-
-
Unit
typ
ma.
3
3
6
6
ns
n.
6
8
ns
2. WRITE MODE
Item
Symbol
Write Pulse Width
t.
Data Setup Time
tWSD
Data Hold Time
tWHD
Address Setup Time
tWSA
Address Hold Time
Test Condition
tWSA
-205
min
typ
6
4
0
I
I
0
2
0
tWHA
2
Chip Select Setup Time
twscs
I
0
0
Chip Select Hold Time
tWHCS
1
0
Write Disable Time
I.,
Write Recovery Time
I ••
tw-6ns
max
Unit
ns
ns
-
ns
5
5
ns
ns
ns
n.
ns
ns
-
-
min
typ
ma.
Unit
-
1.5
1.5
2.5
2.5
ns
min
typ
max
Unit
-
3
5
5
8
3. RISE/FALL TIME
/tem
Output Rise Time
Output Fall Time
Symbol
Test Condition
I.
1/
ns
4. CAPACITANCE
Item
Input Capacitance
Output Capacitance
Symbol
Test Condition
C.
C..
•
HITACHI
pF
pF
343
HM10414,HM10414·1--------------------------------------------------.TEST CIRCUIT AND WAVEFORMS
2. INPUT PULSE
1. LOADING CONDITIONS
GND
-"'=11
-1.7V
HMI0414
~
20%
II
I,
1,=1,=2.0..1 typ
-2.0V
R,=SOlI
v..
CL =30pF{ includes iig and stray capacitance)
3. READ MODE
~-I"-'S--
Addre"~'-S_o%_ _ _ _ _ _ __
-./~_I"~
OOUI
OOUI
4. WRITE MODE
C-.S----SO""'~-----------------------I
*----------
~
!
:--so""'r*-----------------
-Ad-dr••-.- -....
,
!
:
-------r---:-~J/
Dm
/-~-----------
I ; 50%/1\-------------'*
-------+I---t"1- . . . :'---------'j:-;:;j '\"
------4---t"I--~'-~
L
WE
~I~~~
i
t"liA
_ I W.W
lJout
'M
-t -----
'---11 "'K--/50%
~I'S~' f-I'H~
SUPPLY CURRENT
SUPPLY VOLTAGE
va.
200
200
181)
180
!
!
140
I
--r-I-I
12<)
!
r--- r--
160
-
t--
!
140
.z:.
J20
..-
u
!
r- i
100
I
t"·H('.s~r_...;..-------
!
SUPPLY CURRENT
AMBIENT TEMPERATURE
u
I'H'~
-----
va.
1611
.
Ir------.-~---------
)(l()
r'=js'c
S 20
·
~)
-20
20
40
60
60
100
80
Ambient Temperature Ta laC)
344
-5.72
-5.20
Supply Vnltage
•
HITACHI
VEl (V)
- - - - - - - - - - - - - - - - - - - - - - - - - H M 1 0 4 1 4 . HM10414·1
ADDRESS ACCESS TIME
ADDRESS ACCESS TIME
va. AMBIENT TEMPERATURE
VI. SUPPLY VOLTAGE
10
0
9
I
8
I
....§
V
~; V
-
7
6
7
-~ f--
1-
~
5
~
l\IAI
5
I
Ta=2S'C
VI'E=-S.20V
4
20
20
40
"""'-
~
I
I
60
80
4
100
-5.72
Ambient Temperature Ta C'C)
-4.68
-5.20
Supply Voltage VEr (V)
CHIP SELECT ACCESS TIME
vs. AMBIENT TEMPERATURE
CHIP SELECT ACCESS TIME
vs. SUPPLY VOLTAGE
-
3
2
1
1
To=2Sl:
VEE=-S.20V
I
0
-20
20
40
j
80
60
"
100
]
- 5.72
- 5.20
- 4.68
Supply \·nlt&Re Vu'VJ
Ambient Temperature To (Oe)
WRITE PULSE WIDTH
vs. AMBIENT TEMPERATURE
WRITE PULSE WIDTH
VS. SUPPLY VOLTAGE
6
6
5
5
-f4
4
3
3
2
2
1
1
V£E
0
20
20
40
60
1
80
s.20V
rGj25'C
0
100
-5.72
Ambient TempE"rature Ta (t 1
5.20
4~8
Supply Voltage V'RF. (\'1
•
HITACHI
345
HM2110, HM2110-1
1 024-word x 1-bit Fully Decoded Random Access Memory
The HM2110 Series item is an ECl compatible, 1024·word x l·bit,
read/write, random access memory developed for application to
scratch pads, control and buffer memories, etc. which require high
speeds.
• It is compatible with 10K ECl logic.
• Chip select access time ............. 10ns (max.)
• Address access time ............... HM2110: 35ns (max.)
HM2110·': 25ns (max.)
• Power consumption , .....•........• 0.5mW/bit (typ)
• Output obtainable by Wired-OR (open emitter).
'DG -l6A'
• TRUTH TABLE
• PIN ARRANGEMENT
Input
Output
Mode
CS
WE
H
><
Din
x
L
• Not Selected
L
L
L
L
Write "0"
L
L
H
L
Write "I"
L
H
x
Dout-
Read
x : Irrelevant
• : Read out noninverted
• BLOCK DIAGRAM
...
A,
"
A,
A.
32X32
Memory
~~
~~
,,"
'Top V,t'w
• ABSOLUTE MAXMUM RATINGS
Item
Symbol
HM2110 Series
Unit
+0.5 to -7.0
V
Supply Voltage
VEE
Input Voltage
V..
+0.5 to V..
V
Output Current
lnl
-30
mA
Storage Temperature
T."
-65 to +150
'C
Storage Temperature
T$,.{Bias)*
-55 to +125
'C
to Vee
* Under Bias
346
•
HITACHI
---------------------------------------------------------HM2110,HM2110-1
• ELECTRICAL CHARACTERISTICS
e DC CHARACTERISTICS (VEE ~ -5.2V.
RL~500
Symbol
Item
to -2.0V. Ta~O to +75"C. air flow exceeding 2m/sec)
VON
VIN = V1HA or VILB
Output Voltage
VOL
VOHC
Output Threshold Voltage
VIN= VTHB
or
VILA
VOLe
Guaranteed Input Voltage
VIII
High for All Inputs
Input Voltage
Guaranteed Input Voltage
~a
Low for All Inputs
VII',
I'N
typ
maxlAl
-1000
-840
+25'C
-960
-
+75'C
-900
-
-720
O'C
-1870
-
-1665
+25'C
-1850
-
-1650
+75'C
-1830
-
-1625
O'C
-1020
-
-
+ 25'C
-980
-
-
+ 75'C
-920
-
I"
I V'N ~ Va,
Other
All Input and Output Open,
lEE
O~
Test Pin 8
mV
-
-
-
-1645
+25'C
-
-
-1630
+75'C
-
-
-1605
O'C
-1145
-
-840
+25'C
-1105
-
-810
+75'C
-1045
-
-720
O'C
-1870
-
-1490
+25'C
-1850
-
-1475
+ 75'C
-1830
-
-1450
-
-
220
0.5
-
170
-50
-
-
0 to +75'C
Unit
-810
O'C
0 to + 75'C
= VIHA
CS
I nput Current
Supply Current
min(BI
O'C
Test Condition
Ta<25'C
-150
--100
-
Ta",25'C
-125
-90
-
mV
mV
pA
mA
eAC CHARACTERISTICS
(VH~-5.2V
±5%. Ta~O to +75"C. air flow exceeding 2m/sec. see test circuit and waveforms)
1. READ MODE
Item
Symbol
HM2110
Test Condition
min
typ
HM2110-1
max
min
typ
max
Unit
Chip Select Access Time
lACS
-
7
10
-
7
10
ns
Chip Select Recovery Time
IRes
-
7
10
-
7
10
ns
Address Access Time
t"
-
20
35
-
15
25
ns
2. WRITE MODE
Item
Symbol
HM2110
Test Condition
min
HM2110-1
Unit
typ
max
min
typ
max
ns
25
Write Pulse Width
tw
Data Setup Time
tWSD
Data Hold Time
tWHD
Address Setup Time
iWSA
Address Hold Time
tWI/A
ns
Chip Select Setup Time
IWi;;cs
ns
Chip Select Hold Time
tWHCS
\-\'rite Disable Time
Write Recovery Time
tWSA
=8n5
25
ns
ns
ns
tw=25ns
ns
tW'
-_._--._--
i
tWR
eHITACHI
10
10
ns
10
10
ns
347
HM2110,HM2110-1-------------------------------------------------------3. RISE/FALL TIME
min
typ
msx
Unit
Output Rise Time
I.
-
5
ns
Output Fall Time
I,
-
5
-
min
typ
max
Unit
-
4
5
pF
7
8
pF
Symbol
Item
Test Condition
ns
4. CAPACITANCE
Symbol
Item
Input Capacitance
C.,
Output Capacitance
C."I
Test Condition
• TEST CIRCUIT AND WAVEFORMS
1. LOADING CONDITION
2. INPUT PULSE
-'' =11
GND
~
20%
-1.7V
16
II
I.
=" =2.5nl
t.
HM2110
typ
-2.0V
VEE
&=500
CL=30pF(includes probe and
jig capacitance)
3. READ MODE
Addr.ss~'4A~
~-'A(-S-"'"
V,HB
Dout
Dout
VlL
n.
~
~
"
u
Memory Cell
Array
~
<0
~
A,
Dout
A;
Dm
,~
0«
.
-<
...
....
.¢
0«
(Top View)
.;:
• ABSOLUTE MAXIMUM RATINGS (Ta~25'C)
Item
Symbol
Unit
Rating
Supply Voltage
VEE
Input Voltage
V ..
+0.5 to VEE
V
Output Current
[ .... I
-30
mA
Storage Temperature
Td,
-65 to +150
'c
Storage Temperature
T.,,(Bias)·
-55 to +125
'C
* Under Bias
to Vee
+0.5 to -7.0
$
V
HITACHI
363
HM10470,HM10470-1,HM10470F-----------------------------------------------
• TEST CIRCUIT AND WAVEFORMS
eDC CHARACTERISTICS (VEE=-S.2V, RL=SOO to -2.0V, Ta=O to +7S'C. air flow exceeding 2m/sec)
Item
Symbol
Test Condition
VOH
Output Voltage
VIN
=0.
VIHA
or
VOHe
VIN=VIHB
or
-840
-960
-
, -810
-900
-
-720
O'C
-1870
-1665
+25'C
+75'C
+ 25'C
-1850
+ 75'C
-1830
-
O'C
-1020
-
+ 25'C
-980
-
-
+ 75'C
-920
-
-
VILA
VOLe
O'C
-
+ 25'C
-
Guaranteed Input Voltage
High for All Inputs
Input Voltage
VlL
Ir.
Input Current
Supply Current
IlL
lEE
Guaranteed Input Voltage
Low for All Inputs
o to
Vlr.::- ¥INA
II
CS
Other
o to
VIN-VILS
+ 25'C
-1105
-
+ 75'C
-1045
-
-720
O'C
-1870
-
-1490
+2S'C
-1850
-1830
-
-1475
+ 75'C
To-O'C
All Input and Output Open,
Test Pin 9
-
-1145
+75'C
-1645
-810
-1605
-840
mV
-1450
-
-
220
0.5
-
170
-50
-
-
-200-
-160-200"
-
-145
-
-
mV
-1630
-280--
To-75'C
mV
-1625
O·C
+7S'C
Unit
-1650
-
+7S'C
Vr.
ma.(Al
-
-1000
VILS
VOL
Output Threshold Voltage
typ
min !B)
O'C
}fA
mA
* HM10470/F
* * HM10470·1
eAC CHARACTERISTICS(VEE=-S.2V ±S%. Ta=O to +7S'C. air flow exceeding 2m/sec)
Item
Symbol
Chip Select Access Time
lACS
Chip Select Recovery Time
hcs
Address Access Time
tAA
Test Condition
HM10470-1
HM10470/F
min
typ
max
-
-
10
10
15
25
-
Unit
typ
max
-
-
8
ns
-
-
8
ns
12
15
ns
min
2, WRITE MODE
Item
Symbol
Test Condition
HM10470-1
HM10470/F
Unit
min
typ
max
min
typ
max
25
-
-
ns
-
ns
ns
Write Pulse Width
tw
tWSD
2
-
-
15
Data Setup Time
Data Hold Time
tWHD
2
-
-
2
Address Setup Time
tWSA
3
tWH"
2
-
3
Address Hold Time
-
Chip Select Setup Time
twscs
2
-
-
2
-
Chip Select Hold Time
tWHCS
2
-
-
2
-
-
Write Disable Time
tws
-
-
10
-
-
8
ns
Write Recovery Time
two
-
-
10
-
-
8
ns
364
twsA=3ns
tW=tw min
•
HITACHI
2
2
ns
ns
ns
ns
HM10470, HM10470·1, HM10470F
3. RISE/FALL TIME
Symbol
Item
Output Ri.e Time
/,
Output Fall Time
//
Test Condition
min
typ
max
Unit
-
2
-
ns
2
-
ns J
min
typ
max
Unit
-
3
-
pF
4. CAPACITANCE
Item
Symbol
Input Capacitance
C.,
Output Capacitance
C'.I
Test Condition
5
pF
• TEST CIRCU1T AND WAVEFORMS
1. LOADING CONDITION
2. INPUT PULSE
-"'=t1
Test Circuit
Vcc(GND)
~
20%
I,
-1.7V
I.
DOUI
l.=,,=2.0nl typ
M.U.T.
-2.0V
R,=SOil
C,=3OpF(includ••
probe and H,
CApaC itlnee )
3. READ MODE
~... ~
~-,,,-,-00"
Oout
_
50%
4. WRITE MODE
cs
~~
-------------------------7
50%)~ - - - - - -
Addreu
________~--J
- - - - - - -..:. - - - - - (
~~-----------
---r-~~ V ___________~/r-------------Din
____""" __-+_...,i '- _________ -"
50%
1--,.,-
_____ .,v1-'"
'----...,.,/1--..., -
f---:::=~Ir.'s~'=::+=~-".
'lfwrs----.ror_ _ _ _ _ _ __
---------
1----rIl'5CS--_~
_to·,
•
50lt.
t---'••
HITACHI
365
HM10470,HM10470-1,HM10470F--------------------------------------------SUPPLY CURRENT vs.
SUPPLY VOLTAGE
SUPPLY CURRENT vs.
AMBIENT TEMPERATURE
200
200
!I
180
180
<
~
.
160
~
14 0
--
"-
u
l
>.
120
]
160
-= 14 0
r-- r--
~
~
1
'"
100
--
I
120
100
ra=r oc
VEE=-5.20V
0
20
40
I
I
60
80
80
100
-5.72
-4.68
-5.20
Supply Voltage VEE (V)
Ambient Temperature Ta ("C)
ADDRESS ACCESS TIME
vs. AMBIENT TEMPERATURE
ADDRESS ACCESS TIME
vs. SUPPLY VOLTAGE
35
35
30
30
5
25
0
5
l---
0
r-~
fl~ r-v&£=-
5
-20
20
40
60
-
~
~
20
.,
u
~
~
HMI0470/F_
5
1
Hloll 470-1
10
JOV
80
5.72
5020
2
10
0
8
8
6
6
HMI0470/F
HMI047 -I
~~10470/F
10470-1
4
2
2
VT=-5.20V
20
20
40
60
80
ra=j5'C
0
100
5.72
5.20
Supply Voltage VEE (V)
Ambient Temperature Ta. (t:)
366
4.68
CHIP SELECT ACCESS TIME
vs. SUPPLY VOLTAGE
12
0
~
Supply Voltage VEE (V)
CHIP SELECT ACCESS TIME
vs. AMBIENT TEMPERATURE
-
i-
Ta= 50C
5
100
Ambient Temperature Ta ("C)
4
----
•
HITACHI
4.68
-----------------------------------------------HM10470. HM10470-1. HM10470F
WRITE PULSE WIDTH
SUPPLY VOLTAGE
WRITE PULSE WIDTH VB.
AMBIENT TEMPERATURE
.!
5
35
30
30
25
5
HMIO'70/ F
VS.
-
HMIO'70/F
r5
5
-
0
HMI~?O-l
H 10470-1
0
V£E=-Sj20V
5
20
20
60
80
TO=rOC
100
Ambient Temperature To. ("C)
5
5.72
Supply Voltage
eHITACHI
'.68
5.20
VEE
(V)
367
HM10470-15
4096-word x 1-bit Fully Decoded Random Access Memory
The HM10470 is ECL 10K compatible, 4096-words x 1-bit, read/
,-------------,
write, random access memory developed for high speed systems
such as scratch pads and control/buffer storages.
The fabrication process uses the Hitachi's low capacitance, oxide
isolation method with double metalization.
The HM10470 is encapsulated in cerdip-18 pin package, compatible
with Fairchild's F10470.
•
•
•
•
•
•
•
FEATURES
4096-word x 1-bit organization
Fully compatible with 10K ECL level
Address access time: 15ns (max)
Write pulse width: 15ns (min)
Low power dissipation: 0.2 mW/bit
Output obtainable by wired-OR (open emitter)
tDG-IS)
• PIN ARRANGEMENT
• TRUTH TABLE
Input
Output
CS
WE
Din
H
X
X
L
Not Selected
Write "0"
L
L
L
L
L
L
H
L
L
H
X
DODt·
Notes)
Mode
Write "I"
Read
x: Irrelevant
* :Read Out
Nonivert
• BLOCK DIAGRAM
A.
AI
~,
(Top View)
..
..
64 x64
Memory Cell
~-g
A,
~~
A•
><
Array
•~5
.ABSOLUTE MAXIMUM RATINGS (Ta-25'C)
Item
Symbol
Rating
Unit
Supply Voltage
VEE
Input Voltage
V,.
+0.5 to VEE
Output Current
10.11
-30
Storage Temperature
T.t.
-65 to +150
Storage Temperature
T.,. (Bias)·
-55 to +125
* Under Bias
368
•
'-'--V
+0.5 to -7.0
to Vee
HITACHI
I-I
V
rnA
·c
·c
------------------------------------------------------------HM10470-1S
• ELECTRICAL CHARACTERISTICS
.DC CHARACTERISTICS (VEE=-5.2V, RL-50n to -2.0V, Ta=O to +75'C, air flow exceeding 2m/sec)
Item
Symbol
Test Condition
minlBl
VON
Output Voltage
VIN =- Y,HA or VILS
VOL
VOHe
Output Threshold Voltage
VIN-V'HB or VILA
¥oLe
V,N
Guaranteed Input Voltage
High for Ali Inputs
Input Voltage
V"
liN
Input Current
lEE
o to
VIN-V'HA
CS
I"
Supply Current
Guaranteed Input Voltage
Low for All Inputs
i V'N-V",
Other
All Input and Output Open,
o to
max(A)
-lOOO
-
-840
+25'C
-960
-900
-
-810
+ 75'C
O'C
-1870
-
-1665
+ 25'C
-1850
-1830
O'C
-1020
-
-1650
+ 75'C
+ 25'C
-980
+ 75'C
-920
O'C
-
+25'C
+ 75"C
-
-
-1645
-
-
-
-
-1605
-840
-1490
-1105
+ 75'C
-1045
O'C
-1870
-
+ 25'C
-1850
-
-1475
+ 75'C
-1830
-1450
-50
-
-200
-160
+75"C
Ta~O'C
0.5
-
mV
-1630
-1145
-
mV
-1625
O"C
+75"C
Unit
-720
+ 25'C
Ta~75'C
Test Pin 12
typ
O'C
-810
-720
mV
220
170
-
-145
pA
mA
.AC CHARACTERISTICS (VEE =-5.2V±5%, Ta=O to +75'C, air flow exceeding 2m/sec)
1. READ MODE
Item
min
typ
max
Unit
ns
8
ns
tAA
-
-
8
hes
-
15
ns
min
typ
max
Unit
15
-
ns
-
ns
-
ns
Symbol
Chip Select Access Time
tACS
Chip Select Recovery Time
Address Access Time
Test Condition
2. WRITE MODE
Item
Symbol
Test Condition
Write Pulse Width
tw
Data Setup Time
tWSD
2
Data Hold Time
tWHD
2
Address Setup Time
tWSA
Address Hold Time
tWHA
2
-
Chip Select Setup Time
twscs
2
-
-
ns
Chip Select Hold Time
tWHCS
2
-
ns
Write Disable Time
tws
-
8
ns
Write Recovery Time
tWR
-
-
8
ns
twsA-3ns
tw-15ns
•
3
HITACHI
n.
ns
369
HM10470-15-----------------------------------------------------------3. RISE/FALL TIME
min
typ
max
Unit
Output Rise Time
Item
Symbol
I,
Test Condition
-
2
na
Output Fall Time
II
-
2
-
min
typ
-
3
na
4. CAPACITANCE
Symbol
Item
Input Capacitance
Co,
Output Capacitance
Cn'
Test Condition
max
Unit
-
pF
5
pF
.TEST CIRCUIT AND WAVEFORMS
1. LOADING CONDITION
2. INPUT PULSE
Test Circuit
-'~=rr
Vcc(GND)
-1.1V
~
20%
..
"
Dout
M.U.T.
RL
T
",.
O.OIIlF
C~
RL=5OlI
CL=3OpF{includes
;t.
-2.0Y
probe and jig
capacitance)
3. READ MODE
~-~
~-.
A,
A.
A.
i.!
~
~
.~
128x 128
Memory Cell
1
Array
.!i
Dout
~
A.
'-===~~l
Din
(Top View)
.ABSOlUTE MAXIMUM RATINGS (Ta=2S'C)
Symbol
Item
Supply Voltage
Input Voltage
VEE
Output Current
1••,
Storage Temperature
Td.
T.,.(Bias)*
Storage Temperature
to Vee
v..
Rating
+0.5 to -7.0
+0.5 to VEE
-30
Unit
V
V
mA
-65 to +150
·c
-55 to +125
·C
* Under Bias
•
HITACHI
379
HM1~,HM10480F-------------------------------------------------------
• ELECTRICAL CHARACTERISTICS
eDC CHARACTERISTICS(VEE=-5.2V, RL-50Cl to -2.0V, Ta-O to +75"C, air flow exceeding 2m/sec}
Item
Symbol
Vo.
V,N - V,SA or V,U
Output Voltage
VOL
VORe
Output Threshold Voltage
VIN - V,HB or VILA
Guaranteed Input Voltage
High for All Inputs
Input Voltage
V'L
II.
Input Current
Supply Current
Guaranteed Input Voltage
Low for All Inputs
o to
V'N-V'HA
II V'N-VILJ
CS
I'L
I ..
typ
max (A)
-1000
-
-840
+2S'C
-960
-900
O·C
-1870
-
-810
+7S'C
+2S'C
-1850
+7S'C
-1830
.-
O·C
-1020
-
-
+2S'C
-980
-
+7S'C
-920
-
Others
o to
All Input and Output Open,
Test Pin 10
-162S
-114S
+2S'C
-1105
-
+7S'C
-104S
-
-720
O·C
-1870
-
-1490
+2S'C
-1850
+7S'C
-1830
-
-1450
-
-
220
O.S
-
170
+2S'C
-
+7S'C
-
+7S'C
+7S'C
Ta-O'C
-SO
-170
-
Ta-75'C
mV
-1650
O·C
,-
Unit
-720
-1665
-
O·C
VOLe
V,.
min (B)
O·C
Test Condition
-1645
mV
-1630
-1605
-840
-810
mV
-147S
-
-140
-130
pA
mA
eAC CHARACTERISTICS (VEE=-5.2V ±5%. Ta-O to +75"C, air flow exceeding 2m/sec}
1. READ MODE
min
typ
max
Unit
Chip Select Access Time
lACS
2
-
10
ns
Chip Select Recovery Time
hes
2
-
10
ns
Address Access Time
I ..
3
IS
25
ns
min
typ
max
Unit
25
-
-
ns
-
-
na
Item
Symbol
Test Condition
2. WRITE MODE
Item
Symbol
Test Conditi'1n
Write Pulse Width
Iw
Data Setup Time
'WSD
5
Data Hold Time
tWHD
5
Address Setup Time
twSA
twsA-5ns
1.-25ns
5
Address Hold Time
IWHA
5
Chip Select Setup Time
twscs
5
Chip Select Hold Time
tWHCS
Write Disable Time
Iw.
Write Recovery Time
Iw.
380
5
-
•
HITACHI
-
-
ns
ns
ns
ns
5
ns
10
ns
10
ns
-------------------------------------------------------HM10480,HM10480F
3. RISE/FALL TIME
min
typ
max
Unit
Output Rise Time
I,
-
2
-
ns
Output Fall Time
1/
-
2
-
ns
min
typ
-
4
Test Condition
Symbol
Item
4. CAPACITANCE
Test Condition
Symbol
Item
Input Capacitance
C ••
Output Capacitance
CO"'
max
-
7
Unit
pF
pF
• TEST CIRCUIT AND WAVEFORMS
2. INPUT PULSE
1. LOADING CONDITION
Test Ci rcuit
Vcc(GND)
20%
Dout
M.U.T.
O.OI.uF
;J;.
-2.0V
VEE
RL=5Oll
CL=3OpF(includes
probe and jig
capacitance)
3. READ MODE
Address
,,,
DOUI
4. WRITE MODE
50%
...
---Din
50~
\.
50~v'
50%\>/
/1\.
'/'I\.
----
-,
50%'~
~---50%
'J \
~-------------~~
llt'SD
50%
, .. scs
50%
II
..
L}%
,
•
HITACHI
----
firMA
,.
t!rSA
--Do. t
\
/
------
I
HrHCS
..
,
50>1
381
HM100415,HM100415CC
1 024-word x 1-bit Fully Decoded Random Access Memory
The HM100415 is a 1024-word x 1-bit, read/write random access
memory developed for application to scratch pads, control and
buffer storages which require very high speeds.
The HM100415 is compatible with the HD100K families and
includes on·chip voltege and temperature compensation for improved noise margin. This memory is encapsulated in cerdip-16pin
package .
•
•
•
•
•
•
•
•
FEATURES
level .•....•........•.•....•.•.. 100K ECl Compatible
Organization .........•.....•.•...... 1024-word by 1-bit
Address Access Time .....•.••.....•.••...... 10ns (max)
Chip Select Access Time .............•..••••.. 5ns (max.)
Power Consumption .••..••..••......•.•• O.6mW/bit (typ)
Output Obtainable by Wired-OR (open emitter)
Compatible with Fairchild F100415.
• TRUTH TABLE
Inp~t
WE
CS
Din
Output
Mode
H
X
X
L
Not Selected
L
L
L
L
Write "0"
L
L
H
L
Write "I
L
H
X
Dout*
HM100415
(00-16A)
HM100415CC
•
II
(CC-24)
Read
Note.) X : Irrelevant
.PIN ARRANGEMENT
eHM100415
• : Read Out Nonin\'ert
• BLOCK DIAGRAM
32X32
(Top View)
• ABSOLUTE MAXIMUM RATINGS (Ta-2S'C)
Item
eHM100415CC
Symbol
Rating
Supply Volta,"
V.. to Vee
+0.5 to -1.0
Input Voltage
V,.
+0.5 to V..
V
Output Current
I •••
-30
mA
Storage Temperature
T'I,
-65 to +150
'C
Storage Temperature
T.,,(Bias)*
-55 to +125
'C
Unit
V
• Under Bi ••
382
•
HITACHI
------------------------------------------------HM100415,HM100415CC
• ELECTRICAL CHARACTERISTICS
.DC CHARACTERISTICS(Vu--4.5V, R.-SOO to -2.0V. To-O to +8S'C, air flow exceeding 2m/sec}
Item
Output Volt.,e
Symbol
VON
VOL
VORe
Output Threshold Volta.e
Vot.c
Input Volt.,.
Input Current
Supply Current
Telt Condition
V,.- V,NA
V,. - V'N.
or VIL'
or V,LA
min (B)
typ
max (A)
Unit
-1025
-955
-880
mV
-1810
-1715
-1620
mV
-1035
-
-
-
-
-1610
mV
mV
mV
V,.
Guaranteed Input Vol tap
-1165
-
-880
V,£
High/Low for All Inputs
-1810
-
-1475
mV
11.
V,.-V'NA
-
220
JAA
1,£
VIII-V",.
I CS
I Oth.rs
0.5
-
170
-50
1..
All Inputs and Outputs Open
-200
-150
-
JAA
-
IlIA
typ
max
Unit
3
5
n.
3
5
ns
7
10
ns
min
typ
max
Unit
6
4
-
ns
.AC CHARACTERISTICS(~·u--4.5V ±5%, To-O to +8S'C, air flow exceeding 2m/sec}
1. READ MODE
Item
Symbol
Chip Select Acce•• Time
-,.cs
Chip Select Recovery Time
hes
Addreis Access Time
I ..
Test Condition
min
-
2. WRITE MODE
Item
Symbol
Test Condition
'wSA-2n.
Write PuI.e Width
Iw
Data Setup Time
'WSD
2
0
-
ns
Data Hold Time
'WHD
2
0
-
ns
Addre.s Setup Time
'WSA
2
0
-
ns
Address \fold Time
'''HA
2
0
-
ns
Chip Select Setup Time
'wscs
2
0
Chip Select Hold Time
'WHel
2
0
-
n.
I,,-6na
ns
Write Disable Time
IWI
-
3
5
ns
Write Recovery Time
Iw.
-
3
5
ns
min
typ
max
Unit
2
-
ns
2
-
ns
3. RISE/FALL TIME
Item
Output Rise Time
Output
~'all
Time
Symbol
Test Condition
-
I.
1/
4. CAPACITANCE
min
typ
max·
Unit
Input Capacitance
C/o
-
3
-
pF
Output Capacitanc.
CM'
-
5
-
pF
Item
Symbol
Test Condition
•
HITACHI
383
HM100415.HM100415CC--------------------------------------~-------
.TEST CIRCUIT AND WAVEFORMS
2. INPUT PULSE
1. LOADING CONDITION
-"'=6.
Tilt Clrcuit
Vcc(GND)
-1.7V
2091.
•
Dout
1/
It
M.U.T.
-MV
.~
-.,-Z.On. '"
1I,-5CIQ
C,-SOpFO••lucles
probe ancI ill
cr.paoll.... )
3. READ MODE
~N" ~-"::=:j-r-
~-",--
.k--~1i..1
Do••
Do..
_ _ _ _ _ _~
4. WRITE MODE
~s
~""
IO")~--------------------------
50"')(. ----- ------- -- ----~(
;.------ ~-----:;:- / ------ _____~/,...-
'--+-----------
____+-_-+_JI '- - - ____ - - - - I '--+--r-----r-'"
,-----r--+--------------t
Ir--...._
50"'\
1"""... _1\
_ _ _ _ _ _ _ __ -::--'..
Do••
38.4
...cs----;:=!...-______
--------- SO"
1 - - -.......,---1
•
HITACHI
HM100422,HM100422F
HM100422CC-------256-word x 4-bit Fully Decoded Random Access Memory
The HMtOO422 is eCl tOOK compatible, 256-word x 4·bit, read
write, random access memory developed for high speed system such
as scratch pads and control/buffer storages.
Four active low Block Select lines are provided to select each block
independently.
The fabrication process is the Hitachi's low capacitance, oxide
isolation method with double metalization.
The HMt00422 is encapsulated in cerdip-24pin package, or 24pin
flat package compatible with Fairchild's FtOO422•
•
•
•
•
•
•
•
FEATURES
256-word x 4·bit organization
Fully compatible with tOOK ECl level
Address access time: tOns (max.)
Minimum write pulse width: 6ns (min.)
low power dissipation: O.SmW/bit
Output obtainable by wired·OR (open emitter)
HMlOO4Z2CC
• TRUTH TABLE
Output
Mode
as
WE
Din
H
X
X
L
Not Selected
L
L
L
L
Write "0"
L
L
H
L
Write "I"
L
H
X
Dout·
X :
*:
•
(cc-:.)
Input
Notes)
(DG·UA)
HMlOO422F
• PIN ARRANGEMENT
eHM100422
Read
Irrelevant
Read Out Noninvert
A,
A,
• BLOCK DIAGRAM
eHM100422F
MemorY, Cell Array
256 WordsX4 Bits
(Top View)
Block 2
Block 3
Block 4
eHM100422CC
"'_'hJ-'"
I
~
.
'
, '"
4 DI,
DUo
V«
Yrr.
DOt
as.
(T... \',ewl
•
HITACHI
385
HM100422,HM100422F,HM100422CC--------------------
• ABSOLUTE MAXIMUM RATINGS (To-2S'C)
Symbol
Rating
Supply Voltage
Vn to Vee
+0.5 to -7.0
Input Voltage
V"
Output Current
Item
Unit
V
+0.5 to V..
V
1••,
-30
mA
Storage Temperature
T•••
-65 to +150
·C
Storage Temperature
T..,(Bia.)·
-55 to +125
·C
• Under Bias
• ELECTRICAL CHARACTERISTICS
e DC CHARACTERISTICS (VEE - -4.SV. RL-SOO to -2.0V. To-O to +8S'C, air flow exceeding 2m/sec)
Item
Output Voltage
Output Threshold Voltage
min(B)
typ
max (A)
Unit
-1025
-955
-880
mV
VOl.
-1810
-1715
-1620
mV
VONe
-1035
Symbol
VON
Test Condition
V•• - V,NA or VILB
VIII -
V,NB
or
Vi LA
-
-1610
mV
-1165
-
-880
mV
-1810
-
-1475
mV
-
-
220
/lA
0.5
-
170
-
VOLe
Input Voltage
VIN
V"
Guaranteed Input Voltage
High/Low for All Inputs
I'N
V.• -V'NA
mV
I"
V,"-VILB
I BS
I Others
-50
-
-
/lA
I.E
All Inputs and Outputs Open
-200
-165
-
mA
Input Current
Supply Current
-
eAC CHARACTERISTICS(VEE--4.SV ±S%, To-O to +8S·C. air flow exceeding 2m/sec)
1. READ MODE
Item
min
typ
msx
Unit
-
5
ns
tus
-
-
5
ns
I"
-
7
10
ns
min
typ
max
Unit
6
4.5
Symbol
Block Select Acces. Time
tABS
Block Select Recovery Time
Address Access Time
Test Condition
2. WRITE MODE
Item
Symbol
Test Condition
\twu-2ns
-
Write Pulse Width
Iw
Data Setup Time
'W8D
2
0
Data Hold Time
'WHD
2
0
Address Setup Time
twSA
2
0
Address Hold Time
tWHA
2
0
B lock Select Setup Time
tWSBS
2
0
-
Block Select Hold Time
tWHBS
2
0
-
ns
Write Disable Time
Iws
-
4
5
ns
Write Recovery Time
twl
-
4.5
9
ns
Iw-6ns
ns
ns
ns
ns
ns
ns
3. RISE/FALL TIME
min
typ
msx
Unit
'Output Rise Time
Item
Symbol
I.
-
2
-
ns
Output Fall Time
1/
-
2
-
ns
min
typ
Test Condition
4. CAPACITANCE
Item
Symbol
Input Capacitance
C..
Output Capscitance
COlli
386
Test Condition
•
HITACHI
msx
Unit
4
-
pF
7
-
pF
-'---------------------HM100422,HM100422F,HM100422CC
.TEST CIRCUIT AND WAVEFORMS
1. LOADING CONDITION
2. INPUT PULSE
Te.t Circuit
Vcc(GND)
00 ..
M.U.T.
-z.OV
&=5011
c,.-3OpF( includes
probe and j i,
capac itallce)
3. READ MODE
8S~
~t"'''$~
:
o.lUl
-----"i,
~dr~
I
I
1110%
I
~
x. ____
I ~---------------I----IAA--1
~
~.,
4. WRITE MODE
Addreu
I)in
'---
•
HITACHI
387
HM100470,HM100470-15--4096-word x 1-blt Fully Decoded Random Access Memory
The HM100470 is a 4096-words x l·bit, read/write, random access
memory developed for high speed systems such as scratch pads and
control buff.r storages.
The fabrication process is the Hitachi's low capacitance, oxide
isolation method with double metalization.
The HM100470 is compatible with the HD100K ECl families and
includes on-chip voltage and temperature compensation for im·
proved noise margin. This device is encapsulated in cerdip·l8pin
package, compatible with Feirchild's Fl00470.
•
•
•
•
•
•
FEATURES
4096-word x l·bit organization
Full compatible with lOOK ECl level
Address access time:
HM100470
25ns(max)
HM100470·15 15ns(max)
Write puIs. width:
HM100470
25ns (min)
HM100470·15 15ns (min)
• Output obtainable by wired·OR (open emitter)
• TRUTH TABLE
Input
WE
CS
Din
Output
(OG·IS)
• PIN ARRANGEMENT
Mode
H
X
X
L
Not Selected
L
L
L
L
Write "'0"
L
L
H
L
L
H
X
Dout'
Write "'t"
Read
Notes) x : Irrel • .,aat
• : Read Out Nonivert
(Top View)
• BLOCK DIAGRAM
.....
.~,
A~
.~,
..
i!-!
Q
~.!l
1!
...
64x6~
.~
"
MemorY' Cell
Array
~
."AI
.ABSOLUTE MAXIMUM RATINGS(Ta=25'C)
Symbol
Rating
Supply Voltage
V.. to Vee
+0.5 to -7.0
Input Voltage
V••
+0.5 to V..
V
Output Current
In'
-30
mA
Stora,e Temperature
T.I.
-65 to +150
'C
Storale Temperature
T... (Bias)'
-55 to +125
·c
Item
Unit
V
• Under Bi.s
388
.HITACfoI.
-------------------------HM100470'HM100470-15
• ELECTRICAL CHARACTERISTICS
.DC
CHAR~CTERISTICS(V£B--4.5V,
It.1II
Output Volta,.
RL-son to -2.0V,
Va.
Va.
VONe
Output Thr.lhold Voltage
To-O to +8S'C, air flow exceeding 2m/sec}
Telt Condition
SYlllbol
V,. - V'HA or VII..
lIIin(8)
t)'p
max (A)
Unit
-1025
-955
-880
IIIV
-1810
-1715
-1620
mV
-
mV
-1610
mV
-880
VI.-VIIII or VUA
mV
Guaranteed Input Voltage
-1165
-
High/Low for All Input.
-1810
-
-
-
VOloC
Input Volta..
Input Current
Supply Current
V,.
V,.
1,.
Vl.-VIIIA
I,.
I CS
I Others
-50
-
All Input. and Outputa Open
-200
-165
V,.-V'U
1..
-
-1035
0.5
-1475
mV
220
JoIA
110
-
JoIA
mA
.AC CHARACTERISTICS(Vu--4.SV ±S%. To-O to +8S·C. air flow exceeding 2m/sec}
1. READ MODE
Item
Symbol
Chip Select Acce•• Time
tACS
Chip Select Recovery Time
hcs
Address Access Time
I ••
HM100470
HM100470-15
Teat Condi tion
min
t)'p
-
-
-
-
-
Unit
max
min
typ
max
8
-
-
10
ns
10
ns
25
ns
-
8
15
min
-
-
2. WRITE MODE
Item
Symbol
HMl00470-15
HMI00470
Te.t Condition
t wSA-3ns
min
typ
max
15
-
-
Write Puis. Width
Iw
Data Setup Time
'WID
2
Data Hold Time
tWHD
2
Address Setup Time
twSA
Address Hold Time
tWHA
Chip Select Setup Time
twscs
2
Chip Select Hold Time
'WHca
2
Write Disable Time
IWI
-
Write Recovery Time
I w.
tw-twmin
-
3
2
-
-
-
-
Unit
typ
max
-
-
25
-
2
-
2
3
-
2
2
-
2
-
8
8
-
-
ns
ns
ns
-
ns
-
ns
-
ns
-
ns
10
ns
10
ns
3. RISE/FALL TIME
min
typ
max
Unit
Output Rise Time
I,
-.
2
ns
Output Fall Time
1/
-
2
-
min
typ
max
Unit
-
3
-
pF
-
5
-
pF
Item
Test Condition
Symbol
ns
4. CAPACITANCE
Item
'Symbol
Input Capacitance
C"
Output Capacitance
e ..
Test Condition
1
•
HITACHI
389
HMt00470,HM100470·1S-----------------------
• TEST CIRCUIT AND WAVEFORMS
2. INPUT PULSE
1. LOADING CONDITION
T ••1 Circuli
~=t1
Vcc(GNO)
-1.7V
I.
OOUI
M.U.T.
-2.0V
RL=5OII
CL=3OpF(jnclud••
probe and jig
capacitance)
3. READ MODE
4. WRITE MODE
50%
Address
~
------------------
Din
Do_.
390
•
HITACHI
~
I,
HM100474,HM100474-16
HM100474F,HM100474F-16
1024-wordX4-blt Fully Decoded Random Access Memory
The HM100474 is a 1024-words x 4-blt, read/write, random access
memory developed for high speed systems such as scratch pads and
cQntrol/buffer storages.
The fabrication process is the Hitachi's low capacitance, oxide
isolation method with double metalization.
The HM100474 is compatible with the HD100K ECl families and
includes on-chip voltage and temperature compensation for improved noise margin. This device is encapsulated in cerdip-24-pin and
flat 24pin package, compatible with Fairchild's Fl00474.
HM100414. HM100474-15
(DG-24A)
• FEATURES
• 1024-word x 4-bit organization
• Fully compatible with lOOK ECl ievel
• Address access time:
HM100474/F 25ns(max)
HM100474/F-15 15ns(max)
• Write pulse width:
HM100474/F 25ns(min)
HM100474/F-1516ns(min)
• Output obtainble by wired-OR (open emitter)
HM100474F. HM100474F-15
• TRUTH TABLE
(FG-24)
Input
Din
Output
Mode
• PlN ARRANGEMENT
CS
WE
H
X
X
L
Not Selected
L
Write "0"
Write "1"
L
L
L
L
H
L
L
H
x
Dout'
L
eHM100474,HM100474-15
Read
Notes) x : Irrelevant
• : Read Out NOhlvert
• BLOCK DIAGRAM
A,
Block 4
As
eHM100474F, HM100474F-15
A,
As
A1
Vee
AI
NC
A,
.ABSOlUTE MAXIMUM RATINGS (Ta=25'C)
Item
Symbol
Supply Voltage
VEE
to Vee
Rating
A,
Unit
+0.5 to -7.0
V
VII
V,"
I ...,
+0.5 to VEE
V
Vb
-30
mA
Vb
Storage Temperature
T",
-65 to +150
'C
VI,
Storage Temperat!Jre
T... (Bias)'
-55 to +125
'C
Input Voltage
Output Current
,
* Under Bias
LlOI
•
HITACHI
~O,
Vee
VCCA
(Top View)
00,
391
HM100474,HM100474-15,HM100474F,HM100474F-15------------• ELECTRICAL CHARACTERISTICS
.DC CHARACTERISTICS(VEE--4.SV. RL-SOO to -2.0V. Ta-O to +SS"C. air flow exceeding 2m/see)
Item
typ
max (A)
Unit
-1025
-955
-880
mV
VOL
-1810
--1715
-1620
mV
YONe
-1035
-
-
mV
-
-1610
mV
-880
mV
Symbol
VOH
Output Voltage
min(B)
Test Condition
V,II - V,NA or VILS
VII- V,RS or V tLA
Output Threshold Voltage
-
VOl.e
-1475
mV
-
-
220
pA
0.5
-
170
-SO
-
-
Guaranteed Input Voltage
-1165
VIL
High/Low for All Inputs
-1810
IIH
VIII-V'RA
IlL
Vlla-V,LS
I Others
I ..
All Inputs and Outputs Open
-200
Input Voltage
I CS
Input Current
Supply Current
-
V,H
-
-165
pA
mA
.AC CHARACTERISTICS (VEE=-4.SV ±S%. Ta=O to +SS"C. air flow exceeding 2m/sec)
1. READ MODE
Item
Symbol
HMI00474/F-15
HMl00474/F
Test Condition
Unit
min
typ
max
min
typ
8
-
-
10
ns
-
ns
15
-
10
15
25
ns
typ
max
min
typ
-
-
25
15
2
-
2
-
-
3
-
-
-
2
-
-
ns
~
2
-
-
2
-
ns
8
-
10
ns
-
8
-
:...
10
ns
Chip Select Access Time
tACS
-
-
Chip Select Recovery Time
t Res
-
Address Access Time
I ..
-
-
8
max
2. WRITE MODE
Item
Symbol
HMI00474/F-15
Test Condition
min
Write Pulse Width
Data
S~tup
Time
Iw
twu-3ns
15
tWSD
2
Data Hold Time
tWHD
2
Address Setup Time
tWSA
Address Hold Time
tWHA
2
Chip Select Setup Time
'W8CS
2
Chip Select Hold Time
tWHCS
2
Write Disable Time
Iws
-
Write Recovery Time
Iw.
tw==twmin
3
-
HMI00474/F
-
Unit
max
ns
ns
ns
ns
ns
3. RISE/FALL TIME
Item
Symbol
Output Rise Time
I.
Output Fan Time
1/
Test Condition
min
typ
-
2
-
ns
2
-
ns
min
typ
max
Unit
"
-
pF
-
pF
max
Unit
4. CAPACITANCE
Item
Symbol
Test Condition
Input Capacitance
C ••
-
Output Capacitince
COlli
-
392
_HITACHI
7
HM100474,HM100474-15,HM100474F,HM100474F-15------------• TEST CIRCUIT AND 'WAVEFORMS
1. LOADING
2. INPUT PULSE
CONDITIO~
Telt Circuit
Vcc(GND)
M.U.T.
1
RL
20%
,I ,
I
I
..........
e.
·1.7V
Doul
I
I
CL
l/L=5Oll
CL=3OpF(include.
-2.0Y·
probe and jig
capac i lance)
READ MODE
,.
'/
4. WRITE MODE
50% \.
...
----
5O~
5O~K
----
500/
/'\.
-......
Din
ro----
50~~~ _____________ ~:}
----
....
,-
--00. t
------
'.$A
-
----,wses
-I"
"'SD \
50%
,.
50% It
/
l)%
...
_HITACHI
ta'NA
e,,,,(s
...
50/{
393
HM100474,HM100474-15,HM100474F,HM100474F-15------------SUPPLY CURRENT va.
AMBIENT TEMPERATURE
SUPPLY CURRENT
SUPPLY VOLTAGE
200
200
180
<'
~
va.
"'~
Ii0
180
~
"""" ~
0
~
1
16 0
!
14 0
-
-
u
1
~
0
120
100
100
r.=25'C
VIB=-j.50V
80
-20
20
80
60
40
80
100
4.95
Ambient Temperature T4 ("C)
·
.!
4.50
4.05
Supply Voltage Vu (V)
APDRESS ACCESS TIME
APORESS ACe'IS TIMIE
va. AMlIENf TEMPERATURE
VB.
30
0
5
5
20
0
5
5
SUPPLY VOLTAGE
-
~
;::
=
~
I
~
0
0
r.=25'C
VE.rj-4.50V .
5
5
0
-20
20
40
60
80
0
100
-4,95
Ambient Temperature Ta (OC)
CHIP SELECT ACCESS TIME
vs. AMBIENT TEMPERATURE
:!
2
10
0
8
8
·
"'·
4
u
2
----
.-"
V
<"
6
4
Vu=-4.50V
~
4.05
CHIP SELECT ACCESS TIME
vs. SUPPLY VOLTAGE
.2
6
-4.50
Supply Voltage Vn (V)
r.=25'C
~
~ 20
2
20
40
60
80
0
100
394
4.95
4.50
Supply Voltage VEE (V)
Ambient Temperature Ta ("C)
•
HITACHI
4.05
- - - - - - - - - - - - - H M 1 00474,HM1 00474·15,HM1 00474F,HM1 00474F·15
WRITE PULSE WIDTH vs.
AMBIENT TEMPEI'IATUI'IE
WRITE PULSE WIDTH
SUPPLY VOLTAGE
0
30
5
5
0
!:
~
i
15
t
d::
.~
-
20
I---
_I-
5
10
0
~
~ =25'C
VI£-=- .sOV
5
0
VB.
5
20
20
40
60
80
0
100
-4095
4.50
-4.05
Supply Volta,e VEE (V)
Ambient Temperature Ta ("C)
•
HITACHI
395
HM100480, HM100480P
16,384-wordsx1-bit Fully Decoded Random Access Memory
The HM100480 is ECl 100K compatible, 16,384-words x 1-bit,
read/write random access memory developed for high speed
systems such as scratch pads and control/buffer storages.
The fabrication process uses the Hitachi's low capacitance, oxide
isolation method with double metalization.
The HM100480 is encapsulated in cerdip-20 pin and flat-20 pin
pac~age, compatible with Fairchild's 100480 .
HMl00480
• FEATURES
•
•
•
•
•
•
16,384-words x 1-bit organization
Fully compatible with 100K ECl level
Address access time:
25ns (max)
Write pulse width:
25ns (min)
Low power dissipation: 0.05mW/bit
Output obtainable by wired-OR (open emitter)
(00-20)
HMl00480F
.TRUTH TABLE
Input
CS
WE
Output
Din
Mode
H
X
X
L
Not Selected
L
L
L
L
Write '0'
L
L
H
L
L
H
X
Dout·
(FG-20)
Write -1-
.PIN ARRANGEMENT
Read
Notes) x: irrelevant
• : Read Out Noninvert
.BlOCK DIAGRAM
,I,
AI
AI
A.
A.
.~
.s
128X 128
Memor1 Cell
l
Dw,
A.
A.
L'::==";('I Din
.ABSOLUTE MAXIMUM RATINGS (Ta-2S'C)
Symbol
Rati.,
Input Voltage
Output Current
Storage Temperature
V•• to Vee
Vi,
1",
T.I.
Storage tedl~r'ture
T..,(Bias)"
+0.5 to -1.0
+0.5 to V..
-30
-65 to +150
-55 to +125
Item
Supply Voltage
Unit
V
V
IlIA
'C
'C
• Under Bias
396
• HITACHI
(Top View)
----------------------------------------------------HM100480,HM100480F
.ABSOLUTE MAXIMUM RATINGS (Ta-25'C)
Symbol
Rating
Unit
Supply Voltage
Vu to Vee
+0.5 to -1.0
V
Input Voltage
Vi.
+0.5 to V..
V
Output Current
1",
-30
mA
Storage Temperature
T. ,•
-65 to +150
"C
Storage Temperature
T... (Bias)·
-55 to +125
·C
Item
• Under Bias
.ELECTRICAL CHARACTERISTICS
.DC CHARACTERISTICS(Vu--4.SV. RL=SOO to -2.0V, Ta-O to +8S·C. air flow exceeding 2m/sec)
Item
Symbol
Test Condition
VON
Output Voltage
VOL
Vi .. - V,NA or VILB
VoNe
Vjll - V,NB or
Output Threshold Voltage
min(B)
typ
max(A)
Unit
-1025
-955
-880
mV
-1810
-1715
-1620
mV
-1035
-
-1610
mV
VILA
-
VOLe
mV
V,.
Guaranteed Input Voltage
-1165
-
-880
mV
V'L
High/Low for All Input
-1810
-
-1415
mV
I,.
Vill-VINA
-
220
pA
Input Voltage
Input Current
Supply Current
-
-
I CS
I Others
IlL
ViII"'" VILB
I ..
All Inputs and Outputs Open
0.5
-50
-200
110
-165
pA
-
mA
.AC CHARACTERISTICS (VEE =-4.SV±S%, Ta=O to +8S·C. air flow exceeding 2m/sec)
1. READ MODE
min
typ
max
Unit
Chip Select Access Time
tACS
2
-
10
ns
Chip Select Recovery Time
tRCS
2
-
10
ns
Address Access Time
tAA
3
-
25
ns
min
typ
max
. Unit
25
-
-
ns
-
ns
Item
Symbol
Test Condition
2. WRITE MODE
Item
Symbol
Test Condition
twsA-5ns
Write Pulse Width
tw
Data Setup Time
tWSD
Data Hold Time
tWHD
Address Setup Time
tWSA
Address Hold Time
tWHA
5
Chip Select Setup Time
twscs
5
Chip Select Hold Time
tWlfes
Write Disable Time
Iws
Write Recovery Time
twa
5
5
tw=twmin
•
5
-
HITACHI
-
-
-
-
ns
ns
ns
ns
5
.s
10
.s
10
ns
397
HM100480,HM100480F-----------------------------------------------3. RISE/FALL TIME
Item
min
typ
max
Unit
Out",,! Riae Time
I.
-
2
na
Output Fall Time
1/
-
2
-
min
typ
max
Unit
3
-
pF
5
-'
pF
Symbol
Teat Condition
ns
4. CAPACITANCE
Item
Symbol
Teat Condition
Input Capacitance
C"
-
Output Capacitance
C...
-
• TEST CIRCUIT AND WAVEFORMS
1. LOADING CONDITION
2. INPUT PULSE
' '=i1
Teat Circuit
Vcc(CND)
-1.1V
~
20%
,.
"
Dout
M.U.T.
RL=5OIl
CL=3OpF(includes
probe and jig
capacitance)
-2.0V
3. READ MODE
~-,.c-.-Do..
4. WRITE MODE
a
Add....
Din
oo~
-------------------------7
50~1 - - - - - - - - - - - - ~- ----J(
'---+------
~,...-'------------
-----, I
50%/
----.--------
-----+---I--J '-_ - __ - - - __ -I
t-....
so9I,
_ _ _ _ _ .,
1-.... -
- ,...hi
_ _ _ f.---fl'SA
Do.,
398
-....
•
I•.
HCS--:::~
---------
..
~"
HITACHI
50%
______
HM21504, HM21504-1
256-word x 1-blt Fully Decoded Random Access Memory
The HM2504 Series item is a TTL compatible, 256-word x 1-bit,
read/write random access memory developed for application to
buffer memories, control memories, high·speed main memories, etc.
This is a fully decoded, read/write random access memory perfectly
compatible with the TTL logic family, designed as an open collector
output type for simplicity of expansion.
• Level .............•..•..... TTL compatible
• Construction ...•..........•. 256-word x 1 bit
• Read access time .............• HM2504: 55ns (max)
HM2504·1: 45ns (max.)
• Chip select access time •........ 30ns (max.)
• Power consumption ........... 1.8mWlbit (typ)
• Output ........•..• • . . • . • .. Open collector
(00-18)
• PIN ARRANGEMENT
• TRUTH TABLE
Din
Output
Ope.
CoUeetor
I.p.uts
WE
CS
Mode
anyone H
X
X
H
Not Selected
all
L
L
L
H
Write "0"
all
L
L
H
H
all
L
H
X
Dout'
Write ·'1"
Read
Note.) x : Don't care
.. : Read out inverted
(Top View)
• BLOCK DI~GRAM
0;;;;
_ ......._ ... Cii
r-lt=t~-~'-~==::~
Din
.ABSOLUTE MAXIMUM RATINGS
Symbol
Item
HM2504. HM2504-1
Unit
Supply Volta.e.
Vee
-0.5 to +7.0
Input Voltl.e
V"
-0.5 to +5.5
V
Input Current
I"
-12 to +5.0
mA
V
Output Volta.e (OUtput HI.h)
V•• ,
-0.5 to +5.5
V
Output Volta,e (DC Output Low)
I .. ,
+20
Stora,e Temperature
T."
-65 to +150
mA
·C
Storage Temperature
T.,,(Bia.)'
-55 to +125
'C
• Under Bias
•
HITACHI
399
HM2504,HM2504-1------------------------------------------------------.ELECTRICAL CHARACTERISTICS
eDC CHARACTERISTICS (Vee-S.OV ±S%. To-O to +7S'C, air flow exceeding 2m/sec)
Ite..
Output Voltage
Input Voltage
Input Current
Symbol
Te.t Condition
VOL
Vee-4.15V, IOL-16mA
V,.
Guaranteed Input Volta,. Hllh
VIL
Guarant.ed Input Voltale Low
I,.
Vee-5.25V. V•• -4.5V
IlL
Vee-5.25V, V•• -O
Output Leakage Current
Ie ..
Vee-S.2SV, V... -4.5V
Input Clamp Voltage
V,
Vee-5.25V, 1.. --10mA
Icc
Voc-S.25V
All input GND
Supply Current
min
HM2504 Seri ea
typ
mex
Unit
-
0.3
0.45
V
2.0
1.6
V
-
-
1.5
0.85
V
0
20
p.A
-530
-800
p.A
0
50
p.A
-1.0
-1.5
V
135
mA
130
mA
-
-
-
I 0< T,,<25'C
-
I To; Ta<25'C
I Taii:25'C
-1.0
-1.5
V
-
155
mA
95
130
mA
eAC CHARACTERISTICS (Vcc=5.0Y ±5%, Ta-O to +75'C. air flow exceeding 2m/sec)
1. READ MODE
HM2511-l
HM2511
Item
Symbol
Test Condition
Unit
min
typ
max
min
typ
max
Chip Select Access Time
lAcs
40
-
-
30
n.
tZ1CCS
-
15
Chip Select to High Z
20
40
-
-
30
ns
Addre.. Access Time
IAA
-
40
70
-
35
45
ns
2. WRITE MODE
HM2511-l
HM2511
Item
Symbol
Write Pulse Width
Iw
Data Setup Time
tWSD
Test Condition
twsA-min
Unit
min
typ
max
min
typ
max
50
25
-
35
10
-
ns
5
0
-
5
-
-
n.
ns
5
0
-
5
-
-
15
0
-
5
-
ns
tWNiI
5
0
-
5
Chip Select Setup Time
twscs
5
0
5
-
ns
Chip Select Hold Time
tWHes
5
0
-
-
-
5
-
-
ns
Write Disable to High Z
tzws
-
20
40
-
20
35
n.
Write Recovery Time
Iwo
-
42
55
-
30
45
n.
Data Hold Time
tWHO
Address Setup Time
'WSA
Addres. Hold Time
lw-min
ns
3. CAPACITANCE
Item
HM2511 Series
"le~t. Condition
Symbol
Unit
min
typ
max
Input Capacitance
C"
-
3
5
pF
Output Capacitance
Cut
-
9
11
pF
408
•
HITACHI
-------------------------------------------------------HM2511,HM2511-1
• TEST CIRCUIT AND WAVEFORMS
<.
1. LOADING CONDITION
INPUT PULSE
C"
JO,F
L"aa :\
Lo.td fI
3. READ MODE
""-;;--V
Addr~
, '-----------
,,
00111
Load A
00111
1A(~f--- r - - - -
L('Iad B ..!:!I£.H_Z___ __ .J
(All time measurements refer to 1.SV)
4. WRITE MODE
.,;
~~
1\
/
'V
I
~I
/
~/
~(.
/1\
.J
'\
1-"'--'0-
~I\'
:1
J~
f.--'""'1---,".,,-
I----tK'sA_
twscs-
---
Hiih'z---
,~'-------~
Load A
~twlI
Load 8
(All time measurements refer to 1.5V)
5. WRITE ENABLE TO HIGH Z DELAY
5V
HM2511
Load C
6. PROPAGATION DELAY FROM
CHIP SELECT TO HIGH Z
cs
(All tzax parameters are measured
at a delta of O.SV from the logic It"vel
jl.5V
---~'~IZIlCS
,r---~ihz
Dout
and usinR Load C)
_-,"0_".::L,'-!v"",'_ _--'!_}O,SV
_-,"1_"".::L:.:".:.;,I_ _~.I -}O.5V
\ ____l!!~l.
Doyt
•
HITACHI
409
410
•
HITACHI
BIPOLAR PRO
•
HITACHI
411
.PROGRAMMING INFORMATION
Hitachi's sophisticated Fine Emitter technology and programm"",
pulse method enables higher programmabilitY and faster programming time ordinary PROMs, for the highest reliability.
Fast programming time of typically 7.5J.Ls/bit is adhieved with a fine
emitter cell which requires less programming energy; thus, negligible
thermal str.... Further, Hitachi advanced technology allows very
high programmability.
To assure that the element is programmed properly an additional
four programming pulses are applied immediately after a sensa pulsa
indicates conduction in the programmed (one programming pulse:
Series) bit. This high reliability feature virtually eliminates aluminum
migration in the progralT\med cell.
One extra row and one extra column of test cells, plus additional
circuitry built into the PROM chip, allow improved factory testing
of DC, AC and programming characteristics. These test cells and test
circuitry provide enhanced correlation between programmed and
unprogrammed circuits in order to guarantee high programmability
The device is manufactured with outputs low (positive logic "zero")
in all storage cells. To make an output hi., at a particular cell, a
junction must be changed from a blocking state to a conducting
state. This procedure is called programming.
A logic "one" can be permanently programmed into a selected bit
locetion. The desired' bit for programming is selected using ten
address inputs to'turn on transistors 01 and 02. By taking either (or
both) chip eneble inputs high, the chip is disabled and transistor 03
is held off. Then, a train of programming pulses applied to the
desired output flows through the junction into transistor 01. This
programming current changes the junction to the conducting state.
The pulse train is stopped as soon as the sensed voltage indicates that
the salected bit is in the logic in state.
An additional 4 programming pulses (1 programming pulse: S1I8rle.)
are required to ensure that the bit is fully programmed, and to
achieve hiqh reliability. One output must be programmed at a time,
since the internal decording circuit is capable of sinking only one
unit of programming current at time.
and eliability.
INTERNAL PROGRAMMING CIRCUIT
PROGRAMMED CELL (CROSS SECTION)
Aluminum
N(Emltter)
412
•
HITACHI
.HITACHI PROMS AND PROGRAMMING CURRENT
Memory Size
4k
Glr,aniz.tion
lkx4
2kX4
8k
Output
(50na max)
3S
HN25045
(50na max)
-
O.C.
HN25084
(60n. max)
HN25084S( SOn. max)
3S
HN25085
(60na max)
HN25085S(50na max)
HN25088
(60n. max)
O.C.
3S
2kx8
ProtIrammin, Current
S-Series
HN25044
lkx8
16k
N-Series
O.C.
O.C.
3S
HN25088L(100n. max)
HN25089
(60n. max)
HN25089L(100na max)
130mA(typ)
HN25088S(SOns max)
HN2S089S( SOna max)
HN25168S( 60ns max)
HN25169S( 6On. max)
90mA(typ)
Note) O.C. : Open Collector OUIPUI
3 S : !hr. Slale OUlput
Hitachi's PROM has two families in accordance with the program
specifications. They are usually discriminated by the suffix of the
model name. For the S-series PROM, the production technique
established for the N·series PROM is further improved to attain very
small memory cell area and chip area as well as high performance .
• HITACHI
413
HN2E5044, HN25045
1024-word x 4-blt Programmable Read Only Memory
The HITACHI HN26044 and HN25045 are high speed electrically
programmable, fully decoded TTL Bipolar 4096 bit read· only
memories organizad at 1024 words by 4 bits with on-chip address
decoding and two chip enable inputs. The HN25044 and HN25046
are fabricated with logic level "zeros" (low); logic level "ones"
(high) can be electrically programmed in the selected bit locations.
The same address inputs are used for both programming and reading •
• FEATURES
• 1024 words x 4 bits organization (fully decoded)
• TTL Compatible inputs and outputs
• Fast read access time; 30 ns typo (5ci ns max.)
• Medium power consumption; 500 mW typo
• Two Chip enable inputs for memory expansion
• Open collector outputs (HN25044)/Three-stete outputs
(HN25045)
• Standard cerdip 18-pin package
(DG-!8)
• PIN ARRANGEMENT
• BLOCK DIAGRAM
(Top View)
• ABSOLUTE MAXIMUM RATINGS (Ta-2S'C)
Item
Symh!ll
R"tin~
Unit
Supply Vollage
Vee
-0.5 to +7.0
V
Input Voltag.
Vi.
-0.5 to +5.5
V
Output Voltag.
V••t
-0.5 to +5.5
Output Current
10,,'
50
V
mA
Operating Temperature
T."
-25 to +75
'C
Storage Temperature
T."
-65 to +150
'C
414
•
HITACHI
----------------------------------------------------HN25044.HN25045
• DC CHARACTERISTICS (Vcc-4. 7S to S.2SV. Ta-O to +7S'C)
Item
Symbol'
HN250«
Test Condition
min
typ
2.0
-
V,.
Input Voltage
VON
IOH--2mA
VOL
IOL-16mA
I,.
V,.-2.1V
-
I'L
VIL -0.4V
-
-
V••• -5.5V
-
V... -0.4V
-
-
V'L
Output Voltage
Input Current
Output Leakage Current
101.1(
Input Clamp Voltage
V,
1,,--18mA
Power Supply Current
lee
Input Either Open or at Ground
Output Short-circuit Current
10.
Vn.-OV
Input Capacitance
C..
V.. -2V. Vee-OV
Output Capacitance
C•• t
V••• -OV. Vee-OV
-
• AC CHARACTERISTICS (Vcc=4. 7S to S.2SV. Ta=O to 7S'C)
Symbol
min
typ
max
Unit
Address Access Time
IAA
35
50
ns
Chip Enable Access Time
tACE
20
30
ns
Chip Enable Disable Time
iDeE
-
20
30
ns
Item
HN25045
Unit
max
min
typ
40
pA
-0.4
mA
max
-
2.0
0.8
-
-
2.4
0.45
-
40
-0.4
-
-
100
-
-
100
-
40
40
-1.2
100
130
-
-
5
10
1
12
-
-
-
V
0.8
V
-
V
0.45
V
pA
-
-1.2
V
100
130
mA
15
30
60
mA
-
5
10
pF
1
12
pF
Notes: 1. Typ. value Is at vcc=5.0 V and
Ta = 2S"C
2. Output disable time is the time
tp1c:en for the output to reach a
high resistam:e state when either
chip enable is taken high. Output enable time is the time
taken for the output to become
active when both chip enables
are taken low. The high resistance sta te is defined as a point
on the output waveform equal
to a AV of 0.5 V from the
active output level.
• SWITCHING WAVEFORMS
Chip Enable
l.5V
Input
Address
Input
-+-+--,'AC'
v.--,..... .
'1'
I.SV
Output
Output
---~..J'GND
or
or
Output
Output
l.5V
v.---'
.SWITCHING TIME TEST CONDITIONS
SWITCHING
pARAMETER
IAA
tACE
"1"
I.e. "0"
IDeE "1"
iDCE
"0"
HN25045
HN25044
R,
R.
CL
R,
R.
CL
300n
600n
30pF
300n
600n
30pF
10pF
300n
600n
300n
600n
10pF
30pF
00
600n
300n
600n
10pF
00
600n
30pF
300n
600n
30pF
INPUT CONDITIONS
Amplitue" OV to 3V
Ri.e and Fall time .. 6n. from
tv
to 2V
Frequenc)," IMHz
_HITACHI
415
HN25044,HN26045----------------------------------------------------• PROGRAMMING SPECIFICATION
Limit
Characteristic
Unit
25±5
·C
Programming Pul ••
Amplitude
Clamp Voltage
Ramp Rate
Puis. Width
Duty Cycle
130±5%
20+0%-2%
70ma.
7.5±5%
70% min
mA
V
VII's
ps
Sense Current
Amplitud.
Clamp Voltage
Ramp R.te
Sense current interruption before and after address change
20±0.5
20+0%-2%
70ma.
10m in
mA
V
Vips
ps
5.0+5%-0%
V
Ambient Temperature
Programming Vee
7.5±0.1
V
Delay from trailing edge of programming pulse before nnsing
output vol tag.
0.7min
ps
Prolrammihll Time ~lJo~ationLBit
Additional Programming Pul.e Number
lOOma.
4
ms
Time
Maximum Senaed Voltage for progralftJlled "1"
• TYPICAL WAVEFORMS
Vee
A,
I
An
J
V,.
V/L
V,.
CE
V/L
Sense Plalse
7.SV REF.
Sen•• Strobe
416
• HITACHI
Note.
10V point/ISOn load
10V point/150n load
-------------------------------------------------------HN25044,HN25045
• TYPICAL DC CHARACTERISTICS
INPUT CURRENT
INPUT VOLTAGE
OUTPUT LOW CURRENT v••
OUTPUT LOW VOLTAGE
y ••
100
,
@
V'
80
",-
'\I'\.~"
1
Vcc=5.0V
"
~
60
~
'\. IVCC-4.5V
c:I
5.0V
~
.0
..J
'\ 5.5V
I
20
o
2
-1
Input Vol tace
./"
o
V
/
/
200
V,,. (V)
V
400
Output Low Voltage
VOL
600
(mV)
OUTPUT HIGH CURRENT ve.
OUTPUT HIGH VOLTAGE
(HN25045)
1
.!
~
c:I
~
=
j
-40
-50
~_.....L.
_ _I-_...L.._ _
Output Hiah Volt.,e
VDN
~_..J
(V)
• TYPICAL AC CHARACTERISTICS
ACCESS TIME ye.
AMBIENT TEMPERATURE
(HN25044)
ACCESS TIME y ••
AMBIENT TEMPERATURE
(HN25045)
50
0
VcJ••5V
0
30
20
--"
V;5L
1""-
.0
-
Vcc=4.5V
./'
<
:
V/5.0V
30
-
I
r-...L It
I
;::;
20
.\!
5.5V
"-
f' 5.5V
10
10
o
-25
+50
+100
-25
Ambient Tempetature. Til (t)
+50
Ambient Temperature Ta (Oe)
_HITACHI
+100
417
HN25044, HN25045
DISABLE TIME VS.
AMBIENT TEMPERATURE
(HN25044)
DISABLE TIME VB.
AMBIENT TEMPERATURE
(HN25045)
S
S
0
0
Vcc=4.SV
~
~~ ~
'\
0
-~ ~
0
"-
I\;'OV
5.SV
·\.ov
I's.SI'
HN2S04S
HN2S044
0
-25
0
+so
- 2S
+100
+SO
+100
Ambient Temperature To (t')
Ambient Temperature Til (t)
ENABLE TIME VB.
AMBIENT TEMPERATURE
(HN25044)
ENABLE TIME VB.
AMBIENT TEMPERATURE
(HN25045)
20
20
Vcc=4.SV
....
Vcc=4.SV
\
0
\
~
\ S.ov
\
\S.OV
\ S.sv
\
I
0
-2S
-
10
+so
0
-2S
+100
DELAY TIME INCREASE
LOAD CAPACITANCE
(HN25045)
VB.
I
+so
Ambient Temperature To
Ambient Temperature To ("C) .
DELAY TIME INCREASE
LOAD CAPACITANCE
(HN25044)
~.sv
1_
+100
cel
VB.
sur---~-----;----;-----r----'----~
O'---~-----;----;-----r----'----.,
40~--~----~----1-----r----+----~
or_---+~--~----1-----r_--_+----~
30r----+-----r----+---~r_--_T----,
or---_t-----r----+---~r---_t----~
Add to Access
20r_---+----~----
10
100
300
200
Load Capacitance CL (pF)
418
100
200
Load Capacitance CL (pF)
•
HITACHI
HN25084, HN25085
2048-word x 4-bit Programmable Read Only Memories
The HITACHI HN25084 and HN25085 are high speed electrically
programmable, fully decoded TTL Bipolar 8192 bit read only
memories organized as 2048 word by 4 bit with on-chip address
decoding and one chip enable input. The HN25084 and HN25085
are fabricated with logic level "zeros" (low); logic level "ones"
(high) can be electrically programmed in the selected bit locations.
The same address inputs are used for both programming and reading .
•
•
•
•
•
•
•
FEATURES
2048 word x 4 bit organization (fully decoded)
TTL compatible inputs and outputs
r
Fast read access time: 40 ns typo (60 ns max)
Medium power consumption: 550 mW typo
One chip enable input for memory expansion
Open collector outputs (HN25084)!Three·state outputs
(HN25085)
• Standard cerdip 18-pin dual in-line package
.OPERATION
• Programming
A logic one can be permanently programmed into a selected bit
location by using programming equipment. First, the desired word is
selected by the ten address inputs in TTL level. The device is
disabled by bringing
to a logic "one". Then a train of high
current programming pulses is applied to the desired output. After
the sensed voltage indicates that the selected bit is in the logic "one"
state, an additional pulse train is applied, then is stopped.
• Reading
To read the memory the device is enabled by bringing cr to a logic
"zero". The outputs then correspond to the data programmed in the
selected word .
IDG-IS)
• PIN ARRANGEMENT
cr
(Top View)
• LOGIC DIAGRAM
A.
A,
A,
A,
A.
8192 Bit
Address
I : 128
Buffer
Decode
( 128X64)
Memory Cell Array
A.
A"
A.
A,
N
eHITACHI
419
HN25084,HN25085------------------------------------------------------.ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
Supply Vpltage
Item
Vee
-0.5 to +7.0
Unit
V
Input Volta..
V"
-0.5 to +5.5
V
Output Voltage
V•••
-0.5 to +5.5
V
Output Current
1,.,
50
mA
Operating Temperature
T••~
-25 to +75
'C
Storage Temperature
Td.
-65 to +150
'C
.DC CHARACTERISTICS (Vcc-4.1S to 5.25V, Ta-O to 1S'C)
1m in
typ
Input High Voltage
Symbol
V,H
2.0
-
-
V
Input Low Voltage
V,.
-
V
Input High Current
IIH
V,-2.7V
40
pA
Input Low Current
-IlL
V,-0.4V
-
O.S
-
0.40
mA
-
-
-1.2
V
110
150
mA
Characteristic
Test Conditions
Output Low Voltage
VOL
Output Leakage Current
IoLIC
Output Leakage Current
lOLl( 2
Vo-0.4V
Input Clamp Voltage
V,
I,--1SmA
Power Supply Current
Icc
Inputs Either Open or at Ground
Output High Voltage'
IoL -16mA
I
VOH
Output Short Circuit Current'
-los
Vo-5.25V
Io--2mA
Vo-OV
-
-
max
Unit
0.45
V
100
pA
40
pA
2.4
-
-
V
15
-
60
mA
• Note: Applicable to HN 25089 only.
• AC CHARACTERISTICS (Vcc-4.1S to S.2SV. Ta-O to 7S'C)
min
typ
max
Unit
Addre •• Acce •• Time
Symbol
I ..
-
40
60
ns
Chip Enable Acces. Time
lACE
-
25
35
ns
Chip Enable Disable Time
tDeE
-
25
35
ns
Characteristic
Note)
Te.t Condition.
1. Output Load: See Test Circuit.
2. Measuremenl Reference: l.SV for both' Inputs and outputs.
• SWITCHING WAVEFORMS
Chip Enable
Address
1000ut
Input
v. __.,........
Output
Output
or
_'AAj
Output
420
-+-+--,/ACI .,'
tAceT
Output
\ ..
1._5V_ _ _ _ _--'
v.--_./
•
HITACHI
-------------------------------------------------------HN25084.HN25085
• SWITCHING TIME TEST CONDITIONS
HN250S4
SWITCHING
PARAMETER
t ..
lACE
"I"
tACE
"0"
IDCE:
"1"
toeE 110"
HN25085
R.
R.
CL
R.
R.
CL
3000
6000
30pF
3000
6000
30pF
10pF
3000
6000
3000
6000
10pF
30pF
00
6000
3000
&000
10pF
00
6000
30pF
3000
6000
30pF
INPUT CONDITIONS
Amplitude-OV to 3V
Rise .nd F,n time-5ns from tV to 2V
Frequeney -IMHz
• PROGRAMMING SPECIFICATION
Characteristic
Unit
Limit
25±5
·C
130±$%
?9:t:?%
mA
V
Ambient Temperature
Programming Pulse
Amplitude
Clamp Voltage
Ramp Rate
Pulse Width
Duty Cycle
70m.~
VIliS
7.S±S%
70% min
ps
20±0.S
20±2%
70mox
IOmin
mA
V
Sense Current
Amplitude
Clamp Voltage
Ramp Rate
Sense Current Interruption before and after address change
ps
V
7 .S±O.1
V
Delay from trailing edge of programming pulse before sensing
output vol tage
0.7min
ps
Programm ing Pulse Number
looma.
ms
4
Time
VC('
Maximum Sensed Voltage for programmed "1"
Additional Programming Pulse Number
10V point/lSOO load
VII'S
5.0+5%-0%
Programming
Notes
• TYPICAL WAVEFORMS
Vcr
.\,
\
A.
--.I
v,.
v"
Sen lit Puist'
7.5V REF.
St'III1t'Strllhfo
•
HITACHI
421
HN25084S,HN28088S
2048-word x 4-bitProgrammable Read Only Memories
The HITACHI HN25084S and HN250855 are high speed electrically
programmable, fully decoded TTL Bipolar 8192 bit read only
memories organized as 2048 words by 4 bits with on-chip address
decoding and one chip enable input. The HN25084S and HN250855
are fabricated with logic level "zeros" (low); logic level "ones"
(high) can be electrically programmed in the selected bit locations.
The same address inputs are used for both programming and reading.
• FEATURES
• 2048 words x 4 bits organization (fully decoded)
• TTL compatible inputs and outputs
• Fast read ac;cess time: 25 ns typo (50 ns max)
• Medium power consumption: 550 mW typo
• One chip enable input for memory expansion
• Open collector outputs (HN25084S)/Three·state outputs
(HN250855)
• Standard cerdip 18..pin dual in·line package
• OPERATION
• Programming
A logic one can be permanently programmed into a selected bit
location by using programming equipment. First, the desired word is
selected by the ten address inputs in TIL level. The device is
disabled by bringing ~ to a logic "one". Then a train of high
current programming pulses is applied to the desired output. After
the sensed voltage indicates that the selected bit is in the logic "one"
state, an additional pulse train is applied, then is stopped.
• Reading
To read the memory the device is enabled by bringing ~ to a logic
"zero". The outputs then correspond to the data programmed in the
selected word .
• LOGIC DIAGRAM
A.
A,
A,
A,
A.
8192 Bit
Address
Buffer
I: 128
Decode
{}2RX64 1
Memory Cell Array
A.
A"
A.
A>
Ao
A,
Cf
422
•
HITACHI
":'i":'"
~
,.:.:,:..
'"''
"
.'
(OG-18'
• PIN ARRANGEMENT
(Top View)
-----------------------------------------------------HN25084S,HN25085S
.ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
Supply Voltage
Item
Vee
-0.5 to +7.0
V
Input Voltage
V ..
-0.5 to +5.5
V
Output Voltage
Vn'
-0.5 to +5.5
V
Output Current
I ..,
50
mA
Unit
Operating Temperatur..
T.",
-25 to +75
'C
Storage Temperature
T.,.
-65 to +150
'C
.DC CHARACTERISTICS (Vcc=4.7S to S.2SV. Ta-O to 7S'C)
min
typ
max
Unit
Input High Volta,e
Symbol
V ••
2.0
-
-
V
Input Low Voltage
V.L
-
-
0.8
V
Input High Current
I ••
V.~2.7V
-
-
40
pA
mA
Characteristic
Test Conditions
Input Low Current
-IlL
V.-O.4V
-
-
0.40
Output Low Volta,.
VOL
Io-16mA
-
-
0.45
V
Output Leaka,. Current
I OLK I
Vo-5.25V
-
100
pA
Output Leaka,. Current
1OLK 2,
Vo-O.4V
-
-
40
pA
Input Clamp Volta.e
V.
I.--18mA
-
-
-1.2
V
Power Supply Current
Icc
Inputs Either Open or at Ground
-
110
160
mA
Output High Voltage·
VOH
Io--2mA
2.4
-
-
Output Short Circuit Current·
-los
Vo-OV
15
-
60
mA
min
typ
V
• Not.: Applle.ble to HN25089 only•
• AC CHARACTERISTICS (Vcc-4.7S to S.25V. Ta=O to 7S'C)
max
Unit
Addr ••• Access Time
I ..
-
25
50
ns
Chip Enable Access Time
t
ACE
-
20
35
ns
Chip Enable Disable Time
foCE
-
15
35
ns
Symbol
Characteristic
Not,l
Test Conditions
1. Output Load: See Test Circuit.
2. Me.surement Referenee: 1.SV for both inputs and output •.
• SWITCHING WAVEFORMS
Address
I~put
Output
or
Output
J.5V
."
." t$V
1.5V
Chip Enable
Input
."
'DcE''I''
V,
1.5V
Output
'''f-
or
,Output
l$V
•
HITACHI
tDC£-O"
V,
423
HN25084S, H N 2 5 0 8 5 ' - - - - - - - - - - - - - - - - - - - - - - • SWITCHING TIME TEST CONDITIONS
SWITCHINC
PARAMETER
ref
,..
,-1:
HN35084S
HN25085S
III
I.
C.
III
I.
C.
3000
6000
30pF
3000
6000
30pF
co
6000
10pF
'Ace
"11~
-
-
'ACI
tlO"
3000
lOOn
10pF
3001'1
6000
10pF
'DCI
"1"
,..
-
co
lOOn
30pF
'DCI
"0"
6000
30pF
3000
6000
30pF
3000
-
INPUT CONDITIONS
A.pIU.IIe-OV to BV
RIN .... F.II 11 •• -5•• , ..... IV I. %V
F.........,-IMH•
• PROGRAMMING SPECIFICATION
min
typ
maK
Unit
30
35
30
'C
Vee
4.75
5.0
5.25
V
Iw
68
19.0
10
7.1
70
90
19.5
93
30.0
70
1.9
mA
V
V/,..I
19
1.4
19.0
10
20
1.5
19.5
Symbol
PARAMETER
Ambient Temperature
r"
Pro,..amming Vee
Prosrammins Pulse
Amplitude
Clamp Volta,e
Ramp Rate
Pulle Width
Duty Cycle
Vw
/,.,
Sense Current
Amplitude
Sense Volta..
Clamp Voltage
Ramp Rate
1.
V.
,..
Address Setup Time
Address Hold Time
Sense Setup Time
Sense Hold Time
'SA
Iss
'.s
10
10
0.1
0.1
Additional Pro,..ammin, Pulse
1
Pro,..amming Pulse Number per bit
I're
,..
-
-
1
-
-
,..1
31
1.6
30.0
mA
V
V
VI,..s
-
,..S
-
9V pOint/200n load
%
ps
ps
ps
1
time
10000
time
~
\0',,,
1
A" \0'"
CE
n
-
1.5
Note
~
---'
V,.
V" -d 'u
~~~~
ins Pulse
IS,
,......
~
-..Jn'-__
I - -_ _ _
- - 90mA (ZOVmax)
Pro,ramminl Pulse
I,
1',
____________________ 0
( ): 200Q100--<"-""
,4,
Address
.4,
Bufrer
r---..,
A.~"""L~_--'
CE,<>--<"-""
rr.
eEl
Chip
Ellable
CEo ~'""L_-'
428
•
HITACHI
(DC-24)
• PIN ARRANGEMENT
(Top View)
---------------------------------------------------HN25088S,HN25089S
• ABSOLUTE MAXIMUM RATINGS
Symbol
Haling
Supply Voltage
Vee
-0.5 to +7.0
V
Input Voltage
V ..
-0.5 to +5.5
V
Output Voltage
V •• ,
-0.5 to +5.5
V
Output Current
1••,
SO
mA
I!em
Unit
Operating Temperature
T...
-25 to +75
'C
Storage Temperature
T.,.
-65 to +150
'C
.DC CHARACTERISTICS (Vcc-4.7S to S.2SV, Ta=O to +7S'C)
min
Iyp
msx
Unit
Input High Voltage
V,.
2.0
-
-
V
Input Low Voltage
V,L
-
O.S
V
Input High Current
I,.
V,-2.7V
-
40
pA
Input Lnw Current
-IlL
VI-0.4V
-
mA
120
2.4
-
-
V
IS
-
60
mA
Characteristic
Symbol
Test Condition.
Output Lnw Voltage
VOL
IOL-16mA
Output Leakage Current
101..1( I
Vo-5.25V
Output Leakage Current
lOLl( 2
Vo-0.4V
Input Clamp Voltage
V,
I,--lSmA
Power Supply Current
Icc
Input. Either Open or at Ground
Output High Voltage·
VON
Output Short Circuit Current·
* Note: Applieable to HN25089S
-los
I",--2mA
Vo-OV
-
0.40
-
0.45
V
-
100
pA
-
40
pA
-
-1.2
V
160
mA
only.
• AC CHARACTERISTICS (Vcc-4.7S to S.25V, Ta-O to 7S'C)
min
typ
max
Unit
Address Acces. Time
IAA
-
25
50
n.
Chip Enable Acce •• Time
lACE
-
20
35
n.
Chip Enable 0 i.able Time
t DeE
-
IS
35
ns
Characteristic
Symbol
Test Condition.
Note) 1. Output LOId: See Test Cireuit.
2. Mea.urement Referenee: 1.5V for both input. and outputl,
• SWITCHING WAVEFORMS
Chip Enable
Input
\.5V
l.5V
Output
or
Output
•
HITACHI
tDCK~O~
429
HN25088S,HN25089S-----------------------------------------------.SWITCHING TIME'TEST CONDITIONS
HN25088S
SWITCHING
PARAMETER
"f:('
11:
I ..
R.
C.
R.
R.
C.
3000
6000
30pF
3000
6000
30pF
10pF
"l"
-
-
lAC' "0"
3000
6000
"l"
-
-
IDC' "0"
3000
6000
lAC'
lOCI
HN25089S
R.
INPUT CONDITIONS
Ampll .... -DV to 3V
Ri .. ud Fan 11 ... -5 •• fro.. IV
to
10pF
0()
6000
300n
6000
10pF
co
6000
30pF
3000
6000
30pF
30pF
2V
Frequency-1MH,
.PROGRAMMING SPECIFICATION
Symbol
PARAMETER
Ambient Temperature
Ttl
Programming Vee
Vee
Programminf Pulse
Amplitude
Clamp Voltage
Ramp R.te
Pulse Width
Duty Cycle
I.
V.
Address Setup Time
Addreu Hold Time
Sen.e Setup Time
Sense Hold Time
A.
·C
4.75
5.0
5.25
V
92
'20.0
70
7.9
mA
90
I.
V.
19
7.4
19.0
70
20
7.5
19.5
I ..
I ..
I ..
10
10
0.7
0.7
7.5
-
-
VIt.
V,.
mA
V
V
VII'S
1'8
p.s
p.a
p.s
-
I
.1
time
-
10000
time
--1
V" ~ IS.
-.~
in, Pulle
~'-----~I \Lf'r:."
~~A1.
=.--1"
_1
I. - - - - - - -
Pru,r.mming Pube
'pO
l::=i----
Vs - - -
430
%
-
-
9V point/2000 load
1'.
21
7.6
20.0
-
1
V
VII'.
-
-
Note
V,.'~
\
At
Unit
30
19.5
..
Programm ing Pulse Number per bit
.....
25
88
' INS
Additional Programming Pulse
typ
20
19.0
10
7.1
70
Ipw
Sen.e Current
Amplitude
Senae Voltage
Clamp Voltage
Ramp Rate
min
_~
I'"-
_________
---90"A(20V .... )
45"A(9V)
-----
2OmA(4V)
--------------------0
eHITACHI
( ):2002 • •
HN25088L, HN25089L
1024-word x a-bit Programmable Read Only Memories
The HITACHI HN25088L and HN25089L are low power and high
speed electrically programmable, fully decoded TTL Bipolar 8192
bit read only memories organized as 1024 words by 8 bits with on·
chip address decoding and four chip enable inputs.
The HN25088L and HN25089L are fabricated with logic level
"zeros" (low); logic level "ones" (high) can be electrically pro·
grammed in the selected bit locations. The same address inputs are
used for both programming and reading .
•
•
•
•
•
•
•
FEATURES
1024 words x 8 bits organization (fully decoded)
TTL compatible inputs and outputs
Fast read access time:
60ns typo (lOOns max.)
Low power consumption: 350mW typo
Four chip enable inputs for memory expansion
Open collector' outputs (HN25088L)/Three·state
outputs (HN25089L)
• OPERATION
• Programming
A logic one can be permanently programmed into a selected bit
location by using programming equipment. First, the desired word is
selected by the ten address inputs in TTL level. The device is
disabled by bringing
and/or (;E2 to as logic "one" or CE3
and/or CE4 to a logic "zero". Then a train of high current
programming pulses is applied to the desired output. After the
sensed voltage indicates that the selected bit is in the logic one state,
an additional pulse train is applied, then is stopped.
• Reading
To read the memory the device is enabled by bringing CET and CE2
to {logic "zero", CE3 and CE4 to a logic "one". The outputs then
correspond to the data programmed in the selected word .
mG-W
• PIN ARRANGEMENT
en
(Top View)
• LOGIC DIAGRAM
Min 811
iti4xl2X 1
Memllry Cell Array
-\ddress
;,
Buffer
f----\
;'~'------'
CEI~...r-..,
CE,
eEl
ChIp
Enable
CE~_,-_---,
•
HITACHI
431
HN25088L,HN25089L----------------------------------------------------.ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
Vee
-0.5 to +7.0
V
Input Voltage
V"
-0.5 to +5.5
V
Output Voltage
Vn,
-0.5 to +5.5
V
Output Current
1_,
50
mA
Operating Temperature
T.. ,
-25 to +75
'C
Storage Temperature
T. ,C
-65 to +150
'c
Item
Supply Voltage
Unit
.DC CHARACTERISTICS (Vcc =4.75 to 5.25V, Ta-O to +75'C)
Symbol
Item
Input 'Voltage
min
typ
max
Unit
VI.
2.0
-
-
V
VIL
-
-
0.8
V
Test Conditions
VOH·
Io.--2mA
2.4
Vo.
I a.-16mA
II.
VI-2.7V
-IlL
VI-0.4V
Vo";'5.25V
-
Vo=0.4V
-
-
Output Voltage
Input Current
Output Leakage Current
IOLK
Supply Current
Icc
Inputs Either Open or at Ground
Output Short-circuit Current
-los·
Vo=OV
Input Clamp Voltage
VI
II--18mA
*
8
-
-
-
V
0.45
V
40
pA
-
0.4
mA
100
pA
40
70
100
mA
-
30
mA
-
-1.2
V
Applicable to HN%5089L only.
• AC CHARACTERISTICS (Vcc -4.75 to 5.25V, Ta=O to +75'C)
Symbol
Item
Address Access Time
IA.
Chip Enable Access Time
tACE
Chip Enable Disable Time
tDeE
min
typ
max
Unit
-
60
100
ns
-
40
70
ns
40
70
ns
Notes) 1. Output Load: See Test Circuit
2. Measurement Reference: l.5V for both inputs and outputs
.SWITCHING WAVEFORMS
Address
Input
1.5V
I"
l~V
1.5V
Output
or
Output
432
IAA
(.sv
Chip Enable
I"
I"f-
Input
Vo
Output
or
Output
1.5V,
•
Vo
HITACHI
l~V
l~V
----------------------------------------------------HN2~8~HN25089L
• SWITCHING TIME TEST CONDITIONS
SWITCHING
PARAMETER
I ..
tACE
"1
lACE
"0"
tDCE
"1"
tDCE
"0"
0
•
HN25088L
HN25089L
RI
R.
C.
RI
R.
C.
3000
6000
30pF
3000
6000
30pF
00
6000
10pF
3000
6000
10pF
00
6000
30pF
3000
6000
30pF
3000
6000
3000
-
-
10pF
-
6000
30pF
INPUT CONDITIONS
Amplitude-OV to 3V
Rille and Fan time-5ns from lV to 2V
Fl'equency-1MHz
• PROGRAMMING SPEC IFICATION
Limit
Characteristic
Programm ing Pulse
Amplitude
Clamp Voltage
Ramp Rate
Pulse Width
Duty Cycle
Unit
25±5
·C
l30±5%
20±2%
70max
7.5±5%
70% min
mA
V
VIps
ps
20±0.5
20±2%
70max
mA
V
VII's
ps
Ambient Temperature
Notes
10V point/1500 load
Sense Current
Amplitude
Clamp Voltage
Ramp Rate
Sense Current Interruption before and after address change
lOmin
5.0+5%-0%
V
7 .5±0.1
V
Delay from trailing edge of programming pulse before sensing
output voltage
0.7min
ps
Programming Pulse Number
loomax
Programming Vee
Maximum Sensed Voltage for programmed "1"
•
Additional Programming Pulse Number
Vee
A,
ms
Time
J
V,.
\
A,
V"
V,.
IE
V"
Sense Pulse
7.5V REF.
Sense Strobe
~----~r------~~
_HITACHI
433
HN28168S, HN28169S
2048-word X 8-bit Programmable Read Only Memories
The HITACHI HN25168S and HN25169S.are high speed electrically
programmable, fully decoded TTL Bipolar 16384 bit read only
memories organized as 2048 words by 8 bits with on-chip address
decoding and three chip enable inputs. The HN25168S and
HN25166S are fabricated with logic level "zeros" (low); logic level
"ones" (high) can be electrically programmed in the selected bit
locations. The same address inputs are used for both programming
and reading •
•
•
•
•
•
•
•
FEATURES
2048 words x 8 bits organization (fully decoded)
TTL compatible inputs and outputs
Fast read access time: 40 ns typo (60 ns max)
Medium power consumption: 600 mW typo
Three chip enable inputs for memory expansion.
Open collector outputs (HN25168S)/Three-state outputs
(HN25169S)
• Standard cerdip 24-pin dual in-line package
• OPERATION
• Programming
A logic one can be permanently programmed into a selected bit
location by using programming equipment. First, the desired world
is selected by the eleven address inputs in TTL level. The device is
disabled by bringing crT to as logic "one" or CE2 and/or CE3 to a
logic "zero". Then a train of high current programming pulses is
applied to the desired output. After the sensed voltage indicates that
the selected bit is in the logic one state, an additional pulse is
applied, then is stopped.
• Reading
To read the memory the device is enabled by bringing rn- to a logic
"zero", CE2 and CE3 to a logic "one". The outputs then
correspond to the data programmed in the selected word •
• LOGIC DIAGRAM
434 '
•
HITACHI
(00-24)
• PIN ARRANGEMENT
(Top View)
- - - - - - - - - - - - - - - - - - - - - - - - - - H N 2 5 1 6 8 S , HN25169S
.ABSOLUTE MAXIMUM RATINGS
Symbol
Ratin.
Supply Volta.e
Item
Vee
-0.5 to +7.0
Input Volta,e
V ..
-0.5 to +5.5
V
Output Voltage
Vn'
-0.5 to +5.5
V
Output Current
In'
50
mA
Operating Temperature
T...
-25 to +75
'C
Stornge Temperature
T ...
-65 to +150
'C
Unit
V
.DC CHARACTERISTICS (Vcc-4.7S to S.2SV, Ta-O to +7S'C)
min
typ
Input Hi,h Volta.e
V,H
2.0
Input Low Volt.,e
VOL
-
Input Hi,h Current
I,.
V,-2.7V
-
-IlL
V,-0.4V
Symbol
Characteristic
,
Input Low Current
Test Conditions
Output Low Volta,e
VOL
Io,-16mA
Output Leaka.e Current
1aLK I
V.-5.25V
Output Le.ka,e Current
IoLIC a
Vo-0.4V
·Input Clamp Volta,e
V,
I,--1SmA
Power Supply Current
Icc
Inputs Either Open or at Ground
VOH
IOH--2mA
Output Hi,h Voltage'
Output Short Circuit Current·
-los
-
Vo-OV
120
max
Unit
-
V
O.S
V
40
pA
0.40
mA
0.45
V
100
pA
40
pA
-1.2
V
170
mA
2.4
-
-
V
15
-
60
mA
• Note: Applicable to HN25)69S onl,.
• AC CHARACTERISTICS (Vcc-4.7S to 5,.2SV, Ta-O to 7S'C)
min
typ
max
Unit
Address Acces. Time
I ..
-
40
60
ns
Chip Enable Access Time
tAC!
-
20
35
ns
Chip Enable Diaable Time
tDCE
-
20
35
ns
Symbol
Characteristic:
Note}
Test Conditions
1. Output Load: See Test CireuiL
2. Mea.urelDent Reference: 1.5V for both inputs .nd outputs.
• SWITCHING WAVEFORMS
1.5V
L5V
Chip Enable
Input
Address
Input
r '''r
I.5V
Output
or
Output
'AA
~.5V
1.5V
lDCE"I"
'AA
'AA
L5V
Vo
I.5V
Output
ot
Output
tDCE~OH
1.5V,
•
V,
HITACHI
435
HN25168S, H N 2 5 1 6 9 S - - - - - - - - - - - - - - - - - - - - - - - - - - -
• SWITCHING TIME TEST CONDITIONS
SWITCHING
PARAMETER
I ••
tACt: tA
"0"
tDCE
"Itt
'DCE
"0"
HN25169S
R,
CL
R,
R,
CL
3000
6000
30pF
3000
6000
30pF
10pF
-
-
1"
tACE
HN25168S
RI
3000
6000
-
-
3000
6000
10pF
30pF
00
6000
3000
6000
10pF
00
6000
30pF
3000
6000
30pF
INPUT CONDITIONS
Amplitude-OV to 3V
Rise and. FaU time - Sa. from 1V to 2V
Frequency -lMHz
.PROGRAMMING SPECIFICATION
Symbol
PARAMETER
Ambient ..Temperature
Ta
Programming Vee
Vee
Programming Pulse
Amplitude
Clamp Voltage
Ramp Rate
Pulse Width
Duty Cycle
Unit
30
·C
4.75
5.0
5.25
V
mA
7.5
92
20.0
70
7.9
88
90
19.0
10
7.1
70
19.5
-
-
19
7.4
19.0
70
20
7.5
19.5
21
7.6
20.0
10
10
0.7
0.7
-
Vs
I ..
I ..
Iss
INA
Additional Programming Pulse
-
-
-
"
-
-
1
-
"S%
mA
V
V
V/"s
"S
,,5
"S
"S
-
1
time
10000
time
~
~
VII.
AUI
---l
V,H
-d.
h.
~~~..
ins Pulse
IS.
Programming Pulse
436
•
HITACHI
Note
V
V/"s
-
-
1
Programming I'\Ilse Number per bit
I'cc
max
25
Vw
Is
Addre.s Setup Time
Address Hold Time
Sense Setup Time
Sense Hold Time
typ
20
Iw
Ipw
Sense Current
Amplitude
Sen.e Voltage
Clamp Voltage
Ramp Rate
min
I-
9V point/2000 load
IIIDRY SUPPORT CIRCUITS
eHITACHI
437
HD2912
Quadruple TTL-to-MOS Clock Drivers
The HD2912, a/clock driver for the MOS memory, has basically the
NAND function. Its input is a TTL level and its output becomes and
NMOS clock input level. It operates on two power supplies - Vee
(5V) and Voo (12V). It anticipates taking as its load a maximum of
ten units of 4K-bit NMOS memories and can drive a load capacity
of 400 pF at high speed.
•
•
•
•
•
TIL·MOS level converter circuit
Switching time: 50 ns (max.)
Load capacity drivable: 600pF
Mounted with 4 circuits
Applicable temperature: 0 to 70°C
IDC-16)
.ABSOLUTE MAXIMUM RATINGS
Symbol
Item
• PIN ARRANGEMENT
HD2912
Unit
Vec·
7.0
V
r"/I
VDD"
IS.0
V
y,
Input Voltage
V,n"
5.5
V
Load Capacitance
CL ....
600
pF
Supply Voltage
Power Dissipation
PT"··
SOO
mW
Operating Temperature
T.,.
o to
+70
'C
Storage Temperature
T",
-65 to +150
'C
A,
B,
B.
A•
• With respect GND
.. *
* ...
per circuit
per package
y.
GND
• RECOMMENDED OPERATING CONDITIONS
Item
Supply Voltage
Symbol
min
typ
max
Unit
Vee
4.75
5.0
5.25
V
Voo
11.4
12
12.6
V
Operating Temperature
ToJir
0
25
70
'C
Load Capacitance
CL
100
pF
Ro
10
-
600
Damping Resistance
-
n
(Top View)
.ELECTRICAL CHARACTERISTICS (Ta-O to +70'C, Vcc=5V ±5%, VDD=12V ±5%)
Item
Symbol
Input Voltage
Output Voltage
Input Current
max
Unit
2.0
-
-
V
V'H
VOL
-
-
O.S
V
0.45
V
11.5
0.6
-
-1
-1.6
-2
-
-3.2
mA
mA
A
VOH
IlL
B
111.
A
I'H
IIH
I,
B
I DDH
Power Supply Current
Input Clamp Voltage
438
Test Condition
typO
VIL
V .. -2V, IOL-O.lmA
V .. -O.SV.IoH--O.lmA
V .. -0.4V
min
VDo-0.9
-
V .. -2.4V
V.. =S.SV
V .. -OV
1DDL
V.. -SV
I CCH
V .. -OV
[eeL
V.. =SV
V,
I .. --12mA
•
HITACHI
-
40
-
SO
16
24
-
O.S
V
pA
pA
12
IS
67
100
mA
mA
mA
mA
mA
-I.S
V
-
1
---------------------------------------------------------------HD2912
.SWITCHING CHARACTERISTICS (Ta-O to +70·C. Vcc-5V. VDD=12V)
min
typ
max
Unit
-
35
50
ns
C.-300pF
-
25
45
ns
RD-On
-
12
25
ns
-
12
25
ns
Symbol
Item
Rising Delay Time
toLH
Falling Delay Time
lOHL
Rise Time
t
Fall Time
t TNI.
Test Condition
TLH
-
eTEST CIRCUIT AND WAVEFORMS
Vee Von
3V
I~~~~~-----ov
'/""
IIIHI
~W_-oOutPUt
t-+---L__~
ITHL
Ie =250ns,I... " =350M,I, ""t.
FALLING DELAY TIME VB.
LOAD CAPACITANCE (1)
RISING DELAY TIME VB.
LOAD CAPACIT..NCE (2)
50
50
-
40
~
-
e
30
I
;:
~
20
~
~~
A~
-
~ :.......
f.- f.-
.......
-.
E
.-!PC:
~
RD=~II
i-- f--
---
10-
30
~
'"
Vcc=5V
20
Voo=12V
Vcc-SV
10
ri= 2sic--
rat2sl-
100
200
300
400
500
200
100
600
RISE TIME AND RISING DELAY TIME
AMBIENT TEMPERATURE
VS.
50
50
--
30
500
400
600
FALL TIME AND FALLING DELAY TIME
AMBIENT TEMPERATURE
VB.
tDLH
300
Load Capacitance CL (pF)
Load Capacitance CI. (pF)
0
-
,..-
J.
;:
;!i
.~
Vo~= 12V
10
40
~
1\.",\)\1
~
= IOtlns
~'~-1---+--~--+---~-1---1
InNL
-.-'THL
ITLN
VDD-12VVcr';SV
0
10
20
30
40
CL=3oopF
RD=QQ
70
60
10
2f)
30
~
50
Voo=12V
Vcc'=SV
CL':'3OOpF
RD;'og
70
60
Ambient Temperature Ta ("C)
Ambient Temperature Ttl ("C)
•
HITACHI
439
HD2912--------------------------------------------~-----------------
SWITCHING TIME VB.
SUPPLY VOLTAGE (1)
SWITCHING TIME VB.
SUPPLY VOLTAGE (2)
so
I
40
I,
t/I/.H
- -----+1~ r--
I
I----
,
10 I----
1l'1'L
i
!
I
i
!
Supply VoltagE'
7IM
,
i.,\,:,.' \'
\'
,
'1'o..l', !J.
C,=~ .J';
'.
I
1'1 II
_I
JIMI
20
I
"
1
1
lUll
i
11,1
0.2
i
I
I,
,I
: :' I'
i
IJ
I
I!
:i
1
.,
,
' 1
, I II' lI. Do" C,d,-50?,. I
I IiJ
One Circuit Operation
I (Other Circuit O,utput-Low lO
1\ I I I I ! I
' 111111
II
;
0.5
1.0
eyel!:' Tilnt'
10.5
11.0
1
11.5
C, =3OOpf
Vee ==5V
r.=25'C
12.5
12.0
~'nu
R,.=OQ
13.0
13.5
IV)
.ITEMS REQUIRING CARE WHEN USING
THE HD2912
When measuring or mounting the HD2912, consider
the following.
1. At the time of "H"level output, if a short circuit
occurs between the output terminal and the
other terminal (the GND terminal or input
terminall, the element will breakdown.
2. When measuring the input/output characteristic
of the circuit, do not place the input level in the
vicinity of the threshold voltage (about 1.SVI for
more than 10 seconds. If this caution is neglected, the element may breakdown.
3. If iu load capacity is less than a certainalue
(100pF), sometimes this element cannot fully
provide its function. Take note of this fact when
designing a system.
4. When mounting this element, it is recommended
providing the output terminal with a damping
resistor (Rol or a diode terminating circuit.
: ' I, I!
!, I; i'
._-
Supply Voltage
I I " II
"r\. !\i. : Ltl ,
I !'j.,:
I
o
5.ti
5.4
---t-f
ITL"r-
10
VI
I I " II·
, I, ·1
!IW
I,'
i 1.;1
I Iii I
\ (" =4(111".'
o
I
--_.
lrHL
POWER DISSIPATION
VB. CYCLE TIME
rilMI
50
rC(
"IHL
I
H,,=CXl
5.2
5.0
4.8
r--------I--
20
-+--c, =JUOpfI
V~"=12V
I
r~=25'C
tru_
4.6
4.4
30
;
!
i
o
r-
l---+---
------ r--- J----
I"L"
w
" " I . (IISI
VfIll
~_________
Clock Driver
440
•
HITACHI
t
~
r.;,;I
HD2916
Quadruple TTL-to-NMOS Clock Drivers
The HD2916, a clock driver for the MOS memory, basically
possesses a NAND function. Its Input is a TTL level and its output
becomes NMOS clock input level. It operates on two power supplies
- Vcc (5V) and Voo (12V). Assuming that a maximum of five
units of 4K·bit NMOS memories may be connected, it is designed to
drive a load capacity of 200pF at high speeds •
•
•
•
•
•
•
•
FEATURES
TTL·MOS level converter
Switching time: 50 ns (max.)
Average power consumption: 600mW (max.)
Load capacity drivable: 300pF
Mounted with 4 circuits
Applicable temperature: 10 to 65°C
(DG'16A)
• PIN ARRANGEMENT
• ABSOLUTE MAXIMUM RATINGS
Symbol
Item
HD2916
Unit
Vee·
-0.5 to +7
V
VDD*
-0.5 to +15
V
Input Terminal Voltage
VIN-
-0.5 to +5.5
V
Output Load Capacitance
CL ••
300
pF
Supply Voltage
Power Dissipation
PT···
Operating Temperature
To,~
Storage Temperature
T...
700
mW
+70
·C
-50 to +150
·C
o to
... With reapect to GND
...... Per circuit
... ...... Per peckap
(Top View)
• RECOMMENDED OPERATING CONDITION
Item
Supply Voltage
Operating Temperature
Input Voltage Level
Symbol
min
typ
max
Unit
Vee
4.75
5.0
5.25
V
VDD
11.4
12.0
12.6
V
Top,
10
25
55
·C
VlH
2.0
V
-0.5
-
5.5
VlL
0.8
V
.ELECTRICAL CHARACTERISTICS (Ta-lO to 55'C, Vcc=5V ±5%, VDD=12V ±5%)
Item
Symbol
A
Input Current
B
Output Voltage
VIN-2.4V
IlL
VIN-0.4V
liN
VIN-2.4V
IlL
VIN-0.4V
VON
VIN-0.8V.loN=-50),A
VOL
VIN-2.0V, IOL-50),A
Average Power Dissipation
* Vcc-5V.
.'
-
-
Unit
-1
max
40
-2
-2
80
-4
),A
-
VDD-0.7 VDD-0.4
-
leeH
VIN-OV
-
-
0.3
13
0.45
20
13
40
39
),A
mA
mA
V
V
IDOL
VIN-5V
-
-
leeL
VIN-5V
40
60
PTA
CL-300pF, j-1MHz
tw-O.5ps one circuit operation
-
mA
mA
mA
mA
300
600
mW
VIN-OV
IDDH
Supply Current
typO
min
Test Condition
liN
VDD-12V
•
HITACHI
441
HD2916------------------------------------------------------------.SWITCHING CHARACTERISTICS (Ta-lO to 55'C. Vcc-5V ±5%. VDD-12V ±5%)
Item
Symbol
Test Condition
CL-200pF
t DLH
,-IMHz
Output Delay Time
typ
-
-
-
tw-O.5,.s
hilL
min
max
Unit
50
ns
50
n8
• TEST CIRCUIT & WAVEFORMS
r.:,,,---3V
I.....
Output
Output
...",
,"'IMH1.'. -soo.•. r rLH = ""L:= IOft.t In.
PROPAGATION DELAY TIME
va. AMBIENT TEMPERATURE
PROPAGATION DELAY TIME
va. LOAD CAPACITANCE
so
0
-- - -:::+
t
30
i--
~
r-- ,
~
I
t~
I
2t I
"7 V-
-
--
fo-
!
0_
.-+::::II-- - -
-
;~'~~~~V
0
-
100
ISO
200
250
i
Vc-c;*SV
" =2OUpF
~
8
-
C","
I- "-- tllHL
"'HI.
-
,
~;~I~~;~V
10
4.4
4.6
4.R
5.0
5.2
,~:~~i
L=r"f;
0
CL=rr l
5.4.
5.6
o
10.5
Supply Voltage Vee (VI
442
70
40
20
o
60
Ta("C1
PROPAGATION DELAY TIME
va. SUPPLY VOLTAGE
•
a
~
50
40
IIIU;
~
.t
30
20
-
50
-fo-
~
_. l - I-- I'",,=IZV-
Ambipnl Temperature
SO
E 30
I
~
i-
10
300
PROPAGATION DELAY TIME
va. SUPPLY VOLTAGE
,:
I
'",11
Load Capacitance CL (pF')
40
f-
0
50
_
-
11011'
I
"-
I'" =5V
i
-~
!
11.0
11.5
12.0
12.5
Supply Voltage VDD (V)
•
HITACHI
13.0
13.5
---------------------------------------------------------------HD2916
POWER DISSIPATION
va. CYCLE TIME
+
500
Duty Cycle 50%
One cireuit_
400
Operation
; ' =3OOpf
JOO
~
C, =ISOpf
I
f' ~
C, =Opf
100
10
.ITEMS REQUIRING CARE WHEN USING
THE HD2916
When measuring or mounting the HD2916, consider
the following:
1. At the time of "H" level output, if a short circuit
occurs between the output terminal and the
other terminal (the GND terminal or input
terminal), the element will breakdown.
2. When measuring the input/output characteristic
of the circuit, do not place the input level in the
vicinity of the threshold voltage (about 1.5V) for
more than 10 seconds. If this caution is neg·
lected, the element may breakdown.
20
Cycle Time Ie,••• (IlS}
•
HITACHI
443
HD2923
Quadruple ECl to TTL Drivers
The HD2923 is a monolithic, high speed Quadruple ECl to TTL
Driver which accepts ECl input signals. It provides high output
current suitable for driving the TTL clock inputs or other. address
multiplexing inputs of N-channel MOS memories such as the
HM4816Aof MK4116.Power supply requirements are ground, +5.0
Volts and -5.2 Volts. The HD2923 requires no particular power
supply' sequencing in order to assure standby mode of memories,
because the outputs are always "high" at applying the power.
Propagation delay is 10ns MAX.
The HD2923 is fabricated by means of HITACH I's Schottky Bipolar
technology to assure high performance over the O°C to 75°C
ambient temperature range.
IOG'16AJ
.FEATURES
• High Speed .•.•... tpd = 10ns MAX. (50% to 2.2V dc out or to
+1.0V dc out, 200pF load)
• low Power ..........••.•....•.••..... 250mW typo (DC)
• 10K ECl Compatible Inputs
• Pin Compatibility ..•....•.......•.. MC10125 or HD10125
• PIN ARRANGEMENT
.ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Unit
Vee
-0.5 to +7
V
VEE
-7 to +0.5
V
Input Voltage
V ..
VEE to +0.5
V
Output Voltage
You,
-1.0 to Vee+1
V
Power Dissipation
Pr
1.0
W
Operating Temperature·
Top~
Supply Voltage
Storage Temperature
•
T."
-10 to +85
·C
-65 to +150
·C
nop View)
The V BB reference voltage is avaiJable
on pin 1 for use in single ended input
biasing
• TRUTH TABLE
under bIas
Input
• RECOMMENDED OPERATING CONDITIONS
Item
Symbol
typ
min
Y
Unit
H
V••
L
4.75
5.0
5.25
V
L
V"
H
VEE
-5.46
-5.2
-4.94
V
H
L
L
VIH
-1.025
Input Voltage
V"
444
B
Vee
Supply Voltage
Operating Temperature
max
Output
A
Top,
-
0
-
-
V
L
H
H
V"
H
H
-
-1.520
V
-
75
·C
$
HITACHI
V"
L
L
Open
Open
H
-----------------------------------------------------------------HD2923
• DC CHARACTERISTICS
Symbol
Item
Test Condition
Power Supply Drain Current
lecH
V .. - -5.2V. Vcc-5.0V
IeCL
Input Current
I .. H
Input Leaka,e Current
leBo
V'N--5.2V
VOH
IOH--1.0mA
VOL
IOL-5.0mA
VOHA
V'H--I.IV.loH--I.OmA
VOLA
VIL--1.48V.loL-5.0mA
V'N--0.8IV
27
mA
-
23.5
29
mA
-
34.5
42
mA
-
-
115
}lA
}lA
-
1.0
-
-
-
-
0.5
V
2.7
-
-
V
-
0.5
V
All inputs-V..
2.7
-
All inputs - Open
2.7
-
VOHS.
Reference Voltage
-
-1.420
-
2.7
-
-
V'NH= -1.890V. V'NL- -2.890V
2.7
-
-
VOHe
Common Mode Rejection Tests
-
VIHH-0.300V. V'NL- -0.825V
VOLe
V'NH- -I. 890V. V'NL- -2.890V
V
-
V'NH-0.300V. V'NL- -0.825V
V••
Unit
22
-
Threshold Voltage
Protection Tests
max
-
2.7
Output Volta,.
Indeterminate Input
typ
min
-I ..
-1.150
V
V
V
0.5
V
0.5
• AC CHARACTERISTICS
Symbol
Item
Test Condition
ID.
50% to +2.2V. CL-200pF
IDF
50% to +1.0V. CL-200pF
Rise Time
1+
+1.0V to +2.2V. CL=200pF
Fall Time
r
+2.2V to +1.0V. CL-200pF
Propa,ation Delay Time
min
typ
msx
Unit
-
-
10
ns
-
-
10
ns
-
5
ns
5
ns
-0.890V
V,.
-1.690V
Vour
eHITACHI
445
HITACHI AMERICA, LTD.
ELECTRONIC DEVICES SALES & SERVICE DIVISION
HEADQUARTERS
U. S. SALES OFFICE
Hitachi, Ltd.
Nippon Bldg., 6-2, 2-chome
Ohtemachi, Chiyoda-ku. Tokyo, 100, Japan
Tel: 212-1111
Telex: J22395, J22432
Fax: 011-813-214-3158
REGIONAL OFFICES
Hitachi America, Ltd.
Electronic Devices Sales & Service Division
1800 Bering Drive
San Jose, CA 95112
Tel: 408/292-6404
Telex: 17-1581
Twx: 910-338-2103
Fax: 408-2922133
Fax: 408-2949618
DISTRICT OFFICES
Hitachi America, Ltd.
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Cranford, NJ 07016
201 1272-11 00
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617/229-2150
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Bloomington, MN 55431
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Hitachi America, Ltd.
1 Parkland Blvd., #1222E
Dearborn, MI 48126
NORTHWEST REGION
Hitachi America, Ltd.
224 W. Brokaw Rd., Suite 260
San Jose, CA 95110
408/277-0712
313/271-4410
SOUTHWEST REGION
Hitachi America, Ltd.
9700 Reseda Blvd., Suite 208
Northridge, CA 91324
2131701-6606
446
_HITACHI
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