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1984/1985
MICROELECTRONIC
DATA BOOK

Copyright © 1984 Mostek Corporation (All rights reserved)
Trade Marks Registered

®

Mostek reserves the right to make changes in specifications at any time and without notice. The information furnished
by Mostek in this publication is believed to be accurate and reliable. However, no responsibility is assumed by Mostek
for its use; nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted
under any patents or patent rights of Mostek.
The "PRELIMINARY" designation on a Mostek data sheet indicates that the product is not characterized. The specifications are subject to change, are based on design goals or preliminary part evaluation, and are not guaranteed. Mostek
Corporation or an authorized sales representative should be consulted for current information before using this product.
No responsibility is assumed by Mostek for its use. No license is granted under any patents, patent rights, or trademarks
of Mostek. Mostek reserves the right to make changes in specifications at any time and without notice.
The "TARGET SPECIFICATION" designation on a Mostek data sheet indicates that the product is not yet available. The
TARGET SPECIFICATION is an initial disclosure of specification goals for the product. The specifications are subject to
change, are based on design goals, and are not guaranteed. Mostek Corporation or an authorized sales representative
should be consulted for current information before using this product. No responsibility is assumed by Mostek for its use;
nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. No license is
granted under any patents, patent rights, or trademarks of Mostek. Mostek reserves the right to make changes in specifications at any time and without notice.
The "PRODUCT PROFILE" designation on a Mostek literature item indicates that the product is not available as of the
print date of this document and that the specification goals have not yet been fully established. the PRODUCT PROFILE
is an initial disclosure of a new product's features and general information. The information given in the PRODUCT PROFILE
is subject to change and is not guaranteed. Mostek Corporation or an authorized sales representative should be consulted
for current information before using this product. No responsibility is assumed by Mostek for its use; nor for any infringements
of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents,
patent rights, or trademarks of Mostek. Mostek reserves the right to make changes in the product at any time and without
notice.
The "APPLICATION BRIEF" or "APPLICATION NOTE" designation on a Mostek literature item indicates that the literature
item contains information regarding Mostek product features and/or their varied applications. The information given in the
APPLICATION BRIEF or APPLICATION NOTE is believed to be accurate and reliable; however, the information is subject
to change and is not guaranteed. No responsibility is assumed by Mostek for its use; nor for any infringements of patents
and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights,
or trademarks of Mostek.
PRINTED IN USA July 1984
Publication No. 4420479

1984/1985 MICROELECTRONIC DATA BOOK

Table of Contents

@J

General Information

~

Read-only Memory

eJ

Dynamic Random Access\Memory

0J

Static Random-Access Memory

®J
eJ
91
®J

68000 Family
Z80 Family
3870 Single Chip Family
Microcomputer Peripherals
Programmed Microcomputer Products
68000, 68200, Z80 and 3870 Dev. System Products

@J
9J

e]
@J
eJ

Tone Dialers
. Pulse Dialers
Repertory Dialers
Tone Decoders
CODECs & Filters
Ethernet

I.
III.
III.
IIIII.
I.

1984/1985 MICROELECTRONIC DATA BOOK

Table of Contents

TABLE OF CONTENTS

I. Table of Contents
Functional Index .................................................................. 1-1

II. General Information
Mostek Profile .................................................................... 11-1
Package Descriptions ............................................................. 11-5
Order Information ................................................................ 11-14
U.S. and Canadian Sales Offices ................................................... 11-15
U.S. and Canadian Representatives ................................................. 11-16
U.S. and Canadian Distributors ..................................................... 11-17
International Sales RepslDistributors ................................................ 11-19
International Marketing Offices ..................................................... 11-19
European Sales RepslDist. ........................................................ 11-20

MEMORY COMPONENTS
III. Read-only Memory
MK36000 (P/J/N) Series ........................................................... 111-1
MK37000 (P/J/N) Series ........................................................... 111-5
MK38000 (P/N)-25 ................................................................ 111-9
Guidelines for Submitting & Verifying Customer ROM Patterns ........................... 111-13
MK3901M(P/N) Series ............................................................ 111-17
MK2364 (P/N)-20/25 ............................................................. 111-19
MK2365 (P/N)-20/25 ............................................................. 111-23
MK23128 (P/N)-20/25 ............................................................ 111-27

IV. Dynamic Random Access Memory
MK4027 (J/N)-2/3 . ................................................................ IV-1
MK4027 (J/N)-4 ., ............................................................... IV-13
MK4116 (J/N/E)-2/3 . .............................................................. IV-17
MK4516 (N/J)-9 ................................................................. IV-31
MK4516 (N/J/E)-10/12/15 .......................................................... IV-41
MK4516 (N/J)-20 ................................................................ IV-51
MK4564 (P/N/J/E)-12 ............................................................. IV-61
MK4564 (P/N/J/E)-15/20 ........................................................... IV-71
MK45H64 (P/N/J/E)-8/10/12 ........................................................ IV-81
MK45H56 (P/N/E)-8/10/12 ......................................................... IV-83
MK4856 (N/P/J/E)-10112/15 ........................................................ IV-93

V. Static Random-Access Memory
MK4104 (P/J/N) Series ............................................................. V-1
MK4801A (P/J/N)-1/2/3/4 ............................................................ V-7
MK4801A (P/J/N)-55170/90 ......................................................... V-13
MK4701 (N)-20 .................................................................. V-19
MK6116 (J/N)-15/20/25/MK6116L (J/N)-15/20/25 ......................................... V-21
MK4501 (N)-8/10 ................................................................. V-27
MK4501 (N)-12/15/20 ............................................................. V-29
MK4511 (N/E)-15 .......................... , ...................................... V-41
MK48C02/MK48C02L (N)-15/20/25 .................................................. V-43
MK48Z02 (8)-15/20/25 ............................................................ V-51

1-1

MICROCOMPUTER COMPONENTS
VI. 68000 Family
MK68000
MK68008
MK68010
MK68200
MK68230
MK68451
MK68564
MK68901

CPU
Central Processing Unit ............................... VI-1
CPU
Central Processing Unit .............................. VI-53
VMM
Virtual Memory Microprocessor ........................ VI-59
16-Bit Microcomputing Unit ........................... VI-65
MCU
Parallel InterfacelTimer .............................. VI-111
PIIT
MMU Adv. Inf. Memory Management Unit ........................... VI-121
SIO
Serial Input/Output Controller ........................ VI-125
Multi-Function Peripheral ............................ VI-137
MFP

VII. Z80 Family
MK3880
MK3881
MK3882
MK3883
MK3884/517
MK3884/517
MK3801

A&B CPU
PIO
CTC
DMA
SIO
S10/9
STI

Central Processing Unit .............................. VII-1
Parallel 110 Controller ................................ VII-9
Counter Timer Circuit ............................... VII-17
Direct Memory Access Controller ...................... VII-25
Serial Input/Output Controller ......................... VII-43
Single Channel Serial Input/Output Controller ........... VII-59
Serial Timer Interrupt Controller ....................... VII-63

VIII. 3870 Single Chip Family
3870 Family Selection Guide ...................................................... VIII-1
MK3870/38P70
Single Chip Microcomputer ........................... VIII-3
MK2870
28 Pin Microcomputer .............................. VIII-31
MK3873/38P73
Serial Port Microcomputer ........................... VIII-49
MK3875/38P75
Stand By RAM Microcomputer ....................... VI 11-75

IX. Microcomputer Peripherals
MK3805N
MK3807

CMOS Microcomputer Clock/RAM ...................... IX-1
Programmable CRT Video Control Unit VCU ............. IX-13

X. Programmed Microcomputer Products
SCU20

Serial Control Unit .................................... X-1

XI. 68000, 68200, Z80 and 3870 Development System Products
Radius
AIM68000
AIM68200
AIMZ80BE
AIM7XE
EPP1
Matrix 68K
Matrix 80/SDS
Eval 70
M/OS-80
MICROSOFT
ASM-68000/LNK-68000
ASM-68200/LNK-68200
CRASM-70
Ordering Guide

Remote Development Station .......................... XI-1
Application Interface Module ........................... XI-5
Application Interface Module .......................... XI-11
Application Interface Module for Z80 ................... XI-15
Application Interface Module for 3870 Series ............. XI-19
EPROM Programmer ................................ XI-23
Microcomputer System .............................. XI-29
Microcomputer Development System ................... XI-31
Evaluation System for 3870 ........................... XI-35
Flexible Disk Operating System ....................... XI-39
M80/L80, Basic-80, Bascom, Fortran-80 ................. XI-43
Structured Macro Cross Assembler/Relocating Linkage EditorXI-45
Structured Macro Cross Assembler/Relocating Linkage EditorXI-49
Cross-Assembler for 3870 ............................ XI-53
Development Systems Products ....................... XI-55

1-2

TELECOMMUNICATIONS
XII. Integrated Tone Dialers
MK5087 (N/P/J) ................................................................. XII-1
MK5089 (N/P/J) ................................................................. XII-7
MK5087/89 Electronic Drive App. Brief .............................................. XII-13
MK5380 (N/P/J) ................................................................ XII-15
MK5175/MK5380 Pulse/Tone Switchable Application App. Note .......................... XII-23
Tone II vs Tone III App. Brief ..................................................... XII-27
Loop Simulator App. Brief ........................................................ XII-29

XIII. Integrated Pulse Dialers with Redial
MK50981 (N)-05 ................................................................ XIII-1
MK50982 (N) ................................................................... XI 11-5
MK50991 (N) .................................................................. XIII-11
MK50992 (N)-05 ............................................................... XIII-17
Pulse Dialer Comparison App. Brief .................... ,.................. , ........ XIII-21
Current Sources App. Brief ...................................................... XIII-23

XIV. Repertory Dialers
MK5175 (N) .................................................................... XIV-1
MK5175/MK5380 Pulse/Tone Switchable Application App. Note .......................... XII-23
MK51n (N), MK5176 (N) ......................................................... XIV-11
MK5375 ............................................................. , ........ XIV-21
MK5374/MK5376 ............................................................... XIV-33
MK5370/MK5371/MK5372 ............................................... , ....... .'XIV-35

XV. Integrated Tone Decoders
MK5102 (N/P/J) ...................................................... ' .......... XV-1
MK5103 (N/P/J) ................................................................. XV-5
MK5102/S3525A App. Brief ............................................. , ......... XV-11
DTMF Receiver System App. Brief ................................................. XV-13
MK5102 (N)-5 DTMF Decoder App. Note ............................................ XV-15

XVI. CODECs & Filters
MK5116 (J/N) . .................................................................. XVI-1
MK5151 (J/P) . ................................................................. XVI-11
MK5156 (J/P) ........................................................ , ........ XVI-23
MK5316 (J) ................................................................... XVI-33
MK5320 (J) .......................................................... , ........ XVI-35
MK5356 (J) ................................................................... XVI-37
MK5326 (J) ................................ " .................................. XVI-39
Integrated PCM CODEC Technology Update ........................................ XVI-41

XVII. Ethernet
MK68590
MK68591

LANCE
SIA

Local Area Network Controller for Ethernet ............. XVII-1
Serial Interface Adapter ............................ XVII-15

1-3

1-4

1984/1985 MICROELECTRONIC DATA BOOK

Mostek - Technology For Today And Tomorrow

•

DRAM, it was possible to increase production from six million units in 1982 to more
than 41 million in 1983.
At Mostek, our goal is to provide faster,
denser, lower power products-at competitive prices. Through aggressive
research and development, innovative
design and commitment to quality, Mostek
is ready to anticipate and meet your
needs now, and in the future.

Quality products
based on efficient,
innovative designs.
Today's sophisticated applications
require electronic components and subsystems that deliver high performance,
high reliability. Mostek dedicates vast
resources to research and development to
give you exactly what you need: effi.c.ient,
cost-effective solutions to your specific
design needs.
Quality and reliability are built into
Mostek products every step of the way,
from the initial design stages through
manufacturing and testing. And we follow
up with extensive product training, sales
and customer support. All to achieve
Mostek's final objective-outstanding performance in your system.
Mostek combines state-of-the-art NMOS
and CMOS process technology with smart
design to develop high-quality products
that are also highly manufacturable.
Because of the efficient design of our 64K

MEMORIES

Mostek is an industry leader in the
design and manufacture of dynamic
RAMs, including the MK45H64, the
world's fastest DRAM, and the MK4856,
the first 32Kx8 256K DRAM. To meet the
precise manufacturing requirements of the
256K DRAM, Mostek has more direct-stepon-wafer (DSW) machines on-line than any
other manufacturer in the world. And more
experience with those machines as well.
Other Mostek memory product innovations
include the first true non-volatile RAM and
the BiPORTTM series of interconnect
devices.
11-1

Many of our products are qualified to
meet stringent military requirements, including the new MKB4501 BiPORT FIFO
memory chip, screened to MIL-STD-883,
Class B. And the MKB45H64, the world's
fastest DRAM, is also now available to the
armed forces through Mostek.
MICROCOMPONENTS
MEMORY SYSTEMS

At Mostek, we're dedicated to improving
the power and versatility of our MK68200
16-bit single-chip microcomputer and
MK68000 microprocessor families. For
example, our high-performance MK68200
microcomputer has the speed and power
ideal for robotics and other complex tasks.
And our MK68000 family of microprocessors and peripherals lets you
quickly develop even the most
sophisticated .I/O-intensive applications.

The performance and reliability of
Mostek industry-standard circuits is built
into all of our memory systems products.
For example, the MK8200 general-purpose
mass memory system delivers the fastest
throughput and highest density currently
available anywhere.
SEMICUSTOM CIRCUITS

Mostek now offers the designer a way
to reduce part count and increase system
reliability and performance: a full family of
2- and 3-micron gate arrays. Mostek
semicustom circuits let you design your
circuits to your specific applications. And
our captive photomask facility and largescale wafer production and assembly
facilities make Mostek a turn-key vendor,
unlike other semicustom suppliers.

MICROCOMPONENT SUPPORT

Mostek manufactures a complete line of
emulation tools. With four different cards,
Mostek supports its four different
microprocessor families, including the new
MK68200 microcomputer. By using any of
our four Mostek AIMTM modules with either
the Mostek RADIUS™ remote development
station or the Mostek MATRIX™ standalone development system, you get complete hardware/software development and
debug capabilities at competitive prices.

MILITARY

Mostek delivers the latest state-of-the-art
microelectronics in military versions.

11-2

the growing needs of the communications
industry, our product line has been expanded recently to include single and
repertory integrated dialer circuits capable
of both tone and pulse dialing.

MICROCOMPUTER SYSTEMS

Mostek offers a full line of 8-bit STD-Z80
BUS microcomputer boards and systems.
For 16-bit applications, Mostek VMEbus
systems deliver high performance and
expandability. And our new VME MATRIX
68I(TM is a multi-user, 16-bit development
system featuring the UniPlus+™ UNIX™
System III operating system.

SOFTWARE

Mostek provides powerful software
development packages for 8- and 16-bit
systems. For 8-bit microprocessors,
Mostek offers the CPIM™ V3.0 industrystandard operating system. To meet the
needs of rapildly growing 16-bit applications, Mostek offers the versatile VME
MATRIX 68K, a multi-user development
system which employs the UniPlus™ UNIX
operating system. UniPlus+ is derived
from the UNIX System III.

COMMUNICATIONS

Mostek is the world's largest independent supplier of large-scale integrated
circuits for telecommunications applications. Mostek participates in three major
market segments-analog applications,
digital applications (such as PBXs), and
computer information networks. To meet

11-3

11-4

I!

UNITED
TECHNOLOGIES
MOSTEK

MICROELECTRONIC
PRODUCTS
PACKAGE DESCRIPTIONS

Plastic Dual-In-Line Package (N)

8 Pin

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11-9

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2 POSITIONAL~IS DATUM.
I "0
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11-11

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5. WHEN THE SOLDER L!AD FINISH IS SPECIFIED, THE
MAXIMUM LIMIT SHALL BE INCREASED BY .003 IN.
4. MEASURED FROM CENTERLINE TO CENTERLINE AT
LEAD TIPS.
3. PACKAGE STANDOFF TO BE MEASURED PER JEDEC
REQUIREMENTS.
2. OVERALL LENGTH INCWDES ,010 IN. FLASH ON EITHER
END OF THE PACKAGE.
1. LEAD FINISH IS TO BE SPECIFIED ON THE DETAIL
SPECIFICATION.

C
D
E
F
G
H

NOTES:

INCHES
MAX.

MIN.
3.180
.890
.790

.170
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J
K

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L
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NOTES
2

3

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4
5
5

68000 Family
Ceramic Dual-In-Line Package (P)

64 Pin

MILLIMETERS
DIM MIN MAX
A 80.52 82.04
B 22.25 22.96
C
3.05
4.32
D 0.38
0.53
F 0.76
1.40
G
2.54 esc
0.20
0.33
J
K 2.54
4.19
L 22.61 23.11
M
10°
N
1.02
1.52

INCHES
MIN MAX
3.170 3.240
0.900 0.920
0.120 0.170
0.Q15 0.021
0.030 0.057
0.100 esc
0.008 0.D13
0.100 0.165
0.890 0.910
10°
0.020 0.060

NOTES:
1. Dimension!Eis datum.
2. Positional tolerance for leads:
1$0(0.25 (0.010)
T A@I
3.
il> seating plane.
4. Dimension "L" to center of leads
when formed parallel.
5. Dimensioning and tolerancing per
ANSI Y14.5, 1973.

rn

Case 746.01

11-12

@I I

Ceramic Leadless Chip Carrier (E)
84 Pin
TOP VIEW

75

84

1

11
12

1
c

DIM.

INCHES
MIN.
MAX.

A

1.138

1.167

B

1.138

1.167

C

.070

.090

D

.080

.110

E

.044

.056

F

.044

.056

G

.075

.095

H

.048

.052

H

.048

.052

J

.033

.039

K

.010

.018

L

.495

.505

M

.495

.505

32

111111I111"llllllllfL\\\\\\\~

T

NOTES

1

I

0

CM-t 1h
'1UlJIW IiliHllillilf L....;I

NOTES
1. BODY MATERIAL SHALL BE A1 2 03
2. PLATING SHALL BE GOLD OVER NICKEL AS SPECIFIED IN THE
DETAIL SPECIFICATION

11-13

BOTTOM

T

F

ORDERING INFORMATION

r-r

Factory orders for parts described in this book should include a four-part number as explained below:
Example: MK,,4167

1 . Dash Number

2. Package
L..-_ _ _ _ _ _

3. Device Number

' - - - - - - - - - - - 4. Mostek Prefix
1 . Dash Number
One or two numerical characters defining specific device performance characteristics and operating temperature
range.

2. Package
Gold side-brazed ceramic DIP

P

-

J

- CER-DIP

N
K
T
E
D
F

-

Epoxy DIP (Plastic)
ceramic DIP
Ceramic DIP with transparent lid
Ceramic leadless chip carrier
Dual density RAM-PAC
Flat pack

Tin~side-brazed

3. Device Number
1XXX
2XXX
3XXX
38XX
4XXX
5XXX
7XXX

or 1XXXX
or 2XXXX
or 3XXXX
or 4XXXX
or 5XXXX
or 7XXXX

-

Shift Register, ROM
ROM, EPROM
ROM, EPROM
Microcomputer Components
RAM
Telecommunication and Industrial
Microcomputer Systems

4 . Mostek Prefix
MK - Standard Prefix
MKB - Military Hi-Rei screening to MIL-STD-883 Class B for extended temperature range operation.
MKI - Industrial Hi-Rei screening for -40°C to +85°C operation.

11-14

u.s.

AND CANADIAN SALES OFFICES

CORPORATE HEADQUARTERS
Mostek Corporation
1215 W. Crosby Rd.
P.O. Box 110169
Carrollton, Texas 75006
214/466-6000

TWX 910-860-5975

TWX 910-576-2802

Southeast U.S.
Mostek
13907 N. Dale Mabry Highway
Suite 201
Tampa, Florida 33618

Michigan
Mostek
Orchard Hill Place
21333 Haggerty Road
Suite 321
Novi, MI 48050

813/962-8338

TWX 810-876-4611
Mostek

REGIONAL OFFICES
Northeastern Area
Mostek
777 West Putnam
Greenwich, Conn. 06830
203/531-1146

TWX 710-579-2928
Northeast U.S.
Mostek
83 Cambridge SI.
Suite 2-D
Burlington, Mass. 01803
617/273-3310

TWX 710-348-0459
Southeastern Area
Mostek
Pavilions at Greentree
Suite 101
Marlton, New Jersey 08053
609/596-9200

TWX 710-940-0103

303 Williams Ave.

Suite 1031
Huntsville, AL 35801
205/539-2061

TWX 910-997-0411
Upstate NY Region
Mostek
4651 Crossroads Park Dr., Suite 201
Liverpool, NY 13088
315/457-2160

TWX 710-545-0255
Chicago Region
Mostek
Two Crossroads of Commerce
Suite 360
Rolling Meadows, III. 60008

TWX 910-338-2219
Seattle Region
Mostek
1107 North East 45th SI.
Suite 411
Seattle, WA 98105

Central U.S.
Mostek
4100 McEwen Road
Suite 151
Dallas, Texas 75234

North Central U.S.
Mostek
6101 Green Valley Dr.
Bloomington, Mn. 55438

206/632-0245

214/386-9340

TWX 910-444-4030

TWX 910-860-5437
Southwest Region
Mostek
4100 McEwen Road
Suite 237
Dallas, Texas 75234

Southern California
Mostek
18004 Skypark Circle
Suite 140
Irvine, Calif. 92714

214/386-9141

TWX 910-595-2513
Arizona Region
Mostek
Camelback Arboleda Office Park
1661 E. Camelback
Suite 179
Phoenix, AZ 85016

Chevy Chase #4
7715 Chevy Chase Dr., Suite 116
Austin, TX 78752

TWX 910-291-1207

408/287-5080

313/348-8360

TWX 810-242-1471

TWX 910-860-5437

312/577-9870

Western Region
Northern California
Mostek
1762 Technology Drive
Suite 126
San Jose, Calif. 95110

512/458-5226

TWX 910-874-2007

714/250-0455

602/279-0713

TWX 910-957-4581

612/831-2322

11-15

u.s.

AND CANADIAN REPRESENTATIVES

ALABAMA
Conley & Associates. Inc.
3322 Memorial Pkwy.• S.w.
Suite 19
Huntsville. AL 35801

GEORGIA
Conely & Associates. Inc.
3951 Pleasantdale Road
Suite 201
Doraville. GA 30340

205/882-0316

414/447-6992

TWX 810-726-2159

TWX 810-766-0488

ARIZONA
Summit Sales
7825 E. Redfield Rd.
Scottsdale. AZ 85260

Remtek. Inc.
18 Perimeter Park
Suite 100
Atlanta. GA 30341

602/998-4850

404/453-4705

TWX 910-950-1283
CALIFORNIA
CK Associates
8333 Clairemont Mesa Blvd.
Suite 105
San Diego. CA 92111

ILLINOIS
Carlson Electronic Sales'
Associates. Inc.
600 East Higgins Road
Elk Grove Village. IL 60007

KD Associates
201 Benton Avenue
Linthicum. MD 21090
301/859-5151 (Baltimore Area)
301/261-1311 (Washington Area)
TWX 710-862-9320
MASSACHUSETTS
New England Technical Sales'
101 Cambridge Street
Burlington. MA 01803
617/272-0434

6031778-8495 (Home)
TWX 710-332-0435

NEW MEXICO
Waugaman Associates
P.O. Box 14894
Albuquerque. NM 871111
or
9004 Menaul NE
Suite 7
Albuquerque. NM 87112
505/294-1436

NEW YORK
ERA Inc.
354 Veterans Memorial Highway
Commack. NY 11725

UTAH
Waugaman Associates
5258 Pinemont Dr.
Suite B-l00
Salt Lake City. UT 84107
801/261-0802

TLX 757949
WASHINGTON
Northwest Marketing Assoc. '
12835 Bellevue-Redmond Rd.
Suite 330N
Bellevue. WA 98005
206/455-5846

TWX 910-443-2445

516/543-0510

312/956-8240

MICHIGAN
Action Components
21333 Haggerty Road
Suite 310B
Novi. MI 48050

619/279-0420

TWX 910-222-1819

313/349-3940

Qual ity Peri pherals
1210 S. Bascom Ave.
Suite 10
San Jose. CA 95128

Mar-Con Associates Inc.
4836 Main S1.
Skokie. IL 60077

Comp-U-Tronics. Inc.
Route 2. Box 98
Blue Springs. MI 64015

315/446-2881

414/476-2790

TWX 710-541-0604

TWX 910-222-1819

312/675-6450

816/229-3370

Tri-Tech Electronics. Inc.
3215 East Main St.
Endwell. NY 13760
6071754-1094
TWX 510-252-0891

CANADA
Cantec Representatives Inc. '
1573 Laperriere Ave.
Ottawa. Oniario
Canada. K1Z 7T3
6131725-3704
TWX 610-562-8967

408/559-3882

Quality Peripherals
17941 Skypark Circle
Suite H
Irvine. CA 92714
714/250-1033

COLORADO
Waugaman Associate'
4800 Van Gordon
Wheat Ridge. CO 80033
303/423-1020

TWX 910-938-0750

910-223-3645
Compucon
312/677-3230

INDIANA
Technology Marketing' Corp.
599 Industrial Drive
Carmel. IN 46032
317/844-8462

TWX 910-997-0194
Technology Marketing Corp.
3428 West Taylor St.
Fort Wayne. IN 46804

MINNESOTA
Cahill. Schmitz & Cahill. Inc.'
315 N. Pierce
St. Paul. MN 55104
612/646-7217

TWX 910-563-3737
Dytec/North. Inc.
1821 University Ave.
Suite 173 South
St. Paul. MN 55104
612/645-5816

TWX 910-563-3724

219/432-5553

CONNECTICUT
New England Technical Sales
240 Pomeroy Ave.
Meriden. CT 06450
203/237-8827

TWX 710-461-1126

TWX 810-499-4111
IOWA
Carlson Electronic Sales
204 Collins Road. N.E.
Cedar Rapids. IA 52402
319/377-6341

FLORIDA
Conely & Associates. Inc.'
P.O. Box 309
235 S. Central
Oviedo. FL 32765
305/365-3283

TWX 810-856-3520
Conely & Associates. Inc.
4019 W. Waters
Suite 2
Tampa. FL 33614
813/885-7658

TWX 810-876-9136
Conely & Associates. Inc.
P.O. Box 700
1612 NW. 2nd Avenue
Boca Raton. FL 33432
305/395-6108

TWX 510-953-7548
Remtek. Inc.
728 Degan Drive
Port 81. Lucie. FL 33452
305/878-6771

TWX 910-222-1819
KANSAS
Rush & West Associates'
107 N. Chester Street
Olathe. KS 66061
9131764-2700
Wichita 316/683-0206

TWX 910-749-6404
KENTUCKY
Technology Marketing Corp.
8819 Roman Court
P.O. Box 91147
Louisville. KY 40291
502/499-7808

TWX 810-535-3757
MARYLANO
Arbotek Associates
102 W. Joppa Road
Towson. MD 21204
301/825-0775

TWX 710-862-1874

TWX 510-226-1485
(New Jersey Phone #
800/645-5500. 5501)

Tri-Tech Electronics Inc. '
6836 East Genesse St.
Fayetteville. NY 13066

Tri-Tech Electronics. Inc.
300 Main St.
E. Rochester. NY 14445
7161385-6500

TWX 510-253-6356
Tri-Tech Electronics. Inc.
14 Westview Dr.
Fishkill. NY 12524
914/897-5611

Micro Resources. Inc.
4640 W. 77th St.
Suite 109
Edina. MN 55435
612/830-1454

MISSOURI
Rush & West Associates
720 Manchester Road
Suite 211
Ballwin. MO 63011
314/394-7271

TWX 910-752-653

TWX 710-541-0604
OHIO
The Lyons Corp.
4812 Frederick Rd.
Dayton. Ohio 45414
TWX 810-459-1754

809/843-7139

503/297-2581

TELEX 910-464-5157
TEXAS
Technological System Sales
4255 LBJ Freeway
Suite 282
Dallas. TX 75234
214/458-0644

609/429-1551
215/627-0149 (Philadelphia Line)
TWX 710-896-0881

'Home Office

11-16

514/683-6131

TWX 610-422-3985

216/659-9224

TWX 510-928-1829

609/424-6622

Cantec Representatives Inc.
3639 Sources Blvd.
Suite 116
Dollard Des Ormeaux. Quebec
Canada H9B 2K4

PUERTO RICO
Jose L. Puig
New England Technical Sales Corl
P.O. Box 8804
Ponce. Puerto Rico PR00732

919/876-9862

Tritek Sales. Inc.
21 E. Euclid Ave.
Haddonfield. NJ 08033

4161791-5922

TWX 610-492-2683

The Lyons Corp.
4615 N. Streetsboro Rd.
Richfield. Ohio 44286

OREGON
Northwest Marketing Assoc.
9999 SW. Wilshire S1.
Suite 124
Portland. OR 97225

NEW JERSEY
Datronix
1930 E. Marlton Pike
Executive News. Suite P-79
Cherry Hill. NJ 08003

Cantec Representatives Inc.
8 Strathearn Ave .• Unit 18
Brampton. Ontario
Canada LBT 4L8

513/278-0714

TWX 810-427-9103
NORTH CAROLINA
Conely & Associates. Inc.
4050 Wake Forest Road
Suite 102
Raleigh. NC 27609

WISCONSIN
Carlson Electronic' Sales
Associates. Inc.
Northbrook Executive Ctr.
10701 West North Ave.
Suite 12
Milwaukee. WI 53226

u.s.

AND CANADIAN DISTRIBUTORS

ALABAMA
Schweber Electronics
2227 Drake Avenue SW.
Suite 14
Huntsville, ALA 35805
205/882-2200
ARIZONA
Kierulff Electronics
4134 E. Wood St.
Phoenix, AZ. 85040
602/437-0750
TWX 910/951-1550

Schweber Electronics
11049 North 23rd Drive
Phoenix, AZ. 85029
602/997-4874
TWX 910/950-1174
CALIFORNIA
Arrow Electronics
2961 Dow Avenue
Tustin, CA 92680
714/838-5422
TWX 910-595-2860

Arrow Electronics
19748 Dearborn St.
Chatsworth, CA 91311
2131701-7500
TWX 910-493-2086
Arrow Electronics
9511 Ridgehaven Court
San Diego, CA 92123
619/565-4800
TWX 310/371-8757
Arrow Electronics
521 Weddell Dr.
Sunnyvale, CA 94086
4081745-6600
TWX 910/339-9371
Kierulff Electronics
2585 Commerce Way
Los Angeles, CA 90040
2131725-0325
TWX 910/580-3106
Kierulff Electronics
3969 E. Bayshore Rd.
Palo Alto, CA 94303
415/968-6292
TWX 910/379-6430
Kierulff Electronics
8797 Balboa Avenue
San Diego, CA 92123
619/278-2112
TWX 910/335-1182
Kierulff Electronics
14101 Franklin Avenue
Tustin, CA 92680
7141731-5711
TWX 910/595-2599
Schweber Electronics
17822 Gillette Avenue
Irvine, CA 92714
714/863-0200
TWX 910/595-1720
Schweber Electronics
3110 Patrick Henry Dr.
Santa Clara, CA 95050
4081748-4700
TWX 910/338-2043
COLORADO
Arrow Electronics
1390 S. Potomac Street
Suite 136
Aurora, CO 80012
303/696-1111
TWX 910/932-2999

Kierulff Electronics
7060 S. Tucson Way
Englewood, CO 80112
303/790-4444
TWX 910/932-0169
CONNECTICUT
Arrow Electronics
12 Beaumont Rd.
Wallingford, CT 06492
203/265-7741
TWX 710/476-0162

Kierulff Electronics
1536 Landmeier Rd.
Elk Grove Village, IL 60007
312/640-0200
TWX 910/222-0351

Kierulff Electronics
13 Fortune Drive
Billerica, MA 01865
617/935-5134
TWX 710/390-1449

Schweber Electronics
904 Cambridge Dr.
Elk Grove Village, IL 60007
312/364-3750
TWX 910/222-3453

Lionex Corporation
1 North Avenue
Burlington, MA 01803
617/272-9400
TWX 710/332-1387

INDIANA

Schweber Electronics
25 Wiggins Avenue
Bedford, MA 01730
617/275-5100
TWX 710/326-0268

Kierulff Electronics
165 N. Plains Industrial Rd.
Wallingford, CT 06492
203/265-1115
TWX 710/476-0450

Advent Electronics Electronics
8446 Moller
Indianapolis, IN 46268
317/872-4910
TWX 810/341-3228

Schweber Electronics
Finance Drive
Commerce Industrial Park
Danbury, CT 06810
203/792-3500
TWX 710/456-9405

Arrow Electronics
2718 Rand Road
Indianapolis, IN 46241
317/243-9353
TWX 810/341-3119

MICHIGAN
Arrow Electronics
3810 Varsity Drive
Ann Arbor, MI 48104
313/971-8220
TWX 810/223-6020

Pioneer Electronics
6408 Castleplace Drive
Indianapolis, IN 46250
317/849-7300
TWX 810/260-1794

Pioneer Electronics
13485 Stamford
Livonia, MI 48150
313/525-1800
TWX 810/242-3271

FLORIDA
Arrow Electronics
1001 NW. 62nd St.
Suite 108
Ft. Lauderdale, FL 33309
305m6-7790
TWX 510/955-9456

Arrow Electronics
50 Woodlake Dr.
Palm Bay, FL 32905
3051725-1480
TWX 510/959-6337
Kierulff Electronics
4850 N. State Road 7
Suite E
Ft. Lauderdale, FL 33319
305/486-4004
TWX 510/955-9801
Kierulff Electronics
3247 Tech Drive
St. Petersburg, FL 33702
813/576-1966
TWX 810/863-5625
Schweber Electronics
2830 North 28th Terrace
Hollywood, FL 33020
305/927-0511
TWX 510/954-0304
Schweber Electronics
181 Whooping Loop
Altamonte Springs, FL 32701
(Orlando)
305/331-7555

IOWA

Advent Electronics
682 58th Avenue
Court South West
Cedar Rapids, IA 52404
319/363-0221
TWX 910/525-1337
Arrow Electronics
1930 St. Andrews Dr., NE
Cedar Rapids, IA 52402
319/395-7230
Schweber Electronics
5270 North Park Place, N.E.
Cedar Rapids, IA 52402
319/373-1417
KANSAS

Schweber Electronics
Wycliff Commercial Center
10300 West 103rd Street
Suite 103 Building F
Overland Park, KS 66214
913/492-2921
MARYLAND

Arrow Electronics
4801 Benson Aven ue
Baltimore, MD 21227
301/247-5200
TWX 710/236-9005

GEORGIA
Arrow Electronics
2979 Pacific Drive
Norcross, GA 30071
404/449-8252
TWX 8101766-0439

Kierulff Electronics
825 D. Hammonds Ferry Road
Linthicum, MD 21090
301/636-5800
TWX 710/234-1971

Kierulff Electronics
5824 E. Peachtree Corner East
Norcross, GA 30092
404/447-5252
TWX 8101766-4527

Pioneer Electronics
9100 Gaither Road
Gaithersburg, MD 20877
301/921-0660
TWX 710/828-0545

Schweber Electronics
303 Research Drive, Suite 210
Norcross, GA 30092
404/449-9170
TWX 8101766-1592

Schweber Electronics
9218 Gaither Rd.
Gaitherbursg, MD 20877
301/840-5900
TWX 710/828-9749

ILLINOIS

MASSACHUSETTES
Arrow Electronics
Arrow Drive
Woburn, MA 01801
617/933-8130
TWX 710/393-6770

Arrow Electronics
2000 Algonquin Road
Schaumburg, IL 60195
312/397-3440
TWX 910/291-3544

11-17

Schweber Electronics
12060 Hubbard Ave.
Livonia, MI 48150
313/525-8100
TWX 810/242-2983
MINNESOTA
Arrow Electronics
5230 W. 73rd Street
Edina, MN 55435
612/830-1800
TWX 910/576-3125

Kierulff Electronics
7667 Cahill Rd.
Edina, MN 55435
612/941-7500
TWX 910/576-2721
Schweber Electronics
7424 W. 78th Street
Edina, MN 55345
612/941-5280
TWX 910/576-3167
MISSOURI
Arrow Electronics
2380 Sc h uetz Road
St. Louis, MO 63141
314/567-6888
TWX 9101764-0882

Kierulff Electronics
2608 Metro Park Blvd.
Maryland Heights, MO 63043
3141739-0855
TWX 9101762-0721
Olive Electronics
9910 Page Blvd.
St. Louis, MO 63132
314/426-4500
TWX 9101763-0720
Schweber Electronics
502 Earth City Expressway
Suite 203
Earth City, MO 63045
3141739-0526
Semiconductor Spec
3805 N. Oak Trafficway
Kansas City, MO 64116
816/452-3900
NEW HAMPSHIRE
Arrow Electronic
1 Perimeter Rd.
Manchester, NH 03103
603/668-6968
TWX 710/220-1684

Schweber Electronics
Farms Bld'g #2 1st Floor
Kilton & South River Road
Manchester, NH 03102
603/625-2550
TWX 710/220-7572
NEW JERSEY
Arrow Electronics
6000 Lincoln Drive East
Marlton, NJ 08053
609/596-8000
TWX 710/897-0829

Arrow Electronics
2 Industrial Rd.
Fairfield, NJ 07006
201/575-5300
TWX 7101734-4403
Kierulff Electronics
37 Kulick Road
Fairfield, NJ 07006
201/575-6750
TWX 7101734-4372
Schweber Electronics
18 Madison Road
Fairfield, NJ 07006
201/227-7880
TWX 7101734-4305
NEW MEXICO
Arrow Electronics
2460 Alamo Ave. S.E.
Albuquerque, NM 87106
505/243-4566
TWX 910/989-1679
NEW YORK
Add Electronic
7 Adler Drive
E. Syracuse, NY 13057
315/437-0300

Arrow Electronics
25 Hub Drive
Melville, NY 11747
516/391-1300
TWX 510/224-6155
Arrow Electronics
7705 Maltlage Drive
P.O. Box 370
Liverpool, NY 13088
315/652-1000
TWX 710/545-0230
Arrow Electronics
3000 S. Winton Road
Rochester, NY 14623
716/427-0300
TWX 510/253-4766
Arrow Electronics
20 Oser Ave.
Hauppauge, NY 11787
516/231-1000
TWX 510/227-6623
Lionex Corporation
400 Oser Ave.
Hauppauge, NY 11787
516/273-1660
TWX 510/227-1042
Schweber Electronics
3 Town Line Circle
Rochester, NY 14623
716/424-2222
Schweber Electronics
34 Jericho Turnpike
Westbury, NY 11590
516/334-7474
TWX 510/222-3660

•

u.s.

AND CANADIAN DISTRIBUTORS

NORTH CAROLINA
Arrow Electronics
938 Burke St.
Winston Salem, NC 27102

Schweber Electronics
7865 Paragon Road
Suite 210
Dayton, OH 45459

9191725-8711

513/439-1800

TWX 510/931-3169
Arrow Electronics
3117 Poplarwood Court
Suite 123, P.O. Box 95163
Raleigh, NC 27625
919/876·3132
TWX 510/928·1856

Hammond Electronics
2923 Pacific Avenue
Greensboro, NC 27406
919/275·6391
TWX 510/925·1094

KierulH Electronics
1 North Commerce Center
5249 North Blv'd.
Raleigh, NC 27604
919/872·8410
TWX 310/377-2204

Schweber Electronics
1 Commerce Center
5285 North Blv'd.
Raleigh, NC 27604
919/876·0000

TWX 510/928·0531
OHIO
Arrow Electronics
7620 McEwen Road
Centerville, OH 45459
513/435·5563
TWX 810/459·1611

Arrow Electronics
6238 Cochran Road
Solon, OH 44139
216/248·3990
TWX 810/427·9409

Kierulff Electronics
23060 Miles Road
Cleveland, OH 44128
216/587·6558

TWX 810/427-2282
Pioneer Electronics
4800 East 131st Street
Cleveland, OH 44105
216/587·3600

TWX 810/422-2211
Pioneer Electronics
4433 Interpoint Blvd.
Dayton, OH 45424
513/236·9900
TWX 810/459·1622

Schweber Electronics
23880 Commerce Park Road
Beachwood, OH 44122
216/464·2970
TWX 810/427·9441

OKLAHOMA
Arrow Electronics
4719 S. Memorial
Tulsa, OK 74745
918/665·7700

KierulH Electronics
12318 E. 60th St.
Tulsa, OK 74145
918/252-7537
TWX 910/845·2150

Quality Components
9934 East 21st South
Tulsa, OK 74129
918/664·8812

Schweber Electronics
4815 South Sheridan
Fountain Plaza
Suite 109
Tulsa, OK 74145
918/622-8000

OREGON
Arrow Electronics
10160 S.w. Nimbus Ave., F·3
Portland, OR 97223
503/684-1690

PENNSYLVANIA
Arrow Electronics
650 Seco Rd.
Monroeville, PA 15146
412/856·7000

TWX 7101797·3894
Pioneer Electronics
259 Kappa Drive
Pittsburgh, PA 15238
4121782·2300

TWX 7101795·3122
Pioneer Electronics
261 Gibraltar
Horsham, PA 19044
215/674-4000
TWX 510/665·6778

Schweber Electronics
231 Gibraltar Rd.
Horsham, PA 19044
215/441-0600
TWX 510/665·6778

Schweber Electronics
1000 R.I.D.C. Plaza
Suite 203
Pittsburgh, PA 15238
4121782-1600

SOUTH CAROLINA
Hammond Electronics
1035 Lowndes Hill Rd.
Greenville, SC 29602

Schweber Electronics
6300 La Calma Dr.
Suite 240
Austin, TX 78752

Prelco Electronics
480 Port Royal St. W.
Montreal 357 P.Q. H3L 2B9

803/233-4121

512/458-8253

Telex 05·82-7590

TWX 810/281-2233

Schweber Electronics
10625 Richmond
Suite 100
Houston, TX 77042
7131784-3600
TWX 910/881·4836

Prelco Electronics
215 Stafford Road
Nepean, Ontario K2E 7Kl

TEXAS
Arrow Electronics
10125 Metropolitan Dr.
Austin, TX 78758
512/835·4180

TWX 910/874-1348

UTAH

Arrow Electronics
13715 Gamma Road
Dallas, TX 75240

Arrow Electronics
4980 Amelia Earhart Dr.
Salt Lake City, UT 84116

214/386-7500

TWX 910/860-5377
Arrow Electronics
10899 Kinghurst Drive
Suite 100
Houston, TX 77099
713/530·4700

TWX 910/880-4439
Kierulff Electronics
3007 Longhorn Blv'd.
Suite 105
Austin, TX 78758

801/539-1135

Kierulff Electronics
2121 South 3600 West
Salt Lake City, UT 84119
801/973-6913
TWX 910/925-4072

WASHINGTON
Arrow Electronics
14320 NE 21st
Bellevue, WA 98005
206/643·4800

512/835·2090

TWX 910/444-3033

TWX 910/874-1359

Kierulff Electronics
1053 Andover Park East
Tukwila, WA 98188

Kierulff Electronics
9610 Skillman Ave.
Dallas, TX 75243

206/575-4420

214/343-2400
TWX 910/861-9149

TWX 910/444·2034

Kierulff Electronics
10415 Landsbury Dr.
Suite 210
Houston, TX 77099

WISCONSIN
Arrow Electronics
434 Rawson Avenue
Oak Creek, WI 53154

713/530-7030

TWX 910/880·4057
Quality Components
4257 Kellway Circle
Addison, TX 75001
214/387·4949

TWX 910/860-5459
Quality Components
2427 Rutland Drive
Austin, TX 78758
512/835·0220

4141764-6600
TWX 910/262·1193

Kierulff Electronics
2236 G.w. Bluemound Road
Waukesha, WI 53186
4141784-8160
TWX 910/265·3653
Schweber Electronics
150 Sunnyslope Road
Suite 120
Brookfield, WI 53005

TWX 910/874-1377

4141784-9020

Quality Components
1005 Industrial Blv'd.
Sugarland, TX 77478

CANADA
Prelco Electronics
7611 Bath Road
Mississauga, Ontario
Toronto L4T 3Tl

713/491-2255
TWX 910/880-4893

Schweber Electronics
4202 Beltway Drive
Dallas, TX 75234
214/661-5010
TWX 910/860-5493

'Franchised for USA and Canada excluding California for military products

11-18

416/678·0401

Telex 06·96·8915

514/389-8051

6131726-1800

R.A.E. Industrial
3455 Gardner Court
Burnaby, B.C. V5G 4J7
604/291-8866

TWX 610/929-3065
R.A.E. Industrial
11680 170th Street
Edmonton, Alberta T5S lJ7
403/451-4001

Telex 037·2653
Zentronics
155 Colonnade Rd.
Nepean, Ontario
K2E7Kl
613/226·8840

Zentronics
8 Tilbury Court
Brampton, Ontario
(Toronto) L6V 2L1
416/451-9600

Telex 06-97678
Zentronics
505 Locke St.
St. Laurent, Quebec
H4T IX7
5141735·5361
Telex 058-27535
Zentronics
590 Berry Street
Winnipeg, Manitoba R3H OSI
204m5·8661

Zentronics
564/10 Weber Street, N.
Waterloo, Ontario N2L 5C6
519/884-5700

Zentronics
11400 Brideport Road
Unit 108
Richmond, BC V6X IT2
604/273·5575

Zentronics
3300-14 Avenue, N.E. Bay #1
Calgary, Alberta T2A 6J4
403/272-1021

INTERNATIONAL SALES REPRESENTATIVES AND DISTRIBUTORS
ARGENTINA
Rayo Electronics S.R.L.
Belgrano 990, Pisos 6y2
1092 Buenos Aires,
Republic of Argentina
(38)-1779,
Telex: 122153 ANS BK RAYO
AUSTRALIA
Amtron Tyree Pty. Ltd.
176 Cope Street
Waterloo, N.S.w. 2017
Australia
(02) 69-89.666
Telex: 25643 ANS BK TYREE
BRAZIL
Cosele, Ltd.
Rua da Consolachao, 867 2 and
Conj 22
01301 Sao Paulo - Sp,
Brazil
(11) 259 3719/255 1733
Telex: 1130869 ANS BK CSLE BR

HONG KONG
CET
1402 Tung Wah Mansion
199 - 203 Hennessy Road
Wanchai, Hong Kong
(5) 729 376
Telex: 85148 ANS BK CET HX
ISRAEL
Telsys Ltd.
12 Kehilat Venetsia St.
69010 Tel-Aviv, Israel
(3) 494891-2, 494881-2
Telex: b32392
JAPAN
Systems Marketing, Inc.
Shin - kanda Bldg. 1-8-5 Kaji-cho
Chiyoda-ku
Tokyo 101, Japan
32542751
Telex: 25276 ANS BK SMITOK
FAX 3 254 3288

Tomen Electronics Corp.
2-1-1 Uchisaiwai - Cho
Chiyoda - Ku
Tokyo, Japan 100
(03) 506 3670
Telex: J23548 ANS BK TMELC
KOREA
Vine Overseas Trading Corp.
Room 308 Korea Electric
Association Bldg.
11-4, Supyo-Dong, Jung-Ku
CPO Box 3154
Seoul, Korea
(02) 266 1663
Telex: K24154 ANS BK VINEJO
Seoul Corp LTD.
CPO Box 5003
Seoul 100, Korea
(02) 752 6121
FAX (02) 754 1348
Telex: K28641 ANS BK SJLEE

NEW ZEALAND
E.C.S. Div. of Airspares
P.O. Box 1048
Airport Palmerston North,
New Zealand
(63) 77-407
Telex: 791 3766 ANS BK Airspare
3766 NZ
SINGAPORE
Dynamar International, LTD.
12 Lorong Bakar Batu Unit 05-11
Kolam Ayer-Industrial Park,
Singapore 1334
7476188
TLX RS26283
ANS BK DYNAMA
FAX 7472648

SOUTH AFRICA
Promilect
P.O. Box 56310
Pinegowrie, 2123,
Transvaal
789-1400
Telex: 424822
TAIWAN
Dynamar Taiwan Ltd.
P.O. Box 67 - 445
Taipei, Taiwan
(2) 541 8251
Telex: 11064 ANS BK 11064
DYNAMAR
FOR ALL OTHER COUNTRIES
Mostek Corporation
International Dept.
MS 2220
P.O. Box 110169
Carrollton, Texas 75006, USA
214/466-6000
Telex: 4630093 ANS BK MSTA
FAX 466 7602

INTERNATIONAL MARKETING OFFICES
EUROPEAN HEAD OFFICE
Mostek International
Av de Tervuren 270-272 Bte 21
B-1150 Brussels/Belgium
021762.18.80
Telex: 62011

GERMANY
PLZ 1-5 Mostek GmbH
Friedlandstrasse 1
D-2085 Quickborn
(04106) 2077178
Telex: 213685

FRANCE
Mostek France s.a.r.1.
35 Rue de Montjean
Z.A.C. Sud, Sentiers 504
F-94266 Fresnes Cedex
(1)666.21.25
Te lex: 204049

PLZ 6-7 Mostek GmbH
Schurwaldstrasse 15
D-7303 Neuhausen/Filder
(07158) 66.45
Telex: 72.38.86
PLZ 8 Mostek GmbH
Freischutzstrasse 92
D-8000 Munchen 81
(089) 95.10.71
Telex: 5216516

IRELAND
Mostek Ireland B.V.
Irish Sales Office
Snugboro Industrial Park
Blanchardstown, Co. Dublin
(1) 217333
Telex: 30958

SWEDEN
Mostek Scandinavia AB
Spjutvagen 7
S-17561 Jarfalla
Sweden
08-362820
Telex: 12997

ITALY
Mostek Italia SRL
Via F.D. Guerrazzi 27
1-20145 Milano
(02) 318.5337/349.2696
and 34.23.89
Telex: 333601

UNITED KINGDOM
Mostek U.K. Ltd.
Masons House,
1-3 Valley Drive
Kingsbury Road
London, NW.9
01-2049322
Telex: 25940

11-19

JAPAN
Mostek Japan KK
3 - 24 Sakuragaoka - Machi
Shibuya - ku
Tokyo 150
(03) 496 4221
TLX 78123686 ANS BK
MKJAPAN
FAX (03) 496 4787
FAR EAST
Mostek Asia LTD
Suite 613 - 617
Mount Parker House
1111 Kings Road
Hong Kong
Phone: 5-681157-9
Telex: 72585 MKHK HX
FAX 5 - 665450

•

EUROPEAN SALES REPRESENTATIVES AND DISTRIBUTORS
AUSTRIA
Transistor Vertrelbsges, mbH
Auhofstrasse 41 A
A-1130 Vienna
(0222) 829451, 829404
Telex: 0133738
DENMARK
Semicap APS
Alhambravej 3
DK-1826 Kobenhavn V

01-22.15.10
Telex: 15987
FINLAND
Insele Oy
Kumpulantie 1
SF-00520 Helsinki 52

90-750.600
Telex: 122217
FRANCE
Copel
Rue Fourny, Z.1.
B.P. 22, F·78530 BUC
(1) 956 10.18
Telex: 698965
Facen
110 Av de Flandre
F59290 Wasquehal. Nord
(20) 98.92.15
Branch Offices in:
Lille, lyon,
Nancy, Rouen, Strasbourg
Mecodis
33-35, Rue Pierre Brossolette
F-94000 Creteil
(1) 898.-1111
Telex: 231160

P.E.P.
541, Av. du General de Gaulle
F-92140 Clam art
(1)630.24.56
Telex: 204534

Ecker
Koenlgsberger Strasse 2
D-6120 Michelstadt
(06061) 2233
Telex: 4191630

Scaib
80 Rue d'Arcueil
SILIC 137
F-94523 Rungis Cedex
(1)-687.23.13
Telex: 204674
Branch offices;
Blanquefort, la Madeleine, lyon,
Meylan, Nantes

POSITRON GmbH
Benzstrasse 1
Postfach 100364
D-7016 Gerlingen/Stuttgart
(07156) 3560
Telex: 7245266
Branch Offices in:
Hamburg, Dusseldorf, Munchen

Sorhodis
150-152, Rue A. France
F-69100 Villeurbanne
(7) 855 0044
Telex: 380181
GERMANY
Dr Dohrenberg
Bayreuther Strasse 3
D-l000 Berlin 30
(030) 213.80.43
Telex: 0184860
Retron GmbH
Rodeweg 18
Postfac h 3143
3400 Goettingen
(0551) 9040
Telex: 96733
Branch Offices in:
Hannover, Frankfurt,
Stuttgart, Krailling
Raffel-Electronic GmbH
lochnerstrasse 1
D-4030 Ratingen 1
(02102) 280.24
Telex: 8585180

Matronic GmbH
Lichtenberger Weg 3
D-7400 Tubingen
(07071) 45031
Telex: 17707111
Dema-Electronic GmbH
Turkenstrasse 11
D-8000 Munchen 2
(089) 2724053
Telex: 0529345
ITALY
Comprel S.p.A.
via Ie Fulvio Testi 115
1-20092 Cinisello B. (Mi)

(02) 61.20.641/2/3/4/5
Telex: 332484
Branch Offices in:
Bologna, Civitanova Marche,
Firenze,
Vicenza, Roma, Torino
Kontron S.p.A.
Via Medici del Vascello.26
1-20138 Milano
(02) 50721
Telex: 312288
Branch Offices in:

Pad ova, Torino,
Modena, Roma, Genova

11-20

THE NETHERLANDS
Nijkerk Elektronlka BV
Drentestraat 7
NL - 1083 HK Amsterdam
(020) 462221
Telex: 11625

SWITZERLAND
Memotec AG
Gaswerkstrasse, 32
CH-4901 Langenthal
063-28.11.22
Telex: 68636

NORWAY
Satt Electronics AIS
P.O. Box 70
O.H. Bangs Vei 17
N-1322 Hovik
02-12.36.00
Telex: 72558

UNITED KINGDOM
Celdis Limited
37-39 Loverock Road
Reading
Berks RG 31 ED
0734-58.51.71
Telex: 8483770

PORTUGAL
Digicontrole lDA
Av. de Roma 105
Sexto Esq uerdo
1700 Lisboa
(19) 923924
Telex: 15084

Hill Electronics
290 Antrim Road
Belfast
(0232) 755611
Telex: 747103

SPAIN
Comelta S.A.
Emilio Munoz 41, ESC 1
Planta 1 Nave 2
Madrid-17
(01) 754 3001
Telex: 42007
Branch Office:
C. Pedro IV, 84-5 a Planta
Barcelona 5

(03) 300-7712

Pronto Electronic Systems Ltd
466-478 Cranbrook Road,
Gants Hill,llford
Essex lG2 6lE
01-554 62.22
Telex: 8954213
VSI Electronics (UK) ltd.
Roydonbury Industrial Park
Horsecroft Road
Harlow, Essex
CM195 BY
(0279) 35477
Telex: 81387

Telex: 51934
SWEDEN
Nordisk Elektronik AB
Box 27301
S-102 54 Stockholm
08-635040
Telex: 10547

Thame Components Ltd.
Thame Park Road
Thame,Oxon
OX93XD
084 421.31.46
Telex: 837917

1984/1985 MICROELECTRONIC DATA BOOK

B

UNITED

MEMORY
COMPONENTS

TECHNOLOGIES
MOSTEK

64K-BIT READ-ONLY MEMORY
MK36000(P/J/N) SERIES
FEATURES

o
o

o

MK36000 8K x 8 Organization"Edge Activated" * operation (CE)

Standard 24 pin DIP

o Low Power Dissipation - 220mW Max Active

Access Time/Cycle Time

PIN

Access

Cycle

MK36000-4

250ns

375 ns

MK36000-5

300 ns

450 ns

o

Low Standby Power Dissipation - 45mW Max, (CE High)

o On chip latches for addresses

o

Single +5V

± 10% Power Supply

o

Inputs and three-state outputs - TTL compatible

o

Outputs drive 2 TTL loads and 100pF

o

MKB version screened to MIL-STD-883

DESCRIPTION
enable (CE) input at a TTL high level. In this mode, power
dissipation is reduced to typically 45mW, as compared to
unclocked devices which draw full power continuously. In
system operation, a device is selected by the CE input, while
all others are in a low power mode, reducing the overall
system power. Lower power means reduced power supply
cost, less heat to dissipate and an increase in device and
system reliability.

The MK36000 is a N-channel silicon gate MOS Read Only
Memory, organized as 8192 words by 8 bits. As a state-ofthe-art device, the MK36000 incorporates advanced circuit
techniques designed to provide maximum circuit density
and reliabilitywith the highest possible performance, while
maintaining low power dissipation and wide operating
margins.
Use of a static storage cell with clocked control periphery
allows the circuit to be put into an automatic low power
standby mode. This is accomplished by maintaining the chip

The edge activated chip enable also means greater system
flexibility and an increase in system speed.

FUNCTIONAL DIAGRAM (MK36000)

PIN CONNECTIONS

2
3

24 vce
23 AS
22 Ag

A4 4
A3 5
A2 6
A1 7

21 A12
20 CE
19 A10
18 A11

A7 1

As
As

_ _ _ Vcc

--_Vss

Ao 8

17

°7

00

9

16

Os

°110

15
14
13

Os

~11

vss 12

a..
°3

PIN NAMES
CE

Address
Outputs
+5V
* Trademark of Mostek Corporation

111-1

~S
CE

GND
Chip Enable

•

ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Terminal Relative to Vss ........................................................ -1.0 V to +7 V
Operating Temperature TA (Ambient) ............................................................ O°C to + 70°C
Storage Temperature - Ceramic (Ambient) ..................................................... -65°C to +150°C
Storage Temperature - Plastic (Ambient) ...................................................... -55°C to +125°C
Power Dissipation .................................................................................. 1 Watt
'Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED DC OPERATING CONDITIONS6
(O°C :::;TA ::::; +70°C)

SYM

PARAMETER

Vcc

MIN

TYP

MAX

Power Supply Voltage

4.5

5.0

5.5

V

V il

Input Logic 0 Voltage

-1.0

0.8

V

V IH

Input Logic 1 Voltage

2.0

Vcc

V

UNITS NOTES
6

DC ELECTRICAL CHARACTERISTICS
(Vcc

= 5V ±10%) (O°C:::; TA :::; +70°C) 6

SYM

PARAMETER

ICC1

V cc Power Supply Current (Active)

ICC2

Vcc Power Supply Current (Standby)

II(l)

Input Leakage Current

IO(l)

Output Leakage Current

Val

Output Logic "0" Voltage
@ lOUT = 3.3 mA

VOH

Output Logic "1" Voltage
@ lOUT = -220 J.lA

MIN

TYP

MAX

UNITS NOTES

40

mA

1

8

mA

7

-10

10

j.LA

2

-10

10

j.LA

3

0.4

V

2.4

V

AC ELECTRICAL CHARACTERISTICS
(Vcc

= 5V ±10%) (O°C:::; TA :::; +70°C)6
-4

-5

SYM

PARAMETER

MIN

tc

Cycle Time

375

tCE

CE Pulse Width

250

t AC

CE Access Time

tOFF

Output Turn Off Delay

tAH

Address Hold Time Referenced to CE

60

75

ns

t AS

Address Setup Time Referenced to CE

0

0

ns

tp

CE Precharge Time

125

150

ns

NOTES:
1. Current is proportional to cycle rate. ICCl is measured at the specified
minimum cycle time. Data Outputs open.
2. VIN=OVt05.5V(VCC=5V)
3. Device unselected; VOUT = 0 V to 5.5 V
4. Measured with 2 TIL loads and 100 pF, transition times = 20 ns

111-2

5.

6.

MAX

MIN

MAX UNITS NOTES

450

ns

4

10000

ns

4

250

300

ns

4

60

75

ns

4

10000

300

Capacitance measured with Boonton Meter or effective capacitance
calculated from the equation:
C = ~ with 6. V = 3 volts

A minimum 2 ms time delay is required after the application of VCC (+5)
before proper device operation is achieved. IT must be at VIH for this time
period.
7. CE high.

CAPACITANCE

(O°C :::; TA :::; 70°C)
SYM

PARAMETER

CI
Co

TVP

MAX

UNITS

NOTES

Input Capacitance

5

8

pF

5

Output Capacitance

7

15

pF

5

TIMING DIAGRAM

~----------tc--------------------------~
CHIP ENABLE

ADDRESS

V

DATA OUTPUT

OH

- ____________

VOL -

DESCRIPTION (Continued)
The MK36000 features onboard address latches controlled
by the CE input. Once the address hold time specification
has been met, new address data can be applied in
anticipation of the next cycle. Outputs can be wire 'OR'ed
together, and a specific device can be selected by utilizing
the CE input with no bus conflict on the outputs. The CE
input allows the fastest access times yet available in 5 volt
only ROM's and imposes no loss in system operating
flexibility over an unclocked device.

Any application requIring a high performance, high bit
density ROM can be satisfied by the MK36000 ROM. This
device is ideally suited for 8 bit microprocessor systems
such as those which utilize the Z80. It can offer significant
cost advantages over PROM.
OPERATION
The MK36000 is controlled by the chip enable (CE) input. A
negative going edge at the CE input will activate the device
as well as strobe and latch the inputs into the on-chip
address registers. At access time the outputs will become
active and contain the data read from the selected location.
The outputs will remain latched and active until CE is
returned to the inactive state.

Other system oriented features include fully TIL compatible
inputs and outputs. The three state outputs, controlled by
the CE input, will drive a minimum of 2 standard TIL loads.
The MK36000 operates from a single +5 volt power supply
with a wide ±1 0% tolerance, providing the widest operating
margins available. The MK36000 is packaged in the
industry standard 24 pin DIP.

111-3

•

111-4

B

UNITED
TECHNOLOGIES
MOSTEK

MEMORY
COMPONENTS
64K-BIT MOS READ-ONLY MEMORY
MK37000(P/J/N) SERIES

FEATURES

o Organization; 8K x 8 Bit ROM - JEDEC Pinout

o

Mask ROM replacement for 2764 EPROM

o

o

No Connections allow easy upgrade to future
generation higher density ROMs

o

Low power dissipation: 220mW max active, 45mW
max standby

Pin compatible with Mostek's BYTEWYDETM Memory
Family

o Access Time/Cycle Time
PIN
MK37000-5

ACCESS
300 ns

MK37000-4

250 ns

CYCLE
450 ns
375 ns

o CE and OE functions facilitate Bus control
o MKB version screened to MIL-STD-883

DESCRIPTION
The MK37000 is a N-channel silicon gate MOS Read
Only Memory, organized as 8192 words by 8 bits. As a
state-of-the-art device, the MK37000 incorporates
advanced circuit techniques designed to provide
maximum circuit density and reliability with the highest
possible performance, while maintaining low power
dissipation and wide operating margins. The MK37000
is to be used as a pin/function compatible mask
programmable alternative to the 2764 8K x 8 bit
EPROM. As a member of the Mostek BYTEWYDE

Use of clocked control periphery and a standard static
ROM cell makes the MK37000 the lowest power 64K
ROM available. Active power is a mere 220mW while
standby (cr high) is only 45mW. To provide greater
system flexibility an output enable (OE) function has
been added using one of the extra pins available on the

FUNCTIONAL DIAGRAM (MK37000)

PIN CONNECTIONS

 0) ...... , ...................... OV
Operating temperature, T A (Ambient) ............ O°C to + 70°C
Storage temperature (Ambient)(Ceramic) ....... -65°C to + 150°C
Storage temperature (Ambient)(Plastic)
...... -55°C to + 125°C
Short circuit output current .......................... 50mA
Power dissipation .................................. 1 Watt

*Stresses greater than those listed under
"Absolute Maximum Ratings" may cause
permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the
operating sections of this specification
is not implied.
Exposure to absolute
maximum rating conditions for extended
periods may affect device reliability.

RECOMMENDED DC OPERATING CONDITIONS 4
(DOC ~ T A ~ 70°C) 1
PARAMETER

MIN

TYP

MAX

UNITS

VOO

Supply Voltage

10.8

12.0

13.2

volts

VCC

Supply Voltage

4.5V

5.0

5.5

volts

2,3

VSS

Supply Voltage

0

0

0

volts

2

VBB

Supply Voltage

-4.5

-5.0

-5.7

volts

2

VIHC

Logic 1 Voltage, RAS, CAS, WR ITE

2.4

7.0

volts

2

VIH

Logic 1 Voltage, all inputs except
RAS, CAS, WRITE

2.2

7.0

volts

2

VIL

Logic

-1.0

.8

volts

2

a Voltage, all inputs

DC ELECTRICAL CHARACTERISTICS 4
(O°C ~ TA ~ 70t)' (VOO = 12.0V ± 10%; VCC
PARAMETER

=

5.0V ± 10%; VSS

=

TYP

NOTES
2

OV; -5.7V ~ VBB ~-4.5V)
NOTES

MAX

UNITS

1001

Average VOO Power Supply Current

35

mA

5

1002

Standby VOO Power Supply Current

2

mA

8

1003

Average VOO Power Supply Current
during "RAS only" cycles

25

mA

ICC

VCC Power Supply Current

IBB

Average VBB Power Supply Current

150

f.1A

II (L)

Input Leakage Current (any input)

10

f.1A

7

IO(L)

Output Leakage Current

f.1A

8,9

VOH

Output Logic 1 Voltage
-5mA

VOL

Output Logic
3.2mA

MIN

mA

10
@

lOUT =

a Voltage @

lOUT =

6

volts

2.4
0.4

volts

NOTES
1.

TA is specified for operation at frequencies to tRC >tRC (min).
OperatIOn at higher cycle rates with reduced ambient temperatures
and higher power dissipation is permissible provided that all AC
parameters are met. See figure 2 for derating curve.

6.

J~cdi~PCeonnd~e~~e~Ut~~~~~a~il~~ i~u;~~~~~:4~~t5~lf ~~~~ ~~v~a~:ta
Out. At all other times ICC consists of leakage currents only.

7. All device pins at 0 volts except VBB which is at -5 volts and the
pin under test which is at +10 volts.

2. All voltages referenced to VSS'

8. Output is disabled (high-impedance) and ~ and CAS are both
at a logic 1. Transient Stabllization is required prior to measurement of this parameter.

3. Output voltage will swing from VSS to VCC when enabled,with
no output load. For purposes of maintaining data in standby mode,
VCC may be reduced to VSS without affecting refresh operations or
data retention. However, the VOH (min) specification is not
guaranteed in th is mode.

9. OV ~VOUT ~+ 10V.
10. Effective capacitance is calculated from the equation:

4. Several cycles are required after power-up before proper device
operation is achieved. Any 8 cycles which perform refresh are
adequate for this purpose.

C =

5. Current is proportional to cycle rate.1001 (max) is measured at
the cycle rate specified by tRC (min). See figure 1 for 1001 limits
at other cycle rates.

La
Lv

with

Lv

= 3 volts.

11. A.C. measurements assume tT

IV-2

= 5ns.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS(4, 11, 17)
(00 e:;;;;; TA:;;;;; 70° C)1 (Voo = 12 OV+- 10% Vec = 5 OV +
- 10% Vss = OV -5 7V:;;;;; VBB :;;;;;-4 5V)
I

I

I

MK4027-2

PARAMETER

MIN

MAX

MK4027-3
MIN

MAX

UNITS

NOTES

tRC

Random read or write cycle time

320

tRWC

Read write cycle time

tRMW
tpc

Read modify write cycle time

320
320

Page mode cycle time

170

tRAC

Access time from row address strobe

150

tCAC

Access time from column address strobe

100

tOFF

Output buffer turn-off delay

40

tRP

Row address strobe precharge time

100

tRAS

Row address strobe pulse width

150

tRSH

Row address strobe hold time

100

135

ns

tCAS

Column address strobe pulse width

100

135

ns

tCSH

Column address strobe hold time

150

tRCD

Row to column strobe delay

20

tASR

Row address set-up time

0

tRAH

Row address hold time

tASC

Column address set-up time

tCAH
tAR
tcsc

Chip select set-up time

tCH
tCHR
tT
tRCS

Read command set-up time

0

375
375

ns

12

ns
ns
ns

12
12
12

200

ns

13,15

135

ns

14,15

50

ns

405
225

120
10,000

50

200

200
25

ns
10,000

ns

ns
65

ns

0

ns

20

25

ns

-10

-10

ns

Column address hold time

45

55

ns

Column address hold time referenced to ~

95

120

ns

-10

-10

ns

Chip select hold time

45

55

ns

Chip select hold time referenced to RAS

95

Transition time (rise and fall)

3

120
35

3

16

ns
50

0

ns

17

ns

tRCH

Read command hold time

0

0

ns

tWCH

Write command hold time

45

55

ns

tWCR
twp

Write command hold time referenced to RAS

95

120

ns

Write command pulse width

45

55

ns

tRWL

Write command to row strobe lead time

50

70

ns

tCWL

Write command to column strobe lead time

50

70

ns

tDS

Data in set-up time

0

0

ns

18

tDH

Data in hold time

45

55

ns

18

tDHR

Data in hold time referenced to RAS

95

120

ns

tCRP
tcp

0

0

ns

Column precharge time

60

80

tRFSH

Refresh period

twcs

Write command set-up time

0

0

ns

19

tCWD

CAS to WFrTTt delay

60

80

19

tRWD

RAS to WR ITE delay

110

145

ns
ns

tDOH

Data out hold time

10

10

/...IS

Column to row strobe precharge time

2

Notes Continued

ns
2

ms

19

17. VIHC (Min) Qr VIH (min) and VIL (max) are reference levels for
measuring timing of input signals. Also, transition times are
measured between VIHC or VIH and VIL'

12. The specifications for tRC (min) and tRWC (min) are used only to

~~~~~~!er~~~~e(~Ir~ ; ; ;:'~t 7~~~: ~~s~::~~ns~~e;i~8~ef~I~~~';;~;a.

18. These parameters are referenced to CAS leading edge in random
write cycles and to ii\TRT'fE leading edge in delayed write or read·
modify·write cycles.

ting curve.

13. Assumes that tRCD :;;;;;tRCD (max).

19. twcs, tCWD' and tRWD are restrictive operating parameters in

14. Assumes that tRCD ~tRCD (max).

~h:~~~I:ii;ea~r :ae~~/:r~~/cY:~~i~~~y~~~aO~I~t ~if~~x?ai~v;'tfeSJ:~n),

15. Measured with a load circuit equivalent to 2 TTL loads and 100pF

written into the selected cell. If tCWD ~tCWD (min) and tRWD ~
tRWD (min), the cycle is a read·write cycle and Data Out will contain
data read from the selected cell. If neither of the above sets of conditions
is satisfied, the condition of Data Out (at access time) is indeterminate.

16. Operation within the tRyt;:> (max) limit insures that tR.AC (max)

~:~ ~e i:n;r~a:~1~a~~~~ s~e~~i~i~i~~ ~~ a( ~::,)e~~if.~'~:no~~~~~:
time is controlled exclusively by tCAC'

IV-3

AC ELECTRICAL CHARACTERISTICS

= 12.0V ± 10%; VSS = OV;-5.7V
..J
a..
a..

::l

en

",<;)

20mA

0

I-f- ,.- ~

E

~

...

~
~

UJ

1.1

lIZ

,

40

,

50

o

1.0

2.0

3.0

4.0

•

CYCLE RATE (MHz) = 103 /tCYC (ns)

~-t'l.

Figure 2. Maximum ambient temperature versus cycle rate
for extended frequency operation.

~

2.0

60

UJ

"
1.0

~

4027.1/2~t-

iii

/"~~, ~I'"

",<;)'J,'\

. MK

~

«

1

'II'

'"

:!:

I'

'1>'1.-';

I"X

I-

0:
:!:

250

300

IM~.40~7.~

«

~
I,0Il'"

')."

~+-

.

~

~"'~

..+'
S)Q~r"

~",~+-~-r-~

lOrnA

~

E

320

I 1
III J

400

3.0

4.0

CYCLE RATE (MHz) = 103 ItCYC (n5)

Figure 1. Maximum 1001 versus cycle rate for device
operation at extended frequencies.

IV-4

READ CYCLE
tRc----------------------~

V 1HC V 1L -

tCSH -----------

I --------------.t

t RCO ____-...11-------;-- tRSH ------------i~

VI~--------~~------------~ ~.-----~II--tCAS------~~ r---4~-----------­
V1L

ADDRESSES

cs

-

•

VV IHIL-

V 1H V 1L -

VOH-

DOUT

V OL-

EARLY WRITE

t RC

tAR

VIHCVIL -

----,
I
I
I

VIHC-

V 1L -

t RAS

t RSH
t CAS

V1H1L

ADDRESSES V

t

CHR
tcAC

-§ttRAC
VOH- - - _ _ _ _ _ _ _ _ _ _ _ _ _

V

OL

tOff

-

OPEN

IV-5

READ-WRITE / READ-MODIFY-WRITE CYCLE

14-0--------------- t

RWC/ tRMW --------------~

14---..!.--- t

RSH

------i~I__--'----- t CAS

---

tCSH---------~

ADDRESSES

DOUT

"RAS ONLY" REFRESH CYCLE
~----------1......_ - - -

tRC

tRAS

RAS
~-----tRP---~.~1

ADDRESSES

VIHVll-

NOTE: DOUT remains unchanged from previous cycle.

IV-6

PAGE MODE READ CYCLE
t RAS --------------------------------~~~
RAS

CAS

V1HCV 1L -

~-t-A-R

__
·...!...I_ _ _ _ _ _ _ _ _ _----,r

JF---------j~,':;}

V 1HCV 1L -

V 1H -

VIL-~LLLL~~~~~~-----L~~LLLL~~----~~~J~~-----£~~~LLLL~~LL~~~~

DOUT

VOH-

VALID
DATA

VOL-

WRITE

"7}L
~::CWI!/&

"Jt@L I,,,

t RCH
-f.f

Vt#$##/;;

PAGE MODE WRITE CYCLE
~-------------------------------tRAS------------------------------~
V IHCV1L -

V 1HC -

V IL -

1H
IL-

ADDRESSES VV -

DOUT

VO H -

VOL-----~-------+~------~~

'--------

IV-7

•

ADDRESSING
The 12 address bits required to decode1 of the 4096
cell locations within the MK 4027 are multiplexed
onto the 6 address inputs and latched into the on-chip
address latches by externally applying two negative
going TTL level clocks. The first clock, the Row
Address Strobe (RAS), latches the 6 row address
bits into the chiR. The second clock, the Column
Address Strobe (CAS), subsequently latches the 6
column address bits plus Chip Select (CS) into the
chip. The internal circuitry of the MK 4027 is designed to allow the column information to be externally applied to the chip before it is actually required.
Because of this, the hold time requirements for the
input signals associated with the Column Address
Strobe are also referenced to RAS. However, this
gated CAS feature allows the system designer to compensate for timing skews that may be encountered in
the multiplexing operation. ~nce the Chip Select
signal is not required until CAS time, which is well
into the memory cycle, its decoding time does not add
to system access or cycle time.
DATA INPUT/OUTPUT
Data to be written into a selected cell is latched into
C!!L9n-chip r~ter by a combination of WR ITE and
CAS while ~ is active. The later of the signals
(WRITE or CAS) to make its negative transition is
the strobe for the Data In register. This permits
several options in the write cycle timing. In a write
cycle, if the WR ITE input is br:Q!,!9ht low prior to
CAS, the Data I n is strobed by C~and the set-up
and hold times are referenced to CAS. If the data
input is not available at CAS time or if it is desired
that the cycle be a read-write cycl~he WR ITE
signal must be delayed until after l"A~. I n this
"delayed write cycle" the data input set-up and
hold times are referenced-.!Q the negative edge of
WRITE rather than to CAS. ~ illustrate this
feature, Data In is referenced to WRITE in the timing
diagram depicting the read-write and page mode
write cycles while the "early~ite" cycle diagram
shows Data In referenced to CASLNote that if the
chip is unselected (CS high at CAS time) WR ITE
commands are not executed and, consequently,
data stored in the memory is unaffected.
Data is retrieved from the memory in a read cycle
by maintaining WR ITE in the inactive or high state
throughout the portion of the memory cycle in which
CAS is active. Data read from the selected cell will
be available at the output within the specified access
time.
DATA OUTPUT LATCH
Any change in the condition of the Data Out Latch
is initiated by the CAS signal. The output buffer is
not affected by memory (refresh) cycles in wh ich
only the RAS signal is applied to the MK 4027.

IV-8

Whenever CAS makes a negative transition, the output will go unconditionally open-circuited, independent of the state of any other input to the chip. If
the cycle in progress is a read ,read-mod ify-write, or a
delayed write cycle and the chip is selected, then
the output latch and buffer will again go active and
at access time will contain the data read from the
selected cell. This output data is the same polarity
(not inverted) as the input data. If the cycle in
Illi2Qress is a write cycle (WRITE active low before
CAS goes low) and the chip is selected, then at access
time the output latch and buffer will contain the
input data. Once having gone active, the output will
remain valid until the MK 4027 receives the next
CAS neg~tise edge.
Intervening refresh cycles in
which a A is received (but no C7\S) will not cause
val id data to be affected. Conversely, the output
will assume the open-circuit state during any cycle
in which the MK 4027 receives a CAS but no RAS
signal (regardless of the state of any other inputs).
The output will also assume the~en circuit state in
normal cycles (in which both RAS and CAS signals
occur) if the chip is unselected.
The three-state data output buffer presents the data
output pin with a low impedance to VCC for a logic
1 and a low impedance to VSS for a logic O. The
output resistance to Vce (logic 1 state) is 420nmaximum and 135 n typically. The output resistance
to VSS (logic 0 state) is 125n maximum and 35 n
typicariy.
The separate VCC pin allows the output buffer to be powered from the supply voltage of
the logic to which the chip is interfaced. During
battery standby operation, the Vce pin may have
power removed without affecting tile MK 4027 refresh---.m2..eration. This allows all system logic except
the RAS timing circuitry and the refresh address
logic to be turned off during battery standby to
conserve power.
REFRESH
Refresh of the dynamic cell matrix is accomplished
by performing a memory cycle at each of the 64 row
addresses within each 2 millisecond time interval.
Any cycle in which a RAS signal occurs, accomplishes
a refresh operation. A read cycle will refresh the
selected ..Low, regardless of the state of the Chip
Select (CS) input.
A write or read-modify-write
cycle also refreshes the selected row, but the chip
should be unselected to prevent writing data into
the selected cell. If,.lli!ring a refresh .fYfle, the
MK 4027 receives a RAS signal but no CAS signal,
the state o.L.1be output will not be affected.~ow­
ever, if "RAS-only" refresh cycles (where RAS is
the only signal applied to the chip) are continued
for extended periods, the output buffer may eventually lose proper data and go open-circuit. The
output buffer will r~gain. activi.ty with th~ first
cycle in which a CAS Signal IS applied to the chip.

POWER DISSIPATION/STANDBY MODE
Most of the circuitry used in the MK 4027 is dynamic
and most of the power drawn is the resu It of an
address strobe edge. Because the power is not drawn
during the whole time the strobe is active, the
dynamic power is a function of operating frequency
rather than active duty cycle. Typically, the power
is 170mW at 1 f..L sec cycle rate for the M K 4027 with
a worse case power of less than 470mW at 320nsec
cycle time. To minimize t~verall system power,
the Row Address Strobe (RAS) should be decoded
and supplied to only the selected chips. The CAS
must be supplied to all chips (to turn off the unselected output). Those chips that did not receive
a R~ however, will not dissipate any power on
the CAS edges, exceRt for that required to turn off
the outputs. If the RAS signal is decoded and suppi ied on Iy to the selected ch ips, then the Ch ip Select
(CS) input of allsbips can bEL..91.a logic O. The chips
that receive a CAS but no RAS will be unselected
(output open-circuited) regardless of the Chip Select
input. For refresh cycles, however, eit~the CS
input of all chips must be high or the CAS input
must be held high to prevent several "wire-GRid"
outputs from turning on with opposing force. Note
that the MK 4027 will dissipate considerably less
power when the refresh operation is accomplished
with CRAS-only" cycle as opposed to a normal
RAS/CAS memory cycle.
PAGE MODE OPERATION
The "Page Mode" feature of the MK 4027 allows
for successive memory operations at mUltiple column
locations of the same row address with increased
speed without an increase in power. This is done by
strob.l.!:!.fL the row address into the chip and keeping
the RAS signal at a logic 0 throughout all successive
memory cycles in which the row address is common.

IV-9

This "page mode" of operation will not dissipate the
~~Ser associated with the negative going edge of
. Also, the time required for strobing in a new
row address is eliminated, thereby decreasing the
access and cycle times. The chip select input (CS)
is operative in page mode cycles just as in normal
cycles. It is not necessary that the chip be selected
during the first operation in a sequence of page
cycles. Likewise, the CS input can be used to select
or disable any cycle(s) in a series of page cycles.
This feature allows the page boundary to be extended
beyond the 64 column locations in a single chip.
The page boundary can be extended by applying
R'AS to multiple 4K memory blocks and decoding
C"S to select the proper block.
POWER UP
The MK 4027 requires no particular power supply
sequencing so long as the Absolute Maximum Rating
Conditions are observed. However, in order to insure
compliance with the Absolute Maximum Ratings,
MOSTEK recommends sequencing of power supplies
such that VBB is applied first and removed last.
VBB should never be more positive than VSS when
power is applied to VDD.
Under system failure conditions in which one or more
supplies exceed the specified limits significant additional margin against catastrophic device failure may
be achieved by forcing RAS and Data Out to the
inactive state.
After power is applied to the device, the MK 4027
requires several cycles before proper device operation
is achieved. Any 8 cycles which perform refresh are
adequate for this purpose.

•

TYPICAL DEVICE CHARACTER ISTICS
TYPICAL ADDRESS AND DATA INPUT LEVELS vs. VDD
3.0

e
TJ = 50 C

TJ = 50t
VBB =-5.0V

2.5

en
I-

TYPICAL CLOCK INPUT LEVELS vs. VDD
3.0
VBB =-5.0V

en
I-

2.5

o

~ 2.0

--

..J
W

~

>
W
1.5

..J

I::l

c..
Z

~

-

1.0

~

~

I----

~

0
~ 2.0

-

..J

VIH (MIN)

W

>
w

..J

1.5

VIL (MAX)

c..

~

VILC (MAX)
1.0

0.5
10

11
12
13
VDD SUPPLY VOLTAGE (VOLTS)

14

11

10

2.5

,I

e
T J = 50 C
VDD =12.0V,

TJ = 50t
2.5

VDD =12.0V

enI-

VIHC (MIN)

..J

02.0

..J

?

VIH (MIN)

W

..J

14

TYPICAL CLOCK INPUT LEVELS vs. VBB

2.0

>
W

13

3.0

..J

o
?

12

VDD SUPPL Y VOLT AG E (VOLTS)

TYPICAL ADDRESS AND DATA INPUT LEVELS vs. VBB
3.0

~

VIHC (MIN)
~

I::l

0.5

en
I-

---

..J

..J

..J
W

~

1.5

I::l

1.5

..J

c..

I::l

VIL (MAX)

~

0.5
- 4.0

-4.5
-5.0
-5.5
VBB SUPPLY VOLTAGE (VOLTS)

0.5

-6.0

-4.0

TYPICAL ADDRESS AND DATA INPUT LEVELS vs. TJ
3.0
VDD =12.0V
2.5

-6.0

-4.5
-5.0
-5.5
VBB SUPPLY VOL TAGE (VOLTS)

TYPICAL CLOCK INPUT LEVELS vs. TJ
3.0
iVDD =12.0V
VBB =-5.0V

VBB =·-5.0V

en
I-

en
I-

..J

o
?

VILC (MAX)

c..
~ 1.0

1.0

2.5

..J

o
?

2.0
VIH (MIN)

..J
W

2.0

-

..J
W

>

>
W

~ 1.5

..J

I::l

VIHC (MAX)
1.5

-

I::l

c..

z

c..

VIL (MAX)

~

-1.0

0.5
-10

-

VIL (MAX)

1.0

20
50
80
TJ, JUNCTION TEMPERATURE (eC)

0.5
-10

110

IV-10

20
50
80
TJ, JUNCTION TEMPERATURE (t)

110

TYPICAL ACCESS TIME (NORMALIZED) vs. VBB

TYPICAL ACCESS TIME (NORMALIZED) V5. VDD
1.2

1.2~------~------_r------_.------~

s;-

s;o

TJ = 50°C

o

~ 1.1

~

II

o

o

~ 1.0

TJ = 50°C

~ 1.11--------~-------4--------+-------~
II

~

~

a:

!Xl
!Xl

~

I-

~0.9

>

~ 1.0 I--------+-----+----+-------~

ex:
a:

~

t:

Ii! 0.9 ~------~------_4--------+_------~
!Xl

o

~

~

U

~O.S
a:

~O.SI--------~-------4--------+-------~
I-

I-

______ ______ ______ ______
-4.0
-4.5
-5.0
-5.5
-6.0

0.7

0.7~

10

11
12
13
VDD SUPPLY VOLTAGE (VOLTS)

14

~

1.2

i:l 1.1
Ln

u

t:

~-------4-----+-----~----~

u 1.0
ex:

[7

a:

ex:
a:

t:

=tu 0.9 1-------+--------+--------1-----------4

20.9
u

I-

/'

ex:
a:

~

u

~ O.S

1/

..,II

II

1.0

/'

U

TJ=50'C

U

~

TYPICALACCESS TIME (NORMALIZED)
vs JUNCTION TEMPERATURE

1.2

~ 1.1~------~-------+--------~----~

~U

~

VBB SUPPLY VOLTAGE (VOLTS)

TYPICAL ACCESS TIME (NORMALIZED) vs. VCC

$"

~

I-

I---------+-- ------+--------I---------l

O.S

I-

0.7
0.7 L..,-------....L-------""""""':----------".I..::---------,,-J
4.0
4.5
5.0
5.5
6.0
VCC SUPPLY VOLTAGE (VOLTS)

-10

50

so

110

TYPICAL IDD1 vs. JUNCTION TEMPERATURE

TYPICAL IDD1 vs. VDD
35

35~------~------_r------_.------~

~

20

TJ,JUNCTION TEMPERATURE (OC)

TJ = 50°C

130r-------~------~----~---+--------1
tRC = 320n5

I-

Z

-

w

~25r-------~--~~-q---------+--------1

--

:J

u

>
...J

~20r------=~------~--~--~~-------1

tRC

320ns

tRC

-

tRC
tRC

:J

en

375n5

--

500n5
600ns

o

915r-----~=r--------1--------~------_1

10~

10

___

~

____

~

___

~

___

11
12
13
VDD SUPPLY VOLTAGE VOLTS

10
-10

~

14

IV-11

20
50
SO
TJ, JUNCTION TEMPERATURE (OC)

110

•

'V-12

m

UNITED

MEMORY
COMPONENTS

TECHNOLOGIES
MOSTEK
4096

x 1-BIT DYNAMIC RAM

MK4027(J/N)-4

FEATURES

o

Industry standard 16-pin DIP (MK 4096)
configu ration

o

Improved performance with "gated CAS", "RAS
only" refresh and page mode capability

o

250ns access time, 380ns cycle

o

All inputs are low capacitance and TTL compatible

o ±10% tolerance on all supplies (+12\1, ±5V)

o Input latches for addresses, chip select and data in

o

o

ECl compatible on VSS power supply (-5.7V)

o low Power: 462mW active (max)
27mW standby (max)

Three-state TTL compatible output

o Output data latched and valid into next cycle
o MKB version screened to Mll-STD-883

DESCRIPTION
The M K 4027 is a 4096 word by 1 bit MOS random
access memory circuit fabricated with MOSTEK's
N-channel silicon gate process. This process allows
the M K 4027 to be a high performance state-of-theart memory circuit that is manufacturable in high
volume. The MK 4027 employs a single transistor
storage cell utilizing a dynamic storage technique
and dynamic control circuitry to achieve optimum
performance with low power dissipation.
A unique multiplexing and latching technique for
the address inputs permits the MK 4027 to be packaged in a standard 16-pin DIP on 0.3 in. centers. This
package size provides high system-bit densities and is
compatible with widely available automated testing
and insertion equ ipment.

System oriented features include direct interfacing
capability with TTL, only 6 very low capacitance
address lines to drive, on-chip address and data
registers which eliminates the need for interface
registers, input logic levels selected to optimize noise
immunity, and two chip select methods to allow the
user to determine the appropriate speed/power
characteristics of his memory system. The MK 4027
also incorporates several flexible operating modes. In
addition to the usual react and write cycles, readmodify write, page-mode I and FfAS-only refresh
cycles are available with the MK 4027. Page-mode
timing is very useful in systems requiring Direct
Memory Access (DMA) operation.

FUNCTIONAL DIAGRAM

PIN CONNECTIONS

I
Vee
2
DIN
WRITE 3
RAS 4

(° 1. '

DATA OUT

(Dour'

5

16 Vss
15

CAS

14 DOUT
13

CS

12

Ao
A2
AI

6

7

A3
II A4
10 A5

VOO

8

9 Vee

PIN NAMES
AO-A5

CAS

CS
DIN

~T
WRITE
VBB
VCC
VDD
VSS

IV-13

ADDRESS INPUTS
COLUMN ADDRESS STROBE
CHIP SELECT
DATA IN
DATA OUT
ROW ADDRESS STROBE
READ/WRITE INPUT
POWER (-5V)
POWER (+5V)
POWER (+ 12V)
GROUND

•

ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to VBB ..
-0.5V to +20V
Voltage on VDD, VCC relative to VSS ........... -1.0V to +15V
VBB-VSS (VDD-VSS > 0). . .. . . . . . . . . . . .
. .... , .... OV
Operating temperature, T A (Ambient) ............ O°C to + 70°C
Storage temperature (Ambient)(Ceramic) ....... -65°C to + 150°C
Storage temperature (Ambient)(Plastic)
..... -55°C to + 125°C
Short Circuit Output Current .......................... 50mA
Power dissipation .................................. 1 Watt

*Stresses greater. than those listed under
"Absolute Maximum Ratings" may cause
permanent damage to the device. This is
a stress rating only and functional opera·
tion of the device at these or any other
conditions above those indicated in the
operating sections of this specification
is not implied.
Exposure to absolute
maximum rating conditions for extended
periods may affect device reliability.

RECOMMENDED DC OPERATING CONDITIONS 4
(DOC ~ TA ~ 70°C) 1
PARAMETER

MIN

TYP

MAX

UNITS

VOO

Supply Voltage

10.8

12.0

13.2

volts

2

VCC

Supply Voltage

4.5V

5.0

5.5

volts

2,3

VSS

Supply Voltage

0

0

0

volts

2

VBB

Supply Voltage

-4.5

-5.0

-5.7

volts

2

VIHC

Logic 1 Voltage, RAS, CAS, WRITE

2.4

7.0

volts

2

VIH

Logic 1 Voltage, all inputs except
RAS, CAS, WRITE

2.2

7.0

volts

2

VIL

Logic 0 Voltage, all inputs

-1.0

.8

volts

2

NOTES

DC ELECTRICAL CHARACTERISTICS 4
(DoC ~ TA ~ 70"C)1 (VDD = 12.0V ± 10%; VCC = 5.0V ± 10%; VSS = OV; -5.7V ~ VBB ~-4.5V)
MAX

UNITS

1001

Average VOO Power Supply Current

PARAMETER

35

mA

5

1002

Standby VOO Power Supply Current

2

mA

8

1003

Average VOO Power Supply Current
during "RAS only" cycles

25

mA

ICC

VCC Power Supply Current

IBB

Average VBB Power Supply Current

150

fJ.A

II(L)

Input Leakage Current (any input)

10

fJ.A

7

IO(L)

Output Leakage Current

10

fJ.A

8,9

VOH

Output Logic 1 Voltage @ lOUT =
-5mA

VOL

Output Logic 0 Voltage @ lOUT =
3.2mA

MIN

TYP

mA

NOTES

6

volts

2.4
0.4

volts

NOTES
1.

T A is specified for operation at frequencies to tRC ~ tRC (min).

7. All device pins at 0 volts except VSS which is at -5 volts and the
pin under test which is at +10 voltS.

2. All voltages referenced to VSS'
8. Output is disabled (high·impedance) and ~ and CAS are both
at a logic 1. Transient stabilization is required prior to measure·
ment of th is parameter.

3. Output voltage will swing from VSS to VCC when enabled,with
no output load. For purposes of maintaining data in standby mode,

~aq; ::\~yn~~~~d~~:de~~r:ii,se ~i~~(~~~f)e~;~nC~f~~:~~~~ ~:~~~tions or

9. OV ~VOUT ~+ 10V.

guaranteed in th is mode.

10. Effective capacitance is calculated from the equation:
4. Several cycles are required after power·up before proper device
operation is achieved. Any 8 cycles which perform refresh are
adequate for this purpose.
5. Current is proportional to cycle rate.1001 (max) is measured at
the cycle rate specified by tRC (min). See figure 1 for 1001 limits
at other cycle rates.

6.

JcCcdi~~ea"nd~e~~e~Ut~r~~~~a~il~~ i~u;~~~~~:~~u3t5~t ~~~~ ~~v~a~:ta
Out. At all other times ICC consists of leakage currents only.

C ~

!:,.Q with!:" V ~ 3 volts.

I'w
11. A.C. measurements assume tT

~

5ns.

12. The specifications for tRC (min) and tRWC (min) are used only to indicate
cycle time at which proper operation over the full temperature range (0° .;;
TA';; 70°C) is assured.

IV-14

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS(4, 11, 17)
(00 e,,;;; T A";;; 70° C)1 (VDD = 12.0V± 10%, Vee = 5.0V ± 10%, VSS = OV, -5.7V";;; VBB ";;;-4.5V )
MK4027-4
PARAMETER

MIN

tRC

Random read or write cycle time

380

MAX

ns

12

tRWC

Read write cycle time

395

ns

tRMW

Read modify write cycle time

470

ns

12
12

tpc

Page mode cycle time

285

tRAC

Access time from row address strobe

tCAC

Access time from column address strobe

tOFF

Output buffer turn-off delay

12

ns

13,15

165

ns

14,15

60

ns

tRP

Row address strobe precharge time

120

tRAS

Row address strobe pulse width

250

tRSH

Row address strobe hold time

165

ns

tCAS

Column address strobe pulse width

165

ns

tCSH

Column address strobe hold time

250

ns

tRCD

Row to column strobe delay

tASR

Row address set-up time

tRAH

Row address hold time

tASC

Column address set-up time

tCAH

Column address hold time

35

NOTES

ns

250
0

UNITS

85

ns

ns

0

ns

35

ns

-10

ns

75

ns

tAR

Column address hold time referenced to RAS

160

ns

tcsc

Chip select set-up time

-10

ns

tCH

Chip select hold time

75

ns

tCHR

Chip select hold time referenced to RAS

tT

Transition time (rise and fall)

3

tRCS

Read command set-up time

0

160

16

ns

50

ns

17

ns

tRCH

Read command hold time

0

ns

tWCH

Write command hold time

75

ns

tWCR

Write command hold time referenced to RAS

160

ns

twp

Write command pulse width

75

ns

tRWL

Write command to row strobe lead time

85

ns

tCWL

Write command to column strobe lead time

85

ns

tDS

Data in set-up time

0

ns

18

tDH

Data in hold time

75

ns

18

tDHR

Data in hold time referenced to RAS

160

ns

tCRP

Column to row strobe precharge time

0

ns

tcp

Column precharge time

tRFSH

Refresh period

twcs

Write command set-up time

0

ns

19

tCWD

CAS to WRITE delay

90

ns

19

tRWD

RAS to WRITE delay

175

ns

19

tDOH

Date out hold time

10

J,Ls

Notes Continued
13. Assumes that tRCD ";;;tRCD (ma.·).
14. Assumes that tRCD ;;;'tRCD (max).
15. Measured with a load circuit equivalent to 2 TTL loads and 100pF
16. Operation within the tRCD (max) limit insures that tF\AC (max)
can be met. tRCD (max) is specified as a reference POint only; if
tRCD is greater than the specified tRCD (max) limit, then access
time is controlled exclusively by tCAC'

•

ns

10,000

110

ns

2

ms

17. VIHC (min) or VIH (min) and VIL (max) are.refere~ce ievels for
measuring timing of input signals. Also, transition times are
measured between VIHC or VIH and VIL'
18. These parameters are referenced to CAS leading edge in random
write cycles and to iiVRT'FE leading edge in delayed write or readmodify-write cycles.
19. twcs, tCWD' and tRWD are restrictive operating parameters in

.

~hree~~~I:ii~ea~r :ae~$/:r~~~f,;:~~i~~~Y6~~aO~I~t ~i~rb15~~~1tfeSJ~~n),

written into the selected cell. If tCWD ;;;'tCWD (min) and tRWD;;;'
tRWD (min), the cycle is a read-write cycle and Data Out will contain
data read from the selected cell. If neither of the above sets of conditions
is satisfied, the condition of Data Out (at access time) is indeterminate.

IV-15

AC ELECTRICAL CHARACTERISTICS
(O°C ..;;;TA ~ 70t) (VDD = 12.0V ± 10%; VSS

= OV ;-5.7V~VBB~-4.5V)
TYP

MAX

UNITS

C 11

Input Capacitance (AO-A5), DIN, CS

4

5

pF

10

C 12

Input Capacitance liAS, CAS, WRTiE:

8

10

pF

10

Co

Output Capacitance (DOUT)

5

7

pF

PARAMETER

MAXIMUM 1001 vs. CYCLE RATE FOR DEVICE OPERATION
AT EXTENDED FREQUENCIES
Figure 1

CYCLE TIME tCYC (ns)
380
400

500

1000

300

250

SOmA

«

40mA

.§.

....z

~'\ ~
~~
f.<.,v,

w

a::
a::
:::l

30mA

U

~,

>...J

:P

~~~

a..
a..

:::l

~~

CI)

0

~~~

20mA
f-- f-- f-

9

I-- I--

r7
10mA

o

1/

"

-<.--l~

~~./

..,"

o

j".

b<~'l,.~

~

I,,-

"

1.0

2.0

3.0

4.0

CYCLE RATE (MHz) = 103 /tCYC (ns)

SUPPLEMENT - To be used in conjunction with MK4027(J/N)-1 /2/3 data sheet.

IV·16

NOTES

8,10

B

UNITED

MEMORY
COMPONENTS

TECHNOLOGIES
MOSTEK

16,384
FEATURES
D Recognized industry standard 16-pin configuration from MOSTEK

x 1-BIT DYNAMIC RAM

MK4116(J/N/E)-2/3

D Read-Modify-Write, RAS-only refresh, and Pagemode capability
D All inputs TTL compatible,low capacitance, and

protected against static charge
D 128 refresh cycles
D ECl compatible on VBB power supply (-5.7V)

o MKB

version screened to MIL-STD-883

o JAN version available to MIL-M-3851 0/240

FUNCTIONAL DIAGRAM

jg

PIN CONNE;;ION:

~~(j~~~f)

WRITE

3

14

Dou'~

RAS

4

13

As

Ao

5

12

A2

6

II

AI

7

10

voo

8

9

PIN NAMES
ADDRESS INPUTS
COLUMN ADDRESS
,STROBE
DATA IN
DATA OUT
ROW ADDRESS STROBE

Available per MIL-STD-883 B. Mostek is qualified per JM38150 Class B.
IV-17

iiiiRTfE
VBB
Vee
VDD
VSS

READ/WRITE INPUT
POWER (-5V)
POWER (+5V)
POWER (+12V)
GROUND

•

ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to VB B . . . . . . . . . . . . . . . . . . . '. -O.5V to +20V
Voltage on Voo, Vee supplies relative to Vss .......... -1.0V to +15.0V
VBB-VSS (Voo-VSS >OV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OV
Operating temperature, T A (Ambient) . . . . . . . . . . . . . . . . . . . ooe to + 70t
0
Storage temperature (Ambient) Ceramic . . . . . . . . . . . . . . . -55°e to + 150 e
Storage temperature, (Ambient) Plastic ................... -55°C to +125°C
Short circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Watt
RECOMMENDED DC OPERATING CONDITIONS6
0
(Ooe tRC
(min). Operation at higher cycle rates with reduced ambient
temperatures and higher power dissipation is permissible, however, provided AC operating parameters are met. See figure 1
for derating curve.

2.

All voltages referenced to VSS'

3.

Output voltage will swing from VSS to VCC when activated with
no current loading. For purposes of maintaining data in standby

mode, VCC may be reduced to VSS without affecting refresh
operations or data rete.ntio~. However, the VOH (min) specification IS not guaranteed In th IS mode.

4.

1001,1003, and 1004 depend on cycle rate. See figures 2,3, and
4 for 100 limits at other cycle rates.

5.

~Cf~ 19~nl~VI~ ~~t~e0~~d i~~ ~~ nOe~ie~\~Or~~~~'a ~o~ i ~ ;:~~~~;

IV.18

(13512 typ) to data out. At all other times ICC consists of
leakage currents on Iy.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (6,7,8)
(0 'C:s;;; T A:S;;; 70 e) 1 (VDD = 12.0V ± 10%; Vee = 5.0V ± 10%, Vss = OV, VBB = -5.7V :::; VBB :::; -4.5V)
0

MK 411&-2

MK 4116-3

PARAMETER
Random read or write cycle time

SYMBOL

MIN

MIN MAX

tRC

Read-write cycle time

tRWC

375

ns

405

ns

9

225

ns

Read modify write cycle time

tRMW

320
320
320

Page mode cycle time

tpc

170

Access time from RAS

MAX

375

UNITS
ns

NOTES

9
9

tRAC

150

200

ns

9
10,12

Access time from CAS

tCAC

100

135

ns

11,12

Output buffer turn-off delay

tOFF

a

40

a

50

ns

13

Transition time (rise and fall)

tT

3

35

3

50

ns

8

RAS precharge time

tRP

100

120

RAS pulse width

ns

tRAS

150 10,000

200 10,000

ns

RAS hold time

tRSH

100

135

ns

CAS hold time

tCSH

150

200

ns

CAS pulse width

tCAS

100 10,000

135 10,000

ns

RAS to CAS delay time

tRCD

20

25

ns

CAS to RAS precharge time

tCRP

-20

-20

ns

Row Address set-up time

tASR

a

a

ns

tRAH

20

25

ns

Row Address hold time

50

65

14

Column Address set-up time

tASC

-10

-10

ns

Column Address hold time

tCAH

45

55

ns

tAR

95

120

ns

Read command set-up time

tRCS
tRCH

a
a

ns

Read command hold time

a
a

Write command hold time

tWCH

45

55

ns

Write command hold time referenced to RAS

tWCR

95

120

ns

Write command pulse width

twP

45

55

ns

Write command to RAS lead time

tRWL

Write command to CAS lead time

tCWL

50
50

70
70

ns

Data-in set-up time

tDS

a

a

ns

15

Data-in hold time

tDH

45

55

ns

15

Data-in hold time referenced to RAS

tDHR

95

120

ns

CAS precharge time (for page-mode cycle only)

tcp

60

Refresh period

tREF

Column Address hold time referenced to

WR ITE command set-up time

RAS

twcs

CAS to WRi'fr delay

tCWD

RAS to WR ITE delay

tRWD

NOTES (Continued)
Several cycles are required after power-up before proper device
6.
operation is achieved. Any 8 cycles which perform refresh are adequate
for this purpose.
7.
AC measurements assume tT = 5ns.
8.
VIHC (min) or VIH (min) and VIL (max) are reference levels for measuring
timing of input signals. Also transition times are measured between
VIHC or VIH and VIL.
9.
The specifications for tRC (min) tRMW (min) and tRWC (min) are used
only to indicate cycle time at which proper operation over the full
temperature range (O°C :S TA:S 70°C) is assured
10.
Assumes that tReD :StRCD (Max). If tRCD is greater than the maximum
recommended value shown in this table, tRAC will increase by the
amount that tRCD exceeds the value shown.
11.
Assumes that tRCD (max).
12.
Measured with a load equivalent to 2 TIL loads and 100pF.
tOFF (max) defines the time at"which the output achieves the open circuit
13.
condition and is not referenced to output voltage levels.

14.

15.

16.

17.

IV-19 18 .

ns

80

ns

2

2

-20
60
110

ns

-20
80
145

ms
ns

16

ns

16

ns

16

Operation within the tRCD (max) limit insures that tRAC (max) can be
met. tR'CD (max) is specified as a reference point only if tRCD is greater
than the specified tRCD (max) limit, then access time is controlled
exclusively by tCAC.
These parameters are referenced to CAS leading edge in early write
cycles and to WRITE leading edge in delayed write or read-modify-write
cycles.
tWCS, tCWD and -tRWD are restrictive operating parameters in read
write and read modify write cycles only. If tWCS 2 tWCS (min). the cycle
is an early write cycle and the data out pin will remain open circuit(high
impedance) throughout the entire cycle; If tCWD 2 tCWD (min) and
tRWD 2tRWD (min), the cycle is a read-write cycle and the data out will
contain data read from the selected cell; If neither of the above sets of
conditions is satisfied the condition of the data out (at access time) is
indeterminate.
Effective capacitance calculated from the equation C = 1 ill with /',V
= 3 volts and power supplies at nominal levels.
/', V
CAS = VIHC to disable DOUT.

•

AC ELECTRICAL CHARACTERISTICS
(DoC ~ T A ~ 70°C) (VOO = 12.0V ± 10%; VSS
PARAMETER

= OV; VBB = -S.7V ~ VBB ~ -4.SV)

SYMBOL

Input Capacitance (AO-A6), DIN

RAS, CAS, WRITE

Input Capacitance

Output Capacitance (DOUT)

MAX

UNITS

4

5

pF

CI2

8

10

pF

17

Co

5

7

pF

17,18

17

CYCLE TIME tRc(ns)

CYCLE TIME tRC(ns)

r

3711

1000

500

70

320

4001

I

I

fj

,,~

::E
w

60

~

~

!.

~

;;)

40mA

0

30mA

t

~

::E

0
E

<(

20mA

X

++~

3.0

.oI!!i .....
~

CYCLE RATE (MHz) = lol/tRC(ns)
~

Fig. 1 Maximum ambit:nt temperature versus cycle rate for extended

~

./

I'

.-+-

frequency operation. T A' (max) for operation at cycling rates greater
than 2.66 MHz (tCYC<.375ns) is determined by T A (max)o C
9,0 x

(cycle rate MHz -2.66) for -3. T A (max)

°c = 70 -

..:

- f--

1--

:IE

4.0

"

.~~

.
r-+- '- +-+-- ~I!
r-r-' -f-- ,,~I-~~ - '\~~~ .
r-- ~r-~~~~.,L
.

«

50

~~-

+T 9.~(j\:'l-.
_ .. ~
~~~

rz:

>

~

r

. ':1-

ffirz:

ai

2.0

.t7 ~-

-<. ~~ ' ./

~

w

1.0

t

. .1

tsr-

~o

300

.J
. f-

N

':/

lIZ

400

"'I':\)

~

500

50mA

I I
r~

"<
I-

1000

260

300

I

~

TA (MAX)

NOTES

TYP

Cll

- - f - "- - f-f-- I-f--

f--f---

= 701.0

9,0

3.0

2.0

4,0

CYCLE RATE (MHz) = 103 1 tRC(ns)

x cycle rate MHz -3.125MHz) for·2 only.
Fig.

2 Maximum '001 versus cycle rate for device operation at

extended frequencies. '001 (max) curve is defined by the equation:

CYCLE TIME tRC(ns)
1000

500

300

'001 (max) mA = 10 + 9.4 x cycle rate [MHz] fO.r

-3

'001 (max) mA = 10 + 8.0 x cycle rate [MHz] for

-2

250

CYCLE TIME tpC'(ns)

50mA

40mA

~

!.
~

~

\~

30mA

":Jfl~ ~
f>-+L~
~~;::~~

0

t

8

~

'v\~/

;;)

>

~

,:~~ ~t

20mA

--\O~~~-r-\'

P
X
«

.oIIiI~

:IE

"

IOmA

1

io"

f--I---

~:-

1

..."'"

40mA

-t-r+-+-+-t-++· c- ._,- . I--f--r-t--+--+-++-r-t+-+--+--++-f-+ +--j-+--+--+--+-+-~

r- _. --

I- - - -

"

.

1-1- - - .

30mA

,.

f·-

.-f-+-t-+-+-+-tr-t--+-+-r-t--+-1

+-t-+--+-+-I--+-+-+--f-- +- +-4 +-f--j-+--+-+--+-f---I

~,
,

,

I"

io"
0

.'

u

u

~

u

CYCLE RATE (MHz) .. 103 /tpc(ns)
Fig. 3 Maximum

'003 versus cycle rate for device operation at

extended frequencies. '003 (max) curve is defined by the eq~ation:
'003(max) mA
'003(max) mA

= 10 + 6.5 x
= 10 + 5.5 x

cycle rate [MHz] for -3
cycle rate [MHz] for

-2

Fig. 4 Maximum '004 versus cycle rate for device operation in page
mode.

'004

(max)

'004 (max) mA = 10

curve

is

defined

by

+ 3.75 x cycle rate [MHz] for -3

'004 (max) mA = 10 + 3.2 x cycle rate [MHz] for -2

IV-20

the

equation:

READ CYCLE
tRc----------------------~~

~-------------------------- tRAS--------~

RAS
I

--------------101

\4-------------------tCSH
______~----~I- tRSH

-----------t1~

14-------'-- t CAS -------t~

CAS

•

VIH_

ADDRESSES

WRITE

V

1L

-

V IHe-

I.---

v I L -.LJ.~u...L-I...L....i.-'t'~...........,

t CAC

-------t~

t RAC - - - - - - -_____--,

VOH
DOUT

- ___________________________

tOFF

VALID
DATA

OPEN
VOL -

WRITE CYCLE (EARLY WRITE)
~----------------------tRC

1 4 - - - - - - - - - - - - - - - t RAS --------------~

- - - - - - - - - t AR -------.__1

.....__-:--____ t RSH ----------~

~---------_-_-_-_-~-~~-~--t-cs7~~~~~~-t-CA-S----------------_~~~~

ADDRESSES

WRITE
t

I

RWL

I-- tOH

..I

V 1H -

DIN
tOHR

V OH -

DOUT

OPEN

V OL -

IV-21

READ-WRITE/READ-MODIFY-WRITE CYCLE
1 0 4 - - - - - - - - - t RWC/ tR M W - - - - - - - - - - . . j
RAS
14-----~- t RSH

----~

~~--I___t___tCSH-------.t

-~----'---- t CAS - - - - - - - . - . t

ADDRESS ES

~II ~~

DOUT

"RAS-ONL Y" REFRESH CYCLE

ADDRESSES

:',~=W$$#~ t'''AD~~~SS

=

Y;/m/&//////!II$I$////;m

VOH - _ _ _ _ _ _ _ _ O P E N - - - - - - - - -

IV-22

PAGE MODE READ CYCLE

t

RAS

------------------------~----~

~----------~~------------------------~(.~(------------I..

j'-

t RP

t RSH

..
- > - - - - t CRP
VI HC-_----;--.:-------.:h.

VIL -

I

ADDRESSES VV H

I L-

I

14-------- t RAC -------t-t-l-t
VOH-____________

DOUT

~I__

VOL-~tRCS:::1r4r__L_~~:F---r~b~
~II~?/III!/II!II

'<01/$II/ji//

PAGE MODE WRITE CYCLE

~-----------------------------tRAS ----------------------------~

ADDRESSES

IV-23

•

DESCRIPTION (continued)

prior to CAS, the DI N is strobed by C& and the
set-up and hold times are referenced to CAS. If the
input dqta is not available at CAS time or if it is
desired that the cycle be a read-write cy~ the
WRITE signal will be delayed until after CAS has
made its negative transition. In this "delayed write
cycle" the data input set-up and hold times are referenced to the negative edge of WR ITE rather than
CAS. (To illustrate this feature, DI N is referenced to
WR ITE in the timing diagrams depicting the readwrite and page-mode write cycles wh ile the "early
write" cycle diagram shows DIN referenced to CAS).

System oriented features include ± 10% tolerance on
all power supplies, direct interfacing capability with
high performance logic families such as Schottky
TTL, maximum input noise immunity to minimize
"false triggering" of the inputs (a common cause of
soft errors), on-chip address and data registers which
el iminate the need for interface registers, and two
chip select methods to allow the user to determine
the appropriate speed/power characteristics of his
memory system. The MK 4116 also incorporates
several flexible timing/operating modes. I n addition
to the usual read, write, and read-modify-write
cycles, the MK 4116 is capable -2Ldelayed write
cycles, page-mode operation and RAS-only-EJresh.
Proper control of the clock inputs(RAS, CAS and
WRITE) allows common I/O capability, two dimensional chip selection, and extended page boundaries
(when operating in page mode).

Data is retrieved from the memory in a read cycle
by maintaining WR ITE in the inactive or high state
throughout the portion of the memory cycle in which
CAS is active (low). Data read from the selected cell
will be available at the output within the specified
access time.

ADDRESSING

DATA OUTPUT CONTROL

The 14 address bits required to decode 1 of the
16,384 cell locations within the MK 4116 are multiplexed onto the 7 address inputs and latched into the
on-chip address latches by externally applying two
negative going TTL-le'£§.L1:locks. The first clock, the
Row Address Strobe (RAS), latches the 7 row address
bits into the chiR. The second clock, the Column
Address Strobe (CAS), subsequently latches the 7
column address bits into the chip. Each of these
signals, RAS and CAS, triggers a sequence of events
which are controlled by different delayed internal
clocks. The two clock chains are linked together
logically in such a way that the address multiplexing
operation is done outside of the critical path timing
sequence for read data access. The later events in
the CAS clock sequence are inhibited until~
occu rence of a delayed sign§!Jierived from the RAS
clock chain. This "gated CAS" feature allows the
CAS clock to be externally activated as soon as the
Row Address Hold Time specification (tRAH) has
been satisfied and the address inputs have been
changed from Row address to Column address
information.

The normal condition of the Data Output (DOUT)
of the MK 4116 is the high impedance (open-circuit)
state. That is to say, anytime CAS is at a high level,
the DOUT pin will be floating. The only time the
output will turn on and contain either a logic 0 or
logic 1 is at access time during a read cy'cle. DOUT
will remain valid from access time until CAS is taken
back to the inactive (high level) condition.

Note that CAS can be activated at any time after
tRAH and it will have no effect on the worst case
data access time (tRAC) up to the point in time when
the delayed row clock no longer inhibits the remaining sequence of column clocks. Two timing endpoints result from the internal gating of CAS wh ich
are called tRCD (min) and tRCD (mill No data
storage or reading errors will result if CAS is applied
to the MK 4116 at a point in time beyond the tRCD
(max) limit. However, access time will then be determined exclusively by the access time from CAS
(tCAC) rather than from RAS (tRAC), and access
time from RAS will be lengthened by the amount
that tRCD exceeds the tRCD (max) limit.
DATA INPUT/OUTPUT
Data to be written into a selected cell is latched into
an on·chip r~ter by a combination of WR ITE and
CAS while _R_AS is active. The later of the signals
(WR ITE or CAS) to make its negative transition is the
strobe for the Data In (DIN) register. This permits
several options in the write cycle tim ing. I n a write
cycle, if the WR ITE input is brought low (active)

If the memory cycle in progress is a read, read-modify
write, or a delayed write cycle, then the data output
will go from the high impedance state to the active
condition, and at access time will contain the dati
read from the selected cell. Th is output data is thf
same polarity (not inverted) as the input data. Onclhaving gone active, the output will remain valid until
CAS is taken to the precharge (logic 1) state,whether
or not RAS goes into precharge.
I~cycle in progresu an "early-write" cycle
(WRITE active before CAS goes active), then the
output pin will maintain the high impedance state
throughout the entire cycle. Note that with this
type of output configuration, the user is given full
control of the--'2o..uT pin simply by controlling the
placement of WRITE command during a write cycle,
and the pulse width of the Column Address Strobe
du ring read operations. Note also that even though
data is not latched at the output, data can remain
valid from access time until the beginning of a subsequent cycle without paying any penalty in overall
memory cycle time (stretching the cycle).

This type of output operation results in some very
significant system implications.
Common I/O Operation - If all write operations are
handled in the "early write" mode, then DIN can be
connected directly to DOUT for a common I/O data
bus.
Data Output Control - DOUT wil'---.@.main valid
during a read cycle from tCAC until CAS goes back
to a high level (precharge), allowing data to be valid
from one cycle up until a new memory cycle begins
with l]QJlenalty in cycle time. This also makes the
RAS/CAS clock timing relationship very flexible.
Two

IV-24

Methods of Chip Selection -

Since DOUT

is not latched, CAS is not required to turn off the
outputs of unselected memory devices in a matrix.
This means that both CAS and/or RAS can be decoded for chip selection. If both RAS and CAS are
decoded, them a two dimensionar (X,Y) chip select
array can be realized.
Extended Page Boundary
Page-mode operation
allows for successive memory cycles at mu Itiple
column locations of the same row address. By decoding CAS as a page cycle select signal, the page
boundary can be extended beyond the 128 column
locations in a single chip. (See page-mode operation).
OUTPUT INTERFACE CHARACTERISTICS'
The three state data output buffer presents the data
output pin with a low impedance to VCC for a logic
1 and a low impedance to VSS for a logic O. The
effective resistance to V CC (logic 1 state) is
420 n maximum and 135n typically. The resistance
to VSS (logic 0 state) is 95 n maximum and 35 n
typically. The separate VCC pin allows the output
buffer to be powered from the supply voltage of the
logic t(} which the chip is interfaced. During battery
standby operation, the VCC pin may have power
removed without affecting the MK 4116 refresh
operation. This allows all system logic except the
RAS timing circuitry and the refresh address logic to
be turned off during battery standby to conserve
power.
PAGE MODE OPERATION
The "Page Mode" feature of the MK 4116 allows for
successive memory operations at multiple column
locations of the same row address with increased
speed without an increase in power. This is done by
strobing the row address into the chip and maintaining the RAS signal at a logic 0 throughout all successive memory cycles in wh ich the row address is common. This "page-mode" of operation will not dissipate the~wer associated with the negative going
edge of RAS. Also, the time required for strobing
in a new row address is eliminated, thereby decreasing the access and cycle times.

POWER CONSIDERATIONS
Most of the circuitry used in the MK 4116 is dynamic
and most of the power drawn is the result of an
address strobe edge. Consequently, the dynamic
power is primarily a function of operating frequency
rather than active duty cycle (refer to the MK 4116
current waveforms in figure 5). This current characteristic of the MK 4116 precludes inadvertent
burn out of the device in the event that the clock
inputs become shorted to ground due to system
malfunction.
Although no particular power supply noise restriction
exists other than the supply voltages remain within
the specified tolerance limits, adequate decoupling
should be provided to suppress high frequency
noise reSUlting from the transient current of the
device. This insures optimum system perf~rmance
and reliability. Bulk capacitance requirements are
minimal since the MK 4116 draws very little steady
state (DC) current.
In system applications requiring lower power dissipation , the operating frequency (cycle rate) of the
MK 4116 can be reduced and the (guaranteed maximum) average power dissipation of the device will be
lowered in accordance with the 1001 (max) spec
limit curve illustrated in figure 2 .
NOTE: The
MK 4116 family is guaranteed to have a maximum
IDD1 requirement of 35mA @ 375ns cycle (320ns cycle
for the -2) with an ambient temperature range from 0°
to 70°C. A lower operating frequency, for example 1
microsecond cycle, results in a reduced maximum Idd1
requirement of under 20mA with an ambient
temperature range from 0° to 70°C.
It is possible the MK4116 family (-2 and 3 speed
selections for example) at frequencies higher than
specified, provided all AC operating parameters are met.
Operation at shorter cycle times «tRC min) results in
higher power dissipation and, therefore, a reduction in
ambient temperature is required. Refer to Figure 1 for
derating curve.
NOTE: Additional power supply tolerance has been included on the VBB
supply to allow direct interface capability with both -5V systems -5.2V Eel
systems.

The page boundary of a single MK 4116 is limited to
the 128 column locations determined by all combinations of the 7 column address bits. However, in
system applications which utilize more than 16,384
data words, (more than one 16K memory block), the
page boundary can be extended by using CAS rather
than RAS as the chip select signal. RAS is applied to
all devices to latch the row address into each device
and then CAS is decoded and serves as a page cycle
~elect sign~Only those devices which receive both
RAS and CAS signals will execute a read or write
cycle.

mICAs CYCLE

ffi/CAs

m

CYCLE

ONLY CYCLE

t

___ Jr

J

:r lJ

I

'('

II

/

/

"'-

I'-+-

REFRESH
Refresh of the dynamic cell matrix is accomplished
by performing a memory cycle at each of the 128
row addresses within each 2 millisecond time interval.
Although any normal memory cycle will perform the
refresh operation, this function is most easily accomplished with "RAS-only" cycles. RAS-only refresh
results in a substantial reduction in operating power.
This reduction in power is reflected in the 1003
specification.

LONG

r

~

I.\.

/\..

v

'1.

Ir

(~~~ +60

I

r

__ ..I)

V

i'I

1/

A.

1'1

1"-1-

III

11111

Llli

Jl~

IJ

\.

11
j

50 NANOSECONDS I DIVISION

'\.,

1
1'-V

Fig. 5 Typical Current Waveforms

IV-25

A

L

{

V

II'

/

~

_1 IA.

t..{\...

III

-"IA,

+80

fI f

Ii II<..

lin
f 1111
I'

If'I

U

•

Although RAS and/or CAS can be decoded and used
as a ch ip select signal for the M K 4116,overall system
power is minimized if the Row Address Strobe
(RAS) is used for this purpose. Al.L!!pselected devices (those which do not receive a RAS) will remain
in a lo~ower (standby) mode regardless of the
state of CAS.

such that VSS is applied first and removed last.
VSS should never be more positive than VSS when
power is applied to VDD.
Under system failure conditions in which one or more
supplies exceed the specified limits significant additional margin against catastrophic device failure may
be achievea by forcing RAS and CAS to the inactive
state (high level);

POWER UP
The MK 4116 requires no particular power supply
sequencing so long as the Absolute Maximum Rating
Conditions are observed. However, in order to insure:
compliance with the Absolute Maximum Ratings,
MOSTE K recommends sequencing of power suppl ies

After power is applied to the device, the MK 4116
requires several cycles before proper device operation
is achieved. Any 8 cycles which perform refresh
are adequate for this purpose.

TYPICAL CHARACTERISTICS

~

TYPICAL ACCESS TIME (NORMALIZEOI vs. Vaa

TYPICAL 1001 vS.VOD

1.2 TYPICAL ACCESS TIME (NORMALIZED) ~,. Vao

~

to'

tRC

~

~
'1'.1

375n5

TJ

=

50°C

~

2'.',0

~ 1.0

~

~

tAC=500 ru

If

~O.9

~O,9

~

IRc .. 75Qns

~0.8

~O.8f-----+---t----+--I
0·'''',0----",11-----,J'''-----.J.:,,--;-'
Vao SUPPLY VOLTAGE (VOLTS)

TYPICAL 'OD2VI

-

TJ=50'C

VBa SUPPLY VOLTAGE (VOLTS)

Vao

TYPICAL ACCESS TIME (NORMALIZEDlvs

TYPICAL I003vS Voo

Vee

I -----'---

1-

2:1.0

I

a:: 1.0

~O.8

VOOSUPPlYVOLTAGE (VOLTS)

I

I

1,·2

O·'~_'.-;;-O--.J.:---,+----,+---;!

1O':-=1O----,L11---:c":'---.,.::-,,-----"7.

~

t

~-

(j09

~
~08

~O.6

I
11

12

4,5

13

Vee

VOOSUPPLY VOLTAGE (VOLTS)

5.0

5.5

SUPPLY VOLTAGE {VOLTSI

TYPICAL IODJ vsJUNCTIQN TEMPERATURE

20

VOO"lJ.2V

i

118 TJ=SOC

l~th-O-----+'20:-----;;'!<-O--=~80----!

11

TJ,JUNCTIQN TEMPERATURE I"CI

TJ. JUNCTION TEMPERATURE I CI

TYPICAL CLOCK INPUT LEVELS VS.VOD

2.5

Voo SUPPL Y VOL TAGE (VOL TSI

TYPICAL CLOCK INPUT LEVELSvs

~~PICAL

Vaa

ADDRESS AND DATA INPUT LEVELS vs VOO

TJoSOC

3~;~;-i
I

18

2.S VpO
:

=

12.0V.

I VIHC (MIN;

VIHC (MINI

~

~'H'M'N'
~--+---VILC

~IL(MAX)

(MAXI

---

-;->----r---"""'"V;VILC (MAX)

05L----L-----:l:-----",------i
10

Vas SUPPLY VOLTAGE (VOLTS)

VOOSUPPLY VOLTAGE (VOLTS)

TYPICAL AOORUSANO DATA INPUT LEVELS

VI

20
50
80
TJ.JUNCTIONTEMPERATURE ( C)

Vas

I

30
TJ'50C

25~O_D--=-'?:?V

I
;;;

I

~20r------~-

--

I

V)H (MIN)

~ 15

i----+----i VIL (MAX)

~

05":-'."-0--,':--_-=-'.':-0--:-:,,:-----'-

1.0

20
50
ao
TJ.JUNCTIONTEMPERATURE ( C)

VSSSUPPLY VOLTAGE (VOLTS)

IV-26

O'7;-lO---,-,---,,;----~--!·
VppSUPPLY VOLTAGE (VOLTSI

B

UNITED
TECHNOLOGIES
MOSTEK

MEMORY
COMPONENTS
16,384 x 1-BIT DYNAMIC RAM
MK4116-53 (N)

FEATURES
o Recognized industry standard 16-pin configuration from
Mostek

o Read-Modify-Write, RAS-only refresh and Page-mode
capability

o 200 ns access time, 375 ns cycle
o Low power:

,4'~2

mW active, 20 mW standby (max)

/'/',:.::::,'? / i/'>
__
o Output da,:ta ¢,.~,Y9Uect. .,by CAS and unlatched at end of
l
cycle to all6w ,r\"vO"''''~fTensional chip selection and
extended pag'~ tip~ndahl<:""'"

,>

\", ;,.",,,,,,,...,,,,.."",l""

o Common I/O capability using "early write" operation

o All inputs TIL compatible, low capacitance, and
protected against static charge
o 128 refresh cycles

,~"\::~:t.,,),

",/l/,l'

DESCR IPTION<"'//

I' ":,::,~, """"

generatiQ:~:'i~:O~:::~,y'f\~miC

The MK4116 is a new
random
including sense amplifiers, assures that power dissipation
is minimized without any sacrifice in speed or operating
access memory circuit organized as 19":~'84 ~~rd~ by 1 bit.
margin. These factors combine to make the MK4116 a truly
As a state-of-the-art MOS memory d~~t£el)~,~,,:~~4116
superior RAM product.
(16K RAM) incorporates advanced clrcci'i"t/,:.,:rQ,!=¥'jques
designed to provide wide operating margins,'b6th)~te~na.uy
and to the system user, while achieving perform~,I'i'ce 17~,~14 i", Multiplexed address inputs (a feature pioneered by Mostek
in speed and power previously seen only in Mostek,;:~:""I"i'ig~/""::://~""".f.!;?r its 4K RAMs) permits the MK4116 to be packaged in a
performance MK4027 (4K RAM).
"
1>",""'/'/;('St~Qdard 16-pin DIP. This recognized industry standard
""/,::~::"'.,::::"""":::Q,~~'~i3;ge configuration, while compatible with widely
The technology used to fabricate the MK4116 is Mostek's '···'·. .,::::::>av,?'h~~1·~::' automated testing and insertion equipment,
double-poly, N-channel silicon gate, POLY IFM process. This
P~:~~:k!:~~'''P',~9:J'~est possible system bit densities and simplifies
process, coupled with the use of a single transistor dynamic
syst~frj:,:t:J'pgraqe,·,trom 4K to 16K RAMs for new generation
storage cell, provides the maximum possible circuit density
apPli~ation~.,l~6hT~ritical clock timing requirements allow
and reliability, while maintaining high performance
use of the<~::t.Jltipr¢<,i,J"19,. technique while maintaining high
capability. The use of dynamic circuitry throughout,
performand~':,::.:,:::::,:"",·<. ,,/',,:,,::""""'::,>.,::'

i

"","" li'\~,~",:""~\~ I"",

PIN CONN ECTIOt\!.~ ::. " \.S,"'·")~"'l

FUNCTIONAL DIAGRAM

V

--'"
--''"
--'"

.

',-"--~
',--~

',-'o--~

I

BB

DIN,

2

WRITE

3

RAS

4

Ao

5

A2

6

A1

7

Voo

8

PIN NAMES
Ao -A6 Address Inputs
CAS
Column Address
Strobe
Data In
DIN
Data Out
Dour
Row Address Strobe
RAS
IV-27

WRITE
V BB

vee
V DD

vss

Read/Write Input
Power (-5 V)
Power (+5 V)
Power (+12 V)
Ground

ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to V BB ..............•......•........•••...•........•........•...•.. -0.5 V to +20 V
Voltage on V oo , VCC supplies relative to Vss .........•...•..........•.•.•.......•......•••.... -1.0 V to +15.0 V
V BB - V ss (V DO - V ss > 0 V) .•...•••...........•....•........................•.............••..•......... 0 V
Operating Temperature, TA (Ambient) .................•..........••.............•..•..•.•........ O°C to +55°C
Storage Temperature (Ambient) (Ceramic) .•....•.•.................•.......................... -65°C to +150°C
Storage Temperature (Ambient) (Plastic) .....................•................................. -55°C to +125°C
Short Circuit Output Circuit ...•.....................................•........... " .................... 50 mA
Power Dissipation .•.•....................•...............................•......•.................. 1 Watt
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS
(O°C :::; TA:::; 55°C)

SYM

PARAMETER

MIN

TYP

MAX

UNITS

NOTES

Voo
VCC
Vss
V BB

Supply Voltage

10.8
4.5
0
-4.5

12.0
5.0
0
-5.0

13.2
5.5
0
-5.7

V
V
V
V

1
1,2
1
1

V IHC

Input High (Logic 1) Voltage,
RAS, CAS, WRITE

2.4

-

7.0

V

1

V IH

Input High (Logic 1) Voltage,
all inputs except RAS, CAS,
WRITE

2.2

-

7.0

V

1

V IL

Input Low (Logie 0) Voltage,
all inputs

-1.0

-

0.8

V

1

MAX

UNITS

NOTES

35

mA

3
4

200

J.1.A

-10

1.5
10
100

mA
J.1.A
J.1.A

-10

27
10
200

mA
J.1.A

J.1.A

DC ELECTRICAL CHARACTERISTICS
O°C :::;TA :::; 55°C) (Voo

= 12.0 V ± 10%; Vcc = 5.0 V ± 10%; V BB =-5.0 V ± 10%; Vss =0 V)

SYM

PARAMETER

1001
ICC1
IBB1

OPERATING CURRENT
Average power supply operating current
(RAS, CAS cycling; t RC = 375 ns)

1002
ICC2
IBB2

STANDBY CURRENT
Power supply standby current (RAS
DOUT = High·lmpedance)

1003
ICC3
IBB3

REFRESH CURRENT
Average power supply current, refresh mode
(RAS cycling, CAS =V IH 6 t RC = 375 ns

II(L)

INPUT LEAKAGE
Input leakage current, any input
(V BB = -5 V, 0 V:::; V IN :::; +7.0 V, all other
pins not under test = 0 volts)

-10

10

IO(L)

OUTPUT LEAKAG E
Output leakage current (DOUT is disabled,
V :::;VOUT :::; +5.5 V)

-10

10

J.1.A

0.4

V
V

MIN

=V IHC'

3

J.J.A

o
V OH
VOL

OUTPUT LEVELS
Output high (Logic 1) voltage (lOUT = -5 mAl
Output low (Logic 0) voltage (lOUT =4.2 mAl

IV-28

2.4

3

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS 5,6,7
(O°C::; TA ::; 55°C) (Voo

= 12.0 V ±

10%; VCC

= 5.0 V ±

10%, VSS

= 0 V, VB = -5.0 V ±

10%)

MK4116-53**
SYM

PARAMETER

MIN

t RC

Random read or write cycle time

t RWC

MAX

UNITS

NOTES

375

ns

17

Read-write cycle time

375

ns

17

tRMW

Read Modify Write

405

ns

t RAC

Access time from RAS

200

ns

8,10

t CAC

Access time from CAS

135

ns

9,10

tOFF

Output buffer turn-off delay

0

50

ns

11

tr

Transition time (rise and fall)

3

50

ns

7

t RP

RAS precharge time

120

tRAS

RAS pulse width

200

t RSH

RAS hold time

135

tCAS

CAS pulse width

135

tCSH

CAS hold time

200

t RCO

RAS to CAS delay time

25

t CRP

CAS to RAS precharge time

-20

ns

t ASR

Row Address set-up time

0

ns

tRAH

Row Address hold time

25

ns

t ASC

Column Address set-up time

-10

ns

tCAH

Column Address hold time

55

ns

tAR

Column Address hold time referenced to RAS

120

ns

t RCS

Read command set-up time

0

ns

t RCH

Read command hold time

0

ns

t WCH

Write command hold time

55

ns

tWCR

Write command hold time referenced to RAS

120

ns

twp

Write command pulse width

55

ns

t RWL

Write command to RAS lead time

70

ns

tCWL

Write command to CAS lead time

70

ns

tos

Date-in set-up time

0

ns

13

tOH

Date-in hold time

55

ns

13

ns
10000

ns
ns

10000

ns
ns

65

ns

12

**This device can be operated at an ambient temperature of 70°C if the refresh interval is changed to 128 refresh cycles
every 1.1 ms.

IV-29

•

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (5,6,7)
(O°C :STA:S 55°C) (Voo

= 12.0 V ± 10%; Vee = 5.0 V ±

10%, VSS

=0

V, V BB

= -5.0 V ± 10%)

MK4116-53**
SYM

PARAMETER

MIN

tOHR

Date-in hold time referenced to

tREF

Refresh Period

twcs

WRITE command set-up time

t cwo

CAS to WRITE delay

t RWO

RAS

RAS

MAX

2

NOTES:
1. All voltages referenced to Vss.
2. Output voltage will swing from VSS to VCC when activated with no current
loading. For purposes of maintaining data in standby mode, VCC may be reduced
to VSS without affecting refresh operations or data retention. However, the VOH
min specification is not guaranteed in this mode.
3. 10D1 and 1003 depend on cycle rate. The maximum specified current values are
for tRC = 375 ns. 100 limit at other cycle rates are determined by the following
equations:
10D1 (max) [MA] = 10 + 10.25 x cycle rate [MHz]
1003 (max) [MA] = 10 + 7 x cycle rate [MHz]
4. ICC1 depends upon output loading. During readout of high level data VCC is
connected through a low impedance (135 typ) to data out. At all other times ICC
consists of leakage currents only.
5. Eight cycles are required after power-up or prolonged periods (greater than 2 ms)
of RAS inactivity before proper device operation is achieved. Any 8 cycles which
perform refresh are adequate for this purpose.
6. AC measurements assume IT = 5 ns.
7. VIHC(min) orVIH (min) andVIL (max) are reference levels for measuring timing of
input signals. Also, transition times are measured between VIHC or VIH and VIL.
8. Assumes that tRCD :s tRCD (max). If tRCO is greater than the maximum
recommended value shown in this table, tRAC will increase by the amount that
tRCO exceeds the value shown.

NOTES

ns

120

to WRITE delay

UNITS

ms

-20

ns

14

80

ns

14

145

ns

14

9. Assumes that tRCD ::0: tRCO (max).
10. Measured with a load equivalent to 2 TTL loads and 100pF.
11. tOFF (max) defines the time at which the output achieves the open circuit
condition and is not referenced to output voltage levels.
12. Operation within the tRCO (max) limit insures that tRAC (max) can be met. tRCD
(max) is specified as a reference point only; if tRCO is greater than the specified
tRCO (max) limit. then access time is controlled exclUSively by tCAC'
13. These parameters are referenced to CAS leading edge in early write cycles and to
WRITE leading edge in delayed write or read-modify-write cycles.
14. twcs, tcwo and tRWO are restrictive operating parameters in read-write and
read-modify-write cycles only. If twcs ::0: twcs (min), the cycle is an early write
cycle and the data out pin will remain open circuit (high impedance) throughout
the entire cycle; if tcwo ::0: tCWD (min) and tRWD ::0: tRWO (min), the cycle is a
read-write cycle and the data out will contain data read from the selected cell: if
neither of the above sets of conditions is satisfied the condition of the data out (at
access time) is indeterminate.
15. Effective capacitance calculated from the equation C = !Ql with LW=3 volts
and power supplies at nominal levels.
!c,V
16. CAS =VIHC to disable DOUr17. The specifications for tRC (min) and tRWC (min) are used only to indicate cycle
time at which proper operation over the full temperature range (O°C:STA:S 55°C)
is assured.

AC ELECTRICAL CHARACTERISTICS
(O°C:S T A:S 55°C) (VOO

=

12.0 V

SYM

PARAMETER

Cl1

±

10%, VSS

=

OV; V BB

=

-5.0 V

±

10%)
TYP

MAX

UNITS

NOTES

Input Capacitance (Ao-A6 ), DIN

4

5

pF

15

C I2

Input Capacitance RAS, CAS, WRITE

8

10

pF

15

Co

Output Capacitance (D ouT )

5

7

pF

15,16

DESCRIPTION (Continued)

System

oriented

features

include

direct

interfacing

speed/power characteristics of this memory system. The

capability with high performance logiC families such as

MK4116

Schottky TIL, maximum input noise immunity to minimize

operating modes. In addition to the usual read, write, and

also

incorporates

several

flexible

timing/

"false triggering" of the inputs (a common cause of soft

read-modify-write cycles, the MK4116 is capable of delayed

errors), on-chip address and data registers which eliminate

write cycles, and RAS-only refresh. Proper control of the

the

clock inputs (RAS, CAS and WRITE) allows common I/O

need for

interface registers,

and two chip select

methods to allow the user to determine the appropriate

capability, and two dimensional chip selection.

IV-30

m

UNITED

TECHNOLOGIES
MOSTEK

MEMORY
COMPONENTS
16,384 x 1-BIT DYNAMIC RAM
MK4516(N/J)-9

FEATURES

o

Recognized industry standard 16-pin configuration from
Mostek

o

Common 110 capability using "early write"

o

Read, Write, Read-Write, Read-Modify-Write and PageMode capability

o

All inputs TTL compatible, low capacitance, and
protected against static charge

o

Single +5 V (± 10%) supply operation

o

On chip substrate
performence

o

Scaled POLY 5 technology

o

Active power 193 mW maximum
Standby power 20 mW maximum

o

Pin compatible with the MK4564 (64K RAM)

90 ns access time, 200 ns cycle time

o

128 refresh cycles (2 msec)

o

bias

generator for

optimum

DESCRIPTION
The MK4516 is a single +5 V power supply version of the
industry standard MK4116, 16,384 x 1 bit dynamic RAM.
The high performance features of the MK4516 are
achieved by state-of-the-art circuit design techniques as
well as utilization of Mostek's "Scaled POLY 5" process
technology. Features include access times starting where
the current generation 16K RAMs leave off, TTL
compatability, and +5 V only operation.
The MK4516 is capable of a variety of operations including
READ, WRITE, READ-WRITE, READ-MODIFY-WRITE,
PAGE MODE, and REFRESH.

The compatibility with the MK4564 will also permit a
common board design to service both the MK4516 and
MK4564 (64K RAM) deSigns. Therefore, the MK4516 will
permit a smoother transition to the 64K RAM, as the
industry standard MK4027 did for the MK4116.
The user requiring only a small memory size need no longer
pay the three power supply penalty for achieving the
economics of using dynamic RAM over static RAM when
using this new generation device.
DUAL IN-LINE PACKAGE PIN OUT
Figure 1

The MK4516 is designed to be compatible with the JEDEC
standards for the 16K x 1 dynamic RAM. The MK4516 is
intended to extend the life cycle of the 1 6K RAM, as well as
create new applications due to its superior performance.

N/C 1
DIN (D) 2

WRiTE(W) 3
RAS(RE) 4
Ao 6
A2 6
A17

PIN FUNCTIONS

(Fie)

Ao·Ae
CAS (CE)

Address Inputs

RAS

Col. Address Strobe

WR'iTe fih Read/Write Input

Row Address Strobe

DIN (D)

Data In

N/C

Not connected

Dour (0)

Data Out

Vee

Power (+6V)

Vss

GND

Vee B

Available soon in MIL·STD·883 Class B (MKB4616)

IV-31

16
16
14
13

Vss

CAS (CE)
Dour(Q)
As

12 A3
11 A4
10 All
9 N/C

•

ABSOLUTE MAXIMUM RATINGS*
Voltage on Vee Supply Relative to Vss ............................................•..•....•••. -1.0 V to +7.0 V
Operating Temperature, TA (Ambientl ............................................................. O°C to + 70°C
Storage Temperature (Ceramicl ......•.....•...•...................•........••.......•.•..... -65°C to +150°C
Storage Temperature (Plasticl .......•.................•........................•............ -55°C to +125°C
Power Dissipation .•....................••...........•...............................•....•.•..•.... 1 Watt
Short Circuit Output Current .•......•...............•.•..•.............•...••..................••.... 50 mA
'Stresses greater than those listed under "Absolute Meximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated In the operational sections of this specification is not Implied. Exposure to absolute
maximum rating conditions for extended periods may affect rallability.

RECOMMENDED DC OPERATING CONDITIONS
(O°C S TA S 70 0 q
SYM

PARAMETER

MIN

TYP

MAX

UNITS

NOTES

Vee

Supply Voltage

4.5

5.0

5.5

V

2

V IH

Input High (Logic 11 Voltage,
All Inputs

2.4

-

Vec +1

V

2

V IL

Input Low (Logic 01 Voltage,
All Inputs

-2.0

-

0.8

V

2,19

MAX

UNITS

NOTES

35

mA

3

3.5

mA

DC ELECTRICAL CHARACTERISTICS
(O°C :5 TAS 70°Cj(Vcc = 5.0 V ± 10%1
SYM

PARAMETER

ICC1

OPERATING CURRENT

MIN

Average power supply operating current
(RAS, CAS cycling, t RC = tRC min.l
ICC2

STANDBY CURRENT
Power supply standby current (RAS
DOUT = High Impedancel

= CAS =V IH ,

ICC3

RAS ONLY REFRESH CURRENT
Average power supply current, refresh mode
(RAS cycling, CAS =V IH ; t RC = t RC min.l

30

mA

3

ICC4

PAGE MODE CURRENT
Average power supply current, page mo~
operation (RAS =V 1L, t RAS = t RAS max., CAS
cycling; tpc = tpc min.l

32

mA

3,20

II(L)

INPUT LEAKAGE
Input leakage current, any input
(0 V:5 V 1N S +5.5 V, all other
pins not under test =0 voltsl

-10

10

p.A

IO(L)

OUTPUT LEAKAGE
Output leakage current (DOUT is disabled,
V:5 V OUT S +5.5 VI

-10

10

p.A

0.4

V
V

o
V OH
VOL

OUTPUT LEVELS
Output High (Logic 11 voltage (lOUT = -5 mAl
Output Low (Logic 01 voltage (lOUT =4.2 mA

IV·32

2.4

AC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (4,6,6,16)
(O°C:::; TA :::; 70°C), VCC

SYMBOL
STD
ALT

= 5.0 V ± 10%
PARAMETER

MK4516-9
MIN
MAX

UNITS

tRELREL

t RC

Random read or write cycle time

200

ns

tRELREL
(RMW)

tRMW

Read-modify-write cycle time

250

ns

tRELREL
(PC)

tpc

Page mode cycle time

100

ns

tRELQV

t RAC

Access time from RAS

90

ns

tCELQV

t CAC

Access time from CAS

50

ns

t CEHOZ

tOFF

Output buffer turn off delay

0

40

ns

tT

tT

Transition time (rise and fall)

3

50

ns

tREHREL

tRP

RAS precharge time

100

tRELREH

t RAS

RAS pulse width

90

tCELREH

t RSH

RAS hold time

60

ns

tRELCEH

tCSH

CAS hold time

90

ns
ns

--

ns
10000

ns

tCELCEH

tCAS

CAS pulse width

50

tRELCEL

tRCO

RAS to CAS delay time

20

tREHWX

tRRH

Read command hold time referenced to RAS

0

ns

tAVREL

t ASR

Row Address set-up time

0

ns

tRELAX

tRAH

Row Address hold time

15

ns

t AVCEL

t ASC

Column Address set-up time

0

ns

tCELAX

tCAH

Column Address hold time

15

ns

tRELA(C)X

tAR

Column Address hold time referenced to RAS

55

ns

tWHCEL

t RCS

Read command set-up time

0

ns

tCEHWX

tRCH

Read command hold time referenced to CAS

0

ns

tCELWX

t WCH

Write command hold time

25

ns

tRELWX

t WCR

Write command hold time referenced to RAS

65

ns

t WLWH

twp

Write command pulse width

25

ns

tWLREH

t RWL

Write command to RAS lead time

50

ns

tWLCEH

tCWL

Write command to CAS lead time

50

ns

IV-33

40

ns

•

AC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (Continued)

STD

SYMBOL
ALT

MK4516-9
MIN
MAX

PARAMETER

UNITS

t OVCEL

tos

Data-in set-up time

0

ns

tCELOX

tOH

Data-in hold time

25

ns

tRELOX

tOHR

Data-in hold time referenced to RAS

65

ns

tCEHCEL
(PC)

tcp

CAS precharge time
(for page mode cycle only)

45

ns

tRVRV

tREF

Refresh period

tWLCEL

twcs

WRITE command set-up time

0

ns

tCELWL

t cwo

CAS to WRITE delay

50

ns

tRELWL

t RWO

RAS to WRITE delay

90

ns

tCEHREL

t CRP

CAS to RAS precharge time

0

ns

CAPACITANCE
(O°C ~ TA ~ 70°C)(V cc = 5.0 V

2

ms

± 10%)

SYMBOL

PARAMETER

TYP

MAX

CI1

Input (Aa-Aa), DIN

4

5

pF

17

CI2

Input RAS, CAS, WRITE

8

10

pF

17

Co

Output (D OUT )

5

7

pF

17,18

NOTES:
1, No user connection to Pin 1 (Leadless Chip Carrier only), This pin must be left
floating,
2, All voltages referenced to VSS'
3, ICC is dependent on output loading and cycle rates, Specified values are
obtained with the output open,
4, An initial pause of 500!-,s is required after power-up followed by any 8
start-up cycles before proper device operation is achieved, RAS may be
cycled during the initial pause, If RAS inactive interval exceeds 2ms. the
device must be re-initialized by a minimum of 8 RAS start-up cycle,
5, AC characteristics assume tT = 5 ns
6, VIH min and VIL max are reference levels for measuring timing of input
signals, Transition times are measured between VIH and VIL'
7, The minimum specifications are used only to indicate cycle time at which
proper operation over the full temperature range (O°C :::; TA :::; 70°C) is
assured,
8, Load = 2 TIL loads and 100 pF,
9, Assumes that tRCD :::; tRCD (max), If tRCD is greater than the maximum
recommended value shown in this table, tRAC will increase by the amount
that tRCD exceeds the value shown,
10, Assumes that tRCD 2: tRCD (max),
11, tOFF max defines the time at which the output achieves the open circuit
condition and is not referenced to VOH or VOL,
12, Operation within the tRCD (max) limit insures that tRAC (max) can be met,

RAs

UNITS NOTES

tRCD (max) is specified as a reference point only; if tRCD is greater than the
specified tRCD (max) limit, then access time is controlled exclusively by
tCAC'
13, Either tRRH or tRCH must be satisfied for a read cycle,
14, These parameters are referenced to CASleading edge in early write cycles
and to WRITE leading edge in delayed write or read-modify-write,
15, twcs, tCWD' and tRWD are restrictive operating parameters in
READ/WRITE and READ/MODIFY/WRITE cycles only, If twcs 2: twcs,
(min) the cycle is an EARLY WRITE cycle, and the data output will remain
open circuitthroughoutthe entire cycle, IftCWD 2:tCWD (min) and tRWD 2:
tRWD (min), the cycle is a READ/WRITE, and the data output will contain
data read from the selected cell, If neither of the above conditions is met, the
condition of the data out (at access time and until CAS goes back to VIH) is
indeterminate,
16, The transition time specification applies for all input signals, In addition to
meeting the transition rate specification, all input signals must transit
between VIH and VIL (or between VIL and VI H) in a monotonic manner.
17, Effective capacitance calculated from the equation c = I t1Twith t1V = 3 volts
iW
and power supply at nominal level.
18, CAS = VIH to disable DOUT
19, Includes the dc level and all instantaneous signal excursions,
20, Page Mode operation is not guaranteed on the standard MK451 6, This
function is available on request,

IV-34

READ CYCLE
t RC

Figure 2
t RAS

RAS

tAR

V 1H
V 1L
tT

tCSH I
t

CAS

RSH

tCAS

V 1H
V 1L

ADDRESSES

•

V 1H
V 1L

WRiTE

V 1H
V 1L

L tCAC

t RAC
V OH

OPEN

DOUT
VOL

WRITE CYCLE (EARLY WRITE)
Figure 3
t RC
t RAS
V 1H

RAS

V 1L

tAR

~I
tC~H

t RSH
tCAS

CAS

V 1H
V 1L

V 1H

ADDRESSES

WRiTE

V 1L

V 1H
V 1L

~-----tDHR----~

V OH

VOL---------------------------------------OPEN
IV-3S

READ-WRITE/READ-MODIFY-WRITE CYCLE
Figure 4

1 4 - - - - - - - - - - tRMW

CAS

ADDRESSES

WRITE

VII'
V IL

V IH
V IL

V IH
VIL I....J,.J,..~~.....,

"RAS-ONLY"REFRESH CYCLE
NOTE: CAS =

Figure 5

RAS

ADDRESSES

DOUT

v'H' WRiTE = DON'T CARE

V IH
V IL

=

::~ 1//////J/!//a AD~~~SS J/IJlllkjlJ/J//II/IIiKYffi
tAO'

OH
V
- - - - - - - - - - OPEN - - - - - - - - - VOL

IV-36

PAGE MODE READ CYCLE (20)
Figure 6

PAGE MODE WRITE CYCLE (20)
Figure 7

RAS

CAS

ADDRESSES

WRiTE

DIN

V IH
V IL

V IH
V IL

V IH
V IL

V IH
V IL

V IH
V IL

IV·37

OPERATION
The 14 address bits required to decode one of the 16,384
cell locations within the MK4516 are multiplexed onto the
seven address inputs and latched into the o'n-chip address
latches by externally applying two negative going TIL-level
clocks. The first clock, Row Address Strobe (RAS), latches
the seven row addresses into the chip. The high-to-Iow
transition of the second clock, Column Address Strobe
(CAS), subsequently latches the seven column addresses
into the chip. Each ofthese signals, RAS and CAS, triggers a
sequence of events which are controlled by different
delayed internal clocks. The two clock chains are linked
together logically in such a way that the address
multiplexing operation is done outside of the critical timing
path for read data access. The later events in the CAS clock
sequence are inhibited until the occurrence of a delayed
signal derived from the RAS clock chain. This "gated CAS"
feature allows the CAS clock to be externally activated as
soon as the Row Address Hold specification (t RAH ) has been
satisfied, and the address inputs have been changed from
Row address to Column address information.
The "gated CAS" feature permits CAS to be activated at any
time after tRAH' and itwill have no effect on the worst case
data access time (tRAd up to the point in time when the
delayed row clock no longer inhibits the remaining
sequence of column clocks. Two timing endpoints result
from the internal gating of CAS, which are called tRCO (min)
an~CO (max). No data storage or reading errors will result
if CAS, is applied to the MK4516 at a point in time beyond
the tRCO (max) limit. However, access time wi.!.L!ben be
determined exclusively by the access time from CAS (tcAd
rather than from RAS (tRAd, and RAS access time will be
lengthened by the amount thatt Rco exceeds the tRCO (max)
limit.

Datalnput/Output
Data to be written into a selected cell is latched into an
on-chip register by a combination of WRITE and CAS while
RAS is active. The latter of WRITE or CAS, to make its
negative transition, is the strobe for the Data In (DIN)
register. This permits several options in the write cycle
timing. In a write cycle, if the WRITE input is brought low
(active) prior to CAS being brought low (active), the DIN is
strobed by CAS, and the Input Data set-up and hold times
are referenced to CAS. If the input data is not available at
CAS time (late write) or if it is desired that the cycle be a
read-write or read-modify-write cycle, the WRITE signal
should be delayed until after CAS has made its negative

transition. In this "delayed write cycle", the data input setup and hold times !!!!eferenced to the negative edge of
WRITE rather than CAS.
Data is retrieved from the memory in a read cycle by
maintaining WRITE in the inactive or high state throughout
the portion of the memory cycle in which both the RAS and
CAS are low (active). Data read from the selected cell is
available at the output port within the specified access time.
The output data is the same polarity (not inverted) as the
input data.

Data Output Control
The normal condition of the Data Output (Dour) of the
MK4516 is the high impedance (open-circuit) state;
anytime CAS is high (inactive), the Dour pin will be floating.
Once the output data port has gone active, it will remain
valid until CAS is taken to the precharge (inactive high)
state.

Refresh
Refresh of the dynamiC cell matrix is accomplished by
performing a memory cycle at all 128 combinations of the
seven row address bits within each 2 ms interval. Although
any normal memory cycle will perform the required
refreshing, this function is most easily accomplished with
"RAS-only" cycles.

Page Mode Operation *
The Page Mode feature of the MK4516 allows for
successive memory operations at multiple column locations
within the same row address. This is done by strobing the
row address into the chip and maintaining the RAS signal
low (active) throughout all successive memory cycles in
which the row address is common. The first access within a
page mode operation will be available at tRAC or tCAC time,
whiohever is the limiting parameter. However, all
successive accesses within the page mode operation will be
available at t CAC time (referenced to CAS). With the
MK4516, this results in as much as a 55% improvement in
access timesl Effective memory cycle times are also
reduced when using page mode.
The page mode boundary of a single MK4516 is limited to
the 128 column locations determined by all combinations of
the seven column address bits. Operations within the page
boundary need not be sequentially addressed, and any
combination of read-write and read-modify-write cycles are
permitted within the page mode operation.

• see note 20

IV·38

MK4616A FUNCTIONAL BLOCK DIAGRAM

~--~-+-~~------~--------~~

•
~,--~----~--------------------------------------------~ ~~~~~~~

IV-39

IV·40

m

UNITED

TECHNOLOGIES
MOSTEK

MEMORY
COMPONENTS
16,384

x

1-BIT DYNAMIC RAM
M K4516(N/J/E)-1 0/12/15

FEATURES

o

Recognized industry standard 16-pin configuration from
Mostek

o

Common 1/0 capability using "early write"

o

Read, Write, Read-Write, Read-Modify-Write and PageMode capability

o Single +5 V (± 10%) supply operation
o On chip substrate
performance

bias

generator

for

optimum

o All inputs TIL compatible, low capacitance,
protected against static charge

o Active power 193 mW maximum
Standby power 20 mW maximum (MK4516-1 0)
Standby power 17 mW maximum (MK4516-12/15)

o Scaled POLY 5 technology

o 100 ns access time, 235 ns cycle time (MK4516-1 0)
120 ns access time, 270 ns cycle time (MK4516-12)
150 ns access time, 320 ns cycle time (MK4516-15)

o 128 refresh cycles (2 msec)

and

o Pin compatible with the MK4564 (64K RAM)

DESCRIPTION
The MK4516 is a single +5 V power supply version of the
industry standard MK4116, 16,384 x 1 bit dynamic RAM.
The high performance features of the MK4516 are
achieved by state-of-the-art circuit design techniques as
well as utilization of Mostek's "Scaled POLY 5" process
technology. Features include access times starting where
the current generation 16K RAMs leave off, TIL
compatability, and +5 V only operation.
The MK4516 is capable of a variety of operations including
READ, WRITE, READ-WRITE, READ-MODIFY-WRITE,
PAGE MODE, and REFRESH.

create new applications due to its superior performance.
The compatability with the MK4564 will also permit a
common board design to service both the MK4516 and
MK4564 (64K RAM) designs. The MK4516 will therefore
permit a smoother transition to the 64K RAM as the
industry standard MK4027 did for the MK4116.
The user requiring only a small memory size need no longer
pay the three power supply penalty for achieving the
economics of using dynamic RAM over static RAM when
using this new generation device.
PIN OUT
Figure 1

The MK4516 is designed to be compatible with the JEDEC
standards for the 16 K x 1 dynamic RAM. The MK4516 is
intended to extend the life cycle of the 16K RAM, as well as

LEADLESS CHIP CARRIER (1)
DUAL-IN-LiNE PACKAGE

Ao-As

Address Inputs

16 Vss

N/C 1

PIN FUNCTIONS

15

DIN (D) 2

RAS (RE)

WRiTE {W)
FiAS(RE)

Row Address Strobe

Ao 5
A2 6

(Vii) Read/Write Input

CAS (CE)

Col. Address Strobe

WRITE

DIN (D)

Data In

N/C

Not connected

DOUT (Q)

Data Out

Vee

Power (+5V)

Vss

GND

3
4

A,7

Vee 8

CAS (ff}

14 Dour (0)
MK4516

~(WI ~J
mlREI ~J
N/C

~J

[~

13 A.
12 A3
11 A.
10 As
9 N/C

r-, r-, r-'

1811911101

Available soon in MIL-STD-883 Class B (MKB4516)

IV-41

1111

N/C

•

ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc Supply Relative to Vss ........................................................ -1.0 V to +7.0 V
Operating Temperature, TA (Ambient) ............................................................ O°C to + 70°C
Storage Temperature (Ceramic) .............................................................. -65°C to + 150°C
Storage Temperature (Plastic) ............................................................... -55°C to +125°C
Power Dissipation .................................................................................. 1 Watt
Short Circuit Output Current ......................................................................... 50 mA
'Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device, This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied, Exposure to absolute
maximum rating conditions for extended periods may affect reliability,

RECOMMENDED DC OPERATING CONDITIONS
(O°C

:s TA :s 70°C)

SYM

PARAMETER

MIN

TYP

MAX

UNITS

NOTES

Vcc

Supply Voltage

4.5

5.0

5.5

V

2

V 1H

Input High (Logic 1) Voltage,
All Inputs

2.4

-

V cc +1

V

2

V 1L

Input Low (Logic 0) Voltage,
All Inputs

-2.0

-

.8

V

2,19

MAX

UNITS

NOTES

35

mA

3

3

mA

3.5

mA

21

DC ELECTRICAL CHARACTERISTICS
(O°C

:s TA:S 70°C) (V cc =

5.0 V

±

10%)

SYM

PARAMETER

ICC1

OPERATING CURRENT
Average power supply operating current
(RAS, CAS cycling, t RC = t RC min.)

ICC2

STANDBY CURRENT
Power supply standby current (RAS
DOUT = High Impedance)

MIN

= CAS = V 1H,

ICC3

RAS ONLY REFRESH CURRENT
Average power supply current, refresh mode
(RAS cycling, CAS = V 1H ; t RC = t RC min.)

30

mA

3

ICC4

PAGE MODE CURRENT
Average power supply current, page mode
operation (RAS = V 1L, tRAS = t RAS max., CAS
cycling; tpc = tpc min.)

32

mA

3,20

II(L)

INPUT LEAKAGE
Input leakage current, any input
(0 V :s V 1N :s +5.5 V, all other
pins not under test = 0 volts)

-10

10

/-LA

IO(L)

OUTPUT LEAKAGE
Output leakage current (DOUT is disabled,
V:S VOUT:S +5.5 V)

-10

10

/-LA

0.4

V
V

o
V OH
VOL

OUTPUT LEVELS
Output High (Logic 1) voltage (lOUT = -5 mAl
Output Low (Logic 0) voltage (lOUT = 4.2 mA

IV-42

2.4

AC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (4,5,6,16)
(O°C :::; TA:::; 70°C), V cc = 5.0 V

±

10%

SYMBOL

MK4516-10

MK4516-12

MK4516-15

PARAMETER

MIN

MIN

MIN

tRELREL t RC

Random read or write cycle time

235

270

320

ns

7,8

tRELREL tRMW
(RMW)

Read-modify-write cycle time

285

320

410

ns

7,8

tRELREL tpc
(PC)

Page mode cycle time

125

145

190

ns

7,8,20

tRELQV tRAC

Access time from RAS

100

120

150

ns

8,9

tCELQV tCAC

Access ti me from CAS

55

65

80

ns

8,10

t CEHOZ tOFF

Output buffer
turn-off delay

0

45

0

50

0

60

ns

11

Transition time (rise
and fall)

3

50

3

50

3

50

ns

6,16

tREHREL t RP

RAS precharge time

110

tRELREH t RAS

RAS pulse width

115

tCELREH t RSH

RAS hold time

70

85

105

ns

tRELCEH tCSH

CAS hold time

100

120

165

ns

tCELCEH tCAS

CAS pulse width

55

1()4

65

1()4

95

1()4

ns

tRELCEL tRCD

RAS to CAS delay time

25

45

25

55

25

70

ns

12

tREHWX tRRH

Read command hold time
referenced to RAS

0

0

0

ns

13

tAVREL t ASR

Row Address set-up time

0

0

0

ns

tRELAX

Row Address hold ti me

15

15

15

ns

Column Address seFup time

0

0

0

ns

Column Address hold time

15

15

20

ns

tRELA(C)X tAR

Column Address hold time
referenced to RAS

60

70

90

ns

tWHCEL tRCS

Read command set-up time

0

0

0

ns

tCEHWX t RCH

Read command hold time
referenced to CAS

0

0

0

ns

tCELWX t WCH

Write command hold time

25

30

45

ns

tRELWX t WCR

Write command hold time
referenced to RAS

70

85

115

ns

t WLWH twp

Write command pulse width

25

30

50

ns

tWLREH t RWL

Write command to RAS lead time

60

65

110

ns

tWLCEH tCWL

Write command to CAS lead time

45

50

100

ns

STD

tT

ALT

tT

tRAH

tAVCEL tAS C
tCELAX

tCAH

IV-43

MAX

MAX

120
1()4

140

MAX UNITS NOTES

135
1()4

175

ns
1()4

ns

13

•

AC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (Continued)
SYMBOL
STD

ALT

PARAMETER

MK4516-10

MK4516-12

MK4516-15

MIN

MIN

MIN

MAX

MAX

MAX UNITS NOTES

tOVCEL tos

Data-in set-up time

0

0

0

ns

14

tCELDX tOH

Data-in hold time

25

30

45

ns

14

tRELDX tOHR

Data-in hold time referenced to
RAS

70

85

115

ns

tCEHCEL tcp
(PC)

CAS precharge time
(for page mode cycle only)

60

70

85

ns

tRVRV

Refresh period

tREF

2

2

2

20

ms

tWLCEL twcs

WRITE command set-up time

0

0

0

ns

15

tCELWL tcwo

CAS to WRITE delay

55

65

80

ns

15

tRELWL t RWO

RAS to WRITE delay

100

120

150

ns

15

tCEHREL t CRP

CAS to RAS precharge time

0

0

0

ns

CAPACITANCE
(O°C::; TA ::; 70°C) (Vcc = 5.0 V

SYMBOL

PARAMETER

CI1

±

10%)

TYP

MAX

Input (Ao-A6 ), DIN

4

5

pF

17

CI2

Input RAS, CAS, WRITE

8

10

pF

17

Co

Output (D OUT)

5

7

p~

17,18

NOTES:
1. No user connection to Pin 1 (Leadless Chip Carrier only). This pin must be left
floating.
2. All voltages referenced to VSS.
3. ICC is dependent on output loading and cycle rates. Specified values are
obtained with the output open.
4. An initial pause of 500 IJ.S is required after power-up followed by any 8 RAS
start-up cycles before proper device operation is achieved. RAS may be
cycled during the initial pause. If RAS inactive interval exceeds 2ms, the
device must be re-initialized by a minimum of 8 RAS start-up cycle.
5. AC characteristics assume tT = 5 ns
6. VIH min and VIL max are reference levels for measuring timing of input
signals. Transition times are measured between VIH and VIL.
7. The minimum specifications are used only to indicate cycle time at which
proper operation over the full temperature range (O°C :5 TA :5 70°C) is
assured.
8. Load = 2 TIL loads and 100 pF.
9. Assumes that tRCD :5 tRCD (max). If tRCD is greater than the maximum
recommended value shown in this table, tRAC will increase by the amount
that tRCD exceeds the value shown.
10. Assumes that tRCD 2: tRCD (max).
11. tOFF max defines the time at which the output achieves the open circuit
condition and is not referenced to VOH or VOL.

UNITS NOTES

12. Operation within the tRCD (max) limit insures that tRAC (max) can be met.
tRCD (max) is specified as a reference point only; if tRCD is greater than the
specified tRCD (max) limit, then access time is controlled exclusively by
tCAC'
13. Either tRRH or tRCH must be satisfied for a read cycle.
14. These parameters are referenced to CASleading edge in early write cycles
and to \iiiRi'fE leading edge in delayed write or read-modify-write.
15. twcs, tCWD' and tRWD are restrictive operating parameters in
READ/WRITE and READ/MODIFY/WRITE cycles only. If twcs 2: twcs
(min) the cycle is an EARLY WRITE cycle and the data output will remain
open circuit throughout the entire cycle. If tCWD2:tCWD (min) and tRWD 2:
tRWD (min) the cycle is a READ/WRITE and the data output will contain data
read from the selected cell. If neither of the above conditions are met the
condition of the data out (at access time a nd until CAs goes back to VIH) is
indeterminate.
16. The transition time specification applies for all input signals. In addition to
meeting the transition rate specification, all input signals must transit
between VIH and VIL (or between VIL and VIH) in a monotonic manner.
17. Effective capacitance calculated from the equation c = I ~with tN =' 3 volts
and power supply at nominal level.
t:N
18. CAs = VIH to disable DOUT'
19. Includes the dc level and all instantaneous Signal excursions.
20. Page Mode operation is not guaranteed on the standard MK4516. This
function is available on request.
21. Applies to MK4516-10 only.

IV-44

READ CYCLE
Figure 2

t RC
t RAS

RAS

tAR

V IH
V IL

tT
tCSH I
tRSH

CAS

ADDRESSES

tCAS

V IH
V IL

•

V IH
V IL

WRi'fE

V IH
V 1L

L tCAC
t RAC

DOUT

V OH

OPEN

VOL

WRITE CYCLE (EARLY WRITE)
Figure 3
t RC
V 1H
RAS

..

tAR

t RAS

,

V 1L

tC~H

t RSH
tCAS

V 1H
CAS

V 1L

V 1H
ADDRESSES

WRiTE

V 1L

V 1H
V 1L

VALID
DATA

DIN
tOHR

V OH
DOUT

OPEN

VOL

IV·45

READ·WRITE/READ·MODIFY·WRITE CYCLE
Figure 4

14---------

CAS

ADDRESSES

tRMw

----------.1

V IH
V IL

V IH
V IL

WRiTE

DIN

V IH
V IL

"-'-J..~~""'"

V OH
VOL

I

OPEN

VALID
DATA

~~ ~
"RAS·ONLY"REFRESH CYCLE
NOTE:

CAS = V IH, WRii'E = DON'T CARE

Figure 5

RAS

ADDRESSES

Dour

V IH
V IL

~:~ 7IiI/I!IIII11M 'm AD~".V;SS JI/I/II! 1.111//II!IIJ//llh
V OH

VOL

- - - - - - - - - - OPEN - - - - - - - - - -

IV-46

PAGE MODE READ CYCLE (20)
Figure 6
t RAS

RAS

VIH
VIL

r(
;
'

CAS

VIH
VIL

ADDRESSES

VIH
VIL

...

~he~

;"

DOUT

~-=:f

t RSH

•
'0,"

V OH
VOL

WRITE

f'C

)J

VIH
VIL

PAGE MODE WRITE CYCLE (20)
Figure 7

RAS

V IH
V IL

CAS

V IH
V IL

ADDRESSES

V IH
V IL

WRii'E

V IH
V IL

DIN

V IH
V IL

IV-47

',eH

J~

~W!I$~

OPERATION

write cycle" the data input set-up and hold times are
referenced to the negative edge of WRiTE rather than CAS.

The 14 address bits required to decode 1 of the 16,384 cell
locations within the MK4516 are multiplexed onto the 7
address inputs a nd latched into the on-chip address latches
by externally applying two negative going TIL-level clocks.
The first clock, Row Address Strobe (RAS), latches the 7 row
addresses into the chip. The high-to-Iow transition of the
second clock, Column Address Strobe (CAS), subsequently
latches the 7 column addresses into the chip. Each of these
signals, RAS and CAS, triggers a sequence of events which
are controlled by different delayed internal clocks. The two
clock chains are linked together logically in such a way that
the address mUltiplexing operation is done outside of the
critical timing path for read data access. The later events in
the CAS clock sequence are inhibited until the occurrence
of a delayed signal derived from the RAS clock chain. This
"gated CAS" feature allows the CAS clock to be externally
activated as soon as the Row Address Hold specification
(tRAH) has been satisfied and the address inputs have been
changed from Row address to Column address information.

Data is retrieved from the memory in a read cycle by
maintaining WRITE in the inactive or high state throughout
the portion of the memory cycle in which both the RAS' and
CAS are low (active). Data read from the selected cell is
available at the output port within the specified access time.
The output data is the same polarity (not inverted) as the
input data.
Data Output Control
The normal condition of the Data Output (Dour) of the
MK4516 is the high impedance (open-circuit) state;
anytime CAS is high (inactive) the Dour pin will be floating.
Once the output data port has gone active, it will remain
valid until CAS is taken to the precharge (inactive high)
state.
Refresh

The "gated CAS" feature permits CAS to be activated at any
time after tRAH and it will have no effect on the worst case
data access time (t RAC ) up to the point in time when the
delayed row clock no longer inhibits the remaining
sequence of column clocks. Two timing endpoints result
from the internal gating of CAS which are called tRCO (min)
an~o (max). No data storage or reading errors will result
if CAS is applied to the MK4516 at a point in time beyond
the tRCO (max) limit. However, access time will then be
determined exclusively by the access time from CAS (tcAd
rather than from RAS (tRAd, and RAS access time will be
lengthened by the amount that tRCO exceeds the tRCO (max)
limit.

Refresh of the dynamic cell matrix is accomplished by
performing a memory cycle at all 128 combinations of the
seven row address bits within each 2 ms interval. Although
any normal memory cycle will perform the required
refreshing, this function is most easily accomplished with
"AAS-only" cycles.
Page Mode Operation *

Data Input/Output
Data to be written into a selected cell is latched into an
on-chip register by a combination of WRITE and CAS while
RAS is active. The latter of WRITE or CAS to make its
negative transition is the strobe for the Data In (DIN) register.
This permits several options in the write cycle timing. In a
write cycle, if the WRITE input is brought low (active) prior to
CAS being brought low (active), the DIN is strobed by CAS,
and the Input Data set-up and hold times are referenced to
CAS. If the input data is not available at CAS time (late write)
or if it is desired that the cycle be a read-write or readmodify-write cycle the WR'iTE signal should be delayed until
after CAS has made its negative transition. In this "delayed

The Page Mode feature of the MK4516 allows for
successive memory operations at multiple column locations
within the same row address. This is done by strobing the
row address into the chip and maintaining the RAS signal
low (active) throughout all successive memory cycles in
which the row address is common. The first access within a
page mode operation will be available at t RAC or t CAC time,
whichever is the limiting parameter. However, all
successive accesses within the page mode operation will be
available at t CAC time (referenced to CAS). With the
MK4516, this results in as much as a 55% improvement in
access times! Effective memory cycle times are also
reduced when using page mode.
The page mode boundary of a single MK4516 is limited to
the 128 column locations determined by all combinations of
the seven column address bits. Operations within the page
boundary need not be sequentially addressed and any
combination of read-write and read-modify-write cycle are
permitted within the page mode operation.

* see footnote 20

IV·48

MK4516 FUNCTIONAL BLOCK DIAGRAM

•
v"

IV-49

IV-50

m

UNITED
TECHNOLOGIES
MOSTEK

MEMORY
COMPONENTS
16,384 x 1-BIT DYNAMIC RAM
MK4516(N/J)-20

FEATURES

o

Recognized industry standard 16-pin configuration from
Mostek

o

Common I/O capability using "early write"

o

Read, Write, Read-Write, Read-Modify-Write and PageMode capability

o

All inputs TTL compatible, low capacitance, and
protected against static charge

o

Single +5 V (± 10%) supply operation

o

On chip substrate
performance

o

Scaled POLY 5 technology

o

Active power 193 mW maximum
Standby power 17 mW maximum

o

Pin compatible with the MK4564 (64K RAM)

200 ns access time, 450 ns cycle time

o

128 refresh cycles (2 msec)

o

bias

generator for

optimum

DESCRIPTION
The compatibility with the MK4564 will also permit a
common board design to service both the MK4516 and
MK4564 (64K RAM) designs. Therefore, the MK4516 will
permit a smoother transition to the 64K RAM, as the
industry standard MK4027 did for the MK4116.

The MK4516 is a single +5 V power supply version of the
industry standard MK4116, 16,384 x 1 bit dynamic RAM.
The high performance features of the MK4516 are
achieved by state-of-the-art circuit design techniques as
well as utilization of Mostek's "Scaled POLY 5" process
technology. Features include access times starting where
the current generation 16K RAMs leave off, TTL
compatability, and +5 V only operation.
The MK4516 is capable of a variety of operations including
READ, WRITE, READ-WRITE, READ-MODIFY-WRITE,
PAGE MODE, and REFRESH.

The user requiring only a small memory size need no longer
pay the three power supply penalty for achieving the
economics of using dynamic RAM over static RAM when
using this new generation device.

DUAL IN-LINE PACKAGE PIN OUT
Figure 1

The MK4516 is designed to be compatible with the JEDEC
standards for the 16 K x 1 dynamic RAM. The MK4516 is
intended to extend the life cycle of the 16K RAM, as well as
create new applications due to its superior performance.
N/C 1
DIN (D) 2

PIN FUNCTIONS

WRITE(W) 3
Ao-As
CAS feE)

Address Inputs

RAS (RE)

Col. Address Strobe

WRITE \W) ReadlWrite Input

DIN (D)

Data In

N/C

Not connected

DouT(Q)

Data Out

Vee

Power (+5V)

Vss

GND

RAS(RE)4
Ao 5
A2 6

Row Address Strobe

A,7
Vee 8

Available soon in MIL-STD-883 Class B (MKB4516)

IV-51

16
15
14
13

Vss
CAS(eE)
DOUT(Q)
A6

12 A3
11 A4

10 A5

9 N/C

•

ABSOLUTE MAXIMUM RATINGS*
Voltage on V cc Supply Relative to Vss ........................................................ -1.0 V to +7.0 V
Operating Temperature, TA (Ambient) ............................................................ O°C to + 70°C
Storage Temperature (Ceramic) .............................................................. -65°C to +150°C
Storage Temperature (Plastic) ............................................................... -55°C to +125°C
Power Dissipation .................................................................................. 1 Watt
Short Circuit Output Current ......................................................................... 50 mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS
(O°C :5 TA :5 70°C)

SYM

PARAMETER

MIN

TYP

MAX

UNITS

NOTES

VCC

Supply Voltage

4.5

5.0

5.5

V

2

V IH

Input High (Logic 1) Voltage,
All Inputs

2.4

-

V cc +1

V

2

V IL

Input Low (Logic 0) Voltage,
All Inputs

-2.0

-

0.8

V

2,19

MIN

MAX

UNITS

NOTES

35

mA

3

3

mA

DC ELECTRICAL CHARACTERISTICS
(O°C :5 TA::; 70°C) (Vcc

= 5.0 V ± 10%)

SYM

PARAMETER

ICC1

OPERATING CURRENT
Average power supply operating current
(RAS, CAS cycling, t RC = t RC min.)

ICC2

STANDBY CURRENT
Power supply standby current (RAS
DOUT = High Impedance)

ICC3

RAS ONLY REFRESH CURRENT
Average power supply current, refresh mode
(RAS cycling, CAS = V IH; t RC = t RC min.)

30

mA

3

ICC4

PAGE MODE CURRENT
Average po~ supply current, page mo~
operation (RAS =V IL, tRAS = tRAS max., CAS
cycling; tpc = tpc min.)

32

mA

3,20

II(L)

INPUT LEAKAGE
Input leakage current, any input
(0 V ::; V IN ::; +5.5 V, all other
pins not under test = 0 volts)

-10

10

pA

IO(L)

OUTPUT LEAKAGE
Output leakage current (DOUT is disabled,
V::; V OUT :5 +5.5 V)

-10

10

p.A

0.4

V
V

= CAS =V IH ,

o
V OH
VOL

OUTPUT LEVELS
Output High (Logic 1) voltage (lOUT = -5 mA)
Output Low (Logic 0) voltage (lOUT =4.2 mA

IV-52

2.4

AC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (4,5,5,15)
(O°C ~TA ~ 70°C), VCC = 5.0 V ± 10%
STD

SYMBOL
ALT

PARAMETER

MK4616·20
MIN
MAX

UNITS

tRELREL

t RC

Random read or write cycle time

450

ns

tRELREL
(RMW)

tRMW

Read-modify-write cycle time

525

ns

tRELREL
(PC)

tpc

Page mode cycle time

220

ns

tRELOV

t RAC

Access time from RAS

200

ns

tCELOV

t CAC

Access time from CAS

100

ns

t CEHOZ

tOFF

Output buffer turn off delay

50

ns

tT

tT

Transition time (rise and fall

50

ns

tREHREL

t RP

RAS precharge time

200

tRELREH

t RAS

RAS pulse width

200

tCELREH

t RSH

RAS hold ti me

100

ns

tRELCEH

tCSH

CAS hold time

200

ns

tCELCEH

tCAS

-CAS pulse width

120

10000

ns

tRELCEL

t RCD

RAS to CAS delay time

30

100

ns

tREHWX

tRRH

Read command hold time referenced to RAS

45

ns

tAVREL

t ASR

Row Address set-up time

0

ns

tRELAX

tRAH

Row Address hold time

20

ns

tAVCEL

t ASC

Column Address set-up time

0

ns

tCELAX

tCAH

Column Address hold time

20

ns

tRELA(C)X

tAR

Column Address hold time referenced to RAS

150

ns

tWHCEL

t RCS

Read command set-up time

0

ns

tCEHWX

t RCH

Read command hold time referenced to CAS

0

ns

tCELWX

tWCH

Write command hold time

60

ns

tRELWX

tWCR

Write command hold time referenced to RAS

160

ns

t WLWH

twp

Write command pulse width

60

ns

tWLREH

t RWL

Write command to RAS lead time

110

ns

tWLcEH

tCWL

Write command to CAS lead time

100

ns

3

IV·53

ns
10000

ns

•

AC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (Continued)
SYMBOL
STD
ALT

MK4616-20
MIN
MAX

PARAMETER

UNITS

tovCEL

tos

Data-in set-up time

0

ns

tCELOX

tOH

Data-in hold time

60

ns

tRELOX

tOHR

Data-in hold time referenced to RAS

160

ns

tCEHCEL
(PC)

tcp

CAS precharge time
(for page mode cycle only)

110

ns

tRVRV

tREF

Refresh period

tWLCEL

twcs

WRITE command set-up time

tCELWL

t cwo

tRELWL
tCEHREL

2

ms

0

ns

CAS to WRITE delay

100

ns

t RWO

RAS to WRITE delay

200

ns

t CRP

CAS to RAS precharge time

0

ns

CAPACITANCE
(OOe :5 TA :5 70°C) (Vcc = 5.0 V

± 10%)
TYP

MAX

Input (Ao-Ae), DIN

4

5

pF

17

CI2

Input RAS, CAS, WRITE

8

10

pF

17

Co

Output (Dour)

5

7

pF

17,18

SYMBOL

PARAMETER

CI1

NOTES:
1. No user connection to Pin 1 (Leadless Chip Carrier only). This pin must be left
floating.
2. All voltages referenced to VSS.
3. ICC is dependent on output loading and cycle rates. Specified values are
obtained with the output open.
4. An initial pause of 500 /-tS is required after power-up followed by any 8 RAS
start-up cycles before proper device operation is achieved. RAS may be
cycled during the initial pause. If RAS inactive interval exceeds 2ms, the
device must be re-initialized by a minimum of 8 RAS start-up cycle.
5. AC characteristics assume tr = 5 ns
6. VIH min and VIL max are reference levels for measuring timing of input
signals. Transition times are measured between VIH and VIL.
7. The minimum specifications are used only to indicate cycle time at which
proper operation over the full temperature range (O°C :S TA :S 70°C) is
assured.
8. Load = 2 TIL loads and 100 pF.
9. Assumes that tRCD :S tRCD (max). If tRCD is greater than the maximum
recommended value shown in this table, tRAC will increase by the amount
that tRCD exceeds the value shown.
10. Assumes that tRCD ~ tRCD (max).
11. tOFF max defines the time at which the output achieves the open circuit
condition and is not referenced to VOH or VOL'
12. Operation within the tRCD (max) limit insures that tRAC (max) can be met.

UNITS NOTES

tRCD (max) is specified as a reference point only; if tRCD is greater than the
specified tRCD (max) limit, then access time is controlled exclusively by
tCAC'
13. Either tRRH or tRCH must be satisfied for a read cycle.
14. These parameters are referenced to'CA§" leading edge in early write cycles
and to WRITE leading edge in delayed write or read-modify-write.
15. twcs, tCWD' and tRWD are restrictive operating parameters in
READ/WRITE and READ/MODIFY/WRITE cycles only. If twcs ~ twcs,
(min) the cycle is an EARLY WRITE cycle, and the data output will remain
open circuit throughout the entire cycle.lftcWD ~tCWD(min)andtRWD ~
tRWD (min), the cycle is a READ/WRITE, and the data output will contain
data read from the selected cell. If neither of the above conditions is met, the
condition of the data out (at access time and until CAS goes back to VIH) is
indeterminate.
16. The transition time specification applies for all input signals. In addition to
meeting the transition rate specification, all input signals must transit
between VIH and VIL (or between VIL and VIH) in a monotonic manner.
17. Effective capacitance calculated from the equation c IIlTwith IlV 3 volts
and power supply at nominal level.
IlV
18. CAS = VIH to disable DOUT.
19. Includes the dc level and all instantaneous signal excursions.
20. Page Mode operation is not guaranteed on the standard MK4516. This
function is available on request.

IV-54

=

=

READ CYCLE

t RC

Figure 2
t RAS

ftAS

tAR

V IH
V IL
T

tCSH I
t RSH

CAl

ADDRESSES

tCAS

V IH
V IL

•

V IH
V IL

'W'RffE

V IH
V IL

L tCAC
t RAC

DOUT

V OH

OPEN

VOL

WRITE CYCLE (EARLY WRITE)
Figure 3
t RC
V IH
RAS

t RAS

-I

tAR

V IL

t RSH
tC,H
tCAS

CAS

V IH

I

V IL

V IH
ADDRESSES

'W'RffE

V IL

V IH
V IL
t

1

I

I

~tos

__
RWL_I

j.--tOH
VALID
DATA

DIN
tOHR

DOUT

V OH

OPEN

VOL

IV-55

READ·WRITE/READ·MODIFY·WRITE CYCLE
Figure 4

1 4 - - - - - - - - - - tRMW - - - - - - - - - - - - . 1
m

V IH

CAS

VII'

ADDRESSES

WFiiTE

DIN

V IL

V IL

V IH
V IL

V IH
V IL

V OH
VOL

I

OPEN

VALID
DATA

~- ~
"RAS·ONLY"REFRESH CYCLE
NOTE:

CAS = VIH' WRii'E = DON'T CARE

Figure 5

RAS

ADDRESSES

Dour

V IH
V IL

~:~ WI//I/II/~tm AD~~~SS
V OH
VOL

/$////7$/$111//// j0

- - - - - - - - - - OPEN - - - - - - - - - -

IV·56

PAGE MODE READ CYCLE (20)
Figure 6
~--------------------------tRAS----------------------------~

RAS

CAS

V IH
V il

~--------~--------------------------~s~r--------------------

V IH
V il

ADDRESSES

V IH
V il

DOUT

V OH
VOL

WRITE

V IH
V il

PAGE MODE WRITE CYCLE (20)
Figure 7

t RAS
RAS

CAS

ADDRESSES

WRITE

DIN

V IH
V il

V IH
V IL

V IH
V IL

V IH
V IL

V IH
V IL

IV-57

OPERATION
The 14 address bits required to decode one of the 16,384
cell locations within the MK4516 are multiplexed onto the
seven address inputs and latched into the on-chip address
latches by externally applying two negative going TIL-level
clocks. The first clock, Row Address Strobe (RAS), latches
the seven row addresses into the chip. The high-to-Iow
transition of the second clock, Column Address Strobe
(CAS), subsequently latches the seven column addresses
into the chip. Each of these signals, RAS and CAS, triggers a
sequence of events which are controlled by different
delayed internal clocks. The two clock chains are linked
together logically in such a way that the address
mUltiplexing operation is done outside of the critical timing
path for read data access. The later events in the CAS clock
sequence are inhibited until the occurrence of a delayed
signal derived from the RAS clock chain. This "gated CAS"
feature allows the CAS clock to be externally activated as
soon as the Row Address Hold specification (tRAH) has been
satisfied and the address inputs have been changed from
Row address to Column address information.
The "gated CAS" feature permits CAS to be activated at any
time after tRAH' and it will have no effect on the worst case
data access time (tRAd up to the point in time when the
delayed row clock no longer inhibits the remaining
sequence of column clocks. Two timing endpoints result
from the internal gating of CAS, which are called t RCD (min)
an~CD(max). No data storage or reading errors will result
if CAS is applied to the MK4516 at a point in time beyond
the t RCD (max) limit. However, access time wi~en be
determined exclusively by the access time from CAS (tcAd
rather than from RAS (t RAC ), and RAS access time will be
lengthened by the amount that t RCD exceeds the t RCD (max)
limit.

Data Input/Output
Data to be written into a selected cell is latched into an
on-chip register by a combination of WRITE and CAS while
RAS is active. The latter of WRITE or CAS, to make its
negative transition, is the strobe for the Data In (DIN)
register. This permits several options in the write cycle
timing. In a write cycle, if the WRITE input is brought low
(active) prio.!:....!£. CAS being brought low (active), the DIN is
strobed by CAS, and the Input Data set-up and hold times
are referenced to CAS. If the input data is not available at
CAS time (late write) or if it is desired that the cycle be a
read-write or read-modify-write cycle, the WRITE signal
should be delayed until after CAS has made its negative

transition. In this "delayed write cycle", the data input setup and hold times are referenced to the negative edge of
WRITE rather than CAS.
Data is retrieved from the memory in a read cycle by
maintaining WRITE in the inactive or high state throughout
the portion of the memory cycle in which both the RAS and
CAS are low (active). Data read from the selected cell is
available at the output port within the specified access time.
The output data is the same polarity (not inverted) as the
input data.

Data Output Control
The normal condition of the Data Output (D OUT ) of the
MK4516 is the high impedance (open-circuit) state;
anytime CAS is high (inactive), the DOUT pin will be floating.
Once the output data port has gone active, it will remain
valid until CAS is taken to the precharge (inactive high)
state.

Refresh
Refresh of the dynamic cell matrix is accomplished by
performing a memory cycle at all 128 combinations of the
seven row address bits within each 2 ms interval. Although
any normal memory cycle will perform the required
refreshing, this function is most easily accomplished with
"RAS-only" cycles.

Page Mode Operation *
The Page Mode feature of the MK4516 allows for
successive memory operations at multiple column locations
within the same row address. This is done by strobing the
row address into the chip and maintaining the RAS signal
low (active) throughout all successive memory cycles in
which the row address is common. The first access within a
page mode operation will be available at t RAC or t CAC time,
whichever is the limiting parameter. However, all
successive accesses within the page mode operation will be
available at t CAC time (referenced to CAS). With the
MK4516, this results in as much as a 55% improvement in
access times! Effective memory cycle times are also
reduced when using page mode.

IV-58

The page mode boundary of a single MK4516 is limited to
the 128 column locations determined by all combinations of
the seven column address bits. Operations within the page
boundary need not be sequentially addressed, and any
combination of read-write and read-modify-write cycle are
permitted within the page mode operation.

MK4516 FUNCTIONAL BLOCK DIAGRAM

~--~-+~ ~----~~-------1-+~

•
~,--~----~--------------------------------------------~ ~--~~~--~

IV-59

"'II

IV-60

!t

UNITED

TECHNOLOGIES
MOSTEK

MEMORY
COMPONENTS

65,536 x 1-BIT DYN( AMIC RAM
MK4564 P/N/J/E)-12
FEATURES

o

Recognized industry standard 16-pin configuration
from Mostek

o

Single +6 V (± 1()oAI) supply operation

o

On chip substrate
performance

o

Low power: 330 mW active, max
22 mW standby, max

bias

generator for optimum

o

Common 1/0 capability using "early write"

o

Read, Write, Read-Write, Read-Modify-Write and PageMode capability

o

All inputs TIL compatible, low capacitance, and
protected against static charge

o

Scaled POLY 6™ technology

o 128 refresh cycles (2 msec)
Pin 9 is not needed for refresh

o 120 ns access time, 220 ns cycle time
o Extended Dour hold using CAS control (Hidden Refresh)
DESCRIPTION
The MK4664 is the new generation dynamic RAM.
Organized 66,636 words by 1 bit, it is the successor to the
industry standard MK4116. The MK4664 utilizes Mostek's
Scaled Poly 6 process technology as well as advanced
circuit techniques to provide wide operating margins, both
internally and to the system user. The use of dynamic
circuitry throughout, including the 612 sense amplifiers,
assures that power dissipation is minimized without any
sacrifice in speed or internal and external operating
margins. Refresh characteristics have been chosen to
maximize yield (low cost to user) while maintaining
compatibility between dynamic RAM generations.

Multiplexed address inputs (a feature dating back to the
industry standard MK4096, 1973) permits the MK4664 to
be packaged in a standard 16-pin DIP with only 16 pins
required for basic functionality. The MK4664 is designed to
be compatible with the JEDEC standards for the 64K x 1
dynamic RAM.
The output ofthe MK4664 can be held valid up to 10 J.Lsec by
holding CAS active low. This is quite useful since refresh
cycles can be performed while holding data valid from a
previous cycle. This feature is referred to as Hidden Refresh.
The 64K RAM from Mostek is the culmination of several
years of circuit and process development, proven in
predecessor products.

PIN FUNCTIONS

PIN OUT
Figure 1
DUAL-IN-LiNE PACKAGE

Ao- A 7

Address Inputs

RAS (RE)

CAs (CE)

Column Address
Strobe
Data In
Data Out

WRiTE (Wi

D(N(D)
DoUT (0)

Vee
Vss
N!C

Row Address
Strobe
Read!
Write Input
Power (5V)
GND
Not Connected

LEADLESS CHIP CARRIER

16 Vss
D'N (D) 2
WRITE(W) 3

Available soon in MIL-STD-883 Class B (MKB).

IV-61

16

CAs(eE)

I

[~

linlll'!'l

~J

[Th

Ae

~J

L!.4

N/C

[ij

A3

CD

A4

WfiiTE(WI

14 DOUT (0)

m(RE)

4

13 AI

Ao

6

12 A,

N/C

11 A.

AO

A,

7

10 As

Vcc 8

9 A7

A2

3

iJ
[J

TOP VIEW

Dou.,.!Q)

•

ABSOLUTE MAXIMUM RATINGS·

Voltage on Vcc supply relative to Vss .•.....••..........•.......•..•..........••....•......•••• -1.0 V to +7.0 V
Operating Temperature, TA (Ambient) ...••..••...................•...•...........................• O°C to +70C
Storage Temperature (Ceramic) ....••..•.............•..•..............................•..... -65°C to +150°C
Storage Temperature (Plastic) ...•.•.•..............•...•.........•.....••.......•.......••.. -55°C to +125°C
Power Dissipation .....•...•....•..•...•..........•..••.........•.....••........................•... 1 Watt
Short Circuit Output Current ...•.•.......•.•..•..•....•.......•..•..•....••.•..............••.•..•.•. 50 mA
·Stresses greater than those listed undar "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those Indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS
(O°C S TA ::5 70°C)
SYM

PARAMETER

MIN

TYP

MAX

UNITS

NOTES

Vcc

Supply Voltage

4.5

5.0

5.5

V

1

V1H

Input High (Logic 1) Voltage,
All Inputs

2.4

-

Vcc +1

V

1

V1L

Input Low (Logic 0)
Voltage, All Inputs

-2.0

-

.8

V

1,18

MIN

MAX

UNITS

NOTES

2

DC ELECTRICAL CHARACTERISTICS
(O°C S TA ::5 70°C) (Vcc = 5.0 V ± 10%)
SYM

PARAMETER

ICC1

OPERATING CURRENT
Average power supply operating current
(RAS, CAS cycling; tRC =t RC min.)

60

mA

ICC2

STANDBY CURRENT
Power supply standby current (RAS
DOUT = High Impedance)

4

mA

ICC3

R'AS ONLY REFRESH CURRENT

50

mA

2

40

mA

2

=V1H,

Average power supply current, refresh mode
(RAS cycling, CAS =V1H ; tpc =tpc min.)
ICC4

PAGE MODE CURRENT
Average power supply current, page mode
operation (RAS =V1L, tRAS =tRAS max., CAS
cycling; tpc =tpc min.)

II(L)

INPUT LEAKAGE
Input leakage current, any input
(0 V ::5 V1N ::5 Vcd, all other pins not under
test =0 volts

-10

10

JJ.A

IO(L)

OUTPUT LEAKAGE
Output leakage current (D OUT is disabled,
OV SVOUT :5Vcd

-10

10

JJ.A

0.4

V
V

VOH
VOL

OUTPUT LEVELS
Output High (Logic 1) voltage (lOUT =-5 mA)
Output Low (Logic 0) voltage (lOUT =4.2 mA)

IV-62

2.4

NOTES:
1. All voltages referenced to VSS.
2. ICC is dependent on output loading and cycle rates. Specified values are
obtained with the output open.
3. An initial pause of 500 /-Is is required after power-up followed by any 8 RAS
cycles before proper device operation is achieved. Note that RAS may be
cycled during the initial pause.
4. AC characteristics assume If = 5 ns.
5. VIH min. and VIL max. are reference levels for measuring timing of input
signals. Transition times are measured between VIH and VIL'
6. The minimum specifications are used only to indicate cycle time at which
proper operation over the full temperature range (O°C S TA S 70°C) is
assured.
7. Load = 2 TIL loads and 50 pF.
8. Assumes that tRCo-S tRCD (max). If tRCD is greater than the maximum
recommended value shown in this table, tRAC will increase by the amount
that tRCD exceeds the value shown.
9. Assumes that tRCD ;::: tRCD (max).
10. tOFF max defines the time at which the output achieves the open circuit
condition and is not referenced to VOH or VOL.
11. Operation within the tRCD (max) limit permits tRAC (max) to be met. tRCD
(max) is specified as a reference point only; if tRCD is greater than the
specified tRCD (max) limit, then access time is controlled exclusively by
tCAC'

12. Either tRRH or tRCH must be satisfied for a read cycle.
13. These parameters are referenced to CAS leading edge in early write cycles
and to WRiTE leading edge in delayed write or read-modify-write cycles.
14. twcs, tCWD, and tRWD are restrictive operating parameters in
READ/WRITE and READ/MODIFY/WRITE cycles only. If twcs ;::: twcs
(min) the cycle is an EARLY WRITE cycle and the data output will remain
open circuit throughout the entire cycle.lftCWD ;:::tCWD(min)andtRWD;:::
tRWD (min) the cycle is a READ/WRITE and the data output will contain data
read from the selected cell. If neither of the above conditions are met the
condition of the data out (at access time and until CAS goes back to VIH) is
i ndeterm i nate.
15. In addition to meeting the transition rate specification, all input signals must
transmit between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
16. Effective capacitance calculated from theequation C = I Atwith A V = 3 volts
and power supply at nominal level.
17. CAS = VIH to disable DOUT.
18. Includes the DC level and all instantaneous signal excursions.
19. WRITE = don't care. Data out depends on the state of CAS. If CAS = VIH, data
output is high impedance. If CAS = VIL, the data output will contain data
from the last valid read cycle.

;:v

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
= 5.0 V ± 10%

(3,4,5,15) (O°C :'5 TA:5 70°C), V cc

STD

SYMBOL
ALT

PARAMETER

MK4564-12
MIN
MAX

UNITS

NOTES

tRELREL

t RC

Random read or write cycle time

220

ns

6,7

tRELREL
(RMW)

tRMw

Read-modify-write cycle time

260

ns

6,7

tRELREL
(PC)

tpc

Page mode cycle time

145

ns

6,7

tRELQV

t RAc

Access time from RAS

120

ns

7,8

tCELQV

t CAC

Access time from CAS

75

ns

7,9

tCEHQZ

tOFF

Output buffer turn-off delay

0

40

ns

10

tr

tr

Transition time (rise and fall)

3

50

ns

5,15

tREHREL

tRP

RAS precharge time

90

tRELREH

t RAS

RAS pulse width

120

tCELREH

t RSH

RAS hold time

75

ns

tRELCEH

tCSH

CAS hold time

120

ns

tCELCEH

tCAS

CAS pulse width

75

10,000

ns

tRELCEL

tRCO

RAS to CAS delay time

15

45

ns

11

tREHWX

tRRH

Read command hold time referenced to RAS

10

ns

12

tAvREL

tASR

Row address set-up time

0

ns

tRELAX

tRAH

Row address hold ti me

15

ns

tAVCEL

t ASC

Column address set-up time

0

ns

tCELAX

tCAH

Column address hold time

15

ns

Column address hold time referenced to RAS

70

ns

tRELA(C)X tAR

IV-63

ns
10,000

ns

•

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued)
(3,4,5,15) (O°C :5 TA:5 70°C), V cc

= 5.0 V ± 10%
MK4564-12

SYMBOL
STD

ALT

PARAMETER

MIN

MAX

tWHcEL

t RCS

Read command set-up time

0

ns

tCEHWX

t RCH

Read command hold time referenced to CAS

0

ns

tCELWX

t wcH

Write command hold time

30

ns

tRELWX

t WCR

Write command hold time referenced to RAS

75

ns

t WLWH

twp

Write command pulse width

15

ns

tWLREH

t RWL

Write command to RAS lead time

35

ns

tWLCEH

tCWL

Write command to CAS lead time

35

ns

tovCEL

tos

Data-in set-up time

0

ns

13

tCELOX

tOH

Data-in hold time

30

ns

13

tRELOX

tOHR

Data-in hold time referenced to RAS

75

ns

tCEHCEL
(PC)

tcp

CAS precharge time (for page-mode
cycle only)

60

ns

t RVRV

tREF

Refresh Period

tWLCEL

twcs

WRITE command set-up time

0

ns

14

tCELWL

t cwo

CAS to WRITE delay

50

ns

14

tRELWL

t RWO

RAS to WRITE delay

95

ns

14

tCEHCEL

t CPN

CAS precharge time

25

ns

2

UNITS

NOTES

12

ms

AC ELECTRICAL CHARACTERISTICS
(O°C :::; TA:::; 70°C)(Vcc

= 5.0 V ± 10%)
MAX

UNITS

NOTES

5

pF

16

Input Capacitance RAS, CAS, WRITE

10

pF

16

Output Capacitance (D OUT)

7

pF

16,17

SYM

PARAMETER

CI1

Input Capacitance

CI2
Co

(Ao - A 7), DIN

IV-64

READ CYCLE
Figure 2

V

ADDRESSES

1H

_

V 1L -

V

_
1H

WRiTE

V

Dour

I.--tCAC'--......~

V 1L -

1 4 - - - - - - t R A C - - - - -.......~

_
OH

VOL ....

------------------------OPEN---------~--------~

WRITE CYCLE (EARLY WRITE)
Figure 3

V

_
1H

RAS

V 1L -

CAS

V 1H V 1L -

V

ADDRESSES

_
1H

V 1L -

V 1H -

WRITE

V 1L -

lo4----

tOHR

-----~

VOH- __________________________________

V OL -

IV-65

OPEN ------------------------------------

•

READ-WRITE/READ-MODIFY-WRITE CYCLE
Figure 4
~

_____________________________ tRMW ________________________

~

RAS

V

ADDRESSES V

1H

_
-

1l

WRiTE

V 1H _
V 1l -

~~~~~~'"

V OH -

VOL _ -----+--------------------U

VIH

_

T7'7"TT7'"T'T'O...,...,..,.,.,.,rrTT77777"""""'"7"7":l"7'7":I'7TrT7"'T'T777"7"TT7'7T>""""""O'7T."""'"

~--.,-~--.J

/'7'T.rT7"7'77''T77''''''''''''''''''''''7'7":.-rT''''''

V 1l

-

~~".kU~~~~~".kU~"'"""'""'''''LLL~''''''''''.LLI.~~~

_"'::"';"'''-'-'---'1

\LLoLLLLLL""""'~,""",,<.LL.""~

"RAS-ONLY" REFRESH CYCLE
Figure 5

~-------------------tRC------------------~~
....- - - - - - - - t RAS

ADDRESSES

~ AD~~~SS

IV-66

------.t

PAGE MODE READ CYCLE
Figure 6

tRAs-------------------------------·~l~

RAS
V IL -

CAS

~~~J

;L,,,{

V IH V IL

-

•

ADDRESSES V IH V il

J~------------------------97~~~

PAGE MODE WRITE CYCLE
Figure 7

CAS

ADDRESSES

V IH
V il

WRITE

V IH
V il

DIN

V IH
V il

IV-67

The output data is the same polarity (not inverted) as the
input data.

OPERATION
The eight address bits required to decode 1 of the 65,536
cell locations within the MK4564 are multiplexed onto the
eight address inputs and latched into the on-chip address
latches by externally applying two negative going TIL-level
clocks. The first clock, Row Address Strobe (RAS), latches
the eight row addresses into the chip. The high-to-Iow
transition of the second clock, Column Address Strobe
(CAS), subsequently latches the eight column addresses
into the chip. Each of these signals, RAS and CAS, triggers a
sequence of events which are controlled by different
delayed internal clocks. The two clock chains are linked
together logica lIy in such a way that the address
multiplexing operation is done outside of the critical timing
path for read data access. The later events in the CAS clock
sequence are inhibited until the occurrence of a delayed
signal derived from the RAS clock chain. This "gated CAS"
feature allows the CAS clock to be externally activated as
soon as the Row Address Hold specification (tRAH) has been
satisfied and the address inputs have been changed from
Row address to Column address information.
The "gated CAS" feature perm its CAS to be activated at any
ti me after tRAH a nd it wi II have no effect on the worst case
data access time (tRAd up to the point in time when the
delayed row clock no longer inhibits the remaining
sequence of column clocks. Two timing endpoints result
from the internal gating of CAS which are called tRCD (min)
an~D (max). No data storage or reading errors will result
if CAS is applied to the MK4564 at a point in time beyond
the t RCD (max) limit. However, access time will then be
determined exclusively by the access time from CAS (tcAd
rather than from RAS (tRAd, and RAS access time will be
lengthened by the amount that t RCD exceeds the t RCD (max)
limit.

DATAINPUT/OUTPUT
Data to be written into a selected cell is latched into an
on-chip register by a combination of WRITE and CAS while
RAS is active. The latter of WRITE or CAS to make its
negative transition is the strobe for the Data In (DIN) register.
This permits several options in the write cycle timing. In a
write cycle, if the WRITE input is brought low (active) prior to
CAS being brought low (active), the DIN is strobed by CAS,
and the Input Data set-up and hold times are referenced to
CAS. If the input data is not available at CAS time (late write)
or if it is desired that the cycle be a read-write or readmodify-write cycle the WRITE signal should be delayed until
after CAS has made its negative transition. In this "delayed
write cycle" the data input set-up and hold times are
referenced to the negative edge of WRITE rather than CAS.
Data is retrieved from the memory in a read cycle by
maintaining WRITE in the inactive or high state throughout
the portion of the memory cycle in which both the RAS and
CAS are low (active). Data read from the selected cell is
available at the output port within the specified access time.

DATA OUTPUT CONTROL
The normal condition of the Data Output (D OUT) of the
MK4564 is the high impedance (open-circuit) state;
anytime CAS is high (inactive) the DOUT pin will be floating.
Once the output data port has gone active, it will remain
valid until CAS is taken to the precharge (inactive high)
state.

PAGE MODE OPERATION
The Page Mode feature of the MK4564 allows for
successive memory operations at multiple column locations
within the same row address. This is done by strobing the
row address into the chip and maintaining the RAS signal
low (active) throughout all successive memory cycles in
which the row address is common. The first access within a
page mode operation will be available at tRAC or tCAC time,
whichever is the limiting parameter. However, all
successive accesses within the page mode operation will be
available at t CAC time (referenced to CAS). With the
MK4564 this results in approximately a 45% improvement
in access times. Effective memory cycle times are also
reduced when using page mode.
The page mode boundary of a single MK4564 is limited to
the 256 column locations determined by all combinations of
the eight column address bits. Operations within the page
boundary need not be sequentially addressed and any
combination of read, write, and read-modify-write cycles is
permitted within the page mode operation.

REFRESH
Refresh of the dynamic cell matrix is accomplished by
performing a memory cycle at each of the 128 row
addresses within each 2 ms interval. Although any normal
memory cycle will perform the required refreshing, this
function is most easily accomplished with "RAS-only"
cycles.
The RAS-only refresh cycle requires that a 7 bit refreshaddress (AO-A6) be valid at the device address inputs when
RAS goes low (active). The state of the output data port
during a RAS-only refresh is controlled by CAS. If CAS is
high (inactive) during the entire time that RAS is asserted,
the output will remain in the high impedance state. If CAS is
low (active) the entire time the RAS is asserted, the output
port will remain in the same state that it was prior to the
issuance of the RAS signal. If CAS makes a low-to-high
transition during the RAS-only refresh cycle, the output
data buffer will assume the high impedance state. However,
the CAS may not make a high to low transition during the
RAS-only refresh cycle since the device interprets this as a
normal RAS/CAS (read or write) type cycle.

IV-68

HIDDEN REFRESH
A RAS-only refresh cycle may take place while maintaining
valid output data by extending the CAS active time from a
previous memory read cycle. This feature is referred to as a
hidden refresh. (See figure below.)

HIDDEN REFRESH CYCLE (SEE NOTE 19)
- {......_ _M_EM_OR_Y---JCyf=={I......-_R_E_FR_ES_Hc - , ' r = = i

CAS

ADDRESSES

DOUT

\~

____________

~r-

•

7lEf3lIIIfrllEYJI//flRII!!I:.
7lllllJ
V[///I//TI///lJlJIIZ
------~<~------------~>-

IV-69

IV-70

l!

UNITED
TECHNOLOGIES
MOSTEK

MEMORY
COMPONENTS
65,536

x 1-BIT DYNAMIC RAM

MK4564(P/N/J/E)-15/20

FEATURES

o

Extended DOUT hold using CAS control (Hidden Refresh)

Recognized industry standard 16-pin configuration from
Mostek

o

Common I/O capability using "early write"

o

Single +5V (± 10%) supply operation

o

Read, Write, Read-Write, Read-Modify-Write and PageMode capability

o

On chip substrate
performance

o

All inputs TTL compatible, low capacitance, and
protected against static charge

o

Scaled POLY 5™ technology

o

128 refresh cycles (2 msec)
Pin 9 is not needed for refresh

o

o
o

bias generator for optimum

Low power: 300 mW active, max
22 mW standby, max
150 ns access time, 260 ns cycle time (MK4564-15)
200 ns access time, 330 ns cycle time (MK4564-20)

DESCRIPTION

Multiplexed address inputs (a feature dating back to the
industry standard MK4096, 1973) permit the MK4564 to
be packaged in a standard 16-pin DIP with only 15 pins
required for basic functionality. The MK4564 is designed to
be compatible with the JEDEC standards for the 64K x 1
dynamic RAM.

The MK4564 is the new generation dynamic RAM.
Organized 65,536 words by 1 bit, it is the successor to the
industry standard MK4116. The MK4564 utilizes Mostek's
Scaled POLY 5 process technology as well as advanced
circuit techniques to provide wide operating margins, both
internally and to the system user. The use of dynamic
circuitry throughout, including the 512 sense amplifiers,
assures that power dissipation is minimized without any
sacrifice in speed or internal and external operating
margins. Refresh characteristics have been chosen to
maximize yield (low cost to user) while maintaining
compatibility between dynamic RAM generations.

The output ofthe MK4564 can be held valid up to 10 ~sec by
holding CAS active low. This is quite useful since refresh
cycles can be performed while holding data valid from a
previous cycle. This feature is referred to as Hidden Refresh.
The 64K RAM from Mostek is the culmination of several
years of circuit and process development, proven in
predecessor products.

PIN FUNCTIONS

PIN OUT
DUAL·IN·LlNE PACKAGE

LEAD LESS CHIP CARRIER
0IN1D ) N C \Iss

Ao-A 7
CAS(~)
DIN (D)
DouT(Q)

(RE)

Address Inputs

RAS

Column Address
Strobe
Data In
Data Out

WRITE
Vee
Vss
N/C

(W)

Row Address
Strobe
Read/
Write Input
Power (5V)
GND
Not Connected

16

v••

16

mice)

\2\ \I 1I\ L_.1
\181

1.._
WRITelWI

en retl
:1~

1,,-"

l_J

.!.J

14 DourlQ)

L!..ts

Dou~Q)

L~

AS

[~

A3

13 As

12 A.

11 A.

AO

~J

[I:2 A4

10 A.
9 A7

r;1
A1

Available soon in MIL-STD-883 Class B (MKB).

IV·71

r~l r,~i r,~i
'Icc

A7

AI5

•

ABSOLUTE MAXIMUM RATINGS*
Voltage on Vee supply relative to V 55 .....•......................•................•....•.•..... -1.0 V to +7.0 V
Operating Temperature, TA (Ambient) ..........................•.•................................ O°C to + 70C
Storage Temperature (Ceramic) .....•................................•....................... -65°C to +150°C
Storage Temperature (Plastic) ................•..................................•....•.•.... -55°C to +125°C
Power Dissipation .•..•.......................................•.....................•............... 1 Watt
Short Circuit Output Current .......•.................•............................................... 50 mA
'Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS
(O°C :$ TA :$ 70°C)

SYM

PARAMETER

MIN

TYP

MAX

UNITS

NOTES

Vee

Supply Voltage

4.5

5.0

5.5

V

1

V 1H

Input High (Logic 1) Voltage,
All Inputs

2.4

-

V ee +1

V

1

V 1L

Input Low (Logie 0)
Voltage, All Inputs

-2.0

-

.8

V

1,18

MAX

UNITS

NOTES

54.0

mA

2

4

mA

DC ELECTRICAL CHARACTERISTICS
(O°C:$ TA :$ 70°C) (Vee

= 5.0 V ± 10%)

SYM

PARAMETER

lec1

OPERATING CURRENT
Average power supply operating current
(RAS, CAS cycling; t Re = 330 ns)

ICC2

STANDBY CURRENT
Power supply standby current (RAS
DOUT = High Impedance)

ICC3

RAS ONLY REFRESH CURRENT
Average power supply current, refresh mode
(RAS cycling, CAS = V 1H ; t RC = t RC min.)

45

mA

2

ICC4

PAGE MODE CURRENT
Average power supply current, page mode
operation' (RA'S =V 1L, t RA5 = t RA5 max., CAS
cycling; tpc =tpc min.)

40

mA

2

II(L)

INPUT LEAKAGE
Input leakage current, any input
(0 V :$ V 1N :$ V cd, all other pins not under
test = 0 V

-10

10

iJ- A

IO(L)

OUTPUT LEAKAGE
Output leakage current (DOUT is disabled,
OV:$ V OUT :$ Vcd

-10

10

iJ- A

0.4

V
V

V OH
VOL

MIN

=V1H,

OUTPUT LEVELS
Output High (Logic 1) voltage (lOUT = -5 mAl
Output Low (Logic 0) voltage (lOUT = 4.2 mAl

IV-72

2.4

NOTES:
1. All voltages referenced to VSS.
2. ICC is dependent on output loading and cycle rates. Specified values are
obtained with the output open.
3. An initial pause of 500 jJ.S is required after power-up followed by any 8 ill
cycles before proper device operation is achieved. Note that RAS may be
cycled during the initial pause.
4. AC characteristics assume tT = 5 ns.
5. VIH min. and VIL max. are reference levels for measuring timing of input
signals. Transition times are measured between VIH and VIL.
6. The minimum specifications are used only to indicate cycle time at which
proper operation over the full temperature range (O°C ~ TA ~ 70°C) is
assured.
7. Load = 2 TIL loads and 50 pF.
8. Assumes that tRCD ~ tRCD (max). If tRCD is greater than the maximum
recommended value shown in this table, tRAC will increase by the amount
that tRCD exceeds the value shown.
9. Assumes that tRCD 2': tRCD (max).
10. tOFF max defines the time at which the output achieves the open circuit
condition and is not referenced to VOH or VOL.
11. Operation within the tRCD (max) limit insures that tRAC (max) can be met.
tRCD (max) is specified as a reference point only; if tRCD is greater than the

~~~~~ied tRCD (max) limit. then access time is controlled exclusively by

12. Either tRRH or tRCH must be satisfied for a read cycle.
13. These ~eters are referenced to CAS leading edge in early write cycles
and to WRITE leading edge in delayed write or read-modify-write cycles.
14. twcs, tCWD, and tRWD are restrictive operating parameters in
READ/WRITE and READ/MODIFY/WRITE cycles only. If twcs 2': twcs
(min) the cycle is an EARLY WRITE cycle and the data output will remain
open circuit throughout the entire cycle.lftcWD 2':tCWD (min) and tRWD 2':
tRWD (min)the cycle is a READ/WRITE and the data output will contain data
read from the selected cell. If neither of the above conditions are met the
condition of the data out (at access time and until CAS goes back to VIH) is
indeterminate.
15. In addition to meeting the transition rate specification, all input signals must
transmit between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
16. Effective capacitance calculated from the equation C = I b.twith b. V =3 volts
and power supply at nominal level.
17. CAS = VIH to disable DOUT.
18. Includes the DC level and all instantaneous Signal excursions.
19. WRITE = don't care. Data out d~nds on the state of CAS. If CAS = VIH, data
output is high impedance. If CAS = VIL, the data output will contain data
from the last valid read cycle.

;;:v

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
= 5.0 V ± 10%

(3,4,5,15) (O°C :::; TA:::; 70°C), Vcc

SYMBOL
STD
ALT

PARAMETER

MK4564-15
MIN
MAX

MK4564-20
MIN MAX

UNITS NOTES

tRELREL

t RC

Random read or write cycle time

260

330

ns

6,7

tRELREL
(RMW)

tRMw

Read modify write cycle time

300

390

ns

6,7

tRELREL
(PC)

tpc

Page mode cycle time

155

200

ns

6,7

tRELQV

t RAC

Access ti me from RAS

150

200

ns

7,8

tCELQV

tCAC

Access ti me from CAS

85

115

ns

7,9

tCEHQZ

tOFF

Output buffer turn-off delay

°

40

50

ns

10

tT

tT

Transition time (rise and fall)

°

3

50

3

50

ns

5,15

tREHREL

t RP

RAS precharge time

100

tRELREH

t RAS

RAS pulse width

150

tCELREH

t RSH

RAS hold time

85

115

ns

tRELCEH

tCSH

CAS hold time

150

200

ns

tCELCEH

tCAS

CAS pulse width

85

10,000

115

10,000

ns

tRELCEL

t RCD

RAS to CAS delay time

20

65

25

85

ns

11

tREHWX

tRRH

Read command hold time
referenced to RAS

20

25

ns

12

°

°

ns

120
10,000

200

ns
10,000

ns

tAVREL

t ASR

Row address set-up time

tRELAX

tRAH

Row address hold time

20

25

ns

tAVCEL

tAS C

Column address set-up time

tCELAX

tCAH

25

°

ns

Column address hold time

°

35

ns

Column address hold time
referenced to RAS

90

120

ns

tRELA(C)X tAR

IV-73

II

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued)
(3,4,5,15) (O°C :::; TA:::; 70°C), V cc

= 5.0V ± 10%
MK4564-15

SYMBOL

MIN

MAX

MK4564-20
MIN

MAX

UNITS NOTES

STD

ALT

PARAMETER

tWHCEL

t RcS

Read command set-up time

0

0

ns

tCEHWX

t RCH

Read command hold time
referenced to CAS

0

0

ns

tCELWX

tWCH

Write command hold time

35

55

ns

tRELWX

t WCR

Write command hold time
referenced to RAS

100

140

ns

12

t WLWH

twp

Write command pulse width

25

45

ns

tWLREH

tRWL

Write command to RAS lead time

35

55

ns

tWLCEH

tCWL

Write command to CAS lead time

35

55

ns

tOVCEL

tos

Data-in set-up time

0

0

ns

13

tCELOX

tOH

Data-in hold time

30

55

ns

13

Data-in hold time
referenced to RAS

95

140

ns

CAS precharge time
(for page-mode cycle only)

60

75

ns

tRELOX . tOHR

tCEHCEL
(PC)

tcp

tRVRV

tREF

Refresh Period

tWLCEL

twcs

WRITE command set-up time

tCELWL

t cwo

tRELWL
tCEHCEL

2

2

ms

-10

-10

ns

14

CAS to WRITE delay

55

80

ns

14

tRWO

RAS to WRITE delay

120

165

ns

14

t CPN

CAS precharge time

30

35

ns

AC ELECTRICAL CHARACTERISTICS
(0° :::; TA:::; 70°C), Vee

= 5.0 V ± 10%

SYM

PARAMETER

Cil

Input Capacitance (Ao - A 7 ), DIN

5

pF

16

CI2

Input Capacitance RAS, CAS, WmTE

10

pF

16

Co

Output Capacitance (D OUT )

7

pF

16,17

MAX UNITS NOTES

IV-74

READ CYCLE

V'H_

RAS

V'L-

V'H_

CAS

V'L-

ADDRESSES

•

V'H_
V'L-

WRi'i'E

V'H_
V'L-

i . - - tCAC

V
Dour

_
OH
VOL -

OPEN

WRITE CYCLE (EARLY WRITE)

RAS

V'H_
V'L -

CAS

V'HV'L -

ADDRESSES

V'H_
V'L -

WRITE

D'N

V'L -

V'H_
V'L tDHA

Dour

VOH V OL -

OPEN

IV-75

~

VALID
DATA

tOFF

READ-WRITE/READ-MODIFY-WRITE CYCLE

tRMW
V

RAS

_

IH

V IL -

CAs

V

_
IH

V IL -

WRiTE

V

_
IH

V IL -

DOUT

L""

V OH VOL -

tRAC
V
DIN

_
IH

V IL -

"RAS-ONLY" REFRESH CYCLE

~----------------------------tRC-----------------------------~

...----------tRAs ---~

ADDRESSES

~ AD"o~';SS

IV-76

PAGE MODE READ CYCLE

tRAs----------------------------··~l~

---tRSH----;.f L t .. {

1'--------:----+---------:--------------1 J ...

•
:?-------------------~~~

PAGE MODE WRITE CYCLE

CAS

ADDRESSES

WRi'fE

V IH
V IL

V IH
V IL

DIN

Iv-n

OPERATION

DATA OUTPUT CONTROL

The eight address bits required to decode 1 of the 65,536
cell locations within the MK4564 are multiplexed onto the
eight address inputs and latched into the on-chip address
latches by externally applying two negative going TTL-level
clocks. The first clock, Row Address Strobe (RAS), latches
the eight row addresses into the chip. The high-to-Iow
transition of the second clock, Column Address Strobe
(CAS), subsequently latches the eight column addresses
into the chip. Each of these signals, RAS and CAS, triggers a
sequence of events which are controlled by different
delayed internal clocks. The two clock chains are linked
together logically in such a way that the address
mUltiplexing operation is done outside of the critical timing
path for read data access. The later events in the CAS clock
sequence are inhibiteo until the occurrence of a delayed
signal derived from the RAS clock chain. This "gated CAS"
feature allows the CAS clock to be externally activated as
soon as the Row Address Hold specification (t RAH ) has been
satisfied and the address inputs have been changed from
Row address to Column address information.

The normal condition of the Data Output (Dour) of the
MK4564 is the high impedance (open-circuit) state;
anytime CAS is high (inactive) the Dour pin will be floating.
Once the output data port has gone active, it will remain
valid until CAS is taken to the precharge (inactive high)
state.

The "gated CAS" feature permits CAS to be activated at any
time after tRAH and it will have no effect on the worst case
data access time (tRAd up to the point in time when the
delayed row clock no longer inhibits the remaining
sequence of column clocks. Two timing endpoints result
from the internal gating of CAS which are called tRco (min)
an~o (max). No data storage or reading errors will result
if CAS is applied to the MK4564 at a point in time beyond
the tRco (max) limit. However, access time will then be
determined exclusively by the access time from CAS (tcAd
rather than from RAS (t RAC )' and RAS access time will be
lengthened by the amount that tRCO exceeds the tRCO (max)
limit.

PAGE MODE OPERATION
The Page Mode feature of the MK4564 allows for
successive memory operations at mUltiple column locations
within the same row address. This is done by strobing the
row address into the chip and maintaining the RAS signal
low (active) throughout all successive memory cycles in
which the row address is common. The first access within a
page mode operation will be available at t RAC or tCAC time,
whichever is the limiting parameter. However, all
successive accesses within the page mode operation will be
available at t CAc time (referenced to CAS). With the
MK4564 this results in approximately a 45% improvement
in access times. Effective memory cycle times are also
reduced when using page mode.
The page mode boundary of a single MK4564 is limited to
the 256 column locations determined by all combinations of
the eight column address bits. Operations within the page
boundary need not be sequentially addressed and any
combination of read, write, and read-modify-write cycles
is permitted within the page mode operation.

REFRESH

DATA INPUT/OUTPUT
Data to be written into a selected cell is latched into an
on-chip register by a combination of WRITE and CAS while
RAS is active. The latter of WRITE or CAS to make its
negative transition is the strobe for the Data In (DIN) register.
This permits several options in the write cycle timing. In a
write cycle, if the WRITE input is brought low (active) prior to
CAS being brought low (active), the DIN is strobed by CAS,
and the Input Data set-up and hold times are referenced to
CAS.lfthe input data is not available at CAS time (late write)
or if it is desired that the cycle be a read-write or readmodify-write cycle the WRITE signal should be delayed until
after CAS has made its negative transition. In this "delayed
write cycle" the data input set-up and hold times are
referenced to the negative edge of WRITE rather than CAS.
Data is retrieved from the memory in a read cycle by
maintaining WRITE in the inactive or high state throughout
the portion of the memory cycle in which both the RAS and
CAS are low (active). Data read from the selected cell is
available at the output port within the specified access time.
The output data is the same polarity (not inverted) as the
input data.

Refresh of the dynamic cell matrix is accomplished by
performing a memory cycle at each of the 128 row
addresses within each 2ms interval. Although any normal
memory cycle will perform the required refreshing, this
function is most easily accomplished with "RAS-only"
cycles.
The RAS-only refresh cycle requires that a 7 bit refresh
address (AO-A6) be valid at the device address inputs when
RAS goes low (active). The state of the output data port
during a R'AS-only refresh is controlled by CAS. If CAS is
high (inactive) during the entire time that RAS is asserted,
theoutputwill remain in the high impedance state. If CAS is
low (active) the entire time that RAS is asserted, the output
port will remain in the same state that it was prior to the
issuance of the RAS signal. If CAS makes a low-to-high
transition during the RAS-only refresh cycle, the output
data buffer will assume the high impedance state. However,
CAS may not make a high to low transition during the
RAS-only refresh cycle since the device interprets this as a
normal RAS/CAS (read or write) type cycle.

IV-78

HIDDEN REFRESH
A RAS-only refresh cycle may take place while maintaining
valid output data by extending the CAS active time from a
previous memory read cycle. This feature is referred to as a
hidden refresh. (See figure below.)

HIDDEN REFRESH CYCLE (SEE NOTE 19)

~"f==4

- { \ . ._ _
M_EM_OR_Y--,'n....._ _
RE_FR_ES_H

\~
ADDRESSES

____________

~m7llEJJlT///IfrllK

'llllllJ
DaUl

~r-

VII!/I!I(!I////I/JO

------c(

VALID DATA

>-

--------'

IV-79

•

IV-SO

m

UNITED
TECHNOLOGIES
MOSTEK

MEMORY
COMPONENTS
65,535 x 1-BIT DYNAMIC RAM
M K45H64(P/N/J/E)-8/1 0/12

FEATURES
D

PIN FUNCTIONS

Recognized industry standard 16-pin configuration from
Mostek

D Single +5V (± 10%) supply operation

D On

chip substrate
performance

bias

generator for

optimum

Address Inputs

RAS (RE)

Column Address
Strobe
Data In
Data Out

WRITE (Vii)

D Low power: 330 mW active, max (-10)

Row Address
Strobe
Read/
Write Input
Power (5V)
GND
Not Connected

22 mW standby, max
D 80 ns access time, 145 ns cycle time (MK45H64-8)

100 ns access time, 175 ns cycle time (MK45H64-1 0)
120 ns access time, 210 ns cycle time (MK45H64-12)
D Fast page mode cycle time, 100 nsec for -10

PIN OUT
DUAL-IN-LiNE PACKAGE LEADLESS CHIP CARRIER

D Extended DOUT hold using CAS control (Hidden Refresh)
O'NIDI N/C v"

N/C 1

D Common I/O capability using "early write"

O'N(O) 2
WRITE(W) 3

D Read, Write, Read-Write, Read-Modify-Write, and Page-

RAS(RE) 4

Mode capabilities

•

16 CAS

inputs TTL compatible, low capacitance, and
protected against static discharge.

(Cih

14 °OUT(O)

WRITE{W)

W{RE}

13 A.
12 A3

D All

l~J I]':, t~8J

16 Vss

N/C

11 A.

AO

10 As

A2

9 A7

CJrn,cr,

lj

LJ

,

".
,".,.

,

[~ A3

3 ,

,,

..

7 ,

n

tel
A'

r-, , , I-I
:91
v"

1101

1111

.7

AS

Dour/ Q )

A.
N/C

[~ A'

D 128 refresh cycles (2 msec)

Pin 9 is not needed for refresh

DESCRIPTION
The MK45H64 is a second generation, 64K dynamic RAM.
Organized as 65,536 words by 1 bit, it is optimized for high
speed, minimum cycle time applications such as video and
graphics memory, buffer memory, and mainframe memory.
The MK45H64 utilizes Mostek's latest scaled NMOS
process technology for maximum circuit density, wide
operating margins, and optimum reliability. Some features
of this process include silicon gate, double Jayer poly
interconnect, 1.5 p. channel lengths, and 200 A capacitor
oxide for maximum critical charge.
Multiplexed address inputs (a feature dating back to the
industry standard MK4096, 1973) permit the MK45H64 to

be packaged in a standard 16-pin DIP with only 15 pins
required for basic functionality. The MK45H64is designed
to be compatible with the JEDEC standards for the 64K x 1
dynamic RAM.
The MK45H64 features very fast page mode cycle times
(equal to R,A.S access). Additionally, TRAS (max) is specified
at40 p.secto allow an entire page of 256 bits to be accessed
within a single RAS cycle.
The outputofthe MK45H64 can be held valid upt040 p'sec
by holding CAS active low. This isquite useful since refresh
cycles can be performed while holding data valid from a
previous cycle. This feature is referred to as Hidden Refresh.

IV-81

•

IV-82

m

UNITED

MEMORY
COMPONENTS

TECHNOLOGIES
MOSTEK

262,144
FEATURES

o

PIN FUNCTIONS

Recognized industry standard 16-pin configuration from
Mostek

o

Single +5V (± 10%) supply operation

o

On-chip substrate bias generator for optimum performance

o

Low power: 412 mW active, max
22 mW standby, max

o

80 ns access time, 145 ns cycle time (MK45H56-8)
100 ns access time, 175 ns cycle time (MK45H56-1 0)
120 ns access time, 210 ns cycle time (MK45H56-12)

o

Fast page mode cycle time, 100 ns for -10

o

Extended DOUT hold using CAS control (Hidden Refresh)

x 1-BIT DYNAMIC RAM
MK45 H56(P/N/E)-8/1 0/12

Ao·As

Address Inputs

RAS (RE)

CAS (CE)

Column Address
Strobe
Data In
Data Out

WRITE(W)

DIN(D)
DOUT(Q)

PIN OUT
DUAL-IN-L1NE PACKAGE

As 1
DIN (D) 2
WRITE(W) 3

o Common liD capability using "early write"

o

Read, Write, Read-Write, Read-Modify-Write, and PageMode capability

o All inputs TIL compatible, low capacitance, and
protected against static discharge

o

Vee
Vss

Row Address
Strobe
Read/
Write Input
Power (5V)
GND

16 Vss
15 CAs' (eEl
14DouT (QI

RAS(REI4

13 As

Ao'5

12 A3

A2 ·6

11 A4

A, 7

10 A6

Vee 8

9 A7

256 refresh cycles (4 ms)
Pin 1 is not needed for refresh

DESCRIPTION
The MK45H56 is a 256K dynamic RAM, organized as
262,144 words by. 1 bit. It is optimized for high speed,
minimum cycle time applications such as video and
graphics memory, buffer memory, and mainframe memory.
The MK45H56 utilizes Mostek's latest scaled NMOS
process technology for maximum circuit density, wide
operating margins, and optimum reliability. Some features
of this process include silicon gate, double layer metal and
poly interconnects, 1.5 micron channel lengths, and 200 A
capacitor oxide for maximum critical charge.
.
MUltiplexed address inputs (a feature dating back to the
industry standard MK4096, 1973) permit the MK45H56 to

be packaged in a standard 16-pin DIP. The MK45H56 is
designed to be compatible with the JEDEC standards for the
256K x 1 dynamic RAM.
The MK45H56 features very fast page mode cycle times
(equal to RAS access). Additionally, t RAS (max) is specified at
40 f.lS to allow an entire page of data to be accessed within a
single RAS cycle.
The output of the MK45H56 can be held valid up to 40 f.lS by
holding CAS active low. This is quite useful since refresh
cycles can be performed while holding data valid from a
previous cycle. This feature is referred to as Hidden Refresh.

IV-S3

ABSOLUTE MAXIMUM RATINGS*
Voltage on Vee supply relative to Vss .......................................................... -1 .0 V to +7.0 V
Operating Temperature, TA (Ambient) ............................................................ O°C to + 70°C
Storage Temperature (Ceramic) .............................................................. -65°C to +150°C
Storage Temperature (Plastic) ............................................................... -55°C to +125°C
Power Dissipation .................................................................................. 1 Watt
Data Out Current ...................................................................................50 rnA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS
(O°C ::; TA ::; 70°C)
SYM

PARAMETER

MIN

TYP

MAX

UNITS

NOTES

Vec

Supply Voltage

4.5

5.0

5.5

V

1

V ,H

Input High (Logic 1) Voltage,
All Inputs

2.4

-

V ce +1

V

1

V ,l

Input Low (Logic 0)
Voltage, All Inputs

-2.0

-

.8

V

1,18

MAX

UNITS

NOTES

75

mA

2

4

rnA

DC ELECTRICAL CHARACTERISTICS
(O°C ::; TA::; 70°C) (Vec = 5.0 V ± 10%)
SYM

PARAMETER

ICCl

OPERATING CURRENT
Average power supply operating current
(RAS, CAS cycling; t RC = 175 ns)

ICC2

STANDBY CURRENT
Power supply standby current (RAS
DOUT = High Impedance)

ICC3

RAS ONLY REFRESH CURRENT
Average power supply current, refresh mode
(RAS cycling, CAS = V ,H; t RC = 175 ns)

60

rnA

2

ICC4

PAGE MODE CURRENT
Average power supply current, page mode
operation
(RAS = V 1L, t RAS = t RAS max., CAS cycling;
tpc = tpc min.)

50

rnA

2

I'(l)

INPUT LEAKAGE
Input leakage current, any input
(OV::; V ,N ::; Vcd, all other pins not under
test = 0 volts

-10

10

p,A

'Oll)

OUTPUT LEAKAGE
Output leakage current (DOUT is disabled,
OV ::; V OUT::; V cd

-10

10

p,A

0.4

V
V

V OH
VOL

MIN

= V ,H,

OUTPUT LEVELS
Output High (Logic 1) voltage (lOUT = -5 rnA)
Output Low (Logic 0) voltage (lOUT = 4.2 mAl

IV-84

2.4

NOTES:
1. All voltages referenced to VSS.
2. ICC is dependent on output loading and cycle rates. Specified values are
obtained with the output open.
3. An initial pause of 500 "s is required after power-up, followed byanyB RAS
cycles before proper device operation is achieved. Note that RAs may be
cycled during the initial pause.
4. AC characteristics assume tT = 5 ns.
5. VIH min. and VIL max. are reference levels for measuring timing of input
signals. Transition times are measured between VIH and VIL.
6. The minimum specifications are used only to indicate cycle time at which
proper operation over the full temperature range (O°C ::; TA ::; 70°C) is
assured.
7. Load = 2 TTL loads and 100 pF.
B. Assumes that tRCD ::; tRCD (max.). If tRCD is greater than the maximum
recommended value shown in this table, tRAC will increase by the amount
that tRCD exceeds the value shown.
9. Assumes that tRCD 2: tRCD (max.).
10. tOFF max. defines the time at which the output achieves the open circuit
condition and is not referenced to VOH or VOL'
11. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met.
tRCD (max.) is specified as a reference point only; if tRCD is greater than the
specified tRCD (max.) limit, then access time is controlled exclusively by
tCAC'

12. Either tRRH or tRCH must be satisfied for a read cycle.
13. These parameters are referenced to CAS leading edge in early write cycles
and to iiiiRii'E leading edge in delayed write or read-modify-write cycles.
14. twcs, tCWD, and tRWD are restrictive operating parameters in
READ/WRITE and READ/MODIFY/WRITE cycles only. If twcs 2: twcs
(min.), the cycle is an EARLY WRITE cycle, and the data output will remain
open circuit throughout the entire cycle.lftcWD 2:tCWD (min.) and tRWD 2:
tRWD (min.), the cycle is a READ/WRITE, and the data output will contain
data read from the selected cell. If neither of the above conditions are met,
the condition of the data out (at access time and until CAS goes back to VIH)
is indeterminate.
15. In addition to meeting the transition rate specification, all input signals must
transmit between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
16. Capacitance with Boonton meter or effective capacitance calculated from
the equation C =lliwith Do V =3 volts and power supply at nominal level.
DoV
17. CAS = VIH to disable DOUT.
lB. Includes the DC level and all instantaneous signal excursions.
19. i.i\i'Ri'TE =don't care. Data out depends on the state of CAs. If CAs =VIH, data
output is high impedance. If CAS = VIL' the data output will contain data
from the last valid read cycle.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(3,4,5,15) (O°C gA:5 70°C), VCC = 5.0V ± 10%
SYMBOL
STD
ALT

PARAMETER

MK46H66·8
MIN MAX

MK46H66·10 MK46H66·12
MIN MAX MIN MAX UNITS NOTES

tRELREL

t RC

Random read or write cycle time

145

175

210

ns

6,7

tRELREL

tRMW

Read-modify-write cycle time

166

200

239

ns

6,7

(RMW)

tRW

Read-write cycle time

149

180

216

tRELREL
(PC)

tpc

Page mode cycle time

80

100

120

ns

6,7

tRELOV

tRAC

Access ti me from RAS

80

100

120

ns

7,8

tCELOV

t CAC

Access time from CAS

45

55

65

ns

7,9

t CEHOZ

tOFF

Output buffer turn-off delay

0

30

0

30

0

35

ns

10

tT

tT

Transition time (rise and fall)

3

50

3

50

3

50

ns

5,15

tREHREL

t RP

RAS precharge time

55

tRELREH

t RAS

RAS pulse width

80

tCELREH

t RSH

RAS hold time

45

55

65

ns

tRELCEH

tCSH

CAS hold time

80

100

120

ns

tCELCEH

tCAS

CAS pulse width

45

40,000

55

40,000

65

40,000

ns

tRELCEL

t RCD

RAS to CAS delay time

8

35

10

45

12

55

ns

11

tREHWX

tRRH

Read command hold time
referenced to RAS

0

0

0

ns

12

65
40,000

100

ns

80
40,000

120

40,000

ns

tAVREL

t ASR

Row address set-up time

0

0

0

ns

tRELAX

tRAH

Row address hold ti me

8

10

12

ns

tAVCEL

t ASC

Column address set-up time

0

0

0

ns

tCELAX

tCAH

Column address hold time

12

15

18

ns

IV-8S

II

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued)
(3,4,5,15) (O°C :::; TA:::; 70°C), V cc

= 5.0V ± 10%

SYMBOL
STD

ALT

tRELA(C)X tAR

MK45H56-8 MK45H56-10 MK45H56-12
PARAMETER
Column address hold time
referenced to RAS

MIN

MAX

MIN

MAX

MIN

MAX UNITS NOTES

47

60

73

ns

tWHCEL

t RCS

Read command set-up time

0

0

0

ns

tCEHWX

t RCH

Read command hold time
referenced to CAS

0

0

0

ns

tCELWX

t WCH

Write command hold time

16

20

24

ns

tRELWX

tWCR

Write command hold time
referenced to RAS

51

65

79

ns

12

t WLWH

twp

Write command pulse width

10

10

12

ns

tWLREH

tRWL

Write command to RAS lead time

16

20

24

ns

tWLCEH

tCWL

Write command to CAS lead time

20

24

28

ns

tOVCEL

tos

Data-in set-up time

0

0

0

ns

13

tCELOX

tOH

Data-in hold time

16

20

24

ns

13

tRELOX

tOHR

Data-in hold time
referenced to RAS

51

65

79

ns

CAS precharge time
(for page-mode cycle only)

25

35

45

ns

tCEHCEL
(PC)

tcp

t RVRV

tREF

Refresh Period

tWLCEL

twcs

WRITE command set-up time

tCELWL

tcwo

tRELWL
tCEHCEL

4

4

ms

4

0

0

0

ns

14

CAS to WRITE delay

28

35

42

ns

14

t RWO

RAS to WRITE delay

63

80

97

ns

14

t CPN

CAS precharge time

15

20

25

ns

AC ELECTRICAL CHARACTERISTICS
(O°C :::; TA:::; 70°C) (Vcc

= 5.0V ± 10%)

SYM

PARAMETER

CI1

Input Capacitance

CI2
Co

MAX UNITS NOTES

(Ao - As), DIN

5

pF

16

Input Capacitance RAS, CAS, WRITE

5

pF

16

Output Capacitance (D OUT)

7

pF

16,17

IV-86

READ CYCLE

RAS

V'H_
V'L-

CAs

•

V'H_
V'L-

ADDRESSES

V'H_
V'L-

WRITE

V'H_
V'L-

\ . - - t CAC
t RAC

V
DOUT

OH

_

V OL -

WRITE CYCLE (EARLY WRITE)

RAS

V'H_
V'L -

CAS

V'HV IL -

ADDRESSES

V'H_
V'L-

WRITE

DIN

V IL -

V'H_
V IL tOHR

DOUT

V OH V OL -

~

VALID
DATA

OPEN

OPEN

IV-87

tOFF

READ-MODIFY-WRITE CYCLE

~------------------------------tRMW--------------------------~~

V

WRiTE

_
IH

V ll

-

V OH -

DOUT

V Ol

-

V

_

DIN

IH

V ll

L-.",
tRAC

-

READ-WRITE CYCLE
tRw

RAS

V IH
V 1L

CAs

V IH
V IL

V IH

ADDRESSES V

IL

WRITE

V IH
V IL

DOUT

DIN

V OH
VOL

V IH
V IL

Iv·aa

PAGE MODE READ CYCLE

~

FiAS

CAS

V IL -

_____________________________ tRAS ____________________________

~

~----------~------~------------------~ J~-------------------t+------ t RSM

VIM VIL

-

~~----------------------~

PAGE MODE WRITE CYCLE

CAS

ADDRESSES

VIM
VIL

WRITE

V _
IM
V IL

DIN

VIM
V IL

IV-89

The output data is the same polarity (not inverted) as the
input data.

OPERATION
The 18 address bits required to decode one of the 262,144
cell locations within the MK45H56 are multiplexed onto the
nine address inputs and latched into the on-chip address
latches by externally applying two negative going TIL-level
clocks. The first clock, Row Address Strobe (RAS), latches
the nine row addresses into the chip. The high-to-Iow
transition of the second clock, Column Address Strobe
(CAS), subsequently latches the nine column addresses
into the chip. Each ofthese signals, RAS and CAS, triggers a
sequence of events that are controlled by different delayed
internal clocks. The two clock chains are linked together
logically in such a way that the address multiplexing
operation is done outside of the critical timing path for read
data access. The later events in the CAS clock sequence are
inhibited until the occurrence of a delayed signal derived
from the RAS clock chain. This "gated CAS" feature allows
the CAS clock to be externally activated as soon as the Row
Address Hold specification (tRAH ) has been satisfied and the
address inputs have been changed from Row address to
Column address information.
The "gated CAS" feature permits CAS to be activated at any
time after t RAH , and it will have no effect on the worst case
data access time (tRAd up to the point in time when the
delayed row clock no longer inhibits the remaining
sequence of column clocks. Two timing endpoints result
from the internal gating of CAS, and they are called tRCO
(min) an~o (max). No data storage or reading errors will
result if CAS is applied to the MK45H56 at a point in time
beyond the tRCO (max) limit. However, access time will then
be determined exclusively by the access time from CAS
(tcAd rather than from RAS (tRAd, and RAS access time will
be lengthened by the amount that tRCO exceeds the tRCO
(max) limit.
DATA INPUT/OUTPUT
Data to be written into a selected cell is latched into an
on-chip register by a combination of WRITE and CAS while
RAS is active. The latter of WRITE and CAS to make its
negative transition is the strobe for the Data In (DIN) register.
This permits several options in the write cycle timing. In a
write cycle, if the WRITE input is brought low (active) prior to
CAS being brought low (active), the DIN is strobed by CAS;
and the Input Data set-up and hold times are referenced to
CAS. If the input data is not available at CAS time (late write)
or if it is desired that the cycle be a read-write or readmodify-write cycle, the WRITE signal should be delayed
until CAS has made its negative transition. In this "delayed
write cycle" the data input set-up and hold times are
referenced to the negative edge of WRITE rather than CAS.
Data is retrieved from the memory in a read cycle by
maintaining WRITE in the inactive or high state throughout
the portion of the memory cycle in which both the RAS and
CAS are low (active). Data read from the selected cell is
available at the output port within the specified access time.

DATA OUTPUT CONTROL
The normal condition of the Data Output (Dour) of the
MK45H56 is the high impedance (open-circuit) state;
anytime CAS is high (inactive), the Dour pin will be floating.
Once the output data port has gone active, it will remain
valid until CAS is taken to the precharge (inactive high)
state.
PAGE MODE OPERATION
The Page Mode feature of the MK45H56 allows for
successive memory operations at multiple column locations
within the same row address. This is done by strobing the
row address into the chip and maintaining the RAS signal
low (active) throughout all successive memory cycles in
which the row address is common. The first access within a
page mode operation will be available at tRAC or t CAC time,
whichever is the limiting parameter. However, all
successive accesses within the page mode operation will be
available at t CAc time (referenced to CAS). With the
MK45H56, this results in an approximate 45% improvement
in access times. Effective memory cycle times are also
reduced when using page mode.
The page mode boundary of a single MK45H56 is limitedto
the 512 column locations determined by all combinations of
the nine column address bits. Operations within the page
boundary need not be sequentially addressed, and any
combination of read, write, and read-modify-write cycles is
permitted within the page mode operation.
REFRESH
Refresh of the dynamic cell matrix is accomplished by
performing a memory cycle at each of the 256 row
addresses within each 4 ms interval. Although any normal
memory cycle will perform the required refreshing, this
function is most easily accomplished with "RAS-only"
cycles.
The RAS-only refresh cycle requires that an 8-bit refresh
address (AO-A7) be valid at the device address inputs when
RAS goes low (active). The state of the output data port
during a RAS-only refresh is controlled by CAS. If CAS is
high (inactive) during the entire time that RAS is asserted,
the output will remain in the high impedance state. If CAS is
low (active) the entire time the RAS is asserted, the output
port will remain in the same state as priortothe issuance of
the RAS signal. If CAS makes a low-tochigh transition
during the RAS-only refresh cycle, the output data buffer
will assume the high impedance state. However, CAS may
not make a high to low transition during the RAS-only
refresh cycle since the device interprets this as a normal
RAS/CAS (read or write) type cycle.

lV-gO

HIDDEN REFRESH
A RAS-only refresh cycle may take place while maintaining
valid output data by extending the CAS active time from a
previous memory read cycle. This feature is referred to as a
hidden refresh. (See figure below.)

HIDDEN REFRESH CYCLE (SEE NOTE 19)

M_EM_OR_Y~CY(=={,-_R_EF_RE_SH--,CY(=={

- { , -_ _

CAS

ADDRESSES

WRiTE
Dour

\~------!

•

71f2I3lI[!I!7leIllfl/IIT~

'UllllJ
--------(

VIlfj//f/lJIIT[i/lJ/

>-

' - _ _ VALID
_ DATA
_ _ _- J

IV-91

lV-92

II

UNITED

TECHNOLOGIES
MOSTEK

MEMORY
PRODUCTS
32K x 8-BIT DYNAMIC RAM
MK4856 (N/P/J/E) - 10/12115

FEATURES

DESCRIPTION

o LD3 ™ Technology

The MK4856 is the new generation, dynamic RAM.
Organized 32,768 words by 8 bits, it is the successor to the
industry standard 64K x 1. The MK4856 utilizes Mostek's
LD3 ™ process technology as well as advanced circuit
techniques to provide wide operating margins, both
internally and to the system user. The use of dynamic
circuitry throughout, and a novel sense amplifier scheme,
assures maximum device signal margins while maintaining
high performance. Refresh characteristics have been
chosen to minimize external interface circuitry.

o Single +5 V (± 10%) Supply Operation
o On-Chip Substrate Bias Generator
o Low Power 275 mW active, max
27.5 mW standby, max
o 100 ns Access Time (MK4856-1 0)
o 120 ns Access Time (MK4856-12)

The output ofthe MK4856 can be held valid up to 10 J.Lsec by
holding G active low. This is quite useful since refresh
cycles can be performed while holding data valid from a
previous cycle. This feature is referred to as hidden refresh.

o 150 ns Access Time (MK4856-15)
o Extended Data Output Using G control
o Hidden Refresh

PIN CONNECTION

o Read, Write, Read-Modify-Write capability

Figure 1
28 Vee
27 W

A..

o All inputs TTL compatible, low capacitance, and
protected against static charge
o 256 Refresh Cycles (4msec)

A'2

A,

25 Au

A.

3

26 A.

A.

15

24

A.

8

23 A"
22 G

A. 7

o

Non-Multiplexed for easy user interface

o Density Extension of JEDEC standard 28-pin static RAM
family

PIN FUNCTIONS
Address Inputs
Data .Input/Output
Chip Enable/Address Strobe
Output/Refresh Control
Read/Write Input
Power (+5)
Ground

IV·93

Aa

A2

8

21 A,.

A,

9

20

Ao

10-

E

19 00,

00. 11

18 00"

00,12

17 00"

OOa 13

18 00.

V•• 14

16 OOa

•

ABSOLUTE MAXIMUM RATINGS*
Voltage on V cc supply relative to V ss ...........................•............................ - 1 .0 V to 7.0 V
Operating Temperature, TA (Ambient) .......................................................... O°C to + 70°C
Storage Temperature (Ceramic) .................. ; .................•...................... - 65°C to + 150°C
Storage Temperature (Plastic) ....•.................................•...................... - 55°C to + 125°C
Power Dissipation ....•..•......................•.................•................................ 1 watt
Output Current ................................................................................... 20 mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS
(O°C S TA S 70°C)

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

NOTES

VCC

Supply Voltage

4.5

5.0

5.5

V

1

V IH

Input High (Logie 1) voltage, All
Inputs

2.4

-

V cc + 1

V

1

V IL

Input Low (logic 0) voltage, All Inputs

-2.0

-

0.8

V

1,12

TYP

MAX

NOTES

5 pF

10

AC ELECTRICAL CHARACTERISTICS
(O°C S TA S + 70°C) (V cc = +5.0 volts ± 10%)

SYMBOL

PARAMETER

CIN1

Input Capacitance

CIN2

Input Capacitance E, G, W,

10 pF

10

Coa

Input/output capacitance of DO

8 pF

10,11

MAX

UNITS

NOTES

50

mA

2

5

mA

2

Ao - A14

DC ELECTRICAL CHARACTERISTICS
(0°CSTA S70°C)(Vcc

=5.0V± 10%)

MIN

SYMBOL

PARAMETER

Icc1

OPERATING CURRENT
Average Power supply operating current
(e cycling; t RC = t RC min)

ICC2

STANDBY CURRENT
~wer supply standby current
(E = V1H ; DO = High Impedance)

ICC3

G BEFORE E REFRESH CURRENT
Average power supply current;
refresh mode cycling;
tRC =t RC min)

50

mA

2,13

GBEFORE EREFRESH CURRENT
Average power supply current;
Hidden refresh mode (E cycling;
t RC =t RC (min), DO active)

50

mA

2,14

iE

ICC4

IV-94

DC ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL

PARAMETER

ICC5

"[ ONLY REFRESH CURRENT
Average power supply current,
refresh mode (e cycling;
t RC = t RC (min);
W

MIN

MAX

UNITS

NOTES

50

mA

2

= V 1H; 'IT = V 1H )

II(L)

INPUT LEAKAGE
Input leakage current. any input
(0 V:;; V 1N :;; V CC, all other pins not under
test = 0 V)

-10

10

pA

lo(L)

OUTPUT LEAKAGE
Output leakage current
(DOUT is disabled, 0 V :;; V OUT :;; V CC)

-10

10

pA

VOH

OUTPUT LEVELS
Output High (Logic 1) voltage
(lOUT = -1 mal

2.4

VOL

Output Low (Logic 0) voltage
(lOUT = 4.2 mal

I

V

V

0.4

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(3, 4, 5, 6) (O°C :;; TA:;; 70°C) (Vcc = 5.0 ± 10%)
SYMBOL
ALT
STD

PARAMETER

MK4856-10
MIN
MAX

MK4856-12
MIN
MAX

MK4856-15
MIN
MAX

UNITS

NOTES

t RC

TEL2EL2
(R/W)

Random read or write cycle

180

210

260

ns

7,8

tRMW

TEL2EL2
(RMW)

Read-Modify-Write Cycle Time

260

295

355

ns

7,8

tCEA

TEL1 DQV

Chip Enable (E') Access Time

100

120

150

ns

16

tOEA

TGL1DQV

Output Enable access

30

35

40

ns

tOFF

TGH2DOZ

Output Buffer turn-off delay

0

40

0

40

0

40

ns

9

tT

tT

Transition Time (rise and fall)

3

50

3

50

3

50

ns

6

t EP

TEH2EL2

Chip Enable (E) precharge
time

70 ns

4 ms

80 ns

4ms

100 ns

4ms

tE

TEL1 EH1

Chip Enable (E) pulse width

100

10,000

120

10,000

150

10,000

ns

tG

TGL1GH1

Output Enable pulse width

30

10000

35

10000

40

10000

ns

t ASE

TAVEL2

Address Set up time

0

0

0

ns

tAHE

TEL1AX

Address Hold Time

20

20

25

ns

t GSE

TGH2EL2

Output Enable set up time

0

0

0

ns

tGWD

TGH2WL2

Output Enable to write delay
time

40

40

40

ns

tGEL

TGL1 EH1

Output Enable to Chip Enable
Lead Time

0

0

0

ns

tRcs

TWH2EL2

Read command (W) set up time

0

0

0

ns

IV-95

•

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued)
SYMBOL
ALT
STD

MK4856-10
MIN MAX

PARAMETER

MK4856-12
MIN MAX

MK4856-15
MIN MAX

UNITS

t RCH

TEH2WL2

Read Command hold time

0

0

0

ns

twcs

TWL1EL2

Write command (W) set up
time for early write

0

0

0

ns

t WCH

TEL1WH1

Write (W) hold time

35

40

50

ns

twp

TWL1WH1

Write command
width

35

40

50

ns

tWEL

TWL1EH1

Write command (W) to
chip enable (E) lead time

35

40

50

ns

tOSE

TDOVEL2

Data In, Set up Time
referenced to E for early write

0

0

0

ns

tosw

TDOVWL2

Data In Set Up Time
referenced to W for late write

0

0

0

ns

tOH

TEL1 DOX

Data In Hold Time,
Early Write

35

40

50

ns

tOHW

TWL1DOX

Data In hold time,
Late Write

20

20

25

ns

t EGO

TEL1 GL2

Chip Enable (E) to output
enable (<3) delay time

30

35

40

ns

tREF

TRVRV

Refresh Interval

t GSER

TGL 1 EL2

Output Enable (<3) set up
time for refresh

0

0

0

ns

tGEH

TEL1GH1

Output Enable (E) hold time
for refresh

30

35

40

ns

READ CYCLE
Figure 2

{WI pulse

4

4

~--------------------tRC--------------------~~
~----------tE--------~~

A

W

4

tGEL
tG

G

DO

VALID DATA OUT

IV-96

ms

NOTES

EARLY WRITE CYCLE

~-------------L--tRC----------------~~

Figure 3

i 4 - - - - -t E - - - - - . t

______ t=

t ASE

tAHE

~

~ ADDRESS VALID

A

_ _tw_CS:j

't

F

'wcH~

==:Y

twp

I I

ttOSE~ ~tOHj
DO

- - - - - - (VALID DATA

INj"""'""-----------------------

LATEWRITE CYCLE

t RC

Figure 4

tE

~

1\

i\

~--A-D-D-R-ES-S--V-A-Ll-D-~
.tASE~

A

~tAHE

t EWL

1\f4--'w.-y
""'-

tosw

r-

DO

II-

VALID DATA

t EP

., I

tOHW

IN

..
f-

READ-MODIFY-WRITE CYCLE
Figure 5

~-------------------------tRMW--------------------------~

A

DO

VALID
DATA OUT

IV-97

•

HIDDEN REFRESH CYCLE
Figure 6
14------------tRc----------t~ ....f-----tE

---.t

~------tE-----~

~~
A

~

ADDRESS VALID

-Jt

I

RCH

~--------------tG---------------~

DQ

VALID DATA OUT

REFRESH CYCLE
Figure 7

~----------------tRC------------------~

~---------tE--------~~~~~----tEP

tGEH - - - - i..~1

.

Jr//J/lllfl!lZ/Z1Z/0 r!ll!

IV-98

CHIP ENABLE REFRESH CYCLE
Figure 8

~---------------------------tRC----------------------~
~------------tE----------~~

E

A

w

G

•

!lJ

NOTES:
1. All voltages referenced to VSS.
2. ICC is dependent on output loading and cycle rates. Specified values are
obtained with the output open.
3. An initial pauseof 500l's is required after power-up followed byany8 cycles
before proper device operation is achieved. Note that E may be cycled during
the intial pause. On chip refresh counter is static and does not require
initialization.
4. AC characteristics assume tT = 5 ns.
5. VIH min and VIL max are reference levels for measuring timing of input
signals. Transition times are measured between VIH and VIL.
6. In addition to meeting the transition time specification, all input signals must
transit between VIH and VIL (or VIL and VIH) in a monotonic manner.
7. The minimum specifications are used only to indicate cycle times at which

proper operation over the full temperature range (O°C :S TA :S 70°C) is
assured.
8. Load = 4 ma and 100 pF.
9. toft max defines the time at which the output achieves open circuit condition
and is not referenced to VOH or VOL.
10. Capacitance measured with a 800nton meter or equivalent.
11. G = VIH to disable DO.
12. Includes the DC level and all instantaneous signal excursions.
13. DO Tri-state prior to Egoing low, DO remains tri-state through refresh.
14. DO active prior to going low, DO determined by
15. Write starts with the laterofE orW going low (except during a refresh cycle).
16. tCEA assumes tOEA ~ tOEA (max).
17. Any memory cycle will refresh a segment of the MK4856. All combinations
of address bits AO-A7 (256 memory cycles) are required.

IV-99

E

G.

IV-100

1984/1985 MICROELECTRONIC DATA BOOK

IJ

UNITED

TECHNOLOGIES
MOSTEK

MEMORY
COMPONENTS
4096 x 1-BIT STATIC RAM
MK4104 (P/J/N) SERIES

FEATURES

o

Combination static storage cells and dynamic
control circuitry for truly high performance

PART NUMBER

ACCESS TIME

CYCLE TIME

MK4104-3/-33
MK4104-4/-34

200ns
250ns
300ns
350ns

310ns
385ns
460ns
535ns

M K41 04-5/-3,~,,"':::""')
MK4104-6
"
,l' ,t'"

...

i

f

o

Battery

o

Single +5V Power Supply ( ± 10% tolerance)

[J

Fully TTL Compatible

1""

,II"

'I(

"

Fanout:

150mW (Max)

2 - Standard TTL
2 - Schottky TTL
12 - Low Power Schottky TTL

li

"""~J~(y.p",,'::::""~~~~"

and -35)

Standby Power Dissipation less than 28 mW
(at VCC = 5.5V)

,~" I"~

o Low'f:;'~'~JlV~\
Dissipation:
i /
~

o

(3V /1 OmW on -33, -34

o

"" .r:.::::;::::::;:"/" . . ",:>

D ESC R I PT I ON

Standard 18-pin DIP

" ,"i, : : ': ;: ~: : ~,: : >

The MOSTE K M K 4104 is'<;haracterof noise margin when driven by standard TTL and a
minimum of 500mV when used with high pertoristics of static and dynamic mel'n:o~'v"""".te¢'Pl'~"t~ues to
.
.
achieve a TTL compatible, 5 volt on:.f'Y';""'~'i'S'.!Jl performance Schottky TTL. These margins are Wider than
mance, low power memory device. ", I t,llj"tiliZEl's"""'pdvanced circuit design co,"!~epts and ar,."l' in~"d"y,~t.i~,e> on most TTL compatible MOS memories available.
state-of-the-art N-channel Silicon gate prOCeS~)l'pe¢),~J~ ""'~',,The push-pull output (no pull-up resistor required)
Iy ta,ilored to provide static data storage wi~h "thf.v~,r./"<"""'"~~,,Iivers a one level ~f 2.4V minimum and a zero
formance (speed and power) of dynamic R~1Yt$'("'\,:"'"J~~,e,1 of .4 volts maximum. The output has a fanout
Since th~ sto~a~e cell .is static,-1be devic~ may""t):,~"""" """""or,.~",,.s~andard TTL loads or 12 low power Schottky
stopped indefinitely with the CE clock In the on",,)' I,
'I',., ""I
(Logic 1) state.
,(,::,/ I "/,,,,":~':,,,,,>
Th~,,:,~::FrAM "et'Rploys an innovative static cell which
All input levels, including write enable (WE) and chip occupies ~<~'E!'~e, 2.75 square mils (1h the area of preenable (CE) are TTL compatible with a one level of vious ce.fl.~) afig ,0,issipates power levels comparable
FUNCTIONAL DIAGRAM

""

:':::'P'f~~::~~'~I'ECTIONS

A2

3

A3

4

18

Vee

17

A6

,"'J,~

A7

,(

~15 "i~,,8

A4

5

A5

6

,~,a

AIO

Dour

7

12

All

WE8

II

DIN

Vss

10

~

i,::::::"",A9

9

PIN NAMES
AO - A11

CE
DIN
DOUT

V-1

ADDRESS INPUTS
CHIP ENABLE
DATA INPUT
DATA OUTPUT

Vss
VCC
WE

GROUND
POWER (+5V)
WRITE ENABLE

DESCR IPTION (Cont'd)
to CMOS. The static cell eliminates the need for
refresh cycles and associated hardware thus allowing
easy system implementation.

ation, needed for Z80 interfacing, without external
circuitry.
The MK4104-3X series has the added capability of
retaining data in a reduced power mode. VCC maybe
lowered to 3V with a guaranteed power dissipation of
only 10mW maximum. This makes the MK4104
ideal for those applications requiring data retention
at the lowest possible power as in battery operation.

Power supply requirements of +5V ± 10% tolerance
combined with TTL compatability on all I/O pins
permits easy integration into large memory configurations. The single supply reduces capacitor
count and permits denser packaging on printed circuit
boards. The 5V only supply requirement and TTL
compatible I/O makes this part an ideal choice for
next generation +5V only microprocessors such as
MOSTEK's MK3880 (Z80). The early write mode
(WE active prior to eE) permits common I/O operREAD CYCLE

Reliability is greatly enhanced by the low power
dissipation which causes a maximum junction rise of
only at 8°C at 1.86 Megahertz operation. The MK
4104 was designed for the system designer and user
who require the highest performance available along
with MOSTEK's proven reliability.

....
VIH

VIL

VIH

ADDRESSES
VIL

VIH

WE
VIL

VIH

DIN
VIL

~~:~_-_-~_-_-_-_-_-_
,--_ _--«

WRITE
twc

READ

- - - - - - i......_ - - -

tRC ----~

V~ ID )>_-------~-------___< VALID
V·10

OUT ' } - -

The MK4801 A features a fast CE (50% of Address Access)
function to permit memory expansion without impacting
system access time. A fast OE (50% of access time) is
included to permit data interleaving for enhanced system
performance.

(tCEA or tOEA) rather tha n the address. The st~ of the 8 data
I/O signals is controlled by the Chip Enable (CE) and Output
Enable (OE) control signals.

The MK4801 A is pin compatible with Mostek's
BYTEWYDETM memory family of RAMs, ROMs and
EPROMs. Mostek also offers a higher performance version
of the MK4801 A designated the MK4801 A.

The MK4801A is in the Write Mode whenever the Write
Enable (WE) and Chip Enable (CE) control inputs are in the
low state.

OPERATION

Write Mode

The WRITE cycle is initiated by the WE pulse going low
provided that CE is also low. The leading edge of the WE
pulse is used to latch the status of the address bus.

Read Mode
The MK4801 A is in the READ MODE whenever the Write
Enable Control input (WE) is in the high state.
In the READ mode of operation, the MK4801 A provides a
fast address ripple-through access of data from 8 of 8192
locations in the static storage array. Thus, the unique
address specified by the 10 Address Inputs (An) define
which 1 of 1024 bytes of data is to be accessed.
A transition on any of the 10 address inputs will disable the
8 Data Output Drivers after t AZ . Valid Data will be available
to the 8 Data Output Drivers within tAA after the last address
input signal is stable, providing that the CE and OE access
times are satisfied. If CE or OE access times are not met,
data access will be measured from the limiting parameter

NOTE: In a write cycle the latter occurri ng edge of either WE
or CE will determine the start of the write cycle. Therefore,
t AS ' two and tAH are referenced to the latter occurring edge
of CE or WE. Addresses are latched at this time. All write
cycles whether initiated by CE orWE must be terminated by
the rising edge of WE. If the output bus has been enabled
(CE and DE low) then WE will cause the output to go to the
high Z state in t wEZ '
Da~n must be va Iid tosw prior to the low to high tra nsition
of WE. The Data In lines must remain stable for tOHW after
WE goes inactive. The write control of the MK4801 A
disables the data out buffers during the write cycle;
however, OE should be used to disable the data out buffers
to prevent bus contention between the input data and data
that would be output upon completion of the write cycle.

V-11

V-12

m

UNITED

TECHNOLOGIES
MOSTEK

MEMORY
COMPONENTS

1K x 8-BIT STATIC RAM
M K4801 A( P/J/N )-55/70/90
FEATURES

o

o

Static operation

o

Organization: 1K x 8 bit RAM JEDEC pinout

o

Pin compatible with Mostek's BYTEWYDpM memory
family

o

24/28 pin ROM/PROM compatible pin configuration

o

High performance

cr and OE functions facilitate bus control
Access Time

R/W
Cycle Time

MK4801A-55

55 nsec

55/65 nsec

MK4801A-70

70 nsec

70/80 nsec

MK4801A-90

90 nsec

90/100 nsec

Part No.

DESCRIPTION
The MK4801 A excels in high speed memory applications
where the organization requires relatively shallow depth
with a wide word format. The MK4801 A presents the user a
high density cost effective alternative to bipolar and
previous generation N-MOS fast memory.

The MK4801 A uses Mostek's Scaled POLY 5™ process and
advanced circuit design techniques to package 8,192 bits of
static RAM on a single chip. Static operation is achieved
with high performance and low power dissipation by
utilizing Address Activated™ circuit design techniques.
BLOCK DIAGRAM

OA.TAINPUTS/OUTPUTS
DOO-D07

Figure 1

PIN CONNECTIONS
Figure 2

IICC -----ONO _______

t:f _ _ _--+I

w.---~

A7 1
A62
A5 3
A44
A35
A26
A17
A08
000 9
00,10
0°2 11
VSS12

YSENSEAMP

.WRITEDRIIJER

128118118
MEMORY CELL
MATRIX

819281T
STATIC RAM

24 Vee
23AS
22 Ag
21 WE
20 OE
19 NC
18 CE
170 °7
16006
150 °5
140 °4
1300 3

TRUTH TABLE
CE

X

OE

WE

Mode

DQ

VIH

X

X

Deselect

High Z

VIL

X

VIL

Write

DIN

VIL

VIL

VIH

Read

Dour

VIL

VIH

VIH

Read

High Z

PIN NAMES
~-A9

CE
VSS
VCC

= Don't Care

V-13

Address Inputs
Chip Enable
Ground
Power (+5V)

Write Enable
Output Enable
No Connection
Data In/
Data Out

•

ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to VSS ............................................................. -.5V to + 7.0V
Operating Temperature TA (Ambient) ............................................................ O°C to + 70°C
Storage Temperature (AmbientXCeramic) ...................................................... -65°C to +150°C
Storage Temperature (AmbientXPlastic) ....................................................... -55°C to +125°C
Power Dissipation .................................................................................. 1 Watt
Output Current ..................................................................................... 20mA
'Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation ofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS7
(O°C :::;TA :::; +70°C)
SYM

PARAMETER

MIN

TYP

MAX

UNITS

NOTES

Vee

Supply Voltage

4.75

5.0

5.25

V

1

Vss

Supply Voltage

0

0

0

V

1

V IH

Logic "1" Voltage All Inputs

2.2

7.0

V

1

V IL

Logic "0" Voltage All Inputs

-2.0

.8

V

1,9

TYP

MAX

UNITS

NOTES

60

125

mA

8

DC ELECTRiCAL CHARACTERISTICS',1
(O°C :::; TA :::; + 70°C) (Vee = 5.0 V ± 5%)
SYM

PARAMETER

lec1

Average Vcc Power Supply Current

IlL

Input Leakage Current (Any Input)

-10

10

}.LA

2

IOL

Output Leakage Current

-10

10

}.LA

2

V OH

Output Logic "1" Voltage lOUT
= 1 mA

2.4

VOL

Output Logic "0" Voltage lOUT
=4mA

MIN

V

0.4

V

CAPACITANCE',7
(O°C:::; TA :::; + 70°C) (Vec = +5.0 V ± 5%)
SYM

PARAMETER

TYP

MAX

CI

All pins (except 0/0)

4 pF

6 pF

COlO

0/0 pins

10 pF

12 pF

V-14

NOTES

6

AC ELECTRICAL CHARACTERISTICS
(O°C ::s TA ::s 70°) (Vcc = 5.0 V ± 5%)

3,4

MK4801A-55 MK4801A-70 MK4801A-90
SYM

PARAMETER

MIN

MAX

t RC

Read Cycle Time

tAA

Address Access Time

55

70

90

ns

5

tCEA

Chip Enable Access Time

25

35

45

ns

5

tCEz

Chip Enable Data Off Time

30

ns

tOEA

Output Enable Access
Time

45

ns

tOEZ

Output Enable Data Off
Time

5

30

ns

tAZ

Address Data Off Time

10

10

10

ns

twc

Write Cycle Time

65

80

100

ns

tAS

Address Setup Time

0

0

0

ns

see
text

tAH

Address Hold Time

15

20

30

ns

see
text

tosw

Data To Write Setup Time

5

5

5

ns

tOHW

Data From Write Hold
Time

10

10

10

ns

two

Write Pulse Duration

25

30

40

ns

tWEZ

Write Enable Data Off Time

tWPL

Write Pulse Lead Time

55

MIN

MAX

70

15

5

5

25

15

10

5
40

5

5

OUTPUT LOAD

MAX UNITS NOTES

90

20

5

35

50

NOTES:
1. All voltages referenced to Vss.
2. Measured with .4:5 VI:5 5.0 V. outputs deselected and Vee = 5 V.
3. Ae measurements assume Transition Time = 5 ns. levels VSS to 3.0 V.
4. Input and output timing reference levels are at 1.5 V.
5. Measured with a load as shown in Figure 3.
6. Output buffer is deselected.
7. A minimum of 2 ms time delay is required after application of Vee (+5 V)
before proper device operation can be achieved.
8. lee measured with outputs open.
9. Negative undershoots to a minimum of -1.5 V are allowed with a maximum
of 50 ns pulse width.

MIN

20

15

5

5

ns

25

60

5

see
text

ns
ns

5V

Figure 3
1.1Kn
D.U.T. --~.-.---.

680n

;::, 30pF
(Including Scope and Jig)

V-1S

•

TIMING DIAGRAM
Figure 4
READ

READ

1..- - - - - t R C - - - - . , .....- - - - t R C

DOo-DQ7

-----------1(

WRITE

-----.j4-----

twc

----tl
..~1

' - -_ _ _.J

TIMING DIAGRAM
Figure 5

WRITE
1 - 4 - - - - - twc

WRITE

----0+011-----

READ

twc ----lI~---- tRC ----~

iij>-r___-( V~ ID )>-_____-«,-V-~-~-I~-D-H)-~---------«
......

V-16

VALID OUT

'J--

The MK4801 A features a fast CE (50% of Address Access)
function to permit memory expansion without impacting
system access time. A fast OE (50% of access time) is
included to permit data interleaving for enhanced system
performance.

(t CEA or tOEA) rather tha n the address. The state of the 8 data
1/0 signals is controlled by the Chip Enable (CE) and Output
Enable (OE) control signals.

The MK4801 A is pin compatible with Mostek's
BYTEWYDETM memory family of RAMs, ROMs and
EPROMs.

The MK4801 A is in the Write Mode whenever the Write
Enable (WE) and Chip Enable (CE) control inputs are in the
low state.

Write Mode

OPERATION
The WRITE cycle is initiated by the WE pulse going low
provided that CE is also low. The leading edge of the WE
pulse is used to latch the status of the address bus.

Read Mode
The MK4801 A is in the READ MODE whenever the Write
Enable Control input (WE) is in the high state.

NOTE: In a write cycle the latter occurring edge of either WE
or CE will determine the start of the write cycle. Therefore,
tAs, two and tAH are referenced to the latter occurring edge
of CE or WE. Addresses are latched at this time. All write
cycles whether initiated by CE orWE must be terminated by
the rising edge of WE. If the output bus has been enabled
(CE and OE low) then WE will cause the output to go to the
high Z state in t WEZ '

In the READ mode of operation, the MK4801A provides a
fast address ripple-through access of data from 8 of 8192
locations in the static storage array. Thus, the unique
address specified by the 10 Address Inputs (An) define
which 1 of 1024 bytes of data is to be accessed.
A transition on any of the 10 address inputs will disable the
8 Data Output Drivers after tAl' Valid Data will be available
to the 8 Data Output Drivers within tAA after the last address
input signal is stable, providing that the CE and OE access
times are satisfied. If CE or OE access times are not met,
data access will be measured from the limiting parameter

DaE!.!.n must be valid tosw priortothe low to high transition
of WE. The Data In lines must remain stable for tOHW after
WE goes inactive. The write control of the MK4801 A
disables the data out buffers during the write cycle;
however, OE should be used to disable the data out buffers
to prevent bus contention between the input data and data
that would be output upon completion of the write cycle.

V-17

•

V-18

m

UNITED

MEMORY
COMPONENTS

TECHNOLOGIES
MOSTEK
128

x 8 NON-VOLATILE RAM

MK4701 (N)-20

FEATURES
BLOCK DIAGRAM

o Data retention

Figure 1

in the absence of power

D Data security provided by automatic write protection
during power failure

o

Direct replacement for volatile byte wide Static RAM
RAM

D +5 Volt only Operation

o

Unlimited write cycles

D Low Power--75MW standby; 385 MW active
D 24-pin Dual In-Line Package with JEDEC standard
pinout

1/0 CKTRY

PIN CONNECTIONS

D Read Cycle time equals Write Cycle time

Figure 2

D Optional address signature simplifies external
decoder circuitry
D High performance

Part No.

Access Time

MK4701-20

200 ns

R/W
Cycle Time
200 nsec

24 vee
23 ASs

AS 7

1

A6

2

As

3

22 AS g

A4

4

21

A3

5

20

A2

6

19 N/AS 10

A1

7

18

Ao

8

DQ o

9

iN
G

E

17 DQ 7
. 16 DQ6
15 DQ s

DQ 1 10

14 DQ 4

DQ 2 11
GND 12

13 DQ3

TRUTH TABLE
PIN NAMES

Vee

E

G

W

Mode

DQ

<5.5V
volts

VIH

X

X

Deselect

High Z

VIL

VIH

VIL

Write

DIN

>4.75
volts

VIL

VIL

VIH

Read

DOUT

<4.5

VIL

VIH

VIH

Read

High Z

X

X

X

Write
Protect

High Z

AS 7-AS 10 Address Signature Inputs
N - Non Volatile Enable
Ao-As Address Inputs

Vee Power (+5V)

E Chip Enable

W· Write Enable

GND Ground

G Output Enable

000-00 7 Data In/Data Out

V·19

V-20

B

UNITED
TECHNOLOGIES
MOSTEK

MEMORY
COMPONENTS
2K x 8 CMOS STATIC RAM
MK6116 (J/N) - 15/20/25
MK6116L (J/N) - 15/20/25

FEATURES

TRUTH TABLE

o Direct replacement for 2K x

8 Byte Wide Static RAM

E

G

W

MODE

DQ

POWER

o

+5 Volt only Read/Write

VIH

X

X

Deselect

High Z

Standby

o

24-Pin Dual in Line package, JEDEC pinout

VIL

X

VIL

Write

DIN

Active

o

Read Cycle time equals write cycle time

V IL

VIL

V IH

Read

DOUT

Active

o

V IL

VIH

VIH

Read

High Z

Active

High Performance

PIN NAMES

Part No.

Access Time

RIW
Cycle Time

Ao - A10 Address Inputs

Vee

Power (+5 V)

MK6116/L-25

250 nsec

250 nsec

E

Chip Enable

W

Write Enable

M K6116/L-20

200 nsec

200 nsec

GND

Ground

G

Output Enable

MK6116/L-15

150 nsec

150 nsec

DOo - DQ?

Data In/Data Out

DESCRIPTION
The MK6116/6116L are 16,384-bit, CMOS Static RAMS,
organized 2K x 8 using advanced HCMOS process
technology. They are direct replacements for the popular
24-pin 6116/6116L type static CMOS RAMS. Both devices
have the same functional operating characteristics
except for active and standby power levels.

PIN CONNECTIONS
Figure 1

24

Vee

As

2

23

As

3

22

As
Ag

A4

4

21

iN

A3

5

20

G

A2
A,

6

19

A,o

7

18

E

8

17

D~

DOs
DOs

A7

Ao
DOc
DO,

9

16

10

15

0°2
GND

11

14

0°4

12

13

0°3

BLOCK DIAGRAM
Figure 2

V-21

ABSOWTE MAXIMUM RATINGS·
Voltage on any pin relative to Vss ................................................. -0.3 V to +7.0 V
Operating Temperature T A (Ambient) ................................................. 0 °C to + 70°C
Storage Temperature (Ambient) (Plastic) ........................................... -55°C to +125°C
Storage Temperature (Ambient) (Cerdip) ........................................... -65°C to +150°C
Power Dissipation. . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............. 1 Watt
Output Current .......................................................................... 20 mA
·Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS
(O°C s T A S + 70°C)

SYM

PARAMETER

MIN

MAX

UNIT

NOTES

VCC

Supply Voltage

4.50

5.50

V

1

GND

Supply Voltage

0

0

V

1

V IH

Logic "1" Voltage All Inputs

2.2

VCC + 0.5V

V

1

V IL

Logic "0" Voltage All Inputs

-0.3

0.8

V

1,6

DC ELECTRICAL CHARACTERISTICS
(O°C S TA S +70°C) (Vcc = 5.0 volts

±

10%)

MK6116
SYM

PARAMETER

Icc1

Average V cc Power Supply Current

Icc2

TTL Standby Current (E :2:: V IH )

ICC3

CMOS Standby Current (E:2::Vcc -0.2V)

IlL

Input Leakage Current (Any Input)

MIN

MAX

MK6116L
MIN

MAX

UNITS

NOTES

70

60

mA

5

15

12

mA

2ma
-1

+1

-5

100p.a
-1

+1

p.A

2
2

IOL

Output Leakage Current

+5

-5

+5

p.A

V OH

Output Logic "1" Voltage (lOUT

=

-1.0 mA)

2.4

Vec +
0.5V

2.4

Vee +
0.5V

V

VOL

Output Logic "0" Voltage (lOUT

=

2.1 mA)

-0.3

0.8

-0.3

0.8

V

V-22

AC ELECTRICAL CHARACTERISTICS
+70°C) (Vcc = 5.0 V ± 10%)

(O°C~TA~

SYM

MK6116/L·15

MK6116/L·20

MK6116/L·25

MIN

MIN

PARAMETER

MIN

t RC

MAX

MAX

Read Cycle Time

150

tAA

Address Access Time

150

200

250

ns

3

tCEA

Chip Enable Access Time

150

200

250

ns

3

tCEZ

Chip Enable Data Off Time

50

60

70

ns

tOEA

Output Enable Access Time

75

100

125

ns

tOEZ

Output Enable Data Off Time

70

ns

tOH

Output Hold from Address Change

200

50

MAX

UNITS NOTES
ns

250

60

15

15

15

ns

150

200

250

ns

0

0

0

ns

160

ns

twc

Write Cycle Time

tAS

Address Setup Time

tCEW

Chip Enable to End of Write

90

120

tAW

Address Valid to End of Write

120

140

180

ns

two

Write Pulse Width

90

120

160

ns

tWR

Write Recovery Time

10

10

10

ns

tWEZ

Write Enable Data Off Time

tos

Data Setup Time

40

60

100

ns

tOH

Data Hold Time

0

0

0

ns

60

60

80

3

ns

CAPACITANCE (T A = 25°C)

SYM

PARAMETER

MAX

NOTES

CI

Capacitance on all pins (except D/O)

7 pF

7

COlO

Capacitance on D/O pins

10 pF

4,7

NOTES:
1. All voltages referenced to GND.
2. Measured with GND sV,sVcc and outputs deselected.
3. Measured with load as shown in Figure 3.
4. Output buffer is deselected.
5. Icc, measured with outputs open.
6. Negative spikes of -1.0 volts allowed for up to 10 ns once per cycle.
7. Effective capacitance calculated from the equation C = I at, with a v = 3 volts
and power supply at nominal level.
N

AC TEST CONDITIONS
Input Levels:
Transition Times:
Input and Output Timing
Reference Levels:

OUTPUT LOAD DIAGRAM
Figure 3
+5V

O.U.T - - - - 4.....- - _

0.6 V to 2.4 V

1.0K n

5 ns

100 pF

(INCLUOING SCOPE ANO JIG)

0.8 V or 2.2 V

V·23

TIMING DIAGRAM
Figure 4

READ

READ

WRITE

t RC

t RC

twc

__
t
-rtmi
AAI I

:J

~

lX

I

..

t'll"I

~tAS

I

w

tAW

C
~

II

I

tWR

I I

TIMING DIAGRAM
Figure 5

WRITE

/ , . . . - -_

WRITE

_

_

~

READ

-1

_
1

to"

I
I

w

V-24

OPERATION

Write Mode

Read Mode

The MK6116/6116L is in the Write Mode whenever the
Wand Einputs are in the lo~ state. The latter occurring
falling edge of either W or E will determine the start of
the Write Cycle. Therefore, tAS ' two, an~ tc~ are
referenced to the latter occurring edge of E or W. The
Write Cycle is terminated by the earlier rising edge of
Eor W. The addresses must be held valid throughout
the cycle. W must return to the high state for a minimum
of tWR prior to the initiation of another cycle.

The MK6116/6116L is in the Read Mode whenever W
(Write Enable) is high and E (Chip Enable) is low, providing a ripple-through access of data from eight of
16,384 locations in the static storage array. Thus, the
unique address specified by the 11 Address Inputs (An)
defines which one of 2048 bytes of data is to be
accessed.
Valid data will be available to the eight Data Output
Drivers within tAA after the !!st add~ss input signal is
stable, providing that the E and G (Output Enable)
access times are satisfied. If E or G access times are
not met, data access will be measured from the limiting
parameter (tCEA or tOEA) rather than the address. The
state of the eight Data I/O signals is controlled by the
E and G control signals. The data lines may be in an
indeterminate state between tOH and tAA , but the data
lines will always have valid data at tAA .

If the output bus has been enabled

(E or Glow), then

Vii will disable the outputs in tWEZ from

its falling edge;
however, care must be taken to avoid a potential bus conten.!i,on. Data-In must be valid tos prior to the rising edge
of E or W_and..must remain valid for tOH after the rising
edge of E or W.

ORDERING INFORMATION

PART NO.
MK6116N-15

ACCESS TIME

PACKAGE TYPE

TEMPERATURE RANGE

150 ns

Plastic

0° to 70°C

MK6116LN-15

150 ns

Plastic

0° to 70°C

MK6116N-20

200 ns

Plastic

0° to 70°C

MK6116LN-20

200 ns

Plastic

0° to 70°C

MK6116N-25

250 ns

Plastic

0° to 70°C

MK6116LN-25

250 ns

Plastic

0° to 70°C

MK6116J-15

150 ns

Cerdip

0° to 70°C

MK6116LJ-15

150 ns

Cerdip

0° to 70°C

MK6116J-20

200 ns

Cerdip

0° to 70°C

MK6116LJ-20

200 ns

Cerdip

0° to 70°C

MK6116J-25

250 ns

Cerdip

0° to 70°C

MK6116LJ-25

250 ns

Cerdip

0° to 70°C

V-25

V-26

B

UNITED

TECHNOLOGIES
MOSTEK

MEMORY
COMPONENTS

512 x 9 BiPORTTM PARALLEL IN-OUT FIFO
MK4501 (N)-8,10
FEATURES

PIN CONNECTIONS - DIP
Figure 1

o First-In, First-Out Dual Port Memory
o Flexible 512 x 9 organization

VIi

o State-of-the-art HCMOS technology
o Asynchronous and simultaneous read/write

o

o High performance

Part No.

Access Time

R/W
Cycle Time

MK4501-8

80 ns

100 ns

W

MK4501-10

100 ns

120 ns

R= Read

3

02

4

25

06

01

5

24

07

DO

6

23

XI
FF

7

22

FLIRT
RS

8

21

EF

00

9

20

XO

Q1

10

19

07

Q2

11

18

06
05

03 12

17

08 13

16

04

GNO 14

15

R

PIN NAMES

= Write

RS = Reset
FL/RT = First Load/Retransmit
D = Data In
00 = Data Out

DESCRIPTION
The M K4501 is a member of the BiPORTTM Memory Series,
which utilizes special two port cell techniques. Specifically,
this device implements a First-In, First-Out algorithm,
featuring asynchronous read/write operations, full and
empty flags, and unlimited expansion capability in both
word size and depth. The main application ofthe MK4501 is
as a rate buffer, sourcing and absorbing data at different
rates, (e.g. interfacing fast processors and slow peripherals).
The full and empty flags are provided to prevent data
underflow and overflow. The data is loaded and emptied on

04
05

03

o Fully expandable by word width or depth

o Retransmit capability

Vee

2

Bidirectional applications

o Empty and full warning flags

28
27
26

08

XI = Expansion In
XO = Expansion Out
FF = Full Flag
EF = Empty Flag
Vee = 5 Volts
GND = Ground

a First-In, First-Out basis (FIFO), and the latency for the
retrieval of data is approximately one load cycle (write).
Since the writes and reads are internally sequential,
thereby requiring no address information, the pinout
definition will serve this and future higher density devices.
The ninth bit is provided to support control or parity
functions.

V-27

V-28

!J

UNITED
TECHNOLOGIES
MOSTEK
512

MEMORY
COMPONENTS

x 9 BiPORTTM PARALLEL IN-OUT FIFO
MK4501 (N)-12,15,20

FEATURES

PIN CONNECTIONS - DIP

o

First-In, First-Out Dual Port Memory

o

Flexible 512 x 9 organization

o

State-of-the-art HCMOS technology

Figure 1

VIi

o

Asynchronous and simultaneous read/write

o

Bidirectional applications

o

Empty and full warning flags

o

Retransmit capability

o

High performance

Part No.

Access Time

R/W
Cycle Time

MK4501-12

120 ns

140 ns

MK4501-15

150 ns

175 ns

MK4501-20

200 ns

235 ns

Vee

04
05

02

4

25

06

01

5

24

07

00

6

FLIRT

Xi
FF

7

23
22

8

21

00 9
01 10
Q2 11

EF
XO

19

07

18

06

20

RS

03 12

17

05

08 13

16

04

GNO 14

15

R

PIN NAMES

W = Write

R = Read
RS = Reset
FL/RT = First Load/Retransmit
D = Data In
00 = Data Out

DESCRIPTION
The MK4501 is a member of the BiPORTTM Memory Series,
which utilizes special two port cell techniques. Specifically,
this device implements a First-In, First-Out algorithm,
featuring asynchronous read/write operations, full and
empty flags, and unlimited expansion capability in both
word size and depth. The main application of the MK4501 is
as a rate buffer, sourcing and absorbing data at different
rates, (e.g. interfacing fast processors and slow peripherals).
The full and empty flags are provided to prevent data

28
27
26

3

Fully expandable by word width or depth

o

2

08
03

Xi' =

Expansion In
XO = Expansion Out
FF = Full Flag
EF = Empty Flag
Vee = 5 Volts
GND = Ground

underflow and overflow. The data is loaded and emptied on
a First-In, First-Out basis (FIFO), and the latency for the
retrieval of data is approximately one load cycle (write).
Since the writes and reads are internally sequential,
thereby requiring no address information, the pinout
definition will serve this and future higher density devices.
The ninth bit is provided to support control or parity
functions.

V-29

•

MK4501 BLOCK DIAGRAM
Figure 2

00-08

DATA INPUTS

READ

512.9

POINTER

DATA OUTPUTS

ao-as
RS

I - - - - t - - -.... EF
1 - - - - + - - -.... FF

L----,.------'

xo

RESET
The MK4501 is reset whenever the Reset Enable Control
input (RS) is in the low state. During a RESET, both the
internal read and write pointers are set to the first location.
A RESET is required after power up before a Write operation
- can begin. Both W andR must be in the high state during a
RESET (refer to the following discussion for required state of
fliRT and Xi).

READ MODE
The MK4501 initiates a READ CYCLE on the falling edge of
Read Enable Control Input (R), provided that the EMPTY
FLAG (EF) is not set. In the READ mode of operation, the
MK4501 provides a fast access of data from 9 of 4608
locations in the static storage array. The data is accessed on
a First In, First Out basis independent of any ongoing WRITE
operations. After if goes high, the data outputs will return to
a high impedance condition until the next READ operation.

In the event that all data has been read from the FIFO, the EF
will go low, and further READ operations will be inhibited
(the data outputs will remain in high imp~ance). Upon
completion of a valid WRITE operation, the EF will go high
after twEF , and a valid READ can begin.

WRITE MODE
The MK4501 initiates a WRITE CYCLE on the falling edge of
the Write Enable Control Input (W) provided that the FULL
FLAG (FF) is not set. Data set-up and hold time
requirements must be satisfied with respect to the rising
edge -of W. The data is stored sequentially and
independently of any ongoing READ operations.
To prevent a data overflow condition, the (FF) will go low,
and further WRITE operations will be inhibited. Upon
completion of a valid READ operation, the FF will go high
after t RFF, and a valid WRITE can begin.

V-30

RESET
Figure 3

~________________ tRS--------------~

_e-_F__________

~~_-_-_-_--_-_t_EF_L~~~~~~~~~
__

____________________t_R_SR______

NOTES:
1. tRSC = tRS + tRSR
2. iN and R = VIH during RESET.

ASYNCHRONOUS WRITE AND READ OPERATION
Figure 4

~--------tRC --------.......------tRpw --....-t

00-08
DATA OUT VALID

~---------------~C-----------~

14------- ~pw ---------;~......- - -

~:

lr=_tD_S_-_-I_ __
t-_-_-_t_D_H__"""'

00-08
------------------{

DATA IN VALID

)----------(

NOTE:
1. tRC = tRR + tRPW
2. twc = tWR + twpw

V-31

DATA IN VALID

•

FULL FLAG FROM LAST WRITE TO FIRST READ
Figure 6

LAST WRITE

FIRST
WRITE

f\
-+ twFF

FF

ADDITIONAL
READS

~/

R

W

FIRST READ

--

------

-'

--

tRFF

;'-

EMPTY FLAG FROM LAST READ TO FIRST WRITE
Figure 6
LAST READ

FIRST WRITE

W

EF

DATA OUT

V·32

ADDITIONAL
WRITES

FIRST
READ

RETRANSMIT
Figure 7
J . + - - - - t R T ----~

J

\

~

~ ....

Fi,W

\

NOTES:
1, tRTC = tRT + tRTR
2,
andFF may change state during retransmit as a resultofthe offset ofthe
read and write pointers, but flags will be valid at tRTC'

EF

RETRANSMIT
BLOCK DIAGRAM OF SINGLE 512 x 9 FIFO

The MK4501 can be made to retransmit data when the
Retransmit Enable Control input (RT) is pulsed low, A
RETRANSMIT operation will set the internal read pointer to
the first location and will not affect the write pointer. Rand
W must be inactive during RETRANSMIT. This feature is
useful when less than 512 Writes are performed between
RESETs. The RETRANSMIT feature is not compatible with
Depth Expansion, (See page 6).

Figure 8

EXPANSION OUT

WRITE

(W)

(R)

SINGLE DEVICE CONFIGURATION
4
5

A single MK4501 may be used when the application
requirements are for 512 words or less, The MK4501 is in a
Single Device Configuration when the Expansion In Control
input (xi) is grounded, (See Figure 8),

o
1

WIDTH EXPANSION
Word width may be increased simply by connecting the
corresponding input control signals of multiple devices.
Status Flags (EF and FF) can be detected from anyone
device. Figure 9 demonstrates an 18-bit word width by
using two MK4501 s. Any word width can be attained by
adding additional MK4501 s.

EXPANSION IN

(xi)

BLOCK DIAGRAM OF 512 x 18 FIFO MEMORY (WIDTH EXPANSION)
Figure 9

XO
OAT

FULL FLAG

RES

---"'-=""---ja.j -

4
5

o
- ' - _.

- -4--

5
I---------l~

0

..,._ _ _ _ _ _-\ __ L_

NOTE:
Flag detection is accomplished by monitoring the FF and IT signals on either
(any) device used in the width expansion configuration, Do not connect any
output control signals together,

V-33

~~~------~

(Ffi'l RETRANSMIT

•

DEPTH EXPANSION (DAISY CHAIN)
3. The Expansion Out (XO) pin of each device must be tied
tothe Expansion In (XI) pin of the next device. See Figure
10.

The MK4501 can easily be adapted to applications when
the requirements are for greater than 512 words. Figure 10
demonstrates Depth Expansion using three MK4501 s. Any
depth can be attained by adding additional MK4501 s. The
MK4501 operates in the Depth Expansion configuration
when the following conditions are met:

4. External logic is needed to generate a composite Full Flag
and Empty Flag. This requires the ORing of all EFs and
the ORing of all FFs. (Le. all must be set to generate the
correct composite FF or EF). See Figure 10.

1. The first device must be designated by grounding the
First Load Control input (FL.).

5. The Retransmit function is not allowed in the Depth
Expansion Mode.

2. All other devices must have FL in the high state.

BLOCK DIAGRAM OF 1536 X9 FIFO MEMORY (DEPTH EXPANSION)
Figure 10

xo

~--~~--+----------------Vcc

V·34

COMPOUND EMPANSION
The two expansion techniques described above can be
applied together in a straight forward manner to achieve
large FIFO arrays. (See Figure 11 ).
BIDIRECTIONAL APPLICATIONS
Applications, which require data buffering between two

s· ~tems (each system capable of READ and WRITE
.Jperations), can be achieved by pairing MK4501 s, as
shown in Figure 12. Care must be taken to assure that the
appropriate flag is monitored by each system. (i.e. FF is
monitored on the device where W is used; EF is monitored
on the device where Ris used.) Both Depth Expansion and
Width Expansion may be used in this mode.

COMPOUND FIFO EXPANSION
Figure 11

MK4501
MK4501
-------I-.fDEPTH EXPANSION ~----II~ DEPTH EXPANSION
BLOCK
BLOCK

R.W.RS

MK4501
DEPTH EXPANSION
BLOCK

NOTES:
1. For depth expansion block see DEPTH EXPANSION Section and Figure 10.
2. For Flag detection see WIDTH EXPANSION Section and Figure 9.

BIDIRECTIONAL FIFO APPLICATION
Figure 12

~---------RB

FF A ~---------i

~------~~ EFB

SYSTEM B

SYSTEM A

RA

---------;~

~---------WB

EF A

.-------------t

B

V-3S

•

RESET AND RETRANSMIT TRUTH TABLE - SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
Table 1

INTERNAL STATUS

INPUTS

OUTPUTS

Mode

RS

RT

XI

Read Pointer

Write Pointer

EF

FF

Reset

0

X

0

Location Zero

Location Zero

0

1

Retransmit

1

0

0

Location Zero

Unchanged

X

X

Read/Write

1

1

0

Increment*

Increment*

X

X

*Pointer will increment if flag is high.
RESET AND FIRST LOAD TRUTH TABLE - DEPTH EXPANSION/COMPOUND EXPANSION MODE
Table 2

INTERNAL STATUS

INPUTS
Mode

t

OUTPUTS

RS

FL

XI

Read Pointer

Write Pointer

EF

FF

Reset-First Device

0

0

t

Location Zero

Location Zero

0

1

Reset all
other Devices

0

1

t

Location Zero

Location Zero

0

1

Read/Write

1

X

t

X

X

X

X

Xi is connected to XO of previous device. See Figure 10.

FL/RT

Reset Input

FF

Full Flag Output

First Load/Retransmit

XI

Expansion Input

Empty Flag Output
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to GND ............................................................ -0.5 V to +7.0 V
Operating Temperature TA (Ambient) ............. , .............................................. O°C to +70°C
Storage Temperature ...................................................................... -55°C to +125°C
Power Dissipation .............................................................. '.................... 1 Watt
Output Current ..................................................................................... 20 mA
'Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device, This is a stress rating only, and functional operation of
the device at these, or any other conditions above those indicated in the operational sections of this specification, is not implied, Exposure to absolute maximum
ratings for extended periods may affect device reliability,

RECOMMENDED D.C. OPERATING CONDITIONS'
(O°C ~ TA :s + 70°C)

SYM PARAMETER
Vee

Supply Voltage

GND Ground

MIN

TYP

MAX

UNITS

4.5

5.0

5.5

V

0

0

0

V

V 1H

Logic "1 " Voltage All Inputs

2.0

Vee + 1

V

V 1L

Logic "0" Voltage All Inputs

-0.3

0.8

V

V-36

NOTES

4

DC ELECTRICAL CHARACTERISTICS'
(O°C :::; TA:::; + 70°C) (Vcc

= 5.0 volts ± 10%)
MIN

MAX

UNITS

NOTES

Input Leakage Current (Any Input)

-1

1

}.LA

5

IOL

Output Leakage Current

-10

10

}.LA

6

V OH

Output Logic "1" Voltage lOUT = -1 mA

2.4

VOL

Output Logic "0" Voltage lOUT = 4 mA

0.4

V

ICC1

Average V cc Power Supply Current

80

mA

3

8

mA

3

500

}.LA

3

TYP

MAX

SYM

PARAMETER

IlL

ICC2

V

~erage Standb~u~nt

(R = W = RST = FLIRT = V IH )
ICC3

Power Down Current (All Inputs = V cc -0.2 V)

•

AC ELECTRICAL CHARACTERISTICS
(O°C :::; TA:::; + 70°C) (V cc

= +5.0 volts ± 10%)

SYM

PARAMETER

CI

Capacitance on Input Pins

7 pF

Co

Capacitance on Output Pins

12 pF

NOTES

2

AC ELECTRICAL CHARACTERISTICS8
(O°C :::; TA :::; + 70°C) (Vcc

= +5.0 volts ± 10%)
4501-12

4501-15

4501-20

SYM

PARAMETER

MIN MAX MIN MAX MIN MAX

t RC

Read Cycle Time

140

tA

Access Time

tRR

Read Recovery Time

20

25

35

ns

tRPW

Read Pulse Width

120

150

200

ns

tRL

Read Pulse Low to Data Bus at Low Z

20

25

25

ns

tov

Data Valid from Read Pulse High

5

5

5

ns

tRHZ

Read Pulse High to Data Bus at High Z

twc

Write Cycle Time

140

175

235

ns

twPw

Write Pulse Width

120

150

200

ns

tWR

Write Recovery Time

20

25

35

ns

175
150

120

ns
200

50

35

V·37

235

UNITS NOTES

60

ns

7

ns

7

AC ELECTRICAL CHARACTERISTICS8 (Cont.)
(O°C :5 TA:::; + 70°C) (Vee

= +5.0 volts ± 10%)
4501-12

4501-15

4501-20

MIN MAX MIN MAX MIN MAX

UNITS NOTES

SYM

PARAMETER

tos

Data Set Up Time

40

50

65

ns

tOH

Data Hold Time

10

10

10

ns

t Rse

Reset Cycle Time

140

175

235

ns

t RS

Reset Pulse Width

120

150

200

ns

t RSR

Reset Recovery Time

20

25

35

ns

tRTe

Retransmit Cycle Time

140

175

235

ns

tRT

Retransmit Pulse Width

120

150

200

ns

tRTR

Retransmit Recovery Time

20

25

35

ns

tEFL

Reset to Empty Flag Low

140

175

235

ns

tREF

Read Low to Empty Flag Low

115

145

195

ns

tRFF

Read High to Full Flag High

110

140

190

ns

tWEF

Write High to Empty Flag High

110

140

190

ns

tWFF

Write Low to Full Flag Low

115

145

195

ns

NOTES:
1. All voltages are referenced to ground.
2. Output buffer is deselected.
3. lee measurements are made with outputs open.
4. 1.5 volt undershoots are allowed for 10 ns once per cycle.

5. Measured with 0.4:S VIN :S Vee.
6. R2: VIH, 0.4:S VOUT:S Vee·
7. Pulse widths less than minimum values are not allowed.
8. Timings referenced as in Figure 14.

OUTPUT LOAD
Figure 13

5V

1.1K
D.U.T. - -__....- - _ .

680n

V-38

30pF

7

7

TRANSITION WAVEFORMS
Figure 14

3.0V - - - - - - - - - -

A-------_ ----------

1.5V - - - - - - - -

oV

3.0V

- - - - - - - 1.5 V - Measurement Point

------_+'''

-------ov

NOTES:
1. Inputs swing 0-3 volts
2. tT = 5 ns.
3. All timing is measured at 1.5 volts
4. Measured with a load shown in Figure 13.

ORDERING INFORMATION

R/W
PART NO.

ACCESS TIME

CYCLE TIME
(CLOCK FREQUENCY)

PACKAGE TYPE

TEMPERATURE RANGE

MK4501-12

120 ns

140 ns (7.1 MHz)

Plastic

0° to 70 0 e

MK4501-15

150 ns

175 ns (5.7 MHz)

Plastic

0° to 70 0 e

MK4501-20

200 ns

235 ns (4.2 MHz)

Plastic

0° to 700 e

V-39

•

V-40

m

UNITED
TECHNOLOGIES
MOSTEK

MEMORY
COMPONENTS
512 x 9 BIPORTTM RAM
MK4511 (N/E)-15

FEATURES

o

512 x 9 bit Dual Port RAM utilizes unique
BiPORTTM Cell/Array

o

Simplifies "multi-processing"

o

Provides convenient method of tightly coupling
microprocessors with "shared store"

o

Usable as "controller" for expansion of "shared
store" multiport systems

o

Requires no external "arbitration" - totally asynchronous operation

o

Symmetrical control functions including Chip
Enable (E), Output Enable (3), and Write Enable

FUNCTIONAL DIAGRAM
Figure 1

ADX 0-8

ADY 0-8

Ey
Gy

(W)

Wy

o

Hardwired INTERRUPT control supports multiport
"handshake" operation

o

Utilizes MOSTEK's high technology HCMOS
process

o

High Speed - 130 ns (Access Time)
150 ns (READ/WRITE)
Cycle Time)

o

Low Power -

PIN CONNECTIONS
Figure 2

ADXs

SO mA (Active)
200 p.A (Standby)

o

2S-pin dual-in-line low cost plastic package

o

Address-Data multiplexing

PIN NAMES

E

G

= Chip Enable
= Output Enable
= Write Enable

W
INT = Interrupt Out

AD
= Address/Data
Vee = 5 Volts
GND = Ground

V-41

28 vee
ADX 4

ADXe

2

27

ADX 7

3

ADXa

4

26 ADX 3
25 ADX 2

\fix
Ex
INT x

5

24 ADX 1

6
7

23

ADXo

22

Gx

INT y

8

Ey

9

Wy

10

Gy
20 ADY o
19 ADY 1
21

ADY a

11

18 ADY 2

ADY 7

12

17

ADY 3

ADY e

13

16

ADY 4

GND

14

15 ADY s

•

V-42

IJ

UNITED

TECHNOLOGIES
MOSTEK

MEMORY
COMPONENTS

2K x 8 BATTERY BACK-UP RAM
MK48C02, MK48C02L (N) -15/20/25
FEATURES
Access Time

R/W
Cycle Time

MK48C02-15
MK48C02L-15

150 ns

150 ns

MK48C02-20
MK48C02L-20

200 ns

200 ns

o No battery drain during normal operating conditions
o Ultra low battery drain during battery back-up

MK48C02-25

250 ns

250 ns

o

Part No.
Ideal Non-Volatile RAM with a single external Lithium
Cell

o Data security provided by automatic write protection
during power failure

o Data retention down to 1 .8 V
o Low battery warning
o Power fail detect Signal available for memory expansion
o Fully static Chip Enable and Output Enable facilitate bus
control
o High performance

PIN CONNECTIONS

BLOCK DIAGRAM

Figure 1

Figure 2

VS1

1

28 Vee

N.C. 2
A7 3
A6 4

27 N.C.

Vee

,-

As
24 Ag

5
6

23 W

I

A3

7

22

G

A2

8

21

A10

I
I
I

A1

9

20

E

I

17 D05
15 D03

Vee

E

G

W

MODE

DQ

POWER

~5.5

V IH

X

X

Deselect

HighZ

Standby

V IL

X

V IL

Write

DIN

Active

;:::::4.75 V IL

V IL

V IH

Read

Dour

Active

V IL

V IH

V IH

Read

HighZ

Active

X

X

X

Write
Protect

HighZ

CMOS
Standby

volts

E = Chip Enable

000 - DQ7 = Data In/Data Out
GND = Ground

W

DOo·D07
~-.;..-- E
i4--+--- W
I
G

TRUTH TABLE

16 D04

Ao - AlO = Address Inputs

VB

POWER
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY

L ______________ J

PIN NAMES

Vee = Power (+5 V)

I

I
I

A5

D02 13
GND 14

I

I

25

19 D~
18 D06

----------1

I

26 PF

A4

Ao 10
DOo 11
D01 12

VB'

-

=Write Enable
G = Output Enable
PF = Power Fail

volts

<4.5
volts

Detect Output

= Battery Inputs
V-43

•

Write Cycle. Therefore, tAs, two' and teEware referenced to
this latter occurring edge of E' or W. The Write Cycle is
terminated by the earlier rising edge of E or W. The
addresses must be held valid throughout the cycle.Wmust
return to the high state for a minimum of tWR prior to the
initiation of another cycle. If the output bus has been
enabled (E and G low), then W will disable the outputs in
tWEZ from its falling edge; however care must be taken to
avoid a potential bus con~nti~ Data-In must be valid tos
prior to the rising edge of E or Wand must remain valid for
tOH after the rising edge of Eor W.

DESCRIPTION
The MK48C02/MK48C02L is a CMOS RAM with integral
power fail support circuitry for battery backup applications.
The fully static RAM uses a HCMOS six transistor cell and is
organized 2K x 8. Included in the device is a feature to
conserve battery energy and a method of providing data
security during Vee transients. Battery voltage is checked
on each power-up with the status communicated via the
V LB pin. A precision voltage detector, nominally set at 4.60
volts, write-protects the RAM to prevent inadvertent loss of
data when Vee is out of.tolerC!!l,ce. In this way, all input and
output pins (including E and W) become "don't care". The
device permits full functional ability of the RAM for Vee
above 4.75 volts, provides write protection for Vee less
than 4.50 volts, and maintains data in the absence of Vee
with no additional support circuitry other than a primary
cell. The current supplied by the battery during data
retention is for junction leakage only (typically less than 5
na) because all power-consuming circuitry is turned off. The
low battery drain allows the use of a long life Lithium
primary cell.

Data Retention Mode
In the normal mode of operation, the MK48C021
MK48C02L operates as a static RAM. However, Vee is
being constantly monitored. Should the supply voltage
decay, the RAM will automatically write-protect itself in the
Vee range between 4.75 and 4.50 volts as long as the slew
@!e (tf ) specification is satisfied. The open collector output,
Ef, will go low when the RAM is write-protected. By holding
E or W above V 1H for a minimum of tpo before power-down,
incomplete write cycles to the RAM will be avoided. Once
Vee falls below 4.50 volts, all inputs to the RAM become
"don't care" and may be as high as 5.50 volts.

OPERATION
Read Mode
The MK48C02/MK48C02L is in the Read Mode whenever
W (Write Enable) is high and E (Chip Enable) is low,
providing a ripple-through access of data from eight of
16,384 locations in the static storage array. Thus, the
unique address specified by the 11 Address Inputs (An)
define which one of 2048 bytes of data is to be accessed.
Valid data will be available to the eight Data Output Drivers
within tAA after the last address input signal is stable,
providing that the E and G(Output Enable) access times are
satisfied.lfE or IT access times are not met, data accesswill
be measured from the limiting parameter (teEA or tOEA)
rather than the address. The state of the eight Data 1/0
signals is controlled by the E and G control signals. The data
lines may be in an indeterminate state betweent OH andtAA,
but the data lines will always have valid data at t AA .
Write Mode
The MK48C02/MK48C02L is in the Write Mode whenever
the WandE inputs are in the low state. The latter occurring
falling edge of either W or E will determine the start of the

As Vee falls below approximately 3.0 volts, the power
switching circuit connects the external energy source to
supply power to the RAM. In the Data Retention mode, the
current drain on the energy source will be less than IBAT
max.
This redundant battery scheme has been provided to
enhance data retention reliability. If only one battery is used,
VB, and VB 2 should be connected together.
When Vee rises above approximately 3.0 volts, the power
switching circuit connects external Vee to the RAM and
disconnects the external energy source. As Vee rises from a
4.50 to 4.75 volts, the exte!:!:l& energy source is checked. If
the voltage is belowV LB , a BOK(BatteryOK)flag will beset.
Normal RAM operation can resume tREe after Vee exceeds
4.75 volts. Whenever Vee is between 4.50 and4.75 volts, E
or W must be in the high state to prevent inadvertant write
cycles. The BOK flag can be checked on the first write cycle
after a power-up. This write cycle will not be executed if
either battery is below V LB .

V·44

ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to Vss .................................. ~ ......................... -0.3 V to +7.0 V
Operating Temperature TA (Ambient) ............................................................ O°C to + 70°C
Storage Temperature (Ambient) .............................................................. -55°C to +125°C
Power Dissipation .................................................................................. 1 Watt
Output Current ..................................................................................... 20 mA
'Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational section of this specification is nol implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS
(O°C:::; TA :::; +70°C)

SYM

PARAMETER

MIN

MAX

UNITS

NOTES

Vcc

Supply Voltage

4.75

5.50

V

1

GND

Supply Voltage

0

0

V

1

V IH

Logic "1" Voltage All Inputs

2.2

Vcc + 0.5 V

V

1

V IL

Logic "0" Voltage All Inputs

-0.3

0.8

V

1,6

VB

Battery Voltage

1.8

3.5

V

1,7

V LB

Low Battery Warning (lLOAD

1.8

2.4

V

1

l::"VB

Battery Switch Differential Voltage

0.7

V

MAX

UNITS

NOTES

80

mA

5

3

mA

1

mA

= 1OI-'A)

DC ELECTRICAL CHARACTERISTICS
(O°C :::; TA :5 + 70°C) (Vcc = 5.0 volts + 100A> - 5%)

MIN

SYM

PARAMETER

ICC1

Average V cc Power Supply Current

ICC2

TTL Standby Current (E

ICC3

CMOS Standby Current (E ;::: V cc - 0.2 V)

IlL

Input Leakage Current (Any Input)

-1

+1

~

2

IOL

Output Leakage Current

-5

+5

~

2

V OH

Output Logic "1" Voltage (lOUT

=-1.0 mAl
Output Logic "0" Voltage (lOUT = 2.1 rnA)
PF Logic "0" Voltage lOUT = 50 ~

2.4

VOL
V pFL
IBAT

ICHG

= VIH)

Battery Back-Up Current
VB = 3.5 V, Vcc =0 V

I MK48C02L
I MK48C02
-5

Battery Charging Current
VB = 1.8 V, Vcc = 5.5 V

V-45

V
0.4

V

0.4

V

1

~

50

~

+5

na

AC ELECTRICAL CHARACTERISTICS
(O°C :5TA :5 +70°C) (Vcc = 5.0 V + 10% - 5%)
MK48C02-20
MK48C02L-20

MK48C02-15
MK48C02L-1S
SYM PARAMETER

MIN

MIN

MAX

MAX

MK48C02-25
MIN

MAX

ns

250

200

UNITS NOTES

t RC

Read Cycle Time

tAA

Address Access Time

150

200

250

ns

3

tCEA

Chip Enable Access Time

150

200

250

ns

3

tCEZ

Chip Enable Data Off Time

35

40

50

ns

tOEA

Output Enable Access Time

70

80

90

ns

tOEZ

Output Enable Data Off Time

35

40

50

ns

tOH

Output Hold from Address
Change

15

15

15

ns

twc

Write Cycle Time

150

200

250

ns

tAs

Address Setup Time

0

0

0

ns

tCEW

Chip Enable to End of Write

90

120

160

ns

tAW

Address Valid to End of Write

120

140

180

ns

two

Write Pulse Width

90

120

160

ns

tWR

Write Recovery Time

10

10

10

ns

tWEZ

Write Enable Data Off Time

tos

Data Setup Time

40

60

100

ns

tOH

Data Hold Time

0

0

0

ns

150

60

50

80

3

ns

CAPACITANCE
= 25°C)

(TA

SYM

PARAMETER

MAX

NOTES

CI

Capacitance on all pins (except 0/0)

7 pF

8

COlO

Capacitance on 0/0 pins

10 pF

4,9

NOTES:
1. All voltages referenced to GND.
2. Measured with GND::::; VI::::; VCC and outputs deselected.
3. Measured with load as shown in Figure 3.
4. Output buffer is deselected.
5. ICC1 measured with outputs open.
6. Negative spikes of -1.0 volts allowed for up to 10 ns once per cycle.
7. Battery voltages below VB min may allow loss of data.
8. Effective capacitance calculated from the equation C = I lit. with IIV = 3 volts
and power supply at nominal level.
X\T

OUTPUT LOAD DIAGRAM
Figure 3

D.U.T

5V

----1It----e
1.0K n

100 pF
(INCLUDING SCOPE AND JIG)

AC TEST CONDITIONS
Input Levels:
Transition Times:
Input and Output Timing
Reference Levels:

0.6 V to 2.4 V
5 ns
0.8 V or 2.2 V

V-46

TIMING DIAGRAM
Figure 4

t

G

Vi

-J.o"

0°0 .0°7

WRITE

READ

READ
~-- t RC ---~

....1 - - - - t RC ------!~

....1 - - - -

twc ------!~

I I
-.J

tOH

VALID OUT

TIMING DIAGRAM
Figure 5

WRITE

WRITE

k=

READ

twc--~ ~--twc---I"~'---',C

-

E

-G

/ - - - - - - 1-1~"
~

t
I

W

VALID
IN

DOa·D~

V-47

POWER·DOWN, POWER·UP CONDITIONS
Figure 6
vcc-----~

------

-1

tRB

PF
(with 87K

h---

fI------...J~
11

EorW---..1

n pullup resistor)

J~------------~,

LEAKAGE CURRENT _________________
IBAT SUPPLIED FROM

t.

tpFR . . -

,----

).-.. . -------~~______. . ._______
-

V B1 OR V B2

POWER·DOWN/POWER·UP TIMING

(O°C :5 TA :5 +70°C)
SYM

PARAMETER

tpD

E or W at V 1H before Power Down

tF

Vee slew from 4.75 V to 4.50 V (E or W at V 1H )

tFB

MIN

MAX

UNITS

NOTES

0

IJ.S

300

IJ.S

Vee slew from 4.50 to 3.0 V

10

IJ.S

tRB

Vee slew from 3.0 V to 4.50 V

1

IJ.S

tR

Vee slew from 4.50 to 4.75 V

0

IJ.S

tREe

E or W at V 1H after Power Up

2

ms

tpFF

PF at logic '0' (Vee :5 4.50 V)

0

ns

1,2

tpFR

PF at logic '1' (Vee ~4.75 V)

2

ms

2

NOTES:
1.
starts to go low when Vee
when Vee::; 4.50 v.

PF

(E or W at V 1H )

WARNING: Under no circumstances are negative

< 4.75 V. It is guaranteed to be at a logic '0'

Vce = 4.75 V

2. Measured with load

Pin26~87KO

D.U.T.

10pF

V·48

undershoots, of any amplitude, allowed when device is
in battery backup mode.

"N
cO" "

~ )C

~CX)
OJ

:~

Vee

:

n=i
:

ROW

tj

DECODER.

~

m

::JJ

MAm~

-<

OJ

»
0

MEMORY
128 x 128

"

C.
"tI

::JJ

»
~

POWER
SWITCHING
CIRCUIT

DDu

I

l
D~

I

VB

INPUT
DATA
CONTROL

••

COLUMN 1/0
COLUMN DECODER

••

"'T1

c

:2
0
-t

0

:2

»
r-

INTERNAL
Vee

C

i>

G)

,::

::JJ

»

01::0

co

~

G~
VOLTAGE
REFERENCE
AND
COMPARATOR

CONTROL
LOGIC

80K
POK
E o------+--L----

PF
Ao A1

Ag A 10

ORDERING INFORMATION
TEMPERATURE RANGE

ACCESS TIME

PACKAGE TYPE

MK48C02N-15

150 ns

Plastic

0° to 70°C

MK48C02LN-15

150 ns

Plastic

0° to 70°C

MK48C02N-20

200 ns

Plastic

0° to 70°C

MK48C02LN-20

200 ns

Plastic

0° to 70°C

MK48C02N-25

250 ns

Plastic

0° to 70°C

PART NO.

V-50

II

UNITED
TECHNOLOGIES
MOSTEK

MEMORY
COMPONENTS
2K x 8 ZEROPOWERTM RAM
MK48Z02 (8) -15/20/25
PIN NAMES

FEATURES
o Data retention in the absence of power
o Data security provided by automatic write protection
during power failure
o Direct replacement for volatile 2K x 8 Byte Wide Static
RAM

Ao - A,o

Address Inputs Vcc System Power (+5 V)

E

Chip Enable

W

Write Enable

GND

Ground

G

Output Enable

o +5 Volt only Read/Write
DCa - DQ7 Data In/Data Out

o Unlimited write cycles
o CMOS - 440 MW active; 5.5 MW standby

PIN CONNECTIONS
Figure 1

o 24-Pin Dual in Line package, JEDEC pinout
o Read cycle time equals write cycle time
o Low Battery Warning
Part No.

R/W
Cycle Time

A7

24

Vcc

Access Time

A6

2

23

As

250 nsec

250 nsec

As

3

22

A9

A4

4

21

W

MK48Z02-25
MK48Z02-20

200 nsec

200 nsec

MK48Z02-15

150 nsec

150 nsec

DESCRIPTION
The MK48Z02 is a 16,384-bit, Non-Volatile Static RAM,
organized 2K x 8 using HCMOS and an integral Lithium
energy source. The ZEROPOWERTM RAM has the
characteristics of a CMOS static RAM, with the important
added benefit of data being retained in the absence of
power. Data retention current is so small that a miniature
Lithium cell contained within the package provides an
energy sou rce to preserve data. Low cu rrent dra i n has been
attained by the use of a full CMOS memory cell, novel
analog support circuitry, and carefully controlled junction
leakage by an all implanted CMOS process. Safeguards

I

E

G

W

MODE

DQ

POWER

:::;5.5
volts

V IH

X

X

Deselect

HighZ

Standby

V IL

X

V IL

Write

DIN

Active

V IL

V IL

V IH

Read

Dour

Active

V IL

VIH

VIH

Read

HighZ

Active

X

X

X

Write
Protect

High

Zero

<4.5
volts

20

G

6

19

A,o

A,

7

18

E

17

D~

Ao

8

DOo
DO,

9

16

D06

10

15

J<)os

D0 2
GND

11

14

D04

12

13

D03

,------------1

VCC

volts

5

BLOCK DIAGRAM
Figure 2

TRUTH TABLE

~4.75

A3
A2

ZEROPOWERTM is a trademark of Mostek Corporation.

:
I
I
I
I

I

I

I, utM

T+
f

•

VOLTAGE SENSE

POWER

~

AND
~
SWITCHING'------------CIRCUITRY
BOK

2K"S

CR':~S

J

AO·A'O

~I

CEll

±___

~.

L __________

V-51

i

K

CELL

000007

II

~

I

G

I

J

W

against inadvertent data loss have been incorporated to
maintain data integrity during the uncertain operating
environment associated with power-up and power-down
transients. The ZEROPOWERTM RAM can replace existing
2K x 8 static RAM, directly conforming to the popular Byte
Wide 24-pin DIP package (JEDEC). MK48Z02 also matches
the pinning of 2716 EPROM and 2K x 8 E2PROM. Like other
static RAM, there is no limit on the number of write cycles
that can be performed. Since the access time, read cycle,
and write cycle are less than 250 ns and require +5 volts
only, no additional support circuitry is needed to interface to
a microprocessor.
OPERATION

If the output bus has been enabled (E and G low), then W
will disable the outputs in tWEZ from its falling edge;
however, care must be taken to avoid a potential bus
contention. Data-In must be valid tos prior to the rising edge
ofE orWand must remain validfort OH after the rising edge
of E orW.
Data Retention Mode
The ZEROPOWERTM RAM provides full functional capability
for Vee above 4.75 volts, guarantees write protection for
Vee less than 4.50 volts, maintains data in the absence of
Vee' and needs no additional support circuitry. The block
diagram shown in Figure 7 illustrates this self-contained
solution.

Read Mode
The MK48Z02 is in the Read Mode whenever W (Write
Enable) is high and E (Chip Enable) is low, providing a
ripple-through access of data from eight of 16,38410cations
in the static storage array. Thus, the unique address
specified by the 11 Address Inputs (An) defi nes wh ich one of
2048 bytes of data is to be accessed.
Valid data will be available to the eight Data Output Drivers
within tAA after the last address input signal is stable,
providing that the E and G(Output Enable) access times are
satisfied. If Eor Gaccess times are not met, data access will
be measured from the limiting parameter (teEA or tOEA)
rather than the address. The state of the eight Data I/O
signals is controlled by the E and Gcontrol signals. The data
lines may be in an indeterminate state between tOH andtAA,
but the data lines will always have valid data at tAA .
Write Mode
The MK48Z02 is in the Write Mode whenever the Wand E
inputs are in the low state. The latter occurring falling edge
of either VI! or E will determine the start of the Write Cycle.
Therefore, t AS ' two' and teEw are referenced to the latter
occurring edge of E or W. The Write Cycle is terminated by
the earlier rising edge ofE orW. The addresses must be held
valid throughout the cycle. W must return to the high state
for a minimum oftWR priortothe initiation of another cycle.

The MK48Z02 constantly monitors Vee. Should the supply
voltage decay, the RAM will automatically write-protect
itself in the Vee range between 4.75 and 4.50 volts (Figure
6). Once Vee falls below 4.50 volts, all inputs to the RAM
become "DON'T CARE" (-0.3 $ V 1N $ 5.5 volts), and all
outputs are high impedance.
During power-up, when Vee rises above approximately 3.0
volts, the power switching circuit connects external Vee to
the RAM and disconnects the Lithium cell. As Vee rises
from 4.50 to 4.75 volts, the Lithium cell is checked; if the
voltage is below 2.0 V, a flag will be set. Normal RAM
operation ca n resu me after Vee exceeds 4.75 volts. The flag
can be checked on the first write cycle after a power-up.
This first write cycle will not be executed if a Lithium cell has
been depleted, thereby warning of an impending data loss.
This can be easily implemented in a power-up.
As Vee falls below approximately 3.0 volts, the power
switching circuit connects the internal Lithium power
source to the memory matrix, maintaining the voltage
required to retain data. Junction leakage is the only current
consumption mechanism in the data retention mode. The
internal Lithium source supplies this current, which is
typically 300 pA at room temperature.

V-52

ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to Vss ............................................................ -0.3 V to +7.0 V
Operating Temperature TA (Ambient) ............................................................ O°C to + 70°C
Storage Temperature (Ambient) ............................................................... -20°C to +70°C
Power Dissipation .................................................................................. 1 Watt
Output Current ..................................................................................... 20 rnA
'Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
CAUTION: Under no conditions can the "Absolute Maximum Rating" forthe voltage on any pin be exceeded since it will cause permanent damage. Specifically, do
not perform the "standard" continuity test on any input or output pin, i.e. do not force these pins below -0.3 V DC.

RECOMMENDED DC OPERATING CONDITIONS
(O°C ::5 TA ::5 + 70°C)
SYM

PARAMETER

MIN

MAX

UNITS

NOTES

VCC

Supply Voltage

4.75

5.50

V

1

GND

Supply Voltage

0

0

V

1

V IH

Logic "1 " Voltage All Inputs

2.2

Vcc+0.5V

V

1

V IL

Logic "0" Voltage All Inputs

-0.3

0.8

V

1,6

MIN

MAX

UNITS

NOTES

80

rnA

5

3

rnA

1

rnA

DC ELECTRICAL CHARACTERISTICS
(O°C :::; TA:::; + 70°C) (V cc = 5.0 volts + 10% - 5%)
SYM

PARAMETER

ICCl

Average V cc Power Supply Current

ICC2

TTL Standby Current

ICC3

CMOS Standby Current (E ~ V CC - 0.2 V)

IlL

Input Leakage Current (Any Input)

-1

+1

J.LA

2

IOL

Output Leakage Current

-5

+5

J.LA

2

V OH

Output Logic "1 .. Voltage (lOUT

= -1.0 rnA)

VOL

Output Logic "0" Voltage (lOUT

= 2.1

(E =V IH )

V

2.4

V

0.4

rnA)

AC ELECTRICAL CHARACTERISTICS
(O°C:::; TA :::; +70°C) (Vcc = 5.0 V+ 10% - 5%)
MK48Z02-15 MK48Z02-20 MK48Z02-25
SYM

PARAMETER

MIN

t RC

Read Cycle Time

150

tAA

Address Access Time

150

200

250

ns

3

tCEA

Chip Enable Access Time

150

200

250

ns

3

tCEZ

Chip Enable Data Off Time

35

40

50

ns

tOEA

Output Enable Access Time

70

80

90

ns

tOEZ

Output Enable Data Off Time

35

40

50

ns

MAX

MIN

MAX

MAX UNITS

250

200

V-53

MIN

NOTES

ns

3

AC ELECTRICAL CHARACTERISTICS (Cont.)
(O°C ~TA ~ +70°C) (Vcc = 5.0 V + 10% - 5%)
MK48Z02-15 MK48Z02-20 MK48Z02-25
SYM

PARAMETER

tOH

Output Hold from Address Change

15

15

15

ns

twc

Write Cycle Time

150

200

250

ns

tAs

Address Setup Time

0

0

0

ns

tcEW

Chip Enable to End of Write

90

120

160

ns

tAW

Address Valid to End of Write

120

140

180

ns

two

Write Pulse Width

90

120

160

ns

tWR

Write Recovery Time

10

10

10

ns

tWEZ

Write Enable Data Off Time

tos

Data Setup Time

40

60

100

ns

tOH

Data Hold Time

0

0

0

ns

MIN

MAX

MIN

MAX

MIN

60

50

MAX UNITS

80

NOTES

ns

CAPACITANCE (T A = 25°C)
SYM

PARAMETER

MAX

NOTES

CI

Capacitance on all pins (except D/O)

7 pF

8

COlO

Capacitance on D/O pins

10 pF

4,8

NOTES:
1. All voltages referenced to GNO.
2. Measured with GNO S VI S VCC and outputs deselected.
3. Measured with load as shown in Figure 3.
4. Output buffer is deselected.
5. ICCl measured with outputs open.
6. Negative spikes of -1.0 volts allowed for up to 10 ns once per cycle.
7. Each MK48Z02 is marked with a 4 digit data code XXYY. XX designates the
year of manufacture andYY designates the week in that year. Example 8340
would be interpreted as year 1983 week 40 or September 25. 1983. The
expected tOR is defined as starting at date of manufacture and proceeding
without interruption.
8. Effective capacitance calculated from the equation C = 16t. with 6 = 3 volts
and power supply at nominal level.
6V

Figure 3

+5V

D.U.T - - -....----e

AC TEST CONDITIONS
Input Levels:
Transition Times:
Input and Output Timing
Reference Levels:

OUTPUT LOAD DIAGRAM

100 pF

0.6 V to 2.4 V
5 ns

(INCLUDING SCOPE AND JIG)

0.8Vor 2.2 V

V-54

TIMING DIAGRAM
Figure 4

READ

-

-

t RC

~

READ

WRITE

t RC

twc

~

~~"I

~

K=

D(

~tAAI

4. r-I

I

tAS
tAW

1."11"I

~

II

I

twR

I I
Vii

TIMING DIAGRAM
Figure 5
WRITE
~---twc ---"~I

WRITE

READ

~--twc--~~--

W
twEZ

VALID
OUT

DOa -Da..,

V-55

POWER-DOWN, POWER-UP CONDITIONS
Figure 6

4.75 V
4.50V

1-

3.0V

EorW
LEAKAGE CURRENT
IL SUPPLIED FROM
LITHIUM CELL

-t~­

----JJt'\~t"1_----1 J----~It"r
-~
________..JIJr---1!
/I---(

DATA RETENTION TIME

..

~I--------

tOR

...

POWER-DOWN/POWER-UP TIMING
(O°C:::; TA :::; +70°C)
SYM

PARAMETER

tpo

E or W at V IH before Power Down

tF

Vee slew from 4.75 V to 4.50 V (E or W at V IH )

tFB

MIN

MAX

UNITS

0

",,5

300

",,5

Vee slew from 4.50 V to 3.0 V

10

",,5

tRB

Vee slew from 3.0 V to 4.50 V

1

",,5

tR

Vee slew from 4.50 V to 4.75 V (E or W at V IH )

0

",,5

tREe

E or W at V IH after Power Up

2

ms

SYM

PARAMETER

tOR

Expected Data Retention Time

MIN

10

MAX

NOTES

UNITS

NOTES

years

7

WARNING:
Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode.

V-56

."N

cO' m
::D
Cil 0
s:::

-...J"U

o

~

m

::D
::D

l>

s:

A2 0

ROW
DECODER

I ••

"2

C

MEMORY MATRIX
128 x 128

~

A8 0

Vee

o2
l>

rC
DOo
INPUT I
DATA
CONTROL

POWER
SWITCHING
CIRCUIT
D~

.,::
U1
.....

••

COLUMN I/O
COLUMN DECODER

INTERNAL
Vee
--1...-

l
G
VOLTAGE
REFERENCE
AND
ICOMPARATOR

CONTROL
LOGIC

W
BOK
POK

E

Ao A,

Ag A,o

••

~

G>

::D

l>

s:

ORDERING INFORMATION
ACCESS TIME

PACKAGE TYPE

TEMPERATURE RANGE

MK48Z02B-15

150 ns

Plastic

0 0 to 70°C

MK48Z02B-20

200 ns

Plastic

0 0 to 70°C

MK48Z02B-25

250 ns

Plastic

0° to 70°C

PART NO.

V-58

1984/1985 MICROELECTRONIC DATA BOOK

l!

UNITED
TECHNOLOGIES
MOSTEK

MICROCOMPUTER
COMPONENTS

16-BIT MICROPROCESSOR
MK68000

Advances in semiconductor technology have provided the
capability to place on a single silicon chip a microprocessor
at least an order of magnitude higher in performance and
circuit complexity than has been previously available. The
MK68000 is the first of a family of such VLSI microprocessors from Mostek. It combines state-of-the-art
technology and advanced circuit design techniques with
computer sciences to achieve an architecturally advanced
16-bit microprocessor.

II

The resources available to the MK68000 user consist of the
following:
•
•
•
•
•
•

17 32-Bit Data and Address Registers
16 Megabyte Direct Addressing Range
56 Powerful Instruction Types
Operations on Five Main Data Types
Memory Mapped liD
14 Addressing Modes

PIN ASSIGNMENT

PROGRAMMING MODEL
31

1615

87

~

I

I
I

~

I
I

~

I

f-

I

l-

I
I

I

I

I

l-

~

I
I
I
I

o

0

-

I

-

,r-

I

f-

I

f-

-

02
03 EIGHT
DATA
04 REGISTERS

06

02

07

01

08

DO

09

AS

010

UOS

011

lOS

012

06

R/iN

013

OTACK

BGACK

-

BR

A23

Vee
ClK

A22

GNO
HALT

Vee
A20

RESET

A19

VMA

A5

-

A6

VPA

PROGRAM
COUNTER

ISYSTEM BYTE! USER BYTE

0

I

A21

A1B
A17

TWO STACK
POINTERS

87

015

A1
SEVEN
A3 ADDRESS
A4 REGISTERS

-

014

GNO

AO

A2

I

15

05

03

05

07

-

I
I

04

iiG

1615

I

01

-

31

r-

DO

-

STATUS
REGISTER

VI-1

A16

BERR

A15

IPl2

A14

iffi

A13

IPlO

A12

FC2

A11

FC1

A10

FCO

A9

A1

A8

A2

A7

A3

A6

A4

A5

Included in the register indirect addressing modes is the
capability to do postincrementing, predecrementing, offsetting and indexing. Program counter relative mode can
also be modified via indexing and offsetting.

As shown in the programming model, the MK68000 offers
seventeen 32-bit registers in addition to the 32-bit program
counter and a 16-bit status register. The first eight registers
(00-07) are used as data registers for byte (8-bit), word
(16-bit), and long word (32-bit) data operations. The second
set of seven registers (AO-A6) and the system stack pointer
may be used as software stack pointers and base address
registers. In addition, these registers may be used for word
and long word address operations. All 17 registers may be
used as index registers.

The MK68000 instruction set is shown in Table 2. Some
additional instructions are variations, or subsets, of these
and they appear in Table 3. Special emphasis has been
given to the instruction set's support of structured highlevel languages to facilitate ease of programming. Each
instruction, with few exceptions, operates on bytes, words,
and long words and most instructions can use any of the 14
addressing modes. Combining instruction types, data types,
and addressing modes, over 1000 useful instructions are
provided. These instructions include signed and unsigned
multiply and divide, "quick" arithmetic operations, BCD
arithmetic and expanded operations (through traps).

A 23-bit address bus provides a memory addressing range
of greater than 16 megabytes. This large range of
addressing capability, coupled with a memory management
unit, allows large, modular programs to be developed and
operated without resorting to cumbersome and time
consuming software bookkeeping and paging techniques.

DATA ADDRESSING MODES

The status register contains the interrupt mask (eight levels
available) as well as the condition codes; extend (X),
negative (N), zero (Z), overflow (V), and carry (C). Additional
status bits indicate that the processor is in a trace (T) mode
and/or in a supervisor (S) state.

Table 1

Mode

Five basic data types are supported. These data types are:
•
•
•
•
•

Bits
BCD Digits (4-bits)
Bytes (8-bits)
Word (16-bits)
Long Words (32-bits)

Register Direct
Register Indirect
Absolute
Immediate
Program Counter Relative
Implied

STATUS REGIST!;:R
USER BYTE

Absolute Data Addressing
Absolute Short
Absolute Long

EA = (Next Word)
EA = (Next Two Words)

EA
EA
An
EA

= (An)
= (An), An -An + N
- An - N, EA = (An)
= (An) + d16

EA

= (An) + (Xn) + da

Immediate Data Addressing
Immediate
Quick Immediate

DATA = Next Word(s)
Inherent Data

Implied Addressing
Implied Register

EA = SR, USP, SP, PC

NOTES:

d'6 =Sixteen-bit Offset
(displ acement)
EA = Effective Address
N = 1 for Byte, 2 for
An = Address Register
Word, and 4 for Long
Dn = Data Register
Word. If An is the
Xn = Address or Data Register
Stack Pointer and
used as Index Register
the operand size is
SR = Status Register
byte, N = 2 to keep
PC = Program Counter
the Stack Pointer
( ) = Contents of
on a word boundary.
da = Eight-bit Offset
Replaces
(displacement)

ali

SUPERVISOR
STATE

EA= Dn
EA=An

Register Indirect Addressing
Register Indirect
Postincrement Register Indirect
Predecrement Register Indirect
Register Indirect with Offset
Indexed Register Indirect with
Offset

The 14 addressing modes, shown in Table 1, include six
basic types:

SYSTEM BYTE

Register Direct Addressing
Data Register Direct
Address Register Direct

Program Counter Relative
Addressing
EA = (PC) + d16
Relative with Offset
Relative with Index and Offset EA = (PC) + (Xn) + da

In addition, operations on other data types such as memory
addresses, status word data, etc., are provided for in the
instruction set.

•
•
•
•
•
•

Generation

NEGATIVE
ZERO
OVERFLOW
CARRY

VI-2

INSTRUCTION SET
Table 2

Mnemonic Description

Mnemonic

Description

Mnemonic

Description

ABCD
ADD
AND
ASL
ASR

EOR
EXG
EXT
JMP
JSR
LEA
LINK
LSL
LSR
MOVE
MOVEM
MOVEP
MULS
MULU
NBCD

Exclusive Or
Exchange Registers
Sign Extend
Jump
Jump to Subroutine
Load Effective Address
Link Stack
Logical Shift Left
Logical Shift Right
Move
Move Multiple Registers
Move Peripheral Data
Signed Multiply
Unsigned Multiply
Negate Decimal with
Extend
Negate
No Operation
One's Complement
Logical Or

PEA
RESET
ROL
ROR
ROXL
ROXR
RTE
RTR
RTS
SBCD
See
STOP
SUB
SWAP
TAS

Push Effective Address
Reset External Devices
Rotate Left without Extend
Rotate Right without Extend
Rotate Left with Extend
Rotate Right with Extend
Return from Exception
Return and Restore
Return from Subroutine
Subtract Decimal with Extend
Set Conditional
Stop
Subtract
Swap Data Register Halves
Test and Set Operand

TRAP
TRAPV
TST
UNLK

Trap
Trap on Overflow
Test
Unlink

Bee
BCHG
BCLR
BRA
BSET
BSR
BTST
CHK
CLR
CMP
DBee
DIVS
DIVU

Add Decimal with Extend
Add
Logical And
Arithmetic Shift Left
Arithmetic Shift Right
Branch Conditionally
Bit Test and Change
Bit Test and Clear
Branch Always
Bit Test and Set
Branch to Subroutine
Bit Test
Check Register Against
Bounds
Clear Operand
Compare

NEG
Test Condition, Decrement NOP
NOT
and Branch
OR
Signed Divide
Unsigned Divide

VARIATIONS OF INSTRUCTION TYPES
Table 3

Instruction
Type
ADD

AND

Variation
ADD
ADDA
ADDQ
ADDI
ADDX
AND
ANDI
ANDI to CCR
ANDI to SR

CMP

CMP
CMPA
CMPM
CMPI

Description

Instruction
Type

Variation

Add
Add Address
Add Quick
Add Immediate
Add with Extend
Logical And
And Immediate
AND Immediate to
Condition Codes
AND Immediate to
Status Register

MOVE

MOVE
MOVEA
MOVEQ
MOVE from SR
MOVE to SR
MOVE to CCR
MOVE USP

MOVE
Move Address
Move Quick
Move from Status Register
Move to Status Register
Move to Condition Codes
Move User Stack Pointer

Compare
Compare Address
Compare Memory
Compare Immediate

NEG

NEG
NEGX
OR
ORI
ORI to CCR

Negate
NeQate with Extend
Logical Or
Or Immediate
Or Immediate to
Condition Codes
OR Immediate to Status
Register

OR

ORI to SR

EOR

Description

EOR
Exclusive Or
EORI
Exclusive Or Immediate
EORI to CCR Exclusive OR Immediate
to Condition Codes
EORI to SR Exclusive OR Immediate
to Status Register

SUB

VI·3

SUB
SUBA
SUBI
SUBQ
SUBX

Subtract
Subtract Address
Subtract Immediate
Subtract Quick
Subtract with Extend

•

DATA ORGANIZATION AND ADDRESSING
CAflABILITIES

having an even address the same as the word, as shown in
Figur~ 1 . The low order byte has an odd address that is one
count higher than the word address. Instructions and
multibyte data are accessed only on word (even byte)
boundaries. If a long word datum is located at address n (n
even), then the second word of that datum is located at
address n + 2.

The following paragraphs describe the data organization
and addressing capabilities of the MK68000.
OPERAND SIZE

The data types supported by the MK68000 are: bit data,
integer data of 8, 16, or 32 bits, 32-bit addresses and binary
coded decimal data. Each of these data types is put in
memory, as shown in Figure 2.

Operand sizes are defined as follows: a byte equals 8 bits, a
word equals 16 bits, and a long word equals 32 bits. The
opera nd size for each instruction is either expl icitly encoded
in the instruction or implicitly defined by the instruction
operation. All explicit instructions ~upport byte, word or long
word operands. Implicit instructions support some subset of
all three sizes.

ADDRESSING
Instructions for the MK68000 contain two kinds of
information: the type of function to be performed, and the
location of the operand(s) on which to perform that function.
The methods used to locate (address) the operand(s) are
explained in the following paragraphs.

DATA ORGANIZATION IN REGISTERS
The eight data registers support data operands of 1, 8, 16, or
32 bits. The seven address registers together with the active
stack pointer support address operands of 32 bits.

Instructions specify an operand location in one of three
ways:

DATA REGISTERS. Each data register is 32 bits wide.
Byte operands occupy the low order 8 bits, word operands
the low order 16 bits, and long word operands the entire 32
bits. The least significant bit is addressed as bit zero; the
most significant bit is addressed as bit 31.

Register Specification - the number of the register is given
in the register field of the instruction.
Effective Address - use of the different effective address
modes.
Implicit Reference - the definition of certain instructions
implies the use of specific registers.

When a data register is used as either a source or
destination operand, only the appropriate low-order portion
is changed; the remaining high-order portion is neither
used nor changed.

INSTRUCTION FORMAT

ADDRESS REGISTERS. Each address register and the
stack pointer is 32 bits wide and holds a full 32 bit address.
Address registers do not support byte sized operands.
Therefore, when an address register is used as a source
operand, either the low order word or the entire long word
operand is used depending upon the operation size. When
an address register is used as the destination operand, the
entire register is affected regardless of the operation size. If
the operation size is word, any other operands are sign
extended to 32 bits before the operation is performed.

Instructions are from one to five words in length, as shown
in Figure 3. The length of the instruction and the operation
to be performed is specified by the first word of the
instruction which is called the operation word. The
remaining words further specify the operands. These words
are either immediate operands or extensions to the effective
address mode specified in the operation word.
PROGRAM/DATA REFERENCES
The MK68000 separates memory references into two
classes: program references, and data references. Program
references, as the name implies, are references to that
section of memory that contains the program being

DATA ORGANIZATION IN MEMORY
Bytes are individually addressable with the high order byte
WORD ORGANIZATION IN MEMORY
Figure 1
15

14

13

12

11

10

9

7

8

6

5

4

3

2

o

WORD 100000
BYTE 000000

BYTE 000001
WORD 100002

BYTE 000002

~

···

BYTE 000003

~

WORDtFFFFE
BYTE FFFFFE

BYTE FFFFFF

VI-4

DATA ORGANIZATION IN MEMORY
Figure 2
BIT DATA
1 BYTE = 8 BITS
7

6

5

o

2

3

4

INTEGER DATA
8 BITS

1 BYTE
15

14

13

12

10

11

9

7

BYTE 2

1 WORD
14

15

12

13

6

4

5

~BI

BYTE 0

IMSB

=

8

11

10

9

3

2

0

2

0

BYTE 1
BYTE 3

= 16 BITS

8

7

6

5

4

3

~BI

WORDO

IMSB

WORD 1
WORD2
1 LONG WORD

15

14

12

13

11

9

10

MSB
-

-LONGWORDO

=32 BITS

7

6

5

4

3

2

0

HIGH ORDER

- --

-

8

- -

-- - - - - - - - - -

LOWORDER

LSB

-

-LONG WORD 1 -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-LONG WORD 2 -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

ADDRESSES
1 ADDRESS = 32 BITS
15

14

13

12

11

10

9

MSB
-

6

7

8

o

2

3

4

5

HIGH ORDER

-ADDRESS 0 -

-

LOWORDER

LSB

-

-ADDRESS 1 -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-ADDRESS2- -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

MSB = Most Significant Bit
LSB = Least Significant Bit
15
MSD

14

13

12

DECIMAL DATA
2 BINARY CODED DECIMAL DIGITS = 1 BYTE
11

10

9

BCD1

BCDO
BCD4

8
LSD

BCD5

..

..

MSD = Most Slgnrflcant Digit
LSD = Least Significant Digit

VI-5

7

6

5

4

3

o

2

BCD2

BCD3

BCD6

BCD7·

II

executed. Data references refer to that section of memory
that contains data. Generally, operand reads are from the
data space. All operand writes are to the data space.

specified by the effective address register field.
Address Register Direct. The operand is in the address
register specified by the effective address register field.

REGISTER SPECIFICATION
MEMORY ADDRESS MODES
The register field within an instruction specifies the register
to be used. Other fields within the instruction specify
whether the register selected is an address or data register
and how the register is to be used.
EFFECTIVE ADDRESS
Most instructions specify the location of an operand by
using the effective address field in the operation word. For
example, Figure 4 shows the general format of the single
effective address instruction operation word. The effective
address is composed of two 3-bit fields: the mode field, and
the register field. The value in the mode field selects the
different address modes. The register field contains the
number of a register.
The effective address field may require additional
information to fully specify the operand. This additional
information, called the effective address extension, is
contained in the following word or words and is considered
part of the instruction, as shown in Figure 3. The effective
address modes are grouped into three categories: register
direct, memory addressing, and special.
REGISTER DIRECT MODES
These effective addressing modes specify that the operand
is in one of the 16 multifunction registers.

These effective addressing modes specify that the operand
is in memory and provide the specific address of the
operand.
Address Register Indirect. The address ofthe operand is in
the address register specified by the register field. The
reference is classified as a data reference with the
exception of the jump and jump to subroutine instructions.
Address Register Indirect With Postincrement. The
address of the operand is in the address register specified by
the register field. After the operand address is used, it is
incremented by one, two, or four depending upon whether
the size of the operand is byte, word, or long word. If the
address register is the stack pointer and the operand size is
byte, the address is incremented by two rather than one to
keep the stack pointer on a word boundary. The reference is
classified as a data reference.
Address Register Indirect With Predecrement. The
address of the operand is in the address register specified by
the register field. Before the operand address is used, it is
decremented by one, two, or four depending upon whether
the operand size is byte, word, or long word. If the address
register is the stack pointer and the operand size is byte, the
address is decremented by two rather than one to keep the
stack pointer on a word boundary. The reference is
classified as a data reference.

Data Register Direct. The operand is in the data register
INSTRUCTION OPERATION WORD
GENERAL FORMAT
Figure 3
15

14

13

12

11

10

9

8

7

6

5

4

3

2

o

3

2

o

OPERATION WORD
(FIRST WORD SPECIFIES OPERATION AND MODES)
IMMEDIATE OPERAND
(IF ANY, ONE OR TWO WORDS)
SOURCE EFFECTIVE ADDRESS EXTENSION
(IF ANY, ONE OR TWO WORDS)
DESTINATION EFFECTIVE ADDRESS EXTENSION
(IF ANY, ONE OR TWO WORDS)

SINGLE-EFFECTIVE-ADDRESS INSTRUCTION
OPERATION WORD
Figure 4

15

14

13

12

11

10

9

7

8

6

5

4

EFFECTIVE ADDRESS
REGISTER
MODE

VI-6

Address Register Indirect With Displacement. This
address mode requires one word of extension. The address
of the operand is the sum of the address in the address
register and the sign-extended 16-bit displacement integer
in the extension word. The reference is classified as a data
reference with the exception of the jump and jump to
subroutine instructions.

with the exception of the jump and jump to subroutine
instructions.
Absolute Long Address. This address mode requires two
words of extension. The address of the operand is developed
by the concatenation of the extension words. The highorder part of the address is the first extension word; the
low-order part of the address is the second extension word.
The reference is classified as a data reference with the
exception of the jump and jump to subroutine instructions.

Address Register Indirect With Index. This address mode
requires one word of extension. The address of the operand
is the sum of the address in the address register, the signextended displacement integer in the low order eight bits of
the extension word, and the contents of the index register.
The reference is classified as a data reference with the
exception of the jump and jump to subroutine instructions.

Program Counter With Displacement. This address mode
requires one word of extension. The address of the operand
is the sum of the address in the program counter and the
sign-extended 16-bit displacement integer in the extension
word. The value in the program counter is the address of the
extension word. The reference is classified as a program
reference.

SPECIAL ADDRESS MODES
The special address modes use the effective address
register field to specify the special addressing mode instead
of a register number.

IMPLICIT INSTRUCTION REFERENCE SUMMARY
Table 5

Absolute Short Address. This address mode requires one
word of extension. The address of the operand is the
extension word. The 16-bit address is sign extended before
it is used. The reference is classified as a data reference

Instruction
Branch Conditional (Bcd, Branch
Always (BRA)
Branch to Subroutine (BSR)

EFFECTIVE ADDRESS ENCODING SUMMARY
Table 4

Implied
Register(s)

PC
PC,SP

Check Register against Bounds (CHK)

SSP, SR

register number

Test Condition, Decrement and Branch
(DBed

PC

001

register number

Signed Divide (DIVS)

SSP, SR

Address Register Indirect

010

register number

Unsigned Divide (DIVU)

SSP, SR

Address Register Indirect
with Postincrement

011

register number

Addressing Mode

Mode

Register

Data Register Direct

000

Address Register Direct

Jump (JMP)
Jump to Subroutine (JSR)

Address Register Indirect
with Predecrement

100

register number

Address Register Indirect
with Displacement

101

register number

Address Register Indirect
with Index

110

register number

Absolute Short

111

000

Absolute Long

111

001

PC,SP

Link and Allocate (LINK)

SP

Move Condition Codes (MOVE CCR)

SR

Move Status Register (MOVE SR)

SR

Move User Stack Pointer (MOVE USP)

USP

Push Effective Address (PEA)

SP

Return from Exception (RTE)

PC,SP,SR

Return and Restore Condition Codes (RTR) PC, SP, SR

Program Counter with
Displacement

111

010

Program Counter with
Index

111

011

Immediate or Status
Register

PC

111

Return from Subroutine (RTS)
Trap (TRAP)

SSP, SR

Trap on Overflow (TRAPV)

SSP, SR

Unlink (UNLK)

100

VI·7

PC,SP

SP

II

instructions form a set of tools that include all the machine
functions to perform the following operations:

Program Counter With Index. This address mode requires
one word of extension. The address is the sum of the
address in the program counter, the sign-extended
displacement integer in the lower eight bits of the extension
word, and the contents of the index register. The value in
the program counter is the address of the extension word.
This reference is classified as a program reference.

Data Movement
Integer Arithmetic
Logical
Shift and Rotate
Bit Manipulation
Binary Coded Decimal
Program Control
System Control

Immediate Data. This address mode requires either one or
two words of extension depending on the size of the
operation.

The complete range of instruction capabilities combined
with the flexible addressing modes described· previously
provide a very flexible base for program development.

Byte operation - operand is low order byte of extension
word
Word operation - operand is extension word
Long word operation - operand is in the two extension
words, high-order 16 bits are in the first extension
word, low-order 16 bits are in the second extension
word.

DATA MOVEMENT OPERATIONS

Table 4 is a summary of the effective addressing modes
discussed in the previous paragraphs.

The basic method of data acquisition (transfer and storage)
is provided by the move (MOVE) instruction. The move
instruction and the effective addressing modes allow both
address and data manipulation. Data move instructions
allow byte, word, and long word operands to be transferred
from memory to memory, memory to register, register to
memory, and register to register. Address move instructions
allow word and long word operand transfers and ensure
that only legal address manipulations are executed. In
addition to the general move instruction there are several
special data movement instructions: move multiple
registers (MOVEM), move peripheral data (MOVEP),
exchange registers (EXG), load effective address (LEA),
push effective address (PEA), link stack (LINK), unlink stack
(UNLK), and move quick (MOVEO). Table 6 is a summary of
the data movement operations.

IMPLICIT REFERENCE

INTEGER ARITHMETIC OPERATIONS

Condition Codes or Status Register. A selected set of
instructions may reference the status register by means of
the effective address field. These are:
ANDI to CCR
ANDI to SR
EORI to CCR
EORI to SR
ORI to CCR
ORI to SR
EFFECTIVE ADDRESS ENCODING SUMMARY

Some instructions make implicit reference to the program
counter (PC), the system stack pointer (SP), the supervisor
stack pointer (SSP), the user stack pointer (USP), or the
status register (SR). Table 5 provides a list of these
instructions and the registers implied.
SYSTEM STACK
The system stack is used implicitly by many instructions;
user stacks and queues may be created and maintained
through the addressing modes. Address register seven (A7)
is the system stack pointer (SP). The system stack pointer is
either the supervisor stack pointer (SSP) or the user stack
pointer (USP), depending on the state of the S-bit in the
status register. If the S-bit indicates supervisor state, SSP is
the active system stack pointer, and the USP cannot be
referenced as an address register. If the S-bit indicates user
state, the USP is the active system stack pointer, and the
SSP cannot be referenced. Each system stack fills from high
memory to low memory.
INSTRUCTION SET SUMMARY
The following paragraphs contain an overview of the form
and structure of the MK68000 instruction set. The

The arithmetic operations include the four basic operations
of add (ADD), subtract (SUB), mUltiply (MUL), and divide
(DIV) as well as arithmetic compare (CMP), clear (CLR), and
negate (NEG). The add and subtract instructions are
available for both address and data operations, with data
operations accepting all operand sizes. Address operations
are limited to legal address size operands (16 or 32 bits).
Data, address, and memory compare operations are also
available. The clear and negate instructions may be used on
all sizes of data operands.
The multiply and divide operations are available for signed
and unsigned operands using word multiply to produce a
long word product, and a long word dividend with word
divisor to produce a word quotient with a word remainder.
Multiprecision and mixed size arithmetic can be accomplished using a set of extended instructions. These
instructions are: add extended (ADDX), subtract extended
(SUBX), sign extend (EXT), and negate binary with extend
(NEGX).
A test operand (TST) instruction that will set the condition
codes as a result of a compare of the operand with zero is
also available. Test and set (TAS) is a synchronization

VI-8

instruction useful in multiprocessor systems. Table 7 is a
summary of the integer arithmetic operations.

INTEGER ARITHMETIC OPERATIONS
Table 7

Instruction

DATA MOVEMENT OPERATIONS
Table 6

Operand Size

Operation

8,16,32

16,32

Dn + (EA) -- Dn
(EA) + Dn -- EA
(EA) + #xxx -- EA
An + (EA) -- An

Instruction

Size

Operation

EXG

32

Rx-Ry

LEA

32

EA-- An

ADDX

8,16,32
16,32

-(Ax) + -(Ay) + X -- (Ax)

-

8,16,32

0-- EA

8,16,32

8,16,32

An -- -(SP)
SP -- An
SP + displacement -- SP
(EA)s -- EAd

CLR

LINK

16,32

16,32

(EA) -- An, Dn
An, Dn -- EA

Dn -(EA)
(EA) - #xxx
-(Ax) - (Ay)+
An -(EA)

DIVS

32 -16

Dn/(EA) -- Dn

MOVEP

16,32

(EA)-- Dn
Dn -- EA

DIVU

32 -16

Dn/(EA) -- Dn

MOVEO

8

#xxx -- Dn
EXT

8 -- 16
16 -- 32

(Dn)8 -- Dn16
(Dn), 6 -- Dn32

MULS

16* 16 -- 32

Dn* (EA)- Dn

MULU

16* 16 -- 32

Dn* (EA) -- Dn

NEG

8,16,32

0- (EA) -- EA

NEGX

8,16,32

o - (EA) -

8,16,32

16,32

Dn - (EA) -- Dn
(EA) - Dn -- EA
(EA) - #xxx -- EA
An - (EA) -- An

SUBX

8,16,32

-(Ax) - - (Ay) - X - (Ax)

TAS

8

(EA) - 0,1 - EA[7]

TST

8,16,32

(EA)-O

MOVE

ADD

CMP
MOVEM

PEA

32

SWAP

32

UNLK

EA-- -(SP)
Dn[31 :16]

-

Dn[15:0]

An -- Sp
(SP)+ -- An

NOTES:
s = source
d = destination
[ ] = bit numbers
-( ) = indirect with predecrement
( )+ = indirect with postincrement
# = immediate data

SUB

X - EA

Dx - Dy - X -- Dx

LOGICAL OPERATIONS
Logical operation instructions AND, OR. EOR, and NOT are
available for all sizes of integer data operands. A similar set
of immediate instructions (ANDI, ORI, and EORI) provides
these logical operations with all sizes of immediate data.
Table 8 is a summary of the logical operations.

Dx + Dy + X -- Dx

NOTE: [ ] = bit number

x

= extend bit

Memory shifts and rotates are for word operands only and
allow only single-bit shifts or rotates.

SHIFT AND ROTATE OPERATIONS

Table 9 is a summary of the shift and rotate operations.

Shift operations in both directions are provided by the
arithmetic instructions ASR and ASL and logical shift
instructions LSR and LSL. The rotate instructions (with and
without extend) available are ROXA. ROXL, ROA. and ROL.
All shift and rotate operations can be performed in either
registers or memory. Register shifts and rotates support all
operand sizes and allow a shift count specified in the
instruction of one to eight bits, or 0 to 63 specified in a data
register.

BIT MANIPULATION OPERATIONS
Bit manipulation operations are accomplished using the
following instructions: bit test (BTST), bit test and set (BSET),
bit test and clear (BCLR), and bit test and change (BCHG).
Table 10 is a summary of the bit manipulation operations.
(Bit 2 of the status register is Z.)

VI-9

•

LOGICAL OPERATIONS
Table 8
Instruction

AND

BINARY CODED DECIMAL OPERATIONS
Table 11

Operand Size

Operation

8,16,32

DnA(EA) -- Dn
(EA)ADn -- EA
(EA)A#xxx - EA
Dn v (EA) -- Dn
(EA) v Dn -- EA
(EA) v #xxx - EA

8,16,32

OR

EOR

8, 16,32

(EA) a1 Dy - EA
(EA) a1 #xxx - EA

NOT

8,16,32

-(EA) -- EA

NOTE: -

BINARY CODED DECIMAL OPERATIONS
Multiprecision arithmetic operations on binary coded
decimal numbers are accompolished using the following
instructions: add decimal with extend (ABCD), subtract
decimal with extend (SBCD), and negate decimal with
extend (NBCD). Table 11 is a summary of the binary coded
decimal operations.

Operation

ASL

8,16,32

~O

ASR

8,16,32

LSL

8,16,32

LSR

8,16,32

O~

ROL

8,16,32

ROR

8,16,32

~
~

ROXL

8,16,32

ROXR

8,16,32

~

rl x H

Operation

BTST

8,32

- bit of (EA) - Z

BSET

8,32

- bit of (EA) -- Z
1 - bit of EA

BCLR

8,32

- bit of (EA) - Z
0- bit of EA

BCHG

8,32

- bit of (EA) - Z
- bit of (EA) - bit of EA

DXlO+DylO+X -- Dx
-(Ax), a + -(Ay), a + X - (Ax)

SBCD

8

DxlO - DylO - X -- Dx
-(Ax), a - - (Ay),o - X -- (Ax)

NBCD

8

O-(EA),o-X- EA

CC - carry clear
CS - carry set
EQ - equal
F - never true
GE - greater or equal
GT - greater than
HI - high
LE - less or equal

Instruction

LS - low or same
LT - less than
MI - minus
NE - not equal
PL - plus
T - always true
VC - no overflow
VS - overflow

Operation

Conditional
Bee
DBee
See

Branch conditionally (14 conditions)
8- and 16-bit displacement
Test condition, decrement, and branch
16-bit displacement
Set byte conditionally (16 conditions)

Unconditional
BRA
Branch always
8- and 16-bit displacement
BSR
Branch to subroutine
8- and 16-bit displacement
JMP
Jump
JSR
Jump to subroutine

BIT MANIPULATION OPERATIONS
Table 10
Operand Size

8

The conditional instructions provide setting and branching
for the following conditions:

HXh
- ',-' C I

Instruction

ABCD

PROGRAM CONTROL OPERATIONS
Table 12

~O

co .., I..

Operation

Program control operations are accomplished using a series
of conditional and unconditional branch instructions and
return instructions. These instructions are summarized in
Table 12.

SHIFT AND ROTATE OPERATIONS
Table 9
Operand
Size

Operand
Size

PROGRAM CONTROL OPERATIONS

= invert

Instruction

Instruction

'Returns
RTR
RTS

VI-10

Return and restore condition codes
Return from subroutine

SYSTEM CONTROL OPERATIONS
SYSTEM CONTROL OPERATIONS

System control operations are accomplished by using
privileged instructions, trap generating instructions, and
instructions that use or modify the status register. These
instructions are summarized in Table 13.

Table 13

Instruction
Privileged
RESET
RTE
STOP
ORI to SR
MOVE USP
ANDI to SR
EORI to SR
MOVE EA to SR

SIGNAL AND BUS OPERATION DESCRIPTION
The following paragraphs contain a brief description of the
input and output signals. A discussion of bus operation
during the various machine cycles and operations is also
given.
SIGNAL DESCRIPTION
The input and output signals can be functionally organized
into the groups shown in Figure 5. The following
paragraphs provide a brief description of the signals and
also a reference (if applicable) to other paragraphs that
contain more detail about the function being performed.

Trap Generating
TRAP
TRAPV
CHK

ADDRESS BUS (A1 THROUGH A23). This 23-bit,
unidirectional, three-state bus is capable of addressing 8
megawords of data. It provides the address for bus
operation during all cycles except interrupt cycles. During
interrupt cycles, address lines A 1, A2, and A3 provide
information about what level interrupt is being serviced
while address lines A4 through A23 are all set to a logic
high.

Status Register
ANDI to CCR
EORI to CCR
MOVE EA to CCR
ORI to CCR
MOVE SR to EA

DATA BUS (DOTHROUGH D15). This 16-bitbidirectional,
three-state bus is the general purpose data path. It can
transfer and accept data in either word or byte length.
During an interrupt acknowledge cycle, the external device
supplies the vector number on data lines DO-D7.

Reset external devices
Return from exception
Stop program execution
Logical OR to status register
Move user stack pointer
Logical AND to status register
Logical EOR to status register
Load new status register

Trap
Trap on overflow
Check data register against upper
bounds
Logical AND to condition codes
Logical EOR to condition codes
Load new condition codes
Logical OR to condition codes
Store status register

Address Strobe (AS). This signal indicates that there is a
valid address on the address bus.
Read/Write (R/W). This signal defines the data bus
transfer as a read or write cycle. The R/W signal also works
in conjunction with the upper and lower data strobes as
explained in the following paragraph.

ASYNCHRONOUS BUS CONTROL. Asynchronous data
transfers are handled using the following control signals:
address strobe, read/write, upper and lower data strobes,
and data transfer acknowledge. These signals are explained
in the following paragraphs.

Upper And Lower Data Strobes (UDS, LDS). These
signals control the data on the data bus, as shown in Table
14. When the R/W line is high, the processor will read from
the data bus as indicated. When the R/W line is low, the
processor will write to the data bus as shown.

INPUT AND OUTPUT SIGNALS
Figure 5

Operation

__~VczcI2~)_~-1------------~~_ _ _ _~~
GNDI2) .....

ADDRESS BUS) A1·A23

CLK

~

A
DATA BUS

MICROPROCESSOR

AS
RiW

--'f-

UEiS
LliS

Data Transfer Acknowledge (DTACK). This input
indicates that the data transfer is completed. When the
processor recognizes DT ACK during a read cycle, data is
latched and the bus cycle terminated. When DTACK is
recognized during a write cycle, the bus cycle is terminated.

00-015

}-~"~~.
BUS

CONTROL

STATUS

r

6Boo
PERIPHERAL
CONTROL

~m.{

CONTROL

-

_

FC2

DTACK

E

iiii

17m

iffi

iiI'A

BGACK

i!ERR

jji[Q

RESET

iPri

HALT

An active transition of data transfer acknowledge, DTACK,
indicates the termination of a data transfer on the bus.

....

}~ ~.CONTROL

--

l~'"""~
CONTROL

.. iiiL2

If the system must run at a maximum rate determined by
RAM access times, the relationship between the times at
which DTACK and DATA are sampled are important.
VI-11

•

All control and data lines are sampled during the
MK68000's clock high time. The clock is internally buffered,
which results in some slight differences in the sampling and
recognition of various signals. The DTACK signal, like other
OATA STROBE CONTROL OF OATA BUS
Table 14

UOS LOS

R/W

High

High

-

Low

Low

High

08-015

00-07

No valid data

No valid data

High

Valid data bits
8-15

Valid data bits
0-7

Low

High

No valid data

Valid data bits
0-7

Low

High

High

Valid data bits
8-15

No valid data

Low

Low

Low

Valid data bits
8-15

Valid data bits
0-7

High

Low

Low

Valid data bits
0-7*

Valid data bits
0-7

Low

High

Low

Valid data bits
8-15

Valid data bits
8-15*

control at the end of the current bus cycle.
Bus Grant Acknowledge (BGACK). This input indicates
that some other device has become the bus master. This
signal cannot be asserted until the following four conditions
are met:
1. a bus grant has been received
2. address strobe is inactive which indicates that the
microprocessor is not using the bus
3. data transfer acknowledge is inactive which indicates
that either memory or the peripherals are not using the
bus
4. bus grant acknowledge is inactive which indicates that
no other device is still claiming bus mastership
INTERRUPT CONTROL (lPLO, IPL1, IPL2). These input
pins indicate the encoded priority level of the device
requesting an interrupt. Level seven is the highest priority
while level zero indicates that no interrupts are requested.
The least significant bit is given in IPLO and the most
significant bit is contained in IPL2. These lines must remain
stable until the processor signals interrupt acknowledge
(FCO-FC2 are all high) to insure that the interrupt is
recognized.
SYSTEM CONTROL. The system control inputs are used
to either reset or halt the processor and to indicate to the
processor that bus errors have occurred. The three system
control inputs are explained in the following paragraphs.

*These conditions are a result of current implementation
and may not appear on future devices.
control signals, is internally synchronized to allow for valid
operation in an asynchronous system. If the required setup
time (#47) is met during 54, DTACK will be recognized
during 55 and 56, and data will be captured during 56. The
data must meet the required setup time (#27).

Bus Error (BERR). This input informs the processor that
there is a problem with the cycle currently being executed.
Problems may be a result of:

If an asynchronous control signal does not meet the
required setup time, it is possible that it may not be
recog n ized du ri ng that cycle. Beca use of th is, asynch ronous
systems must not allow DTACK to precede data by more
than parameter #31.
Asserting DTACK (or BERR) on the rising edge of a clock
(such as 54) after the assertion of address strobe will allow
an MK68000 system to run at its maximum bus rate. If
setup times #27 and #47 are guaranteed, #31 may be
ignored. If DTACK and BERR are asserted at the same time,
the MK68000 will recognize the BERR and abort the cycle.
BUS ARBITRATION CONTROL. These three signals
form a bus arbitration circuit to determine which device will
be the bus master device.
Bus Request (BR). This input is write ORed with all other
devices that could be bus masters. This input indicates to
the processor that some other device desires to become the
bus master.
Bus Grant (BG). This output indicates to all other potential
bus master devices that the processor will release bus
VI-12

1. nonresponding devices
2. interrupt vector number acquisition failure
3. illegal access request as determined by a memory
management unit
4. other application dependent errors.
The bus error signal interacts with the halt signal to
determine if exception processing should be performed or
the current bus cycle should be retried.
Referto BUS ERROR AND HALT OPERATION paragraph for
additiona I information about the interaction of the bus error
and halt signals.
Reset (RESET). This bidirectional signal line acts to reset
(initiate a system initialization sequence) the processor in
response to an external reset Signal. An internally
generated reset (result of RESET instruction) causes all
external devices to be reset and the internal state of the
processor is not affected. A total system reset (processor
and external devices) is the result of external halt and reset
signals applied at the same time. Refer to RESET
OPERATION paragraph for additional information about
reset operation.
Halt (HALT). When this bidirectional line is driven by an
external device, it will cause the processor to stop at the
completion of the current bus cycle. When the processor

has been halted using this input, all control signals are
inactive and all three-state lines are put in their highimpedance state. Refer to BUS ERROR AND HALT
OPERATION paragraph for additional information about the
interaction between the halt and bus error signals.

FUNCTION CODE OUTPUTS
Table 15

FC2

FC1

FCO

Cycle Type

Low
Low
Low
Low
High
High
High
High

Low
Low
High
High
Low
Low
High
High

Low
High
Low
High
Low
High
Low
High

(Undefined, Reserved)
User Data
User Program
(Undefined, Reserved)
(Undefined, Reserved)
Supervisor Data
Supervisor Program
Interrupt Acknowledge

When the processor has stopped executing instructions,
such as in a double bus fault condition, the halt line is driven
by the processor to indicate to external devices that the
processor has stopped.

6800 PERIPHERAL CONTROL. These control signals are
used to allow the interfacing of synchronous 6800
peripheral devices with the asynchronous MK68000.
These signals are explained in the following paragraphs.

SIGNAL SUMMARY
Table 16
r--"

Three State
On HALT On BGACKI

Signal Name

Mnemonic

Input/Output

Active State

Address Bus

A1-A23

output

high

yes

yes

Data Bus

DO-D15

input/output

high

yes

yes

AS

output

low

no

yes

R/W

output

read-high
write-low

no

yes

UDS, LDS

output

low

no

yes

DTACK

input

low

no

no

Bus Request

BR

input

low

no

no

Bus Grant

BG

output

low

no

no

BGACK

input

low

no

no

IPLO, IPL1, IPL2

input

low

no

no

Bus Error

BERR

input

low

no

no

Reset

RESET

input/output

low

no*

no*

HALT

input/ output

low

no*

no*

E

output

high

no

no

Valid Memory Address

VMA

output

low

no

yes

Valid Peripheral Address

VPA

input

low

no

no

FCO, FC1,FC2

output

high

no

yes

Clock

CLK

input

high

no

no

Power Input

Vee

input

-

-

-

Ground

GND

input

-

-

-

Address Strobe

Read/Write
Upper and Lower Data Strobes
Data Transfer Acknowledge

Bus Grant Acknowledge
Interrupt Priority Level

Halt
Enable

Function Code Output

* open drain
VI-13

II

WORD READ CYCLE FLOW CHART

BYTE READ CYCLE FLOW CHART

Figure 6

Figure 7
SLAVE

BUS MASTER

Address Device

Address Device
1)
2)
3)
4)
5)

SLAVE

BUS MASTER

1)
2)
3)
4)
5)

Set R/W to Read
Place Function Code on FCO-FC2
Place Address on A1-A23
Assert Address Strobe (AS)
Assert Upper Data Strobe (UDS) and Lower
Data Strobe (LDS)

Set R/Vii to Read
Place Function Code on FCO-FC2
Place Address on A1-A23
Assert Address Strobe (AS)
Assert Upper Data Strobe (UDS) or Lower
Data Strobe (LDS) (based on AO)

I

I
Input Data
1) Decode Address
2) Place Data on DO-D15
3) Assert Data Transfer
Acknowledge (DTACK)

1 ) Decode Address
2) Place Data on DO-D7 or D8-D15
(based on ODS or LDS)
3) Assert Data Transfer Acknowledge
(DTACK)

Acquire Data

Acquire Data

1) Latch Data
2) Negate UDS or LDS
3) Negate AS

1) latch Data
2) Negate UDS and LDS
3) Negate AS

Terminate Cycle

Terminate Cycle

1) Remove Data from DO-D7 or D8-D15
2) Negate DTACK

1) Remove Data from DO-D15
2) Negate DTACK

I
Start Next Cycle

Start Next Cycle

Enable (E). This signal is the standard enable signal
common to all 6800 type peripheral devices. The period for
this output is ten MK68000 clock periods (six clocks low;
four clocks high). Enable is generated by an internal ring
counter which maycome up in any state. (Le., at power on, it
is impossible to guarantee phase relationship of E to CLK). E
is a free-running clock and runs regardless of the state of
the bus on the MPU.

The information indicated by the function code outputs is
valid whenever address strobe (AS) is active.

Valid Peripheral Address (VPA). This input indicates that
the device or region addressed is a 6800 family device and
that data transfer should be synchronized with the enable
(E) signal. This input also indicates that the processor should
use automatic vectoring for an interrupt. Refer to
INTERFACE WITH 6800 PERIPHERALS.

SIGNAL SUMMARY. Table 16 is a summary of all the
signals discussed in the previous paragraphs.

Valid Memory Address (VMA). This output is used to
indicate to 6800 peripheral devices that there is a valid
address on the address bus and the processor is
synchronized to enable. This signal only responds to a valid
peripheral address (VPA) input which indicates that the
peripheral is a 6800 family device.
PROCESSOR STATUS (FCO, FC1, FC2). These function
code outputs indicate the state (user or supervisor) and the
cycle type currently being executed, as shown in Table 15.

CLOCK (ClK). The clock input is a TTL compatible signal
that is internally buffered for development of the internal
clocks needed by the processor. The clock input should not
be gated off at any time, and the clock signal must conform
to minimum and maximum pulse width times.

BUS OPERATION
The following paragraphs explain control signal and bus
operation during data transfer operations, bus arbitration,
bus error and halt conditions, and reset operation.
DATA TRANSFER OPERATIONS. Transfer of data
between devices involves the following leads:
• Address Bus A 1 through A23
• Data Bus DO through D15
• Control Signals
The address and data buses are separate parallel buses

VI-14

READ AND WRITE CYCLE TIMING DIAGRAM
Figure 8
50 51 5253545556 5750 515253 54 55 5657 50 515253 54 w
ClK
A1-A23
A5

~~~------~~~------~~~------------~~
~____________~r-\

\
\

U05
l05

\
\

\

\
\

/

\

R/W

/

/

I

OTACK

\

/

/

08-015

(

)

00-07

(

)
)

FCO-2

~

_____.-JI

,-

<==
(

r

-----=========:..~

X~--============~~
~--------------------~~
)

X

~-------REAO- -- - -- -~- - - - -WRITE' - -

-.rc- ---- - -5l0W READ - - - - -

----~

WORD AND BYTE READ CYCLE TIMING DIAGRAM
Figure 9
50 51 52 53545556 5750 515253 54 55 5657 50 515253 5455 56 57
ClK

H

H
I

A1-A23
AO*

I
I

\
\
\

A5
U05
l05

I

r-

\
\

r-

/

/

R/w

\

/

\

OTACK

\

/

08-015

(

)

00-07

(

)

)

X

X

FCO-2

=x

C

I

>-)-

*Internal 5ignal Only
~-- WORD READ ----~--OOO BYTE REAO---~ --EVEN BYTE READ--~

used to transfer data using an asynchronous bus structure.
In all cycles, the bus master assumes responsibility for
deskewing all signals it issues at both the start and end of a
cycle. In addition, the bus master is responsible for
deskewing the acknowledge and data signals from the slave
device.
The following paragraphs explain the read, write, and readmodify-write cycles. The indivisible read-modify-write cycle
is the method used by the MK68000 for interlocked
mUltiprocessor communications.

NOTE
The terms assertion and negation will be used extensively.
This is done to avoid confusion when dealing with a mixture
of "active-low" and "active-high" signals. The term assert

or assertion is used to indicate that a signal is active or true
independent of whether that voltage is low or high. The
term negate or negation is used to indicate that a signal is
inactive or false.
Read Cycle. During a read cycle, the processor receives
data from memory or a peripheral device. The processor
reads bytes of data in all cases. If the instruction specifies a
word (or double word) operation, the processor reads both
bytes. When the instruction specifies byte operation, the
processor uses an internal AO bit to determine which byte to
read and then issues the data strobe required for that byte.
For byte operations, when the AO bit equals zero, the upper
data strobe is issued. When the AO bit equals one, the lower
data strobe is issued. When the data is received, the
processor correctly positions it internally.

VI-15

II

WORD WRITE CYCLE FLOW CHART

BYTE WRITE CYCLE FLOW CHART

Figure 10

Figure 11

BUS MASTER

BUS MASTER

SLAVE

Address Device

Address Device
1)
2)
3)
4)
5)
6)

SLAVE

1) Place Function Code on FCO-FC2
2) Place Address on A 1-A23
3) Assert Address Strobe (AS)
4) Set R/W to Write
5) Place Data on 00-07 or 08-015 (according
toAO)
6) Assert Upper Data Strobe (UOS) or Lower
Data Strobe (LOS) (based on AO)

Place Function Code on FCO-FC2
Place Address on A 1-A23
Assert Address Strobe O~S)
Set R/W to Write
Place Data on 00-015
Assert Upper Data Strobe (UOS) and
Lower Data Strobe (LOS)

I

1 ) Decode Address
2) Store Data on 00-015
3) Assert Data Transfer Acknowledge
(OTACK)

1 ) Decode Address
2) Store Data on 00-07 if LOS is asserted
Store Data on 08-015 if UOS is asserted
3) Assert Data Transfer Acknowledge
(OTACK)

t

t

Terminate Output Transfer

Terminate Output Transfer
1)
2)
3)
4)

Negate UOS and LOS
Negate AS
Remove Data from 00-015
Set R/W to Read

1)
2)
3)
4)

Negate UOS and LOS
Negate AS
Remove Data from 00-07 or 08-015
Set R/Vii to Read

I

I
Terminate Cycle

Terminate Cycle

1) Negate OT ACK

1 ) Negate OTACK

I

I

Start Next Cycle

Start Next Cycle

WORD AND BYTE WRITE CYCLE TIMING DIAGRAM
Figure 12
50 51 5253545556 5750 515253 54 55 5657 50 515253 54S5 56 57
CLK

AO*

AS

~

U05

\

/
/

/

L05

1\
/
\
)
08-015 ~;::===========\__----<
00-07 ~===~--========~I

R/W

F\

OTACK

FCO-2

)(_ _ _ _ _ _ _~

X

I
'L---.!

{\

/
)

\

I

r
>

)

)

X

>

*Internal 5ignal Only

1'--- - - WORD WRITE

- -- --~- -ODD BYTE WRITE ----- +----EVEN BYTE WRITE - - --~

VI-16

READ-MODIFY-WRITE CYCLE FLOW CHART
Figure 13
SLAVE

BUS MASTER
Address Device
1) Set R/W to Read
2) Place Function Code on FCO-FC2
3) Place Address on A 1-A23
4) Assert Address Strobe (AS)
5) Assert Upper Data Strobe (UOS) or Lower
Data Strobe (LOS)

,.

L I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - - ,

Input Data
1) Decode Address
2) Place Data on 00-07 or 08-015
3) Assert Data Transfer Acknowledge

(DTACK)

1) Latch Data
2) Negate 015S or LOS
3) Start Data Modification

I

I

.

Terminate Cycle
1) Remove Data from 00-07 or 08-015
2) Negate oTACK

Start Output Transfer
1) Set R/W to Write
2) Place Data on 00-07 or 08-015
3) Assert Upper Data Strobe (UfiS) or Lower
Data Strobe ([[is)

L I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - . "

Input Data
1) Store Data on 00-07 or 08-015
2) Assert Data Transfer Acknowledge
(OTACK)

Terminate Output Transfer
1)
2)
3)
4)

Negate iJl5!: or [[is
Negate AS
Remove Data from 00-07 or 08-015
Set R/IN to Read

Terminate Cycle
1) Negate OTACK

I
Start Next Cycle

A word read cycle flowchart isgiven in Figure 6. A byte read
cycle flow chart is given in Figure 7. Read cycle timing is
given in Figure 8 and Figure 9 details word and byte read
cycle operation.

Write Cycle. During a write cycle, the processor sends data
to memory or a peripheral device. The processor writes
bytes of data in all cases. If the instruction specifies a word
operation, the processor writes both bytes. When the
instruction specifies a byte operation, the processor uses an
internal AO bit to determine which byte to write and then
issues the data strobe required for that byte. For byte
operations, when the AO bit equals zero, the upper data
strobe is issued. When the AO bit equals one, the lower data
strobe is issued. A word write cycle flow chart is given in
Figure 10. A byte write cycle flowchart is given in Figure 11.
Write cycle timing is given in Figure 8 and Figure 12 details
word and byte write cycle operation.

Read-Modify-Write Cycle. The read-modify-write cycle
performs a read, modifies the data in the arithmetic-logic
unit, and writes the data back to the same address. In the
MK68000 this cycle is indivisible in that the address strobe
is asserted throughout the entire cycle. The test and set
(TAS) instruction uses this cycle to provide meaningful
communication between processors in a mUltiple processor
environment. This instruction is the only instruction that
uses the read-modify-write cycles and since the test and set
instruction only operates on bytes, all read-modify-write
cycles are byte operations. A read-modify-write cycle flow
chart is given in Figure 13 and a timing diagram is given in
Figure 14.

BUS ARBITRATION. Bus arbitration is a technique used
by master-type devices to request, be granted, and
acknowledge bus mastership. In its simplest form, it
consists of:

VI-17

•

READ-MODIFY-WRITE CYCLE TIMING DIAGRAM
Figure 14
50 51 52 53 54 55 56

57 58 59510511512513514515516517518519

ClK

A1-A23
AS
UDS or lOS

R/W
DTACK

08-015
FCO-2

----~========~-~-_-_-_~-_-_~~-_~==~
\

(~~~~

____~r____

r_____

~~~~L

r---

J'--___________________>C
I-oc----- - - --- -- -- INDIVISIBLE CYCLE

1. Asserting a bus mastership request.
2. Receiving a grant that the bus is available at the end of
the current cycle.
3. Acknowledging that mastership has been assumed.

- - - -- - - - - - -

--.J

BUS ARBITRATION CYCLE FLOW-CHART
Figure 15
PROCESSOR

REQUESTING DEVICE
Request the Bus
1) Assert Bus Request (Bri)

Figure 15 is a flow chart showing the detail involved in a
request from a single device. Figure 16 is a timing diagram
for the same operations. This technique allows processing
of bus requests during data transfer cycles.

Grant Bus Arbitration
1) Assert Bus Grant (BG)
I

The timing diagram shows that the bus request is negated
at the time that an acknowledge is asserted. This type of
operation would be true for a system consisting of the
processor and one device capable of bus mastership. In
systems having a number of devices capable of bus
mastership, the bus request line from each device is wire
ORed to the processor. In this system, it is easy to see that
there could be more than one bus request being made. The
timing diagram shows that the bus grant signal is negated a
few clock cycles after the transition of the acknowledge
(BGACK) signal.

Acknowledge Bus Mastership
1 ) External arbitration determines next bus
master
2) Next bus master waits for current cycle to
complete
3) Next bus master asserts Bus Grant
Acknowledge (BGACK) to become new
master
4) Bus master negates SA
I

Terminate Arbitration
1) Negate 1m (and wait for BGACK to be
. negated)

However, if the bus requests are still pending, the processor
will assert another bus grantwithin a few clock cycles after
it was negated. This additional assertion of bus grant allows
external arbitration circuitry to select the next bus master
before the current bus master has completed its
requirements. The following paragraphs provide additional
information about the three steps in the arbitration process.
Requesting the Bus. External devices capable of becoming
bus masters request the bus by asserting the bus request
(BR) signal. This is a wire ORed signal (although it need not
be constructed from open collector devices) that indicates to
the processor that some external device requires control of
the external bus. The processor is effectively at a lower bus
priority level than the external device and will relinquish the
bus after it has completed the last bus cycle it has started.
When no acknowledge is received before the bus request
signal goes inactive, the processor will continue processing
when it detects that the bus request is inactive. This allows

Operate as Bus Master
1) Perform Data Transfers (Read and Write
cycles) according to the same rules the processor uses.

Release Bus Mastership
1) Negate BGACK

Re-Arbitrate or Resume Processor
Operation

ordinary processing to continue if the arbitration circuitry
responded to noise inadvertently.
Receiving the Bus Grant. The processor asserts bus grant
(BG) as soon as possible. Normally this is immediately after
internal synchronization. The only exception to this occurs
when the processor has made an internal decision to
execute the next bus cycle but has not progressed far
enough into the cycle to have asserted the address strobe

VI-18

BUS ARBITRATION CYCLE TIMING DIAGRAM
Figure 16
ClK
A1-A23
AS
lDS/UDS

R/iN
DTACK

00-015
FCO-2

BR
BG

\~----------------

BGACK

PROCESSOR --~ -- DMA DEVICE--~-- -- -PROCESSOR - -- -...j...f- - - DMA DEVICE - ---

(AS) signal. In this case, bus grant will not be asserted until
one clock after address strobe is asserted to indicate to
external devices that a bus cycle is being executed.
The bus grant signal may be routed through a daisy-chained
network or through a specific priority-encoded network. The
processor is not affected by the external method of
arbitratio'" as long as the protocol is obeyed.

STATE DIAGRAM OF MK68000 BUS
ARBITRATION UNIT

Acknowledgement of Mastership. Upon receiving a bus
grant, the requesting device waits until address strobe, data
transfer acknowledge, and bus grant acknowledge are
negated before issuing its own BGACK. The negation of the
address strobe indicates that the previous master has
completed its cycle, the negation of bus grant acknowledge
indicates that the previous master has released the bus.
(While address strobe is asserted no device is allowed to
"break into" a cycle.) The negation of data transfer
acknowledge indicates the previous slave has terminated
its connection to the previous master. Note that in some
applications data transfer acknowledge might not enter into
this function. General purpose devices would then be
connected such that they were only dependent on address
strobe. When bus grant acknowledge is issued the device is
bus master until it negates bus grant acknowledge. Bus
grant acknowledge should not be negated until after the bus
cycle(s) is (are) completed. Bus mastership is terminated at
the negation of bus grant acknowledge.
The bus request from the granted device should be dropped
when bus grant acknowledge is asserted. If bus request is
still asserted after bus grant acknowledge is negated, the
processor performs another arbitration sequence and
issues another bus grant. Note that the processor does not
perform any external bus cycles before it re-asserts bus
grant.
BUS ARBITRATION CONTROl. The bus arbitration
control unit in the MK68000 is implemented with a finite
state machine. A state diagram of this machine is shown in
Figure 17. All asynchronous signals to the MK68000 are

VI-19

Figure 17

RA

R = Bus Request Internal
A = Bus Grant Acknowledge Internal
G = Bus Grant
T = Three-state Control to Bus Control logic**
X = Don't Care
*State machine will not change state if bus is in SO. Refer to
BUS ARBITRATION CONTROL for additional information.
**The address bus will be placed in the high impedance state if T is
asserted and AS is negated.

synchronized before being used internally. This synchronization is accomplished in a maxim.um of one cycle of the
system clock, assuming that the asynchronous input setup
time (#47) has been met. The input signal issampled onthe
falling edge of the clock and is valid internally after the next
falling edge.
As shown in Figure 17, input signals labeled R and A are
internally synchronized on the bus request and bus grant
acknowledge pins respectively. The bus grant output is
labeled G and the internal three-state control signal T. 1ft is
true, the address, data, and control buses are placed in a

II

BUS ARBITRATION DURING PROCESSOR BUS CYCLE
Figure 18

BUS THREE STATED--------i' BUS RELEASED FROM THREE STATE AND
BG ASSERTED
PROCESSOR STARTS NEXT BUS CYCLE
BR VALID INTERNAL
irnACR NEGATED INTERNAL
BR SAMPLED
BGACK SAMPLED
BR ASSERTED
BGACK NEGATED

CLK
SO S1 S2 S3 S4 S5 S6 S7
BR --------~\

SO S1 S2 S3 S4 S5 S6 S7 SO S1

J

BG==========~~~~~~~':::~=~__~/~----------------------------BGACK

==~~~~-=~

A 1-A23
AS

_____-JI'

1

\'-. _ _ _ _ _-1

-;;:.)~------------~~(==::;:--______-;::!----C

,\-___-Jr__

\\-_ _ _

___~r__
'~ _ _ _ _ _ _r-'~----------------~~~______~I

------~,'- _ _ _ _ _ _f'------------------~~~

UOS
lOS

==:x

FCO-FC2

)

(

R/VV

'----1

DTACK
00-015

,'---;::::=.r__
__

- - - - - - - - - « ' -___---'
PROCESSOR

•

ALTERNATE BUS MASTER

PROCESSOR

BUS ARBITRATION WITH BUS INACTIVE
Figure 19

BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE ----~
BGACKNEGATED------------------_ _ _ _ _ _~
BG ASSERTED AND BUS THREE STATED - - - - .
BR VALID I N T E R N A L - - - - - - -.....
BR SAMPLED - - - - - - - -......
BR ASSERTED

--------:1..

ClK
SO S 1 S2 S3 S4 S5 S6 S7

SA

SO S1 S2 S3 S4

1

\

BGACK

I~---------------\'-_____~J

A1-A23

_--{~==~____--;:-?'--_-_-_-_-_-_-_-_-_-_-~-----------------I(L_-.--_

BG

-------------~======~\-~

AS
\~______~I
'----------------~
UOS - - - - . . \
I~---------"
~
LOS
FCO-FC2

,

~

(

J>---___________),-------------\,.(____

R/VV--------------------~

' - - _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J

~ --------~'----I

00-015

------.[(~---------~-]_!)~==:_::_---===~~==----===::_

•

PROCESSOR

..

I.

BUS INACTIVE

..

I..

VI·20

ALTERNATE BUS MASTER

1

... :ROCESSOR..

BUS ERROR AND HALT OPERATION. In a bus
architecture that requires a handshake from an external
device, the possibility exists that the handshake might not
occur. Since different systems will require a different
maximum response time, a bus error input is provided.
External circuitry must be used to determine the duration
between address strobe and data transfer acknowledge
before issuing abus error signal. When a bus error signal is
received, the processor has two options: initiate a bus error
exception sequence or try running the bus cycle again.

high-impedance state when AS is negated. All signals are
shown in positive logic (active high) regardless of their true
active voltage level.
State changes (valid outputs) occur on the next rising edge
after the internal signal is valid.
A timing diagram of the bus arbitration sequence during a
processor bus cycle is shown in Figure 18. The bus
arbitration sequence while the bus is inactive (i.e.,
executing internal operations such as a multiply instruction)
is shown in Figure 19.

Exception Sequence. When the bus error signal is
asserted, the current bus cycle is terminated. If BEAR is
asserted before the falling edge of 52, AS will be negated in
57 in either a read or write cycle. As long as BERR remains
asserted, the data and address buses will be in the highimpedance state. When the BERR is negated, the processor
will begin stacking for exception processing. The bus error
exception sequence is entered when the processor receives

If a bus request is made at a time when the MPU has already
begun a bus cycle but AS has not been asserted (bus state
SO), BG will not be asserted on the next rising edge. Instead,
BG will be delayed until the second rising edge following its
internal assertion. This sequence is shown in Figure 20.
BUS ARBITRATION SPECIAL CASE
Figure 20

BUSTHREESTATED--------~

BG ASSERTED-----,
BR VALID INTERNAL
BR SAMPLED
SA ASSERTED

II

BUS RElEASED FROM THREE STATE AND
PROCESSOR STARTS NEXT BUS CYCLE
BGACK NEGATED INTERNAL
BGACK SAMPLED ~
BGACK NEGATED

++

l

CLK
BR \~ _ _ _ _ _ _ _ _ _ _ _....JI

BGACK

----------~\~==~----~I
\

A1.A23~
AS

-1

UDS

-.!

LOS

-1

)

I

(

\

\

>-C

rr-

~

I'
I'
I'

\

~

~

FCO-FC2
R/W

---1

DTACK

-1

00-015

..

~

'----l
PROCESSOR

r-

\

-I"

ALTERNATE BUS MASTER

-I"

~ROCESSOR

----+-

BUS ERROR TIMING DIAGRAM
Figure 21
CLK
A1-A23
~

UDS
~

R/VV

OTACK

(~====================~~~======
~~~~~~

08-015
00-07

<

FCO-2

HALT

~

\

BlAR
INITIATE

RESPONSE

!-CREAD ...... - - --FAiiuR-E--- -

BUS ERROR:

~J-~
------IN-IT-I-A-TE--B-US---

- ..... - - --,... -OETECTION---- - -

VI·21

-~RRORSTACi 100
MilLISECONDS -+1,--_ _ _ _ _ _ _ _ _ __

__________________~1

HALT
~

t<4ClOCKS

BUS CYCLES

2

3

4

5

6

NOTES:
1 ) Internal start-up time
2) SSP High read in here
3) SSP low read in here
4) PC High read in here
5) PC low read in here
6) First instruction fetched here.

Bus State Unknown:

~

All Control Signals Inactive
Data Bus In Read Mode:

"----I
~

"halts" (does nothing) and when the halt Signal is
constantly inactive the processor "runs" (does something).
The single-step mode is derived from correctly timed
transitions on the halt Signal input. It forces the processor to
execute a single bus cycle by entering the "run" mode until
the processor starts a bus cycle then changing to the "halt"
mode. Thus, the single-step mode allows the user to
proceed through (and therefore debug) processor operations one bus cycle at a time.
Figure 23 details the timing required for correct single-step
operations. Some care must be exercised to avoid harmful
interactions between the bus error signal and the halt pin
when using the single cycle mode as a debugging tool. This
is also true of interactions between the halt and reset lines,
since these can reset the machine.
When the processor completes a bus cycle after recognizing
that the halt signal is active, most three-state signals are put
in the high-impedance state. These include:
1. address lines
2. data lines
This is required for correct performance of the re-run bus
cycle operation.
While the processor is honoring the halt request, bus
arbitration performs as usual. That is, halting has no effect
on bus arbitration. It is the bus arbitration function that
removes the control signals from the bus.
The halt function and the hardware trace capability allow
the hardware debugger to trace single bus cycles or single
instructions at a time. These processor capabilities, along
with a software debugging package, give total debugging
flexibility.
Double Bus Faults. When a bus error exception occurs, the
processor will attempt to stack several words containing
information about the state of the machine. If a bus error
exception occurs during the stacking operation, there have
been two bus errors in a row. This is commonly referred to

VI-23

as a double bus fault. When a double bus fault occurs, the
processor will halt. Once a bus error exception has
occurred, any bus error exception occurring before the
execution of the next instruction constitutes a double bus
fault.
Note that a bus cycle which is re-run does not constitute a
bus error exception, and does not contribute to a double bus
fault. Note also that this means that as long as the external
hardware requests it, the processor will continue to re-run
the same bus cycle.
The bus error pin also has an effect on processor operation
after the processor receives an external reset input. The
processor reads the vector table after a reset to determine
the address to start program execution. If a bus error occurs
while reading the vector table (or at any time before the first
instruction is executed), the processor reacts as'if a double
bus fault has occurred and it halts. Only an external reset
will start a halted processor.
RESET OPERATION, The reset signal is a bidirectional
signal that allows either the processor or an external signal
to reset the system. Figure 24 is a timing diagram for reset
operations. Both the halt and the reset lines must be applied
to ensure total reset of the processor.
When the reset and halt lines are driven by an external
device, it is recognized as an entire system reset, including
the processor. The processor responds by reading the reset
vector table entry (vector number zero, address $()()()(X)())
and loads it into the supervisor stack pointer (SSP). Vector
table entry number one at address $000004 is read next
and loaded into the program counter. The processor
initializes the status register to an interrupt level of seven.
No other registers are affected by the reset sequence.
When a RESET sequence is executed, the processor drives
the reset pin for 124 clock periods. In this case, the
processor is trying to reset the rest of the system. Therefore,
there is no effect on the i nterna I state of the processor. All of
the processor's internal registers and the status register are
unaffected by the execution of a RESET instruction. All
external devices connected to the reset line will be reset at

•

DTACK, BERR, HALT ASSERTION RESULTS
Table 17

Asserted on Rising
Edge of State
N
N+2

Case
No.

Control
Signal
DTACK
BERR
HALT

A
NA
NA

5
X
X

Normal cycle terminate and continue.

1

2

DTACK
BERR
HALT

A
NA
A

5
X
5

Normal cycle terminate and halt. Continue when HALT
removed.

3

DTACK
BERR
HALT

NA
NA
A

A
NA

Normal cycle terminate and halt. Continue when HALT
removed.

DTACK
BERR
HALT

X
A
NA

X
5

5

DTACK
BERR
HALT

A
A

6

DTACK
BERR
HALT

NA
NA
A

4

Result

5
Terminate and take bus error trap.

NA

X

X
5
5

Terminate and re-run.

X

Terminate and re-run when HALT removed.

A

5

Legend:
N - the number of the current even bus state (e.g., 54, 56, etc.)
A - signal is asserted in this bus state
NA - signal is not asserted in this state
X -don't care
5 - signal was asserted in previous state and remains asserted in this state
BERR AND HALT NEGATION RESULTS
Table 18

Conditions of
Termination in
Table 17

Control
Signal

Bus Error

BERR
HALT

Re-run

BERR
HALT

Re-run

BERR
HALT

Normal

Normal

Negated on Rising
Edge of State
N+2
N

•
•
•
•
•

or
or
or

•
•
•

Results -

Next Cycle

Takes bus error trap.

Illegal sequence, usually traps to vector
number O.
Re-runs the bus cycle.

•

BERR
HALT

•
•

or

BERR
HALT

•

or

May lengthen next cycle.

•
•

If next cycle is started it will be terminated
none as a bus error.

Legend:
• =signal is negated in this bus state

VI-24

the completion of the RESET instruction.
Asserting the reset and halt pins for 10 clock cycles will
cause a processor reset, except when Vee is initially applied
to the processor. In this case, an external reset must be
applied to the reset pin for at least 100 milliseconds.
THE RELATIONSHIP OF DTACK, BERR, AND HALT
In order to control termination of a bus cycle for a re-run or a
bus error condition properly, DTACK, BERR, and HALT
should be asserted and negated on the rising edge of the
MK68000 clock. This will assure that when two signals are
asserted simultaneously, the required setup time (#47) for
both of them will be met during the same bus state.
This, or some equivalent precaution, should be designed
external to the MK68000. Parameter #48 is intended to
ensure this operation in a totally asynchronous system, and
may be ignored if the above conditions are met.
The preferred bus cycle terminations may be summarized
as follows (case numbers refer to Table 17):

store results. A special case of the normal state is the
stopped state which the processor enters when a STOP
instruction is executed. In this state, no further memory
references are made.
The exception processing state is associated with
interrupts, trap instructions, tracing and other exceptional
conditions. The exception may be internally generated by an
instruction or by an unusual condition arising during the
execution of an instruction. Externally, exception processing can be forced by an interrupt, by a bus error, or by a
reset. Exception processing is designed to provide an
efficient context switch so that the processor may handle
unusual conditions.
The halted processing state is an indication of catastrophic
hardware failure. For example, if during the exception
processing of a bus error another bus error occurs, the
processor assumes that the system is unusable and halts.
Only an external reset can restart a halted processor. Note
that a processor in the stopped state is not in the halted
state, nor vice versa.
PRIVILEGE STATES

Normal Termination: DTACK occurs first (case 1).
Halt Termination: HALT is asserted at same time, or
precedes DTACK (no BERR) cases 2 and 3.
Bus Error Termination: BERR is asserted in lieu of, at
same time, or preceding DTACK (case 4); BERR negated
at same time, or after DTACK.
Re-Run Termination: HALT and BERR asserted at the
same time, or before DTACK(cases 5 and 6); HALT must
be negated at least 1 cycle after BERR.
Table 17 details the resulting bus cycle termination under
various combinations of control signal sequences. The
negation of these same control signals under several
conditions is shown in Table 18 (DTACK is assumed to be
negated normally in all cases; for best results, both DTACK
and BERR should be negated when address strobe is
negated.)
Example A: A system uses a watch-dog timer to terminate
accesses to un-populated address space. The timer asserts
DTACK and BERR simultaneously after time-out. (case 4)

The processor operates in one of two states of privi lege: the
"user" state or the "supervisor" state. The privilege state
determines which operations are legal, is used by the
external memory management device to control and
translate accesses, and is used to choose between the
supervisor stack pointer and the user stack pointer in
instruction references.
The privilege state is a mechanism for providing security in a
computer system. Programs should access only their own
code and data areas, and ought to be restricted from
accessing information which theydo not need and must not
modify.
The privilege mechanism provides security by allowing
most programs to execute in user state. In this state, the
accesses are controlled, and the effects on other parts of the
system are limited. The operating system executes in the
supervisor state, has access to all resources, and performs
the overhead tasks for the user state programs.

PROCESSING STATES

SUPERVISOR STATE. The supervisor state is the higher
state of privilege. For instruction execution, the supervisor
state is determined by the S-bit of the status register; if the
S-bit is asserted (high), the processor is in the supervisor
state. All instructions can be executed in the supervisor
state. The bus cycles generated by instructions executed in
the supervisor state are classified as supervisor references.
While the processor is in the supervisor privilege state,
those instructions which use either the system stack
pointer implicity or address register seven explicitly access
the supervisor stack ~.ointer.

The MK68000 is always in one of three processing states:
normal, exception, or halted. The normal processing state is
that associated with instruction execution; the memory
references are to fetch instructions and operands, and to

All exception proceSSing is done in the supervisor state,
regardless of the setting of the S-bit. The bus cycles
generated during exception processing are classified as
supervisor references. All stacking operations during
exception processing use the supervisor stack pointer.

Example B: A system uses error detection on RAM
contents. Designer may (a) delay DTACK until data verified,
and return BERR and HALT simultaneously to re-run error
cycle (case 5), or if valid, return DTACK; (b) delay i5fACK
until data verified, and return BERR at same time as DTACK
if data in error (case 4); (c) return DTACK prior to data
verification, as described in previous section. If data invalid,
BERR is asserted (case 1) in next cycle. Error-handling
software must know how to recover error cycle.

VI-25

II

USER STATE. The user state isthe lower state of privilege.
For instruction execution, the user state is determined by
the S-bit of the status register; if the S-bit is negated (low),
the processor is executing instructions in the user state.

REFERENCE CLASSIFICATION
Table 19

Function Code Output
FC1
FCO
FC2

Most instructions execute the same in user state as in the
supervisor state. However, some instructions which have
important system effects are made privileged. User
programs are not permitted to execute the STOP
instruction, or th'e RESET instruction. To ensure that a user
program cannot enter the supervisor state except in a
controlled manner, the instructions which modify the whole
status register are privileged. To aid in debugging programs
which are to be used as operating systems, the move to user
stack pointer (MOVE USP) and move from user stack pointer
(MOVE from USP) instructions are also privileged.
The bus cycles generated by an instruction executed in user
state are classified as user state references. This allows an
external memory management device to translate the
address and to control access to protected portions of the
address space. While the processor is in the user privilege
state, those instructions which use either the system stack
pointer implicity, or address register seven explicitly, access
the user stack pointer.
PRIVILEGE STATE CHANGES. Once the processor is in
the user state and executing instructions, only exception
processing can change the privilege state. During exception
processing, the current setting of the S-bit of the status
register is saved and the S-bit is asserted, putting the
processing in the supervisor state. Therefore, when
instruction execution resumes at the address specified to
process the exception, the processor is in the supervisor
privilege state.
REFERENCE CLASSIFICATION. When the processor
makes a reference, it classifies the kind of reference being
made, using the encoding on the three function code output
lines. This allows external translation of addresses, control
of access, and differentiation of special processor states,
such as interrupt acknowledge. Table 19 lists the
classification of references.
EXCEPTION PROCESSING
Before discussing the details of interrupts, traps, and
tracing, a general description of exception processing is in
order. The processing of an exception occurs in four steps,
with variations for different exception causes. During the
first step, a temporary copy of the status register is made,

Reference Class

0

0

0

(Unassigned)

0

0

1

User Data

0

1

0

User Program

0

1

1

(Unassigned)

1

0

0

(Unassigned)

1

0

1

Supervisor Data

1

1

0

Supervisor Program

1

1

1

Interrupt Acknowledge

and the status register is set for exception processing. In the
second step the exception vector is determined, and the
third step is the saving of the current processor context. In
the fourth step a new context is obtained, and the processor
switches to instruction processing.
EXCEPTION VECTORS. Exception vectors are memory
locations from wh ich the processor fetches the address of a
routine which will handle that exception. All exception
vectors are two words in length (Figure 25), except for the
reset vector, which is four words. All exception vectors lie in
the supervisor data space, except for the reset vector which
is in the supervisor program space. A vector number is an
eight-bit number which, when multiplied by four, gives the
address of an exception vector. Vector numbers are
generated internally or externally, depending on the cause
of the exception. In the case of interrupts, during the
interrupt acknowledge bus cycle, a peripheral provides an
a-bit vector number (Figure 26) to the processor on data bus
lines DO through 07. The processor translates the vector
number into a full 24-bit address, as shown in Figure 27.
The memory layout for exception vectors is given in Table
20.
As shown in Table 20, the memory layout is 512 words long
(1024 bytes). It starts at address 0 and proceeds through
address 1023. This provides 255 unique vectors; some of
these are reserved for TRAPS and other system functions.
Of the 255, these are 192 reserved for user interrupt
vectors. However, there is no protection on the first 64
entries, so user interrupt vectors may overlap at the
discretion of the systems designer.

EXCEPTION VECTOR FORMAT
Figure 25
WORDO

NEW PROGRAM COUNTER (HIGH)

AO

=0, A1 =0

WORD 1

NEW PROGRAM COUNTER (LOW)

AO

=0, A1 = 1

VI-26

EXCEPTION VECTOR ASSIGNMENT
Table 20

Vector
Number(s)

Dec

Address
Hex

Space

Assignment

SP

Reset Initial SSP

0

0

000

-

4

004

SP

Reset Initial PC

2

8

008

SO

Bus Error

3

12

OOC

SO

Address Error

4

16

010

SO

Illegal Instruction

5

20

014

SO

Zero Divide

6

24

018

SO

CHK Instruction

7

28

01C

SO

TRAPV Instruction

8

32

020

SO

Privilege Violation

9

36

024

SO

Trace

10

40

028

SO

Line 1010 Emulator

11

44

02C

SO

Line 1111 Emulator

12*

48

030

SO

(Unassigned, reserved)

13*

52

034

SO

(Unassigned, reserved)

14*

56

038

SO

(Unassigned, reserved)

15

60

03C

SO

Uninitialized Interrupt Vector

16-23*

64

040

SO

(Unassigned, reserved)

92

05C

96

060

SO

Spurious Interrupt

24

-

25

100

064

SO

Level 1 Interrupt Autovector

26

104

068

SO

Level 2 Interrupt Autovector

27

108

06C

SO

Level 3 Interrupt Autovector

28

112

070

SO

Level 4 Interrupt Autovector

29

116

074

SO

Level 5 Interrupt Autovector

30

120

078

SO

Level 6 Interrupt Autovector

31

124

07C

SO

Level 7 Interrupt Autovector

32-47

128

080

SO

TRAP Instruction Vectors

188

OBC
SO

(Unassigned, reserved)

48-63*

64-255

192

OCO

252

OFC

256

100

1020

3FC

-

User Interrupt Vectors

SO

-

*Vector numbers 12, 13, 14, 16 through 23 and 48 through 63 are reserved for future enhancements by Mostek. No user
peripheral devices should be assigned these numbers.

VI·27

II

PERIPHERAL VECTOR NUMBER FORMAT
Figure 26

08 07

015

DO

IGNORED
Where:
v7 is the Ms8 of the Vector Number
vO is the LsB of the Vector Number

ADDRESS TRANSLATED FROM 8-BIT VECTOR NUMBER
Figure 27
A10 A9 A8

A23

A7

A6 A5

A4 A3

A2

A1

AO

ALL ZEROES

KINDS OF EXCEPTIONS, Exceptions can be generated by
either internal or external causes. The externally generated
exceptions are the interrupts and the bus error and reset
requests. The interrupts are requests from peripheral
devices for processor action while the bus error and reset
inputs are used for access control and processor restart. The
internally generated exceptions come from instructions, or
from address errors or tracing. The trap (TRAP), trap on
overflow (TRAPV), check register against bounds (CHK) and
divide (DIV) instructions all can generate exceptions as part
of their instruction execution. In addition, illegal instructions, word fetches from odd addresses and privilege
violations cause exceptions. Tracing behaves like a very
high priority, internally generated interrupt after each
instruction execution.
EXCEPTION PROCESSING SEQUENCE. Exception
processing occurs in four identifiable steps. In the first step,
an internal copy is made of the status register. After the
copy is made, the S-bit is asserted, putting the processor
into the supervisor privilege state. Also, the T-bit is negated
which will allow the exception handler to execute
unhindered by tracing. For the reset and interrupt
exceptions, the interrupt priority mask is also updated.
In the second step, the vector number of the exception is
determined. For interrupts, the vector number is obtained by
a processor fetch, classified as an interrupt acknowledge.
For all other exceptions, internal logic provides the vector
number. This vector number is then used to generate the
address of the exception vector.
The third step is to save the current processor status, except
for the reset exception. The current program counter value
and the saved copy of the status register are stacked using
the supervisor stack pointer. The program counter value
stacked usually points to the next unexecuted instruction,
however for bus error and address error, the value stacked
for the program counter is unpredictable, and may be
incremented from the address of the instruction which
caused the error. Additional information defining the
current context is stacked for the bus error and address
error exceptions.

The last step is the same for all exceptions. The new
program counter value is fetched from the exception vector.
The processor then resumes instruction execution. The
instruction at the address given in the exception vector is
fetched, and normal instruction decoding and execution is
started.

MULTIPLE EXCEPTIONS, These paragraphs describe the
processing which occurs when multiple exceptions arise
simultaneously. Exceptions can be grouped according to
their occurrence and priority. The Group exceptions are
reset, bus error, and address error. These exceptions cause
the instruction currently being executed to be aborted, and
the exception processing to commence at the next minor
cycle of the processor. The Group 1 exceptions are trace and
interrupt, as well as the privilege violations and illegal
instructions. These exceptions a Ilow the current instruction
to execute to completion, but preempt the execution of the
next instruction by forcing exception processing to occur
(privilege violations and illegal instructions are detected
when they are the next instruction to be executed). The
Group 2 exceptions occur as part of the normal processing
of instructions. The TRAP, TRAPV, CHK, and zero divide
exceptions are in this group. For these exceptions, the
normal execution of an instruction may lead to exception
processing.

°

°

Group exceptions have highest priority, while Group 2
exceptions have lowest priority. Within Group 0, reset has
highest priority, followed by bus error and then address
error. Within Group 1, trace has priority over external
interrupts, which in turn takes priority over illegal
instruction and privilege violation. Since only one
instruction can be executed at a time, there is no priority
relation within Group 2.
The priority relation between two exceptions determines
which is taken, or taken first, if the conditions for both arise
simultaneously. Therefore, if a bus error occurs during a
TRAP instruction, the bus error takes precedence, and the
TRAP instruction processing is aborted. In another example,
if an interrupt request occurs during the execution of an
instruction while the T -bit is asserted, the trace exception
has priority, and is processed first. Before instruction

VI-28

priority levels are numbered from one to seven, level seven
being the highest priorty. The status register contains a
three-bit mask which indicates the current processor
priority, and interrupts are inhibited for all priority leVels less
than or equal to the current processor priority.

EXCEPTION GROUPING AND PRIORITY
Table 21

Group

0

1

Exception

Processing

Reset
Bus Error
Exception processing begins
Address Error within two clock cycles
Trace
Interrupt
Illegal
Privilege

An interrupt request is made to the processor by encoding
the interrupt request level on the interrupt request lines; a
zero indicates no interrupt request. Interrupt requests
arriving at the processor do not force immediate exception
processing, but are made pending. Pending interrupts are
detected between instruction executions. If the priority of
the pending interrupt is lower than or equal to the current
processor priority, execution continues with the next
instruction and the interrupt exception processing is
postponed. (The recognition of level seven is slightly
different, as explained in a following paragraph.)

Exception processing begins
before the next instruction

TRAP, TRAPV,
2

CHK,

Zero Divide

Exception processing is started
by normal instruction execution

processing resumes, however, the interrupt exception is
also processed, and instruction processing commences
finally in the interrupt handler routine. A summary of
exception grouping and priority is given in Table 21 .

If the priority of the pending interrupt is greater than the
current processor priority, the exception processing
sequence is started. First a copy of the status register is
saved, and the privilege state is set to supervisor, tracing is
suppressed, and the processor priority level is set to the
level of the interrupt being acknowledged. The processor
fetches the vector number from the interrupting device,
classifying the reference as an interrupt acknowledge and
displaying the level number of the interrupt being
acknowledged on the address bus. If external logic requests
an automatic vectoring, the processor internally generates
a vector number which is determined by the interrupt level
number. If external logic indicates a bus error, the interrupt
is taken to be spurious, and the generated vector number
references the spurious interrupt vector. The processor
then proceeds with the usual exception processing, saving
the program counter and status register on the supervisor
stack. The saved value ofthe program counter is the address
of the instruction which would have been executed had the
interrupt not been present. The content of the interrupt
vector whose vector number was previously obtained is
fetched and loaded into the program counter, and normal
instruction execution commences in the interrupt handling
routine. A flow chart for the interrupt acknowledge
sequence is given in Figure 28; a timing diagram is given in
Figure 29, and the interrupt processing sequence is shown
in Figure 30.

EXCEPTION PROCESSING DETAILED DISCUSSION
Exceptions have a number of sources, and each exception
has processing which is peculiar to it. The following
paragraphs detail the sources of exceptions, how each
arises, and how each is processed.
RESET. The reset input provides the highest exception
level. The processing of the reset signal is designed for
system initiation, and recovery from catastrophic failure.
Any processing in progress at the time of the reset is
aborted and cannot be recovered. The processor is forced
into the supervisor state, and the trace state is forced off.
The processor interrupt priority mask is set at level seven.
The vector number is internally generated to reference the
reset exception vector at location 0 in the supervisor
program space. Because no assumptions can be made
about the validity of register contents, in particular the
supervisor stack pointer, neither the program counter nor
the status register is saved. The address contained in the
fi rst two words of the reset exception vector is fetched as the
initial supervisor stack pointer, and the address in the last
two words of the reset exception vector is fetched as the
initial program counter. Finally, instruction execution is
started at the address in the program counter. The powerup/restart code should be pointed to by the initial program
counter.

Priority level seven is a special case. Level seven interrupts
cannot be inhibited by the interrupt priority mask, thus
providing a "non-maskable interrupt" capability. An
interrupt is generated each time the interrupt request level
changes from some lower level to level seven. Note that a
level seven interrupt may still be caused by the level
comparison if the request level is a seven and the processor
priority is set to a lower level by an instruction.

The RESET instruction does not cause loading of the reset
vector, but does assert the reset line to reset external
devices. This allows the software to reset the system to a
known state and then continue processing with the next
instruction.
INTERRUPTS. Seven levels of interrupt priorities are
provided. Devices may be chained externally within
interrupt priority levels, allowing an unlimited number of
peripheral devices to interrupt the processor. Interrupt

UNINITIALIZED INTERRUPT. An interrupting device
asserts VPA or provides an interrupt vector during an
interrupt acknowledge cycle to the MK68000. If the vector
register has not been initialized, the responding MK68000
Family peripheral will provide vector 15, the uninitialized

VI-29

II

interrupt vector. This provides a uniform way to recover
from a programming error.

INTERRUPT ACKNOWLEDGE SEQUENCE
FLOWCHART
Figure 28

SPURIOUS INTERRUPT. If during the interrupt acknowledge cycle no device responds by asserti ng DTACK or VPA,
the bus error line should be asserted to terminate the vector
acquisition. The processor separates.the processing of this
error from bus error by fetching the spurious interrupt
vector instead of the bus error vector. The processor then
proceeds with the usual exception processing.

INTERRUPTING DEVICE

PROCESSOR

Request Interrupt

I

Grant Interrupt
1 ) Compare interrupt level in status register
and wait for current instruction to complete
2) Assert address strobe (AS)
3) Place interrupt level on A1. A2. A3
4) Set function code to interrupt acknowledge
5) Assert address strobe (AS)
6) Assert data strobes (UDS' and IDS)

INSTRUCTION TRAPS. Traps are exceptions caused by
instructions. They arise eitherfrom processor recognition of
abnormal conditions during instruction execution, or from
use of instructions whose normal behavior is trapping.

I

Some instructions are used specifically to generate traps.
The TRAP instruction always forces an exception, and is
useful for implementing system calls for user programs.
The TRAPV and CHK instructions force an exception if the
user program detects a runtime error, which may be an
arithmetic overflow or a subscript out of bounds.

Provide Vector Number
1) Place vector number on DO-D7
2) Assert data transfer acknowledge (DTACK)

I

Acquire Vector Number
1) latch vector number
2) Negate UDS and lDS
3) Negate AS

The signed divide (DIVS) and unsigned divide (DIVU)
instructions will force an exception if a division operation is
attempted with a divisor of zero.

,

ILLEGAL AND UNIMPLEMENTED INSTRUCTIONS.
Illegal instruction is the term used to refer to any ofthe word
bit patterns which are not the bit pattern of the first word of a
legal instruction. During instruction execution, if such an
instruction is fetched, an illegal instruction exception
occurs.

Release
1) Negate DTACK
r -_ _ _ _ _ _I

•

Start Interrupt Processing
• Although a vector number is one byte. both data strobes are asserted
due to the microcode used for exception processing. The processor
does not recognize anything on data lines D8 through D15 atthis time.

Word patterns with bits 15 through 12 equaling 1010 or
1111 are distinguished as unimplemented instructions and

INTERRUPT ACKNOWLEDGE SEQUENCE TIMING DIAGRAM
Figure 29
ClK

A1-A3

==>-<

AS~

\

'---_-JI
'---_-J(
'---_-J(

UDS*~.

lDS~

\

DTACK
08-015
00-07
FCO-2
IPlO-2

\'------~

\

R/Vii

\

/

<

<
(

=x
\

LAST BUS CYCLE OF INSTRUCTION
(READ OR WRITE)
I

\

<

)

<

\
~----------------------J7

STACK
lACK CYCLE
STACK AND
PCl
1
(VECTOR NUMBER ACQUISITION)
1 VECTOR FETCH I
..
__ (SSP)~.~."~--------------••~....~----~
•.
I~·"----------~.~.

* Although a vector number is one byte, both data strobes are asserted due to the microcode used for exception processing. The processor
does not recognize anything on data lines 08 through 015 at this time.

VI-30

INTERRUPT PROCESSING SEQUENCE
Figure 30

LAST BUS CYCLE
OF INSTRUCTION
DURING WHICH
INTERRUPT WAS
RECOGNIZED

---.

STACK
PCL
(AT SSP- 2)

~

lACK
CYCLE
(VECTOR NUMBER
ACQUISITION)

---..

STACK
STATUS
(AT SSP- 6)

r---+-

STACK
PCH
(AT SSP-4)

-...

,
~

READ
VECTOR
HIGH
(A16-A31)

READ
VECTOR
LOW
(AO-A15)

FETCH FIRST TWO
INSTRUCTION WORDS
OF INTERRUPT
ROUTINE

NOTE:
SSP refers to the value of the supervisor stack pointer before the interrupt occurs.

separate exception vectors are given to these patterns to
permit efficient emulation. This facility allows the operating
system to detect program errors, or to emulate unimplemented instructions in software.

PRIVILEGE VIOLATIONS. In order to provide system
security, various instructions are privileged. An attempt to
execute one of the privileged instructions while in the user
state will cause an exception. The privileged instructions
are:
STOP
RESET
RTE
MOVE to SR

AND (word) Immediate to SR
EOR (word) Immediate to SR
OR (word) Immediate to SR
MOVE USP

TRACING. To aid in program development, the MK68000
incl udes a faci Iity to allow instruction by instruction traci ng.
In the trace state, after each instruction is executed an
exception is forced, allowing a debugging program to
monitor the execution of the program under test.
The trace facility uses the T -bit in the supervisor portion of
the status register. If the T-bit is negated (off), tracing is
disabled, and instruction execution proceeds from instruction to instruction as normal. If the T-bit is asserted (on) at
the beginning of the execution of an instruction, a trace
exception will be generated after the execution of that
instruction is completed. If the instruction is not executed,
either because an interrupt is taken, or the instruction is
illegal or privileged, the trace exception does not occur. The
trace exception also does not occur if the instruction is
aborted by a reset, bus error, or address error exception. If
the instruction is indeed executed and an interrupt is
pending on completion, the trace exception is processed
before the interrupt exception. If, during the execution of the
instruction, an exception is forced by that instruction, the
forced exception is processed before the trace exception.

As an extreme illustration of the above rules, consider the
arrival of an interrupt during the execution of a TRAP
instruction while tracing is enabled. First the trap exception
is processed, then the trace exception, and finally the
interrupt exception. Instruction execution resumes in the
interrupt handler routine.

BUS ERROR. Bus error exceptions occur when the
external logic requests that a bus error be processed by an
exception. The current bus cycle which the processor is
making is then aborted. Whether the processor was doing
instruction or exception processing, that processing is
terminated, and the processor immediately begins
exception processing.
Exception processing for bus error follows the usual
sequence of steps. The status register is copied, the
supervisor state is entered, and the trace state is turned off.
The vector number is generated to refer to the bus error
vector. Since the processor was not between instructions
when the bus error exception request was made, the
context of the processor is more detailed. To save more of
this context, additional information is saved on the
supervisor stack. The program counter and the copy of the
status register are of course saved. The value saved for the
program counter is advanced by some amount, two to ten
bytes beyond the address of the fi rst word of the instruction
which made the reference causing the bus error. If the bus
error occurred during the fetch of the next instruction, the
saved program counter has a value in the vicinity of the
current instruction, even if the current instruction isa
branch, a jump, or a return instruction. Besides the usual
information, the processor saves its internal copy of the first
word of the instruction being processed and the address
which was being accessed by the aborted bus cycle.
Specific information about the access is also saved whether
it was a read or a write, whether the processor was
processing an instruction or not, and the classification

VI-31

II

itself from the system rather than destroy all memory
contents. Only the RESET pin can restart a halted processor.

displayed on the function code outputs when the bus error
occurred. The processor is processing an instruction if it is in
the normal state or processing a Group 2 exception; the
processor is not processing an instruction if it is processing
a Group 0 or a Group 1 exception. Figure 31 illustrates how
this information is organized on the supervisor stack.
Although this information is not sufficient in general to
effect full recovery from the bus error, it does allow software
diagnosis. Finally, the processor commences instruction
processing at the address contained in the vector. It is the
responsibility of the error handler routine to clean up the
stack and determine where to continue execution.

AD DR ESS ER ROR. Address error exceptions occur when
the processor attempts to access a word or a long word
operand or an instruction at an odd address. The effect is
much like an internally generated bus error, so that the bus
cycle is aborted, and the processor ceases whatever
processing it is currently doing and begins exception
processing. After exception processing commences, the
sequence is the same as that for bus error including the
information that is stacked, except that the vector number
refers to the address error vector instead. Likewise, if an
address error occurs during the exception processing for a
bus error, address error, or reset, the processor is halted. As
shown in Figure 32, an address error will execute a short
bus cycle followed by exception processing.

If a bus error occurs during the exception processing for a
bus error, address error, or reset, the processor is halted,
and all processing ceases. This simplifies the detection of
catastrophic system failure, since the processor removes
SUPERVISOR STACK ORDER
Figure 31
15

14

13

12

11

10

8

9

6

7

5

LOWER
ADDRESS

4

lR/wjl/N

I- ACCESS ADDRESS -

-

-

-

-

-

HIGH
- - -

-

-

-

-

o

2

3

I

FUNCTION
CODE

----------

LOW
INSTRUCTION REGISTER
STATUS REGISTER
HIGH

r-PROGRAM COUNTER-

--- - - - -

-------------

LOW
R/W (read/Write): write

=O. read =1. I/N (instruction/not): instruction =O. not =1

ADDRESS ERROR TIMING
Figure 32

50 S1 S2 53 S4 S5 S6 S7 SO 51 S2 S3 S4 S5 S6 S7

SO S1 S2 S3 S4 S5

\

L-

~----------~L-

\

\

DO-D15

r..

...

f--_ _ READ---....~I f--ADDRE55

ERROR~APPROX. 8~WRITE STACK----.I

WRITE

VI-32

----rcLOCKS IDLE.~

------J

INTERFACE WITH 6800 PERIPHERALS

6800 INTERFACING FLOW CHART

To interface the synchronous 6800 peripherals with the
asynchronous MK68000, the processor modifies its bus
cycle to meet the 6800 cycle requirements whenever a
6800 device address is detected. This is possible since both
processors use memory mapped I/O. Figure 33 is a flow
chart of the interface operation between the processor and
6800 devices.

Figure 33
PROCESSOR
Initiate Cycle

SLAVE

1 ) The processor starts a normal Read or
Write cycle

,

Define 6800 cycle
1) External hardware asserts Valid Peripheral
Address (VPA)

DATA TRANSFER OPERATION
Three signals on the processor provide the 6800 interface.
They are: enable (E), valid memory address (VMA), and valid
peripheral address (VPA). Enable corresponds to the E or 4>2
signal in existing 6800 systems. It is the bus clock used by
the frequency clock that is one tenth of the incoming
MK68000 clock frequency. The timing of E allows 1 MHz
peripherals to be used with an 8 MHz MK68000. Enable
has a 60/40 duty cycle; that is, it is low for six input clocks
and high for four input clocks. This duty cycle allows the
processor to do successive VPA accesses on successive E
pulses.

Synchronize With Enable
1) The processor monitors Enable (E) until it is
low (Phase 1 )
2) The processor asserts Valid Memory Address (VMA)

Transfer Data
1 ) The peripheral waits until E is active and
then transfers the data

6800 cycle timing is given in Figure 34. At state zero (SO) in
the cycle, the address bus and function codes are in the
high-impedance state. One half clock later, in state 1, the
address bus and function code outputs are released from
the high-impedance state.
During state 2, the address strobe (AS) is asserted to
indicate that there is a valid address on the address bus. If
the bus cycle is a read cycle, the upper and/or lower data
strobes a re aIso asserted instate 2. If the bus cycle is a write
cycle, the read/write (R/W) signal is switched to low (write)
during state 2. One half clock later, in state 3, the write data

I
Terminate Cycle
1) The processor waits until E goes low. (On a
Read cycle the data is latched as E goes
low internally)
2) The processor negates VMA
3) The processor negates AS. UOS. and lOS

•

Start Next Cycle

6800 CYCLE OPERATION
Figure 34

SO S2 S4 S6 SO S2 S4 Sw SwSwSw SwSw SwSw Sw Sw S6 SO S2 S4 SwSwSwSwSw Sw 56 SO
ClK
A1-A23

AS
UOS
lOS
R/Vii

OTACK

~

08-015

~>---------------<(

00-07

~......------------((

FCO-2

X

>----<
>----<
X

X

I
/\

E
VPA
VMA

>--

l>C
L

\

/

\
f--~.9!!~~l_~ ______ ~~Q~~.!..P!:!SR~~
CYCLE
READ CYCLE
(WORST CASE)

VI-33

_____

/
\

r

+ ___ ~~OE~~.!.!'!:!.~~l___ -1
WRITE CYCLE
(BEST CASE)

II

is placed on the data bus, and in state 4 the data strobes are
issued to indicate valid data on the data bus.

peripheral address decoding should prevent unintended
accesses.

The processor now inserts wait states until it recognizes the
assertion of VPA. The VPA input signals the processor that
the address on the bus is the address of a 6800 device (or an
area reserved for 6800 devices) and that the bus should
conform to the <1>2 transfer characteristics of the 6800 bus.
Valid peripheral address is derived by decoding the address
bus, conditioned by address strobe.

INSTRUCTION SET

After the recognition of VPA, the processor assures that the
Enable (E) is low, by waiting if necessary, and subsequently
asserts VMA. Valid memory address is then used as part of
the chip select equation ofthe peripheral. This ensures that
the 6800 peripherals are selected and deselected at the
correct time. The peripheral now runs its cycle during the
high portion of the E signal.
During a read cycle, the processor latches the peripheral
data in state 6. For all cycles, the processor negates the
address and data strobes one half clock cycle later in state 7
and the Enable signal goes low at this time. Another half
clock later, the address bus is put in the high-impedance
state. During a write cycle, the data bus is put in the highimpedance state and the read/write signal is switched high
at this time. The peripheral logic must remove VPA within
one clock after address strobe is negated. DTACK should
not be asserted while VPA is asserted.
Notice that the MK68000 VMA is active low, contrasted
with the active high 6800VMA. This allows the processor to
put its buses in the high-impedance state on DMA requests
without inadvertently selecting peripherals.

INTERRUPT INTERFACE OPERATION
During an interrupt acknowledge cycle while the processor
is fetching the vector, if VPA is asserted, the MK68000 will
assert VMA and complete a normal 6800 read cycle as
shown in Figure 35. The processor will then use an
internally generated vector that is a function of the interrupt
being serviced. This process is known as a utovectoring. The
seven autovectors are vector numbers 25 through 31
(decimal).
This operates in the same fashion (but is not restricted to)
the 6800 interrupt sequence. The basic difference is that
there are six normal interrupt vectors and one NMI type
vector. As with both the 6800 and the MK68000's normal
vectored interrupt, the interrupt service routine can be
located anywhere in the address space. This is due to the
fact that while the vector numbers are fixed, the contents of
the vector table entries are assigned by the user.

The following paragraphs provide information about the
addressing categories and instruction set of the MK68000.

ADDRESSING CATEGORIES
Effective address modes may be categorized by the ways in
which they may be used. The following classifications will
be used in the instruction definitions.
Data

Memory

Alterable

Control

If an effective address mode may be used to
refer to data operands, it is considered a data
addressing effective address mode.
If an effective address mode may be used to
refer to memory operands, it is considered a
memory addressing effective address mode.
If an effective address mode may be used to
refer to alterable (writeable) operands, it is
considered an alterable addressing effective
address mode.
If an effective address mode may be used to
refer to memory operands without an associated size, it is considered a control addressing
effective address mode.

Table 22 shows the various categories to which each of the
effective address modes belong. Table 23 is the instruction
set summary.
The status register addressing mode is not permitted unless
it is explicitly mentioned as a legal addressing mode.
These categories may be combined, so that additional, more
restrictive, classifications may be defined. For example, the
instruction descriptions use such classifications as
alterable memory or data alterable. The former refers to
those addressing modes which are both alterable and
memory addresses, and the latter refers to addressing
modes which are both data and alterable.

INSTRUCTION PRE-FETCH
The MK68000 uses a 2-word tightly-coupled instruction
prefetch mechanism to enhance performance. This
mechanism is described in terms of the microcode
operations involved. If the execution of an instruction is
defined to begin when the microroutine for that instruction
is entered, some features of the prefetch mechanism can be
described.

Since VMA is asserted during a utovectoring, the 6800

VI-34

1) When execution of an instruction begins, the operation
word and the word following have already been

AUTOVECTOR OPERATION TIMING DIAGRAM
Figure 35
50 52 54 56 50 52 54 5w 5w 5w 5w 5w 5w 5w 5w 5w 5w 56 50 52
ClK

~================~
~

A1-A3
A4-A23
A5

~

U05*

________.________~r-\

l05
R/VV
OTACK

~

08-015

--c=J~----------------------

00-07

~---------------

FCO-2

X

IPlO-2

~~-------------------------------------

E
VPA

c

7

L------_\=======~------~/~

II

\'--__________1

VMA

I--~~~~-+- - - - -- -

AUTOVECTOR OPERATION - - - -

--i

* Although a vector number is one byte, both data strobes are asserted due to the microcode used for exception processing. The processor does not
recognize anything on data lines 08 through 015 at this time.

EFFECTIVE ADDRESSING MODE CATEGORIES
Table 22

Effective
Address
Modes

Mode

Register

On
An
(An)

000
001
010

register number
register number
register number

X

(An)+
-(An)
d(An)

011
100
101

d(An,ix)

Data

Addressing Categories
Memory
Control
Alterable

X
X
X

-

-

-

X

X

X

register number
register number
register number

X
X
X

X
X
X

-

X

X
X
X

xxx.L

110
111
111

register number
000
001

X
X
X

X
X
X

X
X
X

X
X
X

d(PC)
d(PC,ix)
#xxx

111
111
111

010
011
100

X
X
X

X
X
X

X
X

-

-

-

xxx.w

-

-

INSTRUCTION SET
Table 23

Mnemonic

Description

Operation

Condition
Codes
XN ZVC

ABCD

Add Decimal with Extend

(Destination), o+(Source), 0 - Destination

* U * U *

ADD

Add Binary

(Destination)+(Source) - Destination

* affected

a cleared

U undefined

- unaffected
VI-3S

1 set

[ ] = bit number

* * * * *
d = displacement

INSTRUCTION SET (CONTINUED)
Table 23

Mnemonic

Description

Operation

Condition
Codes
XN Z VC

ADDA

Add Address

(Destination)+(Source) - Destination

- - - - -

ADDI

Add Immediate

(Destination)+lmmediate Data - Destination

* * * * *

ADDQ

Add Quick

(Destination)+lmmediate Data - Destination

* * * * *

ADDX

Add Extended

(Destination)+(Source)+ X - Destination

* * * * *

AND

AND Logical

(Destination) A (Source) - Destination

-

* * 0 0

ANDI

AND Immediate

(Destination) A Immediate Data - Destination

-

* * 0 0

ANDI to CCR

AND Immediate to Condition Codes

(Source) A CCR - CCR

* * * * *

ANDI to SR

AND Immediate to Status Register

(Source) A SR - SR

* * * * *

ASL,ASR

Arithmetic Shift

(Destination) Shifted by  - Destination

* * * * *

Bee

Branch Conditionally

If ee then PC+d - PC

- - - - -

BCHG

Test a Bit and Change

BCLR

~

«bit number» OF Destination - Z
«bit number» OF Destination  OF Destination
~

- - * - -

Test a Bit and Clear

~ «bit number» OF Destination - Z
0-  - OF Destination

-

-

* - -

BRA

Branch Always

PC + d - PC

-

-

-

BSET

Test a Bit and Set

1 -  OF Destination

- - * - -

BSR

Branch to Subroutine

PC - -(SP), PC+d - PC

-

BTST

Test a Bit

~

- - * - -

CHK

Check Register against Bounds

If Dn <0 or Dn> «ea» then TRAP

-

CLR

Clear an Operand

o-

- 0 1

CMP

Compare

(Destination) - (Source)

- * * * *

CMPA

Compare Address

(Destination) - (Source)

-

CMPI

Compare Immediate

(Destination) - Immediate Data

- * * * *

CMPM

Compare Memory

(Destination) - (Source)

- * * * *

DBee

Test Condition, Decrement and Branch If ~ ee then Dn - 1 - Dn; if Dn =I: - 1 then
PC + d - PC

DIVS

Signed Divide

(Destination)/(Source) - Destination

- * * * 0

DIVU

Unsigned Divide

(Destination)/(Source) - Destination

- * * * 0

EOR

Exclusive OR Logical

(Destination) $ (Source) - Destination

-

~

* affected

o cleared

U undefined

-

-

«bit number» OF Destination - Z

«bit number» OF Destination - Z

Destination

- unaffected

VI-36

1 set

[ ] = bit number

-

-

-

-

* U U U

o

0

* * * *

- - - - -

* * 0 0

d = displacement

INSTRUCTION SET (CONTINUED)
Table 23

Condition
Codes
XN ZVC

Mnemonic

Description

Operation

EORI

Exclusive OR Immediate

(Destination)

EORI to CCR

Exclusive OR Immediate to Condition
Codes

(Source)

e

CCR -- CCR

* * * * *

EORI to SR

Exclusive OR Immediate to Status
Register

(Source)

e

SR -- SR

* * * * *

EXG

Exchange Register

Rx-Ry

- - - - -

EXT

Sign Extend

(Destination) Sign-extended -- Destination

- * *

JMP

Jump

Destination -- PC

- - - - -

JSR

Jump to Subroutine

PC -- -(SP); Destination -- PC

- - - - -

LEA

Load Effective Address

Destination -- An

- -

LINK

Link and Allocate

An -- -(SP); SP -- An; SP + d -- SP

- - - - -

LSL, LSR

Logical Shift

(Destination) Shifted by  -- Destination

* * * 0 *

MOVE

Move Data from Source to Destination (Source) -- Destination

e

- * *

Immediate Data -- Destination

-

- * *

o0

o0

-

-

o0

MOVE to CCR Move to Condition Code

(Source) -- CCR

* * * * *

MOVE to SR

Move to the Status Register

(Source) -- SR

* * * * *

MOVE from
SR

Move from the Status Register

SR -- Destination

-

MOVE USP

Move User Stack Pointer

USP -- An, An -- USP

- - - - -

MOVEA

Move Address

(Source) -- Destination

-

-

-

- -

MOVEM

Move Multiple Registers

Registers -- Destination
(Source) -- Registers

-

-

-

-

-

MOVEP

Move Peripheral Data

(Source) -- Destination

-

-

-

-

-

MOVEQ

Move Quick

Immediate Data -- Destination

- * * 0 0

MULS

Signed Multiply

(Destination)* (Source) -- Destination

-

* *

MULU

Unsigned Multiply

(Destination)* (Source) -- Destination

-

* *

NBCD

Negate Decimal with Extend

0- (Destinationl,o - X -- Destination

* U * U *

NEG

Negate

0- (Destination) -- Destination

* * * * *

NEGX

Negate with Extend

0- (Destination) - X -- Destination

* * * * *

NOP

No Operation

-

-

-

NOT

Logical Complement

~

-

* *

OR

Inclusive OR Logical

(Destination) v (Source) -- Destination

-

* *

* affected

o cleared

U undefined

(Destination) -- Destination

- unaffected

VI-37

1 set

[ ] = bit number

d

- -

-

-

-

o0
o0

-

-

o0
o0

= displacement

II

INSTRUCTION SET (CONTINUED)
Table 23

Mnemonic

Description

Operation

Condition
Codes
XN ZVC

ORI

Inclusive OR Immediate

(Destination) v Immediate Data - Destination

- * * 0 0

ORI to CCR

Inclusive OR Immediate to Condition
Codes

(Source) V CCR - CCR

* * * * *

ORI to SR

Inclusive OR Immediate to Status
Register

(Source) V SR - SR

* * * * *

PEA

Push Effective Address

Destination - -(SP)

- - - - -

RESET

Reset External Devices

-

-

-

ROL, ROR

Rotate (Without Extend)

(Destination) Rotated by  - Destination

-

* * 0 *

ROXL, ROXR

Rotate with Extend

(Destination) Rotated by  - Destination

* * * 0 *

RTE

Return from Exception

(SP)+ - SR, (SP)+ - PC

* * * * *

RTR

Return and Restore Condition Codes

(SP)+ - CC; (SP)+ - PC

* * * * *

RTS

Return from Subroutine

(SP)+ - PC

-

SBCD

Subtract Decimal with Extend

(Destinationl,o - (Sourcel,o - X - Destination

* U * U *

Sec

Set According to Condition

If ee then 1 's- Destination else O's- Destination

-

STOP

Load Status Register and Stop

Immediate Data - SR; STOP

* * * * *

SUB

Subtract Binary

(Destination) - (Source) - Destination

* * * * *

SUBA

Subtract Address

(Destination) - (Source) - Destination

-

SUBI

Subtract Immediate

(Destination) - Immediate Data - Destination

* * * * *

SUBQ

Subtract Quick

(Destination) - Immediate Data - Destination

* * * * *

SUBX

Subtract with Extend

(Destination) - (Source) - X - Destination

* * * * *

SWAP

Swap Register Halves

Register [31 :16] - - Register [15:0]

-

* * 0 0

TAS

Test and Set an Operand

(Destination) Tested - CC; 1 - [7] OF Destination

-

* * 0 0

TRAP

Trap

PC - -(SSP); SR - -(SSP) -; (Vector) - PC

-

-

-

-

-

TRAPV

Trap on Overflow

If V then TRAP

-

-

-

-

-

TST

Test an Operand

(Destination) Tested - CC

-

* *

o

0

UNLK

Unlink

An - SP; (SP)+ - An

- - - - -

* affected

o cleared

U undefined

- unaffected

fetched. The operation word is in the instruction
decoder.
2) In the case of multi-word instructions, as each
additional word of the instruction is used internally, a
fetch is made to the instruction stream to replace it.
3) The last fetch from the instruction stream is made
VI-38

1 set

[

] = bit number

-

-

-

-

-

-

- - -

-

-

-

-

-

-

d = displacement

when the operation word is discarded and decoding is
started on the next instruction.
4) If the instruction is a single-word instruction causing a
branch, the second word is not used. But because this
word is fetched by the preceding instruction, it is
impossible to avoid this superfluous fetch. In the case of

an interrupt or trace exception, both words are not
used.
5) The program counter usually points to the last word
fetched from the instruction stream.

INSTRUCTION EXECUTION TIMES
The following paragraphs contain listings of the instruction
execution times in terms of external clock (ClK) periods. In
this timing data, it is assumed that the memory cycle time is
4 clock periods. Any wait states ca used by a longer memory

cycle must be added to the total instruction time. The
number of bus read and write cycles for each instruction is
also included with the timing data. This data is enclosed in
parenthesis following the execution periods and is shown
as: (r/w) where r is the number of read cycles and w is the
number of write cycles.

NOTE
The number of periods includes instruction fetch and all
applicable operand fetches and stores.

EFFECTIVE ADDRESS CALCULATION TIMING
Table 24

Addressing Mode

Byte, Word

Long

On
An

Register
Data Register Direct
Address Register Direct

0(0/0)
0(0/0)

0(0/0)
0(0/0)

(An)
(An)+

Memory
Address Register Indirect
Address Register Indirect with Postincrement

4(1/0)
4(1/0)

8(2/0)
8(2/0)

-(An)
dIAn)

Address Register Indirect with Predecrement
Address Register Indirect with Displacement

6(1/0)
8(2/0)

10(2/0)
12(3/0)

d(An,ix)*
xxx.w

Address Register Indirect with Index
Absolute Short

10(2/0)
8(2/0)

14(3/0)
12(3/0)

xxx.l
d(PC)

Absolute long
Program Counter with Displacement

12(3/0)
8(2/0)

16(4/0)
12(3/0)

d(PC,ix)*
#xxx

Program Counter with Index
Immediate

10(2/0)
4(1/0)

14(3/0)
8(2/0)

*The size of the index register (ix) does not affect execution time.

MOVE BYTE AND WORD INSTRUCTION CLOCK PERIODS
Table 25

Dn

An

(An)

(An)+

Destination
-(An)

dIAn)

d(An,ix)*

xxx.W

xxx.L

On
An
(An)

4(1/0)
4(1/0)
8(2/0)

4(1/0)
4(1/0)
8(2/0)

8(1/1 )
8(1/1 )
12(2/1 )

8(1/1)
8(1/1 )
12(2/1 )

8(1/1)
8(1/1 )
12(2/1 )

12(2/1 )
12(2/1 )
16(3/1 )

14(2/1 )
14(2/1 )
18(3/1 )

12(2/1 )
12(2/1 )
16(3/1 )

16(3/1 )
16(3/1 )
20(4/1 )

(An)+
-(An)
dIAn)

8(2/0)
10(2/0)
12(3/0)

8(2/0)
10(2/0)
12(3/0)

12(2/1 )
14(2/1 )
16(3/1 )

12(2/1 )
14(2/1 )
16(3/1 )

12(2/1 )
14(2/1 )
16(3/1 )

16(3/1 )
18(3/1 )
20(4/1 )

18(3/1 )
20(3/1 )
22(4/1 )

16(3/1 )
18(3/1 )
20(4/1 )

20(4/1 )
22(4/1 )
24(5/1 )

d(An,ix)*
xxx.w
xxx.l

14(3/0)
12(3/0)
16(4/0)

14(3/0)
12(3/0)
16(4/0)

18(3/1 )
16(3/1 )
20(4/1)

18(3/1 )
16(3/1 )
20(4/1)

18(3/1 )
16(3/1 )
20(4/1 )

22(4/1 )
20(4/1 )
24(5/1 )

24(4/1)
22(4/1 )
26i5/1 )

22(4/1 )
20(4/1 )
24(5/1 )

26(5/1 )
24(5/1 )
28(6/1 )

d(PC)
d(PC,ix)*
#xxx

12(3/0)
14(3/0)
8(2/0)

12(3/0)
14(3/0)
8(2/0)

16(3/1 )
18(3/1 )
12(2/1 )

16(3/1 )
18(3/1 )
12(2/1 )

16(3/1 )
18(3/1 )
12(2/1 )

20(4/1 )
22(4/1 )
16(3/1 )

22(4/1 )
24(4/1)
18(3/1 )

20(4/1 )
22(4/1 )
16(3/1 )

24(5/1 )
26(5/1 )
20(4/1 )

Source

*The size of the index register (ix) does not affect execution time.

VI·39

II

MOVE LONG INSTRUCTION CLOCK PERIODS
Table 26

On

An

(An)

(An)+

Destination
-(An)

d(An)

d(An,ix)*

xxx.W

xxx.L

Dn
An
(An)

4(110)
4(1/0)
12(3/0)

4(1/0)
4(1/0)
12(3/0)

12(1/2)
12(1/2)
20(312)

12(1/2)
12(1/2)
20(3/2)

14(1/2)
14(1/2)
20(3/2)

16(2/2)
16(2/2)
24(4/2)

18(2/2)
18(2/2)
26(4/2)

18(2/2)
16(2/2)
24(4/2)

20(312)
20(312)
28(5/2)

(An)+
-(An)
d(An)

12(3/0)
14(3/0)
16(4/0)

12(3/0)
14(3/0)
16(4/0)

20(312)
22(3/2)
24(4/2)

20(3/2)
22(3/2)
24(4/2)

20(3/2)
22(3/2)
24(4/2)

24(412)
26(4/2)
28(5/2)

26(4/2)
28(4/2)
30(5/2)

24(4/2)
26(4/2)
28(5/2)

28(5/2)
30(512)
32(6/2)

d(An,ix)*
xxx.W
xxx.L

18(4/0)
16(4/0)
20(5/0)

18(4/0)
16(4/0)
20(5/0)

26(4/2)
24(4/2)
28(5/2)

26(4/2)
24(4/2)
28(5/2)

26(4/2)
24(4/2)
28(5/2)

30(5/2)
28(5/2)
32(6/2)

32(5/2)
30(5/2)
34(6/2)

30(5/2)
28(5/2)
32(6/2)

34(6/2)
32(6/2)
36(7/2)

d(PC)
d(PC,ix)*
#xxx

16(4/0)
18(4/0)
12(3/0)

16(4/0)
18(4/0)
12(3/0)

24(4/2)
26(4/2)
20(312)

24(4/2)
26(4/2)
20(3/2)

24(4/2)
26(4/2)
20(3/2)

28(5/2)
30(5/2)
24(4/2)

30(5/2)
32(5/2)
26(4/2)

28(5/2)
30(5/2)
24(4/2)

32(5/2)
34(6/2)
28(5/2)

Source

*The size of the index register (ix) does not affect execution time.
STANDARD INSTRUCTION CLOCK PERIODS
Table 27

Instruction

Size

op, An

op, On

op On, 

ADD

Byte, Word
Long

8(110) +
6(1/0) +**

4(1/0) +
6(1/0) +**

8(1/1)+
12(1/2) +

AND

Byte, Word
Long

-

4(1/0) +
6(1/0) +**

8(111 )+
12(1/2)+

CMP

Byte, Word
Long

6(1/0)+
6(1/0) +

4(110) +
6(1/0) +

-

DIVS

-

-

158(1/0) +*

-

DIVU

-

-

140(1/0) +*

-

EOR

Byte, Word
Long

-

4(1/0)***
8(1/0)***

8(111 )+
12(1/2) +

MULS

-

-

70(110) +*

-

MULU

-

-

70(1/0) +*

-

OR

Byte, Word
Long

-

4(1/0) +
6(1/0) +**

8(1/1) +
12(1/2) +

SUB

Byte, Word
Long

8(1/0) +
6(1/0) +**

4(110) +
6(1/0) +**

8(1/1) +
12(1/2) +

-

+ add effective address calculation time
* indicates maximum value
** total of 8 clock periods for instruction if the effective address is register direct
*** only available effective address mode is data register direct
DIVS, DIVU - The divide algorithm used by the MK68000 provides less than 10% difference between the best and worst case
timings
MULS, MULU - The multiply algorithm requires 38+ 2n clocks, where n is defined as:
MULU: n = the number of ones in the 
MULS: n = concatenate of the  with a zero as the LSB; n is the resultant number of 10 or 01 patterns in the 17 -bit
source; i.e., worst case happens when the source is $5555
VI-40

IMMEDIATE INSTRUCTION CLOCK PERIODS
Table 28

Size

op #, On

op#, M

op #, An

ADDI

Byte, Word
Long

8(2/0)
16(3/0)

12(2/1)+
20(3/2) +

-

ADDQ

Byte, Word
Long

4(110)
8(1/0)

8(1/1)+
12(1/2) +

8(1/0)*
8(110)

ANDI

Byte, Word
Long

8(2/0)
16(3/0)

12(2/1) +
20(3/1) +

-

CMPI

Byte, Word
Long

8(2/0)
14(3/0)

8(2/0) +
12(3/0) +

EORI

Byte, Word
Long

8(210)
16(3/0)

12(2/1) +
20(3/2) +

-

Long

4(1/0)

-

-

ORI

Byte, Word
Long

8(2/0)
16(3/0)

12(2/1) +
20(3/2) +

-

SUBI

Byte, Word
Long

8(210)
16(3/0)

12(2/1) +
20(3/2) +

-

SUBQ

Byte, Word
Long

4(110)
8(1/0)

8(1/1) +
12(1/2) ~

8(1/0)*
8(110)

Instruction

MOVEQ

8(2/0)**
14(3/0)

-

+ add effective address calculation time
*word only
** uses CMPA instruction and only supports word or long word immediate values
SINGLE OPERAND INSTRUCTION CLOCK PERIODS
Table 29

Size

Register

Memory

Byte, Word
Long

4(1/0)
6(1/0)

8(1/1)+
12(1/2) +

Byte

6(110)

8(1/1) +

NEG

Byte, Word
Long

4(1/0)
6(1/0)

8(1/1) +
12(1/2) +

NEGX

Byte, Word
Long

4(1/0)
6(1/0)

8(1/1) +
12(1/2) +

NOT

Byte, Word
Long

4(110)
6(1/0)

8(1/1) +
12(1/2) +

See

Byte, False
Byte, True

4(110)
6(1/0)

8(1/1) +
8(1/1) +

TAS

Byte

4(1/0)

10(1/1) +

TST

Byte, Word
Long

4(110)
4(1/0)

4(1/0)
4(1/0) +

Instruction

CLR
NBCD

+ add effective address calculation time

VI-41

II

SHIFTIROTATE INSTRUCTION CLOCK PERIODS
Table 30

Size

Register

Memory

Byte, Word
Long

6 + 2n(1/0)
8 + 2n(1/0)

8(1/1) +

ASR, ASL

Byte, Word
Long

6 + 2n(1/0)
8 + 2n(1/0)

8(1/1) +

LSR. LSL

Byte, Word
Long

6 + 2n(1I0)
8 + 2n(1/0)

8(1/1) +

ROR, ROL

Byte, Word
Long

6 + 2n(1/0)
8 + 2n(1/0)

8(111) +

ROXR,ROXL

Instruction

-

-

-

+ add effective address calculation time
n is the shift or rotate count

BIT MANIPULATION INSTRUCTION CLOCK PERIODS
Table 31

Dynamic

Static

Instruction

Size

Register

Memory

Register

Memory

Byte
Long

-

BCHG

8(110)*

8(111 )+

-

12(2/1)+

-

12(2/0)*

-

Byte
Long

-

BCLR

10(1/0)*

8(111 )+

-

12(2/1 )+

-

14(2/0)*

-

Byte
Long

-

BSET

8(1/0)*

8(111 )+

-

12(2/1 )+

-

12(2/0)*

-

Byte
Long

-

BTST

6(1/0)

4(110)+

-

8(2/0)+

-

10(2/0)

-

+ add effective address calculation time
* indicates maximum value
CONDITIONAL INSTRUCTION CLOCK PERIODS
Table 32

Trap or Branch
Taken

Trap or Branch
Not Taken

Byte
Word

10(2/0)
10(2/0)

8(110)
12(2/0)

BRA

Byte
Word

10(2/0)
10(2/0)

-

Byte
Word

18(2/2)
18(2/2)

-

BSR

CC true
CC false

-

DBee

10(2/0)

12(2/0)
14(3/0)

CHK

-

40(513)+ *

8(1/0)+

TRAP

-

34(4/3)

-

TRAPV

-

34(5/3)

4(110)

Instruction

Displacement

Bee

+ add effective address calculation time

* indicates maximum value
VI-42

-

JMP, JSR, LEA, PEA, MOVEM INSTRUCTION CLOCK PERIODS
Table 33

Instr

Size

(An)

(An)+

-(An)

dIAn)

d(An,ix)+

xxx.W

xxx.L

d(PC)

d(PC,ix)*

JMP

-

8(2/0)

-

-

10(2/0)

14(3/0)

10(2/0)

12(3/0)

10(2/0)

14(3/0)

JSR

-

16(2/2)

-

-

18(2/2)

22(2/2)

18(2/2)

20(3/2)

18(2/2)

22(2/2)

LEA

-

4(110)

-

-

8(2/0)

12(2/0)

8(210)

12(3/0)

8(210)

12(2/0)

PEA

-

12(1/2)

-

-

16(2/2)

20(2/2)

16(2/2)

20(3/2)

16(2/2)

20(2/2)

MOVEM

Word

M-'R

Long

MOVEM

Word

R~M

Long

12 + 4n
12 + 4n
(3 + n/O) (3 + n/O)
12 + 8n
12 + 8n
(3 + 2n/0) (3 + 2n/0)
8 + 5n
(2/n)
8 + 10n
(2/2n)

-

-

-

-

16 + 4n
18 + 4n
16 + 4n
20 + 4n
18 + 4n
16 + 4n
(4 + n/O) (4 + n/O) (4 + n/O) (5 + n/O) (4 + n/O) (4 + n/O)
16 + 8n
18 + 8n
16 + 8n
20 + 8n
16 + 8n
18 + 8n
(4 + 2n/0) (4 + 2n/0) (4 + 2n/0) (5 + 2n/0) (4 + 2n/0) (4 + 2n/0)

8 + 5n 12 + 5n
(2/n)
(3/n)
8 + 10n 12 + 10n
(2/2n)
(3/2n)

14 + 5n
(3/n)
14 + 10n
(3/2n)

12 + 5n
16 + 5n
(3/n)
(4/n)
12 + 10n 16 + 10n
(3/2n)
(4/2n)

-

-

-

-

-

-

II

n is the number of registers to move

* is the size of the index register (ix) does not affect the instruction's execution time
time to fetch immediate operands, perform the operations,
store the results, and read the next operation. The number
of bus read and write cycles is shown in parenthesis as:
(r/w). The number of clock periods plus the number of read
and write cycles must be added to those of the effective
address calculation where indicated.

EFFECTIVE ADDRESS OPERAND CALCULATION
TIMING
Table 24 lists the number of clock periods required to
compute an instruction's effective address. It includes
fetching of any extension words, the address computation,
and fetching of the memory operand. The number of bus
read and write cycles is shown in parenthesis as (rIw). Note
there are no write cycles involved in processing the effective
address.

In Table 28, the headings have the following meanings: # =
immediate operand, Dn = data register operand, M
memory operand, and An = address register operand.

MOVE INSTRUCTION CLOCK PERIODS

SINGLE OPERAND INSTRUCTION CLOCK PERIODS

Tables 25 and 26 indicate the number of clock periods for
the move instruction. This data includes instruction fetch,
operand reads, and operand writes. The number of bus read
and write cycles is shown in parenthesis as: (r/w).

Table 29 indicates the number of clock periods for the single
operand instructions. The number of bus read and write
cycles is shown in parenthesis as: (r/w). The number of
clock periods plus the number of read and write cycles must

STANDARD INSTRUCTION CLOCK PERIODS

MULTI-PRECISION INSTRUCTION CLOCK PERIODS
Table 34

The number of clock periods shown in Table 27 indicates
the time required to perform the operations, store the
results, and read the next instruction. The number of bus
read and write cycles is shown in parenthesis as: (r/w). The
number of clock periods plus the number of read and write
cycles must be added to those of the effective address
calculation where indicated.

Size

op Dn, Dn

opM, M

ADDX

Byte, Word
Long

4(1/0)
8(110)

18(3/1 )
30(5/2)

CMPM

Byte, Word
Long

-

12(3/0)
20(5/0)

SUBX

Byte, Word
Long

4(110)
8(1/0)

18(3/1)
30(5/2)

ABCD

Byte

6(110)

18(3/1 )

SBCD

Byte

6(110)

18(3/1)

Instruction

In Table 27, the headings have the following meanings. An

= address register operand, Dn = data register operand, ea
= an operand specified by an effective address, and M =
memory effective address operand.
IMMEDIATE INSTRUCTION CLOCK PERIODS
The number of clock periods shown in Table 28 includesthe
VI-43

be added to those of the effective address ca Icu lation where
indicated.

be added to those of the effective address calculation where
indicated.

SHIFTI ROTATE INSTRUCTION CLOCK PERIODS

BIT MANIPULATION INSTRUCTION CLOCK PERIODS

Table 30 indicates the number of clock periods for the shift
and rotate instructions. The number of bus read and write
cycles is shown in parenthesis as: (r/w). The number of
clock periods plus the number of read and write cycles must

Table 31 indicates the number of clock periods required for
the bit manipulation instructions. The number of bus read
and write cycles is shown in parenthesis as: (r/w). The
number of clock periods plus the number of read and write

MISCELLANEOUS INSTRUCTION CLOCK PERIODS
Table 35

Instruction

Size

Register

Memory

Register - Memory

Memory - Register

ANDI to CCR

Byte

20(3/0)

-

-

Word

20(3/0)

-

-

-

Byte

20(3/0)

-

-

-

EORI to SR

Word

20(3/0)

-

-

-

ORI to CCR

Byte

20(3/0)

-

-

-

ORI to SR

Word

20(3/0)

-

MOVE from SR

-

6(110)

8(111 )+

-

-

MOVE to CCR

-

12(2/0)

12(2/0)+

-

-

MOVE to SR

-

12(2/0)

12(2/0)+

-

-

Word

-

-

16(2/2)

16(4/0)

Long

-

-

24(2/4)

24(6/0)

-

6(110)

-

-

-

Word

4(1/0)

-

-

-

EXT

Long

4(1/0)

-

-

-

LINK

-

16(2/2)

-

-

-

MOVE from USP

-

4(110)

-

-

-

MOVE to USP

-

4(1/0)

-

-

-

NOP

-

4(1/0)

-

-

-

RESET

-

132(1/0)

-

-

-

RTE

-

20(5/0)

-

-

-

RTR

-

20(5/0)

-

-

-

RTS

-

16(4/0)

-

-

-

STOP

-

4(010)

-

-

-

SWAP

-

4(1/0)

-

-

-

UNLK

-

12(3/0)

-

-

-

ANDI to SR
EORI to CCR

MOVEP
EXG

+ add effective address calculation time
VI-44

-

AC ELECTRICAL WAVEFORMS
Figure 36
These waveforms should only be referenced in regard to the edge-to-edge measurement of the timing specifications. They are not intended as a
functional description of the input and output signals. Refer to other functional descriptions and their related diagrams for device operation.

\~----------1H~----------

~--~--------------~5'~------------------~~--~

E

CLK

A23-A1

FC2-FCO

•

------~--~~~~

------:----:-7"--!'c~-~<----:-;____t____;_;_~;::;:__-_;_----'

LDS. UDS READ CYCLE

LDS. UDSWRITECYCLE

R/WREAD CYCLE

--------------~--~

R/WWRITE CYCLE

~0r-

DATA OUT

55~~_ _~11......::::::::r

____________________________3®~47~~________________________~~11~~
}--

ASYNCHRONOUS INPUTS
(SEE NOTE 1) - - - - - - - - - - - - HALT. RESET (INPUT)-- -

-

-

-

-

-

-

__

-

---------------------,

DATA IN- -

-- -

-

-

-

-

-

-

-

-

NOTE1: Setup time for the asynchronous inputs BERR. BGACK. BR.
DTACK. IPLO-IPL2. and VPA guarantees their recognition at the next
falling edge of the clock.

-- - - -- -

-

-- -- - -

NOTE 2: Waveform measurements for all inputs and outputs are
specified at: logic high 2.0 volts. logic low 0.8 volts.

VI-45

=

=

cycles must be added to those of the effective address
calculation where indicated.

EXCEPTION PROCESSING CLOCK PERIODS
Table 36

CONDITIONAL INSTRUCTION CLOCK PERIODS
Exception

Periods

Address Error

50(4/7)

Bus Error

50(4/7)

Interrupt

44(5/3)*

JMP, JSR, LEA, PEA, MOVEM INSTRUCTION CLOCK
PERIODS

Illegal Instruction

34(4/3)

Privileged Instruction

34(4/3)

Table 33 indicates the number of clock periods required for
the jump, jump to subroutine, load effective address, push
effective address, and move multiple registers instructions.
The number of bus read and write cycles is shown in
parenthesis as: (r/w).

Trace

34(4/3)

Table 32 indicates the number of clock periods required for
the conditional instructions. The number of bus read and
write cycles is indicated in parenthesis as: (r/w). The
number of clock periods plus the number of read and write
cycles must be added to those of the effective address
calculation where indicated.

*The interrupt acknowledge bus cycle is assumed to take
four external clock periods

MULTI-PRECISION INSTRUCTION CLOCK PERIODS
Table 34 indicates the number of clock periods for the
multi-precision instructions. The number of clock periods
includes the time to fetch both operands, perform the
operations, store the results, and read the next instructions.
The number of read and write cycles is shown in
parenthesis as: (r/w).
In Table 34, the headings have the following meanings: Dn
= data register operand and M = memory operand.

MISCELLANEOUS INSTRUCTION CLOCK 'PERIODS
Table 35 indicates the number of clock periods for the
following miscellaneous instructions. The number of bus
read and write cycles is shown in parenthesis as: (r/w). The
number of clock periods plus the number of read and write
cycles must be added to those of the effective address
calculation where indicated.

EXCEPTION PROCESSING CLOCK PERIODS
Table 36 indicates the number of clock periods for exception
processing. The number of clock periods includes the time for
all stacking, the vector fetch, and the fetch of the first
instruction of the handler routine. The number of bus read
and write cycles is shown in parenthesis as: (r/w).

VI-46

AC ELECTRICAL SPECIFICATIONS
(Vcc = 5.0 Vdc ± 5%; Vss = 0 Vdc; TA = O°C to 70°C, Figure 34)

No.

Characteristic

SMHz
8MHz
10MHz
4MHz
Symbol MKS8000-4 MKS8000-S MKS8000-8 MKS8000-10
Min Max Min Max Min Max Min Max

Unit

1

Clock Period

tcyc

250

500

167

500

125

500

100

500

ns

2

Clock Width Low

tCl

115

250

75

250

55

250

45

250

ns

3

Clock Width High

tCH

115

250

75

250

55

250

45

250

ns

4

Clock Fall Time

tct

-

10

-

10

-

10

-

10

ns

5

Clock Rise Time

tCr

-

10

-

10

-

10

-

10

ns

6

Clock Low to Address

tCLAV

-

90

-

80

-

70

-

55

ns

6A

Clock High to FC Valid

tCHFCV

-

90

-

80

-

70

-

60

ns

7

Clock High to Address/Data
High Impedance (maximum)

tCHAZx

-

120

-

100

-

80

-

70

ns

8

Clock High to Address/FC
Invalid (minimum)

t CHAZn

0

-

0

-

0

-

0

-

ns

9'

Clock High to AS, DS Low
(maximum)

t cHSLx

-

80

-

70

-

60

-

55

ns

10

Clock High to AS, DS Low
(minimum)

tCHSln

0

-

0

-

0

-

0

-

ns

112

Address to AS, DS
(read) Low/ AS Write

t AVSl

55

-

35

-

30

-

20

-

ns

11A2

FC valid to AS, DS
(read) Low/ AS Write

tFCVSl

80

-

70

-

60

-

50

-

ns

12'

Clock Low to AS, DS High

t ClSH

-

90

-

80

-

70

-

55

ns

13 2

AS, DS High to Address/FC
Invalid

tSHAZ

60

-

40

-

30

-

20

-

ns

142

AS, DS Width Low (read)!
AS Write

tSl

535

-

337

-

240

-

195

-

ns

-

285

-

170

-

115

-

95

-

ns

tSH

285

-

180

-

150

-

105

-

ns

14A2

DS Width Low (Write)

(

15 2

AS, DS Width High

16

Clock High to AS, DS High
Impedance

t CHSZ

-

120

-

100

-

80

-

70

ns

172

AS, DS High to R/W High

tSHRH

60

-

50

-

40

-

20

-

ns

18'

Clock High to R/W High (maximum)

tCHRHx

-

90

-

80

-

70

-

60

ns

19

Clock High to R/W High (minimum)

tCHRHn

0

-

0

-

0

-

0

-

ns

20'

Clock High to R/W Low

tCHRl

-

90

-

80

-

70

-

60

ns

20A

AS Low to R/W Valid

t ASRV

-

20

-

20

-

20

-

20

ns

212

Address/Valid to RIW Low

t AVRl

45

-

25

-

20

-

0

-

ns

VI-47

III

AC ELECTRICAL SPECIFICATIONS (Continued)
(Vcc

=5.0 Vdc ± 5%; V ss =0 Vdc; TA =O°C to 70°C, Figure 34)

No.
21A2

Characteristic
FC Valid to RIW Low

8MHz
10 MHz
SMHz
4MHz
Symbol MKS8000-4 MKS8000-S MKS8000-8 MKS8000-10
Min Max Min Max Min Max Min Max

Unit

tFCVRL

80

-

70

-

60

-

50

-

ns

222

R/W Low to

OS Low (write)

t RLSL

200

-

140

-

80

-

50

-

ns

23

Clock Low to Data Out Valid

t CLOO

-

90

-

80

-

70

-

55

ns

24

Clock High to R/W, VMA High
Impedance

tCHRZ

-

120

-

100

-

80

-

70

ns

25 2

DS High to Data Out Invalid

t SHoO

60

-

40

-

30

-

20

-

ns

26 2

Data Out Valid to DS Low (write)

tOOSL

55

-

35

-

30

-

20

-

ns

27 5

Data In to Clock Low (set up time)

t OICL

30

-

25

-

15

-

10

-

ns

28 2

AS, DS High to DTACK High

tSHOAH

0

490

0

325

0

245

0

190

ns

29

DS High to Data Invalid (hold time)

t SHol

0

-

0

-

0

-

0

-

ns

30

AS, DS High to BERR High

tSHBEH

0

-

0

-

0

-

0

-

ns

DTACK Low to Data In (setup time)

tOALOI

-

180

-

120

-

90

-

65

ns

312,5
32

HALT and RESET Input Transition
Time

tRHrf

0

200

0

200

0

200

0

200

ns

33

Clock High to BG Low

t CHGL

-

90

-

80

-

70

-

60

ns

34

Clock High to BG High

t CHGH

-

90

-

80

-

70

-

60

ns

35

BR Low to BG Low

tBRLGL

1.5

3.5

1.5

3.5

1.5

3.5

1.5

3.5

clk. per.

36

BR High to BG High

tBRHGH

1.5

3.0

1.5

3.0

1.5

3.0

1.5

3.0

clk. per.

37

BGACK Low to BG High

tGALGH

1.5

3.0

1.5

3.0

1.5

3.0

1.5

3.0

elk. per.

BGACK Low to BR High
(to Prevent Rearbitration)

tBGKBR

30

-

25

-

20

-

20

-

ns

37A

38

BG Low to Bus High Impedance
(with AS high)

tGLZ

-

120

-

100

-

80

-

70

ns

39

BG Width High

tGH

1.5

-

1.5

-

1.5

-

1.5

-

clk. per.

40

Clock Low to VMA Low

tCLVML

-

90

-

80

-

70

-

70

ns

41

Clock Low to E Transition

tCLE

-

100

-

85

-

70

-

55

ns

42

E Output Rise and Fall Time

tErf

-

25

-

25

-

25

-

25

ns

43

VMA Low to E High

tVMLEH

325

-

240

-

200

-

150

-

ns

44

AS, DS High to VPA High

tSHVPH

0

240

0

160

0

120

0

90

ns

45

E Low to Address/VMAlFC
Invalid

tELAI

55

-

35

-

30

-

10

-

ns

46

BGACKWidth

t BGL

1.5

-

1.5

-

1.5

-

1.5

-

elk. per.

47 5

Asynchronous Input Setup Time

t ASI

30

-

25

-

20

-

20

-

ns

VI-48

AC ELECTRICAL SPECIFICATIONS (Continued)
(Vcc = 5.0 Vdc ± 5%; Vss = 0 Vdc; TA = O°C to 70°C, Figure 34)
No.

Characteristic

8MHz
4MHz
S MHz
10 MHz
Symbol MKS8000-4 MKS8000-S MKS8000-8 MKS8000-1C
Min Max Min Max Min Max Min Max

48 3

BERR Low to DTACK Low

tBELDAL

50

-

50

-

50

-

50

-

ns

49

E Low to AS, DS Invalid

t ELSI

-80

-

-80

-

-80

-

-80

-

ns

50

E Width High

tEH

900

-

600

-

450

-

350

-

ns

51

E Width Low

tEL

1400

-

900

-

700

-

550

-

ns

52

E Extended Rise Time

tCIEHX

80

-

80

-

80

-

80

-

ns

53

Data Hold from Clock High

t CHDO

0

-

0

-

0

-

0

-

ns

54

Data Hold from E Low (Write)

tELDOZ

60

-

40

-

30

-

20

-

ns

55

R/W to Data bus Impedance change

t RLDO

55

-

35

-

30

-

20

-

ns

56

Halt/RESET Pulse Width (Note 4)

t HRPW

10

-

10

-

10

-

10

-

!elk. per.

NOTES:
1. For a loading capacitance of less than or equal to 50 picofarads, subtract 5
nanoseconds from the values given in these columns.
2. Actual value depends on actual clock period.
3. If #47 is satisfied for both DTACK and BERR, #48 may be 0 ns.

Unit

4. After VCC has been applied for 100 ms.
5. If the asynchronous setup time(#47) requirements are satisfied, the DTACK
low-to-data setup time (#31) requirement can be ignored. The data must
only satisfy the data-in to clock-low setup time (#27) for the following cycle.

AC ELECTRICAL WAVEFORMS - BUS ARBITRATION
Figure 37

!~~O:;~

______________ ~-----

~1

~

-F9

:;;:A}....--.-;
I

elK
These waveforms should only be referenced in regard to the edge-to-edge measurement of the timing specifications. They are not intended as a
functional description of the input and output signals. Refer to other functional descriptions and their related diagrams for device operation

RESET TEST LOAD

HALT TEST LOAD

TEST LOADS

Figure 38

Figure 39

Figure 40

+5Vdc

+5 Vdc

+5Vdc
TEST
POINT

2.9n

910n

MMD7000
I130PF

I

OR EQUIVALENT

70PF

~ln:I~~~/;1 Parasiticsl
RL = 6.0 kfl for
AS. A1-A23, BG, 00-015. E
FCO-FC2. LOS, R/iN. UOS. VMA
*R = 1.22 kll for A 1·A23. BG.
E. FCO-FC2

VI-49

II

DC ELECTRICAL CHARACTERISTICS
(Vee = 5.0 Vdc ± 5%; V ss = 0 Vdc; TA = O°C to 70°C, Figures 35, 36, 37)
Symbol

Min

Max

Unit

Input High Voltage

V 1H

2.0

Vee

Vdc

Input Low Voltage

V 1L

Vss - 0.3

0.8

Vdc

BERR, BGACK, BR, VPA,
DTACK, CLOCK, IPLO-IPL2,
HALT, RESET

lin

-

2.5
20

/.IAdc

-

AS, A 1-A23, DO-D15,
FCO-FC2, LDS,
R/W, UDS, VMA

ITS1

-

20

MAdc

AS, A 1-A23, BG, E***
DO-D15, E, FCO-FC2,
LDS,R/W,UDS,VMA

V OH

2.4

-

Vdc

Characteristic

Input Leakage Current
@5.25V

Three-State (Off State) Input Current
@ 2.4 V/O.4 V

Output High Voltage (lOH

= -400 MAdc)

E*
Output Low Voltage
(lOL = 1.6mA)
(lOL = 3.2mA)
(lOL = 5.0mA)
(lOL = 5.3mA)

V ee-O·75

HALT
A 1-A23, BG, FCO-FC2
RESET
E, AS, DO-D15, LDS, RIW,
UDS, VMA

Power Dissipation (Clock Frequency
8 MHz)****

=

Capacitance (Package Type Dependent)
(V in = 0 Vdc; TA = 25°C;
Frequency = 1 MHz**)

-

0.5
0.5
0.5
0.5

PD

-

1.5

W

Cin

-

20.0

pF

-

VOL

-

*with external pullup resistor of 1 .1 K n
**capacitance is periodically sampled rather than 100% tested
***without external pullup resistor
****During normal operation instantaneous Vee current requirements may Ibe as high as LSA
MAXIMUM RATINGS
Rating

Symbol

Value

Unit

Supply Voltage

Vee

-0.3 to + 7.0 Vdc

Input Voltage

V in

-0.3 to + 7.0 Vdc

Operating Temperature

TA

Oto70

°C

Storage Temperature

Tstg

-55 to 150

°C

VI-50

Vdc

MK68000 ORDERING INFORMATION
PART
NO.

PACKAGE
TYPE

MAX. CLOCK

MK68000P-4

Ceramic

4.0 MHz

MK68000P-6

Ceramic

6.0 MHz

MK68000P-8

Ceramic

8.0 MHz

MK68000P-10

Ceramic

10.0 MHz

FREQUENCY

TEMPERATURE
RANGE

0° to 70°C

VI-51

VI-52

m
.

UNITED

MICROCOMPUTER
COMPONENTS

TECHNOLOGIES
MOSTEK

16-BIT MICROPROCESSOR
WITH 8-BIT DATA BUS
MK68008
FEATURES

MK68008
Figure 1

D 17 32-bit data and address registers
D 56 basic instruction types
D Extensive exception processing
D Memory mapped 1/0

•

D 14 addressing modes
D Complete code compatibility with the MK68000
GENERAL DESCRIPTION
The MK68008 is a member of the MK68000 family of advanced microprocessors. This device allows the design
of cost effective systems using 8-bit data buses, while
providing the benfits of a 32-bit microprocessor architecture. The performance of the MK68008 is greater than any
8-bit microprocessor and superior to several 16-bit microprocessors.
A system implementation based on an 8-bit data bus reduces system cost, in compairson to 16-bit systems, due
to a more effective use of components, byte-wide memories, and peripherals. In addition, the non-multiplexed address and data buses eliminate the need for external
demultiplexers, thus further simplifying the system.
The MK68008 has full code compatibility (source and
object) with the MK68000, which allows programs to be
run on either MPU, depending on performance requirements and cost objectives.
The 1 megabyte, non-segmented linear address space of
the MK68008 allows large modular programs to be developed and executed efficiently. A large linear address space
allows program segment sizes to be determined by the
application, rather than forcing the designer to adopt an
arbitrary segment size without regard to his individual requirements.
The programmer's model, as shown in Figure 3, is identical to that of the MK68000, with 17 32-bit registers, a 32-bit
program counter, and a 16-bit status register. The first eight
registers (DO-D7) are used as data registers for byte (8-bit),
word (16-bit), and long word (32-bit) operations.

VI-53

PIN ASSIGNMENT
Figure 2

A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14

Vee
A15
GNO
A16
A17
A18
A19
07
06
05
04
03

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

M
K
6
8
0
0
8

48
47
36
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

A2
A1
AO
FCO
FC1
FC2

1P[2/0
IPl1
BERR

VPA
E

RESET
HALT
GNO
ClK
BR

BG
OTACK
R/W

OS
AS
DO
01
02

The second set of seven registers (AO-A6) and the system
stack pOinter (A7) may be used as software stack pointers
and base address registers. In addition, the registers may
be used for word and long word operations. All of the 17
registers may be used as index registers.

STATUS REGISTER
Figure 4

System Byte

The system stack is used by many instructions. The 14
addressing modes allow the creation of user stacks and
queues. The system stack pOinter is either the supervisor
stack pOinter (SSP) or the user stack pointer (USP), depending on the state of the S bit in the status register.
If the S bit indicates that the processor is in the user state,
then the USP is the active system stack pointer, and the
SSP is protected from user modification.
The status register, as shown in Figure 4, may be considered as two bytes: the user byte and the system byte.
The user byte contains five bits defining the overflow (V),
zero (2), negative (N), carry (C), and extended (X) condition codes. The system byte contains five bits. Three bits
are used to define the current interrupt priority; any interrupt level higher than the current mask level will be
recognized. (Note that level 7 interrupts are non-maskable-that is, level 7 interrupts are always processed).
Two additional bits indicate whether the processor is in
the trace (T) mode and/or in the supervisor (S) state.
PROGRAMMER'S MODEL

Interrupt
Mask

User Byte
(Condition Code Register)

Zero
Overflow
Carry

DATA TYPES AND ADDRESSING MODES
Five basic data types are supported. These data types are:
• Bits
• Words (16 bits)
• BCD Digits (4 bits)
• Long Words (32 bits)

Figure 3

• Bytes (8 bits)
31
fff-

-

-

31

rr-

16 15

87

I

I

I
I

I
I

I
I

I

I
I
I

I

I

I

1

- 00
01
- 02
- 03

-

-

04

I

f-

I

I
I

!

r-------U;e"; s'taZkp;;i;;t'e7 ----

I

Eight
Oata
Registers

05
06
07

Most instructions can use any of the 14 addressing modes
which are listed in Table 1. These addressing modes consist of six basic types:
• Register Direct

AO
- A1
- A2
- A3

• Register Indirect
Seven
Address
Registers

• Absolute

- A4

-

• Program Counter Relative

A5
- A6

-lA

L____S~~v~o~t~k!~t~ _ _ _ _ J
~

In addition, operations on other data types such as memory addresses, status word data, etc., are provided in the
instruction set.

1615

r-

r-

I

I

I

I
I
I
I

f-

I
I
I

o

0

I
15
87
0
ISystem Byte: User Byte I

7

Two Stack
Pointers

• Immediate
• Implied

Program
Counter
Status
Register

VI-54

ADDRESSING MODES
Table 1

Mode
Register Direct Addressing
Data Register Direct
Address Register Direct
Absolute Data Addressing
Absolute Short
Absolute Long
program counter Relative Addressing
Relative with Offset
Relative with Index and Offset
Register Indirect Addressing
Register Indirect
Postincrement Register Indirect
Predecrement Register Indirect
Register Indirect with Offset
Indexed Register Indirect with Offset
Immediate Data Addressing
Immediate
Quick Immediate
Implied Addressing
Implied Register

Generation
EA=Dn
EA=An
EA=(Next Word)
EA=(Next Two Words)
EA=(PC)+d 16
EA=(PC)+(Xn)+d s
EA=(An)
EA=(An), An-An+N
An-An-N, EA=(An)
EA=(An)+d 16
EA=(An)+(Xn)+d s
DATA=Next Word(s)
Inherent Data
EA=SR, USp, Sp, PC

NOTES:
EA = Effective Address
An =Address Register
Dn = Data Register
Xn=Address or Data Register used as Index Register
SR=Status Register
PC=Program Counter
( ) = Contents of
da=S-Bit Offset (Displacement)
d 16 =16-Bit Offset (Displacement)
N = 1 for byte, 2 for word, and 4 for long word. If An is the stack pointer and the
operand is byte, N =2 to keep the stack pointer on a word boundary.
-=Replaces

The register indirect addressing modes also have the
capability to perform post-incrementing, pre-decrementing,
offsetting, and indexing. The program counter relative
mode may be used in combination with indexing and offseting for writing relactable programs.
INSTRUCTION SET OVERVIEW
The MK68008 is completely code compatible with the
MK68000. This means that programs developed for the
MK68000 will run on the MK68008 and vice versa. This
applies equally to either source code or object code.

VI-55

The instruction set was designed to minimized the number
of mnemonics remembered by the programmer. To further
reduce the programmer's burden, the addressing modes
are orthogonal.
The instruction set, shown in Table 2, forms a set of programming tools that include all processor functions to perform data movement, integer arithmetic, logical operations,
shift and rotate operations, bit manipulation, BCD operations, and both program and system control. Some additional instructions are variations or subsets of these and
appear in Table 3.

II

INSTRUCTION SET

VARIATIONS OF INSTRUCTION TYPES

Table 2

Table 3

Mnemonic
ABCD
ADD
AND
ASL
ASR
Bee
BCHG
BCLR
BRA
BSET
BSR
BTST
CHK
CLR
CMP
DBee
DIVS
DIVU
EOR
EXG
EXT
JMP
JSR
LEA
LINK
LSL
LSR
MOVE
MOVEM
MOVEP
MULS
MULU
NBCD
NEG
NOP
NOT
OR
PEA
RESET
ROL
ROR
ROXL
ROXR
RTE
RTR
RTS
SBCD
See
STOP
SUB
SWAP
TAS
TRAP
TRAPV
TST
UNLK

Description
Add Decimal With Extend
Add
Logical And
Arithmetic Shift Left
Arithmetic Shift Right
Branch Conditionally
Bit Test and Change
Bit Test and Clear
Branch Always
Bit Test and Set
Branch to Subroutine
Bit Test
Check Register Against Bounds
Clear Operand
Compare
Test Condition, Decrement and Branch
Signed Divide
Unsigned Divide
Exclusive Or
Exchange Registers
Sign Extend
Jump
Jump to Subroutine
Load Effective Address
Link Stack
Logical Shift Left
Logical Shift Right
Move
Move Multiple Registers
Move Peripheral Data
Signed Multiply
Unsigned Multiply
Negate Decimal with Extend
Negate
No Operation
One's Complement
Logical Or
Push Effective Address
Reset External Devices
Rotate Left without Extend
Rotate Right without Extend
Rotate Left with Extend
Rotate Right with Extend
Return from Exception
Return and Restore
Return from Subroutine
Subtract Decimal with Extend
Set Conditional
Stop
Subtract
Swap Data Register Halves
Test and Operand
Trap
Trap on Overflow
Test
Unlink

Instruction
Type
ADD

AND

Variation
ADD
ADDA
ADDQ
ADDI
ADDX
AND
ANDI
ANDI to CCR
ANDI to SR

CMP

CMP
CMPA
CMPM
CMPI

EOR

EOR
EORI
EORI to CCR

EORI to SR

MOVE

MOVE
MOVEA
MOVEQ
MOVE from SR
MOVE to SR
MOVE to CCR
MOVE USP

NEG

NEG
NEGX

OR

OR
ORI
ORI to CCR
ORI to SR

SUB

SUB
SUBA
SUBI
SUBQ
SUBX

VI-56

Description
Add
Add Address
Add Quick
Add Immediate
Add with Extend
Logical And
And Immediate
And Immediate to
Condition Codes
And Immediate to
Status Register
Compare
Compare Address
Compare Memory
Compare
Immediate
Exclusive Or
Exclusive Or
Immediate
Exclusive Or
Immediate to
Condition Codes
Exclusive Or
Immediate to
Status Register
Move
Move Address
Move Quick
Move from Status
Register
Move to Status
Register
Move to Condition
Codes
Move User Stack
Pointer
Negate
Negate with
Extend
Logical Or
Or Immediate
Or Immediate to
Condition Codes
Or Immediate to
Status Register
Subtract
Subtract Address
Subtract
Immediate
Subtract Quick
Subtract with
Extend

ORDERING INFORMATION

Part No.
MK6S00SN-S
MK6S00SN-10

Package Type
Plastic
Plastic

Max. Clock Frequency
s.o MHz
10.0 MHz

Temperature Range
00 to 700 C
00 to 70 0 C

•

VI-57

VI-58

m

UNITED

TECHNOLOGIES
MOSTEK

MICROCOMPUTER
COMPONENTS
VIRTUAL MEMORY
MICROPROCESSOR
MK68010

FEATURES

o
o

MK68010
Figure 1

17 32-bit data and address registers
16-megabyte direct addressing range

o Virtual
o 57

memory/machine support

powerful instruction types

D High-performance looping instructions

o Operations on five

main data types

II

D Memory mapped 1/0

o 14 addressing

modes

GENERAL DESCRIPTION

The MK68010 is the third in a family of advanced
microprocessors from Mostek. Utilizing VLSI technology,
the MK68010 is a fully implemented 16-bit microprocessor
with 32-bit registers, a rich basic instruction set, and versatile addressing modes.
The MK68010 is fully object code compatible with the
earlier members of the MK68000 family and has the added features of virtual memory support and enhanced instruction execution timing.
The MK68010 possesses an asynchronous bus structure
with a 24-bit address bus and a 16-bit data bus.
As shown in the programming model (Figures 3 and 4),
the MK68010 offers 17 32-bit general purpose registers,
a 32-bit program counter, a 16-bit status register, a 32-bit
vector base register, and two 3-bit alternate function code
registers. The first eight registers (DO-D7) are used as data
registers for byte (8-bit), word (16-bit), and long word (32-bit)
operations. The second set of seven registers (AO-A6) and
the stack pointers (SSP, USP) may be used as software
stack pointers and base address registers. In addition, the
address registers may be used for word and long word
operations. All of the 17 registers may be used as index
registers.
The status register, as shown in Figure 5, contains the interrupt mask (eight levels available) as well as the condition codes; extend (X), negative (N), zero (Z), overflow (V),
and carry (C). Additional status bits indicate that the processor is in the trace (T) mode and in the supervisor (S)
or user state.
VI-59

PIN ASSIGNMENT
Figure 2
04
03
02
01
DO

AS
uos
lOS
R/W
OTACK

iiG
iiGACR'

BR
Vee
ClK
GNO
HALT
~
VMA
E

\iPA
BERR
IPl2
IPll
IPlO
FC2
FCl
FCO
Al
A2
A3
A4

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

05
06
07
08
09
010
011
012
013
014
015
GNO
A23
A22
A21
Vee
A20
A19
A18
A17
A16
A15
A14
A13
A12
All
Al0
A9
A8
A7
A6
AS

The vector base register is used to determine the location of
the exception vector table in memory to support multiple vector tables. The alternate function code registers allow the supervisor to access user data space or emulate CPU space cycles.

FUNCTIONAL DESCRIPTION
DATA TYPES AND ADDRESSING MODES

SUPERVISOR PROGRAMMING MODEL SUPPLEMENT
Figure 4

Five basic data types are supported. These data types are:
• Bits
• BCD Digits (4 bits)

31

I

1615

0

!

I(SSP)
A7
Supervisor Stack
Pointer

L.._ _ _ _ _ _- - ' - .- - -_ _ _.......

• Bytes (8 bits)

15

87

0

1L..-__.....JiL--_c_c_R---I'SR

• Words (16 bits)

31

1'---____- - - - - - - -........1VBR

• Long Words (32 bits)

Vector Base Register

8
2

In addition, operations on other data types such as memory addresses, status word data, etc., are provided in the
instruction set.
The 14 address modes, shown in Table 1, include six basic
types:

Status Register

0

0 SFC Alternate Function
DFC Code Registers

STATUS REGISTER
Figure 5

• Register Direct
• Register Indirect
• Absolute

System Byte

User Byte
(Condition Code Register)

• Program Counter Relative
• Immediate
• Implied

Carry

Included in the register indirect addressing modes is the
capability to do post-incrementing, pre-decrementing, offsetting, and indexing. The program counter relative mode
can also be modified via indexing and offsetting.
PROGRAMMING MODEL

INSTRUCTION SET OVERVIEW

Figure 3
31

16 15
I

r
'-

-

I
I

I
I
I

--

I
I

31

1615

r
I31
I

I
I

I

87

DO
01
02

I
I
I
I

I

I
I
I
I

- 03
- 04
-- 0506
07

Oata

Registers

0

~~

Address
Registers

ItJsP) ~~7:t;rtack

0

Ipc

7
0
r::::=:=JCCR

Program
Counter
Condition Code
Register

The MK68010 instruction set is shown in Table 2. Some
additional instructions are variations, or subsets, of these,
and they appear in Table 3. Special emphasis has been
given to the instruction set's support of structured highlevel languages to facilitate ease of programming. Each
instruction, with few exceptions, operates on bytes, words,
and long words, and most instructions can use any of the
14 addressing modes. By combining instruction types, data
types, and addressing modes, over 1000 useful instructions are provided. These instructions include signed and
unsigned multiply and divide, "quick" arithmetic operations, BCD arithmetic, and expanded operations (through
traps). Also, 33 instructions may be used in the loop mode
with certain addressing modes and the DBee instruction
to provide 230 high performance string, block manipulation, and extended arithmetic operations.

VI-SO

VIRTUAL MEMORY/MACHINE CONCEPTS
In most systems that use the MK68010 as the central processor, only a fraction of the 16 megabyte address space
will actually contain physical memory. However, by using
virtual memory techniques, the system can appear to the
user to have 16 megabytes of physcial memory available.
These techniques have been used for several years in
large mainframe computers and more recently in minicomputers. Now, with the MK68010, they can be fully supported
in microprocessor-based systems.
In a virtual memory system, a user program can be written as though it has a large amount of memory available
when it actually has only a small amount of memory
physically present in the system. In a similar fashion, a
system can be designed to allow user programs to access
other types of devices not physically present in the system,
such as tape drives, disk drives, printers, or CRTs. With
proper software emulation, a physical system can be made
to appear to a user program as any other computer
system, and the program may be given full access to all
the resources of that emulated system. Such an emulated
system is called a virtual machine.
VIRTUAL MEMORY
The basic mechanism for supporting virtual memory in
computers is to provide only a limited amount of highspeed physical memory that can be accessed directly by
the processor, while maintaining an image of a much larger
"virtual" memory on secondary storage devices such as
large capacity disk drives. When the processor attempts
to access a location in the virtual memory map that is not
currently residing in physical memory (referred to as a
page fault), the access to that location is temporarily
suspended while the necessary data is fetched from the
secondary storage and placed in physical memory; the
suspended acccess is then completed. The MK68010 provides hardware support for virtual memory with the capability of suspending an instruction's execution when a bus
error is signaled and then completing the instruction after
the physical memory has been updated as necessary.
The MK68010 uses instruction continuation rather than
instruction restart to support virtual memory. With instruction restart, the processor must remember the exact state
of the system before each instruction is started to restore
that state if a page fault occurs during its execution. Then,
after the page fault has been repaired, the entire instruction that caused the fault is re-executed. With instruction
continuation, when a page fault occurs, the processor
stores its internal state and then, after the page fault is
repaired, restores that internal state and continues execution of the instruction. For the MK68010 to utilize

VI·61

instruction continuation, it stores its internal state on the
supervisor stack when a bus cycle is terminated with a
bus error signal. It then loads the program counter from
vector table entry number two (offset $008) and resumes
program execution at that new addresss. When the bus
error exception handler routine has completed execution,
an RTE instruction is executed that reloads the MK68010
with the internal state stored on the stack, re-runs the
faulted bus cycle, and continues the suspended instruction. Instruction continuation has the additional advantage
of allowing hardware support for virtual 110 devices. Since
virtual registers may be simulated in the memory map, an
access to such a register will cause a fault, and the function of the register can be emulated by software.
VIRTUAL MACHINE
One typical use for a virtual machine system is in the
development of software which is an operating system for
another machine that has hardware also under development and is not available for programming use. In such
a system, the governing operating system (OS) emulates
the hardware of the new system and allows the new OS
to be executed and debugged as though it were running
on the new hardware. Since the new OS is controlled by
the governing OS, the new one must execute at a lower
privilege level than the governing as so that any attempts
by the new OS to use virtual resources that are not
physically present, and should be emulated, will be trapped by the governing OS and handled in software. In the
MK68010, a virtual machine may be fully supported by running the new OS in the user mode and the governing OS
in the supervisor mode so that any attempts to access
supervisor resources or execute privileged instructions by
the new OS will cause a trap to the governing OS.
In order to fully support a virtual machine, the MK68010
must protect the supervisor resources from access by user
programs. The one supervisor resource not fully protected
in the MK68000 is the system byte of the status register.
In the MK68000, the MOVE from SR instruction allows user
programs to test the S bit (in addition to the T bit and interrupt mask) and thus determine that they are running in
the user mode. For full virtual machine support, a new OS
must not be aware that it is running in the user mode and
thus should not be allowed to access the S bit. For this
reason, the MOVE from SR instruction on the MK68010
is a privileged instruction, and the MOVE from CCR instruction has been added to allow user programs
unhindered access to the condition codes. By making the
MOVE from SR instruction privileged, when the new OS
attempts to access the S bit, a trap to the governing OS
will occur and the SR image passed to the new OS by the
governing OS will have the S bit set.

•

ADDRESSING MODES
18ble 1

Mode
Register Direct Addressing
Data Register Direct
Address Register Direct
Absolute Data Addressing
Absolute Short
Absolute Long
Program counter Relative Addressing
Relative with Offset
Relative with Index and Offset
Register Indirect Addressing
Register Indirect
Postincrement Register Indirect
Predecrement Register Indirect
Register Indirect with Offset
Indexed Register Indirect with Offset
Immediate Data Addressing
Immediate
Quick Immediate
Implied Addressing
Implied Register

Generation
EA=Dn
EA=An
EA={Next Word)
EA=(Next Two Words)
EA=(PC)+d 16
EA=(PC)+(Xn)+d s
EA=(An)
EA=(An), An-An+N
An-An-N, EA=(An)
EA=(An)+d 16
EA=(An)+(Xn)+d s
DATA=Next Word(s)
Inherent Data
EA=SR, USp, SSP,
PC, VBR, SFC, DFC

NOTES:
EA=Effective Address
An =Address Register
Dn = Data Register
Xn =Address or Data Register used as Index Register
SR=Status Register
PC=Program Counter
( )=Contents of
da=S·Bit Offset (Displacement)
d 16 =16·Bit Offset (Displacement)
N = 1 for byte, 2 for word, and 4 for long word. If An is the stack pOinter and the
operand size is byte, N =2 to keep the stack pointer on a word boundary.
- =Replaces

VI-62

INSTRUCTION SET SUMMARY
Table 2
---:-:---'

Mnemonic
ABCD*
ADD*
AND*
ASL*
ASR*
Bee
BCHG
BCLR
BRA
BSET
BSR
BTST
CHK
CLR*
CMP*
DBee
DIVS
DIVU
EOR*
EXG
EXT
JMP
JSR
LEA
LINK
LSL*
LSR*

Description

Mnemonic

Add Decimal with Extend
Add
Logical And
Arthmetic Shift Left
Arthmetic Shift Right
Branch Conditionally
Bit Test and Change
Bit Test and Clear
Branch Always
Bit Test and Set
Branch to Subroutine
Bit Test
Check Register Against Bounds
Clear Operand
Compare
Decrement and Branch Conditionally
Signed Divide
Unsigned Divide
Exclusive Or
Exchange Registers
Sign Extend
Jump
Jump to Subroutine
Load Effective Address
Link Stack
Logical Shift Left
Logical Shift Right

MOVE*
MULS
MULU
NBCD*
NEG*
NOP
NOT*
OR*
PEA
RESET
ROL*
ROR*
ROXL*
ROXR*
RTD
RTE
RTR
RTS
SBCD*
See
STOP
SUB*
SWAP
TAS
TRAP
TRAPV
TST*
UNLK

*Loopable Instructions

VI-63

Description
Move Source to Destination
Signed Multiply
Unsigned Multiply
Negate Decimal with Extend
Negate
No Operation
One's Complement
Logical Or
Push Effective Address
Reset External Devices
Rotate Left without Extend
Rotate Right without Extend
Rotate Left with Extend
Rotate Right with Extend
Return and Dea"ocate
Return from Exception
Return and Restore
Return from Subroutine
Subtract Decimal with Extend
Set Conditional
Stop
Subtract
Swap Data Register Halves
Test and Set Operand
Trap
Trap on Overflow
Test
Unlink

II

VARIATIONS OF INSTRUCTION TYPES
Table 3

Instruction
Type
ADD

AND

"

Variation

ADD*
ADDA*
ADDQ
ADDI
ADDX*
AND*
ANDI
ANDI to CCR
ANDI to SR

CMP

EOR

CMP*
CMPA*
CMPM*
CMPI
EOR*
EORI
EORI to CCR
EORI to SR

MOVE

NEG
OR

MOVE*
MOVEA*
MOVEC
MOVEM
MOVEP
MOVEQ
MOVES
MOVE from SR
MOVE to SR
MOVE from CCR
MOVE to CCR
MOVE USP
NEG*
NEGX*
OR*
ORI
ORI to CCR
ORI to SR

SUB

SUB*
SUBA*
SUBI
SUBQ
SUBX*

*Loopable Instructions

VI-64

Description
Add
Add Address
Add Quick
Add Immediate
Add with Extend
Logical And
And Immediate
And Immediate to
Condition Codes
And Immediate to
Status Register
Compare
Compare Address
Compare Memory
Compare Immediate
Exclusive Or
Exclusive Or Immediate
Exclusive Or Immediate to
Condition Codes
Exclusive Or Immediate to
Status Register
Move Source to Destination
Move Address
Move Control Register
Move Multiple Registers
Move Peripheral Data
Move Quick
Move Alternate Address Space
Move from Status Register
Move to Status Register
Move from Condition Codes
Move to Condition Codes
Move User Stack Pointer
Negate
Negate with Extend
Logical Or
Or Immediate
Or Immediate to
Condition Codes
Or Immediate to
Status Register
Subtract
Subtract Address
Subtract Immediate
Subract Quick
Subtract with Extend

m

UNITED

TECHNOLOGIES
MOSTEK

MICROCOMPUTER
COMPONENTS

68200 16-BIT
SINGLE-CHIP MICROCOMPUTERS
M K68201/M K68E201/M K68211/M K68E211
FEATURES

D 16-bit, high performance, single-chip microcomputer

MK68200
Figure 1

D 14 address and data registers
Eight 16-bit or sixteen 8-bit data registers
Six 16-bit address registers
D Advanced 16-bit instruction set
Bit, byte, and word operands
Nine addressing modes
Byte and word BCD arithmetic

•

D High performance (6 MHz instruction clock)
500 ns register-to-register move or add
3.5 p,s 16 x 16 multiply
4.0 p,s 32/16 divide
D Available with 0 or 4K (2K x 16) bytes of ROM
D 256 byte RAM (128 x 16)
D Three 16-bit timers
Interval modes
Event modes
One-shot modes
Pulse and period measurement modes
Two input and two output pins
D Serial channel
Double-buffered receive and transmit
Asynchronous to 375 Kbps
Synchronous to 1.5 Mbps
Address wake-up recognition and generation
Internal/external baud rate generation
D Parallel I/O
Up to 40 pins
Direction programmable by bit
One 16-bit or two 8-bit port(s) with handshaking
D Interrupt controller
16 independent vectors
Eight external interrupt sources
One non-maskable interrupt
Individual interrupt masking

D Optional external bus
16-bit, multiplexed address/data bus
Automatic bus request/grant arbitration
Two control bus versions:
68000-compatible bus (UPC)
General Purpose Bus (GP)
D 8 and 12 MHz time base versions produce 4 and 6
MHz instruction clock rates, respectively.
Crystal or external TTL clock

D Single + 5 volt power supply
D 48-pin DIP or 84-pin LCC
GENERAL DESCRIPTION
MK68200 designates a series of new, high-performance,
16-bit, single-chip microcomputers from Mostek. Implemented in Scaled Poly-5 NMOS, they incorporate an
architecture designed for superior performance in
computation-intensive control applications. A modern,
comprehensive instruction set, which features both high
speed execution and code space efficiency, is combined on-chip along with extensive, flexible I/O capabilities.
On-chip RAM and optional on-chip ROM are provided
within a full 64K byte addressing space.
VI-65

MK68200 LOGICAL PINOUT SINGLE·CHIP MODE
Figure 2

16 1/0

PORT
0

1/0 16

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

PORT
1

}~ANM
INTERRUPTS

XI2

6
6

6

XI1

4

4

XIO

3
2

SI
RClK

1

TCLK

0

1/0

0

SO

I

0

16

TAO

I

0

14

TBO

I

13

TAl

MK68200

3
2

VCC
GND

1/0

REsEi'

}_w
} nMEA.

ClKOUT

0

I

12

TBI

ClK1

I

I

11

ClK2

I

I

10

9

om"}

I

0
0

8

RDYl

NMI
MODE

STRl
RDYH

PORT
4
PORTO
HANDSHAKE

MK68200 SINGLE·CHIP PIN ASSIGNMENT (4S·PIN DIP)
Figure 3

P1-8

48

P1-9

47

VCC
P1-7

P1-10

46

P1-8/X12

P1-11

45

P1-5/X11

P1-12

44

P1-4/X10

P1-13

43

P1-3/SI

P1-14

42

P1-2/RCLK

P1-15

41

P1-1/TCLK

P4-8

40

P1-0/S0

10

38

NMi

P4-8
P4-10

11

38

RESET

P4-11

12

37

P4-12/TBI

MODE

13

38

P4-13/TAI

CLK2

14

35

P4-14/TBO

CLK1

15

34

P4-15/TAO

CLKOUT 18

33

PO-O

PO-15

17

32

PO-1

PO-14

18

31

PO-2

PO-13

18

30

PO-3

PO-12

20

29

PO-4

PO-11

21

28

PO-5

PO-10

22

27

PO-8

PO-8

23

28

PO-7

GND

24

25

PO-8

VI·66

The MK68200 is designed to serve the needs of a wide
variety of control applications, which require high performance operation with a minima~ parts count implementation. Industrial controls, instrumentation, and
intelligent computer peripheral controls are all examples
of applications served by the MK68200. High speed
mathematical ability, rapid 1/0 addressing and interrupt
response, and powerful bit manipulation instructions
provide the necessary tools for these applications. In
addition to its single-chip microcomputer configuration,
both distributed intelligence and parallel multiprocessing system configurations are supported by the
MK68200, as illustrated in Figures 12 and 13.
In applications requiring loosely coupled, distributed
intelligence, several MK68200's may be interconnected
on a common serial network. The on-chip USART supports a wake-up mode in which an additional bit is
appended to the data stream to distinguish a serial data
word as address or data. The wake-up logic prevents
the serial channel from generating interrupts unless a
specific address is recognized.
Alternately, the MK68200 may be configured as an
expandable CPU device which can access external
memory and 1/0 resources. In this operating mode,
parallel 1/0 pins are replaced by multiplexed addressl
data and control lines. Bus arbitration logic is incorporated on the chip to support a direct interface in parallel
shared bus multiprocessor system configurations. Two
versions exist which support two types of control signals
present on the expanded bus configuration. The
General Purpose (GP) bus option allows the MK68200
to operate either as an executive or a peripheral processor. As an executive procesor, the MK68200 can control an external system bus and grant the use of it to
requesting devices, such as DMA controllers andlor peripheral processors. As a peripheral control processor,
the MK68200 can provide intelligent local control of an
1/0 device in a computer system and, thereby, relieve
the executive processor of these tasks. In this configuration, the MK68200 has the capability of effectively performing DMA transfers between system memory and
the 1/0 device. The on-chip resources of ROM, RAM,
and 1/0 are accessed within the MK68200 without affecting the utilization of the shared system bus so that
only external communications compete for bus
bandwidth.
The Universal Peripheral Controller (UPC) bus option
supports a direct interface to a 68000 executive processor. Thus, the MK68200 can be used as a costeffective, intelligent peripheral controller in 68000
systems. The UPC version's direct bus interface to the
68000 makes the MK68200 particularly well-suited for
performing many intelligent 1/0 functions in a 68000
system. For example, since the MK68200 includes both
a serial channel and an external bus capable of performing DMA transfers, it can be programmed to act as

serial protocol controller with DMA capability, as shown
in Figure 4.
Table 1 summarizes the specific MK68200 device types
that are discussed in this data sheet. A complete guide
to the part numbering scheme used throughout this
document may be found in the Ordering Information
section. All MK68200 devices retain most of the 1/0
features when they are used in the expanded bus
mode; however, 24 pins of parallel 1/0 are sacrificed
when this mode is used. When the expanded bus mode
is selected, the MK68201/XX generates UPC
(68000-compatible) control signals, while the
MK68211/XX generates GP control signals. Also
available are 84-pin emulator versions of these devices
that do not have on-Chip ROM, but instead have additional pins to support a second complete address/data
bus to access off-chip ROM, RAM, EPROM, or 1/0
devices. This bus is referred to as the private bus and
is not bonded out on 48-pin versions.
For additional information on the MK68200, refer to the
MK68200 Principles of Operation Manual, publication
number 4420399, and to the MK68200 Programming
Reference Guide, publication number 4420465.
SINGLE·CHIP DESCRIPTION
Figure 2 is a diagram which illustrates the functions of
specific pins for a MK68201 or MK68211, operating in
a single-chip mode. When the device is operating in one
of the expanded bus modes, the pins on Port 0 become
the multiplexed addressldata bus, and the upper half
of Port 1 becomes the control signals (GP or UPC) for
the bus. The following description applies to the pins
only when the device is used in the non-expanded or
single-chip mode. Descriptions of the pin functions for
the expanded bus modes may be found in the Expanded Bus Operation section of this data sheet.
Vee, GND
(Power, Ground)
Power Supply pins.
(single + 5 V)
RESET
Input, active low. RESET input overrides ongoing execution (including interrupts) and resets the chip to its
initial power-up condition. RESET cannot be masked.
CLKOUT

(Clock Output)
Output. CLKOUT will output the instruction clock rate,
which is one-half of the frequency provided on CLK1
and CLK2.
CLK1, CLK2

(Time base Inputs)
Inputs. CLK1 and CLK2 may be connected to a crystal,
or CLK1 may be connected to an external TTLcompatible oscillator while CLK2 is left floating. The

VI·67

II

SERIAL DMA CONTROLLER
Figure 4

DEVICE TYPE SUMMARY
Table 1
Device
'TYpe

Ex~anded

Bus
Version

ROM
(Bytes)

RAM
(Bytes)

PKG.
48-pin DIP

MK68201/04

UPC

0

256

MK68201/44

UPC

4096

256

48-pin DIP

MK68E201/04

UPC

0

256

84-pin LCC

MK68211/04

GP

0

256

48-pin DIP

MK68211/44

GP

4096

256

48-pin DIP

MK68E211/04

GP

0

256

84-pin LCC

instruction clock rate is one-half of the frequency provided on CLK1 and CLK2.
NMI
(Non-Maskable Interrupt)
Input, active low, negative edge triggered. The NMI
request line has a higher priority than all of the maskable interrupts. NMI is always enabled regardless of
whether the L1E (Level 1 Interrupt Enable) bit is set in
the Status Register.
MODE
Input. The MODE pin is used to configure the MK68200
on power-up and reset to one of the following states:
Mode Pin
Vee
- No expansion (singie chip mode)
GND
- Partial Expansion
CLKOUT - Full Expansion

po-o - PO-15
(Port 0)
Input/Output. Each bit in Port 0 may be individually programmed for general purpose input or output. Port 0
also has several handshaking modes to allow parallel,
asynchronous communication with other devices. The
high and low bytes may be programmed individually or
jointly to be inputs, outputs, or bidirectional.

P1-0 - P1-15
(Port 1)
Input/Output. Each of the 16 bits in Port 1 may be individually programmed for input or output. Additionally,
the lowest seven bits of Port 1 may be programmed to
serve specific alternate functions, as listed below.
VI-S8

P1-6/X12
(External Interrupt 2)
Input, rising or falling edge triggered. The programmer
may select the rising or falling edge as active for X12.
P1-5/XI1
(External Interrupt 1)
Input, fixed falling edge triggered. The XI1 interrupt may
be used to interrupt the MK68200 on the falling edge
of an input pulse.
P1-4/XI0
(External Interrupt 0)
Input, low level triggered. The XIO interrupt input is leveltriggered (unlike X11, XI2). It may be used to produce
an internally vectored interrupt or to cause an external
fetch of an interrupt vector number when the MK68200
is used in an expanded mode with the GP bus.
P1-3/SI
(Serial Input)
Input, active high. SI is used to input receive serial data
when the receiver is enabled.
P1-2/RCLK
(Receive Clock)
Input/Output, active high. Depending on the mode programmed, RCLK can be used by the serial port as
either an input or an output pin. When used as an input pin, RCLK provides the receive clock and/or the
transmit clock. When RCLK is not providing the transmit
or receive clock, it can be used as an output for Timer
C. In this mode, the receive clock is being provided by
Timer C.

P1-1ITCLK
(Transmit-Clock)
Input/Output, active high. Depending on the mode programmed, TCLK can be used by the serial port as either
an input or an output pin. When used as an input pin,
TCLK provides ·the transmit clock. When TCLK is not
providing the transmit clock, it can be used as an output for Timer C. In this mode, the transmit clock is being provided by either Timer C or RCLK.
P1-1/S0
(Serial Output)
Output, active high. SO is used to output transmit serial
data when the transmitter is enabled.

P4·8 • P4·15
(Port 4)
Inputs and Outputs. P4-8, P4-9, P4-14, and P4-15 may
be used as general purpose outputs, and P4-10, P4-11 ,
P4-12, and P4-13 may be used as general purpose inputs. Interrupts may be generated on the positive transitions on P4-10 and P4-11. Depending on the mode
selected, interrupts may be generated on the positive
or negative transitions on P4-12, or they may be
generated on the positive, negative, or combined transitions on P4-13. Additionally, these bits may be programmed to serve specific alternate functions, as listed
below.
P4-15ITAO
(Timer A Output)
Output. TAO may be programmed for special functions
in the interval, event, and pulse modes for Timer A. In
the interval mode, TAO's state is determined by the
Timer A latch (high or low) that is currently active. That
is, if the counter is using the high latch for comparison,
TAO is high. If the counter is using the low latch for comparison, TAO is low. In the event mode, TAO is initialized to a "1" state and toggles each time the counter
matches the Timer A high latch. In the pulse/period
modes, TAO is initiated to a "1" state and toggles on
positive transitions on TAL
P4-14ITBO
(Timer B Ouput)
Output. TBO may be programmed for special functions
in the interval and one-shot modes for Timer B. In the
interval mode, TBO is initialized to a "1" state and toggles each time the counter matches the Timer B latch
value. In the one-shot modes, TBO is initialized to a "1"
state, and the counter begins counting in response to
the occurrence of an active edge on TBI. TBO will not
go low until the counter matches the value loaded into
the Timer B latch.
P4-13ITAI
(Timer A Input)
Input, positive and/or negative edge triggered. TAl may

be programmed for special functions in the event mode
or pulse/period modes for Timer A. In the event mode,
the counter is incremented on each active transition
(positive or negative edge programmable) on TAL In the
pulse/period modes, the counter measures the time during which the signal on TAl remains high and low.
P4-12ITBI
(Timer B Input)
Input, positive or negative edge triggered. TBI may be
programmed for special functions for the Timer B oneshot modes. In the one-shot modes, TBI acts as a trigger input
P4-11/STRH, P4-10/STRL
(Strobe High Byte, Strobe Low Byte)
Input, active high. STRH and STRL are both used for
input, output, and bidirectional handshaking on Port O.
1) Output mode: The positive edge of this strobe is
issued by the peripheral to acknowledge the receipt of
data made available by the MK68200.
2) Input mode: The stobe is issued by the peripheral
to load data from the peripheral into the Port 0 input
register. Data is latched into the MK68200 on the
negative edge of this signal.
3) Bidirectional mode: When the STRH signal is active,
data from the Port 0 output register is gated onto the
Port 0 bidirectional data bus.
The negative edge of STRH acknowledges the receipt
of the output data. The negative edge of the signal applied to the STRL signal is used to latch input data into
Port O.
P4-9/RDYH, P4-8/RDYL
(Ready High Byte, Ready Low Byte)
Output, active high. RDYH and RHYL are used for input, output, and bidirectional handshaking on Port O.
1) Output mode: The ready signal goes active to indicate
that the Port 0 output register has been loaded, and the
peripheral data is stable and ready for transfer to the
peripheral device.
2) Input mode: The ready signal is active when the Port
register is empty and is ready to accept data
from the peripheral device.

o input

3) Bidirectional mode: The RDYH signal is active when
data is available in Port 0 output register for transfer
to the peripheral device. In this mode, data is not placed on the Port 0 data bus unless STRH is active. The
RDYL signal is active when the Port 0 input register is
empty and is ready to accept data. from the peripheral
device.

VI-69

•

PROCESSOR ARCHITECTURE
The MK68200 microcomputer contains an advanced
processor architecture, combining the best properties
of both 8- and 16-blt processors. Thus a large majority
of instructions operate on either byte or word operands.
A block diagram shown in Figure 5 summarizes the Internal architecture of the MK68200.
REGISTERS
The MK68200 register set includes three system
registers, six address registers, and eight data registers.
The three 16-bit system registers, as shown in Figure
6, include a Program Counter, a Status Register, and
a Stack Pointer. The six address registers may be used
either for 16-bit data or for memory addressing. The
eight 16-bit data registers are used for data and may
also be referenced as sixteen 8-bit registers, providing
great flexibility in register allocation.
ADDRESSING
The MK68200 directly addresses a 64K byte memory
space, which is organized as 32K 16-bit words. The
memory is byte-addressable, but most transfers occur
16 bits at a time for increased performance over 8-bit
microcomputers. All inputloutput is memory-mapped,
and the on-chip 1/0 is situated in the top 1K bytes of
the address space. In the single-chip mode, all
resources including ROM, RAM, and 1/0, are accessed via an internal or private bus. The memory map,
which is accessed by this bus in the single-chip mode,
is depicted in Figure 7.
Nine addressing modes provide ease of access to data
in the MK68200, as depicted in Table 2. The four register
indirect forms utilize the address registers and the Stack
Pointer and support many common data structures such
as arrays, stacks, queues, and linked lists. 1/0 Port addressing is a short form addressing mode for the first

16 words of the I/O port space and allows most instructions to access the most often referenced 1/0 ports in
just one word. Many microcomputer applications are
1/0 intensive and short, fast addressing of 1/0 has a
significant impact on performance.
INSTRUCTION SET
The MK68200 Instruction set has been designed with
regularity and ease of programming in mind. In addition, instructions have been encoded to minimize code
space, a feature which is especially important in singlechip microcomputers. Small code space is related to
execution speed, and most instructions execute in either
three or six instruction clock periods. (An instruction
clock period is equal to 167 ns with a 6 MHz instruction
clock). See Table 3.
In addition to operations on bytes and words, the
MK68200 has rapid bit manipulation instructions that
can operate on registers, memory, and ports. The bit
to be affected may be an immediate operand of the instruction, or it may be dynamically specified in a
register. Operations available include bit set, clear, test,
change, and exchange; and all bit operations perform
a bit test as well. Since each instruction is indivisible,
this provides the necessary test-and-set function for the
implementation of semaphores.
The MOVE group of instructions has the most extensive capabilities. A wide variety of addreSSing mode
combinations is supported including memory-tomemory transfers. A special move multiple is included
to save and restore a specified portion of the registers
rapidly.
In total, the MK68200 instruction set provides a programming environment, similar to the 68000, which has
been optimized for the needs of the single-chip
microcomputer marketplace. A summary of the instruction set is provided in Table 4.

ADDRESSING MODES
Table 2

Register
Register Indirect
Register Indirect with Post-increment
Register Indirect with Pre-decrement
Register Indirect with Displacement
Program Counter Relative
Memory Absolute
Immediate
I/O Port

V1·70

MK68200 BLOCK DIAGRAM
Figure 5

GENERAL PURPOSE 1/0 (18 BITS)
OR
ADDRESS/DATA BUS (18 BITS)

M

o

GENERAL PURPOSE 1/0 (18 BITS)
OR
CONTROL BUS (8 BITS) • 1/0 (8 BITS)
XX
SRTS
I
I
ICC 0

2

D
E

1

l

l

K K

TIMER
1/0

PORTO
HANDSHAKE

T
B

T
R
H

S S

o

T
R
l

ClKl
ClK2
ClKOUT

MAIN
MIMOIn'
2K x 18 ROM

128 x 18 FlAM

V1·71

•

REGISTER SET
Figure 6
DATA REGISTERS:
OHO

OLO

DO

OH1

OL1

01
02

15

14

13

OH3

OL3

03

OH4

OL4

04

OH5

OL5

05

OH6

OL6

06

OH7

OL7

07

12

11

10

9

8

7

6

5

4

3

2

0

ADDRESS REGISTERS:

AO
A1

A2
A3
A4
A5
15

14

13

12

11

10

9

8

7

6

5

4

3

2

0

SYSTEM REGISTERS:

o
15

14

13

12

11

10

9

8

7

6

5

4

3

2

14

13

12

11

10

9

8

7

6

5

4

3

2

SP

I

PC

0

o
15

I

0

I
15

14

13

12

11

10

9

8

VI-72

7

6

5

4

3

2

0

SR

ADDRESSING SPACE FOR SINGLE-CHIP CONFIGURATION
Figure 7

ADDRESS

CONTENTS

$FFFF
FUTURE 1/0 EXPANSION AREA
(RESERVED)
$FC28
$FC27
PORT 0 THROUGH PORT 19
$ FCOO
$FBFF
ON-CHIP RAM (256 BYTES)
$FBOO
$FAFF
FUTURE RAM
AND
ROM EXPANSION

II

$1000
$OFFF
}
$0020
$001F
$0000

INTERRUPT
VECTORS

INSTRUCTION EXECUTION TIMES
Table 3

Instruction lYpe

Clock
Periods

Execution Time
with 6 MHz
clock (ILS)

Move Register-to-register

3

0.5

Add Register-to-register (binary or BCD)

3

0.5

Move Memory-to-register

6

1.0

Add Register-to-memory

9

1.5

Multiply (16 x 16)

21

3.5

Divide (32/16)

23

3.84

Move Multiple (save or restore
all registers)

55

9.2

V 1-73

ON·CHIP ROM
(4096 BYTES)

INSTRUCTION SET SUMMARY
Table 4

INST.

DESCRIPTION

ADD
ADD.B
AD DC
ADOC.B
AND
AND.B
ASL
ASL.B
ASR
ASR.B
BCHG
BCLR
BEXG
BSET
BTST
CALLA
CALLR
CLR
CLR.B
CMP
CMP.B
DADD
DADD.B
DADDC
DADDC.B
DI
DIVU
DJNZ

ADD
ADD BYTE
ADD WITH CARRY
ADD WITH CARRY BYTE
LOGICAL AND
LOGICAL AND BYTE
ARITHMETIC SHIFT LEFT
ARITHMETIC SHIFT LEFT BYTE
ARITHMETIC SHIFT RIGHT
ARITHMETIC SHIFT RIGHT BYTE
BIT CHANGE
BIT CLEAR
BIT EXCHANGE
BIT SET
BIT TEST
CALL ABSOLUTE
CALL RELATIVE
CLEAR
CLEAR BYTE
COMPARE
COMPARE BYTE
DECIMAL ADD
DECIMAL ADD BYTE
DECIMAL ADD WITH CARRY
DeCIMAL ADD WITH CARRY BYTE
DISABLE INTERRUPTS
DIVIDE UNSIGNED
DECREMENT COUNT AND JUMP
IF NON-ZERO
DJNZ.B
DECREMENT COUNT BYTE AND
JUMP IF NON-ZERO
DNEG
DECIMAL NEGATE
DNEG.B DECIMAL NEGATE BYTE
DECIMAL NEGATE WITH CARRY
DNEGC
DNEGC.B DECIMAL NEGATE WITH CARRY
BYTE
DSUB
DECIMAL SUBTRACT
DSUB.B
DECIMAL SUBRTRACT BYTE
DSUBC
DECIMAL SUBTRACT WITH CARRY
DSUBC.B DECIMAL SUBTRACT WITH CARRY
BYTE
EI
ENABLE INTERRUPTS
EOR
EXCLUSIVE OR
EOR.B
EXCLUSIVE OR BYTE
EXG
EXCHANGE
EXG.B
EXCHANGE BYTE
EXT
EXTEND SIGN

V1·74

INST.

DESCRIPTION

HALT
JMPA
JMPR
LlBA
LlWA
LSR
LSR.B
MOVE
MOVE.B
MOVEM
MOVEM.B
MULS
MULU
NEG
NEG.B
NEGC
NEGC.B
NOP
NOT
NOT.B
OR
OR.B
POP
POPM
PUSH
PUSHM
RET
RETI
ROL
ROL.B
ROLC
ROLC.B

HALT
JUMP ABSOLUTE
JUMP RELATIVE
LOAD INDEXED BYTE ADDRESS
LOAD INDEXED WORD ADDRESSED
LOGICAL SHIFT RIGHT
LOGICAL SHIFT RIGHT BYTE
MOVE
MOVE BYTE
MOVE MULTIPLE REGISTERS
MOVE MULTIPLE REGISTERS BYTE
MULTIPLY SIGNED
MULTIPLY UNSIGNED
NEGATE
NEGATE BYTE
NEGATE WITH CARRY
NEGATE WITH CARRY BYTE
NO OPERATION
ONE'S COMPLEMENT
ONE'S COMPLEMENT BYTE
LOGICAL OR
LOGICAL OR BYTE
POP
POP MULTIPLE REGISTERS
PUSH
PUSH MULTIPLE REGISTERS
RETURN FROM SUBROUTINE
RETURN FROM INTERRUPT
ROTATE LEFT
ROTATE LEFT BYTE
ROTATE LEFT THROUGH CARRY
ROTATE LEFT THROUGH CARRY
BYTE
ROTATE BYTE
ROTATE RIGHT BYTE
ROTATE RIGHT THROUGH CARRY
ROTATE RIGHT THROUGH CARRY
BYTE
SUBTRACT
SUBTRACT BYTE
SUBTRACT WITH CARRY
SUBTRACT WITH CARRY BYTE
TEST
TEST BYTE
TEST NOT
TEST NOT BYTE

ROR
ROR.B
RORC
RORC.B
SUB
SUB.B
SUBC
SUBC.B
TEST
TEST.B
TESTN
TESTN.B

INPUT/OUTPUT ARCHITECTURE
The 110 capabilities of the MK68200 are extensive, en·
compassing timers, a serial channel, parallel 110, and
an interrupt controller. All of these devices are acces·
sible to the programmer as ports within the top 1K bytes
of the address space, and the most commonly ac·
cessed ports may be accessed with the short port
addressing mode. A description of these ports Is given
in Table 5.

In total, 40 pins out of the 48 are used for 110, and the
functions they perform are highly programmable by the
user. In particular, many pins can perform multiple func·
tlons, and the programmer selects which ones are to
be used. For example, TAl may be used as an input for
Timer A, an Interrupt source, or a general purpose In·
put pin, and the interrupt source may be selected
simultaneously with either of the other functions.

PORT DESCRIPTIONS
Table 5

ADDRESS

READ/WRITE

BYTE·
ADDRESSABLE

0
1

$FCOO
$FC02

READIWRITE
READIWRITE

YES
YES

2
3

$FC04
$FC06

YES

4

$FC08

LOW BYTE: READIWRITE
HIGH BYTE: READ
INPUTS: READ ONLY
OUTPUTS: READIWRITE

5
6
7
8
9

$FCOA
$FCOC
$FCOE
$FC10
$FC12

NO
NO
NO

10

$FC14

NO

SERIAL I/O TRANSMIT CONTROL AND STATUS

11

$FC16

NO

TIMER B LATCH

12

$FC18

READIWRITE
READIWRITE
STATUS: READ ONLY
CONTROL: READIWRITE
STATUS: READ ONLY
CONTROL: READIWRITE
READ GETS COUNTER
WRITE GOES TO LATCH
READ GETS COUNTER
OR LATCH
WRITE GOES TO LATCH
READ GETS COUNTER
OR LATCH
WRITE GOES TO LATCH
READIWRITE
READIWRITE

16 EXTERNAL I/O PINS OR ADDRESS/DATA BUS
16 EXTERNAL 1/0 PINS (INCLUDING INTERRUPT,
SERIAL 1/0 PINS, AND BUS CONTROL)
(RESERVED)
SERIAL TRANSMIT (LOW BYTE) AND
RECEIVE (HIGH BYTE) BUFFER
8 EXTERNAL 1/0 PINS (TIMER CONTROL
AND PORT 0 HANDSHAKE CONTROL)
(RESERVED)
(RESERVED)
INTERRUPT LATCH REGISTER
INTERRUPT MASK REGISTER
SERIAL I/O RECEIVE CONTROL AND STATUS

NO

TIMER A, LOW LATCH

NO

TIMER A, HIGH LATCH

NO
NO

READIWRITE
READIWRITE
READIWRITE
READ GETS COUNTER
WRITE GOES TO LATCH
AND COUNTER

NO
NO
NO
NO

TIMER CONTROL, INTERRUPT EDGE SELECT
PORT 0 HANDSHAKE MODE BITS, FAST/
STANDARD, BUS LOCK, BUS SEGMENT BITS
PORT 0 DIRECTION CONTROL (DDRO)
PORT 1 DIRECTION CONTROL (DDR1)
SERIAL 1/0 MODE AND SYNC REGISTER
TIMER C LATCH

PORT

13

$FC1A

14
15

$FC1C
$FC1E

16
17
18
19

$FC20
$FC22
$FC24
$FC26

NO

VI·75

FUNCTION

•

TIMERS
The MK68200 includes three on-chip timers, each with
unique features. They are denoted Timer A, Timer B,
and Timer C. All three timers are a full 16 bits in width,
and count at the instruction clock rate of the MK68200
processor. Thus, this rate provides a resolution equal
to the instruction clock period (tc) of the MK68200. The
maximum count interval is equal to tc *2 16 . For a 6
MHz MK68200, a 167 nanosecond clock is provided with
a maximum count interval of 10.945 milliseconds. Each
timer has the capability to interrupt the processor when
it matches a predetermined value stored in an
associated latch.
Timer A is capable of operating in interval, event, and
two pulse/period modes. There is one 16-bit counter and
two 16-bit latches (high and low) associated with Timer
A. Once Timer A is initialized in the interval mode, the
counter is reset, and then it increments at the instruction clock rate until the value loaded into the high latch
is reached. The counter is then reset, and it increments
until the low latch value is reached, and the cycle is
repeated. In the event mode, the counter is incremented
for every active edge on TAl (programmable as positive
or negative) until the value in the high latch is reached,
at which time the counter is reset, and the cycle repeats.
In the pulse/period modes, the time that the pulse applied stays high and low is measured. The counter is
reset on the occurrence of any transition on TAl, and
it increments at the instruction clock rate until occurrence of the next transition. The value in the counter
at the end of the high level or low level time is loaded
into the appropriate latch. Interrupts may be generated
each time the counter reaches the high latch or low

latch value in the interval mode or when the counter
reaches the high latch in the event mode. An interrupt
is also generated whenever the counter overflows. See
the Pin Description section of this data sheet for TAl
and TAO functions in the various Timer A modes.
Timer B is capable of operating in interval and one-shot
modes. There is one 16-bit counter and one 16-bit latch
associated with Timer B. In the interval mode, the
counter is initially reset and incremented at the instruction clock rate until the value in the latch is reached.
The counter is then reset, and the cycle repeats. In the
one-shot modes, the counter begins incrementing in
response to an active transition (programmable as
positive or negative) on TBI. The counter is reset when
the value in the Timer B latch is reached. In the retriggerable one-shot mode, active transitions on TBI always
cause the counter to reset and begin incrementing. In
the non-retriggerable one-shot mode, active transitions
on TBI have no effect until the counter reaches the latch
value. Interrupts may be generated each time the
counter reaches the latch value. See the Pin Description section of this data sheet for TBI and TBO functions in the various Timer B modes.
Timer C has a 16-bit down counter and latch associated
with it and operates only in the interval mode. The output of Timer C toggles each time the counter value rolls
over from 0 to the latch value and may be used to internally supply the baud rate clock for the serial port.
An interrupt may also be generated each time the
counter rolls over to the latch value. Timer C may be
output on the TCLK pin (P1-3) depending on the mode
programmed.

TIMER MODES
Table 6

Timer

Modes

A
A
A

Interval
Event
Pulse Width and Period Measurement

B
B
B

Interval
Retriggerable One-shot
Non-retriggerable One-shot

C
C

Interval
Baud Rate Generation

VI-76

SERIAL CHANNEL

The serial channel on the MK68200, as shown in Figure
8, is a full-duplex USART with double buffering on both
transmit and receive. Word length, parity, stop bits, and

modes are fully programmable. The asynchronous
mode supports bit rates up to 375 Kbps, and the byte
synchronous mode operates up to 1.5 Mbps. Either
internal or external clocks may be used.

SERIAL CHANNEL
Figure 8

- -..
~

RECEIVE CONTROl&
STATUS REGISTER

RECEIVE SHIFT
REGISTER

-- ..P18
(8:15)

P18
(0:7)

MODE REGISTER

SYNC/ADDRESS REGISTER

-

..

--

-...

~

P9

---

SI

II

"
RECEIVE BUFFER

PH3

TRANSMIT BUFFER

PL3

p

- -...

..-

TRANSMIT SHIFT
REGISTER

-- p

INTERNAL DATA BUS

vl-n

"
TRANSMIT CONTROL &
STATUS REGISTER

P10

SO

In addition to the typical USART functions, the serial
channel can operate In a special wake-up mode with
a wake-up bit appended to each data word, as illustrated
In Figure 9. This wake-up bit is used to differentiate normal data words and special address words. The receiver
can be programmed to receive only address words or

only address words with a specific data value. In this
way, the processor can be interrupted only when it
receives its particular address and can then change
mode to receive the following data words. Wake-up
capability is especially useful when several MK6S200
microcomputers are Interconnected on one serial link.

SERIAL FRAME FORMAT
Figure 9

STARTt

PARITY
(OPTIONAL)

DATA

WAKE·UP
(OPTIONAL)

STOPt

MSB

LSB

tUSED IN ASYNCHRONOUS MODE ONLY

PARALLEL 110

mabie options on Port 4, provide the necessary control.

Two 16-bit ports, PO and P1, may be used for parallel
1/0. If individual bits are desired, each of the 32 bits may
be separately defined as input or output. Bits may be
grouped to provide the exact data widths desired. Port
o has the additional capability of operating under the
control of external handshaking signals. Eight- or
sixteen-bit sections of PO may be individually controlled
as input, output, or bidirectional 1/0. Two pairs of Ready
and Strobe signals, which are available as program-

INTERRUPT CONTROLLER
The MK6S200 interrupt controller provides rapid service
of up to 15 interrupt sources, each with a unique internal vector. The lowest 16 words of the address space
contain the starting addresses of the service routines
of each potential interrupt source and reset, as shown
in Figure 10.

INTERRUPT AND RESET VECTORS
Figure 10
VECTOR NUMBER

NAME

MNEMONIC

VECTOR LOCATION

0

RESET

RESET

0000

NON·MASKABLE INTERRUPT

NMI

0002

2

SPARE

SPARE

0004

3

EXTERNAL INTERRUPT 2

XI2

0006

4

STROBE LOW

STRL

0008

6

TIMER A OUTPUT

TAO

OOOA

6

TIMER A INPUT

TAl

OOOC

7

STROBE HIGH

STRH

OOOE

8

RECEIVE SPECIAL CONDITION

RSC

0010

9

RECEIVE NORMAL

RN

0012

A

EXTERNAL INTERRUPT 1

XI1

0014

B

TIMER B OUTPUT

TBO

0016

C

TIMER B INPUT

TBI

0018

D

EXTERNAL INTERRUPT 0

XIO

001A

E

TRANSMIT

XMT

001C

F

TIMER C

TC

001E

VI-78

LEVEL 2

LEVEL 1

complement of RAM, ROM, or 1/0, or when operation
in a parallel multiprocessing system is desired, the
MK68200 may be placed in an external bus mode. The
MODE pin is used to select the expansion capability
on reset. The MODE pin has three states, which select
fully expanded external bus, partially expanded external bus, or no expanded bus (single-chip configuration).
The MK68200 may also be reconfigured dynamically
through software. In an expansion mode, Port 0
becomes the 16-bit multiplexed, addressldata bus, and
eight bits from Port 1 become control signals which handle data transfer and bus arbitration. Sixteen lines are
still available for 1/0 functions, including eight lines from
Port 1 and all eight lines of Port 4.

Interrupt sources and RESET are prioritized in the order
shown in Figure 10, with RESET having the highest
priority. NMI is the only non-maskable interrupt. All of
the other sources share an interrupt enable bit in the
processor Status Register. This bit is automatically
cleared whenever an interrupt is acknowledged. Also,
each of these sources has a corresponding individual
mask bit. This feature allows selective masking of particular interrupts, including the ability to choose any
priority scheme desired with only minimal software
overhead. In fact, 15 levels of nested priority may be
programmed.
EXPANDED BUS OPERATION
When it is necessary to expand beyond the on-chip

MK68200 LOGICAL PINOUT EXPANDED BUS
Figure 11

14

o
o

14
13

16 I/O

MULTIPLEXED
ADDRESSI
DATA
BUS

16

13

0

12

0 12

11

I

11

10

0

10

9

I

9

8

0

8

7

1/0

7

UPC·

GP

lJ5S
l1i5i

L!
Hi
R/W

i5i

As
iG
SA

Ai
I1mF1
ICi'IO'C'f

6

6

XI2

6

6

XI1

4

4

XIO

3

3

SI

2

2

RCLK

1

1

TCLK

0

SO

0

MK68200

1/0

1/0

VCC
GND

I

0

16

I

0

14

TBO

RESET

I

I

13

TAl

ClKOUT 0

I

12

TBI

ClK1

I

11

RIG

ClK2

I

10

NMi

0

9

0

8

MODE

I

I

•

R/W

iGlCK
6TACK

DTACK

}

EXTERNAL
INTERRUPTS

}

SERIAL

}

TIMERS

CONTROL
BUS

PORT
1

TAO

VI·79

PORT
4

MK68200 EXPANDED BUS

As shown in Figure 11, two different control bus versions

Figure 12

are available: a Universal Peripheral Controller (UPC),
which generates 68000-compatible signals, and a
General Purpose (GP) bus, which can be used to interface to a wide variety of existing microprocessor buses.
With the selection of an expanded bus mode, the
MK68200 can act either as a general purpose CPU chip
(bus grant device) or as an intelligent peripheral 1/0 controller to a host CPU (bus request device). These two
system configurations are illustrated in Figures 13 and 14.

UPC

BR
BG

AS
DTACK
BGACK
RiW
UDS
LDS

GP
BUSOUT
BUSIN
AS
DTACK
DS
RiW

He
[8
P4·8
P4·9
P4·10
P4·11
MODE
CLK2
CLK1
CLKOUT
AD15
AD14
AD13
AD12
AD11
AD10
AD9
GND

48 Vee
47 P1·7
46 P1·6/X12
45 P1·5/X11
44 P1·4/X10
43 P1·3/SI
42 P1·2/RCLK
41 P1·lITCLK

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

40

P1·0/S0

39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

NMI
RESET
P4·12/TBI
P4·13/T AI
P4·14/TBO
P4·151T AO
ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8

With the GP bus option, the user may configure the
MK68200 in either of the two ways shown in Figures
13 and 14. As a host CPU (Figure 13), the MK68200 bus
arbitration logic causes the device to act as the system
bus grantor. In other words, the MK68200 would normally have control of the system bus and would grant
its use to DMA devices or peripheral CPUs. Alternately, the MK68200 may be configured as a peripheral CPU
(Figure 14) that must issue a request to the bus grant
device before being allowed to use the system bus. The
selection of one of these two configurations is
accomplished by the P4-11 pin at reset time. During
reset, P4-11 serves as the RIG input (0 = bus grantor,
1 = bus requestor). Following reset and at all times during program execution, P4-11 may be used as a general
purpose input pin.

HOST CPU HARDWARE CONFIGURATION
Figure 13

MK68200
BUS GRANT
CPU

SYSTEM BUS

OPTIONAL
ROM

PERIPHERAL
1/0
CONTROLLER

RAM
TIMERS
SERIAL 1/0
161/0
LINES

VI-80

PERIPHERAL I/O CONTROLLER CONFIGURATION
Figure 14

SYSTEM BUS

68000
OR
OTHER CPU

MK68200
1/0
CONTROLLER
OPTIONAL
ROM

OPTIONAL LOCAL BUS

RAM
TIMERS
SERIAL 1/0
161/0
LINES

With the GP bus operating in the host CPU configuration, the MK68200 may be used to interface with external memory and 1/0 devices in a manner that is
analogous to any general purpose microprocessor.
Additionally, the MK68200 retains its on-chip RAM and
1/0 resources, with on-chip ROM as an option, dependingon the expansion configuration selected. BUSIN and
BUSOUT are used to perform the bus arbitration handshake function, where BUSIN acts as the bus request
input and BUSOUT as the bus grant output.
In the full expansion configuration, anyon-chip ROM
which may exist on the device is disabled, and program
memory starting at location $0000 is located off-chip
and is addressed via the expanded bus, as shown in
Figure 15. In effect, the internal bus from locations
$OOOO-$FAFF is mapped onto the external bus. In the
partially expanded configuration (Figure 16), on-chip
ROM may be accessed on the internal bus. To gain
greater addressability in the partial expansion configuration, a scheme is implemented to allow access
of a full 64K-byte address space in four segments on
the expanded system bus through the 16K byte "window" on the internal bus. Basically, the most significant
two bits of address on the expanded bus are replaced

with two user-defined segment bits available to the programmer in an internal 1/0 control port location.
As a peripheral 1/0 controller, the MK68200 operates
as a bus requestor that gains mastership of the system
bus from the bus grant CPU. The GP bus version may
be selected to implement this system configuration in
cases where an interface to a general purpose CPU is
desired. In this case, the BUSIN and BUSOUT lines are
again used to perform the bus arbitration handshake
function, where BUSOUT now acts as bus request output, and BUSIN acts as bus grant input. In this configuration, the MK68200 can conceivably act as a
complete peripheral 1/0 control subsystem on a single
chip, with 16 lines of 1/0 and its on-Chip ROM, RAM,
timers, and serial 1/0 performing the necessary interface to the 1/0 device. The UPC bus version provides
the peripheral 1/0 control function with a direct interface to a 68000 bus grant Cpu. Note that the UPC bus
version can operate only as a bus request device. Once
the MK68200 has gained mastership of the system bus
via the 68000 bus arbitration handshake lines (BR, BG,
and BGACK), it may proceed to perform DMA transfers
and communicate with system memory or other 1/0
devices in the system.

VI-81

II

FULL EXPANSION BUS GRANTOR MEMORY MAP
Figure 15

EXTERNAL SYSTEM

INTERNAL

$FFFF

$FFFF , - . - - - - - - . . . ,

/ I

1/0

/
I

$ FCOO

!... .!..

RAM

$FBOO

/

/ / ;' I
/ I I / I
I
I
I
II I /
I / I
I / / I /
$COOO I
I / I / I

I

I

I

I

I

I

I

I

I

I

I

..! -.! -.!

I
I

-1. I

I

I

/

/ /

/

$COOO

I

I /
I I I
/ /
/ / /
/ / I

$8000

/

/ I

I

I

/

I /
I

/
/

I

I EXPANDED I
11;'1/1
/ I / II I
/ I I I
/ /
/ I I / /
/

/

I

/ /
I

$4000 I

$8000

I / /'
/ I /

1/ / /

I

$4000

/
I / /
1/
1 11 1
/ / I /
I

/

/

/

/ / I I
I I / / /

/
$0000

/

/

/

I

/

I

I

1-----VECTORS

I

$0000 " - - - - - - -......

VI·82

As in the case of the GP bus grant configuration, the
portion of the internal (or private) bus address space
that is mapped onto the expanded bus when the part
is operating as either a GP or a UPC bus request device
is determined by the expansion configuration selected.
In the partial expansion bus requestor case, the
resulting memory map is identical to that shown for the
GP grant configuration in Figure 16. During the time the
MK68200 is executing its program from ROM and accessing internal RAM and I/O resources, the expanded bus is held in a tri-state condition. The bus arbitration
logic within the MK68200 monitors each memory
reference to detect external bus addresses (referenced in segments via the 16K byte DMA window).
Whenever such an external reference occurs, the logic
automatically holds the processor in a wait state as it
proceeds to obtain mastership of the bus. As soon as
use of the system bus is obtained, the processor is
allowed to continue the reference. This procedure is
transparent to the programmer. In the case of successive external references, the expanded bus is retained until an internal reference is encountered.
Finally, if the on-chip resources are insufficient to perform the control task in the bus requestor configuration,
the internal bus address range (excluding on-chip RAM,
I/O) may be mapped onto an external local bus, which
is physically the same as the system bus but logically
separated with bus buffers. This is the full expansion
bus requestor configuration. The memory map for this
configuration is shown in Figure 17. The bus arbitration
sequence is still performed only when a reference to
the system bus through the DMA window is made. In
this manner, the I/O subsystem is isolated from the host
CPU.

When operating as a bus request device, it is possible
to retain the external bus for an indefinite period of time
using a bus lock feature. This will help facilitate the
transfer of large blocks of data. Thus, the on-chip bus
arbitration logic allows a maximum amount of concurrent processing in parallel, multiprocessing configurations with a minimum of hardware and software
overhead. The bus lock feature may be used by the
MK68200 in a bus grantor mode to keep any peripheral
from gaining mastership of the bus.
In any of the GP expanded bus modes, the MK68200
may respond to peripheral devices on the expanded
bus which generate an interrupt request on XIO. The
MK68200 will obtain the XIO interrupt vector number
from the requesting peripheral on the bus during an
interrupt acknowledge cycle. When responding to an
interrupt on XIO, the MK68200 will wait for the bus arbitration logic to gain control of the bus and then asserts
neither HB nor LB while asserting AS to signify that an
interrupt acknowledge cycle is in progress.
Timing diagrams and design parameters for the read,
write, and bus arbitration cycles are given in the AC
Electrical Specifications section for both the GP and
the UPC bus options. Bus timing for the interrupt
acknowledge cycle is given for the GP device in the AC
Electrical Specifications section. There is a userprogrammable speed selection associated with the read
and write cycles for both the UPC and GP mask option
parts. A bit in an internal I/O port allows the user to
select either the standard or the fast read/write cycle
on the expanded bus. The standard bus cycle is four
clock periods, while the fast bus cycle is three clock
periods.

VI·S3

•

PARTIAL EXPANSION MEMORY· MAP
Figure 16

INTERNAL
$FFFF , . . . . . - - - - - - - . . . ,

EXTERNAL SYSTEM
$FFFF , . . . . . - - - - - - - - ,

1/0
$FCOO 1 - - - - - - - - - - 1
RAM
$FBOO 1 - - - - - - - - - - 1

SEGMENT 3

$COOO ~-~-------:"--1

/

/

/

/ I

/

I

1

/

/

/

/

/ /1/.// /

/

EXPANDED
I
/
(DMA WINDOW)
/

/

1

/

'

/
/
$8000

$COOO ~---------1

/

/

/

/
1

/

SEGMENT 2

'

/ /
/

/

/

/ I
I /
/ / /

$8000

I----------i

SEGMENT 1

$4000

$4000

1-----------1

SEGMENTO

1------VECTORS

$0000 ' - - - - - - - - - -

$0000 - - - - - - - - -

VI·84

FULL EXPANSION BUS REQUESTOR MEMORY MAP
Figure 17

INTERNAL
$FFFF r - - - - - - ' " ' " t

EXTERNAL LOCAL
$ FFFF

,...-.....-~,.--,---,.....

EXTERNAL SYSTEM
$FFFF..--------.

I/O
$FCOO~---~

RAM
SEGMENT 3

$COOO ' - - - - - - - - I

SEGMENT 2

$80001--------1

SEGMENT 1

$40001------

$4000

SEGMENTO

$0000 ____
V_EC_T_OR_S_~

vI-as

$0000 ' - - - - - - - - - I

II

EXPANDED BUS SIGNALS (Common for GP and
UPC Options)
R/W
(Read/Write)
Output, active high and low. RIW determines whether
a read or a write is being performed during the current
bus cycle. It is stable for the entire bus operation. A high
signal denotes a read, and a low signal denotes a write.
DTACK
(Data Transfer Acknowledge)
Input, active low. When the addressed device has either
placed the requested read data on the bus or taken the
write data from the bus, DTACK should be brought low
to signify completion. The data portion of the bus cycle
will be extended indefinitely until this signal is asserted.
For systems using the GP bus, in which no devices
need wait states, DTACK may be strapped low.
AS
(Address Strobe)_
Output, active low. AS is used to ~nify that the address
is stable on the multiplexed bus. AS is high at the beginning of each bus cycle and goes low after the address
has stabilized. It then returns to the high state near the
end of the bus cycle.
UPC BUS SIGNALS
UDS
(Upper Data Strobe) .
Output, active low. U'E5"S is used to signify the data portion of the bus cycle 12r.!be upper byte of the data bus.
For read operations, UDS should be used by the external device to gate its most significant bytes onto the
multiplexed address/data bus. For writes, UD signifies
that the upper byte of the bus contains valid data to be
written from the processor.

LOS
(Lower Data Strobe)
Output, active low. ll5'§ is used to signify the data portion of the bus cycle for the lower byte of the data bus.
For read operations, Li5Sshould be used by the external device to gate its least significant byte onto the
multiplexed address/data bus. For writes, []5§' signifies
that the lower byte of the bus contains valid data to be
written from the processor.

iR
(Bus Request)
_
Output, active low, open drain. BR goes low when the
MK68200 requires the use of the external bus as a bus
master.

VI·S6

BG
(Bus Grant)
_
Input, active low. BG notifies the MK68200 that it has
been granted the external bus.
BGACK
(Bus Grant Acknowledge)
Output, active low, open drain. The MK68200 will assert
BGACK when it assumes mastership of the system bus.
GP BUS SIGNALS
P4·11 / R/G
(Request/Grant)
During reset, P4-11 serves as the R/G input (0 = bus
grantor, 1 = bus requestor). Following reset, and at all
times during program execution, P4-11 may be used as
a general purpose input pin.

OS
(Data Strobe)
_
Output, active low. DS is used to signify the data portion of the bus cycle. For read operations, DS should
be used by the external device to gate its contents onto
the multiplexed address/data bus. For writes, DS
signifies that valid data from the processor is on the bus.
HB
(High Byte)
Output, active low. HB signifies that the upper byte of
the data is to be read or written. It remains active for
the entire bus cycle.

Li
(Low Byte)
Output, active low. LB signifies that the lower byte of
the data bus is to be read or written. (Both HB and LB
active imply that an entire word is to be read or written). LB remains active for the entire bus cycle.
BUSIN
(Bus Input)
__
Input, active low. BUSIN provides one of two functions:
bus request or bus grant. When the MK68200 is the bus
grant device, its BUSIN signal is a bus request input
from a requesting device on the bus. When the
MK68200 is a bus request device, its BuSi'N signal is
a bus grant from the granting device on the bus.
BUSOUT
(Bus Output)
Output, acti~ BUSOUT provides the opposite
function of BUSIN. When BUSIN is a bus request
signal, BUSOUT is the corresponding bus grant, and
vice versa.

EMULATOR VERSION
referred to as the private bus. The private bus includes
a multiplexed address/data bus as well as bus control
signals. There are 22 pins associated with the private
bus. All of the 40 I/O port pins that exist on the 48-pin
versions are available to the user for configuration either
as general purpose or special I/O pins, or as expanded
bus pins.

The emulator versions of the MK68200 are available in
84-pin, leadless chip carrier packages. Figure 18
illustrates the logical pinout of the emulator version.
Table 1 summarizes the emulator parts described in this
data sheet. The emulator versions have no on-chip
ROM, but instead they include a second complete bus,

MK68E200 LOGICAL PINOUT
Figure 18
PORT 4

"
0

~

0

I~
:z: "'" :z:
II: II: > ~
c

I!! ~ ~ Ii;

~ ~ :=! ~

o 0 -

......

~

c

II)

II:

II:

~

al

00

-

0

0

-

-

-

0

1/0

16

110

14
13

16
14
13
12

12

11

11

10

10
PORTO
OR
EXTERNAL
ADDRESSI
DATA BUS

•

-

9

PRIVATE BUS
ADDRESSI
DATA

8

7

6

MK68E200
EMULATOR
VERSION

6
4
3
2
1
0

1/0
1/0

0
0
0

~

P'B'Hi
PBR/W

'PBDTACK

0

0

::::::

(.)
Q,
;:)

Q,

C!l

::::::

1919l~ lili I~ Ii I~

...
xx
N

:.: :.:
2

)(

I~ I~ I~ II! I~ I~ II Ii
Y
PORT 1

VI·87

iii

~ ~ ~

0

PBAS

0

Pii5'§

}

PRIVATE
BUS
CONTROL

MK68E200 PIN ASSIGNMENT (84-PIN LCC)
EMULATOR VERSION
Figure 19

~

c..

11

10

ii:

~ ~

0:

9

c:

5

~
Do.

4

't

"?

in

ii:

c..

a:

3

2

1

~

~

~

~

~

n

~

n n

12

~

74

NC

13

73

P4-12

P1-12

14

72

P4-13
PB-15

P1-13

15

71

P1-14

16

70

PB-14

P1-15

17

69

PB-'3

P8lB

18

68

PB-12

PBHB

19

67

PB-"
P8-'0

PBR/Vii

20

66

i>Bi5TACi<

21

65

PB-9

PBAS

22

64

PB-8

PBDS

23

63

PB-7

P4-8

24

62

PB-6

P4-9

25

61

PB-5

P4-10

26

60

PB-4

MK68E200

P4-11

27

59

PB-3

MODE

28

58

PB-2

ClK2

29

57

PB-'

ClK1

30

56

PB-O

CLKOUT

31

55

GND

NC

~

~

Vee

33

34

35

c

L()

z

Cl

36 37

~

t"')

38

N

39

40

~

~ ~ ~ ~ ~ ~

41

42

43

44

0')

co

I"

t.D

~ ~

45 46

L()

V

47

48

C"')

N

~ ~ ~ ~ ~ ~

VI-88

49

50 51

52 53

PRIVATE BUS OPERATION

which is exclusively reserved for in-circuit-emulator, or
AIM, use ($FEOO-$FFFF). The user should ensure that
no external devices reside in the in-circuit-emulator
area.

The address/data lines and control signals that constitute the private bus are functionally equivalent to the
internal signals used to access internal resources on
the 48-pin versions of the MK68200. Thus, the private
bus may be used to interface EPROM memory in
emulating mask ROM versions of the MK68200. Alternately, any combination of ROM, RAM, and I/O may
reside on the private bus.

The private bus interface is the same as that for the GP
expanded bus. All read/write transfers made exclusively
on the private bus are three clock periods, regardless
of the state of the Fast/Standard (F/S) bus timing selection bit. The user should ignore all activity on the private
bus while accesses are in progress on the expanded
bus. Care should also be taken that no external devices
reside on the private bus in the memory space intended
for expanded bus accesses. Note that there are three
pins shown on the pin diagram of Figure 19 which are
labeled "NC" and are not to be connected. They are
reserved for use in future versions of the emulator
device.

The address that is generated on the private bus is identical to that which is internally generated for 48-pin versions. When the part is used in a configuration that
supports system bus addressing through the DMA window, any references in this region of the memory map
produce an address on the private bus identical to that
specified by the programmer. In other words, the segment bits have no effect on the private bus address.
Write data appears on the private bus pins for all write
operations, regardless of whether the reference is onchip or off-chip. The MK68200 emulator version reads
data from the private bus, unless data is read from onchip RAM or I/O or from the external bus formed by the
Port 0 and Port 1 I/O pins.

CRYSTAL SELECTION
The wide frequency range of crystals that can be
chosen for the MK68200 offers the user a large degree
of flexibility. To aid in the selection of a suitable crystal,
the suggestions shown in Figure 20 should be considered by the user. The MK68200 offers an output pin
that will provide a system clock signal at one-half of the
crystal frequency.

The I/O port range of the memory map ($FCOO-$FFFF)
is actually subdivided into space which is exclusively
reserved for on-chip I/O ($FCOO-$FDFF) and space

CRYSTAL CONNECTION
Figure 20

X TAL

~~D~----<

AMPLIFIER
INPUT

AMPLIFIER
OUTPUT

GND

cl

= 10 pf typical
C2 = 20 pf typical

If it is desirable to "tune" the
oscillator to a precise frequency,
C 2 may be a variable capacitor.

c2 should be In the range of
Cl :s; C2 :s; 2 Cl •

For a high frequency operation
C'l '" 5 - 10 pf.

VI-89

•

SUMMARY OF CRYSTAL SPECIFICATIONS
Figure 21

SPECIFICATION

FREQUENCY RANGE

PARALLEL RESONANCE
FUNDAMENTAL MODE
CL 20 pf to 40 pf
AT CUT

1 MHz - 12.0 MHz

=

ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ....................................................... -25 0C to + 1000C
Storage Temperature .......................................................... - 65 0C to + 1500C
Voltage on Any Pin with Respect to Ground .......................................... -.3 V to + 7 V
Power Dissipation ....................................................................... 1.5 W
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This Is a stress rating only and functional operation
of the device at these or any other condition above those Indicated In the operation sections of this specification Is not Implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

MK68200 DC ELECTRICAL CHARACTERISTICS
(Vee .. 5.0 V : 5%, Ta = 0° to 70°C)
TEST
CONDITIONS

SYMBOL

PARAMETER

MIN

MAX

UNITS

V1L

Input low voltage; all inputs

-0.3

0.8

V

V 1H

Input high voltage; all inputs

2.0

Vee

V

VOL

Output low voltage; all outputs

0.4

V

IOL

VOH

Output high voltage; all outputs

V

IOH= - 25O It A

lee

Input power supply current

200

mA

III

Input leakage current

:10

itA

ILO

Tri-state output leakage current in
float

:10

itA

2.4

= 2.0

mA

= 0 to Vee
VOUT = 0.4 V to
V 1N

Vee

CAPACITANCE
TA = 25°C, f = 12 MHz with unmeasured pins returned to ground.
SYMBOL

PARAMETER

MAX

UNIT

TEST CONDITION

C1N

Input CapaCitance

10

pf

Tri-state Output Capacitance

10

pf

Unmeasured pins
returned to
ground

COUT

VI-90

MK68200 AC ELECTRICAL SPECIFICATIONS
4 MHz
NO.

DESCRIPTION

MIN

6MHz

MAX

MIN

MAX

UNITS

NOTES
1

1

RESET low time

20

20

state
times

2

ClK 1 width high (external
clock input)

45

30

ns

3

ClK 1 width low (external
clock input)

45

30

ns

4

ClK 1 period (external clock input)

125

1000

83

1000

ns

1.000

8.000

1.000

12.000

MHz

5

Crystal input frequency

6

Clock Period (PHI 1)

250

167

ns

7

PHI 1 low to PHI 1 high

125

83

ns

8

PHI 1 high to PHI 1 low

125

83

ns

9

PHI 1 low to ClKOUT low

40

27

ns

10

PHI 1 high to ClKOUT high

40

27

ns

•

MK68200 EXPANDED BUS AC ELECTRICAL SPECIFICATIONS
(UPC, GP, AND PRIVATE BUSES)
4MHz
NO.

DESCRIPTION

MIN

6MHz

MAX

MIN

MAX

UNITS

NOTES

11

PHI 1 low to RIW, HB, or lB
valid

115

76

ns

2

12

PHI 1 high to AS low

115

76

ns

2

76

ns

2

ns

2

ns

2

ns

2

13

PHI 1 low to address valid

14

AS low to address invalid

115

15

PHI 1 low to tristate address

16

Tristate address to OS, lOS, or
UOS starting low (fast cycle)

17

PHI 1 low to OS, lOS, or UOS
low (fast cycle)

165

110

ns

2

18

PHI 1 low to data out valid during
write

115

76

ns

2

19

PHI 1 low to RIW, HB, lB
invalid

0

0

ns

2

20

PHI 1 low to address/data bus
driven

0

0

ns

2

21

AS low to OS, lOS, or UOS
starting low (fast cycle)

ns

2

70

50
90

10

60
10

100

225

VI·91

70

150

MK68200 EXPANDED BUS AC ELECTRICAL SPECIFICATIONS
(UPC AND GP BUSES)
4 MHz
NO.

DESCRIPTION

22

Tristate address to OS, LOS, or
UOS starting low (standard cycle)

23

PHI 1 high to OS, LOS, or UOS
low (standard cycle)

6MHz

MAX

MIN
135

MIN

MAX

90

UNITS
ns

110

165

ns

2

ns

2

ns

2

24

Valid Oata Setup to PHI 1 low

25

AS low to OS, LOS, or UOS
starting low (standard cycle)

225

26

RIW, HB, or LB valid to AS
starting low

60

60

ns

27

Address valid to AS starting low

60

60

ns

28

Input data hold time from PHI 1
low

45

30

ns

29

Input data hold time from OS,
LOS or UOS high

0

0

ns

30

PHI 1 low to OS, LOS, or UOS
high

10

5
350

NOTES

150

230

120

180

ns

31

OTACK low setup to PHI 1 high

15

10

ns

32

LOS, UOS, or OS high to
OTACK high (hold time)

-30

-30

ns

33

LOS, UOS, or OS pulse width

240

150

ns

34

PHI 1 high to AS high

35

PHI 1 low to data out invalid

36

90

60

ns

0

0

ns

AS inactive

235

150

ns

37

OS, LOS, or UOS high to data
out invalid

180

110

ns

38

OS, LOS, or UOS high to AS
high

5

5

ns

MK68200 EXPANDED BUS AC ELECTRICAL SPECIFICATIONS (UPC BUS)
4 MHz
NO.

DESCRIPTION

6 MHz

MIN

MAX

MIN

MAX

UNITS

39

BGACK low to BR high

100

450

100

300

ns

40

BG low to BGACK low

50

600

50

400

ns

41

BGACK, AS, OTACK, inactive
to BGACK low; BG already low

0

600

0

400

ns

42

BGACK low to AS, UOS, LDS,
or address/data bus driven

40

135

40

90

ns

43

AS, LOS, UOS or address/data
bus tristate to BGACK high

0

180

0

120

ns

VI·92

NOTES

MK68211 EXPANDED BUS AC ELECTRICAL SPECIFICATIONS (GP BUS)
4 MHz
NO.

DESCRIPTION

MIN

6 MHz

MAX

MIN

MAX

100

175

UNITS

44

Tristate AS, OS, RIW, LB, HB
to BUSOUT low (bus grantor, fast
cycle, no wait states)

45

BUSIN low to BUSOUT low (bus
grantor, fast cycle, no wait states)

46

BUSOUT high to AS, RIW, LB,
HB driven (bus grantor)

15

47

BUSIN high to BUSOUT high
(bus grantor)

520

48

Tristate address/data bus to
BUSOUT low (bus grantor)

70

70

ns

49

BUSOUT high to address/data
bus driven (bus grantor)

50

50

ns

50

BUSOUT low to AS, OS, RIW,
LB, HB driven (bus requestor,
BUSIN low)

240

150

ns

51

BUSIN low to AS, DS, RIW,LB,
HB driven (bus requestor,
BUSOUT low)

270

52

Tristate AS, OS, RIW, LB, HB,
to BUSOUT high (bus requestor)

180

53

BUSOUT high to BUSIN high
(bus requestor)

54

BUSIN low to address/data bus
driven (bus requestor)

350

250

ns

55

Tristate address/data bus to
BUSOUT high (bus requestor)

100

65

ns

ns

1900

1200
15

900

650

NOTES

ns
ns

300

600

180

500

100

ns

•

ns

ns

530

400

ns

MK68E200 BUS AC ELECTRICAL SPECIFICATIONS (PRIVATE BUS)
4 MHz

NO.

DESCRIPTION

MIN

MAX

6 MHz
MIN

MAX

UNITS

56

Valid Data Setup to PHI 1 low

30

20

ns

57

PBRIW valid to PBAS starting
low

40

40

ns

58

Address valid to PBAS starting
low

35

35

ns

59

Input data hold time from PHI 1
low

0

0

ns

60

Input data hold time from PBDS
high

-25

-25

ns

VI-93

NOTES

MK68E200 EXPANDED BUS AC ELECTRICAL SPECIFICATIONS (PRIVATE BUS) (Cont.)
4 MHz
NO.

DESCRIPTION

61

PHI 1 low to PBDS high

62

PBDTACK low setup to PHI 1 high

63

6 MHz

MAX

MIN

MIN

MAX

130

105

UNITS
ns

20

15

ns

PBDS high to PBDTACK high
(hold time)

-15

-15

ns

64

PBDS pulse width

190

65

PHI 1 high to PBAS high

66

PHI 1 low to data out invalid

125

NOTES

ns

100

75

ns

10

10

ns

67

PBAS inactive

200

135

ns

68

PBDS high to data out invalid

200

135

ns

69

PBDS high to PBAS high

15

15

ns

MK68200 INPUT/OUTPUT AC ELECTRICAL CHARACTERISTICS
6 MHz

4 MHz
NO.
70

DESCRIPTION
Active and inactive For X12, X11,
pulse times
STRH, STRL,
TAl, TBI, NMI
For XIO

MIN

MAX

5

MIN

MAX

NOTES

1

3

state
times

71

Input data setup to falling edge of
STRH, STRL

50

35

ns

72

Input data hold from the falling
edge of STRH, STRL

60

40

ns

73

RDYH, RDYL low time

74

Delay from STRH, STRL high to
RDYH, RDYL low

75

Delay from data valid to RDYH,
RDYL high during output

76

Delay from STRH high to data out

n

Port 0 data hold time from STRH
low

78

Delay to Port 0 float from STRH
low

79

TCLK,RCLK period (asynchronous)
TCLK,RCLK period (synchronous)

80
81

3

1

5

UNITS

3

1

3

state
times

110

75

ns

3

3

state
times

85

ns

125
15

10
75

1

1

ns
50

ns

4.0
1.0

DC
DC

2.67
.667

DC
DC

p,s

TCLK, RCLK width low

4

DC

4

DC

state
times

1

TCLK, RCLK width high

4

DC

4

DC

state
times

1

VI-94

MK68200 INPUT/OUTPUT AC ELECTRICAL SPECIFICATIONS
4 MHz

6 MHz

NO.

DESCRIPTION

82

TCLK low to SO
TCLK as input
delay (sync mode)
TCLK as output

330

220

75

50

SI to RCLK high
setup time (sync
mode)

RCLK as input

30

20

RCLK as output

180

120

RCLK as input

45

30

RCLK as output

0

0

83

84

SI hold time from
RCLK high
(sync mode)

MAX

MIN

MIN

UNITS

MAX

NOTES

ns

ns

ns

NOTES
1. One state time is equal to one-half of the instruction clock (PHI 1) period.
2. For the private bus case, the signals referenced apply to the equivalent
private bus signals.

II

OUTPUT TEST LOAD
Figure 22

LOAD 2

LOAD 1

IN914

IN914

URX

.......-~'v" ,~---"

+2.5V

~o----4~--'--"""'--K

II
TCOM RING

TCOM RING

TEST LOAD 2 IS APPLICABLE TO THE
FOLLOWING PINS:
CLKOUT, PBUi , Piiiiii , PBRm, PeDs
P4-15, P4-14, P4-9, P4-8, AND PBAS .

TEST LOAD 1 IS APPLICABLE TO ALL PINS
EXCEPT THOSE LISTED UNDER TEST LOAD 2
AND TEST LOAD 3.

LOAD 3

2KIl (1%)

TEST LOAD 3 IS APPLICABLE TO THE
FOLLOWING PINS:
Pl-12 AND Pl-8.

VI-95

,

I----'''.''''_----.n

+2.5V

MK68200 AC TIMING
Figure 23

elK 1
(EXTERNAL CLOCK
SIGNAL)

RESET

_::l
__~'_____0_1~~{f-,r-_-_-_~_'~-------------------------

X12, X11, XIO,
TAl, TBI, NMI ,
STRl,STRH

MK68201 UPC BUS TIMING (FAST CYCLE)
Figure 24

SO

PH"

eLKour

S1

S3

S2

S4

S5

f I

~0 ~~~
:t~
I'\L

Riiii

,-----.I
I

AID (READ)

.I ':'@
II.

k-@

~

I

~~

~@~
I

_ _

AID (WRITE)

.===><

~'7~
-l

I

I

5F

2t~~---------------------®
~
---.l
..
®

@ _____________DA_~_O_U_T______________..
AD~RESS@4~~

~

=:J

I.f-----@I--..

VI-96

MK68201 UPC BUS TIMING (STANDARD CYCLE)
Figure 25

so

S2

S1

S3

S5

S4

S6

1-4----0----+1
PHI1

"'-KOUT

RiVi

I

AS

o

rn-~
===><=

®:L

®
r-®

f

~~r

',----..;Y

I

I

@~

I

~@

AID
(READ)

~@_~14----

@_I_-+I

------1®~
1~1@t=
AID
(WRITE)

ADDRESS

I~

DATA OUT

I-@~

I·

VI·97

S7

MK68201 UPC BUS ARBITRATION TIMING
Figure 26

CLKOUT

BR

BG

~

-r-®J

~lt---

~--------------~/

@
AS

VI-98

MK68211 GP BUS TIMING (FAST CYCLE)
Figure 27

so

S1

S3

S2

S5

S4

--®---.j

I___

PHI1

0-~

r-

®:!
~11-

elKOUT

I"

Y

I"

/.1

RM
LBHB

AS

I"

~"""--~-------'----'~k®
1

I [~

~®I

--,.L@ -€V

AID (READ)

ADDRESS

~~

1>--~4------.-----"I""

LJJ

-

~

I

II
@~~

®

OS

DTACK

AID (WRITE)

====><

1

-j

ADDRESS.

®t=

~~.- - - - - D A - J A - O U - T- - - - ' " " " " :

~I.- - @ - - - + 1

~H

VI-99

'--_ _

MK68211 GP BUS TIMING (STANDARD CYCLE)
Figure 28

so

S1

S3

S2

S4

S5

14---0---.!
PHI1

"

V

"

I

Y

_ _....J

I

AS

AID
(READ)

AID
(WRITE)

1--.1 @t=
ADDRESS

I~

DATA OUT

~@-.t

VI-100

S6

S7

MK68211 GP BUS ARBITRATION TIMING (BUS GRANTOR)
Figure 29

CLKOUT

r --

AS,OS,RIW
ili,Hii

I

I

-_JJ

@

I

't=@1@-

BUS IN

BUS OUT

AID

~

Ie
~@

MK68211 GP BUS ARBITRATION TIMING (BUS REQUESTOR)
Figure 30

CLKOUT

AS,OS,Rm
m,HB

----------1

1

...--@~.
BUSOUT

AID

------------®-=1~------------~~----------VI-101

II

MK68200 PRIVATE BUS TIMING (FAST CYCLE)
Figure 31

so

•

S3

S2

S1

S5

S4

®---~

r

I" f -1"k@
I

-.\

I

PBAS

@I

@~

®J t:

PB AID
(READ)

®
Piii5S
I

@

® ~
PBDTACK

PB AID
(WRITE)

::::::x

I

~I

ADDRESS

@C
~

~f=@

DATA OUT

I.

VI·102

@

.,

INPUT/OUTPUT AC TIMING
Figure 32

DATA INPUT:

STRH
STRL

t

@~..----

,-@

PO~O----------------~~~~----------~----~~
INPUT
,_
I\~_ _ _ _ __

RDYH

1'--------'1 ,..--------,

RDYL

~-~®i------!- II

INPUT/OUTPUT AC TIMING
Figure 33

DATA OUTPUT:

STRH
STRL

t+----@)----.

VI-103

INPUT/OUTPUT AC TIMING
Figure 34

BIDIRECTIONAL 1/0:

PORTO ------~

OUTPUT DATA

INPUT DATA

STAL

RDYL

RDYH

----------------------~/

8 ~-

®
STRH

VI-104

78

INPUT/OUTPUT AC TIMING
Figure 35

SERIAL I/O:

~------~------~
TCLK

so

®-r- __----------

------------~~L-~------~------~

RCLK

SI

VI-105

•

PART NUMBERING INFORMATION

basic device type, the amount of ROM and RAM, the
desired package type, temperature range, power supply
tolerance, and expandable bus interface type.

There are two types of part numbers for the 68200 family of devices. The generic part number describes the

Generic Part Number
An example of the generic part number is shown below:
M

K

6

8

2

0

I

4

4

N

o

6

Denotes maximum instruction clock
frequency.
4 = 4 MHz
6 = 6 MHz
Denotes operating temperature range
o = OOC - + 700C

Package Type

NOTES

1. Available for emulator only.
2. Must be "0" when specifying the emulator.

VI-106

P = Ceramic DIP
N = Plastic DIP
E = Leadless Chip Carrier 1

RAM Designator

4 = 256 Bytes

ROM Designator

0 = None 2
4 = 4K Bytes

Basic Device Type

68201 = UPC Bus
68211 = GP Bus
68E201 = Emulator with
UPC Bus
68E211 = Emulator with
GP Bus

Device Order Number
An example of the device order number is shown below:

M

K

4

1

5

2

N

-

0

6

Denotes maximum instruction clock frequency.
4 = 4 MHz
6 = 6 MHz
Denotes operating temperature range.
= OOC - + 70 0C

o

Package Type

P = Ceramic
N = Plastic
E = Leadless Chip Carrier 1

Customer/Code Specific Number (assigned by Mostek)
Basic Device Type 40 = Emulator Device
41 = UPC Expanded Bus Version,
o or 4K bytes ROM
42 = GP Expanded Bus Version,
o or 4K bytes ROM

NOTES
1. Available for emulator only.

VI-107

•

ORDERING INFORMATION
The device selection table shown below lists available versions of the 68200.
MAXIMUM CLOCK
FREQUENCY

TEMPERATURE
RANGE

Plastic 48·pin

6 MHz

0 0 to 700 C

MK41XXXN·06

Plastic 48·pin

6 MHz

0 0 to 700 C

MK68E201/04·06

MK40000E·06

Ceramic LCC

6 MHz

0 0 to 700C

M K68211 104·06

MK42000N·06

Plastic 48·pin

6 MHz

0 0 to 700 C

M K68211 144·06

MK42XXXN·06

Plastic 48·pin

6 MHz

0 0 to 70 0C

M K68E211/04·06

MK40010E·06

Ceramic LCC

6 MHz

0 0 to 700 C

M K68201 104·04

MK41000N·04

Plastic 48·pin

4 MHz

0 0 to 700 C

M K68201 144~04

MK41XXXN·04

Plastic 48·pin

4 MHz

0 0 to 700 C

M K68E201 104·04

MK40000E·04

Ceramic LCC

4 MHz

0 0 to 700 C

M K68211 104·04

MK42000N·04

Plastic 48·pin

4 MHz

0 0 to 70 0C

M K68211 144·04

MK42XXXN·04

Plastic 48·pin

4 MHz

0 0 to 70 0C

MK68E211/04·04

MK40010E·04

Ceramic LCC

4 MHz

0 0 to 70 0C

GENERIC
PART NO.

DEVICE
ORDER NO.

PACKAGE
TYPE

M K68201 104·06

MK41000N·06

M K68201 144·06

VI·108

II

VI-109

VI-110

m

UNITED
TECHNOLOGIES
MOSTEK

MICROCOMPUTER
COMPONENTS

PARALLEL INTERFACErrlMER (Plm
MK68230
FEATURES
MK68230
Figure 1

D 68000 Bus Compatible

o Port Modes Include:
Bit I/O
Unidirectional 8-bit and 16-bit
Bidirectional 8-bit and 16-bit

D Programmable Handshaking Options

o 24-bit

•

Programmable Timer Modes

D Five Separate Interrupt Vectors
D Separate Port and Timer Interrupt Service Requests
D Registers are Read/Write and Directly Addressable
D Registers are Addressed for MOVEP (Move
Peripheral) and DMAC Compatibility
GENERAL DESCRIPTION
The MK68230 Parallel Interface/Timer (PIIT) provides
versatile double-buffered parallel interfaces and an
operating system oriented timer to MK68000 systems.
The parallel interfaces operate in unidirectional or
bidirectional modes, either 8 or 16 bits wide. In the
unidirectional modes, an associated data direction
register determines whether the port pins are inputs or
outputs. In the bidirectional modes, the data direction
registers are ignored, and the direction is determined
dynamically by the state of four handshake pins. These
programmable handshake pins provide an interface flexible enough for connection to a wide variety of low,
medium, or high speed peripherals or other computer
systems. The PI/T ports allow use of vectored or autovectored interrupts, and also provide a DMA request pin for
connection to the Direct Memory Access Controller or
a similar circuit. The PI/T timer contains a 24-bit wide
counter and a 5-bit prescaler. The timer may be clocked
by the system clock (PI/T ClK pin) or by an external
clock (TIN pin), with the option of using a 5-bit prescaler.
It can generate periodic interrupts, a square wave, or a
single interrupt after a programmed timer period. Also,
it can be used for elapsed time measurement or as a
device watchdog.

PIN ASSIGNMENT
Figure 2

05
06
PAO
PA1
PA2 6
PA3
PA4
PA6
PA7
Vee

H1
H2
H3
H4
PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

The PI/T consists of two logically independent sections:
the ports and the timer. The port section consists of Port
VI-111

04
03
02
01
DO
R/VV
DTACK

cs

ClK
RESET
Vss _ _

PC7/TIACK
PC6/PiACK
PC5/PIRQ
PC4/DMAREQ
PC3/TOIJT
PC2/TIN
PC1
PCO
RS1
RS2
RS3
RS4
RS5

A (PAO-PA7), Port B (PBO-PB7), four handshake pins
(H1, H2, H3, and H4), two general 1/0 pins, and six dualfunction pins. The dual-function pins can individually
operate as a third port (Port C) or as an alternate function related to either Ports A and B, or the timer. The four
programmable handshake pins, depending on the mode,
can control data transfer to and from the ports, can be
used as interrupt generating inputs, or can be used as
1/0 pins. The timer consists of a 24-bit counter, optionally
clocked by a 5-bit prescaler. Three pins provide complete
timer 1/0: PC2/TIN, PC3/TOUT, and PC71
TIACK. Of course, only the ones needed for the given
configuration perform the timer function, while the others
remain Port ClIO.

LOGICAL PIN ASSIGNMENT
Figure 3

PAO-7
PBO-7

00-07

H1
H2
H3
H4

MKS8230
PIIT

~

PC7/TIACK*
PCS/PIACK*
PC 5 / I5'fi!m. *
PC4/0MAREQ*
PC3/TOUT*
PC2/TIN*
PC1

The system bus interface provides for asynchronous
transfer of data from the PItT to a bus master over the
data bus (00-07). Data transfer acknowledge (DTACK),
register selects (RS1-RS5), chip select, the read/write line
(RIW), and Port Interrupt Acknowledge (PlACK) or Timer
Interrupt Acknowledge (TIACK) control data transfer
between the PItT and the MK68000.

__________J-~PCO

"Individually Programmable Dual-Function Pin

MK68320 BLOCK DIAGRAM
Figure 4
38
VSS

39
40
RESET ClK

41

ES

42
43
OTACK R/W

44
00

45
01

46
02

47
03

48
04

1
05

2
06

3
07

•
Port
Interrupt!
DMA
Control
logic

Handshake
Controllers
and
Mode logic

PC7!

iiAa
37

PC61
PlACK
36

PC5!
PiRQ
35

PC4! PC3ITOUT PC21TIN
DMAREQ
33
32

34

VI-112

PCl
31

PCO
30

t

RSl
29

t

RS2
28

t

RS3
27

t

RS4
26

PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7

4
5
6
7
8
9
10
11

Hl
H2
H3
H4

13
14
15
16

PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7

17
18
19
20
21
22
23
24

t

RS5
25

PitT SYSTEM BLOCK DIAGRAM
~---------------------'\.

Figure 5

MK68000

1------4 PC5/PiRa
PC4!
DMAREO

MK68230
PI/T

PC'

pco

has been accepted at the data bus. Data
transfer acknowledge is compatible with
the MK68000 and with other Mostek bus
masters. A holding resistor is required to
maintain DTACK high between bus cycles.

PIN DESCRIPTION
Throughout this data sheet, signals are presented using
the terms active and inactive, or asserted and negated
independent of whether the signal is active in the highvoltage state or low-voltage state. (The active state of each
logic pin is given below.) Active low signals are denoted
by a superscript bar. RIW indicates a "write" is active low
and a "read" active high.
00-07
(Bidirectional Data
Bus)

The data bus pins 00-07 form an 8-bit
bidirectional data bus tolfrom the MK68000
or other bus master. These pins are active
high.

RS1-RS5
(Register
Selects)

RS1-RS5 are active high, high-impedance
inputs that determine which of the 25 possible registers is being addressed. They are
provided by the MK68000 or other bus
master.

RIW
(ReadIWrite
Input)

R/W is the high-impedance ReadIWrite
signal from the MK68000 or bus master,
indicating whether the current bus cycle is
a read (high cycle) or write (low cycle).

CS is a high-impedance input that selects
CS
(Chip Select the PItT registers for the current bus cycle.
Input)
Address strobe and the data strobe (upper
and lower) of the bus master, along with the
appropriate address bits, must be included
in the chip select equation. A low level corresponds to an asserted chip select.
DTACK
(Data
Transfer
Acknowledge
Output)

DTACK is an active low output that signals
the completion of the bus cycle. During
read or interrupt acknowledge cycles,
DTACK is asserted by the MK68230 after
data has been provided on the data bus;
during write cycles it is asserted after data

RESET
(Reset
Input)

RESET is a high-impedance input used to
initialize all PItT functions. All control and
data direction registers are cleared and
most internal operations are disabled by
the assertion of RESET (lOW).

ClK

The clock pin is a high-impedance, TTlcompatible signal with the same specifications as the MK68000. The PItT contains
dynamic logic throughout, and hence this
clock must not be gated off at any time.
It is not necessary that this clock maintain
any particular phase relationship with the
MK68000 clock. It may be connected to an
independent frequency source (faster or
slower) as long as all bus specifications
are met.

(Clock
Input)

PAO-PA7
and
PBO-PB7
(Port A and
Port B)

Ports A and Bare 8-bit ports that may be
concatenated to form a 16-bit port in certain modes. The ports may be controlled
in conjunction with the handshake pins
H1-H4. For stabilization during system
power-up, Ports A and B have internal pull
up resistors to Vcc. All port pins are active
high.

H1-H4
(Handshake
Pins Inputs
or Output)

Handshake pins H1-H4 are multi-purpose
pins that (depending on operational mode)
may provide an interlocked handshake, a
pulsed handshake, an interrupt input (independent of data transfers), or simple 1/0
pins. For stabilization during system power-

VI-113

a

up, H-2 and H4 have internal pullup
resistors to Vcc. Their sense (active high
or low) may be programmed in the Port
General Control Register bits 3-0. Independent of the mode, the instantaneous level
of the handshake pins can be read from
the Port Status Register.
PortC
(PCO-PC7/
Alternate
Function)

This port can be used as eight general
purpose I/O pins (PCO-PC7) or any combination of six special function pins and
two general purpose I/O pins (PCO-PC1).
(Each dual function pin can be standard
I/O or a special function independent of
the other Port C pins.) The dual function
pins are defined in the following paragraphs. When used as a Port C pin, these
pins are active high. They may be individually programmed as inputs or outputs
by the Port C Data Direction Register.

TIACK) are timer I/O pins. TIN may be
used as a rising-edge triggered external
clock input or an external run/halt control
pin (the timer is in the run state if run/halt
is high and in the halt state if run/halt is
low). TOUT may provide an active low
timer interrupt request output or a generalpurpose square-wave output, initially high.
TIACK is an active low high-impedance
input used for timer interrupt acknowledge.
Port A and B functions have an independent pair of active low interrupts request
(PIRQ) and interrupt acnkowledge (PlACK)
pins.
The DMAREQ (Direct Memory Access Request) pin provides an active low Direct
Memory Access Controller (DMAC) request pulse of three clock cylcles.

The alternate functions (TIN, TOUT,
MAXIMUM RATINGS

Symbol

Value

Unit

VCC

-0.3 to +7.0

V

Input Voltage

Vin

-0.3 to +7.0

Operating Temperature Range

TA

Characteristics
Supply Voltage

T stg

Storage Temperature
NOTE:
This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields; however, it is advised that normal precautions

VI-114

o to

70

-55 to +150

V
°C
°C

be taken to avoid application of any voltage higher than maximum-rated voltages
to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either VSS or Vee).

± 5%, TAO to 70°C, unless otherwise noted)

5.0 Vdc

DC ELECTRICAL CHARACTERISTICS (VCC

Symbol

Min

Max

Unit

All inputs

VIH

VSS +2.0

VCC

V

All inputs

VIL

VSS -0.3

VSS +0.8

V

to 5.25 YL_
H1, H3, RIW, RESET, CLK, RS1·RS5, CS

lin

-

10.0

/LA

-

ITSI

-0.1

20
-1.0

/LA
mA

VOH

VSS +2.4

-

V

VOL

-

0.5

V

PINT

-

750

mW

Cin

-

15

pF

Characteristics
Input High Voltage
Input Low Voltage
Input Leakage Current (Vin

=0

Hi·Z (Off State) Input Current (Vin

= 0.4 to

~

DTACK, PCO·PC7, 00·07
H2, H4, PAO·PA7, PBO·PB7
Output High
(ILOAD =
(ILOAD =
(ILOAD =

Voltage
-400/LA, VCC = min)
-150/LA, VCC = min)
-100/LA, VCC = min)

DTACK, 00·07
H2, H4, PBO·PB7, PAO·PA7
PCO·PC7

--

Output Low Voltage
(ILOAD = 8.8 mA, VCC = min)
PC3fTOUT, PC5/PIRQ
(ILOAD = 5.3 mA, VCC = min)
00·07, DTACK
(ILOAD = 2.4 mA, VC~ = min)
PAO·PA7, BO·PB7, H2, H4, PCO·PC2, PC4, PC6,PC7
Internal Power Dissipation (Measured at TA
Input Capacitance (Vin

= 0,

TA

=

25°C, f

AC ELECTRICAL SPECIFICATIONS -

= O°C)
= 1 MHz)

CLOCK TIMING

8 MHz
Characteristics

10 MHz

12.5 MHz

Symbol

Min

Max

Min

Max

Min

Max

Unit

f

2.0

8.0

2.0

10.0

4.0

12.0

MHz

Frequency of Operation

tCYC

125

500

100

500

80

250

ns

Clock Pulse Width

tCL
tCH

55
55

250
250

45
45

250
250

35
35

125
125

ns

Clock Rise and Fall Times

tCr
tCf

-

10
10

-

10
10

5
5

ns

Cycle Time

AC ELECTRICAL SPECIFICATIONS (Vee

-

-

= 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = O°C to 70 °C, unless otherwise noted)
8 MHz

Number

-

Characteristics

1

RIW, RS1·RS5 Valid to CS Low (Setup
Time)

2

CS Low to RIW and RS1·RS5 Invalid (Hold
Time)

10 MHz

12.5 MHz
Min

Max

Min

Max

Min

0

-

0

-

0

-

ns

100

-

65

-

ns

-

-

60

20

20

-

ns

-

55

ns

80

ns

3(1)

CS Low to CLK Low (Setup Time)

30

4(2)

Max

Unit

CS Low to Data Out Valid

-

75

-

65

5

RS1·RS5, RIW Valid to Data Out

-

140

-

100

6

CLK Low to DTACK Low (ReadIWrite Cycle)

0

70

0

60

0

55

ns

DTACK Low to CS High (Hold Time)

0

-

0

-

0

-

ns

8

CS or PlACK or TIACK High to Data Out
Invalid (Hold Time)

0

-

0

-

0

-

ns

9

CS or PlACK or TIACK High to 00·07
High Impedance

-

50

-

45

-

45

ns

7(3)

VI·115

AC ELECTRICAL SPECIFICATIONS (Continued)

10 MHz

8 MHz
Number
10
11

12.5 MHz

Min

Max

Min

Max

Min

Max

Unit

CS or PlACK or TIACK High to DTACK
High

-

50

-

45

-

40

ns

CS or PlACK or TIACK High to DTACK
High Impedance

-

100

-

55

-

45

ns

Characteristic

12

Data In Valid to CS low (Setup Time)

0

-

0

-

ns

CS low to Data In Invalid (Hold Time)

100

-

0

13

65

-

60

-

ns

14

Port Input Data Valid to H1(H3) Asserted
(Setup Time)

100

-

60

-

50

-

ns

H1(H3) Asserted to Port Input Data Invalid
(Hold Time)

20

-

20

-

20

-

ns

Handshake Input H1(H4) Pulse Width
Asserted

40

-

40

-

40

-

ns

Handshake Input H1(H4) Pulse Width
Negated

40

-

40

-

40

-

ns

H1(H3) Asserted to H2(H4) Negated
(Delay Time)

-

150

-

120

-

100

ns

ClK low to H2(H4) Asserted
(Delay Time)

-

100

-

100

-

80

ns

20(4)

H2(H4) Asserted to H1(H3) Asserted

0

-

0

0

-

ns

21(5)

ClK low to H2(H4) Pulse Negated
(Delay Time)

-

125

-

-

100

ns

15
16
17
18
19

22(9,10)
23
24
25(9,10)
26
27
28
29
30(7)
31

~

125

Synchronized H1(H3) to ClK low on which
DMAREQ is Asserted

2.5

3.5

2.5

3.5

2.5

3.5

ClK
Per.

ClK low on which DMAREQ is Asserted to
ClK low on which DMAREQ is Negated

2.5

3

2.5

3

2.5

3

ClK
Per.

ClK low to Port Output Data Valid (Delay
Time) (Modes 0 and 1)

-

150

-

120

-

100

ns

Synchronized H1(H3) to Port Output Data
Invalid (Modes 0 and 1)

1.5

2.5

1.5

2.5

1.5

2.5

ClK
Per.

H1 Negated to Port Output Data Valid
(Modes 2 and 3)

-

70

-

50

-

50

ns

H1 Asserted to Port Output Data High
Impedance (Modes 2 and 3)

0

70

0

70

0

70

ns

Read Data Valid to DTACK low
(Setup Time)

0

-

0

-

0

-

ns

ClK low to Data Output Valid, Interrupt
Acknowledge Cycle

-

120

-

100

-

80

ns

H1(H3) Asserted to ClK High (Setup Time)

50

-

40

-

40

-

ns

PlACK or TIACK low to 9lK low
(Setup Time)

50

-

40

-

30

-

ns

VI·116

AC ELECTRICAL SPECIFICATIONS (Continued)

8 MHz

12.5 MHz

Min

Max

Min

Max

Min

Max

Unit

3

3

3

3

3

3

ClK
Per.

Synchronized H1(H3) to ClK low on which
H2(H4) is Asserted

3.5

4.5

3.5

4.5

3.5

4.5

ClK
Per.

34

ClK low to DTACK low Interrupt
Acknowledge Cycle (Delay Time)

-

100

-

100

-

80

ns

35

ClK low to DMAREQ low (Delay Time)

0

120

0

100

0

80

ns

36

ClK low to DMAREQ High (Delay Time)

0

120

0

100

0

80

ns

2.5

3.5

2.5

3.5

2.5

3.5

ClK
Per.

Synchronized CS to ClK low on which
PIRQ is High Impedance

3

3

3

3

3

3

ClK
Per.

39

ClK low to PIRQ low or High Impedance

0

250

0

225

0

200

ns

40(8)

TIN Frequency (External Clock) - Prescaler
Used

0

1

0

1

0

1

fclk
(Hz) (6)
fclk
(Hz) (6)

Number
32(10)
33(9,10)

37(10)
38(10)

41
42

Characteristic
Synchronized CS to ClK low on which
DMAREQ is Asserted

Synchronized H1(H3) to ClK low on
which PIRQ is Asserted

TIN Frequency (External Clock) - Prescaler
Not Used

0

1/8

0

1/8

0

1/8

TIN Pulse Width High or low
(External Clock)

55

45

45

1

-

1

-

43

TIN Pulse Width low (Run/Halt Clock)

1

-

44

ClK low to TOUT High, low, or High
Impedance

0

250

0

225

0

200

ns

CS, PlACK, or TIACH High to CS, PlACK,
or TIACK low

50

-

30

-

30

-

ns

45

NOTES:
1.

10 MHz

ns
ClK
Per.

not be recognized until the next rising of the clock.

This specification only applies if the PlfT had completed all operations initiated by the previous bus cycle when CS was asserted. Following a normal read or write bus cycle, all operations are complete within three clocks
after the falling edge of the ClK pin on which DTACK was asserted. If CS
is asserted prior to completion of these operations, the new bus cycle, and
hence, DTACK is postponed.

8.

If these two signals are derived from different sources, they will have different instantaneous frequency variations. In this case the frequency applied to the TIN pin must be distinctly less than the frequency at the ClK
pin to avoid lost cycles of the TIN signal. With signals derived from different
crystal oscillators applied to the TIN and ClK pins with fast rise and fall
times, the TIN frequency can approach 80 to 90% of the frequency of the
ClK signal without a loss of a cycle of the TIN signal.

If all operations of the previous bus cycle were complete when CS was
asserted, this specification is made only to insure that DTACK is asserted
with respect to the falling edge of the ClK pin as shown in the timing
diagram, not to guarantee operation of the part. If the CS setup time is
Violated, DTACK may be asserted as shown, or may be asserted one clock
cycle later.
2. Assuming the RS1-RS5 to data valid time has also expired.
3.

This specification imposes a lower bound on CS low time, guaranteeing that
CS will be low for at least 1 ClK period.

4.

This specification assures recognition of the asserted edge of H1(H3).

5.

This specification applies only when a pulsed handshake option is chosen
and the pulse is not shortened due to an early asserted edge of H1(H3).

6.

ClK refers to the actual frequency of the ClK pin, not the maximum
allowable ClK frequency.

7. If the setup time on the rising edge of the clock is not met, H1(H3) may

This limit applies to the frequency of the signal at TIN compared to the frequency of the ClK signal during each clock cycle. If any period of the
waveform at TIN is smaller than the period of the ClK signal at that instant,
then it is likely that the timer circuit will completely ignore one cycle of the
TIN signal.

If these two signals are derived from the same frequency source then the
frequency of the signal applied to TIN can be 100% of the frequency at the
ClK pin. They may be generated by different buffers from the same signal
or one may be an inverted version of the other. The TIN signal may be
generated by and 'AND' function of the clock and a control signal.
9. The maximum value is caused by a peripheral access (H1 (H3) asserted)
and bus access (CS asserted) occurring at the same time.
10. Synchronized means that the input signal has been seen by the PlfT on
the appropriate edge of the clock (rising edge for H1(H3) and falling edge
for CS).

VI-117

•

CLOCK INPUT TIMING DIAGRAM
Figure 6

1+-------

READ CYCLE TIMING DIAGRAM
Figure 7

WRITE CYCLE TIMING DIAGRAM
Figure 8

NOTE:
Timing measurements are referenced to and from a low voltage of 0.8 volts and
a high voltage of 2.0 volts, unless otherwise noted.

VI·118

tcyc - - - - - - . l

lACK TIMING DIAGRAM
Figure 9

ClK-

PiACK
orTIACK_

00-07

NOTE:
Timing measurements are referenced to and from a low voltage of 0.8 volts and
a high voltage of 2.0 volts, unless otherwise needed.

PERIPHERAL INPUT TIMING DIAGRAM

•

Figure 10
ClK

PA(PB)0·7

H1(H3)

H21H4) IINTL) _

_______

H2(H4) -

---------------------------,.

+-_-J

(Pulsed) _

PERIPHERAL OUTPUT TIMING DIAGRAM
Figure 11

CLK
PA(PB)0-7- ----..",v----+--------------1f----H~,...-----__+--------_+----­
(MOO.1)---~~---+_----------~~---~I~------_+---------_r-----

PA(PB)0·7 -

(MO 2. 3)_
H2(H4) (Pulsed) _

H1(H3)

H2(H4) - - - - - - - - - - "
(INTL)_

NOTES:
1. Timing diagram shows H1, H2, H3, and H4 asserted low.
2. Timing measurements are referenced to and from a low voltage of 0.8 volts
and a high voltage of 2.0 volts, unless otherwise noted.

VI-119

MK68230 ORDERING INFORMATION

PART NO.
MK68230N-8
MK68230N-10

PACKAGE TYPE

MAX CLOCK FREQUENCY

48 Pin Plastic
DIP

8.0 MHz
10.0 MHz

VI-120

TEMP. RANGE
0° to 70 0

e

I!

UNITED

MICROCOMPUTER
COMPONENTS

TECHNOLOGIES
MOSTEK

MEMORY MANAGEMENT UNIT
MK68451
FEATURES

o Compatible with
o Provides virtual

MK68451

MK68000 and MK68008

Figure 1

memory support for the MK68010

o Provides efficient memory allocation
D Seperates address spaces of system and user
resources

•

D Provides write protection
D Supports paging and segmentation
D 32 segments of variable size with each MMU

o Multiple MMU capability to expand to any number of
segments

D Allows inter-task communication through shared
segments
D Quick context switching to cut operating system
overhead

A multitasking operating system is simplified, and reliability
is enhanced, through the use of the MMU.

D Simplifies programming model of address space

The MK68451 memory management unit (MMU) is the
basic element of a memory management mechanism
(MMM) in an MK68000 family system. The operating system is responsible for insuring the proper execution of user
tasks in the system environment, and memory management is basic to this responsibility. The MMM provides the
operating system with the capability to allocate, control,
and protect the system memory. A block diagram of a
single-MMU system is shown in Figure 3.

D Increases system reliability
D DMA-compatible
GENERAL DESCRIPTION

The MK68451 memory management unit (MMU) provides
address translation and protection for the 16 megabyte
addressing range of the MK68000 MPU. Each bus master
(or processor) in the MK68000 family provides a function
code and an address during each bus cycle. The function code specifies an address space, and the address
specifies a location within that address space. The function codes distinguish between user and supervisor
spaces and, within these, between data and program
spaces. This separation of address spaces provides the
basis for memory management and protection by the
operating system. Provision is also made for other bus
masters to have separate address spaces for logical DMA.

An MMM, implemented with one or more MK68451 MMUs,
can provide address translation, separation, and write protection for the system memory. The MMM can be programmed to cause an interrupt when a chosen section of
memory is accessed, and can directly translate a logical
address into a physical address, making it available to the
MPU for use by the operating system. Using these features, the MMM can provide separation and security for
user programs and allow the operating system to manage
the memory in an efficient fashion for multitasking.

VI-121

FUNCTIONAL DESCRIPTION

PIN ASSIGNMENT
Figure 2

MEMORY SEGMENTS

PADO
MAS
HAD
MODE
WIN
FAULT
IRQ
GND
FC3
FC2
FC1
FCO
AS
RESET
DTACK

ED
UDS
LDS
GO
ANY
ALL
lACK

cs

CLOCK

vee
R/Vi
RS1
RS2
RS3
RS4
RS5
A8

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

M
K
6
8
4
5

The MMM partitions the logical address space into contiguous pieces called segments. Each segment is a section of the logical address space of a task which is mapped
via the MMM into the physical address space. Each task
may have any number of segments. Segments may be
defined as user or supervisor, data-only or program-only,
or program and data. They may be accessed by only one
task or shared between two or more tasks. In addition, any
segment can be write protected to insure system integrity. A fault (MK68000 bus error) is generated by the MMM
if an undefined segment is accessed.

PAD1
PAD2
PAD3
PAD4
PAD5
PAD6
PAD7
PAD8

Vee
PAD9
PAD10
PAD11
PAD12
PAD13
PAD14
PAD15
A23
A22
A21
A20
A19
A18
A17
GND
A16
A15
A14
A13
A12
A11
A10
A9

FUNCTION CODES AND ADDRESS SPACES
Each bus master in the MK68000 family provides a function code during each bus cycle to indicate the address
space to be used for that cycle. The address bus then
specifies a location within this address space for the operation taking place during that bus cycle.
The function codes appear on the FCO-FC2 lines of the
MK68000 and divide the memory references into two
logical address spaces-the supervisor and the user
spaces. Each of these is further divided into program and
data spaces. A separate address space is also provided
for internal CPU-related activities, such as interrupt
acknowledge, giving a total of five defined function codes.
The address space of the MK68000 is shown in Figure 4.
ADDRESS SPACE OF MK68000
Figure 4

CPU

SIMPLIFIED BLOCK DIAGRAM OF SINGLE-MMU
SYSTEM

SUPERVISOR
Program
Data

Program

USER

Data

o

Figure 3

1

R/W

AS
FCO-FC2

A1-A23
MK680001
MK68010
MPU

Function
3~ Code
logical
Address"

.

- ~~~

R/W

L

Mapped
Address
Strobe

AS

R/W

FCO-FC2 MAS
Physical
Address

FFFFFF

--'"

MK68451
MMU

Al~

IPL

f-+-

t--- IRQ

BERR

i"-

t--- FAULT

Al-A7

FFFFFF

PA8-PA23 "'"
PA1-PA23/

/\

Memory
Array

In addition to the 3-bit function code provided by the
MK68000, the MK68451 MMU also allows a fourth bit (FC3)
which provides for the possibility of another bus master
in the system. In this case, FC3 would be a function of
bus grant acknowledge (BGACK) of the MK68000 to
enable a second set of eight function codes. This raises
the total number of possible function codes to 16. If there

VI-122

is only one bus master (the MPU), the FC3 pin on the MMU
should be tied low, and only eight address spaces can then
be used.

SCHEMATIC DIAGRAM OF DESCRIPTOR MAPPING
Figure 6
1 of 32
Descriptors

ADDRESS SPACE NUMBER

The AST is a set of MMU registers that defines which task's
segments are to be used in address translation for each
cycle type (supervisor program, supervisor data, etc.). The
AST contains an 8-bit entry for each possible function
code. Each entry is assigned an ASN (task number) and
this is used to select which descriptors may be used for
translation. The logical address is then translated by one
of these to produce the physical address. Figure 5 is a
typical memory map of a task's address space.
MEMORY MAP OF TYPICAL TASK ADDRESS SPACE
Figure 5
cPU

SUPERVISOR
Program
Data

FFFFFF

~

USER

Program

Data

Physical
Address

Logical
Address

Each task in a system has an address space comprised
of all the segments defined for that task. This address
space is assigned a number by programming all the
address space number (ASN) fields in its descriptors with
the same value. This value can be considered a task number. The currently active task's number is kept in the
appropriate entry(s) in the address space table (AST).

AST

1

Function
Code
FFFFF

TRANSLATION
During normal translation, the MMU translates the logical
address provided by the MK68000 to produce a physical
address which is then presented to the memory array. This
is accomplished by matching the logical address with the
information in the descriptors and then mapping it into the
physical address space. A block diagram of the MK68451
is shown in Figure. 7
Refer to Figure 3 for the following information. The logical
address is composed of address lines A1-A23. The upper
16 bits of this address (A8-A23) are translated by the MMU
and mapped into a physical address (PA8-PA23). The lower
seven bits of the logical address (A1-A7) bypass the MMU
and become the low-order physical address bits (PA1-PA7).
In addition, the data strobes (UDS and LDS) remain unmapped to become the physical data strobes for a total
of eight unmapped address lines.

FFFFFF

Task 01 Segment

FUNCTIONAL BLOCK DIAGRAM
Figure 7

DESCRIPTORS
Address translation is done using descriptors. A descriptor is a set of six registers (nine bytes) which describe a
memory segment and how that segment is to be mapped
to the physical addresses. Each descriptor contains base
addresses for the logical address masks. The size of the
segment is then defined by "don't cares" in the masks.
This method allows segment sizes from a minimum of 256
bytes to a maximum of 16 megabytes in binary increments
(Le., powers of two). This also forces both logical and
physical addresses of segment boundaries to lie on a segment size boundary. That is, a segment can only start on
an address which is a multiple of 2k. The segments can
be defined in such a way to allow them to be logically or
physically shared between tasks. Descriptor mapping is
shown schematically in Figure 6.

VI-123

Physical Address

•

ORDERING INFORMATION

Part Number

Package Type

Max Clock
Frequency

Temperature
Range

MK68451N-S
MK68451N-10

Plastic
Plastic

S.O MHz
10.0 MHz

0° to 70°C
0° to 70°C

VI-124

!t

UNITED
TECHNOLOGIES
MOSTEK

MICROCOMPUTER
COMPONENTS

SERIAL INPUT/OUTPUT CONTROLLER

MK68564

FEATURES
MK68564
Figure 1

o Compatible with MK68000 CPU
o Compatible with MK68000 Series DMA's
o Two independent, full-duplex channels
o Two independent baud rate generators
• Crystal oscillator input
• Single-phase TIL clock input

•

o Directly addressable registers (all control registers are
read/write)

o Data rate in synchronous or asynchronous modes
• 0-1 M bits/second with 5.0 MHz system clock rate

o Self-test capability
o Receive data registers

are quadruply buffered;
transmit data registers are doubly buffered

o Daisy-chain priority interrupt logic provides automatic
interrupt vectoring without external logic

o Modem status can

be monitored
• Separate modem controls for each channel

PIN DESCRIPTION
Figure 2

o Asynchronous features
•
•
•
•
•
•

01 1
03 2
05 3
07 4
INTR 5
elK 6
XTAl1 7
XTAl2 8
RESET 9
RxROYA 10
"i'XRDYA 11

5, 6, 7, or 8 bits/character
1, 1112, or 2 stop bits
Even, odd, or no parity
x1, x16, x32, and x64 clock modes
Break generation and detection
Parity, overrun, and framing error detection

o Byte synchronous features
•
•
•
•

Internal or external character synchronization
One or two sync characters in separate registers
Automatic sync character insertion
CRC-16 or CRC-CCITI block check generation and
checking

Vee 12
lEO 13
SYNCA 14
TxCA 15
RxCA 16
RxDA 17
TxOA 18
OTRA 19
RTSA 20
CTSA 21
OCOA 22
A223
A424

o Bit synchronous features
•
•
•
•
•
•
•

Abort sequence generation and detection
Automatic zero insertion and deletion
Automatic flag insertion between messages
Address field recognition
I-field residue handling
Valid receive messages protected from overrun
CRC-CCITI block check generation and checking
VI-125

MK68564
SIO

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

DO
02
04
06
R/W
lACK
OTACK

ES
RxROYB
TxROYB
GNO

iET
SYNCB
TxCB
RxCB
RxOB
TxOB

i5TRB
RTSB
CTSB
OCOB
A1
A3
A5

GENERAL DESCRIPTION

RESET
Device Reset

The MK68564 SIO is a dual-channel, Serial Input/Output Controller, designed to satisfy a wide variety of serial
data communications requirements in microcomputer
systems. Its basic function is a serial-to-parallel, parallelto-serial converter/controller; however, within that role, it
is systems software configurable so that it may be optimized for any given serial data communications
appl ication.
The MK68564 is capable of handling asynchronous protocols, synchronous byte-oriented protocols (such as IBM
Bisync), and synchronous bit-oriented protocols (such
as HDLC and IBM SDLC). This versatile device can also
be used to support virtually any serial protocol for
applications other than data communications (cassette
or floppy disk interface, for example).
The MK68564 can generate and check CRC codes in
any synchronous mode and may be programmed to
check data integrity in various modes. The device also
has facilities for modem controls in each channel. In
applications where these controls are not needed, the
modem controls may be used for general-purpose 110.

Input, active low. Reset disables both
receivers and transmitters, forces TxDA
and TxDB to a marking condition, forces
the modem controls high, and disables
all interrupts. With the exception of the
status registers, data registers, and the
vector register, all internal registers are
cleared. The vector register is reset to

"OFH".
INTR
Interrupt
Request

Output, active low, open drain. INTR is
asserted when the MK68564 SIO is
requesting an interrupt. INTR is
negated during an interrupt acknowledge cycle or by clearing the pending
interrupt(s) through software.

lACK
Interrupt
Acknowledge

Input, active low. lACK is used to signal
the MK68564 SIO that the CPU is
acknowledging an interrupt. CS and
lACK must not be asserted at the same
time. If interrupts are not used then
lACK should be pulled high.

iB

Input, active low. lEI is used to signal
the MK68564 SIO that no higher priority device is requesting interrupt service.

Interrupt
Enable In
SIO PIN DESCRIPTION
GND:

Ground.

Vee:

+5 volts (±5%).

CS:
Chip Select

Input active low. CS is used to select the
MK68564 SIO for access to the internal registers. CS and lACK must not be
asserted at the same time.

RIW:
Read/Write

Input. RIW is the signal from the bus
master, indicating whether the current
bus cycle is a read (high) or write (low)
cycle.

DTACK:
Data Transfer
Acknowledge

Output, active low, tri-stateable. DTACK
is used to signal the bus master that
data is ready or that data has been
accepted by the MK68564 SIO.

A1-A5:
Address Bus

Inputs. The address bus is used to
select one of the internal registers during a read or write cycle.

DO-D7:

Bidirectional, tri-stateable. The data bus
is used to transfer data to or from the
internal registers during a read or write
cycle. It is also used to pass a vector
during an interrupt acknowledge cycle.

Data Bus

CLK:
Clock

lEO
Interrupt
Enable Out

Output, active low. lEO is used to signal
lower priority peripherals that neither
the MK68564 SIO nor another higher
priority peripheral is requesting interrupt
service.

XTAL1
XTAL2
Baud Rate
Generator
Inputs

Inputs.A crystal may be connected between XTAL1 and XTAL2, or XTAL1 may
be driven with a TTL level clock. When
using a crystal, external capacitors must
be connected. When driving XTAL1 with
a TIL level clock, XTAL2 must be allowed to float.

RxR5YA
RxRDYB
Receiver
Ready

Outputs, active low. Programmable
DMA output for the receiver. The
RxRDY pins pulse low when a character is available in the receive buffer.

TxRDYA
TxRDYB
Transmitter
Ready

Outputs, active low. Programmable
DMA output for the transmitter. The
TxRDY pins pulse low when the transmit buffer is empty.

CTSA
CTSB
Clear to
Send

Inputs, active low. If Tx Auto Enables is
selected, these inputs enable the
transmitter of their respective channels.
If Tx Auto Enables is not selected, these
inputs may be used as general purpose
input pins. The inputs are Schmitttrigger buffered to allow slow rise-time
input signals.

Input. This input is used to provide the
internal timing for the MK68564 SIO.

VI-126

DCDA
DC DB
Data Carrier
Detect

Inputs, active low. If Rx Auto Enables
is selected, these inputs enable the
receiver of their respective channels. If
Rx Auto Enable is not selected, these
inputs may be used as general purpose
input pins. The inputs are Schmitt-trigger buffered to allow slow rise-time
input signals.

RxDA
RxDB
Receive Data

Inputs, active high. Serial data input to
the receiver.

TxDA
TxDB
Transmit
Data

Outputs, active high. Serial data output
of the transmitter.

RxCA
RxCB
Receiver
Clocks

Input/output. Programmable
receive clock input, or baud
generator output. The inputs
Schmitt-trigger buffered to allow
rise-time input signals.

TxCA
TxCB
Transmitter
Clocks

Input/output. Programmable pin, transmit clock input, or baud rate generator
output. The inputs are Schmitt-trigger
buffered to allow slow rise-time input
signals.

BTSA
RTSB
Request to
Send

Outputs, active low. These outputs
follow the inverted state programmed
into the RTS bit. When the RTS bit is
reset in the asynchronous mode, the
output will not change until the character in the transmitter is completely
shifted out. These pins may be used as
general purpose outputs.

DTRA
DTRB
Data
Terminal
Ready

Outputs, active low. These outputs
follow the inverted state programmed
into the DTR bit. These pins may also
be used as general purpose outputs.

SYNCA
SYNCB
Synchronization

Input/output, active low. The SYNC pin
is an output when Monosync, Bisync,
or SDLC mode is programmed. It is
asserted when a sync/flag character is
detected by the receiver. The SYNC pin
is a general purpose input in the Asynchronous mode and an input to the
receiver in the External Sync mode.

pin,
rate
are
slow

II

VI-127

MK68564 ELECTRICAL SPECIFICATIONS
ABSOWTE MAXIMUM RATINGS·
Temperature Under Bias ....................................................... -25°C to +100°C
Storage Temperature .......................................................... -65°C to +150°C
Voltage on Any Pin with Respect to Ground ........................................... -.3 V to + 7 V
Power Dissipation .................................. , .................................. 1.5 Watt
'Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Ex~osure to absolute maximum
rating conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS
(Vee = 5.0 V ± 5%, GND = 0 Vdc, TA = 0 to 70°C)
CHARACTERISTIC

SYM

MIN

MAX

UNIT

INPUT HIGH VOLTAGE

ALL INPUTS

VIH

GND + 2.0

Vee

V

INPUT LOW VOLTAGE

ALL INPUTS

V IL

GND -0.3

GND +0.8

V

POWER SUPPLY CURRENT
OUTPUTS OPEN

ILL

190

rnA

INPUT LEAKAGE CURRENT (VIN = 0 to 5.25)

liN

±10

p,A

THREE-STATE (OFF STATE) INPUT CURRENT
0< VIN < VeeDTACK, 00-07, SYNC, 'FxC, RXC,
INTR

ITSI

20
±10

p,A
p,A

OUTPUT HIGH VOLTAGE
(I LOA 0 = -400 p,A, Vee=MIN) DTACK, 00-07
(I LOAO= -150p,A, Vee=MIN) ALL OTHE~
OUTPUTS (EXCEPT XTAL2 & INTR)*
OUTPUT LOW VOLTAGE
(ILOAO=5.3 rnA, Vee=MIN) INTR, DrACK, 00-07
(ILOAO=2.4 rnA, Vee=MIN) ALL arHER
OUTPUTS (EXCEPT XTAL2)*

VOH

GND+2.4

V

0.5

VOL

V

*XTAL2 SPECIAL
INTR (OPEN DRAIN)
CAPACITANCE
TA=25°C, 1=1 MHz unmeasured pins returned to ground.

CHARACTERISTIC
Input Capacitance

CS, lACK
ALL arHERS

Tri-state Output Capacitance

VI-128

SYM

MAX

UNIT

C IN

15
10

p1
p1

COUT

10

p1

TEST
CONDITION
Unmeasured
pins
returned to
ground

AC ELECTRICAL CHARACTERISTICS
(VCC=5.0 Vdc±5%, GND=O Vdc, TA=O to 70 c C)

NUMBER PARAMETER

3.0 MHz
MIN
MAX

1

ClK Period

330

1000

4.0 MHz
MIN
MAX

5.0 MHz
MAX
MIN

250

200

1000

1000

UNITS NOTES
ns

2

ClK Width High

145

105

80

ns

3

ClK Width low

145

105

80

ns

4

ClK Fall Time

5

ClK Rise Time

6

CS low to ClK High (Setup Time)

0

0

7

A1-AS Valid to CS low (Setup Time)

0

0

0

ns

8

DATA Valid to CS low (Write Cycle)

0

0

0

ns

9

CS Width High

50

50

50

ns

DTACK low to A1-A5 Invalid
(Hold Time)

0

0

0

ns

11

DTACK low to DATA Invalid
(Write Cycle Hold Time)

0

0

0

ns

12

CS High to DTACK High (Delay)

13

ClK High to DTACK low

14

RIW Valid to CS low (Setup Time)

0

15

DTACK low to RIW Invalid
(Hold Time)

0

16

ClK low to DATA Out

17

CS High to DATA Out Invalid
(Hold Time)

10

30

30

30

30

30

ns

30

ns

0

ns

60

55

50

ns

325

320

295

ns

0

0

0
550
0

0

18

CS High to DTACK High Impedance

19

DTACK low to CS High

110

20

DATA Valid to DTACK low

70

21

lACK Width High

50

22

lACK low to ClK High
(Setup Time)

0

0

ns
ns

100

105

ns

0

ns

70

70

ns

50

50

ns

1

0

ns

1

410

410

410

ns

2

330

330

ns

2

23

ClK low to INTR Disabled

24

ClK low to DATA Out

25

DTACK low to lACK High

26

lACK High to DTACK High

60

55

50

ns

27

lACK High to DTACK High
Impedance

110

105

100

ns

28

lACK High to DATA Out Invalid
(Hold Time)

29

DATA Valid to DTACK low

30

ClK low to lEO low

330
0

0

•

ns
450

0

0

0

1

ns

0
450

1

ns

0

0

0

0

ns

195

195

195

ns

2

ns

3

220

VI-129

220

220

AC ELECTRICAL CHARACTERISTICS (Cont.)
(Vcc=5.0 Vdc±5%, GND=O Vdc, TA=O to 70°C)

NUMBER PARAMETER

3.0 MHz
MIN
MAX

4.0 MHz
MAX
MIN

5.0 MHz
MAX
MIN

UNITS NOTES

31

lEI low to lEO low

140

140

140

ns

3

32

lEI High to lEO High

190

190

190

ns

4

33

lACK High to lEO High

190

190

190

ns

4

34

lACK High to INTR low

200

ns

5

35

lEI low to ClK low (Setup Time)

36

lEI low to INTR Disabled

500

425

425

ns

6

37

lEI low to DATA Out Valid

225

225

225

ns

6

38

DATA Out Valid to DTACK low

ns

6

39

lACK High to DATA Out High
Impedance

40

CS High to DATA Out High
Impedance

41

CS or lACK High to ClK low

42

TxRDY or RxRDY Width low

3

43

ClK High to TxRDY or RxRDY low

44

ClK High to TxRDY or RxRDY High

200
10

200
10

10

55

55

ns

55
120

90

ns

90

ns

3

3

300

300

300

ns
ClK
Period
ns

335

300

300

ns

150

120

150
100

100

100

7
8,10

lACK High to CS low or CS High
to lACK low (not shown)

50

50

50

ns

45

CTS, DCD, SYNC Pulse Width High

200

200

200

ns

46

CTS, DCD, SYNC Pulse Width low

200

200

200

ns

47

TxC Period

1320

DC

1000

DC

800

DC

ns

48

TxC Width low

180

DC

180

DC

180

DC

ns

49

TxC Width High

180

DC

180

DC

180

DC

ns

50

TxC low to TxD Delay (X1 Mode)

51

TxC low to INTR low Delay

52

RxC Period

53

RxC Width low

54

RxC Width High

55

RxD to RxC High Setup Time
(X1 Mode)

0

56

RxC High to RxD Hold Time
(X1 Mode)

140

57

RxC High to INTR low Delay

10

13

10

13

10

13

ClK
Period

10

58

RxC High to SYNC low Delay
(Output Modes)

4

7

4

7

4

7

elK
Period

10

300

ns

9

5

300
9

5

9

1320

DC

1000

DC

800

DC

ClK
Period
ns

180

DC

180

DC

180

DC

ns

180

DC

180

DC

180

DC

ns

300
5

VI-130

0

9

10
9

ns

0

140

1

140

ns

AC ELECTRICAL CHARACTERISTICS (Cant.)
(Vcc=5.0 Vdc±5%, GND=O Vdc, TA=O to 70°C)

NUMBER PARAMETER

3.0 MHz
MIN
MAX

4.0 MHz
MIN
MAX

5.0 MHz
MIN
MAX

UNITS NOTES

1

1

1

ClK
Period

XTAL 1 Width High (TTL in)

145

100

80

ns

XTAL 1 Width Low (TTL in)

145

100

80

59

RESET low

60
61

10

ns

62

XTAL 1 Period (TTL in)

330

2000

250

2000

200

2000

63

XTAL 1 Period (Crystal in)

330

1000

250

1000

200

1000

ns
ns

NOTES:
1. This specification only applies if the SIO has completed all operations initiated by the previous bus cycle, when CS or lACK was asserted. Following a read, write, or interrupt acknowledge cycle, all operations are
complete within two ClK cycles after the rising edge of CS or lACK. If
CS or lACK is asserted prior to the completion of the internal operations,
the new bus cycle will be postponed.
2 .If iEi meets the setup time to the falling edge of ClK, 1112 cycles following
the clocking in of lACK.
3. No internal interrupt request pending at the start of an interrupt
acknowledge cycle.
4. Time starts when first signal goes invalid (high).
5. If an internal interrupt is pending at the end of the interrupt acknowledge

cycle.
6.lf Note 2 timing is not met.
7. If this spec is met, the delay listed in note 1 will be one ClK cycle instead
of two.
8. Ready Signals will be negated asynchronous to the ClK, if the condition
causing the assertion of the signals is cleared.
9. If RxC and TxC are asynchronous to the System Clock, the maximum clock
rate into RxC and TxC should be no more than one-fifth the System Clock
rate. If RxC and TxC are synchronized to the falling edge of the System
Clock, the maximum clock rate into Rxe and TxC can be one-fourth the
System Clock rate.
10. SIO Clock (ClK) Cycles as defined in Parameter 1.

OUTPUT TEST lOAD
Figure 3
+2.1 Vdc
for all outputs except

DTACi(, 00-07,

iNfR,
CL = 130 pf
RL = 16K n
R1 = 450 n
TEST
POINT

INTR TEST lOAD
Figure 4

for OTACK, 00-07
CL = 130 pf
RL = 6Kn
R1 = 200 n

+5 V dc

RL = 740 n

NOTE:
XTAl2 output test load is a cyrstal.

I
VI-131

CL = 130 pf

XTAL2

•

READ CYCLE
Figure 5

~----------~16~-------+4---+-~

00-07

OTACK---------------------------------------------------------------4------~

NOTE:
Waveform measurements for all inputs and outputs are specified at logic high
= 2.0 volts, logic low = 0.8 volts.

WRITE CYCLE
Figure 6

ClK

CS

R/W

A1-A5

00-07

------------------<

DTACK --------------------------------------------------------------------~

NOTE:
Waveform measurements for all inputs and outputs are specified at logic high
= 2.0 volts, logic low = 0.8 volts.

VI-132

INTERRUPT ACKNOWLEDGE CYCLE (lEI LOW)
Figure 7
ClK

wm ________________________________

~

00·07

OTACK--------------------------------~------------------~

~--------------------------------~--~---------------------+------~---

NOTE:
Waveform measurements for all inputs and outputs are specified at logic high
= 2.0 volts, logic low = 0.8 volts.

INTERRUPT ACKNOWLEDGE CYCLE (lEI HIGH)
Figure 8

ClK

lEI

------------------------------------11 ~--""""\

INTR - - - - - - - - - -..- - - - - - - - - - - - - - - - - f

r----f---"

00·07

OTACK--------------------------------~~--~r_------~--,

3'

NOTE:
Waveform measurements for all inputs and outputs are specified at logic high
= 2.0 volts, logic low = 0.8 volts.

VI-133

•

DMA INTERFACE TIMING
Figure 9

CLK
~

U

~::~~
~---------------~--------------~4Zr---------------------------------~

XTAL'

TTL IN

CRYSTAL IN

NOTE:
Waveform measurements for all inputs and outputs are specified at logic high
= 2.0 volts, logic low = 0.8 volts.

SERIAL INTERFACE TIMING
Figure 10

1=J9'-----TxD

SYNC

NOTE:
Waveform measurements for all inputs and outputs are specified at logic high
= 2.0 volts, logic low = 0.8 volts.

VI·134

MK68564 ORDERING INFORMATION

PART NO.

PACKAGE TYPE

MAX. CLOCK FREQUENCY

TEMPERATURE RANGE

MK68564N-03

Plastic

3.0 MHz

0° to 70°C

MK68564N-04

Plastic

4.0 MHz

0° to 70°C

MK68564N-05

Plastic

5.0 MHz

0° to 70°C

II

VI-135

VI-136

m

UNITED
TECHNOLOGIES
MOSTEK

MICROCOMPUTER
COMPONENTS
MK68901
MULTI-FUNCTION PERIPHERAL

FEATURES

MK68901

o

8 Input/Output Pins

Figure 1

• Individually programmable direction
• Individual interrupt source capability
- Programmable edge selection

o 16 Source

interrupt controller

II

• 8 Internal sources
• 8 External sources
• Individual source enable
• Individual source masking
• Programmable interrupt service modes
- Polling
- Vector generation
- Optional In-service status
• Daisy chaining capability

o

Four timers with individually programmable prescaling

DEVICE PINOUT
Figure 2

• Two multimode timers
- Delay mode
Pulse width measurement mode
Event counter mode
• Two delay mode timers
05
41

• Independent clock input

Sl

04
03
02

• Time out output option

o

MK68901
MFP

Single channel USART
• Full Duplex
• Asynchronous to 62.5 kbps

XTAl2
TAl

TBI

• Byte synchronous to 1 Mbps
• Internal/external baud rate generation

11

12

• DMA handshake signals
VI-137

01

DO

• Modem control

Da-Di

Data Bus (bi-directional, tri-stateable). The
data bus is used to receive data from or
transmit data to one of the internal registers
during a read or write cycle. It is also used to
pass a vector during an interrupt acknowledge cycle.

ClK:

Clock(input). This input is used to provide the
internal timing for the MK68901 MFP.

RESET:

Device reset. (input, active low). Reset
disables the USART receiver and transmitter,
stops all timers and forces the timer outputs
low, disables all interrupt channels and clears
any pending interrupts. The General Purpose
Interrupti 1/0 lines will be placed in the tristate input mode. All internal registers
(except the timer, USART data registers, and
transmit status register) will be cleared.

INTR:

Interrupt Request (output, active low, open
drain). INTR is asserted when the MK68901
MFP is requesting an interrupt. INTR is
negated during an interrupt acknowledge
cycle or by clearing the pending interrupt(s)
through software.

lACK:

Interrupt Acknowledge (input, active low).
lACK is used to signal the MK68901 MFP
that the CPU is acknowledging an interrupt.
CS and lACK must not be asserted at the
same time.

iEf:

Interrupt Enable In (input, active low). lET is
used to signal the MK68901 MFP that no
higher priority device is requesting interrupt
service.

lEO:

Interrupt Enable Out (output, active low). lEO
is used to signal lower priority peripherals
that neither the MK68901 MFP nor another
higher priority peripheral is requesting
interrupt service.

la-Ii

General Purpose Interrupt 1/0 lines. These
lines may be used as interrupt inputs andlor
1/0 lines. When used as interrupt inputs,
their active edge is programmable. A data
direction register is used to define which lines
are to be Hi-Z inputs and which lines are to be
push-pull TTL compatible outputs.

SO:

Serial Output. This is the output of the USART
transmitter.

SI:

Serial Input. This is the input to the USART
receiver.

RC:

Receiver Clock. This input controls the serial
bit rate of the USART receiver.

• loop back mode

o

68000 Bus compatible

o

48 Pin DIP

INTRODUCTION
The MK68901 MFP (Multi-Function Peripheral) is a
combination of many of the necessary peripheral functions
in a microprocessor system. Included are:
Eight parallel 1/0 lines
Interrupt controller for 16 sources
Four timers
Single channel full duplex USART
The use ofthe MFP in a system can significantly reduce chip
count, thereby reducing system cost. The MFP is completely
68000 bus compatible, and 24 directly addressable internal
registers provide the necessary control and status interface
to the programmer.
The MFP is a derivative of the MK3801 STI, a Z80 family
peripheral.

PIN DESCRIPTION
GND:
Vcc:

Ground
+5 volts (± 5%)

CS:

Chip Select (input, active low). CS is used to
select the MK68901 MFP for accesses to the
internal registers. CS and lACK must not be
asserted at the same time.

DS:

Data Strobe (input, active low). DS is used as
part of the chip select and interrupt
acknowledge functions.

R!W:

ReadIWrite (input). RIW is the signal from
the bus master indicating whether the
current bus cycle is a Read (High) or Write
(low) cycle.

DTACK:

Data Transfer Acknowledge. (output, active
low, tri-stateable). DTACK is used to signal
the bus master that data is ready, or that data
has been accepted by the MK68901 MFP.

A 1-A5:

Address Bus (inputs). The address bus is used
to address one of the internal registers during
a read or write cycle.
VI-138

TC:

Transmitter Clock. This input controls the
serial bit rate of the USART transmitter.
Receiver Ready. (output, active low) OMA
output for receiver, which reflects the status
of Buffer Full in port number 15.

RR:

REGISTER MAP
Figure 4
Address Abbreviation Register Name
Port No.

Transmitter Ready. (output, active low) OMA
output for transmitter, which reflects the
status of Buffer Empty in port number 16.

TR:

Timer Outputs. Each of the four timers has an
output which can produce a square wave.
The output will change states each timer
cycle; thus one full period of the timer out
signal is equal to two timer cycles. TAO or
TBO can be reset (logic "0") by a write to
TACR, or TBCR respectively.

TAO,TBO,
TCO, TOO:

XTAL1,
XTAL2:

GPIP
AER
DDR

GENERAL PURPOSE I/O
ACTIVE EDGE REGISTER
DATA DIRECTION REGISTER

3
4
5
6

IERA
IERB
IPRA
IPRB
ISRA
ISRB
IMRA
IMRB
VR

INTERRUPT ENABLE REGISTER A
INTERRUPT ENABLE REGISTER B
INTERRUPT PENDING REGISTER A
INTERRUPT PENDING REGISTER B
INTERRUPT IN-SERVICE REGISTER A
INTERRUPT IN-SERVICE REGISTER B
INTERRUPT MASK REGISTER A
INTERRUPT MASK REGISTER B
VECTOR REGISTER

7
8
9
A
B

10
11
12

TACR
TBCR
TCDCR
TADR
TBDR
TCDR
TDDR

13
14
15
16
17

SCR
UCR
RSR
TSR
UDR

C
D
E
F

Timer Clock inputs. A crystal can be connected between XTAL 1 and XTAL2, or XTAL 1 can
be driven with a TIL level clock. When driving
XT AL 1 with a TIL level clock, XTAL2 must be
allowed to float. When using a crystal,
external capacitors are required. See Figure
27. All chip accesses are independent of the
timer clock.

TAI,TBI:

0
1
2

Timer A,B inputs. Used when running the
timers in the event count or the pulse width
measurement mode. The interrupt channels
associated with 14and 13 are used for TAl and

TIMER A CONTROL REGISTER
TIMER B CONTROL REGISTER
TIMERS C AND D CONTROL REGISTER
TIMER A DATA REGISTER
TIMER B DATA REGISTER
TIMER C DATA REGISTER
TIMER D DATA REGISTER
SYNC CHARACTER REGISTER
USART CONTROL REGISTER
RECEIVER STATUS REGISTER
TRANSMITIER STATUS REGISTER
USART DATA REGISTER

TBI, respectively. Thus, when running a timer
in the pulse width measurement mode, 14.or
13 can be used for liD only.

MK68901 BLOCK DIAGRAM
Figure 3

DATA
(8)

ADDRESS
(5)

TIMERS

TCO

C8r.D

TDO
XTAL1

..
C
P

TIMERS
A8r.B

U

XTAL2
TAO
1.....
. . - - - TAl
TBO
TBI

cs

B

FiR

R/W

U

DS

S

SI
RC
SO
TC

DTACK

USART

1/0

fA
GENERAL PURPOSE
I/O-INTERRUPTS

VI-139

10-17

•

INTERRUPTS

IERA and IERB. Note: changing the edge bit, with the
interrupt enabled, may cause an interrupt on that channel.

The General Purpose I/O-Interrupt Port (GPIP) provides
eight 1/0 lines that may be operated either as inputs or
outputs under software control. In addition, each line may
generate an interrupt on either a positive going edge or a
negative going edge of the input signal.
The GPIP has three associated registers. One allows the
programmer to specify the Active Edge for each bit that will
trigger an interrupt. Another register specifies the Data
Direction (input or output) associated with each bit. The
third register is the actual data 1/0 register used to input or
output data to the port. These three registers are illustrated
in Figure 5.
The Active Edge Register (AER) allows each of the General
Purpose Interrupts to produce an interrupt on either a 1-0
transition or a 0-1 transition. Writing a zero to the
appropriate bit of the AER causes the associated input to
produce an interrupt on the 1-0 transition, while a 1 causes
the interrupt on the 0-1 transition. The edge bit is simply one
input to an exclusive-or gate, with the other input coming
from the input buffer and the output going to a 1-0 transition
detector. Thus, depending upon the state of the input,
writing the AER can cause an interrupt-producing
transition, which will cause an interrupt on the associated
channel, if that channel is enabled. One would then
normally configure the AER before enabling interrupts via

The Data Direction Register (DDR) is used to define 10-17 as
inputs or as outputs on a bit by bit basis. Writing a zero into a
bit of the DDR causes the corresponding Interrupt-I/O pin to
be a Hi-Z input. Writing a one into a bit of the DDR causes
the corresponding pin to be configured as a push-pull
output. When data is written into the GPIP, those pins
defined as inputs will remain in the Hi-Z state while those
pins defined as outputs will assume the state (high or low) of
their corresponding bit in the GPIP. When the GPIP is read,
the data read will come directly from the corresponding bit
of the GPIP register for all pins defined as output, while the
data read on all pins defined as inputs will come from the
input buffers.
Each individual function in the MK68901 is provided with a
unique interrupt vector that is presented to the system
during the interrupt acknowledge cycle. The interrupt vector
returned during the interrupt acknowledge cycle is shown
in Figure 6, while the vector register is shown in Figure 7.
There are 16 vector addresses generated internally by the
MK68901, one for each of the 16 interrupt channels.
The Interrupt Control Registers (Figure 8) provide control of
interrupt processing for all 1/0 facilities of the MK68901.
These registers allow the programmer to enable or disable

GENERAL PURPOSE 1/0 REGISTERS
Figure 5
ACTIVE

EDGE

REGIST.ER
1 =RISING
0= FALLING

PORT 1 (AER)

DATA DIRECTION REGISTER
PORT 2 (DDR)
~----~--~~--~~--~----~----~----~----~

1 =OUTPUT
0= INPUT

GENERAL PURPOSE 1/0 DATA REGISTER
PORT 0 (GPIP)

INTERRUPT VECTOR
Figure 6
IV,

~---------,----------~I~I__________~----__--~

I

IV3 - IV0

Vector bits 3-0 supplied by the

MFP based llpon the interrupting
channel.
4 most significant bits. Copied
from the vector register.

VI-140

any or all of the 16 interrupts, providing masking for any
interrupts, and provide access to the pending and in-service
status of the interrupts. Optional end-of-interrupt modes

are available under software control. All the interrupts are
prioritized as shown in Figure 9.

VECTOR REGISTER
Figure 7

Port B (VR)

!~
I

__

V_7__

~_V_6 ~
__

__
V_5__

~_V 4~ ~S~-L *__~___*__~__*__~
__

__

__

' - - - - - - - S = In-Service Register Enable

~

_____________________ Upper 4 bits of the Vector register.

* = Unused bits: read as zeros

Written into by the user.

INTERRUPT CONTROL REGISTERS
Figure 8

•

INTERRUPT ENABLE REGISTERS
ADDRESS

7

6

5

4

3

2

A
PORT 3

(IERA)

PORT 4

B
(IERB)

INTERRUPT PENDING REGISTERS

3
PORT 5

PORT 6

(IPRA)
B
(IPRB)

6
PORT 7

2

A

INTERRUPT IN-SERVICE REGISTERS
5
3
2

o

A

(ISRA)
~--~~--~----~~~~----~~~~----~--~

PORT 8

B

(ISRB)

7
PORT 9

6

INTERRUPT MASK REGISTERS
5
4
3
2

o

A
(IMRA)
~--~----~----~~~~----~~~~--~~--~

PORTA

B

(IMRB)

VI-141

that channel is acknowledged it will pass its vector, and the
corresponding bit in the Interrupt Pending Register (IPRA or
IPRB) will be cleared. IPRA and IPRB are readable; thus by
polling IPRA and IPRB, it can be determined whether a
channel has a pending interrupt. IPRA and IPRB are also
writeable and a pending interrupt can be cleared without
going through the acknowledge sequence by writing a zero
to the appropriate bit. This allows anyone bit to be cleared,
without altering any other bits, simply by writing all ones
except for the bit position to be cleared to IPRA or IPRB. Thus
a fully polled interrupt scheme is possible. Note: writing a
one to IPRA, IPRB has no effect on the interrupt pending
register.

INTERRUPT CONTROL REGISTER DEFINITIONS
Figure 9

Priority

Channel

HIGHEST

1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000

LOWEST

Description
General Purpose Interrupt 7(17)
General Purpose Interrupt 6(16)
Timer A
Receive Buffer Full
Receive Error
Transmit Buffer Empty
Transmit Error
Timer B
General Purpose Interrupt 5(15)
General Purpose Interrupt 4(14)
Timer C
Timer D
General Purpose Interrupt 3(13)
General Purpose Interrupt 2(12)
General Purpose Interrupt 1(11 )
General Purpose Interrupt 0(10)

Interrupts may be either polled or vectored. Each channel
may be individually enabled or disabled bywriting a one or a
zero in the appropriate bit of Interrupt Enable Registers
(IERA,IERB--see Figure 8 for all registers in this section).
When disabled, an interrupt channel is completely inactive.
Any internal or external action which would normally
produce an interrupt on that channel is ignored and any
pending interrupt on that channel will be cleared by
disabling that channel. Disabling an interrupt channel has
no effect on the corresponding bit in Interrupt In-Service
Registers (ISRA,ISRB); thus, if the In-service Registers are
used and an interrupt is in service on that channel when the
channel is disabled, it will remain in service until cleared in
the normal manner. IERA and IERB are also readable.
When an interrupt is received on an enabled channel, its
corresponding bit in the pending register will be set. When

A CONCEPTUAL CIRCUIT OF AN
CHANNEL

The interrupt mask registers (IMRA and IMRB) may be used
to block a channel from making an interrupt request.
Writing a zero into the corresponding bit of the mask
register will still allow the channel to receive an interrupt
and latch it into its pending bit (if that channel is enabled),
but will prevent that channel from making an interrupt
request. If that channel is causing an interrupt request at
the time the corresponding bit in the mask register is
cleared, the request will cease. If no other channel is
making a request, INTR will go inactive. If the mask bit is
re-enabled, any pending interrupt is now free to resume its
request unless blocked by a higher priority request for
service. IMRA and IMRB are also readable. A conceptual
circuit of an interrupt channel is shown in Figure 10.
There are two end-of-interrupt modes: the automatic endof-interrupt mode and the software end-of-interrupt mode.
The mode is selected by writing a one or a zero to the S bit of
the Vector Register(VR). If the S bit of the VR is a one, all
channels operate in the software end-of-interrupt mode. If
the S bit is a zero, all channels operate in the automatic
end-of-interrupt mode, and a reset is held on all in-service
bits. In the automatic end-of-interrupt mode, the pending bit
is cleared when that channel passes its vector. At that point,
no further history of that interrupt remains in the MK68901
MFP. In the software end-of-interrupt mode, the in-service

INTERRUPT

Figure 10
EDGE
REGISTER

ENABLE
REGISTER

S

INTERRUPT
IN-SERVICE

INTERRUPT
INTERRUPT
REQUEST

~----------------------~-------PASSVECTOR

VI-142

bit is set and the pending bit is cleared when the channel
passes its vector. With the in-service bit set, no lower
priority channel is allowed to request an interrupt or to pass
its vector during an acknowledge sequence; however, a
lower priority channel may still receive an interrupt and
latch it into the pending bit. A higher priority channel may
still request an interrupt and be acknowledged. The inservice bit of a particular channel may be cleared by writing
a zero to the corresponding bit in ISRA or ISRB. Typically,
this will be done at the conclusion of the interrupt routine
just before the return. Thus no lower priority channel will be
allowed to request service until the higher priority channel
is complete, while channels of still higher priority will be
allowed to request service. While the in-service bit is set, a
second interrupt on that channel may be received and
latched into the pending bit, though no service request will
be made in response to the second interrupt until the inservice bit is cleared. ISRA and ISRB may be read at any

time. Only a zero may be written into any bit of ISRA and
ISRB; thus the in-service bits may be cleared in software but
cannot be set in software. This allows anyone bit to be
cleared, without altering any other bits, simply by writing all
ones except for the bit position to be cleared to ISRA or ISRB,
as with IPRA and IPRB.
Each interrupt channel responds with a discrete 8-bit vector
when acknowledged. The upper four bits of the vector are
set by writing the upper four bits of the VR. The four low
order bits (Bit 3-Bit 0) are generated by the interrupting
channel.
To acknowledge an interrupt, lACK goes low, the lEI input
must go low (or be tied low) and the MK68901 MFP must
have an acknowledgeable interrupt pending. The Daisy
Chaining capability (Figure 11) requires that all parts in a
chain have a common lACK. When the common lACK goes

A CONCEPTUAL CIRCUIT OF THE MK68901 MFP
DAISY CHAINING
Figure 118

r

-----------------------,

MK68901 MFP

TIEI--~----------------------------------------------------~

iACK ------------4t---1

FREEZE
INTERRUPT CONTROL

L _____________________________

DAISY CHAINING
Figure 11b

HIGHEST
PRIORITY

LOWEST
PRIORITY

MK68901

r - - lEI

-=-iAC'K

MK68901

lEO

lEI

MK68901

lEO

i'AcK

lACK

1
-

1
VI-143

~------

lEI

JACK

I

~

•

The four timers are programmed via three Timer Control
Registers and four Timer Data Registers. Timers A and Bare
controlled by the control registers TACR and TBCR,
respectively (see Figure 12), and by the data registers TADR
and TBDR (Figure 13). Timers C and D are controlled by the
control register TCDCR (see Figure 14) and two data
registers TCDR and TDDR. Bits in the control registers allow
the selection of operational mode, prescale, and control,
while the data registers are used to read the timer or write
into the time constant register. Timer Aand B input pins, TAl
and TBI, are used for the event and pulse width modes for
timers A and B.

low, all parts freeze and prioritize interrupts in parallel. Then
priority is passed down the chain, via iEi and lEO, until a part
which has a pending interrupt is reached. The part with the
pending interrupt, passes a vector, does not propagate lEO,
and generates DTACK.
Figure 9 describes the 16 prioritized interrupt channels. As
shown, General Purpose Interrupt 7 has the highest
priority, while General Purpose Interrupt 0 is assigned the
lowest priority. Each of these channels may be reprioritized,
in effect, by selectively masking interrupts under software
control. The binary numbers under "channel" correspond to
the modified bits IV3, IV2, IV1 , and IVa, respectively, of the
Interrupt Vector for each channel (see Figure 6).

With the timer stopped, no counting can occur. The timer
contents will remain unaltered while the timer is stopped
(unless reloaded by writing the Timer Data Register), but
any residual count in the prescaler will be lost.

Each channel has an enable bit contained in IERA or IERB, a
pending latch contained in IPRA or IPRB, a mask bit
contained in IMRA or IMRB, and an in-service latch
contained in ISRA or ISRB. Additionally, the eight General
Purpose Interrupts each have an edge bit contained in the
Active Edge Register (AER), a bit to define the line as input or
output contained in the Data Direction Register (DDR) and
an 110 bit in the General Purpose Interrupt-110 Port (GPIP).

In the delay mode, the prescaler is always active. A count
pulse will be applied to the main timer unit each time the
prescribed number of timer clock cycles has elapsed. Thus,
if the prescaler is programmed to divide by ten, a count
pulse will be applied to the main counter every ten cycles of
the timer clock.

TIMERS

Each timea count pulse is appliedtothe main counter, itwill
decrement its contents. The main counter is initially loaded
by writing to the Timer Data Register. Each count pulse will
cause the current count to decrement. When the timer has
decremented down to "01 ", the next count pulse will not
cause it to decrement to "00". Instead, the next count pulse
will cause the timer to be reloaded from the Timer Data
Register. Additionally, a 'Time out" pulse will be produced.
This Time Out pulse is coupled to the timer interrupt
channel, and, ifthat channel is enabled, an interrupt will be
produced. The Time Out pulse is also coupled to the timer
output pin and will cause the pin to change states. The

There are four timers on the MK68901 MFP. Two of the
timers (Timer A and Timer B) are full function timers which
can perform the basic delay function and can also perform
event counting, pulse width measurement, and waveform
generation. The other two timers (Timer C and Timer D) are
delay timers only. One or both of these timers can be used to
supply the baud rate clocks for the USART. All timers are
prescaler/counter timers with a common independent
clock input (XTAL1, XTAL2). In addition, all timers have a
time-out output function that toggles each time the timer
times out.

TIMER A AND B CONTROL REGISTERS
Figure 12
Port C (TACR)

*

*

*

Port 0 (TBCR)

TIMER
A
RESET
TIMER

*

*

*

RESET

C3

0
0
0
0
0
0
0
0
1
1
1
1

* Unused bits: read as zeros

C2

0
0
0
0
1
1
1
1
0
0
0
0

C,

Co

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

B

AC 3

AC 2

AC,

AC o

BC 3

BC 2

BC,

BC o

Timer Stopped
Delay Mode, -:- 4 Prescale
Delay Mode, -:- 10 Prescale
Delay Mode, -:- 1 6 Prescale
Delay Mode, -:- 50 Prescale
Delay Mode, -:- 64 Prescale
Delay Mode, -:- 100 Prescale
Delay Mode, -:- 200 Prescale
Event Count Mode
Pulse Width Mode, 4 Prescale
Pulse Width Mode, 10 Prescale
Pulse Width Mode, 16 Prescale
Pulse Width Mode, 50 Prescale
Pulse Width Mode, 64 Prescale
Pulse Width Mode, 100 Prescale
Pulse Width Mode, 200 Prescale

VI-144

output will remain in this new state until the next Time Out
pulse occurs. Thus the output will complete one full cycle
for each two Time Out pulses.
If, for example, the prescaler were programmed to divide by
ten, and the Timer Data Register were loaded with 100
(deci ma I), the ma i n cou nter wou Id decrement once for every
ten cycles of the timer clock. A Time Out pulse will occur
(hence an interrupt if that channel is enabled) every 1000
cycles of the timer clock, and the timer output will complete
one full cycle every 2000 cycles of the timer clock.
The main counter is an a-bit binary down counter. It may be
read at any time by reading the Timer Data Register. The
information read is the information last clocked into the
timer read register when the OS pin had last gone high prior
to the current read cycle. When written, data is loaded into
the Timer Data Register, and the main counter, if the timer
is stopped. If the Timer Data Register is written while the
timer is running, the new word is not loaded into the timer
until it counts through H"01 ". However, if the timer is
written while it is counting through H"01 ", an indeterminate value will be written into the time constant register. This
may be circumvented by ensuring that the data register is
not written when the count is H"01 ".
If the main counter is loaded with "01 ", a Time Out Pulse
will occur every time the prescaler presents a countpulseto
the main counter. If loaded with "00", a Time Out pulse will
occur after every 256 count pulses.

Changing the prescale value with the timer running can
cause the first Time Out pulse to occur at an indeterminate
time, (no less than one nor more than 200 timer clock cycles
times the number in the time constant register), but
subsequent Time Out pulses will then occur at the correct
interval.
In addition to the delay mode described above, Timers A and
B can also function in the Pulse Width Measurement mode
or in the Event Count mode. In either ofthese two modes, an
auxiliary control Signal is required. The auxiliary control
input for Timer A is TAl, and for Timer B, TBI is used. The
interrupt channels associated with 14 and 13 are used for TAl
and TBI, respectively, in Pulse Width mode. See Figure 15.
The pulse width measurement mode functions much like
the delay mode. However, in this mode, the auxiliary control
signal on TAl orTBI acts as an enabletothetimer. When the
control signal on TAl or TBI is inactive, the timer will be
stopped. When it is active, the prescaler and main counter
are allowed to run. Thus the width of the active pulse on TAl
or TBI is determined by the number of timer counts which
occur while the pulse allows the timer to run. The active
state of the signal on TAl or TBI is dependent upon the
associated Interrupt Channel's edge bit (GPIP 4 for TAl and
GPIP 3 for TBI; see Active Edge Register in Figure 5.)lf the
edge bit associated with the TAl or TBI input is a one, it will
be active high; thus the timer will be allowed to run when
the input is at a high level. Ifthe edge bit is a zero, the TAl or
TBI input will be active low. As previously stated, the

TIMER DATA REGISTERS (A, B, C, AND D)
Figure 13

Port F (TADR)I...._D_7_L-_D_6_..L-_D_5_..L-_D_4_...L__D_3---'__
D_2__''___D_,--''---_D_o---'

port'O(TBDRI~I_D_7_L-_D_6_L__D_5~_D_4_...L__D_3~

__D_2__''___D_,--''---_D_o---'

1_D_7_L-_D_6_...L-_D_5~_D_4_...L-_D_3---'

__D_2--''---_D_,_L-_D_o---'

Port" (TCDR) ....

Port12~DDRII,---_D_7_L-_D_6_..L-_D_5~_D_4_...L-_D_3---,

__D_2__,,___D_'--,,---_D_o---,

TIMER C AND D CONTROL REGISTER
Figure 14

Port E (TCDCR)

CC,

*
C 2 C,

o

o
o
o

* Unused bits: read as zeros

Co

0

o

0

1

1

1
1
0

1

0

1
1

1
1

*

Timer Stopped
Delay Mode, -;- 4 Prescale
o Delay Mode, -;- 10 Prescale
1 Delay Mode, -;- 16 Prescale
o Delay Mode, -;- 50 Prescale
1 Delay Mode, -;- 64 Prescale
o Delay Mode, -;- 100 Prescale
1 Delay Mode, -;- 200 Prescale

VI-145

DC,

II

A CONCEPTUAL CIRCUIT OF THE MFP TIMERS IN
THE PULSE WIDTH MEASUREMENT MODE
Figure 15

TIMER A
PULSE WIDTH MODE

TIMER B
PULSE WIDTH MODE

interrupt channel (13 or 14) associated with the input still
functions when the timer is used in the pulse width
measurement mode. However, if the timer is programmed
for the pulse width measurement mode, the interrupt
caused by transitions on the associated TAl or TBI input wi II
occur on the opposite transition.
For example, ifthe edge bit associated with the TAl input
(AER-GPIP 4) is a one, an interrupt would normally be
generated on the 0-1 transition of the 14 input signal. If the
timer associated with this input (Timer A) is placed in the
pulse width measurement mode, the interrupt will occur on
the 1-0 transition of the TAl signal instead. Because the
edge bit (AER-GPIP 4) is a one, Timer A will be allowed to
count while the input is high. When the TAl input makes the
high to low transition, Timer A will stop, and it is at this point
that the interrupt will occur (assuming that the channel is
enabled). This allows the interrupt to signal the CPU that the
pulse being measured has terminated; thus Timer A may
now be read to determine the pulse width. (Again note that
13 and 14 may still be used for I/O when the timer is in the
pulse width measurement mode.) If Timer A is reprogrammed for another mode, interrupts will again occur
on the transition, as normally defined by the edge bit. Note
that, like changing the edge bit, placing the timer into or
taking it out of the pulse width mode can produce a
transition on the signal to the interrupt channel and may
cause an. interrupt. If measuring consecutive pulses, it is
obvious that one must read the contents of the timer and
then reinitialize the main counter by writing to the timer
data register. If the timer data register is written while the
pulse is going to the active state, the write operation may
result in an indeterminate value being written into the main
counter. If the timer is written after the pulse goes active,
the timer counts from the previous contents, and when it

counts through H"01 ", the correct value is written into the
timer. The pulse width then includes counts from before the
timer was reloaded.
In the event count mode, the prescaler is disabled. Each
time the control input on TAl or TBI makes an active
transition as defined by the associated Interrupt Channel's
edge bit, a count pulse will be generated, and the main
counter will decrement. In all other respects, the timer
functions as previously described. Altering the edge bit
while the timer is in the event count mode can produce a
count pulse. The interrupt channel associated with the
input (13 for TBI or 14 for TAl) is allowed to function normally.
To count transitions reliably, the input must remain in each
state (1/0) for a length of time equal to four periods of the
timer clock; thus signals of a frequency up to one fourth of
the timer clock can be counted.
The manner in which the timer output pins toggle states has
previously been described. All timer outputs will be forced
low by a device RESET. The output associated with Timers A
and B will toggle on each Time Out pulse regardless ofthe
mode the timers are programmed to. In addition, the outputs
from Timers A and B can be forced low at any time by
writing a "1" to the reset location in TACR and TBCR,
respectively. The output will be forced to the low state
during the WRITE operation, and at the conclusion of the
operation, the output will again be free to toggle each time a
Time Out pulse occurs. This feature will allow waveform
generation.
During reset, the Timer Data Registers and the main
counters are not reset. Also, if using the reset option on
Timers A or B, one must make sure to keep the other bits in
the correct state so as not to affect the operation of Ti mers A
and B.

VI-146

USART
Serial Communication is provided by a full-duplex doublebuffered USART, which is capable of either asynchronous
or synchronous operation. Variable word length and
start/stop bit configurations are available under software
control for asynchronous operation. For synchronous
operation, a Sync Word is provided to establish
synchronization during receive operations. The Sync Word
will also be repeatedly transmitted when no other data is
available for transmission. Moreover, the MK68901 allows
stripping of all Sync Words received in synchronous
operation. The handshake control lines RR (Receiver Ready)
and TR (Transmitter Ready) allow DMA operation. Separate

receive and transmit clocks are available, and separate
receive and transmit status and data bytes allow
independent operation of the transmit and receive sections.
The USART is provided with three Control/Status Registers
and a Data Register. The USART Data Register form is
illustrated in Figure 16. The programmer may specify
operational parameters for the USART via the Control
Register, as shown in Figure 17. Status of both the Receiver
and Transmitter sections is accessed by means of the two
Status Registers, as shown in Figures 18 and 19. Data
written to the Data Register is passed to the transmitter,
while reading the Data Register will access data received by
the USART.

USART DATA REGISTER
Figure 16

D,

Port 17 (UDR)

•

USART CONTROL REGISTER (UCR)
Figure 17
Port 14 (UCR)

*
-;.-16/-;.-1:

WLO-WL 1:

Unused bits; read as zero

When this bit is zero, data will be clocked
into and out ofthe receiver and transmitter
at the frequency of their respective clocks.
When this bit is loaded with a one, data
will be clocked into and out of the receiver
and transmitter at one sixteenth the
frequency of their respective clocks.
Additionally, when placed in the divide by
sixteen mode, the receiver data transition
resynchronization logic will be enabled.

ST1

o
o
t1
1

WLO

0
0

0

1
1

0

1

PARITY :

Word Length
8 bits
7 bits
6 bits
5 bits

Start/Stop bit control (format control).
These two bits set the format as follows:
VI-147

Parity Enabled. When set (H1 H), parity will
be checked by the receiver, parity will be
calculated, and a parity bit will be inserted
by the transmitter. When cleared ("OH), no
parity check will be made and no parity bit
will be inserted for transmission.
For a word length of 8 the MFP calculates
the parity and appends it when transmitting a sync character. For shorter lengths,
the parity must be stored in the Sync
Character Register (SCR) along With the
sync character.

E/O:
STO-ST1:

o

t NOTE+16 only

Word Length Control. These two bits set
the length of the data word (exclusive of
start bits, stop bits,and parity bits) as
follows:
WL1

STO Start Bits Stop Bits Format
SYNC
o
o
0
1
1
1
ASYNC
ASYNC
1
1%
1
1
2
ASYNC

Even-Odd. When set (,,1 H), even paritywill
be used if parity is enabled. When cleared
("0"), odd parity will be used if parity is
enabled.

Note that the synchronous or asynchronous format may be
selected independently of a-+-1 or -+- 16 clock. Thus it is
possible to clock data synchronously into the device but still
use start and stop bits. In this mode, all normal
asynchronous format features still apply. Data will be
shifted in after a start bit is encountered, and a stop bit will
be checked to determine proper framing. If a transmit
underrun condition occurs, the output will be placed in a
marking state, etc. It is conversely possible to clock data in
asynchronously using a synchronous format. There is data
tra nsition detection log ic bu iIt into the receive clock ci rcu itry

which will re-synchronize the internal shift clock on each
data transition so that, with sufficiently frequent data
transitions, start bits are not required. In this mode, all other
common synchronous features function normally. This resynchronization logic is only active in -+- 16 clock mode.
RECEIVER
The receiver section of the USART is configured by the UCR
as previously described. The status of the receiver can be
determined by reading and writing to the Receiver Status
Register (RSR). The RSR is configured as follows:

RECEIVER STATUS REGISTER (RSR)
Figure 18

Port 15 (RSR)

BF:

OE:

FOUND/SEARCH

MATCH/CHARACTER

OR BREAK DETECT

IN PROGRESS

Buffer Full. This bit is set when the
i ncom i ng word is tra nsferred to the receive
buffer. The bit is cleared when the receive
buffer is read by reading the UDR. This bit
of the RSR is read only.

FE:

F/S:

Found/Search. This combination control
bit and flag bit is only used with the
synchronous format. It can be set or
cleared by writing to this bit of the RSR.
When this bit is cleared, the receiver is
placed in the search mode. In this mode, a
bit by bit comparison of the incoming data
to the character in the Sync Character
Register (SCR) is made. The word length
counter is disabled. When a match is
found, this bit will be set automatically,
and the word length counter will start as
sync has now been achieved. An interrupt
will be generated on the receive error
channel when the match occurs. The word
just shifted in will, of necessity, be equal to
the sync character, and it will not be
transferred to the receive buffer.

B:

Break. This flag is used only when the
asynchronous format is selected. This flag
will be set when an all zero data word,
followed by no stop bit, is received. The flag
will stay set until both a non-zero bit is
received and the RSR has been read at
least once since the flag was set. Break
indication will not occur if the receive
buffer is full.

M/CIP:

Match/Character in Progress. If the
synchronous format is selected, th is flag is
the Match flag. It will be set each time the
word transferred to the receive buffer
matches the sync character. It wi II be reset
each time the word transferred to the
receive buffer does not match the sync

Overrun Error.This flag is set if the
incoming word is completely received and
due to be transferred to the receive buffer,
but the last word in the receive buffer has
not yet been read. When this condition
occu rs, the word in the receive buffer is not
overwritten by the new word. Note that the
status flags always reflect the status ofthe
data word currently in the receive buffer.
As such, the OE flag is not actually set until
the good word currently in the buffer has
been read. The interrupt associated with
this error will also not be generated until
the old word in the receive buffer has been
read.
OE flag is cleared by reading the receiver
status register, and new data words
cannot be shifted to the receive buffer until
this is done.

PE:

the FE flag is set or cleared when a word is
tra nsferred to the receive buffer.

Parity Error. This flag is set if the word
received has a parity error. The flag is set
when the received word is transferred
from the shift register to the receive buffer
if the error condition exists. The flag is
cleared when the next word which does
not have a parity error is transferred to the
receive buffer.
Frame Error. This flag only applies to the
asynchronous format. A frame error is
defined as a non-zero data word which is
not followed by a stop bit. Like the PE flag,
VI-148

character. If the asynchronous format is
selected, this flag represents Character in
Progress. It will be set upon a start bit
detect and cleared at the end of the word.
SS:

Sync Strip Enable. If this bit is set to a one,
data words that match the sync character
will not be loaded into the receive buffer,
and no buffer full signal will be generated.

RE: :

Receiver Enable. This control bit is used to
enable or disable the receiver. If a zero is
written to this bit of the RSR, the receiver
will turn off immediately. All flags
including the F/S bit will be cleared. If a
one is written to this bit, normal receiver
operation is enabled. The receive clock has
to be running before the receiver is enabled.

There are two interrupt channels associated with the
receiver. One channel is used for the normal Buffer Full
condition, while the other channel is used whenever an
error condition occurs. Only one interrupt is generated per
word received, but dedicating two channels allows separate
vectors: one for the normal condition, and one for an error
condition. If the error channel is disabled, an interrupt will
be generated via the Buffer Full Channel, whether the word
received is normal or in error. Those conditions which
produce an interrupt via the error channel are: Overrun,
Parity Error, Frame Error, Sync Found, and Break. If a
received word has an error associated with it, and the error
interrupt channel is enabled, an interrupt will occur on the
error channel only.
Each time a word is transferred into the receive buffer, a
corresponding set of flags is latched into the RSR. No flags
(except CIP) are allowed to change until the data word has
been read from the receive buffer. Reading the receive
buffer allows a new data word to be transferred to the
receive buffer when it is received. Thus one should first read
the RSR then read the receive buffer (UDR) to ensure that
the flags just read match the data word just read. If done in
the reverse order, it is possible that subsequent to reading
the data word from the receive buffer, but prior to reading
the RSR, a new word may be received and transferred to the
receive buffer and, with it, its associated flags latched into
the RSR. Thus, when the RSR is read, those flags may
actually correspond to a different data word. It is good
practice, also, to read the RSR prior to a data read as, when
an overrun error occurs, the receiver will not assemble new
characters until the RSR has been read.

As previously stated, when overrun occurs, the OE f.lag will
not be set and the associated interrupt will not be generated
until the receive buffer has been read. If a break occurs, and
the receive buffer has not yet been read, only the B flag will
be set(OE will not be set). Again, this flag will not be set until
the last valid word has been read from the receive buffer. If
the break condition ends and another whole data word is
received before the receive buffer is read, both the Band OE
flags will be set once the receive buffer is read.
If a break occurs while the OE flag is set, the B flag will also
be set.
A break generates an interrupt when the condition occurs
and again when the condition ends. If the break condition
ends before it is acknowledged by reading the RSR, the
receiver error interrupt indicating end of break will be
generated once the RSR is read.
Anytime the asynchronous format is selected, start bit
detection is enabled. New data is not shifted into the shift
register until a zero bit is detected. If a +16 clock is selected,
along with the the asynchronous format, false start bit
detection is also enabled. Any transition has to be stable for
3 positive going edges of the receive clock to be called a valid
transition. For a start bit to be good, a valid 0-1 transition
must not occur for 8 positive clock transitions after the initial
valid 1-0 transition.
After a good start bit has been detected, valid transitions in
the data are checked for continously. When a valid
transition is detected, the counter is forced to state zero, and
no more transition checking is started until state four. At
state eight, the "previous state" of the transition checking
logic is clocked into the receiver.
As a result of this resynchronization logic, it is possible to
run with asynchronous clocks without start and stop bits if
there are sufficient valid transitions in the data stream. This
logic also makes the unit more tolerant of clock skew for
normal asynchronous communications than a device
which employs only start bit synchronization.

VI-149

II

TRANSMITTER STATUS REGISTER (TSR)
Figure 19

Port 16 (TSR)

AUTO

END OF

TURNAROUND

TRANSMISSION

TRANSMITTER
The transmitter section of the USART is configured as to
format. word length, etc. by the UCR, as previously
described. The status of the transmitter can be determined
by reading or writing the Transmitter Status Register (TSR).
The TSR is configured as follows:
BE:

Buffer Empty. This status bit is set when
the word in the transmit buffer is
transferred to the output shift register and
thus the transmit buffer may be reloaded
with the next data word. The flag is cleared
when the transmit buffer is reloaded. The
transmit buffer is loaded by writing to the
UDR.

UE:

This bit is set when the last word has been
shifted out of the transmit shift register
before a new word has been loaded into
the transmit buffer. It is not necessary to
clear this bit before loading the UDR.
This bit may be cleared by either reading
the TSR or by disabling the transmitter.
After the setting of the UE bit. one full
transmitter clock cycle is required before
this bit can be cleared by a read. The timing
in some systems may allow a read of the
TSR before the required clock cycle has
been completed. This would result in the
UE bit not being cleared until the following
read. To avoid this problem, a dummy read
of the TSR should be performed at the end
of the UE service routine.

disabled, the transmitter will stop at the
next rising edge of the internal shift clock,
and END will immediately be set. The END
bit is cleared by re-enabling the transmitter.
B:

The BREAK bit cannot be set until the
transmitter has been enabled and the
transmitter has had sufficient time (one
clock cycle) to perform the internal reset
and initialization functions.
H,L:

Only one underrun error maybe generated
between loads of the UDR regardless of
the number of transmitter clock cycles
between UDR loads.
AT:

END:

Break. This control bit will cause a break to
be transmitted. When a "1" is written to
the B bit of the TSR, a break will be
transmitted upon completion of the
character (if any) currently being transmitted. A break will continue to be
transmitted until the B bit is cleared by
writing a "0" to this bit of the TSR. At that
time, normal transmission will resume.
The B bit has no function in the
synchronous format. Setting the "B" bit to
a one keeps the "BE" bit from being set to a
one. So, if there were a word in the buffer
at the start of break, it would remain there
until the end of break, at which time it
would be transmitted (if the transmitter is
still enabled). If the buffer were not full at
the start of break, it could be written at any
time during the break. If the buffer is empty
at the end of break, the underrun flag will
be set (unless the transmitter is disabled).

This bit causes the receiver to be enabled
at the end of the transmission of the last
word in the transmitter if the transmitter
has been disabled. The AT bit is cleared at
the end of the transmission.
End of transmission. When the transmitter
is turned off with a character still in the
output shift register, transmission will
continue until that character is shifted out.
Once it has cleared the output register, the
END bit will be set. If no character is being
transmitted when the transmitter is
VI-1S0

High and Low. These two control bits are
used to configure the transmitter output,
when the transmitter is disabled, as
follows:
H

L

Output State

o
o

o

Hi-Z
Low ("0")
High
Loop -Connects transmitter output to receiver
input, and TC to Receiver
Clock (RC and SI are not
used; they are bypassed
internally). In loop back
mode, transmitter output
goes high when disabled.

1
1

1

o
1

SYNC CHARACTER REGISTER
Figure 20

Port13(SCR)I~__D_7__~_D_6__~__D_6__~_D_4__~_D_3__~__D_2__~_D_1__~_D_O__~
Altering these two bits after Transmitter
Enable (XE) is set will alter the output state
until END is false. These bits should be set
prior to enabling the transmitter. The state
of these bits determine the state of the first
transmitted character after the transmitter
is enabled. If the high impedance mode
was selected prior to the transmitter being
enabled, the first bit transmitted is indeterminate.
XE:

Transmitter Enable. This control bit is used
to enable or disable the transmitter. When
set, the transmitter is enabled. When
cleared, the transmitter will be disabled. If
disabled, any word currently in the output
register will continue to be transmitted
until finished. If a break is being
transmitted when XE is cleared, the
transmitter will turn off at the end of the
break character boundary, and no end of
break stop bit is transmitted. The transmit
clock must be running before the transmitter is enabled. A "one" bit always
precedes the first word out of the
transmitter after the transmitter is enabled.
There is a delay between the time the
transmitter enable bit is written and when
the transmitter reset goes low; therefore,
the H & L bits should be written with the
desired state prior to enabling the transmitter.

Like the receiver section, there are two separate interrupt
channels associated with the transmitter. The buffer Empty
condition causes an interrupt via one channel, while the
Underrun and END conditions will cause an interrupt via
the second channel. When underrun occurs in the
synchronous format, the character in the SCR will be
transmitted until a new word is loaded into the transmit
buffer. In the asynchronous format. a "Mark" will be
continuously transmitted when underrun occurs.
The transmit buffer can be loaded prior to enabling the
transmitter. When the transmitter is disabled, any character
currently in the process of being transmitted will continue to
conclusion, but any character in the transmit buffer will not
be transmitted and will remain in the buffer. Thus no buffer
empty interrupt will occur nor will the BE flag be set. If the
buffer were already empty, the BE flag would be set and
would remain set. When the transmitter is disabled with a
character in the output register but with no character in the

transmit buffer, an Underrun Error will not occur when the
character in progress concludes.
Often it is necessary to send a break for some particular
period. To aid in timing a break transmission, a transmit
error interrupt will be generated at every normal character
boundary time during a break transmission. The status
register information is unaffected by this error condition
interrupt. It should be noted· that an underrun error, if
present, must be cleared from the TSR, and the interrrupt
pending register must be cleared of pending transmitter
errors at the beginning of the break transmission or no
interrupts will be generated at the character boundary time.
If the synchronous format is selected, the sync character
should be loaded into the Sync Character Register (SCR) as
shown in Figure 20. This character is compared to the
received serial data during a Search, and will be
continuously transmitted during an underrun condition.
All flags in the RSR or TSR will continue to function as
described whether their associated interrupt channel is
disabled or enabled. All interrupt channels are edge
triggered and, in many cases, it is the actual output of a flag
bit or flag bits which is coupled to the interrupt channel.
Thus, if a normal interrupt producing condition occurs while
the interrupt channel is disabled, no interrupt would be
produced even if the channel was subsequently enabled,
because a transition did not occur while the interrupt
channel was enabled. That particular flag bit would have to
occur a second time before another "edge" was produced,
causing an interrupt to be generated.
Error conditions in the USART are determined by
monitoring the Receive Status Register and the Transmitter
Status Register. These error conditions are only valid for
each word boundary and are not latched. When executing
block transfers of data, it is necessary to save any errors so
that they can be checked at the end of a block. In order to
save error conditions during data transfer, the MK68901
MFP interrupt controller may be used by enabling error
interrupts for the desired channel (Receive error orTransmit
error) and by masking these bits off. Once the transfer is
complete, the Interrupt Pending Register can be polled,to
determine the presence of a pending error interrupt, and
therefore an error.
Unused bits in the sync character register are zeroed out;
therefore, word length should be set up prior to writing the
sync word in some cases. Sync word length is the word
length plus one when parity is enabled. The user has to
determine the parity of the sync word when the word length

VI-151

•

is not 8 bits. The MK68901 MFP does not add a parity bit to
the sync word if the word length is less than 8 bits. The extra
bit in the sync word is transmitted as the parity bit. With a
word length of eight, and parity selected, the parity bit for
the sync word is computed and added on by the MK68901
MFP.

RR

RECEIVER READY

RR is asserted when the Buffer Full bit is set in the RSR
unless a parity error or frame error is detected by the
receiver.

TR

TRANSMITTER READY

TR is asserted when the Buffer Empty bit is set in the TSR
unless a break is currently being transmitted.

asserted, and R/W must be high. The internal read control
signal is essentially the combination of CS, OS, and
RD/WR. Thus, the read operation will begin when CS and
OS go active and will end when either CS or OS goes
inactive. The address bus must be stable prior to the start of
the operation and must remain stable until the end of the
operation. Unless a read operation or interrupt acknowledge cycle is in progress the data bus (0 0 -0 7 ) will
remain in the tri-state condition.
To write a register, CS and OS must be asserted and R/W
must be low. The address must be stable priortothe start of
the operation and must remain stable until the end of the
operation. After the MK68901 asserts DTACK, the CPU
negates OS. At this time, the MFP latches the data bus and
writes the contents into the appropriate register. Also,
when OS is negated, the MFP rescinds DTACK.
For an interrupt acknowledge, the operation starts when
lACK goes low, and ends when lACK goes high. The data
bus is tri-stated when either lACK or OS goes high.

REGISTER ACCESSES
All register accesses are dependent on ClK as shown in the
timing diagrams. To read a register, CS and OS must be

MK68901 ELECTRICAL SPECIFICATIONS - PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias .................................................................. -25°C to +1 OO°C
Storage Temperature ..................................................................... -65°C to +150°C
Voltage on Any Pin with Respect to Ground .................................................... - 0.3 V to +7 V
Power Dissipation .................................................................................. 1.5 W
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation 01
the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

D. C. CHARACTERISTICS
TA = O°C to 70°C; Vee = +5 V ± 5% unless otherwise specified.
TEST
CONDITION

MIN

MAX

UNIT

Input High Voltage

2.0

Vee +.3

V

V 1L

Input low Voltage

-0.3

0.8

V

V OH

Output High Voltage (except DTACK)

VOL

Output low Voltage (except DTACK)

0.5

V

IOL = 2.0 mA

ILL

Power Supply Current

180

mA

Outputs Open

III

Input leakage Current

±10

p,A

V1N=OtoV ee

ILOH

Tri-State Output leakage Current in Float

10

}.LA

V OUT = 2.4 to Vee

ILOL

rrri-State Output leakage Current in Float

-10

}.LA

V OUT = 0.5 V

IOH

DTACK output source current

-400

}.LA

V OUT

= 2.4

IOL

DTACK output sink current

5.3

mA

V OUT

= 0.5

SYM

PARAMETER

V 1H

V

2.4

All voltages are referenced to ground

VI-152

IOH = -120}.LA

CAPACITANCE
TA = 25°C, f = 1 MHz unmeasured pins returned to ground.

SYM

PARAMETER

C1N
COUT

MAX

UNIT

Input Capacitance

10

pf

Tri-state Output Capacitance

10

pf

AC ELECTRICAL CHARACTERISTICS (Vee

TEST
CONDITION
Unmeasured
pins
returned to
ground

= 5.0 Vdc ± 5%, GND =0 Vdc, TA =O°C to 70°C)

NUM

CHARACTERISTIC

1

CS, OS Width High

2

R/W, A1-A5 Valid to falling CS (Setup)

3

MK68901
MIN
MAX

UNIT

FIG

50

ns

21,22

0

ns

21,22

Data Valid Prior to Rising OS (Setup)

280

ns

21

4

CS, lACK Valid to Falling Clock (Setup)

50

ns

21-24

5

CLK Low to DTACK Low

220

ns

21,22

6

CS, OS or lACK High to DTACK high

60

ns

21-24

7

CS, OS or lACK High to DTACK Tri-state

100

ns

21-24

8

CS, OS or lACK High to Data Invalid (Hold Time)

ns

21-24

9

CS, OS or lACK High to Data Tri-state

ns

21-24

10

CS or OS High to R/W, A 1-A5 Invalid (Hold Time)

ns

21,22

11

Data Valid from CS Low

ns

21

12

Read Data Valid to DTACK Low (Setup Time)

50

ns

21

13

DTACK Low to OS, CS or lACK High (Hold Time)

0

ns

21-24

14

lEI low to falling CLK (Setup)

50

ns

23

2

15

lEO Valid from Clock Low (Delay)

180

ns

23

1

16

Data Valid From Clock Low (Delay)

300

ns

23

17

lEO Invalid from lACK High (Delay)

150

ns

23,24

18

DTACK Low from Clock High (Delay)

180

ns

23,24

2

19

lEO Valid from lEI Low (Delay)

100

ns

24

1

20

Data Valid from lEI Low (Delay)

220

ns

24

21

Clock Cycle Time

250

1000

ns

21-24

22

Clock Width Low

110

ns

21-24

23

Clock Width High

110

ns

21-24

24

CS, lACK Inactive to Rising Clock (Setup)

100

ns

21-24

25

I/O Minimum Active Pulse Width

100

ns

26

lACK width High

150

ns

0
50
0
310

VI-1S3

23-24

NOTE

3

4

•

AC ELECTRICAL CHARACTERISTICS (Continued) (Vcc = 5.0 Vdc

± 5%, GND = 0 Vdc, TA = OCC to 70 c C)

MK68901
MIN
MAX

NUM

CHARACTERISTIC

27

1/0 Data valid from Rising CS or DS

450

ns

28

Receiver Ready Delay from Rising RC

600

ns

29

Transmitter Ready Delay from Rising TC

600

ns

30

Timer Output Low from Rising Edge of CS or DS
(A & B) (Reset TOUT)

450

ns

31

TOUT Valid from Internal Timeout

2 tCLK
+300

ns

32

Timer Clock Low Time

110

ns

33

Timer Clock High Time

110

ns

34

Timer Clock Cycle Time

250

1000

UNIT

NOTE

ns

35

RESET Low Time

36

Delay to Falling INTR from External
Interrupt Active Transition

37

Transmitter Internal Interrupt Delay from Rising
of Falling Edge of TC

550

ns

38

Receiver Buffer Full Interrupt Transition Delay
from Rising Edge of RC

800

ns

39

Receiver Error Interrupt Transition Delay from
Falling Edge of RC

800

ns

40

Serial In Set Up Time to Rising Edge of RC
(Divide by one only)

80

ns

41

Data Hold Time from rising edge of RC
(Divide by one only)

350

ns

42

Serial Output Data Valid from Falling Edge of TC (--;-1 )

43

Transmitter Clock Low Time

500

ns

44

Transmitter Clock High Time

500

ns

45

Transmitter Clock Cycle Time

1.05

46

Receiver Clock Low Time

500

ns

47

Receiver Clock High Time

500

ns

48

Receiver Clock Cycle Time

1.05

49

CS, lACK, DS Width Low

50

Serial Output Data Valid from Falling
Edge of TC (--;-16)

2

FIG

p's
380

440

00

ns

ns

p's

00

p.S

80

TCLK

490

ns

NOTES:

1. lEO only goes low if no acknowledgeable interrupt is pending. If lEO goes
low, DTACK and the data bus remain tri-stated.
2. DTACK will go 10watA if spec. 14 is met; otherwise, DTACK will go lowat B.
3. If the setup time is not met, CS or iACK will not be recognized until the next
falling ClK.

4. If this setup time is met (for consecutive cycles), the minimum hold-off time
of one clock cycle will be obtained. If not met, the hold-off will be two clock
cycles.

VI-154

TIMER A. C. CHARACTERISTICS
Definitions:
Error = Indicated Time Value - Actual Time Value
tpsc

= tCLKx Prescale Value

Internal Timer Mode
Single Interval Error (free running) (Note 2) ...........................................•............. ± 100 ns
Cumulative Internal Error ..........................................................................••... 0
Error Between Two Timer Reads ...........................•.........................•...... ± (tpsc + 4 t CLK )
Start Timer to Stop Timer Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2 tCLK + 100 ns to - (tpsc + 6tCLK + 100 ns)
Start Timer to Read Timer Error .................................................. 0 to - (tpsc + 6tCLK + 400 ns)
Start Timer to Interrupt Request Error (Note 3) ....................................... -2 tCLK to - (4tCLK +800 ns)
Pulse Width Measurement Mode
Measurement Accuracy (Note 1) ..................................................... 2 tCLK to - (tpsc + 4tCLK )
Minimum Pulse Width .............................................................................. 4tCLK
Event Counter Mode
Minimum Active Time of TAl, TBI ..................................................................... 4tCLK
Minimum Inactive Time of TAl, TBI ................................................................... 4tCLK
NOTES:
,. Error may be cumulative if repetitively performed.
2. Error with respect to TOUT or INT if note 3 is true.
3. Assuming it is possible for the timer to make an interrupt request
immediately.

VI·155

•

READ CYCLE
Figure 21

ClK

R/W

A1 - A5

00-07------------------------------------~

OTACK----------------------------------~~~

WRITE CYCLE
Figure 22

ClK

R/Vii

A1 -A5

---

Clock Capacitance

35

pF

CIN

Input Capacitance

5

pF

COUT

Output Capacitance

10

pF

VII-3

•

MK3880A-4. MK3880B-6. Z80-CPU
AC CHARACTERISTICS
TA

=O°C to 70°C, Vee = +5 V ± 5%, Unless Otherwise Noted

SIGNAL SYMBOL

4>

Ao-15

te
tJ4>H)
tJ4>L)
tr,f

Clock
Clock
Clock
Clock

to(AO)
tF(AO)
taem
taci

Address Output Delay
Delay to Float
Address Stable Prior to MREO (Memory Cycle)
Address Stable Prior to 10RO, RD or WR
(I/O Cycle)
Address Stable From RD, WR. 10RO or MREO
Address Stable From RD or WR During Float

tea
teaf
tOlD)
tF(O)
tS(O)

0 0 -7

tS(O)
t dem
t dei
tedf
tH
tOL(MR)
tOH(MR)

MREQ

tOH(MR)
tw(MRL)
tw(MRH)

WR

MREO Delay From Falling Edge of Clock,
MREO Low
MREO Delay From Rising Edge of Clock,
MREO High
MREO Delay From Falling Edge of Clock,
MREO High
Pulse Width, MREO Low
Pulse Width, MREO High

(n8)

(n8)

(n8)

(n8)

250
110
110

[12]
500
500
30

165
70
70

[12]
500
500
20

110
90

90
80

[13]
[14]

[24]
[25]

[15]
[16]

[26]
[27]
150
90

130
80

35

30

50

40

[17]
[18]
[19]
0

[28]
[29]
[30]
0

20

85

20

70

85

70

85

70

[20]
[21]

[20]
[21 ]
65

85

70

85

70

85

70

tOL(RO)
tOL(RO)
tOH(RO)
tOH(BO)

RD
RD
RD
RD

85
95
85
85

70
80
70
70

tOL(WR)
tOL(WR)
tOH(WR)
tw(WRL)

~

tOL(lR)

tOH(IR)

-

Data Output Delay
Delay to Float During Write Cycle
Data Setup Time to Rising Edge of Clock During
M1 Cycle
Data Setup Time to Falling Edge at Clock During
M2 to M5
Data Stable Prior to WR (Memory Cycle)
Data Stable Prior to WR (I/O Cycle)
Data Stable from WR
Input Hold Time

3880B-6
MIN
MAX

75

tOH(IR)

-RD

Period
Pulse Width, Clock High
Pulse Width, Clock Low
Rise and Fall Time

3880A-4
MIN
MAX

10RO Delay From Rising Edge of Clock,
10RO Low
10RO Delay From Falling Edge of Clock,
10ROLow
10RO Delay From Rising Edge of Clock,
10RO High
10RO Delay From Falling Edge of Clock
Clock, 10RO High

tOL(IR)

10RO

PARAMETER

Delay
Delay
Delay
Delay

From
From
From
From

Rising Edge of Clock, RD Low
Falling Edge of Clock, RD Low
Rising Edge of Clock, RD High
Falling Edge of Clock, RD High

Delay From Rising Edge of Clock, WR Low
WR Delay From Falling Edge of Clock, WR Low
WR Delay From Falling Edge of Clock, WR High
Pulse Width, WR Low

NOTES:
A. Data should be enabled onto the CPU data bus when RD is active. During
interrupt acknowledge data should be enabled when iVii and 10RQare both
active.

15

15

65
80
80
[22]

60
70
70
[22]

B. The ~ signal must be active for a minimum of 3 clock cycles.
[Cont'd. on next page).

VII-4

MK3880A-4, MK3880B-6, Z80-CPU (con't.)

SIGNAL SYMBOL

3880 A-4
MAX
MIN

PARAMETER

(n5)

(n5)

3880 B-6
MIN
MAX
(n5)

(n5)

M1

t OL(M1)
t OH(M1)

M1 Delay From Rising Edge of Clock M1 Low
M1 Delay From Rising Edge of Clock M1 High

100
100

80
80

RFSH

tOL(RF)

RFSH Delay From Rising Edge of Clock,
RFSH Low
RFSH Delay From Rising Edge of Clock,
RFSR' High

130

110

120

100

tOH(RF)
WAIT

tS(WT)

WAIT Setup Time to Falling Edge of Clock

HALT

to(HT)

HALT Delay Time From Falling Edge of Clock

INT

ts(IT)

INT Setup Time to Rising Edge of Clock

80

70

NMI

tvv(NMI)

Pulse Width, NMI Low

80

70

BUSRO

tS(BQ)

BUSRO Setup Time to Rising Edge of Clock

50

BUSAK

tOL(BA)

BUSAK Delay From Rising Edge of Clock,
BUSAK Low
BUSAK Delay From Falling Edge of Clock,
BUSAK High

tOH(BA)
RESET

[1)

tACM

ts(RS)

RESET Setup Time to Rising Edge of Clock

tF(C)

Delay to/from Float (MREO, IORO, RD and WR)

tmr

M1 Stable Prior to IORO (Interrupt Ack.)

= tw( H) + tf-75

[17) tdcm

= tc -170

[2)

taci = te - 80

[18) tdci = tw (L) + tr -170

[3)

tCA = tw (L) + tr - 40

[19) tcdf = tw (L) + tr -70

[4)

tcaf = tw (L) + tr - 60

[20) tw (MRL)

= tc -30

[5)

tdcm

[21) tw (MAR)

= tw (H) + tf -20

[6)

tdci

[7)

tcdf = tw (L) + tr - 80

[23) tmr = 2tc + tw (H) + tf -65

[8)

tw (MRL) = tc - 40

[24) tACM = tw (H) + tf -50

[9)

tw (MRH)

70

60
300

nsec

260

50

100

90

100

90

60

60
80

70
[31 ]

[23]

LOAD CIRCUIT FOR OUTPUT

TEST POINT

= tc -

210

= tw(L) + tr -

[10) tw(WR)

[22) tw

210

= tw (H) + tf -

30

= tc- 4O

(wi'h = tc -30

[25) taci

[26) tCA = tw (L) + tr -50
[27) tcaf = tw (L) + tr -45

[12) tc = tw(H) + tw(L) + tr + tf

[28) tdcm = tc -140

[13) tacm = tw (L) + t r -140

= tc -70

[15) tca = tw (L) + tr -50
[16) tcaf

R2 =9.53KO

= tc -55

[11) tmr = 2 tc + tw (H) + tf - 80

[14) taci

FROM OUTPUT _ _----+---~
UNDER TEST

NOTES (Cont'd.)
Output Delay vs. Load Capacitance
TA =70°C V CC = 5 V ± 5%
Add 10 nsecdelayfor each 50pF increase in load upto a maximum of 200 pF
for the data bus and 100 pF for address and control lines.

[30) tcdf = tw (L) + tr -55
[31) tmr = 2tc + tw (H) + tf -50

= tw (L) + tr -45

VII-5

II

A.C. TIMING DIAGRAM
Timing measurements are made at the following voltages, unless otherwise specified:
CLOCK
OUTPUT
INPUT
FLOAT

"1"
V ee -·6
2.0V
2.0V
LV

"0"
.8V
.8V
.8V
±0.5 V

JUr'Lnunun__ nu~L1
- -t-

-I-P~

tD(ADI

~~------~----------~

O 16
•

A

=L>r- -----

,~---

____ J'

--- - -

-~.

Jr-f-__f--+--++--4--++J1

'---+l-----I-----V}<" --- ----

=·r~!<'1~:
t''Ir,: t~

0 {IN
.
0 7

OUT

.H
--

tDH(M1) -

tDL(M1)

--7

!

tDH (RF)
tDL (RFI

1-+

-

~---<'-+-­

/VF

l-jtl

MREQ

--t-.e-m-+<+t~NDL~(ir

tDH~(MR)

4-1"-

-

'-~--~I~~'H-~-(MJR)
~~ tW(MRi:r-~

t--++------+'I

_______

:

I

v

tDiT

.-;

tDL_~
(WRII

tDL~(lR)

I

tDH~(IR)

-

I
I~'---++---+---H-++'-"""

1 t.ei~

"---__---"Il/'

-

-

-- tee
0--

tedt

-

tF (C)
I-

r-

I--.~

--

11

I
jIf'

I

tDH~ (WRI
-

/

~

f'\

I

tDH~(WR)-

_t~1

'------...,..
',------

tD (HT)

tS(IT)

____ ,

,

f-=

tH
--~

!'I....--I.l.....-~

,

,---tS(BQ)

tH

1-· -

---i
!

I

I

f"-----'1.~

----,'

Y,,,-tDL (BA)

BUSAK

RESET

tS(RS) ~

-

----~x=-----i.: ,-----------~

"

,

VII-6

~~(C)

~ ' .. -- ----~ ~,' r "1--"'1-V1--., ~
,-~-/
~_
VI--"_., __ r i'I!_

-

-

t~ (WRLI

tD!i(RDI-

tDL~(WRI

-teaf

I

tDH;j;(lR)-

FL~(RD'

I- - - - - - -__f+-----------4---4----+-4-:......

---------,'

d

tF (D)

... ~--

_

,l

'

".

------++-------~---+-----+---+-ll-..- -

tS(WT)

)-

"tDij'RD' -

--+----+~--I_+______t4__-+---____I_,-+---+-+---tdem -

-

MR

N-----+--i+--~

-tw (MRHI

""'I~l't-D-L~-(_+RD+_I)---tD-H-~-(R-D-)4
-..r

tDl$(lR)

fr

~ '.
__ _.... J.-

__ .... ___
----

... - _ .

--+ --- --- -..~1'-

f-----j
i

tDH(BA)

ORDERING INFORMATION

PACKAGE TYPE

MAX CLOCK
FREQUENCY

MK3880AN-04 Z80-CPU

Plastic

4.0 MHz

0° to +70°C

MK3880BN-06 Z80-CPU

Plastic

6.0 MHz

0° to +70°C

PART NO.

TEMPERATURE RANGE

•

V11-7

Vll-8

m

UNITED
TECHNOLOGIES
MOSTEK

MICROCOMPUTER
COMPONENTS
PARALLEL I/O CONTROLLER
MK3881

FEATURES

o
o

PIO PIN CONFIGURATION
Figure 1

Two independent a bit bidirectional peripheral interface
ports with 'handshake' data transfer control

DO

a.

Interrupt driven 'handshake' for fast response

DATA

BUS

o

j

03

D.
05

Anyone of four distinct modes of operation may be
selected for a port, including:

PORT A

I/O

06
07

Byte output
Byte input
Byte bidirectional bus (Available on Port A only)
Bit control mode
All with interrupt controlled handshake

o

0,
'02

PORT B/A SEL

CONTROL/OAT A
SEL
Pia
CONTROL

CHIP ENABLE

M1

{

IORO

AD

Daisy chain priority interrupt logic included to provide for
automatic interrupt vectoring without external logic

PORT B

I/O

iiiiT

o Eight outputs are capable
transistors

of driving

Darlington

INTERRUPT
CONTROL

INT ENABLE IN

{

INT ENABLfi. OUT

o All inputs and outputs fully TTL compatible
can be programmed to interrupt if any specified peripheral
alarm conditions should occur. This interrupt capability
reduces the amount of time that the processor must spend
in polling peripheral status.

o Single 5 volt supply and single phase clock required.
INTRODUCTION
The zao Parallel I/O Circuit is a programmable, two port
device which provides a TTL compatible interface between
peripheral devices and the zao-cpu. The CPU can
configure the zao-Plo to interface with a wide range of
peripheral devices with no other external logic required.
Typical peripheral devices that are fully compatible with the
zao-Plo include most keyboard, paper tape readers and
punches, printers, PROM programmers, etc. The zao-Plo
utilizes N channel silicon gate depletion load technology
and is packaged in a 40 pin DIP.

PIN DESCRIPTION
A diagram of the zao-Plo pin configuration is shown in
Figure 1. This section describes the function of each pin.
zao-cpu Data Bus (bidirectional, tristate)
This bus is used to transfer all data and
commands between the zao-cpu and the
zao-Plo. Do is the least significant bit of the
bus.

One of the unique features of the zao-Plo that separates it
from other interface controllers is that all data transfer
between the peripheral device and the CPU is accomplished
under total interrupt control. The interrupt logic of the PIO
permits full usage of the effic;ient interrupt capabilities of the
zao-cpu during I/O transfers. All logic necessary to
implement a fully nested interrupt structure is included in
the PIO so that additional circuits are not required. Another
unique feature of the PIO is that it can be programmed to
interrupt the CPU on the occurrence of specified status
conditions in the peripheral device. For example, the PIO

VII·9

B/A Sel

Port B or A Select (input, active high)
This pin defines which port will be accessed
during a data transfer between the zao-cpu
and the zao-Plo. A low level on this pin
selects Port A while a high level selects Port
B. Often Address Bit Ao from the CPU will be
used for this selection function.

C/OSel

Control or Data Select (input, active high)
This pin defines the type of data transfer to be
performed between the CPU and the PIO. A

•

If AD is active a MEMORY READ or I/O READ
operation is in progress. The RO signal is
used with B/A Select, C/O Select, CE and
10RO signals to transfer data from the zaoPia to the zao-cpu.

high level on this pin during a CPU write to
the Pia causes the zao data bus to be
interpreted as a command for the port
selected by the B/A Select line. A low level on
this pin means that the zao data bus is being
used to transfer data between the CPU and
the Pia. Often Address bit A1 from the CPU
will be used for this function.
Chip Enable (input, active low)
A low level on this pin enables the Pia to
accept command or data inputsfrom the CPU
during a write cycle or to transmit data to the
CPU during a read cycle. This signal is
generally a decode of four I/O port numbers
that encompass port A and B, data and Control.

lEI

Interrupt Enable In (input, active high)
This signal is used to form a priority interrupt
daisy chain when more than one interrupt
driven device is being used. A high level on
this pin indicates that no other devices of
higher priority are being serviced by a CPU
interrupt service routine.

lEO

Interrupt Enable Out (output, active high)
The lEO signal is the other signal required to
form a daisy chain priority scheme. It is high
only if lEI is high and the CPU is not servicing
an interrupt from this Pia. Thus this signal
blocks lower priority devices from interrupting while a higher priority device is being
serviced by its CPU interrupt service routine.

INT

Interrupt Request (output, open drain, active
low)
When INT is active the zao-Plo is requesting
an interrupt from the zao-cpu.

Ao-A7

Port A Bus (bidirectional, tri-state)
This a bit bus is used to transfer data and/or
status or control information between Port A
of the zao-Plo and a peripheral device. Ao is
the least significant bit of the Port Adata bus.

A STB

Port A Strobe Pulse from peripheral Device
(input, active low)
The meaning of this signal depends on the
mode of operation selected for Port A as
follows:

System Clock (input)
The zao-Plo uses the standard zao system
clock to synchronize certain signals internally.
This is a single phase clock.
Machine Cycle One Signal from CPU (input,
active low)
This signal from the CPU is used as a sync
pulse to control several internal PIO operations. When M 1 is active and the RO signal is
active, the zao-cpu is fetching an instruction
from memory. Conversely, when M 1 is active
and 10RO is active, the CPU is acknowledging
an interrupt. In addition, the M1 signal has
two other functions within the zao-Plo.
1. M1 synchronizes the Pia interrupt logic.
2. When M1 occurs without an active RO or
10RO Signal, the Pia logic enters a reset
state.
10RO

Input/Output Request from zao-cpu (input,
active low)
The 10RO signal is used in conjunction with
the B/A Select, C/O Select, CE, and RO
signals to transfer commands and data
between the zao-cpu and the zao-Plo.
When CE, RO and 10RO are active, the port
addressed by B/A will transfer data to the
CPU (a read operation). Conversely, when CE
and 10RO are active but RO is not active, then
the port addressed by S/A will be written into
from the CPU with either data or control
information as specified by the C/O Select
signal. Also, if IORO and M1 are active
simultaneously, the CPU is acknowledging
. an interrupt and the interrupting port will
automatically place its interrupt vector on the
CPU data bus if it is the highest device
requesting an interrupt.

3) Bidirectional mode: When this signal is
active, data from the Port A output register
is gated onto Port A bidirectional data bus.
The positive edge of the strobe acknowledges the receipt of the data.

Read Cycle Status from the zao-cpu (input,
active low)

4) Control mode: The strobe is inhibited internally.

VII·10

1) Output mode: The positive edge of this
strobe is issued by the peripheral to
acknowledge the receipt of data made
available by the Pia.
2) Input mode: The strobe is issued by the
peripheral to load data from the peripheral
into the Port A input register. Data is
loaded into the Pia when this signal is
active.

ARDY

Register A Ready (output, active high)
The meaning of this signal depends on the
mode of operation selected for Port A as follows:

status or control information between Port B
of the PIO and a peripheral device. The Port B
data bus iscapable of supplying 1.5 ma@ 1.5 V
to drive Darlington transistors. Bo is the least
significant bit of the bus.

1) Output mode: This signal goes active to
indicate that the Port A output register has
been loaded and the peripheral data bus is
stable and ready for transfer to the
peripheral device.

Port B Strobe Pulse from Peripheral Device
(input, active low)
The meaning ofthis signal is similar to that of
A STB with the following exception:

2) Input mode: This signal is active when the
Port A input register is empty and is ready
to accept data from the peripheral device.
3) Bidirectional mode: This signal is active
when data is available in Port A output
register for transfer to the peripheral
device. In this mode data is not placed on
the Port A data bus unless A STB is active.
4) Control mode: This signal is disabled and
forced to a low state.

In the Port A bidirectional mode this signal
strobes data from the peripheral device
into the Port A input register.

BRDY

Register B Ready (output, active high)
The meaning ofthis signal is similar to that of
A Ready with the following exception:
In the Port A bidirectional mode this signal
is high when the Port A input register is
empty and ready to accept data from the
peripheral device.

Port B (bidirectional, tristate)
This 8 bit bus is used to transfer data and/or

OUTPUT LOAD CIRCUIT
Figure 2
TEST POINT

FROM OUTPUT O---~t-----..-------«;
UNDER T.EST

1 N914 OR EQUIVALENT

C L = 50 pF on DO - 0 7
C L = 50 pF on All Others

For further details on this device, please consult the PIO
MK3881 Technical Manual, included in Section IV.

V11-11

•

ELECTRICAL SPECIFICATIONS
MK3881
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ............................................................ Specified operating range
Storage Temperature ....................................................................... -65°C to +150°C
Voltage On Any Pin With ..................................................................... -0.3 V to +7 V
Respect To Ground
Power Dissipation ....................................................................................6 W
All ac parameters assume a load capacitance of 100 pF max. Timing references between two output signals assume a load
difference of 50 pF max.
*Stressesabove those listed under "Absolute Maximum Ratings" maycause permanent damage tothedevice. This is a stress rating only and functional operation of
the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

D.C. CHARACTERISTICS
TA = O°C to 70°C, Vee = 5 V ± 5% unless otherwise specified

SYMBOL

PARAMETER

MIN

MAX

UNIT

V,Le

Clock Input Low Voltage

-0.3

0.80

V

V ,He

Clock Input High Voltage

Vee -.6

Vee +.3

V

V ,L

Input Low Voltage

-0.3

0.8

V

V ,H

Input High Voltage

2.0

Vee

V

VOL

Output Low Voltage

0.4

V

IOL = 2.0 mA

V OH

Output High Voltage

V

IOH = -250 pA

lee

Power Supply Current

70*

mA

III

Input Leakage Current

±10

pA

V,N=OtoVcc

ILOH

Tri-State Output Leakage Current in Float

10

p,A

V OUT = 2.4 to Vee

ILOL

Tri-State Output Leakage Current in Float

-10

pA

VOUT= 0.4 V

ILO

Data Bus Leakage Current in Input Mode

±10

p.A

O:::;V,N :::;Vcc

IOHD

Darlington Drive Current

mA

V oH =1.5V
Port B Only

2.4

-1.5

TEST CONDITION

*150 mA for -4, -10, and -20 devices.

CAPACITANCE
TA = 25°C, f = 1 MHz

SYMBOL

PARAMETER

MAX

UNIT

Cq,

Clock Capacitance

10

pF

Unmeasured Pins

C
'N

Input Capacitance

5

pF

Returned to Ground

COUT

Output Capacitance

10

pF

VII-12

TEST CONDITION

A.C. CHARACTERISTICS MK3881. MK3881-10. MK3881-20. Z80-PIO
TA

= O°C to 70°C, V CC = +5 V ± 5%, unless otherwise noted

SIGNAL

cp

C/D SEL
CE ETC.

3881
MIN
MAX

SYMBOL

PARAMETER

tc
tW(H)
tW(L)
t r, t f

Clock
Clock
Clock
Clock

th

Any Hold Time for Specified Set-Up Time

tS(CS)

Control Signal Set-up Time to Rising Edge of
cp During Read or Write Cycle

tOR(O)
tS(O)

Data Output Delay from Falling Edge of RD
Data Set-up Time to Rising Edge of cp During
Write or M1 Cycle
Data Output Delay from Falling Edge of IORO
During INTA Cycle
Delay to Floating Bus (Output Buffer Disable Time)

Do - D7
tol(O)
tF(O)

Period
Pulse Width, Clock High
Pulse Width, Clock Low
Rise and Fall Times

400
170
170

[1 ]
2000
2000
30

3881-4
MIN
MAX

UNIT

[1 ]
2000
2000
30

nsec
nsec
nsec
nsec

250
105
105

0

0

nsec

145

145

nsec

430

380

nsec
nsec

340

250

nsec

160

110

nsec

50

50

lEI

tS(IEI)

lEI Set-Up Time to Falling Edge of IORO During
INTA cycle

140

140

nsec

lEO

tOH(lO)
tOL(lO)
tOM(IO)

lEO Delay Time from Rising Edge of lEI
lEO Delay Time from Falling Edge of lEI

210
190

160
130

nsec
nsec

lEO Delay from Falling Edge of M1 (Interrupt
Occurring Just Prior to M1) See Note A.

300

190

nsec

IORO

tS(IR)

IORO Set-Up Time to Rising Edge of cp During
Read or Write Cycle

115

115

nsec

M1

t S(M1)

M1 Set-Up Time to Rising Edge of cP During
INTA or M1 Cycle. See Note B.

210

90

nsec

RD

tS(RO)

RD Set-Up Time to Rising Edge of cP During
Read or M 1 Cycle

115

115

nsec

tS(PO)

Port Data Set-Up Time to Rising Edge of
STROBE (Mode 1)
Port Data Output Delay from Falling Edge of
STROBE (Mode 2)
Delay to Floating Port Data Bus from Rising
Edge of STROBE (Mode 2)
Port Data Stable from Rising Edge of IORO
During WR Cycle (Mode 0)

260

230

nsec

Pulse Width, STROBE

150

150

[4]

[4]

toS(PO)
Ao -A7
Bo - B7

tF(PO)
tOI(PO)

ASTB
BSTB

tWIST)

INT

to(lT)
t o(IT3)

INT Delay Time from Rising Edge of STROBE
INT Delay Time from Data Match During
Mode 3 Operation

ARDY

tOH (RY)

BRDY

tOL(RY)

Ready Response Time from Rising Edge of IORO
Ready Response Time from Rising Edge of
STROBE

VII-13

230

210

nsec

200

180

nsec

200

180

nsec

nsec
nsec

490
420

440
380

nsec
nsec

tc+ 46O
tc +
400

tc+41 0
tc +
360

nsec
nsec

•

A. 2.5 tc

> (N-2)tOL(lO)+tOM(IO)+tS(lEI)+TIL Buffer Delay, if any.

[3]

Increase tOI (D) by 10 nsec for each 50 pF increase in loading up to 200 pF
max.

B. M 1 must be active for a minimum of 2 clock periods to reset the PIO.
[1]
[2]

tc = t W (H) + tw(L) + tr + tf
Increase tOR(O) by 10 nsec for each 50 pF increase in loading up to 200 pF
max.

[4]

For Mode 2: tw (ST) > tS(PO)

[5]

Increase these values by 2 nsec for each 10 pF increase in loading up to
.100 pF max.

TIMING DIAGRAM
Figure 3

Timing measurements are made at the following voltages, unless otherwise specified:
CLOCK
OUTPUT
INPUT
FLOAT

lEI

lEO

READY
(A ROY OR
B ROY)

Si'ROBE
(AS'fB

OR

BsT"Eh

(MODE 2)

(MODE 1)

(MODE 3)

INT

VII-14

"'"

4.2V
2.0V
2.0V
6V

"0"
O.BV
Q.BV
O.BV
0.5V

ORDERING INFORMATION
PART NO.

DESIGNATOR

PACKAGE TYPE

MAX CLOCK FREQUENCY

MK3881 N

l80-PIO

Plastic

2.5 MHz

MK3881 P

l80-PIO

Ceramic

2.5 MHz

MK3881 N-4

l80A-PIO

Plastic

4.0 MHz

MK3881 P-4

l80A-PIO

Ceramic

4.0 MHz

MK3881 P-10

l80-PIO

Ceramic

4.0 MHz

TEMPERATURE
RANGE

0° to 70°C

-40° to +85°C

•

VII-15

VlI·16

!t

UNITED

TECHNOLOGIES
MOSTEK

MICROCOMPUTER
COMPONENTS
COUNTER TIMER CIRCUIT
MK3882

FEATURES

o

laO-CTC PIN CONFIGURATION
Figure 1

All inputs and outputs fully TIL compatible

o Each channel may be selected to operate in either
Counter Mode or Timer Mode
DATA BUS
CPU

o Used in either mode, a CPU-readable Down Counter
indicates number of counts-to-go until zero

1

ZC/TO,

CHANNEL
SIGNALS

CLK/TRG2

ZC/T02

o A Time Constant Register can automatically reload the
Down Counter at Countlero in Counter and Timer Mode

MK3882
Z80·CTC

CSa

•

CS,

o Selectable positive or negative trigger initiates time
operation in Timer Mode. The same input is monitored
for event counts in Counter Mode.

CTC
CONTROL

CHIP
ENABLE

'6

o Three channels have lero Count/Timeout outputs
capable of driving Darlington transistors
+5V

o Interrupts may be programmed to occur on the zero
count condition in any channel

GND

o Daisy chain priority interrupt logic included to provide for
automatic interrupt vectoring without external logic

INTERRUPT {INT ENA:
CONTROL

INT

ENAa~~

~:
"

OUT

INTRODUCTION

~-----.....I

The laO-Counter Timer Circuit (CTC) is a programmable
component with four independent channels that provide
counting and timing functions for microcomputer systems
based on the l80-CPU. The CPU can configure the CTC
channels to operate under various modes and conditions as
required to interface with a wide range of devices. In most
applications, little or no external logic is required. The l80CTC utilizes N-channel silicon gate depletion load
technology and is packaged in a 28-pin DIP. The laO-CTC
requires only a single 5 volt supply and a one-phase 5 volt
clock.

the l80-CTC. There are a bits on this bus, of
which Do is the least significant.
CS1-CSO

Channel Select (input, active high)
These pins form a 2-bit binary address code
for selecting one of the four independent CTC
channels for an I/O Write or Read (See truth
table below.)
CS1

CTC PIN DESCRIPTION
A diagram of the l80-CTC pin configuration is shown in
Figure 1. This section describes the function of each pin.

lao-cPU Data Bus (bidirectional, tristate)
This bus is used to transfer all data and
command words between the laO-CPU and

VII-17

ChO
Ch1
Ch2
Ch3

0
0
1
1

CSO

a
1

a
1

Chip Enable (input, active low)
A low level on this pin enables the CTC to
accept control words, Interrupt Vectors, or
time constant data words from the l80 Data

Bus during an I/O Write cycle, or to transmit
the contents of the Down Counter to the CPU
during an I/O Read cycle. In most applications this signal is decoded from the a least
significant bits of the address bus for any of
the four I/O port addresses that are mapped
to the four Counter/Timer Channels.
CI~k(

!SYMBOL
tc
tw(H)
t~l)

t r, t f
tH

CS, CE, etc. ts(CS)

to(D)
ts(D)
Do - D7

tol(D)
tr=!D)

lEI

38823882-4
MIN MAX

PARAMETER
Clock
Clock
Clock
Clock

Period
Pulse Width, Clock High
Pulse Width, Clock low
Rise and Fall Times

Any Hold Time for Specified
Setup Time
Control Signal Setup Time to
Rising Edge of  During Read
or Write Cycle
Data Output Delay from Rising
Edge of  During Read Cycle
Data Setup Time to Rising Edge
of  During Write or M1 Cycle
Data Output Delay from Falling
Edge of IORO During INTA Cycle
Delay to Floating Bus (Output
Buffer Disable Time)

ts(IEI)

lEI Setup Time to Falling Edge
of IORO During INTA Cycle

tOH(IO)

lEO Delay Time from RiSing Edge
of lEI
lEO Delay Time from Falling
Edge of lEI
lEO Delay from Falling Edge of
M1 (Interrupt Occurring just
Prior to M1)

tod lO )

400
170
170

(1 )
2000
2000
30

MIN

MAX

250
105
105

(1 )
2000
2000
30

UNIT COMMENTS
ns
ns
ns

0

0

ns

160

145

ns

240
60

200
50

ns
ns

340

160

ns

230

110

ns

200

140

220

160

ns

(3)

190

130

ns

(3)

300

190

ns

(3)

toM(lO)

IORO

ts(IR)

IORO Setup Time to Rising Edge
of  During Read or Write Cycle

250

115

ns

M1

ts(M1 )

M1 Setup Time to Rising Edge
of  During INTA or M1 Cycle

210

90

ns

RD

ts(RD)

RD Setup Time to Rising Edge
of  During Read or M1 Cycle

240

115

ns

INT

to(IT)

INT Delay from Rising Edge of 

td CK )
t r, t f

Clock Period
Clock and Trigger Rise and Fall
Times
Clock Setup Time to Rising Edge
of  for Immediate Count
Trigger Setup Time to Rising
Edge of  for Enabling of
Prescaler on Following Rising
Edge of 

ts(TR)

ClK/
TRG O_3

t~CTH)
t~CTL)

Clock and Trigger High Pulse
Width
Clock and Trigger low Pulse
Width

VII-20

(2)

ns

lEO

ts(CK)

(2)

(7)

td, ZC/TO High
ZC/TO Delay Time from Falling
Edge of <1>, ZC/TO Low

tDdZC)

TOO-2

NOTES:
1. tc = tw (H) + tw(L) + tr + tf.

3882-4
MIN
MAX

UNIT COMMENTS

190

120

ns

(7)

190

120

ns

(7)

OUTPUT LOAD CIRCUIT

Increase delay by 10 nsec for each 50 pF increase in loading 200 pF
maximum for data lines and 100 pF for control lines.
3. Increase delay by 2 nsec for each 10 pF increase in loading, 100 pF
maximum.
4. RESET must be active for a minimum of 3 clock cycles.
5. Counter mode
6. Timer mode
7. Counter and Timer mode

Figure 2

2.

TEST POINT

VCC

FRot.1 OUTPUT
ur,OER TEST

CR1' CR4 lN9l4 OR EQUIVALENT
CL = 50 pF ON ALL PINS

I

VII-21

•

TIMING DIAGRAM
Figure 3

CLOCK
OUTPUT
INPUT
FLOAT

Timing measurements are made at the following voltages, unless otherwise specified:
T3/TW

00- 0 7
_tDl(O)--- tS(Ml)-

Mi
tOM(iO)-

lEI

ts(lEI)

lEO

-

tOL(lO)

-

INT

tc(CK)

(COUNTER MODE)

CLK/
TRG _
O3
(TIMER MODE)

ZC/TO O_
2

VII-22

T4/T3

T1

"1 "

"0"

4.2V
2.0V
2.0V
6.V

O.BV
O.BV
O.BV
0.5V

ORDERING INFORMATION
PART NO.

DESIGNATOR

PACKAGE TYPE

MAX CLOCK FREQUENCY

MK3882N

Z80-CTC

Plastic

2.5 MHz

MK3882P

Z80-CTC

Ceramic

2.5 MHz

MK3882N-4

Z80A-CTC

Plastic

4.0 MHz

MK3882P-4

Z80A-CTC

Ceramic

4.0 MHz

MK3882P-10

Z80-CTC

Ceramic

4.0 MHz

TEMPERATURE
RANGE

0° to 70°C

-40° to +85°C

•

VII·23

VII-24

fJ

UNITED

MICROCOMPUTER
COMPONENTS

TECHNOLOGIES
MOSTEK

DIRECT MEMORY ACCESS CONTROLLER
MK3883
FEATURES

o

Transfers, searches and search/transfers in byte-ata-time, burst or continuous modes. Cycle length and
edge timing can be programmed to match the speed
of any port.

o

Standard Z80 Family bus-request and prioritized
interrupt-request daisy chains implemented without
external logic. Sophisticated, internally modifiable
interrupt vectoring.

o

Direct interfacing to system buses without external
logic.

o Dual port addresses (source and destination)
generated for memory-to-I/O, memory-to-memory,
or I/O-to-I/O operations. Addresses may be fixed or
automatically incremented/decremented.

o

o

Next-operation loading without disturbing current
operations via buffered starting-address registers.
An entire previous sequence can be repeated
automatically.
Extensive programmability of functions. CPU can
read complete channel status.

GENERAL DESCRIPTION
The MK3883 Z80 DMA (Direct Memory Access) is a
powerful and versatile device for controlling and
processing transfers of data. Its basic function of
managing CPU-independent transfers between two
ports is augmented by an array of features that optimize
transfer speed and control with little or no external logic
in systems using an 8- or 16-bit data bus and a 16-bit
address bus.

PIN FUNCTIONS

PIN ASSIGNMENTS

Figure 1

Figure 2

ZSODMA

SYSTEM
ADDRESS
BUS
SUS
{
CONTROL

As

1

40 AS

A4

2

39 A7

A3

3

38 lEI

A2

4

37

A,

5

36 lEO

Ao

6

35 DO

ClK

7

340,

WR

8

RD

9

33 O2
32 0 3

IORO 10
+sv 11

OV=M
CONTROL {

29 Os

BAO 13

28 Os

BAI14

270 7

CE/WAIT 16

+6V

GND

CLK

VII-2S

31 0 4
30 GNO

MREO 12

iffiSiffi 1 5

BUS

iNT

26

M1

25 ROY

A,S 17

24 AS

A'4 18
A'3 19

23

AU 20

21 A"

As

22 A,o

•

Transfers can be done between any two ports (source
and destination), including memory-to-I/O, memory-tomemory, and I/O-to-I/O. Dual port addresses are
automatically generated for each transaction and may
be either fixed or incrementing/decrementing. In
addition, bit-maskable byte searches can be performed
either concurrently with transfers or as an operation in
itself.
The MK3883 l80 DMA contains direct interfacing to
and independent control of system buses, as well as
sophisticated bus and interrupt controls. Many programmable features, including variable cycle timing and
a uto-restart minimize CPU software overhead. They are
especially useful in adapting this special-purpose
transfer processor to a broad variety of memory, 110 and
CPU environments.

FUNCTIONAL DESCRIPTION
Classes of Operation
The MK3883 l80 DMA has three basic classes of
operation:
• Transfers of data between two ports (memory or 1/0
peripheral)
• Searches for a particular 8-bit maskable byte at a
single port in memory or an 110 peripheral
• Combined transfers with simultaneous search
between two ports
Figure 4 illustrates the basic functions served by these
classes of operation.
BASIC FUNCTIONS OF THE Z80 DMA
Figure 4

The MK3883 l80 DMA is an n-channel silicon-gate
depletion-load device packaged in a 40-pin plastic, or
ceramic DIP. It uses a single +5V power supply and the
standard l80 Family single-phase clock.

Z800MA

1/0

l80 ENVIRONMENT WITH MULTIPLE DMA
CONTROLLERS
Figure 3

1/0

L--+-_--+....PERIPHERAL
SYSTEM
BUSES

1.
2.
3.
4.
5.

PRIORITY 2

-"

f

V

" +5

Search memory
Transfer memory-to-memory (optional search)
Transfer memory-to-I/O (optional search)
Search I/O
Transfer I/O-to-I/O (optional search)

OMA

,...

INT
ROY
lEI

+5V

1-

WT'

I

lEO

lEI

~

I"RIORITY 1

ROY

f1\

~

.J,.

V

DMA

During a transfer, the DMA assumes control of the
system control, address, and data buses. Data is read
from one addressable port and written to the other
addressable port, byte by byte. The ports may be
programmed to be either system main memory or
peripheral 110 devices. Thus, a block of data may be
written from one peripheral to another, from one area of
main memory to another, or from a peripheral to main
memory and vice versa.
During a search-only operation, data is read from the
source port and compared byte by byte with the DMAinternal register containing a programmable match
byte. This match byte may optionally be masked so that
only certain bits within the match byte are compared.
Search rates up to 1.25M bytes per second can be
obtained with the 2.5MHz MK3883 l80 DMA or 2M
bytes per second with the 4MHz MK3883-4 l80 DMA.
In combined searches and transfers, data is transferred
between two ports while simultaneously searching for a
bit-maskable byte match.
Data transfers or searches can be programmed to stop
or interrupt under various conditions. In addition, CPUreadable status bits can be programmed to reflect the
condition.

VII-26

Modes of Operation

Variable Cycle

The MK3883 Z80 DMA can be programmed to operate
in one of three transfer andlor search modes:

The Z80 DMA has the unique feature of programmable
operation-cycle length. This is valuable in tailoring the
DMA to the particular requirements of other system
components (fast or slow) and maximizes the datatransfer rate. It also eliminates external logic for Signal
conditioning.

• Byte-at-a-time: data operations are performed one
byte at a time. Between each byte operation the
system buses are released to the CPU. The buses
are requested again for each succeeding byte
operation.
• Burst: data operations continue until a port's Ready
line to the DMA goes inactive. The DMA then stops
and releases the system buses after completing its
current byte operation.
• Continuous: data operations continue until the end
ofthe programmed block of data is reached before the
system buses are released. If a port's Ready line goes
inactive before this occurs, the DMA simply pauses
until the Ready line comes active again.

There are two aspects to the variable cycle feature. First,
the entire read and write cycles (periods) associated
with the source and destination ports can be
independently programmed as 2, 3 or 4 T-cycles long
(more if Wait cycles are used), thereby increasing or
decreasing the speed with which all DMA signals
change (Figure 5).
VARIABLE CYCLE LENGTH
Figure 6

In all modes, once a byte of data is read into the DMA,
the operation on the byte will be completed in an orderly
fashion, regardless of the state of other signals
(including a port's Ready line).
Due to the DMA's high-speed buffered method of
reading data, operations on one byte are not completed
until the next byte is read in. Consequently, total transfer
or search block lengths must be two or more bytes, and
those block lengths programmed into the DMA must be
one byte less than the desired block length (count is N-1
where N is the block length).
Commands and Status
The Z80 DMA has several writeable control registers
and readable status registers available to the CPU.
Control bytes can be written to the DMAwhile the DMA
is enabled or disabled, but the act of writing a control
byte to the DMA disables the DMA until it is again
enabled by a specific command. Status bytes can also be
read at any time, but writing the Read Status command
or the Read Mask command disables the DMA.
Control bytes to the DMA include those which effect
immediate command actions such as enable, disable,
reset, load starting-address buffers, continue, clear
counters, clear status bits and the like. In addition, many
mode-setting control bytes can be written, including
mode and class of operation, port configuration, starting
addresses, block length, address counting rule, match
and match-mask byte, interrupt conditions, interrupt
vector, status-affects-vector condition, pulse counting,
auto restart, Ready-line and Wait-line rules, and read
mask.
Readable status registers include a general status byte
reflecting Ready-line, end-of-block, byte-match and
interrupt conditions, as well as Dual-byte registers for
the current byte count, Port A address and Port B
address.

II
Second, the four signals in each port specifically
associated with transfers of data (1/0 Request, Memory
Request, Read and Write) can each have its active
trailing edge terminated one-half T-cycle early. This
adds a further dimension of flexibility and speed,
allowing such things as shorter-than-normal Read or
Write signals that go inactive before data starts to
change.
Address Generation
Two 16-bit addresses are generated by the Z80 DMA for
every transfer or search operation, one address for the
source Port A and another for the destination Port B.
Each address can be either variable or fixed. Variable
addresses can increment or decrement from the
programmed starting address. The fixed-address
capability eliminates the need for separate enabling
wires to 1/0 ports.
Port addresses are multiplexed onto the system address
bus, depending on whether the DMA is reading the
source port or writing to the destination port. Two
readable address counters (2-bytes each) keep the
current address of each port.
Auto Restart
The starting addresses of either port can be reloaded
automatically at the end of a block. This option is
selected by the Auto Restart control bit. The byte
counter is cleared when the addresses are reloaded.

VII-27

The Auto Restart feature relieves the CPU of software
overhead for repetitive operations such as CRT refresh
and many others. Moreover, the CPU can write different
starting addresses into buffer registers during transfers
causing the Auto Restart to begin at a new location.
Interrupts
The MK3883 Z80 DMA can be programmed to interrupt
the CPU on four conditions:
• Interrupt on Ready (before requesting bus)
• Interrupt on Match
• Interrupt on End of Block
• Interrupt on Match at End of Block
Any of these interrupts cause an interrupt-pending
status bit to be set, and each ofthem can optionally alter
the DMA's interrupt vector. Due to the buffered
constraint mentioned under "Modes of Operation,"
interrupts on Match at End of Block are caused by
matches to the byte just prior to the last byte in the block.
The DMA shares the Z80 family's elaborate interrupt
scheme, which provides fast interrupt service in realtime applications. In a Z80 CPU environment, the DMA
passes its internally modifiable 8-bit interrupt vector to
the CPU, which adds an additional eight bits to form the
memory address of the interrupt-routine table. This
table contains the address of the beginning of the
interrupt routine itself.
I n this process, CPU control is transferred directly to the
interrupt routine, so that the next instruction executed
after a n interrupt acknowledge is the first instruction of
the interrupt routine itself.

have their BAI connected to the BAD of a higher-priority
DMA.
BAO. Bus Acknowledge Out (output, active Low). In a
multiple-DMA configuration, this pin signals that no
other higher-priority DMA has requested the system
busses. BAI and BAD form a daisy chain for multipleDMA priority resolution over bus control.
BUSRQ. Bus Request (bidirectional, active Low, open
drain). As an output, it sends requests for control of the
system address bus, data bus and control bus to the
CPU. As an input when multiple DMAs are strung
together in a priority daisy chain via BAI and BAD, it
senses when another DMA has requested the buses
and causes this DMA to refrain from bus requesting until
the other DMA is finished. Because it is a bidirectional
pin, there cannot be any buffers between this DMA and
any other DMA. It can, however, have a unidirectional
into the CPU. A pull-up resistor is connected to this pin.
CE/WAIT. Chip Enable and Wait (input, active Low).
Normally this functions only as a CE line, but it can also
be programmed to serve a WAIT function. As a CE line
from the CPU, it becomes active when WR and 10RO are
active and the I/O port address on the system address
bus is the DMA's address, thereby allowing a transfer of
control or command bytes from the CPU to the DMA. As
a WAIT line from memory or I/O devices, after the DMA
has received a bus-request acknowledge from the CPU,
it causes wait states to be inserted in the DMA's
operation cycles thereby slowing the DMA to a speed
that matches the memory or liD device.

External devices can keep track of how many bytes have
been transferred by using the DMA's pulse output,
which provides a signal at 256-byte intervals. The
interval sequence may be offset at the beginning by 1 to
255 bytes.

ClK. System clock (input). Standard Z80 single-phase
clock at 2.5MHz (MK3883) or 4.0MHz (MK3883-4). For
slower system clocks, a TTL gate with a large pullup resistor
may be adequate to meet the timing and voltage level
specification. For higher-speed systems, use a clock driver
with an active pullup to meet the V 1H specification and
risetime requirements. In all cases there should be a
resistive pullup to the power supply of 10K ohms (max) to
ensure proper power when the DMA is reset.

The interrupt line outputs the pulse signal in a manner
that prevents misinterpretation by the CPU as an
interrupt request, since it only appears when the Bus
Request and Bus Acknowledge lines are both active.

00-07' System Data Bus (bidirectional, 3-state).
Commands from the CPU, DMA status, and data from
memory or liD peripherals are transferred on these
lines.

PIN DESCRIPTIONS

lEI. Interrupt Enable In (input, active High). This is used
with lEO to form a priority daisy chain when there is
more than one interrupt-driven device. A High on this
line indicates that no other device of higher priority is
being serviced by a CPU interrupt service routine.

Pulse Generation

AO-A15' System Address Bus (output, 3-state). Addresses generated by the DMA are sent to both source
and destination ports (main memoryor liD peripherals)
on these lines.
BAI. Bus Acknowledge In (input, active Low). Signals
that the system buses have been released for DMA
control. In multiple-DMA configurations, the BAI pin of
the highest priority DMA is normally connected to the
Bus Acknowledge pin of the CPU. Lower-priority DMAs

lEO. Interrupt Enable Out (output, active High). lEO is
High only if lEI is High and the CPU is not servicing an
interrupt from this DMA. Thus, this signal blocks lowerpriority devices from interrupting while a higher-priority
device is being serviced by its CPU interrupt service
routine.

VII-28

INT. Interrupt Request(output, active Low, open drain).
This requests a CPU interrupt. The CPU acknowledges
the interrupt by pulling its 10RO output Low during an
M1 cycle. It is typically connected to the INT pin of the
CPU with a pullup resistor and tied to all other INT pins
in the system.

RD. Read (bidirectional, active Low, 3-state). As an
input. this indicates that the CPU wants to read status
bytes from the DMA's read registers. As an output, after
the DMA has taken control of the system buses, it
indicates a DMA-controlled read from a memory or I/O
port address.

IORO. Input/Output Request (bidirectional, active
Low, 3-state). As an input, this indicates that the lower
half ofthe address bus holds a valid I/O port address for
transfer of control or status bytes from or to the CPU,
respectively; this DMA is the addressed port if its CE pin
and its WR or RD pins are simultaneously active. As an
output, after the QMA has taken control of the system
busses, it indicates that the lower ha If of the address bus
holds a valid port address for another I/O device
involved in a DMA transfer of data. When 10RO and M 1
are both active simultaneously, an interrupt acknowledge is indicated.

WR. Write (bidirectional, active Low, 3-state). As an
input, this indicates that the CPU wants to write control
or command bytes to the DMA write registers. As an
output, after the DMA has taken control of the system
busses, it indicates a DMA-controlled write to a memory
or I/O port address.

M1. Machine Cycle One (input, active Low). Indicates
that the current CPU machine cycle is an instruction
fetch. It is used by the DMA to decode the return-frominterrupt instruction (RETI) (ED-4D) sent by the CPU.
During two-byte instruction fetches, M1 is active as
each opcode byte is fetched. An interrupt acknowledge
is indicated when both M1 and 10RO are active.
MREO. Memory Request (bidirectional, active Low, 3state). This indicates that the address bus holds a valid
address for a memory read or write operation. As an
input, it indicates that control or status information from
or to memory is to be transferred to the DMA, if the
DMA's CE and WR or RD lines are simultaneously
active. As an output, after the DMA has taken control of
the system buses, it indicates a DMA transfer request
from or to memory.

ROY. Ready(input, programmable active Lowor High).
This is monitored by the DMA to determine when a
peripheral device associated with a DMA port is ready
for a read or write operation. Depending on the mode of
DMA operation (byte, burst or continuous), the ROY line
indirectly controls DMA activity by causing the BUSRO
line to go Low or High.
INTERNAL STRUCTURE
The internal structure of the MK3883 Z80 DMA
includes driver and receiver circuitry for interfacing
with an 8-bit system data bus, a 16-bit system address
bus, and system control lines (Figure 6). In a Z80 CPU
environment, the DMA can be tied directly to the
analogous pins on the CPU (Figure 7) with no additional
buffering, except for the CE/WAIT line.
The DMA's internal data bus interfaces with the system
data bus and services all internal logic and registers.
Addresses generated from this logic for Ports A and B
(source and destination) of the DMA's single transfer
channel are multiplexed onto the system address bus.

BLOCK DIAGRAM
Figure 6

INTERRUPT
AND BUS
PRIORITY
LOGIC

PULSE
LOGIC

BYTE
COUNTER

PORTA
ADDRESS

SYSTEM
DATA
BUS

CONTROL

SYSTEM
ADDRESS
BUS

BUS
CONTROL
LOGIC

CONTROL
AND
STATUS
REGISTERS

VII-29

BYTE
MATCH
LOGIC

PORTB
ADDRESS

•

Specialized logic circuits in the DMA are dedicated to
the various functions of external bus interfacing,
internal bus control, byte matching, byte counting,
periodic pulse generation, CPU interrupts, bus requests,
and address generation. A set oftwenty-one writeable
control registers and seven readable status registers
provide the means by which the CPU governs and
monitors the activities of these logic circuits. All
registers are eight bits wide, with double-byte
information stored in adjacent registers. The two
starting-address registers (two bytes each) for Ports A
and B are buffered.

RRO-RRS - Read Registers 0 through 6

Writing to a register within a write-register group
involves first writing to the base register, with the
appropriate pointer bits set, then writing to one or more
of the other registers within the group. All seven of the
readable status registers are accessed sequentially
according to a programmable mask contained in one of
the writeable registers. The section entitled "Programming" explains this in more detail.
A pipelining scheme is used for reading data in. The
programmed block length is the number of bytes
compared to the byte counter, which increments at the
end of each cycle. In searches, data byte comparisons
with the match byte are made during the read cycle of
the next byte. Matches are, therefore, discovered only
after the next byte is read in.

The 21 writeable control registers are organized into
seven base-register groups, most of which have
multiple registers. The base registers in each writeable
group contain both control/command bits and pointer
bits that can be set to address other registers within the
group. The seven readable status registers have no
analogous second-level registers.
The registers are designated as follows, according to
their base-register groups:

In multiple-DMA configurations, interrupt-request
daisy chains are prioritized by the order in which their
lEI and lEO lines are connected. The system bus,
however, may not be pre-empted. Any DMA that gains

WRO-WR6 - Write Register groups 0 through 6 (7 base
registers plus 14 associated registers)

access to the system buses keeps them until it is
finished.

MULTIPLE-DMA INTERCONNECTION TO THE

zao CPU

Figure 7

COMMON:

....---------4BUSAK

!NT
BUSRQ
M1

CPU

iC5Ra
MREQ
RD

TO NEXTDMA
FROM HIGHER-PRIORITY
INTERRUPTING DEVICE

DMA

DMA
lEO I--------,J~ lEI

lEI
RDY

lEO
RDY

VII-30

TO LOWER-PRIORITY
INTERRUPTING DEVICE

Writing

WRITE REGISTERS

WRO

Base register byte
Port A starting address (low byte)
Port A starting address (high byte)
Block length (low byte)
Block length (high byte)

WR1

Base register byte
Port A variable-timing byte

Control or command bytes are written into one or more
ofthe Write Register groups (WRO-WR6) by first writing
to the base register byte in that group. All groups have
base registers and most groups have additional
associated registers. The associated registers in a group
are sequentially accessed by first writing a byte to the
base register containing register-group identification
and pointer bits (1 's) to one or more of that base
register's associated registers.

WR2

Base register byte
Port B variable-timing byte

READ REGISTERS

WR3

Base register byte
Mask byte
Match byte

WR4

Base register byte
Port B starting address (low byte)
Port B starting address (high byte)
Interrupt control byte
Pulse control byte
Interrupt vector

WR5

Base register byte

WR6

Base register byte
Read mask

Figure 8a.
READ REGISTER 0

0 7 0 6 0 5 0 4 0 3 O2 0, DO
STATUS BYTE

~l1;
L--_ _ _ _ _ _

'

= DMAOPERATION

HAS OCCURRED

o = READY ACTIVE
.UNDEFINED

o = INTERRUPT PENDING
0 = MATCH FOUND

'----------0

= END OF BLOCK
UNDEFINED

READ REGISTERS
READ REGISTER'

RRO

Status byte

RR1

Byte counter (low byte)

RR2

Byte counter (high byte)

BYTE COUNTER
I (LOW
BYTE)

'---...L.._'---L----''---'---L_..I....--I.

READ REGISTER 2
BYTE COUNTER
I (HIGH
BYTE)

'---...L.._'--~_L---L---'_..I..--J.

RR3

Port A address counter (low byte)

READ REGISTER 3

RR4

Port A address counter (high byte)

'---...L.._L...--L----''---'---L_...L...--I.

RR5

Port B address counter (low byte)

RR6

Port B address counter (high byte)

PORT A ADDRESS COUNTER
I (LOW
BYTE)

READ REGISTER 4
'---...L.._'---L----''---'---L_..I....--I

PORT A ADDRESS COUNTER
(HIGH BYTE)

READ REGISTER 5
PORT B ADDRESS COUNTER
I (LOW
BYTE)

PROGRAMMING

L---L-_L--.....&.----IL-.....L.---L_..I....--I.

READ REGISTER 6

zao

The
OMA has two programmable fundamental
states: (1) an enabled state, in which itcan gain control
of the system buses and direct the transfer of data
between ports, and (2) a disabled state, in which it can
initiate neither bus requests or data transfers. When the
OMA is powered up or reset by any means, it is
automatically placed into the disabled state. Program
commands can be written to it by the CPU in either state,
but this automatically puts the OMA in the disabled
state, which is maintained until an enabled command is
issued by the CPU. The CPU must program the OMA in
advance of any data search or transfer by addressing it
as an I/O port and sending a sequence of control bytes
using an Output instruction (such as OTIR for the
CPU).

zao

PORT B ADDRESS COUNTER
I (HIGH
BYTE)

' -........._ ' - - - ' - _ ' - -........- - ' _.............J.

This is illustrated in Figure a. In this figure, the
sequence in which associated registers within a group
can be written to is shown by the vertical position ofthe
associated registers. For example, if a byte written to the
OMA contains the bits that identify WRO (bits 00, 01
and 07), and also contains 1 's in the bit positions that
point to the associated "Port A Starting Address (low
byte)" and "Port A Starting Address (high byte)" then
the next two bytes written to the DMA will be stored in
these two registers, in that order.

VII-31

•

WRITE REGISTERS

WRITE REGISTER 2

Figure 8b
WRITE REGISTER 0

BASE REGISTER BYTE

................-r-.......,r-'--.-""--,r-'--.-"'-r~...,.... BASE REGISTER BYTE

o
o

0

0= MEMORY
1 = 1/0
0= PORT B ADDRESS DECREMENTS
1 = PORT B ADDRESS INCREMENTS

DO NOT USE

1 = TRANSFER
o

1
o = PORT B
1 = PORT A

0= PORT B ADDRESS VARIABLE
1 = PORT B ADDRESS FIXED

= SEARCH
= SEARCHITRANSFER

r---r-'---r---r--r---,---r---r---, PORT B

PORT A
PORT B

'--r-.L..'T""'""'----'--""--,,.--L-r-.......,,.-&--r-' VARIABLE TIMING BYTE
o = CYCLE LENGTH = 4
1 = CYCLE LENGTH = 3
o = CYCLE LENGTH co 2
o
1 DO NOT USE
~-+-----+--+---= WR ENDS Y2 CYCLE EARLY
= AD ENDS Y2 CYCLE EARLY
=c MFi'Eci ENDS Y2 CYCLE EARLY
' - - - - = 10RQ ENDS Y2 CYCLE EARLY

PORT A STARTING ADDRESS
................-r-""--,-.L..-.-"'----'--"'----'----' (LOW BYTE)
PORT A STARTING ADDRESS
................,.........,......-"'--......-"----'----' (HIGH BYTE)

'----J,.-.-.L---L._.L---'-_"---......L~

......-----1-+----

......-+----

BLOCK LENGTH
(LOW BYTE)
WRITE REGISTER 3

BLOCK LENGTH
'--.........-"'---L.-.L---'--"'--~---'(HIGH BYTE)

D7 D6

D5

D4 D3

O2

D,

DO

.......~-.-"'-r--'--r-.a......,..............-'----'-_O... BASE REGISTER BYTE
WRITE REGISTER 1

1 = STOP ON MATCH

07

De 0 5 0 4

-+--+-+-- =
-+---+-- =

0 3 O2 0 1 DO
o

'----L.-.-~--L.-.-~~-"---......L~

BASE REGISTER BYTE

0= MEMORY
1 = 1/0

DMA ENABLE
INTERRUPT ENABLE"

................- " ' - -.........-."'--.........-"'----'-----1

o = PORT A ADDRESS DECREMENTS
1 = PORT A ADDRESS INCREMENTS

MASK BYTE (0 = COMPARE)

.......--'-_"'----'-_"'----'-__"'--..........~MATCHBYTE

0= PORT A ADDRESS VARIABLE
1 = PORT A ADDRESS FIXED

are always read in a fixed sequence beginning with RRO
and ending with RR6. However, the register read in this
PORTA
sequence is determined by programming the Read Mask
~""""'-.-"'---L.-"""",.--L-.-L.....,r-'-~ VARIABLE TIMING BYTE
in WR6. The sequence of reading is initialized bywriting
an Initiate Read Sequence or Set Read Status command
o = CYCLE LENGTH = 4
1 = CYCLE LENGTH = 3
to WR6. After a Reset DMA, the sequence must be
o = CYCLE LENGTH = 2
initialized with the Initiate Read Sequence command or
1 DO NOT USE
o
a Read Status command. The sequence of reading all
.......-+----+---+--- = WR ENDS Y2 CYCLE EARLY
registers that are not excluded by the Read Mask
" - - - - - - - t - - - I - - - = RD ENDS Y2 CYCLE EARLY
L...--+_ _ _ = MREQ ENDS Y2 CYCLE EARLY register must be completed before a new Initiate Read
L...-_ _ = 10RQ ENDS Y2 CYCLE EARLY
Sequence or Read Status command.
Fixed-Address Programming
Reading
The Read Registers (RRO-RR6) are read by the CPU by
addressing the DMA as an I/O port using an Input
instruction (such as INIR for the
CPU). The readable
bytes contain DMA status, byte-counter values, and
port addresses since the last DMA reset. The registers

zao

A special circumstance arises when programming a
destination port to have a fixed address. The load
command in WR6 only loads a fixed address to a port
selected as the source, not to a port selected as the
destination. Therefore, a fixed destination address must
be loaded by temporarily declaring it a fixed-source

VII-32

VRITE REGISTERS

WRITE REGISTER 6

igure 8b

D7 D6

VRITE REGISTER 4
'7 D6

D5

D4 D3 D2 D1

11

DO

D5 D4 D3 D2

I I I
I I I I I
0
0
0
0
1

1

D1

11

DO

I BASE REGISTER BYTE

HEX
BASE REGISTER BYTE

0
0

0

1
1

0

=
=
=
=

1
1

C3

BYTE
CONTINUOUS
BURST
DO NOT PROGRAM

C7

0

0

0

0

CF

0

0

D3 1

0

CB

PORT B STARTING
ADDRESS (LOW BYTE)
PORT B STARTING
ADDRESS (HIGH BYTE)
INTERRUPT
CONTROL BYTE

0

1

AB
AF
A3

1 = INTERRUPT ON MATCH
= INTERRUPT AT END OF
BLOCK
= PULSE GENERATED
= STATUS AFFECTS VECTOR
= INTERRUPT ON RDY

1

0
0
0

0
0

0
0
0
0

1
1

1

0

0

87

0

0

0

0

83

0

0

0

0

PULSE CONTROL BYTE

A7

0

0

0

INTERRUPT VECTOR

BF

0

B3

0

8B

0

B7

0

BB

0

= INTERRUPT ON RDY
= INTERRUPT ON MATCH
= INTERRUPT ON END OF
BLOCK
= INTERRUPT ON MATCH
AT END OF BLOCK

0

0

0

0
.1

0

0

0

0
0

WRITE REGISTER 5
D7 D6 D5

D4 D3 D2 D1

DO

0

RESET INTERRUPT CIRCUITRY,
DISABLE INTERRUPT AND BUS
REQUEST LOGIC, UNFORCE
INTERNAL nEADY CONDITION,
DISABLE "MUXCE" AND STOP
AUTO REPEAT.
RESET PORT A TIMING TO
STANDARD zao CPU TIMING.
= RESET PORT B TIMING TO
STANDARD zao CPU TIMING.
LOAD STARTING ADDRESS FOR
BOTH PORTS, CLEAR BYTE
COUNTER.
ADDRESS CONTINUE FROM
PRESENT LOCATIONS, CLEAR
BYTE COUNTER.
ENABLE INTERRUPTS.
DISABLE INTERRUPTS.
RESET AND DISABLE INTERRUPT
CIRCUITS (LIKE RETI) AND
UNFORCETHEINTERNALREADY
CONDITON.
BOTH AFFECT ALL
ENABLE DMA OPERATIONS EXCEPT INTERRUPTS,
DISABLE DMA BUT DO NOT RESET
ANY FUNCTIONS.
INITIATE READ SEQUENCE TO THE
FIRST REGISTER DESIGNATED AS
READABLE BY THE READ MASK
REGISTER.
SET READ STATUS SO NEXT READ
IS FROM STATUS REGISTER.
FORCE AN INTERNAL READY
CONDITION INDEPENDENT
"OF THE RDY" INPUT. (USED FOR
MEMORY-TO-MEMORY
OPERATIONS WHERE NO RDY
SIGNAL IS NEEDED. THIS
COMMAND DOES NOT FUNCTION
IN THE "BYTE-AT-A- TIME" MODE).
CLEAR MATCH AND END OF
BLOCK STATUS BITS.
ENABLE AFTER RETI SO DMA
REQUESTS BUS ONLY AFTER
RECEIVING A RET!. MUST BE
FOLLOWED BY AN ENABLE DMA
COMMAND.
READ MASK IS THE FOLLOWING
BYTE

BASE REGISTER BYTE
READ MASK (1
o = READY ACTIVE LOW
1 = READY ACTIVE HIGH
O=CEONLY
1 = C"E7'WAii' MULTIPLEXED
o = STOP ON END OF BLOCK
1 = AUTO REPEAT ON END OF BLOCK

= ENABLE)

STATUS
BYTE COUNTER (LOW BYTE)
BYTE COUNTER (HIGH BYTE)
PORT A ADDRESS (LOW BYTE)
PORT A ADDRESS (HIGH BYTE)
PORT B ADDRESS (LOW BYTE)
PORT B ADDRESS (HIGH BYTE)

VII-33

II

SAMPLE DMA PROGRAM
Figure 9

COMMENTS

07

08

06

1
1
Block Length B lock Length
Upper
Lower
Follows
Follows

04

03

O2

0,

DO

HEX

1
PortA
Upper
Address
Follows

1
PortA
Lower
Address
Follows

0
B-"A
Temporary
for
Loading B
Address

0

1

79

WRO sets OMA to receive
block length. Port A starting address and temporarily
sets Port B as source.

0

Port A address (lower)

0

1

0

1

0

0

0

0

50

Port A address (upper)

0

0

0

1

0

0

0

0

10

Block length (lower)

0

0

0

0

0

0

0

0

00

Block length (upper)

0

0

0

1

0

0

0

0

10

WR1 defines Port A as
peripheral with fixed
address.

0

0
No Timing
Follows

0
Address
Changes

1
Address
Increments

0
Port is
Memory

1

0

0

14

This is
PortA

WR2 defines Port B as
peripheral with fixed
address.

0

0
No Timing
Follows

1
Fixed
Address

0

1
Port is
1/0

0
This is
Port B

0

0

28

WR4 sets mode to Burst.
sets OMA to expect Port B
address.

1

1

0

0
No Interrupt
Control Byte
Follows

0
No Upper
Address

1
Port BLower
Address
Follows

0

1

C5

Port B address (lower)

0

0

0

0

0

1

0

1

05

WR5 sets Ready active High

1

0

0
No Auto
Restart

0
No Wait
States

1
ROY
Active High

0

1

0

8A

WR6 loads both Port addresses
and resets block counter!

1

1

0

0
Load

1

1

1

1

CF

WRO sets Port A as source!

0

0

0

1
A-..B

WR6 reloads Port addresses
and resets block counter

1

1

0

0
Load

1

1

1

1

CF

WR6 enables DMA to start
operation.

1

0

0

0
Enable DMA

0

1

1

1

87

Burst Mode

0
0
No Address of Block
Length Bytes

Transfer. No Search

0
1
Transfer. No Search

05

NOTE: The actual number of bytes transferred is one more than specified by the block length.
*These commands are necessary only in the case of a fixed destination address.

address and subsequently declaring the true source as
such, thereby implicitly making the other a destination.
The following example illustrates the steps in this
procedure, assuming that transfers are to occur from a
variable-address source (Port A) to a fixed-address
destination (Port 8):
1. Temporarily declare Port 8 as source in WRO.
2. load Port 8 address in WRS.
3. Declare Port A as source in WRO.
4. load Port A address in WRS.
5. Enable DMA in WRS.
Figure 9 illustrates a program to transfer data from
memory (Port A) to a peripheral device (Port 8). In this
example, the Port A memory starting address is 10S0H
and the Port 8 peripheral fixed address is OSH' Note that
the data flow is 1001 H bytes-one more than specified

by the block length. The table of DMA commands may be
stored in consecutive memory locations and transferred
to the DMA with an output instruction such as the zao
CPU's OTIR instruction.
INACTIVE STATE TIMING (DMA as CPU Peripheral)
I nits inactive state, the DMA is addressed by the CPU as
an I/O peripheral for write and read (control and status)
operations. Write timing is illustrated in Figure 10.
Reading of the DMA's status byte, byte counter or port
address counters is illustrated in Figure 11. These
operations require less than three T-cycles. The CE,
10RO and RD lines are made active over two rising
edges of ClK, and data appears on the bus
approximately one T -cycle after they become active.

VII-34

ACTIVE STATE TIMING (DMA as Bus Controller)

CPU-TO-DMA WRITE CYCLE

Figure 10

The DMA is active when it takes control of the system
bus and begins transferring data.

ClK

Default Read and Write Cycles
CE_t-_""'\
lORa

By default, and after reset the DMA's timing of read and
write operations is exactly the same as the
CPU's
timing of read and write cycles for memory and 1/0
peripherals, with one exception: during a read cycle,
data is latched on the falling edge of T3 and held on the
data bus across the boundary between read and write
cycles, through the end of the following write cycle.

zao

CPU-TO-DMA READ CYCLE
Figure 11

Figure 12 illustrates the timing for memory-to-1I0 port
transfers and Figure 13 illustrates 1I0-to-memory
transfers. Memory-to-memory and I/O-to-I/O transfer
timings are simply permutations of these diagrams.

MEMORY-TO-I/O TRANSFER
Figure 12

ClK

_ -yr- '- n:

{

~

WRITE

RO

r

II

~

MREO READ

n..:. rt:-"- [tr--

Variable Cycle and Edge Timing

I

-1'\

zao

I
f~

1\

10RO

f~

\

WR

IJ-

--- ---1-)1'\

t--

+- -

-- --

1--

~/~ --

-

I/O-TO-MEMORY TRANSFER
Figure 13

ClK

r--

SLrL ...... rLrL
IX

A O·A 15
{
READ
RO

-I--

r-"-

IL

/

t\

I

00. 0 7

WRITE

1)-

\

{MREO

r

I---

~V
- - V'K - - 1-1--

The
DMA's default operation-cycle length for the
source (read) port and destination (write) port can be
independently programmed. This variable-cycle feature
allows read or write cycles consisting of two, three or
four T -cycles (more if Wait cycles are inserted), thereby
increasing or decreasing the speed of all signals
generated by the DMA. In addition, the trailing edges of
the 10RO, MREO, RD and WR signals can be
independently terminated one-half cycle early. Figure
14 illustrates this.
In the variable-cycle mode, unlike default timing, 10RO
comes active one-half cycle before MREO, RD and WR.
CE/WAIT can be used to extend only the 3 or 4 T -cycle
variable cycles. It is sampled at the falling edgeofT2 for
3- or 4-cycle memory cycles, and at the falling edge of
T3 for 4-cycle 1/0 cycles.
During transfers, data is latched on the clock edge
causing the rising edge of RD and held until the end of
the write cycle.

I--

WR

CE7WAiT -'

r--

IX

IX

-f--t\.
10RO

The default timing uses three T-cycles for memory
transactions and four T-cyclesfor 1/0 transactions,
which include one automatically inserted wait cycle
between T 2 andT3.lfthe CE/WAIT line isprogrammed
to act as WAIT line during the DMA's active state, it is
sampled on the falling edge of T 2 for memory
transactions and the falling edge of TW for 1/0
transactions. If CE/WAIT is low during this time another
T -cycle is added, during which the CE/WAIT line will
again be sampled. The duration of transactions can thus
be indefinitely extended.

--

~-

.

V'\

I- - -

1--

Bus Requests
Figure 15 illustrates the bus request and acceptance
timing. The RDY line, which may be programmed active

•

VARIABLE-CYCLE AND EDGE TIMING

BUS RELEASE WHEN NOT READY (BURST MODE)

Figure 14

Figure 18

ClK
ClK

ACTIVE
ROY

INACTIVE

I.

~CURRENT
IORO , ' -_ _ _'--

BYTE
OPERATION

MREO~

t

RD. WR

I

,-r- .,--I

I

-~-

BUS RELEASE ON MATCH
(BURST AND CONTINUOUS MODES)

t

Figure 19

4-CYClE
EARLY
END

2-CYClE
EARLY
END

DMA
INACTIVE

BUS REQUEST AND ACCEPTANCE

ROY INACTIVE

Figure 15

'Bu'SR6:

I.

--------~/r--------------~~
~ BYTE
BYTE n + 1
READ 100
READ IN AND
MATCH FOUND
ON BYTE N

_I...

DMA DMA
ACTIVE INACTIVE

BUS RELEASE (BYTE-AT-A-TIME MODE)
Figure 16

ClK~'LJL..JL...rL.r

I~~_ _ _ _- - I •
I
I

BITSRQ

'/~

BAI
DMA ACTIVE

I

~

DMA INACTIVE

BUS RELEASE (CONTINUOUS MODE)
Figure 17

ROY

ACTIVE
INACTIVE

High or low, is sampled on every rising edge of ClK.lf it
is found to be active, and the bus is not in use by any
other device, the following rising edge of ClK drives
BUSRO low. After receiving BUSRO, the CPU
acknowledges on the BAI input either directly or
through a multiple-OMA daisy chain. When a low is
detected on BAI for two consecutive rising edges of ClK,
the OMA will begin transferring data on the next rising
edge of ClK.
Bus Release Byte-at-a-Time
In Byte-at-a-Time mode, BUSRO is brought high on the
rising edge of ClK prior to the end of each read cycle
(search-only) or write cycle (transfer and transfer /
search) as illustrated in Figure 16. This is done
regardless of the state of ROY. There is no possibility of
confusion when a Z80 CPU is used since the CPU
cannot begin an operation until the following T-cycle.
Most other CPUs are not bothered by this either,
although note should be taken of it. The next bus
request for the next byte will come after both BUSRO
and BAI have returned high.
Bus Release at End of Block

{

~lAST BYTE
OPERATION
BLOCK

DMA
INACTIVE

In Burst and Continuous modes, an end of block causes
BUSRO to go High usually on the same rising edge of
ClK in which the OMA completes the transfer of the
data block (Figure 17). The last byte in the block is
transferred even if ROY goes inactive before completion
of the last byte transfer.

VII-36

Bus Release on Not Ready
In Burst Mode, when ROY goes inactive it causes
BUSRO to go High on the next rising edge of ClK after
the completion of its current byte operation (Figure 18).
The action on BUSRQ is thus somewhat delayed from
action on the ROY line. The DMA always completes its
current byte operation in an orderly fashion before
releasing the bus.

being read. Matches at End-of-Block are, therefore,
actually matches to the byte immediately preceding the
last byte in the block.
The ROY line can go inactive after the matching
operation begins without affecting this bus-release
timing.
Interrupts
Timings for interrupt acknowledge and return from
interrupt are the same as timings for these in other Z80
peripherals.

By contrast, BUSRQ is not released in Continuous mode
when ROY goes inactive. Instead, the OMA idles after
completing the current byte operation, awaiting an
active ROY again.

Interrupt on ROY (interrupt before requesting bus) does
not directly affect the BUSRQ line. Instead, the interrupt
service routine must handle this by issuing the
following commands to WR6:
1. Enable after Return From Interrupt (RETI) Command
-Hex B7
2. Enable DMA- Hex 87
3. A RETI instruction that resets the IUS latch in the
Z80DMA

Bus Release on Match
If the DMA is programmed to stop on match in Burst or
Continuous modes, a match causes BUSRQ to go
inactive on the rising edge of ClK after the next byte
following the match (Figure 19). Due to the pipelining
scheme, matches are determined while the next byte is

II

ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Operating Ambient Temperature Under Bias ...................... As Specified Under "Ordering Information"
Storage Temperature .................................................................... -65°C to +150°C
Voltage on any pin with respect to ground .................................................... -0.3V to +7V
Power Dissipation .................................................................................. 1.5W
Stresses greater than those listed under Absolute Maximum Ratings maycause permanent damage to the device. This is a stress rating only; operation ofthe device at
any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

STANDARD TEST CONDITIONS

Figure 20

The characteristics below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND. Positive current flows
into the referenced pin. Standard conditions are as
follows:
• +4.75 ~ VCC :::; +5.25V
• GND = OV
• ODC ~ TA ~ + 70°C

FROM OUTPUT Q----,----r-M._-I
UNDER TEST

All AC parameters assume a load capacitance of
100pF max. Timing references between two output
signals assume a load difference of 50pF max.
DC CHARACTERISTICS
SYM

PARAMETER

MIN

MAX

UNIT

Vile

Clock Input Low Voltage

-0.3

0.80

V

VIHC

Clock Input High Voltage

VCC-·6

5.5

V

Vil

Input Low Voltage

-0.3

0.8

V

VII-37

TEST CONDITION

DC CHARACTERISTICS
SYM

PARAMETER

MIN

MAX

UNIT

VIH

Input High Voltage

2.0

5.5

V

VOL

Output Low Voltage

0.4

V

IOL =3.2mA for BUSRO
IOL =2.0mA for all others

VOH

Output High Voltage

V

IOH=250J,LA

ICC

Power SU8Ply Current
MK388
MK3883-4

III

Input Leakage Current

ILOH

2.4
150
200

TEST CONDITION

mA
mA

±10

J,LA

VIN = 0 to VCC

Tri-State Output Leakage Current
in Float

10

J,LA

VOUT=2.4 to VCC

ILOL

Tri-State Output Leakage Current
in Float

-10

J,LA

VOUT=O.4V

ILD

Data Bus Leakage Current in
Input Mode

±10

J,LA

O:::;VIN :::;VCC

MAX

UNIT

Vee = 5V ± 5% unless otherwise specified, over specified temperature range.

CAPACITANCE
MIN

TEST CONDITION

SYM

PARAMETER

C

Clock Capacitance

35

pF

Unmeasured Pins

CIN

Input Capacitance

10

pF

Returned to Ground

COUT

Output Capacitance

10

pF

f = 1 MHz, over specified temperature range

INACTIVE STATE AC CHARACTERISTICS
(See Figure 21)

MK3883

MK3883-4

SYM

PARAMETER

MIN

MAX

MIN

MAX

UNIT

1

TcC

Clock Cycle Time

400

4000

250

4000

ns

2

TwCh

Clock Width (High)

170

2000

105

2000

ns

3

TwCI

Clock Width (Low)

170

2000

105

2000

ns

4

TrC

Clock Rise Time

30

30

ns

5

TfC

Clock Fall Time

30

30

ns

6

Th

Hold Time for Any Specified
Setup Time

7

TsC(Cr)

lORa, WR, CE

8

TdDO(RDf)

RD to Data Output Delay

9

TsWM(Cr)

Data In to Clock

TdCf(DO)

IORO to Data Out Delay (lNTA Cycle)

NO

i 10

0

t to Clock t Setup

280

0

ns

145

ns

500

t Setup (WR or M1)

t

VII-3S

50

380
50

340

ns
ns

160

ns

INACTIVE STATE AC CHARACTERISTICS (Continued)
MK3883
NO

SYM

PARAMETER

MIN

11

TdRD(Dz)

RDtto Data Float Delay (output buffer
disable)

12

TsIEI(IORO) lEI

13

TdIEOr(lElr)

14

TdIEOf(IElf)

15

TdM1(1EO)

M1tto IEOt Delay (interrupt just prior
to M1 ,)

16

TsM1f(Cr)

M 1 to Clock

17

TsM1 r(Cf)

M1

18

TsRD(C)

19

Tdl(lNT)

Interrupt Cause to INT .. Delay (lNT
generated only when DMA is
inactive)

20

TdBAlr
(BAOr)

BAI

21

TdBAlf
(BAOf)

BAI

22

TsRDY(Cr)

t to 10RO , Setup (INTA Cycle)
lEI t to lEO t Delay
lEI t to lEO t Delay

+

t Setup

t to Clock, Setup
RD t to Clock t Setup (M1 Cycle)

MAX

MIN

160
140

MAX

UNIT

110

ns

140

ns

210

160

ns

190

130

ns

300

190

ns

210

90

ns

20

0

ns

240

115

ns

t to SAO t Delay

t to BAO t Delay
ROY Active to Clock t Setup

MK3883-4

500

500

ns

200

150

ns

200

150

ns

150

100

ns

ACTIVE STATE AC CHARACTERISTICS
(See Figure 22)

MK3883-4

MK3883

MIN(ns) MAX(ns) MIN(ns)

MAX(ns)

SYM

PARAMETER

1

TcC

Clock Cycle Time

400

2

TwCh

Clock Width (High)

180

2000

110

2000

3

TwCI

Clock Width (Low)

180

2000

110

2000

4

TrC

Clock Rise Time

30

30

5

TfC

Clock Fall Time

30

30

6

TdA

Address Output Delay

145

110

7

TdC(Az)

Clockt to Address Float Delay

110

90

8

TsA(MREO) Address to MREO

9

TsA(IRW)

NO

t Setup (Memory Cycle)

Address Stable to 10RO, RD, WR
(1/0 Cycle)

t Setup

250

(2)+(5)-75

(2)+(5)-75

(1 )-80

(1 )-70

*10

TdRW(A)

RD, WR t to Addr. Stable Delay

(3)+(4)-40

(3)+(4)-50

* 11

TdRW(Az)

RD, WR

t to Addr. Float

(3)+(4)-60

(3)+(4)-45

12

TdCf(DO)

Clock

t to Data Out Delay

230
VII·39

150

•

ACTIVE STATE AC CHARACTERISTICS
MK3883-4

MK3883
NO

SYM

PARAMETER

MIN(ns) MAX(ns) MIN(ns)

MAX(ns)

*13

TdCr(Dz)

Clock

90

90

14

TsDI(Cr)

Data In to Clock Setup (Read cycle when
rising edge ends read)

15

TsDI(Cf)

Data In to Clock Setup (Read cycle when
falling edge ends read)

*16

TsDO(WfM) Data Out to WR

t Setup (Memory Cycle)

17

TsDO(Wfl)

Data Out to WR

t Setup (1/0 cycle)

*18

TdWr(DO)

WR

19

Th

Hold Time for Any Specified Setup Time

*20

TdCr(Mf)

Clock

21

TdCf(Mf)

Clock

22

TdCr(Mr)

Clock

23

TdCf(Mr)

t to MREO t Delay
Clock t to MREO +Delay

24

TwMl

MREO Low Pulse Width

(1 )-40

*25

TwMh

MREO High Pulse Width

(2)+(5)-30

26

TdCr(lf)

Clock

27

TdCf(lf)

Clock

28

TdCr(lr)

Clock

*29

TdCf(lr)

30

TdCr(Rf)

-t to 10RO +Delay
Clock t to RD t Delay

31

TdCf(Rf)

Clock

32

TdCr(Rr)

33

t to Data Float Delay (Write Cycle)
t

50

35

t

60

50

(1)-210

(1 )-170

100

t to Data Out Delay

100

(3)+(4)-80

(3)+(4)-70

0

t to MREO t Delay

t to MREO t Delay

t to 10RO t Delay

0
100

85

100

85

100

85

100

85
(1 )-30
(2)+(5)-20

90

75

t to 10RO t Delay

110

85

t to 10RO +Delay

100

85

110

85

100

85

t to RD t Delay

130

95

Clock

t to RD t Delay

100

85

TdCf(Rr)

Clock

t to RD t Delay

110

85

34

TdCr(Wf)

Clock

t to WR

80

65

35

TdCf(Wf)

Clock

*36

Clock

t
t

Delay

90

80

TdCr(Wr)

t to WR Delay
Clock t to WR t Delay

100

80

37

TdCf(Wr)

Clock

t to WR t Delay

100

80

38

TwWI

WR Low Pulse Width

39

TsWA(Cf)

WAIT to Clock

40

TdCr(B)

Clock

t to BUSRO Delay

100

100

41

TdCr(lz)

Clock

t to 10RO, MREO, RD, WR Float Delay

100

80

(1 )-40

t Setup

(1 )-30

70

NOTES:
1.
Numbers in parentheses are other parameter-numbers in this table; their
values should be substituted in equations.
All equations imply DMA default (standard) timing.
2.

70

3. Data must be enabled onto data bus when RD is active.
4. Asterisk(") before parameter number means the parameter is not illustrated
in the AC Timing Diagrams.

VII-40

INACTIVE STATE CHARACTERISTICS
Figure 21

ClK

RD

Ml

lEI

lEO

INT

INTERRUPT
CONDITION _ _ _ _ _ _ _ _ _ _ _ _ _-',

BAI

BAO

•

ACTIVE STATE CHARACTERISTICS
Figure 22

elK

°0·°7

MEMORY CYCLE

I

INPUT

OUTPUT

MREO

RD

WR

1/0 CYCLE

lORa

RD

WR

WAIT

BUSRO

VII-41

ORDERING INFORMATION

PART NO.

PACKAGE TYPE

MK3883N
MK3883P

Z80-0MA Plastic
Z80-0MA Ceramic

2.5 MHz
2.5 MHz

O°C to +70°C
O°C to +70°C

MK3883N-10
MK3883P-10

Z80-0MA Plastic
Z80-0MA Ceramic

2.5 MHz
2.5 MHz

-40°C to +85°C
-40°C to +85°C

MK3883N-4
MK3883P-4

Z80A-OMA Plastic
Z80A-OMA Ceramic

MAX CLOCK FREQUENCY TEMPERATURE RANGE

4MHz
4MHz

VII·42

O°C to +70°C
O°C to +70°C

I!I

UNITED
TECHNOLOGIES
MOSTEK.

MICROCOMPUTER
COMPONENTS

SERIAL INPUT/OUTPUT CONTROLLER
MK3884/517/SIO
FEATURES

DESCRIPTION

o

The MK3884 Z80 510 Serial Input/Output Controller is
a dual-channel data communication interface with
extraordinary versatility and capability. Its basic
functions as a serial-to-parallel, parallel-to-serial converter/controller can be programmed by a CPU for a
broad range of serial communication applications.

Two independent full-duplex channels, with
separate control and status lines for modems or other
devices.

o Data rates of 0 to 500K bits/second in the x1 clock
mode with a 2.5MHz clock (MK3884 Z80 510), or 0 to
800K bits/second with a 4.0MHz clock (MK3884-4
Z80SI0).

o

Asynchronous protocols: everything necessary for
complete messages in 5, 6, 7 or 8 bits/character.
Includes variable stop bits and several clock-rate
multipliers; break generation and detection; parity;
overrun and framing error detection.

o Synchronous protocols: everything necessary for
complete bit- or byte-oriented messages in 5, 6, 7 or 8
bits/character, including IBM Bisync, SDLC, HDLC,
CCITI -X.25 and others. Automatic CRC generation/checking, sync character and zero insertion/deletion, abort generation/detection and flag
insertion.

o

Receiver data registers quadruply buffered,
transmitter registers doubly buffered.

o Highly sophisticated and flexible daisy-chain
interrupt vectoring for interrupts without external
logic.

The device supports all common asynchronous and
synchronous protocols, byte- or bit-oriented, and
performs all of the functions traditionally done by
UARTs, USARTs and synchronous communication
controllers combined, plus additional functions
traditionally performed by the CPU. Moreover, it does
this on two fully-independent channels, with an
exceptionally sophisticated interrupt structure that
allows very fast transfers.
Full interfacing is provided for CPU or DMA control. In
addition to data communication, the circuit can handle
virtually all types of serial I/O with fast (or slow)
peripheral devices. While designed primarily as a
member of the Z80 family, its versatility makes it well
suited to many other CPUs.
TheZ80 510 is an n-channel silicon-gate depletion-load
device packaged in a 40-pin plastic, or ceramic DIP. It
uses a single +5V power supply and the standard Z80
family single-phase clock.

MK3884 Z80 510
PIN ASSIGNMENTS

MK3884 Z80 510 PIN FUNCTIONS
Figure 1

Figure 2

01
03
Os
07

CPU
DATA
BUS

iNT
lEI

CHANNEL A

lEO

I

MOOEM
CONTROL

CHANNEL B

I

MOOEM
CONTROl

+SV GNO ClK

04
06

iOiiQ

CE
BIA
C/o

+5V

Ri5
GNO

R.OA

W7ii'6V'B
SYNcB

R.CA
TxCA

RxTxCB

R.OB

T.OA

T.08

5i'RA
iii'SA

i5'i'RB

CTs'A
DCoA

Ci"S'B
6C5i

ClK

VII-43

O2

M1
W7ii"6Y'A
SVNEA

CONTROL
FROM
CPU

DO

iffiij

RES'E'f

•

PIN DESCRIPTIONS

the CPU during a read cycle.

FiglJ.res 1 through 6 illustrate the three pin configurations (bonding options) available in the 510. The
constraints of a 40-pin package make it impossible to
bring out the Receive Clock (RxC), Transmit Clock (~),
Data Terminal Ready (i5iR) and Sync (SYNC) signals for
both channels. Therefore, either Channel B lacks a
signal or two signals are bonded together in the three
bonding options offered:

ClK. System Clock (input). The 510 uses the standard
l80 System Clock to synchronize internal signals. This

•
•
•

MK3887 l80 510 lacks SYNCB
MK3885 l80 510 lacks DTRB
MK3884 l80 510 has all four signals, but iXCB and
RxCB are bonded together

is a single-phase clock.
CTSA, CTSB. Clear To Send (inputs, active Low).
When programmed as Auto Enables, a Low on these
inputs enables the respective transmitter. If not
programmed as Auto Enables, these inputs may be
programmed as general-purpose inputs. Both inputs
are Schmitt-trigger buffered to accommodate slowrisetime signals. The 510 detects pulses on these inputs
and interrupts the CPU on both logic level transitions.
The Schmitt-trigger buffering does not guarantee a
specified noise-level margin.

The pin descriptions are as follows:
B/A. Channel A Or B Select (input, High selects
Channel B). This input defines which channel is
accessed during a data transfer between the CPU and
the 510. Address bit AO from the CPU is often used for
the selection function.
C/o. Control Or Data Select (input, High selects
Control). This input defines the type of information
transfer performed between the CPU and the 510. A
High at this input during a CPU write to the 510 causes
the information on the data bus to be interpreted as a
command for the channel selected by B/A. A Low at
C/O' means that the information on the data bus is data.
Address bit A1 is often used for this function.
CEo Chip Enable (Input, active Low). A Low level at this
input enables the 510 to accept command or data input
from the CPU during a write cycle, or to transmit data to

00-07' System Data Bus (bidirectional, 3-state). The
system data bus transfers data and commands between
the CPU and the l80 510. DO is the least significant bit.
DCDA, DCDB. Data Carrier Detect (inputs, active
Low). These pins function as receiver enables if the 510
is programmed for Auto Enables; otherwise they may be
used as general-purpose input pins. Both pins are
Schmitt-trigger buffered to accommodate slowrisetime signals. The 510 detects pulses on these pins
and interrupts the CPU on both logic level transitions.
Schmitt-trigger buffering does not guarantee a specific
noise-level margin.
DTRA, DTRB. Data Terminal Ready (outputs, active
Low). These outputs follow the state programmed into
laO 510. They can also be programmed as generalpurpose outputs.
In the MK3885 bonding option, DTRB-is omitted.

MK3885 Z80 SIO PIN FUNCTIONS

MK3885 l80 SIO PIN ASSIGNMENTS

Figure 3

Figure 4

0,

DO

03

O2

Os

04
06

07

CPU
DATA
BUS

lEI

'iOii'O
CE

lEO

B/A

iNT
CHANNEL A

!

MOOEM
CONTROL

Mi

C/O

Ri5
w/RoyA

~
RxOA

I

CHANNEl B

IMOOEM
\CONTROl

R.OB

TxCA

RxCii
TxCii

TxOA

i5Ci5A
ClK

VII-44

SYNCB

RxCA

Di'RA
'i'i'fSA
CTSA

+SV GNO ClK

GNO

'W7'iffiVii

TxOB

iffiij

CTSB
OCOB

RESET

lEI. Interrupt Enable In (input. active High). This signal
is used with lEO to form a priority daisy chain when
there is more than one interrupt-driven device. A High
on this line indicates that no other device of higher
priority is being serviced by a CPU interrupt service
routine.
lEO. Interrupt Enable Out (output. active High). lEO is
High only if lEI is High and the CPU is not servicing an
interrupt from this SIO. Thus. this signal blocks lower
priority devices from interrupting while a higher priority
device is being serviced by its CPU interrupt service
routine.
INT. Interrupt Request (output. open drain. active Low).
When the SIO is requesting an interrupt. it pulls iNi
Low.
lORa. InputlOutput Request (input from CPU, active
Low). 10RO is used in conjunction with B/A. C/O. CE
and RD to transfer commands and data between the
CPU and the SIO. When"CE. RD and 10RO are all active.
the channel selected by BIA transfers data to the CPU (a
read operation). When CE and 10RO are active. but RD is
inactive. the channel selected by BIA is written to by the
CPU with either data or control information as specified
by C/O. As mentioned previously. if 10RO and M 1 are
active simultaneously. the CPU is acknowledging an
interrupt and the SIO automatically places its interrupt
vector on the CPU data bus if it is the highest priority
device requesting an interrupt.
M1. Machine Cycle (input from zao CPU, active Low).
When M1 is active and RD is also active. theZaO CPU is
fetching an instruction from memory; when M1 is active
while 10RO is active. the SIO accepts M1 and 10RO as

an interrupt acknowledge if the SIO is the highest
priority device that has interrupted the Z80 CPU.
RxCA, RxClJ. Receiver Clocks (inputs). Receive data is
sampled on the riSing edge of RiC. The Receive Clocks
may be 1. 16. 32 or 64 times the data rate in
asynchronous modes. These clocks may be driven by
the zao CTC Counter Timer Circuit for programmable
baud rate generation. Both inputs are Schmitt-trigger
buffered (no noise level margin is specified).
In the MK3aa4 bonding option. RxCB is bonded together
with TxCB.
RD. Read Cycle Status (input from CPU. active Low). If
RD is active. a memory or 1/0 read operation is in
progress. RD is used with BIA, CE and 10RO to transfer
data from the SIO to the CPU.
RxDA, RxDB. Receive Data (inputs. active High).
Serial data at TTL levels.
RESET. Reset (input. active Low). A Low RESET
disables both receivers and transmitters, forces TxDA
and TxDB marking, forces the modem controls High and
disables all interrupts. The control registers must be
rewritten after the SIO is reset and before data is
transmitted or received.
RTSA, RTSB. Request To Send (outputs, active Low).
When the RTS bit in Write Register 5 (Figure 14) is set.
the RTS output goes Low. When the RTS bit is reset in
the Asynchronous mode. the output goes High after the
transmitter is empty. In Synchronous modes. the RTS
pin strictly follows the state of the RTS bit. Both pins can
be used as general-purpose outputs.

MK3887 zao SIO PIN FUNCTIONS

MK3aa7 zao SIO PIN ASSIGNMENTS

Figure 5

Figure 6

0,
03
06
07

TNT
CHANNEl A

lEI

I

MOOEM
CONTROL

BiA'
C/o

SYNCA

CHANNElB

I

MOOEM
CONTROl

+5V GNO ClK

VII-4S

lORa

Ce

M;
+6V

CPU

04

06

lEO

W7RDvA

CONTROL
FROM

DO

°2

R5
GNO

WIiiDvi

RxOA

RxOB

ibcA

RxCa

hCA

TxCB

TxOA

TxOB

DTRA
RT5A

iiTSa

OTRB

CTsA

ern

i5CDA

DCffii

ClK

REm

•

SYN1!A, SYN'C"B".

Synchronization (inputs/outputs,
active Low). These pins can act either as inputs or
outputs. In the asynchronous receive mode, they are
inputs similar to CTS and DCl5'. In this mode, the
transitions on these lines affect the state of the Sync/Hunt status bit in Read Register 0 (Figure 13), but have
no other function. In the External Sync mode, these
lines also act as inputs. When external synchronization
is achieved, SYNC must be driven Low on the second
rising edge ofl1X'C' after that rising edge of11xC"on which
the last bit of the sync character was received. In other
words, after the sync pattern is detected, the external
logic must wait for two full Receive Clock cycles to
activate the SYNC input. Once SYNC is forced Low, it
should be kept Low until the CPU informs the external
synchronization detect logic that synchronization has
been lost or a new message is about to start. Character
assembly begins on the rising edge of"RXC that
immediately precedes the falling edge of SYNC in the
External Sync mode.

rate generation.
In the MK3884 bonding option, TxCB is bonded together
with l1xCI3.
TxDA, TxDB. Transmit Data (outputs, active High).
Serial data at TTL levels.
W/RDYA, W/RDYB. Wait/Ready A. Wait/Ready B
(outputs, open drain, when programmed for Wait
function; driven High and Low when programmed for
Ready function). These dual-purpose outputs may be
programmed as Ready lines for a DMA controller or as
Wait lines that synchronize the CPU to the 510 data rate.
The reset state is open drain.

In the internal synchronization mode (Monosync and
Bisync), these pins act as outputs that are active during
the part of the receive clock (RxC) cycle in which sync
characters are recognized. The sync condition is not
latched, so these outputs are active each time a sync
pattern is recognized, regardless of character
boundaries.
In the MK3887 bonding option, SYNCB is omitted.

FUNCTIONAL CAPABILITIES
The functional capabilities of the Z80 510 can be
described from two different points of view: as a data
communications device, it transmits and receives serial
data in a wide variety of data-communication protocols;
as a Z80 family peripheral, it interacts with the Z80 CPU
and other peripheral circuits, sharing the data, address
and control buses, as well as being a part of the Z80
interrupt structure. As a peripheral to other microprocessors, the 510 offers valuable features such as nonvectored interrupts, polling and simple handshake
capability.
Figure 8 illustrates the conventional devices that the
SIO replaces.

TxCA, TxCB. Transmitter Clocks (inputs). TxD changes
from the falling edge of TxC. In asynchrono~s modes,
the Transmitter Clocks may be 1, 16, 32 or 64 times the
data rate; however, the clock multiplier for the transmitter and the receiver must be the same. The Transmit
Clock inputs are Schmitt-trigger buffered for relaxed
rise- and fall-time requirements (no noise level margin
is specified). Transmitter Clocks may be driven by the
Z80 CTC Counter Timer Circuit for programmable baud

The first part of the following discussion covers SIO
data-communication capabilities; the second part
describes interactions between the CPU and the SIO.
DATA COMMUNICATION CAPABILITIES
The SIO provides two independent full-duplex channels
that can be programmed for use in any common
asynchronous or synchronous data-communication

BLOCK DIAGRAM
Figure 7
~

SERIAL DATA

J CHANNEL CLOCKS
SYNC
WAIT/READY

INTERNAL
CONTROL
lOGIC

MODEM OR
} OTHER CONTROLS
DATA
CPU
BUS I/O

CONTROl~......._~
INTERRUPT
CONTROL
LINES

MODEM OR
} OTHER CONTROLS
INTERRUPT
CONTROL
lOGIC

B
CHANNElB

VII-46

~ SERIAL DATA
~CHANNElClOCKS

.m:c.__

WAIT/READY

CONVENTIONAL DEVICES REPLACED BY THE Z80 510
Figure 8

CHANNEL

A

MICROPROCESSOR
INTERFACE

CHANNEL

B

MICROPROCESSOR
INTERFACE

ti
ZBO
SIO

CHANNEL
A
CHANNEL
B

protocol. Figure 9 illustrates some of these protocols.
The following is a short description of them. A more
detailed explanation of these modes can be found in the
MK3884 Z80 510 Technical Manual.

receive and transmit clock inputs. In asynchronous
modes, the SYNC pin may be programmed as an input
that can be used for functions such as monitoring a ring
indicator.

Asynchronous Modes. Transmission and reception
can be done independently on each channel with five to
eight bits per character, plus optional even or odd parity.
The transmitters can supply one, one-and-a-half or two
stop bits per character and can provide a break output at
any time. The receiver break-detection logic interrupts
the CPU both at the start and end of a received break.
Reception is protected from spikes by a transient spikerejection mechanism that checks the signal one-half a
bit time after a Low level is detected on the receive data
input (RxOA or RxOB in Figure 5). If the Low does not
persist-as in the case of a transient-the character
assembly process is not started.

Synchronous Modes. The 510 supports both byteoriented and bit-oriented synchronous communication.
Synchronous byte-oriented protocols can be handled in
several modes that allow character synchronization
with an 8-bit sync character (Monosync), any 16-bit
sync pattern (Bisync) or with an external sync signal.
Leading sync characters can be removed without
interrupting the CPU.

Framing errors and overrun errors are detected and
buffered together with the partial character on which
they occurred. Vectored interrupts allow fast servicing
of error conditions using dedicated routines. Furthermore, a built-in checking process avoids interpreting a
framing error as a new start bit: a framing error results
in the addition of one-half a bit time to the point at which
the search for the next start bit is begun.
The 510 does not require symmetric transmit and
receive clock signals-a feature that allows it to be used
with MK3882 Z80 CTC or many other clock sources. The
transmitter and receiver can handle data at a rate of 1,
1/16, 1/32 or 1/64 of the clock rate supplied to the

Five-, six- or seven-bit sync characters are detected
with 8- or 16-bit patterns in the 510 by overlapping the
larger pattern across multiple in-coming sync
characters, as shown in Figure 10.
CRC checking for synchronous byte-oriented modes is
delayed by one character time so the CPU. may disable
CRC checking on specific characters. This permits
implementation of protocols such as IBM Bisync.
Both CRC-16 (X 1e + X15 + X2 + 1) and CCITI (Xle + X12 +
X5 +1) error checking polynomials are supported. In all
non-SOLC modes, the CRC generator is initialized to D's;
in SOLC modes, it is initialized to 1 'so The 510 can be
used for interfacing to peripherals such as hard-sectored floppy disk, but it cannot generate or check
CRC for IBM-compatible soft-sectored disks. The 510
also provides a feature that automatically transmits
CRC data when no other data is available for transmission. This allows very high-speed transmissions under

VII-47

•

The 510 can be conveniently used under DMAcontrol to
provide high-speed reception or transmission. In
reception, for example, the 510 can interrupt the CPU
when the first character of a message is received. The
CPU then enables the DMA to transfer the message to
memory. The 510 then issues an endcof-frame interrupt
and the CPU can check the status of the received
message. Thus, the CPU is freed for other service while
the message is being received.

DMA control with no need for CPU intervention at the
end of a message. When there is no data or CRC to send
in synchronous modes, the transmitter inserts 8- or
16-bit sync characters regardless of the programmed
character length.
The 510 supports synchronous bit-oriented protocols
such as SDLC and HDLC by performing automatic flag
sending, zero insertion and CRC generation. A special
command can be used to abort a frame in transmission.
At the end of a message the 510 automatically transmits
the CRe and trailing flag when the transmit buffer
becomes empty. If a transmit underrun occurs in the
middle of a message, an externallstatus interrupt
warns the CPU of this status change so that an abort
may be issued. One to eight bits per character can be
sent, which allows reception of a message with no prior
information about the character structure in the information field of a frame.

1/0 INTERFACE CAPABILITIES
The 510 offers the choice of polling, interrupt (vectored
or non-vectored) and block-transfer modes to transfer
data, status and control information to and from the
CPU. The block-transfer mode can also be implemented
under DMA control.
Polling. Two status registers are updated at
appropriate times for each function being performed (for
example, CRC error-status valid at the end of a
message). When the CPU is operated in a polling
fashion, one of the SIO's two status registers is used to
indicate whether the 510 has some data or needs some
data. Depending on the contents of this register, the
CPU will either write data, read data, or just go on. Two
bits in the register indicate that a data transfer is
needed. In addition, error and other conditions are
indicated. The second status register (special receive
conditions) does not have to be read in a polling
sequence, until a character has been received. All
interrupt modes are disabled when operating the device
in a polled environment.

The receiver automatically synchronizes on the leading
flag of a frame in SDLC or HOLC, and provides a
synchronization signal on the SYNC pin; an interrupt
can also be programmed. The receiver can be
programmed to search for frames addressed by a single
byte to only a specified user-selected address or to a
global broadcast address. In this mode, frames that do
not match either the user-selected or broadcast address
are ignored. The number of address bytes can be
extended under software control. For transmitting data,
an interrupt on the first received character or on every
character can be selected. The receiver automatically
deletes all zeroes inserted by the transmitter during
character assembly. It also calculates and auto'matically
checks the CRC to validate frame transmission. At the
end of transmission, the status of a received frame is
available in the status registers.

Interrupts. The 510 has an elaborate interrupt scheme
to provide fast interrupt service in real-time applications. A control register and a status register in Channel
B contain the interrupt vector. When programmed to do

Z80 SID PROTOCOLS
Figure 9

PARITY

START
I STOP
____~
t
MARKING LINE
Ll§@ I ~ II DATA II '

* . . .----.-.-... __....,--.--_
i

'MARKING LINE

ASYNCRONOUS

I

SYNC

I

DATA

::
;:
:;

I

I

I

CRC,

I

DATA

I

CRC,

I CRC21

DATA

I

CRC,

I

CRC,

I

DATA

CRc 2 1

MONOSYNC

I

SYNC

I

SYNC
DATA
SIGNAL

Ii

DATA

I

I

BISYNC

I

I

CRC2

I

EXTERNAL SYNC
_F_LA_G--&.IA_D_D_R_ES_s-LI_ _ _IN_F_0-4iiATION

FLAG

SDlC/HDlC/X.25

VARIABLE LENGTH SYNC CHARACTERS
Figure 10
6 BITS
DATA
8

'6
VII-48

DATA

DATA

DATA

I

so, the 510 can modify three bits of the interrupt vector
in the status register so that it points directly to one of
eight interrupt service routines in memory, thereby
servicing conditions in both channels and eliminating
most of the needs for a status-analysis routine.
Transmit interrupts, receive interrupts and external/status interrupts are the main sources of interrupts.
Each interrupt source is enabled under program control,
with Channel A having a higher priority than Channel B,
and with receive, transmit and external/status
interrupts prioritized in that order within each channel.
When the transmit interrupt is enabled, the CPU is
interrupted by the transmit buffer becoming empty.
(This implies that the transmitter must have had a data
character written into it so it can become empty.) The
receiver can interrupt the CPU in one of two ways:

interrupt routine itself.
CPU/DMA Block Transfer. The SIO's block-transfer
mode accommodates both CPU block transfers and
OMA controllers (ZaO OMA or other designs). The blocktransfer mode uses the Wait/Ready output signal,
which is selected with three bits in an internal control
register. The Wait/Ready output signal can be programmedWAIlline in the CPU block-transfer mode or
as a READY line in the OMA block-transfer mode.
To a OMA controller, the 510 'i1EAl5'V output indicates
that the 510 is ready to transfer data to or from memory.
To the CPU, the WAIT output indicates that the 510 is
not ready to transfer data, thereby requesting the CPU to
extend the I/O cycle.
TYPICAL zao ENVIRONMENT

• Interrupt on first received character
• Interrupt on all received characters

Figure 11

Interrupt-on-first-received-character is typically used
with the block-transfer mode. Interrupt-on-allreceived-characters has the option of modifying the
interrupt vector in the event of a parity error. Both of
these interrupt modes will also interrupt under special
receive conditions on a character or message basis
(end-of-frame interrupt in SOLC, for example). This
means that the special-receive condition can cause an
interrupt only if the interrupt-on-first-received-character or interrupt-on-all-received-characters mode
is selected. In interrupt-on-first-received-character, an
interrupt can occur from special-receive conditions
(except parity error) after the first-received-character
interrupt (example: receive-overrun interrupt).

A.

..A

fr--,I

,....

OMA

iNT
ROY
lEI

~

lEO

iNT

The main function of the external/status interrupt is to
monitor the signal transitions of the Clear To Send
(CTS), Data Carrier Detect (OCO) and Synchronization
(SYNC) pins (Figures 1 through 6). In addition, an
external/status interrupt is also caused by a CRCsending condition or by the detection of a break
sequence (asynchronous mode) or abort sequence
(SOLC mode) in the data stream. The interrupt caused by
the break/abort sequence allows the 510 to interrupt
when the break/abort sequence is detected or
terminated. This feature facilitates the proper termination of the current message, correct initialization of the
next message, and the accurate timing of the break/abort condition in external logic.
In a zao CPU environment (Figure 11), 510 interrupt
vectoring is "automatic": the 510 passes its internallymodifiable a-bit interrupt vector to the CPU, which adds
an additional a bits from its interrupt-vector (I) register
to form the memory address of the interrupt-routine
table. This table contai ns the address of the beginning of
the interrupt routine itself. The process entails an
indirect transfer of CPU control to the interrupt routine,
so that the next instruction executed after an interrupt
acknowledge by the CPU is the first instruction of the

--- lEI

r-IA.
IV

ROY
DMA

.A
y

ARCHITECTURE
DESCRIPTION
The internal structure of the device includes a zao CPU
interface, internal control and interrupt logic, and two
full-duplex channels. Each channel contains its own set
of control and status (write and read) registers, and
control and status logic that provides the interface to
modems or other external devices.
The registers for each channel are designated as
follows:
WRO-WR7 - Write Registers 0 through 7
RRO-RR2 - Read Registers 0 through 2
The register group includes five 8-bit control registers,

VII-49

•

two sync-character registers and two status registers.
The interrupt vector is written into an additional a-bit
register (Write Register 2) in Channel B that may be read
through another a-bit register (Read Register 2) in
Channel B. The bit assignment and functional grouping
of each register is configured to simplify and organize
the programming process. Table 1 lists the functions
aSSigned to each read or write register.

The logic for both channels provides formats,
synchronization and validation for data transferred to
and from the channel interface. The modem control
inputs, Clear To Send (CTS) and Data Carrier Detect
(DCD), are monitored by the external control and status
logic under program control. All external
control-and-status-Iogic signals are general-purpose in
nature and can be used for functions other than modem
control.

Read Register Functions

Data Path. The transmit and receive data path
illustrated for Channel A in Figure 12 is identical for
both channels. The receiver has three a-bit buffer
registers in a FIFO arrangement. in addition to the a-bit
receive shift register. This scheme creates additional
time for the CPU to service an interrupt at the beginning
of a block of high-speed data. Incoming data is routed
through one of several paths (data or CRC) depending on
the selected mode and-in asynchronous modes-the
character length.

RRO
RR1
RR2

Transmit/Receive buffer status, interrupt
status and external status
Specia I Receive Condition status
Modified interrupt vector (Channel B only)

Write Register Functions

WRO
WR1

WR2
WR3
WR4
WR5
WR6
WR7

Register pointers, CRC initialize, initialization
commands for the various modes, etc.
Transmit/Receive interrupt and data transfer
mode definition.
Interrupt vector (Channel B only)

The transmitter has an a-bit transmit data buffer
register that is loaded from the internal data bus, and a
20-bit transmit shift register that can be loaded from the
sync-character buffers or from the transmit data
register. Depending on the operational mode, outgoing
data is routed through one of four main paths before it is
transmitted from the Transmit Data output (TxD).

Receive parameters and control
Transmit/Receive miscellaneous parameters
and modes
Transmit parameters and controls
Sync character or SDLC address field
Sync character or SDLC flag

The system program first issues a series of commands
that initialize the basic mode of operation and then other
commands that qualify conditions within the selected

C~PU
I/O

TRANSMIT AND RECEIVE DATA PATH (CHANNEL A)
Figure 12

_

11/0

DATA BUFFERI

TOCHANNELB----------------------------~~------------------------------

EXTERNAL STATUS LOGIC
CONTROL LOGIC, ETC.

INTERNAL DATA BUS

r--------.,

TxDA

RxDA

VII-50

mode. For example, the asynchronous mode, character
length, clock rate, number of stop bits, even or odd parity
might be set first; then the interrupt mode; and finally,
receiver or transmitter enable.
Both channels contain registers that must be
programmed via the system program prior to operation.
The channel-select input (B/A) and the control/data
input (C/O) are the command-structure addressing
controls, and are normally controlled by the CPU
address bus. Figures 15 and 16 illustrate the timing
relationships for programming the write registers and
transferring data and status.
Read Registers. The SIO contains three read registers
for Channel B and two read registers for Channel A
(RRO-RR2 in Figure 13) that can be read to obtain the
status information; RR2 contains the internally-modifiable interrupt vector and is only in the Channel B
register set. The status information includes error
conditions, interrupt vector and standard
communications-interface Signals.
To read the contents of a selected read register other
than RRO, the system program must first write the
pointer byte to WRO in exactly the same way as a write
register operation. Then, by executing a read
instruction, the contents of the addressed read register
can be read by the CPU.

The status bits of RRO and RR1 are carefully grouped to
simplify status monitoring. For example, when the
interrupt vector indicates that a Special Receive Condition interrupt has occured, all the appropriate error bits
can be read from a Single register (RR1).
Write Registers. The SIO contains eight write registers
for Channel B and seven write registers for Channel A
(WRO-WR7 in Figure 14) that are programmed
separately to configure the functional personality of the
channels; WR2 contains the interrupt vector for both
channels and is only in the Channel B register set. With
the exception of WRO, programming the write registers
requires two bytes. The first byte is to WRO and contains
three bits (00-02) that point to the selected register; the
second byte is the actual control word that is written
into the register to configure the SIO.
WRO is a special case in that all of the basic commands
can be written to it with a single byte. Reset (internal or
external) initializes the pointer bits 00-02 to point to
WRO. This implies that a channel reset must always
point to WRO.
The SIO must have the same clock as the CPU (same
phase and frequency relationship, not necessarily the
same driver).

READ REGISTER BIT FUNCTIONS
Figure 13
READ REGISTER 0

READ REGISTER 2
'Used With External/Status
Interrupt Mode

lUI~
L-~i:

READ REGISTER 1

1071061051041031021011001

r..-_ _ _ _ _ _ _ _ _
L-ALLSENT

1
0
1
0
1
0
1
0

0
1
1
0
0
1
1
0

I FIELD BITS
IN PREVIOUS
BYTE

I FIELD BITS IN
SECOND PREVIOUS
BYTE

0
0
0
0
0
0
1
2

3
4
5
6
7
8
8
8

0
0
0

1
1
1
1
0

PARITY ERROR

10.-_ _ _

~~gy~::~~~RE~~'6R

'Residue Data For Eight
Rx Bits/Character Programmed

_ _ _ _ _ _ END OF FRAME (SOLC)
Used With Special Receive Condition Mode

VII-51

'Variable if Status Affects
Vector is Programmed

~~

INTERRUPT
VECTOR

•

WRITE REGISTER BIT FUNCTIONS
Figure 14

WRITE REGISTER 0

WRITE REGISTER 4

107'0810111041031021011001

I I

o
o
o
o

I
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER

1
1
1
1

o
o
1
1

o
o
1
1

o
1

o
1

0
1
0
1
0
1
0
1

0
1
2
3
4
II
8
7

SYNC MODES ENABLE
1 STOP BIT/CHARACTER
1V2 STOP BITS/CHARACTER
2 STOP BITS/CHARACTER
B BIT SYNC CHARACTER
18 BIT SYNC CHARACTER
SOLC MOOE (01111110 FLAG)
EXTERNAL SYNC MODE

NULLCOOE
SENO ABORT (SOLC)
RESET EXT/STATUS INTERRUPTS
CHANNEL RESET
ENABLE INT ON NEXT Rx CHARACTER
RESET TxlNT PENOING
ERROR RESET
RETURN FROM INT (CH-A ONLY)

X1 CLOCK MOOE
X1S CLOCK MODE
X32 CLOCK MODE
X84 CLOCK MODE

NULL CODE
RESET Rx CRC CHECKER
RESET Tx CRC GENERATOR
RESET Tx UNOERRUN/EOM LATCH

WRITE REGISTER II

WRITE REGISTER 1
1071081051041031021011001

III

I

1
EXT INT ENABLE
Tx INT ENABLE
...- - - - STATUS AFFECTS VECTOR
(CH_ BONLY)

Rx INT OISABLE
\
Rx INT ON FIRST CHARACTER
INT ON ALL Rx CHARACTERS (PARITY AFFECTS VECTOR)
•
INT ON ALL Rx CHARACTERS (PARITY DOES NOT AFFECT VECTOR)

WAIT /REAOY ON R/T
WAIT/READY FUNCTION
L...----WAIT /REAOY ENABLE

'drOn

Tx 5
Tx 7
Tx 6
Tx 8

BITS (OR LESS)/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER

OTR

Spe~i.1

Condition

WRITE REGISTER 2 (CHANNEL B ONLY)

WRITE REGISTER 8

riTiTTD~
~V4~ \

INTERRUPT
VECTOR

VII
V8
V7

'Also SOLC Address Field

WRITE REGISTER 3

IIII

WRITE REGISTER 7

10 71 Osl 061 0 41 0 310 21 011001

o
o
1

1

Rx 6
Rx 7
Rx 8
Rx B

~

IL.::=
L-".,
SYNC
...CHARACTER LOAD INHIBIT
ADDRESS SEARCH MOOE ISOLC)
Rx CRC ENABLE
ENTER HUNT PHASE
AUTO ENABLES

BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER

'For SOLC It Must Be Programmed
to "01111110" For Flag Recognition

VII-52

Read Cycle. The timing signals generated by a zao
CPU input instruction to read a data or status byte from
the SIO are illustrated in Figure 15.
Write Cycle. Figure 16 illustrates the timing and data
signals generated by a zao CPU output instruction to
write a data or control byte into the SIO.
Interrupt-Acknowledge Cycle. After receiving an interrupt-request signal from an SIO (INT pulled Low), the zao
CPU sends an interrupt-acknowledge sequence (M1
Low, and 10RO Low a few cycles later) as in Figure 17.
The SIO contains an internal daisy-chained interrupt
structure for prioritizing nested interrupts for the
various functions of its two channels, and this structure
can be used within an external user-defined daisy chain
that prioritizes several peripheral circuits.
The lEI ofthe highest-priority device is terminated High.
A device that has an interrupt pending or under service
forces its lEO Low. For devices with no interrupt
pending or under service, lEO = lEI.
To insure stable conditions in the daisy chain, all
interrupt status signals are prevented from changing
while M1 is Low. When 10RO is Low, the highest
priority interrupt requestor (the one with lEI High) places
its interrupt vector on the data bus and sets its internal
intElrrupt- under-service latch.

READ CYCLE

Return From Interrupt Cycle. Figure 1a illustrates the
return from interrupt cycle. Normally, the zao CPU
issues a RETI (return from interrupt) instruction at the
end of an interrupt service routine. RETI is a 2-byte
opcode (EO-40) that resets the interrupt-under-service
latch in the SIO to terminate the interrupt that has just
been processed. This is accomplished by manipulating
the daisy chain in the following way.
The normal daisy-chain operation can be used to detect
a pending interrupt; however, it cannot distinguish
between an interrupt under service and a pending
unacknowledged interrupt of a higher priority.
Whenever "EO" is decoded, the daisy chain is modified
by forcing High the lEO of any interrupt that has not yet
been acknowledged. Thus the daisy chain identifies the
device presently under service as the only one with an
lEI High and an lEO Low. Ifthe next opcode byte is "40",
the interrupt-under-service latch is reset.
The ripple time of the interrupt daisy chain (both the
High-to-Low and the Low-to-High transitions) limits the
number of devices that can be placed in the daisy chain.
Ripple time can be improved with carry-look-ahead, or
by extending the interrupt-acknowledge cycle. For
further information about techniques for increasing the
number of daisy-chained devices, refer to the MK3aaO
zao CPU Product Specification.

INTERRUPT ACKNOWLEDGE CYCLE

Figure 15
T1

Figure 17
CLOCK

CLOCK

I

CE, C/o,

BI

I

M1~~_____________________~I/

A _ _.-J.'"'+_ _ _+-___- J

I

~

lORa

R5------------------~I~-------

RD
M1

--------------+-----------

lEI

:::::::::7

I

:\:::::

DATA ---------~ECTO'~--

DATA-------------~

WRITE CYCLE

RETURN FROM INTERRUPT CYCLE

Figure 16

Figure 18

CLOCK

o'd;,,'
lORa

~Tl
T2
TW
T3
T,

~
~

RD

I

I

IEI----- _____ -.I I

M1-------------~I~------DATA _ _ _ _ _ _ _ _ _ _ _

I

.....J.i:r----

)@Y_______

lEO _ _ _ _ _ _ _ _ _

VII-53

II

ABSOLUTE MAXIMUM RATINGS
Voltages on all inputs and outputs with respect to GND ........................................... -0.3V to +7.0V
Operating Ambient Temperature ............................................ As Specified in Ordering Information
Storage Temperature ........................................................................ -65°C to +1.50°C
Stresses greeter than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation olthe device atany
condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.

STANDARD TEST CONDITIONS
The characteristics below apply for the following
standard test conditions, unless otherwise noted. All
voltages are referenced to GND. Positive current flows
into the referenced pin. Standard conditions are as
follows:

2.1 K

FROM OUTPUTo-_....._
UNDER TEST

• +4.75V::; VCC::; +5.25V
• GND = OV
• TA as specified in Ordering Information

.....-tII....

All AC parameters assume a load capacitance of 100 pF
max. Timing references between two output signals
assume a load difference of 50 pF max.

DC CHARACTERISTICS
SYM

PARAMETER

MIN

MAX

VILC

Clock Input Low Voltage

-0.3

+0.80

V

VIHC

Clock Input High Voltage

VCC -0.6

+5.5

V

VIL

Input Low Voltage

-0.3

+0.8

V

VIH

Input High Voltage

+2.0

+5.5

V

VOL

Output Low Voltage

+0.4

V

IOL

= 2.0mA

VOH

Output High Voltage

+2.4

V

IOH

= -250 p.A

III

Input Leakage Current

-10

±10

p.A

0< VIN < VCC

IZ

3-State Output/Data Bus Input
Leakage Current

-10

+10

p.A

0< VIN < VCC

IL(SY)

SYNC Pin Leakage Current

-40

+10

p.A

o j-----------'lt<;-""
T ROL

0

0 -0

7

-------------------------------------+------~

TSAR = Address Setup Time for a Read Cycle
T ORO = Data Output Delay from CERD
T ooz = Time to Tri-State Following a Read Cycle
T HAR = Required Address Hold Time Following a Read Cycle

V11-76

WRITE CYCLE
Figure 17

TSOW _ _ _~
~------------~

Tww = C'EWR High Time Between Writes
T SAW = Address Setup Time for a Write Cycle
T SOW = Data Setup Time Prior to the End of a Write Cycle
T HOW = Required Data Hold Time Following a Write Cycle
THAW = Required Address Hold Time Following a Write Cycle

14----THOW

•

TWM = CEWR pulse width low

INTERRUPT ACKNOWLEDGE CYCLE
Figure 18

Mi----_

TSM1
IORO-------------------------------~

Tooz

0 0 -0 7

------------------------------------------------------<

T
= I~O Pulse Width Low ___
'OL
T SMI = M1 Setup Time prior to lORa For an Acknowledge cycle
Tool = Access Time for Vector
T ooz = Time to Tri-State Following a Vector,
T OHVZ = Data hold time following M1 lORa during interrupt acknowledge cycle

vlI-n

TIMER A.C. CHARACTERISTICS
Definitions:
Error

= Indicated Time Value - Actual Time Value

tpsc = tCLK x Prescale Value
Internal Timer Mode
VCC +.:
Single Interval Error (free running) (Note 2) . " ............................. " .............. " ........ ± 100 ns
Cumulative Internal Error .............................................................................. " 0
Error Between Two Timer Reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± (tpsc + 4 t CLK )
Start Timer to Stop Timer Error ....................................... 2 tCLK + 100 ns to -(tpsc + 6tcLK + 100 ns)
Start Timer to Read Timer Error ................................................... 0 to -(tpsc + 6 tCLK + 400 ns)
Start Timer to Interrupt Request Error (Note 3) ........................................ -2 tCLK to -(4t CLK +800 ns)
Pulse Width Measurement Mode
Measurement Accuracy (Note 1) ....................................................... 2 tCLK to -(tpsc + 4t CLK )
Minimum Pulse Width ............................................................................... 4tCLK
Event Counter Mode
Minimum Active Time of 13, 14 •••.••••••.•••••.••.•••••••••••••••••••••..••..••...••••.••...•••.••••••• 4tCLK
Minimum Inactive Time of 13, 14 •••••..••••.•••••••••••••••••.••••.••••••••••..•••..••••••••••••.•••...• 4tCLK
NOTES:
1.
2.
3.

Error may be cumulative if repetitively performed.
Error with respect to TOUT or INT if note 3 is true.
Assuming it is possible for the timer to make an interrupt request
immediately.

ORDERING INFORMATION

PART NO.

DESIGNATOR

PACKAGE TYPE

MAX CLOCK
FREQUENCY

TEMPERATURE
RANGE

MK3801 N-O

Z80-STI

Plastic

2.5 MHz

MK3801 N-4

Z80-STI

Plastic

4.0 MHz

MK3801N-6

Z80-STI

Plastic

6.0 MHz

o to 70°C
o to 70°C
o to 70°C

V 11·78

1984/1985 MICROELECTRONIC DATA BOOK

Table of Contents

0...1 . . . . . . . . . "'"

Random ..Access Memory

3870 Single Chip Family

3870 FAMILY
SELECTION GUIDE

I

ROM DEVICES

MEMORY

I

I/O

I PKG·I

ADDRESS
RANGE

MISC.

I

/

2870/10

1K

64

0

20

No

28

12 bits

1K

No

3870/10

1K

64

0

32

No

40

12 Bits

1K

No

3870/20

2K

64

0

32

No

40

11 Bits
12 Bits

2K

No

(Note 2)

38C70/20

2K

64

0

32

No

40

16 Bits

2K

Halt
Mode

CMOS

3870/30

3K

64

0

32

No

40

12 Bits

3K

No

3870/40

4K

64

0

32

No

40

12 Bits

4K

No

64

32

No

40

12 Bits

4K

No

64

64

29

Yes

40

12 Bits ~K + 64

No

4032 64

64

30

No

40

12 Bits

Yes

3870/42
3873/22
3875/42

I

4032 64
2K

4K

II
Baud rate generator

Address externa I
Memory (EPROM)
through socket on top
of 40 pi n packa ge

P-PROM DEVICES
97300

o

64

64

29

Yes

40

12 Bits

4K

No

(38P73)

97310

o

64

64

29

Yes

40

12 Bits

4K

No

(38P73)

97400

64

64

32

No

40

12 Bits

4K

No

(38P70)

97403

o
o

64

64

30

No

40

12 Bits

4K

Yes

(38P75)

97410

o

64

64

32

No

40

12 Bits

4K

No

(38P70)

97500

o

64

64

32

No

40

16 Bits 8K +64

No

(38P70)

97501

o

64

64

32

No

40

16 Bits 8K +64

No

(38P70)

97502

o

64

64

32

No

40

16 Bits

No

(38P70)

NOTES:
1. Usable address range is the amount of memory that can effectively be
addressed. This may be less than the full range of the address registers
either because the amount of on-chip memory is less than the possible

VIII-1

64K

address range or, in the case of P-PROM devices, all address bits are not
externally available.
2. The original 3870 device (3870/20) has 11 bit address registers. Aversion is
now available with 12 bit address registers.

VIII-2

m

UNITED

TECHNOLOGIES
MOSTEK

MICROCOMPUTER
COMPONENTS
MK3870 AND MK38P70

MK3870 FEATURES

o Available with 1 K, 2K, or 4K bytes of mask
programmable ROM memory

o

64 bytes scratchpad RAM

o Available with 64 bytes executable RAM

o

32 bits (4 ports) TTL compatible I/O

o Programmable binary timer
Interval timer mode
Pu Ise width measurement mode
Event'counter mode

o

External interrupt input

o

Crystal, LC, RC, or external time base options

o

Low power (275 mW typ.)

MK3870 PIN CONNECTIONS
XTll ___

o

Single +5 volt supply

MK38P70 FEATURES

o

EPROM version of MK3870

o Piggyback PROM (P-PROMF M package
o Accepts 24 pin or 28 pin EPROM memories

o

Identical pinout as MK3870

o

In-Socket emulation of MK3870

,

40 -+- Vee

xn2_ 2

39-~

PO'O_

3

38 -

EXT INT

POT .........

4

37...........

P02-

5

36 ___

PiD
Pi1

6
7

35 - - 34 .......

P40"-'

8

33 - - ,,"0

P4i ........

9

32-

~1

P42 ........... 10

31 - - -

P52

P'4"3..--... "

30 - - -

P53

P44 ........... , 2

29_

~4

P45 .........

13

28_

~

P'4"64--+-

14

27 - - -

p:r-7 ...........

,5

25 -

P56
Ps7
Pi7

~6"""""

17

24 -

Pi6

PO"5 -

18
19

23-m

26 - - -

22_1Si4
21

The MK3870 is a complete 8-bit microcomputer on a single
MOS integrated circuit. The MK3870 can execute a set of
more than 70 instructions, and is completely software
compatible with the rest of the devices in the 3870 family.
The MK3870 features 1-4K bytes of ROM and optional
additional executable RAM depending on the specific part
type designated by a slash number suffix. The MK3870 also
features 64 bytes of scratchpad RAM, a programmable
binary timer, and 32 bits of 1/0.
The programmable binary timer operates by itself in the
interval timer mode or in conjunction with the external
interrupt input in the pulse width measurement and the

VIII-3

P'i1"'

150")-16

M4 .............

GENERAL DESCRIPTION

Pi"2

P03S"i"Rc5BE ___

XTll --...
XTL2 _

1
2

POCi_
POi ........

3
4

PO 2 ..........

5

~-6

P40Pi1 ........

P42 -

9
10

P43 ......... 11
P44 _
12
~_13

m_14
P47 _

15

P(J7 -

P06 __

16
17

P(JS -

18

_

TEST

40 ....-..-

Vee

3 9 - ~T
38 -

EXT INT

37 ..-..

'PUr

36 ___

PiT

35 _

Prr

34 _ _

p,3

33 - -

P50

32-~

31 -

P5"2

30_~

29 -

28 - - -

P54
P5S

27_~

26 -

1557

25 - -

Pi7

24-m
23-m

PO"4 - - - 19

22_1Si4

G N D - 20

21

_

TEST

•

EXTINT

MK3870 BLOCK DIAGRAM

F;gu~ IXl:~ocTI
1

MEMORY ADDRESS BUS

64 x8
EXECUTABLE
RAM

MAIN
CONTROL
LOGIC

RESULT BUS

TEST

1/0 (8)

1/0 (8)

1/0 (8)STRQEiE

1/0 (8)

FUNCTIONAL PIN DESCRIPTION

event counter modes of operation. Two sources of vectored,
prioritized interrupt are provided with the binary timer and
the external interrupt input. The user has the option of
specifying one of four clock sources for the MK3870 and
MK38P70: Crystal, LC, RC, or external clock. In addition, the
usercan specify either a ±1 0% power supply tolerance or a
±5% power supply tolerance.

PO-O-- PO-7, P1-0--P1-7, P4-0--P4-7, and P5-0--P5-7 are
32 lines which can be individually used as either TIL
compatible inputs or as latched outputs.

The MK38P70 microcomputer is the PROM based version
ofthe MK3870. It is called the piggyback PROM (P-PROM)TM
because of its packaging concept. This concept allows a
standard 24-pin or 28 pin EPROM to be mounted directly on
top of the microcomputer itself. The EPROM can be
removed and reprogrammed as required with a standard
PROM programmer. The MK38P70 retains exactly the
same pinout and architectural features as other members
of the 3870 family. The MK38P70 is discussed in more
detail in a later section.

RESET may be used to externally reset the MK3870. When
pulled low the MK3870 will reset. When then allowed to go
high the MK3870 will begin program execution at program
location H '000'.

PIN NAME
PO:O -- PCf..7
P1-0 -- P1-7
J54:O -- P4-7
P5-0 -- P5-7
STROBE
EXTINT
RESET
TEST
XTL 1, XTL 2
Vce, GND

DESCRIPTION
1/0 Port 0
1/0 Port 1
I/O Port 4
1/0 Port 5
Ready Strobe
External Interrupt
External Reset
Test Line
Time Base
Power Supply Lines

TYPE
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Output
Input
Input
Input
Input
Input

STROBE is a ready strobe associated with I/O Port 4. This
pin, which is normally high, provides a single low pulse after
valid data is present on the P4-0--P4-7 pins during an
output instruction.

EXT INT is the external interrupt input. Its active state is
software programmable. This input is also used in
conjunction with the timer for pulse width measurement
and event counting.
XTL 1 and XTL 2 are the time base inputs to which a crystal,
LC network, RC network, or an external single-phase clock
may be connected. The time base network must be
specified when ordering a mask ROM MK3870. The
MK38P70 will operate with any of the four configurations.

TEST is an input, used only in testing the MK3870. For
normal circuit function this pin may be left unconnected, but

VIII-4

it is recommended that TEST be grounded. On MK38P70
devices, the TEST must be grounded.

architecture is common to all members of the 3870 family.
All 3870 devices are instruction set compatible and differ
only in amount and type of ROM, RAM, and 1/0. The unique
features of the MK3870 are discussed in the following
sections. The user is referred to the 3870 Family Technical
Manual for a thorough discussion of the architecture,
instruction set, and other features which are common to all
3870 family devices.

Vee is the power supply input (single +5v).
MK3870 ARCHITECTURE
The basic functional elements of the MK3870 are shown in
Figure 1. A programming model is shown in Figure 2. The
MK3870 PROGRAMMABLE REGISTERS, PORTS,
AND MEMORY MAP
Figure 2

CPU REGISTERS

I 0 PORTS

BI:>.iARY
TIMER

ACCUMULATOR

PORT 7

A

SCRATCHPAD MEMORY

SCRATCHPAD

DEC

~o

7 _ 8 BITS_ 0

HEX

OC,

o

I
INTERRUPT
CONTROL PORT

STATUS
REGISTER
iWI

PORT 6

o z

I
N
T
R
C
N
T
R
L

PARALLEL
I 0 PORTS
PORT 5

C
E A
E R R
R o R
Y
F
L
0

S
I
G
N

V

5 BITS

.. 0

INOIRECT
SCRATCHPAO
AOORESS REGISTER

PORT 4

"
'2

10

A

HL

11

8

KU

,3
14

D

15

KL

12
13

au

14

16

QL

15

17

§

W

4 __

I
I

J
HU

61

3D

75

62

3E

76

63

3F

77

7 __ 8 8ITS_ 0

~;J

PORT 1

5

32

0

_6BITS~_

PORT 0
MAIN

7_8BITS-_0

MEMORY

PROGRAM
COUNTER

bU,,-_p,--,O_ _
PO_L.....1

~

11
87
0
_128IT5_

STACK
REGISTER

11

~

87
_128ITS_

DATA
COUNTER

1

DC

!DCU

I

DCl!

87
11
_17BITS_
RAM

MK3870122
MK3870/42

AUXDATA
COUNTER

I

DCI U

11

DCl

I

{ii

7 _ 8 BIT5_ 0

DCI LJ

87
_128IT5_

VIII-5

DEC
0
1

HEX

1022
1023

3FI
3FF

2046
2047

7FE
7FF

3070
3071

BFE
BFF

4030
4031

0
1

FBE
FBF

....--- MK3870/1D

ROM TOP
MK3870120
.......- MK3870/22

ROM TOP
_MK3870/42

4032
4033

4094
4095

FFE
FFF

ROM TOP
......-- MK3870/40

•

MK3870 MAIN MEMORY
SIZES AND TYPES BY SLASH NUMBERS
Figure 3
Hex

~

~
I
I

I
I

I

I

RAM

Dec

/ "":F=-=F'::-F-4~0~9~5-"""'> 64 bytes
"

FCD 4032
FBF 4031

_

executable
RAM

800 2043
7FF 2047

~

400 1024
3FF 1023

ROM

3870/10

2K

2K

4K

4K

ROM

ROM

ROM

ROM

3870/40

3870/42

3870/20 3870/22

00000000

w...------------~v~----------------All devices contain 64 bytes of scratch pad RAM.

NOTE: Data derived from addressing any locations other than
those within a part's specified ROM space or RAM space
(if any) are not tested nor are the data guaranteed. Users
should refrain from entering this area of the memory
map.

Scratchpad
RAM Size
(Decimal)

Address
Reg ister Size
(PO, P, DC, DC1)

ROM
Size
(Decimal)

Executable
RAM Size

MK3870/10

64 bytes

12 bits

1024 bytes

o bytes

MK3870/20*

64 bytes

12 bits

2048 bytes

o bytes

MK3870/22

64 bytes

12 bits

2048 bytes

64 bytes

MK3870/40

64 bytes

12 bits

4096 bytes

o bytes

MK3870/42

64 bytes

12 bits

4032 bytes

64 bytes

Device

*The MK3870/20 is equivalent to the original 3870 device in memory size; however, the original 3870 had an 11 -bit
Address Register. The original 3870 with 11-bit Address Register is available where required. Consult the section
describing ROM Code Ordering Information for additional information.

V111-6

I/O PIN CONCEPTUAL DIAGRAM WITH OUTPUT
BUFFER OPTIONS
Figure 4

OUTPUT
BUFFER

z0

PORT

D

1/0

PIN

~

<

a:

::::I
C!l

~

z
o(J
a:
0

~

a:
0

n-

C

<
w
a:

Q

~

a:
0

nc

<

0

....I

6
w

a:

~

(f)

::::I
aI

<
<
C
~

•

OUTPUT BUFFER OPTIONS
(MASK PROGRAMMABLE)

Vcc

6Kl! TYP.

STANDARD
OUTPUT

OPEN DRAIN
OUTPUT

DIRECT DRIVE
OUTPUT

Ports 0 and 1 are Standard Output type only.
Ports 4 and 5 may both be any of the three output options (mask programmable bit by bit)
The STROBE output is always configured similar to a Direct Drive Output except that it is capable of driving 3 TTL loads.

REm and EXT INT may have standard 6Kll (typical) pull-up or may have no pull-up. (mask programmable).
RESET and EXT INT do not have internal pull up on the MK38P70.

V111-7

MK3870 MAIN MEMORY
There are four address registers used to access main
memory. These are the Program Counter (PO), the Stack
Register (P), the Data Counter (DC), and the Auxiliary Data
Counter (DC1). The Program Counter is used to address
instructions or immediate operands. The Stack Register is
used to save the contents of the Program Counter during an
interrupt or subroutine call. Thus, the Stack Register
contains the return address at which processing is to
resume upon completion of the subroutine or interrupt
routine. The Data Counter is used to address data tables.
This register is auto-incrementing. Of the two data
counters, only Data Counter (DC), can access the ROM.
However, the XDC instruction allows the Data Counter and
Auxiliary Data Counter to be exchanged.
The graph in Figure 3 shows the amounts of ROM and
executable RAM for every available slash number in the
MK3870 pin configuration.

The MK38P70 can act as an emulator for the purpose of
verification of user code prior to the ordering of mask ROM
MK3870 devices. Thus, the MK38P70 eliminates the need
for emulator board products. In addition, several MK38P70s
can be used in prototype systems in order to test design
concepts in field service before committing to high-volume
production with mask ROM MK3870s. The compact size of
the MK38P70/EPROM combination allows the packaging
of such prototype systems to be the same as that used in
production. Finally, in low-volume applications, the
MK38P70 can be used as the actual production device.

Most of the material which has been presented for the
MK3870 in this document applies to the MK38P70. This
includes the description of the pin configuration,
architecture, programming model, and 1/0 ports. Additional
information is presented in the following sections.

MK38P70 MAIN MEMORY
EXECUTABLE RAM
The upper bytes of the address space in some of the
MK3870 devices are RAM memory. As with the ROM
memory, the RAM may be addressed by the PO and the DC
address registers. The executable RAM may be addressed
by all MK3870 instructions which address Main Memory.
Additionally, the MK3870 may execute an instruction
sequence which resides in the executable RAM. Note this
cannot be done with the scratchpad RAM memory, which is
the reason the term "executable RAM" is given to this
additional memory.

I/O PORTS
The M K3870 provides four, 8 bit bidirectional I nputlO utput
ports. These are ports 0, 1,4, 5. In addition, the Interrupt
Control Port is addressed as Port 6 and the binary timer is
addressed as Port 7. The programming of Ports 6 and 7 and
the bidirectional 1/0 pin are covered in the 3870 Family
Technical Manual. The schematic of an 1/0 pin and
available output drive options are shown in Figure 4.
An output ready strobe is associated with Port 4. This flag
may be used to Signal a peripheral device that the MK3870
has just completed an output of new data to Port 4. The
strobe provides a single low pulse shortly after the output
operation is completely finished, so either edge may be used
to signal the peripheral. STROBE may also be used as an
input strobe to Port 4 after completing the input operation.

There are two basic versions of the MK38P70. These are
the 97400 series and the 97500 series. The 97400 series
parts have twelve bit address capability thus a total 4K
memory map like the MK3870 ROM devices. The 97500
series has 16 bit address capability. The 97400 series
accepts 24 pin EPROMs, and the 97500 series accepts 28
pin EPROMs.
As can be seen from Figure 6, both the 97400 series and the
97500 series contain on-chip RAM in the upper portion of
their memory maps and no on-chip ROM. Instead of on-chip
ROM, address and data lines are brought out to the 28 pin
socket located directly on top of the 40 pin package so that
external memory devices (principally EPROMs) are
addressed.
By using an external EPROM, the 38P70 may be used to
emulate the 3870 ROM devices. The 97400 series can
directly emulate the following devices.
MK3870/10
MK3870/20
MK3870/22
MK3870/42

MK38P70 GENERAL DESCRIPTION

The MK3870/40 cannot be emulated exactly by the 97400
series because the 97400 devices have the 64 bytes of
RAM in the upper memory map while the 3870/40
provides ROM memory in this address space.

The MK38P70 is the EPROM version of the MK3870. It
retains an identical pinout with the MK3870, which is
documented in the section of this data sheet entitled
"FUNCTIONAL PIN DESCRIPTION". The MK38P70 is
housed in two packages which incorporate a 28 or 24-pin
socket located directly on top of the package. A number of
standard EPROMs may be plugged into this socket.

Besides the difference in the size of the address registers,
97500 series can also emulate many of the 3870 ROM
devices. This difference in address capability should not
cause any functional difference as long as normal
programming practice is used. That is, as long as address
roll-over or automatic truncation is not used. One such
usage would be an end around branch (branching forward

VIII-8

MK38P70 BLOCK DIAGRAM

EXTINT

Figure 6
EXTERNAL
PROM

MEMORY ADDRESS BUS

MEMOR_Y
ADDRESS
REGISTERS

PO: P
DC, DC1
MAIN
CONTROL
LOGIC

RESULT BUS

TEST

1/0 (8)

1/0 (8)

1/0 (8)

1/0 (8)STROBE

RESET

MK38P70 MAIN MEMORY MAP
HEX

Figure 6

FFFF - FFCO

FFB"F--

RAM

l

I

I
I
I
I
I

I
I
I
I
I

I
I
I
I
I

DEC
65535
65472
65471

I

RAM

I
I
I

I
I
I

J.

..L

'T'

'T'

I
I
I
I
I
I
I

OFFF
OFCO

- - ~ - : EXTERNAL
4032
I MEMORY

0FiiF - - 403-1-

I EXTERNAL I
: MEMORY:

~

__

MK97400
SERIES

MK38P70
TYPE

0000

_

'--_ _---'
MK97500
SERIES

SCRATCHPAD
RAM SIZE
(DECIMAL)

ADDRESS
REGISTER
SIZE

EXTERNALLY
ADDRESSABLE
MEMORY
SIZE

INTERNAL
EXECUTABLE
RAM
SIZE

97400 Series

64 bytes

12 bits

4032 bytes

64 bytes

97500 Series

64 bytes

16 bits

65472 bytes

64 bytes

MK38P70 devices have no internal ROM memory.
VIII-9

•

at upper memory to get to lower memory). Another case
would be in using automatic truncation of data loaded into
the 12 bit address registers on the ROM devices. For
example, to access some particular location (03FF hex for
example) via the data counter, one could load that address
into DC using the DCI instruction. The instruction
DCI73FF'
would cause 3FFtobe loaded into the DC of the 3870 ROM
device because the upper bits of the DC (bits 12-15) do not
exist. If that instruction was followed by the LM instruction,
the data stored at location 3FF would be obtained. The
97500 series devices would not truncate the 73FF address
to 3FF. As previously stated, this type of programming is
generally not done and thus the 97500 devices can be used
to emulate the following devices directly.
MK3870/10
MK3870/20
MK3870/40

The 97500 series can also be used to emulate the
remainder of the 3870 devices as long as one accounts for
the difference in the location of the RAM memory. In the
97500 devices, RAM is located at FFCO through FFFF.
While in 3870 devices this RAM (when it exists) is located at
OFCO through OFFF. When this minor difference is
accounted for, the 97500 series will also emulate the
following devices.
MK3870/22
MK3870/42

MK38P70 EPROM SOCKET
A 28 or 24 pin socket is located on top of the 40 pin package,
depending on the specific device. A 28 pin top socket array
was used so that the same package could be used for all
38P70 devices but could accommodate both 24 pin and 28
pin. Due to pin-out differences between various common
memory devices, several different versions of the M K38P70
are provided with differing signals connected to particular
pins on the socket. Figure 7 shows the various options
available. When 24 pin memories are used, they are
inserted so that pin 1 of the memory device is plugged into
pin 3 of the array(the 24 pin memory is lower justified in the
28 pin array).

MK38P70 I/O PORTS
For custom 3870 ROM codes, the user is given a bit by bit
selection of I/O options on I/O ports 4 and 5. Additionally,
the user has the option of selecting whether or not either
RESET or EXT INT has an internal pull-up resistor. This
flexibility allows about 172 million possible variations in I/O
portand RESET and EXTINTconfigurations. Obviously, it is
not practical to offer this variety in an "off the shelf" product

like the 38P70. Thus a few variations are offered which still
give some flexibility to the designer. The available I/O
options are also shown in Figure 7.

28 PIN SOCKET SIGNALS
The 40 package pins are the identical signals that are
provided with the MK3870 ROM devices. In addition to
these 40 inputs and outputs, various other signals are
implemented on the 38P70 die which are available for
connection to the top socket. Depending upon the
particular version, some subset of these signals are
connected to the 28 or 24 pin socket. These Signals are
described below.

Ao - A" (97400 Series)
Ao - A'5 (97500 Series)
These are the address buses. They are always outputs and a
new address will appear on this bus during each machine
cycle. Normally this is the address of op-codes or operands,
but there are machine cycles wherein no op-code or
operand is required by the CPU. During these cycles, an
address is still provided but the data that may be read from
that address is not used.
DO - 0 7 (97400 and 97500 Series)

This is the bi-directional data bus for the external memory.
Normally these lines are high impedance inputs. During
op-code or operand reads, they receive data from the
external memory and conduct it onto the internal 38P70
data bus. During those cycles wherein the operation is
strictly internal to the 38P70, they remain hi-z inputs. Data
may be presented to the 38P70 by an external memory
device but it is not conducted onto the internal data bus. This
includes machine cycles wherein op-codes or operands are
read from the internal executable RAM. During the operand
write machine cycle that occurs in the ST (store) instruction,
they become push-pull outputs to conduct data to be written
out to the external memory. However, if data is written to
the internal executable RAM, this transaction is strictly
internal and thus the data bus lines remain in their hi-z
state. It, therefore, depends upon the address as to whether
this bus becomes an active output bus or remains high
impedance. If the address of the operand is not within the
internal executable RAM space when a ST instruction is
executed, Do - D7 will become active outputs at the appropriate time, or else they will remain in the hi-z state. The
97400 devices do not provide a RD (read) control signal, nor
is this signal provided on all versions of the 97500 series.
Thus if a ST is executed with the operand address being that
of external memory, that memory may access data and
drive it onto Do - D7 while the 38P70 is also driving data onto
Do -D7 and a bus conflict will result. This condition should
be avoided; thus the user should note whether or not his
external memory will drive Do - D7 in this event. If it will
drive Do - D7, an ST with that operand address should be
avoided. In general, one would not normally execute a write
to a memory location where there is ROM or EPROM
memory instead of RAM. However, some 3870 users have

V111-1 0

MK38P70 VERSIONS
Figure 7

TOP 28 PIN
SOCKET ARRAY
WIRING VERSION

PORT 4
1/0 TYPE

PORT 5
1/0 TYPE

MK97400

TTL

TTL

2716,2516,2532,2758
MK34000 ROM

A

MK97410

Open
Drain

Open
Drain

2716,2516,2532,2758
MK34000 ROM

A

MK97501

TTL

TTL

2764, 2732, MK37000 ROM
MK34000 ROM

B

MK97521

TTL

Open
Drain

2764,2732,
MK37000 ROM MK34000 ROM

B

DEVICE

1
2
3 (1) *
4 (2)
5 (3)
6 (4)
7 (5)
S (6)
9 (7)
10 (S)
11 (9)
12 (10)
13 (11)
14 (12)

2S.
27 •
(24) 26 •
(23) 25 •
(22) 24 •
(21) 23 •
(20) 22 •
(19)21.
(1S) 20 •
(17) 19 •
(16) 1S •
(15) 17 •
(14) 16 •
(13) 15 •

SUPPORTS THESE
MEMORY DEVICES

Vee

Vee
Vee
Vee

A'2
A7
A6
A5
A4
A3
A2
A,
Ao
Do

As
A9
Vee
Vss

A,o
A"
07
06
05
04
03

0,
'0 2
Vss

••
••
•
•••
•••
•••

~
Vee

As
A9

~
~

MREQ

07
06
05
04
03
VERSION
B

VERSION A

*NOTE: On Version A packages, sockets are provided in only 24 of the 28
possible locations for a 24 pin EPROM,

VIII-11

•

found the ST instruction useful even in devices like the
3870/20 which have no executable RAM. In this case it
causes the data counter to increment (to perhaps totalize
some event) but otherwise does nothing as one cannot
write the internal ROM. No internal conflicts will occur if
one attempts to write a 3870 ROM location. Most 97500
versions place a RD (read, active low) signal on the top
socket pin which matches the DE (output enable, active low)
input on most memories. Since RD will remain high during
an operand write, the external memory would not have its
data outputs enabled and no conflict will occur.

remain high. It will also remain high during an operand
write cycle.
WR (97500 Series Only)
This is the active low write control output. It is normally high
but will go low then return high during an operand write if
the address is not that of internal executable RAM.
FETCH (97500 Series Only)
This is the active low fetch status signal which signals that
an op-code fetch occurred during that cycle. It is generated
for use of the 97500 as a development system component.

MREQ (97500 Series Only)
This is an active low output which occurs during each
machine cycle. It goes high at the start of each cycle then
goes low for the remainder of the cycle.

It will go low during all op-code fetches whether from
internal or external memory.

RD (97500 Series Only)

38P70 EXTERNAL MEMORY TIMING

This is the active low read output which goes high at the
start of each cycle then goes low if data (op-codes or
operands) are to be read from external memory. During
cycles wherein a strictly internal operation occurs, RD will

The following Figures show the relative waveforms for the
signals used to interface with external memory. The timing
parameters are labeled. Their values are given in the A.C.
Characteristics section of the Electrical Specifications.

97400 SERIES TIMING
Read Cycle
Figure 8

PREVIOUS ADDRESS

CURRENT ADDR VALID

-_>E

DATA VALID

T dhr

~

Actively driven by 38P70 but not necessarily in
valid state.

-)

Not actively driven by the 38P70. May be
actively driven by external memory but does
not have to be in a valid state or may be placed
in hi-z state by external memory.

VIII-12

97500 SERIES TIMING
Figure 9

I...
MREQ

OP-CODE FETCH

J

I

~Thm4

R5J

~T

---~""I~""'1I(------OPERAND READ---------i·~1

L--_-----II

I

'-------'I

I

1.-.-_ _-----'

hr

•

DO-D7~

A. OP-CODE AND OPERAND READ
FROM EXTERNAL MEMORY

VIII-13

97500 SERIES TIMING (Continued)
Figure 9

!+---OP.COOE FETCH-----I--+I••- - - - - - O P E R A N D WRITE

J

------~,I

.~_-----II

I

I~-----Tw-----~

Do' 0 7

==x=.
B. OPERAND WRITE TO EXTERNAL
MEMORY

VIII·14

97500 SERIES TIMING (Continued)
Figure 9

CD

u

u

°0.°,5 ~)f--~>CXlf-----------1(>a'k--C. EXAMPLES OF VARIOUS CYCLES

CD

Op-code fetch from external memory followed
by an internal cycle (short cycle).
Op-code fetch from external memory followed
by an internal cycle (long cycle) such as an
operand read or write internal executable RAM.
CD Op-code fetch from internal executable RAM.
@ Op-code fetch frorn internal executable RAM
followed by a internal cycle (long cycle) such as
an operand read or write of internal executable
RAM.
CD First cycle of an interrupt acknowledge. Had an
interrupt not occurred. this would have been an
op-code fetch. If it would have been an external
op-code fetch. RD will still go low but FETCH
will not indicate a fetch cycle. Externally this
would appear to be an operand read exceptthat
it occurs in a short cycle and all real operand
reads occur in a long cycle.

CD

3870 TIME BASE OPTIONS
The 3870 contains an on-Chip oscillator circuit which
provides an internal clock. The frequency of the oscillator
circuit is set from the external time base network. The time
base for the 3870 may originate from one of four sources:
1)
2)
3)
4)

Crystal
LC Network
RC Network
External Clock

The specifications for the four configurations are given in
the following text. There is an internal 26 pF capacitor
between XTL 1 and GND and an internal 26 pF capacitor
between XTL 2 and GND. Thus, external capacitors are not
necessarily required. In all external clock modes the
external time base frequently is divided by two to form the
internal PHI clock.
CRYSTAL SELECTION

The type of network which is to be used with the mask ROM
MK3870 must be specified at the time when mask ROM
devices are ordered. However, the MK38P70 may operate
with any of the four configurations so that it may emulate
any configuration used with a mask ROM device.

The use of a crystal as the time base is highly recommended
as the frequency stability and reproduction from system to
system is unsurpassed. The 3870 has an internal divide by
two to allow the use of inexpensive and widely available TV
Color Burst Crystals (3.58 MHz). Figure 11 lists the required
crystal parameters for use with the 3870. The Crystal Mode
time base configuration is shown in Figure 10.

VIII·15

•

Through careful buffering ofthe XTL 1 pin it may be possible
to amplify this waveform and distribute it to other devices.
However, Mostek recommends that a separate active
device (such as a 7400 series TTL gate) be used to oscillate
the crystal and that the waveform from that oscillator be
buffered and supplied to all devices, including the 3870, if a
single crystal is to provide the time base for more than just a
single 3870.
While a ceramic resonator may work with the 3870 crystal
oscillator, it was designed specifically to support the use of
this component. Thus, Mostek does not support the use of a
ceramic resonator either through proper testing, parametric
specification, or applications support.

LC NETWORK
The LC time base configuration can be used to provide a less
expensive time base for the 3870 tha n ca n be provided with
a crystal. However, the LC configuration is much less
accurate than is the crystal configuration. The LCtime base
configuration is shown in Figure 12. Also shown in the
figure are the specified parameters for the LC components,
along with the formula for calculating the resulting time
base frequency. The minimum value of the inductor which
is required for proper operation of the LC time base network
is 0.1 millihenries. The inductor must have a Qfactorwhich
is no less than 40. The value of C is derived from C external,
the internal capacitance of the 3870, CXTL' and the stray

CRYSTAL MODE CONNECTION
Figure 10

XTL1

XTL2

D
AT- CUT

CRYSTAL PARAMETERS
Figure 11

a)
b)
c)
d)

Parallel resonance, fundamental mode AT-Cut
Shunt capacitance (Co) = 7 pf max.
Series resistance (Rs) = See table
Holder = See table below.

Frequency

Series Resistance

Holder

f = 2-2.7 MHz

Rs = 300 ohms max

HC-6
HC-33

f = 2.8-4 MHz

Rs = 150 ohms max

HC-6
HC-18*
HC-25*
HC-33

*This holder may not be available at frequencies near the lower end of this range.

VIII-16

LC MODE CONNECTION
Figure 12

XTL2

XTL1

---

1----

L

I

rrm

I
L _________ ~

I

I

~----------

CEXTERNAL
(OPTIONAL)

f=

2

rr

'VLC

capacitances, CS1 and CS2 ' CXTL is the capacitance looking
into the internal two port network at XTL 1 and XTL2. CXTL is
listed under the "Capacitance" section of the Electrical
Specifications. CS1 and CS2 are stray capacitances from
XTL 1 to ground and from XTL2 to ground, respectively. C
external should also include the stray shunt capacitance
across the inductor. This is typically in the 3 to 5 pf range
and significant error can result if it is not included in the
frequency calculation.

Crystal or LC time base configuration. Figure 14 illustrates a
curve which gives the resulting operating frequency for a
particular RC value. The x-axis represents the product of the
value of the resistor times the value of the capacitor. Note
that three curves are actually shown. The curve in the
middle represents the nominal frequency obtained for a
given value of RC. A maximum curve and a minimum curve
for different types of 3870 devices are also shown in the
diagram.

Variation in time base frequency with the LC network can
arise from one of four sources: 1) Variation in the value of
the inductor. 2) Variation in the value of the external
capacitor. 3) Variation in the value of the internal
capacitance of the 3870 at XTL 1 and XTL2 and 4) Variation
in the amount of stray capacitance which exists in the
circuit. Therefore, the actual frequency which is generated
by the LC circuit is within a range of possible frequencies,
where the range of frequencies is determined by the worst
case variation in circuit parameters. The designer must
select component values such that the range of possible
frequencies with the LC mode does not go outside of the
specified operating frequency range for the 3870.

The designer must select the RC product such that a
frequency of less than 2 MHz is not possible, taking into
account the maximum possible RC product and using the
minimum curve shown in Figure 14 below. Also, the RC
product must not allow a frequency of more than 4 MHz,
taking into account the minimum possible Rand C and
using the Maximum curve shown below. Temperature
induced variations in the external components should be
considered in calculating the RC product.

RC CLOCK CONFIGURATION

Frequency variation due to Vee with all other parameters
constant with respect to +5V = +7 percent to -4 percent on
all dENices.

The time base for the 3870 may be provided from an RC
network tied to the XTL2 pin, when XTL 1 is grounded. A
schematic picturing the RC clock configuration is shown in
Figure 13. The RC time base configuration is intended to
provide an inexpensive time base source for applications in
which timing is not critical. Some users have elected to tune
each unit using a variable resistor or external capacitor thus
reducing the variation in frequency. However, for increased
time base accuracy, Mostek recommends the use of the

Frequency variation from unit to unit owing to switching
speed and level at constant temperature and Vee = + or - 5
~~~

.

Frequency variation due to temperature with respect to 25
C (all other parameters constant) is as follows:

VIII-17

PART #

VARIATION

387X-OO, -05
387X-10, -15

+6 percent to - 9 percent
+9 percent to -12 percent

•

RC MODE CONNECTION
Figure 13

RCMODE

XTL2

XTL1

R

I

--L~

MINIMUM R

C

=26.5 pF

I

=4K n

--L

± 2.6pF + Cexternal

FREQUENCY VS. RC
Figure 14

3MHz

2MHz~------~----------~-----------;------~-'~~~----~

RC PRODUCT

2 x 10-7

VIII-18

2.5 x 10-7

3 x 10-7

CEXTERNAL
(OPTIONAL)

Variations in frequency due to variations in RC components
may be calculated as follows:

=-18 percent minus negative

=-21 percent minus

frequency variation due to
RC components

negative frequency
variation due to RC
components

Maximum RC = (R max) (C external max + CXTL max)
Minimum RC
Typical RC

=(R min) (C external min + CXTL min)

Total frequency variation due to Vce and temperature of a
unit tuned to frequency at +5V Vec' 25 C

= (R typ) (C external typ +

387X-OO, -05

{CXTL max + CXTL min})

= + 13 percent

2

Positive Freq. Variation

= RC typical - RC minimum

387X-10, -15

= + 16 percent

EXTERNAL CLOCK CONFIGURATION

RC typical
The connection for the external clock time base
configuration is shown in Figure 15. Refer to the DC
Characteristics section for proper input levels and current
requirements.

Negative Freq. Variation = RC maximum - RC typical
RC typical
due to RC Components
Total frequency variation due to all factors:
387X-OO, -05
= + 18 percent plus positive
frequency variation due
to RC components

387X-10, -15
= +21 percent plus positive
frequency variation due
to RC components

Refer to the Capacitance section of the appropriate 3870
Family device data sheet for input capacitance.

EXTERNAL MODE CONNECTION
Figure 15

III
XTL1

XTL2

I

NO CONNECTION

EXTERNAL
CLOCK
INPUT

VIII-19

ELECTRICAL SPECIFICATIONS
MK3870, MK38P70

OPERATING VOLTAGES AND TEMPERATURES
Dash
Number
Suffix

Operating
Voltage
VCC

Operating
Temprature
TA

-00
-05
-10
-15

+5V ± 10%
+5V±5%
+5V ± 10%
+5V±5%

O°C -70°C
O°C -70°C
-40°C - +85°C
-40°C - +85°C

See Ordering Information for explanation of part numbers.
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ..................•................
Storage Temperatu re ...•..................................
Voltage on any Pin With Respect to Ground
(Except open drain pins and TEST) ........•................
Voltage on TEST with Respect to Ground ................... .
Voltage on Open Drain Pins With Respect to Ground ..•.......
Power Dissipation ....................................... .
Power Dissipation by anyone I/O pin ...................... .
Power Dissipation by all I/O pins .......................... .

-00, -05

-10,-15

-20°C to +85°C
-65°C to +150°C

-50°C to +1 OO°C
-65°C to +150°C

-1.0V to +7V
-1.0V to +9V
-1.0V to +13.5V
1.5W
60mW
600mW

-1.0V to +7V
-1.0V to +9V
-1.0V to +13.5V
1.5W
60mW
600mW

*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at
these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

AC CHARACTERISTICS
TA, V CC within specified operating range.
I/O power dissipation :5 1OOmW (Note 2)
-00,-05

-10,-15

SIGNAL

SYM

PARAMETER

MIN

MAX

MIN

MAX

XTL1
XTL2

to

Time Base Period, all clock modes

250

500

250

500

ns

tex(H)
tex(L)

External clock pulse width high
External clock pulse width low

90
100

400
400

100
110

390
390

ns
ns

t

Internal ep clock

2t()

2to

WRITE

tw

Internal WRITE Clock period

4tep
6tep

4tep
6tep

I/O

tdl/O

Output delay from internal
WRITE clock

0

tsi/O

Input setup time to internal
WRITE clock

1000

tl/O-s

Output valid to

tsL
tRH



STROBE

RESET

STRC5BE delay

tEH

0

1200

1200

4MHz-2MHz

Short Cycle
Long Cycle
ns

50pF plus
one TIL load

ns

3tep
-1000

3tep
+250

3tep
-1200

3t
+300

ns

I/O load =
50pF + 1 TIL load

STROBE low time

8tep
-250

12tep
+250

ns

STROBE load=
50pF + 3TIL loads

RESET hold time, low

6tep
+750

Step
12tep
-300 +300
6tep
+1000

power
supply
rise
time '0.1

power
supply
rise
time +.15

6tep
+750
2tep

6tep
+1000
2tep

tRPOC RESET hold time, low for power
clear
EXTINT

1000

UNIT NOTES

EXT INT hold time in active and
inactive state

VIII·20

ns

ms
ns
ns

To trigger
interrupt
To trigger timer

AC CHARACTERISTICS FOR MK38P70 Signals brought to top 28 pin socket.
TA, Vee within specified operating range.
I/O Power Dissipation :5 100 mW (Note 2)
97400 Series (See Note 3)
-00, -05
SYMBOL

PARAMETER

MIN

taas

External memory required
access time from Ao-A" stable

3t<1>
-850

MAX

-10, -15
MIN

MAX

3t<1>
-850

UNIT CONDITION

ns

CLAo-A"
50 pF

=

97500 Series (See Note 3)
-00, -05

MAX UNITS CONDITION

SYMBOL

MREO

Thm

MREO high time

2t<1>
-100

2t<1>
-100

ns

Load = 50 pF + 1
TTL load

RD

Thr

RD high time

2t<1>
-100

2t<1>
-100

ns

Load = 50 pF + 1
TTL load

WR

Tw

WR low from
MREOlow

3 to
-200

3 to
+100

3 to
-200

3 to
+100

ns

Load = 50 pF + 1
TTL load

Twl

WR low time

to
-100

to
+100

to
-100

to
+100

ns

Tft

FETCH stable prior
to rising MREO

650

650

650

650

ns

Load = 50 pF + 1
TTL Load

Tfh

FETCH hold time
after MREO high

Ta

Ao - A'5

Do - D7

MAX

-10, -15

SIGNAL

FETCH

MIN

MIN

PARAMETER

= 20 pF

20

20

ns

Load

Address stable prior
to RD or MREO falling

t<1>
-400

t<1>
-400

ns

Load = 50 pF + 1
TTL load

Tah

Address hold time after
MREO, RD, or WR high

15

15

ns

Load

Taas

External memory required
access time from

3t<1>
-850

3t<1>
-850

ns

Tmas

External memory required
access time from MREO
or RD low

2t<1>
-450

2t<1>
-450

ns

Tdhr

Required data hold time
after MREO rising

0

0

ns

Tda

Data bus active after
MREO or RD high

t<1>

t<1>

Tdw

Data stable prior to WR
falling

5t<1>
-2250

5t<1>
-2250

ns

Load = 50 pF + 1
TTL load

Tdhr

Data hold after WR high

15

15

ns

Load

Tdfw

Data ~Iay to float
after MRE rising

200

V111-21

200

ns

= 20 pF

= 20 pF

•

CAPACITANCE
TA = 25°C
All Part Numbers
SYM

PARAMETER

CIN

Input capacitance

CXTL

Input capacitance; XTL 1, XTL2

MIN

MAX

UNIT NOTES

10

pF

23.5

29.5

pF

-00, -05

-10, -15

unmeasured
pins grounded

DC CHARACTERISTICS
TA' V cc within specified operating range
I/O power dissipation::; 100 mW (Note 2)

SYMBOL

PARAMETER

Icc

Average Power Supply

MIN

MAX
85

MIN

MAX
110

UNIT DEVICE
rnA

Current

MK3870/10
Outputs Open

85

110

rnA

MK3870/20
Outputs Open

94

125

rnA

MK3870/22
Outputs Open

100

130

rnA

MK3870/40
Outputs Open

100

130

rnA

MK3870/42
Outputs Open

125

150

rnA

MK38P70lX02
No EPROM,
Outputs Open

V111-22

DC CHARACTERISTICS (cont.)

-00, -05
SYMBOL

PARAMETER

Po

Power Dissipation

MIN

MAX
400

-10,-15
MIN

MAX
525

UNIT DEVICE

mW

MK3870/10
Outputs Open

400

525

mW

MK3870/20
Outputs Open

440

575

mW

MK3870/22
Outputs Open

475

620

mW

MK3870/40
Outputs Open

475

620

mW

MK3870/42
Outputs Open

600

VIII-23

750

mW

MK38P70/X02
No EPROM,
Outputs Open

II

DC CHARACTERISTICS (cont.)
TA V CC within specified operating range, I/O power dissipation::; 1OOrnW (Note 2)

-00,-05
SYM

PARAMETER

VIHEX

-10,-15

MIN

MAX

MIN

MAX

External Clock input high level

2.4

5.8

2.4

5.8

V

VILEX

External Clock input low level

-.3

.6

-.3

.6

V

IIHEX

External Clock input high current

100

130

/-LA

VIHEX=VCC

IILEX

External Clock input low current

-100

-130

/-LA

VILEX=VSS

VIHI/O

Input high level, 1/0 pins

VIHR

VIHEI

Input high level, RESET

Input high level, EXT INT

UNIT CONDITIONS

2.0

5.8

2.0

5.8

V

Standard pull-up

2.0

13.2

2.0

13.2

V

Open drain (1)

2.0

5.8

2.2

5.8

V

Standard pull-up

2.0

13.2

2.2

13.2

V

No Pull-up

2.0

5.8

2.2

5.8

V

Standard pull-up

2.0

13.2

2.2

13.2

V

No Pull-up

-.3

.8

-.3

7

V

(1)

--

VIL

Input low level

IlL

Input low current, all pins with
standard pull-up resistor

-1.6

-1.9

rnA VIN=O.4V

IL

Input leakage current, open drain
pins, and inputs with no pull-up resistor

+10
-5

+18
-8

/-LA
/-LA

VIN=13.2V
VIN=O.OV

10H

Output high current pins with
standard pull-up resistor

10HDD

Output high current.
direct drive pins

-100

-89

/-LA

VOH=2.4V

-30

-25

/-LA

VOH=3.9V

-100
-1.5

-80
-1.3

!-LA VOH=2.4V
rnA VOH=1.5V
rnA VOH=0.7V

-11

-8.5
-300

-270

/-LA VOH = 2.4V

Output low current

1.8

1.65

rnA VOL =0.4V

STROBE Output Low current

5.0

4.5

rnA VOL =0.4V

10HS

STROBE Output High current

10L
10LS

VIII-24

DC CHARACTERISTICS FOR MK38P70
Signals brought to top 25 pin socket
TA, Vee within specified range
I/O Power Dissipation:::; 100 mW (Note 2)
97400,97500 Series
-00, -05
SYMBOL

PARAMETER

V 1H
V 1L

-10, -15

MIN

MAX

MIN

MAX

Input high level (Do - 0 7)

2.0

Vee
+.3

2.1

Vee
+.3

V

Input low level (Do - 0 7)

Vss

.8

Vss

.7

V

±15

pA

-.3

UNIT CONDITION

-.3

IL

Input Leakage (Do - 0 7)

V OH

Output high level (all outputs and
0 0 -0 7 in output mode)

VOL

Output low level (all outputs and
Do-D7 in output mode)

IOH

Output source current (all outputs
and 0 0 -0 7 in output mode)

IOL

Output sink current (all outputs
and 0 0 -0 7 in output mode)

Ree

Package resistance from device
pin 40 to top socket Vee
pin(s)

n

Rss

Package resistance from device
pin 20 to top socket Vss pin(s)

n
n

lee

Supply current available from
top socket Vee pin(s)

Iss

Do - 0 7 in Hi-z
input mode

±10
2.4

2.4

.4

V

.4

V

-100

-90

pA

V OH = 2.4V

1.8

1.65

mA

VOL =.4 V

n
n

Supply current available from
top socket Vss pin(s)

NOTES:
1. RESET and EXT INT have internal Schmit triggers giving minimum .2 V
hysteresis.
2. Power dissipation for 1/0 pins is calcualted by1:(VCC - VIL)( IIIL I) =:I:(VCCVOH) (IIOH I ) = :I:(VOH)(IOL)
3. AC timing for external memory signals on 38P70 are measured from either
the.8 or 2.0 volt points as applicable. High meansat or above 2.0 volts. Low

Pin 28, 27, or 26
'when Vee
Pin 1 if Vee
Pin 23 if Vee
Pin 14 when Vss
Pin 2 or 22 when
Vss

-185

-185

mA

-20
-10

-20
-10

LI pin 28 27, 26
. when Vee
mA Pin 1 if Vee
mA Pin 23 if Vee

190
2
2

190
Z
2

mA
rnA
mA

Pin 14 if Vss
Pin 2 ifVs~
Pin 22 if Vss

means at or below.8 volts. Stable means high or low as appropriate. Rising
means signal is no longer below.8 volts. Falling means signal is no longer
above 2.0 volts. Hold times on outputs assume full rated load on reference
signal and 20 pf load on specified signal. For 97400 series. only applicable
specification is Taas as no other signals are available to reference to other
than Ao-A11'

TIMER AC CHARACTERISTICS
Definitions:
Error = Indicated time value - actual time value
tpsc = t X Prescale Value
Interval Timer Mode:
Single interval error, free running (Note 3) ............................................................ ±6t
Cumulative interval error, free running (Note 3) ........................................................... 0
VIII-2S

•

Error between two Timer reads (Note 2) .......................................................... ± (tpsc + tell)
Start Timer to stop Timer error (Notes 1, 4) .•............................•...............•.. + tell to - (tpsc + tell)
Start Timer to read Timer error (Notes 1, 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . • .. -5tell to - (tpsc + 7tell)
Start Timer to interrupt request error (Notes 1, 3) ......................•............................ -2tell to -8tell
Load Timer to stop Timer error (Note 1) ..•.•.........•.•.•..••..••••.•..•••••••.••••••••••• + tell to - (tpsc + 2tell)
Load Timer to read Timer error (Notes 1, 2) •..............•. '. ............................. -5t ± to - (tpsc + 8t ±)
Load Timer to interrupt request error (Notes 1, 3) ........•.......................................... -2tell to -9tell
Pulse Width Measurement Mode:
Measurement accuracy (Note 4) •......•...•••.......•••.•....•.•.....•.••••••.••••..••. + tell to -(tpsc + 2tell)
Minimum pulse width of EXT INT pin ..............................................•.....•............. 2tell
Event Counter Mode:
Minimum active time of EXT INT pin ............................................•..................... 2tell
Minimum inactive time of EXT INT pin ................................................................. 2tell
Notel:
1. All times which entail loading. starting. or stopping the Timer are referenced from the end of the last machine cycle of the OUT or OUTS instruction.
2. All times which entail reading the Timer are referenced from the end of the last machine cycle of the IN or INS instructipn.
3. All times which entail the generation of an interrupt request are referenced from the start of the machine cycle in which the appropriate interrupt request latch is
set. Additional time may elapse if the interrupt request occurs during a privileged or multicycle instruction.
4. Error may be cumulative if operation is repetitively performed.

AC TIMING DIAGRAM
Figure 16

External Clock

Internal ell Clock

1/0 Port Output

STROBE

RESET

EXTINT

ICPBIT]=OO ~H=f
~'-----

lep Brr2 ° 1

Note: All AC measurements are referenced to V 1L max., V 1H min., VOL (.8v), or V OH (2.0v).

VIII·26

INPUT/OUTPUT AC TIMING
Figure 17

INTERNAL
WRITE

CVCLE TIMING

14----~++-----.,j.c-------_++----i*-- DEPENDS ON INSTRUCTION

CLOCK

SHOWN FOR
4MHz EXTERNAL

INS
OP CODE
FETCHED

PLACED ON
DATA BUS

CLOCK
PORT PINS

A. INPUT ON PORT 4 OR 5

INTERNAL
WRITE

CLOCK
OUT OR
OUTS
OP CODE
FETCHED

PORT ADDR.
ON DATA
BUS

ACCUMU LA TOR
CONTENTS
ON DATA BUS

NEXT
OP CODE
FETCHED

II

PORT PINS
STAVS LOW

STROBF
(ACTIVE FOR PORT 4 ONL VI

FOR TWO WRITE
CVCLES

B. OUTPUT ON PORT 4 OR 5

!l/O-S

INTERNAL
WRITE

CLOCK
OUTS 0.1
FETCHED

ACC DATA
ON BUS

NEXT
OP CODE
FETCHED

PORT PINS

C. INPUT ON PORT 0 OR 1

D. OUTPUT ON PORT O. 1

VIII·27

-15

STROBE SOURCE CAPABILITY
(TYPICAL AT vee = 5 V, TA= 25°C)
Figure 18

1

1
I

S

I

0
U
R
C
E

,

-10

C
U

T

I

1

i

- •.

1

f""'oi'ooo..

-5

i-1- "--- f-··t··+-f-

...... ~

I

.... r-.~

i

M
A

!

I

J._

...... ~

R
R
E
N

J

!

,

~~~-

f-r-----

I

'
I

'"

,

~ '~

I

-~'I---'

~

J:"'j..."

I

t

-

--+--- ...:...

1_1-

~'

......

OUTPUT VOLTAGE

STROBE SINK CAPABILITY
(TYPICAL AT Vee = 5 V, TA = 25°C)
Figure 19
S
I

+100

+50

T

t-t-~+j

r--~ -,+,--t-,.Y1"
1
I
:./ J j

M

i

I

J.".oi"""!""

+-#--

.loot- t..:.:

'J.--+-+.-

-

i

i

f-L,

1,

-r-~ f---4-.-f-..
'I

l'

J~

!/!'
All

A

!,

I

+·-+·1+-

,-~L ;,t
;.-.I-l-~ -.---;.--~-.

1---+-';--, --~i~. f-l--

C
U

R
R
E
N

:-\-l+t--L: -+.;.
t-----'---+'--+--+-,------'-

N
K

1

I

1

I I -L-Ll.. i '
1111-11

i

II

f-

I

I I
I
Ii
i

OUTPUT VOLTAGE

STANDARD I/O PORT SOURCE CAPABILITY 1,5
= 5 V, TA = 25°C)

(TYPICAL AT Vee
Figure 20

S

0

f"

U

R
C

E

1'.

-1,0

..... i"o..

r"

c
U

R
R
E
N

T

i'

..... t-....

-,5

.....
......
.....~

M
A

-1--1

'"

r--...

..........

OUTPUT VOL TAGE

DIRECT DRIVE I/O PORT SOURCE CAPABILITY
(TYPICAL AT Vee = 5 V, TA = 25°C)
Figure 21
So
I-t--+-+--+ .-t--t--ll-t.-+-r--t-+.+-+-+-+-+-+---r-+ . - r--f--f-

U

~

C

=
~

f--- -- .- -.- . - f -

-10+-+--1e----+-+--++-+-!--I--I-.-+-+-+_+-H-+-+-+_+--1

-~~ ~-

r-- --r10-1:==+--+-+-.1----1

-- -

--1'

=-~ .-~:
-- -

--

----f-

f - -.. - - --- ---

-5 +-+----jt-e----+....
-+--+r--+f""oo-f....""""'d--t-t-l-t- ++--I-+-+--+-+--1
1 - - - - +-t--1r-......-+t-...-"!"...t:--+---t-t-l-t-+-+--+-H

_1--_ - f- i"'i"-I--+-+--+-+-+-

r--..~

T

~
t- - .

-I-t---t-- -++-+-I--+-+-+-~:i-",-+-t--1-+-

OUTPUT VOLTAGE

VIII·28

1/0 PORT SINK CAPABILITY
(TYPICAL AT Vee = 5 V, TA = 25°C)

-

Figure 22

--

100

I - -1--1--

-I-- -

,-I--

-

--

~r---

-

~

P(~ASl',c

50

- - --1--

r-

-r--,

CERA.M~
....
.....

1--

100

-~

200

300

400

500

-1000

600

POliO MW

MAXIMUM OPERATING TEMPERATURE VS.
1/0 POWER DISSIPATION
+60

Figure 23

S
I
N
K

+50

c

+40

U

R
R

+30

E
N

_ _ I"""

-~I"'"

T

+20

M
A

~

+10

-~

...... V ..... ""'"
OUTPUT VOL TAGE

information defining 1/0 options and oscillator options will
be combined with the information described in the generic
part number to define a customerlcode specific device
order number. Note: the specific device order number will
be used to differentiate between the MK3870/20 with
12-bit Address Registers and the original 3870 with 11-bit
Address Register, as mentioned in an earlier section.

ORDERING INFORMATION
There are two types of part numbers for the 3870 family of
devices. The generic part number describes the basic device
type, the amount of ROM and Executable RAM, the desired
package type, temperature range, and power supply
tolerance. For each customer specific code, additional
GENERIC PART NUMBER
.An example of the generic part number is shown below.
MK3870/22 P-1 0

l~power

L - - - - - t..

Supply Tolerance

0= 5V ± 10%
5 = 5V ± 5%

Operating Temperature Range

0= O°C - +70°C
1 = -40°C - +85°C

Package type

. P = Ceramic
N = Plastic

Executable RAM Designator

0= None
2 = 64 bytes

ROM Designator

1
2

= 1K Bytes
= 2K bytes

Basic Device Type

VIII-29

4

= 4K Bytes

•

DEVICE ORDER NUMBER
An example of the device order number is shown below.
MK 14007 N - 0 5

11 :
~--.....

1--_ _ _ _" .

Power Supply Tolerance

0= 5V ± 100A>
5 = 5V± 5%

Operating Temperature Range

0= O°C - +70°C
1 = -40°C - +85°C

Package Types

P = Ceramic
N = Plastic

Customer/Code Specific Number

The Customer/Code specific number defines the ROM bit
pattern, I/O configuration, oscillator type, and generic part
type to be used to satisfy the requirements of a particular
customer purchase order. For further information on the
orderi ng of mask ROM devices, the customer should refer to
the 3870 Family Technical Manual.
Examples of a 38P70 device order number is shown below.
MK 97400R 00

11 :
~--~.

Power Supply Tolerance

0= 5V ± 10%

Operating Temperature Range

0= O°C - +70°C
1 = -40°C - +85°C

Package Type

R = Piggyback

""------i~ Port

I/O Options

" ' - - - - - -...... Maximum Size of EPROM

See Figure 7
See Figure 7

VIII-30

B

UNITED

TECHNOLOGIES
MOSTEK

MICROCOMPUTER
COMPONENTS
3870 SINGLE CHIP MICRO FAMILY
MK2870

MK2870 FEATURES

MK2870
Figure 1

o

28-pin version of the industry standard MK3870 single
chip microcomputer

o

Available with 1 K bytes of mask programmable ROM
memory

o

64 bytes scratch pad RAM

o

20 bits TIL compatible I/O

o

Programmable binary timer
Interval timer mode
Pulse width measurement mode
Event counter mode

o

External interrupt input

o

Crystal, LC, RC, or external time base options

o

Low power (275 mW typ.)

o

Single +5 volt supply

•
MK2870 PIN CONNECTIONS
Figure 2

GENERAL DESCRIPTION
The MK2870 is the 28-pin version of the industry standard
Mostek MK3870 single chip microcomputer. It is offered as
a low cost device which can be used in those applications
that do not require the entire I/O capability of the 40 pin
MK3870. The compact 28-pin package makes the MK2870
ideally suited for applications where PC board space is a
premium.
The MK2870 can execute more than 70 instructions, and is
completely software compatible with the rest of the devices
in the 3870 family. The MK2870 features 1 K bytes of ROM.
The MK2870 also features 64 bytes of scratchpad RAM, a
programmable binary timer, and 20 bits of I/O.
The programmable binary timer operates by itself in the
interval timer mode or in conjunction with the external
interrupt input in the pulse width measurement and the
event cou nter modes of operation. Two sources of vectored,
prioritized interrupt are provided with the binary timer and
the external interrupt input. The user has the option of
specifying one of four clock sources for the MK2870:

VIII-31

28
27

STROBE

1
2
3
4

P4-0

5

P4-1

6

24
23

P4-2

7
8
9

22
21
20

10
11
12·

19

P5-4

18
17

P5-5

13
14

16
15

Vee
XTL1
XTL2

P4-3

P4-4
P4-5
P4-6
P4-7
PO-7
GND

26
25

RESET
EXTINT

Pf.1"
P1-2
P1-3
P5-0

P5-1
P5-2
P5-3

P5-6
P5-7
TEST

MK2870 BLOCK DIAGRAM
Figure 3

EXTINT
XTL1

XTL2

~

MEMORY ADDRESS BUS

ROM

MAIN
CONTROL
lOGIC

RESULT BUS

TEST

liD (3)

liD (1)

Crystal, LC, RC, or external clock. In addition, the user can
specify either a ±10% power supply tolerance or a ±5%
power supply tolerance.

PIN NAME

DESCRIPTION

TYPE

PO-7
P1-1 -- P1-3
P4-0 -- P4-7
P5-0 -- P5-7
STROBE
EXTINT
RESET
TEST
XTL 1, XTL 2
Vcc' GND

liD Port 0 Bit 7
I/O Port 1 Bits 1-3
liD Port 4
liD Port 5
Ready Strobe
External Interrupt
External Reset
Test Line
Time Base
Power Supply
Lines

Bidirectional
Bidirectional
Bidirectional
Bidirectional
Output
Input
Input
Input
Input
Input

I/O (8) STROBE

liD (8)

STROBE is a ready strobe associated with I/O Port 4. This
pin, which is normally high, provides a single low pulse after
valid data is present on the P4-0--P4-7 pins during an
output instruction.
RESET may be used to externally reset the MK2870. When
pulled low the MK2870wili reset. When then allowed to go
high the MK2870 will begin program execution at program
location H '000'.
EXT INT is the external interrupt input. Its active state is
software programmable. This input is also used in
conjunction with the timer for pulse width measurement
and event counting.
XTL 1 and XTL 2 are the time base inputs to which a crystal,
LC network, RC network, or an external single-phase clock
may be connected. The time base network must be
specified when ordering a mask ROM MK2870.

FUNCTIONAL PIN DESCRIPTION
PO-7, p:j"':1--P1-3, P4-0--P4-7, and P5-0--P5-7 are 20 lines
which can be individually used as either TIL compatible
inputs or as latched outputs.

TEST is an input, used only in testing the MK2870. For
normal circuit functionality this pin may be left
unconnected, but it is recommended that TEST be
grounded.
Vce is the power supply input (single +5 V).

VIII-32

MK2870 ARCHITECTURE

MK2870 MAIN MEMORY

The basic functional elements of the MK2870 are shown in
Figure 3. A programming model is shown in Figure 4. The
MK2870 is instruction set compatible. The unique features
of the MK2870 are discussed in the following sections. The
user is referred to the 3870 FamilyTechnical Manual for a
thorough discussion of the architecture, instruction set, and
other features.

There are four address registers used to access main
memory. These are the Program Counter (PO), the Stack
Register (P), the Data Counter (DC), and the Auxiliary Data
Counter (DC1). The Program Counter is used to address
instructions or immediate operands. The Stack Register is
used to save the contents of the Program Counter during an
interrupt or subroutine call. Thus, the Stack Register

MK2870 PROGRAMMABLE REGISTERS, PORTS,
AND MEMORY MAP
Figure 4
I

CPU REGISHRS

0 PORTS

BI:IIARY
TIMER

SCRATCHPAD MFMORY

ACCUMULATOR

PORT 7

SCRATCHPAD

DEC

~o

7 __ -8 BITS-__ 0

HEx

OCl

o

I
INTERRUPT
CONTROL PORT

STATUS
REGISTER

PORT 6

J

,2

KU

",2

14

Kl

13

,5

au

14

16

al

,5

,7

Hl

o
T
R R
C F
N l
0
W

PARALLEL
I 0 PORTS
PORT 5

PORT 0

C

S

A
R
R

I
G
N

4"
5 SITS . 0
INDIRECT
SCRATCHPAD
ADDRESS REGISTER

PORT 4

PORT,

l
E
R
o

I
I

I~

IISU

5

7_8BITS_o

, 3

61

3D

75

62

3E

76

63

3F

77

DEC

HEX

0
1

0
1

1022
1023

3FF
3FF

•

1

ISl

32
0
-SSITS_

PROGRAM
COUNTER

I

PO

I

pou

POL

I

0
11
87
_12BITS_

ROM

STACK
REGISTER
Pl 1
0

I PU
11

NOTE: All 32 parallel 1/0
port pins are available in the
MK2870. However. only 20 of the
bits are connected to 1/0 pins.
Refer to the pin diagram for
complete definition.

"

,0

HU

87
-12BITS-

~

~

DATA
COUNTER
DC
DCI 1
IDCU
I
87
11
0
-12BITS_

AUx DATA
COUNTER

"

I

DC ILl

87
0
-12BITS-

VIII-33

2046
2047

7FE

7FF

I
I
I
I
I
I

~

7"'-8 BITS--.. 0

DC'
IDCIU

I

--

4032

4033

4094
4095

FCO
FCl

MRK~~76~~ 0

MK2870 MAIN MEMORY
SIZE AND TYPE
Figure 5

o~

400 1024
3FF 1023

00000000

2870/10

This device contains 64 bytes of scratchpad RAM.
NOTE:
Data derived from addressing any locations other than
those within a part's specified ROM space or RAM space
(if any) is not tested nor is it guaranteed. Users should
refrain from entering this area of the memory map.

Device

MK2870/10

Scratchpad
RAM Size
(Decimal)

Address
Register Size
(PO, p, DC, DC1)

ROM
Size
(Decimal)

Executable
RAM Size
(Decimal)

64 bytes

12 bits

1024 bytes

o bytes

VIII·34

I/O PIN CONCEPTUAL DIAGRAM WITH OUTPUT
BUFFER OPTIONS
Figure 6

PORT
1/0
PIN

z
o

i=

C!l

.~

Z

o

u
a:

o

....
a:
o0-

....

C

C


CXI

....

Internal ep clock

210

2to

WRITE

tw

Internal WRITE Clock period

4tep
6tep

4tep
6tep

I/O

tdl/O

Output delay from internal
WRITE clock

0

t sl/O

Input setup time to internal
WRITE clock

1000

tl/O-s

Output valid to STROBE delay

tsL

STROBE

RESET

EXTINT

500
400
400

1000

500
390
390

0

1200

1200

ns
ns
ns

4 MHz - 2 MHz

Short Cycle
Long Cycle
ns

50 pF plus
one TTL load

ns

I
3tep
-1000

3tep
+250

3tep
-1200

3tep
+300

ns

I/O load =
50 pF + 1 TTL load

STROBE low time

Step
-250

12tep
+250

8tep
-300

12tep
+300

ns

STROBE load =
50 pF + 3TTL loads

tRH

RESET hold time, low

6tep
+750

6tep
+1000

t RPoe

RESET hold time, low for power
clear

power
time+O.l

power
supply
rise
time + .15

6tep
+750

6tep
+1000

ns

To trigger
interrupt

2tep

2tep

ns

To trigger timer

tEH

EXT INT hold time in active and
inactive state

•

UNIT NOTES

supply
rise

VIII-41

ns

ms

DC CHARACTERISTICS
TA' Vee within specified operating range
I/O power dissipation :5 100 rnW (Note 2)

-00, -05
SYMBOL

PARAMETER

Icc

Average Power Supply Current

Po

Power Dissipation

V IHEX

External Clock input high level

2.4

5.8

V ILEX

External Clock input low level

-.3

.6

IIHEX

External Clock input high current

IILEX

External Clock input low current

VIHI/O

Input high level, I/O pins

V IHR

V IHEI

Input high level, RESET

Input high level, EXT INT

MIN

MAX

-10,-15
MIN

MAX

UNIT DEVICE

85

110

rnA

MK2870/10
Outputs Open

400

525

rnW

MK2870/10
Outputs Open

2.4

5.8

V

-.3

.6

V

100

130

/-LA

VIHEX=VCC

-100

-130

/-LA

VILEX=VSS

2.0

5.8

2.0

5.8

V

Standard pull-up

2.0

13.2

2.0

13.2

V

Open drain (1)

2.0

5.8

2.2

5.8

V

Standard pull-up

2.0

13.2

2.2

13.2

V

No Pull-up

2.0

5.8

2.2

5.8

V

Standard pull-up

2.0

13.2

2.2

13.2

V

No Pull-up

-.3

.8

-.3

.7

V

(1 )

V IL

Input low level

IlL

Input low current, all pins with
standard pull-up resistor

-1.6

-1.9

rnA

V IN = 0.4 V

IL

Input leakage current, open drain
pins, and inputs with no pull-up resistor

+10
-5

+18
-8

/-LA
/-LA

V OH = 13.2 V
V IN = O.OV

IOH

Output high current pins with standard
pull-up resistor

-100

-89

p,A

VOH = 2.4 V

-30

-25

/-LA

VOH = 3.9V

VIII-42

DC CHARACTERISTICS (cont.)
TA' Vee within specified operating range, I/O power dissipation;::: 100 mW (Note 2)

-00, -05
SYM

PARAMETER

MIN

IOHDD

Output high current, direct drive
pins

-100
-1.5

MAX

-10,-15
MIN

MAX

mA
mA

V OH = 2.4 V
V oH =1.5V
V OH = 0.7 V

p.A

-80
-1.3
-8.5

UNIT CONDITIONS

-11

-300

-270

p.A

V OH = 2.4 V

Output low current

1.8

1.65

mA

VOL = 0.4 V

STROBE Output Low current

5.0

4.5

mA

VOL = 0.4 V

IOHS

STROBE Output High current

IOL
IOLS

TIMER AC CHARACTERISTICS
Definitions:
Error = Indicated time value - actual time value
tpsc = tlfl x Prescale Value
Interval Timer Mode:
Single interval error, free running (Note 3) ............................................................ ±6tlfl
Cumulative interval error, free running (Note 3) ........................................................... 0
Error between two Timer reads (Note 2) ........................................................ ±(tpsc + tlfl)
Start Timer to stop Timer error (Notes 1,4) ................................................ +tlfl to - (tpsc + tlfl)
Start Timer to read Timer error (Notes 1, 2) .............................................. -5t Ifl to - (tpsc + 7tlfl)
Start Timer to interrupt request error (Notes 1, 3) ............................................... -2tlfl to -8 tlfl
Load Timer to stop Timer error (Note 1) .................................................. + tlfl to - (tpsc + 2tlfl)
Load Timer to read Timer error (Notes 1, 2) ............................................ -5tlfl ± to - (tpsc + 8tlfl)
Load Timer to interrupt request error (Notes 1, 3) ............................................... -2tlfl to -9tlfl
Pulse Width Measurement Mode:
Measurement accuracy (Note 4) ........................................................ + tlfl to - (tpsc + 2tlfl)
Minimum pulse width of EXT INT pin .................................................................. 2tlfl
Event Counter Mode:
Minimum active time of EXT INT pin .................................................................. 2tlfl '
Minimum inactive time of EXT INT pin ................................................................. 2tlfl
NOTES:
1. All times which entail loading, starting, or stopping the Timerare referenced
from the end of the last machine cycle of the OUT or OUTS instruction.
2. All times which entail reading the Timer are referenced from the end of the
last machine cycle of the IN or INS instruction.
3. All times which entail the generation of an interrupt request are referenced
from the start of the machine cycle in which the appropriate interrupt
request latch is set. Additional time may elapse if the interrupt request
occurs during a privileged or multicycle instruction.
4. Error may be cumulative if operation is repetitively performed.

VIII-43

•

AC TIMING DIAGRAM
Figure 13

External Clock

Internal 

I- I- iL: z o o Il. o Il. a: a: C!l U o 6 w a: ct w a: o o ct o ....I a: ~ CI) ::> II) ct ct I- o OUTPUT BUFFER OPTIONS (MASK PROGRAMMABLE) STANDARD OUTPUT OPEN DRAIN OUTPUT DIRECT DRIVE OUTPUT Ports 0 and 1 are Standard Output type only. Ports 4 and 5 may both be any of the three output options (mask programmable bit by bit) The STROBE output is always configured similar to a Direct Drive Output except that it is capable of driving 3 TTL loads. RESET and EXT INT may have standard 6Kfl (typical) pull-up or may have no pull-up (mask programmable). These two inputs have Schmitt trigger inputs with a minimum of 0.2 volts of hysteresis. Serial In is a Schmitt trigger input with a minimum of O.2V hysterisis. Serial Out (SO) is the Standard Output type. SRClK output is capable of driving 3 TTL loads. VIII-54 PORT D SERIAL PORT CONTROL REGISTER SERIAL PORT REGISTERS Figure 5A The Serial Port Control register is write only and is addressed as Port D. The bit assignment is pictured in Figure 5C. The function of each bit is described below. TRANSMIT BUFFER N2, N1, NO - WORD LENGTH SELECT SERIAL OUT These bits select one of the eight possible word lengths which are available with the MK3873 serial port. The serial port will shift the programmed number of bits through the Shift Register. If the Transmit mode is selected, data will be shifted out of the least significant bit (SRO) of the Shift Register to the Serial Out line (SO) while data is simultaneosly sampled at the Serial Input (51) line and shifted into the most significant bit (SR15) of the Shift Register. When the Receive mode is selected, data will be sampled at 51 and shifted in, but the SO line will be disabled such that it remains in a marking condition (Logic "1 "). After the programmed number of bits have been shifted, the serial port logic will generate an endof-word condition. This end-of-word condition will cause an interrupt if the serial port INTERRUPT ENABLE bit has been set. RECEIVE BUFFER Figure 58 SERIAL PORT STATUS REGISTER o _ BIT NO :~:~DI==:===:======i==================== , [ - - OVFl UNDFl L__ READY OVERFLOW UNDERFlOW Figure 5C It should be noted that the word values have been chosen so that the MK3873 can be programmed to send and receive a wide variety of asynchronous serial codes with various combinations of start and stop bits. Shown in Figure 6 is a table which gives the word length. SERIAL PORT CONTROL REGISTER PORT D WRITE ~ WORD LENGTH SELECT N2 N1 NO o 0 0 o 0'1 010 o 1 1 Values which would be programmed into the MK3873 Serial Port Register for Baudot, ASCII and 8 bit binary codes in an asynchronous word format are shown in the table of Figure 6. Shown in the table are word length values for various combinations of data bits, start and stop bits, and parity. It can be seen that the MK3873 serial port can accommodate many different word lengths of asynchronous or synchronous data. o o 0 1 1 0 1 1 WORD LENGTH 4 Bits 7 Bits 8 Bits 9 Bits 10 Bits 11 Bits 12 Bits 16 Bits ASYNCHRONOUS WORD LENGTHS Figure 6 DATA WORD BAUDOT ASCII #OF BITS START BITS STOP BITS PARITY 5 5 5 5 7 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 2 1 2 1 2 1 2 1 2 No No Yes Yes No No Yes Yes No No Yes Yes 7 7 7 8 Bit Binary 8 8 8 8 VIII-55 WORD LENGTH (BITS) 7 8 8 9 9 10 10 11 10 11 11 12 • START DETECT SEARCH When the START DETECT bit is enabled the serial port will not shift data through the Shift Register until a valid start bit is detected at the SI input pin. The Start Detect mode is operative only when the Async mode has been selected by programming bit 2 of the Serial Port Control Register to a logic "0". By selecting the Async mode, the internal SHIFT clock frequency is divided by 16 from the clock frequency at the SRCLK pin. (Recall that SRCLK can be an input or an output depending on whether the internal baud rate generator or the external clock is selected). When the START DETECT bit is set, the serial port logic looks for a high to low transition on the SI input. Until this transition occurs, the internal SHIFT clock is held low and no data is shifted in through the shift register. Once the transition is sensed, the SI input will be sampled on every SRCLK pulse for seven clock periods. If the logic level remains at zero on the SI input for each ofthe seven clock periods, the serial port logic will begin shifting data into the Shift Register on the eighth SRCLK pulse. Data will be shifted in at the +16 or SHIFT clock rate until the number of bits which have been programmed into the word length select have been shifted in. Once the programmed number of bits have been shifted in, the start detect circuitry will be rearmed and will begin searching for the next high-to-Iow transition on SI. This operation is pictured in the example shown in Figure 7. The SEARCH bit is enabled by programming it to a logic "1 ". When enabled, the SEARCH bit causes the serial port logic to generate an interrupt at every bit time if the serial port interrupt has been enabled. This interrupt will occur regardless of whether the Transmit or Receive mode has been selected and whether the Synchronous or Asynchronous mode has been selected. The Search mode is usually used for recognition of a sync character in synchronous serial data transmission. The MK3873 serial port does not automatically detect sync characters. SYNC/ASYNC The SYNCI ASYNC bit is used to select either the Synchronous mode of operation or the Asynchronous mode of operation. "In the Synchronous mode of operation data is shifted through the Shift Register at a rate which is +1 the rate of SRCLK. When the Synchronous mode is selected, the start bit detect circuitry cannot be enabled, even if the START DETECT bit is programmed to a "1 ". In the Asynchronous mode (SYNCI ASYNC =0) the internal SHIFT clock operates at a rate which is +16 the rate of SRCLK. XMIT/REC The XMIT IREC bit is used to select either the Transmit or Receive modes of operation. When programmed to a "1 " XMIT is selected and the serial port will shift data on the SO line as well as shift data into the SI input. Transmitted data will be enabled on the SO output on the falling edge of the internal SHIFT clock. When the Receive mode is selected (by programming XMIT IREC = 0), data will be clocked into the Shift Register on the rising edge of SHIFT, as it is when the When the START DETECT bit is disabled, data is continuously shifted through the Shift Register. An end-ofword condition will be generated each time the programmed number of bits has been shifted into or out of the Shift Register. A serial port interrupt will be generated when the end of word condition occurs if it has been enabled. MK3873 SERIAL PORT START BIT DETECTION Figure 7 ~--- ASYNCHRONOUS DATA WORD NEW - - - - - - -.....--l ......~-----WORD I --1_ ~~._~ _1----'-----;1f---1"-----1 c::J _____ ~ ____ -:-55- ___ :_____ ~__ IIIIII r!~~i: STOP IIIIIII ( :~~::ClK ----~~-------------~)7~-----------------=~------------- ru SHIFT BIT COUNT EDGE DETECT REARMED (END OF WORD CONDITION) I 00 01 02 03 N-' N 00 where N is the word length value selected by programming bits N2-NO in the serial port control register VIII-56 01 Transmit mode is enabled, but data will be disabled from being shifted out on Serial Out. Serial Out will be held at a marking, or logic "1 ", condition. SERIAL PORT INTERRUPT ENABLE By programming this bit to a "1 ", the serial port interrupt will be enabled. A serial port interrupt may then occur when an end-of-word condition is generated. Program control will be vectored to one of two locations upon a serial port interrupt, depending on thewaytheXMITIREC bit has been programmed. If the Transmit mode has been selected by programming XMITIREC bit to a "1 ", then program control will be vectored to location EO (Hex). For the Receive mode (XMITIREC = 0) program control will be vectored to 60 (Hex) when the serial port interrupt occurs. With the addition of the Serial Port Interrupt, the MK3873 has three sources of interrupt. If these three interrupts were to occur simultaneously, priority between them would be such that they would be serviced in the following order: 1) Serial Port 2) Timer 3) External Interrupt STATUS REGISTER Reading port D of the MK3873 by performing an Input or Input Short (IN or INS) instruction will load the contents of the Serial Port Status Register into the Accumulator. ,The two bits which make up the Status Register are shown in Figure 5B. The operation of these two bits is described below: READY - The meaning of the READY flag depends on whether the Transmit or Receive mode is selected. When the Transmit mode has been selected, the READY flag is set when a Transmit Buffer empty condition occurs. This means that any previous data which may have been loaded into the Transmit Buffer register pair has been transferred into the Shift Register. Loading either byte of the Transmit Buffer will clear the READY flag until the time that the Transmit Buffer register pair is loaded into the Shift Register during an end-of-word condition In the Receive mode (XMITIREe = 0), the READY flag is used to indicate a Receive Buffer full condition, This means that a word of the programmed length has been shifted in and has been loaded into the receive buffer register pair. Reading one of the ports E or F which make up the receive buffer register pair will clear the READY flag. The READY flag will remain a 0 until the next word is completely shifted in and loaded into the receive buffer. OVFL/UNDFL is like the READY flag; the meaning of OVFL/UNDFL depends on the programming of the XMIT IREC bit in the Serial Port Control Register. When the Transmit mode has been selected OVFL/UNDFL is used to indicate a transmitter underflow condition. A transmitter underflow condition can occur as follows: Assume that the Transmit mode is selected. Suppose that a word is loaded into the Transmit Buffer register. The serial port logic will load the contents ofthe Transmit Buffer into the Shift Register and will begin to shift the word out on the SO pin. When the contents of the Transmit Buffer are loaded into the Shift Register, the serial port logic will signal the Transmit Buffer empty condition by setting the READY flag to a "1 ". When the word in the Shift Register is completely shifted out, an end-of-word condition will be generated. The serial port logic will then check to see if new data has been loaded into the Transmit Buffer. If it has not the OVFL/UNDFL flag will be set indicating that the serial port logic has run out of data to send. The OVFL/UNDFL flag can be usedto signal an error condition to the firmware, or it can be used to signal that all data has been cleared out of the Shift Register for the purposes of line turnaround. The OVFL/UNDFL flag which, in this case, represents a transmitter underflow condition, is reset by reading the Status Register. When the Receive mode is programmed, OVFL/UNDFL is used to signal that the Receive Buffer has overflowed. This overflow condition can occur as follows: Suppose that a serial word is shifted in, generating an end-of-word condition. The serial port logic will load the contents of the Shift Register into the Receive Buffer, and will set the READY flag to a "1" to indicate that the Receive Buffer is full. When the next word being received is completely shifted in, generating the next end-of-word condition, the serial port logic will check to see if the Receive Buffer has been read by examining the state of the READY flag. If the READY flag = 0, then the previous word has already been read from the Receive Buffer by the software and the serial port logic will load the current word into the Receive Buffer and will again set the READY flag. If the READY flag = 1, then the previous word has not been read from the Receive Buffer. The serial port logic will load the new word into the Receive Buffer, destroying the previous word. This action is signalled by the serial port logic setting the OVFL/UNDFL to a "1" signalling a receive buffer overflow condition. In this case reading the status register also clears the OVFL/UNDFL flag. BAUD RATE CONTROL REGISTER Port C is designated as the Baud Rate Control register. Four bits, 0-3, are used to select nine different internal baud rates or an external clock. When an internal baud rate is programmed, the SRCLK output is generated at a frequency which is divided from the MK3873's time base frequency. The SRCLK frequency can be calculated by dividing the time base frequency by the divide factor shown in Figure 8 forthe bit pattern which is programmed into bits C3-CO. Also shown in Figure 7 is the programming of bits C3-CO to obtain a set of standard baud rates when a 3.6864MHz crystal is used as a time base. VIII-57 • BAUD RATE CONTROL PORT PORT C WRITE ONLY word, it is usually necessary to insert start and stop bits in software into the 16 bit word which is to be loaded in two halves into the Transmit Buffer register. Figure 8 7 PORTC WRITE 6 5 4 3 2 1 0 Bit No. Shift Clock Rate (" 3.6864 MHz time base ~IC3IC2IC1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 SRCLK Ico! Divide Factor SYNC .,.24 1 1 153.6 kbs 1 0 76.8 kbs "'48 0 1 38.4 kbs "'96 0 0 19.2 kbs "'192 1 1 9600 bps "'384 1 0 4800 bps "'768 0 1 2400 bps "'1536 0 0 1758.8 bps "'2096 1 1 73072 1200 bps 0 0 External Clock Mode RESET ASYNC 9600 4800 2400 1200 600 300 150 110 75 bps bps bps bps bps bps bps bps bps When any of the internal baud rates are selected, pin 36 becomes an output port pin. This pin is capable of driving three standard TIL inputs and provides a square wave output from the frequency selected in port C. The SYNCI ASYNC bit in the Serial 110 Control register has no effect on the output clock rate. The output will always be +1 directly from the baud rate generator. If all zeros are loaded into this port, the External Clock mode is selected. Pin 36 becomes an input. Any TIL compatible square wave input can be used to generate the clock for the serial port. TRANSMIT AND RECEIVE BUFFERS The Receive Buffer registers are two eight bit registers which are addressed as ports E and F (Hex) and are read only. The Receive Buffer registers may be read at any time. The Transmit Buffer registers are also two 8-bit registers which are write only and addressed as ports E and F (Hex). In the Receive mode, the contents of the 16 bit Shift Register are transferred to the Receive Buffer Register pair when a complete word has been shifted in. Bits SR15-SR8 of the Shift Register are loaded into bits 7-0 of port E while bits SR7-SRO are loaded into bits 7-0 of Port F. When entering the Transmit mode, the first data transfer from the Transmit Buffer to the 16 bit Shift Register won't occur until a 1 word time delay after entering Transmit Mode. In the Receive mode, no transfers between the Transmit Buffer and the 16 bit Shift Register can occur. The serial port does not automatically right justify incoming data, nor does it insert or strip start and stop bits from an asynchronous data word. Therefore, it is usually necessary to right justify incoming data read from the Receive Buffer registers in software through shift instructions, as well as strip start and stop bits if an asynchronous data format is being used. Likewise, in transmitting an asynchronous data The reset circuit on the MK3873 is used to initialize the device to a known condition either during the course of program execution or on a power on condition. This section discusses the effect of RESET on the serial port logic. A more complete description of RESET may be found in the 3870 Family Technical Manual. Upon reset, both the serial port control register (port D) and the Baud Rate Control register (port C) are loaded with zeroes. This action sets the serial port control logic in the following state: N2, N 1, NO (word length) = 4 bits START DETECT disabled SEARCH disabled Asynchronous Receive mode Serial port interrupt disabled External Clock mode (SRCLK = 1). Ports E and F are undefined After the first control word is written to the Serial Port Control Register which selects an internal clock mode, the SRCLK will become an output and will remain high for one-half of a clock period as programmed into port C. It will then go low and produce a clock output waveform with the selected frequency. ASYNCHRONOUS RECEIVE OPERATION Figure 7 illustrates the timing for an example using the serial port in the Asynchronous mode. When operating in this mode, the Serial Port Control Register should be programmed for receive (XMITIREC = 0) and the START DETECT bit should be enabled. Also, the Async mode should be selected, which allows the start detect circuitry to operate and sets the internal SHIFT clock at a rate which is divided by 16 (+16) from the SRCLK rate. Upon selecting the Async mode and the START DETECT bit, the internal SHIFT clock is held low until a negative transition occurs on the SI pin. After a valid edge has been detected (see the START DETECT bit operation section) the SHIFT clock will go high and data will be shifted in at the middle of each bit time. When the programmed number of bits have been shifted in, an end-of-word condition is generated and a serial port receive interrupt will occur if it has been enabled. After the falling edge of SHIFT following the end-of-word interrupt, the start detect circuitry will be enabled in preparation for the next word. Thus, if a start bit is present immediately following the time when the start detect circuitry is enabled, SHIFT Clock will again go high approximately one bit-time after the riSing edge of SHIFT which clocked in the last bit of the preceeding word and caused the end-of-word interrupt. In other words, SHIFT VIII-58 SYNCHRONOUS TRANSMIT OR RECEIVE TIMING Figure 9 SYNCHRONOUS- - - - - r - - - -,- - - - DATA STREAM , 1 _ _ _ _ _ I _ _ _ _ _1_ _ _ _ I - - - -,--n- - --,- - - --,- - 1 , -.J _ _ _ _ ..l. --? r- __ L, - - - - , 1- - ---1- ---- : ____ - - - SHIFT CLOCK rs BIT COUNT N 00 01 02 )5 can go high again on the eighth SRCLK pulse as soon as the start detect circuitry is rearmed. The Shift Register may be read before the next end-of-word condition; otherwise, a receiver overrun error will occur. For a 9600 bps data rate, this would require reading the Receive Buffer within N x 104 j.Ls from the time that the end-of-word condition is generated, where N is the number of bits in the data word. The example in Figure 7 shows the timing required for asynchronous data reception from a device such as a teletype. Within this data stream are start, data and stop bits. A typical format requires 1 start bit, 8 data bits and 2 stop bits for a total of 11 bits. All of these bits will be residing in the 16 bit Shift Register when the end-of-word interrupt is generated. It is, therefore, necessary to strip the start and stop bits from the data. SYNCHRONOUS RECEIVE OPERATION For synchronous operation, the START DETECT bit should not be enabled and the XMITIREC bit should be programmed to a zero. Also the Sync mode should be enabled so that the internal SHIFT clock is divided by 1 ,or is equivalent to, SRCLK. Once a control word is written to port D specifying START DETECT = 0, Receive mode, and Sync mode, then the Serial Port will continuously shift data into the MSB of the upper half of the Shift Register at the SRCLK rate and will generate an end-of-word condition when the programmed number of bits have been shifted in. An illustration of synchronous receive timing is shown in Figure 9. This diagram is a synchronous receive sequence for a word which is N bits in length, where N corresponds to the number of bits which have been programmed into the Serial Port Control Register. Note the relationship of SHIFT clock, the synchronous data stream, and the bit count. Since the START DETECT bit is not enabled, the serial port logic N-1 N 00 will continuously shift data in and generate end-of-word conditions at regular intervals. When the end-of-word condition occurs, a serial port receive interrupt occurs if it has been enabled, and the contents of the Shift Register will be loaded into the Receive Buffer. The serial port logic will set the READY flag in the Serial Port Status Register, indicating that the receive buffer is full. Since the serial port is double-buffered on receive, the program has entire word time to read the Receive Buffer. At 9600 bps this corresponds to a word time of N x 104j.Ls, where N is the number of bits in a word. Note that if a new control word is written to port D during the time that a serial word is shifted in, the bit count will be reset. When using the Synchronous Receive mode on the MK3873, it is usually necessary to establish word synchronization in the data stream. The SEARCH bit, when enabled, causes the serial port logic to interrupt on each rising edge of SHIFT so that the data stream can be examined on a bit by bit basis. When the last bit of a sync word is found, the Search mode can be disabled and the serial port logic will shift in data and interrupt at the word rate. ASYNCHRONOUS TRANSMIT OPERATION The Asynchronous Transmit mode of operation is initiated by setting the XMIT IREC bit to a "1 ", and by programming the SYNCI ASYNC bit to a "0". Also, there must be an SRCLK pulse by selecting an internal or external source for SRCLK by programming port C. Upon setting XMITIREC to a "1 ", there will be a 1 word length delay prior to the actual transfer of the first word from the Transmit Buffer to the 16 bit Shift Register. Serial data will then be shifted to the right on each rising edge of the internal SHIFT clock, and each new bit in the data stream will be enabled onto the SERIAL OUTPUT pin (SO) at the time of the falling edge of the VIII-59 • internal SHIFT clock. As mentioned, one word time delay is generated between the time that the Transmit mode is initiated by programming XMITIifEC = 1 and the time that the contents of the Transmit Buffer are transferred into the Shift Register. This word time delay is generated internally to the MK3873 by counting the number of SHIFT clock pulses which correspond to the number of bits programmed into the word length select section of the Serial Port Control Register (N2, N1, NO). Therefore, the word time delay is equivalent to the time it takes to shift a complete serial data word out of the Shift Register. The same word time delay will result if data had been loaded prior to programming the XMIT IREC bit to a "1". As mentioned in the "START DETECT" bit description, the internal SHIFT clock is disabled when this bit is programmed to a "1". Sincethe serial port logic counts SHIFT clock pulses to generate the word time delay, the Transmit Buffer contents will never be transferred to the Shift Register and shifted out when the START DETECT bit is enabled. Also, the Transmit Buffer contents cannot be loaded into the Shift Register when XMITIREC bit =O. When the initial serial data word has been transferred into the Shift Register, the READY flag is set in the Serial Port Status Register which is used to indicate the Transmit Buffer is empty. A transmit interrupt will be generated if the INTERRUPT ENABLE bit has been set in the Serial Port Control Register, and program control will be vectored to location EO (hex). When operating the serial port in a polled environment with the serial port interrupt disabled, the READY bit can be used as a flag which indicates that new data may be loaded into the Transmit Buffer. In an interrupt driven software configuration, new data may be loaded into the Transmit Buffer at the beginning of the serial port interrupt service routine. During the operation of the Transmit Mode the SERIAL INPUT pin (SI) is sampled and shifted into the Shift Register. However, since the START DETECT bit must be disabled during a transmit sequence, there is no way of establishing bit synchronization on any incoming serial data. Therefore, in the Asynchronous mode, the serial port can only be used in a half-duplex configuration. After a block of data has been sent, it is sometimes useful for the program to know when the last serial word has been shifted out of the shift register. This is especially useful when operating the MK3873 with a bidirectional halfduplex transmission line. Once the block of serial data has been completely shifted out of the port, then it is usually desirable to reverse the direction of the line so that data may be received. One way of determining when the last word has been shifted out of the Shift Register is through the use of the OVFL/UNDFL status bit in the Serial Port Status Register. The sequence would take place as follows: The program loads the Transmit Buffer with the last serial data word which is to be sent out either when the "READY" bit is set or during a transmit interrupt service routine. Loading the Transmit Buffer clears the READY flag. At the next end-ofword condition, the last serial data word is transferred from the Transmit Buffer into the Shift Register, which sets the READY flag once again. At this point the program would not load any more data into the Transmit Buffer and the READY flag will remain set. When the last word is completely shifted out of the Shift Register, the serial port logic will check to see if any new data has been loaded into the Transmit Buffer register pair. When it determines that there is no new data in the Transmit Buffer, the serial port logic will set the OVFL/UNDFL bit in the serial port status register and will return the SERIAL OUTPUT pin (SO) to a marking condition (logic "1 "). The SERIAL OUTPUT pin (SO) is always returned to a marking condition on transmitter underflow when the ASYNC mode is selected. Since the OVFL/UNDFL bit is set when the last serial data word has completely been sent out, it can be used as a Signal to indicate the end of transmission and that the direction of the transmission line may be set for receive. SYNCHRONOUS TRANSMIT OPERATION The Synchronous Transmit mode of operation is selected by programming bit 2 (XMIT IREC) of the Serial Port Control register to a "1" and setting the SYNCI ASYNC bit to a "1". Figure 9 illustrates serial output timing relationships in the Synchronous mode. Data is shifted to the right on each rising edge of the internal SHIFT clock. Output data is not enabled to the SERIAL OUTPUT pin (SO) until the falling edge of the SHIFT clock. In a 16 bit data word, SRO, the least significant bit of the Shift Register is shifted out first, and SR15, the most significant bit ofthe Shift Register, is shifted out last. While the Shift Register contents are being output on a bit by bit basis, data is simultaneously shifted in to the Shift Register through the SI pin. As discussed in the "ASYNCHRONOUS TRANSMIT OPERATION" section, a word time delay is generated between the time that data is written to the Transm it Buffer and the time that the contents of the Transmit Buffer are loaded into the Shift Register once the XMITIREC bit has been programmed to a one (1). Another way of loading the initial data word into the Transmit Buffer requires the word synchronization having been achieved through recognition of a received sync character. Recall that in the Transmit mode, data is sampled at SI and shifted into the Shift Register at the same time that data is shifted out through SO. Upon power up or reset, a control word may be written to Port D which specifies Transmit and Synchronous modes. Word synchronization can then be achieved through the use of the SEARCH bit as described in the section which covers Synchronous Receive mode. Once word synchronization is achieved, the SEARCH bit is disabled and the serial port shifts in data and generates an end-of-word condition at the word rate. Each time the end of word condition is reached, receive data VIII-SO is transferred from the shift register into the Receive Buffer. At the same time, data is transferred from the Transmit Buffer into the Shift Register. Therefore, in the Synchronous Transmit mode, the serial port may be used in a full duplex mode if word synchronization is established. At each end of word condition, output data is transferred to the Shift Register from the Transmit Buffer. At the same time, an incoming data word is transferred from the Shift register to the Receive Buffer register pair. In this case, the End-of-Word transmit routine would be used for sending data by loading the Transmit Buffer register, and for receiving data by reading the Receive Buffer register. Note that once word synchronization is established, an amount of time which is equal to one word time is available following the end-ofword interrupt for loading data into the Transmit Buffer. The serial port operates differently in the Transmit mode for Synchronous operation than it does for Asynchronous operation. In the Asynchronous mode, after a word has been shifted out, the SO line is returned to a marking condition if no new data has been loaded into the Transmit Buffer. In the Synchronous mode, after a word has been shifted out, the contents of the Transmit Buffer are loaded into the Shift Register regardless of whether or not new data was loaded into the Transmit Buffer. If new data was not loaded since the last time the transmit buffer was read, the OVFL/UNDFL flag is set which signals a transmitter underflow condition. This feature of always reloading the Shift Register with the contents of the Transmit Buffer when an end-of-word condition occurs allows a sync word to be continuously generated without CPU intervention when the transmitter is idle. This feature also allows variable duty cycle, variable frequency waveforms to be generated on the Serial Output line. MK3873 CLOCKS The time base network used with the MK3873 may be one of the four different types listed below. Crystal LC RC External Clock The type of network which is to be used with the MK3873 is to be specified at the time when mask ROM MK3873 devices are ordered. The time base specification for each of the four modes are covered in the 3870 Family Technical Manual. is housed in the "R" package which incorporates a 28 pin socket located directly on top of the package. The MK38P73 can act as an emulator for the purpose of verification of user code prior to the ordering of mask ROM MK3870 devices. Thus, the MK38P73 eliminates the need for emulator board products. In addition, several MK38P73s can be used in prototype systems in order to test design concepts in field service before committing to high-volume production with mask ROM MK3873s. The compact size of the MK38P73/EPROM combination allows the packaging of such prototype systems to be the same as that used in production. Finally, in low-volume applications the MK38P73 can be used as the actual production device. Most of the material which has been presented for the MK3873 applies to the MK38P73. The MK38P73 has the same architecture and pinout as the MK3873. Additional information is presented in the following sections. MK38P73 MAIN MEMORY As can be seen from the block diagram in Figure 10, the MK38P73 contains no on-chip ROM. The memory address and data lines are brought out to the 28 pin socket located directly on top of the 40 lJin package. The MK38P73 will address up to 4096 bytes of external EPROM memory. There is one memory version of the MK38P73, and it is designated as the MK38P73/02. The MK38P73/02 contains 64 bytes of on-chip executable RAM. The MK38P73/02 can emulate the mask ROM MK3873/22 device. Addressing of main memory on the MK38P73 is accomplished in the same way as it is for the MK3873. See Figure 12 for Main Memory addresses and for address register size in the MK38P73. MK38P73 EPROM SOCKET A 28 pin EPROM socket is located on top of the MK38P73 "R" package. The socket and compatible EPROM memories is shown in Figure 11. When 24 pin memories are used in the 28 pin socket, they should be inserted so that pin 1 of the memory device is plugged into pin 3 of the socket. (The memory should be lower justified in the 28 pin socket.) MK38P73 GENERAL DESCRIPTION The 28-pin socket has been provided to allow use of both 24-pin and 28-pin memory devices. Minor pin-out differences in the memory devices must be accommodated by providing different versions of the MK38P73. The MK38P73 is the EPROM version of the MK3873. It retains an identical pinout with the MK3873. The MK38P73 Initially, the MK38P73 that is compatible with the MK2716 is available. The MK38P73 designedto accommodate the 28- VIII-61 • MK38P73 BLOCK DIAGRAM EXT INT Figure 10 SERIAL SERIAL SERIAL CLOCK INPUT 1511 SRCLK OUTPUT 1501 MK38P73 "R" PACKAGE PINOUT Figure 11 pin memory devices will be available at a later date. Vee vee 2S vss vee 27 A7 Vee 26 A6 AS 2S AS A9 24 A4 Vee 23 A3 Vss 22 A2 A 10 21 A1 A11 AO 07 00 06 01 Os 02 04 Vss 03 MK97310 (Open Drain) Compatible Memories 2758 MK2716 2516 2532 MK38P73 I/O PORTS The MK38P73 is offered with open drain type output buffers on Ports 4 and 5. This open drain version is provided so that user-selected open drain port pins on the mask ROM MK38P73 can be emulated prior to ordering those mask ROM parts. Figure 11 lists the part ordering numberfor an MK38P73/02. MEMORY ACCESS TIMING A timing diagram depicting the memory access timing of the MK38P73 is shown in Figure 13. The t Internal clock 210 210 WRITE tw Internal WRITE Clock period 4t 6t 4t 6t I/O tdl/O Output delay from internal WRITE clock 0 tsl/O Input setup time to internal WRITE clock 1000 tl/O-s Output valid to STROBE delay 3t -1000 3t +250 3t -1200 3t +300 ns I/O load = 50pF + 1 TIL load tsL STROBE low time 8t -250 12t +250 8t -300 12t +300 ns STROBE load = 50pF+3TILloads tRH RESET hold time. low 6t +750 STROBE RESET tRPOC RESET hold time. low for power clear EXTINT tEH EXT INT hold time in active and inactive state 1000 0 1200 ...-. tit +1000 power power supply supply rise rise time tlrne 01 015 6t +750 2t 6t +1000 2t VIll-65 1200 UNIT NOTES 4MHz-2MHz Short Cycle Long Cycle ns 50pF plus one TIL load ns ns ms ns ns To trigger interrupt To trigger timer • CAPACITANCE TA = 25°C All Part Numbers MIN SYM PARAMETER CIN Input capacitance; 1/0, RESET, EXT INT, TEST CXTL Input capacitance; XTLl, XTL2 23.5 MAX UNIT 10 pF 29.5 pF NOTES unmeasured pins grounded AC CHARACTERISTICS FOR SERIAL I/O PINS TA. VCC within specified operating range. I/O Power Dissipation::; 1oomW (Note 2) -00, -05 SIGNAL SYM PARAMETER SRCLK tC(SRCLK) MIN MAX MIN Serial Clock Period in External Clock Mode 3.3 00 00 tw(SRCLKH) Serial Clock Pulse Width, High. External Clock Mode 1.3 00 00 J.1.S tw(SRCLKL) Serial Clock Pulse Width, Low. External Clock Mode 1.3 00 00 J.1.S tr(SRCLK) Serial Clock Rise Time Internal Clock Mode 60 60 ns 0.8V-2.0V CL = 100pf tf(SRCLK) Serial Clock Fall Time Internal Clock Mode 30 30 ns 2.4V -O.4V CL = 100pf tS(SI) Setup Time To Rising Edge of SRCLK (SYNC Mode) 0 0 ns tH(SI) Hold Time From Rising Edge of SRCLK (SYNC Mode) 1500 1500 ns tD(SO) Data Output Delay From Falling Edge of SRCLK (SYNC Mode) 1190 1190 ns i SI S~ -10,-15 VIII-66 MAX UNIT CONDITIONS J.1.S AC CHARACTERISTICS FOR MK38P73 (Signals brought out at socket) TA' VCC within specified operating range. I/O Power Dissipation:::; 100mW (Note 2) -00, -05 SYMBOL PARAMETER taas* Access time from Address A11-Ao' stable until data must be valid at 07- 0 0 MIN MAX -10, -15 MIN MAX 650 UNIT CONDITION ns = 2.0MHz *See Table in Figure 13. DC CHARACTERISTICS TA, VCC within specified operating range 1/0 power dissipation:::; 100mW SYMBOL PARAMETER ICC Average Power Supply MIN MAX 103 MIN MAX 138 UNIT DEVICE mA MK3873/12 Outputs Open Current MK38P73/02 138 165 mA No EPROM, Outputs Open Po 485 Power Dissipation 645 mW MK3873/22 Outputs Open MK38P73/02 646 775 mW No EPROM, Outputs Open VIII-67 • DC CHARACTERISTICS TA, V CC within specified operating range 1/0 Power Dissipation:::; 1OOrnW (Note 2) -00,-05 -10,-15 MIN MAX MIN MAX External Clock input high level 2.4 5.8 2.4 5.8 V VILEX External Clock input low level -.3 .6 -.3 .6 V IIHEX External Clock input high current 100 130 JJA VIHEX=VCC IILEX External Clock input low current -100 -130 JJA VILEX=VSS VIHI/O 1/0 input high level SYM PARAMETER VIHEX VIHR VIHEI Input high level, RESET Input high level. EXT INT UNIT CONDITIONS 2.0 5.8 2.0 5.8 V standard pull-up (1) 2.0 13.2 2.0 13.2 V open drain (1) 2.0 5.8 2.2 5.8 V standard pull-up (1) 2.0 13.2 2.2 13.2 V No pull-up 2.0 5.8 2.2 5.8 V standard pull-up (1) 2.0 13.2 2.2 13.2 V -.3 .8 -.3 0.7 V No pull-up (1) VIL 1/0 ports, RESET', EXT INT' input low level IlL Input low current, standard pull-up pins -1.6 -1.9 rnA VIN=0.4V IL Input leakage current, open drain pins RESET and EXT INT inputs With no pull-up resistor +10 -5 +18 -8 JJA JJA VIN=13.2V VIN=O.OV 10H Output high current, standard -100 -89 JJA VOH=2.4V pull-up pins -30 -25 JJA VOH=3.9V Output high current, -100 -80 JJA VOH=2.4V direct drive pins -1.5 rnA rnA VOH=1.5V VOH=0.7V 10HDD -1.3 -11 -8.5 10L Output low current, 1/0 ports 1.8 1.65 rnA VOL =O.4V 10HS STROBE Output High current -300 -270 JJA VOL =2.4V 10LS STROBE output low current 5.0 4.5 rnA VOL =O.4V VIII-S8 DC CHARACTERISTICS FOR MK38P73 (Signals brought out at socket) TA, V CC within specifiec operating range, 1/0 Power Dissipation::; 100mW. (Note 2) -00, -05 -10, -15 SYM PARAMETER ICCE Power Supply Current for EPROM VIL Input Low Level Data bus in -0.3 0.8 VIH Input High Level Data bus in 2.0 5.8 10H Output High Current -100 -30 -90 -25 pA pA VOH=2.4V VOH=3.9V 10L Output Low Current 1.8 1.65 mA VOL =0.4V IlL Input Leakage Current pA Data Bus in Float MIN MAX MIN -185 MAX UNIT CONDITION -185 mA -0.3 0.7 V 2.0 5.8 V 10 10 DC CHARACTERISTICS FOR SERIAL PORT 1/0 PINS TA, VCC within specified operating range 1/0 Power Dissipation::; 1OOmW (Note 2) -00, -05 SYM PARAMETER VIHS -10, -15 MIN MAX MIN MAX Input High for SI, SRCLK 2.0 5.8 2.0 5.8 V VILS Input Low level for SI, SRCLK -.3 .8 -.3 0.7 V IlLS Input low current for SI, SRCLK -1.9 mA VIL = 0.4V 10HSO Output High Current SO VOH = 2.4V VOL = 3.9V 10LSO -1.6 -100 -30 -90 -25 pA pA 1.8 1.65 mA VOL = 0.4V -300 -270 pA VOH = 2.4V 5.0 4.5 mA VOL = O.4V Output Low Current SO 10HSRC Output High Current SRCLK UNIT TEST CONDITIONS 10LSRC Output Low Current 1. RESET and EXT INT have internal Schmit triggers giving minimum .2V hysteresis. 2. Power dissipation for I/O pins is calculated by l (Vee - VIU (IIILI )+ l (Vee - VOH) (Iim+1) + l (VOL) (IOL) TIMER AC CHARACTERISTICS Definitions: Error = Indicated time value - actual time value tpsc = t x Prescale Value Interval Timer Mode: Single interval error, free running (Note 3) ............................................................. ±6t Cumulative interval error, free running (Note 3) ............................................................ 0 Error between two Timer reads (Note 2) ................................. . . . . . . . . . . . . . . . . . . . . . . .. ± (tpsc + t Start Timer to stop Timer error (Notes 1,4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. +t to -(tpsc +t to -(tpsc + 7t to -8t to -(tpsc + 2t to -(tpsc + 8t to -9t to -(tpsc +2t 4» Minimum pulse width of EXT INT pin ............................................................... 2t4> Event Counter Mode: Notes: 1. 2. 3. 4. Minimum active time of EXT INT pin ............................... . Minimum inactive time of EXT INT pin .............................. . 2t4> 2t4> All times which entail loading. starting. or stopping the Timer are referenced from the end of the last machine cycle of the OUT or OUTS instruction. All times which entail reading the Timer are referenced from the end of the last machine cycle of the IN or INS instruction. All times which entail the generation of an interrupt request are referenced from the start of the machine cycle in which the appropriate interrupt request latch is set. Additional time may elapse if the interrupt request occurs during a privileged or multicycle instruction. Error may be cumulative if operation is repetitively performed. AC TIMING DIAGRAM Figure 14 External Clock Internal

21 _ Pi6 V111-75 Pi4 TEST valid data are present on the P4-0 - P4-7 pins during an output instruction. PIN NAME DESCRIPTION TYPE PO-2- PO-7 Pf=5 - P1-7 P4-0 - P4-7 P5-0 - P5-7 STROBE EXTINT RESET TEST XTL 1, XTL 2 VCC, GND VSB VBB 1/0 Port 0 1/0 Port 1 1/0 Port 4 1/0 Port 5 Ready Strobe External Interrupt External Reset Test Line Time Base Power Supply Lines Standby Power Substrate Decoupling Bidirectional Bidirectional Bidirectional Bidirectional Output Input Input Input Input Input Input Input GENERAL DESCRIPTION The MK3875 Single Chip Microcomputer offers a Low Power Standby mode of operation as an addition to the 3870 Family. The Low Power Standby feature provides a means of retaining data in the executable RAM on the MK3875 while the main power supply line (Ved is at 0 volts and the rest of the MK3875 microcomputer is shut down. The executable RAM is powered from an auxiliary power supply input (VSB ) while operating in the Lower Power Standby mode. When V SB is maintained at or above its minimum level, data is retained in the executable RAM memory with a very low power dissipation. The MK3875 retains commonality with the rest of the industry standard 3870 family of single chip microcomputers. It has the same central processing unit, oscillator and clock circuits, and 64 byte scratch pad memory array. Also, the 3870's sophisticated programmable binary timer is included which provides three different operating modes. Two pins on the MK3875 are dedicated to the Low Power Standby mode and are designated as VSB and V BB . The RESET line serves to resetthe MK3875 and place it in a protected state so that the contents of the Executable RAM will remain unchanged when Vee isbeing powered down to o volts. All other pins on the MK3875 are identical in function to corresponding pins on the MK3870, so that pin compatibility is maintained. The MK3875 executes the entire 3870 instruction set. The MK38P75 microcomputer is the PROM based version of the MK3875. It is called the piggyback PROM (P-PROM)TM because of its packaging concept. This concept allows a standard 24-pin or 28-pin EPROM to be mounted directly on top of the microcomputer itself. The EPROM can be removed and reprogrammed as required with a standard PROM programmer. The MK38P75 retains the pinout and architectural features as other members ofthe 3870family. The MK38P75 is discussed in more detail in a later section. FUNCTIONAL PIN DESCRIPTION RESET - may be used to externally reset the MK3875. When pulled low, the Mk3875 will reset. When allowed to go high the MK3875 will begin program execution at program location H '000'. Additionally, when RESET is brought low all accesses of the executable RAM are prevented and the RAM is placed in a protected state for powering down Vee without loss of data. EXT INT is the external interrupt input. Its active state is software programmable. This input is also used in conjunction with the timer for pulse width measurement and event counting. XTL 1 and XTL 2 are the time base inputs to which a crystal (2 to 4 MHz), LC network, RC network, or an external singlephase clock may be connected. The time base network must be specified when ordering an MK3875. TEST is an input used only in testing the MK3875. For normal circuit function this pin may be left unconnected but it is recommended that TEST be grounded. Vee is the power supply input +5 V. V SB is the RAM standby power supply input. V BB is the substrate decoupling pin. A .01 micro-Farad capacitor is required which is tied between VBB and GND. MK3875 ARCHITECTURE The basic functional elements of the mask ROM MK3875 single chip microcomputer are shown in the block diagram in Figure 1. A programming model is shown in Figure 2. Much of the Mk3875 architecture is identical with the rest of the devices in the 3870family. The significant features of the MK3875 are discussed in the following sections. The user is referred to the 3870 Family Technical Manual for a thorough discussion of the architecture, instruction set, and other features which are common to the 3870 family. MAIN MEMORY The main memory section on the MK3875 consists of a combination of ROM and executable RAM. There are four registers associated with the main memory section. These are the Program Counter (PO), the Stack Register (P), the Data Counter (DC) and the Auxiliary Data Counter (DC1). The Program Counter is used to address instructions duri ng progra m execution. P is used to save the contents of PO during an interrupt or subroutine call. Thus, P contains the return address at which processing is to resume upon completion of the subroutine or the interrupt routine. PO-2 - PO-7, P1-0 - P1-7, P4-0 - P4-7, and P5-0 - P5-7 are 30 lines which can be individually used as either TIL compatible inputs or as latched outputs. The Data Counter (DC) is used to address data tables. This register is auto-incrementing. Ofthe two data counters only DC can access the memory. However, the XDC instruction allows DC and DC1 to be exchanged. STROBE is a ready strobe associated with 1/0 Port 4. This pin, which is normally high, provides a single low pulse after The length of the PO, P, DC, and DC1 registers for all MK3875 devices is 12 bits. Figure 3 shows the amounts of V111-76 MK3875 BLOCK DIAGRAM EXTINT Figure 1 MEMORY ADDRESS BUS MAIN CONTROL LOGIC ROM RESULT BUS TEST 1/0(6) 1/0 (8) 1/0 (8)STROBE 1/0 (8) RESET ROM and Executable RAM for each device in the MK3875 family. available for use as general purpose I/O pins. Ports 1,4, and 5 are all a full 8 bits wide. EXECUTABLE RAM The schematic of an 110 pin and available output drive options are shown in Figure 4. The upper bytes of the total address space in all MK3875 devices are RAM memory. As with the ROM memory, the RAM may be addressed by the PO and DC address registers. The executable RAM may be accessed by all 3870 instructions which address main memory indirectly through the Data Counter (DC) register. Additionally, the MK3875 may execute an instruction sequence which resides in the executable RAM. Note that this sequence cannot be done with the scratch pad RAM memory, which is the reason the term "executable RAM" is given to this additional memory. The contents of the executable RAM memory are preserved when the Low Power Standby mode is in operation. I/O PORTS The MK3875 provides 30 bits of bidirectional parallel I/O. These lines are addressed as Ports 0, 1,4 and 5. In addition, the Interrupt Control Port is addressed as Port 6 and the binary timer is addressed as Port 7. The programming of Ports 6 and 7 and the bidirectional 110 pins are covered in the 3870 Family Technical Manual. Since two pins are dedicated to serve the Standby Power mode (VSB )' port 0 has only the upper 6 bits, PO-2 - PO-7, An output ready strobe is associated with Port 4. This flag may be used to signal a peripheral device that the MK3875 has just completed an output of new data to Port 4. The strobe provides a single low pulse shortly after the output operation is completely finished, so either edge may be used to signal the peripheral. STROBE may be used as an input strobe simply by doing a dummy output of H 'OC), to Port 4 after completing the input operation. STANDBY POWER MODE On the MK3875, the contents of the on-chip executable RAM can be saved when the Standby Power mode is operative. The Standby Power mode allows the MK3875's main power supply to drop all way down to 0 volts while the on-chip executable RAM is powered from the auxiliary low power supply input, V SB ' Thus, key variables may be maintained within the MK3875 executable RAM during the time th'at the rest of the microcomputer is powered down. On the MK3875, two of the pins which are used as bidirectional port pins on the MK3870 are used for the Standby Power feature. Port 0, Bit 0 (PO-O), remains readable and writeable although it is not connected to a package pin. The logic level being applied to the auxiliary vlII-n • 3875 PROGRAMMABLE REGISTERS, PORTS AND MEMORY MAP Figure 2 CPU REGISH.RS I 0 PORTS BINARY TIMER SCRATCHPAD MfMORY ACCUMULATOR PORT 7 A 7 _ 8 BITS_ 0 7_B8ITS- 0 SCRATCHPAD DEC HEX ~o OCl o I INTERRUPT CONTROL PORT STATUS REGISTER iWI PORT 6 l~ HZ I lsi 7 _ 8 81T5_ 0 C I N T R C N T R L 4_ PARALLEL I O,PORTS PORT 5 o 5 V I G N Z C E A E R R R o R Y F L .0 INOIRECT SCRATCHPAD ADDRESS REGISTER HL KU KL au 14 16 aL 15 17 A 12 11 8 12 13 13 14 0 15 61 3D 75 62 3E 76 63 3F 77 7 __ 8 BITS-- 0 ~~ PORT 4 5 PORT 1 PORT 0 10 § 0 W 5 BITS 11 J HU I 7_6BITS .....2 32 0 _6BITS_ MAIN MEMORY PROGRAM COUNTER PO bu I POL l 0 87 _128ITS_ 11 § STACK REGISTER 11 ROM DATA COUNTER \ AUX DATA COUNTER 11 87 0 _121lIT5_ HEX 2046 2047 7FE 7FF 8 87 _12BITS_ DC !DCU I 11 87 _1,IlITS_ DEC 0 1 Ea :=;~!i 7· V111·78 -8BIT8-0 _MK3875/22 ROM TOP 4030 4031 FBE FBF 4032 4033 FCO FC1 4094 4095 FFE FFF _MK3875/42 ROM TOP MK3875 MAIN MEMORY SIZES AND TYPES BY SLASH NUMBER Figure 3 ~ I I HEX DEC /'" ~, I I FFF 4095 FCO 4032 FBF 4031 800 7FF 2048 2047 > 64 BYTES EXECUTABLE RAM I ! I I 2K ROM 4K ROM 3875/22 3875/42 00000000 \~----------~ r -________ J1 V All devices contain 64 bytes of scratchpad RAM Data derived from addressing any locations other than within the specified ROM or RAM space is not tested nor is it guaranteed. Users should refrain from entering this area of the memory map. Device Scratchpad RAM Size (Decimal) MK3875/22 MK3875/42 64 bytes 64 bytes Address Register Size (PO,P,DC,DC1 ) ROM Size (Decimal) Executable RAM Size 12 bits 12 bits 2048 bytes 4032 bytes 64 bytes 64 bytes power supply input (VSB) can be read at Port 0, Bit 1 (PO-1 ). Writing to PO-1 has no effect. A capacitor (.01 microfarads) must be connected between pin 3 (VBB) and ground. VBB is bonded directly to the substrate of the MK3875. The purpose of the capacitor is to decouple noise on the substrate of the circuit when VCC is switched on and off. It is recommended that Nickel Cadmium batteries (typical voltage of 3 series cells = 3.6V) be used for standby power, since the MK3875 can automatically trickle charge the three NiCads.lf morethan three cells in series are used, the charging circuit must be provided outside the MK3875. Whenever RESET is brought low, the executable RAM is placed in a protected state. Also the RAM is switched from V CC power to the V SB power. When powering down, it may be desirable to interrupt the MK3875 when an impending power down condition is detected, so that the necessary data can be saved before VCC falls below the minimum level. After the save is completed, RESET can fall, which prevents any further access of the RAM. The timing for this power down sequence is illustrated in Figure 5A. A second power down sequence is illustrated in Figure 5B, and may be used if a special save data routine is not needed. The EXT INT line need not be used. Note that for both cases shown in Figures 5A and 5B, RESET must be low before Vce drops below the minimum specified operating voltage for the MK3875. This is to ensure that the contents of the executable RAM are not altered during the power down sequence. There may be a set of variables stored in the RAM memory which is continually updated during the tme when the MK3875 is in its normal operating mode. If a particular variable occupies more than one byte of RAM, there can be a problem if a reset occurs in response to an impending power down condition during the time that the multi-byte variable was being modified. If such a reset occurs, then only part of the variable may contain the updated value, while the rest contains the old value. An example of this ,case would be when a double precision (2 byte) binary number is being saved in the executable RAM. Suppose that a new value of the number has been calculated in the program, and that this new value is to replace the old value contained in the executable RAM; note that a reset could occu r just after the program wrote one byte ofthe new val ue V111-79 • 1/0 PIN CONCEPTUAL DIAGRAM WITH OUTPUT BUFFER OPTIONS Figure 4 PORT 1/0 PIN z o i= oCt a: ::J (!l ~ a: ir: oQ. u C oCt z o a: o 6w w a: ~ a: oQ. C oCt o....I a: ~ I/) ::J III oCt ~ oCt C OUTPUT BUFFER OPTIONS (MASK PROGRAMMABLE) Vcc 6K!lTYP STANDARD OUTPUT OPEN DRAIN OUTPUT DIRECT DRIVE OUTPUT Ports 0 and 1 are Standard Output type only. Ports 4 and 5 may both be any of the three output options (mask programmable bit by bit) The STROBE output is always configured similar to a Direct Drive Output except that it is capable of driving 3 TTL loads. RESET and EXT INT may have standard 6K!l (typical) pull-up or may have no pull-up (mask programmable). These two inputs have Schmitt trigger inputs with a minimum of 0.2 volts of hysteresis. RESET and EXT INT do not have internal pull up on the MK38P75. VIII-SO into the RAM. When power is restored following the Standby Power mode, the double precision variable would contain an erroneous value. "set" is a good byte of data. While this method significantly encumbers the data storage process, it eliminates the neeCl for a power fail interrupt which both reduces external circuitry and leaves the external interrupt pin completely free for other use. This problem can be avoided ifthe external interrupt is used to signal the MK3875 of an impending power down condition. The user's system should be designed sothatthe MK3875 can properly save all variables between the time that the external interrupt occurs and RESET falls. If multibyte variables must be saved during the Standby Power mode and it is not desirable to use the external interrupt in the manner described above, then each byte of a multi-byte variable may be kept with an associated flag. The method of updating a two byte variable would be as follows: Often it is necessary to distinguish between an initial power-on condition wherein there is no valid data stored in the RAM (or where V SB has dropped below the minimum required stand-by level) and a re-application of power wherein valid RAM data has been maintained during the power outage. One method of distinguishing between these two conditions is to reserve several memory locations for key words and checksums. When Vee is applied and processor operation begins, these locations can be checked for proper contents. However, this method may not be perfectly accurate as those locations holding key codes may be maintained even though V SB drops below its minimum required level while other RAM locations may lose data, or they could power up with the exact data required to match the key codes. Also a checksum may be matched on occasion even though RAM data has been corrupted. The accuracy of this method is improved by increasing the number of memory locations used and the variety of key codes and or checksums used. - Clear Flag Word 1 - Update Byte 1 - Set Flag Word 1 - Clear Flag Word 2 - Update Byte 2 - Set Flag Word 2 Now if RESET goes low during the update of a byte of a variable, the flag word associated with that byte of data will be reset. Any byte of the variable where the flag word is SAVE ROUTINE REQUIRED, VSB • > 3.2 VOLTS Figure 5a VCC SUSTAINED~PACITOR OR BATTERY UNTIL RESET BROUGHT LOW ~I VCC VlAIN POWER SUPPl Y FAILURE DETECTED I ~ l EXT INT I ~~;-/, L I iiESeT I I -1 I I I I ~ DATA SAVE MUST BE DONE HERE ~ I ff I ~ j.-- ACCESS TO RAM INHIBITED EXECUTION -BEGINS AGAIN I NO SAVE ROUTINE REQUIRED, VSB > 3.2 VOLTS Figure 5b VCC - - - - _ - - - . . . . . . MAIN POWER FAILURE DETECTED 1 - ) / ~ ...... _ _ _ _-j)( ('-_ _ _ _ _/ \~_~}~/ ________~r-- VIII-81 A more reliable method is the external VSB flip-flop. The flip-flop is designed to power up in a known first state and hold that first state until forced into a second state. As long as V SB is above the minimum operating level, the flip-flop can hold the second state, but, if V SB drops below the minimum level, the flip-flop will flip back to the first state. Thus when power is initially applied or if V SB drops below the minimum level during a Vee outage, the flip-flop will be in the first state. The flip-flop output can be read through a port pin by the processor when processor operation begins to determine whether the RAM data is valid (second state) or invalid (first state). If the flip-flop is found to be in the first state it can be forced to the second state by the processor. If it holds the second state, VSB is above the minimum level (batteries are charged). CONCEPTUAL DIAGRAM Figure 6 FROM 38715Rlm The MK38P75 is offered with two types of output buffer options on Ports 4 and 5. These are the open drain output buffer and the standard output buffer which are pictured in Figure 4. The open drain version of the MK38P75 is provided so that user-selected open drain port pins on the MK3875 can be emulated prior to ordering those mask ROM devices. Figure 9 lists which version(s) of the MK38P75 has open drain output buffers and which has standard output buffers in parentheses following the specified MK38P75 part ordering number (MK9XXXX). MK38P76 MAIN MEMORY As can be seen from the block diagram in Figure 7, the MK38P75 contains executable RAM in the main memory map. The MK38P75 contains noon-chip ROM. Instead, the memory address lines are brought out to the 28-pin socket located directly on top of the 40-pin package, so the external ERPOM memory is addressed as main memory. A conceptual diagram is shown in Figure 6. FROM 38715 PORT 4 OR 15 PIN MK38P75 1/0 PORTS TO 38715 PORT PIN There is one memory version of the MK38P75 and it is designated as the MK38P75/02. The MK38P75/02 contains 64 bytes of on-chip executable RAM. The MK38P75/02 can emulate the following devices. MK3875/22 MK3875/42 The MK38P75/02 cannot exactly emulate the MK3875/40 because of the 64 bytes of executable RAM in the upper ROM space of the MK3875/40. MK38P75 GENERAL DESCRIPTION The MK38P75 is the EPROM version of the MK3875. It retains an identical pinout with the MK3875, which is documented in the section of this data sheet entitled "FUNCTIONAL PIN DESCRIPTION". The MK38P75 is housed in the "R" package which incorporates a 28-pin socket located directly on top of the package. A number of standard EPROMs may be plugged into this socket. The MK38P75 can act as an emulator for the purpose of verification of user code prior to the ordering of mask ROM MK3875 devices. Thus, the MK38P75 eliminates the need for emulator board products. In addition, several MK38P75s can be used in prototype systems in order to test design concepts in field service before commiting to high-volume production with mask ROM MK3875s. The compact size of the MK38P75/EPROM combination allows the packaging of such prototype systems to be the same as that used in production. Finally, in low-volume applications, the MK38P75 can be used as the actual production device. Most of the material which has been presented for the MK3875 in this document applies to the MK38P75. This includes the description of the pin configuration, architecture, and programming mode. Additional information is presented in the following sections. Addressing of main memory on the. MK38P75 is accomplished in the samewayas it isforthe MK3875. See Figure 8 for main memory addresses and for address register size in the MK38P75. MK38P75 EPROM SOCKET A 28-pin ERPoM socket is located on top of the MK38P75 "R" package. The socket and compatible ERPOM memories are shown in Figure 9. When 24-pin memories are used in the 28-pin socket, they should be inserted so that pin 1 of the memory device is plugged into pin 3 of the socket (the 24-pin memory should be lower justified in the 28-pin socket). The 28-pin socket has been provided to allow use of both 24-pin and 28-pin memory devices. Minor pin-out differences in the memory devices must be accommodated by providing different versions of the MK38P75. Initially, the MK38P75 that is compatible with the MK2716 is available. The MK38P75 designed to accommodate the 28-pin memory devices will be available at a later date. VIII-82 MK38P75 BLOCK DIAGRAM EXTINT Figure 7 MEMORY ADDRESS BUS 64)(8 EXECUTABLE RAM MAIN CONTROL lOGIC ROM RESULT BUS $ 1/0 (6) TEST 1/0 (8) 1/0 (8)STROBE 1/0 (8) MK38P75 MAIN MEMORY MAP Figure 8 HEX F RAM FCO FBF DEC 64 BYTES 4096 4032 4031 INTERNAL EXECUTABLE RAM 1 I I I I I 80.0________________2_0_4_8 1- - - 2047 7FF I I I 1 I EXTERNAL 1 EPROM I ~ ______ ~I __________________ ~OOO~ ~ MK38P75/02 Device MK38P75/02 97403 Scratchpad RAM Size (Decimal) Address Register Size po, P, DC, DC1) ROM Size (Decimal) Executable RAM Size 64 bytes 12 bits o bytes 64 bytes VIII-S3 • MK38P75 uR" PACKAGE SOCKET PINOUT MEMORY ACCESS TIMING Figure 9 MK97413 (Open Drain Outputs) Compatible Memories 2758 MK2716 2516 2532 MK97403 (Standard Outputs) Compatible Memories 2758 MK2716 2516 2532 A timing diagram depicting the memory access timing ofthe MK38P75 is shown in the next table. The clock signal is derived internally inthe MK38P75 bydividingthetime base frequency by two and is used to establish all timing frequencies. The WRITE signal is another internal signal to the MK38P75 which corresponds to a machine cycle, during which time a memory access may be performed. Each machine cycle is either 4 clock periods or 6 clock periods long. These machine cycles are termed short cycles and long cycles, respectively. The worst case memory cycle is the short cycle, during which time an op code fetch is performed. This is the cycle which is pictured in the timing diagram. After a delay from the falling edge of the WRITE clock, the address lines become stable. Data must be valid at the data out lines of the PROM for a setup time prior to the next falling edge of the WRITE pulse. The total access time available for the MK38P75 version is shown as taas or the time when address is stable until data must be valid on the data bus lines. The equation for calculating available memory access time along with some calculated access times based on the listed time base frequencies is shown in the following table. MEMORY ACCESS SHORT CYCLE OP CODE FETCH MK38P75 Figure 10 WRITE A" - ~ \ I I PREVIOUS ADDRESS Ao I :. Signal is internal to the MK38P75 6 taas = time base freq. -850 ns (FROM ADDRESS STABLE) ACCESS TIME 3.5 MHz 3MHz 2.5 MHz 2MHz 650 ns 825 ns 1.15 J1S 1.55 J1S 2.15 J1S ! NEW ADDRESS I I I I I I I I I 4MHz \ VIII-84 ~ I I I tea. ~I I I I ! DATA VAUD I I I I 3875 TIME BASE OPTIONS CRYSTAL SELECTION The 3875 contains an on-chip oscillator circuit which provides an internal clock. The frequency of the oscillator circuit is set from the external time base network. The time base for the 3875 may originate from one of four sources: The use of a crystal as the time base is highly recommended as the frequency stability and reproducability from system to system is unsurpassed. The 3875 has an internal divide by two to allow the use of inexpensive and widely available TV Color Burst Crystals (3.58 MHz). Figure 12 lists the required crystal parameters for use with the 3875. The Crystal Mode time base configuration is shown in Figure 11. 1) 2) 3) 4) Crystal LC Network RC Network External Clock The type of network which is to be used with the mask ROM MK3875 must be specified at the time when mask ROM devices are ordered. However, the MK38P75 may operate with any of the four configurations so that it may emulate any configuration used with a mask ROM device. The specifications for the four configurations are given in the following text. There is an internal 26 pF capacitor between XTL 1 and GND and an internal 26 pF capacitor between XTL 2 and GND. Thus, external capacitors are not necessarily required. In all external clock modes the external time base frequently is divided by two to form the internal PHI clock. Through careful buffering of the XTL 1 pin it maybe possible to amplify this waveform and distribute it to other devices. However, Mostek recommends that a separate active device (such as a 7400 series TIL gate) be used to oscillate the crystal and that the waveform from that oscillator be buffered and supplied to all devices, including the 3875, in the event that a single crystal is to provide the time base for more than just a single 3875. While a ceramic resonator may work with the 3875 crystal oscillator, itwas not designed specifically to support the use of this component. Th us, Mostek does not support the use of a ceramic resonator either through proper testing, parametric specification, or applications support. CRYSTAL MODE CONNECTION Figure 11 XTl1 XTL2 AT-CUT VIII-8S • CRYSTAL PARAMETERS Figure 12 a) b) c) d) Parallel resonance, fundamental mode AT-Cut Shunt capacitance (Co) = 7 pf max. Series resistance (Rs) = See table Holder = See table below. Frequency f = 2-2.7 MHz f = 2.8-4 MHz Series Resistance Holder Rs = 300 ohms max HC-6 HC-33 Rs = 150 ohms max HC-6 HC-18* HC-25* HC-33 *This holder may not be available at frequencies near the lower end of this range. LC NETWORK is 0.1 millihenries. The inductor must have a Q factor which is no less than 40. The value of C is derived from C external. the internal capacitance of the 3875, CXTL' and the stray capacitances, CS1 and CS2 . CXTL is the at XTL 1 and capacitance looking into the internal two port network XTL2. CXTL is listed under the "Capacitance" section of the Electrical Specifications. CS1 and CS2 are stray capacitances from XTL 1 to ground and from XTL2 to ground, respectively. C external should also include the stray shunt capacitance across the inductor. This is typically in the 3 to 5 pf range and significant error can result if it is not included in the frequency calculation. The LC time base configuration can be used to provide a less expensive time base for the 3875 than can be provided with a crystal. However, the LC configuration is much less accurate than is the crystal configuration. The LC time base configuration is shown in Figure 13. Also shown in the figure are the specified parameters for the LC components, along with the formula for calculating the resulting time base frequency. The minimum value of the inductor which is required for proper operation of the LC time base network LC MODE CONNECTIOI\I Figure 13 XTL1 --- XTL2 ---- L I I rrrn L _________ ~ I I ~---------- CEXTERNAL (OPTIONAL) f= V111-86 2 rr v-LC network tied to the XTL2 pin, when XTL 1 is grounded. A schematic picturing the RC clock configuration is shown in Figure 14. The RC time base configuration is intended to provide an inexpensive time base source for applications in which timing is not critical. Some users have elected to tune each unit using a variable resistor or external capacitor thus reducing the variation in frequency. However, for increased time base accuracy Moste,k recommends the use of the Crystal or LC time base configuration. Figure 15 illustrates a curve which gives the resulting operating frequency for a particular RC value. The x-axis represents the product of the value of the resistor times the value of the capacitor. Note that three curves are actually shown. The curve in the middle represents the nominal frequency obtained for a given value of RC. A maximum curve and a minimum curve for different types of 3875 devices are also shown in the diagram. Variation in time base frequency with the LC network can arise from one of four sources: 1) Variation in the value of the inductor. 2) Variation in the value of the external capacitor. 3) Variation in the value of the internal capacitance of the 3875 at XTL 1 and XTL2, and 4) Variation in the amount of stray capacitance which exists in the circuit. Therefore, the actual frequency which is generated by the LC circuit is within a range of possible frequencies, where the range of frequencies is determined by the worst case variation in circuit parameters. The designer must select component values such that the range of possible frequencies with the LC mode does not go outside of the specified operating frequency range for the 3875. RC CLOCK CONFIGURATION The time base for the 3875 may be provided from RC MODE CONNECTION an RC RCMODE Figure 14 XTL2 XTL1 R I --L'T' I MINIMUM R =4K n C = 26.5 pF ± 2.6pF + Cexternal -L FREQUENCY VS. RC Figure 15 4MHz1-------~----~~~~--------_r----------+_----~ 3MHz 2MHz1-------~--------~----------_r----~~~~~----~ RC PRODUCT 1 x 10. 7 2 x 10.7 V111·87 2.5 x 10.7 3 x 10. 7 CEXTERNAL (OPTIONAL) • The designer must select the RC product such that a frequency of less than 2 MHz is not possible taking into account the maximum possible RC product and using the minimum curve shown in Figure 15. Also, the RC product must not allow a frequency of more than 4 MHz taking into account the minimum possible Rand C and using the Maximum curve shown. Temperature induced variations in the external components should be considered in calculating the RC product. Positive Freq. Variation = RC typical - RC minimum RC typical Negative Freq. Variation due to RC Components = RC maximum - RC typical RC typical Total frequency variation due to all factors: 387X-00, -05 = +18 percent plus positive Frequency variation from unit to unit due to switching speed and level at constant temperature and Vee = + or - 5 percent. frequency variation due to RC components ... 387X-10, -15 = +21 percent plus positive frequency variation due to RC components =-18 percent minus negative =-21 Frequency variation due to Vee with all other parameters constant with respect to +5V = +7 percent to -4 percent on all devices. Frequency variation due to temperature with respect to 25 C (all other parameters constant) is as follows: PART # frequency variation due to RC components Total frequency variation due to Vee and temperature of a unit tuned to frequency at +5V Vee' 25 C VARIATION 387X-00, -05 = + 13 percent 387X-OO, -05 387X-10, -15 +6 percent to - 9 percent +9 percent to -12 percent Minimum RC = (R min) (C external min + CXTL min) 387X-10, -15 = + 16 percent EXTERNAL CLOCK CONFIGURATION Variations in frequency due to variations in RC components may be calculated as follows: Maximum RC = (R max) (C external max + CXTL max) percent minus negative frequency variation due to RC components The connection for the external clock time base configuration is shown in Figure 16. Refer to the DC Characteristics section for proper input levels and current requirements. Refer to the Capacitance section of the appropriate 3875 Family device data sheet for input capacitance. Typical RC = (R typ) (C external typ + {C XTL max + CXTL min)) 2 EXTERNAL MODE CONNECTION Figure 16 XTL1 XTL2 I NO CONNECTION EXTERNAL CLOCK INPUT VIII-SS MK3875, MK38P75 ELECTRICAL SPECIFICATIONS OPERATING VOLTAGES AND TEMPERATURES Operating Dash Operating Number Temperature Voltage Suffix TA VCC - 00 +5V ± 10% O°C - 70°C - 05 +5V ± 5% O°C - 70°C - 10 +5V ± 10% -40°C - +85°C - 15 +5V ± 5% -40°C - +85°C See order information for explanation of part numbers. ABSOLUTE MAXIMUM RATINGS* -00, -05 -10,-15 Temperature Under Bias ................................. . Storage Temperature .................................... . Voltage on any Pin With Respect to Ground (Except open drain pins and TEST) ....................... . Voltage on TEST with Respect to Ground ................... . Voltage on Open Drain Pins with Respect to Ground ......... . Power Dissipation ....................................... . Power Dissipation by anyone I/O pin ...................... . Power Dissipation by all 110 pins .......................... . -20°C +85°C -65°C + 150°C -50°C to 100°C -65°C to +150°C -1.0V to +7V -1.0V to +9V -1.0V to +13.5V 1.5W 60mW 600mW -1.0V to +7V -1.0V to +9V -1.0V to 13.5V 1.5W 60mW 600mW 'Stresses above those listed under" Absolute Maximum Ratings" maycause permanent damage to the device. This is a stress rating only and functional operation ofthe device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating and conditions for extended periods may affect device reliability. AC CHARACTERISTICS TA, V CC within specified operating range I/O Power Dissipation < 1OOmW (Note 4) SIGNAL SYM PARAMETER -00,-05 MIN MAX -10,-15 MIN MAX XTLl XTL2 to Time Base Period, all clock modes 250 500 250 500 ns tex(H) tex(L) External clock pulse width high External clock pulse width low 90 100 400 400 100 110 390 390 ns ns t Internal clock WRITE tw Internal WRITE Clock period I/O tdl/O Output delay from internal WRITE clock 0 tsliO Input setup time to internal WRITE clock 1000 STROBE RESET tllO- s Output valid to STROBE delay 2to 4t 6t 1000 0 3t 3t 3t -1000 +~ -1200 12t +250 8t -300 STROBE low time 8t -250 tRH RESET hold time, low 6t +750 6t +1000 power power supply tEH EXT INT hold time in active and inactive state S~:IY time +5.0 6t +750 2t VIII·89 1200 4MHz-2MHz Short Cycle Long Cycle ns 50pF plus one TIL load ns 1200 tsL tRPOC RESET hold time, low for power clear EXTINT 2to 4t 6t UNIT NOTES 3t +300 125<1> +300 ns ns 110 load = 50fF + 1 TIL load STROBE load = 50pF + 3TIL loads ns rise time +5.5 ms 6t +1000 2t ns ns To trigger interrupt To trigger timer II AC CHARACTERISTICS FOR MK38P76 (Signals brought out at socket) TA' Vee within specified operating range. I/O Power Dissipation :5 100 mW. (Note 2) -00,-06 SYMBOL PARAMETER MIN taas * Access time from Address A,,-Ao stable until data must be valid at D7"DO 650 MAX -10,-16 MIN MAX UNIT CONDITION ns 650 = 2.0 MHz *See Table in Figure 10 CAPACITANCE TA = 25°C All Part Numbers SYM PARAMETER CIN Input capacitance; I/O RESET, EXT INT, TEST CXTL Input capacitance; XTL 1, XTL2 MAX MIN UNIT NOTES 10 pF 23.5 29.5 pF -00,-05 -10,-15 unmeasured pins grounded DC CHARACTERISTICS TA, V CC within specified operating range I/O Power Dissipation :5 100mW (Note 4) SYM PARAMETER ICC Average Power Supply Current PD Average Power Dissipation VIHEX External Clock input high level 2.4 5.8 VILEX External Clock input low level -.3 .6 IIHEX External Clock input high current IILEX External Clock input low current VIHI/O Input high level, I/O pins VIHR Input high level, RESET VIHEI VIL VILRPT MIN Input high level, EXT INT I/O ports, RESET, EXT INT input low level RESET input low level to protect RAM during loss at V CC MAX MIN MAX UNIT NOTES 94 125 mA Outputs Open (5) 440 575 mW Outputs Open (6) 2.4 5.8 V -.3 .6 V 100 130 J-LA VIHEX=VCC -100 -130 !J.A VILEX=VSS 2.0 5.8 2.0 5.8 V Standard Pull-Up (1 ,2) 2.0 13.2 2.0 13.2 V Open Drain (1,3) 2.0 5.8 2.2 5.8 V Standard Pull-Up(1, 2) 2.0 13.2 2.2 13.2 V No Pull-Up (1,3) 2.0 5.8 2.2 3.8 V Standard Pull-Up(1, 2) 2.0 13.2 2.2 13.2 V No Pull-Up (1,3) -.3 .8 -.3 .7 V -.3 .4 -.3 .4 V -1.9 mA -- -.- IlL Input low current, standard pull-up pins -1.6 VIII·90 VIN=0.4V (2) DC CHARACTERISTICS (Continued) TA' Vcc within specified operating range I/O Power Dissipation ~ 100 rnW (Note 4) SYM PARAMETER IL Input leakage current, open drain pins Reset and EXT INT inputs With no pull-up resistor 10H Output high current, standard Pull-Up pins 10HDD -00, -05 MIN MAX -10, -15 MIN MAX +10 -5 +18 -8 UNIT NOTES pA pA VIN=13.2V VIN=O.OV (3) -100 -89 pA VOH=2.4V -30 -25 pA VOH=3.9V Output high current -100 -80 pA VOH=2.4V Direct Drive pins -1.5 -1.3 rnA rnA VOH=1.5V VOH=0.7V -11 -8.5 10L Output low current, I/O ports 1.8 1.65 rnA VOL=O.4V 10HS STROBE Output High current -300 -270 pA VOL=2.4V 10LS STROBE output low current 5.0 4.5 rnA VOL=O.4V DC CHARACTERISTICS FOR STANDBY POWER PINS VCC' TA within operating range I/O Power Dissipation ~ 100 rnW (Note 4) -00, -05 SYMBOL PARAMETER VSB Standby V CC for RAM ISB Standby Current ICHARGE Trickle charge available on VSBwith VCC in operating range. -10,-15 MIN MAX MIN MAX 3.2 VCC MAX 3.2 VCC MAX V 6 7.5 rnA VSB = VSB MAX 3.7 5.0 rnA VSB =VSB MIN -19 rnA rnA VSB = 3.8V VSB - 3.2V -.8 -.7 -15 UNIT NOTES DC CHARACTERISTICS FOR MK38P75 (Signals brought out at socket) TA' V cc within specified operating range, I/O power dissipation ~ 100 rnW (Note 2) -00, -05 SYM PARAMETER ICCE Power Supply Current for EPROM V IL Input Low Level Data bus in -0.3 0.8 V IH Input High Level Data bus in 2.0 5.8 IOH Output High Current IOL Output Low Current IlL Input Leakage Current MIN MAX -10,-15 MIN -185 MAX UNIT CONDITION -185 rnA -0.3 0.8 V 2.0 5.8 V -100 -90 pA VoH =2.4 V -30 -25 pA V oH =3.9 V 1.8 1.65 rnA V oL=0.4 V pA Data Bus in Float 10 VIII-91 10 • 1. RESET and ET INT have internal Schmit triggers giving minimum .2V hysteresis. 2 i'i'E'SE'i" and EXT INT prgrammed with standard pull-up 3. RESET or EXT INT programmed without standard pull-up 4. Power dissipation for 1/0 pins is calculated by I (Vee - VIL) (1lILI) I I (Vee - VOH) (IiOHIl+ I (VOL) (IOL) 5. lee exclusive of Icharge' 6. PD exclusive of battery charging power. Battery charging power dissipated inside the MK3875 (Vee - Vss) (Icharge)' TIMER AC CHARACTERISTICS Defi n itions: Error tpsc = Indicated time value - actual time value = t x Prescale Value Interval Timer Mode Single interval error, free running (Note 3) ........................... . . . . . . . • . . . . . . . . . . . . . . . . . . . . • . .. ±6t Cumulative interval error, free running (Note 3) .......................................................... 0 Error between two Timer reads (Note 2) ........................................................ ±(tpsc + t to - (tpsc + t to -(tpsc + 7t to -8t4> Load Timer to stop Timer error (Note 1) ................................................. +t to -(tpsc + 2t to -(tpsc + 8t to -9t4> Pulse Width Measurement Mode Measurement accuracy (Note 4) ....................................................... +t to -(tpsc +2t Minimum pulse width of EXT INT pin ................................................................ 2t Event Counter Mode Minimum active time of EXT INT pin .............•............... , ................................... 2t 4> Minimum inactive time of EXT INT pin ............................................................... 2t 4> Notes: 1. All times which entail loading, starting, or stopping the Timer are referenced from the end of the last machine cycle of the OUT or OUTS instruction. 2. All times which entail reading the Timer are referenced from the end of the last machine cycle of the IN or INS instruction. 3. All times which entail the generation of an interrupt request are referenced from the start of the machine cycle in which the appropriate interrupt request latch is set. Additional time may elapse if the interrupt request occurs during a privileged or multicycle instruction. 4. Error may be cumulative if operation is repetitively performed. VIII-92 AC TIMING DIAGRAM Figure 17 External Clock Internal Clock Input capacitance; 110, RESET, EXT INT, 1/0 Port Output • STROBE RESET EXTINT 3(,--- ICP B I T 0 J= Ir----tEH -----.I: ICPBIT2=1 _ Note: All AC measurements are referenced to V 1L max., VIII-93 V 1H min., VOL (.8v), or V OH (2.0v). INPUT/OUTPUT AC TIMING Figure 18 INTERNAL WRITE CLOCK CYCLE TIMING ~-----·+-----------~~-------------~4-----~*----'DEPENDSONINSTRUCTION 3iJS* * CYCLE TIMING SHOWN FOR 4MHz EXTERNAL CLOCK OP CODE FETCHED PORT ADDR. PLACED ON DATA BUS 3iJS* PORT DATA DRIVEN ON TO DATA BUS PORT PINS A. INPUT ON PORT 4 OR 5 CYCLE TIMING ----+--- DEPENDS ON INSTRUCTION ,-----t.... INTERNAL WRITE CLOCK 3iJS* OUTOR OUTS OP CODE FETCHED PORT ADDR. ON DATA BUS ACCUMULATOR CONTENTS ON DATA BUS NEXT OPCODE FETCHED PORT PINS STAYS LOW STROBF (ACTIVE FOR PORT 4 ONLY) FOR TWO WRITE CYCLES tl/O-S B. OUTPUT ON PORT 4 OR 5 INTERNAL WRITE CLOCK OUTS 0,1 FETCHED ACC DATA ON BUS PORT PINS C. INPUT ON PORT 0 OR 1 D. OUTPUT ON PORT 0, 1 VIII-94 STROBE SOURCE CAPABILITY (TYPICAL AT VCC =6V, TA =26°C) -15 Figure 19 s o U R C E -10 c U R R E N T 1"""0"",- ..... ~ .... t-.,. -5 r--. M A '"' '" '" I""ii OUTPUT VOLTAGE STROBE SINK CAPABILITY (TYPICALATVCC = 6V, TA = 26°C) Figure 20 S I N +100 K C U R ~ L,...io-' +50 1-.... .... i..;' N T ~ 1,/ M A j • j OUTPUT VOLTAGE STANDARD 1/0 PORT SOURCE CAPABILITY (TYPICAL AT VCC =5V, TA =25°C) Figure 21 -1.5 s o U R C E c -1.0 " ~ ""'' ' '" 1"" U R R E l'- N .... ""- '" " ""'' ' '" T M A -.5 1"" ,...." ""'" OUTPUT VOLTAGE DIRECT DRIVE 110 PORT SOURCE CAPABILITY (TYPICALATVCC = 5V, TA = 25°C) Figure 22 s o U R -10 C E c ,.....t-.... U R R E N -j--. .... -5 f"'ii", ~ T '"I" M A OUTPUT VOLTAGE V111-95 10.... I/O PORT SINK CAPABILITY (TYPICAL AT VCC = 5V, TA = 25°C) Figure 23 +60 S I N +50 K C U +40 R R E +30 N T +20 M A .... ~ +10 -~~ ~ -~ ~~ " OUTPUT VOL TAGE MAXIMUM OPERATING TEMPERATURE VS. I/O POWER DISSIPATION Figure 24 - 100 TA 'C ..... ~ .... ~~4sr,c 50 100 200 300 - ..... ~ 400 500 CERA,M"'ic! ...... 600 POI/OMW VIII-96 .... r- 1000 ORDERING INFORMATION supply tolerance. For each customer specific code, additional information defining I/O options and oscillator options will be combined with the information described in the generic part number to define a customer/code specific device order number. There are two types of part numbers for the 3870 family of devices. The generic part number describes the basic device type, the amount of ROM and executable RAM, the desired package type, temperature range and power GENERIC PART NUMBER An example of the generic part number is shown below. MK3875/ 2 2 P - I 0 1~ 0= 5V ± 10% 5 = 5V ±5% Power Supply Tolerance .Operating Temperature Range L--_~~ Package type P = Ceramic N = Plastic Executable RAM Designator 2 = 64 Bytes ROM Designator 2 = 2K Bytes 4 = 4K Bytes Basic Device Type DEVICE ORDER NUMBER An example of the device order number is shown below. MK 19000 N - 0 5 11 : Power Supply Tolerance 0= +5V ± 10% 5 = +5V ± 5% Operating Temperature Range 0= O°C - +70°C 1 = -40°C - +85°C ~----t.. Package Types P = Ceramic N = Plastic Customer/Code Specific Number The customer/code specific number defines the ROM bit pattern, I/O configuration, oscillator type, and generic part type to be used to satisfy the requirement of a particular customer purchase order. For further information on the ordering of mask ROM devices, the customer should refer to the 3870 Family Technical Manual. VIII-97 • V111·98 1984/1985 MICROELECTRONIC DATA BOOK I! UNITED TECHNOLOGIES MOSTEK MICROCOMPUTER COMPONENTS CMOS MICROCOMPUTER CLOCK/RAM MK3805N FEATURES o PIN OUT Figure 1 Real-time clock counts seconds, minutes, hours, date of the month, day of the week, month, and year. Every 4th year, February has 29 days. o Serial I/O for minimum pin count (8 pins) o 24 x 8 RAM for scratchpad data storage o Simple Microcomputer interface 1 2 3 4 5 capability for read or write of clock or RAM data. Low-power CMOS X2 3 GND 4 PIN NAME 3805N o Single byte or mUltiple byte (Burst Mode) data transfer o 2 7 SCLK MK3805N 6 1/0 5 CE PIN DESCRIPTION frequency TTL Compatible (Vee CKO Table 1 o High speed shift clock independent of crystal oscillator o '8avcc X1/CI = 5V) 6 7 8 GENERAL DESCRIPTION CKO X1/C1 X2 GND CE I/O SCLK Vee DESCRIPTION Buffered System Clock Output Crystal or External Clock Input Crystal Input Power Supply Pin Chip Enable for Serial I/O Transfer Data Input/Output Pin Shift Clock for Serial I/O Transfer Power Supply Pin output frequencies for any given crystal frequency. This feature can eliminate having to use a separate crystal or external oscillator for the microprocessor, thereby reducing system cost. Many microprocessor applications require a real-time clock and/or memory that can be battery powered with very low power drain. The MK3805N is specifically designed for these applications. The device contains a real-time clock/calendar, 24 bytes of static RAM, an on-chip osci Ilator, and it com m un icates with the microprocessor via a simple serial interface. The MK3805N is fabricated using CMOS technology, thus ensuring very low power consumption. Interfacing the CLOCK/RAM with a microprocessor is greatly simplified using synchronous serial communication. Only 3 lines are required to communicate with the CLOCK/RAM: (1 ) CE (chip enable), (2) I/O (data line) and (3) SCLK (shift register clock). Data can be transferred to and from the CLOCK/RAM one byte at a time or in a burst of up to 24 bytes. The real-time clock/calendar provides seconds, minutes, hours, day, date, month, and year information to the microprocessor. The end of the month date is automatically adjusted for months with less than 31 days, including correction for leap year every 4 years. The clock operates in either the 24 hour or 12 hour format with an AM/PM indicator. TECHNICAL DESCRIPTION Figure 2 is a block diagram of the CLOCK/RAM chip. Its main elements are the oscillator and divider circuit, divider control logic, the real-time clock/calendar, static RAM, the serial shift register, and the command and control logic. The on-chip oscillator provides a real-time clock source for the clock/calendar. It incorporates a programmable divider so that a wide variety of crystal frequencies can be accommodated. The oscillator also has an output available that can be connected to the microprocessor clock input. A separately programmable divider provides several different The shift register is used to communicate with the outside world. Data on the I/O line is either input or output on each shift register clock pulse when the chip is enabled. If the chip is in the input mode, the data on the I/O line is input to the shift register on the rising edge of SCLK.lf in the output IX-1 • BLOCK DIAGRAM EXTERNAL CLOCK INPUT I Figure 2 X,/c,rDq BUFFER CKO OSCILLATOR AND DIVIDERS REAL TIME CLOCK , 1/0 I DIVIDER CONTROL LOGIC SHIFT IIA'L-- _ _ _....J REGISTER DATA BUS ~ SCLK t ~---r-r-----------~ COMMAND AND CONTROL LOGIC - ADDRESS & CONTROL BUS ,J 24 x 8 RAM CE mode, data is shifted out onto the I/O line on the falling edge of SCLK. The command and control logic receives the first byte input by the shift register after CE goes active. This byte must be the command byte and will direct further operations within the CLOCK/RAM. The command specifies whether subsequent transfers will be data input or data output, and which register or RAM location will be involved. A control register provides programmable control of the divider for the internal clock signal, the external clock signal, the crystal type and mode, and the write protect function. The real-time clock/calendar is accessed via seven dynamic registers. These registers are seconds, minutes, hours, day, date, month, and year. Certain bits within these registers also control a run/stop function, 12/24 hour format, and indicate AM or PM (12 hour mode only). These registers can be accessed sequentially in Burst Mode, or randomly in a single byte transfer. The static RAM is organized as 24 bytes of 8-bits each. They can be accessed either sequentially in burst mode, or randomly in a single byte transfer. IX·2 POWER UP A time base on the crystal input pins is necessary for correct power up. This time base can be provided by a crystal or it can be derived from another generated clock source. It should be noted that a delay exists between power up and the correct power up state of the clock and control registers. DATA TRANSFER Data Transfer is accomplished under control of the CE and SCLK inputs by an external microcomputer. Each transfer consists of a single byte ADDRESS/COMMAND input followed by a single byte or mUltiple byte (if Burst Mode is specified) data input or output, as specified by the ADDRESS/COMMAND byte. The serial data transfer occurs with LSB first, MSB last format. ADDRESS/COMMAND BYTE The ADDRESS/COMMAND Byte is shown below: 7 6 1%1 5 A4 4 3 2 A3 A2 A1 1 0 AO~ As defined, the MSB (bit 7) must be a logical 1; bit 6 specifies a Clock/Calendar/Control register if logical 0 or a RAM register if logical 1; bits 1-5 specify the designated register(s) to be input or output; and the LSB (bit 0) specifies a WRITE operation (input) if logical 0 or READ operation (output) if logical 1 . ADDRESS/COMMAND bits and DATA bits are input on the rising edge of SCLK, and DATA bits are output on thefalling edge of SCLK. A data transfer terminates if CE goes high, and the transfer must be reinitiated by the proper ADDRESS/ COMMAND when CE again goes low. The data I/O pin is high impedance when CE is high. BURST MODE DATA INPUT Burst Mode may be specified for either the Clock/ Calendar/Control registers or for the RAM registers by addressing location 31 Decimal (ADDRESS/COMMAND bits 1-5 = logical 1). As before, bit 6 specifies Clock or RAM and bit 0 specifies read or write. Following the 8 SCLK cycles that input the WRITE Mode ADDRESS/COMMAND byte (bitO =logical 0), a DATA byte is input on the rising edge of the next 8 SCLK cycles (per byte, if Burst Mode is specified). Additional SCLK cycles are ignored should they inadvertently occur. There is no data storage capability at location 31 in either the Clock/Calendar/Control registers or the RAM registers. DATA OUTPUT Following the 8 SCLK cycles that input the READ Mode ADDRESS/COMMAND byte (bit 0 =logical 1), a DATA byte is output on the falling edge of the next 8 SCLK cycles (per byte, if Burst Mode is specified). Note that the first data bit to be transmitted from the CLOCK/RAM occurs on the falling edge of the last bit of the command byte. Additional SCLK cycles retransmit the data byte(s) should they inadvertently occur, so long as CE remains low. This operation permits continuous Burst Read Mode capability. SCLK and CE CONTROL All data transfers are initiated by CE going low. After CE goes low, the next 8 SCLK cycles input an ADDRESS/ COMMAND byte of the proper format. An SCLK cycle is the sequence of a positive edge followed by a negative edge. For data inputs, the data must be valid during the SCLK cycle. If bit 7 is not a logical 1, indicating a valid CLOCK/RAM ADDRESS/COMMAND, the ADDRESS/COMMAND byte is ignored as are all SCLK cycles until CE goes high and returns low to initiate a new ADDRESS/COMMAND transfer. See Figure 3. DATA TRANSFER SUMMARY A data transfer summary is shown in Figure 3. DATA TRANSFER SUMMARY II Figure 3 I. SINGLE BYTE TRANSFER ~I~ _______________~r...l.1_A_4--lI_R_:C---LI_1--L_-L-_L---L=-:::-:-L:-::~=~_-'----J)-- 1 A2 I/O --<,--R_:W---LI_A_o-L-A_-.JIL..--L1_:_3 ADDRESS/COMMAND DATA INPUT/OUTPUT ,U. BURST MODE TRANSFER CEII--________________~ ~f~------------~ 1/0-\ R/wl 1 I 1 I 1 I 1 I 1 I R:C I ADDRESS/COMMAND 1 I I DATA I/O BYTE 1 ;; I )>---- ~...l.----:D~A~TA"""I/*-O'-;::BYT=:d-E""'N--' FUNCTION NOTES CLOCK 1) Data input sampled while SCLK is high 2) Data output changes on falling edge of clock 3) Rising edge of CE terminates operation and resets address/command RAM IX-3 BYTE N SCLK B 72 24 200 n REGISTER DEFINITION X4 X3 Xtal Mode CLOCK/CALENDAR 0 0 1 1 The Clock/Calendar is contained in 7 writeable/readable registers, as defined below. Address Function 0 1 0 1 Binary Microprocessor Baud Rate Color Burst Primary Frequencies 222,221, 220 Hz 8, 5, 4, 2.5, 2, 1.25, 1 MHz 7.3728, 3.6864, 1.8432 MH. 3.5795 MHz Range (BCD) CRYSTAL DIVIDER PRESCALER 0 1 2 Seconds+Clock Halt Flag Minutes Hours/AM-PM/12-24 Mode 3 Date 4 5 6 Month Day Year 00-59 00-59 00-23 or 01-12 01-28,29, 30,31 01-12 01-07 00-99 X2, X1, and XO specify a particular prescaler divider selection necessary to generate a 1 Hz frequency for the Clock/Calendar. Refer to Table 2 for complete definition. SYSTEM CLOCK OUTPUT Data contained in the Clock/Calendar registers is in binary coded decimal format (BCD). C1 and CO designate the system clock output frequency selected. The options are X, X/2, X/4, and ~2 kHz. When in the Binary Mode and C1, CO = '1', the output frequency is 2048 Hz. In any other mode the output frequency is ~2048 Hz. Refer to Table 3 for complete definition. CLOCK HALT FLAG WRITE PROTECT Bit 7 of the Seconds Register is defined as the Clock Halt Flag. Bit 7 = logical 1 inhibits the 1 Hz input to the Clock/Calendar. Bit 7 is set to logical 1 on power-up to prevent counting, and it may be set high or low by writing to the seconds register under normal operation of the device. Bit 7 of the Control Register is the WRITE PROTECT Flag. Bit 7 is set to logical 1 on power-up, and it may be set high or low by writing to the Control Register. When high, the WRITE PROTECT Flag prevents a write operation to any internal register, including the other bits of the Control Register. Further, logic is included such that the WRITE PROTECT bit may be reset to a logic 0 by a Write operation without altering the other bits of the Control Register. AM-PM/12-24 MODE Bit 7 of the Hours Register is defined as the 12 or 24 hour mode select bit. When high, the 12 hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20-23 hours). TEST MODE BITS Bit 7 of the Date Register and Bit 7 of the Day Register are Test Mode Bits utilized in testing the MK3805N. These bits should be logic 0 for normal operation. CONTROL REGISTER The Control Register specifies the crystal mode/frequency to be used, the system clock output frequency, and the WRITE PROTECT Mode for data protection. The Control Register is located at address 7 in the Clock/Calendar / Control address space. 7 6 I WP I C1 5 I CO I 4 3 2 X4 X3 X2 o X1 XO CLOCK/CALENDAR/CONTROL BURST MODE Address 31 Decimal of the Clock/Calendar/Control Address space specifies Burst Mode operation. In this mode, the 7 Clock/Calendar Registers and the Control Register may be consecutively read or written. Addresses above address 7 (Control Register) are non-existent; only addresses 0-7 are accessible. RAM The static RAM is contained in 24 writeable/readable registers, addressed consecutively in the RAM address space beginning at location O. RAM BURST MODE Address 31 Decimal of the RAM address space specifies Burst Mode operation. In this mode, the 24 RAM registers may be consecutively read or written. Addresses above the maximum RAM address location are non-existent and are not accessible. CRYSTAL DIVIDER MODE REGISTER SUMMARY X4 and X3 specify the Crystal frequency divider mode selected. IX-4 A Register, Data Format summary is shown in Figure 4. MICROCOMPUTER CLOCK/RAM ADDRESS/COMMAND REGISTER, DATA FORMAT SUMMARY Figure 4 I. ADDRESS/COMMAND FORMAT 7 11 5 6 fIn II. REGISTER ADDRESS A. CLOCK 7 6 A41 A3 1 A2 1 A, 1 Ao 5 I 0 MINI 1 0 0 4 3 0 0 0 0 1 HR 11 0 0 0 0 DATE 11 0 0 0 0 MONTH 11 0 o Io 11 DAY 11 [ 0 o 1 0 11 YEAR 11 0 0 0 CONTROL 11 0 CLOCK BURST 11 0 2 3 l%1 REGISTER DEFINITION 0 SEC 11 4 0 2 I 11 l~ 00-591 CH 1 l%l 00- 59 1 0 1 I l/wl 0 01-28/291 01-30 T, 01-31 0 I Ol/wl 01-121 0 0 I 1 1 1 0 11 11 11 11 I1 11 0 0 0 1 1 1 0 1 l/wl k%J I 10 SEC 0 I tiM 1 ~ 0 ~ RAM D~TA I I I 1~ D~~A 80 00 AlP HR HR 110DATE DATE 01 MONTH 01 I I 0 10 M 0 0 0 0 o I 00 DAY 01 I YEAR 10 YEAR IWp I C, I I MIN 1 0-99 0 SEC 10 MIN 01-07 [T21 1r;%1 1 4 3 12 121 011 24 1 0 00-23 l/wl 11 11 0 0 1 1 0 7 0 0 POWER ON RESET 1 1 Co ! X4 1 X 3 ! X21 x, I XO! 00 AO B. RAM RAM 0 RAM 23 RAM BURST 11 11 ~.1 I 1 I 0 I 1 1 11 11 0 •• • 1 1 I I 1 1 11 RAM 17w1 IX-5 I I XX • • • XX II CRYSTAL SELECTION The wide frequency range of crystals that can be chosen for the Clock/RAM offers the user a large degree of flexibility. To aid in the selection of a suitable crystal, the following suggestions should be considered by the user. First, the MK3805 offers an output pin that will provide a system clock signal at either the crystal frequency, % the crystal frequency, or % the crystal frequency. A system that requires a 4MHz clock initially may operate with an 8 MHz clock in the future. By applying an 8 MHz crystal to the Clock/RAM, a software change could provide the faster clock. Second, it is well known that, for a CMOS part, power dissipation will increase in direct proportion with frequency. Using a 1 MHz crystal and programming the CKO pin for 2048 Hz will cause the MK3805 to draw a minimum of power. (See Figures 9 and 10). The crystal connection is shown in Figure 5.lf a generated clock signal is to be used as a time base, the connection isto Pin 2 (CKI) with Pin 3 left floating. CRYSTAL CONNECTION SUMMARY OF CRYSTAL SPECIFICATIONS Figure 5 Figure 6 G x,,, AMP~lI-IF-IE-R---+-----4D~FIER Frequency Range Specification INPUT PIN2 1 MHz - 8.4 MHz Parallel resonance OUTPUT c, PIN 3 Fundamental mode GND c, =10 pf typical C 2 =20 pf typical CL _ - =20 pf to 40 pf AT cut If it is desirable to "tune" the oscillator to a precise frequency, C 2 may be a variable capacitor. C 2 should be in the range of . C, ~C2~2C,. For low frequency operation (1 MHz) C1 ... 10 - 20 pf For a high frequency operation (8 MHz) C 1 "'6 -10 pf. INPUT TIMING DIAGRAM Figure 7 SCLK 1/0 - - - - ( \ -J/ COMMAN~D~__________J/\~_______ DATA ______ ---------INPUT INPUT WRITE DATA TRANSFER (n Bits) IX·6 CRYSTAL FREQUENCY SELECTION Table 2 Crystal Frequency Divider Mode X4 X3 X2 X1 XO fXTAL (MHz) Crystal Frequency Binary Mode 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 8.388608 8.388608 4.194304 4.194304 2.097152 2.097152 1.048576 Reserved Microprocessor Mode 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 8.000000 5.000000 4.000000 2.500000 2.000000 1.250000 1.000000 Reserved Baud Rate Mode 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 7.372800 7.372800 3.686400 3.686400 1.843200 1.843200 0.921600 Reserved Color Burst Mode 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 7.159040 7.159040 3.579520 3.579520 1.789760 1.789760 0.894880 Reserved Comments Power on condition CLOCK OUTPUT SELECTION Table 3 C1 CO CKO Output Frequency 0 0 1 1 0 1 0 1 fXTAL fXTAL + 2 fXTAL + 4 = 2048 Hz Comments Power on condition Frequency applies for use with Binary Mode only. Other operating modes produce a CKO signal approximately equal to' 2000 Hz. IX-7 III ELECTRICAL SPECIFICATIONS MK3805N-03 ABSOLUTE MAXIMUM RATINGS* Voltage on Vee relative to GND ............................................................. -O.S V to + 12.0 V Voltage on any pin ...................................................................... -O.S V to + Vee + .S Temperature under bias ...................................................................... -SO°C + 9SoC Storage Temperature ....................................................................... -SsoC to +12SoC 'Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. DC OPERATING CONDITIONS O°C :::; TA :::; + 70°C SYMBOL PARAMETER MIN MAX UNIT NOTES Vee Supply Voltage 4.S S.S V 1 V SB RAM Retention Standby 3.S V 1,7 MAX UNIT NOTES DC ELECTRICAL CHARACTERISTICS O°C :::;TA :::; + 70°C, Vee = SV ± 10% SYMBOL PARAMETER MIN lecl Power Supply Current 6.0 mA 2 leC2 Power Supply Current 10.0 mA 3 ICC3 Power Supply Current 2.0 mA 4 lec4 Power Supply Current 600 J-LA S -1.0 1.0 p,A 6 -10.0 10.0 J-LA 6 V 1 V 1 III Input Leakage Current, SCLK and CE ILO Output Leakage Current, I/O Pin V IH Logic "1" Voltage, All Inputs except X1 V IL Logic "0" Voltage, All Inputs 2.2 0.8 V IHXl Logic "1" Voltage, Xl Input 3.9 V I/OH Output Logic "1" Voltage, 110 pin 2.4 VI/OL Output Logic "0" Voltage, I/O pin V eKH Output Logic "1" Voltage, CKO pin V eKL Output Logic "0" Voltage, CKO pin 8 0.4 2.4 0.4 NOTES: 1. All voltages referenced to GND. 2. Crystal/Clock Input frequency =8.4 MHz. fCKO = 4.2 MHz with 30 pf load. 3. Crystal/Clock input frequency = 8.4 MHz. fCKO =8.4 MHz with 100 pf load. 4. Crystal/Clock input frequency = 8.4 MHz. fCKO = 2084 Hz with 30 pf load. 5. 6. 7. 8. V 1(loH=-1 OOJ-LA) V 1(lOL = 3.8 mAl V 1(10H = 1.0 mAl V 1(lOL = S.O mAl Crystal/Clock Input frequency = 1 MHz. fCKO = 2048 Hz with a 30 pf load. Measuredwith VCC = 5.0V. O:5VI :55.0V. outputs in high impedance state. Applied to pin 8 to retain data in RAM during a power fault. VIHX1 spec. applies only to the external clock input configuration. CAPACITANCE TA = 2SoC MAX UNIT TEST CONDITION Capacitance on Input Pin 10 pF Note 1 CliO Capacitance on I/O pin 12 pF Note 1 Cx Capacitance on X1 /C1 and X2 12 pF Note 1 SYMBOL PARAMETER CI NOTE: l.6.t 1. Measured as C = .6.V· with V = 3 V. and unmeasured pins grounded. IX-8 AC ELECTRICAL CHARACTERISTICS O°C :5TA :5 + 70°C, Vcc = 5V ± 10% NUM SYMBOL PARAMETER MIN MAX UNIT NOTES Crystal frequency 800 8400 kHz 1.0 jJ.S 1,6 40 ns 1,6 1 fx 2 tcss CE to SCLKt set up time 3 tscs SCLK low set up time to CE 4 tSCH SCLKt to CEI hold time 1.0 jJ.S 1,5,6 5 toss Input Data to SCLKI set up time 400 ns 1,6 6 tSOH Input Data from 200 ns 1,6 7 tsoo Output Data from 600 ns 1,2,3,6 8 tcoz CEt to I/O high impedance 500 ns 1,2,3,6 9 tSWL SCLK low time 1.95 00 jJ.S 10 tSWH SCLK high time 1.95 00 jJ.S 11 fSCLK SCLK frequency DC 250 kHz SCLK~ ~ hold time SCLK~ delay time 12 t SR' tSF SCLK Rise and Fall Time 1 jJ.S 4,6 13 t CR ' tCF CKO Rise and Fall Time 50 ns 4,6 14 tCWH CE high time 2.0 NOTES: 1. Measured atVIH = 2.0VorVIL =O.BV and 50 ns rise and fall times on inputs. 2. Measured at VOH = 2.4V and VOL = O.4V. 3. Load Capacitance = 100 pF 4. tr and tf measured from O.BV to 2.2 V jJ.S 5. tSCH must follow the last rising edge of SCLK during a write cycle in order to allow time to complete a write to the internal register. 6. All voltages referenced to ground. OUTPUT TIMING DIAGRAM Figure 8 \ --JI\'-________----;;DATA~-------...;/ COMMAN_D_ _ '-----INPUT OUTPUT READ DATA TRANSFER (n Bits) IX-9 III ~ .. :!!S:~ c CC 6.6 _ 0 "'0 Cil O m O CO » OrlJf/) - -r G) XI l> ~ SELR2 DOT COUNTER CARRY 38-32 la. >.< en 39,40.1.2 ',-. 3 ,CHIP ENABLE 9 DATA STROBr ... 0'" SCROLL RESET START SELF LOAD 6 II OPERATION The design philosophy employed was to allow the MK3807 Programmable CRT Video Control Unit (VCU) to interface effectively with either a microprocessor based or hardwire logic system. The device is programmed by the user in one of two ways: via the processor data bus as part of the system initialization routine, or during power up via a Horizontal Formatting: Characters/Data Row PROM tied on the data bus and addressed directly by the Row Select outputs of the chip (See Figure 2). Seven 8-bit words are required to program the chip fully. Bit assignments for these words are shown in Tables 2, 3 and 4. The information contained in these seven words consists of the following: A 3 bit code providing 8 mask programmable character lengths from 20 to 132. The standard device will be masked for the following character lengths; 20,32,40,64,72, 80, 96, and 132. Horizontal Sync Delay 3 bits assigned providing up to 8 character times for generation of "front porch". Horizontal Sync Width 4 bits assigned providing up to 16 character times for generation of horizontal sync width. Horizontal Line Count 8 bits assigned providing up to 256 character times for total horizontal formatting. Skew Bits A 2 bit code providing from a 0 to 2 character skew (delay) between the horizontal address counter and the blank and sync (horizontal, vertical, composite) signals to allow for retiming of video data prior to generation of composite video signal. The Cursor Video Signal is also skewed as a function of this code. Vertical Formatting: I nterlaced/N on-interlaced This bit provides for data presentation with odd/even field formatting for interlaced systems. It modifies the vertical timing counters as described below. A logic 1 establishes the interlace mode. Scans/Frame 8 bits assigned, defined according to the following equations: Let X = value of 8 assigned bits. 1) in interlaced mode-scans/frame =2X + 513. Therefore for 525 scans, program X = 6 (00000110). Vertical sync will occur precisely every 262.5 scans, thereby producing two interlaced fields. Range = 513 to 1023 scans/frame, odd counts only. 2) in non-interlaced mode-scans/frame = 2X + 256. Therefore for 262 scans, program X = 3 (00000011 ). Range = 256 to 766 scans/frame, even counts only. In either mode, vertical sync width is fixed at three horizontal scans (=3H). Vertical Data Start 8 bits defining the number of raster scans from the leading edge of vertical sync until the start of display data. At this raster scan the data row counter is set to the data row address at the top of the page. Data Rows/Frame 6 bits assigned providing up to 64 data rows per frame. Last Data Row 6 bits to allow up or down scrolling via a preload defining the count of the last displayed data row. Scans/Data Row 4 bits assigned providing up to 16 scan lines per data row. IX-16 ADDITIONAL FEATURES MK3807 VCU Initialization: Under microprocessor control-The device can be reset under system or program control by presenting a 1010 address on A3-0. The device will remain reset at the top of the even field page until a start command is executed by presenting a 1110 address on A3-0. Via "Self Loading"-In a non-processor environment, the self loading sequence is effected by presenting and holding the 1111 address on A3-0, and is initiated by the receipt of the strobe pulse (OS). The 1111 address should be maintained long enough to ensure that all seven registers have been loaded (in most applications under one millisecond). The timing sequence will begin one line scan after the 1111 address is removed. In processor based systems, self loading is initiated by presenting the 0111 address to the device. Self loading is terminated by presenting the start command to the device which also initiates the timing chain. Scrolling-In addition to the Register 6 storage of the last displayed data row a "scroll" comma nd (address 1011) presented to the device will increment the first displayed data row count to facilitate up scrolling in certain appl ications. CONTROL REGISTERS PROGRAMMING CHART Table 2 Horizontal Line Count: Characters/Data Row: Horizontal Sync Delay: Horizontal Sync Width: Skew Bits Total Characters/Line = N + 1, N = 0 to 255 (DBO = LSB) DB2 DB1 DBO = 20 Active Characters/Data Row 000 o 0 1 = 32 010 = 40 o 1 1 = 64 1 0 0 = 72 1 0 1 = 80 0 1 1 = 96 1 1 1 = 132 = N, from 1 to Tcharacter times (DBO = LSB, N = 0 Disallowed) = N, from 1 to 15 character times (DB3 = LSB, N =0 Disallowed) Cursor Delay Sync/Blank Delay DB7 DB8 (Character Times) o 0 0 0 1 0 1 0 o 1 Scans/Frame Vertical Data Start: Data Rows/Frame: Last Data Row: Mode: Scans/Data Row: 2 2 1 2 8 bits assigned, defined according to the following equations: Let X = value of 8 assigned bits. DBO = LSB) 1) in interlaced mode- scans/frame = 2X + 513. Therefore for 525 scans, program X = 6 (0000110). Vertical sync will occur preCisely every 262.5 scans, thereby producing two interlaced fields. Range = 513 to 1023 scans/frame, odd counts only. 2) in non-interlaced mode-scans/frame = 2X + 256. Therefore for 262 scans, program X = 3 (00000011 ). Range = 256 to 766 scans/frame, even counts only. In either mode, vertical sync width is fixed at three horizontal scans (= 3H) N = number of raster lines delay after leading edge of vertical sync of vertical start position. (DBO = LSB) Number of data rows = N + 1, N = 0 to 63 (DBO = LSB) N = Address of last displayed data row, N = 0 to 63, ie; for 24 data rows, program N = 23. (DBO = LSB) Register 1, DB7 = 1 established Interlace Interlace Mode Scans per data Row = N + 2. N = 0 to 14, odd or even counts. Non-Interlace Mode Scans per Data Row = N + 1, odd or even count, N =0 to 15. IX·17 III SELF LOADING SCHEME Figure 2 l...f - DBO~~ .... ro' ... .A ... LA V'-' .... 1'1 ... ""'" ~ + A1 A 2 : A3; CE ! _LA """" Vr" ... t- .. .A ~ ""1'1 ........ ..... t... .....f'I ~ DB7 Ao MK3807 PROGRAMMABLE CRT VIDEO CONTROL UNIT (VCU) "J1 ....... ........ ""'" "" .... ..""FJ D<} ~~RO ... I~ R1 R2 R3 AO A1 MK2716 SLOAD (FROM SYSTEM) A2 A3 CE A4 +5 It ROW SELECTS TO CHARACTER GENERATOR OPTIONAL START-UP SEQUENCE When employing microprocessor controlled loading of the MK3807 VCU's registers, the following sequence of instruction may be used optionally: ADDRESS 1 1 1 0 101 0 COMMAND o 0 0 0 Start Timing Chain Reset Load Register 0 o o o Load Register 6 Start Timing Chain 1 Tlele sequence of START RESET LOAD START is necessary to ensure proper initialization of the registers. This sequence is not required if register loading is via either of the Self Load modes. IX-18 REGISTER SELECTS/COMMAND CODES Table 3 A3 0 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 AO 0 1 0 1 0 1 0 1 Select/Command Load Control Register 0 Load Control Register 1 Load Control Register 2 Load Control Register 3 Load Control Register 4 Load Control Register 5 Load Control Register 6 Processor Initiated Self Load Description 0 0 0 0 0 1 0 1 0 Read Cursor Line Address Read Cursor Character Address Reset See Table 4 Command from processor instructing MK3807 VCU to enter Self Load Mode (via external PROM) Resets timing chain to top left of page. Reset is latched on chip by OS and counters are held until released by start command. Increments address of first displayed data row on page, i.e.; prior to receipt of scroll command-top line =0, bottom line =23. After receipt of Scroll Command-top line = 1, bottom line = O. Up Scroll 0 o o 1 o o 1 Load Cursor Character Address' Load Cursor Line Address' Start Timing Chain Receipt of this command after a Reset or Processor Self Load command will release the timing chain approximately one scan line later. In applications requiring synchronous operation of more than one VCU the dot counter carry should be held low during the OS for this command. Device will begin self load via PROM when OS goes low. The 1111 command should be maintained on A3-0 long enough to guarantee self load. (Scan counter should cycle through at least once). Self load is automatically terminated and timing chain initiated when the all "1 's" condition is removed, independent of OS. For synchronous operation of more than one VCU; the Oot Counter Carry should be held low when the command is removed. Non-Processor Self Load NOTE 1: During Self-Load, the Cursor Character Address Register (REG 7) and the Cursor Row Address Register (REG 8) are enabled during states 0111 and 1000 of the R3-RO Scan Counter outputs respectively. Therefore, Cursor data in the PROM should be stored at these addresses. BIT ASSIGNMENT CHART Table 4 HORIZONTAL LINE COUNT SKEW BITS DATA ROWS/FRAME I I I I I I ~ I REG 317] II I REG 0 I; I i tic MODE INTERLACED/ H SYNC WIDTH H SYNC DELAY NON·INTERLACED I REG1171 el I _ SCANS/DATA ROW REG 21 X I! I 131.2~1 i i 101 LAST DISPLAYED DATA ROW REGel=x=l=xl:~=1===i==:llo=:1 SCAN LINES/FRAME REG41 I I I I _ I I I 10 1 REG717/ / / CHARACTERS/DATA ROW VERTICAL DATA START i I~ IffG I REG I I 10 1 CURSOR ROW ADDRESS -I ~ I I I i I I I' I ·1 xix I~ I REG IX-19 i/ CURSOR CHARCTER ADDRESS I i I I~ I II MAXIMUM GUARANTEED RATINGS* Operating Temperature Range ...................... , , , ,., , , , , , , , , , , , , , , , , , , , ,. , , , , , , , , , , , , , , , " ooe to + 70°C Storage Temperature Range " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " -55°C to + Lead Temperature (soldering, 10 sec.) " " " " " " ' . " " " " " " " " " " " " " " " " " " " " " " " " + Positive Voltage on any Pin, with respect to ground, , , , , , , , , , , , , , , , , , , , , , , , , , , , , . , . , .. , , , , , . , , , , , , , . , , + Negative Voltage on any Pin, with respect to ground, , .... , , , , , . , , . , .. , , . , , , , . , , . , , , , , , , , , . , . , , .... , .... 150°C 325°C 1S.0 V -0.3 V 'Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. NOTE: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their outputs when the AC power is switched on and off. In addition, voltage transients on the AC power line may appear on the DC output. For example, the bench power supply programmed to deliver +12 volts may have large voltage transients when the AC power is switched on and off. If this possibility exists it is suggested that a clamp circuit be used. DC CHARACTERISTICS (TA = ooe to 70°C, Vec = +5V ± 5%, VOO = +12V ± 5%, unless otherwise noted) PARAMETER INPUT VOLTAGE LEVELS Low Level, VIL High Level, VIH OUTPUT VOLTAGE LEVELS Low Level - VOL for RO-3 Low Level - VOL, all others High Level - VOH for RO-3, OBO-7 High Level - VOH all others MIN TYP MAX VCC V V 0.4 0.4 V V 250 10 pA. J,LA 15 40 15 pF pF pF 10 J,LA 100 70 mA mA O.S VCC-1.5 UNIT COMMENTS 2.4 2.4 INPUT CURRENT Low Level, IlL (Address, CE only) Leakage, IlL (All inputs except Address, CE) INPUT CAPACITANCE Data Bus, CIN OS, Clock, CIN All other, elN 10 25 10 IOL=3.2 ma IOL =1.6 ma IOH=SOJ,La IOH=40J,La VIN=0.4V O::;VIN ::;VCC DATA BUS LEAKAGE in INPUT MODE lOB POWER SUPPLY CURRENT SO 40 ICC 100 IX·20 0.4:5 VIN :5 5.25 V AC CHARACTERISTICS (TA = 70°C) PARAMETER MIN DOT COUNTER CARRY frequency PWH PWL t r , tf 0.5 35 215 TYP 4.0 10 DATA STROBE PWDS 150ns MAX 50 UNIT COMMENTS MHz Figure 3 Figure 3 ns Figure 3 ns Figure 3 ns 10jLs Figure 4 ADDRESS, CHIP ENABLE Set-up time Hold time 125 50 ns ns Figure 4 Figure 4 DATA BUS - LOADING Set-up time Hold time 125 75 ns ns Figure 4 Figure 4 125 60 ns ns Figure 4, CL =50pF Figure 4, CL =50pF 125 ns Figure 3, CL =20pF 750 ns Figure 5, CL =20pF DATA BUS - READING TDEL2 TDEL4 5 OUTPUTS, HO-7, HS, VS, BL, CRV CE-TDEL 1 OUTPUTS: RO-3, DRO-5 '" TDEL3 II AC TIMING DIAGRAMS VIDEO TIMING Figure 3 DOT COUNTER CARRY "11+ ~:I~ r~---------"~ ~ ~""'-.'-~----~--------------~----~-P-W-L----------------~--------------------~~J~--- PW H ~~ HO-7 H SYNC, V SYNC, BLANK, CURSOR VIDEO, COMPOSITE SYNC ... TDEL1---~ RESTRICTIONS ,. Only one pin is available for strobing data intothe device via the data bus. The cursor Xand Y coordinates are loaded into the chip by presenting one set of addressesand are output by presenting a different set of addresses. Therefore, the standard WRITE and READ control signals from most microprocessors must be "NORed" externally present a single strobe (5s) signal to the device. 2. In interlaced mode, the total number of character slots assigned tothe horizontal scan must be even to ensure that vertical sync occurs precisely between horizontal sync pulses. IX-21 LOAD/READ TIMING Figure 4 1~--------TSETUP1--------~-~1 ADDRESS CHIP ENABLE DBO-7 LOADING IN OF DATA DBO-7 READING OUT OF DATA os --------------------------------~ SCAN AND DATA ROW COUNTER TIMING Figure 6 HSYNC RO-3 DRO-5 --.-r----------------------_+-----:=-__-J ...... TDEL3* *RO·3 and DRO-6 may change prior to the falling edge of H sync GENERAL TIMING Figure 6 L START OF LINE N START OF LINE N+1 , .JI_--£.V"""-ZI,---"Z:....LI-,--ZZ,---"!t.....L..7",,,,-V'--I,I.J-/L-"IZr.....LZ-L-!-'--ZIl-J-7-'-/~O;....c..7.J-Z""--'7J~n h-V/T"TO-r-Z"""'Z HORIZONTAL TIMING - ACTIVE VIDEO = CHARACTERS PER DATA LINE ------~~~~ HORIZONTAL SYNC DELAY (FRONT PORCH) HORIZONTAL SYNC WIDTH HORIZONTAL LINE COUNT=H VERTICAL TIMING START OF FRAME M OR ODD FIELD /i00i_~-------------- START OF FRAME M+1 OR EVEN FIELD SCAN LINES PER FRAME ------------------'J.~I JI~__L..V7Z2'_'_'__iI..._.l.ZZ--'-Z"""_Z"-LO-'-Z4-l.7Z--'-7"""_Z4-I.ZZ--'-Z...!-".jOr.....LZ-'-Z..I..-jZZI-,L.Z-'-Z.s........J.Z1"-'-Z..I..-j/I1(,..."L..---1nL-_-L-VZZL..L-L. I_ VERTICAL DATA ~- --1 ACTIVE VIDEO = DATA ROWS PER FRAME START IX-22 _I ~ . L VERTICAL SYNC == 3H COMPOSITE SYNC TIMING Figure 7 V OH HSYNe --fl~n~-----!n,----~nL....--~nL...--_1L VOL: I : VOH : ,: I V SYNC ; VoL! :.--H VOH : ! .:. H-+\ ;"'HI2~ COMPOSITE SYNC VERTICAL SYNC TIMING Figure 8 --------i..~I. II(r-------FRAME . M+J - - - - - - - - - - - - - - FRAME M SCAN COUNTER IS HELD RESET DURING V BLANK, SCANS/DATA H ,I ROW 13579~ COUNTER-RO 0 2 4 6 8 0 2 4 6 8 0 N=9 DATA ROW COUNTER ~ MAINTAINS. LAST COUNT. DURING V BLANK DATA ROW COUNTER-DROl""_ _--=:-::-_ _-.a1 23 N=23 22 J o fVERTICAL DATA START SCAN = (REG5) BLANK JUUUUlJUlJUUU1.JlJ1JUUULJiLANk - C lJUU1JUUUUUUUUlJJUU1J1J1JUL VERTICAL SYNC -------------------------------EXAMPLE BASED ON NON-INTERLACED (REG 1. BIT 7~:= 0). 24 DATA ROWS. 10 SCANS/DATA ROW IX-23 II IX·24 1984/1985 MICROELECTRONIC DATA BOOK Ac~ce5.S Memory Programmed Microcomputer Products II UNITED MICROCOMPUTER COMPONENTS TECHNOLOGIES MOSTEK SERIAL CONTROL UNIT SCU20 FEATURES o SCU20 Figure 1 Provides programmable remote 1/0 functions, real time operational capabilities, and standardized network communications on a 40 pin chip. o Performs preprogrammed functions on command, including: • Byte input and output • Bit input and output • Set, clear, and toggle selected pins • Data access from real time functions o Performs real time preprogrammed functions, including: • Data log on external interrupt, timer, or host control, up to 63 bytes of data • Five Event Counters driven from external interrupt, timer or host control o Up to 24 programmable 1/0 pins o Allows user to network up to 255 SCUs on a single communications channel o o o o o Figure 2 Asynchronous serial data transmission. XTL1 Selectable Baud rate (300, 1200, 2400, or 9600 Baud) Secure, Error resistant data link protocol Requires single +5 volt supply 40 Vee XTL2 39 RESET PO-O 38 EXT. INT. PO-1 37 PO-2 36 SRCLK PO-3 SERAi5iN 35.SI 34 SO Low power (275mW typ) INTRODUCTION P4-0 33 P5-0 P4-1 32 P5-1 P4-2 31 P5-2 P4-3 11 30 P5-3 29 P5-4 P5-5 The SCU20 serial control unit is a preprogrammed MK3873 single chip microcomputer. It is a general purpose remote controlldata acquisition unit, with 38 preprogrammed functions available to the user. Communications with the SCU20 take place over an asynchronous half duplex communications channel at 300, 1200,2400, or 9600 Baud. The communications protocol is efficient and error resistant, and yet easy to implement on the host system. P4-6 14 P5-6 P4-7 15 P5-7 PO-7 16 BO PO-6 17 B1 PO-5 18 PO-4 19 GND 20 X-1 • The SCU20 can be used for both monitoring and control systems where remote intelligence is required. It can be configured to provide many different input/output and data acquisition functions through its 24 I/O pins. Such intelligent fu'nctions as Data Log and Event Counters allow many different applications that will not burden the host system with constant update requirements. SI - Serial input. Receives serial asynchronous data from the host. SO - Serial output. Transmits serial asynchronous data to the host. RTS - Request to send (output, active low). FUNCTIONAL PIN DESCRIPTION CTS - Clear to send (input, active low). The SCU20 is housed in a plastic 40 pin dual in-line package. RESET - External reset (input, active low). EXT. INT. - External interrupt (input, active low). SERADIN - Serial address input/address mode (input, active low. See SCU20 Address section). BO, B1 - Baud rate select. Vee - Power supply, 5 volts. GND- Power supply ground. Figure 2 shows the location of each pin on the SCU20. The following describes the function of each pin. SCU20 PINOUT DEFINITION XTL 1, XTL2 - Time base inputs for 3.6864 MHz crystal. PO-O - PO-7 - SCU20 port 0 (Bidirectional, active low). SCU20 address input or general purpose data port (see SCU20 Address section). Data available strobe for port 4 (output active low). P4-0 - P4-7 - SCU20 port 4 (Bidirectional, active low). General purpose data port. P5-0 - P5-7 - SCU20 port 5 (Bidirectional, active low). General purpose data port. SRCLK - SCU2 NETWORK The SCU2 Network is a serial linked network of devices in the SCU2 family. All communications are via a common serial link using the SCU2 family communications protocol. In this way, a distributed control facility may be easily implemented from standard parts, and controlled by the host computer via the serial link. Figure 3 illustrates the SCU2 Network. Clock signal generated by internal Baud rate generator. SCU2 NETWORK Figure 3 HOST .----------------r---~------ SCU2x #1 SCU2x #2 - - - - -------, SCU2x #n X·2 the only command that does not require a specific SCU2x address as part of the command. It uses the system reset address which is recognized by each device. Each SCU2x in the network has an individual address to, which it will respond. All SCU2x devices in the network are slave processors to the host, and are unable to initiate communications except in response to the host. SCU20 ADDRESS When the system is initialized, all SCU2x devices are in the listen mode, and are performing no functions. The host will issue an inquiry command to each device. Once all devices have been queried, the host will issue commands to each device to set up the particular operational parameters required of it. When this has been done, the host may then use the devices to control equipment, measure values, etc., by issuing commands and receiving responses. The address to which the SCU20 responds may be established in one of two ways. The first mode is the Direct Strapped Address mode, and is enabled bytying the SERADIN pin directly to ground. In this mode, the SCU20 address is strapped at port O. Because of this, port 0 is not available as a general purpose I/O port. Unless issuing a response, the SCU2x is always in the listen mode. If a command has been sent to an SCU2x, a response is expected within a specific time period. If none is forthcoming, it means that the command transmitted was not successfully received by the device. In this case, the host must take steps either to notify the operator orto retransmit the command. The second mode is the Serial Address Input mode. The SERADIN pin is used to input the address as a serial 8-bit stream from a shift register. SRCLK is used as a shift clock for this operation. The STROBE signal is used at initialization time to cause the address to be loaded into the shift register before shifting begins. In the Serial Address mode, port 0 becomes available for use as a general purpose data I/O port. If a system error occurs in the host, it may suspend operation of the entire network by transm itti ng the network reset command which causes all devices to be reset. This is Figure 4 illustrates both methods of establishing the SCU20 address. SCU20 ADDRESS ESTABLISHMENT Figure 4 DIRECT STRAPPED ADDRESS • II 16 .3 SCU20 SERIAL ADDRESS INPUT SCU20 ~ ADDRESS t SHIFT REGISTER LD - SERADIN .. SC I SRCLK STB X-3 37 36 SCU20 COMMUNICATIONS MODEM SIGNALS The SCU20 communicates with the host computer over a half duplex asynchronous serial link. The communications protocol is simple, yet error resistant. RTS and CTS are provided to facilitate handshaking with modems. Just prior to responding to a valid command, RTS will go to logic 1, indicating thatthe SCU20 is ready to send data back to the host. CTS is an input to the SCU20 that is tested after RTS goes active to determine if the SCU20 may begin transmitting data. The general form of the communication message is as follows: IHDR I ADDR I CMD I DATA I DATA I. • • • I LRC HDR - PARALLEL 1/0 PORTS I Message header. Hex '01' indicates a command message from the host; Hex '02' indicates a response from the SCU20. ADDR - SCU20 Address. Indicates which SCU20 the message is for, or originates from. The Data Direction Register defines the usage of each pin in the port. If a bit is set to 0, then the corresponding pin is used as input. If a bit is set to 1, then the corresponding pin is used as an output. When a port is read, all bits are sampled for input whether or not they are marked for input. When a port is written to, however, only those pins declared as output will be modified. CMD - Command. Indicates the function to be performed. DATA - Any data that may be required by the particular command. LRC - The SCU20 has a minimum of 2 parallel 1/0 ports and a maximum of 3 available for general use, depending on the address selection mode chosen. For each of these ports, there exist 2 registers that control and modify the 110 to and from the ports. These are the Data Direction Register (DDR) and the Mask Register(MR). The Mask Register provides a data mask that may be applied to the input dat;:! before transmission to the master. The mask is established once and may be used repeatedly before being changed by establishing a new mask value. If a pin is to be available upon read, the corresponding bit in the mask register is set to 1, while a pin that is to be masked out will have its mask bit set to O. Linear Redundancy Check. 214 Bit Times Message Separation < a Bit Times Byte· Separation SCU20 PREPROGRAMMED FUNCTIONS Messages are to be transmitted in block mode, with a message separation of at least 14 bit times. Interbyte separations should be no more than a bit times within a message. The SCU20 has a variety of preprogrammed functions available to the user. Each of these functions addresses a different general area of application such that the SCU20 is truly a general purpose device. A message from the host to the SCU20 will generate a response if there is no transmission error. If any transmission error is detected, no response will be made. PORT COMMANDS Possible transmission errors are LRC errors, parity errors, interbyte separation errors, or intermessage separation errors. BAUD RATE SELECTION LOGIC COMMANDS The serial Baud rate is selected by a strapped option on the SCU20. Those options are listed below: BAUD RATE BO iPin 25) B1 iPin 24) 300 1200 2400 9600 Low Low High High Low High Low High There are several commands which allow the host to manipulate the a-bit general purpose 110 ports. The host may load data into anyone or all of the ports, may read any or all of the ports with or without a mask, may read with a new mask, or may read using the last defined mask. When data is loaded, the resulting port state is returned in the response message. In addition to performing data 1/0 with the ports, the host may perform logical operations with the ports and data from the host. These commands allow the host to AND, OR, or Exclusive OR (XOR) data with any or all of the ports, and output the result to the ports. The resultant output is returned in the command response message. X·4 BIT COMMANDS as the entire SCU2 network. These commands provide the host with the ability to query each individual SCU2x on the network for its type, the last message it sent, and for detailed error codes. In addition, there are commands that allow the host to reset an individual device, or to cause the entire SCU2 network to reset with a single command. These commands allow the host to SET, CLEAR, TEST, or TOGGLE bits in the ports by specifying bit number (0 - 24). Any pin that is declared as an input will not be changed. EVENT COUNTERS ERROR PROCESSING There are 5 Event Counters defined in SCU20. They are 16 bit up counters, and are driven by the timer, the external interrupt, or by host command. They may be used as simple event counters, or may be used in conjunction with the Data Log, and Pulse functions. The SCU20 does not provide a "negative acknowledge" response to command stream errors. Those errors are parity errors, LRC errors, unidentifiable commands, overrun, or violation of the separation specifications as described earlier. DATA LOG In some cases, the SCU20 will provide error response to functional errors in commands that have been recognized. This response will be either a "NAKO" or a "NAK3" as specified for the command. "NAKO" is the hex value H'FB', and "NAK3" is the hex value H'FE'. The Data Log function allows the user to command the SCU20to log data from the ports specified in the command, and store the data in the on-board RAM. Up to 63 bytes of data may be accumulated in the log, and may be captured on external interrupt, timer, or host command through use of an Event Counter. IH'2' I ADDR I H'FB' or H'FE' LRC Data from the Log is transmitted back to the host in a single read command burst. SCU20 COMMANDS CONTROL COMMANDS Figure 5 gives a complete list of the commands and functions available to the SCU20. For a full description of these commands and their use, refer to the SCU20 Operations Manual. There are several commands to control the SCU20 as well SCU20 COMMANDS Figure 5 FUNCTION COMMAND CODES # DATA # DATA BYTES (CMD) BYTES (RESP) 3 1 3 0 0 1 3 0 0 0 1 3 1 3 1 3 1 3 ERR COD RET ** PORT COMMANDS ** Load Data Direction Registers Load Port (0,4,5) Load All Ports Read Port (0, 4,5) Read All Ports Read Port Masked, Mask Provided Read All Ports, Masks Provided Read Port using Previous Mask Read All Ports using Previous Masks 1E 00,01,02 03 04,05,06 07 08,09,OA OB OC,OD,OE OF X-5 - - • ** PORT LOGIC COMMANDS ** 10,11,12 13 14,15,16 17 18,19,1A 1B AN 0 Data to Port AND Data to All Ports OR Data to Port OR Data to All Ports XOR Data to Port XOR Data to All Ports 1 3 1 3 1 3 1 3 1 3 1 3 - 1 1 1 1 0 0 1 1 - 1 1 1 1 1 0 2 0 0 0 3 0 0 0 var. 1 NAKO 0 0 0 1 0 var. 1 1 0 NAK3 - - ** BIT COMMANDS ** 1F 20 21 22 Set Bit in Port Clear Bit in Port Toggle Bit in Port Test Bit in Port ** EVENT COUNTERS ** Start Event Counter Read Event Counter Clear Event Counter Stop Event Counter Step Event Counter 80 81 82 83 84 NAKO NAKO NAKO NAKO ** DATA LOG COMMANDS ** Start Data Log Stop and Read Data Log Read Data Log Count 85 86 87 - ** SCU CONTROL COMMANDS ** Enquiry Return SCU Type Read Error Code Reset SCU20 (data byte must be H'AA') General Reset (SCU2 Network) 1C 10 F7 F9 FF X-6 - - ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ..................................................................... -20 0 e to +85°C Storage Temperature ....................................................................... -65°e to +150°C Voltage on any Pin With Respect to Ground (Except open drain pins and TEST) .............................................................. -1.0 V to +7 V Voltage on TEST with Respect to Ground .................................•...................... -1.0 V to + 9 V Voltage on Open Drain Pins With Respect to Ground .......................................... -1.0 V to +13.5 V Power Dissipation .................................................................................. 1.5 W Power Dissipation by anyone I/O pin2 ................................................................ 60 mW Power Dissipation by all I/O pins2 ................................................................... 600 mW 'Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. OPERATING VOLTAGES AND TEMPERATURES Operating Voltage Vee .......................................................................... +5 V ± 10% Operating Temperature TA ........................................................................ 0° - 70°C AC CHARACTERISTICS TA' Vee within specified operating range. I/O Power Dissipation:::; 100 mW (Note 2) SIGNAL SYM PARAMETER MIN MAX XTL1 XTL2 to Time Base Period, all clock modes 250 500 ns tex(H) tex(L) External clock pulse width high External clock pulse width low 90 100 400 400 ns ns t Internal clock STROBE t l/O - s output valid to STROBE delay 3t -1000 3t +250 ns I/O load = 50 pF + 1 TTL load tsL STROBE low time 8t -250 12t +250 ns STROBE load = 50 pF + 3TTL loads tRH RESET hold time, low 6t +750 ns t RPoe RESET hold time, low for power clear power supply rise time ms RESET UNIT NOTES 4 MHz - 2 MHz 3.6864 required for standard baud frequencies 210 +0.1 EXTINT tEH EXT INT hold time in active and inactive state X-7 6t +750 ns To trigger interrupt • CAPACITANCE TA = 25°C All Part Numbers SYM PARAMETER CIN Input capacitance; I/O, RESET, EXT INT CXTL Input capacitance; XTL 1, XTL2 M'fl\i""" MAX UNIT NOTES 10 pF 23.5 29.5 pF MIN MAX unmeasured pins grounded AC CHARACTERISTICS FOR SERIAL I/O PINS TA' V cc within specified operating range. I/O Power Dissipation:::; 100 mW (Note 2) SIGNAL SYM PARAMETER UNIT CONDITIONS SRCLK tr(SRCLK) Serial Clock Rise Time 60 ns 0.8V - 2.0V CL = 100 pf ~(SRCLK) Serial Clock Fall Time 30 ns 2.4 V - 0.4 V CL =100 pf DC CHARACTERISTICS TA' V cc within specified operating range. I/O Power Dissipation:::; 100 mW (Note 2) MAX UNIT Average Power Supply Current 103 mA SCU20 Outputs Open Power Dissipation 485 mW SCU20 Outputs Open SYM PARAMETER Icc Po MIN x-a DEVICE DC CHARACTERISTICS TA , Vee within specified operating range I/O Power Dissipation ~ 100 rnW (Note 2) SYM PARAMETER MIN MAX UNIT V 1HEX External Clock input high level 2.4 5.8 V V 1LEX External Clock input low level -.3 .6 V IIHEX External Clock input high current 100 pA V IHEX = Vee IILEX External Clock input low current -100 pA V ILEX = VSS V IHIIO I/O input high level 2.0 5.8 V standard pull-up (1 ) 2.0 13.2 V open drain (1) 2.0 5.8 V standard pull-up (1 ) 2.0 13.2 V No pull-up 2.0 5.8 V standard pull-up (1) 2.0 13.2 V No pull-up -.3 .8 V (1 ) V IHR V IHEI Input high level, RESET Input high level, EXT INT CONDITIONS V IL I/O ports, RESET', EXT INT' input low level IlL Input low current, I/O ports and EXT IN -1.6 rnA VIN = 0.4 V IL Input leakage current, RESET input +10 -5 pA pA VIN = 13.2 V VIN = O.OV IOH Output high current, I/O ports -100 pA V OH = 2.4 V -30 pA V oH =3.9V IOL Output low current, I/O ports 1.8 rnA VOL = 0.4 V IOHS STROBE Output High current -300 p.A VOL = 2.4 V IOLS STROBE output low current 5.0 rnA VOL = 0.4 V X-g • DC CHARACTERISTICS FOR SERIAL PORT I/O PINS TA, Vcc within specified operating range I/O Power Dissipation:::; 100 rnW (Note 2) MIN MAX UNIT Input High for SI 2.0 5.8 V V llS Input Low level for SI -.3 .8 V IllS Input low current for SI -1.6 rnA Vil = 0.4 V IOHSO Output High Current SO -100 -30 /-LA /-LA V OH = 2.4 V V ol =3.9V IOlSO Output Low Current SO 1.8 rnA V Ol =O.4V IOHSRC Output High Current, SRCLK -300 /-LA V OH = 2.4 V IOlSRC Output Low Current, SRCLK 5.0 rnA VOL = 0.4 V SYM PARAMETER V IHS TEST CONDITIONS NOTES 1. 2. RESET and EXT INT have internal Schmitt triggers giving minimum .2 V hysteresis. Power dissipation for I/O pins is calculated by ~(VCC - VIL) ( IlL) + ~(VCC - VOH) ( 10H ) + ~(VOL) (IOL) AC TIMING DIAGRAM Figure 6 External Clock Internal

+RETURN + LINE FEED Prompt character. Informs the computer that the EPROM programmer has successfully executed a command. F+RETURN + LINE FEED Fail character. Informs the computer that the EPROM programmer has failed to execute the last-entered command. ?+RETURN + LINE FEED Question mark. Informs the computer that the EPROM programmer does not understand a command. TECHNICAL SPECIFICATIONS ELECTRICAL SPECIFICATIONS Dimensions Serial Communication Link 7.8 in (19.8 cm) x 10.8 in. (27.4 cm) 2.0 in. (5.1 cm) maximum thickness RS232 or TTL compatible Operating Temperature Power Supply Requirements 11 5 V AC @ 200 ma XI-24 SOfTWARE COMMAND The high level commands supported by the RADIUS software for EPP-1 are: OUTPUT xxxx xxxx 'filename' COMMAND DESCRIPTION BATCH 'filename' Accept command input from a Host file BIT Illegal bit test on EPROM BLANK Check if EPROM is blank COMPARE 'filename' Compare data from Host to EPROM Programmer DEVICE xxxx Select the device address to be used for programming, verifying, or loading device data DIRECT Allows direct entry of commands to the EPROM programmer via the console. May be terminated with control-C. FAMILY [xxxx] Select/display the family/ pinout HELP [Command name] Display a HELP description of all commands or of a specific command DESCRIPTION Output data from EPROM programmer to Host *(pause [msg]) Pause while in batch mode; message can be displayed. PROGRAM Program EPROM device with data in RAM QUIT Exit the utility; return EPROM programmer to keyboard control RAM xxxx Select RAM address to be used for data transfer SHUFFLE xxxx Merge 2 blocks of RAM; complement of SPLIT SIZE xxxx Select the hex number of bytes to be transferred; must be selected after RAM command SPLIT xxxx Split even/odd numbered bytes into 2 blocks; complement of SHUFFLE SUM Calculate check-sum of programmer RAM INPUT 'filename' Input data from Host to EPROM programmer SWAP Swap nibbles in every byte in RAM LOAD Load EPROM data from the EPROM into RAM TRANSPARENT LOG 'filename' Log console activity to a Host file Allows RADIUS development system transparent communication to Host VERIFY MEMORY xxxx [xxxx] Display or update EPROM programmer RAM Verify EPROM device with data in RAM MOVE xxxx xxxx xxxx Move a block of data in RAM OFFSET xxxx Select an offset to be added to input addresses and subtracted from output addresses XI·25 II EPROMs SUPPORTED The following EPROMs may be programmed by the EPP-1 . MANUFACTURER PART # SIZE FAMILY /PINOUT CONFIGURATION # ADVANCED MICRO DEVICES 4716 2Kx8 1923 ELECTRONIC ARRAYS 2716 2Kx8 1923 FUJITSU 8516 (2716) 2Kx8 1923 HITACHI 46532 4Kx8 1925 HITACHI 46732 4Kx8 1924 INTEL 2758 1K x 8 1922 INTEL 2716 2Kx8 1923 INTEL 2732 4Kx8 1924 INTEL 2764 8Kx8 3533 MITSUBISHI 2716 2Kx8 1923 MOSTEK 2716 2Kx8 1923 MOTOROLA MCM2716 2Kx8 1923 MOTOROLA 2532 4Kx8 1925 MOTOROLA 68764 8Kx8 6424 NATIONAL SEMICONDUCTOR 2716 2K x8 1923 NATIONAL SEMICONDUCTOR 2532 4Kx8 1925 NATIONAL SEMICONDUCTOR 2732 4Kx8 1924 NIPPON ELECTRIC 2716 2Kx8 1923 OKI 2716 2Kx8 1923 TEXAS INSTRUMENTS 2508 1K x8 1922 TEXAS INSTRUMENTS 2516 2Kx8 1923 TEXAS INSTRUMENTS 2532 4Kx8 1925 TEXAS INSTRUMENTS 2564 8Kx8 3130 TOSHIBA 323 2Kx8 1923 XI-26 EPP-1 DIRECT COMMAND SUMMARY CONTROL COMMANDS RETURN Execute a command ESC Abort a command UTILITY COMMANDS G Software Configuration number This command returns a 4-digit hex number representing the software configuration of the programmer. Set Begin RAM BLOCK LIMIT L 1. Defines first RAM address (in HEX) to be used for data transfers. Also functions as the RAM source address in the RAM-RAM Block Move command. (HHHH); Set Block Size BLOCK LIMIT L2. Sets number of bytes (in HEX) to be transferred. Must be set after the Set Begin RAM command is used. (HHHH): Set Begin Device BLOCK LIMIT L3. Sets the first device address (in HEX) to be used in data transfers. Also functions as the destination address in the RAM-RAM Block Move Command. S Sum-Check Causes programmer to calculate the check-sum of RAM data and output it to the computer. F Error-Status Inquiry EPROM programmer returns a 32 bit error code. X Error-Code EPROM programmer outputs Error Codes stored in scratchpad RAM and then clears them from memory. H No operation This is a null command and always returns a prompt character (». T Illegal Bit Test Test for illegal bit in a device. B Blank Check Check that no bits are programmed in a device. Family and Pinout EPROM programmer sends a 4-digit number (FFPP) where FF is the family code and PP is the pinout in effect. Select Family and Pinout A 2-digit family code (FF) and pinout code (PP) specifies programming of a particular device. R Respond Programmer indicates status and outputs device word limit, byte size, and programming pulse polarity. L Load Load device data into RAM. P Program Program RAM data into device. V Verify Verify device against RAM. (HHHH)< DEVICE COMMANDS (FFPP)@ XI·27 • ORDERING INFORMATION Designator Description EPP-1 EPROM PROGRAMMER w/wall mount transformer (US) MK78229-0 EPP-1 EPROM PROGRAMMER w/in line transformer (international) MK78299-1 Part No. EPP-1 Technical Manual 4420379 XI-2S I! UNITED TECHNOLOGIES MOSTEK SYSTEMS TECHNOLOGY VME MATRIX 68K MICROCOMPUTER SYSTEM MK75102 FEATURES o VMEbus compatible o 68000 Processor and 68451 Memory Management Unit on CPU board o 512K byte dynamic RAM with byte parity and longword (32 bit) capability o 128K byte additional dual-ported dynamic RAM on CPU board o 36M byte (unformatted) 5% inch Winchester disc o 1M byte (unformatted) 5% inch floppy disc o Real time calendar clock o Parallel (Centronics compatible) output port o UNIPLUS+ (UNIX SYSTEM III plus Berkley 4.1 enhancements) * OIS - Single processor - Multiuser (5 MAX) o BOOT68K MONITOR (firmware) - Initialization - Bootstep loading - Serial host down loading - Diagnostics - Transparent mode - Console interface o 68000 ASSEMBLER o C COMPILER o DIAGNOSTIC PACKAGE o 3 Spare VMEbus slots for expansion, backplane 32 bit data paths o FCC Approved "NOTE: UNIX is a trademark of BELL LABORATORIES. UNIPLUS+ is a trademark of UNISOFT SYSTEMS. VME MATRIX 68K SYSTEM Figure 1 MATRIX 68K DESCRIPTION The MATRIX 68K is a multiuser, VMEbus based, UNIX system designed around the powerful 68000 microprocessor.The MATRIX 68K has seven VMEbus compatible cards (see Figure 2), 36M byte of Winchester hard disk storage and 1 M byte of floppy storage. The system also has five serial ports, one parallel printer port (Centronics compatible) and 640K byte of main memory (512K byte on the DRAM and J 28K byte on the MMCPU). All of this is packaged in an enclosure measuring 12.25 inches high x 17.7,5 inches wide X 26 inches deep, containing a ten slot double-VME motherboard (fully capable of 32-bit data transfers),Mostek 1/0 Panels and a power supply available in either 115 or 230 volt AC versions; The software provides the ability to efficiently develop software for VMEbus applications. The MATRIX68K software includes the UniPlus+ (UNIX System III) Operating System, 68000 Assembler, C Compiler and a Mostek system diagnostic package. The system firmwa'l'e, BOOT 68K, initializes the system, controls bootstrap loading and has a number of convenient utilities. XI-29 • OPTIONAL SOFTWARE PACKAGES The following software packages are available as additions to the basic software described above: • • • • FORTRAN COMPILER PASCAL COMPILER MOSTEK MACRO ASSEMBLER/LINKER 68000 RECONFIGURATION OPTION MATRIX 68K BLOCK DIAGRAM Figure 2 VME BUS SYSCON MMCPU SIO 4 CHANNELS DRAM 256KB/BOARD (2 EACH) SASI 4 TERMINALS DISK DRIVE XI-30 FDC IB UNITED TECHNOLOGIES MOSTEK SYSTEMS TECHNOLOGY MATRI)(TM-80/SDS MICROCOMPUTER DEVELOPMENT SYSTEM INTRODUCTION MATRIXTM-80/SDS Figure 1 The Mostek MATRI)(TM is a complete state-of-the-art, floppy disk-based computer. Not only does it provide all the necessary tools for software development, but it provides complete hardware/software debug through Mostek's AIMTM series of in-circuit emulation cards for the 68000, Z80, and the 3870 family of single-chip microcomputers. The MATRIX has at its heart the powerful OEM-80E (Single Board Computer), the RAM-80BE (RAM I/O add-on board), and the FLP-80E (floppy disk controller board). Because these boards and software are available separately to OEM users, the MATRIX serves as an excellent test bed for developing systems applications. The disk-based system eliminates the need for other mass storage media and provides ease of interface to any peripheral normally used with computers. The file-based structure for storage and retrieval consolidates the data base and provides a reliable portable media to speed and facilitate software development. Development System Features The MATRIX is an excellent integration of both hardware and software development tools for use throughout the complete system design and development phase. Debug can then proceed inside the MATRIX domain using its resources as if they were in the final system. Using combinations of the Monitor, Designer's Debugging Tool, execution time breakpoints, and single step/multistep operation along with a formatted memory dump, provides control for attacking those tough problems. The use of the Mostek AIMTM options provides extended debug with versatile hardware breakpoints on memory or port locations, a buffered in-circuit emulation cable for extending the software debug into its own natural hardware environment. Package System Features From a system standpoint, the MATRIX has been designed to be the basis of an end-product, such as a small business/industrial computer. Other hardware options are available, with even more to be added. Expansion of the disk drive units to a total of four single-sided or double-sided units provides up to two megabytes of storage. This computer uses the third-generation Z80 processor supported with the power of a complete family of peripheral chips. Through the use of its 158 instructions, including XI-31 16-bit arithmetic, bit manipulation, advanced block moves and interrupt handling, almost any application from communication concentrators to general purpose accounting systems is made easy. OEM Features The hardware and software basis for the MATRIX is also available separately to the OEM purchaser. Through a software licensing agreement, all Mostek software can be utilized on these OEM series of cards. MATRIX RESIDENT FIRMWARE (DDT-SO) The Designer's Debugging Tool consists of commands for facilitating an otherwise difficult debugging process. The MATRIX allows rapid source changes through the editor and assembler. This is followed by DDT operations which close the loop on the debug cycle. The DDT commands include: Memory Port Execute Hexadecimal Copy - display, update, or tabulate memory - display, update or tabulate I/O ports - execute user's program - performs 16 bit add/sub - copy one block to another II provided. Symbolic addressing and an extensive HELP Facility ease the use of AIM-6S000. MATRIX SYSTEM SPECIFICATIONS • • • • • • • • • • Z80 CPU 4K-byte PROM bootstrap and Z80 debugger 60K bytes user RAM (56K contiguous) 8 x 8 bit I/O ports (4 x PIO) with user-definable drivers/ receivers Serial port, RS 232 and 20 mA current loop 4 channel counter/timer (CTC) 2 single-density, single-sided disk drives; 250K bytes per floppy disk 3 positions for AIM modules, Serial Interface, etc. PROM programmer I/O port. Programmer itself is optional. Bus compatible with Mostek SDE series of OEM boards HARDWARE DESCRIPTION OEM-SOE CPU Module The OEM-SOE provides the essential CPU power of the system. While using the Z80 as the central processing unit, the OEM-80E is provided with other Z80 family peripheral chip support. Two Z80 PIO's give 4 completely programmable 8 bit parallel I/O ports with handshake from which the standard system peripherals are interfaced. Also on the card is the Z80-CTC counter timer circuit which has 3 free flexible channels to perform critical counting and timing functions. Along with 16K of RAM, the OEM-80E provides 5 ROM/PROM sockets which can be utilized for 10/20K of ROM or 5/1 OK PROM. Four sockets contain the firmware. The remaining socket can be strapped for other ROM/PROM elements. RAM-SOBE AIM-ZSOBE (S.O MHz max. clock rate) The AIM-ZSOBE is an improved Z80 In-Circuit-Emulation module usable at Z80-CPU clock rates of up to 6MHz. The AIM-ZSOBE is a two processor solution to In-Circuit Emulation which utilizes a Z80-CPU in the buffer box for accurate emulation at high clock rates with minimum restrictions on the target system. The AIM-Z80BE provides real time emulation (no WAIT states) while providing full access to RESET, NMI and INT control lines. Eight single byte software breakpoints (in RAM) are provided as well as one hardware trap (RAM or ROM). The emulation RAM on the AIM-Z80BE is mappable into the target system in 256 byte increments. A 1024 word x 48 bit history memory is triggerable by the hardware intercept and can be read back to the terminal to provide a formated display of the Z80-CPU address, data, and control busses during the execution of the program under test. Several trigger options are available to condition the loading of the history memory. AIM-7XE The AIM-7XE module provides debug and in-circuit emulation capabilities for the 3870 series microcomputers on the MATRIX. Multiple-breakpoint capability and singlestep operation allow the designer complete control over the execution of the 3S70 Series microcomputer. Register, Port display, and modification capability provide information needed to find system "bugs." All I/O is in the user's system and is connected to AIM-7X by a 40-pin interface cable. The RAM-SOBE adds additional memory with Mostek's MK4116 16K dynamic memory along with more I/O. These two fully programmable 8-bit I/O ports with handshake provide additional I/O expansion as system RAM memory needs to grow. Standard system configuration is 4SK bytes for a system total of 60K bytes user RAM (56K contiguous). The debugging operation is controlled by a mnemonic debugger which controls the interaction between the Z80 host computer and the 3870 slave. It includes a history module for the last 1024 CPU cycles and also supports all 3870 family circuits. FLP-SOE DCC-SOE Integral to the MATRIX system is the floppy disk controller. The FLP-SOE is a complete IBM 3740 single-density/ double-sided controller for up to 4 drives. The controller has 12S bytes of FIFO buffer resulting in a completely interruptable disk system. The DCC-80E multi-channel serial controller board was developed as a general purpose four port serial I/O card. DCC-SOE can be user configured to interconnect computer systems and will support SDLC and BYSINC protocols. OPTIONAL MODULES COMPATIBLE WITH MATRIX Assembly and linking are done using cross products supplied by Mostek or other vendors. AIM-saooo (10 MHz max. clock rate) MECHANICAL SPECIFICATIONS The AIM-68000 is an advanced development tool which provides project debug capabilities for both hardware and software via in-circuit emulation of the MK68000 Microprocessor. Real-time emulation is provided up to 10 MHz operation. Flexible breakpoints and Single-Step emulation with Invisible Break on Register Contents are Overall Dimensions: CPU subsystem - 8" High x 21" wide x 22" deep (20.3 cm x 53.3 em x 55.8 em) Disk Subsystem - 8" High x 21" wide x 22" deep (20.3 em x 53.3 cm x 55.S em) XI-32 Humidity: up to 90% relative, noncondensing. ELECTRICAL SPECIFICATIONS Material: Structural Foam (Noryl) INPUT 100/115/230 volts AC ± 10% 50 Hz (MK78189) or 60 Hz (MK78188) Weight: CPU Subsystem 25 Ibs (11.3 Kg) Disk Subsystem 50 Ibs (22.7 Kg) OUTPUT CPU subsystem Fan Capacity: 115 CFM +5 VDC at 12A max. +12 VDC at 1.7A max. -12 VDC at 1.7A max. Card Cage: Six slots DIN 41612 type connectors Disk subsystem Operating Temperature: +1 O°C to +35°C +5 VDC at 3.0A max. -5 VDC at 0.5A max. +24 VDC at 3.4A max. ORDERING INFORMATION See Development System Products ordering guide. PERIPHERALS AND CABLES NAME DESCRIPTION PART NO. PPG-8/16 Programmer for 2708,2758 and 2716 PROM Includes interfacing cables to MATRIX. MK79081-1 SD-WW Wire wrap card compatible with MATRIX. MK79063 SD-EXT Extender card compatible with MATRIX. MK79062 LP-CABLE Interface cable from MATRIX Microcomputer to Centronics 306 or 702 printer MK79089 PPG-CABLE Interface cables from MATRIX to PPG-8/16 PROM programmer (MK79081). MK79090 XI-33 II XI-34 B UNITED TECHNOLOGIES MOSTEK SYSTEMS TECHNOLOGY EVAL-70 3870 EVALUATION SYSTEM FEATURES o An ideal hardware and/or software design aid for the MK38P70 and MK3870 family of Single-Chip Microcomputers o Includes a 2K byte firmware monitor o Keypad for command and data entry o 7 -segment address and data display o Programming socket for MK2716/2758's o Crystal controlled system clock EVAL-70 Figure 1 o 2K bytes of MK4118 static RAM (up to 4K optional) o Sockets for up to 4K bytes of MK2716 PROM's o Flexible memory map strapping options o Current loop or RS-232 serial loader optional (110-3001200 baud) o 3 general purpose timer/counters o 3 general purpose external interrupts o Easy to use - requires only two supplies for normal operation (+5, +12) o Ideal for evaluation of MK3870 family single-chip microcomputers o USING EVAL-70 Full in-circuit emulation of MK3870 single-chip microcomputer family. DESCRIPTION EVAL-70 is a single board computer with on-board keypad, address and data displays, and 2716 PROM programmer. EVAL-70 is designed to be an easy-to-use introduction tothe industry standard MK3870 family of single-chip computers. Programs can be written and debugged in RAM using the powerful DDT-70 operating system. The 40 pin AIM cable can be used to perform real-time emulation of the MK3870 family of devices. After debugging, programs can be loaded into MK2716's for final circuit checkout (and emulation). The photograph above shows how EVAL-70 is used as a program development tool. Only an external power supply is required for operation of EVAL-70; the built-in keyboard and display offer all the functions needed to design, develop, and debug programs for the MK3870 family of single-chip microcomputers at the machine code level. COMMAND SUMMARY OM: Display memory: allows memory to be displayed and (RAM) updated. DR: Display registers: allows the user's register values to be displayed and updated. DP: Display ports: allows the contents of ports 0 thru F to be displayed and updated HX: Hex calculator: allows hexadecimal arithmetic calculations to be performed (add and subtract) GO: causes execution of a user program at a specified address XI-35 II BK: Breakpoint: allows a breakpoint to be set or reset ST: Step: ca uses si ng Ie-step execution of a user program at a specified address LD: Load: initiates the serial loader (optional) MV: Move: allows a block of memory to be moved or copied from one space to another RO, R8: Read PROM: causes the PROM programmer socket to be read into address space 00-7FF or 800-F7F PO, P8: Program PROM: causes the contents of address space 000-7FF or 800-F7F to be programmed into the PROM programmer socket EVAL-70 KEYBOARD DRAWING IEIUIRlllllDI BLOCK DIAGRAM EVAL-70 uses several membersofthe F8 multichipfamily. A MK3850 Central Processing Unit (CPU) provides the ALU, registers, system control and two 8-bit ports. A MK90071 Peripheral Input Output chip (Pia) provides two more 8-bit ports plus a flexible timer/interrupt control block. These four ports are connected to the AIM cable connector for in-circuit emulation of the MK3870 family devices, and also to the PROM programmer socket. An additional Pia (MK90073) interfaces the LED display and keyboard. A MK3853 Static Memory Interface chip(SMI) interfaces the operating system ROM, uptotw02KPROMsand uptofour 1 KRAMs.Aswitch option allows either the 4K of PROM or the 4K of RAM to appear at address OOOOH, with the other 4K appearing at 1000H. The operating system ROM may be up to 8K (currently 2K) starting at 8000H. A switch option allows reset to either OOOOH or to the 8000H ROM. USING EVAL-70 WITH LARGER SYSTEMS BLOCK DIAGRAM Although the EVAL-70 operating system (DDT-70) was designed to make program machine code entry simple and quick, many users will find it more efficient to assemble their programs on a larger computer and then download to EVAL-70. PIO MK90071 CPU MK3850 The download to EVAL-70 may be accomplished in either of two ways: 1) SMI PIO MK3853 MK90073 2) KEYBOARD XI-36 A PROM may be programmed on the Development System, and then read into RAM by the EVAL-70 for debugging. A direct connection may be made between a serial port on the Development System and the serial loader port on EVAL-70. An optional serial loader program is provided in the EVAL-70 Operations Manual. DEVELOPMENT SYSTEM DEVELOPMENT SYSTEM EVAL-70 XI-37 II EVAL-70 BOARD SPECIFICATIONS Operating Temperature: O°C - 50°C Power Supplies Required: +5VDC ±5% 1.0A max +12VDC ±5% 0.1A max +25VDC ±5% 0.1 A max Board Size: 8.5 in. (21.6 cm) x 12 in. (30.5cm) x 2 in. (5cm) Connectors and Cables: 40 pin in-circuit-emulation cable is provided. ORDERING INFORMATION See Development System Products ordering guide. XI-3S m UNITED TECHNOLOGIES MOSTEK SYSTEMS TECHNOLOGY FLEXIBLE DISK OPERATING SYSTEM - M/OS-SO USER FEATURES o Virtual CPIMTM compatibility gives the user many available programs to choose from. M/OS-80 provides a direct migration path to CP/M compatibility without any changes to the system hardware. SYSTEM FEATURES o Additional utilities and systems commands provide increased capability and functionality to the user. o M/OS-80 is a more sophisticated and powerful floppy disk operating system than any other micro-operating system available. It provides the user with a unique, but invisible, library structure. By assigning one system disk as a Master Library disk, the system can free the user to place all application-related files on another disk while still having the utility of the various system programs on-line. Provided on standard media for use with Mostek standard systems and MD Series boards for short system integration time. INTRODUCTION M/OS-80 is a CPIMTM compatible, floppy disk operating system for the MD or SO series of microcomputer board systems. It offers a comprehensive solution to a wide variety of system design problems. The software is provided on an 8-inch single-sided, single-density floppy diskette which can be booted on Mostek disk-development systems or user-configured systems (see "Hardware Required" paragraph). M/OS-80 can be altered for different inputloutput hardware configurations by using the MOSGEN Utility (sold separately). Unlike other operating systems, M/OS-80 provides the user with comprehensive error messages. In most cases, methods of recovery are displayed and the operator is given several options from which to choose. HARDWARE REQUIRED M/OS-80 is currently supplied in three versions. V3 is designed to run on Mostek's MATRIX systems and on systems built with MD Series boards. An MD Series system must contain the following boards: Several powerful utilities are provided with M/OS-80. These programs give the user a broad base of support and will improve design efficiency. These include: Item Processor Console Interface Printer Interface Floppy Interface Memory Editior (Edit) Designer's Development Tool (Debugger) Transfer Utility (XFER) FilelDisk Dumps (DSKDUMP) Print Utility (PRINT) Print Spooler (SPOOL) Several System Utilities The V5 system is for use with a Mostek Phantom PROM system configuration. The following boards are required: Because of M/OS-80's CP/M compatibility, a large number of pre-written programs are available. M/OS-80 is designed to run programs written for other CP IMcompatible operating systems, such as CDOSTM, I/OSTM, and SDOSTM, provided these programs conform to the standards described by Digital Research in versions 1.4 through 2.2. Virtually all compilers and interpreters now sold for use on CP1M (versions 1 .4 -2.2) will work. For those Mostek customers who are currently running FLP-80DOS, CPIM is a Trademark of Digital Research. Inc. COOS is a Trademark of Cromemco. Inc. Hardware Required MDX-CPU1 or MDX-CPU2 MDX-EPROM/UART or MDX-SIO MDX-PIO or MDX-SIO MDX-FLP1 or MDX FLP2 (2) MDX-DRAM with 64K of RAM Item Processor Floppy Interface Memory Hardware Required MDX-CPU3 or MDX-CPU4 MDX-FLP2 (2) MDX-DRAM with 64K of RAM (required only for MDX-CPU4) The V6 system is for use with a Mostek Phantom hard-disk system. The following boards are required: SOOS is a Trademark of SO Systems. Inc. liaS is a Trademark of Infosoft Systems. Inc. XI-39 • Item Processor Floppy Interface Memory Hard Disk Interface Hardware Required MDX-CPU3 or MDX-CPU4 MDX-FLP2 (2) MDX-DRAM with 64K of RAM (required only for MDX-CPU4) Delete a line(s) or character(s) Put a block of text into another file Get a block of text from another file View text on the console screen Print text on the line printer Create a set of commands which can be executed as a macro MDX-SASI1 & MDX-SASI2 XFER - Transfer Utility With either the V3, V5 or V6, M/OS-80 requires 64K bytes of RAM for operation. Four bootstrap PROMs are supplied with V3, and one bootstrap PROM is supplied with V5 orV6. The system initially must have at least one 8-inch, singlesided, single-density floppy disk drive in order to boot-up M/OS-80. Up-to-four disk drives are supported. The V6 configuration can also boot-up from hard disk. The XFER'program is a general-file transfer utility. It allows for the moving of files from disks or devices to other (or the same) disks or devices. The XFER features include: Transfer an ASCII file Compare two files without moving Filter out illegal ASCII characters Conditionally transfer a file (user prompted) Transfer a Read-Only file Expand tabs Verify files after moving Print HEX address of comparison failure Transfer only old files Transfer only new files Table 1 details the peripheral and CPU configurations required for the M/OS-80 versions. M/OS-SO CONFIGURATION SUMMARY Table 1 DSKDUMP - Disk Dump PERIPHERALS CPU1 CPU2 CPU3 CPU4* UART Console SIO Console STI Console SIO Line Printer PIO Line Printer STI Line Printer FLP1 FLP2 SASI V3 V3 V3 V3 N/A N/A V5/6 V5/6 V5** 16 V5** 16 N/A N/A N/A N/A N/A V3** V3 V3** V3 N/A N/A N/A N/A V5/6 V5/6 V3 V3*** * V3 V3*** * N/A N/A V5/6 V5/6 V6 V6 PRINT - Print Utility Not Applicable. Future Design. SID line printer configuration is supplied as alternate on systems disk. Single-density only. NOTE: 1. MOSGEN Utility may be purchased to configure systems for different peripherals and smaller sizes of RAM. See the MOSGEN Data Sheet for more information. EDIT - Text Editor The ASCII EDITor file provided with M/OS-80 provides a text editor for users who do not have access to a screeneditor. The editor allows creation and modification of the text files by several easy-to-use commands. EDIT features include: Find a text string Change a text string Find a line Insert new text The DSKDUMP program allows reading or modifying of a file, the disk data area, or the disk directory. Each block requested is read into a 128-byte buffer, then displayed. The blocks are numbered sequentially. Any block can be selected, displayed, modified, and written back to the disk. The PRINT utility formats ASCII files to the CRT or printer with automatic headings, tabbing and pagination. Userspecified options include page width and length, page headings, date printed of the top of each page, and page formatting. SPOOL - Print Spooler The SPOOL file system feature is used to output a file from the printer to a system list device while the system continues with other functions. Any ASCII file may be spoolprinted, and direct printer activity is prevented while a spoolprint is active. Other System Utilities M/OS-80 provides several other system utilities to permit a user the highest degree of flexibility in the manipulation of the files and programs created and used with the system. Some of these utilities include: programs to format disks, change disk labels, examine directories, and to diagnose disk problems. A PROM programming utility is also included that interfaces with Mostek's PPG 8/16. XI-40 ORDERING INFORMATION DESIGNATOR DESCRIPTION PART NO. M/OS-80V3 One diskette containing all M/OS-80 programs in binary, four bootstrap PROMs, and one Operations Manual. (See Table 1 for hardware configuration requirements.) Requires the signed Software License Agreeement (enclosed) with purchase order. MK71 01 OC-81 M/OS-80V5 One diskette containing all M/OS-80 programs in binary, one bootstrap PROM, and one Operations Manual. (See Table 1 for hardware configuration requirements.) Requires the signed Software License Agreement (enclosed) with purchase order. MK71 011 C-81 M/OS-80V6 One diskette containing all M/OS-80 programs in binary, one PROM for booting from floppy or hard disk, and an Operations Manual. (See Table 1 for hardware configuration requirements.) Requires the signed Software License Agreement (enclosed) with purchase order. MK71012C-81 M/OS-80 Operations Manual Detailed description of the operation and use of the M/OS-80 software package. 4420064 MOSGEN System generation utilities and device drivers, data sheet 4420268 M80/L80 BASIC-80 BASCOM FORTRAN-80 Microsoft language packages, data sheet 4420309 AIM-Z80 In-circuit-emulation for Z80, data sheet 4420245 • XI-41 XI-42 m UNITED TECHNOLOGIES MOSTEK SYSTEMS TECHNOLOGY MICROSOFT MBO/L80 MICROSOFT BASIC-80 MICROSOFT BASCOM MICROSOFT FORTRAN-80 - MK71002 MK71003 MK71004 MK71005 FEATURES BASIC-SO o M/OS-80 development aids for Z80 microcomputer o CP /MTM compatible o Macro assembler BASIC-80 is the most extensive implementation of BASIC available for the Z80 microprocessor. In three years of use, it has become the world standard for microcomputer BASICs, meeting the requirements for the ANSI subset standard for BASIC, and supporting many unique features rarely found in other BASICs. o Relocating linking loader o BASIC interpreter and compiler o FORTRAN compiler o Common relocatable object format-link modules in different languages BASCOM INTRODUCTION A series of Microsoft program development tools are now available from Mostek. They offer a comprehensive solution to a wide variety of system and application design problems. The software is provided on 8-inch single-sided singledensity floppy diskettes and operates under M/OS-80. MSO/LSO M80 is a relocatable macro assembler for Z80 microcomputer systems, incorporating almost all "big computer" assembler features without sacrificing speed or memory space. The M80/L80 package is comprised of the M80 assembler, L80 linking loader, and a cross reference utility. Portions of this data sheet are copyrighted by Microsoft, Inc. CP/M is a trademark of Digital Research, Inc. XI-43 Microsoft's BASIC compiler (BASCOM) is a powerful new tool for programming BASIC applications or microcomputer system software. The single-pass compiler produces extremely efficient, optimized machine code that is in standard Microsoft relocatable binary format. Execution speed is typically 3-1 times faster than interpreter BASICs. The M80/L80 assembler/linker package is included with BASCOM. a FORTRAN-SO Microsoft's FORTRAN-80 package provides new capabilities for users of Z80 microcomputer systems. FORTRAN-80 is comparable to FORTRAN compilers on large mainframes and minicomputers. All of ANSI standard FORTRAN X3.9-1966 is included except the COMPLEX data type. Therefore, users may take advantage of the many application programs already written in FORTRAN. The M80/L80 assembler/linker package is included with FORTRAN-80. II ORDERING INFORMATION DESIGNATOR DESCRIPTION PART NUMBER M801L80 Relocating macro assembler/linker on diskette, with operations manual MK71002C-80 BASIC-80 BASIC interpreter on diskette, with operations manual MK71003C-80 BASCOM BASIC compiler on diskette with operations manual (includes M80/L80) MK71004C-80 FORTRAN-80 FORTRAN compiler on diskette, with operations manual (includes M80/L80) MK71005C-80 M/OS-80 CP /MTM compatible disk operating system data sheet 4420271 XI-44 m UNITED TECHNOLOGIES SYSTEMS MOSTEK TECHNOLOGY ASM-68000 STRUCTURED MACRO CROSS ASSEMBLER LNK-68000 RELOCATING LINKAGE EDITOR FOR DECTM PDP-11™, VAXTM, OR VME-MATRIX 68K BENEFITS ASM-68000 is one of the most powerful tools available for assembly language programming of the MK68000 microprocessor. The assembly language is standard and virtually compatible with the Motorola definition. The package is easy to install on any DECTM PDP-11 TM, VAX:rM, orVME-Matrix 68KTM computer system. Coupled with RADIUSTM and AIM-68000™ for debugging/incircuit-emulation, the ASM-68000 package offers the user complete software development capability. is used to translate source statements written in the MK68000 assembly language into relocatable object code (68000 machine language). The assembler assigns storage locations to instructions and data and performs auxiliary assembler actions designated by the user. The LNK-68000 Relocating Linkage Editor, supplied with the package, combines relocatable object code modules into an absolute load module ready to be debugged. Debugging can be completed using Mostek's RADIUS Remote Development Station and AIM-68ooo in-circuit-emulator. The package is designed to be run on a host minicomputer such as the DEC PDP-11 family, the DEC VAX (running in compatiblity mode) or the VME-Matrix 68K microcomputer system. The ASM-68ooo/LNK-68ooo package is supplied on magnetic tape or floppy diskette. FEATURES ASM-68000 o The ASM-68000 provides the programmer with the means to translate standard MK68000 assembly language source statements into relocatable object code for subsequent input to the LNK-68000 Linkage Editor. The assembler generates a complete printed listing containing the source language input, assembled object code, and additional information, such as error messages, which are useful to the programmer. In addition, a symbol table and cross reference table can be requested to provide additional information. Absolute or relocatable code generation o Uses Motorola standard asembly language mnemonics and addressing modes and directives for macros and conditional assembly o Provides enhanced macro and conditional assembly capability o Provides structured control statements for efficient programming: IF-THEN-ELSE FOR-ENDF LOOP-ENOL REPEAT-UNTIL WHILE-ENDW EXIT o Provides for complex expression evaluation o Produces a complete assembly listing including symbol table and cross reference listing o Provides a listing formatting option which wi" automatically align source statement fields and indent structured statements o Package includes the Relocating Linkage Editor GENERAL DESCRIPTION Mostek's ASM-68ooo Structured Macro Cross Assembler "DEC, PDP, VAX, RSX, and VMS are trademarks of Digital Equipment Corporation. Matrix, RADIUS, and AIM are trademarks of Mostek Corporation. XI-45 Assembly is a five-phase process: the macro phase, structured phase, symbol definition phase, code generation phase, and cross reference listing phase. The macro phase reads in the user-specified input file and processes the macro, conditional, and include directives (if any). The structured phase translates the user-specified control structures into their corresponding executable instruction sequences. The symbol definition phase creates a symbol table, associating user-defined labels with values and addresses. In the code generation phase, the translation from source language to machine language takes place, using the symbol table. As each source line is processed in turn, the assembler generates appropriate object code and the assembly listing. The cross reference phase outputs the symbol table to the listing file. Ifthe cross reference option is requested, the cross references are written out with the symbol table. A" standard mnemonics are accepted for instructions and operands, assembler directives, symbolic names, operators and expressions, macros, and conditional assembly • directives. All of the Motorola defined syntax is allowed. In addition, the assembler provides enhanced macro and conditional facilities, and a set of powerful structured statements. The assembler produces a relocatable object module in Mostek relocatable format which contains information to allow LNK-68000 to combine modules and assign memory addresses. This offers many advantages to the user: reassembly is not required when the locations of subroutines are changed; the object module is substantially smaller than the source program; relocation is faster than reassembly; and relocation is handled automatically by the Linkage Editor. The ASM-68000 completely checks the syntax of the user program and generates messages in the listing when errors are found. The messages are explicit, and they detail the source of the error. The user guide supplied with the assembler describes how to correct the error. OPTIONS The Assembler allows the following options to be selected by the user: Program assembly control: ORG SECTION OFFSET END EQU SET REG DC DS DCB - Absol ute origin - Relocatable program section - Defines offsets - Program end - Assigns permanent value - ASSigns temporary value - Defines register list - Defines constants - Defines storage - Defines constant block Listing output control: PAGE [NO]LlST [NO]FORMAT SPC n LLEN n TTL string OPT FAIL - Ejects listing page Enables or disables the listing Enables or disables formatting of listing Skips n lines Sets line length on listing Specifies title for listing Specifies assembler options Generates error condition Linkage Editor control: [NO]OBJECT - Selects or deselects the object output [NO]LlST - Selects or deselects the listing output [NO]MACRO - Selects or deselects the listing of macro expansions [NO]CROSS REFERENCE - Selects or deselects the cross reference/l isti ng [NO]STRUCTUR E - Selects or deselects listing ofthe code generated by structured control statements [NO]FORMAT - Selects or deselects formatting of the source listing [NO]MOTOROLA - Selects Mostek - or Motorola - format input souce IDNT XDEF XREF - Generates identification record for LNK-68000 - External symbol definition - External symbol reference Macro and conditional assembly directives: MACRO ENDM MEXIT IFC ENDC INCLUDE - Macro definition - End of macro definition - Terminates macro expansion - Conditional assembly - End of conditional assembly - Inserts code from another source file LANGUAGE Macro functions: All standard M K68000 assembly language mnemonics and addressing modes are allowed. Symbols may be any number of characters, the first eight of which are significant. The first character of a symbol may be upper or lower case letters or a period. Additional characters may be upper or lower case letters, numbers, dollar sign, period, or underscore. Numbers may be specified as octal (preceded with @), binary (preceded with %), decimal, or hexadecimal (preceded with $). ASCII strings are included in apostrophes. Expression operators include arithmetic (+ - * f), shift »), and logical (& for AND, ! for OR). «< DIRECTIVES Assembler directives for controlling operation of the assembler include the following: XI-46 IARG(n) INARG INEXP IQUAL - Returns string of the nth macro argument - Returns number of parameters in a macro call - Expands to decimal number representing the expansion number of the macro - Expands to the qualifier name of the macro call STRUCTURED CONTROL STATEMENTS The ASM-68000 accepts structured control statements which provide for higher-level constructs. These statements make a program more readable and improve programming efficiency without compromising the desirable aspects of programming in assembly language. Several formats of the structured statements are available and are described below: OPTIONS The LNK-68000 provides a number of user selection options: - If, then, end if structure - If, then, else, end if IF-THEN-ELSE-ENDI structure IF-THEN-ELSEIF-ELSE-ENDI - If, then else if, else, end if structure FOR-BY-DO-ENDF - FOR structure FOR-DOWNTO-BY -DO-ENDF - FOR DOWNTO 'structure - Looping structure LOOP-ENDL - Exit a FOR, LOOP, EXIT REPEAT, or WHILE loop - REPEAT structure REPEAT-UNTIL - WHILE structure WHILE-DO-ENDW IF-THEN-ENDI A - Accepts user commands from the command input device B - Forces E;lach relocatable section to start on a page boundary H - Lists header information in each object module to the listing file - Lists the command line and all user commands to the listing file M - Lists the load map S - Allocates segments which do not have a userspecified starting address sequentially U - Lists any unresolved references at the end of pass 1 on the console X - Lists the external symbol definitions to the listing file Expressions used in the above statements allow testing of condition codes in the Condition Code Register of the 68000, comparing of simple operands such as used in a compare instruction, and checking of compound expressions which make use of logical AND and OR operations. The comparison operators include: minus less than always true not equal higher or same overflow set carry set less than or = lower plus carry clear greater than greater than never true or equal The LNK-68000 generates syntax error messages, fatal messages, and warning messages for the user. These messages detail the source of the error. The user manual supplied with the Linkage Editor describes how to correct the error. USER COMMANDS Any sequence of commands may be placed in a separate user command file and executed by the Linkage Editor upon request. The following user commands are provided: equal lower or same overflow clear higher - Extends (or replaces) the input file name capability of the command line - Causes an immediate, orderly halt to all ABORT processing - Signals the end of the user commands END - Assigns an absolute value to a symbol DEFINE specified in XREF directive in the program - Indicates the beginning execution address ENTRY of the load module being produced SEGMENT - Defines a memory management unit segment for the load module - Defines the starting address at which a START particular section(s) will be stored - Directs all listings to the listing device LIST - Produces an immediate listing of the LlSTM current load map - Produces an immediate listing of all LlSTU currently unresolved external references - Produces an immediate listing of the LlSTX current external symbol definitions INPUT LNK-68000 The LNK-680oo Relocating Linkage Editor accepts object modules generated by ASM-68000 and combines them into an absolute load module ready for subsequent debugging. The linker can be directed to generate the absolute load module in either Mostek HEX format or Motorola S-record format, which are not currently compatible with the UNIX operating system. The user can specify up to four "segments" of memory. For example, ROM code can be contained in a segment separate from RAM data. Up to 16 relocatable sections, plus absolute and named common sections (limited only by available memory) may be allocated among the segments. Comprehensive listing output options are provided, including a load map, externally defined symbols, undefined symbols, multiply defined symbols, segment lengths, and error counts. A library feature enables the user to load only the modules needed from library files. Extensive control of LNK-68000 is provided interactively at link time, including section order, address assignment, resolution of undefined references, and generation of listings. OPERATING ENVIRONMENT The ASM-68000 package is supplied in two forms: 1) the DOS-11 formatted, 9-track, 800BPI magnetic tape in compiled object form, ready to link and run on DEC PDP-11 XI-47 • computers under RSX-11 M or on DEC VAX computers under VMS in compatibility mode and 2): one double-sided, double density 5%-inch floppy diskette in executable object format, ready to install on the VME-Matrix 68K system UniPlus+ is a trademark of Unisoft System Incorporated. UNIX is a trademark of Bell Laboratories and signifies software derived from UNIX System III under license from AT&T. under UniPlus+™ Operating System (UNIXTM System III). Command files for automated installation are provided. Complete instructions are included with the package. Debugging can be completed by using Mostek's RADIUS Remote Development Station and the AIM-68(x)() incircuit-emulator. See the appropriate data sheet for more information. ORDERING INFORMATION PART NUMBER DESIGNATOR DESCRIPTION ASM-68(x)() MK68000 Structured Macro Coss Assembler, with manuals, includes LNK-68000, for RSX11 M or VAX in compatibility mode. RADIUS RADIUS Remote Development Station Data Sheet 4420194 AIM-68000 MK68000 Application Interface Module Data Sheet 4420316 ASM/LNK 68000 MK68000 Structured Macro Cross Assembler, with manuals. Includes the LNK-68ooo, for VME-Matrix 68K/UniPlus+. ASM-68ooo Manual only 4420297 LNK-68ooo Manual only 4420299 VME-Matrix 68K VME based developmental system. Uses the UniPlus+ version of UNIX. It comes equipped with a 36 MB Winchester Drive, 2 1-MB 5%-inch floppy disk, and a 640K bytes of memory. MK75102 XI-48 MK71020C-33 MK71020C-56 IJ UNITED TECHNOLOGIES MOSTEK SYSTEMS TECHNOLOGY ASM-68200 STRUCTURED MACRO CROSS ASSEMBLER LNK-68200 RELOCATING LINKAGE EDITOR BENEFITS ASM-682oo is a powerful state-of-the-art tool used in the assembly language programming of the MK68200 microcomputer. The assembly language contains macro statements and structured control statements which are similar to those found in higher level languages. These features can improve program readability and programming efficiency. The package is easy to install and runs on any DECTM PDP-1 pM under RSX-11 MTM, VAXTM under VMSTM in compatibility mode, or VME-MATRIX 68KTM system under the UniPlus+™ operating system which is a UNIXTM system III port. ASM-682oo is coupled with RADIUSTM and AIM-682ooTM for debugging and in-circuit-emulation. The ASM-682oo package offers the user complete software development capability. FEATURES o Generates absolute or relocatable code o Assembles the MK68200 standard instruction mnemonics and directives o Provides enhanced macro and conditional assembly capability o Provides structured control statements for efficient programming: IF-THEN-ELSE FOR-EN OF LOOP-ENOL REPEAT-UNTIL WHILE-ENDW EXIT o Provides for complex expression evaluation o Produces a complete assembly listing including a symbol cross reference listing o Provides a listing formatting option which will automatically align source statement fields and indent structured statements o The package includes the Relocating Linkage Editor DESCRIPTION Mostek's ASM-682oo Structured Macro Cross Assembler is used to translate source statements, written in the *DEC. PDP-11. RSX. VAX. and VMS are trademarks of Digital Equipment Corporation. MK68200 assembly language, into relocatable object code (68200 machine language). The assembler assigns storage locations to instructions and data, and it performs auxiliary assembler actions designated by the user. The LNK-682oo Relocating Linkage Editor, supplied with the package, combines relocatable object code modules into an absolute load module, which is ready to be debugged. Debugging can be completed using Mostek's RADIUS Remote Development Station and AIM-682oo in-circuit-emulator. The package runs on a host minicomputer such as the DEC PDP-11 family, the DEC VAX, or microcomputer such astheVMEMATRIX 68K/UniPlus+. The ASM-682oo/LNK-682oo package is supplied on magnetic tape or floppy diskette. ASM-68200 The ASM-682oo provides the programmer with the means to translate standard MK68200 assembly language source statements into relocatable object code for subsequent input to the LNK-682oo Linkage Editor. The assembler generates a complete printed listing containing the source language input, assembled object code, and additional information, such as error messages that are useful to the programmer. In addition, a symbol cross reference table can be requested to provide additional information. Assembly is a five-phase process that includes a macro phase, a structured phase, a symbol definition phase, a code generation phase, and an optional cross reference listing phase. The macro phase reads in the user-specified input file and processes the macro, conditional, and include any directives. The structured phase translates the userspecified control structures into their corresponding executable instruction sequences. The symbol definition phase creates a symbol table, aSSOCiating user-defined labels with values and addresses. In the code generation phase, the translation from source language to machine language takes place using the symbol table. As each source line is processed, in turn, the assembler generates the appropriate object code and the assembly listing. The cross reference phase outputs a symbol table with cross references to the listing file. The assembler produces a relocatable object module in Mostek relocatable format. which contains information to allow LNK-682oo to combine modules and assign memory addresses. This offers advantages to the user. A program may be partitioned into a number of small modules that may be assembled separately and linked together. Individual XI-49 • program sections may be relocated in memory without reassembly, and general purpose object libraries may be created and searched at link time. Program assembly control: ORG SECTION OFFSET END EOU SET REG DC DS DUP The LNK-68200 generates syntax error messages, fatal messages, and warning messages for the user. These messages detail the source of the error; and the user manual, supplied with the Linkage Editor, describes how to correct the error. OPTIONS The Assembler allows the following options to be selected by the user: - Absolute origin Relocatable program section Defines offsets Program end Assigns permanent value Assigns temporary value Defines register list Defines constants Defines storage Duplicates constant block listing output control: [NO]OBJECT - Selects or deselects the object output. [NO]LlST - Selects or deselects the listing output. [NO]MACRO - Selects or deselects the listing of macro expansions. [NO]CROSS REFERENCE - Selects or deselects the cross reference listing. INO]STRUCTURE - Selects or deselects listing of the code generated by structured control statements. [NO]FORMAT - Selects or deselects formatting of the source listing. PAGE Ejects listing page [NO]LlST - Enables or Disables the listing [NO]FORMAT - Enables or Disables formatting of listing SPC n - Skips n lines LLEN n - Sets line length on listing TTL string - Specifies title for listing OPT - Specifies assembler options FAIL Generates error condition linkage Editor control: IDNT XDEF XREF LANGUAGE - Generates identification record for LNK-68200 - External symbol definition - External symbol reference Macro and conditional assembly directives: A program consists of sequences of assembly language source statements. Source statements may include executable instructions, assembler directives, macro statements, structured statements, or comment statements. Each source statement has an overall format that is some combination of the following fields: 1. LABEL 2. OPERATION MACRO ENDM MEXIT IFC ENDC INCLUDE 3. OPERAND 4. COMMENT - Macro definition End of macro definition Terminates macro expansion Conditional assembly End of conditional assembly Inserts code from another source file Macro functions: User-defined symbols include macro names and labels, which may be referenced in the operand field. The first char·acter of a user-defined symbol must be a letter, and the remaining characters can be composed of letters, digits, or an underscore. User-defined symbols may be of any length, but only the first eight characters are significant. Expressions in the operand field may include arithmetic operators (+ - * I), shift operators »), and logical operators (& for AND, ! for OR). Numbers may be specified as octal (preceded with @), binary (preceded with %), decimal, or hexadecimal (preceded with $). ASCII strings are included in apostrophes. IARG(n) INARG INEXP «< DIRECTIVES Assembler directives for controlling operations of the assembler include the following: IOUAL - Returns string of the nth macro argument - Returns number of parameters in a macro call - Expands to decimal number representing the expansion number of the macro - Expands to the qualifier name of the macro call STRUCTURED CONTROL STATEMENTS The ASM-68200 accepts structured control statements that provide for higher-level constructs. These statements make a program more readable and improve programming efficiency without compromising the desirable aspects of programming in assembly language. Several formats of the XI-50 structured statements are available and are described below: IF-THEN-ENDI IF-THEN-ELSE-ENDI IF-THEN-ELSEIF-ELSE-ENDI FOR-TO-DO-ENDF A - Accepts user commands from the command input device. B - Forces each relocatable section to start on a page boundary. H - Lists header information in each object module to the listing file. - Lists the command line and all user commands to the listing file. L - Specifies an object library to be searched if there are any unresolved references. M - Lists the load map. Selects load module format of S-record or Hex. S - Allocates segments that do not have a userspecified starting address sequentially. U - Lists any unresolved references at the end of pass 1 on the console. X - Lists table of externally defined symbols to the listing file. If, then, end if structure If, then, else, end if structure If, then, else if, else, end if structure - FOR structure FOR-DOWNTO-DO-ENDF FOR DOWNTO structure LOOP-ENOL Looping structure. REPEAT-UNTIL REPEAT structure WHILE-DO-ENDW - WHILE structure EXIT - Exit a FOR, LOOP, REPEAT, orWHILE loop Expressions used in the above structured statements allow testing of condition codes in the Status Register of the 68200 and comparison of simple operands, such as those used in the compare instruction. Compound expressions, which make use of logical AND and OR operations, are also supported. The following statements illustrate the use of the REPEAT-UNTIL construct and a compound expression: a - The LNK-68200 generates syntax error messages, fatal messages, and warning messages for the user. These messages detail the source of the error; and the user manual, supplied with the Linkage Editor, describes how to correct the error. USER COMMANDS Any sequence of commands may be placed in a separate user command file and executed by the Linkage Editor upon request. The following user commands are provided: REPEAT MOVE (AO)+, (A 1)+ UNTIL AO #1000 OR (AO) #0 INPUT ABORT LNK-68200 END DEFINE The LNK-68200 Relocating Linkage Editor accepts object modules generated by ASM-68200 and combines them into an absolute load module ready for subsequent debugging. The load module can be generated in either Mostek HEX format or Motorola S-record format. ENTRY SEGMENT The user can specify up to four "segments" of memory. For example, ROM code can be contained in a segment separate from RAM data. Upto 16 relocatable sections, plus absolute and named common sections (limited only by available memory), may be allocated among the segments. Comprehensive listing output options are provided including a load map, externally defined symbols, undefined symbols, multiply defined symbols, segment lengths, and error counts. A library feature enables the user to load only the modules needed from library files. Extensive control of LNK-68200 is provided interactively at link time including section order, address assignment, resolution of undefined references, and generation of listings. START LIST LlSTM LlSTU LlSTX LIBRARY OPTIONS The LNK-68200 provides a number of user selectable options: XI-51 - Extends (or replaces) the input file name capability of the command line. - Causes an immediate, orderly halt to all processing. - Signals the end of the user commands. - Assigns an absolute value to a symbol specified in XREF directive in the program. - Indicates the beginning execution address of the load module being produced. - Defines segment attributes and the relocatable section numbers (0-15) to be included in the segment. - Defines the starting address at which a particular section(s) will be stored. - Directs all listings to the listing device. - Produces an immediate listing of the current load map. - Produces an immediate listing of all currently unresolved external references. - Produces an immediate listing of the table of externally defined symbols. - Specifies an object library to be searched if there are any unresolved references. • OPERATING ENVIRONMENT MATRIX68K microcomputers under UniPlus+ (UNIX System III). The ASM/LNK68200 software package is supplied in 2 forms: 1 . DOS-11 formatted, 9 track, 800BPI magnetic tape in compiled object form, ready to link and run on DEC PDP-11 computers under RSX-ll M and VAX computers under VMS in compatibility mode; 2. double-density, double-sided 51,4 inch floppy diskette in executable object form, ready to install on VME- Each package contains command files for automated installation aswell as complete installation instructions and reference manuals. Debugging can be completed by using Mostek's RADIUS Remote Development Station and the AIM-68200 in-circuit emulator. See the appropriate data sheet for more information. ORDERING INFORMATION DESIGNATOR DESCRIPTION PART NUMBER ASM-68200 MK68200 Structured Macro Cross Assembler includes LNK-68200 for use under RSX-11 M or VAX in compatibility mode. Includes manuals. MK71030C-33 ASM-68200 MK68200 Structured Macro Cross Assembler includes LNK68200 for use on VME-MATRIX68K/UniPlus+ microcomputer system. Includes manuals. MK71030C-56 ASM-68200 User's Guide. Manual only. 4420357 LNK-68200 User's Guide. Manual only. 4420397 MK68200 Principles of Operation. Manual only. 4420399 RADIUS RADIUS Remote Development Station Data Sheet 4420194 AIM-68200 MK68200 Application Interface Module Data Sheet 4420396 Matrix, RADIUS, and AIM are trademarks of Mostek Corporation. UniPlus+ is a trademark of Unisoft System Incorporated. UNIX is a trademark of Bell Laboratories and signifies software derived from Unix System III under license from AT&T. XI-52 m UNITED TECHNOLOGIES MOSTEK SYSTEMS TECHNOLOGY CRASM-70 3870 CROSS-ASSEMBLER FEATURES o Assembles standard 3870 and F8 source o Produces absolute load module in F8HEX format o Runs under M/aS-80 on any Mostek disk system system. The Mostek MATRIX-80/S0S disk development system can be used for stand-alone assembly and debug capability, with the AIM-7X plugged directly into the system. The assembler object module may also be downloaded from a M/aS-80-based system to a Mostek RADIUS development system containing an AIM-7X. o Produces complete assembly listing to disk or printer o Produces symbol reference table DESCRIPTION The Mostek 3870 Cross Assembler (CRASM-70) runs under the M/aS-80 operating system, and assembles standard 3870/F8 assembly language. The output is an absolute object file (load module) in F8HEX format. A conversion utility is provided to convert F8HEX files to Mostek Hex for use with the AIM-7X in-circuit-emulator CRASM-70 produces an assembly listing which can be directed to a disk file or directly to the M/aS-80 LST: list device (printer). The listing shows program address, machine code, and line number for each statement, along with each source program statement. Any errors which are found in the source program are indicated in the listing. A symbol reference table is printed at the end ofthe listing. Up to 500 symbols may be used in the source program. CRASM-70 is supplied on a standard 8-inch single-sided single-density CP1M-compatible diskette, precompiled, ready to run under M/aS-80. II M/OS-SO, RADIUS, and MATRIX are trademarks of Mostek Corporation CPIM is a trademark of Digital Reserach Corporation XI-53 ORDERING INFORMATION DESIGNATOR DESCRIPTION PART NUMBER CRASM-70 3870/F8 Cross Assembler, runs under M/OS-80, on 8" SSSD diskette, with manual MK71007C-80 CRASM-70 Documentation package for above MK71007D RADIUS Remote Development Station data sheet 4420194 AIM-7XE Application Interface Module data sheet 4420246 XI-54 IJ UNITED TECHNOLOGIES MOSTEK SYSTEMS TECHNOLOGY DEVELOPMENT SYSTEMS PRODUCTS ORDERING GUIDE RADIUS - Remote Development Station RADIUS is a hardwarelsoftware development station that connects to a host computer. When you order a RADIUS, you must specify the operating voltage characteristics. The host software must be ordered separately (as described in the next section). DESCRIPTION ORDER RADIUS for 60 Hz, 115 VAC Operation MK78213 RADIUS for 50 Hz, 230 VAC Operation MK78214 RADIUS HOST SOFTWARE RADIUS host software is provided on a variety of media depending on host environment. When you order please specify one of the following. DESCRIPTION ORDER MIOS Version - implemented for M/OS-80 and CPIM supplied on single-sided, single-density, 8-inch floppy diskette. MK78224-11 RSX Version - implemented for RSX-11 M V3.2 supplied on DEC DOS-11 format 9-track magnetic tape, 800 BPI. Host must have a FORTRAN IV (ANSI-66) compiler. MK78224-33 VMS Version - implemeted for VMS V2.3 supplied on DEC DOS-11 format 9-track magnetic tape, 800 BPI. Host must have a FORTRAN IV (ANSI-66) compiler. MK78224-34 Rehostable Version - supplied in source form. Host must have a FORTRAN IV (ANSI-66) compiler. Supplied on ASCII 9-track magnetic tape, 800 BPI, blocked in 80-character records. MK78224-45 MATRIX UNIX version-implemented for UNIX on the MATRIX 68K. Supplied on a double sided, double density 5 1,4 inch floppy diskette. MK78224-56 MATRIX is a stand-alone, floppy disk based development system. It is supplied with MIOS V3.01, the M80 assembler, and the L80 linker. When you order a MATRIX, you must specify the operating voltage characteristics: DESCRIPTION ORDER MATRIX for 60 Hz, 115 VAC operation MK78188 MATRIX for 50 Hz, 230 VAC operation MK78189 XI-55 • AIM-7XE (Application Interface Module for 387X) AIM-7XE is the in-circuit-emulator for the 387X family. It will function in both RADIUS and MATRIX. When AIM-7XE is ordered, a personality module must also be ordered. This personality module provides emulation for the 3870 or 3873 family. In addition, the AIM-7X software must be ordered separately (as described in next section). DESCRIPTION ORDER AIM-7XE - control board and history board for 387X families. MK79094 APM-70 - personality module for 3870 family MK79093 APM-73 - personality module for 3873 family MK79092 AIM-7X (Software for AIM 7XE) The following software configurations are available for use with AIM 7XE. Please specify one of the following when ordering. DESCRIPTION ORDER Unix Version - configured for use with the MATRIX 68K. Supplied on a double sided double density 5 % inch floppy diskette. MK78225-50 M/OS-80 Version - configured for use with M/OS-80 and CP1M host and RADIUS. Supplied on single-sided, single-density, 8-inch floppy diskette. MK78225-10 RSX and VMS Version - configured for use with RSX-11 M V3.2 and VMS V2.3 host and RADIUS. Supplied on DEC DOS-11 format 9-track magnetic tape, 800 SPI. MK78225-30 ASCII Version - configured for use with general host and RADIUS. Supplied on ASCII 9-track magnetic tape, 800 SPI. MK78225-40 M/OS-80 Version - configured for use with MATRIX. Supplied on single-sided, single-density, 8-inch floppy diskette. MK78225-11 AIM-Z80AEI AIM-Z80SE (Application Interface Modules for Z80) AIM-Z80AE andAIM-Z80SE are the in-circuit-emulatorsfortheZ80. Theywillfunction in both RADIUS and MATRIX. When either of the two is ordered, the AIM-Z80 software must be ordered separately (as described in the next section). DESCRIPTION ORDER AIM-Z80AE - In-circuit-emulator for 2.5 and 4 MHz Z80. Provides 32K emulation RAM MK78181-4 AIM-Z80SE - In-circuit-emulator for 2.5,4, and 6 MHz Z80. Provides 16K emulation RAM MK78204 XI-56 AIM-Z80 (Software for AIM-Z80AEI AIM-Z80BE) The following software configurations are available for use with AIM-Z80AE or AIM-Z80BE. Please specify one of the following when ordering. DESCRIPTION ORDER Unix Version - configured for use with the MATRIX 68K. Supplied on a double sided double density 5 % inch floppy diskette. MK78226·50 M/OS-80 Version - configured for use with M/OS-80 and CP1M host and RADIUS. Supplied on single-sided, single-density, 8-inch floppy diskette. MK78226-10 RSX and VMS Version - configured for use with RSX-11 M V3.2 and VMS V2.3 host and RADIUS. Supplied on DEC DOS-11 format 9-track Magnetic tape, 800 BPI. MK78226-30 ASCII Version - configured for use with general host and RADIUS. Supplied on ASCII 9-track magnetic tape, 800 BPI. MK78226-40 M/OS-80 Version - configured for use with MATRIX. Supplied on single-sided, single-density, 8-inch floppy diskette. MK78226-11 AIM-68000 (Application Interface Module for 68000) AIM-68000 is the in-circuit-emulator for the 68000. It will function in both RADIUS and MATRIX. When AIM-68000 is ordered, the AIM-68000 software must be ordered separately (as described in the next section). DESCRIPTION ORDER AIM-68000 - In-ciruit-emulator for up to 10 MHz 68000. Includes two (2) control boards and a buffer boxlcable assembly. MK78228 AIM-68000 (Software for AIM-68000) The following software configurations are available for use with AIM-68ooo. Please specify one of the following when ordering. DESCRIPTION ORDER RSX and VMS Version - configured for use with RSX-11 M V3.2 and VMS V2.3 host and RADIUS. Supplied on DEC DOS-11 format 9-track magnetic tape, 800 BPI. MK78232-30 ASCII Version - configured for use with general host and RADIUS. Supplied on ASCII 9-track magnetic tape, 800 BPI. MK78232-40 M/OS 80 Resident Version-configured for use with the MATRIX Development System. MK78232-11 M/OS 80.. Hosted Version-configured for down loading from MATRIX to RADIUS . MK78232-10 UNIX - Version - configured for use with the MATRIX 68K. MK78232-50 XI·57 • EVAL-70 EVAL-70 is a 3870 family evaluation system. It includes an in-circuit-emulation cable. I DESCRIPTION ORDER EVAL-70 MK79086 ASM/LNK 68000 ASM/LNK is the assembler and linker for the 68000. The following software configurations are available on ASM/LNK 68000. DESCRIPTION ORDER 68000 structured Macro Cross Assembler and linker for use on DEC PDP-11 systems running RSX-11 M or DEC VAX Systems running in compatibility mode under VMS. MK71020C-33 68000 structured Macro Cross Assembler and linker for use on MATRIX-68K with UNIX operating system. MK71020C-56 68000 Cross Assembler and linker for use on 8080/Z80 Systems using the M/OS-80 or CP1M Operating System for use with Mostek development system equipment. MK78238C-11 AIM-68200 (Application Interface Module For 68200) AIM-68200-ln-circuit-emulator for the 68200. It will function in both RADIUS and MATRIX. When AIM-68200 is ordered, the AIM-68200 software must be ordered separtely (as described in the next section). DESCRIPTION ORDER AIM-68200-ln-Circuit-emulator for up to a 6 MHz 68200. Includes two (2) control boards and a buffer box/cable assembly. MK78235 AIM-68200 (Software For AIM-68200) The following software configurations are available for use with AIM-68200. Please specify one of the following when ordering. DESCRIPTION ORDER RSX and VMS Version - configured for use with RSX-11 M V3.2 and VMS V2.3 host and RADIUS. Supplied on DEC DOS-11 format 9-track magnetic tape, 800 BPI. MK78234-30 ASCII Version - configured for use with general host and RADIUS. Supplied on ASClI9-track magnetic tape, 800 BPI. MK78234-40 M/OS 80 Resident Version - configured for use with the MATRIX Development System. MK78234-11 M/OS 80 Hosted Version ~ configured for down loading from MATRIX to RADIUS. MK78234-10 UNIX Version - configured for use with the MATRIX 68K. MK78234-50 XI-58 EPP-1 (EPROM Programmer) EPP-1 is a programmer for use with RADIUS. DESCRIPTION ORDER EPP-1 EPROM programmer MK78229-0 EPP-1 (SOFTWARE FOR EPP-1) DESCRIPTION ORDER PROM programmer utility for EPP-1 (Data 1/0) MK78236 ASM/LNK 68200 ASM/LNK 68200 is the assembler and linker for the 68200. The following software configurations are available on ASM/LNK 68200. DESCRIPTION ORDER 68200 structured Macro Cross Assembler and Linker for use on DEC PDP-11 systems running RSX-11 M or DEC VAX system running in compatibility mode under VMS. MK71030C-33 68200 Structured Macro Cross Assembler for use on MATRIX 68K with UNIX operating system. MK71030C-56 68200 Cross Assembler and Linker for use on 8080/Z80 systems using the M/OS-80 or CP/M operating system. MK71039C-11 CRASM-70 CRASM-70 is the cross assembler that runs under MO/S-80 operating svstem, and assembles standard 3870/F8 assembly language. DESCRIPTION ORDER Cross Assembler for 3870/F8 runs on MATRIX. MK71007C-80 XI-59 • XI-60 1984/1985 MICROELECTRONIC DATA BOOK l! UNITED TECHNOLOGIES MOSTEK TELECOMMUNICATION PRODUCTS INTEGRATED TONE DIALER MK5087(N/P/J) FEATURES PIN CONNECTIONS Figure 1 o Pin-for-pin compatible with MK5085 with improved performance o Direct telephone-line operation with no external power supply V+----.1 XMTR SWITCH""-- 2 o Auxiliary switching functions on chip o Low standby power o 15"-~~~?BW TONE COL 1----.3 14""'-ROW1 COL 2......----.4 13"-ROW2 COL 3----.5 12~ROW3 V-----.6 11"-ROW4 Minimum external parts count OSC IN----'7 o Uses inexpensive 3.579545 MHz television color-burst crystal to provide high-accuracy tones 16 ......----.TONE OUT OSCOUT4-- 8 10"""----'MUTE OUT 9..-COL4 o On-chip regulation of dual-and single-tone amplitudes o Uses low-cost calculator-type keyboard (Form A contact) or standard 2-of-8 keyboard sine wave and requires little or no filtering for low-distortion applications. The same operational amplifier that accomplishes the current-to-voltage transformation necessary for the D-to-A converter also mixes the low and high-group signals. Frequency stability of this type of tone generator is such that no frequency adjustment is needed to meet standard DTMF specifications. o Multiple key entry pin-selectable to either single tone or no tone DESCRIPTION The MK5087 is a monolithic integrated circuit fabricated using the complementary-symmetry MOS (CMOS) process. A member of the TONE 11* family of integrated tone dialers, the MK5087 uses an inexpensive crystal reference to provide eight different audio sinusoidal frequencies, which are mixed to provide tones suitable for Dual-Tone-MultiFrequency (DTMF) telephone dialing. Pin connections are shown in Figure 1 and a block diagram is shown in Figure 2. FUNCTIONAL DESCRIPTION V+, Pin 1 Pin 1 is the positive supply pin. The voltage on Pin 1 should be between 3.5 and 10.0 volts, measured relative to V-(Pin The MK5087 was designed specifically for integrated tonedialer applications that require the following: wide-supply operation with regulated output, auxiliary switching functions, single-contact keyboard inputs, and Single Tone Inhibit option. Keyboard entries to the TONE 11* family of integrated tone dialers cause the selection of the proper divide ratio to obtain the required two audio frequencies from the 3.579545 MHz reference oscillator. D-to-A conversion is accomplished on-chip by a conventional R-2R ladder network. The tone output is a stairstep approximation to a * Trademark of Mostek Corporation 6). XMTR SWITCH, Pin 2 Pin 2 is connected to the emitter of an on-chip bipolar transistor whose collector is connected to V+. With no keyboard input this transistor is turned on and pulls Pin 2 up to within V BE of the V+ supply. When a keyboard entry is sensed, this output goes open circuit(high impedance). The XMTR Switch output switches regardless of the state of the Single Tone Inhibit input. XII-1 II MK5087 BLOCK DIAGRAM Figure 2 v+ '--+__~__rR~R~~-.__~~V+ RR '0 OSC OUT .>O----t-.MUTE OUT SINE WAVE COUNTER D/A CONVERTER SINE WAVE COUNTER D/A CONVERTER V+ r---~ OSC IN TONE OUT V+ Rc 2 Rc INHIBIT Rc C, C2 C3 XMTR SWITCH 5 SINGLE TONE '--______________________......________+'''''C Rc v- C4 vKEYBOARD CONFIGURATIONS ROW-COL INPUTS, Figure 3 Pins 3, 4, 5, 9, 11, 12, 13, 14 1 t-----.. COL .... The MK5087 features inputs compatible with the standard 2-of-8 keyboard, the inexpensive single-contact (Form A) keyboard, and electronic input. Figure 3 shows how to connect to the two keyboard types and Figure 4 shows waveforms for electronic input. The inputs are static, i.e. there is no noise generation as occurs with scanned or dynamic inputs. ..------i.~ ROW CLASS A KEYBOARD c 1:__-==== ::: The internal structure of the MK5087 inputs is shown in Figure 5. RR and Rc pull in opposite directions and hold their associated input sensing circuit turned off. When one or more row or column inputs are tied together, however, the input sensing circuits sense the "% Level" and deliver a logic signal to the internal circuitry of the MK5087 and cause the proper tone or tones to be generated. 2-0F-8 KEYBOARD ELECTRONIC INPUT Figure 4 :~ ~~ .......... nL..___ ........... Ur---- When operating with a keyboard, normal operation is for dual-tone generation when any single button is pushed, and single-tone operation when one or more buttons in the same row or column is pushed. Activation of diagonal buttons will result in no tones being generated. COLUMNS When the inputs to the MK5087 are electronically activated, per Figure 4, input to a single row and column will result in that dual-tone digit's being generated. Input to a ROWS XII-2 INPUT CURRENT VS. INPUT VOLTAGE single column will result in that column tone being generated. Input to mUltiple columns will result in no tone being generated. Graph 1 800 Activation of a single row is not sensed by the internal circuitry of the MK5087. If a single-row tone is desired, two columns must be activated along with the desired row. 600 400 ROW AND COLUMN INPUTS INPUT CURRENT Figure 5 - JJ.A V+ 200 2 3 4 5 ROW INPUT 6 7 8 9 10 INPUT - VOLTS v- OUTPUT FREQUENCY DEVIATION Table 1 COLUMN INPUT ~tandard DTMF (Hz) f1 V-, Pin 6 697 % Deviation Tone Output From Standard Frequency Using 3.579545 MHz Crystal 701.3 +0.62 +0.19 LOW GROUP +0.61 f2 710 711.4 f3 852 857.2 ROW Pin 6 is the power supply return pin and it is the measurement reference for V+ (Pin 1). OSC IN, Pin 7; OSC OUT, Pin 8 f4 941 935.1 -0.63 f5 1209 1215.9 +0.57 f6 1336 1331.7 f7 1471 1471.9 -0.32 HIGH GROUF -0.35 f8 1633 1645.0 +0.73 COL The MK5087 contains an on-board inverter with sufficient loop-gain to provide oscillation when working with a lowcost television color-burst crystal. The inverter's input is Osc In (Pin 7) and output is Osc Out (Pin 8). The circuit is designed to work with a crystal cut to 3.579545 MHz to give the frequencies in Table 1. The oscillator is disabled whenever a keyboard input is not sensed. of the state of the Single Tone Inhibit input. Any crysta I freq uency deviation from 3.579545 M Hz wi II be reflected in the tone output frequency. Most crystals do not vary more than ± .02%. SINGLE TONE INHIBIT, Pin 15 MUTE OUT, Pin 10 The Mute output is a conventional CMOS gate that pulls to V-with no keyboard input and pullstothe V+ supply when a keyboard entry is sensed. This output is used to control auxiliary switching functions that are required to actuate upon keyboard input. The Mute output switches regardless XII-3 The Single Tone Inhibit input is used to inhibit the generation of other than dual tones. It has a pull-up to the V+ supply and, when left floating or tied to V+, single ordual tones may be generated as described in the paragraph under row-column inputs. When forced to the V- supply, any input situation that would normally result in a single tone will now result in no tone, with all other chip functions operating normally. • TONE OUT, Pin 16 The output pin is connected internally in the MK5087 to the emitter of annpn transistor whose collector is tied to V+. The input to this transistor is the on-chip operational amplifier which mixes the row and column tones together. TYPICAL DUAL-TONE WAVEFORM (ROW 1, COL. 1) Figure 8 The level of a dual-tone output is the sum of the levels of a single-row and a single-column output. This level is controlled by an on-chip reference which is not sensitive to variations in the supply voltage. ROW 2 TONE OUTPUT Figure 6 r-V 0 r-U r-T SPECTRAL ANALYSIS OF WAVEFORM IN FIG. 8 (Vert-10 dB/div., Horizontal-1 kHz/div.) Figure 9 TIME~ 44.7 /ls/div. COLUMN 4 TONE OUTPUT Figure 7 v 0 U T TIME-..19/ls/dlv. OUTPUT WAVEFORM The row and column output waveforms are shown in Figures 6 and 7. These waveforms are digitally-synthesized using on-chip D-to-A converters. Distortion measurement of these unfiltered waveforms will show a typical distortion of 9% or less. The on-chip operational amplifier of the MK5087 mixes the row and column tones to result in a dual-tone waveform. Spectral analysis of this waveform will show that typically all harmonic and intermodulation distortion components will be -30 dB when referenced to the strongest fundamental (column tone). A commonly quoted method of dual-tone distortion measurement is the comparison of total power in the unwanted components (i.e. intermodulation and harmonic components) with the total power in the two fundamentals. For the MK5087 dual-tone waveform, THD is --20 dB maximum. A simpler measurement may be made directly from the screen of a spectrum analyzer by relating any component to one ofthe fundamentals. The MK5087 dual-tone spectrum will show all individual harmonic and IMD components are typically at least -30 dB with respect to the column tone. Figures 8 and 9 show a typical dual-tone waveform and its spectral analysis. TYPICAL APPLICATION Figure 11 shows an application of the MK5087 in a standard telephone set that uses the standard 2500-type network. The tone levels and loop compensation that result from this application meet the requirements of the U.S. telephone systems. XU-4· ABSOLUTE MAXIMUM RATINGS* DC Supply Voltage V+ ............................................................................ 10.5 Volts Any Input Relative to V+ ...................................................................... " +0.30 Volts Any Input Relative to V- ......................................................................'... -0.30 Volts Operating Temperature ..............................•....................................... -30°C to +60°C Storage Temperature ........................................................................ -55°C to +85°C Maximum Circuit Power Dissipation .................................. 500 mW @ 25°C (see derating curve below) 'Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device, This is a stress rating only and functional operation ofthe device at these or any other condition above those indicated in the operational sections of this specification is not implied, Exposure to absolute maximum rating conditions for extended periods may affect device reliability, RECOMMENDED OPERATING CONDITIONS 60+---____________ POWER DISSIPATION DERATING CURVE ~ Figure 10 DC 20 O~----~------+_----_+------~----~ o 100 200 300 400 500 mW ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS (-30°C < - TA < - 60°C) SYM PARAMETER MIN TYP MAX UNITS NOTES V+ DC Operating Voltage 3.5 10.0 V 1 V 1l Input Voltage Low - "0" V- 30% ofV+ V 1, 11 V1H Input Voltage High - "1 " 70% ofV+ V+ V 1, 12 R1PS'fj Input Pull-up Resistance, STI 20 100 kO 3 TYP MAX UNITS NOTES 0.25 0.50 100 200 pA pA 2,7 2,7 1.0 5.0 2.0 15.0 mA mA 2,6,8,9 2,6,8,9 AC CHARACTERISTICS (-30°C::::; TA::::; 60°C; 3.0 V ::::; V+ ::::; 10.0 V) SYM PARAMETER ISSB Supply Current-Standby (Pin 6, V+ = 3.5 V) (Pin 6, V+ = 10.0 V) Iso 10HX 10LX 10HM 10lM MIN Supply Current-Operating (V+ = 3.5 V) (V+ = 10.0 V) Output Drive, XMTR Switch-No Entry (V+ = 3.5 V, V OHX = 2.5 V) (V+ = 10.0 V, V OHX = 8.0 V) -15 -40 mA mA -25 -100 Output Drive, XMTR Switch-Valid Entry (V+ = 10.0 V, Output =0.0 V) 0.1 10.0 pA Output Drive, MUTE - Valid Entry (V+ = 3.5 V, V OH = 3.0 V) (V+ = 10.0 V, V OH = 9.5 V) 0.5 1.0 2.0 4.0 mA mA Output Drive, MUTE - No Entry (V+ = 3.5 V, VOL = 0.5 V) (V+ = 10.0 V, VOL = 0.5 V) 0.5 1.0 2.0 4.0 mA mA Input Current Rows and Columns - SEE GRAPH 1 XII-5 II AC CHARACTERISTICS (Continued) SYM PARAMETER V NKD Tone Output-No Key Down t R1SE Tone Output Rise Time V OUT Tone Output Voltage Row Tone (R L = 1K, 620 .0, 330 D) Col Tone (R L = 1K, 620.0,330.0) PE HB Pre-Emphasis, High Band DIS Output Distortion MAX UNITS -80 dBm 3.0 5.0 ms 5,9 317 396 400 500 504 630 mVRMS mVRMS 1,3,6 1,3,6 1.0 2.0 3.0 dB -20 dB MIN NOTES: 1. All voltages referenced to V-. 2. All outputs unloaded. 3. TA = 25°C. 4. Any row plus any column at V+ ~ 4 volts. 5. Time from a valid keystroke with no bounce to allow wave to go from minimum to 90% of the final magnitude of either frequency. 6. True RMS Readings 7. Current Out Of Pin 6 No Key Depressed. TYP NOTES 4,10 8. Current Out Of Pin 6 One Key Depressed. 9. Crystal parameters RS::; 100 n, LM = 96 mH, CM = 0.02 pF, Ch = 5 pF, f = 3.579545 MHz, CL = 18 pF. 10. Output Distortion measured in terms of total out-of-band power relative to the sum of Rowand Column fundamental power. 11. Column inputs require a voltage low (0) of 10% of V+ (max). 12. RoW inputs require a voltage high (1) of 90% of V+ (min). TYPICAL APPLICATION IN 2500-TYPE TELEPHONE Figure 11 V+ '~---14-t ROW 1 aH'----~13::-l ROW 2 TONE 12 ROW 3 OUT 16 t-i----=-11::-t FiOW4 MK5087 L------.:-i COL 4 L..-_ _ _ _-:-\ COL 3 12011 L--------::-t COL 2 MUTE~--r---r--' 3.579545 MHz OUT 10 G 2N6660 300 K 1K NOTE: Transient protection circuitry not shown. XII·6 _ UNITED TECHNOLOGIES MOSTEK TELECOMMUNICATION PRODUCTS INTEGRATED TONE DIALER M KS089(N/P/J) FEATURES PIN CONNECTIONS o Minimum external parts count o High-accuracy tones Figure 1 V+~1 o Digital divider logic, resistive ladder network, and CMOS TONE DISABLE ~ 2 operational amplifier on single chip o o o COL1~3 Uses inexpensive 3.579545 MHz television color-burst crystal Multiple key entry pin selectable to either single tone or no tone 16~TONEOUT SINGLE TONE . . - INHIBIT 14...-ROW1 15 COL 2---+- 4 13~ROW2 COL3---+- 5 1.2~ROW3 v- ---+- 6 11...-ROW4 OSC IN ---+- 7 OSCOUT~ 8 10~ANYKEY DOWN 9"-COL4 Interfaces easily in electronic or J.LP dialing applications o Tone Disable inhibits tone generation without defeating the Any Key Down output high-group signals. Frequency stability of this type of tone generation is such that no frequency adjustment is needed to meet standard DTMF specifications. DESCRIPTION The MK5089 is a monolithic integrated circuit fabricated using the complementary-symmetry MOS (CMOS) process. A member of the TONE 11* family of integrated tone dialers, the MK5089 uses an inexpensive crystal reference to provide eight different audio sinusoidal frequencies which are mixed to provide tones suitable for Dual-Tone MultiFrequency (DTMF) telephone dialing. The MK5089 was designed specifically for integrated tone dialer applications that require the following: fixed supply operation, a negative-true keyboard input, Tone Disable input, stable output tone level, and an Any Key Down output that is open circuit when no keyboard buttons are pushed and pulls to the V- supply when a button is pushed. Keyboard entries to the TONE 11* family of integrated tone dialers cause the selection of the proper divide ratio to obtain the required two audio frequencies from the 3.579545 MHz reference oscillator. D-to-A conversion is accomplished on-chip by a conventional R-2R ladder network. The tone output is a stairstep approximation to a sine wave and requires little filtering for low-distortion applications. The same operational amplifier that accomplishes the current-to-voltage transformation necessary for the D-to-A converter also mixes the low- and *Trademark of Mostek Corporation XIJ-7 Pin connections are shown in Figure 1 and a block diagram is shown in Figure 2. FUNCTIONAL DESCRIPTION V+, Pin 1 Pin 1 is the positive supply pin. The voltage on Pin 1 sho.uld be between 3.0 and 10.0 volts, measured relative to V(Pin 6). TONE DISABLE, Pin 2 The Tone Disable input is used to defeat tone generation when the keyboard is used for other functions besides DTMF signaling. It hasa pull-uptotheV+ supply and, when tied to the V- supply, tones are inhibited. All other chip functions operate normally. ROW-COLUMN INPUTS, Pins 3,4,5,9,11,12,13,14 With Single Tone Inhibit at V+, connection of V- to a single column will cause the generation of that column tone. Connection of V- to more than one column will result in no II BLOCK DIAGRAM Figure 2 V+ R7R;"R;R; 14 13 12 11 11 RRI V+ RAI V- RRI RRI SINE WAVE .COUNTER IKEYBOARD LOGIC: OSC OUT OSC IN 8 +4 . ROW COUNTER f-+ DIA CONVERTER VKB~ J.112 V+ COLUMN / . COUNTER 7 IKEYBOARD LOGICi SINE WAVE 'COUNTER r-- DIA CONVERTER 10 ANY K t-- r-- VKB -~ V: DOWN 18 TONE r--. OUT ~ V- 2 r~, 16 l~cl ''0' c,- 4 6 C; C; V+ l' 9 C4 FUNCTIONAL DESCRIPTION (Continued) 2-0F-8 KEYBOARD tones being generated. The application of V- to only a row pin or pins has no effect on the circuit. There must always be at least one column connected to V- for row tones to be generated. If a single-row tone is desired, it may be generated bytying any two column pins and the desired row pin to V-. Dual tones will be generated if a single-row pin and a single-column pin are connected to V-. When Single Tone Inhibit is tied to V-, only dual tones will be generated. Figure 4 Each keyboard input is standard CMOS with a pull-up resistortothe V+ supply. These inputs may be controlled by a keyboard or electronic means. Open-collector TTL or standard CMOS (operated off same supply as the MK5089) may be used for electronic control. Refer to Figures 3 and 4. The switch contacts used in the keyboards may be void of precious metals, due to the CMOS network's ability to recognize resistance up to 1 kO as a valid key closure. V+ v- ____ V- -c:t :-::: ____ V-, Pin 6 Pin 6 is the power supply return pin and it is the measurement reference for V+ (Pin 1). OSC IN, Pin 7; OSC OUT, Pin 8 The MK5089 contains an on-board inverter with sufficient loop-gain to prqvide oscillation when working with a lowcost television color-burst crystal. The inverter's input is Osc In (Pin 7) and output is Osc Out (Pin 8). The circuit is designed to work with a crystal cutto3.579545 MHztogive the frequencies in Table 1. The oscillator is disabled whenever a keyboard input is not sensed. ELECTRONIC INPUT Figure 3 SINGL E TON"E INHIBI RCI 3 TONE --L-E DISAB RCI r---- COLUMNS U ::=U- ROWS Any crystal frequency deviation from 3.579545 MHz will be reflected in the tone output frequency. Most crystals do not vary more than ± .02%. XII-8 OUTPUT FREQUENCY DEVIATION TYPICALSINGLE-ROWLEVELVS.SUPPLYVOLTAGE Table 1 Figure 5 Standard DTMF (Hz) 11 f2 ROWf3 f4 Tone Output Frequency Using 3.579545 MHz Crystal 697 770 852 941 701.3 771.4 857.2 935.1 % Deviation From Standard 1.0 0.9 +0.62 +0.19 +0.61 -0.63 +1 (i) ~ a: 0.8 en I- ...J f5 Col f6 f7 f8 1209 1336 1477 1633 1215.9 1331.7 1471.9 1645.0 o C 0.7 +0.57 -0.32 High -0.35 Group +0.73 -1 -;::. 0 0.6 -2 ...J UJ > UJ UJ z 0.3 0.2 2.0 -4 > UJ ...J ...J UJ -6 0z I-7 -8 -9 -10 -11 I- The Any Key Down output is used for electronic control of receiver and/or transmitter switching and other desired functions. It switches to the V- supply when a keyboard button is pushed, and is open-circuited when not. The AKD output switches regardless of the Tone Disable and Single Tone Inhibit inputs. C -5 0.4 0 ;:) 0 -3 UJ 0.5 ...J ANY KEY DOWN, Pin 10 al ~ -;::. ;:) C e- 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 SUPPLY VOLTAGE (v+) (VOLTS) ROW 2 TONE OUTPUT SINGLE TONE INHIBIT, Pin 15 Figure 6 The Single Tone Inhibit input is used to inhibit the generation of otherthan dual tones. It has a pull down tothe V- supply and when floating or tied to V-, any input situation that would normally result in a single tone will now result in no tone, with all other chip functions operating normally. When forced to the V+ supply, single or dual tones may be generated as described in the paragraph under RowColumn Inputs. +-I~ t::q+-U +-} TIME--.44.7 jJ.s/div TONE OUT, Pin 16 COLUMN 4 TONE OUTPUT The tone output pin is connected internally in the MK5089 to the emitter of an npn transistor whose collector is tied to V+. The input to this transistor is the on-chip operational amplifier which mixes the row and column tones together and provides output level regulation. The output tone level of the MK5089 is a function of supply voltage. Figure 5 is a plot of the typical output level of a single-tone output vs. supply voltage. The level of a dualtone output is the sum of the levels of a single-row and a single-column output. Figure 7 II rr ~v f-O f-U f-T TIME-..19 jJ.s/ div The row and column output waveforms are shown in Figures 6 and 7. These waveforms are digitally-synthesized using on-chip D-to-A converters. Distortion measurement of these unfiltered waveforms will show a typical distortion of 7% or less. The on-chip operation amplifier of the MK5089 mixes the row and column tones to result in a dual-tone waveform. Spectral analysis of this waveform will show that typically XII·9 all harmonic and intermodulation distortion components will be -30 dB down when referenced to the strongest fundamental (column tone). A commonly-quoted method of dual-tone distortion measurement is the comparison of total power in the unwanted components (i.e. intermodulation and harmonic components) with the total power in the two fundamentals. For the MK5089 dual-tone waveform, THO is -20 dB maximum. A simpler measurement may be made directly from the screen of a spectrum analyzer by relating any component to one ofthe fundamentals. The MK5089 dual-tone spectrum will show all individual harmonic and IMO components are typically at least 30 dB down with respect to the column tone. SPECTRAL ANALYSIS OF WAVEFORM IN FIG. 8 (Vert-10 dB/div, Horizontal-1 kHz/div) Figure 9 .. 1, . ~ ~! ~ l I' ~"' \~iln~1\~, ~ ~II': l.. ~'..ljlll~ ~ fl.~· . IN~: Figures 8 and 9 show a typical dual-tone waveform and its spectral analysis. " :I \ i. TYPICAL DUAL-TONE WAVEFORM (ROW 1, COL. 1) I i ! • 'Ji. Figure 8 I !: . 11 , ., III . "'. ~ \1"\ \1II.!' _1. '.1.. I"I• '. . '. !1 . ' ..I " \.,. . . . '", a., II II' t I,!., V Ii i ~. '1 I f .............. '' " II . I I TONE LEVEL TEST CIRCUIT Figure 10 V+ 3.579545 MHz CRYSTAL 0 V+ 7 OSC TONE 16 IN OUT MK5089 8 OSC OUT 3 -COl1 4 14 COl2 VO UT Rl = 10 K -= ROW1 v- 6 NOTE: Keyboard connections shown are for Rowtone level test. Only Cc;T'i (Pin 3) should be connected to V- for Column tone level test. XII-10 ABSOLUTE MAXIMUM RATINGS* DC Supply Voltage V+ ............................................................................ 10.5 Volts Any Input Relative to V+ ...................................................................... " +0.30 Volts Any Input Relative to V- ......................................................................... -0.30 Volts Operating Temperature ...................................................................... -30 D C to +60 D C D Storage Temperature ........................................................................ -55 D C to +85 C D Maximum Circuit Power Dissipation .................................. 500 mW @ 25 C (see derating curve below) 'Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation ofthe device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. POWER DISSIPATION DERATING CURVE 60-+-----TA 40 (oC) 20 DERATE AT 9 mW/oC WHEN SOLDERED INTO PC BOARD. O~----~--~----~--~----~--o 200 300 400 500 100 mW ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS (-30D C :5 TA :5 60D C) MAX UNITS 3.0 10.0 V Input "0" V- 30% ofV+ V V IH Input "1 " 70% ofV+ V+ V RI Input Pull-Up Resistor 20 100 kO MAX UNITS NOTES -7 dBm 1,7 3 dB -20 dB 2,6 5.0 ms 3 SYM PARAMETER MIN V+ Supply Voltage V IL TYP NOTES AC CHARACTERISTICS (-30 D C :5 TA :5 60 D C; 3.0 V :5 V+ :5 10.0 V) SYM PARAMETER V OUT Tone Output (R LOAD TYP MIN = 10K) -10 PE HB Pre-Emphasis, High Band DIS Output Di.stortion t R1SE Rise Time IAKD Any Key Down Sink Current to V- IAKDO AKD Off-Leakage 2.0 J.l.A@5V Iso Supply Current-Operating 2.0 mA@3.5V 5 ISST Supply Current-Standby 200 J..LA@10.0V 4 V NKD Tone Output - No Key Down (R LOAD = 10 kO) -80 2.4 2.7 2.8 500 J.l.A@5V NOTES 4. 1. Single-tone, low-group. Any V+ between 3.4 and 3.6 V. OdBm = .775 V. 2. Any dual-tone. AnyV+ between 3.4 and 1O.OV. See Figure 10 and Figure 11 .. 5. One key depressed only. Outputs unloaded. 3. Time from a valid keystroke with no bounce to allow the waveform to go from 6. min. to 90% of the final magnitude of either frequency. Crystal parameters: RS:O; 100 0, LM = 96 mH, CM = 0.02 pF, Ch = 5 pF, f = 3.579545 MHz ± 0.02%, CL = 18 pF. 7. XII-11 dBm Stand-by condition is defined as no keys activated, iiiiilb1t = Logical O. To = Logical 1, Single Tone Output Distortion measured in terms of total out-of-band power relative to the sum of Rowand Column fundamental power. For 3.4 V:o; V+ :0; 10.0 V, Tone Output is typically [0.0855 (V+) ± 1 dB] mV rms . Refer to Figures 5 and 10. II TYPICAL APPLICATION electronic or J.LP dialing applications, as shown in Figure 11. The MK5089 row and column inputs must be pulled low for a valid key entry. The MK5089 has internal pull-up resistors for both the rows and columns. Therefore, the MK5089 keyboard inputs may be driven by CMOS, TTL, and TTL open-collector logic without the requirement for external pull-up resistors. Thus, the MK5089 can be easily used in v+ and V-on the M K5089 shou Id be typica Ily con nected to the supply used for the electronic drive circuitry. However, care must be taken to ensure that V+ does not exceed the specified 10 volt maximum. The logic levels present at the MK5089 inputs must meet the criteria specified under the Absolute Maximum Ratings and Electrical Characteristics. TYPICAL APPLICATION Figure 11 V+ R1-r-1~--------------­ R2~ R3----------~~~------­ R4-------------~r-L-C1~~-----------C2----------~~~------­ C3~ C4----------------~ NUMBER DIALED 1 6 8 D TONEOUT~4-- ~~tid ----Y+ Xl____________1.:.,.4-=-4ROW 1 ~~~--------------_1~3~ROW2 12 - - TONEt-1.;..;:6'---_~TONE Xl-----------~ROW 3 OUT OUT ~--~----------------11~ROW4 3 ~5089 X)------------~COL1 ~r_~----------------4~COL2 ~------------~5~COL3 2~f_~----------------~9~COL4 70SC AKD 10 IN 3.579545r:::::J MHz 8 OSC OUT v6 • Inverters are not needed if the driving signals R1 - C4 are inverted and can drive a 20 k!l load. NOTE: U1 and U2 are hex inverters (TIL - 7404, 74LS04; TIL open-collector - 7405. 74LS05; CMOS - 4049) tt ~ 50 ms and45 ms ~ tid~ 3 s to meet Bell Specifications PUB 47001. section 4.3 tt = tone duration time tid = interdigit time XII-12 ..... -------~ v- 10 K m UNITED TECHNOLOGIES MOSTEK TELECOMMUNICATION PRODUCTS MK5087/89 ELECTRONIC DRIVE The purpose of this application brief is to provide information as to the various means by which the MK5087 and MK5089 keyboard inputs may be electronically driven. pulled low for a valid key entry. Since the MK5087 has internal pull-up resistors on the rows and pull-down resistors on the columns, external pull-ups are only needed when driving the column inputs with TIL open-collector logic. The circuit diagram in Figure 1 shows the interface for electronically driving the MK5087. The MK5087 keyboard inputs can be driven by both CMOS and TIL logic. With the MK5087, the row inputs must be Figure 1 ,.........~..........< V+ V+ 4.7K (4x) R1 JI'-_ _ _ _ _ _ __ R2 R3 ----t"'L-----------~~~------­ C1 .J"!'--_ _ _ _ _ __ R4--------------~~ C2 r-11...-______ C3 C4 ----t"'L-r--"1.--- NUMBER DIALED 1 6 8 V+ 1~rl--+---~-+--+--14-1 R OW 1 1J11:l-.....-:;-----+---+--+---i~__t ROW 2 '1Y)-+---I_t-+-..;..13~R0W3 ~>-~____+-~r-t-+-~12~ROIvV4 .-----lE-----t 11 3 ~-;u:z~--~----+-~~~--~COL2 Z)__;-~~----~4~COL3 !~--~--~~--------~5~COL4 9 D °1~C 1K MUTE 10 3.579545 J.+tt ~ MK5087 1~--+-~r-+-"~COL4 TONEOUT~ ~ TONE TONE ~---e--o OUTPUT OUT 16 MHz ~tid 6 V- * Only needed when using TTL open-collector logic ** Inverters and buffers are not needed if the driving signals R1 - R4 are inverted and R1 - C4 can drive a 4.7 kO load. NOTE: U1 is a hex inverter (TTL - 7404, 74LS04; TTL open-collector - 7405, 74LS05; CMOS - 4049) U2 is a hex buffer (TTL open-collector - 7407. 74LS07, 7417, 74LS17; CMOS - 4050) tt ;::: 50 ms and 45 ms ;::: tid;::: 3 s to meet Bell Specifications PUB 47001, section 4.3 tt = tone duration time tid = interdigit time XII-13 II The MK5089 row and column inputs must be pulled low for a valid key entry. The MK5089 has internal pull-up resistors for both the rows and columns. Therefore, the MK5089 keyboard inputs may be driven by CMOS, TTL, and TTL open-collector logic without the requirement for external pull-up resistors. The interface for electronically driving the MK5089 is shown in Figure 2. Figure 2 v+ R1 ~ v+ ________________ ~------------1-4~RONV1 ---I"'L-- R2 13 ROW 2 TONE rt R3 r-L- R4 ~-~----------~ ROW 4 11 MK5089 J"I C1 rt C2 C3-I1.---C4 NUMBER DIALED 3~ 1~r-~---------------4~COL2 ~---F----~ 6 8 - 10K 9 COL4 D TONEOUT~ .j 5 COL 3 r-'I.....1 TONE nc.-----------1""'"12.~ OUT ...1-6---4...-....a OUTPUT 7 3.579545 j.tt ~ J+tid MHz °1~C OSC 8 OUT AKD 10 v6 v* Inverters are not needed if the driving signals R1 - C4 are inverted and can drive a 20 kfl load. NOTE: U1 and U2 are hex inverters (TIL - 7404, 74LS04; TIL open-collector - 7405, 74LS05; CMOS - 4049) tt ~ 50 ms and 45 ms ~ tid ~ 3 s to meet Bell Specifications PUB 47001, section 4.3 tt = tone duration time tid = interdigit time V+ andV- onthe MK5087 and MK5089 should be typically connected to the supply used for the electronic drive circuitry. However, care must be taken to ensure that V+ does not exceed the 10 volt maximum as specified in the MK5087 and MK5089 data sheets. The logic levels present at the MK5087 and MK5089 inputs must meet the criteria specified in the respective data sheets and repeated in Table 1. The high logic level must not exceed V+ and the low logic level must not be more negative than V-. LOGIC LEVEL REQUIREMENTS Table 1 MK5087 MK5089 Column High ?:..7 V+ ?:..7V+ Column Low :S.1 V+ :S.3V+ Row High ?:..9 V+ ?:..7 V+ Row Low :S.3V+ :S.3V+ XII-14 m UNITED TECHNOLOGIES MOSTEK TELECOMMUNICATION PRODUCTS INTEGRATED TONE DIALER) MK5380(N/P/J FEATURES o Low standby power o Minimum external parts count o o o PIN CONNECTIONS Figure 1 V+-.. 1 CHIP -.. DISABLE 2 Uses inexpensive 3.579545 MHz television color-burst crystal to provide high-accuracy tones Improved loop compensation 15 . - SINGLE TONE INHIBIT COL 1 - " 3 14 . - 'RO\iV'1 COL2-.. 4 13 . -R'Ow"2 COL 3 - " 5 12.-ROW3 Distortion lower than industry standards v-~6 OSCIN~7 o Low voltage operation - 2.5 volts 16 - . . TONE OUT OSCOUT~8 11'-ROW4 10 ~MUTEOUT 9.-COL4 o Uses low-cost calculator-type keyboard (Form A contact) or standard 2-of-8 keyboard o Auxiliary switching functions on chip o Multiple key entry pin-selectable to either single tone or no tone D-to-A conversion for synthesis of the tones is accomplished on chip by a sinusoidally tapped resistor tree. DESCRIPTION Pin connections are shown in Figure 1 and a block diagram of the MK5380 is shown in Figure 2. The MK5380 is a monolithic, integrated circuit fabricated using Mostek's Silicon Gate CMOS process. A member of the Tone 111* family of integrated tone dialers, the MK5380 uses an inexpensive crystal reference to provide eight different audio sinusoidal frequencies, which are mixed to provide tones suitable for Dual-Tone-Multi-Frequency (DTMF) telephone dialing. The MK5380 was designed specifically for integrated tonedialer applications that require the following: wide-supply operation with regulated output, scanned keyboard inputs, auxiliary switching functions, and a Chip Disable input. Keyboard entries to the MK5380 integrated tone dialer cause the selection of the proper divide ratio to obtain the required two audio frequencies from the 3.579545 MHz reference oscillator. FUNCTIONAL DESCRIPTION V+, Pin 1 Pin 1 is the positive supply pin. The voltage on Pin 1 should be between 2.5 and 10.0 volts, measured relative to V- (Pin 6). CHIP DISABLE, Pin 2 When the Chip Disable input is connected to the V- supply, tone generation will be inhibited, the keyboard inputs will go to a high impedance state, and the amplifiers and oscillator will be powered down. The Chip Disable input has a pull-up resistor to the V+ supply and when floating or tied to V+, the MK5380 will operate normally. *Trademark of Mostek Corporation XII-15 II MK5380 BLOCK DIAGRAM Figura 2 v+ 14 13 12 11 KEYBOARD SCAN CIRCUITRY TONE OUT ~15 TONE INHIBIT --+-~.----+---' Cii_--+-----+-+--+-2~ OI;~~LE KEYBOARD SCAN CIRCUITRY OD = Oscillator Disable CD = Chip Disable v- KE'VBOARD CONFIGURATION FUNCTIONAL DESCRIPTION (Continued) Figure 3 COL-ROW INPUTS, ~ns~4,5,9,11,1~13,14 cor . . t------4~ . --------I... Rffiiii CLASS A KEYBOARD L1:-----..~ : ~ 2-0F-8 KEYBOARD ELECTRONIC INPUT Figura 4 --..t_! 14-1" v_ td The internal structure of the MK5380 Rowand Column inputs is shown in Figure 5. These inputs are designed to sense a connection between Rowand Column, or an electronic input as shown in Figure 4. Table 1 is a functional truth table for these inputs. Note that at least one Rowand one Column input must be active to generate a valid output. When operating with a keyboard, normal operation is for dual-tone generation when any single button is pushed, and single-tone operation when more than one button in the same row or column is pushed. Activation of two or more diagonal buttons will result in no tones being generated. 0Hw 0E zZ The MK5380 features inputs compatible with the standard 2-of-8 keyboard, the inexpensive single-contact (Form A) keyboard, and electronic input. Figure 3 shows how to connect to the two keyboard types and Figure 4 shows waveforms for electronic input. E NOTE: td is minimum tone duration plus oscillator start up time (tRISE ) ROWS V-, Pin 6 Pin 6 is the power supply return pin and it is the measurement reference for V+ (Pin 1). XII·16 ROW AND COLUMN INPUTS Figure 5 FUNCTIONAL TRUTH TABLE Table 1 ACTIVE LOW INPUTS ROW COLUMN OUTPUT One One Dual Tone Two or More One Column Tone One Two or More Row Tone Two or More Two or More No Tone ::::0---0' r-~------~----~----------.Q STROBE (ROW) OR STROBE (COL) : NOTE: STI is floating. CD is floating. 'STATIC PROTECTION CIRCUITRY NOTE: Chip Disable is floating. When CD is tied to V-, Rowand Column inputs go to a high impedance state. OSC IN. Pin 7; OSC OUT. Pin 8 The MK5380 contains an on-board inverter with sufficient loop gain to provide oscillation when working with a lowcost television color-burst crystal. The inverter's input is Osc In (Pin 7) and output is Osc Out (Pin 8). The circuit is designed to work with a crystal cutto 3.579545 MHz to give the frequencies in Table 2. The oscillator is disabled whenever a keyboard input is not sensed. Any crystal freq uency deviation from 3.579545 MHz will be reflected in the tone output frequency. Most crystals do not vary more than ± .02%. OUTPUT FREQUENCY DEVIATION MHz Crystal 13 14 697 770 852 941 699.1 766.2 847.4 948.0 +0.31 -0.49 -0.54 +0.74 Low Group 15 COL 16 17 18 1209 1336 1477 1633 1215.9 1331.7 1471.9 1645.0 +0.57 -0.32 -0.35 +0.73 High Group 11 ROW1 2 3.579545 When forced to the V- supply, anytime two or more rows (or columns) are activated, no tone will result. The Tone output pin is connected internally in the MK5380 to the emitter of an npn transistor whose collector is tied to V+. The base of this transistor is the output of the on-chip operational amplifier which mixes the row and column tones together. % Deviation From Standard Standard DTMF (Hz) The Single Tone Inhibit input is used to inhibit the generation of other than dual tones. It has a pull-up to the V+ supply and, when floating, single or dual tones may be generated as described in the paragraph under Row-Column inputs. TONE OUT, Pin 16 Table 2 Tone Output Frequency Using SINGLE TONE INHIBIT. Pin 15 The level of a dual tone output is the sum of the levels of a single row and a single column output. This level is controlled by an on-chip reference which is not sensitive to variations in the supply Voltage. A typical single-tone sine wave output is shown in Figure 6. This waveform is synthesized using a resistor tree with sinusoidally weighted taps. MUTE OUT. Pin 10 The M ute output is a conventiona I CMOS inverter that pulls to V- with no keyboard input and pulls to the V+ supply when a keyboard entry is sensed. This output is used to control auxiliary switching functions that are required to actuate upon keyboard input. The Mute Output switches regardless ofthe state ofthe Single Tone Inhibit input. Mute output is not affected by keyboard inputs when CD is tied to V-. XII·17 • A simple measurement of distortion may be made directly from the screen of a spectrum analyzer by comparing any component to one of the fundamentals. SPECTRAL ANALYSIS OF WAVEFORM IN FIG. 7 (Vert-10 dB/div. Horizontal - 600 Hz/div.) Figure 8 TYPICAL SINE WAVE OUTPUT - SINGLE TONE Figure 6 1+ : \ ( \ . <> .. .. \V'" . 1 .-j .r\···r'· \ / .j .. .. ---\'"'''''' . \V' ... .~ " TONE LEVEL TEST CIRCUIT Figure 9 Figures 7 and 8 show a typical dual-tone waveform and its spectral analysis. 2 7 TYPICAL DUAL-TONE WAVEFORM (Row 1, Co11) Figure 7 3.579545 MHz CRYSTAL D '---+-~'-- 50Kohm break impedance specification required by the telephone company. In the Tone mode however, 01 is bypassed to allow the MK5380 to directly modulate the telephone line with the DTMF signal. TONE MODE OPERATION In the Tone mode, the Mode switch selects the RC oscillator as the frequency reference and connects the MK5175 Mode input to the positive supply, thus XII-23 • bypassing 01. In this mode, pin 16 (Pulse/13-key) of the MK5175 is pulled high placing the MK5175 in the 12-key Tone mode, and causing pulsing transistors 05 & 06 to always be turned on (thus keeping the speech network always connected to the line, as in a standard tone application). Diode 06 prevents current drain on the battery by the telephone line or the speech network. Diode 01 prevents charging of the battery and allows the tone dialer to modulate the line (else the battery will act as a large capacitor dampening the DTMF tones). It should be noted that clipping of the DTMF signal will occur if the minimum instantaneous modulated voltage level drops below the battery voltage minus the series diode drop (2.5 volts in this case). When off hook in the Tone mode, the MK5175 features a bidirectional keyboard scheme that will passively monitor key inputs while the MK5380 scans the keyboard and generates the corresponding tones. When the MK5175 senses a * or # key has been entered, it will disable the MK5380 (MK5175 DO, pin 10, will pull MK5380 CD, pin 2, low) before the tone can be generated. Thus the * and # keys can be used to control the MK5175 without their tones being generated. The * or # tones may be generated by entering them twice (consecutively), however they cannot be stored in memory for later redial. When on hook in the Tone mode, the MK5175 leaves the MK5380 enabled (CD high) so excess standby current is not drawn through the CD pull-up resistor. In order to avoid keyboard contention, the MK5175, when on hook, passively monitors the keyboard until the MK5380 completes one full keyboard scan cycle and then disables it (the MK5380 keyboard inputs go to a high impedance state when the chip is disabled) and continues scanning the keyboard until the key is released. When on hook, the MK5380 remains disabled only while a key is depressed, thus operating as efficiently as possible. It is very important to realize that the MK5175 will only operate with a tone dialer that has an active low keyboard scanning scheme, whose inputs will go to a high impedance state when the chip is disabled. To our knowledge, the MK5380 and MK5389 are the only tone dialers with these features. ALTERNATE CIRCUIT SUGGESTIONS replaced with a low leakage capacitor (1000 to 10,000ltF) and a series resistor Rs (5 to 10K). This capacitor would be charged directly from the line (through Rs) when off hook, and trickle charged (through a 10Mohm resistor to the postive side of the bridge) when on hook. In such an application it would be advantageous to do memory storage when off hook. Adding another switch labeled PROG/DIAL in series with HKS, pin 15, (PROG= HKS to V +, Dial = HKS to V -) would enable this function. Thus numbers could be programmed into memory while off hook, thereby eliminating the unwanted current drain of key entry operations while on hook. It is important to note that if a battery is not used, the telephone will eventually lose memory if disconnected from the phone line or if another phone on the same line remains off-hook for a prolonged period of time. The constant current regulator 01 may also be eliminated, but care should be taken to minimize the voltage transients on the dialers when pulsing and to guarantee supply current during break. Placing a 10.5V zener diode and a 68uF capacitor across the supply pins of the dialers should take care of this problem. With 01 removed, the anode of diode 06 should be connected to the collector of transistor 06 and a jumper should be put in place of Q1. CONCLUSIONS This application is quite suitable for users requiring rotary (Pulse) dialing to reach a long distance service such as MCI or SPRINT, and then switching to Tone mode to dial the long distance number into the MCI or SPRINT system. The application will also operate quite well as a standard Tone or Pulse 10-number repertory dialer. The circuit however, has a problem when dialing in the Tone mode and switching to the Pulse Mode without a hookswitch transition in between. This is due to the fact that during Tone mode manual dialing, the MK5175 passively monitors the keyboard and stores each digit into the LND (Last Number Dialed) buffer while the MK5380 generates the tones on the line. If the circuit is then switched to pulse mode (prior to a hookswitch transition), the MK5175 will outpulse the information just entered into its LND buffer. The battery and series diode 01 may be elimil)ated and XII-24 ~3: CO C UI "" Ii ~ ~ UI CA) CO o dz 06 1N914 !!! "U c: rm l> en R13 390K "U "U 15 C1 STi C3 C2 f~~o~ 3VI -=- D48~~Hz _14 Rl -13 R2 R3 12 -11 R4 5 7 STORE 8 7 13R2 6 . ~ 3.579545MHz ~ OSC (5 12 R3 Z ~ 11R4 0- r- 2N5550 05 SPEECH NETWORK OSC __ _M~E r - .--- ~ N 3 3·C1 -4 C2 4C2 -5 C3 5C3 ei" I • • 71°~C CJ1 R1 2500 MUTE 10 R4 51K 02~ 1000 RCVR 2N 5401 lN914(x2) 2CO R2 390K ~ • , RS 20K '~MOOE 03 '0 R12 10K 151HKS 1 l 02 1N914 R10 10K MUTE~ PULSE 16 R5 390K II XII-26 m UNITED TECHNOLOGIES MOSTEK TELECOMMUNICATION PRODUCTS INTEGRATED DIALER COMPARISONTONE II vs TONE III The purpose of this Application Brief is to define the major differences between Mostek's Tone 11* and Tone 111* series of integrated tone dialers. The Tone III series was developed as an improvement over Tone II. The minimum operating dc voltage of Tone III has been reduced and loop compensation of the tones generated has been improved. Distortion has also been reduced due to a scheme in which DTMF tones are synthesized using a sinusoidally tapped resistor tree. The Tone III family of integrated tone dialers is fabricated using Mostek's Silicon Gate CMOS process. Tone III devices use a scanned keyboard scheme with which various keyboard types or electronic input may be used. Tone III dialers also have a Chip Disable feature which causes tone generation to be inhibited, the keyboard inputs to go to a high-impedance state, and the amplifiers and oscillator to be powered down. The following is a comparison of the major differences between the MK5087 and MK5089 (Tone II), and the MK5380 (Tone III) and MK5389 (Tone III). DC OPERATING VOLTAGE o MK5087 - 3.5 to 10.0 V o o MK5089 - 3.0 to 10.0 V TONE OUTPUT o MK5089 - Low Group: [.0855 V DD ± 1 dB] V rms into 10 kO load High Group: 2.7 dB above low group o MK5389 - Low Group: [0.0778 V DD ± 1 dB] V rms High Group: 2.7 dB above low group The following are designed to deliver U.S. telephone system tone levels in a telephone. On a fixed supply the levels will be: o MK5087 - Low Group: 317-504 mV rms into 1 kO load High Group: 2.0 dB above low group o MK5380 - Low Group: 245 mV rms typically (see notes 1 and 2) High Group: 2.0 dB above low group KEYBOARD TYPE o MK5087 - Class A; 2-of-7 or 2-of-8 (K/B common floating) o MK5089 - 2-of-7 or 2-of-8 (K/B common tied to V-) o MK5380/5389 - Class A; 2-of-7 or 2-of-8 (K/B common floating or tied to V-) TYPICAL APPLICATIONS o MK5087 (Uses fixed supply or modulating supply in telephone) • Telephone tone-dialer applications o MK5089 (Uses fixed or regulated supply in telephone) • Electronic or ,uP-dialing applications • European telephone applications AUXILIARY FUNCTIONS o Pin 2 • MK5087 - Bipolar XMTR SW (no key open) • MK5089 - Tone Disable • MK5380/5389 - =C:-:hi~p-=D:-:-is-a-:-bl:-e MK5380/5389 - 2.5 to 10.0 V = 1; key input = o Pin 10 • MK5087/5380 - CMOS MUTE SW (no key = 0; key input = 1 ) • MK5089/5389-N-Chnl MUTE SW (AKD) (no key open; key input = 0) = o MK5380 (Uses fixed supply or modulating supply in telephone) • Telephone tone-dialer applications • Electronic or ,uP-dialing applications • Interfaces to MK5175/7 repertory dialers o MK5389 (Uses fixed or regulated supply in telephone) • European telephone applications • Electronic or ,uP-dialing applications • Interfaces to MK5175/7 repertory dialers *Trademark of Mostek Corporation XII-27 II NOTES: 1. TONEOUT (measured at Pin 16 in loop applications) = 155 mV rms (typical). RE=100n. 2. In loop applications, the low-group single-tone output amplitude is a function of RE and RL by the relationship: __V_o__ TONEOUT 0.2 + XII·28 where Vo is the tone output amplitude at the phone line and RL is the equivalent ac impedance in shunt with the tone generator (RL typically varies with loop current). RE is the resistor value from TONEOUT to V-. In a 2500-Type application RL will typically vary from 200 to 500 n. Thus, at the phone line, tone output levels will range from 200 to 400 mV rms , depending on loop current. I1 UNITED TELECOMMUNICATION PRODUCTS TECHNOLOGIES MOSTEK LOOP SIMULATOR The following is a simple circuit which can be used to simulate a telephone loop for most testing purposes. Potentiometer R2 may be varied to provide various loop currents simulating different loop lengths. Normal loop currents range between 20 and 80 mA. Resistor R1 is used to limit the loop current to a maximum of approximately 120 mA (Tip and Ring short-circuited). An ammeter, I, is used to measure the loop current and capacitor C1 and resistor R3 are used to simulate the 600 0 impedance of the telephone line. Inductor L provides a high impedance in series with the power supply so that the impedance across Tip and Ring is effectively 600 O. ~--"'---------OTIP II + v ~------------------------~~-----------ORING v = 48 V (power supply or battery) = Ammeter (100 mA full scale) R1 2500 (5 Watts) C1 = 500 p.F, -10%, +50%, (50 V) R2 2 kG (2 Watts) L ;::: 10 H up to 150 mA dc (RL = 150 0) R3 600 0 ±1 % (% Watt) XII-29 • XII-30 1984/1985 MICROELECTRONIC DATA BOOK fj UNITED TECHNOLOGIES MOSTEK TELECOMMUNICATION PRODUCTS INTEGRATED PULSE DIALER WITH REDIAL MK50981 (N)-05 FEATURES o PIN CONNECTIONS Direct telephone-line operation o CMOS technology is used for low-voltage, low-power operation o o _ V+ Uses either a standard 2-of-7 matrix keyboard with pos. true common or the inexpensive Form A-type keyboard Ceramic resonator used as frequency reference for accuracy PULSEOUTPUT 2 ,ON-HOOK COL 1 3 ROW1 COL2 4 COL3 5 V- 6 OSCIN 7 ROW2 MK50981 o Make/Break ratio pin-selectable o Redial with either a * or # input DESCRIPTION 8 The MK50981 is a monolithic CMOS integrated circuit, which converts keyboard inputs into pulse signal outputs, Simulating a rotary telephone dial. It is designed to operate directly from the telephone line and can be interfaced properly to meet telephone specifications in systems utilizing loop-disconnect signaling. Two outputs, one to pulse the telephone line and one to mute the receiver, are provided to implement the pulse dialer function. Timing is accomplished by using a ceramic resonator as the frequency reference for the on-chip oscillator. The MK50981 is in either the on-hook or off-hook mode, as determined by the input to the pin designated "OnHook/Test." In order to accept any key inputs, the MK50981 mustbe in the off-hook state. Upon sensing a key input, the normally static oscillator is enabled, and the row and column inputs are alternately strobed to verify that the keyboard input is valid. The decoded input is then entered into an on-chip memory. The memory stores up to 17 digits and allows keystrokes to be entered at rates comparable to tone dialing telephones. Entering the first digit (except * or #) clears the memory buffer and starts the outpulsing sequence. As additional digits are entered, they are stored in the memory and outpulsed in turn. The memory has a FIFO (first-in-first-out) type architecture, and more than 17 digits may be dialed in any number sequence. The limitation is that there can never be more than 17 digits remaining to be outpulsed. ROW3 ROW4 11 - 9 MUTE OUTPUT MAKE/BREAK SELECT The MK50981 also features the redial function. Any 17digit number sequence may be redia led with a * or # key input, providing that the circuit enters the on-hook mode for a finite time. Functions of the individual pins are described below. V+, Pin 1 This is the positive supply input to the part; it is measured relative to V- (Pin 6). The voltage on this pin must b,~_ regulated to less than 6 volts, using either the on-chip reference circuitry or an external form of regulation. The V REF output provides a negative reference voltage relative to the V+ supply. Its magnitude is a function of the internal parameters, which define the minimum operating voltage of each part. In a typical application, the V REF pin is simply tied to V- (Pin 6). The internal circuit, with its associated I-V characteristic, is shown in Figure 1 . XIII-1 • ABSOLUTE MAXIMUM RATINGS* DC Supply Voltage, V+ ............................................................................ 6.2 Volts Operating Temperature ................................. , ..................................... -30°C to 60°C Storage Temperature ........................................................................ -55°C to +85°C Maximum Power Dissipation 25°C .................................................................. 500mW Maximum Voltage on any Pin ....................................................... (V+) + 0.3; (V-) -0.3 Volts 'Stresses above these listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation ofthe device at these, or at any other condition above those indicated in the operational sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS AT 25°C SYM PARAMETER MIN TYP MAX UNITS V+ DC Operating Voltage 2.5 4 6.0 V IMR Memory Retention Current 0.7 pA 1 lop DC Operating Current 100 pA 2 V REF Magnitude of (V+ - V REF ) ISUPPLY = 150pA 2.5 V Mute Sink Current: V+.= 2.5V, Va = 0.5V 2.0 mA Pulse Sink Current: V+ = 2.5V, Va = 0.5V 4.0 mA 1M Ip NOTES NOTES Typical values are to be used as a design aid and are not subject to production testing. 1. Current necessary for memory to be maintained. All outputs unloaded. On-Hook mode. 2. Current required for proper circuit function. Off-Hook Mode. Valid key input, VREF tied to V-. XIII-2 AC CHARACTERISTICS SYM PARAMETER fosc Oscillator Frequency (antiresonant mode) PR Pulse Rate t8 Break Time: Pin 9 tied to V+/ tied to V- t lDP MIN MAX UNITS NOTES 480 kHz 1 10.0 pps 61.0/67.0 ms 800 ms TYP Interdig ita I Pause NOTES "Typical" values are exact values with a nominal 480 kHz frequency reference (except for oscillator start-up time). KEYBOARD INPUTS, Pins 3,4, 5, 11, 12, 13, 14 Tbe MK50981 incorporate.s an innovative keyboard scheme that allows use of either the standard 2-of-7 keyboard with positive common or the inexpensive singlecontact (Form A) keyboard, as shown in Figure 2. 1. Ceramic resonator should have the following equivalent values: R < 200. RA ~ 70kO. Co :5 500pF. TYPICAL I-V CHARACTERISTICS Figure 1 7.0 V+ (PIN 1) 6.0 A valid key entry is defined by either a single row being connected to a single column, or V+ being simultaneously presented to both a single row and column. 5.0 IREF mA 4.0 When in the On-Hook mode, the row and column inputs are held high, and no keyboard inputs are accepted. When Off Hook, the keyboard is completely static, until the initial valid key input is sensed. The oscillator is then enabled, and the row and columns are alternately scanned (pulled high, then low) to verify that the input is valid. The input must remain valid continuously for 10ms of debounce time to be accepted. 3.0 2.0 (PIN 2) 1.0 V-, Pin 6 2 V+ - V REF This pin is the negative supply pin input. 3 4 5 VOLTS OSCILLATOR IN, OUT, Pin 7,8 The MK50981 contains an on-chip inverter with sufficient gain to provide oscillation when working with a low-cost 480kHz ceramic resonator (anti-resonant mode). In addition to the resonator, two external capacitors are required. Suggested equivalent values for the resonator are given in the timing specification section. These values will insure proper oscillator operation in the specified voltage range. The MK50981 may be driven externally with a 480kHz signal on Pin 7. MAKE/BREAK SELECT, Pin 9 The Make/Break ratio may be selected by connecting the pin to either the V+ or V- supply. Table 1 indicates the two popular ratios from which the user can choose. XIII-3 II the last digit, the oscillator is disabled and the circuit stands by for additional inputs. KEYBOARD CONFIGURATION Figure 2 SINGLE-CONTACT APPLICATION 1 COL-----~ Switching the MK50981 to On-Hook while it is outpulsing causes the remaining digits to be outpulsed at 100 x the normal rate (M/B ratio is then 50/50). This feature provides a means of rapidly testing the device and is also an efficient method by which the circuitry is reset. When the outpulsing in this mode, which can take up to 300ms, is completed, the circuit is deactivated and will require only the current necessary to sustain the memory and Power-Up-Clear detect circuitry (refer to the electrical specifications). -----ROW FORM A KEYBOARD C i.""-----t COL .... ------ROW 2-0F-7 KEYBOARD Upon returning Off-Hook, if the first key entry is either * or #, the number sequence stored on-chip will be outpulsed. Any other valid key entries will clear the memory and outpulse the new number sequence. VOLTAGE - FED APPLICATION v+-ci- COL -----ROW MAKE/BREAK RATIO SELECTION Table 1 ELECTRONIC INPUT ~: 1-1 - - - - - --h.'. ____ ~:- Input To Make/Break Pin tKD - -- - --nl----- COLUMNS V+ (Pin 1) V- (Pin 6) Pulse Output Make Break 39% 61% 33% 67% MUTE OUTPUT, Pin 10 ROWS The Mute Output consists of an open-drain, N-channel transistor. It provides the logic necessary to mute the receiver, while the telephone line is being pulsed. ON-HOOK/TEST, Pin 15 The "Test" or "On-Hook" input of the MK50981 has a 1OOkD. pull-up to the positive supply. A V+ input or allowing the pin to float sets the circuit in its On-Hook or test mode, while a V- input sets it in the Off-Hook or Normal Mode. When Off-Hook, the MK50981 will accept key inputs and outpulse the digits in normal fashion. Upon completion of PULSE OUTPUT, Pin 16 The Pulse output is an open-drain, N-channel transistor. This output provides the logic necessary to pulse the telephone line with the correct Make/Break, pulse rate, and interdigital pause timings. XIII-4 I'J UNITED TELECOMMUNICATION PRODUCTS TECHNOLOGIES MOSTEK INTEGRATED PULSE DIALER WITH REDIAL MK50982(N) FEATURES PIN CONNECTIONS o Direct telephone-line operation o CMOS technology is used for low-voltage, low-power operation V+ - - . o Uses standard 2-of-7 matrix with pas. true common or the inexpensive Form A-type keyboard V REF 4 - o Ceramic resonator used as frequency reference for guaranteed accuracy o Make/Break ratio pin-selectable o Redial with either 1 2 154-0N-HOOK/TEST COL 1 - - ' 3 14.-ROW1 COl2 - - . 4 13.-ROW2 COL 3 - - . 5 12.-ROW3 v- --. 6 * or # 1 6 ~ PULSE OUTPUT 114-ROW4 OSCIN - - . 7 10 --.MUTE OUTPUT OSCOUT4- 8 9 . - ~~~~BREAK o Provision for rapid testing o On-chip voltage regulator o Power-Up-Clear circuitry DESCRIPTION The MK50982 is a monolithic CMOS integrated circuit which converts keyboard inputs into pulse signal outputs simulating a rotary telephone dial. It is designed to operate directly from the telephone line and can be interfaced properly to meet telephone specifications in systems utilizing loop-disconnect signalling. Two outputs, one to pulse the telephone line and one to mute the receiver, are provided to implement the pulse dialer function. Accurate timing is accomplished by using a ceramic resonator as the frequency reference for the on-chip oscillator. The MK50982 is in either the on-hook or off-hook mode as determined by the input to the pin deSignated, "OnHook/Test." In order to accept any key inputs, the MK50982 must be in the off-hook state. Refer to Figure 1 for a block diagram. Upon sensing a key input, the normally static oscillator is enabled and the row and column inputs are alternately strobed to verify that the keyboard input is valid. The decoded input is then entered into an on-chip memory. The memory will store up to 17 digits and allows keystrokes to be entered at rates comparable to tone dialing telephones. Entering the first digit (except* or #) clears the memory buffer and starts the outpulsing sequence. As additional digits are entered, they are stored in the memory and outpulsed in turn. The memory has FIFO-(first-in-first-out) type architecture and more than 17 digits may be dialed in any number sequence. The limitation is that there can never be more than 17 digits remaining to be outpulsed. The MK50982 also features the redial function. Any 17-digit number sequence may be redialed with an* or # key input, providing that the circuit enters the on-hook mode for a finite time, tOH (refer to discussion on the On-Hook/Test Pin). An on-chip "Power-Up-Clear" circuit insures reliable operation of the MK50982. If the supply to the circuit should become insufficient to retain data in the memory (see electrical specifications), a "Power-Up-Clear" will occur upon regaining a proper supply level. This function will prevent the "Redial" or spontaneous outpulsing of incorrect data. A new number sequence may be entered in normal fashion. FUNCTIONAL DESCRIPTION V+, Pin 1 This is the positive supply input to the part and is measured relative to V- (pin 6). The voltage on this pin must be regulated to less than 6 volts using either the on-chip reference circuitry or an external form of regulation. XIII-5 II V-, Pin 6 BLOCK DIAGRAM Figure 1 v+ v- This IS the negative supply pin to which VREF is normally tied (see VREF paragraph). KEYBOARD INPUTS, Pins 3,4,5, 11, 12, 13, 14 The MK50982 incorporates an innovative keyboard scheme that allows either the standard 2-of-7 keyboard with positive common or the inexpensive single-contact (Form A) keyboard to be used, as shown in Figure 3. A valid key entry is defined by either a single row being connected to a single column or V+ being simultaneously presented to both a single row and column. OSC. MAKE/BREAK When in the On-Hook mode, the row and column inputs are held high and no keyboard inputs are accepted, thus preventing any accidental key contacts from causing excessive current flow. ON-HOOK The VREF output provides a negative reference voltage relative to the V+ supply. Its magnitude is a function of the internal parameters which define the minimum operating voltage of each part. In a typical application, as shown in Figure 5, the VREF pin is simply tied to V-(Pin 6). The internal circuit with its associated I-V characteristic is shown in Figure 2. When Off-Hook, the keyboard is completely static until the initial valid key input is sensed. The oscillator is then enabled and the row and columns are alternately scanned (pulled high, then low) to verify the input is valid. The input must remain valid continuously for 1Oms of debounce time to be accepted. KEYBOARD CONFIGURATION Figure 3 TYPICAL I-V CHARACTERISTICS SINGLE CONTACT APPLICATION Figure 2 ~ COL .. ROW II FORM A KEYBOARD V+ 7.0 c±: (PIN 1) 6.0 COL ROW 2-0F-7 KEYBOARD 6.0 IREF mA VOL TAGE - FED APPLICATION 4.0 3.0 2.0 :±: f v+ .. COL ROW 2-0F-7 KEYBOARD (PIN 2) ELECTRONIC INPUT I-----..J t KD 1.0 V+ - V REF ~+ - - - - - - - nl------COLUMNS ~+ - - - - - - VOLTS X111-6 - n'------ROWS Upon returning Off-Hook, if the first key entry is either* or #, the number sequence stored on-chip will be outpulsed. Any other valid entries will clear the memory and outpulse the new number sequence. OSCILLATOR IN, OUT, Pins 7,8 The MK50982 contains an on-chip inverter with sufficient gain to provide oscillation when used with a low-cost 480kHz ceram ic resonator (a nti -resonant mode). In addition to the resonator, two external capacitors are required. Suggested equivalent values for the resonator are given in the timing specification section. These values will insure proper oscillator operation in the specified voltage range. The MK50982 may be driven externally with a 480kHz signal on Pin 7. PULSE OUTPUT, Pin 16 The Pulse output is an open-drain N-Channel transistor designed to drive an external bipolar transistor. These transistors would normally be used to pulse the telephone line by controlling the loop current through the network. The timing characteristics of the Pulse output are shown in Figure 6. MAKE/BREAK SELECT, Pin 9 The Make/Break ratio may be selected by connecting the pin to either the V+ or V- supply. Table 1 indicates the two popular ratios from which the user can choose. TEST CIRCUIT A test circuit is shown in Figure 4. This circuit can be used to demonstrate the basic operation of the MK50982. MAKE/BREAK RATIO SELECTION Table 1 TYPICAL APPLICATION Input to Make/ Break Pin The schematic diagram in Figure 5 shows one method which can be used to interface the pulse dialer with the telephone line. In the approach shown, the pulse dialer circuitry is in series with the speech network. V+ (Pin 1) V- (Pin 6) Pulse Output MAKE 39% 33% BREAK 61% 67% A current source of some type is desired to present a high impedance to the telephone line while guaranteeing sufficient current to power the MK50982 (?: 150 /-LA). The current source shown is constructed with two components, 02 and R1. The current is reg u lated by the negative feedback provided by R1 to the gate of 02. Several other implementations can be considered, such as a constant current diode, or a configuration using bipolar transistors. MUTE OUTPUT, Pin 10 The Mute output consists of an open-drain N-channel transistor. It provides the logic necessary to mute the receiver while the telephone line is being pulsed. A typical method of interfacing this output is shown in the application diagram in Figure 5. Figure 6 shows the timing characteristics of the Mute output. ON-HOOK/TEST, Pin 15 The "Test" or "On-Hook" input of the MK50982 has a 100kO pull-up to the positive supply. A V+ input or allowing the pin to float sets the circuit in its On-Hook or test mode, while a V- input sets it in the Off-Hook or Normal Mode. Any digits to be tested in the "OnHook/Test" mode must be entered while "Off-Hook." When Off-Hook, the MK50982 will accept key inputs and outpulse the digits in normal fashion. Upon completion of the last digit, the oscillator is disabled and the circuit stands by for additional inputs. Switching the MK50982 to On-Hook while it is outpulsing causes the remaining digits to be outpulsed at 100 x the normal rate (M/B ratio is then 50/50). This feature provides a means of rapidly testing the device and is also an efficient method by which the circuitry is reset. When the outpulsing in this mode, which can take up to 300ms, is completed, the circuit is deactivated and will require only the current necessary to sustain the memory and Power-Up-Clear detect circuitry (refer to the electrica I specifications). The purpose of transistor 01 is to take the place of an additional hookswitch contact. When 51 closes, 01 is turned on and On-Hook(pin 15) is pulled to V-. This sets the MK50982 in the normal mode, ready to accept key inputs. When going On-Hook, 51 is opened, causing 01 to be turned off. An on-chip resistor pulls pin 15 to V+ and the current source is disabled. The purpose of 01 is to limit any reverse current flow through the current source. A large-value resistor, R3, allows a small amount of current to maintain the memory on MK50982. To return Off-Hook, S1 is closed, causing 01 to be turned on thus tying the On-Hook pin to V-. The Pulse and Mute outputs drive external transistors to perform the outpulsing function. The receiver is connected through transistor 06 to the speech network. Mute causes the transistor to be held on until outpulsing begins. When Mute switches low, the receiver is removed from the speech network. The pops caused by breaking the line are then isolated from the receiver. The Pulse output drives transistors 03 and 05 to make and break the line until the digit has been completely outpulsed. Mute then switches high, returning the receiver to the speech network. X111-7 II TEST CIRCUIT Figure 4 POWER SUPPLY \J / -2 FROM KEY80ARD --!. {~ --r 6 MK60982 HO: *100pF::: r- rl!--~} ~ - OFFHOOK 30kO ~ FROM KEYBOARD 11 480kHz CERAMIC 7 RESONATOR j 16 16kO 16 1 L.......- 10 8 9 67%BREA~ 81% BREAK 0--1OOpF TYPICAL APPLICATION Figure 5 C V+ + 1 MIB 15 ON-HOOK Q1 V- t -_ _ _~~......._I2 V REF 3 1 4 C MK60982 C2 C3 2 3 14 R1 13 R2 4 5 6 7 8 9 12 R3 PUISE 16 TYPICAL "500" TYPE SPEECH NETWORK 10 MUTE 1---+----+----; Q 4 11 * 0 # R4 FORM A KEYBOARD OSCIN C2 01. 3. 4 = 2N5550 05. 6 = 2N5401 02 = 2N3822 OSC OUT C3 01 = 1N914 C1 = 20/lF (low leakage) C2.3 = 100pF ± 20% R1 = 8k!1 R2 = 500k!1 R3 = 22M!1 XIII·8 R4.5 = 390k!1 R6.9 = 100k!1 R7.8 = 3k!1 ABSOLUTE MAXIMUM RATINGS* DC Supply Voltage, V+ .......................................................................... 6.2 Volts Operating Temperature ................................................................... -30°C to +60°C Storage Temperature ..... " ........................... , . . .. . . .. . . . . . . . . . . .. . . . . . . .. .. . . . -55°C to +85°C Maximum Power Dissipation (25°C) ........................... " .................................. 500mW Maximum Voltage on any Pin ............. c • • • • • • • • • • • • • • • • • • • • • • • • • • , ••••••••••• (V+) +0.3; (V-) -0.3 Volts • Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating ()nly and functional operation of the device at these or any other <::ondltlon above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (-30°C:::; TA:::; 60°C) DC CHARACTERISTICS SYM PARAMETER: SPECIFIC CONDITIONS MIN V+ DC Supply Voltage 2.5 IMR Memory Retention Current: Note 1 lop DC Operating Current: Note 2 V REF Magnitude of (V+ - VREF): ISUPPLY 1M Mute Sink Current: V+ = 2.5, Ip Pulse Sink Current: V+ = 2.5V, iLKG Mute and Pulse Leakage: V+ == 6.0V, VA == 6.0V RKI TYP* MAX UNITS 6.0 V 2.5 /-LA 100 150 /-LA 3.5 V 0.7 = 150 /-LA 1.5 2.5 = 0.5V 0.5 2.0 mA 1.0 4.0 mA Va Vo = 0.5V 0.001 1.0 p.A Keyboard Contact Resistance 1.0 k!l CK1 Keyboard Capacitance 30 pF KIL "0" Logic Level V- 20% of V+ V KIH "1" Logic Level 80% of V+ V+ V KRu Keyboard Pull-Up Resistance: Note 3 KRo ROH 4.0 k!l Keyboard Pull-Down Resistance: Note 3 100 k!l On-Hook Pull-Up Resistance 100 kn NOTES 'TYPlcal values are to be used as a design aid and are not subject to production testing 1. Current necessary for memory to be maintained. All outputs unloaded.OnHook mode 2. Current required for proper circuit function. Off- Hook mode:. Valid Key Input, V RE ' tied to VKeyboard to be scanned at 500Hz when oscillator enabled. Rowand Column to alternately pull high and low AC CHARACTERISTICS* (The timing Relationships are shown in Figure 6) MIN TYP MAX UNITS SYM PARAMETER: SPECIFIC CONDITIONS fosc Oscillator Frequency (antiresonant mode): Note 1 tOB Keyboard Debounce Time tKO Time for Valid Key Entry tos Oscillator Start-Up Time 6,0 ms PR Pulse Rate 10,0 pps tB Break Time: Pin 9 Tied to V+/Tied to V- tlDP Interdigital Pause 480 kHz 10 ms 40 ms 61.0/67.0 800 ms ms NOTES: "Typical values are exact with a nominal 480 kHz frequence reference (except for oscillator start-up time). Ceramic resonator should have the following equivalent values R <20n. RA 2: 70k Co ~ 500pF, XIII·9 n. II TIMING CHARACTERISTICS Figure 6 ~ J;I....___________________ KEY INPUT ~ =+I ~ tos DIGIT 4 I ~g~~MN ~------~III~---------------~ ROWSCAN ON-HOOK INPUT ~I'~-------4Ju~1 ---------.-------=t.nJ1JL. ! ,----- ! ! -+I 1--- lOB MUTEOUTPUT PULSE OUTPUT OSCILLATORIN ~DIGIT2I TI II __ 1 I I DIGIT4 I I I I mnru 1 Ii II I DI~ ~! LJ1Jr-----.......,lSU1JlJ i:f";;:."~uNI Osc.Ol"IIIIII~O''"''.'' OFF.(NORMAL) HOOK MODE ~ ON· TESTHOOK MODE L--REOIAL MODE I11111 100m I XIII-10 I I I l.POp Illi 800 ms:j UNITED TECHNOLOGIES MOSTEK TELECOMMUNICATION PRODUCTS INTEGRATED PULSE DIALER WITH REDIAL MK50991(N) " FEATURES PIN CONNECTIONS o Direct telephone-line operation o CMOS technology is used for low-voltage, low-power operation o Uses either a standard 2-of-7 matrix keyboard or the inexpensive Form A-type keyboard VREF.-2 17'--~~S~OOK/ COL 1--'3 16""'--ROW 1 Inexpensive RC oscillator used as frequency reference COL 2--'4 1S.....--ROW 2 COL3--.S 14""'--ROW3 V----.S 13.--"RffiiV"4 RC1---'7 12 .-.MUTE OUTPUT RC2...-S 11.....--M/B SELECT RC3.-g 104--20/10 PPS SELECT o V+--'1 o Redial with either a o Make/Break ratio and pulse rate are pin-selectable * or # o Provision for rapid testing o On-chip voltage regulator o Power-up-clear circuitry input 18 --'PULSE OUTPUT DESCRIPTION The MK50991 is a monolithic CMOS integrated circuit which converts keyboard inputs into pulse signal outputs simulating a rotary telephone dial. It is designed to operate directly from the telephone line and can be interfaced properly to meet telephone specifications in systems utilizing loop-disconnect signalling. Two outputs are provided to implement the pulse dialer function, one to pulse the line and another to mute the receiver. The mute output can be interfaced with a bistable latching relay in applications with this requirement. The MK50991 is in either the on-hook or off-hook mode as determined by the input to the pin designated "OnHook/Test." In order to accept any key inputs, the MK50991 must be in the off-hook state. Upon sensing a key input, the normally static oscillator is enabled and the row and column inputs are alternately strobed to verify that the keyboard input is valid. The decoded input is then entered into an on-chip memory. The memory will store up to 17 digits and allows keystrokes to be entered at rates comparable to tone dialing telephones. Entering the first digit (except * or #) clears the memory buffer and starts the outpulsing sequence. As additional digits are entered, they are stored in the memory and outpulsed in turn. The memory has a FIFO-(first-infirst-out) type architecture and more than 17 digits may be dialed in any number sequence. The limitation is that there can never be more than 17 digits remaining to be outpulsed. The MK50991 also features the redial function. Any 17digit number sequence may be redia led with a * or # key input, providing that the circuit enters the on-hook mode for a finite time, tOH (refer to discussion on the On-Hook/Test pin). An on-chip "Power-Up-Clear" circuit insures reliable operation of the MK50991. If the supply to the circuit should become insufficient to retain data in the memory (see electrical specifications), a "Power-Up-Clear" will occur upon regaining a proper supply level. This function will prevent the "Redial" or spontaneous outpulsing of incorrect data. A new number sequence may then be entered in normal fashion. XIII-11 • ABSOLUTE MAXIMUM RATINGS* DC Suppiy Voltage, V+ ........•......................................•......................... 6.2 Volts Operating Temperature ....•................•............................................. -30°C to +60°C Storage Temperature ....................•................................................. -SsoC to +8SoC Maximum Power Dissipation 2SoC ....................................•.......................... SOOmW Maximum Voltage on any Pin ....••............................................. (V+) + 0.3; (V-) - 0.3 Volts ·Stresses above these listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS -30°C:::; TA :::; 60°C SYM MIN PARAMETER V+ DC Operating Voltage IMR Memory Retention Current: (Note 1 ) lOp DC Operating Current: (Note 2) VREF Magnitude of (V+ - V REF ): I supply::;: 150p,A TYP* 2.S IML Mute Sink Current: V+ ::;: 2.5V, Vo IMH Mute Source CurrentV+ 2.0V Ip Pulse Sink Current: V+ ILKG Mute and Pulse Leakage: V+ 6.0V = O.SV = 2.5V, Va MAX UNITS 6.0 Volts 0.7 2.5 p,A 100 150 p,A 1.5 2.S 3.5 Volts 0.5 2.0 mA O.S 2.0 rnA 1.0 4.0 rnA ::;: = 2.5V, Va =0.5V = 6.0V, Vo = 0.001 1.0 p,A RKI Keyboard Contact Resistance 1.0 kO CKI Keyboard Capacitance 30 pF KIL Keyboard "0" Logic Level V- 20% of V+ Volts KIH Keyboard "1. " Logic 80% of V+ V+ Volts KRU Keyboard Pull-Up Resistance: (Note 3) 100 kO KRD Keyboard Pull-Down Resistance: (Note 3) 4.0 kO ROH On-Hook Pull-Up Resistance 100 kO L~vel NOTES: *Typical values are to be used as a design aid and are not subject to production testing. 1. Current necessary for memory to be maintained. All outputs unloaded. On-Hook mode. VREF tied to V-. 2. Current required for proper circuit function. Off-Hook Mode. Valid key input. VREF tied to V-. 3. Keyboard to be scanned at 500Hz when oscillator enabled. Rowand Column to alternately pull high and low. XIII-12 AC CHARACTERISTICS (The Timing Relationships are shown in Figure 4) SYM PARAMETER MIN TYP MAX UNITS fOSC Oscillator Frequency (Note 1) 4.0 kHz bof OSC1 Frequency Stability: 2.5 to 3.5V (Note 2) ±4 % bof OSC2 Frequency Stability: 3.5 to 6.0V (Note 2) ±4 % bofOSC3 Frequency Stability: 150-500,.,.A (Note 3) ±3 % PR Pulse Rate: Pin 10 tied to V+/V- 20/10 pps tOB Keyboard Oebounce Time 10 ms tKD Time for Valid Key Entry tB Break Time: Pin 9 tied to V+/ tied to V- tIDP' tPDP Interdigital Pause, Predigital Pause (Note 4) tMO Mute Overlap of Pulse 40 ms 66,.0/60.0 ms 800+ tM ms 5 ms NOTES: "Typical" values are exact assuming a 4kHz frequency reference, 1, A change in the frequency will result in a proportional change in all circuit timing. 2, For stated voltages. the given "typical" Ll.fOSC holds from part to part over the stated operating temperature range, 3. Using VREF in conjunction with a current source results in the given "typical" Ll.fOSC from part to part over the stated operating temperature and current. 4, Time from last break to next break. tM = 100ms-tS = make time. Functions of the individual pins are described below: VREF TYPICAL I-V CHARACTERISTICS Figure 1 V+, Pin 1 7.0 This is the positive supply input to the part and is measured relative to V- (pin 6). The voltage on this pin must be regulated to less than 6 volts using either the on-chip reference circuitry or an external form of regulation. 6.0 II 5.0 4.0 The VREF output provides a negative reference voltage relative to the V+ supply. Its magnitude is a function of the internal parameters which define the minimum operating voltage of each part. In a typical application, as shown in Figure 5, the VREF pin is simply tied to V-(Pin 6). The internal circuit with its associated I-V characteristic is shown in Figure 1. KEYBOARD INPUTS, Pins 3, 4, 5,13,14,15,16 3.0 2.0 PIN 2 -VREF 1.0 1.0 The MK50991 incorporates an innovative keyboard XIII·13 2.0 V+ -VREF 3.0 4.0 VOLTS 5.0 scheme that allows either the standard 2-of-7 keyboard with positive common or the inexpensive single contact (Form A) keyboard to be used. A valid key entry is defined by either a single row being connected to a single column or V- being simultaneously presented to both a single row and column. When in the On-Hook mode, the rowandcolumn inputs are held high and no keyboard inputs are accepted. When Off-Hook, the keyboard is completely static until the initial valid key input is sensed. The oscillator is then enabled and the rows and columns are alternately scanned (pulled high, then low) to verify the input is valid. The input must remain valid continuously for 10 ms of debounce time to be accepted. 20/10 PPS SELECT, Pin 10 Tying this input to either V+ (Pin 1) or V- (Pin 6) will select a pulse rate of either 20 or 10 pps respectively. MAKE/BREAK SELECT, Pin 11 The Make/Break ratio may be selected by connecting the pin to either the V+ or V- supply. The table below indicates the two popular ratios from which the user can choose. MAKE/BREAK RATIO SELECTION Table 1 INPUT TO MAKE/BREAK PIN KEYBOARD CONFIGURATIONS Figure 2 ~ COL~ ~ROW Form A Type Keyboard [±:::: v_ i 1L- 2·of-7 Matrix Keyboard Negative Common v+-----'] r--COL VLJ v+-----, r--ROW VLJ 3.5KCs 2K [ 1.386+-C - · -K+l Electronic Input 40% 60% ON-HOOK/TEST, Pin 17 In ( K ) ] 1.5K + 0.5 where Cs is the stray capacitance on Pin 7. Accuracy and stability will be enhanced with the capacitance minimized. OSCILLATOR CONFIGURATION Figure 3 66% V- (Pin 6) MUTE OUTPUT, Pin 12 The MK50991 contains on-chip inverters to provide an oscillator which .will operate with a minimum of external components. Figure 3 shows the on-chip configuration with the necessary external components. Optimum stability occurs with the ratio K = Rs/R equal to 10. The oscillator period is given by: = RC BREAK 34% The Mute output consists of a complementary pair of CMOS transistors. It provides the logic necessary to be interfaced with a bistable latching relay to Mute the speech network. Upon coming off-hook, a negative transition on Mute will insure the speech network is properly connected to the telephone line. When outpulsing begins, a positive transition will switch the relay, continuously muting the network until the entire number sequence entered is outpulsed. Figure4 shows, in detail, the timing diagram of the Mute Output. RC OSCILLATOR, Pins 7,8,9 T MAKE V+ (Pin 1) COL ~ ~ROW 2-of-7 Matrix Keyboard PULSE OUTPUT The "Test" or "On-Hook" input of the MK50991 has a 100k.o. pull-up to the positive supply. A V+ input or allowing the pin to float sets the circuit in its On-Hook or test mode while a V- input sets it in the Off-Hook or Normal Mode. When Off-Hook, the MK50991 will accept key inputs and outpulse the digits in normal fashion. Upon completion of the last digit, the oscillator is disabled and the circuit stands by for additional inputs. Switching the MK50991 to On-Hook while it is outpulsing causes the remainingdigits to be outpulsed at 100 x the normal rate (M/B ratio is then 50/50). This feature provides a means of rapidly testing the device and is also an efficient method by which the circuitry is reset. When the outpulsing in this mode, which can take up to 300ms, is completed, the circuit is deactivated and will require only the current necessary to sustain the memory and Power-Up-Clear detect circuitry (refer to the electrical specifications). Upon returning Off-Hook, a negative transistion on the Mute Output will insure the speech network is connected to the line. If the first key entry is either a * or #, the number sequence stored on-chip will be outpulsed. Any other valid key entries will clear the memory and outpulse the new number sequence. XIII-14 TIMING CHARACTERISTICS Figure 4 DIGIT DIGIT KEY INPUT ----.....,~ REDIAL ~r----------- CO~~~~ -In.ru-u-ul_~O~~~c:?~U~~~C~~ __ ~---------=uu­ ROW SCAN ~_5_0~~~~9'!!_S~~~ - ----~--- - - ----.ruu-ON-HOOK INPUT MUTE OUTPUT PU LSE OUTPUT RC2 OUTPUT ~ : r----~ ! I I --~i I' :---T1 " I I I if ii :! i .--- :r--I!L--------------f! U I i ; !: I: I I I I I I I! I I~ I ~HZOSCILLATOR Hg~K ! L-....J"L.J I : i~ ~b~:p=.n~~:::=r~JC",~~ATOROl1FF L---------~----~ ~I f.--- r NORMAL DIALING OFF-HOOK MODE RJ8b1L OF~tD~OK TEST MODE PULSE OUTPUT, Pin 18 The Pulse Output consists of an open-drain N-channel transistor. This output provides the logic necessary to pulse the telephone line with the correct Make/Break, pulse rate, and interdigital pause timings. The timing characteristic of the Pulse Output is shown in Figure 4 above. TYPICAL APPLICATION The schematic diagram in Figure S shows one method which can be used to interface the MKS0991 with the telephone line. In this approach, the speech network is connected directly to the telephone line through a metallic relay contact. The pulse signalling circuitry is in parallel with the speech network. A current source of some type is desired to present a high impedance to the telephone line while guaranteeing sufficient current to power the MKS0991 (>1S0J.LA). Transistor 02 provides the source current to the device. The magnitude of this current is determined by the voltage on R1 due to the forward-biased diodes D1 and D2· Transistor 01 provides a regulated bias current to the diodes as well as 02. When in the On-Hook mode, 51 and 52 are open. The current source is disabled in this manner and only a small amount of current, supplied through R3, is needed to maintain data in the memory. The relay is open, thereby disconnecting the speech network from the telephone line. When coming Off-Hook, switches 5l and 5'2 close, connecting the On-Hook input to V-. Immediately the output of Mute switches low. This transition pulses the relay through Os and 06, latching it in the closed position. The speech network is now attached directly to the telephone line for normal conversation. Diode D3 will hold the pulsing Darlington composed of transistors 03 and 04 off. Upon receiving a valid key entry, Mute switches high. This transition pulses the relay to its open state, thereby muting the network. The loop current is still passed through the Darlington pair, 0 3 and 0 4 , for a predigital pause time of approximately 840ms. (tPDP). Break is accomplished when the Pulse output switches low, cutting the Darlington off. During break, current flow is limited to the current source and the Pulse pullup resistor R4, insuring a high impedence in this interval. Pulsing of the complete digit continues in this manner. Each digit in the number sequence dialed is separated by standard interdigital pauses (tiDP)' After the final digit is outpulsed, the Mute Output returns low and the speech network is connected back to the telephone line through the relay contact for normal conversation. Returning On-Hook causes Mute to switch high, removing the network from the line. Applications which do not require operation with a bistable relay may use our MK50981 pulse dialer to better advantage. XIII·15 II TYPICAL APPLICATION Figure 5 >---+------fAC + TELEPHONE LINE >---+------'-I--t-t-----. r =.~\: ~~ ~~ B : ~ l!02_1~0~1~_I____'-~~R~__~__~__________-4-J~~~~~~~__~~RB>---I~_I-J OJ. fis L _ _ _ _ _ _ _ _ _ _ _ _ _ _-1 ---c; Q4 R7 300k Q3 2N3904 R9 200 k R6 3.3 k XMTR 0R8 51 k R10 20 k Ol 'N'r NOTE: Memory retention cannot be guaranteed if battery is not used. XIV-10 R5 20k R12 20 k IB UNITED TECHNOLOGIES MOSTEK TELECOMMUNICATION PRODUCTS TEN NUMBER REPERTORY DIALER WITH PACIFIER TONE MK5177(N), MK5176(N) FEATURES PIN CONNECTION Figure 1 o Silicon Gate CMOS process for low-voltage (2 to 10 V) and low-power operation V+ - - . 1 MODE - - . 2 o o cor; Low memory-retention current of 300 nA typical Auto-dials ten 16-digit numbers including Last Number Dialed (LND) o Pacifier Tone Output o Oscillator Selectable in pulse mode (RC or ceramic resonator) o Stand-alone pulse dialer o Interfaces with Mostek's tone dialers o PABX pause key input o Last number dialed memory o Last number dialed may be copied into anyone of nine other locations. o Make/Break ratio is pin selectable in pulse mode o Uses either the inexpensive Form-A type keyboard or the standard 2-of-7 matrix keyboard with common V- o Optional use of 13th key input to control repertory functions in tone mode 18 ..... PUlSE/13KEY 17-+- HKS ..... 3 16 ..... ROW1 COl2 ....-. 4 15 ...... ROW2 COl3 ...... 5 14 ...... ROW3 v- --.6 13 ...... ROW4 OSC/RC - - . 7 12 ----. MUTE/DD OSC/NC - - . 8 11-+- MB/CNTl OSC ----. 9 SELECT 10--. PACIFIER TONE Pin 2, the "Mode Select" input determines whether signaling will be pulse or tone. The interpretation of several inputs and outputs is dependent upon the mode selected. In the pulse mode, the time base for the circuit is selectable between a ceramic resonator and an RC oscillator. In Tone mode, the circuit can use only the RC oscillator. DESCRIPTION The MK5177 and MK5176 are monolithic, integrated, tennumber repertory dialers manufactured using Mostek's Silicon Gate CMOS process. The circuit accepts keyboard inputs and provides the pulse and mute logic levels required for loop-disconnect signaling. In addition, the MK5177/6 interfaces with the MK5380 or MK5389 tone generator circuits for DTMF signaling. The MK5177 is functionally similar to the MK5175 except for pins 9 and 10, which provide the additional features of Oscillator Select and Pacifier Tone Output. The MK5176 is the same as the MK5177, but has continuous mute timing on its Mute output (see Figure 5b). An on-chip RAM is capable of storing ten 16-digit telephone numbers, including the last number dialed. When used in a PABX system, a pause (# key) may be stored in the number sequence. The repertory dialer will recognize this pause when automatically dialing and stop until another key input is received. The MK5177 /6 repertory dialer uses a standardized pinout, shown in Figure 1, common to other Mostek tone and pulse dialers. This facilitates the design of a family of telephone products using common PC boards and circuit components. The block diagram in Figure 2 illustrates the general internal structure of the MK5177/6. FUNCTIONAL DESCRIPTION V+, Pin 1 Pin 1 is the positive supply input to the part and is measured relative to V- (Pin 6). The voltage on this pin should not exceed 10 volts. A low voltage detect circuit will perform a power-up initialization whenever the supply voltage at this pin falls below a level necessary to guarantee proper circuit operation. XIV-11 II MK5177/6 BLOCK DIAGRAM Figure 2 MANUAL/AUTO· DIAL CONTROL lOGIC MB /CNTL >,-'.:...;'I__________---J I I MODE~2~1--~.r-------' I I I I OSC SEl >-,9~1---"'"l........___...J I I I I I L_ - - -:;--- i I - - - - - - - ~---16-----------w------~ OSC IN OSC OUT PACIFIER TONE HKS MODE, Pin2 KEYBOARD INPUTS, Pins 3, 4, 5,13,14,15,16 The MK5177 /6 will function in either tone or pulse mode, dependent upon the logic level presented to pin 2. For pulse mode operation, this pin must be tied to V- (pin 6). For tone mode, it should be tied to V+ (pin 1). The interpretation of pins 7, 8, 11, 12, and 18 is dependent upon the mode selected. The MK5177/6 incorporates a keyboard scheme that allows either the standard 2-of-7 keyboard with negative common or the inexpensive single-contact (Form A) keyboard to be used, as shown in Figure 3. KEYBOARD CONFIGURATIONS Figure 3 COL » ________A .. h. _ _ _---« ROW v_£ FORM A TYPE OF KEYBOARD c < ROW .,h._ _ _ _ -~~------~< RONV .. h. _ _ _--« 2-7 MATRIX KEYBOARD NEGATIVE TRUE COMMON .. h. _ _ _--« COL 2 OF 7 MATRIX KEYBOARD XIV-12 COL A valid key entry is defined by either a single row being connected to a single column or byV- being simultaneously presented to both a single row and column. In the tone mode, the MK5177/6 features a bidirectional keyboard scheme. As the MK5177/6 passively monitors the key inputs (using the scan provided by the tone dialer), they are debounced, decoded; and stored in the on-chip LND (Last Number Dialed) buffer. The keyboard inputs in tone mode normally have high impedance, allowing the tone chip to scan the keyboard lines and begin signaling immediately upon detecting a key entry. A command key entry disables the tone chip, and scanning is then controlled by the repertory dialer until the key is released. In tone mode, auto-dialing is performed by the MK5177/6, which simulates key-contact closures. The tone generator accepts these inputs as valid keyboard information and generates the proper DTMF frequencies. In the pulse mode, the MK5177/6 keyboard inputs are static until an initial valid key input is sensed. The oscillator is then enabled, and the rows and columns are alternately scanned (pulled high, then low) to verify that the input is valid. Keyboard bounce is ignored for 32 ms after the initial key down is detected. A key input is accepted if it is valid after this initial debounce time. This scheme guarantees any valid key inputto be recognized in less than 40 ms after the initial key closure. provides for a tone rate of 100 ms on and 100 ms off and a pulse rate of 10 pps. The frequency of oscillation is approximated by the equation: Fosc = 1/(1.45 RC). The value suggested for the capacitor (C) should be 410 pF or lower, and resistor (R) may be adjusted for the desired signaling rate. 10 PPS and 5 TPS operation is achieved by selecting a 390 pF capacitor and a 220K Ohm resistor. A more accurate and constant frequency reference in pulse mode is obtained using a 480 kHz ceramic resonator, as shown in Figure 4b. The ceramic resonator is connected in parallel with an on-chip inverter. Two external capacitors to ground also are required. OSCILLATOR SELECT, Pin 9 This pin determines the mode of oscillation used by the repertory dialer when in pulse mode. The ceramic resonator is chosen by tying this pin to Pin 1 (V+). The RC oscillator is chosen by tying this pin to Pin 6 (V-). In tone mode, this input must be tied either high or low; however, it will not affect the mode of oscillation, which is always RC. The timing of the repertory dialer is independent of the tone chip that uses a 3.5795 MHz crystal as its frequency reference. V-, Pin 6 PACIFIER TONE, Pin 10 Pin 6 is the power supply return pin and is the reference for all input levels and the V+ supply (pin 1 ). OSCILLATOR, Pins 7 and 8 The RC oscillator (Figure 4a) requires a resistor and capacitor to provide the frequency reference for the MK5177/6. The resistor should be connected from Pin 7 (Osc/RC) to pin 1 (V+) and the capacitor from Pin 7 to Pin 6 (V-). Pin 8 should be connected to V+ for normal operation. The nominal frequency for standard operation is 8 kHz. This The pacifier tone consists of a burst of a 5OO-Hz square wave. The burst is initiated with the acceptance of a valid key input (following the debounce time) and terminates after 28 ms or with the release of the key, whichever comes first. The output has high impedance when not active. MB/CNTL, Pin 11 The level on pin 18 determines the control-key inputs required to implement the repertory-dialer function. In the OSCILLATOR CONFIGURATIONS Figure 4 B. CERAMIC RESONATOR A. RC OSC 7 v+ CR o1----.-_--t 8 7 vNOMINAL FREQUENCY vFREQUENCY 8 kHz XIV-13 480 kHz II 13-key tone mode, pin 11 can be used to control the repertory-dialer functions of the phone with a momentary SPST switch to the negative supply connected to th is input. This feature allows the basic keyboard to operate the same as in a standard telephone, and only the closure ofthe 13th key will initiate a repertory dialer function. The "*" and "#" key inputs will be accepted as normal DTMF inputs ~however, they will not be stored in the LND buffer). In 12 key mode, this pin should be connected to the positive supply (V+). Table 1 MB Input %Break %Make V+ V- 60 68 40 32 Dialer Disable signal which inhibits the generation of tones during command key entries. The timing characteristics in tone mode are shown in Figure 5a. In pulse mode, the make/break ratio may be selected by connecting this pin to either the V+ or V- supply. Table 1 indicates the two ratios available. In the pulse mode, pin 12 is the Mute output. It provides the logic necessary to mute the receiver while the telephone line is being pulsed. A typical method of interfacing this output is shown in the application diagram in Figure 8. Figure 5b shows the timing characteristics of the Mute output for both the MK5177 and MK5176. The continuous MUTE/DIALER DISABLE, Pin 12 Pin 12 is the output of an open-drain, N-channel transistor. In the tone mode, it is used to provide the tone dialer with a TONE MODE TIMING Figure 5a 'I ~ * * * 'L.-________--Jr>--------L--_ _ _ _ _ _ _ _ _ __ MANUAL KEY ENTRY DIGIT 9 PAUSE It "- ON HOOK STORE DIGIT DIGIT 41 STORE "- LOCATION 6 AUTO·DIAL AUTO DIAL LOCATION 5 CONTINUE· 5 KEYINPUT~~~ HKSINPUT 0'iAffii5iSABLE ------.,L...Jr--------{~~ CQ[1----If'J'"1fc~~~~ lfUlJlJU2!)OHlSCANFReaUENCY~ EOr2 ROW2~~~ ROW3~~~ L-.J ROW4 PACIFIER TONE ~~Jr----- ---------1-------1--------1-------1-----< ·---mID------I-- -----1--- -< !------I- -- -- (MK6380)TONE~ --I-L--- ---1- ---- --- - --- ~ ·.h.D...... -.l A~ /T PULSE MODE TIMING Figure5b KEY INPUT DIGIT 2 COLUMN SCAN -AAJlJUl ROW SCAN PACIFIER TONE *MUTE OUTPUT **MUTEOUTPUT PULSE OUTPUT HOOKSWITCH STORE SCANA"'V, LOCATION 1 LOCATION 1 II lIlJlJlJU U . SCAN Acnv, II II I1JU1JlL ----1---- --l1li---- ---< .. ------- ------ ----------111-----.----11-------- 11------8--------- ------f f----- ----------- ---- -----,1-_ _ _...., r - - - - - 1 - - - - - - - - - - - L - - - - - 1 ; ..Jr t-) _ _ _ _ _ II I ~I--"""JL---1----------lltl,~~ ~I I II oscmmR * 3 ~I---------' I II ~t;',-J,~C "-, 1.'::- NORMAL DIAL * MUTE OUTPUT FOR MK5176 ** MUTE OUTPUT FOR MK51n I I · I ~ u u II I ~TIDP. -I 1TM -, - I a:::::wILJ,"j~r~ :r~ co"'" m AlTERNATE LOCATION XIV-14 II I AlITO-DIAl ~ Mute timing provided by the MK5176 is particularly useful in applications sensitive to noise generated during dialing, such as in cordless telephones. ignored and not affect the number dialed. In tone mode, if a key is entered while auto-dialing, it will interfere with the keyboard outputs generated by the MK5177/6. The key entry is detected and auto-dialing is interrupted until the key is released. The keyboard entry generates a DTMF Signal if valid. HKS, Pin 17 The HKS (hook switch) input determines how the repertory dialer will handle key entries. When in the off-hook state (pin tied to V-), signaling is enabled, and all entries will be stored in the LND buffer. A control-key input in this state initiates the AUTO-DIAL function. The MK5177 /6 repertory dialer will not store either a "*,, or "#" entry in the buffer but will allow the tone generator to signal these digits as described below. 12-KEY OPERATION In the on-hook state (pin 17 tied to V+), the dialer stores key information in the LND buffer as they are entered but will not pulse out or allow the DTMF generator to tone. A control-key input is interpreted as a STORE command, causing the information present in the LND buffer to be copied into the indicated location. NORMAL DIALING A hook-switch transition terminates all dialer operations immediately and initializes all counters and latches. The dia ler is then ready to accept a key entry wh ich wi II be stored over previous data in the LND buffer. PULSE/13KEY, Pin 18 In the tone mode, a V+ level at pin 18 allows the MK5177 /6 to accept inputs from a control key (n.o. SPST) connected from CNTL (Pin 11) to V-. It is used to initiate all repertory functions. This is referred to as 13-key tone mode. With Pin 18 tied toV-, the MK5177 /6 is set in the 12-keytone mode, and the "*,, and "#" keys are used in control functions. Pulse mode defaults to 12-key mode. Both 12- and 13-key tone modes are discussed in more detail in the Operations section of this data sheet. In the pulse mode, Pin 18 is the Pulse output. It consists of an open-drain, N-channel transistor and provides the necessary timing for make, break, interdigital delay, and pulse rate to meet dialer specifications worldwide. The timing charcteristics' of the Pulse output are shown in Figure 5b. GENERAL OPERATION During normal dialing, each digit is stored in the LND (Last Number Dialed) buffer, location O. The telephone number dialed can be left in this temporary LND buffer for later use, or it can be copied into any of the other nine permanent memory locations (1-9). The wrap-around feature of the buffer allows more than 16 digits to be dialed. Entries following the sixteenth input will be stored beginning with the first buffer location, replacing the information originally stored there. Any number of digits maybe entered and dialed correctly. In pulse mode, the user should not get more than 15 entries ahead of the digit being pulsed. Keys entered while auto-dialing in pulse mode will be In pulse mode, digits 0-9 will result in the pulsing of that digit at the standard rate of 10 pps. If the RC oscillator is utilized, this rate can be varied, achieving a pulse rate of up to 20 pps. The "*,, and "#" keys enable the repertory functions listed below. In tone-mode operation, digits 0-9 cause the generation of respective DTMF signal. In order to tone a "*,, or "#" key, it must be entered twice. The second entry will generate the desired DTMF tone, although it will not be stored in memory. STORAGE Telephone numbers may be entered into the LND buffer while either on-hook or off-hook. However, the MK5177 /6 must be in the on-hook mode for a number to be copied into a permanent memory location. The LND is copied by entering the key sequence "**", followed by the address (1-9) of the desired memory location. This operation requires 300 ms before going off-hook or initiating another store, and does not change the data in the LND buffer. Information present in the LND buffer when new data are entered is replaced and cannot be recalled. The storage operation may be performed with the telephone off-hook. It requires the addition of an additional switch (Figure 7), providing an excellent "scratchpad memory". Numbers may be entered and copied without signaling the line, making use of line current rather than battery current. Scratch pad memory is useful whenever the user has a need to record a te~:ephone number. AUTOMATIC DIALING The automatic dialing function is implemented by going off-hook and entering a "*", followed by the address(1-9)of the desired telephone number. Dialing will begin with the release of the address key and can be interrupted by initiating a new redial command or with a transition on the HKS pin. The LND buffer will contain the information last entered. A key sequence of "*,, 0 will cause the last number entered to be redialed. More than one number sequence may be automatically dialed from memory without returning on-hook. XIV-15 III PAUSE/CONTINUE ENTRIES The MK5177/6 has a feature that allows an indefinite pause to be programmed into the first 15 digits of a number sequence by entering a "#" key at the point in the sequence where a pause is desired. As the number is automatically dialed, the circuit will stop dialing when the pause is encountered. Any key entry, except for a "*,, key, will cause the MK5177/6 to continue .dialing the remainder of the number. If more than one pause was originally programmed into the number sequence, a corresponding number of "continue" commands must be made in order for the number to be completely dialed. The "continue" input will not be recognized until one IDP period following the signaling of the digit preceding the pause. This is approximately 940 ms in pulse mode and 100 ms in tone mode. 13-KEY MODE OPERATION NORMAL DIALING An additional mode of operation (tone mode only) is the ability to use the entire keyboard for normal signaling such that when any key is depressed once, including "*,, or "#", the proper DTMF signal is generated. This feature is activated by connecting Pin 18 to V+. The repertory-dialer functions are then initiated by an extra control key (n.o. SPST) connected from Pin 11 (MB/CNTL)to V-. This key will be referred to as "C". autodialed by entering CoN when the input to HKS (pin 17) is low. Autodialing may be initiated immediately following a hookswitch transition or manual key entries, or after the completion of a previous auto-dial number. PAUSE/CONTINUE An indefinite pause may be inserted into the number sequence with a C-# entry. This feature is quite useful when dialing through a PABX. When a number sequence with a pause is autodialed, signaling will stop when the pause is reached and will continue only when a valid key input is detected. EXAMPLES I. Pulse and 12-Key Tone Mode CALL FRIEND AT MOSTEK, i) Off-hook, dial 42 (PBX access code), and # (PAUSE) ii) Dial 1-214-466-1 000. ii) CALL COMPLETED, PARTY NOT IN. iii) On-hook, enter 3 (stores number into permanent memory location 3) SOME TIME LATER ... AUTO-DIAL LOCATION 3. iv) Off-hook, enter 3, receive dial tone, enter 3 to continue. NUMBER IS AUTO-DIALED, PARTY ANSWERS. ** * II. 13-KeyTone Mode STORAGE The information in the LND buffer may be "copied" or stored into one of the nine perma nent memory locations when the input to HKS is high. The control sequence for this function is CoN. The information will be copied, yet the LND buffer information will be left intact. AUTOMATIC DIALING Information stored in any of 10 memory locations may be CALL "INFORMATION" TO GET THE NUMBER FOR MOSTEK'S MARKETING DEPARTMENT. i) Off-hook dial 1-214-555-1212, SET TELEPHONE TO "SCRATCHPAD" ii) Enter 1-214-466-1241; the information is stored in the LND buffer. HIT THE HOOKSWITCH; AUTO-DIAL MOSTEK iii) Enter CoO, autodial of the LND buffer begins. CALL COMPLETED, ORDER SOME MK5177 REPERTORY DIALERS FOR YOUR NEW TELEPHONE DESIGN. FUNCTIONAL SUMMARY Table 2 FUNCTION Store in permanent memory Redial from memory Enter PABX Pause Redial Last Number Tone Tone # C is a control-key entry N is a digit entry (0-9) * 13-KEYTONE • 12-KEYTONE • * C N t CN C# t CO t * t # t * * N # t *0 t ** , • indicates HKS input is high • indicates HKS input is low XIV-16 # # N PULSE •t * * * N # t *0 - N ABSOLUTE MAXIMUM RATINGS* DC Supply Voltage, V+ ........................................................................... 10.5 Volts Operating Temperature ...................................................................... -30°C to +60°C Storage Temperature ....................................................................... -55°C to +125°C Maximum Power Dissipation (25 C) ................................................................. 500 mW Maximum Voltage on Any Pin ............................................................. (V+) +0.3, (V-) -0.3 'Stresses above those listed under "Absolute Maximum Ratings" may cause permanentdamagetothe device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposureto absolute maximum ratings for extended periods may affect device reliability. OPERATING SPECIFICATIONS ELECTRICAL SPECIFICATIONS SYM PARAMETER MAX UNITS NOTES V+ DC Operating Voltage 10.0 Volts 1 lop Operating Current (Tone) 50 100 J.lA 2 lop Operating Current (Pulse) 100 200 /-LA 2 IS8 Standby Current (V+ 1.0 2.0 /-LA 3 IMR Memory-Retention Current 0.3 1.0 /-LA 1 V MR Memory-Retention Voltage 1.5 1.3 V 1 IML Mute-Sink Current 0.5 2.0 mA 4 Ip Pulse-Sink Current 1.0 4.0 mA 4 IpT Pacifier Tone Source/Sink 200 500 /-LA 4 ILKG Mute And Pulse Leakage 1.0 /-LA 5 RKI Key Contact Resistance 1.0 k-Ohms 6 CK1 Keyboard Capacitance 30 pF 6 KIL "0" Logic Level V- 0.2V+ Volts KIH "1" Logic Level 0.8V+ V+ Volts KRU Keyboard Pullup 100 k-Ohms 7 KRD Keyboard Pulldown 1.0 k-Ohms 7 ReNT CNT Pullup (pin 11 ) 100 k-Ohms 8 MIN TYP* 2.0 = 2.5 V) .001 NOTES: 1. The memory will be retained at a lower voltage level than that required for circuit operation. If either IMR or VMR is maintained, the memory contents will not be cleared. 2. Operating current with a valid key input at 2.5 volts. 3. Standby current on-hook or off-hook with all inputs unloaded. 4. 5. 6. 7. a. XIV-17 For V+ = 2.5, Sink Va = 0.5 Volts, Source Va = 2.0 volts. Leakage with V+, Va = 10.0 Volts Keyboard contact resistance and parasitic capacitance, maximum values. Keyboard 1/0 pins will scan 250 Hz with oscillator-enabled pulse mode and during 55 in tone mode. Tone mode only. • OPERATING CHARACTERISTICS (cont) AC CHARACTERISTICS SYM PARAMETER FCR Oscillator (Cer. Res.) FRC Oscillator (RC) .6.F RC Oscillator Stability TOB Debounce Time TKO Valid Key-Down Time Tos Oscillator Start-Up Time TROL Key-Rollover OVLP Time PR Pulse Rate TB Break Time (pin 11 V+/V-) T,op MIN TYP* MAX 480 8 16 UNITS NOTES kHz 1 kHz 2 +3% -3% 32 3 ms 4 ms 40 8 ms ms 4 5 10 PPS 60/68 ms Interdigital Pause Time 940 ms Tpop Predigital Pause Time 170 ms TMOL Mute Overlap Time 2 ms TR Tone Rate 5 TPS TpT Pacifier-Tone-Burst Time 28 ms 7 FPT Pacifier-Tone Frequency 500 Hz 8 6 NOTES: 1. Ceramic Resonator should have the following equivalent values: R < 20 Ohms, RA > 70k Ohms, Co < 500 pF. 2. The RC values chosen determine frequency. The nominal frequency is 8 kHz. To accelerate dialing, the frequency may be increased to twice the nominal value. This would double signaling rate and halve most timing specifications. 3. Voltage range of 2.5 to 6.0 volts, over temperature, and unit-to-unit variations. 4. Key entry must be present after 32 ms to be valid. 5. Rollover is the time key inputs must be invalid for successive entries to be recognized. 6. Time from initial key input till first break or tone output. 7. Tone burst will terminate if key released before 28 ms. 8. This is a square-wave output. TYPICAL APPLICATIONS In pulse-mode operation, the MK5177/6/MK5380 pair is isolated from the line and pulsing transients by constant current diode Q1. The tone generator is always disabled in pulse mode (except for the on-hook state). In tone mode, Q1 is bypassed allowing the OTMF tone generator to modulate the line directly. The time base for the repertory dialer is an RC oscillator circuit using R8 and C2, and the frequency reference for the tone generator is supplied by a 3.5795 MHz crystal. PULSE/TONE SWITCHABLE APPLICATION This application circuit, shown in Figure 6, allows the user to switch between tone and pulse modes with the use of a single SPOT switch. Standby current for the MK5177/6/ MK5380 pair will typically be less than 1.5 pA when onhook, during which time the circuit will be in tone mode. When on-hook, there is no real difference in functionality between tone and pulse mode. Current is supplied by the battery when on-hook and by the line when off-hook. Diode 06 serves to prevent current flow from the battery to the network or to the line. Diode 01 prevents charging of the battery and clipping of the generated tones. In tone-mode operation, the MK5380 should never be forcibly disabled or removed from the circuit, since initial detection of any key input depends upon the scan circuitry of the tone chip. *Typical values are not subject to production testing; typical timing values assume a nominal frequency reference of 8 KHz. Common circuitry is used to mute the transmitter and receiver in both modes of operation. Mute (MK5177/6) removes the transmitter and receiver in pulse mode by cutting off Q3 and Q4 through 02. With these elements removed, pulsing is accomplished by switching Q6 on (MAKE) and off (BREAK). Pulsing through the network in this way is termed "series pulsing". Mute (MK5380) operates similarly in the tone mode; the CMOS logic level is XIV-18 inverted through 02, which provides base drive for 03 and 04. During Mute, 02 is off, thereby cutting off 03 and 04. supply to eliminate any sudden current flow from on-hook key entries. Also shown is a piezo resonator that is driven directly by the pacifier-tone output (MK5177/6). This resonator may be dedicated to the repertory dialer or shared with the ringer circuitry for increased economy. PULSE-ONLY The application of the MK5177/6 repertory dialer in a pulse-only circuit is identical to that ofthe MK5175 (shown in the MK5175 data sheet), except for the ability of the MK5177/6 to use an RC oscillator. The RC oscillator not only costs less but provides a means to accelerate the signaling rate from 10 pps to 20 pps. TONE-ONLY APPLICATION The tone-only application (Figure 7) is much like the switchable application (Figure 6), but since it is tone-only, it uses a minimum number of external components. It consists primarily of a standard tone-application circuit with some additional supply considerations. The application shown in Figure 8 uses parallel pulsing and illustrates how storage can be accomplished off-hook with the addition of a single programming switch. When switched to a program mode while off-hook, pulse signaling is inhibited, but numbers may be entered into the LND buffer and then stored into any of the nine permanent memory locations, providing a versatile "scratchpad" feature. 'The MK5177/6 repertory dialer shares the keyboard with the MK5380 and controls the activity of the tone chip through the keyboard and Dialer Disable. When on-hook, the load resistor on the tone output is connected to the TONE - PULSE SWITCHABLE Figure 6 TIP. RING _1. ST! 3V BATIERY M K 5 3 8 0 C;; HKS2 ON HOOK i5"i57M'iffE12 _18 PULSE R1 R2 R3 R4 R5 R6 R7 R8 100 390K 10K 51K 390K 20K 20K 220K R9 R10 R11 R12 R13 C1 C2 Z1 10K 10K 100K 10K 390K .005 IlF 390 pF 10K220 XIV-19 01-6 01 02 03 04 05 06 Z2 X2 1N914 J500/CR022 2N5401 2N5550 2N5550 2N5550 2N5550 1N753 Piezo Resonator MK5177/6/MK5380 TONE MODE APPLICATION CIRCUIT Figure 7 DIODE BRIDGE 02 ~ NO ON HOOK M K M K , 5 5 7 3 7 8 o esc 7 X, IN ~3.6795 Dli r- - - - - - - --, : esc MH, CRYSTAL 8 OUT 1 ----.----1 ·'""0+-<0--.:... SCRATCHPAO 2 CD t-'2_ _ _ _ _-1 PAC 10 TONE 1 1 : NO e~OK OSC SEL i L ____ ..: __ R1 R2 R3 R4 R5 R6 R7 220K 390K 10K 3.3K 390K 100 22 390 pF .005 ",F 1 N914 1 N914 2N5401 2N5550 2N6660 C1 C2 01 02 01 02 03 Z1 Z2 10K220 1N753 MK5177/6 PARALLEL PULSE MODE - NO BATrERY Figure 8 HKS1 N.C. ON HOOK . I DIODE BRIDGE C2 ':" '000 pF 1- - - - - - - --l ~____~I~~~ r I N.O. ON HOOK HKS2 I I I : ___ ':'"______ J R1 R2 R3 R4 R5 R6 R7 RS 10K 200K 2.2 M 150 470K 100K 3K 390K R9 R10 C1 C2 01-3 Z1 Z2 220K 240K 390 pF 1000 ",F 1 N914 10KS20 1N753 XIV-20 01 02 03 04 2N5401 2N5550 2N5550 2N5550 m UNITED TECHNOLOGIES MOSTEK TELECOMMUNICATIONS PRODUCTS TEN-NUMBER REPERTORY TONE/PULSE DIALER MK5375 FEATURES o CMOS Technology provides low-voltage operation PIN CONNECTION Figure 1 o Converts push-button inputs to both DTMF and loopdisconnect signals o Stores ten 16-digit telephone numbers, including last number dialed o Pacifier tone and PBX pause o Last-number-dialed (LND) privacy o Manual and auto-dialed digits may be cascaded o Ability to store and dial both "*,, and "#" DTMF signals o Variable dialing rate v+ 18 PULSE MODE SELECT 17 HKS ROW1 COL 1 16 COL 2 15 ROW 2 COL 3 14 ROW 3 v- 13 ROW 4 RATE CONTROL 12 MUTE OUTPUT OSC1 8 11 PACIFIER TONE/CHIP DISABLE OSC2 9 10 DTMF OUTPUT DOn-chip power-up-clear guarantees data integrity DESCRIPTION The MK5375 is a monolithic, integrated circuit manufactured using Mostek's proprietary Silicon Gate CMOS process. This circuit provides the necessary signals for either DTMF or loop disconnect dialing. It also allows for the storage of ten telephone numbers, including as many as 16 digits each, in on-chip memory. The MK5375 accepts rapid keypad inputs (up to 25 key entries per second) and buffers these inputs in the FIFO (First-In-First-Out) LND (Last-Number-Dialed) register. Each digit entry is accompanied by a pacifier tone, which is activated after the digit has been debounced, decoded, and properly stored. Signaling occurs at a rate determined by externally connected components, allowing the dialing rate to be adjusted for any system. Privacy is also an important feature. The MK5375 allows the LND (Last-Number-Dialed) buffer to be cleared following a call, without affecting data stored in other permanent memory locations. The memory in the permanent locations may be easily protected from inadvertent key entries with the addition of a simple "memory lock" switch to the application. All of these options plus additional features are discussed in more detail in the following sections. The first section contains a brief detailed description of each pin function. The second section describes the device operation. This is followed by the DC and AC Electrical Specifications, and a few application suggestions. FUNCTIONAL PIN DESCRIPTION V+ (Pin 1) The flexibility of the dialer makes possible a variety of applications, such as "scratchpad" number storage. In "scratchpad" applications, the MK5375 inhibits signaling during entry, without interrupting a conversation. Pin 1 is the positive supply for the circuit and must meet the maximum and minimum voltage requirements as stated in the electrical specifications. XIV-21 II MK5375 FUNCTIONAL BLOCK DIAGRAM v+ Figure 2 r- ___________ v- .l!_ J.s ___________________ ., I I I I I I PT/CD o--t+--.j I CMOS RAM (840 BITS) I I I I I LND REGISTER PULSE/MUTE 1--_+-'8-o;;um O~~~T 1'2 1--4---0 O~~~T I I I IL ________________________________ MODE SELECT (Pin 2) In normal operations, Pin 2 determines the signaling mode used; a logic level 1 0J +) selects Tone Mode operation, while a logic level 0 0J -) selects Pulse Mode operation. This input must be tied to one of the supplies to guarantee proper dialing. This pin can also be used to force the device into a test mode; this mode of operation is not suitable for normal dialing. KEYBOARD INPUT: COL1, COL2, COla, ROW4, ROW3, ROW2, ROW1 (Pins 3,4,5,13,14,15,16) The MK5375 keypad interface allows either the standard 2-of-7 keyboard with negative common or the inexpensive single-contact (FORM-A) keyboard to be used (Figure 3). A valid key entry is defined by either a single Row being connected to a single Column or by V - being presented to both a single Rowand Column. In standby mode either all the rows will be a logic 1 0J +) and all the columns will be a logic 0 0J -), or vice versa. The keyboard interface logic detects when an input is pulled low and enables the RC (Rate Control) oscillator and keypad scan. Scanning consists of alternately strob- XIV-22 I I ~ ing the rows and columns high through on-chip pullups. After both valid row and column key closures have been detected, the debounce counter is enabled. Breaks in contact continuity (bouncing contacts, etc.) are ignored for a debounce period (Tdb) of 32 ms. At this time the keypad is sampled, and if both row and column information is valid, this information is buffered into the LND location. RATE CONTROL (Pin 7) The Rate Control input is a single-pin RC oscillator. An external resistor and capacitor determine the rate at which signaling occurs in both Tone and Pulse modes. An 8 kHz oscillation provides the nominal signaling rates of 10 PPS (Pulses per second) in Pulse Mode and 5 TPS (Tones per second) in Tone Mode; the Tone duty cycle is 98 ms on, 102 ms off. The RC values on this input can be adjusted to a maximum oscillation frequency of 16 kHz resulting in an effective Pulse rate of 20 PPS and a Tone rate of 10 TPS. The frequency of oscillation is approximated by the following equation: Fosc = 1/(1.49RC). (1.0) The value suggested for the capacitor (C) should be a maximum of 410 pF to guarantee the accuracy of the oscillator. The resistor is then selected for the desired signaling rate. Nominal frequency (8 kHz) is achieved with component values of 390 pF and 220 kohms. Parasites must be taken into account. KEYPAD SCHEMATICS Figure 3 3A. Calculator-1\tpe Keypad OSCIN,OSCOUT (Pins 8,9) Pins 8 and 9 are the input and output, respectively, of an on-chip inverter with sufficient loop gain to oscillate when used in conjunction with a low-cost television colorburst crystal. The nominal crystal frequency is 3.579545 MHz, and any deviaton from this standard is directly reflected in the Tone Output frequencies. R1 R3 This oscillator is under direct control of the repertory dialer and is enabled only when a tone signal is to be transmitted. During all other times it remains off, and the input has high impedance. The input OSCIN may be driven by an external source. C1 C2 C3 DTMF OUTPUT (Pin 10) The DTMF Output pin is connected internally to the emitter of an NPN transistor, which has its collector tied to V +, as shown on the functional block diagram (Figure 2). The base of this transistor is the output of an on-chip operational amplifier that mixes the Rowand Column Tones together. 38. Standard Telephone-1\tpe Keypad The level of the DTMF Output is the sum of a single row frequency and a single column frequency. A typical singletone sine wave is shown in Figure 4. This waveform is synthesized using a resistor tree with sinusoidally weighted taps. The tone level of the MK5375 is a function of the supply voltage. The voltage to the device may be regulated to achieve the desired tone level, which is related to the supply by either of the following equations: T(O) = 20 LOG [(O.078V + )/0.775] dBm. T(O) = 0.085(V+) VRMS. r I I R'-{)-4 r - - -Q- -¢- ~ ¢- -cP- -cP- - -..., - -¢- -cP--¢ --0- R2 ¢--dr-CP- (2.0) (2.1) '---~--Cf--~~o------" COMMON PACIFIER TONE OUTPUT / CHIP DISABLE (Pin 11) (CONNECT TO V - OR LEAVE FLOATING) - - - MECHANICAL LINKAGE This pin normally has high impedance. Upon acceptance of a valid key input, and after the 32 ms debounce time, a 500 Hz square-wave will be output on this pin. The square-wave terminates after a maximum of 30 ms or when the valid key is no longer present. The purpose of this pacifier tone is to provide to the user audible feedback that a valid key has been entered. This feature is useful particularly for on-hook storage and pulse-mode signaling. XIV·23 • TYPICAL SINE WAVE OUTPUT - SINGLE TONE SPECTRAL ANALYSIS OF WAVEFORM IN FIG. 7 Figure 4A (Vert-10 dB/div. Horizontal - 600 Hz/div.) Figure 4C TYPICAL DUAL-TONE WAVEFORM (Row 1, Col 1) OUTPUT FREQUENCY Figure 48 Table 1 KEY INPUT XIV-24 STANDARD FREQUENCY ACTUAL FREQUENCY % DEVIATION ROW 1 697 699.1 +0.31 2 770 766.2 -0.49 3 852 847.4 -0.54 4 941 948.0 +0.74 COL 1 1209 1215.9 +0.57 2 1336 1331.7 -0.32 3 1477 1471.9 -0.35 The pacifier tone is not enabled when manually dialing in tone mode. This eliminates any confusion between the audible DTMF feedback and the pacifier tone, and prevents distortion of the DTMF signal by any of the pacifier tone frequency components. In both cases, the tone confirms that the key has been properly entered and accepted; whereas, without the tone, the user will not know if the keys have been properly entered. meets Bell Telephone and EIA specifications for loopdisconnect signaling. The Make/Brake ratio is set to 40/60 on the standard MK5375. The pulse rate is determined by the RC values selected for the Rate Control, Pin 7. Note: The standard make/break ratio may not be suitable if the Pulse dialing rate is accelerated. IMPORTANT: This pin also serves as a chip-disable pin. Pulling this input high through a resistor will disable the keypad (high impedance) and initialize all counters and flip-flops (memory remains undisturbed). Pulling the input low through the same resistor enables the circuit. For the device to function properly, the resistor to V - (Pin 6) is required. The MK5375 can be used in low-priced phones with basic 3 x 4 matrix keypads. The block diagram in Figure 2 shows the data and control signal flow between the various functional blocks. The keypad entries are decoded, debounced, and if valid, they are stored into the LND (Last-Number-Dialed) buffer, which acts much like a FIFO (First-In-First-Out) register. Each subsequent entry is stacked in the buffer. Typically, the dialing sequence begins 172 ms after the first digit is accepted in Pulse Mode operation and 132 ms in Tone Mode operation. Each digit buffered into the RAM is dialed out with a 98 ms burst of DTMF and an inter-signal time of 102 ms. This feature is useful in several applications, as described in the application notes section. MUTE OUTPUT (Pin 12) This pin is the Mute output for both Tone and Pulse modes of operation. The timing is dependent upon which mode is being used. The output consists of an open-drain, N-channel device. During standby, the output has high impedance and generally requires an external pullup resistor to the positive supply. In Tone Mode, the Mute output is used to remove the transmitter and the receiver from the network during DTMF Signaling. The output will mute continuously while auto-dialing and during manual DTMF signaling until each digit entered has been signaled. In Pulse Mode of operation, the Mute output is used to remove the receiver or even the entire network from the line. These timing relationships are shown in Figure 5. HKSINPUT (Pin 17) DEVICE OPERATION Buffering the data into the RAM prior to signaling is an important feature of the repertory dialer. It allows for the use of less expensive keypads, since the user cannot enter the digits too quickly for the system, and the pacifier tone can be used to provide audible feedback following each key entry not generating a DTMF signal. It also guarantees that the data stored in the RAM matches exactly the digits actually dialed. Manual dialing and auto-dialing can be executed in any order, consecutively or cascaded. The dialer must complete auto-dialing the previous entry before another key is entered. Digits should not be entered while the device is autO-dialing. Most digits would be ignored unless preceded by a control key; in which case, an error in dialing may occur. KEYPAD CONFIGURATION Figure 6 This pin is a high-impedance input and must be switched high for on-hook operation or low for off-hook operation. A transition on this input will cause the on-chip logic to initialize, terminating any operation in progress at the time. Signaling is inhibited while on-hook, but key inputs will be accepted and stored in the LND register. The information stored in the LND register may be copied into an alternate location only while on-hook. A logic level may be presented to this input, independent of the position of the hook-switch, allowing on-hook operations, such as storage, to be performed off-hook. PULSE (Pin 18) This is an output driven by an open-drain, N-channel device. In Pulse Mode operation, the timing at this output XIV·25 1 2 3 4 5 6 7 8 9 * 0 # STORE DIAL LND PAUSE • MK5375 TIMING DIAGRAM OFF-HOOK OPERATION PULSE MODE Figure SA MANUAL DIALING ~----~~---------------11 ~f---------------------KEYPAD INPUT ROW SCAN -----mnruuumni COLUMNSCAN ~I PACIFIER TONE ____ PULSE OUTPUT ~""'~, _250 Hz_ ~ ff-f_ _ _ _ _ _ _ { 1 ---I~: f_ _ _ _ ( f f-(------------------i( ffinL_____ mnmL______---11 ,.:.-------------------11 I I s----------, ~ LJ ------~--~ I _250 Hz_ rl L...J L.J I .1 ~ ti''''''~ ~ '" ~ MK5375 TIMING DIAGRAM - I I t- _'IIlJU1J1JlJlJlJL nnnnnnnnr- hu uu uuuuu f I 1-___________________ I ~---~r ~SIG~I~~~L ..IN.G~~ jl-------------------- Lw ~..• ~",-J LL-J I· .. TONE MODE Figure 58 MANUAL DIALING AUTO - DIAL DIAL ~ KEYPAD INPUT ROW SCAN REDIAL ---lIU1JUUU1Jl1 COLUMN SCAN 250 Hz Scan I~ lflIlflJUlu.I___________ 1-________ • PACIFIER TONE _ _ _ _ _.L..__________________________~ TONE OUTPUT _ _ _ _ _ _- ' 250 Hz Scan /Ill TONE IN TONE L__2_L-_~_~r____ MUTE OUTPUT HOOKSWITCH ---lllflJlJlJU IlflJlJlJU 2_50_H..:,.Z..:..:sc..:,.an__________ ....JrtIUlJU1J I 250 Hz Scan ~L________________________________________ --------------~--~---~------~ r---J ~~?T~H I__--i CRYSTAL OSC _ _ _ _ _ _ _ _-f"llUllJJWJ.Illl....__--I\IWII1I1III1Wl1l1ll'\.____ "~~ ~--1:L XIV-26 I NORMAL DIALING The "*" (STAR) key is used as the modifier to control repertory functions. All numeric keys will signal normally unless preceded by a modifier. To signal either a "*" or "#", these keys must be entered twice in succession. The first entry is not signaled or stored. D is any data (telephone numbers) being entered or dialed. N is the address (memory location) in which numbers are stored. The number sequence stored in the LND buffer can be transferred to one of the other nine permanent locations with the simple sequence "*" followed by the address. New digits may be written into the LND buffer while on-hook. To enter either a "* " or "#" signal the digit must be entered twice in succession. PABX PAUSE (Off-Hook and On-Hook) LND PRIVACY ~ ~ ... ~ c::J ON HOOK A single " *" input prior to going on-hook or prior to coming off-hook will erase the information stored in the LND buffer. AUTO DIALING (Off-Hook) opt opt opt The key sequence " * ", followed by any digit, will autodial the number sequence stored in the designated address location while off-hook. An indefinite pause is stored in a number sequence by entering the" *" key modifier, followed by a "#" key input. When the number sequence is redialed, the dialer will pause when it encounters the" #" entry. A key input will cause it to continue. PULSE DIALING Most of the Pulse key operations are the same as they were in Tone Mode; PABX Pause is the only exception. In Pulse Mode, the pause may be stored as in tone mode, "* #", or with a single "#" input. Two "#" inputs will store two pauses. The" *" key exercises the control function; two "*" inputs will be the same as a single input (multiple inputs are not accepted.) STORAGE (On-Hook) opt opt opt II XIV-27 ABSOWTE MAXIMUM RATINGS· DC Supply Voltage V + ................................................................. 6.5 Volts Operating Temperature .......................................................... -30°C to +60°C Storage Temperature ............................................................ -55°C to +85 °C Maximum Power Dissipation (25°C) ....................................................... 500 mW Maximum Voltage on any Pin ........................................... ( V +) + 0.3; (V -) - 0.3 Volts ·Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS POWER DISSIPATION DERATING CURVE 100 200 300 400 500 DERATE AT 9 mW/oC WHEN SOLDERED INTO PC BOARD. mW ELECTRICAL SPECIFICATIONS DC CHARACTERISTICS -30°C :s; TA :s; 60°C SYM CHARACTERISTIC MIN V+ DC Operating Voltage 2.5 TYP 0.3 MAX UNIT 6.0 V 1.0 NOTES ISB Standby Current pA 1 V MR Memory Retention Voltage 1.5 1.3 V 2 'MA Memory Retention Current 750 200 nA 2 'T Operating Current (Tone) 0.5 1.0 mA 3 Ip Operating Current (Pulse) 50 150 IJ-A 3 'ML Mute Output Sink Current 1.0 3.0 mA 4 'pL Pulse Output Sink Current 1.0 3.0 mA 4 Ipc Pacifier Tone Sink/Source 250 500 IJ-A 5 KAU Keypad Pullup Resistance 100 kOHMS KAO Keypad Pulldown Resistance 500 OHMS NOTES: (All specifications are for 2.5 volt operation, unless otherwise stated. Typical values are representative values at room temperature and are not tested or guaranteed parameters.) 1. All inputs unloaded, Quiescent Mode (Oscillator off) 2. Meeting these minimum supply requirements will guarantee the rentention of data stored in memory. 3. All outputs unloaded, Single key input 4. VouT =0.5 Volts 5. Sink current for V ouT =0.5; source current for V ouT =2.0 VOLTS AC CHARACTERISTICS -- KEYPAD INPUTS, PACIFIER TONE TYP SYM CHARACTERISTIC TKO Keypad Debounce Time 32 FKS Keypad Scan Frequency 250 TAL Two Key Rollover Time FpT Frequency Pacifier Tone TpT Pacifier Tone F AC Frequency RC Oscillator MIN -5.0 NOTES: 1. Times based upon 8 kHz RC input for Rate Control 2. Deviation of oscillator frequency takes into account all voltage (2.5 to 6.0 volts), temperature (-30 0 to +60 ec), and unit-to-unit variations. The XIV-28 MAX UNIT NOTES mSEC 1 Hz 1 4 mSEC 1 500 Hz 1 30 mSEC 1 ±2.5 % 2 +5.0 tolerance of the external RC components or parasitic capacitance is not included. AC CHARACTERISTICS -- TONE MODE SYM CHARACTERISTIC TNK Tone Output No Key Down MIN TYP -13 173 -12 194 MAX UNIT NOTES -80 dBm 1 -11 218 dBm mV (RMS) 1 dB 1 To Tone Output PE Pre-emphasis, High Band V DC Average DC Bias Tone Out 1.7 DIS Output Distortion 5.0 8.0 TR Tone Signaling Rate 5 10 PSD Pre-signal Delay 132 ISD Inter-$ignal Delay 100 mSEC 2 2.7 NOTES: 1, Load = 10 kfl VOLTS % 1 1/SEC 2 mSEC 2 2, These values are directly related to the RC input to Pin 7, nominally 8 kHz, AC CHARACTERISTICS -- PULSE MODE OPERATION SYM CHARACTERISTIC TYP MIN MAX UNIT NOTES PR Pulse Rate 10 PPS 1 PDP Predigital Pause 172 mSEC 1 IDP Interdigital Pause 940 mSEC 1 T MO Mute Overlap Time 2 mSEC 1 NOTES: 1, Typical times assume nominal RC input frequency of 8 kHz, An increase in frequency results in an equal decrease in time values and an equal increase in rate values, APPLICATION CIRCUIT time intervals. The MK5375 integrated circuit provides the ability to convert keypad inputs into either DTMF or loopdisconnect signals compatible with most telephone systems. Both modes of signaling utilize loop currents to transmit the desired signaling information to the central office. DTMF signaling requires that the loop current be modulated, producing an analog signal on the telephone line. Transistor 01 modulates the loop current by amplifying the DTMF signal coupled to its base from the Tone Output. The Mute output removes the receiver and transmitter by switching transistors 02 and 03. This eliminates any interference with the DTMF signal from the transmitter and cuts down on the amplitude of the DTMF tone heard at the receiver. The timing diagram in Figure 5B illustrates the time relationship between key entries, Tone Output, and -MuteOutput. The circuit schematic in Figure 7 illustrates a typical implementation of the MK5375 dialer IC along with the necessary components required to interface with the telephone line in a tone/pulse application. In loop-disconnect signaling, each digit dialed consists of a series of momentary interruptions of loop current called "breaks" (Le., a digit "1" consists of a single break, a digit "2" consists of two breaks, and so on. The Pulse output is dedicated to loop-disconnect signaling and controls the flow of loop current through the speech network switching transistors, 04 and 05. The Mute output, through transistors 02 and 03, removes the receiver and transmitter to eliminate loud pops in the receiver caused by switching current through the network. The Pulse and Mute output signals, as shown in Figure SA, consist of make, break, and interdigital The voltage regulator circuit comprising resistor R2, zener diode Z2, and transistor 06 serves several purposes. In tone mode operation, it provides the regulated supply voltage to the MK5375 which determines the DTMF signal amplitude at the Tone Output. Varying the supply voltage will vary the DTMF output signal. In pulse mode, it helps provide some isolation from the transients caused by switching the speech network in and out. During normal off-hook dialing, the MK5375 operates XIV-29 II is unchanged from the basic tone/pulse switchable telephone described above. using current from the telephone line. On-hook number storage and memory retention current are supplied by the battery shown in Figure 7. Transistor 06 prevents the flow of battery current to the speech network. The two devices in Figure 8 are hooked up in parallel with one another except for their oscillator pins and the Chip Disable inputs. A DPDT switch is used to select between the two dialers through the Chip Disable pin; one device is activated while the other is put on standby. The rate at which .dialing occurs is determined by the values chosen for resistor R1 and capacitor C1. These values can be predetermined using equation (1.0) described above. The 3.5795 MHz crystal is used as a reference for synthesizing the DTMF signals and is activated only for the short periods during which these tones are being generated. Some applications may include a memory lock switch to prevent any of the data stored to be changed inadvertently. This memory lock switch can take the form of a locking key switch, which would allow only the person with the key to alter data stored in memory. The application circuit schematic in Figure 8 gives an example of the various features which can be utilized with the addition of several switches. The example also shows that multiple devices may be used to increase the effective storage capability of the telephone design. A scratch pad feature may be implemented to allow offhook programming of the memory while inhibiting dialing. A switch is added in series with the telephone hookswitch to allow the dialer to be forced into its on-hook key entry mode while the telephone set is off-hook. Much of the circuitry used to modulate and pulse the line, mute the speech network, and regulate the supply voltage MK5375 CIRCUIT SCHEMATIC Figure 7 R6 3.1 VOLT Zl R9 R1 RR V+ TYPICAL 2500 TYPE SPEECH NETWORK MODE PULSE 3.5795·MHZ CRYSTAL OSC1 c::::J MUTEt-12_ _ _ _ _ _ _ _+--I OSC2 OUT PT/CD 11 R4 -= PAC TONE TO RCVR OR PIEZOELECTRIC SOUNDER XIV·30 R1 R2 220K 1.6K R4 R5 R6 R7 R8 R9 R10 R11 R12 220K 1000 160K 150K 240K 3.3K 110K 560K 10K 01 02 02 03 05 06 01 Zl 2N5550 2N5550 2N6660 2N6600 2N5401 2N5550 1N914 1N4619 01 290 PF C2 68"PF C3 1"F BATTERY 3 VOLT CELL BRIDGE MK5375 APPLICATION CIRCUIT SCHEMATIC Figure 8 2N5401 R2 1.Sk 01 2N5550 Rl 220k R11 10k Cl =r.390PF 01 1N914 _ C2 ~V -=- B8tteryI100UF --=- Ie A -PULSE· HKS TONE TONE aSCl HKS -PULSE· CSCl Speech Network MK5375 OSC2 MODE ·MUTE· GND R4 220k CD T MODE -MUTE· GNO XTAL2 3.S8mHz R3 220k V Cl C2 C3 C4 C6 Rl R2 R3 R4 R5 R6 R7 R8 R' 150k 3.3k 01 luF luF 1N4001 D2-5 lN4001 2N5550 01 02 03 04 05 06 XIV-31 390pf 100uF 2N5550 2N5550 2N5401 2N2222 2N6666 XIV·32 m UNITED TECHNOLOGIES MOSTEK TELECOMMUNICATIONS PRODUCTS 10 NUMBER REPERTORY TONE/ PULSE DIALER M K5374/M K5376 FEATURES D Converts push-button inputs to both DTMF and pulse signals PIN CONNECTION Figure 2 D Stores ten 16-digit telephone numbers including last V+ 24 PULSE OUTPUT MODE SELECT 23 13KEY number dialed HKS 21 RoW1 RoW2 20 D Pacifier tone and PBX pause D Last number dialed (LND) privacy D Manual and auto-dialed digits may be cascaded D Ability to store and dial both 22 * and # DTMF signals 19 ROW3 18 ROW4 N.C. N.C. 17 RATE CONTROL 16 fmTE" OSC1 15 OSC2 11 14 PACIFIER TONE/CHIP DISABLE DTMF OUTPUT TONE LEVEL SELECT 12 13 M·B SELECT PIN CONNECTION Figure 1 V+ 18 PULSE OUTPUT MODE SELECT 17 HKS COL1 16 ROW1 COL2 15 ROW2 COIT 14 ROW3 v- 13 ROW4 RATE CONTROL 12 MUTE OSC1 11 PACIFIER TONE/CHIP DISABLE OSC2 10 DTMF OUTPUT 6 Additional functions available are a Pacifier Tone output, PABX pause, external control of the signaling rate, and total functional control with either a standard 3x4 matrix keypad (FORM-A) or a 2 of 7 keyboard. A 13th key option, available only on the MK5376, allows control of the dialer's repertory features. The telephone keypad then functions for signaling purposes only, independent of the repertory functions. This feature is important for users unfamiliar with the MK5376 special features. The dialer's flexibility provides for many applications, for example, off-hook programming, the use of additional chips in parallel for 10, 20, and 30 number repertory phones, and permanent memory protection . DESCRIPTION The MK5374 is a monolithic, integrated circuit manufactured using Mostek's Silicon Gate CMOS process. This circuit provides the necessary signals for either DTMF or loop disconnect dialing. Ten telephone numbers of up to 16 digits each may be stored in the on-chip RAM. Manual and auto-dialed numbers may be cascaded in any order. The dialer is available in two standard package sizes, an 18-pin (MK5374) and a 24-pin (MK5376) version. The MK5376 adds more flexibility to the basic MK5374 repertory dialer, making it suitable for a broader range of applications. The extra pins allow control of the tone level, choosing between a supply-independent tone level and one that is supply dependent. In addition, the 13th key mode available in the M-B (Make/Break) Ratio is user selectable. XIV-33 • XIV-34 m UNITED TECHNOLOGIES MOSTEK TELECOMMUNICATIONS PRODUCTS SINGLE NUMBER PULSE TONE SWITCHABLE DIALER M K5370/M K5371 1M K5372 PIN CONNECTION Figure 2 FEATURES o Stand-alone DTMF and pulse signaling o Softswitch automatically switches signaling mode o Recall of last number dialed (up to 28 digits long) o Flash key input initiates timed o Microprocessor hook flash interface (BCD inputs) for smart telephones o Timed PABX pause V+ 1 24 PULSE OUTPUT MODE/TEST 2 23 HKS C1/STROBE 22 R1/A C2 21 R2/B NC 10·20 PPS SELECT 5 20 M·B SELECT 6 19 MODE OUTPUT Ca 7 18 Ra/C V- 8 17 R4/D 16 MUTEl OUTPUT OSCl 9 OSC2 10 15 PACIFIER TONE/BCD MODE C4 11 14 DTMF OUTPUT HOOK FLASH TIMING 12 13 TONE LEVEL D 10/20 PPS select option o Form-A and 2-of-8 keyboard interface D Pacifier tone DESCRIPTION D Powered from telephone line, low operating voltage for long loop applications PIN CONNECTION Figure 1 18 V+ MODE/TEST C1/STROBE 3 C2 C3 16 R1/A 4 15 R2/B 5 14 R3/C V-8 OSCl PULSE OUTPUT 17 HKS 7 13 The MK5371 is a monolithic, integrated circuit manufactured under Mostek's Silicon Gate CMOS process. This circuit provides necessary signals for either DTMF or loop disconnect (Pulse) signaling. The MK5371 buffers up to 28 digits into memory that can be later redialed with a single key input. This memory capacity is sufficient for local, long distance, overseas, and even computerized long-haul networks. Users can store all 12 signaling keys and access several unique special functions with single key entries. These functions include: Last Number Dialed (LND), Softswitch (Mode), Flash, and Pause. Figure 3 shows the keypad configuration. R4/D 12 MUTEl OUTPUT OSC2 8 11 PACIFIER TONE/BCD MODE 54 9 10 DTMF OUTPUT KEYPAD CONFIGURATION Figure 3 XIV-3S FLASH 1 2 3 4 5 6 MODE 7 8 9 PAUSE * 0 # LND II The LND key input automatically redials the last number dialed. The device ignores additional key entries during autodialing. The Mode key simplifies the process of alternating dialing modes. This input automatically toggles the immediate dialing mode. The function is also stored in memory. During auto-redial, the signaling mode is toggled each time the Mode code appears in the digit sequence. The signaling mode always defaults to the mode selected (hardwire or switch) at Pin 2 (MODErrEST). Switching modes through Pin 2 toggles the immediate dialing mode and changes the default, but it is not stored in memory. Two features simplify PABX dialing. The PAUSE key stores a timed pause in the number sequence. Redial is then delayed until an outside line can be accessed or some other activity occurs before normal signaling resumes. The FLASH key simulates a hook flash to XIV-36 transfer calls or to activate other special features provided by the PABX or a central office. The MK5370/MK5371 ensures exact timing for the hook flash. In addition to interfacing with standard keypads, the MK5370/MK5371 also accepts parallel BCD inputs. This feature simplifies interfacing a microprocessorbased design to the telephone line. The MK5371 buffers 28 bytes of information, including special functions. All features are provided in an 18-pin package and also a more versatile 24-pin version, the MK5372. It includes RC programmable hook-flash timing, selectable tone levels, and the addition of both Make-Break (M-B) and 10-20 PPS select in Pulse Mode. The MK5370 is an 18-pin package that provides a continuous Mute output while signaling in Pulse Mode and a supplyindependent tone level. 1984/1985 MICROELECTRONIC DATA BOOK Tone Decoders B UNITED TECHNOLOGIES , MOSTEK TELECOMMUNICATION PRODUCTS INTEGRATED TONE DECODER MK5102(N/P/J) FEATURES o Detects all 16 standard DTMF digits o Requires minimum external parts count for minimum system cost o o MK5102 PIN OUT v+ OSCIN Uses inexpensive 3.579545 MHz crystal for reference Digital counter d~'!ection with period averaging insures minimum false response o 16-pin package for high system density o Single supply 5 Volts ± 10% o Output in either 4-bit binary code or dual 2-bit row/column code o Latched outputs The MK5102 is a monolithic integrated circuit fabricated using the complementary-symmetry MaS (CMOS) process. Using an inexpensive 3.579545 MHz television colorburst crystal for reference, the M K51 02 detects and decodes the 8 standard DTM F frequencies used in telephone dialing. The requirement of only a single supply and its construction in a 16-pin package make the MK5102 ideal for applications requiring minimum size and external parts count. XV·1 I/C 15 I/C OSC OUT 3 14 I/C STROBE 4 13 FORMAT CONTROL 5 12 6 11 I/C HIGH-GROUP INPUT LOW-GROUP INPUT 01 7 10 04 02 8 9 03 v- DESCRIPTION 2 16 MK5102 The MK5102 detects the high and low group DTMF tones after band splitting using a digital counting method. The zero crossings of the incoming tones are counted over several periods and the results averaged over a longer period. When a minimum of 33 milliseconds of a valid DTMF digit is detected, the proper data is latched into the outputs and the output strobe goes high. When a valid digit is no longer detected, the strobe Will return low and the data will remain latched into the outputs. Minimum interdigit time is 35 milliseconds. The MK5102 is designed to interface with the MK5099 Integrated Pulse Dialer with only one additional DIP Package. These two parts working together form a DTM F-to-Pulse converter that meets the recognized telephone standards. • ABSOLUTE MAXIMUM RATINGS*' DC Supply Voltage V+ (Referenced to V-) ......................... +6.0 Volts Operating Temperature ........................................ O°C to 70°C Storage Temperature ...................................... -55°C to 100°C Maximum Circuit Power Dissipation .....' ............................ 300 mW Voltage on any pin, with respect to V- ..... , ........... , ........... -0.3 Volt Voltage on any pin, with respect to V+ ............................. +0.3 Volt *Operation Above Absolute Maximum Ratings.M&v Damage The Devic/i! ELECTRICAL CHARACTERISTICS 0° C < T A < 70° C V- = 0 Volts PARAMETER Supply Voltage (V+) Lo Group & Hi Group Inputs STROBE D1, D2, D3, D4 OUTPUTS FORMAT CONTROL Input CONDITIONS MIN (V-= 0) MAX UNITS 4.5 5.5 Volts 0.9 V+ Volts Peak-to-Peak "0" Level 0.0 0.4 Volt @ 1.6 mA "1" Level "0" Level (V+)-1 0.0 V+ 0.5 Volts @ 0.1 mA Volt @ 700p.A "1" Level (V+)-0.5 V+ Volt@ 700p.A 50% Duty Cycle Square Wave Frequency Detect Band Width ± 2.0 Tone Coincidence Duration 33 Interdigit Interval Signal to Noise Ratio Supply Current @ 5.5V TYP ± 2.5 ± 2.9 NOTES 1,2 % of fo ms 4 35 ms 4 18 dB 3 Inputs and Outputs Unloaded 5 10 mA NOTES: 1. 2. Due to internal biasing, this input must be capacitively coupled with a low leakage .05 p. F capacitor. 3. SN where SA No coupling capacitor is needed if the DTMF square wave meets the following criteria: "1" LdL a. Logic "0" level = 1 Volt (max) b. Logic" 1" level = 4 Volts (min) Signal-To-Noise Ratio is defined as: NA 4. = 20 log ~~ = RMS Amplitude of single tone being detected. = RMS white noise in the band from 300Hz to 3.4KHz. Tone coincidence duration and interdigit interval measured at Highand Low-group inputs. Filter and/or limiter or comparator characteristics will affect the overall detect time. OSCILLATOR The MK5102 contains an on-board inverter with sufficient gain to provide oscillation when working with a low cost television "color burst" crystal. The inverter input is OSC IN (pin 2) and output is OSC OUT (pin 3). The circuit is designed to work with a crystal cut to 3.579545 MHz to give detection of the standard DTM F frequencies. a 4-Bit Binary Code, a Dual 2-Bit Row/Column code, or high-impedance output for use with bus-structured circuitry. This three-state input is' controlled as follows: FORMAT CONTROL.INPUT VV+ Floating FORMAT CONTROL (PIN 5) The Control pin is used to control the output format of Pins D 1 through D4. This three-state input selects XV-2 OUTPUT DATA FORMAT High Impedance 4-Bit Binary Dual 2-Bit Row/Column FORMAT CONTROL (Continued) SUGGESTED INPUT LIMITER CIRCUIT The following table describes the two output codes. Figure 2 100K!l Table 1 Dual 2-Bit Row/Column Column Row 4-Bit Binary 03 04 02 01 02 03 04 01 Digit 1 0 0 0 1 0 1 0 1 2 0 0 1 0 0 1 1 0 3 0 0 1 1 0 1 1 1 4 0 1 0 a 1 0 0 1 5 0 1 0 1 1 0 1 0 6 0 1 1 a 1 0 1 1 7 0 1 1 1 1 1 0 1 8 1 0 0 0 1 1 1 0 9 1 0 0 1 1 1 1 1 0 1 0 1 0 0 0 1 0 * # 1 0 1 1 0 a 0 1 1 1 0 a a 0 1 1 A 1 1 0 1 0 1 a 0 B 1 1 1 0 1 0 0 0 C 1 1 1 1 1 1 0 0 D 0 0 0 a 0 a a 0 HIGH GROUP FIL TER DTMF IN Figure 1 Col 2 Col 3 Col4 CD 0 IT] 0 0 0 Row 3 [?J 0 0 0 0 Row4 ~ @] (!J Row2 lKn OUTPUTS 01 THRU 04 (PINS 7 THRU 10) Outputs Dl thru D4 are CMOS push-pull when enabled and open-circuited (high impedance) when disabled by the format control pin. D 1 thru D4 are the data out I ines. The output data can be in two formats as described in the section about the format control pin (pin 5). The Dual 2-Bit Row/Column code decodes with D 1 and D2 indicating the row selected, and D3 and D4 indicating the column selected. The two output codes allow the user to obtain either 1-of-16 or 2-of-8 output data by using only a single additional package. I/C (PINS 13 THRU 16) Col 1 Row 1 MK5102 LOW GROUP FILTER Figure 1 shows the relationship between the data output code shown in Table 1 and the standard DTMF keyboard. DTMF DIALING MATRIX lKn @] @J Note: Column 4 is for special applications and is not normally used in telephone dialing. Pins 13 thru 16 are internally connected and are intended to be left floating. STROBE (Pin 4) The STROBE output goes to a "1" when 33 miliseconds ofa valid DTMF signal is detected and remains at a "1" until an interdigit interval has been detected. The data at Dl-D4 are already valid when STROBE goes to a "1" and will remain unchanged until the next DTMF digit is detected. LOW-GROUP INPUT (Pin 11) and HIGH-GROUP I NPUT (Pin 12) DETECTION FREQUENCY Table 2 Low Group fo High Group fo Row 1 = 697 Hz Column 1 = 1209 Hz Row 2 = 770 Hz Column 2 = 1336 Hz Row 3 = 852 Hz Column 3 = 1477 Hz Row 4 = 941 Hz Column 4 = 1633 Hz The low- and high-group inputs are comparators that can detect capacitively-coupled square-wave signals as small as 0.9 volts peak-to-peak. The circuitry driving these inputs would typically use back-to-back silicon diodes as symmetrical limiters to regulate this level. These inputs are biased to the midpoint of the supply with a resistive divider. Nominal input impedance is 1OOK n. XV-3 II MK5102 BLOCK DIAGRAM INPUT BAND SPLIT REQUIREMENTS J'-_OO_"--'-'-----OOl HIGH GROUP osc IN I >-f-!~I • .,.~"u". i i osc OUT LOWQROUP I 500 Hz 1000 Hz 2000 Hz 3000 Hz L .. _____.___ _ FREQUENCY RELATIVE INPUT LEVEL VS FREQUENCY NOTES: 1. Dial tone notch filter adequate to maintain SIN ratio of ~ 18dB in above pass bands. 2. Filter response described above will normally result in operation to 6dB of twist with 18dB SIN. XV·4 I _J B UNITED TECHNOLOGIES MOSTEK TELECOMMUNICATION PRODUCTS INTEGRATED TONE DECODER MK5103(N/P/J) FEATURES o o o PIN CONNECTIONS Figure 1 Detects all 16 standard DTMF digits Requires minimum external parts count for minimum system cost v+ Uses inexpensive 3.579545 MHz crystal for reference o Digital counter detection with period averaging insures minimum false response o o o 16-pin package for high system density Single supply: 5 volts ±1 0% Output in either 4-bit binary code or dual 2-bit row/column code o Will operate at 14dB SIN ratio under worst-case signal conditions o Latched outputs DESCRIPTION The MK5103 is a monolithic integrated circuit fabricated using the complementary-symmetry MOS (CMOS) process. Using an inexpensive 3.579545 MHz televisioncolor-burstcrystal for reference, the MK5103 detects and decodes the 8 standard DTMF frequencies used in telephone dialing. The requirement of only a single supply and its construction in a 16-pin package make the MK5103 ideal for applications requiring minimum size and external parts count. The MK5103 detects the high- and low-group DTMF tones after band splitting using a digital counting method. The zero crossings of the incoming tones are counted over several periods and the results averaged OSCIN 2 15 N/C OSC OUT 3 14 N/C STROBE 4 MK510313 FORMAT CONTROL 5 12 v- 6 11 D 7 10 A C 8 9 B N/C HIGH-GROUP INPUT LOW-GROUP INPUT over a longer period. When a minimum of 30 milliseconds of a valid DTMF digit is detected, the proper data is latched into the outputs and the output strobe goes high. When a valid digit is no longer detected, the strobe will return low and the data will remain latched into the outputs. Minimum interdigit time is 35 milliseconds. The M K51 03 is desig ned to interface with the M K5099 Integrated Pulse Dialer with only one additional DIP package. These two parts working together form a DTMF-to-Pulse converter that meets the recognized telephone standards. A block diagram of the MK5103 is shown in Figure 2. Functions of the individual pins are described beginning on page 2. t- f BLOCK DIAGRAM Figure 2 ~/C HIGHC INPUT j VALID TONE STROBE ~NSC II OSC OUT xv-s ABSOLUTE MAXIMUM RATINGS* DC Supply Voltage V+ (Referenced to V-) ........................................................ +6.0 Volts Operating Temperature ...................................................................... O°C to 70°C Storage Temperature ..................................................................... -55°C to 100°C Maximum Circuit Power Dissipation .............................................................. 300mW Voltage on any pin, with respect to V- ............................................................ -0.3 Volt Voltage on any pin, with respect to V+ ........................................................... +0.3 Volt· "Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ElECTR ICAl CHARACTER ISTICS O°C::5 TA :::5 70°C V- = 0 Volts PARAMETER CONDITIONS Supply Voltage (V+) (V- Lo Group & Hi Group Inputs STROBE, A, B, C, D OUTPUTS FORMAT CONTROL INPUT MIN = 0) TYP MAX UNITS 4.5 5.5 Volts 47% -·53% Duty Cycle Rectangular Wave 0.9 V+ Volts Peak-to-Peak "0" Level 0.0 0.4 Volt @ 1.6 mA "1" Level (V+)-1 V+ Volts @ 0.1 mA "0" Level 0.0 0.5 Volt @ 700JJ,A "1" Level (V+)-0.5 V+ Volt @ 700JJ,A ± Frequency Detect Band Width 2.0 ± 2.5 ± 2.9 NOTES 1,2 % offo Tone Coincidence Duration 30 ms 4 Interdigit Interval 35 ms 4 Signal-to-Noise Ratio 14 dB 3,5 Supply Current @ 5.5V Inputs and Outputs Unloaded 2 NOTES: 1. Due to internal biasing, this input must be capacitively coupled with a low-leakage 0.05 IlF capacitor. 2. 3. L::dL Signal-To-Noise Ratio is defined as: SN = 20 log ~ 4. Tone coincidence duration and interdigit interval measured at High- and Low-group inputs. Filter and/or limiter or comparator characteristics will affect the overall detect time. 5. Signal-To-Noise Ratio with 33db Filter Separation. A. Logic "0" level = 1 Volt (max) 8. Logic "1" level = 4 Volts (min) FUNCTIONAL DESCRIPTION mA where SA = RMS Amplitude of single tone being detected. NA = RMS white noise in the band from 300Hz to 304KHz. No coupling capacitor is needed if the DTMF rectangular wave meets the following criteria: "1" 5 OSCILLATOR 3.579545 MHz to give detection of the standard DTMF frequencies. FORMAT CONTROL (PIN 5) The MK5103 contains an on-board inverter with sufficient gain to provide oscillation when working with a low-cost television "color-burst" crystal. The inverter input is OSC IN (pin 2) and output is OSC OUT (pin 3). The circuit is designed to work with a crystal cut to The Control pin is used to control the output format of Pins 7 through 10. This three-state input selects a 4-bit Binary Code, a Dual 2-Bit Row/Column code, or highimpedance output for use with bus-structured circuitry. This three-state input is controlled as follows: XV-6 Table 3 shows the detection frequency associated with each row or column: FORMAT CONTROL FUNCTIONS Table 1 DETECTION FREQUENCY Table 3 FORMAT CONTROL INPUT OUTPUT DATA FORMAT vv+ High Impedance 4-Bit Binary Dual 2-Bit Row/Column Floating Low Group fo Row 1 Row 2 Row 3 Row 4 The following table describes the two output codes. 0 1 2 3 4 5 6 7 8 9 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 * # A B C D 4-Bit Binary C B A 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0 0 1 1 1 0 0 0 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 1 0 0 0 0 The Dual 2-Bit Row/Column code decodes with A and B indicating the column selected, and C and D indicating the row selected. The two output codes allow the user to obtain either 1of-16 or 2-of-8 output data by using only a single additional package. N/C (PINS 13 THRU 16) Pins 13 thru 16 are not internally connected and may be used as tie points. STROBE (PIN 4) Figure 3 shows the relationship between the data output code shown in Table 2 and the standard DTMF keyboard. DTMF DIALING MATRIX Figure 3 Col2 Col 3 Col4 Row 1 QJ [I] 0 ~ Row 2 0 IT] ~ W Row 3 [2] ~ W [£] Row4 0. [£] [!] [QJ Note: = 1209 Hz = 1336 Hz = 1477 Hz = 1633 Hz A thru D are the data out lines. The output data can be in in two formats as described in the section about the format control pin (pin 5). 1 0 1 1 0 1 1 0 1 0 1 1 0 0 0 0 Col 1 1 2 3 4 Outputs A thru D are CMOS push-pull when enabled and open-circuited (high impedance) when disabled by the format control pin. Dual2-Bit Row Column D C B A 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 Column Column Column Column OUTPUTS A THRU 0 (PINS 7 THRU 10) Table 2 Digit = 697 Hz = 770 Hz = 852 Hz = 941 Hz High Group fo The STROBE output goes to a "1" when 30 milliseconds of a valid DTMF signal is detected and remains at a "1" until an interdigit interval has been detected. The data at A-D are already valid when STROBE goes to a "1" and will remain unchanged until the next DTMF digit is detected. LOW-GROUP INPUT (PIN 11) AND HIGH-GROUP INPUT (PIN 12) The circuitry driving these inputs, as shown in Figure 4, should be squaring circuits which use resistive dividers to set the output duty cycle to 50%. The squaring circuit shown was designed to provide hysteresis and allowthe circuit to respond to signal levels of -28dBm or greater, where -28dBm corresponds to a peak-to-peak voltage of 87.1 mV. Any squaring circuit providing a 47% - 53% duty cycle over the receiver and dynamic range is sufficient. The high-group and low-group signals are provided by the high-group filter and the low-group filter, as shown in Figure 4. These filters have the response characteristics shown in Figure 5 and are used to separate the DTMF signal into its high-group and lowgroup components. Column 4 is for special applications and is not normally used in telephone dialing. XV-7 • SUGGESTED INPUT LIMITER CIRCUIT INPUT BAND SEPARATION FILTER Figure 4 Figure 5 683Hz 980 Hz 1186 Hz 1888 Hz OdS ·5dS ·10dS DTMF IN 470 MK6103 R4 ·ladS ·20dS ·26dS ·30dS ·33dS 500 Hz 470 R4 1000 Hz 2000 Hz 3000 Hz FREQUENCY RELATIVE INPUT LEVEL VS FREQUENCY NOTES: APPLICATIONS Two possible applications of the MK5103 are shown in Figure 6 and Figure 7. The dual2-bit row/column code is useful when interfacing a key-to-pulse converter, as shown in Figure 6. On this circuit, the MK5103N-5, CD4556 and MK5099 combine to form a tone-to-pulse converter, which allows the use of DTMF telephones in rotary exchanges. The DTMF tones are detected by the MK5103N-5. which then generates the corresponding row/column code. Each CD4556 then uses this 2-bit code to select 1 of 4 active-low outputs. The MK5099 then interprets these signals as a valid key closure and generates a corresponding series of pulses. TONE-TO-PULSE CONVERTER Figure 6 For simple remote-control applications, the circuit of Figure 7 is useful. After a valid tone is detected, strobe will go high and one of the 16 outputs on the binary-to1-of-16 encoder will go true. Thus, a DTMF transmitter and 16-key keyboard can be used to control 1 of 16 functions in a DTMF receiver. v+ CLASS A KEYBOARD 2 3 t::::I 3.579545MHz c:J 3.579545MHz r-., U2 MK5103 10 A 9 B 8 C 4 7 0 -= TRANSMISSION MEDIUM 10K v+ 13 R4 , P'DTSE 18 15 R2 16 R1 14 R3 Yo CD L. _ Co 4566B E a; ~~ ~: rA'---_ _ _ _ _ _ _--I 52 10U313 ~B::.-_---------I 03 98 v- xv-a 16-CHANNEL REMOTE CONTROL figure 7 CLASS A KEYBOARD v+ Formal Control t:::J 3.579546MHz V+ c::J 3.579545MHz TRANSMISSION MEDIUM ,--, 16 TONE OUT I r:- 10 A"--_ _ _, 9 B 8 C L_.J 4 7 0 STROBE 10K v+>-~~~~--------~ 10K 2N2222 *CD4514 OUTPUTS ARE ACTIVE HIGH C04515 OUTPUTS ARE ACTIVE LOW OUTPUT SELECT CHANNEL D CHANNELl CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 5 CHANNEL 6 CHANNEL 7 CHANNELS CHANNEL 9 CHANNEL 0 CHANNEL * CHANNEL # CHANNEL A CHANNEL B CHANNEL C • XV-9 XV-10 UNITED I! TECHNOLOGIES MOSTEK TELECOMMUNICATION PRODUCTS MK5102/S3525A DTMF RECEIVER SYSTEM An inexpensive DTMF receiver system with a low parts count may be constructed using the Mostek MK5102 or MK5103 Tone Decoder with the AMI S3525A Bandsplit Filter. The S3525A is an 18-pin monolithic CMOS switched-capacitor filter. It uses a 3.58 MHz crystal as a time base and has a buffered clock output to drive the oscillator of the MK51 02/3. The S3525A also has on-chip comparators which can be used to construct adjustable squaring circuits. will be well within its range.) With the potentiometer adjusted so that the filter has unity gain, the results listed in Tables 1,2, and 3 should be obtained. Tabl~s 1 and 2 show the Mitel test tape (CM7291 ) results for the DTMF receiver system using the S3525A and the MK5102 or MK5103, respectively. Table 3 shows the Minimum Tone Coincidence Duration for the system using the MK5102 and MK5103 at various input levels. The operation of the circuit shown in Figure 1 has been verified at temperatures of O°C, 25°C, and 70°C. However, Tables 1, 2, and 3 show only the data for circuit operation at 25°C. Using the circuit shown in Figure 1, the duty cycle of the signals provided to the MK51 02 should be within the 50 ± 1% range which is required for reliable operation. (Since the MK5103 requires a 50 ± 3% duty cycle, the input signals MK5102/S3525A DTMF RECEIVER SYSTEM Figure 1 +12V +5V O'~l!'F ~22!'F J'' o F N DT~ II 1 ~ 25K I 181 CKOUT FH OUT 15 Voo =r=1 !,F 0'1!'Ft 10 K HI IN FH SO 11 IN- r HI IN I~ FORMAT ~ CONTROL 20K 10 O'~i !'F 8 6BOK 9 I 12 HIGHGROUP IN 330K II T IN+ 2K 47nPF 1K FL OUT 14 II BV AEF 0.1!'F+ LO IN- FLSO 5 O.~~!'F 7 OSCIN 16 OSC OUT 17 330K II 4 Vss LO IN+ 20K 680K 6 I STROBE 4 MK5102 OR MK5103 S3525A ==1!'F 1 V+ 21 OSC IN 470pF 1K FEEDBACK V II IN 5.1 K ~ D C 11 G~060~ B STROBE 7 8 9 4-BIT BINARY OUTPUT IN 1 . 10 A 2K V6 10M 3.58 MHz -1DtXV-11 II MK5102 WITH AMI S3525A MITEL TAPE (CM7291) TEST RESULTS MK5103 WITH AMI S3525A MITEL TAPE (CM729~1 TEST RESULTS Table 1 Table 2 TEST # TEST # RESULTS RESULTS 2a, b BW = 4.6% of fa 2a,b BW = 5.0% of fa 2c, d BW = 4.9% of fa 2c,d BW = 5.1% of fa 2e, f BW = 4.7% of fa 2e, f BW = 4.9% of fa 2g, h BW = 5.0% of fa 2g, h BW = 5.2% of fa 2i, j BW = 4.8% of fa 2i,j BW = 5.1 % of fa 2k, I BW = 4.7% of fa 2k, I BW = 5.0% of fa 2m, n BW = 4.8% of fa 2m, n BW = 5.2% of fa 20, p BW = 4.7% of fa 20,p BW 3 160 decodes 4 Acceptable Amplitude Ratio 5 Dynamic Range 6 Guard Time 7 8 = 5.1 % of fo 3 160 decodes 4 Acceptable Amplitude Ratio 5 Dynamic Range 6 Guard Time 99.0% Successful Decode at SIN Ratio of 12 dB 7 99.9% Successful Decode at SIN Ratio of 12 dB 1 Hit on Talk-Off Test 8 1 Hit on Talk-Off Test = 18.2 dB = 32 dB = 34.8 ms MK51 02/3 WITH AMI S3525A MINIMUM TONE COINCIDENCE DURATION MK5102 Decode Time MK5103 Decode Time -28 dBm 43.4 ms 38.9 ms -25 dBm 37.4 ms 34.7 ms -20dBm 37.0 ms 34.7 ms -10 dBm 36.3 ms 28.8 ms OdBm 37.3 ms 28.8 ms +6 dBm 36.5 ms 28.9 ms dB = 32 dB = 32.5 ms NOTES: 1. More information regarding the S3525A is available from: American Microsystems Inc. 3800 Homestead Rd. Santa Clara, CA 95051 Telephone: (408) 246-0330 TWX: 910-338-0018 2. More information regarding the MK51 02 and MK51 03 is available from: Mostek Telecom Dept. 1215 W. Crosby Rd. Carrollton, Texas 75006 Telephone: (214) 323-1000 Table 3 Input Level dBm (60001 = 19.1 3. The AMI S3525A used in this evaluation wasa typical part. Slightly different results may be obtained depending upon the particular S3525A used. XV-12 B . UNITED TECHNOLOGIES MOSTEK TELECOMMUNICATION PRODUCTS DTMF RECEIVER SYSTEM A DTMF receiver system with a low parts count may be constructed using the MK5102 or MK5103 tone decoder and the ITT 3040A and ITT 3041 A hybrid filter!. The ITT 3040A and ITT 3041 A filters have on-chip limiters so that external squaring circuits are not needed. An alternate design allowing precise adjustment of external squaring circuits is described in another Mostek Application Note 2• Tables 1 and 2 show the MITEL (CM7290) tape results using the ITT 3040A/41 A with the MK51 02 and MK51 03, respectively. NOTES: (1) (2) ITT 3040A and ITT 3041 A filters with limiters may be obtained from: ITT North Microsystems Division 700 Hillsboro Plaza Deerfield Beach. Florida 33441 Telephone: 305-421-8450 TWX: 510-953-7523 MK51 02N-5 DTMF Decoder Application Note, "Design Considerations for a DTMF Receiver System" is available from: Mostek. Telecom Dept. 1215 W. Crosby Rd. Carrollton, Texas 75006 Telephone: 214-323-6000 Figure 1 +5V +12V ITT 4 3041A Limiter Out MK5102 or MK5103 'High-Group Filter +5V DTMF Signal In V+ ___.... Osc~2 In 12 High....----~ Group Input m 3.579545 MHz Strobe +5V +5V +12V ITT 3040A 5 Format 11 Low,...------iofGroup Input -". 4 Limiter Out • Low-Group Filter XV·13 MK5102 with ITT 3040A and ITT 3041A MITEL TAPE (CM7290) TEST RESULTS Table 1 MK5103 with ITT 3040A and ITT 3041A MITEL TAPE (CM7290) TEST RESULTS Table 2 TEST # RESULTS TEST # RESULTS 2a, b BW=4.7%of fo 2a,b BW = 5.3 % of fo 2c,d BW = 4.8 % of fo 2c,d BW = 5.2 % of fo 2e, f BW = 5.4 % of fo 2e, f BW = 5.0 % of fo 2g, h BW = 4.9 % of fo 2g, h BW 2i, j BW = 5.3 % of fo 2i, j BW = 5.6 % of fo 2k, I BW = 5.4 % of fo 2k, I BW 2m, n BW = 5.6 % of fo 2m, n BW = 5.4 % of fo 20, p BW = 4.9 % of fo 20,p BW 3 159 decodes 3 = 5.4 % of = 5.3 % of = 5.6 % of fo fo fo 159 decodes 4 Acceptable Amplitude Ratio = 19.7 dB 4 Acceptable Amplitude Ratio = 19.9 dB 5 Dynamic Range = 25 dB 5 Dynamic Range 6 Guard Time = 32.9 ms 6 Guard Time 7 99.9% Successful Decode at SIN Ratio of 12 dB 7 99.9% Successful Decode at SIN Ratio of 12 dB 8 3 Hits on Talk-Off Test 8 9 Hits on Talk-Off Test XV·14 = 30 dB = 23.3 ms m UNITED TECHNOLOGIES MOSTEK TELECOMMUNICATION PRODUCTS MK5102(N)-5 DTMF DECODER APPLICATION NOTE This application note will describe all of the requirements for building a high-quality DTMF receiver using the MK5102N-5 and hybrid filters. The following topics will be discussed: 1. 2. 3. 4. 5. 6. 7. Power supply requirements Band separation filter requirements Squaring circuit requirements Squaring circuit-to-decoder coupling requirements Receiver testing Output formatting Other system considerations Since the MK51 02N-5 is intended to be a portion of a tone receiver SYSTEM, SYSTEM requirements must be met before a satisfactory decoder can be constructed. A block diagram of a typical system is shown in Figure 1. Each portion of the block diagram is discussed in succeeding paragraphs. TYPICAL DTMF RECEIVER Figure 1 FROM TELEPHONE ments are not as stringent for the MK5102N-5 as they are for competing designs. As shown in figure 2, the MK5102N-5 requires a band separation of only 33dB in an average application. The 33dB requirement allows for a SIN ratio of 18dB, 6dB of twist, and a detection bandwidth of at least ± 2%. A reduction of twist margin or SIN requirements will result in a corresponding lower requirement for band separation. For example, if there is not a requirement for twist margin, the band separation can be reduced to 27dB. In a system with no noise and no twist, the band separation can be 22d B. The plot shown in Figure 2 depicts corner frequencies of 683Hz, 960Hz, 1184Hz and 1666Hz. These represent a 2% deviation from the DTM F frequencies of 697Hz, 941 Hz, 1209Hz and 1633Hz, respectively. This deviation is necessary because of the requirement that a DTMF receiver must detect frequencies which are 2% higher or lower than the nominal DTMF frequency. Table 1 lists the 8 DTMF frequencies and the corresponding frequencies which a DTMF decoder is required to detect. BAND SEPARATION FILTER REQUIREMENTS LINE INTERFACE Figure 2 OdS ;;; POWER SUPPLY REQUIREMENTS :5! -lOdS z ~ a: For proper operation of the MK5102N-5, the V+ power supply must be between 4.5 VDC and 5.5' VDC, with V- grounded. A power supply decoupling capaGitor (typically .1 u F) should be connected between V+ and V- to insure that no high-frequency noise is present on the V+ supply. Typically, a 1-volt peak-to-peak signal may be applied to V+ and the MK5102N-5 will function properly. ~ -20dB ~ g -3OdS ·-33dB 500 Hz 1000 Hz 1600 Hz 2000 Hz BAND SEPARATION FILTER REQUIREMENTS FILTER REQUIREMENTS NOTES: For proper operation of the MK51 02N-5, an external band separation filter must be provided to split the DTM F signal into its high-group and low-group components. However, the band separation require- 1, Dial tone notch filter must maintain SIN ratio ~ 18dB 2, Filter response shown will allow operation to 6dB of twist with 18dB SIN, XV·15 • TABLE I POSSIBLE INPUT WAVEFORMS 8 STANDARD OTMF FREQUENCIES AND CORRESPONDING UPPER AND LOWER REQUIRED DETECTION FREQUENCIES Figure 3 LOWER DETECTION DTMF FREQUENCY FREQUENCY (HZ) LIMIT (HZ) 697 770 852 941 1209 1336 1477 1633 683 755 834 922 1184 1309 1447 1600 UPPER DETECTION FREQUENCY LIMIT (HZ) 711 786 869 960 1233 1363 1507 1666 ~r--I-4-+-+--f--\--f--T-t+-If---\-f-+-f-_+_-I REJECT !-+----I-+-+-\--+-+-+-+-~\--If+_-_I--\-_+_+__.I REJECT (9) f--ll-f-+-+-+--+--+-+-+-I-t---Jf--lr-f-+-t--t--I VALID INPUT SQUARING CIRCUITS DETECTION ALGORITHM The detection approach used in, the MK51 02N-5 utilizes zero-crossing detection and digital period-counting. To increase the rejection of random noise and the residue from out-of-band components, an averaging scheme is used. Figure 3(a) shows nine cycles of a symmetrical sine wave. If zero-crossings were the only detection criteria, and if the average period-count obtained over nine periods were acceptable, then the signal in Figure 3(a) represents a valid tone. The jitter of the zero-crossings is integrated out by the nine-period average. However, based on the simple nine-period average, the signal shown in Figure 3(b) would be accepted as a valid tone. To improve rejection of this speech-type waveform, the nine-period detection time can be broken into three period-averaged sub-groups as indicated by the dashed lines in Figure 3(b). By combining the nine-period average and the sub-group average criteria, 200 false hits are obtained on 30 minutes of a standard speech tape. Figure 3(c) represents a type of waveform that would produce a hit based on the nine-period and sub-group average algorithm. To improve rejection of this wavefQrm, requirements must be placed on every single period in addition to the nine-period average and the sub-group average. However, the waveform of Figure 3(d) will be detected using only these three criteria. Therefore an additional requirement must be placed on each half-period of the waveform. Figure 3(e) shows the only type of signal which will be accepted by a detection algorithm which requires the following: 1. 2. 3. 4. f--'r-I-~--f---+-~r-+-t-+-++-T-+++--\--1 REJECT Valid nine-period average Three valid sub-group averages Valid single-period Valid half-period Using these four criteria, the number of hits on a standard speech tape can be reduced to less than six. As described above, to minimize the number of false hits, a detection algorithm must place stringent requirements on each half-period of the input waveform (high group or low group). To successfully meet these requirements, the duty cycle of the input waveform must be between 49% and 51%. The input squaring circuit must therefore provide an output which accurately tracks the input without adversely affecting the duty cycle. Such a circuit, an inverting comparator with hysteresis, is illustrated in Figure 4. INPUT SQUARING CIRCUIT Figure 4 +6 C, ~rL~~R >---1 ~"---4 >---._.. +6 R1 R2 10K 6aOK TO MK6102N·6 C1 is used to ac couple the filter output to the squaring circuit so that DC bias present at the filter output will not affect the performance of the squaring circuit. R3, R4, and R6 establish a bias level at about 2.5 Volts, and R5 is used to provide the same bias level at the inverting input of the comparator used in the squaring circuit. The maximum input bias current for the LM2901 is 500nA, so the DC bias level at the in,verting input is effectively the same' as the voltage at the wiper of R6. R6 must be adjusted so that, for an input signal level of -28dBm, the output duty cycle will be 50%. This adjustment compensates for XV·16 the input offset voltage of the LM2901. R L is the pullup resistor for the open-collector output of the comparator. R 1 and R2 set the hysteresis level. Their values are determined by the following approximate relationships: where VUT is the upper threshold VLT= (2.5-VOU (R2) (R1+R2) where VL T is the lower threshold and VOL is the output saturation voltage In both cases, any variation due to the current in R5 is ignored. For central office appl ications, the tone receiver system must operate over an input signal level range of -26dBm to +6dBm. The squaring circuit, therefore, must respond to signal levels of -26d Bm or greater but is not required to respond to lower signal levels. To allow for signal attenuation through the band separation filter, the squaring circuit should be set to respond to signal levels of -28dBm or greater. The -28dBm cutoff point corresponds to a peak-to-peak voltage of 87.1 m V. For a 50% duty-cycle output waveform, VUT should be set 43.5mV above and VLT should be set 43.5mV below the DC bias point. The passive components for the squaring circuit are then selected as follows: RL = 1kn R2 = 680kn R1 = 12kn R3 = R4 = 470n Chosen value. Chosen value. Calculated value. Chosen value for DC bias. R5 = 100kn Chosen value. Tradeoff effect on DC bias vs. drop across R5 due to 2901 input bias current. Chosen value. Must be low impedance over frequency range' of 683Hz to 1666Hz. To achieve proper operation at low signal levels, R 1 must be 10kn. The discrepancy between the calculated value and the actual required value results from component tolerances. Since many commercially-available filters exhibit a ringing characteristic at their output, as shown in Figure 5 and Figure 6, additional circuitry is required to detect the beginning of ringing and squelch the output of the squaring circuit. The 'required circuitry, an envelope detector, is shown in Figure 7. The detector consists of two precision rectifiers, two sample-andhold circuits, and a comparator. C3 is used to couple the low-group filter output to the envelope detector. Z1a, 01, C1, R2, and R3 then rectify the incoming signal and store a peak value. The R2/R3/C1 time constant is set for 20ms so that the voltage at the inverting input of Z2 will represent Y:z the peak value of the incoming signal. Z1 b, 02, R1and C2 also rectify the incoming signal and store a peak value, but the time constant is set for 1.4ms so that the voltage at the non-inverting input of Z2 will represent the instantaneous peak value of the incoming waveform. As long as the instantaneous value is greater than Y:z of the peak value, the comparator output will be high. However, as soon as the instantaneous value decreases to less than Y:z the peak value (this will occur as ringing begins), the comparator output will go low and inhibit the output of the squaring circuit. It is necessary to provide only one envelope detector since the MK5102N-5 will treat the absence of a valid lowgroup/high-group tone combination as interdigit time. LOW-GROUP FILTER RESPONSE (3044) Figure 5 DTMF INPUT TO FILTER (5V/DIV.) LOW-GROUP FILTER OUTPUT (IV/DIV.) SQUARING CIRCUIT OUTPUT (5V/DIV.) STROBE FROM MK5102N-5 (5V/DIV.) EACH TIME DIVISION = 10 MS XV·17 • HIGH-GROUP FILTER RESPONSE (3045) Figure 6 EACH TIME DIVISION = 10 ms DTMF INPUT TO FILTER (5V/DIV.) LOW-GROUP FILTER OUTPUT (lV/DIV.) SQUARING CIRCUIT OUTPUT (5V/DIV.) STROBE FROM MK5102N-5 (5V/DIV,) ENVELOPE DECAY DETECTOR Figure 7 Z1 = 1458 Z2 C3 FROM R3 15K .00/-LF = 2901 v+ LOW-GROUP~~"'-'----I '>---I~TO SQUARING FILTER CIRCUIT R1 1.5K ENVELOPE DETECTOR OPERATION Figure 8 LOW-GROUP FILTER OUTPUT (lV/DIV,) INSTANTANEOUS PEAK DETECTOR (lV/DIV.) AVERAGE PEAK DETECTOR (lV/DIV.) LOW-GROUP INPUT TO 5102N-5 (5V/DIV.) XV-18 SQUARING CIRCUIT-TO-DECODER COUPLING The output of the squaring circuit may be tied directly to the MK5102N-5 if it meets the following requirements: The peak-to-peak value of the coupled signal must be greater than .9 volts but less than V+ volts. OUTPUT SIGNALS 01, 02, 03, and 04 are the data output lines. The output format present on these pins is determined by the format control (pin 5) as snown in Table 2. Logic 1;;;a. 4 volts Logic 0 ~ 1 volt A squaring circuit with an output that does not meet these requirements must be capacitively coupled to the MK5102N-5 with a 0.05~F capacitor. The value of the coupl ing capacitor is critical because of the impedance of the bias circuit at the high-group or low-group input. As shown in Figure 9, the sudden appearance of a tone burst causes the DC bias point to shift upward. Until the DC bias returns to its normal level, the input comparator will not switch and the input signal will be ignored, causing an increase in the dual-tone detection time. Using a 0.05~F capacitor will minimize the effect of this DC level shift. FORMAT CONTROL FUNCTIONS TABLE 2 Format Control Input Data Output Format v- High ImpedancE: v+ 4-Bit Binary Floating Dual 2-Bit Row/Column SHIFT IN DC BIAS LEVEL CAUSED BY APPLICATION OF TONE BURST Figure 9 HIGH-GROUP INPUT (lV/DIV.) COUPLING CAP. = 1~F SQUARING CIRCUIT OUTPUT (IV/DIV.) Table 3 describes the two output codes available. TABLE 3 OUTPUT FORMAT Key Row Col. 1 2 3 1 1 1 1 4 2 2 2 3 3 3 4 4 4 1 2 3 4 5 6 7 8 9 0 * # A B C D 2 3 1 2 3 1 2 3 2 1 3 4 4 4 4 4-Bit Binary 01 02 03 04 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 1 Oual2-Bit Row/Column Row Column 01 02 03 04 1 1 0 1 1 1 0 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 1 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 1 1 0 1 1 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0 When all detection criteria are present, the MK5102N-5 will latch the proper data into its outputs and strobe will go high. After an interdigit time has been detected, strobe will go low, but the data will remain on 01 through 04. The dual 2-bit row/column code is useful when interfacing a key-to-pulse converter, as shown in Figure 10. On this circuit, the MK5102N-5, CD4556 and MK 5099 combine to form a tone-to-pulse converter, which allows the use of DTMF telephones in rotary exchanges. The DTMF tones are detected by the MK 5102N-5, which then generates the corresponding row/column code. Each CD4556 then uses this 2-bit code to select 1 of 4 active-low outputs. The MK5099 then interprets these signals as a valid key closure and generates a corresponding series of pulses. XV-19 • TEST CIRCUIT FOR CERMETEK AND NORTH ELECTRIC FILTERS Figure 13 +5 1J.!F FROM RECORDER +12 -12 -=- 1K 20 I NPUT OUTPUT 16 5 +5 13 V+ 18 V470 GND CH12960R3045 HIGH-GROUP FIL TER 1t~o +5 10K 600 .\1 +12 --12 = -=- CH1295 Of! 3044 LOW-GROUP FIL TER V4 STROBE 20SC. 3.58 MHzCJ 3 IN OSC. +5 OUT 1K LOW11 GROUP INPUT +5 1 470 6 HIGH-GROUP INPUT V+ -=- 1J.!F 20 INPUT OUTPUT 16 5 V+ 13 V18 GND MK5102N-5 12 1 TO EVENT COUNTER 10K _~o 15K TABLE 4 TABLE 5 MITEL TAPE TEST RESULTS FOR NORTH ELECTRIC FILTERS TEST# RESULTS MITEL TAPE TEST RESULTS FOR CERMETEK FILTERS RESULTS TEST# I 5.6 % of fo 2a, b BW= 4.7 % of fo 2a, b BW= 2c, d BW= 5.2 % of fo 2c,d BW = 5.7 % of fo 2e, f BW = 5.1 % of fo 2e, f BW= 5.0 % of fo 29, h BW= 5.1 % offo 2g, h BW = 5.3 % of fo 2i, j BW= 5.1 % of fo 2i, j BW= 5.2 % of fo 2k, I BW= 4.9 % of fo 2k, I BW= 5.0 % of fo 2m, n BW= 5.5 % of fo 2m, n BW = 5.5 % of fo 20, p BW= 5.0 % of fo 20,p BW= 3 3 159 decodes 5.0 % of fo 158decodes 4 Acceptable Amplitude Ratio =J3.1dB 4 5 Dynamic Range = 31.33 5 Dynamic Range = 6 Guard Time = 34.23 ms 6 Guard Time 7 dB 7 99.E' % Successful Decode at N/S Ratio = 33.4 31.67 dB ms 98.33 % Successful Decode at N/S Ratio of -12dbV of -12dbV 8 Acceptable Ampl itude Ratio =- 12.6dB 8 3 Hits on Talk-Off Test XV-20 3 Hits on Talk-Off Test SPECTRAL RESPONSE OF 3044 LOW-GROUP FIL TER SPECTRAL RESPONSE OF CH1295 LOW-GROUP FILTER Figure 16 Figure 14 FILTER 0 GAIN (dB) -10 FILTER 0 GAIN (dB) .10 -20 -20 -30 ·30 -40 -40 -50 ·50 -60 -60 -70 ·70 FREQUENCY (HZ) SPECTRAL RESPONSE OF 3045 HIGH·GROUP FILTER SPECTRAL RESPONSE OF CH1296 HIGH-GROUP FILTER Figure 17 Figure 15 FILTER 0 GAIN (dB) -10 FILTER 0 GAIN (dB) .10 -20 ·20 -30 ·30 -40 -40 -50 ·50 -60 ·60 -70 ·70 -80 ·80 750 950 1150 1350 1550 1750 1960 2150 2350 2550 2750 750 950 1150 1350 1550 1750 1960 2150 FREQUENCY (HZ) FREQUENCY (HZ) OTHER SYSTEM CONSIDERATIONS System noise will affect the operation of the M K51 02N-5 by causing the detection bandwidth to shrink. The instantaneous value of the low-group or high-group waveform is represented by the following approximate relationship, a = aT sin wTt + aN sin wNt, where a is the instantaneous amplitude of the overall waveform, aT is the amplitude of the hig~­ group or low-group component, and a1\1 is the amplitude of the noise. If the highly-simplified noise term (aN sin wNt) were removed, then the remaining term would represent a pure sine wave and the zero crossings of the waveform would be repeatable from cycle to cycle. All detection criteria would be present and the DTMF tone would be detected within a ± 2.0% to ± 2.9% bandwidth. However, adding the noise term introduces instantaneous amplitude variations which will effectively alter the duty cycle of the sine wave by causing the zero crossing points to jitter. If 0.5% jitter is caused by system noise, detection bandwidth will be decreased by .5%. Therefore, as the system noise level increases, the detection bandwidth will d~­ crease. As noted in the Filter Requirements paragraph, the 33dB band separation requirement allows for a SIN ratio of 18dB, with 6dB of twist, which means that the algorithm in the MK5102N-5 has been set up to provide a ± 2% minimum detection bandwidth in the presence of noise which is 18dB below the signal level and in the presence of high-group and low-group signals with an amplitude difference of 6dS. XV-21 • SUMMARY The MK5102N-5 provides a high-performance solution for DTM F detection at a lower cost than competing approaches. Band separation requirements for the MK5102N-5 are not as stringent as for competing designs, and, as was seen in the test results of Table 4 and Table 5, the MK5102N-5 provides excellent talkoff rejection. When used in conjunction with either the Cermetek or the North Electric filters, the MK5102N-5 will give the user a high-quality DTMF receiver which may be used in myriad applications. XV·22 1984/1985 MICROELECTRONIC DATA BOOK Information a) CODECs & Filters m UNITED TECHNOLOGIES MOSTEK TELECOMMUNICATIONS PRODUCTS J.t-255 LAW COMPANDING CODEC MK5116(J/N) FEATURES D ±5-Volt Power Supplies PIN CONNECTIONS Figure 1 D Low Power Dissipation - 30mW (Typ) o o o Follows the w255 Companding Law 16~+VREF ANALOG INPUT - - . 1 15'--VRE.F Synchronous or Asynchronous Operation 14~ANALOG On-chip sample and hold 12..... DIGITAL INPUT MASTER CLOCK - - . D On-Chip Offset Null Circuit Eliminates Long.:rerm Drift XMIT SYNC ---. Errors and Need for Trimming D Single 16-Pin Package o GROUND 13 .---. ANALOG OUTPUT N/C - .- 1 1 . - DIGITAL GROUND 10~ RCV CLOCK XMIT CLOCK - - . 9 ...... RCVSYNC DIGITAL OUTPUT"- Minimal External Circuity Required o Serial Data Output of 64kb/s-2.1 Mb/s at 8kHz Sampling Rate o Separate Analog and Digital Grounding Pins Reduce System Noise Problems DESCRIPTION A block diagram of a PCM system using the MK5116 is shown in Figure 2. PCM SYSTEM BLOCK DIAGRAM Figure 2 The MK5116 is a monolithic CMOS companding CODEC which contains two sections: (1) An analog-to digital converter which has a transfer characteristic conforming to the w255 companding law and (2) a digital-to-analog converter which also conforms to the w255 law. TRANSMITTER These two sections form a coder-decoder which is designed to meet the needs of the telecommunications industry for per-channel voice-frequency codecs used in telephone digital switching and transmission systems. Digital input and output are in serial format. Actual transmission and reception of 8-bit data words containing the analog information is done at a 64kb/s-2.1 Mb/s rate with analog signal sampling occurring at an 8kHz rate. A sync pulse input is provided for synchronizing transmission and reception of multi-channel information being multiplexed over a single transmission line. DIGITAL TRUNK (AI'D) FROM OTHER { CHANNELS 2 WIRE CABLE I I RECEIVER I (D/A) I I DIGITAL TRUNK I I I I L The pin configuration of the MK5116 is shown in Figure 1. XVI-1 \.~c~ E~H~N~ _ _ _ • FUNCTIONAL DESCRIPTION: (Refer to Figure 3 for a Block Diagram) XMIT SYNC, Pin 6 (Refer to Figure 10 for the Timing Diagram) MK5116 BLOCK DIAGRAM This input is synchronized with XMIT CLOCK. When XMIT SYNC goes high, the digital output is activated, and the AID conversion begins on the next positive edge of MASTER CLOCK. The conversion by MASTER CLOCK can be asynchronous with XMIT CLOCK. The serial output data is clocked out by the positive edges of XM IT CLOCK. The negative edge of XMIT SYNC causes the digital output to become three-state. XMIT SYNC may remain high longer than 8 XMIT CLOCK cycles, but must go low for at least 1 master clock before the transmission of the next digital word (refer to Figure 12). Figure 3 r-------------------------~ .-------------4r-g~~~ XMIT SYNC TRANSMIT SECTION XMIT CLOCK XMIT CLOCK, Pin 7 (Refer to Figure 10 for the Timing Diagram) MASTER CLOCK DIGITAL INPUT RCV SYNC RCV CLOCK ANALOG OUTPUT The on-Chip 8-bit output shift register of the MK5116 is unloaded at the clock rate present on this pin. Clock rates of 64kHz-2.1MHz can be used for XMIT CLOCK. The positive edge of the INTERNAL CLOCK transfers the data from the master to the slave of a master-slave flip-flop (refer to the Figure 5). If the positive edge of XMIT SYNC occurs after the positive edge of XMIT CLOCK, XMIT SYNC will determine when the first positive edge of INTERNAL CLOCK will occur. In this event, the hold time for the first clock pulse is measured from the positive edge of XMIT SYNC. RECEIVE SECTION RVC SYNC, Pin 9 (Refer to Figure 11 for the Timing Diagram) POSITIVE AND NEGATIVE REFERENCE VOLTAGES (+V +REF and -VREF) Pins 16 and 15 These inputs provide the conversion references for the digital-to-analog converters in the MK5116. +VREF and -VREF must maintain 100ppM/oC regulation over the operating temperature range. Variation of the reference directly affects system gain. ANALOG INPUT, Pin 1 Voice-frequency analog signals which are bandwidthlimited to 4kHz are input at this pin. Typically, they are then sampled at an 8kHz rate (refer to Figure 4). The analog input must remain between +VREF and -VREF for accurate conversion. The recommended input interface circuit is shown in Figure 9. MASTER CLOCK, Pin 5 This signal provides the basic timing and control signals required for all internal conversions. It does not have to be synchronized with RCV SYNC, RCV CLOCK, XMIT SYNC, or XMIT CLOCK and is not internally related to them. XVI-2 This input is synchronized with RCV CLOCK, and serial data is clocked in by RCV CLOCK. Duration of the RCV SYNC pulse is approximately 8 RCV CLOCK periods. The conversion from digital to analog starts after the negative edge of the RCV SYNC pulse (refer to Figure 4). The negative edge of RCV SYNC should occur before the 9th positive clock edge to insure that only eight bits are clocked in. RCV SYNC must stay low for 17 MASTER CLOCKS (min.) before the next digital word is to be received (refer to Figure 13). RCV CLOCK, Pin 10 (Refer to Figure 11 for Timing Diagram) The on-Chip 8-bit shift register for the MK5116 is loaded at the clock rate present on this pin. Clock rates of 64kHz-2.1MHz can be used for RCV CLOCK. Valid data should be applied to the digital input before the positive edge of the internal clock (refer to Figure 5). This set up time, tRDS, allows the data to be transferred into the MASTER of a master-slave flip-flop. A hold time, tRDH, is required to complete this transfer. If the rising edge of RCV SYNC occurs after the first rising edge of RCV CLOCK, RCV SYNC will determine when the first positive edge of INTERNAL CLOCK will occur. In this event, the set-up AID, D/A CONVERSION TIMING Figure 4 .t;----------------. __---'-1- XMIT SYNC 125/Lsec -------------~·~I -Jr- \ ...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~"'15-20/LSeC ~ SAMPLE AND HOCD\ I SAMPLE TIME ~... __- - - - - - - - '" 32 MASTER CLOCKS ENABLE SAR SAR REQUIRES ",128 MASTER CLOCKS ________________________________-J;f RCVSYNC DATA INPUT/OUTPUT TIMING Figure 5 Required For Data To Transfer From Master to Slave 200ns MK5116 XMIT Internal Clock DIGITAL OUT _______________.Jx RCV Internal Clock Valid Data l-- 200ns Required To Transfer Data From Master to Slave DIGITAL IN RCV SYNC - l k-- 50ns Required to Load Master _____ I _------------------- __--JX Valid Incoming Data and hold times for the first clock pulse should be measured from the positive edge of RCV SYNC. DIGITAL OUTPUT, Pin 8 The MK5116 output register stores the 8-bit encoded sample of the analog input. This 8-bit word is shifted out under control of XMIT SYNC and XMIT CLOCK. When XMIT SYNC is low, the DIGITAL OUTPUT is an open circuit. When XMIT SYNC is high, the state of the DIGITAL OUTPUT is determined by the value of the output bit in the serial shift register. The output is composed of a Sign Bit, 3 Chord Bits, and 4 Step Bits. The Sign Bit indicates the polarity of the analog input while the Chord and Step Bits indicate the magnitude. In the first Chord, the Step Bit has a value of O.6mV. In the second Chord, the Step Bit has a value of 1.2m\/. This doubling of the step value con- XVI-3 tinues for each of the six successive Chords. Each Chord has a specific value; and the Step Bits, 16 in each Chord, specify the displacement from that value (refer to Table 1). Thus the output, which follows the w255 law, has resolution that is proportional to the input level rather than to full scale. This provides the resolution of a 12-bit AID converter at low input levels and that of a 6-bit converter as the input approaches full scale. The transfer characteristic of the AID converter (p.-Iaw Encoder) is shown in Figure 6. DIGITAL INPUT, Pin 12 The MK5116 input register accepts the 8-bit sample of an analog value and loads it under control of RCV SYNC and RCV CLOCK. The timing diagram is shown in Figure 11. When RCV SYNC goes high, the MK5116 uses RCV • DIGITAL OUTPUT CODE wLAW Table 1 Chord Code Chord Value 1. 000 O.OmV 2. 001 10.11mV 3. 010 30.3mV 4. 011 70.8mV 5. 100 151.7mV 6. 101 313mV 7. 110 637mV 8. 111 1.284V CLOCK to clock the serial data into its input register. RCV SYNC goes low to indicate the end of serial input data. The 8 bits of the input data have the same functions described for the DIGITAL OUTPUT. The transfer characteristic of the D/A converter (Jt-Law Decoder) is shown in Figure 7. Step Value 0.613rnV 1.226mV 2.45mV 4.90mV 9.81mV 19.61mV 39.2mV 78.4mV ANALOG OUTPUT, Pin 13 EXAMPLE: 1 011 0010 = + 70.8mV + (2 x4.90mV) Sign Bit Chord Step Bits If the sign bit were a zero, then both plus signs would be changed to minus signs. 11111111 ~ 11110000 J 11100000 ~ 11010000 1 11000000 S S OFFSET NULL 1011 0000 } 1010 0000 The offset-null feature of the MK5116 eliminates long-term drift errors and conversion errors due to temperature changes by going through an offset-adjustment cycle before every conversion, thus guaranteeing accurate AID conversion for inputs near ground. There is no offset adjust of the output amplifier because the resultant DC error (VOFFSElu) will have no effect, since the output is intended to be AC-coupled to the external filter. The sign is not used to null the analog input. Therefore, for an analog input of 0 volts, the sign bit will be stable. 1001 0000 01000 0000 - - - - . ... 0000 0000 ~ 00010000 !l! 00100000 C 0011 0000 01000000 J 0101 0000 ~ 01100000 ...... I!" 01110000 ~ ..... 0111 1" 1 ANALOG INPUT (VOLTS) PERFORMANCE EVAWATION D/A CONVERTER (J.t-Law Decoder) TRANSFER CHARACTERISTIC Figure 7 J +Y OPERATION OF CODEC WITH 64kHz XMIT/RCV CLOCK FREQUENCIES XMIT/RCV SYNC must not be allowed to remain at a logic "1" state. XMIT SYNC is required to be at a logic "0" state for 1 master-clock period (min.) before the next digital word is transmitted. RCV SYNC is required to be at a logic "0" state for 17 master-olock periods (min.) before the next digital word is received (refer to Figures 12 and 13). AID CONVERTER (/L-Law Encoder) TRANSFER CHARACTERISTIC Figure 6 The analog output is in the form of voltage steps (100% duty cycle) having amplitude equal to the analog sample which was encoded. This waveform is then filtered with an external low-pass filter with sinxlx correction to recreate the sampled voice signal. , REF 1 J -2- ANALOG OUTPUT (YOLTS) """~ ~ The equipment connections shown in Figure 8 can be used to evaluate the performance of the MK5116. An analog signal provided by the HP3551A Transmission Test Set is connected to the Analog Input (Pin 1) of the MK5116. The Digital Output of the CODEC is tied back to the Digital Input, and the Analog Output is fed through a lowpass filter to the HP3551A. Remaining pins of the MK5116 are connected as follows: (1) RCV SYNC is tied to XMIT SYNC (2) XMIT CLOCK is tied to MASTER CLOCK. The signal is inverted and tied to RCV CLOCK. J 'I The following timing signals are required: ~I!I~I! lllill QOOOooCS (1) MASTER CLOCK = 1.536 MHz (2) XMIT SYNC repetition rate = 8kHz (3) XMIT SYNC width = 8 XMIT CLOCK periods - ,-A-. ~ ~ ~ ~ When all the above requirements are met, the setup of DIGITAL INPUTS XVI-4 Figure 8 permits the measurement of synchronous system performance over a wide range of analog inputs. The data register and ideal decoder provide a means of checking the encoder portion of the MK5116 independently of the decoder section. To test the system in the asynchronous mode, MASTER CLOCK should be separated from XMIT CLOCK, and MASTER CLOCK should be separated from RCV CLOCK. XMIT and RCV SYNCS are also separated. Some experimental results obtained with the MK5116 are shown in Figure 14 and Figure 15. In each case, both the measured results and the corresponding 03 Channel Bank specifications are shown. The MK5116 exceeds the requirements for Signal~to-Oistortion ratio (Figure 14) and for Gain Tracking (Figure 15). SYSTEM CHARACTERISTICS TEST CONFIGURATION Figure 8 IDEAL DECODER MK6116 t---~ANALOG INPUT ~~~;~;1-1.::..3_ _ _ _ _ _ _~c>\ I SYSTEM ENCODER ONLY I L---l I I I ,..-------, I L __ HP3661A SOUT + NOUT NOTE: The ideal decoder consists of a digital decompander and a 13-bit precision DAC. ABSOWTE MAXIMUM RATINGS DC Supply Voltage, V+ .... DC Supply Voltage, V - . Ambient Operating Temperature, TAo . Storage Temperature Package Dissipation at 25°C (Derated 9mW/oC when soldered into PCB) Digital Input .. Analog Input +VREF -VREF 0 0 0 0 0 0 • 0 0 •• • 0 0 0 0 • • 0 0 0 0 • 0 0 •• 0 • 0 0 0 0 0 0 0 0 0 0 0 ••• 0 0 0 0 0 0 0 • 0 0 0 00.000 •• 0 • 0 0 0 •• 0 • 000 •••••• 0 0 0 0 0 0 0 0 • 0 0 0 • 0 0 0 0 0 0 0 0 •• 0 0 ••••• 0 0 0 0 0 ••• 0 •• 0 0 0 • 0 0 0 0 0 0 0 0 • 0 0 0 • 0 • 0 0 0 0 0 0 •• 0 0 0 0 +6V 6V O°C to 70°C -55°C to +125°C 500mW 0.5V S VIN S V + V - S VIN S V + -Oo5Vs +VREFsV+ V- S -VREFs +Oo5V 000.00.00000. ••• 0 0 0 0 0 0 •• 0 • 0 • 0 0 0 • 0 0 0 0 0 0 0 0 0 0 0 •• 0 0 0 0 0 " • 0 0 0 0 0 0 •• 0 000 0 • 0 • 0 • 0 0 0 • 0 • 0 0 0 0 0 0 0 0 000 0 0 0 0 0 ••• 0 • 0 • 00 •• 0 0 0 0 •• 0 •• 0 0 0 •• • 0 0 0 0 • 0 0 0 0 0 0 0 • • 0 0 ••• 0 0 0 0 0 0 0 0 0 • •• 0 0 0 0 0 0 0 0 • 0 0 0 • 00000 0 0 • 0 0 0 0 0 0 0 • 0 0 0 • 0 • 0 000000. 0 0 • 0 000.00.00 0 • 0000000. 0 • 0 • 0 0 0 0 0 0 • 0 0 0 0 0 • 0 • 0 0 0 000.0000000 0 • 0 • 0 0 0 • •• 0 0 0 • 0 0 •• 0 0 0 0 ••• 0 0 0 ••• 0 •• • 0 0 0 0 0 0 • 0 .0.000. 0 0 0 0 0 0 0 0 0 •• • 0 0000. 000.0.000.0 •• 0 • 0 • 0 0 • 0 0 0 • 0 0 0 0 0 0 • 0 0 0 •• 0 0 0 0 0 0 • • 0 0 0 0 0 0 0 .' •• 0 0 0 • 0 - 0 • 0 0 0 • - • 0 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damages to the device. This is a stress rating only and functional operation of the device at these or any other condition above those Indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may effect device reliability. ELECTRICAL OPERATING CHARACTERISITCS POWER SUPPLY REQUIREMENTS SYM PARAMETER MIN TYP MAX UNITS V+ Positive Supply Voltage 4.75 5.0 5.25 V V- Negative Supply Voltage -5.25 -5.0 -4.75 V +VREF Positive Reference Voltage 2.375 2.5 2.625 V 1 -VREF Negative Reference Voltage -2.625 -2.5 -2.375 V 1 XVI-5 NOTES • TEST CONDITIONS: V+ DC CHARACTERISTICS = 5.0V, V- = -5.0V, +VREF = 2.5V, -VREF = -2.5V, TA = O°C to 70°C UNITS NOTES 2 kO 2 Analog Input Resistance NonSampling 100 MO CINA Analog Input Capacitance 150 250 pF 2 VOFFSET/1 Analog Input Offset Voltage ±1 ±8 mV 2 ROUTA Analog Output Resistance 1 10 IOUTA Analog Output Current SYM PARAMETER RINAS Analog Input Resistance During Sampling RINANS MIN 0.25 VOFFSET/O Analog Output Offset Voltage Logic Input Low Current IINLOW (VIN = 0.8V) Digital Input, Clock Input, Sync Input IINHIGH IINHIGHX TYP MAX 0.5 0 mA +20 ±850 mV ±0.1 ±10 p,A 3 Logic Input High Current (VIN = 2.4V) Digital Input, Master and RCV Clock Input, RCV Sync Input ±0.1 ±10 p,A 3 Logic Input High Current (V ln = 2.4V) TX Clock, TX Sync -.25 -0.8 mA 3 8 12 pF ±0.1 ±10 p,A 0.4 V 4 V 4 10 mA 5 5 Coo Digital Output Capacitance IDOL Digital Output Leakage Current VOUTLOW Digital Output Low Voltage VOUTHIGH Digital Output High Voltage 3.9 1+ Positive Supply Current 4 1- Negative Supply Current 2 6 mA IREF+ Positive Reference Current 4 20 p,A IREF- Negative Reference Current 4 20 p,A MIN TYP MAX UNITS 1.5 1.544 2.1 MHz 1.544 2.1 MHz AC CHARACTERISTICS (Refer to Figure 10 and Figure 11) SYM PARAMETER FM Master Clock Frequency FR, Fx PWCLK XMIT, RCV Clock Frequency 0.064 Clock Pulse Width (MASTER, XMIT, RCV) 200 t RC, tFC Clock Rise, Fall Time (MASTER, XMIT, RCV) t RS, tFS Sync Rise, Fall Time (XMIT, RCV) t OIR , tOIF Data Input Rise, Fall Time twsx , tWSR Sync Pulse Width (XMIT RCV) ns 25% of PWCLK 25% of PWCLK 25% of PW CLK _8_ Fx(FR) XVI·6 ns ns ns p,s NOTES AC CHARACTERISTICS (Refer to Figure 10 and Figure 11) SYM PARAMETER tps Sync Pulse Period (XMIT, RCV) txcs XMIT Clock-to-XMIT Sync Delay tXCSN MIN TYP MAX UNITS NOTES p.s 125 50% of tFC (tRS) ns XMIT Clock-to-XMIT Sync (Negative Edge) Delay 200 ns txss XMIT Sync Set-Up Time 200 txoo XMIT Data Delay 0 200 ns 4 txop XMIT Data Present 0 200 ns 4 tXDT XMIT Data Three State tOOF Digital Output Fall Time tOOR Digital Output Rise Time tSRC RVC Sync-to-RCV Clock Delay t RoS 6 ns 150 ns 4 50 100 ns 4 50 100 ns 4 50% of tRC (t FS) ns 6 RCV Data Set-Up Time 50 ns 7 t ROH RCV Data Hold Time 200 ns 7 tRCS RCV Clock-to-RCV Sync Delay 200 ns tRSS RCV Sync Set-Up Time 200 ns tSAO RCV Sync-to-Analog Output Delay 7 p's SLEW+ Analog Output Positive Slew Rate 1 V/I"'s SLEW- Analog Output Negative Slew Rate 1 VlfJ's DROOP Analog Output Droop Rate 25 p.V/p.s 7 AC CHARACTERISTICS (Refer to Figures 14 and 15) SYM PARAMETER MIN TYP MAX GTx Gain Tracking Transmit -.2 -.4 -1.25 0.0 ±0.1 ±0.2 +.2 +.4 +1.25 dB dB dB Analog Input=+3 to -37dBmO Analog Input=-37 to -50dBmO Analog Input =-50 to -55dBmO Relative to 0 dBmO GTR Gain Tracking Receive -.2 -.4 -1.25 0.0 ±0.1 ±0.2 ±.2 +.4 +1.25 dB dB dB Input Level =+3 to -37dBmO Input Level=-37 to -50dBmO Input Level=-50 to -55dBmO Relative to 0 dBmO GTE_E Gain Tracking End to End -.4 -.8 -2.50 0.0 ±0.1 ±0.2 +.4 +.8 +2.50 dB dB dB Analog Input=+3 to -37dBmO Analog Input=-37 to -50dBmO Analog Input=-50 to -55dBmO Relative to 0 dBmO SOX Signal to Distortion Transmit 37 31 26 dB dB dB Analog Input=O to -30dBmO Analog Input= -40dBmO Analog Input= -45dBmO SDR Signal to Distortion Receive 37 31 26 dB dB dB Input Level=O to -30dBmO Input Level = -40dBmO Input Level = -45dBmO XVI-7 UNITS TEST CONDo II AC CHARACTERISTICS (Refer to Figures 14 and 15) SYM PARAMETER SD E_E Signal to Distortion End to End MIN TYP MAX UNITS TEST CONDo Nx Idle Channel Noise Transmit 17 dBncO Analog Input=O Volts NR Idle Channel Noise Receive 0 dBncO NE-E Idle Channel Noise End to End 18 dBncO Analog Input=O Volts 35 29 24 dB dB dB Analog Input=O to -30 dBmO Analog Input= -40 dBmO Analog Input= -45 dBmO Digitallnput=O Code Digital Output to Digital Input CT RX Crosstalk Receive to Transmit -80 dB Analog In= -50 dBmO at 2600 Hz Digitallnput= 0 dBmO at 1008 Hz digital CTXR Crosstalk Transmit to Receive -80 dB Analog In=O dBmO at 1008 Hz Digital Input=O Code TLP Transmission Level Point dB 6000 +4 NOTES: 1. +VREF and -VREF must be matched within ± 1% in order to meet system requirements. 2. Sampling is accomplished by charging an internal capacitor; therefore, the designer should avoid excessive source impedance. Input-related device characteristics are derived using the Recommended Analog Input Circuit. See Figure 9. 3. When a transition from a "1" to a "0" takes place, the user must sink the "1" current until reaching the "0" level. 4. Driving 30pF with 10H = 100",A, IOL = 500",A. 5. Results in 30 mW typical power dissipation (clocks applied) under normal operating conditions. 6. This delay is necessary to avoid overlapping CLOCK and SYNC. 7. The first bit of data is loaded when the Sync and Clock are both "1" during bit time 1 as shown on RCV timing diagram. RECOMMENDED ANALOG INPUT CIRCUIT Figure 9 COOEC TYPICAL C,NA, R'NAS r SOURCE lMPEOANCE I : 1 'V I - I I I I I XVI·8 ~F 3 k -=- TRANSMITTER SECTION TIMING Figure 10 PCM DATA PRESENT NOTE: All rise and fall times are measured from O.4V and 2.4V, All delay times are measured from 1.4V, RECEIVER SECTION TIMING Figure 11 2.4V RCV SYNC 1.4V O.4V r- ----------------------------------------~\ L ANALOG OUTPUT NOTE: All rise and fall times are measured from O.4V and 2.4v' All delay times are measured from 1.4V. XVI-9 III 64kHz OPERATION, TRANSMITTER SECTION TIMING Figure 12 1~4~-------------------------------------125Msec--------------------------------------~ ~ XMITSYNC r\:\ J SIGN BIT THREE- MSB S~\INEXT WORD) L~ ______________________________ ) V PCM DATA PRESENT NOTE: All rise and fall times are measured from O.4V and 2.4V. All delay times are measured from 1.4V. 64kHz OPERATION, RECEIVER SECTION TIMING Figure 13 ~1~.- ____________________________________ 125Msec ______________________________________ I RCV SYNC ---.--J ~~~I I ~STER U ~ERIODS ~;~.~~ ~ PWCLK--~ I~ -----., r----., r----, ----.J -, RCV NOTE: All rise and fall times are measured from O.4V and 2.4V. All delay times are measured from 1.4V. MK5116 SINGLE-ENDED SIGNAL TO DISTORTION Figure 14 MK5116 SINGLE-ENDED GAIN TRACKING Figure 15 25.0 -10 -30 -40 -50 -60 INPUT LEVEL (dBmO) INPUT LEVEL (demO) XVI-10 ~(MIN) m UNITED TECHNOLOGIES MOSTEK TELECOMMUNICATION PRODUCTS J-t-255 LAW COMPANDING CODEC MK5151(J/P) FEATURES o ±5-Volt Power Supplies o Low Power Dissipation - 30mW (Typ) an 8kHz rate. A sync pulse input is provided for synchronizing transmission and reception of multichannel information being multiplexed over a single transmission line. The pin configuration of the MK5151 is shown in Figure 1. o Follows the J.L-255 Companding Law o Zero Code Suppression and Sign-Magnitude Data Format PIN CONNECTIONS Figure 1 o On-Chip Sample and Hold DIGITAL OUTPUT~ 1 XMIT CLOCK---"2 AlB SEL (XMIT)---..3 B SIGNAL IN-..4 A SIGNAL IN~5 o On-Chip Offset Null Circuit Eliminates Long-Term Drift Errors and Need for Trimming o 24-N/C 2~XMITSYNC 22-4- MASTER CLOCK 21-4-V+ 20-4-ANALOG INPUT RCV. SYNC~6 RCV. CLOCK-"7 AlB SEL. (RcV.)---..a A SIGNAL OUT.-9 Single 24-Pin Package o Minimal External Circuitry Required o Serial Data Output of 64kb/s - 2.1 Mb/s at 8kHz Sampling Rate o Separate Analog and Digital Grounding Pins Reduce System Noise Problems 19-4-+VREF 18~-VREF 17-4-ANALOG GROUND 16-N/C 15-N/C B SIGNAL OUT.-l0 DIGITAL INPUT--.ll DIGITAL GROUND---.12 , 4--'ANALOG OUTPUT , 3-4-V- A block diagram of a PCM system using the MK5151 is shown in Figure 2. DESCRIPTION The MK5151 is a monolithic CMOS companding CODEC which contains two sections: (1) An analog-todigital converter which has a transfer characteristic conforming to the J.L-255 companding law and (2) a digital-to-analog converter which also conforms to the 1-'-255 law. PCM SYSTEM BLOCK DIAGRAM Figure 2 TRAN,MlnER (A/OI 'ROM OYMEFI { CHANNELl These two sections form a coder-decoder which is designed to meet the needs of the telecommunications industry for per-channel voice-frequency codecs used in telephone digital switching and transmission systems. Digital input and output are in serial format. Actual transmission and reception of 8-bit data words containing the analog information is done at a 64kb/s2.1 Mb/s rate with analog signal sampling occuring at XVI·11 AI!CEI\fEA ID/AI DIGITAL TRUNK • FUNCTIONAL DESCRIPTION: (Refer to Figure 3 for a Block Diagram) XMIT SYNC, Pin 23 (Refer to Figure 12 for the Timing Diagram) MK5151 BLOCK DIAGRAM This input is synchronized with XMIT CLOCK. When XMIT SYNC goes high, the digital output is activilted and the AID conversion begins on the next positive edge of MASTER CLOCK. The conversion by MASTER CLOCK can be asynchronous with XMIT CLOCK. The serial output data is clocked out by the positive edges of XMIT CLOCK. The negative edge of XMIT SYNC causes the digital output to become three-state. XMIT SYNC must go low for at least 1 master clock prior to the transmission of the next digital word. (Refer to Figure 14). Figure 3 ,...-_ _ _ _ _ _ _ _ _ _ _ _ _ _--. DIGITAL OUTPUT XM IT CLOCK, Pin 2 (Refer to Figure 12 for the Timing Diagram) The on-chip 8-bit output shift register of the MK5151 is unloaded at the clock rate present on this pin. Clock rates of 64kHz -2.1 MHz can be used for XMIT CLOCK. The positive edge of the INTERNAL CLOCK transfers the data from the master to the slave of a master-slave flipflop (Refer to Figure 5). If the positive edge ofXMIT SYNC occurs after the positive edge of XMIT CLOCK, XMIT SYNC will determine when the first positive edge of INTERNAL CLOCK will occur. In this event, the hold time for the first clock pulse is measured from the positive edge of XMIT SYNC. ANALOG OUTPUT B SIG. A SIG OUT OUT POSITIVE AND NEGATIVE REFERENCE VOLTAGES (+VREF and -VREF) Pins 19 and 18 These inputs provide the conversion references for the digital-to-analog converters in the MK5151 . +VREF and -VREF must maintain 100ppM/oC regulation over the operating temperature range. Variation of the reference directly affects system gain. RCV. SYNC, Pin 6 (Refer to Figure 13 for the timing diagram) This input is synchronized with RCV. CLOCK and serial data is clocked in by RCV. CLOCK. Duration of the RCV. SYNC pulse is approximately 8 RCV. CLOCK periods. The conversion from digital-to-analog starts after the negative edge of the RCV. SYNC pulse (Refer to Figure 4). The negative edge of RCV. SYNC should occur before the 9th positive clock edge to insure that only eight bits are clocked in. RCV. SYNC must stay low for 17 MASTER CLOCKS (min.) before the next digital word is to be received (Refer to Figure 15). RCV CLOCK, Pin 7 (Refer to Figure 13 for Timing Diagram) ANALOG INPUT, Pin 20 Voice-frequency analog signals which are bandwidthlimited to 4kHz are input at this pin. Typically, they are then sampled at an 8kHz rate (Refer to Figure 4.). The analog input must remain between +VREF and -VREF for accurate conversion. The recommended input interface circuit is shown in Figure 11. MASTER CLOCK, Pin 22 This signal provides the basic timing and control signals required for all internal conversions. It does not have to be synchronized with RCV. SYNC, RCV. CLOCK, XMIT SYNC or XMIT CLOCK and is not internally related to them. The on-ch ip 8-bit sh ift reg ister for the M K5151 is loaded at the clock rate present on this pin. Clock rates of 64kHz-2.1 MHz can be used for RCV. CLOCK. Valid data should be applied to the digital input before the positive edge ofthe internal clock (Refer to Figure 5). This set up time, tRDS, allows the data to be transferred into the MASTER of a master-slave flip-flop. The positive edge of the INTERNAL CLOCK transfers the data to the SLAVE of the master-slave flip-flop. A hold time, bDH, is required to complete this transfer. If the rising edge of RCV. SYNC occurs after the first rising edge of RCV. CLOCK, RCV. SYNC will determine when the first positive edge of INTERNAL CLOCK will occur. In this XVI-12 AID, 01 A CONVERSION TIMING Figure 4 I~~"------------------------------125~SeC----------------------------~~~1 ______J7' XMITSYNC \~____________________________________________--J~ ~""'15-20~SeC~ SAMPLE AND HOLD SAMPLE TIME -------~ "'" 32 MASTER CLOCKS \1 ~-- ___________________________________ ~ 11-0.... __- - - - - - - - - - - - - - - ENABLE SAR SAR REQUIRES =128 MASTER CLOCKS ----------------------~I RCV. SYNC ____________________________________________________-JI ANALOG OUTPUT UPDATED DATA INPUT IOUTPUT TIMING Figure 5 I..200ns .1 Required For Data To Transfer From Master to Slave XMIT Internal Clock MK5151 I DIGITAL OUT --------X XMIT SYNC .---------Valid Data _ _ _ _ _ _ _ _ _J Rev. I ~ Internal Clock ~ -----..X XMIT CLOCK Required To Transfer Data '-- 200ns From Master to Slave DIGITAL IN _ RCV SYNC RCV CLOCK ..-50ns Required to Load Master Valid Incoming Data DIGITAL OUTPUT, Pin 1 while the Chord and Step Bits indicate the magnitude. In the first Chord, the Step Bit has a value of O.6mV. In the second Chord, the Step Bit has a value of 1.2mV. This doubling of the step value continues for each of the six successive Chords. The MK5151 output register stores the 8-bit encoded sample of the analog input. This 8-bit word is shifted out under control of XMIT SYNC and XMIT CLOCK. When XMIT SYNC is low, the DIGITAL OUTPUT is an open circuit. When XMIT SYNC is high, the state of the DIGITAL OUTPUT is determined by the value of the output bit in the serial shift register. The output is composed of a Sign Bit, 3 Chord Bits, and 4 Step Bits. The Sign Bit indicates the polarity of the analog input Each Chord has a specific value and the Step Bits, 16 in each Chord, specify the displacement from that value (Refer to Table 1). Thus the output, which follows the 1L-255 law, has resolution that is proportional to the input level rather than to full scale. This provides the resolution of a 12-bit AID converter at low input levels and that of a 6-bit converter as the input approaches full scale. The transfer characteristic of the AID converter (Wlaw Encoder) is shown in Figure 6. event, the set-up and hold times for the first clock pulse should be measured from the positive edge of RCV. SYNC. XVI-13 • DIGITAL OUTPUT CODE p.-LAW Table 1 1. 2. 3. 4. 5. 6. 7. 8. Chord Code 111 110 101 100 011 010 001 000 DIGITAL INPUT, Pin 11 Chord Value O.OmV 10.11 mV 30.3mV 70.8mV 151.7mV 313mV 637mV 1.284V The MK5151 input register accepts the 8-bit sample of an analog value and loads it under control of RCV. SYNC and RCV. CLOCK. The timing diagram is shown in Figure 13. When RCV. SYNC goes high, the MK5151 uses RCV. CLOCK to clock the serial data into its input register. RCV. SYNC goes low to indicate the end of serial input data. The 8 bits of the input data have the same functions described for the SERIAL OUTPUT. The transfer characteristic of the 01 A converter (p.-Iaw Decoder) is shown in Figure 7. Step Value 0.613mV 1.226mV 2.45mV 4.90mV '9.81mV 19.61 mV 39.2mV 78.4mV EXAMPLE: 1 100 1101 = +70.8mV + (2 x 4.90mV) Sign Bit Chord Step Bits If the sign bit were a zero, then both plus signs would be changed to minus signs. AID CONVERTER (p.-Law Encoder) TRANSFER CHARACTERISTIC Figure 6 '000 0000 t...-- '000" " '00' " " '0'0'" '0" III ~ 15"" ~ J , The analog output is in the form of voltage steps (100% duty cycle) having amplitude equal to the analog sample which was encoded. This waveform is then filtered with an external low-pass filter with sinxlx correction to recreate the sampled voice signal. When the 8th bit of the word is a signalling bit, it is assigned a value of Y2 step. This results in a lower system quantization error rate than would result if the bit were arbitarily set to 0 (no step) or 1 (full step). OPERATION OF CODEC WITH 64kHz XMIT IRCV. CLOCK FREQUENCIES I "" "00 " " ~ :l ---+--t-~~~i~~ RCV CLOCK RCV. SYNC, Pin 9 (Refer to Figure 11 for the Timing Diagram) RECEIVE SECTION POSITIVE AND NEGATIVE REFERENCE VOLTAGES (+VREF and -VREF) Pins 16 and 15 These inputs provide the conversion references for the digital-to-analog converters in the MK5156. +VREF and -VREF must maintain 100ppM/oC regulation over the operating temperature range. Variation of the reference directly affects system gain. ANALOG INPUT, Pin 1 Voice-frequency analog signals which are bandwidthlimited to 4kHz are input at this pin. Typically, they are then sampled at an 8kHz rate (Refer to Figure 4.). The analog input must remain between +VREF and -VREF for accurate conversion. The recommended input interface circuit is shown in Figure 9. MASTER CLOCK, Pin 5 This input is synchronized with RCV. CLOCK and serial data is clocked in by RCV. CLOCK. Duration of the RCV SYNC pulse is approximately 8 RCV. CLOCK periods. The conversion from digital-to-analog starts after the negative edge of the RCV. SYNC pulse (Refer to Figure 4). The negative edge of RCV. SYNC should occur before the 9th positive clock edge to insure that only eight bits are clocked in. RCV. SYNC must stay low for 17 MASTER CLOCKS (min.) before the next digital word is to be received (Refer to Figure 13). RCV CLOCK, Pin 10 (Refer to Figure 11 for Timing Diagram) The on-chip 8-bit shift register for the MK5156 is loaded at the clock rate present on this pin. Clock rates of 64kHz-2.1 MHz can be used for RCV. CLOCK. Valid data should be applied to the digital input before the positive edge of the internal clock (Refer to Figure 5). This set up time, tRDS, allows the data to be transferred into the MASTER of a master-slave flip-flop. The positive edge of the INTERNAL CLOCK transfers the data to the SLAVE of the master-slave flip-flop. A hold time, tRDH, is required to complete this transfer. If the rising edge of RCV. SYNC occurs after the first rising edge of RCV. CLOCK, RCV. SYNC will determine when the first positive edge of INTERNAL CLOCK will occur. In This signal provides the basic timing and control signals required for all internal conversions. It does not have to be synchronized with RCV. SYNC, RCV. CLOCK, XMIT SYNC or XMIT CLOCK and is not internally related to them. XVI-24 AID, 01 A CONVERSION TIMING Figure 4 ~~r---125J.lSeC---~~ ______~~XMITSYNC \~____________________________________________________--J~ ~=15-20J.lSeC~ ------__~ \1 SAMPLE AND HOLD SAMPLE TIME ~--------------------------------------------------~ = 32 MASTER CLOCKS ~.... ~_____________ ENABLE SAR SAR REQUIRES =128 MASTER CLOCKS -------------------~/ RCV. SYNC __________________________________________________________ -J~ ANALOG OUTPUT UPDATED DATA INPUT IOUTPUT TIMING Figure 5 I..200ns ~I XMIT Internal Clock MK5156 DIGITAL OUT ________-"x RCV Required For Data To Transfer From Master to Slave -.J I Internal Clock XMIT SYNC Valid Data '-- Required To Transfer Data 200ns From Master to Slave -~ ----~I I\. XMIT CLOCK DIGITAL IN RCV.SYNC k-50ns Required to Load Master RCV.CLOCK Valid Incoming Data this event, the set-up and hold times for the first clock pulse should be measured from the positive edge of RCV. SYNC. DIGITAL OUTPUT, Pin a The MK5156 output register stores the a-bit encoded sample of the analog input. This a-bit word is shifted out under control of XMIT SYNC and XMIT CLOCK. When XMIT SYNC is low, the DIGITAL OUTPUT is an open circuit. When XMIT SYNC is high, the state of the DIGITAL OUTPUT is determined by the value of the output bit in the serial shift register. The output is composed of a Sign Bit, 3 Chord Bits, and 4 Step Bits. The Sign Bit indicates the polarity of the analog input while the Chord and Step Bits indicate the magnitude. In the first two Chords, the Step Bit has a value of 1.2mV. In the third Chord, the Step Bit has a value of 2.4mV. This doubling of the step value continues for each of the five successive Chords. Each Chord has a specific value and the Step Bits, 16 in each Chord, specify the displacement from that value (Refer to Table 1). Thus the output, which follows the Alaw, has resolution that is proportional to the input level rather than to fu II sca Ie. This provides the resol ution of a 12-bit AID converter at low input levels and that of a 6bit converter as the input approaches full scale. The transfer characteristic of the AID converter (A-law Encoder) is shown in Figure 6. DIGITAL INPUT, Pin 12 The MK5156 input register accepts the a-bit sample of an analog value and loads it under control of RCV. SYNC and RCV. CLOCK. The timing diagram is shown in Figure 11. When RCV. SYNC goes high, the MK5156 uses RCV. CLOCK to clock the serial data into its input register. RCV. SYNC goes low to indicate the end of serial input data. The a bits of the input data have the same functions described for the DIGITAL OUTPUT. The XVI-2S • . DIGITAL OUTPUT CODE: A LAW transfer characteristic of the DI A converter (A-law Decoder) is shown in Figure 7. Table 1 1. 2. 3. 4. 5. 6. 7. 8. Chord Value O.OmV 20.1 mV 40.3mV 80.6mV 161.1mV 332mV 645mV 1.289V Chord Code 101 100 111 110 001 000 011 010 Step Value 1.221 mV 1.221 mV 2.44mV 4.88mV 9.77mV 19.53mV 39.1 mV 78.1 mV ANALOG OUTPUT, Pin 13 The analog output is in the form of voltage steps (100% duty cycle) having amplitude equal to the analog sample which was encoded. This waveform is then filtered with an external low-pass filter with sinx/x correction to recreate the sampled voice signal. OPERATION OF CODEC WITH 64kHz XMIT IRCV. CLOCK FREQUENCIES EXAMPLE: 110 0111 = +80.6mV+ (2 x 4.BBmV) 1 Sign Bit Chord Step Bits If the sign bit were a zero, then both plus signs would be changed to minus signs. AID CONVERTER (A-Law Encoder) TRANSFER CHARACTER ISTIC Figure 6 C/) I- :J Q" I- ~ ~ (,!l Q _ ....... 10101010 10100101 10110101 1000 0101 10010101 11100101 11110101 11000101 11010101} II 01010101 0100 0101 01110101 01100101 0001 0101 0000 0101 00110101 00100101 00101010 XMIT IRCV. SYNC must not be allowed to remain at a logic "1" state. XMIT SYNC is required to be at a logic "0" state for 1 master clock period (min.) before the next digital word is transmitted. RCV. SYNC is required to be at a logic "0" state for 17 master clock periods (min.) before the next digital word is received (Referto Figures 12and13). OFFSET NULL / The offset null feature of the MK5156 eliminates long-term drift errors and conversion errors due to temperature changes by going through an offset adjustment cycle before every conversion, thus guaranteeing accurate AID conversion for inputs near ground. There is no offset adjust of the output amplifier because, since the output is intended to be AC - coupled to the external filter, the resultant DC error (VOFFSET/O) will have no effect. The sign bit is not used to null the analog input. Therefore, for an analog input of 0 volts, the sign bit will be stable. I I ./ I-VREF -vREF 0 t VREF 2 tVREF -2- ANALOG INPUT (VOLTS) 01 A CONVERTER (A-Law Decoder) TRANSFER CHARACTERISTIC PERFORMANCE EVALUATION Figure 7 The equipment connections shown in Figure 8 can be used to evaluate the performance of the MK5156. An analog signal provided by the HP3552A Transmission Test Set is connected to the Analog Input (Pin 1) of the MK5156. The Digital Output of the CODEC is tied back to the Digital Input and the Analog Output is fed through a low-pass filter to the HP3552A. Remaining pins of the MK5156 are connected as follows: +VREF I +VREF I 2 / ."...~ ANALOG OUTPUT (VOLTS) ."... -~ / 2 (1) (2) J -VREF 0..- ............ .... 0 0 0 0 ~50 5 0 §§§ ~ § ill 00 o 0 o .... § § DIGITAL INPUTS .... 0 0 .... .... 0 RCV. SYNC is tied to XMIT SYNC XMIT CLOCK istiedtoMASTER CLOCK. The signal is inverted and tied to RCV. CLOCK. The following timing signals are required: 0 .... 00 ~§ (1) (2) (3) MASTER CLOCK = 1.536 MHz XMIT SYNC repetition rate = BkHz XMIT SYNC width = 8 XMIT CLOCK periods When all the above requirements are met, the setup of Figure B permits the measurement of synchronous system performance over a wide range of analog inputs. XVI·26 The data register and ideal decoder provide a means of checking the encoder portion of the MK5156 independently of the decoder section. To test the system in the asynchronous mode, MASTER CLOCK should be separated from XMIT CLOCK and MASTER CLOCK should be separated from RCV. CLOCK. XMIT CLOCK and RCV. CLOCK are separated also. Some experimental results obtained with the MK5156 are shown in Figures 14 and 15. SYSTEM CHARACTERISTICS TEST CONFIGURATION Figure 8 DIGITAL INPUT DIGITAL OUTPUT r-.-_-------,I 1.020kHz I SIGNAL SOURCE I I I I I I HP3552A IDEAL DECODER MK5156 I--_ _ ~ANALOG INPUT I ANALOG 13 OUTPUT 1 - - - = 0 - - - - - - - - - - < 1 \ SYSTEM I L 1.020 kHz NOTCH FILTER L __ ENCODER ONLY l I I FILTER L..--_ _ _ ~ J SOUT+ NOUT NOTE: The ideal decoder consists of a digital decompander and a 13-bit precision DAC. ABSOLUTE MAXIMUM RATINGS DC Supply Voltage, V+ ............................................................................... +6V DC Supply Voltage, V- .......................................................................•....... -6V Ambient Operating Temperature, TA' ..................................................•••........ O°C to 70°C Storage Temperature .................................................................... -55°C to +125°C Package Dissipation at 25°C (Derated 9mW/oC when soldered into PCB) ............................ 500mW Digital Input ............................................................................ -0.5V :5 VIN :5 V+ Analog Input .............................................................................. V-:5 VIN :5 V+ +VREF' ............................................................................. -O.5V :5 +VREF :5 V+ -VREF ............................................................................... V-:=; -VREF :=; +0.5V Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL OPERATING CHARACTERISTICS POWER SUPPLY REQUIREMENTS SYM PARAMETER MIN TYP MAX UNITS V+ Positive Supply Voltage 4.75 5.0 5.25 V V- Negative Supply Voltage -5.25 -5.0 -4.75 V +VREF Positive Reference Voltage 2.375 2.5 2.625 V 1 -VREF Negative Reference Voltage -2.625 -2.5 -2.375 V 1 XVI·27 NOTES • TEST CONDITIONS: V+ = 5.0V, VDC CHARACTERISTICS = -5.0V, + V REF = 2.5V, -VREF = -2.5V, TA =O°C to 70°C SYM PARAMETER UNITS NOTES RINAS Analog Input Resistance During Sampling 2 kO 2 RINANS Analog Input Resistance Non-Sampling 100 MO CINA Analog Input Capacitance 150 250 pF 2 VOFFSETjI Analog Input Offset Voltage ±1 ±8 mV 2 RouTA Analog Output Resistance 20 50 louTA Analog Output Current (VOFFSET/O) Analog Output Offset Voltage -200 ± 850 mV hNLOW Logic Input Low Current (VIN = 0.8V) Digital Input, Clock Input, Sync Input ± 0.1 ±10 J.LA 3 Logic Input High Current (VIN = 2.4V) Digital Input, Clock Input, Sync Input -0.25 -0.8 mA 3 8 12 pF ± 0.1 ±10 J.LA 0.4 V 4 V 4 hNHIGH MIN Coo Digital Output Capacitance IDoL Digital Output Leakage Current VOUTLOW Digital Output Low Voltage VOUTHIGH Digital Output High Voltage 0.25 TYP MAX 0.5 0 mA 3.9 1+ Positive Supply Current 4 10 mA 5 1- Negative Supply Current 2 6 mA 5 IREF+ Positive Reference Current 4 20 J.LA IREF - Negative Reference Current 4 20 J.LA MIN TYP MAX UNITS 1.5 2.048 2.1 MHz 0.064 2.048 2.1 MHz AC CHARACTER ISTICS (Refer to Figure 10 and Figure 11) SYM PARAMETER FM Master Clock Frequency FR, Fx XMIT, RCV. Clock Frequency PWCLK Clock Pulse Width (MASTER, XMIT, RCV.) tRC, tFC Clock Rise, Fall Time (MASTER, XMIT, RCV.) tRS, tFS tOIR,tOIF 200 ns Sync Rise, Fall Time (XMIT, RCV.) Data Input Rise, Fall Time 25% of PWCLK ns 25% of PW CLK ns 25% of PW CLK ns twsx, tWSR Sync Pulse Width (XMIT, RCV.) _8_ Fx(FR) J.LS tps Sync Pulse Period (XMIT, RCV.) 125 J.LS txcs XMIT Clock-to-XMIT Sync Delay tXCSN XMIT Clock-to~XMIT Sync (Negative Edge) Delay XVI-28 NOTES 50% of tFc(tRS) ns 200 ns 6 AC CHARACTERISTICS CONTINUED (Refer to Figure 10 and Figure 11) SYM PARAMETER MIN txss XMIT Sync Set-Up Time 200 MAX TYP UNITS NOTES ns txoo XMIT Data Delay 0 200 hop XMIT Data Present 0 ns 4 200 ns 4 150 flS 4 tXOT XMIT Data Three State tOOF Digital Output Fall Time 50 100 ns 4 tOOR Digital Output Rise Time 50 100 ns 4 tSRC RCV. Sync-to-RCV. Clock Delay 50% of tRC (tFS) ns 6 tROS RCV. Data Set-Up Time 50 ns 7 tROH RCV. Data Hold Time 200 ns 7 bcs RCV. Clock-to-RCV. Sync Delay 200 ns tRSS RCV. Sync Set-Up Time 200 ns tSAO RCV. Sync-to-Analog Output Delay 7 J.l.S SLEW+ Analog Output Positive Slew Rate 1 V/J.l.s SLEW- Analog Output Negative Slew Rate 1 V/J.l.s DROOP Analog Output Droop Rate 25 J.l.V/J.l.s 7 SYSTEM CHARACTERISTICS (Refer to Figures 14 and 16) SYM PARAMETER MIN TYP SID Signal-to-Distortion Ratio 35 29 24 39 34 29 GT Gain Tracking -0.4 -0.8 -2.5 ±0.1 ±0.1 ±0.2 +0.4 +0.8 +2.5 Nlc Idle Channel Noise -80 -68 TLP Transmission Level Point +4 NOTES: " +VREF and -VREF must be matched within ± , % in order to meet system requirements, 2, Sampling is accomplished by charging an internal capacitor; therefore, the designer should avoid excessive source impedance, Input related device characteristics are derived using the Recommended Analog Input Circuit. See Figure g, 3, When a transition from a "'" to a "0" takes place, the user must sink the "'" current until reaching the "0" level. 4, Driving 30pF with IOH = -'00 IJA, IOL = 500 IJA. 5, Results in 30 mW typical power dissipation (clocks applied) under normal operating conditions, 6, This delay is necessary to avoid overlapping Clock and Sync, 7, The first bit of data is loaded when Sync and Clock are both "'" during bit time' as shown on RCV, timing diagram, UNITS TEST CONDo MAX dB dB dB Analog Input=O to -30dBmO Analog Input=-40dBmO Analog,lnput=-45dmO dB dB dB Analog Input=+3 to -37dBmO Analog Input=-37 to -50dBmO Analog Input=-50 to -55dBmO dBmOp Analog Input=O Volts; note 2, dB 600n RECOMMENDED ANALOG INPUT CIRCUIT Figure 9 XVI·29 CO DEC f SOURCE ANeE I i '( ~ TYPICAL CINA, RINAS • TRANSMITTER SECTION TIMING Figure 10 PCM DATA PRESENT NOTE: All rise and fall times are measured from O.4V and 2.4V. All delay times are measured from 1.4V. RECEIVER SECTION TIMING Section 11 RCV SYNC rA~N~A7LO~G~O~U~T=P~U=T~------------------------------------------------------------------------------------~~ NOTE: All rise and fall times are measured from O.4V and 2.4V. All delay times are measured from 1.4V. XVI-30 64kHz OPERATION, TRANSMITTER SECTION TIMING Figure 12 I~.~------------------------------------125Msec------------------------------------4.~Ir----- ,r-X-M-I-T-S-Y-N-C------------------------------------------------------------, ~ ---.l - 1 I..1- U 1 MASTER ~ 14--- CLOCK PWCLK ~I I - PERIOD (MIN) ) l V PCM DATA PRESENT NOTE: All rise and fall times are measured from O.4V and 2.4V. All delay times are measured from 1.4V. 64kHz OPERATION, RECEIVER SECTION TIMING Figure 13 ~1·~------------------------------------125Msec---------------------------------------4~~I I RCV SYNC ---.--J ~ ~I I ~ 1- PWCLK r-------, ..------, 4 ~ASTER L.J CL~C~ PERIODS ~(MIN) NOTE: All rise and fall times are measured from O.4V and 2.4V. All delay times are measured from 1.4V. III XVI-31 MK5156 SID RATIO VS. INPUT LEVEL M5156 GAIN TRACKING PERFORMANCE Figure 14 Figure 15 CCITI SPECIFICATIONS INPUT LEVel (dBmO) INPUT LEVEL (dBmO) XVI-32 m UNITED TECHNOLOGIES MOSTEK TELECOMMUNICATIONS PRODUCTS COMPANDING CODEC WITH FILTERS MKS316(J) FEATURES o PIN CONNECTIONS Figure 1 Per-channel, single-chip CODEC with filters D AT&T D3/D4 and CCITT compatible o Pin-programmable wlaw/power-down o ±5 volt power supplies, ±5% Low power dissipation • 40 mW operating (typ) • .5 IlW power down (typ) o TIL/CMOS-compatible digital inputs and outputs o Gain adjust available at the transmit and receive filter stages o Synchronous or asynchronous operation D Serial data rate from 64 kb/s to 4.096 Mb/s o Separate internal analog and digital grounds reduce system noise problems D Single 16-pin package D Minimal external component count DESCRIPTION The MK5316 is a monolithic device containing a companding CODEC and PCM filters on a single chip. This device has been designed to meet the needs of the telecommunications industry for per-channel, voicefrequency CODECs and PCM filters. Both the transmit and receive sections have been incorporated into a single package with negligible loss of crosstalk immunity. Typical device applications are PBX systems, central offices, channel banks, and other telephone digital switching and transmission systems. The MK5316 transmit section is composed of an input amplifier, a band-pass filter, and a compressing AID 2 15 GS x VFxl- Vee 3 14 VFXOF Vee 4 13 VFx1e DR 5 12 POII' GRDD 6 11 Ox FSR 7 10 CLKR 8 9 FS x CLKx GRDA D On-chip voltage references o 16 VFRO converter. The operational amplifier output is available for use in an inverting gain configuration at the transmit stage. By disabling the amplifier, this output can be used as a noninverting high-impedance input to the bandpass filter. The band-pass, switched-capacitor filter provides rejection of the 50-60 Hz power line' frequency and the band-limiting required for an 8 kHz sampling system. The AID converter transforms the band-limited, voice-frequency signals into 8-bit words using one of two selectable companding laws. The encoded data is transmitted in a serial format under the control of a data clock and a frame synchronization input. The receive section of the MK5316 is composed of an expanding D/A converter and a low-pass filter. The D/A converter receives 8-bit words in a serial format under control of a data clock and a frame synchronization input. The low-pass, switched-capacitor filter smooths the voltage steps of the D/A converter and provides compensation for the sinx/x decoder response. The receive filter output may then be adjusted to system levels by use of a voltage divider network. Pin connections for the MK5316 are shown in Figure 1. XVI-33 II XVI-34 _ UNITED TECHNOLOGIES MOSTEK TELECOMMUNICATIONS PRODUCTS COMPANDING CODEC WITH FILTERS MK5320(J) FEATURES o Per-channel, single-chip CODEC with filters and receive power amplifiers o AT&T D3/04 and CCITT compatible o Pin-programmable wlaw/A-law/power-down o On-chip voltage references o ±5 volt power supplies, ±5% o Low power dissipation • 40 mW typical without power amplifiers • .5 p.W typical in power down mode o TTL/CMOS-compatible digital inputs and outputs o Gain adjust available at the transmit and receive filter stages o Synchronous or asynchronous operation o Serial data rate from 64 kb/s to 4.096 Mb/s o Separate internal analog and digital grounds reduce system noise problems o Single 20-pin 300-mil package o Minimal external component count DESCRIPTION The MK5320 is a monolithic silicon-gate CMOS device containing a companding CODEC, PCM filters, and recceive power amplifiers on a single chip. This device has been designed to meet the needs of the telecommunications industry for per-channel, voice-frequency CODECs and PCM filters. Both the transmit and receive sections have been incorporated into a single package with negligible loss of crosstalk immunity. Typical device applications are PBX systems, central offices, channel banks, and other telephone digital switching and transmission systems. The MK5320 transmit section is composed of an input amplifier, a band-pass filter, and a compressing AID PIN CONNECTIONS Figure 1 VFRO .- 1 20 .... GRDA PWRI -. 2 19-GSx PWRO+.- 3 18'- VFxl- PWRO'.- 4 17'- VFxl+ Vee -. 5 16-'VFxOF Vee -. 6 15'- VFx1e DR -. 7 14"- PD/p.-A GRDD ..... 8 13 ..... Dx FSR .... 12'- FS x CLKR .... 10 9 11'- CLKx converter. The operational amplifier output is available for use in a gain configuration at the transmit stage. By disabling the amplifier, this output can be used as a non inverting high-impedance input to the band-pass filter. The band-pass, switched-capacitor filter provides rejection of the 50-60 Hz power line frequency and the band-limiting required for an 8 kHz sampling system. The AID converter transforms the band-limited, voicefrequency signals into 8-bit words using one of two selectable companding laws. The encoded data is transmitted in a serial format under the control of a data clock and a frame synchronization input. The receive section of the MK5320 is composed of an expanding D/A converter, a low pass filter, and a differential power amplifier pair. The D/A converter receives 8-bit words in a serial format under control of a data clock and a frame synchronization input. The lowpass, switched-capacitor filter smooths the voltage steps of the D/A converter and provides compensation for the sinx/x decoder response. The receive filter output may then be adjusted to system levels by use of a voltage divider network. The differential power amplifier pair is available for use in applications requiring low-impedance drive capability. Pin connections for the MKS320 are shown in Figure 1. XVI-35 • XVI-3S I! UNITED TECHNOLOGIES MOSTEK TELECOMMUNICATIONS PRODUCTS COMPANDING CODEC WITH FILTERS MK5356(J) FEATURES o Per-channel, single-chip CODEC with filters o CCITT compatible o Pin-programmable A-Iaw/power-down o On-chip voltage references o ±5 volt power supplies, ±5% o Low power dissipation • 40 mW operating (typ) • .5 p,W power down (typ) PIN CONNECTIONS Figure 1 GRDA o TTL/CMOS-compatible digital inputs and outputs o Gain adjust available at the transmit and receive filter stages o Synchronous or asynchronous operation o Serial data rate from 64 kb/s to 4.096 Mb/s o Separate internal analog and digital grounds reduce system noise problems o Single 16-pin package o Minimal external component count DESCRIPTION The MK5356 is a monolithic device containing a companding CODEC and PCM filters on a single chip. This device has been designed to meet the needs of the telecommunications industry for per-channel, voicefrequency CODECs and PCM filters. Both the transmit and receive sections have been incorporated into a single package with negligible loss of crosstalk immunity. Typical device applications are PBX systems, central offices, channel banks, and other telephone digital switching and transmission systems. The MK5356 transmit section is composed of an input amplifier, a band-pass filter, and a compressing AID 16 GS x VFRO 2 15 VFxl- Vee 3 14 VFXO F Vee 4 13 VFx1e DR 5 12 PD/A GRDD 6 11 Ox FS R 7 10 FS x CLKR 8 9 CLKx converter. The operational amplifier output is available for use in an inverting gain configuration at the transmit stage. By disabling the amplifier, this output can be used as a noninverting high-impedance input to the bandpass filter. The band-pass, switched-capacitor filter provides rejection of the 50-60 Hz power line frequency and the band-limiting required for an a kHz sampling system. The AID converter transforms the band-limited, voice-frequency signals into a-bit words using A-law companding. The encoded data is transmitted in a serial format under the control of a data clock and a frame synchronization input. The receive section of the MK5356 is composed of an expanding D/A converter and a low pass filter. The D/A converter receives a-bit words in a serial format under control of a data clock and a frame synchronization input. The low-pass, switched-capacitor filter smooths the voltage steps of the D/A converter and provides compensation for the sinx/x decoder response. The receive filter output may then be adjusted to system levels by use of a voltage divider network. Pin connections for the MK5356 are shown in Figure 1. XVI·37 II XVI-38 m UNITED TECHNOLOGIES MOSTEK TELECOMMUNICATIONS PRODUCTS COMPANDING CODEC WITH FILTERS MK5326(J) FEATURES PIN CONNECTIONS D Per-channel, single-chip CODEC with filters and receive power amplifiers Figure 1 20 GROA PWRI 2 D Pin-programmable A-Iaw/power-down 19 GS x PWRO+ VFxl- D On-chip voltage references 3 4 18 PWRO' 17 VFxl+ Vee 5 16 VFXO F Vee 6 15 VFx1e DR 7 14 PO/A GROO 8 13 Ox FS R 9 12 FS x 10 11 CLK x D CCITI compatible VFRO D ±S volt power supplies, ±S% D Low power dissipation • 40 mW typical without power amplifiers • .5 JJ-W typical in power down mode CLKR D TTL/CMOS-compatible digital inputs and outputs D Gain adjust available at the transmit and receive filter stages D Synchronous or asynchronous operation D Serial data rate from 64 kb/s to 4.096 Mb/s D Separate internal analog and digital grounds reduce system noise problems D Single 20-pin 300-mil package D Minimal external component count DESCRIPTION The MKS326 is a monolithic silicon-gate CMOS device containing a companding CODEC, PCM filters, and recceive power amplifiers on a single chip. This device has been designed to meet the needs of the telecommunications industry for per-channel, voice-frequency CODECs and PCM filters. Both the transmit and receive sections have been incorporated into a single package with negligible loss of crosstalk immunity. Typical device applications are PBX systems, central offices, channel banks, and other telephone digital switching and transmission systems. The MKS326 transmit section is composed of an input amplifier, a band-pass filter, and a compressing AID converter. The operational amplifier output is available for use in a gain configuration at the transmit stage. By disabling the amplifier, this output can be used as a noninverting high-impedance input to the band-pass filter. The band-pass, switched-capacitor filter provides rejection of the 50-60 Hz power line frequency and the band-limiting required for an 8 kHz sampling system. The AID converter transforms the band-limited, voicefrequency signals into 8-bit words using A-Iaw companding. The encoded data is transmitted in a serial format under the control of a data clock and a frame synchronization input. The receive section of the MKS326 is composed of an expanding D/A converter, a low pass filter, and a differential power amplifier pair. The D/A converter receives 8-bit words in a serial format under control of a data clock and a frame synchronization input. The lowpass, switched-capacitor filter smooths the voltage steps of the D/A converter and provides compensation for the sinx/x decoder response. The receive filter output may then be adjusted to system levels by use of a voltage divider network. The differential power amplifier pair is available for use in applications requiring low-impedance drive capability. Pin connections for the MKS326 are shown in Figure 1. XVI-39 • XVI-40 m UNITED TECHNOLOGIES MOSTEK TELECOMMUNICATION PRODUCTS INTEGRATED PCM CODEC TECHNOLOGY UPDATE INTRODUCTION A general trend towards the conversion of voice signals to digital information is currently occurring. TDM PCM is the most popular form of digital transmission. per word are transmitted in a serial bit stream at 1.544 Mbits/sec. Each voice channel is sampled at an 8kHz rate so this signal must be bandlimited to less than 4kHz in order to prevent undesirable aliasing. Today there are several important applications for this TDM scheme: 1. A high speed digital data link between central offices to pass many conversations over one pair of wires. 2. The electronic connection of two different circuit paths. 3. Concentrators Figure 1 shows how a 1kHz input signal is sampled every 125 p.sec. At each of these sampling times, the analog information is converted into an eight-bit digital word that is later sent out in serial format at the 1.544 Mbits/sec rate. Traditionally this connection had been done by electromechanical crossreed switches. Very low "on" resistance, low crosstalk, and immunity from the large ringing or transient voltages were required. Since the electromechanical technique was deemed to be of lower reliability, an all electronic approach was desired. Electronic cross point switches were designed and built, but because the electrical requirements mentioned above are extremely difficult to meet, the results were not entirely satisfying. The digital approach obviates the analog switch problem by first performing an A to D conversion, then assigning a time slot for each voice channel. For the D3 channel bank, 24 channels of digital data of 8 bits Figure 2 shows how the 24 voice channels are time division multiplexed onto one wire (for simplicity only simplex operation is shown). Channel 1 analog information is first bandlimited to less than 4kHz, then sampled and converted to a companded digital code. This 8 bit word is serially transmitted to a multiplexer where digital information from all the other channels are assimalated. The final bit stream of 1.544mbit/sec is sent to the demultiplexer where the appropriate alphanumeric channel is connected to numeric channel. This control (selection) is done by the main computer or processor. One may see that any numeric channel could be connected to any alphanumeric channel by means of a different time slot assignment. This completes the switching in a completely digital manner. 8kHz SAMPLING SYSTEM Figure 1 XVI·41 • AID AND DI A CONVERSION TIMING Figure 4 ----125/lS-----r-1 ~I. XMITSYC n n r-_________ ~~----~~L.~~~~~~~_T_R_A_N_SM_I_T_PR_E_V_IO_U_S_SA_M_P_L_E________ I... ~ ___________ ::- 80/ls ENABLE SAR ---.r~-7 /lS RCV SYNC Fl... 1"RECEIVE NEXT SAMPLE ----------~----~ f ~7/lS 1.-- ______________________ ~ UPDATE OUTPUT ANALOG process is completed, the output of the SAR is loaded into the output buffer. The data is transmitted serially at the output clock rate during the period the XMIT SYNC is high. During the signalling frame, signalling information (SigA/SigB) is inserted into the output bit stream in place of the 8th data bit as selected by the AlB select (SMIT) input. CIRCUIT DESCRIPTION The system timing is controlled by the sequence controller which operates at master clock rate of 1.5 - 2.1 MHz. All necessary signals, e.g. and S&H, SAR clock Encode/Decode control, etc; are generated in this section. To insure proper encode operation, decode interrupt is allowed only when the internal SAR clock is I L _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ lowthus resulting in a variable (5-7 J.Ls) decode interrupt interval. The 8 to 13 bit converter gives a one-to-one translation between 8 bit companded code at its input to a 13 bit linear code at its output thus allowing the use of a linear DAC in the digital-to-analog conversion process. The 13-bit linear DAC operates on the charge distribution principal of a binary weighted capacitor ladder. As shown in Figure 5, the capacitor ladder has two sections of 7 bits (7 most significant bits) and 6 bits (6 least significant bits) connected by a 64: 1 ca~ac­ itor divider. The equivalent circuit of the two sections can be drawn as shown in Figure 6. CAPACITOR LADDER Figure 5 XVI-42 Initially S1 is connected to Vin and S2 is closed. The op. amp. is operating as a unity gain follower and its offset voltage (Voff), along with the analog input voltage, is stored on the capacitor. CAPACITOR LADDER EQUIVALENT CIRCUIT Figure 6 1.016pf rf-'--I..-----1~~DAC ~8 ~64'1 ~ 127,1 ~ -=- Then switch S2 is opened and S1 is switched to analog ground. The voltage at the inverting input of the op-amp is now Voff-Vin. Thus when the amplifier operates with S2 open it acts as a comparator with effectively zero offset and -Vin applied on its inverting input. The other end of the capacitor can now be operated as a OAC. Thus the capacitor ladder performs all the necessary functions of offset-null sample-hold as well as a DAC in the encode section of the chip. 7 ~ WnCnV r 127 n=1 WHERE OUTPUT -=- Wn = 0 or 1 for the n th bit. C n = n th bit capacitor. Vr = Reference Voltage I+Vref or -Vref) The output of the OAC can be written as: VOAC = ~ 128 [ 7 ~ + Wn Cn n=1 J 13 ~ Wn (C n/64) n=8 which is equivalent to the output of a 13 bit OAC with an equivalent output capacitance of 128pF. EXPERIMENTAL RESULTS The set up of Figure 8 was used to evaluate the chip performance. CHIP PERFORMANCE Figure 8 I n the encode section th is equ iva lent capacitor of 128pF is also employed to perform the additional function of offset-null and sample-hold as shown in Figure 7. OFFSET NULL/SAMPLE HOLD Figure 7 . Unit #1 Unit #2 XMIT 1 XMIT2 RCV 1 RCV 2 The MK5151 CODEC performance exceeds the AT& T 03 channel bank specifications. Figure 9 shows the signal-to-quantizing distortion as a function of input level. S2 Vi"l~~ Idle channel noise of 13-14dBrnCO is better than the 03 spec by 9-10dB. Gain tracking is shown in Figure 10. SIGNAL-TO-NOISE RATIO Figure 9 42 42 40 33 30 03 CHANNEL BANK SPECS 20 15 10 +10 +3 0 -10 -20 -30 INPUT LEVEL IdBmO) XVI-43 -40 -45 -50 -60 • GAIN TRACKING Figure 10 +3~d ~ 03 CHANNEL BANK SPECS ~«««(I(((((I('/((((((((((t(((( <.:l Z :;z u <1: +0.5 0 +3 -10 0 -20 -30 -0.1 -0.1 -40 -50 -55 -60 a: I- e; ;;;;;;;;;;;; 0_05 z ATA - - , 24-ADDRESS LOCAL AREA NETWORK CONTROLLER FOR ETHERNET (LANCE) ~ SERIAL INTERFACE ADAPTER (SIA) ~ 8 TRANSCIEVER CABLE POWER ~ LOCAL MEMORY NETWORK INTERFACE MODULE XVII-4 ETHERNET NETWORK CABLE FUNCTIONAL DESCRIPTION SERIAL DATA HANDLING LANCE provides the Ethernet interface as follows. In the transmit mode (since there is only one transmission path, Ethernet is a half duplex system), the LANCE reads data from a transmit buffer by using Direct Memory Access (DMA) and appends the preamble, sync pattern (two ones after alternating ones and zeros in the preamble), and calculates and appends the complement of the 32-bit CRC. In the receive mode, the destination address, source address, type, data, and CRC fields are transferred to memory via DMA cycles. The CRC is calculated as data and transmitted CRC is received. At the end of the packet, if this calculated CRC does not agree with a constant, an error bit is set and an interrupt is generated to the microprocessor. In the receive mode, LANCE accepts packets under four modes of operation. The first mode is a full comparison of the 48-bit destination address in the packet with the node address that was programmed into the LANCE during an initialization cycle. There are two types of logical addresses. One is a group type mask where the 48-bit address in the packet is put through a hash filter in order to map the 48-bit physical addresses into 1 of 64 logical groups. This mode can be useful if sending packets to all of one type of a device simultaneously on the network. (Le., send a packet to all file servers or all printer servers). The second logical address is a multicast address where all nodes on the network receive the packet. The last receive mode of operation is the so called "promiscuous mode" in which a node will accept all packets on the coax regardless of their destination address. COLLISION DETECTION AND IMPLEMENTATION The Ethernet CSMAlCD network access algorithm is implemented completely within the LANCE. In addition to listening for a clear network cable before transmitting, Ethernet handles collisions in a predetermined way. Should two transmitters attempt to seize the network cable at the same time, they will collide, and the data on the network cable will be garbled. LANCE is constantly monitoring the CLSN (Collision) pin. This signal is generated by the transceiver when the signal level on the network cable indicates the presence of signals from two or more transmitters. If LANCE is transmitting when CLSN is asserted, it will continue to transmit the preamble, (normally collisions will occur while the preamble is being transmitted) then will "jam" the network for 32 bit times (3.2 microseconds). This jamming ensures that all nodes have enough time to detect the collision. The transmitting nodes then delay a random amount of time according to the "truncated binary backoff" algorithm defined in the Ethernet specification to minimize the probability of the colliding nodes having multiple collisions with each other. After 16 abortive attempts to transmit a packet, LANCE will report a RTRY error due to ex- cessive collisions and step over the transmitter buffer. During reception, the detection of a collision causes that reception to be aborted. Depending on when the collision occurred, LANCE will treat this packet as an error packet if the packet has an address mismatch, as a runt packet (a packet that has less than 64 bytes), or as a legal length packet with a CRC error. Extensive error reporting is provided by the LANCE through a microprocessor interrupt and error bits in a status register. The following are the significant error conditions: CRC error on received data; transmitter on longer than 1518 bytes; missed packet error (meaning a packet on the network cable was missed because there were no empty buffers in memory), and memory error, in which the memory did not respond (handshake) to a memory cycle request. BUFFER MANAGEMENT A key feature of the LANCE and its DMA channel is the flexibility and speed of communication between the LANCE and the host microprocessor through common memory locations. The basic organization of the buffer management is a circular queue of tasks in memory called descriptor rings, as shown in Figure 4. Separate descriptor rings describe either transmit or receive operations. Up to 128 tasks may be queued on a descriptor ring for execution by the LANCE. Each entry in a descriptor ring holds a pointer to a data memory buffer and an entry for the data buffer length. Data buffers can be chained or cascaded to handle a long packet in multiple data buffer areas. The LANCE searches the descriptor rings to determine the next empty buffer. This enables it to chain buffers together or to handle back-to-back packets. As each buffer is filled, an "own" bit is reset, signaling the host processor to empty this buffer. MICROPROCESSOR INTERFACE The parallel interface of the LANCE has been designed to be "friendly" or easy to interface to many popular 16-bit microprocessors. These microprocessors include the following: MK68000, Z8000, 8086, LSI-11, T-11, and MK68200. (The MK68200 is a 16-bit single chip microcomputer being sampled by Mostek with an architecture modeled after the MK68000). The LANCE has a wide 24-bit linear address space when it is in the Bus Master Mode, allowing it to DMA directly into the entire address space of the above microprocessors. The LANCE uses no segmentation or paging methods and as such the addressing is closest to MK68000 addressing. However, it is compatible with the others. When the LANCE is a Bus Master, a programmable mode of operation allows byte addressing either by employing a BytelWord control signal, much like that used on the 8086 or the Z8000, or by using an Upper Data Strobe/Lower Data Strobe much like that used on the MK68000, LSI-11 and MK68200 microprocessors. A programmable polarity on XVII-5 • microprocessor. the Address Strobe signal eliminates the need for external logic. LANCE interfaces with multiplexed and demultiplexed data busses and features control signals for address/data bus transceivers. The cause of the interrupt is ascertained by reading CSRO. Bit (06) of CSRO, INEA, enables or disables interrupts to the microprocessor. In a polling mode, BIT (07) of CSRO is sampled to determine when an interrupt causing condition occurred. After the initialization routine, packet reception and transmission, transmitter timeout error, a missed packet, and memory error, LANCE generates interrupts to the LANCE MEMORY MANAGEMENT Figure 4 LANCE CSR REGISTERS rl POINTER TO INITIALIZATION BLOCK RECEIVE BUFFER I _~R_EC_E_IV_E_D_E_S_C_RI_PT_O_R_R_I_NG_S_ _.......,~ PA~~~~ 0 V/J--------I r:;~ ADDRESS OF RECEIVE BUFFER 0 ~~ BUFFER r:~ BUFFER 0 BYTE COUNT r;::: ~/ ~ [;:?' MODE OF OPERATION ~;; PHYSICAL ADDRESS .•: . r:: -::1""-----;:;------L__------.-.-.--1 LOGICAL ADDRESS FILTER i'" ~~ t::::;v -~ POINTER TO RECEIVE RINGS NUMBER OF RECEIVE ENTRIES POINTER TO TRANSMIT RINGS DATA PACKET 1 1 ~;; INITIALIZATION BLOCK oSTATUS - ~---------~ ~ N DATA PACKET N ~ TRANSMIT DESCRIPTOR RINGS NUMBER OF TRANSMIT ENTRIES TRANSMIT BUFFER ""'~DATA PACKET 0 VV /V ~ ADDRESS OF TRANSMIT BUFFERS 0 ~ BUFFER 0 STATUS ~ BUFFER 0 BYTE COUNT ~ @§ ~ 1 : - -- DATA PACKET 1 • §§--+-----: ~ : -----I ~ N -----_-....--.IIo..r-· .., P~~~~T N XVII-6 LANCE INTERFACE DESCRIPTION the bus transceivers. DALI signals to strobe data toward the LANCE and DALO signals to strobe data or addresses away from the LANCE. During a read cycle, DALO goes inactive before DALI goes active to avoid "spiking" of bus transceivers. ALE, DAS and READY time all data transfers from the LANCE in the Bus Master mode. The automatic adjustment of the LANCE cycle by the READY signal allows synchronization with variable cycle time memory due either to memory refresh or to dual port access. Bus cycles are a minimum of SOO ns long and can be increased in 100 ns increments. WRITE SEQUENCE READ SEQUENCE At the beginning of a read cycle, valid addresses are placed on DALOO-DAL15 and A1S-A21. The BYTE Mask signals (BMO and BM'1) become valid at the beginning of this cycle as does READ, indicating the type of cycle. The trailing edge of ALE or AS strobes the addresses AO-A15 into the external latches. Approximately 100 ns later, DALOO-DAL15 go into a tri-state mode. There is a 50 ns delay to allow for transceiver turnaround, then DAS falls low to signal the beginning of the data portion of the cycle. At this point in the cycle, the LANCE stalls waiting for the memory device to assert READY. Upon assertion of READY, DAS makes a transition from a zero to a one, latching memory data. (DAS is low for a minimum of 200 ns). The write cycle begins exactly like a read cycle with the READ line remaining inactive. After ALE or AS pulse, the DALOO-DAL15 change from addresses to data. DAS goes active when the DALOO-DAL15 are stable. This data remains valid on the bus until the memory device asserts READY. At this point, DAS goes inactive, latching data into the mem~device. Data is held for 75 ns after the negation of DAS. LANCE INTERFACE DESCRIPTION MODE BUS SLAVE The LANCE enters the Bus Slave Mode whenever CS becomes active. This mode must be entered whenever writing or reading the four status control registers (CSRO, CSR1, CSR2, and CSR3) and the register address pointer (RAP). RAP and CSRO may be read or written to at any time, but the LANCE must be stopped for CSR1, CSR2, and CSR3 to be written to. The bus transceiver controls, DALI and DALO, control XVII-7 • MK68590 ELECTRICAL SPECIFICATION ABSOWTE MAXIMUM RATINGS Temperature Under Bias ....................................................... -25°C to +100°C Storage Temperatu re. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................ - 65°C to + 150°C Voltage on Any Pin with Respect to Ground ........................................... - 7 V to + 7 V Power Dissipation ....................................................................... 2.0 W Stresses above those listed under ''Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC CHARACTERISTICS TA =O°C to 70°C, Vee = +5 V ± 5% unless otherwise specified. SYMBOL PARAMETER VIL VIH VOL @ IOL = 3.2 mA VOH @ IOH = -0.4 mA IlL @ Vin = 0.4 to Vee MAX UNITS -0.5 +0.8 V +2.0 Vee +0.5 V +0.5 V MIN V +2.4 ±10 p,A MAX UNITS 10 pf COUT 10 pf CIO 20 pf CAPACITANCE F=1 MHz SYMBOL PARAMETER MIN CIN AC TIMING SPECIFICATIONS TA = O°C to 70°C, Vee = +5 V± 5% unless otherwise specified. # SIGNAL SYMBOL PARAMETER TEST CONDITIONS MIN ns TYP ns MAX ns 1 TCLK TlCT TCLK period 99 101 2 TCLK TlCL TCLK low time 45 55 3 TCLK TlCH TCLK high time 45 55 4 TCLK TlCR Rise time of TCLK 0 8 5 TCLK TlCF Fall time of TCLK 0 8 6 TENA TTEP TENA propagation delay after the rising edge of TCLK CL = 50 pf 7 TENA TTEH TENA hold time after the rising edge of TCLK CL = 50 pf XVII-8 95 5 AC TIMING SPECIFICATIONS (CONTINUED) TA = O°C to 70°C, VCC = +5 V ± 5% unless otherwise specified. MIN ns TYP ns MAX ns # SIGNAL SYMBOL PARAMETER TEST CONDITIONS 8 TX TTDP TX data propagation delay after the rising edge of TCLK CL=50 pf 9 TX TTDH TX data hold time after the rising edge of TCLK CL=50 pf 10 RCLK TRCT' RCLK period 85 11 RCLK TRCH RCLK high time 38 12 RCLK TRCL TRCR RCLK low time 38 Rise time of RCLK 0 8 Fall time of RCLK 0 8 13 RCLK 14 RCLK TRCF 95 5 118 AX TROR RX data rise time 0 8 16 RX RX data fall time 0 8 17 RX TROF TROH RX data hold time (RCLK to RX data change) 5 18 RX TROS RX data setup time (RX data stable to the rising edge of RCLK) 60 19 RENA 20 CLSN TOPL TCPH 21 15 RENA low time 120 CLSN high time 80 TOOFF Bus master driver disable after rising edge of HOLD 0 50 22 AlDAL TOON Bus master driver enable after falling edge of HLDA 0 150 23 HLDA THHA Delay to falling edge of HLDA from falling edge of HOLD (Bus master) 0 24 RESET AlDAL TRW RESET pulse width low 200 25 AlDAL TevCLE Readlwrite, address/data cycle time 600 26 A TXAS Address setup time to the falling edge of ALE 75 27 A TXAH Address hold time after the rising edge of DAS 35 28 DAL TAS Address setup time to the falling edge of ALE 75 29 DAL TAH Address hold time after the falling edge of ALE 35 30 DAL TROAS Data setup time to the rising edge of DAS (Bus master read) 50 XVII-9 II AC TIMING SPECIFICATIONS (CONTINUED) TA = O°C to 70°C, Vee = +5 V± 5% unless otherwise specified. TEST CONDITIONS MIN ns TYP ns # SIGNAL SYMBOL PARAMETER 31 DAL T AOAH Data hold time after the rising edge of DAS (Bus master read) 0 32 DAL TOOAS Data setup time to the falling edge of DAS (Bus master write) 0 33 DAL Twos Data setup time to the rising edge of DAS (Bus master write) 200 34 DAL TWOH Data hold time after the rising edge of DAS (Bus slave read) 35 35 DAL TS001 Data driver delay after the falling edge of DAS (CSR 0,3, RAP) (Bus slave read) 400 36 DAL TS002 Data driver delay after the falling edge of DAS (CSR 1,2) (Bus slave read) 1200 :r1 DAL T SAOH Data hold time after the rising edge of DAS (Bus slave read) 0 38 DAL TSWOH Data setup time to the falling edge of DAS (Bus slave write) 0 39 DAL Tswos Data setup time to the falling edge of DAS (Bus slave write) 0 40 ALE TALEW ALE width high 130 41 ALE TDALE Delay from rising edge of DAS to the rising edge of ALE 70 42 DAS Tosw DAS width low 200 43 DAS TAOAS Delay from the falling edge of ALE to the falling edge of DAS 80 44 DAS T AIOF Delay from the rising edge of DALO to the falling edge of DAS (BUS master read) 35 45 DAS T AOYS Delay from the falling edge of READY to the rising edge of DAS 46 DALI T AOIF Delay from the rising edge of DALO to the falling edge of DALI (Bus master read) 35 47 DALI T AIS DALI setup time to the rising edge of DAS (Bus master read) 135 48 DALI TAIH DALI hold time after the rising edge of DAS (Bus master read) 0 49 DALI T AIOF Delay from the rising edge of DALI to the falling edge of DALO (Bus master read) 55 50 DALO Tos DALO setup time to the falling edge of ALE (Bus master read) 110 51 DALO T AOH DALO hold time after the falling edge of ALE (Bus master read) 35 52 DAOj TWOSI Delay from the rising edge of DAS to the rising edge of DALO (Bus master write) 35 XVII-10 Taryd= 300 ns 100 MAX ns 35 250 AC TIMING SPECIFICATIONS (CONTINUED) TA = O°C to 70°C, Vee = +5 V± 5% unless otherwise specified. # TEST CONDITIONS SIGNAL SYMBOL PARAMETER MIN ns 53 CS TeSH CS hold time after the rising edge of DAS (Bus slave) 0 54 CS Tess CS setup time to the falling edge of DAS (Bus slave) 0 55 ADR TSAH ADR hold time after the rising edge of DAS (Bus slave) 0 56 ADR TSAS ADR setup time to the falling edge of DAS (Bus slave) 0 TYP ns 57 READY TARYD 58 READY TSRDS Data setup time to the falling edge of READY (Bus slave read) 75 59 READY TRDYH READY hold time after the rising edge of DAS (Bus master) 0 60 READY TSR01 READY driver turn on after the falling edge of (CSR 0, 3, RAP) DAS (Bus slave) 600 61 READY TSR02 READY driver turn on after the falling edge of (CSR 1,2) DAS (Bus slave) 1400 62 READY TSRYH READY hold time after the rising edge of DAS (Bus slave) 0 63 READ TSRH READ hold time after the rising edge of DAS (Bus slave) 0 64 READ TSRS READ setup time to the falling edge of DAS (Bus slave) 0 Delay from the falling edge of ALE to the falling edge of READY to insure a minimum bus cycle time (600 ns) XVII-11 MAX ns 80 35 OUTPUT LOAD DIAGRAM Figure 5 TEST POINT R, = 1.2K CR, -CR 4 FROM OUTPUT UNDER TEST --+-_ _--.._ _~ Q - -_ _ CR, CL IN914 OR EQUIVALENT =100pf min @ 1 MHz O.4mA I SERIAL LINK TIMING DIAGRAM - SIA INTERFACE SIGNALS Figure 6 RENA CLSN J -t==,,=+}- TCLK Timing measurements are made at the following voltages. unless otherwise specified: XVII-12 OUTPUT INPUT FLOAT .. ,.. "0" 2.0 V 2.0 V V 0.8 V 0.8V 0.5 V LANCE BUS MASTER TIMING DIAGRAM Figure 7 100 200 300 400 500 600 I I I I I I A 16·23 ALE DAL 0·15 (WRITE) i5Alo (WRITE) i5ALi (WRITE) READ (WRITE) DALO·15 (READ) DALO (READ) I5AIi (READ) READ (READ) SMO,1 NOTE:. The Bus Master cycle time will increase from a minimum of 600 ns in 100 ns steps until the slave device returns READY. XVII-13 • LANCE BUS SLAVE TIMING DIAGRAM Figure 8 ------60. 6 1 - - - - - - - - . j --1 64 58 READ (READ) DAlO-15 (READ) READ (WRITE) DAlO-15 (WRITE) DATA OUT ~+rr---9~_~~~~ ~ I DATA IN _'--_ __ _ " I XV"-14 B UNITED TECHNOLOGIES MOSTEK TELECOMMUNICATION PRODUCTS SERIAL INTERFACE ADAPTER (SIA) MK68591 FEATURES SIA ADAPTOR Figure 1 D Compatible with Ethernet D Crystal controlled Manchester Encoder D Manchester Decoder acquires clock and data within six-bit times with an accuracy of ±3ns. D Guaranteed carrier detection and collision detection threshold limits - Carrier/collision detected for greater than -300mV - No carrier/collision for less than -175mV D Input signal conditioning rejects transient noise - Transients < 10ns for collision detector inputs - Transients < 16ns for carrier detector inputs D Receiver decodes Manchester data with up to ±20ns clock jitter (at 10MHz) D TTL compatible host interface The MK68591 Serial Interface Adapter (SIA) is a Manchester Encoder/Decoder compatible with Ethernet specifications. In an Ethernet application, the MK68591 interfaces the MK68590 Local Area Network Controller for Ethernet (LANCE) to the Ethernet transceiver cable, acquires clock and data within 6 bit-times and decodes Manchester data up to ± 20ns phase jitter at 10M Hz. SIA provides both guaranteed signal threshold limits and transient noise suppression circuitry in both data and collision paths to minimize any false start conditions. PIN ASSIGNMENT Figure 2 TYPICAL ETHERNET NODE Figure 3 D Transmit accuracy ±O.01% (without adjustments) GENERAL DESCRIPTION CLSN Collislon+ RX Collision- RENA Recelve+ RCLK Recelve- TSEL Test GND l VCCl GND2 VCC2 Xl PF X2 RF TX GND3 TCLK Trensmit+ TENA Trensmlt- ETHERNET CONTROLLER XVII-1S II IJ UNITED TECHNOLOGIES MOSTEK Mostek Cprporation, 1215 West Crosby Rd. Carrollton, Texas 75006 USA; (214) 466-6000 In Europe, Contact: Mostek Brussels 270-272 Avenue de Tervuren (BTE21) B-1150 Brussels, Belgium; Telephone: 762.18.80 PRINTED IN USA July 1984 Publication No. 4420479 Copyright 1984 by Mostek Corporation All rights Reserved


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