1984_NEC_Microcomputer_Catalog 1984 NEC Microcomputer Catalog
User Manual: 1984_NEC_Microcomputer_Catalog
Open the PDF directly: View PDF 
.
Page Count: 658
| Download | |
| Open PDF In Browser | View PDF |
NEe
NEC Electronics
1
9
DATA
8
4
BOOK
NEe
1983/1984 MICROCOMPUTER CATALOG .
The information in this document is subject to change without notice. NEe Electronics
Inc. makes no warranty of any kind with regard to this material, including, but
not limited to, the implied warranties of merchantability and fitness for a particular
purpose. NEe Electronics Inc. assumes no responsibilities for any errors that may
appear in this document. NEe Electronics Inc. makes no commitment to update .
nor to keep current the information contained in this document.
No part of this document may be copied or reproduced in any form or by any means
without the prior written consent of NEC Electronics Inc.
© 1983 by NEC Electronics Inc.
Printed in the United States of America
NEe
CONTENTS
GENERAL INFORMATION
SINGLE CHIP 4·BIT MICROCOMPUTERS
SINGLE CHIP a·BIT MICROCOMPUTERS
MICROPROCESSORS
PERIPHERALS
PACKAGE OUTLINES
QUALITY & RELIABILITY
OF NEC MICROPROCESSORS
REPRESENTATIVES & DISTRIBUTORS
NEe
FUNCTIONAL INDEX
SINGLE CHIP
4-BIT MICROCOMPUTERS
PERIPHERALS
Selection Guide................
2-1
Alternate Source Guide . . . . . . . . .
2-4
ROM-Based Products Ordering
Procedure ... .... . ...
2-6
fJ.COM-4 ...... ..............
3-1
fJ.PD557L .................... 3-13
fJ.PD5521553 ........ ... .... 3-15
fJ.PD5501554.................. 3-17
fJ.PD550U554L .. ............ 3-19
fJ.PD556B Evaluation Chip. . . . . 3-21
fJ.PD7500 Series Introduction .. 3-25
fJ.PD7501 .................... 3-35
fJ.PD7502I7503 .............. 3-41
fJ.PD7506 ...... . ........... 3-47
fJ.PD750717508 ............... 3-53
fJ.PD7507S .............. .... 3-61
fJ.PD7508A .. . . . . . .. .. . 3-67
fJ.PD7508H ................... 3-75
fJ.PD7514 .................... 3-81
fJ.PD7519175CG19E . ... ..... 3-89
fJ.PD7520 .................... 3-97
fJ.PD7527175281753717538 ..... 3-103
fJ.PD7500 Evaluation Chip .... 3-105
MC-430P .................... 3-113
SINGLE CHIP
8-BIT MICROCOMPUTERS
2-2
Selection Guide ..... . " .... .
Alternate Source Guide ....... .
2-4
ROM-Based Products Ordering
Procedure ................ ..
2-6
4-1
fJ.PD78OO ................. .
fJ.PD780117802 .............. . 4-11
fJ.PD78C06/78C05 ..... . .... . 4-35
fJ.PD780917807178P09 ..... . . 4-45
fJ.PD781017811 ............ .. 4-51
fJ.PD8021 ................. . 4-65
fJ.PD8041A18741A. . . . ..... . 4-71
4-83
fJ.PD8048H18035HL ......... .
fJ.PD8748 ................. . 4-91
fJ.PD80C4818OC35 .. .. .. ... .. 4-103
fJ.PD8049H18749H18039HL .... . 4-119
4-127
fJ.PD80C49/80C39 ........ .
MICROPROCESSORS
Selection Guide .......... ..
Alternate Source Guide ...... .
fJ.PD780 ................... .
fJ.PD8085AHlfJ.PD8085A-2 .. .
fJ.PD8086 ................ ..
fJ.PD8088 ................. .
Selection Guide ......
2-3
Alternate Source Guide .... .
2-4
ROM-Based Products Ordering
Procedure . . .. .. . ... ....
2-6
fJ.PD765A17265 ...............
6-1
fJ.PD7201A ... .. .. ... ...... 6-15
fJ.PD7210
6-31
fJ.PD7220 ............... .... 6-47
fJ.PD7225 ... .... . ......
6-71
fJ.PD7227 .......... .. ...... 6-79
fJ.PD7228 ......... ..... ..... 6-87
fJ.PD7261 .. .. .. .. .... ...... 6-93
fJ.PD7720 .. , ........ ... 6-115
fJ.PD77P20 ..... ... ....
6-123
fJ.PD7751 ...
.. .......... 6-131
fJ.PD7752 . ......... ..... 6-133
fJ.PD7761m621/Mc-4760 ...... 6-135
fJ.PD815518156 ....... . ..... 6-137
fJ.PD8155H/fJ.PD8156H .... .. 6-145
fJ.PB8212 .... ... . . . . . 6-153
fJ.PB821618226 .. ..
6-159
fJ.PD8237A-5 ................ 6-163
fJ.PD8243 .....
.. . .. .. ... 6-175
fJ.PD82C43 .......... . .. . 6-181
fJ.PD8251A18251AF .......... 6-187
fJ.PD8253-2/fJ.PD8253-5 ....... 6-205
fJ.PD8255A-21fJ.PD8255A-5. .. 6-213
fJ.PD8257-21fJ.PD8257-5 ..
.. 6-221
fJ.PD8259A1fJ.PD8259A-2 .. . ... 6-231
fJ.PD8279-21fJ.PD8279-5 ....... 6-249
fJ.PB828218283 ..........
6-259
fJ.PB8284A .........
6-263
fJ.PB828618287 . .
6-269
fJ.PB8288 ......
6-275
fJ.PB8289 .. ............ .... 6-283
fJ.PD83551fJ.PD8355-21
fJ.PD8755A .............. .. 6-293
PACKAGE OUTLINES .... ......
7-1
QUALITY a
RELIABILITY OF NEC
MICROPROCESSORS
8-1
a
REPRESENTATIVES
DISTRIBUTORS ..............
2-2
2-4
5-1
5-15
5-27
5-39
1-1
9-1
II
1-2
NEe
PRODUCT
J.LCOM-4 ......................... .
MC-430P ..................... .
MC-4760 .. .. . .. .. .. .. . ... ............
J.LPD550 ............................. .
J.LPD550L .................. .
J.LPD552 ........................... .
J.LPD553 .......................... ..
J.LPD554 ............................. .
J.LPD554L ........................... .
J.LPD556B .................... .
J.LPD557L .......................... .
J.LPD765A ........................ . ..
J.LPD780 ............................. .
J.LPD7201A ........... .
NUMERICAL INDEX
PAGE
3-1
3-113
6-135
3-17
3-19
3-15
3-15
3-17
3-19
3-21
3-13
6-1
5-1
6-15
6-31
6-47
6-71
6-79
6-87
6-93
6-1
3-105
3-25
3-35
3-41
3-41
3-47
3-53
3-61
3-53
3-67
3-75
3-81
3-89
3-97
3-103
3-103
3-103
3-103
J.LP07210
J.LPD7220
J.LPD7225
J.LPD7227
J.LPD7228
J.LP07261
J.LPD7265
J.LPD7500 Evaluation Chip
J.LPD7500 Series Introduction .......... .
J.LPD7501 ................... .
J.LPD7502
J.LPD7503
J.LPD7506
J.LPD7507 ............ .
J.LPD7507S ............. .
J.LPD7508 ............... .
J.LPD7508A ............. .
J.LPD7508H .......... ..
J.LPD7514
J.LPD7519
J.LPD7520
J.LPD7527
J.LPD7528
J.LP07537
J.LPD7538
J.LP07720
6-1~5
6-123
J.LPD77P20 ...................... ..
J.LPD7751
6-131
J.LPD7752
6-133
6-135
J.LPD7761
6-135
J.LPD7762
4-1
J.LPD7800
4-11
J.LPD7801
J.LPD7802 ..
4-11
J.LPD78C05 .............. .
4-35
J.LPD78C06 .............. .
J.LPD7807 .............. ..
J.LPD7809 .................. .
J.LPD78P09 .................. ..
4-35
4-45
4-45
4-45
PRODUCT
PAGE
4-51
4-51
4-65
4-83
4-103
4-119
4-127
4-71
4-83
4-103
J.LPD80C48 .. .
4-119
J.LPD8049H .. .
J.LP080C49 ........................... . 4-127
5-15
J.LPD8085AH ..... .
5-15
J.LPD8085A-2 .. .
5-27
J.LPD8086
5-39
J.LPD8088 ...
6-137
J.LPD8155 ..
6-145
J.LPD8155H ...
J.LPD8156 ...
.. ............. . 6-137
6-145
J.LPD8156H ............ ..
6-153
6-159
!,PB8216 .......... .
6-159
J.LPB8226 .......... .
6-163
J.LPD8237A-5 ........ .
6-175
J.LPD8243 ....... .
6-181
J.LPD82C43 ...... .
J.LPD8251A .................... .
6-187
J.LPD8251AF ..
6-187
J.LPD8253-2 ..................... .
6-205
6-205
J.LPD8253-5 ......... .
6-213
J.LPD8255A-2 ...
6-213
J.LPD8255A-5 ..
6-221
J.LPD8257-2.
6-221
J.LPD8257-5.
6-231
J.LPD8259A .... .
6-231
J.LPD8259A-2 ........... ...... ..
6-249
J.LP08279-2 ...... .
6-249
J.LPD8279-5 ........ ..
6-259
J.LPD8282 ....... ..
6-259
J.LPD8283 ........ .
6-263
J.LPD8284A ...... .
6-269
J.LPD8286 ............... .
6-269
J.LPD8287
6-275
J.LPD8288
6-283
J.L!'D8289
6-293
J.LI>D8355 .... .. .. ..
6-293
J.LPD8355-2 ......... ..
6-293
J.LPD8355A ...
4-71
J.LPD8741A
J.LPD8748 ....
4-91
4-119
J.LPD8749H .
6-293
J.LPD8755A
J.LP07810
J.LP07811
J.LPD8021 ......... ..
J.LPD8035HL ........ .
J.LPD80C35 ............ .
J.LPD8039HL ........... .
J.LPD80C39 ........ .
J.LPD8041A ..
J.LPD8048H .. .
1-3
II
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
NEe
GENERAL INFORMATION
fJ
NEe
MICROCOMPUTER SELECTION GUIDE
SINGLE CHIP4-BIT MICROCOMPUTERS
DEVICE
FAMILY
ROM
RAM
1/0
PROCESS
OUTPUT
FEATURES
SUPPLY
VOLTAGE
PINS
j.LP0553
j.LCOM-43H
2000 x 8
96 x 4
35
PMOS
0.0.
A
-10
42
j.LP0557L
j.LCOM-43SL
PMOS
0.0.
A
j.LCOM-44H
j.LCOM-45
96 x 4
64 x 4
21
j.LP0552
2000 x 8
1000 x 8
0.0.
A
32 x 4
PMOS
PMOS
28
42
640 x 8
35
21
-8
-10
A
640 x 8
32 x 4
21
PMOS
j.LP0554
j.LCOM-45
1000 x 8
32 x 4
PMOS
0.0.
-10
28
j.LP0554L
j.LCOM-45L
1000 x 8
32 x 4
21
21
A
A
-10
-8
28
j.LCOM-45L
0.0.
0.0.
PMOS
0.0.
A
-8
j.LP0556B
j.LCOM-43
External
96 x 4
35
PMOS
0.0.
B
-10
28
64
MC-430P
j.LCOM-43
2000 x 8
UVEPROM
96 x 4
35
PMOS
0.0.
G
-10
42
j.LP07500
j.LP07501
j.LP07500 Series
External
256 x 4
46
CMOS
0.0.
96 x 4
24
+2.7 to 5.5
+2.7 to 5.5
j.LP07500 Series
23
0.0.
0
+2.7 to 5.5
64
j.LP07503
j.LP07500 Series
4096 x 8
128 x 4
224 x 4
CMOS
CMOS
0.0.
j.LP07502
1024 x 8
2048 x 8
C
0
64
j.LP07500 Series
0
j.LP07500 Series
j.LP07500 Series
1024 x 8
2048 x 8
64 x 4
128 x 4
22
CMOS
CMOS
0.0.
j.LP07506
j.LP07507
32
CMOS
j.LP07507S
j.LP07500 Series
2048 x 8
128 x 4
20
j.LP07508
j.LP07500 Series
4096 x 8
224 x 4
j.LP07508H
j.LP07500 Series
j.LP07508A
j.LP07500 Series
4096 x 8
4096 x 8
32
32
208 x 4
CMOS
j.LP07519
j.LP07520
j.LP07500 Series
j.LP07500 Series
4096 x 8
768 x 8
256 x 4
48 x 4
32
28
j.LP07514
j.LP07500 Series
4096 x 8
256 x 4
24
31
j.LP07528/38 j.LP07500 Series
4096 x 8
2048 x 8
160 x 4
35
160 x 4
35
j.LP0550
j.LP0550L
j.LP07527/37
Notes.
A
B
C
o
E
F
G
0.0.
j.LP07500 Series
224 x 4
23
64
+2.7 to 5.5
64
0.0.
0.0.
+2.7 to 5.5
+2.7 to 5.5
40/52
CMOS
0.0.
+2.7 to 5.5
28
CMOS
CMOS
0.0.
+2.7 to 5.5
40/52
40/52
CMOS
0.0.
0.0.
+2.7 to 5.5
A
F
PMOS
0.0.
0.0.
CMOS
0.0.
0
CMOS
CMOS
0.0.
0.0.
A
A
= - 35V VF Display Drive
= ",COM-4 EvaluatIOn Chip
= ",PD750X Evaluation Chip
= LCD Controller/Driver
= LED Display Controller/Driver
= VF Display Controller/Driver
=
28
Pin-Compatible with ",PD546
= Open Drain
2-1
E
28
+2.7 to 5.5
40
+2.7 to 5.5
-6to-10
64
28
+2.7 to 5.5
+2.7 to 5.5
80
42
+2.7 to 5.5
42
NEe
MICROCOMPUTER·SELECTION GUIDE.
SINGLE CHIP 8-BIT MICROCOMPUTERS
DEVICE
.,.P08021
.,.PD8035HL
.,.PD8039HL
.,.P08041
.,.P08041A
.,.P08048H
.,.P08049H
.,.P08741A
.,.P08748
.,.P08749H
.,.P080C35
.,.P080C48
.,.P080C39
.,.PD80C39H
.,.P080C49
.,.PD80C49H
.,.PD7800
.,.P07801
.,.PD7802
.,.P078C05
.,.PD78C06
.,.P07807
.,.PD7809
.,.P07810
.,.P07811
SPECIAL FEATURES
ROM
Zero-Cross Detector
.,.P08048 w/External Memory
.,.PD8049 w/External Memory
Peripheral Interface w/Slave Bus
Enhanced .,.P08041
Expansion Bus
High Speed .,.P08048
UV-EPROM .,.P08041A '
UV-EPROM .,.P08048
UV-EPROM .,.PD8049
CMOS 8035
CMOS 8048
CMOS 8039
CMOS8039H
CMOS 8049
CMOS8049H
Development Chip
8080 Expansion Bus
64K Memory Address Space
Expanded .,.P07801
CMOS Microprocessor
CMOS Microcomputer
7809 w/Ext. Memory
8/16 Bit Microcomputer
Romless .,.P07811
8 Channel A/0/8-16 Bit Micro
RAM
1/0
PROCESS
OUTPUT
CYCLE
1024 x 8
64 x 8
64 x 8
External
External 128 x 8
1024 x 8
64 x 8
1024 x 8
64 x 8
1024 x 8
64 x 8
2048 x 8 128 x 8
1024 x 8
64 x 8
64 x 8
1024 x 8
2048 x 8 128 x 8
External
64 x 8
64 x 8
1024 x 8
External 128 x 8
External 128'x 8
2048 x 8 128 x 8
2048 x 8 128 x 8
External 128 x 8
4096 x 8 128 x 8
21
27
27
NMOS
HMOS
HMOS
3.6 MHz
6MHz
11 MHz
18
18
27
27
18
27
NMOS
. NMOS
HMOS
NMOS
NMOS
BO
TS,BD
TS,BD
TS, BD
TS,BO
TS,BO
TS,BO
TS,BO
TS, BO
27
27
27
27
27
HMOS
CMOS
CMOS
CMOS
CMOS
TS,BO
TS, BO
TS,BD
TS, BO
TS,BO
27
27
48
CMOS
CMOS
NMOS
48
6144 x 8
48
48
48
40
64 x 8
External 128
4096 x 8 128
External 256
8192 x 8 256
External
4096 x 8
x
x
x
x
8
8
8
8
256 x 8
128 x 8
40
44
44
HMOS
6MHz
6MHz
6MHz
11 MHz
SUPPLY
VOLTAGE
+5
+5
+5
+5
+5
+5
+5
+5
6MHz
6MHz
11 MHz
6MHz
6MHz
8MHz
12MHz
+5
+5
'+2.7 to 5.5
+2.7 to 5.5
+2.7to 5.5
+2.7 to 5,5
TS, BD
TS, BO
'TS, BD
8MHz
12,MHz
+2.7to 5.5
+2.7 to 5.5
4MHz
NMOS
TS,BD
4MHz
+5
+5
NMOS
CMOS
HCMOS
HMOS
HMOS
NMOS
NMOS
TS,BD
4MHz
4MHz
4MHz
12MHz
12MHz
12MHz
+5
'"+5
+5
12MHz
+5
TS, BD
TS,BO
TS, BD
TS,BD
TS,BD
TS,BO
+5
+5
+5
MICROPROCESSORS
DEVICE
PRODUCT
SIZE
PROCESS
OUTPUT
Microprocessor
Microprocessor
Microprocessor
8-bit
8-bit
NMOS
3-State
2,5 MHz
.,.P0780-1
.,.P0780-2
NMOS
NMOS
3-State
3-State
4.0 MHz
6,0 MHz
.,.P08085A
.,.P08085A-2
.,.P08085AH
.,.P08086
.,.P08086-2
.,.P08088·
Microprocessor
Microprocessor
Microprocessor
Microprocessor
Microprocessor
Microprocessor
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
3-State
3-State
3-State
3-State
3-State
3-State
3.0 MHz
5.0 MHz
3.0 MHz
5.0 MHz
8.0 MHz
5.0 MHz
.,.P0780
8-bit
8-bit
S-bit
8-bit
16-bit
16-bit
8-bit
2-2
CYCLE
SUPPLY
VOLTAGES
+5
+5
+5
+5
+5
+5
+5
+5
+5
PINS
40
40
40
40
40
40
40
40
40
PINS
28
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
64
64
64
64
64
64
64
64
64
NEe
MICROCOMPUTER SELECTION GUIDE
SYSTEM SUPPORT
DEVICE
PRODUCT
!,PD765A
Double Sided/Double Density
Floppy Disk Controlier
!,PD7201A
SIZE
PROCESS
OUTPUT
CYCLE
SUPPLY
VOLTAGES
PINS
8-blt
NMOS
3-State
8 MHz
+5
40
Mult,·Protocol Senal Controller
8-bit
NMOS
3-State
4 MHz
+5
40
!,PD7210
IEEE Controlier (Talker, Listener,
Controlier)
8-b,t
NMOS
3-State
8 MHz
+5
40
!,PD7220
Color Graphic Display Controller
8-blt
NMOS
3-State
5 MHz
+5
40
!,PD7225
Alpha Numeric LCD
Controller/Driver
8-b,t
CMOS
-
-
2,7105,5
52
!,PD7227
Dot Matrix LCD Controlier/Drlver
8-blt
CMOS
8-blt
CMOS
-
64
Oot Matrix LCD Controller/Driver
-
2,7 to 5,5
!,PD7228
2,7 to 5,5
80
!,PD7720
Signal Processor
16-blt
NMOS
3-State
8 MHz
+5
28
!,P077P20
EPROM Version of !,P07720
16-blt
NMOS
3-State
8 MHz
+5
28
!,PD8155H
256 x 8 RAM with I/O Ports
and Timer
8-bit
HMOS
3-State
-
+5
40
!'PD8155-2
256 x 8 RAM with I/O Ports
and Timer
8-bit
NMOS
3-State
-
+5
40
256 x 8 RAM with I/O Ports
8-bit
HMOS
3-State
-
+5
40
-
+5
40
+5
24
+5
16
!,PD8156H
and Timer
!,PD8156-2
256 x 8 RAM with I/O Ports
and Timer
8-b,t
NMOS
3-State
!,PB8212
I/O Port
8-blt
Bipolar
3-State
!,PB8216
Bus Driver Non-Inverting
4-bit
Bipolar
3-State
!,PB8226
Bus Driver Inverting
4-bit
Bipolar
3-State
!,PD8243
I/O Expander
4x4blts
NMOS
3-State
-
+5
16
+5
24
!,PD82C43
I/O Expander
4x4blts
CMOS
3-State
+5
24
!,PD8251 A/ AF
Programmable Communications
Interface (Async/Sync)
8-bit
NMOS
3-State
A-9,6K baud
S-64Kbaud
+5
28
!'PD8253-2/-5
Programmable Timer .
8-b,t
NMOS
3-State
4.0 MHz
+5
24
!'PD8255A-2/-5
Peripheral Interface
8-blt
NMOS
3-State
-
+5
40
+5
40
+5
40
20
!'PD8257-2/-5
Programmable DMA Controller
8-blt
NMOS
3-State
IlPD8259-2/-5
Programmable Keyboard/Display
Interface
8-b,t
NMOS
3-State
!'PB8282/8283
8-Bit Latches
Bipolar
3-State
5 MHz
+5
IlPB8284A
Clock Driver
Bipolar
3-State
5 MHz
+5
18
IlPB8286/8287
8-81t Bus Transceivers
Bipolar
3-State
5 MHz
+5
20
IlPB8288
Bus Controller
Bipolar
3-State
5 MHz
+5
20
IlPB8289
Bus Arbiter
Bipolar
3-State
5 MHz
+5
20
IlPD8355/-2/A
2048 x 8 ROM with I/O Ports
NMOS
3-State
4MHz
-
IlPD8755A
2048 x 8 EPROM with I/O Ports
8-bit
NMOS
3-State
-
IlPD8759A/A-2
Programmable Interrupt Controller
8-bit
HMOS
3-State
518 MHz
!,PD7751
ADPCM Speech Synthesizer
8-blt
NMOS
3-State
6 MHz
+5
!,PD7752
Formant Speech Synthesizer
8-bit
CMOS
3-State
36 MHz
+5
28
!,PD7761 }
!,PD7762
!,MC-4760
K 3 Chip-SR Speech Recognilion
Chip Set
16-blt
8-blt
NMOS
NMOS
Hybrid
3-State
3-State
3-State
8 MHz
4 MHz
2 MHz
+5
+5
+5, ±12
28
64
24
8-blt
+5
40
+5
40
+5
28
40
SPEECH
PRODUCTS
-
2-3
II
NEe
MICROCOMPUTER ALTERNATE SOURCE GUIDE
I
MANUFACTURER
AMD
PART NUMBER
INTEL
NEC REPLACEMENT
AM8085A
Microprocessor (3.0 MHz)
fLPD8085A
AM8155
Programmable Peripheral Interface
with 256 x 8 RAM
fLPD8155
AM8156
Programmable Peripheral Interface
with 256 x 8 RAM
fLPD8156
AM8212
110 Port (8-Bit)
fLPB8212
AM8214
Priority Interrupt Controller
fLPB8214
AM8216
AM8226
Bus Driver, Inverting
Bus Driver, Non-Inverting
fLPB8216
fLPB8226
AM8251
fLPD8251
AM8255
Programmable Communications
Interface
Programmable Peripheral Interface
AM8257
Programmable DMA Controller
fLPD8257
AM8355
Programmable Peripheral Interface
with 2048 x 8 ROM
Single Chip Microcomputer
fLPD8355
AM8048
AMI
DESCRIPTION
7500 Family
78C06n8C05
7810n811
fLPD8255
fLPD8048
4-Bit CMOS Microcomputer
fLPD750X
8-Bit CMOS Microcomputer
fLPD78C06n8C05
16-Bit High-Performance
Microcomputer
fLPD7810n811
7807/7809
16-Bit High-Performance
Microcomputer
fLPD7807/7809
7720
Signal Processor
fLPD7720
8021
8035HL
Microcomputer with ROM
Microprocessor
fLPD8021
fLPD8035HL
8039HL
Microprocessor
fLPD8039HL
8041A
Programmable Peripheral Controller
with ROM
fLPD8041A
8048H
Microcomputer with ROM
fLPD8048H
8049H
Microcomputer with ROM
Microprocessor (3.0 MHz)
fLPD8049H
fLPD8085A
8085A
8085A-2
Microprocessor (5.0 MHz)
fLPD8085A-2
8086
Microprocessor (16-Bit)
8155/8155-2
Programmable Peripheral Interface
with 256 x 8 RAM
Programmable Peripheral Interface
with 256 x 8 RAM
fLPD8086
fLPD8155/8155-2
8156/8156-2
fLPD8156/8156-2
8212
110 Port (8-Bit)
8214
Priority Interrupt Controller
fLPB8214
8216
fLPB8216
8226
Bus Driver, Non-Inverting
Bus Driver, Inverting
8243
110 Expander
fLPD8243
2-4
fLPB8212
fLPB8226
I
NEe
MICROCOMPUTER ALTERNATE SOURCE GUIDE
I
MANUFACTURER
INTEL (CONT.)
NATIONAL
T.I.
PART NUMBER
8251A
DESCRIPTION
NEC REPLACEMENT
Programmable Communications
Interface (AsynciSync)
"PD8251A
"PD8253-5
"PD8255A-5
8253-5
Programmable Timer
8255A-5
8257-5
Programmable Peripheral Interface
Programmable DMA Controller
"PD8257-5
8259A
Programmable Interrupt Controller
"PD8259A
8272
Double Sided/Double Density
Floppy Disk Controller
"PD765
8279-5
Programmable Keyboard/Display
Interface
"PD8279-5
828218283
8-Bit Latches
"PB8282/8283
8284
Clock Driver
8286/8287
8-Blt Transceivers
"PB8284
"PB8286/8287
8288
8355
Bus Controller
Programmable Peripheral Interface
with 2048 x 8 ROM
"PB8288
"PD8355
8741A
Programmable Peripheral Controller
with EPROM
"PD8741A
8748
Microcomputer with EPROM
"PD8748
8749H
8755A
Microcomputer with EPROM
"PD8749H
"PD8755A
Programmable Peripheral Interface
with 2K x 8 EPROM
8274
Multiprotocol Serial Controller
"PD7201
I NS8048
Microcomputer with ROM
"PD8048
I NS8049
8212
Microcomputer with ROM
I/O Port (8-Blt)
"PD8049
8214
Priority Interrupt Controller
"PB8214
8216
Bus Driver, Non-Inverting
8226
Bus Driver, Inverting
"PB8216
"PB8226
INS8251
INS8253
Programmable Communications
Interface
Programmable Timer
INS8255
Programmable Peripheral Interface
INS8257
INS8259
Programmable DMA Controller
"PD8257-5
Programmable Interrupt Controller
"PD8259A
SN74S412
I/O Port (8-Bit)
"PB8212
2-5
"PB8212
"PD8251A
"PD8253-5
i>-PD8255A-5
J
NEe
ROM·BASED PRODUCTS ORDERING PROCEDURE
The following NEC products fall under the guidelines set by the ROM-based Products Ordering Procedure:
.."PD7801
.."PD7802
.."PD78C06
.."PD7807
.."PD7808
.."PD7811
.."PD8021
.."PD8041AH
.."PD8048H
.."PD80C48
.."PD8049H
.."PD80C49
.."PD8355
.."PD550
.."PD550L
.."PD552
.."PD553
.."PD554
.."PD554L
.."PD557L
.."PD7501
.."PD7502
.."PD7503
.."PD7506
.."PD7507
.."PD7507S
.."PD7508
.."PD7508A
.."PD7508H
.."PD7514
.."PD7519
.."PD7520
.."PD7527
.."PD7528
.."PD7537
.."PD7538
.."PD7720
.."PD2308A
.."PD2316E
.."PD2332
.."PD2364
.."PD2380
.."PD23128
.."PD23256
.."PD231 000
.."PD23C128
.."PD73128G
.."PD23C256
.."PD731 000
NEC Electronics Inc. is able to accept mask patterns in a variety of formats to facilitate the trahsferral of ROM mask information. These are intended to suit various customer needs and minimize turnaround time. Always enclose a listing of the code
and a complete "ROM Code Submission" form. The following is a list of acceptable media for code transfertal.
•
•
•
•
PROM/EPROM equivalents to ROM devices
Sample ROMs or ROM-based microcomputers
ISIS-II compatible 8" floppy disks
CP/M (® Digital Research Corp.) compatible 8" single-density floppy disk
Thoroughly tested verification procedures protect against unnecessary delays or costly mistakes. NEC Electronics Inc. will
return the ROM code patterhs to the customer in the most convenient format. Unprogrammed EPROMs, if sent with the
ROM code, can be programmed and returned for verification. Earth satellites and the world-wide GE Mark III timesharing
systems provide reliable and Instant communication of ROM patterns to the factory.
The following is an example of a ROM code transferral procedure. The .."PD8048H is used here; however, the process is the
same for all other ROM-based products.
1. The customer contacts his local NEC Electronics Inc. Sales Representative, concerning a ROM pattern for the
.."PD8048H that he would like to send.
2. Since an EPROM version of that part is available. the .."PD8748 is proposed as a code transferral medium.
Alternatively. a .."PD2716 or a floppy disk may be used.
3. Two programmed .."PD8748s are sent to NEC Electronics Inc., along with a listing and the "ROM Code Submission"
form. A floppy disk may also be sent as back-up.
4. NEC Electronics Inc. compares the media provided and enters the code into GE-TSS. The GE-TSS file is accessed
at the NEC factory and a copy of the code is returned to NEC Electronics Inc. for verification. One of the .."PD8748s
is erased and reprogrammed with the customers code as the NEC factory has it. The .."PD8748s, a listing, and a
"ROM Code Verification" form are returned to the customer for final verification.
5. Once the customer has notified NEC Electronics Inc. in writing that the code is verified, and has provided both the
mask charge payment and a hard-copy purchase order, work begins immediately on production of his .."PD8048Hs.
Please contact your local Sales Representative for assistance with all ROM-based product orders.
2-6
NEe
ROM Code Submission
Date' ___________________
To' NEC Electronics Inc.
252 Humboldt Court
Sunnyvale, CA 94086
Attn
ROM-Based Product Administrator
We are ready to place our purchase order for our ----C:cu-',,-om-.-'-=P-.,C",N:7u-m--:b-.,----' your ------:cN"'EC"""Pa-"C":NC"u-m7"b.-'-----' and are
submllting Two copies of the ROM Code on the following medium/media (Please check all applicable boxes)'
D fJPD2716
D fJPD8741A
D CP/M® compatible 8" single-denSity floppy disk
D fJPD2732
D
~PD8748
D Intel ISIS-II compatible 8" Single-density floppy disk
D fJPD2764
D
~PD8749H
D Intel ISIS-II compatible 8" double-density floppy disk
D fJPD27128
D jJPD8755A
Please manufacture this device with the speCial marking.
, and with the I/O Port Loading Options (available only on the ),JPD7519, jJPD7527, ),JPD7528, jJPD7537, ),JPD7538, /JPD8b21, IJPD80C48, and /JPD80C49,
and not available on all other NEC ROM-Based Products) selected on the back of this page
The mask charge payment and the ROM code listing are also enclosed
Please return the processed ROM code to the follOWing individual for our verification
Name
Company
DIVISion
Shlppmg Address (not a P
a
Box please)
State
Glty
Telephone Number
Send this form along with the ROM code, a listing, and the mask charge payment, In a package clearly marked with "ROM
CODE ENCLOSED" to the attention of the ROM-Based Product Administrator at the address above
CP I M IS
a registered trademark Of Digital Research Corp
2-7
Device
Port
110 Port Loading Option
TO
T1
T2
T3
T4
T5
T6
T7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
POolINTo
0
0
zero-crossing detector
P23 -P2,
P3 3-P30
P4 3-P40
P5 3-P50
P80
P8,
P82
P8 3
P90
P9,
P92
P9 3
P100
P10,
P102
P10 3
P11 0
P11,
P11 2
P11 3
dlfect connection
(no zero-crossing detector)
open drain
open drain
open drain
[J open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
IlPD8021
T1
POO-P07
0
0
zero-crossing detector
open drain
0
0
TTL-compatible
TTL-compatible
IlPD80C48
IlPD8OC49
P10-P17
P20-P23
P24-P27
o
o
o
CMOS (-5IJA)
CMOS (-5J,JA)
CMOS (-5~A)
0
0
0
TTL-compatible (-50IJA)
TTL-compatible ( - 50J,JA)
TTL-compatible (- 50J,JA)
~PD7519
SO
S1
S2
S3
S4
S5
S6
S7
T8/S8
T9/S9
l10/S10
T11/S11
T12/S12
T13/S13
T14/S14
T15/S15
open
open
open
open
open
open
open
open
open
open
open
open
open
open
open
open
open
open
open
open
open
open
open
open
drain
drain
drain
drain
drain
drain
drain
drain
drain
drain
drain
drain
drain
drain
drain
drain
drain
drain
drain
drain
drain
drain
drain
drain
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
pull-down
pul'-doWh
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
V LOAD
V LOAD
V LOA D
V LOA D
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
~ ..
IlPD7527
IlPD7528
IlPD7537
IlPD7538
2-8
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
resistor
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
V LOAD
V LOA D
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
V LOAD
NEe
SINGLE CHIP 4·BIT MICROCOMPUTERS
II
NEe
,..COM-4
4-81T SINGLE CHIP MICROCOMPUTER FAMILY
DEseR IPTION
The tlCOM4 4-bit Microcomputer Family is a broad product line of 14 individual
devices designed to fulfill a wide variety of design criteria. The product line shares a
compatible architecture and instruction set. The architecture includes all functional
blocks necessary for a single chip controller, including an ALU, Accumulator, Byte·
wide ROM, RAM, and Stack. The instruction set maximizes the efficient utilization
of the fixed ROM space, and includes a variety of Single Bit Manipulation, Table
Look-Up, BCD arithemetic, and Skip instructions.
The tlCOM·4 Microcomputer Family includes seven different products capable of
directly driving 35V Vacuum Fluorescent Displays. Four products are manufactured
with a CMOS process technology. tlCOM-4 Microcomputers are ideal for low-cost
general purpose controller applications such as industrial controls, instruments,
appliance controls, intelligent VF display drivers, and games.
F EATU R ES • Choice of ROM size: 2000 x B, 1000 x 8, or 640 x 8
• Choice of RAM size: 96 x 4, 64 x 4, or 32 x 4
- Six 4-Bit Working Registers Available
- One 4-Bit Flag Register Available
• Powerfu I Instruction Set
- Choice of 80 or 58 Instructions
- Table Look·Up Capability with CZP and JPA Instructions
- Single Bit Manipulation of RAM or I/O Ports
- BCD Arithmetic Capability
• Choice of 3-Level, 2-Level, or 1-Level Subroutine Stack
• Extensive I/O Capability
- Choice of 35 or 21 I/O Lines
42/52,PIn Packages
28-Pin Package
2
1
- 4-Bit Input Ports
- 4·Bit I/O Ports
2
2
4
- 4·Bit Output Ports
2
- 3-B it Output Ports
- 1-B it Output Port
• Programmable 6-Bit Timer Available
• Choice of Hardware or Testable Interrupt
• Built-In Clock Signal Generation Circuitry
• Built-In Reset Circuitry
• Single Power Supply
• Low Power Consumption
• PMOS or CMOS Technologies
• Choice of 42'pin DIP, 2B'pin DIP, or 52'pin Flat Plastic Package
3-1
II
"COM-4
Internal Registers
The ALU, the Accumulator, and the Carry Flag together comprise the central portion
of the IlCOM-4 Microcomputer Family architecture. The ALU performs the arithmetic
and logical operations and checks for various results. The Accumulator stores the
results generated by the ALU and acts as the major interface point between the RAM,
the I/O ports, and the Data Pointer registers. The Carry F/F can be addressed directly,
and can also be set during an addition. The IlPD546, IlPD553, IlPD557 L, and IlPD650
also have a Carry Save F IF for storage the value of the Carry F IF.
Data Pointer Registers
The DPH register and 4-bit DPL register reside outside the RAM. They function as the
Data Pointer, addressing the rows and columns of the RAM, respectively. They are
individually accessible and the L register can be automatically incremented or
decremented.
RAM
All IlCOM-4 microcomputers have a static RAM organized into a multiple-row by
16-column configuration, as follows:
MICROCOMPUTER
RAM
Il PD546,Il PD553,
IlPD557L, and !,PD650
ORGANIZATION
96 x 4
Il PD547,Il PD547L
IIlPD552, and jtPD651
64 x 4
[Il PD550.jtPD550L,
IlPD554, jtPD554L,
and IlPD652
32 x 4
DPH
DPL
6 rows x 16 columns
3
4
4 rows x 16 columns
2
4
2 rows x 16 columns
1
4
!
I
~~
The IlPD546, IlPD553, IlPD557L, and IlPD650 also have a 4-bit Flag register and six
4·iJit working registers resident in the last row of the RAM. Their extended instruction
set provides 10 additional instructions With which you can access or manipulate these
seven registers.
ROM
The ROM is the mask-programmable portion of the IlCOM-4 Microcomputer which
stores the application program. It is organized as follows:
MICROCOMPUTER
IlPD546,IlPD553,
IlPD557L, and jtPD650
I---IlPD547,IlPD547L,
_~PD552,IlPD651
Il PD554.Il PD554L,
and IlPD652
IlPD550 and jtPD550L
~----
I
!
.,
ORGANIZATION
ROM
2000 x 8
1000 x 8
PAGES
8
16
8
8
I
i -- 1000 x 8
L
FIELDS
8
I
640 x 8
I
8
8
8
3-2
FUNCTIONAL
DESCRIPTION
,..COM-4
FUNCTIONAL
DESCRIPTION
(CONT.)
Program Counter and Stack Register
The Program Counter contains the address of a particular instruction being executed.
It is incremented during normal operation, but can be modified by various JUMP and
CALL Instructions. The Stack Register IS a LIFO push-down stack register used to save
the value of the Program Counter when a subroutine is called. It IS organized as follows:
STACK
ORGANIZATION
ALLOWABLE
SUBROUTINE CALLS
I'PD546,I'PD553,
I'PD557 L, and I'PD650
I'PD651
I'PD547,I'PD547L,
and I'PD552
3 words x 11 bits
3 Levels
I'PD550,I'PD550L,
I'PD554,I'PD554L,
and I'PD652
1 word x 10 bits
MICROCOMPUTER
...-..
2 Levels
--~
2 words x 10 bits
1 word x 10 bits
..-
-
1 Level
1 Level
Interrupts
AIIIlCOM-4 microcomputers are equipped with a software-testable Interrupt which
skips an instruction If the Interrupt FIF has been set. The TIT Instruction resets the
Interrupt F IF.
In addition, the IlPD546, IlPD553, IlPD557L, and IlPD650 have a level-triggered hardware interrupt, which causes an automatic stack level shift and interrupt service routine
call when an interrupt occurs.
Interval Timer
The IlPD546, IlPD553, IlPD557 L, and IlPD650 are equipped with a programmable
6-bit interval timer which consists of a 6-blt polynomial counter and a 6-bit binary
down counter. The STM Instruction sets the initial value of the binary down counter
and starts the timing. The polynomial counter decrements the binary down counter
when 63 Instruction cycles have been completed. When the binary down counter
reaches zero, the timer F IF is set. The TTM instruction tests the timer F IF, and skips
the next Instruction if it is set.
Clock and Reset Circuitry
The Clock Circuitry for any IlCOM-4 microcomputer can be implemented by connecting either an Intermediate Frequency Transformer (1FT) and a capacitor, or a Ceramic
Resonator and two capacitors, to the CLO and CL 1 Inputs. The Power-On-Reset
Circuitry for any IlCOM-4 microcomputer can be implemented by connecting a
Resistor, a Capacitor, and a Diode to the RESET input.
3-3
",COM-4
I/O Capability
The pCOM·4 microcomputer family devices have either 35 or 21 I/O lines, depending
upon the individual device, for communication with and control of external Circuitry.
They are organized as follows:
FUNCTION
/JPD546, /JPD547,
/JPD547L, /JPD552,
/JPD553, /JPD650.
and /JPD651
PORT
SYMBOL
Port A
PAO·3
4-81t Input
Port 8
PBO·3
4-Blt Input
Port C
PCO·3
4-81t Input/Output
Port D
PDO·3
·4·Blt Input/Output
IVF Dnve POSSIble)
Port E
PEO·3
4·Blt Output
Port F
PFO.3
4·Blt Output
IVF Dnve PosSIble I
•
PGO·3
4· Bit Output
IVF Dnve POSSIble)
•
PGO·l
l·Blt Output
IVF Dnve POSSIble)
Port H
PHO·3
4·Blt Output
IVF Dnve POSSIble)
Port I
PIO·2
3·Blt Output
(VF Drive Possible)
IVF Dnve PosSiblel
(VF Dnve Possible)
Port G
/JPD550, /JPD550L,
/JPD554, /JPD554L.
/JPD557L, and /JPD652
·
•
·
·•
•
•
·
·•
--
·
•
·
Development Tools
The NEC Development System (NOS) is
editing, and assembling source code into
Assembler is available for systems which
System or the CP/M (® Digital Research
available for developing software service code,
object code. In addition, the ASM·43 Cross
support either the Intel ISIS·II Operating
Corp.) Operating System.
The EVAKIT-43P Evaluation Board is available for production device emulation and
prototype system debugging. The SE·43P Emulation Board is available for demon·
strating the final system design. The pPD556B ROM·less Evaluation Chip is available
for small pilot production.
3-4
FUNCTIONAL
DESCRIPTION
(CaNT.)
IlPD546, IlPD553,
IlPD557L,IlPD650
BLOCK DIAGRAM
,..COM-4
INSTRUCTION BUS B BIT
PIO·2
RAM
DECODER
PHO·3
CONTROL
AND
PGO·3
PFO·3
flAM
96 x 4
PEO·3
PDO·3
PCO·3
STACK 0
I/O
INTERFACE
PBO·3
4 BIT
STACK 1
B BIT
STACK 2
CLO
PAO·3
RES
Netf'
Siock dIagram above apphes to /-lPD546, p.PD553, and ,u.PD650 4-blt microcomputers The
,uPD557L block diagram IS similar to the above, except that PBO-3, PGl_3. PHO-3, and
PtO-2 have been eliminated to accommodate the ,uPD557L's 28-pln package
IlPD547, IlPD547 L,
IlPD552, IlPD651
BLOCK DIAGRAM
INSTRUCTION BUS 8 BIT
RAM
IJECODER
CONTROL
AND
DECODE
RAM
64x 4
ROM
1000x 8
8 BIT
8 BIT
10
INTERFACE
4 BIT
8 BIT
INT
F/F
IN
3-5
r
STACK 1
ipPD651 ON L YI
RES
11
tLPD550, tL PD 550L,
tLPD554, tL PD 554L,
tLPD652
IlCOM-4
BLOCK DIAGRAM
INSTRUCTION BUS 8 BIT
RAM
OECODER
ROM
CONTROL
AND
DECODE
PGo
!-lPD550 I 640 x 8
"PD550L (
PFo 3
RAM
8 BIT
32 X 4
PEO·3
PDO·3
PCn 3
PA O_3
I/O
INTERFACE
4 BIT
' 8 BIT
INT
FiF
CLo
CL,
The tLPD546, fJPD553, fJPD557 L, and tLPD650 execute all 80 instructions of the
extended tLCOM-4 instruction set. The 22 additional instructions are indicated by
shading.
The tLPD547, tLPD547 L, tLPD550, fJPD550L, tLPD552, fJPD554, tLPD554L, fJPD651 ,
and tLPD652 execute a 58 instruction subset of the fJCOM-4 instruction set.
3-6
IN r
1
RES
INSTRUCTION SET
",COM-4
I NSTRUCTION SET
SYMBOL DEFINITIONS
The following abbreviations are used in the description of the pCOM-4 instruction set:
SYMBOL
EXPLANATION AND USE
Accumulator
ACC
ACC n
address
Bit UnU of Accumulator
Immediate address
C
Carry F/F
C'
Carry Save F/F
Immediate data
data
Dn
Bit un" of immediate data or immediate address
DP
Data Pointer
Upper Bits of Data Pointer
DPH
Lower 4 Bits of Data Pointer
DPL
FLAG
INTE F/F
INT F/F
P(
)
F LAG Register
Interrupt Enable F/F
Interrupt F/F
Parallel Input/Output Port addressed by the value within the brackets
Pn
Bit un" of Program Counter
PA
Input Port A
PC
Input/Output Port C
PD
Input/Output Port D
PE
Output Port E
R
R Register
S
S Register
SKIP
STACK
TC
Number of Bytes in next instruction when skip condition occurs
Stack Register
6-Bit Binary Down Timer Counter
TIMER F/F
Timer F/F
W
W Register
X
X Register
y
Y Register
Z
(
[
Z Register
)
The contents of RAM addressed by the value within the brackets
1
The contents of ROM addressed by the value within the brackets
..
Exchange
-
Complement
¥
LOGICAL EXCLUSIVE OR
+-
Load, Store, or Transfer
Applies to pPD546, pPD553, pPD556B, pPD557L, and pPD650 only
3-7
INSTRUCTION SET
IlCOM-4
X
ACC~ lOP)
Exchange A wIth the RAM con-
0
0
tents addreuad by OP
XI
XC
Ace with RAM con-
tents addressed by OP, Increment
Ace" (OPI
OPL -DPL-1
- FH
Exchange Ace with the RAM
contents addreued by OP.
• FH
decrement
SkiP If
Skip If
XMdata
Exchange
Ace- (OPI
OPL -OPL + 1
Skip ,f
-OH
ACC~loP)
Exchange Ace with the RAM
DPH - DPH ¥ 01-0
contents addressed by OP. Per-
1+5
oPL -OH
1+5
oPL - FH
01
DO
01
Do
1+5
DPL
01
Do
1+5
OPL - FH
form I LOGICAL EXCLUSIVE·
OR Between DPH and 2 bits of
immediate data, store the results
XMI data
Exchange
DPH +- OPH ¥ 01'()
OPL-OPt + 1
contents addressed by OP. Per-
SkiP ,f OPL "" OH
XMOdata
Ace WIth the RAM
ACC~ lOP)
ACC~ lOP)
DPH +- DPH ¥ D1'()
OPL +- OPL-1
SkiP if DPL - FH
0
~
OH
form a LOGICAL EXCLUSIVEOR Between DPH and 2 bits of
Immediate data, store the results
In DPH Increment OPL. Skip If
-OH
Exchange Ace With the RAM
contents addressed by Op. Perform e LOGICAL EXCLUSIVE·
OR Between DPH and 2 bits of
Immechate date, store the results
In DPH decrement DPL, SkiP If
- FH
0
3-8
INSTRUCTION SET
(CaNT.)
MNEMONIC
AD
"COM-4
FUNCTION
Ace .... Ace + lOP)
Skip If overflow
DESCRIPTION
Add the RAM contents addressed
by DP to Ace; skiP if overflow IS
1 +S
Overflow
1 +S
Overflow
generated
ADC
Ace +- Ace + lOP) + C
If overflow occurs,
C~I
ADS
Ace+-Ace+ lOP) + C
if overflow occurs,
e +- 1 and skIp
Add the RAM contents addressed
by OP and the carry F IF to Ace.
if overflow occurs, set Carry F/F
and
OAA
ACc- ACC+ 6
DAS
ACC- ACC+ 1O
Add 10 to Ace to Adjust
Oe<:imel for BCD Subtraction
EXL
ACC ~ ACC'" (DPI
Perform a LOGICAL
EXCLUSIVE-OR between the
INC
DEC
IND
OED
3-9
INSTRUCTION SET
(CONT.)
IlCOM-4
MNEMONIC
SKIP
CONOITION
FUNCTION
RMBdlta
(OPlblt+- O
5MBdata
(OPlblt-'
data
PEbit -0
SEa data
PEblt-'
APB data
PIDPLlblt
+-
0
SPB data
P(OPLlblt
+-
1
JMP address
P10.o-01
JCP address
JPA
PS·2- ACC
P1.o - 00
CALaddreSi
Stack-P+2
PlO.o - D10.o
CZP address
Stack-P+ 1
Pl0-S- 00000
PS-2 +- 03-0
Pl-O- 00
Store a return address IP + 2) In
the stack,call the subroutine program at the location specified by
11 bits of Immediate data
1
D7
De
Store a return address IP + 11m
the stack, call the subroutine program at one of sixteen locations In
Page 0 of Field 0, specified by 4
3-10
Ds
D4
Os
D3
DlO
D2
D1
DB
DO
D3
D2
D1
DO
",COM-4
INSTRUCTION SET
(CaNT.)
FUNCTION
DESCRIPTION
TIT
II
oeD
NOP
Perform no operatIon, con·
sume one machine cycle
3 -11
",COM-4
Package Outlines
For information. see Package Qutline Section 7.
Plastic, ... COM-4C
Plastic Minifl!!t, ...COM-4G
IlCOM4DS-2-82-CAT
3-12
NEe
f'PD557L
4-BIT SINGLE CHIP MICROCOMPUTER WITH
VACUUM FLUORESCENT DISPLAY DRIVE
CAPABILITY
DESCRIPTION
Thel1PD557L IS a 4-blt single chip microcomputer which has the same architecture as
the I1 PD553, but IS pin-compatible with the I1PD550L and the I1PD554L. The I1PD557 L
contains a 2000 x 8-blt ROM and a 96 x 4-bit RAM, which Includes SIX working registers and the FLAG register. It has a lever-triggered hardware Interrupt Input INT, a
three-level stack and a 6-blt programmable timer. The I1PD557L provides 21 I/O lines,
organized into the 4-bit Input port A, the 4-blt I/O ports C and D, and the 4-blt output
ports E and F, and the 1-blt output port G. The 17 I/O ports and output ports are
capable of being pulled to -35V In order to drive Vacuum Fluorescent Displays directly.
The I1 PD557L tYPically executes all 80 instructions of the extended I1COM-4 family
instruction set with a 2511s Instruction cycle time. It is manufactured with a modified
PMOS process, allowing use of a single -8V power supply and IS available In a 28-pln
dual-I n-Ilne plastic package.
The I1PD550L and the I1PD554L are upward-compatible with the I1 PD557L.
PIN CONFIGURATION
Cll
PCo
PIN NAMES
Clo
2
VGG
PAO-PA3
Input Port A
Input/Output Port C
PCl
3
RESET
PCO-PC3
PC2
4
iNT
POO-PD3
Input/Output Port 0
PC3
5
PA3
PEO-PE3
Output Port E
POo
6
PA2
PFO-PF3
Output Port F
PGO
Output Port G
POl
P02
8
P03
9
I1PD
557L
PAl
PAO
PGo
PEa
PF3
INT
'cLQ=Cll
Interrupt Input
External Clock Signals
RESET
Reset
VGG
Power Supply Negative
PEl
PF2
VSS
Power Supply PosItive
PE2
PFl
TEST
PE3
PFo
Factory Test Pm
(Connect to VSS)
VSS
TEST
ABSOLUTE MAXIMUM Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10°C to +70°C
RATINGS* Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +125°C
SupplyVoltage,VGG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-15to+0.3V
Input Voltages (Port A, INT, RESET) . . . . . . . . . . . . . . . . . . . . . . -15 to +0.3V
(Ports C, D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +0.3V
Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +0.3V
Output Current (Ports C, D, each bit) . . . . . . . . . . . . . . . . . . . . . . . . . .. - 4 mA
(Ports E, F, G, each bit) . . . . .. . . . . . . . . . . . . . . . . . -25 mA
(Total, all ports) . . . . . . . . . . . . . . . . . . . . . . . . . . .. -100 mA
*COMMENT Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the devIce. ThIs IS a stress rating only and functional operatIOn of the devIce at these or
any other condItions above those indicated In the operational sections of thIs specificatIOn IS not
implied. Exposure to absolute maximum ratmg conditions for extended penods may affect device
reliability.
Rev/1
3-13
II
,""PD557L
Ta =-lo'C,o +70'C. VGG =--B.OV ± 10%
DC CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL. MIN
TYP
MAX
UNIT
TEST
CONDITIONS·
VIH
0
-2.5
V
Port. A. C. D. INT. RESET.
VILl
-6.5
VGG
V
Ports A, INT, RESET
VIL2
-6.5
-35
V
PortsC,D
Clock Voltage HIgh
Vq,H
0
-0.6
V
CLO Input, External Clock
Clock Voltage Low
".~L
-5.0
VGG
V
CLo Input, External Clock
Input Voltage High
Input Voltage Low
Input Leakage Current High
ILiH
+10
~A
Port. A. C. D. INT. RESET
VI =-lV
ILiLl
-10
~A
Ports A. C. D. INT. RESET
V =-9V
Input Leakage Current Low
ILIL2
-30
~A
Ports C, D, VI '" -35V
Clock Input Leakage Current High
IL.,H
+200
~A
eLO Inpu,. V.,H = OV
Clock Input Leakage Current Low
ILq,L
-200
~A
CLO Inpu,. V.,L =-9V
VOHl
-1.0
V
VOH2
-4.0
V
ILOLl
-10
~A
Ports C through G,
Va =-9V
ILOL2
-30
~A
Ports C through G t
Va =-35V
-36
rnA
Output Voltage High
Ports C through G,
IOH ""-2 mA
Ports E. F. G, IOH =-20 mA
Output Leakage Current Low
Supply Current
-20
IGG
Ta= 2SoC
CAPACITANCE
LIMITS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Input Capacitance
CI
15
pF
Output Capacitance
Co
15
pF
Input/Output Capacitance
Cia
15
pF
Ta = -10'C
TEST
CONDITIONS
t= 1 MHz
'0 +70'C. VGG =-8.0V ± 10%
AC CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Oscillator Frequency
t
Rise and Fall Times
tr,tf
0
0.3
IJS
Clock Pulse Width High
'q,WH
2.0
8.0
IJS
'4>WL
2.0
8.0
IJS
Clock Pulse Width Low
100
180
TEST
CONDITIONS
kHz
External Clock
t-----l/f---~-~
CLOCK WAVEFORM
Package Outlines
For information, see Package Outline Section 7.
Plastic, fl.PD557LC
Plastic Shrinkdip, ,..,PD557LCT
3-14
557LDS-REV 1-2-82-CAT
NEe
"PD552
"PD553
4·BIT SINGLE CHIP MICROCOMPUTERS WITH
VACUUM FLUORESCENT DISPLAY DRIVE
CAPABILITY
DESCRIPTION
The IlPD552 and the IlPD553 are pin-compatible 4-bit single chip microcomputers
which have similar architectures_
The IlPD552 contains a 1000 x 8-bit ROM and a 64 x 4-bit RAM_ It has a testable
interrupt input INT, a single-level stack, and executes all 58 instructions of the
IlCOM-4 family instruction set. The IlPD552 is upward compatible with the IlPD553.
The IlPD553 contains a 2000')( 8-bit ROM, and a 96 x 4-bit RAM which includes six
working registers and the Flag register. It has a level-triggered hardware interrupt, a
three-level stack, and a programmable 6-bit Timer. The IlPD553 executes all 80
instructions of the extended IlCOM-4 family instruction set.
Both the IlPD552 and the IlPD553 provide 35 I/O lines organized into the 4-bit input
Ports A and B, the 4-bit I/O Ports C and D, the 4-bit output Ports E, F, G, and H, and
the 3-bit output Port I. The 27 I/O ports and output ports are capable of being pulled
to ~35V in order to drive Vacuum Fluorescent Displays directly. Both devices typically
execute their instructions With a 10 IlS instruction cycle time. The IlPD552 and the
IlPD553 are manufactured with a standard PMOS process, allowing use of a Single
~10V power supply, and are available in a 42-pin dual-In-line plastic package.
PIN CONFIGURATION
CL,
PCo
PC,
PC2
PC3
2
3
4
5
VGG
PB3
PB2
PB,
iNT
6
PBO
PA3
PA2
PAl
PAO
PI2
PI,
PIO
PH3
PH2
PH,
PHO
PG3
PG2
PG,
PGO
RESET
PDQ
PO,
P02
P03
PEO
PEl
PE2
PE3
PFO
PF,
PF2
PF3
TEST
VSS
ABSOLUTE MAXIMUM
RATINGS*
CLo
8
Il PD
552/
553
PIN NAMES
PAO-PA3
Input Port A
PBO-PB3
I nput Port B
PCO,PC3
I nput/Output Port C
POO-P03
I nput/Output Port 0
PEO-PE3
Output Port E
PFO·PF3
Output Port F
PGO-PG3
Output Port G
PHO-PH3
Output Port H
PIO-PI2
Output Port I
INT
I nterrupt Input
CLO·CL,
External Clock Signals
RESET
Reset
VGG
Power Supply Negative
VSS
Power Supply Positive
TEST
Factory Test Pm
(Connect to VSS)
Operating Temperature ... _ . . . . . . . . . . . . . . . . . . . . . . . . . . . -10°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +125°C
SupplyVoltage,VGG...
. . . . . . . . . . . . . . . . . . . -15 to +0.3V
Input Voltages (Port A, B, INT, RESET) . . . . . . . . . . . . . . . . . . . . . .-15 to +0.3V
(Ports C, D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40 to +0.3V
Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40 to +0.3V
Output Current (Ports C through I, each bit) . . . . . . . . . . . . . . . . . . . . . . -12 mA
(Total, all ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -60 mA
*COMMENT Stress above those listed under "Absolute MaXimum Ratings" may cause permanent
damage to the deVice. ThiS IS a stress rating only and functional operatIon of the deVice at these or
any other conditIOns above those mdicated In the operational sections of thiS specIfIcation is not
implIed. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability .
3-15
II
",PD552/553
DC CHARACTERISTICS
LIMITS
PARAMETER
Input Voltage High
Input Voltage Low
SYMBOL
MIN
TYP
MAX
UNIT
Ports A through 0, INT,
RESET
VIH
0
VIL1
-75
VGG
V
Ports A, B, INT, RESET
VIL2
-75
-35
V
Ports C, 0
V
CLO Input. External Clock
Clock Voltage High
Vq>H
0
Clock Voltage Low
Vq>L
-60
-35
TEST
CONDITIONS
-08
VGG
V
V
CLO Input, External Clock
Ports A through 0, INT,
Input Leakage Current High
ILiH
+10
pA
RESET, VI =-lV
Input Leakage Current Low
IUL1
-10
pA
Ports A through 0, fiiJ'f,
RESET, VI = -11V
ILlL2
-30
pA
PortS C, 0, V I '" -35V
ILrpH
+200
pA
CLO Input, V.pH - OV
Clock Input Leakage Current Low
IL¢L
-200
pA
Output Voltage High
VOH
Clock Input Leakage Current High
I
-20
A, .
V
'LOL,
-10
pA
ILOL2
-30
pA
-50
mA
Output Leakage Current Low
Supply Current
-30
IGG
CLO Input,VIj>L=-11V
Ports C through L
IOH = -8 mA
Ports C through I,
VO""-11V
Ports C through I,
Va'" -35V
CAPACITANCE
LIMITS
TYP
MAX
UNIT
CI
15
pF
Output Capacitance
Co
15
pF
Input/Output Capacitance
CIO
15
pF
PARAMETER
SYMBOL
MIN
Input Capacitance
TeST
CONDITIONS
f'" 1 MHz
AC CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
MIN
TYP
150
MAX
440
UNIT
TEST
CONDITIONS
KH,
OSCillator Frequency
f
RIse and Fall Times
tr,tf
0
03
p'
Clock Pulse Width High
tq,WH
05
5.6
Clock Pulse Width Low
t~WL
0.5
56
"'
EXTERNAL CLOCK
"'
1------l/f-----_~
CLOCK WAVEFORM
Package Outlines
For information, see Package Outline Section 7.
Plastic, fLP0552C/553C
3-16
552/553DS-2-82-CAT
NEe
,.,PD550
,.,PD554
4-BIT SINGLE CHIP MICROCOMPUTERS WITH
VACUUM FLUORESCENT DISPLAY DRIVE
CAPABILITY
DESCRIPTION
The IlPD550 and the IlPD554 are pin.compatible 4·bit single chip microcomputers
which have the same architecture. TlJe only difference between them is that the
IlPD550 contains a 640 x 8·bit ROM, whereas the IlPD554 contains a 1000 x 8·bit
ROM. Both devices have a 32 x 4·bit RAM, a testable interrupt input INT, and a
single·level stack. The IlPD550 and the IlPD554 provide 21 I/O lines organized into'
the 4·bit input port A, the 4·bit I/O ports C and D, the 4·blt output ports E and F,
and the l·bit output port G. The 17 I/O ports and output ports are capable of being
pulled to -35V in order to drive Vacuum Fluorescent Displays directly. The IlPD550
and the IlPD554 typically execute all 58 instructions of the lleOMA family instruc·
tion set with a 10 Ils instruction cycle time. Both devices are manufactured with a
standard PMOS process, allowing use of a single -10V power supply, and are available
in a 28 pin dual·in·line plastic package.
PIN NAMES
PIN CONFIGURATION
Cl,
Clo
PAO·PA3
Input Port A
PCo
VGG
PCO,PC3
Input/Output Port C
PC1
RESET
POO·P03
Input/Output Port 0
PC2
iNT
PEO·PE3
Output Port E
PC3
PA3
POO
PA2
PFO·PF3
Output Port F
PGIL
ClO·Cl,
Output Port G
External Clock Signals
PO,
PAl
INT
Interrupt Input
P02
PAO
RESET
Reset
P03
PGO
VGG
Power Suppl y Negative
PEO
PF3
Power Supply Poslti ve
PEl
PF2
VSS
TEST
PE2
PF,
PE3
PFo
Vss
TEST
Factory Test PI n
(Connect to VSS)
ABSOLUTE MAXIMUM Operating Temperature . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . -10°C to +70°C
RATINGS* Storage Temperature .....
o-40°Cto +125°C
000000000000000000000000.0
-15 to +0.3V
Supply Voltage, VGG ..
Input Voltages (Port A, INT, RESET) . . . . . . . . . . . . . . . . . . . . . . . .-15 to +0.3V
(Ports C, D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40 to +0.3V
Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40 to +O.3V
Output Current (Ports C, 0, each bit) ..
do .
-4 mA
-15 mA
(Ports E, F, G, each bit) .
(Total, all ports) .
-60 mA
0
0
0
0
•
0
0
••••
0
*COMMENT. Stress above those
damage to the deVice. This
IS
I,~sted
•
0
0
••••••••••••••••••••
0
••••••••
0
••
0
•••••••••••••••
•••••
0
••••••••
under "Absolute
0
•
Ma~lmum
0
0
0
0
••••••••
0
0
••••••••
•••
0
0
Ratmgs" may cause permanent
a stress rating only and functional operation of the deVice at these or
any other conditions above those indicated In the operational sections of th IS specification IS not
Implied. Exposure to absolute maximum rating conditions for extended periods may affect deVice
reliability.
3-17
II
IlPD550/554
DC CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
Input Voltalll High
Input Voltage low
MIN
TYP
MAX
TEST
CONDITIONS
UNIT
Pons A, C, D, !lIlT; RESET
VIH
0
-2.0
V
VIL,
-4.3
VGG
V
Pons A, INT, RESET
VIL~
-4.3
-35
V
Po"sC,D
Ext.r~1
Clock Voltllfll High
VI/lH
0
-0.8
V
eLO Input,
Clock Voltllfll Low
V,.L
-8.0
VGG
V
CLQ Input, Extarnsl Clock
Input L.eakage Current High
ILIH
+10
~A
Ports A, C, D, iiii'\", RESET
VI--IV
ILILI
-10
"A
ILIL2
-30
~A
Ports C, D, VI = -35V
Ild>H
+200
IlA
CLQ Input, V,.H .OV
Input Leakage Current Low
Clock Input Leakage Current High
CJock Input leakage Current Low
Output Voltage HIgh
Pons A, C, D, iNT, RESET
Vt--11V
Ild>L
-200
"A
CLQ Input, V,.L --IIV
VOH,
-1.0
V
Pons C, D, IOH • -2 mA
VOH2
-2.5
V
Pons E, F, G, IOH =-IOmA
ILOL,
-10
"A
Pons C through G,
Vo --l1V
ILOL2
-30
~A
Port. C through G.
Vo --35V
-40
mA
Output Leakage Current low
SupplV Current
Clock
-20
IGG
Ta· 25"C
LIMITS
PARAMETER
SYMBOL
MIN
TVP
MAX
UNIT
Input Capacitance
CI
15
pF
Output C.pacitance
Co
15
pF
Input/Output Capacitance
CIO
15
pF
TEST
CONDITIONS
CAPACITANCE
f-I MHz
AC CHARACTERISTICS
LIMITS
PARAMETER
Oscillator Froquencv
RI_ Ind FIll Tim..
Clock Puill Width High
Clock Pul.. Width Low
SYMBOL
MIN
MAX
UNIT
f
150
440
KHz
tr'f
0
0.3
~.
"WH
0.5
5.6
~.
"WL
0.5
6.6
TVP
TEST
CONDITIONS
Extamal Clock
,..
!4-----1/f-------.j
CLOCK WAVEFORM
Vss
V."L
vGG
Package Outlines
For Informatlon,._ Package Outline Section 7.
PlastiC, ",PD550C/554C
Plastic Shrinkdip, ",PD550CT
Plastic Shrinkdip, ",PD554CT
3-18
550/654DS-I-82-CA T
NEe
IlPD550L
IlPD554L
4-BIT SINGLE CHIP MICROCOMPUTERS WITH
VACUUM FLUORESCENT DISPLAY DRIVE
CAPABILITY
OESCR IPTION
The !lPD550L and the !lPD554L are pin-compatlble 4·bit single chip microcomputers
which have the same architecture. The only difference between them IS that the
!lPD550L contains a 640 x 8·bit ROM, whereas the !lPD554L contains a 1000 x 8·bit
ROM. Both devices have a 32 x 4-bit RAM, a testable interrupt Input INT, and a single.
level stack. The !lPD550L and the !lPD554L provide 21 I/O lines organized into the
4·blt input port A, the 4-bit I/O ports C and D, the 4·bit output ports E and F, and the
l·bit output port G. The 17 I/O ports and output ports are capable of being pulled to
-35V in order to drive Vacuum Fluorescent Displays directly. The !lPD550L and the
!lPD554L typically execute all 58 instructions of the !lCOMA family instruction set
with a 25!ls Instruction cycle time. Both devices are manufactured with a modified
PMOS process, allowing use of a single -8V power supply, and are available in a 28,pln
dual·m·line plastic package.
The !lPD550L and the !lPD554L are upward compatible with the !lPD557L.
PIN NAMES
PIN CONFIGURATION
CLl
PCo
2
CLo
VGG
PCl
3
RESET
PC2
PC3
4
iiiiT
5
POo
6
PA3
PA2
POl
7
P02
8
P03
9
!lPD
550L/
554L
PEO
PEl
PAQ· PA3
PCO,PC3
POO·P03
PEO·PE3
PFO·PF3
PGo
CLO·CLl
PAl
INT
RESET
PAO
PGO
PF3
VGG
VSS
TEST
PF2
PF,
PE2
PE3
Input Port A
Input/Output Port C
Input/Output Port 0
Output Port E
Output Port F
Output Port G
External Clock Signals
Interrupt Input
Reset
Power Suppl y Negative
Power Supply POSltl ve
Factory Test PI n
(Connect to VSS)
PFo
TEST
VSS
ABSOLUTE MAXIMUM Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10oC to +70°C
RATINGS* Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +125°C
Supply Voltage, VGG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-15 to +0.3V
Input Voltages (Port A, INT, RESET) . . . . . . . . . . . . . . . . . . . . . . . .-15 to +0.3V
(Ports C, D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40 to +O.3V
Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40 to +O.3V
Output Current (Ports C, D, each bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4 mA
(Ports E, F, G, each bit) . . . . . . . . . . . . . . . . . . . . . . . . . -15 mA
(Total, all ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -60 mA
Ta= 25°C
'COMMENT: Stress above those lISted under "Absolute MaXimum Ratings" may cause permanent
damage to the deVice. ThiS is a stress rating only and functional operation of the device at these or
any other conditions above those Indicated
In
the operational sections of this specification is not
Implied. Exposure to absolute maximum rating conditions for extended pariods may affect device
reliability.
3-19
II
",PD550L/554L
T a'"
10°C to +70"C, VGG '" --8 OV
t
10%
DC CHARACTERISTICS
LIMITS
PARAMETER
Input Voltage High
Input Voltage Low
SYMBOL
MIN
TYP
MAX
UNIT
TEST
CONDITIONS
VIH
0
-1 6
V
Ports A, C, 0, INT, RESET
VILl
-45
VGG
V
Ports A, INT, RESET
VIL2
A5
-35
V
Ports C, 0
Clock Voltage High
V¢H
0
-06
V
CLO Input, External Clock
Clock Voltage Low
V"L
-50
VGG
V
CLO I nput, External Clock
Input Leakage Current High
ILiH
+10
"A
VI'" ---tV
I LlL,
-10
"A
Ports A, C, 0, tNT, RESET
V, = -9V
Ports C, 0, VI'" --35V
Ports A, C, 0, INT, RESET
I nput Leakage Current Low
III L2
-30
"A
Clock I nput Leakage Current High
IL¢H
+200
"A
CLO Input, V¢H - OV
Clock Input Leakage Current Low
IL¢L
-200
"A
CLO Input, V¢L '" -9V
VOH,
-1 0
V
Ports C, 0, IOH "" ··2 mA
VOH2
-25
V
Ports E, F, G. IOH '" -10 mA
'LOLl
-10
"A
ILOL2
-30
"A
-24
mA
MAX
UNIT
Output Voltage High
Ports C through G,
Vo = -9V
Output Leakage Current Low
Ports C through G,
Supply Current
~
IGG
12
Vo = -35V
Ta~25°C
CAPACITANCE
LIMITS
PARAMETER
SYMBOL
MIN
TYP
Input Capacitance
C,
15
pF
Output CapacitanCe
Co
15
pF
Input/Output Capacitance
C,O
15
pF
MAX
UNIT
T a ~ -10°C
to
TEST
CONDITIONS
f = 1 MHz
+70°C, VGG ~ -8.0V ± 10%
AC CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
MIN
TYP
f
100
180
KH,
Rise and Fall Times
tptf
0
0.3
Clock Pulse Width High
t¢WH
2~O
80
Clock Pulse Width Low
t~WL
2.0
8.0
"'
"'
"'
Oscillator Frequency
TEST
CONDITIONS
External Clock
1------1/f-------.1
CLOCK WAVEFORM
Package Outlines
For information, see Package Outline Section 7.
PlastiC, [J.PD550LC/554LC
3-20
550 L/554 LDS-2-82-CA T
NEe
",PD556B
",COM-4 4-BIT SINGLE CHIP
ROM-LESS EVALUATION CHIP
DE~CRI PTION
The I1PD556B is the ROM-less eva!uatlon chip for the I1COMA 4-bit single chip microcomputer family. The I1PD556B IS used In conjunction with an external 2048 x 8-blt
program memory, such as the I1PD2716 UV EPROM, to emulate each of the 14 different I1COMA single chip microcomputers.
The I1PD556B contains a 96 x 4-bit RAM, which Includes six working registers and the
Flag register. It has a level-triggered hardware interrupt, a three-level stack, and a programmable 6-bit timer. The I1PD556B executes all 80 instructions of the extended
I1COMA family Instruction set.
The I1PD556B provides 35 I/O lines organized into the 4-bit input Ports A and B, the
4-bit I/O Ports C and D, the 4-bit output Ports E, F, G, and H, and the 3-bit output
Port I. It tYPically executes ItS instructions with a 1Oils instruction cycle time. The
I1PD556B IS manufactured with a standard PMOS process, allOWing use of a single -1 OV
power supply, and IS available In a 64-pin quad-in-Ilne ceramic package.
PIN NAMES
PIN CONFIGURATION
PAO-PA3
Input Port A
PBO-PB3
Input Port B
PCO-PC3
I nput/Output Port C
PDO-PD3
Input/Output Port D
PEO-PE3
Output Port E
PFO-PF3
Output Port F
PGO-PG3
Output Port G
PHO-PH3
Output Port H
P10-P12
Output Port I
INT
Interrupt Input
10-7
Instruction Input
PCO-10
Program Counter Output
ACC/PC
Accumulator/Program
Counter Select
BREAK
Break Input
STEP
Single Step Input
CLO-CL1
External Clock Source
RESET
Reset
VGG
Power Supply Negative
VSS
Power Supply Positive
TEST
Factory Test Pm
(Connect to VSS)
3-21
IJ
IlP,D556B
BLOCK
DIAGR~~
Ace/PC
BA EAK
PA3_0
RAM
96,4
I
I
---SR EAK
AND
STEP
CONTROl_ STEP
P·SELECTOR
RAM
DECODER
PB3_0
UPI
DOWN
COUNT-
PC3_0
PD3.0
salT
CONTROL
AND
d-----:-- INT
PH3_0
'-----_ _ _ _ _11'"11_ _ _----'+,,'"
CL1
CLa
Operating Temperature ....
. . . . . . . . . . . . . . . . . . . . . . . -10°C to +70°C
Storage Temperature.
-40°C to +125°C
.................
-15Vto+O.3V
SupplyVoltage,VGG .....
All Input Voltages. . . . . . . . . . . . . . . . . . .
. ......... -15V to +O.3V
All Output Voltages. . . . . . . . . .
.. ......
-15V to +O.3V
Output Current (total, all ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4 mA
Ta = 25°C
'COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. Th,s is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
raliability.
3-22
ABSOLUTE MAXIMUM
RATlNGS*
IlPD556B
DC CHARACTERISTICS
Ta '" -looC to +70 0 C, VGG::: -10V ± 10%, VSS ::: OV
LIMITS
PARAMETER
SVMBOL
Input Hlqh
TV.
MIN
MAX
-2,0
VIH
TEST
CONOITIONS
UNIT
V
Ports A to 0, '7-0
BREAK, STEP,
Voltage
fiiJT,
RESET,
and Ace/PC
~------
Input Low
Voltaqe
-4,3
VIL
V
VGG
Ports A to 0,17_0
BREAK, STEP,
iNi'. RESET,
and Ace/PC
Clock Hlqh
Voltage
V,.,H
Clock Low
V"IL
-60
-O,S
V
CLO Input, External Clock
VGG
V
CLO Input, Extprnal Clock
>10
"A
Ports A and B, '7-0
Voltage
Input Leakaqe
Current Hlql1
Input Leaka(Je
Current Low
110
"A
Ports C and 0, VI" -1V
-10
"A
Ports A and B, 17.0
INf, RESET, BREAK. STEP,
ACC/PC, VI • -IIV
IUL
-10
"A
Ports C and D. VI
Clock Input
Leakage High
rL~'IH
t2QO
"A
CLO Input, External Clock,
V¢H =" OV
Clock Input
Leakage Low
I L':ll
-200
"A
CLO Input, External Clock,
VOH1
-10
V
Ports C to I, P,O-D
IOH ""-1.0 rnA
VOH2
-2.3
V
Ports C to I, PlO.0
IOH IE -3.3 rnA
Output Leakage
Current Low
ILOL
-30
"A
Ports C to I, P 10.0
VO=-IIV
Supply Current
IGG
-50
mA
Ta"
-1cfc to
-30
+7rf'C, VGG "" -10V ± 10%
LIMITS
PARAMETER
CAPACITANCE
SVMBOL
MIN
MAX
UNIT
150
TV.
440
KH,
0
03
"'
"'
Frequency
f()
Clock Rise and Fall Times
tr,tf
Clock Pulse Width High
t¢WH
05
56
Clock Pulse Width Low
t¢WL
05
56
Input Setup Time
'IS
Input Hold Time
tlH
0
BREAK to STEP Interval
tBS
200
STEP to RUN Interval
tSB
200
STEP Pulse Width
tws
30
5
BREAK to Ace Interval
tBA
200
ACC/PC Pulse Width
twA
30
STEP to Ace Interval
tSAl
200
PC to STEP Ovarlap
tSA2
PC to RUN Interval
tAS
ACCfPC
~
IIV
VL - -IIV
Output Hlqh
Voltage
AC CHARACTERISTICS
1NT. RESET. BREAK, STEP,
ACC/PC, VI --IV
ILiH
PlO-0 Delay
"'
"'
"'
"'
.,
"'
5
0
tDAPl
15
tDAP2
15
TEST
CONDITIONS
"'
"'
"'
.'"'
.'.'
f = 400 KHz, "1" Written
f - 400 KHz, "'" Wrttten
f - 400 KHz. "1" Written
f - 400 KHz, "'" Wrttten
f - 400 KHz, "1" Wrttten
f
400 KHz, "1" Wrttten
f '" 400 KHz, "1" Wrttten
f
400 KHz, "1" Written
f - 400 KHz, "1" Written
f "" 400 KHz, "1" Written
Ta=25°C
LIMITS
SYMBOL MIN
PARAMETER
TYP
MAX
TEST
UNIT CONDITIONS
Input Capacitance
CI
15
pf
Output Capacitance
Co
15
pf
Input/Output Capacitance
CIO
15
pf
3-23
f= 1 MHz
II
,..PD5568
CLOCK WAVEFORM
____x=
__'_f="]
TIMING WAVEFORMS
(PC)
17-0
BREAK
-+__________J
STEP _ _ _
ACC/PC
P10-0
(PCln
Package Outlines
For information, see Package Outline Section 7.
Ceramic Quil, fl-PD556B
3-24
556BDS-1-82-CAT
NEe
!-,PD7500 SERIES
CMOS 4·BIT SINGLE CHIP
MICROCOMPUTER FAMILY
Description
The IJPD7500 Series CMOS 4-Bit Single Chip
Microcomputer Family is a broad product line of 16
indi~idu~1 devices designed to fulfill a wide variety of
applications. The advanced 4th generation architecture
includes all of the functional blocks necessary for a
single chip controller, including an ALU, Accumulator,
Program Memory (ROM), Data Memory (RAM), four
General Purpose Registers, Stack Pointer, Program
Status Word (PSW), 8-Bit Timer/Event Counter,
Interrupt Controller, Display Controller/Driver, and 8-Bit
Serial Interface. The instruction set maximizes the
~fficient utilization of fixed Program Memory space, and
Includes a variety of addressing, Table-Look-up,
Logical, Single Bit Manipulation, vectored jump, and
Condition Skip Instructions.
The IJ PD7500 Series includes four different devices,
the ~PD7501, ~PD7502, ~PD7503, and IJPD7514, capable of directly driving Liquid Crystal Displays with up to
16 7-segment digits. The IJPD7508A, IJPD7528,
IJPD7517, ~PD7538, IJPD7537, and IJPD7519 can directly drive up to 35V Vacuum Fluorescent Displays with up
to 8 7-segment digits, and the IJPD7519 can directly
drive up to 35V Vacuum Fluorescent Displays with up to
16 7-segment digits.
All 16 devices are manufactured with a Silicon gate
CMOS process, consuming only 900IJA max at 5V, and
only 400IJA max at 3V. The HALT and STOP powerdown instructions can significantly reduce power
consumption even further.
The flexibility and the wide variety of IJPD7500 Series
devices available make the IJPD7500 series ideally
suited for a wide range of battery-powered, solarpowered, and portable products, such as telecommunication devices, hand-held instruments and meters,
automotive products, industrial controls, energy
management systems, medical instruments, portable
terminals, portable measuring devices, appliances, and
consumer products.
Features
D Advanced 4th Generation Architecture
D Choice of 8-Bit Program Memory (ROM) size:
- 1K, 2K, 4K internal, or 8K external bytes
D Choice of 4-Bit Data Memory (RAM) size:
- 64,96, 128,208,224, or 256 internal nibbles
D RAM Stack
D Four General Purpose Registers: 0, E, H, and L
- Can address Data Memory and 110 ports
- Can be stored to or retrieved from Stack
D Powerful Instruction Set
- From 58 to 110 instructions, including:
- Direct/indirect addressing
- Table Look-up
- RAM Stack Push/Pop
- Single byte subroutine calls
- RAM and 110 port single bit manipulation
- Accumulator and 110 port Logical operations
- 10 IJS Instruction Cycle Time, typically
D Extensive General Purpose 110 Capability
- One 4-Bit Input Port
- Two 4-Bit latched tri-state Output Ports
- Five 4-Bit inputllatched tri-state Output Ports
- Easily expandable with IJPD82C43 CMOS 110
Expander
- 8-Bit Parallel 110 capability
D Hardware Logic Blocks - Reduce Software
Requirements
- Operation completely transparent to instruction
execution
- 8-Bit Timer/Event Counter
- Binary-up counter generates INTT at
coincidence
- Accurate Crystal Clock or External Event
operation possible
- Vectored, Prioritized Interrupt Controller
- Three external interrupts (INTO, INT1, INT2)
- Two internal interrupts (INTT, INTS)
- Display ControlierlDriver
- Complete Direct Drive and Control of Multiplexed LCD or Vacuum Fluorescent Display
Display Data automatically multiplexed from
RAM to dedicated segment/backplane/digit
driver lines
- 8-Bit Serial Interface
3-line 110 configuration generates INTS upon
transmission of eighth bit
- Ideal for distributed intelligence systems or
communication with peripheral devices
- Complete operation possible in HALT and STOP
power-down modes
D Built-in System Clock Generator
D Built-in Schmidt-Trigger RESET Circuitry
D Single Power Supply, Variable from 2.7V to 5.5V
D Low Power Consumption Silicon Gate CMOS
Technology
- 900 IJA max at 5V, 400 IJA max at 3V
- HALT, STOP Power-down instructions reduce
power consumption to 20 IJA max at 5V,
1DIJA at 3V (Stop mode)
D Extended - 40°C to + 85°C Temperature Range
Available
D Choice of 28-pin, 40-pin, 42-pin dual-in-linepackages, or 52-pin, 64-pin, or 80-pin flat plastic
packages.
Rev/1
3-25
3
1:
7500 7501 7502 7503 7514
Feature.
Internal ROM
1K
2K
4K
4K
(a-blt words)
8K
Expandable to
256x4 96x4 128x4 224x4 256x4
RAM
24
23
23
67
32
110 Unes
8-BIt TlmerlEvent
•
•
•
•
•
Counter
8-BH Serial Interface
•
•
•
•
•
2x4
4x4
4x4
Registers Outside RAM 4x4
92
110
63
92
92
Instructions
6.67
6.67
6.67
5
6.67
Min Cycle Time (/ls)
4
4
4
4
5
Interrupts
RAM
RAM
RAM
RAM
RAM
Stack Levels
Display
LCD
LCD
LCD
LCD
Controllerl
Driver
c.>
I
I\)
7506
1K
7507 75075 7508 750BA 7519
2K
2K
4K
7537
7538
2K
4K
2K
4K
•
2x4
58
6.67
2
RAM
•
•
•
4x4
92
6.67
4
RAM
•
•
•
•
•
•
•
4x4
91
6.67
4
RAM
4x4
92
6.67
4
RAM
4x4
92
6.67
4
RAM
VFD
drive
4x4
92
6.67
4
RAM
VFD
only
•
•
•
•
•
•
•
•
2x4 2x4
2x4 2x4
67
67.
66
66
4
4
4
4
3
3
3
3
RAM
RAM
RAM
RAM
VFD
VFD
VFD
VFD
DRIVE DRIVE DRIVE DRIVE
ONLY ONLY ONLY ONLY
14-bit
D/A
...
900
20
....
-10"C
to ..
IlA at
IlA at
5V ± 10%; 4001lA at 3V ± 10%
5V ± 10%; 101lA at 3V ± 10%
-40°C
to
+70"C
+85°C
Package.
2a-pln DIP
40-pln DIP
52-!!ln Flat
64-l!ln Flat
64-pln QUIL
42-pln DIP
80-pln Flat
4K
7528
64x4 128x4 128x4 224x4 208x4 256x4 160x4160x4160x4160x4
20
32
32
28
32
35
35
22
35
35
Analog 1/0
en Current Consumption
(max)
Normal Operation
Stop Mode
Operating
Temperature Range
4K
7527
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
"--aen
~
0
0
U)
m
:II
m
U)
IAPD7500 SERIES
Instruction Set
The ",P07500 Series Instruction Set consists of 110
powerful instructions designed to take full advantage of
the advanced ",P07500 architecture in your application.
It is divided into two subsets, according to the
complexity of the device.
Instruction Set "A" is available for the higherperformance ",P07500 Series devices having either a
2K x 8-bit or a 4K x 8-bit Program Memory. It can be
used with the ",P07500, ",P07502, ",P07503, ",P07507,
",P07507S, ",P07508, ",P07508A, ",P07519, ",P07514,
",P07527, ",P07528, ",P07537, and ",P07538 products.
Instruction Set "B" is available for the lower-cost
",P07500 Series devices having a 1K x 8-bit Program
Memory. Its instructions are a compatible subset of
Instruction Set "A," and can be used with the
",P07500, ",P07501, and I-IP07506 products.
Instruction Set Symbol Definitions
The following abbreviations are used in the description
of the I-IP07500 Series Instruction sets:
Symbol
A
An
addr
bit
Bit "n" of two-bit operand
Bl
Bel
Bit Specified
Bn
Bank
borrow
C
data
D
On
DE
DL
E
-0
o
-0
BiiO(i:SB)
1
1
0
1
1
Bit 1
Bit 2
Bit 3 (MSB)
Bank Flag of PSW (,uPD7500 only)
Resulting value Is less than OH
Carry Flag
Immediate data operand
0 Register
Bit "n" of Immediate data operand
DE Register Pair
DL Register Pair
3
E Register
H
~H=L
Accumulator
Bit "n" of Accumulator
Address
Operand specifying one bit of a nibble
H Register
______~H=L~R=e~gl=st~e~rp~a~lr~~_______________________________
IER
IRFn
Interrupt Enable Register
IERblt:
0
1
Interrupt:
INTT
INTO/S
Interrupt Master Enable F/F
Interrupt "n"
Interrupt Request Flag "n"
overflow
L Register
Resulting value Is greater than FH
IME
INTn
P( )
PC
PCn
PSW
2
INT1
3
INT2
Parallel Input/Output Pan addressed by the value within the parentheses
Program Counter
Bit "n" of Program Counter
Program Status Word
PSWblt:
0
1
2
3
NOT
Flag:
Carry
Bank
SKO
SK 1
Register Pair, specified by the 3-blt immediate data operand 02-0, as
follows:
02
01
DO
rp
Additional Action
--0 --0 DL
none (Instruction set "A" only)
o
0
1
DE
none (instruction set "A" only)
1
0
0
HL decrement L; Skip If L = FH
1
0
1
HL +
Increment L; skip if L = OH
11
OHL
none
Skip Cycles: 0 when Skip condition does not occur
1 when skip condition does occur
Serial 110 Shift Register
Serial 110 Count Register
Stack Pointer
String Effect; In a string of similar instructions, only the first
encountered Is executed; the remainder of the Instructions In the string
are executed as NOP Instructions
Operand specifymg ROM Table Data
Bit "n" of ROM Table Data
Timer Counter Register
Timer Modulo Register
The contents of the RAM location addressed by the value within the
parentheses
The contents of the ROM location addressed by the value within the
brackets
Load. Store, or Transfer fight operand into left operand
Exchange the left and fight operands
Logical NOT (One's comptement)
AND
LOGICAL AND
rp
o
S
SIO
SIOCR
SP
String
taddr
Tn
TCR
TMR
( )
--.OR
XOR
3-27
LOGICAL OR
LOGICAL Exclusive OR
Instruction pertains to ~P07500 only
~PD7500
SERIES
Instruction Set "A"
For the flPD7500, flPD7502, flPD7503, flPD7507, flPD7507S, flPD750B, flPD750BA, and flPD7519 devices only
Instruction Code
Mnemonic
Function
De.crlptlon
Byte.
D7
De
DS
D4
D3
D2
D1
Do
HEX
1
05
1
D4
1
D3
0
D2
0
01
0
DO
OO-FF
03
02
0,
DO
10-1F
Dl
DO
40,41
50-52
Cycl••
Skip Condition
Lo.d
LADR addr
Load Accumulator
from directly
addressed RAM
A-(D7-0)
LAI data
A-03 _0
Load Accumulator
with Immediate
data
LAMrp
A-(rp)
rp = OL, DE, HL-, HL+, HL
If rp
HL -, skip if borrow
If rp = HL + , skip if overflow
Load Accumulator
from Memory,
possible $klP
=
=
LAMT
("PD7500, "PD7502
only)
ROM addr
PC10-6,
0, C, Aa_o
A-[ROM addr)7_4
(HL)-[ROM addr)3_0
Load Accumulator
and Memory from
Table
LAMTL
/APD7503,
jJPD7507, ",PD7S07S,
/JPD7S0B, ,uPD7508A,
,wPD7519, only)
LoEI data
ROM addr = PC11-8,
A3_0, (HL)3_0
A-[ROM addr)7_4
(HL)-[ROM addr)3_0
Load Accumulator
and Memory from
Table Long
0-07_4
Load DE register
pair with Immedl~
ate data
Load 0 register
with immediate
data
~PD7S00.
E-0 3_0
Lol data
D-0 3_0
LEI data
E-D3_0
LHI data
H-03_0
0
07
0
06
02
1
H-07~4
L-D3~O
LHLT taddr
ROM addr
OCOH + D3~O
H-[ROM addr)7_4
L -[ROM addr)3_0
LLI data
L-03-D
ST
(HL)-A
Load HL register
pair with Immedlate data
=
String
l+S
See explanation
of "rp" in symbol
definitions
5E
3F
34
0
07
1
D6
0
05
D.
Load E register
with immediate
data
Load H register
with Immediate
data
LHLI data
38
0
D7
1
D6
0
05
0
04
Load HL register
pair from ROM
Table
Load L register
with immediate
data
1
03
1
02
1
Dl
DO
OO~FF
4F
1
03
1
02
1
Dl
0
DO
20~2F
1
03
1
02
1
0,
0
DO
3E
OO-OF
1
03
1
02
1
Dl
0
DO
30~3F
1
03
1
02
1
Dl
0
DO
4E
OO-FF
String
D3
D2
Dl
DO
CO-CF
String
1
03
1
02
1
Dl
0
DO
3E
10-1F
3E
3E
Store
Store A to Memory
1
57
0
Tran.f.r
TAD
O-A
Transfer A to 0
3E
AA
TAE
E-A
Transfer A to E
3E
8A
TAH
H-A
Transfer A to H
3E
BA
TAL
L-A
Transfer A to L
3E
9A
TDA
A-D
Transfer 0 to A
3E
AB
TEA
A-E
Transfer E to A
3E
8B
THA
A-H
Transfer H to A
3E
BB
TLA
A-L
Transfer L to A
3E
9B
Exchang.
XAO
A-D
Exchange A with 0
XAoR addr
A-(07_0)
Exchange A with
directly addressed
RAM
Exchange A with E
Exchange A with H
1
07
0
06
0
1
05
4A
1
04
1
D3
XAE
A-E
XAH
A-H
XAL
A-L
A-(rp)
DL, DE, HL-, HL+,HL
rp
if rp
HL -, skip If borrow
if rp = HL +, skip if overflow
E::xchange A with L
Exchange A with
Memory, Possible
Skip
XHDR addr
H-(D7-0)
Exchange H with
directly addressed
RAM
0
D7
0
06
1
D5
1
D4
1
D3
XLDR addr
L-(07_0)
Exchange L with
directly addressed
RAM
0
07
D6
1
D5
1
04
1
03
XAM rp
=
=
0
02
0,
1
DO
39
OO-FF
4B
7A
7B
01
DO
44,45
54-56
0
D2
1
01
0
DO
3A
OO-FF
0
D2
1
Dl
1
DO
3B
OO-FF
02
3-28
1+5
See explanation
or "rp" in symbol
definitions
",PD7500 SERIES
Instruction Set "A" (Cont.)
For the ~PD7500, ~PD7502, ~PD7503, ~PD7507, ~PD7507S, ~PD7508, ~PD7508A, and ~PD7519 devices only
In.tructlon Code
Mnemonic
Function
Byt..
D7
De
Ds
D4
D3
DZ
D1
DO
HEX
ANL
A-A AND (HL)
AND Accumulator
and Memory
3F
B2
EXL
A-A XOR (HL)
Exclusive-Or
Accumulator and
Memory
7E
ORL
A-A OR (HL)
OR Accumulator
and Memory
3F
B6
, ,
Accumulator
CMA
A-NOT A
Complement
Accumulator
AMBblt
(HLlblt-O
bIt
B,.O (0·3)
Reset Memory bit
5MBbit
(HLlblt-t
bit
B,.O (0·3)
Set Memory bit
=
=
0
, ,
Bit Manipulation
0
0
3-29
7F
B,
BO
68-68
B,
BO
6C·6F
Cycl••
Skip Condition
~PD7500
SERIES
Instruction Set "A" (Cont.)
For the ,..PD7500, ,..PD7502, ,..PD7503, ,..pD7507, ,..PD7507S, ,..PD7508, f'PD7508A, and ,..PD7519 devices only
Inatructlon Code
Mnemonic
Function
o.acrlptlon
D7
De
D4
D3
D2
D,
Do
HEX
Os
04
0
03
0'0
02
Dg
0,
Os
DO
30-37
OO-FF
Os
04
03
02
0,
DO
DIl-FF
DS
, ,
Brt••
ere.••
Sklp- Condition
B,.nch
CALL addr
CALT addr
JAM data
(SP-')-PC7-4
(SP - 2)-PC3_0
(SP-3)-PSW
(SP -4)-PC11_'S
SP-SP-4
BANK-O
PC11-0
PC'O.o-O,O-O
(SP -')-PC7-4
(SP - ')-PC3-0
(SP-3)-PSW
(SP - 4)-PC11_&
ROM addr = OCOH + Os-a
BANK-O
PC11_'O-OO
PC9_7-[ROM addr!7_S
PC6_S-00
PC4_0-[ROM addr!4_0
PC11_S-D3_0
Call subroutine
0
07
0
06
Call subroutine
through ROM Table
(single byte)
, , , ,
PC7~4-A
03
02
0,
DO
3F
'O-'F
03
02
0,
DO
SO-BF
PC3_0-(HL)
JCP addr
PCS-O-Ds-O
Os
04
SP-SP + 4
RTPSW
PC11_S-(SP)
PSW-(SP+')
PC3-0-(SP + 2)
PC7_4-(SP +3)
Return from
43
Subroutine and
restore PSW
SP-SP+4
RTS
PC11_S-(SP)
BANK-(SP+')
PC3_0-(SP + 2)
PC7-4-(SP +3)
SP-(SP+4)
Skip unconditionally
Return from
Subroutme; then
E-(SP)
D-(SP+')
Pop DE register
pair off Stack
SB
Unconditional
Instruction
St.ck
POPDE
, +S
skip next
0
0
,
3E
SF
0
SP-SP+2
POPHL
L-(SP)
H-(SP+')
Pop HL register
pair off Stack
3E
9F
SP-SP+2
PSHDE
(SP-')-D
(SP-2)-E
SP-SP-2
Push DE register
pair on Stack
3E
SE
PSHHL
(SP-')-H
(SP-2)-L
SP-SP-2
Push HL register
pair on Stack
3E
9E
TAMSP
SP7-4-A
SP3_,-(HL)3_'
SPO-O
A-SP7_4
(HL)3_,-SP3_'
(HL)O-O
Transfer Accumulator and Memory
to Stack Pomter
3F
3'
Transfer Stack
Pointer to
3F
3S
TSPAM
Accumulator and
Memory
, , ,
Condition•• Skip
SKABT bit
SKAEI data
Skip if Ablt = 1
bI1
B,_O(O-S)
=
Skip If A
SKAEM
Skip if A
SKC
SKDEI data
SklptfC
= 03-0
=(HL)
=1
Skip If D = 03-0
Skip if Accumulator
0
bit true
Skip if Accumulator
B,
03
equals Immediate
BO
74·71
,+S
Abit = 1
2+S
A
DO
3F
60-6F
SF
,+S
A
SA
3E
60-6F
3E
40-4F
1+S
C
, , , ,
02
0,
data
Skip if Accumulator
equals Memory
,
, , ,
, , ,
, , ,
SkIp If Carry
Skip If 0 equals
Immediate data
03
02
0,
03
02
0,
SKEEl data
Skip if E
= 03-0
Skip If E equals
Immediate data
SKHEI data
Skip 'f H
= 03-0
Skip .f H equals
Immediate data
03
3-30
02
0,
0
Do
0
DO
0
DO
3E
70-7F
2+S
2+S
2+S
= 03-0
= (HL)
=,
o = 03_0
E = 03-0
H = 03-0
",PD7500 SERIES
Instruction Set "A" (Cont.)
For the I'PD7500, I'PD7502, I'PD7503, I'PD7507, I'PD7507S, I'PD7508, I'PD7508A, and ,.pD7519 devices only
In..NOtIon Code
Mnemonic
SKLEI data
Function
D7
Ds Ds D4
e o n _ S ..... ICont.,
0
0
1
1
1
1
0
0
0
SldpHLmD:J.O
SKMBF bit
TAMMDD
TMR7-4-A
TMfI3.o-IHL)
D!
...
1
D3
0
1
D2
0
Deoorlptlon
1Iyt. .
Dt
Do
"U
1
Dl
Bl
0
DO
3E
50.5F
1Q.83
Bo
CpIH
SIdp Condftlon
= D3.o
2+S
L
I+S
IHL)blt • 0
2+S
IRFn
3F
3F
Tranlfer
Accumulator and
Memory to Timer
Modulo Raglator
TCNTAM
3F
3B
Transfer Timer
A-TCR7-4
(HL)-TCR3-0
Count Reglat., 10
TIMER
TCR7·0-il
Memory
Start Timer
DI data
IME F/F-il II data = 0
IER3-0-IER3.0 AND NOT
D3.0 II data < > 0
Disable Interrupt.
Interrupt Maater
Enable FIF or
EI data
IME F/F-1 If da'a • 0
IER:J.O-IER3.0 OR D:J.O
Ildate<>O
Enable Interrupt,
Interrupt Mastar
Enable F/F or
Sldp IllRFn AND D3-0 < > 0
specified
Sldp II Interrupt
Request Fleg I.
true
Accumulator and
SKI data
IRF~
IRFn+-IRFn AND NOT 03-0
SIO
TAMSIO
SIOCR-O
IRFO/S-O
SI07-4-A
SI03.o-(HL)
TSIOAM
A-SI07-4
(HL)-SI03·0
ANPdata
P(P3-0)-P(P3-0) ANO 03-0
IP port
A-P(P:J.O)
IPI (axcept
.P075078)
IP54
A-P(I)
IPL
A-P(5)
(HL)-P(4)
A-P(l)
OPport
P(P3-0)-A
OP3
OP54
OPl
P(3)-A
P(5)-A
P(4)-(Hl)
P(l)-A
ORP data
P(P3.o)-(P:J.O) OR 03.0
3F
32
Int........ Control
1
0
0
1
1
0
0
0
1
D3
1
D2
1
D3
1
D2
1
D2
1
Dl
1
Dl
1
DO
3F
8O·8F
1
1
Dl
DO
3F
80-8F
1
DO
3F
40.4F
apeclfled
Start $orlalllO
Operation
Transfer Accumulator and Memory
1051 Shift
Register
Transfer 51 Shift
Reglater to Accumulator and Memory
AND output port
latch with
1
D3
.....lln......c.
0
0
1
1
0
0
1
3F
33
3F
3E
3F
3A
0
03
........11/0
1
0
02
01
0
00
Immediate data
Input from port.
Immediate add.....
Input from Pon 1
Input Byte trom
Porta 5 and 4
Input from Port
specifled by L
Output to port.
Immediate addreu
Output to Port 3
Output Byte to
Porta 5 and 4
Output \0 port
apoclflod by l
OR output port
latch with
=-
1
1
P3
P2
1
P3
0
pz
1
0
PI
0
Po
4C
Oo.FF
1
PI
0
1
Po
3F
co.cF
71
3F
38
70
0
0
D3
1
02
0
Dl
0
Do
1
P3
0
1
P2
0
1
PI
1
Po
1
P3
1
P2
0
PI
1
Po
3F
ED-EF
73
3F
3C
72
4D
Oo.FF
:~~:=P--------------------------------~::~t~:~~;=~=O=I:~~~O-d~.--~--~---7--~--~--~--~--~--~:=~~--~~----~-------------37
3-31
",PD7500 SERIES
Instruction Set "B"
For the IlPD7500, IlPD7501, and IlPD7506 devices only
Instruction Code
Function
Mnemonic
art..
D ••crlptlon
D7
LADR addr
A-(D6-0)
LAI data
A-D3-0
Load Accumulator
with immediate data
A-(rp)
HL-, HL+, Hl
rp
If rp = HL -, skip If borrow
If rp = Hl + , skip If overflow
Load Accumulator
from Memory,
possible skip
LAMT
=
D4
D2
D,
DO
HEX
03
0
D2
0
D,
0
DO
38
Oo-SF
03
02
0,
DO
'O-'F
0,
DO
50·52
D3
, , ,
Load Accumulator
from directly
addressed RAM
LAMrp
De
D5
Load
0
D6
D5
04
eVel••
Skip Condition
Strmg
1 +S
See explanation
of "rp" In symbol
definitions
5E
ROM addr = PC10-6,
0, C, A3-0
LHLI data
Load HL register
pair with immediate data
04
(HL)-A
(HL)-D3-0
l-L + 1
Store A to Memory
Store Immediate
CO-OF
, " ,
40-4F
02
03
02
0,
DO
0
02
0
0,
DO
Stor.
5T
STU data
DO
0,
03
String
S7
data and
Increment L
, , ,
Exch.nge
XADR addr
A-(D6-Q)
0
06
Exchange A with
directly addressed
RAM
Exchange A with H
DS
04
03
,
XAH
A-H
XAL
XAMrp
A-L
A-(rp)
rp
HL-,HL+,HL
If rp
HL -, skip If borrow
If rp
HL +, skip If overflow
Exchange A with L
Exchange A with
Memory, Possible
Skip
XHDR addr
H-(06-0)
Exchange H with
directly addressed
RAM
0
06
D5
04
D3
0
D2
Exchange L with
directly addressed
RAM
0
06
D5
04
D3
03
XLDR addr
=
=
=
L-(D6_0)
,
7A
DO
78
54-56
0,
0
DO
3A
00-5F
0
02
0,
DO
0O-5F
02
0,
DO
7C
0,
, , ,
, , ,
39
DO-SF
,
, ,
, ,
1+5
See explanation
or "rp" in symbol
deflnttions
7C
1+5
Carry
OO-OF
'+5
Overflow
1+5
Carry
38
Altlthmetlc
AC5C
A, C-A±(HL)+C
skip if carry
AISC data
A-A + D3-o
skip If overflow
A-A + (HL)
skip If overflow
A5C
ANL
A-A AND (HL)
EXL
A-A XOR (HL)
ORL
A-A OR (HL)
Add with carry;
skip If carry
Add immechate;
skip it overflow
Add memory; skip
if overflow
Loglca.
0
0
AND Accumulator
and Memory
Exclusive-Or
Accumulator and
Memory
3F
82
7E
3F
OR Accumulator
and Memory
86
, ,
Accumulator
CMA
A-NOT A
Complement
Accumulator
RAR
C-AO
AO-A,
A1-A2
A2-A3
A3-C(old)
Rotate
Accumulator fight
through Carry
RC
C-O
5C
C-'
Reset Carry
Set Carry
0
7F
3F
83
,
, , ,
Program Statu. Word
0
3-32
78
79
=1
=1
JAPD7500 SERIES
Instruction Set "B" (Cont.)
For the
~PD7500, ~PD7501,
and
~PD7506
devices only
Instruction Code
Mnemonic
Function
D ••crlptlon
Byte.
D.
DDRS addr
(06.0)-(06.0) - ,
skip II (06.0)
FH
=
D8
DS
D4
D3
Increment and Decr•••nt
0
0
Decrement directly
addressed RAM;
0
06
05
04
03
D2
, , , ,
02
D,
Do
HEX
0
0,
0
Do
3C
OO·SF
C,cl ••
2.S
Skip Condition
(06.0)
= FH
skip If borrow
L-L - ,
OLS
= FH
skip If L
IDRS addr
(06.0)-(06.0) • ,
skip II (06.0)
OH
ILS
L--L + 1
=
skip If L
= OH
Decrement L; skip
I'borrow
Increment directly
addressed; skip If
overflow
, , , ,
05
04
03
02
0
0,
,
DO
Increment L; skip If
overflow
RMBblt
(HL)blt-O
bit
B,.O (0·3)
Reset Memory bit
5MBblt
(HL)b~-'
Set Memory bit
=
0
06
, ,
Bit Manipulation
0
0
bit = B,.O (0·3)
, ,
= FH
=OH
56
'.S
L
3D
OO·SF
2.S
(06.0)
59
'.S
L
B,
BO
68·6B
B,
BO
6C·6F
=OH
Branch
CALL addr
CAL addr
JAM data
JCP addr
RT
RTS
(SP-,)-PC7.4
(SP - 2)-PC3.0
(SP-3)-PSW
(SP-4)-PC'O·8
SP-SP-4
BANK-O
PC'O.O-O'CJ.O
(SP -')-PC7.4
(SP - 2)-PC3.0
(SP-3)-PSW
(SP-4)-PC,O.a
BANK-O
PC,O.O001D40300002D,DO
Call subroutine
0
07
0
06
05
Call.hort to
CAL address
30w37
04
0
03
0'0
02
D9
0,
D6
DO
OCJ.FF
04
03
D2
D,
DO
'ECJ.FF
II
subrountlne
, , ,
PC, 0.8-02.0
PC7·4-A
PC3·0-(HL)
PC5·0-05·0
Vectored Jump on
Accumulator and
Memory
PC'O·6-(SP)
BANK-(SP.')
PC3.0-(SP.2)
PC7·4-(SP.3)
SP-SP.4
PC'O.a-(SP)
BANK-(SP.')
PC3.o-(SP.2)
PC7.4-(SP.3)
SP-SP • 4
Return from
Subroutine
53
Return from
5B
05
04
03
02
D,
DO
3F
'0·17
02
0,
DO
80·BF
,.S
Unconditional
Subroutine; then
skip next
Instruction
Skip unconditionally
TAMSP
SKABT
SP7·4-A
b~
SKAEI data
Skip II Ablt = ,
bit = B'.0(0·3)
Skip II A = 03.0
SKAEM
Skip II A
SKC
SKLEI data
SklpllC='
Skip II L 03.0
SKMBF bit
= (HL)
=
Skip If Accumulator
bit true
Skip If Accumulator
equals Immediate
B,
03
02
0,
=,
BO
74-77
,.S
Ab~
2.S
A = 03-0
DO
3F
GO·6F
SF
,.S
A
'.S
2.S
C
=(HL)
=,
0
DO
BO
SA
3E
SO·SF
60·63
L
= D3-0
'.S
(HL)blt
, , , ,
data
Skip If Accumulator
equals Memory
Skip If Carry
Skip If L equals
Immediate data
Skip If Memory
bit false
, , ,
03
3-33
02
0,
B,
=0
J-lPD7500 SERIES
Instruction Set
"a" (Cont.)
For the ~PD7500, ~PD7501, and ~PD7506 devices only
Instruction Code
Function
Mnemonic
Description
D7
D6
Tlmer/Event
TAMMOD
TMR7_4-A
TMR3_0-(HL)
Transfer
Accumulator and
Memory to Timer
Modulo Register
TCNTAM
(except J.jPD7506)
A-TCR7_4
(HL)-TCR3_0
Transfer Timer
Count Register to
Accumulator and
Memory
TIMER
TeR7_0-a
Clear Timer
Counter Register
IRFT+-O
SKI data
Skip .f 1RFn AND 03-0 < > 0
IRFn-IRFn AND NOT 03-0
Skip If Interrupt
Request Flag is true
SID
(except J,lPD7S06)
SIDCR-O
IRFOtS-O
Start Senal 110
Operation
TAMSID
(except IlPD7506)
SI07_4-A
SI03_0-(HL)
lator and Memory
TSIOAM
(except /.lP07506)
A-SID7_4
HL-SI03_0
Transfer 510 Shift
Register to
Accumulator and
Memory
IP port
A-P(P3_0)
Input from port,
Immediate address
IPI
IP54
A-(I)
A-P(5)
(HL)-P(4)
Input from Port 1
IPL
A-P(L)
Input from Port
specified by L
OPport
P(P3-0)-A
Output to port,
Immediate address
OP3
(except JAPD7506)
P(3)-A
Output to Port 3
0
DS
D4
D.
D2
D,
DO
HEX
By' ••
Cycl.s
Skip Condition
~ount.r
0
1
3F
3F
3F
3B
3F
32
Interrupts
1
0
0
1
02
1
01
1
DO
Serial Interface
1
0
0
0
0
1
3F
40-41
2+S
1RFn
=1
3F
33
3F
3E
Transfer Accumuto SIO Shift Register
3F
3A
Par.llell/O
1
0
1
0
1
P3
1
P2
0
1
PI
1_
Po
3F
CO-CF
71
3F
38
70
1
P3
0
1
P2
1
PI
1
Po
3F
EO-EF
Input Byte from
Ports 5 and 4
73
OP54
STOP
3F
37
Enter STOP Mode
Development Tools
For software development, editing, debugging, and
assembly into object code, the NOS Development
System, designed and manufactured by NEC
Electronics U_S.A., Inc_, is available_ Additionally, for
systems supporting either the ISIS-II (®Intel Corp_),
CP/M (® Digital Research Corp_) operating systems, or
Fortran IV ANSI 1966 V3_9, the ASM75 CrossAssembler is available_
Once software development is complete, the code can
be completely evaluated and debugged with hardware
by the Evakit-7500 Evaluation Board_ Available options
include the Evakit-7500-LCD LCD driver board (for the
I-IPD7501, I-IPD7502, and I-IPD7503), Evakit-7500-VFD
Vacuum Fluorescent Display driver board (for the
I-IPD7508A and I-IPD7519), and the Evakit-7500-RTT
Real Time Tracer. The SE-7502 System Emulation
Board will emulate complete functionality of the
I-IPD7501, I-IPD7502, or I-IPD7503 for demonstrating your
final system design_ The SE-7508 System Emulation
Board will emulate complete functionality of the
I-IPD7506,I-IPD7507,I-IPD7507S,I-IPD7508,orI-lPD7508A
for demonstrating your final system design_ All of these
boards take advantage of the capabilities of the
I-IPD7500 Rom-less evaluation chip to perform their
tasks_
Complete operation details on any I-IPD7500 Series
CMOS 4-Bit Microcomputer can be found in the
I-IPD7500 Series CMOS 4-Bit Microcomputer Technical
Manual.
7500DS-REV1-7-83-TRIUM-CA T
3-34
NEe
IJPD7501
CMOS 4·BIT SINGLE CHIP
MICROCOMPUTER WITH LCD
CONTROLLER/DRIVER
Description
The ",PD7501 is a CMOS 4-bit single chip microcomputer which has the ",PD750x architecture.
The ",PD7501 contains a 1024 x 8-bit ROM, and a 96 x
4-bit RAM.
The ",PD7501 contains two 4-bit general purpose
registers located outside RAM. The subroutine stack is
implemented in RAM for greater nesting depth and flexibility, providing such operations as the pushing and
popping of register values. The ",PD7501 typically executes 63 instructions of the ",PD7500 series "8"
instruction set with a 10",s instruction cycle time.
The ",PD7501 has two external and two internal edgetriggered testable interrupts. It also contains an 8-bit
timer/event counter and an 8-bit serial interface to help
reduce software requirements. The on-board LCD controller/driver supervises all of the timing required by the
24 Port S segment drivers and the 4 Port COM backplane drivers, for either a 12-digit 7-segment quadriplexed LCD, or an 8-digit 7-segment triplexed LCD.
The ",PD7501 provides 24 110 lines organized into the
4-bit input/serial interface Port 0, the 4-bit input Port 1,
the 4-bit output Port 3, and the 4-bit I/O Ports 4, 5, and
6. It is manufactured with a low power consumption
CMOS process, allowing the use of a single power supply between 2.7V and 5.5V. Current consumption is
less than 900",A maximum, and can be lowered much
further in the HALT and STOP power-down modes. The
",PD7501 is available in a space-saving 64-pin flat
plastic package.
The ",PD7501 is upward compatible with the ",PD7502
and the ",PD7503.
Pin Configuration
Pin Identification
Pin
s,
s,
s"
Sn
COMO
COMl
cc,
o
COM2
",PD7501
0
Voo
'"
'"
'"
4-blt latched trl-state output Port 3 (active high).
2-4,64
P33·P30
P03/S1
4-blt Input Port Olser!al 1/0 Interface (active high).
This port can be configured either 8S a parallel Input port,
or 8S the 8-blt s8rl81 1/0 Interface, under control of the
55
P02/S0
POl/SCi<
POo'lNTl
s.rlal mode select register. The Serial Input SI (active
~)(a:I~:II~:~P~~e:~~~~~~~~~:~jz~;: ~::a~~=~~f~:~Ck
comprise the a·bit serial If 0 Interface. Line POO Is always
shared with edernal Interrupt INT l'
8-11
PIIa·P60
12·15
P53·P50
16·19
P43·P40
20.21
X2. Xl
22
23-25
VSS
VlCD3' VlCD2'
VlCDl
26.58
VDD
27-30
31·54
56
523.5 0
RESET
57.59
Cl 1• Cl2
60·63
P1 3•P1 0
(PIOIINTOJ
COM3-COMO
4-blt Input/latched trl-state output Port 6 (active high).
Individual lines can be configured either a8 inputs or as
outputs under control of the Port 6 mode select register.
4-bit input/latched tri-state output Port 5 (active high). Can
also perform 8-bit parallel 110 in conjunction with Port 4.
4-blt inputllatched tri-state output Port 4 (active high). Can
also perform 8-bit parallel 110 In conjunction with Port 5.
Crystal clock/external event input Port X (active high). A
crystal oscillator circuit Is connected to input Xl and output X2 for crystal clock operation. Alternatively. external
event pulses are connected to Input X1 while output X2 Is
left open for external event counting.
Ground.
LCD bias voltage supply inputs to LCD voltage controller.
Apply appropriate voltages from a voltage ladder connected across VOD'
Power supply positive. Apply single voltage ranging from
2.7V to 5.5V for proper operation.
lCO backplane driver outputs.
LCD segment driver outputs.
RESET Input (active high). RIC circuit or pulse Initializes
"PD7501 after power-uj:t.
System clock Input (active high). Connect 82kQ resistor
across Cl l and CL2. and connect 33pF capacitor from
Cll to VSS' Alternatively, an external clock source may
be connected to Cll. whereas Cl2 Is left open.
4-blt Input Port 1 (active high). Line Pl0 18 also shared
with external interrupt INTO.
"
"
= 25·C
Operating Temperature
Storage Temperature
Power Supply Voltage, VOO
All Input and Output Voltages
Output-Current (Total. All Output Ports)
COM3
'"
P101 1NTO
No connection.
Absolute Maximum Ratings·
So
Voo
NC
5
Ta
cc,
Function
S,mbol
No.
-10·Cto +70·C
-65·Cto + l50·C
-O.3Vto +7.0V
-O.3VtoVoO +O.3V
IOH'" -20mA
IOL = 30mA
'Comment: Stress above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Rev/1
3-35
EJ
'
",PD7501
Block Diagram
P01/SCK
P03/S1
P02/S0
PO()JINTI INTO/PIO
IJL-....,..---'
L(')
H(')
Program Memory
Stack Polnto, (7)
1024 X 8-BIt ROM (.;07501)
P40·P43
Instruction
Decoder
Data Memory
98 x 4.illt RAM (p!'07501)
P50·P53
P60·P63
System
Clock
Generator
CLI
Standby
Control
CL2
RESET
Voo
VSS
VLCOI'
VLC02'
VLC03
3-36
So-S23
COMO·COM3
PIO/INTO
DC Characteristics
",PD7501
T. = - 10·C to + 70·C, VDD = 2.7Vto 5.5V
....
&.Imlt.
P.r.meter
..In
I,mllol
Input VOIlogo High
Input Voltage Low
Input Leakage Current High
1)p
0.7VOD
VIH!
Output Vottage High
Alllniliuts Other thin eL1' X1
VIH2
VOD-0.5
VDO
VIHOR
0.9VDO DR
V°DoR+ 0 . 2
VILI
0
V
CL1,X1
RESET I DatIl Retention Mode
03VOD
Allinputa Other than Cl1. X1
V
0.5
VILa
CL1' XI
All Inpula Other than Cl1' X1
ILIHI
,.A
10
ILlH2
Input Leakage Current Low
T."'_......
Unit
VDO
ILiLl
-3
ILI~2
-10
All Inputa Other thlln Cl1. X1
,.A
VOD - 1.0
VOH
VDD = 5V ± 10'lll,IOH = -1.0 mA
V
VDD - 0.5
VOL
VDD = Z.7V 10 5.6V, IOH = -100,.A
Output Leakage Current High
ILOH
Output Le.kage Current Low
ILO L
VDO • 5V ± 10'111, IOL = 1.8 mA
V
0.5
-3
VI = OV
CL1,X1
0.4
Output Yoltage Low
VI = VOO
el1' X1
VOO. 2.7V to S.SV. IOL • 400 jAA
,.A
Vo
,.A
VO. OV
c
YOO
VDD = 5V ± 10'M1
COMO to COM3' 2.7V" VLCD" VOD
RCOM
kg
Output Impedance
ZO
RS
Supply Voltaga
So 10 SZ3' 2.7V" VLCD" VOO
ZO
1001
300
90
150
400
100Z
IODOR
0.5
10
0.4
10
VOD = 2.7V 10 5.5
VDO
Normal Operation
ZO
Supply Current
= 2.7V to S.SY
Dati Retention Mode
V
Z.O
VOO OR
VDD
VOO = 5V ± 10'111
VOO
Stop Mode, XI • OV
.A
= 5V :t
10%
VDO = 3V ± 10'111
=
BY :t 10%
VOD ;;: 3V :t 10%
Data Ret.ntlan Mode
V0DoR = Z.OV
AC Characteristics
T.
= -10·Cto +70·C, VDD =2.7Vto 5.5V
.,......0.
P.r.....t.r
ICC
Sytttem Clock Oscillation Frequency
&.Imlt_
210
R=IZkIl±Z'III
CL1,CL2 C=33pF±5%
Voo • 5V
t
80
100
130
RIC Clock R
=-
VOO .. 3V
± 10%
zoo
300
10
System Clock AI.. and Fall Tim••
teR,ICF
System Clock Pulse Width
ICH,ICL
'XX
180
10
135
O.Z
1.5
50
3.5
50
26
3Z
0
Counter Clock Oscillation Frequency
IXR,IXF
Counter Clock Pulee Width
tXH'txL
KHz
160 kQ
13.
Q.Z
C=33pF±S'III
.-
.
Voo
CL1. Extemal Clock
KHz
..
3.5
.1
7.0
8.7
X1. Extemal Pul.. Input
..
1.1
3.3
IKH,IKL
3.0
Q.5
fit
SI Hold Time attar SCRt
ISIK
300
IKSI
450
SO Oelay Time after iCK~
IKSO
INTO Pul .. Width
IIOH,IIOL
10
2/,+
10
SI Setup Time to
X1. Extemal Pulse Input
INTI Pu", Wldlh
111H,111L
IRSH,IRSL
RESET Setup Time
ISRS
RESET Hold Time
IHRS
f i l s an Input
§CR' 18 an Input
JeT{ Is an output
ns
ns
850
1200
RESET Pulse Width
n.
...
..
no
no
3-37
&'
2.7V to 5.5V
Voo
=-
SV :I: 1'*
VOO
:I
2.7V to 5.5V
VOD = 5V ± 10'111
VOO
= 2.7V to 5.5V
X1' External Pulse Input
SCi( II an output
14.0
1ei(PulooWldlh
= 2.7V to 5.SV
CL1' External Clock
4.0
IKCY
Voo
10%
VOO = 5V ± 10'111
.s
1.5
lreK Cycle Time
± 2%
50
300
'X
Counter Clock Rile and Fan Times
T_t Conditions
Unit
200
60
IC
....
"In
lZ0
VOO = 5V ± 10'M1
VOO = 2.7V 10 •. 6V
VOO = 5V ± 10%
VOO
= 2.7V to 5.5V
Voo
=
5V
t
10%
VOO = Z.7V 10 5.5V
Voo
:=
5V
t
10%
VOO = Z.7V 10 5.5V
Voo
:::I
5V :t 10%
VOO • 2.7v to 5.5V
VOO = 5V ± 10%
VOO
= 2.7V to 5.5V
J.tPD7501
Capacitance
T.
= 25°C, VDD
= OV
&./mit.
P .....eter
Input Capacitance
O~put
Capacitance
Input/Output Cap.cHance
SYMbol
Typ
Min
Max
15
15
15
C,
Co
CI/O
Unit
pF
pF
pF
=
f
1 MHz
Unmeasured pins
returned to VSS
Timing Waveforms
Clocks
' 'il
ll1C
CL' __________
'CL
"'r'CH
.~~
l11C
'XL
x1--------------------
Serlallnterface
'XRFIXH
:\
-- V,H
-- VIL
~
-- V,H
--V,L
'KCY
J~'KH~
'KL
"\
_VIH
--VIL
t--'SIK- j--'KSI-- V,H
Valid
Input Data
SI
--VIL
SO-----------------------------=='---------------V-.,-id-O-U-'p-u-'-o-m-.------------~Xc---------------i--'KSO
--X
---
~
U>
,,/ R = 160kQ
0-
/
20
C
33pF
1c
®)
Supply Voltage (Note
U>
V
/
V
L
I
XI
I
X2
fD~Rl
r
Xtal
r
20
c1
10
Cl
C2
Xtel
[J
C2
R1 = 330kQ
L
't-[
Supply Voltage VOO (V)
II
= 20pF
= 30pF
= 32.768KHz
Supply Vonag. VOO (V)
Supply Current
vs
Supply Current
vs
System Clock Oscillation Frequency
System Clock Oscillation Frequency
(Note (j))
(Note (j))
Voo = 5.0V
250
250
I cr;:r~1
Voo
c
I
= 39pF
c
1c
= 27pF
200
= 3.0V
f}
~
•
a·
·
150
u
0-
100
U>
~~------4------4------~-----4-l
50~-+------+------r-----f------~
100
C
50
= 100 pF
C
= 56pF
V 39pF
C
l/:::~~~iF
./
1-;:::::::
100
200
300
Oscillation Frequency
400
500
100
f+ (KHz)
200
300
400
Oscillation Frequency', (KHz)
Not••:
Z>Q. Q.zz
NC
P03/X,
8-11
47~50
P60~P63
4·blt input/latched tristate output Port 6 (active
high). Individual lines can be configured either
as Inputs or as outputs under control of the Port
6 mode select register.
12,13
3,5
CL1, Cl2
System clock Input (active high). Connect l20kQ
resistor across Cl1 and CL2' Alternatively, an
external clock source may be connected to Cll.
whereas Cl2 Is 'eft open.
7, 33
NC
NC
P2O'PSTB
P40
P21'PTOUT
P2 2
P53
14
P23
NC
P52
NC
15
P60
NC
P61
P51
P62
P50
P63
NC
NC
NC
NC
P0o/INTO
P13
Function
Symbol
1,25·27 24, 29, 30, 34
16·19
9-11,16
20·23
• 16-18,21
24,3
23,41
28
31
1,2,4,6
12-15, 19. 20,
25·28,32,
35, 37-40, 46,
Voo
Power supply positive. Apply single voltage
ranging from 2.7V to 5.5V for proper operation.
RESET
RESET Input (active high). RIC circuit or pulse
initializes JAPD7507 or ~P07508 after power·up.
P10·P13
4·blt Inp~t/tri.tate output Port 1 (active high).
Data output to Port 1 Is strobed In synchronlza·
tlon with a P201PSTB pulse.
4·blt Input/latched tristate output Port 5 (active
high). Can also perform a·blt parallel 110 In conjunction with Port 4.
2·bit Input Port 0 (active high). Line PDO is
always shared with external Interrupt INTO
(active high). Line P03 Is always shared with
crystal clock/external event Input Xl (active
high).
VSS
NC
Ground.
No connection.
Rev/2~__~5~1,~5=2_______________________________________
3-47
II
IAPD7506
Block Dla,ran,
P20-P23
P20IPSfi.
P211PTOUT
L(4)
H(4)
Program Memory
Stack POinter (6)
1024 x 8-aH AOM ' ....D7608}
P40-P43
Instruction
Decoder
Data Memory
84 x 4-BH RAM ' ....D7508}
PSO-P53
P6o-P63'
System
Clock
Generator
Standby
Control
RESET
t
VDD
t
Vss
Absolute Maximum Ratln,.·
OperatIng TempBrature
Storage Temperatura
Po_r Supply Voltap, VDD
All Input and Output Voltagea
Output-Currant (Total, All Output pons)
Capacitance
T. = .·C, VDD = ,OV
-10·Cto +70·C
-65·Cto +150·C
-O.3Vto +7.0V
-O.3VtoVDD +O.3V
IOH = -20mA
IOL = 32mA
·Comment: Stress above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute max·
imum rating conditions for extended periods may affect
device reliability.
Par.....~
Sym....
-
""'/to
Two
...
f
15
Input CopK......
CI
Output~"""
Co
15
Input/Output
CopK......
CUO
15
-T_
Unit
pF
= 1MHz.
Unmauured pin.
returned to
3-48
"
Vss '
/JPD7506
DC Characteristics
T.
= -10'C to + 70'C, VDD =2.7V to S.SV
Umltl
P.r....".,
VIH
Input Voltage High
Input Voltage Low
Typ
IIIIn
a""bol
VOO
Input Leakage Cur,ent High
VIH2
VOO-D.S
VDD
0.9 VDD DA
VDD DA +0.2
VIL
0
Dutput VoHogo High
el1' Xl
RESET. oata Retention Mode
All Inputl Other thin ell' Xl
V
0.5
CL I , XI
All Inputa Other than
ILiH
_A
10
ILiL
-3
ILlL2
-10'
All Inputs Other than ell' X 1
_A
Output Leakage Current High
ILOH
VOO
ILO L
VDD DA
-3
2.0
IDDI
600
100
300
Vo = VOD
.A
Vo = OV
:I
-10D,.tA
IOl = 1.8mA
= 400",A
Data Retention Mod.
VDD = 5V ± 10%,
Normal Operation
10
IO~
5.5Y, IOH
10~.
VOO = 2.7V 10 5.5V, IOl
.A
V
200
= 2.7Vto
VOO = 5V ±
V
0.5
Supply Voltage
VI = OV
VDD = 5V ± 10%,IOH. -1.OmA
V
VDD - 0.5
Output Leakege Current Low
VI = VOD
CLI' XI
0.4
VOL
el1• Xl
CLI' XI
VDD - 1.0
VOH
Output Voltage Low
Supply Current
V
0.3 VDD
ILlH2
Input Leakage Current Low
All Inputa Other than ell. Xl
VIHDA
VIL2
Test Condltlona
Unit
III••
0.7 VOD
Stop Mode, Xl
.A
0.3
Voo = 3V ± 10%
VDD = 5V ± 10%
= OV
VOD = 3V ± 10%
Data A••entlon Mode
0.3
YODOR
=
D
2.0V
AC Characteristics
T.
= -10'Cto +70'C,VDD =2.7VtoS.SV
LImit.
P.ramet.,
Symbol
Icc
System Clock Oscillation Frequency
IIIIn
III••
120
200
260
60
100
130
180
60
10
Ie
Syetem Clock RI.. and Fall Times
'cA,tcF
System Clock Pulse Width
tcH,lCL
I.x
200
10
1.5
50
3.5
50
32
IXA,tXF
COunter Clock PulM Width
tXH,tXL
Port I Output Sotup TIme to PSTBt
50
300
I.
Counter Clock RI.. and Fall Times
CLI , CL2
A = 160 kQ ± 2%
kHz
CL1. External Clock
135
0.2
""
""
ISTP
PSTB Pul.. Width
tSWL
ns
350
500
1500
300
ns
IIOH' IIOL
10
RESET PuIM Width
'RSH,tASL
10
=
5V ± 10%
Voo "" 2.7V to 5.SV
XI, X2 Crystal Oscillator
X1' External Pulse Input
VDO = 5V ± 10%
VDO = 2.7V to 5.5V
X1' External Pulse Input
X1, External Pulse Input
VDO = 5V ± 10%
VOD = 2.7V 10 5.5V
VOD = 5V ± 10%
VOO = 2.7V 10 5.5V
VOD
ns
INTO PulM Width
VOD = 2.7V 10 5.5V
VOO = 5V ± 10%
""
IpST
Port 1 Output Hold Time after PSTBt
= 2.1V to 5.SY
VDD = 5V ± 10%
YOO
CL1. External Clock
1.5
3.5
300
VDD = 3V ± 10%
CL1. External Clock
kHz
,..
VDD = 5V ± 10%
YOO
300
0.2
25
A = 82 kll ± 2%
135
Counter Clock Oscillation Frequency
Teet Condnlon8
Unit
""
""
3-49
III
5V ± 10%
VDO = 2.7V 10 5.5V
VDD = 2.7V to 5.5V
",PD7506
nmlng Waveforms
Clocks
~i
1lfc
lCL
CL1 _ _ _ _ _ _ __
~~
_V'H
".I~FIXH ~
IXL
xl _ _ _ _ _ _ _ __
\
ICRFICH
-
VIL
-
V'H
-V'L
Output Strobe
y.
IpST
PSTB
j--ISTPVIH
\
-VIL
ISTL
Extern~~::,_te_r_ru_p_t
_______
~~
ResetRESET _ _ _ _ _ _ _ _ _
Data Retention Mode
-v== ==t'-__________=: :
_ _ _ _II_OL__
-_
-_
-_
-_
-_-_
-_
IIOH
~:~~~~~~~~-I-R-SL--_-_-_-_-_-~y----
IRSH
---\1;.__________=~::
r---Oala Relenl,on Mode---!J-_ _ _ _ _ __
~-IS-R-SI
fL-
VOO------,'
if
RESET------'
~.
~
3-50
________________
= ~~OOR
= ~:rOR
I-lPD7506
Operating Characteristics
= 25°C
Typical, Ta
Supply Current
v.
Supply Voltage (Note
Supply Current
v.
CD)
®)
Supply Voltage (Note
,------------ --
~
200
1c
R
/
100
9
I
50
;-
l?: /
V
V
1c
~
0.
g.
R
1/
10
g
C
~
V
/'
0
/
20
.
'"
0
i
= 240kQ
'"
/
V
/
/
V
Xl X2 I
I
JD~Rl
ClIO t2
Xtal
20
R1
= 330kQ
C2 ==
C1
10
~
1.
Xtal
20pF
30pF
= 32.768KHz
Supply Voltage VOO (V)
Supply Voltage VOO (V)
11
System Clock Oscillation Frequency
v.
v.
System Clock Oscillation Frequency
Supply Voltage
Resistance
IC[{t l
500
.f
J:
""'-
0-
c
100
-
1< 200
~
~
.J:g
\~O=5V
~
0-
~
R
= 82kQ
A
= 160kQ
150
c
2
:;;
;
~
'CL~J'
::I:
VOO=3V
0
250
~
50
100
-
50
t...
50
100
200
500
Supply Voltage VOO (V)
Resistance R (K ohms)
Notes:
(1). Only RIC system clock is operating and consuming power. All other internal logic blocks are not active.
@ Only crystal oscillator clock is operating and consuming power. All other internal logic blocks are not active.
Package Outlines
For information, see Package Outline Section 7.
Plastic, ,...PD7506C
Plastic Miniflat, ,...PD7506G
Plastic Shrlnkdip, ,...PD7506CT
3-51
7506DS·REV2·7·83-TRIUM·CAT
Notes
3-52
NEe
",PD7507
",PD750a
CMOS 4·BIT SINGLE CHIP
MICROCOMPUTERS
Description
The j.lPD7507 and the j.lPD7508 are pin-compatible
CMOS 4-bit single chip microcomputers which have the
same j.lPD750x architecture.
The j.lPD7507 contains a 2048 x 8-bit ROM, and a 128 x
4-bit RAM. The j.lPD7508 contains a 4096 x 8-bit ROM,
and a 224 x 4-bit RAM.
Both the j.lPD7507 and the j.lPD7508 contain four 4-bit
general purpose registers located outside RAM. The subroutine stack is implemented in RAM for greater nesting
depth and flexibility, providing such operations as the
pushing and popping of register values. The j.lPD7507
and the j.lPD5708 typically execute 92 instructions of the
j.lPD7500 series "A" instruction set with a 10j.ls instruction cycle time.
The j.lPD7507 and the j.lPD7508 have two external and
two internal edge-triggered hardware vectored interrupts.
They also contain an 8-bit timer/event counter and an
8-bit serial interface to help reduce software requirements.
Both the j.lPD7507 and the j.lPD7508 provide 32 I/O lines
organized into the 4-bit input/serial interface Port 0, the
4-bit input Port 2, the 4-bit output Port 3, and the 4-bit I/O
Ports 1, 4, 5, 6, and 7. They are manufactured with a low
power consumption CMOS process, allowing the use of a
single power supply between 2.7V and 5.5V. Current consumption is less than 900j.tA maximum, and can be
lowered much further in the HALT and STOP power-down
modes. The j.lPD7507 and the j.lPD7508 are available in
either a 4O-pin dual-in-line plastic package or in a spacesaving 52-pin flat plastic package.
The j.lPD7507 is downward compatible with the j.lPD7506
and the j.lPD7507S.
Pin Configuration
NC
P4,
P'O
P40
P"
P53
P'2
P'3
NC
P3Q
P52
P5,
,..PD7507G
,..PD7508G
P50
PS3
P3,
P62
P32
P6,
P33
P60
P70
P7,
P03/S'
P02/S0
P72
NC
Pin Identification
. .PIn
DIP
sa·Pln
FI8t
!lon.....
'unctlon
'.40
32,34
X2,X'
2-5
38-39
4-blt _hod tri...... output Port 2 (activo high).
P2g-P23
Uno P2g 10 .... sh.r.d with PSTB. tho Port,
P2g1PSTB
output otrobe pul.. (activo Iow}. lin. P2, 10 aIoo
P2,/PrOUT
~:~)~OUT' the tlm.....ut FIF signal
6·9
4144
P'g-P'3
4-blt Inputltrf._. output Port, (active high).
Data output to Port 1 18 strobed In synchronization with a P20fPSTB pul...
Cryatal cl.ck/....mal .vant Input Port X (.ctlvo
high). A crystal oacillator circuit .s connected to
Input X, and output X2 for crystal clock operatton. Alternatively. external event pulses are connected to Input X, while output X2 Is '-ft open
for
external event counting.
=.,":
x,
'11-13
46-49
P3g-Pla
4-bH latChed tr._. output POrt 3 (activo hllh):
P20IPSTB
Vss
'4-'7
511-52,2
P7g-P73
4--btt input/latched trl·stat, output Port 7 (active
P2,/PTOUT
P22
P43
X2
P42
P4,
P23
P32
P33
P53
P52
P5,
,..pD7507C
"PD7508C
'9,2'
5,9
a."CLz
Sy8IOm clock Input (activo high). ConMd 82k!2
_ r acrooe Cl, and CLz, .nd connoct 33pF
capacitor trom Cl, to Yss. Alternatively, on
external clock aource may be connected to CLt.
who.... CLz Is loll opon.
20
7,33
YDD
Power supply posltlv•. Apply slnglo voH_
ranging trom 2.7V to 5.5V lor proper operation.
PS3
22
'0
INT,
PS2
ps,
Extomallnt.rrupt INT, (active high). This 10 •
~alng .dg......ggered Int.rrupt.
23-28
II, '2
'5,'8
PDglINTO
PO,/SCI<
POzISO
PD:IJSI
4-b~ Input Port o/S.rlal WO Interlac. (actlv. high).
Thle port can be configured elthar as • 4-blt
parallel Input port, or as tho 8-blt ..~all/O Int...
face, under control of the ....... mode select
reginr. Tho _Input 51 (actiVO high), So!!!!....
Output SO (activo low), and tho So~al Clock SCK
(activo low) uoed lor synchronizing data transtor
comprise tho 8-blt aeriol WO Int_. Un. POg
P50
pSo
P70
P7,
P03fSI
P72
P02/S0
P73
RESET
RESET Input (actIv. high). RIC circuit or pul..
InHlall... ,...07507 or ,...07508 alter power-up.
P4g
P'o
P',
P'2
P'3
P30
P3,
high).
RESET
'8
po,lIl:R"
::C=:t::h~~ :::I=~I::.!8
POQ/INTO
Cl,
INT,
VDD
Cl2
Intorrupt.
Rev/1
3-53
II
",PD75071750a
Absolute Maximum Ratings *
Pin Identification (Cont.),
40-.....
DIP
-
T.
H-Pln
'.ctlon
. .mba!
27-30
.7·20
P60-P83
4-bit Input/la1chod tri·118t. output Pori 6 (active
high). Individual lin.. can be contlgured .Ithor
.. Inputs or sa outputs under control of the Port
6 mod. aaloct raglsta,.
3.-34
2.·24
P5o-P53
4-blt Inputlll1c:hod t , _ output Port 5 ( _
high). Can 0180 portorm B-bM porallel VO In oonJunction wlth Port 4.
3~
25.26.
28.30
P40·P43
4-bM Input/lotchad _ . output Pori 4 (active
high). Can oleo portorm B-bM poraIlel VO In c0njunction wMh Pori 5.
39
V!!l!
3'
NC
•• 4.8.8.
13,14,27,29,
35.40.45
= 2S·C
-10·Cto +1O·C
-65·Cto + 1SO·C
-O.3Vto +7.0V
-O.3VtoVoO +O.3V
Operating Temperature
Storage Temperature
Power Supply Vohage. VOb
All Input and Output Voltages
Output-Current (Total, All Output Ports)
=
=
IOH
-20mA
IOL 30mA
·Comment: Stress above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Ground.
No connection .
DC Characteristics
T.
=
P_-
-10·C to + 70·C, VDD
Input Voltage High
Input VoMaga Low
Input Laabga Curtanl High
= 2.7V to S.SV
..In
TrP
VIH
0.7VDD
VDD
VIH2
VDD-0.5
VDD
T _ _•
Unit
Allinpula Othe' than Cl •• X.
V
0.3 VDD
o
ILiL
Ill~
-.0
,.A
VOL
Output Leakag. Current High
ILOH
All Inputs Other than CL•• X.
VDD • 5V ± '0'"'. 'oH • - •• 0 mA
V
0.4
VDD. 2.7Vto6.5Y,IOH. -1001lA
VDD = 5V 10 'O%.IOL = '.8 mA
V
0.5
VDD- 2.7VIOS.5V,IOL
,.A
Output L08Icog. Current Low
ILO L
VDDoR
-3
VOUT = OV
V
300
900
.50
400
SUpply Current
0I1a Retention Mod.
'0
0.4
'0
VDD = 5V 10 '0'"'
Normal Operation
20
0.5
= 400,..
VOUT = VDD
,.A
2.0
IDO.
VI == oV
CL"X,
VDO - 0.5
Supply VoMaga
VI = VDO
CL•• X.
,.A
VDO - ••0
Output Voltage Low
Cl •• X.
All Input. Other than Ct.1' X1
'0
-3
VOH
_Ion _
All Inputs biher thin CL1. X1
V
0.5
IllH
Output VoIt_ High
CL•• X.
RESET. 0I1a
VDO DR +0.2
VIHDR
Vil
Vll 2
IUH2
Input Lukllge Cwrent Low
....
~.
.........1
Stop
M_.
VDD = 3V 10 '0%'
Vpp. SV t 10_
X• • OV
VDD
0I1a RI1anlion _
= 3V
10 .0,",
VDDDR = 2.0V
AC Characteristics
T.
=
-10·Cto +70·C,VDD
P_-
Syotom Clock Oocllll1lon Frequency
= 2.7VtoS.SV
........'
'cc
....
120
80
'C
tcA.tCF
System Clock Pul.. Width
'<:H·teL
Count.r Clock OScIIllII:lon Frequency
'xx
'30
180
200
300
'35
'0
0.2
'.5
50
3.5
50
25
32
Count., Clock RIeo and Foil TImoo
txR,tXF
Count.r Clock PuI.. Width
txH.tXL
'35
0.2
'.5
3.5
3-54
CL•• Cl2
KHz
.
..
R= '80k2102,",
C .. 33 pF t -5'"'
CL1' Extamal Clock
VDO
= IV
t'O%
VOD = 3V 10 10%
VDD • 2.7V 10 5.IV
VDD. IV 10 '0%
VDD • 2.7V to S.5V
CL•• Extomol Clock
VDD = IV t '0,",
CL1' Extern. Clock
VDD • 2.7V 10 5.BV
X•• X2 CryI10I OocUII1Or
50
300
'.
R= 82(kQ ± 2%
C_33pF 10 5,",
280
'00
80
.0
8yI1om CIoclc RI.. and Fall Tim..
200
T_ _ _
Unit
KHz
.
,..
XI. Extarnol Pul. . Input
VDD = 5V t .0,",
VDO = 2.7V to I.IV
X•• External Pulao Input
X•• Extern", Pul.. Input
YDD. BY :t 10%
VDD a 2.7V to 5.5V
j.LPD750717508
AC Characteristics (Cont.)
P ..........
.,'"
• ,mltol
LlmH.
Typ
..
.,
T ••• CondItIon •
UnH
4.0
.0
7.0
SCK Cycl. Tim.
IKCY
6.7
SCK I. an output
14.0
I.B
..
3.3
SCK Pul.. Width
tKH,tKL
3.0
6.5
51 Setup Time to
!1m"t
ISIK
300
450
51 Hold Time after ~t
IKSI
SO Delay Time aftar SC'K,
IKSO
Port 1 Output Setup Time to PSTBt
IpST
Port 1 Output Hold Time att.r Pfij't
ISTP
B50
1/(2IfBOO)
n.
1/(211"2000)
350
300
ISWL
tNT0 Put.. Width
IIOH'IIOL
10
INT 1 Pulse Width
II,WH,II, WL
RESET Pul.. Width
IRSH'IRSL
2/1\
10
RESET Setup Time
'SRS
RESET Hold Time
IHRS
= 25·C, VDD = OV
Umlta
Parameter
.ymbol
Input Capacitance
C,
Output Capacitance
Input/Output Capacitance
"'n
Typ
n.
ns
11(21.-2000)
.0
....
no
Capacitance
T.
500
1500
1I(2It-BOO)
PSTB Pul. . Width
n.
..
.,
T••t
Condition.
Unit
SCi( 'S an Input
SCK. Is an output
= 1 MHz
15
pF
f
Co
15
pF
CI/O
15
Unmeasured pins
returned to VSS
3-55
VOO
= 5V ± 10%
= 2.7V to 5.5V
= 5V ± 10%
VOO
= 2.7V to 5.SV
VOO
YOO
VOO = SV ± 10%
YOO
= 2.7V to 5.5V
VOO= SV ± 10%
VOO
= 2.7V to
VOO
= 5V ± 10%
VOO
=
VOO
= 5V ± 10%
2.7V
YOO = 2.7V
to
to
S.5V
S.5V
VOO = 5V ± 10%
n.
n.
1200
300
ScKla an Input
5.5V
VOO
= 2.7v to 5.5V
VOO
= 5V ± 10%
VOO
= 2.7V to S.SV
,.,PD7$0717508
Block Diagram
X2
INTI
P10-P13
P2Q-P23
D(4)
E(4)
L(4)
H(4)
Program Memory
Stack Pomter
1....
2048 • II-BIt ROM
D7507)
_
• 8-BIt ROM ....D7&08)
P40-P43
Instruction
Decoder
Data Memory
128 • 4-BIt RAM (,.pD7507)
224 • 4-8/1 RAM (,.pD7508)
P5o-P53
CL
System
Standby
Clock
Control
Generator
P7o-P73
CLI
CL2
RESET
VDD
Vss
3-56
( P2otPSTII.)
P2111'TOUT
",PD7507/7508
Timing W.veforms
Clocks
eLI
xI
1cL-ry--'".4
~1I
Ille
~~
-V!H
________ VIL
~
lIIe
"v="q
'xL
-V+H
~
Serial Interlace
_______________
-V~
IKH
IKL
IeR
~
_VIH
_ _ _ _ _ _ _ _....:- VIL
talK
Valid
81
Input Data
r------------------------~VIH
-VIL
IKSOj
80
Output Strobe
External Interrupts
INTO
INTI
~
~
Plo-"I3
PSTB
X
Valid Output Data
i
r--4
IpsT
ISTL
~
qOL
~
qlL
F-QoH==t
F"IH==\
-VIH
VIL
VIH
-
VIL
-VIH
-VIL
-VIH
VIL
-VIH
VIL
RESET-~i---i<______·I~------:J/~-'IIStI-\
Reset
-VIH
........._ _ _ _ _ _ _ _...:
VIL
Data Retention
Mode
VDD _ _
_ _ _ _ _ _J!----Data Retent,on MOda----l
RESET_----:lM
~r--itt!lS---
~
3-57
-
VIH
-vlIDoR
~------------------------- :~
II
~PD7507/7508
Operating Characteristics
(Typical, Ta
25°C)
=
Supply CUrrent
v.
Supply Current
v.
Supply Voltage (Note
,------
200
~I=
R
E
50
/
.
0.
/'
0-
/
/
/
/
~V
0
S?
u
®)
20
100
..~
CD)
C
33pF
1
Supply Voltage (Note
1
10
0
S?
E
~
..
V
V
/
U
~
U>
R = 180kQ
/
V
/
V
I
I
}4Rl
X,
X2
Xlal
U>
C11 (]
20
R1
C1
t2
= 330kQ
= 20pF
C2 = 30pF
10
Y
3
l.
4
Xtal
Supply Voltage VDD (V)
= 32.768KHz
Supply Voltage VOO (V)
Supply Current
Supply CUrrent
vs
vs
System Clock Oscillation Frequency
System Clock Oscillation Frequency
(Not.
Not. G))
G))
Voo = 5.0V
250
250
c
Icr;r~1
c
1
= 27pF
VOO = 3.0V
r
= 39pF
200
0
S?
E
~
150
u
.
-a
0-
100
U>
I--"-Ic----j----+----+----+-I
100
C = 100 pF
~
__
50
1---"11-----"1----+----+----+-1
50
C = 39 F
~~
C=56pF
~_
C=2r
/
!~
100
200
300
400
100
500
Oscillation Frequency f~ (KHz)
200
300
Oscillation Frequency
400
f+ (KHz)
Not. .:
(j) Only RIC system clock is operating and consuming power. All other internal logic blocks are not active.
<2l
Only crystal oscillator clock is operating and consuming power. All other internal logic blocks are not active.
3-58
500
fJPD750717508
Operating Characteristics (Cont.)
(Typical, Ta
25°C)
=
..
System Clock Oscillation Frequency
v.
System Clock Oscillation Frequency
Supply Voltage
Resistance
250
500
ICgJ'1
I~
N'
x
~
02 200
i
'" Voo = 5V
~
~
"- 'DO
,
1= 33pF
r
¥~
0
~
SO
200
~
r
~
-
SO
100
200
= 82kQ
'SO
:
0
~
A = 160kQ
'DO
SO
4
R
"c
Voo =~
3V
c
!
C=33PF
'CL1'c '
500
Supply Voltage VOO (V)
ReSistance R (K ohms)
II
Package Outlines
For information, see Package Outline Section 7.
Plastic, fLPD7507C/OBC
Plastic Miniflat, fLPD7507G/OBG
Plastic Shrinkdip, fLPD7507CU fLPD750BCU
7507/750BDS-REV1-7-B3-TRIUM-CA T
3-59
NOTES
3-60
NEe
~PD7507S
CMOS 4·BIT SINGLE CHIP
MICROCOMPUTER
Pin Identification
Description
The ",PD7507S is a CMOS 4-bit single chip microcomputer which has the same ",PD750x architecture.
Pin
The ",PD7507S contains a 2048 x 8-bit ROM, and a 128
x 4-bit RAM.
The ",PD7507S contains two 4-bit general purpose
registers located outside RAM. The subroutine stack is
implemented in RAM for greater nesting depth and flexibility, providing such operations as the pushing and
popping of register values. The ",PD7507S typically executes 91 instructions of the ",PD7500 series" A" instruction set with a 10",s instruction cycle time.
The ",PD7507S has two external and two internal edgetriggered hardware vectored interrupts. It also contains
an 8-bit timer/event counter and an 8-bit serial interface
to help reduce software requirements.
The ",PD7507S provides 20 I/O lines organized into the
4-bit input/serial interface Port 0, the 4-bit output Port 2,
the 4-bit output Port 3, and the 4-bit I/O Ports 4 and 5.
It is manufactured with a low power consumption
CMOS process, allowing the use of a single power supply between 2.7V and 5.5V. Current consumption is
less than 900",A maximum, and can be lowered much
further in the HALT and STOP power-down modes. The
",PD7507S is available in a 28-pin dual-in-line plastic
package.
The ",PD7507S is upward compatible with the ",PD7507,
and downward compatible with the ",PD7506.
No.
Function
Symbol
1.25-27
P40·P43
4--blt Input/latched trl·state output Port 4 (active high). Can also
perform a..bit parallel I/O In conjunction with Port 5.
U
X2' Xl
Crystal clock/external event Input Port X (active high). A
crystal oscillator circuit Is connected to input X1 and output X2
tor crystal clock operation. Alternatively, external event pulses
are connected to Input X1 while output X2 Is left open for
external event counting.
4·7
4--bit latched tri-state output Port 2 (active high). Line P21 is
shared with PTOUT' the tlmer~ut F/F signal (active high).
8-11
12
P20·P23
P21/PTOUT
P30·P33
RESET
13.15
CL1. CL2
14
VOO
16
INT,
External Interrupt tNT 1 (active high). This Is a rising edgetriggered interrupt.
17-20
POOIINTO
4-bit input Port Olserlal 1/0 interface (active high). This port
can be configured either as a 4·bit parallel Input port, or as the
B-blt serial I/O Interface, under control of the serial mode
select register. The Serial Input SI (active high), Serial Output
SO (active low), and the Serial Clock sa< (active low) used for
synchronizing data transfer comprise the B-bit serial 110 Interface. Line POD is always shared with external interrupt INTO
(active high) which Is a rising edge·triggered Interrupt.
P01/SCK
P02/S0
P03/S1
4-blt latched trl-state output Port 3 (active high).
RESET Input (active high). RIC circuit or pulse Initializes
",PD1501 or ",PD150B after power-up.
System clock Input (active high). Connect 82kQ resistor
across Cl1 and Cl2. and connect 33pF capacitor from Cl1 to
VSS' Alternatively. an external clock source may be connected
to Cl whereas CL2 is left open.
"
Power supply positive. Apply Single voltage rangmg from 2.7V
to 5.5V for proper operation.
21·24
P50·P53
4-blt Inputltatched tri-state output Port 5 (active high). Can also
perform B-btt parallel 110 In conjunction with Port 4.
28
VSS
Ground.
Absolute Maximum Ratings·
Pin Configuration
Ta
P43
Vss
Xl
P42
X2
P41
P20
P40
P21fPTOUT
P53
P22
P52
P23
P51
P30
P31
P50
P03/S1
P32
P021S0
P33
RESET
-10·C to + 70·C
-65·Cto +150·C
-O.3Vto +7.0V
-O.3VtoVOO +O.3V
IOH = -17mA
IOL = -34mA
'Comment: Stress above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
P01/SCK
POOflNTO
CLl
INTI
Voo
CL2
= 25°C
Operating Temperature
Storage Temperature
Power Supply Voltage, vOO
All Input and Output Voltages
Output-Current (Total, All Output Ports)
Rev/1
3-61
II
",PD7507S
Block Diagram
P0 1'SS;K
P03/Sf
P02/S0
P201P23
(P21/PTOUT)
P30·P33
H(4)
Program Memory
2048
l(4)
Stack Pointer (8)
x 8-BfT ROM ("P07507S)
P40-P43
Instruction
Data Memory
Decoder
128 x 4-BfT ("P07507S)
P50·P53
System
Clock
Generator
Cll
Standby
Control
Cl2
RESET
VOO
Vss
3-62
IJPD7507S
DC Characteristics
T.
=
= 2.7V to S.SV
-10·C to + 70·C, VDD
LImit.
P.ramet.r
Input Voltage High
Input Voltage Low
Symbol
T¥p
Min
0.7 Voo
VOO
V'H2
VOO_0.5
VOO
V'HOR
0.9 VOO OR
VODOR
VIL
0
Input Le.kage Currant Low
Output Voltage Low
Output Leakage Current High
Output Leakage Current Low
Supply Voltage
RESET, Data Retention Mode
+ 0.2
All Inputs Other than CL1. X1
v
0.5
_,A,,"-:-'n,p..ut_S_Dt_hO_'_'h_"_n_C_l_l,_X--,l_ _ _ VI = VOO
'l'H
VUH 2
10
Cll' Xl
_ _A='_"_np~u_••_Dt_h_O'_'_h"_n_C_l--,l_,X_l~_ _
-3
'Lll
-10
Vl'l2
Output Voltage High
All Inputs Other than CL1. Xl
0.3 VOO
V'l2
Input Leakage Current High
Unit
Max
V'H
VOO - 1.0
VOH
0.4
V
0.5
VOO
= 5V ± 10%,IOH = -1.0 mA
= 2.7V.o 5.5V, 'O~'"'-:=:7-::-10:-0-,-,.A
_ _ _ _ _ __
YOO
= SV ± 10%. IOL ,. 1.8 mA
Voo
V
VOO - 0.5
VOL
VI=OV
Cll' Xl
Voo= 2.7Y to 5.5V, IOL ,. 400 ",A
'lOH
Vo = OV
-3
'lOl
v
2.0
VOO OR
'DOl
300
900
70
300
Supply Current
Data Retention Mode
VOO
20
0.3
10
0.4
10
Yoo = SV :t 10%
Normal Operation
Stop Mode, Xl
= 3V
± 10%
Yoo ,. 5V ± 10%
= OV
VOO
Data Retantlon Mode
= 3V
± 10%
YODOR = 2.0V
AC Characteristics
T.
=
-10·Cto +70·C,VDD
= 2.7VtoS.SV
Parameter
Symbol
Icc
Syatem Clock Oscillation Frequency
200
240
75
100
120
200
300
135
75
'e
System Clock Rlae and Fan Time.
'cR' 'CF
System Clock Pul.. Width
'CH,'Cl
Counter Clock Oecillation Frequency
Mu
Min
150
'x.
'x
Counter Clock At .. and Fall Time.
txR' txF
Counter Clock Pulse Width
txH,txL
10
10
135
0.2
1.1
50
3.5
50
20
32
KHz
300
135
0.'
1.5
CL1' External Clock
...
...
3.5
...
...
...
6.7
1.3
,..
2.2
51 Setup Time to SCKt
'S'K
300
'KS'
4SO
SO Oelay Time after
'NT0 Pu'" W'dth
SCK'
INT 1 Pul.e Width
"lH'llll
RESET Pu'u W'dth
IRSH,'RSl
RESET Setup Time
'SRS
RESET Hold Time
'HRS
1200
no
.'...
10
,..
10
no
ns
3-63
III
2.7V to 5.5V
VOO = 2.7V
'0 5.5V
VOO
= 5V ± 10%
VOO
ill
2. TV to 5.SV
Voo == 5V ± 10%
YOO
VOO
=
2.7V to 5.5V
ml••nlnput
Yoo = SV t 10%
Voo
=
2.7V to S.SV
=
=
Voo
=-
t
10%
2.7V to 5.5V
Veo = SV
VOO ==
± 10%
2.7V to 5.5V
Voo = 5V
VOO
no
8SO
"OH"'Ol
'SCi( ,. an Input
no
'KSO
VOO
VOO = 5V ± 10%
VOO :: SV
X1' External Pul.. Input
SCK I. an output
6.5
SI Hold Time after SCKt
± 10%
± 10%
X1' Externa' Pul.. Input
~I.anoutput
3.3
'KH"Kl
CL1' External Clock
X1' External Pulse Input
14.0
SCi< Pu'" Width
= 5V
VOO = 3V
VOO
CL1' External Clock
KHz
4.0
'KCY
R=82kQ±2%
Cll , C~ C = 33 pF ± 5%
RIC Clock R = 160 kQ ± 2%
C=33pF±5%
50
7.0
SCK Cycle Time
Te.t Condition_
Unit
t
10%
2.7V to 5.5V
SY
t 10%
VOO = 2.7V to 5.5V
VOO
VOO
= SY t 10%
= 2.7V to 5.SV
IJ
1lPD7507S
Capacitance
T.
= 2SoC. VDD = OV
p_amet.,
Input Cepachance
Output COpacltance
Input/Output Capacitance
.........
C!
Co
- ....
"'"
~.
ClIO
T_
ContIIuon.
15
pF
f=1MHz
15
pF
15
PF
Unmeasured pins
returned to Vss
Timing Waveforms
Clocks
CL--------1c-'~:~~~~=_tc_L___:_C_r=_1 '" 4'-________ =::
XI--------IX-,~----
tXL
:-'F ~ 4'--_________ =~::
---"'7t
tKCY
Serlallnte"ace
tKL
"\
lr-!KH~
_VIH
_VIL
I---tSIK_ r- tKSI -VIH
Valid
51
Input Data
,<
-VIL
50---------------~~------V-.I-ld-0-~-~-t-D-m-a-----~)(~--------__ ::
I--IKso
-F =t,,__________=::~
Extern~::,-terru--p-t;..s-..;...----~'______tlO_L_-_-_-_~~-_-_-.....
tlOH
INTI---------~~____t_II_L_-_-~_-~_-_-:yl-======--tl-IH_==\'-__________=: :
ResetREsET _ _ _ _ _....,.._ _
Data Retention Mode
---.~::~~~~-------"'-S-L----~---- tASH - - - \...__________=~::
L---
1-
VDD------~--:--tsAs--I
RESET------'jf--~
I
Oat. Retention Moda--t
Rl--tH-AS--"-~~~~~~~~~~~_-_-_-____________<= ~~DA
_
= ~:~DA
3-64
/JPD7507S
Operating Characteristics
25°C)
(Typical, Ta
=
Supply Current
vs
Supply Current
vs
Supply Voltage (Note
Supply Voltage (Note
CD)
®)
,--~~
~
200
R
~
,/
C
1= 33pF
100
Q
9
I
50
/'
<..>
~
a.
/
cil
/
20
/
~V
/'
~
10
B
c
~
/
i3
V
~
a.
R = 160kQ
/
cil
/
/
/
/
I
X,
X2
foqRl
20
C11 []
Rl ==
10
't.r
3
Supply Voltage VOO (V)
Supply CUrrent
vs
System Clock Oscillation Frequency
250
'T;J~'
Supply Current
vs
System Clock Oscillation Frequency
Q))
(Not.
Voo = 5.0V
250
C[;t1~1
I
C = 39pF
200 I-"'--'=---';~TM=--
~Q
B
J
J
I
Q))
Voo = 3.0V
1
~
II
=
Supply Voltage VOO (V)
(Nole
t2
330kQ
C,
20pF
C2
30pF
lito, ~ 32.788 KHz
L
4
I
150
/--i-:r---...",r-"""7'''''-7'l''''-----t-----t-l
100
/-..::;./----/------1~----t-----t-l
200
9
E
j
.
150
~
a.
II)
100
C=100pF
~
50
_~~
1--+-----1------+------1------+-1
100
200
300
Oscillation Frequency
400
C=39F
50
/.
I'~
~
200
300
Oscillation Frequency
f.
400
(KHz)
Not. .,
(J) Only RIC system clock is operating and consuming power. All other internal logic blocks are not active.
~ Only crystal oscillator Clock is operating and consuming power. All other internal logic blocks are not active.
3-65
r
C= 27
~
100
500
f+ (KHz)
C=56pF
500
J.lPD7507S
Operating Characteristics (Cont.)
(Typical, Ta = 25°C)
System Clock Oscillation Frequency
v.
v.
System Clock OSCillation Frequency
Supply Voltage
ResIstance
IC~'1
500
I~
~
'";.
200
fw
C=33PF
"'" ~5V
"- 100
c
2
~
Voo
~
0
50
,
250
."
r
1=
33pF
200
~
R
= 82kQ
R
= 160kQ
~
g
~ 150
0-
J:c
~
= 3V
IctJ~1
~
~
100
-
50
L,
50
100
200
500
Supply Voltage Voo (V)
Resistance R (K ohms)
Package Outlines
For information, see Package Outline Section 7.
Plastic, ",PD7507SC
Plastic Shrinkdip, ",PD7507SCT
3-66
7507DS-REV1-7-83-CAT
NEe
J.(PD7508A
CMOS 4·BIT SINGLE CHIP
MICROCOMPUTER WITH VACUUM
FLUORESCENT DISPLAY DRIVE
CAPABILITY
De.crlptlon
The j.lPD7508A is a CMOS 4-bit single chip microcomputer which has the j.lPD750x architecture. It is identical
to the j.lPD7508, except for a slightly smaller RAM, and
16 lines of vacuum fluorescent display drive capability.
The j.lPD7508A contains a 4096 x 8-bit ROM, and a 208
X 4-bit RAM.
The j.lPD7508A contains four 4-bit general purpose
registers located outside RAM. The subroutine st/lck is
implemented in RAM for greater nesting depth and flexibility, providing such operations as the pushing and
popping of register values. The j.lPD7508A typically executes 92 instructions of the j.lPD7500 series "A" instruction set with a 10j.ls instruction cycle time.
The j.lPD7508A has two external and two internal edgetriggered hardware vectored interrupts. It also contains
an 8-bit timer/event counter and an 8-bit serial interface
to help reduce software requirements.
The j.lPD7508A provides 32 I/O lines organized into the
4-bit input/serial interface Port 0, the 4-bit output Port 2,
the 4-bit output Port 3, and the 4-bit I/O Ports 1, 4, 5, 6,
and 7. Ports 3, 4,5, and 6 are capable of being pulled
to - 35V in order to drive vacuum fluorescent displays
directly. It is manufactured with a low power consumption CMOS process, allowing the use of a single power
supply between 2.7V and 5.5V. Current consumption is
less than 900joiA maximum, and can be lowered much
further in the HALT and STOP power-clown modes. The
j.lPD7508A is available in a 40-pin dual-in-line plastic
package.
Pin Name.
Pin Configuration
X2
X,
P20IPSTB
Vss
P2I/PTOUT
P22
P43
P23
P41
P42
PIO
P40
PII
P53
PI2
P52
PI3
P51
P30
PSO
P31
P53
P32
P52
P33
P51
P70
PSO
P71
P03/SI
P72
P02ISO
P73
POlliCK
POOIINTO
RESET
ClI
INTI
VDO
Cl2
400Pin
DIP
.,.......
....ctlon
Cryatal clock external event Input Port X (active high). A crystal
O8Clllltor circuit Is connected to Input Xi and output X2 tor
crystal clock operation, AltemaUvely. externalev.nt pulnl are
connected to Input X. while output X2 I. lett open lor external
1.40
X2. XI
2·5
P2g-P23
4-bIt latched trlatate output Port 2 (active high). Line P20 Is
P20PSTB
.teo shared with PSTa. the Port 1 output strobe pUlee (active
P21/PTOUT
.'gnal (aCllve high).
event counting.
6·9
PIg-PI 3
lOW). Line P21 Is also ahared with PTOUT' the tlmar out F/F
4-b1t Inputltrlltate output Port 1 (active h'slh). Data output to
Port 1 18 strobed In .ynchronlzatlon with. P2o'PSTi pul...
11).13
P30·P33
4·blllatched Irl..... OUlput POll 3lactlYl. high).
14-17
18
P7g-P73
RESET
RESET Input (active high). RIC circuit or pulse Initializes
19,21
ClI. Cl2
System clock Input (active high). Connect 82kO raalator across
CL1 and CL2. and connect 33 pF capacitor from CL1 to VSS'
Alternatively. an external clock source may be connected to
CL1. whe,..a CL2 Is left open.
:w
Voo
Power aupply positive. Apply lingle voltage ranging from 2.7V
to &.SV for proper operation.
22
INTI
4·blt Input/latched trlatate output Port 7 (active high).
",,07507 or ",,07508 "".r pcwer·up.
Externallntenupt INT 1 (active high). This Is a "alng edge-
Irlggered Interrupt.
23·28
POollNTO
POIISCK
P021SO
POWSI
4-blt Input Port O/88rlaII/O Interface (active high). This port can
be conllgured either al a 4-bIt parallel Input port. or a. the a-bit
..rial IJO Interface, under control 01 the serla' mode select
register. The Serl.llnput 81 (acttve high). S.rI.1 Output SO
(ICtive low). and the Serial Clock ICK (acttve Io~) ueed lor aynchronlzlng dill transfer comprl.. the 8-blt ..rial I/O Interface.
Line POo I. &twa,a shared with e.temllinterrupt INTO (active
high) which Is a rialng edg..trIggered Intoriupt.
27·30
P5g-P83
4-blt Inputllatched trls...e output Port 6 (active htgh). Individual
Ifn.. can be conflgured either •• Inpub or aa outputs under
control 01 the Port 8 mode select regl.,.,.
31-34
P5g-P53
4-blt Input/latched tristate output Port 5 (active high). Can al80
perform 8-blt par"" I/O conJunction wtth Port 4.
3&·38
P4g.p4a
4-blt lriputllatched trls...e output Port 4 (acttve high). Can alao
perform a-bit parallel 110 In conjunctkln with Port 5.
39
Vgs
Ground.
Absolute Maximum RatingsOperating Temperature
-10OCto +70OC
Storage Temperature
-&SoCto +150°C
Power Supply Voltage, VOD
-O.3Vto +7.0V
Input Voltages, Porta 4, 5, and 6
(VDD - 4O.0)V to (VDD + O.3)V
AlIOtherlnputPorts
-O.3VtoVDD +O.3V
Output Voltages, Porta 3, 4, 5, and 6 (VDD - 40.O)V to (VDD + O.3)V
A"OtherOutputPorts
-O.3VtoVDD +O.3V
Output-CUrrent (Total, A" Output Ports)
IOH = -150mA
IOL =50mA
·Comment: Stress above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated In the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
Rev/2 device reliability.
3-67
II
",PD7508A
BloCk Diagram
P011SCK
P031S1
P021SO
P10-P13
P20·P23
P20/PSTB.
P21/PTOUT
P30·P33
l(4)
H(4)
Stack Pomter
Program Memory
P40·P43
4086 x 8-Bit ROM (,.Po7508A)
Instruction
Decoder
Data Memory
208 x 4·811 RAM ,"PD7508A)
P50·P53
System
Clock
Generator
Standby
Control
t
RESET
t
VDD
t
VSS
3-68
JAPD7508A
DC Characteristics
Ta
= -10·C to
+ 70·C, VDD
2.7Vto 5.5V
LImits
Symbol
Parameter
Input Voltage High
Ma.
T.p
M'n
V.H
0.7 VOO
V.H2
VOO - 0.5
VOO
V1HOR
O. 9V ODOR
VODOR + 0.2
a. 3V OC
VOO - 35.0
VIL3
RESET, Data Retention Mode
AlllnputB Other than Cl,. X,. Ports 4, 5, and 6
V
0.5
V.L2
Input Leakage Current Low
All Inputs Other than CLIo X,. Ports 4, 5, and 6 VI
10
ILlH2
' LlH 3
60
IUL,
-3
IUL2
·10
'L.L3
·30
VOO - 2.0
Output Voltage High
jlA
Ports 4, 5, and 6,
Voo
= 5V ±
VOO
= 2.7V to 5.5V,
VDD
= SV
VOO
=2.7V 10 5.5V, 'OL =400,",
V
0.5
IlOH,
'"'
10%, IOH
'LOH2
30
'LOL2
-3
Vo
Supply VaHage
VOO OR
V
300
900
70
300
0.3
10
'DOOR
0.4
10
Capacitance
,!Fa
=25·C, VDD =OV
Umlts
P.r.meter
Symbol
M'n
T.p
Ma.
Unit
Te.t
Condition.
= 1MHz,
Input Capacitance
C.
20
pF
f
Output Capacitance
Co
20
pF
Unmeasured pins
returned to VSS
Input/Output
Capacitance
CliO
20
3-69
Vo = -30V
Data Retention Mode
Voo
= 5V
= 3V
= 5V
±
10%
VDO
= 3V ±
10%
Voo
Normal Operation
VOO
Stop Mode,
'002
Vo = -30V
= OV
20
Supply Current
-100,",
Ports 3, 4, 5, and 6,
-30
'00,
=
= 1.6mA
=
Output Leakage Current Low
2.0
II
= -1.0mA
'OH
± 10%, IOl
Vo
VOO
Ports 3, 4, 5, and 6,
'LOL2
= -30.0V
CLIo X,
0.4
Output leakage Current High
= VOO
= Veo
VI = OV
All Inputs Other than Cl" X,
_p,...0_rt...,
• .,.4,_5_._an_d_6_,_ _ _ _ _ _ _ _ _ VI
VOO - 0.5
VOL
VI
CLIo X,
V
VOH
Output Voltage Low
Porta 4, 5, and 6
CLIo Xl
IUHl
Input Leakage Current High
Test Conditions
All Inputs Other than Cl1. X,
0.3VOO
VIL1
Input Voltage Low
Unit
VOO
X,
= OV
Data Retention Mode, VODOR
= 2.0V
± 10%
± 10%
J.LPD7508A
AC Characteristics
T.
=
-10·C to + 70·C, vDD
= 2.7Vto 5.5V
.........,
P.,.me1'"
Icc
UmIta
MIn
1)p
M ••
150
200
240
75
100
120
R=B2k2±2%
C = 33pF ±5'110
R
c.33pF:t5%
410
CL,.
Voo = 5V ± 10%
125
External
Clock
VOO = 2.7V.o 5.5V
KHz
Sylrtam ClOck Alae and Fan Times
tcR·'CF
System Clock Pulae Width
'CH.'CL
'xx
75
135
10
10
0.2
1.1
50
3.5
50
25
Counter Clock Oscillation Frequency
32
=
CL,. CL2
RIC Clock
System Clock Oscillation Frequency
'C
TNt Conditione
UnH
".
CL1. Externa' Clock
".
External
Clock
50
410
VDD
CL"
160kQ :1:2%
0.2
".
X1. External Puln Input
".
X1' External Pulse Input
1.1
'XH.'XL
VOO = 5V t 10%
Input
VOO
= 2.7V to S.5V
5.0
SCKls
VOO
=
14.0
an
output
Voo
= 2.7V to 5.5V
1.3
SCKI.
YOO
z
".
SV :t 10%
5V t 10%
an
3.3
,..
2.2
Input
VOO • 2.7V 10 S.5V
SCKI.
YOO == SV:t 10%
an
6.5
SI Setup Time to SCKt
'SIK
.3
SI Hold Time after SCKt
'KSI
.45
,..
VOO = 5V ±
na
'KSO
VOO = 2.7V to &.5V
1200
1/(210.
VOO = 5V ± 10%
800)
Port 1 Output Setup Time to PSTSt
'PST
n.
1/(210.
VOO
2000)
100
Port 1 Output Hold Time .ner PSTSt
'STP
n.
100
'SL
INTO Pul.e Width
"OH' 'IOL
INT 1 Pul.. Width
'I,H"I,L
RESET Pul.. Width
'RSH"RSL
=
2.7V to 5.5V
VOO = 5V t 10%
VOO
1(210.
800)
PSTB Pulse Width
VOD = 2.7V.o 5.5V
output
".
650
SO Delay Time after SCK.
= 5V
VOO
= 2.7V to S.5V
:t 10%
YOO = 5V ± 10%
an
7.0
tKH.tKL
VOO
VOO = 2.7V 10 5.5V
SCKI.
3.0
SCi( Pulse Width
= 2.7V 10 5.5V
X1' External Pul•• Input
txA,txF
'KCY
VOD
X1. X2 Crystal Oscillator
3.5
Sci( Cyole Time
SV ± 10%
= IV:t 10%
135
Counter Clock Pulee Width
=
VDO • 2.7V to 5.5V
KHz
Ix
Counter Clock Ai.. and Fall Times
YOO
VOO = 3V ± 10%
=
2.7V to S.SV
VOO = 5V ± 10%
ns
1/(210.
2000)
VOO
,..
10
,..
,..
2/fc
10
3-70
2"
2.7V to 5.5V
",PD7508A
Timing Waveforms
~
ClocksC L , - - - - = . : . - ' c I
XI
'xt
O
~I__
_________
F
lIt
~'CR
_.
ICL
__
ICH
Y
Serial Interface
==t'------.
'XL _ ' _ I t o
'X'~~
~
-V+H
V,L
'XH
-V+H
'KCY
---------- -
V,L
'KL - - - - - l
SCK---------_
_VIH
1----------- VIL
-+-___---liir---Va-hd--i
''-__In..:.p_u':...o:,:a.::'a_...J-r -----------------
SI _ _ _ _ _ _ _ _
VIH
-VIL
SO,-------------'KS-Oj~----------------
~..._ _ _ _ _ _ _ _V._h_d_OU'__:..:pu::.'.::.oa::::'a=_______'X'________ -
VIH
VIL
Output Strobe
f - - - 'STP-----1
tpST
PSTB
~
-VIH
-VIL
I
Extemal Interrupts
INTO
INTI
Reset
RESET.
Data Retention Mode
VOO
RESET
'STL
~
'IOL
~
'I,L
~
OH
F'IIH==\
-VIH
VIL
-VIH
VIL
tRSL
t----Oata Retention
Ab·
F" =t
y_'RSH-\
-VIH
VIL
MOde~
~
3-71
_ VIH
-VOO
VI DR
VI~OR
II
"/-lPD7508A
Operating Characteristics
TypIcIII, T.
= 25°C
Supply Current
Supply Current
vs
Supply Voltage (No'.
_.
~
200
R
100
1:
.
,.
50
/
Co
/
V
/
V
:?:/
~
10
~
L
1:
,~
.
,.
V
./'
u
®)
20
~
§
(j))
C
l= 33pF
~
vs
Supply VOHage (Noto
/
0
Co
R = 160kQ
/
'"
'"
/
/
I
X2
R
l
20
ClIO
10
Cl = 20pF
C2 = 30pF
X,al = 32.788KHz
L
'tj
Supply Voltage
250
Voo (V)
Supply Voltage
= 330kQ
Voo (V)
Supply Current
Supply Current
vs
System Clock OscUlalton Frequency
(NOIe (j))
System Clock Oscillation Frequency
I cr;J~1
vs
(Note
VDD = 5.0V
250
roo~-.~~~~~c-
~
~
(j))
I Cr;J~1
Voo
I
I
200
= 3.0V
~
1:
1:
..
u
i
~ 150
I
I
foqt2
X,
R1
~
V
150
a..,
100
(/)
f--"'-f----f----i----i----+-l
100
C=100pF
~
__
50
f--f----f----if----i----+-l
200
300
Oscillation Frequency
400
~~
~
"'"
100
500
f+ (KHz)
200
300
OscIllation Frequency
400
f+ (KHz)
Notes:
(j) Only RIC system clock is operating and consuming power. All other intemallogic blocks are not active.
®
C=2r
50
I~
100
C=39pF
C=56pF
Only crystal oscillator clock is operating and consuming power. All other internal logic blocks are not active.
3-72
500
",PD7508A
Operating Characteristics (Cont.)
Typical, Ta
= 25°C
System Clock Oscillation Frequency
System Clock Oscillation Frequency
vs
V8
Supply Voltage
Resistance
IClhl,1
500
c=33PF
!~
~
:;. 200
"
~
~
!
c
100
I
~
""
t...
100
50
I
i
~
200
'CL~1~'
1=
1
VOO = 5V
VOO =
50
250
33pF
-
R = 82kQ
150
100
R
-
= 160kQ
50
500
Supply Voltage VOO (V)
ReSistance R (K Ohms)
Package Outlines
For information,._ Package Outline Section 7.
Plastic, jJ.PD7508AC
Plastic Shrinkdip, jJ.PD7508ACU
Ceramic Piggyback, jJ.PD75CG08E
3-73
7508AD5-REV2-7-83-TRIUM-CAT
II
NOTES
3-74
NEe
JLPD7508H
HIGH SPEED CMOS
4-BIT SINGLE CHIP
MICROCOMPUTER
Description
The f,tPD7508H is a high-speed CMOS 4-bit single
chip microcomputer which is based upon the f,tPD7500
series architecture.
The f,tPD7508H contains a 4096 x 8-bit ROM, and a 224 x
4-bit RAM. It contains four 4-bit general purpose registers
located outside RAM. The subroutine stack is implemented
in RAM for greater nesting depth and flexibility, providing
such operations as the pushing and popping of register
values. The f,tPD7508H typically executes 92 instructions
of the f,tPD7500 series "A" instruction set with 4f,ts instruction cycle time.
The f,tPD7508H has two external and two internal edgetriggered hardware vectored interrupts. It also contains an
8-bit timer/event counter and an 8-bit serial interface to help
reduce software requirements.
The f,tPD7508H provides 32 I/O lines organized into the 4-bit
input/serial interface Port 0, the 4-bit input Port 2, the 4~bit
output Port 3, and the 4-bit I/O Ports 1, 4, 5, 6, and 7. It IS
manufactured with a low power consumption CMOS process, allowing the use of a single power supply between
2.7V and 5.5V. Current consumption is less than 900f,tA
maximum, and can be lowered much further in the HALT
and STOP power-down modes. The f,tPD7508H is available
in a 40-pin dual-in-line plastic package. The f,tPD7508H is
downward compatible with the f,tPD7508 and the f,tPD7507.
The f,tPD7508H is ideally suited as a controller in the following applications:
D telephone/telecommunication equipment
D portable instruments
D automotive dashboard controls
D medical instruments
D portable and hand-held computer terminals
D office equipment
Development Tools
For software development, editing, debugging, and assembly into object code, you can use the NEC Development
System (NOS). Additionally, for systems supporting either
the ISIS-II (®Intel Corp.), CP/M (®Digital Research Corp.)
operating systems, or Fortran IV ANSI 1966 V3.9, the
ASM75 Cross-Assembler is available.
During software development, the code can be completely
evaluated and debugged with hardware by the Evaklt-7500
Evaluation Board. The Evakit-7500-RTT Real-Time Tracer
Board is an optional device used to examine operation of
your code in the actual prototype circuit. The SE-750~
System Emulation Board will emulate complete functionality of the f,tPD7508H for demonstrating your final system
design. All of these boards take advantage of the capabilities of the f,tPD7500 ROM-less evaluation chip to perform
their tasks.
Complete operation details on the f,tPD7508H CMOS
4-bit Microcomputer can be found in the f,tPD7506,
f,tPD7507, and f,tPD7508 CMOS 4-bit Microcomputers
Technical Manual.
Features
Advanced 4th Generation Architecture
Program Memory (ROM) size: 4K x 8-bit bytes
Data Memory (RAM) size: 224 x 4-bit nibbles
RAM Stack
Four General Purpose Registers: 0, E, H, and L
- Can address Data Memory and I/O ports
- Can be stored to or retrieved from Stack
D 92 Powerful Instructions, including
- Direct/indirect addressing
- Table look-up
- RAM stack push/pop
- Single byte subroutine calls
- RAM and I/O port single bit manipulation
- Accumulator and I/O port logical operations
- 4f,ts instruction cycle time, typically
D Extensive General Purpose I/O Capability
- One 4-bit input port
- Two 4-bit latched tri-state output ports
- Five 4-bit input/latched tri-state output ports
- Easily expandable with f,tPD82C43 CMOS
I/O expander
- 8-bit parallel I/O capacity
D Hardware Logic Blocks - Reduce Software
Requirements
- Operation completely transparent to
instruction execution
- 8-bit Timer/Event counter
- Binary-up counter generates INTTat
coincidence
- Accurate Crystal Clock or External Event operation
possible
- Vectored, Prioritized Interrupt Controller
- Three external interrupts (INTo, INT" INT2 )
- Two internal interrupts (lNTT' INTs)
- 8-bit Serial Interface
- 3-line I/O configuration generates INTs upon transmission of eighth bit
- Ideal for distributed intelligence systems or communication with peripheral devices
- Complete operation possible in HALT and STOP
power-down modes
D Built-in System Clock Generator
D Built-in Schmidt-Trigger RESET Circuitry
D Single Power Supply, Variable from 2.7V to 5.5V
Low Power Consumption Silicon Gate CMOS
Technology
- 900f,tA max at 5V, 400f,tA max at 3V
- HALT, STOP power-down instructions reduce power
consumption to 20f,tA max at 5V, 10f,tA at 3V
(Stop Mode)
D Extended -40°C to +85°C Temperature Range
Available
D 40-pin Dual-in-line Plastic Package
D
D
D
D
D
o
Revl1
3-75
IJ
ILPD7508H
Pin Configuration
Pin Identification
Pin
Clock OUt
EVENT
P201PSTB
VSS
P21/PTOUT
P43
P22
P42
P23
P41
Pl0
P40
Pll
P12
P53
P52
P51
P50
P31
P63
P32
P62
P33
P61
P70
P60
P71
P03lSI
P72
P02/S0
P73
P0 11!R:R"
RESET
POotlNTO
VOO
INT1
=2S'C
Operating Temperature
Storage Temperature
Power Supply Voltage, Voo
All Input and Output Voltages
Output Current (Total, All Output Ports)
Crystal Clock OUtput (active high) The Crystal Oscillator frequency IS
diVided by 12, and then output through a buffer
2-5
P20-P23
P2gfP;re
P2,/PT oUT
4-brt latched trI-state output Port 2 (active high). Line P20 IS also shared
with PSTB • the Port 1 output strobe pulse (active low). Line P2, IS also
shared wJth PrOUT' thellmer-oul F/F signal (active high).
609
P1 o·P1 3
4-blt I"put/tn-state output Port 1 (active high). Data output to Port 1 IS
strobed In synchronization with a P20/PSTB pulse.
-10'C to +70'C
-65'C to +15O'C
-O.3Vto+7.0V
-O.3V to Voo + O.3V
IoH = -20mA
IoL =30mA
4-brt mput/latched tn-state output Port 3 (active high).
14-17 P70·P73
4-brt Input/latched trl-state output Port 7 (active high).
18
RESET
RESET Input (active high). RiC circuit or pulse InJtlahzes .u,P07507 or
.u,PD7508 after power-up.
19.21
X"~
Crystal Clock Oscillator Input (active high). Connect a 4.19MHz crystal
across X" and Xl!'
20
V"
Power supply POSitive. Apply aingle voltage ranging from 2.7V to 5.5V
for proper operation.
22
INT,
External interrupt tNT, (active high). This IS a nsmg edge-triggered
Interrupt.
23·26 POJ!!:!!s.
PO,fSCK
Po,JSO
Po,fSI
4-blt Input Port OISenallfO Interface (active high). ThIS port can be
configured either as a 4-blt parallel Input port, or as the a-bJt serial 110
Interlace, under control of the serial mode select register. The Senal
Input SI (active hlgh~ Serial OUtput SO (active low), and the Serial Clock
SCK (active low) used fOr synchronizing data transfer comprise the 8-brt
serlSll/O Interface Lme POo Is always shared with extemallnlerrupt INTo
(active high) which ls a riSing ectge-trlggered interrupt.
27-30 P6,,-1'6,
4-blt Input/latched trf-state output Port 6 (active hlgh).lndlVfdual hnes
can be configured either aa inputs or as outputs under control of the
Port 8 mode select reglater.
31-34 P5,,'P5,
4-bit Input/latched trl-state output Port 5 (active high). Can also perform
8-bJt parallel 110 In conjunction wtth Port 4.
35·38 P4,.p4,
4-bJt Input/latched trf-state out;Jut Port 4 (active htgh). can also perform
8-blt parallel I/O In conJunction with Port 5.
X,
Absolute Maximum Ratings·
T.
Function
Clock Out
l1Jo13 P3,,·P3,
P13
P30
X,
Symbol
No.
39
Vss
Ground.
40
EVENT
EVENT counter pulse Input (active high)
·COMMENT: Exposing the device to stresses above
those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits described in
the operational sections of this specification. Exposure
to absolute maximum rating conditions for extended
periods may affect device reliability.
3-76
jJ-PD7508H
Block Diagram
P20·P23
H (4)
II
L(4)
Program Memory
Stack POinter (8)
4096 x 8-blt ROM (~PD1508H)
Instruction
Decoder
Data Memory
224 x 4-bit RAM (~PD7508H)
I,
t
System
Clock
Generator
j
Clock
Standby
Control
t
~
X,
X,
RESET
Voo
VSS
Out
DC Characteristics
Limits
Parameter
Input Voltage High
Symbol
Min
V,H
0.7 Voo
V1H2
Voo-O.S
Typ
Voo
Input Leakage Current High
V"
0.3 Voo
VILa
0.5
All Inputs Other than X,
V
10
RESET, Data Retention Mode
V
.A
-3
II.IL
-10
'lL.a
VOH
Output Voltage Low
VOL
Output Leakage Current High
ILOH
Output Leakage Current Low
ILO b
Supply Voltage
V ODPR
0.5
-3
V
300
150
1002
= 5V ± 10%,loH =
Veo = 5V ::t 10%, 10L
Vo
,.A
Vo
IOO[)R
0.4
10
3-77
-1.0mA
= 1.6 mA
= Voo
= OV
Data Retention Mode
Voo
Normal Operation
'00
10
= OV
Veo = 2.7V to S.SV,loL = 400 f.LA
900
0.5
VI
Voo = 2.7Vto5.5V,loH = -100j.l.A
20
Supply Current
= Voo
X,
,.A
V
2.0
VI
X,
Veo
V
Voo - 0.5
0.'
1001
All Inputs Other than X1
X,
All Inputs Other than X,
.A
Veo - 1.0
Output Voltage High
X,
All Inputs Other than Xl
IUH
IIH2
Input Leakage Current Low
Test Conditions
Unit
VOOQR +0.2
V1H3
Input Voltage Low
Max
Voo
.A
Stop Mode,
X,
= 5V ± 10%
Voo = 3V ± 10%
= OV
Data Retention Mode
Voo
= SV ± 10%
Voo = 3V ± 10%
VOODR = 2.0V
fJ.PD7508H
AC Characteristics
T. = -10·Cto +70·C,V oo = 2.7Vto 5.5V
Limits
Typ
MIn
Symbol
Parameter
Max
'120
TBO
TBD
60
TBO
TBO
TBO
TBO
Icc
TBO
60
System Clock Oscillation Frequency
10
Ic
32
300
fEVENT
icF" tCF
EVENT Pulse Mdth
tXH' tXL
KHz
Voo
R = 250kll ± 2%
Voo = 3V ± 10%
C=33pF±S%
,"Cy
EVENT
~s
Voo = 2.7VtoS.SV
EVENT
.s
.s
3.3
3.0
i
i
lSi.
300
t KSI
450
ns
n.
850
SO Delay Time after SCK !
t KSO
Port 1 Output Setull Time to P STB i
tpST
Port 1 Output Hold Time after PSTS i
tSTP
P STS Pulse Width
t.SWl
INto Pulse Width
~OH' tlOL
INT, Pulse Width
tl,WH,t'lWL
RESET Pulse Width
tASH'tRSL
1200
1I(21~"800)
300
350
300
.s
.s
10
21'$
10
Limits
Typ
Test
Ma'
Unit
Conditions
Input Capacitance
C,
15
pF
f= 1 MHz
Output Capacitance
Co
15
pF
Unmeasured pins
Input/Output Capacitance
ClIO
15
pF
returned to Vss
ns
ns
1/(21~"2000)
T. = 25·C, voo = OV
Min
500
1500
Capacitance
Symbol
ns
ns
1/(21","2000)
1/(21","800)
Parameter
SCK is an Input
SCK is an output
6.5
51 Setup Time to SCK
Voo
= 5V
Voo
= 2.7VtoS.SV
± 10%
3-78
Voo - 2.7V to 5.5V
Voo - 5V ± 10%
SCK is an output
1.8
SI Hold Time after SCK
= 2.7Vt05.5V
Von = SV ± 10%
6.7
tKH"~L
Voo
EVENT
SCK Is an input
14.0
SCK Pulse Width
Voo - 2.7VtoS.SV
Voo = 5V ± 100/0
KHz
4.0
7.0
SCK Cycle nme
10%
X1• X2 Crystal Oscillator
.s
1.5
3.5
= 5V ±
C=33pF±5%
Veo = 5V ± 10%
135
0.2
= 120kO ± 2%
Xh External Clock
50
EVENT Frequency
EVENT Rise and Fall Times
R
TBO
10
25
I,
Test Conditions
Unit
Voo
= SV ± 10%
Voo = 2.7V to S.5V
Voo = 5V ± 10%
Voo = 2.7VtoS.5V
Voo
=
Voo
= 2.7Vto 5.SV
Voo
= SV
Voo
= 2.7V to S.SV
5V ± 10%
± 10%
Voo
= 2.1V to S.SV
= SV ± 10%
Voo
= 2.7VtoS.SV
Voo
= SV ± 10%
Voo
Voo = 2.7VtoS.SV
f.LPD7508H
Timing Waveforms
Clocks
Xl~~~r_tc,~~."It= '"~
Serial Interlace
t
~--------t:"~1
-
t",
~'----------- -
y
_ _ _ _ _ _ _ _ _ _- '
Key
-
V'H
V,L
_ _ _ _oJ
_VIH
1"-_ _ _ _ _ _ _ _ _ _- - VIL
-!____Jr-v.
...--...
~ ln~pu_t~D~at~._~,-,---------------~--VIH
Sl _ _ _ _ _ _ _
__
Valid
-VIL
SO~-----t-KSO?--------
~_ _ _ _ _ _ _ _ _V._lid~OU=tP=u~t:Da:ta~_ _ _ _ _~)(
-VIH
-------'
VIL
Output Strobe
P1o·PI3'------------1
t psT - - - -
___
PSTS----------
J
... -----,
-VIH
-VIL
.,.,, _ _ _-1_
-----.:.IF '~H ==t
External Interrupts
INTo_~_t'"
-VIH
'--_________
1_----.:;
INT1--.i
t " - F
"H
===-\
-
VIH
VIL
~_________
RESET_~~:t_RS'_~_IRSH
VIL
Reset
- \
-VIH
'--_ _ _ _ _ _ _ _ _.
1VDD---------~~D
Data Retent/on Mode
RESET----.....:lH
VIL
ata Retention MOde----t
I
hdt-t,,-RS-----~
_
_VIH
__________________ -~~DoR
VIL DR
3-79
II
Package Outlines
For Information, se. Package Outlin. Section 7.
Plastic, ",PD7508HC
Plaatic Shrlnkdlp, ",PD7508HCU
3-80
7508HD8-Rev1-7-83-CAT-L
NEe
f.1PD7514
CMOS 4·BIT SINGLE CHIP
MICROCOMPUTER WITH
LCD CONTROLLERIDRIVER
Description
Pin Configuration
°1'"
!zoo_
The fLPD7514 CMOS 4-bit single chip microcomputer
has the standard fLPD750X architecture. It contains 4K x
S-bits of program memory ROM, 256 x 4-bits of data
memory RAM, an S-bit timer/event counter, and an S-bit
serial interface.
The on-chip LCD controller/driver is capable of driving a
variety of LCD displays configured from biplexed to quadriplexed (2-4 backplane). It can utilize up to 32 segment
and 4 common drive lines that are output from a 12S-bit
(32 x 4) display data memory.
The fLPD7514 also features 4 vectored interrupts (2 internal
and 2 external) and 2 standby modes. It is available in the
SO-pin plastic flat package to conserve space and is manufactured with a low power consumption CMOS process
allowing the use of a single 5V power supply. A powerful 92
instruction set (subset of fLPD750X Instruction Set A)
allows greater software flexibility.
The fLPD7514 is capable of forming a system with a
minimum amount of additional circuitry. It is designed to
operate with low power and can be used for a wide variety
of applications because the chip can generate a reference
clock for timer operations.
;~~~~~~~~~~~~~~M
o.D.o..D.o..D.o.D.D.D.D.a.D.a.D.a.
P4,
P4,
x,
x,
VLC3
VLC2
VLC1
COM 3
COM 2
COM,
COMo
S"
S"
So.
S"
S"
S"
RESET
S"
INn
S,
S,
S,
S,
NC
S,
S"
S"
S"
S"
NC
S"
Features
o 4-bit single chip microcomputer
o 92 instructions (subset of fLPD7500 set A)
o Instruction cycle: 5fLS/400kHz at 5V
o Program memory (ROM): 4096 x S bits
o Data memory (RAM): 256 x 4 bits
o Vectored interrupts: 2 externals, 2 internals
Vss
P3,
P3,
PI,
PI,
PI,
PI,
P2 olPS'i'B
P2,IPTOUT
P2,
P7,
P7,
P7,
P7,
CL,
CL,
Pin Identification
Pin
No.
Function
Symbol
VO
OS-bit timer/event counter
OS-bit serial interface
On-Chip LCD controller/driver
-1/2 bias: biplexed, triplexed
-1/3 bias: triplexed, quadriplexed
- Segment outputs: 32 lines
- Common outputs: 4 lines
Standby modes (stop/halt)
Low-power data retention capability
31110 lines
Dan-chip RC oscillator for system clock
On-chip crystal oscillator for count clock
CMOS technology
Single power supply
SO-pin plastic flat package
110 pins (4 bl1s) of Port 4 (4-blt 110 port).
Count Clock Oscillation pins to be connected to
crystal. Xl Is for External Clock input.
o
LCD bias voltage supply Input pins.
LCD common signal output pins.
12-22.
~:=!~: S,-5"
LCD segment signal output pins.
43-46
o
o
o
o
o
o
o
33
Voo
Power supply positive.
47
INT1
External Interrupt Input pin.
48
RESET
Reset Input pin.
System Clock Oscillation pins to be connected to Re.
49, 50 ell' c~
51-54 P7o-P73
55
56
57
el, IS tor External Clock mput.
110
P21/PTOUT
TOUT output (PTOUT).
P2,lPSTB
58-61 P1 o-P1 3
110
62,63, P3 -pa
3
0
65,66
64
67
68
69
70
3-S1
P01/SCK
1/0 pins (4 bits) of Port 1 (4·blt 1/0 port), not including
latches.
Output pins (4 bits) of Port 3 (4·bit output port~
V..
PO,lSI
Po,lSO
ItO pins (4 bits) of Port 7 (4---blt 1/0 port~
Output pins (3 bits) of Port 2 (3·bit output port). Com~
monly used as Strobe output (PSTB) for Port 1 output.
P2,
Ground.
1/0
110
Input pms (4 bits) of Port 0 (4-bit input port). Commonly uSf!!l!!.lnterrupt Request input (INTO). Serial
Clock 1/0 (SCK). Serial Data Input (51), Serial Data out·
pul (SO,
PO,tINTO
71-74
P6o-P6 3
If0
1/0 pins (4 bits) of Port 6 (programmable 4~blt I/O port).
75-78
PS,-P5,
1/0
110 pins (4 bits) of Port 5 (4~bit 110 port).
IJ
f.1PD7514
Block Diagra lTl
SCKlPO,
x,
x,
INT1
INTO/POo
Sl/POa
SOfPO:z
~~~o
PTOUT/P2 1
Program Memory
4096 x 8 Bits
Instruction
Decocter
P70-P7 3
3-82
j.LPD7514
Program Memory (ROM)
Program Memory is a mask-programmable ROM of 4096word x 8-bit configuration, and is addressed by the program
counter. Program Memory stores programs and table data.
Program Memory Map
The address locations of the program memory are from
OOOH to FFFH. RESET, Interrupt, start address, and the
table areas of LHLT and CALT instructions have been allocated specific memory locations. When a program is
generated, the aforementioned memory locations must be
taken into consideration.
OOOH
RESET Start Address
OtOH
INTT Start Addreas
020H
INTO/S Start Address
O3OH
INT1 Start Addres8
T
I
Subroutine
Entry
OCOH
OCFH
ODOH
OFFH
Look-up Table 01
LHLT Instruction
Look·up Table 01
CALT Instruction
(Can Addre.. Table)
11-------11
7FFH
FFFH
TL..-------IT
Timer/Event Counter Configuration
f-_-- (Co,ncld.nce SIgnal)
INTT
CP
f-+-.-- TOur (10 Seroallntertace)
Timer
Re....
CM, - - - - L . . . /
Not. .:
R 1----+---- INTS
POd'NTO
Notea. -
8:
~
100
= s.ov
ICgJ11
500
c = 39pF
C - 100pF
~~
I~
N'
C V56PF
/-~~ ~7PF
Q
9
E
~ 150
VOO
Resistance
"'" 200
;-
.,
>o
u
~
C=33PF
"-
1
&5V
C"
~
o
100
"-i~
o
~
~
0
50
L.
100
200
300
OSCillation Frequency
t,
400
500
(KHz)
50
100
200
Resistance R (K ohms)
Note:
,<~
0,
'"
AO
::~
A" '" 1'<-:
:-
",
0
tmPGtII
roM
,,1'02716
(EMOMI
0
'"
0
,
~
~
STEP
,
t=
~
IIREAK
ACC/f'C
0
'00
'"
'--
J
SF
6
6
1 : ).IPD556
2 : Pull-Up Resistors
3 : ).IPC7905 (3-Terminal 5 Volt Voltage Regulator)
4: ).IPD2716 (EPROM)
5 : ).IPD546C/).IPD547C Compatible Pins (42 Pins)
6 : EPROM Write Pads (24 Pads)
Operating Temperature ..... .
-10°Cto+70°C
Storage Temperature.
-25°C to +85°C
Supply Voltage, VGG
-15 to +O.3V
Input Voltages .... .
-15to+O.3V
Output Voltages . . . . . . . . . . .
-15 to +O.3V
Output Current (Total, all ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4mA
Ta=25°C
*COMMENT: Stress above those listed under" Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
3 -114
ABSOLUTE MAXIMUM
RATINGS*
MC·430P
MC-430P 42-PIN OPERATING
SPECI FICATIONS
DC CHARACTERISTICS
T a'" _1O
O
e to
+70"C VGG '" -10V
+
10% VSS
=
av·
LIMITS
SYMBOL
PARAMETER
MIN
TYP
MAX
Input Voltage HIgh
V,H
0
-20
V
Input Voltage Low
V,l
-43
VGG
V
Clock Voltage HIgh
V"H
0
Clock Voltage Low
V"L
-60
Input Leakage Current High
IUH
Input Leakage Current Low
'Lll
Glock Input Leakage Current High
Clock Input Leakage Current Low
-08
TEST
CONDITIONS
UNIT
Ports A through 0, INT,
RESET
Ports A through 0, INT,
RESET
V
CLO Input, External Clock
VGG
V
CLO Input, External Clock
+10
"A
RESET. V,
-10
"A
Ports A through D, tNT,
RESET, VI = ~11V
ILtPH
+200
"A
CLO Input, V$H = OV
ILcJlL
-200
"A
CLolnput,VI,bL=-11V
Ports A through D. INT,
=
-1V
VOH,
-1 0
V
Ports C through I,
IOH = ~1 0 mA
VOH2
-23
V
Ports C through I,
tOH = -3.3 rnA
Output Voltage High
AC CHARACTERISTICS
Output Leakage Current Low
'lOl
Supply Current
IGG
T a"" -10G e to +70"e, VGG '" -10V
PARAMETER
CAPACIT ANCE
:!:
-110
"A
-165
rnA
SYMBOL
MIN
liMITS
TVP
MAX
f
Rise and ~all Times
tr,tf
0
0.3
Clock Pulse Width High
t~WH
0.5
5.6
Clock Pulse Width Low
t~wl
0.5
5.6
=
150
440
UNIT
TEST
CONDITIONS
KH,
,JS
.'"'
EXTERNAL CLOCK
2SG C
liMITS
PARAMETER
CLOCK WAVEFORM
VO"'-1'V
10%
Oscillator Frequency
Ta
Ports C through I,
-10
SYMBOL
MIN
TVP
MAX
UNIT
Input Capacitance
CI
15
pF
Output Capacitance
Co
40
pF
Input/Output Capacitance
C,O
30
pF
1-----1/f-.:-----1
3-115
TEST
CONDITIONS
f '" 1 MHz
11
MC·430P
MC·430P 24·PAD
UV·EPROM
PROGRAMMING SPECIFICATIONS
~PD2716
DC CHARACTERISTICS
PROGRAM, PROGRAM VERIFY AND PROGRAM INHIBIT MODE
Ta = 25°C ± SoC, VCC
CD
0@
= +5V ± 5%, Vpp
= +25V ± 1V
LIMITS
PARAMETER
SYMBOL
MIN.
Input High Voltage
V,H
+20
Input Low Voltage
V ,L
..()1
Input Leakage Current
I,L
Vpp Current
Vee Current'
TYP
MAX.
V
V
+08
il0
.A
IpP1
+5
mA
IpP2
+30
mA
+100
mA
ICC
TEST CONDITIONS
UNIT
Vee +1
V IN ;;; 525V/O.45V
CE/PGM = V IL
:=: ~e::Zt
CE/PGM .. V I H Program Mode
AC CHARACTERISTICS
PROGRAM, PROGRAM VERIFY AND PROGRAM INHIBIT MODE
Ta = 25°C ± 5°C, VCC CD= +5V ± 5%,
Vpp~= +25V
± 1V
LIMITS
TEST
SYMBOL MIN TYP MAX UNITS CONDITIONS
PARAMETER
Address Setup Time
tAS
2
I'S
OE Setup Time
tOES
2
I'S
Data Setup Time
tDS
2
I'S
Address Hold Time
tAH
2
I'S
I'S
OE Hold Time
tOEH
2
Data Hold Time
tDH
2
Output Enable to Output Float Delay
tDF
0
Output Enable to Output Delay
tOE
Program Pulse Width
tpw
45
Program Pulse Rise Time
tpRT
5
ns
Program Pulse F all Time
tpFT
5
ns
I'S
120
ns
CE/PGM = VIL
120
ns
CE/PGM = VIL
55
m$
50
Test Conditions
o BV to 2 2V
Input Pulse Levels
Input Timing Reference Level ..
Nom
Output Timing Reference Level
O.BV and 2V
1V and 2V
CD
Vee must be applied Simultaneously or before Vpp and removed after Vpp
@
Outing programming, program Inhibit, and program verlfV.,8 maximum of +26V
should be applied to the Vpp pin Ovenhoot voltages to be generated by the Vpp
power supply should be limited t9 less than +26V
CAPACITANCE
LIMITS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
TEST
CONDITIONS
Input Capacitance
CIN
60
pF
VIN = OV
Output Capacitance
COUT
45
pF
VOUT= OV
3-116
MC·430P
PROGRAM MODE
TIMING WAVEFORM
"0-10
VALID INPUT
ADDRESS N + m
OQ.)
tDF
CE/PGM
II
Package Outlines
For information, see Package Outline Section 7.
Cerdip, MC-430PD
MC-430Pds-12-81-CAT
3-117
NOTES
3-118
NEe
SINGLE CHIP a·BIT MICROCOMPUTERS
II
NEe
",PD7800
HIGH END SINGLE CHIP 8-BIT MICROCOMPUTER
ROM-LESS DEVELOPMENT DEVICE
DESCR IPTION
F EATU R ES
PIN CONFIGURATION
The NEC /JPD7800 is an advanced 8-bit general purpose single-chip microcomputer
fabricated with N-channel Silicon Gate MOS Technology_ Intended as a ROM-less
development device for NEC /JPD780 117802 designs, the /JPD7800 can also be used
as a powerful microprocessor in volume production enabling program memory flexibility. Basic on-chip functional blocks include 128 bytes of RAM data memory, 8-bit
ALU, 321/0 lines, Serial I/O port, and 12-bit timer. Fully compatible with the
industry standard 8080A bus structure, expanded system operation can be easily
implemented using any of 8080A/8085A peripheral and memory products. Total
memory address space is 64K bytes.
• NMOS Silicon Gate Technology Requiring Single +5V Supply.
• Single-Chip Microcomputer with On-Chip ALU, RAM and I/O
- 128 Bytes RAM
- 32 I/O lines
• Internal 12-Bit Programmable Timer
• On-Chip 1 MHz Serial Port
• Five-Level Vectored, Prioritized Interrupt Structure
- Serial Port
- Timer
- 3 External Interrupts
• Bus Expansion Capabilities
- Fully 8080A Bus Compatible
- 64K Byte Memory Address Range
• Wait State Capability
• Alternate Z80™ Type Register Set
• Powerful 140 Instruction Set
• 8 Address Modes; Including Auto-Increment/Decrement
• Multi-Level Stack-Capabilities
• Fast 2/Js Cycle Time
• Bus Sharing Capabilities
A~
DB7
DBS
DB5
DB4
DB3
DB2
DB,
DBO
INT2
INf,
~
M'
WI\
1fD
"PO
7800
PC7
Pte
PCs
PC4
Pe3
PC2
PC,
~
SI
SO
A'ESE'f
STe
x,
VSS (OV)
TM: Z80 is a registered trademark of Zilog, Inc.
Rev/2
4-1
II
IlPD7800
PIN NO
1,49-63
2
3-10
DESIGNATION
ABO-AB15
EXT
DBO-DB7
11
12
INTO
INT1
13
INT2
14
WAIT
15
M1
16
WR
17
RD
18-25
PCO-PC7
26
SCK
27
SI
28
SO
29
30
R3E'f
31
33-40
41-48
STB
Xl
PAO-PM
PBO-PB7
FUNCTION
(Tri-State, Output) 16-bit address bus_
(Output) EXT is used to simulate j.lPD780117802
external memory reference operation_ EXT distinguishes between internal and external memory
references, and goes low when locations 4096
through 65407 are accessed_
(Tri-State Input/Output, active high) 8-bit true
bi-directional data bus used for external data
exchanges with I/O and memory_
(Input, active high) Level-sensitive interrupt input_
(Input, active high) Rising-edge sensitive interrupt
input. Interrupts are initiated on low-to-high transitions, providing interrupts are enabled.
(Input) INT2 is an edge sensitive interrupt input
where the desired activation transition is programmable. By setting the ES bit in the Mask
Register to a 1, INT2 is rising edge sensitive. When
ES is set to 0, INT2 is falling edge sensitive.
(Input, active low) WAIT, when active, extends
read or write timing to interface with slower
external memory or I/O. WAIT is sampled at
the end of T 2, if active processor enters a wait
state TW and remains in that state as long as
WAIT is active.
(Output, active high) when active, M1 indicates
that the current machine cycle is an OP CODE
FETCH_
(Tri-State Output, active low) WR, when active,
indicates that the data bus holds valid data. Used
as a strobe ~al for external memory or I/O write
operations. WR goes to the high impedance state
during HALT, HOLD, or RESET.
(Tri-State Output, active low) Frn is used as a
strobe to ~e data from external devices on the
data bus. RD goes to the high impedance state
during HALT, HOLD, and RESET_
(Input/Output) 8-bit I/O configured as a nibble
I/O port or as control lines.
(Input/Output) SCK provides control clocks for
Serial Port Input/Output operations_ Data on the
SI line is clocked into the Serial Register on the rising edge_ Contents of the Serial Register is clocked
onto SO line on falling edges_
(Input) Serial data is input to the processor
through the SI line. Data is clocked into the Serial
Register MSB to LSB with the rising edge of SCK_
(Output) SO is the Serial Output Port. Serial data
is output on this HilS on the falling edge of SCK,
MSB to lSB.
(Input, active low) ~initializes the j.lPD7800.
(Output) Used to simulate /-lPD780117802 Port E
operation, indicating that a Port E operation is
being performed when active.
(Input) Clock Input
(Output) 8-bit output port with latch capability.
(Tri-State Input/Output) 8-bit programmable I/O
port. Each line configurable independently as an
input or output.
PIN DESCRIPTION
",PD7800
BLOCK DIAGRAM
'6
~
AB6-15
"'"
AB()"7
ill
INC/DEC
PC
INTO
SP
INT,
INT2
INT
CONTROL
V
A
DATA
} MAIN
G.R
D
H
V
A
C
D
MEMORY
(128 BYTE)
I
ALT
G.R
PC4(TO
II
PA7-O
PC]i
PCflI
AD
HOLD HLDA
4-3
Wit
pe5/IOIM
M1
WAIT
RESET
STa
EXT
Vee Vss
X1
,..PD7800
Architecturally consistent with ~PD7801/7802 devices, the ~PD7800 uses a slightly
different pin-out to accommodate for the address bus and lack of on-chip clock
generator. For complete ~PD7800 functional operation, please refer to ~PD7801
product information_ Listed below are functional differences that exist between
~PD7800 and ~PD7801 devices.
j.lPD7800/7801 Functional Differences
1. The functionality of ~PD7801 Port E is somewhat different on the j.lPD7800.
Because the ~PD7800 contains no program memory, the address bus is made
accessible to address external program memory. Thus, lines normally used for Port
E operation with the j.lPD7801 are used as the address bus on the IlPD7800. ABOAB15 is active during memory access 0 through 4095.
2. Consequently Port E instructions (PEX, PEN, and PER) havE! different
functionality .
PEX Instruction - The contents of Bane! C register are output to the address bus.
The value 01 H is output to the data bus. STB becomes active.
PEN InstrUction - B and C register contents are output to the address bus. The
value 02H is output to the data bus. STB becomes active.
PER Instruction - The a~dress bus goes to the high impedance state. The value
04H is output to the data bus. STB becomes active.
3. ON-CHIP CLOCK GENERATOR. The IlPD7800 contains no internal clock generator. An external clock source is input to the Xl input.
4_ PIN 30. This pin functions as the X2 crystal connection on the IlPD7801. On the
IlPD7800, pin 30 functions as a strobe output (STB) and becomes active when a
Port E instruction is executed. This control signal is useful in simulating ~PD7801
Port E operation - indicating that a port E operation is being performed.
5. PIN 2. Functions as the 4> out clock output used for synchronizing system external
memory and I/O devices, on the ~D7801. On the ~PD7800, this pin is used to
simulate external memory reference oPeration of the j.lPD7801. EXT is used to
distinguish between internal and external memory references and goes low when
location 4096 through a5407 are accessed.
RECOMMENDED CLOCK DRIVE CIRCUIT
~
I.
__""_o+·
,.,07800
10K
31 Xl
C.DOMHz
4-4
FUNCTIONAL DESCRIPTION
",PD7800
ABSOLUTE MAXIMUM
RATINGS*
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10oe to +70o e
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°e to +150°C
Voltage On Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - O.3V to +7 .OV
'COMMENT: Stress above those lISted under "Absolute Maximum Ratmgs" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those mdicated in the operational sections of this specification is not
Implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
DC CHARACTERISTICS
Ta = -10°C - +70°C, VCc= +5.0V ± 10%
LIMITS
PARAMETER
SYMBOL MIN
Input Low Voltage
Input High Voltage
OUtput Low Voltage
MAX
UNITS
TEST
CONDITIONS
VIL
0
0.8
V
VIH1
2.0
VCC
V
Except SCK, X1
VIH2
3.8
VCC
V
SCK,X1
0.45
VOL
Output High Voltage
CAPACITANCE
TYP
VOH1
2.4
VOH2
2.0
V
IOL= 2.0mA
V
IOH=-1OO I'A
V
IOH =-500I'A
ILiL
-10
I'A
VIN =OV
ILiH
10
I'A
VIN = VCC
ILOL
-10
I'A
VOUT=045V
High Level Output Leakage Current
ILOH
10
I'A
VOUT = VCC
VCC Power Supply Current
ICC
110 200
mA
Low Level Input Leakage Current
High Level Input Leakage Current
Low Level Output Leakage Current
Ta=25°C,Vcc=GND=OV
LIMITS
PARAMETER
SYMBOL MIN
TYP
MAX
UNITS
Input Capacitance
CI
10
pF
Output Capacitance
Co
20
pF
Input/Output Capacitance
CIO
20
pF
4-5
TEST
CONDITIONS
fc = 1 MHz
All pms not
under test at OV
II
,..PD7800
AC CHARACTERISTICS
Ta ~ -10'C to +70'C. VCC ~ +5.0V ± 10%
CLOCK TIMING
LIMITS
PARAMETER
SYMBOL
MIN
MAX
2000
TEST
UNITS CONDITIONS
XOUT Cycle Time
tCYX
454
ns
tCYX
XOUT Low Level Width
tXXL
212
ns
tXXL
XOUT High Level Width
tXXH
212
ns
tXXH
READIWRITE OPERATION
LIMITS
PARAMETER
SYMBOL
RD L.E. - X OUT L.E.
tRX
Address (PEO.15) - Data
Input
tADl
MIN
MAX
TEST
UNITS CONDITIONS
ns
20
550+500xN
200(T3); 700(T4)
ns
ns
RD T.E. - Address
tRA
RD L.E. - Data Input
tRD
l'ilJT.E. - Data Hold
Time
tRDH
RD Low Level Width
tRR
RD L.E. - WAIT L.E.
tRWT
450
ns
Address (PEO.15)WAIT L.E.
tAWTl
650
ns
WAIT Set Up Time
tWTS
180
WAIT Hold Time
(Referenced from
X OUT L.E.l
tWTH
0
Ml ... RD L.E.
tMR
200
ns
RDT.E .... M1
tRM
200
ns
ns
350 + 500 x N
ns
ns
0
ns
850+500xN
ns
(Referenced from
XOUT L.E.)
120
ns
IO/1'iif "'1iU L.E.
tlR
200
"R15 T.E .... 101M
tRI
200
X OUT L.E .... WR L.E.
txw
270
ns
Address (PEO.15)'"
tAX
300
ns
XOUTT.E.
Address (PEO.15)'"
Data Output
tAD2
450
ns
Data Output ... WR
T.E.
tDW
600+500xN
ns
WR T.E .... Data
tWD
150
ns
Address (PEO.15) ...
WR L.E.
tAW
400
ns
W!'! T.E .... Address
tWA
200
ns
WR Low Level Width
tww
600+500xN
ns
loffiil... WR L.E.
tlW
500
ns
WI'! T.E ....
tWI
250
ns
ns
Stabilization Time
Stabilization Time
IOiM
4-6
tCYX
~
500 ns
"PD7800
AC CHARACTERISTICS
(CONT.)
SERIAL I/O OPERATION
PARAMETER
SYMBOL
MIN
MAX
UNIT
CONDITION
SCK Cycle Time
tCYK
SOO
900 4000
ns
ns
SCK Input
SCK Output
SCK Low Level Width
tKKL
350
400
ns
ns
SCK Input
SCK Output
SCK HIgh Level Width
tKKH
350
400
ns
ns
SCK Inp t
SCK Output
ns
SI Set·Up TIme (referenced from SCK T.E.)
tSIS
80
SI Hold Time (referenced from SCK T.E.)
tSIH
260
SCK L.E.
~
SO Delay Time
ns
1S0
tKO
~High -+ SCK L.E.
tCSK
100
SCK T.E. -+ SCS Low
tKCS
100
SCK T.E. -+ SAK Low
tKSA
ns
ns
ns
260
ns
MAX
UNIT
250
ns
PEN, PEX, PER OPERATION
PARAMETER
SYMBOL
MIN
X1 L.E. -+ EXT
tXE
Address (ABO.1S) ~ STB L.E.
tAST
200
Data (DBO.7) ~ STB L.E.
tDST
200
STB Hold Time
tSTST
300
tSTD
400
STB
~
Data
CONDITION
tCYX = 500 ns
HOLD OPERATION
PARAMETER
SYMBOL
MIN
MAX
UNIT
HOLD Set·Up Time (referenced from
X OUT L.E.)
tHDSl
tHDS2
100
lUU
ns
ns
HOLD Hold Time (referenced from ~OUT
L.E.!
tHDH
100
ns
XOUT L.E. -+ HLDA
tXHA
HLDA High
~
Bus Floating (High Z State)
H LOA Low ~ Bus Enable
tHABF
-150
tHABE
100
ns
150
ns
350
ns
CONDITION
Notes:
EO/ABOPE15/AB15
454
cj>OUT Low Level Width
cj>OUT High Level Width
tcj>cj>L
tcj>cj>H
tr,tf
150
cj>OUT Rise/F.II Time
2000
TEST
CONDITIONS
ns
ns
ns
150
40
ns
REAO/WRITE OPERATION
LIMITS
PARAMETER
'J!m L.E ..... cj>OUT
L.E.
Address (PEO.1S) .... Data
Input
mJT.E ..... Address
Rri L,E ..... Data Input
1rn"T.E, .... Data Hold
Time
SYMBOL
tRcj>'
MIN
100
tADl
tRA
lAD
tRDH
MAX
TEST
UNITS CONDITIONS
ns
550+5OOxN
ns
350 + 500 x N
ns
ns
2oo(T3); 7oo(T4)
ns
0
1f[) Low Level Width
tRR
FiD"L.E ..... WAlT L.E.
tRWT
450
ns
Addre$s (PEO.15) ....
WAIT L.E.
tAWTl
650
ns
WAIT Set Up Time
IRefereneed from
cj>OUT L.E.)
WAIT Hold Time
(Referenced from
cj>OUT L.E.l
Ml .... RD"L.E.
tWTS
290
tWTH
0
tMR
200
ns
FmT,E ..... Ml
tRM
200
ns
liR
tRI
tcj>'lI!
200
ns
tAcj>
100
ns
tAD2
450
ns
Data Output ....'WFf
T.E.
tow
6!lO + 500 x N
ns
WRT.E ..... Data
Stabilization Time
two
'160
ns
Address (PEO.15)'"
'WAL.E.
tAW
400
ns
WR T.E .... Address
tWA
200
ns
WR Low Lavel Width
tww
6OO+500xN
nl
IOI1\lf... WR L.E.
tlW
500
ns
WRT.E .... IO/M
tWI
260
ns
I
101M ... 1'ro L.E.
Fm T.E .... 101M'
cj>OUT L.E, .... WR L.E.
Address (PEO.15) ....
4>OUTT.E.
Address (PEO.15) ....
Data Qutput
850+500xN
ns
ns
120
ns
200
40
ns
125
ns
Stabilization Time
4-30
tCYcj>. = 500 ns
jJ..PD7801/7802
AC CHARACTERISTICS
(CONT.)
SERIAL I/O OPERATION
PARAMETER
SYMBOL
MIN
MAX
UNIT
CONDITION
SCK Cycle Time
tCYK
BOO
900 4000
ns
ns
SCK Input
SCK Output
SCi< Low Level Width
tKKL
350
400
ns
ns
SCK Input
SCK Output
SCi< HIgh
tKKH
350
400
ns
ns
SCK Input
SCK Output
ns
Level Width
SI Set-Up Time (referenced from SCK T.E.)
tSIS
80
SI Hold Time (referenced from SCK T.E.)
tSIH
260
"SCi< L.E. -+ SO
tKO
Delay Time
ns
lBO
~Hlgh -+ SCK L.E.
tCSK
100
SCK T.E. -+ SCS Low
tKCS
100
SCK T.E. -+ SAK Low
tKSA
ns
ns
ns
260
ns
HOLD OPERATION
PARAMETER
SYMBOL
MIN
MAX
UNIT
HOLD Set-Up Time (referenced from
SOUT L.E.)
tHDSl
tHDS2
200
200
ns
ns
HOLD Hold TIme (referenced from SOUT
L.E.l
tHDH
0
ns
/60UT L.E.
tDHA
-+
HLDA
HLDA High -+ Bus Floating (High Z State)
tHABF
H LOA Low -+ Bus Enable
tHABE
110
100
ns
-150
150
ns
350
ns
CONDITION
tCY = 500 ns
Notes:
IJtJl'lr~""ith~t~~ ____________ _
8-bit programmable InllIJt/Qutpu!P0rt-"'i!l1latch ___ _
Po~_6-bit nibble 1/0 or Contro--,Ip"-o_rt_ _ _ _ _ _ __
Port E.... __ 16-bit A~ress/O__"_tput port
Port A_ Port A is an 8-bit latched output port. Data can be
readily transferred between the accumulator and the output
latch buffers. The contents of the output latches can be
modified using arithmetic and logic Instructions. Data
remains latched at Port A unless acted on by another Port A
instruction or a RESET IS issued.
Port B_ Port B is an 8-bit I/O port. Data is latched at Port B
in both the Input or Output mode. Each bit of Port B can be
independently set to either Input or Output modes. The
Mode B register programs the individual lines of Port B to
be either an Input (Mode Bn = 1) or an Output (Mode Bn~o)
Port C_ Port C is a 6-bit I/O port with internal pull-up
resistors.
Port E (7aCOS)_ Port E IS a 16-bit address bus/output port.
It can be set to one of two operating modes using the PER
or PEX instruction.
D 16-bit address bus -the PER Instruction sets this
mode for use with external I/O or memory expansion
(up to 60K bytes, externally).
D 16-bit output port - the PEX instruction sets Port E to
a 16-bit output port. The contents of Band C registers
appear on PE 8 -PE '5 and PE o-PE respectively.
"
Address bus AB15-ABo (7aCOS)
These lines are the 16 bit-to-bit address bus to the main
memory. The 78C05, having no internal ROM, must
address the area from 0 to 4096 as external ROM.
The 78C05 AB lines are unlike the 78C06 PE lines in that
they have no internal latches. When the Port E output
instruction PEX is executed In a 78C05, the register pair
BC is output to the AB lines for only one clock cycle during
the third machine cycle. This is provided to allow external
hardware to emulate the Port E operation of the 78C06.
4-37
II
fJ.PD78C06178COS
Functional Description (Cont.J
<--- ------- --------- - --------PEX Instructlon---- - - - - - - - - - - - - - - - - - - - - - - - >
1----1----1----1---- 1----1---- 1----I ---- 1---- 1 ----I ----1---- 1
1,
12
13
14
T,
T2
T3
14
T,
T2
13
M,-I--------------\~--------------------------------------------AB~~____~1.~t~B~~e~F~et=ch~____~X~
______~2~n~d~B~~.~F~etc~h~_____JX~__~B~C__~X~______________
Timer Block DIagram
I N 5 T R U C T I O N - - < . . - - - - - - - - - - - - - - - - + - - - - - - . -_____________~--------------___,
Prescaler 1
(3)
System Clock = Oscillation Frequency x 1/4
Timer operation
A programmable 8-bit timer is provided on-chip for
measuring time intervals, generating pulses, and general
time-related control functions. It is capable of measuring
time intervals from 811s to 32ms in duration. The timer consists of a prescaler which decrements an 8-bit counter at a
fixed 811s or 12811S rate. Count pulses are loaded into the
8-bit upcounter through the timer register.
Countup operation is initiated upon execution of the STM
instruction when the contents of the upcounter are fully
incremented and a coincidence occurs, an interval interrupt
(INTT) is generated. Count operation may be reinitialized
with the STM instruction. The duration of the timeout may
be altered by loading new contents into the timer register.
The timer flip-flop is set by the STM instruction and reset
on a countup operation. Its output (To) is available externally and may be used for general external
synchronization.
Timer interrupt (INTT) may be disabled through
the interrupt.
Serial Port Block Diagram
51
50
Octal Counter
S
Start $1/0
R
T8
4-38
T.(INT5)
/J-PD78C06178COS
Functional Description (Cont.)
15
Serial port operation
The on-chip serial port provides basic synchronous serial
communication functions allowing the NEC fLPD78C06/05
to serially interface with external devices.
Serial transfers are synchronized with either the internal
clock or an external clock input (SCK). The transfer rate is
fixed at 0.5 Mbitlsecond if the internal clock is used or is
variable between DC and 0.5 Mbit/second when an external clock is used. The Clock Source Select is determined
by the Mode C register. The serial clock (internal or external SCK) is enabled when the Serial Chip Select signal
(SCS) goes low. At this time receive and transmit operations through the Serial Input port (SI)/Serial Output port
(SO) are enabled. Receive and transmit operations are
performed MSB first.
Interrupt structure
The fLPD78C06/05 prOVide a maskable Interrupt
structure capable of handling vectored prioritized
interrupts. Interrupts can be generated from six different
sources: two external interrupts, two internal interrupts,
and nonmaskable software interrupt. When activated each
interrupt branches to a designated memory' vch
interrupt branches to a designated memory vector location
for that interrupt.
Interrupt Structure
INT
Vectored Memory
Location
Internal, Timer
INTT
Overflow
External, level sensitive
INT.
INT,
Type
Priority
16
External, RIsing edge
sensitive
RESET (Reset)
An active-low signal on this input for more than 4f.Ls forces
the fLPD780C06/05 into a Reset condition. RESET affects
the following internal functions:
The Interrupt Enable flags are reset, and interrupts
are inhibited.
The Interrupt Request flag is reset.
The Halt flip-flop is reset, and the Halt state is released.
The contents of the Mode B register are set to FF H , and
Port B becomes an input port.
All flags are reset to O.
The internal Count register for timer operation is set to
FFH and the timer F/F is reset.
The contents of the prQg!am counter are set to OOOOH'
Data bus (DBo-DB7)' RD, and WR go to a high impedance state.
Once the RESET input goes high, the program is started at
location OOOOH'
Registers
The fLPD78C06/05 contain seven 8-bit registers and two
16-bit registers.
o
o
o
o
o
o
o
o
PC
SP
General purpose registers. The general purpose registers A, B, C, 0, E, H, l, can function as auxiliary registers to
the accu~~lator or in pairs as data pointers (BC, DE, HL).
Auto~~t!C Increment and decrement addressing mode
capabilities extend the uses for the DE and HL register pairs.
Accumulator (A)
All data transfers between the fLPD78C06/05 and external
memory or 1/0 are done through the accumulator.
Program counter (PC)
The PC is a 16-bit register containing the address of the
next instruction to be fetched. Under normal program flow,
the PC is automatically Incremented. However, in the case
of a branch instruction, the PC contents are from another
register or an instruction's immediate data. A reset sets the
PC to OOOOH'
Stack pointer (SP)
The stack pointer is a 16-bit register used to maintain the
top of the stack area (Iast-In/flrst-out). The contents of the
SP are decremented during a Call or Push instruction or if
an interrupt occurs. The SP is incremented during a Return
or POP instruction.
Address Modes
Register addressing
Register indirect
addressing
Automatic increment
addressing
Automatic decrement
addressing
Working-register
addressing
Direct addressing
Immediate addressing
Immediate extended
addressing
Register addressing
~
r
.~
The instruction opcode specifies a register r which contains
the operand.
Register indirect addressing
The instruction opcode specifies a register pair which contains the memory address of the operand. Mnemonics with
an X suffix are ending this address mode.
4-39
II
/-LPD78C06IVac05
Address Modes (Cont.)
Automatic increment addressing
Instruction Set Definitions
rp
Operand
r
rl
r2
sr
Memory
~------------~'~~-----~~----~.~
EI
'------1-
The opcode specifies a register pair which contains the
memory address of the operand. The contents of the register pair are automatically incremented to point to a new
operand. This mode provides automatic sequential stepping when working with a table of operands.
srl
sr2
rp
rpl
rpa
wa
Automatic decrement addressing
rp
word
byte
bit
if
F
Memory
~r-------------'I~r-----~~------'Io~~ndl
G
'-------1-
Not.s: 1. When special register operands sr, sr1, sr2 are used, PA =
Working-register addressing
PC
PC
Description
A,B,C,D,E,H,L
B,C,D,E,H,L
A,B,C
PA, PB, PC, MK, MB, TM., TM" S,
SM,SC
PA, PB, PC, MK, S, TM., TM " SC
PA, PB, PC, MK
SP, B, D, H
B,D,H
B, D, H, D+, H+, D-, H8-bit immediate data
la-bit immediate data
B-bit immediate date
3-bit immediate data
FO,l, FT, FS
CY,Z
I
+1
Memory
I
Operand
2.
3.
4.
The contents of the register are linked with the byte following the opcode to form a memory address which contains
the operand. The V register is used to indicate the memory page. This address mode is useful as a short-offset
address mode when working with operands in a common
memory page where only one additional byte is required
for the address. Mnemonics with a W suffix indicate
this address mode. In the 78C06/0S the V register is
always FFH.
5.
6.
Port A, PB = Port B, PC = Port C, MK = Mask register,
MB = Mode B register, MC = Mode C Register, TM. =
Timer register 0, TM, = Timer register 1, S = Senal register.
When regi~ter pair ~perands_rp, rp1 are used, SP = Stack
Pointer, B - BC, D - DE, H - HL.
Operands rPa, rPa1, wa are used In Indirect addressing and
auto-incrementlauto-decrement addressing modes.
B = (BC), D = (DE), H = (HL)
D+ = (DE)+, H+ = (HL) + ,D- = (DE)-, H- = (HL)-.
When the interrupt operand If is used, 1=0 = INTF'O, F1 =
INTF1, FT = INTFT, FS = INTFS.
When the operand F is used, CY = Carry and Z = Zero.
The V register IS always FFHex.
Instruction Set
No.
Mnemonic Operand Bytes
Clock
ere•••
Operation
8-bit Data Transfer
MOV
MOV
MOV
MOV
MOV
MOV
MYI
Direct addressing
r1,A
6
6
14
14
A, ,1
.r,A
A, .,,
r,word
r1-A
A_r1
sr_A
A-ar1
,-(word)
word. ,
25
25
',by1e
11
r-byte
14
(V,wa}_A
lOAW
wa
wa
14
A_(V,wa)
STAX
rps
39
The two bytes following the opcode specify an address of a
location containing the operand.
lOAX
,pa
('pa)-A
A-(rpa)
seCD
word
28
(word) +- C, (word
Immediate addressing
PC
PC + 1
Immediate extended addressing
PC
PC + l'
PC + 2
SDED
word
_d
28
28
(_d) - E, (word
28
(word) - SPL•
Opcode
PC
PC
+1
Low Address
PC + 2 High Address
I
Operand
I
STAW
1 Byte
9
(word)-r
18·bit Data Tr.n.....
SHLD
+ 1) +- B
+ 1) - D
(word) - L, (word + 1) - H
SSPD
_d
LBCD
word
4
28
C-(word~
B-(word + 1)
LDED
word
4
28
E-(word~
D-(word + 1)
Low Operand
LHlO
word
28
L_(word~
H -(word + 1)
High Operand
LSPD
word
28
PUSH
rp1
21
POP
rp1
18
LXI
rp, word
16
Opcode
4-40
(word
+ 1) -
SPH
SPL-(word~
SPH-(word
+ 1)
(SP -1)~rp1H'
(SP - 2)-'p1 L
rp1 L _(SP)
rp1 H-(SP + 1~
sp-sp + 2
rp-word
Skip ~
Condition CV Z
f,1PD78C06/78C05
Instruction Set (Cont.,
No.
Instruction Set (Cont.,
Clock
Mnemonic Operand Bytes Cycl..
Operation
Skip
Fla.s
Condition CY Z
No. Clock
Mnemonic Operand Bytes Cycl••
Arithmetic
ADD
A"
ADDX
rpa
ADC
r2
INRW
WI
A,r
A-A + ('pa)
A_A+r+CY
DCA
r2
ADCX
rpa
15
A_A + (rpa) + CY
DCRW
WI
SUB
A"
12
A-A-r
INX
rp
SUBX
rpa
15
A_A - (rpa)
DCX
rp
SBB
A,'
12
A_A-r-CY
SBBX
rpa
15
A_A - ('pa) - CY
SUBNB
15
A_A
+ (rpa)
SUBNBX ,po
15
A -A
+ (rpa)
No Carry
STC
No Borrow
CLC
rpa
A,r
12
A_AVr
ORAX
rpa
15
A-AV(rpa)
XRA
A,r
12
A_AVr
rp_rp+1
rp_rp -1
Doclrnal Adjust
CV_1
CY-O
Rotate Lell Dlg,t
17
Rotate Right Digit
Am
RAL
Am + 1-Am,Ao-CY,
RAL
15
A_A¥(rpa)
12
A - r-1
No Borrow
OTAX
rpa
15
A - (rpa) - 1
No Borrow
JMP
LTA
A,r
12
A- r
Borrow
JB
LTAX
rpa
15
A - (rpa)
Borrow
ONA
A,r
12
AAr
No Zero
JR
JRE
ONAX
rpa
15
AA (rpa)
No Zero
OFFA
A,r
12
AAr
Zero
OFFAX
rpa
15
AA (rpa)
Zero
NEA
A,r
12
A - r
NEAX
rpa
A,r
EQAX
rpa
15
12
15
A - (rpa)
EQA
Zero
No Zero
Zero
Zero
XRI
A, byte
CY-A1
Jump
word
10
word
13
PC-PC + 1 + Jdl_p1
word
13
PC-PC
CALL
word
16
CALF
word
16
CALT
word
19
Immedillte Dabi Transfer (Accumulator)
ADINC
A, byte
7/11
A-A+byte
No Carry
A, byte
7/11
A_A - byte
No Borrow
PC_word
II
+ 2 + Jdlsp
Can
No
SUINB
+ 1_Am,Ag_CY,
CY-#.,
Am - 1 -Am,A7 -CV,
CY-A.
RAR
A,r
A-A¥byte
Borrow
17
rpa
7/11
Borrow
(V, wa) - (V, wo) - 1
RRD
XRAX
2
Carry
r2_r2-1
RLD
OTA
A- r
A - (rpa)
Carry
Rotate and Shift
11115 A_A \ (rpa)
ANAX
r2-r2+1
(V, wo) _ (V, wa) + 1
Accumulator
No Borrow
A.r
ORA
13
DAA
Logical
ANA
13
Miscellaneoua
No Carry
A,'
Skip
Flags
Condition CV Z
Increment/Decrement
INR
15
12
ADDNC
A"
ADDNCX rpa
Operation
(SP - 1) _(PC - 3).,
(SP - 2) _(PC - 310.,
PC-word
(SP -1)_(PC - 2).,
(SP - 2)_(PC - 2lL,
pet5 -PCt1
-00001,
petO-pc;. _fa
(SP (SP PCL PC. -
t)_(PC - 1).,
2)-(PC -IlL,
(126 - 2Io~
(129 + 2te)
btum
ADI
A, byte
7/11
A_A+byte
ACI
A, byte
7/11
SUI
A, byte
7/11
A-A + byte + CY
A_A - byte
SBI
A, byte
7/11
A_A - byte - CY
ANI
A, byte
ORI
A, byte
7/11
A_AVby1e
on
A, byte
7/11
A - byte - 1
No Borrow
LTI
7/11
A - byte
Borrow
SKNC
SkiP If No Carry
DNI
A, byte
A, byte
7/11
AAbyte
8KNZ
Skip d No Zero
Z=o
OFfi
A, byte
7/11
AAbyte
SkiP If No INT X
'=0
RET
11
PCL -(SP~ pc.-(SP + 1)
SP_SP - 2
RETS
PCL -(SP~PC.-(SP + 1)
REn
15
PSW-(SP+2~
SP-SP+3,SIRQ-O
Skip
NEI
A, byte
7/11
A - byte
Zero
Zero
No Zero
EDI
A, byte
7/11
A - byte
Zero
ANI
sr2, byte
3
17
sr2 - sr2 A byte
EI
Enable Interrupt
ORI
sr2, byte
3
17
.r2 - sr2 V byte
DI
Disable Interrupt
OFFI
or2, byte
14
..2 A byte
DNI
sr2, byte
14
.r2 A byte
No
8KNIT
otherwise reset INT X
CPU Centrol
NOP
Immedlat. Dalai Transfer (Specla. Register)
No Operation
Serial Por1 Control
Zero
Zero
Start (Trigger) SenaillO
Start Timer
SIO
No
S11I'I
Working Ragim.
Port .: Control
ANIW
WI, byte
16
(y, WI) - (y, WI) A byte
ORIW
WI, byte
16
(y, WI) - (y, wa) V byte
onw
wo, byte
13
(y, WI) - byte - 1
No Borrow
LTIW
WI, byte
13
(y, WI) - byte
Borrow
ONIW
wo, byte
13
(V, wa) A byte
No
OFFIW
WI, byte
13
(y, wa) A byte
Zero
NEIW
WI, byte
13
(V, wa) - byte
No Zero
EQIW
W8,
byte
13
(y, wa) - byte
Zero
Zero
4-41
PEX
11
PER
11
PE'5_a-B,PE7_0-C
Port E AB Mode
CY = 0
f.LPD78C06/78COS
DC Characteristics
Program Status Word (PSW) Operation
Operation
Reg. Memory
Immediate
ADD
ADC
SUB
SBB
ADDX
ADCX
SUBX
SBex
ADI
ACI
SUI
SBI
ANA
ORA
ANAX
ORAX
ANI
ORI
XRA
XRAX
XRI
SUINB
GTI
LTAX
NEA
EQA
INR
OCR
D3
D2
DO
Z
SK
He
L1
LO
CY
Skip
Ta
= -10°Cto
+ 70°C; Vee
= 5V
± 10%
Limits
ANIW
ORIW
SUBNB
GTA
ONAX
OFFAX
D4
Parameter
AD:cINccc:----
lTA
D5
Symbol
Tvp
Min
Input High leakage ILIH
Current
Input Low Leakage
Current
GTIW
LTI
lTIW
ONI
OFFI
ONIW
OFFIW
Output High
leakage Current
NEI
EQI
NEIW
EQIW
Output Low
Leakage Current
Max
"'11L"-,_ _-_B=--_ _ _ _
-:::90~_
IIl2
-40
Input low Current
~AD:CD:CNccC:---AC::DDNCX
SUBNBX
GTAX
D6
Unit
3
f.l,.A
VIN - Vce
(Except REl, X,)
-3
f.l,.A
YIN - OV Except WAIT,
PCO-PC 5 ,X,
f.l,.A
YIN - OV
(Stop Mode, X,)
-3
------
NEAX
EQAX
-3
'lOl
INRW
DCRW
lecl
Vce Supply Current
DAA
Test Conditions
_'.::.A~.:oV'"'N_=--=O"_V-'(W:.cAc:12T,'_P.::.Co"_-,--"PC. 5 )
f.l,.A YIN = OV (X,)
3.5
6.0
p..A
YOUT = Vec
f.l,.A
VOUT = OY
rnA
Operation Mode
c"'lc...,C2~_ _ _ __:0C_.8-_-c:1.c_B--m-:A-c:Hac_I'-Mc::oC_dc_.-=-=
'ee3
15
Stop Mode (X, - OV,
X2 = Open)
f.l,.A
RLL, RLR
RLD- RRD
Low Power Data Memory Retention
Characteristics for Stop Mode Operation
Ta = -10°C to + 70°C
5TC
CLC~_ _ _ _ _ _~~~_ _ _ _ __
_ _ _ _ _ _ _ _--"M::cV~1A., by'.
Limits
MVI L, byte
LXI H, word
Symbol
Parameter
5KNC
5KNZ
SKNIT
RETS
Data Retention
Voltage
VCCDR
Data Retention
Supply Current
IceOR
Min
t
0.8
Flag affected accordmg to result of operation
1 Flag set
a Flag reset
•
'5
REL Input Delay
Time
'0
Test Conditions
i~e~~;e2~fV' (X, = OV,
p..A
0.2YeeDR
V
YCCDR
V
0.8VeeDR
Flag not affected
Unit
v
,--_--c--=A-'-II-'o'-'h=er jns.,-'r,-uc=-:'c:.,o"-ns~_ _ _ _ _ _ _ _~_ _ _,-_-,,,-_ _
Notes:
Max
Typ
2.0
500
.s
.s
Absolute Maximum Ratings*
REL Input High Time tREL
ITa = 25°C)
Notes: In data retention mode. Input voltages to WAIT and PCO-pe 5 pins (with pull-up resistors)
~upplyVoltage,
Vce
Input Voltage, V,
-O.3Vto +7.0V
- O.3V to Vec + O.3V
Output Voltage, Vo
- O.3V to Vee + O.3V
10
should be maintained same as V CCDR level, other Input voltages should be kept less than
V CCDR level
"O-=u",tp",u",tccH-'Ci",g'-Ch--=C,-,u",r'-Cre=-:n'-Ct",1""0"'HC'(=D-=ec..vi-=c-=e--="-=0'-Cta:::I)'-_.________ .-_5m_~
Output Low Current, 10L (Device Total)
43.5mA
-=O-"p-=e.:cra:c:t::.:in,",g...".:ce=-:m=-:po:.e",r-=a",tu:c:r-=e,-,T.:c0....p' =-T'-_ _ _ _ _ _ _ _-10°C to + 70°C
Storage Temperature, TSTG
- 40°C to + 125°C
Limits
Address (PEo-PE
to Data Input
RD LE to Data Input
Input High Voltage
Unit
1200
+1000
xN
'RA
300 (T,)
1300 (T,)
ns
700
+ 1000
tRD
ns
x N
RD TE to Data Hold
Time
Max
Unit
Test Conditions
RD low Time
'RR
1700
+1000
ns
Except D80-DB7, X1
V1H2
Vee - 2.0
Vee
DBo-D87
RD LE to WAIT LE
VIH3
Vee - 0.5
Vee
V
X,,'_ _ _ _ _ __
0.3Vec
V
Except OBo-DB 7• X,
Address (PEo-PE,s)
1200
ns
toWAITLE
WAIT Set-u p-=T:-'m-.-:'-o-'-WT-S---6-0-0-------n-s
0
"V''''12'--_-'''-_ _ _ _-'O-:.Bc-_-ccV_ccD__
Bo...-_D_B"-,_ _ _ _~
VOH1
Output Low Voltage Val
Test Conditions
ns
Vee
VOH2
Input High Current
.
Max
O.7Vcc
VIL.3
Output High Voltage
Typ
300
V1H1
V'Ll
Input Low Voltage
Typ
Min
,5)
RD TE to Address
Limits
Min
'R.
RD LE to 4>OUT LE
DC Characteristics
Symbol
Symbol
Parameter
Ta = -10°C to + 70°C; Vee = 5V ± 10%
Parameter
DC Characteristics
Read/Write Operation
*COMMENT: Exposing the device to stresses above
those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be
operated under conditions outside the limits described
in the operational sections of this specification. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
0.5
V
X,
2.4.-:c:::-_ _ _ _ _~V-C"lo"'-H-=---1=0:=0'::.A"---Vee - 0.5
V
IOH = -50f.l,.A
0.45
700
90
f,iA
VIN = Vce{REl)
IIH2
40
f.l,.A
YIN = Vee (X,)
ns
4>OUT lE
: : ; ~Id Time after
~OUT
4-42
LE to WR LE
ns
tWTH
VIOL = 1.8mA
I'H'
x N
tw
200
ns
300
ns
250
ns
t CY '" = 1000ns
I-LPD78C06/78C05
DC Characteristics (Cont.)
Capacitance
Read/Write Operation
T. = 25"C;Vcc = GND = OV
Limit.
Parameter
Symbol
Address (PEo-PE 15)
to Da1a Oulpul
lAD,
Data Output to WR TE tDW
Typ
Min
Limits
Max
Unit
Test Conditions
ns
850
1200
+1000
x N
ns
Parameter
Unit
15
pF
Co
15
pF
CliO
15
pF
Input Capacitance
C,
Output Capacitance
1/0 Capacitance
Typ
Max
Symbol
Min
WR TE to Da1a Stable
Time
two
300
ns
AC Characteristics
Address (PEo-PE'5)
toWRLE
lAW
800
ns
T. = -10"Cto +70·C;Vcc = +5V ± 10%
Clock Timing
WR TE to Address
Stable Time
tWA
300
ns
WRLowTlme
Iww
1200
+1000
xN
ns
WR LE to WAIT LE
Iwwr
ns
=
Limits
Symbol
Min
X, Input Cycle Time
teyx
227
X, Input Low Time
X, Input High Tllne
tXXL
108
tXXH
106
!POUT Cycle Time
Icv.
908
!POUT Low Time
t...L
300
!POUT High Time
t ..H
300
!POUT RlselFall Time
tR,IF
Parameter
250
test Conditions
Ie 1MHz
Unmeasured pms
returned to OV
Note.: CD Applies only to IJ.PD78C05
N IS number of TWAIT
LE IS leading edge, and TE IS trailing edge
Serial Operation
Typ
Max
Unit
10000
ns
Test CondltiDns
ns
ns
40000
ns
ns
ns
150
ns
Limits
Parameter
Symbol
IcvK
SCK Low TIme
Io384 "" 'XTAL x Vo!e4
Bit Address Instructions
The following bits may be addressed directly with certain
instructions:
Any bit in a 16-byte group in RAM
Any bit in the five 8-bitl/O ports (A, B, C, D, F)
Any bit in the variable threshold port
Any bit in the following special registers:
9-bit interrupt mask register, serial mode register, timer
mode register, timer/event counter output register
An addressed bit may be tested, set, cleared, or
complemented.
An addressed bit may be moved to or from the carry flag.
An addressed bit may be ANDed, ORed, X-ORed with the
carry flag.
o
o
o
o
Difference between the ILPD7801, ILPD7811,
ILPD7807, and ILPD7809
"PD7BOI
_7811
ePD7B07
Number of Instructions
134
158
185
165
1..,1t Operation Instruction
No
vel
Yes
Yes
1"",a/12MHz
MultiplylDlvide instruction
Instruction Cycle
Number of General-purpose
FIog"'l8r.
On-chlp ROM CapacHy
No
Yes
Yes
Yes
2""14MHz
1""112MHz
1""112MHz
18
18
16
4K By\8I
4KByte.
No
"PD78"
18
8K By\8I
On-chip RAM CapacHy
128 By\8I
256 By\8I
256 Bytel
256 By\8I
Dlrect·AcId_ble External
Memory Capacity
&oK By1ea
&oK By1ea
S4K Byte.
56KBy\8I
Interrupt
Internal
Source
External
110 Lines
Threahold Variable Port
TImer/Counter
Timer
COunter
Watchdog TImor
Asynchronoul
3
48
40+4
No
No
8 Bits
8 BI11
12 BIts
8 Bttax 2
8Bltax2
8 Bttax2
No
No
168H8
16Bit8
16 BI1a
No
Yes
No
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
AID Converter
No
Yes
Yes
Yes
Yes
Standby Function
No
Yea
Hold function
Yes
No
Serial Interface SynChronous
1I0Interfaca
Technology
Package
No
vel
28'
Yes
Yes
No
Yes
Yes
40
NMOS
NMOS
NMOS
NMOS
64-Pm Flat
S4-P,nQUIP
S4-PlnQUIP
64-Pm QUIP
.. at 4K~byte Access
Package Outlines
For Information, s_ Package Outline Section 7,
Plastic Quil, .,.PD7807G/09G
Plastic Shrlnkdlp, .,.PD7809CW/07CW
780917807178P09DS-7-83-CAT-L
4-49
Notes
4-50
NEe
Description
The NEC J.1.PD7810/J.1.PD7811 is a high-performance
single-chip microcomputer integrating sophisticated onchip peripheral functionality normally provided by external
components. The device's internal 16-bit ALU and data
paths, combined with a powerful instruction set and
addressing, make the J.1.PD7810/7811 appropriate in data
processing as well as control applications. The device
integrates a 16-bit ALU, 4K-ROM, 256-byte RAM with an
8-channel A/D converter, a multifunction 16-bit timer/event
counter, two 8-bit timers, a USART and two zero-cross
detect Inputs on a single die, to direct the device into fast,
high-end processing applications involving analog signal
interface and processing.
The J.1.PD7811 is the mask-ROM high volume production
device embedded with custom customer program. The
J.1.PD7810 is a ROM-less version for prototyping and small
volume production. The J.1.PD78PG11 E is a piggy-back
EPROM version for design development.
Features
NMOS silicon gate technology requiring + 5V supply
Complete single-chip microcomputer
- 16-bit ALU
- 4K-ROM
- 256-byte RAM
0441/0 lines
Two zero-cross detect inputs
Two 8-bit timers
Multifunction 16-bit timer/event counter
Expansion capabilities
- 8085A bus compatible
- 60K-byte external memory address range
8-channel, 8-bit A/D converter
- Auto scan
- Channel select
Full duplex USART
- Synchronous and asynchronous
153 instruction set
- 16-bit arithmetic, multiply and divide
1J.1.s instruction cycle time (12MHz operation)
Prioritized interrupt structure
- 2 external
- 4 internal
Standby function
On-Chip clock generator
64-quil package
J,LPD781 01 J,LPD7811
HIGH-END SINGLE-CHIP
8-BIT MICROCOMPUTER
WITH AID CONVERTER
Pin Configuration
PA,
PA,
PA,
PA,
PA,
PA,
Vee
Voo
DB,
DB,
DB,
DB,
DB,
DB,
DB,
DB,
PA,;
PA,
PB,
PB,
PB,
PB,
PB,
PB,
PB,
PB,
PF,
PF,
PF,
PF,
PF,
PF,
PF,
PF,
ALE
pc,
pc,
pc,
pc,
pc,
pc,
pc,
pc,
WR
lID
AVec
VAREF
AN,
AN,
AN,
AN,
AN,
AN,
AN,
AN,
NMI
INT1
MODE1
RESET
MODEO
X,
X,
V's
o
o
AVss
Pin Identification
PIn
o
o
o
o
No.
Symllol
1-8
PA,;-PAr
Function
Port A: (Three·S1ate InpuVoutpul) a·btI
programmable 110 port. Each line Independently
programmable.s an Input or output. Reset places all
lines of Port A in input mode
9-16
PBo-PB,
Port B: (Th_atelnpuVoulpul) B-bll
programmable 110 port Each line Independently
programmable 88 an input or output. Reset places all
hnas of Port B In input mode.
o
17
PC,
PorI C: (Th....state
hnsm" Data (TxO):
input/output) 8-brt
58rlal data output
programmable 110 port.
termtnal.
---,-----------,,-------~each line Independently ---=Reoa-,-ve--=Data:-:-----
o
o
o
o
terminal.
Input or output.
--,--------,,--------A1ternstlvely. Port C may -:--=-=-:----19
PC,
be used 88 control linea
serial Clock
for USART and Ilmer.
(SCK): SerIal clock
Reset puts Port C In Port Input/output termmal.
mode and all llnel In
When Internal clock IS
18
PC,
programmable 8S an
Input mode.
20
PC,
o
o
o
(RxO): Serial data Input
used, the output can
be elected; when an
external clock Is used,
the Input can be selected.
Timer Input (TI)/Interrupt
request Input (INT,):
Timer clock mput
terminal; can also be
used as fallmg edge,
maskable-Interrupt Input
terminal and AC Input
zero-cross detection
terminal.
Tlmer Outpul (TO): ThIs
output IlgnallS a square
wave whose frequency IS
determined by the
timer/counter.
22
PC,
Counter Inpul (CI):
External pulse Input
tennlnal to the tlmerl
event counter.
23-24
Pc.. PC,
Counter Outputs 0, 1
(CO.-CO,): Program·
mabla rectangular wave
output tennlnal baaed on
timer/event counter.
4-51
II
/-LPD7810/7811
Pin Identification (Cont.)
Pin
Pin
Function
Function
No.
Sy-mbol
Failing-edge, nonmaskable interrupt (NMI) input.
44
RD
INTl
This signal is a nsing-edge, maskable Interrupt Input
This mput is also used to make the zero-cross
detection AC Input.
(Three-state output, active low) Ro IS used as a
strobe to Q!!e data from external devices onto the
data bus. RD goes high during Reset.
45
WR
MODEl
Used as input in conjunction with MOOEO to select
appropriate memory expansion mode. Also outputs
M1 Signal during each opcode fetch.
(Three-state output, active low) WR, when active,
indicates that the data bus holds valid data. Used
as a strobe ~al for external memory or I/O write
operations. WR goes high during Reset.
46
ALE
The strobe signal is for latchmg the address signal
to the output from Por-PDo when accessing external
expanSion memory.
47-54
PFo-PFr
Port F: (Three-state
Input/output) S-blt
programmable 110 port.
Each hne conftgurable
independently as an
Input or output
Address Bus: When
external expansion
memory is used,
multiplexed address/data
bus can be selected.
55-62
oBo-DB 7
Port 0: S-blt
programmable 110 port.
This byte can be
designated as either
input or output.
Address Bus: When
external expansion
memory IS used,
multiplexed address/data
bus can be selected.
63
Voo
Vcc
No.
Symbol
25
NMI
26
27
28
RESET
(Input, active low). RESET Initializes the fJ.-PD7811.
29
MODEO
Used as input In conjunction with MODEl to select
appropriate memory expanSion mode. Also used to
30-31
X2,X 1
(crystal)
ouputlO/M.
This IS a crystal connection term mal for system
clock oscillation. When an external clock IS supplied
Xl is the Input.
32
Vss
33
AVss
AID converter power supply ground potential. Sets
conversion range lower limit.
34-41
ANo-AN r
Eight analog Inputs to the AID converter. AN r -AN 4
can also be used as a digital Input port for failing
edge detection.
42
VAREF
Reference voltage for A/o converter. Sets conversion
range upper limit.
43
AVcc
Power supply voltage for AID converter.
Power supply ground potential.
64
ThiS IS a backup power terminal for on-chip RAM.
+ 5V power supply.
Not•• : 1 clock cycle = 1 CL = 3/f
1 machine cycle = 3 or 4 clock cycles
1 InstructIOn cycle = 1 to 19 machine cycles
f System clock frequency (MHz)
Block Diagram
X1~
OSC
X2
PC
SP
12
,.
EA
pel/hD
PC1/RxD
PC2/SCK
Program
Memory
(8K-Byte)
NMI
Data
Memory
(256-BYTE)
INn
PC3/TI/INT2
PC4/TO
PC5/C1
PCB/COO
",,_-'==-?"1
v-----. ____
pe7/COl
AN7-0
VAREF
AVCC
/WSS
~--,,_ _ _ _-,
Insl
Decoder
11
Vee
4-52
Vss
,...,PD7810n811
Functional Index
Memory map
The j..LPD7811 can directly address up to 64K-bytes
of memory. Except for the on-chip ROM(O-4095) and
RAM(65280-65535), any memory location can be used
as ROM or RAM. The following memory map defines
the 0-64K-byte memory space for the j..LPD7811.
Memory Map
Reset/Standby Release
IROO
Internal ROM
4,096 Bytes x B
IROl
OFFFH
1000H
External
Memory
61.184 Byles x 8
10H
IR02
18H
IR03
20H
IRQ4
28H
IROS
II
FEFFH
FFOOH
Internal RAM
256 BytesxB
FFFFH
60HI
80H
Call Table
SoftlNT
I
}=O
LowADRS
81H
High ADRS
82H
LowADRS
83H
High ADRS
}=1
'-
BEH
Low AORS
}
A-=O"'RS::-----;
BFH f-----,H:-,g7h-:
COH
User's Area
OFFFH
4-53
t
= 31
ILPD781 0/7811
Input/Output
Memory Expansion
8 Analog Input Lines
44 Digital I/O Lines: five 8-bit ports (Port A, Port S, Port C,
Port D, Port F) and 4 input lines (AN 4 -AN 7)
1. Analog Input Lines
ANo-AN7 are configured as analog input lines for onchip ND converter.
2. Port Operation
- Port A, Port S, Port C, Port F
Each line of these ports can be individually
programmed as an input or as an output. When
used as I/O ports, all have latched outputs, highimpedance inputs.
-Port D
Port D can be programmed as a byte input or a
byte output.
-AN 4 -AN 7
The high-order analog input lines, AN 4 -AN 7 can be
used as digital input lines for falling edge detection.
3. Control Lines
Under software control, each line of Port C can be
configured individually to provide control lines for
serial interface, timer and timer/counter.
4. Memory Expansion
In addition to the single-chip operation mode
fJ.PD7811 has 4 memory expansion modes. Under
software control, Port D can provide multiplexed
low-order address and data bus and Port F can provide high-order address bus. The relation between
memory expansion modes and the pin configurations
of Port D and Port F is shown in the table that follows.
Port Configuration
None
PortO
PortF
256 Bytes
PortO
=-~~_.~~~~_ PortF
4K Bytes
Port 0
I/O Port
110 Port
Multiplexed Address/Data Bus
1/0 Port
Multiplexed Address/Data Bus
Port Fo-Fa Address Bus
_!,~~t F4-F7.-:-:yO--:P::-o-:-rt----:~:___=__~~~16K Bytes
Port D
Multiplexed Address/Data Bus
Port Fo-Fs Address Bus
Port F6 -f7 110 Port
60K Bytes
PortO
PortF
Multiplexed Address/Data Bus
Address Bus
Timers
The timer/event counter consists of two 8-bit timers. The
timers may be programmed independently or may be cascaded and used as a 16-bit timer. The timer can be set in
software to increment at intervals of 4 machine cycles
(1fJ.s at 12MHz operation) or 128 machine cycles (32fJ.s
at 12MHz), or to increment on receipt of a pulse at T 1 .
Timer/Event Counter
The 16-bit multifunctional timer/event counter can be used
for the following operations:
Interval timer
External event timer
Frequency measurement
Pulse width measurement
Programmable square-wave output
Timer Block Diagram
r - - -Timer 0
,-- -
-
-
Timer 1
- -
-
--l
Timer/Event
Counter
Senal
Interface
I
I
I
i INTT,
I
I
____ J
Internal Bus
= 3Jf (250n8 12MHz operatIon)
f System clock frequency (MHz)
Notes; 1 CL
4-54
J.LPD7810n811
Block Diagram for Timer/Event Counter
Output
Control
4CL~~~~~--,
PC,ICI
o-~r-~~~~~~+------j
To
r-~~-CP,
CPo
CPo
CP,
INTEO
Interrupt
Control
EIN
f-~~~~~~~~~~~~~--4~~~~~EIN
=
Notes: CL 3/t (250n5 12 MHz operation)
f System clock frequency (MHz)
AID Converter Block Diagram
8·Bit AID Converter
8 Input Channels
4 Conversion Result Registers
2 Powerful Operation Modes
Auto Scan Mode
Channel Select Mode
Successive Approximation Technique
Absolute Accuracy
± 1.5 LSB (± 0.6%)
Conversion Range
0 rv 5V
Conversion Time
50 lis
Interrupt Generation
AVec
AVss
VAREF
ANO
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Analog/Digital Converter
The j.LPD781 017811 features an 8-bit, high-speed, high
accuracy AID converter. The AID converter comprises a
256-Resistor Ladder and Successive Approximation Register (SAR). There are four conversion result registers
(CR o -CR 3 ). The 8-channel analog input may be operated
in either of two modes. In the select mode, the conversion
value of one analog input is sequentially stored in CR o-CR 3 .
In the scan mode, the upper four channels or the lower four
channels may be specified. Then those four channels will
be consecutively selected and the conversion results
stored sequentially in the four conversion result registers.
4-55
~
c
C;
~
m
x
m
Jl
INTE1
INTEIN
II
f.LPD781017811
Interrupt Structure
There are 11 interrupt sources. Three are external interrupts
and 8 are internal. These 11 interrupt sources are divided
into 6 priority levels as shown in the table below.
Universal Serlal Interface Block Diagram
Interrupt
Request
Interrupt
Type of Interrupt
NMI (Non-maskable Interrupt)
IROO
INTTO (Coincidence signal from timer 0)
IROI
INTTI (Coincidence signal from timer I)
IR02
16
IR03
24
INTI (Maskable interrupt)
INT2 (Maskable interrupt)
INTEO (Coincidence signal from timerl
event counter)
INTEl (Coincidence signal from timerl
event counter)
IR04
32
IROS
40
INTEIN (Failing signal of CI and TO
counter)
INTAD (AID converter interrupt)
INTSR (Serial receive interrupt)
INST (Serial send interrupt)
Internal
Zero·crossing Detector
The INT1 and INT2 terminals (used common to TI and PC 3 )
can be used to detect the zero-crossing point of slow moving AC Signals. When driven directly, these pins respond as
a normal digital input.
To utilize the zero-cross detection mode, an AC signal of
approximately 1-3V AC peak-to-peak magnitude and a
maximum frequency of 1kHz is coupled through an external
capacitor to these pins.
For the INTI pin, the internal digital state is sensed as a
zero until the rising edge crosses the DC average level,
when it becomes a one and INT1 interrupt is generated.
For the INT2 pin, the state is sensed as a one until the failing edge crosses the DC average level, when it becomes
a zero and INT2 interrupt is generated.
The zero-cross detection capability allows the user to make
the 50-60Hz power signal the basis for system timing and
to control voltage phase sensitive devices.
NMI
INTTa
INTT1
INT1
iNf2
INTEO
INTEl
INTEIN
INTAD
INTSR
INTST
ov
EA
SB
AN7·AN4
Zero-crossing Detection Circuit
Standby Function
The I-LPD781017811 offers a standby function that
allows the user to save up to 32 bytes of RAM with backup power (VDD) if the main power (Ved fails. On powerup
the I-LPD7811 checks whether recovery was made from
standby mode or from cold start.
c
Universal Serial Interface
The serial interface can operate in any of three
modes: synchronous, asynchronous, and 1/0 interface.
The 1/0 interface mode transfers data MSB first for ease
of communication with certain peripheral devices. Synchronous and asynchronous modes transfer data LSB first.
Synchronous operation offers two modes of data reception.
In the search mode, data is transferred one bit at a time
from serial register to receive buffer. This allows a software
search for a sync character. In the nonsearch mode, data
transfer from serial register to transmit buffer occurs 8 bits
at a time.
4-56
I-LPD781017811
Operand FormatlDescription
Format
r
r1
r2
sr
sr1
sr2
sr3
sr4
rp
rp1
rp2
rp3
rpa
rpa1
rpa2
rpa3
wa
word
bY.te
bit
Irf
Description
V,A,B,C,D,E,H,L
EAH,EAL,B,C,D,E,H,L
A,B,C
PA, PB, PC, PD,PF, MKH MKL, ANM, SMH, SML, EOM, ETMM, TMM, MM,MCC, MA, MB, MC MF, TXB, TMO, TM1
PA, PB, PC, PO, PF, MKH, MKL, ANM, SMH, EOM, TMM, RXB, CRO, CR1, CR2, CR3
PA, PB, PC, PO, PF, MKH, MKL, ANM, SMH, EOM, TMM
ETMO,ETM1
ECNT, ECPT
SP, B, D,H
V,B,D,H,EA
Sp, B, 0, H, EA
B,D,H
B, 0, H, 0+, H+, 0-, HB,D,H
B, 0, H, 0+, H+, 0-, H-, 0+ byte, H+A, H+B, H+EA, H+byte
0, H, 0+, H+ +, 0+ byte, H+A, H+B, H+EA, H+byte
8-bit immediate data
16-blt immediate data
8-bit immediate data
3-bit immediate data
CY,HC,Z
FNMI, FTO, FT1, F1, F2, FEO, FE1, FEIN, FAD, FSR, FST, ER, OV, AN4, AN5, AN6, AN7, SB
Remarks
1. sr-sr4(specla' register)
PA
-PortA
PB
= Port B
PC
= Port C
PO
= Port 0
PF
= Port F
Mode A
MA
MB
=ModeB
MC
=ModeC
MCC = Mode Control C
MF
=ModeF
MM
= Memory Mapping
TMO = nmer Register 0
TM1 = nmer Register 1
TMM = nmer Mode
ETMO = nmer/Event
Counter Register 0
ETM1 = nmer/Event
Counter Register 1
=
3. rpa-rpa3(rp addressing)
ECNT - TimerlEvent
Counter Upcounter
ECPT = Timer/Event
Counter capture
ETMM = Timer/Event
Counter Mode
EOM = Timer/Event
Counter Output Mode
ANM = AID Channel Mode
CRO = AID Conversion
to
Result 0-3
CR3
TXB = Tx Buffer
RXB = Rx Buffer
SMH = Serial Mode High
SML = Serial Mode Low
MKH = Mask High
MKL = Mask Low
2. rp-rp3(register pair)
SP = Stack Pointer
B = BC
o = DE
H = HL
V =VA
EA = Extended Accumulator
L ~!~:I)+
H+
0H-
= (HL +
(DE= (HL)-
=
4. f (nag)
CY = Carry
5. Irf (interrupt nag)
FNMI
INTFNMI
FTO
INTFTO
FT1
INTFT1
F1
INTF1
F2
INTF2
FEO
INTFEO
FE1
INTFE1
FEIN
INTFEIN
FAD
INTFAD
4-57
(DE) + +
(HL) + +
(DE + bre)
(HL + A
(HL + B)
HL + EA)
HL + byte)
0++
H++
0+ byte
H+A
H+B
H + EA
H + byte
!
HC = Half carry
FSR
FST
ER
OV
AN4
to
AN7
SB
=
=
=
=
=
Z = Zero
INTFSR
INTFST
Error
Overflow
Analog Input 4-7
= Standby
II
J,LPD7810n811
Instruction Groups
I·bit Date Transfe,
OPeode
Mnemonic
Op.,.nd
(word), r
r,byte
01101 R2R,R o
or2, byte
wo, byte
01100100
01110001
rpal,byte
W8
010010A,Ao
01100011
00000001
rpl2
AsO 11 1 A,A,Ao
A,rl
MOV
81
00011 T2T,To
00001T2T,To
01001101
01001100
01110000
01110000
r1.A
.r,A
A, or1
r,(word)
13
82
84
r1~A
A_r1
1 1 0 S,S,s"s,So
11 S,S,SoS,S,So
01101 A,A,An
01111 A,A,An
Dots
Low Adrs
High Adrs
Low Adrs
High Adrs
10
10
17
17
7
STAW
LOAW
STAX
LDAX
sr_A
A-sr1
r_(word)
(word)~r
r-byte
String skip, other r
MYI
MYIW
MVIX
wa
rpa2
AsO 1 01 AsA1Ao
Skip
Condition
Op.atlon
State
SoO 0 0 0 s"S,So
DIIseI
Osta
0IIse1
DIIseI
Osta
l'
13
10
Data
= A or L
sr2 -byte
(V, wa) ~ byte
(rpal) ~ byte
(V,wa)~A
Data*(j)
10
10
7113
(rpa2}_A
Data*(D
7/13
A_{rpa2)
A~(V,wa)
B_B',C_C',D_9'
EX)(
01001000
10101111
E_E',H_H',L_L'
EXA
01001000
01001000
10101100
10101110
V,A-V',A',EA-EA'
EXH
H,L_H',L'
iI-bit Data TNn."r
BLOCK
DMOV
SBCD
SDED
SHLD
SSPD
STEAX
LBCD
LOED
LHLD
LSPD
LOEAX
1
~(HL)+,C~C
00010000
00010001
rp3, EA
EA, rp3
01'3, EA
EA, or4
101101 P,P,
rp3 L +- EAL, rp3 H +- EAH
101001P1PO
01001000
EAL +- rp3 L• EAH +- rp3 H
I
(word)
(word)
(WOrd)
(word)
01110000
rp03
word
01001000
01110000
I
I
l
word
word
13
(C + 1)
13
(C + 1)
(DE) +
0+
0-
1101001 U,
110000V1VO
00011110
00101110
00111110
00001110
1001 C,C.C,C,
00011111
LowAdr.
High Adrs
I
I
l
00101111
00111111
00001111
(word) ~ C, (word + 1) ~ B
20
(word) +- E, (word
20
(wore!) +- L, (WOrd
EA_sr4
+ 1) +- 0
+ 1) +- H
(worcl)-SPL.(word
+ 1)-SPH
(rpa3) ~ EAL, (rpa3 + 1) ~ EAH
20
C_(word~B_(word+
20
E-(worcl), D-(word
20
14120
01001000
PUSH
rpl
101100,0,0,
13
POP
rpl
10100Q2Q,QO
10
LXI
rp2, word
o P,P,PoD 100
HIgh Byte
End If borrow
20
20
Low Byte
- 1
sr3_EA
word
rpa3
1 OOOC8~C,CO
~(HL)-, C~C
1.
1.
20
14120
Dots '®
End If borrow
(DE) -
10
1)
+ 1)
L +- (word), H +- (word + 1)
SP L _(word), SPH-(word
+ 1)
EAL -(rpa3), EAH _(rpa3 + 1)
(SP -1)-rpl H-(8P SP~8P - 2
2)~rplL
rplL ~(SP~rplH~(SP + 1)
SP_SP+2
rp2_(word)
String skip when rp2 = H
8-blt A,Hhmetlc (Reglate,)
TABLE
ADD
ADC
ADDNC
SUB
SBB
SUBNB
ANA
ORA
XRA
GTA
A,r
r,A
A,r
r,A
A,r
r,A
A,r
r,A
A,r
r,A
A,r
r,A
A,r
r,A
A,r
r,A
A,r
r,A
A,r
r,A
01001000
10101000
01100000
11000R,A,A,
01000R2R,R o
11010R2R,R o
01010R2R,R o
10100R2R,R o
00100R2R,R o
17
8
8
8
8
8
11100A,A,An
01100A,A,An
11110R2R,R o
01110R2R,R o
10110R2R,R o
8
8
8
00110R2R,R o
10001 R:tR,Ro
00001 R2R,R o
10011A,A,An
00011 R2R,R o
10010R,A,An
00010A,A,An
10101 R,A,An
00101 R2R,R o
4-58
C~(PC
+ 3 + A)
B_(PC+3+A+l)
r_r+A
A-A+r+CY
r_r+A+CY
A_A+r
No Carry
r_r+A
No Carry
A_A-r
r_r-A
A-A-r-CY
8
8
8
8
r_r-A-CY
8
8
8
r-rAA
8
8
8
8
A_AVr
A_A-r
No Borrow
r-r-A
A_AAr
No Borrow
A-AVr
r_rVA
r_rVA
A - r-1
No Borrow
A-I
No Borrow
r
/-LPD781 0/7811
Instruction Groups (Cont.)
a·bit Arithmetic
(~glste'l
(Cont.)
OPCode
Mnemonic
LTA
NEA
Operand
A,
81
01100000
83
82
84
State
10111 A R R
'
,
0
Skip
Condition
Operation
A
Borrow
Borrow
',A
00111 R2 R,R o
8
,- A
A,'
11101 R2 R,R o
8
A -,
No Zero
',A
A, ,
01101R2R,R o
8
,- A
No Zero
11111 R2 R,R o
8
A-,
Zero
',A
8
,- A
Zero
8
AAR
No Zero
8
AAR
Zero
EQA
ONA
A,'
01111 R2R,R o
11001R2R,R o
OFFA
A,'
11011 R2R,R o
S·bit Arithmetic (Memory)
ADDX
,po
ADCX
,po
11010A2A,A o
ADDNCX
'pa
10100A2A,A o
SUBX
11100A2A,A o
SBBX
'pa
,po
SUBNBX
,pa
, 011 0 A,A,1\o
01110000
11
A_A
+ (rpa)
11
A_A
+
+ ('pa)
(rpa)
+ CY
"
A~A
11
A_A - (rpa)
11
A~A
- ('pa) - CY
11
A~A
- ('pa)
- ('pa)
No Carry
-~
11110A2A,A o
--
No Borrow
ANAX
'pa
A~A
'pa
10001 A2A,A o
10011 A2A,A o
11
ORAX
11
A~AV('pa)
XRAX
'pa
10010A2A,A o
11
A~AV('pa)
GTAX
'pa
10101 A2A,A o
11
A - (,pa),- ,
No Borrow
LTAX
'pa
10111 A2A,A o
11
A - ('pa)
Borrow
-_._.
-~
Immediate Data
No Zero
NEAX
11
rpa
11111 A2A,A o
11001A2A,A o
11
A-(rpa}
No Zero
rpa
11011 A2A,A o
11
A+- (rpa)
Zero
EQAX
rpa
ONAX
OFFAX
A, byte
ADI
ACI
SUI
SBI
Zero
_~-=-Da:c:to=-~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _7,-_ _ccA_~-,-~ + byte
~'~b~~e~____~o~'~'~'-O-'O-O------~O~'~O~O.~O~R~,~R,~R~o--------_D~a_'a____________~'~'_____r~r+b~e
5 3 1000525 1 5 0
sr2, byte
01 1 0
A, byte
01010110
-- Data --;.
r,byte
01110100
01010R2R1Ro
0110
5 3 1010525 150
_ _ _ _ _c-_-:sr2, byte
ADINC
01 0001 1 0
A - (rpa)
20
Data
001 001 t 0
01110100
001 00R2R,Ro
sr2, byte
0110
5 3 0 1 0 a 5 25 15 0
A, byte
011 001 1 0
«-
11
20
~ Data --;.
A, byte
r,byte
sr2
~sr2
+ byte
____'_7_ _ _A_~_A + byte + -'C_Y_ _ _ _ _ _ _ __
7
---:Dc-a-'a------~~,-,-·
20
Data -'>
Data
r+--r + byte + CY
sr2_sr2+ byte + CY
A ~ A + b.-'-Yt':-e_ _ _ _ _ _-cN_O Carry __ ~
r ........ r + byte _ _ _ _ _ _ _-,-Nc:0-,Cc::o",rr,-Y_
sr2 _ sr2 + byte
No Carry
7_ _ _ _~~_~~~._."
r_r - byte
11
r,byte
01110100
sr2, byte
0110
A,byte
01110110
~Data-'>
r, byte
0111010 a
01110 R2R1RO
sr2, byte
01 1 0
5 311 1 0525 15 0
11
20
r ...... r ~~. __~:_____._.. __._____ _
sr2 ~ sr2 - byte - CY
A, byte
00 11 011 0
Data
7
A ~ A - byte_ _ _ _ _ _-;:N_OBorrow
20
sr2 ...... sr2 - byte
_ _ ._~ _ _ _
A -::--~-: byte ~ CY
Data
--",-cb'-Ytc-.-:-_ _-:c0-c'-c'~'-0_;'-'-0-'-0---0-'occ'_;'.':-0':-RC',":R-'C,RC"o------------:'cc'---'-c-c-r . - byte _ _ _ _ _ ~N_O_B~~
_ _ _ _ _ _ _-"-5''''2",bo-Y"te'-_--'-O_'_'_'_,-,-0--"1_ _ _-=53011 0 52515=,o~___
20
sr2 ...... sr2 _ byte
__ ~_B_o_rr_ow
__
A,byte
00000111
Data
7
A~A \ byte
SUIN8
ANI
ORI
XRI
r,byte
01110100
00001R2R1Ro
sr2, byte
01100100
5 300015 25 15 0
A,byte
00010111
Data
r, byte
01110100
00011 R2R,Ro
sr2, byte
0110
5 3 0 0 1 1 $25, $0
A, b~e
000' 0110
Data
r, byte
0111 0 1 00
0 a 0 1 0 R2R1RO
011 0 1
00100111
$30 0 1 052$150
Data
sr2 byte
- - - - - - : - - A, ~te
GTI
NEI
Data
sr2 <:-sr~~!!!. __ .. __.__ "_ _ _ _ _ _ ,
A ...... AV byte
11
r
01101
00110111
Data
0 1 110 1 00
0 0 1 1 1 R2R1 Ro
sr5, byte
0110
$30111525,50
A,byte
01100111
~Data_
r, byte
0111010 a
01101 R2R1RO
1
rv_b-cyccte-:-:-_ _ __
_ _ _-'--_ __'_A'-~_'_A'_V'_b,,~"_e _, _ _ _ ,_~__,_ _ _~
__ ~ ____
Da_ta_~~
11
r
1
20
sr2 ~ sr2 11 byte
<-
r V byte
--~~------"--~_-_-_-_-~~~~~_e ~-,~------:No
$3°101525,50 _ _ _ _-'-
A, byte
r, byte
~
20. _____ ----.!r2 ~ sr2 V_;b-'Y'-te'------
Data
sr5, byte
A, byte
EQI
1~ _ _ _'_-~~~~_._
20
---"',"by"te"-----'-o-'-,-'-,'-,O'-,-'O-'O'----O-O-'-O-'-''-R-'-,R-,ccR-o-----D-a-ta------ 11
sr5, byte
LTI
1
Data
r, byte
sr5, byte
4-59
_____!.4_ _ ."
r - byte - 1
Borrow
No Borrow
srS-_b'-y'_e_-_'_ _ _ _ _
No Borrow
7
A - byte
Borrow
11
r - byte
-----;B~orrow
II
f.LPD781 0/7811
Instruction Groups (Cont.)
Immediate Data (Cont.)
OPCode
Mnemonic
Operand
81
01000111
ONI
_ r, byte_____?~~~
sr5,byte
1
0110
83
82
~Data-----
__
<---_O'~ta-._
._ _ _ _ _
"'__
. ___. _ _ '_.
14
____________ ~
Data
No Zero
_sr~~y~~ ___
No Zero
A \ byte
Zero
_ _-'""'---_ _~r-,"\ byte
Zero
._ _ .~_~ ____ ~~_~.y~~ _ _ _ _ _ _ _ _Z_e_ro_ _
~
01 1 0
No Zero
-------~~-----
OFFI
8r5, byte
Skip
Condition
Operation
__0_1__~~~~. _ _ _ _Dl!!~ _ _ _ _ _ _ ~1_ _ _r_~_~x~_
$31001$2$1$0
__ ~~~~ __ .,_~~~_~~ 1
State
84
Working Register
ADDW
wa
01110100
11000000
-'-A=Dc::Cc:W------~w=a------------- --'-'------11 01
A-DD-N-CW-----;,~----
SUBW
Offset
- - -.. -'- - - - - - -
-----1010--t--------- -
wa
1110
14
"---
14
---+------;,-;-;- ---------- ---- .--
SBBW
wa
SUsN~---_;~--'----'--ANAW
----·-·101-1-~~'--'----·'·---
wa
wa
wa
A <---A
~
____ ~'"_~
+ (V,wa)
No Carry
A ::j\l,wa)_
A<---A-(V,wa)
_. ___ .________ _
No Borrow
1-'"4--.--'-A~_--'-A'-__ \-C(:v, W~)., _ _ _ _ _ _ _ _ _ _ _
.1.____
GTAW
~.<-A +"(~~~~_£~
"-A~~(lI.."'al~~
--------14
1 0001 000
_ O_A_A"!.-_ _ _ _.___________ ...:-::-=-___':--_~O 1
XRAW
wa
01110100
10010000
lTAW
14
14
Offset
14
14
A ..- A V (V, w_a)~_ _ __
A<-A¥(V,wa)
---------_._-,,-'""-------
.. _____ .~~_1_~"~~.. _ _ _ _ _ ~~___
.~'"_" __A - (V, wa) -:-: _~ ______ '" ___ ~_!':!:_row_
_______ ~,_~ _ _ _ _ _ _ ~,___
__ _ _ _ _~1~ ____ "~~"~~)_
14
A - (V, wa)
NEAW
1110
Ec:Qcc/l:.ccW,--------w-a-------+--1111
_________ ". _ _ _ "~_4_ "" ~-:: JY~
Borrow
No Zero
______ """"__ . _Z_er_o____
ONIW
wa, byte
0100
OFFIW
wa, byte
0101
- - - ...- - - - - ' " " - -
13
(V, wa) \ byte
16·bit Arithmetic
+ r2
EADD
EA,r2
DADO
EA, rp3
DADC
EA,rp3
11 0 1
DADDNC
EA, rp3__
1010
ESUB
EA,r2
0000
011000R1Ro
11
EA<---EA-r2
DSUB
EA rp3
01110100
111001 P1PO
11
EA<---EA - rp3
11
EA_EA - rp3 - CY
11
EA<---EA - rp3
01110000
010000R 1Ro
11
EA<---EA
0100
110001 P1 PO
11
EA<---EA+rp3
11
EA.(C.-.-EA
11
EA_EA
I
+ rp3
+ rp3
+ CV
No Carry
DSBB
EA, rp3
1111
DSUBNB
EA,rp3
1011
DAN
EA, rp3
100011 P1PO
11
EA<---EA - rp3
DOR
EA,rp3
1001
11
EA_EAVrp3
DXA
EA, rp3
100101P1PO
11
EA<---EAJlrp3
DGT
EA,rp3
101011 P1PO
11
EA-rp3-1
No Borrow
DlT
EA,rp3
1011
11
EA - rp3
Borrow
1
No Borrow
ONE
EA,rp3
1110
11
EA - rp3
No Zero
DEQ
EA, rp3
1111
11
EA - rp3
Zero
DON
EA,rp3
1100
11
EAA rp3
No Zero
DOFF
EA,rp3
11 0 1
11
EAA rp3
Zero
MUl
r2
DIV
r2
Multiply/Divide
01001000
001011 R1Ro
0011
j
32
EA--A x r2
59
EA<--- EA - r2, ~2 <---S~ _ _ _ _ _
16
(V, wa)
Increment/Decrement
INR
r2
010000R t Ro
INAW
wa
00100000
INX
DCA
+1
~
(V, wa)
rp
00 P1POOO 1 0
rp <---rp + 1
EA
10101000
EA<---EA+1
r2
010100R 1Ro
DCAW
DCX
r2 - r2
-Offset-
00110000
4
<---Offset_
16
Carry
r2+-r2-1
Borrow
(V, wa) _ (V, wa) - 1
Borrow
rp
00 P1POO 0 11
rp_rp - 1
EA
10101001
EA~EA
4-60
Carry
+1
-1
J.LPD7810/7811
Instruction Groups (Cont.)
Others
OPCode
Mnemonic
Operand
Skip
82
81
Condition
Operation
State
84
83
0-:1-:1-=0..:0-=0-=0,:-1_ _ _-:-:_-:-:c-:-:c:-:-________________ ~ __~~~ AdJu~.!!ccumula_l_or_ _ _ _ __
01001000
00101011
8
CY-l
DAA
STC
CLC
-~----------------
CMC
--
j
01001000
00101010
CY- 0
CY_CY
--- ----- --10101010
NEGA
00111010
--'---------------'-------'-----'--------
A-A+l
------------------
Rotate and Shift
--------=1 100-;----- ___
RLD
RRO
RLL
01001000
r2
01 001 000
00111000
17
n
001101 R1 RO
RLR
r2
___-+_____ JiO_R_,_R__
Sll
r2
001001R,Ro
r2m-t1 --r2m• r2o---CY,
-~_-_-_-_-_-_-- ~~~ ~:r2m. r2~ ~Cy~-~__-_-____- _-_-_
- -__
- _ _- _
__
O ______
___
----------------t-----!-=OOR-,-Ro----------~-----8-SlR
r2
~
SLLC
r2
000001R,Ro
SLRC
r2
ORLL
EA
Rotate Left. Digit
__ _
r2m+,-r2 m,r2o <-Q,
-~:~~~r2:, ~~.=O,-----------_EY-_~~'L__
8
r2 m+ 1 --r2 m,r2o-0,
Carry
r2m_ 1 <- r2m. r27 _0,
CV- r20
Carry
---------------4-----+--------------------------~~------------
ORLR
EA
DSLL
EA
OSLR
EA
!
00 R,R o
EA,,+1- EAn,EAO-O,
10100100
~~~-----=~------i._-----tt~~~------------~---C=7Y---EA-'~5~~_~_ _ _ _ _ __
i
0000
EA"_,-EA,,.EA15-0.
Jump
JMP
word
JB
01010100
_LowAdrs-->
High Adrs
10
PC -(word)
00100001
JR
word
11-Jdlsp1-
JRE
word
0100111
JEA
-Jdlsp-
10
PC-PC + 1 + Jdlsp1
10
PC-PC + 2 + Idlsp
16
(SP - 1) -(PC + 3) ••
(SP - 2)-(PC + 3k
01001000
00101000
01000000
_LowAdrs_
01001000
00101001
17
(SP - l)_(PC + 2)••
(SP - 2)-(PC + 2k
PC.-B.SP-SP - 2
fa-
13
(SP - l)~(PC + 2) ••
(SP - 2) -(PC + 2k
PC15-11-00001,
PC 1o-o-fa,SP-SP - 2
Call
CALL
word
High Adrs
PC_(word~SP_SP
CALB
- 2
CALF
word
01111_
CALT
word
1aD-ta--
16
SOFTI
01110010
16
RET
10111000
10
PC ~ (SP). PC. - (SP + 1)
SP_SP + 2
+ 1001
10
SP_SP + 2,PC-PC + n
01100010
13
PC, -(SP~ PC. -(SP + 1)
PSW-(SP + 2~SP~SP + 3
(SP - l)~(PC + 1)••
(SP - 2) -(PC + 1),
PC, - (128 + 21a~ PC. (129 + 21a~SP-SP - 2
(SP - 1) _PSW. (SP - 2)_
(PC + l)•• (SP - 3)~(PC + 1),.
PC ~0060H.SP ~SP - 3
Return
RETS
RETI
PC, -(SP~ PCH -(SP + 1)
Unconditional
Skip
Skip
BIT
blt,WB
10
-Offset-
4-61
Bit Test
(V. wa)
bit = 1
II
,..,PD7810/7811
Instruction Groups (Cont.)
CPU Control
OPCode
Mnemonic
Operand
81
Skip
82
83
State
84
Condition
Operation
~~K_ _~_ .___~ ____ "__~ __.__O=-',-,0,-,0,-,1+0c:0c:0,---_ _-=O-=0-=0-=0-,1'-F2: ((Rr)) 0 - 3)),
.r. ~ 0 - 1
CPL C
(e)
Exchange the Accumulator and desig-
nated register's contents
=
0 -,
Exchange Indirect contents of Accumu·
lator and location
In
data memory
Exchange Indirect 4·brt contents of
Accumulator and data memory
FLAGS
NOT (e)
<-
Complement Content of carry bit
CLR C
(C)-O
Clear content of carry bit to 0
ANLD Pp, A
(Ppl <- (Ppl AND (AQ-3)
p '" 4 - 7
designated port (4 - 7).
IN A, Pp
1M
Input data from designated port (1 - 2)
MOVD A, Pp
{A 0 -3J.- (Pp),p
INPUT/OUTPUT
Logical and contents of Accumulator WItt
(P p ), p '" 1 - 2
<-
Into Accumulator
=
4-7
Move contents of designated port (4 - 7)
Into Accumulator
(A 4 - 7) +-0
MOVD Pp , A
iPp) +- A 0 - 3, p = 4 - 7
ORLDPp,A
(Ppl +- (PpJ OR (A 0 - 3)
p=4-7
Logical or contents of Accumulator
With designated port (4 - 7)
OUTL Pp, A
(Ppl
+-
(A), p = 1 - 2
Output contents of Accumulator to
designated port (1 - 2)
INC Rr
(Rr)
+-
(Rr) + 1, r
Increment by 1 contents of deSignated
register
INC@Ar
((Rr)) -((Rr)) + 1,
r = 0-1
Increment Indirect by 1 the contents of
data memory location
CALL addr
i(SPj}
Call desIgnated Subroutine
Move contents of Accumulator to deSIgnated port (4 - 7)
REGISTERS
0-7
SUBROUTINE
<-
(PCI, (PSW 4 - 7)
'10
'7
(SP) .... (SPI + 1
(PC 8 - 10) <- addr 8 -10
(PCO-7J-addrD-7
(PC 11) <- DBF
RET
(SPj +- (SP) - 1
(PC) -- ((SP))
Return from Subroutine Without restorIng Program Status Word
MOVA, T
(AI~(TI
Move contents of TImer/Counter into
Accumulator
MOVT,A
ITI
TIMER/COUNTER
~
(AI
0
Move contents of Accumulator into
TImer/Counter
STOP TCNT
Stop Count for Event Counter
STRT CNT
Start Count for Event Counter
STRT T
Start Count for Timer
NOP
No Operation performed
MISCELLANEOUS
Notes
I
0
CD
InstructIOn Code Oeslgnatlons rand p form the binary representatIon of the RegIsters and Ports involved
@
The dot under the appropriate flag bIt indIcates that Its content IS subject to change by the instructIOn It appears in
@
Numerlcal,Subscnpts appeanng In the FUNCTION column reference the specific bits affected.
® References to tne address and data are speCified in bytes 2 and/or 1 of the Instruction
Symbol DefinitIons
SYMBOL
A
addr
C
DESCRIP'tION
Program Memory Address (12 bIts)
T
T,
Carry Flag
X
ClK
Clock Signal
CNT
Event Counter
D
d,ra
P
SYMBOL
The' Accumulator
DESCRIPTION
TImer
Testable Flag 1
external RAM
PrefiX for Immediate Data
@
Nibble DeSIgnator (4 bits)
$
Number or ExpreSSion (8 bits)
Ixl
''In.Page'' Operation DeSignator
Pp
Port DeSignator (p
R,
Register De'tgnator (r
((xli
1,2 or4 -7)
0,1 or 0 - 7)
~
4-68
PrefiX for Indirect Address
Program Counter's Current Value
Contents of External RA'M Location
Contents of Memory Location Addressed
by the Contents of External RAM Location
Replaced By
IlPD8021
iNSTRUCTION SET
DESCRIPTION
FUNCTION
MNEMONIC
D.
INSTRUCTION CODE
D.
DO
D3
D:!
Dl
DO
0
d7
d6
0
dS
0
dO
0
d3
0
d2
1
dl
dO
0
d7
0
d6
0
d.
1
d,
0
d3
0
d2
dl
dO
0
d7
1
d6
0
d.
d,
0
d3
0
d2
1
dl
dO
d3
0
d2
1
dl
dO
0
d2
dl
dO
'3
'2
'I
8()
'3
0
83
'2
1
'2
'I
0
'I
8()
D7
CYCLES
BYTES
FLAG
C
ACCUMULATOR
ADD A, "data
(AI
+-
(AI + data
Add ImmedIate the speCified Data to the
Accumulator
Add A, Rr
(A)-fA) +(Ar)
for r =0-7
Add contents of designated register to
the Accumulator
ADDA,@Ar
(AI -(AI + HRr!)
for r· 0-1
Add indirect the contents the data
memory location to the Accumulator
AD DC A, .. data
(AI
+-
(A) + Ie) + data
Add Immediate with carry the specified
data to the Accumulator
ADDC A,Ar
{AI
+-
(AI + Ie) + (Ad
Add With carry the contents of the
designated register to the Accumulator
for r =0-7
ADDCA,@Ar
ANL A, '" data
(AI +- (AI + Ie) + ((Rr))
for r'" 0-1
(AI -lAI AND data
1
Add indirect With carry the contents of
dats memory location to the
Accumulator
Logical and specified Immechate Data
With Accumulator
0
ANL A,Ar
lA) - (A) AND lAd
for r = 0-7
Logical and contents of designated
register With Accumulator
ANl A,@Ar
(A)-lA) AND liAr))
for r = 0 - 1
logical and Indirect the contents of data
memory With Accumulator
CPLA
(A)-NOT (A)
Complement the contents of the
Accumulator
ClRA
(A)-O
CLEAA the contents of the Accumulator
DAA
1
1
1
DECIMAL ADJUST the contents of the
Accumulator
DECA
IAI-IAI-l
DECAEMENT by 1 the Accumulator's
contents
INCA
(A)-IA) +1
Increment by 1 the Accumulator's
contents
OAL A," data
lA) - lAI OA data
logical OA specified Immediate data
With Accumulator
ORlA, Ar
(A) .... (AI OA IRr)
for r =0-7
logical OA contents of designated
register With Accumulator
d7
ORlA@Rr
(A)-IA) OR ((Ar)}
for r:0-1
logical OR Indirect the contents of data
memory location With Accumulator
ALA
(AN +lI-(AN)
IAol-IA71
for N""0-6
Rotate Accumulator left by l·blt With·
out carry
RlCA
(AN + 11- (AN), N = 0-6
'''oI-ICI
(CI- IA7'
Rotate Accumulator left by l-blt through
carry
AAA
(AN)- (AN + 1),N"0-6
IA71-IAOI
Rotate Accumulator nght by l-blt
Without carry
AACA
Rotate Accumulator nght by l·blt
through carry.
SWAP A
IANI-(AN+l),N"'0-6
IA71-ICI
ICI-IAOI
(A4.7) ~ lAO - 3)
XRlA,· data
(A) .... (A) XOR data
logical XOR specified Immediate data
With Accumulator
XRlA, Rr
(A) - (A) XOA (Ad
for r = 0-7
Logical XOA contents of deSignated
register With Accumulator
1
XRLA,@Rr
(A) .... (A) XOR ((Rd)
for r· 0-1
loglcel XOA Indirect the contents of data
memory location With Accumulator
1
Swap the 24·blt nibbles
Accumulator
In
1
d6
d.
d,
0
0
0
dS
d,
d3
1
1
1
the
d7
1
d6
BRANCH
DJNZ Ar, addr
(Ar) -lAd -l,r - 0-7
If(Ari+O
(PC 0-7) -addr
Decrement the specified register and
test contents
JCaddr
(PC 0 - 7)- addr If C = 1
(PC) - (PC) + 2 If C - 0
Jump to specified address If carry flag
IS set
JMP addr
(PC 8 - 101- addr 8 - 10
(PCO -7) .... addrO-7
(PC11l-DBF
Direct Jump to specIfied address Within
the 2K address block
JMPP@A
IPCO-71-((AII
Jump indIrect to specIfIed addl'ftS With
address page
JNCaddr
(PC 0- 7) .... addr If C - 0
(PC)+-(PC)+2,fC=1
Jump to specifIed address If carry flag IS
JNT1 addr
(PCO-7)-addrlfT1 =0
(PC) .... (PC) +2 IfTl = 1
Jump to specifIed address If Test 1 IS low
(PC 0-7) -addr If A- 0
(PC) - (PC)+ 21f A"O
Jump to specifIed address If
Accumulator IS non·zero
JTF addr
IPCO-7)-addrlfTF-l
(PC) - (PC) + 21f TF = 0
Jump to speCifIed address If Timer Flag
IS set to 1
JT1l1ddr
(PCO-7)-addrlfT1 "'1
(PCI +-(PCI + 21fT1 ~O
Jump to sp8Clfted add,... If Test 1
JZaddr
(PCO-71-addrlfA-=O
(PC) +- (PC) + 21fA-0
Jump to specified address If Accumulator
JNZaddr
low
I'. 1
~o.
4-69
1
'7
as
1
'7
810
87
as
'9
as
'. .'.
.
's
'S
0
8•
0
'0
0
.. ....
1
'7
0
'7
1
'7
0
87
as
1
'6
8•
0
0
1
as
'
0
'
1
as
0
8•
0
8•
0
1
0
87
1
as
'7
1
'6
'
83
0
'3
0
'3
0
'3
0
..
. ... ....
0
82
1
'2
1
'2
1
'2
1
'2
1
82
'I
1
81
1
'I
1
'I
1
'I
1
'I
ao
ao
0
ao
ao
0
ao
0
ao
II
IlPD8021
Package Outlines
For information, see Package Outline Section 7.
Plaslic, fLPD8021C
Cerdip, fLPD8021D
4-70
8021 DS-REV2-1-82-CAT
NEe
"PD8041A
"PD8741A
UNIVERSAL PROGRAMMABLE PERIPHERAL
INTERFACE - 8-BIT MICROCOMPUTER
DESCRIPTION
FEATURES
The ).LPDS041A/S741A is a programmable peripheral interface intended for use
in a wide range of microprocessor systems. Functioning as a totally self·sufficient
controller, the ).LPDS041A/S741A contains an S·bit CPU, 1 K x S program
memory, 64 x S data memory, I/O lines, counter/timer, and clock generator in a
40·pin DIP. The bus structure, data registers, and status register enable easy interface
to S04S, SOSOA or SOS5A based systems. The ).LPDS041 A's program memory is factory mask programmed, while the ).LPDS741 A's program memory is UV EPROM to
enable user flexibility.
• Fully Compatible with S04S, SOSOA, SOS5A and SOS6 Bus Structure
• S-Bit CPU with 1 K x a ROM, 64 x a RAM, S-Bit Timer/Counter,
1B I/O Lines
• a-Bit Status and Two Data Registers for Asynchronous Siave-to-Master
Interface
• Interchangeable EPROM and ROM Versions
• Interrupt, DMA or Polled Operation
• Expandable I/O
• 4O-Pin Plastic or Cerdip DIP Package
• Single +5V Supply
PIN CONFIGURATION
Vee
T,
TO
x,
P27/i5A'Ci<
X2
RESET
P26/0RQ
55
CS
P25/'i'BF
P24/0BF
P17
EA
RO
AO
WR
).LPD
a041A/
8741A
SYNC
DO
0,
P'6
P15
P14
P13
P12
Pll
P,O
02
03
04
05
06
07
VSS
VOO
PAOG
P23
P22
P21
P20
Rev/3
4-71
II
",PD8041 A/8741 A
PIN IDENTIFICATION
PIN
NO
SYMBOL
FUNCTION
1,39
TO Tl
Testable input pins using conditional transfer instructions
JTO, JNTO, JT1, JNT1. T 1 can be made the countllr/timer
input using the STRT CNT instruction. The PROM pro·
gramming and verification on the IlPD8741 A uses TO.
2
Xl
One side of the crystal input for external oscillator or
frequency source.
3
X2
The other side of the crystal input.
4
RESET"
5
SS
Active·low input for processor initialization. RESri is also
used for PROM programming, verification, and power down.
Single Step input (active·low). SS together with SYNC out·
put allows the IlPD8741 A to "single·step" through each
instruction in program memory.
6
CS
7
EA
8
RD
Read strobe input (active·low). RD will pulse low when the
master processor reads data and status words from the DATA
BUS BUFFER or Status Register.
9
AO
Address input which the master processor uses to indicate if
a byte transfer is a command or data.
10
WR
Write strobe Input (active·low). WR will pulse low when the
master processor writes data or status words to the DATA
BUS BUFFER or Status Register.
11
SYNC
The SYNC output pulses once for each IlPD8041 A/8741 A
Instruction cycle. It can function as a strobe for external
circuitry. SYNC can also be used together with SS to
"single·step" through each instruction in program memory.
12·19 00.07 BUS
20
VSS
21·24, P20· P27
35·38
Chip Select input (active·low). CS IS u'sed to select the
appropriate IlPD8041A/8741 A on a common data bus.
External Access input (active·hlgh). A logic "1" at this input
commands the IlPD8041 A/8741 A to perform all program
memory fetches from external memory.
The 8·bit, bi·directional, tri·state DATA BUS BUFFER lines
by which the IlP08041A/8741A interfaces to the 8·bit
master system data bus.
Processor's ground potential.
PORT 2 is the second of two 8·bit, quasi·bi·directional I/O
ports. P20,P23 contain the four most significant bits of the
program counter during external memory fetches. P20,P23
also serve as a 4·bit I/O bus for the IlPD8243, INPUT/
OUTPUT EXPANDER. P24-P27 can be used as port lines or
can provide Interrupt Request (IBF and OBF) and DMA
handshake lines (DRQ and DACK).
25
PROG
Program Pulse. PROG is used in programming the IlPD8741 A.
It is also used as an output strobe for the J.[PD8243.
26
VDD
VDD is the programming supply voltage for programming
the IlPD8741A. It is +5V for normal operation of the
IlPD8041A/8741A. VDD is also the Low Power Standby
input for the ROM version.
27·34 PlO,P17
PORT 1 is the first of two 8-bit quasi-bi-directional I/O ports.
40
Primary power supply. VCC must be +5V for programming
and operation of the IlPD8741 A and for the operation of the
IlPD8041A.
VCC
4-72
,..PD8041 Al8741 A
FUNCTIONAL
DESCRIPTION
The /JPDS041 A/S741 A is a programmable peripheral controller intended for use
in master/slave configurations with S04S, SOSOA, SOS5A, SOS6 - as well as most
other S-bit and 16-bit microprocessors_ The' /JPDS041A/S741A functions as a
totally self-sufficient controller with its own program and data memory to effectively
unburden the master CPU from I/O handling and peripheral control functions. The
/JPDS041A/S741 A is an intelligent peripheral device which connects directly to the
master processor bus to perform control tasks wh ich off load main system processing
and more efficiently distribute processing functions.
/JPD8041 A/8741 A
FUNCTIONAL
ENHANCEMENTS
The IlPDS041A/S741 A features several functional enhancements to the earlier
/JPDS041 part. These enhancements enable easier master/slave interface and increased
functionality .
1. Two Data Bus Buffers. Separate Input and Output data bus buffers have been
provided to enable smoother data flow to and from master processors.
INPUT DATA
BUS BUFFER
(8)
II
OUTPUT DATA
BUS BUFFER
(8)
2. S-Bit Status Register. Four user-definable status bits, ST 4-ST7, have been
added to the status register. ST 4-ST7 bits are defined with the MOV STS, A
instruction which moves accumulator bits 4-7 to bits 4-7 of the status register.
ST O-ST 3 bits are not affected.
STs
DS
FO
D3
IBF
OBF
D1
DO
MOV STS, A Instruction OP Code 90H
3. RD and WR inputs are edge-sensitive. Status bits IBF, OBF, F1 and FO are
affected on the trailing edge at RD or WR.
RDOrWR~"...____________________~~
p_ Flags affected
4-73
",PD8041 AJ8741 A
4. P24 and P25 can be used as either port lines or Buffer Status Flag pins. This
feature allows the user to make OBF and IBF status available externally to
interrupt the master processor. Upon execution of the EN Flags instruction,
P24 becomes the OBF pin. When a "1" is written to P24, the OBF pin is
enabled and the status of OBF is output. A "0" written to P24 disables the
OBF pin and the pin remains low. This pin indicates valid data is available from
the ~PD8041 A/B741 A. EN Flags instruction execution also enables P25 indio
cate that the ~PD8041 Al8741 A is ready to accept data. A "1" written to P25
enables the IBF pin and the status of IBF is available on P25. A "0" written to
P25 disables the IBF pin. If OBF is not true, the data at the databus is invalid.
~PD8041A/8741A
FUNCTIONAL
ENHANCEMENTS (CaNT.)
EN Flags Instruction Op code - F5H.
5. P26 and P27 can be used as either port lines or· DMA handshake lines to allow
DMA interface. The EN DMA instruction enables P26 and P27 to be used as
ORO (DMA Request) and i5AcK (DMA acknowledge) respectively. When a
"1" is written to P26, ORO is activated and a DMA request is issued. Deactivation of ORO is accomplished by the execution of the EN DMA instruction,
6ACK anded with RD, or i5ACK anded with WR. When EN DMA has been
executed, P27 (om) functions as a chip select input for the Data Bus
Buffer registers during DMA transfers.
EN DMA Instruction Op Code - E5H.
BLOCK DIAGRAM
MASTEA SYSTEM INTERF ACE
CRVST 4l, LC, OR CLOCr:
~
It,
X,
IiOl'r I'ROG
II IYfifC EA
=T
-t .....
j-.:.:ST:;;"':;;.K_ _
lIDIa'
IIIIEQISTlIlllItANKO
DAT......MOAY
VOO_I'ROGRAMPOWE.. ...,..V
I'OWIlfil {
vee _
+IY ......V
V. _GIIOUND
4-74
... .
",PD8041 A/8741 A
ABSOLUTE MAXIMUM
RATINGS·
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . oOe to +700e
Storage Temperature (Ceramic Package) . . . . . . . . . . . . . . . .. -65°C to +150o e
Storage Temperature (Plastic Package). . . . . . . . . . . . . . . . . .. -65°C to+150°C
Voltage on Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 to +7 Volts <'r"RT-
~--~'AA--I
U
f--A0--1
tAO~
J<
=r
TIMING WAVEFORMS
.
~
j.--t=_'A._ _ _ _.....~
'A'
~'~'
READ CONTROL
--------~---
IAI- IAI XOR IRr!
fa, • ' 0 - ?
LogH;" XOA conlents of ~s,gnated
reg,Utf ...... th Accumulato.
XRl A (jl Ar
IAI· IAI XOA HRrll
10f' • 0 - I
Log,ul XOR Ind"ecl t"e content. of data
memory local'ol'l ...... Ih AccumulatOt
OJNl A, add.
~ 7
(Rd +- (Rd-f, r
If (Rr) *0
(pea - 7) +-addr
(PC 0 - 7) +- addr If Bb '" 1
(PClof- (PC) + 2 ,f Bb = 0
(PC 0 - 7) <-- addr If C = 1
(PC) <-- (PC) + 2 If C " 0
(PC 0 • 7) <-- addr If FO = 1
(PC) -- (PC) + 21t FO = 0
JC..od.
JFO add>'
JFI met.
-..
JMP-'d.
--
MIlIF addr
o
0
IPCO- 71·-otddr IfFl-1
(PCI- fPCI. 2.fFl "0
Decrement the lPl'C.j,ed .tgISle. and
Jump TO spec.hed addteu ,I
ACCumul.lO< b.T " HT
Jumo to speclf.ed «kIteU ,f c."y
Jump to !IP«,f,ed .dd,", .f
F'~
.,
.,b,
II~
FO ,.
.,
Jump to q»ec.f,ed add.en .1 F •• g F I IS
(PC 8 - 10) <- addr 8 - 10
(PC 0 -7) -addrO_7
(PC
--OBF
(PC 0 _ 7) +- ((An
O"Kt Jump to $I)«,foed . t t U wlth,n
th, 2K add.ess block
IPCO-7}-Md'IIC .. O
IPCI-IPCI.2"C~ 1
Jump to lP«.f,ed addrHl If car,y fl .. "
IPC 0 - 71 - add< " ISF =
(Pel-IPCI. 2,t 18F ~ 1
Jump to IPI'Clhtd
lull II.. "low
fPCO-71-addrl'OBF- t
fPCI - IPCI + 2 ,t oaF" 0
Jump to tPeClf.-d addr_ ,I output
n)
'7
10
"
Jump ,ndorectlO $JIec,I.,d add"s$ w.th
w.th Idd"n page
,-
,
,
,
.,
.,, "
"
., .,, .,
.,
, ,
., .,, ., .,, .,
., " .,
.,
, , "
.,
,
" , "
.,
'6
b,
"
"
'0
'0
'6
'0
'6
0
'6
'0
0
.... . ..
'6
"
"
.., .
.. .
.. .
1
add,", ,f Input buffet" "
buffet"tullfl. . . sel
dO
,
BRANCH
J8biildd,
d6
(AN)<--(AN+1},N=O-6 Ro""e Accumulato. "gohl by 1 b,l
ICI
1A71
t'"oughcarry
(CI- IAOI
S.....ap the 24 b.t n.bblH .n the
(A4_7) <-- (AD - 3)
ACCumulatO'
XAL A A,
JOO'
0
Log,cal and (ontl"'l(S of des'gnated
'eg.ste, ..... tt> Accumvlator
OA A
OR LA
D,
log,eal anu spec, toed Immed,ate Data
..... '1" Accumulalor
111,1 AND data
NOT IAI
ClR A
D,
Add Indoreci the contents the dala
(AI' lei' IRt!
(A).
D,
ml'mo'v(Jacat,on to Ii'll' Accumul,te><
for r = O· 7
,
D,
0
data 10 Ihe Accumulato,
AOlleA@R,
D.
the AccumulaTo,
tor r "" 0-1
(AI
D7
0
"
"
'I
"0 "
'I
"0
"
'I
0
"0
"
"
4-78
0
'2
1
'0
0
'0
.
..
..
0
1
"
'0
'I
CYCLES
BVTES
C
.C
Fl40S
FO
F1
'.F
gO,
ST4.7
",PD8041 Al8741 A
INSTRUCTION SET (CONT.)
MNEMONIC
JNTOaddr
JNT1 addr
JNZ addr
JTF addr
JTOaddr
JT. addr
FUNCTION
(pea 7) ..... addr.f TO=O
(PC) .... (P~l + 2IfTO= 1
(PCO-7) ..... addr.f T1 = 0
(PC) +- (PCI + 2 If T 1 on 1
(PC 0- 7) -addr If A" 0
(PCI- (PC) +2,tA= 0
(PC 0-7)-addr IfTF = 1
(PCI- (PC I + 2 If TF '" 0
IPCO-71 +-addr.' TO= 1
(PCI +- (PC I + 211TO= 0
(PCQ-7) -addr If T1 = 1
Jump to specified address
If
Test o
low
II
Jump 10 specifIed address ,I Tell 1 15 lOW
Jump
10
specified addrell.' accumulator
'1 let
to'
Jump
10
~Klh.d
address ,f Test 0 I' at.
specified addr.., ,f Tesl I
I,
a1
(PCI- (PC) +211Tl "'0
JZaddr
(PC 0 - 7j ..... addr If A" 0
(PC) .... (PC) +21fA = 0
De
0
0
INSTRUCTION COOE
., ..,
Jump 10 specified address ,f Accumulator
.. 0
OS
D.
"
0
0
0
"
"
1
1
D3
D.
Do
CVCLES
IYTES
C At
FO
..
., , 0.'
FLAGS
D,
BT..7
0
.. .,."
" ..
" ..
.. .."
., ... .."
0
0
Jump to SPeCified 'ddress ,f Timer F'ag
Jump 10
..,
'S
0
'S
0
'S
0
'S
1
'S
0
'S
0
'S
0
1
1
1
0
, ",
'0
0
,
'3
'2
'3
0
'2
'3
'2
"1
0
1
1
'3
'2
'I
0
'3
0
'3
0
1
1
'0
0
'0
0
'0
0
'2
'I
'0
1
'2
1
'1
'0
'2
'I
'0
'3
.,
0
CON1AOL
EN I
0151
SEL RBO
Enable the External Interrupt ,nput
o,.able the Elliernal Interrupt ,npyt
IB51 ... 0
Selecl Bank 0 !toealiON 0 - 710' Data
Memory
SEL RB1
SeIIlOt Bank 0 (IQClltlons 24 - 311 of
(BS) +-1
Data Memory
ENDMA
Enabla DMA Handlhake
EN FLAGS
Enabla In_rrupt to MIIIttr DIIVIcIi
DATA MOVES
MO" A, ... dlu
,
MOlle the contenU 0' I.... dll'gnated
reg'Iter, ,nlO the Accumulatol
MO"A,Rr
IAI- IArl,r: 0
MO"A,ilFlr
tAI-IiArll r· 0
MOVA,PSW
tAl- IPSWI
MOV Rr, _dill
IAr!" d11la,r = 0
,
MO"Rr A
IArl-IAI,r -0
,
MO"flAr,A
IIR,II-IAI,r "0
., ••
MOIII Immed'ite IhllPICthed dall mto
the dfttgnlled leg,stlr
MOlle Accumuletor Contents mto thl
des'gnaled rlg'ster
1
.,
0
0
·S
·3
·2
.,
do
.,
1
·S
·3
.,
.,
·0
.,
.,
-0
1
0
1
,
IPSWI' IAI
MOVPA,IlA
IPCO
MOVP3A .11.
XCHA, Fir
IPCO 71-111.1
fPC 8 - 101- 01'
111.1" IlPeI!
IAI;! IRrI,,-0-1
XCHA,.Ar
111.1 ;:IIR,II, ,"0- ,
XCHoA,.A,
III. 0- 31
,-0-1
CPlC
ICI-NOTICI
ComplIment Content of c.rry bit
CPl FO
IFOI - NOT IFOI
Complemenl Content of Flit FO
CPl F1
IF1I- NOT IFlI
Complement Contenl 0' F.., f 1
elA C
lei
CI_ content 01 anv tMt 10 0
CLRFO
IFOI-O
CLRF1
(Fl1+-0
C... coment of Fill 1 10 0
MOV $1'8. A
ST4-8T7+-A4-A7
MOVI high order 4 bits of Accumulator Into ..........., bib 4·7
1
71-IAI
IAI .... UPCII
IIR,II 0- 31).
1
Mow. ImmedIate Ihl IPIICI'"ld dall Into
delamemory
Move contlnts of Accumulator Into Ihe
program III"'S word
Mo.... dati ,n Itle CU"lnt PIlI ,nlO Ih.
Accumulltor
Move Program dltl In
3 ,nto the
Accumulator
0
1
0
p.
Exchlnll Ihl Accumulator Ind
deslgna,11Id 'eg,'."s contents
Elich..... Indltet tontent. of Accumu
'"0r end locatlOft In dill memory
E.c..... lndltlCt4 b,t tontents 0'
Accumulator and eM. memory
0
., . -. -,
Move Ind,rect Accumuiltor Contents
,nto dIItl mlmory 10001lon
IIArll· dlla r = 0
(
0
Movi Contlnll 0' the Program Slatus
Word ,nto Ihl AccumulatOf'
MOV. Ar, _ dlta
~
.
MOlle IndlreCtlhe COnllnlS of dltl
mlmolY 10CI"on ,nlo thl Accumulator
1
MOV PSW, A
~
.,
Move Immed'ite thlspeC,fled dlta ,nlO
Ihe Accumulato.
111.1· dill
••
CI_contentO' flllOlOo.
4-79
0
1
·3
0
II
.flPD8041 A/8741 A
INSTRUCTION SET (CONT.)
MNEMONIC
FUNCTION
D7
DESCRIPTION
De
INSTRUCTION CODE
DI
D4
D3
D2
D1
00
CYCLES
C AC
BYTES
FLAGS
F1 18F
FO
oaF
ST4-7
TPUT
ANLPP. -dl"
IPJiI· IPPI AND data ,
2
logical and Immediate specified data
with designated port
or21
n
p :-1
ANLOPP, A
IPPI -- IPPI ANO IA 0
p ••
,
0
,
d7d&dSd4
"
7
IN A, Pp
(AI· (PPI,p: 1
IN A, DBa
(AI-(OSBI
MOVOA,Pp
MOVDPp. A
IAO-JI .... IPPI p=4-7
7)-0
IPPI- A 0 3 p ~ 4 7
DRlDPP. A
IPPI .... IPPI OR IA 0
2
d3
0
d2
P
d, d O
p
o
LogIC" and contln" of Accumut.tor
wtth "tgNtld POrt 14 - 71.
Input data from deSignated POrt 11 or 2)
.n10 Accumulator
Input strobed CBB data Into
Accumulator and elear ISF
'A.
Move conlents of designated port (4 - 71
Into Accumulator
Move contents of Accumulator to
designated port (4 - 7)
p"4
31
Logical or
cont~ls
of Accumuilitor with
.,
designated port (4 - 71
7
OAlPP. =dlta
(PPI -- IPPI OR data
p. ,
2
logical or Immediate specified data with
'designated port (1 or 2)
,
d7
0UTD8B.'"
t088IIAI
Output conteftU of Accumulator onto
o
DUn Pp, A
IPPI- IAI, p'
DEC R,
IRrl- IFhl
DBBlndtetOBF.
,
2
,0
d&
0
dS
p
cf4
p
dO
0
Output contents of AccumulafOr to
designated pori (lor 2)
REGISTERS
IRrl
I r
~
0
INCRr
IRrI·-IRrt+1 r .. O
INC.R,
IIRrll- URrll + I
r '" 0 ,
CALL at,
IISPII- IPCI, (PSW"
7
7
Oecrem..,1 by 1 contents of designated
Increment by 1 content$ of designated
ret'ster
Increment Indirect by 1 the contents of
data Mltmory location
SUBROUTINE
71
a,o
call deslgl'ated Subroutine
ISPI· (SPI + 1
IPCS 101· ;IlIdrB '0
(PCO-71-MtdrO 7
a9
a7I1f5
a8
aS84
a3
a2 · , a o
CPC 111- DBF
RET
(SPI - ISPI
1
CPCI· IISPI!
Return from Subroutine Wtthoi.ot
reuorlng Program Status Word
RETA
ISPI· (SPI 1
IPCI'- IISPH
Return hom Subroutine restor.ng
Progra,,, Status Word
(PSW"
71 - ilSPII
TIMER/COUNTER
EN TCNTI
Enable Intefnal Interrupt Flag for
Timer/Counter output
0
DIS TCNTI
Double Inter",1 Interrupt Flag for
Timer/Counter output
o
MOVA, T
CAl· ITI
MQVT.A
ITI- IAI
·0
Move contents of Timer/Counter !fIto
Accumulator
Move contents of Accumulator mto
Timer/Counter
STOP TCNT
Stop Count for Event Counter
STAT CNT
S,." Count for Event Counter
Stan Count for Timer
STRTT
NOP
Notes
I No Operalion performed
I
ut Low Voltage (RO,
WR, PSEN, ALE)
V OL1
0.45
v
Output LOW' Vottage (PROG)
VOL2
0.45
VIOL = 2.0 rnA
Oulp.!!!.l!!9h Voltage (RO,
WR, PSEN, ALE)
Oulput High Voltage (AU
Dlhe' Outputs)
ns
1/15 tey - 40
ns
1/2 tey -200
Control Pulse Width (PSEN)
Icc,
800
ns
215lcv -200
Data Setup WR
tow
880
ns
13130 tey - 200
110
Data Hold after WR
two
ns
1/1StCY -50 ®
DeIa Hold (RO, PSEN)
lOR
220
ns
1/10 lev -30
RD to Data In
t R01
800
ns
215 tey - 200
PSENto Data in
t R02
550
ns
3/tOtey -200
Addr Setup to WR
tAW
ns
113 tey -150
680
v
IOL = 20mA
2.4
V
IOH = -400 IJ..A
AddrSetuptoData(PSEN)
'A02
2.4
V
IOH = -400 f.lA
Addr Float to RD, WD
tAF C1
290
Addr Float to PSEN
'AFC2
40
ALE to Control (RD, WR)
tLAFCl
ALE to Control (PSEN)
tlAFC2
0.45
V Ol3
OutpUI High Voltage (BUS)
120
1050
tL.A
Control Pulse Width
Input High Voltage (All
2.4
V
_Ad_d_'-SM_U~p_1_0_0ma_(~R=0~)=--I...
AD~'------1-570---n-s-1-1/_15_Ic~v'---_2~
_ _ __
'OH= -40IJ..A
Input Leakage Current
1090
(T"INn
+ O.45V
(BUS, T 0- High Impedance
1m.
RAM Standby VoIlage
Voo
+ Icc
50
2.2
ns
1/5 tey -75
170
ns
1/10 tey -75
120
ns
1/15 tey - 40
620
ns
4115 tey - 40
1!3Dtey -40
f.lA
VCC?:;C2'-;\-tCC2
=
4.5V
-+--r:.C"'A...2 J'-'-___
PSEN
2mA
lmA
\
Read from External Data Memory
2V
OV
4V
r-:---:---!cv---!'!
ALE
Port P1 and P2 Output High Voltage vs. Source Current
Floating
-Vee
=:
4 5V
Write to External Memory
Typ
I~\
ALE
WR
---------1
Bus Floating
1\
Floating
OV
--
4V
2V
Port 2 Timing
BUS Output Low Voltage vs. Sink Current
ALE
Vee
li'P
11
20mA
PFIDG----------------i
lOmA
/
OV
4-86
/
/
tV
2V
J
5V
J.LPD8048H/8035HL
Instruction Set (for Symbol Definitions, see page 8.)
Mnemonic
Function
Description
D,
D.
Instruction Code
D. D. D. Do
D,
Do
0
d,
d,
d,
d,
do
1
1
d,
d,
d,
d,
do
1
1
Cycl••
e
ayt••
FI...
AC
FO
Accumulator
ADDA,#data
(A) - (A) + data
Add Immediate the specified Data to the
Accumulator.
ADD A, Rr
(A) - (A) + (Rr)
forr=O-7
Add contents of designated register to the
ADDA,@Rr
(A) -(A) + ((Rr))
forr=O-1
d,
d.
d,
1
Accumulator.
Add Indirect the contents of the data mem-
ory location to the Accumulator.
ADDC A, # data
(A) - (A) + (C) + d.ta
AOOCA,Rr
(A) - (A) + (C) + (Rr)
lorr=0-7
nated register to the Accumulator.
ADDCA,@Rr
(A) _ (A) + (C) + ((Rr))
forr = 0-1
Add Indirect with carry the contents of data
memory location to the Accumulator.
ANLA,#data
(A) -(A) AND data
logical AND specified Immediate Data with
ANLA,Rr
(A) -(A) AND (Rr)
1orr=0-7
with Accumulator.
ANLA,@Rr
(A) - (A) AND ((Rr))
1orr=0-1
logical AND Indlfect the contents of data
memory with Accumulator
CPLA
(A)_Nar(A)
Complement the contents of the
CLRA
(A)-O
CLEAR the contents of the Accumulator.
Add Immecbate wHh carry the specified
data to the Accumulator.
d,
Add with carry the contents of the desig-
d,
d,
1
---
Accumulator.
d,
d,
Logical AND contents of designated register
0
1
d,
d,
d,
d,
d,
d,
d,
do
---,---
1
Accumulator.
DAA
DECIMAL ADJUST the contents of the
Accumulator.
DEC A
(A)_(A)_l
DECREMENT by 1 the accumulator's
contents.
INCA
(A)-(A)+ 1
Increment by 1 the accumulator's contents.
ORLA, # data
(A) _ (A) OR data
Logical OR specified immediate data with
Accumulator.
ORLA,Rr
(A) ~(A) OR (Rr)
forr = 0-7
logical OR contents of designated register
with Accumulator.
ORLA,@Rr
(A) - (A) OR ((Rr))
forr=0-1
Logical OR Indirect the contents of data
memory location with Accumulator.
RLA
(AN + l)_(AN)
(Ao)-(A,)
forN = 0-6
Rotate Accumulator left by 1 bit without
carry.
RLCA
(AN + 1) _(AN);N = 0-6
(Ao)-(C)
(C)-(A,)
Rotate Accumulator left by 1 bit through
RRA
(AN)_(AN + 1);N=0-6
(A,)-(Ao)
Rotate Accumulator nght by 1 bit without
RRCA
(AN)_(AN + l);N =0-6
Rotate Accumulator right by 1 bit through
carry.
(A,)~(C)
d,
d,
d,
d,
d,
do
d,
d,
d,
d,
d,
do
.,
·0
1
carry.
carry.
(C)-(Ao!
SWAP A
(A.o-,) - (Ao.o)
XRLA, # data
(A) - (A) XOR data
logical XOR specified immediate data with
Accumulator.
1
d,
1
d,
XRLA, Rr
(A) - (A) XOR (Rr)
forr=0-7
Logical XOR contents of designated register
with Accumulator.
1
1
XRLA,@Rr
(A) ~ (A) XOR ((Rr))
forr=0-1
Logical XOR Indirect the contents of data
memory location with Accumulator.
DJNZ Rr, addr
(Rr) _(Rr)_1;r = 0-7
R(R~ = 0
(PC 0-7) -addr
Decrement the specified register and test
JBbaddr
(PCO-7)_addrHBb -1
(PC) _(PC) + '!fBb = 0
Jump to specified address if Accumulator
bit Is set.
JC addr
(PCO-7)_.ddrHC = 1
(PC) -(PC) + .HC = 0
set.
Swap the two 4-bd: nibbles in the
Accumulator.
., ..
.,
., .,
., .,
.,
., .,
1
.,
Branch
1
contents.
Jump to specified address if carry flag Is
JFOaddr
(PCO-7)-addrifFO "" 1
(PC) -(PC) + .HFO 0
Jump to specified address If Flag FO Is set.
JFl addr
(PCO-7)-addritF1 = 1
(PC)-(PC) + .HFl 0
Jump to specified address If Flag F1 IS set.
JMPaddr
(PC8-10) _addr8_10
(PCO-7) -addrO-7
(PCll)-DBF
Direct Jump to specified address wtthin
the 2K address btock.
JMPP@A
(PCO-7)-((A))
Jump Indirect to specified address with
address page.
JNC addr
=0
=1
(PCO-7)-addrHI =0
(PC) _(PC) +. RI = 1
Jump to specified address If carry flag is
JNladdr
=
=
(PC 0-7) _addrHC
(PC)-(PC) + .HC
b,
b,
a.,
0
a.,
810
low.
Jump to specified address If interrupt is low.
·0
., .,
.,
., ., ., .,
bo
., ., " .. .,"
., ., ., ., "
., ., ., ., "
.," ., ., ., .,
1
., ., ., ., ., ., "
.. ., " .. ., .,
.,
1
4-87
0
·0
·0
·0
'0
·0
·0
0
'0
II
J.tPD8048HI8035HL
- --
Instruction Set (Cont.)
-...tptIan
D,
_1_1
JumplO _ _ _ H1HtO 10 low.
JN11IIIdd.
(PCO-7)-IIdd.H1'O = 0
(PC)-(PC) + ZH1'O = 1
JNT1_
(pcO-7)-IIdd.HT1 = 0
(PC)<-(PCI + 2HT1 = 1
Jump 10 _ _ 1Idd_HlMIl 10 low.
JNZ_
(pcO-7)-_HA = 0
(PC) -(PC) + 2HA = 0
JumplOapacIfItd_ H_mu_
lo_
JTF_
(pC 0-7) <-_ITF
=1
(PC) <-(PC) + ZHTF = 0
JumplO-"'"Io IlIIomal-.up! Flag lor 11mo'/
Cou_output
MOVT,A
(T)-(A)
DloabIelnlomallnlorrupi Flag lor 11mer/
Cou_ output
_ _ arTlna/Cou_,nIO
Accum_
_ _ 01 Accum_intoTlna/
Coun18<
STRTCNT
Stop COunt lor E_ Cou_.
SWt Count lor _
COunter.
STRTT
SWt Count lor Tlna.
MOP
No ~n parIormad.
SIOPTCNT
II
01 dooIgnaIod
au_
(A) -(T)
.....
111: I'll Ft
p
(PP) - (PP) OA_
p= 1-2
MOVA, T
c
Accumu_.
OAL pp, # _
DlSlCN11
lIvteo
1
InIO
_ _ arAccumul_1o
LagIcoIOA_oI Accumu_wIth
deslgnotad pori (4-7).
ENlCN11
CrcIee
from doIIg_ port (1 -2) InIO
(Pp)_(PP)OA(AO_3)
P = 4-7
CALL_,
!!3
Inputotrobod BUS_lnIOAccumulalor.
_ _ oIdooIgnaIod port (4-7)
(BUS) _(BUS) OAdaIa
+ 1;
D.
-.
OALDpp,A
«Ar)) - «Rr))
r=0-1
D.
doolg_ port (4-7).
Input _
ORLBIIS,#daIa
INC@A,
Do
1..-....
LogIcoI AND _late 8pociIIed _
_arBUS.
dooIgnotad port (4-7).
8pociIIeddalawlth
Laglcol OA _
_arBUS.
0-7
Do
II,
MI _ _
Noles: VIN;;' VSS + 0 45V
Output Leakage Current
(BUS. TO - High Impedance State)
10L
Power Down Supply Current
100
Total Supply Current
100 + ICC
Ta '" 2SoC ± SoC,
Vee"" +5V ± 10%. Voo '" +25V ±
±10
~A
7
15
mA
Ta - 2SoC
60
135
mA
Ta
Vee;;;' VIN;;;' VSS+045V
25·C
lV
LIMITS
SYMBOL
MIN
VOO Program Voltage High-Level
VOOH
24.0
PARAMETER
4.75
TYP
MAX
UNIT
260
V
5.25
V
VOO Voltage !-ow-Level
VOOL
PROG Voltage High-Level
VPH
PROG Voltage Low-Level
VPl
EA Program or Verify Voltage High-Level
VEAH
EA Voltage Low-Level
VEAL
VOO ~Igh Voltage Supply Current
100
30.0
mA
PROG High Voltage Supply Current
IpROG
16.0
mA
EA t'ilgh Voltage Supply Current
lEA
10
mA
215
21.5
24.5
V
02
V
245
V
5.25
V
4-94
TEST CONDITIONS
DC CHARACTERISTICS
PROGRAMMING THE
IlPD8748
IlPD8748
READ, WRITE AND INSTRUCTION FETCH - EXTERNAL
DATA AND PROGRAM MEMORY
AC CHARACTERISTICS
Ta
=
ooe to +70"e, Vee - VDD ~ +5V ± 10%, Vss
= OV
LIMITS
PARAMETER
SYMBOL
MIN
TVP
MAX
UNIT
ALE Pulse Width
tLL
400
ns
Address Setup before ALE
tAL
120
ns
Address Hold from ALE
tLA
80
ns
Control Pulse Width (PSEN, RD, WRl
tcc
700
ns
Data Setup before WR
tDW
500
ns
Data Hold after WR
tWD
120
Cycle Time
tCY
25
Data Hold
tDR
0
PSEN, RD to Data In
tRD
Addrec;s Setup before WR
tAW
Address Setup before Data In
tAD
Address Float to RD, PSEN
tAFC
Control Pulse to ALE
tCA
Notes
CD
TEST Q)
CONDITIONS
ns
CL - 20pF
150
~s
6 MHz XTAL
200
ns
500
ns
950
ns
ns
230
0
ns
10
ns
For Control Outputs CL == 80 pF
For Bus Outputs CL = 150 pF
tcv
=
25
~s
PORT 2 TIMING
Ta ~ O'C to t70'C; VCC ~ +5V ± 10%
LIMITS
PARAMETER
SYMBOL
MIN
TVP
MAX
UNIT
TEST
CONDITIONS
Port Controi Setup oefore Failing
Edge of PROG
tcp
110
ns
Port Con..!.!..Q.lliold after Failing
Edge of PROG
tpc
100
ns
PROG to Time P21nput must be
Valid
tpR
Output Data Setup Time
top
250
Output Data Hold Time
tPD
65
I nput Data Hold Time
tpF
0
PROG Pulse W,dth
tpp
1200
ns
Port 2 1/0 Data Setup
tpL
350
ns
Port 2 1/0 Data Hold
tLP
150
ns
810
ns
ns
'ns
150
ns
PROGRAMMING SPECIFICATIONS -IlPD8748
Ta ~ 25'C+
- 5QC'VCC~+5V+ 10%'VDD~+25V± IV
-
PARAMETER
SVMBOL
LIMITS
MIN
Address Setup Time before RESET t
tAW
Address Hold Time after RESET t
twA
4tcV
Data In Setup Time before PROG t
tow
Data In Hold Time after PROG •
two
tpH
4tcV
,4tcV
RESET Hold Time to VERIFV
tVDDW
TVP
MAX
UNIT
4tcV
4tcV
4tCV
0
VDD
VDD Hold Time after PROG •
Program Pulse Width
tvDDH
'tpw
Test 0 Setup Time before Program
Mode
'TW
4tcv
Mode
twT
4tcV
Test 0 to Data Out Delay
tDO
50
60
ms
Test 0 Hold Time after Program
4tcV
RESET Pulse Width to Latch
Address
tww
VDD and PROG Rise and Fall Times
tr,tf
4tcV
0,5
Processor Operation Cycle Time
tcv
6.0
RESET Setup Time before EA t
tRE
4tcV
4-95
2,0
JJS
ps
TEST
CONDITIONS
II
",PD8748
TIMING WAVEFORMS
t---~tLL~-tCY-----f·1
ALE
----'Ii-----,L
~
\ - 1_ _ _ _ _
BUS
INSTRUCTION FETCH FROM EXTERNAL MEMORY
L
ALE
FLOATING
FLOATING
BUS
READ FROM EXTERNAL DATA MEMORY
L
ALE
BUS
FLOATING
FLOATING
WRITE TO EXTERNAL MEMORY
4-96
,..PD8748
TIMING WAVEFORMS
(CaNT.)
PORT 2 TIMING
- - - t____ PROGRAM _ _ __
'0
06 0 06 7
II
J.--
---~
~
-.~-'::"
=--,,,
- - -
-;;-- -,,'-____LJ LI__ -'r---------,'~_____
PROGRAMIVERIFV TIMING
II'PD8748 ONL VI
_____-JI
~
\'--_ _~I
==>- --<'-_':::'~~~,::,!:;;:~::,o_-,,~
-
--<~_..;':::~::~:!::"=-_~ ---
----~)(~--------------~)(~--------------VERIFV MODE TIMING
(I'PD8048/8748 ONLVI
Notes:
(j) Condition.!:. CS TTL Logic "1"; Ao TTL Logic "0" must be met. (Use 10K resistor to
@
VCC for CS, and 10K resistor to VSS for Ao)
s,..s can be achieved using a 3 MHz frequency source (LC. XTAL or external) at the
XTAL 1 and XTAL 2 inputs,
tcv
4-97
INSTRUCTION SET
"PD8748
INSTRUCTION CODE
MNEMONIC
FUNCTION
DESCRIPTION
07
06
FLAGS
Os
0_
03
02
0,
DO
dS
d.
d3
d2
d,
dO
CYCLES
ACCUMULATOR
ADD A,
data
#
ADDA,Ar
(A)
<-.
(AI + data
Add Immediate the specified Data to the
Accumulator
(A)
<-
(A) + (Rr)
Add contents of designated register to
forr'" 0- 7
the Accumulator
AOOA,@Rr
(A)·- (A) + {(Rrll
for r '" 0 -- 1
memory location to the Accumulator
ADOC A,
(A)
s:
data
<-
(A)
+ Ie) + data
(AI- (A) + (e} + IRr)
for r '"
ADOC A,@Rr
ANL A.
~
data
0- 7
~
Add Indirect the contents the data
d7
(AI AND data
Add Indirect With carry the contents of
data memory location to the
Accumulator
Logical and specified Immediate Data
With Accumulator
Logical and contents of deSignated
register With Accumulator
ANLA,@Rr
(A) <- (AI AND ((Ad)
for r = a
1
Logical and Indirect the contents of data
memory wllh Accumulator
CPL A
fA)
CLR A
(AI ---0
NOT (AI
dS
d.
d3
d2
d,
dO
d5
d.
1
d3
d2
d,
dO
dS
d.
d3
d2
d,
dO
0
0
d5
0
d.
1
d3
d2
d,
dO
'3
'2
'1
'0
'3
0
'3
0
'3
0
'3
0
'3
'2
,
'1
'0
'2
1
'2
1
'2
1
'2
'I
0
'0
,
d7
d6
d7
0
d6
,
.d6
1
Complement the contents of the
Accumulator
CLEAR the contents of the Accumulator
DAA
DECIMAL ADJUST the contents of the
Accumulator
DEC A
(AI· (AI
INCA
(A)-, IA)'" 1
Increment by 1 the accumulator's
(AI -- (A) OR data
Logical OR specified Immediate data
With AccumUlator
=data
A. Rr
1
DECREMENT by 1 the accumulator's
contents
,
(AI ~- (AI OR (Rd
for r = a -- 7
Logical OR contents of deSignated
register With Accumulator
DRLA,@Rr
(A) ~ (AI OR nRII)
for (= 0-1
Logical OR Indirect the contents of data
memory location With Accumulator
RLA
(AN'" 1) - (ANI
lAO) <- (A71
for N = 0- 6
IAN ... 1) 0 - IAN}, N = a - 6
(A O) ...... IC)
Rotate Accumulator left by 1 bit ..... Ithol,l!
carry
ORL
d6
0
Add With carry the contents Of the
(A) ~ fA) AND (Rd
for r" 0-7
ORL A,
,
Add Immedl,1te With carry the specified
ANL A. Ar
<-
0
deSignated register to the Accumulator
(A) <- (A) + (e) + liAr!)
for r = 0-- 1
(AI
0
d6
0
data to the Accumulator
ADDCA, Rr
0
d7
ALC A
,
Rotate Accumulator left by 1·blt through
carry
IC) --fA7)
ARA
(AN) ... (AN
(A71 <- (AO)
+ 1 J; N " 0- 6
Rotate Accumulator ngh! by '-bit
Without carry
ARCA
(AN) ... IAN
(A7) - (C)
(C) • (Ao'
+ 1), N '" 0-6
Rotate Accumulator right by l'blt
through carry
(A4-71;:: IAO- 31
Swap the 2 4·blt nibbles 111 the
Accumulator
(A)"" (A) XOR data
Logical XOA speCIfied Immediate data
With Accumulator
XAL A. Ar
(A) .- (A) XOA (Ar)
lorr=0-7
Logical XOR contents of designated
regiSter With Accumulator
XRLA.@Rr
IAI <- (A) XOR {(Rd)
for rea - 1
logical XOA Indirect the contents of data
memory location With Accumulator
SWAP A
XRL A.
1:
data
d7
1
BRANCH
DJNZ Rr, addr
(Ar) ..... (Rr) - 1. r = 0 - 7
If (Ar)" 0
(PC 0- 71-acldr
Decrement the specdled register and
test conten«
'7
'6
's
JBb addr
(PC 0- 7) -addr If Bb '" 1
{PC} +-- (PC) ... 2 .f Db '" a
Jump to speCIfied address If
Accumulator bit IS set
b2
'7
bO
's
JC addr
{PCO-71-addrlIC=1
(PCI <- (PCI + 2 If C = 0
Jump to speCified address.1 carry flag
bl
'6
1
..,
..,
'7
'6
's
'7
0
'7
0
'6
1
'6
{PCa - 101 - addr 8- 10
(PC 0- 7j .... addr 0- 7
fPC 11)-- OBF
Direct Jump to spec.fled address With,"
the 2K address blOCk
'10
'7
JMPP@A
IP,C 0- 7) ..... (fA)}
Jump indirect to speCIfied address ...... th
With address page
JNC addr
(PCO- 71 ..... addr If C '" 0
(PC) ~ (PC) + 2 ., C '" 1
Jump to specified address .1 carry flag IS
low
JNI addr
fPCO- 7) -addr 1'1'" 0
fPC).-- (~l + 2 .f I '" 1
Jump to speCified address .f Interrupt
IS low
JFOaddr
,PCO- 7) ..... addr IfFO = 1
(PCI -)(PC) + 2 If FO = 0
JFl addr
{PCO-7) ..... adcirlfFl = 1
{PCl - (PCI + 2 ,_ Fl '" 0
JMP addr
Jump to specified addreu.f Flag FO IS
Jump to speclfted address If Flag Fl IS
'.
'6
1
,
's
1
's
'S
's
'7
~6
's
'7
0
'6
's
4-98
'.
',-.
,-
''0
',--
1
0
,
'0
'I
'I
'I
0
'0
0
'0
2·
'3
0
'3
'2
1
'2
'I
'0
'I
0
'0
BYTeS
C AC
FO
Fl
INSTRUCTION SET (CaNT.)
"PD8748
FLAGS
INSTRUCTION CODe
MNEMONIC
FUNCTION
DESCRIPTION
JNTO addr
(PC 0-7)-addr .fTO-O
JNTt addr
(PCO- 7)_addr.f T1" 0
07
06
BRANCH (CONT I
Jump to specified address .f Test 0
low
IS
(PCI- {PCI + 211TO= 1
Jump to specifIed address I' Test 1 IS tow
fPCI- (PC) + 2.fT1" 1
a
JNZ addr
(PCO-71-addr.f A =
JTF addr
(PCI- (PCI + 2.fA =0
(PC 0-71-addr If TF"1
(PCI- (PCI + 2 ,f TF = 0
Jump to speCified address ,I Timer Flag
JTO addr
(PC 0-71-addr If TO = 1
Jump to specified address 11
IS
set to
"0
'7
1
T~t
0
IS
a
(PCQ-7)-addr If T1 = 1
"(PC) ..... (PC) +2IfTt ..
Jump to specifIed address ., Test 1 IS a 1
(PC 0-71-addr If A" 0
(PC) +- (PCI +21f A" 0
Jump 10 speclfted address If Accumulator
a
J2 addr
.,
Jump to specified address,' accumulator
(pel- (PCI + 2.,TO" 0
JTl addr
'7
0
"0
'7
,,0
"
CONTROL
0
EN'
Enable the ExternallnterruPl Input
DIS I
Disable the External Interrupt Input
ENTO CLK
0
'6
(OBF) - 0
Select Bank 0 (locations 0
Program Memory
SEL MBl
(DBF)-1
Select Bank 1 (locations 2048
Program Memory
SEL ABO
1851-0
Select Bank 0 Uocatlons 0 - 7) of Data
Memory
SEL AB1
(BS) -1
Select Bank 1 !locatIons 24
Data Memory
(A)-data
Move Immediate the specilled data tr'lto
the AcCumulator
data
MOVA, AI
(i~
',.
,
's
'6
0
'6
0
'6
0
'6
's
'4
0
'S
0
'4
's
's
,
,
'.
, ,
's
's
'S
'4
'.
"
"
03
'3
0
'3
0
'3
0
'3
0
'3
0
'3
0
'3
02
0,
, "
'2
, "
, "
, .,
'2
'2
'2
'2
,
'2
'2
"
",
"
DO
CYCLES
BYTES
C
AS;
FO
F,
'0
0
'0
0
'0
0
'0
0
'0
0
'0
0
'0
2047) of
4095) of
31) 01
DATA MOVES
MOV A,
o.
Enable the Clock Output pin TO
SEL MBO
MOVA,
D.
(A)-(Arl,r=O-7
Ar
Move the,contents of the deslqnated
reglstels Into the Accumulator
(AI-({Rrll,r=O-1
Move Indirect the contents of data
memory location tnto the Accumulatol
MOVA, PSW
(Al-(PSWI
Move contents of the Program Status
Word Into the Al,.cumulator
MOVAr,
(Rr) -data, r =0- 7
Move Immediate lhp speCIfied data 11'110
the deSIgnated leglster
data
MOV AI, A
MOV@Rr,A
MOV@Ar,
dala
MOV PSW, A
(Arl - (Al.r" 0-7
Move AccumUlator Contents mto the
designated register
URrll-(AI,r=O-1
Move Indirect Accumulatol Contents
mto data memory locallon
((Rr)) ..... data.r = 0-1
Move Immed.ate the specIfied data mto
data memory
(PSW)-(AI
Move contents of Accumulator mto the
program stalus word
MOVP A,@A
(PC a - 71
IAI-IIPCII
Move cklta m the current paqe Into the
Accumulator
MOVP3 A,@A
(PCO-7)-(AI
(PCB-101-011
Move Plogram data In Paqe 3 mto the
Accumulator
<-
IAI
",,
0
,
de
dS
d,
d6
dS
d,
0
d6
dS
, ,
d.
dJ
d4
0
d3
d4
d3
0
MOVX A,@R
(A)+-{(RrJl,r=0-1
Move IndIrect the contents of external
data memory Into the Accumulator
((Rr))- (AI. r = 0 - 1
Move Indirect thp contents of the
Accumulator IOta external data memory
XCH A, Rr
(AI
XCH A,@Rr
(AI~((Rdl,r=O-1
XCHDA,@Ar
(AO- 3)
r= 0-1
~
(ArI,r" 0-7
~
((Rr}l 0- 31l,
,
It,.
Exchang"
Accumulator and
deslqnated regIster's contents
Exchange Indirect contents of Accumulator and location," data memory
0
Exchange Indirect 4 bit contents ot
Accumulator and data memory
CPL C
ICI
CPL FO
(FOI ' NOT (FOI
Cqrnplement Content of Flag FO
0
CPL Fl
(FlI
Complpment Content at Flag F 1
0
CLR C
ICI
CLA FO
(FO)' 0
Clear content of Flag 0 to 0
CLA Fl
(FlI
Clear content of Flag 1 to 0
NOT tCI
NOTIF11
Complement Content of carry bit
Clear content of carry bit to 0
0
0
4-99
d,
dO
d2
d,
dO
0
d2
0
d,
dO
,
,
IAI-IIPCIi
MOVX@R,A
d2
II
;,.PD8748
INSTRUCTION SET (CaNT.)
INSTRUCTION CODE
MNEMONIC
FUNCTION
.o.NL BUS, . data
(BUS)
ANL pP. :: data
(Ppl
<-
(BUS) AND data
06
07
INPuT/OUTPUT
DESCRIPTION
Logical and Immediate specIfied data
with contents of BUS
<-
(Ppl AND data
p=1-2
ANLD Pp, A
IPp)
+-
(Pp) AND (A 0 - 31
p=4-7
Logical and Immediate specIfied data
with designatpd port 11 or 21
logical and contents of Accumulator with
deSignated port (4 - 7)
(A) ..... (Ppl. p = 1 - 2
INS A, BUS
(AI- (BUS)
I nput strobed BUS data mto Accumulator
MOVD A Pp
(A 0- 3) <- IPpJ,p = 4-7
IA4-7J-O
(Ppl-A 0 = 3,p" 4 - 7
Move contents of deSignated port (4 - 7)
Into Accumulator
03
02
0'
DO
dO
d3
,
d2
d,
dO
0
p'
,
0
0
d6
d5
0
0
d6
d5
dO
d2
0
,
d3
0
d7
d6
d5
dO
d3
d2
d,
d6
d5
dO
d3
d2
0
0
0
0
0
0
a4
a3
a2
,
FLAGS
DO
d7
d,
IN A. Pp
05
",
CYCLES
p
dO
Input data from designated port (1 - 2)
mto Accumulator
MOVO Pp, A
0
Move contents of Accumulator to
deSignated port (4 - 7)
(BUS) ..... (BUS) OA data
LogIcal or ImmedIate speCIfIed data with
contents of BUS
OAlO Pp, A
(Pp) ..... (Pp) OR fA 0 - 3)
p=4-7
LogIcal or contents of Accumulator wIth
deSIgnated port (4 - 7)
OA L Pp: - data
logical or Immediate speCified data wIth
deSIgnated port (1 - 21
OUTl BUS, A
(Pp) ..... (Ppl OA data
p = 1- 2
(BUS) ..... (A)
OUTL Pp, A
(Pp) ..... (A).p=1-2
Output contents of Accumulator to
deSignated port (1 - 2)
DEC Ar
(Ar) ..... (Rr!
+ 1, r = 0 - 7
Decrement by 1 cont~nts 01 deSignated
rpglster
(Rr);-- (Ar)
+ 1. r
Increment by 1 contents 01 deSignated
OAL BUS,
data
Output contents of Accumulator onto
BUS
0
<"
dO
p
p
"1
dO
a1
aO
REGISTERS
INC
jAr!
~r
liAr)) <- ((Rd)
r=0-1
=- 0 - 7
+ 1,
InClement Indirect by 1 the contents 01
data memory location
SUBROUTINE
CALL addr
RET
liSP)) - (PCI, (PSW 4- 71
(SP) <- (SP) + 1
IPC 8 - 10) <- addr 8 - 10
(PCO-7) ..... addr 0-7
(PC 111- OBF
Call deSignated Subroutine
ISPI - ISPI • ,
Return from Subroutine Without
restonng Pr09ram Status Word
(PC) ..... IISP))
AETR
ISP) ..... fSP) = 1
(PC) ..... IISP))
IPSW 4 71 +-- ((SPII
alO
a9
BR
a7
a6
as
Return from Subroutine restOring
Program Status Word
TIMER/COUNTER
EN TCNTI
Enable Internal lI1!errUPt Flag for
Timer/Counter output
DIS TCNTI
Disable Internal II1terrupt Flag for
Timer/Counter output
MOVA, T
fAI
IT!
Move contents of Timer/Counter II1to
Accumulator
MOV T, A
IT!
fAI
Move contents 01 AccumulatOr lOla
Timer/Counter
STOP TCNT
Stop Count for Event Counter
STAT CNT
Start Count lor Event Counter
STRT T
Start Count for Timer
NO'
No Operation performed
MISCELLANEOUS
Notes
o
0
G)
Instruction Code DeSignations rand p form the bmary representation of The Registers and Ports Involved
®
The dot under the apprOpriate flag bit ,ndiCateS that 115 content IS subject to change by the mstructlon It appears m
@
@)
References to the address and data are speclhed 10 bytes 2 and/or 1 of the IOs!ructlon
Numerical Subscripts appearing 10 the FUNCTION column reference the SpecifiC bits affected
Symbol Definitions·
SYMBOL
A
AC
addr
Bb
BS
BUS
C
ClK
CNT
0
data
DBF
FO. F1
I
P
DESCRIPTION
The AccumulatOr
The AUXIliary carry Flag
Program Memory Address (12 bits)
Bit DeSignator (b = 0 - 7)
The Bank Switch
The BUS Port
carry Flag
Clock Signal
Event Counter
Nibble DeslQnator (4 bits)
Number or ExpreSSion (8 bits)
Memory Bank Flip· Flop
Flag.0.1
Interru t
"In-Page" Operation Designator
DESCRIPTION
SYMBOL
Pp
PSW
Rr
SP
T
TF
TO. T1
X
@
$
Ix)
Ilx))
-
Port DeSignator (p == 1, 2 or 4 - 7)
Program Status Word
Register DeSIgnator (r - 0, 1 or 0 71
Stack Potnter
TImer
Timer Flag
Testable Flags 0, 1
External RAM
PrefiX for Immediate Data
PrefiX for Indirect Address
Program Counter's Current Value
Contents of External RAM Location
Contents of Memory LocatIon Addressed
by the Contents of External RAM Location,
Replaced By
4-100
8VTES
C AC
FO
F'
",PD8748
Package Outlines
For information, see Package Outline Section 7.
Cerdip, !,PD8748D, has quartz window
II
4-101
8748DS-REV2-7-83-CAT
Notes
4-102
NEe
f-LPD80C481 f-LPD80C35
CMOS 8·BIT SINGLE·CHIP
MICROCOMPUTER
Description
Pin Identification
The NEC fLPD80C48 is a true stand-alone 8-bit microcomputer fabricated using CMOS technology. All of the
functional blocks necessary for an integrated microcomputer are incorporated, including a 1K-byte ROM, a 64-byte
RAM, 27 I/O lines, an 8-bit timer/event counter, and a clock
generator. This Integrated capability permits use in standalone applications. For designs requiring extra capability,
the I-lPD80C48 can be expanded using peripherals and
memory compatible with industry-standard 8080A/8085A
processors. A version of the I-lPD80C48 without ROM is
offered by the I-lPD80C35.
Providing compatibility with Industry-standard 8048,8748,
and 8035 processors, the I-lPD80C48 features significant
savings in power consumption. In addition to the power
savings gained through CMOS technology, the I-lPD80C48
is pistinct in offering two standby modes (Halt mode and
Stop mode) to further minimize power drain.
Pin
o
D
Testable Input uSing conditional Jump instructions
JTO and JNTO. Also enables clock output via the
ENTO elK instruction.
Test 0
- . --XT-"-l1-- -Crystal 1
One of two mp-u-Cts-t'"""o-,.-xC""t.-,n-.c-,c-rystal oscillator or
LC CirCUit to generate Internal clock signals May
also be used as an mput for external clock signals
_~~~~!~~~~P~!'_b~~~!!:'l ______ _
-
One of two Inputs for external crystal oscillator or
LC Circuit to generate Internal clock signals. (Non__________ 2!~ompatlbleV_'H_)_ _ _ _ _ _ _
-"RESETReset
Active-low Input hne that Initializes the processor Also used to release both the Halt and Stop
modes !-y--,~----1 Vee
80C48
r+
+5V
>-........- - - - - . . . q C l E A R
30V
BatteryI
5V
0 0 ,1--_ _ _ _ _ _ _--1 RESET
t---~-----------+
f
l
,,®
CD
/\0
®1
...L"'V'"
I
T
0
It>o---<
<-
CLEAR
CD
0
Lv
Not••: CD 0 flip-flops must be CMOS (74C74 or equivalent)
® DeSI nated ates must be CMOS 74CQ4 or equivalent
4-104
Q
-=..
v
,,®
1
J
I-lPD80C48/8OC35
Stop Mode Timing
Oscillator
-Tr
Oscillator
"'::: =t4_s
5 Machine Cycles
Oscillation Stabilization Time
Mon
Stop Mode Circuit: Since Voo controls the restarting
of the oscillator, it is important that VDO be protected from
noise interference. The time required to reset the CPU is
represented by t1 (see Stop Mode Timing diagram), which
is a minimum of 5 machine cycles. The reset operation will
not be completed in less than 5 machine cycles. In Stop
mode, it is important to note that if Voo goes LOW before 5
machine cycles have el~e...QJ.Jhe CPU will be deactivated
and the output of ALE, RD, WR, PSEN, and PROG will not
have been stabilized.
Oscillation stabilization time is represented by t2 (see Stop
Mode Timing diagram). When Voo goes HIGH, oscillator
operation is reactivated, but it takes time before oscillation
can be stabilized. In particular, such high Q resonators as
crystals require longer periods to stabilize. Because there
is a delay between restarting of the oscillator and oscillator
stabilization, t2 should be long enough to ensure that the
oscillator has been fully stabilized.
To facilitate Stop mode control, an external capacitor can
be connected to the RESET pin (see Stop Mode Control
Circuit), affecting only t2, allowing control of the oscillator
stabilization time. When Voo is asserted in Stop mode,
the capacitor begins charging, pulling up RESET. When
RESET reaches a threshold level equivalent to a logic 1,
Stop mode is released. The time it takes RESET to reach
the threshold level of logic 1 determines the oscillator stabilization time, which is a function of the capacitance and
pull-up resistance values.
Stop Mode Control Circuit
+
Note:
G)
II
Q)
Polanzed electrolytic capacItor
Port Operation
Port· Loading Options
10H (min) Vee = vpp = 5V ± 10%; V OH = 2.4V (min)
A port-loading option is offered at the time of ordering the
mask. Individual source current requirements for Port 1
Option
Unit
Selected
P 24-PZ7
P1o- Pn
P ZO - P 23
and the upper and lower halves of Port 2 may be factory
-5
-5
-5
A
~A
set at either - 5fJ-A or - 50fJ-A (see Port-Loading Options
-5
B
-50
-5
~A
table). The - 50fJ-A option is required for interfacing with
-5
-5
-50
C
.A
TTUNMOS devices. The - 5fJ-A option is recom-5
-50
0
-SO
.A
mended for interfacing to other CMOS devices. The
-50
E
-5
-5
.A
CMOS option results in lower power consumption and
-50
-5
F
-SO
.A
greater noise immunity.
-5
-50
-50
G
~A
Port lines P10 to P17 and P24 to P27 include a protective
-50
H
-50
-SO
.A
circuit "E" to prevent a signal conflict at the port. The circuit
Notes: (j) The selection of IOH = - 5f.LA Will result In a port source current of I'LP ~ - 40p.A max
when used as mput port
prevents a logic 1 from being written to a line that is being
@ The selection of IOH = - 50 .... A Will result In a port source current of IILP = - 500jJ.A
pulled down externally (see Port Protection Circuit HE" diamax when used as mput port
gram). When a logic 0 is detected at the port line and a logiC
1 is written from the bus, the NOR gate sends a logic 1 to
the D input of the flip-flop. The output is inverted, forcing the
NAND gate to send a high-level output. This turns off transistor A, preventing the output of a logic 1 from the port.
4-105
J.LPD80C48/8OC35
Oscillator Operation
The oscillator maintains an internal frequency for clock
generation and controls all system timing cycles. The
oscillation is initiated by either a self-generating external
resonator or external clock input. The oscillator acts as a
high-gain amplifier which produces square-wave pulses
at the frequency determined by the resonator or clock
source to which it is connected.
To obtain the oscillation frequency, an external LC network
may be connected to the oscillator, or, a ceramic or crystal
external resonator may be connected.
As the crystal frequency is lowered, there is an equivalent
reduction in series resistance (R). As the temperature of the.
crystal is lowered, R is increased. Due to this relationship, it
becomes difficult to stabilize oscillation when there is low
power supply Voltage. When Vee is less than 2.7V and the
oscillator frequency is 3MHz or less, Ta (ambient temperature) should not be less than -10°C.
Port Protection Circuit "E"
ORL.ANL
Pull-up ReSistance
QI--------;
IN
Crystal Frequency Reference Circuit
LC Frequency Reference Circuit
rl
~omln C2
IC,-C,I
Port Expender
Strobe
~20pF
For example, C1 = 3OpF, and C2 = 10pF
Values of C, and C2 do not Include stray capacitance
Instruction Set Symbol Definitions
Symbol
A
AC
addr
b
BS
BUS
C
ClK
CNT
data
DBF
FO, F1
INT
n
External Clock Frequency Reference Circuit
> __ __-"l2 XTAL1
~
Open
XTAL2
PC
Pp
PSW
R,
SP
T
TF
TO, T1
#
Note: A minimum voltage of Vee-liS required for XTAL1 to go HIGH
@
x
(x)
«x»
/\
V
V
4-107
Description
Accumulator
Auxiliary Carry Flag
Program or data memory address (aO-a7) or (ao-a,o)
Accumulator bit (b - 0-7)
Bank Switch
Bus
Carry Flag
Clock
Counter
8-bit binary data (d o-d7)
Memory Bank Flip-Flop
Flag 0, Flag 1
Interrupt pin
Indicates the hex number of the specified register
or port
Program Counter
Port 1, Port 2, or Port 4-7 (p - 1, 2, or 4-7)
Program Status Word
Register Ro-R7 (, = 0-7)
Stack Pointer
Timer
Timer Flag
Test 0, Test 1 pin
Immediate data indication
Indirect address indication
Indicates the hex number corresponding to
the accumulator bit or page number specified
in the operand
Contents of RAM
Contents of memory addressed by (x)
Transfer direction, result
logical product (logical AND)
Logical sum (logical OR)
Exclusive OR
Complement
II
fJ,PD80C48/80C35
Instruction Set
Function
He.
Cod.
Description
ADD A, Rr
ADD A, @Rr
D.
D,
D.
D,
D.
d,
d,
d.
d,
d,
do
Adds immec:hate data d o-d7 to the accumulator.
Sets or clears both carry flags.®
03
.,
d,
d,
d.
d,
(A) - (A)
+ (R,)
Adds the contents of register Rr to the
accumulator. Sets or clears both carry flags ®
6n@
0
1
1
0
1
+ «R,))
Adds the contents of the internal data memory
location specified by bits 0-5 of register R, to the
accumulator. Sets or clears both carry flags.®
6n@)
+ data + (C)
Adds, with carry, Immediate data d o-d7 to the
accumulator. Sets or clears both carry flags.®
13
Adds, with carry, the contents of register R, to the
accumulator. Sets or clears both carry flags.®
7n®
Adds, with carry, the contents of the Internal data
memory location speCified by bits 0- 5 of register
Rp to the accumulator. Sets or clears both carry
flags.®
7n®
,=
0-7
(A) - (A)
= 0-1
(A) - (A)
ADDCA, R,
(A) - (A)
r
0-7
+ (R,) +
ADDCA,
@R,
(A) - (A)
r = 0-1
+ «R,)) + (C)
ANLA,#
data
(A) - (AlI\data
Takes the logical product (logical AND) of
Immediate data d o-d7 and the contents of
the accumulator, and stores the result in the
accumulator.
53
ANLA, Rr
(A). (A)NR,)
Takes the logical product (logical AND) of the
contents of register Rr and the accumulator, and
stores the result In the accumulator
5n®
Takes the logical product (logical AND) of the
contents of the Internal data memory location
specified by bits 0-5 of register Rp and the
accumulator, and stores the result In the
5n®
=
r
(C)
= 0-7
(A) - (A)I\«R,))
r
= 0-1
Cycles
_ _ _ _~~-----accumula-'-o'--_ __
(A)-(A)
Takes the complement of the contents of the
accumulator.
d,
d,
dJ~~4
d,
0
1
1
1
37
CLRA
(A)·-O
Clears the contents
of the accumulator
1 __
0 ____
0 _ _ _ _ _ _1_ _
=-:--:--_----'---'----'---_
_ _ _--:-'----'
..c.-,,--,-=---::.:,--,.
_ _ _ _ _ _ _ 27 _ _ _0_ _ 0
___
~
Converts the contents of the accumulator to BCD.
57
Sets or clears the carry flags. When the lower 4
bits (Ao-J) are greater than 9, or If the AUXiliary
Carry Flag has been set, adds 6 to A0-3 ' When the
upper 4 bits (47) are greater than 9 or If the Carry
Flag (C) has been set, adds 6 to A4-7 If an
overflow occurs at t~IS pO'"t, C IS set,@ _~. _ _. _ ._. _
DA A
Dec A
(A)-(A) - 1
INCA
(A)-(A)
+1
Decrements the contents of the accumulator by 1:
07
Increments the contents of the accumulator by 1.
17
0
1__
~_~
1
1
_ ___ .__ _
ORLA,#
43
Takes the logical sum (logical OR) of Immediate
(A) - (A)Vdala
data
data d o-d7 and the contents of the accumulator,
c-_ _ _ _ _ _ _ _ _ _ _---.:a"'n"'d stores the result'" the accumulator
______ ~ .. _. _ _._________._ _ _ _ _ _ _ _ _ .~"_
(A) - (A)V(R,)
Takes the logical sum (lo~lcal OR) of register Rr
and the contents of the accumulator, and stores
the result In the accumulator
4n®
ORLA,@R,
(A) - (A)'0(R,»)
0-1
Takes the logical sum (logical OR) of the contents
of the Internal data memory location specified by
bits 0-5 In register Rr • and the contents of the
accumulator, and stores the result In the
accumulator.
4n®
RLA
(Ab + 1) - (Ab)
(Ao)-(A,)
b = 0-6
Rotates the contents Of the accumulator one bit to
the left. The MSB IS rotated Into the LSB.
E7
RLCA
(Ab + 1)-(Ab)
(Ao)·-(C)
(C)-(A,)
b = 0-6
Rotates the contents of the accumulator one bit to
the left through carry.
F7
RRA
(Ab) - (Ab
(A,)-(Ao)
b = 0-6
+ 1)
Rotates the contents of the accumulator one bit to
the right. The LSB IS rotated Into the MSB
77
RRCA
(Ab) - (Ab
(A,)-(C)
(C). (Ao)
b
0-6
+ 1)
Rotates the contents of the accumulator one bit to
the right through carry
67
SWAP A
(A4-,)~(A0-3)
exchanges the contents of the lower 4 bits of the
accumulator With the upper 4 bits of the
accumulator.
47
XRLA, # data
(A) - (A!Vdala
Takes the exclUSive OR of Immediate data d o-d7
and the contents of the accumulator, and stores
03
ORLA, R,
,= 0-7
,=
=
=:-:--::-_----c:-:---c:-::-:=_ _ _-:'c:-he:-re_s-::"_It_in_'-c-he_a_ccumulato_',_ _ _--c-_ _--::XRLA, R,
(A) - (AlV(R,)
r
0-7
Takes the exclUSive OR of the contents of register
Rr and the accumulator, and stores ~he result In
the accumulator.
Dn®
XRLA,@R,
(A) - (AM(R,))
r
0-1
Takes the exclUSive OR of the contents Of the
location In data memory specified by bits 0-5 In
register R" and the accumulator, and stores the
result In the accumulator.
Dn®
DJNZ Rp
addr
(R,)-(R,) -1
If (R,) oj. 0, then
(PCo-7) <. addr
0-7
Decrements the contents of register A, by 1, and If
the result is not equal to 0, Jumps to the address
mdlcated by aO-a7'
=
=
Branch
,=
=
=
JBb addr
(PCo-7) addr If b
1
Jumps to the address specified by aO-a7lf the bit
(PC) + 2,fb
0
(PC)
_ _ _ _----''-='_''-='--'-=-=----=----.:':::n
.::.'h:.:.e::.ac:.:c",":::m.::::ul~~or speCified by bo-b 2 lS set.
=
0--
Bytes
"----------
ADDCA,#
data
CPLA
D.
+ dala
r
ANLA,@Rr
D.
(A) - (A)
Acc;umulator
ADD A, #
data
Instruction Code
D,
4-108
En
x2®
1
1
j.LPD80C48/8OC35
Instruction Set (Cont.)
Instruction Code
Hex
Function
Mnemonic
Code
Description
Branch (Cont.)
JCaddr
(pc..-,) ~ add, It C = 1
(PC)~ (PC) + 21tC = 0
JFO addr
Jumps to the address specified by 80-87 It the
Carry Flag Is set.
F6
(PCo-r) ..... addr If FO
1
(PC)~(PC) + 21tFO = 0
Jumps to the address specified by .0-87 if FO
Is set.
B6
JF1 addr
(PCo-r) .... addr If F1 - 1
(PC)~(PC) + 21tF1 = 0
Jumps to the address specified by 80-87 11 F1
Is set.
76
JMPaddr
(PCB-10)
addr8-10
(pc..-,) ~ add,O-'
(PCll)~ OBF
Jumps directly to the address specified by .0-8'0
x4®
JMPP@A
(PCO-,)~«A))
Replaces the lower 8 bits of the Program Counter
with the contents of program memory specified
by the contents of the accumulator, producing
a Jump to the specified address within the
JNC addr
(PC0- 7)
=
+---
and the OBF.
B3
current page.
<-
addr if C = 0
+ 21tC = 1
(PC)~(PC)
JNI addr
a
addr If I =
(PC)~(PC) + 2111 = 1
(PCo-7)
<-
addr if TO - 0
_ _ _ _-'(1'9 ~ (PC) + 21tTO = 1
JNTOaddr
(PCo-7)
JNT1 addr
(PCo-7) <- addrlfT1 =
(PC) ~ (PC) + 2 ItT!
<-
a
Jumps to the address specified by 80-871' the
Carry Flag is not set
E6
Jumps to the 8ddress specified by 80-87 If the
Interrupt Flag Is not set.
86
Jumps to the address specified by 80 -87 If Test 0
IS LOW.
Jumps to the address specified by 80-87 11 Test 1
Is LOW.
46
(PCO-') ~ add' It A " 0
(PC)~(PC) + 21tA = 0
Jumps to the address specified by ao-87If the
contents of the accumulator are not equal to O.
96
JTFaddr
(PCo-7) ..... addr If TF - 1
(PC)~(PC) + 21tTF = 0
Jumps to the address specified by 80-87 If the
Timer Flag IS set. The Timer Flag IS cleared 8fter
the Instruction is executed.
16
JTOaddr
(PCo-7) ..... addr If TO
Jumps to the address specified by 80-a7 if Test 0
36
JNZ addr
=1
=1
JZ
a6
as
56
(PCo-7) .... addr if A - 0
(PC) <- (PC) + 21f A = 1
Jumps to the address specified by ao-87If the
contents of the accumulator are equalto O.
C6
ENI
Enables external mterrupts. When external
Interrupts are enabled, a low-level Input to the INT
pin causes the processor to vector to the mterrupt
service routine.
05
OISI
Disables external interrupts. When external
Interrupts are disabled, low-level mputs to the tNT
pin have no effect on program execution.
15
ENTOCLK
Enables clock output to pm TO.
75
SEL MBO
Clears the Memory Bank Flip-Flop, selecting
Program Memory Bank 0 [program memory
addresses o-2047(10~' Clears PC1l after the next
JMP or CALL Instruction.
E5
Sets the Memory Bank Flip-Flop, selecting
Program Memory Bank 1 {program memory
F5
~
1
Selects Data Memory Bank 0 by clearing bit 4
(Bank SWitch) of the PSW. SpeCifies data memory
Selects Data Memory Bank 1 by setting bit 4
(Bank SWitch) of the PSW. SpeCifies data memory
24-31(10) as registers 0-7 of Data Memory Bank 1.
D5
HALT
Initiates Halt mode.
01
~
data
(A)~(R,)
Moves immediate data d o-d7 into the
accumulator.
23
Moves the contents of register Rr Into the
accumulator.
Fn@
MDV A. @ R,
(A) ~ «R,))
r = 0-1
Moves the contents of internal data memory
specified by bits 0-5 in register Rr • into the
accumulator.
Fn@
MDV A. PSW
(A) ~ (PSW)
Moves the contents of the Program Status Word
mto the accumulator.
C7
MOVRr,#
data
(Rr) <-data
r
0-7
Moves immediate data do-d7 into register Rr .
Bn@
(R,)~(A)
Moves the contents of the accumulator Into
register Rr
An@
MDV @ R,. A
«R,)) ~ (A)
r
0-1
Moves the contents of the accumulator Into the
data memory location speCified by bits 0-5 in
register Rr .
An@
MDV @ R" #
data
«R,)) ~ data
r = 0-1
Moves Immediate data d o-d7 lnto the data
memory location specified by bits 0-5 10
register Rr .
Bn®
MDV PSW. A
(PSW) ~ (A)
Moves the contents of the accumulator mto the
Program Status Word.
07
MOV A,Rr
r
= 0-7
=
r
= 0-7
=
4-109
82
a1
_:a~o_---::-_-::_
ao
_:a2~___:a,'----a70~-~-___:~
a5
a4
a3
1
82
81
ao
a7
a6
as
a4
a3
a2
a1
ao
1
1
1
0
1
0
0
0
Data Moves
(A)
ao
.5 __~a4'____ _-:a~3_
C5
SELRB1
MDV A.#
ao
al
a6
~~:~:aOn~78.0) as registers 0-7 of Data
data
al
a2
a7
~~~:~S;:t~:;~~:t\~~: Sets pe l1 after the next
SELRBO
a2
83
83
Jumps to the address specified by aO-a7 " Test 1
is HIGH.
(OBF)
83
a=-4_ _ _-:a;'____ac:'2_ _a~1_
Control
SELMBI
0
o
87
(PCo-7) ..... addr If T1 - 1
(PC) .... (PC) + 2 If T1
=a
1
o
~___:~-~(P~C~)-~~(P-C~)~+~2~;=fT~O-=~O-;.~H-'-G-H~-~___:~--~~--~~~___:~--_:a,'----a~,~
JT1 addr
1
1
II
J.LPD80C48/8OC35
_u_
instruction Set (Cont.)
-
MOYPA,@A
Hex
Code
Description
Instruction Code
D,
D.
D.
D.
D.
D.
D,
D.
d,
d,
d,
d,
d,
d,
d,
do
p
do
Data Move. (Cont.)
Movea the content. of the program memory
location specified by PC8-11 concatenated willi
(PCo-,) - (A)
(A)-«Pe))
A3
the contents of the accumulator, Into the
accumulator.
MOVP3A,
@A
(PCo-,) - (A)
(PCo-l1) - 001
(A)-«Pe))
Moves the contenta of the program memory
location specified by 0011 (PC8-11' page 3 of
Program Memory Bank 0) and the contents of the
MOVXA,@R
(A)-«II,))
r = 0-1
Moves the contents of the external data memory
location specified by register Rr • Into the
«II,))-(A)
= 0-1
Moves the contents of the accumulator Into the
external data memory location specffled by
register Rr .
9ft@
r
XCH A, R,
(A)_(R,)
r = 0-7
Exchanges the contents of the accumulator and
register Rr •
2n@
XCHA,@R,
(A)-«R,))
r = 0-1
Exchanges the contents of the accumulator and
the contents of the data memory location
specified by bttl 0-5 In register Rr .
2n@>
(Ao..)-«R'Q-3))
Exchanges the contents of the lower 4 bits of the
accumulator with the contents of the lower 4 bits
of the intema' data memory location specified by
bits 0-51n register Rr•
3n@>
E3
accumulator, Into the accumulator.
MOVX@R,A
8n@
accumulator.
XCHOA,@
II,
r
CPLC
(C)-(C)
Takes the complement of the Carry bit.
A7
CPLFO
(FO)-(FO)
Takes the complement of Flag O.
95
CPLFI
(Fl)-(F1)
Takes the complement of Flag 1.
CLRC
(C)-O
Clears the Carry bit.
B5
97
CLRFO
CLRFI
(FO)-O
Clears Flag O.
85
(Fl)-O
Clears Flag 1.
= 0-1
FI_gs
AS
Input/Output
ANLBUS,#
data
(BUS) - (BUS)/ldata
Takes the logical AND of the contents of the bus
and Immediate data do-d7 , and sends the resutt to
the bus.
98
ANLP.. #
data
(P,) - (P"l;\data
Takes the logical AND of the contents of
designated port Pp and Immediate data d o-d7,
and sends the result to port P~ for output.
9n@
Takes the logical AND of the contents of
designated port Pp and the lower 4 bits of the
accumulator, and sends the result to port Pp for
output.
9n@
Loads the accumulator with the contents of
designated port Pe:
On@
ANLO P.. A
p
(P,) - (P,);\(A0-3)
p
INA,Pp
= 1-2
= 4-7
(A)-(P"l
~
= 1-2
INS A, BUS
(A)-(BUS)
Loads the contents of the bus Into the
accumulator on the rising edge of RD.
08
MOVO A, P,
(Ao..)- (P"l
(4,)-0
Moves the contents 01 designated port Pp to the
lower 4 btts of the accumulator, and clears the
upper 4 bits.
On@
Moves the lower 4 bits of the accumulator to
designated port Pp- The upper 4 bits of the
accumulator are not changed.
3n@
Takes the logical OR of the contents of the bus
and Immediate data do-d7 , and sends the result to
the bus.
88
Takes the logica' OR of the contents of deSignated
port Pp and the lower 4 bits of the accumulator,
and sends the resutt to port P~ for output.
8n@
Takes the logica' OR of the contents of designated
port P~ and Immediate data d o-d7 , and sends the
result 0 port p~ for output.
9n@
P'
MOVDPpo A
= 4-7
(P"l- (Ao-,)
p
= 4-7
ORLBUS,#
data
(BUS) - (BUS)\foata
ORLOp.. A
(P,) - (P"lY(-ConttolXOUIputo.uox:::
Expander _ _ _
If'!'
~,~_
Port~
outPut~""-I
..,.
PROG
4-113
f.-'"
I
~D80C48/8OC35
Block Diagram
A
Oscillator
Frequency
Bus
Buffer
and
Latch
Port 1
Multiplexer
RegIster 0
Test 1
Register 1
Register 2
cc
~
FlagO
-+25Vto + 55V
Power
Supply
Test 0
RegIster 3
Flag 1
Timer Flag
Vss
-Ground
Carry
Register 4
Register 5
Register 6
Voo Standby Power Control
Register 7
Ace Bit Test
a-Level Stack
(Vanable Word Length)
Optional Second
Register Bank
Data Store
Control and Tlmmg
XTAL XTAL
1
2
Low
Power
Standby Control
liD
Expander
Strobe
Resident Data Memory (64x8)
OSCillator!
Crystal
Notel j.LPD80C35 does not Include ROM
Absolute Maximum Ratings*
=
T. 25"C
-40"C to +8S0 C
Operating Temperature, Topt
- 65°C to + 150°C
Storage Temperature (Cerdip Package), T••g
Storage Temperature (Plastic Package), T"9
- 65°C to + 125°C
Voltage on Any Pin, VIIO
Vss - 0.3V to Vee + 0.3V
Supply Voltage, Vee
Vss -0.3to +10V
Power Dissipation, Po
0.3Sw
'COMMENT: Exposing the device to stresses above those
listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated
under conditions outside the limits described in the operational sections of this specification. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
4-114
RAM
~/80C35
Operating Characteristic Curves
output High CUmtllt v•. Output High Voltage
Output High CUmtllt va. Output High Voltage
Vee = 45V
..; -400
-15
\
\ ,\yp
J
~
a
~
:z:
i
Vee = 4 SV
1\
;c
-zoo
~
~
\
J-l0
\
~
-
I
\
u
.c
!!'
:z:
io
~
-5
\ I\YP
~ \.
M~
Output High Voltage. YOH (V)
output High Current v•. Supply Voltage
~~
YOH1 = 24V
Output High Voltage,
-150 -15
;C
.:
'S
~
~
u
rj
II
I
I
J
-100-10
6
-so
-5
"
II
YOH1
(V)
Output High CUmtllt va. Supply Voltage
VOH2=VCC-O 5V
1
-04
J
I
..
u
I
.c
:f
S
~
I
-02
V
/
/
/
1/
-I:
Supply Voltage. Vee (V)
Supply VOltage. Vee (V)
Output Low CUmtllt va. Output Low Voltage
Output Low CUmtllt va. Supply Voltage
Vee = 4 5V
VOL = 045V
t--
/
V
1/
/
V'
,,
,,
//
V
05
Output Low Voltage. VOL (V)
L
I
I
Supply Voltage. Vee (V)
4-115
10
II
f.lPD8OC48/80C35
Operating Characteristic Curves (Cont.)
Port Control Hold After PROG, tpc Max ([.lPD80C48), and Address to
Output Delay, taee Min ([.lPD82C43), vs. Supply Voltage
Supply Current vs. Oscillation Frequency
Vee == 3V
Icc Max/
/
. h:ryp
;;
g
05
-~
)
i
\
~ ~Mon
J,tPD82C43:
02
§
.PD80C48
tpe
u
>-
~
Max
01
1i
g.
~ I"---
i'-
(/l
005
003
01
0.5
02
Oscillation Frequency, f(MHz), (1
=15/t
CY )
Supply Voltage, Vee (V)
Cycle Time vs. Supply Voltage
Current Consumption as a Function of Temperature - Normal
Operating Mode
200
f = 6MHz
Vcc=55V
100
10
.
'.2"'
r-
50
Operation Guarantee
I--Z --
Area
20
t
>=
~
10
'"'"
~
u
--
""'-
--
ICCl
"-
I
I-
Halt Mode
-40
85
25
Temperature, Ta reI
Supply Voltage, Vee (V)
Current Consumption as a Function of Operating FrequencyNormal Operating Mode
Supply Current vs. Oscillation FrequencyCD
Vcc~~
Vee == 5 5V
... V
V
,,
5
,
,,
r----.
,,
,
,,
,
,,
// '/
,,
,,,
1
,,
, ,
V
,
/
/'
"
,
/
01
02
V
/'
, ,
00 5
05
V
...... f.(p
/'
........ ..--
"
./
Max ......
ICCl Max,..........
/
, ,
,
8
//
,,
2
,
,,
,,
,
,,
10
V
02
V/
V
0.5
Oscillator Frequency (MHz)
Note: CD External oscillation IS assumed for frequency less than 1MH7
Internal oscillation requires more power
OscIllation Frequency, f(MHz), (1 == 1SltCY)
4-116
Il-PD80C48/80C35
Operating Characteristic Curves (Cont.)
Current Consumption as a Function of Temperature - Stop Mode
Vee - 5 5V
20
;(
-'Jl
10
,,-
/
/
vV
/
/
/Typ
/'"
-40
25
85
Temperature, T. (0C)
Package Outlines
III
For information, see Package Outline Section 7.
Plastic, fLPD8048HC/35HLC
Ceramic, fLPD8048HD/35HLD
Plastic Shrinkdip, fLPD80C48C
Plastic Miniflat, flPD80C48G/C35G
80C48/80C35DS·REV1·10·83·L-8K
4-117
Notes
4-118
NEe
fJ-PD8049H/fJ-PD8749H/fJ-PD8039HL
HIGH PERFORMANCE
SINGLE CHIP 8·BIT MICROCOMPUTERS
Description
The NEG fLPD8049H, fLPD8749H and fLPD8039HL are single chip 8-bit microcomputers. The processors differ only in
their internal program memory options: the fLPD8049 has
2K x 8 bytes of mask ROM, the fLPD8749 has 2K x 8 of
UV erasable EPROM and the fLPD8039HL has external
program memory.
Pin Identification
Pin
No.
To
Features
High performance 11 MHz operation
Fully compatible with industry standard 8049/8749/8039
Pin compatible with the fLPD8048/8748/8035
HMOS silicon gate technology requiring a single + 5V
±10% supply
1.36 fLs cycle time. All instructions 1 or 2 bytes
Programmable interval timerlevent counter
2K x 8 bytes of ROM, 128 x 8 bytes of RAM
External and internal interrupts
96 instructions: 70 percent single byte
27 110 lines
Internal clock generator
Expandable with 8080Al8085A peripherals
Available in both ceramic and plastiC 40-pin packages
o
o
o
o
o
o
o
o
o
o
o
o
o
Tl
P27
R"Effi
sg
P26
P2S
!NT
One side of the crystal, LC, or external frequency source. (Non-TTL
compatible V1H .)
XTAL2
The other side of the crystal or LC frequency source. For external
sources, XTAL 2 must be driven with the logical complement of the
RESET
Active low input from processor Inltl8lizatlon. RESET IS also used
for PROM programming verification and power-down (non-TTL
compatible VIH~
SS
Single Step inPut (active--Iow~ SS together with ALE allows the
processor to "single-step" through each instruction In program
memory.
INT
Interrupt Input (actlve-Iow~ INT mil start an interrupt if an enable
Interrupt Instruction has been executed. A reset will disable the
interrupt. iff can be tested by issulllg a conditional Jump
instruction.
EA
External Access input (actlve-hlgh~ A logiC "1" at this input com~
mands the processor to perform all program memory fetches from
external memory.
RD
READ strobe outputs (actlve-IO!!l:. RD will pulse low when the processor performs a BUS READ. RD will also enable data onto the
processor 8US from a peripheral device and function as a READ
STROBE for external DATA MEMORY.
PSEN
P17
PIS
PIS
ViR
P14
ALE
P13
DBO
P12
OBI
Pll
DB2
DB3
Pl0
WR
WRITE strobe output (active-low.1:..!{R Will pulse low when the processor performs a BUS WRITE. WR can also function as a WRITE
STROBE for external DATA MEMORY.
11
ALE
Address latch Enable output (actlve-hlgh~ Occurring once each
cycle, the failing edge of ALE latches the address for external
memory or peripherals. ALE can also be used as a clock output.
12-19
0,-1>, BUS
P22
Vss
P20
P21
8-blt, bidirectional port. SY!!£.hron2l!! reads and writes can be performed on this port uSing RD and WR strobes. The contents of the
Do-D7 BUS can be latched In a static mode.
~~~~~c:~t=~!::~~a:C:;~:~~~:n~~II~~~~:~-
ing addressed IIlstruction. Also, for an externa~M d.!!!.store
instruction the Dcr07 BUS, controlled by ALE, RD and WR, contams address and data Information.
Processor's GROUND potential.
20
V"
21-24,
P2IrP27:
35-38
PORT 2
25
PROG
PROG IS used as an output strobe for /J-P08243s dUring I/O expansion. When the fLPD8049H IS used In a stand-alone mode the
PROG pan can be alklwed to float.
26
Voo
Voo IS used to proVide +SVto the 128 x 8-bIt RAM section DUring
normal operation Vee must also be + 5V to provide power to the
other functions in the device. DUring stand-by operation Veo must
remain at + 5V While Vee IS at ground potential.
27-34
P1crP17:
Port 2 IS the second of two 8-brt quasi-bidirectional ports. For
external data memory fetches, the four most Significant bits of
the program counter are contained m P2tJP 23. Bits P20""P23 are
also used as a 4-blt 110 bus for the fLPD8243, INPUT/OUTPUT
EXPANDER.
VDD
PROG
P23
DBS
DB7
Program Store Enable output (actlve-Iow~ PSEN becomes active
only during an external memory fetch.
10
P24
EA
Ali
PSEN
DB4
DBS
XTALI
Vee
XTAL 1
XTAL2
Testable input using conditional transfer functions JTO and JNTO.
The internal State Clock (elK) is available to To usmg the ENTO
eLK instruction. To can also be used during programming as a
testable flag.
XTAL 1 ,"put.
Pin Configuration
TO
Function
Symbol
Port 1 IS one of two 8-bit quasi-bidirectional ports
PORT 1
4-119
39
T1
Testable Input uSing conditional transfer functIOns JT1 and JNT1.
T1 can be made the counter/timer Input using the STRT CNT
instrUction.
40
Vee
Pnmary Power supply. Vcc IS
+5V dunng normal operation
/-LPDS049H/S749H/S039HL
Functional Description
The NEC fLPD8049H, fLPD8749H and the fLPD8039HL are
high performance, single component, 8-bit parallel microcomputers using H-channel silicon gate MOS technology. The
fLPD8049H family functions efficiently in control as well as
arithmetic applications. The powerful instruction set eases bit
handling applications and provides facilities for binary and
BCD arithmetic. Standard logic functions implementation is
facilitated by the large variety of branch and table look-up
instructions.
The instruction set is comprised of 1 and 2 byte instructions,
most of which are single-byte. The instruction set requires
only 1 or 2 cycles per instruction with over 50 percent of the
instructions single-cycle.
The fLPD8049H family of microprocessors will function as
stand-alone microcomputers. Their functions can easily be
expanded using standard 8080N8085A peripherals and
memories.
The fLPD8049H contains the following functions usually found
in external peripheral devices: 2048 x 8 bits of mask ROM
program memory; 128 x 8 bits of RAM data memory; 271/0
lines; an 8-bit interval timerlevent counter; and oscillator and
clock circuitry.
The fLPD8749H differs from the fLPD8049H in its 2048 x 8-bit
UVerasable EPROM program memory instead of the mask
ROM memory. It is useful in preproduction or prototype
applications where the software design has not yet been finalized or in system designs whose quantities do not require a
mask ROM.
The fLPD8039HL is intended for applications using external
program memory only. It contains all the features of the
fLPD8049H except for the internal ROM. The external program memory can be implemented using standard
8080N8085A memory products.
Block Diagram
_Supply
I
Expansion to Additional
External Memory and 110
Bus
Bulle,
~r-----r--------r----~~r---. .------. .--~L-----~~--~------------~~~
~----~
and
~;~
Multiplexer
Reglata'O
Reglat.r1
Reglsler 2
Reglata,3
Reglala,4
RegISIer 5
RegiS.' 6
Reglata,7
8-LavoI Slack
(Variable Word Length)
Opllonal Second
Register Bank
Data Store
COntrol and nmlng
_
XTALXTAL
1
2
Oscillator/
Crystal
Note: ,....PD8039H does not Include ROM.
4-120
DaIa Memory- RAM
(128x8)
j.LPDS049H/S749H/S039HL
Absolute Maximum Ratings*
AC Characteristics
T. = 2S'C
T. = O'Cto +70'C, vee = voo = SV ± 10%, Vss = OV
Limits
Operating Temperature
O'Cto +70'C
Storage Temperature (Ceramic Package)
- 65'C to + 150'C
Storage Temperature (Plastic Package)
-65'Cto +150'C
Voltage on Any Pin
-O.5Vto +7VIJJ
Power Dissipation
1.5W
Note: CD With respect to ground.
'COMMENT: Exposing the device to stresses above those
listed in Absolute Maximum Ratings could cause permanent
damage. The device is not meant to be operated under
conditions outside the limits described in the operational
sections of this specification. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Parameter
Symbol
Limits
Parameter
Symbol
Input Low Voltage
(All Except XTAL 1, XTAL 2)
::u~~~ ~:~~, XTAL 2, RESET)
Min
Typ Max Unit
-0.5
0.8
2.0
V 1H
Input High Voltage
Vee
3.8
(RESET, XTAL " XTAL 2)
Vee
Output Low Voltage (BUS, RD,
WR, PSEN, ALE)
output Low Voltage (All Other
Outputs Except PRDG)
VOLl
Output Low Voltage (PROG)
Test Conditions
V
V
V
0.45
VIOL = 2.0 mA
0.45
VIOL
0.45
VIOL = 2.0 rnA
= 2.0 mA
Output High Voltage (BUS)
2.4
V
IOH = -400IlA
Output High Vottage (RD,
WR, PSEN, ALE)
2.4
V
IOH = -400!-lA
Output High Voltage (All
Other Outputs)
2.4
V
IOH = - 4OiJA,
150
Addr Setup to ALE
tAL
70
ns
2I15tCY -110
Addr Hold from ALE
tLA
50
ns
1I15tCY -40
Control Pulse Width (RD, WR)
tCC1
480
ns
112 tCY -200
Control Pulse Width (PSEN)
350
ns
Data Setup before WR
tow
390
ns
Data Hold after WR
two
40
215 tCY -200
13130tCY -200
1/15tcy -SO ®
Data Hold (RD, PSEN)
110
ns
1110 tCY -30
RDto Data In
350
ns
210
ns
2I5tCY -200
3Il0tCY -200
ns
l/3tCY -150
750
ns
11I151cv - 250
ns
8J15tcY -250
PSEN to Data In
300
Addr Setup to WR
Add, Setup to Data (RD)
480
Add, Setup to Data (PSEN)
Addr Float to RD, WR
Addr Float to PSEN
ALE to Control (RD, WR)
WR, PROG) tCA1
140
ns
2115 tCY -40
10
ns
200
ns
1/30 tCY -40
11StCY -75
50
ns
50
ns
tCA:!
320
ns
4115 tCY -40
Port Control Setup to PROG
tcp
100
ns
1110 tCY -40
Port COntrol Hold to PROG
tpc
160
PROG to P21nput Valid
tPR
Input Data Hold from PROG
tpF
output Data Setup
top
550
140
os
1110 tCY
400
ns
215 tCY -150
1110lev -50
7/10tCY -250
90
ns
tpp
700
ns
Port 2 1/0 Setup to ALE
Port 2 1/0 Hold to ALE
Port Output from ALE
tpL
180
ns
4115 lev - 200
t LP
40
ns
1/10tCY -100
t pv
ns
lev
1.36
.s
3110lev -100
Cycle Time
VD Rep Rate
IOPRR
270
ns
3/15 icy
510
11 MHz
Notes: CD Control Outputs CL = 60pF
BUS Outputs CL = 150pF
® BUS High Impedance Load 20pF
@ Calculated values will be equal to or better than published 8049 values.
AC Characteristics for Programming
T. = 2S'C ± s'C;vee = +sv ± S%;Voo = +21V ± o.sv
Limits
Symbol
Address Setup Time to
RESET I
In.1
Power Down Supply Current
100
Total Supply Current
100
10
+
rnA Ta
= 250C
80 110
Icc
I
Voo Hold Time After PROG
DC Characteristics for Programming
T. = 25'C ± s'C;vcc = +SV ± S'\b;Voo = +21V ± o.sv
Limits
Symbol
Min
VOOH
20.5
Veo Voltage Low Level
4.75
PROG Program Voltage High Level
21.5
5.25
V
V
Test Conditions
J
low
4tCY
two
4lev
IpH
4tCY
t voDW
1.0
tVDOH
1.0
Program Pulse Width
50
Test 0 Setup Time for
Program Mode
4tCY
Test 0 Hold Time After
Program Mode
Test 0 to
60
ms
4tCY
Data Out Oe6ay
4tCY
too
18.5
V
RESET Pulse Width to Latch
Address
tww
4.0
V
~::,Od PROG Rise and Fall
tr
tt
0.5
100
""
17.5
18.5
V
CPU Operation Cycle Time
tCY
4.0
15
""
20.0
mA
RESET Setup Time before EA
tRE
4lev
Notes: Gl Control Outputs CL
Voo High Voltage Supply Current
100
PROG High Voltage Supply Current
IpROG
1.0
mA
EA High Voltage Supply Current
lEA
1.0
mA
Test Conditions
ms
17.5
Low Level
EA Program or Verity Voltage
High Level
1'yp Max Unit
Tvp Max Unit
4tCY
Data In Setup Time to PROG i
Data In Hold Time After
PRDG
Min
4lev
RESET Hold Time to Verify
PRDG Voltage
17130tCY -120
tpo
Address Hold 11me After
RESET I
Parameter
4115 tCY - 200
ns
Output Data Hold
Parameter
Voo Program Voltage High Level
ns
PROG Pulse Wtdth
EA, INT)
Input Leakage Current
Pl1l-17, P20-27, EA, SS
1110tCY -75
1115 tCY -40
Control to ALE (PSEN)
Input Leakage Current
fT"
Conditions
7/30 tcy -170
tLl..
Control to ALE (RD,
DC Characteristics
f lleyl and Test
Tvp Max Unit
ALE Pulse Width
ALE to Control (PSEN)
T. = O'Cto +70'C;Vcc = Voo = +SV ± 10%;Vss = OV
Min
i
=
4tCY
60pF
BUS Outputs CL = l50pF
BUS High Impedance Load 20pF
@ Calculated values will be equal to or better than published 8049 values.
®
4-121
II
fJ.PD8049H/8749H/8039HL
Timing Waveforms
BUS Output Low Vonage vs. Sink Current
Instruction Fetch from External MemOIy
I+\-----Icv - - - - - I
\-"-L-I
,.",
ALE
PSEN
___-+---=-J....:'A~F"'C2,I-'cc'-I-rlc"'A2"_-I'_'____
3mA
vee 2rnA
Read from External Data Memory
.-------Icv---+i
lmA
\
ALE
___~I--_'u~F~~-~~Ic~-1:~....:Ic~A'~____
L-S
RD
~ 'AF~
~
-=FI""oat""'l-ng",r~
Floating
Address
Bus
t AD -
--l
---I,"DF
'D_
Data
4V
Floating
Write to External Memory
Port P1 & P2 Output High Voltage vs. Source Current
ALE
WR
' 0 ",
------=='---1
Floatmg
Vee =
100..l'jp
Port 2 Timing
EXP.:::~
Port
Output
PCH
iJc»
PootCllnl\ool
I~
50..-
0IIIpIII0!III0
EXpa:~ """""'PC"'H"'r-...
-'r"--v-.......:;,:,..,...
Input _
_
_
--:;If...ti---l
av
PRDG~
\
1\
"N
4V
v....
Waveforms for Programming the jJPD8149H
YEAIFY::r- PROGRAM- -
BUS Output High Vonage vs. Source Current
~=---+----:r-
voc
l'jp
/
+2IIV
Voo +5V
/
Iwo
+18V
_I-I'---'~
PROGiiV--~L_,.,,..-------.
___
lCJmA
Program/Verify Timing (ROM/EPROM)
____________Jx~
P~,~
V
______________
av
"N
tV
VOL
4-122
J
j.LPDS049H/S749H/S039HL
Symbol Definitions
Logic Symbol
Description
Symbol
A
1>1::-
addr
Bb
BS
BUS
C
CLK
CNT
0
data
The Accumulator
The Auxiliary Carry Flag
Bft Designator (b = 0 - 7)
The Bank Switch
Reset
Carry Flag
Smgle
Step
Clock Signal
External
Event Counter
Memory Bank Flip-Flop
I
Interrupt
"In-Page" Operation Designator
Pp
Port Designator (p
TF
TI» T1
X
Address Latch
Enable
= 1, 2 or 4 -
Bus
7)
Program Status Word
Register Designator (r = 0, 1 or 0 - 7)
Stack Pointer
Timer
Timer Flag
Testable Flags 0, 1
External RAM
PrefiX for Immediate Data
@
Prefix for Indirect Address
Program COunter's Current value
(x)
((x))
Write
Interrupt
P
T
a049H
8749Hi
a039HL
Program Store
Enable
Nibble Designator (4 bits)
Flags 0, 1
SP
Read
"PO
Number of expression (8 bits)
OBF
Rr
Port 2
The BUS Port
Fo, F1
PSW
Port 1
Program Memory Address (12 bits)
Contents of External RAM Location
Contents of Memory Location Addressed
by the Contents of External RAM location
Replaced By
4-123
Port Expander
Strobe
/J-PDS049H/S749H/S039HL
Instruction Set
InslNelion Code
Function
Mnemonic
Description
Flags
D.
Do
D.
D3
D,
D,
D.
0
d,
d,
d5
d.
d3
d,
d,
d.
d,
d,
0
d5
d,
d,
d,
d,
do
d,
d,
d5
d"
d,
d,
d,
do
d,
d,
d5
d,
d,
d,
d,
do
d,
d,
d,
d,
d,
d,
d,
do
·6
·5
b,
bo
D,
Accumulator
= data
ADDA,
ADDA,Rr
AddA,@Rr
(A) _(A) + «Rr))
1orr=0-1
ADDC A,
= data
ADDCA.,Rr
ADDCA,@Rr
= data
ANLA,
ANLA,Rr
Add Immediate the Speclhed Cata to the
(A) ~ (A) + data
(A) _ (A) + (Rr)
1orr=0-7
Accumulator.
Add contents of designated register to
the Accumulator.
Add Indirect the contents of the data
memory location to the Accumulator.
(A) _ (A) + (C) + data
Add Immediate with carry the specHied
data to the Accumulator.
(A) _ (A) + (C) + (R,)
forr=O-7
Add with carry the contents of the
designated register to the Accumulator.
Add Indirect with carry the contents of
data memory location to the Accumulator.
,(A)-(A) + (C) + «Rr))
forr=O-1
Logical and specified Immediate Data
with Accumulator.
(A) _ (A) AND d.ta
(A)_(A)AND(Rr)
logical and contents of designated
register wHh Accumulator.
forr=O-7
ANLA,@Rr
(A) _ (A) AND «Rr))
forr=O-1
CPLA
(A)-NOT(A)
CLRA
(A)_O
Logical and Indirect the contents of data
memory with Accumulator.
Complement the contents of the
Accumulator.
CLEAR the contents of the Accumulator.
DECIMAL ADJUST the contents of the
DAA
Accumulator.
DEC A
(A)_(A)1
DECREMENT by 1 the Accumulator's
contents.
INCA
(A)-(A)+ 1
Increment by 1 the Accumulator's
contents.
= d.ta
ORLA,
ORLA,Rr
ORLA,@Rr
logical OR specifted Imme(tlate data
(A) _ (A) OR d.ta
with Accumulator.
(A) _(A) OR (Rr)
torr=O-7
logical OR contents of designated
register with Accumulator.
(A) _(A) OR «Rr))
logical OR Indirect the contents of data
forr=O-l
memory location with Accumulator.
(AN + 1)_(AN)
(Aol-(A,)
RLA
Rotate Accumulator left by l-bit without
carry.
forN=O-6
RLCA
(AN + 1)_(AN);N - 0 - 6
(Aol-(C)
(C)-(A,)
RRA
(AN)_(AN + 1);N
(A,)-(A,,)
=0 -
6
(AN)_(AN + 1);N
(A,)-(C)
(C)-(Aol
=0 -
6
RRCA
SWAP A
(A4-,)-(A,,-3)
XRLA,
=data
XRL A, Rr
XRLA,@Rr
Rotate Accumulator left by l-bh through
carry.
Rotate Accumulator right by l-bd
without carry
Rotate Accumulator right by l-bit
through carry.
swap the 2 4-brt nibbles In the
Accumulator.
(A) _ (A) XOR data
Loglcsl XOR specified Immechate data
with Accumulator.
(A) _ (A) XOR (Rr)
logical XOR contents of designated
register with Accumulator
1orr=0-7
(A) _(A) XOR «Rr))
Logical XOR Indll'ect the contents of data
memory location With Accumulator.
forr=O-l
Branch
DJNZ Rr, addr
(Rr)-(Rr) 1;' - 0 - 7
H(Rr) ~ 0:
(pea - 7) +-addr
JBb addr
(PC 0 -7}-addrifBb 1
(PC) -(PC) + 2HBb 0
JC addr
JFOaddr
JF1 addr
Decrement the specified register and
test contents.
=
=
(PC 0 - 7) -add"fC = 1
(PC) -(PC) + 2ifC = 0
Jump to specified address if Accumulator
(PCO-7)-addrffFO=1
Jump to specified address If Flag FO IS
se1.
=0
(PC 0 - 7) -addrIf F1 = 1
(PC) _(PC) + 2HF1 = 0
(PC) -(PC) + UFO
bit IS set
Jump to specified address If carry flag
Isset,
Jump to specified address If Flag F1 IS
set
JMPaddr
(PCS -10)-addrS - 10
(PC 0 -7)-addrO-7
(PCl1)-DBF
Direct Jump to specified address within
the 2K address block,
JMPP@A
(PCO -7)-«A))
Jump indirect to specified address with
address page.
JNC addr
(PC 0 - 7) _addrHC - a
(PC)-(PC) + 2HC 1
Jump to specified address If carry flag
Islow,
JNladdr
(PC a - 7)-addrifl- 0
(PC)-(PC) + 21fl 1
Jump to specifIed address If Interrupt
=
=
is low.
.,
.,
.,
b,
.,
.,
., .,
., ..
1
."" .,·9
., .,
., .,
4-124
·5
·5
.,
.,
as
·5
·5
·5
., ., ., .,
., ., ., .,
., ., ., .,
., ., ., .,
., ., ., .,
., ., ., .,
., ., ., .,
·0
·0
·0
·0
·0
·0
·0
., ., ., ., ·0
Cycles
Bytes
C
AS;
FO
F1
j.1PDS049H/S749H/S039HL
Instruction Set (Cont.)
Flags
InstRiction Code
Mnemonic
Function
D,
Description
D.
D.
D3
D2
D,
., ., .,
., ., "
.......-
.,
.,
.,
.,
.,
.,
.,
.,
.,
.,
.,
.,
.,
.,
.,
D.
Branch (Cont.)
JNTQaddr
(PCD -7)-addrIfTO - 0
(PC)~(PC) + 2nO
1
Jump to specified address If Test 0 is low.
JNT1 addr
(PCD -7)_addrifT1 = 0
(PC) ~(PC) + 2,fn
1
Jump to specified address it Test 1 is low.
JNZaddr
(PCD - 7) _addr if A #= 0
(PC)~(PC) + 2ffA
0
Jump to specified address if Accumulator
JTFaddr
(PCD -7)_addrlfTF = 1
(PC) ~(PC) + 2nF 0
Jump to specified address if Timer Flag Is
JTOaddr
(PC 0 -7)~.ddrlfTO-1
(PC) ~(PC) + 2 lITO 0
Jump to specified address if Test 0 IS a 1.
JT1 addr
(PCO-7)_addrlfT1_1
(PC)~(PC) + 2lfT1
0
Jump to specified address If Test 1 IS a 1.
JZ addr
(PCD -7}-addrIfA - 0
(PC)~(PC) + 21fA
0
Jump to specified address If Accumulator
=
=
=
=
=
=
=
Is non-zero.
settol.
ISO.
..
.., ,
1
0
., ., .,
., ., .,
., .. .,
1
., ., .,
1
Control
EN'
Enable the External Interrupt mput.
D'S I
Disable the External Interrupt mput.
ENTOCLK
.,
., .,
., .,
.,
D.
(OBF)~O
Select Bank 0 (locations 0 - 2047) of
Program Memory.
SELMB1
(OBF)
Select Bank 1 (locations 2048 - 4095) of
Program Memory
SEL RBO
(BS)~O
Select Bank 0 (locations 0 - 7) of
Data Memory.
SEL RB1
(BS)~1
Select Bank 1 (locations 24 - 31) of
Data Memory.
MOV A, - data
(A)
~data
C
AC
FO
F1
..
·0
·0
·0
·0
·0
·0
MOV A, Rr
(A)
~(Rr);r
- 0- 7
MOVA,@Rr
(A)
~«Rr));
r
MOVA,PSW
(A)~(PSW)
~1
II
Data Moves
= data
MOV Rr, A
= data
Move Immediate the specified data mto
the Accumulator.
=0 -
0
d,
d,
Move the contents of the designated
registers Into the Accumulator.
1
=0 -
7
~(A);r
=0 -
«Rr))
~d.ta;
r
1
d,
Move Immediate the specified data IOto
the designated register
- 0- 7
«Rr))
d,
1
=0 -
d,
d,
d,
d,
do
d_
d,
r
d,
r
d,
r
d.
d_
d,
d,
d,
r
do
1
0
1
Move Indirect Accumulator Contents
Into data memory location.
1
Move Immediate the specified data IOto
data memory.
Move contents of Accumulator mto the
program status word.
MOVPA,@A
(PC 0 - 7) ~(A)
(A)~«PC))
Move data In the current page mto the
Accumulator.
MOVP3A,@A
(PCO -7)~(A)
(PCS - 10) ~011
Move Program data m Page 3 mto the
Accumulator.
d,
d,
(A)~«PC))
~«Rr));
1
1
Move Accumulator Contents IOto the
designated register.
(PSW)~(A)
(A)
d_
1
Move Indirect the contents of data
memory location into the Accumulator.
MOVPSW,A
MOVXA,@R
d,
Move contents of the Program Status
Word mto the Accumulator.
(Rr) ~data; r
(Rr)~(A);r
MOV@Rr,A
MOV @ Rr,
Bytes
Enable the Clock Output pm TO.
SELMBO
MOV Rr,
Cycles
r
=0 -
1
Move Indirect the contents of external
data memory mto the Accumulator.
MOVX@R,A
«Rr))~(A);r
XCHA,Rr
(A) c'(Rr); r - 0-7
Exchange the Accumulator and
deSignated register'S contents.
XCHA,@Rr
(A)c'«Rr));r _ 0-1
Exchange Indirect contents of Accumulator and location in data memory.
XCHDA,@Rr
(A 0 - 3) '" «Rr)(O - 3));
r=0-1
Exchange Indirect 4-bit contents of
Accumulator and data memory.
CPLC
(C)
Complement content of carry bit.
CPL FO
(FO) ~ NOT (FO)
Complement content of Flag FO
CPLF1
(F1)~NOT(F1)
Complement content of Flag F1.
CLRC
(C)~O
Clear content of carry bit to O.
CLRFO
(FO)~O
Clear content of Flag 0 to O.
CLRF1
(F1)~0
Clear content of Flag 1 to O.
- 0-1
Move Indirect the contents of the
Accumulator mto external data memory.
Flags
~NOT(C)
4-125
d,
1
/J.PD8049H/8749H/8039HL
Instruction Set (Cont.J
Mn_
Function
Dr
-pHon
D.
D.
D.
D.
D,
D.
0
d,
0
d,
1
d,
1
d,
0
d,
0
d,
0
do
0
d,
1
d,
1
d,
0
d,
P
d,
P
d.
~
ANLBUS.=_
ANLPp,=_
(BUS)
~(BUS)
AND_
(PP)~(Pp)AND_
p=I-2
ANLDPp.A
(Pp)~(Pp)AND(AO
- 3)
p=4-7
INA. PP
(A)~(PP);p
= 1- 2
logical and Immedlate-spec~l8d_
with contents or BUS.
d,
logICal and Immedoata specified data
wfIh dlaogna\8d port (1 or 2~
d,
0
d,
1
0
1
1
logical and contents of Accumulator WJth
designated port (4 - ~
---
D.
(A)~(BUS)
MOVDA.PP
(AO - 3)~(PP);p = 4-7
(A4 -7)~0
a,..
c
F....
FO
At;
Fl
1
Input_l1omdeslgnalo---.
CLEAR
-----~
Q~-+---+-------------4
Clock
~~:: - 1 - - - - - ' - - - - 4
i
O
-
I
I
IN
Crystal Frequency Reference Circuit
LC Frequency Reference Circuit
rl
_L_
45~H
120~H
...L
Nomlnalf
20pF
5.2MHZ
20pF
3.2MHz
C,=Ct;C p•
Not... C2
IC, - C,)
~
20pF
Instruction Set Symbol Definitions
For example, C, == 30pF, and C2 "" 10pF
Values of C1 and C2 do not mclude stray capacitance
Symbol
A
AC
addr
b
BS
External Clock Frequency Reference Circuit
Description
Accumulator
Auxiliary Carry Flag
Program or data memory address (aO-a7) or (aO-al0)
Accumulator bit (b ~ 0-7)
Bank Switch
BUS.____B~uS~~---------------------C
Carry FI1I9
ClK
CNT
Clock
Counter
--~d~a~ta~--~8-~b7.it~b~in~a-r-y~d~m~a~(~d-0--d~7~)------------------_~=
>~--"""------=j XTALl
Open
XTAL2
Note: A minimum voltage ofVcc -1ls reqUired for XTAL1 togo HIGH
__-=D:-B-;:Fc:-----:M=e'-m-,o:-ry Bank Flip-Flop
FO, F1
Flag 0, Flag 1
INT
Interrupt pin
n
Indicates the hex number of the specified register
or port
__-cP""C=--__ Program Counter
__--c='P='P'-:-__-cP=-0:..:r-'.t-'.1'-,P,-0",r-'.t.=2, or Port 4-7 (p = 1,2, or 4-7)
PSW
Program Status Word
R,
Register Ro-R7 (, = 0-7)
SP
Stack Pointer
T
Timer
-----cT=F=---- Timer "'Fo-,a-g----Test 0, Test 1 pin
Immediate data indication
__--""'n"'d.::ir:.ec.::.t=-:a:::d::.:d::.:.re:.s=.s=-.::in"'d::.ic::.:a::.:t"'i0c:.n=___
Indicates the hex number corresponding to
the accumulator bit or page number specified
in the operand
Contents of RAM
Contents of memory addressed by (x)
Transfer direction, result
logical product (logical AND)
TO, T1
#
@
x
(x)
«x»
1\
__.-c"Vc--__--=l:::o'-'g""ic::.:a=:'.:::s.::.um~(:.::lo"'g"'ic:.::a::..'.:::O.:.:R"-)_______________ ._____
¥
Exclusive
OR
-------~~--Complement
4-131
II
~
j-.LPD80C49/80C39
Instruction Set
Instruction Code
Hex
Mnemonic
Description
Function
Code
D.
D.
D,
Do
-~~-~~--"
d,
d,
d,
do
d,
d,
d,
d,
d,
do
1
1
d.
1
d,
0
d,
d,
d,
d,
d,
do
D,
D.
d,
D,
D.
Cycles
Bytes
Accumulator
+ data
ADO A, #
data
(A).- (A)
ADDA,R r
(A) - (A) + (R,)
r = 0-7
ADD A, @R,
(A) - (A) + ((R,))
= 0-1
r
AOOCA,#
Adds the contents of register Rr to the
accumulator Sets or clears both carry ~ags.@
03
6n@
Adds the contents of the Internal data memory
location specified by bits 0-5 of register Rr to the
Sets or clears both carry flags.@
13
(A) e (A) + (R,) + (C)
7n®
Adds, with carry, the contents of the Internal data
memory location specified by bits 0-5 of register
Rr, to the accumulator. Sets or clears both carry
flags.®
7n@
Takes the logical product (logical AND) of
Immediate data d o-d7 and the contents of
the accumulator, and stores the result In the
accumulator.
53
ADOCA,
(A) _ (A) + ((R,)) + (C)
@Rr
r;::: 0-1
ANLA,#
data
(A) - (A)/\data
1
6n@
Adds, with carry, the contents of register Rt to the
accumulator. Sets or clears both carry flags.®
= 0-7
1
~ccumulator.
Adds, wrth carry, Immediate data d o-d 7 to the
accumulator. Sets or clears both carry Ila98.@
r
0
..
(A) - (A) + data + (C)
data
ADDCA, Rr
Adds Immediate data d o-d 7 to the accumulator.
Sets or clears both carry flags.@
1
-~----~-
d,
d,
...
-~~~-.---~---
ANLA, Rr
(A) - (A)/\(R,)
r
ANLA,@Rr
= 0-7
(A) - (A)/\((R,))
r = 0-1
Takes the logIcal product (logical AND) of the
contents of register Rr and the accumulator, and
stores the result In the accumulator.
5n@
Ta!
.Y 20
~
,::
.
~-.
-+
'---
--
t---
r-t-
'"~
0
_ ...._ -
-
I
i
'"
I
Current Consumption as a Function of Operating Frequency Normal Operating Mode
VCC~~
Vee - 5 5V
L/
_.,,
,,
,
,,
21--,
,
,,
1
,
005
01
,
>
,
,
,,
,
02
J/~ ' //
,,
10
8
./
I
V
,,
Max/"
./k;p
/
I
/
"' .... --""
,
./
,
V
V
'eel Max/
--- ,
,
85
25
TemperaturE>, T.. CC)
V
,
,,
Halt Mode
J I1
-40
--r--
5i---
--
Icc I
,
Supply Current vs. Oscillation Frequency'"
,,
I
I
Supply Voltage, Vee (V)
,
I
I
I
I
-_. 1-----
f---
---
Area
i
10
~
~
-----z
optabon Guarantee
I
0
10
I
vV'
V
~r
V
---i- t---
,
0.2
0.5
Oscillator Frequency (MHz)
Note: CDExternal oscillation IS assumed for frequency less than 1 MHz. Internal oscUlation
requires more power.
05
Oscillation Frequency, f(MHz;. (f
V
V
:=
15 tey)
4-140
fLPD80C49/8OC39
Operating Characteristic Curves (Cont.)
Current Consumption as a Function of Temperature - Stop Mode
Vee
20
=5.SV
f-----+---+-f-------.,f-----f
1
u
u
10
-40
85
25
Temperature, Ta
re)
Package Outlines
For information, see Package Outline Section 7.
II
Plastic, ILPD80C49C/C39C
Plastic Shrinkdip. ILPD80C49HC
Plastic Miniflat, ILPD80C49G/C39G
80C49/80C39DS·Rev/1-7-8-83-CAT-L
4-141
NEe
MICROPROCESSORS
iii
NEe
fJ,PD7801 fJ,PD780·1/fJ,PD780·2
HIGH·PERFORMANCE
CP/M®·COMPATIBLE NMOS
8·BIT MICROPROCESSOR
Description
Pin Configuration
The fJ-PD7S0 microprocessor utilizes a highly consistent architectural organization, a comprehensive
instruction set that is a superset of the industry-standard
SOSOA instruction set, and third-generation technology, to
provide a flexible, high-performance, efficient CPU easily
adaptable to a very broad range of industrial and commercial applications.
All software developed on SOSOA-based systems may
be run on 7S0-based systems as a subset of the full 7S0
instruction set. In addition, the NEC fLPD7S0 is fully
pin-compatible and software-compatible with the ZSO®
microprocessor and is therefore perfectly suited for
CP/M® designs. The NEC fJ-PD7S0 provides system
designers with powerful, wide-range logic capability that
requires minimal additional circuitry to complete a microcomputer system.
The output signals of the fJ-PD7S0 are fully decoded and
signal timing is fully compatible with industry-standard
memory and peripheral devices. Two faster versions of the
basic fLPD7S0 (2.5MHz master clock rate) are offered by
the fJ-PD7S0-1 (4MHz master clock rate) and the fLPD7SO-2
(6MHz master clock rate). Other than clock rates, all three
versions are identical.
Features
A,.
A,
As
A7
A.
As
D.
+5V
A,
A.
0,
GND
07
RFSH
D.
M.
0,
RESET
iNT
BUSRQ
WAIT
BUSAK
MREQ
WR
IDRQ
RJj
Pin Identification
Pin
instruction types
Vectored, multilevel interrupt structure
Highly consistent architectural structure featuring dual
register set
Foreground/background programming
Automatic refreshing of external dynamic memory
Signal timing compatible with industry-standard memory and peripheral devices
TTL-compatible signals
Single-phase + 5V clock and + 5VDC power supply
Available in plastic package
Name
No.
Symbol
1-5
30-40
Ao-A 15
Address Bus
Clock
This hne IS used as an Input for external
clock sources.
7-10
0 0-°7
Data Bus
These three-state 1/0 Imes constitute an
8-bit bidirectional data bus
CP/M®-compatible
D Comprehensive, powerful instruction set featuring 15S
D
D
D
A,
--------------------------FU-nC-ti-on-------~
support circuitry
D
D
D
A3
Os
HALT
D Fully ZSO®-compatible
D Industry-standard SOSOA software compatibility
D
D
03
NMI
D PowerfUl, wide-range logic capability requiring minimal
D
A,
0,
12-15
5-1
Smgle + 5V power supply.
11
+5V
Power Supply
16
INT
Interrupt Request
This active-low Input hne is used for interrupt requests by extemalllO devices.
Interrupts are serviced upon completion
of the current instruction if the Interrupt
Enable Flip-Flop (IFF) has been turned on
by the software. There are three Interrupt
response modes: the mode-Q response IS
equivalent to an 8080 Interrupt response,
mode 1 uses location 0038(H) as a restart
address, and mode 2 IS a Simple vectoring
to an interrupt-service routine that can be
located anywhere In memory.
17
NMI
Nonmaskable
Interrupt
This active-low input line is used for nonmaskable Interrupts. A nonmaskable
interrupt is always acknowledged at the
end of the current Instruction, regardless
of whether or not the Interrupt Enable FlipFlop has been turned on, except when the
BUSRQ signal is asserted. Because of the
higher priority of the BUSRQ signal, it is
acknowledged before the NMi signal.
When"'Niii is acknowledged, program
execution automatically restarts from
location 0066(H)'
18
HALT
Halt State
19
MREQ
Memory Request
®Z80 IS a registered trademark of Zllog, Inc
®CP/M IS a registered trademark of Digital Research Corporation
REY/2
These three-state output hnes constitute a
16-bIt address bus. Lines Ao-As output
the external memory address during
refresh operations
This active-low mput line is used with the
HALT instruction to Initiate a halt state.
When HALT is asserted, program execution stops and does not resume until an
Interrupt IS generated. Durmg the halt
state, NOPs are executed In order to continue memory refresh operations.
ThiS three-state active-low output line IS
used to mdicate that the address speCified
for the memory read or write operation
IS valid.
f-LPD7S0nSO·1 nSO·2
Architecture
The architecture includes a dual set of six S-bit generalpurpose registers and two S-bit accumulators and flag
registers. A flexible vectored interrupt structure is supported by an S-bit interrupt vector register that provides
the most-significant S bits of a pointer to a table of vector
addresses, while the requesting device generates the
least-significant S bits of the pointer. Two 16-bit index
registers enable the manipulation of tabular data as
well as facilitating code relocation.
Multilevel interrupts as well as virtually unlimited subroutine
nesting are supported by a 16-bit stack pointer and complimentary 16-bit program counter, enhancing the speed and
efficiency of a wide variety of data-handling operations.
Processing efficiency is additionally supported by a special
memory refresh register that enables automatic refreshing
of all external dynamic memory with minimal processor
overhead.
The dual set of general-purpose registers may be used
as individualS-bit registers or paired as 16-bit registers.
The dual register set (including a dual accumulator and flag
register) not only allows more powerful addressing and data
transfer operations, but also permits programming in foreground/background mode for vastly improved throughput.
Pin Identification (Con~.)
Pin
Name
Function
No.
Symbol
20
IORQ
I/O Request
This three-state active-low output 'me IS
used to mdlcate that the lower half of
the address bus holds a valid address for
an I/O read or write operation. ~
Interrupt acknowledge cycles, lORa
and M', are asserted together to indicate
that a vector address can be sent to the
data bus.
21
RO
Read
This three-state active-low output Ime IS
used to strobe data from external memory
or 1/0 devices onto the data bus. R5 IS
asserted to indicate that the CPU IS
requestmg data from external memory or
110 devices This hne IS three-stated durIng halt or reset condlt,_o_ns_._ _ __
22
WR
Wrrte
This three-state active-low output hne IS
used to strobe data from the data bus to
external memory or 1/0 devices ViR IS
asserted to indicate that the data bus
holds valid data. This hne is three-stated
durmg halt or reset conditions.
This active-low output hne IS used to
Inform the device requestmg bus control
that the data bUS, address bus, and all
three-state~ontrol sIgnals (RD, WR,
10RO, and MREO) are In a hlgh'lmpedance
state and the requesting deVice can now
assume control.
----------------
24
WAIT
Walt State
ThiS active-low Input Ime IS used to indicate that external memory or 110 devices
addressed by the CPU are not ready to
transfer data. When WAIT IS asserted, the
CPU \s placed In a walt condltron
25
BUSRQ
Bus Request
ThiS active-low mput sIgnal IS used to
place the data bus, address bus, and all
three-state bus control sIgnals (WR, RD,
10RO, and MREO) 10 a high-Impedance
state to allow a requestIng deVice to
assume bus control. The BUSRQ signal
has a higher prrorrty than the NMi sIgnal
and IS always honored at the end of the
current machme cycle G)
26
RESET
Reset
This actIve-low Input signal IS used to mitlallze the CPU. When RESET IS asserted,
the Interrupt Enable Flip-Flop IS reset, the
program counter and the I and R registers
are cleared, and Interrupt response mode
o IS enabled. In a reset condition, the
address and data buses are three-stated
and all output control signals are InactIve,
after which program executIon begIns
from address 0000 ®
Machine Cycle 1
ThiS actIve-low output 'me IS used to indicate that the current machine cycle IS the
opcode fetch phase of an instruction
execution.
27
28
RFSH
Refresh
ThiS active-low ol!!E!!!.!ine IS used 10 conJunction With the MREO signal to Imtlate a
refresh read of all external dynamic memory. RFSH and MREQ are both asserted
when the least-significant 7 bits of the
address on the address bus hold a valid
external dynamiC memory address.
29
GNO
Ground
Ground potential
Notes: CD ExceSSive DMA operations resultmg In long periods In which BUSRO IS asserted
can Impair the CPU's ablhty to adequately refresh the dynamiC RAMs
BUSRO does no~ have an Internal pull-up resistor For Input signals to thiS pin In a wlreOR'ed configuration, an external pull-up resistor should be used
® The pulse Width of "RESET must be a minimum of 3 clock cycles In length to remlttalize
the CPU and stabilize operation
5-2
/-LPD780/780-11780-2
Block Diagram
16
Main General-Purpose
Register Set
!
A B Buffer
Alternative General-Purpose
Register Set
-~
r-"~~----,
16
Accumulator
Flag
Accumulator
Flag
A
F
A
F
c
f--_ _:_ _--t_ _ __ _+
I
---1}
___:_',__-+-___c_'
~::eO:~
Interrupt
Vector
Index Register IX
R
General.Purpose Reg,slers
Inst
Decoder
11 1
+5V
GND
Instruction Set
The instruction set of the ~PD780 consists of 158 types of
instructions divided into 16 categories as follows:
8-bit load operations
register exchanges
memory block searches
16-bit arithmetic operations
rotate and shift operations
jump operations
restart operations
miscellaneous operations
16-bit load operations
memory block transfers
This comprehensive instruction set is made more powerful by the array of addressing modes implemented by the
architecture, as follows:
8-bit arithmetic and logic
operations
bit set, reset, and test
operations
liD operations
call operations
return operations
general-purpose
accumulator and flag
operations
5-3
bit addressing
register-indirect addressing
immediate addressing
extended addressing
implied addressing
register addressing
relative addressing
immediate-extended
addressing
indexed addressing
modified page zero
addres~ing
IJ-PD7801780.11780-2
Instruction Set (Cont.)
SYMBOLIC
OPERATION
MNEMONIC
ADC HL,
55
ADCA,r
ADC A,n
DESCRIPTION
NO.
BYTES
NO.T
STATES
C
Z
FLAGS
P/V S
HL-HL+ss+CY
Add with carry reg pair ss to HL
1
15
I
1
V
1
A-A+r+CY
A-A+n+CY
Adc; with carry Reg r to ACe
Add with carry value n to ACe
1
4
7
I
I
I
I
V
V
1
1
H
76
0
X
11
01
101
,,1
101®
010
0
0
1
1
10
11
nn
10
11
10
001
001
nnn
001
011
001
110
nnn
110
101
110
dd
ddd
ddd
ADC A. (HLI
A+--A +(HLl +CV
ADCA,(lX+dt A +-- A + (IX + dl + CY
Add with carry Joe (HLl to ACe
Add with carry toe (IX + dl to ACe
7
19
1
I
I
I
V
V
I
0
0
I
ADC A, (ly + d) A
Add wIth carry toe (ly + d) to ACe
19
I
I
V
I
0
I
AOD A, n
ADDA,
r
ADD A. (HLI
A + (ly + d) + CY
+--
A+--A+n
Add value n to ACe
2
7
A-A+r
Add Reg. r to ACe
1
4
A+--A+(HU
Add location (HLl to ACe
1
7
Add location (IX + dl to ACe
3
19
I
ADD A, (IX + d) A+--A+(JX+d)
I
OPCODE
543 210
N
I
11 111
10 001
101
110
dd
ddd
ddd
11
nn
000 110
nnn nnn
I
V
I
0
1
I
I
V
I
0
I
10 000
I
I
V
I
0
I
10 000 110
I
V
I
0
I
1
A + (Iv + dl
+--
Add locatIon (IV + dl to ACe
3
19
I
ADD HL. S5
HL- HL + ss
Add Reg. pair
to H L
1
11
I
ADO IX, pp
IX <--IX + pp
Add Reg. pair pp to I X
2
15
1
ADO IY, rr
IV
Arjoj
2
15
1
ANDr
ANOn
A-AAr
A ... AAn
4
7
0
0
IV +
<-
'T
R~g.
55
pair rr to IV
Logical' ANO' of Reg r 1\ ACe
I Logical 'AND' of value n 1\ ACe
I
I
V
I
·· ·· ··
· ··
0
X
00 ssl
001®
X
11 011
QQ ppl
101©
001
X
11 111
00 ,,1
101©
001
10
11
nn
10
11
10
100
100
nnn
100
011
100
110
nnn
110
101
110
dd
ddd
ddd
I
I
P
P
I
I
0
0
I
I
7
19
0
0
I
I
P
P
1
1
0
0
I
AND (IY + dJ
A <-AA(IY + dJ
Logical 'AND' of lac !IV + dJ A ACe
19
0
1
P
1
0
1
BIT b, (HLl
Z ~ (HLI b
2
12
X
X
0
1
BlTb,IlX+dl
·
I
Z.-
4
20
BIT b, (IV +d)
z·- (lY+dl b
Test BIT b at location {ly + d}
BIT b, r
Z-rb
CALL ce, nn
If conditIOn cc false contmue,
Test BIT of Reg. r
else same as CALL nn
CALL nn
(SP - 1)
(sp·- 21
PC
+-
<-
~
PC H
PCl
4
2
8
3
10
Unconditional call subroutine at
3
17
CV+-CY
Complement carry flag
A-,
A-n
Compare value n With ACe
cP (HLI
A - (HLI
A-{lX+dl
Compare loc (HU WIth ACe
Compare Joe OX + d) WIth ACe
7
19
Compare loc (ly + d) WIth ACe
19
Compare Reg r With
CP (ly + dl
CPO
A
{HL}
HL ..... HL-l
Be
CPDR
<-
1
Ace
4
7
2
Compa!e locatIon (H LJ and ACe,
decrement HL and Be, repeat untlt
ac=o
2
16
Be - 1
A - (HL)
HL+ HL-'l
aC~BC-l
until A '" (HLl or
Be =
0
5-4
21 If Be
X
X
X
X
X
0
0
0
1
1
1
=0
0
andA'I(HL)
16 If Be '" 0
orA=(HLl
rrr®
11 111 101
10 100 110
dd
ddd
11
01
QQl
11
11
011
001
101®
011
dd
ddd
01
ddd
bbb
11
11
111
001
101®
011
dd
01
ddd ddd
bbb 110
11
01
bbb
ddd
011®
bbb 110
001
110
?~:®®
11 .-100@
nn nnn nnn
nn nnn nnn
11 001
nn nnn
nn nnn
101
nnn
nnn
00 111
111
1
I
V
V
I
I
0
1
1
X
I
I
I
I
I
I
I
I
V
V
I
I
1
1
I
I
10
11
nn
10
11
10
111
111
nnn
111
011
111
110
nnn
110
101
110
dd
ddd ddd
I
1
V
I
1
I
1
4
Compare location (HLl and ACe,
decrement HL and Be
X
0
locatIon nn
CCF
ox +d)
I
nn
Cp,
cPn
CP
1
20
Calt subroutme at location nn 1 f
conditIOn cc IS true
I
·
·
·
·· · ..
·· ·· ..
· ··
I
ddd
0
Logical 'AND' of lac (HL) 1\ ACe
Logical 'AND' of lac (IX + d) A ACe
+ d)
ddd
0
A - AA(HLI
Test BIT b at location (IX
11 111 101
10 000 110
dd
A+-AA(/X+dl
b
ddd
I
AND (HLI
(iX+d)
ddd
0
AND (IX + d)
Test BIT b of location (HU
rrr®
11 011 101
10 000 110
dd
ADD A (ly +d) A
rrr®
rrr®
11
10
111
111
101
110
dd
ddd
ddd
·
l@ ,CD I
1
!
11 101
10 101
101
001
·
1@ lCD,
1
I
11 101
10 111
101
001
f,LPD780n80-1nao-2
Instruction Set (Cont.)
SVMBOLIC
OPERATION
MNEMONIC
DESCRIPTION
NO.
BVTES
NO. T
STATES
e?1
A - (HLI
HL-HL+ 1
BC4-BC-l
Compare location !HU and ACe.
Increment HL and decrement Be
2
CPIR
A - (HLI
HL<-HL+l
Be <- Be - 1
Compare location (HU and ACe,
Increment HL, decrement Be
Repeat untl' Be'" c
2
Complement ACe (l'scomp)
1
4
1
4
A~A
OAA
21 If Be "" 0
and A 4 iHLJ
16 If Be '" 0
or A
until
A=(HL)orBC=Q
e?L
16
Decimal adjust
Ace
r+- r - 1
(HL) ~ (HLI - 1
(IX + d) +- (IX + dl - 1
Decrement Reg r
Decrement loc (HU
Decrement loc (IX + d)
4
11
23
DEC (IV + d)
(ty + dl +- (IV + dl - 1
Decrement loc (lYof d)
23
DEC IX
IX ---IX - 1
Decrement IX
IV -IV-1
DECss
55 ""'55- 1
01
IFF
DJNZ, e
B-B--ldB=O
<-
0
contmue d 8 "
PC ~ PC + e
a
10
Decrement IV
2
10
Decrement Reg pair 55
1
6
Disable Interrupts
1
4
Decrement B and lump relative If
B=O
2
8
IFF
Enable mterrupts
1
4
EX IS?). HL
H-(SP+l)
L- (S?)
Exchange the location {SP} and HL
1
19
IX H .... (SP + 1)
Exchange the location (SP) and IX
2
23
Exchange the location (SP) and IV
2
23
EX (S?I. IX
1
2
EI
<--
IX L - (SP)
EX IS?). IV
IY H .... ISP + 1)
IV I - IS?)
EX AF. AF'
AF .... AF'
Exchange the contents of AF, AF
1
4
EX DE. HL
DE- HL
Exchange the contents of DE and HL
1
4
EXX
BC- BC·
DE - DE·
Exchange the contents of Be, DE. HL
With contents of BC', DE: HL',
respectively
1
4
HL ..... HL·
HALT
Processor Halted
1M 0
IMI
I
1M 2
HALT (walt for Interrupt or resell
1
4
Set Interrupt mode 0
2
8
. Set mterrupt mode 1
I 2
8
Set Interrupt mode 2
2
8
IN A, (n)
A---- In)
Load ACC With Input from deVice n
2
11
IN r. IC)
r+-- (C)
Load Reg r With mput from deVice
2
12
1
11
Ie)
+1
INC (HLI
(HL)
INC IX
IX +--IX+ 1
Increment IX
INC (IX +d)
(IX + dl -- (IX + d) + 1
Increment location (IX
INC IY
IV +--IY
INC (ly +dl
+--
(HL)
Increment location {H Ll
2
10
3
23
Increment IY
2
10
(lY+d)-(lY+d)+l
Increment location (ly + d)
3
23
INC r
r_r+ 1
Increment Reg r
1
4
INCss
ss-ss+ 1
Increment Reg. palT ss
1
6
(HLI
Load location (H L) With Input from
port IC)' decrement HL and 8
2
16
IND
~
+1
(C)
B_ 8'-1
HL-HL-l
+ d)
5-5
·
·
Z
OPCODE
PIV S
N
H
76 543 210
I~
ICD I
1
I
11 101 101
10 100 001
I~
ICD :
1
I
11 101 101
10 110 001
== (HL)
DEer
OEC (HLI
DEC!!X+d)
DEelY
FLAGS
C
· ·, · · ·
·
,
·· ,
,
·
·· ·· ··
·· ·· ··
·· ·· ·· ·· ·· ··
·· ·· ··
·· ·· ·· ·· ·· ··
·· ·· ··
· · ·· ··
·· ·· ·· ·· ·· ··
·· ·· ··
·· ·· ·· ·· ·· ··
·· ·· ··
·· ·· ··
·· ·· ··
·
·· · · · · ·
·
·· ·· ··
1
I
1
?
I
I
V
V
V
1
I
I
1
1
1
I
V
I
1
101
111
1
00
1
00 100 111
I
I
00
00
11
00
dd
11
00
dd
,"
110
011
110
ddd
111
110
ddd
101@
101
101
101
ddd
101
101
ddd
11 011
00 101
101
011
11 111
00 101
101
011
00
ssl 011®
11
110 011
00 010 000
-....-e-2~
11
111
11
100 011
11
11
011 101
100 011
11
11
111 101
100 011
00 001
011
000
11
101
011
11
011
001
01
110 110
11
01
101 101
000 110
11
01
101
010
11
01
101
011
101
110
11
011
011
101
110
nn
nnn
1
?
I
0
:
11
01
101
I
V
1
0
I
00 110 100
I
V
I
0
I
·
·· · . ·, · ·
·
I
V
I
V
,@
X
I
X
",
~~~ CD
000
11 011 101
00 100 011
11 011 101
00 110 100
dd ddd ddd
11 111 101
00 100 011
0
I
11 111 101
00 110 100
dd ddd ddd
0
I
00
1
X
'"
l00®
00 ,,0 011®
11 101
10 101
101
010
f.lPD780/7SO-1178Q-2
Instruction Set (Cont.)
SYMBOLIC
OPERATION,
MNEMONIC
NO
BYTES
DESCRIPTION
NO T
STATES
INOR
IHLI ~ ICI
8 -- B-1
HL·- HL - 1 until B '" 0
Load location (HU with mput from
port (e), decrement HL and deere
ment B. repent until B = 0
21
INI
IHLI ~ ICI
B .- B-1
Load locdtlon (HL) with mput from
port (e). and Increment H Land
decrement B
16
from
21
HL~HL+l
INIR
IHLI ~ ICI
B -- 8 - 1
HL <- HL + 1 until B -=
a
Load location (HL) with
port (e)' Increment HL and
ment B, repeat until B =
C
~
:0
FLAGS
S
P/V
OPCODE
N
H
X
X
a
76 543
210
11
10
101
111
101
010
11
10
101
100
101
010
11
10
101 101
110 010
JP IHLI
PC -- HL
Unconditional Jump to (HL)
11
101
001
JP (IX)
PC'- IX
Unconditional Jump to (IX)
11
11
011
101
101
001
JP (IV)
PC·
Unconditional Jump to (IY)
11
11
111
101
101
001
JP cc, nn
If cc true PC·
10
11
<---cc-'
11
000
011
00
111
000
IV
nn else continue
Jumo to location nn If condition cc
IS
JP nn
PC· nn
Unconditional lump to location nn
10
JR C, e
If C - 0 continue
If C = 1 PC - PC + e
Jump relative to PC + e, II carry - 1
7 If condition
12, If
PC-PC+e
Unconditional Jump relative to PC + e
JR,
01O®
true
.
-'--e-2~
12
00
011
000
110
000
-.--e-2 _ _
JR NC, e
If C = 1 continue
IIC=QPC- PC +e
Jump relative to PC + e If carry = Q
00
JR NZ, e
If Z = 1 continue
Jump relative to PC + e If non-zero
IZ c 01
00
JR Z, e
II Z '" 0 continue
Jump relative to PC + e If zero
IZ 11
00
LO A, (BC)
A~
IBC)
Load ACC With location (BC)
00
001
010
LD A, IDEI
A~
IDEI
Load ACC With location (DE)
00
all
010
LD A, I
A"-I
Load ACC With r
11
01
101
010
101
111
LO A, (nn)
A
Load ACC With locatiOn nn
00
111
010
LO A, R
A - R
11
01
LD IBCI. A'
IBCI
A
Load location (BC) With ACe
LD IDE). A
jOEI-A
Load location tDEI With ACe
LD (HU, n
(HL) .- n
Load lo('atlon (HL) With value n
10
Load Reg pair ss With value nn
Load HL With location (nn)
~e-2-----...
100 000
~e-2 ______
<--
(nn)
~
101
000
~e-2~
0
IFF
13
IFF
Load ACC With Reg R
101
011
101
111
00 000
010
00
010
010
00
110
20
00
,,0
001®
16
00
101
010
Load location (HU With Reg r
01
110
rrr®
Load J With ACC
11
01
101
000
101
111
110
nnn
LD 5S, nn
LD Hl, (nn)
H· (nn + 1)
L <- (nn)
LD (HU,r
IHLI •
LD I, A
I- A
LO IX, nn
IX
LD IX, (nn)
nnn
,
nn
Load IX With value nn
19
11
00
011 101
100 001
IX H <-(nn+l1
IX L ..... (nn)
Load IX With rocatlon (nn)
20
11
00
011
101
LO (IX + d), n
(IX + d) ..... n
Load location (IX + d) With value n
19
11
00
dd
011 101
110 110
ddd ddd
LO(IX+d).r
(IX + d)
Load location (IX + d) With Reg r
19
11
01
dd
011
110
ddd
+--
101
010
nnn
<-
r
5-6
101®
ddd
jl9D7801780-1 1780-2
Instruction Set (Cont.)
SYMBOLIC
OPERATION
MNEMONIC
LD IV, nn
LO IV.
LD
(nn)
55, (nn)
LDOY+dl,n
LD
(ly
+dl. r
LD (nnl. A
LD (nnl.
5S
LD (nnl. HL
DESCRIPTION
IV"- nn
Load IV with location {nnl
SSH .... (nn + 1)
sSL .- (nn)
Load Reg pair dd with location (nn)
Load (ly + dJ with value n
(IV + dl· n
(lY + dl·
4
Load IV with value nn
IV H -- (nn + 11
IV L' (nnl
,
(nn) -- A
(nn + 1\' sSH
tnnl +- sSL
I'
•
20
•
20
•
19
Load location (ly + dl with Reg r
3
19
Load location (nn) with ACe
3
13
Load location Innl with Reg pair dd
(nn + 1) - H
NO T
STATES
NO
BYTES
Load location (nnl with HL
•
3
20
I
16
(nnl- L
LD {nnl. IX
(nn + 1) -
(nnl
LD (nnl. IY
~
IX L
IX H
Load location (nn) with IX
(nn + 1) '-IY H
Load location {nnl with IV
(nnl-IY L
4
•
20
20
LD R, A
R-A
Load R with ACe
2
~
LOr, (HU
r...-(HU
Load Reg r with location (H Ll
1
7
LDr,(lX+dl
r --- (IX + d)
Load Reg r with location (IX + d)
3
19
LOr, (IV+dl
r - (IV + d)
Load Reg r with location (IV + dl
3
19
LD r, n
r~n
Load Reg r with value n
2
7
LD, r,r
r-r'
Load Reg r with Reg r
1
LD SP, HL
SP - HL
Load SP with HL
1
•
LD SP, IX
SP-IX
Load SP with IX
2
10
LOSP. IV
SP-IY
Load SP with IV
2
10
LDD
(DEI- (HLI
DE-DE-l
HL-HL-l
Load location (DEI with location
(HLl, decrement DE. HL and BC
2
16
(DEI - (HLI
Load location (DEI with location
2
21
DE - DE - 1
HL-HL -1
(HLI
2
16
6
BC-Be - 1
LDDR
BC
LDI
~
BC
1 until Be" 0
(DEI- (HLI
Load location IDEI With location
(HLl. Increment DE. HL. decrement
DE .... OE+1
HL .... HL + 1
BC
BC-BC-l
LDIR
(DEI- (HLI
DE - DE + 1
HL- HL + 1
Be - BC - 1 until
NEG
A- O-A
Load location (DEI With location
(HLI. Increment DE. HL, decrement
BC = 0
2
Negate ACC (2'5 complement)
2
21 It BC:fO
16IfBC=O
Be and repeat unttl
Be =
C
Z
FLAGS
P/V S
N
H
·· ·· ··
·· ·· ··
·· ·· ··
·· ·· ··
·· ·· ··
·· ·· ··
·· ·· ··
·· ·· ··
·· ·· ··
·· ·· ··
·· ·· ··
·· ·· ·· ·· ·· ··
·· ·· ··
·· ·· ··
·· ·· ·· ·· ·· ··
·· ·· ··
·· ·· ··
·· ·
·· ·
··
·· ·
OPCODE
76 543 210
11 111 101
00 100 001
nn
nn
nnn
nnn
nnn
nnn
11 111
00 101
101
010
nn
nn
nnn
nnn
nnn
101
~~~®
11
01
ssl
011
nn
nn
nnn
nnn
nnn
nnn
11 111 101
00 110 110
dd ddd ddd
nn
nnn
11
01
111 101®
110
dd
ddd
nnn
",
ddd
00 110 010
nn
nn
nnn
nnn
nnn
~~~®
11
01
101
ssO 011
nn
nn
nnn
nnn
nnn
nnn
00 100 010
nn
nn
nnn
nnn
nnn
nnn
11 011 101
00 100 010
nn
nn
nnn
nnn
nnn
nnn
11 111 101
00 100 010
nn
nn
nnn
nnn
nnn
nnn
11
01
101
001
101
111
01
",
11O®
11
01
011
101®
110
,"
dd ddd ddd
11
01
111
'"
"nnn,
101®
110
dd ddd ddd
00
nn
110®
nnn
01
,"
11
111
001
11
11
011
111
101
001
11
11
111
111
101
001
rrr'®
I
0
0
11 101
10 101
101
000
0
0
0
11 101
10 111
101
000
1(1).
0
0
11
10
0
0
0
11 101 101
10 110 000
1
I
11
01
101 101
100 000
0
5-7
8
I
I
V
I
101 101
000 100
/-LPD780178C).1 1780-2
Instruction Set (Cont.)
SYMBOLIC
OPERATION
MNEMONIC
NOP
NO
BYTES
DESCRIPTION
No operation
A-- AV,
A<· AV n
OR,
OR n
1
Logical 'OR' of Reg r and ACe
LogICal 'OR' of value n and ACe
NO T
STATES
A- AV IHLI
A·- (IX + d)
Logical 'OR' of lac (HU and ACe
Logical 'OR' of loc IIX+diAACC
7
19
OR (ly + di
A·-AVflY+d)
Logical 'OR' of lac IIV +di A ACC
19
OTDR
OTIA
ICi- IHLI
B·- B 1
Hl· Hl 1un1118=0
Load output port (e) with content'>
of location (HL), decrement HL
ICi· (HL)
8·- B-1
Hl· H L + 1 until B
Load output POrt (e) with location
fHL), Increment HL. decrement 8,
repeat until B -
2
load output port (e) with Req r
2
-0
0
and 8, repeat until B
~
2
0
a
21 If B I
16 If B C
0
a
Z
FLAGS
PIV S
21 If B #- 0
16 If B C
·
1
1
P
P
1
P
1
a
1
1
X
1
X
2
11
ICi - IHLI
B· B· 1
Hl HL-l
Load output port Ie) with 'aCaIIQr'
(HLl, mcremf'flt HL and
decrement B
2
16
·
.@ x
OUT!
ICi·- IHU
B· B 1
Hl
HL + 1
L02d output port (C) With lOCution
IHU, InClement HL and
decrement B
2
16
·
@
:~H :- (SP)
(SP + 1)
LOdd IX With top of st
S
M
Sign Negative
S
OPCOOE
76 543 210
11
11
dd
11
111
001
ddd
bbb
11
11
001 011®
bbb
11
00
11
00
11
11
dd
00
11
11
dd
00
001
100
001
100
011
001
ddd
100
111
001
ddd
100
11
00
11
00
11
11
.id
00
11
11
dd
00
001
101
001
101
011
001
nrld
101
111
001
ddd
101
101®
011
ddd
110
'"
'"
011
011®
110
101
011
ddd
110
101
011
ddd
110
011®
'"
011
110
101
011
ddd
110
101
011
ddd
110
11
00
11
00
11
11
dd
00
11
11
dd
00
001
111
001
111
011
001
ddd
111
111
001
ddd
111
011®
10
11
nn
10
11
10
dd
11
10
dd
010
010
nnn
010
011
010
ddd
111
010
ddd
rrr®
110
nnn
110
101
110
ddd
101
110
ddd
10 101
11 101
nn nnn
10 101
11 011
10 101
dd ddd
11 111
10 101
dd ddd
CD
Reg'
B 000
C 001
0 010
E 011
H 100
101
L
110
F
A 111
'"
011
110
101
011
ddd
110
101
011
ddd
110
rrr@
110
nnn
110
101
110
ddd
101
110
ddd
j.LPD7801780·11780.2
Timing Waveforms
Input and output cycles
Opcode fetch instruction cycle
In 110 operations, a single wait state (Tw) is automatically
included to provide adequate time for an 1/0 port to decode
the address from the port address lines and initiate a wait
condition if needed.
At the beginning of the cycle, the contents of the program
counter are placed on the address bus. After approximately
one-half cycle, MREQ is asserted and its falling edge can
be used directly by the external memory as a chip enable
signal. The data from the external memory can be gated
onto the data bus when RD is asserted. The CPU reads
the data at the rising edge of T3' During T3 and T 4' external dynamic memory is refreshed while the instruction is
decoded and executed. The assertion of RFSH indicates
that the external dynamic memory requires a refresh read.
Input Cycle
++___+-':"':::':===-f-_+-+-t~r'-
AO-A'-t~'1>-__
Af, Cycle
IORQ-f-----r~
I---------M, Cycle---------i
T,
liD - f - - - - - r " "
Do-0 7 - f - - - - - r - - - - + - - - - - H
MREQ -+--t-ll
Output Cycle
T,
T2
Port Address
WAIT
-
----------
5 -11
T2
T,
T,
j.LPD7801780-11780-2
Timing Waveforms (Cont.)
Memory read or write cycles
In read and write operations, the MREQ and RD signals
function the same as they do in opcode fetch operations.
In a write operation MREQ is asserted and can be used
directly by external memory as a chip enable signal when
information on the address bus is stable. The WR signal
is used as a write strobe to almost any type of semiconductor memory, and is asserted when data on the data
bus is stable.
IOHcl,(ROI~Ir-+_-+--+--f--+---+--+__+--_
Interrupt request/acknowledge cycle
The interrupt signal is sampled at the riSing edge of the final
clock pulse at th~ end of an instruction. When an inte~
is accepted, an M1 cycle is begun. Instead of MREQ, IORQ
is asserted during this cycle to indicate that an 8-bit vector
LastMCydeoflnstructlon
address can be placed on the data bus by the interrupting
device. This cycle includes the automatic addition of two
wait states to facilitate the implementation of a daisy-chain
priority interrupt protocol.
M, _ _ _ _ _ _ _ _ _ _ _ __
--'-'--'---"1_
LastTState
I
T,
T2
Tw
Tw
Ta
".~~~~..----,~~~v-
iNT~-f==~~~~~- ~=~~-_-_-_ -=.:_-===.:.:_ -_____- _-_~~ ========= ==~~_-=~=_=
X
......A,.
PC
XRefreSh Ad ress
MREQ--~---~----~---_+-~--+_---_+--~
\..-+-
IORQ _ _r_----+-----+_---_+-~-L«-'R~~~
ts""O)~~'"
D~7--r_---_+----+_---_+--__+-+_--~~
In~~---+-
-+__
M, __
~t~DL{~M~"t:::r--I--tMR--+---I
'\.
t OH(M1>H
Al----t-
~---+------~----~------~'
WAIT ____
RD
1________ _
I
I
5-12
f-LltD7801780-1/780-2
Standard Test Conditions
The standard test conditions reference all voltages to
ground (OV) and follow the convention that positive current
flows into the referenced pin. The listing of AC parameters
is based on a load capacitance of 50pF unless explicitly
stated otherwise. For every 50pF increase in load capacitance there is a 10ns delay, up to a maximum increase of
200pF for the data bus and 100pF for the address bus and
the bus control lines.
The operating temperature range is: O°C to + 70°C;
+ 4. 75V :s Vee :s + 5.25V.
Load Circuit for Output
+5V
Load Circuit tor Output
2.2K
FROM OUTPUT <>---....---....-----j1C
UNDER lEST
10K
Absolute Maximum Ratings·
T.
= 25"C
Operating Temperature
O"Cto +70OC
Storage Temperature
- 65°C to
+ 1500C
Voltage on any Pin
-O.3Vto +1V!JJ
Power Dissipation
1.Sw
Note: (j) With respect to ground
*COMMENT: Exposing the device to stresses above
those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be
operated under conditions outside the limits described
in the operational sections of this specification. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
DC Characteristics
T. = o"Cto +7O"C;Vcc = +5V
oth_ise specified.
--
:t:5~unless
I.Imits
-
Unit
Test_. . .
aw-l
Min
Clock Input ~ VOltage
VII.C
-0.3
CI_1npUt High Voltage
VIHC
Input Low VOltage
-0.6
-0.3
Input High VOltage
VII.
V,H
Output Low VOltage
VOL
Output High VOltage
VOH
-Supply ~P0780
Cunent
~P078I).1
Icc
Input~ Currant
T h _ Output Leakage
Current In Float
lu
10
"A VIN
ILOH
10
"A IOV
cc
ILOL
-10
T h _ Output Leakage
Current In Float
Data Bus Leakage Currant
Inlnput_
1YP
Vee
0.45
V
Vee
V
+0.3
2.0
o.a
V
Vee
OA
V
2A
Icc
90
IOL = 1.8mA
V
I"" - - 2SO"A
150
rnA
200
rnA
"10
ILD
V
Ie - 400ns
Ie= 250ns
-
OloVcc
VOUT - 2.4
"A VOUT
"A
= G.4V
OsV1N
sYcc
Capacitance
T. = H"C
----
CI_capo _ _
lnpUt~nce
Output~
I.Imits
II...
Unit
c~
35
pF
c",
COUT
10
SymIooI
II"m
1YP
Test CondItions
pF
'eUnntusurad
= 1MHz
pin.
pF
retumed to ground.
5-13
IJ.PD7801780.11780.2
AC Characteristics
T. = O·C to + 70OC; vee = + 5V ± 5%. unless otherwise specified,
Umits
~PD780'2
Parameter
Symbol
Clock Period
0.4
(j)
Min
"ax
Min
Mu
Unit
D.25
(j)
0.165
(j)
~o
no
Clock Pul.. Width, Clock High
180
®
110
®
65
®
Clock Pull. Width, Clock Low
180
2000
110
2000
65
2000
ns
20
n.
n.
n.
Clock Rise and Fall Time
IRI
Address Output Osley
tD(AD)
Delay to Float
Addro.a Stable P~or 10 i.iiiEci (Memory Cycle)
30
30
145
110
90
110
90
80
®
®
®
Address Stable P~or 10 IORQ, RD or WR (UO Cycle)
ns
®
Address Stable from RD or WR during Roat
Data Oulpul Daley
to(O)
'SP(D)
Data Setup Time to failing Edge or Clock dUring M2 to Me Cycles
230
150
130
n.
90
90
80
no
50
35
60
50
ns
30
40
Data Stable p~or 10 WR (Mamory Cycle)
ns
Data Stable p~or to WR (00 Cycle)
nl
tscaQ)
BUSAK Daley 110m RISing Edge of Clock 10 BUSAK Low
ICUBA)
120
100
90
na
BUSAK Delay from Failing Edge of Clock to BUSAK High
toH(BA)
110
100
90
ns
100
80
70
no
50
80
Daley 10 Floe! (MREQ, IORQ, RD and WR)
no
50
M, Stable PrIor 10 IORQ (Inlerrupl Ack.)
ns
HALT Daley nmo 110m failing Edge of Clock
IORQ Daley loom Riling Edge of Clock to IORQ Low
300
1o(H!)
INT Setup Time to Rising Edge of Clock
80
tOLoMIR)
IORQ Delay from failing Edge of Clock to IORQ Low
iORQ Daley loom Riling Edge of CI_lo IORQ High
iORQ Daley loom failIng Edge of Clock to IORQ Hogh
lottc!>(IR)
M, Defay from RI.'ng Edge of Clock to M, Low
M, Dalay loom Rising Edge of Clock 10 M, High
MREQ Daley 110m Failing Edge 01 Clock 10 MREQ Low
MREQ DaIsy loom Riling Edge of CI_ to MREQ HIgh
UREQ Delay trom Failing Edge of Clock to MREQ High
na
300
80
75
65
ns
110
85
70
na
100
65
70
ns
110
85
70
ns
130
100
80
na
130
100
80
ns
100
85
70
ns
100
65
65
70
no
70
ns
100
....MRL)
no
Pul.. Width, MREQ HIgh
lwtMRH)
ns
Pul.. Width, iiiil Low
tW(NMI)
80
RESET Setup nme 10 Rising Edge of CI_
ts(RS)
80
RD Daley loom RIsing Edge of Clock 10 RD Low
80
80
70
no
130
95
80
no
RD Delay from RIsing Edge of Clock to RD H~h
100
85
70
na
RD Daley loom failing Edge of CI_ to RD High
110
180
65
70
110
ns
130
150
120
100
no
RFSH Daley loom Rising Edge of Clock to RFSH Low
RFSH Daley lrom Riling Edge of CI_ to RFSH High
tOH(RF)
WAIT Setup TIme 10 Failing Edge 01 Clock
IS(W!)
70
80
WR Deley 110m Failing Edge of Clock 10 WR Low
WR Delay 'rom Felling Edge of Clock to WR High
toH;f;(WR}
Pulae WIdth to WR Low
tW(WRL)
@
ill
QiI
Gl>
@
@
+ Iw(L) +
no
CL
= 30pF
na
60
70
WR Daley 110m RISIng Edge of CI_ to WR Low
= 50pF
ns
65
tm.4:(RO)
CL
ns
70
80
100
RD Detey loom Failing Edge of CI_ to RD Low
CL = 50pF
ns
70
80
Pulse Wldlh, MREQ Low
Ie ~ Iw(~H)
C L = 50pF
na
Any Hold Time for Setup T1me
®
®
®
®
®
®
= 200pF
na
®
BUSRQ Setup nme to RISIng Edge of Clock
•• (j)
CL
ns
Data Stable lrom WR
-
CL = 50pF
ns
®
Detay to Float dunng WrIte Cycle
Data Setup Time to Rising Edge of Clock dUring M1 Cycle
ns
no
Add..... Stable from RD or WR
Test Conditions
60
no
90
65
80
70
ns
100
80
70
nl
nl
'R + 'F
Though the structure of the 780 IS statlc, 2OO..,s IS a guaranteed maximum
IACM ~ 1w(H) + Ie - 65 (75)" (50)""
IACI ~ Ie - 70 (80)" (55)""
leA = tw!L) +
SO (40)" (50)"
leAF ~ tw!L) + -45 (60)" (40)""
iocM ~ Ie - t70 (210)" (140)"
loCI = tw!L) +
t70 (210)" (140)"'
IeOF ~ Iw(L) +
70 (80)" (55)""
~ 2tc + tw(H) + 'F - 65 (80)' (SO)"
Iw(MRL) = Ie - 30 (40)"(30)'"
Iw(MRH) ~ 1w!H) + IF - 20 (30)" (20)""
Iw(WR) ~ Ie - 30 (40)' (30)""
"'R
'R 'R
'R 'R -
Package Outlines
For information. see Package Outline Section 7,
Plastic, jJ.PD7S0C
Ceramic, jJ.PD7S0D
These values apply 10 the ~PD780
.. These values apply to the ,...PD780·2
780n80-1nSO-2DS-Rev 2-7-83-CAT-L
5-14
NEe
",PD8085AH
",PD8085A·2
fLPD8085A SINGLE CHIP 8·BIT
N·CHANNEL MICROPROCESSOR
'DESC R I PTI ON
FEATURES
The pPD8085A IS a single chip 8-blt microprocessor which IS 100 percent software
compatible with the Industry standard 8080A. It has the ability of increasing system
performance of the Industry standard 8080A by operating at a higher speed Using
the pPD8085A In conjunction with its family of ICs allows the designer complete
flexibility With minimum chip count.
• Single Power Supply: +5 Volt, ±10%
•
Internal Clock Generation and
System Control
•
Internal Serial In/Out Port.
•
Fully TTL Compatible
•
Internal4-Level Interrupt Structure
•
Multiplexed Address/Data Bus for
Increased System Performance
•
Complete Family of Components for
Design Flexibility
•
Software Compatible with I ndustry Standard 8080A
•
Higher Throughput. pPD8085AH - 3 MHz
pPD8085A-2 - 5 MHz
•
Available in Either Plastic or Ceramic Package
PIN CONFIGURATION
Xl
Vee
HOLD
X2
RO
SOD
HlDA
elK lOUT)
SID
TRAP
RESETIN
READY
RST 7 5
loiM
RST 6.5
RST 5 5
INTR
INTA
ADO
Sl
RD
WR
ALE
",PO
8085A
So
ADl
AD2
A15
A14
AD3
A13
A12
A11
AD4
AD5
AD6
AD7
AlO
Ag
VSS
AS
Rev/S
5-15
",PD8085A
The IlPD8085A contains six 8-bit data registers, an 8-bit accumulator, four testable
flag bits, and an 8-bit parallel binary arithmetic unit_ The IlPD8085A also provides
decimal arithmetic capability and it includes 16-bit arithmetic and immediate operators
which greatly simplify memory address calculations, and high speed arithmetic
operations_
FUNCTIONAL
DESCRIPTION
The IlPD8085A has a stack architecture wherein any portion of the external memory
can be used as a last in/first out (li Fa) stack to store/retrieve the 'contents of the
accumulator, the flags, or any of the data registers.
The IlPD8085A also contains a 16-bit stack pointer to control the addressing of this'
external stack. One of the major advantages of the stack is that multiple level interrupts can easily be handled since complete system status can be saved when an interrupt occurs and then restored after the interrupt is complete. Another major advantage
is that almost unlimited subroutine nesting is possible.
The IlPD8085A was designed with speed and simplicity of the overall system in mind.
The multiplexed address/data bus increases available pins for advanced functions in the
processor and peripheral chips while providing increased system speed and less critical
timing functions. All signals to and from the IlPD8085A are fully TTL compatible.
The internal interrupt structure of the IlPD8085A features 4 levels of prioritized
Interrupt with three levels internally maskable_
Communication on both the address lines and the data lines can be interlocked by using
the HOLD input. When the Hold Acknowledge (HLDA) signal is issued by the processor, its operation is suspended and the address, data and control lines are forced to be
in the FLOATING state. This permits other devices, such as direct memory access
channels (DMA), to be connected to the address and data busses.
The JlPD8085A features internal clock generation with status outputs available for
advanced read/write timing and memory/IO instruction indications. The clock may be
crystal controlled, RC controlled, or driven by an external signal.
On chip serial in/out port is available and controlled by the newly added R 1M and SIM
instructions.
BLOCK DIAGRAM
--Vee
5-16
JlPD8085A
PIN IDENTIFICATION
L
PIN
SYMBOL
NO
1,2
I
i
FUNCTION
NAME
X,. X2
Crystal In
Crystal, Re, or external clock Input
3
AO
Reset Out
Acknowledge that the processor
used 85 a system reset
4
SOD
Senal Out Data
1 bit data out by the SIM Instruction
~. '--...:s"'O=--_ _ _+--=Se='...:'O"-::.In...:o:.:a:::,a,-_+_',,-b::':...'d=a",'a:..:,::.n':.:0c.A:.:C:.:C.",blt
I
6
Trap
Trap Interrupt
I
IS
bemg reset to be
7 by the RIM Instruchon
Highest priority nonmaskable restart Interrupt
Input
RST 7 5
RST65
AST 5 5
,0
Restart
Priority restart Interrupt tnputs, of which 7 5 IS the
INTR
INTA
ADO - AD7
i
20
VSS
Ground
I
21·28
AS - A15
High Address Bus
29,33
50. 5 1
Status Outputs
Outputs which indicate data bus status
Read. Fetch
30
ALE
Address latch
Enable Out
A signal which mdlcates that the lower 8-blts of
address are valid on the AD lines
3',32
WA. RD
Write/Read
Strobes Out
34
I
35
Ground Reference
I
!
A signal out whIch Indicates whether AD or WR
strobes are for 1/0 or memory devices
I
An Input which IS used 10 Increase the data and
address bus access times Ican be used for slow
memory)
i
Ready Input
I
36
37
Reset In
i
~
38,39
Halt. Write.
Signals out which are used as wflte and read strobes
for memory and 110 deVices
101M
Ready
Nonmultlplexed high a-bits of the address bus
Reset Input
An Inp... t which IS used to start the processor actIvity
at address O. resetting IE and HlOA flip flops
HOld Acknowledge
Used to request and Indicate that the processor should
relmqUlsh the bu,s for OMA actlvl'y When hold IS
acknowledged. AD. WR. 101M. Address and Data
busses are all 3 stated
CLK
HLDA. HOLD
OUI and Hold
Input Request
!
~~--r~-----+~~~---+~=~~:.:...:c.~=~---------------
I
L-_4_0____L_~~
VCC ______L-_5V
__
S_uP_p_'v________ L_P_o_w_"_S_U_~pp~I~V_I_nc.P_UI____________________~
ABSOLUTE MAXIMUM
RATINGS*
O°C'o +70°C
-65°C to +150°C
Operating Temperature.
Storage Temperature
-0,5 to +7 Volts
, l,5W
Voltage on Any Pin
Power DISSipation
Ta = 25°e; Vee = ±5V ± 5%, 8085A·2
'COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. ThiS is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability ,
DC CHARACTE RISTICS
Ta'
o'c to +70'C, Vee' +5V ± ,0%, Vss - GND. unl... oth.rwlse speCIfied
LIMITS
PARAMETER
SVMBOL
MIN
MAX
UNIT
Inpul low Voltage
VIL
VSS· 05
VSS + 08
V
Input High VOltage
VIH
20
Vee + 0 5
V
Output low Voltage
VOL
Output High Voltage
VOH
Power SUpply Current (VCC)
ICCIAVI
045
24
170
136
TEST
CONDITIONS
V
tOl = 2 mA on alt outputs
V
IOH • -4oo,..s
mA
CD
tCY min (808SA-21
mA
tey mm (8085AH)
Input leakage
I
"0
Q)
.A
0 .... VIN
Output leakage
ILO
"0
(i)
.A
o 45V "
MaXimum Umt Test
Input Low Levet. Reset
VILR
-05
+08
V
Input HI., llvel. Reset
VIHR
24
Vec + 0 5
V
HysteresIs. Reset
VHY
025
Xl. X2 Input Voltage High
VIHX
4,0
Note
V
Vee+0 5
I j f""
Xl
X2
1·6 MHz> 50% DC
Input frequency must be tWice the Internal operatmg frequency
The Status Outputs are valid <:juring ALE time and have the following meaning:
Halt
Write
Read
Fetch
S1
SO
0
0
0
1
0
These pins may be decoded to portray the processor's data bus status.
5-21
",PD8085A
The ,uPD8085A has five interrupt pins available to the user. INTR is operationally the
same as the 8080 interrupt request, three (3) internally maskable restart interrupts:
RESTART 5.5, 6.5 and 7.5, and TRAP, a non·maskable restart.
RESTART
ADDRESS
INTERRUPT
PRIORITY
Highest
INTERRUPTS
TRAP
2416
I
I
RST 7.5
3C16
RST 6.5
34 16
I
RST 5.5
2C16
INTR
Lowest
INTR, RST 5.5 and RST 6.5 are all level sensing inputs while RST 7.5 is set on a rising
edge. TRAP, the highest priority interrupt, is non-maskable and is set on the rising edge
or positive level. It must make a low to high transition and remain high to be seen, but
it will not be generated again until it makes another low to high transition.
Serial input and output is accomplished with two new instructions not included in the
8080: RIM and SIM. These instructions serve several purposes: serial I/O, and reading
or setting the interrupt mask.
The RIM (Read Interrupt Mask) instruction is used for reading the interrupt mask and
for reading serial data. After execution of the RIM instruction the ACC content is as
follows:
I I /5
SID
I
SERIAL
DATA
IN
I
M
6.5
6.5
I
I
PENDING
INTERRUPTS
INTERRUPT
MASKS
INTERRUPT
ENABLE
Note: After the TRAP interrupt, the R 1M instruction must be executed to preserve the
status of IE.
The SIM (Set Interrupt Mask) instruction is used to program the interrupt mask and to
output serial data. Presetting the ACC for the SIM instruction has the following
meaning:
M
5.5
R
7.5
I
SERIAL
OUT
DATA
SERIAL
OUT
DATA
ENABLE
(1 = ENABLE)
I
RESET
RST7.5
ENABLE
RST
MASKS
(1 = SEn
MASK
SET
ENABLE
(1 = ENABLE)
5-22
SERIAL I/O
~PD8085A
INSTRUCTION SET
The instruction set includes arithmetic and logical operators with direct, register,
indirect, and immediate addressing modes.
Move, load, and store instruction groups provide the ability to move either 8 or 16 bits
of data between memory, the six working registers and the accumulator uSing direct,
register, indirect, and immediate addressing modes.
The ability to branch to different portions of the program is provided with direct, conditional, or computed jumps. Also, the ability to call and return from subroutines is
provided both conditionally and unconditionally. The RESTART (or single byte call
instruction) is useful for interrupt vector operation.
Conditional jumps, calls and returns execute based on the state of the four testable
flags (Sign, Zero, Parity and Carry). The state of each flag is determined by the result
of the last instruction executed that affected flags. (See Instruction Set Table.)
The Sign flag is set (High) if bit 7 of the result is a "1 "; otherwise it is reset (Low). The
Zero flag is set if the result is "0"; otherwise it is reset. The Parity flag is set if the
modulo 2 sum of the bits of the result is "0" (Even Panty); otherwise (Odd Parity) it
is reset. The Carry flag is set if the last instruction resulted in a carry or a borrow out
of the most significant bit (bit 7) of the result; otherwise it is reset.
In addition to the four testable flags, the I.lPD8085A has another flag (ACY) that is
not directly testable. It is used for multiple precision arithmetic operations with the
DAA instruction. The Auxiliary Carry flag is set if the last instruction resulted in a
carry or a borrow from bit 3 into bit 4; otherwise it is reset_
Double preciSion operators such as stack manipulation and double add instructions
extend both the arithmetic and interrupt handling capability of the I.lPD8085A. The
ability to increment and decrement memory, the six general registers and the accumulator are provided as well as extended increment and decrement instructions to
operate on the register pairs and stack pointer. Further capability is provided by the
ability to rotate the accumulator left or nght through or around the carry bit.
Input and output may be accomplished using memory addresses as I/O ports or the
directly addressed I/O provided for in the I.lPD8085A instruction set.
Two instructions, RIM and SIM, are used for reading and setting the internal interrupt
mask as well as input and output to the serial I/O port.
The special instruction group completes the I.lPD8085A instruction set: NOP, HALT
stop processor execution; DAA provides decimal arithmetic capability; STC sets the
carry flag; CMC complements it; CMA complements the contents of the accumulator;
and XCHG exchanges the contents of two 16-bit register pairs directly.
DATA AND INSTRUCTION
FORMATS
Data in the I.lPD8085A is stored as 8-bit binary integers_ All data/instruction transfers
to the system data bus are in the following format:
1071061051041D31021D,lool
MSB
DATA WORD
LSB
Instructions are one, two, or three bytes long. Multiple byte instructions must be
stored in successive locations of program memory. The address of the first byte is used
as the address of the instruction.
TYPICAL INSTRUCTIONS
One Byte Instructions
Register to register, memory
reference, anthmetlC or logical
rotate, return, pUSh, poP. enable,
Two Byte Instructions
or disable mterrupt instructions
I OP COOE
1071061051041031021D, IDo I OPERAND
tions
10 71
Os
10 51 04 10 3 1°21°, I 00
Immediate mode or 110 instruc-
Three Byte Instructions
I 071 061 051 D4 103 ID2 I 01 I DO I QP CODE
~~or;':;~s~l:u~~.~I~~ct load and
ID71 D61 D51 D41 D31 D21 D, IDO I LOW ADDRESSOR OPERAND'
ID71 D61 D51 D41 D31 D21 D, IDO I HIGH ADDRESS OR OPERAND 2
5-23
-----.---
IAPD8085A
INSTRUCTION SET
TABLE
INSTRUCTION
MNEMONIC!
DESCRIPTION
D7
06
Os
04
cope t
D3
02
0,
INSTRUCTION CODEl
MNEMONIC!
DO
DESCRIPTION
D1
06
05
04
OJ
02
0,
DO
Clode
Cvcles J
LOAD REGISTER PAIR
MOV d ,
MOV M ,
Move 'egl,ter 10 ,,,,,'511"
Move reglsler to memory
MOV d,M
Move memory h) '!!'!Im",
MVI d,08
MVI M,08
Move 'rnmf!d,are 10 reglue.
lo~d ,mmed'~te
1
d
0
0
1
d
d
d
1
1
0
0
0
d
d
1
d
0
1
1
,
0
Move ,mmedrale 10 memory
10
1-'-'-'-=--'-'--'-'-======-'-'---=---'-'-=-=-----1
INCREMENT/DECREMENT
INAd
Incremenlregme.
Decremelltreg,sler
INA M
InCfement memory
0
0
d
LOdd ,mmelhdle reg,sl",
p .. " DE
LXI H,D16
LOdd ,mrned',l1e '''c'~menl DE
OPLf~meol Hl
Oe.:remeotSI .. ck P",nler
o
0
0
0
0
0
0
0
0
1
1
0
ARC
AAe
ROTateAlefl MSB to
carlyI8·b.11
RO!8te A roght LSB '0
cany t8·bl11
Rotale AlefTlh.ough
Clltry19·b,tl
ROlateA flghTlhrough
catry!9·bnl
1
1
0
SlAX B
SlAX 0
lDAX 0
Slo'e A dI
SIOte A dl
LOdd A dt
lo,'ct A dt
STA ADOR
Store A d"et!
1
ADOR ,n
AODR ,n
ADDR ,1'1
ADOR 10
o
BC
DE
BC
DE
o
0
0
o
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
Jump
uocond'loonal
on not zero
on ze.o
on no CoilHY
00 cat!e.
d deSlt08hon reg,ste.
PSW ~ Proce$l.or SUlluS Wo.d
SP ~ Slack Po,ote.
08 - 8b'IdalaQuanl,ty ... press.on,O'
COOSl8nt,8twavsB20f ,nUruc"on
016 16 bll dala Qu/lnhly, e~p'l!$s,on or
"onUant. always BJB20f InSI,uCI.on
AOOR - 16 b" Memo.y addren e~p'l!$s,on
6112
6112
6112
6/12
0
0
6/12
6112
5-24
2dddo. ns - 0008 001 C - 0100 -011 E -100 HlOlL _ tlOMemo.y _ 111 A
JTwoPo$S,blecyclel,mes (7110) mdocale
,nUrucl,oo cycles dependent on cond,l,on
Hags
4.
HagalieCled
Itagr>olallected
o -Uag.eset
1 Haysel
,
c,
",PD8085A
INSTRUCTION CYCLE
TIMES
One to five machine cycles (Ml - M5) are required to execute an instruction. Each
machine cycle involves the transfer of an instruction or data byte Into the processor or
a transfer of a data byte out of the processor (the sole exception being the double add
instructIOn). The first one, two or three machine cycles obtain the Instruction from the
memory or an interrupting I/O controller. The remaining cycles are used to execute the
instruction. Each machine cycle requires from three to five clock times (Tl - T5).
Machine cycles and clock states used for each type of instruction are shown below.
INSTRUCTION
TYPE
MACHINE CYCLES EXECUTED
MIN/MAX
ALU R
CMC
CMA
DAA
DCR R
DI
EI
INR R
MOV R, R
NOP
ROTATE
RIM
SIM
STC
XCHG
HLT
DCX
INX
PCHL
RETCOND.
SPHL
ALU I
ALUM
JNC
LDAX
MVI
MOV M, R
MOV R, M
STAX
CALL CONDo
DAD
DCR M
IN
INR M
JMP
LOAD PAIR
MVIM
OUT
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1/3
1
2
2
2/3
2
2
2
2
2
2/5
3
3
3
3
3
3
3
3
3
3
3
3
pop
RET
PUSH
RST
LDA
STA
LHLD
SHLD
XTHL
CALL
4
4
5
5
5
5
5-25
CLOCK STATUS
MIN/MAX
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
6
6
6
6/12
6
7
7
7/10
7
7
7
7
7
9/18
10
10
10
10
10
10
10
10
10
10
12
12
13
13
16
16
16
18
",PD8085A
A minimum computer system consisting of a processor, ROM, RAM, and
I/O can be built with only 3-40 pin packs_ This system is shown below with
its address, data, control busses and I/O ports_
IlPD8085A FAMILY MINIMUM
SYSTEM CONFIGURATION
VCC
,f
rl
INTERRUPTS
I~
a
I
~
RST 7 5 RST 6 5 RST 5.5 TRAP
XI
.PD8065A PROCESSOR
~
X2
w
ADD - - - - --AD7
ADo
ADI
AD2
AD3
RESET IN
As--- -
--AI5
PORTC
PORTB
1111I11I1
'1111I11111
PORTA
l t tt
SID SOD SI so
111
1I111I
PAo - - - - -- PA7
...::>
Ci>
;l1~IB~ ".... ::lw
""
---
PB7
-,
TIMER
N
.PDBI56 RAM-IIO 1256 X 81
0
...
PCo - - - - - PC 5 PSo
0 00:
....
0
0 .... " 100:
:t :t ! !
......
w
AOo - - - -- AD, U
TIMER
w
I~ ..
....
C( lol~ow
a: _a::
;-- OUT
11
11
1
t
t
DATA
AD4
AD5
AD6
AD7
As
Ag
Al0
A11
A12
All
A14
ADR
A15
ALE
iiD
Wi!
10/fli
RDY
CLK
RESET
r- CON
HOLD
HLDA
INTR
iNTA
::J ~:t::la:: U~ a:2
~I~I~I~
FEATURES OF .PDS065A
MINIMUM SYSTEM
2K 256 1414-
ALE ADO- - - - - AD,
.PD8355 ROM-IIO
uPD8755A PROM-IIO 2K X 8
BYTE ROM
BYTE RAM
INTERVAL TIMER
8·BIT I/O PORTS
6·81T IIO-STATUS
INTERRUPT LEVELS
PAO - - - - - - - - PA7
P8o-- - - - - - - P87
111I
1III11111I
II
II
I
I
PORTA
PORTB
Package Outlines
For Information, see Package Outline Section 7.
Plastic, fl-PD8085ACI AHC
CeramiC, fl-PD8085AD
Cerdip, fl-PD8085AD AHD
8085ADS-REV4-7-83-CAT
5-26
NEe
"PD8086
",PD8086-2*
16-BIT MICROPROCESSOR
DESCRIPTION
FEATURES
The /lPD8086 is a l6-blt microprocessor that has both 8-bit and l6-bit attributes. It
has a l6-bit wide physical path to memory for high performance. Its architecture
allows higher throughput than the 5 MHz /lPD8085A·2.
• Can Directly Address 1 Megabyte of Memory
•
•
•
•
•
•
•
PIN CONFIGURATION
Fourteen l6-Bit Registers with Symmetrical Operations
Bit, Byte, Word, and Block Operations
8-,and l6-Bit Signed and Unsigned Arithmetic Operations in Binary or Decimal
Multiply and Divide Instructions
24 Operand Addressin!! Modes
Assembly Language Compatible with the /lPD8080/8085
Complete Family of ,Components for Design Flexibility
GND
AD14
AD13
AD12
ADll
AD10
AD9
ADB
AD7
AD6
AD5
AD4
AD3
AD2
ADl
ADO
NMI
INTR
eLK
GND
Vee
AD15
A16/S3
A17/S4
A1B/S5
A19/S6
BHE/S7
MN/MX
Ri5
HOLD
HLDA
(RO!G'i'ii)
(ROtGT11
WR
(LOCK)
M/iQ
DTtR
(52)
(Si)
i5EiiI
(SO)
ALE
(OSO)
(OSl)
iiii'i'A
TEST
READY
RESET
·Preliminary
Rev/l
5-27
,..PD8086
NO.
2·16,39
SYMBOL
FUNCTION
NAME
MultIPle.ad add .... (Tl) and da.. IT2, T3, TW, T4) bu•.
S-blt peripheral. tied to the lower 8 bits, use AO to condJtion
chip select functions. These lines are tri~state during interrupt
AOO·ADI5
Address/Deta Bus
NMI
Non-Maskable
This
Interrupt
look-up table Is used by the processor for vectoring
Information.
8cknow~ge
17
IS
and hotel states.
an edge triggered Input causing a type 2 Interrupt.)l
18
INTR
I nterrupt Request
A level triggered Input sampled on the last clock cycle of
each Instruction. Vectoring Is via an interrupt look-up table.
I NTR can mask In software by resetting the interrupt enable
bit.
19
CLK
Clock
The cl()Ck input is 81/3 duty cycle input basic timing for the
processor and bus controller.
21
RESH
R....
This active high signal must be high for 4 clock cycles. When
22
READY
Ready
An acknowledgement from memory or 1/0 that data will be
transferred. Synchronization II done by the ",PD8284 clock
generator.
23
TEST
Test
This input is examined by the "WAIT" instruction. and if
low. execution continues. Otherwise the processor waits In an
"Idle" state. Synchronized by the processor on the ieadi"g
adge of CLK.
24
INTA
Interrupt
Acknowledge
This Is a read strobe for reading vectoring information.
During T2. T3. and TW of each interrupt acknowledge
eycle it is low.
25
ALE
AddresS Latch Enable
This Is used In conjunction with the ",PD8282/8283 latches
to latch the addreu. during T 1 of any bus cycle.
26
DEN
00", E""ble
This is tha output enable for the "P08282/8287 transceivers.
It is active low during each memory and I/O 8CC8ssand
INTAcycles.
27
DTtFi
O,ta Transmit/Receive
it raturnslow, the processor restarts executIOn.
Uted to control the direction of data flow through the
' .. " ....Iv....
28
M/IO
MemQry/IO Status
This is used to separate memory access tram I/O access.
29
WR
Write
Depending on the state of the Mfj"O'"lIrr. the processor is
either writing to I/O or memory.
30
HLDA
Hold Acknowledge
A response to the HOLD input, causing the processor to
tri.state the local bus. The bus return active one cycle after
HOLD goes back low.
31
HOLD
Hold
When another device requaltS the Iocel bus. driving HOLD
high, will cause the PPD8086 to issue a H LOA.
32
RD
Reed
Depending on the state of the M/IO line. the processor is
reading from either memory or I/O.
33
MN/MX
Minimum/Maximum
This input is to tell the processor which mode It Is to be used
in. This effects lOme of the pin detlerlptlons.
34
~/S7
8us/High Enabl.
ThiS is used in conjunction wit~ the most significant half of
the data bUI. Peripheral devices on thil half qf the bus use
SHE to condition chip select functionl.
AI6-At9
Most Significant
Address Bits
The four most significant address jlits for mamory oper.
tionl. Low during I/O operat~.·
So-S7
StatUi Outputs
These ara the status OUtpUtl from the processor. They are
utad by the ",PD8288 to gafler~ bus controllignali.
CSt,OSO
Que StatUI
UIJ.!d to track the Internal ",P08086 instructlOfl que.
LOCK
Lock
Thl. output il set by tha "LOCK" instruction to Pl"8V8(lt
other IY1tIm bUI masten from gaining control.
~§
Req'l"'t/Grant
Other local bus marters can force the processor to reba..
the local bus It the end of the ~rrent bus cycle.
3!h18
26,27,211
34-38
24,25
29
30,31
ROIGTI
5-28
PIN IDENTIFICATION
fjPD8086
BLOCK DIAGRAM
EXECUTION UNIT
BUS INTERFACE UNIT
REGISTER FILE
RELOCATION
REGISTER FILE
DATA,
POINTER, AND
INDEX REGS
(SWORDS)
SEGMENT
REGISTERS
AND
INSTRUCTION
POINTER
(5WORDS)
16-BIT ALU
FLAGS
BUS
INTERFACE
UNIT
DT/Fl, DEN, ALE
6-BYTE
INSTRUCTION
OUEUE
TEST-----r------------~~----------~
LOCK
INT
NMI
OSO,OS1
CONTROL & TIMING
RO/GTO,1
HOLD
HLDA
CLK
5-29
RESET READY MN/MX
GND
Vee
IlPD8086
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . oOe to 700 e
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°e to +150o e
Voltage on Any Pin with Respect to Ground . . . . . . . . . . . . . . . . . . . -1.0 to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5W
ABSOLUTE MAXIMUM
RATINGS*
Ta = 25°C
'COMMENT: Stress above those listed under "Absolute Maximym Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
PARAMETER
SYMBOL
MIN
LIMITS
MAX
UNITS
Input low Voltage
Vil
-0.5
+O.S
V
Input High Voltage
VIH
2.0
VCC +0.5
V
Output Low Voltage
VOL
Output High Voltage
VOH
Power Supply Current
IlPDSOS6/
IlPD80S6·2
ICC
Input leakage Current
III
Output Leakage Current
IlO
Clock Input low Voltage
VCl
Clock Input High Voltage
VCH.
Capacitance of Input Buffer
(All input except
ADO-AD1S. RO/GT)
Capacitance of 110 Suffer
(ADO-AD15. RO/GT)
0.45
2.4
TEST
CONDitiONS
V
10L = 2.5 rnA
V
10H =-400IlA
340
350
rnA
rnA
Ta = 25°C
±10
Il A
OVUTPUT)
M/iO
BH'EfS7. A,1g/SS·A1S/S3
ALE
WOITE CYCLE \
ADtS : : :
iJ)
IRD, iN'fA,
OTfR - VOH)
-I--+-~~I~r-W1I
AD1S-AOS
-1-1-1L-~i!-.l---.,....~---~.v-;:;;;:;;tl~-+----~
DT/A
INTA CYCLE
iJ)@
(RD. iNA .. VOH
BHE" VOL)
SOFTWARE HALT
INVALID ADDRESS
QEN,Ri5,WR.iNi'A ~ VO H
SOFTWARE HALT
TelAV
NOTES:
lMck. TM 8C881ocM ADDR/Date BUI is
floating during both INTA cycles. Control for POinter ~
IS shown for IRond INTA cycM.
® S'IJn8ls at 8284 or 8288 .,. shown few reference onfy.
(J)
I!!!..!...SSU!!!5!,2f 1!!L..828B~~£!!!!!.rolsignalstMiiDC.
MWTe, AMWC,IORC, lOwe. AIOWC,INTA end DEN) legs the active high
8288 CEN
All tmn", rnuturement,.re made at 1.SV un... othetwtII noted.
@
Stetullnactrve in state JUst prior to T4-
@)
5-36
',- _ _ _ _ _
",PD8086
ASYNCHRONOUS SIGNAL
RECOGNITION
CLK
NMI
INTR
NOTE:
SIGNAL ,,:_ _ __
CD
Setup requirements for asynchronous signals only to guarantee recognition
at next CLK.
BUS LOCK SIGNAL TIMING
REQUEST/GRANT SEQUENCE
TIMING*
NOTE:
ROY Hold Time Into
"PD8284
RQ/GT Setup Tlma
Statue ActivI Delay
....._1
~ = 20-100 pF for
all 8088 outputs
and Internal loada
ns
45
ns
10
45
ns
COntrol Inactive
Delay <;ll
tcvNX
Address Float to
READ Active
tAZRl
RD Active Delay
tCLRl
10
165
ns
AD Inactive Delay
tClRH
10
150
ns
RD Inactive to Next
Addl'88l Active
tRHAV
tclCL-45
ns
no
Direction Control
Active Delay
\'-~----'/
All signals switch between VOH and VOL unless otherwise specified.
(J) ROY is sampled near the end of T2, T3, TWAIT to determine if TWAIT machine states are
inserted.
@ The cascade address IS valid between the first and second INTA cycles.
@ Two INTA cycles run back·ta-back. The I'PD8088 local Address/Data bus floats during both
INTA cycles. The control signals shown are for the second INTA cycle.
~ Signals at the I'PD8284 and I'PD8288 are shown for reference.
@ The flbD8288 active-~~h CEN lagwWhen the "PD8288 Issues command and control signals
, IORC, I
C, AIOWC, INTA, and DEN).
(MRD. , MWTC, AM
~ All timing measurements are taken at 1.5V unless otherwise specified.
@ Status is inactive prior 'to T4.
5-45
I-tCHDTH-
tCVNX-
r-
Ir--
~PD8088
Timing Waveforms (Cont.)
Asynchronous Input Recognition
ClK
~~----[
NMI
__
?
------------=>i-....J._
~
INTR
\---------l
_m
SlgnaI!-:
Not..
(j) Setup requirements for asynchronous signal~ guarantee recognition at next elK.
Maximum Mode Bus Lock Signal Timing
r
Any ClK Cyelto
ClK
ICLAV
-------11
------
F
j - - - - - A ny ClK Cycle
------/
tClAV
lOCKI-----
-
Maximum Mode RequesVGrant Sequence Timing
Any CLK Cycle
CLK
tGVCH
r---+---- tcHGX
tClGl
AI9iSs-Al&1S3
p_~_vm_u._~_m
...
I
_____
""-.a
0
A15-A8
AD7-AOO
~
_ _ _ _I>--_ _ _ _
~~.>----------""\
. . .
Coprocessor
Gl
>--_ _ _ _ _ _ _ _- J
II
12.81. So
1m. I:iia(
Noto,
(j) The coprocessor risks bus conten!ion if it drives the buses outside the areas shown.
5-46
tclGH
tcuu
r----i
~D8088
' -_ _....
!-,PD8088
Timing Waveforms (Cont.)
Mimimum Mode Hold Acknowledge Timing
\
ClK
..._
~"'ClKCyCI'
~_J-J~ttHHVVCC~HGl
,
HOLD
~.I---~rt --~,----t_+__tClHA-V~
tCLHAV
____
1--
u
....
HLDA
tClAZ
Coprocessor
Note:
(!) All signals switch between VOH and VOL unless otherwise specified.
Package Outlines
For information, see Package Outline Section 7.
Cerdip, fLPD8088D
8088DS-REV1·7 ·83-CAT
5-47
Notes
5-48
NEe
PERIPHERALS
iii
NEe
J.1PD765A/ J.1PD7265
SINGLE/DOUBLE DENSITY
FLOPPY DISK CONTROLLER
Description
The J.LPD765A is an LSI Floppy Disk Controller (FDG) chip
which contains the circuitry and control functions for interfacing a processor to 4 floppy-disk drives. It is capable of
supporting either IBM 3740 Single Density format (FM), or
IBM System 34 Double Density format (MFM) including
double-sided recording. The J.LPD765A provides control
signals which simplify the design of an external phase
locked loop and write precompensation circuitry. The FDC
simplifies and handles most of the burdens associated with
implementing a floppy-disk interface.
The fiPD7265 is an addition to the FDC family that has
been designed specifically for the Sony Micro Floppydisk®
drive. The J.LPD7265 is pin-compatible and electrically
equivalent to the 765A but utilizes the Sony recording format. The J.LPD7265 can read a diskette that has been
formatted by the J.LPD765A.
Hand-shaking signals are provided in the J.LPD765AI
J.LPD7265 which make DMA operation easy to incorporate
with the aid of an external DMA Controller chip, such as the
J.LPDS257. The FDC will operate in either the DMA or nonDMA mode. In the non-DMA mode the FDC generates
interrupts to the processor every time a data byte IS to be
transferred. In the DMA mode, the processor need only
load the command into the FDC and all data transfe(s
occur under control of the FDC and DMA controllers.
There are 15 commands which the J.LPD765A/flPD7265
will execute. Each of these commands requires multiple
S-bit bytes to fully specify the operation which the processor wishes the FDC to perform. The following commands
are available:
READ DATA
READID
SPECIFY
READ TRACK
SCAN EQUAL
SCAN HIGH OR EQUAL
SCAN LOW OR EQUAL
READ DELETED DATA
WRITE DATA
FORMAT TRACK
WRITE DELETED DATA
SEEK
RECALIBRATE
SENSE INTERRUPT STATUS
SENSE DRIVE STATUS
o
o
o
o
o
o
Data Transfers in DMA or Non-DMA Mode
Parallel Seek Operations on Up to Four Drives
Compatible with J.LPDSOSO/S5, flPDSOS6/SS and
J.LPD7S0 (ZSO'") Microprocessors
Single Phase Clock (S MHz)
+5VOnly
40-Pin Plastic Package
", zao IS a registered trademark of 2110g Inc
MIcro Floppydlsk@ IS a registered trademark of Sony Corporation
Block Diagram
Registers
WRClock
WR Data
WR Enable
Serial
Interface
Controller
Preshlf.O
Preshl,.1
ORO
OACK
INT
AD
WR
Ready
Write Protectl
Ao
TwoS.de
Index
Reset
CS
Unit Select 0
Drive
Interface
Controller
Unit Select 1
MFM Mode
II
ClK
RYlISeek
Vee
Head Load
GNO
Head Select
Low Current!
Direction
Fault Reset/Step
Features
Address Mark detection circuitry is internal to the FDC
which simplifies the phase locked loop and read electronics. The track stepping rate, head load time, and
head unload time are user-programmable. The J.LPD765AI
J.LPD7265 offers additional features such as multitrack and
multiside read and write commands and single and double
density capabilities.
Sony (EMCA) Compatible Recording Format
(J.LPD7265)
IBM-compatible Format (Single and Double Density)
(J.LPD765A)
Multisector and Multitrack Transfer Capability
Drive Up to 4 Floppy or Micro Floppydisk® Drives
Data Scan Capability-Will scan a single sector or an
entire cylinder comparing byte-for-byte host memory
and disk data
o
o
o
o
o
Absolute Maximum Ratings*
T. _ 25'C
Operating Temperature
Storage Temperature
All Output Voltages
All Input Voltages
Supply Voltage Vee
Power Dissipation
._".-
--._"'
-10'C to + 70'C
- 40'C to + 12S'C
-O.Sto +7V
-O.Sto +7V
-O.Sto +7V
---1W
- - - - -"-----
*COMMENT: Exposing the device to stresses above
those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be
operated under conditions outside the limits described
in the operational sections of this specification. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Revl1
6-1
Pin Identification
f.LPD765A/7265
Pin
--;;,.::.-."';S;::.=m:;:b=.;-,;;';"'""7.
N=am=e--- I 0
RESET
RD
Vcc
RW/SEEK
iNA
LCT/DIR
CS
FA/STP
A,
HDL
DB,
DB,
DB,
RST
Reset
Processor
Places FDC In Idle state Resets
output lines to FDD to 0 (low)
Does not affect SRT, HUT or
HLT In Specify command If
ROY pin IS held high dUring
Reset, FDC Will generate an
Interrupt Within 1 024 msec To
clear this Interrupt use Sense
Interrupt Status command
Read
I
3:
Processor
Control signal for transfer of
data from FDC to Data Bus,
when 0 (low)
Write
I 1--
Processor
Control signal for transfer of.
data to FDC via Data Bus, when
a (low)
flDY
WP/TS
FLT/TRo
PS,
DB,
DB,
CS
PS,
DB,
DB,
De,
US,
US,
DRQ
HD
DACK
Data Bus
ORO
Data DMA
Request
WE
15
INT
1/0 '1~ Processor
DMA Request IS being made by
FDC when DRO = 1
DACK
DMA
DMA cycle IS active when 0
(low) and controller IS perform,ng DMA transfer.
16
TC
Terminal Count
DMA
Indicates the termmatlon of a
DMA transfer when 1 (high) It
terminates data transfer during
Read/Wr,te/Scan command ,n
DMA or Interrupt mode
17
lOX
Index
FDD
Indicates the beginning of a
disk track
o
RD
RoW
Bldlrectlonal8-blt Data Bus
DMA
Acknowledge
VCO
CLK
GND
IC selected when 0 (low), allowIng RD and WR to be enabled
Selects Data Reg (Ao 1) or
Status Reg (Ao=O) contents of
the FDC to be sent to Data Bus
OMA
14
MFM
TC
lOX
Processor
Chip Select
Data/Status
Reg Select
WDA
Function
Connects To
Pin Configuration
WCK
o
INT
Interrupt
19
CLK
Clock
T. = -10'Cto +70'«;;
.
.
Vee = + 5V ± 5% ul'liess otherWise specified
20
GND
Ground
DC power return
500 KHz, MFM = 1 MHz, With a
pulse Width of 250 ns for both
Parameter
Input Low Voltage
Limits
SymbOI~M~m---lY==p~@~~~M~a.--V1L
Input Low Voltage
(CLK + WR Clock)
VIL(~)
~~~ ~ifJ~~:::)
V1H($)
-0.5
Test
Conditions
Vee
150
+05
V
mA
III
(All Input Pins)
High Level Output
Leakage Current
'LOti
_
_
Low Level Output
Leakage Current _.',!:Q.L..___
_ _ _ _ ~,. _ _ _ !::~___ ,,~~L=__
-10
ycc _" __ _
WCK
Write Clock
22
ROW
Read Data
Window
Phase
Lock Loop
Generated by PLL, and used to
sample data from FDD
23
ROD
Read Data
FDD
Read data from FDD. containing
clock and data bits
Phase
Locked Loop
Inhibits VCO In PLL when 0
(law), enables VCO when 1
24
VCOI
Sync
VCO/Sync
25
WE
Write Enable
o
o
FDD
Enables write data IOta FDD
26
MFM
MFM Mode
o
Phase
Lock Loop
MFM mode when 1, FM mode
when 0
27
HD
Head Select
o
FDD
Head 1 selected when 1 (high),
Head 0 selected when 0 (low)
28, 29
~~~'
Unit Select
o
FDD
FDD Unit selected
30
WDA
Wnte Data
o
FDD
Senal clock and data bits
to FCC
o
FDD
Wnte precompensabon status
during MFM mode Determines
early, late, and normal times
FDD
Senses FCD fault condition In
Read:Wnte mode, and Track 0
condition In Seek mode.
Senses Wnte Protect status In
Read,Wnte mode, and Two-Side
Media In Seek mode
Precompen31, 32 PS" PSo satlon
(preshl!t)
_~.~OUT ~~~~ __
Note: CD TYPical values for Ta -"'- 25°C and nominal supply voltage
Capacitance
T.
21
FM and MFM
.~--,0c:..5_ _ _ _ _
0._65
_ _ _ _V_ __
24
33
FLTfTRo FaultiTrack 0
34
WP/TS
Wnte Protect!
Two Sld~
FDD
35
ROY
Ready
FDD
Indicates FDC IS ready to send
or receive data
= 25'C;fc = 1MHz;Vee = OV
Limits
Parameter
Symbol Min Typ Max
Single phase 8 MHz squarewave clock
Write data rate to FOD FM
08
Vee Supply curre:'"cc'-",lc"eC_ __
Input Load Current
Unit
Processor
~~e;D6t Request generated
18
DC Characteristics
Test
Unit
Conditions
36
HDL
Head Load
o
FDD
Command which causes read
write head In FDC to contact
diskette
37
FRISTP
Fit Reset/Step
o
FDD
Resets fault FF In FCD In Read
Wnte mode, contains step
pulses to move head to another
cylinder In Seek mode
o
FoD
lowers Write current on Inner
tracks In Read/Write mode,
determines direction head Will
step In Seek mode A fault reset
pulse IS Issued at the beginning
of each Read or Write command
prior to the occurrence of the
Head Load signal
o
FDC
When 1 (high) Seek mode
selected and when 0 (low)
Read/Wnte mode selected
Clock Input
capacltanc:~ec-_ _ _ _ _~CC"N","(''L')_
Input Capacitance
C1N
Output Capacitance
COUT
38
39
RW I
SEEK
Read Write .
Seek
40
Vee
+5V
Note: CD Disabled when CS = 1
6-2
CC power.
AC Characteristics
f.LPD765A/7265
T.= -10"Cto+70"Cj
Vee = + 5V ± 5% unless otherwise specified
Timing Waveforms
Limits
Symbol
Parameter
Test
Min TypCD Max
120
125
Conditions
Unit
Processor Read Operation
500
125
Clock Period
"CY
Clock Active (High)
<1>0
Clock Rise Time
"r
20
ns
Clock Fall Time
"I
20
ns
Ag, CS, DACK Se'up Time
'oRO j
'A_
ns
250
8"FDD
5'/4" FDD
Ao. CS, DACK
3 1/2" Sony
125
40
RD
'0'
Data
ns
Ao. es, DACK Hold Time
from RD t
RDWidth
Data Access Time from
10WR
WRWldlh
Data Setup Time to WR
t
t
Data Hold Time from WR
INT Delay Time from RD
i
INT Delay Time from WR
''_-0-
250
'0'
20
C L =100pf
100
ns
CL = 100 pF
t
low
150
j Delay
ns
500
ns
500
ns
200
ns
'MA
DACKWldlh
1M
TC Width
Reset Width
ITe
tRST
Data
ns
IWI
t Mey
WR
ns
,_,'wo
lAM
eS
13
ns
200
I.j.lc),-125 ns
(bR
eS
80
ns
20
ns
100
ns
20
100
ns
20
100
ns
"
Preshlft Delay Time
fromWCK i
Icp
20
WCK 1 ~ WE
tewE
leo
tROO
_1'
twCy--j
Note: Either polarity data window IS valid
Terminal Count
Reset
Reset
H
~ ~ST
Data InlOut
(010)
Internal Registers
Out FOC and InlO Processor
\VA
AD
The f-LPD765A/f-LPD7265 contains two registers which may
be accessed by the main system processor: a Status Register and a Data Register The 8-bit Main Status Register
contains the status information of the FDC, and may be
accessed at any time. The 8-blt Data Register (which actually consists of several registers m a stack with only one
register presented to the data bus at a time), stores data,
commands, parameters, and FDD status information Data
bytes are read out of, or written mto, the Data Register In
order to program or obtain the results after a particular
command. Only the Status Register may be read and used
to facilitate the transfer of data between the processor and
f-LPD765/f-LPD7265.
The relation~ between the Status/Data registers and the
signals RD, WR, and Ao is shown below.
,
-----0---
-~~O------O-
_~1___ ~ __ ~~-1
1
WR
1
0
~-.-
Notes:
Function
Read Mam Status Register
-1iiOg~.I--·--~··-~·---
Illegal
Indicates Data Register IS ready to send or receIVe data to or from the processor. Both bits 010 and ROM should
be used to perform the hand-shaking functions of
"ready"~~~"dlrectlon" ~~_~~E~~~~~: _____ _
Out Processor and Into FOC
RequeslforMaster
(ROM)
RD
A read or write command IS In process. FOC Will not
accept any other command.
The DIO and ROM bits in the Status Register indicate when
data is ready and in which direction data Will be transferred
on the data bus. The maximum time between the last RD or
WR during a command or result phase and DIO and ROM
getting set or reset is 12 f-LS. For this reason every time the
Main Status Register IS read the CPU should wait 12....1:!:.§.
The maximum time from the trailing edge of the last RD
In the result phase to when DB4 (FDC busy) goes low
is 12 f-Ls.
ReadData~
Ao
FOO number 2 IS In the Seek mode. If any of the bits IS
set FOC Will not _~ccept read or write comm~.!'~: ___ _
FOO number 3 IS in the Seek mode. If any of the bits IS
set FOC Will not accept read or write command.
Output
FDD Read Operation
Read Data Wmdow
IS
__ set FOe Will not !~~~t read o~_!,,~e command. __~ ___ _
---'''---'
Step
oo
Description
Symbol
FDD number 0
the Seek mode. If any of the bits
DoB set
FOC Will not accept read or write command
DB, "FD"'D'1·B"uc::.: "yC- -......D,"B -----.=1)0 number 1 IS In -tile Seek mode:--iianyof the bits IS
RW/Seek
Direction
Name
_" _______.._~----===
_ _~~~ __ ~_
0
.----~--
6~4
L-
I
Ready
I
: :
I~
I
Not
I I
: I
I
I II
I
IReadyllllllll!
I
I
I
I
u I
I I
I
I
I
I
I
I I I
I II
\
~I
I A I BI A IBI A I C I Die IDIBI A I
[!] - Data register ready to be written mto by processor
00 - Data register not ready to be written Into by processor
lID - Data register ready for next data byte to be read by processor
[QJ - Data register not ready to be read by processor
j-lPD765A17265
Status Register Identification
Bit
No.
Name
Description
Symbol
Status Register Identification (Cont.)
Bit
No.
Status Reglste, 0
Dr = OandD6 = 0
IC
D,
SE
Equipment
D, Check
EC
D, Not Ready
NR
WP
RY
ThiS bit Is used to Indicate the status of the Ready signal
from the FOD.
~-1and06-0
D, Track 0
TO
This bit Is used to Indicate the status of the Track 0
signal from the FDO.
D, lWo Side
TS
This bit is used to Indicate the status of the lWo Side
signal from the FDD.
D, Head Address
0 7 = 1andD6-1
Abnormal Termination because during command execution the ready signal from FOD changed state.
When the FOC completes the SEEK command, this flag
IS set to 1 (high).
If a fault signal is received from the FOD, or if the Track 0
signal fails to occur after 77 step pulses (Aecahbrate
Command) then this flag is set.
When the FDD is In the not-ready state and a read or
:m: ~~:!!::~~:: :::~~'t~~~:~ ~ :~i~~~er:~ge~
D, Head Address
HD
This flag is used to Indicate the state of the head at
Interrupt.
D, Unit Select 1
US,
!!II
USg
These flags are used to indicate a Drive Umt Number
at Interrupt.
EN
When the FOC tries to access a sector beyond the final
sector of a cylinder, this flag is set.
Ds Data Error
DE
When the FOC detects a CRCG) error In either the 10 field
or the data field, this flag is set.
D, Overrun
OR
If the FOC Is not serviced by the host system during data
transfers within a certain time interval, this flag
Status Register
0, End of Cylinder
D,
t
Not used. This bit Is always 0 (low).
IS
D,
set.
Not used. ThiS bit always 0 (low).
~~~~l~xce:~:ann:' :~~OF~~T:a~:~~~~~:::c~~ATA
specified In the IOR® Register, this flag is set.
D, No Data
ND
During execution of the READ 10 command, if the FOC
cannot read the 10 field without an error, then this flag
is set.
During execution of the READ A cylinder command, If
the starting sector cannot be found, then thiS flag is set.
D, Not Writable
NW
Address
D, Missing
Mark
MA
During execution of WRITE DATA, WRITE DELETED
DATA or Format A cylinder command, If the FDC detects
a write protect signal from the FDO, then this flag is set.
H the FOe cannot detect the 10 Address Mark after
encountering the Index hole twice, then this flag Is set.
H the FDC cannot detect the Data Address Mark or
Deleted Data Address Mark, this flag IS set. Also at the
same time, the MO (Missing Address Mark In data field)
of Status Register 2 is set.
Status Register 2
0,
Not used. This bit Is always 0 (low).
CM
~~~!'~Dce;~~~t!'nfe:~: =~r~1~:~:;:I~;~~:re~
DD
If the FDC detects a CRC error In the data field then thiS
flag Is set.
D, Wrong Cylinder
WC
This bit is related to the NO bit, and when the contents of
C@ on the medium is different from that stored in the
lOR. this flag is set.
D, SCan Equal Hit
SH
During execution of the SCAN command, if the condition
of "equal" is satisfied. this flag is set.
D, Scan Not Satisfied SN
During execution of the SCAN command, if the FDC cannot find a sector on the cylinder which meets the
condition, then thiS flag is set.
D, Bad Cylinder
BC
This bit Is related to the NO bit, and when the contents of
C on the medium Is different from that stored in the lOR
and the contents of e is FF(16)' then this flag is set.
MD
When data is read from the medium, if the FOC cannot
find a Data Address Mark or Deleted Data Address Mark,
then this flag is set.
D, Control Mark
Data Address Mark, this flag IS set.
Ds
Data Error in
Data Field
Missing
D, Address Mark
In Data Field
ThiS bit is used to Indicate the status of the Fault signal
from the FDD.
ThiS bit is used to mdlcate the status of the Write Protected signal from the FOO.
Ds Ready
drive, then this flag is set.
Unit Select 0
FT
D, Write Protected
Invalid Command Issue, (IC~ Command which was
issued was never started.
Ds Seek End
0, Fault
Abnormal Termination of command, (AT). Execution of
command was started but was not successfully
completed.
~=OandD6-1
Interrupt Code
Description
Symbol
Status Register 3
Normal Termination of command, (NT). Command was
completed and properly executed.
D,
Name
HD
ThiS bit IS used to indicate the status of the Side Select
signal to the FOD
D,
Unit Select 1
US,
This bit IS used to indicate the status of the Umt Select 1
signal to the FOD.
D,
Unit Select 0
US,
This bit IS used to mdicate the status of the Umt Select 0
signal to the FOD.
Notes: CD CRC = Cyclic Redundancy Check
@ IDR= Internal Data Register
® Cyhnder (C) IS described more fully In the Command Symbol Descrlpton on page 7
Command Sequence
The f-LPD765A/f-LPD7265IS capable of performing 15 different commands. Each command is Initiated by a multlbyte
transfer from the processor, and the result after execution
of the command may also be a multi byte transfer back to
the processor. Because of thiS multibyte Interchange of
information between the f-LPD765A/f-LPD7265 and the
processor, it is convenient to consider each command
as consisting of three phases:
Command
The FDC receives all Information
Phase:
required to perform a particular operation from the processor.
The FDC performs the operation It was
Execution
Phase.
Instructed to do.
Result Phase. After completion of the operation, status
and other housekeeping information are
made available to the processor
FollOWing are shown the required preset parameters and
results for each command. Most commands require 9 command bytes and return 7 bytes dUring the result phase The
"W'. to the left of each byte Indicates a command phase
byte to be written, and an "R" Indicates a result byte
6-5
I-LPD765A/7265
.......
DahI.u.
Ph•••
Command
RIW
W
W
W
W
W
W
W
W
W
Remarks
D7 DI DR DS Da DI D! DR
Reed_.
MY MF SK 0 0
1
1
0 Command Codes
X
X
X
-
Instruction Set
Instruction Set CD ®
X
X
Command
HD US, Us" @
Sector 10 Information prior
to command execution. The
C
H
R
N
I
EDT
I
4 bytes are commanded
agaI1181 h _ , on Floppy
Disk.
GPL
DTL
Data transfer between the
Execution
W
W
W
W
W
W
W
W
W
Date Bus
DZ DI DR DS Da D. D, DR
Remarks
WrIt. Deleted_
MT MF
X
X
0
X
0
X
1
X
C
H
R
N
0
0
1 Command Code.
HD US, Us"
Sector 10 InfOrmation Prior
to command execution. The
4 byte. are commanded
against header on Floppy
EDT
DIll<.
GPL
DTL
Data transfer between the
Execution
FDD and main system
_uR
Command
STO
STI
STZ
C
H
R
N
_Del _ _
R
R
R
R
R
R
R
W
W
W
W
W
W
W
W
W
MT MF SK
X
X X
X
command executton
Sector 10 Information after
command execution
1
1
0 Command Codes
0
X HD US, US.
C - - - - - Sector 10 InformatIOn prior
H
to command execution. The
4 bytes are commanded
R
N
against header on FlOPPY
EDT
FDD and main system
_uR
Status Information after
Command
Disk.
GPL
DTL
execution
Data transfer between the
R
R
R
R
R
R
R
W
W
W
W
W
W
W
W
W
~--
0
X
MF SK
X X
STO
STI
STZ
C
H
R
N
0
Status Informadon after
command execution
I
Reed A Track
0
0
1
X
X
C
H
R
N
0 Command Codes
HD US, Us"
Sector 10 Information prior
I to command execution
EDT
GPL
DTL
Execution
Data transfer between the
FDO and main system FOC
reads all data fteids from
index hole to EOT.
FDD and ma.n system
ReouR
Command
STO
STI
ST2
C
H
R
N
Write_
R
R
R
R
R
R
R
W
W
W
W
W
W
W
W
W
MY MF
X
X
0
X
0
X
X
C
H
R
N
EDT
Notes:
RaBuH
1
0
1 Command Codes
HD US, Us"
Sector 10 Information prior
to command execution. The
4 bytes are commanded
against header on Floppy
Disk.
GPL
DTL
Execution
_uR
Status InformaHon after
command execution
Sector 10 InformatIOn after
command execution
STO
STI
ST2
C
H
R
N
STO
STI
ST2
C
H
R
N
R
R
R
R
R
R
R
Sector 10 Information after
command execution
W
W
0
X
MF
X
0
X
0
X
1
X
0
1
0 Command Codas
HD US, Us"
Execution
Result
Status Information after
command execution
The first correct 10
Information on the cylinder
IS Blored 1ft Data Register.
STO
STI
STZ
C
H
R
N
R
R
R
R
R
R
R
Sector 10 information after
command execubon
Status Informal1on after
command execubon
Sector 10 Information read
during Execution phase from
Floppy Disk.
Format A Track
Command
R), and the scan operation IS continued. The scan operation continues until one of the following conditions occur:
the conditions for scan are met (equal, low, or high), the last
sector on the track IS reached (EaT), or the terminal count
signal is received.
Comment.
DFDD
= Dprocessor
DFDD
< Dprocessor
Scan Low
or Equal
FF
C8
OA
Command
74
Table 1
@
@
shows the status of bits SH and SN under various conditions of Scan.
Status Register 2
lA
OF
08
04
02
01
lA
OF
08
04
02
01
31/2" Sony Microfloppy
128 bytes/sector
0
OF
FM Mode
GPLCD
Table 2
If the FDC encounters a Deleted Data Address mark on
one of the sectors (and SK = 0), then it regards the sector
as the last sector on the cylinder, sets the CM (Control
Mark) flag of Status Register 2 to a 1 (high) and terminates
the command. If SK = 1, the FDC skips the sector with the
Deleted Address mark and reads the next sector. In the
second case (SK = 1), the FDC sets the CM (Control Mark)
flag of Status Register 2 to a 1 (high) In order to show tnat a
Deleted sector had been encountered.
When either the STP (contiguous sectors = 01, or alternate sectors = 02) sectors are read or the MT (Multitrack)
is programmed, It IS necessary to remember that the last
sector on the track must be read. For example, If STP =
02, MT = 0, the sectors are numbered sequentially 1
through 26 and the Scan command IS started at sector 21,
the following will happen: Sectors 21, 23, and 25 will be
read, then the next sector (26) will be skipped and the Index
hole will be encountered before the EaT value of 26 can
be read. ThiS will result in an abnormal termination of the
command. If the EaT had been set at 25 or the scanning
started at sector 20, then the Scan command would be
completed in a normal manner.
During the Scan command, data IS supplied by either the
processor or DMA Controller for comparison against the
data read from the diskette. In order to aVOid haVing the OR
(Overrun) flag set In Status Register 1, It is necessary to
have the data available In less than 27 f1s (FM mode) or 13
f1s (MFM mode). If an Overrun occurs, the FDC ends the
command with bits 7 and 6 of Status Register 0 set to 0
and 1, respectively.
Seek
The Read/Write head within the FDD is moved from cylinder to cylinder under control of the Seek command. FDC
has four independent Present Cylinder Registers for each
drive. They are cleared only after the Recalibrate command. The FDC compares the PCN (Present Cylinder
Number) which is the current head position with the NCN
(New Cylinder Number), and if there is a difference, performs the following operations:
PCN < NCN: Direction Signal to FDD set to a 1 (high), and
Step Pulses are issued. (Step In)
If the conditions for scan are met, then the FDC sets the
PCN > NCN: Direction Signal to FDD set to a 0 (low), and
SH (Scan Hit) flag of Status Register 2 to a 1 (high) and
Step Pulses are Issued. (Step Out)
terminates the Scan command. If the conditions for scan
The rate at which Step pulses are Issued is controlled by
are not met between the starting sector (as specified by R)
SRT (Stepping Rate Time) in the Specify command. After
and the last sector on the cylinder (EaT), then the FDC
each Step pulse is issued NCN is compared against PCN,
sets the SN (Scan Not Satisfied) flag of Status Register 2 to
and when NCN = PCN, the SE (Seek End) flag is set in
a 1 (high) and terminates the Scan command. The receipt
Status Register 0 to a 1 (high), and the command is termiof a Terminal Count signal from the processor or DMA connated. At this point FDC interrupt goes high. Bits DoB-D3B
troller during the scan operation will cause the FDC to
in the Main Status Register are set during the Seek operacomplete the comparison of the particular byte which IS In
tion and are cleared by the Sense Interrupt Status
process and then to terminate the command. Table 2
command.
6 -11
fJ-PD765A17265
Sense Interrupt Status
An Interrupt signal is generated by the FDC for one of the
following reasons:
1. Upon entering the Result phase of:
a. Read Data command
b. Read A Track command
c. Read ID command
d. Read Deleted Data command
e. Write Data command
f. Format A Cylinder command
g. Write Deleted Data command
h. Scan commands
2. Ready Line of FDD changes state
3. End of Seek or Recalibrate command
4. During Execution phase in the non-DMA mode
Interrupts caused by reasons 1 and 4 above occur during
normal command operations and are easily discernible by
the processor. During an execution phase in non-DMA
mode, DB5 in the Main Status Register IS high. Upon entering the Result phase thiS bit gets cleared. Reasons 1 and 4
do not require Sense Interrupt Status commands. The interrupt is cleared by Reading/Writing data to the FDC. Interrupts caused by reasons 2 and 3 above may be uniquely
identified with the aid of the Sense Interrupt Status command. This command when issued resets the Interrupt
signal and via bits 5, 6, and 7 of Status Register 0 identifies
the cause of the interrupt.
During the command phase of the Seek operation the
FDC is in the FDC Busy state, but during the execution
phase it is in the Nonbusy state. While the FDC is in the
Nonbusy state, another Seek command may be issued,
and in this manner parallel Seek operations may be done
on up to four drives at once. No other command can be
issued for as long as the FDC is in the process of sending
step pulses to any drive.
If an FDD is in a Not Ready state at the beginning of the
command execution phase or during the Seek operation,
then the NR (Not Ready) flag is set in Status Register 0 to a
1 (high), and the command is terminated after bits 7 and 6
of Status Register 0 are set to 0 and 1 respectively.
If the time to write three bytes of Seek command exceeds
150"",s, the timing between the first two step pulses may
be shorter than set in the Specify command by as much
as 1ms.
Recalibrate
The function of this command is to retract the Read/Write
head within the FDD to the Track 0 position. The FDC
clears the contents of the PCN counter and checks the
status of the Track 0 signal from the FDD. As long as the
Track 0 signal is low, the Direction Signal remains 0 (low)
and step pulses are issued. When the Track 0 signal goes
high, the SE (Seek End) flag in Status Register 0 is set to
a 1 (high) and the command is terminated. If the Track 0
signal is still low after 77 step pulses have been issued, the
FDC sets the SE (Seek End) and EC (Equipment Check)
flags of Status Register 0 to both 1s (highs) and terminates
the command after bits 7 and 6 of Status Register 0 are set
to 0 and 1 respectively.
The ability to do overlap Recalibrate commands to multiple
FDDs and the loss of the Ready signal, as described in the
Seek command, also applies to the Recalibrate command.
If the Diskette has more than 77 tracks, then Recalibrate
command should be issued twice, in order to pOSition the
Read/Write head to the Track O.
Seek, Recalibrate, and Sense Interrupt Status
Interrupt Code
Seek End
Bit 6
1
BitS
eaus.
Bit 7
Ready Line changed state, either polarity
Normal Termination of Seek or Recalibrate
command
Abnormal Termination of Seek or Recallbrate command
Table 3
The Sense Interrupt Status command IS used In conJunction with the Seek and Recalibrate commands which have
no result phase. When the disk drive has reached the
desired head position the f.LPD765A/f.LPD7265 Will set the
Interrupt line true. The host CPU must then Issue a Sense
Interrupt Status command to determine the actual cause
of the interrupt, which could be Seek End or a change In
ready status from one of the drives. A graphiC example
is shown:
: - - - Seek (or Recahbrate) Command ---~- Sense Interrupt Status Command - :
I--- Command Phase ---t- Execution Phase _ f - . Command Phase -1- Result Phase-I
INT
:
:
I
I
r--,
:
~
I
I
A,
@
""1LJD un LJ ffi
:
I
un.
r-~,-------,
I
I
I
I
I
1Jn. urn.
I
WR~r--------'Ir----------
U
OIOtr--uu
J[
J[
ROM
,g:5
c
8E~~
&£~s
6-12
~§
~
c
~
-cUe
0,.
~
"z
~~~
OE3:
VI"''''
.;t
~£c::2
~
z
~~E
VI
~ g'm
~
.c
"~
'"z
"'"
fj-PD765A/7265
Specify
The Specify command sets the initial values for each of the
three internal timers. The HUT (Head Unload Time) defines
the time from the end of the execution phase of one of the
Read/Write commands to the head unload state. This timer
is programmable from 16 to 240ms in increments of 16ms
(01 = 16ms, 02 = 32ms ... OF '6 = 240ms). The SRT
(Step Rate Time) defines the time interval between adjacent step pulses. This timer IS programmable from 1 to 16
ms in increments of 1 ms (F = 1ms, E = 2ms, D = 3ms,
etc.). The HlT (Head load Time) defines the time between
when the Head load signal goes high and the Read/Write
operation starts. This timer IS programmable from 2 to 254
ms in increments of 2 ms (01 = 2ms, 02 = 4ms, 03 =
6ms ... 7F = 254ms).
The time intervals mentioned above are a direct function of
the clock (GlK on pin 19). Times indicated above are for an
8MHz clock; If the clock was reduced to 4MHz (minifloppy
application) then all time intervals are Increased by a factor
of 2.
The choice of a DMA or non-DMA operation is made by
the ND (Non-DMA) bit. When this bit IS high (ND = 1) the
Non-DMA mode IS selected, and when ND = 0 the DMA
mode IS selected.
Sense Drive Status
This command may be used by the processor whenever It
wishes to obtain the status of the FDDs. Status Register 3
contains the Drive Status information stored internally in
FDG registers.
Invalid
If an Invalid command is sent to the FDG (a command not
defined above), then the FDG Will terminate the command
after bits 7 and 6 of Status Register 0 are set to 1 and 0
respectively. No interrupt is generated by the fLPD765A/
fLPD7265 dUring this condition. Bits 6 and 7 (DIO and.
ROM) in the Main Status Register are both high (1), Indicating to the processor that the fLPD765A/fLPD7265 IS In the
Result phase and the contents of Status Register 0 (STO)
must be read. When the processor reads Status Register
o it will find an 80 hex, indicating an Invalid command
was received.
A Sense Interrupt Status command must be sent after
a Seek or Recalibrate Interrupt, otherwise the FDG Will
consider the next command to be an Invalid command.
In some applications the user may wish to use this command as a No-Op command to place the FDG in a standby
or No Operation state.
fLPD765A (FM Mode)
GAP4a
40,
FF
SYNC
6,
00
lAM
GAP1
26,
SYNC
FC
FF
00
Index~
fLPD7265 (FM Mode)
6,
lOAM
FE
C
Y
L
H
D
S
E N
C 0
C
R
C
GAP2
11>
FF
DATA AM
SYNC
DATA
6,
(j)
00
C
GAP3
R
(j)
GAP 4b
C
FB or F8
I------------Repeat NTlmes------------j
~--,-,---,----,-~--,-,--~m
Index ~----------RepeatNTlmes------------I
fLPD765A (MFM Mode)
Index~
1-------------RepeatNTlmes-------------l
fLPD7265 (MFM Mode)
lOAM
GAP1
SYNC
32,
4E
12,
00
Index~
3,
A1
I
FE
C
Y
L
H
D
S
E N
C 0
C
R
C
GAP2
22,
4E
DATA AM
SYNC
12,
00
3,
A1
I
DATA
Fa
F8
(j)
C
R
GAP3
(j)
C
1------------RepeatNTlmes--------------j
6-13
GAP4
,""PD765A17265
iLPD765A
I
Format
GAP4a
10
GAP1
lAM
GAP2
DATA
GAP3
10 ((
I
GAP4b
I
;,i----'---'
VcoSYNC
WE
t
r------,\
r
.,.PD7265
Index
~--------------------~{~
I
Format
VcoSVNC
GAP2
DATA
GAP3
10
GAP2
10 ((
I
I
GAP4
i ,/----'----'
- -_ _--'\---<...1 _____~
WE
Note:
GAP1 110
I
,------"'"'\
,
Read
Write
Notea: It IS suggested that the user refer to the followmg applicatIon notes
Modem and Sync
Controls
Internal Data and Control Bus
f---
CS
RD
WR
Channel
A
Serial
Data
and
Control
Logic
I
4 DMA Request
Lines
I
PRI PRO
Interrupt Control
Logic
I
f
INT
INTA
~
Channel
B
Serial
Data
and
Control
Logic
.
} Serial Data
}
¢
Serial Data
Clocks
Modem and Sync
Controls
~
"a.....
...oJ>
iii)
m
~PD7201A
Programming the MPSC2
The software operation of the MPSC2 is very straightforward. Its consistent register organization and high-level
command structure help minimize the number of operations required to implement complex protocol designs.
Programming is further simplified by the MPSC2'S extensive interrupt and status reporting capabilities. This section
is divided into two parts.
The MPSC2 Regilters
The MPSC2 interfaces to the system software with a number of control and status registers associated with each
channel. Commonly used commands and status bits are
accessed directly through control and status registers O.
Other functions are accessed indirectly with a register
pointer to minimize the address space that must be dedicated to the MPSC2.
Control Register
Control
Register
o
Function
Frequently used commands and register pointer control
Interrupt control
Processor/bus Interface control
RacINV8r control
Mode control
Transmitler control
Sync/address character
Sync character
Status Register
Status
Raglster
o
Function
Buffer and "external/status" status
Received character error and special condrtlon status
2
(Channel
Booly)
Interrupt vector
Tx byte count register, low byte
Tx byte count register, hIgh byte
All control and status registers except CR2 are separately maintained for each channel. Control and status
registers 2 are linked with the overall operation of the
MPSC2 and have different meanings when addressed
through different channels.
When initializing the MPSC2 control register 2A (and 2B
if desired) should be programmed first to establish the
MPSC2 processor/bus interface mode. Each channel
may then be programmed to be used separately, beginning with control register 4 to set the protocol mode for
that channel. The remaining registers may then be
programmed in any order.
Control Register 0
Register pOinter (Do - O2 )
The register pointer specifies which register number is
accessed at the next control register write or status register
read. After a hardware or software reset the register pointer
is set to zero. Therefore, the first control byte goes to control register O. When the register pointer is set to a value
other than zero the next control or status (C/O = 1) access
is to the specified register, after which the pointer is reset to
zero. Other commands can be freely combined in control
register 0 by setting the register pointer.
Commands (03 - 0 5 )
Commands commonly used during the operation of the
MPSC2 are grouped in control register O. They include
the following:
Null (000): This command has no effect and is used only
to set the register pointer or issue a CRC command.
Send abort (001): When operating in the SOLC mode this
command causes the MPSC2 to transmit the SOLC abort
code, issuing 8 to 13 consecutive ones. Any data
currently in the transmitter or the transmitter buffer is
destroyed. After sending the abort the transmitter reverts
to the idle phase (flags). When using the Tx byte count
mode enable (06 of CR1), and an underrun condition
occurs, the f,LP07201A will automatically issue the send
abort command.
Reset external status interrupts (010): When the
external/status change flag is set, the condition of bits
0 3 - 0 7 of status register 0 are latched to allow the capture of the short pulses that may occur. The reset external/
status interrupts command reenables the latches so
that new Interrupts may be sensed.
Channel reset (011): This command has the same effect
on a single channel as an external reset at pin 2. A channel
reset command to channel A resets the internal interrupt
prioritization logic. This does not occur when a channel
reset command is issued to channel B. All control
registers associated with the channel to be reset must be
reinitialized. After a channel reset, wait at least four system
clock cycles before writing new commands or controls to
that channel.
Enable interrupt on next chliracter (100): When operating the MPSC2 in an interrupt on first received character
mode this command may be issued at any time. This com,mand must be issued at the end of a message to reenable
the interrupt logic for the next received character (the first
character of the next message).
Reset pending transmitter interrupt/OMA request
(101): A pending transmitter buffer becoming empty interrupt or DMA request can be reset without sending another
character by issuing this command (typically at the end of a
message). A new transmitter buffer becoming empty interrupt or OMA request is not made until another character
has been loaded and transferred to the transmitter shift
register or when, If operating in the synchronous or SOLC
modes, the first CRC character has been sent.
Error Reset (110): This command resets a special receive
condition interrupt. It also reenables the parity and overrun
error latches that allow errors at the end of a message to
be checked.
6-18
j.LPD7201A
End of interrupt (111) (channel A only): Once an interrupt request has been issued by the MPSC2 all lower
priority internal and external interrupts in the daisychain are
held off to permit the current interrupt to be serviced while
allowing higher priority interrupts to occur. At some point in
the interrupt service routine (generally at the end), the
end of Interrupt command must be issued to channel A to
reenable the dalsychain and allow any pending lower prlonty internal interrupt requests to occur. The EOI command
must be sent to channel A for Interrupts that occurred on
either channel.
CRC Control Commands (Os - 0 7 )
The following commands control the operation of the CRC
generator/checker logic.
Null (00): This command has no effect and is used when
issuing other commands or setting the register pointer.
Reset receiver CRC checker (01): This command resets
the CRC checker to zero when the channel is in a synchronous mode and resets to all ones when in an SDLC
mode.
Reset transmitter CRC generator (10): This command
resets the CRC generator to zero when the channel is in
a synchronous mode and resets to all ories when in an
SDLC mode.
Reset idle/CRC latch (11): This command resets the idle/
CRC latch so that when a transmitter underrun condition
occurs (that is, the transmitter has no more characters to
send), the transmitter enters the CRC phase of operation
and begins to send the 16-blt CRC character calculated up
to that point. The latch is then set so that If the underrun
condition persists, Idle characters are sent follOWing the
CRC. After a hardware or software reset the latch IS in
the set state. This latch is automatically reset after the
first character has been loaded into the Tx buffer in the
SDLC mode.
Control Register 1
D,
D,
D,
Walt
Function
Enable
Tx Byte
Count
Mode
Enable
Walton
Receiver
Transmitter
D,
D,
D,
D,
I
D,
Receiver
Interrupt
Mode
D,
D,
Do
Condition Transmitter Ext/Status
Interrupt
Affects
INT
Vector
Enable
Enable
D,
D,
D,
D,
Low Byte
D,
D,
D,
High Byte
External/status interrupt enable (00 )
When this bit is set to one the MPSC2 Issues an interrupt
whenever any of the following conditions occur:
Transition of the DCD input pin
Transition of the CTS input pin
Transition of the SYNC Input pin
Entering or leaving synchronous hunt phase,
break detection or termination
SDLC abort detection or termination
Idle/CRC latch becoming set (CRC being sent)
After ending flag is sent in the SDLC mode
Transmitter interrupt enable (01)
When this bit is set to one the MPSC2 issues an interrupt when:
1) The character currently in the transmitter buffer is
transferred to the shift register (transmitter buffer
becoming empty) or,
2) The transmitter enters the idle phase and begins
transmitting sync or flag characters.
3) The Tx byte mode enable bit is set (CR1 - D6 = 1).
The 7201A will automatically issue a Tx interrupt
or DMA request when the transmitter becomes
enabled (CR5 - D3 = 1).
Condition affects vector (02 ) (programmed
in channel B for both channels)
When this bit is set to zero the fixed vector programmed
in CR2B during MPSC2 initialization is returned in an
interrupt acknowledge sequence. When this bit is set to
one the vector is modified to reflect the cOfldition that
caused the interrupt.
Receiver interrupt mode (0 3 - 0 4 )
This field controls how the MPSC2'S InterruptiDMA logic
handles the character received condition.
Receiver interrupts/OMA request disabled
(00)
The MPSC2 does not issue an interrupt or a DMA request
when a character has been received.
InterruptlOMA on first received character
only (01)
In thiS mode the MPSC2 issues an interrupt only for the first
character received after an enable interruptiDMA on first
character command (CRO) has been given. If the channel
is In a DMA mode, a DMA request is issued for each character received including the first. This mode generally is used
whenever the MPSC2 is in a DMA or block transfer mode.
This wi II signal the processor that the beginning of an
incoming message has been received.
Interrupt (and issue a OMA request) on all
received characters (10)
In this mode an interrupt (and DMA request if the DMA
mode IS selected) is issued whenever there IS a character
present In the receiver buffer. A panty error is considered
a speCial receive condition.
Interrupt (and issue a OMA request) on all
received characters (11)
ThiS mode is the same as the one above except that a
parity error is not considered a speCial receive condition.
The follOWing are considered special receive conditions:
Receiver overrun factor
Asynchronous framing error
Parity error (If specified)
SDLC end of message (final flag received)
Wait on receiver/transmitter (05)
If the wait function is enabled for block mode transfers,
setting this bit to zero causes the MPSC2 to Issue a wait
(WAIT output goes low) when the processor attempts to
write a character to the transmitter while the transmitter
buffer IS full. Setting this bit to one causes the MPSC2 to
issue a wait when the processor attempts to read a character from the receiver while the receiver buffer IS empty.
6-19
m
•
f.LPD7201A
Interrupt vector mode (03 - 05)
This field determines how the MPSC2 responds to an interrupt acknowledge sequence from the processor.
Tx byte count mode enable (06 )
Each channel has a 16-bit Tx byte count register used for
automatic transmit termination. When this bit is set to one
the next two consecutive command cycle writes will be to
the byte count register. The first byte is loaded into the
lower 8 bits and the second to the upper 8 bits of the byte
count register. The byte count register holds the number of
transfers to be performed by the transmitter. A byte counter
is incremented each time a transfer is performed until the
value of the byte counter is equal to the value In the byte
count register. When equal, interrupts or DMA requests will
be stopped until the byte count enable bit is issued and a
new byte count is loaded Into the byte count register. If a
transmit underrun occurs In the SDLC mode, and the byte
count is not equal to the byte count register, the abort
sequence will be. ~ent automatically.
Also, when using the Tx byte count mode, a transmit interrupt or DMA request will automatically become active after
issuing the Tx enable command to CRS.
The Tx byte count mode can be cleared by either a channel
reset command or a hardware reset.
Rx INT mask (06 )
This option IS generally used in the DMA modes. Enabling
this bit Inhibits the interrupt from occurring when the interruptlDMA Request On First Received Character mode IS
selected. In other words, only a DMA request Will be generated when the first character is received.
Wait function enable (07 )
Setting this bit to one enables the wait function which is
described in CR1.
Pin 10 SYNCB/RTSB select (07 )
Programming a zero into this bit selects RTSB as the
function of pin 10. A one selects SYNCB as the function.
Control Register 2 (Channel A)
Control Register 2 (Channel B)
I
0,
D.
Pm10
RxlNT
SVNCBlRTSB
Mask
I
0,
I
I
D.
0,
Interrupt Vector Mode
I
0,
I
I P"o,,~ I
0,
I
D.
DMAMode
DMA Mode Selection
Channel
DR
0
0
A
•
0
o
0
o
Nonvectored
Nonvectored
Nonvectored
Illegal
8085 Master
8085 Slave
8086
8085/8259A Slave
I
0,
0,
0,
D.
0,
0,
0,
D.
Interrupt Vector
Interrupt vector (Do - 0 7 )
When the MPSC2 is used In the vectored Interrupt mode
the contents of thiS register is placed on the bus during the
appropriate portion of the interrupt acknowledge sequence.
Its value IS modified if status affects vector is enabled. The
value of SR2B can be read at any time. This feature is
particularly useful In determining the cause of an Interrupt
when using the MPSC2 in a nonvectored interrupt mode.
Control Register 3
Pin Function
11
Status Register 28 and Interrupt Vector
Bits Affected When Condition Affect. Vector
Is Enabled
I
Select
OMA mode select (Do - 0 1 )
Setting this field determines whether channel A or B is
used in a DMA mode (Le., data transfers are performed by
a DMA controller) or in a non-DMA mode where transfers
are performed by the processor in either a polled, interrupt,
or block transfer mode. The functions of some MPSC2 pins
are also controlled by this field.
D.
Interrupt Acknowledge Sequence Response
29
30
31
32
Non·DMA Non-DMA WAITS DTRB
PRI
PRO
DTRA WAlTA
DMA Non·DMA DRQTxA HAl
PRI
PRO
HAO DRQRxA
DRQTxA HAl DRQRxB DRQTxB HAO DRQRxA
DMA
DMA
DRQTxA DTRB DRQRxB DRQTxB DTRA DRQRxA
DMA
DMA
2fI
0,
I
D.
Number of Received
Bits per Character
0,
D.
Auto
Enter
Hunt
Phase
Enables
0,
0,
0,
Sync
Address Character
Receiver
Search
Load
CRC Enable Mode
Inhibit
D.
Receiver
Enable
Priority (02 )
This bit selects the relative priorities of the various interrupt
and DMA conditions according to the application
requirements.
Receiver enable (Do)
After the channel has been completely initialized, setting
this bit to one allows the receiver to begin operation. This
bit may be set to zero at any time to disable the receiver.
DMAllnterrupt Priorities
Sync character load inhibit (01 )
In the character synchronous modes, this bit inhibits the
transfer of sync characters to the receiver buffer thus performing a "sync-stnpping" operation. When using the
MPSC2'S CRC checking ability this feature should be used
only to strip leading sync characters preceding a message
since the load inhibit does not exclude sync characters
embedded in the message from the CRC calculation. Synchronous protocols using other types of block checking
such as checksum or LRC are free to strip embedded sync
characters with this bit.
D2
Mode
Channel A Channel B
DMAPriorit,
Relation
Interrupt Priority Relation
SRxA. RxA > TxA > SRxB, RxB
0
1
0
1
INT
INT
DMA
INT
>
Txe > ExTA > ExTB
SRxA, RxA > SRxB, RxS > TxA >
TxB > ExTA > ExTB
RxA>TxA
SRxA, RxA > SRxS, RxB > TxB >
ExTA> ExTB
RxA>TxA
SRxA, RxA > SRxB, RxB > Txe >
ExTA> ExTB
0
1
DMA
DMA
RxA > TxA > RxB > SAxA. RxA > SRxB, Rxe > ExTA >
TxB
ExTB
RxA > RxB > TxA > SRxA. RxA > SRxB, RxB > ExTA >
Txe
ExTB
6-20
ILPD7201A
Address search mode (0 2 )
Parity even/odd (0 1)
In the SOLC mode, setting this bit places the MPSC2
in an address search mode. Character assembly does
not begin until the 8-blt character (secondary address
field) follOWing the starting flag of a message matches
either the address programmed Into CR6 or the global
address 11111111.
Programming a zero Into thiS bit when panty is enabled
causes the transmitted parity bit to take on the value
required for odd parity. The received character is checked
for odd parity. Conversely, a one in this bit signifies even
panty generation and checking.
Receiver CRC enable (0 3 )
This field specifies whether the channel is used In a
synchronous (SOLC) or an asynchronous mode. In an
asynchronous mode this field also specifies the number of
bit times used as the stop bit length by the transmitter. The
receiver always checks for one stop bit.
Number of stop bits per sync mode (0 2
ThiS bit enables and disables (1 = enable) the CRC
checker In the COP mode allowing characters from the
CRC calculation to be selectively included or excluded.
The MPSC2 features a one-character delay between the
receiver shift register and the CRC checker so that the
enabling or disabling takes effect with the last character
transferred from the shift register to the receiver buffer.
Therefore, there is one full character time in which to
read the character and decide whether or not It should
be Included in the CRC calculation. In the SOLC mode,
there IS no 8-blt delay.
-
03)
Stop Bits
_~~,!~~~~~~_1_~~~~_~~_es (1"~~~~~!~ _ _ _ _ _
~~~~~~.~~~:.blt tlmes_(2 stop bl_~ _ _ _ _ _ _ _ _
Sync mode (0 4
Enter hunt phase (04 )
Although the MPSC2 receiver automatically enters the sync
hunt phase after a reset, there are times when reentry may
be desired, such as when It has been determined that synchronization has been lost or, in an SOLC mode, to Ignore
the current Incoming message. Writing a one into this bit at
any time after initialization causes the MPSC2 to reenter
the hunt phase.
-
05)
When the stop bits/sync mode field is programmed for
synchronous modes (0 2, 0 3 = 00), this field specifies
the particular synchronous format to be used. This field
is ignored in an asynchronous mode.
Synchronous Formats
Sync
Sync
Mode 1 Mode 2
---
_0_ _ ~ _ _ ~~I!,.!!!:nal s!~ronlzatlo~ char!cter (monosync)
Auto enables (05 )
__
0 _ _ _ _ _ ~ _____
1~~~n~~~!~.~omz~tlOn5haracter (bisync)
SDLC
Setting this bit to one causes the OCO and CTS
Inputs to act as enable inputs to the receiver and transmitter, respectively.
- , _.., - - - -1
Clock rate (0 6 - 0 7 )
Number of received bits per character
(0 6 - 0 7 )
This field specifies the number of data bits assembled to
make each character. The value may be changed on the fly
while a character is being assembled and, if the change is
made before the new number of bits has been reached it
affects that character. Otherwise the new specifications
take effect on the next character received.
Received Bits per Character
This field specifies the relationship between the transmitter
and receiver clock inputs (TxC, RxC) and the actual data
rates at TxO and RxO. When operating in a synchronous
mode a 1x clock rate must be specified. In asynchronous
modes any of the rates may be specified, however, with a 1x
clock rate the receiver cannot determine the center of the
start bit. In thiS mode, the sampling (rising) edge of
RxC must be externally synchronized with the data.
Clock Rates
- - - _o.
_._,,--_._---_._---_._._.._ _ _ _ _ _ _
"s,_"__"._,,
Control Register 4
0,
I
0,
Clock Rate
I
0,
I
I
Clock
Rate 2
07
D6
Clock Rate
a . _ -a - _ . _ - - - _._._-_._-Clock Rate - 1x Data Rate
_
.-----
o - - - - - --c-----------=--------i
_ _----'._ _ _ _ _...:.1
Clock
Rate 1
----
Bits per Character
-_----'.-
External synchronization (SYNC pm becomes an Input)
o
1
1
0
Clock Rate:::: 16x Data Rate
-,-,----,-----
_--'---_ _1
--
Clock Rate - 32x Data Rate
----------~-~.
----------
________________ ~~_~_~~te =:,64X Data Rate _ __
Control Register 5
0,
Sync Mode
I
I
0,
I
0,
Numbe, of Slop Bits
per Sync Mode
I
0,
0,
Panty
Even/Odd
Panty
I
0,
DTR
Enable
Parity enable (Do)
Setting thiS bit to one adds an extra data bit containing
panty information to each transmitted character. Each
received character is expected to contain this extra bit
and the receiver parity checker is enabled.
0,
I
0,
Number of Transmitted
Bits per Character
0,
Send
Break
0,
0,
CRC
Transmitter
Polynomial
Enable
Select
0,
0,
RTS
Transmitter
CRC
Enable
-
Transmitter CRC enable (Do)
A one or a zero enables or disables respectively, the CRC
generator calculation. The enable or disable does not take
effect until the next character IS transferred from the transmitter buffer to the shift register, thus allowing specific
characters to be included or excluded from the CRC calculation. By setting or resetting this bit just before loading
6-21
j.LPD7201A
the next character, it and subsequent characters are
included or excluded from the calculation. If this bit is zero
when the transmitter becomes empty the MPSC2 goes to
the idle phase regardless of the state of the idle/CRC latch.
Transmitted Bits per Character
Transmitted
Bits per
Character 1
Transmitted
Bits per
Character
Bits per Character
5 or less (see below)
RTS (0,)
In synchronous and SOLC modes setting this bit to one
causes the RTS pin to go low while a zero causes it to go
high. In an~nchronous mode setting this bit to zero does
not cause RTS to go high until the transmitter is completely
empty. This feature facilitates programming the MPSC2 for
use with asynchronous modems.
CRC polynomial select (0 2 )
This bit selects the polynomial used by the transmitter and
receiver for CRC generation and checking. A one selects
the CRC-16 polynomial (X16 + X15 + X2 + 1). A zero
selects the CRC-CCITT polynomial (X16 + X12 + x5 + 1).
In an SOLC mode CRC-CCITT must be selected. Either
polynomial may be used in other synchronous modes.
Normally each character is sent to the MPSC2 rightjustified and the unused bits are ignored. However, when
sending five bits or less the data should be formatted as
shown below to inform the MPSC2 of the precise number .
of bits to be sent.
.
Transmitted Bits per Character for
5 Characters or Less
D7
1
D.
1
D.
1
Do
1
D2
0
D,
0
0,
0,
Transmitter enable (0 3 )
0,
After a reset the transmitted data output (TxO) is held high
(marking) and the transmitter is disabled until this bit is set.
In an asynchronous mode TxO remains high until data is
loaded for transmission.
In synchronous and SOLC modes the MPSC2 automatically enters the idle phase and sends the programmed
sync or flag characters.
When the transmitter is disabled in an asynchronous mode
any character currently being sent is completed before TxO
returns to the marking state.
If the transmitter IS disabled during the data phase in a
synchronous mode the current character is sent. TxO then
goes high (marking). In an SOLC mode the current character is sent, but the marking line following is zero-inserted.
That is, the line goes low for one bit time out of every five.
The transmitter should never be disabled during the SOLC
data phase unless a reset is to follow immediately. In either
case, any character in the buffer register is held.
Disabling the transmitter during the CRC phase causes the
remainder of the CRC character to be bit-substituted with
the sync (or flag). The total number of bits transmitted is
correct and TxO.goes high after they are sent.
If the transmitter is disabled during the idle phase the
remainder of the sync (flag) character is sent. TxO then
goes high.
D3
0
0,
03
0,
0,
0,
0,
.0,
D.
Number of Bits per Characte'
D.
D.
Do
D.
Do
OTR (data terminal ready) (0 7 )
When this bit is one the OTR~ut is low (active). Con
versely, when this bit is zero OTR is high.
Control Register 6
0,
0,
0,
0,
D.
Sync Byte 1
Sync byte 1 (Do - 0 7 )
Sync byte 1 is used in the following modes:
Monosync
8-bit sync character transmitted
during the idle phase
Bisync
Least significant (first) 8 bits of
the 16-bit transmit and receive
sync character
External Sync Sync character transmitted during the
idle phase
SOLC
Secondary address value matched to
secondary address field of the SOLC
frame when the MPSC2 is in the
address search mode
Control Register 7
0,
Send break (04)
0,
0,
0,
0,
Do
Sync Byte 2
Setting this bit to one immediately forces the transmitter
output (TxO) low (spacing). This function overrides the
normal transmitter output and destroys any data being
transmitted although the transmitter is still in operation.
Resetting this bit releases the transmitter output.
Sync byte 2 (Do - 0'7)
Transmitted bits per character (05 - 0 6 )
This field controls the number of data bits transmitted in
each character. The number of bits per character may be
changed by rewriting this field just before the first character
is loaded to use the new specification.
Sync byte 2 is used in the following modes:
Monosync 8-bit sync character matched by
the receiver
Bisync
Most significant (second) 8 bits of the 16bit transmit and receive sync characters
SOLC
The flag character, 01111110, must be
programmed into control register 7 for flag
matching by the MPSC2 receiver
6-22
/J-PD7201A
Status Register 0
D,
Breakl
Abort
D,
Idle/CRe
D;
CTS
D,
Sync
Status
D,
D,
Transmitter
DCD
Buffer
Empty
D,
Interrupt
Pending
Do
Received
Character
Available
Received character available (0 0 )
When this bit is set it indicates that one or more characters in the receiver buffer is available for the processor to
read. Once all the available characters have been read the
MPSC2 resets this bit until a new character IS received.
Interrupt pending (01 - channel A only)
The interrupt pending bit is used with the interrupt vector
register (status register 2) to make it easier to determine
the MPSC2'S interrupt status, particularly in a nonvectored
interrupt mode where the processor must poll each device
to determine the interrupt source. In this mode inte~t
pending is set when status register 2B is read, the PRI
input is active (low), and the MPSC2 is requesting interrupt service.
The status registers of both channels need not be analyzed
to determine if an interrupt is pending. If the status affects
vector is enabled and the interrupt pending is set the vector
read from SR2 contains valid condition information.
In a vectored interrupt mode interrupt pending is set during
the interrupt acknowledge cycle (on the leading edge of the
second INTA pulse) when the MPSC2 is the highest priority
device requesting interrupt service (PRI is active). In either
mode if there are no other pending interrupt requests interrupt pending is reset when the end of the interrupt
command is issued.
Transmitter buffer empty (0 2 )
This bit is set whenever the transmitter buffer is empty
except during the transmission of CRC. (The MPSC2 uses
the buffer to facilitate this function.) After a reset the buffer
is considered empty and transmit buffer empty is set.
External/status flags (0 3 -0 7 )
The following status bits reflect the state of the various conditions that cause an external/status interrupt. The MPSC2
latches all external/status bits whenever a change occurs
that would cause an external/status interrupt (regardless of
whether thiS interrupt is enabled). This allows transient
status changes on these lines to be captured with relaxed
software timing requirements.
When the MPSC2 is operated in an interrupt-driven mode
for external/status interrupts, status register 0 should be
read when this interrupt occurs and a reset external/status
interrupt command issued to reenable the interrupt and
the latches. To poll these bits without interrupts, the reset
external/status interrupt command can be issued to first
update the status to reflect the current values.
OCO (03 ): This bit reflects the inverted state of the
OCO input. When OCO is low the OCO status bit is high.
Any transition on this bit causes an external/status interrupt request.
Sync status (04 ): The meaning of this bit depends on the
operating mode of the M PSC2.
Asynchronous mode: Sync status reflects the inverted
state of the SYNC input. When SYNC is low, sync status
is high. Any transition on this bit causes an external/status
interrupt request.
External synchronization mode: Sync status operates in
the same manner as an asynchronous mode. The MPSC2'S
receiver synchronization logic is also tied to the sync status
bit in an external synchronization mode and a low-to-high
transition (SYNC input going low) informs the receiver that
synchronization has been achieved and character assembly begins.
A low-to-high transition on the SYNC input indicates
that synchronization has been lost and is reflected both
in the sync status becoming zero and the generation of
an external/status interrupt. The receiver remains in the
receive data phase until the enter hunt phase bit in
control register 3 is set.
Monosync, bisync, SOLC modes: In these modes, sync
status indicates whether the MPSC2 receiver is in the sync
hunt or receive data phase of operation. A zero indicates
that the MPSC2 is in the receive data phase and a one
indicates that the MPSC2 is in the sync hunt phase (as after
a reset or a setting of the enter sync hunt phase bit). As in
the other modes a transition on this bit causes an external/
status interrupt to be issued. It should be noted that entering a sync hunt phase after either a reset or when
programmed causes an external/status interrupt request
which may be cleared immediately with a reset external/
status interrupt command.
CTS (05): This bit reflects the inverted state of the
CTS input. When CTS is low, the CTS status bit is high.
Any transition on this bit causes an external/status interrupt request.
Idle/CRC (06 ) (Tx underrun/EOM): This bit indicates the
state of the idle/CRC latch used in the synchronous and
SOLC modes. After a hardware reset this bit is set to one,
indicating that the transmitter is completely empty. When
the M PSC2 enters idle phase it automatically transmits
sync or flag characters.
In the SOLC mode the MPSC2 automatically resets thiS
latch after the first byte of a frame is written to the Tx buffer.
When the transmitter IS completely empty, the MPSC2
sends the 16-blt CRC character and sets the latch again.
An external/status interrupt IS Issued when the latch is set,
Indicating that CRC IS being sent. No Interrupt is Issued
when the latch is reset.
Break/abort (07 ): In the asynchronous mode this bit Indicates the detection of a break sequence (a null character
plus framing error that occurs when the RxO input is held
low, spacing, for more than one character time). Break/
abort is reset when RxO returns high (marking).
In the SOLC mode, Break/abort indicates the detection of
an abort sequence when seven or more ones are received
in sequence. It is reset when a zero is received.
Any transition of the break/abort bit causes an external/
status interrupt.
Status Register 1
D,
End of
SOLe Frame
6-23
D,
CRC
Framing
Error
D;
D,
Overrun
Panty
Error
Error
D,
I
D,
I
SOLe ReSidue Code
D,
D,
All Sent
II
•
fJ-PD7201A
When any of these conditions occur and interrupts are
enabled, the MPSC2 issues an interrupt request. In addition, if a condition affects vector mode is enabled, the
vector generated (and the contents of SR2B for nonvectored interrupts) is different from that of a received
character available condition. Thus, it is not necessary to
analyze SR1 with each character to determine if an error
has occurred.
As a further convenience, the parity error and receiver overrun error flags are latched. That is, once one of these errors
occurs, the flag remains set for all subsequent characters
until reset by the error reset command. With this facility SR1
need only be read at the end of a message to determine if
either of these errors occurred anywhere in the message.
The other flags are not latched and follow each character
available in the receiver buffer.
Parity error (04 ): This bit is set and latched when parity
is enabled and the received parity bit does not match the
sense (odd or even) calculated from the data bits.
Receiver overrun error (05): This error occurs and is
latched when the receiver buffer already contains three
characters and a fourth character is completely received,
overwriting the last character in the buffer.
CRClframing error (06 ): In the asynchronous mode a
framing error is flagged (but not latched) when no stop bit is
detected at the end of a character (i.e., RxO is low one bit
time after the center of the last data or parity bit). When this
condition occurs, the MPSC2 waits an additional one-half
bit time before sampling again so that the framing error is
not interpreted as a new start bit.
In the synchronous and SOLC modes this bit indicates the
result of the comparison between the current CRC result
and the appropriate check value and is usually set to one
since a message rarely indicates a correct CRC result until
correctly completed with the CRC check character. Note
that a CRC error does not result in a special receive condition interrupt.
End of SOLC frame (EOF) (0 7 ): This status bit is used
only in the bit synchronous mode to indicate that the end of
frame flag has been received and that the CRC error flag
and residue code are valid. This flag can be reset at any
time by issuing an error reset command. The MPSC2 also
automatically resets this bit when the first character of the
next message frame is sent.
All sent (Do)
This bit is set when the transmitter is empty and reset when
a character is present in the transmitter buffer or shift register. This feature simplifies the modem control software
routines. In the bit synchronous mode, this bit will be set
when the ending flag pattern is sent.
SOLC residue code (01 - 0 3 )
Since the data portion of an SOLC message can consist of
any number of bits and not necessarily an integral number
of characters, the MPSC2 features special logic to determine and report when the end of frame flag has been
received, the boundary between the data field and the CRC
character In the last few data characters that were just read.
When the end of frame condition is indicated, that is, status
register 1 0 7 = 1 and special receive condition interrupt (if
enabled), the last bits of the CRC character are in the
receiver buffer. The residue code for the frame is valid in the
status register 1 byte associated with that data character.
(SR1 tracks the received data in its own buffer.)
The meaning of the residue code depends upon the number of bits per character specified for the receiver. The
previous character refers to the last character read before
the end of frame, and so forth.
Residue Codes
8 Bits per Character
D~
D.
D,
Previous Character
2nd Previous Character
1
0
0
0
CCCCCCCC
CCCCCCCC
CCCCCCCC
CCCCCCCC
CCCCCCCC
CCCCCCCC
CCCCCCCD
CCCCCCDD
CCCCCDDD
CCCCDDDD
CCCDDDDD
CCDDDDDD
CDDDDOOD
DDDDDODD
DDDDDDDD
DDDDDODD
D,
Previous Character
2nd Previous Character
0
CCCCCCC
CCCCCCC
CCCCCCC
CCCCCCC
CCCCCCC
CCCCCCC
CCCCCCD
CCCCCDD
CCCCDDD
CCCDDDD
CCDODDD
CDDDDDD
DDDDDDD
DDDDDDD
0
1
0
0
1
0
1
1
0
0
(no residue)
7 Bits per Character
D. D.
1
0
1
0
0
1
0
1
(no residue)
6 Bits per Character
D.
1
D.
D,
Previous Character
2nd Previous Character
0
0
CCCCCC
CCCCCC
CCCCCC
CCCCCC
CCCCCC
CCCCCC
CCCCCD
CCCCDD
CCCDDD
CCODDD
CDDDDD
DDDDDD
0
1
0
0
0
0
Status Register 28
D,
1
0
0
1
0
0
D,
D,
D,
D,
Interrupt vector (Do - 0 7 - channel B only)
Reading status register 2B returns the interrupt vector that
is programmed into control register 2B. If a condition affects
vector mode is enabled the value of the vector is modified
as shown in the following table.
(no residue)
DDDDD
DDDDD
DDDDD
DDDDD
_ _ _ _ _ _ _ _ 0 _ _ _ _ _ _ _ _ _ _ _ 0 _ _ _ _ __
o
D,
(no ,esldue)
3rd Previous Character
c c cceo0 0 0 0
CCCCD
CCCDD
CCDDD
CDDDD
D,
Interrupt Vector
5 Bits per Character
2nd Previous Character
D,
Special receive condition flags
The status bits described below - parity error (if parity as a
special receive condition is enabled), receiver overrun error,
CRC/framing error, and end of SOLC frame - all represent
special receive conditions.
6-24
j.LPD7201A
Read Register Bit Functions
Condition Affects Vector Modifications
Interrupt
Pending (SRO, Dt
Channel AI
8085 Modes D. D3 D2
8086 Modes D2 D, Do
Read Register 0
Condition
No Interrupt pending
I 0, I 0, I 0, I 0, I 0, I 0, I 0, I Do I
o
0
o
0
Channel B externallstatus change
o
1
Channel B received character available
o
0
1
Channel B transmitter buffer empty
IIU
Channel B special receive condition
o
0
Channel A transmitter buffer empty
o
1
Channel A external/status change
b~guffer Empty }
Sync/Hunt
CTS
Tx Underrun/EOM
Break/Abort
Channel A received character available
Channel A special receive condition
As can be seen code 111 can mean either channel A special receive condition or no interrupt pending. They can be
easily distinguished by examining the interrupt pending bit
(D, ) of status register 0, channel A. In a nonvectored interrupt mode the vector register must be read first for the
interrupt pending to be valid.
Ax Character Available
INT Pendmg (Channel A Only)
Used with
ExternallStatus
Interrupt Mode
Read Register 1(j)
I I I I I I I I I
0,
0,
0,
0,
0,
0,
0,
Do
L
1
0
t
1
1
0
0
0
1
0
1
1
t
0
0
-
I
0
All Sent - Used with External/Status
Interrupt Mode
I-Fie Id
Bits
Previ ous
1
1
1
1
Byt
0
0
0
0
0
0
t
0
2
0
0
0
I·Fleld
Bltsm
Second
PrevIous
Byte
3
4
5
6
7
Residue Data for
Eight Rx Bits per
Character
Programmed
8
8
8
L - Parity Error
}
Ax Overrun Error
CRe/Frammg Error
End of Frame (SOLC)
Read Register 2
VO
I,
I
!
L~
--=~~
"---V3
·-----------·-V4
-=----=== -=-=--= ~~
Interrupt
Vector
--- - - - - - - - - - - - - - - - - - V 7
Notes: CD Used with speCial receive condition mode
® Variable If Status Affects Vector IS programmed
Write Register Bit Functions
Write Register 0
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
POinter for
the Selection of
a Read/Wnte
Register
Null Code
Send Abort (SOLC)
Reset EXT/Status Interrupts
Channel Reset
Enable INT on Next Rx Character
Reset Tx INT/OMA Pending
Error Reset
End of Interrupt (EOI- Channel A only)
Null Code
Reset Rx CRC Checker
Reset Tx CRC Generator
Reset Tx Underrun/EOM Latch
6-25
jJ.PD7201A
Write Register Bit Functions (Cont.)
Write Register 3
Write Register 1
Rx Enable
Sync Character Load Inhibit
EXT INT Enable
Tx INT Enable
Search Mode (SOLe)
L_~===== Address
Rx eRe Enable
L-_ _ _ _ Status Affects Vector
(Channel B only)
EnterEnables
Hunt Phase
L_~======== Auto
Rx tNT and DMA Disable }
Rx INT on First Character
INT on All Rx Characters
(Panty Affects Vector)
tNT on All Rx Characters
Rx5
Rx7
Rx6
RxB
OR Interrupt on
Special Receive
Condition
(Parity Does Not Affect
Bits/Character
Bits/Character
Bits/Character
Bits/Character
Vector)
Walt on RecelverlTransmltter
Tx Byte Count Enable
'-------Walt Enable
Write Register 4
Write Register 2 (Channel B)
Parity Enable
o Parity"" Odd
1 Parity = Even
Sync Modes Enable
1 Stop BltlCharaeter
V1
VO
V3
L~====V2
V5
L~======~
L-=========== ~
11h Stop Bits/Character
2 Stop Bits/Character
}
Interrupt
8-blt Sync Character
16-blt Sync Character
Vector
SOLC
Mode (01111110 Flag)
External Sync Mode
Xl Clock Mode
X16 Clock Mode
X32 Clock Mode
X64 Clock Mode
Tx Byte Count Register
Write Register 5
s.tO
-Bill
W~BII2
Blt3
Low
8114
Byte
Tx CAe Enable
RTS
Blt5
Bit 6
'-----------------BII7
l_~=~====CRC-16/CRC-CCITT
Tx Enable
Send Break
TxS Bits (or LessVCharacter
Tx7 BIts/Character
Tx6 BIts/Character
Tx8 BIts/Character
Tx Byte Count Register
OTR
I~I~I~I~I~I~I~I~I
[I
Lb
Write Register 6
Bit 8
8119
Blll0
81t11
81112
High
Byte
81113
81114
BII15
L ._ _ _ _
SyncB.
tO }
:~~~:::~
l_1=~=k~B~~~~~5Sync
Sync Bit 4
Bit 3
SyncSIIS
Write Register 2 (Channel A)
Address Field
Also SDLC
Sync Bit 6
SyncBrt7
l
Wrne Register 7
o
1
~ode=~g~:~::: g:::=:::~t;~o;~=.
8085 Master M
O
o Priority AxA '> TxA > RxB > TxB
1 Priority RxA > RxB > TxA > Txe
1
1
0
1
1
o
80th Channels Interrupt
Channel A DMA, Channe1 B INT
l
8085 Slave Mode
8086/88 Mode
8085J8269A Slave Mode
Interrupt VectoredlNonvectored
Receive Interrupt Mask
SYNCB
RTSBPln10
Pin 10
}
_1=1::~~~~~~~~~sYnc8It
~~~~:~:
Sync
B.t
11
(j)
Sync Bit 12
10
Sync Bit 13
Sync Bit 14
Sync BI115
Note; GPIB
w
~
09
....
o
<{
I~ I~ I~ ~
Q
<{
III
co
a
co
o
0-
"-
6-41
I- Il
::>....1
III
,....:
o () lii
Ii;
a:
V>
w
a:
III
1
III
Lti
"'
l-
a:
a:
l-
V>
V>
"PD7210
GPIB
MC344BAX4
"P07210
~
~
~
I 5
iill54
0102
DiD,
T/R3 (EOIOE)
'Em
mtv
mml
iiii5Ac'
T/R2 (CIC)
m:r
iJ!!'e'
S/RA_O
PEA-O
OIOB
0107
~:g~
~.--!>
S/RA
OAT<'IA BUSA
S/RB
OATAB 'BUS B
t - - S/RC
OATAC BUSC
' - - - S/Ro
DATA 0 BUS 0
PEA_O
[1>-
EOI
DAV
NRFD
NDAC
S/RA
DATA A
S/RB
OATAB
S/RC
OATAC
S/Ro
DATA 0
L-..-
ATIir
iml
BUSA
BUS B
BUSC
BUS 0
pATAA BUSA
OATAB BUS B
OATAC BUSC
PATAO BUS 0
S/RA-O
PEA-O
i5ii5j
T/RI
DATA A
OATAB
OATAC
DATA 0
.
BUSA
SRO
BUS B
ATN
BUS C
REN
BUS D
PEA-O
IFC
TT
"H""L"
"L"
Note: In this example, high-speed data transfer cannot be made since the bus
transceiver is of the open collector type (Set 82 = 0).
01 B
08
8B
I 7
D7
Os
Os
04
D3
B7
BS
B5
SN75160 B4
B3
B2
91
lii06
Brn5
Iml4
DI03
i5i02
om;
02
01
T/R3 (PE)
PE
"P0721 0
TE
GPIB
T/RI
TE
T/R2 (CIC)
DC
SRO
SRO
ATN
ATN
EOI SN751S1
OAV
NRFO
I
i5Ai7
NFirn
NOAC
F
RE
NOAC
IFC
REN
Note: In the case of low-speed data transfer (82 = 0), the T/R3 pin can be used as a
TRIG output_ The PE input of SN75160 should be cleared to "0_"
6.-42
MINIMUM 8085 SYSTEM
WITH J,LPD7210 (CONT_)
",PD721 0
ABSOLUTE MAXIMUM
RATINGS
(Ta = 25"C)
Symbol
Parameter
Supply Voltage
Input Voltege
Unit
VCC
-0.5 -+ 7.0
V
VI
-0.5 - +7.0
V
Output Voltage
Vo
-0.5 - +7.0
V
Operating Temperature
T opt
Storage Temperatura
DC CHARACTERISTICS
Ratings
Test Conditions
0-+70
-65 - +125
Tstg
·C
·C
(Ta= 0 - +70·C. VCc= 5V ± 10%)
Limits
Parameter
CAPACITANCE
Symbol
Test Conditions
Min
Typ
Max
Unit
Input Low Voltage
VIL
-0.5
+0.8
V
Input High Voltage
VIH
+2.0
VCC+0.5
V
Low Level
Output Voltage
VOL
10L = 2mA
(4 mA : T/R1 Pin)
+0.45
V
High Level
Output Voltage
VOH1
10H =-400"A
(Except I NT)
+2.4
High Level
Output Voltage
liNT Pin)
10H =-400"A
+2.4
VOH2
10H =-50"A
+3.5
Input Leakage
Current
IlL
VIN =OV- VCC
-10
+10
"A
Output Leakage
Currant
10L
VOUT = 0.45V - VCC
-10
+10
"A
Supply Currant
ICC
+180
mA
V
V
(Ta • 25"C. VCC = GND = OV)
Limits
Parameter
Symbol
Test Conditions
Min.
Typ.
Max
Unit
Input Capacitence
CIN
f = 1 MHz
10
pF
Output Capacitence
COUT
All Pins Except Pin Under
Test Tied to AC Ground
15
pF
1/0 Capacitence
ClIO
20
pF
6-43
IlPD7210
(T a = 0 - 70°C, VCC
= 5V
±10%)
AC CHARACTERISTICS
Limlts
Parameter
Symbol
Conditions
~in
Max
Unit
PPSS -+ PPAS, ATN = True
260
ns
EOI. -+T/R1t
tEOTil
PPSS -+ PPAS, ATN
= True
155
ns
EOlt-+T/R14
teoT12
PPAS -+ PPSS, ATN = False
200
ns
ATN. -+ NOAC.
tATNO
AIOS-+ANRS, LIDS
155
ns
ATN. -+T/RH
tATT1
TACS + SPAS -+ TAOS, CIOS
155
ns
ATN. -+T/R2.
tATT2
TAGS
+ SPAS -+ TAOS, CIOS
200
ns
OAW -+ OMAREQ
tOVRQ
ACRS .... ACOS, LACS
600
ns
OAV ..... NRFO.
tOVNR1
ACRS-+ACOS
350
ns
OAW -+ NOACt
tOVN01
ACRS -+ ACOS .... AWNS
650
ns
OAVt -+ NOAC.
tOVN02
AWNS-+ANRS
350
ns
. OAVt -+ NRFOt
tOVNR2
AWNS -+ ANRS -+ ACRS
350
ns
tRNR
ANRS-+ACRS
LACS, 01 reg. selected
600
ns
NOACt -+ OMAREat tNORQ
STRS -+ SWNS -+ SGNS, TACS
400
ns
N OACt -+ OA Vt
STRS -+ SWNS -+ SGNS
360
ns
tWOI
SGNS -+ SOYS, BO
reg•• elected
250
ns
tNROV
SOYS-+STRS, T1 = True
350
ns
twov
SGNS -+ SOYS -+ STRS
BO reg. selected, R FO = True
NF = fc = 8 MHz,
Tl (High Speed)
830
ns
RD. -+ NRFOt
NRFOt -+
DAii.
TRIG
Pulse Width
tTRIG
+tSYNC
50
6-44
ns
IlPD7210
AC CHARACTERISTICS
(CONT.)
(Ta - 0 -70"C. VCC = 5V ± 10%)
Limits
Parameter
Address Setup to
AD
Symbol
tAR
Test Conditions
Min
Max
Unit
RSO- RS2
85
ns
Cs
0
ns
Address Hold from iU)
tRA
0
ns
RD Pulse Width
tRR
170
ns
Data Delay from Address
tAD
250
ns
Data Delay from R D ~
tRD
150
ns
Output Float Delay from ROt
tDF
0
80
ns
RD Recovery Time
tRV
250
ns
Address Setup to WR
tAW
0
ns
Address Hold from WR
tWA
0
ns
WR Pulse Width
tww
170
ns
Data Setup to WR
tow
150
ns
Data Hold from WR
twD
0
ns
WR Recovery Time
tRV
250
ns
DMAREClI Delay from DMAACK
tAKRQ
130
ns
Data Delay from DMAACK
tAKD
200
ns
6-45
"PD7210
TIMING WAVEFORMS
CS, RS2-0
_ _ _'"'""'_ _ _.......tt---- tRR -----1"'1 11_ _ _ _ _ _ _ _'"'"\0
ro-----tRV
----i
07-0
\l
l:::;;K,a~~_______________________________
tAKO
OMAREQ
CS, RS2-0
07-0
Package Outlines
F. Information, _
Package Outline Section 7.
Plastic, ,..PD7210C
Ceramic, ,..PD7210D
7210D8-REV2-7-83-CAT
6-46
NEe
fLPD7220/GDC
fLPD7220-11 fLPD722G-2
GRAPHICS DISPLAY
CONTROLLER
Description
Features
The p,PD7220 Graphics Display Controller (GDC) is an
intelligent microprocessor peripheral designed to be the
heart of a high-performance raster-scan computer graphics
and character display system. Positioned between the
video display memory and the microprocessor bus, the
GDC performs the tasks needed to generate the raster
display and manage the display memory. Processor software overhead is minimized by the GDC's sophisticated
instruction set, graphics figure drawing, and DMA transfer
capabilities. The display memory supported by the GDC
can be configured in any number of formats and sizes up to
256K 16-bit words. The display can be zoomed and panned, while partitioned screen areas can be independently
scrolled. With its light pen input and multiple controller
capability, the GDC is ideal for advanced computer
graphics applications.
For a more detailed description of the GDC's operation,
please refer to the GDC Design Manual.
D Microprocessor Interface
System Considerations
The GDC is designed to work with a general purpose
microprocessor to implement a high-performance
comlPuter graphics system. Through the division of labor
established by the GDC's design, each of the system components is used to the maximum extent through six-level
hierarchy of simultaneous tasks. At the lowest level, the
GDC generates the basic video raster timing, including
sync and blanking signals. Partitioned areas on the screen
and zooming are also accomplished at this level. At the
next level, video display memory is modified during the
figure drawing operations and data moves. Third, display
memory addresses are calculated pixel by pixel as drawing
progresses. Outside the GDC at the next level, preliminary
calculations are done to prepare drawing parameters. At
the fifth level, the picture must be represented as a list of
graphics figures drawable by the GDC. Finally, this representation must be manipulated, stored, and communicated. By handling the first three levels, the GDC takes
care of the high-speed and repetitive tasks required to
implement a graphics system.
.
DMA transfers with 8257- or 8237 -type controllers
FIFO Command Buffering
D Display Memory Interface
Up to 256K words of 16 bits
Read-Modify-Write (RMW) Display Memory cycles
in under 800ns
Dynamic RAM refresh cycles for nonaccessed memory
D Light Pen Input
D External video synchronization mode
D Graphics Mode
Four megabit, bit-mapped display memory
D Character Mode
8K character code and attributes display memory
D Mixed Graphics and Character Mode
64K if all characters
1 megapixel if all graphics
D Graphics Capabilities
Figure drawing of lines, arC/Circles, rectangles, and
graphics characters in 800ns per pixel
Display 1024-by-1024 pixels with 4 planes of color
or grayscale
Two independently scrollable areas
D Character Capabilities
Auto cursor advance
Four independently scrollable areas
Programmable cursor height
Characters per row: up to 256
Character rows per screen: up to 100
D Video Display Format
Zoom magnification factors of 1 to 16
Panning
Command-settable video raster parameters
D Technology
Single +5 volt, NMOS, 40-pin DIP
D DMA Capability
Bytes or word transfers
4 clock periods per byte transferred
Rev/4
6-47
m
/J-PD7220
Pin Configuration
2xWCLK
lj!IIf
HSYNC
V/EXTSYNC
BLANK
ALE
A17
A16
AD15
AD14
AD13
..J!!lQ.
AD12
AD11
V"
DACK
~
AD10
AD9
AO
ADS
DBO
AD7
AD6
AD5
DBl
DB2
DB3
DB4
DB5
AD4
AD3
AD2
ADl
DB6
ADO
DB7
GND 0..:::""_ _ _- ' LPEN
Pin Identification
Character Mode Pin Utilization
"In
Pin
Symbol
No.
No.
Direction
Function
Direction
Function
AD13to 15
OUT
Line Counter Bits 0 to 2 Outputs
2xWCLK
IN
Clock Input
38
A16
OUT
Line Counter Bit 3 Output
iiiiii
OUT
Display Memory Read Input Flag
39
A17
OUT
Cursor Output and Line Counter Bit 4-
HSYNC
OUT
Horizontal Video Sync Output
V/EXTSYNC
IN/OUT
Vertical Video Sync Output or External VSVNC Input
BLANK
OUT
CRT Blanking Output
ALE~
OUT
Address Latch Enable Output
Mixed Mode Pin Utilization
"In
ORO
OUT
DMA Request Output
~
IN
DMA Acknowledge Input
l!Il"
IN
Read Strobe Input for Microprocessor Interface
10
WR
IN
Write Strobe Input for Microprocessor Interface
38
11
AO
IN
Address Select Input for Microprocessor Interface
39
060107
IN/OUT
Bidirectional Data Bus to Host Microprocessor
12-19
Name
35·37
Name
No.
Ground
20
GND
21
LPEN
IN
22·34
ADO to 12
IN/OUT
Address and Data Lines to Display Memory
35-37
AD13to15
IN/OUT
Utilization Varle. with Mode of Operation
38
A16
OUT
Utilization Varies with Mode of Operation
39
A17
OUT
Utilization Varies with Mode of Operliltlon
40
V"
35-37
AD13to15
Direction
Function
INfOUT
Address and Data Btts 13to 15
A16
OUT
Attribute Blink and Clear Line Count." Output
A17
OUT
Cursor and 8tt-Map Area- Flag Output
'Output 10 clock cycles after trailing edge of HSYNC. See figure for
timing example.
Light Pen Detect Input
+5V± 10%
Graphics Mode Pin Utilization
..In
No.
Name
Function
Direction
A013to 15
IN/OUT
Address and Data 81ts 13to 15
38
A16
OUT
Address Bit 16 Output
39
A17
OUT
Address Bit 17 Output
35-37
Block Diagram
r-~D;'M~A~--~----______~~;':~::~~HSYNC
Control
V/EXT SYNC
L-_ _ _- - ' - BLANK
ALE
i5iiN
A-17
A-16
AD-15
A[)..14
AD-13
Parameter
RAM
16x8
' -_ _ _--''''''." AD-Oto 12
+5Vo--GNDo--
LPEN
2 x WCLK 0----
6-48
tLPD7220
GDC Components
Microprocessor Bus Interface
Control of the GOC by the system microprocessor is
achieved through an 8-bit bidirectional interface. The status
register is readable at any time. Access to the FIFO buffer
is coordinated through flags in the status register and operates independently of the various internal GOC operations,
due to the separate data bus connecting the interface and
the FIFO buffer.
Command Processor
The contents of the FIFO are interpreted by the command
processor. The command bytes are decoded, and the
succeeding parameters are distributed to their proper
destinations within the GOC. The command processor
yields to the bus interface when both access the FIFO
simultaneously.
DMA Control
The OMA control circuitry in the GOC coordinates transfers over the microprocessor interface when using an external OMA controller. The OMA Request and Acknowledge
handshake lines directly interface with a ILP08257 or
ILP08237 OMA controller, so that display data can be
moved between the microprocessor memory and the display memory.
Parameter RAM
The 16-byte RAM stores parameters that are used
repetitively during the display and drawing processes. In
character mode, this RAM holds four sets of partitioned
display area parameters; in graphics mode, the drawing
pattern and graphics character take the place of two of the
sets of parameters.
exhausted, the controller accesses the starting address
and line count of the next display area from the parameter
RAM. The system microprocessor, by modifying a display
area starting address, can pan in any direction, independently of the other display areas.
Drawing Controller
The drawing processor contains the logic necessary to
calculate the addresses and positions of the pixels of the
various graphics figures. Given a starting point and the
appropriate drawing parameters, the drawing controller
needs no further assistance to complete the figure drawing.
Display Memory Controller
The display memory controller's tasks are numerous. Its
primary purpose is to multiplex the address and data information in and out of the display memory. It also contains
the 16-bit logic unit used to modify the display memory
contents during RMW cycles, the character mode line
counter, and the refresh counter for dynamic RAMs. The
memory controller apportions the video field time between
the various types of cycles.
Light Pen Deglitcher
Only if two rising edges on the light pen input occur at the
same point during successive video fields are the pulses
accepted as a valid light pen detection. A status bit indicates to the system microprocessor that the light pen
register contains a valid address.
Programmer's View of GDC
The GOC occupies two addresses on the system microprocessor bus through Which the GOC's status register and
FIFO are accessed. Commands and parameters are written into the GOC's FIFO and are differentiated based on
address bit AD. The status register or the FIFO can be read
as selected by the address line.
Video Sync Generator
Based on the clock input, the sync logic generates
the raster timing signals for almost any interlaced, noninterlaced, or "repeat field" interlaced video format. The
generator is programmed during the idle period following
a reset. In video sync slave mode, it coordinates timing
between multiple GOCs.
AO
0
READ
WRITE
Status Register
Parameter Into FIFO
I
I
I
I
I
I
I
I
I
I
I
I I
I
I
I
I
I I
I
FIFDRead
Memory Timing Generator
The memory timing circuitry provides two memory cycle
types: a two-clock period refresh cycle and the readmodify-write (RMW) cycle which takes four clock periods.
The memory control signals needed to drive the display
memory devices are easily generated from the GOC's ALE
and OBIN outputs.
Zoom & Pan Controller
Based on the programmable zoom display factor and the
display area entries in the parameter RAM, the zoom and
pan controller determines when to advance to the next
memory address for display refresh and when to go on to
the next display area. A horizontal zoom is produced by
slowing down the display refresh rate While maintaining the
video sync rates. Vertical zoom is accomplished by repeatedly accessing each line a number of times equal to the
horizontal repeat. Once the line count for a display area is
1
I
I
I
I
I
I
I
I
I
I
I
Command Into FifO
I
I
I
I
I
GDC Microprocessor Bus Interface Registers
Commands to the GOC take the form of a command byte
followed by a series of parameter bytes as needed for
specifying the details of the command. The command processor decodes the commands, unpacks the parameters,
loads them into the appropriate registers within the GOC,
and initiates the required operations.
The commands available in the GOC can be organized into
five categories as described in the following section.
6-49
m
f-LPD7220
GDC Command Summary
SR-7: Light Pen Detect
When this bit is set to 1, the light pen address (LAD)
register contains a deglitched value that the system microprocessor may read. This flag is reset after the 3-byte
LAD is moved into the FIFO in response to the light pen
read command.
Video Control Commands
1. RESET
Resets the GDC to its idle state.
2. SYNC
Specifies the video display format.
3. VSYNC
Selects master or slave video synchronization mode.
4. CCHAR Specifies the cursor and character row
heights.
SR-6: Horizontal Blanking Active
A 1 value for this flag signifies that horizontal retrace blanking is currently underway.
Display Control Commands
1. START
Ends Idle mode and unblanks
the display.
2. SCTRL
Controls the blanking and unblanking of
the display.
3. ZOOM
Specifies zoom factors for the display
and graphics characters writing.
4. CURS
Sets the position of the cursor in
display memory.
5. PRAM
Defines starting addresses and lengths
of the display areas and specifies the
eight bytes for the graphics character.
6. PITCH
Specifies the width of the X dimension
of display memory.
SR-O: Data Ready
When this flag is a 1, it indicates that a byte is available to
be read by the system microprocessor. This bit must be
tested before each read operation. It drops to a 0 while the
data is transferred from the FIFO into the microprocessor
interface data register.
DMA Control Commands
1. DMAR
Requests a DMA read transfer.
2. DMAW
Requests a DMA write transfer.
FIFO Operation & Command Protocol
The first-in, first-out buffer (FIFO) in the GDC handles the
command dialogue with the system microprocessor. This
flow of information uses a half-dupl~x technique, in which
the single 16-location FIFO is used for both directions of
data movement, one direction at a time. The FIFO's direction is controlled by the system microprocessor through
the GDC's command set. The host microprocessor coordinates these transfers by checking the appropriate status
register bits.
Status Register Flags
[
'6
1
5
1
1 1
Status Register (SR)
4
I
1
3
1
2
11
o
I
~Data_y
1
SR-3: Drawing in Progress
While the GDC is drawing a graphics figure, this
status bit is a 1.
SR-1: FIFO Full
A 1 at this flag indicates a full FIFO in the GDC. A 0 ensures
that there is room for at least one byte. This flag needs to
be checked before each write into the GDC.
Data Read Commands
1. RDAT:
Reads data words or bytes from
display memory.
Reads the cursor position.
2. CURD:
Reads the light pen address.
3. LPRD:
7
SR-4: DMA Execute
This bit is a 1 during DMA data transfers.
, SR-2: FIFO Empty
This bit and the FIFO Full flag coordinate system microprocessor accesses with the GDC FIFO. When it is 1, the
Empty flag ensures that all the commands and parameters
previously sent to the GDC have been interpreted.
Drawing Control Commands
1. WDAT
Writes data words or bytes into
display memory.
2. MASK
Sets the mask register contents.
3. FIGS
Specifies the parameters for the
drawing controller.
4. FIGD
Draws the figure as specified above.
5. GCHRD Draws the graphics character into
display memory.
I I
SR-S: Vertical Sync
Vertical retrace sync occurs while this flag is a 1. The
vertical sync flag coordinates display format modifying
commands to the blanked interval surrounding vertical
sync. This eliminates display disturbances.
RFOFul1
RFOEmpty
Drawfhg In Prog.....
DMA Execute
Vertical Sync Active
Horizontal Blank Active
Ugh! _ Datect
The command protocol used by the GDC requires differentiation of the first byte of a command sequence from the
succeeding bytes. The first byte contains the operation
code and the remaining bytes carry parameters. Writing
into the GDC causes the FIFO to store a flag value alongside the data byte to signify whether the byte was written
into the command or the parameter address. The command processor in the GDC tests this bit as it interprets the
6-50
fJ-PD7220
entries in the FIFO.
The receipt of a command byte by the command processor
marks the end of any previous operation. The number of
parameter bytes supplied with a command is cut short by
the receipt of the next command byte. A read operation
from the GDC to the microprocessor can be terminated at
any time by the next command.
The FIFO changes direction under the control of the system microprocessor. Commands written into the GDC
al~ays put the FIFO into write mode if it wasn't in it already.
If it was in read mode, any read data in the FIFO at the time
of the turnaround is lost. Commands which require a GDC
response, such as RDAT, CURD and LPRD, put the FIFO
into read mode after the command is interpreted by the
GDC's command processor. Any commands and parameters behind the read-evoking command are discarded
when the FIFO direction is reversed.
Read·Modify·Write Cycle
Data transfers between the GDC and the display memory
are accomplished using a read-mOdify-write (RMW) memory cycle. The four clock period timing of the RMW cycle is
used to: 1) output the address, 2) read data from the memory, 3) modify the data, and 4) write the modified data back
into the initially selected memory address. This type of
memory cycle is used for all interactions with display memory including DMA transfers, except for the two clock
period display and RAM refresh cycles.
The operations performed during the modify portion of the
RMW cycle merit additional explanation. The circuitry in the
GDC uses three main elements: the Pattern register, the
Mask register, and the 16-bit Logic Unit. The Pattern register holds the data pattern to be moved into memory. It is
loaded by the WDAT parameters or, during drawing, from
the parameter RAM. The Mask register contents determine
which bits of the read data will be modified. Based on the
contents of these registers, the Logic Unit performs the
selected operations of REPLACE, COMPLEMENT, SET, or
CLEAR on the data read from display memory.
The Pattern register contents are ANDed with the Mask
register contents to enable the actual modification of the
memory read data, on a bit-by-bit basis. For graphics drawing, one bit at a time from the Pattern register is combined
with the Mask. When ANDed with the bit set to a 1 in the
Mask register, the proper single pixel is modified by the
Logic Unit. For the next pixel in the figure, the next bit in the
Pattern register is selected and the Mask register bit is
moved to identify the pixel's location within the word. The
Execution word address pointer register, EAD, is also
adjusted as required to address the word containing the
next pixel.
In character mode, all of the bits in the Pattern register are
used in parallel to form the respective bits of the modify
data word. Since the bits of the character code word are
used in parallel, unlike the one-bit-at-a-time graphics drawing process, this facility allows any or all of the bits in a
memory word to be modified in one RMW memory cycle.
The Mask register must be loaded with 1s in the positions
where modification is to be permitted.
The Mask register can be loaded in either of two ways. In
graphics mode, the CURS command contains a four-bit
dAD field to specify the dot address. The command processor converts this parameter into the one-of-16 format
used in the Mask register for figure drawing. A full 16 bits
can be loaded into the Mask register using the MASK command. In addition to the character mode use mentioned
above, the 16-bit MASK load is convenient in graphics
mode when all of the pixels of a word are to be set to the
same value.
The Logic Unit combines the data read from display
memory, the Pattern Register, and the Mask register to
generate the data to be written back into display memory.
Anyone of four operations can be selected: REPLACE,
COMPLEMENT, CLEAR or SET. In each case, if the
respective Mask bit is 0, that particular bit of the read data
is returned to memory unmodified. If the Mask bit is 1, the
modification is enabled. With the REPLACE operation, the
Pattern Register data simply takes the place of the read
data. for modification enabled bits. For the other three operations, a 0 in the modify data allows the read data bit to be
returned to memory. A 1 value causes the specified operation to be performed in the bit positions with set Mask bits.
Fig"re Drawing
The GDC draws graphics figures at the rate of one pixel
per read-mOdify-write (RMW) display memory cycle. These
cycles take four clock periods to complete. At a clock frequency of 5MHz, this is equal to 800ns. During the RMW
cycle the GDC simultaneously calculates the address and
position of the next pixel to be drawn.
The graphics figure drawing process depends on the
display memory addressing structure. Groups of 16 horizontally adjacent pixels form the 16-bit words which are
handled by the GDC. Display memory is organized as
a linearly addressed space of these words. Addressing
of individual pixels is handled by the GDC's internal
RMWlogic.
During the drawing process, the GDC finds the next pixel
of the figure which is one of the eight nearest neighbors of
the last pixel drawn. The GDC assigns each of these eight
directions a number from 0 to 7, starting with straight down
and proceeding counterclockwise.
000
',,--1/'
O~O~O
Drawing Directions
ci6'o
Figure drawing requires the proper. manipulation of the
add tess and the pixel bit position according to the ,drawing
direction to determine the next pixel of the figure. To move
to the word above or below the current one, it is necessary
to subtract or add the number of words per line in display
memory. This parameter is called the pitch. To move to the
word to either side, the Execute word address cursor, EAD,
must be incremented or decremented as the dot address
pointer bit reaches the LSB or the MSB of the Mask register. To move to a pixel within the same word, it is necessary
to rotate the dot address pointer register to the right or left.
6-51
/LPD7220
word address when moving to the next word. It does not
follow a 45 degree diagonal path by pixels.
The table below summarizes these operations for each
direction.
D..
Operations to Addr••• the Next Pixel
000
+ P_EAD
EAD + P-EAD
Drawing Parameters
EAD
001
dAD (MSB) = 1:EAD
010
dAD (MSB) = 1 :EAD
011
EAD - P ...... EAD
dAD (MSB) = 1:EAD + 1 _ EAD dAD-lR
+ 1_
+ 1-
EAD dAD_lR
EAD dAD-lR
100
EAD - P-EAD
101
EAD - P ...... EAD
dAD (LSB) = 1:EAD - 1 ...... EAO
110
dAD (lSB) = 1:EAD - 1 _ EAD dAD-RR
111
EAD + P-EAD
dAD (lSB) = 1 :EAD - 1 _ EAD dAD-RR
dAD-AR
Where P = PItch, LR == Left Rotate, RR = RIght Rotate,
EAD = Execute Word Address, and
dAD = Dot Address stored In the Mask RegIster
Whole word drawing is useful for filling areas in memory
with a single value. By setting the Mask register to all 1s
with the MASK command, both the LSB and MSB of the
dAD will always be 1, so that the EAD value will be incremented or decremented for each cycle regardless of
direction. One RMW cycle will be able to effect all 16 bits of
the word for any drawing type. One bit in the Pattern register is used per RMW cycle to write all the bits of the word
to the same value. The next Pattern bit is used for the
word, etc.
For the various figures, the effect of the initial direction
upon the resulting drawing is shown below:
Oir
000
Line
~#
Arc
~>7
r)
,' "
--
Ul1lJ1J
.~
001
~
010
'
~ L>
~
"
011
100
101
110
111
,
V C'" ~
;/
v~
/J
[
~ C
/,-
:
,
,-
Character SlanlChar Rectangle
fUlJU1
~
~
§
~
DMA
CJ
N\l
0
~
CJ
~
0
~
[J
f"N
0
V n"J ~ f CJ
';,)
~
~ ~ (>
In preparation for graphics figure drawing, the GDC's Drawing Processor needs the figure type, direction and drawing
parameters, the starting pixel address, and the pattern
from the microprocessor. Once these are in place within
the GDC, the Figure Draw command, FIGD, initiates the
drawing operation. From that point on, the system microprocessor is not involved in the drawing process. The GDC
Drawing Controller coordinates the RMW circuitry and
address registers to draw the specifed figure pixel by pixel.
The algorithms used by the processor for figure drawing
are designed to optimize its drawing speed. To this end, the
specific details about the figure to be drawn are reduced
by the microprocessor to a form conducive to high-speed
address calculations within the GDC. In this way the repetitive, pixel-by-pixel calculations can be done quickly,
thereby minimizing the overall figure drawing time. The
table below summarizes the parameters.
Drawing Type
D
DC
Initial Value·
D2
8
Lme
IAII
Arc"
2I AD I-I"11
rsin -
:::pr'-_____
,'-____
"'F
ca
:I
I\)
='
,
•
:i
S'
ea
iIII
Zoomed Display Operation with RMW Cyc/. (3x Zoom)
~·T·TOOTOO+·TM:rMT-M+.
~'I
:1 \
I
I
I
\
I
I
I
RtlW
OIapI8y or AMW
Cycle
Cycle
:I
i"--
\
\
.
i
.::
/
'
CJ)
I
CJ)
C11
'M'.r~
A1S,17
BLANK,
=n
>-<_jXO__ '
(_-1
(-->----< - -
X
X
X'-_____
/
\
=c\
I
"'F
~
....
II
~
~PD7220
lImln.w.v.fo,.... (Coni.)
Ught,.", and ~.,.nal Sync Input nmlng
Clock Timing (2XWCLK)
a==
2XWCLK:~
LP~,
EX. SYNC:
t",
1ltst
La"'
(for AC Tests, axcept 2XWCLK)
VIdeo Sync Signal. nmlng
I.
'I
lH
ZXWCLK:.JV\.../\./\./\ ____
..J\../"\./\... __ ..I"VV ___ J"V\... __ J\...
HBLANt<:J
- - - - " " ' - - __
I
HSYNC:
r
\1.. ____________
ADO-15::::X:::::X:::::::::::x:::::::x::=::::::x:::::x::: x= ==:::t:
I
LCO-4::::::::)(
: \
ADO-15:t;;;*~~~~~~;~:-=-=-:~~~~~~;=-=-=~;~;;;~:-=-~
-+- ___
___
LCO-4:-v-----:x::::
- ---v--------- ----------------- ~---:x::
....A...- _________________________
- - " - - __ _
'
C
-:j(
i {_______________________________________________
'
I
'
===x:
-~----:r:=;<
1
---:
'--____
I
VBLANK:
I
w~:.~-------------------------------~--------JI
,.1·-------------1VIFrome)------------------I
InterlllC8d VIdeo nmlng
.JL __ -IL.JL __ JL.JL __ JL.JL __ -1L - _ ...n.--- ~- --fL..J1--
HBLANK:
I
I
I
I
VBLANK:l-- __ ~---,-------,----L
I
I
I
I I
I I
__ S----,-,-----,-,--
I
I
I
VSYNC:,
I
I
I
II
(Interlace) :
:
I
:
:
I
'j'
j'
Odd Field
I I
IL-I
Even Field _ _-'-:_ __
I
I
I
(NOI~~:.~~,)_)- - - - - - - - ' 1
L-
6-66
IJ.PD7220
Timing Waveforms (Co.,I.)
VIdeo HorIzontal Sync Generator Parameters
1~'-----------------------IH--------------------~
I
I
I
~--------------------------~r-
HBLANK:----.-J
I
I
I
HSYNC:
rI~
I
______ ____________________________
~
I
I
I
I
I
I
I
I
I
~
--1 H~ ~HBP--l,I-,- - - - - C / R - - - - - - - - - i
Video Vertical Sync Generator Parameters
1-1,- - - - - - - - - - - - - - - - - - - 1
VBLANK:
V
---------------1.,
I
I
I
I
I
I
I
I
.....-_---!n
I
I
I
I
I
l
I
I
I
VSYNC:.-J!L-_ _---:_ _ _ _ _ _ _ _ _ _ _ _ _ _
I
I
I
I
I
I
I
I
I
I
I
I- VBP . . ·. I'----------UF------j.....
..
VFP
r
i
2xCCLK
HBLANK
HSYNC
CRS-Image
=±
r'l----1f
r
~
L
s~
r--l0tcLK~
~
L---'-nva-hd----+-1
Cursor
Image
6-67
t--
I~P--1
----1\11;1--Cursor-Image Sit Flag
I
f-LPD7220
Video Field Timing
HSVNC output
BLANK Output
---II
--..J :
r-t---
i
Vertical SYNC LInes
rt-L-.: :
·--t------
Vertical Back Porch Blankod linea
Horizontal.
SYNC--.o
Pulse
Horizontal
Front Porch_
&.
az
Blanking
u
>~
Active
Display
lin..
Horizontal
Back Porch
Blanking
~
~
Vertical Front Porch Blanked Linea
"~JS
Drawing Intervals
~
Drawing Interval
~ Additional DraWing Interval When
~ In Flash Mode
~
R22il
Dynamic RAM ReI....h d Enabled, Otharwlaa
AddKional DrawIng Interval
DMA Request Intervals
DMA Raquaat Int..-val
Addftional DMA Req..... lnterval.
W_ln Flash Mode
6-68
~PD7220
Block Diagram of a Graphics Terminal
---------,
r----------
I
Clock
~P07220
GDC
DBO-7
Data
Blanking
HSYNC
VSYNC
LPEN
Host
CompuW
-----------------~
Multlplane Display "emory Diagram
GDC
AD
Ot015
6-69
J.LPD7220
Package Outlines
For Information, see Package Outline Section 7.
Ceramic, .. PD7220D
7220DS·Rev 4·7·83·CAT·L
6-70
NEe
tJPD7225
INTELLIGENT ALPHANUMERIC
LCD CONTROLLER/DRIVER
Description
The ",PD7225 is an intelligent peripheral device designed
to interface most microprocessors with a wide variety of
alphanumeric LCDs. It can directly drive any static or
multiplexed LCD containing up to 4 backplanes and up
to 32 segments and is easily cascaded for larger LCD
applications. The ",PD7225 communicates with a host
microprocessor through an a-bit serial interface. It
includes a 7-segment numeric and a 14-segment alphanumeric segment decoder to reduce system software
requirements. The ",PD7225 is manufactured with low
power consumption CMOS process allowing use of a
single power supply between 2.7V and 5.5V and is
available in a space-saving 52-pin flat plastiC package.
Pin Configuration
5,
520
5"
5'2
5'3
IS24
25
5,
55
23
5.
53
5,
5,
22
525
526
,.,.
,.
"'0
IlPD7225
5"
5,.
17
52.
530
Features
D Single-chip LCD Controller with Direct LCD Drive
D Low-cost Serial Interface to most Microprocessors
D Compatible with:
7-Segment Numeric LCD Configurations-up to 16
Digits
14-Segment Alphanumeric LCD Configurations-up
to a Characters
D Selectable LCD Drive Configuration:
Static, Biplexed, Triplexed, or Quadriplexed
D 32-Segment Drivers
D Cascadable for Larger LCD Applications
D Selectable LCD Bias Voltage Configuration:
Static, 112, or 113
D Hardware Logic Blocks Reduce System Software
Requirements
- a-Bit Serial Interface
- Two 32 x 4-Bit Static RAMs for Display Data and
Blinking Data Storage
- Programmable Segment Decoding Capability
- 16-Character, 7-Segment Numeric Decoder
- 64-Character, 14-Segment USASCII Alphanumeric Decoder
- Programmable Segment Blinking Capability
- Automatic Synchronization of Segment Drivers
with Sequentially Multiplexed Backplane Drivers
D Single Power Supply, Variable from 2.7V to 5.5V
D Low Power Consumption CMOS Technology
D Extended - 40°C to + a5°C Temperature Range
Available
D Space-saving 52-Pin Flat Plastic Package
,.
16
53'
So
COM3
COM2
COMl
COMO
NC
Cl,
Pin Description
Pin
Ho.
Function
S._I
CL2
SYNC
System clock output (active high). Connect to CL1 whh
180kQ r.elstor, or leave open.
Synchronlzatlon port (active lOW). For muttlchlp operation
tie all SYNC lin•• together.
3-5
7,33
YLCD1'
YLCD2'
YLCD3
LCD bla. voltage supply Inputa to LCD YOhage controller.
Apply appropriate voltage. from a voltage ladder con&
nected aeros. VOD'
Vss
Ground.
VDD
Power supply postllve. Apply single voltage ranging from
SCK
Serial clock Input (active low). Synchronizes 8-blt Hrlal da'a
2.7V to 5.5V for proper operation.
tranafer from mlcroprocel8Or to JoIPD7225.
SI
Serial Input (active high). Oatalnput from mlcroproceasor.
10
CS
ChiP select Input (active low). Enables ,..P07225 for data
Input from microproceasor. Display can also be updated
when ,..P07225 II deeelected.
11
BUSY
Busy output (active low). Handlhake line tncHeat" that
,..P07225 I. ready to receive next data byte.
12
C/D
Command/data Hlect Input (active both high and lOW).
OI81lngulahe. 88l1sll, Input data byte as a command or a.
display data.
13
RESET
Reset Input (active lOW). RIC circuit or pul" Initializes
,..P07225 atter power·up.
14
MC
No connection.
15-18
CDMo-CDM3
LCO Backplane DrIver OUtputl.
19-32,
34-51
Sg-S31
LCD Segment Driver Outputa.
52
CLl
System clock Input (active high). Connect to C~ with
1801Q reelltor, or to external clock IIDUrce.
REVI1
6-71
II
J,lPD7225
Block Diagram
COMO-COM3
LCD Driver
32
Display Latch
32
32
Voo
VLCOI
LCD
VLC0 2
Voltage
Controller
VLC0 3
Segment
32x4Blt
32x4Blt
Decoder
Display RAM
Blinking RAM
Vss
Buffer
Interface
Controller
Command
Decoder
Senal Interface
CS
Cli)
BuSY
SI
SCi<
Command Summary
Instruction Cod.
Binary
Command
1. MODE SET
D.scrlptlon
Initialize the "PD7225, Including selection of:
1) LCD Drive Configuration
2) LCD Bias Voltage Configuration
3) LCD Frame Frequency
HEX
D7 D. D. D. D:a D. Dt Do
0
0
D4 D3 D2 Dl Do 40-5F
2. UNSYNCHRONOUS DATA Synchronize Display RAM data transfer to
TRANSFER
Display Latch with CS
0
0
0
0
0
3. SYNCHRONOUS DATA
TRANSFER
Synchronize Display RAM data transfer to
Display Latch with LCD Drive Cycle
0
0
0
0
0
4. INTERRUPT DATA
TRANSFER
Interrupt Display RAM data transfer to
Display Latch
0
0
0
0
5. LOAD DATA POINTER
Load Data POinter With 5 bits of Immediate
Data
6. CLEAR DISPLAY RAM
Clear the Display RAM and reset the Data
Pointer
7. WRITE DISPLAY RAM
Write 4 bits of Immediate Data to the Display
RAM location addressed by the Data
POinter; Increment Data POinter
8. AND DISPLAY RAM
Perform a Logical AND between the Display
RAM data addressed by the Data Pointer
and 4 bits of Immediate Data; Write result to
same Display RAM location Increment Data
Pointer
6-72
0
30
31
0
38
D4 D3 02 Dl Do EO-FF
0
0
0
0
0
0
0
0
20
0
0 3 O2 0 1 Do DO-DF
0
0 3 O2 Dl Do 90-9F
t-t
Command Summary (Cont.)
PD7225
Instruction Cod.
HEX
Binary
D.scrlptlon
9. OR DISPLAY RAM
10. ENABLE SEGMENT
DECODER
D7 D. D. D. D3 D. Dt D.
Perform a Logical OR between the Display
RAM data addressed by the Data POinter
and 4 bits of Immediate Data, Write result to
same Display RAM location, Increment Data
POinter
0 3 O2 0, Do BO-BF
0
Start use of the Segment Decoder
0
0
0
0
0
11. DISABLE SEGMENT
DECODER
Stop use of the Segment Decoder
0
0
0
0
0
0
14
12. ENABLE DISPLAY
Turn on the LCD
0
0
0
0
0
0
1
11
13. DISABLE DISPLAY
Turn off the LCD
0
0
0
1
0
0
0
0
10
14. CLEAR BLINKING RAM
Clear the Blinking RAM and reset the Data
POinter
0
0
0
0
0
0
0
0
00
15. WRITE BLINKING RAM
Write 4 bits of Immediate Data to the Blinking
RAM location addressed by lhe Data
POinter; Increment Data POinter
0
0
0 3 O2 0, Do CO-CF
16. AND BLINKING RAM
Perform a Logical AND between Blinking
RAM data addressed by the Data POinter
and 4 bits of Immediate Data; Write result to
same Blinking RAM Location; Increment
Data POinter
0
0
0
0 3 O2 0, Do 80-8F
17. OR BLINKING RAM
Perform a Logical OR between Blinking
RAM data addressed by the Data POinter
and 4 bits of Immediate Data, Write result to
same Blinking Location; Increment Data
Pointer
0
0
0 3 O2 0, Do AO-AF
18. ENABLE BLINKING
Start Segment Blinking at the Frequency
Specified by 1 bit of Immediate Data
0
0
0
0
19. DISABLE BLINKING
Stop Segment Blinking
0
0
0
0
Do 1A-1 B
0
0
18
DC Characteristics
Details of operation and application examples can be
found in the "IlPD7225 Intelligent Alphanumeric LCD
Controller/Driver Technical Manual."
Ta
=
- 10·C to + 70·C; vDD
=
+ s.ov
± 100/0
LImits
Parama.er
Absolute Maximum Ratings *
Ta = 2S·C
Supply Voltage, VOO
All Inputs and Outputs with Respect to VSS
Storage Temperature
Operating Temperature
15
input Voltage
High
Input Voltage
-0.3Vto +7.0V
- O.3V to Voo + O.3V
-65·C to + 150·C
-10·C to + 70·C
·COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Symbol
VIH
MIn
Tvp
0.7 VOO
Unit
VOO
V
0.3
voo
VIL
Low
Input Leakage
M ••
IUH
Te.t
Condltlon_8
V
.A
VIH - VOO
.A
VIL - ov
V
BUSY, SYNC.
IOH = -10 IJ.A
Current High
Input Leakage
Current Low
-2
ILIL
Output Voltage
High
VOH
Output Voltage
VOL,
0.5
V
BUSY, 10L - 100.A
VOL2
1.0
V
SYNC,IOl
.A
VOH
Voo
.A
VOL
ov
.A
SYNC. VOS - 1.0V
kQ
COMO-COM3'
VOO ~ VLCO·
Applies to statlc~.
Low
Output Leakage
CUrrent Low
ILOH
Output Short
Circuit Current
lOS
Backplane Driver
RCOM
Output Impedance
VOO -0.5
'LOL
-300
900j.lA
1/2-, and 1/3-LCD
bias voltage schemes
Segment Driver
Output Impedance
14
RSEG
kQ
SO-S31.
VOO ~ VLCO·
Applies to 8tatlc~.
112-, and 1I3-lCD
bias voltage schemes
Supply Current
6-73
100
100
250
.A
ell external clock,
,+ =
200 KHz
",PD7225
DC Characteristics (Cont.)
= o·c to + 70'C; YDD = 2.7 to 5.5Y
AC Characteristics (Cont.)
T.
T.
= O·Cto
+70·C;YDD
LImit.
.,lftbOI
Input Voltage
High
TvP
Min
limit.
....
Symbol
Un"
0.7 VOO
VOO
V
Except SCK
0 •• VOO
VOO
V
SCK
0.3
VOO
v
Except SCK
0.2
V
SCK
Input Voltage
Low
'OSC
50
100
140
,",S
Cll' external clock
VOO
I-----
J-IPD7225
Characteristics Curves
Ta
= 2SoC
Supply Voltage va Oscillation Frequency
External Resistance vs Oscillation Frequency
D
,
200
?
'~
~
~
r;
~
"e
"-
100
c
R
~
?
~ 120
.
~
~
~
VOO
=
I
c
2
,,
y
,,
,
200
100
!
~
3V
50
100
R7V
R
'~
.2
:
1:1
140
,
/
1/
80
500
~
External Resistance R (kQ)
Supply Voltage VOO (V)
Supply Voltage vs Supply Current
~
External Clock
100
Q
.P
E
~
ag-
=:
200 KHz
V
/ V
~
()
f
'7
50
V
III
/'
20
L,
-Supply Voltage Voo (V)
6-76
J..lPD7225
7.Segment Numeric Data Decoder Character Set
Decoded Display RAM Data
Display
Byte
(HEX)
Triplexed
Quadruplexed
Display RAM Address
Display RAM Address
Character
n+2
n+1
n
n+1
n
a
3
5
3
0
7
P
uJ
0
0
3
0
6
51
2
7
E
3
03
Sa
0
7
3
A
7
04
Q,
2
3
3
6
05
Dc
7
2
B
5
7
2
F
5
3
0
7
7
3
F
7
7
3
B
7
3
2
0
2
0
3
7
0
F
3
5
0
0
0
6
0
A
0
2
6
2
E
4
0
0
0
0
0
00
01
C':::.
02
0
Co
EI
(j]
06
_0
B
07
g
08
09
OA
OB
OC
00
OE
OF
D
B
Ii
Ii
aq
G,
,>f lf
~~~
~:'(,
8
3
0
3
6-77
II
I:3! ..-:
"I»
Display
i!:
5"
III
fa
CD
(HEX)
g" i ~
3;
0
3
II
Byte
Char
Display RAM
Address
n+3n+2n+1 n
Display
Byte
::. 0
AO
000
o ..• :s
....
~ •"11 1/1CD
III
A1
Invalid
B1
A2
Invalid
B2
!.
Fa ~
CO)
I'l
""
•
~5"
s=
II
ca
0
BO
•
A3
Invalid
B3
g"
A4
Invalid
B4
AS
Invalid
B5
A6
Invalid
[
="
B6
0>
I
o
0
0
2
B7
II',
o
0
0
A
B8
M!
A7
= 400 KHz
T a = _25°C, VDO = OV
CAPACITANCE
LIMITS
MAX
UNIT
CI
10
pF
Output Capacitance
Co
25
Input/Output Capacitance
CIO
15
PARAMETER
Input Capacitance
SYMBOL
MIN
TYP
CONDITIONS
ftl> = 1 MHz
pF
Unmeasured PinS
pF SYNC retu rned to G rou nd.
6-82
",PD7227
.AC CHARACTERISTICS
Ta
=
_10°C to +70°C, VDD
=
+5.0V ± 10%
LIMITS
PARAMETER
SYMBOL
MIN
f
100
Clock Pulse Width High
tWH
400
Clock Pulse Width Low
tWL
400
ns
SCK Cycle
tCY...K
0.9
I'S
SCK Pulse Width High
tkWH
400
ns
SCK Pulse Width Low
tKWL
400
ns
SCK Hold Time After BUSYt
tKHB
0
ns
SI Setup Time To SCKt
tlS K
100
ns
SI Hold Time After SCKt
tlHK
250
SO Delay Time After SCK.
tODK
320
ns
SO Delay Time After C/D.
tODD
2
I'S
SCK Hold Time After C/D.
tKHD
BUSY Delay Time After 8th SCKt
tBDK
3
I'S
BUSY Delay Time After C/Dt
tBDD
2
I'S
2
I'S
Clock Frequency
MAX
UNIT
1000
KHz
CONDITIONS
ns
ns
2
I'S
BUSY Delay Time After CS.
tBDC
C/D Setup Time to 8th SCKt
tDSK
2
I'S
C/D Hold Time After 8th SCKt
tDHK
2
I'S
CS Hold Time After 8th SCKt
tCHK
2
I's
CS Pulse Width High
tCWH
2M
I'S
CSt Delay Time to BUSY Floating
tCDB
2
SYNC Load Capacitance
AC CHARACTERISTICS
TYP
I'S
CLOAD
= 50pF
pF
100
CLOADS
= 50pF
CLOAD
Ta -10to +70'C.VOO ~ 2.7t055V
LIMITS
SYMBOL
PARAMETER
MIN
TYP
MAX
250
UNIT
100
Clock Pulse Width High
tWH
1800
Clock Pulse Width Low
tWL
1800
ns
SCK Cycle
tCYK
4
I'S
SCK Pulse Width High
tkwH
1800
ns
SCK Pulse Width Low
tKWL
1800
ns
SCK Hold Time After BUSYt
tKHB
a
ns
SI Setup Time To SCKt
tlS K
500
ns
SI Hold Time After SCK t
tlHK
1
SO Delay Time After SCK.
tODK
SO Delay Time After C/D.
tODD
SCK Hold Time After C/Dl
tKHD
BUSY Delay Time After 8th SCK t
tBDK
4
I's
tBDD
3
I'S
3
I'S
BUSY Delay Time After C/Dt
ns
ns
1200
ns
3
I'S
I'S
3
BUSY Delay Time After CS I
tBDC
C/D Setup Time to 8th SCKt
tDSK
3
I'S
C/D Hold Time After 8th SCKt
tDHK
3
I's
CS Hold Time After 8th SCKt
tCHK
3
I'S
CS Pulse Width High
tCWH
2/f
I'S
Cst Delay Time to BUSY Floating
tCDB
3
SYNC Load Capacitance
CLOADS
6-83
CONDITIONS
KHz
f
Clock Frequency
I'S
100
pF
CLOAD
CLOAD
=
=
50 pF
50pF
,.,PD7227
CLOCK WAVEFORM
SERIAL INTERFACE
TIMING WAVEFORMS
cs
c/o
--,
tODD
SO/BUSY
("SO)
-
\
--j1\~~J
_ _ ..J
I
_ --1
" ,__
- ,,'CDJ -''
-- I, ,--- , - - - 1 + - - - - - - - -
r
SO/Bl:.JSY
(as BUSY)
--, ,....."t
r---tB_D~K...,,_/ _
tKHS
I-----'io"*~-
SCK
8th
51
6-84
,--
_
'L
,",PD7227
5 X 7 CHARACTER SET
AS GENERATED IN fLPD7227
o
0
o
Display Byte
... ... ....
.... ... .. .......
.... ....
... .. .. ..
... ........
.. .. ..
.. .... .... ...
....... .
,.' . ..
..........
"
'
•
o
0
0
0
.00
o
o
1
• • • 0,,'-,,- • • ,,"
'
•• "0" ••
"
o
" ' •• ,,
,' 0 " ' ..">"
"
"',
•
".'
.'"
.0'
•
".'
.•••
• ",,'.< •••
(".')'
o
o
••
o
•• 0_..
,
o
•
'
' 0 • • CC".
•
(
.'
~.
" ••
~ (
• • • • 0'
••••
••
u
••
'0".'
•••••
• ~, • ., (
000'.(
•
•
o .:::. :.. :. ::: :
.. ...........
....
,.,) ..
..
•
o
,,.,
",,,
"0
•
o
o
•
'."
"
• • •'
o
, •• , . •
•
•
','
o
0
•
•
•••• c
,
•
...
·... ....... ......
..... ...
"._'
.,'
'
'
,·,°8 • • "
.'
••• c"' • • "
'
•
••
"
,
0 •• """0 •• " • • • • • • •
o ~m:gmm;
~
0""."."',(, •• "
o
" •• "." ••• ',.
~
(00"
o
0
0
0
0
0
Display Byte
0
Do
0
0
0
0
0
:
... :
... .. .
cO
"
...
.. ... .
..
.. .. .....
"
...
0
0
0
o
o
6-85
... :
-
0
0
:
:
"PD7227
Pack. . . Outlines
For Information, . . . Paclulge OUtline Section 7.
PI.stlc Mlniftat, ",PD722713
6-86
7227DS-REVl-7-83-CAT
NEe
Description
f.1PD7228
INTELLIGENT DOT-MATRIX
LCD CONTROLLER/DRIVER
Pin Configuration
The J.LP07228 Intelligent Dot-Matrix LCD ControlierlDriver
is a peripheral device designed to interface most microprocessors with a wide variety of dot-matrix LCOs. It can
directly drive any multiplexed LCD organized as 8 rows x
50 columns or 16 rows by 42 columns. The J.LP07228 has
a standby function to conserve power. It is equipped with
several logic blocks, such as an 8-bit serial interface, a
4-bit parallel interface, an ASCII upper Ilower case, a Kana
character generator, a 50 x 16 static RAM with full readl
write capability, and an LCD timing controller, all of which
reduce microprocessor system software requirements.
The J.LP07228 is manufactured with a single 5V CMOS
process, and is available in an 80-pin space saving flat
plastic package.
c.,
C"
C,.
C'3
C,.
Cl1
C49 /R a
C,.
R'S/R7
R'4 /R 6
C.
C.
Ru/Rs
C7
R'2/R4
C.
Cs
C.
R11 /R3
R'0/R2
RgJR,
C3
R8/RO
VLC5
C.
C,
C.
VLC1
NC
NC
CLOCK
V LC4
o
o
o
o
o
o
C,.
C46 /R '1
C47 /R '0
C4S /R g
o
o
C,.
C17
C42 1R '5
C43 /R'4
C44 /R '3
C4s /R '2
Features
o
o
o
C••
C,.
c••
o LCD direct drive
o 8-line or 16-line multiplexing drive possible with
single chip
- 8-line multiplexing: 400 (50 x 8) dots
- 16-line multiplexing: 672 (42 x 16) dots
8-line or 16-line multiplexing drive with n chip
configuration
- 8-line multiplexing: n x 400 (n x 50 x 8) dots
- 16-line multiplexing: n x 800 (n x 50 x 16) dots
DRAM: 2 x 50 x 8 bits for display data storage
Programmer designated dot (graphics) display
5 x 7 dot-matrix display by on-chip character generator
ASCII characters (alphanumerics, others): 64 characters; JIS characters (Kana and others): 96 characters
Cursor operating command
8-bit serial interface compatible with J.LP07500,
J.LCOM-43N, J.LCOM-87/87LC
4-bit parallel interface compatible with J.LP07500,
J.LCOM-84/84C
Standby function
CMOS
Single power supply
80-pin plastic flat package
Extended - 40°C to + 85°C temperature
range available
C2 ,
C3 •
c3 •
Pin Identification
No.
1-18
42-80
5-12
13-20
Pin
Symbol
Description
CO-C 41
LCD Column Drive Outputs
C42/R'S-C49/Rs
Ro/Ra- R7/ R'5
LCD Row Drive Outputs
LCD Row/Column Drive Outputs
21,22
24-26
VLC1-VLC5
LCD Power Supply
23, 42
NC
No Connection
27
0 0 /51
Data Bus O/Serlallnput
28
O,(P/S)
Data Bus 1 (ParallellSerlal Select)
29
O.(CAE)
Oata Bus 2 (Chip Address Enable)
30
31
0 3 /50
Data Bus 3/Serlal Output
SYNC
Synchronization Signal Input/Output
32
BUSY
Busy Signal Output
33
Voo
Power Supply
34
Vss
Ground
35
STB/SCK
Strobe/Serial Clock Input
36
C/O
Command/Data Select Input
37,38
CAo, CA,
Chip Address Select Inputs
39
CS
Chip Select Input
40
RESET
Reset Signal Input
41
CLOCK
System Clock Input
6-87
fl.PD7228
Block Diagram
CoS
CoNS
System
Serial/Paraliellnterface
Clock
Control
1
'"mm
...
III
~I
Jl
6-88
n
;r-
n
01
~l
~l
~I
~
III
0
0
"-
,.
'0
.!!!
-l"
'ii
$1
~
j.LPD7228
Character Code
Character Cadell and DIsplay Patterns
4
0
I I I I
~
0
0
0
0
... ...
1
1
1
0
1
0
0
0
1
0
1
...
...
...
.....
...
:
... ... :
..
....
1
1
0
...
....
...
0
1
1
1
....
.. .. ...
....
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
...
..
.....
...
...
:
:
.....
.. .
....
. .
...
:
.....
:
.. ...
.
..
: :
. .....
:
.....
..... .....
:
:
...
....
.. .
..
.. : ...:
6-89
.. .
.....
. .. .
.. . ....
.....
:
.
..
:
.....
....
. '".
.. .
...
..:
..
...
: ... .... ..
..
..
:
. :.......:
0
:
... ...
...
. ... :
..
.. ..
....
:
... :
:
:
.....
:
:
:
.....
.....
..
.....
.. .
:
... ..
.....
.....
.....
~ ,. .
.....
:
....
: :
... :
...
D
f,LPD7228
Electrical Specifications
Absolute Maximum Ratings*
Commands for fLPD7228
The fLPD7228 is provided with sixteen types of commands,
each command consisting of one byte (8 bits).
T.
Command Summary
1. Set Frame Frequency
000
2. Set Multiplexing Mode
o
3. Display Off
0000000
4. Display On
o
5. Set Read Mode
o
0001110
6. Set Write Mode
o
o o
11
10
7. Set AND Mode
o
o
11
10
0
OF2F1FO
0
0
=25"C
M2 Ml MO
0
0
0
*COMMENT: Exposing the device to stresses above
those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be
operated under conditions outside the limits described
in the operational sections of this specification. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
0
Capacitance
T.
= 25"C; VDD =OV
Parameter
o
o
8. Set OR Mode
9. Set Character Mode with
Right Entry
o
11
10
o
12. Bit Reset
o o
B2 Bl
BO Jl
JO
B2 Bl
BO Jl
JO
DC Characteristics
Limits
Parameter
Symbot
Min
1)p
II. Unit
O.7Voo
Inpul VoHeae High
V,L
Voo
V
O.8VDD
Voo
V
o
O.3Voo
V
-10
,.A
Inpul Leakage Current High
o
o
0
0
Oulp~
Vollega High
Test
CondHions
EXceptW
VI
Input Leakage Current Low
VOH1
0.5
VOH2
Voo -
= Voo
V, =OV
BUSY. 0 0-03•
Voo -
o
14. "Clear Cursor"
T.st
Conditions
T.= -10"Cto +70"C;VDD = +5V±10%
Inpul Vollege low
13. "Write Cursor"
Umlts
Min Typ Max Unit
~ln~p~~ca~~~CIle~n~~~______~C~IN~________~I~O__~PF~f=IMHZ
10. "Set Character Mode with 0
0
0
0
0
Left Entry·
......:'---'--"---'--=--=----=:;--=--
o
SYllibol
'::~o=~"':::':pec-=ca::O:=n~=ta:::-=---------,~",:",UT-'-----------=~=-------"'::'----- ~:=~::ins
o o
o
11. BitSet
-0.3Vto +7.0V
- 0.3V to Voo + 0.3V
- 0.3V to VDO + 0.3V
-10°C to + 70°C
- 65°C to + 1500C
Supply Voltage, VDO
Input Voltage, V,
Output Voltage, Vo
Operating Temperature, TOPT
Storage Temperature, T8m
V
IOH = -400,.,.A
0.5
15. Load Immediate to
Data Pointer
16. "Set Stop Mode"
06 05 04 03 02 01
o
DO
Bii§Y, Do-D3•
~p~
0
0
0
0
0
Voltage Low
VOL1
0
0.45
VIOL
0.45
V
j.LA.
,.A
Oulpul Leakage Cu,,,,,,1 High
ILOH
10
Note: *Newlyadded (compared to IJ-PD7227)
Output Leakage Current Low
ILOL
-10
Command Summary
Row Output Impedance
RROW
Row/Column Output Impedance RROW/COL
3.0
Instruction Code
Binary
Mnemonic
SFF
SMM
DISP OFF
DISP ON
lDPI
SRM
SWM
SORM
SANDM
SCMl
SCMR
BSET
BRESET
WRCURS
ClCURS
STOP
Column Output Impedance
Set Mul~plexlng Mode
Display Off
DI.playOn
Load Data Pointer With
Immediate
Set Road Mode
SetWrIle Mode
Set OR Mode
Set AND Mode
Set Character Mode with
Left Enlry
Set Character Mode wHh
Righi Entry
BlISet
BII Reeot
Write Cursor
Claar Cursor
Set Stop Modo
1 0 02 0,00
1 1 02 0,00
o
1
0
0
0
0
1
0
0
1
De DIS 0 4 03 02 0, Do
0 1 1 0 0 0 0 , 00
0 1 1 0 0 1 0 , 00
0 1 1 0 1 0 0 , °0
0 1 1 0 1 1 0 , 00
o
1
1
1
0
0
0
1
o
04 D:, D2 0, Do
1 0 4 0 3 O2 0, Do
1 1 1 1 0 1
1
1
1
0
15
200
400
,.A
20
,.A
0
looz
10-14
la-IF
08
09
8O·Bl
Co-Fl
60-Q
64-67
68-6B
= Voo
AC Characteristics
1.imII.
Perameter
71
4O-5F
2O-3F
7D
7C
00000101
Ie = 400kHz
SIop_.
ClK = OV
T. = -10"Cto +70"C;VDD = +5V ± 10%
Common Operation
6C-6F
0111001072
1
10
kO
kO
kO
10
ReOL
Supply Current
o
V
8
Vo
V, = OV
Operating Mode,
Operation
set Frame Frequency
Voo
= 1.7mA
SYNC, IOL =
l00,.A
Symbol Min Typ ..... Unit
Clock Frequency
fc
100
CI_ Pul.. Width HIgh
tWHC
350
n8
Clack Pul.. Widlh Low
t wLC
350
ns
BUSY Delay Tlma from CS •
Iocas
cs t Delay Time
to 'Iill§V floating
2
""
Iocs..
4
~s
CS High Level Time
tWHCS
SYNC Load Capaclta_
ClOY
Data Set-up Time 10 RESET j
I ...
Data Hold Time from RESET ~
6-90
.....
Test
Conditions
1100 kHz
~.
100
pF
CL =50pF
CL
= 50pF
/-LPD7228
AC Characteristics (Cont.)
Serial Interface Timing Waveforms (Cont.)
T. = -10"Cto +7O"C;Voo = +5V ± 10%
AC Test PoInts
Serial Interface Operation
LImits
......meter
Symbol
Min
Unit
SCKCyel.
Icy,
0.9
SCK Pulse Width High
tWHK
400
SCK Pulse Wldlh L.ow
IWLK
400
ns
SCK" Hold 11m. from BUSY 1
IHa'
0
ns
51 Set-up 11m. to SCK 1
lsi,
100
ns
SI Hold llme from SCK 1
tHKI
250
SO Delay llme from §CK j
10'0
~~~h~~mefrom
1..8
BUSY Low-leveillme
1wL.
64
O.3VOD
Clock Waveform
ns
18
x::
O.7VOD
~p=.~
D.3VOD
.
.
.
ns
CL = 50pF
C, = 50pF
Ille
CLOCK
.s
t,,'D
CS Hold 11m. from Elghlh SCK 1
Conditions
.s
320
.....
ciii Set-up 11m. to First SCK j
ciii Hold 11m. from Elghlh SCK 1
=x
O.7VDO
Teol
TJp """
....es
AC Characteristics (Cont.)
T. = -10"Cto +70·C;Voo = +5V ± 10%
Parallel Interface Operation
Interface TimIng waveforms
Umlts
PIIrameter
Symbol
!:~!mmand Set-up Time
IA
Input£2..mmand Hold Time
from STB j
Min
Test
Typ Max Unit
Conditions
100
ns
CL = 80pF
= 20pF
I.
90
ns
C,
230
ns
CL - 80pF
Input Data Hold Time from STB t
Ie
10
ns
CL
Output OBIs Delay TIme
lACe
90
650
n.
CL = 80pF
150
n.
CL
Inpul Data Set-up TIme lo!!Tlf1
50
Output 0818 Hold Time
t"
0
STB Pulse Width Low
1st.
700
STB High Level Time
isH
STB Hold 11m. from BUSY 1
t Has
=~~~mefrom
1os8
C/o Set-up Time 10 First STB !
Is..
CID Hold TIme from
Second S'fij 1
....D
CS Hold T,m. from Second 5TB t
I HSCS
.
.
..
= 20pF
-
20pF
ns
Parallel Interface Timing Waveforms
.s
.s
~D --~--~----------~r--r---
Serial Interface Timing Waveforms
liiJliY _~...~+----------t-\
-U-IWHes
__+_""',.._______
:=i-::1L L
---+--~-~ ~
I
---=ME
K
81
USB
~t::0
SO
----------
Package Outlines
For information, s_ Package Outline Section 7.
Plastic Minlflat, .,.P07228G
~r-
~
0 ...0 3
'wLK
10KB
lttKI
~~B--
__ _
----w..
722805-7·83-CAT-L
6-91
Notes
6-92
j.LPD7261
HARD·DISK CONTROLLER
NEe
Pin Configuration
Description
The fLPD7261 hard-disk controller is an intelligent microprocessor peripheral designed to control a number of
different types of disk drives. It is capable of supporting
either hard-sector or soft-sector disks and provides all control signals that interface the controller with either SMD disk
interfaces or Seagate floppy-like drives. Its sophisticated
instruction set minimizes the software overhead for the host
microprocessor. By using the DMA controller, the microprocessor needs only to load a few command bytes into the
fLPD7261 and all the data transfers associated with read,
write, or format operations are done by the fLPD7261 and
the DMA controller. Extensive error reporting, verify commands, ECC, and CRC data error checking assure reliable
controller operation. The fLPD7261 provides internal
address mark detection, ID verification, and CRC or ECC
checking and verification. An eight-byte FIFO is used for
loading command parameters and obtaining command
results. This makes the structuring of software drivers a
simple task. The FIFO is also used for buffering data during
DMA read/write operations.
SYNC
Vee
RIWOATA
Bn
(RGATE)
RfWCLK
BTO
(WGATE)
RESET
CLK
INT
fC
Features
o
o
o
o
o
o
o
o
o
o
o
o
o
o
Flexible interface to various types of hard-disk drives
Programmable track format
Controls up to 8 drives
Parallel seek operation capability
Multisector and multitrack transfer capability
Data scan and data verify capability
High-level commands, including:
READ DATA
SEEK (normal or buffered)
READ ID
RECALIBRATE (normal or buffered)
WRITE DATA
READ DIAGNOSTIC (SMD only)
FORMAT
SPECIFY
SCAN DATA
SENSE INTERRUPT STATUS
VERIFY DATA SENSE UNIT STATUS
DETECT ERROR
VERIFY ID
CHECK
NRZ or MFM data format
Maximum data transfer rate: 12MHz (SMD mode)
Error detection and correction capability
Simple I/O structure: compatible with most
microprocessors
All inputs and outputs except clock pins are TTLcompatible (clock pins require pullup)
Single + 5V power supply
40-pin dual-in-line package
INDEX
OREQ
SCT
(PCL)
USTG
(PCE)
cs
SSTG
(OSO)
AD
BOIR
(SKC)
WR
TG3
(TRKO)
AO
TG2
(READY)
DO
TGI
(WFLT)
01
BT2
(OSO)
02
BT3
(OSI)
03
BT4
(HSO)
04
BT5
(HS1)
05
BT6
(HS2)
06
BT7
(RWC)
07
BT8
(STeP)
GNO
BT9
(BOIR)
Note: Signals shown In parentheses are used when the
~PD7261 IS In the
floppy-like mode.
Pin Identification - Host Interface Pins
Pin
No.
4
Name
Function
110
Reset input. When high, it forces the device into an
idle state. The device remains idle until a command
is Issued by the system.
RESET
INT
o
OREQ
o
TC
CS
Interrupt request to the system, set high for
request.
DMA request. Normally low, set high to request a
transfer of data between the disk controller and
memory.
This is used as a terminal count input durmg OMA.
Chip select. When low, It enables reading from or
writing Into the register selected by AO.
Read strobe. When low, selected register contents
are read.
• cci.ccwr"'IIIO:C.nC-;i"'n1~o'~he:C--
---;:;---"""----;-----;;Wr""'lte
strO~be-::-.7.W;;:chec::n7Io:c:w:-c.dcc
••cc
10
Wl'I
RO
selected register.
11
12-19
Rev/1
6-93
:::t;~~::~~~:~tb~s~nC:W~:~i~~~t~:n.
AO
DO-07
1/0
GNO
P.S.
20
36
INDEX
37
CLOCK
40
Vee
P.S.
command/status register is setected; when low, the
data buffer is selected.
Data bus port, to be connected to data bus.
Ground.
This signal indicates the beginning of sector zero.
External clock input, used a& timing clock for the
on-chlp processor.
+ 5V power supply.
J.LPD7261
Disl: Interface Pins (Defined by mode)
Pin
No.
SliD
Name
SYNC
PLO LocklRead ~ Enallle
RIW DATA
21
22
23
BT7, RWC
BT8,HS2
25
28
BT5,HS1
27
_"taData
Read CI_ I Servo Clock
RlWCLK
BTB,DIR
BT8, STEP
24
BT4,HSO
BT3,DS1
Blt91 UnHSelectad
Read Clock I Wrlta Clock
Direction In
BH8 I Seek Enel
BH71 W R _ I (SR7)
Stap Pulse
Reduced W\'fte Cu""",
B"a I (AMFounel) I (SRa)
B"5 I Unit Reedy I (SR5)
BH41 On Cylinder I (SR4)
H_SeIecI22
m,WFLT
30
'flit READY
31
TG3, TAKO
32
BDIR,SKC
_SeIecI20
D.... Select 20
Wrlta Fau"
OlIve Selectad
Pnocomp Lata
B'i'ii, DSD
(SR setect Tiii)
tmtt,PCL
35
SCT, PCE
Unit select tag
Secto, I (SR1)
38
38
INOEX
BTO,WGATE
BT1,RGATE
Index I (SAO)
BHO
Index
BH1
ReadGete
wrlta Geta
Not_ The mulbfunctlOr1 signals above are defined by the use of the Specify command By setting
the SSEe bit In the mode byte of the Specify command to a one the floppy-like mode IS
selected To better understand the functIOns of these pms, refer to the ,ndMdual mstructlons
and to the SMD and floppy-like Interface defln~lOns
to
+7IrC
10
+15O"C
- 0.5V
to
+7.0V
*COMMENT: E~posing the device to stresses above
those listed in Absolute Maximum Ratings could cause
permanent damage_ The device is not meant to be
operated under conditions outside the limits described
in the operational sections of this specification_ Exposure to absolute maximum rating conditions for
extended periods may affect device reliability_
AC Characteristics (Processor Interface)
RiWClK
RGATE
R/WDATA_
WGATE
SYNC
SCT
Symbol - :
.=n~LImH=::::~
.
..u:::~cy
90
CLOCK Low TIme
~CH
32
no
CLOCK High TIme
CLOCK RI.. TIme
CLOCK Fall TIme
AD, eli Setup to1115
AO, CS Hold from Jifi
~CL
32
nl
ClK
RESET
Processing Unit
Data Buffer
8-byte FIFO
-------'----0-1
INT __----_---1
10
10
IA•
tRA
tRA
Deta Delay from iIlI
Output Float Delay
Data Dotay from AD, C§
lAO
150
to.
100
150
Wii Pul.. WkHh
Data Sotup to Wli
Data Hold from Wi!
rry
Time from
200
lAD
lAW
200
100
RESET Pul.. Width
IRST
TC Pul.. WkHh
INT Detay from WI!
!wi
Ire
ns
ns
ns
no
na
nl
nl
two
1m, Iov
no
nl
no
nl
no
na
tWA
Iww
low
DREQ Dolay lrom WIi
DREQ Dotay from RD 1
DREQ Delay from RD2
Command!
Status Reg.
~.
~F
Teot
CondHlona
nl
AD Pula Width
AD,
Sotup to WI!
AD, CS Hold from WI!
Format
Controller
Unit
CLOCK Cycle
a
Block Diagram
00-07
O"C
-WC
Voltage on any Pin with Respect to Ground
",,.meler
Seek Complete
34
OREQ
QperaIIng Temporalu"
Storage Temperature
1I'ackOOO
Direction
33
39
Heed Select 2'
B"31 SeekEnor I (SR3)
B"21 Fault I (SR2)
BT2,08O
28
28
Absolute Maximum Ratings·
FIOIIPV"like
nl
200
100
100
~CY
no
IWA!
200
250
no
no
I.A"
250
no
lRAII
150
ns
AC Characteristics (Floppy·like Interface)
Readl
Write
Control
Port
Control
Internal
RAM
Symbol
ROM
(Control Firmware)
83
RlWCLK Low TIme
RlWClK High TIme
RiWClK RI.. TIme
30
DC Characteristics
SWlllbol
--:M=ln~IJmH=::::~:::...
~
Input Low Voltage
Input Low VoHoge
VIL
V,L,
0_5
0_5
InputHlghVoltage
Input High Voltage
V.,
VIH,
+2.0
+3_3
Output Low Voltage
VOL
Output Low Voltage
VOL'
Output High Voltage
Vo.
Output High _ge
Vo.,
Input Leakage Current
Unit
+ 0_8
+0_6
v
v
Vee
Vee
V
V
+0.45
V
Teot
CqncIIHlona
All except ClK
ClK
Alloxcept CLK, RESET
CLK, RESET
..,,-+2.OmA
OREQ,INT, DO-D7
V
..,,=+1.6mAall
~~~ DREQ, INT,
+2.4
V
I"" -100,,", DREQ,
INT, DO-D7
+2A
V
+OAS
~L
IOH - 5O,ttc all
~L1
Output Leakage Cu,,,",
.."
Input Capacitance
elN
Output Capacftence
VO Copacltance
Cour
Supply CUrrent
Icc
Supply Vonaga
Vee
CIO
+4.5
no
tc..
300
nl
lew.
150
no
70
no
150
no
SYNC Dalay from
RiWCLK
Icsy
080, OSI Sot up to §'iiii Iossr
DIRSotuplo!lTEJl'
IDiST
Pul.. Width
tsr.
sm
~OS1 Hold from
250
200
69
~A
Vour Vee to 0.45
pi
pi
pi
f_1MHz
mil Cycle Porlod
Isrca
570
1sT...
200
200
100
100
±500
±10
15
15
20
no
ISTP•
21-34
VIN Vee toO.45
380
mA
5.5
V
1-1 MHz
DlR Hold from li'i'EJ5'
080, OSI Hold from SKC Is...
DlR Hold from SKC
""""
080, DS1 set up to fifi5 t COOT•
~DS1 Hotd from
SfEl5
f-1MHz
DlR Hold from
Vee - 5V ± 10%
DSO, OS1 Hold from SKC IOKDSB
DIR Hold from SKC
IsKOIe
TO = Oto7IrC
T8 - 01070"C
Note; cv
cv
cv
36
cv
cv
cv
cv
58
cv
36
66
88
36
33
200
c,n_,
Silloct
Oporatton
Inretrupr
'NT
Hood
Soloct
Dperatlon
Wii
RTZ,
DATASTB.
cy
Control
CY
CY
CY
cv
oi>cv
cv
nmlng
------'--=4 ~ ~
-
FAULTCLR.,
SERVO,
CY
J-------i::
--.Jr --------II1
Dr#Wllnterface
c,_nm,ns:fP'-
I!/W CLK
to
Sonoo
Unft
allltuo
nmlng
RlWCLK
Timing Waveforms
Host System Interface
RIW Data
('npUl)
II/W Data
Clock
(Output)
~
'"
ctt
~-W--SEEK COMPLETE
p - ' - - - - - - - - - j .::>O-~~-REDUCEO WRITE
CURRENT
Drive Interface
DIRECTION IN
The f.LPD7261 has been designed to implement two of the
more popular types of interfaces: the SMD (Storage Module Drive) and the floppy-like Winchester drive which has
come to be known as the ST-506 (Seagate Technology)
interface. The desired interface mode is selected by the
specify command.
~------~'::>o-~--WRITEG~E
HEAD SELECT 0
p - - - - - - - - - j ~><>--~~- HEAD SELECT 1
7406
HEAD SELECT 2
STEP
DiiiVES'E[T
Floppy-like Interface
DRIVESEL2
In the floppy-like mode the f.LPD7261 performs MFM encoding and decoding at data rates to 6 MHz and provides all
necessary drive interface signals. Included internally is circuitry for address mark detection, sync area recognition,
serial-to-parallel-to-serial conversion, an a-byte FIFO for
data buffering, and circuitry for logical addressing of the
drives. External circuitry required consists of control signal
buffering, a delay network for precompensation, a phase
lock loop, a write clock oscillator and a differential transceiver for drive data. The floppy-like interface can be
implemented with as few as 12 to 14 additional SSIICs.
DRIVESEL3
V2 LS138
7407
DRIVESEL4
Note: ED "" 220n Pull-up/330n Pull-down terminator
SMD Interface
In the SMD mode the f.LPD7261 will support data rates
to 12 MHz in the NRZ format. All control functions necessary for an SMD interface are implemented on-chip with
de-multiplexing of a data lines performed externally by a
single a-bit latch. A small amount of logic is required to
multiplex the data and clock lines, and differential drivers
and receivers are required to implement the actual interface. Depending on individual logic design and the number
of drives used, the SMD interface may be implemented with
as few as 12 ICs.
6-99
IJ-PD7261
2.5K-internal ROM is selected and executed. Some of
these commands are executed by the command processor
without involvement of the format controller. When data
transfers to and from the disk are made, the command
processor loads the appropriate microcode into the format
controller, then relinquishes control. When the data transfer
is complete, the command processor again takes control.
One other important function that the command processor
performs is managing the interface to the disk drives. The
command processor contains an I/O port structure similar
to many single chip microcomputers in that the ports may
be configured as input or output pins. Depending on the
mode of operation selected by the Specify command, the
command processor will use the bidirectional I/O lines for
different functions.
,,"PD7261D SMD Interface
SYNC~
r - - - r - WRITE CLOCK
r-- SERVO CLOCK
R!WCLK~
R/WOATA 2
BTO 38
Bn 39
r- READ CLOCK
'-- WRITE DATA
Y
r- READ DATA
-
-
TX
and - I NDEX
RX
INDEX 36
r- SECTOR
SCT 35
TGl 29
-
-
TG2 30
-
TG3 31
SSTG 33
8T2 28
8T4 26
8T5 25
BT6 24
8T7 23
TAG 2
TAG 3
Command Register
SR SELECT TAG
This register is a write o~register. It is selected when the
AO input is high and the CS input is low. There are two kinds
of commands: disk commands and auxiliary commands.
Each command format is shown below.
An auxiliary command is accepted at any time and is immediately executed, while a disk command is ignored if the onchip processor is busy processing another disk command.
A valid disk command causes the processor to begin
execution using the parameters previously loaded into the
data buffer. Disk commands and the parameters needed
are described in the next section.
BIT 2
r-r-8-Blt r-Latch
r-r--
BT8 22
BT9 21
TAG 1
- - UNIT SELECT TAG
USTG 34
BT3 27
BITO
BIT 1
TX
-
BIT3
-
BIT5
-
BIT6
-
81T7
-
f--
BIT 4
BIT8
~f--~- 81T9
BDIR 32
~
DE
RX
Disk Command Byte
FAULT
- SEEK ERROR
- ON CYLINDER
- UNITREACY
- AM FOUND
- WRITE PROTECTED
-- SEEK END
~c---- UNIT S'ELECTEO
UNIT SELD
I
I
TX
UNIT SEL 1
UNIT SEL 2
Note: TX and AX are differential drivers and receNers
Internal Architecture
CC4
CCO
UA2
UA1
UAO
Umt Address (UA)
CC4-CCO
0
0
0
0
0
0
0
0
Command Processor
o
o
o
CC1
Command Code
The fLPD7261 can be divided into three major internal
logic blocks: command processor; format controller; microprocessor interface.
The command processor is an 8-bit microprocessor with its
own instruction set, program ROM, scratchpad RA!V1, ALU,
and I/O interface. Its major functions are:
To decode the commands from the host microcomputer
that are received through the 8-bit data bus;
To execute seek and recalibrate commands;
To interface to the drives and read the drive status lines;
o To load the format controller with the appropriate microcode, enabling It to execute the various read/write data
commands.
The command processor microprocessor is idle until it
receives the command from the host microcomputer. It then
reads the parameter bytes from the FIFO, and loads them
into its RAM. The command byte is decoded and, depending on its opcode, the appropriate subroutine from the
CC2
CC3
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
1
0
1
1
0
0
0
1
0
Note: CD means the UA field
X
X
X
X
X
[B)
[B]
[5)
[51
[51
X
X
X
X
X
X
0
IS
(Auxiliary Command)
SENSE INT. STATUS GJ
SPECIFY GJ
SENSE UNIT STATUS
DETECT ERROR GJ
RECALIBRATE
SEEK
FORMAT
VERIFYID
READID
READ DIAGNOSTIC
READ DATA
CHECK
SCAN
VERIFY DATA
WRITE DATA
000
[Bjlndlcates buffered mode when set
[51 mdlcates skewed mode when set
Format Controller
The format controller is built with logic that enables it to
execute instructions at very high speed: one instruction per
single clock cycle. The major functions it performs are:
o
o
o
o
6-100
Serial-to-parallel and parallel-to-serial data conversion;
GRG and EGG generation and checking;
MFM data decoding and encoding;
Write precompensation;
J.LPD7261
o Address mark detection and generation;
o ID field search in soft-sector format;
o DMA data transfer control during read/write operations.
The major blocks in the format controller are the sequencer
and the serial/parallel data handler. The sequencer consists of a writable control store (32 words by 16 bits), a
program counter, branch logic, and the parameter register.
The serial/parallel logic consists of a parallel-to-serial converter for disk write operations, a serial-to-parallel converter for disk read operations, precompensation logic for
writing MFM data, comparator logic that locates sync fields,
address marks, and ID fields. There is also comparator
logic that is used during Verify Data commands.
Block Diagram of the Format Controller
Write Data
Precomp. Early
Precomp. Late
RIW C l o c k - - - - - f - - - - - 4 - - - - I
Read Oata
Data
Buffer
RAM
Microprocessor Interface
Read/Write Control
The internal registers are selected via the truth table shown.
Register Selection Table
CS
0
0
0
0
0
0
AO
0
0
RD
0
0
1
X
X
X
1
X
0
WR
1
0
1
0
1
X
0
Selection
Data Buffer
Register CD
Status Register
Command Register
Don't Care
Inhibited
Note: memory: Read ID, Read Diagnostic,
Read Data
Data being read from a disk or external memory is temporarily stored in the data buffer (a-bytes maximum), and is
transferred to external memory or a disk respectively.
Data transfers are terminated externally by a reset signal or
by a read or a write data operation coinciding with an active
terminal count (TC) signal. They are also terminated internally when an abnormal condition is detected or all the data
specified by the sector count parameter (SCNT) has been
transferred.
Data transfers are accomplished by RD or WR signals to
the f1PD7261 when DREO is active. During Read operations, DREO goes active when the FIFO contains three or
more bytes. If the FIFO contains three bytes and an RD
pulse is issued, DREO goes low within t RAI1 . DREO
will stay active on the final sector until the final byte is
extracted. In this case, DREO goes low within t RAI2 . During
Write operations DREO is asserted as soon as a WRITE
DATA command is accepted. DREO remains high until the
FIFO contains six bytes, at which time it goes low within
tWAI ' DREO corresponds to FIFO almost-full and FIFO
almost-empty as implemented in the f1PD7261. This has
been done so that a fast DMA controller may actually overrun the FIFO by one or two bytes without harm.
Recalibrate
01018
~----------------1ST"
The read/write heads of the specified drive are retracted
to the cylinder 0 position. 1ST' is available as a result byte
only if polling mode is disabled. See SPECIFY.
a. Hard Sector
An RTZ (Return to zero) signal is asserted on the bit-6
line with the TAG-3 bit being set. Then the CEH bit of the
status register is set indicating a normal termination of
the command.
After this command is given, the HDC checks the Seek
End, Unit Ready, and Fault lines of the drive continually
6-101
II
•
f-LPD7261
until an active signal is detected on these lines. Then the
SRQ bit of the status register is set indicating that a Sense
Interrupt Status command should be performed. Each bit of
the 1ST (Interrupt Status) byte is set according to the result,
in anticipation of the Sense Interrupt Status command.
b. Soft Sector
There are four different ways to implement the Recalibrate
command when the ST506 interface mode has been specified. Both polling and nonpolling modes of operation are
provided, with both normal or buffered Recalibrate commands available in either mode.
b-1. Normal Mode with Polling
The CEH bit of EST is set to "1" immediately after the
Recalibrate command is issued (a Recalibrate command
may now be issued to another drive). The HOC now begins
generating step pulses at the specified rate. The PCN for
the drive is cleared and the TRKO signal is checked while
stepping pulses are sent to one or more drives. When
TRKO is asserted, the SEN (Seek End) bit of the 1ST
(Interrupt Status) byte is set and the SRQ bit of the status
register is set. This causes an interrupt and requests that a
Sense Interrupt Status command be issued. If 1023 pulses
have been sent and TRKO is not asserted, then the SRQ bit
is again set, but with the SER (Seek Error) bit of the 1ST
byte set. The Ready signal of each drive is checked before
each step pulse is sent, and the Recalibrate command is
terminated if the drive enters a not-ready state, whereby
the NR bit of the 1ST byte is set to ''1:'
b-2. Normal Mode with Polling Disabled
Operation is similar to that in section "b-1;' but the CEH
and CEl bits of the status register are not set until either
the SEN (Seek End) or the SER (Seek Error) condition
occurs. The SRQ bit is not set when polling is disabled, and
the 1ST byte is now available as a result byte when the
Recalibrate command is terminated (see "Preset Parameters and Result Status Bytes"). It is not possible to overlap
Recalibrate operations in this mode.
b-3. Buffered Mode with Polling
This mode operates in a manner similar to that described
in section "b-1;' but with the following differences:
1. 1023 step pulses are sent at a high rate of speed
(approximately 50ILS between pulses)
2. After the required number of pulses are sent, the CEH
bit is set, and then additional Recalibrate or Seek commands will be accepted for other drives
3. The SRQ bit is set when the drive asserts SKC, which
causes the SEN bit of the 1ST byte to be set
4. If SEN is not set within the time it takes to send 1023
"normal" pl:llses (Le., when in normal stepping mode),
then SER of the 1ST byte is set.
b-4. Buffered Mode with Polling Disabled
1023 stepping pulses are immediately sent after the
Recalibrate command is issued. CEH and/or CEl is set
when SEN or SER occurs. SEN is set when TRKO from
the addressed drive is asserted. SER is set if TRKO is not
asserted within the time required to send 1023 "normal"
pulses. The Recalibrate command will be terminated
abnormally if a not-ready condition occurs prior to SEN
being set. The SRQ bit of the status register is not set. The
1ST byte (Interrupt Status) is available as a result byte when
either CEH or CEl is set.
Seek
I
PCNH
01108
PCNL
•
1ST"
PCNH = Physical Cylinder Number, High Byte
PCNL = Physical Cylinder Number, Low Byte
The read/write heads of the specified drive are moved
to the cylinder specified by PCN!"! and PCNL. IST* is
available as a result byte only if polling mode is disabled.See SPECIFY.
a. Hard sector
The contents of PCNH and PCNl are asserted on the bit-O
through bit-9 output lines of the SMD interface with the
TAG-1 control line being set. (The most significant six bits of
PCNH are not used.) The CEH bit of the status register is
then set, and the command is terminated normally.
The HOC then checks the Seek End, Unit Ready and
Fault lines of the drive continually until an active signal is
detected on these lines. The SRQ bit of the status register
is then set requesting that a Sense Interrupt Status command be performed. Each bit of the 1ST (Interrupt Status)
byte is set appropriately in anticipation of the Sense Interrupt Status command.
b. Soft Sector (Normal Stepping, Polling Enabled)
In this mode, the CEH bit of the status register is set to
"1" as soon as the Seek command is issued. This allows
a Seek or Recalibrate command to be issued to another
drive. The HOC now sends stepping pulses at the specified
rate and monitors the Ready signal. Should the drive enter
a not-ready state, the SER bit of the 1ST byte is set and the
SRQ bit of the status register is set, causing an interrupt
and requesting a Sense Interrupt Status command. When
the drive asserts the Seek Complete (SKC) Signal, the SEN
bit of the 1ST byte is set and the SRQ bit of the status register is set, again requesting service.
c. Soft Sector (Normal Stepping, Polling Disabled)
Stepping pulses to the drive begin as soon as the Seek
command is accepted. The Ready signal is checked prior
to each step pulse. If the drive enters a not-ready state the
Seek command is terminated abnormally (CEl 1), and
SER of the 1ST byte is set. If the Seek operation is successful, the Seek command will be terminated normally (CEH =
1) when the drive asserts SKC (Seek Complete). The SEN
(Seek End) bit of the 1ST byte is set and the 1ST (Interrupt Status) byte is available as a result byte. The Sense
Interrupt Status command is not allowed (SRQ is not set),
nor can Seek operations be overlapped in this mode.
d. Soft Sector (Buffered Stepping, POlling Enabled)
As soon as the Seek command is accepted by the HOC,
high-speed stepping pulses are generated. As soon as the
required number of pulses are sent, CEH is set to "1;' indicating a normal termination. Another Seek command in the
same mode may now be issued. (The drive is now controlling its own head positioner and asserts SKC when the
target cylinder is reached.) If the drive has not asserted
SKC (Seek Complete) within the time it takes to send the
required number of pulses in normal stepping mode, or if
the drive enters a not-ready state, then the SER bit of the
1ST byte and the SRQ bit of the status register are set.
Otherwise, the SEN bit of the 1ST byte is set, along with
SRQ of the status register.
6-102
=
j.LPD7261
e. Soft Sector (Buffered Stepping, Polling Disabled)
In this mode, the appropriate number of high-speed stepping pulses are sent as soon as the Seek command is
issued. If the drive enters a not-ready state, or if SKC (Seek
Complete) is not asserted within the time it takes to send
the required number of pulses in normal stepping mode,
then the Seek command is terminated abnormally (CEL =
1). The 1ST byte is available as a result byte and the appropriate bit is set; i.e., SER or NR (Not Ready). If the Seek
operation is successful, the Seek command is terminated
normally (CEH = 1) and the SEN bit of the 1ST byte is set.
The 1ST byte is available as a result byte. The Sense Interrupt Status command is not allowed (SRQ is not set), nor
can Seek operations be overlapped in this mode.
ID bytes of specified sectors are read and compared with
the data that are accessed from local memory via DMA
control. The first sector that is verified is specified by PHN
and PSN when a hard-sector disk is used. For soft-sector
disks, only PHN is given and the Verify ID command begins
comparisons with the first physical sector on the track.
Byte comparisons continue as long as successful or until
the sector count is zero or a CRC error is found.
When using a hard-sector drive, it is possible to have the
HDC verify a Skewed ID field by setting the Skew bit of the
command byte. Refer to the Format Write section, given
earlier, for details.
ReadlD
Format
1001S
PHN
(PSN)
EST
seNT
SCNT
DPAT
GPLl
PHN
PSN
SeNT
EST
SeNT = Sector Count
OPAT = Data Pattern
GPL 1 = Gap Length 1
GPL3
= Gap Length 3
EST
=
Error Status
This command is used to write the desired ID and Data
format on the disk.
a. When using hard-sector drives, this command will begin
format-writing at the sector specified by PHN and PSN,
which are loaded during command phase.
When soft-sector drives are specified, this command will
begin format-writing at the sector immediately following the
index pulse on the track specified by PHN.
In either case, data transmitted from the local memory by
DMA operation is written into the ID field, and the Data field
is filled with the data constant specified by DPAT until DTL
(Data Length) is zero. DTL is established during the Specify command with DTLH and DTLL. The Sector Count,
SCNT, is decremented by one at the end of the FormatWrite operation on each sector. The following bytes are
required by the HDC for each sector: (FLAG), LCNH, LCNL,
LHN, and LSN. FLAG is omitted on soft-sector drives.
These bytes are transferred by DMA.
b. The above operation is repeated until SCNT is equal
to zero. The execution of the command is terminated normally, when the content of SCNT is equal to zero and the
second index pulse has occurred.
c. When using a hard-sector drive, it is possible to write the
ID field displaced from the normal position by 64 bytes by
setting the Skew bit of the command byte ((S) = 1). This is
useful when defective media prevent writing in the normal
area of the sector.
d. Items d, e, and h of the Read Data and item d of the
Write Data command are identical for this command. Refer
to these items (which appear later in this section) for the
remaining Format Write detail.
Verify ID
10005
PHN
PSN
SeNT
EST
I
PHN
(PSN)
EST
SCNT
SCNT
.
[GPL3]
= PhYSical Head Number
= Physical Sector Number
PHN
PSN
I
= Physical Head Number
= Physical Sector Number
= Sector Count
= Error Status
ID bytes of specified sectors are read and transferred to
local memory by DMA.
Hard-sector disks: Beginning with the sector specified by
PHN and PSN, the ID bytes of each sector are read until an
error is found or the SCNT has reached zero.
It is also possible to perform the above operation with
skewed ID fields by setting the Skew bit of the command
byte. This will allow reading ID fields that have been shifted
by 64 bytes by the Write Skewed ID command.
Soft-sector disks: This command will begin checking ID
fields immediately following the index pulse and will continue until one valid ID field is read, or until the second
index pulse is detected.
'1 ~
R
_ea_d__D_ia_9,n_o_s_t_ic____________________________
r
10l0X
I
PHN
PSN
.
EST
= Physical Head Number
= Physical Sector Number
= Error Status
This command is implemented only for hard-sector disks.
The desired physical sector is specified, and the data field
will be read even if the ID bytes of that sector contain a
CRC error. Only one sector at a time may be read by this
command.
PHN
PSN
EST
Read Data
PHN
EST
PHN
FLAG
LCNH
LCNL
LHN
LSN
SeNT
EST
(FLAG)
PHN
LCNH
LCNL
LHN
LSN
SCNT
(FLAG)
LCNH
LCNL
LHN
lSN
seNT
= PhYSical Head Number
= Flag Byte, Hard-sector 10 Field Only
= Logical Cylinder Number, High Byte
= Logical Cylinder Number, Low Byte
= Logical Head Number
= Logical Sector Number
= sector Number
= Error Status
This command is used to read and transfer data via DMA
from the disk to the local memory.
PHN
(PSN)
EST
SCNT
.
= Physical Head Number
= Physical Sector Number
= sector Count
= Error Status
SCNT
a. The HDC reads data from the specified sector which is
determined by the following preset parameters: FLAG (for
hard sector only), LCNH, LCNL, LHN, and LSN. The drive is
selected by UA (Unit Address) in the command byte. The
6-103
ail
f-1PD7261
HOC then transfers the read data to the local memory via
OMA operation.
b. After reading each sector, the HOC updates the SCNT
and LSN to point to the next sector, and repeats the above
described operation until SCNT is equal to zero. During the
above read operations, if LSN is equal to ESN, the HOC
updates LSN, and continues the read operations after
relocating the head (track) specified by LHN.
c. The HOC abnormally terminates the execution of this
command, if SCNT is not equal to zero when the HOC
reads out the data from the last sector (LSN = ESN and
LHN = ETN). The ENC (End of Cylinder) bit of EST (Error
Status) is set to one in this situation.
d. The HOC will terminate this command if a Fault signal
is detected while reading data. The HOC will set the EQC
(Equipment Check) of the EST (Error Status) byte when
this occurs.
e. The HOC will terminate this command abnormally if the
Ready signal from the drive is not active or becomes notactive while a Read Data command is being performed.
The NR (Not Ready) bit of the EST (Error Status) register
will be set to one in this case.
f. The HOC will end this command abnormally if it cannot
find an AM (Address Mark) (soft-sector mode) or a SYNC
byte (hard-sector mode) of the 10 field before three index
pulses occur. Under these conditions, the RRQ (Reset
Request) bit of the STR (Status Register) will be set. In
order to perform further disk commands the HOC will have
to be reset because the Format Controller is hung up
looking for an AM or SYNC byte.
g. ECC mode: If the HOC detects an ECC error during a
read operation, it will execute the following operations:
First, the HOC decides whether or not the error is correctable by checking the syndrome of the error pattern. If the
error is correctable, the HOC terminates the command in
the normal mode after setting the OER (Data Error) bit of
EST register to one. The host system can input the erroraddress and the error-pattern information by issuing the
Detect Error command. If it is not a correctable error, the
HOC will terminate the command in the abnormal mode
after setting the OER bit of the EST register to one.
CRC mode: If the HOC detects a CRC error on a sector
during the read operation, the HOC will terminate the command in the abnormal mode after setting the OER bit of the
EST register to one.
h. If the HOC detects an overrun condition during a Read
Data operation, the OVR (Over Run) bit of the EST register
is set. (An overrun condition occurs when the internal data
FIFO is full, another data byte has been received from the
disk drive, and a OMA service does not occur.) The command is then terminated in the abnormal mode.
i. If the HOC cannot find the desired sector within the
occurrence of two index pulses, the NO (No Data) bit of the
EST register is set to one and the command is terminated
in the abnormal mode.
j. If TC (Terminal Count) occurs during a Read Data command the OMA transfers to the local memory will stop.
However, the HOC does continue the read operation until
SCNT has reached zero or any other errors have been
detected.
k. If the Read Data command has been successfully
completed, the result status will be set indicating such,
and the result status bytes will be updated according to the
number of sectors that have been read. The logical disk
parameters - LSN, LHN, and LCNL - are incremented
as follows:
LSN is incremented at the end of each sector until the
value of ESN is reached. LSN is then set to 0 and LHN is
incremented. If LHN reaches the value of ETN, then LHN
is cleared and LCNL is incremented.
In other words; if a Read or Write operation is terminated
normally, the various parameters will point to the next logical sector.
If the command is terminated in the abnormal mode, the
result status bytes will indicate on which sector, cylinder,
and head the error occurred.
I. If the HOC cannot detect the Address Mark (soft sector)
or SYNC bytes (hard sector) immediately following the VFO
Sync in the data field, the HOC will set the MOM (Missing
Data Mark) bit of the EST register to one, and will terminate
the command in the abnormal mode.
Check
PHN
(FLAG)
LCNH
LCNL
LHN
LSN
SCNT
EST
PHN
(FLAG)
LCNH
LCNL
LHN
LSN
SCNT
= PhySical Head Number
= Flag Byte, Hard-sector 10 Field Only
= logical Cylinder Number, High Byte
= logical Cylinder Number, Low Byte
LHN = Logical Head Number
LSN = logical Sector Number
SeNT = Sector Number
EST = Error Status
PHN
FLAG
LCNH
LCNL
This command is used to confirm that the data previously
written to the medium by the Write Data command contains
the correct CRC or ECC.
a. The HOC reads the data in the sector specified by
FLAG (hard sector only), LCNH, LCNL, LHN, and LSN. The
Check command differs from the Read Data command in
that no OMA transfers occur.
With the exception of the ECC mode, the Check command
is the same as the Read Data command. Please refer to
items b, c, d, e, f, g, h, k, and I of Read Data command for
details.
b. If in the ECC mode, the HOC detects only ECC errors
and does not execute any error-correction operation even
if the ECC errors are correctable. No data transfers have
been made, and there is no data to correct.
Scan
PHN
(FLAG)
LCNH
LCNL
LHN
LSN
SCNT
EST
PHN
(FLAG)
LCNH
LCNL
LHN
LSN
seNT
PHN = Physical Head Number
FLAG = Flag Byte, Hard-sector 10 Field Only
LCNH = Logical Cylinder Number, High Byte
LCNL = Logical Cylinder Number, Low Byte
lSN
SeNT
= logical Head Number
= Logical Sector Number
= Sector Number
EST
= Error Status
LHN
a. In executing the Scan command, the HOC reads the
data from the sector specified by the preset parameters of
the command phase. The HOC then compares this data
6-104
f.LPD7261
with the data transmitted from the local memory. (The purpose of this command is to locate a sector that contains
the same data as the local memory.)
This command will terminate successfully if the data from
the disk and the data from the local memory are the same.
If they are not, the HOC updates SCNT and LSN, and
executes the above-mentioned operation again.
If the HOC cannot locate a sector that satisfies the Scan
conditions, the NCI bit of the STR will be set. The HOC tries
to compare data until the end of the cylinder has been
reached, or until SCNT is zero.
b. If the value of the LSN (Logical Sector Number) is equal
to that of ESN (Ending Sector Number) after updating LSN,
the HOC updates the contents of LHN (increasing by 1) and
that of LSN (LSN = 0), and repeats the operation described
in item a after selecting the next head.
c. After comparing the data transferred from the host
CPU with the data in the specified sectors, the result bytes
(FLAG, which is only for hard-sector disks, LCNH, LCNL,
LHN, and LSN) will be set equal to the sector location that
satisfies the Scan command.
d. The descriptions in d, e, f, h, and i of Read Oata command, and items c and d of Verify Oata command are
identical for this command. Refer to these descriptions
for additional details.
Write Data
PHN
(FLAG)
LCNH
LCNL
LHN
LSN
SCNT
EST
PHN
(FLAG)
LCNH
LCNL
LHN
LSN
=
=
=
=
Physical Head Number
Flag Byte. Hard-oector 10 FIeld Dnly
logical Cylinder Number, High Byte
Logical Cylinder Number, Low Byte
LHN
=
Logica' Head Number
LSN
= logical Sector Number
PHN
FLAG
LCNH
LCNL
SCNT
SeNT = Sector Number
EST = Error Status
Verify Data
PHN
FLAG
LCNH
LeNL
LHN
LSN
checks the CRC bytes (CRC mode) orthe ECC bytes
(ECC mode).
If the HOC detects a CRC or an ECC error on a sector, the
HOC terminates execution of the command abnormally
after setting the OER bit of the EST register to a one.
d. After detecting an active TC signal (TC = 1), the HOC
executes the above operation by comparing the read data
from the disk drive with the data 00 instead of the data from
the main system.
e. After verification of the data on all the sectors, FLAG
(hard sector only), LCNH, LCNL, LHN, and LSN are set
to the values of FLAG, LCNH, LCNL, LHN, and LSN of the
last verified sector.
f. The descriptions in items d, e, f, h, i, and I of the Read
Data command are valid in this command. Please refer to
these items for additional detail.
PHN
(FLAG)
LCNH
LCNL
LHN
LSN
SCNT
EST
PHN
(FLAG)
LCNH
LCNL
LHN
LSN
SCNT
= Physical Head Number
= Flag Byte, Hard-sector 10 Field Only
logical Cylinder Number. High Byte
=
= logical Cylmder Number, Low Byte
= logical Head Number
SeNT
= logical Sector Number
= Sector Number
EST
= Error Status
This command is used to verify data on the disk.
a. The HOC reads the data from the specified sector, and
compares the data transmitted from the local memory via
OMA with the data from the disk.
The sector is specified by FLAG (hard sector only), LCNH,
LCNL, LHN, and LSN, and the drive is selected by UA. If
the data transmitted from the local memory is the same as
that read from the sector, the HOC updates the contents of
LSN and SCNT, and continues the above-mentioned operation. After updating SCNT, if the value of SCNT is equal to
zero, the HOC ends the execution of the command in the
normal mode. If the value of LSN is equal to that of ESN
after updating LSN, the HOC updates the contents of LHN
and LSN, and the HOC continues Verify Oata operation
after selecting the head (track) specified by LHN.
If the data transmitted from the local memory is not the
same as that read from the sector, the HOC ends the
execution of the command in the abnormal mode after
setting the NCI (Not Coincident) bit of STR to one.
b. If, alter verifying the data on the last sector, the contents
of SCNT are not equal to zero, the HOC terminates execution of the command abnormally after setting the ENC (End
of Cylinder) bit of the EST register to one.
c. After verifying the data read from a sector, the HOC
a. This command is used to write data into the data field
of the sectors specified by FLAG (hard disks only), LCNH,
LCNL, LHN, and LSN, and to write CRC bytes or ECC
bytes according to each internally specified mode (CRC or
ECC). The data is written to the disk via DMA transfer from
the local memory.
b. After writing data on a sector, the HOC updates
the contents of SCNT and LSN, and repeats the above
described Write-Data operation until SCNT is equal
to zero.
During the above Write-Data operations, if LSN is equal to
ESN, the HOC updates LHN and LSN, and continues the
Write-Data operations after selecting the new head (track)
specified by LHN.
As described above, the HOC has the capability of multisector and multitrack write operations.
c. The HOC abnormally terminates the execution of
this command, if the SCNT is not equal to zero when
the HOC writes the data to the last sector (LSN = ESN
and LHN = ETN). The ENC (End of Cylinder) bit of the
EST (Error Status) register is set to one in this situation.
d. If the Write Protected signal is active (high) at the beginning of the execution of this command, the HOC ends the
execution of this command in the abnormal mode after
setting the NWR (Not Writable) bit of the EST register to
one.
e. After detecting an active TC signal (TC = 1), the HOC
writes the data 00 to the sector, instead of the data from
the host system, until the SCNT is equal to zero, or until the
HOC detects any abnormal state.
f. In the floppy-like mode, the HOC will set the Reduced
Write Current output bit of port 1 to a one when the cylinder
number becomes greater than that specified by RWCH and
6-105
6
fJ- PD7261
RWCL. These parameters are loaded during execution of
the Specify command.
The descriptions in items d, e, f, h, i, and k of the Read Data
command are applicable here also. Refer to these items for
further detail.
Sense Interrupt Status
1-1-------------------;1
0001X
1ST
Specify
ETN
ESN
(I~~:;~Y
GPL2
0011 X
IAWCLI
Bit
Bit Name
Specified Mode
1 Inhibited
o MFM data when SSEC = 1, NRZ when SSEC = 0
ECC is appended in data field
ECC
(x· , + 1)(X" + x, + 1)
o CRC is appended in data field
1 Generator polynomial: (x'. + 1)
CRCS
o Generator polynomial: (x'. + x" + X S + 1)
Soft-sector disk (floppy-like interface)
SSEC
o Hard-sector disk (SMO interface)
SSEC = 0
SSEC = 1
OSL
Data Strobe Late
STP3
Stepping rate for
ST506 Mode:
OSE
Data Strobe Early
STP2
fH = 2.11ms
SOM
Servo Offset Minus
STP1
OH =33.76ms
SOP
Servo Offset Plus
STPO
assuming a 10MHzStepping Rate = (16 - STP) x 21100 x tCY
processor clock.
07
06
05
D4
03
02
01
DO
MOU
1
CRe·
PAD
POL
DTlL
ETN
ESN
= Data Length, High Byte
I
CRe·
I
PAD
I
POL
I
DTL11
~'----.?::I-_----s::==J
The Sense Unit Status (SUS) command is used to transfer
the Unit Status (UST) to the host. In the case of SMD mode
the SUS command may also be used to transfer the Detail
Status (OS) and Device Type (DT) by using the appropriate
preset parameter value as shown above. No preset parameters are used in the soft-sector mode, although one is
required in the SMD mode. Values other than 1, 2, or 5 do
not produce valid results.
The OS and DT bytes are defined by the type of drives
used. The UST is shown below:
No_
I
UST
Unit Status Byte
MODE = Mode Byte; Selects Operation Mode
DTLH
~I- - - - - - - I
SMDMode
0011X
b. If the Seek or Recalibrate command in progress is completed when this command is issued or if there has been
no change of state of the Ready signal from the drive, this
command will be terminated abnormally.
DTLL
I
~.______~_U_ST_______~~\---D-S---~(~
a. The HOC transfers the new disk status to the host CPU
at the end of a Seek or Recalibrate operation or the new
disk status resulting from a change of state of the Ready
signal, which may occur at any time.
OTLH
Sense Unit Status
Soft-Sector Mode
1
1ST = Interrupt Status
MODe
RCNH, and RCNL may be programmed into the HOC. This
allows for a high degree of versatility.
I
DTL10
I
DTl9
I
DTl6
= Imtlal Value of Polynomial Counter, Either All Zeros or All Ones
= Selects IO/Oata pad of OOH If 0
= Selects IO/Data pad of 4EH If 1.
= Polling Mode If 0
= Nonpolhng Mode If 1.
= Data Length, Low Byte
= Ending Track Number
= Endmg Sector Number
GPl2 = Gap length 2
MGPL 1 = Gap Length 1 (used m SMD mode only), Controls Read Gate Tlmmg
RWCH = Reduced Wnte Current (Cylinder No ), High Byte
RWCL = Reduced Wnte Current (Cylmder No.), Low Byte
The Specify command is used to set the operational mode
of the HOC by presetting various parameters. Parameters
such as MODE, DTLH, DTLL, ETN, ESN, GPL2, GPL11
Interface Type
SMD
Floppy·like
Unit Selected
0
Seek End
0
Write Protected
0
(AM Found)
Drive Selected
Unit Ready
Seek Complete
On Cylinder
Track 000
Seek Error
Ready
Fault
Write Fault
Detect Error
0100X
EACH
EADL
EPT1
EPT2
EPT3
t-------------------I
EACH
EACl
EPT1
EPT2
EPT3
= Error Address, High Byte
= Error Address, Low Byte
= Error Pattern, Byte 1
= Error Pattern, Byte 2
= Error Pattern, Byte 3
This command is used to transfer the error pattern and the
error address to the host CPU, when correctable errors
have occurred during the execution of a Read Data command with the ECC mode enabled.
The error address (EADH and EADL) IS calculated from
the last data byte of the sector that contained a correctable
error which was indicated by the status bits of the previous
Read Data command with the ECC mode enabled. The
error pattern is used for correcting the error data at the
location where the error occurred. After receiving the error
address and the error pattern, the host CPU can correct the
error data by performing an exclusive-OR of the error pattern and the error data.
The result bytes are available to the host CPU within 100 JLs.
6 -106
f.LPD7261
The sector Included
correctable error
Sense Inte"upt Status Request When Controller Nof Busy
INT
Req
I~'----------------DTL-----------------
SENSEINT
STATUS
I
Command
Issue
I
1---------- EAOH, EADL - - - - - - - - - - n-1
STR
Road
I
INT
Req.
I I
fl
,-H---,
"-2
CB
CEH+_C_E_L_ _ _ _ _ _ _~Ir--Jr
The error pattern
EPT,
EPT3
SRO
I
Note: EOn equals error byte
I It---------i
There are no preset parameters or result bytes associated
with this command. The definitions of the 4 LSBs (AAAA)
are given below. The auxiliary command is accepted at any
time and is immediately executed. The auxiliary command
may be used to recover from certain types of error conditions, or to mask and clear interrupts.
Bit Name
Operation
CLCE
Clears the CE bits of the status register,
inactivating the Interrupt request output caused
by Command End condition. This Is used when
no disk commands are going to be issued and It
is desired to clear the Interrupt.
Deactivates the interrupt request output caused
by Sense Interrupt Status Request condition
until a Command End occurs. However, this
command has no effect on the SRQ bit of the
status register.
Clears the data buffer.
This has the same effect as a reset signal on the
Reset input. This function is used whenever the
RRQ bit In the status register Is set (indicating
the format controller is hung up), or when a
software reset is needed.
CB
SRO
~~
INT
Req
I~
System Example
Local Memory
AB
~-----4--4-+-+-+-r---------------IRD
Disk command issue
INT - - - - - ]
CLCE
SENSE INT
Command STATUS
Issue
Command
Local Bus System
ReadlWrite Sequence
::H+~I
-,~
Reads
SRO Mask (SROMl Is Sol
Timing Waveforms
Parameter Another
Writes
Disk
~"'"~.:. r~:. :~.:. I_1 ~J_1.:..11:..:1.:.1,-11_f_ST,-~_:_a_nd_
f !f----:..I-..."I-..."I
Result
Status
L.,s-----I""""
SRO --..J;----:-I-...j
__,J-_-..."'7I-------,L.,J--
Halt Sense Interrupt Status Request
Result
STR
Resd
--~==~If--'
Roq.
STR
INT
Req.
Issue
INT ~
Bus
Req. Read Status
HSRO
Command
Issue
CEH+CEL
WAiT
sue
________
I
I
I fl I I $
-~~-~__!~~~-~~-~-~I_1f~
Is--,
~======;~r~
1r
Local
INT
STR
Read
I· I
OOOOAAAA
'TThr li
I
Sense Interrupt Status Request When Controller Busy
Auxiliary command
Parameter Disk
Writes
Command
Read.
~ll----------
INT
Req
CLB
RST
Result
Status
INT~~
I EPT1
The corrected
data bytes L.____. l -__.--.l._ _- '
HSRQ
STR
Read
....,1
!
it:.=..=.=.=.L-
L{t
f~r-----"T"~-!-ff.- _____ L - -
-----_11.1-'_____(_CLC_E_c_o_m....,mifl-d_I._._ue_l_ _ _ __
6-107
I-LPD7261
Track Format
Hard Sector
Indexl
Sector
Soft Sector
Index
HEAD
SCATTER
These GPL2 bytes of zeros are requi red by
the drive to allow the drive's read data PLOto
become phase- and frequency-sync hronized
with the data bit s recorded on the media.
PLO SYNC
I-OOH (GPL2)
AM
19H(1)
FLAG
(1)
LCN
(2)
LHN
(1)
LSN
(1)
CRC
(2)
10 PAD
OOH (2)
1-
OOHiGPL2)
AM
19H (1)
4EH (GPl1)
-
PLO$YNC
c-
-
"-
10 field
- These bytes are written by the contro
_
-
lIerand
are required by t he drive to ensure p roper
recording and recovery of the last bits of the
data field check codes.
----U"'. ,,..",...
-
PLOSYNC
GAP1
-
r-
OOH (GPl1)
-
-
DATA
A1H
(1)
LCNH
(1)
LCNl
(1)
LHN
(1)
LSN
(1)
CRC
(2)
IDPAD
OOH (3)
}-
es to the controller t
beginning of the I o field or the data fi eldand
it establishes byte synchronization.
"'
OOH (GPL2)
AM
PLO SYNC
OOH (GPL2)
AMA1H
(1)
AM FBH
(1)
DATA
(OIL)
ECC/CRC
(4/2)
DATA PAD
(OIL)
...-These bytes are written by the controller an-d
OOH (2) I -
ENDOF
Indexl RECORD
OOH
S ector
'--
ECC/CRC
(4/2)
are required by the drive to ensure proper
recording and recovery of the last bits of th e I - - I o field check codes.
-
DATA PAD
OOH (3)
INTER
RECORD GAP
4EH (GPL3)
GAP4
I",dex
4EH
System Example Timing Diagrams
Figures 1 through 12 show the interface timing (soft sector and hard sector) required to interface the hard-disk drive.
Figure 1. "Unit Se/ecflon" and
Tag 1
"1"
"State Sense" Timing (Hard Sector)
Tag 2
"1"
Tag 3
"1"
Direction
"1"
Sr Sel Tag
,
"1"
I
US Tag
~------~,~
"1"
I
BT2-BT9
:
\,
~,'--~=-------------
,;.;.:="'-----~d,.,d,..r--i~c..l-npc..u-t-------------Floating
RD Gate
I
"1"
I
WRGate
I
"1"
I
I
j
Index
Sector
Umt Selected
I,
,
1\
______'~yr-~I-g&------------II
\
I
\
I
Seek End
"1"
Bit 0-9
Undefined
I
I
\
I Unit Addr (BT2-BT4), Undefined (Others)
Status
Sense Lines DeVice Status 1
(Umt Ready)
\
\
Umt Select
20_22
~~r-r----'~~u7n~d~~""n-ed~--------------Undefined
UmtAddr
Reset
;--\-----------------------------f---.I
~
State after Reset
Unit
Selection
6-108
"Umt Selected" and "Unit Ready" Signals
are checked through BT9 and BT5 pins
j.1PD7261
Figure 2. Return to Zero Timing
----------------------~Ilr---------------------
(Hard Sector)
----------------------~1Ir-------------------I~r-------llll---------------------Direction
I
~J\~--I
---------+------------lt~I-------------------
~
r~L__
I
I !
I
1-
~
BT2-BT9
I UOit Addr
\
I
FiD'Gai8
I
I
I
Others=O
_____'r
P16=SeakEnd(lnput)
I~L_...!_u::;n",lt:..:Ad=d;..'_ _ _ _ _ _ __
0;I
I
I
i
I
~r_----~--------_+--~ll~--~:-----------------\
\
Index
\
I
I
I
I
\
I
\
\
\
\
I
\
~
'-
\Vr ---+------":..,""" .
Sector
Unit Selected - - f
- ; l-----'
'}.
Seek End
8110-9
I
I
1t=J
bL------~--~~,~~--------------------
::.Un::;d::e.:.:"n::;e:.:d'___--'XI..-=B:.:lt.::6_=.:...__~i'\"'::d'--------------
Status Sense -----::D"'ev-,c-e"Sta=t,..u.".:------ll\~------------Lin..
n~------------UmtSelect
20-22
-G::X
Undefined
~~ Undefined
Add-'----------1.
AdcI":"'--------Umt
Umt
H
t
H
"Return to Zero"
Umt
Selection
P18 (Seek End) signal IS checked at this
point.
IS ISSUed.
Figure 3. ·Seek" nmlng
(Hard Sector)
~~--~Irl---------------
I
n
I
"."
I
I
I
"."
I
I
~/\---------US Tag
f
"."
,
Irl---------------------
f
~/
I
I
I
r~
/
I
~BT8=seek End (Inpu~)
1IT2-BT9
Unit Addr
Cylinder Addr 2-9 r
\
\
\
I
I
Sector
UnH Selected
"-----.ICylinder Addr 0
\
\
\
Index
\Ih-i----------7-,- -
\ ;
I
\
\
\\
\
--..-J
Seal< End
Unit Addr
I
C----.J C~hnde' ~~r,-'.----------+--
\
I
\
I
I
I
\
\
\
\
I
\
\
\
\
\
\
~ ~,..------------~\\..
\
\
....\
~~--r----------
n---'
BIt!HI
Undefined
~:I---.:.Undef1=,;,;ned='--------StatusSen.. _ _ _ _ _--,="'Cy"""'I-"""'-'Ad""'d;..'_ _-inl-_ _ _ _ _ _ _ _ _ _ _ __
Lin..
Device
II-I_ _ _ _ _ _ _ _ _ _ _ __
-<
Statu..
Unit Select
20-22
~~u::;n~~~ned~-------------l:~~u::;n~de~ft.:.:M::d~---------Unit Addr
Unit Addr
H
1
Unit Selection
BTl (Seek End) &lgnal15 checked at thiS
POint.
6-109
fLPD7261
Figure 4. "Head Select" Timing
(Hard Sector)
"1"
"1"
"1"
Direction
\--------
BTO-BT9
~~----------------------------~
Input
X Head Addr 2 XInput
Umt Add~,----'-----J
'1.....:....-------I
RD Gate
\
Head Addr 1
\ Head Add, 0
7
I
\
Index
\
\
Sector
Uno' Selec'ed _ _ _ _'~yr---------------------
Seek End
Bit 0-9
--'u:.;.n:.;.de"'"...
''n:.;.ed"-_ _ _ _ _ _ _~x Head Add, o-2X'l....:U"'n=de:.:':::ln=ed=-_ _ _ __
~~~~: Lines
_ _ _ _ _--=o.:.ev:.;.ic:.;.e...S:.;.'a:.;.'...
U S:.;.I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Umt Select
20_22
H
I· "Head Select" 1
Umt Selection
IS issued.
Figure 5. "Device Status Sense"
~"1-,,---------------------~11
Timing (Hard Sector)
~"I~,,-----------------~1l
~"1~,,-------------------~1l
Direction
\'I....._~I\'I....._~rl
_"O.:.'..:'m.:."~n•.:.'.:.h=m.:.H=O..:C..:i•.:.s:.;.e..:I~.:.'..:m~g..:O_~.:..:.Un.:.I.:.t._ _-----------~ll
BT2-BT9
Fi5"Gate
~:
Device Type l l
Device Status 1
"1"
------------------~\l
Index
Index pulse
I
SAO
\1
I
SRI
\
Sector pulse
Sector
I I
I
I
1
I
I
0T1
\
OT2
\
Unit Selected :::"I:::"""'m-.-an:-:."""h'"'a7,a--::-Un"'",':-:i-.s:-e7Ie:-:cted=.-----------------l1l
Seek End
:::"I~,,------------------~H
..:a.:."_I~_ _ _ __JX~_~B-it-9---"x::x~--B.:.'.:.'9.:.--1--_{~:
Stat~~:nse "O.=v"-ic::.'S"-,m:;;u"."I,,(nos"'I")-----...,X
t
~ Device Type ~~
BitQ-9
___
Device Status 2
Unit Select
On Cylinder
OS
Undefmed
20-.22
"""1","-------------------------
t
The DeVice Status 1
IS read through
BTO-BT9 pms.
6-110
t
The DeVice Status 2 IS
read through BTO-BT9,
Index, Sector pinS
t
The DeVice Type IS read
through BTD-BT9,
Index, Sector pins.
I-LPD7261
Figure 6. "Data Read" Timing (Hard Sector)
Tag 1 }
Thg2
Sr Sel Tag
------------------------------------------------------~
"1"
TagS} ___
Dlreclion
"o_"__________________________________________________~
US Tag
Umt selected} -------------------------------------------------------l
Seek End
Sync
"1"
_ _ _ _ _--'1
AD/Ref elk
(Read Clk)
"I"
\~-----~~~-----~
Index/Sector
~~---------------------------------~
Format
(GPL1)
(GPL2)
(1) (1) (2) (1) (1) (2) (2)
Figure 7. "Data Write" Timing (Hard Sector)
;::~}--------------------------------------------------~\'r----------------------"I"
Sr Sel Tag
Tag 3 }
Direction
"0"
·~~----------------~l~~----------
US Tag
Unot Selected }
Seek End
Sync
RD/Ref elk
----------------------------------------~l~l------------------"I"
"0"
\~------------------~ll~------------------
1
lJlJ1JlJ ----
(Servo Clock)
Write Gate
\
\'-------------~/
Index/Sector
/
11
n
~_______________________________________________'I
~
\l
ECC/CRC
Format
Data
(DTL)
6-111
~
1/1 ~d I
(412) (2)
fLPD7261
Figure 8. "Drive Select· and "Unit Status Sense" Timing (Soft Sector)
Drive Select
~
DS1,_DS~=0, 0 ~~-,1""1_ _ _ _-t:l-~___--'X'-'l,"'O_ _ _ _ _ _ __
______________'Ir--------------------------~ll~--------------------------~r----------~H~--~\~------------
ft.ODrl=-ve-';::SeO::'ec"t3
-----~!----'\\--I
,
,
Drive Select 4
Seek Complete
~~----~11~----~1:
I
\
Drive Selected ------------,.
1)
,
\.
\
\
,
yr'---------------
-------~x:::::=x:=::Y_____-'l!~l_--------'X'--------'---::
X'_____--I-_ ___
_ _ _ _x:::::=x:=::Y
::
X'---_----i'---_
Track 000 _________~x:::::=x:=::Y
Ready
Write Fault
______~~
~~
X~___~____
-----D-rlV-e-l-is----~~~~-r-,ve--2-,s~~~~rD-riv-e-3-isi~*~t----D-"-ve-4-,-s--ill~------i~*~t-D-r-,v-e-2-1S--__L1 _______
selected.
selected
selected.
selected.
selected.
Umt Status IS read through
pinS 29-33 at thiS pOint.
Figure 9. "Normal Seek" Timing (Soft Sector)
Drive Select
Drive Select X
==x
Stable
Drive Selected ~
Direction In
c:=x
nh
:==\
==x:
Stable
C!W
q;=x
I·
S:.;t=ab"-'e=-_d~----'S-"ta"'b,,'e---~
___
l\~---,\Jr----~ll~----~\Jr--------
V
Step
·1
Direction In signal and a step pulse are
ISSUed after Ready signal is checked.
I·
1
The rate at which step pulses are ISSUed IS
controlled by STPn (Step Rate)
Command.
6-112
In
Specify
IJ.PD7261
FIgure 10. "Buffered Seek" nm/ng (Soft Sector)
D"veSelected~
~~
DIrectIon In _ _ _ _.JX~
Step
~
_______________~,ql}_i___________
------411M - - - - - - -
~r\------------
:---:1 I- IsTce
-------~
~~~
~.- - - - - - - - - - - - - - -....'ly~
Seek Complete
~0
c=
wrote Fault ~\.------------------J.r!_tlh~---''-------Lr==--ReadY~
I-
·1
Direction In signal and continuous step
pulses are ISSUed.
I·
·1
Seek Complete, Ready and Write Fault
signals are polled periodically untt! the
seek operation IS completed.
FIgure 11. "Data Read" TImIng (Soft Sector)
Format
Data
(DTL)
(42)
Read Gate --.l1-1--------,'-.Ir---------..;II~I-----....,'__
SYnc _ _ _ _ l~
Ready
'---!r----------~l\r------,'__
,=x::=j~:======================================-:!i:l:~============--
Drove Select ~l-ll----------;Sta=bI~e:-------------Ill
~~·------------~~--------------~tr\----------
Read Gate hne IS activated after Ready
signal IS checked.
Sync hne IS set when bit synchronization
.8 established
6-113
j-LPD7261
Figure 12. "Data Write" Timing (Soft Sector)
Format
Data
(DTL)
ReadGate~l
Sync
\~----------------~n
---------ll~
\~----------------~r-----------II
Il
L
Wrote Gate ---------11!}1----------------------I/
Ready
=r:::=!
II
:l-----------------------------------------------1II
~PRECOMP _________~H:~
____________________-,XL~~~h~d
4li
)[
__________________
~~l---------------------.:.St=ab.:.l.:.e-----------------------lII
II
Drive Select
-I
Read Gate hne Is
activated after Ready
and Write Fault signals
are checked
Write Gate line IS activated dUring the
period between 3 bytes after 10 field's CRe
bytes and 3 bytes after data field's ECC!
CRe bytes.
Package Outlines
For information, see Package Outline Section 7.
Ceramic, f'P07261 0
726105-REV 1·7·83·CAT·L
6-114
NEe
f.LPD7720
DIGITAL SIGNAL PROCESSOR
Pin Identification
Description
Pin
The NEC [LPD7720 Signal Processing Interface (SPI) is an
advanced architecture microcomputer optimized for signal
processing algorithms, Its speed and flexibility allow the
SPI to efficiently implement signal processing functions in
a wide range of environments and applications,
The NEC SPI is the state of the art in signal processing
today, and for the futu re.
No.
o
o
o
o
[L/A Law to Linear Conversion
FFT: 32-point Complex
64-point Complex
ORO
0
DMA Request. Signals that the v.PD7720 IS requestmg a data transfer on the Data Bus.
4,5
PO,P1
0
General purpose output control lines.
6-13
Do~07
1/0
Three-state
2.25 [Ls
5.25 [Ls
0.50 [Ls
0,7ms
1,6 ms
o Fast Instruction Execution - 250 ns
o 16-Bit Data Word
o Multi-Operation Instructions for Optimizing Program
Execution
o Large Memory Capacities
o
o
o
o
Program ROM
512 x 23 Bits
Data ROM
510 x 13 Bits
Data RAM
12B X 16 Bits
Fast (250 ns) 16 x 16 31-Bit Multiplier
Dual Accumulators
Four Level Subroutine Stack for Program Efficiency
Multiple I/O Capabilities
Serial
Parallel
DMA
Compatible with Most Microprocessors, Including:
[LPDBOBO
[LPDBOB5
[LPDBOB6
[LPD7BO (ZBO)'"*
Power Supply + 5V
Technology NMOS
Package - 2B Pin Dip
Port for data transfer between the Oata Register or
Status Register and external Data Bus.
14
GNO
Ground.
15
ClK
Smgle phase Master Clock input.
16
RST
Reset. Imtlalizes the IJ-PD7720 Internal logic and sets
the PC to O.
17
INT
,.
Interrupt. A low to high transition on thiS pin
executes a call mstruction to location 100H,1f Interrupts were previously enabled.
SCK
Serial Data Input/Output Clock. A serial data bit IS
transferred when this pin IS high.
19
SiEN
20
SOEN
21
51
22
SO
Serial Input Enable. Enables the shift clock to the
Serial Input Register.
Senal Output Enable. Enables the shift clock to the
Senal Output Register.
Serial Data Input. Inputs 8- or 16-blt senal data words
from an external device such as an AID converter.
0
Three·state
Features
o
o
o
o
DMA Request ACknOWledge. Indicates to the
f.LPD7720 that the DJ!1a Sus Is ready for a DMA
Dual-Tone Multi-Frequency (DTMF)
Transmitters/Receivers
High Speed Data Modems
Equalizers
Adaptive Control
Sonar/Radar Image Processing
Numerical Processing
o
Performance Benchmarks
o Second Order Digital Filter (Biquad)
o Sine/Cos of Angles
No Connection for masked ROM I-lPD7720 Consult
f1PD77P20 specifications for connection for pmcompatible EPROM verSion
transfer. (DACK = CS. Ao = 0)
o Speech Synthesis and Analysis
o Digital Filtering
o Fast Fourier Transforms (FFT)
o
o
Function
1/0
OACK
Applications
o
Symbol
NC
0
Serial Data Output. Outputs 8- or 16-bit data words to
an external device such as a 01 A converter.
Senal Data Output Request. Specifies to an external
device that the Serial Data Register has been loaded
and IS ready for output. SORQ IS reset when the
entire 8- or Hi-bit word has been transferred.
23
SORO
24
WR
Write Control Signal. Writes an Input from the data
port Into the Data Register.
2S
RO
Read Control Signal. Reads an output to the data port
from the Data or Status Register.
26
CS
Chip..§!lect. Enables data transfer through data port
With RD or WR.
27
Ao
Selects Data Register for Read/Write (lOW) or Status
Register for read (high).
28
Vee
+5V Power
Pin Configuration
*NC
DACK
ORa
CS
PO
P1
WR
Vec
Au
RD
SORa
SO
SI
SOEN
SiEN
Do
0,
O2
03
D.
Os
D.
*Z80 IS a registered trademark of Zllog Corporation
SCK
07
GND
Rev/3
6-115
~
_ _ _ _---'.r-
INT
RST
ClK
*No connection, j.lPD7720
Must be connected for EPROM version. consult j.lPD77P20 specificatIOns
f-LPD7720
Functional Description
Memory
Fabricated in high speed NMOS, the fl-PD7720 SPI is a
complete 16-bit microcomputer on a single chip. ROM
space is provided for program and coefficient storage,
while the on-chip RAM may be used for temporary data,
coefficients, and results. Computational power is provided
by a 16-bit Arithmetic/Logic Unit (ALU) and a separate 16 x
16-bit fully parallel multiplier. This combination allows the
implementation ofa "sum of products" operation in a single
250 ns instruction cycle. In addition, each arithmetic
instruction provides for a number of data movement operations to further increase throughput. Two serial I/O ports
are provided for interfacing to codecs and other seriallyoriented devices while a parallel port provides both data
and status information to conventional microprocessors.
Handshaking signals, including DMA controls, allow the
SPI to act as a sophisticated programmable peripheral
as well as a stand-alone microcomputer.
Memory is divided into three types: Program ROM, Data
ROM, and Data RAM. The 512 x 23-bit words of Program
ROM are addressed by a 9-bit Program Counter which can
be modified by an external reset, interrupt, call, jump, or
return instruction.
The Data ROM is organized in 510 x 13-bit words which
are addressed through a 9-bit ROM pOinter (RP register).
The RP may be modified simultaneously with arithmetic
instructions so that the next value is available for the next
instruction. The Data ROM is ideal for storing the necessary coefficients, conversion tables, and other constants
for your processing needs.
The Data RAM is 128 x 16-bit words and is addressed
through a 7-bit data pointer (DP register). The DP has
extensive addressing features that operate simultaneously
with arithmetic instructions so that no added time is taken
for addressing or address modification.
Block Diagram
I
OMA
I
Interface
ORO
I
N
I
RAM
Logic
Instruction
ROM
512 x 23
128)( 16
-
I
f---
-
Multiplier
I
I
Serial
I/O
Mr--
PC
J
l
I
1
Stack
2
---3
cb
r-L....,
L~~.J
S
S
C
Flag A
A
A
A
1
0
Flag B
B
1
CLK_
D
INT-_
vcc GND_
Interrupt
I
l,1-
LJ
0
RST _ _
OP
S
S
B
0
Z
A
0
V
A
C
B
Z
B
0
V
A
1
0
0
0
V
B
1
V
B
0
I'---K...J..l-'1
L-Jl
I
JJ
l
i
MPX
Shift
j
I
lL
r-o=
Por,:P,
~
Acc A
J
AceS
I
lL
<.- SR
Para/lelliO
6-116
Output
Read/Write
Control LogiC
ALU
l
I
General
P,
fJ-PD7720
Arithmetic Capabilities
General
One of the unique features of the SPI's architecture is its
arithmetic facilities. With a separate multiplier, ALU, and
multiple internal data paths, the SPI is capable of carrying
out a multiply, an add, or other arithmetic operation, and
a data move between internal registers in a single instruction cycle.
instruction cycle. A new product is available for use after
every Instruction cycle, providing significant advantages In
maximizing processing speed for real time signal
processing.
Stack
The SPI contains a 4-level program stack for efficient program usage and interrupt handling.
Interrupt
A single level interrupt is supported by the SPI. Upon sensing a high level on the INT terminal, a subroutine call to
location 100H is executed. The EI bit of the status register is
automatically reset to 0, thus disabling the interrupt facilities until reenabled under program control.
ALU
The ALU is a 16-bit 2's complement unit capable of executing 16 distinct operations on virtually any of the SPI's
internal registers, thus giving the SPI both speed and versatility for efficient data management.
Accumulators (ACCAI ACCB)
Associated with the ALU are a pair of 16-bit accumulators,
each with its own set of flags, which are updated at the end
of each arithmetic instruction (except NOP). In addition to
Zero Result, Sign Carry, and Overflow Flags, the SPI incorporates auxiliary Overflow and Sign Flags (SA1, SB1,
OVA1, OVB1). These flags enable the detection of an overflow condition and maintain the correct sign after as many
as three successive additions or subtractions.
InputlOutput
General
The NEC SPI has three communication ports; two serial
and one 8-bit parallel, each with its own control lines for
interface handshaking. The parallel port also includes DMA
control lines (DRO and DACK) for high speed data transfer
and reduced processor overhead. A general purpose 2-line
output port rounds out a full complement of interface
capability.
ACC AlB Flag Registers
Flag A
SA1
SAO
CA
ZA
OVA1
OVAO
_.,. {
WR
Data Bus
Cs
Do
to External
FlagB
581
580
CB
za
OVa1
OV80
A,
OMA
Interface
Sign Register (SGN)
When OVA1 is set, the SA1 bit will hold the corrected sign
of the overflow. The SGN Register will use SA1 to
automatically generate saturation constants 7FFFH( + ) or
8000H( - ) to permit effiCient limiting of a calculated value.
Multiplier
Thirty-one bit results are developed by a 16 x 16-bit 2's
complement multiplier in 250 ns. The result is automatically
latched to two 16-bit registers M&N (sign and 15 higher bits
in M, 15 lower bits in N; LSB in N is zero) at the end of each
Serial 110 Timing
0,
AD
Intertace
{
SO
SORD
se"aIl O
}
f,LPD7720
Interface
DACK
ORO
Interrupt
INT
Reset
Clock
RST
CLK
Po
P,
}
General
Purpose
Output Port
Serial 110
The two shift registers (SI, SO) are software-configurable to
single or double byte transfers. The shift registers are externally clocked (SCK) to provide a simple interface between
the SPI and serial peripherals such as AID and DI A converters, codecs, or other SPls.
sct(
SORO
_ _--I
SOEN
Output
\~--------------~Il~----------------~I
~·r::X~~~~I)~~~~-~H~19~hZ~_
180r5
140r6
150r7~~
Data
HlghZ
~'-
SOACK
~
J
r------(NextD8i"asei)--------:
SO Load ~L-_____________________________IL..r_-_-_-_'L..1_________
Input Data __--J\~_ _..A...-"-~'--'-...A.--"__J\.....jI_...A....::18""0!..:'5,-"...:;14",0",'6,-"...;1",,50:::.,..:..7J'-__- " ' - - _
\ ' - - - - - - - - - - -_____~I
(
Notes: Data clocked In on riSing edge of SCK
@ Broken hne denotes consecutive sendlnq of next data
SILoad
SlACK
____________________________________
~rlL
_____
--------------------------------~~
6-117
j.LPD7720
Parallel 1/0
Instructions
The 8-bit parallel 1/0 port may be used for transferring
data or reading the SPI's status. Data transfer is handled through a 16-bit Data Register (DR) that is softwareconfigurable for double or single byte data transfers. The
port is ideally suited for operating with 8080, 8085, and
8086 processor buses and may be used with other processors and computer systems.
The SPI has 3 types of instructions, all of which are one 23bit word and execute in 250 ns.
Arithmetic/Move-Return (OP
I
l
Parallel R/W Operation
CS
Ao
WR
RD
Operation
1
X
X
X
X
1
X
1
No effect on internal operation. 0 0 -07
are at high impedance levels
0
0
0
1
Data from 0 0 -0 7 are latched to DR Q)
0
0
0
0
0
0
1
0
X
0
Contents of DR are output to 0 0 -07 Q)
Illegal (SR is read only)
0
Eight MSBs of SR are output to 0 0 -07
0
Illegal (May not read and write
simultaneously)
Note: (j) Eight MSBs or 8 LSBs of data register (DR) are used depending on DR status bit (DRS)
The conditIOn of 5ACR = 0 IS equivalent to Ao =
CS =
0
Status Register (SR)
l~ll8
22 21
20
OP
o0
~~'ect
RT
o1
= aO/RT = 01)
j
17 16 15
I
14.1 13
12111
I~ I I
ALU
DPa.
10 9
OPH-M
J:l
Ii I
7 6 5
41
SRC
I
3 2 1 0
DST
Same as OP instruction
OP/RT Instruction Field Specification
There are two instructions of this type, both of which are
capable of executing all ALU functions listed in Table 2.
The ALU functions operate on the value specified by the
P-select field. (See Table 1.)
Besides the arithmetic functions these instructions can
also modify (1) the RAM Data Pointer DP, (2) the Data ROM
Pointer RP, and (3) move data along the on-chip data bus
from a source register to a destination register (the possible
source and destination registers are listed in Tables 7 and 8
respectively). The difference in the two instructions of this
type is that RT executes a subroutine or interrupt return at
the end of the instruction cycle while the OP does not.
LSB
MSB
Table 1. P-Select Field
o :
0 : 0 :
Mnemonic
0
D'D
0
0
0
RAM
1
Internal Data Bus Q)
lOB
The status register is a 16-bit register in which the 8 most
significant bits may be read by the system's MPU for the
latest 1/0 and processing status.
M Register
0
M
N Register
N
Note: (j) Any value on the on-chip data bus Value may be selected from any of the registers hsted
In Table 7 source register selections
Status Register Flags
Flag
ALU Input
D zo
RAM
Description
RQM (Request for
A read or write from DR to lOB sets RQM ~
Master)._ _ _ _ _ _-c1_.Ac:.n,,-,-ex=ternal read (write) resets RQM ~ O.
USFl and USFO
General purpose flags which may
(User Flags 1 and 0)
be read by an external processor for user
defined Signaling.
DRS (DR Status)
For 16-bi! DR transfers (ORC ~ 0).
DRS ~ 1 after firstS bits have been
transferred
DRS ~ 0 after all 16 bits transferred.
---OMA (OMA Enable)
OMA ~ 0 (Non-OMA transfer mode)
OMA ~ 1 (OMA transfer mode).
ORC (DR Control)
ORC ~ 0 (16-bit mode)
_. ____. _ _ _ _ _..:O::.:R-'-C=_~_''_('.::S__=-b:..cit:..:m.:.co::.:d::.:e''').______...__ _
SOC (SO Control)
SOC ~ 0 (16-bit mode)
SOC ~ 1 (S-bit mode):.._______ _
SIC (SI Control)
SIC ~ 0 (16-bit mode)
SIC ~ 1 (S-bit mode).
EI (Enable Interrupt)
EI ~ 0 (interrupts disabled)
EI ~ 1 (interrupts enabled)..____.__ _
Pl, PO
PO and Pl directly control the state of out(Ports_O and 1) ___ ---"-ll!Pins PO and.!>.':
Table 2. ALU Field
Flags SA 1 SAO CA
ZA OVA 1 OVAO
SSi SSO CS
Z8 OYBi OVBO
Mnemonic D18 D17 D 16 DiS ALU Function
NOP
0
0
0
0 No Operation
OR
0
0
0
1 OR
AND
0
0
1
o
XOR
0
0
1
1 Exclusive OR
SUB
0
1
0
o Subtract
AND
ADD
0
1
0
1 ADD
SBB
0
1
1
o Subtract with
Borrow
ADC
0
1
1
1 Add with Carry
DEC
1
0
0
o Decrement Acc
x
INC
1
0
0
1 Increment Acc
CMP
1
0
1
o Complement
Acc (1's
Complement)
SHR1
1
0
1
1 1-bltR-Shlft
SHL1
1
1
0
o 1-blt l-Shlft
SHL2
1
1
0
1 2-bit L-Shlft
x
SHL4
1
1
1
o 4-blt L-Shlft
X
x
-------,-"-
I
- - .- - · - 1 - - - - - · - -
-~-------c----·---X
XCHG
Notes:
6-118
1
1
1
1 8-blt Exchange
t May be affected, depending on the results
- PrevIous status can be held
a Aeset
X Indefinite
f.1PD7720
Table 3. ASL Field
Table 8. DST Field
Mnemonic
D. 4
Ace Selection
Mnemonic
0
Ace A
@NON
ACCA
ACCB
Table 4. DPL Field
Mnemonic
D. 3
D. 2
0
o
DPINC
0
Low DP Modify (DP3"DPol
o
DPDEC
DPCLR
D..
D. o
MO
0
0
0
0
0
0
M3
0
0
0
@DP
SR Status Register
0
0
SO Serial Out LSB 3 and ends at the
falling edge of <1>2. The ALU commences operation at the
rise of <1>1, and completes all operations at the fall of <1>3.
Once an instruction-ROM address is available at the rise
of <1>3, the instruction is latched, and the source register and
RAM address are determined so that data may be put on
the internal bus by the fall of <1>4. The ALU input is latched
at the rise of <1>1, and the output is available for accumulator latch at the rise of <1>3. The cycle then repeats.
The multiplier takes its input at the rise of <1>1, and its results
are available in 250 ns, at the rise of the next <1>1.
o
0
0
0
0
No Condition
0
0
o
CA = 0
0
0
0
0
0
0
0
0
0
0
0
o
o
o
o
0
a
0
o
CALL
JNCA
0
JCA
0
JNCB
0
JCB
0
JNZA
0
0
JZA
0000
JNZB
0
0
0
0
JZB
0000
JNOVAO
0
0
CB = 0
1
CB = 1
o o
o 1
o
ZA = 0
0
OVAO = 0
ZA=l
ZB = 0
ZB = 1
JOVAO
0
0
0
JNOVBO
0
0
0
o
o
o
JOVBO
0
0
0
01
JNOVAl
0
0
0
JOVAl
0
0
0
JNOVBl
0
0
0
JOVBl
0
0
0
JNSAO
0
0
0
0
0
0
0
CA = 1
o
0
JSAO
0
0
0
0
0
0
0
0
JSBO
0
0
0
0
JNSAl
0
0
0
JSAl
0
0
0
OVAO = 1
Absolute Maximum Ratings*
OOVBO=O
o
o
JNSBO
0
T. = 25·C
OVBO=l
Voltage (Vcc Pin)
-0.5to +7.0V0
(bO
(bF
OB0- 7
(bR
----------.,...-----4
D
t
Notes. CD For SO timing, the data at rlsmg edge of SCK IS valid and the other data IS Invalid In set·
up hold time of data for SCK, the most stnct specifications are the follOWing
setup = tSCK - tOCK
hold = I HZRQ
(1) Voltage at measuring point oft,sc and tlsc for SCK tlmmg
@30V @10V
Development Tools
ns
CY
122
elK Pulse Width
<1>0
elK Rise TIme
<1>'
10
ns
elK Fall Time
<1>'
10
ns
"'" CS. O~K Setup
IAR
TimeforRD
Ao, CS, OACK Hold
TImeforRD
RD Pulse Width
2000
60
IRO
IOF
150
10
ns
tww
250
ns
Data Setup Time
forWR
low
150
ns
250
ns
DB..,_____I::'~
lAM
CL - l00pF
Write Operation
DMA Operation
150
<1>0
toACK
Iscy
480
SCK Pulse Width
ISCK
230
SCK Rise Time
l.sc
20
ns
SCK Fall Time
IISC
20
ns
SORODelay
loRa
30
150
ns
!soc
50
forSCK
!cso
30
SO Delay
lOCK
DC
ns
ns
Voltage at measuring
point
of timing 1.0V and
Seriallnput/Output
3.0V
SOEN Setup Time
CL = 100pF
~s
SCK
tORO
ns
SORO
150
ns
SO Delay from SCK
wrth SORO
tozRO
20
300
ns
SO Delay from SCK
lozse
20
300
ns
SO Delay from SOEN
loz.
20
180
ns
SOEN to SO Floating
1HZ.
20
200
ns
SCK to SO Floatmg
Itiz,e
20
300
ns
SO Delay from SCK
withSORQ
tHZRQ
70
300
ns
SEIN, 51 Setup Time
loe
55
SEIN, 51 Hold Time
!co
30
Po, p, Delay
lop
RST Pulse Width
IRST
CY
INT Pulse Width
tiNT
"CY
ns
ns
CY
+ 150
81
ns
Port Output
ClK~
Note; Voltage at measunng point of AC tlmmg
VIL = VOL = OBV
VIH = VOH = 20V
P.,P,
Capacitance
T. = 25·C; Vee = OV
Parameter
Input Capacitance
Output Capacitance
~
Reset
Limns
ClK, SCK Capacitance
--ilt.-__ _
ns
two
IRV
SCK Cycle Time
forSCK
k::::
ns
OACK Delay Time
SOEN Hold Time
.::::t
Ro~~I··-rtRA
ns
twA
ORa Delay Time
.... Cs, DACK
3.0V
CL = 100pF
100
WR Pulse Width
Time
point
of timing 1.0V and
ns
Ao, CS, OACK Hold
TimeforWR
RD, WR Recovery
--GD--C
lFEH-OOOH
lFFH
V
6-129
f.tPD77P20
Operation Mode
The iJ.PD77P20 may be utilized in an operation mode after
the instruction ROM and data ROM have been programmed. Operation modes are invoked in slightly different
manners depending on the mask level and the specific
mask lot within the series.
Package Outlines
For Information, see Package Outline Section 7.
Ceramic, ".PD77P20D, has quartz window
K·mask
The iJ.PD77P20 K-mask requires that Vpp be supplied in a
different manner than for the E-mask for an operation mode
only. Vpp voltage should be supplied in the following fashion:
o
R
( ' - - - _ 1 ' - - - K f-----.----o+5V ± 5%
Vee
Vpp
Vee - (0.6 ± 0.2S)V
Ipp Min = O.SmA
Max = 3.SmA
=
A silicon junction diode of 0.6V forward voltage (V F) should
be used. R should be BOOO to 1.BKO to satisfy the Vpp and
Ipp requirements.
'
Parts before lot K21031 (excluding K21031) require a NOP
(No Operation) to be programmed into instruction ROM location OOOH in order to properly operate at BMHz. For parts
with lot numbers equal to or greater than K21031 location
OOOH of the instruction ROM does not require a NOR for
BMHz operation.
E·mask and P·mask
The iJ.PD77P20 E-mask and P-mask requires that Vpp be
connected directly to Vee for an operation mode as shown.
The P-mask version is packaged as a cerdip. Note that
these versions are also compatible with the K-mask Vpp
specifications.
r------_---<>+sv ±
V"
5%
Vee
No additional constraints apply to these versions. For both
versions adequate power supply decoupling should be provided.
77P20D5-REV1-7-83-CAT-D
6-130
NEe
fJ-PD7751
ADPCM VOICE SYNTHESIS LSI
Description
The j.LPD7751 is an LSI device for high quality voice synthesis
applications. Based on an ADPCM algorithm (adaptive differential PCM). the device decodes voice data stored in external
ROM and outputs a synthesized voice signal. This output may
be sent to a conventional audio speaker through an 8-bit D/A
converter. filter and power amplifier.
Eight messages can be stored per 128K-bit memory bank. at
compressed bit rates of 14 to 20K-bits/second. Efficient encoding of silences within a message allows further compression of
digitized voice signals. Voices may also be mixed with background music or other sounds.
Features
ADPCM decoding capability
Eight messages selectable per memory bank
Compatible with 2716/32 external ROM
Unlimited number of messages storable in multiple memory
banks
D Variable bit rate 14 to 20Kbps
D Sampling clock 4. 5. or 6KHz
D Compressed encoding for pauses
D Easy voice processing
High quality voice reproduction
Minimum dependence on voice characteristics of
speaker
Easy analysis and data generation
Stable voice quality
Combined voice and background music capability
D N channel MaS
D + 5V single power supply
D 40-pin plastic DIP
Pin Configuration
TEST,
V,,( + 5V)
XTAL,
TEST 3
XTAL2
BUSY
RESET
SEL 2
I.C
SEL1
SELo
START
vo,
va.
TEST2
I.C
I.C.
I.e.
I.C.
D
D
D
D
VO,
VO,
VO,
DATA,
VO,
DATA,
VO,
OATA 2
VO,
DATA3
Vc. c (+ 5V)
DATA.
PROG
DATA5
AD,
DATA,;
AD,
DATA7
AD,
GND
AD,
Pin Identification
Pin
110
Function
No.
Symbol
Name
2,3
XTAL,
Crystal
Form a clock oscillator CirCUit when externally connected to 6MHz cry~tal
RESET
Reset
Initializes the f.LPD7751 Internal logic
START
Start
Starts output of message that has been selected
by SElO'" SEL2. Active low trigger I~~~_~~_
Data
Transfers the compressed vOice data from an
external memory for decodmg.
XTAL2
.~~-~
12-19 DATAo
to
Signal
DATA7
.--.~~
21-24 ADo
to
Address
Signal
0
Specifies to 1/0 expander ports (eg, j..lPD8243) the
address of the external memory contalmng the
stored voice data.
Program
Signal
0
Strobe Signal for decoding address signals Low to
high transition indicates address information IS
VOice
Signal
0
AD,
-~--.--~-~---~~-
25
PROG
-~~~~~~~~~~~- 27-34 VOo
to
VO,
35-37 -""SELo
to
SEL2
38
Busy
26,40 Vee
20
Outputs to D/A converter the 8-blt vOice Signal that
has been decoded via ADPCM
Messag;-~-I- SpeCifies which of eight types of stored messages
Select
Busy
Signal
to be output from external memory
0
GND
Ground
IC
Internal
Connection
Chip status; goes low dUring decode and output
operatlo~~_. _______ . ____ ._ _ _ ~ __
+ 5volt power supply.
Power
Supply
~--.-
5,8-11
0
------
-----~--
Must be left open dUring normal operation.
~~~~~--~-~~---~~----~-~~~-
1,7,39 TEST1
to
TEST3
Test
Input
I
Inputs for LSI testing. Must be connected to GND
dUring normal operation.
Package Outlines
For information, see Package Outline Section 7.
PlastiC. "PD7751
7751 DS·7·83·CAT-W
6 -131
m
Notes
6-132
NEe
I-LPD7752
FORMANT VOICE SYNTHESIS
Description
The fLPD7752 is an LSI for voice synthesis which employs
formant data as accumulated parameters. With five filters
corresponding to the first through the fifth formants, vocal
characteristics are reproduced to synthesize voice at bit rates
as low as 2400bps. The fLPD7752 can be connected easily
to any bus system of the SOSOA family. Through serial
interfaces, the LSI can also be connected to various other
microcomputers. The fLPD7752 operates with attractive low
power consumption because of its CMOS structure.
Features
D Voice synthesizing system using formant parameters
D 5 formants - first through fifth
D Bit rate variable between 5600bps and 2400bps
D Internal 32K-bit ROM for voice data storage (voice
duration: approx. 13 seconds at 2400bps, max 63
messages)
D External formant parameter ROM (option)
DOn-board 9-bit D/A converter - option provided to
interface an external D/A converter
D 3 different voice synthesizing speeds (slow, normal, and
fast)
D Frame length: 10ms or 20ms
D Bus-compatible with the fLPDSOSOA, fLPDSOS5A and
fLPDS04S
D Serial interface for mode/command input
D Clock oscillator circuit
D CMOS structure
D + 5V single power supply
D 2S-pin plastic DIP
Pin Configuration
REO
BUSY
RESET
Pin Identification
Pin
No.
Symbol
REO
Name
Request
generation.
BUSY
VCK
DB,
GNDA
DB,
AVO
DB,
VSTB
DB,
DB,
AD
WR
DB,
l(,
..- ..~~
Indicates message select command
accepted and synthesIs operation IS
progress.
0
Busy
RESET Reset
In
Resets deVice.
4-11
DB ...
DB,
Data Bus
12
SCK
Serial Clock
Clock for senallnput. Should be held high
for parallel input mO.c:de::::..._ _ _ _ __
13
SI
Senallnput
Senal input for mode or command data, as
specified by Ao.
1.
GND
15,16
Ao,A1
Threestate
Bidirectional data bus for input of mode,
command, and formant parameter data to
f.lPDn52, and output of status ~nformation.
Ground
Input Data
Specification of parallel bus Input as mode,
command, or formant data (see 1/0 Control
Signals Table). For serial input: AtJ = 0 for
mode; Ao := 1 for command.
Identification
17
CS
Chip Select
Low-level signal enables read/Write
transfers on parallel data bus.
18,19
X1,X2
Crystal
Oscillator
Connection for 3.6MHz (3.579545MHz)
crystal or ceramiC oscillator, or for Input of
external clock Into Xl.
20
WR
WrIte
Low-level signal wntes bus input to the
f.lPD7752 (mode, command, or formant data
as specified by Ao, Al, see 110 Control
Signals Table).
21
RD
Read
Low-level signal reads status information
from the f.lPD7752, independent of the value
ofAoandA1.
22
VSTB
Voice Output
Strobe
0
Strobe indicates that all 16 bits of senal data
have been output from DVO (digital vOice
output).
23
AVO
Analog VOice
Output
0
SyntheSized analog VOice output from 9-blt
D/A converter. ReqUires external load
resistor
2.
GNDA
Analog Ground
Ground potential for AVO (analog vOice
output)
25
TEST
Test
Input for LSI testmg. Must be connected to
GND durmg normal operation.
26
VCK
Voice Clock
0
Output of 16 clock pulses synchrOnized to
eVOslgnal.
27
DVO
Digital Voice
Output
0
Synthesized digital voice output as the 14
MSB of a 16-bit serial data stream. Output IS
LSS first, and the first two (LSS) bits are
zero.
28
Vee
Power
v"
TEST
Requests a formant parameter from external
ROM. Returns to low level after the
parameter has been written, or If an error
occurs during the parameter transfer, or .f a
stop command IS received dUring vOice
=------c:::-=c--:=--~~----c=--~~"----~~~~=__-
DVO
DB,
Function
1/0
0
+5V power supply.
I/O Control Signals
cs
RD
WR
Ao
A,
X
X
X
X
X
Status read
0
Formant parameter write
Operation
No operation
DB,
X,
SCK
cs
Prohibited
51
A"
Command write
GND
A,
Modewnte
Note:
0 - Low
1 = High
X = Don't Care
Package Outlines
For information, see Package Outline Section 7.
Plastic, fJ.P07752
nS205-7-83-CAT-W
6-133
Notes
6-134
NEe
fJ-PD7761/fJ-PD77621MC.4760
SPEECH RECOGNITION
3·CHIPSET
Description
The fLPD7761, fLPD7762, and MC-4760 constitute a 3-chip
LSI set containing the main functions of an isolated word,
speaker-dependent recognition system. These functions
include an analog interface, processing for voice analysis,
compressed dynamic programming (DP) matching, and
system control. The 3-chip set employs a DP time warping
algorithm to compensate for variations in the rate of speech,
which greatly facilitates the matching of a given spoken
phrase to a stored vocabulary of digitized words. Three kinds
of system I/O interface are supported for ease of control by
external microcomputers. With this LSI chip set, speech
recognition systems can be developed for low cost and with
low total chip count.
Features
D Recognition of 128 isolated words
D Compressed DP matching algorithm
D Word registration capacity: 128 to 512 words
D
D
D
D
D
D
D
D
Pin Configurations
D
AB,s
,bout
Vo<
AB'4
DB,
DB,
DB,
DB.
DB,
DB,
DB,
DB,
AB,~
DORa
HST
, CG
WAIT
RE
WR
liD
NU
NU
lotH
TO
SAK
scs
NU
NU
SCK
SI
SO
RESET
X,
X,
GNO
AB'2
AB"
AB,o
(with 16K-to 64K-byte memory)
Word duration up to 2 seconds
Average 0.5 seconds response time for recognition
Recognition rate above 98 percent
Directly connectable to microphone for voice input
Supports parallel, serial, and RS-232C system I/O
interfaces
Convenient commands for recognition, training, data
transfer, and other functions
Includes analog interface (MC-4760), analysis and
calculation processor (fLPD7761), and control processor
(fLPD7762)
Requires + 5V, + 12V, - 12V power supply
A/D converter sampling at 10kHz
NC
AB,
AB.
AB,
AB,
AB,
AB.
AB,
AB,
AB,
AB,
NU
NU
PU
MM,
MM,
V"
A,
NU
CS
NU
lID
NU
WA
0,
DOAO
0,
NU
0,
DVI
0,
CG
0,
SEL,
SELo
SMPL,
II
SClK
OBF
IBF
NU
RST
ATCs
ATC4
ATC a
ATC 2
ATC,
ATCo
0,
SMPL,
0,
AST
GND
ClK
MICIN
LINE IN
DVO
lPF OUT
ClK
GADJ
SMPL
NC
GND
GND
V+
V-
ATC o
NC
ATC1
NC
ATC 2
AOUT
ATC",
ATC 6
ATC s
ATC 4
776117762/4760DS-7-83-CAT-W
6-135
---_.,-----
Notes
6-136
NEe
"PD8155
"PD8155-2
"PD8156
"PD8156-2
2048 BIT STATIC MOS RAM WITH
1/0 PORTS AND TIMER
OESCR IPTION
FEATURES
The IlPD8155 and IlPD8156 are IlPD8085A family components having 256 X 8 Static
RAM, 3 programmable I/O ports and a programmable timer. They directly interface
to the mUltiplexed IlPD8085A bus with no extern~1 logic. The IlPD81 55 has an active
low chip enable while the IlPD8156 is active high.
• 256 X 8·Bit Static RAM
•
Two Programmable 8-Bit I/O Ports
•
One Programmable 6·Bit I/O Port
•
Single Power Supplies: +5 Volt, ±10%
•
Directly interfaces to the IlPD8085A and IlPD8085A-2
• Available in 40 Pin Plastic Packages
PIN CONFIGURATION
vcc
PC3
PC4
TIMER IN
RESET
PC5
'fi"M"ER 5UT
101M
CE/EE*
AD
WR
ALE
ADO
ADl
AD2
AD3
AD4
AD5
ADS
AD7
IlPD
8155/
8156
Vss
*"PD8l55: ~
"PD8l56: CE
Rev/3
6-137
PC2
PCl
PCO
PB7
PBS
PB5
PB4
PB3
PB2
PBl
PBo
PA7
PAs
PA5
PA4
PA3
PA2
PAl
PAO
II
IlPD8155/8156
The pPD8155 and pPD8156 contain 2048 bits of Static RAM organized as 256 X 8.
The 256 word memory location may be selected anywhere within the 64K memory
space by using combinations of the upper 8 bits of address from the pPD8085A as a
chip select.
FUNCTIONAL
DESCRIPTION
The two general purpose 8-blt ports (PA and PB) may be programmed for Input or
output either in interrupt or status mode. The single 6-bit port (PC) may be used as
control for PA and PB or general purpose Input or output port. The pPD8155 and
pPD8156 are programmed for their system personalities by writing into their
Command/Status Registers (C/S) upon system Initialization.
The timer is a single 14-bit down counter which is programmable for 4 modes of operation; see Timer Section.
Vee 1+5VI
BLOCK
DIAGRAM
t
-
8
-
-
--
~
p
L
IOiNi
A
T
e
CE
1-----
A
R
A
M
~
H
ALE
-'C
0
N
T
R
RESET
0
L
r----
-
-
J
p
B
8
'--
-
--- -
P
e
~
TIMER IN
8
'--
TIMER
6
I
TIMER OUT
I
Vss IOVI
. . . . . . . O°C to +70°C ABSOLUTE MAXIMUM
Operating Temperature . . . . . . . . . .
_65°C to +150°C RATINGS*
Storage Temperature . . . . . . . . . . . . . . .
-0.5 to +7 VoltsCD
Voltage on Any Pin . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5W
Note:
CD
With Respect to Ground.
Ta = 25°C
*COMMENT. Stress above those listed under "Absolute MaXimum Ratings" may cause permanent
damage to the deVice. This is a stress ratIng only and functional operation of the device at these or
any other conditions above those indIcated In the operational sectIons of this speclflcatJOn IS not
Implied. Exposure to absolute maximum rating conditions for extended periods may affect deVIce
reliability.
6-138
,..PD8155/8156
PIN IDENTIFICATION
DC CHARACTERISTICS
PIN
NO.
SYMBOL
FUNCTION
1,2,5
39, 3S, 37
PC3,PC4,PC5
PC2, PC1, PCO
Port C
Used as control for PA and
PS or as a 6·bit general
purpose port
3
TIMER IN
Timer Clock In
Clock input to the 14·bit
binary down counter
4
RESET
Reset In
From J.lPD9JS5A system reset
to set PA, PB, PC to the input
mode
6
TIMER OUT
TImer Counter Output
The output of the timer
function
7
10/M
I/O or Memory
Indicator
Selects whether operation to
and from the chip is directed
to the internal RAM or to
I/O ports
S
CE/CE
Chip Enable
Chip Enable Input. Active
low for J.lPDS155 and
active high for J.lPDS156
NAME
9
RD
Read Strobe
Causes Data Read
10
WR
Write Strobe
Causes Data Write
11
ALE
Address Low Enable
Latches low order address
in when valid
12·19
ADO - AD7
Low Address/Data
3·State address/data bus
to interface directly to
J.lPDSOS5A
20
VSS
Ground
Ground Reference
21·2S
PAO - PA7
Port A
General Purpose I/O Port
29·36
PBO - PB7
Port B
General Purpose I/O Port
40
VCC
5 Volt Input
Power Supply
Ta
= o°c to +70°C; VCC = 5V ± 10%
LIMITS
PARAMETER
SYMBOL MIN
Input Low Voltage
VIL
-0.5
Input High Voltage
VIH
2.0
Output Low Voltage
VOL
Output High Voltage
VOH
TYP MAX
O.S
UNIT
V
VCC-+O· 5 V
0.45
2.4
V
IOL= 2mA
V
IOH
pA
VIN .. Vee to OV
0.45V< VOUT
<,VCC
Input Leakage
IlL
±10
Output Leakage Current
ILO
±10
pA
VCC Supply Current
ICC
180
mA
Chip
pPD8155
Enable
pPD8156
Leakage
IlL ICE)
IILICE)
+100
100
pA
pA
6-139
TEST
CONDITIONS
K
400pA
VIN" VCC to OV
"PD8155/8156
Ta
= o'e to +70'e, vee = 5V
±
10%
AC CHARACTERISTICS
LIMITS
PARAMETER
Address to Latch Set Up Time
Address Hold Time after LeltCh
Latch to READ/WRITE Control
Valid Data Out Delay from READ Control
Address Stable to Data Out Valid
Latch Enable Width
Data Bus Float After READ
READ/WRITE Control to Latch Enable
READ/WRITE Control Width
Data In to WR ITE Set Up Time
Data In Hold Time After WR ITE
Recovery Time Between Controls
WRITE to Port Output
Port Input Setup Time
Port Input Hold Time
Strobe to Buffer Full
Strobe Width
READ to Buffer EmptY
Strobe to INTR On
READ to INTR Off
Port Setup Time to Strobe
Port Hold Time After Strobe
8155/8156
8155·2/8156·2
SYMBOL
MIN
MIN
tAL
tlA
tlC
tAD
tAD
tll
tRDF
tel
tcc
tow
two
tAV
twp
tPA
tAP
tSBF
tss
R8E
Sl
tRol
50
80
100
WRITEto~
tRDE
80
300
50
10
50
400
300
t50
200
400
400
400
50
tWI
tTL
tTH
100
140
330
70
0
10
200
100
0
200
400
120
MAX
30
30
40
70
tpHS
tSBE
tWBE
MAX
170
400
100
0
20
250
150
0
300
tpss
Strobe to Buffer Empty
WRITE to Buffer Full
TIMER-IN to
OUT Low
TIMER-IN to
OUT High
Data Bus Enable from READ Control
I
300
300
300
0
100
400
400
400
400
400
10
300
300
300
300
300
10
READ CYCLE
TEST
UNIT
n,
n,
"'n,
n,
n,
n,
n,
n,
n,
n,
n,
n,
n,
n,
n,
n,
n,
n,
n,
n,
n,
n,
n,
n,
n,
n,
n,
CONDITIONS
150 pF Load
TIMING WAVEFORMS
CE
OR
101M
AO()'7
ALE
RO
WRITE CYCLE
CE
("P081551
OR
CE
u,PD81561
IO/Q
AOo-,
ALE
ViR
6-140
"PD8155/8156
TIMING WAVEFORMS
(CaNT.)
STROBED INPUT MODE
BF _ _ _ _ _ _"
'SBF
INTA
INPUTDATA-------~~~~-~~------------------------
FROM PORT _ _ _ _ _ _~~--_+~~~-----------------------
STROBED OUTPUT MODE
BF
--------',
INTR
OUTPUT DATA
TOPORT ________________~~------------------------
BASIC INPUT MODE
J~'RP
Ri5 ---=--t.-'PR
INPUT
_
~_--------~---......
DATA BUS:::::::x_______
BASIC OUTPUT MODE
OUTPUT _______________
~~--
TIMER OUTPUT
LOAD
COUNTER
FROM CLR
COUNT
RELOAD
----t
FC~6:~t~
I
-..;
I
I
COUNTDOWN fROM 3 TO 0
<20 -Test POlnts--- 2 0 X = =
045
08-08
Inputs are driven at 2.4V for logic 1 and O.45V for
logic O. These timing measurements are made at 2.0V
for logic 1 and O.BV for logic O. A transition time of
20 ns or less is assumed for input timing parameters.
Unles~ noted, output loading is 1 TTL gate plus 50 pF
capacitance.
AC Characteristics
DMA (Master) Mode
Ta = O°C to +70°C; VCC
5"10; VSS
TrP
Max
Unit
200
nl
HLOA Valid to elK High Setup Time
IHS
Input Data from MEMR High Hold
Time
IIDH
Input Data to MEMR High Setup Time
liDS
170
no
Output Data from MEMW High Hold
Time
tODH
10
no
125
75
ns
no
Output Data Valid to MEMW High
10DV
ORO to elK Low (51, 54) Setup Time
lOS
elK to READY Low Hold Time
IRH
20
READY to elK Low Setup Time
IRS
60
ADDSTB High trom elK High Delay
Time
tSTl
130
ns
ACOSTB Low from elK High Delay
Time
ISTl
90
no
no
no
ns
Not•••
(!)
@
= 5V ±
-
UmIt.
= OV
Netl/OW or MEMW pulse width for normal write is ICy-100 ns
and 2tCY-100 ns for extended write. Netl/OR or
pulse
Width for normal read IS 2tCY - 50 ns and tCY - 50 ns for compressed read.
MEMR
TOO1 is measured at 2.0V. tOQ2 IS measured at3.3V. An external pullup resistor of 3.3kQ connected from HRO to VCC is
assumed for t002.
Limit.
Parameter
Symbol
Ma.
Unit
IAEL
200
ns
AEN Low from CLK High (SI) Oolay
T!ma
IAET
130
na
ADR Active to Float Delay from elK
High
IAFAB
READ or WRITE Float from elK High
IAFC
120
IAFDB
170
DB Active to F10at Delay from elK
HIgh
Min
Tvp
AEN High from CLK Low (SI) Oolay
Time
AC Characteristics Peripheral Mode
Ta = O°C to +70°C; VCC = 5V ± 5"10; VSS
LImIt.
90
P.rameter
ADR Valod
Symbol
or CS Low 10 READ Uow
Min
TrP
Max
Unit
IAR
50
no
lAW
150
ns
qs
AOR Valid 10 WRITE High SelUp TIme
CS Low 10 WRITE High Setup Time
lew
150
no
ICy-l00
n.
Data Valid 10 WRITE High Setup Time
IDW
150
no
IRA
ADA from READ High HOld Time
IAHR
DB from ADDSTB Low Hold Time
IAHS
30
ns
ADR or CS- Hold lrom READ High
ADR from WRITE High Hold Tlmo
IAHW
Icy-SO
ns
Data Access 'rom READ Low
ns
70
ns
IABTD
500
ns
ns
RESET to First IIOR or I/OW
IRSTS
'2tCY
ns
100
n.
RESET Pul'" Wldlh
IRSTW
300
no
na
REAOW,dth
IRW
200
no
170
AOR from WRITE High Hold Time
IWA
20
ns
CS High from WRITE High Hold Tlma
IWC
20
ns
Data from WRITE High ~Id Time
'Wg
30
ns
Wrtl.Wldth
IWWS
1&0
ns
170
IASM
140
IRDF
EOP High from CLK High Dalay Time
IAK
ns
lROE
Power Supply High 10 RESET Low Salup TIme
170
EOP Low to elK High Delay Time
You m~st time successive read Dr write operations by the CPU to allow at least 400 ns recovery time for the "PD8237A-5 between read and
writ~ pulses.
6-170
/-lPD8237A-S
Timing Waveforms (Cont.)
DMA Transfer
»
,kI'J"MJ"vr ~ ~rl
5,
CLK
tQs-j
ORO
5,
V
_
f--
fl.}
54
las
5,
5,
H~
t---J
tCl
I-
~ ,\ S ~
~tOF
too_
l--
HRQ
HLDA
--tHS
\\ \\' ~
,////1
tAEL
AEN
-
,
j
~
DOSTS
-[AET
-
-
1--,
!-tSTT
1-
-teps
I
TAOS I - 00-0 7
Ao-A7
I
I
1--- tASStA~S
-
As-A15
-
~~
f...tAF1DB
IFAAB~
I
tAK
1...
!-tArw-
TN
Addrel!s Valid
~
I
I----
toel
tDeTR
tFACI--
,
RE AD
E
-
I-
~
_
\~~~~
to
IAHR
"J
tDel
-j
teCTR
I-tAFC
I}---{
_tDCTW
/'f-- ~F--\
I
(For Extended Write)
LA<
~
Internal EOp
,
I-
CTW
I
E)I;ternal EOp
AFAB
Address v"'J.r
Ir\
~
I
IAH~~ ~t
I-t!R-I
/
ACK
tASM
-I f-
tEPW-1
~\\\\\\\'0
See Note 2, AC CharacteristIcs, OMA Mode
6-171
illl'lllllllll
I-lPD8237A':S
Timing Waveforms (Cont.)
Memory-fa-Memory Transfer
522
52t
tFAAB
r
AO-A7
524
523
5t
tAH5
Address Valid
tAFDB
tFADB
DO-D7
OUT
AS-A15
tFADB
tODH
tODV
tFAC
tlOH
tAFC
MEMR
tDCTW
tDCL
tFAC
MEMvi
tAK
n
tEPW
EXT EOP~\.....,\-.-\-r-\"T"""\"T"""\~\~\.---.\\r--"';\--...\-,..\~\-.-\
Ready
EP5
Z-r---
.......,Z,......,Z---.Z~Z---rZ--r-Z
elK
tDCTR
tDCl
READ
tDCTW
tRH
[tR5
READY
\\\\\\\\\\\1
6-172
tR5
t-tPD8237A.5
Timing Waveforms (Cont.)
Compressed Transfer
CLK _ _ _ _..J
AO-A7
READY
Reset
vcc
RESET
I/ORorllOW
Package Outlines
For information, see Package Outline Section 7.
Plastic, f1PD8237C·5
Ceramic, f1PD8237D·5
Cerdip, f1PD8237AD·5
8237A·5DS·REV1· 7·83·TRIUM-CA T
6-173
NOTES
6-174
NEe
",PD8243
",PD8243H
INPUT/OUTPUT EXPANDER FOR
fLPD8048 FAMILY
DEseR I PT ION
The J.lPD8243 Input/output expander IS directly compatible with the J.lPD8048 family
of single·chip microcomputers. Using NMOS technology the J.lPD8243 provides high
drive capabilities while requiring only a single +5V supply voltage.
The J.lPD8243 interfaces to the J.lPD8048 family through a 4·bit I/O port and offers
four 4·blt bi-directional static I/O ports. The ease of expansion allows for multiple
J.lPD8243's to be added using the bus port.
The bi·directlonal I/O ports of the J.lPD8243 act as an extension of the I/O capabilities
of the J.lPD8048 microcomputer family. They are accessible with their own ANL, MOV,
and OR L instructions.
FEATURES
• Four 4-Bit I/O Ports
•
•
•
•
•
•
•
•
Fully Compatible with J.lPD8048 Microcomputer Family
High Output Drive
NMOS Technology
Single +5V Supply
Direct Extension of Resident J.lPD8048 I/O Ports
Logical AND and OR Directly to Ports
Compatible with Industry Standard 8243
Available in a 24·Pin Plastic Package
P50
24
Vee
P40
2
23
P51
P41
3
22
P52
P53
P42
4
21
P43
5
20
P60
CS
6
19
P61
PROG
7
18
P62
P23
8
17
P63
P22
9
16
P73
P21
15
Pn
P20
14
P71
GND
13
P70
J.lPD
8243
Rev/2
6-175
IJPD8243
General Operation
The I/O capabilities of the pPD8048 family can be enhanced in four 4-bit I/O port
increments using one or more pPD8243's. These additional I/O lines are addressed as
ports 4-7. The following lists the operations which can be performed on ports 4·7.
• Logical AND Accumulator to Port.
• Logical OR Accumulator to Port.
• Transfer Port to Accumulator.
• Transfer Accumulator to Port.
Port 2 (P20,P23) forms the 4-bit bus through which the pPD8243 communicates with
the host processor. The PROG output from the pPD8048 family provides the necessary timing to the pPD8243. There are two 4-bit nibbles involved in each data transfer.
The 'first nibble contains the op-code and port address followed by the second nibble
containing the 4-bit data. Multiple pPD8243's can be used for additional I/O. The
output lines from the pPD8048 family can be used to form the chip selects for the
additional pPD8243's.
Power On Initialization
Applying power to the pPD8243 sets ports 4-7 to the tri-state mode and port 2 to the
input mode. The state of the PROG pin at power on may be either high or tow. The
PROG pin must make a high-to-Iow transition in order to exit from the power on
mode. The power on sequence is initiated any time VCC drops below lV. The table
below shows how the 4-bit nibbles on Port 2 correspond to the pPD8243 operations.
Op-Code
Port Address
0
P20
0
1
1
1
0
1
P21
0
Address Code
Port 4
Port 5
Port 6
Port 7
P23
0
0
1
1
P22
0
1
0
1
Instruction Code
Read
Write
ORLD
ANLD
For example an 0010 appearing on P20-P23, respectively, would
result in a Write to Port 4.
Read Mode
There is one Read mode in the pPD8243. A falling edge on the PROG pin latches the
op-code and port address from input Port 2. The port address and Read operation are
then decoded causing the appropriate outputs to be tri-stated and the input buffers
switched on. The rising edge of PROG terminates the Read operation. The Port
(4,5,6, or 7) that was selected by the Port address (P21-P20) is returned to the tri-state
mode, and Port 2 is switched to the input mode.
Generally, in the read mode, a port will be an input and in the write mode it will be an
output. If during program operation, the pPD8243's modes are changed, the first read
pulse immediately following a write should be ignored. The subsequent read signals a~e
valid. Reading a port will then force that port to a high impedance state.
Write Modes
There are three write modes in the pPD8243. The MOVD Pp,A instruction from the
pPD8048 family writes the new data directly to the specified port (4,5,6, or 7). The
old data previously latched at that port is lost. The ORLD Pp,A instruction performs
a logical OR between the new data and the data currently latched at the selected
port. The result is then latched at that port. The final write mode uses the AN LD
Pp,A instruction. It performs a logical AND between the new data and the data currently latched at the specified port. The result is latched at that port.
The data remains latched at the selected port following the logical manipulation until
new data is written to that port.
6-176
FUNCTIONAL
DESCRIPTION
~PD8243
BLOCK DIAGRAM
PIN IDENTIFICATION
PIN
NO.
SYMBOL
2·5
1.21·23
17·20
13-16
P40, P43
P50, P53
P60, P63
P70- P73
The four 4·bit static bi·dlrectional I/O ports. They
are programmable into the following modes:
input mode (during a Read operation); low
impedance latched output mode (after a Write
operation); and the tri-state mode (following a
Read' operation). Data appearing on I/O lines
P20-P23 can be written directly. That data can
also be logically ANDed or 0 Red with the previous
data on those lines.
6
~
Chip Select input (active-low). When the IlPD8343
is deselected (Cs = 1). output or internal
status changes are inhi bited.
7
PROG
Clock input pin. The control and address information are present on port lines P20-P23 when PROG
makes a high-to-Iow transition. Data is present on
port lines P2o-P23 when PROG makes a low-to-high
transition.
8-11
P20-P23
P2o-P23 form a 4-bit bi-directional port. Refer to
PROG function for contents of P20-P23 at the
rising and falling edges of PROG. Data from a
selected port is present on P20-P23 prior to the
rising edge of PROG if during a Read operation.
12
GND
The IlPD8041 /8741 ground potential.
24
VCC
+5 volt supply.
6-177
FUNCTION
J.LPD8243
Operating Temperature
Storage Temperature ...
Voltage on Any Pin
Power Dissipation ..... .
not fully loaded
tACC(MIN)/j.lPD82C43 vs tpcfMAX)ij.lPD80C48, 49
5
250
\
200
~
150
IJ.PD82C43
~CMIN
tPCM~
100
~ i'-..
~
,- ~PD80C48 _
I - ' - ~PD80C49_ ~
~
50
"
Frequency mHz
Package Outlines
For information, see Package Outline Section 7.
Plastic, fLPD82C43C
Cerdip, fLPD82C43D
Plastic Skinnydlp, fLPD82C43CX
6-186
82C43-REV2-7-83-CAT
NEe
,..PD8251A
,..PD8251 AF *
PROGRAMMABLE COMMUNICATION INTERFACES
DESCRIPTION
FEATURES
The ...,PD8251A/AF Universal Synchronous/Asynchronous ReceiverfTransmitter
I USART) is designed for microcomputer systems data communications. The
USART is used as a peripheral and is programmed by the 8080A or other processor
to communicate in commonly used serial data transmission techniques including
IBM Bi-Sync. The USART receives serial data streams and converts them into parallel data characters for the processor. While receiving serial data, the USART will also
accept data characters from the processor in parallel format, convert them to serial
format and transmit. The USART will signal the processor when it has completely
received or transmitted a character and requires service. Complete USART status
including data format errors i!nd control signals such as TxE and SYNDET, is available to the processor at any time.
•
•
•
•
•
•
•
•
•
•
Asynchronous or Synchronous Operation
Asynchronous:
Five 8-Bit Characters
Clock Rate - 1, 16 or 64 x Baud Rate
Break Character Generation
Select 1, 1-1/2, or 2 Stop Bits
False Start Bit Detector
Automatic Break Detect and Handling (IlPD8251A)
Synchronous:
Five 8-Bit Characters
Internal or External Character Synchronization
Automatic Sync Insertion
Sin!jle or Double Sync Characters
Baud Rate (1X Mode) - DC to 64K Baud
Full Duplex, Double Buff!!red Transmitter and Receiver
Parity, Overrun and Framing Flags
Fully Compatible with 8080A/8085/J.LPD780 (Z80TM)
All Inputs and Outputs are TTL Compatible
Single + 5 Volt Supply, ± 10%
Separate Device Receive and Transmit TTL Clocks
28 Pin Plastic,Cerdip,anc;! Ceramic DIP Packages
N-Channel MOS Technology
PIN NAMES
PIN CONFIGURATION
D2
D,
"1-00
D3
00
lIT>
WI\
Ci
elll
RxO
Vcc
Ir.C
fiTA
m
!5Sif
RESET
eLK
RES T
TiC
TxO
Axe
RxO
RxRDY
T..,OY
CLK
TxD
TxE
eft'
RxADY
TM:
Z80 is a registered trademark of Zilog, Inc.
*Preliminary
SYNOET (,.,.082511
SYNOET/BO ,,"P08251A)
TxROY
Rev/6
6-187
oan:.II .... 18btu'
Control or Dat. II to be Written or ANd
R..t 0.18 eo.,....,.nd
Write 0 ...
Of
Control CornfNnd
ChtpEn.tN
Clock Pul. (TTL)
-.
Tl'lln.mln... Clock mLl
Tr.nemltter OM.
.......... Cloc:kITTLI
Rec..""
oar.
Rec.uWl RUdy (hill cherKter for 10801
rl'llnsrtKtter Rqdy (r..tv fOf char from 8080)
Dat.SetA
Dl'R
o.te TfnYtll'llll Rudv
SYNOET
SyncOlt1ect
DeMctIB,. Detect
R-ayes1 to Send p_
SVHDETIBD
RTS
Sync
eTS
c....toSendo.t.
TxE
Vee
T,....,.,«... Empty
+5 Volt Supply
GNO
Ground
IJ.PD8251A/AF
BLOCK DIAGRAM
FhFlOY,
SYNDET/BD I..,PD8251AIAFI
II-PD8251AF ENHANCEMENTS
PRESENT II-PD8251A
NEW II-PD8251AF
1. A prevIously loaded data character WIll be retransmitted
if Tx was disabled before TxEMPTY by TxEnable ~ or
CTS t, and is re-enabled by TxEnable t or CTS ~ before a new data character is sent to ILPDS251A by CPU.
CPU.
A previously loaded character will be flushed out and
not transmItted on CTS ~ or TxEnable t.
2.
Break Detect does not always reset upon RxData returning to a '1' durong the last bit of the character following
the break. Break detect will latch up, and the device
must be cleared by device Reset.
Break Detect will reset on RxData gOing to '1'.
3.
On TxEnable ~ or CTS t during the first character of a
double-character sync output, the second sync character
will not be output.
Will output both sync characters on TxEnable ~ or CTS
4.
If the Status Register is read durong a status update, an
erroneous status read may resuli.
Some valid status (eIther new or old) will always be
available.
5.
In Rx mode, a hardware or software reset does not force
asynchronous mode, clear hunt condition or require Ii
proper line initialization (1 to 0 transitIon) before receiving. This may cause reception of garbage characters.
Reset WIll clear Rx hunt conditIon, force asynchronous
operation (64X clock), and require a proper line initialization before receIving anything.
6.
Break Detect will occur on the first complete (start bIt to
stop bit) break. This situation could be confused with a
null frame (all zeroes) that also has a framing error.
Will give a framing error at the end of the first complete
or partIal break and will gIve a Break Detect at the stop
bit positIon of the second contiguous break character.
t·
7. Sync Detect does not reset on status read.
Sync Detect will reset on status read.
S.
RxRDY will clear on RD leadIng edge.
RxRDY clears within 2 tCY's of RD lellding edge.
9. TxEMPTY oscillates with internal clock when TxEnable
~ or CTS t.
TxEMPTY WIll not oscillate thIS way.
10. TxROY and TxEMPTY clear on WR traoling edge (data).
TxRDY, TxEMPTY will clear on WR leading edge.
11. Enter hunt command affects asynchronous Rx by loss
of data characters.
Enter hunt WIll not affect asynchronous operation.
12. Writing a command will sometimes clear TxRDY or
TxEMPTY if C/O set up or hold is ma.!llinal. Reading status will sometimes clear RxRDY if C/O set up or hold is
marginal.
C/O set up and hold margin WIll be Improved.
13. Rx data overrun error will not occur and garbage data
may result if RD and CS are active during an internal
data update.
Will Indicate an overrun err,or properly.
14. In asynchronous mode, after a reset, the first TxD bIt
may be shifted out on either the first or second TxC ~
edge.
'
The first TxD bit will be shifted out on the first TxC ~
edge.
15. RxRDY can glitch when ClK does not have a f,xed phase
relationship to RxC.
RxRDY will not glitch.
16. The receiver occasionally gives an extra character following the end of Break conditIon.
No extra characters will occur.
6-188
",PD8251A/8251AF
FUNCTIONAL
DESCRIPTION
The ... PD8251A/AF Universal Synchronous/Asynchronous ReceiverlTransmitters are
designed specifically for 8080 microcomputer systems but work with most 8-bit processors. Operations of the ...PD8251A/AF, like other I/O devices in the 8080 family, are
programmed by system software for maximum flexibility.
In the receive mode, the ... PD8251A/AF converts incoming serial format data into
parallel data and makes certain format checks. In the transmit mode, it formats parallel data into serial form. The device also supplies or removes characters or bits
that are unique to the communication format in use. By performing conversion and
formatting services automatically, the USART appears to the processor as a simple
or "transparent" input or output of byte-oriented parallel data.
BASIC OPERATION
c/o
0
0
RD
0
WR
CS
1
1
0
0
0
0
0
1
1
0
1
1
X
X
X
0
X
1
1
PIN IDENTIFICATION
1
0
fLPD8251A/AF~ Data Bus
Data Bus ~ ILPD8251A/AF
Status -+ Data Bus
Data Bus -+ Control
Data Bus -+ 3·Stcte
PIN
NO.
SYMBOL
1,2,
27,28
5-8
07- Do
26
4
FUNCTION
NAME
Data Bus Buffer
An 8·blt, 3-state bl·dlrectlonal buffer used to
onterface the USART to the processor data
bus. Data IS transmitted or received by the
buffer to response to Input/output or Readl
Write instructions from the processor. The
Data Bus Buffer also transfers Control words,
Command words, and Status
Vec
GND
V CC Supply Voltage
+5 volt supply
Ground
Ground
ThiS logic block accepts mputs from the pro·
cessor Control Bus and generates control signals
Read/Wrote Control Logic
6-189
for overali USART operation The Mode
Instruction and Command Instruction registers
that store the control formats for device functional definition are located to the Read!
Write Control Logic
"PD8251 A/AF
PIN IDENTIFICATION
PIN
NO
21
NAME
SYMBOL
RESET
Reset
(CONT)
FUNCTION
A "one" on
thl~'lnput
forces the USART Into the
"Idle" mode where it will remam until remltlal~
ized with a new set of control words. Minimum
I
RESET pulse wIdth IS 6 tCY.
20
ClK
Clock Pulse
The elK Input provides for Internal device tim109 and IS usually connected to the Phase 2 (TTLi
output of the !,PB8224 Clock Generator.
External Inputs and outputs are not referenced
to ClK, but the ClK frequency must be at
least 30 times the Receiver or Transmitter
clocks In the synchronous mode and 4.5
times for the asynchronous mode.
10
WR
Wnte Data
13
RD
Read Data
A "zero" on this Input Instructs the USART
to accept the data or control word which
the processor IS writing out on the
--
data bus.
A "zero" on thIS onput onstructs the USART
to place the data or status Information
onto the Data Bus for the processor to
read
12
C/O
Control/Data
The Control/Data Input,
In
conjunction With the
WR and RD Inputs, onforms the USART to
accept or provIde either a data character,
control word or status Information via the
Data Bus
= Data, 1 = Control.
o
11
CS
ChIp Select
A "zero" on thIS onput enables the USART to
read from or write to the processor.
Modem Control
22
DSR
Data Set Ready
The ",PD8251A/AF have a set of control Inputs and
outputs which may be used to sImplify the '"terface
to. Modem.
The Data Set Ready Input can b. tested by the
processor via Status mformatlon The Bs1i'mput
IS
normally used to test Modem Data Set Ready
condition
24
DTR
Data Termonal Ready
The Data Termmal Ready output can~ con-
trolled vIa the Command word The DTR output
IS normally used to drive Modem Data Termmal
Ready or Rate Select hnes
23
RTS
Request to Send
The Request to Send output ~be controlled
vIa the Command word The RTS output IS
normally used to drive the Modem Request to
Send Ime
17
CTS
Clear to Send
A "zero" on the Clear to Send Input enables the
USART to transmIt seroal data If the TxEN bIt on
the Command Instruction register IS enabled
(onel
6-190
,..PD8251A/AF
TRANSMIT BUFFER
The Transmit Buffer receives parallel data from the Data Bus Buffer via the internal
data bus, converts parallel to serial data, inserts the necessary characters or bits neeaed
for the programmed communication format and outputs composite serial data on the
TxD Pin.
PIN IDENTIFICATION
PIN
(CONT.)
NO.
SYMBOL
FUNCTION
NAME
The Transmit Control Logic accepts and outputs
all external and Internal signals necessary for
senal data transmission.
Transmitter Ready signals the processor that the
transmitter IS ready to accept a data character.
TxRDY can be used as an Interrupt or may be
Transmit Control Logic
15
TxRDY
Transmitter Ready
tested through the Status information for polled
operation. Loading a character from the processor
18
TxE
automatically resets TxRDY, on the leading edge.
The Transmitter Empty output signals the
processor that the USART has no further char-
Transmitter Empty
acters to transmit. TxE IS automatically reset
upon receiving a data character from the pro*
cessor. In half-duplex, TxE can be used to signal
end of a transmiSSion and request the processor
to "turn the line around," The TxEn bit In the
command instruction does not effect TxE.
In the Synchronous mode, a "one" on thiS out*
put IndiCates that a Sync character or characters are about to be automatically transmitted
as "fillers" because the next data character has
not been loaded.
9
The Transmitter Clock controls the serial charac
Transmitter Clock
TxC
ter transmiSSion rate. In the Asynchronous
mode, the TxC frequency IS a multiple of the
actual Baud Rate. Two bits of the Mode Instruction select the multiple to be 1 x, 16x, or 64x
the Baud Rate. In the Synchronous mode, the
TxC frequency IS automatically selected to
equal the actual ~aud Rate
Note that for both Synchronous and Asynchronous modes, serial data IS shifted out of the
USART by the failing edge of TxC.
19
fLPD8251A/AF
INTERFACE TO 8080
STANDARD SYSTEM BUS
TxD
Transmitter Data
\
The Transmit Control Logic outputs the
composite serial data stream on thiS pin.
\
ADDRESS BUS
AO
)
\
CONTROL BUS
1/0 R
\
IIOW
RESET
,)2
ITTL!
\
DATA BUS
/~
8
(
C/D
-
CS
V
D7 - DO
-RD
8251A/AF
6 -191
-WR
RESET
ClK
,..PD8251 AIAF
The Receive Buffer accepts serial data input at the RxD pin and converts the data
R ECE I V E BU F FER
from serial to parallel format. Bits or characters required for the specific communication technique in use are checked and then an eight-bit "assembled" character is
readied for the processor. For communication techniques which require less than
eight bits, the ILPD8251A/AF set the extra bits to "zero."
PIN IDENTIFICATION
PIN
NO.
SYMBOL
FUNCTION
NAME
This block manages all activities related to
Receiver Control Logic
14
RxRDY
incoming data.
Receiver Ready
The Receiver Ready output Indicates that the
Receiver Buffer
IS
ready with an "assembled"
character for' input to the processor For Polled
operation, the processor can check RxRDY
uSing a Status Read or RxRDY can be connected to the processor Interrupt structure
Note that readmg the character to the processor automatically resets RxRDY
25
RxC
Receiver Clock
The Receiver Clock determines the rate at which
the incoming character IS received In the Asynchronous mode, the Rxe frequency may be 1,16
or 64 times the actual Baud Rate but In the Synchronous mode the FfXC frequency must equal
the Baud Rate. Two bits In the mode Instruction
select Asynchronous at lx, l6x or 64x or Synchronous operation at 1 x the Baud Rate
Unhke TxC, data IS sampled by the fLPD8251A/AF
on the rising edge of RxC.
DATA CHA~ACTER
:I
RECEIVE FORMAT
Notes
I
~
2
3
Generated by .... PD8251AJAF
Does not appear on the Data Bus
If character length IS defined as 5, 6, or 7 bits. the
unused bits are set to "zero ..
6-195
",IPD8251 AIAF
As in Asynchronous transmission, the TxD output remains "high" (marking) until SYNCHRONOUS
TRANSMISSION
the ....PD8251A/AF receive the first character (usually a SYNC character) from the
processor. After a Command Instruction has set TxEN and after Clear to Send
(CTS) goes low, the first character is serially transmitted. Data is shifted out on the
falling edge of TxC and the same rate as TxC.
.
Once transmission has started, Synchronous Mode format requires that the serial
data stream at TxD continue at the TxC rate or SYNC will be lost. If a data character
is not provided by the processor before the p,PD8251A/AF Transmit Buffer
becomes empty, the SYNC character(s) loaded directly following the Mode Instruction will be automatically insElrted in the TxD data stream. The SYNC character(s)
are inserted to fill the line and'maintain synchronization until new data characters
are available for transmission. If the .... PD8251A/AF become empty, and must send
the SYNC characters(s), the TxEMPTY output is raised to signal the processor that
the Transmitter Buffer is empty and SYNC characters are being transmitted.
TxEMPTY is automatically reset by the next character from the processor.
In Synchronous Receive, character synchronization can be either external or inter- SYNCH RONOUS
nal.lfthe internal SYNC mode has been selected, and the Enter HUNT (EH) bit has RECEIVE
been set by a Cqmmand Instruction, the receiver goes into the HUNT mode.
Incoming data on the RxD input is sampled on the rising edge of RxC, and the
Receive Buffer is compared with the first SYNC character after each bit has been
loaded until a match is found. If two SYNC characters have been programmed, the
next recElived character is also compared, When the SYNC character(s) programmed have been detected, the fLPD8251A/AF leave the HUNT mode and are in
character synchronization. At this time, the SYNDET (output) is set high. SYNDET
is au~omatically reset by a STATUS READ.
If external SYNC has been specified in the Mode Instruction, a "one" applied to the
SYNDET (input) for at least one RxC cycle will synchronize the USART,
Parity and Overrun Errors are treated the same in the Synchronous as in the Asynchronous Mode. If not in HUNT, parity will continue to be checked even if the
receiver is not enabled. Framing errors do not apply in the Synchronous format.
The processor may command the receiver to enter the HUNT mode with a Command Instruction which sets Enter HUNT (EH) if synchronization is lost
°7
06
lscs}ol
05
04
03
EP
IPENI
L,
I
0-,
01
DO
I I I I
L1
0
l
CHARACTER LENGTH
0
1
0
0
0
1
1
5
6
BITS
7
8
BITS
BITS
I
I
I
MODE INSTRUCTION
FORMAT
SYNCHRONOUS MODE
0
~
BITS
1
PARITY ENABLE
ENABLEl
11
10
DISABLE)
EVEN PARITY GENERATION/CHE CK
1 EVEN
o opo
ExTERNAL SYNC DETECT
SYNDET IS AN INPUT
SYNOET IS AN OUTPUT
' - - - - - - - - - - - - _ SINGLE CHARACTEA SYNC
1 SINGLE SYNC CHARACTER
o DOUBLE SYNC CHARACTER
6-196
,.,PD8251A/AF
PROCESSOR BYTES 15-8 BITS CHARI
TRANSMIT/RECEIVE
FORMAT
SYNCH RONOUS MODE
DATA
C~\:ACHRS
ASSEr\lBLED SERIAL DATA OUTPUT (T"D)
DATACHAR~;_C_TE_R_S
______
~
TRANSMIT FORMAT
SERIAL OAT A INPUT (RxD)
SYNC
CHAR 1
I
CSHY:~}
DA T A
CH~R:I-A_CT_E_R_S
PROCESSOR BYTES 15 8 BITS CHARI
_ _--,
G)
DATAC::~
RECEIVE FORMAT
Note
G)
If character lenqlh
IS
defined (IS 5, 601 7 l)lts. thf' ul1u~pd
bits are set to "7ero "
COMMAND INSTRUCTION
FORMAT
STATUS READ FORMAT
PARITY ERROR
OV E R RUN ERROR
FRAMING ERROR
CD
After the functional definition of the fLPD8251A/AF has been specified by the Mode
Instruction and the SYNC character(s) have been entered (if in SYNC mode), the
USART is ready to receive Command Instructions and begin communication. A
Command Instruction is used to control the specific operation of the format
selected by the Mode Instruction. Enable Transmit, Enable Receive, Error Reset and
Modem Controls are controlled by the Command Instruction.
After the Mode Instruction and the SYNC character(s) (as needed) are loaded, all
subsequent "control writes" (Ci5 = 1) will load or overwrite the Command Instruction register. A Reset operation (internal via CMD IR or external via the RESET
input) will cause the fLPD8251A/AF to interpret the next "control write", which must
immediately follow the reset, as a Mode Instruction.
It is frequently necessary for the processor to examine the status of an active interface device to determine if errors have occurred or if there are other conditions
which require a response from the processor. The fLPD8251A/AF have features
which allow the processor to read the device status at any time. A data fetch is
issued by the processor while holding the ci5 input "high" to obtain device Status
Information. Many of the bits in the status register are copies of external pins. This
dual status arrangement allows the fLPD8251A/AF to be used in both Polled and
interrupt driven environments. Status update can have a maximum delay of 28
clock periods in the fLPD8251A/AF.
When a parity error is detected, the PE flag is set. It is cleared by setting the
ER bit in a subsequent Command Instruction. PE beong set does not inhibit USART
operation.
If the processor fails to read a data character before the one following is available,
the OE flag is set. It is cleared by setting the E R bit in a subsequent Command
Instruction. Although OE being set does not inhibit USART operation, the
previously received character is overwritten and lost.
If a valid STOP bit IS not detected at the end of a character, the FE flag is ~et. It
IS cleared by settong the ER bit In a subsequent Command Instruction. FE being set
does not inhibit USART operation.
Note.
CD
ASYNC mode only.
6-197
IlPD8251A/AF
COMMAND INSTRUCTION
FORMAT
TRANSMIT ENABLE
1
=
enable
0"'- disable
DATA TERMINAL
READY
"high" will force
i5TR
output to zero
RECEIVE ENABLE
1" enable
0'" disable
SEND BREAK
CHARACTER
1 = forces TxD "low"
0'" normal operation
ERROR RESET
1'" reset all error flags
PE, QE, FE
REQUESrrO SEND
"hIgh" wIll force
output to zero
RTs
INTERNAL RESET
"high" returns USART to
Mode InstructIOn Format
ENTER HUNT MQDE
1 '" enable sealch for Sync
Charactels
CD
STATUS READ FORMAT
0,
I I I I I I I IL
DSR
SYNDET
IBD
FE
DE
PE
I 1
T,E
R,RDY
T,ROY
1 1
SAME DEFINITIONS AS 110 PINS
PARITY ERROR
The PE flag IS set when a parity
error IS detected. It IS reset by
the ER bit afthe Command
Instruction, PE does not mhiblt
operation of the ,.."PD8251A/AF
OVERRUN ERROR
'----
The OE flag IS set when the CPU
does not read a character before
the next one becomes available
It IS reset by the ER bit of the
Command Instruction. DE does
not inhibit operation of the
fJ..PD8251A/AF, but, the prevIously overrun character IS lost.
FRAMfNG ERROR (Async only)
The FE flag IS set when a valid
Stop bit IS not detected at the
end of every character It IS
reset by the ER bit of the
Command Instruction FE does
not inhibit the operation of the
.P08251AIAF.
Notes
CD
No effect
@
TxADY status bit IS I'IOt totallv eqUivalent to the TxADY OlItput pm. the relatlOAShlP
IS
6-198
In
ASYNC mode
as follows
ixROY status bit'" DB Buffer Emptv
TxADY (pm 1 SI '" DB Buffer Emptv •
m •hEn
",PD8251A/AF
ADDRESS BUS
APPLICATION OF THE
f.lPD8251 AIAF
CONTROL BUS
DATA BUS
,.----,
EIATOTTl~
L~:'::O~A':'J
~
CONVERTER
"PD
8251AI
AF
BAUD RATE
GENERATOR
CRT
TERMINAL
ASYNCHRONOUS SERIAL INTERFACE TO CRT TERMINAL,
OC to 9600 BAUD
PHONE
L1NF
INTER
FACE
TELEPHONE
LINE
ASYNCHRONOUS INTERFACE TO TELEPHONE LINES
SYNCHRONOUS
TERMINAL
OR PERIPHERAL
DEVICE
SYNCHRONOUS INTERFACE TO TERMINAL OR PERIPHERAL DEVICE
PHONE
LINE
INTER
FACE
TELEPHONE
LINE
SYNCHRONOUS INTERFACE TO TELEPHONE LINES
6-199
IlPD8251A/AF
... -OoC to +70°C
_65°C to +150°C
-0.5 to +7 Volts
.-0.5 to +7 Volts
-0.5 to +7 Volts
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ali Output Voltages. . . . . . . .. . . . . . . . . .
All Input Voltages. .
. .....•..
Supply Voltages
................... .
ABSOLUTE MAXIMUM
RATINGS·
Ta = 25°C
·COMMENT. Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This IS a stress rating only and functional operation of the device at these or
any other conditions above those Indicated in the operational sections of this specification IS not
implied. Exposure to absolute 1"18ximum rating conditions for extended periods may affect device
rei iab., ity .
Ta
=O"Cto70"C;VCC = 5.0V ± 10%for8251A/AF;GND = OV.
DC CHARACTERISTICS
LIMITS
fLPD8251 AIAF
PARAMETER
SYMBOL
Input Low Voltage
VIL
Input High Voltage
VIH
Output Low Voltage
VOL
Output High Voltage
VOH
MIN
MAX
-0.5
08
2.0 Vee
0.45
2.4
UNIT
V
V
V
±10
Output Float Leakage
IOFL
Input Load Current
IlL
10
~A
Power Supply Current
ICC
laO
mA
10
TEST CONDITIONS
V
~A
~PD8251
IOL= 1.7mA
~PD8251A
IOL = 2.2mA
~PD8251.
IOH' -10C ~A
~P08251A
IOH = -400~A
VOUT = 0.45V
.45V", VOUT '" VCC
.45V '" VIN '" VCC
All Outputs = LogiC 1
Ta = 25"C. VCC' GND' OV
LIMITS
PARAMETER
SYMBOL
MIN
TY'
MAX
UNIT
CAPACITANCE
TEST
CONDITIONS
Input Capacitance
CIN
10
pF
Ie· 1 MHz
I/O Capacitance
CliO
20
pF
Unmeasured
pins returned
toGND
TESTING INPUT, OUTPUT WAVEFORM
a-Fi
2V
INPUTIOUTPUT
4201l18251A AF)
D.U.T.
r
CL
~
/
"0
~
>-
::>
o
/
-10
-20
-100
TEST LOAO CIRCUIT
6-200
~
6K 18251 A AF)
Figure 1.
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC "1" AND
o4SV FOR A LOGtC "0" TIMING MEASUREMENTS ARE MADE AT 2 OV
FOR A LOGIC "1" AND 0 8V FOR A LOGIC "0 "
'20
c
V
SPEC
/
-50
'50
"00
.6 CAPACITANCE (pFI
TYPical a Output
Delay Versus a Capacitance (pFI
IlPD8251 AIAF
AC CHARACTERISTICS
Ta = o'e to 70'e; Vee = 5.0V ± 10% for 8251A/AF; GND = OV.
LIMITS
PARAMETER
SYMBOL
I
MIN
I
j.lPDB251AF
IlPD8215A
MAX
I
I
MIN
MAX
TEST
I UNIT
CONDITIONS
READ
Address Stable belere READ (eS C OJ
W
90
Clock Rise and Fall Time
'RtF
TleD Deley from Failing Edge of Tlce
IDTx
RII: Data Set-Up Time to Sampling Pulse
'SAx
Rx Data Hold Time to Sampling Pulse
tHRx
Transmitter Input Clock Frequency
lXBaud Rate
'T,
135
20
Icv- 9O
70
64X Baud Rate
135
'CY-40
20
.'.'
.'
B4
DC
64
kH,
310
DC
OlD
kH,
615
DC
615
kH,
ITPW
12
12
15
15
'CY
l6X and 64X Baud Rate
'CY
Transmitter Input Clock Pulse Delay
IX Baud Aate
ITPO
'CY
16X and 64X Baud Rate
'cv
Receiver Input Clock Frequency
IX Baud Rate
OC
'R,
64
kH,
l6X Baud Rate
310
DC
310
Kh>
64X Baud Aate
615
DC
615
kH,
Receiver Input Clock Pulse Width
IX Baud Rate
64
12
12
'CV
'cy
Receiver Input Clock Pulse Delay
IX Baud fl:ate
I RPD
15
15
'cy
t6X and 64X 8aud Aate
'CY
'T,
TKROY Delay from Center of Data Bit (i
TxRDY
1 from L.eadlng Edge of WR @
'cy
300
ITxADY
CLEAR
RKRDY Delay from Center of Data Bit
..
Internal SYNDET Delay from Center of Data 81t
RxRDY 1 from leading EdQa of AD C!l
EXlarnal~OET
D
tAPW
16X and 64X Baud Rate
'RX
24
'IS
24
20
'ES
Edge of RxC (j)
300
"
16
20
tTxE
~rQ1..1&lay from RISing Edge of WRITE ITKE.
'cV
20
'oR
'cy
'Cy
'WC
OTR RTS)$
Control to READ Set-Up Time (DSR. CTS) $
'CY
'CY
lAx ROY
CLEAR
Set-lJp Time before Failing
TxEMPTY Delay from Center of Data Bit --"'__ '000
CLOCK AND GATE TIMING
READ TIMING
A" AQ,
cs __"l'_________f-o'f' ____
DATA BUS _ _ _ _
-J~~--~~"~
___
WRITE TIMING
6-208
IlPD8253
PROGRAMMING
THE IlPD8253
The programmer can select any of the SIX operational MODES for the counters uSing
system software. IndiVidual counter programming IS accomplished by loading the
CONTROL WORD REGISTER with the appropriate control word data (AO, A1 ~ 11).
CONTROL WORD FORMAT
SC - Select Counter
SC1
SCO
0
0
Select Counter 0
0
1
Select Counter 1
1
0
Select Counter 2
1
1
Invalid
R L - Read/Load
RL1
RLO
0
0
Counter Latching Operation
1
0
Read/Load Most Significant Byte Only
0
1
Read/Load Least Significant Byte Only
1
1
Read/Load Least Significant Byte F ITESTPOINTS
Q8
Q8
0.45
TIMING
WAVEFORMS
WRITE MODE
WR ---------~
---twLWH
cs __________.
ADDRESS BUS
AO _ _ _ _ _ _ _ _J
DATA BUS
READ/iNTA MODE
RD/iiiiTA _ _ _ _ _ _ _""""" t - - - - - - t R L R H - - -
EN--------------~--~
tRLEl
tRHAX
cs------__
ADDRESS BUS
AO _ _ _ _ _ _ _ _. J
DATA BUS- _ _ _ _ _ _ _ _ _ _ _ _
~A~~~~\.
tR_H_D_Z---,~
______
OTHER TIMING
6-236
_____ _
,..PD8259A
,::Jd
TIMING WAVEFORMS
(CONT.)
INTA SEQUENCE
_~\_(j)---"'\\
J_tJHI_Hc_
...
~--------------~
DB - - - - - - - - - - - -
-1-0 --
-0--
'tCVIAL-1 1--
~--1---~r-~--~
tCVDV --
CD-2----------------~----L4----~----~~----------~
IR TRIGGERING TIMING REQUIREMENTS
EARLIEST IR
CAN BE REMOVED
LATCH'
ARMED
LATCH'
ARMED
LATCH'
ARMED
IA
8086/8088
INT
8080/8085
---+*""
INTA ---+----~
8080/8085
'EDGE TRIGGERED MODE ONLY
DETAILED OPERATIONAL
DESCRIPTION
The sequence used by the ~PD8259A to handle an interrupt depends upon whether
an 8080A/8085A or 8086/8088 CPU is being used.
The following sequence applies to 8080A/8085A systems:
The ~PD8259A derives its versatility from programmable interrupt modes and the
ability to jump to any memory address through programmable CALL instructions. The
following sequence demonstrates how the ~PD8259A interacts with the processor.
1. An interrupt or interrupts appearing on IRO-7 sets the corresponding IR bit(s)
high. This in turn sets the corresponding IRR bit(s) high.
2. Once the I R R bit(s) has been set, the ~PD8259A will resolve the priorities
according to the preprogrammed interrupt algorithm. It then issues an INT signal
to the processor.
3. The processor group issues an INTA to the ~PD8259A when it receives the INT.
4. The INTA input to the ~PD8259A from the processor group sets the highest
priority ISR bit and resets the corresponding IRR bit. The INTA also signals the
~PD8259A to iSSUE! an 8-btt CALL instruction op-code (11001101) onto its Data
bus lines.
5. The CALL instruction code instructs the processor group to issue two more
INTA pulses to the ~PD8259A.
6-237
IlPD8259A
6. The two INTA pulses signal the j.lPD8259A to place its preprogrammed interrupt DETAILED OPERATIONAL
vector address onto the Data bus. The first INTA releases the low-order 8-bits
DESCRIPTION
of the address and the second INTA releases the high-order 8-bits.
(CONT.)
7. The j.lPD8259A's CALL instruction sequence is complete. A preprogrammed
EOI (End-of-Interrupt) command is issued to the j.lPD8259A at the end of an
interrupt service routine to reset the ISR bit and allow the /.IPD8259A to service
the next interrupt.
For 8086/8088 systems the first three steps are the same as described above, then the
following sequence occurs:
4. During the first i'NTA from the processor, the j.lPD8259A does not drive the
data bus. The highest priority ISR bit is set and the corresponding IR R bit is
reset.
5. The j.lPD8259A puts vector onto the data bus on the second INT A pulse from
the 8086/8088.
6. There is no third INTA pulse in this mode. In the AEOI mode the ISR bit is
reset at the end of the second INTA pulse, or it remains set until an EOI command is issued.
8080A/8085A MODE
For these processors, the j.lPD8259A is controlled by three INTA pulses. The first
INTA pulse will cause the j.lPD8259A to put the CALL op-code onto the data bus. The
second and third ii\i'i'A pulses will cause the upper and lower address of the interrupt
vector to be released on the bus.
07
CALL CODE
De
05
1M
03
02
01
DO
LI_'______o_,~-_----,....JI
07
De
0$
7
A7
A6
A5
6
A7
A6
A5
0.
,
DO
A7
A6
A5
A7
A6
A5
,
,
,
,
'3
A7
A6
A5
0
2
A7
A6
A5
0
,
A7
A6
A5
0
0
.,
0
0
A7
A6
A5
0
0
0
0
0
07
os
OS
0.
03
02
0'
DO
,
0
0
0
0
0
0
0
0
,
,
0
0
0
0
0
0
0
0
0
0
0
5
0
IR
7
FIRST 'j'jij'fA
Inl.,.._4
IR
•
,
INTERRUPT
SEQUENCE
03
02
,
0
,
0'
0
0
,
,
0
0
0
0
0
0
0
0
,
0
0
0
0
0
0
SECONDINTA
Interv.I ... 1
A7
A6
,
,
,
,
6
A7
A6
5
A7
A6
4
A7
A6
,
3
A7
AS
0
,2
A7
A6
0
,
0
0
A6
0
0
,
0
A7
0
0
0
0
A7.
A6
0
0
0
0
0
0
,
,
0
6-238
"PD8259A
INTERRUPT
SEQUENCE
(CONT.)
TH I R 0 Tfii'i'A
D7
De
DS
DO
DS
D.
D'
DO
A'5
A,.
A,3
.,2
A11
A,O
A9
A8
In this mode only two INTA pulses are sent to the J.lPD8259A. After the first INTA
pulse, the J.lPD8259A does not output a CALL but internally sets priority resolution.
If it is a master, it sets the cascade lines. The interrupt 'vector is output to the data bus
'
on the second INTA pulse.
IR7
IR6
IR5
IR4
IR3
IR2
IRl
IRO
07
06
05
D4
D3
T7
T6
T6
T6
T6
T6
T6
T6
T6
T5
T5
T5
T5
T5
T5
T5
T5
T4
T4
T4
T4
T4
T4
T4
T4
T3
T3
T3
T3
T3
T3
T3
T3
T7
T7
T7
T7
T7
T7
T7
02
1
1
1
1
0
0
0
0
01
1
1
0
0
1
1
0
0
DO
1
0
1
0
1
0
1
0
INITIALIZATION ICW1 AND ICW2
COMMAND WORDS A5·A15. Page starting address of service routines. In an 8085A system, the 8 request
levels generate CALLs to 8 locations equally spaced in memory. These can be programmed to be spaced at intervals of 4 or 8 memory locations, thus the 8 routines
occupy a page of 32 or 64 bytes, respectively.
The address format is 2 bytes long (AO-A15). When the routine interval is 4, AO-A4 are
automatically inserted by the J.lPD8259A, while A5-A15 are programmed externally.
When the routine interval is 8, AO-A5 are automatically inserted by the J.lPD8259A,
while A6-A15 are programmed externally.
The 8-byte interval maintains compatibility with current software, while the 4-byte
interval is best for a compact jump table.
In an MCS-86 system, T7-T3 are inserted in the five most significant bits of the vectoring byte and the J.lPD8259A sets the three least significant bits according to the interrupt level. AlO-A5 are ignored and ADI (Address Interval) has no effect.
LTIM:
If LTIM = 1, then the J.lPD8259A operates in the level interrupt mode.
Edge detect logic on the interrupt inputs is disabled.
ADI:
CALL address interval. ADI = 1 then interval = 4; ADI = 0 then
interval = 8.
SNGL:
Single. Means that this is the only J.lPD8259A in the system. If SNGL =
1 no ICW3 is issued.
If this bit is set - ICW4 has to be read. If ICW4 is not needed, set
IC4 =0.
IC4:
ICW3
This word is read only when there is more than one J.lPD8259A in the system and cascading is used, in which case SNGL = O. It will load the 8-bit slave register. The functions of this register are:
a. In the master mode (either when SP = 1, or in buffered mode when M/S = 1 in
ICW4) a "1" is set for each slave in the system. The master then releases
byte 1 of the call sequence (for 8085A system) and enables the corresponding slave to release bytes 2 and 3 (for 8086/8088 only byte 2) through the
cascade lines.
6-239
",PD8259A
b. In the slave mode (either when SP = 0, or if BUF = 1 and M/S = 0 in ICW4)
bits 2-0 identify the slave. The slave compares its cascade input with these bits
and if they are equal, bytes 2 and 3 of the CALL sequence (or just byte 2 for
8086/8088) are released by it on the Data Bus.
INITIALIZATION
COMMAND WORDS
(CONT.)
ICW4
SFNM:
If SFNM = 1 the special fully nested mode is programmed.
BUF:
If BUF = 1 the buffered mode is programmed. In buffered mode SP/EN
becomes an enable output and the master/slave determination is by
M/S.
M/S:
If buffered mode is selected: M/S = 1 means the pPD8259A is programmed to be a master, M/S = 0 means the J.lPD8259A is programmed
to be a slave. If BUF = 0, M/S has no function.
AEOI:
If AEOI = 1 the automatic end of interrupt mode is programmed.
pPM:
Microprocessor mode: pPM = 0 sets the pPD8259A for 8085A system
operation, pPM = 1 sets the pPD8259A for 8086 system operation.
D7
DO
DO
1M
III
D2
D1
DO
1·
L-______A_7_______
M______M
______-r______
Ln_M______
A_~_____S_N_Q_L_____
'~_JJ~W1
I
1
A15/17
A141T6
A13/T5
A121T4
Al1fT3
A10
A9
S2/1"02
S1/101
MIS
AlOI
AI IICW2
~------------------~r_--------------------J
r-----------------~~N:~.~
~11-~-L.~
I
1
Sf
as
sa
50
83
~~.
SO/IDO IICWI
~~·DI
YES
I
1
SFNM
(ac.-1)
IU'
I
I
READY TO ACCEPT INTERRUPTS
6-240
•... I~w.
INITIALIZATION
SEQUENCE
",PD8259A
OPPERATIONAL COMMAND
WORDS (OCW's) @
Once the IlPD8259A has been programmed with Initialization Command Words,
It can be programmed for the appropriate interrupt algorithm by the Operation
Command Words. Interrupt algorithms In the IlPD8259A can be changed at any time
during program operation by issuing another set of Operation Command Words. The
following sections describe the various algorithms available and their associated OCW's.
INTERRUPT MASKS
The individual Interrupt Request input lines are maskable by setting the corresponding
bits in the Interrupt Mask Register to a logic "1" through OCW1. The actual masking
is performed upon the contents of the In·Service Register (e.g., if Interrupt Request
line 3 is to be masked, then ,only bit 3 of the IMR is set to logic "1." The IMR in turn
acts upon the contents of the ISR to mask bit 3). Once the IlPD8259A has acknowledged
an interrupt, I.e., the IlPD8259A has sent an INT signal to the processor and the system
controller has sent it an INTA signal, the interrupt input, although it is masked,
Inhibits lower Priority requests from being acknowledged. There are two means of
enabling these lower priority interrupt lines. The first is by issuing an End-of-Interrupt
(EOI) through Operation Command Word 2 (OCW2), thereby resetting the appropriate ISR bit. The second approach is to select the Special Mask Mode through OCW3.
The Special Mask Mode (SMM) and End-of-Interrupt (EOI) will be described in more
detail further on.
FULLY NESTED MODE
The fully nested mode IS the J.lPD8259A's basic operating mode. It will operate in this
mode after the initialization sequence, without requiring Operation Command Words
for formatting. Priorities are set IRa through IR7, with IRa the highest priority. After
the Interrupt has been acknowledged by the processor and system controller, only
higher priOrities will be serviced. Upon receiving an INTA, the priority resolver
determines the priOrity of the Interrupt, sets the corresponding I R bit, and outputs the
vector address to the Data bus. The EOI command resets the corresponding ISR bits at
the end of its service routines.
Notes:
G)
®
Reference Figure 2
Reference Figure 3
6-241
IlPD8259A
ROTATING PRIORITY MODE COMMANDS
The two variations of Rotating Priorities are the Auto Rotate and Specific Rotate
modes. These two modes are typically used to service interrupting devices of equivalent
priorities.
1. Auto Rotate Mode
Programming the Auto Rotate Mode through OCW2 assigns priorities 0-7 to the
interrupt request input lines. Interrupt line IRO is set to the highest priority and
I R7 to the lowest. Once an interrupt has been serviced it is automatically
assigned the lowest priority. That same input must then wait for the devices
ahead of it to be serviced before it can be acknowledged again. The Auto Rotate
Mode is selected by programming OCW2 in the following way (refer to Figure 3):
set Rotate Priority bit "R" to a logic "1"; program EOI to a logic "1" and SEOI
to a logiC "0." The EOI and SEOI commands are discussed further on. The
following is an example of the Auto Rotate Mode with devices requesting
interrupts on lines IR2 and IR5.
Before Interrupts are Serviced:
IS7
In-Service Register
IS6
IS5
IS4
IS3
IS2
IS1
ISO
I ° I ° I I ° I ° I I° I °
Priority Status
Register
--
Highest
Priority
According to the Priority Status Register, IR2 has a higher priority than IR5 and
will be serviced first
After Servicing:
In-Service Register 1
..._OC-.----------4 D
Q
RESET
CK
+----------O-CLK
EFI--~======::(YPCLK
CSYNC------------~~==============i=::--~--:J
RDY1--------~--~~==t:}
1------<_ READY
~---;:--I
AEiii2~~=:J
RDY2
~------------------~
FUNCTIONAL DESCRIPTION
The clock generator can provide the system clock from either a crystal or an external
TTL source. There is an internal divide by three counter which receives its input from
either the crystal or TTL source (EFI Pin) depending on the state of the F/Cinput
strapping. There is also a clear input (C SYNC) which is used for either inhibiting the
clock, or synchronizing it with an external event (or perhaps another clock generator
chip). Note that if the TTL input is used, the crystal oscillator section can still be used
for an independent clock source, using the asc output.
For driving the MaS output level, there is a 33% duty cycle MaS output (CLK) for the
microprocessor, and a TTL output (PCLK) with a 50% duty cycle for use as a peripheral
clock signal. Th is clock is at one half of the processor clock speed.
Reset timing is provided by a Schmitt Trigger input (m) and a flip·flop to synchronize
the reset timing to the falling edge of CLK. Power·on reset is provided by a simple RC
circuit on the RES input.
There are two READY inputs, each with its own qualifier (AEiiii, AEN2). The unused
AEN signal should be tied low.
The READY logic in the 8284A synchronizes the RDY1 and RDY2 asynchronous inputs
to the processor clock to insure proper set up time, and to guarantee proper hold time
before clearing the ready signal.
6-265
",PB8284A
........ oOe to 700e
Operating Temperature
Storage Temperature ..
All Output and Supply Voltages.
. -65°e to +150o e
. .. -O.5Vto+7V
. . - 1 .OV to +5.5V
All Input Voltages . . . . . . . . . .
ABSOLUTE MAXIMUM
RATINGS*
*COMMENT Stress above those listed under "Absolute Maximum Ratmgs" may cause permanent
damage to the device. This IS a stress rating only and functIOnal operation of the device at these or
any other conditions above those mdicated In the operational sections of this speCification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Conditions: Ta ~ O°C to 70°C, VCC ~ 5V ± 10%
PARAMETER
SYMBOL
DC CHARACTERISTICS
MIN
Forward Input Current [ASYNC) IF
(Other Inputs)
MAX
UNIT
-1.3
-0.5
mA
Il A
Reverse Input Current
IR
50
Input Forward Clamp Voltage
Vc
-1.0
140
TEST
CONDITIONS
VF
~
0.45V
VF = O.45V
V
VR
~
5.25V
Ic~-5mA
Power Supply Current
lee
Input low Voltage
Vil
mA
V
VCC~
Input High Voltage
VIH
2.0
V
VCC
~
5.0V
Reset Input High Voltage
VIHR
2.6
V
VCC
~
5.0V
0.8
5.0V
~IOl
Output low Voltage
VOL
V
5 mA
Output High Voltage (ClK)
(Other Outputs)
VOH
4
2.4
V
V
-1mA}
-1 mA IOH
RES Input HystereSIS
VIHR,VILR
0.25
V
VCC
0.45
~
5.0V
AC CHARACTERISTICS
Conditions: Ta""· O°C to 70°C, VCC=5V ± 10%
TIMING REQUIREMENTS
PARAMETER
External Frequency High Time
SYMBOL
TEHEl
MIN
UNITS
25
"'
n,
"'
MH,
13
External Frequency low Time
TElEH
13
EFI Period
TElEl
TEHEL+TElEH+1i
XTAL Frequency
MAX
12
ROY1, ROY2 Set-Up to ClK
TR1VCl
ROY1, ROY2 Hold to ClK
TClR1X
AEN1, AEN2 Set-Up to ROY1, ROY2
TA1VR1V
AEN1, AEN2 Hold to ClK
TClA1X
0
CSYNC Set-Up to EFI
TYHEH
CSYNC Hold to EFI
TEHYl
20
10
CSYNC Width
TYHYl
2 TElEl
RES Set·Up to ClK
TllHCl
RES Hold to elK
TCll1 H
35
ROYl, RDY2 Active Set-Up to ClK
tR1VCH
ROY1, RDY2 Inactive Set.Up to ClK
tR1VCL
35
ASYNC Set Up to ClK
tAYVCl
50
ASYNC Hold to ClK
tClAYX
0
Input Rise Time
tlllH
Input Fall Time
tlLll
90%·90% VIN
10%-10% VIN
1
"'
0
"'
"'n,
"'
n,
15
65
20
35
TEST
CONDITIONS
20
12
6-266
"'
"'
"'
"'
"'n,
"'
"'
n,
2
(2)
ASYNC - lOW
From 0 8V to 2 OV
From 2 OV to 0 8V
",PB8284A
AC CHARACTERISTICS
(CONT.)
TIMING RESPONSES
TEST
PARAMETER
eLK Cycle Period
TCLCL
elK High Time
TCHCL
(1/3 TCLCL) +20
eLK Low Time
TCLCH
(2/3 TCLCL) -15
elK Rise and Fall Time
TCH1 CH2
TCL2CL 1
PCLK High Time
PCLK Low Time
Ready Inactive to elK
Ready Active to eLK
125
TCLCL -20
TPLPH
TCLCL -20
TRYLCL
(3)
TRYHCH
a
10
TPHPL
4
MAX
MIN
SYMBOL
-8
(2/3 TCLcL)-15 0
40
22
eLK To Reset Delay
TCLIL
elK to PCLK High Delay
TCLPH
elK to PCLK Low Delay
TCLPL
ase to elK High Delay
TOLCH
-5
ase to elK
TOLCL
2
22
12
Output Rise Time (except elK)
tOLOH
22
20
Output Fall Time (except elK)
tOHOL
12
Notes:
Low Delay
UNITS
"'
n'
n,
n,
n,
n,
n,
n,
n,
n,
n,
n,
n,
n,
n,
CONDITIONS
Figure 3 and Figure 4
Figure 3 and Figure 4
1 OV to 3 5V
Figure 5 and Figure 6
Figure 5 and Figure 6
From GaV to 2 OV
From 2 OV to a.BV
A
0
1
A->8
1
0
} A and 8
1
1
HIGH
IMPEDANCE
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . oOe to 70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°e to +150o e
All Output and Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . -O.5V to +7V
All Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +5.5V
Ta
=
25°C
*COMMENT: Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
6-270
ABSOLUTE MAXIMUM
RATINGS*
",PB8286/8287
DC CHARACTE R ISTICS
Ta = o°c to 70°C, VCC = 5V ± 10%
SYMBOL
PARAMETER
Input Clamp Voltage
.1- 8287
I.
Power Supply Current
8286
MAX
UNITS
Vc
MIN
-1
V
Icc
ICC
130
160
rnA
rnA
TEST CONDITIONS
IC =-5 rnA
Forward Input Current
IF
-02
rnA
VF =045V
Reverse Input Current
IR
50
~A
VR = 5.25V
Output Low Voltage
- B Outputs
- A Outputs
VOL
Output High Voltage
- B Outputs
- A Outputs
VOH
Output Off Current
Output Off Current
Input Low Voltage
1- A Side
I
B Side
- A Side
'nput Capacitance
V
V
IOL = 32 rnA
IOL=16rnA
V
V
IOH - -5 rnA
IOH =-1 rnA
VOFF = 045V
VOFF = 5 25V
IF
IR
- 00.8
9
VIL
VIL
VIH
i
CD B Outputs -
24
2.4
IOFF
IOFF
Input High Voltage
Note
0.45
0.45
2.0
CIN
16
V
V
VCC = 50V
VCC = 50V
V
VCC=50V
pF
CD
CD
CD
F '" 1 MHz
VBIAS - 2.5V, VCC = 5V
F = 1 MHz
Ta = 25°C
IOL = 32 rnA, IOH = -5 rnA, CL = 300 pF
A Outputs - IOL = 16 rnA, IOH = -1 rnA, CL = 100 pF
AC CHARACTERISTICS
Ta = O°C to 70°C, VCC = 5V ± 10%
SYMBOL
TIVOV
PARAMETER
Input to Output Delay
Inverting
Non-Inverting
MIN
MAX
UNITS
5
5
22
30
ns
ns
Transmit/Receive Hold Time
Transmit/Receive Setup
TEHOZ
Output Disable Time
TELOV
Output Enable Time
TILlH,
TOLOH
Input Output Rise Time
20
ns
TIHIL,
TOHOL
Input Output Fall Time
12
ns
TEHOZ
5
22
ns
10
30
ns
S Outputs - IOL = 32 mA, IOH = -5 mA, CL = 300 pF
A Outputs - IOL = 16 mA, IOH =-1 mA, CL = 100 pF
INPUT/OUTPUT
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC "1" AND 0,45V FOR
A LOGIC "0" TIMING MEASUREMENTS ARE MADE AT 1 5V FOR BOTH
A LOGIC "'" AND "0"
6-271
ns
10
Notes: See waveforms and test load circuit_
AC TESTING INPUT
OUTPUT WAVEFOR'M
ns
TEHTV
TTVEL
",PB8286/8287
WAVEFORMS
I.""
TEHOl
r-
TELOW
OUTOU..
~ - TEHTV---j
__________________
15V
OUT
OUT
214V
~-r
OUT
to VOl.
~."
S-STATE TO VOL
SWITCHING
BOUTPUT
A OUTPUT
BOUTPUT
uv
tlV
..av
....
OUT
TEST LOAD CI RCUITS
I-"
t....
t_
OUT
~t~~--
UV
~-r. .
a.&TATE
TTYIL
~-r
OUT
t....
~'-1'....
MTATETOYOH
IoSrATETO YOH
SWITCHING
BOUTPUT
A OUTPUT
A OUTPUT
FUNCTIONAL
MOS microprocessors like the BOBO/BOB5A/BOB6 are generally capable of dnvmg a
smgle TTL load. This also applies to MOS memory devices. While suffi~lent for min- DESCRIPTION
imum type small systems on a smgle PC board, It IS usually necessary to buffer the
mIcroprocessor and memory sIgnals when a system IS expanded or sIgnals go to other
PC boards.
These octal bus transceivers are designed to do the necessary buffering.
Bi-Directional Driver
Each buffered Ime of the octal dnver consists of two separate tri-state buffers. The B
side of the driver IS designed to drive 32 mA and interface the system side of the
bus to I/O, memory, etc. The A side IS connected to the microprocessor.
Control Gating, OE, T
The OE (output enable) Input is an active low signal used to enable the dri'vers selected
by T on to the respective bus.
T is an input control signal used to select the direction of data through the transceivers. When T is high, data is transferred from the AO-A7 inputs to the BO-B7 outputs, and when low, data is transferred from BO-B7 to the AO-A7 outputs.
6-272
,..PB8286/8287
Package Outlines
For information, see Package Outline Section 7.
Plastic, fLPB8286C/87C
Cerdlp, fLPB8286D/87D
8286/8287-DS-REV1-12-81-CAT
6-273
Notes
6-274
NEe
,..PB8288
CPU SYSTEM
BUS CONTROLLER
DESCRIPTION
FEATU RES
The J.LPB8288 bus controller is for use in medium to large J.LPD80B6/8088 systems. This
20'pm bipolar component provides command and control timing generation, plus
bipolar drive capability and optimal system performance. It provides both
MultibusTM command signals and control outputs for the microprocessor system.
There is an option to use the controller with a multi·master system bus and separate
I/O bus.
• System Controller for IlPD8086/8088 Systems
•
•
•
•
•
•
Bipolar Drive Capability
Provides Advanced Commands
Tri-State Output Drivers
Can be used with an I/O Bus
Enables Interface to One or Two Multi-Master Buses
20-P in Package
PIN NAMES
PIN CONFIGURATION
lOB
VCC
ClK
SO
51
52
DT/R
MCE/PDEN
SO-S2
Status Input P,ns
ClK
Clock
ALE
Address latch Enable
DEN
Data Enable
DTtR
Data Transmit/Receive
ALE
DEN
AEN
Address Enable
AEN
CEN
CEN
Command Enable
MRDC
iN-i'A
lOB
I/O Bus Mode
AMWC
IoRc
AIOWC
Advanced I/O Write
MwTC
AiOWc
GND
TM - Multibus is a trademark of Intel Corp.
10WC
REVI1
6-275
10WC
I/O Write Command
iORC
I/O Read Command
lJloWr;
Advanced Memory Write
MWTC
Memory Write Command
MRDC
Memory Read Command
INTA
Interrupt Acknowledge
MCE/PDEN
Master Cascade/Peripheral
Data Enable
IlPB8288
PIN IDENTIFICATION
PIN
NO.
SYMBOL
FUNCTION
NAME
1
lOB
I/O Bus Mode
Sets mode of IlPB8288, high for the I/O
bus mode and low for the system
bus mode.
2
ClK
Clock
SO, Sl, S2
Status Input Pins
4
DT/R
Data Transmit/Receive
5
ALE
Address latch Enable
6
AEN
Address Enable
7
MRDC
Memory Read
Command
8
AMWC
Advanced Memory
Write Command
9
MWTC
Memory Write
Command
The cI ock signal from the IlPB8284
clock generator synchronizes the
generation of command and control
signals.
The IlPB8288 decodes these status
lines from the Il PB8086 to generate
command and control signals.When
not in use, these pins are high.
This signal is used to control the
bus transceivers in a system. A high
for writing to I/O or memory and
a low for reading data.
This signal is used for controlling
transparent D type latches (J.LPB8282/
8283). It will "strobe in the address
on a high to low transition.
In the I/O system bus mode, AEN
enables the command outputs of
the IlPB8288 105 ns after it becomes
active. If AEN is inactive, the
command outputs are tri-stated.
This active low signal is for switching the data from memory to the
data bus.
This is an advanced write command
which occurs early in the machine
cycle, with timing the same as the
read command.
This is the memory write command
to transfer data bus to memory, but
not as early as AiiiiWC:. (See timing
waveforms. )
11
10WC
I/O Write Command
12
AIOWC
13
10RC
Advanced I/O Write
Command
I/O Read Command
14
INTA
Interrupt Acknowledge
15
CEN
Command Enable
16
DEN
Data Enable
17
MCE/
PDEN
Master Cascade Enable
Peripheral Data Enable
3,19,18
This command is for transferring
information to I/O devices.
This write command occurs earlier
in the machine ~cle than TOWC:
This signal enables the CPU to
read data from an I/O device.
This is to signal an interupting device to put the vector
information on the data bus
This signal enables all command
and control outputs. If CEN is low,
these outputs are inactive.
This signal enables the data transceivers onto the bus.
Dual function pin system.
MC/E - In the bus mode, this
signal is active during an interru pt sequence to read the cascade
address from the master interrupt
controller onto the data bus.
l'Dm - In the I/O bus mode,
it enables the transceivers for the
I/O bus just as DEN enables bus
transceivers in the system bus
mode.
6-276
,..P88288
BLOCK DIAGRAM
8086
STATUS
I
so
-
STATUS
DECODER
~
·2
MWTC
COM·
MAND
AMWc
l'ORC
i'5WC
AiOWC
iNTA
!l1f5Cl
SIGNAL
GENERA·
TOR
( eLK
CONTROL' AEN
INPUT) CEN
CONTROL
LOGIC
CONTROL
SIGNAL
GENERA·
TOR
+5V
GND
~ lOB
DT/R
DEN
MCE/P'De'N
ALE
MULTIBUsTM
COMMAND
SIGNALS
1
ADDRESS LATCH. DATA
TRANSCEIVER, ANO
INTERRUPT CONTROL
SIGNALS
CONNECTING THE BUS CONTROLLER TO THE CPU
I"
jJPBB284
Ls
10
ClK
I
ClK
1
26
80
"
RE;AJLY
22
~T
_21
~
7
3
80
2"
18
52
1
.PDS0861
8088
CPU
MN/MX
~33
ABSOLUTE MAXIMUM
RATlNGS*
OPERATING TEMPERATURE ..
Storage Temperature . . . . . . . . . .
All Output and Supply Voltages
VIL
VIH
Vc
Input High VOltage
=
(SYSBIRESB
Low + TI) CBRQ +
HLT + HPBRQ
(Memory
lOB Mode· lOB = Low
RESB Mode RESB = High Command) •
(SYSB/RESB
High)
=
Svon_1
Input Low Voltage
(I/O Status + TI) •
CBRQ + HLT +
HPBRQ
Memory
lOB
Low
RESB
Low Commands
Per.met.r
HLT + TI • HPBROt
=
=
lOB Mode
Only
-
5V :t1O%
'_a
Surrendered @
92.5Q
250 pF
'--r ·
170Q
1
60PF
6-286
,
Min
Typ
2)AEN
T••t Condition.
I:'::Q
~
I
100PF
",P88289
Typical CPU System Using
the lAP B8289 Bus
Arblter
rlDh
READY
RDYI
8284A
Clock
Driver
"ANYRQT
AEiiff
Cll<
KHi
Bu.
Arbit.r
READY
XACK
bJVCC
ClK
ClK
or
"Control
-y
~
8086
r
8289
Bus
AEN RESB~
+----1
8088
CPU
81atu8
(So. §1. S2)~
I
AEN
Bus
Controller
--/ ClK
ADO-ADI5
A16-A19
ALE
/
Processor
Local Bus
l
STB
OE
lOB
DTiR
~
Addre59
Bus
82821
8283
~
-V
XC
DIS
•
T
OE
Transceiver
""
Command
Bus
I
Addr...
Latch
)
--/
DEN
"-
8288
82861
8287
r
"'-
6-287
Oat• Bus
~PB8289
AEN1
8284A
Clock
XACK (110 B u s ) - - - - - - - - - - - i R D Y 1
R D Y 2 ! - - - - - - - - - - - - - - - - - - X A C K MUlti-master
System Bus
MUlti-master
Control
Bus
8089
lOP
Multi-master
System Bus
I/O Bus
Multi-master
System
Command
10
Command
Bus
vee
82831
Multi-master
System
Address
8282
10
Address
Bus
Address
Latch
Address
Latch
(2 OR 3)
(2 OR 3)
OE
Bus
T
8286/8287
8286/8287
Data
Transceiver
Transceiver
Bus
(2)
(2)
10
Bus
TYPICAL lOB Sy.tem
6-288
MUlti-master
System
Data
Bus
",PB8289
D
AEN2
AENlp---------,
8284A
Clock
:~:.nl BUS·-----------!RDY2
R D Y 1 i - - - - - - - - - - f - - - - - - - - - - X A C K Mull"-masler
System Bus
Mulll·m....r Syalem
Bus Conlrol
I-t---vcc
Mul....m..ter
Syst.m Bus
Resldenl Bus
R.sld.nt COmmand
Bus
Muhl·rnaster Syatem
COmm.nd Bus
Prom
OR
Decoder
828218283
Acldreu
Resldenl Address
aus
Lat.~
Multl·m....r System
Add.... Bus
(2 OR 3)
828818287
Transceiver
(2)
Rnldenl Dala
Bus
• By .ddlng another 8289 arbiter .nd connecting 118 AEN 10 Ihe 8288 who •• AEN Is pre_nty groundacl,
lhe processor could h.v••cce.. 10 twa muhl-m....r buses.
6-289
MulU-mUler Syat8m
Date aus
~PB8289
AC Characteristics
Timing Requirements
Ta
O°Cto +70°C; vcc
=
AC Test Condition Waveform
InputfOutput
5V
± 10%
:4~=X5_-Test POInIS--'~
LImits
Symbol
MIn
elK Cycle Period
tClCL
125
elK Low Time
teLcH
65
elK High Time
tCHCL
35
Status Active
Setup
tSVCH
65
ICLCl-1O
Status Inactive
Setup
tCLCl-10
Parameter
tSHCL
50
Status Active
Hold
tHVCH
10
Status Inactive
Hold
tHVCL
10
ISYSBL
20
tcasBL
20
BUSYN Setup to
BCLK~
CBRON Setup to
BCLK~
BCLK Cycle Time
tSLBL
BClK High Time
tSHCL
30
LOCK Inactive
Hold
tClLL1
10
LOCK Active
Setup
tCLLL2
40
SPRNn to BCLK
Setup Time
tpNBL
15
SVSBfRESB Setup
tCLSR1
SYSB/AESB Hold
tCLSR2
Imtlalization Pulse
tlVIH
Width
Ma.
TVp
Unit
Test Conditions
AC Testing Inputs are driven at 2.4V for LOGIC 1 and O.45V for LOGIC o. The clock IS
driven at 4.3V and 0.25 Timing measurements are made at 1.5V for lOGIC 1 and O.
ns
Timing Waveforms
ns
100
065 (lBLBL)
ns
ns
20
ns
3 tSLBL +
3 tCLCL
Input Rise Time
IILlH
20
ns
From O.SV to 2.0V
Input Fall Time
tlHIL
12
ns
From 2 OV to O.SV
Timing Responses
limits
Max
Parameter
Symbol
BCLK to BREa
Delay CD
tBLBAL
35
BCLK to BPAO
tBLPOH
40
C!J®
MIn
TVp
BPANH to BPAoa tPNPO
Delay CD ®
25
BCLKto BUSY
Low
tSLBYL
60
BCLK to BUSY
Float @
Unit Te.t Conditions
ns
tBLBYH
35
eLK to AEN High
tCLAEH
65
BCLK to AEN Low
tBLAEL
40
BCLKto CBAa
Low
tBLCBL
60
BCLK to CBAa
Float @
tRLCAH
35
Output Rise Time
tOLOH
20
From O.8V to 2.0V
Output Fall Time
'0HOL
12
From 2.0V 10 O.8V
The signals related to ClK are typical processor signals
and do not relate to the depicted sequence of events of
the signals referenced to BClK. The signals shown
related to the BClK represent a hypothetical sequence
of events for illustration. Assume three bus arbiters of
priorities 1, 2, and 3 configured in the serial priority
resolving scheme. Assume arbiter 1 has the bus and is
holding BUSY low. Arbiter 2 detects its processor wants
the bus and pulls BREQ #2 low. If BPRN #2 is high (as
shown), arbiter 2 pulls CBRQ low. CBRQ signals to
higher priority arbiter 1 that a lower priority arbiter
wants the bus. A higher priority arbiter would be given
BPRN when it makes the bus request rather than having
to wait for another arbiter to release the bus through
CBRQ. Arbiter 1 relinquishes the multimaster system
bus when it enters a state of not requiring it, by lowering its BPRO #1 (tied to BPRN #2) and releasing BUSY.
Arbiter 2 now sees that it has priority from BPRN #2
being low and releases CBRQ. As soon as BUSY signifies the bus is available (high), arbiter 2 pulls BUSY low
on the next falling edge of BClK. Note that if arbiter 2
didn't want the bus at the time it received priority, it
would pass priority to the next lower priority by lowering
its BPRO #2 (TPNPO). Note also that even a higher
priority aribiter which is acquiring the bus through
BPRN will momentarily drop CBRQ until it has acquired
the bus.
ns
Notesl
(j) Denotes that the spec applies to both transitions of
the signal.
@ BCLK generates the first BPRD. Subsequent changes of BPRD
are generated through BPRDN
@ Measured at O.5V above GND
6-290
~PD8289
Timing Waveforms
STATE ------T4--------t------
------~~------T2~----_r~----T3------~-------T4
.,------!---'ClCH
ClK
'HVCH
tClll1
tCLL2
lOCK
SYSB/RESB
tClSR1---
tCLSR2
AEN
Processor elK Related
Bus elK Related
tBHCL
IBLBRL
BREa #2
SPRN If2
(BPRO #1)
BPRO #2
(BPRN #3)
ISYSBl
IBLeSL
!-
ISLBYL
tSLBYH
tBLCBH
6-291
J.(PD8289
Package Outlines
For information, .ee Package Outline Section 7.
Cerdip, fLPB8289D
8289DS·REV1·7-83-TRIUM..cAT
6-292
NEe
/JPD8355
/JPD8355·2
/JPD8755A*
16,384-BIT ROM WITH I/O PORTS
*16,384-BIT EPROM WITH I/O PORTS
DESCR IPTION
F EA TU R ES
The IlPD8355 and the IlPD8755A are IlPD8085A Family components. The IlPD8355
contains 2048 x 8 bits of mask ROM and the IlPD8755A contains 2048 x 8 bits of
mask EPROM for program development. Both components also contain two general
purpose 8·bit I/O ports. They are housed In 40 Pin packages, are designed to directly
interface to the IlPD8085A, and are pln·for,pln compatible with each other.
• 2048 X 8 Bits Mask ROM (IlPD8355 and IlPD8355·2)
•
•
•
•
•
•
•
•
PIN CONFIGURATIONS
2048 X 8 Bits Mask EPROM (IlPD8755A)
2 Programmable I/O Ports
Single Power Supplies: +5V
Directly Interfaces to the IlPD8085A
Pin for Pin Compatible
IlPD8755A: UV Erasable and Electrically Programmable
IlPD8335 and IlPD8355·2 Available in Plastic Package
J..LPD8755A Available in Ceramic Package
CE
CE
ClK
RESET
NC
READY
IO/iiii
lOR
RD
lOW
ALE
ADO
ADl
AD2
AD3
AD4
AD5
ADS
AD7
Vss
IlPD
8355/
8355-2
NC: Not Connected
Rev/2
6-293
VCC
PB7
PBS
PB5
PB4
PB3
PB2
PBl
PBo
PA7
PAS
PA5
PA4
PA3
PA2
PAl
PAo
AlO
Ag
AS
CE
CE
ClK
RESET
VDD
READY
101M
lOR
RD
lOW
ALE
ADO
ADl
AD2
AD3
AD4
AD5
ADS
AD7
Vss
IlPD
8755A
VCC
PB7
PBS
PB5
PB4
PB3
PB2
PBl
PBo
PA7
PAS
PA5
PA4
PA3
PA2
PAl
PAo
Ala
Ag
AS
m
I-lPD835518755A
The J.lPD8355 and J.lPD8755A contain 16,384 bits of mask ROM and EPROM
respectively, organized as 2048 X 8. The 2048 word memory location may be
selected anywhere within the 64K memory space by using the upper 5 bits of
address from the J.lPD8085A as a chip select.
FUNCTIONAL DESCRIPTION
The two general purpose I/O ports may be programmed input or output at any
time. Upon power up, they will be reset to the input mode.
VDDCD
vcc (+5V)
BLOCK DIAGRAM
S
AD7 . ADO
--+-
AlO' AS
D
D
READY
CE
IT
ALE
RD
lOW
lOR
ClK
loiM
RESET
PA7·PAO
S
S
Vss (OV)
Note
CD VDD applies to I'PDS755A only.
Operating Temperature (J.lPD8355) ......................... oOe to +70 o e
(J.lPD8755A) . . . . . . . . . . . . . . . . . . . . . . . oOe to +70 o e
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°e to +150 o e
Voltage on Any Pin (J.lPD8355) . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7V CD
(J.lPD8755A) . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7V CD
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.5W
Note:
CD
ABSOLUTE MAXIMUM
RATINGS*
With Respect to Ground
*COMMENT: Stress above those listed under "Absolute MaxImum Ratings" may cause permanent
damage to the device. Th,s is a stress rating only and functIonal operation of the device at these or
any other conditIOns above those indicated In the operational sections of this speCIfication IS not
Implied. Exposure to absolute maximum rating conditions for extended periods may affect deVice
reliability.
Ta
= O°C to +70°C; VCC = 5V
DC CHARACTERISTICS
± 5%
LIMITS
PARAMETER
SYMBOL
MIN
Input Low Voltage
VIL
-0.5
Input High Voltage
VIH
2.0
Output Low Voltage
VOL
MAX
TEST
CONOITIONS
UNIT
= 5.0V CD
= 5.ov·CD
IOL = 2 rnA
IOH = -400 I'A
VIN = VCC to OV
0.8
V
Vee
VCC+0.5
V
Vec
0.45
2.4
V
Output High Voltage
VOH
Input Leakage
IlL
V
Output Leakage Current
ILO
±10
IJA
0.45V "VOUT "Vcc
Vee Supply Current
lee
180/125
rnA
IJPD8355/8355-2
10
IJA
Note: CD These conditions apply to J.lPD8355/J.lPD8355-2 only.
6-294
lAP D8355/8755A
PIN IDENTIFICATION
NO.
PIN
SYMBOL
1,2
CE, CE
Chip Enables
Enable Chip activity for
memory or I/O
NAME
FUNCTION
3
ClK
Clock Input
Used to Synchronize Ready
4
Reset
Reset Input
Resets PA and PB to all inputs
5Q)
NC
Not Con nected
5CV
VDD
Programming
Voltage
Used as a programming voltage,
tied to +5V normally
6
Ready
Ready 0 utput
A tri·state output which is
active during data direction
register loading
7
10/M
I/O or Memory
Indicator
An input signal which is used
to indicate I/O or memory
activity
8
lOR
I/O Read
I/O Read Strobe In
9
RD
Memory Read
Memory Read Strobe In
10
lOW
I/O Write
I/O Write Strobe In
11
ALE
Address low
Enable
Indicates information on
Address/Data lines is valid
12·19
ADO·AD7
low Address/Data
Bus
Multi plexed Low Address and
Data Bus
20
VSS
Ground
Ground Reference
21·23
A8·A 1Q
High Address
High Address inputs for ROM
reading
24·31
PAO·PA7
Port A
General Purpose I/O Port
32·39
PBO·PB7
Port B
General Purpose I/O Port
40
VCC
5V Input
Power Supply
Notes: Q) pPD8355
~ pPD8755A
I/O PORTS
I/O port activity IS controlled by performing I/O reads and writes to selected I/O port
numbers. Any activity to and from the pPD8355 requires the chip enables to be active.
This can be accomplished with no external decoding for multiple devices by utilizing
the upper address lines for chip selects. Q) Port activity is controlled by the following
I/O addresses:
AD,
ADO
0
0
PORT SELECTED
0
1
B
Read or Write PB
1
0
A
Write PA Data Direction
1
1
B
Write PB Data Direction
A
FUNCTION
Read or Write PA
Since the data direction registerlS for PA and PB are each 8·bits, any pin on PA or PB
may be programmed as input o~ output (0 = in, 1 = out).
Note:
CD During ALE time the data/address lines are duplicated on A15·A8.
6-295
~PD8355/8755A
Ta'" O°C
to
70°C VCC- 5V
+
5%
8355
Symbol
Moo
Parameter
320
Clock Cycle Time
teYe
8355·2
Max.
Mm.
Mox
Unit
Test
CondItIons
AC CHARACTERISTICS
200
elK Pulse Width
80
40
T,
r-~---+~~~-------------------r~--r----+~~-r----+---~CLOAD=150pF
elK Pulse Width
120
70
T2
If,t r
elK Rise and Fal! Time
tAL
Address to Latch Set Up Time
tlA
Address Hold Time after Latch
tle
latch to READ/WA ITE Control
tAD
Valid Data Out Dealy from READ Control
170
tAD
Address Stable to Data Out Valid
400
tll
Latch Enable Width
tRDF
Data Bus Float after READ
30
30
50
30
80
30
100
40
'40
330
70
'00
85
'00
READ/WAITE Control to Latch Enable
20
tel
'A
f-=--+---'o:":::===-=-=.:..,:=-====--+:::=-i-----f--:-:c-+----t--"'----1150
Load
READ/WRITE Control Width
250
200
tee
pt-
150
Data
In
to Write Set Up Time
two
Data
In
Hold Time After WR ITE
twp
WRITE to Port Output
tpA
Port Input Set Up Time
50
50
tow
150
10
10
400
400
50
tAP
Port Input Hold Time
tRYH
READY HOLD Time
160
'60
tARY
ADDRESS (CE) to READY
160
160
tAV
Recovery Time Between Controls
tAOE
READ Control to Data Bus Enable
Notes
50
300
200
10
10
30 ns for IJPDB755A
CLOAD'" 150 pF
ROM READ, I/O READ AND WRITE
elK
,tCY/~--"-i\'-
CD
__...JIr---rT'=fT2L
AS-l0-'r.-----------------------------.
10/M_-'-~========~~=========;~--------------------'~-ADO_7 __
J~
__________
~
PROM READ, I/O READ AND WRITE ~
ADDRESS
Aa-10
...J-f-_____"'i
ADO.7 _ _
r-_...J"f-__D_A_T_A_ _ _-'r ---..(
ALE
CE
Notes:
G) I'PD8355
@
®
tcc
I'PD8755A
CE must remain low for the entire cycle
6-296
ADDRESS }-
TIMING WAVEFORMS
JJPD8355/8755A
TIMING WAVEFORMS
(CONT.)
CLOCK
If
WAIT STATE TIMING (READY = 0)
elK
ICE = 1).
fCE = 0)
ALE
1/0 PORT
INPUT MODE,
~~:~~ \-'M~ t~'RP
INPUT~
~
QATA----- - - ' "
BUS _ _ _ _ _ _ _
..1\__________
OUTPUT ".ODE'
\ . . .----.-WP--1
l':L' GL~~CT~~~E~
PORT - - - - - - - - - - - - ~
OUTPUT,_ _ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ __
~
OATA------V
X
BUS _ _ _ _ _ _ ../'\_ _ _ _ _ _..1.
EPROM PROGRAMMING
IlPD8755A
'-._ _ __
Erasure of the IlPD8755A occurs when exposed to ultraviolet light sources of wave·
lengths less than 4000 A. It is recommended, if the device is exposed to room
fluorescent lighting or direct sunlight, that opaque labels be placed over the window to
prevent exposure. To erase, expose the device to ultraviolet light at 2537 A at a
minimum of 15 W·sec/cm 2 (intensity X expose ~ime). After erasure, all bits are in the
logic 1 state. Logic O's must be selectively programmed into the desired locations. It
is recommended that NEC's PROM programmer be used for this application,
6-297
I4PD8355/8755A
Package Outlines
For Information, ••e Package Outline Section 7.
Plastic, f,CPD8355HC/8755AC
Ceramic, f,CPD8355D
Ceramic, f,CPD8355HD
Ceramic, f,CPD8755AD
Cerdip, f,CPD8755AD, has quartz window
8355/8355-218755AD5-REV2-7-83-CAT
6-298
NEe
PACKAGE OUTLINES
IJ
PACKAGE OUTLINES
All packaging information is contained in this Package Outlines section. Specifications and dimensions for every
package are shown together with a list of the products available in each. Additions, changes, and updates will be
incorporated in succeeding editions of the catalog.
Item
MIllimeter.
A
19.4 max
Inchea
0.76 max
0.03
B
0.81
C
2.54
0.10
0
0.5
002
17.78
0.70
1.3
G
2.54 min
a.10ml"
H
0.5 min
002 min
K
II
4.05 max
0.16 max
4.55 max
018 max
7.62
0.30
6.4
025
+010
0.25 -0.05
0.01
Item
Millimeter.
A
19.9 max
1.06
0.042
2.54
0.10
0.46 ± 0.10
0.018 ± 0.004
17.78
0.70
1.5
0.059
G
2.54 min
a.10ml"
H
a.Sml"
0.019 min
K
4.58 max
0.181 max
5.08 max
0.20 max
II
7.62
0.30
6.4
0.25
025
+0.10
0.0098
-0.05
Item
Mlillme.er.
A
23.2 max
B
1.44
I'
Ir-Li
'I
A
fLPB8216D/26D
~K;;]
,~J.I
r
B~ jc~,l
-i~1I
0-15'
)
~
+0.0039
18PIN
Plastic
Inch••
0.91 max
0.055
2.54
0.1
0
0.45
0.02
E
20.32
0.8
1.5
0.059
G
2.5ml"
0.1 min
H
OSmin
0.02 min
II
Cerdip
-0.0019
C
K
1~~L~'~1 '
Inch ••
B
0
fLPB8216C/26C
'I
-A
0.784 max
C
E
f:,
=fMWiJ -I~. ,-J \.I'
0.051
16PIN
Plastic
4.6 max
0.18 max
5.1 max
O.2max
7.62
0.3
6.7
0.26
0.25
0.01
fLPD8284AC
I'
,
~, f~~
·
JW!~ ~~, .,1
7-1
II
PAC
_
~~~~~~~"""""""""""""""""""~"~~~~~~~~~~ln~C~h~
.~
. a._ ~ •.~
WAGE OUTLI N ·
~
18 PIN (Con.
t I
_D
Cer IP
8
_
,
}" : l I_"~,!,
A
-..if--.M
I
'I
J ~B~-IE ~'.I~r
0.15"
G
I\-
;..
.
: ::: ::
•
'M
20.32
0.45
.
"
0.06
:;.~. ~
4.6 max
0.2 max
_
;6.7
M
20 PIN
Plastic
PB8282C/83C
~PB8286C/87C
0.25
Item
Mlilimete,.
A
28.7 max
B
1.05
0.041
C
2.54
0.1
D
0.5-0.1
0.02 -0.004
22.86
0.055
G
2.54 min
0.1 mm
H
O.5mm
0.02 min
M
PB8282D/83D
...PB8286D/87D
~PB8288D
A
1
... PB8289D
0.9
1.4
K
Cerdip
Inch••
1.05 max
3.55
0.14
5.08 max
02max
7.62
0.3
6.4
0.25
0.25 - 0.10
- 0.05
0.01 - 0.004
-0.002
It_
1IIIIIm.I...
A
21.7 max
8
0.7
0.028
C
2.&4
0.1
D
0.48 ± 0.1
0.018 ± 0.004
E
22.88
F
1.4
G
H
2.54 min
0.9
0.055
0.1 min
0.02 min
0.5 min
4.32m8x
0.17 max
5.08ma.
0.2m8x
7.82
0.3
0.27
!L=----~8.8~n:10___::
-K
M
24 PIN
Item
Plastic
... PB8212C
PD8243C
... PD82C43C
~PD8253C-5
A
'I
~'
~~t'
I
_ 0.10
0.05
0.25 +
Mlllllllete,.
Inch••
A
33ma.
a
c
2.63
0.1
2.54
0.1
D
1.3mBX
-~:::"::-:--'0.02
± 0.004
0.5 ± 0.1
E
27.94
F
1.5
0.059
G
2.54ml"
0.1 min
H
0.5 min
0.02 min
I
5.22m8x
0.205m8x
S.72mu
0.225 max
J
K
1.1
15.24
0.6
13.2
0.52
+ 0.10
M _ _ _0_.25_-__
_
0•05
7-2
ft. + 0.004
0.01 _ 0.002
+ 0.004
0.01 _ 0.0019
Item
Millimeter.
A
30.78 max
Inche.
1.21 max
B
1.53 max
0.06 max
c
2.54:t 0.1
0.10 ± 0.004
D
0.46 ± 0.8
0.018 ± 0.03
27.94 ± 0.1
1.02 min
1.10 ± 0.004
0.04 min
G
3.2 min
0.13 min
H
1.02 min
0.04 min
K
M
3.23 max
0.13 max
4.25 max
0.17 max
15.241yp
0.601yp
14.93'yp
0.591yp
0.25 ± 0.05
0.010 ± 0.002
Item
Millimeter.
Inche.
A
33.5 max
1.32 max
B
2.78
0.11
c
2.54
0.1
D
0.46
0.018
27.94
G
fJ.PD8243D
fJ.PD8253D-5
Cerdip
fJ.PB8212D
fJ.PD8243D
fJ.PD82C43D
fJ.PD8253D-5
1.1
1.5
0.059
2.54 min
0.1 min
_-'H"-_ _-=0.5=-m:.:cl:.:cn_ _~0.019 min
K
4.58 max
0.181 max
5.08 max
0.2 max
0.6
15.24
0.53
13.5
M
+ 0.10
0.25
0.01
- 0.05
Item
Millimeter.
A
33 max
B
2.53
c
2.54
D
0.5
E
27.94
+ 0.004
- 0.002
1.3 max
0.1
fJ.PD82C43CX
0.1
±
0.1
0.02 ± 0.004
1.1
1.5
0.059
G
2.54 min
0.1 min
H
0.5 min
0.02 min
K
5.22 max
0.205 max
5.72 max
0.225 max
7.62
0.30
6.4
M
0.25
Plastic
Skinnydip
Inche.
0.25
+ 0.10
0.01
- 0.05
+ 0.004
- 0.0019
------------------------------------------------------28
PIN
Plastic
Item
Mlllimete,.
A
38.0 max
Inche.
1.496 max
B
2.49
0.098
C
2.54
0.10
13.2
M
0.25
fJ.COM-4C
fJ.PD557LC
fJ.PD550C/554C
fJ.PD550LC/554LC
fJ.PD7506C
fJ.PD7507SC
fJ.PD7520C
fJ.PD8021C
fJ.PD8251ACI AFC
fJ.PD8259AC
0.52
+ 0.10
- 0.05
0.01
+ 0.004
- 0.002
7-3
PACKAGE OUTLINES
28 PIN ( C o n t . ) - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Ceramic
fJ.PDn20D
fJ.PDnp20D'
fJ.PD8251AD/AFD
'has quartz window
Item
IIlIIimete,.
A
36.2 max
Inch••
1.43 max
B
1.59 max
0.06 max
c
2.54 ± 0.1
0.1 ± 0.004
0.46 ± 0.01
0.02 ± 0.004
D
33.02 ± 0.1
1.3 ± 0.004
1.02 min
0.04 min
G
3.2 min
0.13 min
H
1.0 min
0.04
3.5 max
O.14m.x
4.5 max
0.18 max
min
_-=.:.K_ _ _l;;.;5'c;:.24;.cI.,.,yp_ _ _
0.6IYP
14.93 Iyp
II
Cerdip
Item
A
fJ.PDS021D
fJ.PD8251AD/AFD
fJ.PD8259AD
37.7 max
2.78
1.1
2.54
0.1
0.46 ± 0.10
0.018 ± 0.004
27.94
1.10
1.3
0.05
G
2.54 min
0.1 min
H
0.5 min
0.020
5.0 max
0.20
5.5 max
0.216
K
15.24
L
14.66
0.60
0.58
0.25 ± 0.05
Millimeter.
Inch••
A
15.85m""
.828 max
c
1.778
.07
D
0.5
.02
E
24.89
.98
F
1.1
.043
G
2.54
H
.1
.51 min
5.08m.x
15.24
~
j..-
fJ.PD8155C/56C
fJ.PD8237C-5
fJ.PD8255AC-5
fJ.PD8257C-5
IbPD8279C-5
fJ.PD8355HC/8755AC
F
--jC~E
~~D
~K~
f
.1
_.
7-4
.2m.x
.52
+ 0.10
- 0.05
.01
+ .004
- .002
G
1.2 min
2.54 min
0.047 min
0.10 min
H
0.5 min
0.018 min
5.22 max
0.206 max
F
lv==L ==\j~I
. .
0.25
.02 min
.600
13.2
II
B
0.010 ± 0.002
Item
K
fJ.PD7507C/OSC
fJ.PD7508AC
fJ.PD7508HC
fJ.PD8041AC
fJ.PD8048HC/35HLC
fJ.PDSOC35C/C48C
fJ.PD8049HC/39HLC
fJ.PD80C49C/C39C
fJ.PD78OC
fJ.PD8085AC/AHC
fJ.PD765AC/7265C
fJ.PD7201AC
fJ.PD7210C
fJ.PDn51C
Inch••
1.48 max
c
II
fJ.PD7506CT
fJ.PD7520CT
fJ.PD7507SCT
fJ.PD554CT
fJ.PD550CT
fJ.PD557LCT
Millimeter. "
0.591yp
0.01 ± 0.002
B
,D
Plastic
Shrinkdip
0.25 ± 0.05
5.72 max
K
15.24 lyp
0.225 ma.
0.600 Iyp
PACKAGE OUTLINES
- - - - - - - - - - - - - - - - - - - - - - - - - 4 0 PIN (Cont.)
Item
Millimeter.
Inch ••
Ceramic
A
51.5
max
2.03 max
S
1.62 max
0.06 max
C
2.54 ± 0.1
0.1 ± 0.004
0
0.5 ± 0.1
0.02
E
48.26 ± 0.1
1.9 ± 0.004
G
H
K
M
Item
1.02 min
0.04 min
a.13m!n
1.0 min
0.04 min
3.5 max
0.14 max
4.5 max
0.18 max
15.24 typ
0.6typ
14.93 typ
0.59 IYP
0.25 ± 0.05
S
13.2
E
0.01 ± 0.0019
Millimeter.
53.34
0
0.004
3.2 min
A
C
::t
max
±
0.25
0.5 ± 0.1
48.56
.1 ± .01
.002 ± .004
1.91
1.3
0.51 min
.02 min
H
7.62
.3
K
15.24
.051
5.08 max
.2mBX
.6
0.25 ± 0.05
Millimeter.
max
.01 ± .002
Inch ••
A
39
c
o
1.778
.07
0.5
.02
E
G
H
35.56
HTT
.043
.1
15.24
.2 max
.52
+0.10
+.004
.01
- 0.05
s~ ~
- .002
TT
I J
U III
~ ~F
---jc~
~~D
.02 min
.600
0.25
'1
A
L
2.54
.51 min
I'
max
1.1
13.2
M
1.54
1.4
5.08 max
K
fJ.PDBOB6D
fJ.PDBOBBD
fJ.PDBOBSAD
fJ.PDB237D-5
fJ.PDBOB5AHD
fJ.PDB741AD*
fJ.PDB74BD*
fJ.PDB749HD*
fJ.PDB75SAD*
'has quartz window
.52
2.54
F
Item
Cerdip
Inch ••
2.1 max
G
M
fJ.PDB041AD
fJ.PDB04BHD/35HLD
fJ.PDB!lC35D/C4BD
fJ.PDB049HD/39HLD
fJ.PD7BOD
fJ.PDBOB5AD
fJ.PD765AD/7265D
fJ.PD7201AD
fJ.P0 7210D
fJ.PD7220D
fJ.PD7261D
fJ.PDB237D-S
fJ.PDB25SAD-5
fJ.PDB279D-5 fJ.PDB755AD
fJ.PDB155D/56D
fJ.PDB355D
fJ.PDB355HD fJ.PDB257D-5
f~1
--I/-M
7-5
J
\'-0-15'
.1
ih
Plastic
Shrinkdip
f1PD7S07CU
fJ.PD7508CU
fJ.PD750BACU
fJ.PD7507HCU
fJ.PD750BHCU
fJ.PDBOC48CU
fJ.PDBOC49HCU
Item
~-------------A--------------~
Ceramic·
Piggyback
A
53.34 max
B
20.32
c
o
fL PD75CGOllE
E
2.1 max
.8
2.54 ± 0.25
.1 ± .01
0.46 ± 0.05
.018 ± .002
1.9
48.26
1.02
.04
G
3.2 min
.126 min
H
1.02 min
.04 min
3.0 max
.118 max
4.32 max
K
M
N
o
.170 max
15.24
.6
15.24
.6
0.25 ± 0.05
33.02
.01 ± .002
1.3
2.54 ± 0.25
.1 ± .01
42PIN------------------------------------------------------
Plastic
fLCOM-4C
fLPD552C/553C
fLPD7527C/28C/37C/38C
Inches
Item
Millimeters
A
56.0 max
2.2 max
B
2.6 max
0.1 max
c
2.54
0.1
o
0.5 ± 0.1
0.02 ± 0.004
E
50,8
2.0
1.5
0.059
G
3.2 min
0.126 min
H
a.Smln
0.02 min
5.22 max
0.20
5.72 max
0.22 max
K
15.24
0.6
13.2
0.52
M
0.3 ± 0.1
Item
MIUimater.
A
56.5 max
B
27.94 ± 0.5
max
0.01 ± 0.004
Cerdip
MC-430PD
r-
I
A
000000000000
11
0 OD~J 11
,000000000000
!L
1~2M
i
~K~
l
I
N
,'lrffi Frr
F
E
2.54
0
0.5
f-c
+-D
E
G
H
50.8
.02
- .004
.05
2.54 min
0.1 min
1.5 ± 0.3
.059 ± .012
1.0 min
.039 min
15.24
.256 max
0.6
.039
L
M
+ .01
2.0
6.5 max
0.35
+ 0.25
.014
- 0.1
+ .01
- .004
N
1.6
0
2.54 ± 0.3
P
2.0
.079
Q
1.74 ± 0.25
.685 ± .01
R
7-6
+ 0.25
1.27
G
K
.1
1.1 ± .02
0.1
- 0.1
l-:I-~~-B ~ ~P .1 ~H
'~ VVV~V~1i V T I ~ Ii VIi v:S1
I~
1
C
Inch••
2.24 max
21.0 max
.063
0.1 ± .012
.827 max
PACKAGE OUTLINES
42 PIN (Cont.)
Item
Millimeter.
A
55.88 max
B
20.32
C
o
----
Inch••
2.2 max
.80
2.5 ± 0.25
.1 ± .01
0.46 ± 0.05
.018 ± .002
--"
50.80
.04
G
3.2m!n
.126 min
H
1.02 min
.04 min
3.0 max
.118 max
4.32 max
.17 max
K
M
15.24
.6
15.24
.6
0.25 ± 0.05
N
33.02
0
2.54
c
o
±
0.25
40.95 max
1.778
K
M
00000000000000
1
.1 ± .01
Plastic
Shrinkdip
Inches
1.612 max
.07
.02
37.34
1.47
fLPD7527CUl28CUI
37CU/38CU
.043
2.54
.1
.51 min
.02 min
5.08 max
.2 max
H
fLPD75CG28E/CG38E
B
.001 + .01
0.5
1.1
G
C
1
Ceramic
Piggyback
1.3
Millimeter.
A
'I
00000000000000
)
2.0
1.02
I'
A
15.24
.600
13.2
.52
+ .004
+ 0.10
0.25
.01
- 0.50
- .002
_____________________________________________________ 44 PIN
Item
A
B
Millimeter.
1.36 ± 0.4
10
+ .3
Inches
.054
.394
- .2
c
o
0.8 ± 0.2
.35
+ 0.3
- 0.1
fLPD80C49G
fLPD80C48G
+ .01
.014
- .004
.315 ± .012
1.0 ± 0.2
.39 :t: .008
+ .004
.006
- 0.005
H
- .008
8.0 ± 0.3
0.15
Plastic
Miniflat
.016
.03 ± .008
+ 0.10
G
+
+ .012
- .0002
0.0 ± 0.1
0.0 ± .004
1.5 max
.059 max
~RDDRDDRRRRD~~
G
7-7
H
PAcKAGE OUTLINES
52~N--------~--------~----------------------~--------
fIT
r~i
Plastic
Miniflat
'
-r-
,,"COM-4G
,,"PD7506G
,,"PD7507G/08G
A
B
C
MiIIl...ter.
14
12.0 ± 0.3
1.0 ± 0.15
+ 0.2
0.4
- 0.1
Inch••
.55
.472 ± .012
.039 ± .006
+ .008
.016
- .004
l' [ , ,,.- --
--L.-
0
~I
,,"PD80C49G/C39G
,,"PD80C48G/C35G
,,"PD7225G
H....
C
---.Lot
_I :~1
~
+ 0.10
_ 0.05
0.15
G
2.2 ± 0.2
.087 ± .008
0.1m..
.004m••
H
20.6 ± 0.4
2.8 max
I---- ----I
.006
+ .004
F
_ .002
.811 ± .016
.110 max
64PIN--------------------------__________________________
Ite...
Plastic
QUIL
A
,,"PD7500G Evaluation
~
Chip
,,"PD7800G
,,"PD7801G/02G
,,"PD7810G/11G
,,"PD7519G
,,"PD78COSG
,,"PD7807G/09G
Millimeter.
41.5
B
1.05 ± 0.2
C
2.54
0.5 ± 0.1
.02 ± .004
E
39.4 ± 0.3
1.55 ± .012
K
1.27 ± 0.25
.05 ± .01
3.6
.142
24.13
.95
19.05
.75
.85
16.5
M
Ceramic
.01
- 0.05
+ .004
- .002
N
23.1 - 25.2
.909 - .99
18.0 - 20.1
.709 - .781
A
MUII.e,."
41.5
Ino....
1.634 max
B
1.05
0.042
C
2.54
0.1
o
0.5 ± 0.1
0.2 ± 0.004
E
39.4
1.55
F
1.27
G
5.4 min
0.21 min
2.35mex
0.13.,..x
A
0.05
24.13
0.95
K
19.05
0.75
L
15.9
0.826
M
7-8
.25
+ 0.10
o
It....
,,"PD5568
.041 ± .008
0.1
o
A
QUIL
Inch••
1.83
0.25 ± 0.05
0.01 ± 0.002
PACKAGE OUTLINES
Item
MIIII.,.ete,.
A
42.0 max
1.65 max
26.67
1.05
c
B
0
2.54 ± 0.25
0.1 ± .01
0.46 ± 0.05
0.018 ± .002
38.10
H
1.02mln
.04 min
.154
max
3.2 min
33.02
N
M
0.25 ± 0.05
.175 max
.126ml"
0.1
:t
.01
.01 ± .002
°
15.24
.6
p
19.05
.75
Q
24.13
.95
C 1
~I'
~M~
A
Millimeters
581yp
1.778typ
o
0.5 typ
0.043 typ
.159typ
3.95 typ
0.156 typ
19.05 typ
0.75 typ
Millimeter.
14
.,.PD7519CW
.,.PD7519HCW
.,.PD7801CW
.,.PD7802CW
.,.PD7810CW/11CW
.,.PD7809CW/07CW
Inch••
.551
B
12 ± 0.3
.472
±
.012
18.0 ± 0.3
.709
±
.012
0
20
.787
1.0 ± 0.15
0.4
fIT
B A
.039 ± .006
+0.2
III
+.008
.016
-0.1
24.7 ± 0.4
-.004
.972 ± .016
+0.10
0.15
+.004
.006
-0.05
0.2
2.35 ± 0.2
18.7 ± 0.4
2.3 max
-.002
.047 ± .008
.0925 ± .008
.736 ± .016
.091 max
I
1
0.108typ
C
K
11
1
1
. - : -
0.669 typ
Item
±
IT
Plastic
Shrinkdip
.878 typ
4.05 typ
1.2
1.
.126
2.75 typ
H
E
.0197 typ
1.1 typ
3.2
M
G
N~r
0.07 typ
2.17typ
17 typ
A
TI
Inche.
55.12 typ
22.3 typ
K
r-0--1
2.284 typ
c
G
.,.PD75CG19E
.,.PD78PG11E
1
+~~
I.
jcp~~~D.1
F
Item
T
00000000000000
max
1.3
2.54 ± 0.25
QUIL Ceramic
Piggyback
B
.05 ± .01
3.9 max
4.45
K
0.25
±
64 PIN (Cont.)
'I
A
D
.04
1.27
I-
00000000000000
1.5
1.02
G
Inch••
~:~
L~g
J-+
~J~
~IPgggggggg:ggg gggggg
7-9
Plastic
Miniflat
.,.PD7501G
.,.PD7502G/03G
.,.PD7227G
.,.PD78C06G
PACKAGE OUTLINES
80PIN-----------------------------------------------------Plastic
Item
m
Miniflat
fLPD7514G
fLPD7228G
Millimeters
+.3
14
B
12.0
0.3
.472 ± .012
C
18.4 ± 0.3
.724 ± .012
0
20
.55
-.2
±
+.3
-.2
0.8 ± 0.15
G
+0.2
-0.1
24.7 ± 0.4
7-10
-.008
.787
0.15
-0.05
K
+.012
-.008
.0315 ± .006
.0925
+.008
-.004
.972 ± .016
+0.10
H
18.7 ± 0.4
------------+1.1 .1
+.012
A
0.35
T1TTTT1'TT'TTT'1ll
Inch••
+.004
.006
-.002
.736 ± .016
2.35 ± 0.2
.0925 ± .008
1.2 ± 0.2
.048 ± .008
+0.25
2.05
-0.10
.081
+.01
-.004
NEe
QUALITY & RELIABILITY
OF NEC MICROPROCESSORS
IIr.II
ail
NEe
Introduction
As large-scale integration reaches a higher level of density,
reliability of devices imposes a profound impact on system
reliability. And as device reliability becomes a major factor,
test methods to assure acceptable reliability become more
complicated. Simply performing a reliability test according to
a conventional method cannot satisfy the demanding requirements for higher reliability: at these new, higher levels of LSI
density, it is increasingly difficult to activate all the elements in
the internal circuits. A different philosophy and methodology
is needed for reliability assurance in microprocessors and
family products. Moreover, as integration density increases,
the degradation of internal elements in an LSI device is seldom detected by measuring characteristics across external
terminals.
In order to improve and guarantee a certain level of reliability
for large-scale integrated circuits, it is essential to build quality and reliability into the product. Then the conventional
reliability tests are followed to ensure that the product demonstrates an acceptable level of reliability.
NEC has introduced the concept of Total Quality Control
(TQC) across its entire semiconductor production line. By
adopting TQC, NEC can build quality into the product and
thus assure higher reliability. The concept and methodology
of Total Quality Control are companywide activities-involving workers, engineers, quality control staffs, and all levels of
management.
NEC has also introduced a prescreening method into the
production line that helps eliminate most of the potentially
defective units. The combination of building quality in and
screening projected early failures out has resulted in superior
quality and excellent reliability.
This Reliability Report describes the philosophy and methodology used by NEC to attain a higher level of reliability for
microprocessors and family products.
Technology Description
Most microprocessors and family products are produced utilizing high performance, high density, N-channel MOS technology. State-of-the-art high performance has been achieved
by introducing fine line generation techniques. The data presented in this report shows that this advanced technology
yields products as reliable as those from previous
technologies.
By reducing physical parameters, circuit density and performance were increased while active circuit power dissipation
decreased. Current state-of-the-art N-channel MOS technology utilizes 2-4fLm channel length and a gate oxide thickness of 3OO-500A. This advanced process yields integration
densities of 400-800 gateslmm 2 with a speed-power product
of 1pJ or less.
Technology evolution
Technology evolved from early P-channel MOS to current
state-of-the-art high performance, high density, N-channel
MOS during the past decade. This evolution is expected to
continue in the future. As a result, even more high level functions will be included in a small area, as past history
demonstrates.
QUALITY AND RELIABILITY
OF NEC MICROPROCESSORS
Reliability Testing
Reliability is defined as the characteristics of an item
expressed by the probability that it will perform a required
function under stated conditions for a stated period of time.
This Involves the concept of probability, definition of a
required function(s), and the critical time used in defining
the reliability.
Definition of a required function, by implication, treats the definition of a failure. Failure is defined as the termination of the
ability of a device to perform its required function(s). Futhermore, a device is said to have failed if it shows inability to perform within guaranteed parameters as given in an electrical
specification.
Discussion of reliability and failure can be approached in two
ways: with respect to systems or to individual devices. The
accumulation of normal device failure rates constitutes the
expected failure rate of the system hardware. Important considerations here are the constant failure period, the early failure (infant mortality) period, and overall reliability level. With
regard to individual devices, areas of prime interest include
specific failure mechanisms, failures in accelerated tests, and
screening tests.
Some of these failure considerations pertain to both systems
and devices. The probability of no failures in a system is the
product of the probability of no failure in each of its components. The failure rate of system hardware is then the sum of
the failure rates of the components used to construct the
system.
Life distribution
The fundamental principles of Reliability Engineering predict
that the failure rate of a group of devices will follow the wellknown Bathtub curve in Figure 1. The curve is divided into
three regions: Infant Mortality, Random Failures, and Wearout Failures.
wearout
:Period
;;
Random Failure Period
'---------------~
' - + - - - - - - - - - - - - - _ Time
Figure 1. Reliability Life (Bathtub) Curve
Infant mortality, as the name implies, represents the early life
failures of devices. These failures are usually associated with
one or more manufacturing defects.
After some period of time, the failure rate reaches a low
value. This is the random failure portion of the curve, representing the useful portion of the life of a device. During this
random failure period there is a decline in the failure rate due
to the depletion of potential random failures from the general
population.
The wearout failures occur at the end of the device's useful
life. They are characterized by a rapidly rising failure rate
over time as devices wear out both physically and electrically.
8-1
Quality and Reliability
of NEC Microprocessors
Thus, for devices which have very long life expectancies
compared to those of systems, the areas of concern will be
the infant mortality and the random failure portions of the
population.
The system failure rates are related to the collective device
failure rates. In a given system, after elimination of the early
failures, the system will be left to the failure rate of its components. In order to make proper projections of the failure rate in
the operating environment, time-to-failure must be accelerated in tests in a predictable way.
FailUre distribution at NEe
MOS and Bipolar integrated circuits returned to NEC from the
field underwent extensive failure analysis at NEC's Integrated
Circuit Division.
First, approximately 50 percent of the field returns were
found to be damaged either from improper handling or misuse of the devices. These units were eliminated from the
analysis. The remaining failed units were classified by their
failure mechanisms, as depicted in Figure 2. These failures
were then related to the major integrated circuit failure mechanisms and to their origins in a particular manufacturing step.
As shown in Figure 2, the first four failure mechanisms
accounted for more than 90 percent of total failures. As a
result, NEC improved processes and material to reduce
these failures. Additionally, NEC introduced screening procedures to detect and eliminate defective devices.
Temperature, humidity, and bias tests are used for testing the
moisture resistance of plastic encapsulated integrated circuits. NEC developed a special process to improve the plastic encapsulation material. As a result, moisture-relatedthus packaging-related-failures have been drastically
reduced.
As a preventive measure, NEC has introduced a special
screening procedure embedded in the production line. A
burn-in at an elevated temperature is performed for 100 percent of the lots. This burn-in effectively removes the potentially defective units. In addition, improvement of the plastic
encapsulation material has lowered the failures in a high temperature and high humidity environment.
20
40
60
80
OXide
Destroyed
100
Percent Fa.ure
SJ02PaHem
Defects
Bond-Wire
Peel or Cut
_lzatIon
Defects
Percent Cumulative
FaHures
MoiS1Ure
PenetratIon
-
Parameter
Degradation
ChlplPeell
Crack
Accelerated reliability testing
As an example, assume that an electronic system contains
1000 integrated circuits and can tolerate 1 percent system
failures per month. The failure rate per component is:
0.01 Failures
_ 13.888 x 10-9 Failures/Hour
720K Device Hours or 13.8888 FITs
Where: FIT
= Failure unit per 109 device hours
To demonstrate this failure rate, note that 13.8888 FITs correspond to one failure in about 7,000 devices in an operating
test of 10,000 hours. It is quickly apparent that a test condition
is required to accelerate the time-to-failure in a predictable
and understandable way. The implicit requirement for the
accelerated stress test is that the relationship between the
accelerated stress testing condition and the condition of
actual use be known.
A most common time-to-failure relationship involves the
effect of temperature, which accelerates manyphysiochemical reactions leading to device failure. Other environmental
conditions are voltage, current, humidity, vibration, or some
combination of these. Table 2 lists the Reliability Assurance
Tests performed at NEC for the N-channel MOS devices.
Table 1. Monthly NEC Reliability Tests
Test
Method
Test Conditions
Lif. Test
High Temperature, Operating
M'L·STD·883B
10054, D
Til = 100°C to 125°C for 1000 hrs
High Temperature, Storage
1DOeC
Til - 150°C for 1000 hrs
High Temperature,
Ta
t-ligh Humidity Test
Pressure Cooker Test
= 85°C @85% RH for 1000 hrs
Ta - 125°C @2.3 Atm for 168 hrs
Environment., Test
= 260°C for las without flux
SOldering Heat Test
2031*
T
Temperature Cycle
101 DC
T=
Thermal Shock
1011A
T = O°C to 100°C for 15 cycles
Lead Fatigue
200482
@250gm: 3 leads, 3 bends
Solderability
2003
T - 230°C for 5s with flux
65°C to
+ 15O"C for 10 cycles
No'., . MI:!..L.:::ST=D-='750::CA:--~---'=~~~-'---='--'-''''-~~~~Temperature Effect: The effect of temperature that concerns us is that which responds to the Arrhenius relationship.
This relates the reaction rate to temperature.
R = Ro Exp[- Ea/kT]
Where: Ro = Constant
Ea = Activation energy in eV
k = Boltzmann's constant
= 8.617*10**( - 5) eV/degrees K
T = Absolute temperature in degrees K
The significance of this relationship is that the failure mechanisms of semiconductor devices are directly applicable to it. A
linear relationship between failure mechanism and time is
assumed.
Activation Energy: Associated with each failure mechanism is an activation energy value. Table 3 lists some of the
more common failure mechanisms and the associated activation energy of each.
Metalization
Corrosion
Figure 2. Failure Distribution of MOS Integrated Circuits
8-2
Quality and Reliability
of NEe Microprocessors
Table 2. Activation Energy and Detection of Failure Mechanisms
Activation
Failure Mechani.m
Energy
Oxide Defect
O.3eV
Detection
Silicon Defect
O.3eV
Ionic Contamination
1.0-1.35eV
High Temperature Operating
Electromlgratlon
O.4-0.8eV
Life Test
Charge Injection
1.3eV
Gold-Aluminum Interface
a.BeV
Metal Corrosion
O.7eV
High Humidity Operating
Life Test
High Temperature Operating Life Test: This test is used to
accelerate failure mechanisms by operating the qevices at an
elevated temperature. For N-channel MOS microprocessors
and their family products, the operating temperature is 125°C.
The data obtained is translated to a lower temperature by
using the Arrhenius relationship.
High Temperature and High Humidity Test: Semiconductor integrated circuits are highly sensitive to the general accelerating effect of humidity in causing electrolytic corrosion between biased lines. The high temperature and high
humidity test is performed to detect failure mechanisms
which are accelerated by these conditions. This test is effective in accelerating leakage-related failures and drifts in
device parameters due to process instability.
High Temperature Storage Test: Another common test is
the high temperature storage test in which devices are subjected to elevated temperatures with no applied bias. This
test is used to detect mechanical problems and process
instability.
Environmental Test: Other environmental tests are performed to detect problems related to the package, material,
susceptibility to extremes in environment, and problems
related to usage of the devices.
Failure Rate Calculation and Prediction
Analysis of integrated circuit failure rates can serve many
useful purposes. For example, the early life failure rate helps
establish a warranty period, while the mature life failure rate
aids in estimating repair costs, spare parts stock requirements, or product downtime. Accurate prediction of failure
rates can also be used for process control.
The following sections describe the failure rate calculation
and prediction methods used by NEC's Integrated Circuit
Division.
The Arrhenius model
Most integrated circuit failure mechanisms depend, to some
degree, on temperature. This relationship can be represented by the Arrhenius model, which includes the effects of
temperature and activation energy of the failure mechanisms.
As applied to accelerated life testing of integrated circuits, the
Arrhenius model assumes that degradation of a performance
parameter is linear with time. Temperature dependence is
taken to be the exponential function that defines the probability of occurrence. The relationship of failure rate to temperature is expressed as:
F,
=
F2* Exp[(Ealk) * (1IT, -1/T 2 )]
Where: F2 = Failure rate at T2
F, = Failure rate atT,
Ea = Activation energy
k = Boltzmann's constant
T = Operating junction temperature in degrees K
This equation explains the thermal dependence of integrated
circuit failure rates and is used for derating the resulting failure rate to a more realistic temperature.
Acceleration factor
The acceleration factor is the factor by which the failure rate
can be accelerated by increased temperature. This factor
is derived from the Arrhenius failure rate expression, resulting in the following form:
A
= F,/F2 = Exp((Ealk) * (1/T,
- 1/T2 )]
Where: A = Acceleration factor
F2 = Failure rate at T2
F, = Failure rate atT,
In calculating the field reliability of an integrated circuit, it is
necessary to calculate the junction temperature. In general,
the junction temperature will depend on the ambient temperature, cooling, package type, operating cycle time, and
power dissipation of the circuit itself. In these terms, the junction temperature (TJ) is expressed as:
TJ = T a
+ Pd * Af * ejA
Where: TJ = Junction temperature
Ta = Ambient temperature
Pd = Power dissipation
Af = Air flow factor
ejA = Package thermal resistance
Table 4 lists derating factors of various failure mechanisms.
This table is generated assuming that an accelerated test is
performed at a junction temperature of 125°C. The result is
then derated to 55°C junction temperature. The acceleration
factor may then be obtained by taking the inverse of the
derating factor.
Table 3. Derating Factors of Failure Mechanisms
Failure Mechanism
Activation Energy
Derating Factor
OXide Defect
O.leV
0.1546
Silicon Defect
O.3eV
0.1546
Ionic Contamination
1.0eV
0.00'984
Electromlgration
MeV
0.08307
Charge Injection
1.3eV
0.0003067
Metal CorrOSion
0.7eV
0.01315
Gold-Aluminum Interface
O.8eV
0.006886
The acceleration of failure mechanisms in a high humidity
and high temperature environment must be expressed as a
function not only of temperature but also of humidity.
According to the reliability test statistics, the acceleration factor in such an environment can best be approximated with
Peck's model as follows:
A = Exp((Ealk) * (1/T, - 1IT2)] * [HdH,] ** 4.5
Where: Ea = Activation energy
k = Boltzmann's constant
T = Junction temperature
H = Relative humidity
8-3
Quality and Reliability
of NEe MicroproceSSOrs
For example, the acceleration factor for high humidity and
high temperature or pressure cooker tests ranges from 100 to
1000 times that of the normal oper"lting environment.
Failure rate calculation
As an example, suppose that NEC's microprocessors and
family product samples are submitted to a 1Ooo-hour life
test at 125°C junction temperature and encounter two failures: one oxide and one metalization defect. The sample
size is 885 units.
Thus, the oxide failure rate is 0.11 percent per 1000 hours and
the metalization failure rate is 0.11 percent per 1000,hours.
Therefore, the total failure rate at 125°C sums to 0.22 percent
per 1000 hours at 1K hours.
Failure rate p~lctlon
To derate these failure rates to a normal operating environment, use the derating factors listed in Table 4.
Oxide Failures = 0.11 • 0.1546 = 0.01701 % per 1K hrs
Metal Failures = 0.11 • 0.01315 = 0.00145% per 1K hrs
Total Failures = 0.01846% per 1K hours
Note that the example above is a snapshot of the high temperature life test performed on a particular lot. It is not accumulated data that can be used to represent overall reliability.
This conservative illustration, however, shows that the failure
rate in a normal operating environment is approximately 12
times lower than that of a higher temperature environment.
The failure rate prediction takes different activation energies
into account whenever the causes of failures are known '
through performing failure analysis. In some cases, however,
an average activation energy is assum9d in order to accomplish a quick first-order approximation: NEC assumes an
average activation energy of 0.7eV whenever the exact failure mechanis,m is not known, to yield a conservative estimate
of failure rates.
Reliability Test Results
Before introducing new technologies or products, NEC's
intemal reliability goals must be attained. Several categories
of testing af'EI used in the internal qualification program to
assure that prod\lct reliability meets NEC's reliability goals.
Once the product is qualified, its reliability level is regularly
monitored in a monthly reliability test.
NEC's Goals on Failure Rates
NEC's approach to achieving high reliability is to build quality
into the product, as opposed to merely screening out defective units. The use of distributed control methods embedded
in the production line, in conjunction with conventional
screening methods, results in the highest reliability at the
lowest cost.
NEC currently maintains failure rates for infant mortality and
long-term device operation as listed in Table 4.
Table 4. Infant Mortality and Long-term Failure Rates
percent F.llure
A.teOoe's
Infant MortalHV failure Rate
O.1011Khra
Long-tenn Life Failure Rate
1.2M Device Hour Average
3.0M Device Hour Average
O.02/1Khr.
O.Ol/1Khre
Infant mortality process average goals
The infant mortality goal for each prOduct group is set at
0.10 percent. When a failure rate exceeds this level, there is
prompt remedial action to reduce this rate.
Long-term failure rate goals
The long-term failure rate goal is based on the following
conditions:
D A minimum of 1.2 million device hours at 1250C is accumulateq to resolve 0.02 percent per 1000 hours at 55°C with
a 60 percent confidence level.
D A minimum of 3 million device hours at 125°C is accumuI~ied to resOlve 0.01 percent per 1000 hours at 55°C With
a 60 p~rcent confidence level.
Infant Mortality Failure Screenlnlll
It is logical to assume that the integrated circuit that fails
at one tempera1Ure would also fail at another temperature,
except that it would fail sooner at a higher temperature. As
can be expected, the failure rate is a function of its associated activation energy. Establishing infant mortality screening, therefore, requires knowledge of the likely failure
mechanisms and their associated activation energy.
The most likely mechanisms associated with infant mortality
failures are,generally manufacturing defects and process
anomalies. Thesegenerally consist of contamination,
cracked chips, wire bond shorts, or bad wire bonds. Since
these describe a number of possible mechanisms, anyone
of whicYl might predominate at a given time, the activation
energy, fot infant mortality might be expected to vary
considerably.
The effectiveness of a screening condition, preferably at
some 'stress level in order to shorten the time, varies greatly
with the failure mechanism being screened for. Another factor
is the economics of the screening process introduced into the
production line. Optimal conditions and duration of a screening process will be a compromise of these two factors.
For example, failures due to ionic contamination have an activation energy of approximately 1.Oev, Therefore, a t5-hour
stress at 125°C junction temperature would be the' equivalent
of approximately 90 days of operation at a junction temperature of 55°C. On the other hand, failures due to'oxide defects
have an activation energy of approximately O.3e\l, and a
15-hqut stress at 125°C junction temperature would be the
equivalent of approximately one week'~ operation at 550C
jUflction temperature. As indicated by this, the conditiQn and
duration of infarit mortality screening would be a strong function of the allowable component failures, hence the system
failure, in the field.
Empirical data, gathered over more than a year at NEC, indicates that early failure does occur after less than 4 hours of
stress at 125°C ampient temperature. This f~ct is supported
by the life test of the same lot, where the failure rate shows
random distribution, as opposed to a decreasing failure rate
which then runs into the random failure region.
NEC has adopted the initial infant mortality burn-in at 125°C
as a standard production screening procedure. As a result,
the field reliability of NEC devices Is an order of magnitude higher than the goals set for NEC's integrated circuit
products.
8-4
Quality and Reliability
of NEe Microprocessors
Life Tests
The most significant difference between NEC's products
and those of other integrated circuit manufacturers is the fact
that NEC's have been prescreened for their infant mortality
defects. The products delivered to customers are operating at
the beginning of the random failure region of the life curve.
The life test data also reflect this fact, as will be shown in the
following sections.
The failure mechanism distribution from field failures, as previously shown in Figure 2, also contains a very low percentage due to infant mortality. The majority of failures are longterm life failures, and these can be eliminated by stringent
process control. Usually, these failure mechanisms have low
activation energy associated with them.
Another significant improvement devised by NEC is plastic
encapsulation and passivation. As a result, NEC products
show excellent reliability in both high humidity and high temperature environments. Following is life test data accumulated over more than a year for N-channel microprocessors
and family products.
High temperature operating life test
This test is used to accelerate failure mechanisms by operating the devices at an elevated temperature. For microprocessors and family products, the failure rate is 0.242 percent per
1000 hours at 125°C. This is equivalent to 0.0071 percent per
1000 hours in an operating environment of 55°C (Table 5).
Table 7. High Temperature Storage Life Test
48 hra
H hr.
168 hr.
2410
000
Total Number of Failures at 1K hr. - 5
Failure Rate at 1K hra at 125°C
= 0.207% per 1 K hrs
Projected Failure Role a1SS'C
= 0.006% par 1 K hr.
Number of F.llures at
Sampl••
tUh,.
48hrs
98hrs
3317
Total Number of Failures at 1K hr. - 8
Failure Rate at 1K hr. at 1250C
= 0.242% per 1K hrs
Projected Failure Rate 81SS'C
= 0.007% per 1 K hrs
5OGh,.
1Khrs
High temperature and high humidity life test
This test is used to accelerate failure mechanisms by
operating the devices at high temperature and high humidity.
Leakage-related failures and device parameter drift are accelerated by this test. For microprocessors and family products,
the failure rate is 0.091 percent per 1000 hours. This is equivalent to 0.0027 percent per 1000 hours in an operating environment of 55°C. The test conditions are Ta = 85°C and
relative humidity (RH) = 80% (Table 6).
1Khr.
500 hra
1
. ."",I. .
Pressure cooker test
This test is effective in accelerating failure mechanisms
related to metalization corrosion due to moisture. The failure
rate is 0.52 percent per 1000 hours at Ta = 125°C and 2.3
Atm at 100 percent humidity. This is equivalent to 0.0013 percent per 1000 hours at 55°C and an environment of 60 percent humidity (Table 8).
Table 8. Pressure Cooker Test
Number of Failures at
Numb.rot
'Semple.
48hra
"hra
iN'''.
1Khr.
500h...
4
1718
No Test Performed
Total Number of Failures at 168 hr. 9
Failure Rata at 125"<:
= 0.54% per 1K hr.
Projected Failure Rate at 55°C
= O.(MJ1% per 1 K hrs
Life test data summary
Table 9 summarizes the life test results and projected failure
rates In the normal operating environment. The failure rate
shows random distribution as opposed to a decreasing failure
rate. This is a result of infant mortality screening.
Table 9. Life Test Data
Number of Failur•• at
Testltern
Number of
Sampl••
High Temperature
UfaTea1
3317
High HumKlHy
UfaTesl
2190
High Temparatura
S10rage Life Test
2410
Table 5. High Temperature Operating Life Test
Numlaerof
Number of Falluree at
Number of
Pressure
CookerToa1
Mhrs 16. hr. 500 hra 1 K hra
Total
Numb.rot
Failures
1718
Total
24
9635
Note: • - No test performed
The projected failure rate in the normal operating environment is calculated assuming that the average activation
energy is 0.7eV.
Figure 3 shows the life distribution of NEC integrated circuits
as a form of the Bathtub curve.
Table 6. High Temperature and High Humidity Life Test
Number of F.llur. at
Numberot
Sampl_
2190
48 hra
H hr.
18. hr.
500 hr.
1Khrs
0 0 0
Total Number of FaHure& lit 1K hr.
=2
Failure Rate III: 1 K hrs at 85"C18S% RH = 0.091% per 1 K hr.
.oso
ProJoc18d Failure Rate 81SS'C!6O% RH - 0.003% par 1 K hrs
High temperature storage life test
This test is effective in accelerating the failure mechanisms
related to mechanical reliability problems and process instability. For microprocessors and family products, the failure
rate is 0.207 percent per 1000 hours at 125°C. This is equivalent to 0.0061 percent per 1000 hours in an operating environment of 55°C (Table 7).
.DID
.DOS
o.sK
lK
2K
3K
4K
5K
10K
20K 30K
Figure 3. Plot of Life Test Results
8-5
Hra
-Quality and Reliability
of NEe Microprocessors
This life test data shows improvements of approximately
an order of magnitude better than NEC's goal. The hours of
operation ~re equivalent to the normal operating environment. Wear-0ut failures, which had been the main target for
reliability improvement, have also been significantly reduced.
This result comes mainly from process improvements and
stringent manufacturing process control.
NEC's main goal has been to improve reliability with respect
to infant mortality and long-term life failures. This can be
achieved by introducing an effective screening method for
infant mortality and building quality into the product.
Thermal stress tests'
Temperature cycling and thermal shock test the thermal compatibilityof material and metal used to make integrated circuits. Table 10 lists the reliability test results of thermal stress
tests.
Table 10. Thermal Stress Results
Numberot
Testllem
S.mpl••
Number
0'
Failur••
SOldering Heat Teat
Ta = 260"C for 10 eecondl
1891
Tempemure Cycle
T. = -&sOC to + 15O'C, 10 cycles
Thermal Sh_ Test
Ta = ere to + 1DCrC, 15 cycles
1891
1891
Mechanical stress tests
In addition to the device life test, NEC performs mechanical
stress tests to detect reliability problems related to the package, material, and device susceptibility to an extreme environment. Table 11 lists mechanical stress test results.
Table 11. MechanIcal Stress Results
leotHam
Mechanical Shock Teat
@l5kg, 3 axl.
Vlbmlon Taot
@100Hzto2kHz,20g
Numberot
Sampl••
Numberot
Fallur••
315
315
Constant AcceteratIon
@2Okg,3axls
315
Lead FOIlg. . Test
@250gms
638
Solderability Teat
@23O'Clor50ac0nds
638
Bullt·ln Quality and Reliabiiity
As large-scale integration reaches even higher levels of density, simple quality inspections cannot assure adequate levels
of product quality and reliability. In order to ensure the reliability of state-of-the-art, very large-scale integrated circuits,
NEC has adopted another approach. Highest reliability and
superior quality of a device can only be achieved by building
-these characteristics into the product at each process step.
NEC, therefore, has introduced the notion of Total Quality
Control (TQC) into its entire semiconductor production line.
Quality control is distributed into each process step and then
all are summed to form a consolidated system.
Approach•• to Total Quality Control
First, the quality control function is embedded into each
process. This method enables early detection of possible
causes of failure and immediate feedback.
Second, the reliability and quality assurance policy is an
integral part of the entire organization. This enables a
companywide quality control activity. At NEC, everyone in the
company is involved with the concept and methodology of
Total Quality Control.
.
Third, there is an on-going research and development effort
to set even higher standards of device quality and reliability.
Fourth, extensive failure analysis is performed periodically
and corrective actions are taken as preventive measures.
Process control is based on statistical data gathered from this
analysis.
The goal is to maintain the superior product quality and reliability that has become synonymous with the NEC name.
The new standard is continuously upgraded and the iterative
process continues.
Implementation of distributed quality control
Building quality into a product requires early detection of possible cause of failure at each process step. Then, immediate
feedback to remove the cause of failure is a must. A fixed
station quality inspection is often lacking in immediate feedback. It is, therefore, necessary to distribute quality control
functions to each process step, including the conceptual
stage. NEC has implemented a distributed quality <;antrol
function at each step of the process. Following is a breakdown of the significant steps:
Product development phase
Wafer processing
Chip mounting and packaging
Electrical testing and thermal aging
Incoming material inspection
Product Development Phase: The product development phase includes conception of a product, review of the
device proposal, organization and phYSical element design,
engineering evaluation, and finally, transfer of the product to
manufacturing. Quality and reliability are considered at every
step. More significantly, at the design review stage and prior
to product transfer, the quality and reliability requirements
have to be examined and determined to be satisfactory. This
often adds two to three months to the product development
cycle. Building in high reliability, however, cannot be
sacrificed.
Wafer Processing Stage Inspection: The in-process quality inspections that occur at the wafer fabrication stage are
listed in Table 12.
o
o
o
o
o
Table 12. Wafer Fabrication Inspection
Wafer
Inspection Item
ReslatlvHy, Dimension, and Appearance,
Lot Ssmpllng Inspac1lon
Mask
PholO-Uthography
Alignment and Etching, 100 Percent Inspection
Claon'ng
Oxide thickness, Sheet ResistIVity, Lot Sampling
Inspection
MetallzaDon and P888rvatlon
Thlcknesa, VUI. C-V Characteristics, and Lot Sampling
Wafer Sort and Scribe
DC Parameters. 100 Percent Inspection
DteSOrt
100 Percent VlauallnepecUon
8-6
Quality and Reliability
of NEe Microprocessors
Chip Mounting and Packaging: The in-process quality
inspections that are done at the chip mounting and packaging
stage are listed in Table 13.
Table 13. Chip Mounting and Packaging Inspection
Proce••
Inspection Item
Die
Incoming Material Inspection
Ole Attach
Appearance. Lot Sampling Inspection
Wire Bonding
Bond Strength, Appearance, Lot Sampling
Packaging
100 Percent Appearance Inspection
Fine Leak*
LotSampilng
100 Percent Inspection
Note;
* For ceramic
package devices only
Electrical Testing and Screening: Electrical testing and
infant mortality screening are performed at this stage. A flowchart of the process is depicted in Figure 4.
DC Parameters
DC Parameters,
AC Functional
aectrlcal,
Appearance, and
DImenSIons
Figure 4. Electrical Testing and Screening
At the first electrical test, DC parameters are tested, according to the electrical specifications, on 100 percent of each lot.
This is a prescreening prior to the infant mortality test. At the
second electrical test, AC functional as well as DC parameter
tests are performed on 100 percent of the subjected lot. If the
percentage of defective units exceeds the limit, the lot is subjected to an additional burn-in. As this defective lot is being
subjected to an additional burn-in, the defective units are
undergoing a failure analysis, the results of which are then
fed back into the process for corrective action.
Incoming Material Inspection : Prior to warehouse storage,
lots are subjected to an incoming inspection according to the
following sampling plan:
Electrical test: DC parameters LTPD
3%
Functional test LTPD
3%
Appearance
LTPD
3%
Reliability assurance test
Samples are continually taken from the warehouse and subjected to monthly reliability tests as discussed in the previous
section. They are taken from similar process groups so that it
can be assumed that any device is representative of the reliability of that group.
In-process screening
Perhaps the most significant preventive measure that NEC
has implemented is the introduction of 100 percent burn-in as
an integral part of the standard production process. Most of
the potential infant failures are effectively screened from
every lot, thereby improving reliability. Assuming average
activation energy of 0.7eV, bum-in at Ta = 125°C for four
hours is equivalent to a week's operation in a normal operating environment. This appears to be ample time for accelerating the time-to-failure mechanisms for early failures.
Process automation, as previously mentioned, has also contributed a great deal in improving reliability. Since its introduction, assembly related failure mechanisms have been
substantially reduced. And, in combination with in-process
screening and materials improvement, it has helped establish
quality and reliability above NEC's initial goals.
Summary and Conclusion
As has been discussed, building quality and reliability into
products is the most efficient way to ensure product reliability.
NEC's approach otdistributing quality control functions to
process steps, then forming a consolidated quality control
system, has produced superior quality and excellent
reliability.
Prescreening, introduced as an integral part of large-scale
integrated circuit production, has been a major factor in
improving reliability. The most recent year's production clearly
demonstrates continuation of NEC's high reliability and the
effectiveness of this method.
Reliability Assurance Tests (RATs), performed monthly, have
ensured high outgoing quality levels. The combination of
building quality into products, effective prescreening of potential failures, and the reliability assurance test has established
a singularly high standard of quality and reliability for NEC's
large-scale integrated circuits.
With a companywide quality control program, NEC is commiUed to building superior quality and highest reliability into
all its products. Through continuous research and development activities, extensive failure analysis, and process
improvements, a higher standard of quality and reliability
will continuously be set and maintained.
o
o
8-7
m
:
Notes
8-8
NEe
REPRESENTATIVES & DISTRIBUTORS
IJ
NEe
u.s. REPRESENTATlVE$
Washington
Alabama
Michigan
~:;v~,~lL~~~mg, Inc
Mlltlmore Sales, Inc
Grand Rapids, MI 49506
ElectroniC Techmcal Sales ASSOCiates
Kirkland, WA98033
616-942-9721
NOVI, MI46050
313-349-0260
206-627-6086
Minnesota
CANADIAN
REPRESENTATIVES
205-533-9261
ArizoRa
Fred Board AsSOCiateS, Inc
Scottsdale, AZ65251
602-994-9366
Tucson, AZ 85704
602-299-1508
George Russell & AsSOCiates
Bloomington, MN 55420
tall"mia
••• Jarse,
CERCO
B G R AsSOCiates
Marlton, NJ 08053
~r~_~J:j~'9~ 92117
Quorum Technical Sales
San1a Clara, CA 96054
406-96O-{I812
Celorado
Gandar, Inc
Go~en, CO 60401
303-233-0155
612-654-1166
609-426-2440
HLM AssOCIates, Inc
~~~~f~ 07054
lew Muico
Rontek, Inc
~5~~~~4NM 87191
Connecticut
_Yort<
HLMAssoClates
Waterbury, CT 06708
ELCOM Sales
203-753-9694
Florida
8emtromcs, Inc
~~~3~~~ngs, FL 32701
Clearwater. Fl33515
613-461-4675
Georgi.
Montgomery Marketing, Inc
Norcross, GA 30092
404-447-6124
IlIInol.
AM E Sales
CollinsVille, IL 62234
616-345-7404
sel~er
AssOCiates
~f1~~~1~~~~ws, IL 60008
Indiana
MIS sales & ASSOCiates, Inc
Fort Wayne, IN 46606
British Columbia
Kaytromcs Western
Penfield, NY 14526
716-365-1400
Skaneateles, NY13152
315-085-6245
HLM ASSOCiates, Inc
Northport, NY 11766
516-757-1608
IIIorth carelina
Montgomery Marketing, Inc
Cary, NC27511
919-467-6319
Pennsylvania
Imtech, Inc
Pittsburgh, PA 15243
412-344-0644
Obi.
Imtech, Inc
Akron, OH 44321
216-666-1165
~f~~%~l'!~ilr14
~~~~£g~~~1 ~N 46260
IQwa
Tennns..
George Russell & AssoCIates
Cedar Rapids, IA 52402
503-640-6066
~;I~I~~u~ ~~::ng, Inc
319-369-9134
615-966-3608
Kansas
A M E Sales
Overland Park, KS 66202
913-262-3971
TelOS
Maryland
ProfesSional Representatives
Baltimore, MD 21208
Carrollton, TX 75006
301-653-3600
Massachusetts
Compass Technology
Woburn, MA 01801
617-933-3336
quobec
~re~tl~er~~ au H8R 3Y8
514-367-0101
Drog..
ElectroniC Technical Sales AsSOCiates
Hillsboro, OR 97123
219-464-1904
~~'?81B~~3r 4G6
Ontario
Kaytromcs, Inc
Concord, Ontano L4K1B1
416-669-2262
Kanata, Ontano K2K 2A3
613-592-6606
Technical Marketing, Inc
Austin, TX 78758
512-635-0064
214-367-3601
Houston, 1)( 77081
713-777-9226
utab
Aspen Sales
Salt lake City, UT 64115
601-467-2401
9-1
NEe NEC Electronics
401 Ellis Street
Mountain View, CA 94943
TEL. 415-960-6000, lWX: 910-379-6985
(
84 MICROCAT-1-84-USA 50 K
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2010:11:15 11:17:03-08:00 Modify Date : 2010:11:15 13:37:29-07:00 Metadata Date : 2010:11:15 13:37:29-07:00 Producer : Adobe Acrobat 9.4 Paper Capture Plug-in Format : application/pdf Document ID : uuid:71dff990-65c1-4213-ac40-bad60af47953 Instance ID : uuid:c21a6726-6d30-4cf7-9042-3936789e833a Page Layout : SinglePage Page Mode : UseNone Page Count : 658EXIF Metadata provided by EXIF.tools