1984_National_Linear_Supplement 1984 National Linear Supplement
User Manual: 1984_National_Linear_Supplement
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LINEAR SUPPLEMENT DATABOOK Amplifiers Comparators Voltage Regulators Voltage References Converters Analog Switches Sample and Hold Sensors III III (II • III Filters Building Blocks II Motor Controllers ,. •II Consumer Circuits Telecommunications Circuits Speech Special Analog Functions Physical Dimensions 8-3 III II TRADEMARKS Following is the most current list of National Semiconductor Corporation's trademarks and registered trademarks. Abuseable™ ISETM pOSitalker™ Anadig™ ISE/16TM QUAD3000™ ANS-R-TRANTM Macrobus™ RATTM Auto-Chem DefiasherTM Macrocomponent™ Scripb'Chek™ BI-FETTM Maxi-ROM® Shelf-ChekTM BI-FET IITM Meab'ChekTM BI-LiNETM Microbus™ data bus (adjective) SERIES/800™ SPIRETM BIPLANTM MICRO-DACTM StarlinkTM BLC/BLXTM p.talker™ STARPLEXTM CIMTM Microtalker™ STARPLEX IITM CIMBUSTM MICROWIRETM SuperChipTM Clock...ChekTM SYS-16TM COPSTM microcontrollers MICROWIRE PLUSTM MSTTM DATACHECKER® Nitride Plus™ TDSTM DENSPAKTM The National Anthem™ DIBTM Nitride Plus Oxide™ NMLTM DIGITALKER® NSC800TM DISCERNTM NS16000™ NSX-16TM Trapezoidal™ TRI-CODETM DNRTM DPVMTM - TAPE-PAKTM Time...ChekTM TRI-POLYTM TRI-SAFETM E-Z-LlNKTM '''SCX-16™ NURAMTM GENIXTM OXISSTM XMOSTM HEX 3000TM Perfect WatchTM XPUTM INFOCHEXTM Pharma..-ChekTM Z STARTM Integral ISETM PLANTM 883B/RETSTM IntelisplayTM Polycraft™ 883S/RETSTM TRI-STATE® Teflon® is a registered trademark of Dupont Corp. Dolby® is a registered trademark of Dolby Labs. Intellec® and MULTIBUS® are registered trademarks of Intel Corp. MULTIMODULETM isa trademark of Intel Corp. Z80® is a registered trademark of Zilog Corp. CXTM is a trademark of CBS Labs. LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 2900 Semiconductor Drive, Santa Clara, California 95051 (408) 721-5000 TWX (910) 339-9240 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied, and National reserves the right, at any time without notice, to change said circuitry or specifications. S-4 Introduction Aftn de permettre a sa clientele une mise a jour plus facile, National Semiconductor propose en plus de sa documentation classique un Additif Lineaire 1984. Ce dernier comporte les informations les plus recentes sur les produits nouvellement sortis ainsi qu'un index recapitulatif de ceux deja exposes dans Ie livre principal. Les produits nouveaux qu'il comporte sont signales par une asterisque et des caracteres gras. Les fiches techniques mises a jour sont imprimees en caractere gras. Ce nouveau systeme a pour but d'orienter la clientele sur les produits les plus recents. L'edition supplementaire contient a peu pres 500 pages de specifications. Elle com'prend possibilites d'application, descriptions, unites supplementaires, courbes caracteristiques de regulateurs de tension, op amps, comparateurs de tension, convertisseurs AID et D/A, modules industriels, circuits audio, radio et TV, dispositifs avances de telecommunication, circuits de synthese de parole Digitalker, ainsi que d'autres produits analogiques. Les produits lineaires de National sont economiques, de haute qualite et fiables. Si vous desirez des renseignements supplementaires sur nos produits nouveaux, veuillez vous adresser a votre representant local de National Semiconductor. Introduction The 1984 Linear Supplement provides the most recent information available on National's new linear products. This supplement also provides a comprehensive index of product listings published in the master databook. New products described herein are indicated by an asterisk and bold type. Revised datasheets are listed in bold type. National's master/supplement databook system allows you to make product selections based on your knowledge of our latest product offerings. This supplement edition presents approximately 500 pages of specifications. It includes applications, descriptions, features, and diagrams of voltage regulators; op amps; voltage comparators; AID and 0/A converters; industrial building blocks; audio, radio, and TV circuits; advanced telecommunications devices; and DIGITALKER® speech synthesis circuits, as well as other analog products. National's linear products offer economy, quality, and reliability. For further information on any of our new products, contact your National Semiconductor sales representative. Introduzione II supplemento 1984 al catalogo "LINEAR" della National fornisce Ie pili aggiornate informazioni sui nuovi prodotti lineari. Questo supplemento presehta, inoltre, un indice completo di tutti i prodotti che sono pubblicati sui catalogo prin- . cipale. I nuovi prodotti descritti nel supplemento sono caratterizzati in neretto, con una '. Einleitung Der Ergiinzungsband Lineare Produkte 1984 enthiilt die aktuellsten Informationen iiber Nationals neue lineare Produkte. Dieser Zusatzband bietet ebenfalls ein umfassendes Verzeichnis aller Produktaufstellungen, die im Hauptdatenbuch enthalten sind. Hier beschriebene neue Produkte sind in Fettdruck, mit ein '. Oberarbeitete Datenbliitter sind in Fettdruck aufgefiihrt. National-Datenbiicher - Hauptbiinde und Zusatzbiinde - geben Ihnen die Moglichkeit, Ihre Produktwahl gemiiJ3 unserer jiingsten Produktangebote zu treffen. I fogli tecnici (datasheets) corretti sono pubblicati in neretto. II sistema catalogo principale/supplemento permette una perfetta scelta dei prodotti, grazie aile pili recenti ed aggiornate informazioni disponibili sugli stessi. Questo supplemento presenta circa 500 pagine di specifiche. Esso comprende applicazioni, descrizioni, caratteristiche e diagrammi su: regolatori di tensione, amplificatori operazionali, convertitori AID e 0/ A, circuiti dedicati per sistemi industriali, circuiti audio e radio/TV, dispositivi avanzati per telecomunicazioni, circuiti per la sintesi del parlato DIGITALKER oltre a numerosi altri. ' Die vorliegende Ergiinzungsausgabe umfam etwa 500 Seiten Spezifikationen. Sie enthiilt Angaben zu Anwendungen, Beschreibungen, Zusiitzen und Diagramme. von Spannungsreglern, op amps, Spannungsvergleicher, A/D- und 0/ A-Wandler, industrielle Bausteine, Audio-, Rundfunk- und Fernsehschaltungen, neueste Telecombauteile, DIGITALKER®- Sprachsynthese-Schaltungen sowie andere analoge Produkte. Nationals lineare Produkte sind kostengiinstig, von hoher Qualitat und zuverliissig. Sollten Sie weitere Informationen iiber unsere neuen Produkte wunschen, setzen Sie Sich bitte mit Ihrem National Semiconductor-Vertreter in Verbindung. I prodotti lineari della National Semiconductor'offrono qualita, affidabilita e soluzioni economiche. Per ulteriori informazioni sui prodotti elencati Vi preghiamo di contattare iI nostro ufficio vendite pili vicino. S-5 Devices listed in Boldface are included In this supplement with changes. Devices listed in Boldface with an asterisk (*) are new parts. Table of Contents SECTION I - AMPLIFIERS Buffer Amplifiers LH0033/LH0033A, LH0033C/LH0033AC, LH0063/LH0063C Fast and Damn Fast Buffer Amplifiers ......................................................... '.... . S 1-7 Combined Functions LM10/LM10B(L)/LM10C(L) Op Amp and Voltage Reference .•.....•................ Instrumentation Amplifiers . LH0036/LH0036C Instrumentation Amplifier .........................'............. . LH0038/LH0038C True Instrumentation Amplifier ................................. . LH0084/LH0084C Digitally Programmable Gain Instrumentation Amplifier ............ . LH0086/LH0086C Digitally Programmable Gain Amplifier .....................•..... LM121/LM221/LM321, LM121A1LM221A/LM321A Precision Preamplifiers .......... . 4-18 4-26 4-37 3-364 4-5 LM163/LM363 Precision Instrumentation Amplifier ............................. . S 1-24 LM725/LM725A1LM725C (Instrume'ntation) Operational Amplifier ................... . Operational Amplifiers LF147/LF347 Wide Bandwidth JFET Input Operational Amplifier .................... . LF155/LF156/LF157 Series Monolithic JFET Input Operational Amplifiers ............ . LF351 Wide Bandwidth JFET Input Operational Amplifier ........................... . LF353 Wide Bandwidth Dual JFET Input Operational Amplifier ...................... . LF400C Fast Settling JFET Input Operational Amplifier ............................. . LF411 AlLF411 Low Offset, Low Drift JFET Input Operational Amplifier ............... . LF412A/LF412 Low Offset, Low Drift Dual JFET Input Operational Amplifier .......... . LF441 AlLF441 Low Power JFET Input Operational Amplifier ....................... . LF442A1LF442 Dual Low Power JFET Input Operational Amplifier ................... . LF444A1LF444 Quad Low Power JFET Input Operational Amplifier ...........•....... LF13741 Monolithic JFET Input Operational Amplifier ..............•................ LH0003/LH0003C Wide Bandwidth Operational Amplifier .......................... . LH005/LH005A Operational Amplifier ...................................... ~ .... . LH005C Operational Amplifier .................................................. . LH0021/LH0021 C 1.0 Amp Power Operational Amplifier ........................... . LH0022/LH0022C High Performance FET Op Amp ................................. . LH0024/LH0024C High Slew Rate Operational Amplifier ........................... . 3-253 3-99 3-14 3-22 3-35 3-42 3-51 3-53 3-60 3-66 3-73 3-81 3-88 3-294 3-299 3-302 3-304 3-311 3-318 LH0032, LH0032A, LH0032C, LH0032AC Ultra Fast FET-Input Operational Amplifier S 1-1 LH0041/LH0041 C 0.2 Amp Power Operational Amplifier ........................... . LH0042/LH0042C Low Cost FET Op Amp ........................................ . LH0044 Series Precision Low Noise Operational Amplifiers .......................... . LH0045/LH0045C Two Wire Transmitter ......................................... . LH0052/LH0052C Precision FET Op Amp .....................•................... LH0061/LH0061 C 0.5 Amp Wide Band Operational Amplifier ....................... . LH0062/LH0062C High Speed FET Operational Amplifier .......................... . LH01 01/LH01 01 C, LH01 01 AlLH01 01 AC Power Operational Amplifier ............... . 3-304 3-311 3-338 3-344 3-311 3-555 3-358 3-382 *LH0132, LH0132C Ultra-Fast FET-Input Operational Amplifier Featuring Low Input Bias Current over ± 10V Input Range ..............•........... , .............. . S 1-18 LH740AlLH740AC FET Input Operational Amplifier ................................ . LH20111LH2011 B/LH2011 C Dual Operational Amplifiers .......................... . LH2101A1LH2201A1LH2301A Dual High Performance Op Amp ..................... . LH2108/LH2208/LH2308, LH21 08A/LH2208A1LH2308A Dual Super Beta Op Amp ... . LH24250/LH24250C Dual Programmable Micropower Op Amp ..................... . LM11/LM11 C/LM11 CL Operational Amplifiers ..................................... . LM101A/LM201A1LM301A Operational Amplifiers ................................ . LM1 07/LM207lLM30~ Operational Amplifiers .................•.•................. LM1 08/LM208/LM308 Operational Amplifiers .................................... . 3-382 3-384 3-397 3-399 3-403 .3-115 3-128 3-140 3-144 5·7 Table of Contents (Continued) LM108A1LM208A1LM308A, LM308A-1, LM308A-2 Operational Amplifiers ............ . LM112/LM212/LM312 Operational Amplifiers .................. '.................. . LM118/LM218/LM318 Operational Amplifiers .................................... . LM124/LM224/LM324, LM124A1LM224A1LM324A, LM2902 Low Power Quad Operational Amplifiers ......................................................... . LM143/LM343 High Voltage Operational Amplifiers ............................... . LM144/LM344 High Voltage, High Slew Rate Operational Amplifier ................. : . LM146/LM246/LM346 Programmable Quad Operational Amplifiers .................. . LM148, LM149 Series Quad 741 Op Amps ............. : ...... : ................... , LM158/LM258/LM358, LM158A1LM258A1LM358A, LM2904 Low Power Dual . Operational Amplifiers ..... : ; .................... : ..............'. '............... . Dual Operational Amplifiers .................. ; ... ~ ................... , .......... . LM216/LM316, LM216A/LM316A Operational Amplifiers ...... : ................... . LM709/LM709A1LM709C Operational Amplifier ....... '......•..................... LM741/LM741A1LM741C/LM741E Operational Amplifier .•............... : ........ . , LM747/LM747A1LM747C/LM747E Dual Operational Amplifiers .................... . LM748/LM748C Operational Amplifier ........................................... . 3-149 3-161 3-165 3-172 3-181 3-188 3-194 3-206 3-216 3-246 3-249 3-257 3-260 3-265 *LM833 Dual Audio Operational Amplifier . ................... ; ................... ' S 1·45 LM1558/LM1458 DualOperational Amplifier ........ ~ ... ~ .............. ; .......... . . LM2900/LM3900, LM3301, LM3401 Quad Amplifiers ............... , ....... .' ...... . LM3011 Wide Band Amplifier ............ , ............ , ... , .................. , . , . , . , , LM4250/LM4250C Precision Reference, "', '.' "., , ",., ,,',.,.,., ", .. , ,.', .,. " Power Amplifiers LM377 Dual 2 Watt Audio Amplifier. , , . , , , . , , , , , , , , , , , , , . , , , , • , .. ; , , ; , , . , , , . , . , . , , LM378 Dual4 Watt Audio Amplifier, , . , , , ... , . , : , . , .. ; .. , , " . , .. , .., .. , ; .. , , ... , , . , . , LM3379 Dual 6 Watt Audio Amplifier, , , . , , . , . , , , , , ,'. " ..., " , , .. , . , , , , . , , , , . , , , .... , LM380 Audio Power Amplifier, , , . , , , .. , ; , . , , .. , , , . , . , , , , , , , , . , , , . , , , , . , , , .. , , , . , , LM383/LM383A 8 Watt Audio Power Amplifier .. " , , , . , , , , " , , , , , , . " , , , . , , , .. , , , , , , LM384 5 Watt Audio Power Amplifier ".,',.,',.,',." .. ,.".,.,',.,"", ... ".,,', LM386 Low Voltage Audio Power Amplifier. , , , . , . , , , . , , .. , , , , . , ,', : , , , , , . , , ; .. " . , , LM388 1,5 Watt Audio Power Amplifier, .. , ~ , ; .. , . , . , . , , , , , , , , ... , . , . , , .. , , .. , , , . , , LM389 Low Voltage Audio Power Amplifier with NPN Transistor Array. , , , , , .. , , ....... ' , 'LM390 1 Watt Battery Operated Audio Power Amplifier ............. : .... : .......... . LM1877 Dual Power Audio Amplifier .............................................. . LM1895/LM2895 Audio Power Amplifier ..... ; ..•....................•............ LM1896/LM2896 Dual Power AudiO Amplifier ...................................... . LM2002/LM2002A 8 Watt Audio Power Amplifier ...................... '............ . LM2877 Dual 4 Watt Power Audio Amplifier. ....................................... . LM2878 Dual 5 Watt Power Audio Amplifier ....................................... . LM13080 Programmable Power Op Amp ......................................... . TDA2003 Audio Power Amplifier ....•............. ; ............ :., .. : ........... . ' Special Amplifiers LH0002/LH0002C Current Amplifier.'... : ........................................ . . LH004/LH004C HighVoltage Operational Amplifier; .......... , , . , , , , . , , ... , , ... " . : . LH211 0/LH221 0/LH231 0 Dual Voltage Follower, ., . , , . , , . , , . , . , ...... , , , . , .. , , ... . LM102/LM202/LM302 Voltage Followers ,~.; ........ " .. ,." , ... ".: ,,',.,, , ,. '" ,. LM110/LM210/LM310 Voltage Follower, "'" , .. ,', ... " " . ,., .. ,. , ,: ,' .. , .. , ... , . LM3080/LM3080A Operational Transconductance Amplifier, , . , .', .... , , " , . , . , , , , .' , , LM13600/LM13600AlLM11600A Dual Operational Transconductance Amplifier with linearizing Diodes and Buffers. , , ... , . , • , , ... , . , ......... : ; : ..... " . , , : , , , . , . , , ... . LM13700/LM13700AlLM11700A Dual Operational Transconductance Amplifier with Linearizing Diodes and Buffers. , , , .. , ... , ... , ..•.. " , .' ... , : , ... , , .. , ;, . , , , ....... S-8 3-268 3-270 10-216 3-279 10-9 10-14 10-18 10-22 10-32 10-36 , 10-40 10-47 10-52 10-59 10-167 10-179 10-184 10-200 10-204 10-210 3-284 10-281 3-291 3-296 3-401 3-135 3-154 9-148 10-242 10-248 Table of Contents (Continued) Video Amplifiers LM159/LM359 Dual, High Speed, Programmable Current Mode (Norton) Amplifiers. . . . . LM733/LM733C Differential Video Amp.. .. ............ .. .... . ... . ... ....... .... .. 3-226 9-54 SECTION 2 - COMPARATORS Combined Function Comparators LM1801 Smoke Detector ....................................................... . Voltage Comparators LF111 ILF211 ILF311 Voltage Comparators ...................................... . LH2111 ILH2211 ILH2311 Dual Voltage Comparator ............................... . LM106/LM206/LM306 Voltage Comparator .... , ................................. . LM111 ILM211 Voltage Comparator ............................................. . LM119/LM219/LM319 High Speed Dual Comparator .............................. . LM139/239/339, LM139A1239A/339A, LM2901, LM3302 Low Power Low Offset. Voltage Quad Comparators ..................................................... . LM160/LM260/LM360 High Speed Differential Comparator .... " ................ '" LM161 ILM261 ILM361 High Speed Differential Comparators ....................... . LM192/LM292/LM392, LM2924 Lo~ Power Operational AmplifierlVoltage Comparator. LM193/LM293/LM393, LM193A/LM293A1LM393A, LM2903 Low Power Low Offset· Voltage Dual Comparators ..................................................... . LM311 Voltage Comparator .................................................... . LM710/LM710C Voltage Comparator ............................................ . LM711 ILM711 C Dual Comparator ............................................... . LM1514/LM1414 Dual Differential Voltage Comparator ............................ . *LP165/LP365 Micropower Programmable Quad Comparator .................... . *LP311 Voltage Comparator ........................................ : .......... . *LP339 Ultra Low Power Quad Comparator ..................................... ~ 9-73 5-5 5-11 5-13 5-16 5-22 5-27 .5-35 5-38 3-242 5-41 5-48 5-56 5-59 5-62 82-1 82-9 82-11 SECTION 3 - VOLTAGE REGULATORS Dual Tracking LM125/LM325/LM325A, LM126/LM326 Voltage Regulators ....................... . 1-51 *LM2935 Low Dropout [)ual Regulator .......................................... . 83-13 Multi-Tracking LM104/LM204/LM304 Negative Regulator ....................................... . LM05/LM205/LM305/LM305A, LM376 Voltage Regulators ........................ . LM723/LM723C Voltage Regulator .................................. ; '........... . Programmable Regulators . LH0075 Positive Precision Programmable Regulator ............ :................... . LH0076 Negative Precision Programmable Regulator .............•................. Switch Mode LH1605/LH1605C 5 Amp High Efficiency Switching Regulator ...................... . LM1524/LM2524/LM3524 Regulating Pulse Width Modulator ...................... . 3-Terminal LM78XX Series Voltag,e Regulators ............................................ , .. LM78LXX Series 3-Terminal Positive Regulators .................................. . LM78MXX Series 3-Terminal Positive Regulators .................................. . LM79LXX Series 3-Terminal Negative Regulators ................................. . LM79LXXAC Series 3-Terminal Negative Regulators ............................... . LM79MXX Series 3-Terminal Negative Regulators ......................... '........ . LM1 09/LM209/LM309 5 Volt Regulator ...........................•............... LM1171LM217/LM317 3-Terminal Adjustable Regulator ........................... . LM117HVILM217HVILM317HV 3-Terminal Adjustable Regulator ................... . LM120 Series 3-Terminal Negative Regulators .................................... . 8-9 1-10 1-13 ,1-143 2-9 2-14 1-163 1-148 1-181 1-184 1-190 1-193 1-198 1-202 1-18 1-23 1-31 1-39 Table of Contents (Continued) LM123/LM223/LM323 5 Volt Positive Regulator................... ... ........ . ... . LM137/LM3271LM337 3-Terminal Adjustable Negative Regulators .............•..... ' LM137HV/LM237HV/LM337HV 3- Terminal Adjustable Negative Regulators (High Voltage) .............•.................•...................................... LM138/LM238/LM338 5 Amp Adjustable Power Regulators. . . . . . . . . . . . . . . . . . . . . . . . . LM140AlLM140/LM340AlLM340 Series 3-Terminal Positive Regulators... .....•... . . LM140LlLM340L Series 3-Terminal Positive Regulators ..............,........ ..... . LM145/LM345 Negative Three Amp Regulator.. . . . . . . . .• .. .. . .. ... .. .. . . .. . . . .. . . . LM150/LM250/LM350 3 Amp Adjustable Power Regulator..................... .... . LM196/LM39610 Amp Adjustable Voltage Regulator... .....•................ . .... . LM317L 3-Terminal Adjustable Regulator............... ............•....... . ... . . LM320LlLM320ML Series 3-Terminal Negative Regulators................ ..... .... . LM330 3-Terminal Positive Regulator........... .....................•••.... . .... . LM337L 3-Terminal Adjustable Regulator......... ..........•...•.•........... ... . LM341 Series 3-Terminal Positive Regulators ..................................•. ; '. LM342 Series 3-Terminal Positive Regulators.. .... ...... ..................... .... . LM2930 3-Terminal Positive Regulator.......................................... LM2931 Series Low Dropout Regulators ........ ; ... ; ........................... ' 1-47 1-58 1-63 1-68 1-76 1-84 1-87 1-91 1-99 1-111 1-122 1-128 1-134 1-136 1-139 S 3-1 S 3-7 SECTION 4 - VOLTAGE REFERENCES Adjustable References *LM185/LM285/LM385 AdJustable Mlcropower Voltage Reference ............... . Fixed References LM103 Reference Diode ......................................................... . LM113/LM313 Reference Diode ............................................... .. LM 134/LM234/LM334 3-Terminal Adjustable Current Sources ..........•..•......... LM136/LM236/LM336 2.5V Reference Diode .....•........•..•..................• LM136-5.0/LM236-5.0/LM336-5.0 5.0V Reference Diode .......................... . *LM168/LM268/LM368 Precision Voltage Reference ............................ . LM185-1.2/LM285-1.2/LM385-1.2 Mlcropower Voltage Reference Diode ......... . LM185-2.5/LM285-2.5/LM385-2.5 Micropower Voltage Reference Diode ......... . *LM199AH-20, LM299AH-20, LM399AH-50 Ultra-Stable References ............ : .. . Precision References LH0070 Series Precision BCD Buffered Reference ................................ . LH0071 Series Precision Binary Buffered Reference .. : ......•............ : ....... . LM129/LM329 Precision Reference .............................................. . LM199/LM299/LM399 Precision Reference ...........................•........... LM199A1LM299A1LM399A Precision Reference ................................•.. LM3999 Precision Reference ....•..•............•......................•...•.... S4-8 2-19 2-22 9-17 2-30 2-36 S4-1 S4-15 S4-21 S4-26 2-5 2-5 2-25 2-54 2-60 2-63 SECTION 5 - CONVERTERS Analog to Digital AD75201 AD7530 10-Bit, AD7521 1AD7531 12-Bit Binary Multiplying DI A Converters. . . . ADB1200 12-Bit Binary AID Building Block ................•........... ~...... ..... ADC0800 8-Bit AID Converter ......................... :... . . .. . . . . . . .. . . . . . • . .. . . ADC0801, ADC0802, ADC0803, ADC0804, ADC0805 8-Bit ,...p Compatible AID Converters . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . ..• . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC0808, ADC0809 8-Bit ,...p Compatible AID Converters with 8-Channel Multiplexer. . • ADC0816, ADC0817 8-Bit ,...p Compatible AID .Converters with 16-Channel Multiplexer .................................................... , .............. ' *ADC0820 8-Bit High Speed ,...p Compatible AID Converter with Track/Hold Function .......................................•.......................'...... * ADC0829 ,...p Compatible 8-Blt AID with 11 Channel MUX/Dlgitallnput ; . . . . . . .. . . . 8-10 8-8 8-10 8-17 8-28 8-60 S 5-1 S 5-12 S 5-28 Table of Contents (Continued) * ADC0831, ADC0832, ADC0834, ADC0838 8-Bit Serial 1/0 AID Converters with Multiplexer Options ........•..•............................................... ADC0833 8-Bit Serial 1/0 AID Converter with 4-Channel Multiplexer ............. . * ADC0844 8 Bit p.P Compatible AID Converter with 4-Channel Multiplexer ........ . ADC1001, ADC1021 10-Bit p.P Compatible AID Converters ......................... . ADC10S0, ADC12S0 12-Bit Successive Approximation AID Converters .............. . ADC1210, ADC1211 12-Bit CMOS AID Converters .............................. . Digital to Analog DACOSOO, DACOS01, DACOS02 S-Bit Digital to Analog Converters ................... . DACOSOB, DACOS07, DACOS06 S-Bit DI A Converters .............................. . DAC0830, DAC0831, DAC0832 MICRO-DAC 8-Bit p.P Compatible, Double-Buffered D to A Converters ........................•.................................... DAC1 000/1/2 and DAC1006171S MICRO-DAC p.P Compatible, Double Buffered D to A Converters ............................................•....................... DAC1020, DAC1 021, DAC1022 1O-Bit Binary Multiplying DI A Converters ............. . DAC1220, DAC1221, DAC1222 12-Bit Binary Multiplying DI A Converters ............. . DAC1200, DAC1201 12-Bit Digital-to-Analog Converters ........................... . DAC120S, DAC1209, DAC1210, DAC1230, DAC1231, DAC1232 MICRO-DAC 12-Bit, p.P Compatible, Double-Buffered D to A Converters ................................... . DAC121~, DAC1219 12-Bit Binary Multiplying DI A Converter ....................... . *DAC1265A, DAC1265 High Speed 12-Bit DI A Converter with Reference .......... . *DAC1266A, DAC1266 High Speed 12-Bit D/A Converter ......................... . DAC12S0A, DAC12S0 12-Bit Digital-to-Analog Converters .......................... . DAC12S0A-1, DAC12S0-1 12-Bit Digital-to-Analog Converters ...................... . DAC12S5A, DAC12S5 (DACS5, DACS7) 12-Bit Digital-to-Analog Converters .......... . LH0091 True RMS to DC Converter ............................................. . Special (Converters) LH0094 Multifunction Converter ................................................. . LM131A/LM131, LM231A1LM231, LM331A/LM331 Precision Voltage-to-Frequency Converters ...•............................................................... LM2907, LM2917 Frequency to Voltage Converter ................................ . S5-36 S5-60 S5-78 S-89 S-97 S5-93 S-11S 8-126 S 5-104 8-151 8-173 8-173 8-183 8-189 8-204 S 5-120 S 5-129 8-208 8-216 S-220 9-291 9-296 S 5-137 9-135 SECTION 6 - ANALOG SWITCHES Multiplexers LF1150S/LF1350S S-Channel Analog Multiplexer ................................. . LF11509/LF13509 4-Channel Differential Analog Multiplexer ....................... . *LM1037 Dual Four-Channel Analog Switch ...........................•.......... LM1038 Dual Four-Channel Analog Switch ..................................... . Standard Analog Switches AH5009, AH501 0, AH5011, AH5012 Monolithic Analog Current Switches ............. . * AH5020C Monolithic Analog Current Switches ................................. . LF11201/LF13201 4 Normally Closed Switches ................................... . LF11202/LF13202 4 Normally Open Switches .................................... . LF11331/LF13331 4 Normally Open Switches with Disable ......................... . LF11332/LF13332 4 Normally Closed Switches with Disable ....................... . LF11333/LF133332 Normally Closed Switches and 2 Normally Open Switches with Disable .....................................................................•. LF13300 Integrating AI D Analog Eluilding Blocks ......•............................ 6-27 6-27 S6-9 S6-15 6-5 S6-1 6-17 6-17 6-17 6-17 6-17 8-233 SECTION 7 - SAMPLE AND HOLD Standard Sample and Hold LF19S/LF29S/LF39S, LF19SA/LF398A Monolithic Sample and Hold Circuits.......... LH0023/LH0023C; LH0043/LH0043C Sample and Hold Circuits. .. ........ ... ....... LH0053/LH0053C High Speed Sample and Hold Amplifier.......................... 5-11 7-5 7-14 7-22 Table of Contents (Continued) SECTION 8 - SENSORS Fluid LM903 Fluid Level Detector ..................................................... LM 1830 Fluid Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature 9-58 9-88 LM34/LM34A, LM34C/LM34CA, LM34D Precision Fahrenheit Temperature Sensors *LM35, LM35A, LM35C, LM35CA, LM35D Precision Centigrade Temperature Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S 8-1 LM135/LM235/LM335, LM135A1-LM235A1LM335A Precision Temperature Sensors. .. LM3911 Temperature Controller....... .. .... ......... .. ....................... .. 9-25 9-156 S 8-2 SECTION 9 - FILTERS Monolithic *MF4 4th Order Switched CapaCitor Butterworth Lowpass Filter .................. . *MF5 Universal Monolithic Switched Capacitor Filter ....... , .................... . MF6 6th Order Switched Capacitor Butterworth Lowpass Filter, ................. . MF10 Universal Monolithic Dual Switched CapaCitor Filter ....................... . TP3052/TP3053/TP3054/TP3057 Monolithic, Serial Interface CMOS CODEC/ FILTER'Family ................................................ ; .............. . *TP3064/TP3067 Monolithic Serial Interface CMOS CODEC/FILTER Combos ...... . S9-1 S9-8 S9-9 S9-17 S9-28 S9-41 SECTION 10 - BUILDING BLOCKS Other Building Blocks *LF13006, LF13007 Digital Gain Set.. .. .... ... .. ........ . ... .. ................. .. *LM1851 Ground Fault Interrupter.................. .... ..... ..... ...... .... ..... Phase Locked Loops LM565/LM565C Phase Locked Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LM1391 Phase Locked Loop Block. . . . . . • . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . Timers LM122/LM222/LM322, LM2905/LM3905 Precision Timers. .. .............. ......... LM555/LM555C Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . LM556/LM556C Dual Timer ........ : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tone Decoders LM567/LM567C Tone Decoder .... : .........'. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Controlled Oscillators LM566/LM566C Voltage Controlled Oscillator ...... ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S 10-1 S 10-8 9-42 10-104 9-5 9-33 9-39 9-50 9-47 SECTION 11 - MOTOR CONTROLLERS Tachometers LM1014 Motor Speed Regulator ....................................... ,... .. . .. S 11-1 SECTION 12 - CONSUMER CIRCUITS Audio LM381 / LM381 A Low Noise Dual Preamplifier ..................................... . LM382 Low Noise Dual Preamplifier ................................ ; ............ . LM387/LM387A Low Noise Dual Preamplifier ..................................... . LM391 Audio Power Circuits .................................................... . LM1035 Dual DC Operated TonelVolume/Balance Circuit .......................... . 10-26 10-29 10-44 10-64 S 12-1 10-75 *LM1036 Dual DC Operated Tone/Volume/Balance Circuit ....................... . S 12-9 LM1037 Dual Four-Channel Analog Switch ..................•..................... 10-80 *LM832 Dynamic Noise Reduction System DNR ................................. .. *LM1040 Dual DC Operated Tone/Volume/Balance Circuit with Stereo Enhancement Facility ........................................................ . S 12-18 S-12 Table of Contents (Continued) LM1112A1LM1112B/LM1112C Dolby B-Type Noise Reduction Processor... .......... 10-88 *LM1121A/LM1121B/LM1121C Dolby B-Type Noise Reduction Processor with DC Switching .................................................................... S 12-28 LM1131A1LM1131B/LM1131C Dual Dolby B-Type Noise Reduction Processor........ 10-97 LM 1818 Electronically Switched Audio Tape System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-113 LM1837 Low Noise Preamplifier for Auto Reversing Tape Playback Systems...... ..... 10-122 *LM1875 20 Watt Power Audio Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. S 12-58 LM1894 Dynamic Noise Reduction System DNR ..... .................... .......... 10-172 LM1897 Low Noise Preamplifier for Tape Playback System...... ..... .. . .. ... ....... 10-191 *LM2879 Dual9-Watt Audio Amplifier . ........................................... S 12-105 *LMC835 Digital Controlled Graphic Equalizer ............. ....................... S 12-126 Automotive ' LM1812 Ultrasonic Transceiver ................................................. . 9-77 LM 1815 Adaptive Sense Amplifier ............................................... . 9-85 *LM1819 Air-Core Meter Driver .. ............................................... . S 12-31 *LM1949 Injector Drive Controller .. ............................................ . S 12-87 *LM1964 Sensor Interface Amplifier . ....................,....................... . S 12-95 *LM2005 20-Watt Automotive Power Amplifier . ................................. . S 12-99 Displays LM1017 4-Bit Binary 7-Segment Decoder/Driver ........•.......................... 11-3 LM3909 LED Flasher/Oscillator ................................................. . 9-152 LM3914 Dot/Bar Display Driver ................................................. . 9-163 LM3915 Dot/Bar Display Driver ................................................. . 9-177 9-193, LM3916 Dot/Bar Display Driver ................................................. . Other LM1851 Ground Fault Interrupter ................................................ . 9-94 Radio LM1310 Phase-Locked Loop FM Stereo Demodulator.... ......... .. . .... .... . ..... 10-102 LM1596/LM1496 Balanced Modulator Demodulator. ..................... ... ....... 10-107 LM 1800 Phase-Locked Loop FM Stereo Demodulator .............................. 10-111 *LM1863 AM Radio System for Electrically Tuned Radios. . . . . . . . . . . . . . . . . . . . . . . .. S 12-46 LM1865/LM1965 Advanced FM IF System........................................ 10-132 LM1866 Low Voltage AM/FM Receiver . . . . . . . . . . . . . . . . . . . . . .. . • . . . . . . . . . . . . . . . . . . 10-146 LM1868 AM/FM Radio System...... ....... ...... . ............ . .. ......... ...... 10-153 LM1870 Stereo Demodulator with Blend ....................................... ;.. 10-161 LM1871 RC Encoder/Transmitter.. .. .. ......... .. ..... ........ . ... .. ............ 9-101 LM1872 Radio Control Receiver/Decoder. ......... ... ...... ........ .............. 9-116 LM3075 FM Detector/Limiter and Audio Preamplifier ............................... 10-218 LM3089 FM Receiver IF System ................................................. 10-220 LM3189 FM Receiver IF System.. . .... ................ .. .. ..... ... .. ....... ..... 10-224 *LM3361A Low Voltage/Power Narrow Band FM IF System ....................... S 12-121 LM3820 AM Radio System...................................................... 10-231 LM4500A High Fidelity FM Stereo Blend Demodulator .............................. '10-235 TBA120S IF Amplifier and Detector... .. .... . ...................... .. .. ..... .. .... 10-274 TBA120U/TBA120T IF amplifier and Detector... .... ................... ........... 10-277 Remote Controllers *LM1893 Carrier-Current Transceiver. . .. . . . . . . . .. . . . . . .. . . . . . . . . . . . . . . . . . . . ... .. S 12-67 Video LM909 Remote Control Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . • . . . . . . . 9-64 LM1 019N Digital Tuning Station Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 LM1821S ..................................................................... obsolete *LM1823 Video iF Amplifier/PLL Detector System ................................ S 12-39 S-13 Table of Contents (ContinU9d) LM1828, LM1848 Color Television Chroma Demodulator................ ... ......... 11-13 11-16 LM1880 No-Holds Vertical/Horizontal ..................... .-...................... *LM1884 TV Stereo Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. S 12-64 LM1886 TV Video Matrix D to A . .. . . .. .. .. . . .. .. . .. .. . . . . . . . . . . . . . . .. . . . . . . . . . .. . 11-23 11-28 LM1889 TV Video Modulator .................................................... 11-37 LM2808 Monolithic TV Sound System ............ ; .. . . . . . .. . .. . .. . .. .. .. .. . .. . . . . . *LM2889 TV Video Modulator ................................................... S 12-112 LM3064 Television Automatic Fine Tuning. . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-41 TBA440C ...................................................................... obsolete TBA510 ..•................•................................................... obsolete TBA530 .......•.....•....•..•...................................•............ , obsolete TBA540 •...•........................•.............................•........... obsolete TBA560C ..................................................................... obsolete TBA920/TBA920S .........•................................................... obsolete TBA950-2 Television Signal Processing Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-63 TBA970 ................................................. '..•...............•.. , obsolete TBA990 ...............•.......................•............................... obsolete 11-72 TDA440 Video IF Amplifier ...................................................... TDA2522/TDA2523 ............................................................ obsolete TDA2530 ..•..........••....... ~ •. " ...•.......•...................• '. . . . . . . . . .. obsolete TDA2540 •............. :...................................................... obsolete TDA2541 .......................•.................••..•...........•..•........ obsolete TDA2560 •..•.....................................................•.•......••. obsolete TDA2591/TDA2593 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. obsolete TDA3500 .......•..••..•..........................................•........... obsolete TDA3501 ..................................................................... obsolete SECTION 13· TELECOMMUNICATIONS CIRCUITS Switching and Transmission TP3020/TP302G-lITP3021/TP3021-1 Monolithic CODECs ....................... . S 13-1 TP3040/TP3040A PCM Monolithic Filter .•........•............................... 9-238 9-245 TP3051, TP3056 Monolithic Parallel Interface CODEC/Filter Family ................. . TP3110, TP3120 Digital Line Interface Controllers (DLlC) .•.......................... 9-249 TP5116A, TP5117A, TP5156A Monolithic CODECs.; ............................. .. 9-223 Teleptione Components TP5087/TP5087A, TP5092/TP5092A, TP5094/TP5094A DTMF (Touch-Tone®) Generators ••..•............................ : ................................•. ' 9-250 TP5088 DTMF Generator for Binary Input Data ................................ , ... . 9-254 TP5393, TP5394, TP53143, TP53144 Pushbutton Pulse Dialer Circuits ............... . 9-271 9-266 TP5395, TP53125 DTMF (Touch-Tone®) Generators, ............................. . 9-281 TP5600, TP5605, TP5610, TP5615 Ten-Number Repertory Pulse Dialers ............. . 9-287 TP5650, TP5660 Ten-Number Repertory DTMF Generators ........................ . *TP5700/TP5700-lITP5710 Telephone Speech Circuits .......................... . S 13-10 TP9151, TP9152, TP9156, TP9158 Push Button Pulse Dialer Circuits with Redial ...... , 9-255 TP50981 ITP50981 A, TP50982/TP50982A, TP50985/TP50985A Push Button Pulse Dialer Circuits .......................•.................................... ',' .... 9-260 TP53130 DTMF (Touch-Tone®) Generator ..............................•......... 9-276 *TP53190 Push-Button Pulse Dialer ............................................. . S 13-17 SECTION 14 • SPEECH Digitalker Speech Synthesis Dn 000 Digitalker Speech Synthesis Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DT1 050/DT1 053 Digitalker Standard Vocabulary Kit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 13-7 13-14 Table of Contents (Continued) DT1 051/DT1 054 Digitalker Speech Evaluation Kit. ................................ . DT1 052/DT1 055 Digitalker Basic Numbers Kit .................................... . DT1 056/DT1 057 Digitalker Standard Vocabulary Kit ............................... . 13-22 13-24 13-26 DTSWSOO Digltalker Vocabulary Selection System DVSS . ....................... . S 14-1 MMS4104 Digitalker Speech Synthesis System . ................................ . S 14-S *TP18 Implementation of a Speech Synthesizer . ................................ . S 14-11 AN252 ....................................................................... . 13-43 SECTION 15 - SPECIAL ANALOG FUNCTIONS LM194/LM394 Supermatch Pair ................................................ . LM195/LM295/LM395 .....•................................................... LM3045, LM3046, LM3086 Transistor Arrays ..................................... . LM3146 High Voltage Transistor Array ......... ; ................................. . 12-4 12-10 12-18 12-23 LP39S Ultra Reliable Power Transistor . ........................................ . S 1S-1 LB-54 Circuit for Evaluation of Custom Vocabulary EPROM Prototype Set ............ . 13-41 SECTION 16 - PHYSICAL DIMENSIONS Physical Dimensions· . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S-15 16-1 Alphanumerical Index AD7520 10-Bit Binary Multiplying DI A Converter •......•.........•.................. 8-8 AD7521 12-Bit Binary Multiplying DI A Converter ................................... . 8-8 AD7530 10-Bit Binary Multiplying DI A Converter .................................•.. 8-8 AD7531 12-Bit Binary Multiplying DI A Converter .•........•......................... 8-8 .ADB1200 12-Bit Binary AID Building Block .........•..•.....•..... : ..............•• 8-10 ADC0800 '8-Bit AID Converter ...............••......•........•................... 8,-17 ADC0801 8-Bit "",p Compatible AID Converter ...•...........•.......•............•. 8-28 ADC0802 8-Bit "",p Compatible AID Converter .........•............................ 8-28 ADC0803 8-Bit "",p Compatible AID Converter ........••.......................•.. , . 8-28 ADC0804 8-Bit "",p Compatible AID Converter ...•....................•............• 8-28 ADC0805 8-Bit "",p Compatible AID Converter ..........•........................•.. 8-28 .ADC0808 8-Bit "",p Compatible AID Converter with 8-Channel Multiplexer ............•• 8-60 ADC0809 8-Bit "",p Compatible AID Converter with 8-Channel Multiplexer ............. . 8-60 ADC0816 8-Bit "",p Compatible AID Converter with 16-Channel Multiplexer ......•....•. S5-1 S5-1 ADC0817 8-Bit "",p Compatible AID Converter with 16-Channel Multiplexer ....•........ ADC0820 8-Bit High Speed "",p Compatible AID Converter with Track/Hold Function ... . S5-12 ADC0829 "",p Compatible 8-Bit AID with 11-Channel MUX/Digitallnput ............... . S5-28 ADC0831 (COP 431) 8-Bit Serial 110 AID Converters with Multiplexer Options ......... . S5-36 ADC0832 (COP 432) 8-Bit Serial 1/0 AID Converters with Multiplexer Options ......... . S5-36 ADC0833 8-Bit Serial 1/0 AID Converter with 4-Channel Multiplexer .....•......•...... S5-60 ADC0834 (COP 434) 8-Bit Serial 110 AID Converters with Multiplexer Options ......... . S5-36 ADC0838 (COP 438) 8-Bit Ser~alllO AID Converters with ,Multiplexer Options ......... . S5-36 ADC0844 8-Bit "",p Compatible AID Converters with 4-channel Multiplexer ............ . S 5-78 ADC100110-Bit "",p Compatible AID Converters ................................... . 8-89 ADC102110-Bit "",p Compatible AID Converters ................................... . 8-89 8-97 ADC1080 12-Bit Successive Approximation AID Converter .....•..•....•............. ADC1210 12-Bit CMOS AID Converter ................. '.......................... . S5-93 S 5-93 ADC1211 12-Bit CMOS AID Converter ........................................... . ADC1280 12-Bit Successive Approximation AID Converter ......... : ................ . 8"97 AH5009 Monolithic Analog Current Switch .•....•................................•. 6-5 AH5010 Monolithic Analog Current Switch ........................................ . 6-5 _ AH50t1 Monolithic Analog Current Switch ........................................ . 6-5 AH5012 Monolithic Analog Current Switch ........................................ . 6-5 AH5020C Monolithic Analog Current Switch •....................................... S 6-1 AN-252 Speech Synthesis ...............•.....•.................................. 13-43 BLX-281 Speech Synthesis Expansion Module ...........................•......... 13-3 DAC0800 8-Bit Digital-to-Analog Converter ........................................ . 8-118 DAC0801 8-Bit Digital-to-Analog Converter ........................................ . 8-118 8-118 DAC0802 8-Bit Digital-to-Analog Converter .......... '............•.•............•... 8-126 DAC0806 8-Bit DI A Converter .................................•.................. 8-126 DAC0807 8-Bit DI A Converter ................................................... . 8-126 DAC0808 8-Bit DI A Converter .......•.........................................•.. DAC0830 MICRO-DACTM 8-Bit "",p Compatible Double-Buffered D to A Converter ...... . S 5-104 DAC0831 MICRO-DACTM 8-Bit "",p Compatible Double-Buffered D to A Converter ...... . S 5-104 DAC0832 MICRO-DACTM 8-Bit "",p Compatible Double-Buffered D to A Converter ...... . S 5-104 8-151 DAC1000 10-Bit, p.P Compatible, Double-Buffered D to A Converters ................. . 8-151 DAC1001 10-Bit, "",p Compatible, Double-Buffered D to A Converters ................. . 8-151 DAC1002 10-Bit, "",p Compatible, Double-Buffered D to A Converters ...............•.. 8-151 , DAC1006 10-Bit, "",p Compatible, Double-Buffered D to A Converters ...............•.. DAC1007 10-Bit, "",p Compatible, Double-BufferedD to A Converters ................. . 8-151 8-151 DAC1008 10-Bit, "",p Compatible, Double-Buffered D to A Converters ........ : .•....... DAC1020 10-Bit Binary Multiplying DI A Converter .................................. . 8-173 DAC102110-Bit Binary Multiplying D/A Converter .................................. . 8-173 5·16 Alphanumerical Index (Continued) DAC1022 10-Bit Binary Multiplying DI A Converter .................................. . 8-173 DAC1200 12-Bit (Binary) Digital-to-Analog Converter ............................... . 8-183 DAC1201 12-Bit (Binary) Digital-to-Analog Converter ........... ~ ................... . 8-183 DAC1208 MICRO-DACTM 12-Bit, ,..,p Compatible, Double-Buffered D to A Converter .... . 8-189 DAC1209 MICRO-DACTM 12-Bit, Compatible, Double-Buffered D to A Converter .... . 8-189 DAC1210 MICRO-DACTM 12-Bit, Compatible, Double-Buffered D to A Converter .... . 8-189 8-204 DAC121812-Bit Binary Multiplying D/A Converter .................................. . DAC1219 12-Bit Binary Multiplying DI A Converter .................................. . 8-204 DAC1220 12-Bit Binary Multiplying DI A Converter ................................. .. 8-173 DAC1221 12-Bit Binary Multiplying DI A Converter .................................. . 8-173 DAC1222 12-Bit Binary Multiplying DI A Converter ................................. .. 8-173 8-189 DAC1230 MICRO-DACTM 12-Bit, p.P Compatible, Double-Buffered D to A Converter .... . DAC1231 MICRO-DACTM 12-Bit, ,..,p Compatible, Double-Buffered D to A Converter .... . 8-189 8-189 Compatible, Double-Buffered D to A Converter.' •... DAC1232 MICRO-DACTM 12-Bit, DAC1265A Hi-Speed 12-Bit DI A Converter with Reference .......................... . S 5-120 DAC1265 Hi-Speed 12-Bit DI A Converter with Reference ...... '..................... . S 5-120 DAC1266A Hi-Speed 12-Bit DI A Converter ...................., .................... . S 5-129 DAC1266 Hi-Speed 12-Bit DI A Converter ......................................... . S 5-129 DAC1280 12-Bit Digital-to-Analog Converter ....................................... . 8-208 DAC1280A 12-Bit Digital-to-Analog Converter ..................................... . 8-208 DAC1280A-1 12-Bit Digital-to-Analog Converter .................................... . 8-216 8-216 DAC1280-1 12-Bit Digital-to-Analog Converter ..................................... . DAC1285 (DAC87) 12-Bit Digital-to-Analog Converter ..............................•. 8-220 8-220 DAC1285A (DAC85) 12-Bit Digital-to-Analog Converter .............................. . DM2502 Successive Approximation Register ................................ ; .... .. 8-228 DM2503 Successive Approximation Register .......................... , ........... .. 8-228 DM2504 Successive Approximation Register ..................................... .. 8-228 DT1000 DIGITALKERTM Speech Synthesis Evaluation Board ......... '............... . 13-7 Dn050 DIGITALKERTM Standard Vocabulary Kit .................................. . 13-14 DT1051 DIGITALKERTM Speech Evaluation Kit .................................... . 13-22 DT1052 DIGITALKERTM Basic Numbers Kit ...................................... .. . 13-28 DT1053 DIGITALKERTM Standard Vocabulary Kit ................................... ' 13"14 13-22 DT1054 DIGITALKERTM Speech Evaluation Kit .................................... . DT1055 DIGITALKERTM Basic Numbers Kit ....................................... . 13-24 DT1056 DIGITALKERTM Standard Vocabulary Kit .................................. . 13-26 Dn057 DIGITALKERTM Standard Vocabulary Kit .................................. . 13-26 DTSW500 DIGITALKERTM Vocabulary Selection System (DVSS) ..................... . S 14-1 LB-54 Circuit for Evaluation 'of Custom Vocabulary EPROM Prototype Set ............. . 13-41 5-5 LF111 Voltage Comparators· .......................................' ............... . 3-14 LF147 Wide Bandwidth Quad JFET Input Operational Amplifier ...................... . LF155 Series Monolithic JFET Input Operational Amplifiers .......................... . 3-22 3-22 LF156 Series Monolithic JFET Input Operational Amplifiers ...... : ................... . LF157 Series Monolithic JFET Input Operational Amplifiers ............. .' ............ . 3-22 LF198 Monolithic Sample and Hold Circuit ........................................ . 7-5 . 7-5 LF198A Monolithic Sample and Hold Circuit .................................. , .... . 5-5 LF211 Voltage Comparator ......................... : ............................ . 7-5 LF298 Monolithic Sample and Hold Circuit ........................................ . 5-5 LF311 Voltage Comparator ..................................................... . 3~14 LF347 Wide Bandwidth Quad JFET Input Operational Amplifier ...................... . LF351 Wide Bandwidth JFET Input Operational Amplifier ............................ . 3-35 3-42 LF353 Wide Bandwidth JFET Input Operational Amplifier ............................ . 7-5 LF398 Monolithic Sample and·Hold Circuit ........................................ . 7-5 LF398A Monolithic Sample and Hold Circuit ................. '...................... . ,..,p ,..,p ,..,p 5-17 Alphanumerical Index (ContinUed) LF400C Fast Settling JFET Input Operational Amplifier ..•........................... LF411 Low Offset, Low Drift JFET Input Operational Amplifier ................•....... LF411 A Low Offset, Low Drift JFET Input Operational Amplifier ..... " ........•....... LF412 Low Offset, Low Drift bual JFEt Input Operational Amplifier .............._..... . LF412A Low Offset, Low Drift Dual JFET Input Operational Amplifier ...•.............. LF441 Low Power JFET Input Operational Amplifier ••...•............•............•. LF441 A Low Power JFET Input Operational Amplifier .....•............•....•...••... LF442 Dual Low Power JFET Input Operational Amplifier ................•....•....... LF442A Dual Low Power JFET InpUt Operational Amplifier ....•...........•..•....... LF444 Quad Low Power JFET Input Operational Amplifier ....................•...•... LF444A Quad Low Power Jf:=Et Input Operational Amplifier •.........•.......•....... LF11201 4 Normally Closed Switches ............................................ . LF11202 4 Normally Open Switches .............................................. . LF11331 4 Normally Open Switches with DiSable .•....................•....••...... LF11332 4 Normally Closed Switches with Disable ................. : ............... . LF11333 2 Normally Closed Switches and 2 Normally Open Switches With Disable •..... LF11508 8-Channel Analog Multiplexer •..............•................•..........• LF11509 4-Channel Differential Analog Multiplexer ...................•......•.....•. LF13006 Digital Gain Set .....••...•........•.............•.•....•...•...•..•.... LF13007 Digital Gain Set ......•..•....•...........•.......... ~ ........•....•...• LF13201 4 Normally Closed Switches ... , ......................................•.. LF13202 4 Normally Open Switches ...........•................•.........•..•..•.• LF13300 Integrating AID Analog Building Block .•.................•..........•...... LF13331 4 Normally Open Switches with Disable .................................. . LF13332 4 Normally Closed Switches with Disable ......•..............•....•......• LF13333 2 Normally Closed Switches and 2 Normally Open Switches With Disable ..... . LF13508 8-Channel Analog Multiplexer •.. '" ..................................... . LF13509 4-Channel Differential Analog Multiplexer ......... ; .......•. , ..•........... LF13741 Monolithic JFET Input Operational Amplifier .......................•........ LH0002 Current Amplifier ........•..••.....................•.....•............... LH0002C Current Amplifier ....................................................... . LH0003 Wide Bandwidth Operational Amplifier .................................... . LH0003C Wide Bandwidth Operational Amplifier ..........•............•......•..•.. LH0004 Higll Voltage Operational Amplifier ...•.......................••.......•.•. LH0004C High Voltage Operational Amplifier .....•......•..•....•.................. LH0005 Operational Amplifier ................................................... . LH0005A Operational Amplifier ........................ .' ........................ .. LH0005C Operational Amplifier ...........•...-..•............................•.... LH0021 1.0 Amp Power Operational Amplifier ..•.......•.........•.......•........• LH0021 C 1.0 Amp Power Operational Amplifier ................................... .. LH0022 High Performance FET Op Amp .•............•.......................•.... LH0022C High Performance FET Op Amp .•........................................ LH0023 Sample and Hold Circuit ...•............•.....•.......................•... LH0023C Sample and Hold Circuit .••.•.•...................•............•.... ; ... LH0024 High Slew Rate Operational Ampiifier .....................•...............• LH0024C High Slew Rate Operational Amplifier ....................•......••....•... LH0032 Ultra Fast FET-Input Operational Amplifier ..................•............... LH0032A Ultra Fast FET-Input Operational Amplifier ......................•.••.••... LH0032AC Ultra Fast FET-Input Operational Amplifier ...................•..•......•. LH0032C Ultra Fast FET-Input Operationai Amplifier ......•.............•..•........ LH0033 Fast and Damn Fast Buffer Amplifiers ........•....•........................ LH0033A Fast and Damn Fast Buffer Amplifiers •......................•...•........ LH0033AC Fast and Damn Fast Buffer Amplifiers ; .... '............................. . 8-18 3-51 3-53 3-53 3-60 3-60 3-66 3-66 3-73 3-73 3-81 3-81 6-17 6-17 6-17 6-17 6-17 6-27 6-27 S 10-1 S 10-1 6-17 6-17 8-233 6-17 6-17 6-17 6-27 6-27 3-88 3-291 3-291 3-294 3-294 3-296 3-296 3-299 3-299 3-302 3-304 3-304 3-311 3-311 7-14 7-14 3-318 3-318 S 1-1 S 1-1 S 1-1 S 1-1 S 1-7 S 1-7 S 1-7 Alphanumerical Index (Continued) LH0033C Fast and Damn Fast Buffer Amplifiers ................................... . S 1-7 4-18 LH0036 Instrumentation Amplifier ................................................ . 4-18 LH0036C Instrumentation Amplifier .............................................. . LH0038 True Instrumentation Amplifier ........................................... . 4-26 LH0038C True Instrumentation Amplifier .......................................... . 4-26 LH0041 0.2 Amp Power Operational Amplifier ..................................... . 3-304 LH0041 C 0.2 Amp Power Operational Amplifier .................................... . 3-304 LH0042 Low Cost FET Op Amp .................................................. . 3-311 3-311 LH0042C Low Cost FET Op Amp ................................................ . 7-14 LH0043 Sample and Hold Circuit ................................................. . LH0043C Sample and Hold Circuit ............................................... . 7-14 LH0044 Series Precision Low Noise Operational Amplifiers .......................... . 3-338 3-344 LH0045 Two Wire Transmitter ....................................•............... LH0045C Two Wire Transmitter .................................................. . 3-344 3-311 LH0052 Precision FET Op Amp .................................................. . LH0052C Precision FET Op Amp ................................................ . 3-311 7-22 LH0053 High Speed Sample and Hold Amplifier ...................... ~ ............. . LH0053C High Speed Sample and Hold Amplifier .................................. . 7-22 LH0061 0.5 Amp Wide Band Operational Amplifier ................................. . 3-355 LH0061 C 0.5 Amp Wide Band Operational Amplifier ................................ . 3-355 3-358 LH0062 High Speed FET Operational Amplifier .................................... . 3-358 LH0062C High Speed FET Operational Amplifier .............................•...... LH0063 Fast and Damn Fast Buffers Amplifiers .................................... . S 1-7 LH0063C Fast and Damn Fast Buffers Amplifiers .................................. . S 1-7 LH0070 Series Precision BCD Buffered Reference ................................. . 2-5 LH0071 Series Precision Binary Buffered Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 2-5 LH0075 Positive Precision Programmable Regulator ................................ . 2-9 LH0076 Negative Precision Programmable Regulator ............................... . 2-14 LH0084 Digitally Programmable Gain Instrumentation Amplifier ...................... . 4-37 4-37 LH0084C Digitally Programmable Gain Instrumentation Amplifier ..................... . LH0086 Digitally-Programmable-Gain Amplifier .................................... . 3-364 LH0086C Digitally-Programmable-Gain Amplifier ................................... . 3-364 LH0091 True RMS to DC Converter .............................................. . 9-291 9-296 LH0094 Multifunction Converter ................................................. . LH0101 Power Operational Amplifier ............................................. . 3-371 LH0101A Power Operational Amplifier .. , .............. , .......................... . 3-371 3-371 LH0101AC Power Operational Amplifier ......................................... .. 3-371 LH01 01 C Power Operational Amplifier ........................................... .. LH0132 Ultra-Fast FET-Input Operational Amplifier ................................. . S 1-18 S 1-18 LH0132C Ultra-Fast FET-Input Operational Amplifier ............................... . LH1605 5 Amp. High Efficiency Switching Regulator ................................ . 1-163 1-163 . LH1605C 5 Amp. High Efficiency Switching Regulator .............................. . LH740A FET Input Operational Amplifier ....................................... : ... . 3-382 3-382 LH740AC FET Input Operational Amplifier ...................... '................... . 3-384 LH2011 Dual Operational Amplifiers .............................................. . 3-384 LH2011 B Dual Operational Amplifiers ............................................ . 3-384 LH2011 C Dual Operational Amplifiers ............................................ . 3-397 LH2101A Dual High Performance Op Amp ........................................ . 3-399 LH21 08 Dual Super Beta Op Amp ................................................ . .3-399 LH2108A Dual Super Beta Op Amp .............................................. . LH2110 Dual Voltage Follower ................................................... . 3-401 5-11 LH2111 Dual Voltage Comparator ................................................ . 3-397 LH2201 A Dual High Performance Op Amp ... ~ .................................... . 8-19 Alphanumerical Index (Continued) LH2208 Dual Super Beta Op Amp ........................•..•.•.....•............• LH2208A Dual Super Beta Op Amp ..•........................•...... : ........... . LH221 0 Dual Voltage Follower ......••........•....•.........•............•...... LH2211 Dual Voltage Comparator .......................•................. '....... . LH2301A Dual High Performance Op Amp ..•...................................... LH2308 Dual Super Beta Op Amp .•.........•...............••.........' .......... . LH2308A Dual Super Beta Op Amp .' .....•...•..•....•..•......................... LH231 0 Dual Voltage Follower .•.••....................•......................... LH2311 Dual Voltage Comparator ...•........•.................•..•............... LH24250 Dual Programmable Micropower Op Amp ................................. . LH24250C Dual Programmable Micropower Op Amp ............................... . LM10 Op Amp and Voltage Reference ......•...•.•..........•..................... LM10B(L) Op Amp and Voltage Reference .................•........ : ...•.........• LM10C(L) Op Amp and Voltage Reference ........ .' ..........•.... , ............... . LM11 Operational Amplifier ......................................•.•..•........... LM 11 A Precision Operational Amplifiers ....•.••. : ...........•..................... LM 11 AC Precision Operational Amplifiers ....................•..................... LM11 C Operational Amplifier .....•...•.................••........................ LM11 CL Operational Amplifier ..................•...•........................•.... LM34/LM34A, LM34C/LM34CA, LM34D Precision Fahrenheit Temperature Sensors .... LM35 Precision Centigrade Temperature Sensors ......•...................•........ LM35A Precision Centigrade Temperature Sensors ..................•.•.....•..•.... LM35C Precision Centigrade Temperature Sensors .•.•.•........................•.. LM35CA Precision Centigrade Temperature Sensors •.•......••........•............ LM35D Precision Centigrade Temperature Sensors ........................•........ LM101A Operational Amplifier ...........................................•.....•.. LM102 Voltage Follower .........•...............••....... : •....•................ LM103 Reference Diode .........•............•..•............................... LM104 Negative Regulator ..•....•......•.....•...... , .....••..................... LM105 Voltage Regulator ..........................•.... : .................•...... LM106 Voltage Comparator ....•..............\: ................................. . LM107 Operational Amplifier .................................................... . LM108 Operational Amplifier .....•........•.........................•............ LM108A Operational Amplifier ................................................... . LM109 5-Volt Regulator ...................................... '.' ..•............... LM110 Voltage Follower. " .. , ........................................•.•...•.... LM111 Voltage Comparator ...................•......•..•.................. '" .,. LM112 Operational Amplifier .•................................•...•.....•........ LM113 Reference Diode ..... '...................•...•...•........................ LM117 3-Terminal Adjustable Regulator ..............•...................•........ LM117HV High Voltage 3-Terminal Adjustable Regulator •............................ LM118 Operational Amplifier .................................................... . LM119 High Speed Dual Comparator •.............................•...•.....•..... LM120 Series 3-Terminal Negative Regulators ..................................... . LM,21 Precision Preamplifier ...........•......................................... LM121 A Precision Preamplifier .....•.•....•.••...•.•.•.......•.•.....•....•...... LM122 Precision Timer ................•.........•.•............................. LM123 3 Amp, 5 Volt Positive Regulator •.•.•.....•..••...•.•..•.•.•............... LM124 Low Power Quad Operational Amplifier •..••.•..•.•.•........................ LM124A Low Power Quad Operational Amplifier ..•...........•.•................... LM125 Voltage Regulator ..... : .•..•.•.•.•...•...............•.....•••.•......•.. LM126 Voltage Regulator •••.......•....••.••.•.•...••..•.....................•.. LM129 Precision Reference •••.•.•....•.....•...•........•.. , .•...•.•.•....•.....• S-2O 3-399 3-399 3-401 5-11 3-397 3-399 3-399 3-401 5-11 3-403 3-403 3-99 3-99 3-99 3-115 1-S-50 1-S-50 3-115 3-115 S8-1 S8-2 S8-2 S8-2 S8-2 S8-2 3-128 3-135 2,-19 ·1-10 1-13 5-13 3-140 3-144 3-149 1-.18 3-154 5-16 3-161 2-22 1-23 1-31 3-165 5-22 1-39 4-5 4-5 9-5 1-47 3-172 3-172 1-51 1-51 2-25 Alphanumerical Index (Continued) LM131 Precision Voltage-to-Frequency Converter ....................... , .......... . S 5-137 LM131A Precision VOltage-to-Frequency Converter ..................... , .......... . S 5-137 LM 134 3-Terminal Adjustable Current Source ...................................... . 9-17 LM135 Precision Temperature Sensor ............................................ . 9-25 LM135A Precision Temperature Sensor ........................................... . 9-25 LM136 2.5V Reference Diode ................................................... . 2-30 LM136-5.0 5.0V Reference Diode .............. ,.................................. . 2-36 1-58 LM137 3-Terminal Adjustable Negative Regulators ................................. . LM137HV 3-Terminal Adjustable Negative Regulator (High Voltage) .................. . 1-63 1-68 LM138 5 Amp Adjustable Power Regulators .........................•.............. LM139 Low Power Low Offset Voltage Quad Comparator ........................... . 5-27 LM139A Low Power Low Offset Voltage Quad Comparator .......................... . 5-27 LM 140 Series 3-Terminal Positive Regulators ...................................... . 1-76 1-76 LM140A Series 3-Terminal Positive Regulators .................................... . LM140L Series 3-Terminal Positive Regulators .................................... . 1-84 LM143 High Voltage Operational Amplifier .... , , ......................... ; ........ . 3-181 LM144 High Voltage, High Slew Rate Operational Amplifier .......................... . 3-188 1-87 LM145 Negative Three Amp Regulator ........................................... . LM146 Programmable Quad Operational Amplifier ................................. . 3-194 LM148 Series Quad 741 Op Amps ............................................... . 3-206 LM149 Series Quad 741 Op Amps .............................................. .. 3-206 LM150 3 Amp Adjustable Power Regulator ........................................ . 1-91 LM158 Low Power Dual Operational Amplifier, ..................................... . 3-216 3-216 LM158A Low Power Dual Operational Amplifier .................................... . LM159 Dual, High Speed, Programmable Current Mode (Norton) Amplifier ............. . 3-226 LM160 High Speed Differential Comparator ...................... ; ................ . 5-35 LM161 High Speed Differential Comparator ....................................... . 5-38 LM 163 Precision Instrumentation Amplifier .............................. '. ......... . S 1-24 S4-1 LM168 Precision Voltage Reference .............................................. . S4-8 LM185 Adjustable Micropower Voltage Reference ................................. . LM185-1.2 Micropower Voltage Reference Diode ........... " ...................... . S4-15 LM185-2.5 MicropowerVoltage Reference Diode .................................. . S4-21 3-242 LM 192 Low Power Operational Amplifier /voltage Comparator ..................' ..... . LM193 Low Power Low Offset Voltage Dual Comparator ........................... .. 5-41 5-41 LM193A Low Power Low Offset Voltage Dual Comparator ........................... . 12-4 LM194 Supermatch Pair ........................................................ . 12-10 LM195 Ultra Reliable Power Transistor .......................................... .. LM196 10 Amp Adjustable Voltage Regulator ...................................... . 1-99 2-54 LM199 Precision Reference ..................................................... . 2-60 LM199A Precision Reference ..................... '.................... ; ....... '... .. LM199AH-20, LM299AH-20, LM399AH-50 Ultra-Stable References .................. . S4-26 3-128 ~M201 A Operational Amplifier ................................................... . LM202 Voltage Follower ........................................................ . 3-135 LM204 Negative Regulator ...................................................... . 1-10 LM205 Voltage Regulator .... , .................................................. . 1-13 LM206 Voltage Comparator ..................................................... . 5-13 3-140 LM207 Operational Amplifier .................................................... . LM208 Operational Amplifier .................................................... . 3-144 LM208A Operational Amplifier ....... , ........................................... . 3-149 1-18 LM209 5-Volt Regulator .......................•...........•..................... 3-154 LM210 Voltage Follower ................................. : ...................... . LM211 Voltage Comparator ......................•..•............................ 5-16 3-161 LM212 Operational Amplifier .................................................... .. 8-21 Alphanumerical Index (Continued) LM216 Operational Amplifier .....•.•.....•..........•........•..•................ 3-246 LM216A Operational Amplifier ........•..•••.........•..•..............•.......... 3-246 LM217 3-Terminal Adjustable Regulator ...............................•.•........• 1-23 LM217HV High Voltage 3-Terminal Adjustable Regulator ............................ . 1-31 LM218 Operational Amplifier .•.............•..•................•............•.... 3-165 LM219 High Speed Dual Comparator ......•.....................•...•........•.... 5-22 LM221 Precision Preamplifier .•.......•..•..•..•........•......................... 4-5 LM221 A Precision Preamplifier ...•........•.•.........••............•..•......... 4-5 LM222 Precision Timer ......••..•.•....•.•.............•..........•............. 9-5 LM223 3 Amp, 5 Volt Positive Regulator ..•..............•.......•....•............ 1-47 LM224 Low Power Quad Operational Amplifier ......•..................•............ 3-172 LM224A Low Power Quad Operational Amplifier ....•...........•................... 3-172 LM231 Precision Voltage-to-Frequency Converter .•....................•......•..... S 5-137 LM231 A Precision Voltage-to-Frequency Converter ..................•.............. S 5-137 LM234 3-Terminal Adjustable Current Source .............•........ : .•..•........... 9-17 LM235 Precision Temperature Sensor ............•.........•......•.•............. 9-25 LM235A Precision Temperature Sensor .....•...................................... 9-25 LM236 2.5V Reference Diode •... ! • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 2-30 LM236-5.0 5.0V Reference Diode ............•..•.......•......................... 2-36 LM237 3-Terminal Adjustable Negative Regulator .................•.............•... 1-58 LM237HV 3-Terminal Adjustable Negative Regulator (High Voltage) .................. . 1-63 LM238 5 Amp Adjustable Power Regulator ...•........••.•.........•.••............ 1-68 LM239 Low Power Low Offset Voltage Quad Comparator ...........•...•......•..... 5-27 5-27 LM239A Low Power Low Offset Voltage Quad Comparator ...•..........•............ LM246 Programmable Quad Operational Amplifier ..............•......•............ 3-194 LM250 3 Amp Adjustable Power Regulator ............................•............ 1-91 LM258 Low Power Dual Operational Amplifier .........................•............ 3-216 LM258A Low Power Dual Operational Amplifier ........•. '..•...•... , ............... . 3-216 LM260 High Speed Differential Comparator ...........................•............ 5-35 LM261 High Speed Differential Comparator ...... : .......•.......................•. 5-38 LM268 Precision Voltage Reference •...•...•............•.•............•.......... S4-1 LM285 Adjustable Micropower Voltage Reference .•.•....•.................•....... S4-8 LM285-1.2 Micropower Voltage Reference Diode ...........•.............. : •....... S4-15 LM285-2.5 Micropower Voltage Reference Diode .....•...•..•.•.................... S4-21 LM292 Low Power Operational AmplifierlVoltage Comparator ....................... . 3-242 LM293 Low Power Low Offset Voltage Dual Comparator .........•...•..•...•........ 5-41 LM293A Low Power Low Offset Voltage Dual Comparator ..•..•...................... 5-41 LM295 Ultra Reliable Power Transistor .....................................•...... 12-10 LM299 Precision Reference .•.•.................................................. 2-54 LM299A Precision Reference ........•..........•.......•." .......•............... 2-60 LM301A Operational Amplifier, .........................•..........•............. ; 3-128 LM302 Voltage Follower ..............................................•........•. 3-135 LM304 Negative Regulator ....•.•...................... ; ..............•........•. 1-10 LM305 Voltage Regulator ............................•........•...•.............. 1-13 LM305A Voltage Regulator ...................................................... . 1-13 LM306 Voltage Comparator ...........•............................•............. 5-13 LM307 Operational Amplifier ............•........................................ 3-140 LM308 Operational Amplifier .................................................... . 3-144 LM308A Operational Amplifier ........................................•........... 3-149 LM308A-1 Operational Amplifier ................................................. . 3-149 3-149 LM308A-2 Operational Amplifier ................................................. . LM309 5-Volt Regulator .......................................................... . 1-18 LM310 Voltage Follower ........................................................ . 3-154 8-22 Alphanumerical Index (Continued) LM311 Voltage Comparator .............•........................................ 5-48 LM312 pperational Amplifier .................................................... . 3-161 LM313 Reference Diode ........................................................ . 2-22 LM316 Operational Amplifier .................................................... . 3-246 LM316A Operational Amplifier ..................................'................. . 3-246 LM317 3-Terminal Adjustable Regulator .......................................... . 1-23 1-31 LM317HV High Voltage 3-Terminal Adjustable Regulator ............................ . LM317L 3-Terminal Adjustable Regulator ...... , .................................. . 1-111 LM318 Operational Amplifier .......................................•...•......... 3-165 LM319 High Speed Dual Comparator ............................................. . 5-22 1-122 LM320L Series 3-Terminal Negative Regulators ...........................•......... LM320ML Series 3-Terminal Negative Regulators .................................. . 1-122 LM321 Precision Preamplifier ..................................................... . 4-5 LM321 A Precision Preamplifier .................................................. . 4-5 LM322 Precision Timer ..........•............................................... 9-5 LM323 3 Amp, 5 Volt Positive Regulator .......................................... . 1-47 3-172 LM324 Low Power Quad Operational Amplifier ..................................... . LM324A Low Power Quad Operational Amplifier ................................... . 3-172 LM325 Voltage Regulator ....................................................... . 1-51 LM325A Voltage Regulator ...................................................... . 1-51 LM326 Voltage Regulator ....................................................... . 1-51 LM329 Precision Reference ..................................................... . 2-25 LM330 3-Terminal Positive Regulator .......................•...•.................. 1-128 LM331 Precision Voltage-to-Frequency Converter .................................. . S 5-137 LM331 A Precision Voltage-to-Frequency Converter ................................ . S 5-137 9-17 LM334 3-Terminal Adjustable Current Source ...•................................... LM335 Precision Temperature Sensor ............................................ . 9-25 LM335A Precision Temperature Sensor ..........................................•. 9-25 LM336 2.5V Reference Diode ................................................... . 2-30 LM336-5.0 5.0V Reference Diode ................................................ . 2-36 LM337 3-Terminal Adjustable Negative Regulator .................................•. 1-58 LM337HC 3-Terminal Adjustable Negative Regulator (High Voltage) ...............•... 1-63 LM337L 3-Terminal Adjustable Regulator ......................................... . 1-134 LM338 5 Amp Adjustable Power Regulator ........................................ . 1-68 LM339 Low Power Low Offset Voltage Quad Comparator •..........•................ 5-27 LM339A Low Power Low Offset Voltage Quad Comparator .......................... . 5-27 LM340 Series 3-Terminal Positive Regulators ....................•.•................ 1-76 1-76 LM340A Series 3-Terminal Positive Regulators .................................... . 1-84 LM340L Series 3-Terminal Positive Regulators .................................... . LM341 Series 3-Terminal Positive Regulators ..•.................................... 1-136 LM342 Series 3-Terminal Positive Regulators .....................................•. 1-139 LM343 High Voltage Operational Amplifier ........................................ . 3-181 LM344 High Voltage, High Slew Rate Operational Amplifier .......................... . 3-188 LM345 Negative Three Amp Regulator ........................................... . 1-87 LM346 Programmable Quad Operational Amplifier ................................. . 1-194 1-91 LM350 3 Amp Adjustable Power Regulator ........................................ . 3-216 LM35~ Low Power Dual Operational Amplifier ..................................... . LM358A Low Power Dual Operational Amplifier ..............................•...... 3-216 LM359 Dual, High Speed, Programmable Current Mode (Norton) Amplifiers ............ . 3-226 LM360 High Speed Differential Comparator ....................................... . 5-35 LM361 High Speed Differential Comparator ...........•. '•.......................... 5-38 LM363 Precision Instrumentation Amplifier .•....................................... S 1-24 S 4-1 LM368 Precision Voltage Reference .............................................. . 5-23 Alphanumerical Index (Continued) LM376 Voltage Regulator ................................................. '....... . 1·13 LM377 Dual 2 Watt Audio Amplifier ...................................... : ....... ; . 10·9 LM378 Dual 4 Watt Audio Amplifier ...•...............•............................ 10·14 LM379 Dual 6 Watt Audio Amplifier ................................. ~ ............. . 10·18 LM380 Audio Power Amplifier ............................................ '....... . 10·22 LM381 Low Noise Dual Preamplifier .............................................. . 10"26 LM;381 A Low Noise Dual Preamplifier ........... , ..........•... ; ........•.......... 10·26 LM382 Low Noise Dual Preamplifier ....•.....•......... , ............. ; ...... '..... . 10·29 LM383 8 Watt Audio Power Amplifier ..............' ............................... . 10·32 LM383A 8 Watt Audio Power Amplifier .......................... ; ........ : ........ . 10·32 LM384 5 Watt Audio Power Amplifier ............. '.. '........ , ...................... ; 10·36 LM385 Adjustable Micropower Voltage Reference ....... '.......................... . 84·8 LM385·1.2 Micropower Voltage Reference Diode .•............................... ; . 84·15 LM385·2.5 Micropower Voltage Reference Diode .............' ..... ; ........ : ...... . 84·21 LM386 Low Voltage Audio Power Amplifier ............................ ~ ........... . 10·40 10·44 LM387 Low Noise Dual Preamplifier ........................' .... , ......... '" ., ... . LM387A Low Noise Dual Preamplifier .............................•................ 10·44 LM388 1.5 Watt Audio Power Amplifier ........................................... . 10·47 LM389 Low Voltage Audio Power Amplifier With NPNTransistor Array ......•.......... 10·52 LM390 1 Watt Battery Operated Audio Power Amplifier ............................. . 10·59 LM391 Audio Power Driver .....•........................................ i .•.••... 10·64 LM392 Low Power Operational AmplifierlVoltage Comparator .... ~ ............. ; .... . 3·242 LM393 Low Power Low Offset Voltage Dual Comparator ............................ . 5·41 LM393A Low Power Low Offset Voltage Dual Comparator ..................' ......... . 5·41 LM394 8upermatch Pair •................................................. ; ..... . 12·4 LM395 Ultra Reliable Power Transistor ......................................•..... ' 12·10 LM396 10 Amp Adjustable Voltage Regulator ........................ '.............. . 1·99 LM399 Precision Reference .............................. '........' ................ . 2·54 LM399A Precision Reference ......... '.................................. '...•...... 2·60 LM555 Timer .............................................•.•................... 9·33 LM555CTimer .•.•••......................... , .. '.... '............. , ............. '. 9·33 LM556 Dual Timer ...............•.........................................'. : . .. ' 9·39 LM556C Dual Timer .......................................... ; .............. '.... . 9"39 LM565 Phase Locked Loop ......................................... ; ............. . 9·42 LM565C Phase Locked Loop .....................................................' 9·42 LM566 Voltage Controlled Oscillator ............. : .........•............ ; ........ . 9·47 LM566C Voltage Controlled Oscillator ...................... '............. : ........ . 9·47 LM567 Tone Decoder .............•.......... '" ................... ; ......... ', .. . 9·50 , 9·50 LM56C Tone Decoder .............................. ; ........' ..•................. LM709 Operational Amplifier ............................ : ....................... . ,3·249 LM709A Operational Amplifier ..................................•.•.. , .. :......... . 3·249 LM709C Operational Amplifier ...•.................... .'................... ; ...... . 3·249 LM710 Voltage Comparator .......... '......... 0' . . . . . . ' . ; . ~' • • • • • • • • • • • • • • • • • • : • • • • • • 5·56 LM710C Voltage Comparator ............................. '.................. '...... ' 5·56 LM711 Dual Comparator ............................... '...... " .. 5·59 , 5·59 LM711 C Dual Comparator ......................... .'........... '................. . LM723 Voltage Regulator ................' .............................. , ......... . 1·143 LM723C Voltage Regulator .......................•...•......... '................ . 1·143 LM725 (Instrumentation) Operational Amplifier ..................................... . 3·253 LM725A (Instrumentation) Operational Amplifier ................................... . 3·253 LM725C (Instrumentation) Operational Amplifier ................ ; .................. . 3·253 LM733 Differential Video Amp ...........•..................... '•.................. 9·54 LM733C Differential Video Amp ................................. .' .....•........... 9·54 0> • • • • • • • • • • • • • • 5·24 Alphanumerical Index (Continued) LM741 Operational Amplifier .................................................... . LM741 A Operational Amplifier ................................................... . LM741 C Operational Amplifier ................................................... . LM741 E Operational Amplifier ................................................... . LM747 Dual Operational Amplifier ..•.............................................. LM747A Dual Operational Amplifier .............................................. . LM747C Dual Operational Amplifier .............................................. . LM747E Dual Operational Amplifier ........................... '................... . LM748 Operational Amplifier .............. ~ ..................................... . LM748C Operational Amplifier ................................................... . LM78XX Series Voltage Regulators .............................................. . LM78LXX Series 3-Terminal Positive Regulators ................................... . LM78MXX Series 3-Terminal Positive Regulators .......... ~ ....................... . LM79XX Series 3-Terminal Negative Regulators ........... , ....................... . LM79LXXAC Series 3-Terminal Negative Regulators ............................... . LM79MXX Series 3-Terminal Negative Regulators ............................... , , .. LM832 Dynamic Noise Reduction System DNRTM .................................. . LM833 Dual Audio Operational Amplifier .. , ....................................... . LM903 Fluid Level Detector .................................... , ................ . LM909 Remote Control Receiver ................................................ . LM1014 Motor Speed Regulator ................................................. . LM1014A Motor Speed Regulator ............................................... .. LM1017 4-Bit Binary 7-Segment Decoder/Driver .................................. .. LM1 019N Digital Tuning Station Detector ......................................... . LM1035 Dual bc Operated TonelVolume/Balance Circuit ............ , ............. . LM1 036 Dual DC Operated TonelVolume/Balance Circuit .......................... . LM1037 Dual Four-Channel Analog Switch ....................................... .. LM1038 Dual Four-Channel Analog Switch ................................... '..... . LM1040 Dual DC Operated TonelVolume/Balance Circuit with Stereo Enhancement Facility, ............................................................... '..... . LM1112A Dolby B-Type Noise Reduction Processor ................................ . LM1112B Dolby B-Type Noise Reduction Processor, ... , .......................... .. LM1112C Dolby B-Type Noise Reduction Processor ............................. ',' .. LM1121A Dolby B-Type Noise Reduction Processor with DC Switching ............... . LM1121 B Dolby B-Type Noise Reduction Processor with DC Switching ............... . LM1121 C Dolby B-Type Noise Reduction Processor with DC Switching ............... . LM1131A Dual Dolby B-Type Noise Reduction Processor ........ : .................. . LM1131 B Dual Dolby B-Type Noise Reduction Processor ........................... . LM1131C Dual Dolby B-Type Noise Reduction Processor ........................... . LM1310 Phase Locked Loop FM Stereo Demodulator .............................. . LM1391 Phase Locked Loop Block ............................................... . LM1414 Dual Differential Voltage Comparator .... '" .............................. . LM1458 Dual Operational Amplifier ............................................... . LM1496 Balanced Modulator-Demodulator ........................................ . LM1514 Dual Differential Voltage Comparator ..................................... . LM1524 Regulating Pulse Width Modulator ........................................ . LM1558 Dual Operational Amplifier ............................................... . LM1596 Balanced Modulator-Demodulator ..........., ............................ ,. LM1800 Phase Locked Loop FM Stereo Demodulator .............................. . LM1801 Smoke Detector ....................................................... . LM1812 Ultrasonic Transceiver ......................... ; ........................ . LM1815 Adaptive Sense Amplifier ............................................... . LM 1818 Electronically Switched Audio Tape System ............................... . 8-25 3-257 3-257 3-257 3-257 3-260 3-260 3-260 3-260 3-265 3-265 1-181 1-184 1-190 1-193 1-198 1-202 S 12-1 S 1-45 9-58 9-64 S 11-1 9-69 11-3 11-7 10-75 S 12-9 S6-9 S 6-15 S 12-18 10-88 10-88 10-88 S 12-28 S 12-28 S 12-28 10-97 10-97 10-97 10-102 10-104 5-62 3-268 10-107 5-62 1-148 3-268 10-107 10-111 9-73 9-77 9-85 10-113 Alphanumerical Index (Continued) LM1819 Air-Core Meter Driver...................... ..... ......................... S 12-31 LM1821 S Video IF PLL Synchronous Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 LM1823 Video IF Amplifier/PLL Detector System.. .... . ... .... ........... .......... S 12-39 LM 1828 Color Television Chroma Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 LM1830 Fluid Detector......................... ... . ..................•.......... 9-88 LM1837 Low Noise Preamplifier for Autoreversing Tape Playback Systems. . . . . . . . . . . . . 10-122 LM 1848 Color Television Chroma Demodulator ........................... '. . . . . . . . . . 11-13 LM1851 Ground Faultlnterrupt ..... ..... ..... ....... ..... ................... ..... S 10-8 LM1863 AM Radio System for Electronically Tuned Radios. . . . . . . . . . . . . . . . . . . . . . . . . .. S 12-46 LM1865 Advanced FMIF System............. ... .. ... .... .. ................. ..... 10-132 LM1866 Low Voltage AM/FM Receiver............................................ 10-146 LM1868 AM/FM Radio System................................................... 10-153 LM1870 Stereo Demodulator with Blend .......................................... " 10-161 LM1871 RC Encoder/Transmitter .................................... ~............ 9-101 LM1872 Radio Control Receiver/Decoder.... .............................. ..... ... 9-116 LM1875 20 Watt Power Audio Amplifier ... ~ ........... '.......... :.... .. ......... ... S 12-58 LM1877 Dual Power Audio Amplifier ................ , ........... ; ................ .. 10-167 LM1880 No-Holds Vertical/Horizontal ...................................... ;... ... 11-16 LM1884 TV Stereo Decoder. ... ................... ........... ............ .. ...... S 12-64 LM 1886 TV Video Matrix D to A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23 LM1889 TV Video Modulator ... . . . . . . . .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. . 11-28 LM1893 Carrier-Current Transceiver ............................................... S 12-67 LM1894 Dynamic Noise Reduction System DNRTM.:................................ 10-172 LM1895 Audio Power Amplifier................................................... 10-179 LM1896 Dual Power Audio Amplifier ........... :................................... 10-184 LM1897 Low Noise Preamplifier for Tape Playback Systems ............. :. . . . . . . . . . . . 10-191 LM1949 Injector Drive Controller ......................................... ~ .. . .. . .. S 12-87 LM1964 Sensor Interface Amplifier. .. .... ...................... .......... .... ..... S 12-95 LM1965 Advanced FM IF System....... ..... ........ . .... .... .. ......... ..... .... 10-132 LM2002 8-Watt Audio Power Amplifier.. . . . .. . . . .. . . .. . . . .. .. . . . . . . . . . . . . . . . . . . . . . . 10-200 LM2002A 8-Watt Audio Power Amplifier ........................................... 10-200 LM2005 20-Watt Automatic Power Amplifier ........................... '. . . . . . . . . . . .. S 12-99 1-148 LM2524 Regulating Pulse Width Modulator. .. . . . . . . . .. . . . .. ... . . . . . . . .. . . . . . . . . . . . . LM2808 Monolithic TV Sound System ............................................. 11-37 LM2877 Dual4-Watt Power Audio Amplifier .......... ;............................. 10-204 LM2878 Dual 5-Watt Power Audio Amplifier ........................ ~ . . . .. . . . . . . . . . . 10-210 LM2879 Dual 9-W~tt Audio Amplifier .............................................. S 12-105 LM2889 TV Video Modulator . .'.................................................... S 12-112 LM2895 Audio Power Amplifier ................. . . . . . . . . . . . . . . . . . . . . .. . . .. . . .. . . . . 10-179 LM2896 Dual Power Audio Amplifier. . . . .. . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . 10-184 3-270 LM2900 Quad Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LM2901 Low Power Low Offset Voltage Quad Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 LM2902 Low Power Quad Operational Amplifier ...................... ;............. 3-172 LM2903 Low Power Low Offset Voltage Dual Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 LM2904 Low Power Dual Operational Amplifier ........... . . . . . . . . . . . . . . . . . . . . . . . . . . 3-216 LM2905 Precision Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-5 LM2907 Frequency to Voltage Converter .. : ...................... '.............. ~ . . 9-135 LM2917 Frequency to Voltage Converter .......................................... _ 3-135 LM2924 Low Power Operational AmplifierlVoltage Comparator ......... '. . . . . . . . . . . . . . 3-242 LM2930 3-Terminal Positive Regulator. . . . . . . . . . .. . . .. . . . . . . ... . .. . .. .. . .... . . . .. . . S 3-1 LM2931 Series Low Dropout Regulators ....................................... ~... S 3-7 LM2935 Low Dropout Dual Regulator ............................................. .- S 3-13 LM3011 Wide Band Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-216 5-26 Alphanumerical Index (Continued) LM3045 Transistor Array. . . . . . . . . . . . . . .. . .. . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . 12-18 LM3046 Transistor Array. .. .................................. .......... .. .... . ... 12-18 LM3064 Television Automatic Fine Tuning ......................................... 11-41 LM3075 FM Detector/Limiter and Audio Preamplifier. ... ...•....... .. ....... .. ... .. . 10-218 LM3080 Operational Transconductance Amplifier. .. . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . 9-148 LM3080A Operational Transconductance Amplifier. . . . . . . . . .. .. . . . . . . . . . . .. . . .. . .. .• 9-148 LM3086 Transistor Array. ...... ... . .... ...... ... .. ... .. .. ............ .... ........ 12-18 LM3089 FM Receiver IF System... ..... .. ....... ....... .......................... 10-220 LM3146 High Voltage Transistor Array.............. ... ....... ......... ... . ..... ... 12-23 LM3189 FM Receiver IF System... ........... ... ..... ................ ............ 10-224 LM3301 Quad Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-270 LM3302 Low Power Low Offset Voltage Quad Comparator ................. ; . . . . . . . . . 5-27 LM3361A Low Voltage/Power Narrow Band FM IF System ........................ '" S 12-121 LM3401 Quad Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-270 LM3524 Regulating Pulse Width Modulator..... ... .............. .... ....... .. ...... 1-148 LM3820 AM Radio System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . 10-231 LM3900 Quad Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-270 LM3905 Precision Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 LM3909 LED Flasher/Oscillator.. ..... . .. . ...... ......... ......... ......... ..... . 9-152 LM3911 Temperature Controller .................................. ................ 9-156 LM3914 Dot/Bar Display Driver........... ....... ......... ... ............ ...... ... 9-163 LM3915 Dot/Bar Display Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . 9-177 LM3916 Dot/Bar Display Driver. .. .......... .. ...... ........... .. ...... .. . .. ...... 9-193 LM3999 Precision Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63 LM4250 Programmable Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-279 LM4250C Programmable Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-279 LM4500A High Fidelity FM Stereo Blend Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-235 LM11600A Dual Operational Transconductance Amplifier with Linearizing Diodes and Buffers. .... ..... ......... ........... .•....... ... ... 10-242 LM11700A Dual Operational Transconductance Amplifier with Linearizing Diodes and Buffers ............................................. 10-258 LM13080 Programmable Power Op Amp. . . . . . . . . .. .. . . . . .. . . . . . . .. . .. . .. . . . . . . . . . . 3-284 LM13600 Dual Operational Transconductance Amplifier with Linearizing Diodes and Buffers ............................................. 10-242 LM13600A Dual Operational Transconductance Amplifier with Linearizing Diodes and Buffers ............................................. 10-242 LM13700 Dual Operational Transconductance Amplifier with Linearizing Diodes and Buffers ............................................. 10-258 LM13700A Dual Operational Transconductance Amplifier with Linearizing Diodes and Buffers ............................................. 10-258 LMC835 Digital Controlled Graphic Equalizer ...................... ; ..... '............ S 12-126 LP165 Micropower Programmable Quad Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S 2-1 LP311 Voltage Comparator ...................................................... S 2-9 LP339 Ultra-Low Power Quad Comparator... ... . ........... .... .... .. ...... ....... S 2-11 LP365 Micropower Programmable Quad Comparator. . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . S 2-1 LP395 Ultra Reliable Power Transistor. . . . . . . . . . . . . . . . . . . .. . . .. . . . . . . . . . . . . • . . . . . . . S 15-1 MF4 4th Order Switched Capacitor Butterworth Lowpass Filter............... .... ..... S 9-1 MF5 Universal Monolithic Switched Capacitor Filter ................................. S 9-8 MF6 6th Order Switched Capacitor Butterworth Lowpass Filter. . . . . . . . . . . . . . . . . . . . . . . . S 9-9 MF10 Universal Monolithic Dual Switched Capacitor Filter. . . . . . . . . . . . . . . • . . . . . . . . . . . . S 9-17 MM54104 DIGITALKERTM Speech Synthesis System............................... S 14-5 MM54C905 12-Bit Successive Approximation Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-262 MM74C905 12-Bit Successive -Approximation Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-262 5-27 Alphanumerical Index (Continued) TBA 120S IF Amplifier and Detector ..........•.........................•..... : ... . 10-274 TBA 120T IF Amplifier and Detector .............................................. . 10-277 TBA 120U IF Amplifier and Detector .................................•............. 10-277 TBA440C Monolithic Video IF Amplifier ....................................... ',' .. . 11-43 TBA51 0 Chrominance Combination ................•.............................. 11-45 TBA530 RGB Matrix Preamplifier ...................................... : ......... . 11-49 TBA540 Reference Combination ................................................. . 11-52 TBA560C Luminance and Chrominance Control Combination ....................•.... 11-56 TBA920 Line Oscillator Combination ............................................ ;. 11.-60 TBA920S Line Oscillator Combination ............................................ . 11-60 TBA950-2 Television Signal Processing Circuit ..................................... . 11-63 TBA970 Television Video Amplifier ............................................... . 11-67 TBA990 Color Demodulator ..... , ............................................... . 11-70 TDA440 Video IF Amplifier ...................................................... . 11-72 TDA2003 Audio Power Amplifier ................................................. . 10-281 11-76 TDA2522 Color Demodulation Combination .................................... : .. . TDA2523 Color Demodulation Combination ....................................... . 11-76 TDA2530 R-G-B Matrix Preamplifier With Clamps .................................. . 11-78 TDA2540 Video IF Amplifier and Demodulator ..................................... . 11-81 TDA2541 Video IF Amplifier and Demodulator ..................................... . 11-84 TDA2560 Luminance and Chrominance Control Combination ................... ; .... . 11-87 TDA2591 Line Oscillator Combination ............................................ . 11-90 TDA2593 Line Oscillator Combination ................. : .......................... . 11-90 TDA3500 Chroma Processor + RGB Drive Combination ............................. . 11-96 ' TD3501 Chroma Processor + RGB Drive Combination ............................. . 11-102 TP18 Implementation of a Speech Synthesizer ..................................... . S 14-11 TP3020/TP3020-1 Monolithic CODECs ........... ; ............................... . S 13-1 TP3021/TP3021-1 Monolithic CODECs ........................................... . S 13-1 TP3040 PCM Monolithic Filter ........•........................................... 9-238 TP3040A PCM Monolithic Filter .......................•........................... 9-238 TP3040A PCM Monolithic Filter .................................................. . 9-238 TP3051 Monolithic Parallel Interface CMOS CODEC/FILTER Family ................. . 9-245 TP3052 Monolithic Serial Interface CMOS CODEC/FILTER Family ................... . S 9-28 TP3053 Monolithic Serial Interface CMOS CODEC/FILTER Family ................... . S 9-28 TP3054 Monolithic Serial Interface CMOS CODEC/FILTER Family ................... . S9-28 TP3056 Monolithic Parallel Interface CMOS CODEC/FILTER Family ................. . 9-245 TP3057 Monolithic Serial Interface CMOS CODEC/FILTER Family ............•. : .... . S 9-28 TP3064 Monolithic Serial Interface CMOS CODEC/FILTER Combos ................. . S9-41 TP3067 Monolithic Serial Interface CMOS CODEC/FILTER Combos ................. . S 9-41 TP3110 Digital Line Interface Controllers (DUC) ................................... . 9-249 TP3120 Digital Line Interface Controllers (DUC) ................................... . 9-249 TP5087 DTMF (TOUCH-TONE®) Generator .......... ; ......•...................... 9-250 TP5087A DTMF (TOUCH-TONElli» Generator ...................................... . 9-250 TP5088 DTMF Generator for Binary Input Data ................. : .................. . 9-254 TP5092 DTMF (TOUCH-TONE®) Generator ....................................... . 9-250 TP5092A DTMF (TOUCH-TONE®) Generator .........•............................ 9-250 TP5094 DTMF (TOUCH-TONE®) Generator ....................................... . 9-250 TP5094A DTMF (TOUCH-TONE®) Generator ..................................... . 9-250 TP5116A Monolithic CODEC .................................................... . 9-223 TP5117A Monolithic CODEC .................................................... . 9-223 TP5156A Monolithic CODEC ............. '.' ...................................... . 9-223 TP5393 Pushbutton Pulse Dialer Circuit ........................................... . 9-271 TP5394 Pushbutton Pulse Dialer Circuit .........•.................................. 9-271 5-28 Alphanumerical Index (Continued) TP5395 DTMF (TOUCH-TONE®) Generator ..................................•..... 9-266 9-281 TP5600 Ten-Number Repertory Pulse Dialer ...................................... . TP5605 Ten-Number Repertory Pulse Dialer ...................................... . 9-281 TP561 0 Ten-Number Repertory Pulse Dialer .................................•..... 9-281 TP5615 Ten-Number Repertory Pulse Dialer .•..................................... 9-281 TP5650 Ten-Number Repertory DTMF Generator .................................. . 9-287 TP5660 Ten-Number Repertory DTMF Generator .................................. . 9-287 TP5700 Monolithic Telephone Speech Circuits .................................... . S 13-10 TP5710 Monolithic Telephone Speech Circuits .....................•............... S 13-10 TP9151 Push Button Pulse Dialer Circuit with Redial ................................ . 9-255 9-255 TP9152 Push Button Pulse Dialer Circuit with Redial ................•................ TP9156 Push Button Pulse Dialer Circuit with Redial ................................ . 9-255 9-255 TP9158 Push Button Pulse Dialer Circuit with Redial ...........................•..... TP50981 Push Button Pulse Dialer Circuit ......................................... . 9-260 TP50981 A Push Button Pulse Dialer Circuit. ....................................... . 9-260 TP50982 Push Button Pulse Dialer Circuit ......................................... . 9-260 TP50982A Push Button Pulse Dialer Circuit. ....................................... . 9-260 TP50985 Push Button Pulse Dialer Circuit ......................................... . 9-260 TP50985A Push Button Pulse Dialer Circuit. ....................................... . 9-260 TP53125 DTMF (TOUCH-TONE®) Generator ...................................... . 9-276 TP53130 DTMF (TOUCH-TONE®) Generator ...................................... . 9-276 TP53143 Pushbutton Pulse Dialer Circuit. ~ ...............................•......... 9-271 TP53144 Pushbutton Pulse Dialer Circuit. ......................................... . 9-271 TP53190 Push-Button Pulse Dialer ............................................... . S 13-17 5-29 Section 1 Amplifiers Amplifiers Section Contents Buffer Amplifiers LH0033/LH0033A, LH0033C/LH0033AC, LH0063/LH0063C Fast and Damn Fast Buffer Amplifiers .................. 5 1-7 Instrumentation Amplifiers LM163/LM363 Precision Instrumentation Amplifiers ........................................................... 5 1-24 Operational Amplifiers LH0032, LH0032~, LH0032C, LH0032AC Ultra·Fast FET·Input Operational Amplifier ............................... 5 1-1 LH0132, LH0132C Ultra·Fast FET·lnput Operational Amplifier Featuring Low Input Bias Current Over ± 10V Input Range ................................................... 5 1-18 LM833 Dual Audio Operational Amplifier ..................................................................... 5 1-45 ~--------------------------------------------------------------------------------, ~National PRELIMINARY ~ Semiconductor r- :l: I:) I:) Co) ,!') r- :l: I:) I:) Co) LH0032,LH0032A,LH0032C,LH0032AC Ultra Fast FET-Input Operational Amplifier ~ r- :l: I:) I:) Co) General Description The LH0032/LH0032A is a high slew rate, high input impedance differential operational amplifier suitable for diverse application in fast signal handling. The high allowable differential input voltage, ease of output clamping, and high output drive capability particularly suit it for comparator applications. It may be used in applications normally reserved for video amplifiers allowing the use of operational gain setting and frequency response shaping into the megahertz region. Features • • • • 500 V IIJ-s slew rate 70 MHz bandwidth 1012.f} input impedance As low as 2 mV max input offset voltage • FET input • Offset null with single pot • No compensation for gains above 50 • Peak output current to 100 mA The LH0032's wide bandwidth, high input impedance and high output capacity make it an ideal choice for applications such as summing amplifiers in high speed D to A converters, buffers in data acquisition systems and sample and hold circuits. Additional applications include high speed integrators and video amplifiers. The LH0032 and LH0032A are guaranteed for operation over the temperature range - 55·C to + 125·C, the LH0032C and LH0032AC are guaranteed for - 25·C to + a5·C. Block and Connection Diagrams .. 11 ., ., .3 ......EI{ COMPENSATION INVERT , , OUTPUT COMPENSATION INPUT NON·INVERT INPUT • ., .0 ., •• TL/K/5265-1 OUTPUT COMPENSATION Order Number LH0032, LH0032A,LH0032C,LH0032AC See NS Package H12B NC TOP VIEW 51-1 TUK/5265-23 N P r- :l: I:) I:) Co) ~ o • - Absolute Maximum Ratings ±18V Supply Voltage, Vs Input Voltage, VIN Differential Input Voltage Operating Temperature Range, T A LH0032G/AG ±Vs ±30Vor ±2Vs , Power Dissipation, PD 1.5W, derate 1OO'C/W to 125'C (Note 1) TA = 25'C 2.2W, derate 70'C/W to 125'C (Note 1) Tc = 25'C DC Electrical Characteristics Symbol Parameter Operating Junction Temperature, TJ Storage Temperature Range Lead Temp. (Soldering, 10 seconds) Vs = ± 15V, T MIN LHOO32AC LHOO32 Mlr, Typ Max Min Typ Max Min Vos Input Offset Voltage aVosl Average Offset aT los Voltage Drift Input Offset Current VIN';'O Input Bias Current Ie Common Mode aVIN= ±10V Rejection Ratio AVOL Open-Loop Voltage Gain VO=±10V, 1=1 kHz RL = 1 kO (Note 6) Vo Output Voltage RL = 1 kO Swing Is Power Supply Current TA=25'C, 10 = 0 (Note 6) PSRR Power Supply Rejection Ratio aVs=10V (±5to ±15V) Units 2 2 5 2 .5 7 2 5 10 2 15 20 (Note 4) 15 30 15 30 .15 50 15 50 /LV/'C mV TJ ,;. 25'C (Note 3) TA = 25'C (Note 5) 10 250 10 30 500 3 25 250 25 50 500 5 pA pA nA TJ = 25'C (Note 3) TA = 25'C (Note 5) 50 1 25 150 5 10 100 1 50 500 5 15 pA nA nA TJ=25'C AC Electrical Characteristics Vs = Symbol LHOO32C Typ Max Min Typ Max TA=TJ=25'C (Note 3) ·VINCM Input Voltage Range CMRR 175'C - 65'C to + 150'C 300'C :s: TA :s: TMAX unless otherwise noted (Note 2) LHOO32A Test .Condltlons - 55'C to + 125C'C - 25'C to + 85'C LH0032CGI ACG Parameter SR Slew Rate ts Settling Time to 1% 01 Final Value ts Settling Time to 0.1 % 01 Final Value tR Small Signal Rise Time tD Small Signai Delay Time ±10 ±12 ±10 ±12 ±10 ±12 ±10 ±12 V 50 60 50 60 50 60 50 60 dB 60 70 60 70 60 70 60 70 dB 57 57 57 57 ±10 ±13.5 ±10 ±13 ±10 ±13.5 ±10 ±13 18 50 60 20 20 50 60 18 22 50 20 60 20 50 60 V 22 mA dB ±15V, RL = 1kO, TJ = 25'C (Note 7) Conditions Av= +1 Av = -1, aVIN = 20V Min Typ 350 500 Max 100 ns 300 Av = +1, aVIN = 1V Units V//Ls 8 20 10 25 1. In order to limit maximum junction temperature to + 17S'C, ~ may be necessary to operate with VS < ± 1SV when TA or Tc exceeds specific values depending on the Po within the device package. Total Po is the sum of quiescent and load-related dissipation. See applications notes AN-277, "Applications of Wide-Band Buffer AmpIHiers",and AN·253, "High-Speed Operational·Amplifier Applications" for a discussion of load·related power dissipation. Note 2. LH0032AG/G are 100% production tested as specHied 'at 2S'C, 125'C, and -55'C. LH0032ACG/CG are 100% production tested at 25'C only. SpecHications at temperature extremes are verilied by sample testing, but these limits are not used to calculate outgoing quality level. Note 3. Specification is at 25'C junction temperature due to requirements of high-speed automatic testing. Actual values at operating temperature will exceed the value at TJ = 25 C. When supply voltages are ± 1SV, no· load operating junction temperature may rise 4O-60'C above ambient, and more under load conditions. Accordingly, Vos may change one to several mV, and 18 and los will change Significantly during warm-up. Refer to 18 and los vs. temperature graph for expected values. Note 4. LH0032AG/G are 100% production lested for this perameter. LH0032ACG/CG are sample tested only. Limits are not used to calculate outgoing quality levels. /;,vOs"n is the average value calculated from measurements at 25'C and TMAX. Note 5. Measured in still air 7 minutes after application of power. Guaranteed thru correlated automatic pulse testing. Note 6. Guaranteed thru correlated automatic pulse testing at TJ = 2S'C. Note 7. Not 100% production tested; verified by sample testing only. Limns are not used to calculate outgoing quality level. o Limits at high/low temp. are sample tested to LTPD = 10 on LH0032CG/ ACG. Note S 1-2 Typical Performance Characteristics ~ ~u; 1.5 '"Ci 1.0 I C §. z>- CASE 8JC ~ 7o°C/W- ~ :::> ... ........ ~ "" iAMBIENT........ f"o,., 0.5 r--8JrlorC/~ I o 25 20 ;; 18 ; 16 60 /' C< . '"~ > 111111 90 PHASE 40 135 180 ~ C> GAIN 20 225 1111111 0 10k ~ ,.~ .. g: Sl j iii" ::!. ~ '" ~ z Ed 60 50 ~ 40 Ii 3D 52 Ul ~ :E :E ... C> .. 40 ~ GAIN 20 o 10k 100M lOOk 45 90 135 II IIII 270 co > >~ :; 20 10 :::> C> Av=+l Vs = ±15V RL=lk ~ T~,,;,,~rC I 11111111 I 10 100 1M 10M a 100M FREQUENCY (Hz) Large Signal Pulse Response I I\.. Av~+l RL~lk +5 - I 10 VS- ±15V_ I VS=±15V Av= +10 RL=lk E w '"~ C> > >- ~ -5 -5 :::> C>. ., -10 o 10M >:::> ">- 100M 10M C> 1M I!! z Large Signal Pulse Response +10 20 IlIl!~\I~I. 6 1M 15 1111111\1 1111 , FREQUENCY 1Hz) E w '"~ lOOk m a ~ RL~lk 10k . !ii'" . .§ ,.:: ." C> > 10 Large Signal Frequency Response PHASE C< W~I±j~J 70 o 26 24 22 20 18 16 14 12 10 8 VS~±15V z 1111111 lOOk 10M 1M FREQUENCY 1Hz) 90 80 • SUPPLY VOLTAGE I ±V) 60 Common Mode Rejection Ratio va. Frequency C> o __~~__~~ 20 10 15 SUPPLY VOLTAGE I ± V) L-~~ 80 45 '/ ././ 12 5 111111 / ./ ZVIN- f---- ~ Bode Plot (Unity Gain Compensallon) 1'\ z 10 :> Bode Plot (Uncompensated) ~ .1 VoU,/./ ~ 50 75 100 125 150 TEMPERATURE (OC) VS~±15V ./ 15 +1 10 80 ./ t-TC~25°C It :::> 14 '" Input Voltage Range and Output Voltage va. Supply Voltage RL~lk 22 I " "" "" o 20 24 I '- 2.0 z C> Supply CUrrent va. Supply Voltage Maximum Power Dlsalpallon 2.5 100M 100 200 FREQUENCY 1Hz) 300 -10 400 100 50D 200 Normalized Input Bias and Offset Current va. Junction Temperature 300 400 500 TIME (ns) TIME Ins) Input Bias Current va. Input Voltage Normalized Input Bias Current During Warm-Up N 120 :: , 100 VS-±15V TA 25°C ! 100 !i! 8Q w ~ C> > w !!l 60 RS =look C> z >~ I 10" ;!!; -' ;! 1 25 45 65 85 105 125 145 165 JUNCTION TEMPERATURE 1°C) C> o 10 TIME FROM POWER TURN-ON (MINUTES) >- 40 '-RS=lOo~ 20 o 10 1111111 100 II- ~ 'lk 10k FREQUENCY 1Hz) TL/K/5265-2 81-3 Typical Performance Characteristics (Continued) Auxiliary Circuits Total Input Noise Voltage va. Frequency· Offset Null Output Short Circuit Protection r--+---Y+ _120 II 110 ~'IO .!! 10 c 10 .= ..•... ~ 7D > 10 III •... '" 50 4D 3D y- 20 ~ I! y- TL/K/5265-15 I. Ik fREDUEICY eNd 10k TUK/5265-14 TL/K/5265-16 ·NoIse voltage includes contribution from source resistance. Typical Applications 10X Buffer Amplifier Unity Gain Amplifier 5 pF 8 pF-IO pF 2k INPUT --'\I"""....;~ INPUT >'.;.;'-.... OUTPUT OUTPUT 9k y_'O I'OOPF y- Ik 100 TUK/5265-17 100X Buffer Amplifier TL/K/5265-18 Non-Compensated Unity Gain Inverter y+ y+ 10k + 10k INPUT ......W'lr-........-Oof 270 OUTPUT O,O'T 100 TL/K/5265-19 S 1-4' TL/K/5265-20 r- ::r: Typical Applications (Continued) Q Q W High Speed Sample and Hold ~ r- ::r: Q 1000 Q W N ]> r- YOUT ::r: Q Q W N s> r- ::r: Q Q W N ~ Y+----~~~---t 0 LOGIC CONTROL _ _"'-_ TLlK/5265-21 ·Use polyslyrene dielectric for minimum drift v- r---*---,I High Speed Current Mode MUX I 3.8 pF R5 11 >--.... -YOUT 12 14 TLlK/5265-22 Applications Information POWER SUPPLY DECOUPLING INPUT CURRENT The lH0032/lH0032A, like most high speed circuits, is sensitive to layout and stray capacitance. Power supplies should be by passed as near to pins 10 and 12 as practicable with low inductance capacitors such as 0.01 /LF disc ceramics. Compensation components should also be located close to the appropriate pins to minimize stray reactances. Because the input devices are FETs, the input bias current may be expected to double for each 11'C junction temperature rise. This characteristic is plolted in the typical performance characteristics graphs. The device will self-heat due to internal power dissipation after application of power thus raising the FET junction temperature 40-60'C above freeair ambient temperature when supplies are ± 15V. The de- S 1-5 Applications Information (Continued) vice temperature will stabilize within 5-10 minutes after application of power, and the input bias currents measured at that time will be indicative of normal operating currents. An additional rise would occur as power is delivered to a load due to additional internal power dissipation. There is an additional effect on input bias current as the input voltage is changed. The effect, Common to all FETs, is an avalanche-like increase in gate current as the FET gateto-drain voltage is increased above a critical value depending on FET geometry and doping levels. This effect will be noted as the input voltage of the LH0032 is taken below ground potential when the supplies are ± 15V. All of the effects described here may be minimized by operating the device with Vs~ ±15V. These effects are indicated in the typical performance curves. INPUT CAPACITANCE The input capacitance to the LH0032!LH0032C is typically 5pF and thus may form a significant time constant with high value resistors. For optimum performance, the input capacitance to the inverting input should be compensated by a small capacitor across the feedback resistor. The value is strongly dePElndent on layout and closed loop gain, but will typically be in the neighborhood of several picofarads. In the non-inverting configuration, it may be advantageous to bootstrap the case and! or a guard conductor to the inverting input. This serves both to divert leakage currents away from the non-inverting input and to reduce the effective input capaCitance. A unity gain follower so treated will have an input capaCitance under a picofarad. HEAT SINKING While the LHOO32!LH0032A is specified for operation without any explicit heat sink, intemal power dissipation does cause a Significant temperature rise. Improved bias current performance can thus be obtained by limiting this temperature rise with a small heat sink such as the Thermalloy No. 2241 or equivalent. The case of the device has no internal connection, so it may be electrically connected to the sink if this is advantageous. Be aware, however, that this will affect the stray capaCitances to all pins and may thus require adjustment of circuit compensation values. For additional applications Information request Application Note AN·253. S 1-6 r::r:: o o w w ....... r::r:: o o ~National ~ Semiconductor LH0033/LH0033A/LH0033C/LH0033AC,LH0063/LH0063C w ~ Fast and Damn Fast Buffer Amplifiers r- ::r:: o o w w (") ....... r::r:: o General Description The LH0033/LH0033A and LH0063 are high speed. FET input. voltage follower/buffers designed to provide high current drive at frequencies from DC to over 100 MHz. The LH0033/LH0033A will provide ± 10 mA into 1 kn loads (± 100 mA peak) at slew rates of 1500V/ jots. The LH0063 will provide ± 2S0 mA into son loads (± SOO mA peak) at slew rates up to 6000V/ jots. In addition. both exhibit excellent phase linearity up to 20 MHz. Both are intended to fulfill a wide range of buffer applications such as high speed line drivers. video impedance transformation. nuclear instrumentation amplifiers. op amp isolation buffers for driving reactive loads and high impedance input buffers for high speed A to Os and comparators. In addition. the LH0063 can continuously drive son coaxial cables or be used as a yoke driver for high resolution CRT displays. For additional applications information. see AN-48. Advantages • Only 10V supply needed for S Vp-p video out • Speed does not degrade system performance • Wide data rate range for phase encoded systems • Output drive adequate for most loads • Single pre-calibrated package Features • Damn fast (LH0063): 6000 V/ jotS • Wide range single or dual supply operation • Wide power bandwidth: DC to 100 MHz • High output drive: ± 10V with son load • Low phase non-linearity: 2 degrees • Fast rise times: 2 ns • High current gain: 120 dB • High input resistance: 1010n These devices are constructed using specially selected junction FETs and active laser trimming to achieve guaranteed performance specifications. The LH0033/LH0033A and LH0063 are specified for operation from -SS'C to + 12S'C; whereas. the LH0033C/LH0033AC and LH0063C are specified from - 2S'C to + 8S'C. The LH0033/ LH0033A is available in either a 1.SW metal TO-8 package or an 8-pin ceramic dual-in-line package. The LH0063 is available in a SW 8-pin TO-3 package. Connection Diagrams Metal Can Package Nt Dual·ln·Llne Package INPUT OFFSET PRESET OFFSET ADJUST OUTPUT Metal Can Package -..:ot--., y+ -..:ot-----...1 Y- TOP VIEW TLiK/5507-2 TOPYIEW TLiK/5507-3 Case Is electrically isolated TOPYIEW TUK/5507-1 Case is electrically isolated Order Numbers LH0033/LH0033A/LH0033C/ LH0033AC,LH0063/LH0063C See NS Packages H12B, HYOBA, KOBA Teflon Is a trademark of E I. DuPont Corp. S 1-7 B ~ ....... !C o o en w ..... r::r:: o o en w (") ~ CD 8 ::I: ....I ...... C") g ::I: ....I ~ C") CI CI :5 .... o C") S CI ::I: ....I ~ C") Absolute Maximum Ratings Supply Voltage(V+ -V-) 40V Maximum Power Dissipation (See Curves) LHOO63/LH0063C LH0033A1LH0033AC/LH0033/LH0033C . Peak Output Current LH0063/LH0063C 5W 1.5W 175'C Maximum Junction Temperature Input Voltage Operating Temperature Range LH0033A1LH0033 and LH0063 LH0033AC/LH0033C and LH0063C ±Vs Continuous Output Current ±250mA - 55'C to + 125'C - 25'C to + 85'C Storage Temperature Range -65' to Lead Temperature (Soldering, 10 seconds) ±250 mA LH0063/LHOO63C LH0033A/LH0033AC/LH0033/LH0033C' ±500mA LH0033A/LH0033AC/LH0033/LH0033C + 150'C 300'C ±100 mA DC Electrical Characteristics Vs;'" ± 15V, TMIN s: TAS: TMAX unless otl1erwise specified (Note 1) Parameter Min Output Offset Voltage . LHOO33AC LHOO33A Conditions 1 Max ··5 50 100 Typ Rs= 1OOn,TJ;"25'C, VIN = OV (Note 2) Rs=100n Min LHOO33 Typ . Max 6 15 50 100 Min LHOO33C Typ Max 5.0 10 50 100 Units Typ Max 12 20 25 mV 50 100 p.V/'C 500 5.0 20 pA nA nA 1.00 VIV 15 20 .10 Min mV ....I .... Average Rs= 100,0, VIN=OV (Note 3) Temperature Coefficient of Offset Voltage CI CI Input Bias Current VIN=OV TJ == 25'C (Note 2) T A = 25'C (Note 4) TJ=TA=TMAX Voltage Gain Vo= ±10V, Rs=100n, RL =1.0kn 0.97 0.98 Input Impedance RL=1 kn 1010 1011 Output Impedance VIN= ±1.0V, RL = 1.0k Output Voltage Swing VI= ± 14V, RL = 1.0k VI= ±10.5V, RL =100n, TA=25'C Supply Current VIN = OV (Note 5) 20 22 21 24 20 22 21 24 V mAo Power Consumption VIN=OV 600 660 630 720 600 660 630 720 mW 8 ::I: C") C") ::I: ....I 100 1.5 7.5 6.0 1.00 250 2.5 10 0.96 0.98 1010 1011 10 ±12 1.00 6.0 0.97 0.98 1010 1011 10 ±12 ±9.0 250 2.5 10 1.00 6.0 0.98 1010 1011 10 6.0 n 10 ±12 ±12 ±9.0 0.96 V ±9.0 ±9.0 n AC Electrical Characteristics Tc=25'C, Vs= ±15\i, Rs=50n, RL =1.0 Kn (Note 6) Parameter Conditions LH0033A Min Slew Rate VIN= ±10V Bandwidth VIN = 1.0 Vrms LHOO33AC Typ Max Min LHOO33 Typ Max Min LHOO33C Typ Max Min 1000 1500 Units Typ Max 1000 1400 1000 1500 1000 1400 100 100 100 100 V/p.s MHz Phase Non-Linearity BW= 1.0Hz to 20 MHz 2.0 2.0 2.0 2.0 degrees Rise Time b.VIN= 0.5V 2.9 3.2 2.9 3.2 ns Propagation Delay b.VIN=0.5V 1.2 1.5 1.2 1.5 ns % <0.1 <0.1 <0.1 <0.1 Harmonic Distortion f> 1 kHz Nota 1: LHOO33A is 100% production tested ss specified at 25' C, 125'C, and-55"C. LH0033AC/C are 100% production tested at 25'C only. Specifications at temperature extremes are verified by sample testing, but these IimHed are not used to calculate outgoing quality level. Note 2: Specification Is at 25'C Junction temperature due to requirements of high speed automatic testing. Actual values at operating temperature will exceed the value at TJ = 25'C. When supply voltages are ± 15V, no·load operating Junction temperature may rise 40·60'C above ambient, and more under load conditions. Accordingly, Vos may change one to several mV, and Ie will change significantly during warm-up. Refer to Ie IrS temperature graph for expected values. Note 3: LH0033A is 100% production tested for this parameter. LH0033AC/C are sample tested only. Umits are not used to calculate outgoing quality levels. tNosll1T is the average,value calculated from measurements at 25'C and TMAX. Note 4: Messured in still air 7 minutes after application of power. Guaranteed through correlated automatic pulse testing. Note 5: Guaranteed through correlated automatic pulse tesling al TJ = 25'C. Note 6: Not 100% production tested; verified by sample testing only. Umits are not used to calculate outgoing qualHy level. S 1-8 r- DC Electrical Characteristics Vs = Parameter ::J: Conditions Output Offset Voltage Rs,,;100kO, TJ=25'C RL = 1000 (Note 2) Average Temperature Coefficient of Output Offset Voltage Rs"; 100 kO (Note 3) Input Bias Current TJ = 25'C (Note 2) Voltage Gain VIN= ±10V, Rs,,;100 kO, RL =1 kO Typ Max 10 25 100 Min 300 CI (0) (0) LHOO63C LHOO63 Min Voltage Gain o ± 15V, TMIN,,;TA,,;TMAX unless otherwise specified (Note 1) Units Typ Max 10 50 100 300 r- ::J: mV mV /J-VI'C CI CI (0) ~ ....... r- ::J: CI CI 0.94 VIN= ±10V, Rs,,;100 kO, RL =500 TJ=25'C 0.92 0.1 0.5 0.96 1.0 0.93 0.98 0.94 0.91 0.1 0.5 nA 0.96 1.0 VIV 0.93 0.98 VIV Input Capacitance Case Shorted to Output 8.0 VOUT= ±10V, Rs,,;100 kO, RL =500 1.0 Output Current Swing VIN= ±10V, RS,,;100 kO 0.2 0.25 0.2 0.25 A Output Voltage Swing RL =500 ±10 ±13 ±10 ±13 V 5.0 7.0 5.09 7.0 Output Voltage Swing VS= ±5.0V, RL =500, TJ=25'C Supply Current TJ=25'C, RL = (Note 4) 00, (0) (0) o ..... r- :::J: CI CI (0) Output Impedance 35 Vs= ± 15V 8.0 4.0 1.0 65 35 pF 4.0 0 V 65 ~ ..... r- ::J: g ..... rQ) (0) ::J: mA CI CI mA o Q) (0) Supply Current Vs= ±5.0V (Note 4) Power Consumption TJ=25'C, RL = Power Consumption Vs= ±5.0V 00, 50 1.05 VS= ± 15V 50 1.95 1.05 500 1.95 500 W mW AC Electrical Characteristics TJ = 25'C, Vs= ± 15V, Rs = 500, RL = 500 (Note 5) Parameter ....... LHOO63 Conditions Min Typ LHOO63C Max I Min Typ Units Max Slew Rate RL =1.0 kO, VIN= ±10V Slew Rate RL =500, VIN= ± 10V, TJ=25'C Bandwidth VIN=1.0Vrms 200 200 MHz Phase Non-Linearity BW=1.0 Hz to 20 MHz 2.0 2.0 degrees Rise Time aVIN=0.5V 1.6 1.9 ns Propagation Delay aVIN=0.5V 1.9 2.1 ns 6000 2000 2400 2000 6000 V//J-s 2400 VI/J-s % Harmonic Distortion <0.1 <0.1 Note 1: LH0063 is 100% produclion tested as specified at 2S'C, 12S'C, and -SS'C. LH0063C is 100% production tested at 2S'C only. SpeCifications at temperature extremes are verified by ssmple testing, but these limits are not used to calculate outgoing quality level. Note 2: Specification is at 2S'C junction temperature due to requirements of high speed automatic testing. Actual values at operating temperature will exceed the value at TJ = 2S'C. When supply voltages are ± ISV, no-load operating junction temperature may rise 40·60'C, above ambient, and more under load conditions. Acccrdingly, Vos may change one to several mV, and Ie ans los will change significantl~ during warm·up. Refer to Ie and los VB temperature graph for expected values. Note 3: LH0063 Is 100% production tested for this parameter. LH0063C is ssmple tested only. Umits are not used to calculate outgoing quality levels. Il.VosliH is the average value calculated from measurements at 2S'C and TMAl(. Note 4: Guaranteed through ccrrelated automatic pulse testing at TJ=2S'C. Note 5: Not 100% production tested; verified by sample testing only. Limits are not used to calculate outgoing quality level. S 1-9 Typical Performance Characteristics LH0033 Power Dissipation r-- I\.. 2.0 .~ , i" ;; 1.5 ~... = ;s I 1.0 I l"'. I 300 6 I CASE (8JC =15"C/W) CASE .. _ " -8JC =60"C/W AMBIENT 8JA =100"C/W 0.5 LH0063 Power Dissipation ! 1\ I\.. AMBIENT (SJA =WC/W) , 100 ~-100 / :::0 . 0_ 200 o -300 -15 -10 -5 0 10 OUTPUT VOLTAGE (V) 50 75 100 125 150 TEMPERATURE ("C) LH0063 Supply Center vs LH0033 Supply Current vs . Supply Voltage 16 1-~=1kb ./ ~+--+"7If-~~+---1 Rs=l00 kO I-Tc= +25"C Ia 19r-~~~~~~~~ V :!:!. 20 ElB~~-4--+--+--r-, +I 14 ~ 12 ~ I 10 1./ ;- r~=±15V 0 10 15 SUPPLY VOLTAOE (±V)· 20 i ~ -2 !j -4 V ~. ~ ~-10 ./ II!IIo 12 ;- !i. 10 !:i o INPuT/" -6 -8 ,.. i! i! -12 10 15 SUPPLY VOLTAGE (±V) 20 6 'INPUT" 'OUTPUT i 0 I 40 t-~S=±ISV ;- e 1.0 i! eli ~ !:i !ie Rs=500 t--R!.=1k0 VIN =1.0 VIm. 30 Av 0.8 0.6 0.2 ;j I O.~ 8.0 35 J: 20 15 10 /. S ~ 1.0 2.0 5.0 10.0 20.0 50 FREOUENCY (MHz) 26 100 ,.~ m '" i c; 2l ! 6.0 ~ 50 LH0033 Rise and Fall Time vs Temperature LH0063 Large Signal Pulse Response 20 Va= ±15V RI=500 AL=1 k 30 I-' ..... 40 50 60 12 10 ;- 8 :!:!. 46 2 11 ~ .... 1"'" '"'> 4.0 0 ~ ! i 20 3D 40 TIME (ns) 10 :E ;:: 10 TlME(ns) O' LH0033 Frequency Response - I 8 I !'OUTPUT .. l ¥s= ±15Y. 1\=1 kO, Rs=500 Tc= +25"C r- 2 5 20 LH0033 Positive Pulse Response RI=500 _RL=1kO Tc= +25"C I ./ 4 10 15 SUPPLYVOLTAGE (±V) LH0033 Negative Pulse Response ~ RL=5OD Rs=lk ±VIN= ±vs Tc=25"C L...-...L...--'__- ' - - ' -__L...--J 5 20 LH0063 Output Voltage vs Supply Vo,tage ;- / / 50 18 16 ./ V' iii 10 16 SUPPLY VOLTAGE (±V) 15 LH0033 Output Voltage vs Supply Voltage .Supply Voltage 18 i ¥S=±15V ITc=25"C :::0 ~ 25 " ~ ... ........ I 200 m ...... ...... I' " LH0063 DC Safe Operating Area ... ... 111.=500 -2 2.0 o -10 -12 -50 ¥S=±ISV TC=2S"C 0 E -4 S -6 I, 60 8L=1 kO -6 o ~O 100 TEMPERATURE ("C) 150 o 1 2 3 4 5 6 7 8 9 101112 TIME (ns) TL/K/5507-4 S 1-10 .-----------------------------------------------------------------------------,~ :::E: Typical Performance Characteristics (Continued) LH0033 Input Bias Current vs Temperature 2 LH0063 Frequency Response LH0063 Input Current 10 w ....... 10k VS-I±l~~ ! i+1 iii I Q Vs=±15~ GO.l00 / Vs=±5V - , ~ z ::! A/ ~ ...... £0.010 ..'"~ r-- -Vs-±10V~ lk ~ Vs-±15V IL" 100 ~/ Vs !\!~ ,. ±5V ~ ;!; 10 ~ o 25 50 75 100 TEMPERATURE ('C) 0.8 0.6 0.4 rr- 0.2 ;!; 0.001 o 125 o 25 220 200 lBO 160 140 120 100 80 60 40 20 1.0 50 75 100 TEMP.ERATURE ('C) 125 '- I"'" 1 "'" ! ~ :!; c; m r:R ~ o '- 10 100 FREQUENCY (MHz) ~ :::E: 1000 g w ~ ~ :::E: Q Q W W (') ....... ~ :::E: Q Q W '\l ...:IE LH0033 Normalized Input Bias Current During Warm-Up BOO 100 Vs-±15V ...-IA 25'C ;: tc IB ! 1£ 700 JINPUTI ! ~ 10 il!i I 1 I o 4' 6 8 10 TIME FROM POWER TURN·ON (MINUTES) 500 400 300 200 ~:a~I~DI L ... ti~,~", 121 ::~IIIC TDZU I.'" i 1.0 0.1 iw ~ :::E: ~ 1'1 I I I I I w (') ~ ;!; I I o 10 8 6 4 2 0 -2 -6' -10 INPUT VOLTAGE (VI TL/K/SS07-S .---.--+15V INPUT Application Hints OFFSET PRESET (OPEN) OFFSET ADJUST RECOMMENDED LAYOUT PRECAUTIONS RF/video printed circuit board layout rules should be followed when using the LH0033 and LH0063 since they will provide power gain to frequencies over 100 MHz. Ground planes are recommended and power supplies should be decoupled at each device with low inductance capacitors. In addition, ground plane shielding may be extended to the metal case of the device since it is electrically isolated from internal circuitry. Alternatively the case should be connected to the output to minimize input capacitance. 2000 L-........_ _....._ -15V TL/K/S507-6 FIGURE 1. Offset Zero Adjust for LH0033 (Pin numbers shown for TO-8) OFFSET VOLTAGE ADJUSTMENT r - -......- - +15V Both the LH0033's and LH0063's offset voltages have been actively trimmed by laser to meet guaranteed specifications when the offset preset pin is shorted to the offset adjust pin. This pre-calibration allows the devices to be used in most DC or AC applications without individually offset nulling each device. If offset null is desirable, it is simply obtained by leaving the offset preset pin open and connecting a trim pot of 1000 for the LH0033 or 1 kO for the LH0063 between the offset adjust pin and V-, as illustrated in Figures 1 and 2. OFFSET PRESET (OPEN) OFFSET ADJUST lk L-........._ _...._ _ 15V TL/K/SS07-7 FIGURE 2. Offset Zero Adjust for LH0063 S 1-11 ~ :::E: ....... I I I Yl I _,~v 012345678 TIME (n.) ~ ..... Q Vs=±15V ;IW PULSE TESTED (TJ=25'CI ~ I/o.UTP~T 100 10 Tc=25'C ... 600 l'! LH0033 Input Bias Current vs Input Voltage LH0063 Small Signal Rise Time Application Hints (Continued) OPERATION FROM SINGLE OR ASYMMETRICAL POWER SUPPUES St-JORT CIRCUIT PROTECTION In order to optimize transient response and output swing, output current limit has been omitted from the LH0033 and LH0063. Short circuit protection may be added by inserting appropriate value resistors between V+ and Vc+ pins and V- and Vc - pins as illustrated in Flf/urss 3 and 4. Resistor values may be predicted by: Both device types may be readily used in applications where symmetrical supplies are unavailable or not desirable. A typical application might be an interface to a. MOS shift register where V+ = +5Vand V- = -12V.ln this case, an apparent output offset occurs due to the device's voltage gain of less than unity. This additional output offset error may be predicted by: (V+-V-) AVo""(1-Av) 2 0.005(V+ -V-) V+ VRUM ""-=Isc Isc . where: where: Av= No load voltage gain, typically 0.99 IscS:100 mA for LH0033 V+ = Positive supply voltage ISCS:250 mA for LH0063 V - = Negative supply voltage For the above example, AVo would be -35mV. This may be adjusted to zero as described in Rgure 2. For AC coupled applications, no additional offset occurs if the DC input is properly biased as illustrated in the Typical Applications section. y+ y+ INPUT INPUT y- y- TUKl5507-9 TL/K/5507 -8 FIGURE 3. LH0033 Using Resistor Current Limiting FIGURE 4. LHOO63 Using Resistor Current Limiting S 1-12 ~-----------------------------------------------------------------------------'r The inclusion of limiting resistors in the collectors of the output transistors reduces output voltage swing. Decoupling Vc+ and Vc- pins with capacitors to ground will retain full output swing for transient pulses. Alternate active current limit techniques that retain full DC output swing are shown in Figures 5 and 6. In A'gures 5 and 6, the current sources are saturated during normal operation, thus apply full supply voltage to the Vc pins. Under fault conditions, the voltage decreases as required by the overload. CAPACITIVE LOADING Both the lH0033 and lH0063 are designed to drive capacitive loads such as coaxial cables in excess of several thousand picofarads without susceptibility to oscillation. However, peak current resulting from (CXdv/dtl should be limited below absolute maximum peak current ratings for the devices. Thus for the lH0033: For Figure 5: (~~!N) XCL,;;;IOUT';;; ±250 mA VeE 0.6V RLlM=-=--=100 Isc 60 mA and for the lH0063: (~~t) XCL,;;;IOUT';;; ±500 mA In Figure 6, quad transistor arrays are used to minimize can qount and: R LIM VeE 1/3(lscl 0.6V 1/3(200 mAl In addition, power dissipation resulting from driving capacitive loads plus standby power should be kept below total package power rating: 8.20 PoPkg.:2: Poc + PAC ·PoPkg.:2:(V+ -V-)XIS+PAC ...--....- -....-+15V INPUT PAC""(Vp_p)2XfXCL where: Vp-p = Peak-to-peak output voltage swing f = Frequency CL = load Capacitance OPERATION WITHIN AN OP AMP LOOP >':':-'-11--- OUTPUT Both devices may be used as a current booster or isolation buffer within a closed loop with op amps such as lH0032, lH0062, or lM118. An isolation resistor of 470 should be used betw~en the op amp output and the input of lH0033. The wide ~andwidths and high slew rates of the lH0033 and lH0063 assure that the loop has the characteristics of the op amp and that additional rolloff is not required. 0.01,.F HARDWARE In order to utilize the full drive capabilities of both devices, each should be mounted with a heat sink particularly for extended temperature operation. The cases of both are isolated from the circuit and may be connected to the system chassis. L......._~~_ _ -15V TL/K/5507-10 FIGURE 5. LH0033 Current Limiting Using Current Sources DESIGN PRECAUTION Power supply bypassing is necessary to prevent oscillation with both the lH0033 and lH0063 in all circuits. low inductance ceramic disc capacitors with the shortest practical lead lengths must be connected from each supply lead (within <% to 1ft" of the device package) to a ground plane. CapaCitors should be one or two 0.1 ~F in parallel for the lH0033; adding a 4.7 ~F solid tantalum capacitor will help in troublesome instances. For the lH0063, two 0.1 ~F ceramic and one 4. 7 ~F solid tantalum capacitors in parallel will be necessary on each supply lead. TL/K/5507-11 FIGURE 6. LH0063 Current Limiting Using Current Sources S 1-13 % o oCo) .... r Co) % o oCo) ~ ..... r % o oCo) Co) n ..... r % o oCo) ~ i. ~ r ..... r Co) % o o en Co) o Schematic Diagrams. LH0063 LH0033/LHOO33A ,.....--";';'0, 12 Y+ 2 Y+ . ') NORMALLY INPUT SHORTED 1 '" Yc+ R6 3 OUTPUT RS 9 , Yc- "I '. NORMALLY 1 ~ NORMALLY I SHORTED 7 '" Y- SHORTED '" '......,,/ NORMALLY SHORTED TL/K/5507-12 TLlK/5507-13 Pin numbers shown lor TO-8 ("Gn ) package. Typical Applications High Speed Automatic Test Equipment ForCing Function Generator VREF1--i........- . 51 lk .....+-....- -.... -2OV TL/K/5507-14 S 1·14 r-----------------------------------------------------------------------------, :::t: r Typical Applications o oCo) (Continued) Co) Gamma Ray Pulse Integrator ...... r :::t: o o +15V Co) ;...... r :::t: o oCo) Co) o ...... r :::t: o oCo) ~ 1M ...... r 1M TTL 1M ~. RnET Co) ...... r :::t: 1M o oQ) 1M Co) o 1M 1M 1M 1M -+_ -IKV L-_ _ TLlK/5507-15 Nuclear Particle Detector Ho3' PARTICLE High Input Impedance AC Coupled Amplifier V+ 15DV '-l.... .'~ LARGE AREA SILICON DIODE ......- _ - - + 1 5 V SHIELD ....~*'i OUTPUT 1M 0.1 pf L-",---15V 1~ TLlK/5507-16 V- fH:<:100 MHz TLlK/5507-17 8.1-15 o (I') g % ....I ..... (I') CD Typical Applications (Continued) Isolation Buffer Coaxial Cable Driver OVERALL FEEDBACK C) C) +15V 3 ~ 51 INPUT -..,..1\0--1 (I') C) C) >*~!t-I OUTPUT 50D % ....I ..... REACTIVE C LOAD ~ -15V S TL/K/5507-19 C) -15V % '::' ..... ....I TUK/5507-18 ~ (I') C) C) % ....I Coaxial Cable Driver ~ v+ (I') g ::z::: ....I INPUT -y,.""",'1 50D vTUK/5507 -20 'Select C1 for optimum pulse respon~e High Input Impedance Comparator with Offset Adjust Instrumentation Shield/Line Driver 51 INPUT-......J\j,."......:~ VTL/K/5507-22 Vt..L vTUK/5507 -21 S 1-16 r- Typical Applications :::E: Q Q (Continued) 1W CW Final Amplifier Co) Co) ..... r- , - - -....-+3DV :::E: l·tr-.1 . ~ 2M Q Q Co) ~ r- :::E: Q -~ '::" Q Co) Co) o ..... r- :::E: TL/K/5507-23 g ~ l:; ..... Single Supply AC Amplifier r- 4.5 MHz Notch Filter :::E: Q Vcc=12.DY Q m Co) ....... Y+ 5: Q Q m Co) OUTPUT 1 iO=2".RICI RI=2 R2 TLlK/5507-24 81 81 22DIl 22DIl Y- CI=~ 2 TLlK/5507-25 High Speed Sample and Hold Y+ ANALOG INPUT OUTPUT YY5.0Y r ~ 'Polycarbonate or Teflon LOGIC ~.....-;-"""" INPUT --1...-/ -=-...... L1" 1/20HOD34 14 YTL/K/5507-26 S 1·17 o ~ :; :s.... ~ National ~ Semiconductor :; LHO 132, LHO 132C :s Ultra-Fast. FET-Input Operational Amplifier N. . General Description Features The LH0132 is a high slew rate, high input impedance differential amplifier. It was developed specifically for sample and hold and other fast signal handling appiications which require very low input currents over the full input voltage range. Input offset and bias currents are guaranteed over a full input common mode range of -10 volts to + 10 volts. 600 pA Ibias at VIN = ±10V 500 V I jJ-s slew rate 70 MHz bandwidth 5 mV offset voltage • FET input • No compensation for gains above 50 • Peak output current to 100 mA .• • • • Block and Connection Diagrams .. 11 Rl RZ RS BALANCE{ { CDIIPENSATIDIiI .Z INVlRT OUTPUT COMPENSAnON I INPUT NON·INVERT INPUT B RI RI QI R' R4 ".. 10 TLlK/5499-4 OUTPUT COMPENSATION NC TOP VIEW Order Number LH0132G or LH0132CG See NS Package H12B S 1-18 TLlK/5499-5 r- :I: ....W Absolute Maximum Ratings Q ±18V Supply Voltage, Vs Input Voltage, VIN Differential Input Voltage Operating Temperature Range, TA LH0132G/AG ±Vs ±30Vor ±2Vs LH0132CG/ACG 175'C Operating Junction Temperature, TJ -65'C to + 150'C Storage Temperature Range Lead Temperature (Soldering, 10 seconds) 300'C Power Dissipation, Po 1.5W, derate 1OO'C/W to 125'C (Note 1) TA = 25'C Tc = 25'C 2.2W, derate 70'C/W to 125'C (Note 1) DC Electrical Characteristics Parameter Vs = ± 15V, T MIN :S: TA :S: T MAX unless otherwise noted (Note 2) LH0132G Test Conditions Min. Vas Input Offset Voltage Average Offset Voltage Drift los Input Offset Current Max. TA=TJ=25'C (Note 3) 2 (Note 4) 25 -10V:S:IN:S:10V Input Bias Current Ie ·VINCM Input Voltage Range CMRR Common Mode Rejection Ratio AVOL Open-Loop Voltage Gain RL =1 kO Is Power Supply Current TJ=25'C, 10=0 PSRR Power Supply Rejection Ratio AVS=10V Slew Rate ts Settling Time to 1% of Final Value Is Settling Time 10 0.10/0 of Rnal Value tR Small Signal Rise Time to Small Signal Delay Time 2 10 20 mV 50 25 p.V!'C pA pA nA TJ=25'C (Note 3) TA=25'C (Note 5) TJ=TA=TMAX 75 1 25 150 5 15 pA nA nA ±10 ±12 ±10 ±12 V 50 60 45 60 dB TJ=25'C 60 70 50 70 dB (Note 6) 57 ±10 (±5 to ±15) ± 15V, RL =1 Parameter SR 5 10 30 300 5 (Note 6) AC Electrical Characteristics Vs = Max. 50 f=70kHZ Output Voltage Swing Units Typ. 15 150 15 RL =1 kO Va Min. TJ = 25'C (Note 3) TA = 25'C (Note 5) TJ=TA=TMAX AVIN= ±10V Vo= ±10V LH0132CG Typ. VIN=O AVosAT N - 55'C to + 125C'C -25'Cto + 85'C 50 kO, TJ = Av=+1 ±10 ±13.5 18 Conditions Av=-1, 47 20 ±13 20 60 45 60 V 22 mA dB 25'C (Note 7) Min. Typ. 350 500 Units V/p.S 100 ns AVIN=20V Max. ns 300 Av= +1, AVIN=1V 8 20 ns 10 25 ns Note 1. In order to limit maximum iunction temperature 10 + 175'C, it may be necessary 10 operate with VS <±15V when TA or Tc exceeds specific values depending on the Po within the device psckage. Total Po is the sum of quiescent and load-related dissipation. See Applications Notes AN-277, "Applications of Wide-Band Buller Amplifiers" and AN-253, "High-Speed Operational-Amplifier Applications" for a discussion of load-related power dissipstion. Note 2. LH0132G Is 100% production tested es specified at 25"C, 150'C, and -55'C. LHOt32CG is 100% producti9n tested at 25'C only. Spscifications at temperature extremes are verified by sample testing, but these limits are not used 10 calculate outgoing quality level. Note 3. SpeCification is at 25'C junction temperature due 10 requirements of high-speed automatic testing. Actual values at opsrating tempsrature will exceed the value at TJ = 25' C_ When supply voltages are ± 15V, no-load operating junction temperature may rise 40-60'C above ambient, and more under load conditions_ Accordingly, VOS may change one 10 severa! mV, and Ie and los will change signmcanlly during warm-up. Refer 10 Ie and los VB. temperature graph for expected values. Note 4. LH0132G Is 100% production tested for this parameter. LH0132CG is sample tested only. Limits are not used to calculate outgoing quality levels. aVosl .6.T is the average value calculated from measurements at 25°C and TMAX. Note 5. Measured in still air 7 minutes aller application of power. Guaranteed thru correlated automatic pulse testing. Note 6. Guaranteed thru correlated automatic pulse testing at TJ = 25'C. Note 7. Not 100% production tested; verified by sample testing only. Limits are not used to calculate outgOing quality level. • Limits at high/low temp. are sample tested 10 LTPD=10 on LHOI32CG/ACG. S 1-19 "r:I: ....W Q N o Typical Performance Characteristics MaxlmumP_ DlselpatJon Supply Current va. Supply Voltage 2.5 I !:i§. 2.0 i 1.5 iiiis "- ....... 1.0 t- i " ....... r" I . 0 i ia: a: ::0 oC/, C"'oo. ::0 I 25 ~ 20 .. ..E I"I!.. ~ 16 14 11111 11111 PHASE 40 m ~ 0 10k 51 Ii • ~ 90 !:: m 135 - iii 111111111 60 z i ~i 40 ;; III 135' t ! CD z ! ~ .. !; If 10k lOOk 1M 10M FREQUENCY (Hzl E ~ ~ .. ..... ~ ::0 100 200 300 ~ = ± 15V-'-IHIIl-tllttflllltftffitIH 01 RL=lk Tc iJ~ri ffilIt-tIttHH1HIHH ~II\IIIII WlIIlLl 100 1M 10M 100M V$= ±15V· Av=+IO RL=lk 0 -5 -10 4G0 100 500 Normalized Input Bias Current During Warm-Up 200 300 TIME (nil 400 500 Total Input Noise .Voltage va. Frequency· ;:; 120 100 :0: ~ !~IQ311 ~i 1~ 'iw 100 VS=±15V TA=2'oC ~ 80 w 60 ~ z~ 4G ~ Z 10' ... 1 I 1 25 45 65 85 105 125 145 165 JUNCTION TEMPERATURE (OCI Av=+1 TIME (nsl Normalized Input Bias and Olfaet Current VB. Junction Temperature 10' ! I' o Large Signal Pulse . Reepanse E ..~ -5 100M 20 10 ...~ -10 5 10 15 SUPPLY VOLTAGE (±VI Large Signal Pulse Response, ~ ~ o FREQUENCY (Hzl ¥S=±15V_ Av=+1 R =Ik - +5 • 10 100M I I I I\.. +10 10 100 ~m 28 24 22 20 18 16 14 12 10 8 6 Large Signal Frequency Reeponse ~ o iB Be 90 G~m, .20 o w lOOk 1M 10M FREQUENCY (Hzl 45 1 RL=lk 10k 0 PHASE 100M 1~1~±jJ~ 40 20 ~ 270 :III~II lOOk 1M 10M FREQUENCY (Hzl 90 80 70 !: I: o ·V8= ±15V.1I 0 Common Mode Rejection Ratio vs. Frequency i 10 15 SUPPlYVOIJAGE ( ±VI 80 45 1. ~N- r-- /~ '/ 5 :: j GAIN 20 , BaM Plot (Unity Gain Comp_Uon) '60 i 10 12 BaM Plot (Uncompensated) iz .L L Vou~ j 50 75 ·,00 125 150 TEMPERATURE (OCI VI= ±15V L 15 +1 18 10 L......I---l___...L.--L_..L--I 80 ~ RL=lk t-Tc=25°C 22 i CASE 8.n:=7D°C/W- AMBIENT....... ~ 0.5 t- 9J o I i Input Voltage Range and Output Voltage va. Supply Voltage ,20 24 024 8 W TIME FROM POWER TURN-ON (MINUTESI II 20 e=" 0 10 100 Ik 10k FREQUENCY (Hzl TL/K/5499-6 81-20 r-------------------------------------------------------------------------, ::J: r Typical Performance Auxiliary Circuits .... Q Co) Characteristics (Continued) Input Bias Current vs. Input Voltage . Output Short Circuit Protection Offset Null ~ r ::J: .... Q r--+---Y+ 10' Co) ~ ...... -( ~ 100 30 25 20 15 Y- TL/K/5499-8 10 Vs+ -YIN-POSITIVE SUPPLY VOLTAGE MINUS INPUT VOLTAGE (V) TUK/5499-9 TUK/5499-7 -NOise voltage Includes contribution from source resistance. Typical Applications Unity Gain Amplifier 10X Buffer Amplifier 8-lopF 5pF 2k INPUT--",,,,,,,_"'I 11 >~""-OUTPUT 10 y- T OUTPUT '0oPF lk loon Y- TYP. BW3ddSS=45 MHz TYP. BW3dS=10 MHz TL/K/5499-1 TUK/5499-10 100X Buffer Amplifier Non-Compensated Unity Gain Inverter y+ y+ 10k 11 10k INPUT-YII'Y-.......-~ OUTPUT 100 TYP. BW3ds=5 MHz TYP. BW3ds=70 MHz TL/K/5499-11 S 1-21 TL/K/5499-2 ~.... o :I ~ .... o Typical Applications (Continued) High Speed Sample and Hold llJ11l1 CO) ::c ....I Vaur v+----~~~---t • Acquisition time for a .1VIN of 10 Yolts '" 800 nsec. 10 .1 % accuracy with droop rale of 300" VlmS oyer - 10V-~_VDUT A3-+--'lJ""""--+::"'+-O-+---. A4-+--'lJ""""--t-:.:...+-6-............ 12 14 TL/Kl5499-3 Applications Information POWER SUPPLY DECOUPLING INPUT CURRENT The LH0132, like most high speed circuits, is sensitive tei layout and stray capacitance. Power supplies should be bypassed as near to pins 10 and 12 as practicable with low inductance capacitors such as 0.01 JJ.F disc ceramics. Compensation components should also be located close to the appropriate pins to minimize stray reactances. Because the input devices are FETs, the input bias current may be expected to double for each 11·C Junction temperature rise. This characteristic is plotted in the typical performance characteristics graphs. The device will self-heat due to internal power dissipation after application of power thus raiSing the FET junction temperature 40-60·C above free- s 1-22 air ambient temperature when supplies are ±15V. The device temperature will stabilize within 5-10 minutes after application of power, and the input bias currents measured at that time will be indicative of normal operating currents. An additional rise would occur as power is delivered to a load due to additional internal power dissipation. There is an additional effect on input bias current as the input voltage is changed. The effect, common to all FETs, is an avalanche-like increase in gate current as the FET gateto-drain voltage is increased above a critical value depending on FET geometry and doping levels. Due to the cascoded FET Input stage design of the LH0132, the gate-ta-drain voltage is kept below this threshold, and the bias current remains relatively constant over the entire common-mode input voltage range. INPUT CAPACITANCE The input .capacitance to the LH0132/LH0132C is typically 5 pF and thus may form a significant time constant with high value resistors. For optimum performance, the input capacitance to the inverting input should be compensated by a small capacitor across the feedback resistor. The value is strongly dependent on layout and closed loop gain, but will typically be in the neighborhood of several picofarads. In the non-inverting configuration, it may be advantageous . to bootstrap the case and/or a guard conductor to the inverting input. This serves both to divert leakage currents away from the non·inverting input and to reduce the effective input capacitance. A unity gain follower so treated will have an input capacitance under a picofarad. HEAT SINKING While the LH0132 is specified for operation without any explicit heat sink, internal power dissipation does cause a significant temperature rise. Improved bias current performance can thus be obtained by limiting this temperature rise with a small heat sink such as the Thermalloy No. 2241 or equivalent. The case of the device has no internal connection, so it may be electrically connected to the sink if this is advantageous. Be aware, however, that this will affect the stray capacitances to all pins and may thus require adjustment of circuit compensation values. For additional applications Information request Application Note AN-253. S 1-23 ~National ~ Semiconductor LM163/LM363 Precision Instrumentation Amplifier General Description The LM163 Is a monolithic true instrumentation amplifier. It requires no external parts for fixed gains of 10, 100 and 1000. High precision is attained by on-chip trimming of offset voltage and gain. A super-beta biopolar input stage gives very low input bias current and voltage noise, extremely low offset voltage drift, and high common-mode rejection ratio. A new two-stage amplifier design yields an open loop gain of 10,000,000 and a gain bandwidth product of 30 MHz, yet remains stable for all closed loop gains. The LM163 operates with supply voltages from ±5V to ±18V with only 1.5 mA current drain. The LM163's low voltage noise, low offset voltage and offset voltage drift make it ideal for amplifying lOW-level, lowimpedance transducers. At the same time, its low bias current and high input impedance (both common-mode and differential) provide excellent performance at high impedance levels. These features, along with its ultra-high common-mode rejection, allow the LM163 to be used in the most demanding Instrumentation amplifier applications, replacing expensive hybrid, module or multi-chip designs. Because the LM163 is internally trimmed, precision external resistors and their associated errors are eliminated. The 16-pin dual-in-line package provides pin-slrappable gains of 10, 100 or 1000. Its twin differential shield drivers eliminate bandwidth loss due to cable ,capacitance. Compensation pins allow overcompensation to reduce band, width and output noise, or to provide greater stability with capacitive loads. Separate output force, sense and reference pins permit gains between 10 and 10,000 to be'programmed using external resistors. On the 8-pin TO-5 and miniDIP packages, gain is internally set at 10, 100 or 500 but may be increased with external resistors. The shield driver and offset adjust pins are omitted on the 8-pin versions. TheLM163/LM163A is rated for -55·C to + 125·C. The LM363/LM363A is rated for OOC to 70·C. Features • • • • • • • • • Offset and gain pretrimmed 12 nVl.JHz input noise (G=500/1000) 130 dB CMRR tyical (G=500/1000) 2 nA bias current typical No external parts required Dual shield drivers Available at 0.5 fJ-VI"C maximum drift Can be used as a high performance op amp Low supply current (1.5 mA typ) Typical Connections S·Pln Package 16-Pln Package V+ + -t--:::+i-"'i Your OUTPUT G=10 2,3,4, open G = 100 3-4 shorted G= 1000 2-4 shorted TL/H/5609-1 Connection Diagrams 16·Pin Dual·ln·Line Package Metal can Package· COMP COMP 1 COMP 2 SENSE OUTPUT REF v- V+ G -1000 G=100 Vos Vos + INPUT +SHIELD '5 .'REF VTOP VIEW "Pinout same for 8-pin DIP ' Order Number LM163, LM363 See NS Package D16C, HOSC, N08A, N16A GR TOP VIEW S 1-24 -INPUT -SHIELO TUH/5609-2 Absolute Maximum Ratings Supply Voltage Differential Input Voltage (Notes 3 and 9) ±18V ±10V Input Voltage Reference and Sense Voltage Equal to Supply Voltage ±25V ±20mA Input Current LM163A/LM163 Electrical Characteristics (Notes 1 and 2) LM163A Parameter Conditions Typ LM163 Tested Limit Typ Tested Limit Units 50 150 100 400 10 4 p.V p.V p.V p.V mV mV FIXED GAIN (a-PIN) G=500 10 G=100 25 G=10 0.2 Input Offset Voltage Drift G=500 G=100 G=10 0.2 1 10 0.5 2 15 1 2 20 2 5 50 p.VI"C p.VI"C p.VI"C Gain Error (± 1OV Swing, 2 kn Load) G=500 0.5 0.05 G=100 0.05 G=10 0.05 0.2 0.4 0.2 0.35 0.2 0.3 0.3 0.6 0.3 0.5 0.3 0.4 % % % % % % 100 200 300 500 2 6 p.V p.V p.V p.V mV mV Input Offset Voltage 50 100 100 300 1.0 2.5 20 35 0.3 0.05 0.05 PROGRAMMABLE GAIN (16-PIN) Input Offset Voltage G=1000 10 50 100 150 300 1 3 25 G=100 25 G=10 0.3 Input Offset Voltage Drift G=1000 G=100 (Note 4) G=10 (Note 4) 0.2 0.5 5 0.5 2 25 0.5 2 10 3 6 50 p.V1°C p.V1°C p.VI"C Gain Error (± 10V Swing, 2 kn Load) G=1000 1.0 1.0 G=100 0.05 G=10 0.4 1.5 2.0 0.2 0.35 1.0 1.1 1.5 2.0 0.3 0.5 1.0 1.1 % % % % % % 50 0.5 0.05 0.4 FIXED GAIN AND PROGRAMMABLE Gain Temperature Coefficient G=1000 G=500 G=100,10 40 20 10 Gain Non-Linearity ( ± 10V Swing, 2 kG Load) G=10,100 0.005 G=500,1000 0.007 S 1-25 ppml"C ppml"C ppml"C 40 20 10 0.001 0.02 0.02 0.04 0.005 0.007 0.02 0.03 0.03 0.05 % % % % • LM 163A/LM 163 Electrical Characteristics (Continued) (Notes 1 and 2) , LM163A Parameter Common-Mode Rejection Ratio (-11VS:VCMS: 13V) Positive Supply Rejection Ratio (5V to 15V) Negative Supply Rejection Ratio (-5V to -15V) Conditions LM163 Typ Tested Limit Typ Tested Limit Units G=1000.500 140 130 G=100 103 G=10 115 126 115 112 100 100 88 120 106 106 94 94 82 dB dB dB dB dB dB G=1000.500 130 G=100 120 G=10 100 120 110 105 96 90 78 dB dB dB dB dB dB G=1000.500 120 G=100 106 G=10 86 105 96 90 80 75 62 dB dB dB dB dB dB Input.Bias Current 2 Input Offset Current 1 120 110 105 95 90 78 110 100 96 86 80 68 125 110 130 120 100 120 106 86 5 15 2 5 16 nA nA 2 1 2 3 nA nA 100 15 GO 3 Common-Mode Input Resistance 100 Differential Mode Input Resistance G=1000.500 G=100 G=10 0.2 2 20 Input Offset Current Change -11VS:VCMS:13V , 10 Reference and Sense Resistance 20 50 160 50 Min Max GO GO BO 0.2 2 20 20 100 300 pAN pAN 35.30 70. 76 kO kO kO 50 35.30 70. 76 Open Loop Gain GCL =1000.500 10 2 10 2 VIp-V Supply Current Positive 1.2 1.2 Negative 1.6 1.8 2.8 2.2 3.3 1.8 2.8' 2.2 3.3 rnA mA rnA rnA 1.6 Note 1: These conditions apply unles~ otherwise noted: V+=V-=15V. VCM=OV, RL=2 kO, reference pin grounded, sense pin connected to output and Tj=25'C. Nole 2: Boldface IImlla are guaranteed over full tempereture renge. Operating ambient lemperature range Is - 55'C 10 + 125'C for the LMI63/LMI63A. Note 3: Maximum rated junction temperature Is 15O'C for the LM163/LM163A. Thermal resistance, junction 10 amblen~ is 150'CIW f~r the TO-99 (H) package and 100'C/W for the ceramic DIP (D). Note 4: These lim"s are guaranteed by correlation but noll00% production tested. They are not used in dele""inioig outgOing quality levels. S 1-26 LM363A/LM363 Electrical Characteristics (Notes 5 and 6) LM363A Parameter Conditions Typ Tested Limit (Note 7) LM363 Design Lrmlt (Note 8) Typ Tested Limit (Note 7) Design Lrmlt (Note 8) 30 100 300 50 200 600 0.5 2.0 5 Units FIXED GAIN (8-PIN) Input Offset Voltage G=500 10 50 75 100 200 1.0 1.75 G=100 25 G=10 0.2 Input Offset Voltage Drift G=500 G=100 G=10 0.2 1 10 0.5 2 15 Gain Error (± 10V Swing, 2 kn Load) G=500 G=100 G=10 0.5 0.05 0.05 0.2 0.2 0.2 G=1000 10 G=100 25 G=10 0.3 50 100 150 300 1 3 G=1000 G=100 G=10 0.2 0.5 5 0.5 G=1000 G=100 G=10 1.0 0.05 0.4 1.5 0.2 1.0 1 2 20 0.4 0.35 0.3 p.V p.V p.V p.V mV mV 4 8 75 p'vrc p'vrc p'vrc 0.1 0.05 0.05 0.5 0.5 0.5 0.8 0.7 0.6 %' % % 50 200 400 100 400 800 1 3 7 p.V p.V p.V p.V mV mV PROGRAMMABLE GAIN (16-PIN) Input Offset Voltage Input Offset Voltage Drift Gain Error (± 10V Swing, 2 kn Load) 2 25 1 2 10 2.0 0.35 1.1 2.0 0.1 0.6 2.5 0.5 1.5 5 10 100 p'vrc p'vrc p.V/'C 3.0 0.7 1.7 % % % FIXED GAIN AND PROGRAMMABLE Gain Temperature Coefficient G=1000 G=500 G=100,10 Gain Non-Unearily (± 1OV Swing, 2 kn Load) G=10,100 G=500, 1000 40 20 10 0.005 0.007 ppmrc ppmrc ppmrc 40 20 10 0.01 0.02 S 1-27 0.02 0.03 0.01 0.01 0.03 0.05 0.04 0.06 % % LM363A/LM363 Electrical Characteristics (Continued) (Notes 5 and 6) LM363A Parameter Conditions LM363 Typ Tested Umlt (Note 7) Design Umlt (Note 8) Typ Tested Limit (Note 7) Design Umlt (Note 8) Units Common-Mode Rejection Ratio (-11V~VCM~13V) G=1000,500 G=100 G=10 140 130 115 126 112 100 115 100 88 130 120 105 114 94 90 104 84 80, dB dB dB Positive Supply Rejection Ratio (5V to 15V) G=1OO0, 500 G=100 G=10 130 120 100 120 105 90 110 95 78 130 120 100 110 100 85 100 95 78 dB dB dB Negative Supply Rejection Ratio (-5Vto -15V) G=1000, 500 G=100 G=10 120 106 86 110 96 80 100 86 68 120 106 86 100 85 70 90 75 60 dB dB dB nA Input Bias Current 2 5 10 2 10 20 Input Offset Current 1 2 3 1 3 5 Common-Mode Input 100 20 100 8 nA GO Re~lstance Differential Mode Input Resistance Input Offset Current Change Reference and Sense Resistance . G=1000, 500 G=100 G=10 -11V~VCM~13V 0.2 2 20 10 0.2 2 20 50 150 50 Min Max 20 GO GO GO 100 300 paN ,30 80 27 83 kO kO kO 50 35 70 30 75 Open Loop Gain GCl = 1000, 500 10 2 10 1 Supply Current Positive 1.2 1.8 2.8 1.2 2.4 Negative 1.6 2.2 3.3 1.6 2.8 Vlp.V 3.0 2.8 3.4 mA mA mA Note 5: These conditions apply unless otherwise noted; V+=V-=15V. VCM=OV. R,L=2 kll. reference,pin grounded. sense pin connected to output and Tj=25"C. Note 8: Boldface IImRs are guaranteed over lull temperature range. Operating ambient temperature range is O"C to 70"C for the LM363/LM363A, Note 7: Guaranteed and 100% production tested. Note 8: Gu,!,&nteed but not 100% tested. These limitS are not used In determining outgoing quality levels. Note 9: Maximum rated Junction temperature Is 100"C for the LM363/LM363A. Thermal resistance. junction to ambient, is 150"C/W for the TO·99(H) package and the miniDIP (N). and 100"C/W for tihe ceramic DIP (D), S1-28 Typical Performance Characteristics TA=25°C Fixed Gain and Programmable Parameter 1000/500 Units 100 10 Input Voltage Noise, rms, 1 kHz 12 18 90 Input Voltage Noise (Note 6) 0.4 1.5 10 ,.Vp-p Input Current Noise, rms, 1 kHz 0.2 0.2 0.2 pAlVHz Input Current Noise (Note 6) 40 40 40 pAp-p Bandwidth 30 100 200 kHz Slew Rate 1 0.36 0.24 VI,.S Settling Time, 0.1 % of 10V 70 25 20 ,.S Offset Voltage Warm-Up Drift (Note 7) 5 15 50 ,.V Offset Voltage Stability (Note 8) Gain Stability (Note 8) nVlvHz 5 10 100 ,.V 0.01 0.005 0.05 % Note 6: Measured for 100 seconds in a 0.01 Hz to 10Hz bandwidth. Nota 7: Measured for 5 minutes in still air. Y+ = Y- = -ISY. Warm·up drift is proportionally reduced at lower supply voltages. Note 8: Change in 1000 hours of operation at 12S·C ambient. Common·' Voltage,' ~-0.8~' ~ -1.0 !:l ~ ... -1.2 i! :!l Q ~ Q . :IE :IE Q r,rr """" ~ 3.0 2.5 • 2.0 1, , ~OI±I~V ~::: r--' """" ~ I- Supply Current VB Supply Voltage Ie Input 1'A=25°C c I- + > . 1--- - ~ 1.300 :::0 '" i'l i! i! r-r POSITIVE SUPPLY 1.200 Vs, ±,sv 1.100 Output Swing Referred to Supplies 0 . I:'""" 5 10 15 SUPPLY VOLTAGE, ± V) ...... ~ 2 ...... ~ 0 " -2 -4 .-6 -8 -55-35-15 5 25 45 65 85105125 TEMPERATURE 'DC) 20 Supply Current vs Temperature 2.4 'Is = ±5VIo ±16V 11.=0 ~-'.D ~ ... !; 1.0 0.5 > .'" :::0 4 Vs= ±15V / 6-1.5 > ~ 1.5 I i!! E1.400 V V C IL=5mA IL:" ;'A -- IL~5~A 1--0 I -1m IL-O 0 -55-35-155 25 45 65 85 105125 TEMPERATURE (DC) ...S.ifj .. 2.0 '"'":::0 1.6 i'" 1.2 Input Offset Current vs 3 Temperature Vs= ±15V -0.5 Q i... ./V !Ii 1.500 ;.... Vs= ±15V - 6 NEGATIVE SUPP~I- z ,':'35-155 25 45 65 85105125 TEMPERATURE 'DC) I I 8 1.800 1.700 ;: 1.600 , Input Bias Current vs Temperature I-- - ..... N~ATlvE JUJLY~ 7~ I.,.;' ,," .JI" Vs= ±15V 2 i'" 1 Iii 0 .. :::0 .JI' ""'" k ;;;;;; ..... ~SITIIVE , UP1Y J- - 0.8 -55-35-155 25 45 65 85105125 TE~PERAtURE 'DC) i '"Q -1 It - .... 1--0 ...~ i! -2 -3 -55-35-15 5 25 45 65 85 105125 TEMPERATURE 'DC) TL/H/5609-3 S 1-29 ~ r---------------------------------------------------------------------------------~ ~ ~ Typical Performance Characteristics (Continued) ~ CD .... Output Current Limit .... :E 50 Input Noise Voltage Js = ~1~V .... 0.35 - :tS '\ i!Ii 0.20 .. - ......... ~ g; 0.15 ~ 0.10 i5 o 0.05 -55-35-155 25 45 65 85 105125 TEMPERATURE (OC) Input Current VB Voltage Overdrive • 4 1 G-l0 -1 G=1 IV V , I 10k FREQUENCY 1Hz) / ~ ;! 0.004 I ~ /i =500.1 15 o lL /, '/J co II ~ / o B-PlN PACKAGE Vs=+15V TA = 25°C II I 4 B 0.1 lilLI, 111/0 0.01 100 10 UG-l0 G=5oo G=I00 15 / 10.002 1- - Gt loo -3 I -4 -15 -10 -5 0 5 10 INPUT VOLTAGE (V) ... "~ / G=10 10k 100 lk FREQUENCY 1Hz) Gain Enar vs Frequency· 10 TA=25°C VS= ±15V J/I / 10 lOOk 1k Gain Nan-LinearitY 0.006 ... I G=100/ V 100 i /0=500 G=1000 -2 1\ ~ III 0.25 , I i lA=25°C ~ 0.30 "POsmv£ =-~ IG Input Current Noise "1000 lk 10k FREQUENCY 1Hz) OUTPUT VOLTAGE SWING (± V) lOOk ·Trlmmed to zero at 100 Hz Positive Power Supply Relectlan Gain Enar VB FrequencY' 10 16-PIN PACKAGE Vs= ±15V TA = II l--t-nff-llf-l-l/H-I 2rf 140 II 120 ;;; :!!.100 :.. ; ~ O,=;l~ B-PlN AND BO 60 " 00/1.1J!1!1 ~I'i' Nil ! I i'" ::0 o 10 120 100 ~ 16-PlN PACKAGES iI2 BALANCED As=O !o10k VS=±15V TA=25°C E ... 2040 0.01 L...L....LJ..w/uif '-1....l.11-L...L.LLI lOOk 100 lk 10k FREQUENCY (Hz) Negative Power Supply Relectlan 140 r-rTTl,....,.-rTrr-1-n,,-,r-rm ~ iil lOOk 100 lk 10k FREQUENCY 1Hz) "" I IG~1501+ttt-Htti ~llJ~Ulr.;:l"~o:ii.;g:jjr,",,"fb:+ltl-t-l-HI G-l00 ~ H O::'-D" 80 1111 I 60~B-PI~N+PAC~KAG-HE~~~·i'~~ 40 As BALANCED Ht-t+ttf-t+fFI As=lk 20 Vs= ±15V o TA=25°C 10 100 lk 10k lOOk FREQUENCY (Hz) ·Trimmed to zero at 100 Hz Negative Power Supply Relectlan Negative Power Supply Relectlan 80 E ... 10 ! iil 60 50 1 "'"' ,, 10 100 lk ,SOURCE RESISTANCE (0) ! 1.lJIj.. 1~=I00 14~10 Bo :-. iil 60 16-PlN PACKAGE Rs BALANCED As=lk 20 Vs=±15V TA=25°C 10k o 10 lk 10k 100 FREQUENCY 1Hz) 140 130 120 co 110 ~ 100 90 BO iil 70 60 50 z E E 40 iil ?ill~ ::0 G!:;odo 120 ;;; :!!.100 ! i. Negative Power Supply Rejection 140 140 B-PIN PACKAGE 130 As BALANCED 120 '=1 kHz, Vs = ±15V =2°C z 110 G=5OO 100 G=100 90 lOOk "" I -~~\O~ 16·PlN PACKAGE (..1 OO~~ Rs BALANCED Y 1=1 kHz Vs= ±15V I TA-25°C , G-l0 , "" , I1TI , 1 10 100 lk SOURCE RESISTANCE (0) 10k TLIHI5609-4 S 1-30 Typical Performance' Characteristics CMRR with Balanced Source Resistance i CMRR with Balanced Source Resistance 160 rTTTrrT"1TTT--::==== 1-t-tttt--H-tII- ;; 140 ~ ~ iii~ 120 100 1;J;+I~~.w BoHr+R~~.~~~~-HH g 60 ~ 40 1-t-tttt--H-RI,,'-HTI'-C'l"HoI H-+tlt-'f- 20 Hr+Ht1-H#-~~~~ 2 ~ 0L...L..J...U.L..1....L.L.u.............w......1-'L..W 10 i e iz 100 lk 10k FREQUENCY (Hz) ITr 1111" 1TTr1--rTT1 i ~ 120 i!i 100 ~ BO g 60 B-PlN PACKAGE ~ I ~ ~ liE ~ l:ot:=I=*jjI:;~~Rs~-~O~W-+1-Hl ~,;" .....kttH-Htl ~~ ~~~~,~~*~~~,~ 2: BO g 60 I+~IH!-T'~ NoijJ'o~1;tH ~ 40 ~ 20 1+++1H1-+Ht-~~rf~H . Ul a: w co 60 '"22 20 ~ B ~~l;t ~ 11111 120 z ~ 100 III BO ~ i!t 60 ..., Ie !': M~ '~OkL 10 120 ~ 100 Ul BO 51 140 z .8 ~ Rsrriil~~ 2 ~ 40 ~ 20 II i'. rm'jOj o o 10 100 ;; 140 Ik 10k FREQUENCY (Hz) z iii co ~ . Ul BO ~ 60 B lOOk lOOk 'RiLl ""HIl Rs=10k 16-PIN PACKAGe 40 Rs BALANCED Vs= ±15V 20 TA=25·C 0 G=1000 100 lk 10k 10 FREQUENCY (Hz) ~ 160 H--t+fHr+ttt- 51 140 !;;: .. 120 rr:".."AR:1oIC lOOk I 1111 ~I~,~o r-:s;tu z 51 BO H-'l'1o<~f"to:5!' >1~~+-Htt 60 40 i .~~ HO ~ B lOOk 100 i!t co 20 1+-Htl-+4~H-HI+I-+'NH 100 lk 10k FREQUENCY (Hz) I ~ 0~1~~~1'0~ CMRR with Unbalanced Source Resistance B lOOk I' ~ 100 co ~ 120 ~ 100 11111 1111 ~ S 120 z ~ ~f' iii 160 rr-rrTr-r-T"TTT--"::====-O Ii '" Ri=mr~ 100 lk 10k FREQUENCY (Hz) iii' 160 ;; 140 co IIIII 10 Rs UNBALANCED Vs= ±15V TA=25·C G=500 CMRR with Balanced Source Resistance 16-PIN PACKAGE Rs BALANCED Vs=±15V TA=25·C ..tJ'00 ,~ lOOk t"t"- '!... B-PlN PACKAGEIl 40 20 lOOk '" 60 H-+tH-~~ i!t '"~ 40 H-+tH-H , ' .... 100 Ik 10k FREQUENCY (Hz) i'- , .n~ i'j:.. 60 CMRR with Unbalanced Source Resistance 111111 0 Rs 10011 60 ~ lOOk 16-PIN PACKAGE Rs UNBALANCED Vs=±15V TA=25·C G=IO o~Rs~lok U~~ 20 III II Ie .. O~Rs~IOk '" 120 B lk 10k FREQUENCY (Hz) ~I 40 '" 160 .Ii~,hoh 1111 I 140 CMRR wllh Unbalanced Source Resistance 160 co 140 co 100 iii 160 ~ 100 lk 10k FREQUENCY (Hz) :e 100 Ik 10k FREQUENCY (Hz) g ill1i" L 0 ! '"~ '"22 O~Rs~IOk 40 10 CMRR wllh Balanced Source Resistance ~I 10 ~ lOOk 16-PIN PACKAGE Rs BALANCED Vs= ±15V TA=25·C Q=.10 BO 0 III I I Rs UNBALANCED Vs= ±15V TA=25·C G=IOO CMRR with Balanced Source Resistance , Rs BALANCED Vs=±15V TA=25·C G=500 40 20 CMRR with Unbalanced Source Resistance ~~ 8-PlN PACKAGE 't"t B 120 ~,~ H.u. ~ 80 Rs=IOk i!t 60 B-PIN PACKAGE' ~ ..., "s~ , -'h!oH'~~H-+ttI ~ 100 III 100 lOOk .... 'to- tfthI ~~~~l!I- co 140 ti i!i J ·1~1 CMRR with Unbalanced ~ !160 120 co 2 .lL I I 100 Ik 10k FREQUENCY (Hz) 1+-i+1H1-+Ht- 100 lk 10k FREQUENCY (Hz) ~ Source Resistance 120 100 z ill ~~,~~·C 10 lOOk '" 160 140 ~ '"~ Rs BALANCED .Rs=IOOk ~ ... Vs= ±15V I II 40 160 rr-rrTr-r-T"TTT~~"""""",""'" 140 CMRR with Balanced Source Resistance 160 rT"1-rrrrn ;; 140 1+-Htt-t-1f-ttjH-t1Itt-~HH CMRR with Unbalanced Source Resistance E Ii a: (Continued) 20 0 .JJ~ r-:-- 6-PIN PACKAGE Rs UNBALANCEI Rrl'i1j-'" Vs= ±15V ~:,~~~C 10 100 IIII lk 10k FREQUENCY (Hz) lOOk TLlH/5609-5 S 1-31 Typical Performance Characteristics Shield Driver Loading Error Shield Driver alas Voltage' 900 1aoo w ~ !l _ 3.0 III 2.0 !.. 1.0 :;. Vs - ±5VTO ± 18V ~ i""- 700 III ,.iii !!i ..... ii! 6QO a· i!l r-... m500 20.0 ~ -3.0 ~ 10.0 !l 0 1-10.0 i 1 30 SHIELD DRIVER CURRENT (,.A) ~" 100 0 I ,., II \ II -200 1 VS-±15V 300 TA=25'C 6=1000 200 ~ 100 !l i -400 B 12 5 0 !l ~ -5 5 I ZO 40 60 !l 0 ~ 5 -5 -10 r I 10 80 E 10 5 ~ 0 -5 co -10 -15 -15 -20 -20 3D 40 ZO \ Vs= ±15V TA=25'C G=5oo 15 E 10 !!l II II 4D Large Signal Transient Response Vs- ±15V TA=25'C 6=1000 15 III ~ !l 30 20 TIME (ps) 20 -10 TIME (lIS) 5 Large Signal Transient Response J 20 10 ~ TIME (IISI Vs- ±15V TA=25'C 6=100 10 , E -20 16 Large Signal Transient Reaponse 15 Vs= ±15V TA=25'C 0=10 -15 'TIME(IIS) ZO 1\ g -200 -300 10 20 I "'" 16 Large Slgnsl Transient Response 15 -100 -,400 o 12 TIME (lIS) 400 Vs- ±15V 300 TA=25'C G=500 200 \ \ II 16 Small Signal Transient Response -300 E r:: II -4D0 12 Sma" Signal Transient Response ~ !l TIME (lIS) 400 -100 200 100 Vs= ±15V TA=25'C G=100 -300 SHIELD DRIVER CURRENT (,.AI ~ 6 1 ~ , 50 30 -3~ -10 10 30 50 SHIELD DRIVER CURRENT (,.AI Small Signal Transient Response \ -100 a -200 10 .... 400 300 w ~ -10 ..... 1'1'0 -50 -400 -30 , -3 50 Vs= ±15V TA=25'C 6=10 ZOO !l ~ ,. -30.0 11~ 10 -300 -50 I\. 8meU Signal Transient Reaponse -20.0 1 I i 1 ~ -10 400 ,/~ 6=1000 Vs= ±15V ... -2 300 ..... ~ ~ 3 -1 -50 -30 Shield DrIVer Loading Error 6=10 Vs= ±15V ... "r-. -1.0 TEMPERATURE ('C) 'Measured between either input and Its respective shield driver. ~ Shield Driver loading Error ~ 6=100 VS'= ±15V ~ -2.0 400 -55-35-155 25 45 65 85105125 30.0 (Continued) I I , \ L~: -15 -20 20 40 TlME(lISl 60 80 10 20 3D' 40 TIME(IISI TL/H/56D9-6 S 1·32 Simplified Schematic (pin numbers in parentheses are for a-pin package) 50"A SHIELD DRIVERS INPUTS -., 16 I I VOS lOOk I L~!!!~~l +9 ..L.. OPTIONAL , ~ COMPENSATION , 15(BI • {:".;,.:::::::.I""',.".___+-___________-+_..... R3 5Dk RI1 300 REFERENCE _12... (5.. 1 W'\r-....-t Rl 50k R4 3.1Dk 11 TLIH/5609-7 Theory of Operation Referring to the Simplified Schematic, it can be seen that the input voltage is applied across the bases of 01 and 02 and appears between their emitters" If RE1-2 is the resistance across these emitters, a differential current equal to VIN/RE1-2 flows from 01's emitter to 02's_ The second stage amplifier shown maintains 01 and 02 at equal collector currents by negative feedback to 04_ The emitter currents of 03 and 04 must therefore be unbalanced by an amount equal to the current flow across REI-2. Defining RE3-4 = RS + R6, the differential voltage across the emitters of 04 to 03 is equal to This voltage divided by the attenuation factor R4 R2 R3+R4 R1+R2 is equal to the output-to-reference voltage. Hence, the overall gain is given by G= Your =R3+R4 x RE3-4. VIN R4 REI-2 ---=--- S 1-33 Clamp diodes are provided to prevent zener breakdown and resulting degradation of the input transistors. At large input overdrives these diodes conduct, greatly increasing input currents. This behavior is illustrated in the liN VS VIN plot In the Typical Performance Characteristics. (The graph is not symmetrical because at large input currents a portion of the current into the device flows out the V- terminal.) Application Hints The LM163 was designed to be as simple to use as possible, but several general precautions must be taken. The differential inputs are directly coupled and need a return path to power supply common. Worst-case bias currents are only 10 nA for the LM363, so the return impedance can be as high as 100 MO. Ground drops between signal return and IC supply common should not be ignored. While the LM163 has excellent common-mode rejection, signals must remain within the proper common-mode range for this speCification to apply. Operating common-mode range is guaranteed from -11 V to + 13V with ± 15V supplies. The high-gain (500 or 1000) versions have large gain-bandwidth products (15 MHz or 30 MHz) so board layout is fairly critical. The differential input leads should be kept away from output force and sense leads, especially at high impedances. Only 1 pF from output to positive input at 100 kO source impedance can cause oscillations. The gain adjust leads on the 16-pin package should be treated as inputs and kept away from the output wiring. The input protection resistors allow a full 10V differential input voltage without degradation even at G = 1000. At input voltages more than one diode drop below V- or two diode drops above V+ input, current increases rapidly. Diode clamps to the supplies, or external resistors to limit current to 20 rnA, will prevent damage to the device. REFERENCE AND SENSE INPUTS The equivalent circJit is shown in the schematic diagram. Limitations for correct operation are as follows. Maximum differentisl swing between reference and sense pins is typically ± 15V (± 10V guaranteed). If this limit is exceeded, the sense pin no longer controls the output, which pegs high or low. The negstive common-mode limit is 1.5V below V-. (This is permissible because R2 and R4 are returned to a node biased higher than V -.) If large positive voltages are applied to the reference and sense pins, the common-mode range of the signal inputs begins to suffer as the drop across R13 and R16 increases. For example, at ± 15V supplies, VREF = VSENSE =OV, signal input range is. typically -12V to + 13.5V. at VREF = VSENSE = 15V, signal input range drops to -11V to+ 13.5V. The reference and sense pin can be as much as 10VaboveV+ as long as a restricted signal common-mode range (-10V min) can be tolerated. For maximum bipolar output swing at ± 15V supplies, the reference pin should be returned to a voltage close to ground. At lower supply voltages, the reference pin need not be hallway between the supplies for maximum output swing. For example, at V+ = + 12V and V- = -5V, grounding the reference pin still allows a + 11V to - 4V swing. For single-supply systems, the reference pin can be tied to either supply if a single output polarity is all that is required. For a bipolar input and output, create a low impedance reference with an op amp and voltage divider or a regulator (e.g., LM336, LM385, LM317L). This forms the reference for all succeeding signal-processing stages. (Don't connect the reference terminal directly to a voltage divider; this degrades gain error.) See Figure 1. POWER SUPPLY The LM163 may be powered .from split supplies from ±5V to ±18V (or single-ended supplies from 10V to 36V). Positive supply current is typically 1.2 rnA independent of supply voltage. The negative supply current is higher than the positive by the current drawn through the voltage dividers for the reference and sense inputs (typ 600 p.A total). The LM163's excellent PSRR often makes regulated supplies unnecessary. Actually, supply voltage can be as low as 7V total but PSRR is severely degraded, so.that well-regulated supplies are recommended below 10V total. Split supplies need not be balanced; output swing and input common-mode range will simply not be symmetrical with unbalanced supplies. For example, at + 12V and - 5V supplies, input common-mode range is typically + 10.5V to -2V and output swing is +11V to -4V. When using ultra-low offset versions, best results are obtained at ± 15V supplies. For example, the LM363A-500's offset voltage is guaranteed within 30 p.V at ±.15V at 25"C. Running at ± 5V results in a worst-case negative PSRR error of 10V (-15V to -5V) multiplied by 3.2X10-:- 6 (110 dB) or 32 p.V, doubling the worst-case offset. Positive PSRR results in another 10 p.V worst-case change. INPUTS The LM163 input circuitry is depicted in the Simplified Schematic. The input stage is run relatively rich (50 p.A) for low voltage noise and wide bandwidth; super-beta transistors and bias-current cancellation (not shown) keep bias currents low. Due to the bias-current cancellation circuitry, bias current may be either polarity at either input. While input current noise is high relative to bias current, it is not significant until source resistance approaches 100 kO. Input common-mode range is typically from 3V above V- to 1.5V below V +, so that a large potential drop between the input Signal and output reference ~can be accommodated. However, a return path for the input bias current must be provided; the differential input stage is not isolated from the supplies. Differential input swing in the linear region is equal to output swing divided by gain, and typically ranges from 1.3V at G= 10 to 13 mV at G= 1000. 8. Usual conflguratlon maxlml... bipolar output awing. !IV -5V"" TL/H/5609-8 b. Unequal aupplles, output ground referred. Full output swing preserved referred to supplies. FIGURE 1. Reference Connec1lons S 1-34 Application Hints (Continued) 12Y 12Y lOY -4 10k I 1 12V I I 5YDR 6.9Y 10k 7.5k I lM336-5. "::' lM329. ETC. Tl/H/56D9-9 c. Single Supply, Unipolar Output d. Single Supply, Bipolar Output FIGURE 1. Reference Connections (Continued) duce an offset shift. A simple low-pass RC filter will usually cure this problem (Figure 2). Use film type resistors for their low thermal EMF. In highly noisy environments, LC filters can be substituted for increased RF attenuation. OUTPUTS The LM163's output can typically swing within 1V of the supplies at light loads. While specified to drive a 2 kfl load to ±10V, current limit is typically 15 mA at room temperature. The output can stably drive capacitive loads up to 400 pF. For higher load capacitance, the amplifier may be overcompensated. The output may be continuously shorted to ground without damaging the device. 100· OFFSET VOLTAGE The LM163's offset voltage is internally trimmed to a very low value. Note that data sheet values are given at Tj=25'C, VCM=OV and V+ =V- =15V. For other conditions, warm-up drift, temperature drift, common-mode rejection and power supply rejection must be taken into account. Warm-up drift, due to chip and package thermal gradients, is an effect separate from temperature drift. Typical warm-up drift is tabulated in the Electrical Characteristics; settling time is approximately 5 minutes in still air. At load currents up to 5 mA, thermal feedback effects are negligible (AVOs';;'2".V at G=1000). Care must be taken in measuring the extremely low offset voltages of the high gain amplifiers. Input leads must be held isothermal to eliminate thermocouple effects. Oscillations, due to either heavy capacitive loading or stray capacitance from input to output, can cause erroneous readings. In either case, overcompensation will help. High frequency noise fed into the inputs may be rectified internally, and pro- 100· o.olt T * Film type t Ceramic disc TL/H/5609-10 FIGURE 2. Low Pass Filter Prevents RF Rectification Instrumentation amplifiers have both an input offset voltage (VIOS) and an output offset voltage (VOOS). The total inputreferred offset voltage (VOSRTI) is related to the instrumentation amplifier gain (G) as follows: VOSRTI= VIOs+VOOsl G. The offset voltage given in the LM163 specifications is the total input-referred offset. As long as only one gain is used, offset voltage can be nulled at either input or output as shown in Figures 3a and 3b. When the 16-pin device is used at multiple gain settings, both VIOS and VOOS should be nulled to get minimum offset at all gains, as shown in Figure 3c. The correct procedure is to trim VOOS for zero output at G = 10, then trim VIOS at G = 1000. 15Y Y· 15Y 10k 50k L-............,.'Irl~ \laos AOJ 50 Y- a. Input Offset Adj. lor 16·Pln Package b. Output Offset Adj. for a·Pln Package c. Input and Output Offset Adjustment for 18-Pln Package Tl/H/S609-11 FIGURE 3. Offset Voltage Trimming S 1-35 ~ r---------------------------------------------------------------------------~----- ~ :J .... :a..:J Application Hints (Continued) Because the LM163's offset voltage is so low to begin with, offset nulling has a negligible effect on offset temperature drift. For example, zeroing a 100 P.V offset, assuming external resistor TC of 200 ppmrC and worst-case internal resistor TC, results in an additional drift component of 0.08 p.V For this reason, drift spec~icalions are guaranteed, with or without external offset nulling. worst-case output offset of 50 mV, creating an input-referred error of 5 mV at G=10 or 50 p.V at G= 1000. GAIN ADJUSTMENT Gain may be increased by adding an external voltage divider between output force and sense and reference; the preferred connection is shown in Rgure 4. Since both the sense and reference pins look like 50 kO (±20 kO) to V-, impedances presented to both pins must be equal to avoid offset error. For example, a 1000 imbalance can create a External resistors connected to the reference and sense pins can only increase the gain. If ultra-low output impedance is not critical, the technique in Rgure 5 can be used to trim the gain to nominal value. Alternatively, the Vos adjustmentterminals on the 16-pin package may be used to trim the gain (Figure tOb). Increasing gain this way increases output offset error. An LM363H-l00 may have an output offset of 5 mV, resulting in input referred offset component of 50 p.V. RaiSing the gain to 200 yields a 10 mV error at the output and changes input referred error by an additional 50 p.V. rc. RI and R2 should be as low as possible to avold errors due to 50 kn .input impadance of reference and sense pins. Total resistance (R2+2RI) should be above 4 kn. however. to prevent excessive load on the LMI63 output. The exact formula for calculating gain (G) Is: . ( 1+--+2RI RI) . .. R2 5~k Go ~ preset gain The last term may be ignored in epplications where gain accuracy is not critical. The table below gives suggested values for RI and R2 along with the calculated error due to "closest value". standard I % resistors. Total gain error tolerance includes contributions from' LMI63 Go error and resistor tolerance (± 1%) and works out to approximately 2.5% in every case. . - HZ HI G~Go TLIHI560Q-12 Gain Increase R1 1.5 1.21k 2 1.21k 2.5 2k 4 1.78k 3 2k 5 2k 6 .2.49k 7 2.94k 8 3.48k 9 3.92k 10 4.42k R2 5k 2.49k 2.74k 2.05k. 1.21k 1k lk lk lk lk 1k Error (typ) +0.6% -0.2% 0 -0.3% -0.6% +0.8% +0.5% -0.9% +0.4% -0.9% -0.7% FIGURE 4. Increasing Gain 2~>B::"""" .J. + ." '" 4 (1f' . I" I __", ~OUTPUT 49.90 SENSE 2000 .10k V----.; lOOk ~--'\N\~J 15k. 111 OPTIONAL V' 9.09k REF VOl ADJ -::.. 49.9D - ~ TUHI560Q-13 FIGURE 5. Adjusting Gain (SoPln Package) Sl-36 ...r- 3: Application Hints (Continued) Heavy Miller overcompensation on the 16-pin package cim degrade AC PSRR. A large capacitor between pins 15 and 16 couples transients on the positive supply to the output buffer. Since the amplifier bandwidth is severely rolled off it cannot keep the output at the correct state at moderate frequencies. Hence, for good PSRR, either keep the Miller capacitance under 1000 pF or use the pin 15-to-ground compensation. COMPENSATION AND OUTPUT CLAMPING The LM163 is internally compensated for unity feedback from output to sense. Increasing gain with external dividers will decrease the bandwidth and increa.se stability margin. Without external compensation, the amplifier can stably drive capacitive loads up to 400 pF. When used as an op amp (sense and reference pins grounded, feedback to inverting input), the LM163 is stable for gains of 100 or more. For greater stability, the device may be over-compensated as in Figure 6. Tables I and II depict suggested compensation components along with the resulting changes in large and small signal bandwidth for the B-pin and 16-pin packages, respectively. Note that the RC network from pin B of the B-pin device to ground has a large effect on power bandwidth, especially at low gains. The Miller capacitance utilized for the 16-pin device permits higher slew rate and larger load capacitance for the same bandwidth, and is preferred when bandwidth must be greatly reduced (e.g., to reduce output noise). a. 8-Pln Package b. 16-Pin Package TLlH/5609-14 FIGURE 6. Overcompensation TABLE I. Overcompensation on 8-Pin Package Small Signal 3dB Bandwidth (kHz) Power Bandwidth (± 10V Swing) (Hz) Maximum Capacitive Load (pF) - 125 95 45 10 1 100k 15k 1.Bk 200 20 400 600 BOO 1000' 1000' - 240 170 BO 20 2 240 170 90 20 2 100k 15k 1.Bk 200 20 100k 15k 1.Bk 200 20 400 900 1200 1600' 2000' Compensation Network (Pin 8 to Ground)t Gain 100 pF, 15k 1000 pF, 5k 0.01 ,..F,500n 0.1 uF 500 100 pF, 15k 1000 pF, 5k 0.01 ,..F, 500n 0.1 uF 100 - 100pF,15k 1000 pF, 5k 0.01 ,..F, 500n 0.1 uF 10 400 900 1200 1600' 2000' "Also stable for CL "' 0.05 I'F tPin 1510 round on 16-pin package . TABLE II Overcompensation on 16 Pin Package Gain Compensation Capacitor (Pin 15 to 16) 1000 0 10 pF 100pF 1000 pF 0.01 Jl,F 100 0 10pF 100 pF 1000 pF 0.01 Jl,F 10 0 10 pF 100pF 1000 pF 0.01 Jl,F Small Signal 3dB Bandwidth (Hz) Power Bandwidth (± 10V Swing) (Hz) Maximum Capacitive Load (pF) 45k 16k 2.5k 250 25 140k 50k 7.5k 750 76 1BOk 60k 9k 900 90 45k 16k 2.5k 250 25 1000' 2000' 2500' 3000' 3000' 900 1600 2000' 2000' 2000' 600 1100 1600 2000' 2000' "Also stable for CL "' 0.05 I'F S 1-37 100k 50k 7.5k 750 75 90k 50k 9k 900 90 G) Co) ..... r- 3: Co) G) Co) Application Hints (Continued) . Because the LM163's output voltage is approximately one diode drop below the voltage at pin 15 (pin 8 for the 8-pin device), this point may be used to limit output swing as seen in Rgure 7s. Current available from this pin is only 50 ,..A. so that zeners must have a sharp breakdown to clamp accurately. Alternatively, a diode tied to a voltage source could be used as in Flflure 7b. 8.2V 50 pF to ground at both shield driver outputs. Do not use only one shield driver for a single-ended signal as oscillations can result; shield driver to input capacitance must be roughly balanced (±30%). To further reduce noise pickup, the shielded signal lines may be enclosed together in a grounded shield. If a large amount of AF noise is the problem, the only sure cure is a filter capacitor at both inputs; otherwise the AFI may be internally rectified, producing an 6.2V offset .>-....--7.5V s DC loading on the shield drivers should be minimized. The drivers can only source approximately 40 ,...A; above this value the input stage bias voltages change, degrading Vas and CMAA. While the shield drivers can sink several mA, Vas may degrade severely at loads above tOO ,...A (see Shield Driver Loading Error curve in Typical Performance Characteristics). Because the shield drivers are one diode drop above the input levels, unbalanced leakage paths from shield to input can produce an input offset at high source impedances. Buffering with emitter-followers (Rgure 8b) reduces this leakage current by reducing the voltage differential and eliminat~ any loading on the amplifier. YoUT s 6.5V .a 15V 12k lN914 lN914 , > - " , - - I V s Your s 2.5V a. Standard Configuration ~15V TUH/5609-15 FIGURE 7. Output Clamp ZOk SHIELD DRIVERS When differential signals are sent through long cables, three problems occur. First, noise, both common-mode and differential, is picked up. Second, signal bandwidth is reduced by the AC low-pass filter formed by the source impedance and the cable capacitance. Finally, when these AC time constants are not identical (unbalanced source impedance and/or unbalanced capaCitance), AC common-mode rejection is degraded, amplifying both induced noise and "ground" nOise. Either filtering at the amplifier inputs or slowing down the amplifier by overcompensating will indeed reduce the noise, but the price is slower response. The LM163's dual shield drivers can actually increase bandwidth while reducing noise. -15V-"V\.,.,.....- ZOk -15V-J\A,."... . . . . +15V b. NPN Followers to Reduce Offsets TLlH/5609-16 The way this is done is by bootstrapping out shield capacitance. The shield drivers follow the input signal. Since both sides of the shield capacitance swing the same amount, it is effectively out of the circuit at frequencies of interest. Hence, the input signal is not rolled off and AC CMAA is not degraded (Rgure 8). The LM163's shield drivers can handle capaCitances (shield to center conductor) as high as 1000 pF with source resistances up to 100 kll. FIGURE 8. Driving Shielded Cables MISCE!-LANEOUS TRIMMING The Vas adjust and shield driver pins available on the 16pin package may be used to trim the other parameters besides offset voltage, as illustrated in Figure 10. The bias-current trim relies on the fact that the voltage on the shield driver and gain setting pins is one diode drop respectively above and below the input voltage. Input bias current can be held to within 100 pA over the entire- common-mode range, and input offset current always stays under 30 pA. The CMAA trims use the shield driver pins to drive the Ves adjust pins, thus maintaining the LM163's ultra-high input impedance. For best results, identical shielded cables should be used for both signal inputs, although small mismatches in shield driver to ground capacitance (:>: 500 pF) do not cause problems. At certain low values of cable capaCitance (50 pF200 pF), high frequency oscillations can occur at high source resistance (~ 10 kO). This is alleviated by adding S 1-38 r-----------------------------------------------------------------------------~ ~ a::: ..... 0) Application Hints (Continued) If power supply rejection is critical. frequenUy only the negative PSRR need be adjusted. since the positive PSRR is more tightly specified. Any or all of the trim schemes of Figure 10 can be combined as desired. As long as the center tap of the 100k trimpot is returned to a voltage 200 mV below V+. the trim schemes shown will not greaUy affect Vas. Both the gain and DC CMRR trims can degrade positive PSRR; the positive PSRR can then be nulled out if desired. The correct order of trimming from first to last is bias current. gain. CMRR. negative PSRR. positive PSRR and Vas· .. Top Trace: Cable Shield Grounded c;:= ~:~ ~ '- Bottom Trace: Cable Shield Bootstrapped LM3830UTPUTIV/IIIV llIO ../DlV TUH/5609-17 TL/H/5609-18 FIGURE 9_ Improved Response using Shield Drivers 15V &Ok 50k lOOk 10M 3.9M 10M 1M 1M a. Bias Current b. Gain c. DCCMRR 15V 15V 100 pF d. ACCMRR ~. Negative PSRR. f. Positive PSRR TL/H/5609-19 FIGURE 10. Other Trims for 16-Pln Package S 1-39 eo:» ..... ~ a::: eo:» 0) eo:» COl) . CD COl) :E Typical Applications .... 4 mA·20 mA Two Wire Current Transmitter ....I - - Is34 COl) CD LM334v· v- :E ....I RID 35.7 HI HIGilIMPEOANCE IAIODE 1lIMSOUCER LXII6XXX PRESSURE TRANSDUCER, ETC. + lN457 3117 r-- .1 I I R6 40.211 R8 lOOk OFFSET A7 lOOk R4 Uk 111 R3 HZ Uk 1% 5DDO GAIN lN914 LM329B 6.BY All 2DDII HI 10011 1% TL/H/5609-20 The LM329 reference provides excellent line regulation and gain stability. When bridge Is balanced POUT = 4 mAl, there's no drop across A3 and A4, so that gain and offset adjustments are non-in· teractive. The LM334 configured as a zero·Te current source supplies quiescent current to circuiL All provides current IimHlng. Design Equations los=(IR6+IR7) (1 +~) =4 rnA Galn=Jl.IOUT "'~XA2+A3+A4", 10mA Jl.VIN AI A3+A4 mV when Av = LM363 voltage gain O.BBV BBmV . P,ck 1334 = ~+ AtO .. 3.B mA 1MAl( =1334 + Vz-2.4V = 26mA All IBRIDGE(MAX) .. 1334·1363-IZ " 1.SmA Precision Current Source (Low Output Current) Precision Op Amp HI C'~ CI 100 pF 0.01 >----.... COMP '::' -VOUT Select for optimum square wave response. Omit for closed loop gains above 100. Not required for instrumenl6tion amplifier configuration. TL/H/5609-21 PreCision Voltage to Current Converter (Low Input Voltage) RI 1.02k AI=A2 >--...."""INw-...... IOUT Aeq=AIllso kfl I =GVIN=GV'N OUT Aeq I kfl TL/H/5609-22 51-40 AI=A2 VIN IOUT=GRi' r-----------------------------------------------------------------------------'r i: .... Typical Applications (Continued) .... Curvature Corrected Platinum RTD Thermometer r G) Co) i: Co) G) Co) 15V >-....-----_....- ........,~loo ..VrC u tt 2.1k 1% Iktt 1% R4 R2 70. 1% 10.- Rl 1% ':' 3.5k·· "'---+:S2o. 0.1% GAIN 200t ZERO utt III R7 70. 1% 350. 1% 2. 1% 1.5M 1% --, r---I R3 105. 1% II ,I 1.8. 1% '70k and 2k should track to S ppmrC "Less than S ppm/'C drift I I tLess than 100 ppm/'C drift lOon' AT ~--------~--~----~~~ o·c R5 1.75. 1% ttThesa resistors should track to. 20 ppm/'C I I I I I This thermometer is cabable of O.OI'C accuracy over - 5O'C to + lS0·C. A unique trim arrangement eliminates cumbersome trim interactions so that zero, gain, and nonlinearity correction can be trimmed in one oven trip. Extra op amps provide full Kelvin sensing on the sensor without adding drift and offset terms found in other designs. A2 is configured as a Howland current pump, biasing the sansor with a fixed I 2 -.I current. TL/H/S609-23 Resistors R2, R3, R4 and RS from a bridge driven into balance by AI. In balance, both inputs of Al are at the same voltage. Since R6 = R7, AI draws equal currants from both legs of the bridge. Any loading of the R4/RS leg by the sensor would unbalance the bridge; therefore, both bridge taps are given to the sensor open circuit voltage and no current Is drawn. For details, request Application Note AN-304. 15V Precision Temperature Controller 15V 5V SERVO RESPONSE TEST POINT ':' , 15V 10k" I I 10k" ~ 10k" STEP GENERATOR 5. LM331 I I LM3951 0.4 RrHERMISTOR '\ ':' I "" " 15k I I I " '- ____ +- ____ ':' _ _':'_ _ +- ____ oJI !!!!.R~I'!!!B~ TUH/S609-24 ·Ultronix 105A wirewound Thermistor=Yeliow Springs #44032 Setpolnt stability=2.SX10-4'C/Hr S 1-41 ~ ~ ~ ....I r------------------------------------------------------------------------------------------, Typical Applications (Continued) Low Frequency Rolloff (AC Coupling) ..... ~ .... CD :E C1 111Hz 3.3,., 2 ...Cl(50k(l) :;~~~.I ~DD ....I 12=10011 = 100Hz Reduced DC vollsge gain attenuates offsat error and Iff noise by a factor of 100. .3D Hz Hz kHz III 11 12 TlIHf5609-25 Precision Comparator with Balancecllnputs and Variable Offset Boosted Currant Source with Umltlng 15V Y+ 15k 1,"57 3YJl IN457 IN457 -MY 10 Rl=R2 lo=GVIN R2 IMAX= Vee 1pd-15!'5 all mVoverdrive R2 AVOUT=V2+0.6V . -SOmA AVOtrr Hysteresls= G(RI +R2) =2 mV -15y-'\N\r-l5V 10k OFFSET ADJ Offset=VSENsefG ±1.3V range TlIHf5609-2B Thermocouple Amplifier with Cold Junction Compensation R9 OUTPUT =10mYf'C 11k HI 10k HI 2k III 5k 2W ZEHO -15Y ADJUST R5 2.05k III '-~_-""Y+ ~~ Ii HZ 2.1Sk III R3 R7 118 CU III C... III 50D BAIN TRIM M 2k III ':' Input protection eireuilly allows thermocouple to short 10 120 VAC withoul damaging amplifier. calibration: 1) Apply 50 mV signal in place of thermocouple. Trim R3 lor VOtrr= 12.25V. 2) Reconnect thermocouple. Trim R9 for correct output. TlIHf5609-27 51-42 Typical Applications (Continued) Synchronous Demodulator SQUARE WAVE CLOCK "" TYPICAL " INPUT SIGNAl ....-""".,.,.0:--..". SOURCES / lOOk > BA I.-I\oLAN/liC""E-4_'" lOOk / ~ CHOPPER· > ....-+-OUTPUT 2k < DC INPUT--.... / OPTICAL -71- 1 Y '=' Q2 LF13333 NORMALLY CLOSED SQUARE WAVE CLOCK TL/H/5609-2B ·Use square wave drive produced by optical chopper to run LF13333 switch inputs. Pulsed Bridge Driver/Amplifier 15V 10k· SECONDARY 10k· lk '=' 12k CLOCK 5 VOLTS 100,.. WIDE 5Hz 2k 15V 39k "TRW MAR-6 precision re.l.tor *=IN4148 tprovlde. '" SOV pulse. for bridge excitation for greater resolution without overdl.slpatlon TL/H/5609-29 51-43 ~ (D ~ :::Ill r---------------------------------------------------------------------------------, Typical Applications (Continued) ...I Precision Barometer a.06k ia.... :::Ill 4.7k ...I 15V 12k LM329 ··Parallel trim lor 28.00· Hg = OV tParaliel trim lor 32.00· Hg=4Vout "B.LH. Electronics OUTPUT #DHF-444114 Pressure Transducer 3500 Input impedance Dutput= I mV/vo~ excitation/psi TLIH/5609-30 Removing Large DC Offsets r- - - - Cl ..,O.15.F I~""""""----I.f I -=I I 100 pF" R3 15M I I L ____ .J TRANSDUCER WITH DC OFFSET C4 0.01 -Optional bandlimiting to reduce noise. Pick RICI = R2C2= R3C3/10 =..12".11 TL/H/5609-31 II = 0.1 Hz lor values shown. Integralor nulls out offset error to LM363 bias currents Ilowing into RI and R2. Removing Small DC CHsets "Optional bandllmHing to reduce noise. Low Irequency braak I lrequencyll=~=O.OI Hz Accommodates out referred offset of several vo~. Limit is set by mex TLIH/5609-32 differential between reference and sense tenninals. S 1·44 ~National PRELIMINARY ~ Semiconductor LM833 Dual Audio Operational Amplifier General Description Features The lM833 and lM833A are dual general purpose operational amplifiers designed with particular emphasis on performance in audio systems. These dual amplifier ICs utilize new circuit and processing techniques to deliver low noise, high speed and wide bandwidth without increasing external components or decreasing stability. The lM833 and lM833A are internally compensated for all closed loop gains and are therefore optimized for all preamp and high level stages in PCM and HiFi systems. The lM833 and lM833A are pin for pin compatible with industry standard dual operational amplifiers. The lM833A guarantees low noise for noise critical applications by 100% noise testing. • Wide dynamic range • low input noise voltage • High slew rate > 140 dB 4.5 nV/JHz 7 V/p.s (typ) 5 VI p.s (min) 15 MHz (typ) 10 MHz (min) 120 kHz 0.002% 0.3 mV • High gain bandwidth product • • • • Wide power bandwidth low distortion low offset voltage large phase margin Schematic Diagram 60· Connection Diagram (1/2lM833) +Vcc ""s_ _ _....._ _ _ _......_ _......_ ...._ _...._ _............. 360 OUT A + Vee -INA OUTB +IN A -"t---'.li~ -IN B L--~+INB TL/H/5218-2 Order Number lM833N See NS Package N08E TL/H/5218-1 Typical Application RIAA Preamp 33~F in---~I PHONO I CARTRIDGE: 470 . I I I IL ':'___ .JI 16k 2DDk 390 T'DO~ TLlH/5218-3 I En = 0.33/-,V AWeighied SIN S 1-45 =I Ay=35dB = 90 dB kHz A Weighted, VIN=10 mV @1=lkHz Absolute Maximum Ratings Supply Voltage VcclVEE Differential Input Voltage (Note 1) V,O Input Voltage Range (Note 1) V'C Power Dissipation (Note 2) Po Operating Temperature Range TOPR -40 -85·C ±15V Storage Temperature Range TSTG -60 - 150·C DC Electrical Characteristics (TA = Symbol 25"C, Vs = ±15V> Parameter Vas Input Offset Voltage los Input Offset Current 500'mW ±18V ±30V Conditions Min Typ' Rs = 100 Ie Input Bias Current Av Voltage Gain RL = 2kO, Va = ±10V YOM Output Voltage Swing RL = 10kO RI- = 2kO Max Units 0.3 5 mV 10 200 nA 500 1000 nA 90 110 dB ±12 ±10 ±13.5 ±13.4 V ±12 V VCM Input Common-Mode Range ±14.0 V CMRR Common-Mode Rejection Ratio Y,N = ±12V 80. 100 dB PSRR Power Supply Rejection Ratio Vs = 15-5V, -15- -5V 80 100 la Supply Current Va = OV, Both Amps AC Electrical Characteristics (TA = Symbol 25·C, Vs = ± 15V, R~ = Conditions Parameter dB 5 Typ 7 Slew Rate RL = 2kO 5 GBWP Gain Bandwidth Product f = 100kHz 10 en1 LM833A Equivalent Input RIAA, Rs = 4700 rnA - 2 kO) Min SR 8 Max V/p,s 15 0.5 Units MHz 0.8 p.V Noise Voltage (Note 3) Design Electrical Characteristics (TA = 25·C, Vs = ± 15V) The following parameters are not tested or guaranteed. Conditions Typ Units 2 p'vrc 0.002 % Symbol Parameter AVos/AT Average Temperature Coefficient of Input Offset Voltage THO Distortion en 2 Input Referred Noise Voltage 2 RS = 1000, JISA 0.5 p.V en 3 Input Referred Noise Voltage 3 Rs = 1000,f = 1 kHz 4.5 nV/.JHz in Input Referred Noise Current f = 1 kHz 0.7 pAl.jHz PBW Power Bandwidth Vo = 27 V PP ' RL = 2 kO, THO';; 1% 120 kHz fu Unity Gain Frequency Open Loop 9 MHz cf>M Phase Margin Open Loop 60 deg Input Referred Cross Talk f=20-20kHz -120 dB RL = 2 k~, f = 20-20 kHz VOUT = 3 Vrms, Av = 1 Note 1: if supply voltage Is less than 15V, Ills equal 10 supply voltage. Nole 2: This Is Ihe permissible value al TA ,; 8S'C. Nota 3: Only Ihe LM833A I. noise lested and guaranteed. See "Noise Measuremenl Clrcuil" for test condllions. , S 1-46 Typical Performance Characteristics _1000 Maximum Power Dissipation vs Ambient Temperature 800 ! 700 ~ 800 li: 500 ::! a: 400 i5 1 400 Co) ~ -, :E 200 \ ~. ill = 300 0 -50 50 100 TEMPERATURE {OC} ;!; , lal~s=- :-;;- ---- ---~. i"""" ~ , ~. o o ! 110 - ~ w ~ 5! 2: 100 ~ z ~ ~ 60 '"> 40 !:3 " ~L '- 100 W to ....'" > 90 !. -uo 10 100 lk 10k lOOk 1M 10M FREQUENCY {Hz} ...= 20 ~ ~ 10 . . . ~ !!l ~ 1 30 21 -150 100 - --- !:3 ¥ m -90 i,....ooo' 90 80 5 10 15 SUPPLY VOLTAGE {±V} TLlH15218-8 1""'" -120m 20 o -60 110 ~ Vs= ±15V '=100 kHz Gain Bandwidth vs Supply Voltage '"'" "z :i ~ ~ ...... 30 '-l:"'"A=~2'::5'-:OC;"";;'-r-"""-'-" '=100 kHz',_-+--f--If--l ~ I- - !. 20 1--+-+--+--+--+--1 ~. r- ~- ~ . o -50 -25 0 25 50 75 100 125 TEMPERATURE {OC} TL/H/5218-10 TLlH/5218-11 S 1-47 20 TLIH/5218-9 Gain Bandwidth Product vs Ambient Temperature ·~HAS~- 1'- TA=25°C RL=2 kn to 80 -50 -25 0 25 50 75 100 125 TEMPERATURE {OC} 20 '" GAIN 80 ~ r-.. - 20 DC Voltage Gain vs Supply Voltage VS=±15V RL=2 kll I'~ z Vs= ±15V R,L=2,kn -30 10 15 SUPPLY VOLTAGE {±V} TlIH15218-6 120 120 Voltage Gain & Phase vs Frequency iii 5 TL/HI5218-5 ~ '" 200 DC Voltage Gain vs Ambient Temperature 10 15 SUPPLY VOLTAGE {± V} I- 100 o TL/H/5218-7 120 '" -50 -25 0 25 50 75 100 125 TEMPERATURE {OC} Supply Current vs Supply Voltage TA=25°C RL=CO.-- 400 300 o 150 --.... 500 I- ~ 100 TA=25°C ~ 600 I- z 200 Input Bias Current vs Supply Voltage 700 ...= TUH/5218-4 10 800 Vs= ±15V '[ 600 if ~ 600 f! Input Bias Current vs Ambient Temperature ~ :i ~ 10 1--+-+--+--+--+--1 10 15 SUPPLY VOLTAGE {± V} 20 TL/H/5218-12 Typical Performance Characteristics (Continued) Slew Rate VB Slew Rate VB Ambient Temperature J ,10 Vs=±15V 1 9 RL=2 kllAv=l "~ ..~ 8 FALUNG-I;;- ~ 7 . ~ w Ii ~ '" ".'$f 6 5 4 .IL~ + Vo 3 , 2i 2 1 T 0 -50 -25 ,0 25 50 75 100 125 TEMPERATURE ('CI ~ ~ w i ~ '" -~ 15 20 ~ t\I ~ c 5 ... -5 ...~ > ~ k-"" Vs=±15V RL=10 kll 14 w /. / ~YolM_ -YOM r--.. 5 40 --- _ 2k 20 f0 100 2 '-T '" ~ 10k lOOk 1M FREQUENCY (Hzl lk Jt>f. \ .... 10k lOOk 1M FREQUENCY (Hzl 10M +PSRR 100 80 Vs = ±15V f' ,-PSRR 60 40 0 100 lk "" 10k lOOk 1M FREQUENCY (Hzl 10M TL/H/5218-18 Distortion vs Frequency .""~ RL=2kll - - '=' lk 5 TL/H/5218-17 1 Vo- 2 \ \ 10 20 10 -50 -25 0 ~5 50 75 100 125 TEMPERATURE ('CI 20 ~,- - 15 120 PSRR vs Frequency 11 I I Vs=f15V 20 TLlH/5218-15 ~ c 10 15 SUPPLY VOLTAGE (± VI 80 '-60 20 l!: ::::0 ....... THO~l% 0 100 S 12 CMR vs Frequency 100 '" c '" TL/H/5218-16 :E l!: ::::0 2i ! -20 .. ::::0 c ~ -15 ...'" c Vo > is -10 120 ~ ...> Maximum Output Voltage va Ambient Temperature :.i! 13 0 ~ Vs=±15V RL=2k1l 25 TL/H/5218-14 Maximum Output Voltage vs Supply Voltage ..".,.i"'" 30 .J. , TL/H/5218-13 TA=25'C 15 RL=10kll 10 Power Bandwidth Supply Voltage 10 1A=25'C / / 9 RL=2kll+ JFALUNG 8 Av-l 7 6 5 4 .IL'~ + 3 2 1 T 0 5 10 15 SUPPLY VOLTAGE (± VI 10M ~ 0.1 z . + "- c ...!i1 Vo 2i c, '"is T 0.01 1 11 1 Yo=3Vrms I~ 0.001 10 Yo =1 Vrms 100 lk 10k lOOk ' FREQUENCY (Hzl TL/H/5218-19 TL/H/5218-20 .J I S 1-48 Typical Performance Characteristics (Continued) Spot Noise Voltage vs Frequency 10 Spot Noise Current vs Frequency LM833~;:fTA 25'C Vs +15V 10 Input Referred Noise Voltage vs Source Resistance 100 LM833A TA =25'C Vs +15V r--....,..,~-~,.....,-r-,-, I"- 0.2 0.1 1 10 100 lk 10k FREQUENCY (Hz) lOOk 10 100 lk 10k FRE1IUENCY (Hz) lOOk 0.1 '-'--'-.J....JL-.l-'-..I.-"':'::"=':= 100 lk 10k lOOk 1M . SDURCE RESISTANCE (0) TL/H/521B-22 TL/H/521B-21 TL/H/521 B-23 Noninverting Amp Noninverting Amp TIME (0.2 ps/DIV) TIME (2 pI/DIV) TL/H/521B-24 TLlH/521B-25 Inverting Amp TIME (2 pI/DIV) TLlH/521B-26 Application Hints The LMB33 is a high speed op amp with excellent phase margin and stability. Capacitive loads up to 50 pF will cause little change in the phase characteristics of the amplifiers and are therefore allowable. Capacitive loads greater than 50 pF must be isolated from the output. The most straightforward way to do this is to put a resistor in series with the output. This resistor will also prevent.excess power dissipation if the output is accidentally shorted. S 1-49 Noise Measurement Circuit Com.,tete ahIeIdi"9 Is required to pr8vant Induced pick up lrom external souices. Always check with 08CiDoscope lor power line noise. +Vee -'IE! AVERAGE RESPONDING AC VOLT METER 181c lk 310 ~ lk _ _ _ _ _ _ _ _ _ _ _ _~"~_ _ _ _ _ _ _ _ _ _~_ _ _ _~._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J FLAt AMP. 40 d8 + 40 dB RIAAPREAMP 35d8.I=lllHz TUH/5218-27 TOtal Gain: 115 dB Of = 1 kHz Input Referred NoIse Voltage: = VO/580,OOD (V) en RIM Preamp VoJtage GaIn, RIAA Deviation V8 Frequency i ~ ~ 50 ~ 40 ~ ~ 30 20 Flat Amp Voltage Gain V8 Frequency 90 Vo=OdBv YIN .. 10 mV 35.0 dB. 1=1 kHz r; ~ '- ~ ! ii ~ ~ ! !i! Iii 'i :~ HIIII 20 10 60 50 !i! 40 30 11111 111111 1 100 lk FREQUENCY (Hzj 20 10 10k 20 100 lk 10k FREQUENCY (Hz) lOOk TL/H/5218-28 TUH/521'-28 S 1-50 Typical Applications NAB Preamp NAB Preamp Voltage Gain vs Frequency 70 H-f.HIlll-H-I+VJ. =10 mV 60 looIoil!ffill-f+1+34.5 dB, 1=1 kHz ~ 50 ;;: 40 '"w !''"§ . 30 > 20 z Vo Av = 34.5 F = 1 kHz En = 0.381'V 10 0 20 A Weighted 200k 100 10k 20k lk FREQUENCY (Hz) Tl/H/5218-31 200 • + TL/H/521B-30 Balanced to Single Ended Converter Sine Wave Oscillator Adder/Subtracter Yl-JV --Va; TL/H/5218-39 S 1·52 TL/H/5218~40 ,-------------------------------------------------------------------------, r !: Typical Application (Continued) C» Co) Co) Tone Control 1 1 fL = 21TR2Cl' fLB= 21TR1Cl Al 11k V, BOOST -BASS-CUT A2 lOOk Cl 0.05,F Al 11k 1 1 fH= 21TR5C2' fHB 21T(R1+2R3)C2 Illustration Is: fL =32 Hz, fLB=320 Hz fH=11 kHz, fHB=I.1 kHz Cl 0.05,F 2DdB---...... 17 dB -----'k R3 11k 3 d B - - - - + - '.... R5 3.6k C2 0.005,F v. R4 500k BOOST -TREBLE-CUT -2DdB---.J TLlH/5218-41 TLlH/5218-42 Balanced Input Mlc Amp If R2=R5, R3=R6, R4=R7 2R2) -(V2-Vl) R4 vo= ( 1+-Rl R3 v, R4 10k R3 10k 10 Band Graphic Equalizer Illustration is: VO= 101(V2-Vl) - - -, - r CUT '" "::' C2 Rl 200 v. R5 10k V, R6 10k Vo 3' C1 R1 R7 10k ":" I "::' V2 L TLlH/5218-43 "::' fo(Hz) C1 C2 R1 R2 32 64 125 250 500 1k 2k 4k 8k 16k 0.12/LF 0.056/LF 0.033/LF 0.015/LF 8200pF 3900pF 2000pF 1100pF 510pF 330pF 4.7/LF 3.3/LF 1.5/LF 0.82/LF 0.39/LF 0.22/LF 0.1/LF 0.056/LF 0.022/LF 0.012/LF 75kO 68kO 62kO 68kO 62kO 68kO 68kO 62kO 68kO 51kO 5000 5100 5100 4700 4700 4700 4700 4700 5100 5100 At volume of change = ± 12dB Q=1.7 Reference: "AUDIO/RADIO HANDBOOK", National Semiconductor, 1980, Page 2-61 S 1-53 Section 2 Comparators Comparators Section Contents Voltage Comparators s s LP165/LP365 Micropower Programmable Quad Comparator. ...•............•............•...............•...... 2-1 LP311 Voltage Comparator .•...•........•....•..••....•.•................................................... 2-9 LP339 Ultra Low Power Quad Comparator ..........................................••.......•....•.••...•...• S 2-11 r- ~National PRELIMINARY ~ Semiconductor '1J Co) Q) CI1 General Description Features The LP165 series consists of four independent voltage comparators. The comparators can be programmed, four at the same time, for various supply currents, input currents, response times and output current drives. This is accomplished by connecting a single resistor between the Vee and ISET pins. These comparators can be operated from split power supplies or from a single power supply over a wide range of voltages. The input can sense signals at ground level even with single supply operation. The unique output NPN transistor stages are uncommitted to either power supply. They can be connected directly to various logic system supplies so that they are highly flexible to interface with various logic families. • Single programming resistor to tailor power consumption,' input current, speed and output current drive capability • Wide single supply voltage range or dual supplies (4 VDC to 36 VDC or ± 2.0 VDC to ± 18 VDcl • Low supply current drain (10 p.A) and low power consumption (10 p.W/comparator)@lsET=0.5 p.A Vcc=5VDC • Uncommitted output stage-selectable output levels • Output directly compatible with DTL, TIL, CMOS, MOS or other special logic families • Input common-mode range includes ground • Differential input voltage equal to the power supply voltage Application areas include battery power circuits, threshold detectors, zero crossing detectors, simple serial AID converters, VCO, multivibrators, voltage converters, power sequencers, and high performance V IF converters, and RTD linearization. Connection Diagram Dual·ln·Line Package y+ OUT3 OUT4 Y- OUT2 Dun Y+ -IN4 +IN3 -IN3 Yc TL/H/S023-1 ISET -INt +IN2 TOPYIEW TLIH/S023-2 Programming Equation Order Numbers LP165D,N or LP365D,N See NS Packages D16A, N16A ISET= Q) , r- LP165/LP365 Micropower Programmable Quad Comparator Typical Connection '1J ..... CI1 (V+)-(V-)-1.3V R SET I SUPPLY::::: 22 x ISET S2-1 AbsQlute Maximum Ratings Supply Voltage 36Vocor ± 18Voc Differential Input Voltage ± 36 Voc Input Voltage (Note 1) -0.3Vto +36Voc Output Short Circuit to Ve (Note 2) VOUT wHh Respect to Ve DPackage 670mW Power Oissipation (Note 3) T,max Continuous ve-7V:S;VOUT:s;ve+ 36V 15O"C 115"C 6jA 90"C/W 9QoC/W Operating Temperature Range Storage Temperature Range Lead Temperature (Sql!1e~ng, 10 seconds) (Note 4) (Note 4) Electrical Characteristics (Note 5) LowpowerVs=5V,ISET=1q p.A LP165 Symbol Paramet,r Conditions Typ -65"C:S;TA:S;150"C 300"C 300"C \ LP36&A Te.ted Design Limit Umlt (Note 6) (Note 7) NPackage 500mW LP365 Tested Typ Design Tested Design Units UmH Typ Limit Umlt (Umlt) U!"H (Note 6) (Note 7) (Note 8) (Note 7) ,9 Vos Input Offset Voltage VCM= OV, Rs=100 1 3 6 1 3 8 3 6 mV (Max) los Input Offset Current VCM;""OV 2 20 50 2 20 50 4 25 75 nA (Max) 18 Input Bias Current VCM=OV 10 50 125 10 50 125 15 75 200 nA (Max) AVOL Large Signal Voltage Gain RL =100k 500 50 500 50 50 300 25 25 VlmV (Min) VCM Input CommonMode Voltage Range 0 0 0 0 0 V (Max) 3 3 3 3 3 V (Min) CMRR Common-Mode Rejection Ratio 0:S;VCM:S;3V 85 75 70 85 75 70 80 75 70 dB (Min) , PSRR Supply Voltage Rejection Ratio ±2.5V:S;Vs, :S;±3.5V 75 65 75 65 85 70 65 85 dB (Min) IS Supply Current Alllnputs=OV, 215 RL =CO 250 300 215 250 300 225 275 300 p.A (Max) VOH Output Voltage High Vc=5V, Ve';"OV, RL =100k 4.9 4.5 . 4.9 4.5 4.9 4.5 VOL Output VoHage Low Ve=OV 0.4 0.4 0.4 0.4 0.4 iSINK Output Sink Current Ve=OV, VO=0.4V iLEAK tR V (Min) V (~ax) 2.4 1.2 0.8 2.4 1.2 0.8 2.0 0.8 0.4 rnA (Min) Output Leakage Vc=5V, Current Ve=OV 2 50 5000 2 50 5000 2 100 5QOO nA (Max) Response TiJlle Vcc=5V, Ve=OV, RL =5k, CL =10 pF (Note 8) 4 4 4 i i S2-2 p.S r- Electrical Characteristics (Continued) (Note 9) High power Vs = LP165 Symbol Parameter Conditions "V eft ..... ± 15V. ISET= 100 ",A LP365A ~ r- LP365 Units Tested Design Tested Design Tested Design (Limit) Typ Limit Limit Typ Limit Limit Typ Limit Limit (Note 6) (Note 7) (Note 6) (Note 7) (Note 6) (Note 7) VOS Input Offset Voltage VCM= OV. Rs=100 1 3 6 1 3 6 3 6 9 mV (max) los Input Offset Current VCM=OV 5 50 100 5 50 100 10 90 200 nA (Max) Is Input Bias Current VCM=OV 60 200 500 60 200 500 80 300 500 nA (Max) AVOL Large Signal Voltage Gain RL =15k 500 100 500 100 100 500 100 100 VlmV (Min) VCM Input CommonMode Voltage Range -15 -15 -15 -15 -15 V (Max) 13 13 13 13 13 V (Min) CMRR Common-Mode Rejection Ratio -15VS:VCM S:13V 85 75 70 85 75 70 80 75 70 dB (Min) PSRR Supply Voltage Rejection Ratio ± 10VS:VS S:±15V 80 70 80 70 70 75 70 70 dB (Min) IS Supply Current All Inputs = OV. RL=co 2.6 3 3.3 2.6 3 3.3 2.8 3.5 3.7 rnA (Max) VOH Output Voltage High Vc=5V. VE=OV. RL =100k 4.9 4.5 4.9 4.5 4.9 4.5 V (Min) VOL Output Voltage Low VE=OV 0.4 0.4 0.4 0.4 0.4 V (Max) ISINK Output Sink Current VE=OV. VO=O.4V ILEAK Output Leakage Vc=15V. VE= -15V Current 10 8 5.5 10 8 5.5 7.5 6 4 rnA (Min) 5 50 5000 5 50 5000 5 50 5000 nA (Max) Response Time Vcc=5V. 1.0 1.0 1.0 ",s VE=OV. RL =5k. CL=10pF (Note 8) Note 1: The input vol'!'ge Is not allowed to go 0.3V above V+ or -0.3V below V- as this will tum on a parasitic transistor causing large currents to flow through the device. Note 2: Short circuits from the oulput to V+ may cause excessive healing and eventual destruction. The current in the oulputleads and the VE lead should not be allowad to exceed 30 mAo The oulput should not be shorted to V- if VE<:(V-) + 7V., Note 3: For operating at elevated temperatures, these devices must be derated based on a thermal resistance of 81A and TI max. TI = TA+ 8jAPo, Note 4: The LP165 may be operated from -55'C<:TA<: + 125'C and the LP365A1LP365 may be operated from O"C<:TA<: + 70"C. Note 5: Boldface numbera apply at temperature extremes. All other numbers apply at T... = TI = 25·C. V+ = 5V, V- = OV, ISET= IOI-'A, RL = lOOk, and Vc= 5V as shown in the Typical Connection diagram. Note 6: Guaranteed and 100% production tested. Note 7: Guaranteed (but not 100% production tested) over the operating temperature and supply voltage ranges. These limits are not used to calculate outlloing quality levels. Note 8: The response time speCified is for a 100 mV input step with 5 mVoverdrive. Note 9: Boldface numbera apply attemperature extremea. All other numbers apply alTA = Tj = 25"C. V+ = + 15V, V- = -15V, ISET = 100 I-'A, RL = lOOk, and Vc= 5V as shown In the Typical Connection diagram. tR S2-3 "'D w en en U) ~ ~ r------------------------------------------------------------------------------------Typical Performance Characteri~tics is Supply Current vs Supply Supply Current vs 10 Voltage ...a. -po 10 Temperature i i 1.0 Ii B iiii 0·1 I... :> ! 1.0 E iii 0.1 u..u...w...I....L.I....L..L.J...u...u...... 10 ISET (pAl 100 o 1000 - :::0 ~ 100 6 ~~ Response Time Negative Transition E ~ ~ 5 mV OVERDRIVE I ~ I I I ISET=10 ,.A ~ 100 10 10 0.1 100 OUTPUT SINK CURRENT (mAl l!100 \ 0 2S 50 T5 100 125 TEMPERATURE ('C) 1'5 0.1 !i5 10 !sET (pAl Im=10pA Z i!5 S 10 I-- r-- ;- ~~ :::0 ISET~l00 pA 1000 ~ I... ~ I- 0.1 -55 -25 ~ 10 ~ ID 8 - TOTAL SUPPLY VOLTAGE (V) 1000 ; 4 I- '1.0 E iii ISET=10 ,.A " HIIIH n u m I- - i Im~100,.A ~ ISET=100pA 1 10 100 ISET (,.AI Response Time Positive Transition 6 5 mV OVERDRIVE flSETI=l~ J- f - I I 4 I 3 tt1 i =ISET=100 ,.A f-~- w 100 ~ ~ >- 50 0 E -50 ;! 4 TIME (pSI 4 TIME (pS) Response Time Negative Transition Response Time Positive Transition 4.5 r--T-TTi-mrlr""-r.,..,~rm 4.01\ 3.5 P~H-,"++++Hfl----t-t-HtHH ~ 3.0 ...~ 2.5 I'W ",~~+H-+I#--H+ltHH I !w i!! 2.0 N 1.5 1-.f-3~~+I--+-H+I1f+H 4.5 4.0 3.5 3.0 2.5 1\.5 mV OVERDRIVE 2.0 10mV 1.5 1'1' II: 1.0 0.5 o 10 III 50mV 100 isET (,.AI 1000 TL/H/5023-3 52-4. r- "'U .... U1 r""'U Typical Applications G) Gated 4·Phase Oscillator Voltage Comparator (0) G) 5V U1 470k "X" 5V 5V 22k lOOk 2k 5V 5V lOOk 22k lOOk 4.7k OUTPUTS 5V lOOk ":" 2k Il ":" 270 pF 5V 5V 4.7k 2k 15 5V 5V 4.7k 5V r O.lpF 20k 14 5V TL/H/5023-4 f~20 Vour TL/H/5023-5 kHz f~ _ _ l_ 1.6eRteCt If you choose V.~25 mV, 75 mV, or 125 mV, then VOUT will fall if all of the other three outputs are low. All four phases run when X is low. When X is high, oscillation stops and power drain is zero. 82-5 Yo, % or U) r---------------------------------------------------------------------------------~ CD C") a. .... ..... Typical Applications ....~ (Continued) Ordinary Hysteresis ~ Hysteresis from Emitter Y+ Y+ 47k Uk o/-~"''''-VOUT 1M TL/H/5023-6 TL/H/S023-7 It is a good practice to add a few millivolts of positive feedback to prevent oscillation When the input voltage is near the threshold. Positive feedback from the emitter can also prevent oscillations when VIN is near the threshold. Bar-Graph Display Level-Sensitive Strobe 5V 5Y 5V 5V 150k 4B.4k IIJ 47k 470k O.4Y ....--1-~ YHEFft lk IIJ 5V STROBE 2k O.3Y ....--1-:..t lk 5V IIJ 2k O.2Vt---1.......;~ 15 lk 5Y IIJ 2k O.lYt--....:.~ 14 lk TUH/5023-B TL/H/S023-9 The positive feedback from pin 16 provides hysteresis. Comparators B, C, and 0 do not respond until activated by the signal applied to comparator A. 52·6 Typical Applications (Continued) Slow Op Amp (Inverter) Slow Op ¥tP (Unlty-Galn Follower) Y+ Y+ ZOk V+ Y+ 47k V+--~~~------~ 1. 18 TUH/5023-10 TUH/5023-11 RS = V+/20".A RS = V+/20".A Unlike most comparators, the LP165 can be used as an op amp, R-C dampipg networks are used. ~ suitable The LP18S can also be used as a hlgh-Input-Impedance loUower-amplifler with the damping components shown. ',' Chopping Outputs Low Battery Detector VaAT 5V Uk 3 5Y Uk Uk 1011 5Y Uk 1M 15 LOW MlTERY .--~~ ALARM 1.11. 5Y 4.7k TUH/5023-13 14 IS GI 6V = 4Sp.A Is GI 3.8V ~ 1 p.A 1=3kHz Comparator A detacts when the supply voltage dropa to 4V and enables comparator B to drive a piezoelectric alarm. TUH/5023-12 Chopping the outputs by modulating the ISET current allows dais to be transmitted via opto-couplers, translormers, etc. 52-7 ~ ~----------------------------------------------~--------------------, CD ~ .... . ...I Simplified Schematic ....~ r-------e-------~----------..------------------~v+ ~ (+) CURRENT SOURCE CONTROL TUH/5023-14 Current sources are programmed by ISET VE Is common to all 4 comparators 52-8 r-------------------------------------------------------------------------,r"U (0) PRELIMINARY ..... ..... ~National ~ Semiconductor LP311 Voltage Comparator General Description Features The LP311 is a low power version of the industry-standard LM311. It takes advantage of stable high-value ion-implanted resistors to perform the same function as an LM311, with a 30:1 reduction in power drain, but only a 6:1 slowdown of response time. Thus the LP311 is well suited for batterypowered applications, and all other applications where fast response is not needed. It operates over a wide range of supply voltages from 36V down to a single 3V supply, with less than 200 p.A drain, but it is still capable of driving a 25 rnA load. The LP311 is quite easy to apply without any oscillation, if ordinary precautions are taken to minimize stray coupling from the output to either input or to the trim pins. (See the LM311 section of the Linear Databook.) • • • • • • • • Low power drain, 900 p.W on 5V supply Operates from ± 15V or a single supply as low as 3V Output can drive 25 mA Emitter output can swing below negative supply Response time: 1.2 p.s Same pin-out as LM311 Low input currents: 2 nA of offset, 15 nA of bias Large common-mode input range: -14.6V to 13.6V with ± 15V supply Auxiliary Circuits Strobing Offset Balancing R2 15k V· TL(H/5711-2 TL/H/5711-1 Note: Do not ground strobe pin. Connection Diagrams Metal Can Package Dual-In-Llne Package V· GROUND V· INPUT ---.r-L_".... 6 BALANCEI STROBE 6 BALANCEI STROBE INPUT VTOPV1EW VTL/H/5711-3 OUTPUT BALANCE TOP VIEW Nol.: Pin 4 connected to case. TL/H/5711-4 Order Number LP311H See NS Package Number HOSC Order Number LP311N See NS Package Number NOSB 82-9 Absolute Maximum Ratings Total Supply Voltage (V84) Collector Output to Negative Supply Voltage (V74) Collector Output to Emitter Output Emitter Output to Negative Supply Voltage (V14) Differential Input Voltage Input Voltage (Note 1) Power Dissipation (Note 2) 36V 500mW 10 sec O·Cto 70·C Output Short Circuit Duration Operating Temperature Range 40V 40V ±30V ±30V ±15V -65·C to 1500C , Storage Temperature Range Lead Temperature (Soldering, 10 seconds) 300·C' Electrical Characteristics (Note 3) Typ Max Units Input Offset Voltage (Note 4) TA=25·C, RsS;100k 2.0 7.5 mV Input Offset Current (Note 4) TA=25·C 2.0 25 nA 15 100 Conditions Parameter Input Bias Current TA=25'C Voltage Gain TA = 25·C, Min RL =5k 40 200 nA V/mV Response TIme (Note 5) TA,=2S·C 1.2 Saturation Voltage (Note 6) VINS; -10 mY, IOUT=25 mA TA=2S·C 0.4 1.5 p.s V Strobe Current (Note 7)" TA=25·C 100 300 p.A Output Leakage Current VIN~10 mY, VOUT=35V TA=25·C 0.2 100 .nA Input Offset Voltage (Note 4) RsS;100k 10 mV Input Offset Current (Note 4) . 35 nA Input Bias Current 1S0 nA + 13.7, -14.7 V+-1.S V Input Voltage Range V-+O.S Saturation Voltage (Note 6) V+~4.SV, V-=OV VINS; -10 mY, ISINKS;1.6 mA 0.1 0.4 V Positive Supply Current TA=2S·C 1S0 300 p.A TA=25·C 80 180 p.A Negative Supply Current Minimum Operating Voltage V TA=25·C 3.0 3.5 Note 1: This rating applies for ± ISV supplies. The posHive input voltage limit is 30V above the negative supply. The negative input voltage limit Is equal to the negative supply voltage or 30V below the positive supply, whichever is less. Note 2: The maximum junction tamperature of the LP3tt is 8S·C. For operating at elevated temperatures, devices in the TO-S package must be deratad based on a thermal resistance of ISO'C/W, junction to ambient, or 4S·C/W, iunction to case. The thermal resistance of the dual·ln-line 'package is 160'C/W, junction to ambient Note 3: These specifICations apply for Vs = ± t5V and O'C"TA "WC, unless otherwise specified. The offset voltage, offset current and bias current specifications apply for any supply voltage from a single 4V supply up to ± t5V supplies. Note 4: The oIIset voltages and offset currenta given are the maximum values required to drive the output wHhin a volt of either supply wHh t rnA load. Thus, these parameters define an error band and take into account the worst-case effects of voltage gain and input impedance. Note 5: The response time specified is for a tOO mV Input step wHh 5 mV overdrive. Note 6: Saturation voltage specification applied to collector·emiller voltage (V7-t) for VCOLLECTOR " (V+ -3V). Note 7: Do not short the strobe pin to ground. It should be current driven, tOO ,.A to 300 ,.A. S2-10 ~Natlonal PRELIMINARY ~ Semiconductor LP339 Ultra-Low Power Quad Comparator General Description ,The LP339 consists of four independent voltage comparators designed specifically to operate from a single power supply and draw typically 60 IJ.A of power supply drain currant over a wide range of power supply voltages. Operation from split supplies is also possible and the ultra-low power supply drain current Is independent of the power supply voltage. These comparators also feature a common-mode range which includes ground, even when operated from a Single supply. Applications include limit comparators, simple analog-to-ciigital converters, pulse, square and time delay generators; VCO's; multivibrators; high voltage logic gates. The LP339 was speCifically designed to interface with the CMOS logic family. The ultra-low supply current makes the LP339 valuable in battery powered applications. Advantages • Ultra-low power supply drain suitable for battery applications • • • • Single supply operation Sensing at ground Compatible with CMOS logic family Pin-out identical to LM339 Features • Ultra-low power supply current drain (60 IJ.A) - independent of the supply voltage (75 IJ.W/comparator at +5 VOC) 3 nA Low Input biasing current ±0.5 nA Low input offset current ±2mV Low input offset voltage Input common-mode voltage includes ground Output voltage compatible with MOS and CMOS logic High output ,sink current capability (30 mA at Vo=2 Voc) . • Supply Input protected against raverse voltages • • • • • • Schematic and Connection Diagrams Dual-In-Une Package V· OUTPUT 3 OUTPUT 4 14 13 r-t...::.....-0U1Nf -INPUT---=---II--+-=~~ 1 2 OUTPUT 2 OUTPUT 1 TLlH/5226-1 Typical Applications (V+ = Y· INPUT 1 - INPUT 1+ INFUT 2- INPUT2+ TOPYIEW Order Number LP339 See NS Packagee N14A. M14A 5.0 Voc) Belle Comparator TLlH/5228-2 Driving CMOS Y· V· +YlNt?J3Dl1 1I4lP3U +YllEF TLlHl5226-3 TLlH/5228-4 S2-11 i Absolute Maximum Ratings Supply Voltage Input Current VIN < - 0.3 Voc (Note 3) 36 Vocor ±18 VOC Differential Input Voltage Input Voltage 570mW 260'C , Lead Temperature (Soldering, 5 seconds) , Output Short Circuit to GND (Note 2) Continuous Electrical Characteristics (V + = 5 Voc, Note 4) Parameter O"Ct070"C -65' to + 150'C Storage Temperature Range -0.3 Voc to 36 Voc Power Dissipation (Note 1) Molded DIP , .sOmA Operating T~mperature RangE!, ± 36Voc Min' Conditions Typ Max Units Input Offset Voltage T A = 25'C (Note 9) ±? ±5 mVOC Input Bias Current IIN(+) or IIN(-) with the Output in the Linear Range, T A = 25'C, (Note'5) 2.5 25 nAOC ±5 nAoc V+ -'1.5 VOC Input Offset Current IIN(+)-IIN(-):TA=25'C Input Common- TA = ±0.5 25~C (Note 6) '0 Mode Voltage Range Supply Current RL = Infinite on all Comparators, T A = 25'C Voltage Gain RL =15 kO, V+=15Voc, TA=25'C Large Signal VIN = TTL Logic Swing, VREF = 1.4 VOC' Reponse Time VRL =5 Voc, RL =5.1 kO, TA=25'C Response Time VRL = 5 Voc, RL = 5.1 kO, T A = 25'C, (Note 7) Output Sink Current VIN(-)=1 Voc, VIN(+)=O, Vo=2Voc, 60 ., 100 /LAOC 500 V/mV 1.3 /LSec " 8 /LSec 20 30 'niAoc 0.20 0.70 . mAOC TA=25'C, (Note 11) VO=0.4Voc Output Leakage Current VIN(+)=1 VOC, VIN(-)=O, VO=5 Voc, TA=25'C 0.1 Input Offset Voltage (Note 9) I nput Offset Current IIN( + ) -IIN(-) Input Bias Current IIN( +) or IIN( -) with O'utput in Linear Range Input Common- Single Supply 0 Output Sink Current VIN(-)=1 Voc, VIN(+)=O, VO=2Voc 15 Output Leakage Current VIN(+)=1Voc, VIN(-)=O, VO=30Voc 1.0 /LAOC Differential Input Voltage All VIN's~O VOC (or V - on split supplies) (Note 8) 36 VOC -, nAoc ±9 mVoc ±1 ±15 nAOC 4 40 nAOC V+-2.0 Voc Mode Voltage Range mAoc Note 1: For operation at high temperatures, the LP339 must be derated basad on a 1?S'C maximum junction temperature and a thermal resistance of17S'C/W which applies for the device soldered in a printed cireuit board, operating In a stili air ambient. The low bias diSSipation and the "ON·OFF" characteristic of the outputs keeps the chip dissipation very small (Po'; 100 mW), provided the outputlTanslstors are allowed to ssturate. Note 2: Short clreuHs from the output to V + can cause excessive heating and eventual destruction. The maximum output current is approximately SO mAo , Note 3: This input current will only exist when the voltage at any of the input leads Is driven negative. It is due to the collector-base junction of the input PNP transistors becoming forward biased and thereby acting as input clamp diodes. In addition to this diode action, there Is also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltage of the comparators to go to the V + voltage level (or to ground for a large Input overdrive) for the time duration that an Input Is driven negative. This is not destructive and normal output states will re-establish when the input voltage, which is negative, again returns to a value greater than ... 0.3 Voc (TA= 2S'C). Note 4: These spectiications apply for V+ =SVoc and O'C,;TA,;70' C, unless otherwise stated. The temperature extremes are guaranteed but not 100% production tested. These pararnelers are not used to calculate outgOing AQL Note 5: The direction of the Input current Is out of the IC due to the PNP input stage. This current is essentially constant, independent of the state of the output, so no loading change exists on the reference or. the input lines as long as the common-mode range is not, exceeded. Note 6: The input common-mode voltage or either input voltage should not be allowed to go negative by more than 0.3V. The upper end of the common-mode voltage range Is V + -l.SV (TA = 2S'C), but either or both inputs can go to 30 Voe without damage. Note 7: The response time spe.cified is for a 100 mV Input step with S mV overdrive. For larger overdriVe signals 1.3!,s can be obtained. See Typical Performance ' ' Characteristics section. Note 8: Positive eXcursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode range, the comparator will provide a proper output state. The low input voltage state must not be less than - 0.3 Voc (or 0.3 Voc below the magnitude of the negative power supply, if used) at TA=2S'C. Note 9: At output switch paint, Vo=2Voe, Rs=On wHh V+ from S Voe; and over the lull input common-mode range (0 Voe to V+ -l.S Voel. Note 10: For Input signals that exceed V +, only the overdriven comparator is affected. With a SV supply, VIN should be limited to 2SV maximum, and a IimHing resistor should be used on all inputs that might exceed the positive supply. Note 11: The output sink current is a function of the output voltage. The LP339 has a bi-modal output section which allows Hto sink large currents via a Darlington connection at output voltages greater than approximately l.S Voe and sink lower currents below this point. (See typical characteristics section and applications section). 52-12 r-----------------------------------------------------------------------------~r 'V w Typical Performance Characteristics ~ IE 80 RL = "t--+-L+-+--+--t--I r-+-+;-,I--;:;!;:-t-+-+--l 60 ~~ Output Sink Current 1.0 II 5 I lA-O'C IS a: TA-25'C a: 3 u 1 r-- - 2": T 1 ~ ~ lA=2S'C 0.8 ~ !:i 0.6 ! TA 7O'C 0.2 0.0 0 10 20 3D V+ - SUPPLY VOLTAGE IVue) 40 5.0 Iii "'c I 3.0 100 mV l!:i 2.0 ~~ 1.0 20mV .... i» EE z- - '" -5D I ~-100 Ii o "-C-..L...J.-.L....L..J1_l-LI...J o 1' 4 ~1TA=25'C ,lA-70'C M ~~,~t~~~=!=~~=!=~~ "~""'-'--.L...JL.......L-L....L...-'--.L...J 0.2 0.4 0.6 0.8 OUTPUT VOLTAGE (Vue) 1.0 Response Times for Various Input Overdrives Positive Transition ..~ .. .'" I II I .... eE 5.0 4.0 HI--.I-+++-Ir-I-+......-I ~ltt-f---+-HH-++-I E ::> W 2O'!..V TA-25'C 20 I IJ ~ 'i i.lt-t--+-+-I_~~ ~~.I1I"" I:z ~- I I I I 5mVI "':i 3.0 -8 m - OVERDRiVE I 2! 2.D -tt-ft-+-HH4""f-l ~,.. 1.0 ~v~~J:I~~1- - 10 15 TlME(,..) OUTPUT VOLTAGE (Vuc) ~ 0.0 Response Times for Various Input Overdrives Negative Transition !:i;- 4.0 ~T~-#';~-+-H in 0.4 I I 0 Sumy VOLTAGE (Vuc) ~ ~ rTAI-O'C = r- .... E z ~ 20t--t--t--+-+-+-+-+~ VJN(CM) = 0 Vuc RINICM) = 10"11 4 ::> " - TA=70'C++-+--I 4D ~ Input Current 100 Supply Current z !:i :S ~ 10: 50 0 IH-I--I--+H-I-......,..'J-I,...,':"-=~ TA-25°C 5 10 15 TIME I,..) 20 TL/H/5226-10 Application Hints All pins of any unused comparators should be grounded. The bias network of the LP339 establishes a drain current which is independent of the magnitude of the power supply voltage over the range of from 2 Vee to 30 Vee. It is usually unnecessary to use a bypass capacitor across the power supply line. Notice that the output section is configured in a Darlington connection (ignoring 03). Therefore, if the output voltage is held high enough (Vo';;! 1 Vecl, 01 is not saturated and the output current is limited only by the product of the betas of 01, 02 and 11 (and the 60n RSAT of 02). The LP339 is thus capable of driving LED's, relays, etc. in this mode while maintaining an ultra-low power supply' current of typically 60 p.A: 'If transistor 03 were omitted, and the output voltage allowed to' drop below about O.B Vee, transistor 01 would saturate and the output current would drop to zero. The circuit would, therefore, be unable to 'pull' low current loads down to ground (or the negative supply, if used). Transistor 03 has been included to bypass transistor 01 under these conditions and apply the current 11 directly to the base of 02. The output sink current is now approximately 11 times the beta of 02 (700 p.A at Vo = 0.4 Vecl. The'output of the LP339 exhibits a bi-modal characteristic with a smooth transition between modes. (See Output Sink Current graphs in Typical Performance Characteristics section.) It is also important to note that in both cases the output is an uncommitted collector. Therefore, many collectors can be tied together to provide an output OFl'tng function. An output pull-up resistor can be connected to any available power supply voltage within the permitted power supply voltage range and there is no restriction on this voltage due to the magnitude of the voltage which is applied to the V + terminal of the LP339 package. The differential input voltage may be larger than V + without damaging the device. Protection should be provided to prevent the input voltages from going negative more than -0.3 Vee (at 25'C). An input clamp diode can be used as shown in the application section. The output section of the LP339 has two distinct modes of operation-a Darlington mode and a grounded emitter mode. This unique drive circuit permits the LP339 to sink 30 mA at Vo=2 Vee (Darlington mode) and 700 p.A at Vo=0.4 Vee (grounded emitter mode). Agure 1 is a simplified schematic diagram of the LP339 output section. -1~-----Vec ....--Vo STROBE INPUT Vo TlfHf5228-29 TLfHf5228-30 TUHf5228-29 S2·16 Typical Applications (Continued) (Single Supply) Transducer Amplifier Zero Crossing Detector (Single Power Supply) V· V· MAGNETIC PICKUP lOOk 30k 10k II lOOk 51k Vo Vo 20M 20M 10k 10k TlIH/5226-32 TUH/5226-31 Spllt·Supply Applications Zero Crossing Detector Comparator With a Negative Reference V· V· 51k Vo TUH/5226-34 TUH/5226-33 S2-17 • Section 3 Voltage Regulators Voltage Regulators Section Contents Dual Tracking LM2935 Low Dropout Dual Regulator ...........•................•...........•...·..•.........•....•..•....... S 3-13 3-Termlnal LM2930 3-Terminal Positive Regulator .....................•.......•.. ; .....................•....•.•.......... S 3-1 LM2931 Series Low Dropout Regulators ..•....•.•..•..•....•.•...•..........•................•....•..•..••.••. S 3-7 r-------------------------------------------------------------------------, r s::: ~National I\) CD (0) ~ Semiconductor o LM2930 3-Terminal Positive Regulator General Description Features The LM2930 3-terminal positive regulator features an ability to source 150 mA of output current with an .input-output differential of 0.6V or less. Efficient use of low input voltages obtained, for example, from an automotive battery during cold crank conditions, allows SV circuitry to be properly powered with supply voltages as low as S.6V. Familiar regulator features such aa current limit and thermal overload protection are also provided. Designed primarily for automotive applications, the LM2930 and all regulated circuitry are protected from reverse battery installations or 2 battery jumps. During line transients, such as a load dump (40V) when the input voltage to the regulator can momentarily exceed the specified maximum operating voltage, the regulator will automatically shut down to protect both internal circuits al"\d the load. The LM2930 cannot be harmed by temporary mirror-image insertion. Fixed outputs of 5V and SV are available in the plastic TO. 220 power package. • • • • • • • • Input-output differential less than 0.6V Output current in excess of ISO mA Reverse battery protection 40V load dump protection Internal short circuit current limit Internal thermal overload protection Mirror-image insertion protection 100% electrical burn-in in thermal limit Voltage Range LM2930T-S.0 LM2930T-S.0 sv SV • Schematic and Connection Diagrams (T0-220) Plastic Package FRONT VIEW TLlH/5539-1 Order Number LM2930T·5.0 or LM2930T·8.0 See NS Package T03B S 3·1 Absolute Maximum Ratings Input Voltage Operating Range Overvoltage Protection' Reverse Voltage (100 ms) Reverse Voltage (DC) Internal Power Dissipation (Note 1) Operating Temperature Range Maximum Junction Temperature Storage Temperature Range Lead Temp. (Soldering, 10 seconds) 26V 40V -12V -6V Internally Umlted - 40"C to + 85"C 125·C -65·C to + 150"C 230·C Electrical Characteristics (Note 2) LM293OT-5.0 (VIN=14V, 10=150 mAo TJ=25°C, C2=10 "F, unless otherwise specified) Parameter Conditions Output Voltage 6VS:VINS:26V, 5 rnAS:lo:S:15~ rnA, TJ=25°C Une Regulation 9VS:VIN16V, 10=5 rnA 6V:S:VIN:S:26V, 10=5 rnA Min Typ Max Unite 4.5 5 5.5 V 7 30 25 80 mV mV 50 Load Regulation 5 rnAS:loS: 150 rnA 14 Output Impedance lOOrnAoc& 10 mAnns, 100 Hz-10kHz 200 Quiescent CUrrent 10=10mA 10=150 rnA 4 18 Output Noise Voltage 10 Hz-loo kHz 140 p.Vrms 20 mVll000hr Long Term Stability Ripple Rejection fo=120Hz mV mn 7 40 56 rnA mA dB , 150 CurrentUmit Dropout Voltage 10=150 rnA Output Voltage Under -12VS:VINS:40V, RL = 1000 400 700 0.32 0.6 V 5.5 V -0.3 rnA Transient Conditions Electrical Characteristics (Note 2) LM2930T-8.0 (VIN=14V, 10=150 mAo TJ=25·C, C2=10 p.F, unless otherwise specified) Parameter Conditione Output Voltage 9.4V:S:VINS:26V, 5 rnA:S: loS: 150 mAo TJ=25°C Une Regulation 9.4V:S:VIN:S:16V, 10=5 mA 9.4VS:VIN26V, 10=5 rnA Min Typ Max Unite 7.2 8 8.8 V 12 50 50 100 mV mV 50 Load Regulation 5 rnA:S: loS: 150 rnA 25 Output Impedance loornAoc& 10mArms, 100Hz-10kHz 300 Quiescent CUrrant 10= 10 rnA 10=150 rnA 4 18 Output Noise Voltage 10Hz-100kHz , l-ong Term Stability Ripple Rejection . 150 Dropout Voltage 10= 150 rnA Output Voltage Under Transient Conditione -12VS:VIN:S:4OV, RL =1000 7 40 -0.3 rnA rnA 170 ,.Vrms 30 mVll000hr 52 fo=120Hz Current Limit mV mO dB 400 700 mA 0.32 0.6 V 8.8 V Note 1: Thennall8IIstance without a heatlllilk /Or junction to case temperature Is 4"C/W and for caaa to ambient temperature Is 5C1'CIW• .Note 2: AU characteriatica are measured with a capacHar across the Input 01 0.1 "F and a capacitor _ the ou1put of 10 "F. All characteriatica except nolle voltage and ripple rejection ratio are meaoured ullng puI.. techniques (tw:<: 10 IllS, duly cvcte:<:5%). Output voltage changaa due to changeS In InIemaI temperature _ be taken Into account eeparately. S3-2 ,-----------------------------------------------------------------------------, r 3: I\) Typical Performance Characteristics CD Co) o 0.6 ~ ..... "...>=z .........a: Q ... Dropout Voltage ~ ..... 0.5 -- 0.4 O.l I- :::0. I- 0.2 ~ :::0 0.1 :::0 ...!!!i 0.6 o ~ 10= 150mA r-10 = ">=z ... ......a: ...Q ... - 5~mA 'O=IOmA I O.l I- 0.2 ...'"~!!!i 0.1 o 100 50 0.4 V :::0 ,..-- o Tj = 25°C 0.5 I- :::0 ~ Dropout Voltage 150 V ./ V o ." co > ... :::0 High Voltage Behavior lM29lo·5 '0=15OmA 5.0 '/ 4.0 1/ / C> 4 I- l '"co 2 '" 1= / 2.0 6 > :::0 co ~ ... ::'"..... / l.O I- 't' I 1.0 2.0 lM29l0·5 Rl = lOon 7 ..... I- 200 B ... I- 150 OUTPUT CURRENT (mA) Low Voltage Behavior ~ 100 50 JUNCTION TEMPERATURE (OC) 6.0 ./ o l.o 4.0 5.0 6.0 I I I o 10 Line Transient Response Tj= 25°C '0= 150mA ""' f-f- ,.. 1\ I If 1\ J 1\1 lO 40 Load Transient Response V,N -VOUT= 9V C2 = 10 jlF V,N- VOUT=9V C2 = 10 F r- 20 INPUT VOLTAGE (V) INPUT VOLTAGE (V) ~ " " ..... " <" .! IZ ... a: a: u 15 lO '" " co co ..... 45 150. 0 o 15 lO 45 TIME !!ts) TIME !!ts) TLlH/5539-2 53·3 Typical Performance Characteristics (Continued) Peak Output Current &00 C ..5 ... I- z .. II: II: u - ~ 300 ~ ~ I ..5 .-'" ~SOC 200 25 . 20 I- 15 II: II: ...u ...'" :; z ". o 10 15 20 25 l,...oo 10 " o r Tj = 25°C u 100 o 30 I- ...z Tj = I""" Quleacent Current VIN"4V C , I- .... 5co ....- ~~. '-4D"c 500 400 35 30 '" ~I"'" "" o 30 INPUT VOLTAGE (VI 22 ....... 1"'" .", 60 90 120 150 OUTPUT CURRENT (mAl Quiescent Current Quiescent Current 70 LM2B30-5 C ..5 l- ....z . 20 10 -ISomA C &0 Ii:... &0 ..5 I. . 40 u u l- I- 30 II: II: II: II: 18 ...z I '" :; 6 ...z '":;... 10 = SOmA u ... " 3 " 10=0 o 40 80 120 JUNCTION TEMPERATURE ("CI 80 iii 60 o 1~.lomA 10.50 rnA 10 20 30 INPUT VOLTAGE (VI 80 Ripple Rejection 10"SOmA VIN-VOUT"BV ~ iii 3 zco ......... co j: u ~ 48 " II: iii: 10 -IS0mA r' 10 160 Ripple Rejection z ......... .......... .... 20 o 0 :s ~ u 60 j: u L ...iil ...... .... 40 II: II. ii! 20 20 VIN-VOUT"BV fO = 120 Hz o o 1 10 100 1k 10k lOOk ·IM o 50 100 150 OUTPUT CURRENT (mAl FREQUENCY (Hzl TUH/5539-3 S3-4 Typical Performance Characteristics (Continued) Output Impedance 10 50 T,"25°C C .! ...i5 20 II: II: .t 15 Tl" 25°C RL "loon TI"ZSoc 25 I"~ "". ~ fl V 0.1 Ravarsa Supply Current Overvoltage Supply Current 30 10 "!,.mA 10 ./ '"'" i 8'" '" -1l1li B .. ~ -150 iii 1 10 100 lk 10k lOOk ~ /" V -2l1li o 0.01 ,/' /' -250 20 1M FREQUENCY (H.I -IZ -18 25 30 INPUTVOLTAGE (VI ... ... -4 -I IIII'IITVOLTAI' (VI Output Voltage (Normalized Output at Reverse Supply 0.1 1.l1li5 D.Z RL _00 T," 25°C Rl-T,"zrc i/ V -11.1 E . 0.15 S 0.1 ~ 0.05 ~ Q -10 -I -t -4 -Z ... ~'.- ,.. ..... ~ Q >t.lH 30 ~ 1°.115 !-Vtfj"'.V .. 0.... -4t-1I 31 INPUTVOLTAGE (VI INPUT VOLTAGE (VI \. ~ ....... - -- o -11.3 ~ w > f-o .... -D.Z -12 to 1V at TJ = 25"C) Output at Overvoltag8 0 20 40 111 10 110 111 140 JUNCnON TEMPERATURE rei TUH/55311-4 Typical Application VIN UNREGULATED INPUT Cl* + O·'T -- T 'Required If regulator I. located far from power supply filler. "C2 may be either an Alumlnum or Tantalum type capacilor bul must be rated to operate at -40'C to guarantee regulator stability 10 that temperature extreme. 10 I'F Is the minimum value required for stability and may be increased without bound. Locata as closa as possible to the regulation. 53-5 VOUT REGULATED OUTPUT C2** 'O F Il TUH/5539-5 o en N :E. r-----------------------------------------------------~------------~ C'), ... Definition of Terms Dropout Voltage: The input-output voltage differential at which the circuit ceases to regulate against further reduction in input voltage. Measured.when the output voltage has dropped 100 mV from the nominal value obtained at 14V input, dropout voltage is dependent upon load current 'and junction 'temperature. , Input Voltage: T!1e DC voltage applied to the input terminals with respect to ground. Long Term Stability: Output voltage stability under accelerated life-test conditions after 1000 hours with maximum rated voltage and junction temperature. Output Noise Voltage: The rms AC voltage at the output, with Constant load and no input ripple, measured over a specified frequency range. Quiescent Current: That part of the positive input current that does not contribute to the positive load current. The regulator ground lead current. Input-Outpu, Differential: The voltage differenCe between the unregulated input voltage and the regulated output voltage for which the regulator will operate. Ripple ReJection: The ratio of the peak-to-peak input ripple voltage to the peak-to-peak output ripple voltage. Temperature Stability of Vo: The percentage, change in output voltage for a thermal variation from room temperature to either temperature extreme. Une Regulation: The change in output voltage for a change in the input voltage. The measurement is made un; der conditions of low diSSipation or by using I!ulse techniques such that the average chip temperature is not significantly affected. Load Regu!atlon: The change in output voltage for a change in load current at constant chip temperature. Maximum Average Power Dissipation ' 18 ! co ~ g 14 12 r-- INFINITE ~ O'-HEATSINK SOC/W 10 r-IO"tiI!.~HEATSINK Io;; HEAT SINK ~ rr- ~ or: I r- t- NO HEAT SINK ~ o 0102030405080701010 AMBIENT TEMPERATURE rei 53-6 TUH/5539-6 I... ~National ~ Semiconductor LM2931 Series Low Dropout Reg~lators General Description Features The LM2931 positive voltage regulator features a very low quiescent current of 1 rnA or less when supplying 10 mA loads. This unique characteristic and the extremely low input-output differential required for proper regulation (0.2V for output currents of 10 mA) make the LM2931 the ideal regulator for standby power systems. Applications Include memory standby circuits, CMOS and other low power processor power supplies as well as systems demanding as much as 150 rnA of output current. Designed primarily for automotive applications, the LM2931 and all regulated circuitry are protected from reverse battery Installations or 2 battery jumps. Ouring line transients, such as a load dump (60V) when the Input voltage to the regulator can momentarily exceed the specified maximum operating voltage, the regulator will automatically shut down to protect both intemal circuits and the load. The LM2931 cannot be harmed by temporary mirror-image Insertion. Familiar regulator features such as short circuit and thermal overload protection are also provided. Fixed output of 5V is available in the plastic TO-220 power .package or the popular T0-92 package. An adjustable output version, with on/off switch, is available In a 5-lead TO220 package. • • • • • • • • • • • Very low quiescent current Output current in excess of 150 mA Input-output differential less than 0.6V Reverse battery protection 60V load dump protection - 50V reverse transient protection Short circuit protection Internal thermal overload protection Mirror-image Insertion protection Available in plastic T0-220 or TO-92 Available as adjustable with TTL compatible switch Output Voltage Options LM2931T-5.0 5V LM2931AT-5.0 LM2931AT-5.0 5V LM2931 AZ-S.O LM2931CT Adjustable (Contact factory for other fixed output options.) SV 5V Schematic and Connection Diagrams YIN~""----- ______""'______", TO-220a-L.... 'RDlTVllW Order Number LM2I31 See NS Package TOIB, Z03A. T05A .lmB"""" To-t2 I YaUT lID RI IV: 210 1111:- I • -- R'I R.2 III •• T0-22O 5-Lead lIZ IV: .... AIII:- RII· .u. aN. ~II I ~?~ P_V• • TLlHt5254-1 S3-7 Absolute Maximum Ratings Input Voltage Internal Power Dissipation' (Note.1 Operating,Temperature Range' . 26V Operating Range Overvoltage Protection lM2931A, lM2931CTAdjustabie lM2931 r.. " . I:"~erna"y Limited '. -40°0 to + 85°C Maximum Junction Temperature 125°C -65~C to . Storag~ Tempe.rature R,ange lead Temp. (Soldering, 10 seconds) 60V 50V 230"C Electrical Characteristics for 5V(.VIN= 14V, 10= 10 mA, Tj=25°C unle~sotherwise ~pe~ified) Parameter :.. LM2931A.5.0 . . Condl,lons Output Voltage 6.0V:S:VINS;26V,.lo:S:150 rnA, !j=25°C line Regulation 9V:S:VIN:S:16V 6V:S:VIN:S:26V .' , Typ Max Min Typ' 4.75 5' 5.25 4.5 5 2 4 .' 5 mA:s:lo:s:'150 mA 14' Output Impedance 100 mAoc and 10 mArms, 100 Hz-10 kHz' 200 Quiescent Current 10:S: 10 mA,.6V:S: VIN:S: 26V, Tj=25°C 10=150 rnA, VIN=14V, Tj=25°C 0.4 load Regulation - Output Noise Voltage ' '. 50·' fo=120Hz 80 Dropout Voltage 10=10mA lo=150mA 0;05 0.3 . . Units ....1.0 ::30.' 14 50 mV mV mV .mO .1 . mA .. 15 .. .. 20 Ripple Rejection .' .. .V 2. 4' 0.4':: 1 15 Maximum Operational Input Voltage '. :5:5 200 :500 long Term Stability - 10 ·.30 ,',' Ma~ :'. .. 10 Hz-100 kHz .. LM293.1-5.0 . " Niln + 150"C p.Vrms 20 80 0.2 0.6 mA 500' . 0.05 0.3 inV/1000 hr .. -dB 0.2 0.6 'V V 26 33' 26 33 . V 60 70 50 70 V Maximum line Transient 'RL =5000, Vo:S:5.5V, 100 ms Reverse Polarity Input Voltage, DC Vo;;:-0.3V -15 -30 -15 -30 V RevElrsePolarity Input Voltage, Transient 1% Duty Cycle, T:S: 100 ms -50 -80 -50 -80 V ., , . .- , S3-8 " Electrical Characteristics for Adjustable (VIN:2:VOUT+0.6V, 10= 10 mA, T·=25°C unless otherwise specified) Parameter Reference Voltage LM2931CT Conditions 10,;;100 mA, Tj=25°C, R1 =27k Measured from VOUT to AdjusfPin, Vo = 3V Units Min Typ Max 1.08 1.20 1.32 V Output Voltage Range R1 =27k 23 V Line Regulation VOUT+0.6V,;;VIN,;;26V 0.2 1.5 mVIV 1 3 Load Regulation 5 mA,;;10';;100 mA 0.3 Output Impedance 100 mADe and 10 mArms, 100 Hz-10kHz 40 Quiescent Current 10=10mA, Tj=25°C 10=150mA During Shutdown RL = 5000 0.4 15 0.8 Output Noise Voltage 10 Hz-100 kHz 100 p.VrmslV 0.4 %/1000 hr Long Term Stability Ripple Rejection fo= 120 Hz 0.002 Dropout Voltage 10=10mA 10=100mA 0.05 0.3 Maximum Operational Input Voltage % mOIV 1 1 mA mA mA 'lIo1V 0.2 0.6 V V 26 33 V 60 70 .V Maximum Line Transient 10 = 10 mA, Reference Voltage,;; 1.5V Reverse Polarity Input Voltage, DC VO:2:-0.3V -15 -30 V Reverse Polarity Input Voltage, Transient 1% Duty Cycle, T';; 100 ms -50 -80 V OnlOff Threshold Voltage Tj=25°C, VO=3V 2.0 2.2 1.2 3.25 V V 20 50 /LA On Off OnlOff Threshold CUrrent 53-9 ~ r-----------------------------------------------------------------------------~----------------- CO) ~ :; Typical Performance Characteristics Dropout Voltage Dropout Voltage 0.1 ~ S ~ 0.5 5 . 0.3 V 0.2 = ~ I -- ~ 0.1 o 'ai ..e,. ~ I 50 ~ 100 0.1 -2 -20 -10 0 10 20 15 '..." B ~' .,. .. == 200 - I-::: ' - - i-- Ij ""25°C 1-- Tj' -40'C 'i i-'" C 25 coS 25 Ir! ......,.a: 20 ~ 15 10 ~ co -5 Quiescent Current 25 iii 20 ....'" ~ ... 1& i3 :; IB iii _. t-- - C .! ... I- ai o 10 20 3D ~ r- -- 1~-JmA 10-10 rnA - -20 -10 0 10.20 30 40 50 60 INPUT VOLTAGE (V) '-'-- 60 90 120 OUTPUT CURRENT (mAl 15 10 iz ..ti l!I. ..~ 15 10 15 -40 ISO v \J _~M2931-5.1 lo·'OmA I I 10 .. ti .l!I ii 3 i 15 10 65 10 &5 fO"201tz 50 I 45 100 Ik 10k FREQUENCY (H.) 120 15 ~ 45 10 10 Ripple Rejection jt-- 55 40 JUNCTION TEMPERATURE ('C) I C2' 100 oFTANT _ I" C2·'00.FALUM, ~ "'\, 1 10 60 r- 10tolA -- r-- ,o~02A Ripple ReJecOon I I I I I I - -- 1~=l~m~- I- ,- I I o 30 Quiescent Current I I 1& 5 co i---~ ~,.... 10"50mA 10 I I/i-" co IL 20 B / INPUT VOLTAGE IV) 30 TIME Co~ Quiescent Current 100 35 1630·4& VIN =14V 300 o 45 3D 3D 400 6.D Load Transient Response TIME Cod Peak Output Current TI" BS'C 5.0 ~ 600 500 4.0 y INPUT VOLTAGE IVI C 3.0 INPUT VOLTAGE IVI If 40 50 60. 30 I Z.II X!N - VOUT' IV 'l00oF -- r- - U Line Transient Response I L / V 1 3.0 150 100 ,. OUTPUT CURRENT CmAl RL • soon II ~ 50 LM2831·5.0 I V' 4.D 1.D 150 f- > '. .,/ Output at Voltage Extremes 10 ~ v ...-..- JUNCTION TEMPERATURE C'CI .12 5.0 ~ c == 0.2 ...i!! .. ..... .. 0.4 c; 0.3 10"lomA ~ o lMZIll-i.D '0' ISO ..A ~ I 10'~mA ,...- 6.0 ~ ;l 0.5 10 =}somA i-- 0.4 ~ c; ,. ,. == Low Voltage Behavior 0.1 IDOl 'IM o 50 100 110 200 OUTPUT CURRENT (mAl TLlH/5254-2 83-10 Typical Performance Characteristics (Continued) Operation During Load Dump Output Impedance 10 lMZ9.iI-6.D 10'llmA g .. " w u z li: ....!! I; 70 50 so 40 3D Reference Voltage 1.30 ·!.I50 lm. ZO ~ I:::: Co "100.F Hl " soon ~ 1.14 1.12 1.10 '" D.Ol 10 100 lk 10k lOOk 1M 100 E I i: , ~ 3.0 ~ 2.8 ~ 2.6 10'" ~ 2.4 i!i ZD 4.0 LM2931 CT ADJUSTABLE 3.8 I 3.6 3.2 2.2 2.0 18 g I O~F i!i I. I O~ i I I o 6 9 12 .15 lB 21 OUTPUT VOLTAGE (V) 300 400 SOO Maximum Power Dissipation (T0·220) On/Off Threshold 3.4 zoo o ,"-- 0.1 12 i!i iili 0.1 D.S D.S a 24 ~JFiNfTE I g ..... ..... ..a 10" CIW HEATSINK i I~I NO HEATSINK 1" - ..... ... ..... """ ...... 24 Maximum Power Dissipation (To-92) I.D D.! 1& ' - - HEATSINK 14 10 """ 6 9 12 15 18' 21 OUTPUT VOLTAGE (V) TIME(ms) FREOUENCY (Hz) 9 ..... : 1.20 D 1 1.24 ~ 1.22 10 ./ 0.1 lM2931CT ADJUSTABLE 1.28 E 1.26 D.' D.3 J L I I ~~ ~ D.l~5·· iEAJ lE~GT~ I"- ~M PC BOAHD LEN:T~' ~::~ ~ - I I J I I I ~ U q G D W I pr BOtR~ D.l AMBIENT TEMPERATURE rCI j_ "'~I 0.2 10 ZO 30 40 50 &0 10 10 90 I I ~ 50 90 ro " 90 AMBIENT TEMPERATURE rCI TUH/5254-3 Typical Applications LM2931 Adjustable VCC R3 Slk V,N UNREGULATED "-::::::r.-" _fr D.1T IN OUT VOUT OFF INPUTC1• ....l_ ON/OFF Cl' O.I.F ;f' lM2!31 ADJUSTABLE Rl 21k ~ ON GND + :;:: .... 100 .F ~C2" Y..z ) ... VOUT= Relerence Voltage x RHR2 A I Note: Using 28k lor Rl will automatically compensate lor errors in VOUT due to the input bias current 01 the ADJ pin (approximately 1 ).LA). 53-11 TLIHI5254-4 'Required il regulator is (ocated lar from power supply filter. "C2 may be either an Aluminum or Tantalum type capacitor but must be raled to operate at - 40'C to guaranlee regulalor stebility to that temperature eldreme. 100).LF is the minimum value required lor stebllity and may be Increased wilhout bound. Locate as close as possible to the regulator. ~ ~ N :I r------------------------------------------------------------------------------------------Application Hints One of the distinguishing factors of the LM2931 series regulators is the necessity of the output capacitor required for device stability. The value required varies greatly depending upon the application circuit and other factors. Thus some comments on the characteristics ~ both capacitors and the regulator are in order. High frequency characteristics of electrolytic capacitors depend greatly on the type and even the manufacturer. As a result, a value of capacitance that works well with the LM2931 for one brand or type may not necessary be sufficient with an electrolytic of different origin. Sometimes actual bench testing, as described later, will be the only means to determine the proper capacitor and value. Experience has shown that, as a rule of thumb, the more expensive and higher quality electrolytics generally require a smaller value for regulator stability. As an example, while a quality 100 ,.,.F aluminum electrolytic covers all general application circuits, similar stability can be obtained with a tantalum electrolytic of only 47 ,.,.F. This factor of two can generally be applied to any special application circuits also. At this pOint, the procedure for bench testing the minimum value of an output capacitor .in a special application circuit should be clear. Since worst-case occurs at minimum operating temperatures and maximum operating currents, the , entire circuit, including the electrolytiC, should be cooled to the minimum temperature. The input voltage to the regulator should be maintained at 0.6V above the output to keep internal power dissipation and die heating to a minimum. Worst-case occurs just after input power is applied and before the die has had a chance to heat up. Once. the minimum value of capacitance has been found for the brand and type of electrolytic in question, the value should be doubled for actual use to account for production variations both in the capacitor and the regulator. (All the values in this section and the remainder of the data sheet were determined in this fashion.) Definition of Terms Dropout Voltage: The input-output voltage differential at which the circuit ceases to regulate against further reduc~ tion in input voltage. Measured when the output voltage has dropped 100 mV from the nominal value obtained at 14V input, dropout voltage is dependent upon load current and junction temperature. Another critical characteristic of electrolytics is their performance over temperature. While the LM2931 is designed to operate to - 40"C, the same is not always true with all electrolytics (hot is generally not a problem). The electrolyte in many aluminum types will freeze around -30"C, reducing their effective value to zero. Since the capacitance' is needed for regulator stability, the natural result is oscillation (and lots of it) at the regulator output. For all application circuits where cold operation is necessary, the output capaCitor must be rated to operate at the minimum temperature. By' coincidence, worst-case stability for the LM2931 also occurs at minimum temperatures. As a reSUlt, in applications where the regulator junction temperature will never be less than 2SoC, the output capacitor can be reduced approximately by a factor of two over the value needed for the entire temperature range. To continue our example with the tantalum electrolytic, a value of only 22 ,.,.F would probably thus suffice. For quality aluminum, 47 ,.,.F would be adequate in such an application. Input Voltage: The DC voltage applied to the input terminals with respect to ground. Input-output Differential: The voltage difference between the unregulated input voltage and the regulated output voltage for which the regulator will operate. LIne Regulation: The change in output voltage for a change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. Load Regulation: The change in output voltage for a change in load current at constant chip temperature. Long Term Stability: Output voltage stability under accelerated life-test conditions after 1000 hours with maximum rated voltage and junction temperature. Another regulator characteristic that is noteworthy is that stability decreases with higher output currents. This sensible fact has important connotations. In many applications, the LM2931 is operated at only a few milliamps of output current or less. In such a circuit, the output capaCitor can be further reduced in value. As a rough estimation, a circuit that is required to deliver a maximum of 10 mA of output current from the regulator would need an output capacitor of only half the value compared to the same regulator required to deliver the full output current of 1S0 mAo If the example of the tantalum capaCitor in the circuit rated at 2SoC junction temperature and above were continued to include a maximum of 10 mA of output current, then the 22 ,.,.F output capacitor could be reduced to only 10 ,.,.F. Output Noise Voltage: The rms AC voltage at the output, with constant load and no input ripple, measured over a specified frequency range. Quiescent Current: That part of the positive input current that does not contribute to the positive load current. The regulator ground lead current. Ripple ReJection: The ratio of the peak-to-peak input ripple voltage to the peak-to-peak output ripple voltage. Temperature Stability of Vo: The percentage change in output voltage for a thermal variation from room temperature to either temperature extreme. In the case of the LM2931CT adjustable regulator, the minimum value of output capacitance is a function of the output voltage. As a general rule, the value decreases with higher output voltages, since internal loop gain is reduced. S3-12 ,-------------------------------------------------------------------------, ~National ~ Semiconductor CI1 LM2935 Low Dropout Dual Regulator General Description The LM2935 positive voltage regulator features a low quiescent current of 3 rnA or less when supplying lOrnA loads from the standby regulator output. This unique characteristic and the extremely low input-output differential required for proper regulation (0.55V for output currents of lOrnA) make the LM2935 the ideal regulator for power systems that include standby memory. Applications include processor power supplies demanding as much as 750 rnA of output current. Designed primarily for automotive applications, the LM2935 and all regulated circuitry are protected from reverse battery installations or 2 battery jumps. During line transients, such as a load dump (SOV) when the input voltage to the regulator can momentarily exceed the specified maximum operating voltage, the 0.75A regulator will automatically shut down to protect both internal circuits and the load while the standby regulator will continue to power any standby load. The LM2935 cannot be harmed by temporary mirror-image insertion. Familiar regulator features such as short circuit and thermal overload protection are also provided. Fixed outputs of 5V are available in the plastic TO-220 power package. Features • • • • • • • • • • • • • Two regulated outputs Output current in excess of 750 mA Low quiescent current standby regulator Input-output. differential less than O.SV at 0.5A Reverse battery protection SOV load dump protection - 50V reverse transient protection Short circuit protection Intemal thermal overload protection Available in plastic TO-220 ON/OFF switch for high current output Reset error flag 100% electrical burn-in Typical Application Circuit 'Required if regulator is located far from power supply filter. 1 ~Cl' SI~' ON/OFF- *. "'"'01 F ~ "Required for stability. May be increased without bound. Capacitor must be rated to operate at the minimum temperature expected for the regulator system. INPUT OUTPUT 2 Vour 5V VOLTAGE VOLTAGE ~ C2' ~50 mA RI RESET 20k 4 SWITCH/ FLAG o---4----.:.tRESET (FOR Vour ONLY) . ~IO~F LM2935 5 GND 13 STANDBY 5V +T OUTPUT 10 mA ::::;:::: C3" t-.1.----_.....I - 10.F ~ FIGURE 1. Test and Application CIrcuit Connection Diagram TO·220 5·Lead Order Number LM2935T &./ I ~ 3: ~ Co) ~ 5 STANDBY OUTPUT 4 SWITCH/RESET 3 GROUND See NS Package Number T05A 2 OUTPUT VOLTAGE (Vour) 1 INPUT VOLTAGE (V'N) FRONT VIEW TL/H/5232-1 S3-13 Absolute Maximum Ratings Input Voltage Operating Range Overvoltage Protection Internal Power Dissipation (Note 1) Operating Temperature Range Maximum Junction Temperature Storage Temperature Range Lead Temp. (Soldering, 10 seconds) 26V 60V Internally Limited Electrical Characteristics FOR VOUT (VIN = Parameter Output Voltage + 125·C -65·Cto + 150·C 150·C 230·C 14V, 10 = 500 mA, Tj = 25·C unless otherwise specified) Conditions 6V~VIN~26V,lp~500 -40"Cto mA, Min Typ Max Units 4.75 5.00 5.25 V 4 10 25 50 mV mV 50 Tj=25·C Line Regulation 9V~VIN~16V,lo=5 6V~VIN~26V,lo=5 mA mA Load Regulation 5 mA~lo~500 mA 10 Output Impedance 500 mAoc and 10 mArms, 100 Hz-10kHz 200 mO Output Impedance 500 mAoc and 10 mArms, 100 Hz-10kHz 200 mO Quiescent Current 10 ~ 10 mA, No Load on Standby 10 = 500 mA, No Load on Standby -10 = 750 mA, No Load on Standby 3 55 120 10 Hz-100 kHz 100 ,..Vrms 20 mVl1000 hr Ripple Rejection fo=120Hz 66 Dropout Voltage 10=500mA 10=750mA 0.45 0.82 Output Noise Voltage Long Term Stability Current Limit M!Il, .L ~ 1.5 L I 1.0 Pl::> co 0.5 i"""'"" I • o 051015202530 INPUT VOLTAGE tV} o o 10 20 30 40 50 INPUT VOLTAGE (V) 60 TLIHI5232-3 83·16 Typical Performance Characteristics (Continued) Quiescent Current (VOUT) 120 110 .. 100 §. 90 i 80 ... 50 fa 40 30 ~ ~ S10PEN VOUT OFF I· " ," 20 10 o ~ I""" " SI OPEN YoUT OFF o o 10 -40· >-IS~Y=10~_ f-- 0 40 BO 120 ~ a: 70 I- 60 ~ ~ Il- 40 loUT -750 rnA'= e ~ 120 ~ 10 100 B 80 ~ ; 6 !z co .f; 60 ij a: i a: l'"'- t-- E z 80 ... !z 70 § 60 co 40 i Ripple Rejection (VSTBY) 150 300 450 600 OUTPUT CURRENT (rnA) 0 18 16 14 z co . 12 ~ 10k V o 20 ~ 1/ o 40 750 I-R\ =2~k RL=1011 5 0.01 50 30 to; :3 a: 100 lk FREQUENCY (Hz) -20 -10 0 10 20 30 40 50 60 INPUT VOLTAGE (V) 50 co 10 o 10=120 Hz S' 0.1 ~ ~ ,. i!!! 160 IjBYiojA- t- 1 a Reset on Startup l!! ~. co 120 Isr=11Ojl Ripple Rejection (VOUT) 0 §: 80 I 1 30 ~ 40 ~ ill a: 10k Output Impedance. H 10~T =150 inA t-t- S10PEN VOUT OFF 10 =120 Hz 70 ~ 9 Quiescent Current (VSTBY) -20 -10 0 10 20 30 40 50 60 10 = co t-t- 10 JUNCTION TEMPERATURE 1°C) 10UTOmA FREQUENCY (Hz) ... ...i lOUT =250 rnA 20 10UT500 rnA 60 40 20 BO I-'lk 40 30 -40 INPUT VOLJAGE (V) YoUT louT =500 rnA ...£2=10.F ,..... 30 50 o 25 ~ ' - _ lOUT = 500 rnA 60 100 160 VSTBY""'" . ISTBy=10 rnA C3=10 .F I- 70 IsTBY -10 rnA .. 140 Ripple Rejection 50 20 Quiescent Current . JUNCTION TEMr;eRATURE (OC) a: 15 o o i ~:3 160 ISTBY -0 rnA 80 .. § I ISTBy=10 rnA STAND8Y OUTPUT CURRENT (rnA) Quiescent Current (VSTBY) ,.....- ffi :s CI VOUT-OUTPUT CURRENT (rnA) 4 1 / V ~ o 100 200 300 400 500 600 700 800 !z / II a ~~ uescentCurrent(V'0 II 5 Quiescent Current (VSTBY) ISTBy=10rnA L iliS ~ a: ~ 10 8 . 6 2 10 15 20 OUTPUT CURRENT IrnA) 25 Maximum Power Dissipation (TO-220) t- r-t-t- r-t-- INIFINAE HEAT SINK r- t- r- I I I I f- I\" ~r-o ~ HiT jINK,_ ~ NO HEAT SINK i""'" o 234567B INPUT VOLTAGE (V) o 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE (OC) TL/H/5232-4 53-17 Circuit Schematic -, I I 'n./H/5232-5 S3-18 ------------------------------------------------------------------------------'r s::: Definition of Terms N Dropout Voltage: The input-output voltage differential at which the circuit ceases to regulate against further reduction in input voltage. Measured when the output voltage has dropped 100 mV from the nominal value obtained at 14V input, dropout voltage is dependent upon load current and junction temperature. Input Voltage: The DC voltage applied to the input terminals with respect to ground. STANDBY OUTPUT The LM2935 differs from most fixed voltage regulators in that it is equipped with two regulator outputs instead of one. The additional output is intended for use in systems requiring standby memory circuits. While the high current regulator output can be controlled with the ON/OFF pin described below, the standby output remains on under all conditions as long as sufficient input voltage is applied to the IC. Thus, memory and other circuits powered by this output remain unaffected by positive line transients, thermal shutdown, etc. The standby regulator circuit is designed so that the quiescent current to the IC is very low « 3 mAl when the other regulator output is off. In applications where the standby output is not needed, it may be disabled by connecting a resistor from the standby output to the supply voltage. This eliminates the need for a more expensive capaCitor on the output to prevent unwanted oscillations. The value of the resistor depends upon the minimum input voltage expected for a given system. Since the standby output is shunted with an internal 5.7V zener (Figure 3), the current through the external rel!istor should be sufficient to bias R2 and R3 up to this point. Approximately 60 ,...A will suffice, resulting in a 10k external resistor for most applications (FIgure 4). Input-output Differential: The voltage difference between the unregulated input voltage and the regulated output voltage for which the regulator will operate. Line Regulation: The change in output voltage for a change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. Load Regulation: The change in output voltage for a change in load current at constant chip temperature. Long Term Stability: Output voltage stability under accelerated life-test conditions after 1000 hours with maximum rated voltage and junction temperature. Output NOise Voltage: The rms AC voltage at the output, with constant load and no input ripple, measured over a specified frequency range. Quiescent Current: The part of the positive input current that does not contribute to the positive load current. The regulator ground lead current. Ripple ReJection: The ratio of the peak-to-peak input ripple voltage to the peak-to-peak output ripple voltage. RD 10k Temperature Stability of VO: The percentage change in output voltage for a thermal variation from room temperature to either temperature extreme. r-~~~~~Y LM2935 Application Hints I ..L:.C3 l' EXTERNAL CAPACITORS I The, LM2935 output capacitors are required for stability. Without them, the regulator outputs will oscillate, sometimes by many volts. Though the 1O,...F shown are the minimum recommended values, actual size and type may vary depending upon the application load and temperature range. CapaCitor effective series resistance (ESR) also factors in the IC stability. Since ESR varies from one brand to the next, some bench work may be required to determine the minimum capacitor value to use in production. Worst-case is usually determined at the minimum ambient temperature and maximum load expected. * TL/H/5232-6 FIGURE 4. Disabling Standby Output to Eliminate C3 Output capacitors can be increased in size to any desired value above the minimum. One possible purpose of this would be to maintain the output voltage during brief conditions of negative input transients that might be characteristic of a particular system. HIGH CURRENT OUTPUT Unlike the standby regulated output, which must remain on whenever pOSSible, the high current regulated output is fault protected against overvoltage and also incorporates thermal shutdown. If the input voltage rises above approximately 30V (e.g., load dump), this output will automatically shutdown. This protects the internal circuitry and enables the IC to survive higher voltage transients than would otherwise be expected. Thermal shutdown is effective against die overheating since the high current output is the dominant source of power dissipation in the IC. CapaCitors must also be rated at all ambient temperatures expected in the system. Many aluminum type electrolytics will freeze at temperatures less than - 30·C, reducing their effective capaCitance to zero. To maintain regulator stability down to - 40·C, capaCitors rated at that temperature (such as tantalums) must be used. No capaCitor must be attached to the ON/OFF and ERROR FLAG pin. Due to the internal circuits of the IC, oscillation on this pin could result. ON/OFF AND ERROR FLAG PIN This pin has the ability to serve a dual purpose if desired. When controlled in the manner shown in Figure 1 (common in automotive systems where 51 is the ignition switch), the pin also serves as an output flag that is active low whenever a fault condition is detected with the high current regulated output. In other words, under normal operating conditions, the output voltage of this pin is high (5V). This is set by an internal clamp. If the high current 53-19 CQ Co) U'I I :J Application Hints (Continued) output becomes IItY8guIated for any reaaon (line transients, IIhort ciJaIIt. thermal shutdown, low Input voltage, etc.) the pin switches to the active low state, and is e&pl!bIe of sinking several milliamps. This output signal can be uSed to Initiate any reset or start-up procedure that may be required of the ayat8m. The ON/OFF pin can also be driven directly from logic circuits. The only requirement is that the 20k pull-up resistor remain in place (FIf/IU9 5). This will not affect the logic gate since the voltage on this pin is Umited by the internal clamp in the LM2935 to 5'1/. The error flag is sacrificed in this arrangement since the maximum sink capability of the pin in the active low state (approximately 5 mA) i& usually not sufficient to pull down the active high logic gate. Of course, the flag can be retained if the driving gate is open collector logic. ., :. CMOS MM74C04 OR EQUiVAlENT l1li LMIm 4 SWlTCHI R£SfT IlllAYED R£8n IWITCIII IIUEt OUT Tl/H/5232-7 FIGURE 6. Controlllnt ON/OFF Terminal wHh a Typical CMOS or TTL LogIc Gllte 53-20 FIGt,lRE 6. Rent Pulse on Powe....Up (with approximately 300 rna delay) Section 4 Voltage References Voltage References Section Contents Adjustable References LM185/LM285/LM385 Adjustable Micropower Voltage Reference ...............................................• 8 4-8 Fixed References LM168/LM268/LM368 Precision Voltage Reference .....•......•............................................... 84-1 LM185-1.2/LM285-1.2/LM385-1.2 MicropowerVoltage Reference Diode ........................................ 8 4-15 LM185-2.5/LM285-2.5/LM385-2.5 Micropower Voltage Reference Diode ...................................•.... 84-21 LM199AH-20. LM299AH-20. LM399AH-50 Ultra 8table Reference ............................................... 8 4-26 r---------------------------------------~------------------------------__, ~National PRELIMINARY ~ Semiconductor r i: .... G) CD .... r i: J\) G) LM168/LM268/LM368 Precision Voltage Reference General Description i: Co) Features The LM168/LM368 are precision, monolithic, temperaturecompensated voltage references. The LM168 makes use of thin-film technology enhanced by the discrete laser trimming of resistors to achieve excellent Temperature coefficient (Tempco) of VOUT (as low as 5ppml"C), along with tight initial tolerance, (as low as 0.02%). The trim scheme is such that individual resistors are cut open rather than being trimmed (partially cut), to avoid resistor drift caused by electromigration in the trimmed area. The LM168 also provides excellent stability vs. changes in input voltage and output current (both sourcing and sinking). This device is available in several output voltage options including 5.0V, 6.2V, and 10.0V and will operate in both series or shunt mode. The devices are short circuit proof when sourcing current. A trim pin is made available for fine trimming of VOUT or for obtaining intermediate values without greatly affecting the Tempco of the device. • .• • • • • • • • • G) 300 /LA operating current Low output impedance Excellent line regulation (.0001 %IV typical) Single-supply operation Externally trimmable Low temperature coefficient Operates in series or shunt mode 10.0, 6.2, or 5.0 volts Excellent initial accuracy (0.02% typical) Replaces 1N821-1N827 zeners Connection Diagram Metal Can Package Ne TL/H/5522-1 Top View ·case connected to V- Order Number LM168BYH-10, LM168BYH-6.2, LM168BYH-5.0, LM268BYH-10, LM268BYH-6.2, LM268BYH-S.O, LM368YH-10, LM368YH-6.2, LM368YH-S.O, LM368H-10, LM368H-6.2, LM368H-S.O See NS Package Number H08C Typical Applications Series Regulator Shunt Regulator 1 mA-l0 mA ! 2 6.200V TLlH/5522-2 TL/H/5522-3 (Replaces 1N827-type Zener) S4-1 .... r CD CD Absolute Maximum Ratings Input Voltage (Series Mode) Reverse Current (Shunt Mode) 35V Power Dissipation Storage Temperature Range Operating Temperature Range 50mA 600mW LM168 LM268 -60'C to + 150'C -55'Cto + 125'C -40'Cto + 85'C LM368 Lead Temperature (Soldering, 10 sec.) O'Cto +70'C 300'C Electrical Characteristics (Note 1) LM168/LM268/LM368 Parameter Conditions VOUT Error: LM168B, LM268B LM368 Typical Tested Limit (Note 2) ±0.02 ±0.02 ±0.05 ±0.1 Design Limit (Note 3) Units (Max. unless noted) % % Line Regulation (VOUT +3V) ,;;: VIN ,;;: 30V ±0.0001 ±0.0005 %N Load Regulation (Note 4) o mA,;;: ISOURCE';;: 10 rnA -10 mA,;;: ISINK';;: 0 mA ±0.0003 ±0.003 ±0.001 ±0.008 %/mA %/mA Thermal Regulation T=20 mS (Note 5) ±0.005 ±0.Q1 %/100mW 250 350 /LA 3 5 /LAN ±5 ±7.5 ±11 ±15 ±10 ±15 ±20 ±30 ppml'C ppml'C ppml'C ppml'C 30 70 100 mA Quiescent Current Change of Quiescent Current vs. VIN (VOUT +3V) ,;;: VIN ,;;: 30V Temperature Coefficient of VOUT (see graph): LM168BY (Note 6) LM268BY LM368Y LM368 -55'C,;;: TA';;: 125'C -40'C';;: TA';;: 85'C O'C';;: TA';;: 70'C O'C,;;: TA';;: 70'C Short Circuit Current VOUT = 0 Noise: 10.0V: 0.1 -10Hz 100Hz-10kHz 6.2V: 0.1 - 10Hz 100Hz -10 kHz 5.0V: 0.1 -10Hz 100Hz -10 kHz VOUT Adjust Range: 10.000V 6.200V 5.000V 30 1100 20 700 16 575 4.5-17.0 4.0-9.5 3.5-7.0 RTRIM = 100k Note 1: Unless otherwise noted, these specifications apply: TA = 25°C, VIN = 15V, ILOAD = uVp-p nV/JRZ uVp-p nV/JRZ uVp-p nV/JRZ 6.0-15.5 5.0-8.5 4.0-6.0 V min. V min. V min. 0, Circuit is operating In Series Mode. Note 2: Tested Limits are guaranteed and tOO% tested In production. Note 3: Design limits are guaranteed (but not 100% production tested) over the indicated temperature and supply voltage ranges. These limits are not used to calculate outgOing quality levels. Note 4: The LM168 has a Class B output, and will exhibit transients at the crossover point This point occurs when the device is asked to sink approximately 120 ".A. In some applications It may be advantageous to preload the output to either VIN or Ground. to avoid this crossover point. Note 5: Thermal Regulation is defined as the change in the output Voltage at a time T after a step change in power dissipation of 100 mW. Note 6: Temperature Coefficient of VOUT is defined as the worst case delta-VOUT measured at Specified Temperatures divided by the total span of the Specified Temperature Range (See graphs). There is no guarantee that the Specified Temperatures are exactly at the minimum or maximum deviation. S4-2 Typical Performance Characteristics Quiescent Current vs. Input Voltage and Temperature 400 ~ 300 m 125'C 25'C" :::0 .. 200 ~ ~ ~. 100 _~5~'CI ~ -!JI i-'" -I25,c ~ 10 20 30 INPUT VOLTAGE (V) o I !3\ ~ ~ 0.1 i--" ~ 1 ~ o Sl .I~ / I ! --, I ~7'r) ., :-1 , I ~ ~ 1 1 1_- !i! -5 70 ' - : -10 I -55 -40 0 25 7085 TEMPERATURE ('C) l ':" ~ ~ ~ 0.1 0.01 100 lk 10k FREQUENCY (Hz) Temperature Coefficient: LM268-10 (Curve B) Temperature Coefficient: LM168-10 (Curve C) 100 lk 10k lOOk 10 1M 10 ! lOOk 10 0: a 0: ~10.000V 3 FREQUENCY (Hz) 10 Temperature Coefficient: LM368-10 (Curve A) 10 ~ 4 I 0.0001 lOOk :;,.. !Ii IJ' iC 10 I 2 3 ~0.001 100 lk 10k FREQUENCY 1Hz) ~ / 0.01 Output Impedance vs. Frequency (Sinking Current) 100 .4 0.1 10 OUTPUT CURRENT (mA) Ripple Rejection vs. Frequency iil ~ " -10 10 ~ 4 0.01 10 -1 SOURCING -3 -4 ;;- ~~ ~ !Ii co ~ OUTPUT CURRENT (mA) Output Impedance vs. Frequency (Sourcing Current) I ~ . SINKING ~ :: co -2 i 40 I" ~ '--12~_ ... 1"" ~ !i! 1'00.. :[ ... 5 §: 10 ~ co 4 3 :r .. ~~ o Q Output Change vs. Output Current ~ -55'C 100 co - ,.... io-':: . ~~ E .... (Note 1) Dropout Voltage vs. Output Current (Series Mode Sourcing Current) n ~10.000V !j -5 co -10 125 " ~ 1 '" :9.3j mV !i! ~ --- 1 I - --- ~ 10.000V !j J !i! ~ C . 125'- ~"'1-' : -55 -40 co I 0 25 70 85 TEMPERATURE ('C) ,- ~ r --- - --- J " 9.35 mV -5 i=: -:-J 1-_ , -10 125 " 180' I -55 -40 /: "'""-1 I 0 25 7085 TEMPERATURE ('C) , 125 TL/H/5522-4 Output Noise vs. Frequency (1) LM368 as is. (3) with Ion in series with 10 f'f, VOUT to Gnd. (4) with Both. Typical Temperature Coefficient Calculations: 1600 (2) with 0.Q1 f'f Mylar, Trim to Gnd. LM368·10 (see Curve A) I' 11200 .,w J .'- ........ ~ 800 ....... ....!OV " ~ = 400 T.C.=7.7 mVl(70' x 1OV) 6.2t- = 11 I--- T.C. ~ 9.35 mV1(125' x 1OV) 5V =7.5X 10E-6=7.5ppm/'C LM168-10 (see Curve C) o 10 x 10E·6= l1ppml'C LM268-10 (see Curve B) 100 lk FREQUENCY (Hz) 10k T.C.=9.35 mVl(180'Xl0V) = 5.2X 1OE-6 = 5.2ppm/'C TL/H/5522-S 84-3 m ~ ~ .... r-----------------------------------------------------------------------------~ Simplified Schematic Diagram m ~ :!i ....m r-------------------~--------_.--_.-V+ CD ..... ~ ... Spf -l---+-WY-TRIM _FOR5V IllllFORUV l711k FOR lOY ~----~--~--~--~--_4--~--~----VOReg. !,J.S. Pat Off. 84-4 TlfHf5522-6 r- ....en iii: Typical Applications Narrow Range Trlmmable Regulator (± 1% min.) Wide Range Trlmmable Regulator CO ..... r- iii: r ......--l!.--.... Your 5 Al 20k N en CO ..... r- VOUT 2M L..."T":'..J~\I\ro4~~ 20k iii: (0) en CO TUH/5522-7 TLlH/5522-B Adjustable Zener Improved Noise Performance v· r........,!...---..... VDur 10"" TL/H/5522-10 TUH/5522-9 ± Reference ± 10V, ±5V References V· r...l.:.,L-.- +Vour 10V 5V -Your -5V VTL/H/5522-11 t> R~ Thin Film Resistor Network, ±0.05% Matching and 5ppm Tracking (Beckman 694-3-R-l0K-A), (Caddock T-914-1 OK-l 00-05) or similar. 54-5 TL/H/5522-12 • Typical Applications (Continued) MultIple Output Voltages y. 2IIV r .......t!--+--1UV 4.111 TlIHl5522-14 TlIHI5522-13 y. R= Thin Film Reslator Network 0.05% Matching and 5ppm Tracking (Beckman 694-3-R-10K-Al, (Caddock T-914-10K-100-05l or e/milar. TlIHI6522-16 Reference with Booster 100 mA Boosted Reference V· V· u 2NZI07 II1II 11111-ZIIO fW r--'~~VuuT ~ (lIPrIONAL .-.....,~-+-Vau! ~JlllE.l.OADl ------" 4 TlIHI6522-16 ~= ------' TlIHI5522-17 S4-6 Typical Applications (Continued) Buffered High-Current Reference with Filter V· TL/H/5522-18 54·7 U) ~ ~ ...... U) 1!S ~ ...... ~ .- :3 r--------------------------------------------------------------------------------, ~National PRELIMINARY ~ Semiconductor LM185/285/385 Adjustable Micropower Voltage Reference General Description The LM18S/LM28S/LM38S are micropower 3-terminal adjustable band-gap voltage reference diodes. Operating from 1.24 to S.3V and over a 10 /LA to 20 mA current range, they feature exceptionally low dynamic impedance and good temperature stability. On-chip trimming is used to provide tight voltage tolerance. Since the LM18S band-gap reference uses only transistors and resistors, low noise and good long-term stability result. Careful design of the LM18S has made the device tolerant of capacitive loading, making it easy to use in almost any reference application. The wide dynamic operating range allows its use with widely varying supplies with excellent regulation. The LM18S is rated for operation over a -SS·C to 12S·C temperature range, while the LM28S is rated -40·C to 8S·C and the LM38S O·C to 70·C. The LM18S is available in a hermetic TO-46 package and the LM28S/LM38S are available in a low-cost TO-92 molded package. Features • • • • • Adjustable from 1.24V to S.30V Operating current of 10 /LA to 20 mA 1% and 2% initial tolerance . 1 ohm dynamic impedance Low temperature coefficient , The extremely low power drain of the LM18S makes it useful for micropower circuitry. This voltage reference can be used to make portable meters, regulators or general purpose analog circuitry with battery life approaching shelf life. Further, the wide operating current allows it to replace older references with a tighter tolerance part. Connection Diagrams TD-92 Plastic Package TD-46 Metal Can Package ~ ~ Bottom View Bottom View TLlH/5250-1 Order Number LM185, LM285 or LM385 See NS Packages H03H and Z03A Typical Applications 1.2V Reference 5.0V Reference 9V 9V R1 50k R1 500k + I -1 LM385 ~ 5V 1.2V + I 1l LM385 ~ S4-8 r VOUT~1.24(~+1 ) R2 120k R3 364k TLlH/5250-2 Absolute Maximum Ratings Reverse Current Forward Current Operating Temperature Range LM185 Series - 40·C to 85·C LM285 Series O·Cto 70·C LM385 Series - 55·C to 150·C Storage Temperature Lead Temperature (Soldering, 10 seconds) 300·C 30mA 10mA -55·Cto125·C Electrical Characteristics (Note 1) Parameter Conditions LM185BX. LM185BY LM185B. LM285BX LM285BY. LM285 Typ Reference Voltage 1.240 IR=100"A B-Series LM285 and LM385 Reference Voltage Change with Current Min co 10~UW~~~~~~~ 10 100 lk 10k FREQUENCY (Hz) 100 lk 10k FREQUENCY (Hz) lOOk lOOk 50 100 150' 200 TIME (ps) TUH/5250-3 LM185 Temperature Coefficient Typical LM285 Temperature Coefficient Typical. i '&. o ~ 0 ,-----..,......,,..-------., (1.241 LM385 Temperature Coefficient Typical i '$ o -5 ~ 0 [;iiII-OP;;;;;::--, aV. -5 5000 -0.5 7000 -10~~~~~----~~~ -55 -25 0.035 0.0028 [!I 0 +25 +70+85 +125 TEMPERATURE (·C) mV/.C -55-40 mV/·C 0 +25 +70+85 +125 TEMPERATURE (·C) 0.025 W·C -+--...... "Ie/·C _ 0.002 ppm/·C ppml"C~ TEMPCO = 1OT~A~ I:/pm 7000 1-~:C~0~::2 L.: 'Ia/·C--'O.0026 . ppm/Dc_[ID TEMPCO +70 ,:"y =-:if TL/H/5250-4 84-10 Typical Applications (Continued) Precision 10V Reference Low AC Noise Reference 15V 15V Rl Rl 5K lOOK ..__......... ~g~T ...- ~~UT "--~t--- R2 301K 1% R2 nOk + r--.............., + C2 R3 10.F 68.1K 1% Cl R4 360 kll 200 mA Shunt Regulator 25V Low Current Shunt Regulator V+ V+ R3 R3 0.47.F 33 + R4 100.A < I < SmA 5O.A r---"'--+- r - -....---4II~ Your 25V • < I < 200mA Your 2.SV HI HI nOk 120k 2N2219 H2 120k H3 lk Serles·Shunt 20 mA Regulator High Efficiency Low Power Regulator 5.1V TO 16V VIN > ..._ .. -~ -, HEAT SINK Rl 22k Iq=70.A 0< lOUT < SOmA I 12N2905 _.J ....+-..... Vour -1.Bvro -5V VOUT=5V R2 3k A3 R3 1M R7 3l2k R4 10K 1% Cl 20k O.I"F + AS 10k A8 1M C2 500"F 1% -15V R6 22k TLlH/5250·5 54·11 Typical Applications (Continued) Voltage Level Detector Voltage Level Detector HI 120k HI 120k H2 1M H2 1M <-12V LEO ON - H3 A3 330 200 -5V -5V Fast Positive Clamp 2HV+ I. + > -12V LEO ON Bidirectional Clamp ~VOI .±2.4V VIN VIN HI Al A2 50pA 02 IN914 A3 240K A4 240K Bidirectional Adjustable Clamp ± 1.BV to ± 2.4V Bidirectional Adjustable Clamp ±2.4Vto.±6V VIN VIN Al HI ....... r----~---H2 330K VOUl 02 IN457 TLlH/5250-6 54-12 Typical Applications - (Continued) Simple Floating Current Detector Current Source +15V OT020mA HI HI 39011 ~2% lN4002 02 01' lp.A < lOUT < 100mA 10UTa~ HI Precision Floating Current Detector - OT020mA HI 33211 :!:1% 02 IN4002 01' TL/H/S2S0-7 , Dl can be any LED, VF=I.5V to 2.2V ,at 3 mAo 01 may act ao an indicator. Dl will be on il ITHRESHOLD lallo below the threshold current, except with 1=0. 54-13 Typical Application (Continued) Centigrade Thermometer, 10 mVrC Freezer Alarm _------_-IV R1 10k R5 &Ok 4.5V .:;, R5 12k IEEPS AT TEMPERATURES AIOVE THAT lET BY R1 (RANGE 18 - 1II"f Ia +12DoFi Schematic Diagram .1 FEEDBACK (FB) TUH/5250-8 54·14 ~National ~ Semiconductor LM185-1.2/LM285-1.2/LM385-1.2 Micropower Voltage Reference Diode General Description The LM185-1.2/LM285-1.2/LM385-1.2 are micropower 2terminal band-gap voltage regulator diodes. Operating over a 10 /loA to 20 rnA current range, they feature exceptionally low dynamic impedance and good temperature stability. Onchip trimming is used to provide tight voltage tolerance. Since the LM185-1.2 band-gap reference uses only transistors and resistors, low noise and good long term stability result. Careful design of the LM 185-1.2 has made the device exceptionally tolerant of capacitive loading, making it easy to use in almost any reference application. The wide dynamic operating range allows its use with widely varying supplies with excellent regulation. Features • Operating current of 10 p.A to 20 mA • 1% and 2% initial tolerance Schematic Diagram • 1!l dynamic impedance • Low temperature coefficient • Low voltage reference-1.235V • 2.5V device also available-LM385-2.5 The extremely low power drain of the LM185-1.2 makes it useful for micropower circuitry. This voltage reference can be used to make portable meters, regulators or general purpose analog circuitry with battery life approaching shelf life. Further, the wide operating current allows it to replace older references with a tighter tolerance part. The LM 185-1.2 is rated for operation over a - 55'C to 125'C temperature range while the LM285-1.2 is rated -40'C to 85'C and the LM385-1.2 COC to 70'C. The LM1851.2/LM285-1.2/LM385-1.2 are available in a hermetic TO46 package and the LM385-1.2 is also available in a lowcost TO-92 molded package. r-----~--~---t----~~-1~--~---+ Centigrade Thermometer Applications Wide Input Range Reference 2.211 Callbratton VIN' 2.lV TO lDV 1. Adjust R1 sa that V1 =temp at 1 mVl'K 1.5Vt 2. Adiust V2 to 273.2 mV 27. tlo for 1.3V to 1.6V battery voltage = 50 p.A to 150 ,.A TUH/5518-1 54-15 -.n .... -. .... C"! co Col) :::IE ..... C"! &I) co N :::IE ..... C"! Absolute Maximum Ratings Reverse Current Forward Current Operating Temperature Range LM185-1.2 LM285-1.2 LM385-1.2 30mA 10mA Storage Temperature Lead Temp. (Soldering, 10 seconds) . 300·C Electrical Characteristics (Note 1) LM185-1.2 LM185BX-1.2 LM185BY-1.2 LM285-1.2 LM285BX-1.2 LM285BY;1.2 co :::IE ..... + 150·C - 55·C to + 125·C -40"C to + 85·C O"Ct070"C • &I) - - 55·C. to Parameter Conditions Typ Reverse Breakdown Voltage TA= 25·0, IMIN s: IR s: IMAX LM185-1.2/LM285-1.2/LM385B-1.2 1.235 , Tested Umlt (Note 2) LM385-1.2 LM385B-1.2 LM385BX-1.2 LM385BY-1.2 Design Limit (Note 3) Typ 1.223 1.247 1.235 LM385-1.2 1.235 Minimum Operating Current 8 10 20 8 Tested Limit (Note 2) Units Limit Design Limit (Note 3) 1.223 1.247 1.205 1.260 VMIN VMAX VMIN VMAX 15 20 p.A Reverse Breakdown IMINS:IRS:1 mA 1 1.5 1 1.5 mV Voltage Change with Current 1 r'nAS:IRS:20 mA 10 20 20 25 mV Reverse Dynamic Impedance IR=40 p.A. f=20 Hz 1 1 {} Wideband Noise (rms) IR=100p.A 10 HzS:fS: 10 kHz 60 60 ",V Long Term Stability IR=100 p.A, T= 1000 Hr TA =25·C±0.1·C 20 20 ppm Average Temperature Coefficient (Note 4) IR= 100 p.A ppml"C X Series 30 30 YSeries ppml"C 50 50 150 ppml"C Other Versions 150 Nota 1: Parameters Identified with boldface type apply at temperature extremes and for IMIN ;I: ~ Ol OA D.. ~ '" -z u.s 1.4 1.0 1.2 0.01 REVERSE VOLTAGE IVI 1.255 0.1 10 Temperature Drift loa Reverse Dynamic Impedance ~ i.. 10 .... 5 .... i.. 1.225 0.1 ............._ 0.01 Noise Voltage .................... 0.1 ID / 0.1 10 loa 10 Filtered Output Noise &00 z.O 80 ~ .:! 500 ..... !!l 400 S 300 ZOO 100 0 10 100 Ik " IUk FREOUENCY IHII i ~ .. Iii 50 co 40 Ik 10k lOOk 1M Response Time r-~r--.....,.--r-....,..---' 1.5t=lZ$~~=~ 1.0 D.51--1-- w 30 ~ !:; 20 ~ 10 0 lOOk 1l1li FREQUENCY IHt/ 10 IR 'IOO"A ..'" V ./ loa REVERSE CURRENT ImAI 100 III Ik > TEMPERATURE rCI ..s loa Reverse Dynamic Impedance !. V 1215 -55 -35 -IS 5 25 45 6& 85 105 125 ~,. 10k 5 w V. 1.235 10 TA - 25'C 'R -IDOpA w '" 0.1 FORWARD CURRENTI"AI ~1.245 ~ 0 1.11 loa REVERSE CURRENT ImAI 'R"OO"A ~ D.• !:; lao Ik Ilk I.' CUTOFF FREQUENCY 11111 TUH/5518-3 84-17 LM385 Applications Nllcropower* 5V Regulator Mlcropower* 10V Reference r::--__- - -....--------4I~--"VIN~5.2V' >~~-""~IOV VO=SV r--~~~~ IL $IOOmA IS0pF 3.SM SOOk LM3B5-1.2 10M • 10 "'" 20 p.A standby current Precision 1 /LA to t mA Current Sources LM3B5-1.Z LM3BS-1.2 Cl IS0pF ----'II'\,.,..... I.SVTO 2 7 V - - - -... ..... -1.SV TO -27V -:--...:;;-...-....;.-+-",.,.~ -30V TUH/551B-4 54·18 LM385 Applications (Continued) METER THERMOMETERS O"C -100"C Thermometer Lower Power Thermometer 150 UTO 1.6V* iHO I2kt 1.5V t 11.3-1.6VI • 2N3638 or 2N2907 select for inverse HFE '" 5 R4 220 t Select for operation at 1.3V * 10 .. 600 p.A to 900 p.A calibration I. Short LM385·1.2, adjust R3 for lour=temp at 1 p.AI'K 2. Remove short, adjust R2 for correct reading in centigrade tla at 1.3V" 500 p.A 10 at 1.6V" 2.4 rnA O"F-50'F Thermometer Mlcropower Thermocouple Cold Junction Compensator v+ 2k 5.lk MERCURY CELL I.345V '" 1M 1% V- + TCADJ 500 LM385-1.2 I.3-I.6V RI R2 + THERMOCOUPLE METER '-' COLD JUNCTION ISOTHERMAL WITH LM334 calibration 1. Short LM385·I.2, adjust R3 for lour= temp at 1.8 p.AI'K 2. Remove short, adjust R2 for correct reading in 'F + Adjustment Procedure TLlH/S51a-5 I. Adjust TC ADJ pot until voltage across Rl equals kelvin temperature multiplied by the thermocouple .eebeck coefficient. 2. Adjust zero ADJ pot until voltage across R2 equals the thermocouple seedbeck coefficient multiplied by 273.2. Thermocouple Seebeck Rl R2 Voltage Voltage AcropRl Acro•• R2 Type Coefflctent (n) (n) C112!rC (my) (p.vrC) (my) 52.3 523 1.24k 15.60 14.32 J 11.78 432 Ik 12.77 42.8 T 11.17 40.8 412 953n 12.17 K 1.766 63.4 ISDn S 6.4 1.908 Typical supply current 50 p.A S4·19 ~ ...: .n ~ =s .;...I ~ .- ,---------------------------------------------------------------------------------Connection Diagrams TO-92 Plastic Package TO-46 Metal Can Package .n CD ~ ~ ~ .- ~ .~ BOTTOM VIEW BOTTOM VIEW TUH/551B-6 Order Numbers LM185-1.2, LM285-1.2, LM385-1.2 See NS Packages H02A, Z03A S4-20 r- iii: .... CD ~National CI1 N • ~ Semicondllctor en r- LM 185-2.5/LM285-2.5/LM385-2.5 Micropower Voltage Reference Diode iii: N CD Cf1 N en r- General Description The LM185-2.5/LM285-2.5/LM385-2.5 are micropower 2terminal band-gap voltage regulator diodes. Operating over a 20 /LA to 20 mA current range, they feature exceptionally low dynamic impedance and good temperature stability. Onchip trimming is used to provide tight voltage tolerance. Since the LM-185-2.5 band-gap reference uses only transistors and resistors, low noise and good long term stability result. Careful design of the LM185-2.5 has made the device exceptionally tolerant of capacitive loading, making it easy to use in almost any reference application. The wide dynamic operating range allows its use with widely varying supplies with excellent regulation. Features • Operating current of 20 /LA to 20 mA • 1.5% and 3% initial tolerance • 10 dynamic impedance • Low temperature coefficient • Low voltage reference-2.5V The extremely low power drain of the LM185-2.5 makes it useful for micropower circuitry. This voltage reference can be used to· make portable meters, regulators or general purpose analog circuitry with battery life approaching shelf life. Further, the wide operating current allows it to replace older references with a tighter tolerance part. For applications requiring 1.2V see LM185-1.2. The LM 185-2.5 is rated for operation over a - 55'C to 125'C temperature range while the LM285-2.5 is rated -40'C to 85'C and the LM385-2.5 O'C to 70'C. The LM1852.5/LM285-2.5/LM385-2.5 are available in a hermetic TO46 package and the LM385-2.5 is also available in a lowcost TO-92 molded package. Schematic Diagram RI ZOOk Rl 50k R4 10k 500k 500k Applications Wide Input Range Reference YIN' 3.1Y TO 30Y TL/H/5519-1 54-21 iii: Co) CD CI1 ~ en Absolute Maximum Ratings Reverse Current Forward Current Operating Temperature Range LM185-2.5 LM285-2.5 LM385-2.5 Storage Temperature Lead Temp. (Soldering, 10 seconds) 30mA 10mA -55°C to + 125°C -40·C to + 85·C O·Cto 70"C -55·Cto + 15O"C 300·C Electrical Characteristics (Note 1) LM185-2.5 LM185BX-2.5 LM185BY-2.5 LM285-2.5 LM285BX-2.5 LM285BY-2.5 Conditione Parameter Typ Reverse Brellkdown Voltage TA= 25·C, IMIN s; IR s; IMAX LM185-2.5/LM285-2.5/LM385B-2.5 Teeted Umlt (Note 2) 2.5 LM385-2.5 LM385B-2.5 LM385BX-2.5 LM385BY-2.5 Dealgn Umlt (Note 3) 2.462 2.538 2.5 LM385-2.5 2.5 Minimum Operating Current 13 Reverse Breakdown Voltage Change with Current 20 ,...A~IRS; 1 mA 1 mA~IR~20 rnA Reverse Dynamic Impedance IR= 100 ,...A. 1=20 Hz Wideband Noise (rms) Typ 20 30 1 10 1.5 20 13 Teeted Umlt (Note 2) UnHe Unlit Deelgn Limit (Note 3) 2.462 2.538 2.425 2.575 VMIN VMAX VMIN VMAX 20 30 p.A 2.0 20 2..5 25 mV mV 1 1 n IR=100,...A 10 Hz~1~ 10 kHz 120 120 ,...V Long Term Stability IR=100 ,...A, T= 1000 Hr TA=25·C±0.1 DC 20 20 ppm Average Temperature Coefficient (Note 4) IR=100,...A X Series YSeries Other Versions 30 50 30 50 150 150 ppm/DC ppm/·C ppm/·C Note 1: Parameters Identified with bOldface type apply at temperature extrelnes and for IMIN - V /' ./ D.I 5 25 45 IS IS 105 125 0.01 Noise 0.1 10 REVERSE CURRENT (mAl 10 100 120 1200 100 1-+++fI1IH1--f-! 1000 ~ 1111 6 1111 S III ~ co 4DO ~ 2DO Ik 10k FREQUENCY (Hz) IDOk ~ co z .... .. ~ liD 1.0 co 40 10 Ik 10k IDOk I-I-I-- ~ > 20 I 2.0 !:i CUTDFF FREQUENCY (Hz) 1k 10k lOOk I 1\.1 DUTPUT ~f-., "'. = .. I INPUT I 200 TIME 4D0 600 (~I) TlIH/5519-3 54-23 1M Response TIme 3.0 10 100 laD FREQUENCY (Hz) Filtered Output Noise 14D1 IDO 10 u .. 2A60 I 10k >- 10 0.1 Reverse Dynamic Impedance IDO TEMPERATURE ('C) '" 0.01 FDRWARD CURRENT (mAl iz 2A7D 2A5D -55 -35 -15 6 100 ;00 r- .... i--'" ~ 2AIO III 10 "25Hz S w ~2.S10 ~ I 'R- 1DO I'A i!:i 2.500 II: 0.1 REVERSE CURRENT (mAl Temperature Drift 2.520 ! 0.01 3.0 . an eN an co CO) ::! ..... an LM385-2.5 Applications Micropower* 5V Regulator Mlcropower* 10V Reference - ..J 10 r----....-- VIN·,5V ~-------.---------.~---VIN~51V S!co 500k 41k ('II. ::! ..J ..... an eN r---"'-"'- anco .... ::! ..J Vo I'L ,s;=5V IOOmA lOOk + LM385·2.5 10M 4.1 pF TANTALUM Zk TLlH/5519-10 '10 .. 30 p.A standby current TL/H/5519-9 Precillion 1 /LA to 1 mA Current SOurces LM385·2.5 LM381i-Z.5 CI 150pF 1.5VTO ZIV--..;..---4----~"""~ -1.5V TO -21V ..;.-...:;;....-4---+.JI,,..,.,~ -30V TLlH/5519-4 "OUT=2~~V METER THERMOMETERS O"C-100"CThermometer O'F-50"F Thermometer lk lk R4 R4 100 220 TL/H/5519-5 CallbraUon Calibration 1. Short LM385-2.5, adjust R3 for 'OUT=temp at 1"AI'K 1. Short LM385·2.5, adjust R3 for IOUT=temp at 1.8 "AI'K 2. Remove shari, adjust R2 for correct reading in centigrade 2. Remove short, adjust R2 for correct reading in 'F 54-24 LM385-2.5 Applications (Continued) Mlcrqpower Thermocouple Cold Junction Compensator Adjustment Procedure 1ft t. Adjust TC ADJ pot until voltage across Rt equals Kelvin temperature multiplied by the thermocouple Seebeck coeffICient 'M '" 2. Adjust zero ADJ pot until voltage across R2 equals the thermocouple Seebeck coefficie~t multiplied by 273.2. TCAOJ 3V + LITHIUM 5DO LM31U5 + THERMOCOUPLE + METER \_" COLD JUNCTION ISOTHERMAL WITH LM334 TL/H/5519-6 Thermocouple Type Seebeck Caefficient R1 (0) R2 (0) 523 432 412 63.4 1.24k 1k 9530 1500 (,.vrC) J S2.3 42.8 40.8 6.4 T K 5 Voltage AcroisR1 @2SD C (my) 15.60 12.77 12.17 1.908 Voltage AcroaaR2 (mY) 14.32 11.78 11.17 1.766 Typical supply curren1 50 p.A Improving Regulation of Adjustable Regulators TLlH/551B-7 Connection Diagrams TO-46 " Metal Can Package ro-92 Plastic Package BOTTOM VIEW BOTTOM VIEW Order Numbers LM185-2.S, LM285-2.S, LM385-2.S See NS Packages H02A, Z03A 54-25 TL/H/551B-9 ~National ~ Semiconductor LM 199AH-20, LM299AH-20, LM399AH-50 Ultra-Stable" References General Description The National Semiconductor LM199AH-20, LM299AH-20, and LM399AH-50 are ultra-stable Zener references specially selected from the production runs of LM199AH, LM299AH, LM399AH and tested to confirm a long-term stability of 20,20, or 50 PPM per 1000 hours, respectively. The devices are measured every 168 hours and the voltage of each device is logged and compared in such a way as to show the deviation from its initial value. Each measurement is taken with a probable-worst-case deviation of ± 2 ppm, compared to the Reference Voltage, which is derived from several groups of NBS-traceable references such as LM199AH-20's, 1N827's, and saturated standard cells, so that the deviation of anyone group will not cause false indications. Indeed, this comparison process has recently been automated using a specially prepared computer program which is custom-designed to reject noisy data (and require Ei repeat reading) and to record the average of the best 5 of 7 readings, just as a sagacious standards engineer will reject unbelievable readings. The typical characteristic for the LM199AH~20'is shown on the next page. This computerized print-out form of each reference's stability is shipped with the unit. For typical application circuits, refer to the LM199 data sheet on preceding pages. For typical performance characteristics, refer to the LM199A data sheet on preceding pages. Features • Sub-surface zener is not degraded by surfacecontamination • Proven reliability, low-stress packaging in T0-46 integrated-circuit hermetic package, for low hysteresis after thermal cycling. 33 million hours MTBF at TA = + 25'C (TJ = +86'C) • Low noise guaranteed. • Low temperature coeffiCient, % ppm/'C guaranteed. Connection and Functional Block Diagrams 3 + I I I TLIH16762-1 Order Number LM199AH-20, LM299AH·20, or LM399AH·50 See NS, Pkg. H04D 1.4 TL1H16762-2 54-26 Absolute Maximum Ratings Temperature Stabilizer Voltage Reverse Breakdown Current Forward Current Reference to Substrate Voltage VIAS) (Note 1) 40V 20 rnA 1 rnA +40V -O.w Operating Temperaure Range LM199A LM299A LM399A Storage Temperature Range Lead Temp. (Soldering. 10 seconds) - SS·C to + 12S·C - 2S·C to + 8S·C O·Cto +70·C - SS·C to + 1S0·C 300·C Electrical Characteristics (Note 2) LM199AH·20, LM299AH·20 Conditions Parameter Reverse Breakdown Voltage 0.SmA,,;IA,,;10mA Reverse Breakdown Voltage Change With Current O.S mA,,;IA";1O rnA -SS·C,,;TA,,;8S·C 8S·C,,;TA,,;12S·C -2S·C,,;TA,,;8S·C 0·C,,;TA,,;70·C } Units Min Typ Max Min Typ Max 6.8 6.9S 7.1 6.6 6.9S 7.3 V 6 9 6 12 mV O.S 1.S Reverse Dynamic Impedance IA = 1 rnA Reverse Breakdown Temperature Coefficient LM399AH·50 LM199A LM299A LM399A O.S 1 0.00002 O.OOOS 0.00002 O.OOOOS 0.0010 O.OOOOS 0.00003 0.0001 n %,·C %I"C %I"C %I"C RMSNoise 10 Hz,,;f,,;10 kHz 7 20 7 SO /LV Long Term Stability Stabilized,22"C,,;TA,,;28·C, 1000 Hours.IA = 1 rnA ±0.1 % 8 20 9 SO ppm 8.S 1S rnA 40 rnA V 200 rnA Temperature Stabilizer TA=2S·C. Still Air. Vs=30V 8.S 14 Supply Current Temperature Stabilizer Supply Voltage TA= -SS·C 22 28 40 Warm-Up Time to O.OS% Vs=30V. TA=2S·C Initial Turn-on Current 9,,;Vs";40. TA=2S·C 9 9 3 140 3 200 140 s Note 1: The substrate Is electrically connected to the negative terminal of the temperature stabilizer. The voltage that can be applied to either terminal 01 the relerence is 40V more positive or O.1V more negative than the substrate. Note 2: These specilications apply lor 30V applied to the temperature stabilizer and - 55'C';;TA';; + 125'C lor the LMI99A; - 25'C';TA';; + 85'C lor the LM299A and O'C,;;TA';; +70'C lor the LM399A. Typical Characteristics National Semiconductor Certified Long Term Drift HRS DRIFT 168 336 S04 672 840 1008 -20 -24 -36 -34 -40 -36 LM199AH-20 Part #6849 Limits LM199AH-20 140 /LV LM299AH-20 140 /LV LM399AH-SO 3S0 /LV Testing Conditions Heater Voltage 30V Zener Current 1 rnA Ambient Temp. 2SC 120 0 80 R I F T J.·V 40 0 ---- -40 --- -80 -120 0 168 336 504 HOURS S4·27 672 840 ta0S TL/H/6762-3 Section 5 Converters Converters Section Contents Analog to Digital ADC0816, 0817 8-Bit p.P Compatible AID Converters with 16 Channel Multiplexer .................................. S 5-1 . ADC0820 8-Bit High Speed ",p Compatible AID Converter with Track/Hold Function •.• ; .••.•....•...•..•..•...•.• S 5-12 ADC0829p.P Compatible 8-Bit AID with 11 Channel MUX/Digilalinput ...•.•••••••••.•.......••••.•..•.•••••••.. S 5-28 ADC0831, AOC0832, AOC0834, ADC0838 8-Bit Serial 110 AID Converters with Multiplexer Options ...••....•....••• S 5-36 ADC0833 8-Bit Serial 1/0 AID Converter with' 4-Channel Multiplex6r •••••...••••.•.•••..•.•.•.•••..••...•••••.... S 5-60 ADC0844 8-Bit ",p Compatible AID Converter with 4-Channel Multiplexer ...•...•••..•.•.•...•.•.•.•.•.•...•••••. S 5-78 ADC1210, ADC121112-BitCMOSAlDConverters ............................................................S5-93 Digital to Analog DAC0830, DAC0831, DAC0832 Micro-Dac 8-Bit p.P Compatible, Double-Buffered 0 to A Converters ••••••••...•••.• S 5-104 DAC1265A, DAC1265 High Speed 12-Bit 01 A Converter with Reference ..•......•..•.••.•.••........••.......•. S 5-120 DAC1266A, DAC1266 High Speed 12-Bil D/ACOnverter ...................................................... S 5-129 Special Converters LM131 AlLM131, LM231 AlLM231, LM331A1LM331 Precision Voltage-to-Frequency Converters ••.•.•.•.•••••••.•• S 5-137 r----------------------------------------------------------------,~ C g ~National ~ Semiconductor ADC0816, ADC0817 8-Bit J.LP Compatible AID Converters with 16-Channel Multiplexer General Description Features The ADC0816, ADC0817 data acquisition component is a monolithic CMOS device with an 8-bit analog-to-digital converter, 16-channel multiplexer and microprocessor compatible control logic. The 8-bit AID converter uses successive approximation as the conversion technique. The converter features a high impedance chopper stabilized comparator, a 2S6R voltage divider with analog switch tree and a successive approximation register. The 16-channel multiplexer can directly access anyone of 16-single-ended analog signals, and provides the logic for additional channel expansion. Signal conditioning of any analog input signal is eased by direct access to t!le multiplexer output, and to the input of the 8-bit AI D converter. • • • • • • The device eliminates the need for external zero and fullscale adjustments. Easy interfacing to microprocessors is provided by the latched and decoded multiplexer address inputs and latched TIL TRI-STATE@ outputs. . The design of the ADC0816, ADC0817 has been optimized by incorporating the most desirable aspects of several AID conversion techniques. The ADC0816, ADC0817 offers high speed, high accuracy, minimal temperature dependence, excellent long-term accuracy and repeatability, and consumes minimal power. These features make this device ideally suited to applications from process and machine control to consumer and automotive applications. For similar performance in an 8-chaimel, 28-pin, 8-bit AID converter, see the ADC0808, ADC0809 data sheet (See AN-2S8 for more information.) • • • • • • • • • • Resolution---a-bits Total unadjusted error-± tIz LSB and ± 1 LSB No missing codes Conversion tim&-100 "S Single supply-S Voc Operates ratiometrically or with S Voc or analog span adjusted voltage reference 16-channel multiplexer with latched control logic Easy interface to all microprocessors, or operates "stand alone" Outputs meet T2L voltage level specifications OV to SV analog input voltage range with single SV supply No zero or full-scale adjust required Standard hermetic or molded 40-pin DIP package Temperature range-40·C to +8S·C or -SS·C to + 12S·C Low power consumptlon-1S mW Latched TRI-STATE output Direct access to "comparator in" and "multiplexer out" for Signal conditioning Block Diagram COMPARATOR IN -----......... . MULTIPLEXER OUT START CLOCK r..m No - - -r---.L----1L-.-, I ~!==::::;:- I ~ __ OENO OF CONVERSION (INTERRUPTI I I I II ANALOG INPUTS TRI· STATE OUTPUT LATCH IUFFER AOORESS LATCH ENAILE EXPANSION CONTROL ADORESS LATCH ANO OECOOER 11 VCC OUTPUT ENABLE GNO TLlH/5277-1 S S-1 CD -4 ~C (') Q CD .... ..... Absolute Ma~imum Ratings (Notes 1 & 2) Supply Voltage (vccl (Note 3) 6.5V Voltage at Any Pin -O.3Vto (Vcc+0.3V) Except Control Inputs -0.3Vto 15V Voltage at Control Inputs (START, OE, CLOCK, ALE, EXPANSION CONTROL, ADD A, ADD B, ADD C, ADD D) Storage Temperature Range -65°C to + 150"C Package Dissipation at TA = 25°C 875mW Lead Temperature (Soldering, 10 seconds) 300"C Operating Conditions (Notes 1 & 2) , Temperature Range (Note 1) TMINS:TAS:TMAX ADC0816CJ -55°CS:TA + 125"C ADC0816CCJ, ADC0816CCN, -40"CS:TAS: +85"C ADC0817CCN Range of Vcc (Note 1) 4.5 Voc to 6.0 VOO Voltage at Any Pin OV to Vcc Except Control Inputs Voltage at Control Inputs OVto 15V (START, OE, CLOCK, ALE, EXPANSION CONTROL, ADD A, ADD B, ADD C, ADD D) Electrical Charact.ristics Converter Specifications: Vcc=5 Voc= VREF(+), VREF(-)=GND, VIN=VCOMPARATOR IN,TMINS:TMAX and fOLK = 640 kHz unless otherwise stated. Symbol Parameter VREF(+) VREFI+I+VREFI-I' 2 VREF{-) Max Units 25°C TMINto TMAX ±% ±% LSB LSB ADC0817 Total Unadjusted Error (Note 5) O"Ct070"C TMINtoTMAX ±1 ±1% ' LSB LSB ADC0816 Total Unadjusted Error (Note 5) Conditions Input Resistance From Ref( + ) to Ref( -) Analog Input Voltage Range (Note 4)V( + ) or V( -) Voltage, Top of Ladder Measured at Ref( + ) Min Typ 1.0 4.5 GND-0.10 Voltage, Center of Ladder Vcc/2 - O.1 kO , Vcc+ 0.1O Voc Vcc Vcc+ 0.1 V Vcc /2 Vcc/2 + O.1 V 2 p.A Voltage, Bottom of Ladder Measured at Ref( -) -0.1' 0 Comparator Input Current fc= 640 kHz, (Note 6) -2 ±0.5 V Electrical Characteristics Digital Levels and DC Specifications: ADC0816CJ 4.5VS:VccS:5.5V, -55°CS:TAS: + 125°C unless otherwise noted. ADC0816CCJ, ADC0816CCN, ADC0817CCN 4.75VS:VccS:5.25V, -40°CS:TAS: + 85°C unless otherwise noted. Symbol I Parameter ANALOG MULTIPLEXER I Conditions Analog Multiplexer ON Resistance (Any Selected Channel) TA=25°C, RL =10k TA=85°C TA=125°C ARoN AON Resistance Between Any 2 Channels (Any Selected Channel) RL=10k IOFF+ OFF Channel Leakage Current Vcc=5V, VIN=5V, TA=25°C TMINtoTMAX RON IOFF(-) OFF Channel Leakage Current Voo=5V, VII~=O, TA=25°C TMINtoTMax I Min I Typ 1.5 I Max / 3 6 9 75 10 I Units kO kO kO 0 200 1.0 -200" -1.0 nA p.A nA p.A CONTROL INPUTS VIN(1) Logical "1" Input Voltage VIN(O) Logical "0" Input Voltage IIN(1) Logical "1" Input Current (The Control Inputs) VIN=15V IIN(O) Logical "0" Input Current (The Control Inputs) VIN=O Icc Supply Current fOLK = 640 kHz V Vcc- 1.5 1.5 V 1.0 p.A -1.0 S5-2 p.A 0.3. 3.0 mA Electrical Characteristics (Continued) Digital Levels and DC Specifications: ADC0816CJ-4.5V S:VeeS: 5.5V, - 55°Cs:TAS: + 125°C unless otherwise noted. ADC0816CCJ,ADC0816CCN, ADC0817CCN-4.75VS:Vee S:5.25V, -40"CS:TAS: + 85°C unless otherwise noted. Symbol I Parameter I Conditions I Min I Typ I Max I Units DATA OUTPUTS AND EOC (INTERRUPT) VOUT(1) Logical "1" Output Voltage 10-360 /LA, TA=85°C 10= -300 /LA, TA=125°C Vee- 0•4 V VOUl(Qt Logical "0" Output Voltage 10=1.6mA 0.45 V VOUT(O) Logical "0" Output Voltage EOC 10=1.2mA 0.45 V lOUT TAl-STATE Output Current Vo=Vee VO=O 3.0 /LA /LA -3.0 Electrical Characteristics Timing Specifications: Vee = VREF( +) = 5V, VREF( -) = GND, tr= tf = 20 ns and TA = 25°C unless otherwise noted. Typ Max Units tws Minimum Start Pulse Width (Figure 5) (Note 7) 100 200 ns Symbol Conditions Parameter Min tWALE Minimum ALE Pulse Width (Rgure5) 100 200 ns is Minimum Address Set-Up Time (FigureS) 25 50 ns TH Minimum Address Hold Time (FigureS) 25 50 ns to Analog MUX Delay Time from ALE As = OO(Figure 5) 1 2.5 /LS tH1, tHO OE Control to Q Logic State CL =50 pF, AL = 10k (Figure 8) 125 250 ns t1H,toH OE Control to Hi-Z CL = 10 pF, AL = 10k (Figure 8) 125 250 ns Ie Conversion Time fe = 640 kHz, (Figure 5) (Note 8) 90 100 116 /Ls fc Clock Frequency 10 640 1280 kHz tEOe EOC Delay Time (FigureS) 8+2/Ls Clock Periods CIN Input Capacitance At Control Inputs 15 pF 0 10 TAl-STATE Output AtTAI-STATE Outputs (Note 8) 10 15 pF Capacitance Note 1: Absolute maximum ratings are those values beyond which the life of the device may be impaired. Note 2: All voltages are measured with respect to GND, unless otherwise spacified. Nota 3: A zener diode exists, internally, from Vcc, to GND and has a typical breakdown voltage of 7 Vee. Note 4: Two on-chlp diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the Vee supply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 100 mV,the output code will be correct To achieve an absolute a Vee to 5 Vee input voltage range will therefore require a minimum supply voltage of 4.900 Vee over temperature variations, initial tolerance and loading. Nota 5: Total unadjusted error includes offset, full·scaIe, and linearity errors. See Fl{Jure 3. None of these AIDs requires a zero or full-scale adjust. However, Han all zero code is desired for an analog input other than O.OV, or if a narrow full·scale span exists (for example: O.5V to 4.5V full·scaIe) the reference voltages can be adjusted to achieve this. See figure 13. COUT Note 6: Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current varies directly with clock frequency and has little temperature dependence (Figura 6). See paragraph 4.0. Nota 7: If start pulse is asynchronous with converter clock the minimum start pulse width is 8 clock periods plus 2 ,.s. Note 8: The outputs of the data register are updated one clock cycle before the rising edge of EOC. S5-3 • Functional Description Multiplexer: The device contains a 16-channel slngle-ended analog signal multiplexer. A particular input channel is selected by using the address decoder. Table 1 shows the input states for the address line and the expanSion control line to select any channel. The address is latched into the decoder on the low-to-high transition of the address latch enable signal. TABLE 1 Selected Analog Channel INO IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 IN11 IN12 IN13 IN14 IN15 All Channels OFF AddreasUne 0 C B A L L L L L L L L H H H H H H H H L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H X X X X Additional single-ended analog signals can be multiplexed to the AID converter by disabling all the multiplexer inputs using the expansion control. The additional external signals are connected to the comparator input and the device ground. Additional. Signal conditioning (i.e., prescaling, sampie and hold, instrumentation amplification, etc.) may also be added between the analog input signal and the comparator input. Expansion Control CONVERTER CHARACTERISTICS The Converter The heart of this single chip data acquisition system is its 8bit analog-ta-digital converter. The converter is designed to give fast, accurate, and repeatable conversions over a wide range of temperatures. The converter is partitioned into 3 major sections: the 256R ladder network, the successive approximation register, and the comparator. The converter's digital outputs are positive true. The 256R ladder network approach (Figure 1) was chosen over the conventional R/2R ladder because of its inherent monotonicity, which guarantees no missing digital codes. Monotonicity is particularly important in closed loop feedback control systems. A non-l!I0notonic relationship can cause oscillations that will be catastrophiC for the system. Additionally, the 256R network does not cause load variations on the reference voltage. The bottom resistor and the top resistor of the ladder network in Agure 1 are not the same value as the remainder of the network. The difference in these resistors causes the output characteristic to be symmetrical with the zero and full-scale points of the transfer curve. The first output transition occurs when the analog signal has reached + Yz LSB and succeeding output transitions occur every 1 LSB later . up to full-scale. H H H H H H H H H H H H H H H H L x = don't care 1• Rue>IO--- CONTROLS FROM U.R. I •+ II1R .:'J-7· · R . . lSIR : R R IIR · · · ·· · ·· · · :J ~ ~gMPARATOR INPUT · · · · · :'J-~ R£F(-IO--- TL/H/5271-2 FIGURE 1. Resistor Ladder and Switch Tree 55-4 l> C Functional Description n (Continued) The successive approximation register (SAR) performs B iterations to approximate the input voltage. For any SAR type converter, n-iterations are required for an n-bit converter. Figure 2 shows a typical example of a 3-bit converter. In the ADCOB16, ADC0817, the approximation technique is extended to 8 bits using the 256R network. The most important section of the AID converter is the comparator. It is this section which is responsible for the ulimate accuracy of the entire converter. It is also the comparator drift which has the greatest influence on the repeatability of the device. A chopper-stabilized comparator provides the most effective method of satisfying all the converter requirements. The AID converter's successive approximation register (SAR) is reset on the positive edge of the start conversion (SC) pulse. The conversion is begun on the falling edge of the start conversion pulse. A conversion in process will be interrupted by receipt of a new start conversion pulse. Continuous conversion may be accomplished by tying the endof-conversion (EOC) output to the SC input. If used in this mode, an external start conversion pulse should be applied after power up. End-of-conversion will go low between 0 and 8 clock pulses after the rising edge of start conversion. . S a. ~ [--FULL.SCALE ERROR = 1/2 LSB C o o C» ..... ~ INFINITE RESOLUTION PERFECT CONVERTER 111 -" ....... .a=: 101 CI 100 ~ m ....... l> The chopper-stabilized comparator converts the DC input signal into an AC Signal. This Signal is then fed through a high gain AC amplifier and has the DC level restored. This technique limits the drift component of the amplifier since the drift is a DC component which is not passed by the AC amplifier. This makes the entire AID converter extremely insensitive to temperature, long term drift and input offset errors. Figure 4 shows a typical error curve for the ADC0816 as measured using the procedures outlined in AN-179. 111 110 i..... 011 010 . L 110 _ I 101 :::> 100 :::> 011 -1 LSB ABSOLUTE ACCURACY ~ -112 LSB QUANTIZATION 010 001 LU.-I18-Z-/B-J/-B-4-18-5/-B-6/-B-l-18- VIN ERROR 0000181C..L1-18-ZIB-3-18-4-IB-518-6-1B-11B-- YIN YIN AS FRACTION OF FULL-SCALE YU'4 AS FRACTION OF FULL·SCALE TUH/5277-3 TL/H/5277-4 FIGURE 2. 3-Blt AID Transfer Curve FIGURE 3. 3-Bit AID Absolute Accuracy Curve FIGURE 4. TypIcal Error Curve S5-5 • ~ r-----------------------------------------------------------------------------~ ..- ~ g Connection Diagram ~ ..- Dual-In-Package CD ~ ~ See Ordering Information OUTPUT ENABLE TOP VIEW TUH/52n-6 Timing Diagram r-In-j CLOCK ,---, START IInI II1II I 1-""ALE !III -~ II1II _--11--_ ALE I -. - ~ ~ STAlLE AOORESS AOOII£SS I I 'M ANALOG ; STAILE INPUT s~.".. OUT r- '0OUTPUT ENAILE OUTPUTS X : MULTIPLEXER EOC ~ / I f---'r:c 1- I 't '-- -1 ----------------..!!",!Y~E-------------------_{I.._ _ _ _ _....J}TUH/52n-7 FIGURES S5·6 Typical Performance Characteristics ...----,----.---r--.... 1.& j C! u t---+---t---;;f-.;bo---f e z ~ co ... ~ ...~ II: ~ 0 ~ -0.5 I-:d~P--t--+---f -I I.2S o L-_-'-_--'-_ _.1.-_-' o I.2S 2.5 3.75 3.7S V,NIVI TUH/5277-8 FIGURE 6. Comparator liN VB VIN (Vee = VREF= 5V) TRI~STATE FIGURE 7. MuHlplexer RON VB VIN (VCC=VREF=5V) Test Circuits and Timing Diagrams t,K. C L = 10 pF t ,H• tHI vee OUTPUT ENABLE Vee GNO --.!.!~l""'----- OUTPUT ENABLE VOH~'H OUTPUT ':' . "'-GNO ------::= ___..J}"'"SOII--TUH/5277-9 =f' tOH' tHO Vee OUTPUT ENA.LE Vee Vee OUTPUT 9011 ENABLE~SO% GNO ---..!I.!IlI.!=l'------- OUTPUT Vee ~~ VOL~ TLlH/5277·10 FIGURE 8 55·7 .... r---------------------------------------------------------------------------------, ~ ~ ~ .... I . Applications Information OPERATION 1.0 RATIOMETRIC CONVERSION The ADC0816, ADC0817 is designed as a cOmplete Oata Acquisition System (DAS) for ratiometric conversion systems. In ratiometric systems, the physical variable being measured is expressed as a percentage of full-scale which is not necessarily related to an absolute standard. The voltage input to the ADC0816Is expressed by the equation VIN Dx Vfs-VZ DMAX-DMIN VIN = Input voltage into the ADC0816 V's = Full-scale voltage Vz = Zero voltage Dx = Data pOint being measured DMAX = Maximum data limit DMIN = Minimum data limit Ratiometric transducers such as pOtentiometers, strain gauges, thermistor bridges, pressure transducers, etc., are suitable for measuring proportional relationships; however, many types of measurements must be referred to an absolute standard such as voltage or current This means a system reference must be used which relates the full-scale voltage to the standard volt. For example, if Vee = VREF = 5.12V, then the full-scale range is divided into 256 standard steps. The smallest standard step is 1 LSB which is then 20 mV. 2.0 RESISTOR LADDER LIMITATIONS The voltages from the resistor ladder are compared to the selected input 8 times in a conversion. These voltages are coupled to the comparator via an analog switch tree which Is referenced to the supply. The voltages at the top, center and bottom of the ladder must be controlled to maintain proper operation. The top of the ladder, Ref( +), should not be more positive than the supply, and the bottom of the ladder, Ref( -), . should not be more negative than ground. The center of the ladder voltage must also be near the center of the supply because the analog switch tree changes from N-channel switches to P-channel switches These limitations are automaticaly satisfied in ratiometric systems and can be easily me.t in ground referenced systems. Figure 10 shows a ground referenced system with a separate supply and reference. In this system, the supply must . be trimmed to match the reference voltage. For instance, if a 5.12V reference is used, the supply should be adjusted to the same voltage within o.w. (1) A good example of a ratiometric transducer is a potentiometer used as a position sensor. The position of the wiper is directly proportional to the output voltage which is a ratio of the full-scale voltage across it Since the data is represented as a proportion of full-scale, reference requirements are greatly reduced, eliminating a large source of error and cost for many applications. A major advantage of the ADC0816, ADC0817 is that the input voltage range is equal to the supply range so the transducers can be connected directly across the supply and their outputs connected directly into the multiplexer inputs, (Figure 9). )0411---+---.....1-----11.15 • t--+-----I: DIGITAL OUTPUT PROPORTIONAL TO ANALOG INPUT DOUT Q -~=~ OUT- vREF Vee 4.75V:sVCC· VREF:s5.25V • Rallomelrlo Iransducers , TUH/5277·11 FIGURE 9. Ratlometrlc Conversion System S5-8 .--------------------------------------------------------------------0> c(') Applications Information (Continued) C) The ADC0816 needs less than a milliamp of supply current so developing the supply from the reference is readily accomplished. In F/{Jure 11 a ground references system is shown which generates the supply from the reference. The buffer shown can be an op amp of sufficient drive to supply the millliamp of supply current and the desired bus drive, or if a capacitive bus is driven by the outputs a large capacitor will supply the transient supply current as seen in Rgure 12. The LM301 is overcompensated to insure stability when output capacitor. loaded by the 10 The top and bottom l!ldder voltages cannot exceed Vee and ground, respectively, but they can be symmetrically less than Vee and greater than ground. The center of the ladder voltage should always be near the center of the supply. The sensitivity of the converter can be increased, (i.e., size of the LSB steps decreased) by using a symmetrical reference system. In Rgure 13, a 2.5V reference is symmetrically centered about Vee/2 since the same current flows in identical resistors. This system with a 2.5V reference allows the LSB to be half the size of the LSB in a 5V reference system. ,...F I--------Ivcc t-----tREF(+) DIGITAL OUTPUT REFERENCED TO GROUND Q - ~ OUT- vREF 4.75V:sVCC=VREF:s5.25V ADCOIIS. n TLJH/5277·12 FIGURE 10. Ground Referenced Conversion System Using Trimmed Supply >--4II---tVcc DIGITAL OUTPUT REFERENCED TO GROUND Q - ~ OUT- VREF 4.75V:sVCC=VREF:SS.25V ADeDltS, n TlJH/5277·13 FIGURE 11. Ground Referenced Conversion System with Reference Generetlng Vee Supply S5-9 ..... CD ;;c (') g ..... ...... .... .... I Applications Information (Continued) IO-1&VDe .... . It I I.,F RI LM32I1 > -1~""-.REF(+) TLlH/52n-14 FIGURE 12. Typical Reference and Supply Circuit 5V .RA _y,,.,,....--1 vce r-_ _...._ _...._ _-4_ _. ._ _...::3..:.:1&~V REF(+) ,........--+--+------11.15 • ....+------1.• • • DOUT DIGITAL OUTPUT 'iiOPORTIONAL TO ANALOG INPUT 1.25V,; VIN S 3.7SV 1----tlnD L..,;_ _. . ._ ........._ _~...-_. ._ _...;;1.;;25~V REFH UV RI REfERENCE RA~RB '-y,,.,,.. .--1 GND • Rallomelrlc Iraneduc... TLlH/52n-1S FIGURE 13. Symmetrically C4tntered Reference 3.0 CONVERTER EQUATIONS The transition between adjacent codes N and N given by: VIN= { (VREF(+)-VREF(-Jl[2:S + 5:2] ±V~E} +VREF(-) + The output code N for an arbitrary input are the integers within the range: 1 Is N VIN-VREFI-l X256±AbsoluteAccuracy VREF(+)-VREF(-) where: VIN = Voitage at comparator input (2) The center of an output code N Is given by: VIN= {(VREF(+)-VREF(-)l[~s] ±VruE] +VREF(-) = VREF Voltage at Ref(+) VREF = Voltage at Ref(-) VTUE = Total unadjusted error voltage (typically (3) VRER+) +~12) S 5-10 (4) l> C Applications Information (Continued) (") If no filter capacitors are used at the analog or comparator inputs and the signal source impedances are low, the comparator input current should not introduce converter errors, as the transient created by the capacitance discharge will die out before the comparator output is strobed. If input filter capacitors are desired for noise reduction and Signal conditioning they will tend to average out the dynamic comparator input current. It will then take on the characteristics of a DC bias current whose effect can be predicted conventionally. See AN-258 for further discussion. 4.0 ANALOG COMPARATOR INPUTS The dynamic comparator input current is caused by the periodic switching of on-chip stray capacitances These are connected altemately to the output of the resistor ladder/switch tree network and to the comparator input as part of the operation of the chopper stabilized comparator. The average value of the comparator input current varies directly with clock frequency and with VIN as shown in Figure6. Typical Application ~ ... '-~)o------------------------~ ADDRESS ~_'---+INTERRUPT ornm (AD4-ADI5J" MSI ADCDBI6 ADCDBI1 LSB COMMON DUT COMPARATDR IN • • • ' ' '] INO VIN' G-SV ANALOG INPUT RANGE TUH/5277-1S • Address latches needed for 8085 and SC/MP interfacing the ACCOSt 6, 17 to a microprocessor Microprocessor Interface Table PROCESSOR 8080 8085 Z-80 SC/MP 6800 READ WRITE MEMA AD AD NRDS VMA->2 eA/W MEMW WR WR NWDS VMAeQ2eR/W INTERRUPT (COMMENT) INTA (Thru AST Circuit) INTA (Thru AST Circuit) INT (Thru RST Circuit, Mode 0) SA (Thru Sense A) IRQA or IRQB (Thru PIA) Ordering Information TEMPERATURE RANGE Error ± % Bit Unadjusted ± 1 Bit Unadjusted Package Outline -4O"Cto +85"C ADC0816CCN -55"Cto + 125"C ADC0816CCJ ADC0816CJ J40A Hermetic DIP J40A Hermetic DIP ADC0817CCN N40A Molded DIP S5-11 ~ .... en ..... l> C (") o co .... ...... ~ 8 ~National ~ ~ Semiconductor ADC0820 8-Bit High Speed ,..,p Compatible A/D Converter with Track/Hold Function General Description Features By using a half-flash conversion technique, the 8-bit ADC0820 CMOS AID offers a 1.5 pos conversion time and dissipates only 75 mW of power. The half-flash technique consists of 32 comparators, a most significant 4-bit ADC and a least significant 4-bit ADC. • • • • • The input to the ADC0820 is tracked and held by the input sampling cirCUitry eliminating the need for an external sample-and-hold for signals moving at less than 100 mVlpos. For ease of interface to microprocessors, the ADC0820 has been designed to appear as a memory location or 110 port without the need for external interfacing logic. • • • Key Specifications • 8 Bits 2.5 pos Max (RD Mode) 1.5 pos Max (WR-RD Mode) • Input signals with slew rate of 100 mVlpos converted without external sample-and-hold to 8 bits 75 mW Max • Low Power ± Yo LSB and ± 1 LSB • Total Unadjusted Error • • • • Resolution • Conversion Time Built-in track-and-hold function No missing codes' No external clocking Single supply-5 Voc Easy interface to all microprocessors, or operates stand-alone Latched TRI-STATEe output Logic inputs and outputs meet both MOS and T2L voltage level speCifications Operates ratiometrically or with any reference value equal to or less than Vee OV to 5V analog input voltage range with single 5V supply No zero or full-scale adjust required Overflow output available for cascading 0.3" standard width 20-pin DIP Connection and Functional Diagrams VRE'(+) 'DFI OFL 4-8IT FLASH ADC (4MSB.) Dual-In-Llne Package DB7 DB6 DB5 DBe V..,(-) \'IN Vee DBO NC OBI m: DB2 DB7 DB3 DB6 Wli/RDY DB5 MODE DBe R1I Cl IlIl VRE'(+) GNO V'EF(-) OUTPUT LATCH AND TRI·STATE BUFFERS 4-8IT DAC V-I(+) OB3 4-8IT FLASH AOC (4 LSB.) DB2 OBI DBO V'EF(-) lHT TOP VIEW TLlH/5501-1 MODE Wli/ROY cs liD TL/H/5501-2 Order Number ADC0820D or ADC0820N See NS Package D20A or N20A FIGURE 1 S5-12 Absolute Maximum Ratings Supply Voltage (Vee> Logic Conlrollnpuls Operating Conditions (NOles 1 & 2) (Noles 1 & 2) 10V Vollage al Other Inpuls and Output Storage Temperalure Range Package Dissipation al TA = 2S·C Lead Temp. (Soldering, 10 seconds) TMIN~TA~TMAX Temperalure Range ADC0820BD, ADC0820CD -0.2VloVee +0.2V -0.2V 10 Vee +0.2V - 65"C to + 1S0·C -SS·C~TA~ 0·C~TA~70"C ADC0820BCN, ADC0820CCN 87SmW 300·C + 12S·C +8S·C -40"C~TA~ ADC0820BCD,ADC0820CCD 4.SVt08V Vee Range . Converter Characteristics The following specifications apply for RD mode (pin 7=0), Vee=SV, VREF( +) = SV, and VREF( -) = GND unless otherwise specified. Boldface limits apply from TUIN to TUAX; all other limils TA=Tj=2S·C. ADC0820BD, ADC0820CD ADC0820BCD, ADC0820CCD Parameter Conditions Typ (Note 6) Resolution Total Unadjusted Error (Note 3) Tested LImit (Note 7) Design LImit (Note 8) ADC0820BCN, ADC0820CCN Typ (Note 6) 8 Tested Limit (Note 7) Design LImit (Note 8) 8 8 ±y. ±y. ±y. ADC0820BD, BCD AOC0820BCN ADC0820CD, CCO AOC0820CCN LImit Units Bits ±1 ±1 LSB LSB LSB LSB Minimum Reference Resistance 2.3 1.25 2.3 1.4 1.25 kG Maximum Reference Resistance 2.3 6 2.3 S.3 6 kG ±1 Maximum VREF( + ) Input Voltage Vee Vee Vee V Minimum VREF( -) Input Voltage GND GNO GND V Minimum VREF( + ) Inpul Voltage VREFl-) VREF(-) VREF(-) V Maximum VREF( -) Input Voltage VREFl+) VREF(+) VREF(+) V Maximum VIN Input Voltage Vec+ 0•1 Vee + 0.1 Vee + 0.1 V Minimum VIN Input Voltage GND-0.1 GND-0.1 GND-0.1 V 3 -3 0.3 -0.3 3 -3 p.A ±% ±% LSB Maximum Analog Input Leakage Current Power Supply Sensitivity CS=Vee VIN=Vee VIN=GND Vee=SV±S% ±1f1a ±% SS-13 ±1f1a p.A DC Electrical Characteristics The following specifications apply for Vee = 5V. unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits T A = TJ = 25"C. ADC0820BD, ADC0820CD ADC0820BCD, ADC0820CCD Parameter CondlUons Typ (Note 6) VIN(l). Logical "1" Vcc=5.25V Input Voltage VIN(O). Logical "0" Vee = 4.75V Input Voltage Tested Umlt (Note 7) Design Umlt (Note 8) ADC0820BCN, ADC0820CCN Typ (Note 6) Tested Limit (Note 7) Design Umlt (Note 8) Umlt Units CS.WR.RO 2.0 2.0 2.0 V Mode 3.5 3.5 3.5 V ~.WR.RD 0.8 0.8 0.8 V Mode 1.5 1.5 1.5 V 1 0.3 170 3 200 /LA /LA /LA -1 /LA IIN(l). Logical "1" Input Current VIN(l) = 5V;~. RO VIN(l)= 5V; WR VIN(1) = 5V; Mode IIN(O). Logical "0" Input Current VIN(O) = OV; CS, RD. WR. Mode VOUT(l). Logical "1" Output Voltage Vee=4.75V.IOUT= -360 /LA; OBO-OB7. OFL. INT Vee = 4.75V. lOUT = -10 p.A; OBO-OB7. OF[. INT 2.4 2.8 ' 2,4 V 4.5 4.6 4.5 V VOUT(O). Logical "0" Output Voltage Vee = 4.75V. lOUT = 1.6 mA; OBO-OB7. OFL. INT. ROY 0.4 0.34 0.4 V lOUT. TRI-STATE Output Current VOUT=5V; OBO-OB7. ROY VOUT=OV; OBO-OB7. ROY 0.1 -0.1 0.1 -0.1 0.3 -0.3 3 -3 -3 /LA /LA ISOURCE. Output Source Current VOUT=OV; OBO-OB7. OF[ INT -12 -9 -6 -4.5 -12 -9 -7.2 -5.3 -6 -4.5 mA mA , ISINK. Output Sink Current VOUT=5V; OBO-OB7. OFL. INT. ROY 14 7 14 8.4 7 mA CS=WR=RO=O 7.5 15 7.5 13 15 mA lee. Supply Current 0.005 0.1 50 1 200 0.005 0.1 50 -0.005 -1 -0.005 3 3 AC Electrical Characteristics The following specifications apply for VCC= 5V. t,= tf= 20 ns, VREF( +)= 5V, VREF( -) = OV and TA ~ 25"C unless otherwise specified. Parameter Conditions leRD, Conversion Time for RO Mode Pin 7 = O. (Figure 2) tACCO. Access TIme (Delay from Failing Edge of RO to Output Valid) Pin 7 = 0, (Figure 2) , tcwR.RD, Conversion TIme for WR-ROMode Pin 7 = Vcc; twA = 600 ns, tRD = 600 ns; (Figures 3a and 3b) twR, Write TIme tRD, Re~d Time I I Min Pin 7 = Vee; (Figures 3a and 3b) Max (Note 4) See Graph Min Pin 7 = Vee; (Figures 3a and 3b) (Note 4) See Graph I tACC1, Access Time (Delay from Falling Edge of RO tei Output Valid) tACC2, Access Time (Delay from Falling Edge of RO to Output Valid) Typ (Note 6) Tested Umlt (Note 7) Design Limit (Note 8) Units ' 1.6 2.5 /Ls leRD+20 leRD+50 ns 1.52 /Ls 600 ns 50 /Ls 600 ns Pin 7 = Vee, tRD tl; (Figure3b) CL=15pF 70 120 ns CL =100pF 90 150 ns S5·14 AC Electrical Characteristics (Continued) The following specifications apply for Vee = 5V, tr=t,= 20 ns, VREF( + ) = 5V, VREF( -) = OV and T A = 25°C unless otherwise specified. Parameter Conditions Tested Limit (Note 7) Typ (Note 6), Design Umlt (Note 8) Units tl, Intemal Comparison Time Pin 7=Vee; (Figures3band 4) CL =50pF 800 1300 ns t1H, toH, TRI-STATE Control (Delay from "Rising Edge of RD to Hi-Z State) RL =1k, CL =10 pF 100 200 ns tjjij'fL, Delay from Rising Edge of WR to Falling Edge of INT Pin 7 = Vee, CL = 50 pF tRO> tl; (Figure 3b) tRO tl) S5-16 Typical Performance Characteristics logic Input Threshold Voltage V8 Supply Voltage ~ 1.7 -55'~STAS l'25'c ~ 1.6 =:co 1.5 !:l;: 1.4 ~- 1.3 :: L ./ ,./ § 1.2 4.5 l / ,/ i ~ 5.0 5.25 5.5 ~ 1\ 2.0 ;a- 1.5 15 1.0 a 0.5 ~ z :l BOO 700 o 90D 2.0 \ ~ 1.5 \ ~ III 1.0 I 0.5 o Vcc l=5V TA=25'C \ 300 40D 'Wtllnl) Accuracy V8 VREF . [VREF=VREF (+ )-VREF (-)1 ~ . \ ~ Vcc=5V VREF=5V TA=25'C tp=500 ns twR=600 n. II: II: \ . 6 r--/---/---i"'-.:-PL...-t I ...~ 1.0 I\. Ip Inl) Output Current VB Temperature t .. Internal Time Delay V8 Temperature 10 2.0 Vec=5V >= ~ z 1.5 co 8 ,.a: ..... II: co 1.0 Ii; ""'- , 1\ 300 400 500 &DO 700 BOO 900 :E .... ..~ 0.5 ~ VCC=5V VREF=5V TA=25'C IwR=600 ns , (8D=600n• o w ,.co~ ~ 0.5 z T VREF (V) 1.5 500 600 700 BOO gOO IRD In.) :E o ! _ f - 2.0 i"' r.l i'. Accuracy V8 tp Accuracy V8lAD Vec=5V VREf=5V TA=25'C . tp=5ODns IRD =600 nl 600 1-"""',---+--+-+--1 5'----'_-'-_........_"'---' -100 -so 50 100 ISO TA-AMBIENT TEMPERATURE ('C) 1 '--~~-'--~-~~ -100 -50 0 50 100 ISO TA-AMBIENT TEMPERATURE I'C) Accuracy V8 tWR 500 10 ~ 2.0 400 r-~--'---r-~--~ ,.8: V" 4.75 11 IB ,/ Vee-SUPPLY VOLTAGE IV) o Power Supply Current V8 Temperature (not Including reference ladder) Conversion Time (RD Mode) V8 Temperature 3r--.----r---.---r--, 0 100 150 -100 -SO 0 50 TA-AMBIENT TEMPERATURE I'C) ., LSB= VREF 256 85-17 0 100 150 50 -100 -50 TA-AMBIENT TEMPERATURE I'C) TUH/5501-11 • Description of Pin Functions Pin Name 1 2 3 4 5 6 VIN DBO DB1 DB2 DB3 WR/RDY 7 Mode 8 RD Pin Name Function Analog Input; range ~GND:S:VIN:S:VCC TRI-STATE data output-bitO (LSB) TRI-STATE data output-bit 1 TRI-STATE data output-bit 2 TRI-STATE data output-bit 3 WR-RD Mode . WJI: With c:5 low, the conversion is started on the falling edge of WR. Approximately 800 ns (the preset internal time out, tl) after the WR rising edge, the result of the conversion will be strobed into the output latch, provided that RD does not occur prior to this time out (see Figures 38 and 3b). AD Mode RDY: This is an open drain output (no internal pull-up device). RDY will go low af- . ter the falling edge of c:5; RDY will go TRI-STATE when the result of the conversion is strobed into the output latch. It is used to simplify the interface to a microprocessor system (see F/{/ure 2). Mode: Mode selection input-it is Internally tied to GND through a 50 p.A current source. RD Mode: When mode is low WR-RD Mode: When mode is high WR-RD Mode With ~ low, the TRI-STATE data outputs (DBO-DB7) will be activated when RD goes low (see Figure 4). RD can also be used to increase the speed of the converter by reading data prior to the preset internal time out (tl, - 800 ns). If this is done, the data result transferred to output latch is latched after the falling edge of the AD (see Figures 3a and 3b). RDMode With c:5 low, the conversion will start with AD going low, also RD will enable the TRI-STATE data outputs at the completion of the cOnversion. RDY going TRISTATE and INT going low indicates the completion of the conversion (see Figure Function 9lJil'f WR-RDMode INT going low indic;ates that the conversion is completed and the data result is in the output latch. INT will go low, - 800 ns (the preset internal time out, tj) after the rising edge of WR (see Figure 3b); or lJil'f will go low after the falling edge of RD, if RD goes low prior to the 800 ns time out (see Figure 38). lJil'f is reset by the rising edge of RD or c:5 (see F/{/ures 38 and 3b). RDMode INT going low indicates that the conversion is completed and the data result is in the output latch. INT is reset by the rising edge of RD or c:5 (see Figure 2). 10 GND" Ground 11 VREF(-) The bottom of resistor ladder, voltage range: GND:S:VAEF(-):S:VAEF(+) (Note 5) 12 VREF(+) The top of resistor ladder, voltage range: VAEF( - ):S:VREF( + ):S:VCC (Note 5) CS must be low in order for the RD or WR 13 c:5 to be recognized by the converter. 14 DB4 TRI-STATE data output-bit 4 15 DB5 TRI-STATE data output-bit 5 TRI-STATE data output-bit 6 16 DB6 TRI-STATE data output-bit 7 (MSB) 17 DB7 18 Overflow output-If the analog input is higher than the VREF( +), OFL will be low at the end of conversion. It can be used to cascade 2 or more devices to have more resolution (9, 10-bit). No connection 19 NC Power supply voltage 20 Vee m 2). 1.0 Functional Description 1.1 GENERAL OPERATION The internal DAC is actually a subsection of t,he MS flash converter. This is accomplished by using the same resistor ladder for "the AID as well as for generating the DAC signal. The DAC output is actually the tap on the resistor ladder which most closely approximates the analog input. In addition, the "sampled-data" comparators used in the ADC0820 provide the ability to compare the magnitudes of several analog signals simultaneously, without using input summing amplifiers. This is especially useful in the LS flash ADC, where the signal to' be converted is an analog difference. The ADC0820 uses two 4-bit flash AID converters to make an 8-bit measurement (Figure 1). Each flash ADC is made up of 15 comparators which compare the unknown input to a reference ladder to get a 4-blt result. To take a full 8-blt reading, one flash conversion is done to provide the 4 most significant data bits (via the MS flash ADC). Driven by the 4 MSBs, an internal DAC recreates an analog approximation of the input voltage. This analog. signal is then subtracted from the input, and the difference voltage is converted by a second 4-bit flash ADC (the LS ADC), providing the 4 least significant bits of the output data word. S5-18 1.0 Functional Description (Continued) 1.2 THE SAMPLED-DATA COMPARATOR Each comparator in the ADC0820 consists of a CMOS inverter with a capacitively coupled input (Figure 5). Analog switches connect the two comparator inputs to the input capacitor (C) and also connect the inverter's input and output. This device in effect now has one differential input pair. A comp-arison requires two cycles, one for zeroing the comparator, and another for making the comparison. In the first cycle, one input switch and the inverter's feedback switch (Figure Sa) are closed. In this interval, C is charged to the connected input (V1) less the inverter's bias voltage (VB, approximately 1.2V). In the second cycle (Agure 5b), these two switches are opened and the other (V2) input's switch is closed. The input capacitor now subtracts its stored voltage from the second input and the difference is amplified by the inverter's open loop gain. The Inverter's input (VB') becomes C VB-(V1-V2)-C+CS and the output will go high or low depending on the sign of VB'-VB· The actual circuitry used in the ADC0820 is a simple but important expansion of the basic comparator described above. By adding a second capacitor and another set of switches to the input (Figure 6), the scheme can be expanded to make dual differential comparisons. In this circuit, the feedback switch and one input switch on each capacitor (Z switches) are closed in the zeroing cycle. A comparison is then made by connecting the second input on each capaci. tor and opening all of the other switches (S switches). The change in voltage at the inverter's input, as a result of the change in charge on each input capacitor, will now depend on both input signal differences. 1.3 ARCHITECTURE In the ADC0820, one bank of 15 comparators is used in . each 4-bit flash AID converter (Figure 7). The MS (most significant) flash ADC also has one additional comparator to detect input overrange. These two sets of comparators operate alternately, with one group in its zeroing cycle while the other is comparing. "-/~L~. Yl--o-"'C}C~ A .--Y -r Va Va T Y2~ CS TUH/5501-13 TL/H/5501-12 • Vo = va .VonC = VI-Va .va'-va • Cs = stray input node capacitor .vo' = = (V2-Vl)-Cc+cs ~ [CV2-CVl) c+cs .vo' is dependent on V2-Vl • Va = inverter input bias voltage FIGURE Sa. Zeroing Phase FIGURE 5b. Compare Phase FIGURE 5. Sampled-Data Comparator Z RLADDER~~ (VI) CI -A S VIN~ Vo = Cl +C2+Cs [Cl(V2-V1)+C2(V4-V3)] (V2) -A Cl + C2+ Cs [AQC1 + AQci!1 Z ANAGND~~ (V3) C2 s 1/2LS8~ (V4) TUH/5501-14 FIGURE 6. ADC0820 Comparator (from MS Flash ADC) S5-19 • ~ B c cc 1.0 Functional Description Detailed Block Diagram (Continued) 48ITMS HillS FlASH CONV 4MSB OAC SWITCHES FWHCONV ~----------------~.------~--------~~--------~. VIM VIIEF( + l VREfI-) --'R.,.I\I\32......~"..;.':.;LSB VOLTAGE R/32 COM' OUTPUT R/16 R/lS R/16 CM OUTPUTS A SWITCH CONTROL LINES OBO-D87 112 lSI VOLTAGE 2-/~ GRGUND!../J! 3 /8 l.-.J REFLADOEIl.!/J! V.. ~ P DACDUT.UT A ..!.../~ .INVW'P MS COMPAIIATORS CM1-CM16 112 lSI . VOlTAGE.!./~ REF / FIGURE 7 85-20 LADOEIl!./W' lS COMPAIIATORS Cll-CLIS Tl/H/5501-15 1.0 Functional Description (Continued) When a typical conversion is started, the WR line is brought low. At this instant the MS comparators go from zeroing to comparison mode (Figure 8). When WR is returned high after at least 600 ns, the output from the first set of comparators (the first flash) is decoded and latched. At this point the two 4-bit converters change modes and the LS (least significant) flash ADC enters its compare cycle. No less than 600 ns later, the RD line may be pulled low to latch the lower 4 data bits and finish the 8-bit conversion. When RD goes low, the flash AIDs change state once again in preparation for the next conversion. WR then RD Mode With the MODE pin tied high, the AID will be set up for the WR-RD mode. Here, a conversion is started with the WR input; however, there are two options for reading the output data which relate to interface timing. If an interrupt driven scheme is desired, the user can wait for INT to go low before reading the conversion result (Figure 8). INT will typically go low 800 ns after WR's rising edge. However, if a shorter conversion time is desired, the processor need not wait for INT and can exercise a read after only 600 ns (Figure A). If this is done, INT will immediately go low and data will appear at the outputs. Figure 8 also outlines how the converter's interface timing relates to its analog Input (VIN). In WR-RD mode, VIN is measured while WR is low. In RD mode, sampling occurs during the first 800 ns of RD. Because of the input connections to the ADC0820's LS and MS comparators, the converter has the ability to sample VIN at one instant (Section 2.4), despite the fact that two separate 4-bit conversions are being done. More specifically, when WR is low the MS flash is in compare mode (connected to VIN), and the LS flash is in zero mode (also connected to VIN). Therefore both flash ADCs sample VIN at the same time. ~ ).-"---I..Q~--JL _______ _ \ ifii 1.4 DIGITAL INTERFACE The ADC0820 has two basic interface modes which are selected by strapping the MODE pin high or low. OBO-087 - - - - - - --c:::>----TL/H/5501-17 FIGURE A. WR-RD Mode (Pin 71s High and tRD< t.) RDMode With the MODE pin grounded, the converter is set to Read mode. In this configuration, a complete conversion is done by pulling RD low until output data appears. An INT line is provided which goes low at the end of the conversion as well as a RDY output which can be used to signal a processor that the converter is busy or can also serve as a system Transfer Acknowledge signal. ifii RD Mode (Pin 7 Is Low) \...._-JI ~~~----------~/ \ "------ 080-087-----------{ -,1 1iII~.... _ _ _ ROY 7 ~-' \_-- --,r }TLlH/5501-18 FIGURE B. WR-RD Mode (Pin 7 Is High and tRD> tl) ~,- _ _ Stand-Alone For stand-alone operation in WR-RD mode, CS and RD can be tied low and a conversion can be started with WR. Data will be valid approximately 800 ns following WR's rising edge. \ ...._..,1 J}-------- 080·087 - - - - - - - - - - - - - - { \ ._ _ WR-RD Mode (Pin 71s High) Stand-Alone Operation TL/H/5501-16 ~LOW When in RD mode, the comparator phases are internally triggered. At the falling edge of RD, the MS flash converter goes from zero to compare mode and the LS ADC's comparators enter their zero cycle. After 800 ns, data from the MS flash is latched and the LS flash ADC enters compare mode. Following another 800 ns, the lower 4 bits are recovered. - - -_ _ _ _ _ _ _ _ __ I!I!LOW - - - - - - - - - - - - - 08D-087 ===)~-_«==J}TLlH/5501-19 S5-21 1.0 Functional Description (Continued) I I, MS COMPARATORS ZERO TO REF£lIENCE LADDER. , LS COMPARATORS FLOAT. , MS COMPARATORS COMPARE YIN TO THEIR RefERENCE LADDER TAl'. THE COMPARATOR OUTPUTS DIGITALLY TRACK II J 1~'>-----800"----,,,ol MS COMPARATOR OUTPUTS ARE LATCHED. THE MS DAC IS SET. THE MS COMPARATOR FLOATS. o LS COMPARATORS COMPARE LSB SECTION OF REFERENCE LADDER. 0 \ YIN·YuoDEll TAP , LS COMPARATORS ZERO TO VIN. THE COMPARATOR'S INPUT CAPACITORS TRACK VIN. \ ' o ~EC~~:re:!~g~:JTS BEREAD. MS COMPARATORS RETUIIH TO ZERO MODE. TLlHl5501-20 Note: MS means most significant LS means least significant FIGURE 8. Operating Sequence (WR-RD Mode) OTHER INTERFACE CONSIDERATIONS In order to maintain conversion accuracy, WR has a maxi· mum width spec of 50 /Ls. When the MS flash ADC's sampled-data comparators (Section 1.2) are in comparison mode (WR is low), the input capacitors (C, Figure 6) must hold their charge. Switch leakage and inverter bias current can cause errors if the comparator is Iefl in this phase for too long. Since the MS flash ADC enters Its zeroing phase at the end of a conversion (Section 1.3), a new conversion cannot be started until this phase is complete. The minimum spec for this time (tp, Figures 2, 3a, 3b. and 4) is 500 ns. 2.0 Analog Considerations 2.1 REFERENCE AND INPUT The two VREF inputs of the ADC0820 are fully differential and define the zero to full-scale input range of the A to D converter. This allows the deSigner to easily vary the span of the analog input since this range will be equivalent to the voltage difference between VIN( + ) and VIN( -). By reducing VREF(VREF=VREF(+)-VREF(-» to less than 5V, the sensitivity of the converter can be increased (i.e., if VREF=2V then 1 LSB=7.8 mV). The input/reference arrangement also facilitates ratiometric operation and in many cases the' chip power supply can be used for transducer power as well as the VREF source. This reference flexibility lets the input span not only be var· ied but also offset from zero. The voltage at VREF(-) sets the input level which produces a digital output of all zeroes. Though V,N is not itself differential, the reference design affords nearly differential-input capability for most measurement applications. Figure 9 shows some of the configurations that are possible. 2.2 INPUT CURRENT Due to the unique conversion techniques employed by the ADC0820, the analog input behaves somewhat differently than in conventional devices. The A/D's sampled-data comparators take varying amounts of input current depending on which cycle the conversion is in. The equivalent input circuit of the ADC0820 is shown in F/{/ure 1Da. When a conversion starts (WFf low, WR-RD mode), all input switches close, connecting VIN to thirty-one 1 pF capacitors. Although the two 4-bit flash circuits are not both in their compare cycle at the same time, VIN still sees all input capacitors at once. This is because the MS flash converter is connected to the input during its compare interval, and the LS flash is connected to the input during Its zeroing phase (Section 1.3). In other words, the LS ADC uses VIN as its zero-phase input The input capacitors must charge to the input voltage through the on resistance of the analog switches (about 5 kG to 10 kG). In addition, about 12 pF of input stray capacitance must also be charged. For large source resistances, the analog input can be modeled as an RC network as shown in Figure 1Ob. As Rs increases, it will take longer for the input capacitance to charge. In RD mode, the Input switches are closed for approximately , 800 ns at the start of the conversion. In WR-RD mode, the time that the switches are closed to allow this charging is the time that WR is low. Since other factors force this time to be at least 600 ns, input time constants of 100 ns can be accommodated without special consideration. Typical total input capacitance values of 45 pF allow Rs to be 1.5 kG without lengthening WR to give VIN more time to settle. S5·22 2.0 Analog Considerations (Continued) External Referenee 2.5V Full-scale Power Supply as Reference Vuo(+1 VIN V,. I-I V'NI-I 1+1 Input Not Referred to GND IN+ Uk Uk 5V -.IoI\ftr-........... 5V-"V'Y\O-......-I 5V LM385-2.5 .~ TLlH/5501-21 . ;: TLlH/5501-22 ~ • Currant path must .tlll •• I.t 'rom VIN( -) to ground TL/H/5501-23 FIGURE 9. Analog Input Options rl :n ~ 1 .. V'N-"V'YIIs\O-+-'liT~"J:S"'B--x.-o'· ~ _12PF R.LADDER,5 LSB COMPf.RATDR}~T s V'N 1 pF ~ • R.N RoN Cs 12 PF ~ T ":" o-l ; T TO MSS-X R·LADDER 350 pF : 32 pF T ,~ TL/H/5501-25 1 pF • -= 16 MSB COMPf.RATORS TLlH/5501-24 FIGURE 108 FIGURE10b 2.3 INPUT FILTERING Sampled-data comparators, by nature of their input switching, already accomplish this function to a large degree (Section 1.2). Although the conversion time for the AOC0820 is 1.5 ,""S, the time through which VIN must be 112 LSB stable is much smaller. Since the MS flash AOC uses VIN as its "compare" input and the LS AOC uses VIN as its "zero" input, the AOC0820 only "samples" VIN when WR is low (Sections 1'.3 and 2.2). Even though the two flashes are not done simultaneously, the analog Signal is measured at one instant The value of VIN approximately 100 ns after the rising edge of WR (100 ns due to intemallogic prop delay) will be the measured value. Input Signals with slew rates typically below 100 mVI p.S can be converted without error. However, because of the input time constants, and charge injection through the opened comparator input switches, faster signals may cause errors. Still, the AOC0820's loss in accuracy for a given increase in signal slope is far less than what would be witnessed in a conventional successive approximation device. An SAR type converter with a conversion time as fast as 1 p.S would still not be able to measure a 5V 1 kHz sine wave without the aid of an external sample-and-hold. The AOC0820, with no such help, can typically measure 5V, 7 kHz waveforms. It should be made clear that transients in the analog input signal, caused by charging current flOwing into VIN, will not degrade the AID's performance in most cases. In effect the ADC0820 does not "look" at the input when these transients occur. The comparators' outputs are not latched while WR is low, so at least 600 ns will be provided to charge the Abc's input capaCitance. It is therefore not neeeasary to filter out these transients Ily putting an external cap on the VIN terminal. 2.4 INHERENT SAMPLE·HOLD Another benefit of the A0C0820's input mechanism is its ability to measure a variety of high speed signals without the help of an extemal sample-and.hold. In a conventional SAR type converter, regardless of Its speed, the input' must remain at least Ya LSB stable throughout· the conversion proceas if full accuracy is to be maintained. Consequently, for , many high speed signals, this signal must be externally sampled, and held stationary during the conversion. S5-23 3.0 Typical Applications 8-Blt Resolution ConflguraUon 5V , . - - - -.....-5V.· TUH/5501-26 9-Blt Resolution Configuration eI "eI WI 'WI lllih. . ." ... .... "'~5V v" .Jo--! IIIi 81 ii" 2 DSD MOO. 3 081 VIEFI+) if;5V sv 1=' : 082 14 :~ 15 DB5 .7 D.1,.F -=' VREFI-) 11 ..L 0.1 pi Iii DB6 17 087 .1 m: "m: GHor. -=' 4~ . 1k ... T ~ 1k " eI 'WI Vee -rsv ~. Jo-!Jm , 3 DBD .. 081 5 DB2 14 DB3 15 OS. 16 DBS .0.. ¥RUI+J 1;SV 1"'~ Vml-I 11 17 086 18 : ':" ':" GNB~ TUH/5501-27 Telecom AID Converter 2511 MulUpie Input Channels AN CH' !'Ok -15V-'W_~=::-I 'Ok 3.0 Typical Applications (Continued) 8-Blt 2-Quadrant Analog Multiplier ..n..r ClK 400 kHz XIN tOV TO S~) lSB 2 lM340·5.0lAZ YIN t-10VTO +10V) 7 15 16 16 15 17 14 1B MSB 13 VOUT= -r VoUT=Y lor h:Z 22 pF TUHf5501-30 Fast Infinite Sample-and-Hold 1.2 jJs VIN .., ,.. tOVT05V) U 2 LSa 12 ..1:,::3_ _ _...._ 15V cs 11 T O1PF . aM 10 10 GNO 13 ~-_........--15V 11 VREFt-) ADCOB20 15V lM34o-5.0lAznl-_5.. V_7~ Vee a' 15 OACOBOO 16 ..--.....M--5V 17 1% .....W _ 1.a2k 1.8k ia MSB 5 1.B2k 1% 85·25 TUHf5501-31 ADC0820 w Q Digital Waveform Recorder _ss ATOD COIIYEIIIERS =~ ANALOG DV ':" - T tV :::J~~DE ..,.. CLR1~ lD !l0- CLR2 2A ::J fR CLK~ II ct::"1 DID MODE :'2. OMnlJ393 lA ., ., - I! ATO 0 CONTRDL LOGIC COUNTDS 2KxBRAM. DID 'el .". Sf _DRY :J "0 ~ 'ell :~g: 1III t£i~: 11 t::o=::, 11 , r=c::. ". 087 '=" C/l ~ )0 )0 Cll :(0:) STORED D7 + DVTO -tV ':" '=" IV '=" • t.3M samples/sec .4kmemory ':" TLlHl5501-32 ~ d: I r----------------------------------------------------------------,~ Ordering Information Temperature Range E rror I ±1/2 LSB Unadjusted I ±1 LSB Unadjusted Package Outline O"C to + 70"C -40"Cto +85"C -55"C to + 125"C ADC0820BCN ADC0820BCD ADC0820BD ADC0820CCN ADC0820CCD N20A-Molded DIP D20A-Cavity DIP S5·27 ADC0820CD D20A-Cavity DIP § ~ ~ ! ~National ~ ~ Semiconductor ADC0829 ""p Compatible 8-Bit AID with 11-Channel MUX/Digitallnput General Description Key Specification The ADC0829 is an 8-bit successive approximation AID converter with an 1'1-channel multiplexer of which six can be used as digital inputs, as well as, analog inputs. This AID is designed to operate from the ,...p data bus using a single 5V supply. Channel selection, conversion control, software configuration and bus interface logic are all contained on this monolithic CMOS device. This device contains three 16-bit registers which are accessed via double byte instructions. The control register is a write only register which controls the start of a new conversion, selects the channel to be converted, configures the 8bit 1/0 port as input or output, and provides information for the 8-bit output register. The conversion results register is a read only register which contains the current status and most recent conversion results. The discrete Input register is also a read only register which contains the four address bits of the selected channel, and the six discrete inputs which are connected to the analog multiplexer. • • • • • 8 Bits Resolution Total Unadjusted Error Conversion Time Single Supply Low Power ± 1f2 LSB and ± 1 LSB 256,...S 5Voc 50mW Features • No missing codes • Operates ratiometrically or with analog span adjusted voltage reference • 11-Channel multiplexer with latched control logic of which six can be used as digital inputs • Easy interface to all microprocessors or operates "stand alone" • 0 to 5V analog input range with single 5V supply • T2 LIMOS input/output compatible • No zero or full scale adjusts required • Standard 28-pin DIP • Temperature range -40·C to +85·C Connection and Block Diagrams VtlEF AGND ¥REF ICHll DND Vee 087 CHO DBB CH2 DB5 CH3 DB4 CH4 DB3 CH5 DB2 PO ICH101 DBI P1 (CHIli D8D PZICHBI CHO, 11 CH2-CHll 11 8 EOC ANALOG DATA REGISTER (READ ONLY) P3 (CH91 1/>, CLOCK DIGITAL DATA REGISTER (HEAD ONLY) P4 (CH6) RSI P5 (CH7) Cj B-BIT AID SUCCESSIVE APPROXIMATION FO-P5 REm AO-A3 CONTROL REGISTER (WRITE ONLY) 8 TOP VIEW TLlF/550B-l DBD-DB7 R/W Ordering Information Error ± 1/2 Bit Unadjusted ± 1 Bit Unadjusted Package Outline ADC0829BCN ADC0829CCN N28B BUS CONTROL LODIC cs HSl iIm'f 1/>2 TL/F/550B-2 S5-28 Absolute Maximum Ratings (Notes 1 and 2) Input Current Per Pin Supply Voltage. Vee (Note 3) 6.5V ±5mA Package Voltage +20 rnA Logie Inputs -0.3V to Vee + 0.3V Operating Conditions (Notes 1 and 2) Analog Inpuls -0.3V to Vee + 0.3V Supply Voltage. Vee -65·Cto + 150·C Temperature Range Storage Temperature 4.75 Voe to 5.5 Voc -40·C to + 85·C Package Dissipation at T A = 25·C (Board Mount) 300·C Lead Temp. (Soldering. 10 seconds) Converter and Multiplexer Electrical Characteristics Vee=5Voe=VREF(+). VREF(-)=GND. SCLK >2 = 1.048 MHz. - 40·C :s; T A + 85·C unless otherwise noted. Parameter Total Unadjusted Error; (Note 3) ADC0829BCN ADC0829CCN Conditions Typ Min (Notes) VREF Forced to 5.000 Voe VREF Forced to 5.000 Voe Reference Input Resistance 1.0 Analog Input Voltage Range (Note 4) V( + ) or V( -) VREF( +) Voltage. Top of Ladder Measured at REF( + ) Units ±% ±1 LSB LSB 4.5 kO GND-0.10, VREF( +) + VREF( -)V Ita 2 0 ge. Max Vee+ 0.1O V Vee Vee + 0.01 V Vee/2- 0.1 Vee/2 vee/2+ 0.D1 v -0.1 0 Center of Ladder VREF( -) Voltage. Bottom of Ladder Measured at REF( -) IOFF, Off Channel ON Channel = 5V ADC0829BCN V ±400 nA p.A Leakage Current (Note 6) OFF Channel = OV ADC0829CCN ±1 ION:On Channel ON Channel = OV ADC0829BCN ±400 nA Leakage Current (Note 6) OFF Channel = 5V ADC0829CCN ±1 p.A AC Characteristics Vee=VREF(+)=5V. t,=tf=20 ns and TA=25·C (Note 7) unless otherwise noted. Parameter Conditions Min tcVc(>2). >2 Clock Cycle Time (1/fcl>2) 0.943 PWH(>2l, >2 Clock Pulse Width, High 440 PWd>2). >2 Clock Pulse Width, Low 410 Typ Max Units 10.0 p.s ns ns 1,(>2). >2 Rise Time 25 ns tt 2l. >2 Fall Time 30 ns tAS, Address Set Up Time RS1, R/W.CS tOOR, Data Delay (Read) DBO-DB7 145 ns tosw, Data Delay Setup (Write) DBO-DB7 185 ns tAH. Address Hold Time RS1, R/W.CE 20 ns tOHW. Input Data Hold Time DBO-DB7 20 ns tOHR. Output Data Hold Time DBO-DB7 10 ns Analog Channel Settling Time 32 ' Clocks Ie. Conversion Time 256 Clocks 335 S5-29 ns I II( Digital and DC Characteristics Vee=4.5V to 5.5V and -40°C~TA,S:85°C unless otherwise m;Jted. I Parameter I Conditions Min Bus Control Inputs (R/W. ENABLE RESE'f. RS1. CS") and Peripheral Inputs (PO·P5) I I Typ Max I 2.0 V'N(1). Logical "1" Input Voltage Units V V'N(O). Logical "0" Input Voltage O.B V liN. Input Leakage Current ±1 p.A <1>2 CLOCK INPUT Vee- O.B V'N(1). Logical "1" Input Voltage .V 0.4 V'N(O). Logical "0" Input Voltage V Data Bus (OBO·OB7) 2.0 VIN(1). Logical "1" Input Voltage V VIN(O). Logical "0" Input Voltage VOUT=OV lOUT. TRI·STATEGiI Output Current 0.8 V -10 /LA 10 p.A VOUT=5V VOUT(1). Logical "1" Output Voltage IOUT= -1.6 rnA VOUT(O). Logical "0" Output Voltage IOUT=1.6mA 2.4 V 0.4 V Power Supply Requirements I I I I I lee. Supply Current 10 mA Note 1: Absolute Maximum Ratings are those values beyond which the life of device may be impaired. Note 2: All voltages are measured with respect to ground. Note 3: Total unadjusted error includes offset, fulf.scale,linearily, and multiplexer error. Note 4: For VIN( -);' VIN( +) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog Input. which will forward·conduct for analog input voltages one diode drop below ground or one diode drop greater than Vee supply. Be careful during testing at low Vee levels (4.5V), as high level analog Inputs (5V) can cause this Input diode to conduct, especially at elevated temperatures, and cause errors for analog Inpuls near full·scaIe. The spec allows 100 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 100 mV, the output code will be correct. To achieve an absolute 0 Vee to 5 Vee input voltage range will therefore require a minimum supply voltage of 4.90 Vee over temperature variations, initial tolerance and loading. Note 5: Typlcals are at 25"C and represent most likely parametric norm. Note 8: Off channel leakage current is measured after the channel'selection. Note 7: The temperature coefficient Is 0.3%I'C. Timing Diagram ., r ....10tI I: PlVLI..1 CI. RSt Vee- D.BY Vee- D.BV ... ~ ~ ~ - I I I.., PlYJt(OtI D.4V MV ~ Z.OV U I.IV 8.1 ~""I ut I:1'U WRITE ,. - ,-1A. -1~0tI lA, DIO-DB7 fA-\- - t2.4~~ -1-1.4 u[:=:F- R~~ V.I S5·30 D.I TL/F/550B-3 2.0 STATE DESCRIPTIONS There are three internal states within the A/D converter: the NO OP state; the sample state; and the converting state. The NO OP state is a stable state since the external stimulus (e.g. start conversion signal) is needed for a state transition. The first transient state is sampling the input. The first 32 clocks of the conversion are used for acquiring the channel; this settling time allows any transients to decay before conversion begins. The second transient state is the actual conversion. The conversion is completed in 256 clocks and the conversion results register is updated. The converter then returns to the stable NO OP state awaiting further instructions. The device has no comparator bias current and draws minimal power during the NO OP state. Pin Description ANALOG AND DIGITAL INPUTS CHO, CH2-CH5-These are dedicated analog inputs. They are fed directly to the internal 12 to 1 multiplexer which feeds the AID converter. PO-P5/CH6-CH11-These 6 pins are dual purpose and may be used as either TTL compatible digital inputs, or analog inputs. When used as digital inputs they may be read via the discrete input register. When they are used as analog inputs they function like CH-O, CH2-5. MICROPROCESSOR INTERFACE SIGNALS DBO-DB7-The bi-directional data lines for the data bus connect to the /LP'S main data bus to enable data transfer to and from the /LP. DBO-DB7 remain in a high impedance state unless the ADC0829 is read. >2 Clock-This signal is used for two purposes. First it synchronizes data transfer in and out of the ADC. Second, it is the master clock for the AID converter logic and all other timing Signals are derived from it. 3.0 INITIALIZATION The device is initialized by an active I~w on RESET. All outputs are initialized to the inactive state and the converter placed in its NO OP state. The data register is not affected by RESET. System TRI-STATE outputs are initialized to the high impedance state. R/iN-The read/write pin controls the direction of data transfer on 00-07. RESET-A low on this pin forces the ADC0829 into a known state. The start bit is cleared, Channel CHO is'selected and the internal byte counter is reset to the MS Byte. The AID data register Is not reset. Reset must be held low for at least 3 clocks. Cs-Ghip Select must be low in order for data transfer between the ADC0829 and the /LP to occur.. RS1-The Register Select pin is used to address the internal registers. 4.0 CONVERSION CONTROL The program normally initiates a conversion cycle with a double write command. (See control word format.) The control word selects a channel, configures the peripheral I/O, and provides peripheral data information. The conversion is initiated by setting the SC bit in the control word high. The converter then resets the start conversion bit and be. gins the conversion cycle, When the conversion is complete and the new conversion results transferred to the data register, the status bit is set. The status bit is not reset when the conversion status is read. A full double byte write into the control word will reset the status bit, or a low level at master RESET. If a new conversion command occurs during a conversion, the conversion is aborted and a new channel acquisition phase will immediately beg!n. POWER SUPPLY PINS Vee-This is the positive 5V supply pin. It powers the digital load and the sample data comparator. Care should be exercised to ensure that supply noise on this pin is adequately filtered, by using a bypass capaCitor from Vee to DGND. DGNo-:--Digital ground should be connected to the systems digital ground. VREF and AGNo-The positive reference pin attaches to the top of the 256R resistor ladder and sets the full scale conversion voltage value. The AGND connects to the bottom of the ladder. The conversion result is ratiometric to VREF - AGND and hence both VREF and AGND should be noise free. Ideally the VREF and AGND should ·be single point connected to the. analog transducer's supply. The VREF and AGND voltages typically are 5V and Ground but they may be varied so long as (VREF-AGND)/2= Vee/2 ±0.1V. 5.0 CONTROL STRUCTURE The control logic continually monitors the control bus waiting for CS to go low and >2 to go high. When this condition occurs, the internal decoder, which has already selected the proper function, activitates. The byte counter will always select the most significant (MS) half first, and the least significant (LS) half second. Single byte instructions' will always access the MSB portion of any word. After a single byte instruction the byte counter will return to the MSB portion of a word when CS is high for a full clock cycle. A 16-bit read or write is accomplished by using a 16-bit load or store instruction which transfers each byte on consecutive clock cycles. This timing is shown in Figure 1. A single byte instruction is especially useful for reading the status bit during a polled interrupt. Figure 2 shows the basic A/D conversion timing sequence and flow. Functional Description 1.0 CONTROL LOGIC The Control Logic interprets the microprocessor control signals and decodes these signals to perform the actual functions of selecting, reading, writing, enabling the outputs, etc. S5-31 I Functional Description (Continued) . TIming for a Typlcel ".p 16 Byte Acceu c Timing for a Typical ".p 8 Byte Acceu TlIF/5508-4 FIGURE 1 --.. ."' ........ ~~ ____________WD_~ ___ ~ ___~ ______________--JX~____ "__IW_._Ma______ ms-@IETSCWUDA1 @UIA._ CD.uw.oa 1ftIUT'1mUIII1WE AlLOWIIIITERfIAL IIUU'IPlEXEII TIl IELEICT Aac.Ef. AND mRmt-,,,ule1ll). (JIAID ............ t-... C\DCIII (D..............R... .... @)EOCII1'READ"A1COIlVEllllDll1:WJllElE. NDDlUAREUIIJEII!lEAD.IFEOI: .,. TtlEIlIEW.uD1MIl. fiGURE 2. AID Conversion Timing Sequence 55·32 Tl/F/5508-5 • 7.0 ANALOG TO DIGITAL CONVERTER The ADC0829 AID Converter is composed of three major sections: the successive approximation register (SAR); the 256R ladder and analog decoder; and the sample-data comparator. Functional Description (Continued) 6.0 WORD FORMAT 6.1 Control Register Word Format <- MSB Word..... <- LSB WORD ..... 117 DBe DBs DB4 DB, DB2 OBI DBo 0117 DBe DBs DB4 DB, DB2 OBi 0 X: SC: CH3-CHO: Hex Value o 1 2-5 6·9 A-F 7.1 Successive Approximation The analog signal at the AID input is compared eight times to various ladder voltages to determine which of the 256 voltages in the ladder most closely approximates the input voltage. This stochastic technique is accomplished by converging on the proper tap in the ladder by simple iterative convergence. There are nine posting registers in the SAR which contain the position of the bit being tested and eight latching registers which remember if the comparison was high or low. Starting with the MSB and continuing downward each bit is set high by the posting register. The analog tree decoder selects the corresponding tap in the ladder and the AID input is compared to that voltage. If the comparison is positive the latch remains set, so higher voltages in the ladder are checked next. If the comparison is negative the bit is reset so lower ladder voltages are sought. After all eight comparisons are made, the cOlJtents of the latching register are transferred to a data register, thus the AID can perform a new conversion while the previous results remain available. Don't Care Start Conversion 1 = Start new conversion o = Do not start new conversion Channel Address Definition SelectCHO Select Vrs!( + ) Select Channels CH2-CH5 Undefined Select CH7-CH10 6.2 Conversion Results Register Word Format S: 7.2 256R Ladder The ladder is a very accurate voltage divider which divides the reference voltage into 256 equal steps. Special consideration was given to the ladder terminations at each end, and also the center, to ensure consistent and accurate voltage steps. The use of a 256R ladder guarantees monotonicity since only a single voltage gradient across the ladder exists. Shorted or unequal resistors in the ladder may cause non-uniform steps but cannot cause a nonmonotonic response so often fatal in closed loop system applications. (See Agure 3.) Status 1 = Data is valid (conversion complete) o = Data is not valid 8 bit converted result 6.3 Discrete Input Word Format <- MSB Word ..... <- LSB WORD ..... B7 DBe DBs DB4 DB3 DB2 OBI DBo 0117 DBe DBs DB4 DB, DB2 OBI 0 CH3-CHO: P5-PO: CONTROLS FROM 5.A.R. I Status of channel address Status of P5-PO interpreted as discrete digital inputs l'hR R R ADU ADDRESS SELECTION CSO· R/W RSI Description 1 0 0 0 0 X X 0 0 1 1 0 Do not respond Write NOOP Write Control Word Read Conversion Results Read Discrete Inputs 1 0 1 \ R TO COMPARATOR fNPUT R 'hR Note: All words are transferred as two 8-bH bytes, MSB transferred first LSB transferred seoond. TL/F/5508-6 FIGURE 3. Resistor Ladder and Switch Tree S5-33 the drift signal is a dc component blocked by the ac amplifier. Functional Description (Continued) Actually of the 256 resistors in the 'Iadder, 254 have the same value while the end point resistors/are equal to 11/2R and 1/2R. This ensures the system output characteristic is symmetrical with the zero and full scale points of its input to output, or transfer curve. The comparator has very high input impedance to dc voltages since it looks like a capacitor. Because the comparator is chopping the dc voltages at the input, the difference between the AID input voltage and ladder voltage appears on .the comparator's input capaCitor. The input voltage difference, chopping frequency, and comparator input capacitor causes a CVF current. The CVF current is a small bias current which will not produce any error when the AID input is connected to a low impedance voltage source. If the voltage source has an output impedance of less than 10k, the error is still insignificant since the bias current exponentially decays. The tree decoder routes the 256 voltages from the ladder to a single point at the comparator input. This allows comparIsons between the AID input and any voltage the SAR directa the decoder to route to the comparator. Since the ladder is dependent upon only the matching of resistors, the voltages it generates are very stable with temperature and have excellent repeatability and long term drift. Adding a capacitor to the input of the comparator integrates the. exponential charging current converting it into dc bias current. (See Figure 1.) Two main considerations on the integration capaCitor are charge sharing with a filter capaCitor and settling time. 8.0 MULTIPLEXER 8.1 Analog Inputs The analog multiplexer'selecta one of 11 channels and directa them to the input of the AID converter. The multiplex~r was designed to minimize the effects of leakage currents " and multiplexer output capaCitance. 9.0 BUS INTERFACE The ADC0829 communicates to the microprocessor through an 8-bit I/O port. The 1/0 port is composed of a TTL to CMOS buffer and a TRI-STATEe output driver. Special input protection is used to prevent damage from static voltages or voltages exceeding the specified range from -0.3V to Vee+0.3V. However, normal precautions are recommended to avoid such situations whenever possible. The TTL to CMOS Buffer translates the TTL voltage levels into CMOS levels very rapidly and is quite stable with supply and temperature. The buffer has a small amount of" hysteresis (about 100 mV) to improve both noise immunity ana internal rise and fall times. 8.2 Dlgltallnputa SIx of the analog inputs can also be. used as digital inputs to sense TTL voltage levels. Care must be taken when these The TRI-STATE bus driver is a bipolar and N-channel pair that easily drive the bus capaCitance. Since the bus drivers collectively can sink or source a quarter of an amp total, a non-overlap circuit is used which guarantees that only one of the two drive transistors is on at a time. inputs are interpreted since TTL levels may not always be present. B,3 AID Comparator Since this output drives the bus capacitance, even the nonoverlapping circuit cannot prevent noise on Vee. The amount of noise depends on the Vee current used to charge the bus capacitance. Probably the most important section of the AID converter is the comparator since the comparator's offset voltage and stability determine the' converter's ultimate accuracy. The low voltage offset of the chopper-stabilized comparator of this converter optimizes performance by minimizing temperature dependent input offset errors as well as drift. The external filter capaCitor on Vee provides some of the transient current while the bus is baing driven. A capacitor with good ac characteristics and low series resistance is a good choice to prevent Vee transients from affecting accuracy. The dc signal appearing at the amplifier input is converted to an ac signal, amplified by an ac amplifier and restored to a dc signal. The drift of the comparator is minimized since Application Information Recommended Supply Vee SUPPlY UHEST& OT... OlEYl"" I-------,-~.. D TLlF/5508-7 Mumplaxer lIoN VB VIN Comparator liN VB VIN (VCC~VREF~5V, '.-1.048 MHz) (VCC~VREF~5V). 2.5 r--"T-'"T""-.---r--, 450 t--t--t---i-+---l 300 2.0 ~ i 1'· ~-150 _jll!f=--+-+---i~-4 OL-~ 0.0 1.0 __ ~~ 2.0 __ 3.0 Vui (V) ,/ ,r -300 ~~ 4.0 ......, 5 O I-"*+.iF-.3I!oO;:::-,........ 0.5 AI' ~ 150 1.5 1---+~~;o;;::f3\(M--I -450 5.0 o 1.25 2.50 Vi" (~) TLlF/5508-8 S5-34 3.75 5.0 TLlF/5508-9 ~ Data Bus Test Circuit c Typical Application 0 Q CD I\) 5V 5.OV CD 080-0B7 OUTPUTS ADDRESS DECllDE A MMD6150 OR EDUIV. AOC0829 R/W R/W MMD7DOO OR EDUIV. 11.7 kIl CI RSI 6BOO AD 4>, ANALOG DR DIGITAL INPUTS 4>, DATA BUS "::' DD-D7 "::' TLlF/5508-10 iiffif DBD-OB7 SYSTEM POWER UP CIRCUITRY nmT ":' 55-35 TLlF/5508-11· = ~ ~ National' .~ ~ Semiconductor CO) co ADC0832, ADC0834 and ADC0838 g ADC0831, (COP431, COP432, COP434 and COP438) = .9:..... . 8-Bit Serial 110 AID Converters with Multiplexer Options __ General Description CO) co ~ The ADC08S1 series are 8-bit successive approximation AID converters with a serial 1/0 and configurable input multiplexers with up to 8 channels. The serial 110 is configured to comply with the NSC MICROWIRETM serial data, exchange standard for easy interface to the COPSTM family of processors, and can 'interface with standard shift registers or "Ps. The 2-, 4- or 8-channel multiplexers are software cOnfigured for single-ended or differential inputs as well as channel assignment. The differential analog voltage input allows increasing the common-mOde rejection and offsetting the analog zero input voltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution. Features • NSC MICROWIRE compatible-direct interface to COPS family procassors • Easy interface to all microprocessors, or operates "stand-alone" • Operates ratiometrically or with 5 Vee voltage reference • No zero or full-scale adjust required • 2-, 4- or 8-channel multiplexer options with address logic • Shunt regulator allows operation with high voltage supplies • OV to 5V input range with single 5V power supply • Remote operation with serial digital data link • T2L1MOS input/output compatible • O.S" standard width, 8-, '14- or 20-pin DIP package Key Specifications • • • • • Resolution Total Unadjusted Error Single Supply Low Power Conversion Time 8 Bits ±Yz LSB and ±1 LSB 5 Voe 15mW S2 "s Typical Application MICROWIRE BIT STREAM COPS CPu 5VDC LM335 Tl/H/5583-1 TRI-S'TATEe ls a registered trademark of National Semiconductor Corp. COf'STII and MICROWIRElM are IrademarI r- C 010 11 -------.:=:::.;:::::::-----------• • • ~ fi 0 18::---~ !!. _ ~c i " o~ _. ., ~ ..... o w Q) Q) -" i!'c . n _ CD _. " CD a. ...... S' 5" ~. .. "C .. d~ i !=i ~ a.-c ~~ ~ -:;- ! ~"S ~ if 8~J ~~ il I!!. CI> ~I =0 m START CONY AND ENABLE TSL OUTPUT BUFFER 16 CLK O-------+---+--+---ll----~ MUX VCC ADDRESS ~ NOTE 1 ~ NOTE 1 .. "'I; iii ~g if ~ .J I''''' ' .... 1 1 .11 ·1 I • 1 -I I' ~ ·1 I -:::IT --f--o START a. ., ·1 1 1__ .- cI4 CD ~ 9CD _I-u , , i , :;- ! '< 8 g CD g .go L2 . R 1 ~ J. EOC R C 87 B& BS TO INTERNAL • CIRCUITRY SAR LOGIC AND LATCH 7V ZENER B4 4 n II • 9-8IT SHIFT REGISTER C es .......IR Fl I _, 14 al-fS.-.-O DO ~ g "S c ii' CQ ~ I~ c.:a N J> C ,.c.:a~ i> c n ~ c.:a CD 8 Single-Ended 8 Pseudo-Differential + + + + + + + + + COM 1-) + ValAs-=- COM 1-) ~ 4 Differential Mixed Mode +1-) 0,1 ~ c.:a -a. -1+) +1-) 2,3 + + 4,5 + 6,7 + + ValAs-=- COMI-) -Ir FIGURE 1. Analog Input Multiplexer Options for the ADC0838 S5-47 TLlH/5583-9 Functional Description (Continued) 4. When the start bit has been shifted into the start location of the MUX register, the input channel has been assigned and a conversion is about to begin. An interval of Y2 clock period (where nothing happens) is automatically inserted to allow the selected MUX channel to settle. The SAR status line goes high at this time to signal that a conversion is now in progress and the 01 line is qisabled (it no longer accepts data). 5. The data out (DO) line now comes out of TRI.sTATE and provides a leading zero for this one clock period of MUX settling time. 6. When the conversion begins, the output of the SAR com· parator, which indicates whether the analo~ input is greater than (high) or less than (low) each succeSSIVe voltage from the intemal resistor ladder, appears at the DO line on each falling edge of the clock. This data is the result of the con· version being shifted out (with the MSB coming first). and can be read by the processor immediately. 7. After 8 clock periods the conversion is completed. The, SAR status line returns low to Indicate this Y2 clock cycle later. 8. If the programmer prefers, the data can be provided in an LSB first format [this makes use of the shift enable (SE) control linel. All 8 bits of thE! result are stored in an output shift register. On devices which do not include the SE con· trol line, the data, LSB first, is automatically shifted out the DO line, after the MSB first data stream. The DO line then goes low and stays low until (';S is returned high. On the ADC0838 the SE line is brought out and if held high, the value of the LSB remains valid on the DO line. When SE is forced low, the data is then clocked out LSB first The ADC0831 is an exception in that its data is only output in MSB first format. 9. All internal registers are cleared when the CS line is high. If another conversion is desired, CS must make a high to low transition followed by address information. ,.....----,f----9- SV The 01 and DO lines can be tied together and controlled througli a bidirectional processor I/O bit with one wire. This is possible because the 01 input is only' "Iooked·at" during the MUX addressing interval while the DO line is still in a high impedance state. All of the logic inputs can be taken to 15V independent of the magnitude of the supply voltage, Vee. 3.0 REFERENCE CONSIDERATIONS The voltage applied to the reference input to these convert· ers defines the voltage span of the analog input (the differ· ence between V'N(MAX) and V'N(M'N) over which the 256 possible output codes apply. The. devices can ~~ used in either ratiometric applications or in systems requlOng abso· lute accuracy. The reference pin must be connected to a voltage source capable of driving the reference input resist· ance of typically 2.4 kO. This pin is the top of a resistor divider string used for the successive approximation conver· sion. In a ratiometric system, the analog Input voltage is propor· tional to the voltage used for the AID reference. This volt· age is typically the system power supply, so the VREF pin can be tied to Vee (done internally on the ADC0832). This technique relaxes the stability requirements of the system reference as the analog input and AID reference move to· gether maintaining the same output code for a given input condition. For absolute accuracy, where the analog"input varies be· tween very specific voltage limits, the reference pin can ,be biased with a time and temperature stable voltage source. The LM385 and LM336 reference diodes are good low cur· rent devices to use with these converters. The maximum value of the reference is limited to the Vee supply voltage. The minimum value, however, can be quite small (see Typical Performance Characteristics) to allow di· rect conversions of transducer outputs providing less than a 5V output span. Particular care must be taken with regard to noise pickup, circuit layout and system error voltage sou~c. es when operating with a reduced span due to the In· creased sensitivity of the converter (1 LSB equals VREF' 256). ~------------~T~----~r~ Vee Vee Z1lk TRANSDUCER E4-- + ADCDB34 VREF r- I-_D;.;V.....'.-.2.-SV_-t + AUCDB32 VREF t--- 1.25V r- GND GND .1 TL/H/S583-10 a) Ratlometrlc b) Absolute with a Reduced Span FIGURE 2. Reference Examples S5-48 Functional Description (Continued) 5.2 Full-Scale 4.0 THE ANALOG INPUTS The most important feature of these converters is that they can be located right at the analog signal source and through just a few wires can communicate with a controlling processor with a highly noise immune serial bit stream. This in itself greatly minimizes circuitry to maintain analog signal accuracy which otherwise is most susceptible to noise pickup. However, a few words are in order with regard to the analog inputs should the input be noisy to begin with or possibly riding on a large common-made valtage. The full-scale adjustment can be made by applying a differential input valtage which is 1 Y2 LSB dawn fram the desired analag full-scale valtage range and then adjusting the magnitude af the, VREF input or Vee for a digital autput cade which is just changing fram 1111 1110 to 1111 1111. 5.3 Adjusting for an Arbitrary Analog Input Voltage Rang!, If the analag zero. valtage of the AID is shifted away fram graund (far example, to. accammadate an analag input signal which daes nat go to. graund), this new zero reference should be properly adjusted first. A VIN (+) valtage which equals this desired zero. reference plus Y2 LSB (where the LSB is calculated far the desired analag span, 1 LSB = analog span/256) is applied to. selected" + .. input and the zero. reference valtage at the corresponding .. -" input shauld then be adjusted to. just abtain the OOHEX to. 01 HEX cade transition. The full-scale adjustment shauld be made [with the praper VIN(-) valtage applied] by forcing a voltage to the VIN(+) input which is given by: The differential input ,af these canverters actually reduces the effects of cornman-made input naise, a signal camman to. bath selected .. + .. and" -" inputs far a canversion (60 Hz is mast typical). The time interval between sampling the .. + .. input and then the" -" input is 1f2 af a clack periad. The change in the cornman-mode voltage during this shart time interval can cause canversian errars. Far a sinusaidal cam man-made signal this errar is: 0.5 ) Verror(max)= Vpeak(27TfCM) ( fCLK where fCM is the frequency af the camman-made Signal, Vpeak is its peak valtage value and fCLK, is the AID clack frequency. For a 60 Hz common-mode signal to. generate a % LSB errar (::::: 5 mY) with the canverter running at 250 kHz, its peak value wauld have to. be 6.63V which wauld be larger than allowed as it exceeds the maximum analag input limits. Due to. the sampling nature af the analag inputs shart spikes af current enter the" +" input and exit the" -" input at the clack edges during the actual canversian. These currents decay rapidly and do. nat cause errars as the internal camparator is strabed at the end af a clack periad. Bypass capacitars at the inputs will average these currents and cause an effective DC current to. flaw thraugh the output resistance af the analog signal source. Bypass capacitors shauld nat be used if the saurce resistance is greater than 1 kO. This source resistance limitation is important with regard to the DC leakage currents af input multiplexer as well. The warst-case leakage current af ± 1 /LA aver temperature will create a 1 mV input errar with a 1 kO saurce resistance. An ap amp RC active law pass filter can pravide bath impedance buffering and naise filtering shauld a high impedance Signal saurce be required. V IN (+) fs adj· = V MAX -1.5 [ (VMAX-VMIN) ] 256 where: VMAX = the high end af the analag input range and VMIN = the law end (the affset zero.) of the analag range. (Both are graund referenced.) The VREF (or Vcc) voltage is then adjusted to provide a cade change fram FEHEX to. FFHEX. This campletes the adjustment pracedure. 6.0 POWER SUPPLY A unique feature af the ADC0838 and ADC0834 is the inclusion af a zener diade cannected fram the V+ terminal to. graund which also connects to the Vcc terminal (which is the actual canverter supply) thraugh a silican diade, as shawn in Figure 3. (See Nate 3) R Vs V+ ..... ...-, 5.0 OPTIONAL ADJUSTMENTS Vee ACTUAL CONVERTER SUPPLY 5.1 Zero Error The zero. af the AID daes nat require adjustment. If the minimum analag input valtage value, VIN(MIN), is nat graund, a zero. affset can be dane. The canverter can be made to autput 0000 0000 digital code for this minimum input voltage by biasing any VIN (-) input at this VIN(MIN) value. This utilizes the differential made aperatian af the AID. The zero. errar af the AID converter relates to the lacatian af the first riser af the transfer functian and can be measured by grounding the VIN( -) input and applying a small magnitude pasitive valtage to the VIN( + ) input. Zero errar is the difference between the actual DC input valtage which is necessary to. just cause an autput digital cade transitian fram 0000 0000 to. 0000 0001 and the ideal Y2 LSB value (Y2 LSB=9.8 mV far VREF=5.000 Vocl. '.4 ~7V GNO TL/H/5583-11 FIGURE 3. An On-Chip Shunt Regulator Diode 55-49 Functional Description (Continued) to be derived from the clock. The low current requirements of the AID and the relatively high clock frequencies used This zener is Intended for use as a shunt voltage, regulator to eliminate the need for any additional regulating components. This is most desirable If the converter is to be remotely located from the system power sOUrce. Figurss 4 and 5 illustrate two useful applications Of this on-board zener when an extemal transistor can be afforded. An imporlant use of the interconn8cting diode between V+ and Vee is shown in F/{/1Jf6S 6 and 7. Here, this diode Is used as a rectifier to allow the Vee supply for the converter (typically in the range of 10k-400 kHz) allows using the small value filter capacitor shown to keep the ripple on the Vee line to well under !4 of an lSB. The shunt zener regula.tor can also be used in this mode. This requires a clock voltage swing which Is In excess of Vz. A current limit for the zener is needed, either built into the clock generator or a rasistor can be used from the elK pin to the V+ pin. Applications 12V r---+- SYSTEM SUI'PlY 12V 1k SYSTEM - W I r -....- - \ : SUPPLY 1.6k y. 1V '.4 CMOS OR NMOS CIRCUITS ANALOG CIRCUITS BND FIGURE 4. Operating with a Temperature Compenaatecl Reference . FIGURE 5. Ullng the AID as the Syetem Supply Regulator V' ~~~----IM----~--.+-~ .'0'"" .......-- -....- ... TIWISDUCER ~""-- .....--------~VIN(·I VR·Ef LM33& t-....----+-< 120k Operating with Ratiometric Transducers Vee (5 voel 20. VXOR t-=+---4VIN('1 Vee 1. ZERO AOJ 3k AIlC1J831 10k VREf I-:-~-t-C 0.7 Vee ""-1--"7' ..... lk fS AOJ 24k TLlH/5583-15 • VIN{-)=O.15 Vee 15% of Vee~VXDR~85% of Vee 85-53 Applications (Continued) Span Adjust: OV:S:VIN:S:3V Vee (SvDe) veet-~'"'""------'" r--C>---1 VIII» + ~IOPF ADC8131 Ul331 Zero-Shlft and Span Adjust 2V:S:VIN:S:SV Vet (SvDe) VINI» Vee + VIN ~IDPF 1.2l ADtOOI VINH ---- -, I I I VREF I SETBZERO CODE VOLTAGE Uk Ik 2VOC ZERO ADJ I LM331 33G I _J ":' ":' ":' TLlH/5583-16 55-54 ---------------------------------------------------------------------,~ c Applications (Continued) ~ w .... Obtaining Higher Resolution ~ V"-1~--. .----------~--------------__, VIN + >2.5V i- - ..~g) + 3ft R VIlEF ADC0832 » l -V'N OO=allOsn +V'N<-V'N Tl/H/5583-18 85-55 = 8 Applications (Continued) .. ~ Convert 8 Thermocouples with only One Cold.JunctlonCompensator IREf cw:I ~ .... N cw:I CD • • • • • 8 ~ .Cf) CD ~ • •• •• • • • • 1k Vee • • • • IREI' CHO 2k 910 22k , 10035 oJ T8 1k 3k LM3B5 Uses the,pseudo-differenUal mode to keep the dlfferenllallnputs constant wHh changes In reterence temperature (TREF). 330 Digital Load Cel.l TLlH/5583-19 • • • • Uses one more wire than load cell ItseII Two mlnl·DIPs could be mounted Inside load cell for digital output transducer Electronic offset and gain trims relax mechanical specs for gauge factor and offset Low level cell output is converted immediately lor high noise immunity S5·56 :J> C oCI Applications (Continued) CO W .... 4 mA-20 mA Current Loop Converter );: lOOk lN414B C oCI CO W 100 INP 24k 6.2k 200k r----:VC~e--.., + +IN ~o Vee CI CD4024 CO W A .... ClK g CI ~--1I--+-~-IN CO W CO CSI----~..AtIv"......, ADCOB31 6N139 DPTO COUPLER 10k 5k > , ":' Ved 101 [d INPUT CHANNElS • No additional connecllons • CS derived from extended high on ClK line> 100 /IS n.n.r---I.Il.J" • Timing arranged for 40 kHz, could be changed up or down by component changa • 10'1. ClK frequancy change without component change OK c i& •+ Ve t loo • Vee To. pl' l ,., Applications (Continued) Two Wire l-Channellnter1ace rif- 12V CLK AND C m 2N29117 CS-li~ 10k 110- 18k ~- 47k 18k V 1/2 LM393 li~ lk l00~ ':" II * lOOk ~II"::" 2N2222 lOOk ':" Vee ~ 110 10k lDk ..J ~ ~lN4148 ~ 16k ~ ":" 17k ~ ~l~oF CLK Vee ~ ':" 2110 lOOk eI LM393 ':" DUAL COMFARATOR T T MC0831 + - -560pF ~ ~lN4148 18k Vee ~ t". ~ .. 5.1V "::- .... • Simpler version of fl.channel • CS derived from long eLK pulse ... ~ '"1I1J"l["""' TL/H/5583-22 Ordering Information Total Unadjusted Error Package Temperature Range ±% Hermetic (J) Hermetic (J) Molded (N) -55"Cto + 125'C -4O'Cto +85"C -O'C to + 70'C ADC0831CCJ ADC0831CCN (COP431CN) ±1 Hermetic(J) Molded(N) -40·Cto + 85'C -O'C to + 70'C ADC0832BJ ADC0832BCJ ADC0832BCN (COP432BN) ±% Hermetic (J) Hermetic(J) Molded(N) - 55'C to + 125'C -40'Cto +85'C -O'Cto +70'C ADC0832CCJ ADC0832CCN (COP432CN) ±1 Hermetic(J) Molded(N) -4O'Cto +85'C -O'C to + 70'C ADC08348J ADC08348CJ ADC08348CN (COP434BN) ±% Hermetic(J) Hermetic (J) Molded(N) - 55'C to + 125'C -4O'Cto +85'C -O'Cto +70'C AQC0834CCJ ADC0834CCN (COP434CN) ±1 Hermetic(J) Molded(N) -40'Cto +85'C -O'C to + 70'C ADC08388J ADC0838BCJ ADC08388CN (COP4388N) ±% Hermetic(J) Hermetic(J) Molded(N) -55"Cto + 125'C - 40'C to + 85'C -O'C to + 70'C ±1 Hermetic (J) Molded(N) -40'Cto +85'C -O'C to + 70'C Part Number ADC0831BJ ADC08318CJ ADC08318CN (COP431BN). ADC0838CCJ ADC0838CCN (COP438CN) Analog Input Channels 1 2 4 8 See NS Packages J08A, J14A, J20A, N08E, N14A, N20A 55-59· ~National ~ Semiconductor ADC0833 8-Bit Serial 1/0 AID Converter with 4-Channel Multiplexer General Description Features The ADC0833 series' is an 80blt successive approximation AID converter with a serial 1/0 and configurable input multiplexer with 4 channels. The serial 1/0 is configured to comply with the NSC MICROWIRETM serial data exchange standard for easy Interface to the COPSTM family of processors, as well as with standard shift registers or "Ps. The 4-channel multiplexer is software configured for singleended or differential inputs when channel assigned by a 4bit serial word. The differential analog voltage input allows increasing the common-mode rejection and offsetting, the analog zero input voltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution. • NSC MICROWIRE compatible-direct interface to COPS family processors • Easy interface to all microprocessors, or operates "stand alone" • Works with 2.5V (LM336) voltage reference • No full-scale or zero adjust required • Differential analog voltage Inputs • 4-channel analog multiplexer • Shunt regulator allows operation with high voltage supplies • OV to 5V input range with Single 5V power supply • Remote operation with serial digital data link • T2L1MOS inputloutput compatible. • 0.3" standard width 14-pin DIP package Key Specifications • • • • • Resolution Total Unadjusted Error Single Supply Low Power Conversion Time 8 Bits ± 1f2 LSB and ± 1 LSB 5Voc 25mW 32 "S Connection and Functional Diagrams SARS ADDRESS CS LATCH AND DECODER Dual-In-Llne Package, DI DI ClJ( 00 CH1 SARS CH2 DO CH3 ¥m/2 4·CHANNEL S.E. OR 2.c:HANNEL DIFf. MUIJIPUER AlNO TOPV1EW See NS Packages J14A,N14A V· (SHUNT Vee VREFI2 AGND (5V) REG) TLlH/5607':'1 S5-60 Absolute Maximum Ratings 15mA 6.5V Supply Voltage, Vee (Note 3) Voltage Logie Inputs Analog Inputs Input Current per Pin Storage Temperature Operating Conditions (Notes 1 & 2) (Notes 1 & 2) Current into V + (Note 3) Supply Voltage, Vee Temperature Range ADCOB33BJ, ADCOB33CJ ADCOB33BCJ,ADC~B33CCJ -0.3Vto + 15V -0.3V to Vee + 0.3V ±5mA 4.5 Voe to 6.3 Voe TMIN:;;TA:;;TMAX -55·C:;;TA:;;125·C -40·C:;;TA:;;B5·C 0·C:;;TA:;;70·C ADCOB33BCN, ADCOB33CCf\ -65·Cto + 150·C Package Dissipation at TA = 25·C (Board Mount) Lead Temp. (Soldering, 10 seconds) O.BW : 300·C Electrical Characteristics The following specifications apply for Vee = v+ = 5V, feLK= 250 kHz unless otherwise specified. Boldface limits apply from tMIN to tMAX; all other limits TA = Tj = 25·C. , Parameter Typ (Note 4) Conditions Tested Limit (Note S) Design Limit (Note 6) ±% ±Ya ±1 ±1 ±Ya Limit Units CONVERTER AND MULTIPLEXER CHARACTERISTICS Total Unadjusted Error ADC0833BCN ADC0883BJ, BCJ ADC0833CCN ADC0833CJ, CCJ I VREF/2 Forced to 2.500 Voe ±1 LSB LSB LSB LSB Minimum Total Ladder Resistance (Note 7) ADC0833BCJ/CCJ/BJ/CJ ADC0833BCN/CCN 4.8 4.8 2.2 2.2 2.2 kn kn Maximum Total Ladder Resistance (Note 7) ADC0833BCJ/CCJ/BJ(CJ ADC0833BCN/CCN 4.8 4.8 8.2 8.2 8.2 kn kn GND-O.OS GND-O.05 GND-O.OS V V Vcc+ O•OS Vee + 0.05 Vcc+ O•OS V V ±% ±% ±% LSB LSB 1 1 1 LSB LSB 6.3 6.3 6.3 V V 8.S 8.5 8.5 V V Minimum Common-Mode Input Range (Note 8) ADC0833BCJ/CCJ/BJ/CJ ADC0833BCN/CCN All MUX Inputs and COM Input Maximum Common-Mode Input Range (Note 8) ADC0833BCJ/CCJ/BJ/CJ ADC0833BCN/CCN All MUX Inputs and COM Input DC Common-Mode Error ADC0833BCJ/CCJ/BJ/CJ ADC0833BCN/CCN '±1j,. ±Y16 Change In Zero Error From Vee= 5V To Internal Zener Operation (Note 3) ADC0833BCJ/CCJ/BJ/CJ ADC0833BCN/CCN 15mAlntoV+ Vee = N.C. VREF=5V Vz, Minimum Internal Diode Breakdown (At V + ) (Note 3) ADC0833BCJ/CCJ/BJ/CJ ADC0833BCN/CCN 15mAlntoV+ Vz, Minimum Internal Diode Breakdown (At V + )(Note 3) ADC0833BCJ/CCJ/BJ/CJ ADC0833BCN/CCN 15mAlntoV+ S5-61 Electrical Characteristics (Continued) The following specifications apply for Vee = V+ = 5V. fClK = 250 kHz unless otherwise specified. Boldface limits apply from tMIN to tMAXi all other limits TA = Tj = 25°C. Parameter Conditions Typ (Note 4) Tested LImit (NoteS) Design Limit (NoteS) ±Yts ±Yta ±% ±% ±% LImit Units CONVERTER AND MULTIPLEXER CHARACTERISTICS (Continued) Power Supply Sensitivity Vcc=5V±5% A~0833BCJ/~/BJ/CJ ADC0833BCN/CCN 10FF. Off Channel Leakage Current (Note 9) ADC0833BCJ/CCJ/BJ/CJ LSB LSB On Channel = 5V. Off Channel = OV' -1 ,.A nA ,.A nA -50 -1 ADC0833BCN/CCN -50 On Channel = OV. Off Channel = 5V -1 A~0833BCJ/~/BJ/CJ ,.A 'nA ,.A nA -50 ' -1 ADC0833BCN/CCN -50 ION. On Channei Leakage Current (Note 9) On Channel = 5V, Off Channel = OV -1 ADC083BCJ/~/BJ/CJ ,.A nA ' p.A nA -200 -1 ADC0833BCN/CCN -200 On Channel = OV. Off Channel = 5V -1 ADC083BCJ/CCJ/BJ/CJ ,.A nA -200 -1 , ADC0833BCN/CCN ,.A nA -200 DIGITAL AND DC CHARACTERISTICS VIN(1). Logical "1" Input Voltage ADC0833BCJ/CCJ/BJ/CJ ADC0833BCN/CCN Vee=5.25V VIN(O). Logical "0" Input Voltage ADC0833BCJ/CCJ/BJ/CJ ADC0833BCN/CCN Vee=4.75V IIN(1). Logical "1" Input Current VIN=Vee \ 0.005 0.005 ADC0833BCN/CCN O.B V V 1 p.A p.A 1 1 VIN=OV ADC0833BCJ/~/BJ/CJ -0.005 -0.005 ADC0833BCN/CCN VOUT(1). Logical "1" Output Voltage ADC0833BCJ/CCJ/BJ/CJ ADC0833BCN/CCN ADC0833BCJ/CCJ/BJ/CJ ADC0833BCN/CCN4.54 V V O.B 0.8 ADC0833BCJ/~/BJ/CJ IIN(O). Logical "0" Input Current 2.0 2.0 2.0 -1 -1 ,.A ,.A -1 Vcc= 4.75V 2.4 2.4 4.5 4.5 lOUT = -360,.A 10UT= -10p.A V V V V 2.4 ' 4.5 " S5-62 Electrical Characteristics (Continued) The following specifications apply for Vee = V+ = 5V. fClK = 250 kHz unless otherwise specified. Boldface limits apply from tMIN to 'MAX; all other limits TA = T) = 25"C. Parameter Testsd Umlt (Note 5) De.lgn Umlt (Note 6) 0.4 0.4 0.4 -0.1 -0.1 0.1 0.1 -3 -3 -3 3 3 /LA /LA /LA /LA 14 14 7.5 7.5 7.5 mA mA 16 16, 9.0 9.0 9.0 mA mA 2 2 5 5 5 mA mA 15 15 15 mA mA Typ Condition. (Note 4) Limit Unit. DIGITAL AND DC CHARACTERISnCS (Continued) VOUT(O). Logical "0" Output Voltage IOUT= 1.6mA. VCC=4.75V ADC0833BCJ/~/BJ/CJ ADC0833BCN/CCN V V lOUT. TRI·STATEOutput Current (DO. SARS) ADC0833BCJ/~/BJ/CJ VOUT=0.4V ADC0833BCN/CCN ADC0833BCJ/~/BJ/CJ VOUT=5V ADCo833BCN/CCN ISOURCE ADC0833BCJ/CCJ/BJ/CJ ADC0833BCN/CCN VOUT Short to GND ISINK VOUT Short to Vee ADC0833BCJ/~/BJ/CJ ADC0833BCN/CCN lee. Supply Current (Note 3) ADC0833BCJ/CCJ/BJ/CJ ADC0833BCN/CCN 3 VREF/2 Open Circuit 1+. Current into V+ (Note 3) ADC0833BCJ/CCJ/BJ/CJ ADC0833BCN/CCN , S5-53 AC Characteristics tr=t1=20 ns fCLK. Clock Frequency Tested Typ Conditions Parameter Umlt (Note 4) (Note Min 5) Design Umlt (Note 6) 10 Max kHz 400 " Umlt Units 8 kHz T C. Conversion Time Not including MUX Addressing Time Clock Duty Cycle (Note 10) Min 40 Max 60 % % 250 ns 90 ns tsET-UP. CS Falling Edge or 1/fCLK Data Input Valid to ClK Rising Edge tHOLD. Data Input Valid after ClK Rising Edge tpd1, tpdo-ClK Falling CL=100pF Edge to Output Data Valid Data MSB First E!50 1500 ns (Note 11) Data lSB First 250 600 ns t1 H, T OH-Rising Edge of CS CL =10 pF, RL =10k 125 250 ns to Data Output and SARS (see TRI-5TATI: Test Circuits) Hi-Z CIN, CapaCitance of Logic 5 pF 5 pF Input COUT, Capacitance of logic Outputs Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired, Note 2: All voltages are measured with respect to ground, Note 3: Internal zener. diodes (approx. 7V) are connected from V+ to GND and Vee to GND. The zener at V+ can operate as a shunt regulator and is connected to Vee via a conventional diode. Since the zener voltage equals the AID's breakdown voltage, the diode insures that Vee will be below breakdown when the device is powered from V+. Functionality is therefore guaranteed for V+ operation evan though the resultant voltage at Vee may exceed the specified Absolute Max. of 6.5V. It is recommended thai a resistor be used to lim" the max. current into V+. Note 4: Typicals are at 25'C and represent most likely parametriC norm. Note 5: Guaranteed and 100% production tested. Note 6: Guaranteed, but not 100% production tested. These lim"- are not used to calculate outgoing quality levels. Note 7: See Applications, section 3.0. Note 8: ForVIN(-);"VIN(+)lhe digital output code will be 0000 0000. Two on-ehip diodes are tied to each analog input (see Block Diagram) which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the Vee supply. Be careful, during tesllng at low Vee ievels (4.5V), as high leval analog inputs (5V) can cause Ihis input diode to conduct.....specially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 Vee to 5 Vee input voitage range willthereiore require a minimum supply voltage of 4.950 Voc over temperature variations, initial tolerance and loading. Note 9: Leaksge current Is measured with the clock not switching. Note 10: A 40% to 60% clock duty cycle ,ange Insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits, the minimum time the clock Is high or the minimum time the clock Is low must be at least 1p.s. Nole 11: Since data, MSB first, is the output of the comparator used In the successive approximation loop, an additional delay Is builtin (see Block Diagram) to allow for comperator response time. S5-64 , Timing Diagrams Data Input Timing Data Output Timing ClK ClK~''''dl ,.---.001 DATA OUT (DO) ____ J , I, INDATA (01) TRI-STATE Test Circuits and Waveforms Vce Vee 1--'--"'o()~~~UT ~IH OOANO::: 10k SARSOUTPUTS . ~ GNO------= 1,=20 ns tOH Vec vec 10k cs GNO DATA OUTPUT OOANOvee~h SARSOUTPUTS VOL ':' ~ 1,=20 ns Leakage Current Test Circuit 5V APC0133 CH A (ON CHANNEL) CHANNEL . .----1::: )g~:NNELS L_________ CH 0 VOLTAGE SELEer TUH/5607-2 55·65 ~.----------------------------------------------------------~ ~ Typical Performance Characteristics Effect of Unadjusted Offset Error va VREF/2 Voltage Linearity Error vs VREF Voltage l&rT~Tm~~~~~nm 1.5 14 ~ 1.25 12 ;; 1.0 r - - r-JcC=5J r-t250 kHz) 0.75 t-- I--TA=2S"C- r-- 10 1 ~ o 0.01 !z 0.5 ::1 0.25 o 0.1 1.0 VRu!2(Vocl Linearity Error vs Temperature 0.50 1 VREF/2 tV) 3.0 ~ 2.5 VREF/2 =2.5V Vcc=5V lz5"C ;; 2.0 .. 0.25 I I: I--t--t--+-F'-i VREF/2:2.5V 'cLK=250 kHz ::1 0 -55"C 0.5 O~~--~~~-L~ -100 -50 50 100 10 100 Power Supply .Current vs Temperature 1 V IL 25"C o 150 TEMPERATURE t"C) 1.5 2.5 Linearity Error vs fClK r--.r--.--..,--..---, ~ I o " zoo 30D 400 500 fClK tkHz) 600 Output Current vs Temperature r-r-r-'-T"""''''-''', 25r--v---r--~-'--, 1 ii:l 1.0 E iil I 0.5 1-t-+-++-+-t-1H fCLK=25D kHz CS="I" 0'--......."'-->-.....................-1....... -75 -50 -25 0 25 so 75 100 125 !sINK Voc = 0.4V O'--~--"""'~~~~ -100 -50 0 50' 100 TEMPERATURE t"C) TEMPERATURE t"C) 125 Power Supply Current VB fClK 1 _'-.l 1.5 Vcc=5V @25"C 11.0 r-~--:jr-:;~..."t"'-t"".., E0.5 I--I--+-+--+---I iil I o '--~--.......--~~~ q 100 200 300 fclKtkHz) S5·66 4DO SOD TUH/5607-3 DI » c oo 13 B~---------'-----1~--~~--~~----~--~ Q) Co) Co) ." C :::J 2- START CONY AND ENABLE TSL OUTPUT BUFFER ClK 0' :::J !!. o.!.!. MUX ADDRESS VCC .... - ,.... 3-, r:: _. . . I f""III CHaO CHI 04 I ) ... Tf""IIIlf""lllT I ~ . sp To , Dl 3 ~ ' cl_ ---.,., 1 , iii' CC -li- ~ 1 1 c START'! n U1 • - ;I\' "' ANALOG MUX (EnUIVAlENT! 1 0' () TIME )-+--t en -I m S~yJ , t ":" cs , V tR ~ CO~_ .- n ~ EOC R C .!!! SAR LOGIC AND lATCH 1VZENER Ir----------------, I N F P U T TO INTERNAL 18 E 85 • TO~~~EU~~:~ 13 I ~ ~ .!! !l 9-BlT SHIFT REGISTER c 1 _, CS~IR 10 Fl nl-fS--.ODP 80 CIRCUITS BV ~30V 1 11 18 INPUT PROTECTION - All LOGIC INPUTS ":" TLlH/5607 -4 • &&80:>OV ~ r-----------------------------------------~-------------------------~ ~ 011( Timing Diagram CLDCK (CLKI r~q:··:···::PD!DN~C!AR~E::::::::::JI~DI~D~I~~.~LEmD!UN~TEIL~N2EX[T~CD~NV~E!RSrnID~N!CY~C~LEI:::::::::i:~~~~~~ DAT?J~' ... DDIrT CARE SGLJIIII! SELECT '--_ _ _ _.~IT:..:l---, I--f---- AID CO.JERSlDN IN PRDCESS-------i l ____....:~TiliAI. ~ ~RSTATUS ~r....:M~UX~C~D~NF:'B~UR~A~TI~DN~WO:RDrl-t-.......;------------~i--....;,------_______ ~- ~ STATE SElTLlNB+--I------nME TAl· STATE DATA~~1----TRHTATE----I TLlH/5607-5 acquisition systems is significantly simplified with this type of input flexibility. One converter package can now handle ground referenced inputs and true differential inputs. A particular input configuration is assigned during the MUX addressing sequence, prior to the !!tart of a conversion. The Ml,JX address selects which of the analog inputs are to be enabled and whether this input is single-ended or differential. In the differential case, it also assigns the polarity of the channels. Differential inputs are restricted to adjacent chan· nel pairs. For example channel 0 and channel 1 may be selected as a differential pair. Channel 0 or 1 cannot act differentially with any other channel. In addition to selecting differential mode the sign may also be selected. Channel 0 may be selected as the positive input and channel 1 as the negative input or vice versa. This programmability is best illustrated by the MUX addressing codes shown in the following table. The MUX address is shifted into the converter through the 01 line. Functional Description 1.0 MULTIPLEXER ADDRESSING The design of the ADC0833 utilizes a sample·data compar· ator structure which provides for a differential analog input to be converted by a successive approximation routine. The actual voltage converted is always \he difference between an assigned" + .. input terminal and a "-" input terminal. The polarity of each· input terminal of the pair being converted indicates which line the converter expects to be the most positive. If the assigned "+ .. input is less than the "-" input the converter responds with an all zeros output code. . A unique input multiplexing scheme has been utilized to provide multiple analog channels with software·configurable single·ended (ground referred) or differential inputs. The an· alog signal conditioning required in transducer-based data TABLE I. MUX Addressing Single-Ended MUX Mode Channel # Address SGL/· 0001 DIF SIGN 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 SELECT 0 1 2 3 + + + + COM Is internally ties to a GND Differential MUX Mode Address Channel # SGU 0001 DIF SIGN 1 0 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 SELECT 8·5-68 0 1 + - - + 2 3 + - - + --------------------------------------------------------------------~~ Functional Description c o (Continued) ting highly noise immune digital data back to the host processor. Since the input configuration is under software control, it can be modified, as required, at each conversion. A channel can be treated as a single-ended, ground referenced input for one conversion; then it can be reconfigured as part of a differential channel for another conversion. Figure 1 illustrates the input flexibility which can be achieved. To understand the operation of these converters it is best to refer to the Timing Diagram and Functional Block Diagram and to follow a complete conversion sequence. 1. A conversion is initiated by first pulling the CS (chip se· lect) line low. This line must be held low for the entire conversion. select) line low. This line must be held low for the entire conversion. The converter is now waiting for a start bit and its MUX assignment word. The analog input voltages for each channel can range from 50 mV below ground to 50mV above Vcc(typically 5V) without degrading conversion accuracy. 2.0 THE DIGITAL INTERFACE A most important characteristic of these converters is their 2. A clock is then generated by the processor (if not provided continuously) and output to the AID clock input. serial data link with the contrOlling processor. Using a serial communication format offers two very significant system improvements; it allows more function to be included in the converter package with no increase in package size and it can eliminate the transmission of low level analog signals by locating the converter right at the analog sensor; transmit- 3. On each rising edge of the clock the status of the data in (01) line is clocked into the MUX address shift register. The start bit is the first logic "1" that appears on this line (all leading zeros are ignored). Following the start bit the converter expects the next 4 bits to be the MUX assignment word. 2 Differential 4 Single-Ended o + 1{ 2'3{ 0, Mixed Mode TL/H/5607-6 FIGURE 1. Analog Input Multiplexer Options for the ADC0833 S5-69 ~ Co) Co) ~~------------------------------------------------------ ~ 00 e C Functional Description (Continued) o o co 4.0 THE ANALOG INPUTS The most important feature of these converters ,is that they can be located right at the analog signal source and through just a few wires can communicate with a controlling processor with a highly noise immune serial bit stream. This in itself greatly minimizes circuitry to maintain analog signal accuracy which otherwise is most susceptible to noise' pickup. However, a few words are in order with regard to the analog inputs should the input be noisy to begin with or possibly ridin'! on a large common-mode voltage. is necessary to just cause an output digital code transition from 0000 0000 to 0000 0001 and the ideal V:! LSB value (V:! LSB = 9.8 mV for VREF/2 = 2.500 VOC), 5.2 Full-Scale The full-scale adjustment can be made by applying a differential input voltage which is 1 V:! LSB down from the desired analog full-scale voltage range and then adjusting the magnitude of the VREF input or VCC for a digital output code which is just chimging from 11111110 to 11111111. The differential input of these converters actually reduces the effects of common-mode input noise, a signal common to both selected" + .. and" -" inputs for a conversion (60 Hz is most typical), The time interval between sampling the .. + .. input and then the .. -" input is V:! of a clock period. The change in the common-mode voltage during this shqrt time interval can cause conversion errors. For a sinusoidal common-mode signal this error is: 5.3 Adjusting for an Arbitrary Analog Input Voltage Range If the analog zero voltage of the AID is shifted away from ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference should be properly adjusted first. A VIN( +) voltage which equals this desired zero reference plus V:! LSB (where the LSB is calculated for the desired analog span, 1 LSB = analog span/256) is applied to selected" + .. input and the zero reference voltage at the corresponding .. -" input should then be adjusted to just obtain the OOHEX to 01 HEX code transaction. 0.5 ) Verror(max) = Vpeak(27TfCM) ( -f, ClK where fCM is the frequency of the common-mode signal, VPEAK is its peak voltage value and fClK is the AID clock frequency. For a 60 Hz common-mode signal to generate a % LSB error (=:: 5 mV) with the converter running at 250 kHz, its peak value would have to be 6.63V which would be larger than allowed as it exceeds the maximum analog input limits. Due to the sampling nature of the analog inputs short spikes of current enter the .. + .. input and exit the .. -" input at the %clock edges during the actual conversion. These currents decay rapidly anti do not cause errors as the internal comparator is strobed at the end' of a clock period. Bypa,ss capaCitors at the' inputs will average these currents and cause an effective DC current to flow through the output resistance of the analog signal source. Bypass capacitors should not be used if the SO\lrce resistance is greater than 1 kO. This source resistance limitation is important with regard to the DC leakage currents of input multiplexer as well. The worllt-case leakage current of ± 1 p.A over temperature will create a 1 mV inut error with a 1 kO source resistance. An op amp RC active low pass filter can provide both impedance buffering and noise filtering should a high impedance sigl1al source be, required. The full-scale adjustment should be made [with the proper Vln(-) voltage applied) by forcing a voltage to the VIN(+) input which is given by: V IN (+)fsadl' = V -15 [ (VMAX - VMIN) ] MAX· 256 where: VMAX= the high end of the analog input range and VMIN= the low end (the offset zero) of the analog range. (Both are gro~nd referenced.) The VREF/2 voltage is then adjusted to provide a code change from FEHEX to FFHEX. This completes the adjustment procedure. 6.0 POWER SUPPLY A unique feature of the ADCOB33 is the inclusion of a 7V zener diode connected from the V+ terminal to ground which also connects to the VCC terminal (which is the act!Jal converter supply) through a silicon diode, as shown in Aguf83. 5.0 OPTIONAL ADJUSTMENTS 5.1 Zero Error The zero of the AID does not require adjustment. If the minimum analog input voltage value, VIN(MIN), is not ground, a zero offset can be done. The converter can be made to output 0000 0000 digital code for this minimum input voltage by biasing any VIN (-) input as this VIN(MIN) value. This utilizes the differential mode operatic:1 of the AID. Vs R V+ ...... Vee ACTUAL CONVERTER SUPPLY '.4 ~7V The zero error of the AID converter relates to the location of the first riser of the transfer function and can be measured by grounding the VIN( -) input and applying a small magnitude positive voltage to the VIN( + ) input. Zero error is the difference between the actual DC input voltage Which GND TLlH/5eD7-8 FIGURE 3. An On-Chlp Shunt Regulator Diode S5-71 w w ~ ~ CD i r--------------------------------------------------------------------------------Functional Description (Continued) This zener is intended for use as a shunt voltage regulator to eliminate the need for any additional regulating compo· nents. This is most desirable if the converter is to be remotely located from the system power source. Agures 4 and 5 illustrate two useful applications of this on·board ze· ner when an external transistor can be afforded. An important use of the interconnecting diode between V+ and Vee is shown in Agures 6 and 7. Here, this diode is used as a rectifier to allow the Vee supply for the converter to be derived from the clock. The low current requirements of the AID (- 3 mAl and the relatively high clock frequen· cies used (typically in the range of 10k-400 kHz) allows usirig the small value filter capacitor shown to keep the ripple on the Vee line to well under % of an LSB. The shunt zener regulator can also be used in this mode. This requires a clock voltage swing which Is in excess of 7V. A current limit for the zener is needed, either built into the clock generator or a resistor. can be used from the elK pin to the V+ pin. Applications 12V r - -.....-SYSTEM SUPPLY 1.6k AOC0833 12Y lk SYSTEM -'VII............----\. SUPPLY Y+ Y+ 7Y :;,---....,r__--~.t-+_ Yee 6.4 Vee 6.4 AOC0833 3 mY/'C T O1 . CMOS OR NMOS CIRCUITS ANALOG CIRCUITS GNO FIGURE 4. Operating with a Temperature Compensated Reference FIGURE 5. Using the AID as the System Supply Regulator Y+ .....-t~()-+-- ...t---Ir__...~+ Vee TRANSDUCER 1'10 PF AOC0833 AOC0833 01...-, 00 ~~OUOO 100 kHz CLOCK • S:Jlf 1+......._--< ClK CS 1+----< CS CLOCK GNO ~....- ...IClK GNO GNO TUH/5607-9 F~GURE 6. Generally Vee from the Converter Clock FIGURE 7. Remote Senslng-Clock and Power on 1 Wire S5-72 Applications (Continued) Digital Link and Sample Controlling Software for the Serially Oriented COP420 and the Bit Programmable 1/0 INSS048 CHO CHO • • • ADC0833 • COP420 • ADC0833 INS8048 • CH3 CH3 TL/H/5607-10 COP CODING EXAMPLE Mnemonic LEI SC OGI CLRA AISC1 XAS LDD NOP XAS 8048 CODING EXAMPLE Instruction ENABLES SIO's INPUT AND OUTPUT C=1 GO=O(CS=O) CLEARS ACCUMULATOR LOADS ACCUMULATOR WITH 1 EXCHANGES SIO WITH ACCUMULATOR AND STARTS SK CLOCK LOADS MUX ADDRESS FROM RAM INTO ACCUMULATOR Mnemonic P1, #OF7H ANL MOV B,#5 MOV A, #ADDR LOOP 1: RRC A JC ONE Instruction ;SELECT AID (CS=O) ;BIT COUNTER +- 5 ;A +- MUX ADDRESS ;CY +- ADDRESS BIT ;TESTBIT ;BIT=O ZERO: ANL P1, #OFEH ;DI+-O JMP CONT ;CONTINUE ;BIT=1 ONE: ORL P1, #1 ;DI+-1 CONT: CALL PULSE ;PULSESKO-1- 0 DJNZ B, LOOP 1 ;CONTINUE UNTIL DONE ;EXTRA CLOCK FOR SYNC CALL PULSE ;BIT COUNTER +- 8 . MOV B,#8 ;PULSE SK 0 ~ 1 0 LOOP 2: CALL PULSE IN A,P1 ;CY+-DO RRC A RRC A ;A+-RESULT MOV A,C ;A(O) +- BIT AND SHIFT RLC A ;C+-RESULT MOV C,A DJNZ B,LOOP2 ;CONTINUE UNTIL DONE RETR ;PULSE SUBROUTINE PULSE: ORL P1, #04 ;SK+-1 NOP ;DELAY ANL P1, #OFBH ;SK+-O RET START: LOADS MUX ADDRESS FROM ACCUMULATOR TO SIO REGISTER t 8 INSTRUCTIONS -+ ,J, XAS XIS CLRA RC XAS XIS 001 LEI READS HIGH ORDER NIBBLE (4 BITS) INTO ACCUMULATOR PUTS HIGH ORDER NIBBLE INTO RAM CLEARS ACCUMULATOR C=O READS LOW ORDER NIBBLE INTO ACCUMULATOR AND STOPS SK PUTS LOW ORDER NIBBLE INTO RAM GO=1 (CS=1) DISABLES SIO's INPUT AND OUTPUT S5·73 Applications (Continued) A "Stand-Alone" Hook-Up lor ADC0833 Evaluation MUXADDRESS ;:::::=i::::::;:::::=1::::~--o&VDC -START lIT 5'.14) J J ,£ ,£ 11 12 13 " 14 PARALLEL 'NPUTS .e INPUT SHIFT REGISTER 74e115 DO Vee " SVac &voc ~~-'+-o'VDe OUTPUT SHIFT REGISTER 'J4C'" DA n· " " NSLIiCI21 II) .... LIB IVac DATA DISPLAV Low Cost Remote Temperature Sensor Vee ClVDe' V"I---._+_.. T'OIlF .,.. .l Uk SVac T. ~m V_R_"_"~---I~.,..~a~AX eH' ..V_'._'-_'___ TLlH/5607-11 55-74 Applications (Continued) Digitizing a Current Flow Vee 0.1 _ 'LOAD (2A FULL·SCALE) (5VDe)~--'-~~~~----------~~~----~------~-----------------------' VCC (5VDC) 100 Vec~----------~-------------, CHO JIM + 240k ADC0833 100 ZERO ADJ 2k 9.lk >.....---------1 CHI LM336 lk """".--........ FS ADJ 120k Operating with Automotive Ratlometric Transducers Vee (5VDC) ) ~ 20k XDR vXOR V'N(t) Ik ZERO ADJ E+- vec f V'NH* ~3k + lOIlF 16k ADCD833 ~ ~ ~ 1/2/~ VREf12 0.35 Vec , + flPf +~=~ Ik FS ADJ ...= Uk ~ ·VIN(-)=O.15 Vee 15% of Vee<:VXDR<:85% of Vee TUH/5607-12 55-75 Applications (Continued) Span Adjust: OV s: VIN s: 3V Vee ,svDe' veel-~~------.... .--<>--tV'N'" ADCGl33 0035 Zero-Shift and Span Adjust: 2V s: VIN s: 5V Yee ,SVDC' Vcet--4.....- - - - - - - - . . , + Uk ADCDI33 SETSZERD eoo. VOLTArG."'\I"""....;._.......'II3'113D~_ _ -+-+__-'~-+__+_.J ,. IVDe 1.71 ZEROAOJ Protecting the Input High Accuracy Comp.arators ,I Vee • _ _ _ _ _ _ _ _ _+'5vDe' 'SVDe >-"lN~...._IV'N'+' Vee SYSTEM TEST POINTS AOC0I33 IV Vee : }o., ¥nt' ADC0833 TO CONTROLLER 2 ¥ntl :}2.3 GND DO DO Diodes are lN914 = alils ff + V'N > = aliOs H + V,N < -V'N -V'N .,.. TUH/5607-13 . For additional application Ideas, refer to the data sheet for the ADC0831 family of serial data converters. 55-76 ---------------------------------------------------------------------,~ g Ordering Information ~ Part Number Temperature Range ADC0833BCJ -40"Cto +85'C ADC0833BCN O'Cto +70'C ADC0833BJ - 55'C 10 + 125'C ADC0833CCJ -40'Clo +85'C ADC0833CCN ADC0833CJ O'Clo +70'C -55'Clo + 125'C 55-77 Total Unadjusted Error ±1/2l5B ±1l5B (0) (0) •• ~ c( r-------------------------------------------------------~------------------_. ~National ~·Semiconductor ADC0844 8-Bit ,..,p Compatible AID Converter with 4-Channel Multiplexer General Description • Easy interface to all microprocessors • Operates ratiometrically or with 5 VDC voltage reference • No zero or full-scale adjust required • 4-channel multiplexer with address logic • Internal clock • OV to 5V input range with single 5V power supply • T2L1MOS input/output compatible • 0.3" standard width 20-pin DIP The ADC0844 is a CMOS 8-bit 'successive approximation AID converter with a versatile analog input multiplexer. The 4-channel multiplexer can be software configured for singleended, differential or pseudo-differential modes of operation. The differential mode provides low frequency input common-mode rejection and allows offsetting the analog range of the converter. In addition, the AID's reference can be adjusted enabling the conversion of reduced analog ranges with 8-bit resolution. This AID is designed to operate from the control bus of the NSC800TM and the wide variety of 8080 "p derivatives. TRI-STATE output latches that directly drive the data bus permit this AID to be configured as a memory location or as an 1/0 device to the microprocessor with no interface logic necessary. Key Specifications • • • • • Features 8 Bits Resolution Total Unadjusted Error Single Supply Low Power Conversion Time ± '12 LSB and ± 1 LSB . 5 VDC 10mW 40 "S • Compatible with 8080 "p derivatives-no interface logic needed Block and Connection Diagrams co !! 18 !1 .,.1!:DGND !19 INTERNAl CLOCK CONTRDL LOGIC -1 Da7 DB6 DB5 DBC MA3/DB3 MAl/D8! MAl/DBl MAD/D8D cr-- 9 LADDER AND DECODER DAC DUTI 11 Dual-In-Llne Package VREF ~ 1! 13 14 TRI·STA)'E OUTPUT LATCHES 15 16 1 17 .... '"''--- COMP - 6AR LATCHES + Vee cs Wii CHl INTR CHI DBO/MAD CH3 D811MAl CH4 D821MA! AGND DB3/MA3 VREF 084 (MSB) DB7 DB5 IIllND DB6 TDPVIEW TL/H/5016-2 ~ MUX ADDRESS LATCHES iiii + I ANALOG MUX AND DECDDER fC See Ordering Information r f3 f5 f6 CHl CHI CH3 CH4 AGND S5-78 TL/H/5016-1 Absolute Maximum Ratings Operating Conditions (Notes 1 & 2) (Notes 1 &2) 6.5V Supply Voltage (Vee) Supply Voltage (VeC> Voltage 4.5 Voe to 6.0 Voe Temperature Range -0.3Vto +15V Logic Control Inputs At Other Inputs and Outputs ADC0844BCN. ADC0844CCN ADC0844BCJ. ADC0844CCJ -0.3V to Vee+ 0.3V Storage Temperature ADC0844BJ. ADC0844CJ -65'Cto + 150'C 875mW Package Dissipation at T A = 25'C Lead Temp. (Soldering. 10 seconds) TMIN:5:TA:5:TMAX O'C:S:TA:5:70"C -40'C:S:TA:5:85'C -55'C:5:TA:5:125'C 300'C Electrical Characteristics The following specifications apply for Vee = 5 Voe unless otherwise specified. Boldface limits apply from TMIN to TMAXi all other limits TA = Tj = 25'C. ADC0844BJ, ADC0844BCJ ADC0844CJ, ADC0844CCJ Conditions Parameter Typ (Note 5) Tested Limit (Note 6) Design Limit (Note 7) ADC0844BCN, ADC0844CCN Typ (Note 5) Tested Limit (Note 6) Design Limit (Note 7) ±% ±% ±1 ±1 Limit Units CONVERTER AND MULTIPLEXER CHARACTERISTICS Maximum Total Unadjusted Error ADC0844BCN ADC0844BJ. BCJ ADC0844CCN ADC0844CJ. CCJ VREF = 5.00 Voc (Note 3) ±% ±1 LSB LSB LSB LSB Minimum Reference Input Resistance 2.4 1.1 2.4 1.2 ' 1.1 kO Maximum Reference Input Resistance 2.4 4.1 2.4 3.8 4.1 kO Maximum Common-Mode Input Range (Note 4) Vcc+ 0•05 Vcc+ 0.05 Vcc+ 0•05 V Minimum Common-Mode Input Range (Note 4) GND-0.05 GND-0.05 GND-0.05 V DC Common-Mode Error Differential Mode ±'As ±% ±'As ±% ±% LSB Power Supply Sensitivity Vee = 5V±5% (Note 8) On Channel = 5V. Off Channel = OV On Channel = OV. Off Channel = 5V ±Y1S ±Ya ±'As ±Ya ±Ya LSB -1 -0.1 -1 ,.,.A 1 0.1 1 ,.,.A Off Channel Leakage Current DIGITAL AND DC CHARACTERISTICS VINll). Logical"1" Input Vol age (Min) Vee = 5.25V 2.0 2.0 2.0 V VINlO). Logical "0" Input Vol age (Max) VCC = 4.75V 0.8 0.8 0.8 V IIN(l). Logicai "1" Input Current (Max) VIN = 5.0V IIN(O). Logical "0" Input Current (Max) VIN = OV VOUT(lt Logical "1" Output oltage (Min) VOUT(Ot Logical "0" Output oltage (Max) Vec = 4.75V lOUT = - 360 ,.,.A lOUT = -10,.,.A Vee = 4.75V lOUT = 1.6mA lOUT. TRI-STATE Output Current (Max) VOUT VOUT ISOURCE. Output Source Current (Min) = = VOUT = ISNK. Output Sink Current (Min) VOUT ICC. Supply Current (Max) CS = = OV 5V OV Vcc 1. VREFOpen 0.005 1 0.005 1 ,.,.A -0.005 -1 -0.005 -1 ,.,.A 2.4 4.5 2.8 4.6 2.4 4.5 V V Of. 0.4 0.34 0.4 V -0.01 0.01 -14 -3 3 -0.3 0.3 -7.5 -3 3 ,.,.A -6.5 -0.01 0 .. 01 -14 -6.5 mA 16 8.0 16 9.0 8.0 mA 1 2.5 1 2.3 2.5 mA S5-79 p.A AC Characteristics Parameter Conditions te. Maximum Conversion Time (See Graph) Typ (Note 5) 30 Tested Limit (Note 6) Design Limit (Note 7) Units ",,5 40 twfWAI. Minimum WR Pulse Width (Note 9) 50 150 ns tACC. Maximum Access Time (Delay from Falling Edge of RD to Output Data Valid) CL = 100pF (Note 9) 145 225 ns tlH. toH. TRI-STATE Control (Maximum Delay from Rising Edge of AD to Hi-Z State) CL = 10pF. RL = 10k (Note 9) 125 200 ns v . (Note 9) 200 400 ns toS. Minimum Data Set-Up Time (Note 9) 50 100 ns tOH. Minimum Data Hold Time (Note 9) 0 50 twl. tAl. Maximum Delay from Falling Edge of WR or fii) to Reset of INTR ns CIN. Capacitance of Logic Inputs 5 pF GoUT. Capacitance of LogiC Outputs 5 pF Note 1: Absolute Maximum Ratings are those values beyond which the IWe of device may be Impaired. Note 2: All voltages are measured with respect to ground. Note 3: Total unadjusted error includes offset. full-scale. linearity, and multiplexer error. Note 4: For VIN (-) ~ VIN (+) the digital output code will be 0000 0000. Two on-chlp diodeS are tiad to eech analog input, which will forward-Conduct for analog input voltages one diode drop below ground or one diode drop greeter then Vrx; supply. Be careful during testing at low Vrx; lovals (4.5V), as high level analog inputs (5V) can cause this input diode to conduct, especially at elevated temperetures, and cause errors for analog inputs neer full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more then 50 mV, the output code will be correct. To achieve an absolute 0 Vee to 5 Vee Input voltage range will therefore require a minimum supply voltage of 4.950 Vee over temperature variations, initial tolerance ~~. . . Nota 5: Typicals are at 2SOC and represent most likely parametric norm. Nota 6: Guaranteed and 100% productfon tested. Note 7: Guaranteed, but not 100% production tasted. These limits are not used to calculate outgoing quality levels. Nota 8: Off chennelleekage current Is measured aftsr the channel selection. Note 9: The temperature coefficient is 0.3%I'C. 55-80 Typical Performance Characteristics Logic Input Threshold Voltage vs Supply Voltage I.B Output Current vs Temperature 25 s: _55 D C TA ~ +125D C <" 20 1.7 1.5 ...ffioS ,....'"'" ... ~ 1.6 ~ 10 £ ~RCE 5.00 525 Vce - SUPPLY VOLTAGE rVDel 1.0 ~ Vce~5V 0.5 40 ~ 3D r-. r-. 20 o 2 o 3 4.5 Conversion Time vs Temperature 50 3D co in 20 . 10 co o -75 -50-25 0 25 50 75100125 TEMPERATURE I'C) - - ~ ~ ~ 4.75 5 6.25 SUPPLY VOLTAGE IV) / I' 5.5 Unadjusted Offset Error vs VREF Voltage 14 Vec-5! 40 :E ;z ~ 0.5 '" 10 \lftEF IV) >= z -r-. """" ~ - 50 ~ I \.. o w ... .... ........ 60 Conversion Time vs VSUPPLY TA=25'C IZfRO AND FULL-SCALE- t - ADJUSTED) I ~ i,.'" TA=25'C ~ ~ ~ I.S .......... Voe - 2.41V Linearity Error vs VREF i" w i"""o ~OC=5V- -75 -50 -250 25 SO 75 100 125 TEMPERATURE I'C) 5.50 Vcc:,SV I I rs+v4=¥1 o 4.75 2 JVtc=s Voc ~OCjoVI ~ co 1.4 1.3 4.50 15 ~ .... Power Supply Current vs Temperature ~ VJN(~I;~~N(-)=O 12 !'" '" 10 I- II- ~ itco t:; o o -75-50 -25 0 25 50 75 100 125 TEMPERATURE I'C) 0.01 - vos=2 mv - , 0.1 1.0 VREF IV) TL/H/5016-3 55·81 TRI-STATE Test Circuits and Waveforms Vee Vee DATA : : : TLlH/5016-4 OUTPUTS ~~IH ""-- GNU ------= TLlH/5016-5 t,.=20n$ tOH. CL 10 pF tOH vee vee GNO OH Vee ~ -- DATA OUTPUTS. 10% VOL TL/H/5016-7 1,=2Ons TLlH/5016-6 Leakage Current Test Circuit 5V CH1 (OFF) ADC0844 1'"---~MCH2 (ON/OFF) CH3 (ON/OFF) CH4 (ON/OFF) CHANNEL VOLmGE SELECT. TL/H/5016-6 55-,82 --------------------------------------------------------------------,~ c oo Timing Diagrams c» ~ ~ Programming New Channel Configuration and Starting a Conversion \'--___r --II'------" cs \~_ _ _ iiii j-------Ic-------I ~:::~~ -----TUH/5016-9 Nole 1: Read slrobe musl occur al leasl600 ns after the assertion of inlerrupllo guarenlee iesel of INTR. Nole 2: MA slands for MUX address. Using the Previously Selected Channel Configuration and Starting a Conversion iiii I_-++---~ 9 ___ ',--_I 1 ---J ------------{ DBD-DB7 '}-_ READING THE RESUIJ OF THE LAST CONVERSION S5-83 TL/H/5016-10 ADC0844 ." C :::I Vee 20' :::I DGND ..L Vag~ -. ~ I -.... CHI CH2 CH3 It. ~~1 -+-t~-"'Il!~or- CH4 ADHD , J .Ji?\. l r-- LADDER AND DECODER ~ ~1 1-' G~ CLK CLK BEN +(-::~~ -V- - I 1 e. I+i m 0' n ~ C L....-. _ +(-) S:~ .. SARLATCH ,~ SHIFT~:STER ii' ca i 3 . ~.JC r- 1. ' "'l ){ -11-+--t--r...,_J'\6'~ , - ONE SHOT en en ~ !...,--j XI'EII ....- - - - - , TRI-STATE" OUTPUT LATCHES MUX DECODER 1£ MUX ADDRESS LA~H L , fiil W "1"=DUTPUT ERAR~ - rr-- 6OD ns ~ DElAY iliTii 1----_-, ----"t'"-, MAD MA1 ..... MA2I-----1"".,' M~~------_t-jr-,--r ~ ,~., -{J;:::; ---1 DIGITAL OUTPUTS .( J>,:.;' J -- - 1 TL/H/5016-11 Functional Description The ADC0844 contains a 4-channel analog multiplexer (MUX) which can be configured in a single-ended, differential, or pseudo-differential mode (Table 1). The specific mode is selected by loading the MUX address latch with the proper address. Inputs to the MUX address latch (MAOMA3) are common with data bus lines (DBO-DB3) and are enabled when the RD line is high. A conversion is initiated via the CS and WR lines. If the data from a previous conversion is not read, the INTR line will be low. The falling edge of WR will reset the INTR line high and ready the AID for a conversion cycle. The rising edge of WR, with RD high, strobes the data on the MAO/DBO-MA3/DB3 inputs into the MUX address latch to select a new input configuration and start a conversion. If the RD line is held low during the entire low period of WR the previ04s MUX configuration is retained, and the data of the previous conversion is the output on lines DBO-DB7. After the conversion cycle (tc;";40 ",5), which is set by the internal clock frequency, the digital data is transferred to the output latch and the INTR is asserted low. Taking CS and RD low resets INTR output high and outputs the conversion result on the data lines (DBO-DB7). Applications Information 1.0 MULTIPLEXER CONFIGURATION The design of these converters utilizes a sample-data comparator structure which allows a differential analog input to be converted by a successive approximation routine. The actual voltage converted is always the difference between an assigned" + .. input terminal and a .. -" input terminal. The polarity of each input terminal of the pair being converted indicates which line the converter expects to be the most positive. If the assigned" + .. input is less than the .. -" input the converter responds with an all zeros output code. A unique input multiplexing scheme has been utilized to provide multiple analog channels. The input channels can be software configured into three modes: differential, single- TABLE I. ADC0844 MUX ADDRESSING MUXAddress CS MA3 MA2 MAl MAO X' L L L L L L H H L H l H L L L H H H H H H L L H H L H X X X L L L L H H H H H X X x = don't care L Channel # RD CHl L L L L H WR If H H H If If H H H If l H L X X L - H H H CH3 CH4 + - r - + - - + - + + H - + - + Single-Ended PseudoDifferential - + Previous Channel Configuration 2 Differential (+1 (+1 (+1 (+1 CH1,CH2{ CH3,CH4{ AGND(-I = = +(-1 -(+1 +(-1 -(+1 TUH/5016-12 TL/H/5016-13 3 Pseudo-Differential Combined -- CH1- (+1 CH2- (+1 CH3- (+1 CH4- MUX Mode Differential + 4 Single-Ended CH1CH2CH3CH4- AGND + H L L L L L L L + CH2 CH1.CH2{ - + CH3- + CH4- + AGND(-I r H TL/H/5016-14 , . TUH/5016-15 FIGURE 1. Analog Input Multiplexer Options 55-85 Applications Information (Continued) ended, or pseudo-differential (Fl{Jure 1). In the differential mode, the channel inputs are grouped in pairs, CH1 with CH2 and CH3 with CH4. The polarity assignment of each channel in the pair is interchangeable. The single-ended mode has CH1-CH4 assigned as the positive input with the negative input being the analog ground (AGND) of the device. Finally, in the pseudo-differential mode CH1-CH3 are positive inputs reflilrenced to CH4 which is now' a pseudoground. This pseudo-ground input can be set to any potential within the input common-mode range of the converter. The analog signal conditioning required in transducer-based data acquisition systems is significantly simplified with this type of input flexibility. One converter package can now handle ground referenced inputs and true differential inputs as well as signals with some arbitrary reference voltage. The analog input voltages for each ch~nnel can range from 50 mV below ground to 50 mV above Vee (typically 5V) without degrading conversion accuracy. small (see Typical Performance Characteristics) to allow direct conversions of transducer outputs providing less than a 5V output lipan. Particular care must be taken with regard to noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1 LSB equals VREF/256). 3_0 THE ANALOG INPUTS 3.1 Analog Differential Voltage Inputs and CommonMode Rejection The differential input of these converters actually reduces the effects of common-mode input noise, a signal common to both selected" + .. and .. -" inputs for a conversion (60 Hz is most typical). The time interval between sampling the .. + .. input and then the inputs is % of a clock period. The change in the common-mode voltage during this short time interval can cause conversion errors. For a sinusoidal common-mode signal this error is: U -" 2.0 REFERENCE CONSIDERATIONS The voltage applied to the reference input to these converters defines the voltage span of the analog input (the difference between VIN(MAX) and VIN(MIN» over which the 256 possible output codes apply. The devices can be used in either ratio metric applications or in systems requiring absolute accuracy. The reference pin must be connected to a voltage source capable of driving the reference input resistance of typically 2.4 kG. This pin is the top of a resistor divider string used for the sl,lccessive approximation conversion. In a ratiometric system (Rgure 2a), the analog input voltage is proportional to the voltage used for the AID reference. This voltage is typically the system power supply, so the VREF pin can be tied to Vcc. This technique relaxes the stability requirements of the system reference as the analog input and AID reference move together maintaining the same output code for a given input condition. For absolute accuracy (Rgure 2b), where the analog input varies between very specific voltage limits, the reference pin can be biased with a time and temperature stable voltage source. The LM385 and LM336 reference diodes are good low current devices to use with these converters. The maximum value of the reference is limited to the Vee supply voltage. The minimum value, however, can be quite VERROR(MAX)=Vpeak (2'IT fCM)XO.5X (~) where fCM is the frequency of the common-mode signal, Vpeak is its peak voltage value and Ie is the conversion time. For a 60 Hz common-mode signal to generate a % LSB error (:::: 5 mY) with the converter running at 40 poS, its peak value would have to be 5.43V. This large a common-mode signal is much greater than that generally found in a well designed data acquisition system. 3_2 Input Current Due to the sampling nature of the analog inputs short duration spikes of current enter the .. + .. input and exit the .. -" input at the clock edges during the actual conversion. These currents decay rapidly and do not cause errors as the internal comparator is strobed at the end of a clock period. Bypass capacitors at the inputs will average these currents and cause an effective DC current to flow through the output resistance of the analog signal source. Bypass capaCitors should not be used if the source resistance is greater than 1 k!l. 5V 5V Vee Vee CH1(+) CH11+) CH2(+) CH2(+) VII'F - ~+- CH31+) CH3(+) CH4(+) CH4(+) LM385 (-)AGND (-)AGND . ~, ":" TLlHf5016-16 b) Absolute with a Reduce Span a) Ratlometrlc FIGURE 2. Referencing Examples S5-86 TLfHf5016-17 Applications Information (Continued) 4.3 Adjusting for an Arbitrary Analog Input Voltage Range If the analog zero voltage of the AID is shifted away from ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference should be properly adjusted first. A VIN (+) voltage which equals this desired zero reference plus ¥2 LSB (where the LSB is calculated for the desired analog span, 1 LSB = analog span/256) is applied to selected" +" input and the zero reference voltage at the corresponding "-" input should then be adjusted to just obtain the OOHEX to 01 HEX code transition. . The full-scale adjustment should be made [with the proper VIN (+) voltage applied) by forcing a voltage to the VIN( -) input which is given by: 3.3 Input Source Resistance The limitation of the input source resistance due to the DC leakage currents of the input multiplexer is important. A worst-case leakage current of ± 1 /LA over temperature will create a 1 mV input error with a 1 kO source resistance. An op amp RC active low pass filter can provide both impedance buffering and noise filtering should a high impedance signal source be required. 4.0 OPTIONAL ADJUSTMENTS 4.1 Zero Error The zero of the AID does not require adjustment. If the minimum analog input voltage value, VIN(MIN), is not ground, a zero offset can be done. The converter can be made to output 0000 0000 digital code for this minimum input voltage by biasing any VIN (-) input at this VIN(MIN) value. This is useful for either differential or pseudo-differential modes of input channel configuration. The zero error of the AID converter relates to the location of the first riser of the transfer function and can be measured by grounding the V- input and applying a small magnitude positive voltage to the V + input. Zero error is the difference between actual DC input voltage which is necessary to just cause an output digital code transition from 0000 0000 to 0000 0001 and the ideal ¥2 LSB value (¥2 LSB = 9.8 mV for VREF=5.000 Voe>. V (+)fsadj·=V -15 [(VMAX-VMIN)] IN MAX· 256 where VMAX=the high end of the analog input range and VMIN=the low end (the offset zero) of the analog range. (Both are ground referenced.) The VREF (or Vee) voltage is then adjusted to provide a code change from FEHEX to FFHEX. This completes the adjustm!lnt procedure. For an example see the Zero-Shift and Span Adjust circuit below. 4.2 Full·Scale The full-scale adjustment can be made by applying a differential input voltage which is 1 ¥2 LSB down from the desired analog full-scale voltage range and then adjusting the magnitude of the VREF input for a digital output code changing from 11111110 to 11111111. Zero-Shift and Span Adjust (2V ~ VIN ~ 5V) Vcc 16VDCl VINI+) Vcc + VIN ~ID"F I I VINI-) lk 2Voc ZERO AOJ 2.7k Uk - - - - -. ADCIII44 SETS ZERO CODE VOLTAGE (2V) -=-SETS VOLTAGE SPAN VREF I I I LM33&-2.6 330 I _J -=- -=- -=- TL/H/5016-18 S5-87 .- ft Applications Information (Continued) C Differential Voltage Input 9-Bit AID III( r------------..-<·Vw R Vwl-...._ R TUH/5016-19 Span Adjust OV:S:VIN:S:SV Vec (5VDCI ...--<>---1 V,N('I vcc I-~'-------., ADCIl844 -TUHI5016-20 Protecting the Input High Accuracy Comparators 5V Vce (5VDCI Vee VrH1 Vee SYSTEM POIr:~ 2 >----1+ } ADCIl844 VrH2 -15VDC ADe0844 TUH/5016-22 TLlHI5016-21 00=8111. ff VIN(+»VIN(-) Diode. are 1N914 00=811 Os if VIN(+) ...------------1 CHI CH2 r-------------i .------------ICH3 lk Vce • Vee ADCD844 910 T2 2k ¥REF r I Ta L , ILM335 .J Vee-Yl,..,..... lk • 3k TL/H/5016-24 . Uses the pseudo-differential mode to keep the differential Inputs constant with changes in reference temperature (TREF). 55-89 Applications Information (Continued) A Stand Alone Circuit IV 3 5V Uk (8PL) CHl 0B7 08& 085 01 11 12 13 8' D84 AOCD844 14 MA3/0B3 13 15 14 1& 17 MAD/OIO 17 18 MAZ/DB2 MAl 1011 02 02 03 03 04 D4 MM74C374 D5 05 12 DB Q& 07 07 08 08 15 NSLI027 (8 PL) '" '" '" '" '" 16 19 11 5V 3 5 7 9 0,02 Oa D4 15 . 5.1k I DlS2 s.n 5.1k 5.1k 10 MUX ADDRESS MAD , '=' 13 MAl & MM8DC95 12 OISl 4 INl 2 TL/H/5016-25 Start a Conversion without Updating the Channel Configuration ~>------------------I~ WR>------------r"""""'" ADC0844 TLlH/5016-26 OS.WR will update the channel configuration and start a conversion. OS.FIO will read the conversion data and start a new conversion without updating the channel configuration. Waiting for the end of this conversion is not necessary. A OS.W!'i can immediately follow the OS.J'j[j, 85-90 l> Applications Information C (') Q CD (Continued) "., "., ADC0844-1NS8039 Interface 5V 5V 40 20 Vee -OBO OBI DB2 DB3 DB4 INS8039 085 DB6 DB7 Viii iiD 12 17 13 16 14 15 15 14 16 13 17 12 18 11 1~ 10 27 DBlIMAl I'REF (+)CHI (-)CH2 OB2IMA2 DB3/MA3 DB4 DB5 ADC0844 DB6 DB7 19 PIO Pit OBO/MAO 18 Viii iiD cs INTR (+)CH3 (-)CH4 TL/H/5016-27 0000 0410 0010 B9FF 0012 0014 0016 B820 89FF 2300 0018 001A 1450 2302 001C 001D 18 1450 SAMPLE PROGRAM FOR ADC0844-INS8039 INTERFACE CONVERTING TWO RATIOMETRIC, DIFFERENTIAL SIGNALS OH ORG JMP BEGIN ;START PROGRAM AT AD DR 10 10H ;MAIN PROGRAM ORG BEGIN: MOV R1,#OFFH ;LOADR1 WITH A UNUSED ADDR ;LOCATION MOV RO#20H ;AID DATA ADDRESS ORL P1,#OFFH ;SET PORT 1 OUTPUTS HIGH MOV A,OOH ;LOAD THE ACC WITH AID MUX DATA ;CH1 AND CH2 DIFFERENTIAL CALL CONV ;CALL THE CONVERSION SUBROUTINE A,#02H ;LOAD THE ACC WITH AID MUX DATA MOV ;CH3 AND CH4 DIFFERENTIAL ;INCREMENT THE AID DATA ADDRESS INC RO CALL CONV ;CALL THE CONVERSION SUBROUTINE ;CONTINUE MAIN PROGRAM ;CONVERSION SUBROUTINE ;ENTRY:ACC-AID MUX DATA ;EXIT: ACC-CONVERTED DATA 0050 0052 0053 0054 0056 0057 0059 005A 99 FE 91 09 3253 81 8901 AO 83 CONV: LOOP: ORG ANL MOVX IN JB1 MOVX ORL MOV RET 50H P1,#OFEH @R1,A A,P1 LOOP A,@R1 P1 &01H @RO,A S5·91 ;CHIP SELECT THE AID ;LOAD AID MUX & START CONVERSION ;INPUT INTR STATE ;(F INTR = 1 GOTO LOOP ;IF INTR ~ 0 INPUT AID DATA ;CLEAR THE AID CHIP SELECT ;STORE THE AID DATA ;RETURN TO MAIN PROGRAM • r--------------------------------------------------------------------------------- • I Applications Information (Continued) I/O Interface to NSC800 RlI Wii AD7 AD6 ADI5 ADI4 ADI3 ADI2 ADll IDiM AD5 AD4 AD3 AD2 ADI ADO 5V STRB liD DMB131 OUT 9 ADC0844 VaEF 2C§ DGND CHI(+I CH2(+1 CH3(+1 8 VR 10 CH4(+1 AGNO '::" '::" TLlHI5016-28 SAMPLE PROGRAM FOR ADC0844-NSC800 INTERFACE 0008 OOOF 001F 3COO 0000' 0003' 0004' 0006' 0008' OOOB' OOOE' OBOA09 08 OE 1F 0608 210000' 11003C EDA3 0010' EB 0011' 0013' 0014' 0017' 3EOF 3D C20013' EDA2 0019' 001A' EB C2000E' NCONV DEL CS ADDTA EQU EQU EQU EQU 8 15 1FH 003CH MUXDTA: DB DB LD LD LD LD OUTI OBH,OAH,09H 08H C,CS B,NCONV HL,MUXDTA DE,ADDTA EX DE,HL LD DEC JP INI A,DEL A NZ,WAIT' EX JP DE,HL NZ,STCONV START: STCONV: WAIT: ;DELAY 50 ,,"sec CONVERSION ;THE BOARD ADDRESS ;START OF RAM FOR AID ;DATA ;MUXDATA ;LOAD AID'S MUX DATA ;AND START A CONVERSION ;HL= RAM ADDRESS FOR THE ;AlDDATA ;WA(T 50 ,,"sec FOR THE ;CONVERSION TO FINISH ;STORE THE AID'S DATA . ;CONVERTED ALL INPUTS? ;IF NOT GOTO STCONV END Nole: this routine sequentially programs Ihe MUX data latch in the signal·ended mode. For CHI·CH4 a conversion is started, then a 50 "S waH for the AID 10 complete a conversion and the data is stored at address ADDTA for CHI, ADDTA + 1 for CH2, etc. Ordering Information Temperature Range O"C to 70"C ± 1,4 LSB Unadjusted ADC0844BCN ± 1 LSB Unadjusted Package Outline -40°C to + 8SoC ADC0844BCJ -SsoC to + 12SoC ADC0844BJ ADC0844CCN ADC0844CCJ ADC0844CJ N20A-Molded DIP J20A-CERDIP J20A-CERDIP S 5-92 )0 C o.... ~National N .... ~ Semiconductor !:! )0 c o.... ADC1210, ADC1211 12-Bit CMOS AID Converters .... .... N General Description Both devices are available in military and industrial temperature ranges. The ADC1210, ADC1211 are low power, medium speed, 12bit successive approximation, analog-to-digital converters. The devices are complete converters requiring only the application of a reference voltage and a clock for operation. Included within the device are the successive approximation logic, CMOS analog switches, precision laser trimmed thin film R-2R ladder network and FET input comparator. Features • • • • • • • The ADC1210 offers 12-bit resolution and 12-bit accuracy, and the ADC1211 offers 12-bit resolution with 1O-bit accuracy. The inverted binary outputs are directly compatible with CMOS logic. The ADC1210, ADC1211 will operate over a wide supply range, convert both bipolar and unipolar analog inputs, and operate in either a continuous conversion mode or logic-controlled START-STOP conversion mode. The devices are capable of making a 12-bit conversion in 100 I-'s typ, and can be connected to convert 10 bits in 30 I-'s. 12-bit resolution ±% LSB or ±2 LSB nonlinearity Single + 5V to ± 15V supply range 100 I-'s 12-bit, 30 I-'s 10-bit conversion rate CMOS compatible outputs Bipolar or unipolar analog inputs 200 kO analog input impedance Block Diagram zz V'IVREFlOO-+-------------------------+----. RZ9 ZOk CLOCK START -CONVERSION COMPLETE COMPARATDR DUTPUT Z-12 Z-1 RZ6 ZOOk RZ5 ZOOk ilZ8 RZl ZOk ZOk OIGITAL OUTPUTS ZO 19 18 11 16 15 TLlH/5677-1 Connection Diagram Dual-In-Line Package ILSBI Z4 2-12 CLOCK z:I COMPARATOR OUTPUT ZZ +VIVREf l Order Number ADC1210HD, ADC1210HCD, ADC1211HD, ADC1211HCD See NS Package 0240 21 GND ,-I ZO v- ,., t. R2B ,-I 11,125 ,-. 17 'IN 1& AZI 15 AZl 2-2 II 14 ~~:~~~:~~~I 2-1 1Z 13 START III:) (MSII L -_ _ _ _ _- ' TOPYIEW TL/H/S677 -2 S5-93 .... .... N .... (.) ~.... .... Absolute Maximum Ratings Maximum Reference Supply Voltage N+) Voltage At Any Logic Pin Analog Input Voltage (.) Maximum Digital Output Current c( Power Dissipation ADC1210HD, ADC1211 HD ±15V Maximum Comparator Output Current -55·Cto + 125·C - 25·C to + 85·C ADC1210HCD, ADC1211 HCD ±10mA Comparator Output Short-Circuit Duration See Curves Operating Temperature Range V++0.3V N C 16V -20V Maximum Negative Supply Voltage (V-) -65·Cto + 150'C Storage Temperature Range Lead Temperature (Soldering, 10 seconds) 300'C 50mA 5 Seconds DC Electrical Characteristics (Notes 1 and 2) Parameter ADC1210 Conditions Resolution ADC1211 Typ Min Max 12 Typ Units Max 12 (Note 3) fCLK = 65 kHz, T A= 25·C fCLK=65 kHz Linearity Error Min Bits ±0.0183 ±0.0366 ±0.0488 %FS %FS Full Scale Error TA = 25·C, Unadjusted 0.20 0.50 %FS Zero Scale Error TA = 25·C, Unadjusted 0.20 0.50 %FS ±1/2 ±1/2 LSB Quantization Error Input Resistor Values R27, R28 20 20 Input Resistor Values R25,R26 200 200 Input Resistor Ratios R25/R26,R27/R26 kn kn 0.6 Logic "1" Input Voltage 8 6 - Logic "0" Input Voltage % 0.6 V 2 2 V 1 1 p.A -1 !LA 0.5 V Logic "1" Input Current • VIN=10.24V Logic "0" Input Current VIN=OV Logic "1" Output Voltage IOUT~-1 p.A Logic "0" Output Voltage iOUT~1 p.A Positive Supply Current V+ =15V, fCLK=65 kHz, TA=25·C 5 8 5 8 rnA Negative Supply Current V-=-15V, TA=2S·C 4 6 4 6 mA -1 9.2 9.2 V 0.5 .AC Electrical Characteristics TA = 25·C, (Notes 1 and 2) Typ Max Conversion Time 100 200 p.s Maximum Clock Frequency 130 65 kHz Parameter Conditions Clock Pulse Width Min 100 t,.~tf~10 Propagation Delay From Clock to Data Output 50 Units ns ns 60 150 ns t,.~tf~10ns 60 150 ns 5 p.s (QOto Q11) Propagation Delay from Clock to Conversion Complete Clock Rise and Fall TIme Input Capacitance 10 Start Conversion Set-Up Time 30 pF ns Nota 1: Unless othOrwise noted, these specifications apply for V+ =10.240V, V-= -15V, over the temperature range -55"C to + 125'C for the ADC1210HD, • ADCI211HD. and -25"Clo +85'C for the ADC1210HCD, ADC1211 HCD. Note 2: All typical values are for TA= 25'C. Note 3: Unless otherwise noted, this specification applies over'the temperature range - 25'C to + 85'C. Provision Is made to edjust zero scale error to OV and fullscale to 10.2375V during testing. Standard linearity test cireuR is shown In Rgure Sa. , , S5-94 --------------------------------------------------------------------,~ o Schematic Diagram o ~ N v- ~ " " II II R25 2aOtt R21 200k o ;; IS R27 tall All ZOIt o o .~ N ~ ~ .zg .1< 'Ok 20011 ........--+_ V'(V."IO:':"T----4~---...,.---+--- C. CONTROL lOGIC START CONVERSION COMPLETE GND~ 14 2-12 TLlH/5677-3 Note: 3 bits shown for clarity Power Dissipation vs Temperature Supply Current vs Supply Voltage 2.25 100 Hz" fCLK'; 250 kHz TA"zs·c'T I 'JA·60·CIW I'- ~ 1.75 ~ . I' S 1.25 !ffi v· PIIN23A~ LOGIC ..... "0" I-" 10- '\ t.5 V+. PiN 23 -;;70Gic "I" ~ v- I--"" 0.75 I-" - ;0: f 0.50 0.25 o o o 25 50 75 100 125 150 o 10 15 SUPPLY VOLTAGE (.V) TEMPERATURE (·CI TLlH/5677-5 TL/H/5677-4 1.0 THEORY OF OPERATION The AOC121 O. ADC1211 are successive approximation analog-to-digital converters. i.e.• the conversion takes place 1 bit at a time by comparing the output of the internal 01 A to the (unknown) input voltage. The START input (pin 13). when taken low. causes the register to reset synchronously on the next CLOCK low-to-high transition. The MSB. 011 is set to the low state. and the remaining bits. 00 through 010. will be set to the high state. The register will remain in this state until the SC input is taken high. When START goes high. the conversion will begin on the low-ta-high transition of the CLOCK pulse. 011 will then assume the state of pin 23. If pin 23 is high. 011 will be high; if pin 23 is low. 011 will remain low. At the same time. the next bit 010 is set low. All remaining bits. 00-09 will remain unchanged (high). This process will continue until the LSB (00) is found. When the conversion process is completed. it is indicated by CONVERSION COMPLETE (CC) (pin 14) going low. The logic levels at the data output pins (pins 1-12) are the complemented-binary representation of the converted analog signal with 011 being the MSB and 00 being the LSB. The register will remain in the above state until the SC is again taken low. An application example is shown in Figure 1. In this case. a o to -10.2375V input is being converted using the ADC1210 with V+ = 10.240V. V- = -15V. Figure 1b is the timing diagram for full scale input. Agure 1c is the timing diagram for zero scale input. Figure 1d is the timing diagram for - 3.4125V input (010101010101 = output). S5-95 ' ~ ~ r----------------------------------------------------------------------------------------------- W ~ g ~ ~ w ~ g +vIVREFI.,U.VO=U....- - - - - - - - - - - - - - - - - - - - - - . , HZ4 CLOCK START CONVERSION COMPLETE COMPARATOR OUT cc ZUlli DIGITAL OUTPUTS 19 ZOOk 18' t7 20 -15V VIN" ovro -,U375V TL/H/5677-6 FIGURE 1a. ADC1210 Connected for OV to -10.2375V (Natural Binary Output) 10 11 12 13 Cp PIN 13 011 010 09 08 07 DB 05 04 03 02 01 Y 00---1 R---1 ~I~____ f-1--------CONVERS10NT1ME---------.,.1 t DATA FIGURE 1b. Timing Diagram for VIN= Full Scale Input 55·96 TLlH/5677-7 :J> 1D 11 12 13 C 0 .... N .... 0 •• ..... :J> C 0 .... N .... .... a. 00 cc----.J L-- 1-1--------coNvERsIDNTlME,---------I1 TL/H/5677-B FIGURE ie. Timing Diagram for VIN = Zero Scale cp PIN 23 all 0'0 09 07 06 05 113 112 a. Oo----.J ~ cc---Jr--------------------------~L---- II-- - - - - - - CONVERSIONTIME----------I·I FIGURE 1d. Timing Diagram for VIN= -3.412SV (010101010101) 55-97 TUH/5677-9 ..... ..... N ..... (.) TABLE 1. Pin Assignments and Explanations Pin Number Mnemonic c( 1-12 011-00 0 ..... N ..... (.) Digital (data) output pins. This information is a parallel 12-bit complemented binary representation of the converted analog signal. All data is valid when "Conversion Complete" goes low. Logic levels are ground and V+. 13 ~ Start Conversion is a logic input which causes synchronous reset of the successive approximation register ,and initiates conversion. Logic levels are ground and V+. 14 CC "Conversion Complete" is a digital output Signal which indicates the status of the converter. When CC is high, conversion is taking place, when low conversion is completed. Logic levels are ground and V+. 15,16 R27,R28 R27 and R28 are two application resistors connected to the comparator non-inverting input. The resistors may be used in various modes of operation. Their nominal values are 20 kG each. See Applications section. 17 +IN Non-inverting input of the analog comparator. This node is used in'various configurations and for cQmpensation of the loop. See Applications section. 18,19 R25,R26 R25 and R26 are two application resistors that are tied internally to the inverting input of the comparator. Their nominal values are 200 kG each. See Applications section. The R2R ladder network will have the same temperature coefficient as these resistors. 20 V- Negative supply voltage for bias of the analog comparator. Optionally may be grounded or operated with voltages to - 20V. 21 22 GND V+(VREF) Ground for both digital and analog signals. V+ sets both maximum full scale and input and output logic levels. 23 CO Comparator output. 24 Cp Q ...... Q c( Function Clock is an input which causes the successive approximation (shift) register to advance , through the conversion sequence. Logic levels are ground and V+. 10-bit conversion accuracy is taking place. The 02 output should be "OR'd" with CONVERSION COMPLETE (CC) in order to ensure that the register does not lock-up upon power turn-on. 2.0 APPLICATIONS, 2.1 Power Supply Considerations and Decoupllng Pin 22 is both the positive supply and voltage reference input to the ADC1210, ADC1211. The magnitude of V+ determines the input logic "1" threshold and the output voltage from the CMOS SAR. The device will operate over a range of V+ from 5V to 15V. However, in order to preserve 12-bit acc:uracy, V+ should be well regulated (0.01%) and isolated from external switching transients. It is therefore recommended that pin 22 be decoupled with a 4.7 ,.F tantalum capacitor in parallel with a 0.1 ,..F ceramic disc capacitor. The V- supply (pin 20) provides negative bias for the FET comparator. Although pin 20 may be grounded in ~ome applications, it must be at least 2V more negative than the most negative analog input signal. When a negative supply is used, pin 20 should also be bypassed with 4.7 ,..F in parallel with 0.1 ,.F. DIGITAL OUTPUTS TUHl56n-l0 FIGURE 2. Short Cycling the ADC1211 to Improve 10-Blt Conversion Time (Continuous Conversion) 2.3 Logic Compatibility . The ADC1210, ADC1211 is intended to interface with CMOS logic levels: i.e., the logic inputs and outputs are directly compatible with series 54C174C and CD4000 family of logic components. The outputs of the ADC1210, ADC1211 will not drive LPTTL, TIL or PMOS logic directly without degrading accuracy. Various recommended interface techniques are shown in Figures 3 and 4. Grounding and circuit layout are extremely important in preserving 12-bit accuracy. The user is advised to employ separate digital and analog returns, and to make these PC board traces as "heavy" as practical. 2.4 Operating Configurations Several recommended operating configurations are shown in Figure 5. 2.2 Short Cycle for Improved Conversion Time (Figure 2) The ADC1210, ADC1211 counting sequence may be truncated to decrease conversion time. For example, when using the ADC12i1, 2 clock intervals may be "saved" if S5-98 l> C Applications Information (Continued) ornaTo 15VI o..... N ..... VcclSVI ;; Vcc ISV, C o ..... N ..... ..... SVSTEMC, DIGITAL OUTPUTS nLOR5V CMOS START COMPATIBLE CONVERSION liliMM7CCBDI ORMM7.QCI02 COMPLETE TL/H/5677-11 FIGURE 3. Interfacing an ADC1210, ADC1211 Running on Y+ > Vee. Example: Y+ = 10.24Y, System Yee = SY Vcc- ISV rl-l-oI-I.--I-I, ~ I5VJlIl" 'v "'T'Mo24 CLOCK P H>- .---J!!- STARTo- " ':~K:·I2- L .11-!!-_~~ {. .IO~_ .0 10 Cp •• •, ' r- • .....--...1-14-0 . 1+---~f.4-o O' ' _ ali 1 .74CIOt '::JL , MM74C801 .". 1+---oooo4~-o MM14C91l2 O. AOC1210. ADC1211 -I>-MM74C1I4 -..!! R r 1-1·-1--1-1-1, '12.'12-, ---,,, IOKN L _ J ~~~::;s a' -!-a, .!..... al!.... Q2J- MM14ctD6 .,~ QO~ L......--.-_..J ___ ~ LSI 'Ok ....- < l Vce o-"II\o_ .. Ic°NVERSION .~COMPLETE '/8!:'::I4~C8:>,"-----.....jJI'i'" TL/H/5677-12 FIGURE 4. Interfacing an ADC1210, ADC1211 Running onY+ < Vee. Example: Y+ = SY, Vee = 15Y 2.S Offset and Full Scale Adjust A variety of techniques may be employed to adjust Offset and Full Scale on the ADC1210, ADC1211. A straight-forward Full Scale Adjust is to incrementally vary V+ (VREF) to match the analog input voltage. A recommended technique is shown In Figure 6. An LM199 and low drift op amp(e.g., the LH0044) are used to provide the precision reference. The ADC1210, ADC1211 is put in the continuous convert mode by shorting pins 13 and 14. An analog voltage equal to VREF minus lY2 LSB (10.23625V) is applied to pins 18 and 19, and AI is adjusted until the LSB flickers equally between logic "1" and logic "0" (all other out· puts must be stable logic "0"). Offset Null is accomplished by then applying an analog input voltage equal to Y2 LSB at pins 18 and 19. A2 is adjusted until the LSB output flickers equally between logic "I" and logic "0" (all other bits are stable). In the circuit of Figure 6, the ADC1210, ADC1211 is configured for Complementary Binary logic and the values shown are for V+ = 10.240V, VFS = 10.2375V, LSB = 2.5 mY. An alternate technique is shown in Rgure 7. In this instance, an LH0071 is used to provide the reference voltage. An analog input voltage equal to VREF minus 1Y2 LSB (10.23~25V) is applied to pins 18 and 19. S5·99 ....C\I ..- g Applications Information (Continued) Voltage at Any Digital Input 17Vee VeetoGND ±25V Temperature Range Part numbers with 'LCN' suffix Voltage at VREF Input Storage Temperature Range Package Dissipation at TA = 25"C (Note 3) TMIN,;;TA,;;TMAX O·Cto 70·C - 40·C to + 85·C Part numbers with 'LCD' suffix -65·Cto +150·C - 55·C to + 125·C Part numbers with 'LD' suffix Voltage at Any Digital Input 500mW VeeTOGND -100mVtoVee DC Voltage Applied to IOUT1 or IOUT2 (Note 4) Lead Temp. (soldering, 10 seconds) 300·C Electrical Characteristics VREF= 10.000 Vee unless otherwise noted. Boldface limits apply over temperature, T MIN,;;TA,;;TMAX. For all other limits TA = 25·C. Parameter Conditions See Note Vcc= 12VOC±5% to 15 Voc±5% Vcc=5 Voc±5% 8 8 Limit Tested Design Tested Design Units Typ. Limit LImit Typ. Limit Limit (Note 12) (Note 5) (Note 6) (Note 12) (Note 5) (Note 6) Converter Characteristics Resolution Linearity Error Max. Zero and full scale adjusted -10V,;;VREF';; + 10V DAC0830LD & LCD DAC0832LD & LCD DAC0830LCN DAC0831LCN DAC0832LCN 0.05 0.2 0.05 0.1 0.2 Differential Nonlinearity Max. DAC0830LD & LCD DAC0832LD & LCD DAC0830LCN DAC0831LCN DAC0832LCN Zero and full scale adjusted -lOV,;;VREF,;;+10V Monotonicity -10V,;;VREF LD&LCD ';;+10V LCN 8 Using Internal Rib -10V,;;VREF,;;+10V Gain Error Tempco Max. Using internal Rib 0.0002 Power Supply Rejection All digital inputs latched high Vce= 14.5V to 15.5V 11.5Vto 12.5V 4.5Vt05.5V 0.0002 0.0006 ±0.2 7 15 Min. 15 All data inputs LD & LCD latched low LCN IOUT2 All data inputs LD & LCD latched high LCN 0.05 0.1 1).2 %FSR %FSR %FSR %FSR %FSR 0.1 0.2 0.4 0.1 0.4 0.1 0.2 0.4 0.1 0.2 0.4 %FSR %FSR %FSR %FSR %FSR 8 8 8 bits bits 8 ±1 ±0.2 0.0006 ±1 0.0002 %FS 0.0006 0/0 FSrC 0/0 FSRIV 0.0130 Reference Input Max. Output Leakage IOUT1 Current Max. 0.05 0.1 0.2 0.05 0.2 0.05 0.1 0.2 8 4, 7 Gain Error Max. VREF= 20 Vp·p, f= 100. kHz All data inputs latched low bits 4, 7 8 0.1 0.4 0.1 0.2 0.4 Output Feedthrough Error 8 8 4, 7 8 9 , 20 15 20 kO 10 15 10 kO 3 10 3 . 100 50 100 100 50 100 100 50 100 100 50 100 mVp·p nA nA Output IOUT1 Capacitance IOUT2 All data inputs latched low 45 115 45 115 pF IOUT1 IOUT2 All data inputs latched high 130 30 130 30 pF S 5-105 Electrical Characteristics VREF= 10.000 Vce unless otherwise IlQted. Boldface limits apply over temperature, T MIN s:TA s:TMAX. For all other limits TA = 25°C. (Continued) Parameter COnditions See Note Vcc=12VDC±S% t01SVoc±S% VCC=SVDC±5% Tested Limit (NoteS) Tested Limit (Notes) Design Limit (NoteS) 0.8 2.0 Typ. (Note 12) L1mH Design Limit (NoteS) typo (Note 12) Units Digital and DC Characteristics Digital Input Voltages Max. Min. Digital input Currents Max. Logic Low Logic High 0.8 0.8 1.0 0.8 O.S 0.8 1.0 LD&LCD LCN 2.0 1.9 2.0 2.0 1.9 -200 -160 -200 +10 +8 +10 2.0 1.7 2.0 Digital Inputs <0.8V LD & LCD LCN :-50 Digital inputs>2.0V LD & LCD LCN 0.1 Supply Current Drain Max. Symbol LD LCD LCN Parameter LD & LCD LCN COndltlona 1.2 -50 0.1 1.2 VCC= 12 VDC±S% to 1SVDC±S% _See Note Typ. Testt!d Limit (NoteS) Design Limit (NoteS) Voc Vee -200 -160 -200 . pAce +10 +8 +10 2.0 1.7 2.0 pAoc rnA . VCC=SVDC±S% Typ. Tested Limit (NoteS) Design Limit (NoteS) Limit Units AC Characteristics Is Current Setting Time VIL =OV, VIH=5V tw Write and XFER Pulse Width Min. VIL =OV, VIH=5V tos Data Setup Time Min. VIL =OV, VIH=5V tOH Data Hold Time Min. VIL =OV, VIH=5V 10 50 10 50 tcs Control Setup Time Min. VIL =OV, VIH=5V 110 200 320 320 400 500 650 900 1.0 11 p.s 1.0 100 180 320 320 375 500 600 900 100 180 320 320 375 500 900 600 ns Control Hold Time 10· 10 VIL =OV, VIH=5V Min. Note 1: "AbsoIutB Msx/mum Ratings" are those values beyond which the safety ci1 the device cannot be guaranteed. Thesa spaclflC8lions are not meant to Imply that the devices should be operated at these "AbsoIutB MsximIJIrf' limits. Note 2: All voltages are measured with respect to GND, unless otherwise specified. Note 3: Max. TJ for the 0 suffix packege is 15O'C with 9JA = 8I1'CIW. Max. TJ for the N suffix package is 125"C with 9JA';' 12O'C/W. Note 4: For current switching applications. both 10UT1 and 1our2 must go to ground or the ''Virtual Ground" 01 an operational amplifier. The linearity error Is degraded by approximately Vas + VREF' For example. H VREF=10V then a 1 mV ollsat, Vas. on IOUT1 or 10U12 will Introduce an additional 0.01% linearity error. Note 5: Guaranteed and 100% production -..d. Note 8: Guaranteed. but not 100% production -..d. Thesa Umits are not used to calculate outgoing quality levels. Note 7: Guaranteed at VREF= ± 10 Vee and VREF= ± 1 Voo. Note 8: The unH "FSR" slends for "Full Scale Range." "Unearlty Error" and "Powar Supply Relection" specs are basad on this un" to eliminate dapendence on a particular VREF valua and to indicate the true performance 01 the part. The "Unearity Error" specification of the DAC0830 Is "0.05% 01 FSR (MAX)". This guarantees thet aller performing a zero and full scale edlustment (see Sections 2.5 and 2.6). the plot 01 the 256 analog voltage outputs will each be within 0.05% XVREF 01 a straight line which passes through zero and full scale. Note 9: To achieve this low feedthrough In the 0 package. the user must ground the metal lid. If the lid Is left floating, the feedthrough is typically &mV. Note 10: A 100nA leakage current with Rjb=20k and VREF-10V corresponds to a zero error of (100X10- 9 X20xtOS)X100/10whlch Is 0.02%:01 FS. Note 11: The entire write pulse must occur within the valid data Interval for the specHied two tos, 1oH. and Is to apply. Nole 12: Typicals are at 25"C and represant mos1 Ukely parametric norm. tcH S5·106 Switching Waveform ILE. CS. V'H---"'\. 50% 50% V'H - - - - - - " \ . 50% ~ o CD DATA BITS loun loun (0) N I~FsmLEDTD J±'hLSB --------' TL/H/560B-2 Definition of Package Pinouts Control Signals (All control signals level actuated) CS: Chip Select (active low). The CS in combination with ILE will enable WR1. ILE: Input Latch Enable (active high). The ILE in combination with CS enables WR1. WR1: Write 1_ The active low WR1 is used to load the digital input data bits (01) into the input latch. The data in the input latch is latched when WR1 is high. To update the input latch-CS and WR1 must be low while ILE is high. WR2: Write 2 (active low). This signal, in combination with XFER, causes the S-bit data which is available in the input latch to transfer to the OAC register. XFER: Transfer control signal (active low). The XFER will enable WR2. VREF: Vee: GND: Reference Voltage Input. This input connects an external precision voltage source to the internal R2R ladder. VREF can be selected over the range of + 10 to -10V. This is also the analog voltage input for a 4-quadrant multiplying OAC application. Digital Supply Voltage. This is the power supply pin for the part. Vcc can be from + 5 to + 15VOC. Operation is optimum for + 15VOC. The pin 10 voltage' must be at the same ground potential as laUT1 and lauT2 for current switching applications. Any difference of potential (Vas pin 10) will result in a linearity change of Vas pin 10 3VREF For example, if VREF = 10V and pin 10 is 9mV offset from laUT1 and IOUT2 the linearity change will be 0.03%. Pin 3 can be offset ± 100mV with no linearity cha~ge, but the logic input threshold will shift. Other Pin Functions Dlo·DI7: Digital Inputs. 010 is the least significant bit (LSB) and 017 is the most significant bit (MSB). IOUT1: DAC Current Output 1. IOUT1 is a maximum for a digital code of all 1'S in the OAC register, and is zero for all O's in OAC register. IOUT2: DAC Current Output 2. IOUT2 is a constant minus IOUT1' or IOUT1 + IOUT2 = constant (I full scale for a fixed reference voltage). R'b: Feedback Resistor. The feedback resistor is provided on the IC chip for use as the shunt feedback resistor' for the external op amp which is used to provide an output voltage for the DAC. This on-chip resistor should always be used (not an external resistor) since it matches the resistors which are used in the onchip R-2R ladder and tracks these resistors over temperature. S5-107 ~ C") ~ ,-------------------------------------------------------------------------------------- g Linearity Error DIGITAL INPUT DIGITAL INPUT DIGITAL INPUT TlIH/560B-3 a) End point test after zero and fs adj. b) Best straight line c) Shifting fs adj. to pass best straight line test Definition of Terms Resolution: Resolution is directly related to the number of switches or bits within the DAC. For example, ,the DAC0830 has 28 or 256 steps and therefore has a-bit resolution. Linearity Error: Linearity Error Is the maximum deviation from a straight line passing through the endpoints of the DAC fransfer characteristic. It is measured after adjusting for zero and full-scale. Linearity error is a parameter intrinsic to the device and cannot be externally adjusted. National's linearity "end point test" (a) and the "best straight line" test (b,c) used by other suppliers are illustrated above. The "end point test" greatly simplifies the adjustment procedure by eliminating the need for multiple iterations of checking the linearity and then adjusting full scale until the linearity is met. The "end point test" guarantees that linearity is met after a Single full scale adjust. (One adjustment vs. multiple iterations of the adjustment.) The "end pOint test" uses a standard zero and F.S. adjustment procedure and is a much more stringent test for DAC linearity. Settling Time: Settling time is the time required from a code transition until the DAC output reaches within ± %LSB of the final output value. Full-scale settling time requires a zero to full-scale or full-scale to zero output change. Full-Scale Error: Full scale error is a measure of the output error between an ideal DAC and the actual device output. Ideally, for the DACOa30 series, full-scale is VREF -1 LSB. For VREF= 10V and unipolar operation, VFULL-SCALE= 10.0000V-39mV=9.961V. Full-scale error is adjuslJible to zero. Differential Nonlinearity: The difference between any two consecutive codes in the transfer curve from'the theoretical 1 LSB is differential nonlinearity. Monotonic: If the output of a DAC increases for increasing digital input code, then the DAC is monotonic. An a-bit DAC which is monotonic to a bits simply means that increasing digital input codes will produce an increasing analog output. Power Supply Sensitivity: Power supply sensitivity is a measure of the effect of power supply changes on the DAC full-scale output. r--------------------, '3 1 '4 01.0-":';:'t---1 18 (MSB) 01, 1'2 '5 OI,o-":':'t---1 '6 01,0--=1--1 0 MULTIPLYING O/A CONVERTER INPUT 01, 0---'-1---1 OREGISTERO I" IOUT1 0 01,0-""::'1---1 RIO (LSB) 01.0--'-1---1 I I ,91 foun a·BIT 8-81T 0 01,0-""::'1---1 VR£F 11* I I I 13 r---<>GNO ILE I I ,1 I I I II cs <>::~~) WII,o- Izo 21 '8 1 WR, O:~~==:::::[)---1 1 7 . I ·NOTE: WHEN [E= ",". a OUTPUTS FOLLOW 0 INPUTS; iffii 0 r---<> Vet I 1'0 J.!!-o GNO L ______~E~~ ~'::"O~A~ ~I~LA~H~:.... _ _ J ' TlIH/560B-4 FIGURE 1. DAC0830 Functional Diagram S 5-108 Typical Performance Characteristics Digital Input Threshold vs. Temperature r-r-rr-r-r-r--r-,--, 2.4 2.0 ~~~~+--+--+--+--+-1 2.0 2.4 g~~ > t- _t-.r-t-~~ 15Voe 1.6 "'" ......... 1.2 :! a lS 0.8 r- .... !:- 1--t--t--t-v-.:.cct-=_5fVo::.ctr--t~-fb""'l E I 0.1 1.6 I- 1.2 a -,....... ~:5'C TA= 125'C I--~ O.B 0.4 1-1-+-+-+--+--+-+--+-1 0.4 O~~~~~~~~~ 0 -55-35-15 5 25 45 65 85 105 125 TA. AMBIENT TEMPERATURE I'C) +0.025 0.000 Gain and Linearity Error Variation vs. Supply Voltage '"T"-r__ .....--'--=:-;---, ~ -0.05 :::: -0.100 13 l 11 5 10 15 Vcc. SUPPLY VOLTAGE IVue) VCC-12V. VIH=3V VCC=15Y. YIH=3V or 5V -55-35-15 5 25 45 65 B5 105.125 TA. AMBIENT TEMPERATURE I 'C) ' ...... -0.025 t - t - t - t - t - t - t - t - - H -0.05 1-+--+--+--+--+--+---+-+-1 Data Hold Time 250 I - + - - + - t - t - t - t - H - l 200 YyC'HC:35y~' - I - yVC,HC:3'2yY. f-+Ycc=5V. 12V.15V YIH=5V ;:; 150 ~ ;;;: , 100 ~ _VCC=15Y. _ YIH=3Y ~ -0.1251--+--t---j-t- TA=25'C- o 0 TA. AMBIENT TEMPERATURE I'C) !~ f--+--+--j-+---t--+~ ........ .. 0.025 -0.075 ~+--~hH-1C=i'5Vj'-0.1 ~~~~~~"-"-.L......I -55-35-15 5 25 45 65 B5 105125 ;: ~ 1--+--+-1--+---+-+---1 -0,075 I--+--+-~-+---+-+---I i -LINEARITY ERROR ... GAIN ERROR 0.05 Write Pulse Width .... ~'NEAR'TY ERROR ~ ffi ;;!; 5 10 15 VCC. SUPPLY VOLTAGE IV) ~ -0.0251-j--.l~ EJORI-j---j------I z §: ~ 13 i5 r-r-r-r-r-r-r--r-,--, 0.075 TL1,c ~ :: Gain and Linearity Error : Variation vs. Temperature Digital Input Threshold vs. Vee : oS ~ 50~~~~$=~~~~ I I \1 -55-35-15 5 25 45 65 B5 105125 TA. AMBIENT TEMPERATURE I'C) TL/H/560B-5 DAC0830 Series Application Hints .. These DAC's are the industry's first microprocessor com· patible, double·buffered B·bit multiplying D to A converters. Double·buffering allows the utmost application flexibility from a digital control point of view. This 20·pin device is also pin for pin compatible (with one exception) with the DAC1230, a 12·bit MICRO·DAC. In the event that a sys· tem's analog output resolution and accuracy must be up· graded, substituting the DAC1230 can be easily accom· plished. By tying address bit Ao to the ILE pin, a two·byte ftP write instruction (double precision) which automatically in· crements the address for the second byte write (starting with Ao= "1") can be used. This allows either an B·bit or the 12·bit part to be used with no hardware or software chang· es. For the simplest B·bit application, this pin should be tied to Vee (also see other uses in section 1.1). Analog signal control versatility is provided by a precision R· 2R ladder network which allows full 4·quadrant multiplica· tion of a wide range bipolar reference voltage by an applied digital word. system to be updated to their new analog output levels simultaneously via a common strobe signal. The timing requirements and logic level convention of the register control signals have been designed to minimize or eliminate external interfacing logiC when applied to most popular microprocessors and development systems. It is easy to think of these converters as B·bit "write·only" memo ory locations that provide an analog output quantity. All in· puts to these DAC's meet TTL voltage level specs and can also be driven directly with high voltage CMOS logic in non· microp'rocessor based systems. To prevent damage to the chip from static discharge, all unused digital inputs should be tied to Vee or ground. If any of the digital inputs are inadvertantly left floating, the DAC interprets the pin as a logic "F. - 1.0 DIGITAL CONSIDERATIONS A most unique characteristic of these DAC's is that the B·bit digital input byte is double·buffered. This means that the data must transfer through two independently controlled B· bit latching registers before being applied to the R·2R lad· der network to change the analog output. The addition of a second register allows two useful control features. First, any DAC in a system can simultaneously hold the current DAC data in one register (DAC register) and the next data word in the second register (input register) to allow fast updating of the DAC output on demand. Second, and probably more important, double·buffering allows any number of DAC's in a S5·109 1.1 Double-Buffered Operation Updating the analog output of these DAC's in a double·buff· ered manner is basically a two step or double write opera· tion. In a microprocessor system two unique system ad· dresses must be decoded, one for the input latch controlled by the CS pin and a second for the DAC latch which is controlled by the XFER line. If more than one DAC is being driven, Figure 2, the CS line of each DAC would typically be decoded individually, but all of the converters could share a common XFER address to allow simultaneous updating of any number of DAC's. The timing for this operation is shown, Figure 3. It is important to note that the analog outputs that will change after a simultaneous transfer are those from the DAC's whose input register had been modified prior to the XFER command. ~ r-----------------------------------------------------------------------------~ (I) ~ DAC0830 Series Application Hints (Continued) DAC 1 ---~~ ANALOG OUTPUT 1 """"-----..L~ANALDG OUTPUT 2 """"-----..L~ANALOG OUTPUT n SYSTEM Wii STROBE ) ________- - - - - - - ' "TIE TO lOGIC llF NOT NEEDED (SEE SEC. 1.1). FIGURE 2. Controlling Mutlple DACs OATABUS =-S/~~; C! m&~ \ \ ______ u / U (INPUT LATCH UPDATED mil \ ANALOG OUTPUT . "I . . . . . - - - - - ( O A C REGISTER LATCHED UPDATED n \ ILE=LOGIC "1" TL/H/5608-6 FIGURE 3 The ILE pin is an active high chip select which can be de· coded from the address bus as a qualifier for the normal CS signal generated during a write operation. This can be used to provide a higher degree of decoding unique control sig· nals for a particular DAC, and thereby create a more effi· clent addressing scheme. Another useful application of the ILE pin of each DAC in a multiple DAC system is to tie these inputs together and use this as a control line that can effectively "freeze" the out· puts of all the DAC's at their present value. Pulling this line low latches the input register and prevents new data from being written to the DAC. This can be particularly useful in multiprocessing systems to allow a processor other than the one controlling the DAC's to take over control of the data bus and control lines. If this second system were to use the same addresses as those decoded for DAC control (but for' a different purpose) the ILE function would prevent the DAC's from being erroneously altered. In a "Stand·Alone" system the control signals are generated by discrete logiC. In this case double-buffering can be controlled by simply taking CS and XFER to a logic "0", ILE to a logic "1" and pulling WRl low to load data to the input latch. Pulling WR2 low will then update the analog output. A logiC "1" on either of these lines will prevent the changing of the analog output. S 5-110 DAC0830 Series Application Hints (Continued) ~--~\~--------~/ vm --------\:-::=____ 1 -:-::1 ANALOG OUTPUT UPDATED DATA LATCHED TUH/5608-7 ILE=LOGIC "1"; WR2 and XFER GROUNDED FIGURE 4 1.2 Single-Buffered Operation In a microprocessor controlled system where maximum data throughout to the DAC is_of primary concern, or when only one DAC of several needs to be updated at a time, a single-buffer!ld configuration can be used. One of the two internal registers allows the data to flow through and the other register will serve as the data latch. Digital Signal feedthrough (see Section 1.5) is minimized if the input register is used as the data latch. Timing for this mode is shown in Rgure 4. be met or erroneous data can be latched. This hold time is defined as the length of time data must be held valid on the digital inputs after a qualified (via CS) WR strobe makes a low to high transition to latch the applied data. If the controlling device or system does not inherently meet these timing specs the DAC can be treated as a slow memory or peripheral and utilize a technique to extend the write strobe. A simple extension of the write time, by adding a wait state, can simultaneously hold the write strobe active and data valid on the bus to satiSfy the minimum WR pulsewidth. If this does not provide a sufficient data hold time at the end of the write cycle, a negative edge triggered oneshot can be included between the system write strobe and the WR pin of the DAC. This is illustrated in Figure 5 for an exemplary system which provides a 250ns WR strobe time with a data hold time of less than 10ns. The proper data set-up time prior to the latching edge (LO to HI tranSition) of the WR strobe, is insured if the WR pulsewidth is within spec and the data is valid on the bus for the duration of the DAC WR strobe. Single-buffering in a "stand-alone" system is achieved by strobing WR1 low to update the DAC with CS, WR2 and XFER grounded and ILE tied high. 1.3 Flow-Through Operation Though primarily designed to provide microprocessor interface compatibility, the MICRO-DAC's can easily be configured to allow the analog output to continuously reflect the state of an applied digital input. This is most useful in applications where the DAC is used in a continuous feedback control loop and is driven by a binary up-down counter, or in function generation circuits where a ROM is continuously providing DAC data: Simply grounding CS, WR1, WR2, and XFER and tying ILE high allows both internal registers to follow the applied digital inputs (flow-through) and directly affect the DAC analog output. 1.4 Control Signal Timing When interfacing these MICRO-DAC to any microprocessor, there are two important time relationships that must be considered to insure proper operation. The first is the minimum WR strobe pulse width which is specified as 900 ns for all valid operating conditions of supply voltage and ambient temperature, but typically a pulse width of only 180ns is adequate if VCc=15Voc. A second consideration is that the guaranteed minimum data hold time of 50ns should 1.5 Digital Signal Feedthrough When data is latched in the internal registers, but the digital inputs are changing state, a narrow spike of current may flow out of the current output terminals. This spike is caused by the rapid switching of internal logic gates that are responding to the input changes. There are several recommendations to minimize this effect. When latching data in the DAC, always use the input register as the latch. Second, reducing the Vcc supply for the DAC from + 15V to + 5V offers a factor of 5 improvement in the magnitude of the feedthrough, but at the expense of 'internal logic switching speed. Finally, increasing Cc (Figure 8) to a value consistent with the actual circuit bandwidth requirements can provide a substantial damping effect on any output spikes. - S5-111 ~ CW) CD ~ ,--------------------------------------------------------------------------------DAC0830 Series Application Hints (Continued) DATA BUS ~J~ ~~________D_A_m_~_Au_D___________~ WRITE ~W;:e ___. . . . WlI I- -+j ~ SYSTEM DATA HOLD TIME « I NORMAL ONE WAIT WIIITE STROBE~ STATE (250 ns) I 10ns) (250 ns) (OUTPUT OF - -........ ONE·SHOT) ~_ OAC Wii .. _I r---PULSE WIDTH~ (350 ns) ~ OAC DATA HOLD TIME (160ns) TLlH/5608-8 FIGURE 5. Accommodating a High Speed System 2.0 ANALOG CONSIDERATIONS The fundamental purpose of any D to A converter is 'to provide an accurate analog output quantity .which is representa· tive of the applied digital word. In the case of the DAcoa30, the output, IOUT1' is a current directly proportional to the product of the applied reference voltage and the digital input word. For application verSatility, a second output, IOUT2' is provided as a current directly proportional to the comple· ment of the digital Input. Basically: Figure 6. The MOS switches operate in the current mode with a small voltage drop across them and can therefore switch currents of either polarity. This is the basis for the 4· quadrant multiplying feature of this DAC. I - VREF x Digital Input. OUT1- 15 kn 256' I - VREF x255-Dlgitallnput 256 OUT2- 15 kn where the digital input is the decimal (base 10) equivalent of the applied a·bit binary word (0 to 255), VREF is the voltage at pin a and 15 kn is the nominal value of the internal resist· ance, R, of the R·2R ladder network (discussed in Section 2.1). . Several factors external to the DAC itself must be consid· ered to maintain analog accuracy and are covered in subsequent sections. 2.1 The Current SWitching R·2R Ladder The analog circuitry, Figure 6. consists of a silicon·chromi· um (SiCr or Si·chrome) thin film R·2R ladder which is deposited on the surface oxide of the monolithic chip. As a result; there are no parasitic diode problems with the ladder (as there may be with diffused reSiStors) so the reference volt· age, VREF, can range -10V to +10V even if Vee for the 'device is 5Voc. The digital input code to the DAC simply controls the posl· . tion of the SPDT current switches and steers the available ladder current to either IOUT1 or IOUT2 as determined by the logiC input level ("1" or "0") respectively, as shown in 2.2 BasiC Unipolar Output Voltage To maintain linearity of output current with changes in the applied digital code, it Is important that the voltages at both of the current output pins be as near ground potential (OVoc) as possible. Wrth VREF= +10V every millivolt ap. pearing at either IOUTl or IOUT2 will cause a 0.01 % linearity error. In most applications this output current is converted to a voltage by using an op amp as shown in Figure 7. The Inverting input of the op amp is a "virtual ground" creat· ed by the feedback from its output through the internal 15 \ kn resistor, Rib. All of the output current (determined by the digital input and the reference voltage) will flow through Rib to the output of the amplifier. Two·quadrant operation can be obtained by reversing the polarity of VREF thus causing IOUT1 to flow Into the DAC and be sourced from the output of the amplifier. The output voltage, In either case, is always equal to IOUTl X Rib and is the opposite polarity of the refer· ence Voltage. .The reference can be either a stable DC voltage source or an AC signal anywhere In the range from -10V to +10V. The DAC can be thought of as a digitally controlled attenua· tor:· the output voltage is always less than or equal to the applied reference voltage. The VREF terminal of the device presents a nominal impedance of 15 kn to ground to exter· nal circuitry. Always use the internal Rib resistor to create an output volt· age since this resistor matches (and tracks with tempera· ture) the value of the resistors used to generate the output current (lOUT1). S 5·112 DAC0830 Series Application Hints (Continued) VREF o-....-w\,-_"""'~_ ••••••• r--4JIf'v-....- - _ Rib ", .. '--T-...-t--....-t----i-+--"-1~---J..-c loun L - - -...---+-----_~--..J.-- ___o 10U12 FIGURE 6 DIGITAL INPUT Rib (INTERNAL) +VREF >-~ '!1=-2- - " " ' - ' - - - - - ' : . . . , 10 3 VREF +15V 1= ,-=- +ilS20k t--- YoUT =v..AX~ 10k =VMIN CODE (0) o • Only a single 255 TVH/5608-14 + 15V supply required • Non-interactive full-scale and zero code output adjustments • VMAX and VMIN must be,;: +5VDC ~nd ;,OV. 1 • Incremental Output Step= 256 (VMAX- VMIN)· 'VOUT=-~-' o" ;;....... ~~ l - i::;::: ""'" I I' AGAIN ERROR Vet = 15V. VREF = 5V OR Vec=12V. VREF=2,5V L1 -0.100 -55 -35-15 5 25 45 65 85 105 125 TA. AM81ENT TEMPERATURE ('C) TL/H/5608-15 FIGURE 16 FIGURE 17 Note: For these curves. VREF is the voltage applied to pin 11 (IOUT1) with pin 12 (lOUT:!! grounded. S 5-116 FIGURE 18 DAC0830 Series Application Hints (Continued) 2.8 Miscellaneous Application Hints These converters are CMOS products and reasonable care should be exercised in handling them to prevent catastroph· ic failures due to static discharge. Conversion accuracy is only as good as the applied reference voltage so providing a stable source over time and temperature changes is an important factor to consider. Overall noise reduction and reference stability is of particular concern when using the higher accuracy versions, the DAC0830 and DAC0831, or their advantages are wasted. 3.0 GENERAL APPLICATION IDEAS The connections for the control pins of the digital input registers are purposely omitted. Any of the control formats discussed in Section 1 of the accompanying text will work with any of the circuits shown. The method used depends on the overall system provisions and requirements. A "good" ground is most desirable. A single point ground distribution technique for analog signals and supply returns keeps other devices in a system from affecting the output of the DACs. During power-up supply voltage sequencing, the -15V (or -12V) supply of the op amp may appear first. This will cause the output of the op amp to bias near the negative supply potential. No harm is done to the DAC, however, as the on-chip 15 kO feedback resistor sufficiently limits the current flow from IOUTI when this lead is internally clamped to one diode drop below ground. The digital input code is referred to as D and represents the decimal equivalent value of the 8-bit binary input, for example: Binary Input· Pin 13 MSB 1 1 0 0 0 Careful circuit construction with minimization of lead lengths around the analog circuitry, is a primary concern. Good high frequency supply decoupling will aid in preventing inadvertant noise from appearing on the analog output. 1 0 0 0 0 Pln7 LSB 1 0 0 0 0 1 0 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 1 0 D Decimal Equivalent 1 0 0 0 0 255 128 16 2 0 Applications DAC Controlled Amplifier (Volume Control) CapaCitance Multiplier +15V +15V lD >=----.....-0 VOUT C, :!: CEOUIV -15V • lpF I vOUT =-V,N(256) --0-- TL/H/5608-16 • Ceaulv=c, ( 1 + 2~6) • When 0 = 0, the amplnier will go open loop and the output will saturate. • Maximum voltage across the equivalent capacItance is • Feedback impedance from the - input to the output varies from 15 kn to 00 as the input code changes from full·scale to zero. rmiled to Vo MAX (op amp) I 256 1+0 • C2 is used to improve seHling time of op amp. S5-117 • ~ C') co B t3 r------------------------------------------------------------------------------------------Applications (Continued) Variable fo. Variable Qo. Constant BW Bandpass Filter Rs liN eOUT TLlH/5608-17 [Ri5 o '/256. _ _ fa - 2".R,C' aa whereC, = C2 = o HO = 1 for RIN [Ri5 (2Ra + R1). '/256 Ra(K + 1)' 3d Rs C; K = 'R5and R, = R4 = b _ + Ra(K BW - 2".R,C(2Ra 1) + A') = R of DAC = 15k R, o Range of fo and a is '" 16 to 1 for circuit shown. The range can be extended to 255 to 1 by replacing R, with a second DACOB30 driven by the same digital input word. o Maximum fo X a product should be ,;: 200 kHz. DAC Controlled Function Generator +15V +15V 1 75k SYMMETRY;; TRIM -15Y WAYESHAPE/ TRIM 15k' -15V +15V 2k OAC0830 ., r- +15 U -15 SQUARE WAVE OUTPUT TL/H/5608-16 o DAC controls the frequency of sine, square. and triangle outputs. •f o = 256(20k)C for VOMAX = VOMIN of square wave output and R, = 3 R2. o 255 to 1 linear frequency range; oscillator stops with 0 = 0 • Trim symmetry and wave-shape for minimum sine wave distortion. 55·118 Applications (Continued) Two Terminal Floating 4 to 20 mA Current Loop Controller INPUT IN4001 lM334 21K1 500g lM3HD lM329D ~4mA"'DUT"20mA TLlH/5608-19 lOUT = VREF [1.. + RI _D_] 256Rfb [1+ &] R3 • DAC0830 linearly controls the current flow from the Input terminal to the output terminal to be 4 mA (lor D=O) to 19.94 mA (lor D=255). • Circu~ operates with a terminal voltage differential of lev to 55V. • P2 adiusts the magnitude of the output current and PI adjusts the zero to luli scale range of output current • Digital inputs can be supplied from a processor using opto isolators on each input or the DAC latches can flow-through (connect control lines to pins 3 and 1001 the DAC) and the input data can be set by SPST toggle switches to ground (pins 3 and 10). DAC Controlled Exponential Time Response SVflNAL V,NITIAL 10k ' " VflNAL , 10k VINITIAL - J V= z:S(VOUT - VIN) + ~:VIN \ T."TooANDe TLlH/5608-20 • Output responds exponentially to Input changes and automatically stops when VOUT=VIN • Output time constant Is dlrectiy proportional to the DAC input code and capacitorC '. Input voltage must be positive (See section 2.7) S 5-119 ~ r---------------------------------------------~~--------------------_. CD ('I ..- ~National ~ ~..- ('I ~ ~ Semiconductor DAC1265A, DAC1265 Hi-Speed 12-Bit D/A Converter with Reference General Description Features The DAC1265A and DAC1265 are fast 12-bit digital to analog converters with internal voltage reference. These DACs use 12 preCision high speed bipolar current steering switches, control amplifier, thin film resistor network, and buried zener voltage reference to obtain a high accuracy, very fast analog output current. The DAC1265A and DAC1265 have 10%-90% full-scale transition time under 35 ns and settle to less than 'h LSB in 200 ns. The buried zener reference has long-term stability and temperature drift characteristics comparable to the best discrete or separate IC references. These digital 'to analog converters are recommended for applications in CRT displays, precision instruments and data acquisition systems reqUiring throughput rates as high as 5 MHz for full range transitions. • Bipolar current output DAC and voltage reference • Fully differeritial, non-saturating precision current switch - ROUT and COUT do not change' with digital input code' • Internal buried zener reference - 10V±1% max • Precision thin film resistors for' use with external op amp for voltage out or as input resistors for a successive approximation AID converter • Superior replacement for 12-bit Of A converters of this type Key Specifications • Resolution and Monotonicity 12 Bits • Unearity 12 Bits (Guaranteed over temperature) • Output Current Settling Time 400 ns max to 0.01 % • Gain Tempco ±15 ppml'C max • Power Supply Sensitivity ±10 ppm of FSf% VSUPPLY Block and Connection Diagrams PWR REFERENCE 4 OUT +Vs UND -Vs '1_" t lD.DV REFERENCE Ne NC ' I • "--r.=:..--.:-"'T"--.:,,;..---r--_~----Q 10VRANGE 20V RANGE REFERENCE & INPUT ANALOG 5 GNU BIPOLAR • II.B5' 2Dt • CURRENT OUTPUT (SUMMING JUNCTION' ...-----7"-<0 1.95. OFFSET 24 23 22 21 20 19 I. 17 11 15 14 13 tLSBI (MSHj TL/H/5242-1 Dual-In-Line Package See Ordering Information NS Package J24A . TLlH/5242-2 S 5-120 · Absolute Maximum Ratings Supply Voltage (V+ and V-) Current Output (Pin 9) Voltage Logic Input Voltage Reference Input Voltage (Pin 6) Analog GND to Power GND ±18V -SV,12V Power Dissipation (Note 1) -1V,7V ±12V V- to +24V 10V Range 20VRange Continuous Operating Temperature Range DAC1265AJ, DAC1265W DAC1265ACJ,DAC1265LCJ Storage Temperature Range ±12V ±1V ±12V Bipolar Offset 1000mW Short-Circuit Duration (Pins 4 to 12) TMINS;TAS; TMAX - 55·C to + 125·C O·Cto +70·C -65·Cto + 150·C 150·C Maximum Junction Temperature Lead Temperature (Soldering, 10 seconds) soo·c Electrical Characteristics VSUPPLY= ± 15V ± 5% unless otherwise noted. Boldface limits apply over temperature, TMINs;TAS;TMAX' For all other limits TA=25·C. DAC1265A Parameter Conditions See Note Typ (Note 11) Tested Limit (Note 2) DAC1265 Design Tested Design Limit Typ Limit Limit (Note 3) (Note 11) (Note 2). (Note 3) Units CONVERTER CHARACTERISTICS Resolution Unearity Error Max I 12 Zero and Full-Scale Adjusted Zero and Full-Scale Adjusted Monotonicity AJ and W Suffix Parts ACJ and LCJ Suffix Parts Full-Scale (Gain) Error Max ±Ys ±% ±% ±% ±% ±% ±% ±% ±% ±% ±y. ±% \ R2= 50n in Figure 1 Offset Error Max Unipolar (Figure 1 Pin 8 Open) All Bits OFF, Bipolar (R1 and R2 = 50n in Logic "a.. Figure2j Zero Error Max MSBON Bipolar (R1 and R2=50n in Rgure2j Gain Adjustment Range Min R2 = 50n ± 50n in Figure 1 Bipolar Offset Adjustment Range Min R1 =50n± 50n and R2=50n in Rgure2 Full-Scale (Gain) Using the AJ and W Suffix Temperature Internal ACJ and LCJ Suffix Coefficients Max Reference 12 12 ±0.1 ±0.20 ±0.1 ±0.20 6 ±0.Q1 ±0.05 ±0.Q1 ±0.05 7 ±0.05 ±0.1 ±0.05 ±0.15 8 ±0.05 ±0.1 ±0.05 ±0.15 9 10 ±0.2 ±0.2 ±0.15 ±0.15 1 ACJ and LCJ Suffix 1 Bipolar Zero Temperature Coefficients Max AJ and W Suffix 5 ACJ and LCJ Suffix 5 7.5 S 5-121 15 15 10 AJ and W Suffix Exclusive of Offset and Range Rs 12 12 12 5 Unipolar Offset Temperature Coefficients Max Output Resistance Bits LSB AJ and W Suffix Parts ACJ and LCJ Suffix Parts Differential Non-Unearity Max 12 4 20 2 1 1 10 5 10 6to 10 5 7.5 % FullScale ppml"C 30 15 2 Bits 12 50 2 2 10 10 6to 10 kn Electrical Characteristics {Continued) VSUPPLY = over temperature, TMIN s: TA s: TMAl(. For all otherlimitsTA = ± 15V ± 5% 25°C. ~nless otherwise noted. Boldface limits apply DAC1265A Parameter Current Output Conditions See Note Unipolar Bipolar DAC1265 Tested Design Tested Design Typ Limit Limit Typ Limit Limit (Nole 11) (Note 2) (Note 3) (Note 11) (Nole2) (Note 3) -2 -1.6to -2.4 -2 -1.6to -2.4 ±1.0 ±0.8to ±1.2 ±1.0 ±0.8to ±1.2 Units mA Output Capacitance 25 25 pF Output Noise (FS, 10 Hz to 100 kHz with Internal 10VRange) Reference 40 40 p.Vrms TypOutput Voltage Ranges ±2.5, ±5, ±10,Ot05,Ot010 Using Internal Offset and Range Rs Reference Input Resistance 20.8 151025 Output Compliance Voltage V 20.8 151025 -1.510 10 kO -1.510 10 V REFERENCE OUTPUT CHARACTERISTICS Reference Voltage Temperature Coefficient ~ IREF=1.5 mA 9.90 10.00 10.10 Max ±12 3.0 0.05 fo.= 1 kHz, 0.5 mAS: IREFS:3 mA V 9.90 10.10 ±8 Reference Oulput Current Min Output Resistance Max 10.00 1.0 0.05 ppml"C. 3.0 mA 1.0 0 DIGITAL AND DC CHARACTERISTICS Logic High Bit ON AJ and W Suffix ACJ and LCJ Suffix Logic Low Max BilOFF AJ and W Suffix ACJ and LCJ Suffix Logic Input Voltage I Logic Input Current Max Logic High Logic Low 2105.5 1.9105.5 2t05.5 2105.5 1.9to 5.5 2105.5 0.8 1.0 AJ and W Suffix 0.8 ACJ and LCJ Suffix 150 150 300 280 300 150 150 AJ and W Suffix ACJ and LCJ Suffix 45 45 100 90 100 45. 45 0.8 1.0 0.8 300 280 300 100 90 100 V p.A Power SUPPlyl1 + Current Max 11_ V+ Supply=15V±10% 3 5 3 5 V- Supply= -15V±10% -12 -18 -12 -18 Power Dissipation Max VSUPPLY= ±15V 225 345 225 345 mW ppmofFSI %VSUPPLY Power Supply Sensitivity Max V+Supply=15V±10% 10 ±3 ±10 ±3 ±10 V- Supply=-15V±10% 10 ±15 ±25 ±15 ±25 S 5-122 mA Electrical Characteristics (Continued) VSUPPLY= ± 15V ± 5% unless otherwise noted. Boldface limits apply over temperature, T MIN::;;TA::;;TMAX. For all other limits TA = 25'C. DAC1265A Parameter See Note Conditions DAC1265 Design Limit (Note 3) Typ (Note 11) 200 400 Typ (Note 11) Tested Limit (Note 2) Tested Limit (Note 2) Design Limit (Note 3) Units 200 400 ns ns AC CHARACTERISTICS Settling Time Max FSR Change Full-Scale Transition Max 10% to 90% Rise Time Plus Delay Time 15 30 15 30 90% to 10% Fall TIme Plus Delay Time 30 50 30 50 Note 1: The typical 6JA of the 24·pin package is 80' C/W. Note 2: Guaranteed and 100% production lested. Note 3: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels. Note 4: Linearity error VOUT-VOFFSET-(DXVLSS) h V V were LSB LSB Note 5: Percent gain error for 10V range VFS ~~~;FSET and D is the digit~1 input (0 to 4095) which produced VOUT. (VFS - VOFFSET~ ~~4095/4096)1 OV Xl 00. Note 6: Unipolar offset error for 10V range~(VmJT/l0V)Xl00 in percent of full·scale. Note 7: Bipolar offset error for 10V range Note 8: Bipolar zero error for 10V Note 9: Gain error tempco range~ VOUT-(-5V) 10V XI 00 in parcent cf full·scale. (VOUT/l OV)X 100 in percent of full·scale. (VFS-VOFFSET)at (TMAX orTMIN)-(VFS-VOFFSET) at 25'C x t06 in ppml'C. 10V range x (TMAxorTMIN -25'C) Note 10: Power supply sensitivity for 10V range ~ 106 X (VFS - VOFFSET) at (16.5V or -1 ~.~~): ~;:. - VOFFSET) at (13.5V or -16.5V) in ppm of FS/%VS. The opposite supply Is held at - t 5V or + 15V respectively. Note 11: Typicals are at 25'C and represent most likely parametric norm. Functional Description and Applications 1.0 BUFFERED VOLTAGE OUTPUT CONNECTION The standard current-to-voltage conversion connections using an operational amplifier are shown here with the preferred trimming techniques. If a low offset operational amplifier (LF411 A) is used, excellent performance can be obtained in many situations without trimming (an op amp with less than 0.5 mV maximum offset voltage should be used to keep offset errors below 'h LSB). Unipolar zero will typically be within ± 'h LSB (plus op amp offset), and if a 500. fixed resistor is substituted for the 1000. trimmer (R2, Figure 1), full-scale accuracy will be within 0.1 % (0.20% maximum). Substituting a 500. resistor for the 1000. bipolar offset trimmer (R1, Figure 2) will give a bipolar zero error typically within ±2 LSB (0.05%). Step 2-Gain Adjust Turn all bits ON and adjust 1000. gain trimmer, R2, until the output is 9.9976V (full-scale adjusted to 1 LSB less than nominal full-scale of 10.000V). If a 10.2375V full-scale is desired (exactly 2.5 mV fbit), insert a 1200. resistor in series with the gain resistor at pin 10 to the op amp output. 1.2 Bipolar Configuration (Figure 2) This configuration will provide a bipolar output voltage from - 5.000V to 4.9976V, with positive full-scale occurring with all bits ON (all 1s). Step 1-offset Adjust Turn OFF all bits. Adjust 1000. offset trimmer, R1, to give - 5.000V output. Step 2-Gain Adjust Turn ON all bits. Adjust 1000. gain trimmer, R2, to give a reading of 4.9976V. 1.1 Unipolar Configuration (Figure 1) This configuration will provide a unipolar OV to 9.9976V output range. Please note that it is not necessary to trim the op amp to obtain full accuracy at room temperature. In most bipolar situations, an op amp trim is unnecessary unless the untrimmed offset drift of the op amp is excessive. Bipolar zero error (MSB bit ON) is not adjusted separately and is typically < ±0.05% of FS after offset and gain adjust. Step 1-offset Adjust (Zero) Turn all bits OFF and adjust zero trimmer, R1, until the output reads O.OOOV (1 LSB=2.44 mV). In most cases this trim is not needed. 55-123 • Functional Description and Applications (Continued) 15V lOOk RI SOk 100 15V REf OUT -15V +VS ":' BIPOLAR Off 4 11 R2 100 OACI265A OAC\Z65 1.95k 2DV RANGE 5k 10 lU5k 5k REf IN - OAC OUTPUT DV TO lDV 10 ak 'OUT =4 x 'REF' CODE CODE INPUT 7 -Vs 13 PWR GNO' 12 M S B - - - - - - - - - - LSB -15V ·Power and analog ground must have a common current return path. See section 4.0 for proper connections.' . TL/H/5242-3 FIGURE 1. OV to 10V Unipolar Voltage Output HI IIIG BIPOLAR Off r-__j.:'.:,102DV RANGE RZ IOU OACI265A DACI266 lU5k REf IN 5k 1.15k - IREf D.SmA 5k OUTPUT -5VTO 5V Ik 'OUT' 4 x 'REF x CODE 12 13 PWRGND* -Vs -15V ~B--------------~ LSI ·Power and analog ground must have a common current retum path. See section 4.0 for proper connections. TUH/5242-5 FIGURE 2. ± 5V Bipolar Voltage Output S 5-124 Functional Description and Applications (Continued) 1.3 Other Voltage Ranges (Figure 3) 3.0 DIGITAL INPUT The DAC1265A and DAC1265 use a standard positive true straight binary code for unipolar outputs (all 1s give fullscale output), and an offset binary code for bipolar output ranges. In the bipolar mode, with all Os on the inputs, the output will go to negative full-scale; with 100...00 (only the MSB on), the output will be O.OOV; with all 1s, the output will go to positive full-scale. The DAC1265A and DAC1265 car] also be easily configured for a unipolar OV to 5V range or ± 2.5V and ± 10V bipolar ranges by using the additional 5k application resistor provided at the 20V range R terminal, pin 11. For a 5V range (OV to 5V or ± 2.5V), the two 5k resistors are used in parallel by shorting pin 11 to pin 9 and connecting pin 10 to the op amp output and the bipolar offset either left open for unipolar or connected through a 100n pot to the REF OUT for the bipolar range. For the ± 10V range use the 5k resistors in series by connecting only pin 11 to the op amp output and connecting the bipolar offset as shown. The ± 1OV option is shown in Figure 3. The threshold of the digital input circuitry is set at 1.4V and does not vary with supply voltage: The input lines can interface with any type of 5V logiC, TTLlDTL or CMOS, and have sufficiently low input currents to interface easily with unbuffered CMOS logiC. The configuration of the input circuit is shown in Figure 4. The input line can be modeled as a 30 kn resistance connected to a -0.7V rail. 2.0 INTERNAL/EXTERNAL REFERENCE USE The performance of the DAC1265A and DAC1265 is specified with the internal reference driving the DAC since all trimming and testing (especially for full-scale and bipolar) is done in this configuration. DIGITAL INPUTS (PINS 13 TO 24) T. The internal reference has sufficient buffering to drive external circuitry in addition to the reference currents required for the DAC (typically 0.5 mA to REF IN and 1.0 mA to BIPOLAR OFFSET, if used). A minimum of 1.5 mA is available for driving external circuits. The reference is typically trimmed to ±0.2%, then tested and guaranteed to ± 1.0% maximum error. The temperature coefficient is comparable to that of the full-scale TC for a particular grade. ' _ - 5pF POWER GROUND 30k . . . - - - . -a.7V TO LOGIC' TLlH/5242-6 FIGURE 4. Equivalent Digital Input Circuit 15V R1 +vs 100 BIPOLAR OFF 11 20V RANGE R2 100 OAC1265A 5k 9,95k DAC12&S 19.95k 10 - IREF O.SmA IOV RANGE' 3 pF Sk DAC - OUTPUT -IOV TO 10V 10 8k lOUT'" 4 x IREF x CODE 12 PWR GND* -VS M S B - - - - - - - - , o__ LSB -15V "'Power and analog ground must have a common current return path. See section 4.0 for proper connections. TL/H/5242-4 FIGURE 3. ± 10V Voltage Output S 5-125 Functional Description and Applications (Continued) tion or breakdown which results in non-linear performance. Compliance limits are not affected by the positive power supply, but are a function of output current and negative supply. 4.0 APPLICATION OF ANALOG AND POWER GROUNDS The DAC1265A and DAC1265 bring out separate analog and power grounds to allow optimum connections for low noise and high speed performance. The two ground lines can be separated by up to 200 mV without any loss in performance. There may be some loss in linearity beyond that level. If these DACs are to be used in a system in which the two grounds will be ultimately connected at some distance from the device, it is recommended that parallel back-toback diodes be connected between the ground lines near the device to prevent a fault condition. 6.0 DIRECT UNBUFFERED VOLTAGE OUTPUT FOR CA· BLEDRIVING The wide compliance range allows direct current-to-voltage conversion With just an output resistor. Figure 5 shows a connection using the gain and bipolar output resistors to give a ± 1.60V bipolar swing. In this situation, the digital code is complementary binary. Other combinations of internal and external output resistors (Rx> can be used to scale to alternate voltage ranges. simply by appropriately scaling the 0 mA.to - 2 mA unipolar output current and using the 10.0V reference voltage for bipolar offset. For example, setting Rx=2.67. kO gives a ± 1V range with a 1 kO equivalent output impedance. This connection is especially useful for directly driving a long cable at high speed. Using a 500 resistor for Rx would allow interface to a 500 cable with a ± 50 mV full-scale SWing. The analog ground at pin 5 is the ground reference point for the internal reference and is thus the "high quality" ground; it should be connected directly to the analog reference pOint of the system. The power ground at pin 12 can be connected to the most convenient ground reference point; analog power return is preferred, but digital ground is acceptable. If power ground contains high frequency noise beyond 200 mV, this noise may feed through the converter, so that some caution will be required in applying these grounds. 5.0 OUTPUT VOLTAGE COMPLIANCE 7.0 HIGH SPEED 12·BIT AID CONVERTERS The fast settling characteristics of the DAC1265A and DAC1265 make them' ideal for high speed successive approximation AID converters. The internal reference and trimmed application resistors allow a 12-bit converter system to be constructed with a minimum parts count. Shown in Figure 6 is a configuration using standard components; this system completes a full 12-bit conversion in 10 ,,"S unipolar or bipolar. This converter will be accurate to ± % LSB of 12 bits and have a typical gain TC of 10 ppml"C. The DAC1265A and DAC1265 have a typical output compliance range from ·-2V to 10V. The current-steering output stages will be unaffected by changes in the output terminal voltage over that range. However, there is an equivalent output impedance of Ok in parallel with 25 pF at the output terminal which produces an equivalent error current if the voltage deviates from power ground. This is a linear effect which'does not change with input code. Operation beyond the compliance limits may cause either output stage satura- 50 +vs REF OUT BIPOLAR OFF 4 11 ZOV RANGE 100 DAC1Z&5A DAC1Z&5 5k 9S5k 10 10V RANGE 19.95k ":' 5k DAC - DAC OUT ID Bk lOUT =4 x IREfX CODE CODE INPUT IZ 24 PWR GND -VS M S B - - - - - - -...... LSB· TLlH/5242-7 FIGURE S. Unbuffered Bipolar Voltage Output S 5-126 Functional Description and Applications (Continued) In the unipolar mode, the system range is OV to 9.9976V, with each bit having a value of 2.44 mV. For true conversion accuracy, an AID converter should be trimmed so that a given bit code output results from input levels from Yz LSB below to Yz LSB above the exact voltage which that code represents. Therefore, the converter zero point should be trimmed with an input voltage of 1.22 mV; trim R1 until the LSB just begins to appear in the output code (all other bits "0"). For full-scale, use an input voltage of 9.9963V (10V-1 LSB- Yz LSB); then trim R2 until the LSB just begins to appear (all other bits "1"). the pretrimmed application resistors are sufficiently accurate that extemal trimmers will be unnecessary, especially in situations requiring less than full 12-bit ±Yz LSB accuracy. For fastest operation, the impedance at the comparator summing node must be minimized. However, lowering,the impedance will reduce the voltage signal to the comparator (at an equivalent impedance at the summing node of 1 kn, 1 LSB=0.5 mV), to the point that comparator performance will be sacrificed. The contribution to this impedance from the DAC will vary with the input configuration (Figure 6, Input Ranges Table). The bipolar signal range is - 5.0V to 4.9976V. Bipolar offset trimming is done by applying a -4.9988V input signal and trimming R3 for the LSB transition (all other bits "0"). FUll-scale is set by applying 4.9963V and trimming R2 for the LSB transition (all other bits "1"). In many applications, To prevent dynamic errors, the input Signal should have a low dynamic source impedance, such as that ofthe LF411A op amp. 15V R3 lUU BIPOLAR UNIPOLAR 'OIIk 8t (UNIPOLAR) 51111 lDO -15V BIPOLAR OFF ':" 11 : } ANALOG INPUTS zav RANGE RZ lUO 5. un 15V la 5V tOY RANGE 5. - DAC Ik 10 'OUT·4. 'REF. CODE CODE INPUT • LSB 13 11 DATA IN 14 mIlT CLDCK TLlH/5242-8 INPUT RANGES Unipolar 0105 Bipolar ±2.5 DIDIO 01020 ±5 ±IO FIGURE 6. Fast PreCision Analog to Digital Converter S5-127 Connect Input to A BloDACOUT InpotloA Input to B Equlv. DACZoUT 1.60kO 2.35kO a.08kO U) r-------------------------------------------------------------------------------~ ....~ Definition of Terms :c Digital Inputs: The OAC1265A and OAC1265 accept digital input codes in binary format and may be user connected for anyone of three binary codes: straight binary. two's comple-ment. or offset binary. ~ O U) ~ .... ~ Digital Input MSBLSB Analog Output Straight Binary Offset Binary -FS (Full-Scale) 000 .. 000 zero zero-1 LSB 011 •.. 111 %FS-1 LSB 100 .. 000 zero %FS 111 .•. 111 +FS":1 LSB +FS-1 LSB Two's Complement' zero +FS-1 LSB -FS zero-1 LSB ·Invert Mse With extemallnverter to obtain Two's Complement coding Unearity Error: Linearity error of a OfA converter 'is an important measure of its accuracy. It describes the deviation from an ideal straight line transfer curve drawn between zero (all bits OFF) and full-scale (all bits ON). Differential Non-Linearity: For a OfA conv!'!rter. it is the difference between the actual output voltage change and the ideal (1 LSB) voltage change for a one-bit change in code. A differential, non-linearity of ± 1 LSB or less guarantees monotonicity; i.e.• the output always increases and never decreases for an increasing input. It is guaranteed by testing the major carry transitions. i.e.. 100...000 to 011...111. etc. Settling Time: Settling time is the time required for the out- ' put to settle to within the specified error band for any input code transition. It is usually specified for a full-scale or major carry transition. Gain Tempco: The change in full-scale analog output over the specified temperature range expressed in parts per million of full-scale per 'C (ppm of FSI"C). Gain error is measured with respect to 25'C at high (TMAX> and low (TMIN) temperatures. Gain tempco is calculated for both high (TMAX-25'C) and low (25'C-TMIN) ranges by dividing the gain error by the respective change in temperature. The specification is the iarger of the two representing worstcase drift. Offset Tempco: The change in analog output with all bits OFF over the specified temperature range expressed in parts per million of full-scale per 'C (ppm of FSf·C). Offset error is measured with respect to 25"C at high (TMAxl and low (TMIN) temperatures. Offset tempco is calculated for both high (TMAX-25'C) and low (25'C-TMIN) ranges by dividing the offset error by the respective change in temperature. The specification given is the larger of the two. representing worst-case drift. Power Supply Sensitivity: Power supply sensitivity is a measure of the change in gain and offset of the 01 A converter resulting from a change in -i5V or + 15V supplies. It is specified under OC conditions and expressed as parts per million of full-scale per percent of change in power supply (ppm of FSfO/O). Ordering Information Temperature Range Linearity Error Over Temperature O'C to 70"C -55'C to + 125'C ± % Bit OAC1265ACJ OAC1265AJ 1--±-':y.c::4:..B-it--t--O-A-C-1-26-5-L-CJ---f-----O-A-C-1-2-6-5-LJ--,---1 S 5-128 . ~National ~ Semiconductor DAC1266A, DAC1266 Hi-Speed 12-Bit D/A Converter General Description • Precision thin film resistors for use with external op amp for voltage out or as input resistors for a successive approximate AID converter • Superior replacement for 12-bit 01 A converters of this type The DAC1266A and DAC1266 are fast 12-bit digital to analog converters. These DACs use 12 precision high speed bipolar current steering switches, control amplifier, and a thin film resistor network to obtain a high accuracy, very fast analog output current. The DAC1266A and DAC1266 have 10%-90% full-scale transition time under 30 ns and settle to less than % LSB in 200 ns. These digital to analog converters are recommended for applications in CRT displays, precision instruments and data acquisition systems requiring throughput rates as high as 5 MHz for full range transitions. Key Specifications • Resolution and Monotonicity 12 Bits • Linearity 12 Bits (Guaranteed over temperature) • Output Current Settling Time 400 ns max to 0.D1 % • Full-Scale Transition Time (10%-90%) 30 ns • Power Supply Sensitivity ±15 ppm of FSI% VSUPPLY Features • Bipolar current output DAC • Fully differential, non-saturating precision current switch - ROUT and COUT do not change with digital input code Block and Connection Diagrams -Y, 1Z AMPSUMM, •• JUNCTION & 1 Ne I o Ne Ne o o , r z ,. o·---r===:t-__--,;-____.,-_......J-----O REFE~:;:; 05___+,,'I"'J"'510-+_---==~ 'OY RANGE 2UVRANGE lZ·iJIT D/A ANALOO 03 _ _ _+,,2110"""_-1 COMMON +"."'.,,""____+ _____1-1 BIPOLAR 07 _ _ _ OFFSET Z4 23 ZZ 21 ZI ,. ,. 11 18 11 14 13 (MSal tLSB) Dual-In-Line Package ANALOG GROUIID 3 AMPSUMIIIINO JUNCTiON REFERENCE IN 5 BIPOLAR DFFsrr ·7 See Ordering Information NS Package J24A lOUT (-2 mA FSJ 9 2DVRANIJE If POWER GROUND 12 TUH/S068-1 Top View S5-129 Absolute Maximum Ratings Supply Voltage (V-) Current Output (Pin 9) Voltage Logic Input Voltage OVto -18V -3V,12V -1V,7V Reference Input Voltage (Pin 5) Analog GND to Power GND Bipolar Offset 10VRange Power Dissipation (Note 1) 1000mW ±12V Operating Temperature Range DAC1266AJ, DAC1266LJ DAC1266ACJ, DAC1266LCJ ±1V ±12V ±12V Storage Temperature Range Maximum Junction Temperature Lead Temp. (Soldering, 10 sec.) TMIN~TA~TMAX - 55·C to + 125·C OOCto +70·C -65·Cto + 1500C 1500C 300·C V- to +24V 20VRange Electrical Characteristics VSUPPLy= -15V ± 5% and VREF = 1O.OOOV unless otherwise noted. Boldface Its apply over temperature, TMIN ~TA ~TMAX. For all other limits TA = 25·C. DAC1266A Parameter Conditions See Note Typ II~- DAC1266 Tested Design Limit Limit (Note 2) (Note 3) Typ Tested Design Limit Limit (Note 2) (Note 3) Units CONVERTER CHARACTERISTICS 12 Resolution Unearity Error Max Zero and Full-Scale Adjusted AJ and LJ SuffIX Parts ACJ and LCJ Suffix Parts Differential Non-Unearity Max Monotonicity 12 LSB ±Ys ±% ±% ±% ±% , ±% ±% ±% ±% ±3,4 ±% . Zero and Full-Scale Adjusted AJ and .LJ Suffix Parts ACJ and LCJ Suffix Parts 12 12 :1;% 12 12 12 Full-Scale (Gain) Error Max R2 = 500 in ·Agure 1 5 Offset Error Max All Bits OFF, Logic"O" Unipolar (Agure 1 Pin 7 Open) Bipolar (R1 and R2 = 500 in Figure 2) Zero Error Max MSBON' Bipolar (A1 and R2 = 500 in Figure2) Gain Adjustment Range Min R2=500±50a in Agure 1 ±0.2 ±0.2 Bipolar Offset Adjustment Range Min R1 =500±500 and R2=500 in Figure 2 ±0.15 ±0.15 Full-Scale (Gain) Temperature Coefficients Max Bits 4 . AJ and LJ Suffix ACJ and LCJ Suffix ±0.1 ±0.20 6 ±0.01 ±0.05 ±0.01 ±0.05 7 ±0.05 ±0.1 ±0.05 ±0.15 8 ±0.05 ±0.1 ±0.05 ±0.15 9 1 1 3 ±0.1 Bits 12 ±0.20 5 5 10 3 1 1 2 2 5 5 10 10 % FullScale ppm/·C 10 Unipolar Offset Temperature Coefficients Max AJ and LJ Suffix ACJ and LCJ Suffix' 1 1 2 Bipolar Zero Temperature Coefficients Max AJ and LJ Suffix ACJ and LCJ Suffix 5 5 10 Output Resistance Exclusive of Offset and Range Rs 7.5 6to 10 7.5 6to 10 kO Current Output Unipolar -2 -1.6to -2.4 -2 -1.6to -2.4 mA Bipolar ±1.0 ±0.8 to ±1.2 ±1.0 ±0.8to ±1.2 55-130 2 10 Electrical Characteristics (Continued) VSUPPLY = -15V ± 5% and VREF = 10.000V unless otherwise noted. Boldface limits apply over temperature, T MIN ~T A ~TMAX. For all other limits T A = 25°C. DAC1266A Parameter Conditions Output Capacitance DAC1266 Tested Design Limit Limit Typ (Note 2) (Note 3) , See Note Typ 25 Using Internal Offset and Range Rs TypOutput Voltage Ranges Units pF 25 ±2.5, ±5, ± 10, 0 to 5, 0 to 10 , Reference Input Resistance V 20.8 15to 25 20.8 15 to 25 Output Compliance Voltage Tested Design Limit Limit (N~te 2) (Note 3) kO -1.5to 10 -1.5to 10 V 2to 5.5 1.9 to 5.5 2to 5.5 2t05.5 1.9to 5.5 2t05.5 V , DIGITAL AND DC CHARACTERISTICS Logic High Bit ON AJ and LJ Suffix ACJ and LCJ Suffix Logie Low Max Bit OFF AJ and W Suffix ACJ and LCJ Suffix Logic High AJ and W Suffix ACJ and LCJ Sufix 150 150 300 280 AJ and W Suffix ACJ and LCJ Suffix 45 45 100 90 Logic Input Voltage I Logic Input Current Max Logic Low 0.8 1.0 0.8 1.0 0.8 300 150 150 300 280 300 100 45 45 100 90 100 0.8 /LA Power Supply Current Max V- Supply= -15V± 10% -12 -18 ...,.12 -18 mA Power Dissipation Max V- Supply= -15V 180 270 180 270 mW Power Supply Sensitivity Max V- Supply= -12V±5% 10 ±15 ±25 ±15 ±25 ppmofFSI V- Supply= -15V±10% 10 ±15 ±25 ±15 ±25 ~. VSUPPLY AC CHARACTERISTICS Settling Time Max Full-scale Transition Max FSRChange 200 400 30 15 30 50 30 50 200 400 Delay Plus 10% to 90% Rise Time 15 Delay Plus 90% to 10% Fall Time 30 Nale 1: The typical OJA of the 24-pin package Is 80" C/W. Nale 2: Guaranteed and 100% production tested. Nale 3: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels. Nate 4: linearity error = VOUT - VOFF~cr LSB (0 x VLSB) where VLSB = VFS - VOFFScr and 0 Is the digital input (0 to 4095) which produced VOUT' 4095 , Nale 5: Percent gain error for 10V range = (VFS - VOFFScr) - (4095/4096)VREF x 100. VAEF Nale 6: Unipolar offset error for 10V range = (VOUTIVAEF) x 100 in percent of full·seale. Nale 7: Bipolar offset error for 10V range = VOUT - (-VAEF/2) X 100 in percent of full·scale. , , VAEF Nale 8: Bipolar zero error for 10V range = (VOUTIVAEF) x 100 In percent of full·scale. Nate 9: Gain error tampeo = (VFS - VOFFScr) at (TMAXarTMIW - (VFS - VOFFScr) at 25"C x 106 in ppmrC. 10V range X (TMAX or TMIN - 2S"C) Nate 10: Power supply sensitivity for 10V range = 106 X (VFS - VOFFScr)at (-13.5V) - (VFS - VOFFscr) at (-16.SV) in ppm of FS/% Vs. VAEFX 20% S 5-131 ns ns Functional Description and Applications 1.2 Bipolar Configuration (Figure 2) This configuration will provide a bipolar output voltage from -5.000V to 4.9976V, with positive full-scale occurring with all bits ON (all 1s). 1.0 BUFFEFIED VOLTAGE OUTPUT CONNECTION The standard current-to-voltage conversion connections using an operational amplifier are shown here with the preferred trimming techniques. If a low offset operational ampli.fier (LF411A) is used, excellent performance can be obtained in many situations without trimming (an op amp with less than 0.5 mV maximum offset voltage should be used to keep offset errors below % LSB). Unipolar zero will typically be within ± % LSB (plus op amp offset), and if a 500 fixed resistor is substituted for the 1000 trimmer (R2, Figure 1), full-scale accuracy will be within 0.1 % (0.20% maximum). Substituting a 500 resistor for the 1000 bipolar offset trimmer (Rl, Rgure 2) will give a bipolar zero error typically within ±2 LSB (0.05%). Step l-offset Ad/ust Turn OFF all bits. Adjust 1000 offset trimmer, Rl, to give -5.000Voutput. Step 2-Galn Ad/ust Turn ON all bits. Adjust 1000 gain trimmer, R2, to give a reading of 4.9976V. Please note that it is not necessary to trim the op amp to obtain full accuracy at room temperature. In most bipolar situations, an op amp trim is unnecessary unless the untrimmed offset drift of the.op amp is excessive. Bipolar zero error (MSB bit ON) is not adjusted separately and is typically < ±0.05% of FS after offset and gain adjust. 1.1 Unipolar Configuration (Figure 1) This configuration will provide a unipolar OV to 9.9976V output range. 1.3 Other Voltage Ranges (Figure 3) Step l-offset Ad/ust (Zero) Turn all bits OFF and adjust zero trimmer, Rl, until the output reads O.OOOV (1 LSB = 2.44 mY). In most cases this trim is not needed. The DAC1266A and DAC1266 can also be easily configured for a unipolar OV to 5V range or ±2.5V and ±10V bipolar ranges by using the additional 5k application resistor provided at the 20V range R terminal, pin 11. For a 5V span (OV to 5Vor ±2.5y), the two 5k resistors are used in parallel by shorting pin 11 to pin 9 and connecting pin 10 to the op amp output and the bipolar offset either left open for unipolar or connected through a 1000 pot to the external Step 2-Galn Ad/ust Turn all bits ON and adjust 1000 gain trimmer, R2, until the output is 9.9976V (full-scale adjusted to 1 LSB less than nominal full-scale of 10.000y). If a 10.2375V full-scale is desired (exactly 2.5 mVIbit), insert a 1200 resistor in series with the gain resistor at pin 10 to the op amp output or use the LH0071 voltage reference. 15V lOOk r--4......Wv--+< ~Jk 100 -15V BIPOLAR OFF 20V RANGE DACI211&A OAC1268 5. 9.95k 10 - IREF 19.95k lOY RANGE D.limA v' OAC 20k ANA GNO 3pF 5k - OUTPUT OY TO lOY '0 Bk lOUT;: 41( 'REF x CODE CODE ,NPUT 8 13 -VS --------I.~ LSB 'TL/H/5068-2 FIGURE 1. OV to 10V Unipolar Voltage Output 85-132 ·Power and analog ground must have a common current return path. See section 3.0 for proper connections. Functional Description and Applications (Continued) RI 100 BIPOLAR OFF 11 oACI2liSA oACI2&6 20V RANGE Sk 9..9Sk - IREF O.5mA OUTPUT -SV TO SV Sk v' ~ oAC DACoUT 8k ANA GNo lOUT c 4 x IREF It CODe 2.4k CDDE INPUT LSB -VS ·Power and analog ground must have a common current return path. See section 3.0 10r proper connections. FIGURE 2. ± 5V Bipolar Voltage Output • RI 100 BIPOLAR OFF 11 !OV RANGE oAC1266A oACI266 AMP SUMMING JUNCTION 19.9Sk S REF IN 10 - IREF D.5mA 10V RANGE 3pF 5k DAC 20k ANA GND Sk 9.9Sk - DAC DUT ID OUTPUT -IOVlo 10V 8k lOUT" 4 It 'REF It CODe ':" CD DE INPUT -VS - - - - - - - -__ .. LSB TUH/5068-3 FIGURE 3. ± 10V Voltage Output ·Power and analog ground must have a common current return path. See section 3.0 for proper connections. S 5·133 Functional Description and Applications (Continued) , reference for the bipolar range. For the ± 1OV range use the 5k resistors in series by connecting only pin 11 to the op amp output and connecting the bipolar offset as shown. The ± 10V option is shown in Rgure 3. 2.0 DIGITAL INPUT The DAC1266A and DAC1266 use a standard positive true straight binary code for unipolar outputs (all 1s give full· scale output), and an offset binary code for bipolar output ranges. In the bipolar mode, with aliOs on the inputs, the output will go to negative full·scale; with 100..• 00 (only the MSB on), the output will be O.OOV; with all 1s, the output will go to positive full·scale. The threshold of the digital input·circuitry is set an .4V and does not vary with supply voltage. The input lines can interface with any type of 5V logic, TTL/DTL or CMOS, and have sufficiently low input currents to interface easily with unbuffered CMOS logic. The configuration of the input circuit is shown in Figure 4. The input line can be modelled as a 30 kO resistance connected to a -0.7V rail. I DIGITAL INPUTS (PINS I3TD 241 I •. ..1... I I -:rPWR - GND 5pF 30k . . . - -..... -O.7V IpwR - 4.0 OUTPUT VOLTAGE COMPLIANCE The DAC1266A and DAC1266 have a typical output compli· ance range from - 2V to 10V. The current-steering output stages will be unaffected by changes in the output terminal voltage over that range. However, there is an equivalent output impedance of Bk in parallel with 25 pF at the output terminal which produces an equivalent error current if the voltage deviates from power ground. This is a linear effect which does not change with input code. Operation beyond the compliance limits may cause either output stage saturation or breakdown which results in non·linear performance. Compliance limits are a function of output current and negative supply. 5.0 DIRECT UNBUFFERED VOLTAGE OUTPUT FOR CABLE DRIVING I i The analog ground at pin 3 is the ground reference point for the internal reference and is thus the "high quality" ground; it should be connected directly to the analog reference point of the system. The power ground at pin 12 can be connected to the most convenient ground reference point; analog power return is preferred, but digital ground is acceptable. If power ground contains high frequency noise beyond 200 mV, this noise may feed through the converter; so that some caution will be required in apply!ng these grounds. 1--0 TO LOGIC GND TL/H/S068-4 FIGURE 4. Equivalent Digital Input Circuit 3.0 APPLICATION OF ANALOG AND POWER GROUND The DAC1266A and DAC1266 bring out separate analog and power grounds to allow optimum connections for low noise and high speed performance. The two ground lines can be separated by up to 200 mV without any loss in per· formance. There may be some loss in linearity beyond that level. If these DACs are to be used in a system in which the two grounds will be ultimately connected at some distance from the device, it is recommended that parallel back·to· back diodes be connected between the ground lines near the device to prevent a fault condition. The wide compliance range allows direct current-to·voltage conversion with just an output resistor. Ftgure 5 shows a connection using the gain and bipolar output resistors to give a ± 1.60V bipolar swing. In this situation, the digital code is complementary binary. Other combinations of internal and external output reSistors (Rx) can be used to scale to alternate voltage ranges, simply by appropriately scaling the 0 rnA to - 2 rnA unipolar output current and using the 10.0V reference voltage for bipolar offset. For example, set· ting Rx= 2.67 kO give a ± 1V range with a 1 kO equivalent output impedance. This connection is especially useful for directly driving a long cable at high speed. Using a 500 resistQr for Rx would allow interface to a 500 cable with a ±50 mV full-scale swing. 6.0 HIGH SPEED 12·BIT AID CONVERTERS The fast settling characteristics of the DAC1266A and DAC1266 make them ideal for high speed successive approximation AID converters. Shown in Ftgure 6 is a configu· ration using standard components; this system completes a full 12-bit conversion in, 10 ).Ls unipolar or bipolar. This converter will be accurate to ± Yz LSB of 12 bits and have a typical gain TC of 10 ppmfOC.. S 5-13~ Functional Description and Applications (Continued) So ~UPF BIPOLAR Off Ok 11 zov RANGE OACI2i&A OAt'2S1 " 9.9511 10 IREF IOV RANGE ~ 19.95/1 REF I,. V· ANA 2.' GND 3 - DAC OAC OUT '0 RX lOUT" 4 "'REF" CODE CODE INPUT -Vs -------~._ "B FIGURE 5. Unbuffered Bipolar Voltage Output R3 1011 OAC12&&A DACI261 AMP SUMMING JUNCTION 111.9511 V· REF IN - IREf O.SmA m ANA GOO CODE INPUT • LSS 13 -Vs 16 9 11 mtiVCiIMP--~ SERIAL OUT ---':'-1 DMZ504 SAR DATA IN 14 mlfT CLOCK TLlH/5068-5 Input Ranges Unipolar Bipolar Equlv. ±2.5 Input to A DACZoUT 1.60kO 010 10 01020 ±5 ±10 BloDACOUT Input 10 A Inpullo B 2.35kO 3.08kO FIGURE 6. Fast Precision Analog to Digital Converter S 5-135 Connect 0105 Functional Description and Applications (Continued) In the unipolar mode, the system range is OV to 9.9976V, with each bit having a value of 2.44 mV. For true conversion accuracy, ~n AID converter should be trimmed so that a given bit code output results from input levels from Y2 LSB below to Y2 LSB above the exact voltage which that code represents. Therefore, the converter zero point should be trimmed with an input vOltage of 1.22 mV; trim R1 until the LSB just begins to appear in the output code (all other bits "0"). For full-scale, use an input voltage of 9.9963V (10V-1 LSB-Y2 LSB); then trim R2 until the LSB just begins to appear (all other bits "1"). The bipolar signal range is - 5.0V to 4.9976V. Bipolar offset trimming is done by applying Ii -4.9988V input signal and trimming R3 for the LSB transition (all other bits "0"). Full-scale is set by applying a 4.9963V and trimming R2 for the LSB transition (all other bits "1"). In many applications, the pretrimmed application resistors are sufficiently accurate that external trimmers will be unnecessary, especially in situations requiring less than full 12-bit ± Y2 LSB accuracy. For fastest operation, the impedance at the comparator summing node must be minimized. However, lowering the impedance will reduce the voltage signal to the comparator (at an equivalent impedance at the summing node of 1 k.o., 1 LSB = 0.5 my), to the point that comparator performance will be sacrificed. The contribution to this impedance from the DAC will vary with the input configuration (Figure 6, Input Ranges Table). To prevent dynamic errors, the input signal should have a low dynamic source impedance, such as that of the LF411 A op amp. Definition of Terms Digital Inputs: The DAC1266A and DAC1266 accept digital input codes in binary format and may be user connected for anyone of three binary codes: straight binary, two's complement, or offset binary. Analog Output Digital Input MSBLSB Straight Binary Offset Binary 000 .•. 000 zero -FS (Full-Scale) 011 ..• 111 Y2FS-1 LSB zero-1 LSB 100•.•000 zero Y2FS 111 ••• 111 +FS-1 LSB ' +FS-1 LSB Two's Complement* Linearity Error: Unearity Error of a DIA converter is an important measure of its accuracy. It describes the deviation from an idea~ straight line transfer curve drawn between zero (all bits OFF) and full-scale (all bits ON). Differential Non-Unearlty: For a 01 A converter, it is the difference between the actual output VOltage change and the ideal (1 LSB) voltage change for a one-bit change in code. A differential non-linearity of ± 1 LSB or less guarantees monotonicity; i.e., the output always increases and never decreases for an increasing input. It is guaranteed by testing the major carry transitions; i.e., 100...000 to 011 ... 111 etc. Settling Time: Setting time is the time required for the output to settle to within the specified error band for any input code transition. It is usually specified for a full-scale or major carry transition. Gain Tempco: The change in full-scale analog output over the specified temperature range 'expressed in parts per million of full-scale per °c (ppm of FSrC). Gain error is measured with respect to 25°C at high (TMAX) and low (TMIN) temperatures. Gain tempco is calculated for both high (TMAX-25°C) and low (25°C-TMIN) ranges by dividing the gain error by the respective change in temperature. The specification is the larger of the two representing worstcase drift. Offset Tempco: The change in analog output with all bits OFF over the specified temperature expressed in parts per million of full-scale per °c (ppm of FSrC). Offset error is measured with respect to 25°C at high (TMAX> and low (TMIN) temperatures. Offset tempco is calculated for both high (TMAX-25°C) and low (25°C- TMIN) ranges by dividing the offset error by the respective change in temperature. The specification given is the larger of the two, representing worst-case drift. Power Supply Sensitivity: Power supply sensitivity is a measure of the change in gain and offset of the DI A converter resulting from a change in -15V supply. It is specified under DC conditions and expressed as parts per million of full-scale per percent of change in power supply (ppm of FS/O/O). zero +FS-1 LSB -FS zero-1 LSB 'Invert MSa with extemallnverter.to obtain Two's Complement coding Ordering Information Temperature Range Unearity Error OverTemperature O"C to 70"C -55°C to + 125°C I~~~-r---------1------------' ± Y2 Bit DAC1266ACJ DAC1266AJ I ±3,4 Bit DAC1266LCJ S 5-136 DAC1266W ~National ~ Semiconductor LM131A/LM131, LM231A/LM231, LM331A/LM331 Precision VOltage-to-Frequency Converters General Description The LM131 ILM231 ILM331 family of voltage-to-frequency converters are ideally suited for use in simple low-cost circuits for analog-to-digital conversion, precision frequencyto-voltage conversion, long-term integration, linear frequency modulation or demodulation, and many other functions. The output when used as a voltage-to-frequency converter is a pulse train at a frequency precisely proportional to the applied input voltage. Thus, it provides all the inherent advantages of the voltage-to-frequency conversion techniques, and is easy to apply in all standard voltage-to-frequency converter applications. Further, the LM131AI LM231A1LM331A attains a new high level of accuracy versus temperature which could only be attained with expensive voltage-to-frequency modules. Additionally the LM131 is ideally suited for use in digital systems at low power supply voltages and can provide low-cost analog-to-digital conversion in microprocessor-controlled systems. And, the frequency from a battery powered voltage-to-frequency converter can be easily channeled through a simple photoisolator to provide isolation against high common mode levels. has low bias currents without degrading the quick response necessary for 100 kHz -voltage-to-frequency conversion. And the output is capable of driving 3 TTL loads, or a high voltage output up to 40V, yet is short-circuit-proof against Vee· Features • Guaranteed linearity 0.01 % max • Improved performance in existing voltage-to-frequency conversion applications • Split or single supply operation • Operates on single 5V supply • Pulse output compatible with all logiC forms • Excellent temperature stability, ± 50 ppml"C max • Low power dissipation, 15 mW typical at 5V • Wide dynamic range, 100 dB min at 10 kHz full scale frequency • Wide range of full scale frequency, 1 Hz to 100 kHz • Low cost The LM131/LM231/LM331 utilizes a new temperaturecompensated band-gap reference circuit, to provide excellent accuracy over the full operating temperature range, at power supplies as low- as 4.0V. The precision timer circuit Typical Applications RIN lovFU~I~ _~",.k"',,IOlI_p-_ _ _ _~T -r "..J.. CIN·· 0 IPF • ,..-1\IIj1\r--+ VLOGIC 1 ~ IZk'llI* :t1"* - ~ 47<1011 ). ~k* GAIN -Vs (OPTIONAL) OFFSET ADJUST ~ }. ADJUST '* ·Use stable components with low temperature coefficients. See Typical Applications section. ··0.1 fLF or 1fLF, See "PrinCiples of Operation." FIGURE 1. Simple Stand-Alone Voltage-to-Frequency Converter with ± 0.03% Typical Linearity (f = 10 Hz to 11 kHz) 55-137 _ TL/H/5680-1 r- s:::: ~ .... l> ...... rs:::: N .... Co) I Absolute Maximum Ratings .- 'a ~ .... ::& ~ .CO) N ::& .... .CO) .- ....::E ~ .CO) .- Supply Voltage Output Short Circuit to Ground Output Short Circuit to Vcc Input Voltage Operating Ambient Temperature Range Power Dissipation (Po at 25°C) and Thermal Resistance (8jAl (H Package) Po 8jA (N Package) Po 8jA LM131A/LM131 40V Continuous Continuous -0.2V to'+ Vs LM231A/LM231 40V Continuous Continuous ~0.2Vto +Vs . LM331A/LM331 40V Continuous Continuous -0.2Vto +Vs TUIN TUAX - 55°C to + 125°C TMIN TUAX - 25°C to + 85°C TMIN TUAX O"Cto +70"C S70mW 150·C/W 570mW lfjO"C/W 500mW 155°C/W , 570mW 150"C/W 500mW 155°C/W Electrical Characteristics TA = 25°C unless otherwise specified. (Note 1) Parameter Conditions VFC Non-Linearity (Note 2) ::& .... Typ Max Units 4.5V s: Vs s: 20V Min ±0.003 ±0.Q1 TMIN s: TA s: TMAJ( ±O.OOS ±0.02 % FullScale % FullScale .±0.024 ±0.14 % FullScale 1.00 1~00 1.05 1.10 kHzlV kHzlV ±30 ±20 ±150 ±50 ppm/DC ppm/DC 0.Q1 O.OOS 0.1 O.OS %IV %IV VFC Non-Unearity In Circuit of Rgure 1 Vs = 15V,f'= 10Hzto11 kHz Conversion Accuracy Scale Factor (Gain) LM131, LM131A, LM231 , LM231A LM331 , LM331A VIN = -10V, RS = 14 kfl Temperature Stability of Gain LM131/LM231/LM331 LM131A1LM231A1LM331A TMIN Change of Gain with Vs 4.5VS:Vs s: 10V 10V s: Vs s: 40V Rated Full-Scale Frequency VIN = -10V Overrange (Beyond Full-Scale) Frequency VIN = -ltV 0.95 0.90 s: TA s: TMAX,4.5V s: Vs s: 20V , 10.0 kHz 10 % INPUT COMPARATOR Offset Voltage LM131/LM231/LM331 . LM131A1LM231A/LM331A TMIN TMIN s: TA s: TMAJ( s: TA s: TMAX Bias Current Offset Current Common-Mode Range TIMER TMIN s: TA s: TMAX ±3 ±4 ·.±3 ±10 ±14 ±10 mV mV mV '--80 -300 nA ±8 ±100 nA Vcc- 2.O V -0.2 \ Timer Threshold Voltage, Pin 5 0.667 0.70 x Vs Input Bias Current, Pin 5 All Devices LM131/LM231/LM331 LM131A/LM231A1LM331A Vs = 15V OVS:VPIN 5 s: 9.9V VPIN5 = 10V VPIN5 = 10V 0.S3 ±10 200 200 ±100 1000 500 nA nA nA. VSAT PIN 5 (Reset) 1= 5mA 0.22 0.5 V S 5-138 r- :s:::: .... Electrical Characteristics (Continued) TA= 25'C unless otherwise specified (Note 1) I Parameter CURRENT SOURCE (Pin 1) Conditions Output Current LM131, LM131A, LM231 , LM231A LM331 , LM331A RS=14 k!l, VPIN 1 =0 Change with Voltage OV~VPIN1~10V Co) I Min I Typ I Max I Units 126 116 135 136 144 156 p.A p.A 0.2 1.0 /LA 0.01 0.02 2.0 TA=TMAX 1.0 10.0 50.0 (10 to 500) LM131, LM131A, LM231 , LM231A LM331, LM331A N 1.76 1.70 1.89 1.89 2.02 2.08 ±60 Stability vs TIme, 1000 Hours ±0.1 % 1=5mA 1=3.2 rnA (2 TTL Loads), TMIN~TA~TMAX VSAT 0.15 0.10 ±0.05 OFF Leakage 0.50 0.40 1.0 V V /LA SUPPLY CURRENT LM131, LM131A, LM231, LM231A LM331, LM331A Vs=5V 2.0 3.0 4.0 mA 2.5 4.0 6.0 Vs=40V mA 1.5 3.0 6.0 mA Vs=5V 2.0 4.0 8.0 mA Vs=40V Note 1: All specifications apply In the circuit 01 Figure 3, with 4.0V,;:Vs';:40V, unless otherwise noted. Note 2: Nonlinearity Is defined as the deviation 01 lOUT from VIN X (10 kHz/-1 0 Voel when the circuit has been trimmed for zero error at 10Hz and at 10kHz, over the frequency range 1 Hz to 11 kHz. For the timing capacitor, Cr, use NPO ceramic, Teflone, or polystyrene. Functional Block Diagrams Vee • 1--------f-----------, I I I I r ;H FREQUENCY: .J. - I ~ ... i9 I PUMP 1.I11V oc I.9 IV oc liAS CURRENTS TOALL CIRCUITS INPUT i VOUT = -fiN RF x 2.09V x As x (Rtc.> ·Us TL/H/S680-8 'Use stable components with low temperature coefficients. SELECT Rx = (Vs - 2V) 0.2mA FIGURE 5. Simple Frequency-ta-Voltage Converter, 10 kHz Full-scale, ±0.06% Non-Linearity ·Use stable components with low temperature coefficients. FIGURE 6. Precision Frequency-to-Voltage Converter, 10 kHz Full-Scale with 2-Pole Filter, ±O.01% Non-Linearity Maximum 55-143 ~ r3: ..... w ..... ~ elf) elf) ~ r----------------------------------------------------------------------------------------------------Typical Applications (Continued) ;c Light Intensity to Frequency Converter ~ elf) elf) +5VTO+15V ~ .... 10=--4--....- FULL ~~u:-:,>. SCALE TUH/56BO-9 'L14F-1, L14G-l or L14H-1, photo transistor (General Electric Co.) or similar Temperature to Frequency Converter v, f--i-.....- t.. 'OUlQ TEU' ""h '''RI IGHlrK . UhF TUH/5680-10 BaBiC Analog-to-Dlgltal Converter Using Voltage-to-Frequency Converter Long-Term Digital Integrator USing VFC , 'V$ 'VI DATl v,. TUH/5680-11 } DUTPUT TO COIIPUTE. TL/H/5680-12 S5-144 .... ....w .... i: Typical Applications (Continued) ~ Analog-to-Dlgital Converter with Microprocessor !i:.... -v, w .... TLlH/5680-13 Remote VOltage-to-Frequency Converter with 2-Wire Transmitter and Receiver FREOUENCY OUTPUT Jt--¥"",,++15V GNO 15DIl POWER SUPPLY lM331 TLlH/5680-14 Voltage-ta-Frequency Converter with Square-Wave Output Using + 2 Flip-Flop +VS' +4.DVoc TO +15VOC CLR PRE 4,. VfC CIRCUIT USING lM331 10Upl/2 SOUARE WAVE . TLlH/5680-15 Voltage-ta-Frequency Converter with Isolators 'Vs +VlDGIC VfC USING lM331 t--UH).-- TD COMPUTER OR ~a COUNTER TO f.TO·V CDNVERTER USING lMI31 DPTOISOlATOR 4NZ. OR SIMILAR TLlH/568D-16 S 5-145 .. r----------------------------------------------------------------------------------------------C') C') :i .. Typical Applications (Continued) Voltage-to-Frequency Converter with Isolators ~ +Vs .:3 +VLOGIC :i ,-- ~--I---I ':" COMPARATOR WITH HYSTERESIS TlfH/5680-17 Voitage-to-Frequency Converter with Isolators +Vs +VLOGIC TELEMETRY USING RF LINK TLlH/5680-18 Voltage-~o-Frequency Converter with Isolators 'Vs +VLOGIC lk TO COMPUTER DR TO COUNTER ...-----, " " " - - - OR TOHON CONVERTER USING LMl3l VFC USING LM331 TlfH/se80-19 Dual-ln-Llne Package Connection. Diagrams Metal Can Package Vs CURRENT OUTPUT 1 REFERENCE CURRENT 2 FREQUENCY OUTPUT 3 Vs COMPARATOR INPUT THRESHOLD GNO GNO TOP VIEW RIC TOP VIEW TLlH/5680-20 TL/H/5680-21 Order Number LM23tAN, LM23tN, LM33tAN, orLM331N See NS Packsge ,NOBE Order Number LM131AH, LM13tH, LM23tAH, LM23tH, LM331AH or LM331H See NS Package H08C S5-146 Schematic Diagram ,-!r. F !i~ ~ L5~ .Ll5 -~ ii' ~~ aT ~,0= u ~"s"L ii 8J' r1 Ta~ 4 .." r. ~ ni='= .La ~~ ;A liS ['\8rF 12;; i'\\ 5J ~ ;A ~ "" ~s~ 12= 4 ~UIiI ~~i , . * 11"1. ~ ~l~, I'! l5 Cif! ---J ~a ---J ~B -J'" ,1J p ~. ~ ~. ,!" ~11'01 ~ ~t-..6 Ii! OlIO! ~ * ~!1IrZ' ~~ ,~r' ~II ~A :E. ~N ~ co! !;!I Ii*-- ill. ~ ~ II '} 1\.8 s-i1 if II __ f..: ,_ II I ~ f--< ,. lr=1 ~ -'B\- 3&loll T'g t:iC~11 ~ i§ ~~r II T~ i= a"-- ~. ii N N wW: ~ ~ II J~~ --tII . TLIH/5680-22 55-147 Section 6 Analog Switches Analog Switches Section Contents Combined Function Analog Switches AH5020C Monolithic Analog Current Switches ...•....•......••...•....•............•........•.••....•..•....•. S 6-1 Multiplexers LM1037 Dual Four-Channel Analog Switch ...•.•...........•...••.•.•...•.. , ..•••....••••..•.••..•..••..•••..•.. S 6-9 LM1038 Dual Four-Channel Analog Switch ........•.....••......•.•.......•...•.......•.......•.•.........•... S 6-15 .----------------------------------------------------------------.. :::z:: J?!I National ~ Semiconductor S o o AH5020C Monolithic Analog Current Switch Gener'al Description Applications A versatile dual monolithic JFET analog switch economically fulfills a wide variety of multiplexing and analog switching applications. These switches may be driven directly from standard 5V logic. • AD/DA converters • Micropower converters • Industrial controllers • Position controllers • Data acquisition • Active filters • Signal multiplexers/demultiplexers • Multiple channel AGC • Quad compressors/expanders • Choppers/demodulators • Programmable gain amplifiers • High impedance voltage buffer • Sample and hold For voltage switching applications see LF13331. LF13332. and LF13333 Analog Switch Family. The monolithic construction guarantees tight resistance match and track. Features • • • • • • • Interfaces with standard TTL "ON" resistance match Low "ON" resistance Very low leakage Large analog signal range High switching speed Excellent isolation between channels 20 1500 50 pA ±10V peak 150 ns 80 dB at 1 kHz Connection and Schematic Diagrams Dual-in-Line Package . TOP VIEW TL/H/5166-1 Order Number AH5020C Se~ NS Package JOBA 4 6' 5 TL/H/5166-2 Note: All diode cathodes are internally connected to the substrate. S6-1 Absolute Maximum Ratings Input Voltage Positive Analog Signal Voltage Negative Analog Signal Voltage Diode Current Drain Current 30V 30V -15V 10mA 30mA Power Dissipation Operating Temp. Range Storage Temperature Range Lead Temp. (Soldering, 10 seconds) 500mW -25'Cto +85'C - 65'C to + 150'C 300'e , Electrical Characteristics (Notes 1 and 2) Symbols Conditions Typ Max Units IGSX Input Current "OFF" Parameter VGO = 4.5V, VSO = 0·7V VGO = 11V, VSO = 0.7V TA = 85'C, VGO = 11V, VSO = 0.7V 0.01 0.Q1 0.1 0.2 10 nA nA nA 10(OFF) Leakage Current "OFF" VSO,= 0.7V, VGS = 3.8V TA = 85'C 0.Q1 0.2 10 nA nA IG(ON) Leakage Current "ON" VGO = OV, Is = 1 mA TA = 85'C 0.08 1 200 nA nA IG(ON) Leakage Current "ON" VGO = OV,ls TA = 85'C 0.13 5 10 nA IJ.A IG(ON) Leakage Current "ON" VGO = OV,ls = -2mA TA = e5'C 0.1 10 20 nA IJ.A rOS(ON) Drain-Source Resistance VGS = 0.5V, Is = 2 mA TA = +85'C 90 150 ' 240 n n VOIOOE Forward Diode Drop 10 = 0.5mA rOS(ON) Match VGS TON Turn "ON" Time TOFF Turn "OFF" Time CT CrossTalk = 2mA 0.8 V 2 20 n See ac Test Circuit 150 500 ns See ac Test Circuit 300 500 ns See ac Test Circuit 120 = 0,10 = 1 mA Note 1: Test conditions 2S'C unless otherwise noted. Note 2: "OFF" and "ON" notation refers to the conduction state of the Fer switch. S6-2 dB > :::J: Test Circuits en C) N C) o AC Test Circuit Cross Talk Test Circuit VA=±10V 10k ....._ ...._<> VOUT (CLsl0 pF) >.:....-...-VOUT 10k 0.1# 10k -15V TLlH/5166-4 ~ TL/H/5166-3 Switching Time Waveforms 5V OR 15V Ir=IISO.l/AS OV O.BV VOUT VA=+10V OV OV VOUT -10V VA=-10V TL/H/5166-5 56-3 Typical Performance Characteristics I. Leakage Current, ID(OFF) vs Temperature Parameter Interaction ~.VaI"-IIV."--111A 1'-. ,,- -1 IlIA. Vas-8V iI Ii! [tra.VaI--15V.Vea .. 8V~~ Ii 200 ~ll00~~ 10k 100 I IDU1-++++Htf 10 PI "" I "" fit I 20 I 'II J 10 1.0 1.0 I 10 100 VaI-BA1E-8OU1ICE CUTOFF VOlTAIIE (V) 10 25 35 45 15 15 7& 85 TEMPERATUlIE ("C) TLlH/5166-6 TL/H/5166-7 "ON" Resistance, rDS(ON) va Temperature 110 S" - IV TTL 125 1100 I .L Ip=-1 RIA IV~ ~ P "'"'" 75 Cross Talk, CT vs Frequency - -120 -110 _-100 !-90 ..- ; -80 1=: 'i' ~ ;;;"'m/l~-11V CMOS \: VA,,±10V -10 t; -40 -30 o 26 35 45 15 15 75 -20 -10 100 85 lk TEMPERATURE ("C) 10k lOOk 1M FREQUENCY (Hz) TL/H/5166-6 TL/H/5166-9 Leakage Current vs Oraln-Gate Voltage i Transconductance vs Drain Current 1.~~ aa -I_ 100 TA=ZSOC V08=-&V 1=1 kHz 1 mElIJ 100 11°~E Ii 1.0 '-'-'-.......... ~ ..L-........- ' -........... -10 -1.0 DRAiN CURRENT (IlIA) TL/H/5166-1D TLlH/5166-11 Drain Current vs Bias Voltage -26 II Normalized Drain Resistance vs Bias Voltage gl00 VDI- -18'1 1.. 1 kHz \ Ii TA=ZSOC \ ll. , I ~'\ ~ ~ """ 1'1... o ~ o e 1000. TL/H/5166-12 VGiiOffl 20 2.0 o 1.0 2.0 3.0 BATE-SOURCE VOLTAIIE (V) ~~18V._-l0,.A:: IDS 1- F '\. "\. VasIOff) • 10 IDSb"-ygs' ~ _f= - t:: J ...",," 0:2 0.4 0.6 0.8 1.0 IVas IVusIDfF) I-NORMAUZED GATE-TlJ.SOURCE VOIJAGE (V) TL/H/5166-13 S6-4 Applications Information THEORY OF OPERATION NOISE IMMUNITY The AH5020 analog switches are primarily intended for operation in current mode switch applications; i.e., the drains of the FET switch are held at or near ground by operating into the summing junction of an operational amplifier. Limiting the drain voltage to under a few hundred millivolts eliminates the need for a special gate driver, allowing the switches to be driven directly by standard TTL. The switches with the source diodes grounded exhibit improved noise immunity for positive analog signals in the "OFF" state. With VIN =. 15V and the VA = 10V, the source of Ql is clamped to about 0.7V by the diode (VGS = 14.3V) ensuring that ac signals imposed on the 10V wlll not gate the FET "ON". SELECTION OF GAIN SETTING RESISTORS If only one of the two switches in each package is used to apply an input signal to the input of an op amp, the other switch FET can be placed in the feedback path in order to compensate for the "ON" resistance of the switch FET as shown in Figure 1. The closed-loop gain of Figure 1 is: Since the AH5020 analog switches are operated current mode, it is generally advisable to make the signal current as large as possible. However, current through the FET switch tends to forward bias the source to gate junction and the signal shunting diode resulting in leakage through these junctions. As shown in Rgure 2, IG(ON) represents a finite error in the current reaching the summing junction of the op amp. AVCL=- R2 + rOS(ONIQ2 -Rl + rOS(ON)Ql For Rl = R2, gain accuracy is determined by the rOS(ON) match between Ql and Q2. Typical match between Ql and Q2 is 20 resulting in a gain accuracy of 0.02% (for Rl = R2 . = 10 k!l). Secondly, the rOS(ON) of the FET.begins to "round" as Is approaches loss. A practical rule of thumb is to maintain Is at less than 1f1o of loss. Combining the criteria from the above discussion yields: Rl MIN () ~ VA(MAX) Ao (2a) IG(ON) or: ~ VA(MAXI lossIl0 whichever is larger. HI VA (2b) = R2 10k 10k ANALOG INPUT -W\~""-""" >--~..... TL/H/5166-14 FIGURE 1. Use of Compensation FET IS",{t- ...--., RIVA=10V -~""'"-o- R2 TL/H/5166-15 FIGURE 2. On Leakage Current, IG(ON) S6-5 I Applications Information (Continued) Where VA(MAX) Ao IG(ON) loss = Peak amplitude of the analog input Accordingly: signal = Desired accuracy = Leakage at a given Is Saturation current of the FET switch = 20 rnA R1 M ~ VAIMIN)Ao (AX) (N) IO(OFF) Where VA(MIN) = Minimum value for the analog input signal Ao = Desired accuracy N = Number of channels IO(OFF) = "OFP' leakage of a given' FET switch = In a typical application, VA might = ±10V, Ao =0.1%, O"C s: TA s: 85"C. The criterion of equation (2b) predicts: . 10V· R1(MIN) ~ 20mA =5 kG As an eXllmple,1f N=10, Ao=0.1%, and IO(OFF) at 85"C for the AH5020. R1(MAX) Is: . (1V)(10- 3) R1(MAX) ~ (10)(10 x 10-11) 10k 10 ForR1 = 511, Is ... 10Vl5k or 2 rnA. The electrical characteristic8 guarantee an IG(ON) s: 1".A at 85"C for the AH5020. Per the criterion of equation (2a): R1 ~ 10 nA Selection of R2, of course, depends on the gain desired and for unity gain R1 = R2. Lastly, the foregoing discussion has ignored resistor tolerances, input bias current and offset voltage of the op amp - all of which should be· considered in setting the overall gain accuracy of the circuit. (10V)(10- 3) 10 kG (MIN) ~ 1 x 10 s ~ Since equation (2a) predicts a higher value, the 10k resistor should be used. The "OFF" condition of the FET also affects gain accuracy. As shown In Figurs 3, the leakage across Q2, ID(OFF) represents a finite error In the current arriving at the summing jUnctiol1 of the op amp. l- I•• R1- R2 81 TLlH/51e8-16 FIGURE 3. Off Leakage Current, ID(OFF) 86-6 Applications Information (Continued) TTL COMPATIBILITY DEFINITION OF TERMS Standard TTL gates pull-up to about 3.SV (no load). In order to ensure turn-off of the AHS020, a pull-up resistor, RE)(T of at least 10 kO should be placed between the SV Vee and the gate output as shown in Figure 4. The terms referred to in the electrical characteristics tables are as defined in Figure 5. AHALOII INPUT IVAl r------'5V 10k Rm (2Ic 10 10k) ":' LOGIC INPUT (VIN) I 5V nL GATE " : ' " : ' .J &.:.:_----- TLlH/51fl6-17 FIGURE 4. Interfacing with + 5V TTL VA .......WIr-...----,,... a::TUH/51fl6-18 FIGURE 5. Definition of Terms ~6-7 ur----------------------------------------------------------------. § Typical Applications ~ Deglltchecl SwItch for Noiseless Audio Switching OFF ftC TYPICALLY 1111-10 ... > ...-OUT TL/H/5166-19 Gain Programmable Amplifier 10k r, 10k I I I 6 18<>--+-__ 'OOk .. I I CharacteristIcs: GaIn L ___' = -EouT = RFS liN 2 GAIN SElECT TUH/5166-20 86-8 ~National ~ Semiconductor LM 1037 Dual Four-Channel Analog Switch General Description Features The LM1037 is a dual, electronically controlled, analog switch with an internal muting facility. Anyone of four stereo signal sources may be selected by means of four control inputs. Its features make it ideal for stereo source selection in audio equipment and for use in a wide range of industrial, automotive, multiplexing or sampling applications. An additional pin is included to allow parallel connection of two or more integrated circuits. • • • • • • • Wide supply voltage range, 5V-2BV Low distortion, 0.04% typical Low noise, typically 5 /LV High input impedance Low output impedance TTL compatible control inputs Very low control current Block Diagram CONTROL INPUT STAGES lA (2) 2A (4) (3) 0 1B (6) (5) V+ 2B (8) SIGNAL INPUTS lC (11) H~_ _....._ _~(1...;.2) VIlAS 2C (13) AND MUTE 10 (17) 20 (15) ..!.....,.2- M~TE OUTPUTS INHIBIT TLlH/5199-1 Order Package Number LM1037 See NS Package N18A 86-9 A~solute Maximum Ratings Supply Voltage Pin 7 Input Current Operating Temperature Range - 20·C to -65·Cto Storage Temperature Range Power Dissipation (Note 1) Lead Temp. (Soldering. 10 set.'Onds) 28V . 5mA + 70·C + 150·C 1.3W 300"C Electrical Characteristics Vs=12V. TA=25·C Conditions Parameter Min Supply Voltage Range Typ 5 Supply Current Units 28 V VSUPPLY= 12V 6.4 8.5 mA VSUPPLy=28V 10 14 mA -0.7 0 0.7 2.8 3.0 ·Voltage Gain Signal Handling (Notes 2. 6) Max VSUPPLy=12V Small-Signal Bandwidth dB Vrms 300 kHz Distortion THO VSIGNAL = 1 Vrms @ 1 kHz Noise Voltage at Output CCIR/ARM Rs=2k Channel Separation (Note 4) VSIGNAL = 1 Vrms @ 1 kHz -70 -95 dB Relative Output in Muted State VSIGNAL = 1 Vrms -70 -90 dB @ 1 kHz 0.04 0.1 % 5 12 ",V Output Impedance 10 n Signal Input Impedance 30 Mn Logic Low Input Level Logic High Input Level 2.0 0.8 V 50 V Typical Performance Characteristics (Vs=12V. TA=25·C unless otherwise noted) C .s ffi ::i ::0 ... ~ It: ::0 '" 11 10 9 8 7 6 5 Supply Current vs Supply Voltage V V / V 7.5 Supply Current vs Temperature -115 ., 1 7.0 ;; -flO 15 ...'"'" ::0 / 6.5 i"'-- ..... ~ E ill 6.0 4 -110 10 20 30 SUPPLY VOLTAGE 'V) ! ~ w !1l-100 ~ ~ ~ 5.5 40 Signal-to-Noise vs Source Impedance (Note 3) 0-105 -95 S! '" -90 0.1 i'i '"w I- 3 0 Signal-to-Noise vs Temperature (Note 3) ....... .,.,.... !1l-105 ~ ........ ~ "" ::i-l00 fjl -95 0 10 20 30 40 50 60 70 80 AMBIENT TEMPERATURE ,·C) 0 10 20 30 40 50 60 70 80 AM81ENT TEMPERATURE I'C) , Channel Separation vs Frequency (Note 4) -70 . -70 AHenuation of Unselected Inputs VB Frequency (NoteS) Ii i" -80 ~ "' /' 51 to '""',- 1 10 100 lk SOURCE IMPEDANCE (kUI 10k '"~ -90 '" uj ./ =c ::0 z "'-100 ... 0.1 1 10 100 FREOUENCY IkHzl lk -110 0.01 I I -90 l= z i-l00 -110 0.01 ~ -80 z 51 ./ I -~ I '/ J 0.1 1 10 100 FREQUENCY (kHz) lk TL/H/5199-2 S6-10 Typical Performance Characteristics Total Harmonic Distortion vs Frequency 0.2 (Continued) (Vs= 12V, TA = 25'C unless otherwise noted) . Total Harmonic Distortion vs Frequency 0.2 SUPPLY VOLTAGE=12V VsIGNAL =100 mVrms Total Harmonic Distortion vs Frequency 0.2 SUPPLYVOLTAGE-12V -.,-- f--¥SIGNAL = 1 Vrm. 0.15 0.15 i! 0.05 0.05 "- o 0.01 0.1 1 " 10 '"!;€ " "- i!: 100 0.01 lk 0.1 01 . 0.05 ro... o 1 r10 100 ....... ....... -" o lk 0.01 0.1 FREQUENCY (kHz) FlIEQUENCY (kHz) - - 0.15 0.1 i!! SUPPLY VOLTAGE =28V VSIGNJ L=5 Vrm. 1 ./ 10 100 lk FREQUENCY (kHz) TL/H/5199-3 Note 1: Above TA=2S'C derate based on TJ max= ISO'C and 8JA=90'C/W. Signal Handling vs Frequency (Note 6) Note 2: The Instantaneous maximum voltage difference between any two input pins of one channel is 9.6V. Voltages in excess of this level may cause increased distortion and degraded channel separation. Note 3: Signal-to-noise measurement referred to a 1 Vrms Input signal using a CCIR filter referenced to 2 kHz and an average responding meter. '\ Nole 4: The level of output signal of a selected undriven amplijier with respect to the output level of a selected driven amplifier. For test purposes, signal is applied to only one input and all other inputs are decoupled to eliminate stray pick-up through external components. Channel separation is then defined as the ratio of Signal levels of the two output pins. \ \ J Note 5: For test purposes, signals are connected to three unselected input pins of one channel group and all other inputs are decoupled to eliminate stray pick-up through external components. Not. 6: Supply voltage 12V; signal handling defined at 1% distortion, 1 kHz. o 0.01 0_1 10 100 lk FREQUENCY (kHz) TLlH/5199-4 Typical Application CONTROL INPUTS r-a "----+-1 r-a "----+-1 r-a "----+-f r-a C'N L..---++--f lA lD L---f-----' C,N 2/\ INPUTS 2D INPUTS C,N 2C C,N R = 100 kO 1/4 watt Cl =10pF C2=1 pF C3=I00pF CIN=1 pF IC C3 TO PIN 7 NEXT DEVICE (MUTE INHI8IT) T T CH2 AUDIO OUTPUTS TLlH/5199-5 56-11 ~ C") ~ ~ ,--------------------------------------------------------------------------------Truth Tables LM1037 Channel selection is achieved by the application of DC voltages to the .control pins. Unselected control pins should be held low. DC Control Pin In HIGH State Input Pair Switched to Output Pins (10, 9) (2,4) (6,8) (11,13) (17,15) (12) A B C D Mute 16 18 1 3 None Low switChing level (Vt.l 2.0V and up to SOV SWITCHING SPEED VERTICAL 2V/DIV HORIZONTAL 2 !'I/DIV CONTROL PULSE PIN 18 I l OUTPUT RESPONSE TL/H/S199-6 2 DEVICES CONNECTED IN PARALLEL To increase the channel switching capacity, two or more devices can be connected together by the direct coupling of the mute inhibit pin 7 and the output pins 9 and 10. Only one output capacitor is required for each common output. DC Control Pin In HIGH State Device Number 1 Device Number 2 Input Pair Switched to Output Pins (10,9) A 16 18 1 3 B C D A 16 18 1 3 None B C D Mute 86·12 (2,4) (6,8) (11,13) (17,15) (2,4) (6,8) (11,13) (17,15) (12) Pin Function Description Device Pins Pin 16-lnputs A Select Pin 18-lnputs B Select Pin 1-lnputs C Select Pin 3-lnputs D Select Pins 2,6,11,17Inputs for Output 1 (Pin 10) Piris4, S, 13, 15Inputs for Output 2 (Pin 9) Pin 12-Mute Bias Level Pin 7-Mute Inhibit Input Pin 9-Output 2 Pin 10-0utput 1 Pin5 Pin 14 Description A high input level selects the corresponding channel. Only one channel should be selected at a time. Unselected channels should have their select inputs at a low level. Open circuit pins represent high input level. a: Two sets of four high impedance channel inputs for the connection of signals to be switched. The DC level at this pin is applied to the outputs when no input is selected and pin 7 is open. The level is internally set by a 25 kn and 33 kn potential divider at 0.6 Vs. This level may be adjusted by means of external resistors. Pin 12 may also be used as an additional common input in which case this signal is present on both outputs when no control input is applied. With this pin unconnected and no channel selection input is present; the mute level at pin 12 is applied to the outputs. With pin 7 grounded and no channel selection input present, the device output emitterfollowers are disabled allowing parallel connection to other device outputs. This pin is a current input and any current applied should be limited to 5 mA maximum. Pin 7 of several devices may be directly connected for parallel operation. These are common output pins for each channel. There are three possible output conditions: 1) Signal selected from 1 of 4 inputs. 2) Mute level output. 3) Device not selected-internal 6 kn pull-down resistors to ground. Positive supply voltage. Negative or ground supply voltage. Application Hints The basic circuit arrangement with minimum external components for use with DC coupled signals is shown in Figure 1. This arrangement may be used in a normal signal selection system or in the feedback path of DC coupled amplifiers for example to make a simple dual programmable power supply. By switching feedback connections dual programmable gain or frequency response amplifiers may be obtained. For switching between signal sources in stereo systems the LM1037 may be connected as shown in the typical application circuit. The input bias is obtainable from pin 12 or an alternative source may be used. If split supply operation is required, pin 12 may be grounded and the signals referenced to ground. r.'!"_ _ _ OPTIONAL COMMON ........Ii:-......;,;",.., INPUT OR BIAS (liN =14kl CHI OUTPUT CHI INPUTS CH2 OUTPUT CH21NPUTS TUH/5199-7 DCcoupledslgnaJs 1.2V -4......---------4 > _______..:1:::9) OUTPUT 2 TL/H/5200-1 Order Number LM1038 See NS Package N18A 86-15 - Absolute Maximum Ratings Supply Voltage Pin 7 Input Current 28V Storage Temperature Range -65'Cto +15O"C Power Dissipation (Note 1) 1.3W . Lead Temperature (Soldering, 10 seconds) 300"C 5mA -20"C to + 70"C Operating Temperature Range Electrical Characteristics Vs=12V, TA=25·C. Parameter Conditions Min Supply Voltage Range Typ Max 5 Supply Current 12 VSUPPly=12V Signal Handling (Notes 2, 6) VSUPPly= 12V V 17 rnA mA 17 28 -0.7 0 0.7 2.8 3.0 VSUPPly=28V Voltage Gain Small·Signal Bandwidth Units 28 dB Vrms 300 kHz Distortion THO VSIGNAl = 1 Vrms Noise Voltage at Output CCIR/ARM Rs=2k Channel Separation (Note 4) VSIGNAl = 1 Vrms @ 1 kHz -70 -95 dB Relative Output in Muted State VSIGNAl = 1 Vrms @ 1 kHz -70 -90 dB @ 1 kHz 0.04 0.1 % 5 12 /LV Output Impedance 10 0 Signal Input Impedance 30 MO Logic Low Input Level Logic High Input Level 2.0 0.8 V 50 V Typical Performance Characteristics (Vs = 12V, TA = 25'C unless otherwise noted) lB Supply Current vs Supply Volta"e 17 ~ I 16 iii . .E 0: 0: :::0 :::0 14 i . .E 0: :::0 I 13 / 12 :::0 11 10 lB -115 17 '!.. -110 13 12 ..... ~ 11 30 10 20 SUPPLY VOLTAGE (V) 40 ..... .... ~':'105 ...~ 1OO az eo ~ ~ -95 0 10 20 30 40 50 60 70 80 AM81ENT TEMPERATURE ('C) Attenuation of Unselected Inputs vs Frequency (Note 5) -70 -70 iD " ~ -80 . . -90 1 10 100 lk SOURCE IMPEDANCE (kD) 10k -110 0.01 -so £i:::0 -90 ~ C_ IOO 0.1 I 10 100 FREQUENCY (kHz) Ik -110 0.01 I If co ./ iii z !-100 I z ./ !i-90 -~ ! / ~ 95 0.1 ~-lOD .... Channel Separation vs Frequency (Note 4) -110 iD -- i-"'" ~ 0 10 20 30 40 50 60 70 80 AMBIENT TEMPEAATURE ('C) Signal-to-Noise vs Source Impedance lNote 3) 1- . ~ a- 105 14 10 0 Slgnal-IOoNolse va Temperature (Note 3) 1 1615 J 15 Supply Current vs Temperature ~ I II J 0.1 1 10 100 FREDUENCY (kHz) lk TUH/52QQ-2 S6-16 r- iii: ..... o Typical Performance Characteristics (Continued) (Vs= 12V, TA= 25°C unless otherwise noted) Co) Total Harmonic Distortion vs Frequency 0.2 0.2 SUPPLY VOLTAGE~12V ¥SIGNAL ~ 100 mVrms SUPPLY VOLTAGE ~12V VSIGHAL =1 Vrms ;< "' o 0.01 ;; 0.1 1 10 ....... lk FREQUENCY (kHz) , i!: I'.. 0.05 ~ 100 SUPPLY VOLTAGE - 2BV VSIGNAL ~ 5 Vrm, ;< i/ 0.1 t--- ~ 0.1 i!: 0.05 0.05 - 0.15 co i!: 0.2 0.15 0.15 ;; 0.1 Total Harmonic Distortion vs Frequency Total Harmonic Distortion vs Frequency o 0.01 ~ ....... -I""-" ........ - ' Q 0.1 1 10 100 lk 0.01 0.1 FREQUENCY (kHz) 1 ./ 10 100 lk FREQUENCY (kHz) TLlH/S200-3 Signal Handling vs Frequency (Note 6) 4 Note I: Above TA=25'C derate based on TJ max=150'C and 8JA=90'C/W. , Note 2: The instantaneous maximum voltage difference between any two Input pins of one channel is 9.SV. Voltages in excess of this level may cause Increased distortion and degraded channel separation. \ Note 3: Signal-la-noise measurement referred to a 1 Vrms input signal using a CCIR filter referenced to 2 kHz and an average responding meter. , \ Note 4: The level of output signal of a selected undriven amplifier with respect 10 the outpul level of a selected driven amplilier. For test purposes, signal is applied to only one input and all other Inputs are decoupled to eliminate stray pick-up through extemal components. Channel separation is then defined as the ratio of signal levels of the two output pins. Note 5: For test purposes, signals are connected to three unselected input pins of one channel group and all other inputs are decoupled to eliminate stray pick·up through external components. 0.01 0.1 1 10 100 lk Note 6: Supply voltage 12V; signal handling defined at 1% distortion, 1 kHz. FREQUENCY (kHz) TL/H/5200-4 Typical Application CONTROL INPUTS O(LSB) C'N ~-++-I lA L-..--t------' f-o 10 C'N '-----+-1 2A INPUTS f-o 20 INPUTS R=100kO 'Awalt Cl=IO,.F C2=I,.F C3=100,.F C'N=I,.F OUTPUTS TL/H/S200-S 56-17 CD CD Cf) 0 Truth Table ..- ::E logic Inputs ..J Latch Enable Pin 18 Mute Pin 1 Input Pin Selected Channel Select Output 1 Output 2 Data Pin 3 Pin 16 Pin 10 Pin 9 1 0 0 0 DPin17 DPin15 1 0 0 1 APin2 APin4 1 0 1 0 BPin6 BPin8 1 0 1 1 CPin11 CPin 13 1 1 0 X X X X X Pin 12 Mute Bias Inputs Previously Selected are Retained Low (O) ...... LM34/LM34A, LM34C/LM34CA, LM34D Precision Fahrenheit Temperature Sensors r s: w General Description Features The LM34 series are precision integrated-circuit temperature sensors, whose output voltage is linearly proportional to the Fahrenheit temperature. The LM34 thus has an advantage over linear temperature sensors calibrated in degrees Kelvin, as the user is not required to subtract a large constant voltage from its output to obtain convenient Fahrenheit scaling. The LM34 does not require any extemal calibration or trimming to provide typical accuracies of ± %OF at room temperature and ±1%OF over a full -50 to +300"F temperature range. Low cost is assured by trimming and calibration at the wafer level. The LM34's low output impedance, linear output, and precise inherent calibration make interfacing to readout or control circuitry especially easy. It can be used with single power supplies or with plus and minus supplies. As it draws only 70 /LA from its supply, it has very low self-heating, less than O.2"F in still air. The LM34 is rated to operate over a-50° to + 300°F temperature range, while the LM34C is rated for a -40° to + 230°F range (O°F with improved accuracy). The LM34 series is available packaged in hermetic T0-46 transistor packages, while the LM34C is also available in the plastic TO-92 transistor package. The LM34 is a complement to the LM35 (Centigrade) temperature sensor. • • • • • • • • • • • Connection Diagrams Typical Applications ~ ...... r s: w Calibrated directly in degrees Fahrenheit Linear + 10.0 mVrF scale factor 1.0°F accuracy guaranteed (at + 77°F) Rated for full -50" to +300°F range Suitable for remote applications Low cost due to wafer-level trimming Operates from 5 to 30 volts Less than 70 /LA current drain Low self-heating, 0.18°F in still air Nonlinearity only ± 0.5°F typical Low-impedance output, 0.40 for 1 mA load TO-46 Metal Can Package* §..... ~ ....ow +Vs I HV TO + 20V) $-.. . ."., BOTTOM VIEW TLlH/8B8S-3 TL/H/68BS-1 FIGURE 1. Basic Fahrenheit Temperature Sensor (+5° to +300°F) ·Case is connected to negative pin. Order Number LM34H See NS Package H03H To-92 Plastic Package BOTTOM VIEW s: ....w ..... +Vs ~VOUT ~fR' T1YH/68BS-2 CHOOSE R,=(-Vsl/5O,.A Vour= +3,000 mVAT +300°F +750 mV AT +75D F = -500 mV AT _50D F = -VS Order Number LM34Z See NS Package Z03A TLlH/8885-4 FIGURE 2. Full-Range Fahrenheit Temperature Sensor S8-1 cr---------------~------------------------------------------------~ II) C") ~ ~National ~~ (3 ~ PRELIMINARY ~ Semiconductor LM35/LM35A,LM35C/LM35CA,LM35D Precision Centigrade Temperature Sensors ~ General Description ~ C") ~ ..... ~ :5 The LM35 series are precision integrated·circuit tempera, ture sensors, whose output voltage is linearly proportional to the Celsius (Centigrade) temperature. The LM35 thus has an advantage over linear temperature sensors calibrated in • Kelvin, as the user is not required to subtract a large con· stant voltage from its output to obtain convenient Centi· grade scaling. The LM35 does not require any external cali· bration or trimming to provide typical accuracies of ± 14·C at room temperature and ±%·C over a full - 55 to + 150·C temperature range. Low cost is assured by trimming and calibration at the wafer level. The LM35's low output imped· ance, linear output, and precise inherent calibration make interfacing to readout or control circuitry especially easy. It can be used with Single power supplies, or with plus and minus supplies. As it draws only 60 p.A from its supply, it has very low self·heating, less than 0.1·C in still air. The LM35 is rated to operate over a-55· to + 150·C temperature range, while the LM35C is rated for a -40· to +110"C range (-10· with improved accuracy). The LM35 series is Connection Diagrams al(allable packaged in hermetic T0-46 transistor packages, while the LM35C is also available in the plastic TO-92 tran· sistor package. Features • • • • • • • • • • • Calibrated directly in • Celsius (Centigrade) Unear + 10.0 mV'·C scale factor 0.5·C accuracy guaranteeable (at + 25·C) Rated for full - 55· to + 150"C range Suitable for remote applications .Low cost due to wafer·level trimming Operates from 4 to 30 volts Less than 60 p.A current drain Low self·heating, o.oa·c in still air Nonlinearity only ±14·C typical Low impedance output, 0.1 n for 1 mA load Typical Applications To-46 Metal Can Package* {§) {§} +Vs Your +Vs 6 GNDO- OUTPUT ~DntI+1o.DntI/OC BDTTDMVlEW TLlH/5516-1 'case is connected to negative pin TL/H/5516-3 FIGURE 1. BasiC Centigrade Temperature Sensor (+:ZOC to + 150·C) Order Number LM35H, LM35AH, LM35CH, LM35CAH or LM35DH See NS Package H03H TO-92 Plastic Package BOTTOM VIEW ' TLlH/5516-2 $r-~ Order Number LM35CZ, orLM35DZ See NS Package Z03A . -Vs Choose Rl = - VS/50 ,.,. VOUT= + 1,500 mV at + 150"C = +250 mV at +2S'C = -550 mVat -55'C TL/H/5516-4 F1Gl:'RE 2,l7ull-Range Centigrade Temperature Sensor sa-2 r- Absolute Maximum Ratings Supply Voltage Output Voltage Output Current Storage Temp., TO-46 Package, T0-92 Package, Lead Temp. (Soldering, 10 seconds): TO-46 Package, TO-92 Package, s:: C1I ..... rs:: Co) + 35V to - 0.2V +6Vto -1.0V 10mA -60'C to + 1BO'C -60'Cto + 1500C Specified Operating Temperature Range: TMIN to TMAX (Note 2) LM35, LM35A - 55'C to + 150'C LM35C, LM35CA -40'C to + 110'C LM35D O'C to + 100'C Co) C1I ~ r- s:: Co) C1I (") ..... rs:: 300'C 260'C Co) C1I g..... Electrical Characteristics (Note 1) (Note 6) r- Parameter Accuracy (Note 7) Conditions Typical TA= +25'C TA= -10'C TA=TMAX TA=TMIN ±0.2 ±0.3 ±0.4 ±0.4 Nonlinearity (Note B) TMIN:S:TA:S:TMAX 0.18 Sensor Gain (Average Slope) TMIN:S:TA:S:TMAX +10.0 +9.9, +10.1 Load Regulation (Note 3) O:S: IL:S: 1 rnA TA= +25'C TMIN:S:TA:S:TMAX 0.4 0.5 1.0 Une Regulation (Note 3) TA= + 25'C 4V:S:VS:S:30V 0.01 0.02 0.05 Quiescent Current (Note 9) VS= +5V, +25'C Vs= +5V Vs= +30V, +25'C Vs=+30V 56 105 56.2 105.5 67 Change of Quiescent Current (Note 3) 4V:S:Vs:S:30V, +25'C 4V:S:Vs:S:30V Temperature Coefficient of Quiescent Current ±0.5 Typical 0.2 0.3 0.4 0.4 1.0 1.0 0.35 Tested Limit (Note 4) 1.0 1.0 1.5 'C 'c +10.0 +9.9, +10.1 mVrC 0.01 0.02 0.05 67 133 56 91 56.2 91.5 0.2 0.5 1.0 2.0 +0.39 +0.5 +2.0 In circuit of Figure t,IL =0 +1.5 Long Term Stability TJ=TMAX. for 1000 hours ±0.08 1.0 3.0 mV/mA mV/mA 0.1 mVIV mVIV /LA 114 p.A 116 /LA /LA 2.0 /LA /LA +0.39 +0.5 /LAf'C +1.5 +2.0 ·C O.OB 6B ·C Nole 1: Unless otherwise noted, Ihese specifications apply: - 55'C;:TJ;: + 150'C for the LM35 and LM35A; - 40';:TJ;: + I IO'C for the LM35C and LM35CA; and o';:TJ;: + 100'C forthe LM35D. Vs= +5Vdc and ILOAO=50 p.A. in the circuit of I'igUffJ2. These specmcations also apply from +2'C to TMAX in the Circuit of Specifications in boldface apply over the full rated temperature range. Nate 2: Thermal resistance of the T0-46 package is 44O'C/W. junclion to ambient, and 24'C/W junction to case. Thermal resistance of the TQ-92 package Is 180'C/W junction to ambient. Fl{JuffJ 1. S8-3 C 'c 'c 'c 0.3 0.1 68 Units (Max.) 0.15 1.0 131 C1I Design Limit (Note 5) ±0.5 0.4 0.5 Minimum Temperature for Rated Accuracy I Design Umit (Note 5) 3.0 0.2 0.5 Co) LM35CA (Note 10) LM35A Tested . Limit (Note 4) s:: • Electrical Characteristics (Note 1) (Note 6) (Continued) LM35 Parameter Conditions Typical ± .~ 0 J ~'r' 60 ....~ \ Minimum Supply Voltage vs. Temperature 120 ~100 w ~ 8 0 0 45 z • 10·92 j: Thermal Response In Stili Air Thermal Time Constant 400 :::0 co 80 i 60 .. ~:::0 ." ~ 40 " 20 0 -75 -25 75 125 25 TEMPERATURE ('CI 175 TL/H/5516-17 Quiescent Current vs. Temperature (lri Circuit of Figure 2.) 200 2.0 lBO 1.5 ...~'60 !Iiac '"o-co ~ 120 ~ i5 100 f3 5 BO 60 I,.,ooi"'" " 1- 0 0.5 .-1.0 175 -2.0 -75 E t..I~ • I!! -1.5 -25 25 75 125 TEMPERATURE ('CI lo.&.i ,w.If"'T TYPICAL· w iii! :::0 • 40 -75 ..... i"! ..... ~ :i! ac 0.5 "'" Accuracy vs. Temperature (Guaranteed) LM35 1.0 ac 140 u . Accuracy vs. Temperature (Guaranteed) L~35~_1- ~-I- III" n.J.: I!I'I LM35i -25 25 75 125 TEMPERA7URE ('CI 88-9 ac ac co 15 iii! 2.5 2.0 1.5 1.0 0.5 0 ~-0.5 1-1.0 !-1.5 ... -2.0 ""- i"II. -'" 111/"'" LM350 I I LM35C I I I.... TmCAL L + "'" ... ... I"~"'" -t- LfoI3~A 'tI3~C ,{,,3,0- -2.5 175 -75 -25 25 75 125 175 TEMPERATURE ('CI TUH/5516-IS Section 9 Filters Filters Section Contents Monolithic MF4 4th Order Switched Capacitor Butterworth Low Pass Filter .....•.....•..•..••.......•.......•....•......•.•. S 9·1 MF5 Universal Monolithic Switched Capacitor Filter .................•.........••••.•...........•...........•.... S 9·8 MF6 6th Order Switched Capacitor Butterworth Low Pass Filter ..•.............................•....•..•..••.•.•. S 9·9 MF10 Universal Monolithic Dual Switched Capacitor Filter ..•.•.•....•.•.•...................•..........•......• S 9·17 TP3052/TP3053/TP3054/TP3057 Monolithic Serial Interface CMOS CODEC/FILTER Family .•• : •...•..•.•...•.•.. S 9·28 TP3064/TP3067 Monolithic Serial Interface CMOS CODEC/FILTER Combos ......•......•....................... S 9-41 !: ~National PRELIMINARY :: ~ Semiconductor MF4 4th Order Switched Capacitor Butterworth Lowpass Filter General Description Features The MF4 is a versatile, easy to use, precision 4th order Butterworth lowpass active filter. Switched capacitor techniques eliminate extemal component requirements and alIowa clock tunable cutoff frequency. The ratio of the clock frequency to the lowpass cutoff frequency is internally set to 50 to 1 (MF4-50) or 100 to 1 (MF4-100). A Schmitt trigger clock input stage allows two clocking options, either selfclocking (via an external resistor and capacitor) for standalone applications, or for tighter cutoff frequency control, a TTL or CMOS logic compatible clock can be directly applied. The maximally flat passband frequency response together with a DC gain of 1 V/V allows cascading MF4 sections for higher order filtering. • • • • • • • • Low cost Easy to use No external components a-pin mini-DIP Cutoff frequency accuracy of ±0.3% Cutoff frequency range of 0.1 Hz to 20 kHz 5V to 14V operation Cutoff frequency set by external or internal clock Block and Connection Diagrams ALTER OUT 5 Dual-In-Llne Package y+ FILTER IN 4TH ORDER BUTTERWORTH lOWPASS FilTER ALTER IN ClKIN y- y+ CLKR AGND MF4CN l.Sh CLK IN AGHD ALTER y- OUT TOP VIEW TL/H/5064-2 Order Number MF4CN See NS Package NOSE CLKR L Sh TUH/5064-1 S9-1 Absolute Maximum Ratings Supply Voltage Power Dissipation 14V Operating Temperature Storage Temperature Lead Temperature (Soldering. 10 seconds) 500mW O"C to 70"C(MF4CN) 150·C 300"C Electrical Characteristics (Note 7) Parameter Conditions Typ Tested Limits Design Umlts Units (Umlts) 0.1 20k 0.1 10k \:iz(min) Hz (max) Hz (min) Hz (max) Y+ =5Y, Y- = -5Y Cutoff Frequency Range (fc) (Note 1) MF4-50 MF4-100 Supply Current fCLK= 250 kHz 2.5 Clock Feedthrough (Peak-ta-Peak) TA=25·C Filter Output 25 DC Gain (Ho) RSOURCE ~ 2 kO 0.0 ±0.15 Clock to Cutoff Frequency Ratio (fCLK/fc) TA=25·C MF4-50 MF4-100 49.98±0.3% 49.98±0.8% fCLK/fcTemperature Coefficient MF4-50 MF4-100 Stopband Attenuation At2fc -25.0 DC Offset Voltage MF4-50 MF4-100 -200 -400 Output Swing RL =5kO +4.0 -4.5 Output Short Circuit Current (Note 6) TA=25·C Source Sink 1.~ mA mA TA=25·C MF4-50 MF4-100 80 78 dB dB fCLK~250 kHz (Note 3.5 mA(max) mV 3) Dynamic Range '(Note 2) Additional Magnitude Response Test Points (Note 4) MF4-50 (fc= 5 kHz) Magnitude at MF4-100 (fc=2.5 kHz) Magnitude at ±15 dB (max) 49.98±0.6% (max) (max) ppml"C ppml"C -24.0 dB (min) mV mV +3.5 -4.0 50 V (min) V (min) TA=25·C fCLK=250 kHz f=6pOOHz f=4500 Hz -7.57 -1.44 f=3000 Hz f=2250Hz S9-2 -7.57±0.27 -1.44±0.12 dB (max) dB (max) ±0.2 ±0.1 dB (max) dB (max) Electrical Characteristics· (Note 7) (Continued) Parameter Conditions Typ Tested Limits Design Limits Units (Umlts) 0.1 10k 0.1 5k Hz (min) Hz (max) Hz (min) Hz (max) V+ =2.5V, V- = -2.5V Cutoff Frequency Range (Ie) (Note 1) MF4-S0 MF4-100 Supply Current fClK = 250 kHz 1.5 Clock Feedthrough (Peak-to-Peak) TA=25"C Filter Output 1S DC Gain (Ho) RSOURCE~2 kO 0.0 ±0.1S Clock to Cutoff Frequency Ratio (feLK lie) TA=2S"C MF4-S0 MF4-100 SO.07±0.3% SO.07±1.6% ICLKlIc Temperature Coefficient MF4-S0 MF4-100 Stopband Attenuation At2fc -2S.0 DC Offset Voltage MF4-S0 MF4-100 -1S0 -300 Output Swing RL =SkO 1.S -2.2 Output Short Circuit Current (Note 6) TA=2S'C Source Sink 28 O.S mA mA Dynamic Range (Note 2) TA=2S"C MF4-S0 MF4-100 80 78 dB dB fClK~250 2.25 mA(max) mV kHz (Note 3) Additional Magnitude Response Test Points (Note 4) MF4-S0 (lc=S kHz) Magnitude at MF4-100 (IC = 2.S kHz) Magnitude at dB (max) SO.07±0.6% ±2S (max) (max) ppm/'C ppml"C -24.0 dB (min) mV mV 1.0 -1.7 V (min) V (min) TA=2~'C fClK=2S0 kHz 1=6000 Hz f=4500Hz -7.S7 -1.46 1=3000 Hz f=2250Hz -7.S7±0.54 -1.46±0.24 dB (max) dB (max) ±0.2 ±0.1 dB (max) dB (max) , S9-3 Logic Input-Output Characteristics (Note 7) (V- = OV, Note 5) Parameter Conditions Typ Tested Umlts Design Umlts Units (Umlts) SCHMITT TRIGGER VT + Positive Going Threshold Voltage VT - Negative Going Threshold Voltage Hysteresis (VT + - VT-) V+=10V 7.0 V+=5V 3.5 V+=10V 3.0 V+=5V 1.5 V+=10V 4.0 V+=5V 2.0 6.1 8.9 3.1 4.4 V (min) V (max) V (min) V (max) 1.3 3.8 0.6 1.9 V (min) V (max) V (min) V (max) 2.3 7.6 1.2 3.8 V (min) V (max) V (min) V (max) Logical "1" Output Voltage (10 = -10 /LA) (Pin 2) V+=10V V+=5V 9.0 4.5 V (min) V (min) logical "0" Output Voltage (10= 10 /LA) (Pin 2) V+ =10V V+=5V 1.0 0.5 V (max) V (max) Output Source Current ClK R Shorted to Ground V+=10V V+=5V 6.0 1.5 3.0 0.75 mA(min) mA(min) ClK R Shorted to V+ V+=10V V-=5V .5.0 1.3 2.5 0.65 mA(min) mA(min) 0.8 V (max) Output Sink Current TTL CLOCK INPUT (CLK R PIN) (Note 8) VIL (logical "0" Input Voltage) VIH (logical "1" Input Voltage) leakage Current at ClK R Pin TA= 25D C, L. Sh Pin Tied to Mid-Supply 2.0 V (min) 2.0 /LA (max) Note 1: The cutoff frequency 01 the filter Is defined as the lrequency where the magnitude response is 3.01 dB less than the DC gain 01 the Iilter. Note 2: For ±5V supplies the dynamic range is referenced to 2.82 Vrms (4V peak) where the wldeband noise over a 20 kHz bandwidth Is typically p.Vrmsfor the MF4-50 and p.Vrms for the MF4-100. For ±2.5V supplies tha dynamic range Is relerenced to 1.06 Vrms (1.5V peak) where the wldeband noise over a 20 kHz bandwidth is typically p.Vrms for bo1h the MF4-50 and Ihe MF4-100. Note 3: The specifICations lor the MF4 have been given for a clock Irequency (ICLKl 01250 kHz and less. Above this clock lrequency Ihe cutoff frequency begins to deviate from the specified error band of ±0.6% but the filter still maintains its magnitude characteristics. See Application Hints. Note 4: Besides checking the cutoff frequency (fel and the stopband attenuation at 2 Ie. two additional frequencies are used to check the magnitude response 01 the filter. The magnitudes are referenced to a DC gain 01 0.0 dB. For a further discussion see Applications Hints. Nota 5: For simplicity all the logic lavels have been referenced to V- =OV (except for the TIL InpUilogic levels). The logic lavels will scale accordingly lor ±5V and ± 2.5V supplies. . Nota 6: The short circuit source current is measured by forcing the output that Is being lested to Its maxlmum positive voltage swing and then shorting that output to the negative supply. The short circuit sink current Is measured by lorcing the output thai is being tested to its maxlmum negative voltage swing and then shorting that output to the posHive supply. These are the worst-case ocndltions. Note 7: Unless o1herwlse stated, these specifications apply over the ocmmerclal temperature range 01 O"C"TA"7O'C. Note 8: The MF4 Is operating with symmetricel spill supplies and L. Sh is lied 10 ground. Missing Values and "Application Hints" section will be added on flna.- data sheet. S9-4 --------------------------------------------------~~ l! Pin Description FilTER OUT FilTER IN AGND V+,v- elKIN L. Sh This is the output of the lowpass filter: It will typically sink 0.90 mA and source 3 mAo Typically, the output will swing to within 1V of each supply rail. This is the input to the lowpass filter. To . minimize gain errors, the source impedance should be less than 2 kn. For more details see Application Hints section. Note that for single supply operation the input signal must be biased to mid-supply or AC coupled. This is the analog ground pin. This pin should be connected to the system ground for dual supply operation or biased to midsupply for single supply operation, see Figure 4. For a further discussion on midsupply biasing techniques see the Application Hints. For optimum filter performance a "clean" ground must be provided. These are the positive and negative supply pins. The MF4 will operate over a supply range of 5V to 14V. Decoupling the supply pins with 0.1 J.£F capacitors is highly recommended. This is the input of a CMOS Schmitt trigger. If an external CMOS logic level clock is to be used, it is applied to this pin. The level shift pin serves two purposes. One, the voltage at this pin sets the input switching threshold of an internal level shift stage. The level shift stage converts either TTL or CMOS logiC levels to full V+ ~o Vclock levels that are required by the internal non-overlapping clock generator. The threshold is approximately 2V above the voltage at the level shift pin. Second, the voltage at this pin enables or disables an internal TRI-STATE buffer between the Schmitt trigger and the level shift stage. When tied to V - , this buffer is enabled and the Schmitt trigger drives the level shift stage. When tied to mid-supply (ground where the MF4 is operating from symmetrical split supplies) or above, the buffer is disabled and is placed in a high impedance state. This allows an external TTL (if L. Sh is connected to ground) or CMOS logic level to be applied to the level shift stage via the ClK R pin. This pin serves as the input for a TTL logic level clock if the L. Sh pin is tied to ground and the MF4 is operating with dual supplies. In the self-clocking mode an external resistor is tied from this pin to the ClK IN pin and an external capacitor is tied from the ClK IN pin to ground. This creates a Schmitt trigger oscillator. When using the selfclocking mode the L. Sh pin must be tied to V-. ClKR DUAL SUPPLY OPERATION 5V-n n - 5V...J U L FILTER CLK IN y- -5Y-+--~ y+ C~ OY 5V MF4 L. Sh IN 5YJUlIN v+ CLK R FILTER CLK IN 5V MF4 AGND L. Sh y- FILTER OUT -5V----I TLlH/5064-3 AGND FlLT£R OUT TLlH/5064-4 FIGURE 1. MF4 Driven with CMOS Level Clock (VIH;;,O.8 Vee* and VIL:S:O.2 Vee) FIGURE 2. MF4 Driven with TTL Level Clock 'vcc=v+-v- S9-5 Lf :::& Pin Description (Continued) DUAL SUPPLY OPERATION C i FILTER IN fCLK RCin [(VCC-VT- )(VT+ )] VCC-VT+ VT- v+ 5Y Typically for Vcc= 10V MF4 l. Sh AGNO V-5V 1 fCLK= 1.69 RC ,FILTER OUT TUH/5064-5 FIGURE 3. MF4 Driven with Schmitt Trigger Oseillator SINGLE SUPPLY OPERATION If an extemal clock Is used, H has to be of CMOS level because the clock is Input to a CMOS SchmHt trigger. The AGND pin must be biased to mid....upply. The Input signal should be DC biased to mld·supply or AC coupled to the Input pin. 10Y'JlJL ov C~ ClK 1---...-1OV R MF4 l. Sh AGNO ..............:.V-_-I4 FilTER out TLlH/5064-6 FIGURE 48. MF4 Driven with an External Cloek FilTER IN V+ 10V fCLK= RC in [(VCC-VT-) (VT+)] VCC-VT+ VTTypically for Vcc= 10V MF4 AGNO 5V BIAS FilTER OUT . TUH/5064-7 An extemal Rand C can be used to generate an on·board clock; ff so, the L Sh pin should remain at ground. FIGURE 4b. MF4 Driven with the Schmitt Trigger Oscillator 59-6 1 fCLK = 1.69 RC Pin Description (Continued) OFFSET ADJUST v ,-ClKIN , C~_ 2 7 MF4 ..!::.!!!..v5Y · . ~t AGND 3 Y+ 5Y 10k 5 !-~:R 4 TUH/5064-8 FIGURE 5. Typical Circuit for AdJuatlng the DC Offset of the Filter. (See Application Hints on mid-supply bias generation) Filter Out should be referenced to AGND. 59-7 ~National a PRELIMINARY Semiconductor MF5 Universal Monolithic Switched Ca,pacitor Filter Gen~ral Features Description The MFS consists of an extremely easy to use. general pur• Low cost pose CMOS active filter building block and an uncommitted • 14-pin DIP op amp. The filter building block. together with an eXternal • Easy to use cl09k and a few resistors. can produce various second order • Clock to Center frequency ratio accuracy ±0.6% functions. The filter building block has 3 output pins. One of • Filter cutoff fr~quency stability directly dependent on the' output pins can be configured to perform highpa~s. allextemal clock quality pass' or notch functions and the remaining 2 output pins • Low sensitivity to extemal component variations perform bandpass and lowpass functions. The center frequency of the filter can be directly dependent on the clock ' • Separate highpass (or notch or allpass). bandpass. lowpass outputs frequl!ncy or it can depend on both clock frequency and • fo x Q range up to 200 kHz external resistor ratiOS. The uncommitted op amp can"'be used for cascading purposes. for obtaining additional all• Operation up to 30 kHz (typical) pass and notch functions. or for various other applications. • Additional uncommitted op-amp Higher order filter functions can be obtained by cascading several MFSs or by using the MFS in conjuction with the MF10 (dual switched capacitor filter building block). The MFS is functionally compatible with the MF10. Any of the classical filter configurations (such as Butterworth; Bessel. Cauer and Chebyshev) can be formed. ' , System Block Diagram v- BP 81 LP 14 INVl CLK ~,Vaz 12 INV2 , AllNO 5011l1li _ 13 +A2 LShU----I TUH/5066-1 Conne~tion, Diagram , Dual-In-Llne Package 14 8P N/AP/HP Voz INV2 INVI MF5 SI Order Number MF5J, N See NS Packages J14A, N14A AOND V- SA y+ LP 6 50/100 eLK LSI! TDPVIEW S9-8 TL/H/5068-2 !!: PRELIMINARY ~ ~National ~ Semiconductor MF6 6th Order Switched Capacitor Butterworth Lowpass Filter ' General Description Features The MF6 is a versatile easy to use, precision 6th order Butterworth lowpass active filter. Switched capacitor techniques eliminate external component requirements and alIowa clock tunable cutoff frequency. The ratio of the clock frequency to the lowpass cutoff frequency is internally set to 50 to 1 (MF6-50) or 100 to 1 (MF6-100). A Schmitt trigger clock input stage allows two clocking options, either selfclocking (via an external resistor and capacitor) for standalone applications, or for tighter cutoff frequency control, a TIL or CMOS logic compatible clock can be directly applied. The maximally flat passband frequency response together with a DC gain of 1 VIV allows cascading MF6 sections for higher order filtering. In addition to the filter, two independent CMOS op amps are included on the die and are useful for any general signal conditioning applications. • • • • • • • • • Low cost Easy to use Nc external components 14-pin DIP Cutoff frequency accuracy of ±0.3% Cutoff frequency range of 0.1 Hz to 20 kHz Two uncommitted op amps available 5V to 14V operation Cutoff frequency set by external internal clock Block and Connection Diagrams FlLTEI DUT Dual·ln·Une Package INVI N,INV2 AGND INY2 Vaz INV1 FILTER OUT YOI lSh MF&CN Vaz INV2 ClK R Y- AGNO eLK Y· IN FILTER IN Yos AOJ TOP VIEW TLlH/5065-2 Order Number MF6 See NS Package t414A CUll LSh, v· vTL/H/5065-1 S9-9 Absolute Mal,Cimum Ratings Supply Voltage Power Dissipation Operating Temperature 14V -500mW Storage Temperature Lead Temperature (Soldering. 10 seconds) 150"C 300·C O·C to 70·C (MFSCN) Electrical Characteristics (Filter) Parameter Conditions Typ Tested Umits (Note 8) Design Limits (Note 9) Units (Limits) 0.1 20k 0.1 10k Hz (min) Hz (max) Hz (min) Hz (max) Y+ = 5Y, Y- = -5Y, TA = 25"C Cutoff Frequency Range (fc) (Note 1) MFS-50 MFS-100 Supply Current Clock Feedthrough (Peak-to-Peak) fCLK=250 kHz ' 4.0 S.O rnA (max) Filter Output Op Amp /I 1 Output Op Amp /I 2 Output 30 25 20 mV mV mV RSOURCE,.;;2 kfl 0.0 ±0.3 dB (max) MFS-50 MFS-100 49.27±0.3% 9B.97±0.3% 49.27±1.0% 9B.97±1.0% (max) (max) fCLK/fc Temperature Coefficient MFS-50 MFS-100 25 25 Stopband Attenuation At2fc -37.5 Unadjusted DC Offset Voltage MFS-50 MFS-100 -300 -500 Output Swing RL =5kfl +4.0 -4.1 fCLK";; 250 kHz (Note 3) DC Gain (Ho) Clock to Cutoff Frequency Ratio (fCLK/fcl Output Short Circuit Current (Note S) ppml"C ppm/·C -3S dB (min) mV mV +3.5 -3.B V (min) V (min) Source Sink 50 1.5 rnA rnA MF6-50 MFS-100 83 81 dB dB Dynamic Range (Note 2) Additional Magnitude Response Test Points (Note 4) MFS-50 (fc=5 kHz) Magnitude at MFS-100 (fC=2.5 kHz) Magnitude at fCLK = 250 kHz 1=SOOOHz 1=4500 Hz -9.47 -0.92 -9.47±0.5 -0.92±0.2 dB (max) dB (max) f=3000Hz 1=2250 Hz -9.48 -0.97 -9.48±0.5 -0.97±0.2 dB (max) dB (max) Attenuation Rate MFS-50 (1c = 5 kHz) f1 = SOOOHz f2 = BOOO Hz -3S dB/octave MFS-100 (1c = 2.5 kHz) 11 = 3000 Hz 12 = 4000 Hz -3S dB/octave $9-10 Electrical Characteristics Parameter (Continued) (Filter) Typ Conditions Tested Limits (Note 8) Design Limits (Note 9) Units (Limits) 0.1 10k 0.1 Sk Hz (min) Hz (max) Hz (min) Hz (max) V+ =2.5V, V- = -2.5V, TA = 25'C Cutoff Frequency Range (fel (Note 1) MF6-S0 MF6-100 Supply Current fClK=2S0 kHz 2.S Filter Output Op Amp # 1 Output Op Amp #2 Output 20 10 10 RsouAce,,;2 kG 0.0 ±0.3 dB (max) MF6-S0 MF6-100 49.45±0.a% 99.35±0.3% 49.4S±1.0% 99.35±1.0% (max) (max) fClK/fc Temperature Coefficient MF6-S0 MF6-100 -15 90 Stopband Attenuation At2fc -37.S Unadjusted DC Offset Voltage MF6-S0 MF6-100 -200 -350 Output Swing Rl =SkG 1.5 -2.2 Clock Feedthrough (Peak-to-Peak) 4.0 mA(max) mV mV mV felK"; 250 kHz (Note 3) DC Gain (Ho) Clock to Cutoff Frequency Ratio (fClK/fel Output Short Circuit Current (Note 6) ppml'C ppm/'C -36 dB (min) mV mV 1.0 -1.7 V (min) V (min) Source Sink 28 O.S mA mA MF6-S0 MF6-100 77 77 dB dB Dynamic Range (Note 2) Additional Magnitude Response Test Points (Note 4) MF6-50 (fC=S kHz) Magnitude at MF6-100 (fC=2.5 kHz) Magnitude at Attenuation Rate MF6-S0 (fe = 5 kHz) MF6-100 (fe = 2.S kHz) fClK = 2S0 kHz f=6000Hz f=4500 Hz -9.54 -0.96 -9.54±0.S -0.96±O.3 dB (max) dB (max) f=3000 Hz f=22S0Hz -9.67 -1.01 -9.67±0.5 -1.01 ±0.3 dB (max) dB (max) f1 = 6000 Hz f2 = 8000 Hz -36 'dB/oclave f1 = 3000Hz f2 = 4000Hz -36 dB/octave S9-11 • Electrical Characteristics (Both Op Amps) Parameter Typ CondItions Tested Umlts (Note 8) DesIgn Umlts (Note 9) Units (Umlts) 67 dB (min) Y+ =5Y, Y-= -5Y, TA = 25°C DC Open Loop Gain 72 _ ~ain Bandwidth Product 1.2 Input Offset Voltage Output Swing RL =2.5kO MHz (min) ±8.0 ±20 mV(max) 4.0 -4.5 3.8 -4.0 V (min) V (min) Output Short Circuit Current (Note 6) CMRR (Op Amp #2 Only) Source Sink 45 2.5 VCMl = 1.8V VCM2 = -2.2V 60 mA mA 55 dB (min) Input Bias Current 10 pA Slew Rate 7.0 V1p.s Y+ =2.5V, Y-= -2.5Y, TA = 25"C DC Open Loop Gain 67 Gain Bandwidth Product 1.2 Input Offset Voltage Output Swing RL=2.5kO 62 dB (min) MHz (min) ±8.0 ±20 mV(max) 1.5 -2.2 1.3 -1.7 V (min) V (min) Output Short Circuit Current (Note 6) CMRR (Op Amp #2 Only) Source Sink 24 1.0 VCMl = 0.5V VCM2 = -0.9V 60 mA mA dB (min) 55 Input Bias Current 10 pA Slew Rate 6 V1p.s , S9-12 Logic Input-Output Characteristics (VParameter = OV. Note 5). TA = 25°C COnditions Typlca! Tested Uri'lits (Note 8) Design Umlts (Note 9) Units (Umlts) SCHMITT TRIGGER VT + Positive Going Threshold Voltage VT - Negative Going Threshold Voltage Hysteresis (VT+ -VT-) V+=10V 7.0 V+=5V 3.5 V+ =10V 3.0 V+=5V 1.5 V+=10V 4.0 V+=5V 2.0 6.1 8.9 3.1 4.4 V (min) V (max) V (min) V (max) 1.3 3.8 0.6 1.9 V (min) V (max) V (min) V (max) 2.3 7.6 1.3 3.8 V(min) V (max) V (miri) V (max) logical "1" Output Voltage (10= -10 /LA) (Pin 11) V+=10V V+=5V 9.0 4.5 V (min) V (min) logical "0" Output Voltage (10 = 10 /LA)(Pin 11) V+=10V V+=5V 1.0 0.5 V (max) V (maX) Output Source Current (Pin 11) ClK R Shorted to Ground V+=10V V+=5V 6.0 1.5 3.0 0.75 mA!min) mA(min) ClK R Shorted to V+ V+=10V V-=5V 5.0 1.3 2.5 0.65 mA(min) mA(min) 0.8 V.(max) Output Sink Current (Pin 11) TTL CLOCK INPUT (Cll( R PIN) (NOTE 7) VIL (logical "0" Input Voltage) VIH (logical "1" Input Voltage) leakage Current at elK R Pin L. Sh Pin Tied 2.0 V (min) 2.0 !LA (max) to Mid-Supply Note I: The cutoff frequency of the fllter is defined as the frequency where the magnitude response Is 3.01 dB less than the DC geln of the filter. Note 2: For ±5V supplies the dynamic range is referenced to 2.82 Vrms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 200 "Vrms for the MF6-50 and 250 "Vrms tor the MF6-IOO. For ±2.5V supplies the dynamic range is reterenced to 1.08 Vrms (1.5V peak) where the wideband noise over a 20 kHz bandwith is typically 140 "Vrms tor both the MF6-50 and the MF6-IOO. Note 3: The specifications for the MF6 have been given for a clock frequency (feud of 250 kHz and less. Above this clock frequency the cutoff frequency begins to deviate from the specified error bend of ±0.6% but the filter still maintains its magnitude characteristics. See Application Hints. Note 4: Besides checking the' cutoff frequency (fc) and the stopband attenuation at 2 fe, two addillonalfrequencies are ~ to check the magnitude response of the IiIter. The magnitudes are referenced to a DC gain of 0.0 dB. For a further discussion see Application HInts. Note 5: For simplicity ail the logic levels have been referenced to V- = OV (except for the TTL Input logic levels). The logic levels will scale accordingly tor ± 5V and ±2.5V supplies. Note 8: The short circuit source current is measured by forcing the output that is baing tested to Its maximum positive voltsge swing and then shorting that output to the negative supply. The short circuit sink current Is meaS\lf8d by forcing the output that is being tested to its maximum negative voltage swing and then shorting that output to the positive supply. These are the worst-<:ase conditions. Note 7: The MF6 Is operating with symmetrical split supplies end L Sh is tied to ground. Note 8: Guaranteed and 100% productioit teated. Note 9: Guaranteed, but not 100% production tested. These limits are not used to determine outgoing quality levels. "Application Hints" section will be added on final data sheet. S9-13 if :::E Pin Description FilTER OUT This Is the output of the lowpass filter. It will typically sink 0.90 rnA and source 3 rnA. Typically,ihe output will swing to within 1Y of each supply rail. YasADJ If needed, this pin is used to adjust the DC offset of the lowpass filter. A typical circuit is shown in F/{Jure 5, where a 50 kO pot is connected between Y+ and Y- and the wiper is connected to the Vas ADJ pin. If the Vas ADJ pin is not used it must be tied to AGND. The DC gain from the Vas AOJ pin to the output of the filter is 2.5 to 3.0. FilTER IN This is the input to the lowpass filter. To minimize gain errors, the source impedance should be less than 2 kO. For more details see Application Hints section. Note tl1at for single supply operation the input signal must be biased to mid-supply or AC coupled. Y02,INY2, N.INY2 Y02 is the output of op amp # 2. INY2 and N. INY2 are the inverting and non-inverting inputs of op amp #2, respectively. These are very high impedance inputs. YOI,INY1 YOI is the output and INY1 is the inverting input of op amp #1. I!IIY1 is also a high impedance input. The non-inverting input is connected to AGND (analog ground) . Internally. Both op amp #1 and op amp #2 will typically sink 1.8 rnA and source 3 rnA and will swing to within 1Y of each supply rail. AGND This is the analog ground pin. This pin should be connected to the system ground for dual supply operation or biased to midsupply for single supply operation, see Rgure 4. For a further discussion on midsupply biasing techniques see tile Application Hints. For optimum filter performance a "clean" ground must be provided. Y+,Y- ClKIN L.Sh CLKR These are the positive and negative supply pins. The MF6 will operate over a supply range of 5Y to 14V. Oecoupling the supply pins with 0.1 p.F capacitors is highly recommended. This is the input of a CMOS Schmitt trigger. If an external CMOS logic level clock is to be used, it is applied to this pin. The level shift pin serves two purposes. One, the voltage at this pin sets the input switching threshold of an internal level shift . stage. The level shift stage converts either TTL or CMOS logic levels to full Y+ to Yclock levels that are required by the internal non-overlapping clock generator. The threshold is approximately 2Y above the voltage at the level shift pin. Second, the voltage at this pin enables or disables an internal TRI-STATE buffer betWeen the Schmitt trigger and the level shift stage. When tied to Y -, this buffer is enabled and the Schmitt trigger drives the level shift stage. When tied to mid-supply (ground where the MF6 is operating from symmetrical split supplies) or above, the buffer Is disabled and is placed in a high impedance state. This allows an external TTL (if L. Sh is connected to ground) or CMOS logic level to be applied to the level shift stage via the ClK R pin. This pin serves as the input for a TTL logiC level cl9Ck if the L. Sh pin is tied t9 ground and the MF6 is operating with dual supplies. In the self-clocking mode an external resistor is tied from this pin to the ClK IN pin and an external capacitor is tied from the ClK IN pin to ground. This creates a Schmitt trigger oscillator. When using the selfclocking mode the L. Sh pin must be tied to Y-. DUAL SUPPLY OPERATION .!~~~---" CLXIN • FILTER IN JlI[ " -IV Tlll'VlIW TL/H/5D65-3 FIGURE 1. MF6 Driven with CMOS logic level Clock (VIH~O.8 Vee* and VILS:O.2 Vee) 'vcc=v+-v- TLiH/5065-4 FIGURE 2. MF6 Driven with TTL Logic Level Clock S9-14 Pin Description (Continued) DUAL SUPPLY OPERATION 141NYt 13 111¥1 12l.S11 lelK -IV [ (~:::~~:) (~~~) ] Typically lor Vcc= 10V 1 lelK = 1':ii9RC FIUER IN TLIH/5065-5 FIGURE 3. MF6 Driven with Schmitt Trigger Oscillator SINGLE SUPPLY OPERATION The AGND pin must be biased to mid·supply. The input signal should be DC biased to mid·supply or AC coupled to the input pin. 10V TO AGNO • or buffer with op amp # 2, then apply to AGND V022 FILTER 3 OUT Yo, 4 11 CLKR 10 V- AGNO 5 9 CLK IN 10V V· 6 Yo. ADJ 7 8 FllTERIN JU[ IOV OV ~5VOC TLIH/5065-6 II an external clock is used, it has to be 01 CMOS logic levels because the clock is Input to a CMOS Schmitt trigger. FIGURE 4a. MF6 Driven with an External Clock 10V 10k lelK 10k t--...::..:f-.. [ (~:::~~:) (~~~) ] Typically for Vcc· = 10V 1 lelK = 1.69 RC ·VCC=V+-V8 FILTER IN TOP VIEW TLIH/5065-7 An external Rand C can be used to generate an onboard clock, il so the L. Sh pin should remain at ground. FIGURE 4b. MF6 Driven with the Schmitt Trigger Oscillator , 59-15 If ~ Pin Description (Continued) OFFSET ADJUST N.IIIVZ.J • V ~..! l!.IMV1 !lUll ~..! ",oJ 1If&" .!lCUCI Itv- _DI - IV Ji INVZ 1.:' 1.:L1D ·v+ii "AlII 7 TUH/5085-8 FIGURE 5. Typical CircuIt for Adjusting Filter DC Offset If not used, connect Vos ADJ pin to AGND) S9-16 is: ." ..... Q ~Nattonal ~ Semiconductor MF10 Universal Monolithic Dual Switched Capacitor Filter General Description Features The MF10 consists of 2 independent and extremely easy to use, general purpose CMOS active filter building blocks. Each block, together with an external clock and 3 to 4 resistors. can produce various 2nd order functions. Each building block has 3 output pins. One of the outputs can be configured to perform either an allpass. highpass or a notch function; the remaining 2 output pins perform lowpass and bandpass functions. The center frequency of the lowpass and bandpass 2nd order functions can be either directly dependent on the clock frequency, or they can depend on both clock frequency and external resistor ratios. The center frequency of the notch and allpass functions is directly dependent on the clock frequency, while the highpass center frequency depends on both resistor ratio and clock. Up to 4th order functions can be performed by cascading the two 2nd order building blocks of the MF10; higher than 4th order functions can be obtained by cascading MF10 packages. Any of the classical filter configurations (such as Butterworth, Bessel. Cauer and Chebyshev) can be formed. • • • • • • • • • Low cost ,20-pin 0.3" wide package Easy to use Clock to center frequency ratio accuracy ± 0.6% Filter cutoff frequency stability directly dependent on external clock quality Low sensitivity to external component variation Separate highpass (or notch or allpass). bandpass. lowpass outputs fo x Q range up to 200 kHz Operation up to 30 kHz System Block Diagram 12 50/100/Cl 6 CONTROL +-DSu Lib CUIa roA~D'-------~~------~~ INV. Vi N/AP/HPa S1. TliH/5645-1 59-17 Absolute Maximum Ratings • Supply Voltage Power Dissipation Operating Temperature 14V 500mW Storage Temperature Lead Temperature (Soldering, 10 seconds) 1500C 3000C OOCt0700C Electrical Characteristics (Complete Filter)Vs= ±5V, TA=25°C Parameter Conditions Frequency Range f o XO<200 kHz Clock to Center Frequency Ratio, fCLK/fo MF10BN MF10CN MF10BN MF10CN Pin 12 High, 0=10 foXO<50 kHz, Mode 1 Pin 12 at Mid Supplies 0= 10, foXO<50 kHz, Mode 1 Min Typ 20 30 Max Units kHz 49.94±0.2% 49.94±0.2% 99.35±0.2% 99.35±0.2% ±0.6% ±1.5% ±0.6% ±1.5% f o XO<50kHz fo<5 kHz, Mode 1 ±2% ±6% fo Temperature Coefficient Pin 12 High (-50:1) Pin 12 Mid Supplies ( - 100:1) foXO<100 kHz, Mode 1 External Clock Temperature Independent ±10 ±100 ppm/DC ppml"C o Temperature Coefficient foXO<100 kHz, Setting Resistors Temperature Independent ±500 ppml"C DC Low Pass Gain Accuracy Mode 1, R1 = R2= 10k o Accuracy (0 Deviation from an Ideal Continuous Filter) o ±2 % Crosstalk 50 dB Clock Feedthrough 10 mV Maximum Clock Frequency 1 Power Supply Current 1.5 8 MHz 10 rnA Electrical Characteristics (Internal Op Amps) 25°C Parameter Coridltlons Supply Voltage Voltage Swing (Pins 1, 2, 19, 20) MF10BN MF10CN Vs= ±5V, RL =5k Voltage Swing (Pins 3 and 18) MF10BN MF10CN Vs= ±5V, RL =3.5k Output short Circuit Current Source Sink Vs= ±5V Op Amp Gain BW Product Op Amp Slew Rate S9-18 Max Units Min Typ ±4 ±5 V ±4.0 ±3.8 ±4.1 ±3.9 V V ±4.0 ±3.8 ±4.1 ±3.9 V V 3 1.5 rnA 2.5 MHz 7 V/IJ-S Definition of Terms HOHP: the gain in ry IV) of the highpass output of each Yz MF10 as f -+ fCLK/2, (Figure 3). Qz: the quality factor of the 2nd orde~. function complex zero pair, if any. (Qz is a parameter used when an allpass output is sought and unlike Q it cannot be directly measured). fz: the center frequency of the 2nd order function complex zero pair, if any. If fz is different from fa, and if the Qz is quite high it can be observed as a notch frequency at the allpass output. fnotch: the notch frequency observed at the notch output(s) of the MF-10. HON1: the notch output gain as f -+ 0 Hz. HON2: the notch output gain as f -+ fCLK/2. felK: the switched capacitor filter external clock frequency. fo: center of frequency of the second order function complex pole pair. fo is measured at the bandpass output of each Yz MF10, and it is the frequency of the bandpass peak occurrence.(Figure 1). Q: quality factor of the 2nd order function complex pole pair. Q is also measured at the bandpass output of each Yz MF10 and it is the ratio of fo over the -3 dB bandwidth of the 2nd order bandpass filter, (Figure 1). The value of Q is not measured at the lowpass or highpass outputs of the filter, but its value relates to the possible amplitude peaking at the above outputs. HOBP: the gain in ry IV) of the bandpass output at f = fo. HOlP: the gain in IV IV) of the lowpass output of each Yz MF10 at f -+ 0 Hz, (Figure 2). ;» ~ ~ BANDPASS OUTPUT /' HOBP O.7DT HoIP t - - . 11++-"'~ ,/1 1'''-. FIGURE 1 Hop ~ Hatr-- ;» i r LOWPASS OUTPUT '" 0.707 HOLP t----I----''I.. HOp = HOLP X _ - - 01.- - !.~11 Q 402 Ip I, I (LOG SCALE) FIGURE 2 E" i HoP HOHP 0.707 HOHP L 0. / Ie = 10 x [ Ip=loX ~-~~-----I, Ip I (LOG SCALE) Hop ~ 2~2) ~ ~) + ( 1_ [~1-~21 -1 = HOHP X _ - - 01.- - !.~11 Q 402 TL/H/5645-2 FIGURE 3 59-19 ( 1_ 2 + 1] -1 0 .... u. ::::E Connection Diagram Dual-In-Llne Package '. lJIa"'!. t!!. LP, 8PA..! ~8'" vA-vi) ~N/APlIIPa N/AP/HPA ...! INVA..! r!!-INVB 51A...! r!!- 51. vt L.Sh SAl'..! ~AGND vt.l .!!oVA' vt..J. .!!.Vii" 1t 5D/lDD/CL LSh..! ~CI.Ka ClKA..!! O' TOP VIEW TLlH/5645-3 Order Number MF10BN or MF10CN See NS Package N20A Pin Description LP, BP, N/AP/HR INV S1 can be bypassed by separate capacitors, if desired. They can be externally tied together and bypassed by a Single capacitor. Analog and digital negative supply respectively. The same comments as for and apply here. Level shift pin; it accommodates various clock levels with dual or single supply operation. With dual ± SV supplies, the MF10 can be driven with CMOS clock levels (± SV) and the L Sh pin should be tied either to the system ground or to the negative supply pin. If the same supplies as above are used but T2L clock levels, derived from OV to SV supply, are only available, the L Sh pin should be tied to the system ground. For single supply operation (OV and 10V) the V VA pins should be connected to the system ground, the AGND pin should be biased at SV and the L Sh pin should also be tied to the system ground. This will accommodate both CMOS and T2L clock levels. Clock inputs for each switched capaCitor filter building block. They should both be of the same level (T2L or CMOS). The level shift (L.Sh) pin description discusses how to accommodate their levels. The dLity cycle of the clock should preferably be close to SO% especially when clock frequencies above 200 kHz are used. This allows the maximum time for the op amps to settle which yields optimum filter operation. By tying the pin high a so: 1 clock to filter center frequency operation is obtained. Tying the pin at mid supplies (i.e., analog ground with dual supplies) allows the filter to operate at a 100:1 clock to center frequency ratio. When the pin is tied low, a simple current limiting circuitry is triggered to limit the overall supply current down to about 2.S mAo The filtering action is then aborted. Analog ground pin; it should be connected to the system ground for dual supply operation or biased at mid supply for single supply operation. The positive inputs of the filter op amps are connected to the AGND pin so "clean" ground is mandatory. The AGND pin is protected against static discharge. CLK (A or B) These are the lowpass, bandpass, notch or allpass or highpass outputs of each 2nd order section. The LP and BP outputs can sink typically 1 mA and source 3 mAo The N/AP/HP output can typically sink and source 1.S mA and 3 mA, respectively. This is the inverting input of the summing op amp of each filter. The pin has stati.c discharge protection. S1 is a signal input pin used in the allpass filter configurations (see modes of operation 4 and S). The pin should be driven with a source impedance of less than 1 kn. It activates a switch connecting one of the inputs of the filter's 2nd summer either to analog ground (SAIB low to VAl or to the lowpass output of the circuit (SAIB high to This allows flexibility in the various modes of operation of the IC. SAIB is protected against static discharge. Analog positive supply and digital positive supply. These pins are internally connected through the IC substrate and therefore and should be derived from the same power supply source. They have been brought out separately so they SO/100/CL VJJ. vt AGND vri S9-2O vri Modes of Operation a The MF10 is a switched ,capacitor (sampled data) filter. To fully describe its transfer functions, a time domain approach will be appropriate. Since this may appear cumbersome and, since the MF10 closely approximates continuous filters, the following discussion is based on the well known frequency domain. The following illustrations refer to Yo of the MF10; the other Yo is identical. Each MF10 can produce a full 2nd order function, so up to 4th order functions can be performed by using cascading techniques. BW HOBP HOLP=-a or HOBP= HOLPxO=HONxO. HOLP (peak) ""OXHOLP (for high a's) The above expressions are important. They determine the swing at each output as a function of the desired a 01 the 2nd order function. MODE 1a: Non-Inverting BP, LP (See Figure 5) = center frequency 01 the complex pole pair = fCLK or fCLK 100 50 fnotch = center Irequency 01 the imaginary zero pair= ' 0 " HOLP = Lowpass gain (as I _ a 0) = _ R2 R1 = ICLK or fCLK 100 50 R3 =R2 '" -1; HOLP (peak)""OXHOLP (for high a's) R3 HOBPl =-R2 HOLP HOBP = Bandpass ~ain (at 1= ' 0 ) = _ R3 R1 HON BW R2 = quality factor of the complex pole pair. =the -3 dB bandwidth of the bandpass output. Circuit dynamics: MODE 1: Notch 1, Bandpass, Lowpass Outputs: fnotch = fo (See Figure 4) fo a:::: HOBP2 = 1 (non-inverting) = Notch output gain as} 1 - 0- R2 R1 Circuit dynamics: HOBPl = a l-fCLK/2 FIGURE 4. MODE 1 . ~8 v+ TL/H/5645-4 FIGURE 5. MODE 1a S9-21 .... o ." =~=R3 .... 0 u. :IE Modes of Operation (Continued) MODE 2: Notch 2, Bandpass, Lowpass: 'notch ~ t-- §: -;;-- ., w , -2.0 -3.0 0.1 1.0 TLlHI5645-08 A SIMPLE AND INFORMATIVE FILTER DESIGN USING THEMF10 Example 1: Design a 4th order 2 kHz lowpass maximally flat (Butterworth filter). The overall gain of the filter is desired to be equal to lVIV. The 4th order filter can be built by cascading two 2nd order sections of (fo, a) equal to: 0=0.541, fo=2 kHz, 0= 1.306, fo=2 kHz. Due to the low a values of the filter, the dynamics of the circuit arEi very good. Any of the modes of operation can be used but Mode la is the most simple: Q-0.541 1,=2kHz IN-1 ~ 112 MF10 MODE I. R3/82=0.541 ifj J H Q=I.30& 1,=2 kHz ~OUT 1/2 MF10 MODEl. R3/R2=1.30& TLIHI5645-10 FIGURE 15 I Since for the first section the smallest resistor is R3, choose R3>5k. Assume R3=10k then R2=18.48k. For the second section choose R2 = 10k and then R3 = 13.06k. Both clock input pins (10, 11) can be tied together and then driven with a single external clock. If the approximate ratio fClK/l00 is chosen (pin 12 is grounded). then with a 200 kHz clock. the cultoff frequency. fe• will be at 2 kHz with a 1.5% maximum error. I -1.0 0.1 100 FIGURE 14 z -0.5 10 IDEAL Q C> co I I II C> , 0.0 II. -1.0 ;; IlIUm I-- ..... o - r- §: The curve for the fClKlfo ratio versus the ideal a has been normalized for a a of 10 which is the a value used for the fClKlfo ratio testing of the MF10. At this point the fClK/fo ratio is 49.94 in the 50:1 mode and 99.35 in the 100:1 mode. These values are within a maximum tolerance of ±0.6% (MF10B) and ±1.5% (MF10C). The above tolerances hold for the entire range of a's; in other words, at 50:1, an MF10B has a ratio of 49.94±0.6% (0=10) and this ratio becomes (49.44±0.6%) at 0=2.1. If these small errors cannot be tolerated, the clock frequency or the resistor's ratio, in Mode 3 and Mode 2, can be adjusted accordingly. fCLK_gg 35 f--I f I I 111111 t-- CLK=4994 t-- fo • ' ....... HOW TO USE THE felK/fo RATIO SPECIFICATION The MF10 is a switched capacitor filter designed to approximate the response of a 2nd order state variable filter. When the sampling frequency is much larger than the frequency band of interest, the sampled data filter is a good approximation to its continuous time equivalent. In the case of the MF10, this ratio is about 50:1 or 100:1. Nevertheless the filter's response must be examined in the z-domain in order to obtain the actual response. It can be shown that the clock frequency to center frequency ratio, fClKlfo and the quality factor, A, deviate from their ideal values determined in the continuous time domain. These deviations are shown graphically in Figures 13 and 14. The ratio, fClK/fo, is a function of the ideal a and the largest errors occur for the lowest values of O. 0.5 ." 1.0 lD 100 IDEAL Q TLlHI5645-9 FIGURE 13 The filter schematic is shown in Rgurs 16. ~'V~ VOUT- ~20 R3 Hz 19 18 17 LPs BPa N/API INV. LI'l N/API BPA HPA INVA 2 3 4 HPa n r:- 16 12 15 Q ' 3 S11 AGND Vi Vo 50/1001 CLKs CL MF1D U' 83 H2 SIA r SAIl 6 VIN J+ vt V{ J 18 ~ L Sh CLKA L T'I. eLK 200 kHz FIGURE 16. 4th Order, 2 kHZ Lowpass Butterworth Filter S9-25 TLIHI5645-11 Applications Information (Continued) With a ± 5V supply, each output node of the IC (pins 1, 2, 3, 18, 19, 20) will swing to ± 3.8V (MF10B) or ± 3.2V (MF10C). The maximum gain of 1.306 occurs at pin 19·at fo~2 kHz. The input voltage amplitude should be limited to less than 7.6 Vp-p/1.306=5.8 Vp-p. If the a of 1.306 section of the MF10 precedes the a of 0.541 section, the maximum gain is at pin 1. This gain can be calculated from the expression for Hop given in Definition of Terms, and equals 1.41. Getting Optimum Cutoff Frequency, feo Accuracy (If needed): In the previous example, an approximate 100:1 ratio was assumed. The true fClK/fo ratio should be read from the curves, Figures 13 and 14. At 100:1 the normalized ratio to . 0=10 is: fClK/fo =99.35. For a's of 0.541 and 1.306 this ratio becomes 99.35-0.75%=98.6. For a 2 kHz fe, the clock frequency should be 2 kHz x 98.6=197.2 kHz. With an MF10B and a 197.2 kHz clock, the maximum error on the 2 kHz cutoff frequency is ±0.6% as indicated in the specs. If only a 200 kHz is available in Mode 1a, the true yalue of fe and its maximum error is: 200 kHz/(98.6±0.6%)= 2028+0.6%. If only a 200 kHz is available and there is need for a tight tolerance cutoff frequency, then Mode 3 should be used instead of Mode 1a. The resistor ratios are: 2nd Section, Q= 1.306 1st Section, Q=0.541 R2/R4 = 0.972 . R2/R4=0.972 R3/R2 = 0.548 R3/R2 = 1.324 R4/R1 = 1 R4/R1 = 1 MF10 OFFSETS The switched capaCitor integrators of the MF10 have higher equivalent input offset than the typical R, C integrator of a discrete active filter. These offsets are created by a parasitic charge injection from the switches into the integrating capacitors; they are temperature and clock frequency independent and their sign is shown to be consistent from part to part. The input offsets of the CMOS op amps also add to the overall offset, but their contribution is very small. Figure 11 shows an equivalent circuit from where output DC offsets can be calculated. VOS1 VOS2 VOS3 =0 mV to ±10 mV = charge injected offset plus op amp offset "" -120 mV to -170 mV (at 50:1) = charge injected offset plus op amp offset eo< 100 mV to 150 mV (at 50:1) The VOS2 and VOS3 numbers approximately double at 100:1. , Output Offsets The DC offset at the BP output(s) of the MF10 is equal to the input offset of the lowpass switched capacitor integrator, VOS3. The DC offsets at the remaining outputs are roughly dependent upon the mode of operation and resistor ratios. Mode 1 and Mode 4 VOS(N) =VOS1 (~+1+ IIHolP") _ V~S3 VOS(BP) =VOS3 VOS(lP) =VOS(N)-VOS2 . 4(17) -- TUH/5645-12 FIGURE 17 89-26 Applications Information a: "TI ..... (Continued) o Comments on output DC offsets: For most applications, the outputs are AC coupled and the DC offsets are not bothersome unless large input voltage signals are applied to the filter. For instance, if the BP output is used and it is AC coupled, the remaining two outputs should not be allowed to saturate. If so, gain nonlinearities and fa, Q errors will occur. For Mode 3 of operation a word of caution is necessary: by allowing small R2/R4 ratios and high Q, the LP output will exhibit a couple of volts of DC offset and an offset adjustment should be made.. Mode 2 and Mode 5 VOS(N) R2) 1 = ( Rp ±1 VOS1X1+R2/R4 +V 1 OS2 1 + R4/R2 VOS3. Q,/1 + R2/R4' Rp=R1//R2//R4 VOS(BP) VOS(lP) =VOS3 =VOS(N)-VOS2 An extreme example: Design a 1.76 kHz BP filter with a Q of 21 and a gain equal to unity. The MF10 will be driven with a 250 kHz clock, and it will be switched 50:1. Mode 3 VOS(HP) VOS(BP) VOS(lP) =VOS2 =VOS3 Resistor values: - (R2 -VOS3+ VOS2 ) + = -R4 R2 R3 R3 1 R3 R2 =21 x 0.353 =59.63; R1 =1 R4( R2 1+ R2) Rp VOS1;Rp=R1//R3//R4 Since R3/R2 is the highest resistor ratio, start with R2 = 10k, then R3 "" 600k, R1 "" 600k, R4 = 80k. Assuming VOS1=2 mV, VOS2=-150 mV, V0S3=150 mV, the DC offset at the LP output is VOS(LP)= +1.2V. The offset adjustment will be done by injecting a small amount of current into the inverting input of the first op amp, Figure 18. This will change the effect VOS1, but the output DC offset of the HP and BP will remain unchanged. Mode 1a a VOS(N.lNV.BP) 1) VOS3 = ( 1+ VOS1- VOS(INV.BP) =VOS3 Vos(LP) =Vos(N.lNV.BP)-VOS2 0 fox f 50= 0.352; RR2 = 0.124 V'fR2R2 R4 = -elK 4 5V SUPPLY - ...~ r---.J.V\/Iv---- ••• >-..- ••• -- R3 "'---~'V'w-----FIGURE 18. Vos Adjust Scheme S9-27 ... TL/H/5845-13 ' ~ Semiconductor ~National r:~ TP3052/TP3053/TP3054/TP3057 Monolithic Serial Interface CMOS CODEC/FILTER Family General Description Features The TP3052, TP3053, TP3054, TP3057 family consists of /l-Iaw and A-law monolithic PCM COOEC/filters utilizing the AID and OIA conversion architecture shown in Figure 1, and a serial PCM interface. The devices are fabricated using National's advanced double-poly CMOS process (microCMOS). The encode portion of each device consists of an input gain adjust amplifier, an active RC pre-filter which eliminates very high frequency noise prior to entering a switched-capacitor band-pass filter that rejects signals below 200 Hz and above 3400 Hz. Also included are auto-zero circuitry and a companding coder' which samples the filtered signal and encodes it in the companded /l-Iaw or A-law PCM format. The decode portion of each device consists of an expanding decoder, which reconstructs the analog Signal from the companded /l-Iaw or A-law code, a low-pass filter which corrects for the sin xIx response of the decoder output and rejects Signals above 3400 Hz and is followed by a singleended power amplifier capable of driving low impedance loads. The devices require two 1.536 MHz, 1.544 MH~ or 2.048 MHz transmit and receive master clocks, which may be asynchronous; transmit and receive bit clocks, which may vary from 64 kHz to 2.048 MHz; and transmit and receive frame sync pulses. The timing of the frame sync pulses and PCM data is compatible with both industry standard formats. • CompletE:! CODEC' and filtering system (COMBO) including: - Transmit high-pass and low-pass filtering - Receive low-pass filter with sin xIx correction - Active RC noise filters - /l-Iaw or A-law compatible COder and DECoder - Internal precision voltage reference - Serial 110 interface -Internal auto-zero circuitry • /l-Iaw with signaling, TP3020 timing-TP3052 • /l-Iaw with signaling, TP5116A family timing-TP3053 • /l-Iaw without signaling, 16-pin-TP3054 • A-law, 16-pin-TP3057 • Meets or exceeds all 03/04 and CCITT specifications • ± 5V operation , • Low operating power-typically 60 mW • Power-down standby mode-typically 3 mW • Automatic power-down • TTL or CMOS compatible digital interfaces • Maximizes line interface card circuit density Connection Diagrams Dual-/n-Une Package Dua/-/n-Llne Package . 1 Va. 18 vFxI + GNDA 2 15 VFxI- GNDA 2 17 VFxI- VfAD 14 GSx VIitO 3 Vaa 1 16 VFxI+ Vee FSt! Vaal 20 VFxI+ 19 GNDA TP3D52 14 FSx 13 Ox MCLKx FSR OSx 17_ TSx TP3053 DR BCLKaI 7 CLKSEL 12 BCLKx , BCLKa! 7 CLKSEL MCLKaI • PDN 9 SIGa 11 MCLKa 10 SIGx MCLKa! • PDN 9 TOP VIEW VFxl- 1. VFRO Vee TP3054 TP3857 DR BCLKa! 7 CLKSEL MCLKaI PDN Dual-/n-Une Package Slit SIIlR 10 11 SIGx TOP VIEW TOP VIEW Order Number TP3054J or TP3057J NSPackage Number J16A Order Number TP3052J NS Package Number J18A S9-28 TL/H/5510-1 Order Number TP3053J NS Package Number J20A --------------------------------------------------------------------------,~ "V Block Diagram Co) C) en R2 I\) ...... ---------------------,I os. -I "V Co) C) en I Co) ...... I I I VFxI+ '::' -I "V Co) C) en I I I ...... "'" ~ II I I ~ en -." I I I I I D. SFx SF!! SIOx SIOx wlAW SIGNAUNG CONTRDL TIMING (TP30521 T1'3D53 DNLY) CONTROL AND I I I II I I =~ ~: ~:: +5V -5V L-1-t-4-----~~~NS Va. Vee GNOA --1 MCLKx MCLKaI BCLKx BCLII,I PON CLIISEL FSo· FS. TL/H/5510-2 FIGURE 1 Pin Description TP3052 Pin No. TP3053 Pin No. 1 2 3 4 5 1 2 3 4 5 6 TP3054 TP3057 Pin No. 1 Function Name 2 3 4 5 Vee GNDA VFRO Vee FSR 6 6 DR 7 7 7 BClKR/ClKSEl 8 8 8 S9·29 Negative power supply pin. Vee = -5V ± 5%. Analog ground. All signals are referenced to this pin. Analog output of the receive filter. Positive power supply pin. Vee= + 5V ±.5%. Receive frame sync pulse which enables BClKR to shift PCM data into DR. FSR is an 8 kHz pulse train. See Rgur8s 2 and 3 for timing details. Receive data input. PCM data is shifted into DR following the FSR leading edge. The bit clock which shifts data into DR after the FSR leading edge. May vary from 64 kHz to 2.048 MHz. Alternatively. may be a logic input which selects either 1.536 MHz/1.544 MHz or 2.048 MHz for master clock in synchronous mode and BClKx is used for both transmit and receive directions (see Table 1). Receive'master clock. Must be 1.536 MHz. 1.544 MHz or 2.048 MHz. May be asynchronous with MCLKx. but should be synchronous with MClKx for best performance. When MClKR is connected continuously low. MClKx is selected for all intemal timing. When MClKR is connected continuously high. the device is powered down. ..,..... 0 C") D. I...... .., 0:1' Pin Description TP3052 Pin No. 0 SFR 9 10 SIGR 10 11 SIGx 12 SFx D. .., C") 0 C") D. Name 9 C") I...... (Continued) TP3054 TP3057 PinNo• TP3053 PlnNo. Function I...... .., (\! 0 C") D. I- 11 13 9 MClKx 14 16 12 FSx 12 14 10 BClKx 13 15 11 Ox 15 17 13 TSx 16 18 14 ~Sx 17 18 19 20 15 16 VFxl VFxl + When high during FSR, this input indicates a receive signal frame. The eighth bit of the PCM data appears at this output after each receive signaling frame . Signal data input. Data at this input is insert!!d into . the 8th bit 6f the PCM word during transmit signaling frames. When high during FSx, this input indicates a transmit signaling frame. Transmit master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be asynchronous with MClKR· Transmit frame sync pulse input which enables BClKx to shift out the PCM data on Ox: FSx is an 8 kHz pulse train, see Figures 2 and 3 for timing details. The bit clock which shifts out the PCM data on Ox. May vary from 64 kHz to 2.048 MHz, but must be synchronous with MClKx. The TRI-STATE® PCM data output which is enabled by FSx. Open drain output which pulses low during the encoder time sial Analog output of the transmit input amplifier. Used to externally set gain. Inverting input of the transmit input amplifier. Non-inverting input of the transmit input amplifier. Functional Description POWER-UP When power is first applied, power-on reset circuitry initializes the COMBO and places it into the power-down mode. All non-essential circuits are deactivated and the Ox and VFRO outputs are put in high impedance states. To powerup the device, a logical low level or clock must be applied to the MClKR/PON pin and FSx and/or FSR pulses must be present. Thus, 2 power-down control modes are available. The first is to pull the MClKR/PON pin high; the alternative is to hold both FSx and FSR inputs continuously low-the device will power-down approximately 2 ms after the last FSx or FSR pulse. Power-up will occur on the first FSx or FSR pulse. The TRI-STATE PCM data output, Ox; will remain in the high impedance state until the second FSx pulse. directions. Table 1 indicates the frequencies of operation which can be selected, depending on the state of BClKRI ClKSEL. In this synchronous mode, the bit clock, BClKx, may be from 64 kHz to 2.048 MHz, but must be synchronous with MClKx. Each' FSx pulse begins the encoding cycle and the PCM data from the previous encode cycle is shifted' out of the enabled Ox output on the positive edge of BClKx. After 8 bit clock periods, the TRI-STATE Ox output is returned to a high impedance state. With an FSR pulse, PCM data is latched via the DR input on the negative edge of BClKx (or BClKR if running). FSx and FSR must be synchronous with MClKx/R· TABLE I. Selection of Master Clock Frequencies SYNCHRONOUS OPERATION For synchronous operation, the same·master clock and bit clock should be used for both the transmit and receive directions. In this mode, a clock must be applied to MClKx and the MClKR/PON pin can be used as a power-down control. A low level on MClKR/PON powers up the device and a high level powers down the device. In either case, MClKx will be selected as the master clock for. both the transmit and receive circuits. A bit clock must also be applied to BClKx and the BClKR/ClKSEl can be used to select the proper internal divider for a master clock of 1.536 MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame. Mastel' Clock Frequency selected BCLKR/CLKSEL TP3057 Clocked 0 1 (or Open Circuit) With a fixed level on the BClKR/ClKSEl pin, BClKx will be selected as the bit clock for both the transmit and receive S9-30 2.048 MHz 1.536 MHz or 1.544 MHz 2.048 MHz TP3052 TP3053 TP3054 1.536 MHz or 1.544 MHz 2.048 MHz 1.536 MHz or 1.544 MHz -----------------------------------------------------------------------,~ Functional Description Signaling for the TP3052 is accomplished by applying a frame sync pulse two bit clock periods long, as shown in Figure 2. With FSx two bit clock periods long, the data present at SIGx input will be inserted as the LSB in the PCM data transmitted during that frame. With FSR two bit clock periods long, the LSB of the PCM data read into the DR input will be latched and appear on the SIGR output pin until updated following the next signaling frame. The decoder will then interpret the lost LSB as "Yz" to minimize noise and distortion. This short frame signaling may also be implemented using the TP3053, providing SFR and SFx are left open circuit or tied low. The TP3052 is not capable of inserting or extracting signaling information in the long frame mode. Signaling for 'the TP3053 may be accomplished in either short or long frame sync mode. The short mode signaling is the same as the TP3052. For long frame signaling, two additional frame sync pulses are required, SFx and SFFi, which indicate transmit and receive signaling frames, respectively. With an SFx signaling frame sync, the data present at the SIGx input will be inserted as the LSB in the PCM data transmitted during that frame. With an SFR signaling frame sync, the LSB of the PCM data at DR will be latched and appear on the SIGR output pin until the next signaling frame. The decoder will also do the "Yz" step interpretation to compensate for the loss of the LSB. (Continued) ASYNCHRONOUS OPERATION For asynchronous operation, separate transmit and receive clocks may be applied. MCLKx and MCLKR must be 2.048 MHz for the TP3057, or 1.536 MHz, 1.544 MHz for .the TP3052, 53, 54, and need not be synchronous. For best transmission performance, however, MCLKR should be synchronous with MCLKX, which is easily achieved by applying only static logic levels to the MCLKR/PDN pin. This will automatically connect ¥CLKx to all internal MCLKR functions (see Pin Description). For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame. FSx starts each encoding cycle and must be synchronous with MCLKx and BCLKx. FSR starts each decoding cycle and must be synchronous with BCLKR. BCLKR must be a clock, the logic levels shown in Table 1 are not valid in asynchronous mode. BCLKx and BCLKR may operate from 64 kHz to 2.048 MHz. SHORT FRAME SYNC OPERATION o The COMBO can utilize either a short frame sync pulse (the same as the TP3020/21 CODECs) or a long frame sync pulse (the same as the TP5116A family of CODECs). Upon power initialization, the device assumes a short frame mode. In this mode, both frame sync pulses, FSx and FSR, must be one bit clock period long, with timing relationships specified in Figure 2. With FSx high during a falling edge of BCLKx, the next rising edge of BCLKx enables the Dx TRISTATE output buffer, which will output the sign bit. The following seven rising edges clock out the remaining seven bits, and the next falling edge disables the Dx output. With FSR high during a falling edge of BCLKR (BCLKx in synchronous mode), the next falling edge of BCLKR latches in the sign bit. The following seven falling edges latch in the seven remaining bits. All four devices may utilize the short frame sync pulse in synchronous or asynchronous operating mode. TRANSMIT SECTION The transmit section input is an operational amplifier with provision for gain adjustment using two external resistors, see Figure 4. The low noise and wide bandwidth allow gains in excess of 20 dB across the audio passband to be realized. The op amp drives a unity-gain filter consisting of RC active pre-filter, followed by an eighth order switched-capacitor bandpass filter clocked at 256 kHz. The output of this filter directly drives the encoder sample-and-hold circuit. The AID is of companding type according to Jol.-Iaw (TP3052, TP3053, TP3054) or A-law (TP3057) coding conventions. A precision voltage reference is trimmed in manufacturing to provide an input overload (tMAXl of nominally 2.5V peak (see table of Transmission Characteristics). The FSx frame sync pulse controls the sampling of the filter output, and then the successive-approximation encoding cycle begins. The 8-~it code is then loaded into a buffer and shifted out through Dx at the next FSx pulse. The total encoding delay will be apprOximately 165 Jol.S (due to the transmit filter) plus 125 Jol.S (due to encoding delay), which totals 290 Jol.S. Any offset voltage due to the filters or comparator is cancelled by sign bit integration. LONG FRAME SYNC OPERATION To use the long (TP5116A-type) frame mode, both the frame sync pulses, FSx and FSR, must be three or more bit clock periods long, with timing relationships speCified in Figure 3. Based on the transmit frame sync, FSx, the COMBO will sense whether short or long frame sync pulses are being used. For 64 kHz operation, the frame sync pulse must be kept low for a minimum of 160 ns. The Dx TRI-STATE output buffer is enabled with the rising edge of FSx or the riSing edge of BCLKx, whichever comes later, and the first bit clocked out is the sign bit. The following seven BCLKx rising edges clock out the remaining seven bits. The Dx output is disabled by the falling BCLKx edge following the eighth riSing edge, or by FSx going low, whichever comes later. A riSing edge on the receive frame sync pulse, FSR, will cause the PCM data at DR to be latched in on the next eight falling edges of BCLKR (BCLKx in synchronous mode). All four devices may utilize the long frame sync pulse in synchronous or asynchronous mode. RECEIVE SECTION The receive section consists of an expanding DAC which drives a fifth order switched-capacitor low pass filter clocked at 256 kHz. The decoder is A-law (TP3057) or Jol.-Iaw (TP3052, TP3053, TP3054) and the 5th order low pass filter corrects for the sin x/x attenuation due to the 8 kHz sample/hold. The filter is then followed by a 2nd order RC active post-filter/power amplifer capable of driving a 600n load to a level of 7.2 dBm. The receive section is unity-gain. Upon the occurrence of FSR, the data at the DR input is clocked in on the falling edge of the next eight BCLKR (BCLKxl periods. At the end of the decoder time slot, the decoding cycle begins, and 10 Jol.S later the decoder DAC output is updated. The total decoder delay is - 10 Jol.S (decoder update) plus 110 Jol.S (filter delay) plus 62.5 Jol.S (Yz frame), which gives approximately 180 Jol.S. SIGNALING The TP3052 and TP3053 Jol.-Iaw COMBOs contain circuitry to insert and extract signaling information in the PCM data stream. The TP3052 is intended for short frame sync appli. cations, and the TP3053 for long frame sync applications, although the TP3053 may also be used in short frame sync applications. The TP3054 and TP3057 have no provision for signaling. S9-31 "U Co) CI U'I N ...... ~ "U Co) CI U'I Co) ...... -f "U Co) CI U'I ~ ...... ~ "U Co) CI !:!] Absolute Maximum Ratings Vee to GNDA VBBtoGNDA Voltage at any Analog Input or Output 7V Voltage at any Digital Input or Output Vee + 0.3V to GNDA-0.3V - 25'C to + 125~C Operating Temperature Range -65'C to + 1500C Storage Temperature Range Lead Temperature (Soldering. 10 seconds) 3000C -7V Vee+0.3Vto VBB-0.3V Electrical Characteristics Unless otherwise noted: Vee = 5.0V ± 5%. VBB = - 5V ± 5%. GNDA = OV. TA= OOC to 700C; typical characteristics specified at Vee = 5.0V. VBB = - 5.0V. TA= 25'C; all signals are referenced to GNDA. Symbol I Parameter DIGITAL INTERFACE VIL I Conditions I Min I Typ I Input Low Voltage Max 0.6 2.2 I Units V VIH Input High Voltage VOL Output Low Voltage Dx.IL ,:,3.2 mA SIGR. IL = 1.0 mA TSX.IL =3.2 mAo Open Drain V VOH Output High Voltage Dx.IH= -3.2 mA SIGR.IH= -1.0 mA 2.4 2.4 IlL Input Low Current GNDAS:VINS:VIL. All Digital Inputs -10 10 ".A IIH Input High Current VIHS:VINS:Vee -10 10 ".A loz Output Current in High Impedance State (TRI-STATE) Ox. GNDAS:Vo,,;:Vee -10 10 p.A 200 0.4 0.4 0.4 V V V V V, ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES) IIXA Input Leakage Current -2.5VS:VS:+2.5V. VFxl+ orVFxl- -200 RIXA Input Resistance -2.5Vs:Vs: +2.5V. VFXI+ orVFXI- 10 RoXA Output ReSistance Closed Loop. Unity Gain RLXA LOad Resistance GSx CLXA Load CapaCitance GSx VoXA Output Dynamic Range GSx. RLS:l0 kO ±2.8 V AvXA Voltage Gain VFxl+ toGSx 5000 VlV 1 3 10 0 kO 50 1 nA MO FuXA Unity Gain B!lndwidth VosXA Offset Voltage -20 2 20 -2.5 2.5 pF MHz mV VCMXA Common-Mode Voltage CMRRXA Common-Mode Rejection Ratio 60 dB V PSRRXA Power Supply Rejection Ratio 60 dB ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES) RoRF Output Resistance PinVFRO RLRF Load Resistance VFRO= ±2.5V CLRF Load Capacitance VOSRO Output DC Offset Voltage 1 3 0 500 pF 200 mV 600 0 -200 POWER DISSIPATION (ALL DEVICES) leeO Power-Down Current 0.5 1.5 mA IBBO Power-Down Current 0.05 0.3 rnA lee1 Active Current 6.0 9.0 rnA IBBl Active Current 6.0 9.0 mA S9-32 Timing Specifications Symbol l/tpM Parameter Frequency of Master Clocks Conditions Min Typ Max 1.5S6 1.544 2.048 Depends qn the Device Used and the BClKR/ClKSEl Pin. MClKx and MClKR Units MHz MHz MHz twMH Width of Master Clock High MCLKx and MClKR 160 tWML Width of Master Clock low MClKx anil MClKR 160 ns tRM Rise Time of Master Clock MCLKx and MClKR 50 ns tFM Fall Time of Master Clock MClKx and MClKR 50 ns tSBFM Set-Up Time from BClKx High (and FSx in long Frame Sync Mode) to MClKx Falling Edge First Bit Clock after the leading EdgeofFSx 100 ns 15.725 ns ns 100 tpB Period of Bit Clock tWBH Width of Bit Clock High VIH=2.2V 485 160 488 twBL Width of Bit Clock low VIL=0.6V 160 tRB Rise Time of Bit Clock tpB=488 ns 50 ns tFB Fall Time of Bit Clock tpB=488 ns 50 ns tHBF Holding Time from Bit Clock low to Frame Sync long Frame Only 0 ns tHOLO Holding Time from Bit Clock High to Frame Sync Short Frame Only 0 ns tSFB Set-Up Time from Frame Sync to Bit Clock low long Frame Only 80 ns tOBO Delay Time from BClKx High to Data Valid load = 150 pF plus 2 lSTTl loads 0 txop Delay Time to TSx low load = 150 pF plus 2 lSTTl loads 140 ns toze Delay Time from BClKx low to Data Output Disabled CL =0 pFto 150 pF 50 165 ns tozF Delay Time to Valid Data from FSx or BClKx. Whichever Comes Later CL=OpFto150pF 20 165 ns tSSFF Set-Up Time from SFXlR High to FSX/R TPS05S0nly 60 ns IssFB Set-Up Time from Signal Frame Sync High to BClKx/R Clock . TP3053 Only 60 ns ns ns 140 ns tsSGB Set-Up Time from SIGx to BClKx TP3052 and TPS05S 100 ns tHBSG Hold Time from BClKx High to SIGx TP3052 and TP3053 50 ns tsOB Set-Up Time from DR Valid to BClKR/X low 50 ns tHBO Hold Time from BClKR/X low to DR Invalid 50 ns tOFSSG Delay Time from BClKR/X low to SIGR Valid load = 50 pF plus 2 lSTTl loads tHBSF Hold Time from BClKx/R low to Signaling Frame Sync TPS05S0nly 100 ns tsF Set-Up Time from FSX/R to BClKx/Rlow Short Frame Sync Pulse (lor 2 Bit Clock Periods long) (Note 1) 50 ns tHF Hold Time from BClKx/R low to FSX/R low Short Frame Sync Pulse (lor 2 Bit Clock Periods long) (Note 1) 100 ns tHBFI Hold Time from Srd Period of Bit Clock low to Frame Sync (FSxor FSR) long Frame Sync Pulse (from 3 to 8 Bit Clock Periods long) 100 ns tWFL Minimum Width of the Frame Sync Pulse (low level) 64k Bitls Operating Mode 160 ns Note 1: For short frame sync timing, FSx and FSR must go high whHe their respective bit clocks are high. S9-3S SOO ns TP3052/TP3053/TP3054/TP3057 ::t 3 5' CO c S' CO DI 3 en BeLKR FSR DR SIGR FIGURE 2. Short Frame Sync Timing -I 3" S" ea MeLK. C ~" MCLK, BClK, -, FS, Dl 3 til g a :l 16 s SF, SIGx en CO l:J Ox U1 BCl"" FS. SfR D. SIGa TL/H/5S10-4 FIGURE 3" Long Frame Sync Timing lSO&d!/tSO&d!/&SO&d!/~SO&d! Transmission Characteristics (All Devices) Unless otherwise specified: TA =O·C to 70·C, Vcc= SV ± S°,{" Vee = -SV ± S%, GNDA = OV, f= 1.02 kHz, VIN = 0 dBmO, tral)smit input amplifier connected for unity-gain non-inverting. Symbol I I Parameter COnditions I Min I Typ I, Max I Units AMPLITUDE RESPONSE Absolute Levels tMAX Nominal 0 dBmO Level is 4 dBm (6000) OdBmO TP30S2,TP30S3,TP30S4 TP30S7 1.2276 1.2276 Vrms Vrms Max Overload Level TP30S2, TP30S3, TP30S4 (3.17 dBmO) TP3057 (3.14 dBmO) 2.501 2.492 VPK VPK GXA Transmit Gain, Absolute TA=2S·C, VCC=SV, Vee = -SV Input at GSx=O dBmO at 1020 Hz GXR Transmit Gain, Relative to GXA f=16Hz f=50Hz f=60Hz f=200Hz f=300 Hz-30oo Hz .1=3300 Hz f=3400Hz f=4000Hz f = 4600 Hz and Up, Measure Response from 0 Hz to 4000 Hz , -0.1S -1.B -0.15 -0.35 -0.7 0.15 dB -40 -30 -26 -0.1 0.15 O.OS 0 -14 -32 dB dB dB dB dB dB dB dB dB GXAT Absolute Transmit Gain Variation with Temperature TA =O"C to BO·C ±0.1 dB GXAV Absolute Transmit Gain Variation with Supply Voltage Vcc=SV±5%, Vee= -5V±5% ±0.05 dB GXRL Transmit Gain Variations with Level . Sinusoidal Test Method Reference Level = -10 dBmO VFxl+ = -40 dBmO to +3 dBmO VFxl + = - SO dBmO to -40 dBmO VFxl+ = -S5 dBmO to -50 dBmO -0.2 -0.4 -1.2 0.2 0.4 1.2 dB dB dB TA=25·C, Vcc=5V, Vee = -5V Input = Digital Code Sequence for dBmO Signal at 1020 Hz -0.15 0.15 dB -0.15 -0.35 -0.7 0.15 0.05 0 -14 dB dB dB dB ±0.1 dB ±0.05 dB GRA Receive Gain, Absolute GRR Receive Gain, Relative to GRA f=OHzt03000Hz f=3300Hz f=3400Hz f=4000 Hz GRAT Absolute Receive Gain Variation with Temperature TA =O·C to GRAV Absolute Receive Gain Variation with Supply Voltage Vcc=5V±S%, Vee = -5V±5% Receive Gain Variations with Level Sinusoidal TeSt Method; Reference Input PCM Code Corresponds to an Ideally Encoded-1 0 dBmO Signal PCM Level = -40 dBmO to + 3 dBmO PCM Level = -50 dBmO to -40 dBmO PCM Level = -55 dBmO to -50 dBmO -0.2 -0.4 -1.2 0.2 0.4 1.2 dB dB dB RL=6000 -2.5 2.5 V o .GRRL VRO Receive Output Drive Level eo·c S9-36 Transmission Characteristics (Continued) (All Devices) Unless otherwise specified: TA = O'C to 70'C, Vcc= 5V ±5%, Vaa = - 5V ± 5%, GNDA = OV, f= 1.02 kHz, VIN = 0 dBmO, transmit input amplifier connected lor unity-gain noninverting. Symbol I - Parameter I Conditions I Min I Typ I . Max I 290 315 ,...S 195 120 50 20 55 BO 130 220 145 75 40 75 105 155 ,...S ,...S ,...S ,...S ,...S ,...S ,...S 1BO Units ENVELOPE DELAY DISTORTION WITH FREQUENCY Transmit Delay, Absolute f=1600Hz DXR Transmit Delay, Relative to DXA 1=500 Hz-600 Hz f=600 Hz-BOO Hz I=BOO Hz-1000 Hz f=1000 Hz-1600 Hz f= 1600 Hz-2600 Hz 1=2600 Hz-2BOO Hz f=2BOO Hz-3000 Hz ORA Receive Delay, Absolute f=1600 Hz ORR Receive Delay, Relative to ORA f=500 Hz-1000 Hz 1= 1000 Hz-1600 Hz f= 1600 Hz-2600 Hz 1=2600 Hz-2BOO Hz 1=2BOO Hz-3000 Hz DXA -40 -30 200 ,...S -25 -20 70 100 145 90 125 175 ,...S ,...S ,...S ,...S ,..S 12 15 dBrnCO -74 -67 (Note 1) dBmOp B 11 dBrnCO -B2 -79 ~BmOp -53 dBmO NOISE Nxc Transmit Noise, C Message Weighted TP3052, TP3053, TP3054 VFxl + = OV Nxp Transmit Noise, P Message Weighted TP3057 VFxl + = OV NRC Receive Noise, C Message Weighted TP3052, TP3053, TP3054 PCM Code Equals Alternating Positive and Negative Zero NRP Receive Noise, P Message Weighted TP3057 PCM Code Equals Positive Zero NRS Noise, Single Frequency f= 0 kHz to 100 kHz, Loop Around Measurament, VFxl + = 0 Vrms PPSRx Positive Power Supply Rejection, Transmit VFxl + = 0 Vrms, Vcc=5.0Voc+100 mVrms 1=0 kHz-50 kHz 40 dBC NPSRx Negative Power Supply Rejection, Transmit' VFxl + = 0 V~ms, Vaa= -5.0 Voc+ 100 mVrms :f=O kHz-50 kHz 40 dBC PPSRR Positive Power Supply Rejection, Receive PCM Code Equals Positive Zero Vc6=5.0Voc+100 mVrms 1=0 HZ-4000 Hz f=4 kHz-25 kHz f=25 kHz-50 kHz 40 40 36 dBC dB dB PCM Code Equals Positive Zero Vaa= -5.0 Voc+ 100 mVrms 1=0 HZ-4000 Hz f=4 kHz-25 kHz 1=25 kHz-50 kHz 40 40 36 dBC dB dB NPSRR Negative Power Supply Rejection, Receive S9-37 Transmission Characteristics (Continued) (All Devices) Unless otherwise specified: TA = O"C to 70·C, Vcc=5V±5%, Vee = -5V±5%, GNDA=OV, f=1.02 kHz, VIN=O dBmO, transmit input amplifier connected for unity-gain non-inverting. Symbol SOS Parameter Conditions Spurious Out-of-Band Signals at the Channel Output Loop Around Measurement, 0 dBmO, 300 Hz-3400 Hz Input Applied to VFxl + , Measure Individual Image Signals at VFRO 4600 Hz-7600 Hz 7600 Hz-8400 Hz 8400 Hz-100,OOO Hz Min Typ Max Units -30 dB -30 -40 -30 dB dB dB DISTORTION STDx STDR Signal to'Total Distortion Transmit or Receive Half-Channel Sinusoidal Test Method Level = 3.0 dBmO =0 dBmO to -30dBmO =-40dBmO XMT RCV =-55dBmO XMT RCV SFDx Single Frequency Distortion, Transmit -46 dB SFDR Single Frequency Distortion, Receive -46 dB IMD Intermodulation Distortion -41 dB 33 36 29 30 14 15 dBC dBC dBC dBC dBC dBC' Loop Around Measu~ement, VFx+ = -4 dBmO to -21 dBmO, Two Frequencies in the Range 300 Hz-3400 Hz CROSSTALK CTX.R Transmit to Receive'Crosstalk, dBmO Transmit Level 1=300 HZ-3400 Hz DR = Steady PCM Code -90 -75 dB Receive to Transmit Crosstalk, dBmO Receive Level f=300 Hz-3400 Hz, VFxl=OV -90 -70 (Note 2) dB o CTR·X o Nole 1: Theoretical worst-case for a perfectly zeroed encoder with alternating sign bit, due to the decoding law. Note 2: CTR.X Is measured with a - 40 dBmO activating signal applied at VFxl + . ENCODING FORMAT AT Ox OUTPUT TP3057 A-Law (Includes Even Bit Inversion) TP3052,TP3053,TP3054 p.-Law VIN (at GSx) = + Full-Scale VIN (at GSx) = OV VIN (at GSx) = - Full-Scale 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 {~ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 S9-38 Applications Information POWER SUPPLIES While the pins of the TP3050 family are well protected against electrical misuse, it is recommended that the standard CMOS practice be followed, ensuring that ground is connected to the device before any other connections are made. In applications where the printed circuit board may be plugged into a "hot" soeket with power and clocks already present, an extra long ground pin in the connector should be used. This common ground point should be decoupled to Vee and Vee with 10 p.F capaCitors. RECEIVE GAIN ADJUSTMENT For applications where a TP3050 family CODEC/filter receive output must drive a soon load, but a peak SWing lower than ± 2.5V is required, the receive gain can be easily adjusted by inserting a matched T-pad or 'IT-pad at the output. Table II lists the required resistor values for soon terminations. As these are generally non-standard values, the equations can be used to compute the attenuation of the closest practical set of resistors. It may be necessary to use unequal values for the R 1 or R4 arms of the attenuators to achieve a precise attenuation. Generally it is tolerable to allow a small deviation of the input impedance from nominal while still maintaining a good return loss. For example a 30 dB return loss against soon is obtained if the output impedance of the attenuator is in the range 282n to 319n (assuming a perfect transformer). All ground connections to each device should meet at a common point as close as possible to the GNDA pin. This minimizes the interaction of ground return currents flowing through a common bus impedance. 0.1 p.F supply decoupiing capacitors should be connected from this common ground point to Vee and Vee. For best performance, the ground pOint of each CODECI FILTER on a card should be connected to a common' card ground in star formation, rather than via a ground bus. T-Pad AHenuator Rl =Zl(~:~:) -2Jm2(N2~1) R2=2Jm2(N2~1) WhereoN = POWER IN POWER OUT and S=~ JZsc. Zoe Zsc ;= impedance with short circuit termination and Zoe = Impedance w~h open circuH termination Also: Z = Where 'IT-Pad AHenuator R4 R4 t ---+-_ --,'110 ~ II--Iu ------' TlIH/5510-5 R3=~(N2;;1) N2-1 ) R3=Zl ( N2-2NS+l Note: See Application Note 370 for further details, 59-39 Applications Information (Continued) TABLE II. AHentuator Tables for Z1 = Z2= 3000 (All Va,uesln 0) dB R1' 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 20 1.7 3.5 5.2 6.9 ,8.5 10.4 12.1 13.8 15.5 ,17.3 34.,4 51.3 68 R2 ' RS 84 100 115 379 143 156 168 180 190 200 210 218 233 246 R4 3.5 6.9 10.4 13.8 17.3 21.3 24.2 27.7 31.1 34.6 70 107 144 183 224 269 317 370 427 490 550 635 720 816 924 1.17k 1.Sk 26k 13k 8.7k 6.5k 5.2k 4.4k 3.7k 3.3k 2.9k 2.61 1.3k 850 650 494 402 380 284 244 211 184 161 142 125 110 98 77 61 52k 26k 17.4k 13k 10.5k 8.7k 7.5k 6.5k 5.8k 5.2k 2.6k 1.8k 1.3k 1.1k 900 785 698 630 527 535 500 473 450 430 413 386 366 Typical Synchronous Application -5V VFxI+ • VFxI- Via D.1,.F=!:: 5V ~D.1,.F=¥ TOSLIC GNDA GSx 1 Vee ' VFaO TP3D54/ TP3057 FSR' FSx - ~ -FROMTP31s5TS: ANALOG INTERFACE - + DIGITAL INTERFACE OR 5VOR GNDA PUN R2 ' ------- -----FROM TP3155 TSAC fROM SLiC R1 BCLI(a/CLKSEL BCIJ(x MCLKa/PUN MCLKx h BCLKx (2.048 MHz/1.544 MHz) TlIH/5510-8 Note 1: XMrr galn=20xlog (Rl:2R2) ,(R1+R2) >10KO. FIGURE 4 89-40 r: '\ ~ I -t ~National PRELIMINARY ~ Semiconductor TP3064/TP3067 Monolithic Serial Interface ~roc~ CMOS CODEC/FILTER Combos General Description Features • Complete CODEC and filtering system including: - Transmit high-pass and low-pass filtering - Receive low-pass filter with sin xix correction - Active RC noise filters - ",-law or A-law compatible COder and DECoder - Internal preciSion voltage reference - Serial 1/0 interface -Internal auto-zero circuitry - Receive push-pull power amplifiers • ",-law-TP3064 • A-Iaw-TP3067 • Meets or exceeds all D3/D4 and CCITT specifications • ± 5V operation • Low operating power-typically 70 mW • Power-down standby mode-typically 3 mW • Automatic powl!r-down • TTL or CMOS compatible digital interfaces • Maximizes line interface card circuit density Block Diagram VFXI+ VfIl+--1I-+< VIiIO TIMING AHO CONTROL TUH/5070-1 S9-41 i ..... The TP3064 (",-law) and TP3067 (A-law) are monolithic PCM CODEC/FILTERS utilizing the AID and D/A conversion architecture shown in Figure 1, and a serial PCM interface. The devices are fabricated using National's advanced double-poly CMOS process (microCMOS). Similar to the TP3050 family, these devices feature an additional Receive Power Amplifier to provide push-pull balanced output drive capability. The receive gain can be adjusted by means of two external resistors for an output level of up to ± 6.6V across a balanced 6000 load. Also included is an Analog Loopback switch and TSx output. FIGURE 1 ;1 I ~ r-~------------------------------------------------------------------------------ ! IlL Connection Diagram t: Dual-In-Line Package • CD 20l-VBB ~ GNDA- 2 I- 19 I--VFxl+ VPO-- 3 VPI- 4 17 -GSx TP3064 TP3067 Order Number TP3064J, TP3067J See NS Package J20A Vcc- 6 16 -ANLB 15-Wx 14 -FSx 13 r-Dx BClKtI/ClKSEl - 12 ~BClKx 9 MClKR/PDN -1.,;1;.;.0_ _ _.....:1.:.11I-MClKx TOP VIEW TLlH/5070-2 Pin Description . TP3064 TP3067 PlnNo. 1 2 3 4 5 6 VPO+ GNDA VPOVPI 7 VFRO Vee FSR 8 DR 9 BClKR/ClKSEl 10 Function Name The non-inverted output of the receive power amplifier. Analog ground. All signals are referenced to this pin. The inverted output of the receive power amplifier. Inverting input to the receive power amplifier. Also 'powers down both amplifiers when connected to Vaa. Analog output of the receive filter. Positive power supply pin. Vee = +5V±5%. Receive frame sync pulse which enables BClKR to shift PCM data into DR. FSR is an 8 kHz pulse train. See Figures 2 and 3 for timing details. Receive'data input. PCM data is shifted into DR following the FSR leading edge. The bit clock which shifts data into DR after the FSR leading edge. May vary from 64 kHz to 2.048 MHz. Altematively. may be a logic input which selects eit~er 1.536 MHz/1.544 MHz or 2.048 MHz for master clock in synchronous mode and BClKx is used for both transmit and receive directions (see Table I). Receive master clock. Must be 1.536 MHz. 1.544 MHz or 2.048 MHz. May be asynchronous with MClKx. but should be synchronous with MClKx for best performance. When MClKR is connected continuously low. MClKx is selected for all intemal timing. When MClKR is connected continuously high. 'the device is powered down. S9-42 Pin Description (Continued) TP3064 TP3067 PlnNo. 11 Name Function MCLKx 12 BCLKx 13 14 Ox FSx 15 16 TSx ANLB 17 GSx 18 19 20 VFxl VFxl + Vee Transmit master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be asynchronous with MCLKR' The bit clock which shifts out the PCM data on Ox. May vary from 64 kHz to 2.048 MHz, but must be synchronous with MCLKx. The TAI-STATE® PCM data output which is enabled by FSx. Transmit frame sync pulse input which enables BCLKx to shift out the PCM data on Ox. FSx is an 8 kHz pulse train, see Figures 2 and 3 for timing details. Open drain output which pulses low during the encoder time slot. Analog Loopback control input. Must be set to logic '0' for normal operation. When pulled to logic '1', the transmit filter input is disconnected from the output of the transmit preamplifier and connected to the VPO+ output of the receive power amplifier. Analog output of the transmit input amplifier. Used to externally set gain. Inverting input of the transmit input amplifier. Non-inverting input of the tran~mit input amplifier. Negative power supply pin. Vee = - 5V ± 5%. Functional Description POWER-UP With a fixed level on the BCLKR!CLKSEL pin, BLCKx will be selected as the bit clock for both the transmit and receive directions. Table I indicates the frequencies of operation which can be selected, depending on the state of BCLKR! CLKSEL. In this synchronous mode, the bit clock, BCLKx, may be from 64 kHz to 2.048 MHz, but must be synchronous with MCLKx. Each FSx pulse begins the encoding cycle and the PCM data from the previous encode cycle is shifted out of the enabled Ox output on the positive edge of BCLKx. After 8 bit clock periods, the TAl-STATE Ox output is returned to a high impedance state. With an FSR pulse, PCM data is latched via the DR input on the negative edge of BCLKx (or BCLKR if running). FSx and FSR must be synchronous with MCLKx/R· When power is first applied, power-on reset circuitry initializes the COMBO and places it into the power-down mode. All non-essential circuits are deactivated and the Ox, VFRO, VPO- and VPO+ outputs are put in high impedance states. To power-up the device, a logical low level or clock must be applied to the MCLKR/PON pin and FSx and/or FSR pulses must be present. Thus, 2 power-down control modes are available. The first is to pull the MCLKR/PON pin high; the alternative is to hold both FSx and FSR inputs continuously low-the device will power-down approximately 2 ms after the last FSx or FSR pulse. Power-up'will occur on the first FSx or FSR pulse. The TAl-STATE PCM data output, Ox, will remain in the high impedance state until the second FSx pulse. SYNCHRONOUS OPERATION TABLE I. Selection of Master Clock Frequencies For synchronous operation, the same master clock and bit clock should be used for both the transmit and receive directions. In this mode, a clock must be applied to MCLKx and the MCLKR/PON pin can be used as a power-down control. A low level on MCLKR/PON powers up the device and a high level powers down the device. In either case, MCLKx will be selected as the master clock for both the transmit and receive circuits. A bit clock must also be applied to BCLKx and the BCLKR/CLKSEL can be used to select the proper internal divider for a master clock of 1.536 MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame. BCLKR/CLKSEL Clocked 0 1 (or Open Circuit) S9-43 Master Clock Frequency Selected TP3067 TP3064 2.048 MHz 1.536 MHz or 1.544 MHz 2.048 MHz 1.536 MHz or 1.544 MHZ 2.048 MHz 1.544 MHz Functional Description (Continued) frame sync pulses, FSx and FSR, must be three or more bit clock periods long, with timing relationships specified in Ftgure 3. Based on the transmit frame sync, FSx, the COMBO will sense whether short or long frame sync pulses are being used. For 64 kHz operation, the frame sync pulse must be kept low for a minimum of 160 ns. The Dx TRI-STATE output buffer Is enabled with the rising edge of FSx or the rising edge of BCLKx, whichever comes later, and the first bit clocked out is the sign bit. The following seven BCLKx rising edges clock out the remaining seven bits. The Ox output is disabled by the falling BCLKx edge following the eighth rising edge, or by FSx going low, whichever comes later. A rising edge on the receive frame sync pulse. FSR. will cause the PCM data at DR to be latched In on the next eight falling edges of BCLKR(BCLKx In synchronous mode). Both devices may utilize the long frame sync pulse in synchronous or asynchronous mode. ASYNCHRONOUS OPERATION, For asynchronous operation, separate transmit and receive clocks may be applied. MCLKx and MCLKR must be 2.048 MHz for the TP3067, or 1.536 MHZ, 1.544 MHz for the TP3064, and need not be synchronous. For best transmission performance, however, MCLKR should be synchronous with MCLKx, which is easily achieved by applying only static logic levels to the MCLKR/PDN pin. This will automatically connect MCLKx to all internal MCLKR functions (see Pin Description). For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame. FSx starts each encoding cycle and must be synchronous with MCLKx and BCLKx. FSR starts each decoding cycle and must be synchronous with BCLKR. BCLKR must be a clock, the logic levels'shown in Table I are not valid in asynchronous mode. BCLKx and .BCLKR may operate from 64 kHz to 2.048 MHz. TRANSMIT SECTION The transmit seclion Input is an operational amplifier with provision for gain adjustment using two external resistors, see Figure 5. The low noise and wide bandwidth allow gains in excess of 20 dB across the audio passband to be realized. The op amp drives a unity-gain filter consisting of RC active pre-filter, followed by an eighth order switched-capacitor bandpass filter clocked at 256 kHz. The output of this filter 'directly drives the encoder sample-and-hold circuit. The AID is of companding type according to ",-law (TP3064) or A-law (TP3067) coding conventions. A precision voltage reference is trimmed in manufacturing to provide an input overload (tMAXl of nominally 2.5V peak (see table of Transmission Characteristics). The FSx frame sync pulse controls the sampling of the filter output, and then the successive-approximation encoding cycle begins. The 8-bit code is then loaded into a buffer and shifted out through Ox at the next FSx pulse. The total encoding delay will be approximately 165 (due to the transmit filter) plus 125 (due to encoding delay), which totals 290 "'S. Any offset voltage due to the filters or comparator is cancelled by sign bit Integration. SHORT FRAME SYNC OPERATION The COMBO can utilize either a short frame sync pulse (the same as the TP3020/21 CODECs) or a long frame sync pulse (the same as the TP5116A family of CODECs). Upon power initialization, the device assumes a short frame mode. In this mode, both frame sync pulses, FSx and FSR, must be one bit clock period lOng, with timing relationships speCified in Figure 2. With FSx high during a falling edge of BCLKx, the next rising edge of BCLKx enables the Ox TRISTATE output buffer, which will output the sign bit. The following seven rising edges clock out the remaining seven bits, and the next falling edge disables the Ox output. With FSR high during a falling edge of BCLKR (BCLKx in synchronous mode), the next falling edge of BCLKR latches in the sign bit. The following seven falling edges latch in the seven remaining bits. Both devices may utilize the short frame sync pulse in synchronous or asynchronous operating mode. ' "'S LONG FRAME SYNC OPERATION To use the long (TP5116A-type) frame mode, both the "'S ENCODING FORMAT AT DX OUTPUT TP3067 A-Law (Includes Even Bit Inversion) TP3064 ",-Law VIN VIN VIN = + Full-Scale = OV = - Full-Scale 1 0 {~ 1 0 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 1 1 0 0 S9-44 1 1 0 0 0 1 1 0 1 0 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 1 1 0 1 Functional Description (Continued) RECEIVE POWER AMPLIFIERS Two inverting mode power amplifiers are provided for directIy driving a matched line interface transformer. The gain of the first power amplifier can be adjusted to boost the ± 2.5V peak output signal from the receive filter up to ± 3.3V peak into an unbalanced 3000 load, or ±4.0V into an unbalanced 15 kO load. The second power amplifier is intemally . connected in unity-gain inverting mode to give 6 dB of signal gain for balanced loads. RECEIVE SECTION The receive section consists of an expanding DAC which drives a fifth order switched-capacitor low pass filter clocked at 256 kHz. The decoder is A-law (TP3067) or /L-Iaw (TP3064) and the 5th order low pass filter corrects for the sin x/x attenuation due to the S kHz sample/hold. The filter is then followed by a 2nd order RC active post-filter with its output at VFRO. The receive section is unity-gain, but gain can be added by using the power amplifiers. Upon the occurrence of FSR, the data at the DR input is clocked in on the falling edge of the next eight BClKR (BClKx) periods. At the end of the decoder time slot, the decoding cycle begins, and 10 /Ls later the decoder DAC output is updated. The total decoder delay is -10 /Ls (decoder update) plus 110 /Ls (filter delay) plus 62.5 /Ls (% frame), which gives apprOximately 180 /Ls. Maximum power transfer. to a 6000 subscriber line termination is obtained by differentially driving a balanced transformer with a y'2:1 turns ratio, as shown in Agure 2. A total peak power of 15.6 dBm can be delivered to the load plus termination. Both power amplifiers can be powered down independently from the PDN input by connecting the VPI input to Vee, saving approximately 12 mW of power. Absolute Maximum Ratings 7V -7V VcetoGNDA VsetoGNDA Voltage at any Analog Input or Output Voltage at any Digital Input or Output Vee+0.3VtoGNDA-0.3V· Operating Temperature Range - 25'C to + 125"C Storage Temperature Range - 65'C to + 150"C lead Temperature (Soldering, 10 seconds) 300'C Vee+0.3Vto Vee- 0•3V Electrical Characteristics Unless otherwise noted: Vec= 5.0V ±5%, Vee = -5V± 5%, GNDA=OV, TA =O"C to 70"C; typical characteristics specified at Vee = 5.0V, Vee = -5.0V, TA = 25'C; all signals are referenced to GNDA. Symbol I Parameter I Conditions I Min I Typ I Max I Units POWER DISSIPATION (ALL DEVICES) IceO Power-Down Current 0.5 1.5 mA leeO Power-Down Current 0.05 0.3 mA lee1 Active Current Power Amplifiers Active, VPI = OV. 7.0 10.0 mA lee1 Active CUrrent Power Amplifiers Active, VPI = OV 7.0 10.0 mA DIGITAL INTERFACE VIL Input low Voltage VIH Input High Voltage 0.6 VOL Output low Voltage Ox, IL = 3.2 mA SIGR, IL = 1.0 mA TSx, IL = 3.2 mA, Open Drain VOH Output High Voltage Ox, IH= -3.2 mA SIGR, IH= -1.0mA '2.4 2.4 IlL Input low Current GNDA:S:VIN:S:VIL, All Digitallnpuls -10 10 /LA IIH Input High Current VIH:S:VIN:S:Vce -10 10 ~ loz Output Current in High Impedance State (TRI-STATE) Ox, GNDA:S:Vo:S:Vee -10 10 ~ S9-45 V V 2.2 0:4 0.4 0.4 V V V V V Electrical Characteristics (Continue~) Unless otherwise noted: Vee =' 5.0V±5%; Vee = -5V:t5%, GNDA = OV, TA = O"Cto 70·C; typical chara~eristics specified at Vee = 5.0V, Vae = -5.0V; TA = 25°C; all signals are referenced to GNDA. Symbol I Parameter I . Conditions I Min I Typ I Max I Units ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES) I,XA Input Leakage Current - 2.5V s;V s: + 2.5V, VFxl + or VFxl- -200 R,XA Input Resistance -2.5VS:VS:+2.5V, VFxl'+ orVFxl- 10 RoXA Output Resistance Closed Loop, Unity Gain 200 nA MO 1 3 10 0 RLXA Load Resistance GSX CLXA Load CapaCitance GSx kO VoXA Output Dynamic Range GSx,RL~10kO ±2.8 V AvXA Voltage Gain VFxl+ toGSx 5000 VIV 50 1 2 pF FuXA Unity-Gain BahdWidth VosXA Offset Voltage -20 20 MHz VCMXA Common-Mode Voltage -2.5 2.5 CMRRXA Common-Mode Rejection Ratio 60 dB PSRRXA Power Supply Rejection Ratio 60 dB mV V ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES) 1 RoRF Output Resistance PinVFRO RLRF Load Resistance VFRO=±2.5V CLRF Load Capacitance VFRO to GNDA' VOSRO Output DC Offset Voltage , VFROto GNDA ,3 10 0 kO 25 pF -200 200 mV 100 ANALOG INTERFACE WITH POWER AMPLIFIERS (ALL DEVICES) IPI Input Leakage Current -1.0VS:VPIS:l.0V -100 RIPI Input Resistance -1.0VS:VPIS:l.0V 10 VIOS Input Offset Voltage ROP Output Resistance Inverting Unity-Gain at VPO+ orVPo- Fc Unity-Gain Bandwidth Open Loop (VPO-) CLP Load CapaCitance -25 RL~15000l RL=6000 RL =3000 GAp+ PSRRp . Gain, VPO- to VPO+ Power Supply Rejection of VeeorVeB 25 mV 1 0 400 kHz VPO+ or VPO- to GNDA 100 500 1000 -1 RL =3000 VPO+ to GI':IDA Level at VPO- = 1.77 Vrms (+3dBmO) nA MO pF pF pF VIV VPO- Connected to VPI okHz-4kHz okHz-50 kHz S9-46 60 36 dB dB Timing Specifications Symbol Conditions Parameter Min Typ Max Depends on the Device Used and the BClKR/ClKSEl Pin MClKx and MClKR tWMH Width of Master Clock High MClKx and MClKR 160 IWMl Width of Master Clock low MClKx and MClKR 160 tRM Rise Time of Master Clock MClKx and MClKR 50 ns tFM Fall Time of Master Clock MClKx and MClKR 50 ns tsBFM Set-Up Time from BClKx High (and FSx in long Frame Sync Mode) to MCLKx Falling Edge First Bit Clock after the leading Edge of FSx 1/tpM 1.536 1.544 2.048 Units Frequency of Master Clock MHz MHz MHz ns ns ns tpB Period of Bit Clock 485 !wBH Width of Bit Clock High VIH=2.2V 160 !wBL Width of Bit Clock low VIL =0.6V 160 tRB Rise Time of Bit Clock tpB=488 ns 50 ns tFB Fall Time of Bit Clock tpB=488 ns 50 ns tHBF Holding Time from Bit Clock low to Frame Sync long Frame Only 0 ns' tHOLO Holding Time from Bit Clock High to Frame Sync Short Frame Only 0 ns tsFB Set-Up Time for Frame Sync to Bit Clock low long Frame Only 80 ns tOBO Delay Time from BClKx High to Data Valid load = 150 pF plus 2 LSTIl loads 0 txop Delay Time to TSx low load = 150 pF plus 2 lSTIl loads toze Delay Time from BClKx low to Data Output Disabled tOZF Delay Time to Valid Data from FSx or BClKx, Whichever Comes Later tsOB Set-Up Time from DR Valid to BClKR/xlow 50 ns tHBo Hold Time from BClKR/X low to DR Invalid 50 ns tOFSSG Delay Time from BClKR/X low toSIGRValid load = 50 pF plus 2 lSTIl loads tSF Set-Up Time from FSX/R to BClKX/Rlow Short Frame Sync Pulse (lor 2 Bit Clock Periods long) (Note 1)' 50 ns tHF Hold Time from BClKX/R Low to FSXlR low Short Frame Sync Pulse (lor 2 Bit Clock Periods long) (Note 1) 100 ns tHBFI Hold Time from 3rd Period of Bit Clock low to Frame Sync (FSxorFSR) long Frame Sync Pulse (from 3 to 8 Bit Clock Periods long) 100 ns !wFL Minimum Width of the Frame Sync Pulse (low level) 64k Bills Operating Mode 160 ns CL =0 pFto 150 pF Note 1: For short frame sync timing. FSx and FSR must go high while their respective bit clocks are high. S9-47 488 15,725 ns ns ns 180 ns 140 ns 50 165 ns 20 165 ns 300 . ns TP30641TP3067 :! 3 5" CD c i" CD ii1 i TSx MeLKa MeLKa BLCKx FIx 0' CD ~ FIGURE 2. Short Frame Sync Timing ~ :I: ~ lo -t 3" S" ca c ~" Al 3o Q :> MCLKx a. MCLK. ! BClKx FS, en co .r.. co I Ox BCLKo FSR --------------~-~ \ \ IS081 ti:-IH80::lJ DR \;=!t: X1X2X3l4j5X6X70==== FIGURE 3. Long Frame Sync Timing J.90Edllt90Edl Transmission Characteristics '(All Devices) Unless otherwise specified: TA = O·C to 70·C, Vee = 5V ± 5%, Vee = -5V±5%, GNDA = OV, f = 1.02 kHz, VIN = 0 dBmO, transmit input amplifier connected for unity-gain non-inverting. Symbol I Parameter AMPLITUDE RESPONSE Absolute Levels tMAX I Conditions I Min I Typ I I Units Max Nominal 0 dBmO Level is 4 dBm (600ll) OdBmO TP3064 TP3067 1.2276 1.2276 Vrms Vrms Max Transmit Overload Level TP3064 (3.17 dBmO) TP3067 (3.14 dBmO) 2.501 2.492 VPK VPK GXA Transmit Gain, Absolute TA=25·C, Vee=5V, Vae= -5V Input at GSx = 0 dBmO at 1020 Hz GXR Transmit Gain, Relative to GXA f=16Hz f=50Hz f=60Hz f=200 Hz f = 300 Hz-3000 Hz f=3300Hz f=3400Hz f=4000Hz f=4600 Hz and Up, Measure Response from 0 Hz to 4000 Hz -0.15 -1.8 -0.15 -0.35 -0.7 , 0.15 dB -40 -30 -26 -0.1 0.15 0.05. 0 -14 -32 dB dB dB dB dB dB dB dB dB dB GXAT Absolute Transmit Gain Variation with Temperature TA = O·C to 70·C ±0.1 GXAV Absolute Transmit Gain Variation with Supply Voltage Vee=5V±5%, Vaa= -5V±5% ±0.05 Transmit Gain Variations with Level Sinusoidal Test Method Reference Level = -10 dBmO VFxl+ = -;-40 dBmO to +3 dBmO VFxl + = - 50 dBmO to - 40 dBmO VFxl + = - 55 dBmO to - 50 dBmO GXRL dB I -1.2 ·0.2 0.4 1.2 GRA Receive Gain, Absolute TA=25·C, Vee=5V, Vaa= -5V Input= Digital Code Sequence for· odBmO Signal at 1020 Hz -0.15 0.15 dB GRR Receive Gain, Relative to GRA f=O Hz to 3000 Hz f=3300Hz f=3400Hz f=4000Hz -0.15 -0.35 -0.7 0.15 0.05 0 -14 dB dB dB dB GRAT Absolute Receive Gain Variation with Temperature TA=O·C to 70"C ±01. dB GRAV Absolute Receive Gain Variation with Supply Voltage Vcc=5V±5%, Vaa= -5V±5% ±0.05 dB GRRL Receive Gain Variations with Level Sinusoidal Test Method; Reference Input PCM Code Corresponds to an Ideally Encoded - 10 dBmO Signal PCM Level = -40 dBmO to + 3 dBmO PCM Level = -50 dBmO to -40 dBmO PCM Level= -55 dBmO to -50 dBmO -0.2 -0.4 -1.2 0.2 0.4 1.2 dB dB dB RL=10kll -2.5 2.5 V VRO Receive Filter Output at VFRO S9-50 -0.2 ~0.4 dB dB dB Transmission Characteristics (Continued) (All Devices) Unless otherwise specified: TA = O·C to 70·C, VCC = 5V±5%, Vss = -5V±5%, GNDA = OV,I = 1.02 kHz, Y,N = 0 dBmO, transmit inputamplifier connected for unity-gain non-inverting. Symbol I I Parameter Conditions ENVELOPE DELAY DISTORTION WITH FREQUENCY DXA Transmit Delay, Absolute f=1600 Hz DXR Transmit Delay, Relative to DXA f=500 Hz-600 Hz f=600 Hz-SOO Hz f=800 Hz-1000 Hz f=1000 Hz-1600 Hz f=1600 Hz-2600 Hz 1=2600 Hz-2800 Hz f= 2800 Hz- 3000 Hz DRA Receive Delay, Absolute f=1600Hz Receive Delay, Relative to DRA f=500 Hz-1000 Hz 1=1000 Hz-1600 Hz f= 1600 Hz-2600 Hz f = 2600 Hz-2S00 Hz f=2S00 Hz-3000 Hz DRR I Min I Typ I -40 -30 Max I Units 290 315 p's 195 120 50 20 55 ·80 130 220 145 75 40 75 105 155 p.s p.s p's p.s p's p's p.s 1S0 200 p.s -25 -20 70 100 145 90 125 175 p.s p.s p's p.s p.s NOISE Nxc Transmit Noise, C Message Weighted TP3064 VFxl + = OV 12 15 dBrnCO Nxp Transmit Noise, P Message . Weighted TP3067 VFxl + = OV -74 -69 (Note 1) dBmOp NRC Receive Noise, C Message Weighted TP3064 PCM Code Equals Alternating Positive and Negative Zero .8 11 dBrnCO NRP Receive Noise, P Message Weighted TP3067 PCM Code Equals Positive Zero -S2 -79 dBmOp NRS Noise, Single Frequency f = 0 kHz to 100 kHz, Loop Around Measurement, VFxl + = 0 Vrms -53 dBmO PPSRx Positive Power Supply Rejection, Transmit NPSRx Negative Power Supply Rejection, Transmit PPSRR Positive Power Supply Rejection; Receive , NPSRR SOS Negative Power Supply Rejection, Receive Spurious Out-of-Band Signals at the Channel Output VFxl+ =0 Vrms, . Vcc=5.0Voc+100mVrms f=O kHz-50 kHz 40 dBC VFxl + = 0 Vrms, Vss= -5.0 Voc+ 100 mVrms f=O kHz-"50 kHz 40 dBC PCM Code Equals Positive Zero Vcc=5.0Voc+100mVrms f=O Hz-4000 Hz f=4kHz-25 kHz f=25 kHz-50 kHz 40 40 36 dBC dB dB PCM Code Equals Positive Zero Vss= -5.0 VOC+ 100 mVrms f=O Hz-4000 Hz f=4kHz-25 kHz f= 25 kHz-50 kHz 40 40 36 dBC dB dB Loop Around Measurement, 0 dBmO, 300 Hz -3400 Hz Input Applied to VFxl +, Measure Individual Image Signals at VFRO 4600 Hz-7600 Hz 7600 Hz-S400 Hz 8400 Hz-100,OOO Hz S9-51 -32 . -40 -32 dB dB dB Transmission Characteristics (Continued) (All Devices) Unless otherwise specified: TA = O"Cto 70"C, Vee = 5V±5%, Vee - 5V±5%, GNDA = OV, f = 1.02 kHz, VIN = 0 dBmO, transmit input amplifier connected for unity.gain non-inverting. Symbol I Parameter DISTORTION I Conditions I Min I Typ I Max I Units STOx Signal to Total Distortion Sinusoidal Test Method STDR Transmit or Receive Half-Channel Level = 3.0 dBmO =OdBmOto -30dBmO =-40dBmO XMT RCV =-55dBmO XMT RCV SFDx Single Frequency Distortion, Transmit -46 dB SFDR Single Frequency Distortion, Receive -46 dB IMD Intermodulation Distortion -41 dB 33 36 29 30 14 15 dBC dBC dBC dBC dBC dBC Loop Around Measurement, VFxl + = -4 dBmO to - 21 dBmO, Two Frequencies in the Range 300 Hz-3400 Hz CROSSTALK CTX-R Transmit to Receive Crosstalk f=300 Hz-3000 Hz DR = Steady PCM Code -90 -75 dB CTR-X Receive to Transmit Crosstalk f = 300 Hz- 3000 Hz, VFxl = OV -90 -70 (Note 2) dB POWER AMPLIFIERS VOL Maximum 0 dBmO Level for Better than ± 0.1 dB Unearity Over the Range -10 dBmO to +3dBmO Balanced Load, RL Connected Between VPO+ and VPORL =6000 RL =12000 RL=30kO SIDp SignallDistortion RL =6000,0 dBmO Measured by extrapolation from the distortion lest result Note 2: CTR.X Is measured with a - 40 dBmO activating signal applied al VFxl +. 3.3 3.5 4.0 Vrms Vrms Vrms 50 dB Note 1: , 59-52 Applications Information POWER SUPPLIES While the pins of the TP3060 family are well protected against electrical misuse, it is recommended that the standard CMOS practice be followed, ensuring that ground is connected to the device before any other connections are made. In applications where the printed circuit board may be plugged into a "hot" socket with power and clocks already present, an extra long ground pin in the connector should be used. All ground connections to each device should meet at a common pOint as close as possible to· the GNOA pin. This minimizes the interaction of ground retum currents flowing through a common bus impedance. 0.1 IlF supply decoupiing capacitors should be connected from this common ground point. to Vee and Vee. For best performance, the ground point of each COOECI FILTER on a card should be connected to a common card ground in start formation, rather than via a ground bus. This common ground point should be decoupled to Vee and Vee with 10 IlF capacitors. Note: See Application Nole 370 for further details Typical Asynchronous Application 3110 3110 R2 11 TUH/5070-5 A1 + A2) ,(A1 Note 1: Transm~ gain = 20 x log ( ~ .. . Note 2: AecelVe gllln + A2) .. 10 kG x A3) ,R4" 10 kG = 20 X log (2""""R4"" FIGURE 2 S9-53 Section 10 Building Blocks Building Blocks Section Contents Other Building Blocks lF13006.lFl3007 Digital G~n Set ....................... , .............. : ................................... S 10-1 LM1851 Ground Fault Interrupter ............................................................................S 10-8 r- "II ..... PRELIMINARY Co) . ~ Semiconductor ~National ~r- "II ..... g..... LF13006, LF13007 Digital Gain Set General Description The LF13006, LF13007 are precision digital gain sets used for accurately setting non-inverting op amp gains. Gains are set with a 3-bit digital word which can be. latched in with WR and CS pins. All digital inputs are TTL and CMOS compatible. The LF13006 shown below will set binary scaled gains of 1, 2, 4, 8, 16, 32, 64, and 128. The LF13007 will set gains of 1, 2,5,10,20,50, and 100 (a common attenuator sequence). In addition, both versions have several taps and two uncommitted matching resistors which allow customization of the gain. The gains are set with precision thin film resistors. The low temperature coefficient of the thin film resistors and their excellent tracking result in gain ratios which are virtually independent of temperature. The LF13006, LF13007 used in conjunction with an amplifier not only satisfies the need for a digitally programmable amplifier in microprocessor based systems, but is also useful for discrete applications, eliminating the need to find 0.5% reSistors in the ratio of 100 to 1 which track each other over temperature. Features • • • • • • Block Diagram and Typical Application 15V -15V ov lie Rl TTL and CMOS compatible logic levels Microprocessor compatible Gain error 0.5% max Binary or scope knob gains Wide supply range + 5V to ± 18V Packaged in 16-pin DIP (LF13006) R2 - -- --, rl- -1- -1- -1- -1- -1I v+ LFI3DD6 ~ v- r--------------,~UT 4R DIG IN 1 DIG IN DIG IN 2 3 2R • -1- - -IWi! e! DATIIBUS CDNTROL You, UHfS TLlH/5114-1 Note: R'" 15 kO S 10-1 . Absolute Maximum Ratings Supply Voltage, V + to V Supply Voltage, V + to GND Voltage at Any Digital Input 36V 25V V+ toGND V+ toV- + 2V Analog Voltage Operating Temperature Range - 40·C to + 85·C Electrical Characteristics (Note 1) Conditions Typ Tested Limit (Note 2) Design Limit (Note 3) Units (Limit) Gain Error AOUT= ±10V ANAGND=OV IINPUT<10 nA 0.3 0.5 0.5 %·(max) Gain Temperature Coefficient AoUT= ±10V ANAGND=OV 0.001 Parameter Digital Input Voltage Low High Digital Input Current Low High Positive Power Supply Current VIL=OV VIH=5V All Logic Inputs Low NJ3gative Power Supply CUrrent All Logic Inputs Low %rC 1.4 1.6 0.8 2.0 0.8 2.0 V(max) V(min) -35 0.0001 -100 1 -1·00 1 ",A(max) ",A(max) 3 -2 5 -5 5 -5 mA(max) - mA(max) Write Pulse Width, tw VIL =OV, VIH=5V 40 100 ns(min) CiilP Select Set·Up Time, tcs VIL =OV, VIH=5V 60 120 ns(min) Chip Select Hold Time, tcH VIL =OV, VIH=5V 0 0 mi(min) DIG IN Set·Up Time, tos VIL = OV, VIH = 5V 80 150 ns(min) DIG IN Hold Time, tOH VIL =OV, VIH=5V 0 0 Switching Time for Gain Change (Note 4) ns(min) ns(max) 200 Switch On Resistance :,3 Unit Resistance, R 15 12-18 kO Rl and R2 Mismatch 0.3 0.5 kO 0.5 %(max) Rl/R2 Temperature· Coefficient 0.001 %rC Nole 1: Parameters are speoified at V+ =tSV and V- = -ISV. Min V+ to ground Yoltage is SV. Min V+ to V- Yoltage Is SV. Boldface numbers apply al temperalure extremes. All other numbers apply at TA=T/=2S'C. Note 2: Guaranteed and 100% production tested. Note 3: Guarantaed (but not 100% production tested) over the operating temperature. These limns are not used to calculate outgoing quality levels. Note 4: Settling time for gain change Is the swnching time for gain change plus settling time (see section on Settling Time). Note 5: WR minimum high threshold Yoltage increases to 2.4V under the extreme conditions when all three digital inputs are simultaneously taken from OV to SV at a slew rate of greater than SOOVI "s. Connection Diagram GAIN TABLE Dual·ln·Line Package Gain Digital Input 000 001 010 011 100 101 110 111 LF13006 AOUT 1 2 4 8 16 32 64 128 BOUT 1 1.25 2.5 5 10 20 40 80 LF13007 AOUT 1 1.25 2 5 10 20 50 100 OIGGNO-:- 1 BOUT 1 1 1.6 4 8 16 40 80 V 16 -ANAGND INPUT- 2 15-H2 y-- 3 14 -He y+- 4 13 -HI 12 - Aour m- 5 Bour- 6 ll-Ci iiii-7 10 - 0lGIN3 01GIN1- 8 9~DIGIN2 . TOP VIEW TLlH/5114-2 Order Numbers·LF13006, LF13007 See NS Packages D16C, N16A S 10-2 Switching Waveforms les VIM fS ViH Wi 50% VIL ViH DATA BITS VIL ~ 50% Block Diagram and Typical Application 15Y -15Y OY ~ los -sii% (Continued) (LF13007) . He Rl , r----------------r- R2 - -- rl- -1- -1- -1- -1- -1Y· Lf13087 ~ V- I TL/H/5114-3 DJ ,.-------BOUT 3R 38 2ft I I DECODE I -1- - -l- L DIG IN 3 WI ei DADi BUS CONTROL UNES TUH/5114-4 Note: A '" 15 kn 810-3 ~ r---------~-------------------------------------------------------------------------- o o (II) or- Typical Performance Characteristics ~ Negative Power Supply g- O 5.0 H~-+-+-t-+-++-I (II) or- ~ Digital Input Threshold va Temperature o Current vs Temperature -1.0 ~ 4.0 ~-2.0 Ii! i-3.0 3.0 PoCt--t-1-t-f""'k:-I-+-I ... 1""" )~ ~ B 2.0 8-4.0 1.0 -5.0 o Vs-±5V t:I:tt:±:±±±:±3 -15 25 &5 105 -55 15a: .. a: :::> ~ ~ 50 i 1.6 40 Ii! 1.2 -25'C I 20 10 -55 -55'C ~ i: I .-. ~ 0.8 - l rC 30 o -55 ,.",.. ..... .",.. io-'" .",.. i-'" o .... Vs= ±5V..... 100 o ! 400 ~ 300 200 ~ <0100 o Va= ±5V ~ .... .",.. io-" .",.. ~~rar ~ 400 -- ~ .",.. 200 co .Vs=: ±1.5V, I If.! 100 Va= ±2OV o .... ~ Vs=±5V ~ i"'"' ~OV Vsj±l 5V """ Vs=±2OV -55' -15 25 &5 105 TEMPERATURE ('C) -55 .-15 25 65 105 TEMPERATURE ('C) TL/Hf5114-5 510-4 ~ vs=±~,. -15 25 &5 TEMPElWURE ('CI » ui300 ui ~ .... 600 i' Iii -55 i-'" io-" Chip Select Set-Up Time, tea Data Set-Up Time, tos 600 i --:tr o -r 20 5 10 15 SUPPLY VOI1AGE (VI -15 25 15 105 TEMPERAWRE ('C) 400 io-"'- 0.4 -15 25 65 105 TEMPERATURE ('CI - iioo Write Width, tw 2.4 ::. !! Vs=±15V f- ~ _ 1.5 m i5 0.5 _ 2.0 60 I. Digital Input Threshold vs Supply Voltage ro~~-r-r'-~~~ 2.5 -15 25 65 105 TEMPERATURE ('C) TEMPERATURE ('C) ~ ~ ~ -55 Logical 0 Input Bias Current vs Temperature E 'V;=±10V.",.. io-" -¥s=±15V 105 r:;; ..... W Application Information use of a lead capacitor from the inverting input to the output of the amplifier. A lead capacitor is effective whenever the feedback around an amplifier is resistive, whether with discrete resistors or with the LF13006/7. This phenomenon is the result of the feedback pole created by the parallel resistance and capacitance from the inverting input of the op amp to AC ground. SeHlIng Time Test Circuit FLOW-THROUGH OPERATION THE LF13006, LF13007 can be operated with control lines CS and WR grounded. In this mode new data on the digital inputs will immediately set the new gain value. Input data cannot be latched in this mode. INPUT CURRENT Current flowing through the input (pin 2) due to bias current of the op amp will result in a gain error due to switch impedance. Normally this error is very small. For example, 10 nA of bias current flowing through 3 kO of switch resistance will result in an error of 30 ",Vat the summing node. However, applications which have significant current flowing through the input must take this effect into account. SETTLING TIME Settling time is a function of the particular op amp used with the LF1300S/7 and the gain which is taken. It can be optimized and stability problems can be prevented through the 10/GAIN:r o . IN OUT TLlH/5114-6 Typl.cal SeHlIng Time Curves :s... S i ~ :z: 100 . ~ . ~ = : lk i)J ~ 100 ~ i!E 100 i Ii ~ ~ ~ l:! co ::... ::... . . co ::... 10 :E :Ii ;::: z Iii... 0 4 6 8 10 12 lEAD CAPACITOR (pF) ...~ 14 . ..Iii ;::: z 1 10 :E ;::: :::l lk Z :::l 1 0 4 8 10 12 lEAO CAPACITOR (pF) 14 4 6 8 10 12 lEAD CAPACITOR (pF) 14 TL/H/5114-7 • Unstable at CL less than 2 pF Typical Applications Variable Capacitance Multiplier Ceffective = Cl (gain set #) Note: Output swing at input op amp Is multiplied by set gain. Signal range may be limited. IN 12 AOUT 15 LF13OO& LF13007 DIGITAL CONTROL 14 2 INPUT -=13 Cl ANA DIGITAL CONTROL GNO 16 '::" TL/H/5114-S S 10-5 Q Q .!» r- ." ..... W Q Q ..... r- ,--------------------------------------------------------------------------------- g ('f) Typical Applications 5 (Continued) SWltchable Gain of ± 1 Programmable Current Source l DIBITAL IN 15V ,.. 30k ~ 15 12 AOUT LF13D06 R VIN-....~I-.....M,..... .+.~ LF13006 LF13007 DIGITAL CONTROL VOUT LM385·1.2V INPUT TLlH15114-11 Note: Digitai code=OOO, VOUT=VIN; Digitai code = 001, VOUT= -VIN Programmable DlfferenUal Amp TLIH15114-10 DIGITAL IN 1 = 1.2V [ _ 1_ ] OUT 120fl gain set # Inverting Gains -IN LF13D116 LF13OD7 ANA 16 GND AOUT 12 DIGITAL CONTROL INPUT 2 +IN LF130D6 16 ANA GND LF13OD7 14 LFl30D6 LF13DB7 15 DIGITAL IN YoUT >---+-VoUT TLIHIS114-12 Inverting gain with high input im· AOUT pedance can be obtained with the 12 LF13006, LF13007 by using the two TLIH15114-13 on·board resistors and a dual op amp as shown. Note 1: Actual gain = set gain-1 since LF13006s are in "inverting mode". Nole 2: Set gain must be same on both LFl3006s. S 10·6 Typical Applications Altered Gain Range IN (Continued) One Octave per Bit Function Generator Variable Gains of Almost 1 OUT 1216 ADUrl BaUT ANA GNO 15 15 12 AaUT UI300S '::" lF13006 2 INPUT 2 INPUT lFI3006 INPUT 2 13 DIGITAL CONTROL 13 DIGITAL CONTROL ANA GNO ADUT 16 12 ANA TL/H/5114-14 TL/H/5114-16 GNO 16 10k 10k TRIANGLE WAVE OUTPUT TLlH/51 14-15 GAINS 9 1.8 1.29 1.125 1.059 1.029 1.014 1.007 GAINS AoUT BOUT 1 1.8 3 4.5 6 7.2 8 8.47 1 1.2 2 3 4 4.8 5.33 5.65 Programmable Instrumentation Amp Attenuator (0 dB to - 42 dB In 6 dB steps) INPUT 12 Aaur . 10k LF130DB ANA 16 UNO LFI3006 LF13007 AaUT 12 10k OUTPUT 10k ANA GNO 16 TL/H/5114-17 Nole I: VOUT=N (A-B), N=sel gain. TL/H/5114-18 Note 2: Ali 10k resistors 0.1 % matched. S 10-7 • .- ,--------------------------------------------------------------------------------, .- ~National II) CD ~ ~ Semiconductor LM1851 Grou,nd Fault Interrupter General Description Features The lM1851 is designed to provide ground fault protection for AC power ,outlets in consumer and industrial environments. Ground fault currents greater than a presettable threshold value will trigger an external SCR-driven circuit breaker to interrupt the AC line and remove the fault condition. In addition to detection of conventional hot wire to ground faults, the neutral fault condition is also detected. • • • • • Full advantage of the U.S. Ul943 timing specification is taken to insure maximum immunity to false triggering due to line noise. Special features include circuitry that rapidly resets the timing capacitor in the event that noise pulses introduce unwanted charging currents and a memory circuit that allows firing of even a sluggish breaker on either half-cycle of the line voltage when external full-wave rectification is used. Internal power supply shunt regulator Externally programmable fault current threshold Externally programmable fault current integration time Direct interface to SCR ' Operates under line reversal; both load vs line and hot vs neutral • Detects neutral line faults Block and Connection Diagram VCC SCR TRIGGER TIMING CAPACITOR INVERTING INPUT SENSITIVITY SET RESISTOR NON·INVERTING INPUT TOP VIEW Order Number lM1851 See NS Package N08E S 10-8 SENSE AMPLIFIER OUTPUT GNO TL/H/5177-1 Absolute Maximum Ratings Supply Current Power Dissipation (Note 1) Operating Temperature Range 19mA 570mW -40'Cto +70'C DC Electrical Characteristics Parameter Power Supply Shunt Regulator Voltage Storage Temperature Range Lead Temp. (Soldering, 10 seconds) - 55'C to + 150'C 300'C TA= 25'C, ISS = 5 mA Min Typ Max Pin 8, Average Value Conditions 22 26 30 Units 'V V Latch Trigger Voltage Pin 7 15 17.5 20 Sensitivity Set Voltage Pin8toPin6 6 7 8.2 V Output Drive Current Pin 1, With Fault 0.5 1 2.4 mA Output Saturation Voltage Pin 1, Without Fault 100 240 mV Output Saturation Resistance Pin 1, Without Fault 100 0 Output External Current Sinking Capability Pin 1, Without Fault, Vpin 1 Held to 0.3V (Note 4) 2.0 5 mA Noise Integra~ion Sink Current Ratio Pin 7, Ratio of Discharge Currents Between No Fault and Fault Conditions 2.0 2.8 3.6 /LA//LA AC Electrical Characteristics TA=25'C,lss=5mA Parameter Conditions Min Typ Max Units 3 5 7 mA Normal Fault Current Sensitivity Figure 1 (Note 3) Normal Fault Trip Time 5000 Fault, Figure 2 (Note 2) 18 ms Normal Fault with Grounded Neutral Fault Trip Time 5000 Normal Fault, 20 Neutral, Figure 2 (Note 2) 18 ms Note 1: For operation in ambient temperatures above 25°C, the device must be derated based on a 125°C maximum junction temperature and a thermal resistance of 17S'C/W junction to ambient Average of 10 trials. Note 3: Required UL sensitivity tolerance is such that external trimming of LM1851 sensitivity will be necessary. Note 4: This externally applied current Is in addition to the internal "output drive current" source. Note 2: 7 TIMING CAP -IN 2 1 SCR <1 _~, ISS -r- O.002 .;; :=-30Dmv "Ii ..! 8 I "N TRIGGER 'LMII5t OPAMP RsET OUTPUT tOOk j047pf I ..!.. ~ 800 Hz "" GND 4 Vee t.iM -:31V I TL/H/5177-2 FIGURE 1, Normal Fault Sensitivity Test Circuit S 10-9 _r----------------------------------------------------------------------- -=s 1ft CD Internal Schematic Diagram TLlH/5177-3 S 10·10 r- s::: ..... Typical Performance Characteristics C» UI Average Trip Time vs Fault Current _=== ·1000 100 ..;:: TV ~ RSET ='f(rm,)' x (UI) " oS SENSE TRANSFORMER 100011 ~ 100 ~ .,!:; FI ~ K: ! ;;: ...oS ..... Normal Fault Current Threshold vs RSET z co .;::... 10 ffi 10 a: ~ .,!:; ~ o I 0.01 0.1 1.0 10 lOOk TRIP TIME (SECONDS) 1M 10M RSET(n) • See Block Diagram ~ 1400 ;:: 1200 z ; ... 1000 Output Drive Current vs Output Voltage Pin 1 Saturation Voltage vs External Load Current, IL ,---r-,.-,--'-r--,.-,--, 10 I-+-t-t-+-t-t--l t-.....;:::\--t-+-t-t--l ~ w co ~ co ffi 800 a:: ~ > z co ;: a: ....'" 600 > ~ 400 0.1 :i l; ~ 200 z ;: o '-"':'_-='~..J....--"_'-...J o 5 10 15 20 25 3D 35 10 OUTPUT VOLTAGE@VPINI (V) 100 'L -EXTERNAL LOAD CURRENT (mA) TL/H/5177-4 Circuit Description (Refer to Block and Connection Diagram) The LM1851 operates from 26V as set by an internal shunt regulator, D3. In the absence of a fault (I, = 0) the feedback path status signal (Vs) is correspondingly zero. Under these conditions the capacitor discharge current, 11, sits quiescently at three times its threshold value, ITH' so that noise induced charge on the timing capacitor will be rapidly re. moved. When a fault current, I" is induced in the secondary of the external Sjilnse transformer, the operational amplifier, A 1, uses feedback to force a virtual ground at the input as it S 10-11 extracts I,. The presence of I, during either half-cycle will cause Vs to go high, which in turn changes 11 from 31TH to ITH. Although ITH discharges the timing capacitor during both half-cycles of the line, I, only charges the capacitor during the half-cycle in which I, exits pin 2. Thus during one half-cycle I,-ITH charges the timing capaCitor, while during the other half-cycle ITH discharges it. When the capaCitor voltage reaches 17.5V, the latch engages and turns off 03 permitting 12 to drive the gate of an SCR. ~ r---------------------------------------------------------------------~------------------- ~ ... ~ :2 Application Circuits A typical ground fault interrupter circuit is shown in F/{/ure 2. It is designed to operate on 120 VAC line voltage with 5 mA normal fault sensitivity. start-up (51 closure) with both a. heavy normal fault and a 20 grounded neutral fault present. This situation is shown diagramatically below. A full-wave rectifier bridge and a 15k/2W resistor are used to supply the' DC power required by the IC. A 1 p.F capacitor at pin 8 used to filter the ripple of the supply voltage and is also connected across the SCR to allow firing of the SCR on either half-cycle. When a fault causes the SCR to trigger, the circuit breaker is energized and line voltage is removed . from the load. At this time no fault current flows and the IC discharge current increases from ITH to 31TH (see Circuit Description and Block Diagram). This quickly resets both the timing capaCitor and the output latch. At this time the circuit breaker can be reset and the line voltage again supplied to the load, assuming the fault has been removed. A 1000: 1 sense transformer is used to detect the normal fault. The fault current, which is basically the difference current between the hot and neutral lines, is stepped down by 1000 and fed into the input pins of the operational amplifier through a 10 "F capacitor. The 0.0033 "F capacitor between pin 2 and pin 3 and the 200 pF between pins 3 and 4 are added to obtain better noise immunity. The normal fault sensitivity is determined by the timing capacitor discharging current, ITH. ITH can be calculated by: ( ITH = Iflrms) x 0 91 2 where If(rms) is the rms input fault current to the operational amp and the factor of 2 is due to the fact that If charges the timing capaCitor only during one half-cycle, while ITH discharges the capaCitor continuously. The factor 0.91 converts the rms value to an average value. Combining equations (1) and (2) we have R SET SET 7V 5mAXO.91 0 TL/H/5177-5 -3 ms GFI turn-on time (15k and 1 p.F) -8 ms Potential loss of one half-cycle due to fault current sense of half-cycles only -4 ms Time required to open a sluggish circuit breaker s: 10 ms Maximum integration time tha~ could be allowed 8 ms Value of integration time that accommodates component tolerances and other variables Ct = I x T (5) V where T = integration time V = threshold voltage I = average fault current into Ct ( 120 V:~(rms) ) \. • x J x (1turn ) 1000 turns x \. T I current division of input sense transformer therefore: G) '--v-J Ct charging on halfcycles only N (RG: RJ \. heavy fault current generated (swamps ITH) (4) 1000 The correct value for RSET can also be determined from the characteristic curve that plots equation (3). Note that this is an approximate calculation; the exact value of RSET depends on the specifiC sense transformer used and LM1851 tolerances. Inasmuch as UL943 specifies a sensitivity "window" of 4 mA-6 mA, provision should be made to adjust RSET on a per-product b!lsis. Independent of setting sensitivity, the desired integration time can be obtained through proper selection of the timing capaCitor, Ct. Due to the large number of variables involved, proper selection of Ct is best done empirically. The following deSign example, then should only be used as a guideline. Assume the goal is to meet UL943 timing requirements. Also assume that worst case timing occurs during GF1 Ra 500 . UL943 specifies s: 25 ms average trip time under these conditions. Calculation of Ct based upon charging currents due to normal fault only is as follows: s: 25 ms Specification 1= M RN 0.4 (OlU (3) 1.5 (o.auf .1-6 .. .......:...~+=..J ....J I '----.,vv-I For example, to obtain 5 mA(rms) sensitivity for the circuit in Figure 2 we have: R INEUTRAL RG 7V If(rms) x 0.91 GFI NEUTRAL (2) . HOT LINE "- 7V ITH=--+2 (1) RSET At the decision pOint, the average fault current just equals the threshold current, ITH. ' e>.!!!!!. • x (0.91) Ct= S 10-12 0.01 p.F (6) '-r-J rmsto average conversion Ct=[(~) x (~) x (ioo) x G)X IO.91)] 17.5 I portion of fault current shunted aroundGFI XO.OO08 (7) Application Circuits (Continued) in practice, the actual value of Cl will have to be modified to include the effects of the neutral loop upon the net charging current. The effect of neutral loop induced currents Is difficult to quantize, but typically they sum with normal fault currents, thus allowing a larger value of Cl. For Ul943 requirements, 0.015 ,.F has been found to be the best compromise between timing and noise. For those GFI standards not requiring grounded neutral detection, a still larger value capaCitor can be used and better noise immunity obtained. The larger capacitor can be accommodated because RN and RG are not present, allowing the full fault current, I, to enter the GFI. In Figllfl12, grounded neutral detection is accomplished by feeding the neutral coil with 120 Hz energy continuously and allowing some of the energy to couple into the sense transformer during conditions of neutral fault. Typical Application SENSE COIL GND/NEUTRAL COIL LOAD {HOT NEU;RAL MOV } LINE o--.....---t---<1"'i'Oo------I l-.....;;;;:;.;...-++-----------f ~;;.:::~H--o CIRCUIT BREA~ER D.DII4IDV -IN .....- ..... --4_........ +IN ..... RSEl 20GpF GNDH-..... •Adiust RSEf for desired sensitivity FIGURE 2. 120 Hz Neutral Transformer Approach S 10-13 TVHlSln-8 • ~ II) CD ~ ~ r-----------------------------------------------------------------------------------------Definition of Terms Normal Fault: An unintentional electrical path, Re, between the load terminal of the hot line and the ground; as shown by the dashed lines." HOT { LINE NEUTRAL ., HOT No~mal Fault plus Grounded Neutral" Fault: The combination of the normal fault and the grounded neutral fault, as shown by the dashed lines. HOT "~F { GFI LINE RG -1 ":" TL/H/S177-7 1 I TlIH/S177-9 Grounded Neutral Fault: An unintentional electrical path between the load terminal of the neutral line and the ground, as shown by the dashed lines. LINE RLOADI --ZtJ, L..._ _..I NEUTRAL -~- NEUTRAL HOT NEUTRAL TLlH/S1 77-8 S 10-14 Section 11 Motor Controllers .. ~ Motor Controllers Section Contents Tachometers LM1014 Motor Speed Regulator •..••.......•......•...•...••.•.. " ... , .•..••..•......•...........••........ S 11-1 ,-------------------------------------------------------------------------, r .... o .... i: ~National ~ Semiconductor ,0. LM 10 14 Motor Speed Regulator General Description The LM1014 is a monolithic integrated circuit specifically designed to provide a low cost motor speed regulator for low voltage DC motors. Features • • • • • Remote pause control Saturation voltage O.1V Motor connected to ground for ease of RF suppression Motor torque compensation Low current consumption • 5V to 20V operating voltage range • Short circuit protection Functional Block Diagram and Typical Connection R' TLlH/6159-1 Connection Diagram Dual-In-Line Package NDN-lNVERTINO INPIlT A2 IHVEBnNG INPUT AZ roROUE COMPENSATION I SHORT CIRCUIT PRIITECnDH INVERnNG INPUT Al REMOTE PAUSE CONTROL OUTPUT A1 GROUND POSITIVE SUPPLY TLlH/6159-2 Order Number LM1014N-2 See NS Package NOSE S 11-1 • Absolute Maximum Ratings Supply Voltage Operating Temperature Range 24V Storage Temperature Range Lead Temp. (Soldering, 10 seconds) -20 to +70'C -65 to + 150'C 300'C Electrical Characteristics (Note 1) Parameter Conditions Supply Voltage Range Supply Current Min Typ 5.0 Current into Pin 5 6.0 Reference Voltage Max Units 20.0 V 8.0 mA 2.0 %VREF 1.33 Line Regulation of Reference Voltage VS=5Vto Vs=20V Pin 2 Remote Stop Current Current into Pin 3 when Grounded Output Current A1 Vs=5V Pin2Gnd Short Circuit Current Limit R1=10 Motor Sense R1 =10, R2=2000 Current Deviation Current into Pin 2: 12 125 15 Comments V 200 0.3 mVl'C p.A (Note 2) 40 mA Current into Pin 7 1.4 A (Note 3) ±3.0 % (I2/Im-1) Exclusive of External Components Tolerances Note 1: Unless otherwise specified, 5V<:.Vs<:.20V and -15·C<:.TA<:.55·C. Note 2: The remote stop is activated by grounding pin 3. The motor restarts after disconnection of the ground connection. Note 3: The culT9nt limit is set by resistor AI, i.e., I "IAV fAt. When the output current exceeds this limi~ the drtve to the output transistor is switched off by a latch circuit The motor can only be restarted after interruption of the supply voltag~. Typical Performance Characteristicsl Application 1. The output voltage VM is given by: R3 R1 R3 VM=VREF(1+ R4)+IM 5R2 3. Parameter of the motor used for the test results shown below: RM=16.30 and back e.m.f.= 3.25V @2000r.p.m.;torque constant 5.9 mAlmNm; External components: R1 = 10 Cu, R2=2000 and R3=16 kO; VREF=1.33V 2. R1 R3.R52 must be equal to dynamic motor winding resistance RM in order to keep the speed constant during load torque variations. CSE=2.2 p.F and C3=0.47 p.F. Parameter Conditions Max Motor Speed Deviation (Voltage) Motor Speed Deviation (Load) Motor Speed Deviation (Temperature) Vs=5Vto 10V Vs=5Vt020V' IM=25 mA to 125 mA' ±0.5% ±1.0% ±1.0% T= +5'Cto +35'C T=-15'Cto +55'C 1.0% 3.0% S 11-2 en () :::T CD 3 I» ( ;' c i' cc DJ 3 en c'.> R8 P,7 RIO ":'4 TL/H/6159-3 t~O~lrn I ...... r----------------------------------------------------------------------------, Application Hints ::E ~ (:) .... This circuit has been primarily designed for cassette tape recorders, but is suitable for all low voltage DC motors, and performs the functions of motor speed control, remote stop (pause) and output short circuit protection. The circuit achieves good speed regulation under conditions of supply voltage, torque and temperature variations. Five components, a PNP pass transistor and four resistors, are required to match the circuit to the motor. As these are external to the IC a very wide range of motor characteristics can be accommodated. Motor speed control is by means of a negative output impedance voltage regulator. The negative output impedance is a function of the external resistors. If the output current exceeds a preset limit, the base drive to the external PNP transistor Is switched off and can only be restarted after reconnection of the supply voltage. The remote stop is activated by closing a DC switch. . System Description The voltage across the terminals of a DC motor is given by: VM=Eo+RMIM Eo= back e.m.f. - proportional to speed 1M = motor current - proportional to load torque RM= motor winding resistance The regulator must therefore be a source whose voltage can be controlled to maintain the desired back e.m.f., with a negative output resistance whose value equals the motor winding resistance in order to maintain the desired speed during torque variations. (See Figure 1) A block diagram of the system is shown in Figure 2 with the external components connected. The circuit comprises of a stable voltage reference source, Vrel, two high gain differential amplifiers, Al and A2, short circuit detector + latch and remote stop' circuit. Amplifier A2 is a high gain differential - input amplifier. (DC collector current: 125 p.A). Feedback through T1 maintains the potentials at the input terminals g and 10 equal, therefore the collector current of T1 will be in the ratio of Rl/R2 of the motor current 1M. This current is mirrored (5 : 1) and will be supplied via Rs. Amplifier A2 has been designed to work with its inputs at or near the supply voltage. Amplifier Al is also a high gain differential amplifier, but with Darlington inputs. (DC collector current :280 p.A). Feedback through T2, Rl, Rs and R4 maintains the potential at pin 1 equal to Vref. The total current through resistor Rs will be: The reference voltage source is based on the bandgap regulator principle(l) and comprises transistors Tl to Tl0. The reference voltage is given by: VreI=Vbel +VT(1 + RR!l:j In RR9 with RR9= 10 with VT=kT. 6 5 5 q The bandgap regulator is driven from an internally generated 3.8 V regulator. This regulator comprises of Tll/T16, T23 and resistors R7 and Re. Resistors R1S and R15, transistors T27 and T26 serve the sole purpose of starting this regulator. It only needs to supply enough base current to T11 to develop 600 mV across R7 to ensure start-up. This start-up network is disabled by transistor T24 as soon as the output voltage exceeds 3V. Resistors Rll and R12 are used to sense the output voltage for this purpose. Current limiting is provided by transistors T51, T52 and T5S. Whim the voltage across the external resistor Rl, connected between pin 8 and 10, becomes high enough to turn on T52 and T53 (approximately 1.4V), current source T51 turns on transistor T55 and the latch circuit changes state, i.e., T47 turns on. Hence transistor Tso is turned on by current source T42 and sinks all the base current supplied to T29, thereby switching off the external transistor. Transistor T25 holds off the start-up circuit. The latch can only be reset by interruption of the supply voltage: The latch circuit Is supplied with equal currents from two collectors of TOO. The purpose of the capacitor connected to the base of T47 is to ensure that the latch always starts in the "T47 off and T54 on" state. The remote stop is activated by connecting pin 4 to ground. Transistor T45 (collector current 180 p.A) activates current source T42. Transistor Tso is driven Into saturation by T42SWitching off the base drive to the external transistor. At the same time, the Darlington connected transistors T58 and T59 discharge the capacitors of the motorfilter and transistor T25 holds off the start-up circuit. After disconnecting pin 4, current source T42 turns off and transistor T29 will supply the maximum base drive to restart the motor. (1) R. J. Widlar. "New Developments in IC Voltage Regulators" IEEE Journal of Solid-State Circuits, February 1971. Vrel + 1M Rl R4 5R2 The output voltage VM is thus given by: V'=V M rei TlIH/6159-4 FIGURE 1. (1+Rs)+1 R1 RS R4 MSR;' Therefore by varying Rs/R4 a no load voltage Vo can be supplied which equals the back e.m.f. Eo of the motor at the desired speed. The value of the negative resistance Ro is given by: Rl(5~J The increase in output voltage VM due to an increase in motor current is given by A 1M Ro. The increase in the voltage drop across the motor winding resistor RM is A 1M RM. In order to keep the speed constant during load torque variations the resistance Ro must be equal to RM. S 11-4 System Description V' SHORT CIRCUIT DETECTOR H2 R1 .. TL/H/6159-1 FIGURE 2. Block Diagram 1. To ensure stable operation of the system the feedback loop requires compensation capacitors between the base-emitter of the power pass transistor and across R3 (to smooth current spikes caused by commutator brushes). Recommended values: Cbe = 2.2 - 10 mF C3 = 0.47 - 1 JIoF 2. To minimize the voltage drop between the supply line and the motor. resistor Rl should be kept to a very low value. Recommended values: Rl = 1-50 R2 = 2000 3. The output current limit is set by R1: llimit"" 1.4v/rl 4. An improved performance of' the system for supply voltage variations can be achieved by connecting a resistor between pin 1 and the supply voltage line. (Vrei 3 and Vref 4 only). Recommended values: R (VreI3) = 6.B MO temperature coefficient of the motor voltage and the output voltage VM. Ideally d Ro/dT is made equal to d RMI dT and d Vo/dT to dEo/dT. The temperature coefficient of Vo is a multiple of the temperature coefficient of the reference voltage Vref. Four reference voltages are available. two with a negative - and two with a positive temperature coefficient. Since dRM/dT is positive. a copper sensing resistor Rl (assuming R2 and R3 are both of the same type) will then give optimum speed regulation over the full temperature range. Altematively. a sensing resistor Rl with a more negative coefficient than that of RM can be employed e.g. carbon but then a reference voltage with a positive temperature coefficient must be used. However. care must be taken that the resistance Rl R3/5R2 never becomes more than RM. otherwise the system will overcompensate for torque changes and can become unstable. Therefore. when employing a sensing resistor with a negative temperature coefficient. RO must be made smaller than RM (factor 0.9). This will degrade the torque regulation accordingly. R(Vrel 4) = 4 MO 5. The overall temperature performance of the regulator system is primarily determined by the matching of the S 11-5 • Section 12 Consumer Circuits Consumer Circuits Section Contents Audio LM832 Dynamic Noise Reduction System DNR ................... : ..•.•....•..........•....•.•..•.....••.•.•. S 12·1 LM1036 Dual DC Operated TonelVolume/Balance Circuit. .•.....•..........•.........•................'........ S 12·9 LM1040 Dual DC Operated TonelVolume/Balance Circuit with Stereo Enhancement Facility .....••.......•....•.. S 12·18 LM1121A1LM1121B/LM1121C Dolby B·Type Noise Reduction Processor with DC Switching ....•...•••........... S 12·28 LM1875 20 Watt Power Audio Amplifier ....... : ..............................................................S 12·58 LM2879 Dual6'Watt Audio Amplifier ..•........••.•... " .. :. '.....•........ '" " ...•..••..•..••............. S 12·105 LMC835 Digital Controlled Graphic Equalizer ....... : ......•....•.•....•.....•...............•.............. S 12·126 Automotive LM1819 Air·Core Meter Driver ....•.•.....................................•..•.......•.·.....•.•.......•.•.• S 12·31 LM1949 )njector Drive Controller ..•.•..•.......•..'. ..•........••••.....................................•... S 12·87 LM1964 Sensor Interface Amplifier ••.......•.....•.••.....•.........••...............................••..•• S 12·95 LM2005 20·Watt Automotive Power Amplifier .•..•..•..........••....•...•..................•..•.......•..... S 12·99 Radio LM1863 AM Radio System for Electrically Tuned Radios •..•.•• , .••....•.••........•..•....•••.............•.• S 12-46 LM3361A Low Voltage/Power Narrow Band FM IF System ....•............•.••.• , .. , •.•.• '" ..............•. S 12·121 Video LM1823 Video IF Amplifier/PLL Detector System ............................................................ S 12·39 LM1884 TV Sterec;> Decoqer .........•...............................•....•.•..••......•..........•.....•..S 12·64 UoII1893 Carrier·CurrentTransceiver ..........................•..•.•...•.•..•.........•....•.......•........S 12·67 LM2889 TV Video Modulator .............................................................................S 12·112 r-------------------------------------------------------------------------, == J?'A NaHonal ~ Semiconductor DYNAMIC NOISE REDUCTION SVS1EM LM832 Dynamic Noise Reduction System DNRTM General Description Features The LM832 is a stereo noise reduction circuit for use with audio playback systems. The DNR system is noncomplementary. meaning it does not require encoded source material. The system is compatible with virtually all prerecorded tapes and FM broadcasts. Psychoacoustic masking. and an adaptive bandwidth scheme allow the DNR to achieve 10 dB of noise reduction. DNR can save circuit board space and cost because of the few additional components required. The LM832 is optimized for low voltage operation with input levels around 30 mVrms. For higher input levels use the LM1894. • • • • • • • • • Low voltage battery operation Non-complementary noise reduction. "single ended" Low cost external components. no critical matching Compatible with all prerecorded tapes and FM 10 dB effective tape noise reduction CCIR/ARM weighted Wide supply range. 1.5V to 9V 150 mVrms input overload No royalty requirements ' Cascade connection for 17 dB noise reduction Applications • • • • A trademark and licenSing agreement Is required for the use of this product Headphone stereo Microcassette players Radio cassette players Automotive radio/tape players Order Number LM832M See NS Package M14A Order Number LM832N See NS Package N14A Application Circuit L INI'IIT L iI.-----.. FROM SOURCE SELECTOR -----------------~~:~ME TAPE PREAMP. STEREOI FM DEMODULATOR, MONO AM DETECTOR, ETC. sw . . . - - - -...- - - , CONTROL C7 39nF R3 2k ON ~f D.65V 40k v+ 3 C3 4 ~22nF 6 C6 B2O"]IF R R FROM ~ 01) (0) ~ sc::re------.. . . ~~------------------------~---~~~ME CONTROL SELECTOR TLlH/5176-1 FIGURE 1. Component Hook-up for Stereo DNR System S 12-1 Absolute Maximum Ratings Supply Voltage Power Dissipation (Note 1) Input Voltage -65 to -t150"C Storage Temperature , '-40to +85· Operating Temperature (Note 1) 300·C Lead Temperature (Soldering, 10 se,conds) 10V 1.2W 1.7Vpp DC Electrical Characteristics TA ='25·CVcc = ~ymbol Parameter 3.0V Conditions VOP Operating Voltage Supply Voltage for Normal Operation Icc(1) Supply Current (1) Pin 9 to GND 0.1 /-IF, BW = Min, Note 2 Min Typ Max 1.5 3.0 9.0 V 2.5 4.0 mA rnA Units Icc(2) Supply Current (2), DC GND Pin 9 with 2k, BW = Max, Note 2 5.0 8.0 VIN(1) Input Voltage (1) Pin 2, Pin 13 0.20 '0.36 0.5 V VIN(2) Input Voltage (2) Pin 6 0.50 0.65 0.8 V VIN(3) Input Voltage (3) Pin 9 0.50 0.65 0.8 V VOUT(1) Output Voltage (1) Pin 4, Pin 11 0.20 0.35 ,0.50 V VOUT(2) Output Voltage (2) Pin 5 Stereo Mode 0.15 0.28 0.40 V VOUT(3) Output Voltage (3) Pin 5 Monaural Mode, DC Ground Pin 14 0.10 0.20 0.30 V VOUT(4) Output Voltage (4) Pin 8 0.25 0.40 0.60 V VOUT(5) Output Voltage (5) Pin 10 BW = Max, Note 2 1.00 1.27 1.50 V VOUT(6) Output Voltage (6) Pin 10 BW=Min, Note 2 0.50 0.65 0.75 V Vos Output DC Shift Pin 4, PIN 11; Change BW Min to Max 1.0 3.0 mV AC Electrical Characteristics Symbol I Parameter MAIN SIGNAL PATH (Note 3) Av Voltage Gain I Conditions I I Min VIN= 30 mVrms, f= 1 kHz, BW=Max, Note 2 -1.0 Typ 0.0 I Max I Units +1.0 dB dB C.B. Channel Balance VIN = 30 mVrms, f = 1 kHz, BW = Max, Note 2 -1.0 0 +1.0 fMIN Min Bandwidth 0.1 /-IF between Pin 9 - GND 600 1000 1500 Hz fMAX Max Bandwidth DC Ground Pin 9 with 2k 24 30 46 kHz THO Distortion VIN=30 mVrrns, f=1 kHz, BW=Max, Note.2 0.07 0.5 MVIN Max Input Voltage THD=3%, f= 1 kHz, BW= Max Note 2 120 SIN Signal to Noise REF = 30 mVrms, BW = Max, CCIRI ARM 60 ZIN Input Impedance Pin.2, Pin 13 14 20 C.S. Channel Separation Ref=30 mVrms, f=1 kHz, BW=Max, Note 2 40 68 dB VRIPPLE=50 mVrms, f= 100 Hz 40 55 dB PSRR PSRR 150 " % mVrms 68 dB 26 kO CONTROL PATH Aysum(1) Summing Amp Gain (1) VIN=30 mVrms at Rand L, f=1 kHz -3.0 -1.5 0.0 dB Avsum(2) Summing Amp Gain (2) PC Ground Pin 14, f= 1 kHz -9.0 -6.0 -3.0 dB Av 1st Gain Amp Gain Pin 6 to Pin 8 25 30 35 dB ZIN 1st Input Impedance Pin 6 28 40 52 kO AVPKD Peak Detector Gain AC In, DC Out; Pin'9 to Pin 10 25 30 35 VIV ZINPKD Input Impedance Pin9 500 800 1100 0 VRPKD Output DC Change Pin 10, Change BW Min to Max 0.5 0.62 0.8 V Note 1: For operation In ambient temperature above 25"C, the dQ;nce must be derated based on a 150"C maximum Junction temperature ";'d a thermal resistance junction to ambient, as follows: LM832N -90" clw, LM833M -150" c/w. Note 2: To force the DNR system into maximum bandwidth, connect a 2k resistor from pin 9 to GND, AC ground pin 9 or pin 6 to select minimum bandwidth. To change minimum and maximum bandwidth, see Application Hints. Note 3: The maximum noise reduction CCIRIARM weighted Is about 14 dB. This Is accomplished by changing the bandwidth from maximum to minimum. In actual operation, minimum bandwidth Is not selected, a nominal minimum bandwidth of about 2 kHz gives 10 dB of noise reduction. See Application Hints. S 12-2 External Component Guide (See Figure 1) PIN Recommended Value Effect Remarks Purpose Smaller Larger C1 10 ",F Power supply decoupling Poor supply rejection Better supply rejection Do not use less than 10 ",F C2,C11 1 ",F Input coupling capacitor Increases frequency of lowfrequency roll-off Reduces frequency of lowfrequency roll-off DC voltage at pin 2 and pin 13 is 0.35V Establishment of Min and Max Bandwidth Bandwidth becomes wider Bandwidth becomes narrower See Note 4 Output coupling capacitor Increases frequency of lowfrequency roll-off Reduces frequency of lowfrequency roll-off DC voltage at pin 4 and pin 11 is 0.35V f= _ _ 1_ 21TC2R'N O3,C10 22 nF for Stereo, 15 nF for mono C4,C8 1 ",F f C5 C6 C7 0.1 ",F 820pF 39nF C9 1 ",F R1,R2 Rl+R2=1 kn R3 e2kn Works with R1 and R2 to set one of the lowfrequency comers in control path Works with input resistance of pin 6 to set one of the low-frequency comers in the control path Works with input resistance of pin 9 to form part of control path frequency weighing Sets attack time This voltage divider sets control path sensitivity Sets gain amp load when DNR is OFF Some high frequency program material may be attenuated Same as above Bandwidth may increase due to low-frequency inputs, causing "Breathing" Same as above f 1 21TC4RLOAD 1 21TCs(R1 + R2) 1.6 kHz See Note 4 f= 1 21TCsRpINS 4.8 kHz See Note 4 Same as above Same as above f 1 21TC7Rp1N7 4.8 kHz See Note 4 Reduces attack and decay time Loads gain amp output, may cause distortion Increases attack and decay time - See Note 4 Sensitivity should be set for maximum noise reduction and minimum audible frequency program effect on high Max bandwidth will be reduced Note 4: The values of the control path filter components (C5. C6. C7, Cg. Rl. R2) and the integrating capacHors (Ga. CIO) should not be changed from the recommended values unless the charecteristics of the noise or progrem material differ substantially from that of FM or tape sources. Failure to use the correct values may result in degraded performance. and therefore the application may not be approved for DNR trademark usage. Please contact National Semiconductor for more information and technical assistance. S 12-3 :3 ....:=E Typical Performance 'Characteristics to I 9 !... ffi ..'" ::> '" !J I: ::> I I -f- 10 I I If I o I ~ o 4 I I 6 to -70 100 lk FREOUENCY (Hz) TlIH/5178-2 o od8=30 mYrms i-30 ~ -40 :0-50 co -60 -70 20 100 lk 10k FREQUENCY (Hz) H+++HIH+HI+IIII-+~-IIffio-l Htt!lllH-HJItIIH-++H~-t Htt!lllH+t:ItIIH-++H~-t H+1tfftt--+1tttHtt--t+tffiilH Htt!lllH+tiItllH-++H~-t Htt!lllH+hItllH-++H~-t 100 tk FREOUENCY (Hz) TlIH/5176-7 60 a;- 50 :s ~ I;TI;~40ld -60 tf- -70 NOMINALBW 1111111 I OdB=30mY 1111111 I -90 100 lk 20 FREQUENCY (Hz) '10k TLlH/5176-9 TLlH/5176-8 FIGURE 9. Frequency response for various Input levels FIGURE 8. Output vs frequency and control path signal ao Vee = 3.0V YiN =30 mYrms ~ ...!!,= -0.8%)- f - - --- 1'00-. 25 50 TEMPERATURE ('C) 75 TlIH/5176-11 FIGURE 11. Change In main signal path maximum bandwidth vs temperature S 12-4 10k FIGURE 7. THO vs frequency ViN=10dB =Od8 =-10d =-2Od = .,.30.d ~ -30 5 -40 c> -50 10k HttHIIH+tiItllH-++H~-t TlIH/5176-6 !-20 lk """"""'==""""""T"TTI""""'" :-;:::WlOTHiII , 1-If-H+lIlIH 20 lOOk FIGURE 6. Output level VB frequency o FREQUENCY (Hz) 10k O.~ 1:!l1t=!!l:I::!:IMI:j -90 -90 -10 . 100 '1 O,g f- ~INI1.\'8M BW 20 10 -20 H-IItlffiH-++ tOO lk FREOUENCY (Hz) TlIH/5176-4 O.B 0.7 iii 0.6 ;; 0.5 ~ 0.4 0.3 0.2 TlIH/5176-5 i 20 FIGURE 4. Power supply rejection ratio vs frequency MAXIMUM BW 1111I1IIJ"Ij". -10 -20 FIGURE 5. Output level change vs supply voltage -10 H+HfHI--+lf++!I -90 10k TL/H/5176-3 Va: (V) ~ -60 !il-70 Ii! -80 FIGURE 3. Channel separation vs frequency 10 :"'f- MINIMUM8W f- t-f-2 a;- -4 ~ -6 I!' -8 ::> co -10 -12 f-t4 YiN =30 mVrms f =400 Hz Ref 1 AT Vee =3V AND MAX BW -16 4 6 10 o ....f- 111111 20 ftff'- i MINIMUMBW .. -90 -90 Va: (V) I I I MAXlMUM8W l- E-50 MAXIMUMBW FIGURE 2. Supply current va supply voltage ft- § ~ -60 co I J 0 z -10 -20 ;;J -30 II: -40 i .... ~I I I I f- f- MINIMUM BW 5 4 3 r- =:::=~:, mVrms _ ~ IIIN=30 mYrms !-10 ~ -20 -30 iii -40 co -50 M~M~MIBW ::~ 10 0 Vce-3,OV _ ...~ ~ ...8 30 ~ 10 0 40 If WITHOUT 19 kHz t- PILOT_ , 20 o I 1~lfffi~ i- 100 lOOk lk 10k , FREQUENCY (Hz) TLlH/5176-10 """'" FIGURE 10. Gain of control path vs frequency -----------------------------------------------------------------------------, r i: Circuit Operation acts as an integrator and is unable to detect it. Because of this, signals of sufficient energy to mask noise open the bandwidth to 90% of the maximum value in less than 1 ms. Reducing the bandwidth to within 10% of its minimum value is done in about 60 ms: long enough to allow the ambience of the music to pass through, but not so long as to allow the noise floor to become audible. 3. Reducing the audio bandwidth reduces the audibility of noise. Audibility of noise is dependent on noise spectrum, or how the noise energy is distributed with frequency. Depending on the tape and the recorder equalization, tape noise spectrum may be Slightly rolled off with frequency on a per octave basis. The ear sensitivity on the other hand greatly increases between 2 kHz and 10kHz. Noise in this region is extremely audible. The DNR system low pass filters this noise. Low frequency music will not appreciably open the DNR bandwidth, thus 2 kHz to 20 kHz noise is not heard. The LM832 has two signal paths, a main signal path and a bandwidth control path. The main path is an audio low pass filter comprised of a gm block with a variable current, and a unity gain buffer. As seen in Figure 1, DC feedback constrains the low frequency gain to Av =' -1. Above the cutoff frequency of the filter, the output decreases at -6 dB/oct due to the action of the 0.022 /LF capacitor. The purpose of the control path is to generate a bandwidth control signal which replicates the ear's sensitivity to noise in the presence of a tone. A single control path is used for both channels to keep the stereo image from wandering. This is done by adding the right and left channels together in the summing amplifier of Rgure 1. The R1, R2 resistor divider adjusts the incoming noise level to slightly open the bandwidth of the low pass filter. Control path gain is about 60dB and is set by the gain amplifier and peak detector gain. This large gain is needed to E'nsure the low pass filter bandwidth can be opened by very low noise floors. The capaCitors between the summing amplifier output and the peak detector input determine the frequency weighting as shown in the typical performance curves. The 1 /LF capacitor at pin 10, in conjunction with internal resistors, sets the attack and decay times. The voltage is converted into a proportional current which is fed into the gm blocks. The bandwidth sensitivity to gm current is 70 Hz/ /LA. In FM stereo applications a 19 kHz pilot filter is inserted between pin 8 and pin 9 as shown in Figure 16. Application Hints The DNR system should always be placed before tone and volume controls as shown in Figure 1. This is because any adjustment of these controls would alter the noise floor seen by the DNR control path. The sensitivity resistors R1 and R2 may need to be switched with the input selector, depending on the noise floors of different sources, i.e., tape, FM, phono. To determine the value of R1' and R2 in a tape system for instance; apply tape noise (no program material) and adjust the ratio of R1 and R2 to slightly open the bandwidth of the main signal path. This can easily be done by viewing the capacitor voltage of pin 10 with an oscilloscope, or by using the.circuit of Figure 12. This circuit gives an LED display of the voltage on the peak detector capacitor. Adjust the values of Rl and R2 (their sum is always 1 kO) to light the LEDs of pin 1 and pin 18.-The LED bar graph does not indicate signal level, but rather instantaneous bandwidth of the two filters; it should not be used as a Signal-level indicator. For greater flexibility in setting the bandwidth sensitivity, R1 and R2 could be replaced by a 1 kO potentiometer. Normal methods of evaluating the frequency response of the LM 832 can be misleading if the input Signal is also applied to the control path. Since the control path includes a frequency weighting network, a constant amplitude but varying frequency input signal will change the audio signal path bandwidth in a non-linear fashion. Measurements of the audio signal path frequency response will therefore be in error since the bandwidth will be changing during the measurement. See Figure 9 for an example of the misleading results that can be obtained from this measurement approach. Although the frequency response is always flat below a single high-frequency pole, the lower curves do not resemble single pole responses at all. To change the minimum and maximum value of bandwidth, the integrating capacitors, C3 and Cl0, can be scaled up or down. Since the bandwidth is inversely proportional to the capacitance, changing this 0.022 /LF capaCitor to 0.015 /LF will change the typical bandwidth from 1 kHz-30 kHz to 1.5 kHz-44 kHz. With C3 and C10 set at 0.022 /LF, the maximum bandwidth is typically 30 kHz. A double pole double throw switch can be used to completely bypass DNR. A more accurate evaluation of the frequency response can be seen in Figure 8. In this case the main signal path is frequency swept while, the control path has a constant frequency applied. It can be seen that different control' path frequencies each give a distinctive gain roll-off. PSYCHOACOUSTIC BASICS . The dynamic noise reduction system is a low pass filter that has a variable bandwidth of 1 kHz to 30 kHz, dependent on music spectrum. The DNR system operates on three princi, pies of psychoacoustics. 1. Music and speech can mask noise. In the absence of source material, background noise can be very audible. However, when music or speech is present, the human ear is less able to distinguish the noise-the source material is said to mask the noise. The degree of masking is dependent on the amplitude and spectral content (frequencies) of the source material, but in general 'multiple tones around 1 kHz are capable of providing excellent masking of noise over a very wide freql,lency range. 2. The ear cannot detect distortion for less than 1 ms. On a transient basis, if distortion occurs in less than 1 ms, the ear The capacitor on pin 10 in conjunction with intemal resistors sets the attack and decay times. The attack time can be altered by changing the size of C9. Decay times can be . decreased by paralleling a resistor with C9, and increased by increasing the value of C9. When measuring the amount of noise reduction of DNR in a cassette tape system, the frequency response of the cassette should be flat to 10 kHz. The CCIR weighting network has substantial gain to 8 kHz and any additional roll-off in the cassette player will reduce the benefits of DNR noise reduction. A typical signal-te-noise measurement circuit is shown in Figure 13. The DNR system should be switched from maximum bandwidth to nominal bandwidth with tape noise as a Signal source. The reduction in measured noise is t!1e signal-to-noise ratio improvement. S12-5 CD W N Application Hints (Continued) ~~~~--------------------~~ 620 620 TL/H/5176-12 FIGURE 12. BBr Graph Display of Peak Detector Voltage TLlH/5176-13 FIGURE 13. Technique for Measuring SIN Improvement of the DNR System CASCADE CONNECTION Additional noise reduction can be obtained by cascading the DNR filters. With two filters cascaded the rolloff is 12 dB per octave. For proper operating bandwidth the capacitors on pin 3 and 12 are changed to 15 nF. The resulting noise reduction is about 17 dB. Agure 15 shows the monaural cascade cOnnection. Note that pin 14 is grounded so only the pin 2 input is fed to the summing amp and therefore the control path. Figure 14 shows the stereo cascade connection. Note that pin 14 is open circuit as in normal stereo operation. ,-----------L.OUTPUT '!1,.., v+---.~-~--~-~F--~-_+~-~-----.' 81* 1,.., L..__________-'-___ 8 OUTPUT RINPUT--f + ·Al + A2 = 1 kO (refer to application hints) FIGURE 14. Stereo cascade Connection TLlH/5178-14 -----------------------------------------------------------------------------, Application Hints (Continued) ~ 3: 00 W N ~------------OW~T 2k 39 nF ON r-~~----~~--~~----~----~~----~----~~~ ..~ v+....,I--... INPUT-------..I TL/H/5176-15 'RI + R2 = I kO (refer to application hints) FIGURE 15. Monaural Cascade ConnllCllon FMSTEREO When using the DNR system with FM stereo as the audio source, it is important to eliminate the ultrasonic frequencies that accompany the audio. If the radio has a multiplex filter to remove the ultrasonics there will be no problem. Standard audio multiplex filters are available for use at the output of the demodulator from several filter companies. Figure 16 shows the additional components L1, C15 and C16 that are added to the control path for FM stereo applications. The coil must be tuned to 19 kHz, the FM pilot frequency. This filtering can be done at the output of the demodulator, before the DNR system, or in the DNR system control path. 1~1-.-F---------~;-:-:;~~6:--- LOUTPUT + .f"l1~ 11 + 10 ON OFF /@R 1 FIIOM FMMPX SW T22RF + 'RI+R2=1 KO (refer to application hints) I~ R IN~T ----1 ROUTPUT + TLlH/S176-16 FIGURE 16. FM Stereo Application FOR FURTHER READING Tape Noise Levels Noise Masking 1. "Masking and Discrimination", Bos and De Boer, JAES, Volume 39, #4,1966. 1. "A Wide Range Dynamic Noise Reduction System" Blackmer, 'dB' Magazine, August-September 1972, Volume 6, #8. 2. "The Masking of Pure Tones and Speech by White Noise", Hawkins and Stevens, JAES, Volume 22, # 1, 1950. 3. "Sound System Engineering", Davis, Howard W. Sams and Co. 4. "High Quality Sound Reproduction", Moir, Chapman Hall, 1960. 2. "Dolby B-Type Noise Reduction System", Berkowitz and Gundry, Sert Journal, May-June 1974, Volume 8. 3. "Cassette vs Elcaset vs Open Reel", Toole, Audioscene Canada, April 1978. 4. "CCIR/ARM: A Practical Noise Measurement Method", Dolby, Robinson, Gundry, JAES, 1978. 5. "Speech and Hearing in Communication", Fletcher, Van Nostrand, 1953. S 12-7 ,. LM832 r OUTPtJT 'ill' r------.---~~~~----~t_----_1--~_t1~1_r------1_----~~~~r_--r_--~~1 vcc s: CD W I\) en i ¢ ii' o:;' ~ () c ::;: I) O.35V en () ::r CD 3 I» ( ;' C/) VII\o RINPUT 2, , , w.. , 11 13 LINPtJT ~ I\) ~I.II I t 1114 MONOIST I 1 t~~t.~ _ (_Jr.,. ItI Is OUT GAIN AMP IN E I I tIJ ( GAIN AMP OUT 1 -1 P 1 1 I 1,0 1 17 • PI< OUT PI 30 z .... I""- r-. r- 1-0.. I" i'... I" ~ r- r--CONIlITIONS:--- -50 ~~ k--" "'" V l,...; V V PIN 7 CONNECTED TO PIN 12 20 100 500 5k FREQUENCY (Hz) 20k iD :s 80 z co ~ 70 '" 2f k-'- r-. . . . ~ 'r--- 60 ill z 50 z c 13 40 FLAT FREOUENCY RESPONSE BALANCED GAINS 3D 20 0.5 0.2 r-.... ~ 20 10 ~ 0.1 ~ ~I~:tl- I-- r- -20 -40 -60 GAIN (dB) 2Dk ill 0.05 0.02 FLAT FREQUENC~~ RESPONSE' :: BALANCED GAINS ~ MAXIMUM GAIN ' Vcc=l2V ..L~" i" fr ~~r- ~ 0.01 Vcc-9V o 100 500 5k FREOUENCY (Hz) THO vs Input Voltage 1.0 TONE CONTROLS FLAT BALANCED GAINS CCIR FILTER .", e: '"co l- -60 Output Noise Voltage vsGaln 60 o 1 ~ ~ 0.01 '=1 kHz FUIT FREOUENCY RESPONSE -;BALANCED GAINS 0.00 10 0 -10 -20 -30 -40 -50 GAIN (dB) Loudness Control Characteristic 20 ...... .... 0.02 V,N=I00 mV TON CONTROLS FLAT -20 90 co :z: 10 12 14 16 SUPPLY VOLTAGE (V) 25 ,, 0.04 4 V4 OR V14 - CONTROL VOLTAGE (V) Channel Separation vs Frequency ~ 0.05 .,I ! THO vs Gain I'ooor. o 10 -40 0.06 CUT 40 Hz OR 16 kHz V' -10 -15 ~+-H-H-+-t-t""i -20 ~~.L-~~~~~.J-J 20 100 500 5k 2Dk FREOUENCY (Hz) 20k / / Loudness Compensated Volume Characteristic Tone Characteristic (Gain vs Frequency) ,-,--ro-ro-r---r-r....., -15 co .... 1 4 V9 - CONTROL VOLTAGE (V) -10 100 500 5k FREQUENCY (Hz) -10 -15 ~ -5 ~"---'~ ~~~~~~~~~ -5 1\ -10 ~-hl!--+- _ .... 2.0 ~ z ;;;: 5 / I . \ 10 I--po.jC--+ 20 _ I 10 !z I '" :s 15 1o:::-+-+-~+-+-~+--h"I -20 I \ 1/ o BOOST 40 Hz OR 16 kHz 10 '\ 15 k-t-l-=. ~ ~ 20 I 15 I CHANNEL , - I -16 -20 ~" o I -B -12 Tone Control Characteristic I .L -80 O.DD 0.0 0.2 0.4 0.6 0.8 INPUT VOLllIGE (VIm.) 1.0 TUH/5142-2 S 12-11 • Application Notes ,TONE RESPONSE The maximum boost and cut can be optimized for individual applications by.selection of the appropriate values of Ct (treble) and Cb (bass). The tone responses are defined by the relationships: 1 0.00065(1 - Bb) + Bass Response = . JCJl~ 1 + 0.~00658b JCJlCb Treble Response = 1 + jCJl5500(1 - atlCt 1+ jCJl5500atCt . Where Bb = at = 0 for maximum bass and treble boost respectively and Bb=.at= 1 for maximum cut. For the values of Cb and Ct of 0.39 ,..F and 0.01 ,..F as shown in the Application Circuit, 15 dB of boost or cut is obtained at 40 Hz and 16 kHz. ZENER VOLTAGE A zener voltage (pin 17=5.4V) is provided which may be used to bias the control potentiometers. Setting a DC level of one half of the zener voltage on the control inputs, pins 4, 9, and 14, results in the balanced gain and flat response condition. Typical spread on the zener voltage is ± 100 mV and this must be taken into account If control signals are used which are not referenced to the zener voltage. If this is the case, then they will need to be derived with similar accuracy. LOUDNESS COMPENSATION A simple loudness compensation may be effected by applying a DC control voltage to pin 7. This operates on the tone control stages to produce an additional boost limited by the maximum boost defined by Cb and Ct. There is no loudness compensation when pin 7 is connected to pin 17. Pin 7 can be connected to pin 12 to give the loudness compensated volume characteristic as Illustrated without the addition of further extema! components. (Tone settings "are for flat response, ~ and Ct as given in Application Circuit.) Modification to the loudness characteristic is possible by changing the capacitors ~ and Ct for a different basic response or, by a resistor network between pins 7 and 12 for a different threshold and slope. SIGNAL HANDUNG The volume control function of the LM1036 is carried out in two stages, controlled by the DC voltage on pin 12, to improve signal handling capability and provide a reduction of output noise level at reduced gain. The first stage is before the tone control proceSsing and provides an initial 15 dB of gain reduction, so ensuring that the tone sections are not overdriven by large input levels when operating with a low volume setting. Any combination of 'tone and volume settings may be 'used provided the output level does not ex,ceed 1 Vrms, VCC=12V (0.8 Vrms, Vcc=9V). At reduced gain « -6 dB) the input stage will overload if the input level exceeds 1.6 Vrms, Vcc=12V (1.1 Vrms, Vcc=9V). As there is volume control on the input stages, the inputs may be operated with a lower overload margin than would otherwise be acceptable, allowing a possible improvement in signal to noise ratio. Application Circuit 47k 18 17 1& LM1D36N 47"" 'p LOUDNESS CDMPEIISATION 0,47"" IN£TTI c:. BALANCE CONTROL D,Dl"",,}; 47k t-------"\M,....------.... ·~47k =~L TUH/5142-3 S 12-12 Applications Information increased, and for increased bass range Cb must be reduced. OBTAINING MODIFIED RESPONSE CURVES The LM1036 is a dual DC controlled bass, treble, balance and volume integrated circuit ideal for stereo audio systems. Rgure 1 shows the typical tone response obtained in the standard application circuit. (Ct= 0.01 /LF, Cb = 0.39 /LF). Response curves are given for various amounts of boost and cut. Rgures 2 and 3 show the effect of changing the response defining capacitors Ct and Cb to 2Ct, Cb/2 and 4Ct, Cb/4 respectively, giving increased tone control ranges. The values of the bypass capacitors may become significant and affect the lower frequencies in the bass response curves. In the various applications where the LM1036 can be used, there may be requirements for responses different to those of the standard application circuit given in the data sheet. This application section details some of the simple variations possible on the standard responses, to assist the choice of optimum characteristics for particular applications. TONE CONTROLS Summarizing the relationship given in the data sheet, basically for an increase in the treble control range C, must be 20 15 .. ... STANDARD APPLICATION CIRCUIT 10 ! ~ 2.7 2.0 1.4 0.7 0.0 -5 -10 -15 100 500 FREQUENCY 1Hz, 5k 20 5.4 !i 4.7 '" 4.0 :§ 3.4 ii 15 10 !z '" m . . ::lI ii z ... ~ -10 ;;: -15 :3 ~ ---:::: Ch/2 2Ct 100 500 5k FREQUENCY (Hz, TlIH/5142~4 TlIH/5142-5 .-l!lE!!.EASED CONTROL RANGE Ib 10 !i ~ 5 0 -10 -15 -20 j~ ~ - ~ -~ -~ 20 .! .... r~ - .......... -- ~~ Ch/4 414 100 20k FIGURE 2. Tone Characteristic (Gain vs Frequency) 15 :i -5 ~ ~ 20 FIGURE 1. Tone Characteristic (Gain vs Frequency) ! 5.4 4.7 !i ~ 4.0 :§ 3.4 2.7 iii ::lI 2.0 z 1.4 ~ 0.7 0.0 -20 20k 20 V ~? ~~ ~ ~~ '-'~ l1li"" ~ ~ _~[f' ~ ~ i-r--; ~ 0 -5 ..... . ii .... .. r-... - ... .... .. INCREASED CONTROL RANGE ..... .... ~ r- ~ 500 5k FREQUENCY (Hz) - 5.4 4.7 4.0 3.4 S !i ..'" :§ 2.7 il 2.0 iii m :II .... 1.4 ~ 0.7 ;;: 0.0 3 20k TL/H/5142-6 FIGURE 3. Tone Characteristic (Gain vs Frequency) • S 12-13 Applications Information (Continued) Rgure 4 shows the effect of changing Ct and Cb in the opposite direction to Ct/2, 2~ respectively giving reduced control ranges. The various results corresponding to the different Ct and Cb values may be mixed if it is required to give a particular emphasis to, for example, the bass control. The particular case with Cb/2, Ctis illustrated in Figure 5. Restriction of Tone Control Action at High or Low Frequencies It may be desired in some applications to level off the tone responses above or below certain frequencies for example to reduce high frequence noise. This may be achieved for the treble response by including a resistor In series with Ct. The treble boost and cut will be 3 dB less than the standard circuit when R = Xc. A similar effect may be obtained for the bass response by reducing the value of the AC bypass capacitors on pins 5 (channel 1) and 16 (channel 2). The internal resistance at these pins is 1.3 kG and the bass boost! cut will be approximately 3 dB less with Xc at this value. An example of such modified response curves is shown in Figure 6. The input coupling capacitors may also modify the low frequency response. It will be seen from Rgures 2 and 3 that modifying Ct and Cb 20 REOUCEO CONTROL RANGE 10 ! 5 ::::: I!I... 0 ~ -5 . -10 -15 bass LOUDNESS CONTROL The loudness control is achieved through control of the tone sections by the voltage applied to pin 7; therefore, the tone and loudness functions are not independent. There is normally 1 dB more bass than treble boost (40 Hz-16 kHz) with loudness control in the standard circuit. If a greater difference is desired, it is necessary to introduce an offset by means of Ct or Cb or by changing the nominal control voltage ranges. Figure 7 shows the typical loudness curves obtained in the standard application circuit at various volume levels (Cb=0.39 ""F). 20 - ~ ~~ ..;; ." I" .. ii... c: 15 e 3.4 ....Iii ~ 2 Cb Cr/2 5.4 4.7 4.0 10 !z 2.7 m :31 2.0 ili 1.4 0.7· ~ 0.0 .... ii . 100 500 FREOUENCY (Hz) 5k - -~..... 20k t. e' .... ~ -~ f- ::::::~ 100 20 5.• !i •. 7 j!! ••0 ~ 3.4 ... ~ ;: ii ~""" ..... ~~ ~ 0 -5 -15 -20 3 20 5 .. ...!,NCREASED BASS CONTROL RANGE -10 I---" :;: -20 . - Other Advantages of DC Controls The DC controls make the addition of other features easy to arrange. For example, the negative-going peaks of the output amplifiers may be detected below a certain level, and control from a high boost condi. used to bias back the tion, to prevent overloading the speaker with low frequency components. S 15 z for greater control range also has the effect of flattening the tone control extremes and this may be utilized, with or without additional modification as outlined above, for the most suitable tone control range and response shape. " 2.7 m :31 2.0 z 1.4 0.7 0.0 e " 3-. Cb/2 Cr 500 5k FREQUENCY (Hz) 2011 TLlH/5142~7 TUH/5142-B FIGURE 4. Tone Characteristic (Gain vs Frequency) 20 ;-~r-r__ FIGURE 5. Tone Characteristic (Gain vs Frequency) r-r-.--r---r.., 10 STANDAIID APPLICATIDN CIRCUff 15 10 ! z -10 ! 5 0 1-+-+-~:"+IIi~+-H z li ~ -5 I--t-I~--+-t---t--''''t--+-i -10 -15 -20 -30 -40 ~ 500 5k FREOUENCY 1Hz) ....i- ....... r-- ............ ....... ....... PIN TCONNECTED TO PIN 12 ." "" l,...o- '~ ko".o.39"F Ct=O.Ol"F -60 L-...L....L......I_L-l....L---L....L...J 100 -... .... ~ ............ -50 ., 20 -20 20 20k 100 500 FREQUENCY (Hz) 5k 20k TLlH/5142-10 TUH/5142-9 FIGURE 7. Loudness Compensated Volume Characteristic FIGURE 6. Tone Characteristic (Gain vs Frequency) S 12-14 r- s::: ..... Applications Information (Continued) Flflures 8 and 9 illustrate the loudness characteristics obtained with Cb changed to Cb/2 and Cb/4 respectively, Or being kept at the nominal 0.01 ,.,.F. These values naturally modify the bass tone response as in Figures 2 and 3. ance, this is easily done and high value resistors may be used for minimal additional loading. It is possible to reduce the rate of onset of control to extend the active range to -50 dB volume control and below. The control on pin 7 may also be divided down towards ground bringing the control action on earlier. This is iIIustrate~ in Rgure 12, With a suitable level shifting network between pins 12 and 7, the onset of loudness control and its rate of change may be readily modified. With pins 7 (loudness) and 12 (volume) directly connected, loudness control starts at typically - 8 dB volume, with most of the control action complete by -30 dB. Figures 10 and 11 show the effect of resistively offsetting the voltage applied to pin 7 towards the control reference voltage (pin 17). Because the control inputs are high imped10 -10 !-20 z ~ -3D -40 10 INCREASED BASS RESPONSE -- ,.... - r-.r--- ~- I' r-.... I"' ;-20 ............. I........ t..... Cb/2 Ct -50 ...... :--.. -10 r..... ~ INCREASED BASS RESPONSE ./ ~ "',. -40 ./'" , """-..... ' ,. 1/ r--- "- -3D Ct Cir/4 -50 ,f-' ....... ./ ./ ....... ...... -60 -60 20 100 SOD 5k FREQUENCY (Hz) 20 20k 100 500 5k FREQUENCY (Hz) 20k TL/H/5142-11 TL/H/5142-12 FIGURE 8_ Loudness Compensated Volume Characteristic 10 -20 ~ -3D -40 -50 -60 10 ~:~~~~~MC:::~~ -10 !z FIGURE 9. Loudness Compensated Volume Characteristic ~ r- .......... .."' p.... ......... ~ zti 100 (-20 z ..... ,....~ , ....... , ............. n~il~T -10 .... li -50 Q,=0.39,.F Cc=o.O'"" 5k ....,.... r- i '1'-0., -40 i.,...o" 5DD FREQUENCY (Hz) -30 ~::S~~~::~~F -60 20k """ ,...... 1'-0., n~1~7 20 100 50D FREQUENCY (Hz) TLlH/5142-13 -10 !-2D ~ -3~ -40 -50 -- - ...... LOUDNESS COMIENSATIOlI ,....f- " ' - ..... :--.. r...... .....' --~, " ..... i...--' ....... i...--' ....... ~ 1/ .. "~'!'~ 100 ,. ./ l- t-' rQ,=O.39,.F -60 20 5k 20k FIGURE 11. Loudness Compensated Volume Characteristic INCREASED RATE OF ONSET OF o TLlH/5142-14 FIGURE 10. Loudness Compensated Volume Characteristic 10 f- ....... i-'" f....... i-'" i""'" .... =0.0' ,.F 5DD 5k FREQUENCY (Hzl 2lik TL/H/5142-15 FIGURE 12. Loudness Compensated Volume Characteristic S 12-15 «:) Co) en Applications I_nformation (Continued) When adjusted for maximum boost in the usual application circuit, the LM1036 cannot give additional boost from the loudness control with reducing gain. If it is required. some additional boost can be obtained by restricting the tone control range and modifying Ct. CtJ. to compensate. A c;ircuit illustrating this for the case of bass boost Is shown in Figure 13. The resulting responses are given in Rgure 14 showing the continuing loudness control action possible with bass boost previously applied. USE OF THE LM1036 ABOVE AUDIO FREQUENCIES The LM1036 has a basic response typically 1 dB down at 250 kHz (tone' controls flat) and therefore by scaling Cb and Ct. it is possible to arrange for operation over a wide frequency range for possible use in wide band equalization applications. As an example Figure 15 shows the responses obtained centered on 10kHz with ~ = 0.039 poF and Ct=0.001 poF. 5k47k ~-......_~...".,.,.......~25k Uk TOP VIEW TL/H/5142-16 FIGURE 13. Modified Application Circuit for Additional Bass Boost with Loudness Control 10 -10 _ !-20 ~ 20 IRESIoNSES _~ wrtH MO~Fml CIRCUIT OF FIGURE 13 _ f"=: -3D I I I I I I 15 ~H LD~II!l" CONTRDI. IASS!OOST ~~ ! ..,I-'" z 11 C.JD.J,., Ct=rDl(" -40 -58 20 lOB 5BB 5k FREQUENCY (Hzl 1'. -15 ./ JL L,.ooV r-.... " V'MAXIMUM BASS AND TREBLE CI1I"- ....200 I 1k 5k 50k FREQUEHCY (Hz) 200k TL/H/5142-18 TL/H/5142-17 FIGURE 14. Loudness Compensated Volume Characteristic V I" D C.=D.D3~'" Ct.D.~ -5 -20 2011 MAxiMUM BASS AND TREBLE ioosT ~ 5 -ID I I -60 i"'-.... 10 AIIDITIOIIAL BASS BOOST OBTAINED FIGURE 15. Tone Characteristic (Gain va Frequency) S 12-16 en 3" 4~~r) 'If' ri-. I CHI VOLUME '2. :::;: YOWME AfII) BA1MCE 11 C5 r I I I r VOlUMEfr~ I1~r;L J 1J\ In~13) iw ::T CD in 52 I» CD 300 ill 3 (5 iil [ C/) ..... ~ :> .! -.J 1111 3(18) TREBLE CANCITOII 4 TREBLE CONTROL C •Connections reversed J: 7 LOUDNESS COMPENSATlDN 14 BASS CONTROL ~ ~ .,.!. • 9tO~W' . ~ Semiconductor ~Nat1onal PRELIMINARY LM1040 Dual DC Operated Tone/Volume/Balance Circuit with Stereo Enhancement r::=acility General Description Features The LM1040 is a DC controlled tone (bess/treble), volume and balance circuit for stereo appUcations in car radio, TV and audio systems. A stereo enhancement facility is included whereby the apparent stereo separation of systems requiring closely spaced speakers may be improved. An additional control input allows loudness compensation to be simply effected. . • • • • • Four control inputs provide control of the bass, treble, balance and volume functions through application of DC voltages from a remote control system or, alternatively, from four potentiometers which may be biased from a zener regulated supply provided on the circuit. . Wide supply voltage range, 9V to 16V Large volume control range, 75 dB typical Tone control, ±15 dB typical Channel separation, 75 dB typical Low distortion, 0.06% typical for an input level of 0.3 .Vrms • High signal to noise, 80 dB typical for an input level of 0.3 Vrms • Few external components required. Each tone response is defined by a single capaCitor chosen to give the desired characteristic. Block and 'Connection Diagrams Dual-In-Llne Package I.NTERNAl SUPPLY D£COUPlE ...!.j~=:;-,c:r--, INPUT 1 STEREO ENHANCEMENT -=-4-1---. ....-_HF22;;.. STEREO ENHANCEMENT 21 TREBLE CAPACITOR 2 TREBLE CAPACITOR 1 NC TREBLE CONTROL INPUT AC BYPASS 1 17 BASS CAPACITOR 2 BASS CAPACITOR 1 LOUDNESS COMPENSATION 9 CONTllOL INPUT 16 BASS CONTROL INPUT BALANCE CONTROL INPUT 11 GNO 12 '-------' TOPYIEW Order Number LM1040N See NS Package Number N24A S 12-18 TL/H/5147-1 Absolute Maximum Ratings Supply Voltage 16V Control Pin Voltage (Pins 6,9,11,14,16) Operating Temperature Range Electric~1 O·Cto + Vee' 70·C Storage Temperature Range -65·Cto Power Dissipation Lead Temperature (Soldering, 10 seconds) + 150·C 1.5W 300·C Characteristics Vee = 12V, TA = 25·C (unless otherwise stated) Conditions Parameter Supply Voltage Range Min Pin 13 Typ 9 Supply Current 35 Zener Regulated Output Voltage Current Pin 19 Maximum Output Voltage Pins 10,15; 1= 1 kHz Vee = 9V, Maximum Gain Vee=12V Max Units 16 V 45 mA 5 V mA 5.4 0.8 1.0 Vrms Vrms Maximum Input Voltage (Note 1) Pins2,23;f=1 kHz, Vee=9V Flat Response, Vee = 12V Gain=-10dB 1.3 1.1 1.6 Vrms Vrms Input Resistance Pins 2, 23; f = 1 kHz 20 30 k!l Output Resistance Pins 10,15;1=1 kHz Maximum Gain V(Pin 14)= V(Pin 19); f= 1 kHz -2 0 Volume Control Range 1=1 kHz 70 75 Gain Tracking Channel1-Channel2 1= 1 kHz o dB through -40 dB -40 dB through -60 dB Balance Control Range Pins 10,15; 1=1 kHz 20 1 2 !l 2 dB dB 3 dB dB 1 -26 -20 dB dB Bass Control Range (Note 2) 1=40 Hz, Cb=0.39 ",F V(Pin 16) = V(Pin 19) V(Pin 16)=OV 12 -12 15 -15 ' 18 -18 dB dB TrebleGontrol Ral)ge (Note2) , 1= 16 kHz, Ct= 0.01 ",F V(Pin 6) = V(Pin 19) V(Pin6)=OV 12 -12 15 -15 18 -18 dB dB Total Harmonic Distortion 1=1 kHz, VIN=0.3Vrms Gain=OdB Gain= -30 dB 0.06 0.03 0.3 % % Channel Separation . Signal/Noise Ratio f= 1 kHz, Maximum Gain Unweighted 100 Hz-20 kHz Maximum Gain, 0 dB = 0.3 Vrms CCIRtARM (Note 3) Gain=O dB, VIN=0.3 Vrms Gain= -20 dB, VIN= 1.0 Vrms Output Noise Voltage at Minimum Gain CCIRtARM (Note 3) 60 76 75 dB 80 dB 79 72 dB dB 10 Supply Ripple Rejection 200 mVrms, 1 kHz Ripple Control Input Currents Pins 6, 9,11,14,16 (V=OV) -0.6 Frequency Response -1 dB (Flat Response, 20 Hz-16 kHz) 250 35 Nole 1: The maximum permissible inpullevel is dependent on tone and volume settings. See Application Notes. Nole 2: The tone control range Is defined by capacitors Ct, and Ct. See Application Notes. Nole 3: Measured with a CCIR filter with a 0 dB level at 2 kHz and an average responding meter. S 12-19 16 ",V -2.5 ",A -50 dB kHz C) r---------------------------------------------------------~--------------------- :5 g Typical Performance Characteristics o Volume Control Characteristic / -20 !z iii ,I -40 -80 ~ ~ o ViN=300 mV_ I=I""z -24 -28 2 3 4 5 I 15 1 4 -5~~~~-r~~r1 ~ 0 - 20 L...-..L-J..-JL-.-J.....J---'_ _L-....l--l 100 500 5k FREOUENCY (Hz) 1.0 FlAT FREOUENCY 0.5 RESPONSE BAlANCED GAINS 0.2 MAXIMUM GAIN Vcc=12V 0.1 ~~ 500 100 Output Noise Voltage vsGaln 60 ~ ,! !C ~ I- ~ I 0.2 0.4 0.8 0.8 INPUT VOLTAGE (Vlms) o 1.0 ~'21 Channel Separation V8 Frequency 25 ~ ..... 1- .... '" ......1'- I... I 50 3D FLAT FREQUENCY RESPONSE BALANCED GAINS 20 100 500 5k FREQUENCY (Hz) ZOk' 15 ~ 1.6 1.4 ~ 1.2 ~ \ o -5 o -80 i1.0& 0.0& 81012141& SUPPLY VOUADE (V) 18 THDv8Gain , ~ 0.05 '" §: 0.03 co z: ~ ... 0.02 0.01 1=1 kHz FLAT FREQUENCY RESPONSE f-0.00 1 2 3 VB - CONTROL VOLTAGE (V) ..., I i 0.04 ~ 20k / ~HZ 16 kHz ...... 10 GAIN = -10 dB 1=1 ""z FlAT FREOUENCY RESPONSE 1.8 BALANCED BAINS" ~ VIM-l00 mY TON CD" ROLS FLAT 20 60 40 -40 -60 GAIN (dS) 1/ V- Input Signal Handling vs Supply Voltage 2.2 ii! Loudness Control Characteristic 90 z -20 ...... i--' 1/ III ~19V o V 12.0 ..... ~~ 1/ 100 5DO 51! FREQUENCY (Hz) 20 I_ TONE CONTROLS FLAT BALANCED GAINS CCIR FILTER ...... 1-0... t-.. t- ...... :--.., -40 ~ -60 2Ok· 51! -3D ....- .... r- ..... FREQUENCY (Hz) " ~ ~; Ii. ~i.oo' - -50 CONDITI NS~ PIN 9 CONNECTED TO PIN 14 1--.1-1-1---'--1-....1-...1.-.1-1 20 20k 0.01 c z: ! -51-+-hIf -15 ~+-HI-t-H~~~ 70 Loudness Compensated Volume Characterl8tlc -10 -10 iii' 80 CUT 40 Hz OR 16 kHz 10 iii' -20 :!!.. -10I-Hf-+ :!!. V 0123456 VB OR Vl6 - CONTROL VOUAGE (V) -15 - 20 0.00 0.0 L 15 ~+-t-~t-~~~~ !z 0.02 ..ilIis .. 5 10 ~p.j:-+ ~ 0.05 :/ -15 Tone Characteristic (Gain vs Frequency) THD vslnput Voltage z co -10 2Or-......,--,---r-,-~-.-......, Io.:-~-=- 20 g \ VII - CONTROL VOLTAGE (V) 10 ! -5 o / / ~ II V14 - CONTROL VOU'AGE (V) Tone Characteristic (Gain vs Frequency) 2O..-.,.-,-,.--":-'r--r--r-r-. BOOST 40 Hz OR 16kHz 10 ! 1\ \ I -16 -20 , / If iz -12 ~ Tone Control Characteristic 15 .1 CHANNEL 2 7 RCHANNEL1- -4 -8 ~ 1 .1 J o I -60 Balance Control Characteristic 4 BALANCED GAINS 10 0 -10 -20 -3D -40 -50 GAIN (dB) TL/H/5147-2 S 12-20 Application Notes out to facilitate this. The arrangement is shown below in basic form. TONE RESPONSE The maximum boost and cut can be optimized for individual applications by selection of the appropriate values of Ct (treble) and Ct, (bass). The tone responses are defined by the relationships: 1 + Bass Response = 1 0.1F 0.00065(1 - ab) . 'W C PlH2 b PlH23 + 0.00065ab jwCb Treble Response = 1 6.5k 6.5k CHANNEL 1 OUTPUT + jw5500(1 - atlCt 1 + jw5500atCt CHANNEL 2 OUTPUT TL/H/5147-3 With a monophonic source, the emitters have the same signal and the resistor and capaCitor connected between them have no effect. With a stereo Signal each transistor works in the grounded base mode for stereo components, generating an in-phase signal from the opposite channel. As the normal signals are inverted at this point, the appropriate phase-reversed cross-coupling is achieved. An effective level of coupling of 60% can be obtained using 4.7k in conjunction with the internal 6.5k emitter resistors; At low frequencies, speakers become less directional and it becomes desirable to reduce the enhancement effect. With a 0.1 p.F coupling capaCitor, as shown, roll-off occurs below 330 Hz. The coupling components may be varied for alternative responses. Where Bb = at = 0 for maximum bass and treble boost respectively and ab = at = 1 for maximum cut. For the values of Cb and Ct of 0.39 p.F and 0.01 p.F as shown in the Application Circuit, 15 dB of boost or cut is obtained at 40 Hz and 16 kHz. STEREO ENHANCEMENT When stereo system speakers need to be closer than optimum because of equipmenVcabinet limitations, an improved stereo effect can be obtained using a modest amount of phase-reversed interchannel cross-coupling. In the LM1040 the input stage transistor emitters are brought Application Circuit r------...--..y..,.,.-.. . . 47k ~47k BASS CONTROL 4.7k 47k VOLUME CONTROL STEREO ENHANCEMENT ON OOFF 0.22 F ;J; ON LOUDNESS COMPENSATION OFF ... ... 47k ----~~-"V'I,.,. 0.1F ~47k BALANCE CONTROL +---------'\M....------__~47k~:~~L ;/;0.22 F TL/H/5147-4 S 12-21 Application Notes (Continued) ZENER VOLTAGE A zener voltage (pin 19=5.4V) is provided which may be used to bias the control potentiometers. Setting a DC level of one half of the zener voltage on the control inputs, pins 6, 11,. and 16, results in the balanced gain and flat response condition. Typical spread on the zener voltage is ± 100 mV and this must be taken into account if control signals are used which are not referenced to the zener voltage. If this is the case, then they will need to be derived with similar accuracy. TONE CONTROLS Summarizing the relation~hip given in the data sheet, basically for an increase in the treble control range Ct must be increased, and for increased bass range ~ must be reduced. Ftgur9 1 shows the typical tone response obtained in the standard application circuit. (Ct=O.01 ""F, Cb=0.39 ""F). Response curves are given for various amounts of boost and cut. '--"T"n-~N"'DAR"T""DAPPIJ-r--'CATI...--rDN-'CI-Rr-cu'rr--' 20 LOUDNESS COMPENSATION A simple loudness compensation may be effected byapplying a DC control voltage to pin 9. This operates on the tone control stages to produce an addHional boost limited by the maximum boost defined by Cb and Ct. There is no loudness compensation when pin 9 is connected to pin 19. Pin 9 can be connected to pin 14 to give the loudness compensated volume characteristic as illustrated without the addHion of further external components. (Tone settings are for flat response, Cb and Ct as given in Application Circuit.) Modification to the loudness characteristic is possible by changing the capacitors Cb and Ct for a different basic response or, by a resistor network between pins 9 and 14 for a different threshold and slope. SIGNAL HANDLING ' The volume control function of the LM1040 is carried out in two stages, controlled by the DC voltage on pin 14, to improve signal handling capabilHy and provide a reduction of output noise level at reduced gain. The first stage is before the tone control processing and provides an initial 15 dB of gain reduction, so ensuring that the tone sections are not overdriven by large input levels when operating wHh a low volume setting. Any combination of tone and volume settings may be used provided the output level does not exceed 1 Vrms, Vcc=12V(0.7 Vrms, Vcc=9V). At reduced gain « -6 dB) the input stage will overload if the input level exceeds 1.6 Vrms, Vcc=12V (1.1 Vrms, Vcc=9V). As there is volume control on the input stages, the inputs may be operated with a lower overload margin than would otherwise be acceptable, allowing a possible improvement in signal to noise ratio. 15 a ::~ i 3.4 i 10 F"~~+-+--+--+--h~ 4.0 "'" I:;::t;:;I~.--t-t-TIIJ!;j-j i z ii 1-"F:JoJtIf-++-t-"~.Fl -5 2.7 ::I 2.0 iii i -ro :~ -15 0.0 .: ~ -20 20 100 500 FREQUENCY (Hz) 5k 20k TUH/5147-5 FIGURE 1. Tone Characteristic (Gain vs Frequency) ~ Rgures 2 and 3 show the effect of changing ,the response defining capacitors Ct and Cb to 2Ct, Cb/2 and 4Ct, ~/4 respectively, giving increased tone control ranges. The values of the bypass capacitors may become significant and affect the lower frequencies in the bass response curves. 20 ..... 15 10 ! Ii '-' I- r...; ~ 5 a -5 -10 -15 -20 INCRWED CONTROL RANGE ,,;' 5.4 ~ , £. 1--0 ~ ~ --- ~ '-' t:::::" 100 Q,/2 i 4.7 4.0 ~ 3.4 ~r;...- ~ .... ~ ~ 2Ct 500 FREOUENCY (Hz) I iI ~ ~~ ~ ~,. 20 ,.,. "" 5k 2.7 2.0 .. i 1.4 0.7 &I 0.0 :3 20k TL/H/5147-6 Applications Information FIGURE 2: Tone Characteristic (Galnvs Frequency) OBTAINING MODIFIED RESPONSE CURVES 20 The LM1040 is a dual DC controlled bass, treble, balance and volume integrated circuit ideal for stereo audio systems. In the various applications where the LM1040 can be used, there may be requirements for responses different to those of the standard application circuit given in the data sheet. This application section details some of the simple variations possible on the standard responses, to assist the choice of optimum characteristics for particular applications. 5.4 15 4.7 10 4.0 c co 3.4 2.7 ! z C '" a i... 0 I 31 ...iii 1.41 -5 2.0 -10 0.7 ~ 0.0 :3 -15 -20 20 100 500 5k FREQUENCY (Hz) 20k TLlH/5147-7 FIGURE 3: Tone Characteristic (Gain vs Frequency) S12-22 -----------------------------------------------------------------------------, r 3: .... Applications Information (Continued) Figure 4 shows the effect of changing Ct and Cb in the opposite direction to Ct/2, 2Cb respectively giving reduced control ranges. The various results corresponding to the different Ct and Cb values may be mixed if it is required to give a particular emphasis to, for example, the bass control. The particular case with Cb/2, Ct is illustrated in Figure 5. RESTRICTION OF TONE CONTROL ACTION AT HIGH OR LOW FREQUENCIES It may be desired in some applications to level off the tone responses above or below certain frequencies for example to reduce high frequency noise. This may be achieved for the trellie response by including a resistor in series with Ct. The treble boost and cut will be 3 dB less than the standard circuit when R = Xc. A similar effect may be obtained for the bass response by reducing the value of the AC bypass capacitors on pins 7 (channel 1) and 18 (channel 2). The internal resistance at these pins is 1.3 kO and the bass boost/cut will be approximately 3 dB less with Xc at this value. An example of such modified response curves is shown in Figure 6. The input coupling capaCitors may also modify the low frequency response. . 20 a 5 ~ 0 .. -5 -10 ·-15 REDUCED CONTROL RANGE i::' ~ ~ ... ..;== ...... Iii' ~~ " 5.4 4.7 4.0 3.4 2.7 :--. 2.0 1.4 ~ 0.7 'e LOUDNESS CONTROL The loudness control is achieved through control of the tone sections by the voltage applied to pin 9; therefore, the tone and loudness functions are not independent. There is normally 1 dB more bass than treble boost (40 Hz-16 kHz) with loudness control in the standard circuit. If a greater difference is desired, it is necessary to introduce an offset by means of Ct or Cb or by changing the nominal control voltage ranges. Figure 7 shows the typical loudness curves obtained in the standard application circuit at various volume levels (Cb = 0.39 ",F). 20 O.p 2 Q, CtI2 100 500 FREQUENCY (Hz) 5k l- t- ~ 10 . .. . $! ;a 5 m :31 ;- 0 iii -5 ~ -10 iii -15 :s -20 20 '" ~ < co It e"" ;......:::!! .... ;:t: ..-:::.iii""" ~ ~ >- f- ~ ~ ~~ i-" ~I' ,... Ct./2 20 100 5.4 !j 4.7 '" ~ 4.0 C§ 3.4 .~ . .. " :s Ct -20 20k .. INCREASED BASS CONTROL RANOE 15 z 500 2.7 :!! 2.0 z 1.4 ~ 0.7 0.0 5k!Ok FREOUENCY (Hz) TL/H/5147-8 FIGURE 4. Tone Characteristic (Gain vs Frequency) TL/H/5147-9 FIGURE 5. Tone Characteristic (Gain vs Frequency) 10 20r-.-.-r-~~r-,-,-, STANDARD APPLICATION CIRCUIT 15 10 ! z iii -10 ~ 0 ~~~+-~~~-+-+-1 ii -30 t--+-1Mf'---i'-+-t-~-t--i -40 -10 -15 -20 ,.-. -, -50 100 500 5k ~ ...... ........ .............. PIN 9 CONNECTED TO PIN 14 .... ........ ..... , . /1""., V ::--0.39 pi' C,=O.OI pi' -60 ~~~~~~~~~~ 20 - .... ;-20 ..... ........... r-.... z 5 -5 A C) The DC controls make the addition of other features easy to arrange. For example, the negative-going peaks of the output amplifiers may be detected below a certain level, and used to bias back the bass control from a high boost condition; to prevent overloading the speaker with low frequency components. co 10 C) OTHER ADVANTAGES OF DC CONTROLS !j 15 ;a It will be seen from Figures 2 and.3 that modifying Ct and Cb for greater control range also has the effect of flattening the tone control extremes and this may be utilized, with or without additional modification as outlined above, for the most suitable tone control range and response shape. 20 20k FREQUENCY (Hz) TL/H/5147-10 100 500 FREOUENCY (Hz) 5k 20k TUH/5147-11 FIGURE 7. Loudness Compensated Volume Characteristic FIGURE 6. Tone Characteristic (Gain vs Frequency) S 12-23 • C) ~ po ~ r--------------------------------------------------------------------------------Applications Information (Continued) Figures 8 and 9 illustrate the' loudness characteristics obtained with Ct, changed to Ct,/2 and Cb/4 respectively, Ct being kept at the nominal 0.01 ,..F. These values naturally modify the bass tone response as in Figures 2 and 3. With pins 9 (loudness) and 14 (volume) directly connected, loudness control starts at typically - 8 dB volume, with most of the control action complete by -30 dB. voltage (pin 19). Because the control inputs are high impedance, this is easily done and high' value resistors may be used for minimal additional loading. It is possible to reduce the rate of onset of control to extend the active range to - 50 dB volume control and below. The control on pin 9 may also be divided down towards ground bringing the control action on earlier. This is illustrated in Figure 12. With a suitable level shifting network between pins 14 and 9, the onset of loudness control and its rate of change may be readily modified. Figures 10 and 11 show the effect of resistively offsetting the voltage applied to pin 9 towards the control reference 10 10 -10 i -20 z ~ -30 -40 INCREASED BASS RESPONSE INCREASED BASS RESPONSE -...r-. -r-~ ....... i-'" .... 10-"" ........ !".... ........ Cb/2 Ct ........ -50 .... - -10 ~ L I' ",. r..... r--. r.... -30 -40 1/...... - .... ;: -20 Cb/4 Ct 'i'oo. I,...;' .... .... " 'r-... . / ",. I,...;' 'i'oo. -50 -60 -60 20 100 500 . 5k FREDUENCY (Hz) 20 20k 100 500 5k FREDUENCY (Hz) 20k TL/H/5147-13 TL/H/5147-12 FIGURE 9. Loudness Compensated Volume Characteristic FIGURE 8. Loudness Compensated Volume Characteristic 10 -10 i z . is -20 -r-. ..... i' ..... -40 l -30 -50 10 :~:::'=~:F """ ,.' ........ ,.~,. -50 20 100 -i-'" ..... 1/..... -- -10 !-20 z is -30 --... -40 -50 C.~O.39"F Ct=O.01 F 500 &k FREOUENCY (Hz) ~::~:~~~=~ o -50 """ n~]~1 20 20k ...... r-.... 1....... i'oo. 100 500 FREOUENCY (Hz) TL/H/5147-14 !-20 ~ -30 -40 INCREASED IIAlIl OF ONSET OF LOUDNESS COMPENSA1IOII ~ ~ ... r0- t--.. r-- ....... t--- t...... ............. r-- !"....I 'r..... l- f- ...... 10-"" i"..- ...... ...... ~ I,...;' ""'.1:: ~ ~ ee. .. O.39"F ~~ l- I- VCt=O.Ol"F -50 111 -60 20 20k FIGURE 11. Loudness Compensated Volume Characteristic 10 -10 5k TL:IH/5147-15 FIGURE 10. Loudness Compensated Volume Characteristic o --...- ... .... 100 500 5k FREQUENCY (Hz) 20k TLlH/5147-16 FIGURE 12. Loudness Compensated Volume Characteristic S 12-24 Applications Information (Continued) USE OF THE LM1040 ABOVE AUDIO FREQUENCIES When adjusted for maximum boost in the usual application circuit. the LM-l040 cannot give additional boost from the loudness control with reducing gain. If it is required. some additional boost can be obtained by restricting the tone control range and modifying Ct. Cb. to compensate. A circuit illustrating this for the case of bass boost is shown in Figure 13. The resulting responses are given in Rgure 14 showing the continuing loudness control action possible with bass boost previously applied. The LM1040 has a basic response typically 1 dB down at 250 kHz (tone controls flat) and therefore by. scaling Cb and C" it is possible to arrange for operation over a wide frequency range for possible use in wide band equalization applications. As an example Figure 15 shows the responses obtained centered on 10 kHz with Cb=0.039 p.F and Ct=O.OOI p.F. LM1040N 19 18 5k 17 Cb~0.22 #-;J; 16 10 15 11 14 12 13 47k r ,# 25k O 22 . 5k TOP VIEW TUHf5147-17 FIGURE 13. Modified Application Circuit for Additional Bass Boost with Loudness Control 20 15 10 -10 ! -20 ~ -30 -40 ! I""' 20 dB (Vs=20V) • Encode output may be used for meter drive in all modes Connection Diagram Dual-In-Line Package NEGATIVE SUPPLY...! v ..! ~POSITIVE SUPPlY ~~ONITOROUTPUTI DECODE OUTPUT ~ENCOOE OUTPUT RECTIFIER OUTPUT-=VARIABLE IMPEOANC~..! CONTROL AMPLIFIER 0 5 FEEDBACK OECOUPUNG- .1! AMPUFIER EK ~INPUT 2!. ~MPLlFIER AB OUTPUT .!!.OECODE INPUT ...! NOISE REDUCTIO~.!. SWITCH 2!!.MODE SWITCH VaEF...! !... ENCODE INPUT TOP VIEW TUH/5160-1 Order Number LM1121AN, LM1121BN or LM1121CN ' See NS Package Number N16E Available to licensees of Oolby Laboratories Ucensing Corporation, San Francisco, CA, from whom licensing and applicetions information must be obtained. S 12-28 Absolute Maximum Ratings Supply Voltage Operating Temperature Range Storage Temperature Range Lead Temp. (Soldering, 10 seconds) 21V - 20'C to + 70'C - 60'C to + 150'C 300'C (Vs= 12V, TA=25'C unless otherwise specified) N.B. 0 dB refers to Dolby level and is 580 mVrms measured at TP1. LM1121A Conditions Min Supply Voltage Range Supply Current Voltage Gain Pin90r11-12 1 kHz, Pin 12 Open Signal/Noise Ratio Encode CCIR/Arm Filter Pin 14, Rs=10k Rs=1k Pin 15, Rs= 10k Pins 14 and 15 Rs=10k Rs=1k Decode NROFF Encode Characteristics 10kHz,OdB 1.3 kHz, -20 dB 5kHz, -20 dB 3kHz, -30dB 5 kHz, -30 dB 10 kHz, -30 dB 10 kHz, -40 dB Variation in Encode Characteristics with Temperature O'C-70'C Distortion 1 kHz,OdB 10 kHz, 8 dB Signal Handling 1 kHz, Dist=0.3% Vs=7.5V Vs=12V Vs=20V Switching Transients Measured at Pin 14 or 15 Encode/ Decode/Encode Typ 7 1 kHz, Noise Voltage Gain Pins 9-14 and 11-15 Reduction OFF 25.2 LM1121B Max Min 20 7 17 24 25.7 26.2 24.7 19.7 0 -16.2 -17.3 -21.7 -22.3 -24.0 -30.1 Min 20 7 17 24 25.7 26.7 71 24.2 Typ Units Max 20 V 17 24 mA 25.7 27.2 dB 19.7 dB 69 75 83 75 83 dB dB dB 83 85 83 85 83 85 dB dB 0.5 -15.7 -16.8 -21.2 -21.8 -23.5 -29.6 0.03 0.2 1.0 -15.2 -16.3 -20.7 -21.3 -23.0 -29.1 -0.2 -16.7 -17.8 -22.2 -22.8 -24.5 -30.3 0.5 -15.7 -16.8 -21.2 -21.8 -23.5 -29.6 1.2 -14.7 -15.8 -20.2 -20.8 -22.5 -28.9 -0.5 -17.2 -18.3 -22.7 -23.3 -25.0 -30.6 <±0.5 0.1 11.2 16.0 21.0 0.03 0.2 10 20 NR OFF/ON/OFF LM1121C Max 75 83 <±0.5 10 Typ 19.7 71.5 See A"gure 1 10 20 20 dB dB dB dB dB dB dB <±0.5 dB 0.03 0.2 0.1 11.2 16.0 21.0 0.5 1.5 -15.7 -14.2 -16.8 -15.3 -21.2 -19.7 -21.8 -20.3 -23.5 ' -22.0 -29.6 -28.6 20 0.2 ~ 11.2 16.0 21.0 dB dB dB 20 mV 45 4.3 65 5.6 80 6.9 45 4.3 65 5.6 80 6.9 45 4.3 65 5.6 80 6.9 Output Resistance Pin 12 Pins 14 and 15 1.8 2.4 30 3.0 55 1.8 2.4 30 3.0 55 1.8 2.4 30 3.0 55 kn kn kn n Control Levels (Pin 7) NROFF NROFF NRON Vs=7V-20V Vs 3.4 Vs 3.4 Vs V 1.2 V Control Levels (Pin 10) Encode Decode Decode Vs=7V-20V Vs V Input Resistance Pins 7 and 10 Open -0.2 3.4 Open 1.2 -0.2 Vs 3.4 Open -0.2 Open 1.2 -0.2 Vs 3.4 Open 1.2 21 -0.2 S 12-29 Open 1.2 21 -0.2 1.2 21 ..... r .... == .... N .... n mV 20 Pins 9 and 11 Pin 13 3.4 .... N .... OJ % % Inp'ut Resistance . N .... ~ .... Electrical Characteristics Parameter !i:.... .... V kn • (,) ,.. N ,.. ,.. ~ iii ,.. ,.. ,.. ~ N Schematic Diagram OECODEINPUT ENCODI! OUTPUT emIl MONITOR OUTPUT y. 18 :c,.. moD 14 IS ENCODE INPUT 0.47 D.47 11 MOOESWITCH 10 N ,.. ,.. ::::I!! ..I 3 GaDti 10/15 R304 NR SWITCH 27D~ + R30II 15k Ga04 0.047 C3D5 D.l 5% C3D7 0.33 5% t---~--t-------~----~~~~~--~------------t~u y- C202 "'1:'"220115 y- y- TUH/5160-2 Circuit Diagram 14 ENCODE OUTPUT LMl121 1 10k /".J\I1IV-....._7!.j ~TCH TUH/5160-3 FIGURE 1. Measurement-Swltchlng Transients S 12-30 ~National PRELIMINARY ~ Semiconductor LM 1819 Air-Core Meter Driver General Description Features The LM1819 is a function generator/driver for air-core (moving-magnet) meter movements. A Norton amplifier and an NPN transistor are included on chip for signal conditioning as required. Driver outputs are self-centering and develop ± 4.5V swing at 20 mAo Better than 2% linearity is guaranteed over a full 305-degree operating range. • • • • Self-centering 20 mA outputs 12V operation Norton amplifier Function generator Applications • Air-core meter driver • Tachometers • Ruggedized instruments TYfJical Application VSA,=14.4Y D4 R7 lN4007 3.3k FROM --IM---J\M~t----'-J\I\III-.... POINTS SIGNAL Is Dl lN4007 R& 10k R3 lOt D2 2N474& t lBY lW Rl 33k Cl 2.7 nF COSINE L...J~~Y"\..AI'V"trv"I..L..J TLlH/S263-1 FIGURE 1. Automotive Tachometer Application. Circuit shown operates with 4 cylinder engine and deflects meter pointer (270°) at 6000 RPM. Order Number LM1819N See NS Package Number N14A S 12-31 ~ .... .... CD Q) Absolute Maximum Ratings Supply Voltage, V+ (pin 13) Power Dissipation (note 1) Operating Temperature 20V 700mW -40"C to 85'C Storage Temperature Lead Temp. (Soldering, 10 seconds) BVCEO -65·G.to -150'C 300'C 20VMIN Electrical Characteristics Vs = 13.1VTA = 25'C unless otherwise specified Parameter Supply Current Regulator Voltage Regulator Output Resistance Reference Voltage Reference Output Resistance Norton Amplifier Mirror Gain NPN Transistor DC Gain Function Generator Feedback Bias Current Drive Voltage Extremes, Sine and Cosine Sine Output Voltage with Zero Input Function Generator Linearity Function Generator Gain Pln(s) 13 Conditions Zero Input Frequency (See Figure 1) . 11 IREG = OmA 11 IREG = Ot03mA 4 IREF = OmA 4 IREF = 0 to 50 /loA 5,6 ISlAS'" 20/loA Typ Min 8.1 8.5 2,12 2 Symbol Is Units mA 8.9 VREG V !l 13.5 1.9 2.1 2.3 .9 k!l 1.1 1.0 125 V1 = 5.1V ILOAD Va = 20mA = VREF FSD hFE 1.0 mA ±4 ±4.5 V -350 0 +350 mV ±1.7 O/OFSD = 305' Meter Deflectionl aVa V VREF 5.3 9, 10 1 Max 65 50.75 53.75 k 5/?75 Degreesl Volt 1: For operation above 2S'C, the LMI B19 must be derated based upon a 125'C maximum iunction temperature and a Ihennal resistance of 12fY'C/W which applies for the device soldered in a printed circuit board and operating in a still-alr ambient Note Application Hints AIRoCORE METER MOVEMENTS Air-core meters are often favored over other movements as a result of their mechanical ruggedness and their independence of calibration with age. A simplified diagram of an aircore meter is shown in Figure 2. There are three basic pieces: a magnet and pointer attached to a freely rotating axle, and two coils, each oriented at a right angle with respect to the other. The only moving part in this meter is the axle assembly. The magnet will tend to align itself with the vector sum of H fields of each coil, where H is the magnetic field strength vector. If, for instance, a current passes through the cosine coil (the reason for this nomenclature will become apparent later) as shown in Figure 3(a), the magnet will align its magnetic axis with the coil's H field. Similarly, a current in the sine coil (Figure 3(b) causes the magnet to align itself with the sine H field. If currents are applied simultaneously to both sine and cosine coils, the magnet will turn to the direction of the vector sum of the two H fields (Figure 3(c)). H is proportional to the voltage applied to a coil. Therefore, by varying both the polarity and magnitude of the coil voltages the axle assembly can be made to rotate a full 360'. The LM1819 is designed to drive the meter through a minimum of 305'. POiNTER MAGNET . ~ ~' ~ '1 ;;; ~ 2 LAIIIIE COILS OF WIRE MOUNTED AT RIGHT ANGLES, WITH MAGNET MOUNTED IN CENTER or<'>OOO COSINE COIL II<>=<><> SINE COIL --~ ~ TL/H/5263-2 FIGURE 2. Simplified Diagram of an Air Core Meter. S 12-32 Application Hints (Continued) E€~~f~~5=< SINE COIL ====~~~===( ~~~~ I I COSINE COIL I COSINE COIL COSINE COIL TL/H/5263-3 ~ ~ ~ FIGURE 3. Magnet and pointer position are controlled by the B field generated by the two drive colis. In an air·core meter the axle assembly is supported by two nylon bushings. The torque exerted on the pointer is much greater than that found in a typical d' Arsonval movement. In contrast to a d'Arsonval movement, where calibration is a function of spring and magnet characteristics, air-core meter calibration is only affected by the mechanical alignment of the drive coils. Mechanical calibration, once set at manufacture, can not change. Making pointer position a linear function of some input is a matter of properly ratioing the drive to each coil. The H field contributed by each coil is a function of the applied current, and the current is a function of the coil voltage. Our desired result is to have 8 (pointer deflection, measured in degrees) proportional to an input voltage: Comparing [3] to [2] we see that if we allow HSINE to vary as the sine of IJ, and HCOSINE to vary as the cosine of IJ, we will generate a net H field whose direction is the same as 8. And since the axle assembly aligns itself with the net H field, the pointer will always pOint in the direction of IJ. THE LM1819 Included in the LM1819 is a function generator whose two outputs are designed ~o vary approximately as the sine and cosine of an input. A minimum drive of ± 20 rnA at ± 4V is available at pins 2 (sine) and 12 (cosine). The common side of each coil is returned to a 5.1 V zener diode reference and fed back to pin 1. 8=kVIN [1] where k is a constant of proportionality, with units of degrees/volt. The vector sum of each coils' H field must folloW the deflection angle 8. We know that the axle assembly always points in the direction of the vector sum of HSINE and HCOSINE. This direction (see Figure 4) is found from the formula: (8) = arctan { I HSINE I / I HCOSINE II Recalling some basic trigonometry, (8)=arctan(sin (IJ) / cos(8» HCOSINE +HSINE [2] [3] HSINE For the LM1819, k"'54°1V (from equation 1). The function generator input (pin 8) is internally connected to the Norton amplifier's output. VIN as considered in equation [1] is actually the difference of the voltages at pins 8 (Norton output! fUflction generator input) and 4. Typically the reference voltage at pin 4 is 2.1V. Therefore, 8=54(Va-2.1) [4] As Va varies from 2.1V to 7.75V, the function generator will drive the meter through the chip's rated 305° range. Air-core meters are mechanically zeroed during manufacture such that when only the cosine coil is driven, the pointer indicates zero degrees deflection. However, in some applications a slight trim or offset may be required. This is accomplished by sourcing or sinking a DC current of a few microamperes at pin 4. A Norton amplifier is available for conditioning various input signals and driving the function generator. A Norton amplifier was chosen since it makes a simple frequency to voltage converter. While the non-inverting input (pin 6) bias is at one diode drop above ground, the inverting input (5) rides on a 2.1V level, equal to the pin 4 reference. Mirror gain remains essentially flat to IMIRROR = 5 rnA. The Norton amplifier's output (8) is designed to source current into its load. To bypass the Norton amplifier simply ground the non-inverting input, tie the inverting input to the reference, and drive pin 8 (Norton output!function generator input) directly. HccSINE . - - - -......- -... TL/H/5263-4 FIGURE 4. The vector sum of HCOSINE and HSINE pOints In a direction 8 measured in a clockwise direction from HCOSINE' An NPN transistor is included on chip for buffering and squaring input signals. Its usefulness is exemplified in Figures 1 & 5 where an ignition pulse is converted to a rectangular wave form by an RC network and the transistor. The emitter is internally connected to ground. It is important not to allow the base to drop below -5Vdc, as damage may occur to the device. The 2.1V reference previously described is derived from an 8.5V regulator at pin 11. Pin 11 is used as a stable supply for collector loads, and currents of up to 5 rnA are easily accommodated. S 12-33 81 CD .CD .- :::IE ..J r-~~------------------------------------------------------------------------------~----- Application Hints (Continued) TACHOMETER ApPLICATION A measure of the operating level of any motor or engine is the rotational velocity of its output shaft. In the case of an automotive engine the crankshaft speed is measured using the units "revolutions per minute" (RPM). It is possible to indirectly measure the speed of the crankshaft by using the signal present on the engine's ignition coil. The fundamental frequency of this signal is a function of engine speed and the number of cylinders and is calculated (for a four-stroke engine) from the formula: f=nCII/120 (Hz) (!) The charge pump circuit in Figure 7 can be operated in two modes: constant input pulse width (Cl acts as a coupling capacitor) and constant input duty cycle (Cl acts as a differentiating capacitor). The transfer functions for these two modes are quite diverse. However: deflection is always directly proportional to R2 and ripple is proportional to C2. , The following variables are used in the calculation of meter deflection: description number of cylinders symbol n where n = number of cylinders, and CII = rotational velocity of the crankshaft in RPM. From this formula the maximum frequency normally expected (for an 8 cylinder engine turning, 4500RPM) is 300 Hz. In certain specialized ignition systems (motorcycles and some automobiles) where the coil waveform is operated at twice this frequency (f = nCII/60). These systems are identified by the fact that multiple coils are used in lieu of a single coil and distributor. Also, the coils have two outputs instead of one. CII, CIIIDLE engine speed at redline and idle, RPM 9 pOinter deflection at redline, degrees 8 charge pump input pulse width, seconds VIN b.() ,peak to peak input VOltages, volts maximum desired ripple, degrees k function generator gain, degees/volt f, flDLE input frequency at redline and idle, Hz Where the NPN transistor and regulator are used to create a pulse VIN=8.5V. Acceptable ripple ranges from 3 to 10 degrees (a typical pOinter is about 3 degrees wide) depending' on meter damping and the input frequency. The constant pulse width circuit, is designed using the follOwing equations: A typical automotive tachometer application is shown in Figure 1. The coil waveform is filtered, squared and limited by the RC network and NPN transistor. The frequency of the pulse train at pin 9 is converted to a proportional voltage by the Norton amplifier'S charge pump configuration. The ignition circuit shown in Figure 5 is typical of automotive systems. The switching element "5" is opened and closed in synchronism with engine rotation. When "5" is closed, energy is stored in Lp. When opened, the current in Lp diverts from "5" into C. The high voltage produced in Ls when "5" is opened is responsible for the arcing at the spark plug. The coil voltage (see Figure 6) can be used as an input to the LM1819 tachometer circuit. This waveform is essentially constant duty cycle. 04 rectifies this waveform thereby preventing negative voltages from reaching the chip. C4 and R5 form a low pass filter which attenuates the high frequency ringing, and R7 limits the input current to about 2.5mA. R6 acts as a base bleed to shut the transistor OFF when "5" is closed. The collector is pulled up to the internal regulator by RAEG. The output at pin 9 is a clean rectangular pulse. (1) 100 j.LA< ~~<3 mA (2) Cl~ 108 Rl (3) (4) R2=~ = 120R1 9 VIN8kf VIN'l/CII8k 1 1 R2A9flDLE R2A9'1/CIIIDLE The constant duty cycle equations are as follows: C2 RAEG ~ 3 kn Many ignition systems use magnetic, hall effect or optical sensors to trigger a solid state switching element at "5." , These systems (see the LM1815) typically generate pulses of constant width and amplitude suitable for driving the charge pump directly. Rl ~ VINX104 -RAEG Cl ~ 8/10(RAEG+Rl) Rz = 9/3.54nCllCl=91425fCl C2 = 425Cl/A9 The values in Figure 1 were calculated with n = 4, c.l = 6000RPM, 9 = 270 degrees, 8= 1 ms, VIN=VAEG=8.5V and A9=3 degrees in the constant duty cycle mode. For distributorless ignitions these same equations will apply if nc.l/60 is substituted for F. 512-34 ----------------------------------------------------~r .... .... co i: co Equivalent Schematic " J iii J f~ "II! ~ ;-- J " ~ E II! ,..5 :! r-4h. TN:g i " il! J~ " ~i' ill " :;; J ~~ ~ f(' o S 12-35 .... CD .... ~ r-----------------------------------~---------------------------------------- ~ Typical Applications 11 REG lltieo OUTPUT TO CHARGE PUMP SPARK PLUG 04 H5 H7 LM1819 10 H& 7,14 TLlH/5263-9 FIGURE 5. Typical Pulse-Squaring Circuit for Automotive Tachometers. OPENED .J "s" CLOSED ."'N~ WAVEFORM L I ~ OY OUTPUT ~ B.5Y CHARGE PUMP OY--' CZ L Cl -I r-NHll-....... L TUH/S263-11 TL/H/5263-10 FIGURE 6. Waveforms Encountered In Automotive Tachometer Circuit. FIGURE 7. Tachometer Charge Pump. Voltage Driven Meter with Norton Amplifier Buffer Y+ =13.1Y NC NC NC Rz 120 lW HZ· 130K COSINE lN4733 Hl lOOk TUH/S263-S Deflect/on = S4 (YIN -. 7)R2/Rl (degrees) o to 30S· deflect/on Is obtained with .7 to SV input "Full scale deflection is adjusted by trimming R2. S 12-36 Typical Applications (Continued) Unbuffered Voltage Driven Meter y+ ~13.1V YIN Hz lZ0 lW COSINE TLlH/5263-6 Deflection = 54(VIN - 2.1) (degrees) oto 305" deflection is obtained for inputs of 2.1 to 7.75V. Full scale deflection is adjusted by trimming the input voltage. Current Driven Meter v+ =13.1V HZ lZ0 HZ· lW SDk COSINE Tl/H/5263-7 Deflection = 54R211N (degrees) Inputs of 0 to 100 ~A deflect lhe meter 0 to 270". ·Full scale deflection is adjusted by trimming R2. S 12-37 ...... o .-------------------------------------------------------------------------, CO ~ Typical Applications (Continued) Level Shifted Voltage Driven Meter v+ = 13.1V HZ 120 lW COSINE 1M 114 LM324 1M 1M Tl/H/5263-8 Deflection= 54VIN (degrees) Inputs 01 0 to S.65V deflect the meter through a range of 0 to 3OS'. Full scale deflection is adjusted by trimming the Input Yoltage. S 12-38 ~National ~ Semiconductor LM1823 Video IF Amplifier/PLL Detector System General Description Features The LM1823 is a complete video IF signal processing system on a chip. It contains a 5-stage gain-controlled IF amplifier, a PLL synchronous amplitude detector, self-contained gated AGC, and a switchable AFC detector. The increased flexibility of the LM 1823 makes it suitable for a wide variety of television applications where high quality video or sound carrier recovery is required. These include home receiver video IFs, cable and subscription TV decoders, and parallel sound IFlintercarrier detector systems. Typical operating frequencies are 38.9 MHz, 45.75 MHz, 58.75 MHz, and 61.25 MHz. • • • • • • • • • • • • Low differential gain and phase IF and detector pin compatible with LM1822 Common-base IF inputs for SAW filters True synchronous video detector using PLL Excellent stability at high system gains Noise-averaged gated AGC system Uncommitted AGC comparator input Internal AGC gate generator Superior small-signal detector linearity AFC detector with adjustable output bias 9 MHz video bandwidth Reverse tuner AGC output Test Circuit Measure parameters at indicated test pOints V2B 12V 10' IFOU~'D1 3D. .--_+-ovn • V1o-..".,.'0il\'.--~_---, 12V 50 90 3 90 4 V3,V4o--'YVv-.....-¥>IY-+------I 180 1t2W 10k V23,V26 .J! H4""". . .--+~-'+--------' 10' V19,V20 10k V9O-W.,...----~..... 1m 1 6k 12V BO' 3D. 0 22 lDO. 6' '::' .. 12V T1 - 50n unbalto bal Mini·Circuits Lab TM01·1T Ll - 9 YzT} #22 wire Order Number LM1823N See NS Package N28B L2 - 4 YzT L3 • 6%T on 'A." form with HF core, shielded All caps in p.F unless noted S 12-39 TL/H/5222-1 &I Absolute Maximum Ratings Power Supply Voltage, V2 IF Supply Current, Is AGC Gate Voltage, V14 - Video Output Current, 116 PLL Filter Current, 118 Detector Input Signal, VDET Power Dissipation Thermal Resistance, (JJA Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temp. (Soldering, 10 seconds) 15V SOmA ±5V 10mA 5mA 1 Vrms 2W 50·C/W 125·C OOCto 70·C -65·C to + 150·C 265·C IDC Electrical Characteristics PARAMETERS GUARANTEED BY ELECTRICAL TESTING TA=25·C, Test Circuit, vIF=VDET=O, VPH=4V, VCOMP=4V, and all switches in position 0 (open) unless noted. Parameter Conditions Min Typ Max Units SO SO mA V 12V Supply Current, 11 + 12 VAGc=6.7V. VCOMP=6V IF Regulator Voltage, V5 VAGC = 6.7V, SW4 Position.1 5.S 6.4 7.0 IF Input Voltage, V7, VS VAGc=2V, SW 2, 3, 4 Position 1 3.2 3.7 4.1 V IF Decouple Offset, V6-V9 VAGC= 2V, SW 2,3,4 Position 1 0 ±30 mV IF Peaker Voltage (Max Gain), V3, V4 VAGC = 2V, SW 2, 3, 4 Position 1 2.3 3.0 3.6 V IF Output Current, 11 VAGC=9V, SW 2,3,4 Position 1, Measure V1,I1 = (12-V1)/50 3.1 5.5 7.8 mA IF Peaker Voltage (Min Gain), V3, V4 VAGC= 9V, SW 2,3,4 Position 1 5.5 6.2 Detector Input Voltage, V28 VAGc=6.7V, SW 1, 4 Position 1 4.3 4.9 5.5 V V 35 V Limiter Tank Voltage, V24, V25 VAGc=6.7V, SW 1, 4 Position 1 6.4 7.0 7.6 AFC Tank Voltage, V23, V26 VAGC=6.7V, SW 1, 4 Position 1 4.3 4.9 5.5 V VCO Tank Voltage, V19, V20 VAGC=6.7V, SW 1, 4 Position 1 4.7 5.2 5.7 V AGC Sync Threshold, V17 SW 1, 2 Position 1, Adjust VCOMP for 113=0 3.S 4.0 4.2 V AGC Filter Leakage Current,I13 SW 1, 2, 4 Position 1 0 ±5 /LA AGC Filter Charge Current, 113 SW 1, 2 Position 1, VCOMP=3.5V 1.6 2.2 2.S mA AGC Filter Discharge Current,I13 SW 1, 2 Position 1, VCOMP=4.5V -0.45 -0.70 -0.90 mA RF AGC Leakage current, 111 VAGC = 2V, All Switches Position 1, Measure V11, 111 = (12-V11 )/6000 20 /LA RF AGC Output Current, 111 VAGC = 10V, All Switches Position 1, Measure V11,I11 =(12-V11)/6000 - S 12-40 0 1.5 1.S \ .mA Detector AC Set-Up Procedure SW 1,4 position 1, VAGC=OV 1. Apply VDET=10 mVrms, 45.75 MHzCWatthe detector input. Tune L1 for maximum AC signal at pin 25, measured with a 10x FET probe or through a 1 pF capacitor to prevent loading of the limiter tank. 2. Increase VDET to 60 mVrms. Adjust L3 until the PLL locks, as indicated by a DC voltage at the video output pin 18. 3. With the detector locked, adjust L3 for 4.0V at pin 18. 4. Adjust VPH for maximum detector efficiency by monitoring pin 16 for a minimum DC voltage. 5. Adjust L2 for 3.0V at pin 27 (on sensitive slope of AFC curve). AC Electrical Characteristics PARAMETERS GUARANTEED BY ELECTRICAL TESTING TA = 25'C. Test Circuit, detector set-up as above, f = 45.75 MHz, VAGC = 6.7V, VCOMP = 4V. and all switches in position 0 (open) unless noted. Min Typ IF Amplifier Gain. vOUT!vIF (Note 1) VAGc=2V, SW 2,3,4 Position 1, VIF= 500 p.Vrms 25 35 VAGC for 15 dB Gain Reduction SW 2,3,4 Position 1. VIF=2.8 mVrms. Adjust VAGC for Same VOUT as Gain Test 4.2 4.6 5.0 V VAGC for 45 dB Gain Reduction SW 2, 3, 4 Position 1, vlF = 89 mVrms, Adjust VAGC for Same VOUT as Gain Test 5.1 5.5 6.1 V Zero Carrier Level, V16 SW 1, 2, 4 Position 1, VDET=O 6.8 7.6 8.4 V Detected Output Level, fl. V16 SW 1, 2, 4 Position 1, VDET= 60 mlVrms. Measure Change in V16 from Zero Carrier Test 2 3 4 V 2 3 V 2.8 3.0 3.2 V 0.5 1.0 V Parameter Conditions Overload Output Voltage, V16 SW 1, 2, 4 Position 1, vDET= 600 mVrms AFC Output Voltage (OFF), V27 SW 1, 2, 4 Position 1, vDET=O AFC Minimum Output Voltage, V27 SW 1, 4 Position 1, VDET=60 mVrms, 46.75 MHz AFC Maximum Output Voltage, V27 . SW 1, 4 Position 1, vDET=60 mVrms, 44.75 MHz PLL Pull-In Range, fl.f 9 10 Max Units dB V MHz SW 1,4 Position 1, vDET=60 mVrms, 3 2 Vary Frequency and Measure the Difference between Lock Points Note 1: The IF ampfifler gain Is specified with the IF output connected to a 50n measurement system which results In a 25n loaded Impedance. The gain In an actual application will typically be 26 dB higher. S 12-41 ~ r-----------------------------------------------------------------~---------- N ,.... CD :5 Design Parameters NOT TESTED OR GUARANTEED Typical Application Circuit Parameter , Typ Maximum System Operating Frequency IF Input Impedance (Differential Pin 7-8), 45 MHz IF Output Impedanc~, 45 MHz IF Gain Control Range Detector Input Impedance, 45 MHz Detector Output Bandwidth, -3 dB Detector Differential Gain (Note 2) Detector Differential Phas,e (Not~ 2) Detector Output Harmonic Levels below 3 Vp-p Video VCO'Temperature Coefficient Note: 2: Differential gain and phase measured with the lim~er Units 70 60 10 55 3 MHz 9 MHz 2 1 -40 -150 deg dB ppm/DC 0 kO dB kO % tank adiusted for minimum differential phase. Typical Application 45.75 MHz (see Applicaiion Notes) 1IV 0.001 31111 • 430 AFC OUTPUT 10k '=' 2' 680 ,IF AMPUFIER LZ '~AFC ON/OFF 0.12/1" IF INPUT llV 60k 15k Am: DElAY~~:-------~~L ADJUST 20k v 1511 TLlH/5222~2 SAW Filter - MuRata SAF45MC/MA Ll - 9 V2T} #22 wire L2 - 4%T on 3.16" form with L3 - 6%T HF core. shielded All caps In ,.F unless noted 512-42 -----------------------------------------------------------------------------, r i!: .... Application Notes Refer to Typical Application Circuit COMMENTS ON RF Coupling The LM1823 is a high gain RF system which is critically dependent on the ground plane and positioning of the external components. For this reason, it is suggested that the printed circuit layo!!t shown in Figure 3 be strictly adhered to. The most sensitive pOints in the system to unwanted RF coupling are the IF input pins 6-9. There are two different signals which can cause different problems when coupling into the IF inputs. If the IF output is coupling to the input, it can cause bandpass tilting, peaking, and in extreme cases, oscillation. The other signal which can couple to the IF inputs is the PLL detector VCO. This VCO coupling can cause AFC skewing, non-symmetrical detector pull-in, and failure of the detector to acquire lock at weak signal levels. These input coupling problems will be most acute at maximum gain and will decrease as the IF is gain reduced by AGC action. The differential IF inputs offer a large amount of inherent rejection to unwanted RF coupling. Therefore, A FULLY BALANCED INpUT SOURCE IS MANDATORY. The input leads must be routed together and socketless operation is recommended above 50 MHz. However, residual coupling may still dictate the maximum IF amplifier gain which can be taken (see Pin Descriptions). PIN DESCRIPTIONS Pin 1-IF Amplifier Output: Pin 1 is connected to an opencollector NPN device. The load on pin 1 must be returned to the 12V supply as close as possible to pin 2. The IF output load may be either resistive as shown in the Typical Application, or an LC tank. The tank need only be used if a tunable bandpass characteristic is desired, or in conjunction with a sound trap. Pin 2-12V Supply: The LM1823 requires a nominal 12V supply but can accept a ± 10% variation. Pin 2 must be RF decoupled to a good ground as close as possible to the IC. Pins 3, 4-IF Gain Adjustment: Pins 3 and 4 are connected to the two emitters of the 4th IF differential amplifier such that the gain of the stage is set by the impedance between the pins. There is an internal 13600 resistor to set the minimum gain when the pins are left open. Adding an external resistor increases the gain by the ratio of the parallel impedance to the original 13600. The pin 3 to 4 external resistor primarily affects the maximum IF gain; the relative gain increase goes away over the first 20 dB of AGC. Pin 5-IF Supply: The IF supply employs an internal 6.4V shunt regulator which is fed by an external dropping resistor from pin 2 to pili 5. RF decoupling from pin 5 to the pin 10 ground plane is critical. Pins 6-9-IF Input and Decouple Pins: The LM1823 uses a common-base differential input stage as shown in Figure 1. Pins 7 and 8 connect directly to the emitters of the input devices,. while pins 6 and 9 decouple the DC feedback loop at the bases. The gain of a common-base amplifier depends inversely on the source impedance. The LM1823 is designed to operate from differential impedances in the 5000. to 20000 range, which is typical for surface acoustic wave (SAW) filters. Alternatively, the IF may be used with a transformer input configuration similar to that shown in the Test Circuit, as long as the required source impedance is maintained. In all cases a balanced source must be used. 01) , - - -....-JlJVv--6.2V N c.:I ~--.-.-JIJ\IIr-6.2V TLIH15222-3 FIGURE 1.IF Input Stage Both the input network to pins i and 8 and decoupling capacitor between pin 6 and pin 9 must be as close to the device as is physically possible to minimize RF coupling. Pin 10-IF Ground: Pin 10 grounds the IF and AGC circuits in the LM1823. It is separate from the detector and chip substrate grounds to prevent internal coupling. Pin 11-RF AGC Output: Pin 11 is connected to an opencollector NPN device. It begins to conduct current when the voltage on the AGC filter capacitor at pin 13 exceeds the voltage set at the takeover pin 12 by approximately 0.6V. When connected to a resistor to 12V, this produces a falling voltage at pin 11 suitable for reverse tuner AGC inputs. Pin 12-RF AGC Takeover Adjust: The voltage preset at pin 12 determines when the IF stops gain reducing and the ~un er begins gain reducing as the pin 13 AGC filter capacitor voltage increases with Signal level. A higher voltage at pin 12 delays the RF AGC takeover until more IF gain reduction has been taken (higher signal levels), while a lower voltage limits the IF gain reduction before RF takeover. When the LM1823 is being used without a tuner, pin 12 may be connected to supply. Pin 13-AGC Filter: Pin 13 is a push-pull current source output from the AGC comparator. The comparator compares the negative sync tips of noise-averaged pin 17 video with an internal 4V reference. Increases in signal produce a current out of pin 13 which charges the filter capaCitor, while decreases discharge the capaCitor. The resulting change in voltage at pin 13 controls the IF and tuner gains to maintain the pin 17 sync tip level at 4V. An optional capaCitor between pin 13 and the takeover pin 12 couples the ripple produced by a rapidly varying signal into the takeover pin to enhance the AGC loop response. Pin 14-AGC Gate Generator Time Constant: The AGC comparator is gated on during sync time by a pulse from an internal gate generator. The gate pulse which· activates the comparator is derived from the sync pulse in the same video which feeds the comparator input (see pin 17 description). An RC time constant on pin 14 determines the slice level on the leading edge of the sync pulse at which the comparator is gated on. This level is approximately VSLICE = 1/(2RC) in millivolts above the sync tip, and should be set at :0;;25% of the sync amplitude. Note that VSUCE only determines when the AGC comparator turns on, and is unrelated to the comparator reference. In the Typical Application, VSLICE= 100 mV, or 10% of a 1V sync pulse. Increasing VSLICE improves the AGC recovery from step changes in signal level but increases the risk of video interaction. When modifying the time constant, change the capacitor value only. S 12-43 • ~r-----------------------------------------------------~------- = C"I ~ Application Notes (Continued) Refer to Typical Application Circuit Pin 15-Supply Decouple: Pin 15 is an additional connection to the 12V supply to allow RF decoupling on the detector side of the chip. ' I Pin 16-Vldeo Output Pin 16 is a Darlington NPN emitterfollower output supplying negative sync video. With no detector input signal the pin 16 voltage sits at the zero carrier level, representing peak white. As the input signal level increases, the pin 16 voltage decreases towards black. The sync pulses are normally the most negative portion of the recovered video. Pin 22-Detector Phase Adjust The video detector requires a reference Signal in phase with the input signal carrier for maximum detection efficiency. However, the action of the PLL inherently sets the VCO phase in quadrature (at 90 degrees) with the limiter output Therefore a variable phase shift network, controlled by pin 22, is used internally between the veo and video detector to insure proper phasing. Pin 22 requires an adjustment voltage centered at y, supply with ± 2V of control range. The pin 22 adjustment procedure described in the Detector AC Set-Up Procedure is an open loop approach where the voltage is adjusted for maximum detected output with a fixed detector input signal. In the Typical Application, with the detector input being fed from the IF amplifier and the. AGC loop active, the pin 22 adjustment is made by maximizing the AGC filter voltage at pin 13. In all cases the detector phase adjustment must be performed after the limiter is tuned. 12V 18 10k 5k 17 lk lk6 16 - 15 VI~EO 15000 resistor. Increasing the Q (larger C) improves stability but reduces the veo control range. The tank shown in the Typical Application will yield a loaded Q of around 15, providing stable operation with a control range in excess of 2 MHz. Pin 21-8ubatrate Ground: Pin 21 grounds the chip substrate along with all of the AFC and PLL detector grounds. "":- OUTPUT 11.fHf5222-4 FIGURE 2. Adjustable Recovered Video Level Pin 17-AGC Comparator Input External negative sync video is fed to the AGC comparator and gate generator via pin 17. An internal low pass filter removes high frequency noise and transients. The peak-ta-peak video level with the AGC loop active is determined by the difference between the zero carrier level at pin 17 and the 4V sync tip level being held by the AGC comparator (see pin 13 description). Pins 23, 26-AFC Tank: A parallel LC tank between pins 23 and 26 sets the center of the AFC characteristic. The internal resistance is typically 20 kO, so that Q will be dominated by the coil Rp. The L1C ratio shown in the Typical Application maximizes Q to provide a steep AFC output slope. A quadrature input signal is required at the AFC tank to operate the AFC detector. This signal is derived by light capacitive coupling from the limiter tank. For applications at 45 MHz and above, the stray printed circuit capacitance from the adjacent limiter tank couples sufficient Signal for proper operation. However, at lower IF frequencies, small (1 pF-5 pF) capacitors may be required between the adjacent pins as shown in the Test Circuit. A second function of pins 23 and 26 allows turning the AFC detector OFF by grounding either side of the AFC tank. Up to 2 kO may be placed in series with the switch connection to prevent unbelancing the tank. When the LM1823 is being used to recover normal video, pin 17 may simply be returned to pin 16. This results in a nominal 3 Vp-p video level, but which is subject to vanations in the pin 16 zero carrier level. The network shown in RgUI'fJ 2 can be used to change the zero carrier at pin 17, thus providing an adjustable recovered video level. The pin 16 video level should be maintained at between 1 Vp-p minimum and 4 Vp-p maximum. In suppressed sync systems, the recovered video at pin 16 may require processing to restore normal sync amplitude before being fed to pin 17. In this case, It is mandatory that a DC path be maintained for the zero carrier level through any external circuitry. Any DC level shift between pins 16 and 17 will have the effect of changing the video level as previously described. Pin 18-PLL Filter: Pin 18 is connected to both the output of the phase detector and the control input of the veo. The polarity of the veo control characteristic is such that increasing the pin 18 voltage increases the veo frequency. An external resistive divider at pin 18 serves two functions. The divider parallel impedance sets the gain of the phase detector, while the divider ratio places the quiescent voltage at the center of the veo control characteristic. The 20 kO i~pedance, y, supply divider shown in the Typical Application has been chosen to provide optimum performance. The series capacitor and resistor to ground complete the PLl filter. An internal zener clamp to ground at pin 18 prevents the phase detector output from pulling the veo control input over 5.BV. For this reason, external voltages should not be forced at pin 18 to avoid damaging the clamp. Pins 19, 2O-VCO Tank: A parallel LC tank between pins 19 and 20 sets the veo center frequency. The tank Q is RpL/Xc, where RpL is the coil Rp loaded by an internal " Pins 24, 25-Llmlter Tank: A parallel LC tank between pins 24 and 25 forms the tuned load for a single stage limiting amplifier which strips amplitude information from the signals feeding the AFC and phase detectors. The amplifier has a small signal gain of approximately 50, with internal Schottky diodes across the tank to limit the output amplitude to 500 mVp-p. The linearity of the detector video outputs depends directly on limiter tuning. Making the limiter adjustment based on maximum signal level at pins 24, 25 as outlined in the Detector AC Set-Up Procedure results in nearly optimum output linearity. However, to completely null the output differential phase the limiter should be adjusted while monitoring this parameter. Pin 27-AFC Detector Output Pin 27 is push-pull current source output from the AFC detector. The polarity is such that pin 27 sources current when the input signal is below the center frequency, and sinks current above the center frequency. An external resistive divider sets both the gain and quiescent output voltage of the AFC. Although the net- S 12-44 ...... s:: ..... Application Notes (Continued) Refer to Typical Application Circuit CD I\) Co) work shown hthe Typical Application sets up the output at 1,4 supply, it could easily be changed to % supply by using equal-valued resistors. When setting up the AFC detector, the tank should always be tuned so the output is at the quiescent divider voltage with the desired center frequency applied. Pin 28-Detector Input: Pin 28 is internally DC-biased and requires an AC-coupled input signal. The network between pins 1 and 28 should not allow over 1 Vrms at the input during Signal transients to prevent overloading the detector. When a tank is being used for the IF output load, a capacitive divider may be used from pin 1 to pin 28 in which the series equivalent capacitance resonates with the coil. AfC AFC DEFEAT OUTPUT ! ~ 12V---..... ~\ .. ~ mc5~~ IF _ _ _ _/ - ' . INPUT VI EO OUTPUT AGC COMPARATOR INPUT TL/H/5222-5 FIGURE 3. Printed Circuit Layout (Component Side). S 12-45 ~ CD CD .----------------------------------------------------------------------------, .... ~National ::E ..J PRELIMINARY ~ Semiconductor LM 1863 AM Radio System for Electronically Tuned Radios General Description The LM1863 is a high performance AM radio system intended primarily for electronically tuned radios. Important to this application is an on-chip stop detector circuit which allows for a user adjustable signal level threshold and center frequency stop window. The Ie uses a low phase noise, levelcontrolled local oscillator. Low phase noise is important for AM stereo which detects phase noise as noise in the L-R channel. A buffered output for the local oscillator allows the Ie to directly drive a phase locked loop synthesizer. The Ie uses a RF AGe detector to gain reduce an external RF stage thereby preventing overload by strong signals. An improved noise floor and lower THO are achieved through gain reduction of the IF stage. Fast AGe settling time, which is important for accurate stop detection, and excellent THO performance are achieved with the use of a two pole AGe system. Low tweet radiation and sufficient gain are provided to allow the Ie to also be used in conjunction with a loopstick antenna. Features • • • • • • • • • • Low supply current Level-controlled, low phase noise local oscillator Buffered local oscillator output Stop circuitry with adjustable stop threshold and adjustable stop window Open collector stop output Excellent THO and stop time performance Large amount of recovered audio RF AGe with open collector output' Meter output Compatible with AM stereo Block Diagram ¥R.. TOV· TUNING VOLTAGE t Hl~ L.o.I ,hl RF INPUT 1.-_ _" MIXER TANX 16 IF IF INPUT OUTPUT 10 12 IN 1B L-_-+____+11:...o ~~OUPLE L---+--+-;.:::""O'""""N.....+AUDID 17 BUFfERED L.O. OUT T TO SyNTltESIZEft (HI TO STOp) TO SYNTHESIZER I LDDIC SUPPLY TL/H/5185-1 Order Number LM1863N See NS Package Number N18A S 12-46 Absolute Maximum Ratings Supply Voltage Operating Temperature Range 16V Package Dissipation (Note 1) 1.89W Storage Temperature Range - 55·C to + 150·C O·Cto +70·C Lead Temperature (Soldering, 10 seconds) 300·C Electrical Characteristics (Test Circuit, TA = 25·C, V+ = 12V, SW1 = Parameter Position 1, SW2 = Position 2, unless indicated otherwise) Conditions Min Typ Max Units 8.3 10 mA 16 V STATIC CHARACTERISTICS Supply Current VIN = OmV Pin 14, Regulator Voltage Operating Voltage Range (See Note 2) Pin 3 Leakage Current VIN Pin 8, Low Output Voltage VIN Pin 15, Output Voltage VIN = = = = 7 OmV 0.1 /LA OmV .15 V OmV 0 V Maximum Sensitivity = 1 MHz, M = 0.3) VIN For VAUDIO = 6 mVrms 7.5 20 dB Quieting Sensitivity VIN for 20 dB SIN in Audio 15 Maximum Signal to Noise Ratio VIN Total Harmonic Distortion VIN Total Harmonic Distortion VIN Audio Output Level VIN Overload Distortion VIN Meter Output Voltage VIN Meter Output Voltage VIN Local Oscillator Output Level on Pin 17 (See Note 3), SW1 = Position 1 Local Oscillator Output Level on Pin 17 (See Note 3), SW1 = Position 2 Stop Detector Valid Station Frequency Window VIN = 10 mV, difference between the two frequencies at which Pin 8 < W, SW2 = Position 1 DYNAMIC CHARACTERISTICS: (fMOD Stop Detector Valid Station Signal Level Threshold V 5.6 1 kHz, fiN = = = = = = = 40 10mV = 0.8 80 10mV 50 mV, M 54 = % .63 2 % 120 160 mVrms 7.5 0.8 /LV dB .26 10mV 10 mV, M /LV 30 % 100 /LV 0.5 V 10mV 4.6 V 147 mVrms 100 125 mVrms I Find VIN for which Pin 8 > 1V RF AGC ThreslJold Find VIN that produces 10 /LA of current into Pin 3 Pin 3 Low Output Level VIN Pin 8 Leakage Current VIN Pin 15 Output Resistance VIN = = = 2.5 4 5.5 kHz 7 16 40 /LVrms 3 6 10 mVrms 30mV 0.1 V 30mV 0.1 /LA 10mV 825 .0 Note 1: Above TA ~ 25'C derate based on TJ(MAX) ~ 150'C and 8jA ~ 66"C/W. Note 2: All data sheet specifications are for V + ~ 12V and may change Slightly with supply. Note 3: The local oscillator level at Pin 17 is identical to the level at Pin 16 since Pin 17 is an emitter follower off of Pin 16. S 12-47 • C") CD ~.. Test Circuit :iii .... TOKO 7NRES·A5627AAG ,-----, I I I I I I I I J t----'W_t-..... 3 lk3 12 13 AUDIO 18 MIXER IN IF OUT IF DECOUPLE 11 10 IF INPUT STOP OUT MIXER OUT .0 820 47k y+ O.1tb 100 4k7 y+ TLlH/5185-2 Typical Performance Characteristics (From Test Circuit) , i§ .~ is 10 I I I '" AUDI~ _2 !~-1D .... M = ft -20 52 If' => ~ s§-3Q "'CO: ~ffi -40 coiffi ;; i; -5D a::fi3 I e. - lruriT- THD+NOISE J 11, ....... ". ~ NDlS~" .I I ii -60 !1l 1,,='0.3' I fMOO=l kHz ...... 1 pV 10 ~V 100 ~V 1 mV 10 mV 100 mV YIN -MIXER INPUT VOLTAGE (Vrms) RF AGC PIN 3 I ~ IrUNE=l MHz NO MODULATION I _I-IME~ER I SUPPLY CURRENT (mA) 'r ;;; :s I rlNt!I 'f" ~ f- -1 AUDIO OUTPUT' (dB) -2 TLlH/5185-10 -4 I -- M=0.3 fMOO=l kHz IrUNE=l MHz V,N=10 mVrm. -3 I \/tN-MIXER INPUT VOLTAGE (VIm.) 812-48 I 1 ~V 10 pV 100 ~V 1 mY 10 mY 100 mV TL/H/5185-9 ~ o 3 4 6 8 10 12 14 16 SUPPLY VOLTAGE (V) TL/H/51B5-11 LM1863: AM ETR Radio » 'a "2. & O· V· ::::J (") a' c f ;::;: ~D C6 ,~ .... 14 0' +I~ ,'~J .24 TINIO C27 KV1235Z o··~I v", I IF I AUDIO OUT In • DECDUPLE '" ~"A IF INPUT R22 '" -~ (Jl .19 ,Ok RJ '00' --'1M ... en ;J;'~ Ok DUMMY '" 'PF-"pF!t~o ~ ,'1" KV'23!Z e18 D.Ol".F C2& 0.... Rl. m. ~ rO"'~A~'!..""'!N1 I C16 ! :PF~' I ! I I L ______ JI &17 SlpF Y,,,, TL/H/51B5-B t98~W' ~ :s.... ~ r--------------------------------------------------------------------------------Performance Characteristics of Applications Circuit tV i n~-r~-+~rf~Cd OO~-r~-+~rf-r~ 50 ~ r- rf- f- NORMALIZED SYSTEM 30 SIN FOR 20 , ,GAIN ;\ VGEN=10pV 30 mY ~1~t:t!:t~~t:~~~~ 0.53 0.73 0.93 1.13 1.33 1.53 10 TL/H/5185-12 30Q mV !i - CROSS MODUlATION 530 kHz I--/---::'--~:::::::.j . . 10~~.?'" L . .--~. fol0kHZ 10 mY L ._ _ 1 mY 3 mY ~ _ _L-_----I 10 mY YGEN1 (VrIDS) 30 mY TLlH/5185-14 The following procedure was used to measure cross modulation: 1. Tune the radio to the center frequency of Interest and tune VGEN. to thts ssme frequency. measured using the following dummy an- 2. Set at 0 dB audio reference with VGEN. ~ 10 mV RMS and 30% AM mod; fMOD ~ 1 kHz_ tenna: TO GATE 3. Remove the modulation from VGEN1 and set the level of VOEN1' 4. Set the modulation level of VGEN2 ~ 80% at fMOO ~ 1 kHz and tune VGEN2 ± 40 kHz away from OFQl center frequency. "'];82 pF S. Increase the level of VGE~2 until -40 dB of audio Is recovered. The level of VGEN2 Is the cross modulatton measurement. . is Cross modulation ..L, VaEN2,~5. ].,1" r-pF TL/H/5185-15 Additional Performance Information: • THO for 80% modulation for fMOD = 1 kHZ at ;;;'~ -10 H--t--H-+-Hc-+--H 1\ i \ ~-~r;-+-r+-+-r;~,+-~ ~ VGEN~ tV is 0.5% VGEN~10 mV Is 0.4% • Tweet < 2% at all input levels. • Typical ti,,!e for valid stop indication < 50 ms. -30 t-HH-t-t-t-t-t-t-t -~~-+-r+-~~~~~ - 50 L-I-'--I-.l-.l-JL-...I.-'---'-..J 31 125 500 2k 8k 10k MOOUIATION FREQUENCY (Hz) TL/H/5185-16 Note: Tweet Is an audio tone produced by the 2nd and 3rd harmonic 01 the IF beating against the received signal. It Is measured as an equivalent modulation level: ie. 30% tweet has the same amplitude at the detector as a desired signal with 30% modulation. S 12-50 IC External Components (See Application Circuit) Component Typical Value C1 2.2J-tF Comments Sets dominant AGC pole, affects stop time and THO. C2 1 J-tF Sets non-dominant AGC pole, affects stop time and THO. C3 0.33 J-tF Stop level threshold decoupling, affects stop time and sensitivity of stop detector to large modulation peaks. C4 10 J-tF Supply decoupling, low frequency. C5 0.1 J-tF Supply decoupling, high frequency. C6 1 f'F C7 0.005J-tF IF decouple, affects IF gain. Audio output filter, removes IF ripple from detector. C8 10 J-tF Regulator decouple, low frequency. C9 Regulator decouple, high frequency. C10 0.1 J-tF 470pF C11 2J-tF C12 0.33 J-tF C14 0.1 J-tF C19 0.001 J-tF C26 0.005J-tF Sets gain at low end of AM band. C28 0.01 J-tF Couples RF stage output to mixer input, keep small to insure proper stop time performance when RF AGC is active. Pad capacitor for varactor, affects tracking. RF AGC decouple, affects stop time and THO. RF AGC high frequency decouple. Local oscillator output coupling. Sets gain at high end of AM band. ' R1 300k Pot. R2 12k Sets size of stop window. R3 50k Open collector pull up resistor. ' R4 1k3 IF filter termination, and gain set. R5 10k Sets RC time constant on audio outputs, smaller values may cause distortion of high frequencies. R6 200k Sets gain of IF stage, affects noise floor and , sensitivity. R7 Meter Oependent Sets full-scale deflection of meter. R8 100k . Sets gain and threshold of RF AGC. R9 1000 R19 10k R21 1.2MO Sets level stop threshold. Aids'mixer output decoupling. Sets 2'nd pole in RF AGC, affects THO for large input signals. Biases pin 5 to 0.4 volts which permits , shorter stop time. R24 8200 Sets system gain. 01, D2, 03, TaKa KV1235Zor Equivalent Varactor diodes. Resonator 450 kHz ± 1 kHz Murata', FX1599 IF filter Murata' CFU450F5 Parallel type resonator. Sets selectivity and tone response. "'Murata Corporation of America 1148 Franklin Rd. S. E. Marietta. GA, 30067, U.S.A. 404-952-9777 S 12-51 • ~ r----------------------------------------------------------------------------- :8 .... . Performance Characteristics of Applications Circuit (Continued) ! Part No. 5MFC-A087YRT TOKO Electronics Ltd. * , Part No. 7TRS-A561OCI TOK9 Electronics Ltd. r --------,I II I I II I T2 ANOT3 r------, .i Tl I I 03 . II I I 51 I 47T 1 I I L _______J I 180pF 6 II (BOTTOM VIEW) (BOTIOM VIEW) TLlH/5185-17 Qu> 95 at 1 MHz Part No. 7NRES-A5628EK TOKO Electronics Ltd. Part No. 7NRES-A5627AAG TOKO Electronics Ltd. 4-6 = 200 "H r-----' I I I I I II I TS' r~---~----41 I 11ST I I TLlH/5185-18 Cen1er Frequency = 2 MHz au> 60 at2 MHz T4 I I 9T I ______ 4 3 ...II L. l00PF=;:::. II II 2 3 I I IS4T 100pF I I I I _________ 6 I L. J I 2 I IL. ___ 1 .an, " (BOTTOM VIEW) I __ .JI 28T ~ (BOnuM VIEW) TLlH/5185-19 Center Frequency = 460 kHz au> 100 at 450 kHz Center Frequency = 450 kHz au> 100 at 450 kHz Part No. 7TRS-A5609AO TOKO Electronics Ltd. r------, I I T6 I I 3 4 I I I 20 I I I I I I I IL 1_______6..JI (8OTTOM VIEW) TL/H/5185-21 Center Frequency = 1 MHz au> 95atlMHz L,-3 = 110 "H 'Toko America Inc. 6520 West Toully Ave. Skokie, Illinois, 60077, U.S.A. 312-&77-3840 S 12·52 TLlH/5185-20 Layout Considerations Although the pinout of the LM1863 has been chosen to minimize layout problems, some care is required to insure proper performance. If the LM1863 is used with a loopstick antenna, care in the placement of C3 must be observed in order to minimize tweet radiation. Orient C3 parallel to the axis of the loopstick and as far away as possible. Keep C3 close to the IC. The ground on C6 should be located near the ground terminal of the 450 kHz ceramic filter. C11 should be located near Q2 and C12 should be located near the IC. Also, the resonator on Pin 7 and resistor R2 should be located near the IC in order to minimize tweet radiation. The mixer output, Pin 9 and the IF input, Pin 10, traces should be as short as possible to prevent stray pick up from the resonator. Applications Information (See typical application and LM1863 schematic diagram.) STOP DETECTOR There are two criteria that determine when an electronically tuned radio is tuned to a valid station. The first criterion is that the incoming signal be of sufficient strength to be listenable. The second criterion requires that the radio be tuned to the center frequency of the incoming station. Both the signal strength threshold and the center tune window are externally adjustable. The signal strength threshold is set by resistor R1. Increasing the value of this resistor will reduce the signal level threshold. There is no difficulty in setting the signal strength threshold, either above or below the AGC threshold. Resistor R2 sets the center tune window. The incoming station is considered to be center tuned whenever the frequency of the signal at the IF output falls within the center tune window. Increasing the value of R2 will narrow the window, while decreasing R2 will widen the window. Since there is some interaction between R2 and R1, R2 should be chosen before R1. In the United States, stations within the AM band are spaced no closer than 10 kHz apart. Consequently, the controller should be set up to stop every 10kHz within the AM band when the ETR is in scan mode. A center tune window anywhere less than ± 10 kHz is therefore adequate in determining the center tune condition, though a narrower stop window is desirable in order to minimize the chance .that side bands from a strong adjacent channel will fall within the stop window. Because of asymmetry in the resonator amplitude characteristic, the center tune stop window will not be symmetric PC Layout (Component Side) TL/H/S185-22 S 12-53 Applications Information (Continued) about the center frequency of the resonator. This is not a problem as long as the stop window brackets the center frequency of the IF and does not extend into the next channel. However, in order to avoid any problems in this regard it is recommended that the resonator center frequency deviate no more than ± 1 kHz from the center frequency of the IF. The stop output, Pin 8, is an open collector NPN transistor. This output must be taken to a positive voltage through a load resistor, R3. A valid stop condition is indicated by a high output level on Pin 8 (i.e., the NPN is turned off). The voltage on this pin should not exceed 16 volts. STOP DETECTOR STOP TIME The amount of time required for the LM1863 to output an accurate stop indication on Pin 8 is defined as the stop time. The stop time determines how quickly the ETR can scan across the AM band. There are several factors that influence the stop time. Since the signal level stop function operates in conjunction with the Automatic Gain Control (AGC), the AGC settling time is a critical factor. This settling time is dominated by the low frequency AGC pole which is set by C1 and internal IC resistances. Decreasing C1 will decrease the AGC settling time but increase total harmonic distortion, THO, of the recovered audio. A good compromise between AGC settling time and THO is very difficult to reach with a Single pole AGC system. Consequently"the LM1863 has been designed with a second, higher frequency, AGC pole. This non-dominant pole is externally set by capacitor C2. As a result, C1 can be made much smaller than it otherwise could for an equivalent amount of THO. Reducing C1 will reduce the stop time. The combination of C1 and C2 as shown In the applications circuit results in a stop time of less than 50 ms for most input conditions, while at the same time the circuit achieves .9% THO at 80% modulation with 400 Hz modulation frequency at 10 mV input signal strength. Had C2 not been present the stop time would still be 50 ms but the THO for similar input conditions would be 8%. By decreasing both C1 and C2 (keeping the ratio of C1/C2 constant) the stop time can be reduced at the expense of THO, while the converse is also true. The addition of a second pole to the AGC response does add some ringing to the AGC voltage following signal transients. The frequency, duration and amount of ringing are dependent on where both AGC poles are placed and to some extent the input signal conditions. The amount of ringing should be kept to a minimum in order to insure proper stop indications. The amount of ringing can be reduced by either reducing C2 (thiS will increase THO) or by increasing C1 (thiS will improve THO but increase stop time). If the ratio of C1/C2 is made too small, an increase in low frequency noise may be noticed resulting from the peaking that a closed loop two pole system exhibits near the unity gain frequency. The extent of this peaking can be observed by examining the amount of recovered audio at various low frequency modulations. In general, the values shown reach a good compromise between THO, stop time, ringing and low frequency noise. The center tuning detector on the LM1863 passes the signal at the IF output through a limiting amplifier which removes most of the modulation from the IF waveform. The output of this limiter is then applied to the resonator on Pin 7. Unfortunately, large modulation peaks are not completely removed by the limiting amplifier. Without C3, these large modulation peaks would cause glitches on the stop output when the LM1863 was tuned to a valid station. C3 acts to reduce these glitches by filtering the output of the center tune circuit. C3, however, also affects the stop time and cannot be made arbitrarily large. A time constant of about 30 ms on Pin 5 gives the best compromise. R21 biases Pin 5 to about .4 volts, which is below the stop threshold at this point. This biasing results in a shorter stop time. Extra precaution can be taken within the software of the controller IC to further insure accurate stop detector performance over a wide variety. of input Signal conditions. A typical controller IC stop algorithm is as follows: The controller waits the first 10 ms after the LM1863 is tuned to the next channel. The controller then samples the LM1863 stop output 10 times within the next 40 ms. If no high output is sensed within that time the controller concludes there is no valid station at the frequency and moves to the next channel. If, however, at least one high output is detected within the first 50 ms the controller waits an additional 200 ms and at the end of that time re-samples the stop output in order to make its final stop determination. RFAGC The RF AGC detector is designed to control the gain of an external RF amplifier which is placed between the antenna and the mixer input. Th~ RF AGC operates by detecting when the input signal to the mixer reaches 6 mVrms, the RF AGC threshold. When the mixer input signal reaches this level the RF AGC is activated and will hold the mixer input level relatively constant at the level of the RF AGC threshold. The gain of the, RF AGC determines how constant the RF AGC can control the RF output. The LM1863 RF AGC is high gain and consequently the RF AGC output, Pin 3, will transition from high to low over a very narrow input range to the mixer when the LM1863 is examined in an OPEN LOOP condition. However, in a radio where the RF AGC controls the RF gain, a CLOSED LOOP negative feedback system is established. In this application the RF AGC output will transition from high to low over a large range of signal levels to the input of the RF stage. The RF AGC threshold has been carefully chosen to pre-' vent overloading the mixer, which would cause distortion and tweet problems. However, the threshold level is suffiCiently large to minimize the possibility of strong adjacent stations de-sensitizing the radio by activating the RF AGC and thereby gain reducing the RF front end. The RF AGC output, Pin 3, is an open collector NPN transistor. This collector must be tied to a positive voltage through a load resistor, R8. Furthermore, decoupling is required (C11 and C12) in order to insure that the RF AGC does not induce significant distortion in the recovered audio. However, the tradeoff between good THO performance and fast stop time is not too severe for the RF AGC because large changes in the RF AGC level are unlikely when moving between adjacent channels. This is because the selectivity in the RF stage is not great enough to cause abrupt Signal level changes at the mixer input as the radio is tuned. Thus, since the RF AGC does not have to follow abrupt signal level changes, the time constant on the AGC output can be relatively long which allows for good THO performance. C12 is required in order to insure good RF decoupling of signals at the RF AGC output, and sets the non-dominant pole. The RF AGe 10 pA threshold is fixed at 6 mVrms at the mixer input. However, due to the gain of the RF stage and S 12-54 Applications Information (Continued) losses through the RF transformers, this level may be different when referenced to the antenna input. For the application circuit shown the RF threshold occurs at 2 mVrms at the dummy antenna input. Thus, the RF AGC threshold can effectively be adjusted by altering the gain of the RF stage. The value of R8 also has some affect on the RF AGC threshold of the application circuit. Smaller values will tend to increase the threshold while larger values will tend to reduce the threshold. GAIN DISTRIBUTION The purpose of this section is to clarify some of the tradeoffs involved in redistributing gain from one portion of the radio to another. An AM radio basically has three gain blocks consisting of the RF stage, the mixer, and the IF stage. The total gain of these three blocks must be sufficiently large as to insure reception of weak stations. Given then a fixed amount of required gain how does distributing this gain among the three blocks affect the radio perform' ance? Large amounts of gain in the RF stage will have the effect of depreasing the RF AGC threshold. A decreased RF AGC threshold means that it is more likely that strong adjacent stations can activate the RF AGC and desensitize the radio. Also,. a lot of RF gain implies large signals across the RF varactor diodes, which is undesirable for good tracking and can result in overloading these varactors which can cause cross modulation. On the other hand, high !'IF gain insures good noise performance and improved THO. High mixer gain implies large signal swings at the mixer output, especially on AGC transients. These large signal swings could cause the mixer ouput transistors to saturate and also could overload the IF stage. On the other hand, redistributing the gain from the IF to the mixer would improve the noise performance of the radio. The gain of the mixer can be controlled moving the tap on the mixer output transformer, T4. Since the output signal level of the IF is held constant by the AGC, increasing gain in the IF has the effect of reducing the signal level at the IF input. Noise sources at the IF input therefore become a larger percentage of the IF input signal thereby degrading the SIN floor of the radio. For this reason, the LM1863 employs 20 dB of IF AGC. The IF gain of the LM1863 is adjustable by changing the tap across the IF ouput coil, or by changing the ratio of R24 to R4. The gain distribution for the application circuit is as follows: V'1 Gain Distribution Vo 15PF 50 TL/H/5185-23 vG = OdB Vl = -16dB V2 = +10dB va = +33dB Vo = +84dB (10,.V) (Pin 18) (Pin 10) (Pi~12) The IF gain could also be varied by changing the value of R6 across the IF output coil. However, it is a good idea to maintain a high 0 IF tank in order to achieve good adjacent channel rejection. In order to prevent distortion due to overloading the IF amplifier, it is important that the impedance Pin 12 sees looking into the IF output tank, T5, does not go below 3K ohms. The above gain distribution is prior to any AGC action in the radio. This distribution represents a good compromise between the various tradeofts outlined previously. LEVEL CONTROLLED LOCAL OSCILLATOR Tracking of the RF varactors with the local oscillator varactor is a serious consideration in order to insure adequate performance of the ETR radio. Due to non-linear capacitance versus voltage characteristic of the varactor, large signals across these varactors will tend to modulate their capaCitance and cause tracking problems. This problem is compounded further if the level of the signals across the varactors change. In an AM radio, the local oscillator frequency changes a ratio of two to one. The 0 of the oscillator tank remains fairly constant over this range. Thus, since = Rpl (t)L = Constant, this implies that Rp(Rp ;", unloaded parallel resistance of the tank) must change two to one. The internal level-control loop prevents the two to one change in AC voltage across the tank which the change in the Rp would otherwise cause. Phase jitter of the local oscillator is very important in regard to AM stereo, where L-R information is contained in the phase of the carrier. Local oscillator jitter has the effect of modulating the L-R channel with phase noise, thus degrading the stereo signal to noise performance. Great care has been taken in the design of the LM1863 local oscillator to insure that phase jitter is a minimum. In fact the dominant source of phase jitter is the high impedance resistor drive to the varactor. The thermal noise of the resistor modulates the varactor voltage, thus causing phase jitter. o VARACTOR TUNED RF STAGE Electronically tuned car radios require the use of a tuned RF stage prior to the mixer. Many of the performance characteristics of the radio are determined by the deSign of this stage. Generally speaking it is very difficult to design an integrated RF stage in bipolar, as bipolar transistors do not have good overload characteristics. Thus, the RF stage is usually designed using discrete components. Because of this there is a great deal of concern with minimizing the number of discrete components without severely sacrificing performance. The applications circuit RF stage does just this. The circuit consists of only two active devices, an N-channel JFET, 01, which is connected in a cascode type of configuration with an NPN BJT, 02. Both 01 and 02 are varactor tuned gain stages. 02 also serves to gain reduce 01 when 02's base is pulled low by the RF AGC circuit on the LM1863. The gain reduction occurs because 01 is driven into a low gain resistive region as its drain voltage is reduced. R10 and C15 set the gain of the 1'st RF stage which is kept high (about 19 dB) for good low signal, signal/noise performance. The gain of the front end to the mixer input referenced to the generator output is about + 10 dB. T2 in conjunction with 01, C21 an~ C26 form the 1'st tuned circuit. C26 does not completely de-couple the RF Signal at the cathode of the varactor. In fact, the compination of C26 and C19 act to keep the gain of the whole RF stage constant over the entire AM band. Without special care in this regard the gain variation could be as high as 14 dB.This gain S 12-55 • r---------------------------------------------------------------------------------- = ~ ~ ..,... Applications Information (Continued) variation would result from the increase in impedance at the secondary's of T2 and T1 as the tuned frequency is increased. The increased impedance results from Ii constant 0= Rp/(wL) of the tanks over the AM band. With C26 and C19 the gain is held constant to within 6 dB (including the tr~cking error) over the entire AM band. C27 de-couples RF signal from the top of T2's primary and allows 02 to operate properly. C18 is a coupling capacitor which in conjunction with C19 couples the signal from the 1'st RF stage to the 2'nd RF stage. R20 acts to isolate this signal from AC ground at C11. R19 acts in conjunction with C12 to set a high frequency (ie: non-domiriant) RF AGC pole'which is important for low distortion when the RF AGC is aGtive. The dominant RF AGC pole is set by R8 and C11. 02 is a high beta transistor allowing for little voltage drop across R20 and R8 due to base current. This keeps 1he emitter of 02 sufficiently high On the absence of RF AGC) to bias 01 in its square law region. R13 acts to reduce the 2'nd stage gain and increase 02's signal handling. R13 must not get too large, however, (ie: R13> 100 0), or low level signal/noise will be degraded. T3 in conjunction wittl C20, C27 and 02 form the 2'nd RF tuned circuit. The output of 02 is capacitively coupled through C28 to the mixer input. The output of'02 is loaded not only by the reflected secondary impedance but also by R22. R22 is carefully chosen to load the 2'nd stage tuned circuit and broaden its bandwidth. The increased bandwidth of the 2'nd stage greatly improves the cross modulation performance of the front end. In the absence of this increased bandwidth, the relatively large AC signals across varactor 02 result in cross modulation. R22 also reduces the total gain of the 2'nd stage. R22 does slightly degrade (by about 6 dB) the image rejection especially at the high end of the AM band. However, the image rejection of this front end is still excellent and 6 dB is a small price to pay for the greatly increased immunity to cross modulation. VARACTOR ALIGNMENT PROCEDURE The following is a procedure which will allow you to properly align the RF and local oscillator trim capacitors and coUs to insure proper tracking across the AM band. 1. Set the voltage across the varactors = 1 volt. 2. Set the trimmers to 50%. 3. Adjust the oscillator coil until the local oscillator is at 9BO kHz. 4. Increase the varactor voltage until the local oscillator (LO) is at 20BO kHz and check to see If this voltage is less than 9.5 volts but greater than 7.5 volts. If it is then the LO is aligned. If it is not then adjust the LO coil/trimmer until the varact6r voltage falls in this range. 5. Set the RF in to 600 kHz and adjust the tuning 'voltage until the LO is at 1050 kHz. Peak all RF coils for maximum recovered audio at low input levels. 6. Set RF in to 1500 kHz and adjust the tuning voltage until the LO is at 1950 kHz. Peak all RF trim capacitors for maximum recovered audio at low input levels. 7. Go back to step 5 and iterate for best adjustment. B. Check the radio gain at 530 kHz and 750 kHz to make sure that the gain is about the same at these two frequencys. If it is not, then slightly adjust the RF coils until it is. The above procedure will insure perfect tracking at 600 kHz, 950 kHz and 1500 kHz. The amount of gain variation across the AM band using the above procedure should not exceed 6dB. ADDITIONAL INFORMATION R16 and C29 decouple unwanted signals on V + from being coupled into the RF stage. This front end also offers superiQr performance with respect to varactor overload by strong adjacent channels. This results because of the way that gain has been distributed between the 1'st and 2'nd stages. In summary, this front end offers two stages of RF gain with the 2'nd stage acting to gain reduce the 1'st stage when RF AGC is active. Furthermore, a unique coupling scheme is ' employed from the output of the 1'st stage to the input of the 2'nd stage. This coupling scheme equalizes the, gain from one end of the AM band to the other. Additional care has been taken to insure that excellent cross modulation performance, image rejection, signal to noise performance, overload performance, and low distortion are achieved. Performance characteristics for this front end in conjunction with the LM1863 are shown in the data sheet. Also, information with regard to the bandwidth of the front end versus tuned frequency are given below. TUNED FREQUENCY 530kHz 600kHz 1200 kHz 1500 kHz 1630 kHz R5 and C7 act as a low pass filter to remove most of the residual 450 kHz IF signal from the audio output. Some residual 450 kHz signal is still present, however, and may need to be further removed prior to audio amplification. This need becomes more important when the LM1B63 is used in conjunction with a loopstick antenna which might pick up an amplified 450 kHz signal. An additional pole can be added to the audio output after R5 and C7 prior to audio amplification if further reduction of the 450 kHz component is required. -3 dB BANDWIDTH 6.6 kHz 7.2 kHz 20.6 kHz 26.4 kHz 36kHz 512-56 Equivalent Schematic Diagram '~~~+------4-----, t------t---o" ~~ ,ill !i~ r+------------+---~"!; I; ~ t------t----J '--------o-~ ~ S 12-57 • ~Nat1onal PRELIMINARY ~ Semiconductor LM1875 20 Watt Power Audio Amplifier General Description Features The LM1875 is a monolithic power amplifier offering very low distortion and high quality performance' for consumer audio applications. • • • • • • • • • • • The LM1875 delivers 20 watts into a 40 or 80 load on ± 25V supplies. Using an 80 load and ± 30V supplies, over 30 watts of power may be delivered. The amplifier is designed to operate with a minimum of external components. Device overload protection consists of both internal current limit and thermal shutdown. The LM1875' deSign takes advantage of advanced circuit techniques and processing to achieve extremely low distortion levels even at high output power levels. Other outstanding features include high gain, fast slew rate and a wide power bandwidth, large output voltage swing, high current capability, and a very wide supply range. The amplifier is internally compensated and stable for gains 9f 10 or greater. Connection Diagram Up to 30 watts output power Avo typically 90 dB Low distortion 0.015%, 1 kHz, 20 W Wide power bandwidth 70 kHz Short circuit protection Thermal protection with parole circuit High current capability 3A Wide supply range 20V-60V Internal protection diodes 94 dB ripple rejection Plastic power' package TO-220 Applications • • • • • High performance audio systems Bridge amplifiers Stereo phonographs Servo amplifiersInstrument systems Typical Applications + Vee C3 4!l-80 O.l~FT Cl 2.2# VINlj TO·220 Power Package (T) ~I '::' l;'M ;1 ii RS 1 '::' -VEE C4 o.l~FT FRONT VIEW '::' R4 20k TUHf5030-1 R3 lk Order Number LM1875 See NS Package T05S TUH/5030-2 S 12-58 Absolute Maximum Ratings Supply Voltage ±30V Input Voltage Operating Temperature Junction Temperature Power Dissipation (Note 1) Lead Temperature (Soldering, 10 seconds) -VEE to Vee O·Cto + 70·C Storage Temperature 150·C 30W 300·C + 150·C -65·Cto Electrical Characteristics Vee= + 25V, -VEE= -25V, TTAS=25·C, RL=80, Av=20 (26 dB), fo=1 kHz, unless otherwise specified. Parameter Conditions Supply Current POUT = OW Typical Tested Umits Units 70 100 mA DC Output Level Output Power THD=1% THD POUT=20W,fo =1 kHz POUT=20W, fo=20 kHz POUT = 20W, RL = 40, fo = 1 kHz POUT=20W, RL =40, fo=20 kHz Offset Voltage Input Bias Current 0 V 25 W 0.Q15 0.05 0.022 0.07 0.6 % % % % ±1 ±15 mV ±0.2 ±2 p.A 0 ±0.5 p.A Input Offset Current Gain-Bandwidth Product fo=20 kHz 5.5 Open Loop Gain DC 90 PSRR Vee, 1 kHz, 1 Vrms - VEE, 1 kHz, 1 Vrms 95 83 Max Slew Rate 8 Current Limit 4 Equivalent Input Noise Voltage 0.4 MHz dB 52 52 V/p.S 3 3- Rs=6000, CCIR dB dB A p.Vrms Note 1: Assumes TTAB equal to 60'C max. For operation at higher tab temperatures and at ambient temperatures greater than 2S'C, the LMI875 must be derated based on a maximum 150'C junction temperature. Thermal resistance depends upon device mounting techniques. 8JC is typically 2' C/W. See Application Hints. Typical Applications (Continued) Typical Single Supply Operation HI 22k .J:. -, Cl C4 Vee 0.1 ~F 82 22k .1:.C2 47 • F T ~tr ~ R4 1M :q R3 22k '1~5 C6 4 LMI875 r---1 V 87 I 3 ~~~_ I C5- .... 0'22~F"J' C3 1~ ~:+ 85 10k ":" R6 200k TlIH/5030-3 S 12-59 U) ..... CD .... :i ,-------------------------------------------------------------~------------------- Typical Performance Characteristics THO vs Power Output §: ~ ~ .. ~ 1.0~_ _ Vs= ±25V Po=IOW ~ 25 0.04 I\, 0.03 0.02 ~ 0.01 i= i$ 0.01 L.....IUJ..LLWJ'--L.l.1.JWIIL-L...u. 1.0 10 0.1 POWER OUTPUT (W) ~ 20 RL=41l ; 15 RL=81l ~ 10 I~ ,,~ 100 90 80 70 ., 60 "., ~ - ~ 1-- Sf 40 40 o 5 10· 15 20 25 SUPPLY.VOLTAGE (±V) o !: "'-..I NE,ATIVE SUPP~~ I z ~ I ~ INPUT Rs =0 RL=4 1 Vrms ~ liN 35 3D ~TSINK -' L N<;. 25 ~ I I 20 5'C/W HEAT SINK' 15 10 5 I I I -,10rWtEAi SljK o 20 50 100 200 SOD lk 2k 5k 10k 20k FlIEQUENCY (Hz) 30 INFINITE HEAT SINK 4D REFERRE~ 30 20 10 o '1 ,... POSITIVE SUPPLY"'" m 50 E iii 20 V 01016202530 SUPPLY VOLTAGE (±V) 45 IIII~ l/ / Device Dissipation vs Ambient Temperaturet . PSRR vs Frequency 100 "., j V ". o 20 50 100200 500 lk 2k 5k 10k 20k FlIEOUENCY (Hz) Supply Current vs Supply Voltage 80 I o 100 J 1iL=80 THO=I!! 30 ~.-~- .,0.06 :z: 1 35 ;; 0.05 0.1 '":1i ..... I:! Power Output vs Supply Voltage THO va Frequency 0.1 0.09 O.OB 0.07 2'C/W ~EATSINK ..... ..... ......... ""'" - 010203040 so 607080 TA-AMBIENT TEMPERATURE ('C) t
INTERFACE = I'C/VI. See Applicalion Hints. Power Dissipation vs Power Output !: ill ~ ill <> I 50 45 40 35 30 25 20 15 10 Power Dissipation vs Power Output 50 45 Vs-±30ti..- - -- ,--"- ..,...q::---I--_1 L --1'-- L .!! !: ill ...-1--'-- i "'f!i .JII '-Vs= ±25V ...10 I 10 5 o 0 10 15 20 25 Vs=±30V 25 20 15 I I RL=41l 10= 1 kHz 0 30 I r, ~ Vs= ±loV ~"Vs'= ±15~ RL~BIl.l 1o=1kH. 40 35 30 POWER OUTPUT (W) L ".- Vs- ±25V ~ Vs- ±20V ~ ~~=~15V o I r-- 10 15 20 25 POWER OUTPUT (W) 30 TL/H/5030-4 "Thermal shutdown with infinite heat sink ""Thermal shutdown with 1'C/W heat sink S 12-60 en n :J' CD 3 01 102 F 1, lkl .,. OZI 3G 310 ~ L:JI"'oz -~i 02i 3k3~ ~04 .3 3k3 Oil 2kl 7. rt: 014 01: ; 029 O~~ t'L- Q& h- -INPIJT en ..... ~ ~ZI ~ 3k& +INPUT 011 Cl -r~ h~ .,0 _~ Q7~. R4 6k1 , ",-,OlD t""111 ~ .5 1112 SIlk ~011 01 18k 013 lk :: 019~ ~a21 016t.. Z2~ G Z3~ tti: ! r~ ~~ R23 lZOk ;~ ~~ lkl ~c 10 VEE 031 IkS 1 L..- Q36"'-t It'f 021 R36 5l1li ZOO 038 lDk .~ 038 ..... 4DX 817 30k ,031 R32 ~~ ~""Q ~ ~: R34~ lDO .. ',jt-' 026 4Dk :~ 12 OUTPUT R25 102 '1 R32 031 100 12 01. 3d ,020 4 041 Vee Q32.,c CQ Q34'~ R29 028 03G R16 Sk2 ~ 026 t" 021 .... 024 118k ~ "- ,:pJ .. ': t-' 012 R9 4119 ~: jAr i' Al 3 ,~ ~~ jAr 024 ..... ,;! ~011 HC4~ ~017 Q9"AR5 GZ2'l1.. ,....I t" 468 ~ 023~ Va (;' C ~ 10k lk 013 01,;! Vee ,~ Rn 3G 020 a y- t"Q33 ."'-' 021 100 SiGNAl VEE 6kS :~,3524 '-- VEE lk C2 ~~ ~ '" Sl8U'1I1 .... r--------------------------------------------------------------------------------U) CD .,.. ~ Application Hints STABILITY The LM1875 is designed to be stable when operated at a closed-loop gain of 10 or greater, but, as with any other high-current amplifier, the LM1875 can be made to oscillate under certain conditions. These usually involve printed circuit board layout or output/input coupling. Proper layout of the printed circuit board is very important. While the LM1875 will be stable when Installed in a board similar to the ones shown in this data sheet, it is sometimes necessary to modify the layout somewhat to. suit the physical requirements of a particular application. When designing a different layout, it is important to retum the load ground, the output compensation ground, and the low level (feedback and input) grounds to the circuit board ground point through separate paths. Otherwise, large currents flowing along a ground conc.uctor will generate voltages on the conductor which can effectively act as signals at the input, resulting in high frequency oscillation or excessive distortion. It is advisable to keep the output compensation components and the 0.1 p.F supply decoupling capaCitors as close as possible to the LM1875 to reduce the effects of PCB trace resistance and inductance. For the same reason, the ground retum paths for these components should be as short as possible. Occasionally, current in the output leads (which function as antennas) can be coupled through the air to the amplifier input, resulting in high-frequency oscillation. This normally happens when the source impedance is high or the input leads are long. The problem can be eliminated by placing a small capacitor (on the order of 50 pF to 500 pF) across the circuit input. Most power amplifiers do not drive highly capacitive loads well, and the LM1875 is no exception. If the output of the LM1875 is connected directly to a capacitor with no series resistance, the square wave response will exhibit ringing if the capacitance is greater than about 0.1 p.F. The amplifier can typically drive load capacitances up to 2 p.F or so without oscillating, but this is not recommended. If highly capacitive loads are expected, a resistor (at least .10) should 'be placed in series with the output of the LM1875. A method commonly employed to protect amplifiers from low impedances at high frequencies is to couple to the load through a 10n resistor in parallel with a 5 p.H inductor. DISTORTION The preceding suggestions regarding circuit board grounding techniques will also help to prevent excessive distortion levels in audio applications. For low THO, it is also necessary to keep the power supply traces and wires separated from the traces and wires connected to the inputs of the LM1875. This prevents the power supply currents, which are large and nonlinear, from inductively coupling to the LM1875 inputs. Power supply wires should be twisted together and separated from the circuit board. Where these wires are soldered to the board,. they should be perpendicular to the plane of the board at least to a distance of a couple of inches. With a proper physical layout, THO levels at 20 kHz with 10W output to an 8n load should be less than 0.05%, and less than 0.02% at 1 kHz. CURRENT LIMIT AND SAFE OPERATING AREA (SOA) PROTECTION A power amplifier's output transistors can be damaged by excessive applied voltage, current flow, or power dissipation. The voltage applied to the amplifier is limited by the design of the extemal power supply, while the maximum current passed by the output devices is usually limited by intemal circuitry to some fixed value. Short-term power dissipation is usually not limited in monolithic audio power amplifiers, and this can be a problem when driving reactive loads, which may draw large currents while high voltages appear on the output transistors. The LM1875 not only limits current to around 4A, but also reduces the value of the' limit current when an output transistor has a high voltage across it. When driving nonlinear reactive loads such as motors or loudspeakers with built-in protection relays, there is a possibility that, an amplifier output will be connected to a load whose terminal voltage may attempt to swing beyond the power supply voltages applied to the amplifier. This can cause degradation of the output transistors or catastrophic failure of the whole circuit. The standard protection for this type of failure mechanism is a pair of diodes connected between the output of the am'plifier and the supply rails. These , are part of the intemal circuitry of the LM1875, and needn't be added extemally when standard reactive loads are driven. THERMAL PROTECTION The LM1875 has a sophisticated thermal protection scheme to prevent long-term thermal stress to the device. When the temperature on the die reaches 170·C, the LM1875 shuts down. It starts operating again when the die temperature drops to about 145·C, but if the temperature again begins to rise, shutdown will occur at only 150"C. Therefore, the device is allowed to heat up to a relatively high temperature if the fault condition is temporary, but a sustained fault will limit the maximum die temperature to a lower value. This greatly reduces the stresses imposed on the IC by thermal cycling, which in tum improves its reliability under sustained fault conditions. Since the die temperature is directly dependent upon the heat sink, the heat sink should be chosen for thermal resistance low enough that thermal shutdown will not be reached during normal operation. Using the best heat sink possible within the cost and space constraints of the system will improve the long-term reliability of any power semiconductor device. POWER DISSIPATION AND HEAT SINKING The LM1875 must always be operated with a heat sink, even when it is not required to drive a load. The maximum idling current of the device is 100 mA, so that on a 60V power supply an unloaded LM1875 must dissipate 6W of power. The 'S4·C/W junction-to-ambient thermal resistance of a TO-220 package would cause the die temperature to rise 324·C above ambient, so the thermal protection circuitry will shut the amplifier down if operation without heat sink is attempted., a S 12-62 Application Hints (Continued) In order to determine the appropriate heat sink for a given application, the power dissipation of the LM1875 in that application must be known. When the load is resistive, the maximum average power that the IC will be required to dissipate is approximately: VS2 PO(MAX):::: 21T2RL + Pa where Vs is the total power supply voltage across the' LM1875, RL is the load resistance, and Pa is the quiescent power dissipation of the amplifier. The above equation is only an approximation which assumes an "ideal" class B output stage and constant power dissipation in all other parts of the circuit. The curves of "Power Dissipation vs Power Output" give a better representation of the behavior of the LM1875 with various power supply voltages and resistive loads. As an example, if the LM1875 is operated on a 50V power supply with a resistive load of 80, it can develop up to 19W of internal power dissipation. If the die temperature is to remain below 150·C for ambient temperatures up to 70·C, the total junction-to-ambient thermal resistance must be less than 150·C-70·C 19W 4.2·C/W. Using (}JAT'2·C/W, the sum of the case-to-heat-sink interface thermal reSistance and the heat-sink-to-ambient thermal resistance must be less than 2.2"C/W. The case-toheat-sink thermal resistance of the TO-220 package varies with the mounting method used. A metal-to-metal interface will be about 1·C/W if lubricated, and about 1.2·C/W if dry. If a mica insulator is used, the thermal resistance will be about 1.6·C/W lubricated and 3.4·C/W dry. For this example, we assume a lubricated mica insulator between the LM1875 and the heat sink. The heat sink thermal resistance must then be less than 4.2"C/W - 2"C/W -1 ,6"C/W = 0.6·C/W. This is a rather large heat sink and may not be practical in some applications. If a smaller heat sink is required for reasons of size or cost, there are two alternatives. The maximum ambient operating temperature can be reduced to 50·C (122·F), resulting in a 1.6·C/W heat sink, or the heat sink can be isolated from the chassis so the mica washer is not needed. This will change the required heat sink to a 1.2·C/W unit if the case-to-heat-sink interface is lubricated. Note: When using a single supply, maximum transfer of heat away from the LM1875 can be achieved by mounting the device directly to the heat sink (tab is at ground potential); this avoids the use of a mica or other type insulator. The thermal requirements can become more difficult when an amplifier is driving a reactive load. For a given magnitude of load impedance, a higher degree of reactance will cause a higher level of power dissipation within the amplifier. As a general rule, the power dissipation of an amplifier driving a 60· reactive load (usually considered to be a worst-case loudspeaker load) will be roughly that of the same amplifier driving the resistive part of that load. For example, a loudspeaker may at some frequency have an impedance with a magnitude of 80 and a phase angle of 60·. The real part of this load will then be 40, and the amplifier power dissipation will roughly follow the curve of power dissipation with a 40 load. Component Layouts Single Supply Split. Supply GND TLIH/5030-6 S 12-63 TLIH/S030-7 • • r-------------------------------------------------------------------------, ~ - ~National PRELIMINARY :i ~ Semiconductor LM 1884 TV Stereo Decoder General Description Applications The LM1884 is a decoder designed for television stereo. An L-R output is provided to drive further audio processing. - Stereo television sets _ Stereo adapters _ Cable television Features _ Low impedance L + Rand L:"" R outputs _ Mono/Stereo switching and indication _ Low distortion - 0.10% typical Block Diagram COMPOSITE .-J 1NPUT""l PIlOT OET£CTlIR ~~~": t<>-tII- + ----..II .......,,..-.... I I I _ _.... 1 ~ REOUIJITOR _____ ~V" ~-..J LMl184 L+R OUT TLlH/6759-1 S 12-64 Absolute Maximum Ratings T A = + 25"C unless otherwise noted Power Supply Voltage Storage Temperature Range 16V Power Dissipation (Package Limitation) 1800mW Derate Above TA = + 25"C 15 mWI"C Operating Temp. Range (Ambient) -65"Cto +150"C Lamp Drive Voltage Max Voltage at Pin 7 with Lamp "Off" 16V Lamp Current -40"C to + 85"C 100mA Electrical Characteristics Parameters Guaranteed by Electrical Testing Test Circuit, T A = + 25"C, Vcc= 12V unless noted I Parameter I Conditions DC I Min I Typ Max I Units VIN = 0 Supply Current Vcc=16V 15 33 50 mA Output Voltage Pin4 1.7 3.5 5.0 V Output Voltage Pin 5 1.7 3.8 5.0 V Output Impedance Pins 4, 5 100 300 n Lamp Leakage Lamp off, pin 7 voltage = 16V 1.0 mA Lamp Saturation Voltage Lamp on, pin 7 current = 100 mA 2.0 V AudiO Composite signal with 38 kHz subcarrier and 10% 19 kHz pilot. L + R Channel Gain VIN=2.5Vpp L=R, pilot off, pin 4 L + R Channel THO VIN = 2.5Vpp L = R, pilot off, pin 4 Gain Ratio, L + R Channel to L - R Channel Adjust P1 for 19 kHz plus/minus 10 hz. (Note 1) 0.8 VIN = 2.5Vpp, L only Supply Rejection 100 mVrms, 1 kHz on supply, VIN=O DC Output Shift, Mono to Stereo Pilot off to on, pins 4, 5 Input Impedance Pin 1 1.0 1.2 0.1 1.0 % -2.0 0.0 2.0 db 30 60 ±20 mV 150 kn 12 20 mV 3 10 mV 15 db 50 PLL Pilot Level for Lamp On Pilot Level for Larnp Off Capture Range Pilot = 25 mVrms % ±0.5 Note 1: The LM1884 will be available tested with a 15.734 kHz pilot after product introduction. Test Circuit Vee 8 Vuc·16V,C pJ~ - P1 ::r 18 C8 H2~ I 15 14 15.734kHz MONITOR STElleo SWI Cl 2.2"F rfJ 4 C6 0.015"F 0.0082.F lOll 1.r 5.1k L+R L-R -------OUTFUTS FIGURE 1. S 12-65 7-¥ R7 660 ~ 5.1k Coefficient resistor recommended 6 C7 0.015"F ~ '=" , . ,af LM1884 7k5 .. Metal film, zero temperature r.r~ ,,-t;, '" • 13 R8 100 COM~snE~.F- -::I.. -.J.~r.J2 INPUT R2 lk 0.47 "F-r-c~ 0.1"F ..l..~3 Rl' _ ,....~OpF 10k "220 5k VCO ADJUST Ir. C4 7k5 10\ ~ Vee INDICATOR LED ':" Tl/H/6759-2 Typical Application Vee BVoe-16 Voe PI 5k VCO ADJUST FM STEREO COM~:~J~ _ _ _"F~_'" (19kHz PILOT) L..ow..,...f....fi-.Vee STEREO INDICATOR LEO OUTPUTS TL/H/6759-3 • Metal film, zero temperature coefficient resistor recommended Supply Current vs Supply Voltage 36 1 I 35 I 34 MolD 33 100 90 r- r- 31 I 30 8 19.2 ~T"--r-""--r--r-"~~ I. ~~ 19.1 !19.0 ~ :~ § 40 I STElIEO ~ 32 iil l:: 30 ~ 20 ili a: 18.7 o VCO Frequency vs Supply Voltage 60r-r-r-r-r-r-~~, ,='1 kH~, 2JO Jms bN pIN lJ 50 19 FREQUENCY (kHz) lB.6 '--"'--'--'--'-.......--''--'--' 8 10 11 12 13 14 15 16 SUPPLY VOLTAGE (V) Power Supply Rejection vs Supply Voltage . ;; 0.6 i .. IS 0.5 0.4 Hc-t-lf Z co 0.3 ~ 30HH~~~~~~~ :Ii iil II == 20~~~~~-4-4-4 0.2 g ... 0.1 o L.!!!!:!=:t::t:CU.J..J o 0.8 1.6 2.4 3.2 4.0 10~~~~~~~~ 8 20 . _ 0.7 ......:-;:::;:0-,-,--.-,-,....,.:.., I 40Hr+-+-,r-r-+-1--~ I 5i lB.8 ""-..... .,./ I 18 ~ ~ 18.9 ~ 10 10 11 12 13 14 15 16 SUPPLY VOLTAOE (V) ! Total Harmonic Distortion vs Composite Input Level Capture Range vs Pilot Level 10 11 12 13 14 15 16 SUPPLY VOLTAGE (V) COMPOSITE INPUT LEVEL (Vp·p) TLlH/6759-4 S 12-66 ,-------------------------------------------------------------------------, r ~National PRELIMINARY ~ Semiconductor BI-LINETM ....== 01) CD Co) LM 1893 Carrier-Current Transceivert General Description Carrier-current systems use the power mains to transfer information between remote locaiions. This bipolar carriercurrent chip performs as.a power line interface for half-du-. plex (bi-directional) communication of serial bit streams of virtually any coding. In transmission, a sinusoidal carrier is FSK modulated and impressed on most any power line via a rugged on-Chip driver. In reception, a PLL-based demodulator and impulse noise filter combine to give maximum range. A complete system may consist of the LM1893, a COPSTM controller, and discrete components. Features • • • • • Noise resistant FSK modulation User-selected impulse noise filtering Up to 4.8 kBaud data transmission rate Strings of D's or 1 's in data allowed Sinusoidal line drive for low RFI • • • • • Output power easily boosted 10-fold 50 to 300 kHz carrier frequency choice TTL and MOS compatible digital levels Regulated voltage to power logic Drives all conventional power lines Applications • • • • • • Energy management systems Home convenience control Inter-office communication Appliance control Fire alarm systems Security systems • Telemetry • Computer terminal interface Typical Application y. y. 11 • 12 TUH/6750-1 FIGURE 1. Block diagram of carrier-current chip with a complement of discrete components making a complete transceiver_ Use caution with this circult-cJangerous line voltage is present. tCamer-Current Transceivers are also called Power linG Carrior (PLC) transceivers. S 12-67 Absolute Maximum Ratings Supply voltage Voltage on pin 12 Voltage on pin 10 (Note 1) Voltage on pins 5 and 17 5.6 V DC zener current 30V 55V 41 V 40V 1QOmA General Electrical Characteristics 150·C Junction temperature: transmit mode receive mode 125·C Maximum continuous dissipation, TA= 25·C, (Note 2): plastic DIP N 1.66W -25t085·C Operating ambient temp. range Storage temperature range -65 to 150·C 260·C Lead temp., soldering, 7 seconds (Note 3). The test conditions are: V+ = 18 V and Fo= 125 kHz, unless otherwise noted. Parameter # Conditions Typical 1 5.6 V Zener voltage, Vz Pin11,lz=2mA 5.6 2 5.6 V Zener resistance, Rz 3 Carrier I/O peak survivable transient voltage, VOT 4 Carrier I/O clamp voltage, Voc Pin 11, Rz=(Vz@10mA-Vz@1 mA)/(10 mA-1 mAl Pin 10, discharge 1 !LF cap. charged to VOT 5 80 5 6· 7 8 Pin 10, loe = 10 mA, RX mode 2N2222 diode pin 8 to 9 Carrier I/O clamp resistance, R10 Pin 10,loe= 10 mA Pin5 TX/RX low input voltage, Vll Pin 5 (Note 9) TX/RX high input voltage, VIH Pin5atO.8V TX/RX low input current, III 9 TX/RX high input current, IIH Pin5at40V 10 RX - TX switch-over time, TRT Time to develop 63% of full current drive through pin 10 11 TX - RX switch-over time, TTR 1 bittime TB= 1/(2FoATM Time TTR is user controlled with CM, see Apps. Info. TX mode, Ro = 6.65 kO, Co = 560 pF Test Design Limit Limit (Note 4) (Note 5) 5.2 5.9 60 44 41 50 20 1.8 2.2 ..,.2 12 ICO initial accuracy of Fo 10 !Ls 2 bit , 125 13 ICO temperature coefficient of Fo TX mode, (FOMAJ(-FOMIN)/(TJMAJ(-TJMIN) 14 Temperature drift of Fo TXmode, -25~TJ~150·C V min. V max. 0 'V max. V min. V max. 0 V max. V min. !LA min . ",A max. ",A min. ",A max. 0.8 2.8 -20 1 -1 10 10-4 Limit Units 113 137 (±200) (±2.0) kHz min. kHz max. PPMI"C (±5.0) % max. Transmitter Ele,ctrical Characteristics (Note 3). The test conditions are: V+ = 18 V and Fo= 125 kHz unless otherwise noted. The transmit center frequency is Fo, FSK low is F1, and FSK high is F2. # Parameter Conditions Typical (13) 1.7 2.1 -1 15 Supply voltage, V+ , range 16 Total supply current, lOT 17 18 Carrier I/O output current, 10 Carrier I/O lower swing limit, VALC 19 THO of 10 (Note 6) 20 FSK deviation, F2 - F1 Meets test 17 spec. at TJ = 25·C and: I(Fj [14V]- F1 [18V])/Fj [18V] I <0.01 I(Fj [24V]-F1 [18V])/F1 [18V]I <0.01 Pin 15. Pin 12 high. lOT is 10 through pin 15 and the average current looc of the Carrier I/O through pin 10 1000 load on pin 10 Pin 10. Set internally be ALC 2N2222 diode pin 8 to 9 Q of 10 tank driving 100 line 1000 load, no tank (F2-F1)/([F2+ F1]12) 21 22 23 Data In. low input voltage, Vll Data In. high input voltage, VIH Data In. low input current, IlL Pin 17 Pin 17 (Note 9) Pin 17 at 0.8 V 24 Data In. high input current, IIH Pin 17at40V Test Limit (Note 4) 14 24 Design Limit (Note 5) (15) (23) Limit Units V min. V max. 42 79 mAmax. 70 4.7 45 4.0 5.7 mAppmin. V min. V max. % max. % max. % min. % max. V max. V min. !LA min. ",A max. !LA min. ",A max. 0.6 5.5 4.4 (2.0) 9 3.7 5.2 0.8 2.8 -10 1 -1. 10 10-4 Transients may reach above 60 V; see. the transient peak voltage characteristic curve. The maximum power dissipation rating should be derated for device operation above 25'C to insure that the Junction temperature remains below the maximum rating. Use a 8JA of 75'CIW for the N package using a socket in still air. Consult the Application Information section for more detail. Note 1: Nole 2: S 12-68 Receiver Electrical Characteristics (Note 3). The test conditions are: V + = 18 V, FO = 125 kHz, ± 2.2% deviation FSK, FDATA=2.4 kHz, VIN= 100 mVpp, in the receive mode, unless otherwise noted. # Parameter Conditions 25 Supply voltage, V+ , range Functional receiver (Note 7) 26 Supply current, lOT lOT is pin 15 (V +) plus pin 10 (Carrier 110) current. 2.4 kO Pin 13 to GND. 27 Carrier 110 input resistance, R10 Pin 10 28 Max. data rate, FMD Functional receiver (Note 7) square-wave data, 2.4 kHz = 4.8 kBaud Typical Test Design Limit Limit (Note 4) (Note 5) (13.5) (28) LImit Units - (12) 13 30 11 5 14 mAmin. mAmax. 19.5 15 30 kOmin. kOmax. 10 4.8 (2.4) V min. V max. kBaud 29 PLL capture range, Fc CF=100 pF, RF=O 0 ±40 ±20 % min. 30 PLL lock range, FL CF=100pF,RF=OO ±45 ±20 % min. 31 Receiver input sensitivity, SIN For a functional receiver (Note 8) Referred to chip side (pin 10) of the line-coupling XFMR: Fo = 50 kHz Fo=300kHz Referred to line side of XFMR: (assuming a 7.07:1 XFMR) Fo=50 kHz Fo=300 kHz 1.8 2.0 1.4 0.26 0.29 0.20 10 2 0.1 55 V min. 0.4 V max. /loA min. /loA max. Vmin. V max. (12) mVRMS mVRMS mVRMS mVRMS mVRMS mVRMS V max. 32 Tolerable input dc voltage offset range, VINDC Pin 10 lower than pin 33 Data Out. breakdown voltage Pin 12, leakage I ~ 20 poA 34 Data Out. low output, VOL Pin 12, sat. voltage at IOL = 2 mA 70 0.15 35 Impulse noise filter current, II Pin 13 charge and discharge current ±50 ±45 ±85 36 Offset hold cap. bias voltage, VCM Pin6 2.0 1.3 3.5 37 Offset hold capacitor max. drive current, IMCM Pin 6. V(pin 3)-V(pin 4)= ±250 mV ±48 ±25 ±80 38 Offset hold bias current, IOHB Pin 6, TX mode. Bias pin 6 as it selfbiased during test 32. -0.5 -20 39 Phase comparator current, IPC Bias pins 3 and 4 at8.5 V Ipc = I(pin 3) + I(pin 4), TX mode 100 50 200 /loA min. poAmax. Pins 3 and 4. RpD=(V@100/loA-V@50/loA)/(50/loA) 10 6 18 kOmin. kOmax. Pin 3 to 4, measured after filtering out the 2Fo component 100 60 180 mVppmin. mVppmax. 40 41 Phase detector output resistance, RpD Phase detector demodulated output voltage, VPD (-40) (40) /loA min. /loA max. nAmin. nAmax. 0.95 0.70 VlVmin. 42 Fast offset cancel voltage "window" VPIN3 - VPIN4 = ± VWINOOW + DC offset VlVmax. Drive for ± 1 /loA pin 6 current 1.20 -to-VPD ratio, VWIVPD 43 Power supply rejection, PSRR dB min. CL = 0.1 /loF. PSRR = CMRR.120 Hz 80 Note 3: The values inside parenthesiS () eppiy over the full operating temperature range after warmup for the specified supply -voltage range. All other numbers apply at TA=TJ=2S·C. Note 4: Guaranteed and 100% production tested. Note 5: Guaranteed (but not t 00% production tested) over the temperature and supply voltage ranges. These limits are not used to calculate outgoing quality levels. Note 6: Total harmonic distortion is measured using THD= [lRMS (all components at or above 2Fo)]/[lRMS (fundamental)]. Note 7: Receiver function is defined as the error-free passage of t cycle of SO% duty-cycle 2.4 kHz square-wave data (2 sequential 208 p.S bits). with the first bit being a "I." All of the data transitions (edges) must fall within ± 10% (± 20.8 "s) of their noise-free positions. RX time delay Is minimized by using no impulse noise filter cap. CI for this tast Note 8: During the sensHivity check. note 7 requirements are followed wHh these exceptions: (1) data rate FDATA = 1.2 kHz. (2) all of the data transHions must fall within ±20% (±41.6 "s) of their noise-free positions. and (3). a time-domain filter cepacHor (CI) is used. The time delay of CI is Yz bit. or 208 "s. (CI is epproximately 8200 pF). Note 9: For TTL compatibility use a pull-up resistor to increase min. VOH to above 2.8 V. S 12-69 Typical Performance Characteristics Supply Current vs., 70 Supply Voltage ! 60 ffi 50 ~ 40 ~~~~+~IOO~C~-~I~~~~§l~~ TX MOOi:- EESE:EEnm ~ 20~§!~l§~R~X~M~00~E~~ ~ C §. 80 Supply Current va. Junction Temperature 70 lal -Ia +looc 60 i'" 50 ::> ,to ::> i 9 10 ~ 20 9 ,.. 50 10 ~N15 ! .- ,:OO1 r M E I '1IRXMoo!;;;l~ 6 IODC. PIN 10 -2 -10 0 10 20 3D 40 BIAS VOLTAGE (V) 50 Pin 10 Current vs. Junction Temperature 12 rT~-rrr~'-rr~~ • =1+ Ri MODE V+=YPlN1S=YPlN10+-b 12 10 Bias Currenta va. Junction Temperature TX MODE-tIODC. PI~Or- 60 FP''''~Iiil~~~I-HRXIMbJE la. PIN 151-F'I"iIi...d-I 40 v+ :s30V:'H-++-I i 1 Vrml0>3DV: 3D H-+--l++-f '--t- Bias Currents va. 14 Supply Voltage 0 -60 -3D 0 30 60 90 120 150 TJ-JUNCTION TEMPERATURE ('C) 60 r-r-r--r-r-r............r""T'"""M...... ! RX MODE 10 Pin 10 Current vs. Supply Voltage 50 TX MODE 40 E 3D 3D 10 20 3D 40 SUPPLY VOLTAGE (V) (V+ = 18V. Fe = 125 kHz. circuit of Rgure 1) ! 2o~~~~t.~*+, ~~ 10 v+ =YPlN15 =YPlN10' H-+-:JJ.+-H-~N15=18V 10 20 3D 40 BIAS VOLTAGE (V) IDOC. PIN 10 RX E w co . ~ co w !l E t- "'- Transmitter Sinusoid THD vs. Junction Temperature Transmitter Output Current va. Junction Temperature 120 rT~-rrrT'"T'-I"T~~ c: 1 0 _ :! 100 1oot::t+++++-H-t11-+-1-H ..... 1'01.. Woc"-' ,.. ~ _::to! .. I I - 100 PULSE TIME (SECONDS) 102 10- 6 10- 4 10- 2 80 &OH-H++~rP~++-H; ! 40H-+++H--t-I~H-~~ 7 20H-++++~1-I-r+++-H-I !i1 H-N--H-H-1'~DOO H--t-I-I"IV--t-I+H-H-H ~ i ,).' N~N-Rr~ITIVF ~LSEI- 0 ................J....L..J...!....L.J...J-u,....u..J -60 -30 0 3D 60 90 120 150 TJ-JUNCTION TEMPERATURE ('C) ALC Voltage vs. Junction Temperature TJ-JUNCTION TEMPERATURE ('C) ICO Frequllncy vs. Junction Temperature rc ~~~~~~~~~ -60 -3~ 0 3D 60 90 120 150 TJ -JUNCTION TEMPERATURE ('C) • .!o. -r- o -60 -30 0 3D 60 90 120 150 TJ-JUNCTION TEMPERATURE ('C) 50 Transient VOltage Survival vs. Pulse Time 100 90 80 70 60 50 40 3D 20 10 0 10 1-++++11-+-1-1-+++++1-1 o ~MI:Ei:lI:f:!:l~ 1.03 Transmitter FSK Deviation vs. Junction Temperature 4.9 H-++++~H--H-+++I; G 1.02 ....,--T:T::crc.:;..:.. l00PPM/'C : 1.01 1+'IoI::-HH-H-HH-H+l ;5- 1.00 @ 1+-!!:CH~I.d-+++H-+-I-I I ~ 0.99 ~til~-I-~'i;!"~~PP~.~~;~~'C~~~~~~~ 0.98 I~ 0.97 H-++-H-HH-H-+t-H-i , -60 -3~ 0 30 60 90 120 150 TJ-JUNCTION TEMPERATURE ('C) -60 -3D 0 3D 80 90 120 150 TJ-J~NCTIOH TEMPERATURE ('C) I:!i 4.7 ~ i!i 4.& £i 4.5 ~ u .. ~' 4.3 4.2 -60 -3~ 0 3D 60 90 120,150 TJ-JUNCTION TEMPERATURE ('C) TLIH/6750-38 S 12-70 Typical Performance Characteristics Maximum Data Rate vs. Junction Temperature Receiver Sensitivity vs. Junction Temperature 3 32 16 2B 14 t::i i... !;;: 24 12 20 ~ 16 c => '" :IE => :IE ~ 10 i ! B ~ c 5i ~ 4 ±10%0UTY CYCLE SHIFT NO LOOP FILTER :IE E 2. w 12 B :IE => :IE ~ :IE 0 -60 -30 0 3D 60 90 120 150 TJ-JUNCTION TEMPERATURE (OC) S :s ~ 20 10-300 kHz f-lo~KI- ~ 10 II 0 ~ -20 II I CAPTURE 9 -10 Cl I II I I OUT OF LOCK CAPTURE '" ~ LA~GE SIGNAL Ip[Lf I : I~ LIOCr OUT OF LOCK It \O~KI -30 I II I I -40 HIGH lDAlA LOOP FllJER I I I I -50 -60 -30 0 30 60 90 120 150 TJ-JUNCTION TEMPERATURE (OC) I. fil o => tlI . '" '" ~ 40 : ~ 31001k~Z g MAX. 10AlA COMPONENT VALUES. 10=125,300 kHz IDAlA = 2.4 kHz IDAlA=I.2 kHz 10 =50 kHz -' -30 3D 20 125 ~H~ rt1 o z Receiver Sensitivity vs. PLL Lock Range and Loop Filter i obT 6F LOCK IN LOCK 10 e. I·AuTIOF LOCK E ~ 10 50 kHz 125 kHz 300 kHz- i 1 -50 c.-> O~: ~ ill i 1 -50 50 VPD !:l 100 120~ lOD~ \\v 5! BO BO iii 60 60 s5 I 40 40 20 o 0 -60 -3~ . 0 30 60 90 120 150 TJ-JUNCTION TEMPERATURE (OC) Offset Hold Cap. Bias Current vs. T CK -30 -10 10 3D LOCK RANGE (% OF 10) 50 Bo 160c: w ~ ~ OUT OF LOCK NO LOOP FILTER PLLlN LOCK Offset Hold Cap. Charge Currents vs. Junction Temperature 140! t ::: FI~ER \ 10 ~ w H!GH IDAlA F1lJER ... CO MPIiNENTS -30 -10 10 3D LOCK RANGE (% OF 10) HIGH IDAlA Phase Detector Output Voltage vs. Junction Temperature 3D 60 90 120 150 TJ-JUNCTION TEMPERATURE (OC) 3rOrH,z LARGE SIGNAL ! III -liD -30 0 IN LOCK 100 ~ 20 10 10 125 kHz 300 kHz -60 -3~ 0 30 60 90 120 150 TJ-JUNCTloN TEMPERATURE (OC) i !... s ~ T 1'50UZ -50 Receiver Sensitivity vs. PLL Lock Range and Fe ~ Ju;ohhc~ -40 100 ~ § :z: ! 0 ~ -10 -20 OEV.=4.4% 70 50 ~ -60 -30 0 30 60 90 120 150 TJ-JUNCTION TEMPERATURE (OC) Bo 60 ,;. 125 kHz IIIw 30 20 10 ~ 50 kHz Impulse Noise Filter Current vs. Junction Temperature ~ 50 40 99.7% OF SQ. WAVE EDGES WITHIN 40%-60% DUTY CYCLE ~ ~ '" PLL Lock Range vs. Junction Temperature and Fe .e PLL Capture & Lock Range vs. Junction Temperature 50 40 3D (V+ =18V. Fo = 125 kHz. circuit of Figure 1) (Continued) i "i ~ 70 ~ 60 .i!l 40 '" 30 .... gj tlI 5'" ~ CHARGE 50 OISCHARGE"!!!I ~ 20 10 o "" IMCM FUll SWITCHING- -60 -3~ 0 3D 60 90 120 150 TJ-JUNCTION TEMPERATURE (OC) • Data Out. Low Voltage vs. Pull Down Current 6 Junction Temperature ,. 1.0 w 10~B ~ !:l c ,. .... ~ l,;o 0.5 c ~I o -60 -3~ 0 30 60 90 120 150 TJ-JUNCTION TEMPERATURE (OC) ~ ; , I'" L; 5 COLLECTOR CURRENT (mA) 10 TUH/e7SO-39 S 12-71 Application Information THE DATA PATH The BI-LINETM chip serves as a power line interface in the system of FJguf'6 3. FJgure carrier-current transceiver 4 shows the interface Circuit now discussed. The controller may select either the transmit (TX) or receive (RX) mode. Serial data from the controller is used to generate a FSKmodulated 50 to aoo kHz carrier on the line In the TX mode. In the RX mode line signal passes through the coupling transformer into the PLL-based receiver. The recreated serial bit stream drives the controller. (ccn With the IC in the TX mode (pin 5 a logic high), baseband data to 5 kHz drive the modulator's Data In pin to generate a switched 0.987111.0221 control current to drive the low TC, triangle-wave, current-controlled oscillator to ±2.2% deviation. The tri-wave passes through a differential attenuator and sine shaper which deliver a current sinusoid through an automatic level control (ALC) circuit to the gain of 200 current output amplifier. Drive current from the Carrier I/O develops III voltage swing on T1'S (Figure 4) resonant tank proportional to line Impedance then passes through the step-down transformer and coupling capaCitor Cc onto the line. Progressively smaller line impedances cause reduced signal swing, but never clipping-thus avoiding potential radio , frequency interference. When large line impedances threaten to allow excessive output swing on pin 10, the ALC shunts current away from the ,output amplifier, holding the voltage swing, constant anp within the amp's compliance limit. The amplifier is stable with a load of any magnitude or phase. In the RX mode (pin 5 a logic low), the TX sections on the chip are disabled. Carrier Signal, broad-band noise, transient spikes, and power line component impinge of the receiver's input highpass filter, made up of Ccand T1, and the tank bandpass filter. In-band carrier Signal, band-limited noise, heavily attenuated line frequency component, and attenuated transient energy pass through to produce voltage swing on the tank, swinging about the positive supply to drive the carrier I/O receiver input. The balanced Norton-input limiter amplifier removes DC offsets, attenuates line frequency, performs as a bandpass filter, and limits the Signal to drive the PLL phase detector differentially. The differential demodulated output signal from the phase detector, containing AC and DC data Signal, noise, system DC offsets, and a large twice-the-carrier frequency component, passes through a a-stage RC lowpass filter to drive the offset cancel circuit differentially. The offset cancelling circuit works by insuring that the (fixed) ± 50 mV signal delivered to the data squaring ("slicing") comparator is centered around the o mV comparator switch point. Whenever the comparator signal plus DC offset and noise moves outside the carefully matched ±50'mV voltage "window" of the offset cancel circuit, it adjusts its DC correction voltage in series with the differential signal to force the signal back into the window. While the signal is within the ± 50 mV window, the DC offset is stored on capaCitor CM. By grace of the highly non-linear offset hold capacitor charging during offset cancelling, the DC cancellation is done much more quickly than with an AC coupling capacitor normally used in place of the offset cancel circuit. Since impulse noise spikes normally ring the signal symmetrically around 0 V, the fuliy bilateral offset cancel topology affords excellent noise rejection. The switched current output of the comparator drives the impulse noise filter integrator capacitor that rejects all data pulses of less than the integrator charge time. False bits and noise may appear as duty-cycle jitter errors at the open collector serial data output. u=:--.-tJ----, POWER LINE Dual-In-Llne Package ICO CAP 1 18 ICO FREQUENCY ICO CAP 2 17 PATAIN lB LIMITER FIllER , PLl FILTER 1 3' PLL FillER 2 Tx/III SELEer LMI893 15 v+ 14 GROUND OFFSEI' HOLD CAP 13 NOISE INTEGRATOR ALC STABILITY 12 PATAOUT BOOST EMmER 11 5.6VZENER BOOST BASE 10 CARRIER 110 I TOP VIEW B TLlH/8750-2 FIGURE 2. Connection Diagram TLlH/8750-3 FIGURE 3. The block diagram of a carrier-current system using the BI-Llne chip to Interface digital controllers via the power line See NS Package Number N18A Order Part LM1893N S 12-72 l> "C ~ ~. O· ::::J Y' CC l~ ti HOT ::::J o 3 CA NUE GNO Tl -... - Ro ~ CONTROLLER S» o::::J· Y+ RA ~ a 2 ~ I ....rn I 1 I L "!YJ ... I}) '" OPTIONAL Rc I I I I L.. __ J Ro 5Y 121 OPTIONAL BOOST TLlH/6750-4 FIGURE 4. Block diagram of a CCT system with the boost and 5V supply options shown in dashed boxes t68~W' II Application Information # Recommended Value Co 560pF Purpose (Continued) Effect of making the component value: Smaller Notes Larger Ro 6.2kO ' Together, Co and Ro Increases Fo set ICO Fo. Increases Fo <5.6 k not recommended. Decreases Fo ± 5% NPO ceramic. Use low TC 2 k pot and 5.6 k fixed R. Decreases Fo > 7.6 k not recommended. Poor Fo TC with < 5.6 k RO. CF 0.047 p.F PLL loop filter pole RF 3.3kO PLL loop filter zero Less noise immune, higher FOATA, more PLL stability. PLL less stable, allows less CF. Less ringing. More noise immune, lower FOATA, less PLL stability. PLL more stable, allows more CF. More ringing. Depending on RF value and Fo, PLL unstable with large CF. See Apps. Info. CF and RF values not critical. Cc 0.22 p.F Couple Fo to line, Ce and :r1 low-pass attenuates 60 Hz. Low TX line amplitude. Less 60 Hz T 1 current. Less stored charge. Drives lower line Z. More 60 Hz T 1 current. More stored charge. :2:250 V non-polar. Use 2Cc onhot and neutral for max. line isolation, safety. Co 0.033 p.F T1 Use recommended XFMR Tank matches line Z, bandpass filters, isolates from line, and attenuates transients. Tank Fo up or in!)rease Tank Fo down or decrease L of T 1 for constant Fo. L of T 1 for constant Fo. Smaller L: /ligher FO or Larger L: lower Fo or increase Ce; decreased Fo decrease Ce; increased Fo line pull. line pull. 100 V nonpolar, low TC, ± 10% High large-signal 0 needed. Optimize for low Fo line pull with control of Fo TC andO. CA 0.1 p.F RA 10kO ALCpoie ALCzero Noise spikes turn ALC off. Less stable ALC. Slower ALC response. More stable ALC. RA optional. ALC stable forCA:2:100pF. CL 0.047 p.F Limiter 50,kHz pole, 60 Hz rejection. Higher pole F, more 60 Hz reject. Fo attenuation? Lower pole F, less 60 Hz ' reject, more noise BW. Any reasonably low TC cap. 300 pF guarantees stability. CM 0.47 p.F Holds RX path Vos Less noise immune, shorter More noise immune, longer Low leakage ±20% cap. Vos hold, faster Vos aqui- Vos hold, slower Vos aqui- Scale with FOATA. sition, shorter preamble. sition, longer preamble. CI 0.047 p.F Rejects short pulses Less impulse reject, delike impulse noise. lay, more pulse jitter. Re 10kO Open-col. pull-up Less available sink I. Rz 12kO 5.6 V Zener bias Larger shunt current, more chip dissipation. ZT :2:44VBV <60 V peak RT 4.70 Transient clamp Transient I limit Higher Rz-excess peak V, Zener and chip damage. Damage ZT, pull up V +. Lower Rz gives enhanced Recommend Zener rated transient clamp. Costly. for :2: 500 W for 1 ms Excessive TX attenuation. Carbon compo recommended RB 1800 OB PowerNPN RG 1.10 Base bleed Boost gain device Current setting R Faster, lower THD 10. Excessive TJ and VSAT. More 10, need higher hie. Inadequate turn-off speed. Boost optional. OB F( - 3 dB) More rugged, but costly. of > 200 MHz. RB > 24 Ohm. 10=700[(10+RG)/10RGJ mApp. Less 10, lower min. hie. CB :2:47 p.F Supply bypass Transients destroy chip. Less supply spike. More impulse reject, delay, less pulse jitter. CI charge time % bit nom. Must be < 1 bit worst-case. Less available source I. RC:2:1.5 kO on 5.6 V . Smaller shunt current, less V + current draw. 1 < Iz <30 mA recommended. (Chip power-up needs 5.6 V) V+ never over abs. max. r=IGURE 5. A quick explanation of the external component function using the circuit of Figure 4. Values given are for V+ = 18 V, Fo = 125 kHz, FOATA = 360 Baud (180 Hz), using a 115 V 60 Hz power line - Component Selection Assuming the circuit of Figure 4 is used with something other than the nominal 125 kHz carrier frequency, 180 Hz data rate, 18V supply voltage, etcetera, the component values listed in Figure 5 will need changing. This section will help direct the CCT designer in finding the required component values with emphasis placed on look-up tables and charts instead of circuit theory. It is assumed that.the designer has selected values for carrier center frequency, Fo; data rate, FOATA; supply voltage, V +; and power line voltage, VL, and frequency, FL. If one or more of those parameters is not defined, one may read the data sheet and make an educated guess - or just pick a nominal value and try the circuit. ter, 2) the lower the maximum data rate the better, and 3) the more time and frequency filtering the better. Use Figure 5 as a quick reference to the external .component function. The Transmitter Co Central to chip operation is the low TC of Fo emitter-coupled oscillator. With proper Co, the Fo of the 2VSE amplitude triangle-wave oscillator output may vary from near DC to above 300 kHz. While Co may have any value, Co should Maxims to keep in mind, based on CCT electrical performance considerations only, are: 1) the higher the Fo the bet- S 12-74 The Transmitter (Continued) be made above 10 pF so that parasitic capacitance is not dominant. Excessive or unbalanced common-mode-toground capacitance should be avoided. A low temperature coefficient (TC) of capacitance «100 PPMI"C), such as a monolithic NPO ceramic multilayer type, preserves low TC of Fa. Figure 6 finds a Co value given Fa. Ro Resistor Ro is used by the IC to generate a VSE/R related current that is multiplied by 2 to produce the 200 /LA ICO control current that sets Fa. The control current TC "bucks" the VeE related tri-wave amplitude across Co to effect a low TC of Fa. Vary Ro to trim Fa, within limits. Raising Fa more than 20% above its untrimmed value by means of decreasing Ra more than 20% is not recommended. Low Ro, and so high control current, risks ICO saturation and poor TC under worst-case conditions. Raising Ro reduces the demodulated signal amplitude from the phase detector; raising Ro by more than a factor of 2 (1 octave) is not recommended. Since lower TC pots are relatively costly, it is recommended that Ra be made up of a 5.6 k fIXed « 100 PPMI"C) resistor with a 2 kO «250 PPMI"C) series pot. CAandRA Components CA and RA control the dynamic characteristics of the transmitter output envelope. Their values are not critical. Use the values given in Figure 5. CA and RA are functions of loaded Tl tank a,.Ro, FOATA, and line impulse noise. Any changes made in CA and RA should be made based on empirical measurements of a CCT on the line. Roughly, CA acts as an ALC pole and RA an ALC zero. Tl At this pOint, the CCT system deSigner may choose to use one of the recommended transformers or to design T1 oneself. Consult "The Coupling Transformer" section to help with the design of T 1 if a new or boost-capable transformer is needed. The recommended 125 kHz transformer functions with an 10 of up to 600 mApp. It is recommended that CCT systems use the recommended transformers, described in Figure 7, for T 1. The 3 fransformers are optimized for use in the ranges of 50 -1 00 kHz, 100200 kHz, and 200-400 kHz with unloaded a's (au) of about 35, and loaded a's (au of about 12. Three secondary taps are supplied with nominal 7.07, 10, and 14.1 turns ratios (N) to drive industrial and residential power line impedances of 3.5, 7, and 140 respectively. All are inexpensive, all have the same pin-outs for easy exchange in a PC board, and all are small - on the order of 10 mm diameter at the base. CQ Tank resonant frequency Fa must be correct to allow passage of transmitter signal to the line. Use Figure 8 to find Co's value. Trimming Fa to equal Fa is done with T I'S trimming slug. The inductance of Tl has a TC of + 150 PPMI"C which may be cancelled by using a -150 PPMI'C cap such as polystyrene. Since circulating current in the tank is 14 ARMS, Co should have a low series resistance (a 1 0 series resistance is too much). Polypropelene caps are excellent, "orange drop" mylars are adequate, while many other mylars are inadequate. A 100V rating is needed for transient protection. !100 . . I!l w ~ 10 z (21r1 "Ll 5DDO ;!: I U 1=18.9, :f 50D z 50 C1 :§ ~U ti z 0.1 ~ co fa II: I 8 0.01 {1 1 10 100 1000 Io-CARRIER CENTER FflEQUENCY (kHzl. 0.5 10 100 lDDD la-CARRIER FREQUEHCY (l FIGURE 11. Output amplifier current and required min. QB h'e versus gain-setting resistor RG Tl/H/6750-13 '" w ~ If l'£ 100 0.1 !: z 0.1 10 Cc-L1NE COUPLING CAPACITANCE IF! '"Iii 10 !i l!l TlIH/6750-11 FIGURE 9. Cc's impedance should be, as a rule-of-thumb, smaller than the lowest expected line impedance lJ ~ iii RG This resistor, in parallel with the internal 10 n resistor, fixes the current gain of the output amplifier, and so the output . current amplitude. Rgure 11 giv~s output current and minimum AC current gain hie for when RG is used to boost output current. 100 1000 10.000 10 -OUTPUT CURRENT ImApp) TlIH/6750-14 as FIGURE 12. Boost transistor power dissipation versus amplifier output current QB as The boost gain transistor must be fast. Double-diffused devices with 50 MHz FT'S work, slower transistors (epi-base types) do not preserve a sinusoidal waveform when Fo is must have a certan minimum hie for high or oscillate. given boost levels, as shown in Rgure 11. Rgure 12 shows the power must dissipate continuously operating with a shorted output. BVCER (R = Rs) must be 60 V or greater and must have adequate SOA for transient survival. as as as ZT Unfortunately, potentially damaging transient energy passes through transformer T 1 onto the Carrier 110 pin (instantaneous power of greater than 1 KW has been measured us- ZT must be used unless some precaution is taken to protect the Carrier 110 pin from line transients or transients caused when stored line energy in Co is discharged by the random phase of power line connection and disconnection. Worst case, Co may discharge a full peak-to-peak line voltage into the tuned circuit. Another way to reduce the need for ZT is by plaCing another magnetic circuit in the signal path that relies on a high, but easily saturated, permeability to couple a primary and secondary winding - a toroidal transformer for example. Toroids cost more than ZT. Use an avalanche diode designed specifically for transient suppression - they have orders of magnitude higher pulse power capability than standard avalanche diodes rated for S12-76 -------------------------------------------------------------,r s::: .... The Transmitter (Continued) III co ZlIIJ Breakdown Voltage Maximum Leakage 44-49V @ 1 rnA f-i!" 1/oLA@40V 300pF@BV I,.H Maximum Clamp Voltage 64.5V@7.BA HlJoo.. 10 kWfor 1 /oLs lJllo. 10,.H 11111 1111 (REA Standard Exponential Pulse) Surge Curr~nt Co) 1m-.. Capacitance Peak Non-Repetitive Pulse Power CD ~~0.1!a 100 70A for 1/120s 0.1 FIGURE 13. Key specifications for a recommended transient suppressor ZT available from General Semiconductor, 2001 West Tenth Place, Tempe, AZ 85281,602-968-3101, part no. SA40A I 10 Co-COUPlING CAPACITANCE (pF) TL/H/6750-15 FIGURE 14. The 60 Hz line rejection of the hlghpass filter made up of Cc and Tl'S line-side winding (neglecting capacitive coupling) equal DC dissipation. Metal oxide varistors have not proven useful because of their inferior clamping coefficient. Specifications for an example minimum diode are given in Figure 13. The Receiver The receiver and transmitter share components Ce, T I, CO, RT, ZT, Co, Ro, and peripheral supply and bias components that are not in need of change for RX mode operation. Values for the balance of the components are now found. Line-Frequency Rejection -4lI To use the ultimate sensitivity of the device, fully 110 dB of 115 V, 60 Hz attenuation is required between the line and the limiter amplifier output. USing the circuit topology of Figure 4, the combined attenuation of the CelT 1 highpass, the tuned transformer, and the bandpass filter attenuation of the limiter amplifier give far more line rejection than the above-stated minimum. However, if some other CCT line coupling circuit is used, line rejection will become important to the system designer. Receiver input power supply rejection (PSRR) and commonmode rejection (CMRR) are one-in-the-same using the supply-referenced signal input of Figure 4. Ripple swings both differential inputs of the Norton amp. equally, while the single-ended input signal swings only the positive input. Overall PSRR consists of the input CMRR (set by the input stage component matching) and the ripple-frequency attenuation of the input amplifier bandpass response that passes carrier frequency but stops low frequencies. A typical 1 % resistor and 1 mV n-p-n mirror offsets give 26 dB of attenuation, the bandpass gives 54 dB 120 Hz attenuation, for an overall BO dB PSRR to allow tens of volts of ripple before impacting ultimate sensitivity. Cc A value was chosen earlier. Knowing Tl'S secondary inductance allows a check of LC line attenuation using Figure 14. TUH/6750-16 !s '~E!III§~!l1 ~ ~ . 0"1111 u § i I d 0.01 I-...L...&..J...L.1.W"---..L...J............. 10 100 1000 IO-CENTER F1IEQUENCY (kHz) TUH/6750-17 FIGURE 15. Given FO, CL is found. Also shown Is the input amplifier'S small signal amplitude response CFandRF These phase-locked loop (PLL) loop filter components remove some of the noise and most of the 2Fo components present in the demodulated differential output voltage signal from the phase detector. They affect the PLL capture range, loop bandwidth, loop overshoot, damping, and capture time. Because the PLL has an inherent loop pole due to the integrator action of the ICO (via Co), the loop pole set by CF and the zerp set by RF gives the loop filter a classical 2nd- CL The Norton input limiter amplifier has a bandpass filter for enhanced receiver selectivity, noise immunity, and line freQuency rejection. The nominal response curve for Fo = 50 kHz is shown in Figure 15. The 300 kHz pole is fixed. The 50 kHz pole is set by CL'S value. After CL is found, the resulting line frequency attenuation is found for the bandpass filter. Use Figure 15 to find a CL value given for Fo. The approximate line frequency attenuation of the bandpass filter may then be found in Figure 16. Figure 15 returns a value for CL 33% larger than nominal, giving a low frequency pole 33% low to allow for component tolerances. S 12-77 ! 70 111111 i 60 mill . n\lJI'- ffi 50 r- -\M'~ Iii ~ "oIH~ I: ! 20 0.01 0.1 1 CL -POLE·smING CAPACITANCE (pF) TUH/6750-18 FIGURE 16. The Norton-Input limiter amplifier bandpass filter line-frequency signal attenuation given CL CM Capacitor CM stores a voltage corresponding to a correction factor required to cancel the phase detector differential output DC offsets. The stored voltage is % of the DC offset plus some bias level of about 2.2 V. A large CM value increases the time required to bias-up the receive path at the beginning of transmission. A large CM does filter well and store its bias voltage long. Because of the initial random charge of CM, the receiver must be given both a positive-going and a negative-going data transition to charge to the proper bias voltage. Therefore, reducing CM'S value to one. that may be charged in less than 1 bit time will not save biasing time and is not recommended. The Transmitter (Continued) [I00om.~11 1 L-~~~~~~~ 10 100 1000 la-CARRIER FREQUENCY (kHz) 100 Tl/H/67S0-19 FIGURE 17. Find CF given Fo. Figure 19 gives the maximum data rate order response. Zero CF and RF give the most stable PLL with the fastest response. Large CF'S with a too-small RF cause PLL loop instability leading to poor capture range and step response or oscillation. Calculation of CF and RF is quite difficult, involving not only the 2nd-order loop step response, but also the PLL non-. dominant poles, the tuned transformer stepped-frequency response, and the RC lowpass step response (for data rates approaching 1 kHz). CF and RF values are best found empirically. Tolerance is not critical. Component values are selected to give the best possible impulse noise rejection while preserving a ± 20% capture range and wide stability margin. Figures 17and 18 give CF and RFvalues versus Fo. Note that CF and RF are a function of data rate only for high data rates and are not plotted against data rate - as one might expect. The reason for this is important to understand if the CCT system designer wishes to find CF and RF empirically. Data signal is, loosely speaking, passed through the PLL loop and is therefore potentially attenuated if the loop bandwidth is on the order of the 3rd harmonic of the data rate, or less. Overall loop bandwidth is held as low as possible for maximum noise rejection while passing the data. Loop bandwidth is roughly proportional to the geometric mean of the unfiltered loop bandwidth and the filter pole set by CF. Therefore, CF is related to data rate. Unfortunately, the loop capture range falls to critically low values when large enough values of CF are used to reduce loop bandwidth down to the 1OD's of Hz range, for low data rates. The obvious way out is to then reduce the unfiltered loop bandwidth. That bandwidth is approximately proportional to the value of Co. For a fixed Fo, unfiltered loop bandwidth reduction requires a larger Co and larger control current. With this chip, changing the control current is not allowed. 50 one is forced to choose a CF/RF combination with some minimum capture range, say ± 20%, that is within some guardband from the point of loop instability. Happily, impulse noise tends to last only fractions of a millisecond so that the lack of low bandwidth loop response with low data rates is not a heavy penalty. As long as there is adequate capture range, the impulse noise filter performs admirably. Note that reducing Fo will reduce the no-filter loop bandwidth, and indeed the maximum data rate falls below the limit set by the RC lowpass filter as Fo falls below 100 kHz. . F:tZI ~ARAl ~. 1-. ~ !iTA RII I 111111 1 10 100 1000 10 -CARRIER FREQUENCY (kHz) TLlH/6750-20 FIGURE 18. Find RF given Fo with FDATA a parameter 20 10 ±10% DATA OUT DUTY CYCLE (50% NOMINAL) I 2 1000 100 10 fa -CARRIER FREQUENCY (kHz) Tl/H/6750-21 FIGURE 19. The maximum data rate versus Fo using loop filter components optimized for max. noise performance while retaining a min. ± 20% capture range (large signal) Use Figure 20 to find CM'S value knowing FOATA, assuming the standard 2 bit receive charge time is desired. The cap. value and TC are not critical, but the capaCitor should have low leakage. The tuned transformer characteristics will affect the demodulated data waveform more than CF and RF at low data rates. Tank Q and off-tuning will affect overshoot during the F5K frequency steps. This is a property of tuned circuits. [,0,000 1 1000 100 10 100 1000 10,000 IoATA-oATA RATE (Hz) TL/H/6750-22 FIGURE 20. Size CM assuming a 2 bit-time receive bias time 512-78 The Transmitter (Continued) CI The impulse noise filter integrator capacitor CI is used to disallow the passage of any pulse shorter than the integrator charge time. That charge time, set to a nominal 'Iz bit time, is the time required for a ± 50 /LA charge current to swing Clover a 2 VSE range. Charge time under worst case conditions must never be greater than a bit time since no signal could then pass. Using a ± 10% capacitor, full junction temperature range, and full specified current range, a maximum nominal charge time of 'Iz bit is recommended. Figure 21 gives CI versus data rate under those conditions. - When evaluating CCT system noise performance on a real power line, it is desirable to vary the signal amplitude to the receiver. This is not easy. An in· line lineproof L-pad is fine except that the line impedance is unknown and variable and so the L-pad will rarely match. Instead, the power output of a chip transmitter may be controlled using the circuit of Figure 23. This circuit controls the ALC. - Monitoring charge current in CM is sometimes important to analyze the offset cancel circuit. Measuring the current by dropping more than a few mV in a series resistor affects operation and is not recommended. A workable method is to make CM small so that it may follow any data signal. Any change in pin 6 voltage shows that the data signal reaching the offset cancel circuit is larger than its nominal ±50 mV voltage window. A CM on the order of 500 pF with a 1 /LA pull-down allows pin 6 to follow the internal signal (with a gain of about 5.6). It is sometimes desirable to place impulse noise on the line. A simple light dimmer with a 100 W light bulb load produces representative impulse noise. Rc The collector pull-up resistor is sized to supply adequate pull-up current drive and speed while preserving adequate output low current drive. ~lDDO oS. ~ - 5 - 2: 100 . 0: tc 10 m I .:s 100 1000 10,000 fDATA-OATA RATE (Hz) TLlH/6750-24 FIGURE 21. Impulse noise filter cap. CI versus FOATA where the charge time Is Yo bit time Breadboarding Tips During CCT system evaluation, some techniques listed below will simplify certain measurements. - Do not allow peak currents of over 1 A through the 5.6 V Zener. In other words, don't short charged capacitors into this low-impedance device. Take care not to momentarily short pins 10 and 11 - damaging the IC. Figure 24 shows some typical Signals beginning with serial data transmitted to received signal. Tuning Procedure First, trim Fa by putting the chip in the TX mode, setting a logical high data input, and measuring the TX high frequency, 1.022 Fa, on the Carrier I/O using these steps: 1. Take pin 17 to a logic low. 2. Take pin 5 to a logic high. 3. Place a counter on pin 10. Use caution when working on this circuit - dangerous line voltages may be present. When evaluating PLL operation, offset cancel circuit operation, and loop filter values, use the filter of Figure 22 to view the demodulated signal minus the 2Fa and noise components. This filter models :the RC lowpass filter on chip. 4. Adjust Ra on pin 18 for F = 1.022Fa. Second, the line transformer is tuned. The chip is placed in the TX mode, a resistive line load is connected to disable the ALC by reducing tank voltage swing below its limit. FSK data is then passed through the tank so that the tank envelope may be adjusted for equal amplitude for high and low data. . PIN 3 • PfN 4 Vo TL/H/6750-25 FIGURE 22. Circuit to view the differential demodulated data signal, minus the noise and 2FO components, conveniently with a single-ended galn-of-ten output S 12-79 ~ a» ....co ::::i ~ r-------------------------------------------------------------------------The Transmitter (Continued) Rgure 25 may be used to find T J, knowing VeE at the operating point in question and VeE at T A = T J = 2S·C. VeE is found by powering up a chip (in RX mode) that has been dissipating zero power at some T A for some time and measuring VeE in under 1" s (for better than S'C accuracy). Altemately, TJ may be calculated using: 1. Take pin S to a logic high. 2. Place a logic-level square wave at or below the receiver's maximum data rate on pin 17. 3. Temporarily place a 330 n resistor across the tank. 4. Place a scope on pin 10. S. Adjust the transformer slug for the lowest envelope modulation. TJ = TA + 9JAPO (1) where 9JA is 7S'C/W for the plastic (N) package using a socket. That 9JA value is for a high confidence level; nominal 9JA for an N package is 60'C/W, lower with good PC board layout. Since Po is a relatively strong function of TJ, an iterative solution process starting with an initial guess for, TJ is used. With the estimated TJ, find the total supply current found in the typical performance characteristics. In lieu of the 330 n resistive load, T 1 may be coupled to the power line to better simulate actual load and tank pull conditions during tank tuning. Alternatively, a passive network representing an average line impedance may be connected to the line side of T 1. The circuit of Figure 23 should then be used to defeat the leveling effect of the ALC. y+ Transmit-To- Receive Switch-Over TIme 75k PIN 7 ---+l~~:URH O.lPF~ TLlH/6750-26 FIGURE 23. A means of transmitter output amplitude " control Is shown Thermal Considerations It is desirable to place the largest possible signal on the power line for maximum range, limited only by the chip power dissipation and maximum junction temperature TJ. The falling output power at elevated TJ allows a more optimal power output- high power at low TJ and lower power"at high TJ for "chip self-protection. However, it is still possible to exceed the maximum T J within the specified ambient temperature limit (TA = 8S'C) under worst case conditions of 100% TX duty cyle, high supply, shorted load, poor PC board layout (with small copper foil area), and an above nominal current part. Under those conditions, a part may dissipate 2140 mW, reaching a TJ = 170"C worst-case (admittedly a rare occurrence). Proper system design includes the measurement or' calculation of TJ max. to guarantee function under worst-case operation. Like all devices with failure modes modeled by the Arrhenius model, the high chip reliability Is further enhanced by keeping the die temperature merCifully below the absolute maximum rating. An important figure-of-merit for a half-duplex CCT link, affecting effective data rate, is the TX-to-RX switch time TTR. Using the recommended component values gives this part a nominal 2 bit-time" (1 bit time = 1 I [2FOATA)) over a wide range of operating conditions, where the receiver requires 1 positive-going and 1 negative-going data transition. T TR cannot be decreased significantly but does increase as noise filtering, especially via CM, is increased. Impulse noise at switch, signals near the limiting sensitivity, poor Fo match between receiver and transmitter because of poor trim or worst-case conditions, and the statistical nature of PLL locking may all contribute to increase T TR to possibly 4 bittimes. TTR is lower when a pair of LM1893's handshake rapidly. The receiver was designed to "remember" the RX-mode DC operating points on CM and CF while in the TX mode. P' ~ ij 1.3 1.2 ~ 1.1 '"" i. 1oO t\. " ~ 0.9 I' ~ m 0.8 iilz15 _-1.87~_ 0.7 I- ~ t\. 0.& -60 -30 0 30 60 90 120 150 180 TJ-JUNCTION TEMPERATURE ('CI TLlH/6750-27 A direct method of measuring operating junction temperature is to measure the VSE voltage on pin 18, which is always available under all operating modes. The graph of FIGURE 25. T J may be found by using the temperature coefficient of pin 18 VeE If VeE Is known at 25'C (1) 10 V/Div. (2) 10 mV/Diy. (3) 400 mY/DiY. (4) 200 mY/DiY. 2 V/Diy. 10 V/Diy. (5) " (6) TLlH/6750-23 FIGURE 24. Oscillogram revealing signals at several Important nodes under weak signal (0.5 mVRMS) conditions with SCR spikes on an otherwise quiet 115 V, 60 Hz power line. The signals are: 1) transmitted data, 2) RX carrier on the tuned transformer, 3) demodulated signal from the PLL, 4) signal after RC lowpass, 5) data at impulse noise filter integrator, and 6) received data. Horizontal scale Is 10 ms per dlv. S 12-80 The Transmitter (Continued) Under noisey worst case conditions, CM will discharge to the point of false operation after 35 bit-times in the TX mode (1400 bit times with no noise and a nominal part, FOATA = 180 Hz). TTR is about 0.8 ms (proportional to the selected FO) plus Y2 bit-time: Total TTR is 3.9 ms plus at 360 Baud. Receive-To-Transmit Switch-Over Time Assume the chip has been in the RX mode and the TX mode is now selected. In less than 10 P.s, full output current is exponentially building tank swing. 50% of full swing is achieved in less than 10 cycles - or under 80 P.5 at 125 kHz. In the same 10 P.s that the output amp went on, the phase detector and loop filter are disconnected and the modulator input is enabled. FSK modulation is produced in 10 /Ls after switching to TX mode. The major components of TTR are described below for a nominal 125 kHz Fo, 180 Hz FOATA, lightly-loaded tank with a 0 of 20, and the circuit of Figure 4. The remote CCT has been operating in the TX mode with a 26.6 Vpp tank swing and is now selected as a receiver. An incoming signal requiring the ultimate receiver sensitivity immediately is placed on the line. First, the tank stored energy at the transmit frequency must decay to a level below the 2.8 mVpp swing caused by the 0.14 mVRMS incoming line signal containing the information to be received. decay time = ...9.... In (Vl) 1TFo Vo 20 1T Power Line Impedance Irrespective of how wide the limits on power line impedance ZL are placed, there are no guarantees. However, since the CCT design requires an estimate of the lowest expected line impedance ZLN encountered for the most efficient transmitter-to-line coupling, line impedance should be measured and ZL limits fixed to a given confidence level. Resonable values for T1 turns ratio, loaded 0, and tank resonant frequency pull Fa may be found to enable a CCT system design that functions with the overwhelming majority of power lines. = I ( 26.6 ) = 0.466 ms (2) x 125 000 n 0.0028 That is 0.47 ms of delay (proportional to liFO and 0). Second, the PLL must acquire the signal, it must lock and settle. Acquisition time is statistical and may take any length of time, but average acquisition time depends on the loop filter components CF and RF and the difference in center frequencies, llFo, of the TX/RX pair. Using the recommended CF and RF (47 nF and 6.2 kn) with a ±4.4% llFo (a ± 100 mV DC offset on CF and RF), lock was measured to take less than 50 cycles of Fo. That is a 0.40 ms delay (proportional to 1/FO). Acquisition is incomplete until the second order PLL loop settles. For the above-mentioned CF and RF, the loop natural frequency FN and damping factor are found to be (reference 1) 2.3 kHz and 1.0 respectively. Settling to. within ± 25 mV of the ± 100 mV DC offset change requires 2.7 periods of FN, or 1.2 ms (a function of CF and RF). Third, the RC lowpass filter introduces a 0.12 ms delay. A limited sampling of ZL was made during the LM1893 design of residential and commercial 115 V 60 Hz power line. Data was also drawn from the research of Nicholson and Malack (reference 2), among others, to produce Figures 26 and 27. All measured impedances are contained within the shaded portions of Figure 27. A nominal 3.5, 7.0 and 14 n ZLN is used throughout the application information with a nominal 45' phase (0' is sometimes used for simplicity). 100 .. § iXL (01 ~ II! BB' 2 J,' ~ ~OkHZ RL(O) 50 ::I -30 -411 -50 - -411 -50 Io-f- --~ MIN I ~ r-~ L 1~~~~~-L~~ 50 100 150 200 250 300 fa-CARRIER FREQUENCY (kHzl TL/H/6750-28 FIGURE 26. Measured line impedance range for residential and commercial 115V, 60 Hz lines IXl (0) !8~ ~ ~ 50 40 ...50 ~50 Rl (0) -20 -3~ MEAN l§ 10 w :z IXL(O) 50 40 30 20 10 0 -10 MAX w :z Fourth, CM must charge up to ±(%)100 = 83 mV depending on the polarity of Fo. Borderline data squaring with zero noise immunity is possible with only ± (%) 50 mV of charging. CM charge current is a linear and asymptotic function approximated by assuming a 50 /LA charge current and a full 83 mV charge voltage. CM charge time is then 1.7 ms (proportional to 1/FoATN. Fifth, the impulse noise filter adds a Y2 bit-time delay 50 40 30 20 10 0 -10 -20 Y2 bit-time for a total of 1.9 bit-times ~~ -BO' TUH/6750-29 ~• :~ 10 0 -10 -20 -30 -40 -50 ~ I- ~ ~300 kH: _56 0 TUH/6750-30 FIGURE 27. Complex-plane plots of measured 115V, 60 Hz line impedance where ZL = RL S 12-81 Rl(O) ri TL/H/6750-31 + jXL Sl = ~ The Transmitter (Continued) I I J,."I' Power Line Attenuation The wiring in most US buildings is a flat 3 conductor cable called Amerflex, BX, or Romex. All referenced line impedances refer to hot-to-neutral impedances with a grounded center conductor. The cable has a 100 .0 characteristic impedance, a 125 kHz quarter-wavelength of 600 m (250 m at . 300. kHz), and a measured 7 dB attenuation for a 50 m run with a 10 .0 termination. Generally, line loads may be treated as lumped impedances. Instrument line cords exhibit about 0.7 pH and 30 pF per meter. Limited tests of CCT link range using this chip show extensive coverage while remaining on one phase of a c;listribution transformer (100's of m) with link failure across transformer phases or through transformers unless coupling networks are utilized. Total line attenuation allowed from full signal to limiting sensitivity is more than 70 dB. Typically, signal .is coupled across transformer phases by parasitic winding capacitance, typically giving 40 dB attenuation between phased 115 V windings: Coupling capacitors must be installed for link operation across phases. Power factor correcting capacitor banks on industrial lines or filter capaCitors across the powt;lr lines of some electronic gear short carrier signal and should be isolated with inductors. Increasing range is sometimes accomplished by electing to install the isolating inductors and coupling capacitors, as well as by electing to use the boost option and by building repeaters. The Coupling Transformer . ~ j,J o N=14.1 ~~ 04 121620 ZL-LiNE IMPEDANCE (111 TLIH/6750-32 FIGURE 28. Impressed line voltage for a given ZL for each of the 3 taps available on the recommended transformers It is known that resonant frequency Fa = Fo and some minimum bandwidth, or maximum Q, will be required to pass signal under full load conditions. L - Ra IIlzLNl' 1- (4) 21TFOQL IZLNI' is the reflected ZLN, QL is the loaded Q, and parallel resistance Ra models 'all transformer losses and sets Qo. Ra IIlzLNl' is found knowing that it absorbs full rated power. _ _loPP[2(-VALC+V+)] Po-loVo- 2,f2 2,f2 (-4.7+V+)lo (5) 4 Po = (18 - 4.7)0.06 = 0200W 4 RalllzLNl' = V02 = (-VALC + V +),f2 = 442.0 (7) Po 10 Ra is found using ZLN and the value for N found when assuming Qu = 35. 1 First, choose the turns ratio N based on an estimated lowest ZL likely encountered, ZLN. Figure 28 shows graphically how N affects line signal. N should be as large as possible to drive ZLN with full signal. If T 1 has an unloaded Q, Qu, of well less than 35, a guess of N somewhat high should be used and later checked for accuracy. The recommended transformers have secondary taps giving a choice' of N=7.07, 10, and 14.1 (nominally) for driving ZLN'S of 14, 7.0, and 3.5.0 respectively (at TJ = 25·C, V+ = 18V, and Qu = 35). QL = BW (0/0 of Fo) The resonating inductance of the tuned primary, L1, is sought. Note that, while standard transformer design gives a transformer self-inductance with an impedance at operating frequency well above load impedance, the tuned transformer requires a low L1 for. adequate Qu and minimum line pull. Result: relatively poor mutual coupling. (3) (8) IZLNI' = N2 ZLN = (7.07)213.9 = 695..0 Ra= a (6) . The compromises might be eliminated by separating the TX output and RX input. An untuned TX coupling transformer with only core coupling (not air-coupled solenoid windings) would employ a high permeability, high magnetic field, low loss, square saturating, toroidal core. The resonant RX path would be isolated from line-pull problems by unilateral amplifier that operates at line voltages with much more than 110 dB of dynamic range. The solution is prohibitively complex and expensive, and is not used. R N_l~-t- where io is in App. at an elevated T J The design arrived at for T 1 is the result of an unhappy compromise - but a workable one. The goals of 1) building T 1 with a stable resonant frequency, Fa, that is little affected by the de-tuning effect of the line impedance ZL, and of 2) building a tightly line-coupled transformer for transmitted carrier with loose coupling for transients, are somewhat mutually exclusive. The tradeoffs are exposed in the following pedagogue for the CCT designer attempting a new boostcapable or different core transformer design. Ll = 21TFOQ N=7.07 ~~ 1 1 1 RalllzLNl' - IZLNI' 1 -695 442 Ra _ 1210 _ 1 .0 Ras=I+Qu2-1+352- = 1210.0 (9) (10) Only QL remains to be foul)d fo calculate Ll' QL is related to the - 3 dB (half-power) bandwidth by 1 (11) An iterative solution is forced where line pull, <1Fa, must be guessed to find QL and Ll. Ll is then used to check the line pull guess; a large error requires a new guess. Try a BW of 8.7% - that is 4.4% for deviation, 1% for TC of Fo, and 3.3% for Fa - giving QL = 11.5. = Ll 442 21T X 125000 x 11.5 = 49.0 II- H Knowing the core inductance per tum, L, and 'Ll, the number of turns is found. T1 = .J!f: = 49.0 = 49 % turns (14) T is normally an integer, but these transformers require so few turns that half-turns are specified, remembering that the remaining % tum is completed on the P.C. board and is loosely coupled. The secondary turns are calculated S 12-82 The Transmitter (Continued) T2 Tl = N= 49.5 7.07 = 7.00 = tivity, there is sometimes good reason to employ it to free the controller from watching for RX signal when no carrier is incoming, or to employ it to reduce the probability of line collisions (when multiple transmitters operate simultaneously to cause one or more transmissions to fail). Unless the detector is heavily filtered or uses a high carrier amplitude threshold, there will be false outputs that force the controller to have Data Out data checking capability just as is required when using no carrier detector. If false triggering is minimized, the probability of line collisions is increased due to the inability to'sense low carrier amplitudes and because of sense delay. The property of the LM1893 to change output state infrequently (although the polarity is undefined) when in the RX mode, even with no incoming carrier, reduces the desire to implement carrier detection and preserves the full ultimate sensitivity. Also, many impulse-noise insensitive transmission schemes, like handshaking, are easily modified to recover from line collisions. (15) 7 turns giving an L2 of 0.98 JJ.H. Note that the recommended 125 kHz transformer mirrors these specifications. The resonating capacitor is 1 Ca = = 33.1 X 10-9 = 33 nF (16) (2'lTFa)2 Ll Line pull AFa was calculated (reference 5) for a ZL magnitude of 140 and up with any phase angle from - 90' to 90'. AFa was 6.4% - well above the 3.3% estimate. Referring to (11), an 11.8% bandwidth is required, forcing Ll to be reduced to reduce Q. That fix was not implemented; some signal attenuation under worst-case drift and AFa is -allowed. Ll is already so small that the 31 gauge winding conducts a % ARMS circulating current. Line Carrier Detection While the addition of a carrier detection circuit (for a mute or squelch function) will only decrease receiver ultimate sensi- 5.6V 62k 10k 5.1M 10k 20k lN914 1,6V 24k TLlH/6750-33 FIGURE 29. A simple carrier amplitude detector with output low when carrier is detected 47 of ~ ~~5~I~k~~~~__~~~____~ LM1B93!PIN 3 PIN 4 2.2 of -Ii -'IoM,.....~__~~....~ 1--''II5'111kl'y-. . 47 of 2,7 1500~F ~O'I~F 80 SPKR PIN 18 10 of 390k AUDIO IN LM1893-1 ~ ±IVp TRANSMlnER !~:::DEV 1,6V TLlH/6750-34 FIGURE 30. A simple linear analog audio transmitter and receiver are shown. The carrier and 1.6V inputs are derived from the carrier detector of Figure 29. The remaining 2 LM339 comparators may be used to build the carrier detector circuit. S 12-83 ~ r-------------------------------------------------------------------------------- m .- ::E .... Line Carrier Detection (Continued) Figure 29 shows a low cost carrier amplitude detection circuit. Pot. R gives a variable threshold; R may be replaced by a fixed resister when the threshold has been chosen. A 150n R gives a 10 mVRMS threshold. The circuit exhibits a 1 ms delay and a 2 ms off delay. Minimize the capacitance of the node including pin 3, especially for operation a high carrier frequencies. An example recommended transmission data packet is shown in Figure 31. The 8 bit 50O/.duty-cycle preamble is long enough to allow receiver biasing with enough bits left over to allow the receiver controller to detect the squarewave that signals the start of a transmission. If there had been no transmission for some time, the receiver would simply need to note that a data transition had occurred and begin its watch for a square-wave. If the receive controller detected the alternating-polarity data square-wave it would then use the sync. bit to signal that the address and data were immediately following. The address data would then be loaded, assuming the fixed format, and tested against its own. If the address was correct, the receiver would then load and store the data. If the address was not correct, either the transmission was not meant for this receiver or noise has fooled the receiver. In the former case, when the transmission was not meant for the receiver, the controller should immediately return to watching the incoming data for its address. If the later case were true, 'then the receive controller would continue to detect edges, tieing itself up by loading false data and being forced to handshake. The square-wave detection and address load and check routines should be fast to minimize the time spent in loops after being false-triggered by noise. If the controller detects an error (a received data packet that does not conform 10 the pre-defined encoding format) it should immediately resume watching the LM1893's Data Out for transmissions. Best receiver operation is obtained when the receive controller has the ability to store all incoming data in a shift register the length of a data packet. The controller would then check the whole packet for proper format. If the test failed, the next bit would be shifted in and the process repeated. Every possible incoming bit sequence would then be checked and dead time reduced. Audio Transmission The LM1893 is designed to allow analog data transmission and reception. Base-band audio-bandwidth signals FM modulate the carrier passing through the tuned transformer (placing a limit on the usable percent modulation) onto the power line to be linearly demodulated by the receiver PLL. Because the receiver data path beyond the phase detector will pass only digital signal, external audio filtering and amplification is required. Figure 30 shows a very simple audiO transmitter and receiver circuit utilizing a carrier detection mute'circuit. A single LM339 quad. comparator may be used to build the carrier detect and mute. Filter bandwidth is held to a minimum to minimize noise, especially line-related correlated noise. Data Encoding At the beginning of a received transmission, the first 0 to 2 , bits may be lost while the chip's receiver settles to the DC bias point required for the given transmitter/receiver pair carrier frequency offset. With proper data encoding, dropped start bits can be tolerated and correct communication can take place. One recommended data encoding scheme is now discussed. Generally, a CCT system consists of many transceivers that normally listen to the line at all times (or during predetermined time windows), waiting for a transmission that directs one or more of the receivers to operate. If any receiver finds its address in the transmitted data packet, further action such as handshaking with the transmitter Is initiated. The receiver might tell the transmitter, via retransmission, that it received this data, waiting for acknowledgement before acting on the received command. Error detecting and correcting codes may be employed throughout. The transmitter must have the capability to retransmit after a time if no response from the receiver is heard - under the assumption that the receiver didn't detect its address because of noise, or that the response was missed because of noise or a line collision. (A line collision happens when more than 1 transmitter operates at one time - causing one or more of the communications to fail). After many re-transmlssions the transmitter might choose to give up. Collision recovery is achieved by waiting some variable amount of time before retransmission, using a random number of bits delay or a delay based on each transmitter's address, since each transceiver has a unique address. A line-synchronous CCT system passing 3 bits per half-cycle may replace the long 8 bit preamble and sync pulse with a 2 bit start-ot-transmission bias preamble. The receive controller might then assume that preamble always starts after bit 1 (the first bit after zero-crossing) so that any data transition at a zero crossing must be the start of the address bits and is tested as such. The line synchronous receiver operates with a Simpler controller than an asynchronous system. Discussion has assumed that the controller has always known when the Data Out is high or low. The controller must sample at the proper time to check the Data Out state. Since noise shows itself as pulse width jitter, symmetrically placed about the no-noise switch-points, optimum Data Out sampling is done in the center of the received data pulse. The receive data path has a time delay that, at low data rates, is dominated by the impulse noise filter integrator and is nominally V. bit (% to 1 bit over tolerance and temperature). At a 2 kHz data rate, an additional delay ot approximately lAo bit is added because of the cumulative delay of . DATA PACKET PREAMBLE aBITS II ADDRESS WORD I DATA WDRD I SYNC BIT TLlH/6750-35 FIGURE 31. A recommended encoded data packet, generated by the transmit controller is shown. The horizontal axis Is time where 1 bit time Is 1I(2FDATA> , S 12-84 -----------------------------------------------------------------------------,r s:: .... Audio Transmission (Continued) the remainder of the receiver. Figure 32 shows that Data Out sampling occurs conveniently at the transmitted data edges for the line synchronous data transmission scheme mentioned in the previous paragraph. With the asynchronous system suggested, the receive controller must sample the Data Out pin often to determine, with several bits of mission Signal, address word, and data word has been built. Handshaking routines are employed that have proven to be very effective - no false operation or AC lines has ever been observed. Covered range, while operating in residential en· virons, is excellent. Operation in commercial and, especially, industrial buildings may be limited because of low line impedance and high noise levels unless the boost option, inductive isolation of capacitors, and capacitive transformer bridging are resorted too. References: 1. Gray, Paul R. and Robert G. Meyer; "Analysis and Design of Integrated Circuits;" John Wiley and Sons; 1977; pp. 575-593; (Phase-Locked Loop tutorial) TL/H/6750-36 FIGURE 32. Operating waveforms of a line· synchronized transceiver pair are shown. The diagram shows how the transmitted data transitions may be used as received data sampling points 2. Nicholson, J.A. and JA Malack; "RF Impedance of Power . Lines and Line Impedance Stabilization Network in Conducted Interference Measurements;" IEEE Transactions on Electromagnetic Compatibility; May 1973; (line impedance data) 3. Southwick, A.A.; "Impedance Characteristics of SinglePhase Power Lines;" Conference Rec.; 1973 IEEE Int. Symp. on Electromagnetic Compatibility; (line impedance data) 4. Hay!, William H. Jr. and Jack E. Kemmerly; "Engineering Circuit Analysis;" McGraw-Hili Books; 1971; pp. 447453; (linear transformer reflected impedance) accuracy, where the square-wave data transitions take place, average their positions assuming a known data rate, and calculate where the center of the data bits are and will continue to be as the address and data are read. A long preamble is helpful. Software that continuously updates the center-of-bit time estimate, as address and data are received, works even better. Alternatively, a coding scheme employing an embedded clock can be used. A line-synchronous system using the LM1893 and COPSTM controller that transmits data packets with a start-of-trans- 5. FCC, "Notice of Proposed Rule Making," Docket 20780, adopted Apr. 14, 1976, (Proposed regulation) 6. Monticelli, Dennis M. and Michael E. Wright; "A Carrier Current Transceiver IC for Data Transmission Over the AC Power Lines;" IEEE J. Solid-State Circuits; vol. SC-17; Dec.1~82; pp.1158-1165; (LM1893 circuit description) 7. Lee, Mitchell; "A New Carrier Current Transceiver IC;" IEEE Trans. on Consumer Electronics; vol. CE-28; Aug. 1982; pp. 409-414; (Application of LM1893) S12-85 m w ~~--------------------------------------------------~ en ~ ....:::E Simplified Schematic ; I II ~!----¥-+------A~~ [~ TUH/6750-37 . S 12-86 ~National ~ Semiconductor LM 1949 Injector Drive Controller General Description Features The LM1949 linear integrated circuit serves as an excellent control of fuel injector drive circuitry in modern au1omotive systems. The IC is designed to control an external power NPN Darlington transistor that drives the high current injector solenoid. The current required to open a solenoid is several times greater than the current necessary to merely hold it open; therefore, the LM1949, by directly sensing the actual solenoid current, initially saturates the driver until the "peak" injector current is four times that of the idle or "holding" current (Figure 3-Figure 7}. This guarantees opening of the injector. The current is then automatically reduced io the sufficient holding level for the duration of the input pulse. In this way, the total power consumed by the sYstem is dramatically reduced. Also, a higher degree of correlation of fuel to the input voltage pulse (or duty cycle) is achieved, since opening and closing delays of the solenoid will be reduced. Normally powered from as-volt ± 10% supply, the IC is typically operable over the entire temperature range (- SsoC to + 12SoC ambient) with supplies as low as 3 volts. This is particularly useful under "cold crank" conditions when the battery voltage may drop low enough to deregulate the Svolt power supply. The LM1949 is available in the plastic mini DIP, (contact factory for other package options). • • • • • • • • • • • • • Low voltage supply (3V-S.SV) 22 mA output drive current No RFI radiation Adaptable to all injector current levels Highly accurate operation TTL/CMOS compatible input logic levels Short circuit protection High impedance input Externally set holding current, IH Internally set peak current (4 X IH) Externally set time-out Can be modified for full switching operation Available in plastic a-pin miniDIP Applications • • • • • Fuel injection Throttle body injection Solenoid controls Air and fluid valves DC motor drives Typical Application Circuit Vim r-I I I --, II __ J JL I r----..., LMl949/LM2949 L, INJECTOR I I I __ 1. Order Number LM1949N NS Package Number NOBS , V,. 1""---, TIMER PEAK TIMER ZI OUTPUT CONTROL LOGIC OUT 0, +_--FSU"'PP""LY"...----oVCC 2N6044 DR EOUIVALENT RT Cc COMP Ri 2n Rs O.1n 2W SENSE INPUT O,4V REF • SENSE GNO D.1V REF PEAK COMPARATOR TL/H/5062-1 FIGURE 1. Typical Application and Test Circuit 812-87 Absolute Maximum Ratings 8V Supply Voltage Power Dissipation (Note 1)- Storage Temperature Range 360mW Input Voltage Range -0.3V to Vee -40"Cto Operating Temperature Range ""65·C to + 150·C Junction Temperature 150·C Lead Temp. (Soldering 10 Seconds) 300·C + 125·C Electrical Characteristics (Vee=5.5V, VIN=2.4V, Tj=25·C, Figure 1, unless otherwise specified.) Symbol lee Parameter Conditions Typ Max Units VIN = OV Pin 8 = OV Pin BOpen 11 2B 16 23 54 26 rnA rnA rnA Input On Level Vee = 5.5V . Vee = 3.0V 1.4 1.2 2.4 1.6 V V Input Off Level Vee = 5.5V Vee = 3.0V Supply Current Off Peak Hold 18 Input Current lOp Output Current Peak Hold Pin 8 = OV Pin 8 Open Output Saturation Voltage 10 rnA, VIN = OV Sense Input Peak Threshold Hold Reference Vee = 4.75V Time-out, t t+RrCT Vs Min 1.0 0.7 1.35 1.15 -25 3 -10 -1.5 -22 V V +25 /LA rnA rnA -5 0.2 0.4 V 350 BB 386 94 415 102 mV mV 90 100 110 % NOTE 1: Thermal resistance from junction to a'l'bient is typically 11 O"C/W for the N·package. Typical Circuit Waveforms 15V _ _ _ _ _ _ _ _ _ _- - , BATTERY VSAn VOLTAGE IOV (VI 5V INPUT PIN I VOLTAGE NORMAL BATTERY VOLTAGE I "COLO CRANK" OR LOW BATTERY VOLTAGE OV IV! 5V OV -.J SENSE INPUT VOLTA~\NIVJ TiMER PIN8 VOLlAGE IVI Vz Qlv~~W~iiUl 15V OV 4A CU~~~W~A' 2A OA TUH/5062-2 S 12-B8 ",.~ Vee R18 m R7~ R3~ R5 o oon ~ m 3 >R28 ~ ~ ~ Q5 ~ " 2~ rn ~ H25 ~ M 3 H2 ~. TIMER en OB Q6 Q3 Q~ .-R33 R19 R36 om) ~Q2B IN 1 ~'II hillJ ~ ~ <0 Rll I R15 R7 ~5 R16 m l t:tr: ll ~59 Ql~ m ~~~ . ~. t~ H , g 01Bj 01~ Qr5~ R12 caMP ~R34 R9 GND 1 ~:c 65 2 j SENSE 6 4 TL/H/5062-3 FIGURE 2. LM1949 Circuit 6t6~W' c» ~ :::& .... r--------------------------------------------------------------------------------Typical Performance Characteristics ...J Supply Current vs Supply Voltage Quiescent Current vs Supply Voltage 12 ! :: VIN= OV T) =25"C I VIN= 2.4V Tj=25"C PE~ liS ,,..",. V a 3.0 I ~:: O!,. ~ .. "- sl.O ~ -off ~ ,- ~ 390 ~385 ........ I 100 ~9O !! = ~ 85 80 " . / V- .99 I I co o I 2 2 3 4 4 2i 0 35 a V~c = 13.0V I I 120 ~K ::0 ~ 15 i IVec = 5.5V H LD v~=aovi r-:::: I _405 3.5 ·80 ·30 0 30 60 90 120 150 JUNCTION TEMPERATURE I" CI =1.5 ~ ~1.0 ... !40 '" 0 " ;;; ON -- OFF ON OFF VCC = 3.OV ~0.5 !! Quiescent Supply Current vs Junction Temperature Sense Input Peak Voltage vs Junction Temperature ) ~2.1 ~C=5.5V ~V_ f-- 5 Input Voltage Thresholds vs Junction Temperature ~2.5 ~ VCC = aD 4 O' L-J....--I--1--l--L--1---1 ·60 ·30 0 30 60 90 120 150 JUNCTION TEMPERATURE I"C) .. 3.0 !:l .s 25 3 ·60 ·30 0 30 60 90 120 150 JUNCTION TEMPERATURE I"CI Output Current vs Junction Temperature .. 30 2 SUPPLY VOLTAGE IVI -- VCC = 5.5V ~ 15 ill SUPPLY VOLTAGE IVI I VIN= OV B ~ ,8 5 o 35r-r-.-'--r-r~-' ~ 10 ~ .98 lie I _14 112 lie 1\ ::195 SUPPLY VOLTAGE IVI T) =25"C Tj =25"C ..=c:. ..... "- Quiescent Supply Current vs Junction Temperature ~ 1.00 o .s ~105 Normalized Timer Function vs Supply Voltage ;:: !; 10 sliD T)=25"C 012345 SUPPLY VOLT~GE IV) ~ 1.0 I .. Sense Input Hold Voltage vs Supply Voltage o 5 ~ Sense Input Peak Voltage vs Supply Voltage z EI.03 2'.97 o ~380 is 1.02 - NOLO ~ 01234587 SUPPLY VOLTAGE IV) .. llj 370 I :::0 !; 10 llj 375 o PEAK- f-- 20 ... !! , ~O.5 i 2 3 4 5 SUPPLY VOLTAGE IVI I ~ ~2.D :25 z ~ i5 I o Tj=25"C .. 30 :::0 HOLJ 0 Input Voltage Thresholds vs Supply Voltage - V ~ 5 2 3 4 5 SUPPLY VOLTAGE IV) :1.5 ~ If '" 10 T)=25"C I / E15 15 ill g ~2.5 !! 20 :::0 /' o o le i:l Output Current vs 35 Supply Voltage ~ 39 co 5"", ~ ;:; 390 ...... ~ Vce = 3.0V ~ 385 !; .!!i 380-- Vee =5.5~1'-.. ~ 375 ~ 370 o ·60 ·30 0 3D 60 90 120 150 JUNCTION TEMPERATURE I"C) 'II , ....... "'- I'. ·60 ·30 0 30 60 90 120 150 JUNCTION TEMPERATURE I"C) TLiH/S062-4 S 12,90 Typical Performance Characteristics Sense Input Hold Voltage vs Junction Temperatllre ! 115.-.---.---r-,.-...---.-"':"" 110 1-+_+____1r-+_+____1-----1 ~ 1051-+_+1____1~+_+____1-----1 ; 1001-+_+____1r-+_+____1-----1 ~ 95f=~,~r=~VC~C=,~5=.5=V~~!::j 't ;= I 04 "--"-"-1"-'''-1''-1'---' ~ 1.031-..---r--t-+--i-----1 I -f---II-+-+-I ! Iii §;= 1.02 r--!I-+, ;:: 1.011--""""'-=-=-1t--!!' _ --;:..-"1 _ ~ 1.00I-oi-V.;;;CC...· "'5.5"'V~::~=-+----, VCC,30V ill ~ .99_ I 90 f--f--i--V1CC 85r-+_+----1~+_+----1-----1 ~ 80~~~~~~~~~ Z 0 30 60 90 120 150 --1 l~ i ~ ·60 ·30 LM1949N Junction Temperature Rise Above Ambient vs Supply Voltage Normalized Timer Function vs Junction Temperature ~ ~ OV ~ (Continued) I I .98 .97 -60 -30 JUNCTION TEMPERATURE I'CI I I I I ! : 0 30 60 90 120 150 JUNCTION TEMPERATURE I CI 61-+-+-+----1-h'"l--I I-- _90% DUTY / ' " 4 2 I CyCLE.... -if "" -"iO% DUTY 0/' CYCLE 0'--..........-'---'---<---'---1..--1 o I 2 3 4 5 SUPPLY VOLTAGE IV) TL/H/5062-5 Application Hints The injector driver integrated circuits were designed to be used in conjunction with an external controller. The LM1949 derives its input signal from either a control oriented processor (COPSTM), microprocessor, or some other system. This input signal, in the form of a square wave with a variable duty cycle and/or variable frequency, is applied to Pin 1. In a typical system, input frequency is proportional to engine RPM. Duty cycle is proportional to the engine load. The circuits discussed are suitable for use in either open or closed loop systems. In closed loop systems, the engine exhaust is monitored and the air-to-fuel mixture is varied (via the duty cycle) to maintain a perfect, or stochiometric, ratio. age and the saturation voltage of 01' The drop across the sense resistor is created by the solenoid current, and when this drop reaches the peak threshold level, typically 385 mV, the IC is tripped from the peak state into the hold state. The IC now behaves more as an op amp and drives 01 within a closed loop system to maintain the hold reference voltage, typically 94 mV, across Rs. Once the injector current drops from the peak level to the hold level, it remains there for the duration of the input signal at Pin 1. This mode of operation is preferable when working with solenoids, since the current required to overcome kinetic and constriction forces is often a factor of four or more times the current necessary to hold the injector open. By holding the injector current at one fourth of the peak current, power dissipation in the solenoids and 01 is reduced by at least the same factor. In the circuit of Figure 1, it was known that the type of injector shown opens when the current exceeds 1.3 amps and closes when the current then falls below 0.3 amps. In order to guarantee injector operation over the life and temperature range of the system, a peak current of approximately 4 amps was chosen. This led to a value of Rs of 0.10. Dividing the peak and hold thresholds by this factor gives peak and hold currents through the solenoid of 3.85 amps and 0.94 amps respectively. INJECTORS Injectors and solenoids are available in a vast array of sizes and characteristics. Therefore, it is necessary to be able to design a drive system to suit each type of solenoid. The purpose of this section is to enable any system designer to use and modify the LM1949 and associated circuitry to meet his/her system speCifications. Fuel injectors can usually be modeled by a simple RL circuit. Figure 3 shows such a model for a typical fuel injector. In actual operation, the value of Ll will depend upon the status of the solenoid. In other words, Ll will change depending Different types of solenoids may require different values of current. The sense resistor Rs may be changed accordingly. An 8-amp peak injector would use Rs equal to .050, etc. Note that for large currents above one amp, IR drops within the component leads or printed circuit board may create substantial errors unless appropriate care is taken. The sense input and sense ground leads (Pins 4 and 5 respectively), should be Kelvin connected to Rs. High current should not be allowed to flow through any part of these traces or connections. An easy solution to this problem on double-sided PC boards (without plated-through holes) is to have the high current trace and sense trace attach to the Rs lead from opposite sides of the board. LI HI ~ 2mH III TUH/5062-6 FIGURE 3_ Model of a Typical Fuel Injector upon whether the solenoid is open or closed. This effect, if pronounced enough, can be a valuable aid in determining the current necessary to open a particular type of injector. The change in inductance manifests itself as a breakpoint in the initial rise of solenoid current. The waveforms on Page 2 at the sense input show this occurring at approximately '130 mV. Thus, the current necessary to overcome_ the constrictive forces of that particular injector is 1.3 amperes. TIMER FUNCTION The purpose of the timer function is to limit the power dissipated by the injector or solenoid under certain conditions. Specifically, when the battery voltage is low due to engine cranking, or just undercharged, there may not be sufficient voltage available for the injector to achieve the peak current. In the Figure 2 waveforms under the low battery condition, the injector·current can be seen to be leveling out at 3 PEAK AND HOLD CURRENTS The peak and hold currents are determined by the value of the sense resistor Rs. The driver IC, when initiated by a logic 1 signal at Pin 1, initially drives Darlington transistor 01 into saturation. The injector current will rise exponentially from zero at a rate dependent upon L1, R1, the battery volt- S 12-91 • .Timer Function (Continued) L INPUT VOLTAGE PIN 1 IVI amps, or 1 amp below the normal threshold. Since continu- ' ous operation at 3 amps may overheat the injectors, the timer function on the IC will force the transition into the hold state after one time constant (the time constant is equal to RrCT). The timer is reset at the end of each input pulse. For systems where the timer function is not needed, it can be disabled by grounding Pin e. For systems where the initial peak state is not required, (i.e., where the solenoid current rises immediately to the hold level), the timer can be used to disable the peak function. This is done by setting the time constant equal to zero, (i:e., Or = a). Leaving RT in place is recommended. The timer will then complete its time-out and disable the peak condition before the solenoid current has had a chance to rise above the hold level. ,The actual range of the timer in injection systems will probably never vary much from the 3.9 milliseconds shown in Figure 1. However, the actual useful range of the timer extends from microseconds to seconds, depending on the component values chosen. The useful range of RT is approximately lk to'240k. The capacitor CT is limited only by stray capacitances for low values and by leakages for large values. The capacitor reset time at the end of each controlier pulse is determined by the supply voltage and the capacitor value. The IC resets the capacitor to an initial voltage (VeE) by discharging it with a current of approximately 15 mAo Thus, a 0.1 J.LF cap is reset In approximately 25 J.Ls. I I I I 4 3 2 1 0 INJECTOR CURRENT (AI I I I 4 3 01 CURRENT (AI 1 0 4 3 2 1 0 ZENER CURRENT (AI 0, COLLECTOR VOLTAGE (VI V VZ· BATT o TLlH/5062-7 COMPENSATION Compensation of the error amplifier provides stability for the circuit during the hold state. Extemal compensation (from Pin 2 to Pin. 3) allows each design to be tailored for the characteristics of the system andlor type of Darlington power device used. In the vast majority of designs, the value or type of the compensation capacitor is not critical. Values of 100 pF to 0.1 J.LF work well with the circuit of Figure 1. The value shown of .01 J.LF (disc) provides a close optimum in choice between' economy, speed, and noise immunity. In some systems, increased phase and gain margin may be acquired by bypassing the collector of 01 to ground with an appropriately rated 0.1 J.LF capacitor. This is, however, rarely necessary. FIGURE 4. Circuit Waveforms amplifier keeps 01 off until the injector current has decayed to the proper value. The disadvantage of this particular co,nfiguration is that the ungrounded zener is more difficult to heat sink if that becomes necessary. The second purpose of Z1 is to provide system transient protection. Automotive systems are susceptible to a vast array of voltage transients on the battery line. Though their duration is usually only milliseconds long, 01 could suffer permanent damage unless buffered by the injector and Z1. This is one reason why a zener is preferred over a clamp diode back to the battery line, the other reason being long decay times. VBm FLYBACK ZENER The purpose of zener Z1 is twofold. Since the load is inductive, a voltage spike is produced at the collector of 01 anytime the injector current is reduced. This occurs at the peakto-hold transition, (when the current is reduced to one fourth of its peak value), and also at the end of each input pulse, (when the current is reduced to zero). The zener provides a current path for the inductive kickback, limiting the voltage spike to the zener value and preventing 01 from damaging voltage levels. Thus, the rated zener voltage at the system, peak current must be less than the guaranteed minimum breakdown of 01. Also, even while Z1 is conducting the majority of the injector current during the peak-to-hold transition (see Figure 4), 01 is operating at the hold current level., This fact is easily overlooked and, as described in the following text, can be corrected if necessary. Since the error amplifier in the IC demands 94 mV across Rs, 01 will be biased to provide exactly that. Thus, the safe operating area (SOA) of 01 must include the hold current with a VeE of Z1 volts. For systems where this is not desired, the zener anode may be reconnected to the top of Rs as shown in Figure 5. Since the voltage across the sense resistor now accurately portrays the injector current at all times, the error S 12-92 --.,I I IL, I INJECTOR I I --.I, Z, Rs TLlH/5062-8 FIGURE 5. Alternate Configuration for Zener Z1 POWER DISSIPATION The power dissipation of the system shown in Figure 1 is dependent upon several external factors, including the frequency and duty cycle of the input waveform to Pin 1. Calculations are made more difficult since there are many discontinuities and breakpoints in the power waveforms of the various components, most notably at the peak-to-hold transition. Some generalizations can be made for normal opera· tion. For example, in a typical cycle' of operation, the majority of dissipation occurs during the hold state. The hold state is usually much longer than the peak state, and in the peak state nearly all power is stored as energy in the magnetic field of the injector, later to be dumped mostly through the zener. While this assumption is less accurate in the case of low battery voltage, it nevertheless gives an unexpectedly accurate set of approximations for general operation. The LM1949 can be easily modified to function as switchers. Accomplished with the circuit of Figures 6 and 7, the only additional components required are two external resistors, RA and Rs. Additionally, the zener needs to be reconnected, as shown, to Rs. The amount of ripple on the hold current is easily controlled by the resistor ratio of RA to Rs. Rs is kept small so that sense input bias current (typically 0.3 mAl has negligible effect on VH. Duty cycle and frequency of oscillation during the hold state are dependent on the injector characteristics, RA, Rs, and the zener voltage as shown in the following equations. Hold Current ::::: ~ Sense Input Hold Voltage (.094V) Vp = Sense Input Peak Voltage (.385V) Minimum Hold Current ::::: R: = Sense Resistor (0.10) Rs 1 Ripple or .0.1 Hold::::: - e Vz e RA Rs V Z = Z l Zener Breakdown Voltage (33V) VSATT = Battery Voltage (14V) L1 R1 n ~Sevz) (VH - The following nomenclature refers to Figure 1. Typical values are given in parentheses: Rs VH ~~ f ::::: RS e RA e VSATT e (1 _ VSATT) o Ll RS Vz Vz fo = Hold State Oscillation Frequency = Injector Inductance (.002H) = Injector Resistance (10) = Duty Cycle of Input Voltage of Pin 1 (0 to 1) VSATT ---v;- Duty Cycle of fo ::::: = Frequency of Input (10Hz to 200Hz) Component Power Dissipation 01 Power Dissipation: Pa ::::: n e (1 - VSATT) e VSAT e VH Vz Rs VSAT = 01 Saturation Volt @ - 1 Amp (1.5V) VH Pa ::::: n e VSATT e Rs Watts Zener Dissipation: Pz ::::: Vz e L1 e f e VS",A",TT::-e_V.!.!H Pz::::: n e ..:.. Rs (V 2 + VH2) p R 2) Watts ((VZ-VSATT) e s VseVz PRA:::::~ Injector Dissipation: VH2 PI ::::: n e Rl e Watts RS2 Sense Resistor: As shown, the power dissipation by 01 in this manner is substantially reduced. Measurements made with a thermocouple on the bench indicated better than a fourfold reduction in power in 01. However, the power dissipation of the zener (which is independent of the zener voltage chosen) is increased over the circuit of Figure 1. VH 2 PR ::::: n RS2 Watts Vp2 PR (worst case) ::::: n RS2 Watts SWITCHING INJECTOR DRIVER CIRCUIT The power dissipation of the system, and especially of 01, can be reduced by employing a switching injector driver circuit. Since the injector load is mainly inductive, transistor 01 can be rapidly switched on and off in a manner similar to switching regulators. The solenoid inductance will naturally integrate the voltage to produce the required injector current, while the power consumed by 01 will be reduced. A note of caution: The large amplitude switching voltages that are present on the injector can and do generate a tremendous amount of radio frequency interference (RFI). Because of this, switching circuits are not recommended. The extra cost of shielding can easily exceed the savings of reduced power. In systems where switching circuits are mandatory, extensive field testing is r!lquired to guarantee that RFI cannot create problems with engine control or entertainment equipment within the vicinity. 5V INPUT VOLTAGE PIN I IV) OV 400mV SENSE INPUT VOLTAGE PIN41mVI OV Vz VBATT 01 COLLECTOR V .A - - VOLTAGE (VI OV TLlH/5Il62-9 FIGURE 7. Switching Waveforms S 12-93 l • v,. JL. PEAK TIMER OUTPUT CORTRDL LIJ&1C +-_..':IIU~PP.l:llY...._ _ _-oVcc OUT Z, 33V 6W ~ 'W IEm al. D.1V REF BEIIIE INPUT HI D.IO 0.4V I'fAK C MPARA H REF %Vi TlIH/5062-10 FIGURE 6. Switching Application Circuit S 12-94 r-------------------------------------------------------------------------, r PRELIMINARY .... == ~National ~ ~ Semiconductor ~ LM1964 Sensor Interface Amplifier General Description The LM1964 is a precision differential amplifier specifically designed for operation in the automotive environment Gain accuracy is guaranteed over the entire automotive temperatUfe range (-40'C to + 125'C) and is factory trimmed prior to package assembly. The input circuitry has been specifically designed to reject common-mode signals as much as 3V below ground on a single positive power supply. This facilitates the use of sensors which are grounded at the engine block while the LM1964 itself is grounded at chassis potential. An external capacitor sets the maximum operating frequency of the amplifier. thereby filtering high frequency transients. Both inputs are protected against accidental shorting to the battery and against load dump transients. The input Impedance is typically 1 MO The output op amp is capable of driving capacitive loads and is fully protected. Also. internal circuitry has been pro- vided to detect open Circuit conditions on either or both inputs and force the output to a "home" position (a ratio of the external reference voltage). Features • Normal circuit operation guaranteed with· inputs up to 3V below ground on a single supply . . • Gain factory trimmed and guaranteed over temperature (±3% of full-scale from -40'C to +125'C) • Low power consumption (typically 1 mAl • Fully protected inputs • Input open circuit detection • Operation guaranteed over the entire automotive temperature range (- 40'C to + 125'C) • Single supply operation SchematiC and Connection Diagrams r---~--.-----1_----._--~~--1_--_1~--_.--------_rl~ r-~--_1~+----+--~._--~----4_----~--~----~--~--~----_r,~ VOUl +Voo ~--~~--~--------------------~--------~----4_------~~----~~D TLlH/6744-1 Dual-In-Llne Package Order Number LM1964N NS Package Number N08E BROUND IfIt'UT- R, INPUT+ Ne Your TLlH/6744-2 Top View S 12-95 Absolute Maximum Ratings Vec Supply Voltage (RVec = 15 kG) VREF Supply Voltage DC Input Voltage (Either Input) ±60V Output Short Circuit Duration -0.3Vto +6V Operating Temperature Range 'r'!definite -40'Cto + 125'C -3Vto +16V Storage Temperature Range - 65'C to + 150'C Input Transients (Note 1) ±60V Lead TemperaturE! (Soldering, 10 Seconds) Electrical Characteristics VCC = Parameter Differential Voltage Gain 12V, VREF = 5V, TA = 25'C unless otherwise noted (Note 2) Conditions VOIF=0.5V -WS:VCMS: + 1V (Note 3) Min Typ Max 4 ..41 4.50 4.59 -2 OS:VOIFS: 1V -1VS:VCMS:+1V 0 OS:VOIFS: 1V -WS:VCMS: +W 0.3 0 3 1.20 45 %/FS MG p.A 1.0 0.3 OS:VOIFS:W -WS:VCMS:+W VIV MG OS:VOIFS: W -3VS:VCMS: + W -40'CS:TAS: + 125'C Inverting Input Bias Current 4.64 %/FS 0.70 OS:VOIFS: 111 -WS:VCMS: + W 4.50 1.20 OS:VOIFS: 1V -3VS:VCMS: + W -40'CS:TA + 125'C Non-Inverting Input Bias Current UnIts Max VIV -3 1.00 Typ 2 OS:VOIFS: 1V -3VS:VCMS: + 1V -40'CS:TAS: + 125'C Differential Input Resistance Min 4.36 VOIF=0.5V, -40'CS:TAS:125'C -3VS:VCMS: +1V Gain Error (Note 5) + 280'C 1.5 p.A 100 OV s: VOIF s: 1V -3VS:VCMS: + W -40'CS:TAS: + 125'C 45 VCC Supply Current Vcc=12V, RVcc=15k 300 500 VREF Supply Current 4.75VS:VREFS:5.5V 0.5 1.0 Common-Mode Voltage Range (Note 4) -40'CS:TAS: + 125'C -1 DC Common-Mode Rejection Ratio Input Referred -1VS:VCMS:+W VOIF=0.5V 50 60 Open Circuit Output Voltage One or Both Inputs Open, -WS:VCMS:+W 0.371 0.397 1 p.A 150 p.A p.A rnA -3 1 V dB 0.423 XVREF 0.365 -3VS:VCMS:+W -40'CS:TAS: + 125'C 0.397 0.429 XVREF rnA Short Circuit Output Current Output Grounded 1.0 2.7 Vec Power Supply Rejection Ratio Vcc=12V, RVec=15K VOIF=0.5V 50 65 dB VREF Power Supply Rejection Ratio VREF= 5VOC . VOIF=0.5V 60 74 dB 5.0 Note 1: This test is performed with a l000n source impedance. Note Z, These parameters are guaranteed and 100% production tested. Note 3: These parameters will be guaranteed but not 100% production tested. Note 4: The LMI964 has been designed to common-mode to .-3V. but production lesting is only performed at ± tv. Note 5: Gain error is given as a percent of full·scale. Full·scale Is defined as tV at the input and 4.SV at the output. S 12-96 Typical Performance Characteristics Inverting Input Bias Current vs Temperature Non-Inverting Input Bias 800 ~urrent vs Temperature 1 ... ...z 1125 ':::> rn 400 ...iii... 200 c .... - :::> l!5 li: I::! 100 a: 600 a: a: .... 150 ....:::>rn 75 ~ 50 !. .!. 25 ~ +' o~~~~~~~~ o -~ -~-~ -25 0 25 50 75 100 125 150 TEMPERATURE ('C) 0.8 ....:::> 0.6 - i :::> 0.4 ~ n ro01251~ e- 15 a: a: G VCC=12V l - I- f-RVcc=15k 0.3 ~ r- ~ 0.2 0.1 -50 -25 0 25 50 75 100 125 150 TEMPERATURE ('C) 0.2 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (OC) Differential Gain vs Temperature Short Circuit Output 4 Current vs Temperature r-. ~ ~ 0.5 .g. 0.4 a: a: III ~ 0 " Vee Supply Current vs Temperature 'I1te~=51.0V !... ...z ~ TEMPERATURE ('C) VREF Supply Current vs 1 Temperature rn "-..;;" 4.700 4.650 z4.600 r--.~ i"""o "- i"""i ~4.550 c ~4.500 ..... m4.4~ is 4.400 .- - .... &.- i-'" 4.350 o 4.300 -50-25 0 25 50 75 100'125150 TEMPERATURE (OC) -50 -25 0 25 50 75 100125 150 TEMPERATURE ('el S 12-97 TLlH/6744-S • Typical Performance Characteristics (Continued) CMRR vs Frequency Voltage Gain vs Frequency 80 1""'T"1"TTT1111""""""""""I"T1 IIIITI1IIT' IIilIT " ITTTTmlII !z 10 iiw 0 '" ~ -10 > 60 lli... IIII 111M! H-+l!JlII!HH-HHI!I--~,CF = 1000'~~ ..." 40 !'" 20 .'" '"lIE 0 -20 -20 10 100 lk 10k lOOk 100 10 FREQUENCY (Hz) VREF Power Supply Rejection ., 80 .iil 60 z ;::: w " 40 ~ .,t '"~ 100 mVrm. CF=O pF ! 60 ~1*~.:tiI E i:l 40 ~Hm~~~+H~~ 20 ~Hm~-tl+HIII--+HRl:Uvelll-e_~1~5 kO ~ 1'0 ~ ., ! 0 If A. -20 10 100 lk 10k lOOk CF-O pF 0 -20 1-+-l+~++lillIIl-I-I Vcc-12 Voe 11111111 ?mill 100 10 FREQUENCY (Hz) lk 10k FREQUENCY (Hz) Test Circuit Vee (9V-16V) VREF (4.7SV-5,SOV) 15k 1 0,01 lOOk Vee Power Supply Rejection 20 :::0 10k 80 UIIIIIII,l,11 VREF=S Voe ~ 0 lk FREQUENCY (Hz) ~F±= 7 8 '~ NON'INVERTIN~.2 _ INPUT ~ ~ /','7 I-- V I 6rJt RF S 12-98 GNO J.. ~F Vour 5 Av=4,5 INVERTIN,~...!. INPUT - 1 - 0,01 ;J; r l00 pF TLlH/6744-5 lOOk TLlH/6744-4 ,-------------------------------------------------------------ir ~National PRELIMINARY ~ Semiconductor U1 LM2005 20-Watt Automotive Power Amplifier General Description The LM2005 is a dual high power amplifier, designed to deliver optimum performance and reliability for automotive applications. High current capability (3.5A) enables the device to deliver lOW/channel into 20 (LM2005S), or 20W bridged monaural (LM2005M) into 40, with low distortion. Wide supply range (8V-18V) Externally programmable gain With or without bootstrap Low distortion Low noise Connection Diagram • • • • • • • • • • Features • • • • • High peak current capability Po=20W bridge High voltage protection AC and DC output short circuit protection to ground or across load Thermal protection Inductive load protection Accidental open ground protection Immunity to 40V power supply transients 3'C/W device dissipation Pin for pin compatible with TDA2005 Typical Application A3 120k Plastic Package TAB CONNECTEO TO PIN 6 11 10 o 9 B 7 6 5 4 3 2 1 BOOTSTRAP 1 OUTPUT 1 + C6 +Vs 220~F A2 lk OUTPUT2 BOOTSTRAP 2 GNO INPUT +2 INPUT -2 BYPASS INPUT -1 INPUT +1 AD AD 1 1 AS TOP VIEW 12 TLlH/5129-1 Order Number LM2005T See NS Package T11A 3: o o I\) Al 12 TL/H/5129-2 FIGURE 1. 20W Bridge Amplifier Application and Test Circuit S 12-99 Absolute Maximum Ratings Operating Supply Voltage 18V DC Supply Voltage (Note 1) 28V Peak Supply Voltage (50 ms) 40V - Power Dissipation 30W -40·Cto +85·C Operating Temperature -SO·Cto -I; 150·C Storage Temperature Lead Temp. (Soldering, 10 seconds) 300·C Output Current Repetitive (Note 2) 3.5A Non-Repetitive 4.5A Electrical Characteristics Vs= 14.4V, RL =20 dual, RL =4.0 bridge, TTAS=25·C, frequency = 1 kHz unless otherwise specified Parameter Conditions Supply Voltage Range Min Quiescent Supply Current Po=OW, Dual Mode DC Output Level (Pins 8 and 10) 6.6 Output Vos (Between Pins 8 and 10) LM2005M only Output Power THD=10% RL=40Dual 20 Dual 40 Bridge 1.60 Dual 3.20 Bridge , Distortion RL =40, Po=2W Dual RL =40, Po=4W"Bridge RL =1.60, Po=4WDual RL = 3.20, Po = 8W Bridge Power Supply Rejection Ratio (Output Referred) Rs=OO, f=100 Hz Dual Bridge Noise (Note 3) Equivalent Input Noise Rs = 00, BW = 20-20 kHz Channel Separation Output Referred Vo = 4 Vrms, LM2005S only Input Impedance Pins 5 and 1 (Non-Inverting) 6 9 18 10 20 Units 18 V 70 120 mA 7.2 7.8 V 150 mV 6.5 10 20 11 22 35 45 W W/Ch W 1 1 1 1 45 55 1.5 70 W/Ch W/Ch 48 -3dB Dual Bridge -3dB Dual Bridge 15 20 Note 1: Intemal voltage IlmH. Note 2: Internal current limit Note 3: Not production tested, Not used 10 calculate AQL S 12-100 % % % % dB dB 5 /J-V 60 dB 200 kO 90 Voltage Gain (Closed Loop) High Frequency Roll Off Max 0.2 0.3 0.3 0.3 Voltage Gain (Open Loop) Low Frequency Roll Off Typ 8 50 dB ' 51 dB 50 40 Hz Hz kHz kHz Equivalent Schematic 1"'-" -*- ~ ~ ~I' h • S 12-101 U) r---------------------------------------~------~----------------------------~-- ~ ~ External Components· (FlIJure 2) Components 1. R1, R2 R5,R4 Comments Sets voltage gain, R' Av'" 1 + R1 for one channel, Components 5.C4,C5 Comments Bootstrap capaCitors, used to increase drive to output stage. 6.C3 Improves power supply rejection. Increasing C3 increases turn-on delay (approximately 2 ms per p.F). 7.C2,C6 Inverting input DC decouple. Low frequency pole: R' Av= 1 + R5 for the other. Where R' is the equivalent resistance of R2 In parallel with an internal 1Ok resistor: 1 FL2 21TZ(inverting)C2 Z (inverting):::: 10 kO. R'= 10k- R2. R2+10k If R2< <10k, then 8·Cc R2 Av""l+ Rl ' 2.R3 Output coupling capacitor. Isolates pins 10 and 8 from load. Low frequency pole; 1 FL3=-----· 21TRLCC . Adjusts output symmetry for maximum power output. 3. Ro,Co Works to stabilize internal output stage. Necessary for stability. Co should be ceramic disc or equivalently good high frequency capacitor. 4.Cl,C9 Input coupling capacitor. Low frequency pole set by Power supply filtering. 1 FL1 . 21TZ (non-inverting) Cl Decreasing capacitor value will also increase noise. Typical Applications (Continued) R3 120k F-__------~~-------.--------_e--~-~ + CS T 100 ,... ":" C9 2.2,... 5 + C6 C2 220,... R1 3.3 ~'hN + 220"F + Cc ~ 200"F R5 3.3 RL 20 TUH/5129-4 FIGURE 2. lOWIChannel Stereo Amplifier Application and Test Circuit S 12-102 -----------------------------------------------------------------------------,~ ..,a:::: Typical Performance Characteristics Device Dissipation vs Ambient Temperature 32 !: z 5! lC !ll ...'"a ~co 80 INFINITE HEAT SINK 28 1111""'- ..... f""'oo 2"d/W~EAT~ "1. .i. :1' "j ...... 24 20 16 ."C/W HEAT SINK""'- 12 ...~ ..!!!'" .... r-... ::> ... 60 II: ::> '" 1 1 1 1 10 20 30 40 so 60 70 80 TA - AM8IENT TEMPERATURE I"C) i I!. 16 ~~ii!'::~ ~ f-: 4 Ii! o ~~ .""'" 16 '" 12 I io"": AV-50dB 1=1 kHz ~L=~ .~;o- ~iIIi jO" §: ~~ z '" III ~ '" '" ~ ~ « 1 10 POWER OUTPUT IW) z .! S . . z ~ II: III z l'i :z: 4 rrr- 50 40 30 10 o 10 E ::> 2 i H-I+IfIIlI.-+-1+ o L..L..........LIII8_... 0.01 100 20 10 0 0.1 1 10 POWER OUTPUT IW/CHANNEL) 32 I! :J' I" BRIDGE 1=1 kHz A¥=50dB THD=10% RL=40 24 20 16 ~ 12 10k • Power Output vs Supply Voltage 28 i 100 lk FREOUENCY 1Hz) 10 WITH BOOTSTRAP " ~ ~ " I' ~ I : ~~ ~~iiOUiiiL CJN=4.7~ 100 lk FREOUENCY 1Hz) 40 30 '" Av=50 dB Vo=4 Vrm. RL=40 CBYPASS =10 ~F 20 Ul '" H-ItHlHl-+++I;;;';'':::;-tt r- 60 RL=401 50 '" ~ Channel Separation (Referred to the Output) vs Frequency 70 ~ 1,J,o ID 60 :!!. ~ r- 11,1 Power Supply Rejection Ratio (Referred to the 70 Output) va Frequency i ~ ~ ~ ~ 20 50 100 200 SOO lk 2k 5k 10k 20k FREOUENCY (Hz) §: r- ~ o " ~ SUI'PLYVOLTAGEIV) u Total Harmonic Distortion iii IJ :!' ro 1 I VS=IUV Av=50 d8 Po=2.5W 0.4 E 18 Total tiarmonlc Distortion vs Frequency (Dual) -' 0.2 8 r- 10 12 14 16 SUI'PLY VOLTAGE IV) 0.6 fil RL=20 B 0.8 ;:: l1li o Av=50dB 1=1 kHz RL=40 Vs=14.4V 0.1 1.0 .. 1 1 1 1 81012141618 SUPPlY VOLTAGE IV) o~ o " ~~ ...,.- Total Harmonic Distortion vs Power Output (Bridge) 10 1 RL=40 I RL=40 ;0- - ~ :;... ...... ~ iIJii: ..... ".¥ ~I.o!!;;;o « u ~ SUPPLY VOLTAGE IV) I" f' ::> 20 11_ 1 1 1 rL-l.~'J " i! 20 ro J j 40 ... ...co 20 , 60 Output Swing vs Supply Voltage ~I' I ~ ~ '" > t:; 8 1 RL=20 RL=3.20 ~~ L. 12 -- 80 Itco Power Output vs Supply Voltage DUAL 1= 1kHz , ~ ~ i I-- P"'" 40 o o 20 - Output Offset Voltage vs 100 Supply Voltage ~ 8"C(W JEATI s , - o Q Supply Current vs Supply Voltage I o 10k 8 I « ~ SUPPLY VOLTAGE IV) ro u " TLlH/5129-5 512-103 Application Hints The high current capability of the LM2005 allows it to continuously endure either AC or DC short circuit to the output with a maximum supply voltage of 16V. This will protect the loudspeaker in a. bridge mode, when a DC short to the output occurs to one side of the speaker. The device will prevent the speaker from destruction by reducing the DC across the load (bridge mode) ·to typically less than 2 Voc(Vs= 14.4V, RL =40.), by an internal" current pullback method. The LM2005 can withstand a constant 28 Voc on the supply with no damage (maximum operating voltage is 18Y). The device is also protected from load dump or dangerous transients up to 40V for 50 ms (every 1000 ms) on the supply with no damage. Protection diodes protect the device driving inductive loads, during which the load can generate voltages greater than supply or less than ground levels. The protection diodes will clamp these transients to a safe VeE above and below the rail. The bridge configuration in Figure 3 is designed for applications requiring minimal printed circuit board area and maximum cost effectiveness. The circuit will function with the elimination of bootstrap components R3, C4 and C5 (refer to Figure 1). This will result in 'Iess output power by decreasing output voltage swing to the load. By using internal feedback' resistors (typically 10 kO), feedback components R2, R3 and C2 (Figure 1) may be omitted where closed loop . voltage gain accuracy is, not critical. The net result is a stable, cost effective circuit that will satisfy many application needs. ~~~------------~------__ v+ + l 100 ,.F 0.01 ,.F 150 150 ~ TUH/5129-6 . Av=41.5 dB @ 1 kHz FIGURE 3. Minimal Component Application Circuit Component Side (Scale 2:1) , TUH/5129-7 FIGURE 4. Printed Circuit Board Layout for LM2005 S 12-104 .-------------------------------------------------------------------------.r ~National PRELIMINARY ~ Semiconductor General Description The LM2879 is a monolithic dual power amplifier which offers high quality performance for stereo phonographs, tape players, recorders, AM-FM stereo receivers, etc. The LM2879 will deliver 9W/channel to an 8n load. The amplifier is designed to operate with a minimum of external components and contains an internal bias regulator to bias each amplifier. Device overload protection consists of both internal current limit and thermal shutdown. The LM2879 is an LM379 in an improved power package. For more information, see AN-125. Features Avo typical 90 dB 9W per channel (typical) 70 dB ripple rejection 70 dB channel separation Internal stabilization Connection Diagram • • • • Self centered biasing 3 Mn input impedance Internal current limiting Internal thermal protection Applications • • • • • • • • • • Multi-channel audio systems Tape recorders and players Movie projectors Automotive systems Stereo phonographs Bridge output stages AM-FM radio receivers Intercoms Servo amplifiers Instrument systems Test Circuit Stereo Amplifier ,,.. Plastic Package 0 co 15 11 10 9 8 7 6 5 4 3 2 1 ~ CD LM2879 Dual 9-Watt Audio Amplifier • • • • • 3: r- V' OUTPUT 2 GND INPUT 2 FEEDBACK 2 GND FEEDBACK 1 INPUT 1 GND OUTPUT 1 BIAS + ,+5"' 11 Oo V' -, 80 INPUT1--1 0.1#1 'III' + c. ,+250"' ,,.. I, I ,INPUTZ--J TOP VIEW TL/H/5291-1 O.1#4F Order Number LM2879 See NS Package T11A TUH/5291-2 S 12-105 Absolute Maximum Ratings Supply Voltage Input Voltage Operating Temperature (Note 1) -65'Cto + 150'C 35V Storage Temperature OV - VSUPPLY O'Cto + 70'C Junction Temperature 150'C Lead Temp. (Soldering. 10 seconds) 300'C Electrical Characteristics Vs = 28V. TTAB25'C. Test Circ\lit of Figure 1. unless otherwise specified. Parameter Conditions Total Supply Current POUT = OW POUT=2W/Channel Min DC Output Level Typ Max Units 12 460 65 mA mA 14 V 10 Supply Voltage Output Power THD=5% THD=10% THO POUT= 1W/Channel. f= 1 kHz POUT=4W/Channel. f= 1 kHz 8 9 8 W W 0.05 0.04 Input Offset Voltage ±15 Input Bias Current 100 Input Impedance, V 34 % % 1 mV nA 3 Open Loop Gain Rs=O!l. Channel Separation f= 1 kHZ Ripple Rejection f= 120 Hz. CF=250,:tF M!l. 50 90 dB 70 dB 70 dB Current Limit 1:5 A SlewR~te 1.4 V//Jos 3 /JoVrms Equivalent Input Noise Voltage, Rs=600!l.. 100 Hz-10 kHz Note 1: For operation at ambient temperatures greater than 2S'C the LM2879 must be derated based on a maximum ISO'C junction temperature. Thermal ,"slstence, junction to case, is 3'C/W. Thermal resistance, case to ambient, is 40'C/W. Typical Performance Characteristics Device Dissipation vs 'Ambient Temperature . .. ~ z Ii e, !!! ~ m 22 20 18 16 14 12 10 8 6 4 2 100 INFINITE HEAT SINK I I " WC/W HEAT SINK I I I I 4'C/W HEAT SINK ....... -- --"'" 0 10 20 30 40 50 60 70 80 TA-AM8IENT TEMPERATURE ('CI Power DIssipation vs Power Output Open Loop Gain i ~ 80 60 !ll a C> > I ~ 40 11 " . .. i!~ 9 ~~ =z 7 z'" " ..z 5~ w,. !'!:z: ill'" .,!il 20 0 100 3~D 10 (- 28V lOOk lk 10k I-FREQUENCY (Hz) 1M BI6 5 4 3 2 1 0 26V 1.00>' ~"'" )i4% 24V r.... 'T r~...r ~2V ~~~2OV ~ lBV 6V 4V' I THD 1-+ I 1=1 kHz RL=BO Av=50 0 1 2 3 4 5.~, 7 8 9 10 POWER OUTPUT (WI CHANNEL) TLlH/5291-3 S 12-106 Typical Performance Characteristi~s BOO 700 ffi~ ~ 600 ~~ ./ , 500 u'" .. ~m a.z 400 a.z ,."':Z: r 300 wU ~i= 200 .. 15'" ","' I 100 o i\v=50, Vs=28V, RL=BO, 1=1 kHz o 80 I I rJlJ ~5 60 20, ~F, &3~ 50 ~PI Ul'" ",>40 a.'" a.'" ,.~ 30 "'w ~a: 20 ~ 10 I _ !: Z ~ !ri! :3 ~ 1 0.5 0.2 0.1 0.05 0.02 0.01 Av=50 RL=80 VCC=2r V ~ ~~=r ~ I'JI...I ~ ~ 10.0 5.0 2.0 .. 0; 0.5 Z 0.2 I 0.1 ~ 0.05 POIO'~P i 60 :z 50 . ill :z: S 0.02 100 lk 10k FREQUENCY (Hz) '\'" ~ ", ~ z '" ii '" >,.~ ~ ,/ . ~ ""!'" Avt51 1=1 kHz RL=BO 20 15 V ./ 10 " /' 10 15 20 25 V SUPPLY IV) 30 35 10 [ Ii: 1.0 . e RL=BIl 9 THO=10% " ill Z Z !Ji0; :z: U U '" Z ~ 0.1 !; := 0.01 ~ !ri! :z: lOOk Power Output/Channel vs Supply Voltage 10 :z :E lk 10k FREQUENCY (Hz) o 20 50 100 200 500 lk 2k 5k 10k 20k FREQUENCY (Hz) Total Harmonic Distortion vs Power Output .. 100 Output Swing vs Vs ~ i\v=20~ ~ ~ RL=80 10 25 ~ III I II VOUT=4 Vrrns lOOk RL=811 Po=0.5W Vcc=2BV IN=b.JoWl' CBYPASS = 50 pF Vcc=28V Av=50 40 0.01 20 50 100 200 500 lk 2k 5k 10k 20k FREQUENCY (Hz) !E ~ i3 220V, i\v=50 C VALUES ARE RIPPLE FILTER ~ 1.0 ~,.. Tl"IiI...'- !« Total Harmonic Distortion vs Frequency !E I ~lrl 70 e Js 10 Total Harmonic Distortion vs Frequency ~ II o 1 '" :z 1 pF OUTPUT POWER (WI CHANNEL) 10 BO 2~01J 70 "' ~ ~ffi / Channel Separation (Referred to the Output) Frequency Supply Rejection vs Frequency Supply Current vs Output Power !!i (Continued) '" ...j! 0.01 ~ ~ 0.1 1.0 POWER OUT (W/CHANNEL) o 10 "'" 6 B 10 12 14 16 lB 20 22 24 26 28 SUPPLY VOLTAGE (V) TLlH/5291-4 S 12-107 Schematic Diagram TUH/5291-5 S 12-108 Typical Applications Two-Phase Motor Drive o C2 0.1~ Cl Rl rO.l~ 27k ':' 5 R8 lOOk R3 27k 84 R7 2700 10k C3 0.04~T TL/H/5291-6 12W Bridge Amplifier 0.1 pi' -tI ....__....__________-, SIGNAl _ _ _ INPUT V+ =28V 1M 0.47~ 10k TL/H/5291-7 S 12-109 Typical Applications (Continued) Simple Stereo Amplifier with Bass Boost 0.02,.,. 1. r- 2k -, 11 0 y. + T S "" III ':' INPUTI-1 CF 1I0Il 0.1,.,. + 1'250~F INPUT2-1 CF 0.1,.,. 8 811 L 2k + T lOOk II I I I lOOk lOOk S "" TUHI5291-8 Power Op Amp (Using Split Supplies) lOOk y+ 10k INPUT .......WI,.-4~::.t y- 'I 0.1,.,. TLlHI5291-9 S 12-110 + T 100PF TLlH/5291-10 Frequency Response of Bass Tone Control . .. i 65 :!!. ~ 55 45 ~ l5 :z 35 ~ 25 I I ......,...,. C~~~:~ ~ESPONSE- 1 - FLAT g t5 ~ 15 I I I ~:~~UM_ f - - .L 4AXIMJM- 1 - CUT f-- - 'ES~NfE- f - - """'" 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) TL/H/5291-11 S 12-111 m r----------------------------------------------------------------------------, !:2 J?'A National .... . ~ Semiconductor PRELIMINARY LM2889 TV Video Modulator General Description Features The LM2889 is designed to interface audio and video signals to the antenna terminals of a TV reCl'liver. It consists of a sound subcarrier oscillator and FM modulator, video clamp, and AF oscillators and modulators for two low-VHF channels. The LM2889 allows video information from VTAs, video disk systems, games, test equipment, or similar sources to be displayed on black and white or color TV receivers. • Pin for pin compatible with LM1889 AF section • Low distortion FM sound modulator (less than 1% THO) • Video clamp for AC-coupled video • Low sound oscillator harmonic levels • 10V to 16V supply operation • DC channel switching • Excellent oscillator stability • Low intermodulation products Block and Connection Diagrams (Dual-In-Line Package) AUDIO 14 SOUND SUPPlY 1 INPUT VlDEB 2 CLAMP GROUND 3 I 4 eH I ..-....._ _ _~:.:.:.11 =~~ Order Number LM2889N See NS Package Number N14A TANK 10 VlDEB REFERENCE 9 CHA OUTPUT I TANN CHAI B CHI OUTPUT TOP VIEW DC Test Circuit 14 13 VA + Is -.--Vs 12V ~ 12 Uk 11 }CHI }CHA 1k 10 9 1k 8 1k 5.1k '::" "*" v. 0.1"F TLlH/5079-1 S 12·112 Absolute Maximum Ratings Supply Voltage Power Dissipation Package (Note 1) Operating Temperature Range Storage Temperature Range 18Voc 700mW 0·Ct070·C -55·Cto + 1500C (V14-V13) Max (V12-V8) Max (V12-V9) Max Lead Temperature (Soldering, 10 seconds) ± 5V oc 7Voe 7Voe 300·C DC Electrical Characteristics (DC test circuit, all switches normally pos. 1, Vs=12V, VA=2V, VB=Ve=10V) Parameter Conditions Supply Current Is Sound Oscillator Current al13 Change VA from - 2V to + 2V Min Typ Max Units 10 16 25 mA 0.2 0.35 .0.6 mA Sound Oscillator Zener Current 113 0.85 rnA 0.9 mA Sound Modulator Audio Current al13 Change SW2 from Pos. 1 to Pos. 2 Video Clamp Voltage V2 Unloaded Loaded SW3Pos.3 5.25 5.1 SW3Pos.2 20 Video Clamp Capacitor Discharge Current (Vs-V2)11 05 5.0 Ch. A Oscillator OFF Voltage, V6, V7 SW1 Pos.2 Ch. A Oscillator Current Level 17 VB=10V, Ve=11V 5.45 J-LA 2 2.5 - Ch. B Oscillator OFF Voltage V4, V5 Voc Voe mVoe 3.5 5.0 2 mA mVoe Ch. B Oscillator Current Level 14 SW1 Pos. 2, VB= 10V, Ve= 11V 2.5 3.5 5.0 mA Ch. A Modulator Conversion Ratio aV9/(V11-V10) Measure a V9 by Changing from VB= 10V, Ve= 11V, to VB=11V, Ve= 10V; Divide byV11-V10 0.3 0.50 0.75 VIV Ch. B Modulator Conversion Ratio aV8/(V11-V10) SW1 Pos. 2, Measure a V8 by Changing from VB= 10V, Ve= 11V, to VB= 11V, Ve= 10V; Divide by V11-V10 0.3 0.50 0.75 VIV AC Electrical Characteristics (AC test circuit, Vs=12V) Parameter Conditions Sound Carrier Oscillator Level (V13) Min Typ Max Units 3.4- Vp-p aft a VIN, SW1 Pos. 2, Change VIN from 1.4V to 1.0V, Measure Af at Pin 13, Divide as Shown 250 Hz/mV Ch.3 RF Oscillator Level v6, v7 Ch. Sw. Pos. 3, f=61.25 MHz, Use FETProbe 550 mVp-p Ch. 4 RF Oscillator Level, v4, v5, Ch. Sw. Pos. 4, f= 67.25 MHz, Use FET Probe 550 mVp-p Sound Modulator Deviation RF Modulator Conversion Gain vOUT/(V10-V11) Ch. Sw. Pos. 3, f=61.25 MHz. (Note 2) 10 mVrmslV Nole 1: For operation in ambient temperatures above 25'C, the device must be derated based on a 15O"C maximum junction temperature and a thermal resistance of 8O'C/W junction to ambient. Nole 2: Conversion gain shown is measured with 750 input RF meter which makes the AC RF output load 37.50. S 12-113 m ~ :i Design Characteristics (AC test circuit, Vs=12V) Parameter Typ Units Sound Modulator Audio THD at ± 25 kHz Deviation, VIN must be 1 kHz Source, Demodulate as Shown in Figure 1 0.8 % .... Sound Modulator Input Impedance (Pin 1) 1.5 kO Sound Modulator Bandwidth 100 kHz Oscillator Supply Dependence, Sound Carrier, RF See Curves Oscillator Temperature Dependence (lC Only) Sound Carrier RF -15 -50 ppml"C ppml"C RF Oscillator Maximum 'Operating Frequency (Temperature Stability Degraded) 100 MHz 30 dB 5 3 % degrees RF Modulator Carrier Suppression (Adjust Video Bias for Minimum RF Carrier at VOUT and Reference to VOUT with 3V Offset at Pins 10 and 11, See Applications Information, RF Modulation Section) 3.58 MHz Differential Gain Differential Phase 2.5V Vp-p Video, 87.5% Mod Output Harmonics below RF Carrier 2nd,3rd 4th and Above -12 -20 Input Impedance, Pin 10, Pin 11 . dB dB 1 MO//2pF AC Test Circuit 1 SWl 14 ...I...-;r_ 0.01 pF r------- 1 I r-y I I~I --f' ~1~3_ _ _ _+-+!I ..... -'±"lpF IL T VIDEO r I TOKO - 5~ pF _____ KAC·K5674HM , ~ 7.5k INPUT 12 -L TO.oolPF 240 4 21/2~1 TURNS)" J :r CH ).",..CH4 _ SWI--" - CH3 100 240'~ 11 -1., VIDEO ....,-68 pF 1 5 10 ~ O.001pF 6 240 21/~~j11.. TURNS 240 +~ '1 T 75PF 75 7 TO.001PF. POUT ~-----------------------------4-+-~V 10pF-'-'- T S12-114 TLlH/5079-2 --------------------------------------------------------------------~------'r s::: 5 pF Test Circuit I\) co 16 TO PIN 13-1 OF LM2889 m 51 10k 15 0.01 ~F 3 14 O.OI~F ":" 13 LM30B9 12 AU~~~ _ _...."7".5,,k,.6~ T fl~I_________~_~V O.Ol~F 1-'1;;..0_ _ _...,",*"0.1# _ TO 7 - PIN 10 9.1k -, O.IBmH I I I 51 pF I I TOKO I IL ______ K5674:.JI TL/H/5079-3 FIGURE 1,4.5 MHz Sound FM Demodulator Typical Performance Characteristics (Refer to AC test circuit unless noted) ! Sound Carrier Oscillator . Supply Dependence 12 (fo = 4.5 MHz, Pin 1 Open) ~ 10 ~ ~ "... 8 I 5.! 3.6V) Mute function (pin 14) 1500mW 12V 1 Vrms -.7t05Vp Operating ambient temperature range Storage temperature range Lead temp. (Soldering 10 seconds) O"t070'C -55' to + 150'C 300'C Parameters Guaranteed By Electrical Testing (Test ckt., TA=25'C, Vs=3.6V, fo=10.7 MHz, Af= ±3 KHz, fMOO= 1 KHz, 500 source) Parameter Measure Supply Voltage Range Vs Supply Current Squelch Off Squelch On Is Is Min· Typ Max Units 2.0 3.6 9.0 V 2.8 3.6 5.0 6.0 mA mA 2.0 6.0 p.V RF Input for -3 dB Limiting RF Input Recovered Audio at Audio Output Audio Output 200 350 Audio Out DC Vg 1.2 1.5 OpAmpGain Vll lv lN 40 55 dB Op amp Output DC Vl0 0.4 0.7 Voc Op Amp Input Bias Current (Vl0- Vll)/1MO Scan voltage Pin 12 high (2V) Pin 12 Low (OV) V13 V13 Mute Switch Impedance, Pin 12 OV Switch S1' from pos.1 to pos.2 3.0 AV14/AI14 mVRMS 1.8 Voc 20 75 nA 0 3.4 0.5 Voc Voc 15 30 ohms Design Parameters Not Tested or Guaranteed Typ Mixer Conversion Gain (Note 2.) 46 VIV Mixer Input Resistance 3.6 Kohm Mixer Input CapaCitance 2.2 pF Detector output impedance 500 ohm Trigger Hysterisis 100 mV Mute off impedance (measure pin 14 with pin 12 @ 2V) 10 Mohm Squelch threshold .65 Voc Detector center frequency slope 0.15 V/KHz Note 1. For operation above 25'C ambient temperature,the device must be derated based on t50"C maximum junction temperature and a thermal resistance OJA of eo·c/w. Nole 2. Mixer gain is supply dependent and effects overall sensHivily accordingly (See Typical Performance Characteristics). S 12·122 -----------------------------------------------------------------------------, r :s:: Typical Performance Characteristics (Test Circuits) Co) Co) Q) ... ~ 10 IS vs. Vs 10 20 dB SIN SENSITIVITY AND AUDIO OUT vs. Vs I I , .... 400 .,.. ; ON "'" , SENSITIVITY ~TE ".- I I , MUTE OFF ~~~IO_ '/' I I / I i/ I I I I 10 Vs (Voll.) 10 3DD Vs (Voll.) THO AND AUD OUT VS Q FM IF CHARACTERISTIC 10 '·10 ,3D , O.B ~ ~ 0.6 Q 0.01 0.1 . ~ 0.4 :> 0.2 ~ V ~,. J / :> ""- ·50 THo I- \. ·40 0.001 AUOIO~ OUT k""" ·20 ·60 I S+N J 0.8 . 0.6 :! 0.4 :§ 0.2 N 10 20 30 QUAD COIL Q 100 RF IN (mVrm.) o 40 TLlH/55B6-2 • 512-123 LM3361A :;:, CD 3 !.: en n ::r CD RI 51K R3 ~R4 10K 10K ", I. I ra6 R2 71KI y ~R5 ~R6 10K ~R7 ~R8 10K 10K ~R9 ~R10 10K ~Rl1 ~R12 10K 10K 10K ~ al~al1 R15 SKI en .... 10K R16 10K R17 13K ~ R22 R11 5QK 13K '" 15 "" R40 7K ---t>J!!!! 5K 037~ R19 13K R25 7K5 U41 ~ 7K . *035 !R2& 33K 3 R42 10K 4 L' R50 IK8 fR52fR53 51K 36K fR54 3K9 J t r 1r R55 2K """ 15K R38 pt 39K R62 20K 2, KQ73 Q5Q R36 75K 12~72 +-r041 Q40* 0 j63 l ''11 R37 ~R44 4K3 :H7K R45 27K R46 2K R47 27K R48 27K R51 10K '~~ 22K "'-.:... R64 470 1. 15 J ' R61 R&D 220K I I ..... 038 039.b 5" Ha36 N' R39 3S» Q74 13 R63 10K I r 14 r-Q75 R&5 51K TUH/5586-3 ,-------------------------------------------------------------------------, r 3: Co) Applications Information (See Internal Schematic) OSCILLATOR The Colpitts type oscillator is internally biased with a regulated current source which assures proper operation over a wide supply range. The collector, base, and emitter terminals are at pins 4, 1, and 2 respectively. The crystal, which is used in the parallel resonant mode, may be replaced with an appropriate inductor if the application does not require the stability of a crystal oscillator. In this case, the resonant frequency will be determined by the inductor in parallel with the series combination of C1 and C2. r c,..L r--_'f.... I I T OVs I t:::J_~ L -=::- C2=r I I - - - - - -... 1 PIN 1 "'lII PIN 6 TUH/5586-4 Co) Q) tic, also increases distortion (see Typical Performance Characteristics). For proper operation, the voltage swing on pin 8 should be adequate to drive the upper rank of the multiplier into switching (about 100 mVrms). This voltage level is dependent on the internal 10 pF capacitor and the tank Rp voltage divider network. After detection and de-emphasis, the audio output at pin 9 is buffered by an emitter follower. OPAMP The op amp inverting input (pin 10) which is internally referenced to .7V, receives dc bias from the output at pin 11 through the external feedback network. Because of the low D.C. bias, maximum swing on the op amp output with 10% distortion is 500mVrms. This can be increased when operating on supplies over 2.3V by adding a resistor from the op amp input to ground which raises the quiescent D.C. at the output allowing more swing (see figure below for selection of added resistor). The op amp is, normally utilized as either a bandpass filter to extract a specific frequency from the audio output, such as a ring or dial tone, or as a high pass filter to detect noise due to no input at the mixer. The latter condition will generate a Signal at the op amp oput, which when applied to pin 12 can mute the external audio amp. for max swing: VOUT=(VS-VBEl/2 (from internal circuit) so Ct=(Cl)(C2)/(Cl +C2) so (VS-VBE)/2=.7( 1 and fo=.159/,1[(Cij MIXER The mixer is double balanced to reduce spurious responses. The upper pairs are switched by the oscillator while the RF input is applied to the lower pair (pin 16). R43 sets the mixer input impedance at 3.6 kG. The mixer output impedance of 1.8 kG will properly match the input impedance of a ceramic filter which is used as a bandpass filter coupling the mixer output to the IF limiting amplifier. IF LIMITER The IF amplifier consists of six differential gain stalles, with the input impedance set by R2 at 1.8 kG to properly terminate the ceramic filter driving the IF. The IF alone (without mixer) has a - 3 dB limiting sensitivity of approximately 50 p.V. The system bandwidth is limited to about 5 MHz due to high impedances in the IF which are necessary to meet low power requirements. The IF output is connected to the external quad coil at pin 8 via an internal 10 pF capacitor. FM DEMOD AUDIO OUT A conventional quadrature detector is used to demodulate the FM signal. The Q of the quad coil, which is determined by the external resistor placed across it, has multiple affects on the audio output. Increasing the Q increases output level but because of nonlinearities in the tank phase characteris- ..... :r> an + :~) d' R2 _ (VS-VBE) R3-1 1A H2 ~7V II """""--ll-- HI O.7V r-.... V. .....---. •r-AJvv-..--tI I-) R3 """"~--o() ~ VOUT • 0,7 R3V () 1 +~ V ~W TUH/5586-5 Increasing OP Amp Swing SQUELCH TRIGGER CIRCUIT The squelch trigger circuit is configured such that a low bias on the input (pin 12) will force pin 13 high (200 mV below supply), where it can support at least a 1 mA load, and pin 14 to be a low impedance, typically 150 to ground. Connecting pin 14 to a high impedance ground reference point in the audio path between pin 9 and the audio amp will mute the audio output. Pulling pin 12 above mute threshold (.65V) will force pin 13 to an impedance of about 60 kO to ground and pin 14 will be an open circuit. There is 100 mV of hysterisis at pin 12 which effectively prevents jitter. S 12-125 • ~NatiOnal . PRELIMINARY Semiconductor. LMC835 Digital Controlled Graphic Equalizer General Description Features The LMC835 is a monolithic, digitally-controlled graphic equalizer CMOS LSI for Hi-Fi audio. The LMC835 consists of a Logic section and a Signal Path section made of analog switches and thin-film silicon-chromium resistor networks. The LMC835 is used with external resonator circuits to make a stereo equalizer with seven bands, ± 12 dB or ± 6 dB gain range and 25 steps each. Only three digital inputs are needed to control the equalization. The LMC835 makes it easy to build a ,.,.P-conlrolled equalizer. The signal path is designed for very low noise and distortion, resulting in very high performance, compatible with PCM audio. • • • • • • No volume controls required Three-wire interface 14 bands, 25 steps each ±12 dB or ±6 dB gain ranges Low noise and distortion TTL, CMOS logiC compatible Applications • • • • • Hi-Fi equalizer Receiver Car stereo Musical instrument Tape equalization • Mixer • Volume controller Connection Diagram Dual-In-Llne Package AUI! '-" .!!: UND AIHI..l !!. AIHS ..J ~ AINI . AIM3 Order Number LMC835N See NS Package N28B ...! AIH. ~ ll. AIHl LCI ...! a Lca LCZ ...! ~ tCg LC3 ..2 ~ LCIO LC4 ...! LC5..! ~ LCIZ LC6 .l!! ~ LCl3 LC7 ..ll Vss ..!! ..!! ..!! ~ ~ ~ ~ D.GND .. CLOCK , rn- LC11 LCl4 Vou DATA STROBE TLlH/6753-1 Top View S 12-126 _ _ 14 ~ LEVEL SHIFT 1 CLOCK DO R1a~?lR I:: III T, I:~ AIM1 0 • I I I In I • ~ AIN! LY I II 2 0-7.3k 1 1 --r-- AIN1 0 ...... Rlb.( 3.Ck S RdC 28 UNO BOOST 3.Ck ~ ~ I II II II II II II II II R5e t-+-t-+-t-+-+-I-HD'~?IW~ :6 dB .......t-+-t-+-~~_--..::.Rl~e,.,.,.. OR ......H-H-HP'....-o-----lPO~ri :12dB Sb RbC <: AIN7 SELECTORAI OUT ....... 5. II II <: Rbb II II 3_CkS S 3.Ck 25 I I o_-,.~ II II RbO 7.3k A41 A5 I ; I I 1- I I :1 h r: II II II II II n II II II II ;I II IIII Ii I II II I II II I .. II I II II I II II I II _II .. A6 1 A711BlflB2 I; I; :1 II II II II II II II II II II II II .. 0-- L Rb2 7.3k AINSg , , LCI ea a3 6 LC2 07 LC3 08 LC4 09 LC5 IB31..u.v.i~J:!~}! II II 26 AINe iii" I 17 Rd2 ~ C • -~11 AA~ 7.3k 3 AIN30-- en ~ 1 RdC - 0' n -4-TO-16 DECODER LATCH 05 16 DATA OJ :1I~~ 01 010 011 LC6 LC7 II .. II II .. II II II II II II II II II II II II II II II II II II II III I II II IIII II I I: II II II II II II II II II II II II II II II II IIII II II II II II II II ;: II II II II II IIII II II II I 11_ II II _ ~~~rr~~~ I' 023 I' 022 I' 021 I' I' I' -I'018 024 LCa LC9 LC10 LCll 020 019 LC12 LCla LCU TUH/6753-2 S&80.,1 U) CO) co o :E .... r-------------------------------------------------------------------------------Operating Ratings Absolute Maximum Ratings 18V Vss-0.3V Supply Voltage, Voo-Vss Allowable Input Voltage (Note 1) tOVOO+0.3V - 60·C to + 150·C Storage Temperature, Tstg Lead Temperature (Soldering, 10,sec), TL +300·C Supply Voltage, VOO-VSS 5Vt016V Digital Ground (Pin 13) Vssto Voo Digital Input (Pins 14, 15, 16) V!lstoVoo Analog Input (Pins 1, 2, 3, 4, 25, 26, 27) (Note 1) VsstoVoo -4O"Cto +85·C Operating Temperature, Tope Electrical Characteristics (Note 2) Voo= 7.5V, Vss= -7.5V, A.GND=OV LOGIC SECTION Symbol Test Conditions Parameter Typ Design Limit (Note 4) Unit (Limit) 0.5 0.5 5 5 mA(Max) mA(Max) mA(Max) mA(Max) IDOL ISSL IOOH ISSH Supply Current Pins 14, 15,16 are OV Pins 14,15, 16 are OV Pins 14, 15,16 are 5V Pins 14,15,16 are 5V VIH High-Level Input Voltage @Pins 14, 15, 16 1.8 2.3 2.5 V (Min) VIL Low-Level Input Voltage @Pins 14, 15, 16 0.9 0.6 0.4 V (Max) fo Clock Frequency tw(,STB) Width of STS Input 0.01 0.01 1.3 0.9 Tested Limit (Note 3) 0.5 0.5 . 5 5 @Pin14 2000 500 500 kHz (Max) See Agure 1 0.25 1 1 ,...S(Min) !setup Data Setup Time See Agure 1 0.25 1 1 ,...S(Min) thold Data Hold Time 'See Agure 1 0.25 1 1 ,...S(Min) tcs Delay from Rising Edge of CLOCK toS'fB .See Figure 1 0.25 . 1 1 ,...S(Min) liN Input Current @Pins 14, 15, 16 OV -4>--.y,fr-----------------o()VaUTB r--, ~------=D~A~U~ I WDRD GENERATDR I I I D.GND L.. __ .J ...... y , f I r - - - - - - - - - - - - - - - - - o ( ) V a u T A >~ TLlHI6753-5 FIGURE 3. Test Circuit for AC Measurement Vl24 V123 V122 Vl21 Vm Vl19 Vl1B + 7.5V rl,,1,rl,rY,rl,rl,rl, . I " .......... ' ,IIYII"V li"Y .. "Y lillY IIIIV lillY' .. 11111111111111 ~ ~. ~~ ~. ~. ~. DATA r - -, ...-----=="'" WDRD GENERATDR D.GND I I I ,. I L.. __ .J LMCB35 TLIH/6753-6 FIGURE 4. Test Circuit for Leakage Current Measurement S 12·131 U) r-----------------------------------------~~--------------------------------------------C") CD (,) Test Circuits (Continued) :3 r------, ILlNo-+---......~.... >-.-+<> VLOUT I I I lk IL____ lOOp I ...:...J VLOUT -ILlN)( 107 TUH/6753-7 FIGURE 5. I to'V Converter o-~~~~,--_,------------_,--1r--------------~i:HC;OO~ CLOCK 10 10 DATA HC74 STAHT 12 0 1-:-~1-4--.::.tCK HC74 tD~ +V __-!~~-----t------o~ +VD7 D6 05 D4 D3 D2 Dl DD TUH/6753-8 FIGURE 6. Simple Word Generator Typical Performance Characteristics Supply Current VB Supply Voltage 2,0 c1.& !.1.4 i = !t:~~~-STO-5V 0.6NO-A.6NO-OV 1.0 ~ 0.8 E 0.8 0.4 0.2 = 1 I j 100 1.2 G Supply Current VB Temperature I --i- i./ ~I-'" .;- !-'ITss I I 1 2 3 4 5 6 7 • • 10 SUPPlY VOLTAGE (:tV) 2.0 ~-:t7.5V 1.8 K-OATA-S'fi-5V c1.l O.GNO-A.GNO-OV In !. 1.4 j 1.2 G 1.0 ~ 0,8 E 0.1 lil 0.4 0.2 o -50,-25 'sa Input Capacitance VB Input Voltage 10 -- • PINS 14. 15. 16 I VI. :t7,5V, TA-25'C r-r-r-O,GNO-A,GND=OV i--r--r-1-1 MHz I- r--r-- I -- II W- f-- '-r-r-- 1 D 25 50 75 100 125 TEMPERATURE ('C) o 012345178910 INPUT VOLTAGE (V) TlIH/6753-9 S 12-132' Typical Performance Characteristics (Continued) Maximum Output Voltage VB Temperature 10 9 Vs~ :t:7.5V :t 12 dB RANGE FLAT - w '=1I1.HI, THO >1% ~- r- - - - 4 3 r-r-,--,,- - -- r- -r- -f- 1 o O~~~----~~~ o 10 2 3 4 S -SO -25 SUPPLY VOLTAGE (:tVI Distortion vs Frequency @ ± 12 dB Range 0.1 r.V:'"s="-:":t':7.';;SV:"'.T:"A-='::2S:-;.C::"m!1=O+m0l :t12 dB RANGE ---FLAT --:t12dB 0.02 ~ z ~ '1IIIIIi~ii ~ O.OOS 0.01 ~ 100 . lK 10K FREQUENCY (Hzl e ii ! 0.02 ~ 0:01 ill ~ 0.98 ~ 0.97 z 0.96 0.95 -SO -25 2S 50 75 100 12S TEMPERATURE (OC) r::---:"':-:::--=---==="""", 0.1 0.02 r--t-t-++tHft---iH+1l+1-\l ~ ~~'lm~~!'11 ~ O.OOS ~ 0.01 0.001 ===l.J.IJ.I11IL:.:l......;w;:,::.:u.I.J.WJI 10 100 lK 10K lOOK FREQUENCY (Hz) 0.002 1--++I+f1~:;;;; 0.001 '---'-L..J...J.J.J..Lu.:.=~~.ll.IJW 0.1 0.2 0.5 OUTPUT VOLTAGE (V,m.) 3 V,-::T5VT,_n', ~;;~:I~oUIGfIGOsr 13 10 Gain vs Frequency @ ± 12 dB Range (Cut) Gain vs Frequency @ ± 12 dB Range (Boost) 0.1 r::-""7'::-::::-;--::==-===", 0.05 - -- Distortion vs Output Voltage @ ± 12 dB Range ~ 0.002 Distortion vs Output Voltage @ ±6dBRange - O.OS ile 0.005 lOOK 1.02 1.01 1 ~ 0.99 0.05 ~#IlIIi=VO~a::;l~v~'m~'~~!lE!. 0.002 25 50 75 100 12S TEMPERATURE (·C) :l == a: Distortion vs Frequency @ ±6dBRange 0.1 r.:----:-=-=:;-:--==__="""" O.OS co Nominal Resistor vs Temperature 1.05 1.04 1.03 V"·:t.'5rT•• t5~ .~.Inu :1Z II UNCII CUI 11 . . 9 -"I -Idl -1 -3 ~ z -5 C -7 -9 0.002 1---H~tf'f'l:tl~+t'f++H+I -11 0.001 0.1 0.2 0.5 1 OUTPUT VOLTAGE (V,m.) -1 10 Gain vs Frequency @ ± 6 dB Range (Boost) 100 lK 10K FREQUENCY (Hz) lOOK Gain vs Frequency @ ±6 dB Range (Cut) -13 10 100 lK 10K FREQUENCY (Hz) 10 Gain vs Temperature L '._::75¥' ,,-H'C lIo-IID1I zl"MNUtUf .IU r~II,1 .Sldl ~ +t~I' .40. ~ . z C -3 .n'li +.10'" .is'.i .io',' .u. :::\:/ ,~, 10 f" 100 lK 10K FREQUENCY (Hz) -1 -2 lOOK :~::a~~v JUl -os .. F -II' -15 •• -2111' -~ ':'. ~ :t 12 dB RANGE I- -.1s'.i -io',; '" ... -4 -UI' -5 :-~D~I -& -10., "" -~$fd~ 10 lOOK 100 lK 10K FREQUENCY (Hz) 1 a lOOK -50 -2S - - Od8 -=- 1 I 5dB 4d8 3d8 2dB 1 d8 FLAT a 25 50 75 100 12S TEMPERATURE (·C) TLlH/6753-10 S 12-133 U) r---------------------------------------------------------------------------------- g ('I) ... Typical Applications 27k YIN. -,N o-JIt,IIo\oo-.... Uk 1+-----::;:==:;::---0 VOUla HP---+ + 15VoCIN 27k P-.P-..-.P-.•-.P-.. -~ 11111111111111 I Zl II Z2 II Z3 II Z4 II Z5 .. Z6 .. Z7 I 111111111 .. 1 1 . + 41~ 11111111111111 I ZlI1Z211Z3I1Z411Z5I1Z6I1Z7' lOOp + 41~ I II .. II II II .. I L_~L_~L_JL_JL_JL_JL_J H~--. -15¥oCIN >::-9-'Mrl 21k 1-:--------------0 VoUlA IOn +15V -15V TLIH16753-11 FIGURE 7. Stereo 7-Band Equalizer TABLE I: Tuned Circuit Elements Z1 fo (Hz) Zl Z2 Z3 Z4 Z5 Z6 Z7 63 160 400 lk 2.5k 6.3k 16k Co(F) CL(F) RL(O) Ro(O) lp. 0.1p. 0.47p. 0.15p. 0.033p. 0.015p. 0.0068p. 0.0033p. 0.0015p. 680p lOOk lOOk lOOk 82k 82k 62k 47k 680 680 680 680 680 680 680 0.068p. 0.022p. 0.01p. 0.0047p. PIN 2. 3 OR 26 PIN "LC" Qo=3.5, Q12dB= 1.05 rBd--' Ico I I~ lOOk I I I I, I I _ _ _ _ .JI l.o=CL RL,Ro 1 10= 2".Jt;;c;; 00=~Co~2 RoOo Q'2dB=Ro+1590 L~. t159D1lo=55k#16k#11k#Bk#3 kill TLlH16753-12 FIGURE 8. Tuned Circuit for Stereo 7-Band Equalizer (Figure 7) S 12·134 Typical Applications (Continued) Performance Characteristics (Circuit of Figure 7) LM835 Gain vs Frequency LM835 Gain vs Frequency @ ± 12 dB Range @ ± 12 dB Range (All Boost or Cut) (1 kHz Boost or Cut) 12l1li. 12 iii 4 i" 0 ~-4 -8 -8 -12 -12 -16 10 10K 100 lK FREOUENCY (Hz) -16 lOOK 10 100 lK 10K lOOK FREOUENCY (Hz) LM835 Gain vs Frequency @ ±6dBRange (All Boost 'or Cut) LM835 Gain vs Frequency @ ±6 dB Range (1 kHz Boost or Cut) 8 6 ... . -211_ '" ;!E ~-2 c -4 -4 ! 1111111111111111111 -6 -8 10 100 lK 10K -6 -8 lOOK 10 100 FREQUENCY (Hz) lK 10K lOOK FREQUENCY (Hz) TUH/6753-13 +15V > ........'W......------------OOVOUT "=' +7,5V lOOk • DATA STROBE 28 27 A,GNO AINS 26 AIHI 25 fqN7 24 LC8 23 LCS 22 LCIO 21 20 LCI1 LC12 19 18 17 LC13 LC14 Voo LC6' Vss LMC835 LCI LC2 LC3 5 LC4 LC5 8 9 10 LC7 11 12 CLOCK '---.O,GNO -7,5V .-.. 11111"111111 1 I I I ZI II Z2" Z3 " II .. .. Z4 .. Z5 .. Z6 II Z7 I .. II II -~.-~.-~.-~.-~.-~ FIGURE 9. 12-Band Equalizer 512-135 TLlH/6753-14 Typical Applications (Continued) TABLE II. Tuned Circuit Elements PIN "LC" 00=4.7, Q12 dB= 1.4 Z1 Z2 Z3 Z4 Z5 Z6 Z7 Z8 Z9 Z10 Z11 Z12 fo (Hz) Co(F) CL(F) Rdo) Ro(O) 16 31.5 63 125 250 500 1k 2k 4k 8k 16k 32k 3.3,.,. 15,.,. 1,.,. 0.39,.,. 0.22,.,. 0.1,.,. 0.047,.,. 0.022,.,. 0.01,.,. 0.0068,.,. 0.0033jl. 0.0015,.,. 0.47,.,. 0.22,.,. 0.1,.,. 0.068,.,. 0.033,.,. 0.015,.,. 0.01,.,. 0.0047,.,. 0.0022,.,. 0.001,.,. 680p 470P. 100k 110k 100k 91k 82k 100k 82k 91k 110k 82k 62k 68k 680 680 680 680 680 680 680 680 680 680 680 510 PIN 26 r ICo I ICl I I A-_"-' Rl L~ ____ J (15900-55k#16k#11k#8kn kO) TL/H/6753- 15 FIGURE 10. Tuned Circuit for 12·Band Equalizer (Figure 9) Performance Characteristics (Circuit of Figure 9) 12 Band Equalizer Application LM835 Gain vs Frequency @ ±6 dB Range (All Boost or LM835 12 Band E.Q. Application Gain vs Frequency @ ± 12 dB Range (1 kHz Boost or Cut) 16 12 8 ;;; !!. ! ! 4 ~ I 0 .. -4 -2 -8 -4 -6~. -8~ 10 100 lK 10K I -12 -16 10 100 lOOK lK 10K lOOK FREQUENCY (Hz) FREQUENCY (Hz) 12 Band Equalizer Application LM835 Gain vs Frequency @ ± 12 dB Range (All Boost or Cut) LM835 12 Band E.Q. Application Gain vs Frequency @ ±6dBRange (1 kHz Boost or Cut) 16~m1 12 rP.tII !z 0 :iI -4 ;;; .. ~ ~ :- -8 -2 -4 -16 -6 -8 -12~E1 f!!tWII 10 100 lK 10K lOOK 10 FREQUENCY (Hz) 100 lK 10K lOOK FREQUENCY 1Hz) TLIH/6753-16 S 12·136 Typical Applications (Continued) VDD ">.....---w\t-...:..j 1 - - - - - - - - - - 0 VDUTB lOOk 47. + VDD r-,r-,r-1r-,r-,r-1r-' 11111111111111 I ZI II Z2 II Z3 II Z4 II Z5 II Z6 II Z7 I 1 1 1 1 1 1 1 1 1 1 1 .. 1 . - - - - _ VDD BV TO 15V .....-_OATA STROBE 5.lk 5.lk CLOCK •1 1 1 1 1 1 1 1 1 1 1 1 11 '::' L...--_D.GND I ZI II Z2 .. Z3 II Z4 . . Z5 II Z6 II Zl I ,111111 .. 11111 ~_JL_JL_JL_JL_JL_JL_J lOOk > .....-""'I'r-:.t 1-----------0 VOUTA TL/H/6753-17 FIGURE 11. Single Supply Stereo Equalizer • S 12-137 U) Cf) ~ Typical Applications (Continued) :IE -' VOUTS TLlH/6753-18 TLlH/6753-19 FIGURE 12. Stereo 7-Input/1·0utput Mixers (THO Is not as low as equalizer circuit) FIGURE 13. Stereo Volume Control, Very Low THO +5V LMC835 DATA I-----t ffiiiii D.GND TL/H/6753-20 FIGURE 14. LMC83S·COP404L CPU Interface S 12-138 ------------------------------------------------------------ir Typical Applications :s::: oCD (Continued) (,) Sample Subroutine Program for Figure 14, LMC83S-COP404L CPU Interface CI1 HEX CODE LABEL 3F LMC835: MNEMONICS LBI 3F 05 SEND LD COMMENTS ;POINT TO RAMADDRESS 3F ;RAMDATA TO A 22 SC ; SET CARRY 335F OGI ;SET PORT G= 1111, OPEN THE AND GATES 4F XAS ; SWAP A AND SIO, CLOCK START 05 LD ;RAMDATA TO A, MAKE SURE A = DATA 07 XDS ; SWAP A AND RAMDATA, RAMADDRESS=RAMADDRESS-1 05 4F LD ;RAMDATA TO A XAS ; SWAP A AND SIO 05 LD ;RAMDATA TO A, MAKE SURE A=NEWDATA 07 XDS ; SWAP A Aim RAMDATA, RAMADDRESS=RAMADDRESS-1 ;RESET CARRY 32 RC 4F XAS 335D OGJ 13 ;SET PORT G=1101, MAKE STROBE LOW 335B OGI 11 ;SET PORT G=lOl1 , MAKE STROBE HIGH, CLOSE THE 4E CBA ; SWAP A AND SIO, CLOCK STOP GATES 43 AISC 48 RET 80 JP ;BDTOA ;RAMADDRESS < 3C "THEN RETURN 3 SEND RAM ADDRESS 3C DATA COMMENTS ;GAIN DATA D4-D7 3D DATA ;GAIN DATA DO-D3 3E DATA ;BAND DATA D4-D7 3F DATA ;BAND DATA DO-D3 Application Hints HOW TO AVOID SWITCHING NOISE DUE TO LEAKAGE CURRENT (Refer to Figures 7 and 8) SWITCHING NOISE The LMC83S uses CMOS analog switches that have small leakages (less than 50 nA). When a band is selected for flat gain, all the switches in that band are open and the resonator circuit is not connected to the LMC835 resistor network. It is only in the flat mode that the small leakage currents can cause problems. The input to the resonator circuit is usually a capacitor and the leakage currents will slowly charge up this capacitor to a large voltage if there is no resistive path to limit it. When the band is set to any value other than flat, the charge on the capaCitor will be discharged by the resistor network and there will be a transient at the output. To limit the size of this transient, RLEAK is necessary. To avoid switching noise due to leakage currents when changing the gain, it is recommended to put RLEAK= 100 KO between Pin 3 and Pin 5-11 each, Pin 26 and Pin 1224 each. The resistor limits the voltage that the capacitor can charge to, with minimal effects on the equalization. The frequency response change due to RLEAK are shown in Figure 15. The gain error is only 0.2 dB and Q error is only 5% at 12 dB boost or cut. S 12-139 ,. U) C') B :I r------------------------------------------------------------------------------------Application tiints (Continued) > ....-OOVOUT , t2 dB r---I"---.-----......,.__--- 11.8 d8 I-~__._-I---+_._M._ I I odB lOOk N~ MODEL "'0110 10"'0 "'0 RESULT TLlH/6753-22 TUH/6753-21 FIGURE 15. Effect of RLEAK REDUCING EXTERNAL COMPONENTS The typical application shown in Figure 7 is switching noise free. The DC-coupled circuit in F/{/ure 16 is also switching noise free, except at 12 dBIS dB switch tum ON/OFF. This switching noise is caused by the Ibias and Voffset of the op amps. Selecting a low Ibias and Valise! op amp can minimize the switching noise due to the 12 dBIS dB switch. The DC· coupled application can also eliminate the RF= 100k resis· tors with only a 0.5 dB gain error at 12 dB boost or cut. tOOk tOOk ·".r LMC835 LMCB35 TLlH/6753-24 TLlH/6753-23 ACCOUPLING FIGURE 16. Reducing External Components S 12·140 DC COUPLING Section 13 Telecommunications Circuits ' Telecommunications Circuits Section Contents Switching and Transmission TP3020/TP3020-1/TP3021/TP3021-1 Monolithic CODECs .•.•.•••...•.•.••...•..••••.•.•.•.•...••••••.•....•. S 13-1 Telephone Components TP5700/TP5700-1/TP5710 Telephone Speech Circuits .•......•...••..........•............•..•.•...•....•... S 13-10 TP53190 Push-Button Pulse Dialer ••.•.•..•......•..•.•.••••..••.••.•.•....••...••.•....•.••••....•..•..... S 13-17 i ~National ~ Semiconductor microCMOS ~ Co) 2 9 ..... ..... -I TP3020/TP3020-1/TP3021/TP3021-1 Monolithic CODECs "0 Co) General Description Features The TP3020 and TP3021 are monolithic PCM CODECs implemented with double-poly CMOS technology. The TP3020 is intended for flo-law applications and contains logic for flolaw signaling insertion and extraction. The TP3021 is intended for A-law applications. Each device contains separate DI A and AID circuitry, all necessary sample and hold capacitors, a precision voltage reference and internal auto-zero circuit. A serial control port allows an external controller to individually assign the PCM input and output ports to one of up to 32 time slots or to place the CODEC into a power-down mode. Alternately, the TP3020/TP3021 may be operated in a fixed time slot mode. Both devices are intended to be used with the TP3040 monolithic PCM filter which provides the input anti-aliasing function for the encoder and smoothes the output of the decoder and corrects for the sin xIx distortion introduced by the decoder sample and hold output. • Low operation power-45 mW typical • Low standby power-1 mW typical • ± 5V operation • TTL compatible digital interface • Time slot assignment or alternate fixed time slot modes • Internal precision reference • Internal sample and hold capacitors • Internal auto-zero circuit • TP3020-flo-law coding with Signaling capabilities • TP3021-A-law coding • Synchronous or asynchronous operation 2 ..... ..... -I "0 Co) 2 ..... .....• Simplified Block Diagram 5V, Vcc VfX .....fr-;;;-,.---I-. DxTiic _ ...."""\jMr..... IMI.LE AID HOLD ...._ _ _ _ _ AID ... scz ...- ..... SC11---, CLKX fSx SlOx ITP3I2UILY} DC CLXC PDN CLKR • SIGR ITP3IIZI DILY} VfR +-+---____< -5V OIDA S 13-1 TL/H/5538-1 Absolute Maximum Ratings Operating Temperature - 25'C to Storage Temperature -6SOCto + 125'C + 150'C Voltage at Any Analog Vee with Respect to GNDD Vee-0.3V to Vee + 0.3V GNDD-0.3V to Vee + 0.3V Input or Output 7V -7V Vee with Respect to GNDD Voltage at Any Digital Input or Output Lead Temperature (Soldering, 10 seconds) 300'C DC Electrical Characteristics Unless otherwise noted TA=O'C to 70'C, Vee=5.0V±5%, Vee = - 5.0V ± 5%. Typical characteristics are specified at Vcc= 5.0V, Vee = -5.0V and TA = 25'C. All digital signals are referenced to GNDD. All analog signals are referenced to GNDA. Symbol I Parameter I Conditions I Min I Typ I Max I Units DIGITAL INTERFACE -10 II Input Current Vll Input Low Voltage VIH Input High Voltage VOL Output Low Voltage Ox. 10l = 4.0 mA SIGR, 10l = 0.5 mA TSx, 10l = 3.2 mA, Open Drain PDN, 10l = 1.6 mA VOH Output High Voltage Dx,IOH=6mA SIGR,IOH=0.6 rnA 2.4 2.4 V V 2.0 kO O output from 14 Ox the encoder. During the encoder time slot, the PCM code for the previous sample of VFx is shifted out, most significant bit first, on the rising edge ofCLKx· Time slot output. This TTL compatible 15 TSx. open-drain output pulses Iqw during the encoder time slot. May be used to enable external TRI-STATE bus driv· ers if highly capacitive loads must be driven. Can be wire ANDed with other TSx outputs. 5V (±5%) input. 16 Vee 17 Master decoder clock input used to CLKR shift in the PCM data on DR and to operate the decoder sequencer. May operate at 1.536 MHz, 1.544 MHz or 2048 MHz. May be asynchronous with CLKx or CLKc. 18 Decoder frame sync pulse. Normally occurring at an 8 kHz rate, this pulse is nominally one CLKR cycle wide. Extending the width of FSR to two or more cycles of CLKR signifies a receive signaling frame. Function Internally connected to GNDA. Connects VFx to an external sample/ hold capacitor if fitted for use with pincompatible NMOS CODECs. E[ldures gain compatibility. Analog input to the encoder. This signal will be sampled at the end of the encoder time slot and the resulting PCM code will be shifted out during the subsequent encode time slot. Unused Analog ground. All analog Signals are referenced to this pin. Receive signaling bit output. During receive sign~ling frames the least significant (last) bit shifted into DR is internally latched and appears at this output-SIGR will then remain valid until changed during a subsequent receive signaling frame or reset by a power-down command. Unused Serial PCM data input to the decoder. During the decoder time slot, PCM data is shifted into DR, most significant bit first, on the falling edge of CLKR· TTL output level which goes high when the CODEC is in the power-down mode. May be used to power·down other circuits associated with the PCM channel. Can be wire ANDed with other PDN outputs. S13·6 -t ." Description of Pin Functions (Continued) (0) TP3020 (Continued) Pin No. Name Function 19 Master encoder clock input used to CLKx shift out the PCM data on Dx and to operate the encoder sequencer. May operate at 1.536 MHz, 1.544 MHz or 2.048 MHz. May be asynchronous with CLKR or CLKe. 20 Encoder frame sync pulse. Normally FSx occurring at an 8 kHz rate, this pulse is nominally one CLKx cycle wide. Extending the width of FSx to two or more cycles of CLKx signifies a transmit signaling frame. Transmit signaling input. During a 21 SIGx transmit signaling frame, the signal at SIGx is shifted out of Dx in place of the least significant (last) bit of PCM data. -5V (±5%) input. 22 Vee 23 Serial control data input. Serial data Dc on Dc is shifted into the CODEC on the falling edge of CLKc. In the fixed time slot mode, Dc doubles as a powerdown input. 24 Control clock input used to shift serial CLKe control data into Dc. CLKc must pulse 8 times during a period of time less than or equal to one frame time, although the 8 pulses may overlap a frame boundary. CLKe need not be synchronous with CLKx or CLKR. Connecting CLKe continuously high places the TP3020/TP3021 into the fixed time slot mode. TP3021 Pin No. 1 2 Name SCl SC2 3 VFx 4 5 NC GNDA 6 7 NC DR 8 PDN TP3021 (Continued) Pin No. Name Function Analog output from the decoder. The 9 VFR decoder sample and hold amplifier is updated approximately 15 J.LS after the end of the decode time slot. 10 NC Unused 11 NC Unused 12 GNDD Digital ground. All digital levels are referenced to this pin. Serial PCM TAl-STATE output from 13 Dx the encoder. During the encoder time slot, the PCM code for the previous sample of VFx is shifted out, most significant bit first, on the riSing edge ofCLKx· Time slot output. This TTL compatible 14 TSx open-drain output pulses low during the encoder time slot. May be used to enable external TAl-STATE bus drivers if highly capacitive loads must be driven. Can be wire ANDed with other TSx outputs. 15 (5V ± 5%) input. Vee 16 CLKR Master decoder clock input used to shift in the PCM data on DR and to operate the decoder sequencer. May operate at 1.536 MHz, 1.544 MHz or 2.048 MHz. May be asynchronous with CLKx or CLKe. 17 Decoder frame sync pulse. Normally FSR occurring at an 8 kHz rate, this pulse is nominally one CLKR cycle wide. 18 CLKx Master e(1coder clock input used to shift out the PCM data on Dx and to operate the encoder sequencer. May operate at 1.536 MHz 1.544 MHz, or 2.048 MHz. May be asynchronous with CLKR or CLKe. Encoder frame sync pulse. Normally 19 FSx occurring at an 8 kHz rate, this pulse is nominally one CLKx cycle wide. -5V (±5%) input. 20 Vee Serial control data input. Serial data 21 Dc on Dc is shifted into the CODEC on the falling edge of CLKe. In the fixed time slot mode, Dc doubles as a powerdown input. 22 CLKe Control clock input used to shift serial control data into Dc. CLKe must pulse 8 times during a period of time less than or equal to one frame time, although the 8 pulses may overlap a frame boundary. CLKc need not be synchronous with CLKx or CLKR. Connecting CLKe continuously high places the TP3020/TP3021 into the fixed time slot mode. Function Internally connected to GNDA. Connects VFx to an external samplel hold capaCitor if fitted for use with pincompatible NMOS CODECs. Ensures gain compatibility. Analog input to the encoder. This signal will be sampled at the end of the encoder time slot and the resulting PCM code will be shifted out during the subsequent encode time slot. Unused Analog ground. All analog Signals are referenced to this pin. Unused Serial PCM data input to the encoder. During the decoder time slot, PCM data is shifted into DR, most significant bit first, on the falling edge of CLKR· Open drain output which turns off when the CODEC is in the power-down mode. May be used to power-down other circuits associated with the PCM channel. can be wire ANDed with other PDN outputs. S 13-7 0 /\) 0 ..... -t ." (0) 0 /\) 0 ..... I -t ." (0) 0 /\) ..... ..... -t ." (0) 0 ..... ..... /\) I ~ r---------------------------------------------------------------------------------------~ • ~ C\I CI Functional Description t POWER-UP SERIAL CONTROL PORT Upon application of power, internal circuitry initializes the CODEC and places it into the power-down mode. No sequencing of 5V or -5V is required. In the power-down mode, all non-essential circuits are deactivated, the TRISTATE PCM data output Dx is placed in the high impedance state and the receive signaling output of the TP3020, SIGR, is reset to logical zero. Once in the power-down mode, the method of activating the TP3020/TP3021 depends on the chosen mode of operation, time slot assignment or fixed time slot. When the TP3020/TP3021 is operated in the time slot assignment mode or the fixed time slot mode with continuous clock, the data on Dc is shifted into the serial. control register, bit 1 first. In the time slot assignment mode, depending on 81 and 82, the data in the RCV or XMT time slot registers is updated at the second FSR or FSx pulse after the first CLK<; pulse, or the CODEC is powered down. In the continuous clock fixed time slot mode, the CODEC is powered up or down at every second FSR or FSx pulse. The control register data is interpreted as follows: C") ~ C\I CI C") a. to..... ~ ~ CI C") a. t: ~ a. to- TIME SLOT ASSIGNMENT MODE The time slot assignment mode of operation is selected by maintaining CLI ~ EXTERNAL COMPONENTS ~ I:~--COL -----TP5319D 'u TO COUNTERS ~ A----ROW 2-0F·7TYPE OTMF KEYBOARD TL/H5130-2 Cl=C2=80pF FIGURE 3. FIGURE 4. Output Timing Waveforms !~I_ _-,D[jr2~_____~!~I___________________ DIGIT 3 KEY -~U _--;..,j-iI-sm. I MUTE r~ II I-lOP PERIOD-j DIAL PULSE ~IDP PERIOD-j nUnU~ ~UnU. - ----:.-~!I.U BREAK -I 1- I I MAKE- - PE~:~~ -I ~ TL/H/5130-3 IDP=lnterdigit Pause FIGURE 5. Mute Not Active Between Digits S 13-20 .---------------------------------------------------------------------,~ Functional Description "'U en Co) (Continued) .... CD o + L1VJI--------.-.t--..-cr LZVJI------..-4-+IIt--+-cr AA + S.IM 10k VDD Note 1: All resistances in ohms and capacitances in JoLF unless otherwise noted. Note 2: OP Rate. 81M and lOP select pins must be tied to the appropriate logic level for desired operation. Note 3: Diode bridge must be added to telephone set. 0.1 lk TUH/5130-4 FIGURE 6. Using the TP53190 Pulse Dialer with Redial Option S 13-21 Section 14 Speech Speech Section Contents DIGITALKER Speech Synthesis . DTSW500 DIGITALKER Vocabulary Selection System DVSS •.................•.•.•.•.•.•.•.•.•.....•.•..•.•..• S 14·1 MM54104 DIGITALKER Speech Synthesis System .••••.•••.••.•..••••.•.•.•...•••..•••.•.............. '.....•. S 14·5 TP18 Implementation of a Speech Synthesis •..••••••••••.••.•.•. , .•••...•••••.•. , .•.•...••..•.•. , ....•.... , S 14·11 i ~National ~ Semiconductor Q Q OTSW-500 OIGITALKER® Vocabulary Selection System (OVSS) Product Description Features The DIGITALKER Vocabulary Development System (DVSS) is a CP/MTM software package which provides 500 highly intelligible English words in a male speaking voice. These words are intended for users of National Semiconductor's DIGITALKER MM54104 Speech Processor Chip. The package provides a complete software environment that allows users to create speech PROMs containing a vocabulary of words, phrases, or sentences put together from the 500 words supplied. The DVSS package consists of 2 floppy disks and a user's manual. The first disk contains the speech data archive and the second contains the system software. Both floppy disks are standard 8" single-sided, single density disks written in CP/M format. In a typical application, a user would start by developing a vocabulary for his envisioned talking product. This vocabulary could be composed of a list of Single words, phrases, or sentences. A standard CP/M text file is created containing the vocabulary list using any CP/M based text editor or the editor provided with the DVSS. This vocabulary list is checked to assure that all words on the list are contained in the current archive. Missing or misspelled words are flagged and the user must then return to the text editor to make corrections. • Create your own speech EPROMs • Choose words from a large database ...,.. 500 words to start - Future library expansion • Build sentences and phrases • No previous knowledge of synthetic speech required • Runs on most CP/M machines • Supports MM54104 Digitalker Speech Processor Chip The DVSS software creates what is called a work file for the vocabulary from an error-free vocabulary list. This work file can then be submitted to the ROM image building routine. The output is a ROM image file in binary format. This file in turn can be used to program PROMs. In order to use the DVSS software, a user needs a computer system that runs CP/M-80 and that has two 8" single density floppy disk drives. Also necessary is a CRT terminal with both upper and lower case capability. (Note that this configuration can actually be thought of as a model of the computer system on which DVSS will operate. There are however computer systems which don't exactly match this model that will run DVSS.) The DVSS programs are easy to use. A complete instruction manual and tutorial examples ensure that even a person unfamiliar with speech or programming will have little difficulty in prodUCing vocabulary lists and speech PROMs. The speech ROM images produced by the DVSS system will be nearly as memory efficient as speech ROMs produced at the National Semiconductor Speech Lab. The data rate for ROMs containing more than 50 words will be approximately 1200 bits per word. (Smaller speech ROMs'resuit in a slightly higher data rates.) Functional Description THE SPEECH DATA ARCHIVE The speech data disk supplied with the system contains 500 words. (Consult Table 1 for a listing of these words.) Each word stored on the floppy is a self-contained, stand-alone, playable entity. Adding further standard vocabulary or even custom words to the archive is a simple operation which is discussed in the software section below. THE SOFTWARE The DVSS software is a CP/M 2.2 applications program written in BDS C which will execute on most CP/M 2.2 compatible computers. The software requires the service of a CRT terminal. OPERATING ON SPEECH DATA ARCHIVES The speech data archive is the basic unit on which all the software operates. The system, as it is shipped from the factory, consists of a single speech data archive containing 500 words. The archive architecture, however, makes it very easy- to add to or create new archives from existing ones. This capability is useful in a number of situations. For instance, as more standard words are released by National Semiconductor, a user may wish to make a new archive that contains the entire standard word library. Or, if the full speech data archive has become too cumbersome or tQo large for storage on a single floppy, a subset of the full archive can be selected to create a new more manageable archive. The word archival software allows the user to obtain a variety of information about the contents of any archive. For example, the user can generate an alphabetical listing of all words in the archive. All of the lists generated by the DVSS can be output to any of the standard CP/M devices such as CON:, the system console, LST:, the system printer, or a file residing on any system supported disk. S 14-1 ,. C) r----------------------------------------------------------------------------------------- ! PREPARING VOCABULARY LISTS PROGRAM SPEECH DATA EPROMS The central purpose of the DVSS system is building speech ROM images which (after conversion to some physical media such as EPROM or RAM) can be played by the MM54104. The first step in building a ROM image is to list the messages, i.e. the words and phrases, that are to be contained in the image. In order to create, and if necessary, correct, such a message list, any CP/M text editor (for example, WORDSTARTM in "non-document" mode) may be used to create a file of the proper format (format specified ,in detail in the manual). The DVSS package includes a simple but powerful text editor that may be used in lieu of other CP/M editors. When the user 'has built a speech ROM image, he can program a physical PROM (or set of PROMs) to contain this image. The DVSS will ditectly support PROM programming on the local PROM programmer in STARPLEXTM systems. Speech ROM images are 'nothing more than CP/M files in binary format They may easily be converted (with user supplied software) to other formats for use with other user supplied PROM programming hardware (for example, with a remote programmer connected, to a serial port). AUDITIONING SUPPORT Customers who are using the DVSS to experiment with DIGITALKER speech, can easily obtain a speech system in which to play their EPROMs. National sells a simple board (DT 1058) and a software upgrade (DT 1060) that enables the original DIGITALKER demonstration board (DT 1000) to play up to eight 16k EPROMs (or 4 32k EPROMs) (see the DT data sheets for more information on these products.) There are also vendors who build DIGITALKER based addons to various computers which can accep~ speech EPROMs. These boards allow a user to play speech EPROMs under computer control (users of these boards might also want to use the DT 1058 PROM boa:rd). A list of such vendors is available on request from National. COMPILING VOCABULARY LISTS After a vocabulary list has been entered into a file, it must be compiled. The compiler checks for existence of words in the archive and prepares a workfile for the image builder. Any missing words are pOinted out for the user. BUILD SPEECH DATA ROM IMAGES Once the user has successfully compiled the vocabulary list, a ROM image 'can be made of these words and/or phrases by using the'ROM image builder. This function retrieves the raw speech data for each word in the vocabulary list, finds all redundancies; eliminates them; and packs the remaining data into a playable image. DTSW- 500 Word List 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 30 40 50 60 70 80 90 100 1000 a a. c. a.m. able abort accumulate acknowledge activate active activity add, address adjust after again air aisle alarm alert all alternate (adjective) amp ampere an and announcement answer april arrival ask assistance astern at attention august authorize auto available average away b back barometric basement bath battery been before between black blocking blue brake budget building buoy busy button by c call cancel capacitance car case caution cease celsius cent centi- (prefix) centigrade centimeter change channel check circuit clear close code cold comma command common communication complete condition configuration connect continue control S 14-2 converter cool copy correct cost count cross customer cut d d. c. danger data date day december decrease default degree delay demonstration deposit depth dial did disable divide dollar door down e east ed (suffix) electric electriCity else emergency enable end enter entry equal er (suffix) error evacuate examine exit extreme f fail failure far farad fast february feet fifth fight fire first floor flow forward friday from frontal fuel fuse g gallon gas get gOing good gram gray great green group h half have hello help here hertz high hit hold home hour house hurt i if in inactive inches incorporated incorrect increase ing (suffix) insert interface intruder invalid (not valid) is it j january july june just k key keypad kilo- I leave left less level lie light lime limit line link listen load lock loop low m march mark may meg- (prefix) mega- (prefix) message meter micro mile milli- (prefix) millimeter million minus minute miss model modem module monday monitor more move my n· nano- (prefix) near need next night no normal north not notice november number 0 o'clock october of off ohm okay on onward open operator optical or other out over over-range p p. m. pair pan parent pass past per percent phone phone number pica place play please plus point pound power program present press pressure pull pulse push put Q quarter r rain range rate re- (prefix) reach ready receive receiver record red remove repair repeat replace reset resistance response restore return reverse right ring room route run s safe saturday seco!1d secure security select send S 14-3 sensor september sequence service set short should side sight sink slow smile smoke sound south space span spare speed spell squad ss (suffix) stair star start station status steam stem stop store storm stream street sub subscriber sunday supervisory switch system t tank tape target tear teen temperature temporary terminate test th (suffix) than thank thank-you that the thee then there therm thermal third this thursday tide time tip today tone total C -I U) == 0 U1 0 • 0 0 II) 3: ~ touch tracking traffic transfer trip true trunk try tuesday tum type u un- (prefix) unable unattended unit unknown unlock up use uth (suffix) utility v voice volt voltage vote w wait wake • wake up warm warning was water watt wave wear wednesday week welcome west what will wind (short i) 514-4 wind (long i) wish with within word work x y yellow yes you your z zone ~National ~ Semiconductor MM54104 DIGITALKER® Speech Synthesis System General Description Features The DIGITALKER'is a speech synthesis system consisting of multiple N,channel MOS integrated circuits. It contains an MM54104 speech processor chip (SPC) and speech ROM and when used with external filter, amplifier, and speaker, produces a system which generates high quality speech including the natural inflection and emphasis of the original speech. Male, female, and children's voices can be synthesized. II Designed to be easily interfaced to most popular micro- processors II 256 possible addressable expressions II Male, female, and children's voices II Any language II Natural inflection and emphasis of original speech II Addresses 12Bk of ROM directly II TTL compatible The SPC communicates with the speech ROM, which contains the compressed speech data as well as the frequency and amplitude data required for speech output. Up to 12Bk bits of speech data can be directly accessed. This can be expanded with minimal external logic. II MICROBUSTM and COPSTM compatible II On-chip switch debounce for interfaCing to manual switches independent of a microprocessor II Easily expandable to greater than 12Bk ROM II Interrupt capability for cascading words or phrases With the addition of an external resistor, on-chip debounce is provided for use with a switch interface. II Crystal controlled or externally driven oscillator , II Ability to store silence durations for timing sequences An interrupt is generated at the end of each speech sequence so that several sequences or words can be cascaded to form different speech expressions. Encoding (digitizing) of custom word or phrase lists must be done by National Semiconductor. Customers submit to the factory high quality recorded magnetic reel to reel tapes containing the words or phrases to be encoded. National Semiconductor will sell kits consisting of the SPC and ROM(s) containing the digitized word or phrases. Typical Applications II Standard vocabulary sets available Applications II Telecommunications II Consumer products II Appliance II Clocks II Automotive II Language translation II Teaching aids II Annunciators Minimum Configuration Using Switch Interface l-I1V 1M -, ---- NO VSS VSS ADDRESS BUS AOR 0-13 SPC SWt-l ROATA MM54104 1-1 INTH CMS SPEECH VCC DSC IN OSC OUT I I I I _______ JI DATA BUS SPEECH ROM DIGtTALKER KIT t.5k 1M "The recipient of these products automatically receives a non-exclusive license under U.S. Patent Applicalion 432,859 and any patent or pat· ents issuing thereon to use such products, to assemble or otherwise incorporate tham into furthar products which may be covered by said patent application, or any patent or patents issuing thereon, and to usa, sell, or otherwise dispose of such products." Protected by U.S. Pat. No. 4124125. F.M. Mozer licenses available. "Single pole 2 position momentary switch ""4.0 MHz crystal Electro FILTER AND AMPLIFIER SPEAKER DynamiCS Corp. 20 pF HCIS TLlB/561.1-1 S 14-5 Absolute Maximum Ratings -65·Cto + 150"C -40·C to 85·C 12V Storage Temperature Range Operating Temperature Range Voo-Vss DC Electrical Characteristics Symbol 12V 7Vt011V 300·C Voltage Any Pin Operating Voltage Range. Voo-Vss Lead Temperature (Soldering. 10 seconds) TA= O·C to 70"C. voo = 7V-11V. vss = OV. unless otherwise specified. Parameter Conditions Min Typ Max Units 0.8 V -0.3 0.6 V 2.0 Voo V 2.2 Voo 'V 0.4 V -0.3 Vll Input Low Voltage Vll Input Low Voltage VIH Input High Voltage VIH Input High Voltage TA= -40·Cto 85·C VOL Output Low Voltage IOl=1.6mA VOH Output High Voltage IOH= -100 J£A 2.4 5.0 V VILX Clock Input Low Voltage -0.3 1.2 V VIHX Clock Input High Voltage 5.5 Voo V VOLX Clock Output Low Voltage Typical Crystal Configuration and 10M Load on Pin 2 1.2 V VOHX Clock Output High Voltage Typical Crystal Configuration and 10M Load on Pin 2 Voo V 100 Power Supply Current 45 mA 100 Power Supply Current 50 mA /LA /LA TA= -40·Cto 85·C 5.5 TA = -40"C to 85·C III Input Leakage ±10 IILX Clock Input Leakage ±10 Vs Silence Voltage VOUT Peak to Peak Speech Output REXT External Load on Speech Output 2.0 Voo=11V V .50 REXT Connected Between Speech Output and Vss AC Electrical Characteristics Symbol V 0.45Voo kO TA= O"C to 70·C. Voo= 7V-11V. Vss= OV. unless otherwise specified. Parameter Min Max Units taw CMS Valid to Write Strobe 350 ns tcsw Chip Select ON to Write Strobe 310 ns ~ Data Bus Valid to Write Strobe 50 ns twa CMS Hold Time after Write Strobe 50 ns twd Data Bus Hold Time after Write Strobe 100 ns tww tred Write Strobe Width (50% Point) 430 twss Write Strobe to Speech Output Delay ROMEN ON to Valid ROM Data ns 2 External Clock Frequency ft Note: Rise and fall times (10% to 90%) of MICROBUS sign8rs should be 50 ns maximum. S14-6 3.92 /Ls 410 /Ls 4.08 MHz Timing Waveforms Command Sequence : =-1el--~.~ t DATAB: 1~1-~I) -!~ ~~-~ ~.:tWj.- -----}::=.;.----'----:-- _______________=tC~. ~ ROM Data Timing ADR 0-13 X _ _ _--' "'-_ _ _ _ _ _~ AVALID_ ADDRESS mm\ . \ I -I'"d!- / - I ...dl- RDMDATAI-'~ Nolel: ROM dala 1-8 can go valid any lime afte' ADR 0-13 changes, howeve, It.musl be valid wlth)n Ihel,ed specilicalions and ,emaln valid unlll ROMEN goes high.. TL/B/56"-2 Crystal Circuit Information Typical Crystal Oscillator N~twork External Clock Input (4.0 MHz) SPC SPC V:D ~ TO CIRCUIT EXTERNAL.....! __ CLOCK- Timing Min UnU. IXH 100 ns IXL 100 ns "=" "'-"''''"'IN~+-----''''+~~RCUIT TL/B/5611-3 Cryslal 4.0 MHz RI 1M R2 I.Sk CI 10-30 pF Order Number MM54104D See NS Package D40C Order Number MM54104N See NS Package N40A C2 40-60 pF Block and Connection Diagrams SW1-8 Dual-In-Llne Package 1-----. 'OR 0-13 OSCIN OSCOUT e! n' IIlIm ROM DATA I-a lNTR eMS SWI(MSII SW7 SPC swa 11 SW5 SW4 SW3 oselN e! USC OUT Wii RDMEN SPEECH our 'NTH ADR4 21 ADR3 13 •4 SW2 27 ADR2 15 SW IILSBI 16 ROATA. (LSI) RDATA2 CMS MM541 04 IZ ADATA3 28 ADR1 25 'OR 0 (LSI) 17 11 ROATA4 vss za RDAlAS (MSII : ROATA7 RDATAI ROATA5 TOP VIEW TL/B/561'-4 514·7 • o~ ..- ~ II) ::i :E r--------------------------------------------------------------------------------Functional Description is issued during a speech sequence, the new speech sequence will be started immediately. When connecting WR to a switch it must be a single pole 2 position switch as shown on page 1. The following describes the function of all SPC input and output pins. Note: In the following descriptions, a low represents a logic o (O.4V nominal), and a high represents a logic 1 (2.4V nominal). ROM Data (RDATA 1-8): This is an 8-bit pafallel data bus which contains the speech data from the speech ROM. INPUT SIGNALS Chip Select (CS): The SPC is selected when CS is low. It is only necessary to have CS low during a command to the SPC. It is not necessary to hold CS low for the duration of the speech data. Data Bus (SW 1-8): This is an 8-bit pafallel data bus which contains the starting address of the speech data. Unused inputs must be tied to Vss. Command Select (CMS): This line speCifies the two commands to the SPC. OUTPUT SIGNALS Interrupt (INTR): This Signal goes high at the completion of any speech sequence. It is reset by the next valid command. It is also reset at power up. ROM Address (ADR Cl-ADR 13): This is a 14-bit parallel bus that supplies the address of the speech data to the speech ROM. ROM Enable (ROMEN): For low power applications, this line can be used to drive a transistor that switches the supply for static speech ROMs. See ROM data timing. Speech Output (Speech Out): This is the analog output that represents the speech data. See frequency response section. CMS o Function Reset interrupt and start speech sequence Reset interrupt only. Write. Strobe (WR): This line latches the starting address (SW1-SW8) into a register. On the rising edge of the WR, the SPC starts execution of the command specified by CMS. The command sequence is shown in the timing waveform section. If a command to start a new speech sequence INPUT/OUTPUT SIGNALS Clock Input/Output (OSC IN, OSC OUT): These two pins connect the main timing reference (crystal) to the SPC. Applications Information Frequency Response of Combined Amplifier and Speaker o /i .... ..... ~ /./ 20 dB/DECADE NOTE I ..... 1.. ~ .............. iii -20 :!! ....'" ....Ie C 1I ~ a: -40 ,1< 40 dBIOECADE NOTE 2 1/ -60 100 NOTEr ~ ~, " / 10 60 dB/DECADE ~ 1k \ 10k FREQUENCY (Hz) TlIB/5611-6 Note 1: This curve is the desired response of the entire audio system Including speaker. Minimum response is a low pass fiRer with a cutoH frequency of 200 Hz. For an audio system with a natural cutoH frequency eround 200 Hz, this fiRer can be eliminated. This cutoff frequency may be tuned for the particular voice being synthesized. For a low pitched male voice ij may be 100 Hz. while for a high pitched female or child's voice it might be 300 Hz. Note 2: This is optional fiRering that can be eliminated by proper selection of the speaker. If this 2 pole response is electronically produced, It should be adjusted as described In Nole 1• . Note 3: This Is optional filtering that can be eliminated for simpler systems. The acceptable range for this cutoH frequency is 6000 Hz-8000 Hz. S14-8 rrr.T Typical Applications (Continued) Minimum Filter Circuit VDD SPEECH (FROMSPCI OUT • VDD O.I.F R ~ :OOH11 SPEAKER C 10 ~0.05.F 200Hz =_12".RC °LM346 or equivalent Filter Circuit to Produce Maximum Frequency Response VDD SPEECH (FROM SPCI OUT 1 7000 HZ ~ 0.05.F 1 = 2".R1Cl = 2".R2C2 1 200 HZ = 1 2,;R3c3 = 2".R4C4 = 1 ~ °lM346 or equivalent DIGITALKER System Utilizing MICROBUS Interface Low Power Configuration Using Static ROM l-\1V l-\1V -, r-DO-Dl •I U S Wi! AD INTR CI I VDD SWI-B VCC IIiR CMS INTR ADR 0-13 SPC ROATAI ... MM54104 C1spEECH OSC IN OUT I L __ ose ADDRESS BUS DATA IUS SPEECH ROM I I I I _ ______ JI OUT -- DIOITALKER KIT r. VOD I I ________ JI L.: I SPC IIlIImI 3k SPEECH ROM TL/B/5611-7 S 14·9 • ~ C) ~ r--------------------------------------------------------------------------------Typical Application$ (Continued) :E :E DIGITALKER System UsIng COP420 Interface 7V-llV Vee = 5V VOO Vee SPC liD eOP4Z0 64k ROM WI! MM54104 01 SYSTEM Vee ROATA J+--~ 1-8 ...ooofDATA SWI-8 LPORT DZ CMS DO 'C! ADR 0-12 I!lTR IN3 Vee 64k RDM Vss FILTER AND AMPLIFIER Speech ROM Expansion for Requirements Greater Than 128k Bits RDATA 1-8 SWI-8 ADR 0-12 INTR ADR 13 SPC WI! . lSTMDDULE , "CI 1 r- MM541 04 R 64i. eMS ,. a U S 00 .... D Q ZNDMDDULE ", 1 • 1 \ 1 64. 64k 64k ROM ROM ROM ROM CI CI R fS X X X YO Yl YZ TO ADDITIONAL ROMS, X ... Y3 ! YN A (LSa) a DECODER -r>eK Dl WlI_ en) '7' - Q D C . CK TUB/5611-B 514·10 Implementation of a Speech Synthesizer National Semiconductor Technical Paper 18 Fred M. Wickersham September 1982 The marriage of extensive speech research and large scale integration has made possible substantial end product enhancement with the implementation of low cost speech synthesis integrated circuits. Although driven by a very large and obvious telecommunications market, present day voice synthesizer solutions produce qualities of stored solid state speech at prices attractive to a myriad of consumer, industrial, and military products. It is reasonable to believe that low cost speech synthesizer circuits, such as the National Semiconductor DIGITALKER® system could provide significant product enhancement to many low, medium and high end appliance products. FACTORS DETERMINING SPEECH SYNTHESIS QUALITY The typical integrated circuit speech synthesis system utilizes raw speech that has been highly compressed and digitized. This digitized, or synthetic speech is stored in low cost read only memory (ROM). This ROM data is controlled by and fed into a speech processor chip (SPC) which also performs the digital-to-analog conversion and consequent reconstructed speed output. Most synthesizers require only simple filtering and amplification to output intelligible and natural human speech. The selection of the appropriate phrase or word to be spoken from the synthesizer is generally controlled by an external microprocessor. This microprocessor is typically programmed to monitor various sensing devices, and addresses the appropriate message for a given situation. Some synthesizers, however, will operate without the control of a microprocessor, depending on switch closures or simple logic activation. Figure 1 shows a typical speech synthesis integrated circuit analysis. INTERFACE TO --+ EXISTlNG--+ APPLICATION SPEECH SYNTHESIZER SPEECH ROM SPEECH OUT TUH/5610-1 SyntheSiS Technique With the specific goal of generating speech, using low data rates to be attractive to consumer products, several approaches to solving the problem have been tried. Perhaps the most obvious approach was the straightforward analogto-digital conversion of the raw human speech waveforms. This approach is satisfactory for storing very high quality speech, but the memory requirements are not cost effective for any consumer products. (However, products such as mainframe computers, where large quantities of mass memory are available, could conceivably utilize this approach.) Initial research into the compressing of the raw speech prior to digitizing revealed that the quality is degraded substantially, with only minor compressions and reductions in data rate. A second approach stemmed from thoughts and strong beliefs that speech could be artificially created, using noise sources and filters. Experiments with this theory proved its feasibility and, in fact, low cost circuitry produced reasonably intelligible but inhuman speech at very low data rates. Further research in this technology evolved and provided human vocal tract. models, relying on parametric data extracted from raw human speech waveforms, but highly analyzed by extensive computer software algOrithms. The final set of digitized and compressed speech data, under microprocessor or computer control, stimulates noise and impulse sources and creates speech by channeling the noise and impulses through time varying filters. The data rates experienced by the vocal tract model approach proved very promising for consumer product applications, but voice quality still left something to be desired. Typically, the vocal tract model algOrithms could be optimized for a Single voice, but the difficulty arose in developing a universal algorithm which did a good job in analyzing and reconstructing any voice submitted for synthesis. The quality of the speech produced by an optimized voice model, however, is typically good, for the most part sounding like natural human speech and is largely intelligible. FIGURE 1_ Typical Speech Synthesis System DIGITALKERI!I is a registered trademark of National Semiconductor Corp. MICAOBUSTM is a trademark 01 National Semiconductor Corp. S 14-11 co .... d.. t- r--------------------------------------------------------------------------------During this period of heavy research in the vocal tract model approach, there remained a small community of researchers who continued to believe that raw human speech waveforms could be highly compressed prior to analog-to-digital conversion, without seriously degrading the quality and nat,uralness of the speech. One particular inventor, Dr. Forrest Mozer, made significant progress in this area, and consequently made possible the DIGITALKER speech synthesis system. This technology again takes raw human speech initially, but then, through a series of processes, compresses the original speech by a factor of 100. Thus it is affordable, and lends itself very nicely to a myriad of consumer products, including appliances. Unlike the vocal tract model approach, the Mozer technology is capable of reproducing any voice with high quality because it compresses only the raw speech waveform. No / attempt at modeling the human vocal tract is made with this process. The raw human speech waveforms contain all speech data such as pitch, amplitude, inflections, articulation, plus all of the resonances and other features which tend to make a voice unique. By nature of the Mozer process, which is merely, but uniquely, tracking and compressing the original waveform, all of these qualities are retained, thus producing highly intelligible and natural stored speech. Understanding the synthesis process may not be crucial in determining the appropriate synthesizer for an application, but certainly a thorough listening test is. Extreme care ought to be exercised in evaluating intelligibility, naturalness, clarity, crispness, different voices and foreign languages, in that order. Certainly for a speech product to be successful in the marketplace, intelligibility of the speech is of prime importance. The testing of intelligibility should be performed by a large set of listeners in the natural environment in which the proposed end product will be utilized. For example, if the synthesizer is to perform a paging function in a department store, the intelligibility ought to be measured in the environment with the usual amounts of background noise of people, commotion, music, cash registers ringing and so on. Crispness and clarity are important factors governing the degree of intelligibility and, in particular, control the intelligibility within relative distances from the output transducer or loudspeaker. Naturalness is a feature which can enhance a product by adding personality to the product, as opposed to a computerlike voice which can be monotonous, unrealistic, and even offensive. The idea of different voices for different products is interesting: celebrity voices, "name brand" or even "trademark" voices could segregate competing products. The ability to easily synthesize different voices could protect a Ford from sounding like a Chevy and vice versa. It is expected that manufacturers of competing talking products will take care that the devices will not speak in the same voice. In fact, each manufacturer can select his favorite voice and submit it for synthesis and feel confident his competitor will do the same, therefore alleviating the possibility that both products will sound the same. Many foreign languages contain complex combinations of sounds which some speech synthesizers have difficulty in reproducing. Samples of the desired language ought to be obtained prior to expending large amounts of money for encoding custom vocabularies. Once again, by nature of the process, the Mozer technology reproduces foreign language waveforms without difficulty. , Single Words vs Complete Phrases Having decided on the synthesis process desired, ample thought should be given to the acceSSing approach to the vocabulary which will ultimately be spoken from the end product. Synthesizer ICs are designed with the capability of accessing address locations. The contents of an address location can be either Single words, phrases, or complete sentences. A potential user's first conclusion is, that since a vocabulary of phrases or sentences is made up of individual words, that it should be necessary to synthesize only each new and different word in the vocabulary, as opposed to all words in the vocabulary. Each different word could be located at a Single address location for concatenation by the microprocessor program,or, each word could be concatenated into phrases or sentences as a par.t of the speech ROM program. In the latter case, each constructed phrase or sentence would be assigned a single address location. This approach is feasible and can feature tremendous flexibility, in that libraries of singly addressed, synthesized words could provide unlimited phrases or sentences for a~ end product. ' The disadvantage to the single word approach is the poor quality of the actual phrases or sentences constructed. (To appreciate the effect using this approach, think about slicing words from recorded messages on a tape, then placing these clipped words into different phrases or sentences. Words in the context of a sentence have cast intonations and inflections which would be improper in other , sentences.) As a solution to this problem, and not having the ability to arbitrarily blend single words together naturally, it is necessary to speak, record and synthesize each single word in a monotone, or some other consistent intonation so that, when the words are concatenated, there is at least some consistency to the words. As we humans speak phrases or sentences, we automatically contour the words together with smooth transitions. In fact, we carefully slur words together to provide smooth and flowing speech. The effect that this has to the syntheSis process is that it produces an unbroken waveform, from beginning to end. While we speak phrases or sentences, we also add energy to express our state of mind. This energy is also evident in the waveform of the spoken phrase. It should be obvious that waveforms of single words do not look like those waveforms of the same words when spoken in complete sentences. If natural flowing sentences would be a feature in the end product, the proper approach is to synthesize complete sentences. The result can be compared to playing back a recorded message from a tape recorder. The entire message of the speaking person can be obtained completely, even to retain his state of mind which might be denoting sadness, happiness, urgency; or whatever the relevant situation might require. Since sentences are, in fact, no more than groups of words slurred together consequently producing a Single continuous waveform, the Mozer synthesizing process merely S 14-12 tracks and compresses the same waveform, thus producing high quality natural stored phrases. Memory requirements in the stored phrase approach may be somewhat larger than the single word approach, but not extensively so. The increase in quality more than outweighs any increase in memory. It is always advisable to synthesize and store complete and natural phrases and sentences to produce the highest quality of synthesized speech and possibly insure the success of the end product It is, however, possible to synthesize a combination of complete phrases and individual words for applications such as a talking clock where "the time is" is a complete phrase and single numbers properly sequenced speak the appropriate time of day. There are some special cases where a single synthesized word can appropriately fit as a part of many phrases. These are words that are typically used in the same place in each phrase and have the same intonation each time such as "check oven time" and "check oven temperature" and "check turn off time." The typical speech synthesizer requires only a simple filter, but care and some experimentation should be performed to understand appropriate frequency cutoffs. These cutoffs are high or lowpass filters or combinations of high and lowpass filters which contour the output speech waveform. Suggestions for proper filter cutoff frequencies are given, but, by and large, these frequencies can be determined by varying the filter values while actually listening to the speech output. In this way, the filter values are decided by what sounds most pleasant to the ear. Baffles, or the speaker enclosures are also a pertinent part of the entire system. The output transducer or speaker stand alone, without any sort of enclosure, although perfectly capable of outputting audio, actually depends on some type of enclosure to faithfully reproduce the original required sounds. Speakers without baffles or enclosures tend to sound empty and generally lose the majority of the low frequency components of the audio. For this reason, most quality audio product manufacturers have paid ample attention to the design of the enclosure which houses the output speaker. A speech synthesizer is no different than any other product requiring a quality audio output, in that the quality of speech output is very much dependent on having and designing an appropriate baffle. Voice Qualities The typical process of any synthesizer relies initially on a selected human speaking the actual phrases to be spoken from the end product. Usually, a high quality tape recording is made of the favorite person speaking the required messages. The tape is then submitted to the synthesizer manufacturer for analysis, compression, and digitizing. Even though some synthesizers reproduce any voice quite nicely, there are still suggestions and guidelines to be observed in selecting a desired voice which would probably apply to any manufacturer's speech synthesizer. The best voice in either male or female is a solid, nonbreathy, crisp, clear, medium pitched voice. Some products might suggest a "sexy" connotation but sexiness in a voice is usually associated with extensive breathiness. Breathiness tends to expand memory requirements quickly and significantly, and usually does not duplicate or synthesize with good quality. Deep pitched male voices tend to get raspy, as' sub·100 Hz frequencies are approached, or else become exceedingly breathy, and can, in fact, excede the lower frequency limits of synthesizers. Because women's voices are higher in frequency, they usually require more memory for synthesis and storage. Similarly to the male voice, a high pitched female or child's voice can excede upper frequency limits of the synthesizer circuit. In these cases, the synthesizing process clamps or flattens the frequency to its upper and/or lower frequency limit, which tends to make the synthesized speech not totally representative of the original person. Once again, a medium pitched clear, crisp, non-breathy voice will yield the most pleaSing results. Filters, Baffles, and Speakers The reader of this paper should begin to appreciate how each part of the synthesis process depends on the next. Having gone through great effort to understand the synthesizer circuit which will provide the best quality, having chosen the best voice for the job, and having produced the tape recording for synthesis, one should understand that no less effort should be put into filtering, baffling and choosing the appropriate output transducer or speaker which, in the end, "speaks" the synthesized messages. The final section of the speech synthesis audio system is the output transducer itself. Speakers come in thousands of varieties to include wattage values, frequency response, physical size, and price. Unfortunately, for most consumer products the tendency is to choose a speaker based on price and 'physical size only. Again, not unlike any other quality audio system, the speaker used in the speech synthesis system ought to be chosen in such a way as to complement and/or enhance the actual synthesized vocabulary. In particular, to reproduce the human voice frequency response, one needs to choose a speaker which has a bandwidth from 60 Hz to about 7000 Hz. Although most ordinary speakers feature this range, physical size (speaker diameter) can impact quality severely. Extremely small speakers in the 1.5 inch to 5 inch diameter range tend to lack bass response that is critical when reproducing a male voice. True, the small speakers will respond to the male frequencies but fullness and robustness is not included. On the. other hand, large speakers, unless compensated, do not enhance high frequencies typical in a female voice. Large uncompensated speakers tend to have a muffled effect on higher frequency female or children's voices. This is not to indicate that a small speaker would be perfect for a female voice because, as in the male voice, it depends on a certain amount of low frequency response to maintain fullness and robustness. The recommendation is that the product deSigner actually test different sizes of baffled speakers with the speech synthesizers and make decisions based on the combination most pleasing to the ear. Having selected an appropriate speaker, and having an understanding of baffling effects, the synthesizer ought to be "tuned" to the actual speaker and baffle to be used in the actual production prototype by once again performing listening tests with a variable filter bank between the synthesizer and speaker. In this way, filter cutoff values can be determined based on the combination most pleasing to the ear. S 14-13 ... ~r--------------------------------------------------------------- f!: APPROACHES TO INTERFACING TO MECHANICAL AND ELECTRONIC SYSTEMS Before discussing the interfacing of a speech synthesizer into a specific application, it is necessary to have an understanding of all input and output functions of the particular synthesizer desired. The particular synthesizer of interest in this paper looks like a typical peripheral on an a-bit microprocessor bus. The SPC relies on a chip select to activate the entire circuit )ogIc, an a-bit code which corresponds to some word or phrase applied to the SW1-SWa address lines, and a write strobe to begin the selected speech output. At the end of any address speech output, an interrupt is provided to the bus to indicate that the previously selected message is completed. While the variety of synthetic speech applications are numerous, the actual implementation in any single application is usually limited to one of the following three techniques: (a) single channel, hardware control logic (b) single channel, software control logic (c) multichannel, hardware or software control logic. Each of these circuit approaches for the SPC will be discussed in this section. Certain applications require a relatively small number of sentences or announcements with very little similarity between the different sentences. An example of this applica- , tion might be a talking elevator controller where the messages are brief and non-redundant, such as "going up", "first floor", "second floor", etc. In this application, certain words are used repeatedly but the number of messages is short. This application and others just like it do not require the assembly of short phrases into complete sentences, nor do they require a dynamic message structure as would be required with an automatic bank teller speaking "your change is ten dollars", where a monetary amount may change from message to message. This fixed message application, therefore may require only the minimum control circuit as shown in Figure 2. In Figure 2, the SPC receives a separate coded input for each complete sentence or word that is synthesized. This input code is received by the SPC through the SW1-SWa ports. The circuit' shown in Figure 2 uses a mechanical switch group to interface to the SPC. These mechanical switches could be toggle switch banks, relays, microswitches, or even rotating thumbwheel switches that put out coded outputs. In the simplest of applications, and if the application only requires up to eight discrete messages, the speech ROM could be coded such that a positive voltage on anyone of the SW lines would cause anyone of the a messages to be spoken. After the proper message address is established on the SW ports, a momentary pulse must be applied to the WR line. If this Signal is applied with a momentary action switch, as .shown in Figure 2, then an external pull-up resistor should be used to pull the WR line up to logic high and complete the on-chip debounce circuitry. The WR input signal will latch the coded message address into the SPC on the rising edge of WR and initiate the speech message. Since each complete message uses a unique address code of the SW ports, no further control action is required after this point. The SPC will speak the requested message and return to the idle state. If a new inpu1 command signal is received, either during or after a me!;sage is spoken, the SPC will immediately abort the' curren.! message and begin the new message. This is a priority override, if you will, to allow superseding the present speech output with a more important message. I 7 V - l 1 V - 1 - - - - - _ t - -. . . . . . 5V ":' 1M MOMENTARY' W VOO Vee fiR ONE OF EIGHT SHOWN $WI OIGITALKER eMS Cf ":' Ne SPEECH OUT 'Single pole, 2 po~ition momentary switch T T CI C2 FIGURE 2. Speech Synthesizer wIth Mechanical Switch Interface -s 14-14 TL/H/5610-2 -I In Figure 3, a message is initiated whenever a valid address code is detected by the combinational logic decoder and timed to insure that all transitions have died. Once the valid code is timed, a set/reset latch is set and a WR rising edge is generated to start the SPC. The circuit in Figure 3 shows a lockout circuit to prevent the aborting of a current message, so that all messages must be completed before a new message can be initiated. Once the message has ended, the SPC will set the INTR line to the high state and a reset pulse will be generated to reset the lockout latch. A new speech message can now be started by momentarily applying an idle address code for the next message of interest, followed by a valid code on the SW input ports. The use of a microprocessor controller expands the versatility of the SPC significantly. Messages that are composed of numerical responses or fixed phrases in random sequence can easily be constructed from a library speech memory. In addition, various tones or warnings can be synthesized and added before, during, or after an announcement to identify the urgency of each message. For example, an automobile message may state that "oil pressure is low". Alone, that message may mean only that pressure has dropped but no immediate hazard exists. If, however, pressure has dropped below a critical value, the message could be compounded to say "warning-oil pressure is low, pull over and stop the engine". In this latter case, phrases of high urgency are added to the initial message to inc~ease its level of importance. Of course, the second message is not completely separate from the first but is, instead, an expansion of the first. This technique allows fewer input address codes to initiate a larger number of messages without assigning a separate address code for each message and for each of its derivatives. This would be particularly important to an electronic bank teller, since a large number of monetary amounts must be synthesized for a relatively small number of finished sentences. While the simple control schemes discussed so far can be used in many applications, a far more important group of applications will take advantage of the SPC's ability to construct sentences from cast phrases and groups of words. This type of application uses an intelligent controller or a microprocessor to string together a group of synthesized phrases, or combinations of phrases and individual words. The electronic bank teller previously mentioned is a good example of this application. The microprocessor controls the stringing of SPC address codes and applies them, one at a time, to the SW address ports of the SPC. Handshake timing between the microprocessor and the SPC is provided with the interrupt line. This microprocessor interface arrangement is shown in Figure 4. 5V LOCK·OUT LATCH Wli DIOITALKEA ':' INTA OSC Vss IN OSC OUT SPEECH ':' R2 AI OR Gales: MM74C32 NOR Gales: MM74C02 TLiH/5610-3 FIGURE 3. Speech Synthesizer with Logic Control Interface S 14-15 ...."U• 00 .... co a.• a typical interface approach to a common low cost 4-bit microprocessor. The final application technique to be covered is the multichannel configuration. The previous arrangements used an SPC and dedicated speech ROMs to provide a single channel of synthetic speech. Appliances, autos, toys, terminals, etc., would probably use a single channel SPC arrangement. But an entirely different group of products could take advantage of a multiple channel approach to reduce the ROM requirements. This group of products includes multiple elevator controllers, electronic bank tellers, multiple pupil learning centers, voice response telephone answering centers, etc. In this application, each channel would use a separate SPC and amplifier circuit, but several channels would share a common speech library ROM. A typical configuration is shown in Figure 6. , The library ROM of Figure 6 is shared over eight SPC channels. Through a series of octal buffers and registers it is possible to interface up to 8 SPC devices to a common speech ROM. The hardware and timing requirements in this application are rather uncomplicated and straightforward as shown in the diagram. The system can be further expanded to as many as 16 lines with the addition of a 4-to-16 line decoder. The entire application hardware and wiring can then be even further simplified by multiplexing address and data over the same parallel bus. This system is demonstrated by Figure 7. This approach is particularly attractive whim each SPC channel is located on an individual circuit card. A telephone central office or PABX announcement system is a typical example of a single channel per card per channel arrangement, but the idea is certainly not limited to just that application. 5V ~ DATA BUS SWl-B WRITE STROBE ~. Af Ii iii DIGITALKER CMS i CHIP SELECT INTERRUPT B INTR XTAL D TLlH/561 0-4 FIGURE 4. Typical Microprocessor Interface Although the SPC works typically in an 8·bit microprocessor system, it will work equally as well in a 4·bit microprocessor system. 4-bit systems are usually very low cost solutions for lower end consumer and industrial products. Figure 5 shows REFERENCES Smith, Jim and Weinrich, David W., AN-252 Speech Synthesis, National Semiconductor Corporation, December 1980. T 5V VDD VCC Vcc SWl-B LPORT DO 01 iii B OIGITALKER SYSTEM 110 02 **{ 03 INTR CKO' SPEECH OUT 'Configured as input line "Additional speech ROM page select lines. TL/H/5610-5 FIGURE 5. Interface to 4-Blt Microprocessor S 14-16 ~-------------------------~ ONE CHANNEL ~~~ ~~. .-+4--I Sl'£ECH ROM DATA I-II-. .~~. . .~ VCC • 81 LS95 octal buffer •• 74LS374 octal register 1 MH.CLOCK FIGURE 6. Multichannel Speech Synthesizer TO ADDITIONAL CHANNELS I" I------------------------------., --------------------------- r L-------------------------, r~-------------------------- lONE CHANNEL I ~"--"~~----"~Q SIC AND CONTROL SPEECH ROM ,... ClK ~.J ...... ------_. VCC 12 11 11~o========3:} ~ 9 CHANNELS ADDITIONAL 11&7411 VDO (7V-IIVJ Ik • 81 LS95 octal buffer •• 74LS374 octal register c1~::---4~~~----~-=~----------------~:>_-------------------t-------J TL/H/5610-6 FIGURE 7. Multichannel Synthesizer with Unified Bus 514-17 • Section 15 Special Analog Functions Special Analog Function Section Contents LP395 Ultra Reliable Power Transistor ••.....•...•......••.•.•.....................•........' ..•......•..•.... S 15-1 ~National PRELIMINARY ~ Semiconductor LP395 Ultra Reliable Power Transistor General Description The LP395 is a fast monolithic transistor with complete overload protection. This very high gain transistor has included on the chip, current limiting, power limiting, and thermal overload protection, making it difficult to destroy from almost any type of overload. Available in an epoxy TO-92 transistor package this device is guaranteed to deliver 100 mAo Thermal limiting at the chip level, a feature not available in discrete designs, provides comprehensive protection against overload. Excessive power dissipation or inadequate heat sinking causes the thermal limiting circuitry to turn off the device preventing excessive die temperature. The LP395 offers a significant increase in reliability while simplifying protection circuitry. It is especially attractive as a small incandescent lamp or solenoid driver because of its low drive requirements and blowout-proof design. Features • • • • • Intemal thermal limiting Internal current and power limiting Guaranteed 100 mA output current 0.5 IJA typical base current Directly interfaces with TIL or CMOS • + 36 Volts on base causes no damage • 2 ,,"S switching time Connection Diagram The LP395 is easy to use and only a few precautions need be observed. Excessive collector to emitter voltage can destroy the LP395 as with any transistor. When the device is used as an emitter follower with a low source impedance, it is necessary to insert a 4.7 KO resistor in series with the base lead to prevent possible emitter follower oscillations. Also since it has good high frequency response, supply bypassing is recommended. . Areas where the LP395 differs from a standard NPN transistor are in saturation voltage, leakage (quiescent) current and in base current. Since the internal protection circuitry requires voltage and current to function, the minimum voltage across the device in the on condition (saturated) is typically 1.6 Volts, while in the off condition the quiescent (leakage) current is typically 200 IJA. Base current in this device flows out of the base lead, rather than into the base as is the case with conventional NPN transistors. Also the base can be driven positive up to 36 Volts without damage, but will draw current if driven negative more than 0.6 Volts. Additionally, if the base lead is left open, the LP395 will tum on. The LP395 is rated for operation over a -40·C to range. + 125·C Typical Applications TO-92 Package CompOSite PNP EMITTEH~COLLECTOH .M'---+-- EMITIER 4.7k BASE --'WH~-t BASEKJ BonOM VIEW TI./H/5525-1 L.._ _....._ _ _ COLLECTOR Order Number LP395Z See NS Package Z03A TUH/5525-2 Fully Protected Lamp Driver V+ TH/H/5525-3 S 15-1 • Absolute Maximum Ratings Collector to Emitter Voltage Collector to Base Voltage Base To Emitter Voltage (Forward) Base to Emitter Voltage (Reverse) Base io Emitter Curr:ent (Reverse) 36V 36V 36V 10V 20mA Collector Current Limit Internally Limited Power Dissipation Internally Limited Operating Temperature Range -40"C to + 125·C -65·C to + 150·C Storage Temperature Range Lead Temperature (Soldering, 10 seconds)" 260·C Electrical Characteristics Symbol Parameter Conditions Typical Tested Limit (Note 2) Design Umlt (Note 3) 36 36 (Note 1) V(Max) ~5 mA(Min) mA(Min) mA(Min) Units (Umlt) VCE Collector to Emitter Operating Voltage 0.5 rnA :S: Ic :S: 100 rnA ICL Collector Current Limit (Note 4) VeE = 2V, VCE = 36V VeE = 2V, VCE = 15V VeE = 2V,2V :S: VCE :S: 6V 45 90 130 60 100 20 50 100 Ie Base Current O:S: Ic :S:,100mA -0.3 -2.0 -2.5 pA(Max) 10 Quiescent Current VeE = OV,O :S: VCE :S: 36V 0.24 0.50 0.60 mA(Max) VCE(SAn Saturation Voltage VeE = 2V, Ic = 100 rnA 1.82 2.00 2.10 V(Max) BVeE Base to Emitter Breakdown Voltage (Note 4) o :S: VCE :S: 36V, Ie = 36 36 V(Min) VeE Base to Emitter Voltage (Note 5) Ic= 5mA Ic - 100 mA (Note 4) 0.79 0.90 1.40 V(Max) V (Max) ts Switching Time VCE = 20V, RL = 2000 VeE = OV, + 2V, OV (JJA Thermal Resistance Junction to Ambient 2 p.A 0.69 1.02 2 p.sec .. 0.4" leads soldered to printed circuit board 150 180 ·C/W (Max) .0.125" leads soldered to printed circuit board 130 160 ·C/W (Max) Nole 1: Parameters identified with boldface type apply at temp. extrames. All other num~ers, unless noted apply at + 2S'C. Note 2: Guaranteed and 100% production tested. Note 3: Guaranteed (but not 100% production tested) oyer the operating temperature and supply voltage ranges. These limits are not used to calculate outgOing quality levels. Note 4: These numbers apply for pulse testing with a low duty cycle. Note 5: Base positive with respect to emitter. S 15-2 Typical Performance Characteristics 5 Volt Transfer Function 160 _ 140 :;::F !1211 100 G &0 Iii I }.'I o o 0.2 0.4 O.S 0.&1.0 1.2 1.41.61.& BASE·EMmER VOLTAGE (V) Available Collector Current ,.. 160 _ 140 i ," 100 I: o - ! f- ~ I- GUARANTEED o "' "' I , t"I!. 25~~~ 125' - I.. 0:5 0.4 ~ 0.3 3 0.2 8 11: 1.OV 60 40 211 O.&V ~ 8 o 0.20.4 0.6 0.& 1.0 1.2 1.4 1.& 1.8 BASE-EMlnER VOLTAGE (V) 06 0.1 I I I I I GUARANTEEO II II I - I' r o 5 10 15 20 25 30 35 40 COUECTOR-EMlnER VOLTAGE (V) I" ." • O.~ o .OV-O.6V r- 5 10 15 20 25 30 35 40 COLLECTOR·EMlnER YOLTAGE (V) Saturation Voltage i 2.0 1.& !:I 1.6 ~ 1.4 i!5 !iii ~ 1.2 - I 1-""- .. .... I-"" .... c:::: """" ~ i""'" TA= -25'C ~ ..- ~ i-'" 1.0 0.& 0.6 5 10 15 20 25 30 35 40 COUECTOR·EMlnER VOLTAGE (V) ~ O.~ 2.2 (VaE=O) oJ GUARANTEED ~~!, 10" 1.1V _140 !1211 Quiescent Collector Current I" B 80 20 PlCJL- o Collector Characteristics 160 :::I '.1 0.& _ 0.7 (VaE=2V) i"o.. !1211 r'C I 10 o I ( Tr 2 T. =_25°C I: TA=-25'C, 20 T 60 1: tA=~5't I: I, -t=1~5'!- (VcE=36V) 70 ! T~=¥C 1 36 Volt Transfer Function au (VCE=5V) o T~=25'C I.... t =125'C 211 40 60 60 100 1211 140 COLLECTOR CURRENT (mA) TLiH/5525-4 Typical Applications Lamp Flasher (Short Circuit Proof) Note: One failure mode incandescent lamps may experience is one in which ·the filament resistance drops to a very low value before It actually blows out. This is especially rough on most solid-state lamp drivers and in most cases a lamp failure of this typa will also cause the lamp driver to fall. Because ollis high gain and blowout·proof design. the LP395 is an ideal candidate lor reliably driving small Incandescent I~mps. Additionally, the current limiting characteristics of the LP395 are advantageous as.it serves to limit the cold filament inrush cU/Ten~ thus increasing lamp lile. V+2:12V LP395 Simplified Circuit r--------------, I COLUCTllR I TLiH/5525-6 I I I I I I I I Optically Isolated Switch ~------~-----V+ 5DO OUTPUT 0.5 I EMITWI L. I _____________ _ TL/H/5525-5 L....____. . .____ YTL/H/5525-7 515·3 ~ r-------------------------------------------~------------------------_, 0) ~ ..J Typical Applications (Continued) Two Terminal Current Limiter + ~ S 15-4 TL/H/5525-08 Section 16 Physical Dimensions ~National ~ Semiconductor All dimensions are in inches (millimeters) PIN NO.1 IDENT -----;... 1ii2.3i9i1 0.485 ~T ~ J 0.008-0.015 (0.203-0.381) I (7.620) 0.300 I---JI TYP ~ MAX ~ 0.054 (1.372) REF L 0.165 (4.191) 0.020-0.060 t=l'--U'" o.015-0.023, (0.381-0.584) II -11-- 0.100 ±O.o10 0.125 (3.115) MIN (2.540 ±0.254) TUH/5271 014E(REVDI NS Package D14E PIN NO.1 IDENT 0.005 R 1...1 0.290-0.320 (7.366-8.128) il r- r- mnn MIN~ 0.050 ±0.005 0.165 0.4851".210 ±0.121) TVP (4.191) ~~ MAX M~ 0.!~5~~::;:::;::;;:::::;:::l:::::!;t;-. 0.008-0.015 (0.203-11.381) m.121) MIN 0.080 (2.032) MAX TVP j L ~.JL (0.381-0.584) 0.100 ±0.010 (2.540 ±0.254) (0.100/(2.540) Bse TVP REL TO LEADS I AND 16) NS Package D16C 516-1 0.020-0.060 (0.508-1.524) 0.125-11.200 (3.175-5.080) 0.150 (3.810) MIN O16C(REVG} •C r---------------------------------------------------------------------------------- o 7ii i 1.010 1---------(25.6541'----------1 E MAX is I .c a. 0.054 i 372i1 ~ '~ OA85 ,.:(~; ;: :.:;: '-L.:;: .:.;:;c.,:·1 W W ~ VVVVW· 0.015-0.0oa (0.381-0.2031 . - I--~;~: --l 0.,00.0.010 (2.540 ±O.2541 REF I -l I II 0.023-0.015 -11- ~y~84-0.3811 I- 1 0.165 r---112.3191----j (4.1911 0.125 (3,1751 MIN D20AIREVBJ NS Package 020A NS Package 022A has been replaced by NS Package J22A. NS Package 024A has been replaced by NS Package J24A. ~ 1 RAD../ . 11.5241 OPTIONAL ~1:.21~0~_-------------~ (32.261 MAX 24 0.060 ____________ 23 22 .!!. 20 19 18 .!!. 1.!, .!! .!!. .!!. 1 ..JJ A,1 L..,,,.....,,,....,,,,....,,,,....,,,,,....,,,...-=....,,,,....,.,....,,,,,,....,.......... 10 11 12 0.005 (0.1211 J.1MI~ H ( 0.010 +0.003 ~:) 0.254 -0058 . -II'. ~::~: 0.600 --(15.24 ~~~) I' --1 0.050 (1.2701 - I Ir.-ii r++-_....l.l.~_ _ _.....;._ _ _lY_P_M_IN_...!__i~:IMAX 0.060 ~ (0.1521 SEATING_ PLANE .~ MAX I I --j I(2.~~~.2541 0.100±0.010 --l~5 II 0.015-0.020 -11--(0.381-0.5081 (3.1751 TYPMIN D2<1DIREVCI NS Package 0240 516-2 ." ::J' 1. ~ c 3· CD ::s en o· 0.110 (15.491 - r- ::s en ~~~~~;;i-,;;n;;rr;~J 0.045 (1.1431 MAXTVP 0.200 (50801 MAX 0.058 (I.27OjTVP II .... 11l:-0.590-0.620 1---(14.99-15.751-1 REF 0.1108-0.015 0.203-0.3811 \ TVP f- ~rH~rH~}HH~~HHHH~Hr U -~~~~~~!~T1CAL ~ t PLANE O.DI&-O.D23 . II . (0.381-0.5841 1 1 TVP OUTWARD TVP ill f 0.100 .!O.DIO _I (2.540 .!O.2541 1 SEATING 0.020-0.0&o ---41 (O.50jl.52 TVP ,0.12& (3.1751 MIN NS Package D40C - [--? :EITr t 0.,78-0.1951 0.Il10-0.1115 ~ OlA J. ---I- (0.6351 MAX SEATING PLAHE~ . 1 f - t UNCONTROLLED LEAD OIA 0.1iGO 0.011-0.019 (D.4116-0.4831 -lJ-~ (l:iJ:' ~ OIA TVP H02AIAEVC) NS Package H02A 516-3 • !! o 'ii c 1 1 C» O.l50-ll.370 DIA IB.HO-II.39BI E is B 0.155-0.1'5 i SEATING PLANE rrr "f 0.315-D.335 DIA 11.101-1.5091 ....... .I 0.500 f 11:!!!!!. r"::.m"., 10.1351 LEAD DIA t 112.701 Mt 0.018-...19 IOAOI-llAl31 DIA TVP NS Package H03A '8 0.209-0.219 DIA (5.308-5.563) , I I SE:LT~:hmIH l .. 0.025 MAX (0.635) UNCONTROLLED LEADDIA y- 0.016-0.019 . (0.406-0A83) DIATYP .. 0 0 0_ --11-- 0,118-0,195 (4.521-4.953) DIA . 0.080-0.105 (2.032 - 2.667) 0.500 (12.701 MIN ~ (0.7621 MAX 0.100 1---+---(2.540) TYP HIl3Ii(llEVCJ NS Package H03H 516-4 SEATING PLANE '_--l*___ 0.400 (10.161 MIN ~_~0:::.2=24~-::.:0:::.2~34 (5.6911 -5.9441 0.016-0.019 (0.408-0.4831 OIA TYP 0.201-0.217 (5.528-5.5121 H04DfREVD) NS Package H04D 0.165-0.185 (4.191-4.6991 REFERENCE PlANE--f---..- 0.195-0.205 IDIA 0.100 TV (2.5401 p 1----~(4.953-5.2011; P.C. HOBC(AEV~ NS Package HOle II S 16-5 , 0.545-0.555 !--(13.843-14.097)------j DIA 1_ . 1 '-I~ t-' , 0.148-0.181 (3.759~.597)J 0.500 . T. 0.030 ~~~~~ ---II-- , 0.030 MAX (0762) UNCONTROLLED LEAD DIA (~Z~) .i 0.016-0.019 (0.406-0.483) 0.595-0.605 (15.113-15.367) DIA --'----'1.---- ~ '< 0.026-0.036 (0.660-0.914) ~A (0.610-0.914) H12BIREVA) NS Package H12B rrr ~ll" 1 . (2t.6ltO.HI) 0.470±0·005 (ll.94±0.127) LID 0.100 (2~) t . 2 . 0.130±0.005 (3.302±0.127) t 0.490±0.005 (12.45±0.127) . EPOXY SEALANT ALL ARO~NO 0.065±0.010 =t==p;:~=:::;:::~~O.Z54) =i=; 0.030±0.004 (0.7S2±0.102) 8ERG LEADS ---If l-r 14----=::::7.;:;;:. ---...,... T 0.125 (3.175) MIN ~-l I.- 0.10II±0.0I0 (2.540±0.254) TYP HYOSA(REVB) NS Package HY08A . S 16·6 -----------------------------------------------------------------------.~ :::F ~ ~ c 3" MAX GLASS CD ;::, 0.025 (0.635) RAD til 0" ;::, til LI 0.290-0.320 (7.366-B.12B) I" (::~~:)M~X 11__ 0.00B-O.012 (0.203-0.305) --l 1· 0.005 I (0.1271 M N GLASS SEALANT 0.030-0.070 (0.762-1.178) T~;J '11 I-- _0._05_5 (1~~7~ 0.200 (5.0BO) MAX ~'~;:~~;;S~I----t ~ 860-;\ il.1 . .950 ±SO 0.310-0.410 (7.874-10.41) 0.010 (0.254) RAO TVP ~ It. --II-- 80TH ENDS __.____;-__~ O.OlB ±II.OOl 0.125-0.200 (0.457 iO.076) (3.175-5.0BO) (0.50B-l.524) 0.100 ±0.010 (2.540 ±0.254) JOSA(AEV H) NS Package J08A 0.7B5 (19.939)~ MAX 12 0.025 (0.635) RAO 11 10 9 8 ~ 0.220-0.310 (5.588-7.874) '--r:-r'"T':'T'"T";"T'""r,I~":T"'1'";"Ir--' ~ 0.290-0.320 ~ ~7.366-8.12B~ .!!:!!!!.MJ. I I I (4.572) 0.125-0.200 (3.175-5.080) (2.489) MAX BOTH ENDS 0.150 (3.81) MIN NS Package J14A S 16-7 JI4A IREV., • 0.025 (0.635) RAIl 0.005-0.020 (0.127 -0.508) RADTYP 0.200 (5.010) 0.001-0.012 (0.203-0.385) MAX J ~ D'01lfO'D03 O.GIG 12.032) MAX BOTII . ENDS. '0.310-0.410 (7.174 10.41) II (0.457±D.078) --11-' 0.1OO±D.010 (2.540± 0.254) J1IACREYJ) NS Package J16A 0.020 . (0.508) HAD MAX TYP 0.025 RAD---!:l (0.635) ..!:!!!. MAX (5.0&11) . 0.020 -8.GIG (0.508-1.524) 0.125-0.200 (3.175~5.080) O.1OO±O.010 12.540±0.254) 0.018±O.0/J3 IO.457±o.o78) TYI' JI' . 0.150 (3.810) MIN J1IA(REYK) NS Package J18A S16·8 ----------------------------------------------------------------------,~ :::r ':i [ ~---------I~~~I MAX--------~~ o 3· CD :::J UJ o· :::J UJ O.IBO (4.5721 MAX 0.290-0.320 17.366-B.12BI ,.,_......L-,150 --U(3.Bl01 MiN I~ 17.874-10.41)-' 0.310-0.410 I 0.100 ±0.010 TVP (2.540 <0.2541 O.OIB 10.003 10.457 lO.0761 ITVPI J20A(REVLI Ir-~~u....L~=..I.!!:L.IM.:.:ALX=I_J..::L.=..L:: I 1.110 1--------------128.19)-------1 . 0.030-0.055 10.162-1.397) 0.420 MAX ::..."'~(lO.668) GLASS ..... 0.400 (10.16) RAD ~~~~~,.rr.~r.r~~~7rItM-m~~ RAD TYP r 0.390-0.420 19.906-10.668)-j Ie : 11 ..!:ill. GLASS ~NT 15.715) MAX 0.020-0.010 10.608-1.118) 0.180 MAX 14.512) _"lT //'M".......... 0.126 ii.ffii MIN MAX 80TH 0.100. ENOS 12.540) ~ TY' NS·Package J22A S 16·9 0.125-0.200 13.175tOBOI --.11- NS Package J20A 0.025 10.635) 0.200 15.0BOi MAX J22AIREVF) .. 1.290 1-01-0--:--------(32.7661--------;...' 0.025 . (0.6351 0.600 i~ 0.514-0.526 RAD 0.030-0.055 (0.762-1.3971 RAD TVP ~ 0.590-0.620 ~ 0.005 ~Ir· ~ ~= ~5" l5" I. +0.025 0.885 -0.080 +0.635) ( 17.40 -1.524 .1 0.008-0.012 (0.203-lt.3051 0.098 (2.48111 MAX J I J24AIREVH) NS Package J24A I------------~;~'--'----------.-l, ..AX " :I I::::' RAD 0.OJO-I.155 ii.iiH.ii11 O.IlI-USO 113A&l-I3Jl0) ~~~rr,~7nr.T~nr.TT~~~~~~~~~,;~~~~~~~S RAD TY' 1.225 15.115) MAX ID"MAX 0.100 ! 0.010 12.540 ! 1.254) TV' NS Package J40A S 16-10 I --j "0 ~ [ UBO-G.925 ~ (22.35-23.501 0.160-0.115 119.304-19.&151 ~-tf-----i 0.220-0.210 ~ (5.588-1.1121 (2.159-2.541 SEATING PLANE T~ N: : -II- 3' CD ::s (II o· ::s (II I _ _ _L_ +_ t' _ _ l c 0.025 (0.6351 ~ MAX UNCD,NTRDLLED LEAD 0.03&-0.044 , 0.122 ~ (3.0911 MAX (0.914-1.1111 TVP 0.410-0.510 ~ (12.446-12.9541 LEAD CIRCLE 40'(7.) KOaAIREYCI NS Package K08A (::!:=::~s:. 0.017 !- (0..321 I x45° 0.l1li7-0.010 (0.178 -O.~I TYP r 0.024-0.031 0.053-0.069 t t ~~ 0'-8' TYPALLLEADS Q t lfEo.020_0.D50==t)1J (0.5011-1.21111 TYPALLWDS 6h rO,O~ J (1.2701 TYP ~ =8b] (0.102-0.2541 AFTER LEAD AMISH ~'---.l L JL o.olL.mg (0.356-0.4931 TYP N14A!REV0) NS Package M14A S 16-11 • NS Packages N08A and NoaS have been replaced by NS Package N08E. { (:::=~O~I] i2.2iii 0.090 8 .!!!!!!. DIA (2.337) PIN NO. 7 6 5 ~ + 0.032+0.005 (0.813±0.1271 0.250±0.OO5 IIOENT~\.:) (6.35±0.1271 OPTION 1 ~7 RAD PIN No.lIOENT~ --'- 1 2 3 4 1 ..!!:l!!!.TYP-l1(1.0161 ' 0.125-0.140 (3.175-3.556) 0.020 (0.5081 MIN NOSE IREV E) NS Package N08E 0.090 0.092 (2.337) (2:: 1.Fm 14 ~fT NO.'IDENT~B 13 0'743-0'770~' 118.87 _ 19.56) lZ 11 18 0.280 PIN 0 MIN 0.300-0.320 II 0_-0.015 ~J T '-m.229~.311) I. 5 +0.025 0.32 -0.015 (, +0.635) \8.255 -0.381 4 0.250.0.005 (6.350>0.127) .1 0.075.0.015 (1.905 .0.381) ~L II ', OPTIONS 2.3 0.145 - 0.200 13.683 - 5.080) 16'94' _11_ 0.018±0.803 0.100 <0.010 (2.540±0.254) (OA57 '0.076) 0.125 - 0.140 (3.175 _ 3.556) Nl .--.L.t_ r 0.009_0.01 (0.229-0254) II- 0.325 -0.015 +0.025 ~ (1.255 +0.635) ~ -0.311 TVP 0.060 ±0.005 (1.524 to.1271 0.130 ±D.005 (3.302 ±0.127) -----t-----.L 0.145-0.200 TVP II 0.018 ±0.D03 0.125-0.140 (0.457 ±O.o76)-11-(3.175-3.556) I f 0.020 (0.508) (3.683-5.010) I MIN N20A(REVE) NS Package N20A S 16-14 t-------(!i~~-!:~:I------~·-ll 13 0.062 (1.5151 RAD PIN NO. IIDENT r. c±> c±> 11 I 0.540,0.005 ~~l~F.F~fT.rr=F.T9F.FT~r.rr~~ffiFTffi~~! ::Jl'0"211 DOTTED OUTLINES REFLECT ALTERNATE MOLDED BODY CONFIGURATION 0.5BO n4.131 MIN 0.030 (0.1&21 0.600-0.620 MAX F~ 95',5' 0.625:::~: _I I-- (15B15+O·635)~ . -G.3BI N2.tAIREYEI NS Package N24A PIN NO. IIDENT D.D3~~ MAX I- 0.600-0.&20 ----j (O'lFtC~~1 0.145-0.210 ••-w. ._~-5'3341 (0.229-0.381) D.D50±0.D15 (l.fTO±0.3811 I- 0.125-0.145 (3.115-3.683) N28B(AEVE) NS Package N28B S 16·15 • \' 1.1112 (1.57&) PI. ND.llDEIfI 1 e C±> RAD ~ 1 ,Zl .,:;;=m==r.i"'r.i'firii"'ffi"F.'i"Tn=m="ir.iffiiFiiir'ffii''T.li'''T.fiT''ili'iffi9lin;;;=iii::lJ • DoOl5 ...,5 11.10....3111) NS Package N40A I-- 0.385-0.428 --l I 1----1- 14.5~±O.127) 0.151 ±0.002 13.835± 0.051) O.05Q±O.OO2 i1.iffi05ii D1~ -0 O:UO±D.Ol0 (2.794±0.254) O.l80±O.Q05 I 110.03-10.67) O. 16. O. lB. ~ 1.020 ±O.015 125.91 ±0.381) 0.032±0.Q05 - O.145±0.015 13.l83±0.3Il) l JlG 0.385 110.03) lIEf ~~ 12.54±0.2fi4) O.200±O.01U 15.0I±0.254) 11 s.ctlon D.032±O.DD5 10.113±0.127) I I-- ~ A-Alftt-;:-T T038-'.ncI-2~~ T 540±0.015 3.72±0.381) ! 1 (O:iiiro:m)~ '-- 7" ~ (1.27) 0.100±0.D1D !!:!!!!TYP 0.016:::: (0.311 :~:) SEAlING PI.AIIE L.! ~ . O.032±0.OO5 ---l~.J:::.l iD.iii±o:ffi) ~_ ..;;;-T T s.ctIDII A-A T038-30nIJ ,,..---- 0.105 :::::: 0.02Z:::: (2.&&7 ::::~) (0.559 ::::) 0.015 ::::~ (, +0254) ,0.381 -0:051 T03B(REV'" NS Package T03B S 16-16 ) 0.151 .0.002 (l.8l5.0.051) olA TAPERED I' ZSloES I IT') 0.540.0.015 lC ~:~~: .~ 0.015 .-olB1 .0254 (. -11.051) 0.035.0.005 10.889 !0.127) TVP -- _ 0.105.0·010 -0.015 .(~ ,<"" -1I.l81 1 0.067.0.0115 11.702 iO.1Z7l TVP T05A (REV 0, NS Package T05A 0.395-0.420 (10.03 -10.67) ~ (2.1~~.254) I 0.151 ±0.DD2 (3.835±0.051) _ rt .050±0.D10 ~----.LJ·=±(t'·27D±tO'254) I D.250±0.0ID (6.350±0.254) t 0.340±0.0ID ~ 0.863 (8.636±0.254) ~'T _I II __ _ (:::: ~::ili)- ~ L~.!.:!!!!. -0.051 (2.667) O.035±O.OO5 TYP (0.669±0.121) _ _ _~_L ~ (4.394 -4.597) 0.321-0.335 ~ SEAnNG PlANE T05B(REVEI NS Package T05S 516·17 • !o "iii 0.781 ± 0.01 0 cCI) E O.177±O.1III5 IU9I±O.I27) 120.01S±O.Z54) ~ is "5 V. i Q. D.6li±O.OI0 -117-.1--lO±O.254) O.110±O.005 11.79UO.I27) t-,0.151±O.002 13.835±D.051) 1""" '\ ~ + - I~ O.410±O.OI0 110•41Io.Z54) ~ ~ O.III6±O.02O . 111.19S±O.508) O.03IM±O.Ol00 11.001 ±O.2S4) 0.166±D.010 (4.21840.254) ~ ~ I:::;::~- I- O.ISO±D.Ol0 (4.1164±0.2S4) !--;D.D67±O.OlD 11.702±O.2S4) .0.670 ±D.OID (17.DII±0.154) C ~ n=t: ~. ~~ t (0.610) NOM . t- - -.1 .,.- a.lOO±O.OI0 ~ o.8i1oH.020 121.644±O.506) ot. ~(~::;~: 0.021 ~::: (0.533~::~~- r I-- - J 0.015±1I.005 ID.381 ±0.127) RADIUSTYP I-: D.1OO ±D.OO5 ' (2.540±0.127) a.169H.Ol0 14.293±a.254) 0.2OII±D.01D 15.OBD±D.Z54) R R l TItA(AEV8) NS Package T11A 0.175-0.185 (4.445-4.699) SEATING PlANE ~ I" "I r---' ) I I I 0.175-0.185 (4.445-4.699). 0.065 (1.651) DlA -.-l. t' L ___ ..J .!!:!!!!. .!!!!!!. 5" NOM ~ ' J 5" NOM 0.025 (l~f (~:) ~ ~ ~ UNGifi~ED ~ -LJ~l--- (0:35~Yi4D6) -II-- ~3683-0.3937) ~ (1.143-1.397) J .!!!!!!. (2.286) 0014-0016 0.0145-0.0155 BEFORE LEAD FINISH 0.045-0.055 ~~. JJwt (3.429-3.683) 10" NOM 10", NOM Z03A(AEV D) NS Package Z03A S 16-18 0.135-0.145 0.050-0.100 0.150-0.180 11.270-2.5401-~~-----t-13 810-H721 13.429 - 3.6131 0.190 -0.210 ~ OIA PC 0.D9D 12.216) R "OM 0.175-0.185 14.445-4.699'·-+---- I:.~:=:.~~:) LEADS 1 AND 3 AND DlA PI: d- 10· "OM (~::=~:~) 0.0145 -0.0155 10.368 -0.394) ~V::~I::~ ZOJDIREVIIII NS Package Z03D S 16-19 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I
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