LOGIC
DATABOOK
VOLUME I
CMOS AC Switching Test
Circuits and Timing Waveforms
CMOS Application Notes
MM54HC/MM74HC .
MM54HCT/MM74HCT
CD4XXX
MM54CXXX/MM74CXXX
LSI/VLSI
Appendicesl
Physical Dimensions
3
III
fII
&II
III
•III
•
III
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4
Introduction
This comprehensive databook provides information on
National Semiconductor's advanced CMOS logic families
MM54HC!74HC high speed, CD4000, MM54CI74C and the
many unique CMOS LSI products. The MM54HCI74HC
family utilizes microCMOS technology to achieve the in·
put and power supply characteristics of CMOS with the
high speed and large output drive of low power Schottky.
The MM54HCI74HC family has the same pinout as equivalent 54LS174LS; in addition, many popular CD4000 series
logic functions are offered where no equivalent TTL function exists.
viele andere CMOS-LSI-Produkte. Die Hochgeschwindigkeits-Logikfamilie MM54HCI74HC basiert auf der
microCMOS-Technologie, die die Eigenschaften der
CMOS-Technik in bezug auf die Stromaufnahme und das
Eiingangsverhalten mit der Geschwindigkeit sowie der
Ausgangs-Treiberkapazitat von Low-Power-SchottkyBausteinen vereinigt. Die MM54HCI74HC-Typen besitzen
die gleichen Anschlufjbelegung wie die aquivalenten
54LSI74LS-Bausteine, aufjerdem werden viele Funktionen
der CD4000-Familie angeboten, fUr die keine entsprechende TTL-AusfUhrung existiert.
The MM54HCTI74HCT is a subfamily of MM54HCI74HC
offering TTL inputs. These MM54HCTI74HCT devices of·
fer convenient TTL level translation to CMOS for those
places in the system where only TTL levels are provided.
Die Serie MM54HCTI74HCT ist ein Teil der MM54HCI
74HC-Familie und besitzt TTL-kompatible Eingange.
Daher eignen sich diese Bausteine insbesondere fUr die
Pegelanpassung zwischen CMOS- und TTL-ICs, z. B. wenn
Schaltungsteile nur in TTL ausgefUhrt werden kennen. Die
CD4000-Serie von National Semiconductor besteht aus
den Bauelementen derCD40XXB- und CD45XXD-Familien.
Diese Typen entsprechen den Spezifikationen der B-Serie
nach JEDEC.
The CD4000 series is National Semiconductor's extensive
line of CD40XXB and CD45XXB series devices. These
parts meet the standard JEDEC "B-Series" specifications.
The popular MM54CI74C series logic family metal'gate
CMOS technology is pin·for-pin and function·for·function
equivalent to the 54174 family of TTL devices. Unique
special function LSI devices in this family are compatible
with MM54HCI74HC and CD4000 series.
Die weit verbreitete Logikfamilie MM54CI74C in MetallGate-Technologie ist anschlufj- und funktionskompatibel
zu den Bausteinen der 54174-TTL-Familie, Einige LSIBauelemente mit Spezial-funktionen'in dieser Familie
sind kompatibel mit Bausteinen der MM54HCI74HC- bzw.
CD4000-Familien.
CMOS LSI offers the design engineer unique solutions to
achieving high density low power systems. These LSI de·
vices utilize both microCMOS Silicon-gate and metal-gate
technologies to o,ffer the design engineer the best solution at the lowest cost.
CMOS-LSI-Bausteine bieten dem Entwicklungsingenieur
Lesungsmeglichkeiten in Form von Systemen mit hoher
Schaltungsdichte bei geringer Stromaufnahme. Diese
LSI·Schaltungen werden mit Hilfe der microCMOSSilicon-Gate- oder Metall-Gate-Technologie hergestellt
und ermeglichen optimale Schaltungsauslegung bei geringsten Kosten.
'
National provides the highest ,Quality and Reliability in
CMOS Logic and LSI. This databook provides detailed
descriptions of MilitarylAerospace Radiation Hardened
Programs, Quality Enhancement and extensive Reliability
Reports. We are proud of our success, which sets a standard for others to achieve. Our company-wide programs to
achieve perfec'tion will continue so that customers can
continue to rely on National Semiconductor's integrated
circuits and prOducts.
National Semiconductor kann bei CMOS-LSI- sowie
logikschaltungen Bauelemente hechster Qualitat und
Zuverlassigkeit anbieten. Dieses Datenbuch enthalt
detaillierte Beschreibungen der Programme fUr strahlenfeste Bauelemente fUr MiliUir sowie Luft und Raumfahrt,
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auch zukUnftig verlasl'en kennen.
Einleitung
Dieses ausfUhrliche Datenbuch enthalt aile Informationen iiber die modernen CMOS,Logikfamilien von
National Semiconductor, namlich iiber die Typenreihen
MM54HCI74HC, CD4000, MM54C174C, aufjerdem Uber
5
Introduction
Introduzione
Ce databook tres complet regroupe to utes les informa·
tions les plus recentes concernant les families logiques
CMOS de National Semiconductor, la MM54HC/74HC
rapide, la CD4000, la MM54C/74C, ainsi que de nombreux
produits originaux LSICMOS. La famille MM54HC/74HC,
realisee en technologie microCMOS combine les carac·
teristiques d'entree et d'alimentation de la CMOS avec la
vitesse et la sortance de'la low·power Schottky. La famille
54HC/74HC presente Ie m~me brochage que la famille
equivalente 54LS/74LS; de plus, la tres populaire famille
CD4000 offre un choix de fonctions logiques sans equiva·
lent en TTL.
II Databook sui dispositivi logici CMOS della National
Semiconductor contiene informazi6ni, dettagliate ed ago
giornate, sulla famiglia ad alta velocita MM54HC/74HC,
sulla famiglia CD4QOO, MM54C/74C e su molti prodotti LSI
CMOS. La famiglia MM54HC/74HC, in particolare utilizza
una tecnologia microCMOS per assommare aile caratte·
ristiche di assorbimerito e di Ingresso/Uscita tipiche del
CMOS quelle di elevata velocita e capac ita di pilotaggio
della tecnologia bipolare "Low Power Schottky". I
dis positivi della famiglia MM54HC/74HC so no pin c9m·
patibili con gli equivalenti dispositivi TTL; nella stessa ne
sono compresi altri che riprendono, funzionalmente, i pili
dlffusi dispositivi CD4000 ove non esista un equivalente
TTL.
La famille 54HCT/74HCT, sous·ensemble de la famille
MM54,HC/74HC, dispose d'entrees compatibles TTL. Ces
circuits MM54HCTl74HCT effectuent un translation de
niveau TTL·CMOS lorsque des portes TTL attaquent des
fonctions log!ques CMOS dans Ie systeme.
La MM54HCT/74HCT rappresenta una sotlofamiglia della
HC, ed offre compatibilita TTL sugli ingressi. La HCTtrova
ideale impiego nei sistemi ove esistano solamente livelli
TTL e si debbano impiegare dispositivi CMOS, come tras·
latori di livello. La famiglia CD4000 della National com·
prende la maggior parte delle funzioni pili diffuse sia
CD40XX che CD45XX. Tutti i dispositivi soddisfano Ie
specifiche JEDEC per la serie "B".
La famille CD4000 de National Semiconductor est con·
stituee par les series de circuits CD40XXB et CD45XXB.
Ces circuits sont conformes aux specifications standard
JEDEC 'Serie B'.
La famille logique Serie MM54C/74C realisee en technol·
ogie CMOS porte·metallique est equivalente broche pour
broche et fonction pour fonction a la famille de Circuits
TTL 54/74. Les circuits LSI de cette famille, realisant des
fonctions speciales uniques, sont compatibles avec les
Series MM54HC/74HC et CD4000.
La nota famiglia MM54C/74C, realizzata in tecnologia
CMOS "metal gate"
equivalente "pin·to·pin" e fun·
zionalmente alia famiglia di dispositiviTTL54/74. Speciali
dispositivi LSI, compresi in questa famiglia sono com·
patibili con Ie serie MM54HC/74HC e CD4000.1 dispositivi
LSI CMOS offrono ai progettisti soluzioni uriiche per
sistemi ove sia richiesta alta integrazione e basso assor·
bimento. Questi LSI sono realizzati sia In tecnologia
microCMOS che "metal gate" peroffrire sempre la mlglior
soluzione ai costi piu ridotti.
e
Les circuits- LSI CMOS offrent aux ingenieurs de concep·
tion des solutions avantageuses leur permettant de
realiser des systemes a-haute densite et consommant
peu. Ces circuits LSI sont realises en technologies
microCMOS porte.silicium et en CMOS porte·metallique,
afin que I'ingenieur de conception dispose de la meilleure
solution au moindre coOt.
National procure la meilleure qualite et la nieilleure
fiabilite elJ logique CMOS et en LSI. Ce Databook fournit
une description detaillee des Programmes d'exposition
aux radiations dans les domaines militaire et spatial, ainsi
que des rapports d'amelioration de la qualite et de la
fia!Jilite. Nous sommes fiers de notre succes, qui introduit
un standard que nous envient nos concurrents. Ces pro·
grammes de qualite sont executes it I'echelle de la societe
to ute entiElre en vue d'atteindre la perfection: ils seront
poursuivis afin que nos clients puissent continuer a faire
confiance aux circuits Integ res et aux produits National
,-.J Semiconductor.
-
La National offre la massima qual ita ed affidabilita per i
suoi pr6dotti logici CMOS e dispositivi LSI. Questo
Databook fornisce una descrizione dettagliata dei pro·
grammi "Radiation Hardened" per dispositivi militarl ed
aerospaziali, I mlglioramenti della qual ita oltre a completi
rapportl sull'affldabllita del componenti. Siamo fieri del
nostro successo che flssa nuovi traguardi, per altrl, da
raggiungere. II nostro programma, che coinvolge tulia la
societa per il raggiungimento della perfezione elettrica
in pieno svolglmento; con Cia i nostri clienti possono con·
tinuare a riporre la massima fiducia nei prodotti della
National Semiconductor.
e
6
Table of Contents
Section ~ -CMOS AC Switching Test Circuits and Timing Waveforms
MM54HC/MM74HC..............................................................
MM54HCT/MM74HCT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CD4000 ................................................ :. . . . . . . . . . . . . . . . . . . . . . .
MM54C/MM74C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-4
1-6
1-8
1-10
Section 2-CMOS Application Notes
MM54HC/MM74HC Application Notes
AN-303 HC-CMOS Power Dissipation ...................... :........................
AN-310 High-Speed CMOS (MM54HC/MM74HC) Processing ............•...............
AN-313 DC Electrical Characteristics of MM54HC/MM74HC High-Speed CMOS Logic .......
AN-314 Interfacing to MM54HC/MM74HC High-Speed CMOS Logic. . . . . . . . . . . . . . . . . . . . . . .
AN-317 AC Characteristics of MM54HC/MM74HC High-Speed CMOS. . . . . . . . . . . . . . . . . . . . .
AN-319 Comparison of MM54HC/MM74HC to 54LS/74LS, 54S/74S and
54ALS/74ALS Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-339 National's Process Enhancements Eliminate the CMOS SCR Latch-Up Problem
in54HC/74HCLogic ...........................................................
AN-340 HCMOS Crystal Oscillators. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-347 MM74HC942 and MM74HC943 Design Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-349 CMOS300 Baud Modem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-368 An Introduction to and Comparison of 54HCTl74HCT
TTL Compatible CMOS Logic....................................................
AN-375 High-Speed-CMOS Designs Address Noise and 1/0 Levels. . . . . . . . . . . . . . . . . . . . . . . .
AN-376 Logic-System Design Techniques Reduce SWitching-CMOS Power. . . . . . . . . . . . . . . . .
2-89
2-94
2-102
2-109
2-119
2-124
2-130
2:138
2-141
2-149
2-215
2-233
2-242
CD4000, MM54C/MM74C Application Notes
AN-77 CMOS, The Ideal Logic Family .............................................. ". .
AN-88 CMOS Linear Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-9054C/74C Family Characteristics .. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .
AN-118 CMOS Oscillators .........................................................
AN-138 Using the CMOS Dual Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-140 CMOSSchmittTrigger-A Uniquely Versatile Design Component. . . . . . . . . . . . . . . . . .
AN-177 Designing with MM74C908, MM74C918 Dual High Voltage CMOS Drivers. . . . . . . . . . . .
AN-248 Electrostatic Discharge Prevention-Input Protection Circuits and
Handling GuideforCMOSDevices ...... : ................................. :.......
AN-257 Simplified Multi-Digit LED Display Design Using
MM74C911/MM74C912/MM74C917 Display Controllers ..............................
AN-377 DC Noise Immunity of CMOS Logic Gates .....................................
MB-18 MM54CLMM74C Voltage Translation/Buffering . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . . . . .
2-3
2-11
2-14
2-20
2-24
2-30
2-40
2-52
2-68
2-253
2-257
LSI/VLSI Application Notes
AN-143 Using National Clock Integrated Circuits in Timer Applications. :. . . . . . . . . . . . . . . . . .
AN-249 MM54240 Asynchronous ReceiverlTransmitier Remote Controller Applicatio~s . . . . . .
AN·250 Applications and Uses otthe MM5321 TV Camera Sync Generator. . . . . . . . . . . . . . . . . .
AN·251 A Broadcast Quality TV Sync Generator Made Economical through LSI .............
AN·350 Designing an LCD Dot Matrix Display Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-35~MM58167AReatTimeClockDesignGuide .......... ;...........................
7
2-36
2-54
2-58
2-62
2-155
2-174
Table of Contents (Continued)
LSI/VLSI Application Notes (Continued)
AN-359 The MM58174A Real Time Clock in a Battery Backed-Up Design Provides
Reliable Clock and Calendar Functions ..•...•.•.....••..•.•..•.... : . . . . . . . . . . . • . . .
AN-365 The MM58274 Add~ Reliable Real-Time Keeping to Any Microprocessor System. . . . . .
AN-371 MM58348/342/341/248 Directly Drive Vacuum Fluorescent (VF) Displays. . . . . . . . . . • .
2-192
2-200
2-221
Section 3-MM54HC/MM74HC Data Sheets
Analog Switches
MM54HC4016/MM74HC4016 Quad Analog Switch ...........•..•.....................
MM54HC40511MM74HC4051 8-Channel Analog Multiplexer. . . . . . . . . . . . • . . . . • . . . . . . . . . .
MM54HC4052/MM74HC4052 Dual4-Channel Analog Multiplexer ......... '.. , ....... , .. , .
MM54HC4053/MM74HC4053 Triple 2-Channel Analog Multiplexer ........... , . . . . . . . . . . . .
MM54HC4066/MM74HC4066 Quad Analog Switch ....................................
MM54~C4316/MM74HC4316Quad Analog Switch with Level Translator; ..... , .... _...... _
3-360
3-386
3-386
3-386
3-397
3-408
Arithmetic Functions
MM54HC85/MM74HC85 4-BJt Magnitude Comparator ' . ' .. ' , . " . ' , . , ' , " , , '.. . .• . . . .. .
MM54HC1811MM74HC181 Arithmetic Logic Units/Function Generator.s. . . . . . . . . . . . . . . . . . .
MM54HC182/MM74HC182 Look-Ahead Carry Generator ....... , ........... , . . . . . . . .. . . .
MM54HC280/MM74HC280 9-Bit Odd/Even Parity Generator/Checker ....................
MM54HC283/MM74HC283 4-Bit BinaryAdderwith Fast Carry . . . ... . .. . . . .. . . . . .. . . . . . . .
MM54HC521/MM74HC521 8-Bit Magnitude Comparator (Equality Detector) ......•..••... :
MM54HC688/MM74HC688 8-Bit Magnitude Comparator(Equality Detector) .......... ; . . . .
3-66
3-158
3-166
3-238
3-241
3-286
3-341
Buffers/Drivers
MM54HC125/MM74HC125 TRI-STATEQuad Buffers ....... , ........................ , ..
MM54HC126/MM74HC126TRI-STATEQuad Buffers .................................. .
MM54HC240/MM74HC240 Inverting Octal TRI-STATE Buffer ..................•.........
MM54HC241/MM74HC241 Octal TRI-STATE Buffer .. , ..........•..........-........... .
MM54HC244/MM74HC244 Octal TRI-STATE Buffer ................................... .
MM54HC365/MM74HC365 HexTRI-STATE Buffer ........................•..... : ..... .
MM54HC366/MM74HC366 Inverting Hex TRI-STATE Buffer ................ ' ............. .
MM54HC367/MM74HC367 HexTRI-STATE Buffer ................................... ~ .
MM54HC368/MM74HC368 Inverting Hex TRI-STATE Buffer ............................. .
MM54HC540/MM74HC540 Inverting Octal TRI-STATE Buffer ........................... .
MM54HC541/MM74HC541 Octal TRI-STATE Buffer ................................... .
MM54HC4511/MM74HC4511 BCD-to-7 Segment Latch/Decoder/Driver .................. .
MM54HC4543/MM74HC4543 BCD·to-7 Segment Latch/Decoder/Driver for
Liquid Crystal Displays .. ~ .................................................... ','
3-93'
3-93,
3-201
3-201
3-210
3-263
3-263
3-263
3-263
3-295
3-295
3-413
3-428
Counters
MM54HC160/MM74HC160Synchronous Decade Counter .........•.... ',' .. .-. .. . . . . . . . .
MM54HC1611MM74HC161 Synchronous Binary Counter ...............................
MM54HC162/MM74HC162Sy.nchronous Decade Counter. . . . . . . . . .. . . . . . . . . . . . . . . . . . . .
MM54HC163/MM74HC163Synchronous Binarx Counter ...............................
MM54HC190/MM74HC190 Synchronous Decade Up/Down Counters with Mode Control .....
MM54HC1911MM74HC191 Synchronous Binary UplDowrrCounters with Mode Control ......
MM54HC192/MM74HC192 Synchronous Decade Up/Down Counters. . . . . . . . . . . . . . . . . . . . .
8
3-135
3-1;35
3-135
3-135
3-170
3-170
3-177
Table of Contents (Continued)
Counters (Continued)
MM54HC193/MM74HC193Synchronous Binary Up/Down Counters .............. , . . . . .. .
MM54HC390/MM74HC390 Dual4-Bit Decade Counter .................................
MM54HC393/MM74HC393 Dual4-Bit Binary Counter ..................................
MM54HC590/MM74HC590 8-Bit Binary Counter with TRI-STATE Output Register ....... . . . .
(
MM54HC592/MM74HC592 8-Bit BinaryCounterwith Input Register. . . . . . . . . . . . . . . . . . . .. .
MM54HC593/MM74HC593 8-Bit Binary Counler with Bidirectional
Input Register/Co~nterOutputs ......... .'. . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . . .. .
M M54HC4017/M M74HC4017 Decade Counter/Divider with 10 Deyoded Outputs. . . . . . . . . . . .
MM54HC4020/MM74HC4020 14-Stage Binary Counter . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .
MM54HC4024/MM74HC4024 7-Stage Binary Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC4040/MM74HC4040 12-Stage Binary Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC4060/MM74HC4060 14-Stage BinaryCounter. .. . . . .. . .. . . . . . . .. . . . . . . . . . . . .. .
3-177
3-276
3-276
3-315
3-317
3-317
3-365
3-36.9
3-369
3-369
3-393
Decodersl Encoders
MM54HC42/MM74HC42 BCD-to-Decimal Decoder ....................................
M M54HC137/M M7 4HC137 3-to·8 Line Decoder with Address Latches (Inverted Output) . . . . . .
MM54HC138/MM74HC138 3-to·8 Line Decoder .................................... ;. .
MM54HC139/MM74HC139 DuaI2-to-4 Line Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC147/MM74HC147 10-to-4 Line Priority Encoder ...............................
MM54HC149/MM74HC149 8-to-8 Line Priority Encoder .... :. . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC154/MM74HC154 4-to-16 Line Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC155/MM74HC155 DuaI2-to-4 Line Decoders. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .
MM54HC237/MM74HC237 3-to-8 Decoderwith Address Latches ........................
MM54HC4514/MM74HC4514 4-to-16 Line Decoder with Latch. . . . . . . . . . . . . . . . .. . . .. . . .. .
3-46
3-102
3-106
3-109
3-112
3-115
3-124
3-128
3-197
3-418
Flip-Flops
MM54HC73/MM74HC73 Dual J-K Flip-Flops with Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC74/MM74HC74 Dual D Flip-Flop with Preset and Clear. . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC76/MM74HC76 Dual J-K Flip-Flops with Preset and Clear. . . . . . . . . . . . . . . . . . . . . . . .
MM54HC107/MM74HC107 Dual J-K Flip·Flops with Clear ......................"..... : . . .
MM54HC109/MM74HC109 Dual J-K Flip-Flops with Preset and Clear. . . . . . . . . . . . . . . . . . . .. .
MM54HC112/MM74HC112 Dual J-K Flip-Flops with Preset and Clear. . . . . . . . . . . . . . . . . . . . . .
MM54HC113/MM74HC113 Dual J-K Flip-Flops with Preset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC173/MM74HC173 TRI-STATE Quad D Flip-Flop .............................. ,.
MM54HC174/MM74HC174 Hex D Flip-Flops with Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC175/MM74HC175 Quad D-Type Flip·Flop with Clear ..... '. . . . . . . . . . . .. . . . . . . . .. .
MM54HC273/MM74HC273 Octal D Flip-Flops with Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC374/MM74HC374 TRI-STATE Octal D-Type Flip-Flop. " " . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC534/MM74HC534 TRI-STATE Octal D-Type Flip-Flop with Inverted Outputs .........".
MM54HC564/MM74HC564 TRI·STATE Octal D-Type Flip-Flop with Inverted Outputs. . . . . . . . . .
MM54HC574/MM74HC574 TRI-STATE Octal D-Type Flip-Flop. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-52
3-56
3-62
3-73
3-77
3-80
3-84
3-147
3-151
3-154
3-234
3-273
3-292
3-301
3-307
Gates/lnverters
MM54HCOO/MM74HCOO Quad 2-lnput NAND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC02/MM74HC02Quad 2-lnput NOR Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC03/MM74HC03Quad 2-lnput Open Drain NAND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC04/MM74HC04.Hex Inverter ...............................................
MM54HC08/MM74HC08 Quad 2-lnput AND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
3-7
3-10
3-13
3-16
3-22
Table of Contents (Continued)
Gates/Inverters (Continued)
MM54HC10/MM74HC10Triple3-lnput NAND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC11/MM74HC11Triple 3-lnput AND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC14/MM74HC14 Hex Inverting Schmitt Trigger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC20/MM74HC20 Dual4-lnput NAND Gate ................................ ; . . . .
MM54HC27/MM74HC27Triple3-lnput NOR Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC30/MM74HC30 8-lnput NAND Gate' .......... \. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC32/MM74HC32 Quad 2-lnput OR Gate .......................................
MM54HC51/MM74HC51 DuaIAND-OR~lnvertGate ....................................
MM54HC58/MM74HC58 Dual AND-OR Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .• .
MM54HC86/MM74HC86Quad 2-lnput Exclusive OR Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC132/MM74HC132 Quad 2-lnput NAND Schmitt Trigger .. .- ... , .. : . . . . . . . . . .. . . . ..
MM54HC133/MM74HC133 13-lnput NAND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC266/MM74HC266 Quad 2-lnput Exclusive NOR Gate ...........................
MM54HC4002/MM74HC4002 Dual4-lnput NOR Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC4049/MM74HC4049 Hex Inverting Logic Level Down Converter. . . . . . . . . . . .. . . . . . .
MM54HC4050/MM74HC4050 Hex Logic Level Down Converter ..........................
MM54HC4075/MM74HC4075 Triple3-lnput OR Gate ....................................
MM54HC4078/MM74HC4078 8-lnput NOR/OR Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HCU04/MM74HCU04 Hex Inverter ... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .
3-25
3-28
3-31
3-34
3-37
3-40
3-43
3-49
3-49
3-70
3-96
3-99
3-231
3-374
3-400
3-400
3-419
3-422
3-19
Latches
MM54HC75/MM74HC75 4-Bit Bistable Latch with Q and Q Output. . . . . . . . . . . . . . . . . . . . . . .
MM54HC259/MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder. . . . . . . . . . . . . . . . . .
MM54HC373/MM74HC373 TRI·STATE Octal D-Type Latch. . . . . . . . . . . . . . . . . . . . . . . . . . ... . . .
MM54HC533/MM74HC533 TRI-STATE Octal D-Type Latch with Inverted Outputs ............
MM54HC563/MM74HC563 TRI-STATE Octal D-Type Latch
with Inverted Outputs ..............................•......................... , .
MM54HC573/MM74HC573 TRI-STATE Octal D-Type Latch .. '. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-59
3-227
3-270
3-289
3-298 '
3-304
Modems
MM74HC942 300 Baud Modem ( + 5, - 5 Volt Supply) ................... : . . . . . . . . . . . . . .
MM74HC943 300 Baud Modem (5 Volt Supply) ................. ;. . . . . . . . . . . . . . . . . . . . . . .
3·344
3-350
Multiplexers/Demultiplexers
MM54HC151/MM74HC151 8-Channel Multiplexer ................................... .
MM54HC153/MM74HC153 Dual4-lnput Multiplexer. .................................. .
MM54HC157/MM74HC157 Quad 2-lnput Multiplexer'.................................. .
MM54HC158/MM74HC158Quad 2·lnput Multiplexer(lnverted Output) ................... .
MM54HC251/MM74HC251 8-Channel TRI-STATE Multiplexer .......................... .
MM54HC253/MM74HC253 Dual4-Channel TRI-STATE Multiplexer ....................... .
, MM54HC257/MM74HC257 Quad 2-Channel TRI-STATE Multiplexer ...................... .
MM54HC298/MM74HC298 Quad 2-lnput Multiplexers with Storage ...................... .
MM54HC354/MM74HC354 8-Channel TRI-STATE Multiplexers with Latches ......•........
MM54HC356/MM74HC356 8-Channel TRI-STATE Multiplexers with Latches .............. .
3-118
3-121
. 3-131
3-131
3-218
3,221
3-224
3-246
3-255
3-255
'Multivibrators
MM54HC123A/MM74HC123A Dual Retriggerable Monostable Multivibrator. . . . . . . . . . . . . . . .
MM54HC221A/MM74HC221A Dual Non-Retriggerable Monostable Multivibrator ...........
10
3-88
3-192
Table of Contents (Continued)
Multivibrators (Continued)
MM54HC423A/MM74HC423A Dual Retriggerable Monostable Multivibrator. . . . . . . . . . . . . . . .
MM54HC4046/MM74HC4046 CMOS Phase Lock Loop. . . . . . .. . . .. . . . . . . . . . . .. . . . . . . .. .
MM54HC4538/MM74HC4538 Dual Retriggerable Monostable Multivibrator . . . . . . . . . . . . . . . .
3·281
3·374
3·422
Registers
MM54HC164/MM74HC164 8·Bit Serial·ln Parallel·Out Shift Register ......................
MM54HC165/MM74HC165 Parallel·ln Serial·Out8·Bit Shift Register. . . . . . . . . . . . . . . . . . . . . .
MM54HC194/MM74HC194 4·Bit Bidirectional Shift Register ..........•................ ,
MM54HC195/MM74HC195 4·Bit Parallel Shift Register ...... , . . . . . . . . . . . . . . . . . . . . . . .. .
MM54HC299/MM74HC299 8·BitTRI·STATE Universal Shift Register. . . . . . . . . . . . . . . . . . . . . .
MM54HC589/MM74HC589 8·Bit Shift Register with Input Latches and
TRI·STATE Serial Output ................................. , . . . . . . . . . . . . . . . . . . . . . .
MM54HC595/MM74HC595 8·Bit Shift Registers with Output Latches. . . . . . . . . . . . . . . . . . . . .
MM54HC597/MM74HC597 8·Bit Shift Registers with Input Latches. . . . . . . . . . . . . . . . . . . . . .
3·140
3·143
3·184
3·188
3·250
3·310
3·320
3·325
Transceivers/Registered Transceivers
MM54HC242/MM74HC242 Inverting Quad TRI·STATETransceiver . . . . . . . . . . . . . . . . . . . . . . . .
M M54HC243/M M74HC243 Quad TRI·STATE Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC245/MM74HC245 Octal TRI·STATE Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC640/MM74HC640 Inverting Octal TRI·STATETransceiver . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC643/MM74HC643 True·lnverting Octal TRI·STATETransceiver . . . . . . . . . . . . . . . . . . . .
MM54HC646/MM74HC646 Non·lnverting Octal Bus Transceiver/Registers. . . . . . . . . . . . . . . . .
MM54HC648/MM74HC648 Inverting Octal Bus Transceiver/Registers. . . . . . . . . . . . . . . . . . . . .
3·206
3·206
3·214
3·330
3·330
3·334
3·334
Section 4-MM54HCT/MM74HCT Data Sheets
Arithmetic Functions
MM54HCT521/MM74HCT521 8·Bit Magnitude Comparator(Equality Detector) . . . . . . . . . . . . .
MM54HCT688/MM74HCT688 8·Bit Magnitude Comparator(Equality Detector) . . . . . . . . . . . . .
4·80
4:111
Buffers/ Drivers
MM54HCT240/MM74HCT240 Inverting Octal TRI·STATE Buffer. . . . . . . . . . . . . . .. . . . . . . . . . .
MM54HCT241/MM74HCT241 Octal TRI·STATE Buffer. . . . . . . .. . . . . . . . . . . . .. . . .. . . . . ... .
MM54HCT244/MM74HCT244 Octal TRI·STATE Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HCT540/MM74HCT540 Inverting Octal TRI·STATE Buffer ..........................
MM54HCT541/MM74HCT541 Inverting Octal TRI·STATE Buffer ................ " . . . . . .. .
4·57
4·57
4·57
4·88
4·88
Counters
MM54HCT191/MM74HCT191 Synchronous Binary Up/Down Counters with Mode Control ....
MM54HCT193/MM74HCT193 Synchronous Binary Up/Down Counters ....... : . . . . . . . . . . . .
MM54HCT590/MM74HCT590 8·Bit BinaryCounterwith TRI·STATE Output Register. . . . . . . . .
MM54HCT592/MM74HCT592 8·Bit BinaryCounterwith Input Register ........ 1 . . . . . . . . . . .
MM54HCT593/MM74HCT593' 8·Bit Binary Counter with Bidirectional Input
Register/CounterOutputs ......................................................
4·46
4·52
4·103
4·105
4·105
Decoders/Encoders
MM54HCT138/MM74HCT138 3·to·8 Line Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HCT139/MM74HCT139 DuaI2·to·4 Line Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
4·27
4·30
Table of Contents (Continued)
Decoders/Encoders (Continued)
MM54HCT149/MM74HCT149 8-Line to 8-Line Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HCT155/MM74HCT155 Dual'2-to-4 Line Decoder/Demultiplexers ...................
4-33
4-36
Flip/Flops
MM54HCT74/MM74HCT74 Dual D Flip-Flops with Preset and Clear. . . . . .. . . .. .. ... . . .. . . .
MM54HCT76/MM74HCT76 Dual J-K Flip-Flops with Preset and Clear ................ ,. . . . .
MM54HCT109/MM74HCT109 Dual J,K Flip-Flops with Preset and Clear ...................
MM54HCT112/MM74HCT112 Dual J-K Flip-Flopswith Preset and Clear ...................
MM54HCT273/MM74HCT273 Octal D Flip-Flop with Clear ..............................
MM54HCT374/MM74HCT374 T.R I-STAT E Octal D-Type Flip-Flop ............... ; .. . . . .. ... .
MM54HCT534/MM74HCT534 TRI-STATE Octal D-Type Flip-Flop. . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HCT564/MM74HCT564 TRI-STATE Octal D-Type Flip-Flop with Inverted Outputs ..... .'.
MM54HCT574/MM74HCT574 TRI-STATEOctal D-Type Flip-Flop. . . .. . . . .. . . . . . . . .. . . ... . .
4-18
4-21
4-24
4-21
4-68
4-75
4-83
4-94
4-100
Gates/lnverters
MM54HCTOO/MM74HCTOO Quad 2-lnput NAND Gate ..................................
MM54HCT04/MM74HCT04 Hex Inverter ......................................... :. . .
MM54HCT05/MM74HCT05 Hex Open Drain Inverter ...... :............................
MM54HCT08/MM74HCT08QuadANDGate ................. :..........................
MM54HCT34/MM74HCT34 Non-Inverting Gate
4-5
4-7
4-9
4-12
4-15
Latches
MM54HCT373/MM74HCT373 TRI-STATE Octal D-Type Latch ............................
, MM54HCT533/M M74HCT533 TRI-STATE Octal D-Type Latch. . .. . .. . . .. . . . . . .. . . .. .. .. . . .
MM54HCT563/MM74HCT563 TRI-STATE Octal D-Type Latch with Inverted Outputs. . . . . . . . . .
M M54HCT573/M M74HCT573 TRI-STATE Octal D-Type Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-75
4-83
4-91
4-97
Multiplexers/ Demultiplexers
MM54HCT157/MM74HCT157 Quad 2-lnput Multiplexer ................ .'. . . . .. . . . . . . . . . .
MM54HCT158/MM74HCT158 Quad 2-lnput Multiplexer(lnverted Output) ....•.............
MM54HCT257/MM74HCT257 Quad 2-Channel TRI-STATE Multiplexer. . . . . . . . . . . . . . . . . . . . .
4-39
4-39
4-65
Shift Registers
MM54HCT164/MM74HCT164 8-Bit Serial-ln/Parallel-Out Shift Register. . . . . . . . . . . . . . . . . . .
MM54HCT299/MM74HCT299 8-Bit TRI-STATE Universal Shift Register. . . . . . . . . . . . . . . • . . . .
MM54HCT323/MM74HCT323 8-Bit TRI-STATE Universal Shift Register. . . . . . . . . . . . . . . . . . . .
4-43
4·71
4-73
Transceiversl Registered Transceivers
MM54HCT245/MM74HCT245 Octal TRI-STATE Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HCT640/MM74HCT640 Inverting Octal TRI-STATE Transceiver. . . . . . . . . . . . . . . . . . . . . .
MM54HCT643/MM74HCT643 True-Inverting Octal TRI-STATE Transceiver. . . . . . . . . . . . . . . . . .
4-61
4-108
4-108
Section 5.-CD4XXX Series CMOS Logic
Arithmetic Functions
CD4008BM/CD4008BC 4-Bit Full Adder . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .
12
5-30
Table of Contents (Continued)
Buffersl Drivers
CD4009M/CD4009C Hex Buffer(lnverting). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . .. .
CD4010M/CD4010C Hex Buffer(Non-lnverting) .......................................
CD4049UBM/CD4049UBC Hex Inverting Buffer .......................................
.
.
.
.
.
5-33
5-33
5-149
5-149
5-199
5-214
5-231
5-214
CD4017BM/CD4017BC Decade CounterlDividerwith 10 Decoded Outputs ... ;. . . . . . . . . ... .
CD4018BM/CD4018BC Presettable Divide-by-N Counter. . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. .
CD4020BM/CD4020BC 14-Stage Ripple-Carry Binary Counter/Divider . . . . . . . . . . . . . . . . . . . .
CD4022BM/CD4022BC Divide-by-8 CounterlDivider with 8 Decoded Outputs .. . . . . . . . . . . . . .
CD4024BM/CD4024BC 7-Stage Ripple-Carry Binary CounterlDivider . . . . . . . . . . . . . . . . . . . . .
CD4029BM/CD4029BC Presettable BinarylDecade UplDown Counter ....................
CD4040BM/CD4040BC 12-Stage Ripple Carry Binary CounterlDivider . . . . . . . . . . . . . . . . • . . . .
CD4060BM/CD4060BC 14-Stage Ripple Carry Binary CounterlDivider . . . . . . . . . . . . . . . . . . . . .
CD4089BM/CD4089BC Binary Rate Multiplier ........................................
CD40160BM/CD40160BC Decade Counter with Asynchronous Clear. . . . . . . . . . . . . . . . . . . . . .
CD40161 BM/CD40161 BC BinaryCounter with Asynchronous Clear. . . . . . . .. . . . . . . . . . . . . . .
CD40162BM/CD40162BC Decade Counter with Asynchronous Clear. . . . . . . . . . . . . . . . . . . . . .
CD40163BM/CD40163BC Binary Counter with Asynchronous Clear. . . . . . . . . . . . . . . . . . . . . . .
CD40192BM/CD40192BC Synchronous 4-BitUplDown Decade Counter.'. . . . . . . . . . . . . . . . . .
CD40193BM/CD40193BC Synchronous 4-Bit UpIDown Binary Counter. . . . . . . . . . . . . . . . . . . .
CD4510BM/CD4510BC BCD UplDown Counter. . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .
CD4516BM/CD4516BC Binary UpJDown Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CD4518BM/CD4518BC Dl!al Synchronous Up Counter .................................
CD4520BM/CD4520BC Dual Synchronous Up Counter .................................
CD4522BM/CD4522BC Programmable Divide-by-n 4-Bit BCD Counter. . . . . . . . . . . . . . . . . . . . .
CD4526BM/CD4526BC Programmable Divide-by-n 4-Bit Binary Counter .. . . . . . . . . . . . . . . . . .
CD4527BM/CD4527BC BCD Rate Multiplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .. .
5-55
5-60
5-67
5-55
5-84
5-94
5-67
5-67
5-192
5-218
5-218
5-218
5-218
5-226
5-226
5-235
5-235
5-258
5-258
5-267
5-267
5-192
CD4050BM/CD4050BC Hex Non-Inverting Buffer. . . . . . . . . . . . . . . . . .
CD4093BM/CD4093BC Quad 2-lnput NAND Schmitt Trigger. . . . . . . . .
CD40106BM/CD40106BC Hex Schmitt Trigger. . . . . . . . . . . . . . . . . . . .
CD4503BM/CD4503BC Hex Non-Inverting TRI-STATE Buffer. . . . . . . . .
CD4584BM/CD4584BC Hex Schmitt Trigger(See CD40106 data sheet).
.
.
.
.
.
......
......
. . .. . .
......
......
...
...
...
...
...
..
..
..
..
..
..
..
..
..
..
.
.
.
.
.
.
.
.
.
.
. ..
...
...
...
...
Counters
Decodersl Encoders
CD4028BM/CD4028BC BCD-to-Decimal Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CD4511 BM/CD4511 BC BCD-to-7-Segment Latch DecoderlDriver . . . . . . . . . . . . . . . . . . . . . . . . .
CD4514BM/CD4514BC 4-Bit Latched 4-to-16 Line Decoders ............................
CD4515BM/CD4515BC 4-Bit Latched 4-to-16 Line Decoders ..... :......................
CD4529BM/CD4529BC Dual4-Channel or Single 8-Channel Analog Data Selector. . . . . . . . . . .
CD4543BM/CD4543BC BCD-to-7-Segment LatchIDecoderlDriver for
Liquid Crystal Display~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-91
5-242
5-253
5-253
5-281
5-300
Flip-Flops
CD4013BM/CD4013BC Dual D Flip-Flop. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. .
CD4027BM/CD4027BC Dual J-K MasterlSlave F:lip-Flop with Set and Reset ................
CD4042BM/CD4042BCQuadClocked D Latch .................................. :.....
CD4043BM/CD4043BCTRI-STATE NOR RIS Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .
CD4044BM/CD4044BCTRI-STATE NAND RIS Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. .
13
5-35
5-87
5-123
5-127
5-127
Table of Contents (Continued)
Flip·Flops (Continued)
CD4076BM/CD4076~CTRI·STATEQuad Flip·Flop . . . . .. . . .. . . .. . . ... . . •.. ..... . . .. . . . .
CD4099BM/CD4099BC 8·Bit Addressable Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CD40174BM/CD40174BC Hex D Flip·Flop . . . . . . . . . • . . • . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .
CD40175BM/CD40175BC Quad D Flip·Flop . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . .
CD4723BM/CD4723BC Dual4·Bit Addressable Latch ......... ".................. ,......
CD4724BM/CD4724BC 8·Bit Addressable Latch . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . .
5·188
5·209
5·223
5·223
5·306
5·306
Gatesllnverters
CD4000M/CD4000C Dual Input NOR Gate Plus Inverter .................•...............
CD4001 M/CD4001 C Quad 2·lnput NOR Gate .................... ~ .•...................
CD4001 BM/CD4001 BC Quad 2·lnput NOR Buffered B Series Gate ....................... .
CD4002M/CD4002C Dual4·lnput NOR Gate ...•......................................
CD4002BM/CD4002BC Dual4·lnput Buffered NOR Gate ...•.......•.......•............
CD4007M/CD4007C Dual Complementary Pair Plus Inverter •............................
CD4011 M/CD4011 C Quad 2·lnput NAN D Gate ........•.........•.....................
CD4011 BM/CD4011 BC Quad 2~lnput NAND Buffered B Series Gate ...................... .
CD4012M/CD4012C Dual4·lnput NAND Gate ......................................•..
CD4012BM/CD4012BC Dual4·lnput Buffered NAND Gate ......................•........
CD4019BM/CD4019BC Quad AND·OR Select Gate ................................... .
CD4023M/CD4023C Triple 3·lnput NOR Gate ...................................•...•..
CD4023BM/CD4023BCTriple3·lnput Buffered NAND Gate .......•.....•............••..
CD4025M/CD4025C Triple 3·lnput NAND Gate ....•.................•......... : ...... .
CD4025BM/CD4025BCTriple3-lnput Buffered NOR Gate .............................. .
CD4030M/CD4030C Quad Exclusive·OR Gate ..................•.......... , ...... ; ... .
CD4041 M/CD4041 C Quad True/Complement Buffer ......................•............
CD4048BM/CD4048BC TRI·STATE Expandable 8-Function 8·lnput Gate ..•.................
CD4069UBM/CD4069UBC Inverter Circuits ..•..............•.........................
CD4070BM/CD4070BC Quad 2·lnput Exclusive·OR Gate ....•............ : ............. .
CD4071 BM/CD4071 BC Quad 2·lnput OR Buffered B Series Gate .........•................
CD4072BM/CD4072BC Dual4·lnput OR Buffer-ed B Series Gate ......................... .
CD4073BM/CD4073BC Double Buffered Triple 3·lnput AND Gate.' ....................... .
CD4075BM/CD4075BC Double BufJered Triple 3·lnput OR Gate •........•.•..•...........
CD4081 BM/CD4081 BC Quad 2·lnput AND Buffered B Series Gate ....................... .
CD4082BM/CD4082BC Dual4·lnput AND Buffered B Series Gate .......•...•.............
CD4519BM/CD4519BC 4·Bit AND/OR Selector ..................................... ..
5·5
5·8
5·12
5-17
5·21
5·27
5·8
5·12
5·17
5·21
5·64
5·76
5·80
5·76
5·80
5·100
5·119
5·143
5·16~
5·172
5·176
5·181
5·184
5·184
5·176"
5·181
5·263
Multiplexers/Demultlplexers
CD4016BM/CD4016BC Quad Bilateral Switch
CD4051 BM/CD4051 BC An"alog Multiplexers/Demultiplexers ........•.........•..•...". . .
CD4052BM/CD4052BCAnalog Multiplexers/Demultiplexers . . . .. .. . ... . . . .. . .. . . .. . .. ..
CD4053BM/CD4053BCAnalog Multiplexers/Demultiplexers . . ... . . . .. . .• . . . .•.. . .. .. . ..
CD4066BM/CD4066BCQuad Bilateral Switch ........................................
CD4512BM/CD4512BC 8·Channel Data Selector ..............•.. ".. . . •. . . . .. .. ... . . .. .
CD4529BM/CD4529BC Dual4·Channel or Single 8-Channel Analog Data Selector . . . . . . . . . . .
5-48
5·154
5·154
5·154
5·162
5·248
5·281
Multivibrators"
CD4046BM/CD4046BC Micropower Phase· Locked Loop. • • • . . . • . . . . • . . . . .• .. . • . . • . . . . . .
CD40476M/CD4047BC Low Power Monostable/Astable Multlvibrator. . . . . . . . . . . . . . . . . • . . .
---------
14
5·131
5·138
Table of Contents (Continued)
Multivibrators (Contin,ued)
CD452BBM/CD452BBC Dual Monostable Multivibrator ., . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . .
CD453BBM/CD453BBC Dual Monostable Multivibrator ................................ ;
CD4541 BM/CD4541 BC Programmable Timer with Oscillator ............................
5-275
5-2B7
5-295
Registers
CD4006BM/CD4006BC 1B-Stage Static Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CD4014BM/CD4014BC B-Stage Static Shift Register ..................................
CD4015BM/CD4015BC Dual4-Bit Static Register ...... : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CD4021 BM/CD4021 BC B-Stage Static Shift Register ..................................
CD4031 BM/CD4031 BC 64-Stage Static Shift Register .................................
CD4034BM/CD4034BC B-Stage TRI-STATE Bidirectional Paraliel/Serial
Input/Output Bus Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CD4035BM/CD4035BC 4-Bit Paraliel-ln/Paraliel-Out Shift Register. . . . . . . . . . . . . . . . . . . . . ..
5-24
5-40
5-44
5-72
5-103
5-107
. 5-115
Section 6-MlVis4CXXX/MM74CXXX Series
Arithmetic Functions
MM54CB3/MM74CB3 4-Bit Binary Full Adder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-34
Buffers/Drivers
MM54C04/MM74C04 Hex Inverter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54C14/MM74C14 Hex Schmitt Trigger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .
MM54C240/MM74C240 Octal Buffers and Une Drivers with TRI-STATE
Outputs(lnverting). . . • . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54C244/MM74C244 Octal Buffers and Line Drivers with TRI-STATE
Outputs (Non-Inverting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . .
MM54C901/MM74C901 Hex Inverting TTL Buffer .... _.................................
MM54C902/MM74C902 Hex Non-Inverting Buffers. . .. . . . . . . .. . . .. .. .. . .. . . . . .. .. . . .. . .
MM54C903/MM74C903 Hex Inverting PMOS Buffer. .. . . .. . . .. . . .. . . . . . . . . . . .. . . . . . .. . .
MM54C904/MM74C904 Hex Non-Inverting PMOS Buffers ......... ; ..... , ..... , . . . .• .. . .
MM54C906/MM74C906 Hex Open Drain N-Channel Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54C907/MM74C907 Hex Open Drain P-Channel Buffer. . . . . . . . • . . • . . . . . . . . . . . . . . . . . . .
MM54C914/MM74C914 HexSchmitt Triggerwith Extended Input Voltage. . . . . . . . . . . . . . . . . .
MM54C941/MM74C941 Octal Buffers/Line Receivers/Line Drivers with
TRI-STATE Outputs ................•...........................................
MM70C95/MMBOC95TRI-STATE Hex Buffers .................................. " . .. . .
MM70C96/MMBOC96TRI-STATE Hex Inverters ........ , ..........•.......... , . .. . . .. . .
MM70C97/MMBOC97TRI-STATE Hex Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .
MM70C9B/MMBOC9BTRI-STATEHexlnverters ........................................
MM74C90BDuaiCMOS30VoitReiayDriver ..........................................
MM74C9114-Digit LED Display Controller .............. :............................
MM74C912 6-DigitBCDLEDDisplayControlierDriver .................................
MM74C917 6-Digit Hex LED Display Controller Driver. . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . .
MM74C91B Dual CMOS 30 Volt Relay Driver. . ... . .. . . . . .. . .. . . . . . . . . . . . . . . .. . . . . . .. . .
MM74C956 4 Character LED Alphanumeric Display Controller Driver(17-Segment) . . . . . . . . . .
MM78C29/MM88C29 Quad Single-Ended Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM78C30/MM88C30 Dual Differential Line Driver ..•....... .' . • • . . . . . . . . . . . . . . . . . . . . • . .
15
6-5
6-12
6-105
6-105
6-117
6-117
6-117
6-117
6-126
6-126
6-13B
6-155
6-164
6-164
6-164
6-164.
6-169
6-173
6-1BO
6-1BO
6-169
6-204
6-20B
6-20B
Table of Contents (Continued)
CMOS Memories
MM54C89/M M74C89 64-Bit (16 x 4) TRI-STATE Random Access Memory _............ " . . . .
MM54C200/MM74C200 256-Bit (256 x 1) TRI-STATE Random Access Memory .............,.
. MM54C910/MM74C910 256-Bit(64 x 4)TRI-STATE Random Access Memory ...............
MM54C989/M M74C989 64-Bit (16 x 4) TRI-STATE Random Access Memory ................
6-44
6-97
6-134
6-160
Comparators
MM54C85/MM74C85 4-Bit Magnitude Comparator .................... : .... ,..........'.
6-38
Counters
MM54C90/MM74C90 4-Bit Decade Counter ................... '. . ... . .. . . . .... . ..•... .
MM54C93/MM74C93 4-Bit Binary Counter .•..................... ,. . .. . .. . . . . . . . . . . . .
MM54C160/MM74C160 Decade Counter with Asynchronous Clear ....... '. . . . . . . . . . . . . . . .
MM54C161/MM74C161 Binary Counter with Asynchronous Clear ........................
MM54C162/MM74C162 Decade Counter with Synchronous Clear ................. ,......
MM54C163/MM74C163 Binary Counter with Synchronous Clear ....... : ...... : ~ . . . . . . . . .
MM54C192/MM74C192 Synchronous 4-Bit Up/Down Decade Counter. . . . . . . . . . . . . . . . . . . . .
MM54C193/MM74C193 Synchronous 4-Bit Up/Down Binary Counter . . ... . . . . .. .. . . .. . . . . .
MM74C925 4·Digit Counter with Multiplexed7·Segment OutputDriver ................. : . .
MM74C926 4-Digit Counter with Multiplexed 7-Segment Output Driver .................... '
MM74C927 4-Digit Counter with Multiplexed 7-Segment Output Driver. . • . . . . . . . . . . . . . . . . .
MM74C928 4-Digit Counter with Multiplexed 7-Segment Output Driver ...
MM74C945 41/2-Digit LCD Up Counter/Latch Driver ............... '. . . . . . . . . . .. . . . . . . . .
MM74C946 4-Digit LCD Up-Down Counter./Latch/Driver . . . . . . . .. . . . . . • . . . . . . . . . . . . . . . . .
MM74C947 4-Digit LCD Up-Down Counter/LatchlDriver .............. : . . . . . . . . . . . . . . . . .
'0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
6-48
6-48
6-68
6-68
6-68
6-68
6-90
6·90
6-186
6-186
6-186
6-186
6-190
6-197
6-190
Decoders/ Encoders
MM54C42/MM74C42 BCD-to-Decimal Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54C4~/MM74C48 BCD-to-7-Segment Decoder ......... '" .............
MM54C154/MM74C154 4-Lineto 16-Line Decoder/Demultiplexer. . . . . . . . . . . . . . . . . . . . . . . .
MM54C915/MM74C915 7-Segment-to-BCDConverter .................................
M M54C922/M M74C922 16-Key Keyboard Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . • . . .
MM54C923/MM74C923 20-Key Keyboard Encoder .........• , . . . . . . .. . . . . . . . . . . . . . . . . .
'0
•
•
•
•
•
•
•
•
•
•
•
•
6-20
6-22
6-63
6-141
6-145
6-145
Flip·Flops
MM54C74/MM74C74 Dual 0 Flip-Flop. . . . . .. . . . . .. . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . .
M M54C76/ M M74C76 Dual J-K FI i p-Flops with Clear and Preset .... ,.....................
MM54C107lMM74C107 Dual J-K Flip-Flopswith Clear .: ...........•.............. ~.....
MM54C173/MM74C173TRI-STATEQuad 0 Flip-Flop ......................... : . •. . . . . . .
MM54C174/MM74C174 Hex 0 Flip-Flop ........................... :.................
MM54C175/MM74C175QuadDFlip-Flop .................... .'.......................
M M54C374/ M M7 4C37 4 Octal 0-Type Flip-Flop with TRI-STATE Outputs ...•..... : . . . . . . . • . .
6-30
6-27
6-27
6-81
6-84
6-87
6-110
Gatesllnverters
MM54COO/MM74COOQuad2-lnputNANDGate ................................•......
MM54C02/MM74C02Quad2-lnput NOR Gate ..... : .................... ,'..............
MM54C08/MM74C08Quad 2-lnputAND Gate ............. : .. '................... '......
MM54C10/MM74C10Triple3-lnput NAND Gate .......................................
MM54C20/MM74C20 Dual4-lnput NAND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
6-5
6-5
6-9
6-5
6-5
Table of Contents (Continued)
Gatesilnverters (Continued)
MM54C30/MM74C30 8-lnput NAND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54C32/MM74C32Quad2-lnputORGate ..........................................
M M54C86/M M7 4C86 Quad 2-lnput EXCLUSIVE-OR Gate'.............................. __
MM54C909/MM74C909QuadComparator ...................................... _... _
6-15
6-18
6-41
6-129
Latches
MM54C73/MM74C73 Dual J-K Flip-Flops with Clear .. _... _...... _...... _..... _. . . . . . . . .
MM54C373/MM74C373 Octal Latch with TRI-STATE Outputs _............ _. . . . . . . . . . . . . .
6-27
,6-110
Multiplexersl Demultiplexers
MM54C150/MM74C150 16-Lineto 1-Line Multiplexer. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . .
MM54C151/MM74C151 8-Channel Digital Multiplexer. . . . . .. . . . . . . . . . . . . . . . .. . . . . . . . . .
MM54C157/MM74C157 Quad 2-lnput Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM72C19/MM82C19TRI-STATE 16-Lineto 1-Line Multiplexer ......................... , . .
6-54
6-59
6-66
6-54
Multivibrators
MM54C221/MM74C221 Dual Monostable Multivibrator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .
MM54C932/MM74C932 Phase Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-101
'6-151
Registers
MM54C95/MM74C95 4-Bit Right-Shift/Left-Shift Registe~ ..... . . . . . . . . . . . . . . . . . . . . . . . . .
MM54C164/MM74C164 8·Bit Parallel-Out Serial Shift Register ..........................
MM54C165/MM74C165 Parallel-Load 8-Bit Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54C195/MM74C195 4-Bit Register. . . . . . . . . . . . . . . . . . . . . . . .• . . . . . . . . . . . . . . . . . . . . .
6-52,
6-73
6-77
6-94
Special Functions
MM54C905/MM74C905 12-Bit Successive Approximation Register
6-121
Section 7- LSIIVLSI CMOS
Display Drivers
MM5450 LED Display Drivers ........................ :.............................
MM5451 LED Display Drivers ......................................... ; ... :........
MM5452 Liquid Crystal Display Drivers .... " . . ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5453 Liquid Crystal Display Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5480 LED Display Driver. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM5481 LED Display Driver .............................................. , .. " .. . .
MM5483 Liquid Crystal Display Driver ................. _. . . . . . . .. . . . . . . . . . . . . . . . . . . . .
MM5484 16-Segment LED Display Driver, 11 Segment LED Display Driver ............ , . . . . .
MM5485 16-Segment LED Display Driver, 11 Segment LED Display Driver .............. :. . .
MM5486 LED Display Driver ............. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM58201 Multiplexed LCD Driver .............................. '. . . . . . . . . . . . . . . . . . . .
MM58241 High Voltage Display Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM58242 High Voltage 20 Output Vacuum Fluorescent Display Driver. .. . . . . . . . . . . . . . . . . . .
MM58248 High Voltage 35 Output Vacuum Fluorescent Display Driver. . . .. . . . . . . . . . . . . . . . .
MM58341 High Voltage 32 Output Vacuum Fluorescent Display Driver ....................
MM58342 High Voltage 20 Output Fluorescent Display Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
7-32
7-32
7-37
7-37
7-43
7-47
7-51
7-54
7·54
7-57
7-85
7-90
7-95
7-100
7-126
7-131
Table of Contents (Continued)
Display Drivers (Continued)
MM58348 High Voltage 35 OutputVacuum Fluorescent Display Driver
MM58438 32·Bit LCD Display Driver
MM58538 Multiplexed LCD8·Row/26·Column Driver
MM58539 Multiplexed LCD 34·Column Driver
MM58540Muitiplexed LCD 32·Row/32·Column Driver
MM58548 Multiplexed LCD 16·Row/16·Column Driver
00000000000000000000000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
000000000000000000000
0
0
0
0
0000
00000000000000000000000000000000000
0000000000000000:
000000000000000000000000
0000000000000000000000000000000000
0
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00
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0
0
0
0
0
0
0
0
0
0
0
0
7·,136
7·141
7·145
7·150
7·155
7·160
Oscillatorsl Dividers
MM5368 CMOS Oscillator Divider Circuit
MM5369 Series 17 Stage Oscillator/Divider.
MM53107Series17·StageOsciliator/Divider
0
0
0
0
0
0
0
0
00000000000000000000000000000000000000000
7·11
7·14
7·17
Other (LSI, VLSI CMOS)
~
MM5034, MM5035 Octal80·Bit Static Shift Register
MM5307 Baud Rate Generator/Programmable Divider
MM531261nfraRedTransmitter
M M53226 Infra Red Transmitter
M M5437 Noise Generator
, M M54240 Asynchronous Receiver/Transmitter Remote Controller
MM58250 Infra Red Transmitter
0
0
0
0
0
0
0
0
0
0
0
0
000000:
0
0
0
0
0
0
0
0
0000000000000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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00000000000
000000000000000000000000000000000000000000000000000
0
0
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;
0
0
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
'0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7-3
7-6
7·19
7·24
7·29
7·62 '
7·105
Real Time Clocks
MM58167AMicroprocessorRealTimeCIock
M M5817 4A Microprocessor Real Ti me Clock
.
MM58274MicroprocessorRealTim~Clocko
00000000000000000000:0000000,00'00000000000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0:
0
0
0
0
Co
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00000000000000000000000000
,
,
7·70
7·78
7·113
Section a-Appendices/Physical Dimensions
Introduction to the Reliability Military/Aerospace Programs
Radiation Hardened Technologies from National Semiconductor
Commercial Quality Enhancement Programs
Silicon Gate Reliability Report
Metal Gate Reliability Report
Physical Dimensions
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18
8·3
8-17
8·33
8·37,
8-49
8-71
Alphanumeric Index
AN-77 CMOS, The Ideal Logic Family ............................................... .
AN-88 CMOS Linear Applications ............................... ~ .................. .
AN-90 54C/74C Family Characteristics ................................. : .......... .
AN-118CMOSOsciliators .......... : ........................................ _.... .
AN-138 Using the CMOS Dual Monostable Multivibrator ............................... .
AN-140 CMOS Schmitt Trigger - A Uniquely Versatile Design Component _............... .
AN-143 Using National Clock Integrated Circuits in Timer Applications ................... .
AN-177 Designing with MM74C908, MM74C918 Dual High Voltage CMOS Drivers ........... .
AN-248 Electrostatic Discharge Prevention - Input Protection Circuits and
Handling Guide for CMOS Devices ............................................... .
AN-249 MM54240 Asynchronous Receiver/Transmitter Remote Controller Applications ..... .
AN-250 Applications and Uses ofthe MM5321 TV Camera Sync Generator. ................ .
AN-251 A Broadcast QualityTV Sync Generator Made Economical through LSI ............ .
AN-257 Sil1)plified Multi-Digit LED Display Design Using·
MM74C911/MM74C912/MM74C917 Display Controllers ............. _............... .
AN-303 HC-CMOS Power DisSipation .............................................. .
AN-310 High-Speed CMOS(MM54HC/MM74HC) Processing ........................... .
AN-313 DC Electrical Characteristics of MM54HC/MM74HC High-Speed CMOS Logic ...... .
AN-314 Interfacing to MM54HC/MM74HC High-Speed CMOS Logic ...................... .
AN-317 AC Characteristics of MM54HC/MM74HC High-Speed CMOS ......... , .......... .
AN-319 Comparison of MM54HC/MM74HC to 54LS/74LS, 54S/74S and
54ALS/74ALS Logic ........................................................... .
AN·339 National's Process Enhancements Eliminate the CMOS SCR Latch·Up Problem
in 54HC/74HC Logic ................... '. .- ..................................... .
AN-340 HCMOS Crystal Oscillators ................................................ .
AN-347 MM74HC942 and MM74HC943 Design Guide .................................. .
AN-349 CMOS 300 Baud Modem ................................................... .
AN·350 Designing an LCD Dot Matrix Display Interface ................................._
AN·353 MM58167 A Real Time Clock Design Guide .................................... .
AN·359 The MM58174A Real Time Clock in a Battery Backed·Up Design Provides
Reliable Clock and Calendar Functions ........................................... .
AN-365 The MM58274 Adds Reliable Real·Time Keeping to Any Microprocessor System ..... .
AN·368 An Introduction to and Comparison of 54HCT/74HCT
TTL Compatible CMOS Logic ................................................... .
AN·371 MM58348/342/341/248 Directly Drive Vacuum Fluorescent (VF) Displays ........... .
AN-375 High-Speed-CMOS Designs Address Noise and I/O Levels ....................... .
AN-376 Logic-System Design Techniques Reduce Switching-CMOS Power ................ .
AN-377 DC Noise Immunity of CMOS Logic Gates .................................... .
19
2-3
2-11
2-14
2-20
2-24
2-30
2-36
2-40
2-52
2-54
2-58
2-62
2-68
2-89
2-94
2-102
2-109
2-119
2-124
2-130
2-138
2-141
2-149
2-155
2-174
2-192
2-200
2-215
2-221
2-233
·2-242
2·253
Alphanumeric
Index(conlinUed)
CD4000M/CD4000C Dual Input NOR Gate Plus Inverter. . . . • . . . . . . • . . . . . . . . . . . . . . . . . . . . •
CD4001 M/CD4001 C Quad 2·lnput NOR Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CD4001 BM/CD4001 BC Quad 2·lnput NOR Buffered B Series Gate . . . . . . . . . . . . . . . . . . . . . . . .
CD4002M/CD4002C Dual4·lnput NOR Gate ..............................•........... '
CD40028M/CD4002BC Dual4-lnput Buffered NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CD4006BM/CD4006BC 18·Stage Static Shift Register. . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CD4007M/CD4007C Dual Complementary Pair Plus Inverter. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CD4008BM/CD4008BC 4·Bit full Adder' ...........•....... : ... '. . . . . . . . . . . . . . . . . . . . . .
CD4009M/CD4009C Hex Buffer (Inverting). . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . .
CD4010M/CD4010C Hex Buffer(Non·lnverting) .......................................
CD4011 M/CD4011C Quad 2·lnput NAND Gate, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CD4011 BM/CD4011 BC Quad 2-lnput NAND Buffered B Series Gate. . . . . . . . . . . . . . . . . . . . . . .
CD4012M/CD4012C Dual4·lnput NAND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . .
CD4012BM/CD4012BC Dual4·lnput Buffered NAND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CD4013BM/CD4013BC Dual D Flip-Flop ............ . . . • . . . .. . . . . . . . . . . . . . . . . . . . . . . . .
CD4014BM/CD4014BC 8·Stage Static Shift Register .....•............................
CD4015BM/CD4015BC Dual4·Bit Static Register .......................... : . . . . . . . . . . .
. CD4016BM/CD4016BC Quad Bilateral Switch ..........................,..............
CD4017BM/CD4017BC Decade Counter/Divider with 10 Decoded Outputs ........ : . . . . . . . .
CD4018BM/CD4018BC Presettable Divide·by·N Counter ............................. '. . .
CD4019BM/CD4019BC Quad AND·OR Select Gate ............•.......................
CD4020BM/CD4020BC 14·Stage Ripple·Carry Binary Counter/Divider ..... '. . . . . . . . . . . . . . .
CD4021 BM/CD4021 BC 8~Stage Static Shift Register ........•.........................
CD4022BM/CD4022BC Divide·by·8 Counter/Divider with 8 Decoded Outputs ............ . . .
CD4023M/CD4023CTriple3·lnput NOR'Gate. . . .. . . .. . . .. . .. • .. .. .•. . . .. . .... . . .. . . .. .
CD4023BM/CD4023BC Triple 3·lnput Buffered NAND Gate ......•..... '. . . . . . . . . . . . . . . . . .
CD4024BM/CD4024BC 7·Stage Ripple-Carry Binary Counter/Divider .. '. . . . . . . . . . . . . . . . . . .
CD4025M/CD4025CTriple3·lnput NAND Gate ................................. '. . .. . . .
CD4025BM/CD4025BC Triple 3·lnput Buffered NOR Gate ...............................
CD4027BM/CD4027BC Dual J·K Master/Slave Flip·Flop with Set and Reset ................
CD4028BM/CD4028BC BCD·to·Decimal Decoder .•................. : . . . . . . . . . . . . . . . . . .
CD4029BM/CD4029BC Presettable Binary/ Decade Up/Down Counter ........ :............
CD4030M/CD4030CQuad Exclusive·ORGate. . . . . . . . . . . . . . .. .. . . . .. . . .. . . ... . . . . .. . ..
CD4031 BM/CD4031 BC 64·Stage Static Shift Register .................................
CD4034BM/CD4034BC 8·Stage TRI·STATE Bidirectional Parallel/Serial
Input/Output Bus Register .. : ..................... '.' .......................... \.
CD4035BM/CD4035BC 4·Bit Parallel·ln/Parallel·OutShif~ Register ..... , ........... , . : . . .
CD4040BM/CD4040BC 12·Stage Ripple Carry Binary Counter/Divider. . . . . . . • . . . . . . . . . . . . .
_ CD4041M/CD4041CQuadTrue/ComplemehtBuffer...................................
CD4042BM / CD4042BC Quad Clocked D Latch ....•............'. . . . . . . . . . . . . . . . . • . . . . .
CD4043BM/CD4043BC TRI·STATE NOR R/S Latches. . . . . . . • . . . . . . . . . . . . . . . . • . . . . . . . . . .
CD4044BM/CD4044BC TRI·STATE NAND R/S Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CD4046BM/CD4046BC Micropower Phase·Locked Loop. . . . . . . •. . . . . . . . . . . . . . . . . . . . . . . .
CD4047BM/CD4047BC Low Power Monostable/Astable Multivibrator. . . . . . . . . . . . . . . . . . . . .
CD4048BM/CD4048BC TRI-STATE Expandable 8·Function 8·lnput Gate. . . . . . . . . . . . . . . . . . . .
CD4049UBM/CD4049UBC Hex Inverting Buffer ........................... "1"..........
CD4050BM/CD4050BC Hex Non·lnverting Buffer. . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CD4051 BM/CD4051 BC Analog Multiplexers/Demultiplexers. . . . . . . . . . . . . . .. . . . . . . . . . . . .
CD4052BM/CD4052BCAnalog Multiplexers/Demultiplexers .. ·............... : . . . . . . . . . .
CD4053BM/CD4053BCAnalog Multiplexers/Demultiplexers ........................... ,
CD4060BM/CD4060BC 14·Stage Ripple Carry Binary CounterlDivider . . . . . . . . . . . . . . • . . . . . .
20
5·5
5·8
5·12
5·17
5·21
5·24
5·27
5·30
5·33
5·33
5·8
5·12
5-17
5·21
5·35
5-40
5·44
5·48
5-55
5·60
5'64
5·67
5·72
5·55
5·76
5·80
5·84
. 5·76
5·80
5·87
5·91
5·94
5·100
5·103
5·107
5·115
5-67
5·119
5·123
5·127
5·127
5·131
5·138
5·143
5·149
5·149
5·154
5·154
5·154
5·67
Alphanumeric Index (Continued)
CD4066BM/CD4066BCQuad Bilateral Switch
CD4069UBM/CD4069UBC Inverter Circuits .......................................... .
CD4070BM/CD4070BC Quad 2-lnput Exclusive-OR Gate ................ '............... .
CD4071 BM/CD4071 BC Quad 2-lnput OR Buffered B Series Gate ......................... .
CD4072BM/CD4072BC Dual4-lnput OR Buffered B Series Gate ......................... .
CD4073BM/CD4073BC Double Buffered Triple 3-lnput AND Gate ........................ .
CD4075BM/CD4075BC Double Buffered Triple 3-lnput OR Gate ......................... .
CD4076BM/CD4076BC TRI-STATE Quad Flip-Flop .................................... .
CD408J BM/CD4081 BC Quad 2-lnput AND Buffered B Series Gate ....................... .
CD4082BM/CD4082BC Dual4-lnput AND Buffered B Series Gate ........................ .
CD4089BM/CD4089BC Binary Rate Multiplier ....................................... .
CD4093BM/CD4093BC Quad 2-lnput NAN D Schmitt Trigger ............................ .
CD4094BM/CD4094BC 8-Stage Shift/Store Register .................................. .
CD4099BM/CD4099BC 8-Bit Addressable Latches ................................... .
CD40106BM/CD40106BC Hex Schmitt Trigger ....................................... .
CD40160BM/CD40160BC DecadeCounterwith Asynchronous Clear '..................... .
CD40161 BM/CD40161 BC Binary Counter with Asynchronous Clear ...................... .
CD40162BM/CD40162BC Decade Counter with Asynchronous Clear ..................... .
CD40163BM/CD40163BC Binary Counter with Asynchronous Clear ...................... .CD40174BM/CD40174BC Hex D Flip-Flop ........................................... .
CD40175BM/CD40175BC Quad D Flip-Flop .......................................... .
CD40192BM/CD40192BC Synchronous 4-Bit Up/Down Decade Counter .................. .
CQ40193BM/CD40193BC Synchronous 4-Bit Up/Down Binary Counter .-.................. .
CD4503BM/CD4503BC Hex Non-Inverting TRI-STATE Buffer ............................ .
CD4510BM/CD4510BC BCD Up/Down Counter ...................................... .
CD4511 BM/CD4511 BC BCD-to-7-Segment Latch DecoderlDriver ........................ .
CD4512BM/CD4512BC 8-Channel Data Selector ..................................... .
CD4514BM/CD4514BC 4-Bit Latched 4-to-16 Line Decoders ........................... .
CD4515BM/CD4515BC 4-Bit Latched 4-to-16 Line Decoders ........................... .
CD4516BM/CD4516BC Binary Up/Down Counter ................................ : .... .
CD4518BM/CD4518BC Dual Synchronous Up Counter ................................ .
CD4519BM/CD4519BC 4-Bit AND/OR Selector ...................................... .
CD4520BM/CD4520BC Dual Synchronous Up Counter ................................ .
CD4522BM/CD4522BC Programmable Divide-by-n 4-Bit BCD Counter .................... .
CD4526BM/CD4526BC Programmable Divide-by-n 4-Bit Binary Counter .................. .
CD4527BM/CD4527BC BCD Rate Multiplier ......................................... .
CD4528~M/CD4528BC Dual Monostable Multivibrator ................................ .
CD4529BM/CD4529BC Dual4-Channel or Single 8-Channel Analog Data Selector .......... .
CD4538BM/CD4538BC Dual Monostable Multivibrator ................................ .
CD4541 BM/CD4541 BC Programmable Timerwith Oscillator ........................... .
CD4543BM/CD4543BC BCD-to-7-Segment Latch/Decoder/Driver for
Liquid Crystal Displays: ....................................................... .
CD4584BM/CD4584BC Hex SchmittTrigger(See CD40106 data sheet) .................... .
CD4723BM/CD4723BC Dual4-Bit Addressable Latch ................................. .
CD4724BM/CD4724BC 8-Bit Addressable Latch ..................................... .
MB-18 MM54C/74CVoitage Translation/Buffering .................................... .
MM5034, MM5035 Octal80-Bit Static Shift Register .................................... .
MM5307 Baud Rate Generator/Programmable Divider ................................. .
MM5368CMOSOsciliatorDividerCircuit ................... ; ....................." .. .
M M5369 Series 17 Stage Osci lIatorlDivider .......................................... .
MM53107 Series 17-Stage Oscillator/Divider ........................................ .
21
5-162
5-168
5-172
5-176
5-181
5-184
5-184
5-188
5-176
5-181
5-192
5-199
5-204
5-209
5-214
5-218
5-218
5-218
5-218
5-223
5-223
5-226
5-226
5-231
5-235
5-242
5-248
. 5-253
5-253
5-235,
5-258
5-263
5-258
5-267
5-267
5-192
5-275
5-281
5-287
5-295
5-300
5-214
5-306 '
5-306
2-257
7-3
7-6
7-11
• 7-14
7-17
Alphanumeric Index(ContinUed) ,
MM53126 Infra Red Transmitter .................................................' .. .
MM53226 Infra Red Transmitter ................................................... .
M M5437 Noise Generator ........................................................ .
MM5450, MM5451 LED Display Drivers .............................................. .
MM5452, MM5453 Liquid Crystal Display Drivers ..................................... .
MM5480 LED Display Driver .............................. : ..................... ".. .
MM5481 LED Display Driver ....................................... , .............. .
MM5483 Liquid Crystal Display Driver ............................................ , ..
MM5484, MM5485 16-Segment LED Display Driver, 11 Segment LED Display Driver ......... .
M M5486 LED Display Driver ............................... _........ " ............. .
M M54240 Asynchronous Receiver/Transmitter Remote Controller ....................... .
MM58167A Microprocessor Real Time Clock ........................................ .
MM58174A Microprocessor Real Time Clock ........................................ .
'MM58201 Multiplexed LCD Driver ....................................•.............
MM58241 High Voltage Display Driver .............. : ............................... .
MM58242 High Voltage 20 Output Vacuum Fluorescent Display Driver .................... .
MM58248 High Voltage 35 Output Vacuum FluorescentDisplay Driver ................... .
MM58250 Infra Red Transmitter .... : .. '............................................ .
MM58274 Microprocessor Real Time Clock .......................................... .
MM58341 High Voltage 32 Output Vacuum Fluorescent Display Driver ................... .
MM58342 High Voltage 20 Output Fluorescent Display Driver .............•..... : ....... .
MM58348 High Voltage 35 Output Vacuum Fluorescent Display Driver. ................... .
MM58438 32-Bit LCD Display Driver .................... : ... '............... : ....... .
MM58538 Multiplexed LCD8-Row/26-Column Driver ... _.............................. .
MM58539 Multiplexed LCD 34-Column Driver ........... '............................. .
MM58540 Multiplexed LCD 32-Row/32-Column Driver ................................. .
MM58548 Multiplexed LCD 16-Row/16-Column Driver ................................. .
MM54COO/M M74COO Quad 2-lnput NAN D Gate ......................., ............... .
M M54C02/M M7 4C02 Quad 2-lnput NOR Gate ........................................ .
MM54C04/MM74C04 Hex Inverter ................................................. .
MM54C08/MM74C08Quad2-lnputANDGate ........................................ .
M M54C10/M M7 4C10 Triple 3-lnput NAN D Gate ...................................... .
MM54C14/MM74C14 HexSchmittTrigger ........................................... .
MM54C20/MM74C20 Dual4:lnput NAND Gate: ........•..............................
Mty154C30/MM74C30 8-lnput NAND Gate ........................................... .
MM54C32/MM74C32'Quad 2-lnput OR Gate ......................................... "
MM54C42/MM74C42 BCD-to-Decimal Decoder ...................................... .
MM54C48/MM74C48 BCD-to-7-Segment Decoder ....................... '............. .
MM54C73/MM74C73 Dual J-K Flip-Flops with Clear ................................... .
MM54C74/MM74C74 Dual D Flip-Flop .............................................. .
MM54C76/MM74C76 Dual J-K Flip-Flops with Clear and Preset ......................... .
MM54C83/MM74C83 4-Bit Binary Full Adder ...............• , ..................... '.. .
MM54C85/MM74C85 4-Bit Magnitude Comparator ................................... .
MM54C86/MM74C86 Quad 2-lnput EXCLUSIVE-OR Gate ..... : ............... : ......... .
M M54C89/M M7 4C89 64-Bit (16 x 4) TRI.STATE Random Access Memory ................. .
MM54C90/MM74C90 4-Bit Decade Counter ......... : ............................... .
MM54C93/MM74C93 4-Bit Binary Counter .......................................... .
MM54C95/MM74C95 4-Bit Right-ShiftiLeft-Shift Register ............................. .
MM54C107lMM74C107 Dual J-K Flip-Flops with Clear ................................. .
MM54C150/MM74C150 16-Lineto 1-Line Multiplexer ................................. .
MM54C151/MM74C151 8-Channel Digital Multiplexer ................................ .
MM54C154/MM74C154 4-Lineto 16-Line Decoder/Demultiplexer .................... ~ .. .
22
7-19
7-24
7-29
7-32
7-37
7-43
7·47
7·51
7·54
7·57
7·62
7·70
7·78
7·85
7·90
7·95
7·100
7·105
7·113
7·126
7·131
7·136
7·141
7·145
7·150
7·155
7·160
6·5
6·5
6·5
6-9
6·5
6·12
6·5
6·15
6-18
6·20
6·22
6·27
6·30
6·27
6·34
6·38
6·41
6·44
6-48
6·48'
6·52
6·27
6·54
6-59
6·63
Alphanumeric
Index(continUed)
MM54C157/MM74C157Quad2-lnput Multiplexer ______________________ ; ___________ ... .
MM54C160/MM74C160 Decade Counter with Asynchronous Clear ...................... .
MM54C1611 M M7 4C161 Binary Counter with Asynchronous Clear ....................... .
MM54C162/MM74C162 DecadeCounterwith Synchronous Clear ....................... .
MM54C1631 M M74C163 Binary Counter with Synchronous Clear ........................ .
MM54C164/MM74C164 8-Bit Parallel-Out Serial Shift Register ......................... .MM54C165/MM74C165 Parallel-Load 8-Bit Shift Register' .............................. .
M M54C173/M M7 4C173 TRI-STATE Quad D FI i p-Flop .................................. .
MM54C174/MM74C174 Hex D Flip-Flop ............................................ .
MM54C175/MM74C175 Quad D Flip-Flop ............................................ .
M M54C192/M M7 4C192 Synchronous 4-Bit Up/Down Decade Counter .................... .
M M54C193/M M74C193 Synchronous 4-BitUp/Down Binary Counter ..................... .
MM54C195/MM74C195 4-Bit Register ............................................. .
MM54C200/MM74C200 256-Bit (256 x 1) TRI-STATE Random Access Memory ............. .
MM54C221/MM74C221 Dual Monostable Multivibrator ................................ .
MM54C240/MM74C240 Octal Buffers and Line Drivers with TRI-STATE
Outputs (Inverting) ............................................................ .
MM54C244/MM74C244 Octal Buffers and Line Drivers with TRI-STATE
Outputs (Non-Inverting) ........................................................ .
MM54C373/MM74C373 Octal Latch with TRI-STATE Outputs ........................... .
MM54C374/MM74C374 Octal D-Type Flip-Flop with TRI-STATE Outputs ................... .
M M54C901/M M7 4C901 Hex .Inverting TTL Buffer ..................................... .
MM54C902/MM74C902 Hex Non-Inverting Buffers ........ '.' .......................... .
MM54C903/MM74C903 Hexlnverting PMOS Buffer ................................... .
MM54C904/MM74C904 Hex Non-Inverting PMOS Buffers .............................. .
MM54C905/MM74C905 12-Blt Successive Approximation Register ..................... .
MM54C906/MM74C906 Hex Open Drain N-Channel Buffer ............................. .
MM54C907/MM74C907 Hex Open Drain P-Channel Buffer. ............................. .
MM54C909/MM74C909 Quad Comparator .......................................... .
MM54C910/MM74C910 256-Bit(64 x 4) TRI-STATE Random Access Memory .............. .
M M54C9141 M M7 4C914 Hex SchmittTrigger with Extended Input Voltage ................. .
M M54C915/M M7 4C915 7-Segment-to-BCD Converter ................................ .
MM54C922/MM74C922 16-Key Keyboard Encoder .................. : ................ .
MM54C923/MM74C923 20-Key Keyboard Encoder ................................... .
MM54C932/MM74C932 Phase Comparator .......................................... .
MM54C941/MM74C941 Octal Buffers/Line Receivers/Line Drivers with
TRI-STATE Outputs ....... : ................................................... .
MM54C989/MM74C989 64-Bit(16 x 4) TRI-STATE Random Access Mem~ry ............... .
MM70C95/MM80C95 TRI-STATE Hex Buffers ........................................ .
MM70C96/MM80C96TRI-STATE Hex Inverters .........•..............................
MM70C97/MM80C97TRI-STATE Hex Buffers ................................. : ...... .
M M70C98/M M80C98 TRI-STATE Hex Inverters ....................................... .
MM72C19/MM82C19TRI-STATE 16-Lineto 1-LineMultiplexer ........................... .
M M74C908 Dual CMOS 30 Volt Relay Driver ..................... ;'................... .
MM74C911 4-Digit LED Display Controller ....................................... _.. .
MM74C912 6-Digit BCD LED Display Controller Driver ................................ .
MM74C917 6-Digit Hex LED Display Controller Driver ................................. .
M M74C918 Dual CMOS 30 Volt Relay Driver ......................................... .
MM74C925 4-Digit Counter with Multiplexed 7-Segment Output Driver ................... .
MM74C926 4-Digit Counter with Multiplexed 7-Segment Output Driver ................... .
MM74C927 4-Digit Counter with Multiplexed 7-Segment Output Driver ................... .
MM74C928 4-Digit Counter with Multiplexed 7-Segment Output Driver ................... .
23
6-66
6-68
6-68
6-68
6-68
6-73
6-77
6-81
6-84
6-87
6-90
6-90
6-94
6-97.
6-101
6-105
6-105
6-110
6-110
6-117
6-117
6-117
6-117
6-121
6-126
6-126
6-129
6-134
6-138
6-141
6-145
6-145
6-151
6-155
6-160
6-164
6-164
6-164
6-164
6-54
6-169
6-173
6-180
6-180
6-169
6-186
6-186
6-186
6-186
Alphanumeric
Index(continUed)
MM74C945 4112-Digit LCD Up Counter/Latch Driver. • . . . . . . . . • . . . . . . . . . . . • . . . . . . . . . . . .
MM74C946 4-Digit LCD Up-Down Counter/Latch/Driver . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . .
MM74C947 4-Digit LCD Up-Down Counter/Latch/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM74C956 4 Character LED Alphanumeric Display Controller Driver(17-Segment) . . . . . . . . . .
MM78C29/MM88C29 Quad Single-Ended Line Driver ............................ '. . . . . . .
MM78C30/MM88C30 Dual
.. . . .. .. .. . . . .. . .. . . . . . . •. . . .. . .. . ..
. Differential Line Driver.
.
MM54HCOO/MM74HCOOQuad2-lnput NAND Gate. . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .. . . . . .
MM54HC02/MM74HC02 Quad 2-lnput NOR Gate ......................................
MM54HC03/MM74HC03, Quad 2-lnput Open Drain NAND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC04/MM74HC04 Hex Inverter ........................................ : .... :.
MM54HCU04/MM74HCU04 Hex Inverter .. , ....................................... : . .
MM54HC08/MM74HC08Quad 2-lnput AND Gate ................. ',' . . . . . . . . . . . . . . . . . . .
MM54HC10/MM74HC10Tripie 3-lnput NAND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
, MM54HC11/MM74HC11Triple 3-lnput AND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC14/MM74HC14 Hex Inverting Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC20/MM74HC20 Dual4-lnput NAND Gate ................... . . . • . . . . . . . . . . . . . .
MM54HC27/MM74HC27 Triple 3-lnput NOR Gate .....•....... " ...... , . . . . .. . . .. . . . . . .
MM54HC30/MM74HC30 8-lnput NAND Gate . . . .. . .. . . . . .. . . . . .. . . . . . .. . . . . . . . . . . .. . .
MM54HC32/MM74HC32 Quad 2-lnput OR Gate .......................... '............ /
MM54HC42/MM74HC42 BCD-to-Decimal Decoder ....................................
MM54H051/MM74HC51 DuaIAND-OR-lnvertGate ....................................
MM54HC58/MM74HC58 Dual AND-OR Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC73/MM74HC73 Dual J-K Flip-Flops with Clear. . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC74/MM74HC74 Dual D Flip-Flop with Preset and Clear ...... .'. . .. . . . . . . . . . . . . . . .
MM54HC75/MM74H.C75 4-Bit Bistable Latch with Q and Q Output ............... ; . . . . . . .
MM54HC76/MM74HC76 Dual J-K Flip-Flops with Preset and Clear. . . . . . . . . . . . . . . . . . . . . . . .
rV1M54HC85/MM74HC85 4-Bit Magnitude Comparator ........ '. . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC86/MM74HC86Quad2-lnput Exclusive OR Gate ...•...........................
MM54HC107/MM74HC107 Dual J-K Flip-Flops with Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC109/MM74HC109 Dual J-K Flip-Flops with Preset and Cle~r ',' . . . . . . . . . . . . . . . . . . . .
MM54HC112/MM74HC112 Dual J-K F,lip-Flops with Preset and Clear. . . . . . . . . . . . . . . . . . . . . .
MM54HC113/MM74HC113 Dual J-K Flip-Flops with Preset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC123A/MM74HC123A Dual Retriggerable Monostable Multivibrator ......... ',' . . . .
MM54HC125/MM74HC125 TRI-STATEQuad Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC126/MM74HC126TRI-STATE Quad Buffers. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .
MM54HC132/MM74HC132 Quad 2-lnput NAND Schmitt Trigger ................. : ..... : . .
MM54HC133/MM74HC133 13-lnput NAND Gate.. . . . . . . . . . . . . . . . . . . ... .. . . . . . . . . . . . . . .
MM54HC137/MM74HC137 3-to-8 Line Decoder with Address Latches {Inverted Output) . . . . . .
MM54HC138/MM74HC138 3-to-8 Line Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC139/MM74HC139 DuaI2-to-4 Line Decod~r .................. , . . . . . . . . . . . . . . . .
MM54HC147/MM74HC147 10-to-4 Line Priority Encoder ...............................
MM54HC149/MM74HC149 8-to-8 Line Priority Encoder. . . . . . . . . . . . . . . . . . . . • . . . . . . . . . • .
MM54HC1511MM74HC151 8-Channel Multiplexer. .. . . . . .. . . . . . . . . . . . .. . . . . . . . . .. . . . .
MM64HC153/MM74HC153 Dual4-lnput Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC154/MM74HC154 4-to-16 Line Decoder.. . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. .
MM54HC155/MM74HC155 DuaI2-to-4 Line Decoders. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC157/MM74HC157 Quad2-input Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC158/MM74HC158Quad 2-lnput Multiplexer(lnverted Output) .................. ','
MM54HC160/MM74HC160Synchronous Decade Counter ................... '. . . . . . . . . . .
MM541"1C161/MM74HC161 Synchronous Binary Counter ..•.......... .".................
MM54HC162/MM74HC162 Synchronous Decade Counter ...............................
24
6-190
6-197
6-190
6-204
6-208
6-208
3-7
3-10
3-13
3-16
3-19
3-22
3-25
3-28
'3-31
3-34
3-37
3-40
3-43
3-46
3-49
3-49
3-52
3-56
3-59
3-62
3-66
3-70
3-73
3-77
3-80
3-84
. 3-88
3-93
3-93
3-96
3-99
3-102
3-106
3-109
3-112
3-115
3-118
3-121
3-124
3-128
3-131
3-131
3-135
3-135
3-135
Alphanumeric
Index(continUed)
MM54HC163/MM74HC163 Synchronous Binary Counter .............................. .
MM54HC164/MM74HC164 8-Bit Serial-In Parallel-Out Shift Register .................... .
MM54HC165/MM74HC165 Parallel-In Serial-Out8-Bit Shift Register ................. " ... .
MM54HC173/MM74HC173 TRI-STATE Quad 0 Flip-Flop ............................... .
MM54HC174/MM74HC174 Hex 0 Flip-Flopswith Clear ................................ .
MM54HC175/MM74HC175 Quad D-Type Flip-Flop with Clear ....... .' ................... .
MM54HC181/MM74HC181 Arithmetic Logic Units/Function Generators .................. .
MM54HC182/MM74HC182 Look-Ahead Carry Generator ............................... .
MM54HC190/MM74HC190 Synchronous Decade Up/Down Counters with Mode Control .... .
MM54HC191/MM74HC191 Synchronous Binary Up/Down Counters with Mode Control ..... .
MM54HC192/MM74HC192 Synchronous Decade Up/Down Counters .................... .
MM54HC193/MM74HC193 Synchronous Binary Up/Down Counters ..................... .
MM54HC194/MM74HC194 4-Bit Bidirectional Shift Register ........................... .
MM54HC195/MM74HC195 4-Bit Parallel Shift Register ............................... .
MM54HC221A/MM74HC221A Dual Non-Retriggerable Monostable Multivibrator .......... .
MM54HC237/MM74HC237 3-to-8 Decoderwith Address Latches ....................... .
MM54HC240/MM74HC240 Inverting Octal TRI-STATE Buffer ........................... .
MM54HC241/MM74HC241 Octal TRI-STATE Buffer ................................... .
MM54HC242/MM74HC242 Inverting Quad TRI-STATETransceiver ....................... .
MM54HC243JMM74HC243 Quad TRI-STATETransceiver ............................... .
MM54HC244/MM74HC244 Octal TRI-STATE Buffer ................................... .
MM54HC245/MM74HC245 Octal TRI-STATETransceiver ............................... .
MM54HC251/MM74HC251 8-Channel TRI-STATE Multiplexer .......................... .
MM54HC253/MM74HC253 Dual4-Channel TRI-STATE Multiplexer ....................... .
MM54HC257JMM74HC257 Quad 2-Channel TRI-STATE Multiplexer ...................... .
MM54HC259/MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder ................. .
MM54HC266/MM74HC266 Quad 2-lnput Exclusive NOR Gate .......................... .
MM54HC273/MM74HC273 Octal 0 Flip-Flops with Clear ............................... .
MM54HC280/MM74HC280 9-Bit Odd/Even Parity Generator/Checker ................... .
MM54HC283/MM74HC283 4-Bit Binary Adderwith Fast Carry .......................... .
MM54HC298/MM74HC298 Quad 2-lnput Multiplexers with Storage ...................... .
MM54HC299/MM74HC299 8-BitTRI-STATE Universal Shift Register ..................... .
MM54HC354/MM74HC354 8-Channel TRI-STATE Multiplexers with Latches .............. .
MM54HC356/MM74HC356 8-Channel TRI-STATE Multiplexers with Latches .............. .
MM54HC365/MM74HC365 Hex TRI-STATE Buffer .................................... .
MM54HC366/MM74HC366 Inverting HexTRI-STATE Buffer ............................. .
MM54HC367/MM74HC367 Hex TRI-STATE Buffer ............ '........................ .
MM54HC368/MM74HC368 Inverting Hex TRI-STATE Buffer ............................. .
MM54HC373/MM74HC373 TRI-STATE Octal D-Type Latch .............................. .
MM54HC374/MM74HC374 TRI-STATE Octal D-Type Flip-Flop ........................... .
MM54HC390/MM74HC390 Dual4-Bit Decade Counter ................................ .
MM54HC393/MM74HC393 Dual4-Bit Binary Counter ................................. .
MM54HC423A/MM74HC423A Dual Retriggerable Monostable Multivibrator .............. .
MM54HC521/MM74HC521 8-Bit Magnitude Comparator(Equality Detector) .............. .
MM54HC533/MM74HC533TRI-STATE Octal D-Type Latch with Inverted Outputs ........... .
MM54HC534/MM74HC534 TRI-STATE Octal D-Type Flip-Flop with Inverted Outputs ......... .
MM54HC540/MM74HC540 Inverting Octal TRI-STATE Buffer ........................... .
MM54HC541/MM74HC541 Octal TRI-STATE Buffer ................................... .
3-135
3-140
3-143
3-147
3-151
3-154
3-158 .
MM54HC563/MM74HC563 TRI-STATE Octal D-Type Latch with Inverted Outputs ........... .
MM54HC564/MM74HC564 TRI-STATE Octal D-Type Flip-Flip with Inverted Outputs ......... .
MM54HC573/MM74HC573 TRI-STATE Octal D-Type Latch ........................ , ..... .
3-298
3-301
3-304
25
3-166
3-170
3-170
3-177
3-177
3-184
3-188
3-192
3-197
3-201
3-201
3-206
3-206
3-210
3-214
3-218
3-221
3-224
3-227
3-231
3-234
3-238
3-241
3-246
3-250
3-255
3-255
3-263
3-263
3-263
3-263
3-270
3-273
3-276
3-276
3-281
3-286
3-289
3-292
3-295
3-295
Alphanumeric
Index(continUed)
MM54HC574/MM74HC574 TRI-STATE Octal D-Type Flip-Flop ........................... .
3-307
MM54HC589/MM74HC589 8-Bit Shift Register with Input Latches and
TRI:STATE Serial Output ....................................................... .
3-310
-MM54HC590/MM74HC590 8-Bit BinaryCounterwith TRI-STATEOutput Register .......... .
3-315
MM54HC592/MM74HC592 8-Bit Binary Counter with Input Register ........... .' ......... .
3-317
MM54HC593/MM74H,C593 8-Bit Binary Counter with, Bidirectional
3-317
Input Register/CounterOutputs ........... ; ........................... : ......... .
3-320
MM54HC595/MM74HC595 ,8-Bit Shift Registers with Output Latches .................... .
MM54HC597/MM74HC597 8-Bit Shift Registers ~ith Input Latches ..................... .
3-325
MM54HC640/MM74HC640 Inverting Octal TRI-STATE Transceiver ....................... .
3-330
3-330
MM54HC643/MM74HC643True-lnverting Octal TRI-STATETransceiver ............ ; ...... .
MM54HC646/MM74HC646 Non-Inverting Octal Bus Transceiver/Registers ................ .
3-334
MM54HC648/MM74HC648 Inverting Octal Bus Transceiver/Registers .................... .
3-334
3-341
MM54HC688/MM74HC688 8-Bit MagnitudeComparator(Equality Detector) .............. .
MM54HC4002/MM74HC4002 Dual4-lnput NOR Gate .................................. .
3-357
MM54HC4016/MM74HC4016Quad Analog Switch ................................... .
3-360
MM54HC4017/MM74HC4017 Decade CounterlDividerwith 10 Decoded Outputs ...... :-: ... .
3·365
MM54HC4020/MM74HC4020 14-Stage BinaryCounter .......................... '...... .
3-369
MM54HC4024/MM74HC4024 7-Stage Binary Counter , ................................ .
3-369
MM54HC4040/MM74HC4040 12·Stage Binary Counter ................................ .
3-369
MM54HC4046/MM74HC4046 CMOS Phase Lock Loop ................................ .
3-374
MM54HC4049/MM74HC4049 Hex Inverting Logic Level Down,Converter .................. .
3-383
MM54HC4050/MM74HC4050 Hex Logic Level Down Converter. : ....................... .
3-383
MM54HC4051/MM74HC4051 8-ChannelAnalog Multiplexer ........................... .
3-386
MM54HC4052/MM74HC4052 Dual4-Channel Analog Multiplexer ....................... .
3-386
MM54HC4053/MM74HC4053Triple2-Channel Analog Multiplexer ....................... .
3-386
MM54HC4060/MM74HC4060 14-Stage Binary Counter ................................ .
3-393
MM54HC4066/MM74HC4066 Quad Analog Switch ................................... .
3-397
MM54HC4075/MM74HC4075Triple3-lnput OR Gate .................................. .
3-402
MM54HC4078/MM74HC4078 8·lnput NOR/OR Gate ...................... : ........... .
3-405
MM54HC4316/MM74HC4316Quad Analog Switch with Level Translator .................. .
3-408
MM54HC4511/MM74HC4511 BCD-to-7 SegmentLatch/DecoderlDriver .................. .
3-413
MM5411C4514/MM74HC4514 4-to-16 Line Decoder with Lat 2V T ). Each time the circuit switches, a current
momentarily flows from Vee to Ground through
both output transistors. Sinee the threshold voltages
of the transistors do not change with increasing
Vee, the input voltage range through which the
upper and lower transistors are conducting simultaneously increases as Vee increases. At the same
time, the higher Vee provides higher V GS voltages
which also increase the magnitude of the J DS
cur~ents. Incidently, if the rise time of the input
signal was zero, there would be .no current flow
from V~e to Ground through the circuit. This
current flows because the input signal has a finite
rise time and, therefore, the input voltage spends a
finite amount of time passing through the region
where both transistors conduct simultaneously.
Obviously, input rise and fall times should be kept
to a minimum to minimize VI power dissipation.
2
•
+ ---
V, .. (VOLTSI
(el
(dl
TL/F/6019·8
FIGURE 2-4. Transfer Characteristics vs Vee.
Considering the subject of noise in a CMOS system,
we must discuss at least two specs: noise immunity
and noise margin.
National's CMOS circuits have a typical noise
immunity of 0.45 Vee. This means that a spurious
input which is 0.45 Vee or less away from Ve~ or
Ground typically will not prop~gate through the
system as an erroneous logic level. This does not
mean that no signal at all will appear at the output
of the first circuit. In fact, there will be an output
signal as a result of the spurious input, but it will
be reduced in amplitude. As this signal propagates
through the system, it will be attenuated even
more by each circuit it passes through until it
finally disappears. Typically, it will not change any
signal to the opposite logic level. In a typical
flip flop, a 0.45 Vee spurious pulse on the clock
line would not cause the flop to change state.
Let's look at the transfer characteristics, Figure 2-4,
as they vary with Vee. For the purposes of this
discussion we will assume that both transistors in
our basic inverter have identical but complementary
characteristics and threshold voltages. Assume the
threshold voltages, VT , to be 2V. If Vee is less
than the threshold voltage of 2V, neither transistor
can ever be turned on and the circuit cannot
operate. If Vee is equal to the threshold voltage
exactly then we are on the curve Figure 2-4a.
We appear to have 100% hysteresis. However, it is
not truly hysteresis since both output transistors
are off and the output voltage is being held on the
gate capacitances of succeeding circuits. If Vee is
somewhere between one and two threshold volt·
ages (Figure 2·4b), then we have diminishing
amounts of "hysteresis" as we approach Vee equal
to 2V T (Figure 2-4c). At Vee equal to two thresholds we have no "hysteresis" and no current flow
through both the upper and lower transistors during switching. As Vee exceeds two thresholds the
National also guarantees that its CMOS circuits
have a 1 V DC noise margin over the full power
supply range and temperature range and with any
combination of inputs. This is simply a variation of
the noise immunity spec only now a specific set of
input and output voltages have been selected and
guaranteed. Stated verbally, the spec says that for
the output of a circuit to be within 0.1 Vee volts
of a proper logic level (Vee or Ground). the input
2·5
.....
I":-
Z
2V T )
Figure 3-3.
'.
voltage, input voltage, input rise time aold output
load capacitance on system power dissipation, we
can say the following:
,_ Power supply voltage: CV2f power dissipation
increases as the square of power supply voltage.
VI power dissipation increases approximately
as the square of the power supply voltage.
2. Input voltage level: VI power dissipation increases if the input voltage lies somewhere
between Ground plus a threshold voltage and
Vee minus a threshold voltage. The highest
power dissipation occurs when V ,N is at 1/2
Vee. CV2f dissipation is unaffected.
3_ Input rise time: VI power dissipation increases
with longer rise times since the DC current path
through the device is established for a longer
period. The CV2f power is unaffected by slow
input rise times.
GNIl~
4_ Output load capacitance: the CV2f power dissipated in a circuit increases directly with load
capacitance. VI power in a circuit is unaffected
by its output load capacitance. However, in·
creasing output load capacitance will slow
down the output rise time of a circuit which in
turn will affect the VI power dissipation in the
devices it is driving.
1.... 0••
GNO_,
o
~1'Q'''l~-
,
VI POWER IS GIVEN BV:
PV1 '" Vee K2" /MAX x RISE TIME TO PERIOD RATIO
RISE TIME TO
PERIOD RATIO
"----v;-
Vee - 2Vy
WHERE - '-
" FREQUENCY
fRISE
x
+ IFALL
~
INTERFACES TO OTHER LOGIC TYPES
'TOTAL
P"I =
I/Z (Vee - IVy) 'CCMAX
/rRISE
There are two main ideas behind all of the following interfaces to CMOS. First, CMOS outputs
should satisfy the current and voltage requirements
of the other family's inputs. Second, and probably
most important, the other family's outputs should
swing as near as possible to the full voltage range
of the CMOS power supplies.
+ IFALL) FREO.
TL.IFI6019·13
FIGURE 3-3. DC Transient Power.
The maximum amplitude of the current is a rapidly
increasing function of the input voltage which in
turn is a direct function of the power supply
voltage. See Figure 2-4d.
P-Channel MOS: there are a number of things to
watch for when interfacing CMOS and P-MOS. The
first is the power supply set. Most of the more
popular P-MOS parts are specified with 17 to 24 V
power supplies while the maximum power supply
voltage for CMOS is 15V. Another problem
The actual amount of VI power dissipated by the
system is determined by three things: power supply
voltage, frequency and input signal rise time. A
very important factor is the input rise time. If the
2-7
~.---------~--------------------~-------------------------------------,
":Z
cc
is that unlike CMOS, the output swing of a pushpull P-MOS output is significantly less than the
power supply voltage across it. P-MOS swings from
very close to its more positive supply (V ss ) to
quite a few volts atJove its more negative supply
(V oo ). So, even if P-MOS uses a 15V _or lower
power supply set, its output sWing will not go low
enough for a reliable interface to CMOS. There are
a number of ways to solve this problem depending
on the configuration of the system. We will discuss
two solutions for systems that are built totally
'with MOS and one solution for systems that
include bipolar logic.
outputs. The CMOS can still drive P·MOS directly
and now the P-MOS can drive CMOS with no
pull-down resistors, The other restrictIOns are that
the total voltage across the CMOS is fess than 15V
and that the bias supply can handle the current
requirements of all the CMOS. This approach IS
useful If the P-MOS supply must be greater than
15V and the CMOS current requirement is low
enough to be done easily with a small discrete
component regulator.
,If the system has bipolar logic, It Will usually
have at least two power supplies. In this case, the
CMOS IS run off the bipolar supply ,and It interfaces directly to P-MOS, Figure 3-6,
FIGURE 3·4. A One Power Supply System Built
Entirely of CMOS and P·MOS.
Run the CMOS from the bipolar supplv and mterface directly to P·MOS
First, MOS only. P·MOS and CMOS uSing the
same power--supply of less than 15V, Figure 3-4.
FIGURE 3·6. A System With CMOS, P·MOS and Bipolar
logic.
In this configuration CMOS drives P-MOS directly.
However, P-MOS cannot drive CMOS directly be·
cause of its output will not pull down close e"ough
to the lower power supply rail. Rpo (R pull down)
is added to each P·MOS output to pull it all the
way down to the lower rail. Its value is selected
such that it is small enough to give the desired
RC time constant when pulling down but not so
small that the P-MOS output cannot pull it
virtually all the way up to the upper power supply
rail when it needs to. This approach will work with
push·pull as well as open drain P-MOS outputs.
N-Channel MOS: IIiterfacing to N·MOS is somewhat simpler than interfaCing to P·MOS although
Similar problems exist. First, N-MOS requires
lower power supplies than P-MOS, being in the
range of 5V to 12V. This is directly compatible
with CMOS. Second, N·MOS logiC levels range
from slightly above the lower power supply rail to
about 1 to 2V below the upper rail.
At the higher power supply voltages, N·MOS and
CMOS can be interfaced directly since the N·MOS
high logiC level will be only about 10 to 20 percent
below the upper rail. However, at lower supply
voltages the N·MOS output level will be down 40
to 40 percent below the urwer rail and something
may have to be done to raise it. The simplest solu·
tion is to add pull up resistors on the N·MOS
outputs as shown in Figure 3-7.
Another approach in a purely MOS system is to
build a cheap zener supply to bias up the lower
power supply rail of CMOS, Figure 3·5.
Use a blBSSUpplv to reduce the
lIoJtageacro~sthe
CMOS
to match the logl& swmg of the P·MOS. Make sure the
resultlllg voltage across the CMOS IS less than lSV.
TLlFI601917
Both operate IIIf ~ame supply With pull up leslStors optional from
N·MOS to CMOS
FIGURE 3-S. A P·MOS and CMOS System Where The
P·MOS Supply is Greater Than 1SV.
FIGURE 3-7. A'System With CMOS and N·MOS Only.
In this configuration the P·MOS supply is selected
to satisfy the P-MOS voltage requirement. The bias
supply voltage is selected to reduce the total
voltage across the CMOS (and therefore its logic
swing) to match the-minimum swing of the P·MOS
TTL, "LPTTL, DTL: two questions arise when
interfaCing bipolar logiC families to CMOS. First,
is the bipolar family's logic "1" output voltage high
enough to drive CMOS directly?
2·8
The LPTTL input current is small enough to allow
CMOS to drive two loads directly. Normal power
TTL input currents are ten times higher th-an
those in LPTTL and consequently the CMOS output voltage will be well above the input logic "0"
maximum of 0;8V: However, by carefully examining the CMOS output specs we will find that a two
input NOR gate can drive one TTL load, albeit
somewhat marginally. For example, the logical
"0" output voltage for both an MM74COO and
MM74C02 over temperature is specified at O.4V
sinking 360J,lA (about 420J,lA at 2SoCI with an
input voltage of 4.0V and a Vee of 4.7SV. Both
schematics are shown In Figure 3-9.
TTL, LPTTL, and DTL can drive 74C series CMOS
directly over the commercial temperature range
without external pull up resistors. However, TTL
and LPTTL cannot drive 4000 series CMOS directly
(DTL canl since 4000 series specs do not guarantee
that a direct interface with no pull up resistors will
operate properly.
DTL and LPTTL manufactured by National (NS
LPTTL pulls up one diode drop higher than the
LPTTL of other vendorsl will also drive 74C
directly over the entire military temperature ran·ge.
LPTTL manufactured by other vendors and standard TTL will drive 74C directly over most of the
mil temperature range. However, the TTL logic
"1" drops to a somewhat marginal level toward the
lower end of the mil temperature range and a pull
up resistor is recommended.
According to the curve of DC margin vs Vee for
CMOS in Figure 2-S, if the CMOS sees an input
voltage greater than Vee - 1.SV (Vee = SVI, the
output is guaranteed to be less than O.SV from
Ground. The next CMOS element will amplify
this O.SV level to the proper logic levels of Vee or
Ground. The standard TTL logic "1" spec is a VOUT
min. of 2.4V sourcing a current of 400J,lA. This
is an extremely conservative spec Sl nce a TTL
output will only approach a one level of 2.4V
under the extreme worst case conditions of lowest
temperature, high input voltage (0.8VI, highest
possible leakage currents (into succeeding TTL
devicesl, and Vee at the lowest allowable (V ce =
4.SVI.
TLlF16019·19
FIGURE 3-9a. MM74COO.·
Under nominal conditions (2SoC, Y'N = O.4V,
nominal leakage currents into CMOS and Vee =
SVI a TTL logic 'T' will be more like Vee - 2V o ,
or Vec - 1.2V. Varying only temperature, the
output will change by two times -2mV per e· C, or
-4 mV per "C. Vec - 1.2V is more than enough
to drive CMOS reliably without the use of a pull
up resistor.
If the system is such that the TTL logic "1" output
can drop below Vee - l.SV, use a pu II up resistor
to improve the logic "1" voltage into the CMOS.
r-i---1>-OX = A""+'B
TLlFI601920
FIGURE 3-9b. MM74C02.
Bot~ parts have the same current sinking spec but
their structures are different. What this means is
that either of the lower transistors in the MM74C02
can sink the same current as the tWQ lower series
transistors in the MM74COO. Both MM74C02
transistors together can sink twice the specified
current for a given output voltage. If we allow the
output voltage to go to 0.8V, then a MM74C02
can sink four times 360J,lA, or 1.44 mA which is
nearly 1.6 mAo Actually, 1.6 mA IS the maximum
Pull up resLstDI,Rpu• IS needed only at the lower end of the Mil
temperature range.
FIGURE 3-8_ TTL to CMOS Interface.
The second question is, can CMOS sink the bipolar
input current and not exceed the maximum value
of the bipolar logic zero input voltage? The logic
"1" input is no problem.
2-9
J;
Z
< 500 nW,
TUFI6020-7
10
FIGURE 7. MM74C04 Inverter Used as a Post Amplifier
for a Battery Operated Op Amp.
,,.
1[11
OPERATINGFRED.UENCY-Kz
TLlFI6020-5
The MM74C04 can also be used~with single supply
amplifier such as the LM324. With the circuit
shown in Figure 8, the open loop gain is approxi·
mately 160 dB. The LM324 has 4 amplifiers in a
package and the MM74C04 has 6 amplifiers per
package.
FIGURE 5. Typical Voltage Gain Versus Frequency
Characteristics for Amplifier Shown in Figure 2.
APPLICATIONS
+12V
Cascading Amplifiers for Higher Gain.
By cascading the basic amplifier block shown in
Figure 2 a high gain amplifier can be achieved. The
gain will be multipl ied by the nU,mber of stages
used. If more than one inverter is used inside the
feedback loop (as in Figure 6) a high~r open loop
gain is achieved which results in more accurate
closed loop gains.
v"
lOOK
TlIFI6020·B
FIGURE 8. Single SupplV Amplifier Using a CMOS
Cascade Post Amplifier with the LM324.
CMOS inverters can be paralleled for increased
power to drive higher current loads. Loads of
5.0 mA per inverter can be expected under AC
conditions.
TLlFI60206
Other 74C devices can be used to provide greater
complem~ntary current outputs. 'The MM74COO
NAND Gate will provide approximately 10 mA
FIGURE 6. Three CMOS Inverters Used as an X10 AC
Amplifier.
2·12
from the Vee supply while the MM74C02 will
supply approximately 10 mA from the n,eg~tive
supply, Shown in Figure 9 is an operational
ampl ifier using a CMOS power post ampl ifier to
provide greater than 40 mA complementary
currents.
TUF16020·10
Phase Shift
Oscillator Using MM74C04
c
"~"""
1/.
MM74CDO
1/.
MM14CJ10
v"
I ntegrator Using
Any I nverting CMOS Gate
TLlF16020·11
II.
MM14CD2
1/.
UM74CD2
IT}
1/.
MM14ca2
1/.
MM74CD2
-6.011
10K
IOUT"'SDmA
VoUT "'6.0 IIp~
Square Wave Oscillator
TLIF16020·9
FI GURE 9. MM74COO and MM74C02 Used as a Post
Amplifier to Provide I ncreased Current Drive.
Other Applications.
INPUT
Shown in Figure 10 is a variety of applications
utilizing CMOS devices. Shown is a linear phase
shift oscillator and an integrator which use the
CMOS devices in the linear mode as well as a few
circuit ideas for clocks and one'shots.
6
TlIFI602G-12
'V'"
C
T"".4RC
One Shot
TlIFJ6020·13
CLOCK
Conclusion
)
Careful study of CMOS characteristics show that
CMOS devices used in a system design can be used
for linear building blocks as well as digital blocks.
TlIFI602o-14
Staircase Generator
Utilization of these new devices will decrease
,package count and reduce supply requirements.
The circuit designer now can do both digital and'
Iinear designs with the same'type of device.
FIGURE 10. Variety of Circuit Ideas Using CMOS
Devices.
2·13
i
z 1.75 rnA
V'N = OV
IIDsl > 1.75 mA
V DS :> 5.0V
IVDsl
V'N
> 5.0V
405
~ l05
Vec = 10V
V'N
= 10V
V'N
IDS 2: 8.0 rnA
VDS :> 10V
=OV
IIDsl?8.0mA
IVDsl
145
045
.> 10V
~3:::==::::3~;;§:4
15
'-----'------'
450V
Note that each device data sheet guarantees these
points in the table of electrical characteristics.
25
lOV
15V
TL/F16021·6
FIGURE 4. Guaranteed Noise Margin Over Temperature
vs VCC
The output characteristics can be used to determine
the output voltage for any load condition. Figures
·1 and 2 show load lines for resistive loads to Vee
for sink currents and to GND for source currents.
The intersections of this load line with the drain
characteristic in question gives the output voltage.
For example at Vee ~ 5.0V. VOUT ~ 1.5V (typ)
to ground.
with a load of 50
Noise immunity is an important device characteristic. However. noise margin is of more use to the
designer because it very simply defines the amount
of noise a system can tolerate under any circumstances and still maintain the integrity of logic
levels.
on
Any noise specification to be complete must
define how measurements are to be made. Figure 5
indicates two extreme cases; driving all inputs
simultaneously and driving one input at a time.
Both conditions must be included because each
represents one worst case extreme.
These figures also show the guaranteed points for
driving two 54L174L standard loads. As can be
seen there is typically ample margin at Vee ~ 5.0V.
In the case where the 54C174C device is driving
another CMOS device the load line is coincident
with the IDS ~ 0 axis and the output will then
typically switch to either Vee or ground.
(
NOISE CHARACTERISTICS
VOUT
Definition of Terms
Noise Immunity: The noise immunity of a logic
element is that voltage which applied to the input
will cause the output to change its output state.
(AI
TLlFI6021-7
Noise Margin: The noise margin of a logic element'
is the difference between the guaranteed logical
"1" ("0") level output voltage and the guaranteed
logical "1" ("0") level input voltage.
The transfer characteristic of Figure 3 shows
typical noise immunity and guaranteed noise
margin for a 54C174C device operating at V ee ~
1OV. The typical noise immunity does not change
with voltage and is 45% of Vee.
·V OUl -" VOUTlllMIN. VOUHOIMAX
VN
We,
10
r.
~
lDY
- l~ C
;
ALLOWABLE NOISE VOLTAGE" 1.0V
IBI
·O·LEVUNOlst.',1A~GIN'
~
J
V,~ .. ,
'.0
.. AO -Vou"., ....
FIGURE 5_ Noisa Margin Test Circuits
',"LtVHNOISEMAAGIN·
V""''''M'' V'N"''''N
6.0
To guarantee a noise margin of 1.0V, all 54C174C
devices are tested under both conditions. It is
important to note that this guarantees that every
node within a system can have 1.0V of noise, in
logic "I" or logic "0" state, without malfunctioning. This could not be guaranteed without testing
for both conditions in Figure 5_
'.0
2.0
2.0
4.0
6.0
VIN
8.0
IV)
10
TlIFf6021·5
FIGURE 3. Tvpical Transf~r Characteristic
2-15
~
Z
1OV ,a ,small increase
in speed is gained by a disproporti~nate increase
iQ power. Conversely, for small decreases in power
below Vee = 5.0V large increases in propagation
delay result.
Another point to consider in the design of a
CMOS system is the affect of power supply
voltage on propagation delay. Figure 8 shows
propagation delay as a function of Vee and
propagation delay times power consumption vs
Vee for an MM74COO operating with 50 pF load
at f = 100 kHz.
Obviously it is optimum to use the lowest voltage
consistent with system speed requirements. However in general it can be seen from Figure 8 that
the best speed power performance will be obtained
in the Vee = 5.0V to Vee = 10V range.
.
Figures 9 and 10 give temperature variations in drain
characteristics for the N-channel and P-channel
devices operating at Vee = 5.0V and Vec = 10V
respectively. As can be seen from these curves the
output sink and source current decreases as temperature increases. The affect is almost linear and
can be closely approximated by a temperature
coefficient of -0.3% per degree centigrade.
x
TA =25 C
150
>
3DO
~,
t,=t,=2Dns'
"c
•
~
1 •
•
,
~
1
2
c
<
1
100
~
i
TEMPERATURE CHARACTERISTICS
.
E
2D0
~
5
~
100
50
~,
Since the tpd can be entirely attributed to rise
and fall time, the temperature dependance of
tpd is a function of the rate at which the output
load capacitance can be charged and discharged.
This in turn is a function of the sink/source
current which was shown above to vary as -0.3%
per degree centigrade. Consequently we can say
that tpd varies as -0.3% per degree centigrade.
Actual measurements of tpd with temperature
verifies this number.
~
c
c
=
J.
n
50
~.
15
10
~
Vee {V)
E!
TLIFI6021·"
FIGURE 8. Speed Power Product and Propagation Delay
vs VCC
Above Vee = 5.0V note the speed power product
curve approaches a straight line. However the
tpd curve starts to "flatten out." Going from
'0 r7.v-"~'~5~oV~---.-T,-.-_-55-C---'
Vee" 50V
4.0
ct
10
30
:i
,.E
2.0
~
~
.9
2.0
1A =+125 C
TA "+70 C
-3.0
T,I\ ,,+25 C
T.o. =0 C·
~o
10
1'1." -55 C
-5,0 ' -________________---J
1.0
2.0
3.0
4.0
5.0
Vounol (V)
1.0
TLlF16021-12
2.0
3.0
4.0
(A) Typical Output Drain Characteristic
IN-Channell
5.0
TLlF/6021·13
VOUT!1l (V)
(B) Typical Output Drain Characteristic
IP-Channell
FIGURE 9
-40
1A :+10 C
:i
12
TA
~
.9
:i
+125 C
so
§
B.o
..9 -12
4,0
-16
20
4.0
VOUT(OJ
(A)
=
60
(V)
80
20
10
TLlF/6021-14
(B~
Typical Output Drain Characteristic
IN-Channel)
FIGURE 10
2-18
4.0
60
V OUTI1I
lVl
80
10
TLIFI6021·15
Typical Output Drain Characteristic
IP-Channell
50
10
indicates that they are almost independent of
temperature. The transfer characteristic is not
dependent on temperature because although both
the N·channel and P·channel device characteristics
change with temperature these changes track each
other closely. The proof of this tracking is the
temperature independance of the transfer charac·
teristics. Noise margin and maximum/minimum
logic levels will then not be dependent on
temperature.
15
TLIF16021·16
As discussed previously power consumption is a
function of Cpo. C L • Vee. f and ILEAKAGE. All
of these terms are essentially constant with tem·
perature except ILEAKAGE' However. the leakage
current specified on each 54C/74C device applies
across the entire temperature range and therefore
represents a worst case limit.
FIGURE 11. Typical Gate Transfer Characteristics
The drain characteristics of Figure 9 and 10 show
considerable variation with temperature. Examina·
tion of the transfer characteristics of Figure 11
2·19
co
~ CMOS Oscillators
National Semiconductor
Application Note 118
Mike Watts .
October 1974
=
;:;
i
40
20
~
I I-- I-- - 1·-
80
>-
""
R1 R2
Req = R1 + R2
- l - I- .cc~
>-
g
....-
30
z
>=
"g
-- -
>-
.J...--t'"
CL
;:;
20
j
10
'"
15 pF
Vee
=:
3.0V
-
-
100
Vcc=S.%
z
0
I--
--
~
50
I
20
i
-Vee -lOY
......-r
~"'5V
.l'
25 50 75 100 125
-50 -25 0
25 50 75 100125
AMBIENT TEMPER,ATURE
AMBIENT TEMPERATURE ( C)
r Cl
20
50
100
150
Cl -LOAD CAPACITANCE (pF)
TLlF16022-4
TLIF16022·2
(a)
TA =25"C
CIRcUIT
1f-+-~EE AC TE5T-
>=
I---'
CL "50pF......... V
0
I---' Ccl~ILF :=1~ t:::
f- r- I I
I I
I I
-50 -25 0
40
150
]
I-- ~EE ;~~~ST CIRCUIT
(b)
FIGURE 2. Propagation Delay for 74C Gates
2·21
(e)
.:...
.....
CD
........
~r-------------------------------------------------------------------,
zca:
.i
Figure 5b, which obviously will not oscillate. This
illustrates that there is some value of Cl that will not
force the network to oscillate. The real difference
between this two gate oscillator and the three gate
oscillator is that the former must be forced to oscillate
by the capacitor while the three gate network will
always oscillate willingly and is simply slowed down by
the capacitor. The three gate network will always
oscillate, regardless of the value of Cl but the two gate
oscillator will not oscillate when Cl is small.
The following three special cases may be useful.
IfRl=R2=R
f~
RC
f~
If R2»> Rl
f~
If R2«< Rl
0.559
---
0.455
---
RC
0.722
RC
MM14C04
MM14CD4
Figure 4 illustrates the approximate output waveform
and the voltage V 1 at the charging node.
MM14CD4
MM14C04
1/2Vcc
lal
V"
v,
TL./FI6022-7
Ibl
TL/F/S022·B
FIGURE 5. Less Than Perfect Oscillator
1/2 Vee
GND
The only, advantage the two gate oscillator has over the
three gate oscillator is that it uses one less inverter.,
This mayor may not be a real concern, depending on the
gate count in each user's specific application. However,
the. next section offers a real minimum parts count
oscillator.
'
.
-tl2 Vee
Your
A SINGLE SCHMITT TRIGGER MAKES
AN OSCILLATOR
TL/F/6022-6
Figure' 6 illustrates an oscillator made from a single
Schmitt trigger. Since the MM74C14 is a hex Schmitt
trigger, this oscillator consumes only one sixth of a
package. The remaining 5 gates can be used either as
ordiryarY· inverters .like the MM74C04 or their Schmitt
trigger characteristics can be used to advantage in the
normal manner. Assuming these five inverters can be used
elsew,here in the system, Figure 6 must represent the
ultimate in low gate count "scillators.
FIGURE 4. Waveforms for Oscillator in Figure 3
Note that the voltage V2 will be clamped by input
. diodes when V 1 is greater than Vee or more negative
than ground. During this portion of the cycle current
will flow through R2. At all other times the only current
through R2 is a very minimal leakage term. Note also
that as soon as V 1 passes through threshold (about 50%
of supply) and the input to the last inverter begins to
change, V 1 will also change in a direction that reinforces
the switching action; i.e., providing positive feedback.
This further enhances the stability and predictability of
the network.
This oscillator is fairly insensitive' to power supply
variations due largely to the threshold tracking close to
50% of the supply voltage. Just how stable it is will be
determined by the frequency of oscillation; the'lower
the frequency the more stability and vice versa. This is
bef:ause propagation delay and the effect of threshold
shifts comprise a smaller portion of the overall period.
Stability will also be enhanced if Rl. is made large
.enough to swamp any variations in the CMOS o~tput
resistance.
FIGURE 6. Schmitt Trigger Os~illator
v.
Voltage 1 is depicted in Figure 7 and changes between
the two thresholds of the. Schmitt trigger. If these
thresholds were constant percentages of Vee over the
supply voltage range, the oscillator would be insensitive
to variations in Vee. However, this is not the case. The
thresholds of the Schmitt trigger vary enough to make
the oscillator exhibit a good deal of sensitivity to Vee.
TWO GATE OSCILLATOR WILL NOT
NECESSARILY OSCILLATE
Applications that do not require extreme stability or
that have access to well regulated supplies should not
be bothered by this sensitivity to Vee. Variations in
threshold can be expected to run as high as four or five
percent when Vee varies from 5V to 15V.
A popular oscillator is shown in Figure 5a. The only
undesirable feature of this oscillator is that it may not
oscillate. This is readily demonstrated by letting the value
of C go t9 zero. The network then degenerates. into
2·22
that can be obtained. Obviously, the fewer inverters
that are used, the higher the maximum possible frequency.
VOUT
GND
v" f----l----f--+--+--l--+_
v,"
CONCLUSIONS
v"
A large number of oscillator applications can be imple'
mented with the extremely simple, reliable, inexpensive
and versatile CMOS oscillators described in this note.
These oscillators consume very little power compared
to most other approaches. Each of the oscillators
requires less than one full package of CMOS inverters of
the MM74C04 variety. Frequently such an oscillator can
be built using leftover gates of the MM74COO, MM74C02,
MM 74Cl 0 variety. Stability superior to that easily
attainable with TTL oscillators is readily attained,
particularly at lower frequencies. These oscillators are
so versatile, easy to build, and inexpensive that they
c.hould find their way into many diverse designs.
GNDr-~---t--+---rTLlF16022·10
FIGURE 7. Waveforms for Schmitt Trigger Oscillator
Figure 6
i~
A CMOS Crystal Oscillator
Figure 8 illustrates a crystal oscillator that uses only
one CMOS inverter as the active element. Any odd
number of inverters may be used, but the total propaga·
tion delay through the ring limits the highest frequency
VOUT
TLlFI6022·"
FIG U R E 8. Crystal Oscillator
2·23
Using the CMOS Dual
Monostable Multivibrator
National Semiconductor
Application Note 138
Thomas P. Redfern
May 1975
INTRODUCTION
The gating, G, on the comparator is designed such that
the comparator output is high when the one-shot is in
its stable state. With the CLR input high the clear input
to FF is disabled allowing the flip-flop to respond to the
A or B input. A negative transition on A or a positive
transition on B sets 0 to a high state. This in tur~ gates
Nl OFF, and N2 and the comparator ON.
The MM54C221/MM74C221 is a dual CMOS monostable
multivibrator. Each one-shot has three inputs (A, Band
CLR) and two outputs (0 and 0). The output pulse
width is set by an external RC network_
The A and B inputs trigger an output pulse on a negative
or positive input transition respectively_ The CLR input
when low resets the one-shot. Once triggered the A and B
inputs have no ,further control on the output.
Gating N2 ON establishes a reference of 0.63 Vee on
the comparator's positive input. Since the voltage on
CEXT can neit change instantaneously Vl = OV at this
time. The comparator then will maintain its one level on
the output. Gating Nl OFF allows C EXT to start charging
through R ExT toward Vee exponentially.
THEORY OF OPERATION
Figure 1 shows that in its stable state, the. one-shot
clamps C EXT to ground by turning N 1 ON and holds
the positive comparator input at Vee by turning N2
OF F. The prefix N is used to denote N-channel transistors.
Assuming a perfect comparator (zero offset and infinite
gain) when the voltage on C EXT , Vl, equals 0.63 Vee.
the comparator output \'ViII go from a high state to a
low state resetting 0 to a low state. Figure 2 is a timing
diagram summarizing this sequence of events.
The signal, G, gating N2 OFF also gates the comparator
OFF thereby keeping the internal power dissipation to
an absolute minimum. The only power dissipation when
in the stable state is that gen'erated by the current
through R EXT ' The bulk of this dissipation is in R EXT
since the voltage drop across Nl is very small for normal
ranges of R EXT '
This diagram is idealized by assuming zero rise and fall
times and zero propagation delay but it shows the basic
operation of the one-shot .. Also shown is the effect of
taking the CLR input low, Whenever CLR goes low FF
To trigger the one-shot the CLR input must be high.
15,7
.n
Vee 0
"
R'
GNDo---t---~~~r----o~--~
N21t-----i
OlR
CLEAR
o-------------------+--------J
J,11
',9
B 2,10
o--------------------+----~
FF
FIGUR"E 1. Monostable Multivibrator Logic Diagram
2-24
Tl.IFI60231
i
•
ClR
_ _ _ _ _ _ i'- __ J•
H
l _____ ~
~
I--T"
R EXT
CEXT--I
I
COMPARATOR
OUTPUT
I
I
l
-------.
TLlF16023·2
FIGURE 2. One-Shot Timing Diagram
is reset independent of all oth~r inputs. Figure 2 also
shows that once triggered, the output is independent of
any transitions on B (or A) until the cycle is complete.
because the leakage and ON impedance of transistor N1
have a minimal effect on accuracy with this value of
resistance.
The output pulse width is determined by the following
equation:
Two values of C EXT were chosen, 1000 pF and 0.1I1F.
These values give pulse widths of 10l1s and 1000l1s with
R EXT = 10 kil.
V1 = Vcc (1 - e'-T/R
EXT CEXT)
= 0.63 Vcc
Figures 3 and 4 show the resulting distributions of pulse
widths at 25°C for various power supply voltages.
(1)
Because propagation delays, at the same power supply
voltage, are the same independent of pulse width, the
shorter the pulse width the more the accuracy is
Solving for t gives:,
T = R EXT C EXT In (1/0.37) = REXT C EXT
(2)
A word of caution should be given in regards to the
U
ground connection of the external capacitor (C EXT )'
It should always be connected as shown in Figure 1 to
pin 14 or 6 and never to pin 8. This is important
because of the parasitic resistor R*. Because of th" large
discharge current through R', if the capacitor is can·
nected to pin 8, a four layer diode action can result
causing the circuit to latch and possibly damage itself.
"'"uu
0
:5
u
"
:::"
O%POIll!PUISCWldth:
1.0
At Vee'" 5V,
At Vee'" IOV,
Tw '" 10 6.. !
Tw"' 10.s
08
AtV cc =1SV,
Tw=9.8 s
0.6
~
H+-H-+-llttftf-+-tvcc :: 5V
H+-H-+-fttH-+.ft Vee" 1OV
H+-H-+-fttH:-:f--l Vee = 15V
0.2
~
'5
2 0 2
90'1" of llllltS
95% of umts
9B%oful1Its
5
OUTPUT PULSE WrOTH (Tw . %1
There are many factors which influence the accUi acy of
the one·shot. The most important are:
Percentageofumtswlthll1 4%.
At Vee = 5V.
At Vee" IOV,
At Vee = 15V.
D.'
">=
ACCURACY
a.
b.
c.
d.
e.
f.
g.
h.
i.
TA '" 25 C
RExT '" 10k
CE:XT'" 1000 [IF
z
w
TLlFf60Z3·3
FIGURE 3. Typical Pulse Width Distribution for 10,us Pulse.
Comparator input offset
Comparator gain
Comparator time delay
Voltage divider R1, R2
Delays in logic elements
ON impedance of N 1 and N2
Leakage of N 1
Leakage of C EXT
Magnitude of R EXT and C EXT
u
z
"'"
O%pulsewrdth.
u
u
0
:5
w
u
0.8
~
0.6
~
">=
g
The characteristics of C EXT and R EXT are, of course,
not determined by the characteristics of the one·shot.
In order to establish the accuracy of the one·shot, devices
were tested using an external resistance of 10 kS1 and
various capacitors. A resistance of 10 kil was chosen
At Vee" 5V.
At Vee" lOV,
At Vee =. 15V.
1.0
04
Tw "- H120'ls
Tw" 100011$
Tw" 982,IS
Percenta!leDfullrbwlthlll 4%.
f-t+H-+-HH--l-+-:',v cc ,. 5V
,..2Vcc =10V
0.2 f-t+-H-+~H~.~tcc "15V
S 2 0 2
At Vee" 5V,
At Vee" lOY,
At Vee "15V,
95% of
97% of
UIII\S
Ullits
98%ofullLlS
5
OUTPUT PULSE WIDTH (T w . %)
TLlF16023·4
FIGURE 4. Typical Pulse Width Distribution for 1000,0.5 Pulse.
2-25
affected by propagation delay. Figures 3 and 4 clearly
show 'this effect. As pointed out in application note
AN·90, 54C/74C Family Characteristics, propagation'
delay is a function of Vee. Figure 3, (Pulse Width =
10j./s) shows much greater variation with Vee than
Figure 4 (Pulse Width = 1000j./s). This same information
\ is shown in Figures 5 and 6 in a different format. In
Figure 1 shows typical power dissipation vs Vee
operating both sides of the one-shot at 50% duty cycle.
Also shown in the same figure is typical minimum pulse
width vs Vee. The minimum pulse width is a strong
function of internal propagation delays. It is obvious
from these two curves that increasing Vee beyond 10V
will not appreciably improve inaccuracy due to propagation delay but will greatly increase power dissipation.
Accuracy is also a function of temperature. To determine
the magn itude of its effects the one-shot was tested at
temperature with the external resistance and capacitance
maintained at 25°C. The resulting variation is shown in
Figures 8 and 9.
~
"
""
'"0
0
~
iii
~
-2
-4
5V
-6
f-++H++-PULSE WIDTH -lOp,
15
10
TLlF16023·5
Vee (VI
TOV
FIGURE 5. Typical Percentage Deviation from
Vee
= 10V Value vs Vee IPW =101'5).
15V
-2~m~~m~
~
"
0
-55
~
~
25
m'
TLlF16023-8
TA - AMBIENT TEMPERATURE I C)
'"
b
FIGURE S. Typical Pulse Width Error vs
Temperature {PW = 101'51.
iii
-2
~
-4
-6
15
10
TUF1602~
Vee (VI
FIGURE 6. Typical Percentage Deviation from
Vee = 10V Value vs Vee (PW = 10001'~1.
these figures the percent deviation from the average
pulse width at 10V Vee is shown vs Vee,. In addition
to the average value the 10% and 90% points are shown.
These percentage points refer to the statistical distribution of pulse width error. As an example, at Vee = 10V
for 10j./s pulse width, 90% of the devices have errors of
less than +1.7% and 10% have errors less than -2.1%.
In other words, 80% have errors between +1.7% and
-2.1%.
-55
1000
250
I-f- TA -25 C
~o~
3::
w"
800
I\.
":rE~. 400
r-'
5~
~
200
0
,/
_r--5
V- I-
.....
~ '~
x
200
I
I\,
~ ~ 600
~~
"
225
./
Up to this .point the external timing resistor, REXT, has
been held fixed at 10 kn. In actual applications other
values may be necessary to achieve the desired pulse
width. The question then arises as to what effect this
will have on accuracy .
10
Vee (V)
;j~
125
~m
25
15
to
m ....
:oJ>
,.~,
"'''
J>J>
75
'"
fll~
0 ....
150
50
TlIF16023-9
0'"
o~
115
100
125
FIGURE 9_ Typicai Pulse Width Error vs
T emp.rature {PW = 10001'51.
The minimum error can be obtained by operating at
the maximum Vee- A price must be paid for this and
this price is, of course, increased power dissipation.
....<
:g
'"
25
TA - AMBIENT TEMPERATURE ( C)
z"
r - -.....- -.....- - >ttl
.... '"
§!:!
-11.
o~
:i~
<",
1
~;;
,,2
~!
FIGURE 10
-'"
i~
TLlF/6023·10
As REXT becomes larger and larger the leakage current
on transistor Nl' becomes an ever increasing problem.
The equivalent circuit for this leakage is shown in
;!
FIGURE 7. Typical Minimum Pulse Width and
Power Dissipation vs Vee.
TlIF/6023·7
Figure 10.
2-26
We have just defined the limitation on the maximum size
of REXT . There is a corresponding limit on the mini·
mum size that REXT can assume. This is brought about
because of the finite ON impedance of NT. As R EXT is
made smaller and smaller the amount of voltage across
Nl becomes significant. The voltage across Nl is:
vIti is given by:
As before, when vIti
Solving for tL gives:
~
0.63 Vee, the output will reset.
(4)
(3)
The output pulse width is defined by:
v (to) ~ (Vee - V N1 ) (1 - e-tOIREXT eEXT)
Using T as defined in Equation 2 the pulse width error is:
+ V N1
~
PW Error
tL -T
x 100%
T
~
0.63 Vee
Solving for to gives:
to
Substituting Equations 2 and 3 gives:
~
R EXT C EXT Qn (Vee - VN1)
0.37 Vee
Pulse Width Error is then:
PW Error
~
.
J
.
x 100%
. Substituting Equations 2 and 4 gives:
PW Error is plotted in Figure 11 for Vee ~ 5, 10 and
15V. As expected, decreasing Vee causes PW Error to
increase with fixed IL' Note that the leakage current,
although here assumed to flow through N 1, is general
and cO\lld also be interpreted as leakage through C EXT '
See MM54C221 /MM74C221 data sheet for leakage limits.
100 .
~
({EXT
CEXT ~n(1/0.371
This function is plotted in Figure 12 for rON' of 50n,
25n and 16.7n. These are the typical values of rON for
a Vee of 5V, 10V and 15V respectively.
.
0
<
1.0
As an example, assume that the pulse width error due to
rON must be less than 0.5% operating at Vee ~ 5V. The
typical value of rON for V ee ~ 5V is 50n. Referring to
'L
,..
~
c
'"c
'"'"
01
if
~
DO'
0.'
IUAIfAGE X ReXT (V)
,..c
'0
=>
c
TL.IFI6023-11
'"c
'"'"
,..'"c
FIGURE 11. Percentage Pulse Width Error Due to Leakage.
1.0
0.1
!<
To demonstrate the usefulness of Figure 11 an example
will be most helpful. Let us assume that Nl has a
leakage of 250 x 10--9 amps, C EXT has leakage of
150 x 10--9 amps, output pulse width ~ 0.1 seconds and
Vee ~ 5V. What REXT C EXT should be used to
guarantee an error due to leakage of less than 5%.
~
=>
~
'k
TlIF/6023·12
Due to Finite rON of Transistor N1
< 350
YS
ReXT.
the 50n curve in Figure 12, REXT must be greater than
10 kn to 'maintain this accuracy. At Vee'" 10V, REXT
must be greater than 5 kn as can be seen from the 25n
curve in Figure 12.
Then:
< 0.14/(250 + 150) x
'M
'OOk
FIGURE 12. Percentage Pulse Width Error
From Figure 11 we see that to meet these conditions
RexT IL < 0.14V.
.
R EXT
'Ok
10-9
Although clearly shown on the MM54C221/MM74C221
data sheet, it is worthwhile, for the sake of clarity, to
point out that the parasitic capacitance between pins
7 (15) and 6 (14) is typically 15 pF. This capacitor is in
parallel with CExTand must be taken intb account when
accuracy is critical.
kn
Choosing standard component values of 250 kn and
O.00411F would satisfy the above conditions.
2-27
~.-------------------------~---------------------------------------------,
C")
.....
Z
TYPICAL APPLICATIONS
-+-vo
>-4~""---I B '
A
ov
FREQUENCY TO DC CONVERTER
VaDe = Vee' AI • Cl . f
LEVEL DETECTOR
Vo = 0 FOR f
Vo = 1 FOR f
2-28
R4f[(R3 + R4) (AI, Cl1J
R4/((R3 + R411Rl • till
TlIF16023-15
TYPICAL APPLICATIONS (Continued)
Linea, VCO
AS
A4
R6
Voe
~
'MAl(
I/(R!' 1:1 +2· R5· 1:21
AI . Cl·'· Vee
TL/F16023·16
GND
Analog Multiplier/Divider
VI
V"
01'
SIOk
16k
lOOk
100
lN914
V"
lN914
D75V cc
r----lOOk
I
OOIF
·ON lM324
V~ Vee
V- oGNO
V,,-...- - - - -......
TLIF16023·17
2·29
CMOS Schmitt Trigger
-a Uniquely Versatile
Design Component
National Semiconductor
Application Note 140
Gerald Buurma
June 1975
INTRODUCTION
ANALYZING THE CMOS SCHMITT
The Schmitt trigger has found many applications in
numerous circuits, both analog and digital. The versa. tility of a TTL Schmitt is hampered by its narrow
supply range, limited interface capability, low input
impedance and unbalanced output characteristics. The
Schmitt trigger could be built from discrete devices to
satisfy a particular parameter, but this is a careful and
sometimes time-consuming design.
The input of the Schmitt trigger goes through a standard
input protection and. is tied to the gates of four stacked
devices. The upper two are P-channel and the lower two
are N·channel. Transistors P3 and N3 are operating in the
source follower mode and introduce hysteresis' by
feeding back the output voltage, out', to two different
points in the stack.
The CMOS Schmitt trigger, which comes six to a
package, uses CMOS characteristics to optimize design
and advan,ce into areas where TTL could not go. These
areas include: interfacing with op amps and transmission
lines, which operate from large split supplies, logic level
conversion, linear operation, and special designs relying
on a ~MOS characteristic. The CMOS Schmitt trigger
has the following advantages:
When the input is at OV, transistors Pl and P2 are ON,
and Nl, N2 and P3 are OFF. Since out' is high, N3 is
ON and acting as a source follower, the drain Ilf Nl,
which is the source of N2, is at Vee-V TH . If the input
voltage 'is ramped up to one threshold above ground
transistor Nl begins to turn ON, Nl and N3 both being
ON form a voltage divider network biasing the source of
N2 at roughly half the supply. When the input is a
threshold above 1/2 Vee, N2 begins to turn ON and
regenerative switching is about to take over. Any more
voltage on the input causes out' to drop. When out' drops,
the source of N3 follows its gate, which is out', the
influence of N3 in the voltage divider with Nl rapidly
diminishes, bringing out' down further yet. Meanwhile
P3 has started to turn ON, its gate being brought low by
the rapidly dropping out'. P3 turning ON brings the
source of P2 low and turns P2 OFF. With P2 OFF, out'
crashes down. The snapping action is due to greater than
unity loop gain through the stack caused by positive
feedback through the source follower transistors. When
the input is brought low again an identical process occurs
in the upper portion of the stack and the snapping
action takes . place when the lower threshold is reached.
• High impedance input (10'2n typical)
• Balanced input and output characteristic;
• Thresholds are typically symmetrical to 1/2 Vee.
• Outputs sour~e and sink equal currents
• Outputs drive to supply rails
• Positive al'ld negative-going thresholds show 10"Y
variation with respect to temperature
• Wide supply range (3-15V), split supplies possible
• Low power consumption, even during transitions
• High noise immunity, 0.70 Vee typical
Applications demonstrating how each of these cha'racteristics can become a design advantage will be given
later in the application note.
J
I"
OUT'
INPUT
OUTPUT
I .2
y;;~
I .,
v"
1FIGURE 1. CMOS Schmitt Trigger,
2-30
TLlF/6024·1
Out' is fed into the inverter formed by P4 and N4;
another inverter built with very small devices, P5 and
N5, forms a latch which stabilizes out'. The output is
an inverting buffer capable of sinking 360llA or two
LPTTL loads.
.
typically 3.6V of threshold difference, enough hysteresis
to overcome almost any spurious signal on the input.
A comparator is often used to recover information sent
down an unbalanced transmission line. The threshold of
the comparator is placed at one half the signal amplitude
(See Figure 4b). This is doen to prevent slicing level
distortion. If a 41ls wide signal is sent down a transmission
line a 41ls wide signal should be received or signal distor·
tion occurs. If the comparator has a threshold above half
the signal amplitude, then positive pulses sent are shorter
and negative pulses are lengthened (See Figure 4c). This
is called slicing level distortion. The Schmitt trigger does
have a positive offset, VT+, but it also has a negative
offset VT -. In CMOS these offsets are approximately
symmetrical to half the signal level so a 4ps wide pulse
sent is also recovered (see Figure 4d). The recovered
pulse is delayed in time but the length is not changed,
so noise immunity is achieved and signal distortion is not
introduced because of threshold offsets.
The typical transfer characteristics are shown in Figure
2; the guaranteed trip point range is shown in Figure 3.
WHAT HYSTERESIS CAN DO FOR YOU
Hysteresis is the difference in response due to the direc·
tion of input change. A noisy signal that traverses the
threshold of a comparator can cause multiple transitions
at the output, if the response time of the comparator is
less than the time between spurious effects. A Schmitt
trigger has two thresholds: any spurious effects must be
greater than the threshold difference to cause multiple
transitions. With a CMOS Schmitt at Vee = 10V there is
20
15
12.9
~
w
Vee:: 15V
15
'"'"
~
:>
V,_
V,.
~
10
w
'"'"
:;
lQ
=
~ 4.33.0
~
5
:>
=
10
15
2.0
0.7
0
20
INPUT VOL TAGE IVI
10
FIGURE 2. Typical CMOS Transfer Characteri.stics
for Three Different Supply Voltages.
FIGURE 3. Guaranteed Trip Point Range.
a) RecervedsrgnalfrorntransrntSSlon
hnewllh thresholds at dlllerent
amplitudes.
bl Recovered SI!lnal horncornp.1rafor
With thmhold VTH h~s multiple
tranSitIOns
cl Recuveredsignal hom comparator
wtth posrllve offset on threshold, VT.,
posltlvepubeshorten,l1egatlve I'ulse
lengthen.
d) Recovered Signal With CMOS Schmitt
tngger, VT• andV T .Restorestrll!
waveform
Recovered sIgnal from Schmitt IS same
width n comparator with thruhold at
VTH,andlsonlydelayedmtlme.
o
1
2
J
4
15
Vee !V)
TLiFIS02402
5
TIME
6
1
B 910
(jJs)
FIGURE 4 .. CMOS Schmitt Trigger Ignores Noise
2·31
TLlFI6024.4
TLlF16024·3
l>
Z
.:...
8
~I
Vee
GNo=~-A*ftV:' ~C~~"
~
~----'J--4j-l V,
I
vee-n n
.
BlASPOlNT~-O"-lJV"
R
TLlFI60245
a) Capacitor impedance at lowest operating frequency should be much less than R IIR
+
1/2R.
VJlflj
.-.,-
V"
~
=
.
G:: -- - - -- - vs,>
TL/F/o024-6
b) By using split supply (±1.5 to ±7.5) direct interface is achieved.
FIGURE 5, Sine to Square Wave Converter with Symmetrical level Detection.
cz
+
RZ
01
lN914
relpOllsetlllleotvoltmetN
_
TlIF16024·7
FIGURE 6. Diode Dump Tach Accepts any Input Waveform.
APPLICATIONS OF THE CMOS SCHMITT
In Figure 4, we sec a frequency to voltage converter that
accepts many waveforms with no change in output
voltage, Although the energy in the waveforms are quite
different, it is only the frequency that determines the
output voltage, Since the output of the CMOS Schmitt
pulls completely to the supply rails, a constant voltage
swing across capacitor C1 causes a current to flow
through the capacitor, dependent only on frequency,
On positive output swings, the current is dumped to
ground through D1, On negative output swings, current
is pulled from the inverting op amp node through 02 and
transformed into an average voltage by R2 and C2,
,Most of the following applications use a CMOS Schmitt
charact"eristic to either simplify design or increase per-
formance. Some of the applications could not be done
at all with another logic family,
The circuit in Figure 5a is the familiar sine to square
wave converter. Because of input symmetry the Schmitt
trigger is easily biased to achieve a 50% duty cycle. The
high input impedance simplifies the selection of the bias,
ing resistors and coupling capacitor. Since CMOS has a
wide supply range the Schmitt trigger could be powered
from split supplies (see Figure 5b). This biases the mean
threshold value around zero and makes direct coupling
from an op amp output possible.
Since the CMOS Schmitt pulls completely to the supply
rails the voltage change across the capacitor is just the
supply Voltage.
2,32
Schmitt triggers are often used to generate fast transitions when a slowly varying function exceeds a predetermined level. In Figure 7, we see a typical circuit, a
, light activated switch, The high impedance input of the
CMOS Schmitt trigger makes biasing very easy. Most
photo cells are several kQ brightly illuminated and a
couple MQ dark. Since CMOS has a 10'2Q typical input
impedance. no effects are felt on the input when the
output changes. The selection of the biasing resistor is
just the solution of a voltage divider equation.
trigger, six low power oscillators can be built. The square
wave output is approximately 50% duty cycle because ot'
the balanced input and output characteristics '~f CMOS.
The output frequency equation assumes that t, ; t2
»
tpdO
+ t pd , '
We earlier saw how the CMOS Schmitt increased noise
immunity on an unbalanced transmission line_ Figure 9
shows an application for a balanced or differential
transmission line. The circuit in Figure 7a is CMOS
EXCLUSIVE OR, the MM74C86, which could also be
built from inverters, and NAND gates. If. unbalanced
information is generated on the line by signal crosstalk
or external noise sources. it is recognized as an error.
,A CMOS application note wouldn't be complete without
a low power application. Figure 8 shows a simple RC
oscillator. With only six R's and C's and one Hex CMOS
'---~~-+ "OR" CONFIGURATION
"AND" CONFIGURATION
TLIFI6024·B
FIGURE 7. Light Activated Switch couldn't be Simpler. The Input Voltage Rises as Light Intensity Increases, when VT+ is
Reached, the Output will go Low and Remain Low until the Intensity is Reduced Significantly.
v"
, ~~
,.
V
VT_
'"
,.
,
II1PUT
WAVEFORMS
. . . . . . . . . . . . ....
"
OUTPUT
WAVEFORMS
TLlF16024.9
FIGURE 8. Simplest RC Oscillator? Six R's and C's make the CMOS Schmitt into Six Low Power Oscillators. Balanced
Input and Output Characteristics give the Output Frequency a Typically 50% Duty Cycle.
Truth Table
lJJMM14C14
A~
A B
1/4MM74C86
B
\l..
o
In
1 1 NC
NC " No ChangE>
either dlrec tlon.
TLIF/6024·10
0
1 0
AB+AB ='Error
Enor IS detettedwhen tlanSmlsSlOn hne IS unbalanced
0 NC
,
D--oERROR
Transrnlueddataappearsat F as longas.transmlsslon Ime IS balanced,
unbalanceddatalslgnoredanderrOTlsdetecte,dbyaboveclfcuit.
b) Differential Line Receiver.
a) Differential Error Detector.
TL.IFI6024-11
FIGURE 9. Increase Noise Immunity by using the CMOS Schmitt Trigger to Demodulate a Balanced Transmission line,
2-33
~
»
Z
.:.a.
8
...
i
Z
DD
MM14C914
INPUT
PROTECTION
02
.".
CMOS
INPUT
>DD
TLIF/6024·12
.".
al
TL/F/6024·13
bl
FIGURE 10. Input Protection Diodes, in a) Normally Limit the Input Voltage Swing to p.3V above Vee and O.3V
below Ground.
In bJ 02 or 01 is Reverse Biased Allowing Input Swings of 25V above Ground or 25V below
V"~/
v,'"
V
Vee.
fO=~
(V y >
-
vT
)
Rc C
V,.o--,\M,.......,t--i
dfo
d~
1/6MM74C04
0_ VIN _1/2Vcc
- 1
= (VT' -VT
IRce :,\
Ro
FIGURE 11, Linear CMOS (Voltage Controll~d Oscillatorl
2·34
TL/F/6024·14
THE SCHMITT SOLUTION
The pulses from the VCO output are quite narrow
because the reset time is much smaller than the integra·
tion time. Pulse stretching comes quite naturally to a
Schmitt trigger. A one·shot or pulse stretcher made with
an inverter and Schmitt trigger is shown in Figure 12.
A positive pulse coming into the inverter causes its
output to go low, dischargi ng the capacitor through the
diode D1. The capacitor is rapidly discharged, so the
Schmitt input is brought low and the output goes
positive. Check the size of the capacitor to make sure
that inverter can fully discharge the capacitor in the
input pulse time, or
C!:lV
ISINK INVERTER> _ _
!:IT
+
The Schmitt trigger, built from discrete parts, is a careful
and sometimes time·consuming design. When introduced
in integrated TTL, a few years ago, many circuit designers
had. renewed interest because it was a building block
part. The input characteristics of TTL often make biasing
of the trigger input difficult. The outputs don't source
as much as they sink, so multivibrators don't have 50%
duty cycle, and a limited supply range hampers inter·
facing with non 5V parts.
The CMOS Schmitt has a very high input impedance with
thresholds approximately symmetrical to one half the
supply. A high voltage input is available. The outputs
sink and source equal currents and pull directly to the
supply rails.
!:lV
R
where,!:l V = Vee for CMOS, and !:l T is the input pulse
width.
A wide threshold range, wide supply range, high noise
immunity, low power consumption, and low board
space make the CMOS Schmitt a uniq'uely versatile
part.
For very narrow pulses, under 100, ns, the capacitor can
be omitted and large resistor will charge up the CMOS
gate capacitance just like a capacitor.
a
Use the Schmitt trigger for signal conditioning, restora'
tion of levels, discriminating noisy signals, level detecting
with hysteresis, level conversion between logic families,
and many other useful functions.
When the inverter input returns to zero, the blocking
diode prevents the inverter from charging the capacitor
and the resistor must cnarge it from its supply. When
the input voltage of the Schmitt reaches VT+, the
Schmitt output will go low sometime after the input
pulse has gone low.
The CMOS Schmitt is one step closer to making design'
limited only by.,the imagination of the designer.
1/6MM14C14 .
1/&MM741:04
JL
t-- 0-----1
--j
1
01
....""----1"-
~>--+
--,
To = 11111 +T
J
T=RCl:n(~C-VBE)
Vee - V H
BESURETHAT
'SINKIIIIVERTER>
CVee
1
t~
R
FIGURE 12. Pulse Stretcher. A CMOS Inverter Discharges a Capacitor,
a Blocking Diode allows Charging through R only. Schmitt Trigger
Output goes Low after the RC Delay.
2·35
TlIF/6024-15
National Semiconductor
Application Note 143
November 1975
Using National Clock
Integrated Circuits in Timer
Applications-
INTRODUCTION
The following is a description of a technique which
-allows the use of the National MM5309; MM53ll,
MM5312 and MM5315 clock integrated circuits as
timers in industrial and ,consumer applications. What
will be presented is the basic technique along with some
simple circuitry and applications.
An easier method is to use one or more deml,lltiplexed
,BCD lines as control waveforms whose edges determine
timer data. In Figure 1 we examine the l·bit of the BCD
data of the units second time.
From this waveform we observe a one second wide pulse
every two seconds. If we look at the 4-bit of the 10,
minutes digit we find a pulse which is 20 minutes wide
and occurs once each hour.
BASIC TECHNIQUE
When first approaching the problem of using clock chips
for timers, the most obvious technique is to attempt to
compare the display data with' preset BCD numbers.
Because of the multiplexing and number of data bits
this technique, while possible, is unwieldy and requires a
large number of components.
Figure 3, is a chart showing the various pulses and their
widths for all digits and the useful BCD lines.
UNIT SECOND
DIGIT TIME
BCD 1
TLID/7397-1
FIGURE 1. 1 Second Pulse Every 2 Seconds
10MINlTE DIGIT
TIME
BCD 1
I
U
1---'0 MI.--\-20MI.-l
L
TUD/7397-2
FIGURE 2.20 Minute Pulse Every Hour
2-36
BCD
PULSE RATE
PULSE WIDTH
BCD
1 Sec Digit
1
2
4
8
8
1 every 2 sec
1 sec'
1 every 10 sec
1 every 10 sec
4 sec
2 sec
1
2
4
8
1 every 2 min
1 min'
1 every 10min
1 every 10min
4 min
2 min
1 every 2 hrs
1 hr'
1 every 12 hrs
1 every 12 hrs
4 hrs
4 hrs
8
1 every 12 hrs
1 every 12 hrs
1 every 12 hrs
10 sec'
20 sec
20 sec
10 Min Digit
1
2
4
1 every 20 min
1 every hr
1 every hr
10 min
20 min
20 min
.
8
Units Hrs Digit (24 Hr Model
1
2
4
1 every 2 11 rs
1 hr'
8
10 Hrs Digit (12 Hr Model
1
2
4
1 every 20 sec
1 every min
1 every min
8
Units Hrs Digit (12 Hr Model
1
2
4
Pl)LSE WIDTH
10 Sec Digit
1 Min Digit
1
2
4
PULSE RATE
10 Hrs Digit (24 Hr Model
1
2
9 hrs
9 hrs
9 hrs
1 every 24 h rs
1 every 24 h rs
10 hrs
4 hrs
*Square waves
TUD17397-3
FIGURE 3
SIMPLE DEMUL TlPLEXING
MORE COMPLEX APPLICATIONS
In the simple case where, for example, a four hour wide
pulse each day is desired, perhaps to turn on lights in the
evening, a simple demultiplexing scheme using one diode
is shown in Figure 4. When power is applied, the internal
multiplex circuitry will strobe each digit until the digit
with the diode connected is accessed. This digit will
sink the multiplex charging current and stop the multiplex scanning. Thus, the BCD outputs now present the
data from the selected digit. The waveforms as previously
discussed are presented at the BCD lines. Note that these
pulses are negative true for all BCD outputs.
Where it is desired to maintain the display, or in more
complex timing of the "10 seconds every two hours"
variety, external demultiplexing shown in Figure 6 can
be used. In this figure the BCD lines are demultiplex~d
with MM74C74 flip-flops. Examining the waveforms of
these circuits we see two edges which allow the 10
second each two hours timing. These are differentiated
by the NAND and INVERTERS and the first edge sets
and the second resets the S-R flip-flop. The output of the
flip-flop is ten seconds wide every two hours. Byexamining the edges of the Figure 3 entries any combination
of timings can be obtained with the circuit of Figure 6.
An advantage of this type of. timer over mechanical
types is the elimination of line power drop outs. The
circuit shown in Figure 5 will maintain timing to within
a few percent during periods of power line failure, but
automatically' return to the 60 Hz line for timing as soon
as power is restored.
LOW FREQUENCY WAVEFORM GENERATION
The asterisked BCD lines in Figure 3 are those waveforms which are symmetric. By the use of the simple
diode demultiplexing scheme previously discussed we
2-37
-
~r-------------------------~----------------------------------------------------------~
o:t
Z
x
'y
1800
<[
:;;
~
VOUT.
~
<[
:;;
~
600 MM74C908 A"IoIo:::+--P-t++-i
-(0 JA = 11 D° CIW) ~rtt--f'.....:t-"H--j
200 H-+++--t--H-+-H-t--H-t""!o~
OL-J-LJ..L--'-"-,-L-'-'-'-"-,-'---'---'-""
0 10 3D 50 70 90 110 130 150
TA - AMBIENT TEMPERATURE (OC)
FIGURE 1
TLIFf6025·'
FIGURE 2. Maximum Power DiSSipation vs
Ambient Temperature
•
TLlF16025-2
2-40
A general application circuit for
MM74C918 is as shown in Figure 3.
the
»
z
OESIGN TECHNIQUE .
MM74C908,
In a typical design, RL must be chosen to satisfy the
load requirement (e.g., a minimum current to turn
on a relay) and at the same time, the power consumed
in the driver package must be kept below its maximum
power handling capability.
Vee
r
I
I
I
I
L
To minimize the design effort, a graphical technique is
developed, which combines all the parameters in one
plot, which can be used efficiently to obtain an optimal
design.
VOUTA
VOUTB
IOUTA
lOUTS
Assume T A = 25°C and that both sections of the
MM74C908 in Figure 3 are operating under identical
conditions. The maximum allowable package dissipation
is:
Po = 2 (Vee - VOUT) x lOUT
TlIF16025-3
FIGURE 3
(6)
1
=-
For both sections A and 8;
VCC -VL
lOUT = - - ' - - RON + RL
(150 - TA) = 1.14W
110
(2)
where Tj = 150°C, IIjA = 110o e/W are used in (1) per
the data sheet.
The device "ON" resistance, RON, is a function of
junction temperature, Tj. The worst·case RON as a
function of Tj is given in (3).
RON = 9 [1 + 0.008 (Tj - 25)]
Thus, the maximum power allowed in each section is:
(3)
Po = (Vee - VOUT) x lOUT = 0.57W
The total power dissipation in the device also consists of
normal CMOS power terms (due to leakage current,
internal capacitance, switching etc.) which are insignifi·
cant compared to the power dissipated at the output
stages. Thus, the output power term defines the allowable
Iimits of operation and is given by:
Po = POA + POB
=
A constant power curve Po = 0.57W can then be plotted
as shown in Figure 4. The circuit must operate below
this curve. Any voltage·current combination beyond it
(in the shaded region) will not guarantee Tj to be lower
than 150o e.
(4)
120UTA • RON + 120UTB • RON
For any given R L, a load line (7) can be
on Figure 4.
Given RLA and RLB, (1), (2), (3), (4) can be used to
calculate PO, Tj, etc. through iteration.
For example, let VL = OV, VCC = 10V, RLA
RLB = 50n, TA = 25°C, IIjA = 110°C/W.
sup~rimposed
1
,
1
lOUT = (Vec - VU- (Vce - VOUT)
RL
RL
= 100n,
(7)
The slope of this load line is -1/RL and It Intersects
with the vertical and horizontal axes at 1/R L (V cc VL) and VCC - VL respectively.
Assume:
RON = 12.28n
By (2):
IOUTA =
Given VCC and VL, a minimum RL can be obtained by
drawing the load line tangent to the constant power
curve. In Figure 4, at VCC - VL = 5V the line inter·
sects lOUT axis at lOUT = 450 rnA. Thus, RL(MIN) =
5V /450 mA = 11.1n. Any R L value below this will
move the intersecting point up and 'cause a section of the
load line to extend into the shaded region. Therefore,
the junction temperature can exceed Tj(MAX) = 150°C
in the worst case if the circuit operates on such a section
of the load line.
10
12.28 + 100
0.089A
10
IOUTB =
12.28 + 50
0.161A
8y (4):
Po
= (0.089)2
• 12.28 + (0.161)2. 12.28 = 0.41W
By (1):
Tj = 70.5°C
Whether this situation will occur or not is determined
by both the value of V CC - V L and the RON range of
the drivers.
And by (3):
RON = 12.28n
2·41
.:..
......
......
,...
,...
,...
1000
Z
...
550
500
450
400
350
300
Z50
1/
IL
V
zoo
150
100
50
0
IL
k'"
V
k'"
vee = 5V
Ti = 1500 e -
1
.1
1.1
0.5 1 '1.5 Z Z.5 3 3.5 4 4.5
vee - VOUT IVI
To a first approximation'-, the section of the load line
between A and e is the operating range for the circuit at
Vee - VL = 5V and RL = 11.1n. Hence, the available
current and voltage ranges for this circuit are 310 mA:::::
lOUT::::: 172 mA and 3.4V ::::: VOUT ::::: 1.9V, respec·
tively.
TLlF/6025-5
FIGURE 5. TyplcallOUT vs Typical VOUT
*Strictly speaking, RON is a non-linear function 'of lOUT. A
typical RON characteristic at Tj = 150°C is shown in Figure 5.
The non-linear characteristic near the origin is due to the fact
that the output NPN transistor is not saturated. As soon as
Thus, by simply drawing no more than 3 straight lines,
one obtains all of the following immediately:
saturation is reached (lOUT ...... 150 rnA) the curve becomes a
straight line which extrapolates back to the origin. For practi·
cal design purposes, it is sufficient to consider RON as a linear
function of lOUT.
1. All the necessary design information (e.g., minimum
RL, minimum available lOUT and VOUT, etc.)
2. Operating characteristics of the circuit as a whole,
including the effect of different RON values due to
process variations, thus, a better insight into the'
circuit operation.
**Note that as the pperating point on the load lin~ moves away
from the Po = O.57W curve, (awav from the tangent point in
this case), the actual junction temperature drops. Therefore, at
point A, for example, the d~vice is actually running 'cooler than
Tj = 150°C, even in the worst case. Hence, RON value drops
below 1SH and the actual operating point is slightly different
fromA.
2-42
~--------------------------------------------------~~
To further simplify the design, a family of such curves
has been generated as shown in Figure 6. Each of these
curves corresponds to a particular T A and Po (per driver)
as indicated, and similar to the Po = O.57W curve in
Figure 4, is generated from (6) by using appropriate T A
values. The application of these curves is illustrated as
follows:
z
b) Vee -'VL = lOV
.:...
The RL(MIN) given in (B) may not be a true
minimum if the tangent point does not fall inside
the specified RON region. The actual RL(MIN)
can be obtained as shown in Figure 7. The calcula·
tions and results are given in Table II.
Example 1
1. In Figure 3, assume that the two drivers in the
MM74e908 package are to operate under identical
conditions. Find minimum RL at TA = 25°e, 45°e,
65°e and 85°e for both Vee - VL = 5V and VeeVL = lOV.
Note that the RL(MIN) values in Table II are
lower than those given by (8). This corresponds to
the section on each of the 4 load lines in Figure 7'
which extends beyond the power limit curve at
each associated. tempera·ture. However; this section
on each load line is outside the specified RON
range. Within the RON range, load lines are below
the power limits; therefore, safe operation is
guaranteed.
Then plot RL(MIN) vs TA.
a) Vee -. VL = 5V
By constructing the load lines tangent to the
curves for TA = 25°e, 45°e, 65°e and 85°e,
RL(MIN) for each case can be obtained through
the vertical coordinate for the intersection points
as shown in Figure 6. These are calculated in
Table I.
The RL(MIN) vs TA plot is as shown in Figure 8.
All the curves generated so far are restricted to
Po ::; O.57W due to our simplifying assumptio~
that both drivers are operating identically. In
Figure 9 a few more curves are added to account
for the general situation in which only the restric·
tion POA + POB <:::: 1.14W is required, (i.e., POA
can be different from POB). Application of
Figure 9 is illustrated as follows:
Note that the same results (within graphical error)
can be obtained analytically by letting dR L/
d RON = O. It can be shown that
(Vee - VU 2
(8)
RL(MIN) =
4X (Max Power Per Oriver)
TABL,E I
TA
lOUT @ 01, 2, 3, 4 (rnA)
5
RL(MIN) = IOUT@ Pl, 2,3,4
(n)
25"C
450
45"C
375
65"C
310
85"C
240
11.1
13.3
16.1
20.8
25"C
261
45"C
230
65"C
197
85°C
166
38.3
43.5
50.8
60.2
TABLE"
TA
IOUT@ 01,2,3,4 (rnA)
RL(MIN)
=
10
IOUT@ 01,2,3,4
(n)
2·43
~
.....
.....
.....
Z
1000
Ii?
Po = 0.57W
~\ \\
~
Po = O.JW
'\.\'
.,,
OJ
~,~ l\
04
r-.",
......
"'-
, 100
/~ON=lB
V
~~~
./
/V
~ ,'~
~ r" LS: ~
~ ~ ~ ~ t::: t-t-.
V
~
~~
~
!./V
ILTA = 25 e
yTA=45e
TA = 65 e
yTA-BS'e
\
~
4.
10
12
11
lJ
14
Vee - VOUT(V)
15
TLlFI5025·6
FIGURE 6
1000
gOO
BOD
700
Po = 0.57W
600
Po = 0,4BW
r,\
Ii?
400
l\'
JOO
Dl
200
Po = O.JW
,
'1\' l\
V
\\'
--s;;:"
~ -:\ ~ ~
~
~
100
/
o
./
././
RON =IB
./
././
/1
;;:,....
S
-
..ii;; "..; ~ ;;;;;.
:==::::
.:::::
~
TA = 25"e
TA=45"C
~4t" .•.,
~B51'e
t- ~
o
10
Vee - VOUT (V)
FIGURE 7
2·44
11
12
lJ
14
15
TlIF16025·1
70
60
VCC -VL = l O r
-Z
~
a:
50
40
./
.....
v
30
20
~
10
25
:,.......-- VVcc'" -
Vl = 5V
T i
45
65
85
105
125
AMBIENT TEMPERATURE rc)
TLIFI6025·8
FIGURE B
1000
900
I
800
700
I.--1111 In· :--
111m 1\1' I I
IlIImu I
'~I. I
1\
PO=0.48W
l 'I~ Po = 0.39W
\\
~I\ ~\))
;X~~TA=9rC
100
~~~.:><,:----.:--::~~~ -r-~TA
l
y. ~"'S~~::--..:t.Y~- -~~
><~......:::::-.....
VV
:::::--
~:: :~~::~
125'&
TA = 130"&
~ . "- TA=135"C
~I TA 140"C
,0i
.
10
VCC - VOUT (V)
FIGURE 9
2·45
11
12
13
14'
15
TLlFI6025·9
~.----------------------------------------------------------------------,
~
.....
Example 2
<
In Figure 3, assume that driver A has' to deliver 200 mA
to its load while driver B needs only 100 mAo Design
'RLA and RLB for VCC - VL ~ 5V.
z
Since PDA + PDB::; 0.9 + O.lB < 1.14W
RLA ~ 7.m
RLB ~ 33.3.11
By inspection of Figure 4, units with high RON values
will not be able to deliver 200 mAo However, since
section B does not need the same 'amount of drive, we
can reduce the power consumed in this section to compensate for the higher power (> 0.57W) required in
section A.
satisfy all the requirements in this problem.
The'design in Example 2 illustrated the simple and
straight-forward use of the curves and the result
meets all the problem requirements. However, it
should be noted that there is not much design margin
left for tolerance in resistances and other circuit
parameters. The reason is obvious-we are pushing at
the power limit of the MM74C908 package-and the
solutions are sirT!ple:
The design procedure follows:
Section A
1. Draw a load line intersecting RON": 18.11 line at
lOUT ~ 200 mA.
2. This load line intersects the lOUT axis at lOUT ~
710 mA and is tangent to PDA "" 0.9W curve, thus
R LA ;:, 5V /710 mA ~ 7.1.11 will guarantee both
PDA::; 0.9W and lOUT A::::: 200 mAo
a) Increase VCC supply
b) Use the higher power package MM74C918.
The design for higher VCC is identical to that in
Example 2 and will not be repeated here.
For the 14-lead higher power (2.27W) MM74C918,
0jA ~ 55°C/W, this is exactly half that of the 8-lead
MM74C908. Therefore, by scaling the lOUT axis by
a factor of 2, the same family of curves in Figure 9
can be applied directly. This is shown in Figure·10.
(Note that the slope of the RON ~ 18.11 line has been
adjusted to the new scale).
Section B
1. Draw a load line intersecting RON ~ 18.11 line at
lOUT'; 100 mA.
2. Similar to (2) above, it is seen .immediately that
RLB'=' 5V /150 mA'~ 33.3.11 will guarantee IOUTB:::::
100 mA and PDB::; 0.18W.
2000
1900
1800
II
1700
1600
III\\~
1500
1100
~\
900
~
Po = 0.27W
~Po=0.~8W
"" ,OC' Yt\.
Y
I_TA=25"C
TA = 40C
TA = 70'C
,,\~-~~=55"C
l\ ~.x '\;~
7r:TA=80"C
I flTA=8T'C
r-0::--"I'~~ I TA=97"C
RON = 18,
1>1---'
lX 1\\ l'.:i':::~~~~t-..
_-r. '
\ I\: ~ .... ;::'r-.:;t-'~~~"
t""~~
~:-"~ ,-
TA = 107 C
4TA=11T'C
300
o
~
"\1\ Xi-xl\.' ,,,,-"I
400
100
Po = 0.36W
Vi (V ~~\
800
200
-- Po = 0.59W
,\ ,\
\\ \.\ V>;
\ PoI= 0,45W
L
:>
500
"
-
~PO=0.77W
-;:. 1000
700
Po = U3W
Po = 1.45W
Po = 1.27W
I - PO=1.14W
"
\ \ \
1200
600
I
1\
1~IIPo=0.95W
1300
_0
Po - 2.27W
Po' 2W
\ir :-
~\
1400
«E
nil 1'."--
\'1\\\
t-
r-....
...... l-- I -
,....
~
~
??
'''"'
TTA 130'C
I.TA-mo c
ITA = 140'C
o
10
Vcc - VOUT (V)
FIGURE 10
2-46
11
12
13
14
15
TLlF16025·10
By drawing the same load lines, it is found that:
$ince PDA + PDB -::; 1.14 + 0.4 = LaW, while the
package is capable of delivering 2.27W, both R LA
and RLB can be lower than the above values and
the circuit still operates safely. By picking the closest
standard resistance values:
RLA'" 5V/710 mA = 7.1Q
guarantees PDA -::; 0.9W
. and
RLA = 20Q
RLB = 43Q
RLB '" 5V/150 mA = 33.3Q
guarantees PDB -::; 0.1aW
For 5% tolerance in these values,
PDA + PDS -::; 1.0aW
19Q -::; RLA -::; 21Q
40:85Q -::; RLB -::; 45.15Q
which is way below the maximum power 2.27W
available. Therefore, both R LA and R LB can be
lowered to account for tolerance in the resistors. Can·
sider specifically the following example:
Thus:
10V
IOUTA(MIN) =2:
18Q+21n
Example 3
Assume driver A, B of the MM74C918 have to deliver
250 mA and 150 mA, respectively, to its load. Design
RLA and RLB at VCC - VL = 10V.
10V
IOUTB(MIN) =2:
Driver A
PDA(MAX) -::;
1. In Figure 11, draw the load line .intersecting RON =
18Q at lOUT =,'250 mAo
2. This load line intersects the lOUT axis at 450 mA.
Thus, by inspection R LA '" 1OV /450 mA '" 22.2Q
guarantees PDA -::; 1.14W.
PDB(MAX)
<(
-
256.4 mA> 250 mA
158.3 mA > 150 mA
18Q + 45.1.5Q
(
10v
)2
18Q+ 19Q
• 18Q = 1.31W
10V
) 2
18Q + 40.85Q
. 18Q = 9,52W
PDA(MAX) + PDB(MAX) -::; 1.31 + 0.52
Driver B
< 2,27W
Therefore:
1. Draw the load line intersecting RON = 18Q at
IOUT= 150 mA,
2, This load line intersects the lOUT axis at 210 mA.
Thus, by inspection RLB '" 10V/210 rnA = 47.6Q
guarantees PDB -::; O.4W.
RLA = 20Q.(1.5W, 5%)
RLB = 43Q (1W, 5%)
will guarantee satisfactory performance of the circuit,
ZOOO
1900
1800
1700
1600
-1500
111m In v
111111 ltlt-I
IIII~' I
, l::b\-I-
1300
E
1100
1'1\ '
~ 1000
V(
800
600
SOD
400
300
ZOO
r--
Po = 0,36W
.\1(\ j)(X Po = O,Z,lW
900
700
Po = I,Z7W
Po = 1.14W
Po = 0,95W
Po = O,77W
I--- Po = 0.S9W
lH\ t-l\ 1\
I I
1-\ Po = 0,4SW
lZ00
_r::J
I - Po = 1.4SW
rtt1:-+--i
H-11
1400
~
Po = Z,Z7W
Po = ZW
Po = i.73W
~\PO=O'IBW
~:o=-f--' TA = 2S"C
~y~y. .~
~~~
r-:.(\'
r----
~\J\
I TA=40"C
'i/TA=S5"C
\.
,'\t\.:"K
I
TA=70"C
/ TA=BO"C
'b- TA=B7"C -
RON=18
.X\: ' - 0.~:""---"""'~~~97"C _~TA=107"C
.Yo ~'\~ ... t>. "'~I1Z,_.>TO
1\ f\.:~ ""~.............
100
o -~
o
:r:-~
(': I ~A:
A ~~~:~
__
I""
~
e--
TA-13S"C
TA=I~"C
7
VCC ~ VOUT (V)
FIGURE 11
2-47
10
11
12
13
14
15
TLlF/6025·11
l>
Z
..:..
...,
...,
~r-------------------------------------------------------------------------------------,
~
.....
Z
Vlt-----------~~----------_.------.
Rf
240k
(bl
TlIF/6025-16
TLlF16025·17
(al
FIGURE 15. Single Driver Oscillator
/'
vcc'
lOV
-------,
I
I
I
I
I
L __ _
I
MM14C908. MM14C9l8
24k
24k
680k
I'M
rO.OlMF
FIGURE 16. Low Cost Siren
2-50
TLIF/602S-19
l:o
The NAND functions at the input can also be used to
reduce package count in applications where both high
output drive and input NAND features are required.
One such example is given in Figure 17.
1/2 MM74C908. MM74C918
1..._
R o---'--t._J
1/2 MMi4C908. MM74C918
----------Tl1F/6025·2Q
FIGURE 17. High Drive RS Latch
2-51
Z
.:...
.....
.....
Electrostatic Discharge
Prevention -Input Protection
Circuits and Handling Guide
for CMOS Devices
National Semiconductor
Application Note 248
Vivek Kulkarni
June 1980
Introduction
Standard Input Protection Networks
During the past few years, there have been significant
increase in the usage of low-power CMOS devices in
system designs. This has resulted in more stringent attention to handling techniques of these devic.es, due to
their static sensitivity, than ever before.
In order to protect the gate oxide against moderate levels
of electrostatic discharge, protective networks are pro·
vided on all National CMO'S devices. as described below.
All CMOS devices, which are composed of complementary
pairs of n- and p-channel MOSFETs, are susceptible to
damage by the discharge of electrostatic energy between
any two pins. This sensitivity to static charge is due to the
fact that gate input capacitance (5 picofarads typical) in
parallel with an extremely high input resistance (10'2 ohms
typical) lends itself to a high input impedance and hence
readily builds up the electrostatic charges, unless pro'per
precautionary measures are taken. This voltage build-up on
the gate can easily break down the thin (1000A) gate oxide
insul!ltor beneath the gate metal. Local defects such as
pinholes or lattice defects of gate oxide can substantially
reduce the dielectric strength from a breakdown field of
8-10 x 106 V/cm to 3-4 x 106 V/cm. This then becomes the
limiting factor on how much voltage can be applied safely
to the gates of CMOS devices.
Figure 1 shows the standard protection circuit used on
all A, B. and 74C series CMOS devices. The series resis·
tance of 200 ohms using a P+ diffusion helps limit the
current when the input is subjected to a high-voltage
zap. Associated with this resistance is a distributed
diode network to Voo which protects against positive
transients. An additional diode to Vss helps to shunt
negative surges by forward conduction. Development
work is currently being done at National on various
other input protection schemes.
0,
INPUT
When a higher voltage, resulting from a static discharge,
is applied to the device, permanent damage lik.e a short to
substrate, Voo pin, Vss pin, or output" can occl,lr. Now
static electricity is always present in any manufacturing
environment. It is generated whenever two different materials are rubbed together. A person walking across a production floor can generate a charge of thousands of volts.
A person working at a bench, sliding around on a stool or
rubbing his arms on the work bench can develop a high
static potential. Table I shows the results of work done by
Speakman' on various static potentials developed in a
common environment. The ambient relative humidity, of
course, has a great effect on the amount·of static charge
developed, as moisture tends to provide a leakage path to
ground and helps reduce the static charge accumulation.
0---'\11.,.......-1
OUTPUT
DIODE BREAKDOWN
0, =25 VOLTS
0,=60 VOLTS
·THDis~ ~~~ ~~~~~NSIC DIODES +-----......-'
Yss
Figure 1. Standard Input Protection Network
Other Protective Networks
Figure 2 shows the modified protective network for
CD4049/4050 buffer. The input diode to Voo is deleted
here so that level shifting can be achieved where inputs
are higher than Voo.
Y"
0,
INPUTo-.....W
TABLE I. Various Voltages Generated in 15%-30%
Most Common
Reading
(Volts)
12,000
39,000
Person walking across
vi nyl floor
.
4,000
13,000
Person working at bench
DIODE BREAKDOWN P+
0, =25 VOLTS
02=60 VOLTS
03 100 VOLTS
·THESE ARE INTRINSIC DIODES
500
3,000
16-lead DIPs in plastic
box
3,500
12,000
16·lead DIPs in plastic
shipping tube
500
3,000
0,
=
Highest
Reading
(Volts)
Person wal king across
carpet
H .....-+-oOUTPUT
'DOll
Relative Humidity (after Speakman')
Condition
.....- - ;
Vss·
TliFIB029·2
Figure 2: Protective Network for CD4049/S0
and MM74C90112
Figure 3 shows a transmission gate with the intrinsic
diode protection. No additional series resistors are used
so the on resistance of the transmission gate is not affected.
.
All CMOS circuits from National's CD4000 Series and
74C Series meet MIL.,STD-38510 zap test requirements
of 400 volts from a 100 pF charging capacitor and 1.S kQ
series resistance. This human body simulated model of
2-52
~E (P·CHANNEll
......
T
......
10M
D,
IN/Duro--
Vo
D.,!. .
or~~~B6~Ec~r~r~
0, =25 VOLTS
'THESE ARE INTRINSIC DIODES
1 S, 2
o---~y-~~
1
~E
1
~OUT/IN
!2 .
TO DEVICE
UNDER TEST
(DUTI
J'00PF
8, == Hg - WETTED' BOUNCELESS' 'RELAY
...
(N-CHANNEll
RS=1.5k
~
HIGH VOLTAGE
SUPPLY
TUF16029-4
TlIFJ60293
Figure 3. Transmission Gate with Intrinsic Diodes to
Protect Against Static Discharge
Figure 4_ Equivalent RC Network to Simulate Human
Body Static Dischame (After Lenzlinger2)
100 pF capacitance in series with 1.5 kQ series resistance
was proposed by Lenzlinger2 and has been widely accepted by the industry. The set-up used to perform the
zap test i"s shown in Figure 4.
Above all, there should be static awareness amongst all
personnel involved who handle CMOS devices or the
slJb-assembly boards. Automated feed mechanisms for
testing of devices, for example, must be insulated from
the device under test at the point where devices are
connected to the test set. This is necessary as the transport path of devices can generate very high levels of
static electricity due to continuous sliding of devices.
Proper grounding of equipment or presence of ionizedair blowers can eliminate all these problems.
VZAP is applied to DUT in the following modes by charging the 100 pF capacitor to VZAP with the switch S1 in
position 1 and then switching to position 2, thus
discharging the charge through 1.5 kll series resistance
into the device under test. Table II shows the various
modes used for testing.
TABLE II. Modes of High-Voltage Test
Mode
+Terminal
-Terminal
1
Input
Vss
2
VDD
Input
3
Input
ASSOCiated Output
4
Associated Output
Input
Pre- and post-zap performance is monitored on the input
leakage parameter at VDD = 18 Volts. It has been found
that all National's CMOS devices of CD4000 and 74C
families can withstand 400 volts zap testing with above
mentioned conditions and still be under the pre- and
post-zap input leakage conditions of ± 10 nA.
Handling Guide for CMOS Devices
From Table I, it is apparent that extremely high' static
voltages generated in a manufacturing environment can
destroy even the optimally protected devices by reaching
their threshold failure energy levels. For preventing such
catastrophies, simple precautions taken could save
thousands of dollars for both the manufacturer and the
user.
In handling unmounted chips, care should be taken to
avoid differences in voltage potential between pins. Conductive carriers such as conductive foams or conductive rails should be used in transporting devices. The'
following simple precautions should also be observed.
1. Soldering-iron tips, metal parts of fixtures and tools,
and handling facilities should be grounded.
2. Devices should not be inserted into or removed from
circwits with the power on because transient voltages
may cause permanent damage.
3. Table tops should be covered with grounded conductive tops. Also test areas should have conductive floor
mats.
2-53
At National all CMOS devices are handled using all the
precautions described above. The devices are also transported in anti-static rails or conductive foams. Antistatic, by definition3 means a container which resists
generation of triboelectric charge (frictionally generated)
as the device is inserted into, removed from, or allowed
to slide around in it. It must be emphasized here that
packaging problems will not be solved merely by using
anti-static rails or containers as they do not necessarily
shield devices from external static fields, such as those
generated by a charged person. Commercially available
static shielding bags, such as 3M company's low resistivity (0;; 104 ohms/sq.) metallic coated polyester bags,
will help prevent damages due to external stray fields.
These bags work on the well-known Faraday cage
principle. Other commercially available materials are
Legge company's conductive wrist straps, conductive
floor coating, and various other grounding straps which
help prevent against the electrostatic damage by providing conductive paths for the generated charge and
eqUipotential surfaces.
It can be concluded that electrostatic discharge prevention is achievable with simple awareness and careful
handling of CMOS devices. This will mean wide and
useful applications of CMOS in system designs.
Footnotes
1. T.S. Speakman, "A Model for the Failure of Bipolar
Silicon Integrated Circuits Subjected to ESD," 12th
Annual Proc. of Reliability Physics, 1974.
2. M. Lenzlinger, "Gate Protection of MIS Devices," IEEE
Transac. on Electron Devices, ED-18, No.4, April 1971.
3. J.R. Huntsman, D.M. Yenni, G. Mueller, "Fundamental
Requirements for Static Protective Containers." Presented at 1980 Nepcon/West Conference, Application
Note - 3M Static Control Systems.
~
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r------------------------------------------------------------------------------------,
Z A Bro,adcast Quality TV Sync
C\I
« Generator Made Economical
through LSI
The growing numberol applications of video tape recorders and TV cameras in the consumer market have resulted in the need for a single-chip LSI integrated circuit
TV camera sync generator_ The National Semiconductor
MM5321 TV Camera Sync Generator has been developed
to economically provide the basic sync functions for
color and monochrome, 525 line, 60Hz, interlaced applications - and provide it with the reliability and accuracy
of a digital IC system_ A Metal-Oxide-Semiconductor'
(MaS) technology was chosen as the most economical
method of obtaining the necessary circuit density and
speed.
Figure 1 shows the simplified block diagram and Figures
2 through 5 are the timing diagrams of the generator.
All inputs and outputs of the 14-pin device are TTL compatible without the use of external components. Two
supplies are required, with the nominal difference be-'
tween them 17 volts. Ambient temperature may be varied
between - 25"C and + 70 "C.
The output functions provided are Horizontal Drive, Vertical Drive; Composite Blanking, Composite Sync, and
Color Burst Gate. In addition, a Field Index output function identifies a particular field, and a Color Burst Sync
output presents a pulse at half the horizontal rate, but
otherwise identical to the Color Burst Gate, and may be
used to synchronize the color burst with the generator.
National Semiconductor
Application Note 251
Robert B. Johnson and
Eugene H. Campbell
May 1980
All output functions are derived from the clock applied
to the Master Clock input. The user may select either of
two input frequencies by selecting the proper horizontal
divider, which is accomplished by hard-wiring the Divider
Control pin to either the Vss (most positive) or VGG (most
negative) power supply.
In color applications, a frequency four times the color
burst is usually available to generate the O"C and 90"C
color sub-carrier signals. Dividing that frequency by
seven results in 2.04545 MHz, which is the input clock
signal to be used when the Divider Control pin is connected to Vss. With the control pin wired to VGG, the horizontal divider is programmed to accept an inpllt signal
eighty times. the horizontal rate, or 1.260 MHz.
The horizontal divider is essentially a 65-bit shift register
which can be shortened to 40-bits with the Divider Control logic. Control logic also selects the proper set of
register taps used for decoding the horizontal timing
edges.
One of the outputs of the horizontal divider is a signal
used to drive the ten·stage vertical counter and 8,42-bit
shift register, which together provide the verical division
and timing edges.
Shift registers are usually very efficient logic blocks in
MOS designs, which is why they were selected for many
of the counters in this product. Parasitic capacitances
may be used to store charge for periods of time that'are
Figure 1. Block Diagram of a TV Camera Sync Generator
Fabricated with MOS/LSI Techniques
2-62
TLlF/6153-1
essentially dependent only on semiconductor junction
characteristics. Thus, in MOS it is possible to design
both dynamic and static shift registers. Dynamic regis'
ters were used for both the vertical and horizontal
counters because in each case the clock frequency is
well above any minimum limitation due to leakage cur·
rent 'considerations, and they offer a layout/size advan·
tage over static type cells. The configuration selected
uses ten transistors and is capable of being reset to
either a "1" or "0" logic state.
'
The vertical divider is comprised of DC flip·flops config·
ured as a ten·stage short·cycled, modulus 525, ripple
counter. Each stage is resettable, and to accommodate
additional vertical reset versatility, stages 1, 2, and 8
can be set or reset.
-II-'=H
HOR'Z~~i( 11111111111111111111111111
COLOR B~~( 1111
n
111111111111111
1IIIIIIIIIIIIn
111111
COLOR B~:( "'-1"-'11----r"1--'-1--'--1"'--1""'1Ir---TI---'I-'--1"'--1"IIllh/II"""'"""TI---'I--'-1-'-1"-1r--TII
+5-----,1-9H-1
, i --------<1,'11--9H-1i -- VER~~~e~
OV
I
I
! .I
VERTIINDEX
CAL+5---.---------------<111----------- 1- 525H
OV
+5
COMPOSI
BLANKINTGE
OV
TIm.
1
21H
rl
.....- - - - - - - - -
1-3H+3H+3H-1
IDllliJlJJlllllm
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I
rrTTT
EOUALIZATION -1-11 1-1- EQUlIZATlON EQUALIZATION-I-III-~I-EQUALIZATION
VERTI
VERTICAL
SYNCCAL
SYNC
TlIF16153-2
Figure 2. Sync Generator Output Waveforms
MASTER
CLOCK
INPUT I_SERRATION GATE_I
l
9 TA ~ 0,B71"
i-I----------------------EQUALIGATEZATION I
FRONT PORCH _ I
I--;r.3TA =0,023H
=00386H"'
-----"--'-'.:"'----:-[---;1
Ir---------ZONTAL SYNC
------7[--111_HORI10 T.=0,0774H
i-I-----------~I
_HORIZONTAL
13 T.=0,10IH
ORIVE~I
--------i
I'
i-----------------
1
HORIZONTAL BLANKING ______
-------iI..- - - - - - 22 TA=O 170H
~,
1
I
i-------1
I-,;;;~~~O:A~I
-------------------;15TA=003B6
i-I---------
Figure 3. Horizontal, Timing Diagram with the Input
Clock Frequency Equal to 2.04545 MHz
2·63
~
r-------------------------------------------~--------------------------------------~----,
It)
C'II
Z
c:r:
1I--fa
10 __
='
Mi -= O.794~s
1.26~MHZ::::
I
I-SERRATION-I
GME
~--------------~----------------------------------6T,;,o°15H
I
I
FRONT PORCH_I
218 :2!= 0.025H
I_I_EQUALIZATION GATE
3 1a ~ 0.0375H
Ui--------
I
II
----------~---;
I
-----II
-HORIZONTAL~I
SYNC
6T,=O,075H
_HORIZONTAL DRIVE_I_ BACK PORCH _I
81a=0.lH
6TB?- 0.075H
Ir----;--I- - Ir---------------
I
----~
Ir---------------------------------------'
_HORIZONTAL BLANKING~
14T8=0.175H
COLOR BURST GATE
I
I- 3Ta?-O.037SR
---------1U
TLlFI0153·4
Figure 4. Horizontal Timing Diagram with the Input
Clock Equal to 1.260MHz
,
1
1
315kHz ::- 0 03175
sec
6
1--EQUALlZ~UON GATE - 1 · · - - - - 3 H - ' - - - I - - - -
l
I
1--SERRATj~N
-------------------~I'
I ~-
1~
~I____~
GATE ~I
~I----------------~I'~
VERTICAL DRIVE & HORIZONTAL INHIBIT
________
--------.1
9H_ _ _ _ _ _ _ _
~r~
FIELD 1NDEX
--Ur-~~----------------------------~I~
-11- ~~W~~~O~~Er~RJ~~1
TLlFI6153·S
Figure 5. Vertical Timing Diagram
2·64
~
z
N
U1
.....
2H INPUT
FROM HORIZ --1~--------'"
DIVIDER
10 STAGE
MODULE 525
VERTICAL
COUNTER
42·BIT
SHIFT
REGISTER
DECODING
AND
SHORT
CYCLE
LOGIC
Tl/F/615J-6
Figure 6. Simplified Vertical Timing Logic
its impurity concentration. They are also affected by
temperature, which reduce the fermi potential (decreas·
ing threshold), and modifies the carrier mobility in the
transistor channel (which lowers the gain factor). the reo
,duct ion in gain factor generally has more effect than the
change in threshold, resulting in an overall reduction in
speed with increasing temperature.
Figure 6 indicates the method of generating the vertical
output functions. Decoding logic detects the 525th state
and short cycles the counter by resetting it to zero. Sim'
ultaneously, the input of the 42·bit shift register is set to
zero and the vertical blanking and ~qualization gates are
initiated. Six register clock periods later, the equalization
gate is terminated and the serration pulse is initiated by
the arrival of a zero state at the sixth bit of the shift reg·
ister. Similarly, the serration gate is terminated and the
equalization gate reinitiated when a zero is detected at
the 12th ta'p and, finally, the equalization gate is termin·
ated when the 18th tap changes to a zero. The vertical
drive pulse is also initiated when the register input goes
to a zero, and is terminated when the zero reaches the
18th bit. The vertical blanking pulse lasts until the zero
propagates to the 42nd bit, at which time the register
input is reset to a logical "1" level.
As far as the sync generator is concerned, this variation
in performance as a function of environmental and power
supply conditions could cause skewing of individual
output timing edges, reducing the accuracy of the sync
functions. Careful design essentially eliminates this
problem in the MM5321. First, all output functions were
matched for total logic delay by simulating circuit per·
formance for all environmental and process variations,
and then optimizing the delays to the output buffers.
Second, all output functions are resynchronized at the
outputs by an internal clock signal running at the input
clock rate, with its own optimized delay characteristics
with respect to the horizontal divider clock. For all
worst·case conditions the output functions reach the
synchronizing point before the synchronizing clock.
Third, all the output buffers themselves are identical
and therefore have matched delays. Thus, the design
results in output functions whose timing delays are
matched with respect to each other, but will have differ·
ences in delay with respect to the input clock on a part
to part basis (due to variations in process variables).
Even on a part to part basis, maximum differences in
delay between two parts with the maximum allowed process variation should be less than 200ns, or 0.003H, at
similar temperature and power supply values.
In some applications, particularly video recorder tape
editing, it is necessary to identify which field of the ver·
tical frame the system is in. For that purpose, the gener·
ator derives a Field Index pulse which identified field
one by occurring for two input clock periods at the lead·
ing edge of thRvertical blanking pulse of field one. Field
one is defined as the field with a whole ~canning line in·
terval between the equalizing pulse and the last line sync
pulse of the preceding field. .
When designing MOS circuits, one must be aware of the
effects of power supply variations, ambienllemperature
excursions, and process variables on circuit performance.
This is the case in design of most circuits of course, but
MOS tends to be more sensitive than bipolar circuits
due to increased parasitic capacitance and limited cur·
rent drive capabilities. The speed pf any MOS product is
essentially dependent upon how fast critical capacitive
nodes can be chamed and discharged. The charging or
discharging current is in turn a function of the size, the
voltages applied to, and the threshold and gain factor of
the transistor(s) supplying the current. Threshold and
gain factor are functions of process variables such as
gate oxide thickness, the type of substrate material and
The output buffers are push·pull using the circuit configuration shown in Figure 7. The output transistors 01
and 02 provide the sink and source characteristics
shown in Figure 8. When' interfacing directly with TTL,
the 800Q resistor serves to limit the excess sink current
supplied to the TTL clamp diode, by reducing the gate
drive to 02. This minimizes excessive power dissipation
on the chip and protects the TTL diode. 08 is the logic
transfer device driven py the synchronizing clock.
2·65
y-
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r----------------------------------------------------------------------------------------------,
Z
ct
SOOQ
~t
SYNCHRONIZING
-'S
CLOCK ..,......,
"
SUFFER
OUTPUT
06
L-____~~----~--~
(
TlIF/6153·7
Vss
Figure 7. Schematic of TTL Compatible Push·Pull Buffer used
on All Outputs of the Sync Generator
r---.. .........
F=::: ~
II TA =-25·~
-....:;
-......::::
-
I--. ~25·C
~~
J-
TA=7t·C
'1
=
=
vss 5.0V
voo= -12.0V
o
5
Vss 5.0V
OL-~__~__~_~~o~=_-_1~2._0V~
5
1
0-1
-1
Vour (VOLTS)
Vour (VOLTS)
TL/F16153·6
Figure 8a. Typical Output Sink Current as a Function
of Output Voltage
.
Tl1F16153·9
Figure 8b. Typical Output Source Current as a Function
of Output Voltage
Voo
INTERNAL INTERNAL
CLOCK
! CLOCK
CLOCK
INPUT
Vss
TLIFJ6153·10
Figure 9. Schematic of Input Clock Buffer
The most critical circuitry in th'e generator, from the
·standpoint of speed, is the input clock buffer (Figure 9).
The buffer is designed to generate a two-phase, full
power supply am'plitude clock signal from the single·
phase low amplitude input signal. 01 through 04 constitute a Schmitt trigger type input stage that guarantees
a trip-paint range of Vss - 4.2V maximum for "0" levels, .
and Vss - 2.0V minimum for TTL "1" levels. When
interfacing directly with TIL, the normal supplies will be
2-66
+5 volts connected to. Vss, and -12V connected to the
VGG pin. For a tolerance of 5% on the Vss supply, the
guaranteed trip'points decipher to a'required input level
more negative than 4.75V-4.2V, or 0.55V, for the "0" level,
and a required level more positive than 4.75V·2.0V,or 2.75,
for the "1" level. These levels are obtainable from standard TIL without any external interface components.
010 and 011 are feedback latches which eliminate in·'
ternal clock overlap problems.
,...--i.>:>--t-'lM>r-'9-+------------.;INPUT
5-BIT S.R.
Vss
VERTICAL
RESET
CONTROL
TO VERTICAL
OIVIOER
RESET
CIRCUITRY
RESET
CONTROL
LOGIC
16-BIT S.R.
t
CLOCK FROM
INPUT CLOCK
BUFFER
V's
TLlFI6153·11
Figure 10_ Basic Logic for Detecting Proper State of the Composite Sync Input
Signal for Resetting the Vertical Divider in "Gen-Lock" Operation
To provide as much versatility as possible, a variety of
divider reset ("gen-clock") features have been included.
The horizontal and vertical dividers have individual Vertical and Horizontal Reset inputs which allow independent resetting of the appropriate divider. With the inputs
tied together, both dividers may be reset simultaneously.
The vertical divider may be reset to either of two states,
depending upon the DC level of the Reset Control pin. If
the Reset Control is tied to Vss, the most positive supply,
a TTL "1" to the "0" level transition on the Vertical Reset .
pin will reset the vertical divider to all zeros, which is
time zero as defined by the vertical timing diagram. With
the Reset Control returned to VGG, a Vertical Reset
pulse will reset the vertical divider to the fifth serration
pulse (eleven 0.5H time intervals from time zero). This
allows the reset pulse to be generated by analog detection of a composite sync or video signal, and used to
gen-Iock the slave sync generator within the same field
interval. The horizontal divider is always reset to zero, as
defined by the horizontal timing diagram.
The Field Index output pulse occurs once during each
field one at time zero and last for two master clock periods. It can be used to gen-Iock similar sync generator
chips by connecting it to their Vertical Reset inputs and
wiring the Reset Control to the Vss supply_
Another method of resetting the vertical divider is provided by using the Reset Control pin as an input for a
composite sync signal from which gen-Iocking is desired.
Th·e slaved generator detects the fifth serration pulse
and resets tne vertical divider to the proper state (Figure
10).
register are reset to zeros. If the composite sync signal
remains low for fifteen master clock periods, another
two-phase signal is generated which acts as the clock
for a 5-bit shift register used to store the sampled state
of the inverted (and filtered) composite sync signal. The
sample is the average value of the filiered signal during
an approximately 200ns sampling window occurring just
before the fifteenth master clock time after the composite sync input signal initially went low. The input trippoint of the 5-bit register determines whether the sampled signal is stored as a "1" or "0" logic state.
.Fifteen input clock periods equal a time of 7.3/As at an
input clock frequency of 2.04545 MHz, and 11.9/As when
the input rate is 1.260 MHz. The only interval of the composite sync waveform which is legitimately low during
this time is the vertical sync pulse. In the present design,
the first five serrated intervals must be successfully detected before the vertical divider is reset to the proper
state. The limitation in this design may be the difficulty
in acutally acquiring legitimate detection due to excessive noise and missing pulses in the composite sync
input signal. If this proves to be the case, it is possible
to eliminate the second and/or fourt,h bits of the 5-bit
register as detection requirements. This should improve
the statistical probability of getting an initial gen-Iock
condition within a reasonable time.
As illustrated above, the 8eset Control input has a dual
function. It selects the reset state of the vertical divider
when hardwired to either Vss or VGG, and acts as a dynamic input when gen-Iocking is to be established using a
composite sync input signal. When using the Reset
Control as the input for a composite sync signal, the
Vertical Reset pin should be hardwired to Vss.
The reset control logic generates a two-phase clock with
a frequency equal to the input clock rate anytime the
composite sync input signal is more negative than the
Reset Control trip-point. A 16-bit dynamic shift register
with its input connected to Vss is driven by the modulated clock signal. When the composite sync input becomes more positive than the Reset Control trip-point,
or if the 16th bit becomes a "1", ·all sixteen bits of the
The MM5321 TV Sync Generator has been designed with
both versatility and economy as the primary objectives.
We feel it exemplifies the role of MaS/LSI standard
products can play in providing useful consumer products
in a manner that both large and small volume users will
find attractive_
2-67
~
11)
~
nearly the same as for the MM74C912/MM74C917 except
that due to multiplexing the 6·digil controllers must be
designed to a higher peak current value.
Once the digit driver has been chosen and the output
voltage at the desired current is known, the segment
resistor, RSEG can be calculated using:
As an example, suppose the the N8N781 (2·digit, 0.7"
common catholde LED display) has been selected.
These displays require an average current of 8mA per
segment for good illumination. The MM74C911 multi·
plexes four digits; thus, anyone digit is on V. of the
time. Each digit must have a peak current four times its
average current to achieve the same brightness. The
MM74C911 must supply about 32mA per segment, and
the MM74C9121MM74C917 would have to supply a"cur·
rent six times the average current or about 48 rnA.
R
SEG
where VLEO is the voltage across the LED, 1.8V; Voo is
the digit driver output voltage at the chosen current;
ISEG is the peak segment current; and VSEG is the
MM74C911 or MM74C912 segment driver output voltage
at the peak segment current, which can be determined
from the curves in Figure B.
The maximum digit driver current Is the maximum num·
ber of "on" segments multiplied by the segment cur·
rent. For the MM74C911 design, the digit current is
"-'260 rnA, and is "-'380 rnA for the MM74C9121MM74C917.
Using this digit current value, the digit driver can be
selected. Figure 7 shows possible digit driver ICs, but
discrete transistors or Oarlingtons may also be used,
and may be desirable in some higher current applications.
It is also important to keep in mind that the output voltage
of 'the driver at the designed current, as this voltage can
affect the display controllers current drive. For most de·
signs, an output voltage of < 2V is reasonable.
Part
Number
D875492
D875494
D88646
D88658
D8BB70
D8BB71 12
D8BB77
D88920
D8B963
D8B97B
D8B692
VSEG - VLEO - Voo
ISEG
In most cases, RSEG can be more quickly determined
from Figure 9 which plots RSEG vs. average segment
current. These curves are plotted for various digit driver
output voltages using current values from Figure B.
Thus, for the above example, if a 0875492 driver I.C. is
used with the MM74C911 to interface to the N8B781
LEOs RSEG = 38 Q assuming the drivers output voltage is
1.0V. Note that Figure 7tabulates minimum output drive
where the above Voo is an approximation of the
08754925 typical Voo at 260 rnA.
Number 01
Drivers
Driver Type
Darlington Driver
Multiple Transistor Driver
Transistor Driver
Transistor Driver
Darlington Driver
Transistor Driver
Transistor Driver
Transistor Driver
Darlington Driver
Transistor Driver
Transistor Driver
Minimum
Output Drive
250mA@1.5V
150 mA@0.35V
B4mA@0.55V
B4mA@0.55V
350mA@1.4V
40mA@0.5V
35mA@0.5V
40mA@0.5V
500mA@1.5V
100mA@O.7V
350mA@1.0V :
6
6
6
4
6
B/9
6
9
B
9
B
Figure 7. Typical LED Digit Drivers and Their Characteristics
(b)
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I
3.5
4.0
4.5
5.0
SEGMENT DRIVER OUTPUT VOLTAGE (V)
SEGMENT DRIVER OUTPUT VOLTAGE (V)
TLIFI8030-8
TLIF16030·9
Figure 8. Typical Segment Driver Current vs', Output Voltage lor (a) MM74C911 (b) MM74C9121MM74C917
2·71
z
~
(a)
(b)
100 rrrrTT""-,---,----r-.,
100
ITT1rTTr--,---,---,---,
90~~~~~--~--~~
90~rH~--r---r---r--1
80 H--H~..,b
80 I-Hr\-\'\--+
70 f-+--\--,~-r'h
70
60 H--\-t\-~tt---:>"
50 f---Jk----'H--71r--;>i'
60 H-Hft-'l7'T-7
50 H,-t-1r-\"'bf----::40 I---H~IIT:~~b_
40
I-+-ft-~~" 300Q for VO H ;. 3.0V and
ROIG > 350 for VO H ;. 3.5 V.
If a transistor digit driver is being used, it is sometimes
desirable to use a base current limiting resistor between
the controller's output and the transistor's base. Thiswill
help limit the power dissipation of the display controller in
critical situations. The digit resistor, ROIG , can be calculated using:
,
RoIG =
A final design consideration is power dissipation_ When
designing a low-power system where the total current is
to be minimized, the total system power consumption is
simply:
.
VOIG-VOI
101
Pr ~Vcdloo + lOll
DISPLAY
HEIGHT (IN.)
0.110
DRIVER
PART NO.
NSA1298
NO. OF DIGITS
9
. TYPICAL RANGE OF
SEGMENT RESISTORS
OS75492
300-10002,
300-20002·
NSA1558
I
0.140
8
OS75492
200-8002
200-18002·
NSN381
0.3
2
OS75492
2N3904
15-802
4
OS75492
15-802
~
NSB3881
0.5
2N390~
NSN581
0.5
2
OS75492
2N3904
10-602
- 0.5
4
OS75492
2N3904
10-602
NSN781
0.7
2
OS75492
2N3904
10-502
,NSB7881
0.7
4
OS75492
2N3904
10-502
NSB5881
FIgure 10. MM74C911 Segment Resistor Values for Various Displays (Vee = 5 V) ("Using Red LED Filter over
Display)
2-72
PART NO.
OISPLAY
HEIGHT (IN.)
NO. OF DIGITS
ORIVER
(RO=O)
TYPICAL RANGE OF
SEGMENT RESISTORS
NSA1298
0.110
9
OS75494
200-800 Q
300-1500 Q*
NSA1558
0.140
8
OS75494
150-700Q
150-1000Q*
NSN381
0.3
2
OS75492
5-50Q
NSB581
0.5
2
OS75492
5-50Q
0.5
6
OS75492
2N3904
5-40Q
0.7
2
OS75492
2N3904
5-30Q
NS5931
NSN781
Figure 11. MM74C9121MM74C917 Segment Resistor for Average Intensity lor Various Displays ('Using Red LED
Filter over Display)
0
<"
g
8
l-
ffi
a:
a:
=>
16
r-r-T:V
u
...
l-
=>
I-
=>
c
!::
'"is
24
~
/
32
40
0
--
""
/
A/
f'
<"
g
I-
ffi
a:
a:
=>
U
I
l-
~
l-
/
=>
c
l-
e;;
TJ=2S'C- -
is
I
1.0
2.0
3.0
4.0
DIGIT OUTPUT VOLTAGE (V)
5.0
t TLlF/6030-12
.
1.0
2.0
3.0
4.0
DIGIT OUTPUT VOLTAGE (V)
5.0
TL/F/6030·13
Figure 12. Typical Digit Driver Current vs. Output Voltage for (a) MM74C911 (b) MM74C912/MM74C917
where 100 is the maximum digit driver output current,
Vce is the power supply voltage, and IDI is the digit dri·
ver input current. .
,
As the digit driver output voltage VDO becomes larger,
the driver dissipates more power, thus the designer
should also ensure that the driver's dissipation is not
exceeded. Generally, the standard digit driver IC will
dissipate around V, watt. (See specific data sheets.) Dri·
ver power dissipation can be calculated by:
When a circuit design employs large segment currents,
the maximum dissipation should be calculated to
ensure that the power consumption of the controller or
digit driver is within the maximum limits. The display
controller power dissipation is:
where Voo and 10iG are the digit driver output voltage
and current. In a standard digit driver, one output will be
active all the time, but if discrete transistors ani used,
each transistor is turned on 25% of the time.'The ave·
rage power dissipation for each discrete transistor digit
driver is '/4 of the above equation.
Pc = S(lsEG)(Vee - VSEG)
where ISEG and VSEG are the peak segment current and
segment voltage, as previously determined; and S is the
maximum number of segments lit per digit. The maxi·
mum package dissipation for the controllers vs.
temperature is shown in Figure 13.
B. Common Anode LED Display
To gain an understanding of how segment current
affects the controllers power dissipation, Figure 14
plots average and peak LED segment current vs. pack·
age dissipation for both the MM74C911 and the
MM74C912/MM74C917. These typical curves are plotted
using the typical segment driver output currents and
voltages from Figure 8.
AithoughconnectingtheMM74C911/MM74C912/MM74C917
to common anode displays is somewhat more difficult
than to common cathode displays, it can be done.
These controllers still provide all the necessary timing
signals, but some extra buffering must be added to
ensure the correct logic levels and drive capability.
2·73
:J>
Z
~
en
......
(b)
(a)
~ 1.0
<:>
~
.75
:'"
0.5
;:: 1.5
Of
25
50
'"is
.""
1\
75
\ 1\
0;;
,
w
'"
'"Of
0
\
<:>
Of 0.25
-50 -25
2.0
z
\
0;;
'"isw
~
\
z
100 125
AMBIENT TEMPERATURE ('C)
0.5
-55 -25
0
25
50.
75
100 125
AMBIENT TEMPERATURE ('C)
TLiF/603."
TLlF/603,.15
Figure 13. MM74C9111MM74C912MM74C917 Maximum Power Dissipation for (a) Plastic "N" Package (b)
Ceramic "J" Package (Note TJ(MAX) = 125°C Maximum Junction Temperature)
2.0
/
~ 1.5
~
0.;
'"is
1.0
'"
Of
z
0.5
V
------5120
1/
1.5
o
/
~
~ 1.0
V
w
'"
;:!
~
V
z
0
0;;
2.0
is
w
:
~ 0.5
V
L
10/40 15/60 20/80 25/100
AVERAGE/PEAK SEGMENT CURRENT (rnA)
V
V
5/30 10/60 15190 20/120
TLiF16030·16
AVERAGE/PEAK SEGMENT CURRENT (rnA)
rLIF/6030·17
Figure 14. Typical Power Dissipation vs. Segment Current for (a) MM74C911 (b) MM74C912JMM74C917
C. Vacuum Fluorescent (VF) Displays
To drive common anode displays, the display
controller's segment outputs must be inverted and the
digit outputs must be current buffered. Figure 15 shows
a s'imple circuit to interface to most common anode displays. An 8-digit calculator digit driver IC, OS8871, is
used to drive the display segments. Segment resistors on .
the controller's segment outputs are not necessary but
may be necessary on the outputs of the OS8871 driver.'
The MM74C911/MM74C912/MM74C917 are not directly
capable of driving VF displays, but serve as a major
functional block to ease'driving 4-'or 6-digit displays.
The controllers provide the multiplex timing for this display, but the segment and digit outputs must be level
shifted, and a filament voltage must be applied.
In Figure 16, a OS8654 or similar device is used to translate the segment and digit voltages to 30V to drive the
segment plates and digit grids. The AC filament voltage
is derived from a separate low-voltage transformer
which is biased by a zener. Since there is no pull-down
in the OS8654, pull-down resistors must be added. The
exact anode and cathode voltages and the bias zener
will depend on the display used, but the basic circuit is
the same.
~
For higher current displays, the choice of digit driver
transistor is important as the digit current will depend
on how high the digit driver output of the display controller can pull up due to the emitter follower configuration. For good display brightness, a high gain medium
power transistor should be used.
2-74
l>
Z
5V
i\)
1
-
...
(4 PLACES)
NSB3BB,
_CE
WE
if
D1
l-Kl
0,
O-K'
03
f
......
Mr-
~
~
)
,..,.
C1I
SiiE
II
U. I
,
04
a
DiD
b
II
I
U
.
d
II
.
I
I
I.
OP
9
RSEG = 10
MM74C911
TO
7 - DO
Sa
S-9
Sb
S,
5-1
4-.
B
7
S
4
5
'-- VCC
3
,
3
,
OS8871
3-d
S.
SI_
,-,
8
S
4
5
1
11.-
I
Sg_
l-b
0-'
7
1
GNO
Sd
"
SOP
~
II
TL.IF/6030·18
Figure 15. MM74C911 to Common Anode LED Interface Using 9 Digit Driver
+5V
I
vcc
-
VCC, = 30V
.-
I
WE
, - IN3
K3
d _ IN4
'1-- INS
K,
AD -
Kl
' I - - INS
01-- IN7
oPI-- INB
MM74C9121
MM74C917
...
TO
OSE
SUE
~
a
OUTI
b - IN'
CE
A2 Al -
VACUUM FLORESCENT DISPLAY
INI
A
N
0
0
E
b
,
DUn
~ OUT3
d
8 OUT4
•
; OUTS
I
4 OUTS
0
OUT7
OUT8
OP
1
1
~
S
E
G
M
E
N
T
S
II II II II II II
, I. W. W. U. i,. W.
-
-~ -~
4
OS
IN10 UT1
02 - B
04
IN'
IN3
01 - A
03
IN4
02
INS
*
(ALL RESISTORS - 100Kg)
D1
:=J h
AC
INPUT
--
DIGIT GRIDS
05
GNO
-~
~ 1 1 nn
100Kg
(8 PLACES)
03 - C
DP
-~
--,
04 - 0
DO -
-~
Dun
OUT3
OUT4
OS8654
OUTS
OUTS
100 Kg
(6 PLACES)
-=
~2= 30V
INS
CATHODE
FILAMENT
16V
*
Figure 16. MM74C9121MM74C917 to Vacuum Fluorescent Display Interface
2-75
TLIFI 6030·19
Ii;
N
Z
2 (6800 system clock) and the VMA
(Valid Memory Access) control signal. When these
inputs equal the corresponding Tn inputs, the output
goes low. The 6800 Riw signal is connected to the WE.
E. Interfacing To The INS8060llNS8070
C_ Interfacing to the NSC800
Like the 6800, the INS8060/8070 series of microprocessors don't have any separate I/O addressing, so the
MM74C911/MM74C912/MM74C917 must be memory
addressed, but unlike the 6800 both the INS8070 series
and the INS8060 have separate read/write strobes,
which can simplify interfacing the display controllers.
Figure 31 illustrates a typical INS8060 interface. The
NWDS (write enable) is directly connected to the
MM74C912s WE input and the DM8131 provides the
address decoding for the controller. The INS8060 has
only 12 address bits (unless using paged addressing) so
bits ~-A11 are decoded by the comparator.
The NSC800 has very different timing because the lower
eight address bits and the data bus are multiplexed. But
when connecting the display controllers as I/O ports,
the interface is only sl,ightly different from the INS8080
design. When an I/O instruction is executed, the port
address that appears on AO-A7 is duplicated on
A8-A15, and this address can be used directly. The controller WE input must be decoded from a WR (write
enable) and 10iM (I/O or memory enable) as shown in
Figure 29. Note that since the NSC800 is a CMOS microprocessor, no pull-up resistors are needed.
Figure 29 uses address bit A15 which is equivalent to bit
A7 on the previous examples. As wit~ the previous
examples, if more address decoding is required, either
gates or decoders could be connected to the CE input.
The INS8070 series microprocessor has the identical
NWDS signal but has 16 address bits. Thus Figure 31
would connect the A10-A15 address bits to the DM8131.
TLlF16030·28
Figure 26. MM74C911/MM74C912/MM74C917 Timing Diagram (See data sheets for numbers)
2-83
5V
f
IIOW
5V
I
vcc
WE
\
/
5V
I t
SEGMENT
OUTPUTS
A7
ADDRESS
BUS
CE
AI
K2
AD
Kl
DJij
MM74C911
,
07
-\
g
05
DIOIT
OUTPUTS
I
04
•d
03
02
II
U.
II
U.
DIGIT DRIVERS
-v'
c
01
II
U.
,i''.
~
DP
06
INS8080
DATA
BUS
fill!
LED DISPLAY
b
DO
-l
PORT ADDRESS = OXXX XXAB (BINARY)
•
~~~~'ll'E xDlGrrD~~lic\RrD~~~)AB
1
Vcc
~
TLIFI6030-29
ALL INPUT RESISTORS 5-1DK
5V
N
......
WR
U'I
LED DISPLAY
,-;;
ID/M-----'
SEGMENT
OUTPUTS
" L'.
" W.
" ,-ii
U.
_".
CE
NSCBOO [ AI5
ADDRESS
A9 ---------~ K2
BUS
AB _ _ _ _ _ _ _ _ _~
KI
IllIl
m
MM74C911
-=
OP
07
06
DIGIT
OUTPUTS
05
0IG
04
NSC800
DATA BUS
L - - - -_ ' " " . .
03
02
01
.J
PORT ADDRESS = DXXX XXAB (BINARYI
~~~ED~~I~ sJ:.~~i (~~~~ I~ND AB
DO
TI
74C911
~
IF/6030·31
Figure 29. NSCBOO Interface to MM74C911
5V
I
VMA
AI5
AI4
AI3
AI2
<1>2
5V
-
B6
--
B5
VCC
B4
B3
B2
BI
---
-"-:-
-=
OMBI31 OUT
T7
T6
li
5V
I
cE
LED DISPLAY
VCC
T5
-\
'/
SEGMENT
OUTPUTS
T4
T3
T2
TI
GNO
-=l=-
~C
010
WE
R/W
SUE
MM74C911
61100
DATA
BUS
g
05
f
04
•
03
d
02
c
01
b
DO
•
5V
.1.
1
K2
" U.
"
"
L!.
".
1
DP
06
Ii
U.
.
-\
f
. DIGIT
OUTPUTS
DIGIT DRIVER
,
PORT AOORESS=EXXA (HEXI
ADDRESS EXXA (HEXI
(WHERE X=OON'T CARE AND
"A" IS DIGIT SELECT (XXDO-XX111
Kl
GNO
~
5V,
AI
$
TLIF/6030·32
AD
Figure 30. MM74C911 to 6BOO Microprocessor Interface
2-85
5V
I
A10 _
A9
--
-
A8
A7
A6
-
,-
87
B6
B5
B'
83
B2
A11--
81
5V
T6
.-
..,-
Vee
T7
T5
TO
OUT
T3
5V
5V
DM8131
1
I
LED DISPLAY
tiE
T2
T1
SEGMENT
OUTPUTS
GNo
~
NWDS--
WE
A2---
K3
oSE
A1---
K2
SoE
AO---
K1
MM74C912
5V--DIGIT
OUTPUTS
OP
03---
0
02---
e
01---
B
00---
A
5V----
M
,hi
a
\
vi
if
II
II
II
II
i,
W. L.!. !...J. W. W. !...!.
LED DIGIT DRIVER
PORT ADDRESS =1110 11XX XABe (BINARY)
~~~~RM DI~?NeEm (~~g-lD1)
-b
TLIF16030033
Figure 31. MM74C9121MM74C917 to INS8060 (SC/MP) Interface
/
2-86
F. Multiple Display Controllers
In systems where multiple display controllers are to be
used, the simple addressing schemes of the previous
examples may prove to be too costly in 1/0 capabilities,
so some extra decoding is necessary to derive the CE
signals. A typical method uses a 2-4 line decoder or a
3-8 line decoder. Where the total time from a stable
address to the write pulse goes inactive is ~ 1,..S, a
CMOS decoder such as the MM74C42 or MM74C154 can
be used, but if faster accessing is required, their LS'
equivalents should be employed.
a memory location. This extra writing and "book·
keeping" software can be eliminated by addressing the
MM74C911/MM74C912/MM74C917 over existing RAM.
When data is written to the controller, it could also be
stored in RAM simultaneously and can be read later by
the CPU.
Figure 31 shows a simple example of this using an
MM74C912 controller and two MM2114 1K x 4 memory
chips. A DM74LS30 is used to detect when the last eight
bytes of this memory is being accessed and enables the
controller display. Thus, the last eight bytes of the RAM
contains a duplicate copy of what the display controller is
displaying.
Figure 32 shows a typical implementation of a 16-digit
display using half of a DM74LS139 decoder to provide
the CE signals for each controller.
IX. Conclusion
G. Making The MM74C9111MM74C9121
MM74C917 Look Like RAM
All three controllers provide simple and inexpensive inter·
faces to multiplexed multidigit displays. These devices
are particularly. well suited to microprocessor en·
vironments, but any type_of CMOS compatible control
hardware can be used. The MM74C911/MM74C9121
MM74C917 can most easily drive common anode dis·
plays. By"providing most of the multiplex circuitry into one.
low-cost integrated circuit, the burden of designing
discrete multiplexing has been eliminated.
So far, the discussion of addressing the controllers has
been to separate the devices from memory, but there
are certain advantages to not doing this. In many
instances, microprocessor software requirements are
such that data outputted to the controller also must be
remembered by the microprocessor for later use. Since
data cannot be read from the display controllers, the
processor must also write the data in a spare register or
" " " 'I"
U.O.U.
I.
, ,,., ., .,
i,'.W.L.!.
" " W.• • -._._.-.
" " " ".
" " U.W.W.W
I
I
~t
~t
SEGMENT & OIGIT
SEGMENT & DIGIT
OUTPUTS
OUTPUTS
MM74C911
a,b,t,d
B. I, g, OP
CPU DATA
BUS 00-07
-
WE CE
11
AD
1
a.b,c,d
B,
I, g. OP
Kl
K2
.
~~
SEGMENT & DIGIT
OUTPUTS
~t
SEGMENT & DIGIT
OUTPUTS
MM14C911
MM74C911
-
i r II·
Al
CPU
ADDRESS
BUS
Kl K2
I
WE CE
i'r II
a,b,c,d
B, I, g, OP
Kl K2
i'r II
I1
MM74C911
WE CE
a,b.c.d
B,f,g,OP
it
Kl K2
WECE
11
1
1
1J~DM74lS139
A2 - A
lYO 1- ....
A3 - B
lYl
AB
-
lY2
lGl
lY3
CPU WRITE
ENABLE
(ACTIVE LOWI
TlIF16030·34
Figure 32_ Multi·Digit Array
2-87
MM2114
A9
A9
A8
A8
A7
A7
A6
A6
A5
A5
A4
A3
A'
A3
A2
A2
Al
Al
AD
AD
CE
C-E
wE
WE
MM2114
DO 01 02 03
DO 01 02 D3
A9
A8
A7
A6
A5
A.
A3
A2
Al
AD
CE
07
06
OM74LS30
05
D.
03
02
D1
DO
WE
-f'---f-
Kl
K2
K3
SEGMENT
&
DIGIT
OUTPUTS
OSE
SliE
'- W.
~
6-DIGIT DISPLAY
bI
Fi,
MM74C912
DP
9
I
,
d
I
,
c
.
b
TLIFJ6030·35
Figure 33_ Display Controller Mapped Over RAM (5-10 KQ Pull-up Resistors may be needed on MM74C912
inputs)
2-88
National Semiconductor
Application Note 303
Kenneth Karakotsios
February 1984
He-MOS Power
Dissipation
If there is one single characteristic that justifies the existence of CMOS, it is low power dissipation. In the quiescent
state, high-speed CMOS draws five to seven orders of magnitude less power than the equivalent LSTTL function.
When switching, the amount of power dissipated by both
metal gate and high-speed silicon gate CMOS is directly
proportional to the operating frequency of the device. This is
because the higher the operating frequency, the more often
the device is being switched. Since each transition requires
power, power consumption increases with frequency.
First, one will find a description of the causes of power consumption in HC-CMOS and LSTTL applications. Next will
follow a comparison of MMS4HC/MM74HC to LSTTL power
dissipation. Finally, the maximum ratings for power dissipation imposed by the device package ",-ill be discussed.
To obtain the quiescent power consumption for any CMOS
device, simply multiply Icc by the supply voltage:
Poc=lccVcc
Sample calculations show that at room temperature the
maximum power dissipation of gate, buffer, and MSI circuits
at Vcc= 6V are 10 p.W, 20 p.W, and 40 p.W, respectively.
Dynamic Power Consumption
Dynamic power consumption is basically the result of charging and discharging capacitances. It can be broken down
into three fundamental components, which are:
1. Load capacitance transient dissipation
2. Internal capacitance transient dissipation
3. Current spiking
d~ring
switching.
Quiescent Power Consumption
Load Capacitance Transient Dissipation
Ideally, when a CMOS integrated circuit is not switching,
there should be no DC current paths from Vce to ground,
and the device should not draw any supply current at all.
However, due to the inherent nature of semiconductors, a
small amount of leakage current flows across all reverse-biased diode junctions on the integrated circuit. These leakages are caused by thermally-generated charge carriers in
the diode area. As the temperature of the diode increases,
so do the number of these unwanted charge carriers, hence
leakage current increases.
The first contributor to power consumption is the charging
and discharging of external load capacitances. Figure 1 is a
schematic diagram of a simple CMOS inverter driving a capacitive load. A simple expression for power dissipation as a
function of load capacitance can be derived starting with:
Leakage cllrrent is specified for all CMOS devices as Icc.
This is the DC current that flows from Vcc to ground when
_ all inputs are held at either Vcc or ground, and all outputs
are open. This is known as the quiescent state.
QL =CLVCC
where CL is the load capacitance, and QL is the charge on
the capacitor. If both sides of the equation are divided by
the time required to charge and discharge the capacitor
(one period, T, of the input signal), we obtain:
~L =
CLVCC
(~)
Vee
For the MMS4HC/MM74HC family, Icc is specified at ambient temperatures (TA) of 2S"C, 8S"C, and 12S"C. There are
three different specifications at each temperature, depending on the complexity of the device. The number of diode
junctions grows with circuit compleXity, thereby increasing
the leakage current. The worst case Icc specifications for
the MMS4HC/MM74HC family are summarized in Table I. In
addition, it should be noted that the maximum Icc current
will decrease as the temperature goes below 2S"C.
TLlLl5021-1
TABLE I. Supply Current (Icel for MMS4HC/MM74HC
Specified at VCC = 6V
TA
Gate
Buffer
MSI
Unit
2S"C
8S"C
12S"C
2.0
20
40
4.0
40
80
8.0
80
160
p.A
p.A
p.A
FIGURE-1. Simple CMOS Inverter Driving a
Capacitive External Load
Since charge per unit time is current (QL/T = I) and the inverse of the period of a waveform is frequency (1 IT = f):
IL =CLVccf
To find the _power dissipation, both sides of the equation
must be multiplied by the supply voltage (P=VI), yielding:
PL =CL Vcc2f
2-89
Mr-------------------------------------------------------~--------------------~
One note of caution is in order. If all the outputs of a device
At this point, it may be assumed that different parts of the
~
are not switching at the same frequency, then the power
internal circuitry are operating at different frequencies. Alconsumption must be calculated at the proper frequency for
though this is true, each part of the circuit has a fixed freeach output:
quency relationship between it and the rest of the device.
Thus, one value of an effective CI can be used to compute
PL=Vee2(CL1 f 1+ CL2f2+'" +CLnfn)'
the internal power dissipation at any frequency. More will be
Examples of devices for which this may apply are: counters,
said about this shortly.
dual flip-flops with independent clocks, and other integrated
'circuits containing dual, triple, etc., independent circuits.
Current Spiking During Switching
Z
«
The final contributor to power consumption is currentspik·
ing during switching. While the input to a gate is making a
transition between logic levels, both the P- and N-channel
transistors are turned partially on. This creates a low imped·
ance path for supply current to flow from Vee to ground, as
illustrated in Figure 3.
Internal Capacitance Transient Dissipation '
Internal capacitance transient dissipation is similar to load
capacitance dissipation, except that the internal parasitic
"on-chip" capacitance is being charged and discharged.
Figure 2 is a diagram of the parasitic nodal capacitances
associated with two CMOS inverters.
.
For fast input rise and fall times (shorter than 50 ns for the
MM54HC/MM74HC family), the resulting power consumption is frequency dependent. This is due to the fact that the
more often a device is switched, the more often the input is
situated between logic levels, causing both transistors to be
partially turned on. Since this power 'consumption is proportional to input frequency and specific to a given device in
any application, as is CI, it can be combined with CI. The
resulting term is called "CPO," the no-load power dissipation
capacitance. It is specified for every MM54HC/MM74HC
device. in the AC Electrical Characteristic seption of each
data sheet.
It should be noted that as input rise and fall times become
longer, the switching current power dissipation becomes
more dependent on the amount of time that both the p. and
N·channel transistors are turned on, and less related to Cpo
as specified in the data sheets. Figure 4 is a representation
of the effective value of CPO as input rise and fall times
increase for the MM54HC/MM74HCOe, MM54HCI
MM74HC139, and MM54HC/MM74HC390. To get a fair
comparison between the three curves, each is divided by
the value of CPO for the particular device with fast input rise
and fall times. This is represented by "CPOO," the value of
Cpo specified in the data sheets for each part. This comparison appears in Figure 5. CPO remains constant for input rise
and fall times up to about 20 ns, after which it rises, approaching a linear slope of 1. The graphs do not all reach a
slope of 1 at the same time because of necessary differ·
ences in circuit design for each part. The MM54HCI
MM74HCOe exhibits the greatest change in CPO, while the
MM54HC/MM74HC139 shows less of an increase in Cpo at
Vee
TL/L/5021-2
FIGURE 2. Parasitic Internal Capacitances
Associated with Two Inverters
C1 and C2 are capacitances associated with the overlap of
the gate area and the source and channel regions of the Pand N-channel transistors, respectively. C3 is due to the'
overlap of the gate and source (output), and is known as the
Miller capacitance. C4 and Cs are capacitances of the para·
sitic diodes from the output to Vee and ground, respectively.
Thus the total internal capacitance seen by inverter 1 driving inverter 2 is:
CI=C1 +C2+2C3+C4+CS
Since an internal capacitance may be treated identically to
an external load capacitor for power consumption calculations, the same equation may be used:
PI=CIVee2f
Vee
Vee
Rp·eHANNEL
INPUT
0--"'"
GNDVOUr>GND
OUTPUT
RN·eHANNEL
TL/L/5021-3
FIGURE 3. Equivalent schematic of a CMOS Inverter whose input Is between logic levels
2·90
TL/L/5021-4
any given frequency. Thus, the power dissipation for most of
the parts in the MM54HC/MM74HC family will fall within
these two curves. One notable exception is the MM54HCI
MM74HCU04.
This equation can be used to compute the total power consumption of any MM54HC/MM74HC device, as well as any
other CMOS device, at any operating frequency. It includes
both DC and AC contributions to power usage. CPO and icc
are supplied in each data sheet for the particular device,
and Vee and f are determined by the particular application.
Comparing HC·CMOS to LSTTL
Although power consumption is somewhat dependent on
frequency in LSTTL devices, the majority 01 power dissipated below 1 MHz is due to quiescent supply current. lSTTl
contains many resistive paths from Vee to ground, and even
when it is not switching, it draws several orders of magnitude greater supply current than HC-CMOS. Figure 6 is a
bar graph comparison of quiescent power requirements
(Veel x (Ieel between lSTTl and HC-CMOS devices.
The reduction in CMOS power consumption as compared to
lSTTl devices is illustrated in Figures 1 and 8. These
graphs are comparisons of the typical supply current (Ieel
required for equivalent functions in MM54HCI,MM74HC,
MM54HC/MM74C, CD4000, and 54lS174lS logic families.
The currents were measured at room temperature (25'C)
with a supply voltage of 5V.
105pF .--,---,---,---,----,
104 pF f---i--j.
-+--¥-......-I
10 3 pF f--f--f-...-.-,lS-hIL---(
'10pF
t
CPO L - - _ L - _ L - _ L - - _ L - - - I
1ns 10ns lOOns 1,...5
10",5
INPUT RISE ANO FALL TIME
TL/L/S021-5
FIGURE 4. Comparison of Typical CPO for
MM54HC/MM74HC08, MM54HC/MM74HC139
MM54HC/MM74HC390 as a Function of
Input Rise and Fall Time.
trlse=tfall, Vcc=5V, TA=25'C
Figure 1 represents the supply current required for a quad
NAND gate with one gate in the package switching. The
MM54HC/MM74l:iC family draws slightly more supply current than the 54CI74C and CD4000 series. This is mainly
due to the large size of the output buffers necessary to
source and sink currents characteristic of the lSTTl family.
Other reasons include processing differences and the larger
internal circuitry required to drive the output buffers at high
frequencies. The frequency at which the CMOS device
draws as much power as the lSTTl device, known as the
power cross-over·frequency, is about 20 MHz,
104 . - - - , - - - , - - , - - , - - - ,
103
1--!--+--+--+--71
100
In Figure 8, which is a comparison of equivalent flip-flops
(174) and shift registers (164) from the different logic families, the power cross·over frequency again occurs at about
20 MHz.
10
11 f----I-""4'=--f;--t-----l
CPO
CPOo
L--_L--,-L-_L--::.L-~
1ns
10ns
lOOns
1,...5
lO/Js
100.1.15
.IP
I
I
INPUT RISE AND FALL TIME
MM74HC~0.003"W
TL/LlS021-6
FIGURE 5. Normalized Effective CPO (Typical)
for Slow Input Rise and Fall Times.
trise=tfall, Vcc=5V, TA=25'C
GATES
LSTTL~8mW
MM74HC~0.005"W
FLlp·FLOPS
ILSTTL~20mW
Inputs that do not pull all the way to Vee or ground can also
1-_ _-'
cause an increase in power consumption, for the same reason given for slow rise and fall times If the input voltage is
MSI LOGIC
MM74HC~0.25"W
between the minimum input high volt~ge and Vee, then the (C°'l:Ji~~, r-------------------,
input N-channel transistor will have a low impedance (Le., OCTALS. ETC.) r-______L_S_TT_L_~_50_.1_00_m_w_ _ _ _ _ ___'.
be "turned on") as expected, but the P-channel transistor
will not be completely turned off. Similarly, if the input is
20
40
60
80
100
between ground and the maximum input low voltage, the PPOWER CONSUMPTION (MILLIWATTS)
channel transistor will be fully on and the N-channel transis·
TL/L/S021-7
tor will be partially on. In either case, a resistive path from
Vee to ground will occur, resulting in an increase in power
FIGURE 6. High Speed CMOS (HC-CMOS) vs. LSTTL
consumption.
Quiescent Power Consumption
Combining all the derived equations, we arrive at the
following:
PTOTAL = (CL + Cpo)Vee2f + leeVee
I
2·91
The power cross-over frequency increases as circuit complexity increases. There are two major reasons for this.
First, having more devices on an LSTTL integrated circuit
means that more resistive paths between Vee and ground
will occur, and more quiescent current will be required. In a
CMOS integrated circuit. although the supply leakage current will increase, it is of such a small magnitude (nanoAmps
per device) that there will be very little increase in total power consumption.
Now consider the LSTTL system. Again. the power consumed in the first block is P1. The amount of power dissipated in the second block is something les~ than P1, but greater than (P1 )/2. For simplicity, we can assume the best case,
that P2=(P1)/2. The power consumption for all system
blocks operating at frequencies Fmax/2 and below will be
dominated by quiescent current, which will not change with
frequency. The power used by blocks 3 through n will be
approximately equal to the power dissipated by block 2,
(P1)/2. The total power consumed in the LSTTL system is:
PTOTAL =(P1+ (P1)/2+ (P1)/2+ ... +(P1)/2
10mA
PTOTAL =P1 + (N-1)(P1)I2
and for n>2, PTOTAL>2(P1)
c
..~
1mA
....z~
100~A
Thus, an LSTTL system will draw more power than an
equivalent HC-CMOS system.
==
0:
au
.
0:
0:'
::>
...~
::>
en
100kHz
1MHz
10MHz
100MHz
INPUT FREQUENCY
TL/L/S021-8
FIGURE 7. Supply Current vs.lnput Frequency
for Equivalent NAND Gates
100mA
,----r-::-::--::-:-:-:-r--,---,
10mA
1===t:=:::::4==;j?:L~
....
i5
..
~
FIGURE 9. Comparison of Equivalent CMOS
and LSTTL Systems
lmA
This effect is further illustrated in Figure 10. An arbitrary
system is composed of 200 gates, 150 counters, and 150
full adders, with 50 pF loads on all of the outputs. The supply voltage is 5V, and the system is at room temperature.
For this system, the worst case power consumption for
CMOS is about an order of magnitude lower than the typical
LSTTL power requirements. Thus, as system complexity increases, CMOS will save more power.
::>
>-
~ 100~A f---~IY'---+--+-----1
::>
en
lO~A 19'~-r----+---+------1
_ _-L_~
1 MHz
10MHz 100 MHz
1~AL---L-_~
10kHz
100kHz
, FREQUENCY
TL/L/S021-9
FIGURE
iI. Supply Current vs. Frequency
Secondly, as system complel(ity increases, the precentage
of the total system operating at the maximum frequency
tends to decrease. Figure 9 shows block diagrams of a
CMOS and an equivalent LSTTL system. In this abstract
system, there is a block of parts operating at the maximum
frequency (Fmaxl, a block operating at half Fmax, a block
operating at one quarter Fmax, and so on. Let us call the
power consumed in the first section P1. In a CMOS system,
since power consumption is directly proportional to the operating frequency, the amount of power consumed by the
second block will be (P1)/2, and the amount used in the
third section will be (P1)/4. If the power consumed over a
large number of blocks is summed up, we obtain:
P'-OTAL =P1+(P1)/2+(P1)/4+ ... +(P1)/(2n - 1)
and PTOTAL";2(P1)
2·92
Maximum Power Dissipation Limits
It is important to take into consideration the maximum power dissipation limits imposed on a device by the package
when designing with. high-speed CMOS. Both the plastic
and ceramic packages can dissipate up to 500 mW. Although this limit will rarely be reached in typical high·speed
applications, the MM54HC/MM74HC family has such large
output current source and sink capabilities that' driving a resistive load could possibly take a device to the 500 mW
limit. This maximum power dissipation rating should be derated by -12 mW
starting at 65'C for the plastiC package and 1Op'C for the ceramic package. This is illustrated in
Figures 11 and 12. Thus, if a device in a plastic package is
operating at 70'C, then the maximum power dissipation rating would be 500 mW - (70'C-65'C) (12 mWrC)=44
mW. Note that the .maximum ambient temperature is 85'C
for plastic packages and 125'C for ceramic packages.
rc,
lkr-----~--_r--~--,_~
LSTTL SYSTEM:
IA
WORST CASE
TYPICAL
AV
'--IL#~A------l
100
~
!ffi
SYY~TEM:
10 HIGH·SPEED CMOS
WORST CASE
TYPICAL
1
I
:i
It.-
g
~
~
::i
<>
'"~
'""-
F=±LF~=r-~-t--i
I
-1HE SYSTEMS
~ 100m f---I __-+__-¥-V'-- ' "CONSIST OF
V
10m 1----1---.('
. /
200 GATES
150 COUNTERS
150 FULL ADDERS
..
III
~
CL=50pF. ALL OUTPUTS
lm~~~~·~-~~~~--~~
100
1k
10k lOOk
1M
:f
10M 100M
700
600
SLOPE = -12mWI"C
r,I
500
400
'\
300
'\
200
100
25
50
75
100
125
150
AMBIENT TEMPERATURE I'C)-
TL/lI5021-11
TlIL/5021-13
FIGURE 10. System Power vs. Frequency
MMHC74HC vs. LSTTL
FIGURE 12. Ceramic Package (MM54HC)
High Temperature Power Derating
for MM54HC/MM74HC Family
.,--,c-r...,--,--,-.,-.,-""...,
f-I--H--I-+-+-+-+-+--+-+--l
BOO f-I--H--I-+-+-+-+-+--+-+--l
1DOD
Summary
900
The MM54HC/MM74HC high·speed silicon gate CMOS
family has quiescent (standby) power consumption five to
seven orders of magnitude lower than the equivalent LSTTL
function. At high frequencies (30 MHz and above), both
families consume a similar amount of power for very simple
systems. However, as system complexity increases, HC·
CMOS uses much less power than LSTTL To keep power
consumption low, input rise and fall times should be fast
(less than 50 to 100 ns) and inputs should swing all the way
to Vee and ground.
H---IH-+-+-+--+--j-HH-l
600 H---IH-+-+-+--+-+--~-+-l
SLOPE=-12mW/'C
500
400 I--I--H--I-+H~4-+--++--l
t-+-+-+-l-+"1\...--t-c1/1t-t--t-+-i
~~~ t~=;~=;~=!~I\~~jt!jj
200 r100
BOD
o
FREOUENCY OF SYSTEM (Hz)
700
1000
900
H--IH--++++-+-+-H--1
There is an easy-to-use equation to compute the power
consumption of any He-CMOS device in any application:
15 25 35 45 55 65 75 85 95105115
AMBIENT TEMPERATURE ('C) TL/lI5021-12
FIGURE 11. Plastic Package (MM74HC)
High Temperature Power Derating
for MM54HC/MM74HC Family
2-93
P'-OTAL = (CL + Cpo)Vec2f+ leeVee
The maximum power dissipation rating is 500 mW per package at room temperature, and must be derated as temperature increases.
(;)
..~ High-Spee~ CMOS
Z
-
-
W
....
o
5102
,:-,'
~
FIGURE 3. P - Well Oxidation, Thermally Grown Silicon
Dioxide Layer Over P- Well Area
FIGURE 4. P + Mask and Formation of Low Resistance P + Type Pockets In
P - Well and N·Substrate
'
•
TULl5044-2
FIGURE 5. P + Oxidation, Thermally Grown Silicon
Dioxide Layer Over P+ Type Pockets,
FIGURE 6'. N + Mask and Formation of Low Resistance N + Type Pockets In
P- Well and N·Substrate
TLlL/5044-3
FIGURE 7. N + Oxidation, Thermally Grown Silicon
Dioxide Layer Over N + Type Pockets
2-95
FIGURE 8. Composite Mask and Openings to N· and P·Channel Devices
FIGURE 9. Gate Oxidation, Thermally Grown Silicon Dioxide Layer Over N· and
P·Channel Devices
TL/L/5044-4
FIGURE 10. Contact Mask and Openings to N· and P-Chanriel Devices
FIGURE 11. Metallization, Metal Mask, Resulting In Gate Metat and Metal Interconnects
TUL/5044-5
FIGURE 12. Passivation Oxide, DepOSited Silicon Dioxide Over Entire Ole Surface
2·96
~----------------------~--------------------------~~
z
Silicon-Gate CMOS Processing
The silicon-gate CMOS process starts with the same two
steps as the metal-gate process, yielding an N - substrate
with an ion-implanted P- well (Figures 13 and 14). That,
however, is where the similarity ends. Next, the initial oxide
is stripped, and another layer of oxide, called pad oxide, is
thermally grown. Also, a layer of silicon nitride is deposited
across the surface of the wafer (Figure 15). The nitride prevents oxide growth on the areas it covers. Thus, in Figure
16, the nitride is etched away wherever fieid oxide is to be
grown. The field oxide is a very thick layer of oxide, and it is
grown everywhere except in the transistor regions (Figure
17). As an oxide grows in silicon, it consumes the silicon
substrate beneath it and combines it with ambient oxygen to
produce silicon dioxide. Growth of this very thick oxide
causes the oxide to be recessed below the surface of the
silicon substrate by a significant amount. A recessed field
oxide eliminates the need for guard ring diffusions, because
current cannot flow through the field oxide, which completely isolates each transistor from every other transistor.
The next step is to deposit a layer of polycrystalline silicon,
also called poly, which will form both the gate areas and a
second layer of interconnect (Figure 18). The poly is then
etched, and any poly remaining becomes a gate if it is over
gate oxide, and interconnect if it is over field oxide. A new
layer of oxide is grown over the poly, which will act as an
insulator between the poly and the metal interconnect (Rgure 18). The poly over the transistor areas is not as wide as
the gate oxide. This allows the source and drain diffusions
to be ion implanted through the gate oxide. The poly.gate
itself, along with the field oxide, is used as a mask for implantation. Therefore, the source and drain implants will automatically be aligned to the gate poly, which is what makes
this process a self-aligned gate process (Figure 2{}).
hence the diode area reduction results in a significantly reduced parasitic capacitance in silicon-gate CMOS.
Another origin of unwanted capacitance is the area where
the gate overlaps the source and drain regions (C4)" The
overlap is much larger in metal-gate processing than insilicon-gate CMOS. This is due to the fact that the metal-gate
must be made wider than the channel width to allow for
alignment tolerances. In silicon-gate processing, since the
gate acts as the mask for the iOll implantation of the source
and drain regions, there is no alignment error, which results
in greatly reduced overlap.
How does the use of polysilicon gates increase the gain of a
MOSFET? Polysilicon may be etched to finer line widths
than metal, permitting the fabrication of transistors with
shorter gate lengths. The equation that describes the gain
of a MOSFET is shown below:
I = (Beta) (Width) [(Gate Voltage)-(ThresholdVoltage)12
2 (Length)
.
Thus, a decrease in gate length will cause an increase in
current drive capability. This, in turn, will allow the transistor
to charge a capacitance more rap,idly, therefore increasing
the gain of the transistor. Also, the gate oxide is thinner for
the silicon-gate CMOS process. A thinner gate oxide increases the Beta term in the equation, which further increases gain. Finally, although it is not apparent from the
processing cross sections, the transistor threshold (turn on)
voltage is lower. This is accomplished by the use of ion
implants to adjust the threshold.
There is one more advantage of silicon-gata processing that
should be noted: the polysilicon provides for an additional
layer of interconnect. This allows three levels of interconnect, which are metal, polysi!icon, and the N+ and P+ ionimplanted regions. Having these three levels helps to keep.
the die area down, since much die area is usually taken up
by interconnection.
When all these advantages are summed up, the result is a
CMOS technology that produces devices as fast as the
equivalent LSTTL device. Figure 25 illustrates a comparison
between the MM74HCOO buffered NAND gate and the
MM74COO, CD4011B, and DM74LSOO NAND gates. The
MM74HCOO is about an order of magnitude faster than the
CD4011B buffered NAND gate, and about 5 times faster
than the unbuffered MM74COO, at 15 pF. As .load capacitance increases, the speed differential between metal-gate
and silicon-gate CMOS increases, with the MM74HCOO operating as fast as the DM74S00 at any load capaCitance.
Figure 21 illustrates the steps of cutting contacts into the
insulating layer of oxide, so the metal may be connected to
gate and field poly, as well as to source and drain implants.
A layer of metal is deposited across the entire wafer, and is
etched to produce the desired interconnection. Finally, as in
metal-gate processing, an insulating layer of oxide is deposited onto the wafer (Figure 22).
Advantages of Silicon-Gate Processing
There are three major ways in which Silicon-gate processing
reduces parasitic capacitance: recessed field oxide, lower
gate overlap capacitance, and shallower junction depths.
Figures 23 and 24 are cross sections of metal gate and
silicon gate CMOS circuits, respectively. These figures show
the parasitic on-chip capacitances (Cl through C4) for each
type of process.
Summary
Polycrystalline Silicon-gate CMOS has many advantages
over metal-gate CMOS. It is faster because on-Chip parasitiC
capacitances are reduced and transistor gains are increased. This is due mainly to a recessed field oxide and a
self-aligned gate process. Transistor gains are increased by
decreasing transistor lengths and threshold voltages, and
increasing beta. Polysilicon also allows for an extra layer of
interconnect, which helps to keep die area down.
The N + and P + source and drain regions, as well as guard
ring regions, in the metal-gate process, have two capacitances associated with them: periphery and area capacitances (C2 and Cl). These capacitances are associated
with the diode junctions between the P + regions and the
N- substrate, as well as the N+ regions and P- well. The
finer line widths of silicon-gate CMOS, coupled with the
shallower junction depths, act to decrease the size of these
parasitic diodes. Capacitance is proportional to diode area,
2·97
c,.,
....
o
-
or--------------------------------------------------------------------------,
CW)
z
0(
FIGURE 13. Initial Oxidation, Thermally Grown Silicon
Dioxide on N - Silicon Subatrate
.
TLlLl5044-6
FIGURE 14.lon-lmplantec:l P- Tub In Which N-Channel
Devlcea Will Be Located
PAD OXIDE
NITRIDE
FIGURE 15. Initial Oxide 18 Stripped, Pad Oxide la Thermally Grown, and a Layer of SilIcon Nitride la Depoalted Acroaa the Surface of the Wafer
Tl/Ll5044-15
TL/Ll5044-16
. FIGURE 16. Nltrldela Stripped In Areaa Where Field Oxide la to be Grown. Ai-eaa
Covered by Nitride Will Become Tranalator Area
2·98
r-----------------------------------------------------------------,~
Z
....oW
TLlLl5044-B
FIGURE 17. Field Oxide Is Thermally Grown. The Nitride
Acts as a Barrier to Oxlde'Growth
FIGURE 18. Nitride Is Stripped, Pad Oxide Is Stripped Over Transistor Areas and a
Thin Gate Oxide Is Grown Polycrystalline Silicon Is Deposited
TLlLl5044-9
FIGURE 19. Polysillcon Layer Is Etched to Provide Gate and Interconnect Poly Areas.
New Layer of Oxidation Is Grown
2-99
o ,--------------------------------------------------------------------------,
....
C'?
P+SOURCE
Z
AND DRAIN
1.0
1.0
2.0
3.0
4.0
5.0
INPUT VOLTAGE
(a)
TL/F/SOS2-4
5.0
VCC='5V
"'~""
4.0
'LSCQ
...~30 b.
-
w
~
.
...E2.0
.
...=>
M
(-----'
~ TA=125"C
r--
TA=25"C
I-TA=-55"C
1.0
1.0
2.0
3.0
INPUT VOLTAGE
(b)
4.0
5.0
TL/F/SOS2-S
FIGURE 3. Input/Output Transfer Characteristics for (a)
'HCOO and (b) 'LSOO Nand Gate
POWER SUPPLY VOLTAGE (VI
TL/F/SOS2-3
FIGURE 2_ Worst Case Input and Output Voltages Over
Operating Supply Range for "HC" and "LS" Logic
The input and output logic voltages and their behavior with
temperature variation is determined by the input to output
transfer function of the logic circuit. Figure 3a shows the
transfer function of the MM54HCOO/MM74HCOO NAND
gate. As can be seen, the N~ND gate has Vee and ground
output levels and a very sharp transition at about 2.25V.
Thus, good noise immunity is achieved, since input noise of
a volt or two will not appear on the output. The transition
point is also very stable with temperature, drifting typically
50 or so millivolts over the entire temperature range. As a
comparison, the.transfer function for a 54LS00174LSOO is
plotted in Figure 3b. LSTTL output transitions at about 1.1 V
and the transition region varies several hundred millivolts
over the temperature range. Also, since the transition region
is closer to the low logic level, less ground noise can be .
tolerated on the input.
The MM54HCT/MM74HCT sub-family of MM54HCI
MM74HC logic provides TTL compatible input logic voltage
levels. This will enable TTL outputs to be guaranteed to
correctly drive CMOS inputs. An incompatibility results because TTL outputs are only guaranteed to pull to a 2.7V
logic high level, which is not high enough to guarantee a
valid CMOS logic high input. To design the entire family to
be TTL compatible would compromise speed, input noise
immunity and circuit size. This sub-family can be used to
interface sub-systems implemented using TTL logic to
CMOS SUb-systems. The input level specifications of
MM54HCT/MM74HCTcircuits are the same as LSTTL. Minimum input high level is 2.0V and the maximum low level is
0.8V using a 5V ± 10% supply.
A fairly simple alternative to interfacing from LSTTL is to tie
a pull-up resistor from the TTL output to Vee, usually
4-10 kn. This resistor will ensure that TTL will pull up to
Vee. (See Interfacing MM54HC/MM74HC High-Speed
CMOS Logic application note.)
Hlgh·Speed CMOS Input Current and Capacitance
Both standard "HC" and TTL compatible "HCT" circuits
maintain the ultra low input currents inherent in CMOS cir·
'cuits when CMOS levels are applied. This current is typically
less than a nanoamp and is due to reverse leakages of the
input protection diodes. Input currents are so small that they
can usually be neglected. Since CMOS inputs present essentially no load, their fanout is nearly infinite.
In typical systems, noise can be capacitively coupled to the
signal lines. The amount of voltage coupled by capacitively
induced currents is dependent on the impedance of the output driving the signal line. Thus, the lower the output impedance the lower the induced voltage. High-speed CMOS offers improved noise immunity over CD4000 in this respect
because its output impedance is one tenth that of CD4000
and so it is about 7 times less susceptible to capacitively
induced current noise.
2-103
....
~.---------------------------------------------------~
~
Z
«
Each CMOS input has some capacitance associated with it,
as do TIL inputs. This capacitance is typically 3-5 pF for
MM54HC/MM74HC, and is due to package, input protection
diode, and transistor gate capacitances. Capacitance information is given in the data sheets and is measured with all
pins grounded except the test pin. This method is used because it yields a fairly conservative result and avoids capacitance meter and power supply ground loops and decoupling
problems. Figure 4 plots typical input capacitance versus
input lIoltage for HC-CMOS logic with the device powered
on. The small'peaking at 2.2V is due to internal Miller feedback capacitance effects.
16
15V
14
UJ
'"i$
....I
12
10
0
>
>....I
8
:::>
6
11.
11.
D
en
When comparing MM54HC/MM74HC input currents to TIL
logic, 54LS174LS does need significantly more input cu~
rent. LSTIL requires 400 /LA of current when a logic low IS
applied and 40 /LA in the high state which is significantly
more than the worst case 1 /LA leakage that MM54HCI
MM74HChas.
c:::J 5.25V
4.75V
6V
4
3V
2V
2
0
HC
METAL
FAMILY GATE
CMOS
LSTTl
TLIF/SOS2- 7
FIGURE 5. Comparison of Supply Range for
"HC", "LS" and Metal-Gate
10.0
9.0
......
...zIII
8.0
~.O
I - VCC=5V
TA = 25°C
'1
i$ 6.0
U
...~
5.0
E
3.0
4.0
~
,.--...,---,--,--,---.,
1 ~A
1---+--j--+---t"""""""""1
!:i!
\.
,.:
ffi
~
a:
a:
:::>
l-
i!
lO~A
u
<.:I
~ lOOnA 1---+---1h",,"-t---::l~--j
2.0
11.
:::>
'"Z
1.0
I-
1.0
2.0
3.0
4.0
l!l 10nA 1--7'4---JioL.._+-
5.0
en
UJ
·s
CJ
INPUT VOLTAGE
TLIF/SOS2-6
50
25
75
TEMPERATURE-OC
FIGURE 4. Input Capacitance vs. Input Voltage
for a Typical Device
TL/F/SOS2-8 .
FIGURE 6. Typical Quiescent Supply Current
Variation wi.th Temperature
MM54HC/MM74HC Power Supply Voltage and
Quiescent Current
Figure 5 compares the operating power supply range of
high-speed CMOS to TIL and metal-gate CMOS. As can be
seen, MM54HC/MM74HC can operate at power supply voltages from 2-6V. This range is narrower than the 3-15V
range of CD4000 and MM54C/MM74C CMOS. The narrower range is due to the silicon·gate CMOS process employed
which has been optimized to attain high operating frequencies at Vcc=5V. The 2-6V range is however much wider
than the 4.5V to 5.5V range specified for TIL circuits, and
guaranteeing operation down to 2V is useful when operating
CMOS off batteries in portable or battery backup applications.
Figure 6 illustrates how this leakage increases with temperature by plotting typical leakage current versus temperature
for an MSI and SSI device. As a result of this temperature
dependence, there is a set of standardized Icc specifications which specify higher current at elevated temperatures.
A summary of these specifications are shown in Table I.
TABLE I. Standardized Icc Specifications for
MM54HC/MM74HC Logic at 25°C, 85°C and 125°C at
Vcc= 6.0V
The quiescent power supply current of the high-speed·
CMOS family is very similar to CD4000 and MM54CI
MM74C CMOS. When CMOS circuits are not switching
there is no current path between Vee and ground, except
for leakage currents which are typically much less than
1 /LA. These are due to diode and transistor leakages.
2·104
Temperature
Gates
Flip-Flops
MSI
25°C
2/LA
4/LA
8/LA
~5°C
20/LA
40 jiA
80/LA
125°C
40/LA
80/LA
160/LA
Output Characteristics
One of the prime advantages of MM54HC/MM74HC over
metal-gate CMOS (besides speed) is the output drive current, which is about ten times C04000 or MM54C/MM74C
logic. The larger output current enables high-speed CMOS
to directly drive large fanouts of 54LS17 4LS devices, and
also enables HC-CMOS to more easily drive large capacitive loads. This improvement in output drive is due to a variety of enhancements provided by the silicon-gate process
used. The basic current equation for a MOSFET is:
Table II summarizes the various output current specifica·
tions for MM54HC/MM74HC CMOS along with their equiva:'
lent LSTTL fanouts. As Table II shows. the output currents
of the MM54HC/MM74HC devices are derated from the
MMY4HC devices. The derating is caused by the decrease
in current drive of the output transistors as temperature is
increased. To show this. Figure 8 plots typical output source
and sink currents against temperature for both standard and
bus driver circuits. This variation is similar to that found in
metal-gate CMOS, and so the same -0.3% per °C derating
that is used to approximate temperature derating of C04000
and MM54C/MM74C can be applied to 54HCI74HC. As an
example. the approximate worst case 25°C current drive
one would expect by using the 4 mA 85°C data sheet number would be about 4 mA at VOUT= 0.26V, and this is what
is specified in the device data sheets.
I = (Beta)(Width/Length)(Vg-VI)Vd-0.5(V~»
Where Vg is the transistor gate voltage, VI is the transistor
threshold voltage, and Vd is the transistor drain voltage
which is equivalent to the circuit output voltage. This CMOS
process, when compared to metal-gate CMOS, has increased transistor gains, Beta, and lower threshold voltages, VI' Also, improved photolithography has reduced the
transistor lengths, and wider !ransistors are also possible
because of tighter geometries.
Figure 7 compares the output high and low current specifications of MM74HC, 74LS and metal-gate CMOS for standard device outputs. High-speed CMOS has worst case output low current of 4 mA which is similar to low power
Schottky TTL circuits, and offers symmetrical logic high and
low currents as well. In addition, CMOS circuits whose functions make them ideal for use driving large capacitive loads
have a larger output current of 6 mA. For example, these
bus driver outputs are used on the octal flip-flops, latches,
buffers, and bidirectional circuits.
II
SOmA
!Z 4DmA
i~
I" '"
r-.."
30mA
~ 20mA
BUS ORIVER
OUTPUT
-
I ...
VCC=5V
VOUT=4.2V
stt:it:::o.-
.... ~
~
~10mA
-60
-20
III
-
20
60
100
TEMPERATURE-OC
(a)
140
TL/F/SOS2-10
SOmA
4mA
i-
Vcc=SV
VOUT=0.4V
VCC=5V,,10%
~
1
3mA
~2mA
~
15
I
i!IIlOL
~
.
.~
~
IWlili0H
COmA
30mA
~
-
lmA -
-
lOrnA
r--.
BUS DRIVER
OUTPUT
r--. r--.
1 __ -
~~TANOARO '"-
-60
74HC·CMOS
- - -rrl
I.... r--.
... 20mA
-20
74LSTTL CD4000 OR
74C-CMOS
20
60
TEMPERATURE-·C
(b)
100
140
TLiF/SOS2-l1
TLiF/SOS2-9
FIGURE 7. Comparison of 74HC, 74LS and CD4000/74C
Output Drive Currents, IOH and lOt
FIGURE 8_ Typical Output (a) Source and (b) Sink
Current Temperature for Standard and Bus Outputs
TABLE 11_ Data Sheet Output Current Specifications
for MM54HC/MM74HC Logic
Device
Vcc=4_5V
Output High
Current
Output Low
Current
LSTTL
.Fanout
Standard 54HC
4.0 mA (VOUT= 3.7V)
4.0 mA (VOUT=0.4V)
10
Bus Driver 54HC
6.0 mA (VOUT=3.7V)
6.0 mA (VOUT=0.4V)
15
Standard 74HC
4.0 mA (VOUT=3.94)·
4.0 mA (VOUT=0.33V)
10
Bus 74HC
6.0 mA (VOUT=3.94)
6.0 mA (VOUT=0.33V)
15
2·105
The data sheet specifications for' output current are measured at only one output voltage for either source or sink
current for each of three temperature ranges, room, commercial, and military, The outputs can supply much larger
currents if larger output voltages are allowed. This is sliown
in Figures 9 and 10, which plot output current versus output
voltage for both .N-channel sink current and P-channel
source current. Both standard and bus driver outputs are
shown. For example, a standard output would typically sink
20 mA with VOL = 1V, and typically capable of a short circuit
current
50 mA.
The output current and voltage characteristics of a logic cir·
cuit determine how well that circuit will switch its output
when driving capacitive loads and transmission lines. The
more current available, the faster the load can be switched.
In order for HC-CMOS to achieve LSTTL performance, the
outputs should have characteristics similar to LSTTL. This
similarity is illustrated in Figure 11 by plotted typical LSTTL
and HC-CMOS output characte~istics together.'
.
As the supply voltage is decreased, the output currents will
decrease. Figure 12a plots the output sink current versus
power supply voltage with a O.4V output voltage, 'and Figure
12b plots output source current against power supply with
an output voltage of Vee-O.BV. It is interesting to note that
MM54HC/MM74HC powered at Vee=3V, typically, will still
drive 10 LSTTL i~puts (T = 25"C).
91
Absolute Maximum Ratings
Absolute maximum ratings are a set of guidelines that define the limits of operation for the MM54HC/MM74HC logic
devices. To exceed these ratings could cause a device to
malfunction and permanently damage itself. These limits
are tabulated in Table III, and their reasons for existing are
discussed below.
1.0
2.0
3.0
4.0
3.0
The largest power supply voltage that should be applied to a
device is 7V. If larger voltages are applied, the transistors
will breakdown, or "punch through". The smallest voltage
that should be applied to a MM54HC/MM74HC circuit is
-0.5V. If more negative voltages are applied, a substrate
diode would become forward biased. In both cases large
currents could flow, damaging' the device.
5.0
OUTPUT VOLTAGE
(8)
TL/F/5052-12
4.0
OUTPUT VOLTAGE
(b)
TLlF/5052-13
FIGURE 9. Typical P·Channel Output Source Current vs.
Output Voltage for (a) Standard and
(b) Bus Outputs
... 80mA I---l--l--l-=-~=--l
~
G60mA 1---l--"7I£:...-+
i
~---r--~
~40mAI---1~~~~--~~~
S
Q20mAr.~~-lr--l~~r--j
5.0
OUTpuT VOLTAGE
(a)
1.0
2.0
3.0
OUTPUT VOLTAGE
(b)
TL/F/5052-14
FIGURE 10. Typical N·Channel Output Sink Current vs. Output Voltage
for (a) Standard and (b) Bus Outputs
2-106
4.0
5.0
TL/F/5052-15
.------------------------------------------------------------,~
lL L
Or--.---.--,-~~~
TA=2~'C
~ -20 r-_t--_t---tL'--t-7_4L7s..-'-!-V_-i
~
1 /74HC
1 /
~-
V
1/
30
r /
I
,'_,
40
Co.)
~
30 r---Hr--r--t---t------l
I--:
/w~~
II
~2D
~ I---=:V
=a:
74LS
1/
-~ 1II//~_+-_+-_+-_+--l
u __
-50
10
= /
~~--~--~--~~
1.0
60,--,---,--,---.--.
TA=25'C
7_4HC
50 t--t--t-:;;~t;:::;;...t-4
...
J~
iJi-40
2:
c
i=
~ -10 r--r--r--V--t-i'---i
2.D
3.0
4.0
_ L_ _- L__~~
DL-~
o
5.0
1.0
OUTPUT VOLTAGE (V)
2.0
3.0
4.D
5.0
OUTPUT VOLTAGE (V)
(a)
TL/F/5052-16
(b)
TL/F/5052-17
FIGURE 11. Comparison of Standard LSTTL and HC-CMOS Output
Cal Source and (bl Sink Currents
'" 24.D
..---r--'----V,.--::71
~ 20.0
I---l---+---;....,.---j
'f.
'"
=
.;
1., 40.0 f-----+--t-----I------l
~
~~~g,RJVER /
BUS DRIVER /
I
T=25'C "'BUS D~IVER _",,_
;;
§t 16.D
V
!C
~ 32.0 I---'---t---'-.::p;'/"--I
T=12_~,~--::;""
•••••
~ 12.0 V 1---.-:;;::' -----1---------·8 8.0 ••••• K'" .'
;;
1;.7__ -- _--~·1
:
0L-__
2.0
1 __
5
7=2
__
~
~
r
4.0
5.0
3.0
SUPPLY VOLTAGE
. (a)
::
6
_ L_ _~
T=25 ~
':> _----
.---
~
V.••••••~
--- p.-••••••••••••••••••••
~. ___ -"0 .,-
2.0
6.0
V
STAN~~RO/ ~.• ----- _---
24.0
ffi
~ 16.0
~ B.O
STANDARD
:: 4.0 r..---=+STANDARD-T=l 25'C -
s
BUS DRIVER,
T=125'C
"
§t
:::;:.r--
3.0
STANDARD
T=125°C
4.0
5.0
SUPPLY VOLTAGE
(b)
TL/F/50S2-1B
6.0
TLIF/S052-19
FIGURE 12_ Output Cal Sink and (bl Source Current
Variation with Power Supply
High-speed CMOS inputs should not have DC voltages applied to them that exceed Vee or go below ground by more
than 1.5V. To do so would forward bias input protection
diodes excessive currents which may damage them. In actuality the diodes are specified to withstand 20 mA current.
Thus the input voltage can exceed 1.5V if the designer limits
his input current to less than 20 mA. The output voltages
should be restricted to no less than - 0.5V and no greater
than Vee+0.5V. or the current must be limited to 20 mA.
The same limitations on the input diodes apply to the outputs as well. This includes both standard and TRI-STATE®
outputs. These are DC current restrictions. In normal high
speed systems. line ringing and power supply spiking unavoidably cause the inputs or outputs to glitch above these
limits_ This will not damage these diodes or internal circuitry.
The diodes have been specifically designed to withstand
momentary transient currents that would normally occur in
high speed systems.
Additionally, there is a maximum rating on the DC output or
supply currents as shown in Table 3. This is a restriction
dictated by the current capability of the integrated circuit
metal traces. Again this is a DC specification and it is expected that during switching transients the output and supply curren,ts could exceed these specifications by several
times these numbers.
For most CD4000 and MM54C/MM74C CMOS operating at
Vee= 5V, the designer does not need to worry about excessive output currents, since the output transistors usually
cannot source or sink enough current to stress the metal or
dissipate excessive amounts of power. The high-speed
CMOS devices do have much improved output characteristics, so 'care should be exercised to ensure that they do not
draw excessive currents for long durations, i.e., greater than
0.1 seconds_ It is also important to ensure that internal dissi- .
pation of a circuit does not exceed the package power dissipation. This will usually only occur when driving large currents into small resistive loads_
TABLE 111_ Absolute Maximum Ratings for
MM54HC/MM74HC CMOS Logic
Symbol
Value
Unit
-0.5 to 7.0
V
DC Input Voltage
-1.5 to Vee + 1.5
V
DC Output Voltage
-0.5toVee+ 0.5
V
±25
mA
mA
Parameter
Vee
DC Supply Voltage
VIN
VOUT
lOUT
Icc
IIK,IOK
Standard
DC Current, Per Output Pin
DC Vee or Ground Current
Bus Driver
±35
Standard
±50
mA
Bus Driver
±70
mA'
±20
mA
Input or Output Diode Current'
2-107
~r-------------------------------------------------------------------------------------~
~
Z
:::>
BASED ON INPUT HIGH _
CUR~E_N_TSr--r--i
'.......
-/+--+--+-~
pULL-Ur,.RES!SroR~rs..-_'I".....t:'r'_+_+__j_+l
VAWES I'
.
I........
1
,....",
/.
4 MIWNUM.RUI$lA!lef lASED O.I-+.
......
~......
2 SIIIK CIlfIRENT U:j:MI:.:;TII::.:~;:::.::NS;..,.,::/;o~.iI'::....j__t
... 1 . ( 1'1 .J-t-"
o
4
8
12
16
20
LSTTL FANOUT
TL/F/5053-2
FIGURE 3. Range of Pull-Up Resistors for Low
Power Schottkey TTL to CMOS Interface
When MM54HC/MM74!1C outputs are driving TIL inputs,
as shown in Figure 5. there is no incompatibility. Both the
high and low output voltages are compatible with TIl. The
only restriction in high-speed CMOS driving TIL is the same
fanout restrictions that apply when TIL is driving TIl.
VCC
STANDARD
HC·CMOS INPUT
----------.--~C~------------~------------~
Rl
,
fiGURE 2. Interfacing LSTTL Outputs to Standard
CMOS Inputs Using a Pull-Up Resistor
2·110
TL/F/5053-3
STANDARD
HC·CMOS INPUT
TYPICAL
LSTTLOUTPIIT
- - - -.....-'lCC
TTL TO
CMOS LEVEL
TIWISLATOR
MM54HCTI
MM74HCT
HC-tMOS LUOIC
.TTL LOUIC
TL/F/5053-4
FIGURE 4. LSTTL Outputs Directly Drives MM54HCT/MM74HCT Logic
Directly Which Can Interface to MM54HC/MM74HC
TfPlCAL
HC·CMDS OUTPUT
'ICc-IV .
1------....-------1
EQUIYAWIT
LITTL INPUT
VCC:--.....- - ,
REO
I,:"
LSTTL LOGIC
HI8H-aPEEO
CMDS LUlIC
TL/F/5053-5
FIGURE 5. High-Speed CMOS Can Directly Connect Up
to LSTTL Within its Fanout Restrictions
2-111
,...
~ r-------------------------------------------------------------------------------~
CO)
Z
coJ"lVIr++----,
I
II
I
I
I
I
I
'--
VCC=5V
II
"
CONTROL
[SYSTEM
I
I
I
.
-_/
r:7o
I CONTROL
~STEM
~IC
.
TL/F/5053-17
FIGURE 15. Interfacing MM54HC/MM74HC to Relays
Conclusion
InterfaCing between different logic families is not at all difficult. In most instances, when no logic level translation between is done, no external circuitry is needed to interconnect logiC families. Even though the wide supply range of
MM54C/MM74C and CD4000 creates many possible logic
level conversion interface situations, most are easily tiandied by employing a minimum of extra circuitry. Additionally,
several special interface devices also simplify logic level
conversion.
110V
R2
TL/F/5053-1B
FIGURE 16. MM54HC/MM74HC Driving an SCR
2-118
l>
Z
AC Characteristics of
MM54HC/MM74HC
'High-Speed CMOS
National Semiconductor
Application Note 317
Larry Wakeman
June 1983
When deciding what circuits to use for a design, speed is
most often a very important criteria. MM54HC/MM74HC is
intended to offer the same basic speed performance as'low
power Schottky TTL while giving the designer the low power
and high noise immunity characteristics of CMOS. In other
words, HC-CMOS is about ten times faster than CD4000
-and MM54C/MM74C metal-gate CMOS logic. Even though
HC-CMOS logic does have speeds similar to LSTTL"there
are some differences in how this family's speeds are specified, and how various parameters affect circuit performance.
To give the designer an idea of the expected performance,
this discussion will include how the AC characteristics of
high-speed CMOS are specified. This logic family has been
specified so that in the majority of applications, the specifications can be directly applied to the design. Since it is
impossible to specify a device under all possible situations,
performance variations with power supply, loading and tem.perature are discussed, and several easy methods for determining propagation delays in nearly any situation are also
described. Finally, it is useful to compare the performance
of HC-CMOS to 54LS/74LS and to CD4000.
capacitor and a 1 kO resistor. To test tpHZ, the resistor is
swiched to ground, and for tpLZ it is switched to Vee. The
TRI-STATE test circuit and typical timing waveforms are
shown in Rgure 2.
W
.....
......
Measurements, where the output goes from the high impedance state to active output, are the same except that measurements are made to the 50% pOints and for bus driver
devices both 50 pF and 150 pF capacitors are used.
5V-,INPIIT
lOll
OV _ _ _.;.10;;.;1I="
VOHOUTPUT
VOL------
J
TL/F/5067-1
(a)
Data Sheet Specifications
Even though the speeds achieved by this high-speed CMOS
family are similar to LSTTL, the input, output and power
supply characteristics are very similar to metal-gate CMOS.
Because of this, the actual measurements for various timing
parameters are not done the same way as TTL. The
MM54HCT/MM74HCT TTL input compatible circuits are an
exception.
5VINPIIT
(CLOCK)
-:"~;C-
5V-
Standard HC-CMOS AC specifications are measured at
Vee=2.0V, 4.5V, 6.0V tor room, military and commercial
temperature ranges. Also HC is specified with LS equivalent
supply (5.0V) and load conditions to enable proper comparison to low power Schottkey TTL. Input signal levels are
ground to Vee with rise and fall times.of 6 ns (10% to 90%).
Since standard CMOS logic has a logic trip point at about
mid-supply, and the outputs will transition from ground to
Vee, timing measurements are made from the 50% pOints
on input and output waveforms. This is shown in Figure f.
Using the mid-supply point gives a more accurate representation of how high-speed CMOS will perform in a CMOS
system. This is different from the 1.3V measurement point
and ground to 3V input waveforms that are used to measure
TTL timing.
This output loading used for data sheet specifications fall
into two categories, depending on the output drive capability
of the specific device. The output drive categories are standard outputs (IOL =4 mAl and bus driver outputs
(IOL = 6 mAl. Timing measurements for standard outputs
are made using a 50 pF load. Bus driver circuits are measured using both a 50 pF and 150 pF load. In all AC tests,
the test load capacitance includes all stray and test jig capacitances.
TRI-STATE® measurements where the outputs go from an
active output level to a high impedance state, are made
using the same input waveforms described above, but the
timing is measured to the 10% or 90% points on the output
waveforms. The test circuit load is composed of a 50 pF
lOll
OV _ _
INPUT
(DATA. J. K. ETC.)
OV
OUTPUT
VOL--------
'NOTE: IW COULD BE EITHER
POSITIVE OR NEGATIVE PULSE
DEPENDING ON SPECIFICATION
TL/F/5067-2
(b)
5V
TEST
DEVICE
Vcc
CL=50pF (STANDARD DEVICE)
CL = 50 or 150 pF (BUFFER oEVICEI
TL/F/5067-3
(c)
FIGURE 1. Typical Timing Waveform for (a) Propagation
Delays, and (b) Clocked Delays. Also Test
Circuit (c) for These Waveforms (t, = tf = 6 ns)
2·119
3,OVINPUT
INPUT
10%
OV _ _';;;;;';;C-
-tPHl-
--tPLH -
VOHOUTPUT
OUTPUT
OUTPUT
-t>
_ _ _ _...;..K.;;J
10%
.
.r'"
VOL-------
TL/F/S067-S
(a)
K'-
TL/F/S067-4
(a)
3V-
INPUT
Vee
(CLOCKI _ _ _ _--l~.J'I-_;_--I~
OV
10%
_
I$ _ _
""":21",°%,--_
t"_
INPUT
1.3V
(D~TAI
OY
-:-t
PlH
OUTPUT
-I,
"."
~l-------------'
(b)
TL/F/S067-S
(b)
FIGURE 2. Typical TRI-STATE (a) Timing Waveforms
and (b) Test Circuit
TliF/SOS7-7
FIGURE 3. Typical Timing Waveforms for (a)
Propagation Delays, and (b) Clocked Delays for 54HCTI
74HCT Devices (tr=t,=6 ns)
Note: Some ea~y data sheets used a different test circun. This has been
changed or will be changed.
The MM54HCT/MM74HCT TIL input compatible devices
are intended to operate with TIL devices. and so it makes
sense to specify them the same way as TTL. Thus. as
shown in Figure 3; typical timing input waveforms use 0-3V
levels and timing measurements are made- from the 1.3V
levels on these signals. The test circuits used are the same
as standard HC input circuits. This is shown in Figure 3.
These measurements are compatible with TIL type specified devices.
'
Specifying standard MM54HC/MM74HC speeds using 2.SV
input measurement levels does represent a specification incompatibility between TIL and most RAM/ROM and microprocessor speed specifications. It should not. however.,
present a design problem. The timing difference that results
from using different measurement pOints is the time it takes
for an output to make the extra excursion from 1.3V to 2.5V.
Thus. for a standard high-speed CMOS output. the extra
transition time should result. worst case. in less than a 2 ns
increase in the circuit delay measurement for a SO pF load.
Thus in speed critical designs adding 1-2 ns safely enables
proper design of HC into the TIL level systems.
Power Supply Affect on AC Performance
The overall power supply range of MM54HC/MM74HC logic
is not as wide as CD4000 series CMOS due to performance
optimization for sVoperation; however. this femily can operate over a 2-6V range which does enable some versatility.
especially when battery operated. Like metal-gate CMOS.
lowering the power supply voltage will result in increased
circuit delays. Some typical delays are shown in Figure 4. As
the supply voltage is decreased from SV to 2V. propagation
delays increase by about two to three times. and when the
voltage is increased to 6V. the delays decrease by 10 -1S 0/0.
80r---~----~--~~--~
l!!
I
:5w
TA=25'C
CL=50pF
60
CI
z
CI
40
...a:co
20
~
:;
oL---~----L---~--~
2
3
5
6
POWER SUPPLY VOLTAGE
TLiF/S067-8
FIGURE 4. Typical Propagation Delay Variations of
74HCOO, 74H.C139, 74HC174 with'Power Supply
In some designs it may be important to calculate the expected propagation delays for a specific situation not covered in
the data sheet. This can easily be accomplished by using
the normalized curve of Figure 5 which plots propagation
delay variation constant, t(V), versus power supply voltage
normalized to 4.5V and 5V operation. This constant, when
used with the following equation and the data sheet 5.0V
specifications, yields the required delay at any power
supply.
tpD(V) =' [t(V)l [tPD(5V)1
Where t(V) is the propagation delay variation with power
supply constant, tpD(5V) is the data sheet 4.5V (use
(CL - = 50 pF) in equation) or 5V delay, CL is the load capacitance and tpD(C,V) is the resultant propagation delay at
the desired load and supply. This equation's first term is the
'difference in propagation delay from the desired load and
the data sheet specification load. The second term is essentially equation 1.0. If the delay is to be calculated at
Vee= 5V, then t(V) = 1 and t(C) = 0.042 nS/pF (standard
output), 0.028 nS/pF (bus output).
1.0
Using the previous 74HCOO example, the delay at Vee=BV
and a 100 pF load is:
Where tpD(5V) is the data sheet delay and tpD(V) is the
resultant delay at the desired supply voltage.
This curve can also be used for the Vee=4.5V specifications.
For example, to calculate the typical delay of the 74HCOO at
Vee = BV, the data' sheet typical of 9 ns (15 pF load) is used.
From Figure 5 t(V) is 0.9, so the BV delay would be 8 ns.
tpD(100 pF,BV)= (0.042)()OO-15)+ (0.9 X 9)= 11 ns
:;;-
T
z
o
15
5:
10
:.'"
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o
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o
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a..
'~
50
-
100
150
200
250
LOAD CAPACITANCE-pF
TLlF/5067-10
N
z
0
0
ii:
~
~
o
20
z
~
:ii!
i
;;:>-
4
FIGURE B. Typical Propagation Delay Variation
With Load Capacitance for 74HC04, 74HC164,
74HC240, 74HC374
0
2
POWER SUPPLY VOLTAGE
TL/F/5067-9
~
FIGURE 5. MM54HCMM74HC Propagation Delay
Variation Vs_ Power Supply Normalized to
Vee = 4.5V, and Vee = 5.0V
~
i
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z
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c'"
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z
Speed Variation with Capacitive Loading
0.10
0.08
.
z 0.06
.;::
ii: 0.04
§
0
When high-speed CMOS is designed into a CMOS system,
the load on a given output is essentially capacitive, and is
the sum of the individual input capacitances, TRI-STATE
output capacitances, and parasitic wiring capacitances. As
the load is increased, the propagation delay increases. The
rate of increase in delay for a particular device is due to the
increased charge/discharge time of the output and the load.
The rate at which the delay changes is dependent on the
output impedance of the MM54HC/MM74HC circuit.· As
mentioned, for high-speed CMOS, there are two output
structures: bus driver and standard.
Figure 6 plots some typical propagation delay variations
against load capacitance. To calculate under a particular
load condition what" the propagation delay of a circuit is, one
need only know what the rate of change of the propagation
delay with the load capacitance and use this number to extrapolate the delay from the data sheet vaue to the desired
value. Figure 7 plots this constant, t(C), against power supply voltage variation. Thus, by expanding on equation 1.0,
the propagation delay at any load and power supply can be
calculated using:
tpD(C,V) = [t(C) (CL - 15 pF)l + [tPD(5V) t(V)]
0.12
~
;rl '0.02
~
\
f\-.'
""
~ANDARO
.........
......
BUS DRIVER'
r----..
r--r--
0
w
>
;::
....
c:;
a..
...,
POWER SUPPLY VOLTAGE
TLlF/5067-11
FIGURE 7. Propagation Delay Capacitance Variation
Constant Vs. Power Supply
Speed Variations with Change
in Temperature
Changes in temperature will cause some change in speed.
As with CD4000 and other metal-gate CMOS logiC parts,
MM54HC/MM74HC operates slightly slower at elevated
temperatures, and somewhat faster at lower temperatures.
The mechanism which causes this variation is the same as
that which causes variations in metal-gate CMOS. This
1.1
2-121
,...
;;
Z
c(
factor is carrier mobility, which decreases with increase in
temperature, and this causes a decrease in overall transistor gain which has a corresponding affect on speed.
Figure 8 shows some typical temperature-delay variations
for some high-speed GMOS circuits. As can be seen,
speeds derate fairly linearly from 25°C at about -0.3%/C.
Thus, 125°C propagation delays will be increased about
30% from 25°C. 54HC174HC speeds are specified at room
temperature, -40 to 85°C (commercial temperature range),
and - 55 to 125°C (military range). In virtually all cases the
numbers given are for the highest temperature.
To calculate the expected device speeds at any temperature, not specified in the device data sheet, the following
equation can be used:
tpO(T)= [1 + ((T -25)(0.003»))[tpo(25)j
1.2
Where tpo(T) is the delay at the desired temperature, and
tpo(25).js the room temperature delay. Using the 74HCOO
example from the previous section, the expected increase in
propagation delay when operated at Vee=5V and 85°C is '
[1 + (85-25)(0.003)](10 ns)1 = 12 ns. The expected delay at
some other supply can also be calculated by calculating the
room temperature delay then calculating ihe delay at the
desired temperature. "
ternal propagation delays. Thus they exhibit the similar temperature and supply dependence as propagation delays.
They are, however, independent of output load conditions.
f
w
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;:::
15
:l
c
...a:
CI
10
w
'"...
;;:
...:>~
CI
50
100
150
200
250
OUTPUT LOAD CAPACITANCE-DF
"
TL/F/5067-13
FIGURE 9_ Typical 'Output Rise or Fall TIme Vs. Load For
Standard and Bus Driver Outputs
Input Rise and Fall Times
f
:3w
'"z
'"ii...
Another speed conSideration, though not directly related to
propagation delays, is input rise and fall time. As with other
high-speed logic families and also CD4000B and 54C17 4C
CMOS, slow input rise and fall times on input signals can
cause logic problems.
Typically, small signal gains for a MM54HC/.MM74HC gate
is greater than 1000 and, if input signals spend appreciable
time between logic states, noise on the input or power supply will cause the output to oscillate during this" transition.
This oscillation could cause logic errors in the user's circuit
as well as disSipate extra power unnecessarily. For this reason MM54HC/MM74HC data sheets recommend that input
rise and fall times be shorter than 500 ns at VCC=4.5V.
40
3D
20
if
co
IE
10
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE-OC
TLlF/5067-12
FIGURE 8. Typical Propagation Delay Variation
With Temperature for 54HC02,54HC390,
54HC139, 54HC151 '
Output Rise and Fall, Setup and Hold Times
and Pulse Width Perfor~ance Variations
So far, the previous discussion has been restricted to propagation delay variations, and in most instances, this is the
most important, parameter to know. Output rise and fall
times may also be important. Unlike TTL type logic families
HC specifies these in the data sheet. High-speed CMOS
'outputs were designed to have typically symmetrical rise
and fall times. Output rise and fall time variations track very
closely the propagation delay variations over temperature
and supply. Figure 9 plots rise and fall time against output
load at Vee = 5V and at room temperature. Load variation of
the transition time is twice the deiay variation because delays are measured at halfway points on the waveform transition.
Setup times and pulse width performance under different
conditions may be necessary when using clocked logic circuits. These parameters" are indirect measurements of in-
Flip-flops and other clocked circuits also should have their
input rise and fall times faster than 500 ns at Vcc=4.5V. If
clock input rise and fall times become too long, System
noise can generate internal oscillations, causing the internal
flip-flops to toggle on the wrong external clock edge. Even if
no noise were present, internal clock skew caused by slow
rise times could cause the logic to malfunction.
If long rise and fall times are unavoidable, Schmitt triggers
(,HC14I'HC132) or other special devices that employ
Schmitt trigger circuits should be used to speed up these
input signals:
Logic Family Performance Comparison
To obtain a better feeling of how high-speed CMOS compares to bipolar and other CMOS logic families, Figure 10
plots MM54HC/MM74HC, 54LS174LS and CD4000B logic
device speeds versus output loading. HC-CMOS p"ropagation delay and delay variation with load is nearly, the same
as LSTTL and about ten times faster than metal-gate
CMOS. Utilizing a silicon-gate process enables achievement
of LSTTL speeds, alld the large output drive of this family
enables the variation with loading to be nearly the same as
LSTTL as well,
When comparing to CD4000 operating at 5V, HC-CMOS is
typically ten times faster, and about three times faster than
CD4000 logic operating at 15V. This is shown in Figure 11.
2·122
40r---~--~--.---.---'
DM7JLS151
80r-.-'-'--r-r~-T-'-'~
•••••••
70~+-+-+-+-+-1-1-1-~4
_+---+1 ......... k-
30 1-
20
10
60~+-+-+-+-+-1-~~~4
..
~Vr-,
~~.
MM74HC151
1--1 I
DM74LS240
MM74HC240
MM74HCOO
74COO
~501--1--~,~~~-+-r-r~4
40
30 1--~+-+-4-~-7~4L-S~00-+-4~
...
r-;:;:~
J..l;~~:~~~~: ~
:;:?: .....••..•
20
10
50
100
150
200
~
250
74HCOO
r- -ltPLH -
tPHL -
-
ht..'.......... iIC1E ..
~~~ffi!=
-60 -40 -20 0 20 40 60 80 100 120 140
OUTPUT CAPACITANCE LOAO-pF
TEMPERATURE-'C
TLlF/S067-14
FIGURE 10. Comparison of LSTTL
and High·Speed CMOS Delays
TlIF/S067-16
FIGURE 12. Comparison of HC·CMOS, Metal·Gate
CMOS, and LSTTL Propagation Delay Vs. Temperature
. Conclusion
At 5V CD4000 has about a tenth the output drive of
MM54HC/MM74HC and as seen in Figure 10, the capacitive delay variation is much larger.
As shown in Figure 12, the temperature variation of HeCMOS is similar to CD4000. This is due to the same physical phenomenon in both families. The 54LS174LS logic family has a very different temperature variation, which is due to
different circuit parameter variations. One advantage to
CMOS is that its temperature variation is predictable, but
with LSTTL, sometimes the speed increases and other
times speed decreases with temperature.
The inherent symmetry of MM54HC/MM74HC's logic levels
and rise and fall times tends to make high to low and low to
high propagation delay very similar, thus making these parts
easy to use.
'
High·speed CMOS circuits are speed compatible with
54LS/74LS circuits, not only on the data sheets, but even
driving different loads. In general, HC-CMOS provides a
large improvement in performance over older metal·gate
CMOS.
By using some of the equations and curves detailed. here,
along with data sheet specifications, the designer can very
closely estimate the performance of any MM54HCI
MM74HC device. Even though the above examples illustrate typical performance calculations, a more conservative
design can be implemented by more conservatively estimating various constants and using worst case data sheet lim·
its. It is also possible to estimate the fastest Propagation
delays by using speeds about 0.4-0.7 times the data sheet
typicals and aggressively estimating the various constants.
200 r---r---'---'-"T""'-~
CD4~18
If
150
S
~ 100
5i
~
~
50
--=1'-'/
(VCC=5V)
_.?
.-
•
•
./
y' 74C374
v. :.'>r
-,'
74C374
(VCC=5V)
CD4011B
(Vcer15V)
(VC.~=~.~~).. I~
1 ........
'
.......
..... •
.........
50
}........
•......... ···~~HC373_
/J~
100
150
200
250
OUTPUT CAPACITANCE LOAO-pF
TL/F/S067-1S
FIGURE 11. Comparison of Metal·Gate CMOS and
High·Speed CMOS Delays
2·123
....CD
~
~
.-----------------------7~------------------------------------------------------------,
National Semiconductor
Application Note 319
Larry Wakeman
June 1983
Comparison of
.
MM54HC/MM74HC to
54LS/74LS, 5aS/74S and
54ALS/74ALS Logic
The MM54HC/MM74HC family of high speed logic components provides a combination of speed and power characteristics that is not duplicated by bipolar logic families or any
other CMOS family. This CMOS family has operating
speeds similar to low power Schottky (54LSI74LS) technology. MM54HC/MM74HC is approximately half as fast (delays are twice as long) as the 54ALS174ALS and 54S174S
logic. Compared to CD4000 and 54C/74C; this is an order
of magnitude improvement in speed, which is achieved by
utilizing an advanced 3.5 micron silicon gate-recessed oxide
CMOS process. The MM54HC/MM74HC components are
designed to retain all the advantages of older metal gate
CMOS, plus provide the speeds required by today's high
speed systems.
Another key advantage of the MM54HC/MM74HC family is
that it provides the functions and pin outs of the popular
54LS174LS series logic components. Many functions which
are unique to the CD4000 metal gate CMOS family have
also been implemented in this high speed technology. In
. addition, the MM54HC/MM74HC. family contains several
special functions not previously implemented in CD400.0 or
54LSI74LS.
Although the functions and the speeds are the same as
54LS17 4LS, some of the electrical characteristics are different from either LS-TTL, S-TTL or ALS-TTL. The following
discusses these differences and highlights the advantages
and disadvantages of high speed CMOS.
and to be 8-10 times faster than CD4000B and MM54C/
MM74C logic. Table I compares high speed CMOS to the
bipolar logic families. HC-CMOS gate delays are typically
the same as LS-TTL, and ALS-TTL is two to three times
faster. S-TTL is also about twice as fast as HC-CMOS. Flipflpp and counter 'speeds also follow the same pattern.
AC PERFORMANCE
As mentioned previously, the MM54HC/MM74HC logic family has been designed to have speeds equivalent to LS-TTL,
FIGURE 1. HC, LS, ALS, S Comparison of Propagation
Delay vs Load for a NAND Gate
Also, HC Ibgic's propagatiQ,n delay variation due to changes
in capacitive loading is very similar to LS-TTL. Figure 1 illustrates this by plotting delay versus loading for the various
bipolar logic families and MM54HC/MM74HC. HC-CMOS
has virtually the same speed and load-delay variation as
30
I
-~
~ 20
.... ,''''
~~~
... ~~ ...7tLS
....
.~~
:::- ~1;
w
co
74LS
z
ij
.~
."
10
co
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-,-
'1'
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50
100
150
LOAD CAPACITANCE (pFI
200
TUF15101-1
TABLE I. Comparison of Typical AC Performance of L5-TTL, S-TTL, AL5-TTL and He-CMOS
Gates
L5-TTL
AL5-TTL'
HC-CMOS
S-TTL
74XXOO
Propagation Delay
8
5
8
4
ns
74XX04
Propagation Delay
8
4
8
3
ns
Combinational MSI
74XX139
Units
i
Propagation Delay
Select
Enable
25
21
8
8
25
20
8
7
Propagation Delay
Address
Strobe
27
26
8
7
26
17
12
12
ns
ns
Propagation Delay
Enable/Disable Time
12
20
3
7
10
17
5
10
ns
ns
74XX174
Propagation Delay
Op'erating Frequency
20
40
7
50
18
50
13
100
ns
MHz
74XX374
Propagation Delay
Enable/Disable Time
Operating Frequency
19
21
50
7
.9
50
16
17
50
11
11
100
ns
ns
MHz
74XX151
74XX240
ns
ns
-
ClockedMSI
2·124
,
~
The previously mentioned curves plot unloaded circuits.
When considering typical system power consumption, capacitive loading should also be considered. Table III lists
components to implement all the support logic for a small
microprocessor based system ..By assuming a typical load
capacitance of 50 pF, the power dissipation for these devices can be calculated at various average system clock frequencies. Figure 3 plots power consumption for 74HC,
74LS, 74ALS and 745 logiC implementations. Above 1 MHz,
capacitive currents now also tend to dominate bipolar power
dissipation as well.
LS-TTL and, as is expected, is slower than ALS and S-.TTL
logic. The slopes of these lines indicate the amount of variation in speed with loading, and are dependent on the output
impedance of the particular logic gate. The delay variation
of LS-TTL and HC-CMOS is similar whereas ALS-TTL and
S-TTL have slightly less variation.
POWER DISSIPATION
CD4000B and MM54C/MM74C CMOS devices are well
known for extremely low quiescent power dissipation, and
high speed CMOS retains this feature. Table II compares
typical HC static power consumption with LS, ALS and 5TTL Even CMOS MSI dissipation is well below 1 /kW while
LS-TTL dissipation is many milliwatts. This makes
MM54HC/MM74HC ideal for battery operated or ultra-low
power systems where the system may be put to "sleep" by
shutting off the system clock.
TABLE III. Hypothetical "Glue" Logic for a
Typical Microprocessor System
TABLE II. Comparison of Typical Quiescent
Supply Current for Various Logic Families
HC-CMOS
LS-TTL
ALS-TTL
S-TTL
SSI
0.0025/kW
5.0mW
2.0mW
75mW
Flip-Flop
0.005,.W
20.0mW
10mW
150mW
MSI
0.25,.W
90mW
40mW
470mW
CMOS dissipation increases proportionately with operating
frequency. Doubling the operating frequency doubles the
current consumption. This is due to currents generated by
charging internal and load capacitances. Figure 2 shows
power dissipation versus frequency for a completely unloaded NAND gate, flip-flop and counter implemented in all 4
technologies.
The LS, 5 and ALS curves are essentially flat because the
quiescent currents mask out capacitive effects, except at
very high frequencies. CapaCitive effects are slightly lower
for the TTL families, so that, at high frequencies, CMOS
dissipation may actually be more than ALS and LS. Howev, er, the power crossover frequency is usually well above the
maximum operating frequency of MM54HC/MM74HC.
100m
100m
~
i
...
1m
II:
:0
'"
.~ 100~
~
lOOk
1M
10M
OPERATING FREQUENCY (Hz)
100M
# oflCs
10
5
10
20
30
20
10
AVERAGE SYSTEM OPERATING FREQUENCY (Hz)
TL/F/5101-2
FIGURE 3. Power Consumption for Hypothetical
Microprocessor System Support Logic
100m
~'-~;~
~
i
10m
:0
~
System Components
Address Decoders (,138)
Address Comparators ('688)
Address/Data Buffers ('240/4)
Address/Data Latches ('373/4)
MSI Control/Gating ('00, '10)
Misc. Counter/Shift Reg (,161, '164)
Flip-Flops ('73/4)
...'"
..
10m
:0
~
II:
1m
iil
~ 100~
~
~
10M
100M
lOOk
1M
OPERATING FREQUENCY (Hz)
lOOk
1M
TlIF/5101-3
(a)
(b)
FIGURE 2. Supply Current Consumption Comparison
for (a) 74XXOO (b) 74XX714 (c) 74XX161 Circuits
2·125
10M
100M
OPERATING FREQUENC\~/~/5101_4
(c)
Z
W
....
CO
Since, in a typical system, some sections will operate at a
high frequency and other parts at lower frequencies, the
average system clock frequency is a simplification. For example, a 10 MHz microprocessor will have a bus cycle frequency of 2 to 5 MHz. Most system and memory components will be accessed a small amount of the time, resulting
in effective clock frequencies on the order of 100 kHz for
these sections. Thus, the average system clock frequency
would be around 1 to 2 MHz, and an 8 to 1 power savings
would be realized by using CMOS.
Second, TTL logic has a slightly smaller logic voltage swing
than CMOS. Thus, for a given load, TTL will actually have a
lower average load current. So, similar to the unloaded example, at very high frequencies, CMOS could consume
more power than TTL. As Figure 5 indicates, these frequencies are usually far above the 30 MHz li.."it of HC-CMOS or
LS-TTL.
INPUT VOLTAGE CHARACTERISTICS
AND NOISE IMMUNITY
To maintain the advantage CMOS has in noise immunity,
the input logic levels are defined to be similar to metal gate
CMOS. At VcC=5V, MM54HC/MM74HC is'designed to
have input voltages of VIH=3.5V and VIL = 1.0V. Additionally, input voltage over the operating supply voltage range is:
VIH=0.7VCC and VIL =0.2Vcc. This compares to VIH=2.0V
and VIL =0.8V specified for LS-TTL over its supply range.
Figure 4 illustrates the input voltage differences, and the
greater noise immunity HC logic has over its supply range.
Maintaining wide noise immunity gives HC-CMOS an advantage in many industrial, automotive, and comp\lter applications where high noise levels exist.
AnQther simplification was made to calculate system power.
CMOS circuits will dissipate much less power when TRISTATE!!>, which would save much power since, in a given
bus cycle, only a few buffers will be enabled. LS, ALS and S,
however, actually dissipate more power when their outputs
are·disabled.
Several interesting conclusions can be drawn from Figure 3.
First, notice that, at higher frequencies, the bipolar logic
families start to dissipate more power. This is a result of
current consumption due to switching the load. As the operating frequency approaches infinity, this will be the dominant
effect. So, for extremely fast low power systems, minimizing ,
load capacitance and overall operating frequency becomes
more important. As lower power TTL logic is introduced,
system power will be increasingly dependent on capacitive
load effects similar to CMOS.
,
I
POWER SUPPLY VOLTAGE IV)
TL/F15101-5
FIGURE 4. Worst-Case Input and Output Voltages Over
Operating Supply Range for HC and LS Logic
.1.
:--- - .
I--J25°C
~
j'
I
-55°C---..
I
o
... -
125°C
3
4
INPUT VOLTAGE (V)
(a)
~
o
-55°C
1ZSoC
l\
o
1
4
I \1
TLlF/5101-6
. FIGURE 5.lnput-Qutput Transfer Characteristics for 74XXOO
NAND Gate Implemented in (a) HC-CMOS (b) LS-TTL (c) ALS-TTL
2·126
.1
o
INPUT VOLTAGE IV)
(b)
25°C
r--
_55°C
o
=4.SV
',-
25°C
t--~5°C
o
~CC
VCC=4,5V
IOH=0.4 mA
Vcc=4.5V
3
INPUT VOLTAGE (VI
TL/F/5101-7.
(c)
being provided to ease design of mixed HC/LS/ALS/S systems. These buffers have o.av and 2.0V TIL input voltage
specifications, and provide CMOS compatible outputs.
When mixing logic, the noise immunity at the TIL to CMOS
interface is no better than LS-TIL, but a substantial savings
in power will occur when using MM54HC/MM74HC logic.
Another indication of DC noise immunity is the typical transfer characteristics for the logic families. Figure 5 shows the
transfer function of the 74XXOO NAND gate for HC-CMOS,
LS-TIL and ALS-TIL. High speed CMOS has a very sharp
transition typically at 2.25V, and this transition point is very
stable over temperature. The bipolar logic transfer functions
are not as sharp and vary several hundred millivolts over
temperature. This sharp transition is due to the large circuit
gains provided by triple buffering the HC-CMOS gate compared to the single bipolar gain stage. Figure 6 compares
the transfer function of the 'HCOa and the' ALSOa, both of
which are double buffered. The' ALSOa has a sharper transition, but the CMOS gate still has less temperature variation and a more centered trip point. However, the TIL trip
point is not dependent on Vee variation as CMOS is.
The high speed CMOS input levels are not totally compatible with TIL output voltage specifications. To make them
compatible would compromise noise immunity, die size, and
significant speed. The designer may improve compatibility
by adding a pull-up resistor to the TIL output. He may also
utilize a series of TIL-to-CMOS level converters which are
INPUT CURRENT
The HC family maintains the ultra-low input currents typical
of CMOS circuits. This current is less than 1 p.A and is
caused by input protection diode leakages. This compares
to the much larger LS-TIL input currents of 0.4 mA for a low
input and 40 p.A for a high input. ALS-TIL input currents are
0.2 mA and 20 p.A and S-TIL input currents are 3'.2 mA and
100 p.A. Figure 7 tabulates these values. The near zero input current of CMOS eases designing, since a typical input
can be viewed as an open circuit. This eliminates the need
. for fanout restrictions which are necessary in TIL logic
designs.
I
Vee=4.5V
Vee =4.5V
I
V
125°C '
i-
25°C
25°C I - -
!~ .....
-55°C"
o
o
1
125°~
o
2
3
4
INPUT VOLTAGE (V)
o
i 55 °C
1I
1
2
3
4
INPUT VOLTAGE (V)
TLlF/5101-9
TLlF/5101-8
(a)
(b)
FIGURE 6. Input-Output Transfer Characteristics for
74XX08 AND Gate Implemented in (a) HC-CMOS (b) ALS-TIL
500
400
.~
.....
400 "A
300
z
::!
'"
'"
:>
:>
200
~
100
.IIL
hH.
LS·TTL
.hL
•
hH.
ALS·TTL
1"A
1"A
.IlL
hH,
HC·CMOS
TL/F/5101-10
FIGURE 7. Comparison of Input Current Specifications
for Various Logic Families
2·127
»
z
W
......
CO
POWER SUPPLY RANGE
currents. High speed CMOS is also included. MM54HCI
MM74HC has the same CMOS-to-CMOS.fanout characteristics as CD4000B, virtually infinite.
Figure 4 also compares the supply range of MM54HCI
MM74HC logic and LS-TTL. The high speed CMOS family is
specified to operate at voltages from 2V to 6V. 54LS, 54S
and 54ALS logic is specified to operate from 4.5~ }o 5.5V,
and 74LS and 74S will operate from 4.75V to 5.25V. 74ALS
is specified over a 4.5V to 5.5V supply range. This wider
operating range for the HC family eases power supply design by eliminating costly regulators and enhances battery
operation capabilities.
TABLE IV. Fanout of HC-CMOS, L50TTL,
AL50TTL, 5-TTL
OUTPUT DRIVE
Since there was no speed, noise immunity. or power tradeoff, standard HC-CMOS was designed to have similar high
current output drive that is characteristic of LS-TTL and
ALS-TTL. Schottky TTL has about 5 times the output drive
of MM54HC/MM74HC. Thus HC-CMOS has an output low
current specification of 4 mA at an output voltage of 0.4V. In
keeping with CD4000B series and 54C/74C series logic, the
source and sink currents are symmetrical. Thus HC logic
can source 4 mA as well. This large increase in output current for high speed CMOS over CD4000B also has the added advantage of reducing signal line crosstalk which can be
of greater concern in high speed systems. Figure 8 compares HC, LS, and ALS specified output currents.
74HC
74LS
74ALS
74S
74HC
74LS
74ALS
74S
4000
10
20
20
50
20
40
40
100
2
4
4
10
MM54HC/MM74HC bus driving circuits, namely the TRISTATE buffers and latches, have half again as much output
current drive as standard outputs. These components have
a 6 mA output drive. The 6 mA was chosen based on a
trade-off of die size and speed-load variations. This current
is less than the 12 mA or more specified for LS and ALS bus
driver circuits, because the bus fanout limitations of these
families, do not apply in CMOS systems. S-TTL bus output
sink. current is 48 mAo
4mA
VOl=O.4V
10l
10H
----..-.ALs-TTL
···
As another indication of the similaritY of HC-CMOS to LSTTL, Figure 9 plots typical output currents versus output
voltage for LS and HC. The output sink current curves are
very similar, but LS source current is somewhat different,
due to its emitter-follower output circuitry. •
Since TTL logic families do have significant input currents
they have a limited fanout capability. Table IV illustrates the
limitations of these families, based on their input and output
4 mA
VOl=O,4V
From, To
10l
10H
----..-.Ls-TTL
4mA
4mA
VOH=
Vol = O.4V Vee -O.BV
10l
10H
----..-.HC·CMOS
TL/F/5101-11
FIGURE 8. Output Current Specifications for ALS-TTL, S-TTL and HC-CMOS
....
1 -10 f---+---l--1JL---~'---l
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3.0
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OUTPUT VOLTAGE (V)
60
TA=25"C
50
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40
if
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30
20
10
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1.0
2.0
3.'0
4.0
5.0
OUTPUT VOLTAGE (V)
TL/F/5101 -12
TL/F/5101-13
(a)
(b)
FIGURE g, Comparison of Standard LS-TTL and HC-CMOS Output (a) Source (b) Sink Currents
2·128
HC-CMOS. Note, though, that HC outputs are completely
compatible with the various TTL family's input specifications; therefore, there is no problem when HC is driving TTL.
Another source of possible problems can occur when the
LS deSign floats device inputs. This practice is not recommended when using LS-TTL, but it is sometimes done. Usually, TTL inputs float high; however, CMOS inputs may float
either high or low depending on the static charge on the
input. It is therefore important to always tie unused CMOS
inputs to either Vee or ground to avoid incorrect logic functioning.
A third factor to consider when replacing any TTL logic is
AC performance. The logic functions provided by S4HCI
74HC are equivalent to LS-TTL, and the propagation delay,
set-up and 'hold times are similar to LS. However, there are
some differences in the way CMOS circuits are implemented which will cause differences in speed. For the most part,
these differences are minor, but it is important to verify that
they do not affect the design.
OPERATING TEMPERATURE RANGE
The operating temperature range and temperature effects
on various HC-CMOS operating parameters differ from bipolar logic. The recommended temperature range for 74LS,
'74S, and 74ALS is O'C to 70'C, compared to -40'C to 8S'C
for the 74HC family. S4 series logic is specified from -SS'C
to 12S'C for all four families.
Temperature variation of operating parameters for the
MM54HC/MM74HC family behave~ very predictably and is
due to the gain decreasing of MOSFET transistors as temperature is increased. Thus the output currents decrease
and propagation delays increase at about 0.3% per degree
centigrade.
Figure 10 shows typical propagation delays for the 74XXOO
over the - SS'C to + 12S'C temperature range. The
'HCOO's speed increases almost linearly with temperature,
whereas the LS and ALS behave differently.
A WORD ABOUT PLUG-IN REPLACEMENT OF TTL
MMS4HC/MM74HC logic implements TTL equivalent functions with the same pin outs as TTL. HC is not designed to
be directly plug-in replaceable, but, with some care, some
TTL systems can be converted to MMS4HC/MM74HC with
little or no modification. The replaceability of HC is determined by several' factors.
One factor is the difference in input levels. In systems where
all TTL is not being replaced and TTL outputs feed CMOS
inputs, the input high voltages, as specified, are not totally
compatible. Although TTL outputs will typically drive HC inputs correctly, an external pull-up resistor should be added
to ,he TTL outputs, or an MM54HCT/MM74HCT TTL compatible circuit should be used. This incompatibility tends to
limit the designer's ability to intermingle TTL and
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The MMS4HC/MM74HC family represents a major step forward in CMOS performance. It is a full line family capable of
being deSigned into virtually any application which now uses
LS-TTL with substantial improvement in power consumption. ALS and S-TTL primarily offer faster speeds than HCCMOS, but still do not have the input and output advantages
or the lower power consumption of CMOS. Because of its
high input impedance and large output drive, HC logic is
actually easier to use. This, coupled with continued expansion of the S4HCI74HC, will make it an increasingly popular
logic family.
20
20
Vcc=5.0V
Ct.=50 pF
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20
60
100
140
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Cl=50pF
VCC=5.0V
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20
60
100
TEMPERATURE I'C)
TEMPERATURE I'C)
(a)
(b)
140
Tl/F/5101-14"
-60
- 20
20
60
100
140
TEMPERATURE I'C)
TL/F/5101-15
(c)
FIGURE 10. Propagation Delay Variation Across Temperature for (a) 74LSOO (b) 74ALSOO and (c) 74HCOO
2-129
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National Semiconductor
National's Process
Application Note 339
Larry Wakeman
Enhancements Eliminate
May 1983
the CMOS SCR Latch-Up
Problem In 54HC/74HC Logic
INTRODUCTION
SCA latch-up is a parasitic phenomena that has existed in
circuits fabricated using bulk silicon CMOS technologies.
The latch-up mechanism, once triggered, turns on a parasitic SCA internal to CMOS circuits which essentially shorts
Vee to ground. This generally destroys the CMOS IC or at
the very least causes the system to malfunction. In order to
make MM54HC/MM74HC high speed CMOS logic easy to
use arid reliable it is very important to eliminate latch-up.
This has been accomplished through several layout and
process enhancements. It is primarily several proprietary innovations in CMOS processing that eliminates the SCA.
First, what is "SCA latch-up?" It is a phenomena common
to most monolithic CMOS processes, which involves "turning on" a four layer thyristor structure (P-N-P-N) that appears from Vee to ground. This,structure is formed by the
parasitic substrate interconnections of various circuit diffusions. It most commonly can be turned on by applying a
voltage greater than Vee or less than ground any input or
output, which forward biases the input or output protection
diodes. Figure 1 schematically illustrates these diodes found
in the MM54HC/MM74HC family. Standard C04000 and
MM54C/MM74C logic also has a very similar structure.
These diodes can act as the gate to the parasitic SCA, and
if enough current flows the SCA will trigger. A second method of turning on' the SCA is to apply a very large supply
voltage across the device. This will breakdown internal diodes causing enQugh current to flow to trigger latch-up. In
HC logic the typical Vee breakdown voltage is above 10V so
this method is more uncommon. In either case, once the
SCA is turned on a large current will flow from Vee to
ground, causing the CM0S circuit to malfunction and pOSSibly damage itself.
CMOS SCA problems can be minimized by proper system
design techniques or added external protection circuits, but
obviously the reduction or elimination of latch-up in the IC
itself would ease CMOS system design,' increase system
reliability and eliminate additional circuitry. For this reason it
was important to eliminate this phenomena in National's
'
.
high speed CMOS logic family.
Characterization of this proprietary high speed CMOS process for latch up has verified the elimination of this parasitic
mechanism. In tests conducted under worst case conditions
(Vee=7V and TA=125°C) it has been impossible to latchup these devices on the inputs or on the outputs.
In testing for latCh-up, caution must be exercised when try- '
ing to force large currents into an IC. As with any integrated
circuit there are maximum limitations to the current handling
capabilities of the internal metalization, and diodes, and
thus they can be damaged by excessive currents. This is
discussed later in the test section.
To enable the user to understand what latch-up is and how
it has been eliminated, it is useful to review the operating of
a simple discrete SCR, and then apply this to the CMOS
SCA. Since most latch-up problems historically have been
caused by extraneous nois!, and system transients, the AC
characteristics of CMOS latch are presented. Also various
methods of external and internal protection against latch-up
is discussed as well as example test methods for determining the latch up susceptibility of CMOS IC's.
SIMPLE DISCRETE SCR OPERATION
To understand the behavior of the SCA structure parasitic
to CMOS IC's, it is first useful tore~iew the basic static
operation of the discrete SCA, and then apply it to the
CMOS SCA. There are two basic trigger methods for this '
SCA. One is turning on the SCA by forcing current into its
gate, and the second is by placing a large voltage across its
" anode and cathode. Figure 2 shows the basic four layer
structure biased into its forward blocking state. The SCA
action can be more easily understood if this device is modeled as a cross coupled PNP and NPN transistor as shown
in Rgure3.
In the case of latch-up caused by forward biasing a diode, if
current is injected into the base of 02, this transistor turns
on, and a collector current beta times its base current flows
into the base of 01. 01 in turn amplifies this current by beta
and feeds it back into the base of 02, where the current is
again amplified. If the product of the two transistors' Beta
becomes greater than one, B(NPN)xB(PNP»I, this current
multiplication continues until the transistors saturate, and
the SCA is triggered. Once the regenerative action occurs a
large anode current flows, and tlie SCA will remain on even
aiter the gate current is removed, if enough anode current
flows to sustain latch-up. However, if the transistor current
gains are small·no self sustaining positive feedback will occur, and when the base current is removed the collector
current will stop. In a similar manner the SCA can be triggered by drawing current by forward biasing the base of 01.
. . - - - - - -...........--,ollTl'lli
DIODES
GATE 1 (Ol)
POLYSILICON
RESISTOR
+-t~-+-c::> OUTPUT
GATE'ZIGZ)
DIFFUSED DIODE
RESISTOR
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TLiFI5346-2
FIGURE 2. Simplified SCR Structure
FIGURE 1. Schematic Diagram of Input and Output
Protection Structures
2·130
product of the PNP and NPN be greater than one in order
for the SCA to trigger applies here as well. This leakage current trigger is characteristic of Schottkey diode operation.
THE CMOS SCR: STATIC DC OPERATION
For discussion purposes CMOS SCA latch up characteristics can be divided into two areas. One is the basic operation of the SCA when static DC voltages are applied, and
the second is the behavior when transients or pulses are
.
applied.
First looking at the device statically, the parasitic SCA in
CMOS integrated circuits is much more complex and its triggering is somewhat different than the simple SCA already
discussed. However, the regenerative feedback effect is basically the same. Figure 4a shows a simplified P - well
CMOS structure illustrating only the diffusions and the resultant parasitic transistors. The NPN transistor is a vertical
device whose emitter is formed by n + diffusions. The Pwell forms the base and the N - substrate forms the collector of the NPN. The PNP transistor is a lateral device. lts
emitter is formed by p + diffusions, its base is the N - substrate, and its collector is the P - well.
.:I---t-oO GATE (Gl)
GATE (G2) o-.....- - C
TLlF/5346-4
FIGURE 3. Cross-Coupled Transistor Model of SCR
Figure 4b illustrates a cross section of a simplified N - well
process .and its corresponding parasitic bipolar transistors.
In this process the NPN is a lateral device and the PNP is
vertical. Essentially the description of the P- well SCA is
the same as the N - well version except the NPN is a low
gain lateral device and the PNP is a high gain vertical transistor. Thus the following discussion for the P- well also
applies to the N - well with this exception.
The second case, the SCA may also be triggered without
injecting any gate current. In the forward blocking state the
small leakage current that is present does not trigger the
SCA, but if the VOltage is increased to a point where significant leakage currents start conducting, these ciJrrents could
also trigger the SCA, again forming a low impedance path
through the device. The same requirement that the Beta
vee
GND
TLlF/5346-6
(a)
GND
P- SUBSTRATE
TLlF/5346-5
(b)
FIGURE.4. Simplified Cross Section of CMOS Processes a) P - well and b) N - well
2·131
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The transistors for the P- well CMOS process are drawn
schematically in Figure 5, so that their cross coupled interconnection is more easily seen. The SCR structure in Figure
5 differs from that of Figure 3 in two ways. First, the transis-"
tors of Figure 5 have multiple emitters, due to the many
diffusions on a typical die. One emitter of each trShsistor
could function as the trigger input to the ,SCR. Secondly, R1
and R2 have been added and are due to P - and N - substrate resistances between the base of each transistor 'and
the substrate power supply contacts.
with many transistors interconnected by many resistances.
Although still somewhat simiplified, Figure 6 attempts to illustrate how the parasitics on a chip connect. It is important
• to remember that any transistor or diode diffusion can paraSitically form part of the SCA. In the figure transistor 01 and
02 are single emitter transistors formed by the input protection diodes. Internal P and N channel transistors have no
external connection and are represented by 03 and 04. 05
and 06 represent output transistor diffusions, and the second emitter corresponds to the output. All of these transistors are connected together by the N - substrate and Pwell resistances, which are illustrated by the resistor mesh.
Gl
G2
GND
'01
TLlF/5346-7
::::t--t---'
FIGURE 5. Schematic of Simple SCR Model
~::::t--t---t--~
Like the discrete SCR there are two basic methods of turning the CMO~ SCR on. The first method is however slightly
different. In the CMOS parasitic SCR 'Current cannot be directly injected into the base of one of its transistors. Instead
either node G1 must be raised above Vee enough to turn on
01, or node G2 must be lowered below ground enough to
turn on 02. If G1 is brought above Vee, current is injected
from the emitter of 01 and is swept to the collector of 01.
The collector of 01 feeds the base of 02 and also R2. R2
has the effect of stealing current from the 'base of 02, but as
current flows through R2 a voltage will appear at the base of
02. Once this voltage reaches 0.6 volts 02 will turn on and
feed current from its collector back into R1 and into 01. If·
0.6 volts is generated across R1, 01 then turns on' even
more.
02
TLlF/5346-8
FIGURE 6. Distributed Model of CMOS SCR
If any of the emitters associated with the trigger inputs G1G4 become forward biased the SCR may be triggeredrAlso
due to the intertwined nature of this structure, part of the
SCR may be initially latched up. In this case only a limited,
amount of current may flow, but this limited latch up may
spread and cause other parts to be triggered until eventually ,
the whole chip is involved.
Again, if the two transistors have enough gain and enough
anode current flows to sustain the SCR, it will turn on; and
remain on even after G1 is returned to Vee. The actual requirements for latch up are altered by the two resistors, R1
and R2. Since the resistors shunt some current away from
the base of both transistors, the resistors essentially reduce
the effective gains of the transistors. Thus the transistors
must ,actually have much higher gains in order to achieve an
overall SCR loop gain greater than one, and hence enable
the SCR to trigger. The actual equations to show quantitatively how the resistors effect the SCR's behavior could be
derived, but it is sufficient to notice that as R1 and R2 become smaller the SCR becomes harder to turn on. IC. designers utilize this to reduce latch up.
In general the trigger to the SCR has been cGnceptualized
as a current, since ideally the CMOS input looks Jnto the
base of the SCR transistors. However this may not be quite
true. There may be some' resistance in series with each
base, due to substrate or input protection resistances. In
newer silicon gate CMOS processes, MM54HC/MM74HC
for example, a poly-silicon resistor is used for electrostatic
protection, and this enables larger voltages to be applied to
the circuit pins without causing latchup. This is because the
poly resistor actually forms a current limit resistor in series
with the diodes. In most applications the designer is more
concerned with accidental application of a large voltage,
and the use of the poly resistor internally enables good voltage resistance to latch up. CMOS outputs are directly connected to paraSitic output diodes since no poly resistor can
be placed on an output without degrading output current
drive. Thus the output latch up mechanism is usually
thought of as a current.
'
The second method of turning on the SCR mentioned earlier also applies here. If the supply voltage is raised to a large
value, and internal substrate diodes start breaking down excessive leakage currents will flow possibly triggering the
SCA. The resistors also affect this trigger method as well,
since they steal some of the leakage currents from 01 and
Q2, and hence it takes more current to trigger the SCA. In
higli speed CMOS the process enhancements reduce the
transistor betas and hence eliminate latch up by this mecha'
nism as well.
While useful, the SCR model of Figures 4 and 5 is very
simplified, since in actuality the CMOS SCR is a structure
2·132
Temperature variations will affect the amount of current required to trigger the SCR. This is readily understandable
since temperature effects the bipolar transistor's gain and
the resistance of the base-emitter resistors. Generally, as
the temperature is increased less current is needed to
cause latch-up. This is because as temperature increases
the bipolar transistor's base-emitter voltage decreases and
the base-emitter resistor value increases. Figure 7 plots trigger current versus temperature for a sensitive CMOS input.
This data was taken on a CMOS device without any layout
or process enhancements to eliminate latch up. Increasing
. temperature from room to 125'C will reduce the trigger current by aQout a factor of three. Once the circuit is latched
up, heating of the device die caused by SCR currents will
actually increase the susceptibility to repeated latch up.
80
~
60
I
I
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~~
40
~20
that this doesn't happen. and care in the layout and circuit
design of 54HC174HC logic has ensured that this will be
avoided.
THE CMOS SCR: TRANSIENT BEHAVIOR
With the introduction of fast CMOS logic the transient nature of the CMOS SCR phenomena becomes more important because signal line ringing and power supply transients
are more prevalent in these systems. Older metal gate
CMOS (CD4000 & 74HC) circuits have slow rise and fall
times which do not cause a large amount of line ringing.
Power supply spiking is also somewhat less. again due to
slow switching times associated with these circuits.
The previous discussion assumed that the trigger to the
CMOS SCR was essentially static and was a fixed current.
Under these conditions a certain value current will cause
the SCR to trigger. but if the trigger is a short pulse the peak
value of the pulse current that will trigger the SCR can be
much larger than the static DC trigger current. This is due to
the poor frequency characteristics of the SCA.
For short noise pulses. < 5 ".s. the peak current required to
latch up a device is dependent on -the duty cycle of the
pulses. At these speeds it is the average current that causes latCh-up., For example. if a 1 MHz 50% duty cycle over
voltage pulse train is applied to a device that latched with
20 mA DC current. then typically the peak current required
will be about 40 mA. For a 25% duty cycle the peak current
would be 80 mA. An example of this is shown in Figure 8
which plots latch up current against over-voltage pulse
width at 1 MHz.
tl
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TEMPERATURE-'C
TL/F/5346-9
FIGURE 7. Temperature versus SCR Trigger Current for
Special CMOS Test Structure
~
120
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DUTY CYCLE := WIT ~ 10011
,!.
OTHER LATCH UP TRIGGER METHODS
There are some other methods of latching up CMOS circuits. they are not as circuit design related and shall only be
briefly mentioned. The first is latch up due to radiation bo'mbardment.ln hostile environments energetic atomic particals can bombard a CMOS die freeing carriers in the substrate. These carriers then can cause the SCR, to trigger.
This can be of concern in high radiation environments which
call for some sort of radiation hardened CMOS logic.
Another latch up mechanism is the application of a fast rise
or fall spike to the supply inputs of a CMOS device. Even if '
insufficient current is injected into the circuit the fast voltage
change'could trigger latch up. This occurs because the volt-'
age change across the part changes the junction depletion
capaCitances. and this change in capacitance theoretically
could cause a current that would trigger the SCR latch. In
actual practice this is very difficult to do because the response time of the SCR (discussed shortly) is very poor.
This is hardly a problem since power supplies must be adequately decoupled anyway.
j-T...jI=lMHZ
~ 100 1-----'.if---l-jUl-
B
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~
80
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;
~ INPUT CURRENT
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20
40
60
80
PULSE DUTY CYCLE-II
100
TL/F/5346-10
FIGURE 8. Trigger Current of SCR of Input Overvoltage
Pulses at High Repetition Rate on Special Test Unit
If the pulse widths become long. many microseconds. the'
latch up current will approach the DC value even for low
duty cycles. This is shown in Figure 9 which plots peak trig,
ger current vs pulse width for the same test device used in
Figure 8. The repetition rate in this case is a slow 2.5 kHz
(period = 400 ".s). These long pulse widths approach the
trigger time of the SCR. and thus pulses lasting several microseconds are long enough to appear as DC voltages to
the SCA. This indirectly indicates the trigger speed of the
SCR to be on the order'of ten to fifteen microseconds. This
is however dependent on the way the IC was designed and
the processing used.
In normal high speed systems noise spikes will typically be
only a few nanoseconds in duration. and the average duty
cycle will be small. So even a device that is not deSigned to
A third latch up cause which is completely internal to the IC
itself and is out of the control of the system designer is
internally triggered latch up. Any internal switching node
connects to a diode diffusion. and as these diffusions switch
the junction depletion capacitance associated with these
nodes changes causing a current to be generated. This current could trigger the SCA. The poor frequency response of
the SCR tends to make this difficult. but as chip geometries
are shrunk packing densities will increase and the gain of
the lateral PNP transistor increase. This may increase the
, latch up susceptibility. It is up to the IC designer to ensure
2·133
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input or output voltages may forward bias the input or output
diodes then some external circuitry may need to be added
to eliminate possible SCR triggering. As with the previous
discussions of latch-up preventing SCR latch-up falls into
two categories: the static case, and the transient condition .
Each is related but has some unique solutions.
In the static condition to ensure SCR latch'up does not occur, the simplest solution is to design CMOS systems so
that their input/output diodes don't become forward Iliased.
To ease this requirement some special circuits that have
some of their input protection diodes removed are provided,
and this enables input voltages to exceed the supply range.
These devices are MM54HC4049/50,· CD4049/50, and
MM54C901/2/3/4.
1=2.5kHz
~
25
'"
15 .
3D
45
60
PULSE WlDTH-~s
TL/F/5346-11
FIGURE 9. Trigger Current of Pulse on Special Test Unit ,
SCR for Single Transient Overvoltage
be latch up resistant, will probably not latch up even with
significant line ringing on its inputs or outputs (Then again
. . .). However, in some systems where inductive or other
loads are used transients of several microseconds can be
easily generated. For example, some possible applications
are automotive and relay drivers. In other CMOS logiC families spikes of this nature are much more likely to cause the
SCR to trigger, but here again MM54HC/MM74HC high
speed CMOS is immune.
If standard logic is used and input voltages will exceed the
supply range, an external network should be added that protects the device by either clamping the input voltage or by
limiting the currents which flow through the internal diodes.
Figure 10 illustrates various input and output diode clamping
circuits that shunt the diode currents when excessive input
voltages are applied, Usually either an additional input or
output diode is required, rarely both, and if the voltages only
exceed one supply then only one diode is necessary. If an
external silicon diode is used the current shunt is only partially effective since this diode is in parallel with the internal
silicon protection diode, and both diodes clamp to about
O.7V.
PREVENTING SCR LATCH UP:
USER SYSTEM DESIGN SOLUTIONS
A second method, limiting input current, is very effective in
preventing latch-up, and several designs are shown in
Figure 11. The simplest approach is a series input resistor. It
is recommended that this resistor should be as large as
possible without causing excessive speed degradation yet
ensure the input current is limited to a safe value. If speed is
critical, it is better to use a combination diode-resistor network as shown in Rgures 11b and 11c. These input networks
effectively limit input currents while using lower input resiStors. The series resistor may not be an ideal solution for
protecting outputs because it will reduce the effective drive
of the output. In most cases this i~ only a problem when the
output must drive a lot of current or must switch large capacitances quickly.
SCR latch-up can be prevented either on the system level
or on the IC level. Since National's MM54HC/MM74HC se·
ries will not latch up, this eliminates the need for the system
deSigner to worry about preventing latch up at the system
level. This not only eases the deSign, but negates the need
to add external diodes and resistors to protect the CMOS
circuit, and hence additional cost. (Note however that even
though the devices don't latch up, diode currents should be
limited to their Absolute Maximum Ratings listed in the Data
Sheets) .•
If one is using a CMOS device that may latch up, older
CD4000 CMOS or another vendors ':IC for example, and its
TL/F/5346-12
Schottky Diodes
Germanium Diodes
Zener Diodes
~
~
~
FIGURE 10. External Input and Output Protection Diodes Circuits for Eliminating SCR Latch-up
~
. L ~ .~ . . -~.~
~TY~~~~
GND 01 VSS
liND OR ¥Ss
GND OR VIs
TLlF/5346-13
(a)
(b)
(c)
FIGURE 11. Input Resistor and Resistor-Diode Protection Circuits for Eliminating Latch-up
2-134
A third approach is instead of placing resistors In series with
the inputs -to place them in series with the power supply
lines as shown in Figure 12. The resistors must be bypassed
by capacitors so that momentary switching currents don't
produce large voltage transients across R1 and R2. These
resistors can limit input currents but primarily they should be
chosen to ensure that the supply current that can flow is
less than the holding current of the SCA. Thus even though
the input current can cause lalch up it cannot be sustained
and the IC will not be damaged.
Most methods previously employed to eliminate latch up are
either not effective, increase the die size significantly, and!
or degrade MOS transistor performance. The process enhancements employed on 54HC!74HC logic circumvent
these problems. Primarily it is effective without degrading
MOS performance.
When deSigning CMOS integrated circuits, there are many
ways that the SCR action of these circuits can be reduced.
One of the several methods of eliminating the SCR is to
reduce the effective gain of at least one of the transistors,
thus eliminating the regenerative feedback. This can be accomplished either by modifying the process and! or by inserting other parasitic structures to shunt the transistor action. Also the substrate resistances modeled as R1 and R2
in Figures 4 and 5 can be reduced. As these resistances,
approach zero more and more current is required to develop
enough voltage across them to turn on the transistors.
'"
"
As mentioned, the current gains of the NPN and PNP parasitic transistors directly affect the current required to trigger
the latch. Thus some layout and process enhancements
can be implemented to reduce the NPN and PNP Betas. In
a P-well process the gain of the vertical NPN is determined
by the specific CMOS process, and is dependent on junction depths and doping concentrations. These parameters
also control the performance of the N-MOS transistors as
well and so process modification must be done without degrading CMOS performance. To reduce the gain of the vertical PNP the doping levels of the P- well can be increased.
This will decrease minority carrier lifetimes. It will also reduce the substrate resistance lowering the NPN base-emitter resistance. However this will increase parasitic junction
capacitances, and may affect NMOS threshold voltages and
carrier mobility. The depth of the well may be increased as
well. This will reduce layout density due to increased lateral
diffusion, and increase processing time as it will take longer
to drive the well deeper into the substrate.
'
.
'ND
TL/F/5346-14
FIGURE 12. Supply Reslstor-Capacltor Circuits for
Eliminating Latch-up
This last solution has the advantage of fewer added components, but also has some disadvantages. This method may
not, prevent latch up unless the resistors are fairly large, but
this will greatly degrade the output current drive and switching characteristics of the device. Secondly, this circuit protects the IC from damage but if diodes currents are applied
causing large supply currents, the circuits will logically malfunction where as with other schemes logic malfunction can
be prevented as well.
PREVENTING LATCH UP: IC DESIGN SOLUTIONS
The previous latch up solutions involve adding extra components and hence extra cost and board space. One can
imagine that in a microprocessor bus system if for some
reason the designer had to protect each output of several
CMOS devices that are driving a 16-bit address bus that up
to 32 diodes and possibly 16 resistors may need to be added. 'Thus for the system designer the preferable solution is
, to use logic that won't latch up.
BND
INPUT
DIDDE
The lateral PNP's gain is determined by the spacing of input
and output diode diffusions to active circuitry and minority
carrier life times in the N - substrate. The carrier life times
are a function of process doping levels as well, and care
must be exercised to ensure no MOS transistor performance degradation. Again the doping levels of the substrate
can be increased, but this will increase parasitiC junction
capacitances, and may alter the PMOS threshold characteristics. The spaCing between input! output diodes and other
N-CHANNEL DRAINI
OUTPUT DIODE
VCC
p-
ADDITIDNAL
SUBSTRATE
CDNTACTS
"DUMMY"
COLLECTORS
ADDITIONAL
SUBSTRATE
CONTACTS
rL/F/5346-15
FIGURE 13. Simplified CMOS Cross Section Showing Added Latch-up Reduction Structures
2-135
diffusions can be increased. This will increase the PNP's
base width, lawering its beta. This may be done only a limited amount without significantly impacting die size and cast.
These methads are emplayed in 54HC174HG CMOS logic,
but in addition processing enhancements were made that
effectively eliminate the PNP transistar. The primary enhancement is .a modificatian ta the doping prafile of the Nsubstrate (P - well pracess). This lawers the conductivity .of
the substrate material while maintaining a lightly dape surface concentration. This allows optimum performance
NMOS and PMOS transistars while dramatically reducing
the gain of the PNI': and its base-emitter resistance. The
gain .of the PNP is reduced because the minarity carrier lifetimes are reduced. This modificatian also increases the effectiveness of the "dummy" collectars by maintaining carriers closer ta the surface. This then eliminates the SCR latch
up mechanism.
Anather method for enhancing the latch-up immunity of
MM54HC/MM74HC is to short out the SCR by creating additional parasitic transistars and reducing the effective substrate reSistances. These techniques employ the use .of
ringing structures (termed guard rings) ta surraund inputs
and outputs with diffusions that are shorted to Vee or
ground. These diffusions act to lawer the substrate resistances, making it harder ta turn on the bipolar transistors.
They alsa act "dummy" collectors that shunt transistar actian by callecting charges directly to either Vee or ground,
rather than thraugh active circuitry. Figure 13 shows a crass
sectian .of hqw this might look and Figure 14 schematically
illustrates haw these techniques ideally madify the SCR
structure.
Ideally, in Figure 14 if the inputs are farward biased any
transistor action is immediately shunted to Vee .or ground
thraugh the "dummy" collectars. Any current not collected
will flow thraugh the resistors, which are now much lawer in
value and will nat allaw the oppOSite transistor ta turn on.
5.0 TESTING SCR LATCH·UP
There are several methads and test circuits that can be
employed to test for latch-up. The .one primarily used ta
characterize the 54HC174HC lagic family is shown in Figure
15. This circuit utilizes several supplies and various meters
ta either force current into the Vee diodes or force current
out of the ground diodes. By cantrolling the input supply a
current is farced into or aut .of an input or output of the test
device. As the input supply voltage is increased the current
inta the diade increases. Internal transistar action may
cause some supply current ta flow, but this shauld nat be
considered latch up. When latch-up occurs the power supply current will jump, and if the input supply is reduced ta
zero the power supply current should remain. The input trigger current is the input current seen just priar to the supply
current jumping.
Vee
Testing latch-up i& a destructive test, but in .order ta test
54HC174HC devices without causing immediate damage,
test limits for the amaunt of input or output currents and
supply valtages should be .observed. Even thaugh immediate damage is avoided, SCR latch-up test is a destructive
test and the IC performance may be degraded when testing
ta these limits. Therefore parts tested ta these limits should
not be used far design or praduction purpases. In the case
of National's high speed CMOS lagic the definition .of "Iatchup praof" requires the fallawing test limits when using the
standard DC pawer supply test as is shawn in Figure 15.
TLfFf5346-16
FIGURE 14. Schematic Representation of SCR with
Improvements to Reduce Turn On.
Unfartunately in .order ta reduce latch up these techniques
add quite significantly ta the die size. and still may nat be
campletely effective.
1. Inputs: When testing latch-up on CMOS inputs the current into these inputs should be limited ta less than
70 mAo Application of currents greater than this may
damage the input pratection paly resistor or input metalization, and prevent further testing .of the IC.
2. Outputs: When testing outputs there is a limit to the met- .
alization's current capacity. Output test currents shauld
be limited to 200 mA. This limitatian. is due again ta metalizatian shart term current capabilities, similar to inputs.
Application of currents greater than this may blow aut the
output.
3. Supply: The power supply voltage is recommended to be
7.0V which is at the absalute maximum limit specified in
54HC174HC and is the worst case valtage for testing
latch-up. If a device latches up it will shart out the power
supply and self destruct. (Another Vendors HC may
latch-up for example.) It is recOmmended that to prevent
immediate destruction of ather vendars parts that the
pawer supply be current limited to less than 300 mA:
The ineffectiveness .of the ringing structures at completely
eliminating latch up is far .one because the callectars are
.only surface devices and carriers can be injected very deep
into the N - substrate. Thus they can very easily ga under
the fairly small "dummy" callectars and be callected by the
relatively large active P- well. A passible salutian might be
ta make the callectar diffusians much deeper. This suffers
fram the same drawbacks as making the well deeper, as
well as requiring additianal mask steps increasing pracess
camplexity. Secandly, the base emitter resistances can be
reduced .only sa much, but again only the surface resistances are reduced. Some transisior action can occur under the
P- well and deep in the N- bulk where these surface
shorts are .only partially effective.
The abave discussion described modifications to a P- well
pracess. For an N - well process the descriptians are the
same except that instead of a P - well an N - well is used
resulting in a vertical PNP instead of an NPN aM a lateral
NPN instead .of a PNP.
2·136
l>
In almost all instances at high temperature, if it is going to
occur, latch-up will occur at current values between
0-50 mA.
There are a few special considerations when trying to measure worst case latch-up current. Measuring input latch-up
current is straight forward, just force the inputs above or
below the power supply, but to measure an output it must
first be set to a high level when forcing it above Vee, or to a
low level when forcing it below ground. When measuring TriState outputs, the outputs should be disabled, and when
measuring analog switches they should be either left open
or turned off.
To measure the transient behavior of the test device or to
reduce IC heating effects a pulse generator can be used in
place of the input supply and an oscilloscope with a current
probe should then replace the current meter. Care should
be exercised to avoid ground loops in the test hardware as
this may short out the supplies.
Although there are several methods of testing latch-up, this
method is very simple and easy to understand. It also yields
conservative data since manually controlling the supplies is
a slow process which causes localized heating on the chip
prior to latch-up, and lowers the latch-up current.
6.0 CONCLUSION
SCR latch-up in CMOS circuits is a phenomena which when
understood can be effectively ,controlled both from the integrated circuit and system level. National's proprietary
CMOS process and layout considerations have eliminated
CMOS latch-up in the MM54HC/MM74HC family. This will
increase the ease of use and design of this family by negating the need for extra SCR protection circuitry as well as
very favorable impact system integrity and reliability.
Testing SCR Latch-Up of HCMOS
VCC DIODE TEST CIRCUIT
GROUND DIODE TEST CIRCUIT
AMMETER
AMMETER
r-----------~--~A
+
7V
-=-
TL/F/5346-17
TA = 125'C
FIGURE 15. Bench Test Setup for Measuring Latcll-up
2·137
Z
W
~
National Semiconducter
Appligation Note 340
Thomas B. Mills
May 1983
HCMOS Crystal Oscillators
With the advent of high speed HCMOS circuits, it is possible
, to build systems with clock rates of greater than 30 MHz.
The familiar gate osciliator circuits used at low frequencies
work well at higher frequencies and either L-C or crystal
resonators maybe used depending on the stability required.
,Above 20 MHz, it becomes expensive to fabricate fundamental mode crystals, so overtone modes are used.
~o
The Pierce oscillator is one of the more popular circuits, and
is the foundation for almost all single gate oscillators in use
today. In this circuit, Figure 2, the signal from the input to the
output of the amplifier is phase shifted 180 degrees. The
crystal appears as a large inductor since it is operating in
the parallel mode, and in conjunction with CA and Ca, forms
a pi network that provides an additional 180 degrees of
phase shift from output to the input CA in series with Ca
Co
-A
+ ..-------D-~C"':""RY"':""S"':""TA-L---.., +
"
-1'
TL/F/5347-1
Crystal Equivalent Circuit
EQUIVALENT
r- -L;- - 81-- -c;-1
I
IL _________ JI
TL/F/5347-3
FIGURE 2. Pierce Oscillator
TLlF/5347-2
plus any additional stray capacitance form the load capacitance for the crystal. In this circuit, CA is usually made about
the same value as Ca, and the total value of both capacitors
in series is the load capacitance of the crystal which is gen- '
erally chosen to be 32 pF. making the value of each capacitor 64'pF. The approximation equations of the load impedance, Zl, presented to the output of the crystal oscillator's
,amplifier by the crystal network is:
Reactance of Crystal Resonator
FIGURE 1
Basic Oscillator Theory
The equivalent circuit of a quartz crystal, and its reactance
characteristics with frequency are shown in Figure 1. FR is
called the resonant frequency and is where L1 and C1 are in
series resonance and the crystal looks like a small resistor
R1. The frequency FA is the antiresonant frequency and is
the point where L1-C1 look inductive and resonate with Co
to form the parallel resonant frequency FA, FR,and FA are
usually less than 0.1 % apart. In specifying crystals, the frequency FR is the oscillation frequency to the crystal in a
series mode circuit, and FR is the parallel resonant frequency. In a parallel mode circuit, the oscillation frequency will
be slightly below FA where the inductive component of the
L1 -C1 arm resonates with Co and the external circuit capaCitance. The exact frequency is often corrected by the
crystal manufacture to a specified load capacitance, usually
20 or 32 picofarads.
TABLE I. Typical Crystal Parameters
Parameter
, R1
L1
C1
Co
a
32kHz
fundamental
200kHz
fundamental
2 MHz
fundamental'
overtone
2OOkO
7000H
.OO3pF
1.7 pF
100k
2kO
27H
0.024pF
9pF
18k
1000
529mH
0.012pF
4pF
54k
200
11mH
O.oo26pF
6pF
100k
30 MHz
Where XC= -j/CllCa and RL is the series resistance of the
crystal as shown in Table I. Also CIl = 21Tf where f is the
frequency of oscillation.
The ratio of the crystal network's input voltage to it's output
voltage is given by:
eA = CIlCa = Ca
ea
CIlCA
CA
CA and Ca are chosen such that their series combination
capacitance equals the load capacitance specified by the
manufacturer, ie 20 pF or 32 pF as mentioned. In order to
oscillate the phase shift at the desired frequency around the
oscillator loop must be 360" and the gain of the oscillator
loop must be greater ot equal to one, or:
(AAl(AF)~1
Where AA is amplifier gain and AF is crystal network voltage
gain of the crystal1T networj<: eA/ea. Thus not only should
the series combination of Ca and CA be chosen. The ratio of
the two can be set to adjust the loop gain of the oscillator.
For example if a 2 MHz oscillator is required. Then
RL = 1000 (Table I). If eA/ea = 1 and the crystal requires a
32 pF load so Ce = 64 pF and then CA becomes 64 pF also.
The load presented by the 'crystal network is ZL = (%1T (2
MHz) (64 pF)2)l100= 16 kll.
2·138
The CMOS Gate Oscillator
When designing with buffered gates, the value of R2 or Cs
may be increased by a factor of 10 or more. This will increase the voltage loss around the feedback loop which is
desirable since the gain of the gate is considerably higher
than that of an unbuffered gate.
A CMOS gate sufficiently approaches the ideal amplifier
shown above that it can be u'sed in almost the same circuit.
A review of mamifacturers data sheets will reveal there are
two types of inverting CMOS gates:
CA and Cs form the load capacitance for the crystal. Many
crystals are cut for either 20 to 32 picofarad load capacitance. This is the capacitance that will cause the crystal to
oscillate at its nominal frequency. Varying this capacitance
will vary the frequency of oscillation. Generally designers
work with crystal manufacturers to select the best value of
load capacitance for their application, unless an off the shelf
crystal is selected.
a) Unbuffered: gates composed of. a single inverting stage.
Voltage gain in the hundreds.
b) Buffered: gates composed of three inverting stages in
series. Voltage gains are greater than ten thousand.
CMOS gates must be designed to drive relatively large
loads and must supply a fairly large amount of current. In a
single gate structure that is biased in its linear region so
both devices are on, supply current will be high. Buffered
gates are designed with the first and second gates to be
much smaller than the output gate and will dissipate little
power. Since the gain is so high, even a small signal will
drive the output high or low and little power is dissipated. In
this manner, unbuffered gates will dissipate more power
than buffered gatE;ls.
Both buffered and unbuffered gates maybe used as crystal
oscillators, with only slight deSign changes in the circuits.
High Frequency Effects
The phase shift thru the gate may be estimated by considering it's delay time:
Phase Shift = Frequency X Time delay X 360'
The "typical gate oscillator" works well at lower frequencies
where phase shift thru the gate is not excessive. However,
above 4 MHz, where 10 nsec of time delay represents 14.4'
of excess phase shift, R2 should be changed to a small
capacitor to avoid the additional phase shift of R2. The value of this capacitor is approximately 1/wC where w=21Tf,
but not less than about 20 pF.
RF=10M2
.~~.
...... 74HCU04
.----fID'I~----4
I I
I c a 62pF
=rCb 62pF
r c a 62pF
Ell
T
Cb =62 PF
TLlF/5347-5
TL/F/5347-4
FIGURE 3. Typical Gate Oscillator
FIGURE 4. Gate Oscillator for Higher Frequencies
In this circuit, RF serves to bias the gate in its linear region,
insuring oscillation, while R2 provides an impedance to add
some additional phase shift in conjunction with Cs. It also
serves to prevent spurious high frequency oscillations and
isolates the output of the gate from the crystal network so a
clean square wave can be obtained from the output of the
gate. Its value is chosen to be roughly equal to the capacitive reactance of Cs at the frequency of oscillation, or the
value of load impedance ZL calculated above. In this case,
there will be a two to one loss in voltage from the output of
the gate to the input of the crystal network due to the voltage divider effect of R2 and ZL. If CA and Cs are chosen
equal, the voltage at the input to the gate will be the same
as that at the input to the crystal network or one half of the
voltage at the output of the gate. In this case, the gate must
have a voltage gain of 2 or greater to oscillate. Except at
very high frequencies, all CMOS gates have voltage gains
well in excess of 10 and satisfactory operation should result.
Theory and experiment show that unbuffered gates are
more stable as oscillators by as much as 5 to 1. However,
unbuffered gates draw more operating power if used in the
same circuit as a buffered gate. Power consumption can be
minimized by increasing feedback which forces the gate to
operate for less time in its linear region.
Improving Oscllator Stability
The CMOS gate makes a' mediocre oscillator when compared to a transistor or FET: It draws mpre power and is
generally less stable. However, extra gates are often available and are often pressed into service as oscillators. If
improved stability is required, especially from buffered gate
oscillators, an approach shown in Figure 5 can be used.
. --t> 1RL=l,k~
-1D~-::·g~;
fca40PF
'!Cb=300 PF
TL/F/5347-6
FIGURE 5. Gate oscillator with improved stability
2·139
~
«
Z
RF: Sets the' bias point, should be as large as practical.
In this circuit, CA and CB are made large to swamp out the
effects of temperature and supply voltage change on the
gate input, and output impedances. A small capacitor in series with the crystal acts as the crystal load and further isolates the crystal from the rest of the circuit.
R1: Isolates the crystal network from the gate output and
provides excess phaseshift decreasing the probability of
spurious oscillation at high frequencies. Value should be ap~
proximately equal to input impedance of the crystal network
or reactance of CB at the oscillator frequency. Increasing:
value will decrease the amount of feedback and improve
stability.
Overtone Crystal Oscillators
At frequencies above 20 MHz, it becomes increasingly difficult to cut or work with crystal blanks and so generally a
crystal is used in it's overtone mode. Also,' fundamental
mode crystals above this frequency have less stability and
; greater aging rates. All crystals will exhibit the same reactance vs. frequency characteristics at odd overtone frequencies that they do at the fundamental frequency. However, the overtone resonances are not exact multiples of
the fundamental, so an overtone crystal must be specified
as such.
CB: Part of load for crystal network. Often chosen to be
twice the value of the crystal load capacitance. Increasing
value will increase feedback.
CA: Part of crystal load network. Often chosen to be twice
the value of the crystal load capacitance. Increasing value
will increase feedback.
CL: Used in place of Rl 'in high frequency applications.
Reactance should !>e approximately equal to 'crystal network input impedance.
In the design of an overtone crystal oscillator, it is very important to suppress the fundamental mode, or the circuit will
try to oscillate there, or worse, at both the fundamental and
the overtone with little predictability as to which. Basically,
this requires that the crystal feedback network have more
gain at the overtone frequency than the fundamental. This is
usually done with a frequency selective network such as a
tuned circuit.
Oscillator design is an imperfect art at best. Combinations
of theoretical and experimental design techniques should
be used.
A. Do not design for an excessive amount of gain around
the feedback loop. Excessive gain will lead to instability
and may result in the oscillator not being crystal controlled.
'The circuit in Figure 6 operates in the parallel mode just as
the Pierce oscillator above. The resonant circuit LA-CB is
an effective short at the fundamental frequency, and is
tuned somewhat below the deferred crystal overtone frequency. Also, CL is chosen to suppress operation in the
fundamental mode.
B. Be sure to worst case the design. A resistor may be
added in series with the crystal to simulate worst case
crystals. The circuit should not oscillate on any frequen- ,
cy with the crystal out of the circuit.
C. A quick check of oscillator peformance is to measure the
frequency stability with ,supply voltage variations. For
HCMOS gates, a change of supply voltage from 2.5 to 6
volts should result in less than 10 PPM change in frequency. Circuit value changes should be evaluated for
improvements in stability.
The coil LA may be tuned to produce maximum output and
will affect the oscillation frequency slightly. The crystal
should be specified so that 'proper frequency is obtained at •
maximum output leyel from the gate.
Some Practical Design Tips
In the above circuits, some generalizations can be made
regarding the selection of component values.
10=31 MHz
RF=10 MQ
'T
II
C1 =20 PF
to O:9,.H
11.5 TURNS
TLIF 15347-7
FIGURE 6. Parallel Mode Overtone Circuit
2-140
MM74HC942 and
MM74HC943 Design Guide
National Semiconductor
Application Note 347
Peter Single
Steve Munich
April 1984
SECTIONS
1) Timing and Control. .......................
a) Input and Output Thresholds ..............
b) Logic States and Control Pin Function ......
c) The Oscillator ..........................
2·141
2-141
2·141
2-142
2) The Modulator ....................... _.... 2-143
a) Operation ...... _...... __ ........... _.. 2-143
b) Transmit Level Adjustment. _....... _...... 2-143
3) The Line Driver .......................... ( .
a) Opera.tion .............................
b) Second Harmonic Distortion ..............
c) Dynamic Range ..........................
d) Transmission of Externally Generated Tones.
i) Using the Line Driver ..................
ii) Using TRI-STATE® Capability ...........
2-144
2-144
2-144
2-144
2-144
2-144
2-144
4) The Hybrid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-145
5) The Receive Filter ......................... 2-145
6) The FTLC Pin .............................. 2-145
7) The Carrier Detect Circuit., ................. 2-146
a) Operation .............................. 2·146
b) Threshold Control. ...................... 2-146
c) Timing ControL ........................ 2-146
8) The Discriminator ......................... 2-147
a) The Hard Limiter ............... , ........ 2-147
b) DiscriminatorOperation .................. 2-147
9) Power Supplies ................ '" ......... 2-147
a) DC LevelS and Analog Interface ............ 2-147
b) Power Supply Noise ..................... 2-147
1) TIMING AND CONTROL
a) Input and Output Thresholds
Originate and Answer Mode
The MM74HC942/943 may be used in a CMOS or TTL environment. In a CMOS environment, no interfacing is required. If the MM74HC942/943 is interfaced to NMOS or
bipolar logic circuits, standard interface techniques may
be used. These are discussed in detail in National
Semiconductor Applicatiori Note AN-314. This note is included in the National Semiconductor MM54HC/74HC
High Speed microCMOS logic Family Databook.
This is controlled by OIA (pin 13). OIA = Vce selects
originate mode. O/A=GND selects answer mode. These
modes refer to the tone allocation used by the modem.
When two modems are communicating with each other
one will be in originate mode and one will be in answer
mode. This assures that each moderri is receiving the tone
pair that the other modem is transmitting. The mod.em on
the phone that originated the phone call is called the
originate modem. The other modem is the answer modem.
The other pin controlling the transmitted tone is TXD
(pin 11).
b) Logic States and Control Pin Function
Transmitted Data
8ell103 Tone Allocation
TXD (pin 11) in conjunction with OIA selects the frequency
of the transmitted tone and thus controls the transmitted
data.
TXD = Vee selects a "mark" and thus the high tone of the
tone pairSfhis is discussed further in the following section.
Data
Space
Mark
2-141
Originate Modem
Answer Modem
Transmit
Receive
Transmit
Receive
1070 Hz
1270 Hz
2025 Hz
2225 Hz
2025 Hz
2225 Hz
1070 Hz
1270 Hz
Squelch Transmitter
Transmitter squelch is achieved by putting SOT = Vee
(SOT is pin 14). The line driver remains active,in this state
(assuming ALB = GND).
The ability of the outputs to TRI-STATE allows the modem
to be connected to'other circuitry in a bus-like configuration with the state SOT or ALB = GND being the modem
chip select.
This state is commonly used during the protocol of establishing a call. The originate user initiates a phone call with
its transmitter squelched, and waits for a tone to be received before beginning transmission. During the wait
time, the modem is active to allow tone detection, but no
tone may be transmitted.
c) The Oscillator
The oscillator is a Pierce crystal oscillator. The crystal
used in such an oscillator is a parallel resonant crystal.
The state SOT = Vee may also be used if the line drivElr is
required but a signal other than modem tones (e.g., DTMF
tones or voice) is to be transmitted. This is discussed further in Transmission of Externally Generated Tones (section 3d).
The Oscillator
*l .H
Analog Loop Back
2.5 pF
2.5 pF
ALB = Vee, SOT = GND selects the state "analog loop
back". (The state ALB = SOT = Vee is discussed in the
following section.)
10M
In a,nalog loop back mode, the modulator output (at the
line driver) is connected to the demodulator input (at the
hybrid), and the demodulator is tuned to the transmitted
frequency tone set. Thus the data on the TXD pin will, after
some delay, appear at the RXD pin. This provides a simple
"self test" of the modem.
The signal applied to the demodulator during analog loop
back is sufficient to cause the carrier detect output CD to
go low indicating receipt of carrier.
J J
CSTRAY
In analog loop back mode, the modulator and transmitter
are active, so the transmitted tone is not squelched.
TLfF/5531-2
Power-Down Mode
The state SOT = ALB = Vee puts' the MM74HC942/943 in
power-down mode. In this state, the entire circuit except
the oscillator is disabled. (The oscillatoris left running in
case it is required for a system clock) . In power-down
mode the 'supply current falls from 8 mA (typ) to 180 p.A
(typ), and all outputs, both analog' and digital, TRI-STATE
(become Hi-Z).
The capacitors used on each end of the crystal are a combination of on-Chip and stray capacitances. This generally
means the crystal is operating with less than the specified
parallel capacitance. This causes the oscillator to run
faster than the frequency of the crystal. This is not a prob.Iem as the frequency shift is small (approximately 0.1%).
Using TRI-STATE Capability
The oscillator is designed to run with equal capacitive.'
loading 6n each side of the crystal. This should be taken
into consideration when designing PC layouts. This need
not be exact.
ALB'
"
CHIP WITH
TRI-STATE
OUTPUTS
SOT'
*
CSTRAY
If a 3.58 MHz oscillator is available, theXTALD pin may be
driven. The internal inverter driving this pin is very weak
and can be overpowered by any CMOS gate output.
TO OTHER
CIRCUITS
"BUS"
CHIP
SELECT
TlIF/5531-1
2-142
The Oscillator and Power· Down Mode
wave frequencies are generated, depending on whether
the modem is set to the orginate or answer mode and
whether the data input to TXD is a logical high or low. See
Timing and Control (section 1) for more information.
When the chip powers down, all circuits except the oscil·
lator are switched off. The oscillator is left running so it
may be used as a clock to drive other circuits within the
system.
The TXD and alA pins set the divisor of a dual modulus
programmable divider. This produces a clock frequency
which is sixteen times the frequency of the carrier to be
transmitted. The clock signal is then fed to a four bit
counter whose outputs go to the sine ROM. The ROM acts
like a four·to·sixteen decoder that selects the appropriate
tap on the D/A converter to synthesize a staircase·
approximated sine wave. A switched capacitor filter and a
low pass filter smooth the sine wave, removing high fre·
quency components and insuring that noise levels are
below FCC regulations.
It is possible to shut the oscillator down by clamping the
XTALS pin to Vee or GND. This will cause the total chip
current to fall to less than 5 p.A. This may be useful in bat·
tery powered systems where minimizing supply current is
important.
Powering Down the Oscillator
r
MM74HC9421943
b) Transmit Level Adjustment
-1..------i ALB
The maximum transmit level olthe MM74HC943 is - 9 dBm.
Since most phone lines attenuate the signal by 3 dB, the
maximum level that will be received at the exchange is
- 12 dBm. This level is also the maximum allowed by most
phone companies. The MM74HC942 has a maximum
transmit level of 0 dBm, making possible adjustments for
line losses up to - 12 dB. The resistor values required to
adju!?t the transmit level for both the MM74HC942 and the
MM74HC943 follow the Universal Service Order Code and
can be found in the data sheets. This resistor added be·
tween the TLA pin and Vce serves to control the voltage
reference at the top of the D/A ladder, adjusting output
levels accordingly.
-f.....- - - - - i SOT
XTALD
I
.J
lN4DD1.
lN417.
ETC.
TLIF/5531-3
Note that for transmission above - 9 dBm the required
resistor must be chosen with the co·operation of the rele·
vant phone company. This resistor is usually wired into the
phone jack at the installation as the resistor value is
specific to the particular phone line. This is called the
Universal Registered Jack Arrangement. This arrange·
ment is possible only with the MM74HC942 because olthe
dynamic range constraints of the MM74HC943.
2) MODULATOR SECTION
a) Operation
The modulator receives data from the transmit data (TXD)
pin and synthesizes a frequency shift keyed, phase
coherent sine wave to be trans'mitted by the line driver
through the transmit analog (TXA) pin. Four different sine
The Modulator
CLDCK--.......,~I
D/)\--.......,~I
TXD--.......,~I
Vee
DI A REFERENCE
GENERATDR
TRANSMIT
CARRIER
(Ie)
TL./F/5531-4
2·143
3) THE LINE DRIVER
a) Operation
The line driver is a class A power amplifier for transmitting
the carrier signals from the modulator. It can also be used
to transmit externally generated tones such as DTMF sig·
nals, as discussed in' section 3d. When used for trans·
mitting modem·produced tones, the external input (EXI)
pin should be grounded to pin 19 for both the MM74HC942
and the MM74HC943. The line driver output is the transmit
analog (TXA) pin.
The Line Driver Equivalent Schematic
+vcc
DTMF, voice or other externally generated tones. Both the
,inverting and non·lnvertlng inputs to the line driver are
available for this purpose. A DTMF tone generator with a
TRI·STATE output may instead be directly connected to
the same node as the TXA pin rather than the line driver.
. The choice of which method to use depends on whether
the MM74HC942 or MM74HC943 is being usedandthesig'
nal level of the transmission. Most phone companies
allow DTMF tone generation at 0 dBm. This level is the
maximum that the MM74HC942 can produce and is be·
yond the range of the MM74HC943.
If the line driver is to be used for external tone generation,
the modem must be powered up and the transmission
must be squelched by the SaT pin being held high. This
will disable the output of the modulator section. The
choice between the EXI pin and DSI pin is up to the user.
The EXI pin gives a fixed gain of about 2. The DSI input
allows for adjustable gain as a series resistor is
necessary.
EXI
Using the DSllnput
r
-- 20k
TRANSMIT
LEVEL
ADJUST
CIRCUIT
VBB
20
TLA
TUFIS5315
GalnAv=~
RDSI
TL/F15531·6
b) Second Harmonic Distortion
If the modem is operating in the originate mode, the line
driver output has frequencies of 1070 Hz for a space and
1270 Hz for mark. The second harmonic for a space fre·
quency is at 2140 Hz, and this falls in the originate modem's
receive frequency band from 2025 Hz to 2225 Hz. While the
modulator produces very little second harmonic energy, the
amplifier has been designed not to degrade the analog out·
put any further. The result is that the second' harmonic is
below - 56 dBm. Thus it is well below the minimum carrier
amplitude recognized by the demodulator.
A better solution may be to use the power·down mode of
the MM74HC942/943 with a DTMFtone generator that has
a TRI·STATE output. Such a device is a TP53130 and is
shown in the diagram following. When the tone generator
is not in use and the modem is not squelched, the DTMF
generator's output is in TRI·STATE. Rather than using the
line driver, the tone generator's output is instead con·
riected to the same node as the TXA pin. The tone gener·
ator is active when the modem is in power·down. Power·
down TRI·STATEs the TXA output.
c) Dynamic Range
Interfacing to DTMF'Generator Using TRI·STATE Feature
The decision to use the MM74HC9420rthe MM74HC943 is
a tradeoff between output dynamic range and power sup·
ply constraints. The power supply is discussed in another
section. The MM74HC942 will transmit af 0 dBm while the
maximum transmit level of the MM74HC943 is - 9 dBm.
This level applies to externally generated tones as well as
the standard modem tone set.
.
It is important to realize that the signal levels referred to
above, and in the data sheet's specifications, are the
levels referred to a 6001l load resistor (representing the
phone line) when driven from the external 6001l source
resistor. Also, the transmit levels discussed previously are
maximum values. Typical values are 1 dB to 2 dB below
these.
d) Transmission of Externally Generated Tones
Since a phone line connection is usually made on the TXA
pin, it may be useful to use the line driver to transmit
ALB'-~"""""
ALB
MM74HC942
MODEM TXA
SQT'--lL....l~....
TP53130
DIALER
CHIP -4~----I TONE
SELECT
DISABLE
TONE
OUTPUT
C}
TOPHO'NE
LINE
TlIF/5531·7
4) THE HYBRID
5) THE RECEIVE FILTER
The MM74HC942/943 has an on·chip hybrid. (A hybrid in
this context refers to a circuit which performs two·to·four
wire conversion.)
The signal from the hybrid is a mixture of transmitted
and received signals. The receive filter removes the
transmitted signals so only received signal goes to the
discriminator.
Under ideal conditions the phone line and isolation net·
work have an equivalent input impedance of soon. Under
these conditions the gain from the transmitter to the op
amp' output is zero, while the gain from the phone line to
the op amp output is unity. Thus the hybrid, by subtracting
the transmitted signal from the total signal on the phone
line, has removed the transmitted component.
The receive filter may be characterized by driving RXA1 or
RXA2 with a signal generator. The fi Iterresponse may then
be observed at the FTLCpin with the capacitor removed. In
this state the output impedance of the FTLC pin is 16 kn
nominal.
6) THE FTLC PIN
The FTLC pin is at the point of the circuit where the receive
filter output goes to the hard limiter input and the carrier
detect circuit input.
Unfor,tunately, these ideal conditions rarely exist and
filtering is used to remove the remaining transmitted
signal component. This is discussed further in the next
section.
The signal at the output of the receive filter may be as low
as 7 mVrms.1t is thus important that the wiring to the FTLC
pin and the associated circuit be clean. Ideally the track
from the capacitor to pin 19 (GND on the MM74HC942,
GNDA on the MM74HC943) should be shared by no other
devices.
Note that the signals into the hybrid must be referred to
GND in the MM74HC942 and GNDA in the case of the
MM74HC943. Thus blocking capacitors are required in the
latter case.· This is discussed further in DC Levels and
Analog Interface (section 9a).
If these precautions are not observed, circuit performance
may be unnecessarily degraded.
The Hybrid
-,
r
r
TXA
RXAZ
-
--
-
THEVENIN EQUIVALENT
OF PHONE LINE AND
ISOLATION NETWORK
I
I
1
600
I.
TO
I RECEIVE
FILTER
I
L
I
-1
MM74HC9421943
- - -
I
I
-1
PHONE LINE
EQUIVALENT
VOLTAGE
SOURCE
I
L
- -
TLlF15531·b
The FTLC Pin and Associated Circuitry
Characterizing the Receive Filter
~2-
- --
MM74HC9421943
I
rH;;;;;;LI;;RI
.------.-I
RECEIVE
FILTER
OUTPUT
I
-i
ETC.
1-I
ETC.
L-.A,/''''''-'I~''--- CARRIER DETECT
L
SELECTIVE
LEVEL
METER
..£!.RCU!!..
-1
0.1 pf
GROUND!
NOISE.!'
TLiF/5531·9
2-145
TLIFI5';3HO
~
Z
-9-------------1 RXAl
O/AI--........-:r
ANSWER
MM74HC942
TXO _
~:::SMITTEO
RXD
RECEIVED
OATA
R2
lk
330
LEO
Cii
CARRIER
DETECT
INDICATION
FIGURE 7. Typical Implementation of an Acoustically Coupled Modem Using the MM74HC942
2·153
+5V
~
5!Z
2 WIRE CONNECTION
4 WIRE CONNECTION
Vee
-,_____ """ ~"""~
cs
'-_..&+________ """"
.....
IN
CAN RISE ANY TIME
,
•••
J~-MUST RISE BY THIS POINT
:
OUT
024
/
"'----'
TLlBI560E)·13
F-IGURE 11. Timing of One Transmission
S24
S1
.,
BP1
LCD 0
7
6'
.3
2
1
0
LCD 1
TLl81.560615
BPB
CS4
LCD 2
CS3
CS2
1
o
CS1
Chip 1 selected
LCD 3
o
Chip 2 selected,
Chip 3 selected
Chip 4 selected
No ,chip selected
TUBI'.l606·14
FIGURE 12. Four Separate LCD Displays
Positioned to Look like Ohe Display
FIGURE 13. Chip Select Scheme
2·160
----------------- ---------------------, l>
Z
12V
W
C11
o
33k
I
2N2222
lOOk
' Voo
VSS
VTC
SI-S24
OATA OUT
24
MM5B201
CLK
13
"
6Bk
r-
-=-
25
12V
~.
40
26
"
DATA IN
CS
e
rjJ-=-
12V 12V 12V
81-37
RC OSC
11V
~I
0001 )IF
5V
2
6k
1
6k
6k
6k
~
CSt
MM58201
rl2
r4
3 CS2
6
5 CS3
B
9 CS4
p} 1
11 ClK
12
13 DATA tN
~
NPUT
PORT
Itl
#2
#3
'4
1
A
i'"
----------------------
MM5B2!l1
#4
r--
rU_
...
JL
1
MM74C906
5V
...
75k
L
I
DATA OUT
1
128 CONNECTIONS FROM LCD
12V
FIGURE 14. Diagram of Application
OATA
BUS
01
01
0,
0,
02
02
0,
0,
03
03
04
04
0,
05
05
05
06
06
0,
0,
MM74HC374
9_
0,
04
12
15
...
,.
...
'"
SEGMENTS
1-?1
12V
6k
p~
10
,.
MM5B201
#3
12V 12V
6k
~
BACKPLANES
1-8
,.....
~
>->--
r-------.
,330k
5V
OUTPUT
PORT
DATA
BUS
INPUT
PORT
01
jfii
ADORESS
OECOOE
05
0,
MM74HC02
Viii
ADDRESS
DECODE
MM74HC02
a. Output Port
b. Input Port
FIGURE 15. Input and Output Ports for Interface
2·161
12V
~
33k
lOOk
I
~~2N2222
g
40
26
Vss
VTC YOD
r-¥.24
DATA OUT
51-524
ClK
MM58201
#1
23
DATA IN
25
BI-87
RCOSC
68k
cs
'::'
12V 12V 12V 12V
SV
6k
2
1 CSI
4
3 CS2
6
5 CS3
8
9 CS4
>->--
6k
6k
21
...
6k
13
r-BPI
...
6k
12
-'-
MMS8201
#2
I-
'--
MM58201
#3
-
5V
7.Sk
11 ClK
~
~
8ACKPLANES
1-8
...
#1
#3
·11
6k
-I-
!>o-
.
#2
~
#4
~
,..
MMS8201
#4
DATA IN
J
MM74C906
DATA OUT
INPUT
PORT
.",
SEGMENTS 1-24
12V 12V
10
--,
-""
104 CONNECTIONS FROM lCO
330k
12V
0.001 ""
I
I
TlIB1560619
FIGURE 16. Diagram of Master·Slave Set·Up Not Used for this Application
SOFTWARE
MAIN
The real heart of this system is the software which con·
sists of four parts. Part one is the initialization portion.
This sets up the MM5B201s as "masters" and programs
them for B backplanes. It then sets up the needed pOinters
for the other subroutines which consist of:
This prog·am initializes the MM58201s. It controls the se·
quence of display output by calling other programs.
It first sends out a "dummy" transmission to make sure
that the chips are ready to respond te;> a valid transmission.
It then programs the chips to be "masters" and to use
eight backplanes.
After initialization, this program sets up the correct
pointers to display a graphic symbol. First it displays the
upper eight ·bits of it, then it displays the lower eight bits.
1) GRAPH: displays pattern on LCD.
2) TEXT: prints ASCII characters on display.
3) SCROLL: scrolls whatever pattern is displayed to
the right until q::D is cleared.
The words "TESTING MM58201" are then displayed. A call
to scroll then causes this to scroll to the right until the
screen is blank. Finally the words "END OF TEST" appear
and the program ends.
This application used an NSCBOO™ with 8080 mnemon·
Ics. It could easily be adapted for other microprocessors.
The method to create a custom graphic symbol will be
demonstrated in the next section.
2·162
Ntwr.ln
EXTHN r;F,'f-'lt:'t I·, WF,'),l r',· Mfl[)L ~ 'f ,~X r ~ CUI;':SDl~ ,SCI~()LL
'IN:I.TIAI..J:ZF:: nil,: STACI(
LXI iii·', I.FFFH
.IN:J:T·IAL.IZE
• meT MODE II
INlf:
MUI
DUT
; SET p'()fn A
MUl:
OUT
MUl
OUT
1"nrN1FI~
rHE EIlIl
PORT A
A,OOH
27H
AS ()UTPUT AND porn C AS INPUT
A,IIFFH
Z'lH
'F'ORT A [)I)I~
(\,11011
Z611
• p()fn ~, [)I)I~
F()f~
,XN:I?rIAI..:I:ZE:. THl" r-OIJI~ ~.iI32111 'S
MVX A, 0
• SET FClH WIUTE M()r:)E
~nA MODE
L.XI 1·1, MASTEH
.SE:ND A COMPLETE, TRANSMISBION TO
MVI Ed lOIlOI:'
ANY OL[) CHII" SE:L.~:CT.
MUl: [),OIlOOl.l.10B
CALI.. IoIRI:TE
L.Xl: H,MABTEH
CI...EAI~
OUT
;C()NI~:[(;URE c~hps 0, :l, 2~ ANl) ~) AS MASTEF~3
MUl 1),000111"1 1 IIr"
CALL wr:
; ~,(ltUE ALL
r.
!.II
:1>
~;TATr::n
PUSH F'B!"!
PUSH Et
I'WlH D
I-'USH 1·1
• FL,~C; I:CII, A ("<[:AD (Jf·'EHA1:DN
MVI: Ad.IIUOOIiOOD
STf'J MlIr)E
.JMI" G"Af'fIl
C;nAI"II:
;SAVE ALL ST()TI::S
1~'lJ!3H FJ!:;:W
["'USH '"
r'UEH 0
F'USH H
;Fl.AG
F1m
A I-IflITE
Ad)
SiA MDD":
()PEf~AT.WN
MVJ
; CAl.CUl.M Eo I-IfU.CH ";El~!O J. TO AI;C[Sf)
CHAP)-11: MVI D,'(IEEH
;STAra WITH Cq l
ACCl
MOV A,C
Sl.Jl: 2".
;~:;U[nl""""CT ~~/f rl;'UM COIJtMtJ '.'OI.!NT
.Ie: GO
.11' CAf~I':Y J~,; ~:U 1111, CDI,HI,!: r '.:1-1:1"1" 1:',; !JI.:.L.LCTI"L'
MOV e,A
; I~Ef; C GET~) NEW COLUMN Nl.IMI.:~:r~
MliV A,D
m.. c
; .J:NCF~EMENT TilE ell Tn N"·X r CfUl"
MOV D,A
.JMP Ace;
1MA]:N LOOP
MOV E.C
M.UJC)P; CALL I-IRr:TE
I)CF': l:
I)CI'! ",
1;0:
[)CF~
E:;
.JZ ENI).G
MOV
!31<,[P:t:
END.C;;
; GET COLUMN NIJMBEI~
1or~AW :3 CliLUMNS
; SlIBTI~AC:T 3. FI':OM COl.UMN COUNT
HF DONE, dUMP.
1 ADD " TO ADDf:u;~~:
)Jerl C
;
F\[~S rOI~I:·
:3 II'fTE8 OF DATA
; Il E:ITS PER I3YT);:
lI~OTATE
DATA
;GET NEXT "'IT
:SET CB
: OUTPUT A "'IT OF DATA
.JNZ DIS~!
l:NX H
DCR 8
;LOOP LlN'fIL DONE WITH ),:Y'TE
dNZ
;LOOP UNTIL DONE WITH
[)I~a
,j
B'fTE,S
STATEB
POP [)
POP ,,:
)'·{)P f'SW
)~ET
DIBPLY:
;)):[~;PL.AY
1~()lITINE
INPUT:
A·· DATA AND CHIP SELECT
),:1:1' 7 .. DATA
IlIH! 0···" •• CHIP SEI_ECT
OUTPUT: NO REGISTEHS [IISTUHE:ED
DUTPUT ONE BIT TIl 58201.
PUSH PSW
~SAVE
ANI
OUT
D)U
OUT
ANI:
CIUT
:MASK OFF UNWANTED !Ill'S
;SF;T UP DATA AND CH:rF' SEl.ECT
; CL.[J);){ HIGH
:l00011].W
201-)
01011000118
20H
10 l.U:l ].18
211H
POP F·'llW
STATES
;CL.DCI< I.OW
;.I~I::STOI~E~
)~ET
MODEl
DS 1
END
2·166
STAH::S
TEXT
multiplied by six because the data to be displayed is six
bytes long. We now have the offset into the table. The
character is displayed on the LCD. This operation is
repeated until all the characters have been displayed.
This subroutine will take the ASCII text pointed to by HL and
display it on the LCD starting at the column pointed tei by
the memory location CURSOR. The data should end with a
zero. CURSOR should be in the range of 0-15 as this is the
e~tent of this LCD display. The first operation is the calcula·
tion of the offset into the ASCII table of the first character.
Thirty·two is subtracted from the ASCII number because
the table starts with a space character. This result is then
A custom font can be generated using the same technique
as that used to create a custom graphic symbol.
N80ao
EXTfIN GIlAPH
PUBLIC TEXT, L.ETTR. CURSOR
TEXT:
;DISPI.. AY A CHARACTEFl STFIING ON LCI) [)ISPLAY
INPUT: HL .•. PIJJ:NT!, TO I:'EGINNING OF STRI:NG
CURSOR •• CllIlRE:NT CUlmOR POSITl:ClN
CIUTI:'UT: ClIRSOIl <= I=URSI)R + LENI;TH OF STI~:[NG
NO FlEGISTERS DISTURBED
PW;H PSW
PUSH H
T • LOOl:': MOV A.M
CPI 0
.JZ T .FIN
CALL LETTR
INX H
.JMP T • LOOP
T .F:[N: POP H
POP PSW
RET
;SAVE STATES
I CHEI=K FOR ENI) OF STRING
I F'RINT LETTER
II_OOP UNTIL DONE
I RESTORE STATE'S
I_ETTR:
;))ISPL.AY AN ASCII CHARACTER I)N LCD [)ISPl.AY
INPUT: A - CHARACTER TO DISPLAY
I=UI~SOI~ .. CUFlRENT CURSOR LOC:AT:WN (0 .• 95)
OUTPUTI CURSOIl -(= CURSOR + 1
NO REGISTI~RS DISTURBED
ISAVE STATES
PUSH
F'USH
PUSH
PUSH
I:'SW
13
I).
H
; SET UP HI_ TI) POINT' TO CORRm=T [)ATA
L.XI H,ASCII
; HL POINTS TCI BASE' AD[)RESS
MVI B.O
lec GETS ASCI]: CIFFSET MINUS A CONSTANT
SUI ZOH
MOV C.A
I=ALL. MlILT
IMULTIPLY OFFSET E'Y 6 d30 , 0
;&
1~~7 ~
~3:~;I':t 9r
OI'U,7,O,O¥O
()
o
,ZEh':34~6~j,
I'
0:.0 0
0
t!,~5" ~J'''2Eh f) ,
34,20,lZ7~20¥31,(1
DB 8,8,62"B,E)"O
1)1;: ()
,6'fI'4f:~, {J,
0 , ()
DB Br8d3,t':h8rO
DE: () ,(761'96, 0 I' 0 , 0
DB
:32,:L6,BI'''l,;~~O
DE: (,2· Bl, 7::~1' 6('1 , liZ ,0
D8 o ,66, :I.~!7,6"'h 0,0
DE: lZZ,7:3, 7~11'7~h70, 0
DEI 3.1+ I' 6~7j I' 7:3,7::) I' ~5At I' 0
(m
DE)
DE:
I)E)
DI;:
DE)
[lE:
DE.:
r.)I;:
DE)
DE:
I)EI
DI;:
DE)
;!
;.
~t
;"
"
;(
~ )
;lK
...
;
;'
; ~.
";;
;0
;:1
;2;::!
1.~hEhd3, :l.~·~6,EhO
;'1
39 I' 6(? , be,], 69 I' ~)7 , ~J
, 7::1 I' 7~~!' 7-::~ \I .(f9', 0
;: ~.)
;6
t7
II~'
:1
,97,1.7~ch7pO
~)4
, I~I >' 7:~ \I 7~~, ~)"l , 0
:l~?'6~ 0
.:tH91'9,Yv
O~~j.q\l~j"l,(J~O,O
;0
t9
;:
Ol'rJ, 0
n~
8 \1'2:0 ~ :34 tf)~5, 0 dl
=<
961'~54,~:;4.
20,20,20,20~ZO,O
II '16~JI':3.q. 'I I!. 0 ,HI' (I
2!'b'BEh,~5,2,.(J
b~~, ,6~:;
I' 93\1 B9',?t3, 0
121,18111711113,124,0
DI;:
1.~?7 'I
DE,:
6~?'
;==
D·
t?
'm
'A
7:3, 73 \l7~h' ~..i4 ,0
6~5 'I 6~i ,3"h n
; I~I
j:C
DI,: . :1.~~7 'I 6~j, 6~:;, 651' 6'2:,0
DE) 127 \l7~.>, ;.r~~, I.)~j, ,65,0
DE: :l.27,91J9,j,l,()
DE) 62,65,65,81~lj.1!10
DE: 127,B,8,O,127,O
DE) O,65,l27,b5~O'l()
;0
DI~
\16'.:;,
aZ,b'l,6.lf,64, 6:3, (l
DB 127,8,20,31'165'10
DE: 1~~7, 6"!-, b'l" b.lf '164,0
DB
1.2, 21':127,0
DB :I.~~7,"hBpj.6, 1.~~7, 0
DE, 62,65,lJ~j,i)5'162, 0
1;.?,:~,
tE
;F
a;
;1-1
;r
hJ
tH
;L
;N
;N
HI
DE: j.~~7,9\19,~),6, I)
DB 62,6'':;,01 ,~~~1,9.lf .. O
DI;: 127,9,2~'j~41,70, 0
DE) 3.lh6CY,7:3,~U. ,3"h 0
;P
DB 1,1,127,1'11'10
DB .:t.)~J,64,6'" ,6.lf '16~)'10
DB 3.L ,aZ,6.ltll:3?,3:L, 0
;T
DE) 127,321"24,~J2, 1.~~7, 0
DE: 9'1' ,2.0 ,8,;!O, 9Y ~ 0
';H
DB
~3r.l'fp1201'4,'::hO
DI~
97, Ell, 7~1, 69,67,0
":ND
2-168
;Q
;I~
HI
;u
,V
;X
;y
;z
l>
Z
SCROLL
This subroutine will scroll whatever is displayed on the
LCD to the right until the screen is clear. It first reads in
three columns of data. It then writes three columns of data
with the HL pointer shifted by one byte. This will shift the
displayed data by one column. This is repeated until the·
N80fJO
PU8l.IC
EXTI~N
entire LCD has been shifted by one column. Then the en·
tire operation is repeated until all the displayed data is
shifted off the screen.
This subroutine could easily be adapted to scroll the
display to the left if desired.
SCI~CJl.l.
h'EAD. GF'A~'I'I
8CFmLL:
;SCHOLLS DISPLAY TCJ THE f(WHT lItH:!L CI.Em,
l:NPUT:
NONE
OUTPIJT: NCJ HEGISTEFm AI,[ CHANt:ED
SCF~EEN
:IS SCFWLL.t:::D UNTIL CLEf.lH
;SAVE ALL STATES
PU!3H F"!~W
PUSH I::
PIISH D
PUSH H
; S[T UP ALl. THI~ 1'(lINTEr~s
MVI D. 96
; LClCIP UNT:IL SCREEN IS Cl.EA!': (96 CYCl.ES)
!':[PEAT: MVl: Adl
;CI.EAf~ FIRST BYTE IN £.:lJI'F[I",
STA E::UFFER
MV:l: [:.:1
mEAl.) ,I COU.lMNS ALWAY:':
Mvr c.o
;STAln WITH COl.UMN ZE:HD
;!
lOOk
>
~
OUTPUT
PORT
6Bk
>
12V
li:o
10k
>
BPl ~
BP2 ~
17
BP3
BP4 16
26 VTC
"'=
"::1
10k
25 CS
5V
10
MM5B201
11
Oa.!JU
~
12V
)
,"
rD~DD
~--r:2N2222
BP6
23
"':M74C906
330k
12V
'11
O'OOl"F
21
r
J
DDDD
J.
BP5 15
24 CLK
12 ...... 13
II
n n nn
~
13
BP7
BPB 12
Sl 11
OATA IN
'
S2 10
AC OSC
S6
S5
6
rI
S4
B
S3
9
TUB15606·22
FIGURE 19, Diagram of a Six-Digit Seven-Segment LCD Multiplexed Display
- OSe-NV
Ii
o
11).
C")
Z
E: -- l.!'NGTH OF [)ATA SmING (MUL T:r:t='LE OF 3)
IlUT PUT
NO HEGISTEHS DI:STURBED
DATA STRINt> IS DISPL.AYEI)
NUMHEI;: :
pusn~ PSW
PUSH 8
PUSH I)
PUSH Ii
[)IGa:
LODP:
MVI [),,,
tI..C)(lP FCm " D:J:C;xrS
L.[)AX E)
LXI IhTAl'L.t:
ADD L.
MIlV l.,A
MVI A,QOH
AIX; H
MOV Il.A
MOV A,M
;GET OUTPUT DATA FROM TABLE
PUSH PSW
l.XI
MOV
ADD
MOV
DCR
H,DATA
A,l.
[)
L,A
;STORE INTO DATA "rUFFER
L
POP PSW
MOV M,A
INX
B
OCF~
E
DCR 0
dNZ L.OIlP
LXI H,OATA
CALL. WIUTE
MOV A,E
n:NCF~EMENT PDJ:NTEI~
TIl DATA STRI:NG
; DECREMENT '.' OF Dm:nS
:J DIGIT COUNT
; IF NOT nm~D D:rGIT THEN Ul(lF' BACf(
it)EC:F~EME,NT
. ; t)IS!'L.AY THEBE THI~EE D:rGITS
; CHECf(
I'·C)F~
LAST· DIG:n IlF [lATA !,TRING
ANA I'!
dNZ.DIG3
POP H
POP D
POP Er
;RESTORE
BTATE~I
POF' PSW
RET
l,mITE::
t)ISF'LAY " Dl:~;ITS
INPUT
HL.···· POINTS Til STAI~T IlF DATA
E .- COl.UMN ADDF~E~IS
OUTPUT
NO HEGISTE:t~S DISTURBED
PUSIi
F'UBI-I
puml
1"~IW
r::
;SAVE
~iTATES
t)
PUSH H
MOV A,E
RLC
HU;
MOV E,A
;GET ADIIRE:SS "rIT!, AT 1-Il:GH E:ND OF "rYTI,:
2·172
,OUTPUT F:rVE
AO[)f~ESS
I:'IT!;
MVI CJ'5
H.LllIlP: HOV A.E
r~L.C
;I~OTATE ADDHESS
MOV 1::,11
MV1: 11.3.11000000£' ;GET MSB 8. ENAE'L.E CHIP SEI..ECT InT
ANII E:
I;ALl. OUT
;OUTPUT Brf" H.l:TH. CHIP ~;EL.ECT
DCf~ C
.JNZ W.l.Ollp
,LOOP UNTJL ADOHESS IS OUT
'SICNAl. FUf, A WIUTE
MVl: A.OIHI
CAl.L. UUT
;OUTPUT THE
HVl:
I)IS1!
MVI
MOV
DIS;!:
MOV
tlJlJTf'UT A ZERO E)IT
DATA
8,~J
C,13
,3 BYTES OF [)ATA
;: a I::ITB PEF~ BYTE:
D,M
1'1.0
mOT ATE [)ATA
I~HC
MOV D.A
i'lNl: :lOOOOOOlm
(mI OOOOOOOW
CAl.L. OUT
DCH C
.JNZ ens;!
INX H
OCR B
,JNZ [Hm
POP H
,GET NEXT BIT
H)XSABl.E CHIP !lEl.ECT
,LOOP UNf.l:L. DONE W.rHI "'YTE
. ; LOOP lINT:l:L DONE WtTH :1 BYTE];
;: HESTOF~E STATES
POP [)
f"OP ",
F'O!=' PSW
f~ET
OUr:
;c,Um~OllTINE
TO DlJ'TPUT ONE IHT TO THE MM~m201.
:r:NPUT
A
DATA E)IT IN MSB PCHl:ITIIlN
IllJTf'UT
NO HEG:n~TI:J;:S DISTUF~BED
... OUTPUT ONE I:':n TO 513Z0:l
PUSH PSW
[JUT ZOH
IlRl: 01000000B
OUT ;~OH
ANI :lOl,Hll.W
[JUl ZOH
'POP PSW
'(;l.OCI< InCH
'CL.OCI< L.DW
I~ET
DATA!
DS 3
TADl.El
01"
OOHJ.:Lll.B, 00000110E:, 0111:l.L01:LI':' 0100:L1l.l.E)
DB Ol100110e~.0110:l:l01B. O:l111:l018. OJ0001:ll~
DB 01:l11.:L11.B, Ol.:LOl1111::
END
SUMMARY
The MM58201 makes it easy to interface a multiplexed
LCD display to a microprocessor. It is simply a matter of
connecting the display and the microprocessor to the
chip, choosing a value for V TC , then interfacing your pro·
gram to use the subroutines listed here or similar ones.
Multiplexed LCDs are the perfect way to cut down on dis·
play interconnections while still taking advantage of the
LCD's low power consumption and high contrast ratioand the MM58201 makes them easy to use.
2·173
National Semiconductor
Application Note 353
Milt Schwartz
May 1984
MM58167A Real Time Clock
Design Guide
The MM58167A is a real-time 24-hour format clock with inout! output structure and control lines that facilitate interfacing to microprocessors. It provides a reliable source of calendar data from milliseconds through months, as well as 6
bytes plus 2 nibbles of RAM, which are available to the user
if the alarm (compare) interrupt is not used. The MM58167A
features low power consumption (typically 4.5 microamperes at 3·volt supply) during battery backed mode, flexible
interrupt structure (alarm and repetitive). and a fast internal
update rate (1 kHz). Systems utilizing this deilice include,
personal computers, process control, security, and data ac·quisition.
Hardware Description Overview
1.0 Figure 1 is a functional block diagram of the MM58167A.
It can be subdivided into the following sections:
1.1 Oscillator
The oscillator consists of an intemal inverter to which
the user connects a 32.768 kHz crystal, bias resistor
and capacitors, to form a Pierce parallel resonant circuit.
1.2 Prescaler
This application note covers hardware interface to microprocessors, clock interrupts, oscillator operation, accuracy,
calibration' techniques. software, and battery back-up considerations.
The prescaler divides the 32.768 kHz oscillator down to
1 kHz using pulse swallowing techniques. The 1 kHz
pulse rate is the incrementing signal for the timekeeping
counters.
Block Diagram '
OSCIN
OSC OUT
0P£Ij
INTERRUPT
OUTPUT
(NOT OPEllAnONAl
OURINOJlWli Ii!lIVII
CONDITION)
lID
ORAIN- RDV
WI!
00
Dl
D2
D3
D4
mIlDlY
lIImIIUPI'
IIllfiIIlf
(0P£Ij ORAIN
OPERATION OURING
JIWlilllllVll CONOITION)
07
n
Pi!ImI"DDIWi
AD
A1
A2
A3
A4
ADDRESS
OECODEII
1--__•
ADDRESS OECOIIES
TL/B/5727-1
FIGURE 1
2-174
Hardware Description Overview (Continued)
1.3 Timekeeping Counters
1.8 Input/Output and Control Lines
The input/output structure consists of a 5-bit address
bus and 8-bit bidirectional data bus. The control lines
are chip select, power down, read and write. In addition,
a ready output is provided for those microprocessors
that have wait-state capability and meet the timing requirements of the ready signal. The power down input
acts as a chip select of opposite polarity. It differs from
the chip select in that it TRI-STATES the main interrupt
output while the chip select does not TRI-STATE the
interrupt. The power down input is intended to facilitate
deselecting the chip for battery backed operation. Chip
select, read and write are active low controls. The ready
output is active low open drain and is caused by chip
select and the negative-going-edge of read or write (it is
an internal one-shot). If the ready output is not used as a
control line when interfacing to a microprocessor, it may
be left open circuit.
The timekeeping section consists of a 14-stage BCD
counter, each stage having read/write capability. The
counters keep time in a 24-hour format. Figure 8 shows
the counter detail of calendar-date-time format.
1.4 Rollover Status
A rollover status bit (read only) informs the user that
invalid data may have been read, due to the counters
being incremented during a counter read or between
successive counter reads. This situation occurs because the counters are clocked asynchronously with reo
spect to the microprocessor.
1.5 RAM
14 nibbles of RAM are provided for alarm (compare)
interrupt or general storage. The nibbles are packed 2
per address except for 2 locations, address 08 and OD
(HEX). The nibble at address 08 appears in the high
order 4 bits, while the nibble at address OD appears in
the low order 4 bits. See memory map Figure 2 for details.
Address
In HEX
07060504
03020100
8
Milliseconds
No RAM
Exists
9
Tenths of Seconds
Hundredths
of Seconds
A
Tens of Seconds
Units of Seconds
'B
Tens of Minutes
Units of Minutes
C
Tens of Hours
Units of Hours
D
No RAM
Exists
Day of Week
~
Tens
Day of Month
Units
Day of Month
F
Tens of
Months
Units of
Months
Detail Descriptions
OSCILLATOR
Figure 3 represents the internal and external circuitry that
comprise the oscillator. The inverter, which is the heart of
the oscillator, is designed to consume minimum power. The
inverter has a typical gain of 30 at 1 kHz and' 4 at 30 kHz. '
The oscillator input may be driven from an external source.
If this is desired, the input should swing rail-to-rail and be
approximately a 50% duty cycle. The oscillator output pin is
open circuit for this case. The external oscillator circuit may
be constructed using a CMOS inverter, N·FET, or a transistor (see Figure 4). Referring to Figure 3, the external 20 MO
resistor biases the inverter in its active region. The internal
feedback resistor may be too large in value to guarantee
reliable biasing.
The external series resistor is to protect the crystal from
being overdriven and possibly damaged. Manufacturers of
these crystals specify maximum power that the crystal can
dissipate. It is this rating which determines what value of
series resistor,should be used. The two external capaCitors
are effectively in series with each other (from an A.C. viewpoint). This total value comprises the load capaCitance (typi·
cally 9 to 13 picofarad) specified by the crystal manufacturer
at the crystal's oscillating frequency. The rule of thumb in
choosing these capaCitors is:
1110ad capacitance = 1/C1 + 1/C2
C2 is greater than C1 (typically two to four times)
FIGURE 2. RAM Memory Map
1.6 Comparator
A 46-bit comparator compares values in RAM against
the counters to provide an alarm (compare) interrupt.
When a compare occurs, the main interrupt will be actio
vated if the DO bit of the interrupt control register was
set. The standby interrupt will be activated if a "1"was
written to address 16 hex.
1.7 Interrupt Hardware
C1 is usually trimmed to obtain the 32768 Hertz frequency.
The start-up time of this oscillator may vary from two to
seven seconds (empirical observation) and is due to the
high "0" of the crystal. Typical waveform values monitored
at the oscillator output are observed to be 3 volts peak to
peak riding on a 2.5 volt D.C. level (for V + = 5 volts).
Interrupt hardware consists of two interrupt outputs. The
main interrupt and the standby interrupt. The main interrupt is an active high push·pull output. The standby interrupt is an active low open drain output. For the main
interrupt, an 8-bit control register allows the user to select from 1 to 7 interrupt rates, as well as an alarm. An
8-bit status register informs the user which of the 8 interrupts occurred. A one-bit control register enables/disables the standby interrupt. The standby interrupt is activated only for the alarm condition. A 46-bit comparator
matches the timekeeping counters against RAM for the
alarm interrupt.
CHOOSING THE CRYSTAL
The below parameters describe the crystal to be used
Parallel Resonant, tuning fork (N cut) or XV Bar
0>=35,000
, 9 to 13 Picofarad
Load CapaCitance (CL)
Power Rating
Accuracy
Temperature Coefficient
2·175
20 Microwatt Max.
User Choice
User Choice
~
r--;----------
C")
20M
Z
TYP
-+--ofRD
1><>-tI---IWR
"Xl......---IA4
MM58167
»-+---IA3
SCRAMBLE HEADER
FOR NORMAL OPERATION
A HEADER WIRED STRAIGHT IHRDUGH IS USED
TL/B/5727- 7
FIGURE 6. Hardware to Achieve a Static Read of Address 1
2·177
Detail Descriptions (Continued)
square wave that is one second high, one second low when
the oscillator is at 32,768 Hertz. Refer to Figure 7 for static
read hardware. If the 32,768 Hertz is to be measured d(ectIy, then a HI impedance LO capacitance amplifier or comparator or CMOS gate should be connected to the oscillator
output pin to prevent the measuring instrument from offsetting the frequency of the oscillator. This addition is permanently a part of the oscillator circuit and must be battery
backed if the clock is battery backed. The reason for battery
backing this buffer is to ensure that its input impedance
does not change during the power down operation which.
could result in the oscillator stopping or being offset in
frequency.
sheet counts milliseconds. The 1 second and slower Signals
are jitter free. Refer to Figure 8 for counter block diagram.
TIMEKEEPING COUNTERS
The timekeeping counters are intended to work with valid
BCD values. In general, if illegal codes are entered then no
guarantee is given for recovery. As shown in Figure 8, the
timekeeping stages are arranged as a ripple counter. The
month, day of month, and day of week counters count 1
through N. The milliseconds through hours counters count 0
through N. The rollover of a counter stage increments the
next higher order counter. This rollover takes place when
the highest allowed value plus one is decoded. For example, in a 30-day month, the day of month counter would
decode the value 31, reset to one and increment the month
counter. If the highest allowed value plus one is written to a
counter, the counter will reset when the write is removed
and "may" increment the next higher order counter.
PRESCALER OPERATION
The 32,768 Hertz signal is divided to an even 32,000 Hertz
using pulse swallowing techniques. This is accomplished by
dropping three pulses every 128 counts of the 32,768 Hertz
signal. The resulting 32 kHz is then divided to produce 1
kHz which is the internal incrementer for the rest of the
timekeeper. This 1 kHz waveform is nonmonoto.nic with respect to individual periods. As a result, there are 750 short
and 250 long periods within a one second interval.
For example, if February 29 is written to the clock, the read
back will be a "1" in the day of month counter and the
month may read "3". However, for leap year use, February
31 may be written. If this is done on Mar 1 at 0 (hours
through milliseconds), then the clock will read March 1 after
24 hours. In this way, the value Feb 31 could be used as an
indication that the date is really Feb 29. Refer to Figures BA
98, and Be for flowcharts of a program and alarm interrupt
bit map that take leap year into account. Note that the software implemented leap year counter is accurate at least
through the year 2048. For a perpetual calendar, a more
sophisticated algorithm would be needed.
The short period is 1/1024 seconds, and the long period is
[1/1024 + 3/32768] seconds. As a result, the milliseconds,
hundredths and tenths of seconds "jitter". The inaccuracy
on an individual period basis is about 91 microseconds. The
period and number of clock edges are correct over one second within the accuracy of the crystal oscillator. The ten
thousandths of seconds counter referred to in the data
r'""
!2
'WAIT'
1
Sl
ONE+SHOT
.,
i:
'li.
~
SlISF~ORN~~~~::~~~: +FOR NORMAL OPERATION,
Sl IS CONNECTED TO 1.
CS
RO
WR
A4
A3 MM58167
A2
A1
AD
DO
TL/B/5727-B
FIGURE 7. Static Read Hardware Where Up Has External Wait State Capability
2·178
l>
Z
1 kHz
W
en
Co)
HUNDREDTHS
OF SEC
4 BITS
TENTHS
OF
SEC
4 BITS
UNITS
DAY
DAY
OF
OF
WEEK
3 BITS
MONTH
4 BITS
TENS
DAY
OF
MONTH
2 BITS
TL/B/5727-9
FIGURE 8. BCD Timekeeping Counters
2-179
~.-----------------------------------------------------------------------------,
~
Z
Z
lJ
~
I
l
...
COMPUTER ~
POWER
UNE
~
INCREMENT
LEAP YEAR
COUNTER
MANUAL
ON·OFF
I
I
(
RETURN
STANDBY
INTERRUPT
BAmRY
BACKED
MM5B167A
'::'
+v
---
*' V
r
I
I.'(
-Eo~
!
I
'HC
W
~
WRITE FEB 31
TO CLOCK
CLEAR STANOBY INTERRUPT
(S2 =OPEN CIRCUIT)
p...
,
YES
I
iN'fli
CJ1
~
COMPUTER
(COUNT =4)
?
RESET LEAP YEAR
COUNTER TO 0
W
BATIERY
ALARM INTERRUPT ON MARCH
TURN POWER ON TO COMPUTER
Note: Use the three least significant bits of millisecond RAM as a five-state software
counter for leap year.
At first power on, the leap year counter is
initialized.
)
TLiB/5727-11
FIGURE 9B. Leap Year Flow Chart and Hardware
DATA
Address
Function
Hi Nibble
4
3
Milliseconds
0
1
Hundredths and
Tenths of Seconds
0
LoNibble
2
1
0
7
6
5
4
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
,
,
3
2
1
0
No RAM Exists
0
0
0
0
Seconds
0
1
0
1
0
0
0
0
0
0
0
0
0
Minutes
0
1
0
1
1
0
0
0
0
0
0
0
0
Hours
0
1
1
0
0
0
0
0
0
0
0
0
0
Day of Week
0
1
1
0
1
1
1
X
X
Day of Month
0
1
1
1
0
0
0
0
0
0
0
0
1
Months
0
1
1
1
1
0
0
0
0
0
0
1
1
No RAM Exists
FIGURE 9C. Clock RAM Bit Map For Alarm Interrupt on March 1@ 0 Hrs
2·181
INTERRUPTS
The 58167 has two interrupt output pins. The main interrupt
(pin 13) is active "high", and is active when the power down
pin is "high". When power down (pin 23) is low, the main
interrupt output is TRI-STATED. The second interrupt is the
"standby interrupt" and is im active low open drain requiring
a pull up resistor to VDD. This interrupt is always powe(ed.
Refer to Figure 10 for typical sink current versus voltage out
characteristics. Separate control bits exist for the two interrupts. The main interrupt offers two modes ~f operation
which may be combined. Mode 1 is the interactive repetitive
interrupt. For this case, a logic 1 is written to one or more
bits in the control register (address 11 hex) from D1 through
D7, a logic 0 is written into the DO position. Refer to Figure
11 for bit configuration of the interrupt control and status
registers.
the clearing of the interrupt output as well as the siatus
register. It is the positive-going-edge of the read strobe
which causes the preceding. This clearing action precludes
polling the status register. For precision timing, the positivegoing-edge of the repetitive interrupt should be used as a
trigger. The one-per-second through one-per-month repetitive interrupts will be as accurate as the setting of the crystal oscillator. The ten-per-second interrupt will be accurate
to about 91 microseconds. Refer to prescaler description for
more detail.
The second mode of main interrupt is the "compare" or
"alarm". In this case, a specific value is entered in the RAM
of the clock. When the time keeping counter(s) match that
value, the interrupt becomes active. Refer to Figure 13 for a
typical example. Figures 11 and 12 show internal interrupt
logic and waveforms. In addition to a specific one time interrupt (alarm), a repetitive interrupt can be achieved by reprogramming the selected RAM location with a future event
value. The rule of thumb for an "alarm" interrupt is: All nibbles of higher order than specified are set to C hex (always
compare). All nibbles lower than specified are set to "zero".
A programming example of the fastest interrupt rate obtainable (500 per second) is given in Figure 14. This program
written in NSC800 code (Z80) sets "always compare" conditions (CC hex) in RAM locations 9 through 'c, E and F.
RAM location D which corresponds to the day of the week
counter (a single digit), is set to C. RAM location 8 is set to
O. When the first interrupt occurs, the service routine reads
the status register and sets the value 2 into RAM location 8.
At succeeding interrupts, the values 4, 6, 8 are set into location 8 and the sequence repeats.
-40'C sTA s +85'C
lS 0.75
.e
VoD=2V
0.5
0.25
OL.-L._----J_ _ _ _ __
0.5
1.5
VOUT (V)
TLIB15727-12
FIGURE 10. Typical Curve of I vs V of Standby Interrupt
As a result, the clock chip provides an interactive repetitive
interrupt, that occurs when the selected counter rolls over.
That is, the user must clear the interrupt so the neXt one can
be recognized. This is done by reading the interrupt status
register (address 10 hex). This read results in the user obtaining the interrupt status (which interrupt occurred) and
If an interrupt is activated and the interrupt occurs during
battery backed operation (power down), the main interrupt
output will be active I)igh when system power returns.
STANDIY
?"
.."... >----7"'----,
Cl-WRITE
ADDRESS
DECODE
~~
IN'EMU"
PI~13
N
DATA BUS
.".
TLIB15727-13
FIGURE 11. Interrupt Registers and Logic
2·182
m;z
~I
COMPARE
0
COMPARE
INTERRUPT
OUTPUT
STANDBY
INTERRUPT
OUTPUT
U;
~
~
(~
(PIN 13)
\
(PIN 14)
CAUSED BY
" ] - - ~EAOING INTERRUPT
STATUS REGISTER
'-I
J--fAUSED BY
WRITING A 0
TO ADDRESS 16 HEX
1 kHz
I
/
COUNTER
ROLLOVER
'¢.
jo
~
CAUSEOB~~
REPETITIVE
INTERRUPT
OUTPUT
~
~
I
READING INTERRUPT
STATUS REGISTER
TL/B/5727-14
FIGURE 12. Internal Interrupt Timing
-~
.
DATA
Address
LoNlbble
HI Nibble
Function
4
3
2
1
0
7
6
5
4
Milliseconds
0
1
0
0
0
0
0
0
0
Hundredths and
Tenths of Seconds
0
1
0
0
1
0
0
0
0
0
Seconds
0
1
0
1
0
0
0
0
0
Minutes
0
1
0
1
1
0
0
1
0
0
0
0
1
3
2
1
0
No RAM Exists
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
X
X
Hours
0
1
1
0
0
Day of Week
0
1
1
0
1
Day of Month
0
1
1
1
0
1
1
X
X
1
1
X
X
Months
0
1
1
1
1
1
1
X
X
1
1
X
X
No RAM Exists
FIGURE 13. Ram Mapping for Alarm Interrupt at 10:22:00 Every Day
2·183
NAME (' 1500Hz' )
rITLE 58167 500HZ REPETITIVE INTERRUPT (10/13/83)
;THIS PROGRAM 15 FOR USE WITH THE 58167 powEll DOWN BOARD
;INTERFACED TO THE NSC888 BOARD. CODE 15 NSC800.
;A 500HZ SIGNAL IS GENERATED AT THE INTERRUPT PIN (13).
;THIS SIGNAL IS GENERATED USING THE COMPARE INTERRUPT
;AND UPDArING THE "RAIl" FOR THE NEXT INTERRUPT
ORG 0800H
4092
4091
4090
408F
408E
408D
408C
408B
408A
4089
4088
10ic
RESET
CONT
STAT
MON
DOM
DOW
HRS
MIN
SEC
HT
MIL
VEC1
VEC2
1010
0800'
0802'
0805'
0807'
080A'
080C'
080E'
0811'
0813'
0816'
0818'
081B'
081E'
0820'
0823'
0826'
,0829'
082C'
082F'
0832'
0835'
0837'
OSSA'
083C'
083E'
0840'
0841'
3E
32
3E
32
3E
D3
31
3E
32
3E
32
3A
3E
32
32
32
32
32
32
32
3E
32
SE
32
FB
00
C3
00
101C
09
101D
08
BB
1FFF
FF
4092
00
4091
4090
CC
408F
408E
408D
408C
408B
408A
4089
00
4088
01 I
4091!
0900'
0903'
0905'
0907'
090A'
090C'
090F'
0912'
0914'
0917'
09lA'
091B'
SA 4088
E6 FO
FE 80
CA 0912'
C620
32 4088
C3 0917'
3E 00
32 4088
3A 4090
FB
C9
INIT:
040928
040918
04090H
04081H
040HEH
0408DH
0408CH
0408BH
0408AR
04089H
04088H
0101CH
0101DH
LD
LD
LD
LD
LD
OUT
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
NOP:
0840
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
A,O
(VEC1) ,A
A,009H
(VEC2) ,A
A,8
(OBBH) ,A
SP,OlFFFH
, A,OFFH
(Reset) ,A
A,O
(CONT) ,A
A, (STAT)
A,OCCH
(MON) ,A
(DOM) ,A
(DOW) ,A
(HRS) ,A
(MIll) ,A
(SEC) ,A
'(HT) ,A
A,O
(MIL) ,A
A,l
(CONT), A
EI
NOP
JP
;SET UP INTRPT FOR NSC888
;INIT STACK POINTER
;RESET ALL CLOCK COUNTERS
;CLEAR INTRPT CONTROL
:CLEAR ANY PEIIDING IIITRPT
;SET RAM FOR INTRPT
;SET COMPARE INTRPT
NOP
:WASTE TIME, AWAlrING
;INTERRUPT
;INTERRUPT SERVICE ROUTINE GETS THE VALUE IN THE
;MILLISECOND RAIl, TEST FOR 8, IF YES THEN SET RAIl
;EQUAL TO 0, CLEAR INTERRUPT AND RETURN.
;IF NO, ADD 2 TO RAM MILLISECOND,
;CLEAR INTERRUPT AND RETURN.
ii' REMEMBER' , RAIl MILLISECONDS IS I 'HIGH' 'I ORDER NIBB~
;ONLY
ORG 0900H
LD
AND
CP
JP
ADD'
LD
JP
ZERO:
LD
LD
RETRN: LD
EI
RET
;GET RAM M1LLSEC
;MASK
'
;? RAII=8
A,(MIL)
OFOH
080H
Z,ZERO
A,020H
(MIL) ,A
RETRN
A,O
(MIL) ,A
A, (STAT)
;CLEAR 1NTRP!
EIID
FIGURE 14. NSC800 Assembly Code for 500 Hz Interrupt
STANDBY INTERRUPT
A "1" written to address 16 hex enables the standby interrupt and a "0" disables it. This interrupt also becomes active when a match exists between time keeping counter(s)
and a value written into RAM. The standby interrupt can be
cleared as soon as it is recognized. The user should ensure
that a delay of one millisecond or greater exists prior to
'reenabling the standby interrupt. This delay is necessary
because of the internal signal level which cause~ the interrupt. If this delay does not occur, then the stanc1by int,lfrupt
becomes reactivated until the internal latched compare
goes away, which occurs at the next 1 kHz clock. Figure 12
illustrates interrupt timing.
sor ports (for single chip microprocessors like the 8048),
peripheral adapter, a'nd separate latches. The advantage of
memory mapped interface is use of all memory reference
instructions. The disadvantages are the processor may
need to be "wait-stated" and the environment is noisier with
respect to the crystal oscillator. Refer to Figure 15 for typi~
cal bus interface.
Microprocessors that have separate ports (16 are sufficient)
offer the capability to interface directly without "wait-stating", or additional device count. Eight of the port bits (data)
need to be bidirectional for this interlace. Figure 16 indicates port interlace. Programmable peripheral interlace devices such as the 8255A or NSC810 afford the user the
advantage of timing control by data bit manipulation, as weI!
as a less noisy environment with respect to the oscillator
cirCUit. Hgure 17 depicts the 8255A and NSC810 interface.
External latches may be used in place of the programmable
peripheral interlace device. This results in higher package
count but easier troubleshooting. Also, the latches do not
have to be manipulated through a control register. Figure 18
illustrates the external latch approach. For the peripheral
approaches, address, data, chip select, read and write
strobes are manipulated by controlling the data bus bits via
program execution. The peripheral interlace approach facilitates calibration of the oscillator because the chip' select,
read strobe, and address lines can be set to steady state
logic levels. Refer to calibration techniques for more detail.
RAM
RAM is organized as shown in Figure 2. There are 4 bits of
RAM for each BCD counter. The RAM may be used as general purpose or for an alarm interrupt. It is possible under
certain conditions to perform the compare interrupt and use
selected bits of the RAM for general purpose storage. AllY
RAM position that is set for the 'always compare' condition
allows the user to manipulate the 2 LO order bits in each
nibble. However, the 2 high order bits in each nibble position
must be maintained as logic 1'5. For example, the user may
have an alarm interrupt that does not use the day of the
week as a' condition for interrupt. Therefore the 2 low order
bits might be used as a 4 state software counter to keep
track of leap year. Reading and writing the RAM is the same
as any standard RAM.
fJI
HARDWARE INTERFACE CONSIDERATIONS
There are four basic methods of interfacing the 5l116? A 10 a
microprocessor. They are memory mapped, microproces-
(8085)
(Z8o
NSC800)
pl'SYSTEM
BUS (NON·MUXED)
FOR NSC800,
l8o, 8085,
OR ANY
MM58167A
PROCESSOR
WITH WAIT
STATE CAPABILITY
iii
TL/8/5727-15
FIGURE 15. Typical ",p Bus Interface
o
2·185
CS
RD
cs
iiii
WI
PORTt
8048
WI
A4
A3
A2
A1
A4
A3 MM58t67A
A2
At
AD
PORT 2
..
AD,
...
DATA BUS
"'III-
D7-DO
'"
TLlB/5727 - 16
FIGURE 16. MM58167A Interfaced to Single Chip Microcomputer
r-
~p
..
BUS
-,I
CS
RD
WR
ADDRESS
...
DATA
~
IOT/M
"
"'III
..
ALE
CS
RD
WI
A4-AO
NSC8tO
OR
INSB255
} NSC8tO PORT 2
...
'"
.
DATA
.....
...
'"
MM58167A
07-00
TLlB/5727-17
FIGURE 17; MM58167A Interfaced to p.P Through Peripheral Adapter
,I
I"'" ADDRESS
BUS ..
'ADDRESS
--
I.
10-
CS
Wii-::LJ--
"'. DECODER
.r-
LE
CS
iiii
OC
HCT373
...
l1li
WR
A4
A3
A2
At
AD
Wi!
A4
A3
A2
At
AD MM58t67A
'"
--
WRTI
1-[>0-
7'
LE
OC
~
BUS
...
HCT373
..
DATA BUS
'"
07-00
III.
....
'"
iiii
"-
DC
LE -
HCT373
--+iiii
~
... --+Wii
TLlB/5727-1e
FIGURE 18. MM58167A Interfaced to p.p Using TRI-STATE Latches
2·186
~-------------------------------------------------------,~
z
POWER DOWN/BATTERY BACKED CONSIDERATIONS
Battery back up of the clock may be considered by the user
to maintain time during power failure, provide a "wake-up"
alarm, save the time that power failure occurred, calculate
how long power failure lasted. The first step in providing a
battery backed system is to isolate the system supply from
the battery. This is to ensure that the battery is not discharged by the system supply when power failure occurs.
Figure 19 shows two techniques to achieve isolation. Figure
19A is implemented using diodes to isolate. In one case a
Schottky diode is used to guarantee minimum voltage drop
loss, while in the other case an adjustable voltage regulator
(LM317) is used from a higher voltage and regulated to
about 5.7 volts. A 1N914 diode in series with the regulator
achieves the 5 volts for the clock. The Schottky diode has a
drop of about 0.3 volts. Thus the V + of the clock is typically
at 4.7 volts. The user must be cautious about input signals
not exceeding the 4.7 volt V+, since the clock is a CMOS
device. This situation could arise if the devices driving the
inputs of the clock were CMOS and received power from
the 5 volt system supply. Figure 198 makes use of the low
saturation of a PNP transistor (0.1 volt) to take care of the
above situation. The NPN transistor is used to achieve isolation. The zener diode ensures that the circuit stops conduct-~
ing and appears open circuit before the battery switches in.
(.)
CIt
Co)
Some basic considerations must be adhered to in a power
down situation where the real time clock is battey backed.
One is to ensure no spurious write strobes accompanied by
a chip select occur during power down or power up. Another
is to guarantee the system is stable when selecting/deselecting the clock. Also, any legitimate write-in-progress
should be completed. To accomplish this, hardware is implemented such that early power failure is detected (usually
a comparator detects DC failure, a retriggerable one-shot
detects AC failure) See Figures 20 and 21. At this point the
clock chip is deselected. The worst case is the power fails
faster than the detection circuit can cause deselection.
When power returns, the hardware detects power on, but
the system must be stable before communication is allowed
with the real-time-clock.
12V
•
5V--I*---t---lI4---,
TUB/5727-19
A
":" ''CHOOSE Dl WITH BREAKOOWN=YBATT
TL/B/5727-20
B
FIGURE 19. Isolating System Supply from Battery
5Y
5Yr-----P--.,
SYSTEM
SYSTEM
30k
~-----II--..... VrRIP
200k
~
TL/B/5727-21
FIGURE 20. Sensing D_C. Failure Using a Comparator
2·187
M,---------------------------------------------------------------------r-------,
~
Z
..L
-
':"
2N2222~5\1
-
~
All
lOOt
TL/B/5727 -23
FIGURE 22. Detailed Schematic of Power Down Circuitry, and Interface to NSC888 Board
CSC"N\f
~
M
Z
«
A wait state generator was implemented using the chip select as the sensing signal. This was necessary to comply
with NSCSOO wait state timing. The wait generator provides
2 microseconds of access time, which is more than adequate to meet clock chip timing requirements. Pull-down resistors were added to all clock input pins to guarantee Jlo
floating inputs during power down. This ensures that'the
CMOS clock does not draw excessive current from the battery during power down. A diode isolates 5-volt system from
the battery (A 3.4-volt Tadiran nonrechargeable lithium cell
was used in this application). The battery is isolated from
the 5-volt supply using a circuit comprised of PNP and NPN
transistors along with a zener diode. The zener diode value
was selected such that the combined voltage drop of the
zener and the base emitter of the NPN transistor was greater than the battery voltage. This ensures no current will be
drawn from the battery by the 5-volt supply when power
failure occurs.
The battery is non rechargeable, but allows up to 10 microamps of charge current without damaging the cell. An
LM139 voltage comparator and LM385-2.5 voltage reference were used to sense the 5-volt system supply. The trip
point was adjusted such that when the 5-volt supply
dropped to 4.6 volts, the comparator switched from low to
high. Observation of the comparator output showed oscillation, but caused no malfunction. The duration of the oscillation was about 100 microseconds. Burst noise on, the 5-volt
supply was about 0.5 volts peak to peak. F;or the circuitry
implemented, the 5-volt supply should fall no faster than 1
volt per millisecond. This rate allows 100 microseconds for
deselect to take place while the supply is falling from 4.6
volts to 4.5 volts. ThOs, deselect occurs while the system is
stable.
Miscellaneous
TEST MODE
The test mode applies the oscillator output to the input of
the millisecon'd counter. This affords faster testing of the
chip. This mode is intended for factory testing, where a programmable pulse generator is used. A pulse rate of 50 kHz
may be used in this mode. The pulse should swing rail to rail
and be a square wave. Apply the pulses to the oscillator
input pin, leaving the oscillator output pin open circuit. The
basic sequence would be to write values to the counters,
enter test mode and apply a known number of pulses. Next,
read the counters using normal read sequence.
GO COMMAND
A write to address 15 hex (data is a "don't care") will clear
the seconds counter is equal to or greater than 40 when the
GO command is executed, then the minute counter will be
incremented.
REST COMMAND
Writing the value FF hex to address 12 hex causes the
hours through milliseconds counters to be reset to zero. The
day of week, day of month, and month counters are set to 1.
Writing the value FF hex to address 13 hex causes the RAM
to be cleared.
GENERAL TIMING CONSIDERATIONS:
To guarantee a valid read/write without using the ready output, the following criteria must be met.
Read Operation
1. Address setup before RD = 100 ns min
2. CS to RD=O min
3. Read strobe width = 950 ns min
4. Address hold after read = 50 ns min
Write Operation
1. Address setup before WR= 100 ns min
2. CS to WR=O ns min
3. WR and data must be coincident for 950 ns min
4. Data hold after WR = 110 ns min
5. Address hold after WR = 50 ns min
If the ready output is used to guarantee read write operation, then the following recommendations are made. Referencing the April 1982 data sheet, during a read, the ready
line makes its positive transition 100 nanoseconds before
data is valid. (Not shown in the data sheet). The user should
not use this signal to latch data into an external latch. If this
Signal is used to wait state a microprocessor, then a critical
examination of the microprocessor timing with respect to
when it terminates its wait stated cycle must be made. This
examination must also include allY set-up time the processor needs prior to reading data. Also, note that the ready
output (per the data sheet) negative-going-edge occurs 150
nanoseconds after the read or write strobe has gone low.
Check microprocessor timing to ensure that the ready signal
would be recognized as a "wait-signal".
It is not advised to perform sequential reading by connecting chip select and read low and cycling through the counters by changing address lines. The reason is that it is possible to cause an internal latch to "flip," the result being an
error in timekeeping.
the seconds through milliseconds counters. If the value in
(
2·190
~------------------------------------------~~
SOFTWARE CONSIDERATIONS
Writing the Counters
Reading the Counters
The counters may be written to in any order, because the
write overrides the internal increment. If it is desired to write
all the counters without increments occurring in between
writes then the complete write operation must be performed within 800 microseconds. As long as valid BCD values (with respect to the specific counter) are written, no
other counter is affected by the write. In general, writing the
high order to low order counters is the conservative approach. This method is less susceptible to increments between writes for cases where the writing takes greater than
800 microseconds. For initialization of time, if the "GO"
command is issued prior to any write, then 10 milliseconds
are available to write from months through tenths and hundredths of seconds without any effect due to internal incrementing.
A read of one counter plus the rollover status bit or all the
counters plus the rollover bit must be done within 800 microseconds. If the rollover status bit is a "1" then a complete read of counter(s) must be performed again. The 800
microsecond value is conservative. If the time between the
read of any counte~(s) and the rollover status bit exceeds
800 microseconds, then the status bit will always be set.
, The order of reading must be counter(s) first, then rollover
status bit. This is because the positive going edge of the
read strobe clears the status bit. Refer to Figure 23. The
status bit is enabled for a period of 150 microsecond maximum at a rate of 1 kHz. If during this 150 microsecond period a counter(s) read occurs, the status bit will be set. This is
true no matter how often the rollover status is read during
that time period. Each rollover status read resets the status
bit, but any counter read within the 150 microsecond period
will set the rollover status bit. If the counters are read after a
repetitive interrupt, then allow 150 microseconds (conservative) from the sense of the interrupt to the read of the counters (ripple delay time) and the data will be valid. If the counters are read after a compare interrupt, the read can occur
immediately and will be valid.
BIBLIOGRAPHY
MM58167A Microprocessor Real Time Clock Data Sheet
April 1982.
"Crystal Oscillator Design And Temperature Compensation" By Marvin E. Frerking.
National Semiconductor Application Note AN-313 D.C.
Electrical Characterization Of High Speed CMOS Logic.
LM-139 Quad Voltage Comparator Data Sheet.
RD. CS
ANY CDUNTElI-_......._ "
Tl/B/5727-25
FIGURE 23. Rollover Status Bit Logic
2·191
z
~
Co)
m
z The MM58174A Real Time
« Clock in a Battery Backed-Up
Design Provides Reliable .
Clock and Calendar' Functions
National Semiconductor
Application Note 359
Steve Munich
February 1984
INTRODUCTION
National Semiconductor's MM58174A microprocessor
real time clock is a reliable and economical solution to
adding clock and calendar timekeeping to any system.
This metal-gate CMOS circuit (Figure 1) will operate with a
supply voltage as low as 2.2V, allowing easy implementation of battery back-up circuitry to maintain timekeeping
year after'year, even when the system's main supply fails.
The MM58174A has counters for months, day of month,
day of week, hours, minutes, seconds and tenths of seconds, as well as a register for automatic leap year calculations. Also included are periodic and single interrupt
capabilities at 0.5, 5 and 60 second intervals.
This application note will describe how to interface the
MM58174A to microprocessors with battery backed-up
circuitry. Included will be a functional circuit description,
trouble-shooting hints, crystal OSCillator adjustment and
supplier information. Please refer to the data sheet for AC
and DC electrical specifications and timing diagrams_
DESCRIPTION OF FEATURES
shown in Table I. Months through minutes registers can be
read'and written to. Tens of seconds, units of seconds and
tenths of seconds registers can only be read and are reset
to zero when counting is enabled by the start/stop flipflop. When properly addressed, a nibble of data appears
on the data pins DBO-DB3 when a read occurs, and data is
accepted on these pins during a write. Any unused data
pins will be ignored during a write operation (e.g., days of
week uses only DB2 through DBO). To insure prop.er
counter incrementation and accessing, all timing specifications must be observed. It is particularly important that
the RD strobe width be less than 15 P.s for the highest
timekeeping accuracy, but never greater than 15 ms.
Address 13 is a write only leap year status register.
Writing a "1" to DB3 at this address will cause the time
02/2823:5959.9 to roll over to 02/29 00:00 00.0 in one-tenth
of a second. If a "1" is instead written to any other data bit,
the roll-over will go to 03/01 00:0000.0 and the leap year
will occur as shown in Table II.
.
Reading and Writing the Time
The MM58174A has BCD counters for tenths of seconds
through months, which are accessed by a 4-bit address as
CONTROL BUS
ADDRESS BUS
INTERRUPT
DATA BUS
32 kHZ'
U
TLfF/6169·1
FIGURE 1. Block Diagram
2-192
TABLE I. Address Decoding for Internal
Registers
Address Bits
AD3 AD2 AD1 ADO
Selected Counter
oTest Only
0
1 Tenths of Seconds 0
2 Units of Seconds
0
3 Tens of Seconds
0
4 Units of Minutes
0
5 Tens of Minutes
0
6 Units of Hours
0
7 Tens of Hours
0
8 Units of Days
1
9 Tens of Days
1
10 Day of Week
1
11 Units of Months
1
1
12 Tens of Months
13 Years
·1
14 Stop/Start
1
15 Interrupt·
1
TABLE II.
Yea~
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Mode
Write Only
Read Only
Read Only
Read Only
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
Write Only
Write Only
R~ad or Write
READ TENS OF MONTHS
THROUGH UNITS OF
SECONDS (AOOR 12
THROUGH 02)
Status Register
Mode: Address 13, Write Mode
Leap
Leap
Leap
Leap
Year
Year-1
Year-2
Year :- 3
DB3
DB2
DB1
DBO
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
Detecting Changed Data
It is possible that during a sequential read of months.
through tenths of seconds a roll-over may occur. If the time
at the start of the read is 23:59 59.5 and it rolls over to the
time 00:00 00.0, the microprocessor could read back 23:50
00.0 or 23:00 oo.b, etc. Wrong data could also be stored in
the clock if the clock is running and is updated during a
write (the start/stop flip-flop discussed in the next'
paragraph will help avoid invalid writes). The MM58174A
has a data-changed flip-flop which indicates that a tenths
of seconds roll-over has occurred. This flip-flop sets all the
data lines high each time the tenths of seconds counter is
updated. The "F" on the data lines is then cleared by the
next low-to-high trarisition of any read strobe. In a sequential read of the counters, the tenths of seconds counter
may change while the read strobe is low, but an "F" may
never be seen before the read strobe comes high. Thus,
the "F" may not be detected, although the experimental
probability of this occurrence is approximately one in ten
thousand reads, in the worst-case. It is essential to restart
the whole sequence of reads, beginning from the tens of
months register whenever an "F" is encountered on the
data lines. A better procedure, outlined in the flowchart of
. Figure 2, would be to always begin each sequence of
reads with the tenths of seconds register and end with this
register. If comparing the two values read from this
register shows them to be equal, the data read is valiCt and
should be used. If the compare yields two different values,
repeat the same sequence of reads until the same value is
TLlFI61b92
FIGURE 2. Flowchart to Detect Changed Data
read from the tenths of seconds register at the beginning
and end of the sequence. It is advisable to use a machine
code clock reading routine, or else the time to execute
machine-interpreted code may be longer than one-tenth of
a second, invalidating all sequential reads.
Clock Accuracy
Two important factors affect the accuracy of the
MM58174A. Any internal counter can jitter by -30.51'5,
meaning that the true count can be late by this amount.
Also, whenever the clock is restarted (see next section), instead of holding a "0" in the tenths of seconds position for
one-tenth of a second, the clock immediately jumps to a
"1". So each time the clock is restarted, one-tenth of a second is lost. Accuracy would be maintained if the clock.is
restarted 0.1 second after the time reference's minutes
change.
2-193
not tolerate it. When the supply falls below 4V but stays
above 2.2V, the MM58174A is in the sleep mode and only
microamps are drawn from the battery. In this mode, the
chip is not accessible by reading or writing, but time is being maintained.
Starting and Stopping the Clock
Table I shows that address 14 accesses the start/stop flipflop. A "1" on DBO will start the clock. Writing a "0" to DBO
will stop it. This flip-flop is used for precise starting and
stopping of the clock. It also prevents writing invalid data
during a clock roll-over, as mentioned in the last paragraph. Before any sequence of writes, stop the clock.
Restart it after the last write is completed,
On power-up from zero volts Vee, one must make sure the
chip is not in the test mode. This is done by writing a "0" to
DB3 at address O. It is advisable to do this even when coming out 01 the sleep mode. The test mode is mainly for production testing of the circuit.
Interrupts
There are several things to consider when designing the
power-down circuitry. The basic functional requirements
are to disable the chips before full power loss or malfunction, and to wait for Vee to stabilize before enabling the
chip on power-up. A desirable feature would be to allow
the read or write in progress to complete. Figures 3 and 4
include a typical power-down circuit which achieves these
goals. In general, avoid using TTL since it is not rated
below 4.5V. The power-down circuitry's signals to the
MM58174A must not be allowed to deviate more than a
diode drop above the clock's supply or below ground in
order to avoid triggering SCR latch-up. Finally, be sure to
use a PNP switch instead of c-.. 'A¥r--t
..
"*
-15 pF
TLlF16169·10
FIGURE 10. Crystal Oscillator
Crystal Information
;ENABLE NSC800 INTERRUPTS
I
Choose one of the following crystal types: parallel resonant or tuning fork (NT CUT or XY BAR) with a 0>35,000
and a frequency of 32.768 kHz. The load capacitance required ranges from 9 pF to 13 pF. The maximum power
rating is 20 p.w. The choice of crystal accuracy and
temperature coefficient are left to the user. Two crystals
used in our lab are RCD's #RV-38 and Saroni>s's
#NTF3238C.
FIGURE 7. Initialization
Figure 7 shows the necessary initialization code for the
NSC800, NSC810A, and the MM58174A, which use the read
and write subroutines. Of greatest importance is the code
to insure that the clock is not in the test mode. Notice that
a DI instruction is used to disable interrupts before a "0" is
2·198
Oscillator Adjustment and External Drive
A well·tuned oscillator for the MM58174A will have a fre·
would be to isolate the oscillator from the probe by adding
an inverter to the small capacitance at pin 14. This would
quency error of no more than ± 10 ppm. This would result
load the oscillator, but the input capacitance of the gate
in the clock being off by ± 5 minutes per year. This is a
worst·case number, taking into account such factors as , would not be affected by a probe at the output. The total
temperature variation (- 40°C to 85°C) and supply varia·
capacitance 6n pin 14 should be kept near 15 pF.
tion (2.2V to 5.5V). The external oscillator components can
To drive the oscillator from an external clock, connect the
also contribute to error and this should be taken into ac·
clock to pin 14 (crystal out) and tie pin 15 (crystal in) high.
count by the user.
Adjusting the trimmer capacitor at pin 15 will minimize the
oscillator error. But simply putting a scope probe on the
CONCLUSION
crystal will load the oscillator with at least 10 pF,
significantly altering the frequency. There are two good ' The MM58174A can easily be interfaced to a microproc·
essor to bring the functions of a real time clock and calen·
ways of isolating the probe from the osciflator. One
dar to any system. With a power·fail/back·up circuit, the
method is to put the part in the test mode by writing a "0"
system will be able to keep accurate time for years, in·
to DB3 at ADO, then tune the signal at DBO to 16,384.00 Hz
using an accurate frequency counter. Another method
dependent of the system power supply.
fJI
2·199
lI)
~ The MM58274 Adds Reliable
Z
< Real-Time Keeping to Any
Microprocessor System
National Semiconductor
Application Note 365
Peter K. Thomson
April 1984
1.3 POWER SUPPLY ISOLATION SCHEMES
1.3.1. The Need for Isolation
1.3.2 Isolation Techniques I - 5V Supply Only
1.3.3 Isolation Techniques II - Negative
Supply Switched
1.3.4 Other Methods
INTRODUCTION
When a Real-Time Clock (RTC) is to be added into a digital
sysiem, the designer will face a number of design constraints and problems that do not usually occur in normal
systems. Attention to detail in both hardware and software
design is necessary to ensure that a reliable and trouble
free product is implemented.
1.4 POWER FAIL PROTECTION
1:4.1 Write Protect Switch
The extra circuitry required for an RTC falls into three main
1.4.2 5V Sensing
groups: a precise oscillator to control real-time counting; a
1.4.3 Supply Pre-Sense
backup power source to maintain time-keeping when the
1.4.4 Switching Power Supplies
main system power is removed; power failure detection and
1.4.5 Summary
write protection circuitry. The MM58274 in common with
most RTC devices uses an on·chip oscillator circuit and an
. 2.0 SOFTWARE
external watch crystal (frequency 32.768 kHz) as the time
reference. A battery is the usual source of backup power,
2.1 DATA VALIDATION
along with circuitry to isolate the battery·backed clock from
2.1.1 Post·Read Synchronization
the rest of the system. Like any CMOS component, the RTC
2.1.2 Pre-Read Synchronization
must be protected against data corruption when the main
2.2 INTERRUPT AS A 'DATA-CHANGED' FLAG
system power fails; a problem that is very often not fully
2.3 WRITING WITHOUT HALTING TIME-KEEPING
appreciated.
Rather than dealing strictly with anyone particular application, this applications note discusses all of the aspects
involved in adding a reliable RTC function to a microprocessor system, with descriptions of suitable circuitry to
achieve this. Hardware problems, component selection, and
physical board layout are examined. The software examples
given in the data sheet are explained and clarified, and
some other software suggestions are presented. Finally a
number of otherwise unrelated topics are lumped together
under 'Miscellany'; including a discussion on how the
MM58274 may be used directly to upgrade an existing
MM58174A installation.
CONTENTS
2.4 THE CLOCK AS A I'P WATCHDOG
2.5 THE ,JAPANESE CALENDAR
3.0 MISCELLANY
3.1 CONNECTION TO NON-MICROBUS SYSTEMS
3.2 TEST MODE
3.3 TEST MODE AND OSCILLATOR SETTING
3.4 UPGRADING AN MM58174 SYSTEM WITH
THE MM58274
3.5 WAIT STATE GENERATION FOR FAST I'PS
APPENDIX A-I Reading Valid Real-Time Data (Reprinted
1.0 HARDWARE
1.1 COMPONENT SELECTION
1.1.1 Crystal
1.1.2 Loading Capacitors
1.1.3 Backup Battery:
Capacitors
Nickel·Cadmium Cells
Alkaline
Lithium
Other Cells and Notes
Temperature' Range
1.2 BOARD LAYOUT
1.2.1 Oscillator Connection
1.2.2. Battery Placement
1.2.3 Other Components
from the MM58274 Data Sheet)
APPENDIX A-2 MM58274 Functional Truth Tables
1.0 HARDWARE
Selecting the correct components for the job and implementing a good board layout is crucial to developing an
- accurate and reliable Real-Time Clock function. The range
of component choice~ available is large and the suitability of
different types depends on the demands of the system.
1.1 COMPONENT SELECTION
With· reference to Figure 1, the oscillator components and
the battery are examined and the suitability of different
types is discussed.
2-200
r--------.~--------------------~----~~--e_--e_--_.~+5V
r- ---,---,
I
Voo
OSCILLAlOR
GUARD GROUND
16
15 (OPTIONAL)
I
I
100 nF
DISK
Dl
4.7k
R2
RCH
Si
~~~----------~~~~
Z01
TR3
L
Mr.:~--~-w'!"'J
3.6V
MM58274
i ~~;:D==B~l:::::::::::::::::j:.
3.3k
~~~DB~O_--~--------t---~1L~~~-l
A03
AD2
AD1
20 pF
R1.
Vss
ADO
100 nF DISK
TLIF/6737·1
FIGURE 1. MM58274 System Installation
1.1.1 Crystal
temperature range with close tolerance and low temperature coefficients (typically ± 3 ppm/K, for good quality examples). If trimming is undesirable a pair of close tolerance
(± 5% or better) capacitors in the range 18 pF-20 pF may
be used. The average time-keeping accuracy for this configuration is within ± 20 seconds per month.
The oscillator is designed to work with a standard low power
NT cut or XY Bar clock crystal of 32.768 kHz frequency. The
circuit is a Pierce oscillator and is shown complete in Figure
2. The 20 MG resistor biases the oscillator into its linear
region and ensures oscillator start-up. The 200 kG resistor
prevents the oscillator amplifier from overdriving the crystal.
If very low power crystals are used (i.e., less than 1 jJ.W) an
external resistor of arou nd 200 kG may have to be added to
reduce the drive to the crystal.
1.1.3 Backup Battery
There are a number of different cell types available that can
be used for time-keeping retention. Some cells are more
suitable than others, and the way in which the system is
used also influences the choice of cell. Ideally the standby
voltage of the RTC should be kept as low as possible, as the
supply current increases with increasing voltage (Figure 3).
Four different power sources are discussed: capacitors,
nickel-cadmium rechargeable cells, alkaline and lithium primary cells.
The oscillator will drive most normal watch crystalS, with up
to 20 I'W drive available from the on-Chip oscillator.
CLOCK 10
COUNTER
CIRCUITRY
200 kll
50
~
40
I
TLIF16737·2
~ 30
FIGURE 2. Complete Oscillator Diagram
If
~ 20
1.1.2 Loading Capacitors
10
Two capacitors are used to provide the correct output loading for the crystal. One is a fixed value capacitor in the
range 18 pF-20 pF and the other is a variable 6 pF-36 pF
trimmer capacitor. Adjusting the trimmer allows the crystal
loading (and hence the oscillator frequency) to be fine tuned
for optimal results.
o
1/
/
1
Voo (V)
.
The capacitors are the components most likely to affect the
overall accuracy of the oscillator and care must be exercised in selection. Ceramic capacitors offer good operating
2-201
TLlf16737-3
FIGURE 3. Typical 100 (I'A) vs. Voo (V) for MM58274 in
Standby Mode (TA
25°C)
=
, Capacitors
When the system is permanently powered, and any long
term removal of system power (I.e., more than a few hours)
requires complete restarting, then a 1-2 Farad capacitor
may be sufficient to run the clock'during the power down,
This car'! keep the clock running for 48-72 hours.
d. Operating temperature range.
e. The method of battery connection and mounting.
In general soldered cells are preferable to connector
mounted cells. With replaceable batteries, the battery and
connector contacts must be kept thoroughly clean. Dirty or
corroded contacts can cause the clock to be starved of
power, giving 'erratic and unreliable per.formance. The ease
of operator access for cell replacement should also be considered.
Nickel-Cadmium Cells
Nickel-cadmium (Ni-Cad) cells can be trickle-charged from
the system power supply using a resistor as shown in Figure,
1. The exact value of resistor used depends on the capacity
and number of cells in the battery, Consult the manufacturers data for information on charging rates and times.
A 3- or 4-cell battery should be used to power the clock (the
nominal battery voltages are 3,6V for 3 cells in series and
4,8V for 4 cells), with 3 cells preferable. PCB mounting batteries of 100 mAh capacity are available and these will give
. around 6 months data. retention (at normal room temp'erature). For this cell type to be used the system must spend a
large proportion of its time turned on to keep the battery
charged (I.e., used daily),
Temperature Range
The performance of any cell will be satisfactory for most
office or domestic environments. When 'ruggedized' equipment is to be used (I.e., field portable equipment, automotive, etc.) the temperature specification of different cell
types should be taken into account when selecting a cell.
Lithium cells offer good performance over OOC-70oC with
little loss in capacity. Once again, the manufacturer's data
should be examined to determine suitability, especially
since different cells of the same type can have markedly different characteristics.
Alkaline
Alkaline cells are among the least expensive primary cells
which are suitable for use in real-time clock applications.
They are available in a large range of capacities and shapes
and have a very good storage (shelf) life.
Few types of cells will offer any useful capacity at temperatures in or below the range 0°C-l0°C, and fewer still will
operate over the full military temperature range (-55°C to
+ 125°C). Solid lithium cells and mercury-cadmium cells
are two systems which can cover this range.
Two cells in series will provide a nominal 3V, which is adequate to power the clock (via the isolating diode). The main
problem with the alkaline system is that the cell terminal
voltage drops slowly over the life of the cell. When the 'voltage at the clock supply pin drops to 2.2V, the cells must be
replaced (battery voltage around 2.6V-2.7V), With present
alkaline celis, this point is usually reached when the cells
are only 'k to 2/a discharged.
1.2 BOARD LAYOUT
1_2.1 Oscillator Connection
The oscillator components must be built as close to the pins
of the clOCk chip as is physically possible, The ideal configuration is shown in Figure 4. From Figure 2, the oscillator
circuit, it can be seen that both Osc In and Osc Out are high
impedance nodes, susceptible to noise coupling from adjacent lines, Hence the oscillator should, as far as is practicable, be surrounded by a guard ground. The absolute
maximum length of PCB tracking on either pin is 2.5 cm (1
inCh). Longer tracks ihcrease the parasitic track to track
capacitances, increalling the risk of noise coupling and
hence reducing the overall oscillator stability.
Provisions must be made either to check the battery voltage
at regular intervals or to replace the cells regularly enough
to avoid the danger of using discharged cells. Once again
the manufacturers data regarding capacity and cell voltage
againsi time must be examined to determine a suitable cell
selection. A good alkaline system will supply 1'-2 years continuous time-keeping.
'
Where the system operates in humid or very cold environments (below 5°C), condensation or ice may form on the
PCB. This has the effect of adding parasitic resistances and
capacitances between pins 14 and 15, and also to ground.
This variation in loading adversely affects the stability of the
oscillator and in extreme cases may cause the o~cill~tor to
stop.
Lithium
Lithium cells are the most suitable cell for real-time clock
applications, A single cell with 3V potential is sufficient to
power the system. The cell potential is very stable over use
and the storage life is excellent. The energy density of lith- ,
ium cells is very high, giving enough capacity in a physically
small cell to power the clock continuously for at least 5 years
(at room temperature using a 1,000 mAh cell).
Keeping the PCB tracks as short as possible will help to
minimize the problem, and on its own this may be sufficient.
Where the operating conditions are particularly severe, the
PCB and oscillator components should be coated with a
suitable water repellent material, such as lacquer or silicon
grease (suitability being determined by the electrical prop- '
erties of the materials - high impedance and ,low dielectric
constant),
'
Several cells which are recommended for RTC use are
D2/3A', D2A', and 1/6DEUP". Each have 1,000 mAh
capacity, These cells are available with solder pin connections for PCB mounting, giving a reliable backup supply.
Other Cells and Notes
There are many other types of cells, both primary and secondary, which may be adapted for RTC use, When selecting
a cell type, attention must be paid to:
a, Cell capacity and phYSical size.
b. Storage (shelf) life. '
c. Voltage variation over use.
Figures 2 and 4 show the trimmer placed on 'Osc Out. The
placement of the trimmer capacitor on either Osc In or Osc
Out is not critical. Placing the trimmer on Osc Out yields a
smaller trim range, but less susceptibility to changes in trim. mer capacitance, Placement of the trimmer capacitor on
Osc In gives a wider trim span, but slightly greater susceptibility to capacitance changes,
*OuraceJl Trade Number.
* *Tadiran Trade Number.
2-202
r------------------------------------------------------------,~
Z
w
m
FIGURE 4. Oscillator Board Layout
1.2.2 Battery Placement
1.2.3 Other Components
For the batt~ry, placement is less critical than with the oscillator components. Practical considerations are of greater
imporlance now; i.e. accessibility. The battery should be
placed where it is unlikely to be accidentally shorted or disconnected during routine operation and servicing of the
equipment.
The placement of the other RTC dedicated components
(e.g., supply disconnection and power failure protection
components) is not particularly critical. However, the same
guidelines. as applied to the battery should be followed when
the PCB layout is designed.
1.3 POWER SUPPLY ISOLATION SCHEMES
When replaceable cells are used, connecting a 100 !,F
capacitor across the RTC supply lines will keep the clock
operating for 30-40 seconds with the battery disconnected
(Figure 5). This allows the battery to be replaced regardless
of whether or not the main supply is active.
....
r--~--
1.3.1 The Need for Isolation
There two reasons for disconnecting the clock circuit from
the rest of the system:
1. To prevent the backup battery from trying to power the
whole system when the main power fails.
2. To minimize the battery current (and extend battery life)
by preventing current leakage out of the RTC input pins.
....- - t - +5V
--~,.....-
The MM58274 inputs have internal pull-up devices which
pull the inputs to VDD in power down mode. This turns off the
internal TTL input buffers and causes the !,P interface functions of the clock to go to full CMOS logic levels, drawing no
supply current (except for the unavoidable leakage current
of the internal MOS transistors). For the MM58274 this is
achieved by isolating the ground (Vss) supply line from the
rest of the system.
3.6V
BATTERY..L
'--....- -....- -........0-4 .........-.-ov
Figures 6a and 6b show the two cases where first VDD (6a)
and then Vss (6b) are open-circuited. The line out from the
MM58274 represents any of the Control, Address, or Data
lines on the RTC, with the internal pull-up resistor shown.
The two diodes and resistor Rs represent the logic device
connected to the RTC input and the resistance of the rest of
the system with no power applied.
100 RF
TLlF16737·5
FIGURE 5. Simplified Power Supply Diagram with
100!,F Capacitor Added
2-203
U) r-----------~------------------------------------------------------------------------~
~
VDD DISCONNECTION
,
Z
Z
~
1.4 POWER FAIL PROTECTION
rt.lF16737 \1
FIGURE 10. Battery Discharge Path via Un isolated
Interrupt Output
None of the disconnection components are at all critical,
with general purpose transistors being completely adequate
for the. t~sk. 01 should be a small-signal silicon or germanium diode.
lOne of the major causes of unreliability in RTC designs is
due to inadequate power failure protection. As the system is
powered up and down, the flP and surrounding logic can
produce' numerous spurious signals, including spurious
writes and illegal control signals (i.e., RD and WR both
active together).
Bipolar logic devices can produce spikes and glitches as the
internal biasing switches off around 3V-3.SV, and the transistors operate in their linear region for a short time. Any
such spurious signals, if applied to the RTC, could cause
the time ~ata to be corrupted. Systems using 74HC logic
and CMOS processors are less stringent in their power failure requirements as the devices tend to work right down to
around 2V. Some forl)1 of write protection is still required,
however.
1.3.3 Isolation Techniques II Negative Supply Switched
Where a negative! voltage supply is available (either regulated or unregulated) the circuit of Figure 11 may be used.
This is similar in operation to its diode equivalent shown in
Figure 12; where the voltage drops across the diodes provide the correct potential to the clock. Figure 11 has the
advantage, however that the clock power: is supplied from
the ground line by transistor action, rather than via the resistor as in Figure 12. Less power is dissipated in the resistor
as only transistor bias current need by drawn.
In order to protect the time data, the system must be physically prevented from writing to the clock when the power
supply is not stable. The ideal situation is to ban Write
access to the clock before the system + SV starts to fail, and
then keep the chip 'locked-out' until the power is restored
and stabilized. This ideal access control signal is illustrated
in Figure 13 .
.....- -....- - - - - - - + 5 V
Three methods of power fail protection are discussed,
although there are also many other possibilities.
INT
1.4.1 Write Protect Switch
By far the simplest and 'potentially the most hazard-free
method is to use a switch on the WR control line to the clock
(Figure 14). This is completely adequate, but requires the
intervention of an operator. to alter time data or program
interrupts.
-v,
Some thought must be given to ensuring that the operator
cannot accidentally leave the WR line switched in. This may
be achieved by the physical access method used (i.e., the
machine is impossible to operate or switch off when in the
time setting mode, because of the placement of access
hatches, etc.) or with software. The switch state could be
sensed by trying to alter the data in the Tens of Years
counter or Interrupt register just prior to leaving the clock
setting routine, and refusing to leave the routine until the
WR switch has been opened. The switch condition should
similarly be checked whenever the system is Initialized or
reset.
~-------DV
TLlF16737.12
FIGURE 11. Negative Voltage Driven Supply
Disconnection Scheme (Decou piing
Capacitors Omitted for Ctarity)
.-------.....------ + 5V
The physical location of the switch should also be considered for ease of accessibility. How easy the switch is to
reach will depend on the system; i.e., in some cases a 'tamper proof' clock may be required.
-V, --'1M"..............
FIGURE 12. Diode Equivalent Circuit of Figure 11.
2·20S
•
-SYSTEM SUPPLY
SYSTEM SUPPLY
UN/DEFINED
UNDEF\INED
PRE.FAILURE
LOCKOUT PERIOD
_ _ _+-I!+,O+----~~RD~A~p~~~~~~J
SYSTEM 5V
I
POST.FAILURE
LOCKOUT PERIOD
---+'-1;-+-_.......
~~ _ _ _ _ _ _ _ _ _ _---J~
WRITE ACCESS'"E'NABLE
TLlFl6737."
FIGURE 13. RTC Access Lockout Definition
selected to suit the Zener diode reference used. The combination of R4, D3 and C2 provide an RC time coh.stant to
delay the comparator when sensing the return of 5V (to pro·
vide the post·failure delay in Figure 13). The LM139 has an
open·collector output which is held low when 5V is present
and is switched off when 5V fails. This line is pulled high by
R5 to flag power failure (P. Fail). Since the comparatpr is a
linear device drawing a bias current, it is powered by the
system 5V supply to avoid consuming battery power.
One 74HC75 package contains four latches, of whioh two
are used. These are transparent latches controlled by the
'G' input. With G high, the latch is transparent and the Q
and Q outputs follow the Data input. When G is low, the
state of Q and on the falling edge is latched. In this way,
F2 prevents P. Fail from locking out the clock if there is a
Write cycle in progress. F1 isolates the WR input on the
clock when F2 passes the P. Fail signal. C1, R2 and D1 do
not slow the advent of P. Fail, but they cause a delay in the
release of the function to mask any comparator noise or
oscillation as the comparator switches off or on (i.e., during
the undefined supply periods).
FIGURE 14. Write Protection by Manually
Switching WR
a
1.4.2 5V Sensing
The circuit of Figure 15 senses the system 5V supply and
prevents access to the clock if the supply falls below
4.2V-4.3V. This circuit should be used where only the sys·
tem 5V is available for reference. The LM139 comparator
and associated components sense the 5V supply and gen·
erate the power fail signal (P. Fail). The 74HC75 and compo·
nents disconnect the WR line.
D2, C3 and R6 smooth the comparator supply and help it to
function effectively. The time constants of the RC networks
should be selected to suit the power supply of the system
that is used. Comparing the functioning of this circuit with
the ideal case of Figure 13 shows that most of the conditions
can be satisfied, except that there is no real pre·failure lockout period. This cannot be achieved without some form of
look ahead power failure.
R3 and ZD1 provide a referehce voltage of 2V-3V for the
comparator. R4 and VR1 form a potential divider chain
sensing the 5V line, and VR1 is adjusted to switch the com·
parator output at 4.2V-4.3V. An alternative to VR1 would be
to use a pair of close tolerance resistors (± 2%) with values
WR FROM pP
CONTROL BUS
r---~----'~---'---~--+-'---'~-~--~---~---+5V
02
VBAT.L
FIGURE 15. Power Supply Failure Detection and Write Protection Circuitry
2·206
As an alternative to Fl a permanently powered 74HC4066
analog switch could be used as the isolating component
(Figure 16). The 74HC4066 does not require pull-up resistors
on its inputs as there are no internal CMOS buffers inside
this device which must be controlled. The resistor on the
WR line is for the benefit of the 74HC7S.
1.4.4 Switching Power Supplies
Switching power supplies are available which generate
power failure signals. This signal may be adequate for direct
use as a P. Fail line, but the manufacturer's information
should be consulted to determine the suitability of a given
power unit. P. Fail must still be gated with the Write signal for
the clock, regardless of the actual detection method
employed.
Note that both of the devices mentioned must be permanently powered from the battery to be useful in this way.
Unused gates in any such device must NOT be used in combinational logic that is not permanently powered. All unused
inputs should be tied to VDD or Vss to. render them inactive.
~----~----------------~-------t------------~---t-----+5V
Voo
MM58274
cs
no
p. FAIL
iiiii
Vss
VSAT..L
OV
•
FIGURE 16_ Fl Replaced by a 74HC4066 Analog Switch (Pull-Up ftesistors Not Required on CS or RD Inputs)
1.4.3 Supply Pre-Sense
The same circuit of Figure 1S can be used with unregulated
supplies or other voltage lines which will fail before the SV
line. To aChieve this, point X is connected to the sensed voltage instead of Sv, and the R4IVR 1 ratio is adjusted to suit.
The majbr benefit here is that advance warning of an
impending SV failure can be detected, allowing a pre-failure
lOCkout signal to be generated.
+5V
Rp (= R5 IN FIGURE 14)
Cs +
RUM
P. FAIL
Less precision is required to sense the unregulated supply
than the system 5V supply. Consequently less complex circuitry can be used to do the detection and this is reflected in
the circuit of Figure 17. Most SV regulators will operate with
an input voltage from 7V to 2SV. Typically the input voltage is
around 9V to 12V, giving some headroom. In Figure 17 this
voltage is high enough to drive a current through the Zener
diode and turn on transistor TR1, holding P. FAIL low. RUM
limits the Zener current. The Zener voltage is selected to
switch off before the regulator fails, around 7.SV-S.5V
depending on the time constant of the supply. With no current, TRl switches off and Rp pulls P. Fail high.
~--------t-----~~--4--0V
TLIF/673?16
FIGURE 17. Power Fail Signal Generation from
Unregulated Supplies
1.4.5 Summary
The general guidelines for power fail protection are:
1. Physically isolate the WR input to the clock. The I'P
cannot be relied upon to logically operate the isolation
mechanism.
2. The clock should be isolated before the SV power line
starts to fail, and stay isolated until after it has reestablished.
3. Consider the action of the sensing and protection circuitry if the supplies oscillate or if a momentary glitch
occurs.
When power is re-applied the SV supply will stabilize before
the Zener switches on, removing P. Fail. To provide a longer
post-failure lockout period RUM could be replaced with two
resistors and a diode/capacitor delay as in Figure 1S.
Figure 18 is another extension of the same basic idea to pro-
vide an advance interrupt signal to allow I'P houseke.eping
before the RTC (and CMOS RAM) is lOCked out. The extra
rectifying components Dl, Ct and Rt keep NMI off as long as
input power is present. Time constant 72 is selected to be at
2-3 times faster than 710 the supply time constant. The interrupt signal is thus asserted before P. Fail.
2-207
....~_~_--+5V
....--1-----+ p. FAIL
NMI
--~----------~~--4-~----~~~-'--OV
'RS
= EQUIVALENT RESISTANCE OF THE SYSTEM.
lUFI6737·"
FIGURE 18. Power Fail Circuit with !,P Housekeeping Interrupt
4. The Power Fail sigoal must be gated with Write strobes to
the ATC. A foreshortened Write may also cause data corruption.
5. Logic components. (and ICs in general) should be
avoided when designing power failure schemes. Discr.ete
components are far more predictable in their. performance when the power supplies are not well defined. The
exception to this general rUle is when using permanently
powered HCMOS logic devices. They will function in a
reliable manner down to 2V.
2.1.2 Pre-Read Synchronization
The Interrupt Timer technique uses pre-read synchronization. Once it has been initialized as described, the interrupt
timer times out just after the real-time data has changed.
Thus the !,P is guaranteed a full 100 ms period in which to
read the time counters before the next change occurs.
The interrupt timer has to be synchronized with the realtime counters because it is an independent unit which may
. be started and stopped at any time by the !,P. This software
synchronization is achieved by using another pre-read technique. The timer is set up and ready to go, but then the I'P
waits for DCF to occur before issuing the start command.
The same technique could be used to actually read the
time~data, but post-read synchronization is faster.
System-powered logic devices cannot be reiied on for power
failure or Write isolation (not even CMOS).
2.0 SOFTWARE
2.1 DATA VALIDATION
2.2 INTERRUPT AS A 'DATA-CHANGED' FLAG
The MM58274 data sheet describes in some detail three different methods of reading the clock and validating the realtime data. These iechniques' are reproduced in Appendix
A-t. Rather than repeating the data sheet examples, this
applications note examines the principles that lie behind the
techniques suggested.
.
DCF is set every 100 ms when the l/tOths of seconds
counter is changed. When the time is only being read to the
nearest second or minute, it would be useful to have a flag
which is only set by a change in the lowest order counter
being used.
2.1.1 Post-Read Synchronization
If the interrupt output from the clock is not being used, the
timer can be used as a programmable data-changed flag. To
achieve this, the timer is set up and started in exactly the
same way as described for interrupt time reading (Appendix
A-1). The interrupt output however, should be left unconnected. When reading the real-time data, the technique
used is the same as for the normal Data-Changed Flag
except that the Interrupt Flag is tested instead of DCF.
USing the Data-Changed Flag (OCF) or the lowest order
time register as outlined in the appendix: Time Reading
using DCF and Time Reading with very slow Read cycles;
are both examples of post-read synchronization.
Note that the lowest order real-time register which is to be
read out should be used to initially synchronize the counter.
The interrupt timer is started when the real-time counter
value is seen to change.
The basic problem is that the !,P must somehow be synchro-·
nized with the changes in real-time in order to read valid
data. This synchronization can either be done prior to reading the time data (pre-read), or after reading the data (postread synchronization).
What this means is that the data is read out first, and then
verified. This is achieved by defining a random time-slot,
started by the first DCF or low order register read, and
ended by the second such read. If DCF has not been set
during the time-slot or the lowest order register has not
changed, then no real-time change occurred during that
time-slot. All real-time reads during the time-slot are thus
guaranteed.
2.3 WRITING WITHOUT HALTING TIME-KEEPING
For most purposes the ATe should be halted when the time
is being set, especially if large numbers of counters are
2-208
being updated. The clock can also then be re-started in synchronism with an external time r.eference. If only a few
counters are to be altered and the clock'is already synchronized, then this can' be done without s$opping the clock. An
example of a minor change which may be undertaken in this
way is daylight savings (winter/summer change of hour).
3.0 MISCELLANY
3.1 CONNECTION TO NON Microbus™ SYSTEMS
Adding the MM58274 to non Microbus processors is made
fairly straightforward because of the flexibility of the control
signal timing. Figure 19 shows two examples of logic to connect the clock to a 6502/6800 microprocessor bus.
The problem to be overcome when writing in this way is that
the write strobe may coincide with a time change pulse. As
the time counters are synchronous, the 100 ms clock pulse
is fed to each one. Writing to one counter may cause a spurious carry to be generated from that counter, caus,ing the
next one up the chain to be incremented.
Figure 19a the RD and WR inputs are strobed, generating
reasonably typical Microbus type control signals. In Figure 19b, CS is used as the strobe signal. There is no particular advantage to either circuit, they are just variations on the
same theme. This circuit flexibility may be used to advantage to save SSI packages in the board design.
Since a spurious carry will only affect the next counter if it
coincides with a time update pulse, the solution is once
again to synchronize clock access with the real-time
change. The most suitable method for this is pre-read synchronization. In other words, the !,P must wait for DCF to be
set before starting to write data to the clock, giving a guaranteed 100 ms period for writing.
cs-------1
RIW -._-,",\
2.4 THE CLOCK AS A !,P WATCHDOG
The interrupt timer can be used as a !,P watchdog circuit,
operating on a non-maskable interrupt input to the pP. The
timer is se, up in either single or repeat interrupt mode for
the watchdog period required: 0.1 s, 0.5s or 1 second are
probab'ly the most useful times for this. Synchronization
with real-time is not required.
a)
<'2
CS
In the main program loop the !,P writes to the clock,
stopping and then re-starting the interrupt timer. The timer
period selected will depend on how long the main loop takes
to execute. As long as the "p continues to execute the loop,
no time-outs occur and no interrupts are generated. If the
"p fails for some reason to reset the timer, it eventually
times out, generating the initializing interrupt to restore
operations.
R/W-....---4
TlIF/6737-21
b)
FIGURE 19. 6800/6502 "p Bus Interface
2.5 THE JAPANESE CALENDAR
Because the MM58274 has a programmable leap year
counter, this allows the possibility of programming for the
Japanese Showa calendar. The Japanese calendar counts
years from the time that the present Japanese Emperor
comes to power. Emperor Hirohito took office in 1926
(Showa year 1), hence 1984 is Showa year 59. Since the
days and months of Showa follow the Gregorian pattern,
Showa year 59 is also a leap year.
3.2 TEST MODE
Test Mode is used by National Semic;onductor when the
MM58274 is tested during manufacture. It enables the realtime counters to be clocked rapidly through their full count
sequence.
The MM58274 counters are clocked synchronously to simplify "p access, with ripple carry signals from each counter
to the next. In Test Mode some of these carries are intercepted and permanently asserted causing the counters to
count each clock pulse. The prescaler is also bypassed so
that the counters count every clock applied to the Osc
In pin. The Test Mode counter connection is shown in
The normal law for the MM58274 is to program 'the number
of years since last leap year: This remains the same
whether the clock is loaded with the Gregorian or Showa
year. When software is used to calculate the leap year
count value from the year, then the formula used must
be modified.
Figure 20.
The formula for the Gregorian year is:
Leap Year Value = [Gregorian Year/4J REMAINDER
If Test Mode is to be used for incoming inspection or device
verification, then the clock waveform of Figure 21 should be
applied to the oscillator input (Osc In, pin 15). The MM58274
uses semi-dynamic flip-flops in the counters which are only
fully"siatic when the oscillator input is high. Thus Figure 21
shows that the oscillator waveform is normally high, pulsing
low to clock the real-time counters. The time data in the
counters changes on the rising edge of Osc In.
Whereas for the Showa year the formula is:
Leap Year Value = [(Showa Year + 1)/4J REMAINDER
Leap Year Value is the number from a to 3 which is written
into the leap year counter, and is the REMAINDER of the
integer calculations shown above.
2·209
•
ISOLATED IN TEST MODE
CLOCK
START/STOP
XTAL o-..Doo-_....,...-!_.)
IN
x.;r~~ o--2"'00"'k"'ll.......
iNT
v-~... r NO INTERRUPT
PROG'D
TEST MODE
INTERRUPT
PERIOD (SEC)
0.1
0.5
1
INTERRUPT""""'~o-_L-.J
5
10
30
60
S}ART/STOP
DIVIDE
COUNT
+49
+241
+481
+2401
+4801
+14401
'+28801
TUFf6737·22
FIGURE 20, Test Mode Interconnection Diagram of Internal Counter Stages
10 pS " tw " 35 pS IVDD = 2V-5.5V)
VIH" 75%VDD
OSC IN
(PIN 15)
I'
\
'I
,r-----.\'--~I~~TLiF/6737·23
FIGURE 21. Oscillator Waveform for Couriter Clocking in Test Mode
The pulse width limits for reliable clocking are shown on the
diagram. When running· with a 32 kHz crystal, the normal
pulse width is 15.26 p.s. With no forcing input, the oscillator
will self bias to around 2.5V (VDD = 5V). While a few hundred mV swing above and below this level is sufficient 10
drive the oscillator, for guaranteed test clocking the input
should swing between V1H 2! 75% VDD and V1LS 25% VDD .
ing the ATC into test mode, then disconnecting it from the
system to tune on battery backup). Alternatively, the clock
can be slightly overtuned at operational voltage, tuning to
32.7681 kHz.
In a similar way, where the RTC spends equal amounts of
time in both operational and standby modes (Le., powered
by day, standby at night), the oscillator may be tuned somewhere between the two conditions. Following these tuning
suggestions will not eliminate time-keeping errors, but they
will help in minimizing them.
3.3 TEST MODE AND OSCILLATOR SETTING
When Test Mode is used to set the oscillator frequency, the
interrupt timer must be disabled (interrupt register programmed with all Os) for the oscillator frequency to appear
on the interrupt output. No test equipment should be connected directly to either oscillator pin, as the added loading
will alter the characteristics of the oscillator making precise
'
tuning impossible.
Time-keeping accuracy cannot be exactly specified. It
depends on the quality of the components used in the oscillator circuit and their physical layout, also the stability of the
supply voltage, the variations in ambient temperature, etc.
With good components and a reasonably stable environment however, time-keeping accuracy to within 4 seconds/
month can be achieved, although 8 seconds/month is somewhat more typical in practical systems.
Note that oscillator frequency will vary slightly as the supply
varies between operating and standby voltages. Typically
this variation will be around ± 6 seconds per month
(VSTANDBY = 2.4V), slowing at standby voltage. When the
clock will spend the greater part of its working life in standby
mode, it may prove worthwhile to correct for this in the tuning. This can be done by tuning at standby voltage (by writ-
3.4 UPGRADING AN MM58174A SYSTEM WITH
THE MM58274
The MM58274 has the same pin-out as the MM58174A and
can be used as a direct replacement, with certain reserva2-210
tions. The two devices are not quite the same in their external circuit appearances, and this is reflected in their
applications circuits. In addition, the MM58274 is not software compatible with the MM58174A, requiring a change in
the operating system to use the MM58274.
The change of pin of the tuning capacitor (from Osc Out to
Osc In) is not critical.
b) The Supply Disconnection Scheme
The MM58174A uses mostly pull-down devices on its IlP
inputs to pull the inputs to CMOS levels, and so the 5V
power line is discon'.:!!Zted o.!:J!lis device. The two exceptions to this are the CS and WR inputs which have pull-up·
resistors to inactivate the internal write st~obe. As Figure 5a
Figure 22 shows the circuit diagram for the MM58174A system connection. There are two major differences between
this and the MM58274 diagram (Figure 1); a) the oscillator
circuit and b) the supply disconnection scheme.
-
. rr--+
100nF~
,
READY
~
~
DELAY
STROBE
GENERATOR
(SEE
FIGURE 9)
~~
'"~
iiii
:il
'-'
WR
DB3
DB2 .
'" I'
DBl
DBO
;
AD3
AD2
AD1
ADO
INTERRUPT
.£!.
~
.J
TJVDD
74HC4066 :
f"
4.7k
OV
rh
CS 1
RD 2
WR 3
'-'
5
6
7
r
I
L
4
~
5V
~ ~ 3·5V
r-
H+
POWER
CHIP
SELECT
lOGIC
~
C1I
2.2k
10k
~
l>
Z
MM58174A
16
15- r
OSCilLATOR GUARD GROUND (OPTI ONAl)
- - - - - - - - - --1
~
13
12
4.~
,t
O~
I
I
~ 1:2.768 kHz ~
I =15 pF::;i-_6-36_pF...JI
LI--~~
19
* Use resistor with Ni-C ad cells only.
.....
TLF67372':
FIGURE 22. MM58174A System Installation
a) The Oscillator Circuit
'
The MM58274 normally operates with an 18 pF-20 pF fixed
loading capacitor as opposed to the 15 pF of the MM58174A.
This is a reflection of the greater internal capacitance of the
MM58174A, rather than any change in the characteristics
of the oscillator itself. The MM58274 will operate using a
15 pF capacitor, but the oscillator will probably need to be
retrimmed.
shows, there is a leakage path through these pins, which in
most MM58174A installations are individually isolated.
The largest penalty in inserting an MM58274 into' an
MM58174A circuit is the battery current that is lost through
the pull-up devices. This will increase the typical supply current from 4 IlA to 50-100 IlA and it is up to the individual user
to decide whether or not this drain is tolerable in a particular
application.
Operating with a 15 pF capacitor will make the oscillator
more sensitive to changes in the environment, i.e., temperature, voltage, moisture, etc. This will result in lower accuracy
in time-keeping. The oscillator is more prone to stopping at
low voltage. Oscillation would normally be mainfained down
to 1.8V-1.9V (although not guaranteed); with a 15 pF load it
may only oscillate down to 2.0V-2.1 V. It is thus.important to
check the battery regularly and replace it before the RTC
voltage falls below 2.2V.
The most important requirement is that the WR input should
be electrically isolated or current leakage through pin inputs
may force the inputs low enough to cause spurious writes to
occur. Since it is already customary to isolate these inputs
for the MM58174A, this may not be a problem. Where this
has not been done, either the circuit will have to be modified
or the WR PCB track can be cut and a switch or some extra
circutry added to allow isolation.
Note that power fail disconnection and input isolation may
be achieved using the same components. In Figure 22 the
MM74HC4066 analog switch will do both jobs.
Where possible the 15 pF capacitor should be replaced by
an 18 pF-20 pF capacitor (anywhere in the range 18 pF20 pF is adequate), or a second 3 pF-5 pF capacitor may be
added in parallel with the 15 pF.'
The current drained by the input pull-ups may be minimized
with some attention to the data/address driving devices. It is
·When components have been soldered into the oscillator circuit, allow the
circuit to cool to room temperature before attempting to retune the OSCillator.
2·211
fII
~
~
Z
«
,-----------------------------------------------------------------------------,
duce wait states of any length required to enable the RTC to
be accessed, using the 74HC74 dual D-type flip-flop.
often possible to replace LSTTL devices with standard 7400
series devices and reduce the leakage (at the cost of some
increase in operating current). Many 7400 series device outputs lack diodes in the right places to pass leakage currents. LSTTL devices will, for the main part, have these
diodes, CMOS devices will always have diodes to both
power rails on inputs and outputs.
The RTC CS signal clocks up a logic 1 on the Q output of th,e
first F/F, removing the Preset from all the other F/Fs and,
pulling the !,P WAIT line low, via the transistor. The other
F/Fs 1 to n, form a shift register clocked by 1he <1>2 system
clock.
There is no hard and fast rule for this. Where devices from
one manufacturer work, the same part from a differEint one
may not. Some trial and error experimentation may prove
worthwhile in selecting devices.
After n <1>2 clocks (where n is the number of flip-flops in the
shift register) a logic 0 shifts out from the nth F/F, resetting
the main flip-flop. The main F/F then presets the shift register and clears the WAIT signal, ready for the next CS edge to
repeat the cycle. On power-up the delay generator will initialize itself after a maximum of n system clocks have
occurred so no reset signal is required. Some !,Ps demand
that a WAIT/READY input is synchronized with <1>2 of the system clock. This can readily be achieved by selecting the correct <1>2 edge as the clock signal for the shift register chain ..
3.S WAIT STATE GENERATION FOR FAST !,Ps
f,llthough' the MMSB274 has faster access times than the
MMSB174A, in many cases, the !,P will be too fast to directly
access the RTC, Figure 23 shows a circuit which will pro-
FLlp·FLOP - MM74HC74 D·TYPE LATCH
10 _P WAIT/READY I/P
02 OR ~
(CHECK ,P o-----+-~
REQUIREMENTS)
.....- - - -.....---TLIFI6737·;>S
FIGURE .23. Access Delay Generator (Clocked wait State Generator)
2·212
~--------------------------------------------~--------~>
APPENDIX A-1. READING VALID REAL-TIME DATA
4) Read control register ADO repeatedly until data-changed
flag is set.
TIME READING USING DCF
5) Write 0 or 2 to control
Using the Data-Changed Flag (DCF) technique supports
microprocessors with block move facilities, as all the necessarY time data may be read sequentially and then tested for
validity as shown below.
1) Read the control register, address 0: This is a dummy
read to reset the data-changed flag (DCF) prior to reading
the time registers.
2) Read time registers: All desired time registers are read
out in a block.
3) Read the control register and test DCF: If DCF is stiff
clear (logic 0), then no clock setting pulses have occurred
since step 1. All time data is guaranteed good and time
reading is complete.
If DCF is set (logic 1). then a time change has occurred
since step 1 and time data may not be consistent. Repeat
steps 2 and 3 until DCF is clear. The control read of step 3
will have reset DCF, automatically repeating the step 1
action.
TIME· READING USING AN INTERRUPT
In systems such as point-of-sale terminals and data loggers,
time reading is usually only required on a random demand
basis. Using the data-changed flag as outlined above is
ideal for this type of system. Where the I'P must respond to
any change in real-time (e.g., industrial timers/process controllers, TV/vCR clocks or any system where real-time is
displayed) then the interrupt timer may be for time reading.
Software is used to synchronize the interrupt timer with the
time changing as outlined below:
register. Interrupt timing
commences.
When interrupt occurs, read out all required time data.
There is no need to test DCF as the interrupt 'presynchronizes' the time reading \ilready. The interrupt flag is
automatically reset by reading from ADDRO to test it. In
repeat interrupt mode, the timer continues to run with no
further I'P intervention necessary.
TIME READING WITH VEFW SLOW READ CYCLES
If a system takes longer than 100 ms to complete reading of
all the necessary time registers (e.g., when CMOS processors are used or where high level interpreted language routines are used) then the data-changed flag will always be set
when tested and is of no value. In this case, the time registers themselves must be tested to ensure data accuracy.
The technique below will detect both time changing
between read strobes (i.e., between reading tens of minutes
, and units of hours) and also time changing during read,
which can produce invalid data.
1) Read and store the value of the lowest order time register
required.
2) Read out all the time registers required. The registers
may be read out in any order, simplifying software
requirements.
3) Re-read the lowest order register and compare it with the
value stored previously in step t. If it is still the same,
then all time data is good. If it has changed, then store
the new value and go back to step 2.
In general, the rule is that the first and last reads must both
be of the lowest order time register. These two values can
then be compared to ensure that no change has occurred.
This technique works because for any higher order time register to change, all the lower order registers must also
change. If the lowest order register does not change, then
no other register has changed either.
1) Select the interrupt register (write 2 or 3 to ADDRO).
2) Program for repeated interrupts of the desired time interval (see Table liB in Appendix A-2): Do not start the timer
yet.
3) Read control register ADO: This is a dummy read to reset
the data-changed flag.
2-213
z
~
CIt
APPENDIX A-2. FUNCTIONAL TRUTH TABLES FOR MM58274
TABLE I. Address Decoding for Internal Registers
Address Bits
Register Selected
.).
o Control Register
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Tenths of Sees
Units Seconds
Tens Seconds
Units Minutes
Tens Minutes
Units Hours
Tens Hours
Units Days
Tens Days
Units Months
Tens Months
Units Years
Tens Years
Day of Week
Clock Settingllnterrupt Registers
AD3
AD2
ADl
ADO
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
·1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
l'
0
0
0
0
1
1
1
1
Access
Split Read and Write
Read Only
RIW
RIW
,
R/W
RIW
R/W
RIW
RIW
RIW
~
R/W
RIW
RIW
RIW
RIW
Riw'
TABLE IIA. Clock Setting Register Layout
Data Bits Used
Function
Leap Year Counter
DB3
DB2
X
X
AMIPM Indicator (12 Hour Mode)
Comments
DBO
DBl
X
12-24 Hour Select Bit
Access
o indicates a Leap Year
RIW
0= AM 1 = PM
o in 24 Hour Mode
RIW
o=
12 Hour Mode
1 = 24 Hour Mode
X
RIW
TABLE liB. Interrupt Control Register
~
No Interrupt
0.1 Second 0.5 Second
1 Second
5 Seconds
10 Seconds
30 Seconds
60 Seconds
Control Word
-
Function
Comments
DB3
DB2
DBl
DBO
X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
·0
1
Interrupt output cleared, StartlStop bit set to 1.
0/1
0/1
0/1
0/1
I
0/1
0/1
0/1
.
Timing Accuracy: Single Interrupt Mode (all time delays): , ± 1 ms
Repeated Mode: ±1 ms on initial timeout, thereafter synchronous with first interrupt (i.e., timing errors do not
accumulate).
DB3 =' 1 for Repeated Interrupt
DB3 = 0 for Single Interrupt
TABLE III. The Control Register Layout
Access (ADDRO)
DB3
DB2
DBl
Read From:
Data Changed Flag
0
0
Write To:
Test
Clock
Start/Stop
Interrupt
Select
Interrupt
StartlStop
0= Normal
1 = Test Mode
o=
o=
o=
Clock Run
1 = Clock Stop
2·214
Clk. Set Reg.
1 = Int. Reg.
DBO
Interrupt Flag
Int. Run
1 = Int. Stop
An Introduction to
and Comparison of
54HCT/74HCT TTL
Compatible CMOS Logic
National Semiconductor
Application Note 368
Larry Wakeman
March 1984
The 54HC/74HC series of high speed CMOS logic is
unique in that it has a sub·family of components,
designated 54HCT/74HCT. Generally, when one en·
counters a 54/74 series number, the following letters
designate some speed and power performance, usually
determined by the technology used. Of course, the letters
HC designate high speed CMOS with the same pinouts
and functions as 54LS/74LS series. The sub·family of HC,
called HCT, is nearly identical to He with the exception
that its input levels are compatible with TTL logic levels.
either the specific function does not exist in CMOS or the
CMOS device may not have adequate performance. Since
the system designer still desires to use HC where possible,
he will mix HC with these products. If these devices are
specified to be TTL compatible, incompatibilities may
result at the interface between the TTL, NMOS, etc. and HC.
More specifically, in the case of where a TTL or NMOS out·
put may drive an HC input, a specification incompatibility
results. Table I lists the output drive specifications of TTL
compatible outputs with the input specifications of
54HC/74HC. Notice that the output high level of a'TTL
specified device will not be guaranteed to have a logic
high output voltage level that will be guaranteed to be
recognized as a valid logic high input level by HC. A TTL
output will be equal tQ or greater than 2.4V, but an HCMOS
input needs at least 3.15V.lt should be noted that in an ac·
tual application the TTL output will pull·up probably to
about Vce minus 2 diode voltages, and HC will accept
voltages as low as 3V as a valid one level so that in almost
all cases there is no problem driving HC with TTL.
This simple difference can, however, lead to some confu·
sion as to why HCT is needed; how HCT should be used;
how it is Implemented; when it should be used; and how its
performance compares to HC or LS. This paper will at·
tempt to answer these questions.
It should also be noted that not all HCTs are the same.
That is, HCTs from other vendors' may have some charac·
teristics that are different. Thus, when discussing general
characteristics this paper will directly address National
Semiconductor's 54HCT/74HCT which is compatible with
JEDEC standard 7. Other vendors' ICs which also meet
this standard will probably have similar characteristics.
Even with the specified incompatibility, it is possible to
improve the TTL·CMOS interface without using HCT.
Figure 1 illustrates this solution, By merely tying a pull·up
resistor from the TTL output to Vec , this will force the out· .
put high voltage to go to Vee. Thus, HC can be directly in·
terfaced very easily to TTL. This works very well for
systems with a few lines requiring pull·URS, but for many
interfacing lines, HCT will be a better solution.
WHY DOES HCT EXIST?
Ideally, when a designer sits down to design a low power
high speed system, he would like to use 54HC/74HC, and
CMOS LSI components. Unfortunately, due to system reo
quirements he may have to use NMOS microprocessors
and their NMOS or bipolar peripherals or bipolar logic
(54S/74S, 54F/74F, 54ALS/74ALS, or 54AS/74AS) because
TYPICAL
LS·TTL OUTPUT
STANDARD
HC·CMDS INPUT
Vee
Vee
RI
TLJFI6751.'
FIGURE 1. Interfacing LS·TTL Outputs to Standard
CMOS Inputs Using a Pull·Up Resistor
2·215
~
C')
:Z
c::c
The input high logic level of HC is the only source of in·
compatibility. 54HC/74HC can drive TTL easily and its in·
put low level is TTL compatible. Again referring to Table I,
the logic output of the TTL type device will be recognized
to be a valid logic low (0) level, so there is no incompatibil·
ity here. Table II shows that the specified output drive of
HC is capable of driving many LS·TTL inputs, so there is no
incompatibility here either (although one should be aware
of possible fanout restrictions similarto that encountered
when designing with TTL).
WHEN TO USE 54HCT/74HCT LOGIC
The 54HCT/74HCT devices are 'primarily intended to be
used to provide an easy method of interfacing between
TTL compatible microprocessor and associated periph·
erals and'bipolar TTL logic to 54HC/74HC. There are
essentially two application areas where a designer will
want to perform this interface.
The question then arise!>: since only the input high level
must be altered, why not design CMOS logic to be TTL
compatible? 54HC/74HC was designed to optimize per·
formance in all areas, and making a completely TTL
compatible logic family would sacrifice significant per·
formance. Most importantly, there isa large loss of AC
noise immunity, and there are speed and lor die size
penalties when trying to design for TTL ipput levels,
1. The first case is illustrated in Figure 2. In this case the
system is a TTL compatible microprocessor. This figure
shows an NS16XXX (any NMOS p.P may be substituted)
that is in a typical system and therefore must be inter·
faced to 54HC/74HC. In this instance, the popular gate"
buffer, decoder, and flip-flop functions provided in the
54HCT/74HCT sub·family can be used to interface the
many lines that come from TTL compatible outputs, It is'
also easy to upgrade this configuration to an all CMOS
system once the CMOS version of the microprocessor is
available by replacing the HCT with HC.
Thus, since it is obvious that there is a need to inteilace
with TTL and TTL compatible logic, yet optimum perform·
ance would be sacrificed, a limited sub·family of HCT
devices was created. It is completely TTL input compat·
ible, which enables gua'ranteed direct connection of TTL
outputs to its inputs. In addition, HCT still provides many
of the other advantages of 54HC/74HC.
2. A second application 1s, when in speed·critical situations a faster logic element than HC, probably ALS or AS,
must be used in a predominantly 54HC/74HC system, or a
specific logic function unique to TTL is placed into an HC
design. This situation is illustrated in Figure 3. In this
case, pull-up resistors on an HC input may be sufficient,
but if not, then an HCT can be used to provide the guaran·
teed interface.
TABLE I. Ol,ltput Specifications for LS·TTL and NMOS LSI Compared to the Input
Specifications for HCT and HC
Note the specified incompatibility between the output levels HC input levels.
LS Output
Output,
High
Output
.Low
HC Inputs
NMOS Output
HCT Input
VOUT
lOUT
VOUT
lOUT
VIN
liN
VIN
liN
2.7V
400p.A
2.4V
400p.A
3.15V
1p.A
2.0V
1 p.A
0.5V
B.OmA
O.4V
2.0mA
0.9V
1p.A
0.8V
1 p.A
,
Input
High
Input
vee = 4,5V
TABLE II. 54HC/74HC and 54HCT/74HCT Output Specifications Compared to
54LS/74LS TTL Input Specifications and Showing Fanout
Both HC and HCT output specifications are the same for the two sets of output types.
HC Output
Standard
Output
Bus
Output
Output
High
Output
Low
Output
High
Output
Low
HCTOutput
LS Inputs
VOUT
lOUT
VOUT
lOUT
VII~
liN
3.7V
4.0 mA
3.7V
4.0mA
2.0V
40p.A
O.4V
4,OmA
,0.4V
4.0mA
O.BV
400p.A
3.7V
6.0mA
3.7V
6.0mA
2.0V
40p.A
O.4V
6.0mA
O.4V
6.0mA
O.BV
400p.A
Vee=4.5V
2·216
Fanout
10
15
...
A16A23
"
,....
ADDAD15
AD-A23
74HCT244
!
I-
74HCT373
NS16XXX
CPU GROUP
lOR OTHER,J'1
,....
74HCT245
RD-WR
INTR
ROY
PH2
f
DO-D16
74HCT245
!
74HCXX
CMOS UART
CMOS PlO
CMOS D/A/D
74HCXX
CMOS RAM
CMOS EPROM
ALE
~
ADDRESS BUS
.oil
~DATABUsf
.oil
""
CONTROL BUS
lL/F/67512
FIGURE 2. Applications Where a TIL Compatible
NMOS Microprocessor is Interfaced to a CMOS
System
CMOS SYSTEM
....
"
,.....
,....
S, AS, FAST ALS
OR UNIQUE
TTL FUNCTION '
...,..
...
--,..
HCT
...
....,.
TL/F/6151·3
FIGURE 3. A Conceptual Diagram Showing How HCT
May Be Used to Interface a Faster ALS Part or Some
Unique TTL Function in a CMOS System
The functiqns chosen for implementation in 54HCT/74HCT
were chosen to avoid the undesirable situation where the
designer is forced to add in an extr.. gate solely forthe inter'
face. A variety of HCT functions are provided to not only in·
terface to HC, but to perform the desired logic function at
the same time.
PERFORMANCE COMPARISON: HCT vs HC LS·TTL
To enable intelligent use of HCT in a design, both for the interface to NMOS or TIL and for TIL replacement applica·
tions, it is useful to compare the various performance
parameters of HCT to those of HC and LS·TTL.
Input/Output Voltages and Currents
Although not the primary intention, a third use for 54HCTI
74HCT is as a direct plug·in replacement for 54LS/74LS
logic in already designed systems. 1f't"lCT is used to replace
,LS, power consumption can be greatly reduced, usually by
a factor of 5 or so. This lower power consumption, and
hence less heat dissipation, has the added advantage of in·
creaSing system reliability (in addition to the greater
reliability of 54HCI74HC and 54HCTI74HCT). This is extremely useful in power-critical designs and may even offer
the advantage of reduced power supply costs.
Table III tabulates the input voltages for LS·TTL and
LS·TTL compatible ICs, HCT, and HC. Since HCT was designed to have TTL compa!ible inputs, its input voltage
levels are the same. However, the input currents for HCT
are the same as HC. This is an advantage over LS-TTL,
since there are no fanout restrictions when driving into
HCT as there are when driving into LS.
Referring to Table II, the output voltage and current
specifications for HC and HCT gates are shown. As can be
seen, the output specifications of HCT are identical to HC.
This was chosen since the primary purpose of HCT is to
drive into HC as the interface from other logic.
One note of caution: when plug·in replacing HCT for TIL,
54HCTI74HCT(as well as 54HC174HC) does not have iden·
tical propagation delays to LS. Minor differences will oc·
cur, as would between any two vendors' LS products. To be
safe, it is recommended that the designer verify that the
performance 6f HCT is acceptable.
2·217
There are some differences as to how LS-TTL, ALS-TTL
and AS-TTL outputs are specified when compared to HCT
(or HC), as shown in Table IV. The military parts are ~asy to
compare. HC/HCT has the same 10L as LS and much
greater 10H' At the commercial temperature range a direct·
comparison is difficult. LS has a higher output current, but
also a higher output voltage and narrow operating temperature range. Taking these into account, the output drive of
74HC/HCT is roughly the same as LS.
This may be a minor point since normally HCT is mixed
with TTL and in this case the worst-case system noise
margin is defined by the TTL circuits. If the HCT is being
driven only by HC and not LS, then the worst-case Vee
margin is determined by the HC devices. This is not a norma~ usage, but may occur if, for example, some spare HCT
logic' can be utilized by HC to save chip count. Figure 4
graphs input noise margin for HC, HCT in an LS application and HCT being driven by HC. As one can see, the HC
has a large Vee and ground noise margin, the HCT interfacin'g from LS has a miirgin equal to LS, and the HCT interfacing from HC has'a skewed margin_
In the HC family, there is a higher output drive specified10r
bus compatible devices. 'Again, HCT is identical. As can
be seen back in Table II, the bus drive capability of both HC
and HCT are identical, and both source and sink currents
are symmetrical. This increased drive over standard devices provides better delay times when they are used in
high load capacitance bus organized CMOS systems_
r----------,
5.0
E
w
...
~.
4.0
~
co
Both HC and HCT also have another voltage/current
specification which is applicable to CMOS systems. This
is the no load output voltage. In CMOS systems, usually
the DC output drive for a device need not be greater than
several p.A since all CMOS inputs are very high impedance.
For this reason, there is a 20 p.A output voltage specification which says that 54HC/74HC and 54HCTl74HCT will
pull to within 100 mV of the supplies.
:» 3.0
t-
:::0
!;
2.0
~
t-
~
E 1.0
I
!i
0.0
(al
NOISE MARGIN TRADEOFFS WITH HCT
(el
(bl
. . , = specified data sheet performance
The nominal trip point voltage for an HCT device has been
designed to be around 1.4V, as compared to the 2.5V for a
standard HC device. This will degrade the ground level
noise margin for HCT by almost a volt: HC, on the other
hand, has its trip point set to offer optimal noise margin
for both Vee and ground.
c:::J
= actual device performance
TLIFI67S1·4
FIGURE 4. Guaranteed and Typical Noise Margins for
a) HC b) HCT in TTL System c) HCT in HC System
TABLE III. A Comparison of Input Specifications for 54LS/74LS, NMOS·LSI, 54HC/74HC,
and 54HCT/74HCT
.
The HCT specifications maintain the TTL compatible input voltage requirements and the He input
currents.
LS Inputs
Input
High
Input
Low
NMOS· LSI Input
HC Inputs
HCTlnput
VIN
liN
VOUT
lOUT
VIN
liN
VIN
liN
2.0V
40p.A
2.0V
10p.A
3.15V
1 p.A
2.0V
1 p.A
0.8V
400p.A
0.8V
10p.A
0.9V
1 p.A
0.8V
1 p.A
Vee=4.5V
TABLE IV_ This Compares the Output Drive of HC and HCT to LS for both the Military
Temperature Range and the Commercial Temperature Range Devices at Rated Output Currents
Commercial Temperature·
Military Temperature
HC/HCT Output
LS Output
HC/HCT Output
VOUT
lOUT
VOUT
lOUT
VOUT
lOUT
VOUT
lOUT
Input
High
3.7V
4.0mA
2.5V
400 p.A
, 3.84V
4.0mA
2.7V
400p.A
Input
Low
O.4V
4.0mA
O.4V
4.0mA
0.33V
·4.0mA
0.5V
8_0mA
,
Vee=4.5V
*The commercial temperature range for HC/HCT is - 40°C to
+ 85°C, but for LS it is O°C to 70*C.
2-218
LSOutput
POWER CONSUMPTION OF HCT
In normal HC applications, power consumption is essentially zero in the quiescent state but is proportional to
operating frequency when operating_ In LS, large quiescent currents flow which overshadow (except at very high
frequencies) other dynamic components_ 54HCT/74HCT
is a combination of these, depending on the application.
Both quiescent and frequency-dependent power can be
significant.
Referring back to Figure 1, this figure shows an LS-TTL
output driving an HCT input. To see how quiescent current
is drawn, notice that it is possible to have valid TTL
voltages of 2.7V and OAV (ignoring the pull-up resistor).
With OAV on the HCT input, we find the input N-channel
transistor OFF and the P-channel ON. Thus, the output of
this stage is high. Also, since one of the P or N-channel
transistors is OFF, no quiescent current flows. However,
when the HCT input is high, 2.7V, the III-channel is ON and
the P channel is slightly ON. This will cause some current
to flow through both the transistors, even in the static
state.
Thus in a TTL applcation, HCT has the unusual characteristic that it will draw static current only when its inputs are
driven by TTL (and TTL-I ike) outputs, and only when those
outputs are high. Thus, to calculate total power, this
quiescent power must be summed with the frequency-dependent component.
When HCT is driven by HC, as it possibly might be, the HC
outputs will have high and low levels of Vee and ground;
never statically turning on both transistors simultaneously_ Thus in this application, HCT will only dissipate
frequency-dependent power, and CpD calculations can be
made to determine power (see National Semiconductor
application note, AN-303). In the latter application, HCT
will dissipate the same amount of power as HC; in the first
TTL application, the power dissipated will be more Since
there is also a DC component.
To show this, Figure 5 plots power versus frequency for an
HCTOO being driven by HC, typical LS and worst-case LS.
Notice that at the lower frequencies, the DC component
for the TTL input is much greater; at higher frequencies,
the two converge as the dynamic component becomes
dominant.
SPEED/PROPAGATION DELAY PERFORMANCE
Of primary importance is the speed at which the components operate in a system. HCT was designed to have
the same basic speeds as HC. This was accomplshed in
spite of the fact that HCT requires the addition of a TTL input translator, which will add to internal propagation
delays. A second concern in the design was to maintain
the required speeds while minimizing the possible power
consumption of the input stage when driven TTL high
levels.
These requirements dictated designing HCT on a slightly
more advanced 31' N-well process, as well as increasing
the die to help compensate for speed loSS. This process is
slightly faster than the standard HC process, and this
enables the HCT parts to have the same delays as their HC
counterparts, while minimizing possible quiescent currents. Figure 6 shows a comparison of 74HCT240 and
74HC240 propagation delays, and they are identical.
100m
25
i'
/
;; 10m
V
~
C>
ii:
'"'"z
:::>
1m
:3
~ 1001'
~
(al
~~
~
lOp
10k
~
20
C>
15
~
z
I:Ii'"
V-
:y
~
Of
C>
V
If
10
./
HCrO
5
0
lOOk
1M
10M
100M
OPERATING FREQUENCY (HzI
120
40
80
LOAD CAPACITANCE (pFI
160
TLIFI67516
TUF/6751·5
FIGURE 5_ Power Consumption of 74HCTOO Being
Driven by a) W,orst-Case TTL Levels b) Typical TTL Levels
c) CMOS Levels
FIGURE 6_ Typical Propagation Delay vs Load for
74HC240 and 74HCT240 Are Virtually the Same_ Slight
Differences Result from Different Design and Processing_
2-219
»
Z
~
CO
One interesting point is that HCT and HC speed specifications are measured differently. One can compare the AC
test waveforms in the HC databook and see that HC is
measured with OV-5V input waveforms and using 2.5V
points on these waveforms. HCT, on the other hand, is
tested like LS-TTL. HCr's input waveforms are OV':'3V and
timing is measured using the 1.3V on both the input and
the output waveforms.
The different test conditions for HCT result because HCT
will be primarily usd in LS-TTL applications. If HCT is used
in HC systems, the actual speeds will be slightly different,
but the differences will be small « 1 ns-2 ns).
HC and HCT speeds are not identical to LS-TTL. Some
delays will be faster and some slightly slower. This is due
to inherent differences in designing with CMOS versus
bipolar logic. For an average system implemented in HC or
LS-TTL, the same overall performance will result. On an individual part basis, some speeds will differ, so the
designer should not blindly assume that HC or HCT will
duplicate whatever a TTL IC does.
€MOS LATCH-UP AND ELECTROSTATIC DISCHARGE
'
OF 54HCT/74HCT
These two phenomena are not strictly performance
related in the same sense that speed or noise Immunity
are. Instead, latch-up and electrostatic discharge (ESD)
immunity impact the ease of design, insusceptibility to
spurious or transient signals causing a failure, and
general reliability of 54HCT/74HCT.
Latch-up is a phenomenon that is a traditional problem
with older CMOS families; however, as with 54HC/74HC,
latch-up has been eliminated in 54HCT/74HCT circuits. In
older CMOS, it is caused by forward biasing any protection diode on either an IC's input or output. If enough current flows through the diode (as low as 10 mAl, then it is
possible'to trigger a parasitic SCR (four layer diode) within
the IC that will cause the Vce and ground pins to short out.
Once shorted, the supply pins will remain so even after the
trigger source is removed, and can only be stopped by
removing power. Latch-up is described in much more
detail in National Semiconductor application note
AN-339, and, in particular, a set of performance criteria is
discussed.
.
By a combination of process' enhancements and some
careful IC layout techniques, the latch-up condition cannot occur in 54HC/74HC or 54HCTl74HCT.lf one attempts
to cause latch-up by forcing current into the protection
diodes, the IC will be overstressed in the same manner as
overstressing a TTL circuit.
ESD has also been a concern with CMOS ICs. Primarily for
historical reasons, MOS devices have always been considered to be sensitive to damage due to static discharges. However, process enhancements and careful input protection network design have actually improved
54HC/74HC and 54HCTl74HCT immunity to where it is actually better than bipolar logic. This includes 74ALS, 74LS,
74S, 74AS and 74F. ESD is measured using a standard
military 38510ESD test circuit, which zaps the test device.
by discharging a 100 pF capacitor through a 1.5 k{) resistor
into the test circuit. ESD test data is shown in National
Semiconductor reliability report, PR-11.
CONCLUSION
HCT is a unique sub-family deSignation of HC. It is intended primarily for TTL level to HC interfacing, although
it is far from restricted only to this application. HCT can be
used as a pin-for-pin socket replacement of TTL, or can be
mixed with HC logiC.
54HCTl74HCT has the same speeds as HC and LS, the
same noise immunity as TTL and a significantly lower
power consumption than LS-TTL, although it is slightly
greater than HC. Additionally, by providing latch-up immunity and low ESD sensitivity like the 54HC/74HC family,
the overall system reliability and integrit¥ is increased. All
of these performance parameters enable HCr's use in a
wide range of applications.
2-220
National Semiconductor
Application Note 371
David Stewart
August 1984
The M M58348/342/341 12481
242/24,1 Directly Drive
Vacuum Fluprescent (VF)
Displays
1. INTRODUCTION
National has produced a family of high voltage display
drivers which is specially designed for use with vacuum
fluorescent (VF) displays, These circuits are fabricated
using a standard metal gate CMOS process which has
been extended to allow a maximum operating voltage of
60V, thus enabling the design of bright multiplexed
displays. In this way, the advantages of CMOS are retained (low power), while the ran~e of applications lor this
technology is increased. Many of today's high voltage
MOS display drivers require the use of one external
resistor per display output, and this leads to a considerable increase in component count and board area.
National's display drivers, however, incorporate an on·
board pull·down resistor structure which removes these
disadvantages,
This application note is intended to demonstrate several
ways in which these display drivers can be configured to
drive and control a wide range of VF displays. Although
particular attention will be given to one specific display, a
32·character alphanumeric display, the design is pre·
sented in such a way as to enable easy extrapolation to
the system designer's specific application.
2. FUNCTIONAL DESCRIPTION
There are six circuits in this new family of high voltage VF
drivers and they can be sub-divided according to maxi·
mum operating voltage, number of display outputs, data
interfacing requirements and ability to be cascaded, Each
of the three circuit configurations is available with maxi·
mum operating voltages of 35V (MM583XX) or 60V
(MM582XX). Due to the nature of the output stage required
to attain high voltage operation of CMOS devices, the
drive capabilities of the display output decrease as maxi·
mum operating voltage increases. Therefore, to maintain
the option of trading off display voltage against drive cur·
rent, each circuit has a high voltage (reduced drive) version
and a low voltage (high drive) version, The three circuit
configurations can be identified by the number of display
outputs they contain (e,g., 20, 32 or 35 outputs). In all
cases, data is entered serially into a 5V internal CMOS
shift register, This data is latched to the output either by
an external enable control Signal (MM5824113411242/342)
or automatically by a leading start bit in the data stream
(MM5B248/34B), Figure 1 shows how ihe 6 device numbers
correspond to the different circuit configurations and
operating voltages.
The MM58348/248 devices use a two control line data input format (data in and clock) which enables the 40-pin
part to have 35 display outputs. To load data into the controller, a start bit precedes the 35 data bits. The start bit is
a logical "1" clocked into the IC by the first clock pulse.
Next, 35 data bits are clocked into these parts. The start
and data bits are shifted in on the rising edge of the clock,
As the data is clocked into the IC, the start bit is shifted
down the 35-bit register. On the riSing edge of the 36th
clock pulse, data is transferred to the display register and
the start bit is shifted into the control latch. On the
negative edge of the clock, the shift register is cleared.
The display register feeds the level shifters that translate
5V CMOS levels to the 35V-60V required by the display.
The MM58348/248 devices are not cascadable. Typically,
these devices would perform the segment refresh drive in
a multiplexed multi-digit system. A functional block dia- .
gram is shown in Figure 2.
The MM58341 1241/342/242 devices use a three control line
data input format (data in, clock and enable) and have
either 32 or 20 display outputs, as given by Figure .1. This
configuration sacrifices some outputs to enable cascading, enhance control signal flexibility, and provide brightness control. Here again, data is shifted into the shift register on the rising edge of clock, but no start bit is needed.
Instead, the enable Signal is taken high to input data tothe
chip, When the enable is taken low, the contents of the
shift register are loaded into the display register. Again,
the display register feeds the level translator and display
d~~~p~&
•
Each of the MM58241 1341 and MM58242/342 devices has
a serial data output pin which is connected directly to the
last stage's output of the shift register. By connecting
data out from one device to the data in pin of another
device, and by holding each circuit's enable constantly
high, the display drivers can be cascaded. The result is a
shift register with a variable number of bits, depending on
the mix of circuits used.
The MM58341/241/342/242 devices also have a blanking
control input. A logic high on this pin'turns all outputs off,
while still retaining the display data. If a logic "0" is then
applied, the display data will return unchanged. Consequently, the brightness of the display is proportional to the
duty cycle of this blank signal. A functional block diagram
of these devices is shown in Figure 3.
Operating Voltage
35V
BOV
Number
of
Outputs
20
32
35
MM5B342
MM58341
MM5B348
MM58242
MM5B241
MM58248
20 and 32 output drivers use envelope enable data format
and may be cascaded.
35 output (5 x 7 dot matrix) drivers use start bit data format.
FIGURE 1. The Complete VF Display Driver Family
2-221
•
..... r------------------------------------------------------------------------------------------,
~
~
Block Diagrams
«
OUTPUT
35
OUTPUT
1
...----4+-
ViliS
(-30V FOR
MM58348,
-55V FOR
MM58248)
OATA IN
CLOCK
5V
OV
TlIF/7394·2
FIGURE 2. MM583481248
OUTPUT
32* /20 t
OUTPUT
1
1+--f4f-- VOIS
(-30V FOR
MM58341/342,
-55V FOR
MM58241/242)
CLOCK-.........~
ENABLE - - - -......
5V
OV
TLIF11394·3
FIGURE 3. MM583411241* and MM583421242 t
2·222
.------------------------------------------------------------,~
Z
2. FUNCTIONAL DESCRIPTION (Cantinued)
Referring to. the functional block diagrams shown in
Figures 2 and 3, it is clear that all the internal logic is im·
plemented in standard 5V CMOS. Such signals do not pas·
sess sufficient drive for the high voltage aut put stage, so
the data passes through a bank af 15V level shifters to the
output section. A schematic of the output stage is shawn
in Figure 4.lt can be seen that all these display drivers use
a two·stage high valtage structure with active pull·up tran·
sistors and passive pull-down resistars to the display voltage. Because resistar pull-downs are used, it is the autput
switching "off" time which is critical for the system
deSign, and this is typically 20 I'S far a rail-to-rail voltage
SWing.
h:
h
- .....- - - - -.....LEVEL
SHIFTER
OUTPUT
--+1I
HIGH VOLTAGE
P-CHANNEL
TRANSISTORS
I
can then be displayed. Using these techniques necessitates that the display be continually refreshed with each
digit of data, even when that data has nat changed.
To see the advantage of multiplexing, if a 32 character
5 x 7 dot matrix display is used, a tatal of 1120 segments is
available. For this reason, the display is multiplexed and
has 32 grid inputs and 35 segment inputs. The required
refreshing task must be accomplished w,ithout the detection of flickering by the human eye, Le., at a rate greater
then 50 Hz. (Refresh timing is discussed later.)
Given the aforementioned display pinout and control
logic, it is desirable in multiplexed displays to use the
MM58341 to contro.l the display grids (digits) and one
MM58348 to control the display anodes (segments).
VDD=5V±0.5V
3.2. The Display-Driver Interface
When using the MM58XXX series, no buffering is required
between the driver output pins and the VF display. It is
necessary only that the driver charge and discharge the
display in such a time that the refresh rate outlined in the
previous section can be achieved. All the VF drivers have
LSTTL compatible inputs, and, as the data source is
generally a microprocessor, no special interface requirements exist.
~OISPLAY
r
r
OUTPUT
PULL·DDWN
RESISTORS
- ...- - - - -.....-
VDlS = -30V
OR VDlS= -55V
TLIF/73944
FIGURE 4. High Voltage Output Structure
3.3. The Microprocessor-Driver Interface
3. DESIGN CONSIDERATIONS
Typically, the system utilizing these display drivers will
have some sort of microprocessor or single chip computer
contralling the display. Thus, this processor will control
one or more of the display drivers. The drivers have relatively little intelligence, therefore the hast processor will
be in charge of updating the display drivers and generating refresh timing if needed. The advantage of having minimal intelligence on the drivers themselves is flexibility.
Virtually any display size or type' can be used with equal
ease, from small 7-segment, to British flag types, to larger
5x7,7x90r5x12displays.
3.1. The VF Display Configuration
The operatian of a VF display is merely an extension af the
valve principle, Le., it is a voltage contralled device. An AC
waveform is applied across the filament of the display,
and this excitation causes electrons to be emitted. If both
the grid and the anode are at a high positive voltage with
respect to the cathode, the electrons reach the anode
area, which is coated with a fluorescent material. When
bombarded by electrons, this material emits light, hence
one segment of the display is turned on.
The drivers can be directly interfaced to the microcontroller, COPSTM4XX, or 80C48/9. This would normally be
accomplished by connecting the driver's data and clock
lines to control ports on the micropracessor. The
MM58248/348 series is capable of accepting clack rates
up to. 1 MHz, and the MM58241/341 800 kHz. This is far
faster than the control port bit manipulation rates for
these controllers and will ensure compatibility with most
low end micraprocessors. 1 MHz input clock rates will also
ensure that the desired display refreshing rate is attained.
This particular family of display drivers can drive a wide
range of VF displays. The simplest case is where each display segment can be directly driven by wiring each output
to the display anode. This normally occurs on displays
with asmall number of digits and segments (e.g., 4 characters of 7 segments) and this can be driven by cascading
the drivers until sufficient data bits are available. This
display configuration has the advantage of not requiring
any refreSh (which would be required if a multiplexed configuration were used) but has the disadvantage of needing
one wire per segment.
.
In higher end systems using NSC800™ar6800 8-bit microprocessars, the 1 MHz clock rate, caupled with a 300 ns
minimum pulse width, simplifies direct interfacing of
these drivers to al'P bus. In the simple case, sO,me logic for
address decoding would set aside an I/O port for communication to. each driver, then several bits of the data bus
cauld be gated to create the clock, data and enable
signals.
As the size of the display increases, the number of available segments also rises, thus a multiplexing scheme
which will reduce the number of display connectians is
desirable. This is normally achieved by hard wiring all the
. segments (anodes) of each digit together, then using the
grids to select each digit in turn. The correct segment data
2-223
~
......
~ r---------------------------------------------~----------------------------------------------__,
l:;
4. TYPICAL DESIGN IMPLEMENTATION
4.2. A 32-Dlglt 5 x 7 Dot Matrix Application
nductor
Application Note 375
Larry Wakeman
September 1984
High-Speed-CMOS designs
address noise and
1/0 levels
To maximize the benefits of high-speed CMOS, you must cope
with environmental interactions and component limitations.
Especially important are system noise decoupling and
both transient and steady-state level control
Designs using high-speed-CMOS logiC, such as the
MM54HC174HC Series, can attain characteristics that mark
improvements over LS-TTL deSigns. To optimize these
characteristics, however, you must adopt proper design procedures. This article deals with the ICs' input-output and
noise-immunity considerations.
High-speed CMOS logiC is essentially a digital-IC family that
combines TTL (bipolar) and CD4000 (CMOS) characteristics. Because of the family's high speed, you must be more
aware of the reqUirements of fast systems than in the case
of CD4000B logic. Although the 54HC174HC IC's CMOS
construction results in noise immunity comparable to the
CD4000 family, its high speed necessitates system-grounding and supply-decoding. techniques normally used in LSTTL system deSign.
The following sections discuss general usage guidelines,
system noise susceptibility and immunity, and the 54HC/
74HC logic's power-supply-noise characteristics. Note that,
unless specific exceptions are stated, the considerations
discussed apply also to 54HCTI74HCT, HC's TTL-compatible subset.
Latch-up results if either the input- or output-protection diodes are forward biased because of voltages above Vee or
below ground. As a result, the IC's internal parasitic SCR
shorts Vee to ground Figure 1 shows the diodes in a CMOS
IC, schematically (a) and in a simplified die cross section
(b).
Thanks to some processing refinements, SCR latch-up isn't
a problem with the MM54HC174HC Series. There are, however, limitations on the currents that the internal metallization and protection diodes can handle, so for high-level transients (pulse widths less than 20 ms and inputs above Vee
or below ground), you must limit the current of the IC's internal diode to 20 mA rms, 100 mA peak. Usually, a simple
resistor configured in series with the input suffices.
Powering the device is another important design concern.
Don't power up inputs before both Vee and ground are con(a)
Vee
01
DIODE
FOLLOW BASIC GUIDELINES
The basic rules for designing with 54HC174HC circuits are
similar to those that apply to 74LS, CD4000B and 54C/74C
devices. First, under normal static operating conditions, the
input should not exceed Vee or go below ground. In normal
high-speed systems, transients and line ringing can cause
inputs to violate this rule momentarily, forCing the ICs to.
enter an SCR-Iatch-up mode.
Vee
INPUT DIODE DR
DurpUT DIFFUSION
DIFFUSEDDIOOE
RESISTOR
INPUT
POLVSILleOH
RESISTOR
02
{
03
~~~~:
05
OUTPUT
04
TLfFf8127-1
INPUT DIODE DR
OUTPUT DIFFUSION
Vee
GND
(b)
05
N- SUBSTRATE
TLfFf8127-2
FIGURE 1. Essential but sometimes eVil, the diodes in CMOS-logic ICs can be easily damage~ by excessive
currents. Reversed supplies or large Input or output currents can cause diode burnout.
Published in EDN Magazine
@Copyright 1984 Cahners Publishing
2·233
~,r-----------------------~-------------------------------------------------'
(a)
nected, and don't plug or unplug pc boards into or from
powered connectors unless input currents are short lived or
limited in the manner already described. Both conditions
can forward bias input diodes, resulting in excessive diode.
Vee
currents. Again, Figure 1 shows these diodes and the possible current paths. If these conditions are unavoidable, add
~N~I_.YoUT
external current limiting to prevent damage to 54HC17 4HC
circuits, or use special connectors that apply power before
50PF
signals. Some family members (notably the HC4049/50)
have modified input structures and can survive the applicaTlIF/8127-3
tion of power to the input before the supply.
(b)
Floating inputs are a frequently overlooked problem. CMOS
inputs have extremely high impedance and, if left open, can
float to any voltage. This situation can result in logic-func2V
50 ns
2V
tion mishaps and unnecessary power consumption. Moreover, open inputs are susceptible to electrostatic damage.
You should thus tie unused inputs to Vee or ground, either
through a resistor or directly.
~
Z
-+-_.....-1
FROM
REGULATED
POWER
SUPPLY
,
(CIRCUiTiOARD
C1
L
I
I
.J
I
L
- -
-
I
.J
TLlF/B127-29
TL/F/B127-2B
FIGURE 12. Tailor bypassing to the system's supply scheme. Circuit diagram (a) shows the method to
use with local regulators; (b) shows the scheme to adopt with a centralized regulated supply.
Use tantalum- or aluminum-electrolytic capacitors.
Before presenting the guidelines, examine some comparative attributes of earlier CMOS, HC, HCT and LS·TIL devices. First, because of higher speeds and larger output currents, the supply-bypassing requirements of HC devices are
more rigorous than those of earlier metal-gate-CMOS ICs.
Compared with those of LS-TIL, the requirements for
HC/HCT are similar or a little more stringent, depending on'
the application.
Furthermore, for random logic, 54HC174HC and
54LS174LS are similar, but in bus-driving applications HC
devices can produce larger spikes. Finally, HCT logic needs
better groun!iing than HC logic. In fact, its design considerations closely follow those of LS-TIL. However, as with HC,
HCT exhibits greater Vee spiking in bus-driving applications.
Now you're ready for the guideiines:
• Keep Vec-bus'routing short. When using double-sided or
multilayer circuit boards, use strip-line, transmission-line
or ground-plane techniques.
• Keep ground lines short, and on pc boards make them as
wide as pOSSible, even if trace width varies. Use separate
ground traces to supply high-current devices such as relay and transmission-line drivers.
• In systems mixing linear and logic functions and where
supply noise is critical,to the analog components' performance, provide separate supply buses or even separate supplies.
2·241
• If you use local regulators, bypass their inputs with a tantalum capacitor of at least 1 ",F (Figure 12a), and bypass
their outputs with a 10- to 50-",F tantalum- or alumiumelectrolytiC capacitor (b).
• If the system uses a centralized regulated power supply,
use a 10- to 20-",F tantalum-electrolytic capacitor or a
50- to 100-",F aluminum-electrolytic capacitor to decouple the Vce bus connected to the circuit board (Figure
12b).
• Provide localized decoupling., For random logic, a rule of
thumb dictates approximately 10 nF (spaced within 12
cm) per every two to five packages, and 100 nF for every
10 packages. You can group these capaCitances, but it's
more effective to distribute them among the ICs. If the
deSign has a fair amount of synchronous logic with outputs that tend to switch simultaneously, additional decoupiing might be advisable. Octal flip flops and buffers in
bus-oriented circuits might also require more decoupling.
Note that wire-wrapped circuits can require more decoupiing than ground-plane or multilayer pc boards.
• For circuits that drive transmission lines or large capacitive loads (",P buses, for example), use a 10 nF ceramic
capacitor close to the devices' supply pins.'
• Finally, terminate transmission-line ~rounds near the
drivers.
z~
National Semiconductor
Application Note 376
Larry Wakeman
October 1984
Logic-System Design
« Techniques Reduce
SWitching-CMOS Power
By adopting cfJrtain techniques in the design ofyour CMOS-based logic system,
you can effect dramatic reductions in the transitional power these
zero-qUiescent-current devices consume when switching.
This article describes ways to reduce the power consumption in logic designs using high-speed CMOS ICs. The
MM54HC174HC logic family has near-zero power dissipation when in the quiescent mode. Its only substantial power
drain arises from dynamic switching currents. Traditional
TTL and NMOS systems do not share this low-power feature, requiring instead that you reduce power by selecting
low-power ICs and external components.
The CMOS device is inherently efficient, but you can greatly
enhance system efficiency by designing around the follow, ing guidelines:
• minimizing effective system operating frequency;
• minimizing static dc-current paths (eg, in pull-up or -down
resistors);
• putting the logic to sleep (by removing the clock);
• capitalizing on power-down situations.
Total system power dissipation is the sum of two components: static (or quiescent) and dynamic power. LS TTL systems consume such a great amount of quiescent power that
the dynamic component pales into insignificance. When using 54HC174HC logic in power-critical applications, however, you must consider both components. The following sections describe how to determine system power by using HC
devices' power:dissipation-capacitance (Cpo) specs. The
text also discusses a few power-reduction philosophies and
some of the differences in consumption for 54HCT/74HCT
TTL-compatible CMOS logic. Because system power is simply total Icc times the supply voltage, the calculations treat
power and current interchangeably.
Calculating the quiescent power is just as easy-the sum of
the dc currents times the supply voltage. Thus, total system
The currents in this expression are caused by pull-up and
load resistors and TTL, NMOS and line!!r circuits in the system. If it's appreciable-although unlikely-you can include
the very small quiescent Icc of MM54HC174HC'devices.
Generally, the worst-case Icc values in the CMOS ICs' data
sheets are very conservative. Typical values range from ten
to 100 times less than the limits; moreover, it's almost statistically impossible for a system to contain all worst-case
devices.
As pOinted out earlier, the major contributors to CMOS ICs'
power dissipation are dynamic switching currents. Figure 1
is a schematic diagram of one 74HCOO NAND gate, and it
shows the dynamic currents that result from switching one
input Low to High. When the IC is not switching, there's no
dc-current path from Vcc to ground except for leakage. This
is because whenever an n-channel device'is On, its,complementary p-channel partner is Off.
CMOS power consumption is caused by the transient currents that charge and discharge internal and external capacitances during logic transitions. As frequency increases,
these currents naturally increase. You can't measure these
currents or their associated capacitances individually, but
you can measure the total current. You can equate this total
current to a power-dissipation capacitance (CPO) as follows:
+
Icc = (CPO
CU(VCC)(fIC),
(2)
where Icc is the supply current, Vee is the supply voltage,
flC is the input toggle rate and CL is the toggled load capacitance. Referring ~gain to Figure 1, the load current IL results
from switching the load capacitance. To obtain the internal
equivalent capacitance, you must subtract the load current
•
from Icc.
quiescent power is
PSYSTEM = (ICc'1
+ ICC2 + ... ICCn) Vcc.
(1)
Vee
....- ....--t-H--:--t---~- VOUT
t-t-~
V,. --+-----4~_I
TLlF/8128-1
FIGURE 1. Principal contributors to CMOS power consumption, these transient currents are the result
of transitional charging and discharging of Internal and load capacitances. The average currents are
naturally a function of the operating frequency. '
Published in EON Magazine @ Copyrlgh11984 Cahners Publishing Co.
2·242
Using the CpO figure spec'd in data sheets, you can estimate the current consumption of each device in your system if you know the toggling frequency. By multiplying both
sides of Equation 2 'bY'Vee, you can determine the dynamic
power consumption.
consumption), you might do well to characterize CPO for
your particular application.
The nearby Figure 2 shows a circuit for measuring Cpo.
Normally, the IC is set up in a given toggling mode, with ·its
output pins pulled out of the test socket to reduce stray-induced errors. For automated testing, you could use a standard load (eg, 50 pF) and subtract its Icc contribution from
the total. The ammeter in series with the Vee line is bypassed with 0.1- and 1-fLF capacitors.
POYNAMle = (CPO + CLl(Vee2 )(f).
(3)
As mentioned, Cpo is an indirect measure of the amount of
switching current a circuit consumes. It depends on how
much of the circuit's internal logic is switching and. how
many outputs are toggling. For example, a 74HC374 octal 3state flip flop clocked at 1 MHz disSipates much more power
if its data inputs change every clock period than it would if
its outputs are disabled and its inputs are tied High or Low
during clocking.
.
For simple measurements, you can set the input's toggle
frequency at 200 kHz, with Vee=5V. This yields an ammeter re.ading in microamps. that's equal to CPO in picofarads.
You ·could use other voltages and frequencies, but little variation should result. For example, JEDEC's high-speedCMOS committee recommends 1 MHz.
Figure 3 shows that when the flip flop's outputs are enabled
and the data inputs are changing, virtually all internal nodes
are toggling and all internal parasitic capacitances are
charging. On the other hand, if the data is held High and the
outputs are disabled, only the clock logic dissipates power
(and very little at that). All other sections are static.
To better understand what datasheet CPO means, the following listing describes by part type how each IC is toggled.
In measuring CPO, the worst path is always chosen. Moreover, within the constraints listed, as much of the internal
.circuitry and as many of the outputs as possible are toggled
simultaneously.
As you'll see, the method of testing CPO (see "Test Cpo in
realistic situations") can yield various values that might or
might not be applicable to the particular way the part is being used. Fortunately, several generalizations allow reasonable approximations to CPO's value, as discussed in the following section.
• Gates: All inputs except one are held at either Vee or
ground, depending on which state causes the output to
toggle. Toe one remaining input is toggled at a. given
frequency. CPO is given on a per-gate basis..
• Decoders: One input is toggled, thereby causing the outputs to toggle at the same rate. Normally, one of the
address-select pins is switched whil~ the decoder is enabled. All other inputs are tied to Vee or ground, whichever enables operation. CPO is expressed on a per - independent - decoder basis.
TEST CPO IN REALISTIC SITUATIONS
In 54HC174HC data sheets, one or two Cpo values are
specified. At best, the parameter is a simplification of the
worst-case operating mode of a device under typical operating conditions. However, because most devices have several possible toggling modes (each having a different power
-!.J:.
I
o
POWER
AMMETER
SUPPLY
PULSE
GENERATOR
(NOTE I)
I J'L
I
Vee
INPUT(SI
TEST Ie OUTPUT(S)
(HOTE3)- INPUT(S)
GND
*
t-....- - (NOTE 2)
t·
TLlF/8128-2
Noles: 1. OUTPUT = square wave with,,; 6-nsec rise and fall times; levels = GNO and Vee.
2. Bend all output pins from test socket, or US~ known load and deduct its current from measured Icc.
3. Terminate all unused inputs to GNO or Vee.
FIGURE 2. Measure equivalent CMOS-system capacitance with this simple test circuit. The text describes how to toggle
the various CMOS logic functions (excepting one-shots, of course, which draw dc powe~).
2-243
•
• Multiplexers: One data input is tied high, and a second
is tied low. The address-select lines and enable inputs
are configured such that by toggling one address line the
two data inputs are alternately selected, causing the outputs to toggle. If it's a 3-state MUX, CpO is given for
outputs both enabled and disabled. Cpo is measured per
multiplexer function.
100 mW rTnm,.-,rTTTlllr-TTT....."T'T.....
10mW
lmW
• 3-state buffers and transceivers: When the outputs
are enabled, CPO is measured as for simple gates; ie, on
a per:buffer basis. The same holds true for the 3-state
condition. Transceivers are measured per buffer as well,
both enabled and disabled.
lpW
10 kHz 100 kHz 1 MHz
• I.8tches: The device is clocked and data is toggled every
other clock pulse. Other preset or clear inputs are held to
enable output toggling. If the device has commonly
clocked latches, the clock is toggled and one latch is
exercised. 3-state latches are measured with their outpUfs both enabled and disabled. Cpc is given on a perlatch basis.
.
10 MHz 100 MHz
TLIFIB12B-3
FIGURE 3. Output status determines dynamic
dissipation In this 3-state-output flip flop. The IC
dissipates an order-of-magnltude higher power
with Its outputs enabled.
The most accurate approach, however, is to determine each
component's operating frequency and its capacitive load.
This method is used in critical battery powered applications.
The following section describes this approach and proposes
simplifications. In this approach, system dynamic power is
the sum of the individual circuits' power dissipation:
• Flip flops: The same as for latches. The device's inputs
are configured to toggle, and any preset or clear inputs
are held inactive.
• Shift registers: The register is clocked and the serial
data input is toggled every other clock pulse, as for latches and flip flops. Other clear or load pins are held inactive, and parallel data inputs are held at Vcc or ground.
3-state devices are measured with outputs both enabled
and disabled. If the device takes parallel loads only, it's
loaded with 10101010... and clocked to shift the data out,
then reloaded.
Pr = Pl + P2 + P3 + P4 + ... etc,
(4)
where Pr is the total power and Pn is the power for each
component. By substituting Equation 3 into Equation 4, the
total system power is
Pr = (CPl + CL1)(Vcc2)(f) +
(CP2
+ CL2)(Vcc2)(f) + ... etc..
(5)
.0
Counters: A signal is applied to its clock input; other
clear or load inputs are held inactive. CpO is given. for
each counter within a package.
• Arithmetic circuits: adders, magnitude comparators,
encoders, parity generators, ALUs and other miscellaneous circuits. The general rule is to exercise these parts to
obtain the maximum number of outputs toggling simultaneously while toggling only one or two inputs.
In Equation 5, load capacitances CL1, CL2, etc are not simply the sum of all individual output loads. CL is actually dependent on device type. Why? Different devices switch a
different number of outputs simultaneously. What's more,
these outputs can toggle at a different rate from that of the
IC's clock or input. Thus, for an individual IC and its load, the
actual power is
PIC = Vcc2 [(Cpof) + (CL1fL1) + (CL2fL2) + ... J. (6)
• Display drivers: CPO is generally not required for LED
drivers, because the LEOs use so much more power they
overshadow the drivers' CPO; moreover; when blanked
the drivers are rarely driven at any significant speed. If
needed, however, Cpo is measured with outputs enabled
and disabled, while toggling between a lamp test and
blank (if provided), or between a display of numbers 6
and 7. LCD drivers are tested by toggl!ng their phase
inputs, which control the segment and backplane waveforms: If either of these driver types has latched inputs,
the latches are set to a flow-through mode.
where CL is the load on each of the simultaneously toggling
outputs, and fL is the toggle rate seen by the load. A good
example is the power dissipation of a 4-bit CMOS counter.
Here there are four output terms-each output switches at a
different frequency. Accordingly, there are four (each) distinct CL and fL terms. To simplify Equation 6, ·define an
effective load capaCitance CLE which is the actual load multiplied by the ratio of the load toggle rate to the IC's toggle
frequency:
(7)
Substituting Equation 7 into Equation 6 and grouping
terms,
PIC = Vcc2 f(Cpo + CLEl + CLE2 + ... ).
(6)
• One-shots: In some cases, when a device's Icc is significant, CPO might not be specified. When it is, CpO is tested by toggling one trigger input such that the output is a
square wave. The timing resistor is tied to a separate
Vcc line, to eliminate its power contribution.
This procedure simplifies the process because output toggle rates are almost exclusively a binary division of the input
clock. Thus, for an accurate calculation of system power,
you must calculate it for each IC using Equation 8 and take
the total. The counter is a prime candidate for using Equation 8. Here, the first stage's effective output capacitance is
half the actual; the second, one-quarter, and so on.
FIGURING DYNAMIC SYSTEM POWER
How do you calculate a system's dynamic power? You can
do it on several levels, depending on the accuracy needed.
The simplest approach is to use a CPO model that's the sum
of the CMOS ICs' Cpos and the load capacitances. Then,
assuming an average frequency, plug these numbers into
Equation 2 or Equation 3.
2·244
TAILOR f, C TO DEVICE TYPE
To make practical use of the foregoing methods, the following list describes most of the, CMOS-logic categories in
terms of effective load and operating frequency:
• Gates and buffers: Power calculations for these are
straightforward. CPO, given for each gate, sums directly
with its output load. Operating frequency is the rate at
which the output toggles. For disabled 3-state buffers,
the power calculation uses the 3-state-output CPO mUltiplied by the input frequency (no load capacitance included.)
These rules notwithstanding, it's rarely necessary to go
through a detailed analysis of each IC. In most instances, a
simpler analysis can yield good results. In noncritical appli• cations where power consumption is used to determine the
system's power-supply needs, the simpler analysis suffices.
U!ijng this method, you estimate the average operating frequency for major sections of the ,system. Next, sum all the
CPos and effective loads in each section:
PBLOCK = vcc2 fAI(G [(CPl + CLE1) +
(CP2 + CLE2) + ... + (CPn + CLEn)]. (9)
Thus, to approximate the total system's power consumption, you must approximate the effective loads for each
group of devices (or the entire system) and add them together:
• Decoders: Each independent decoder can toggle no
more than two outputs at a time. To calcl!late power consumption, sum Cpo with Jhe load on two outputs. The
frequency is the rate at which the outputs switch.
• Multiplexers: For non-3-state devices, sum the loads on
all used outputs and add the sum to CPO. The frequency
is that at which the outputs switch. For 3-state devices,
use only Cpo; the frequency is the inputs' toggle rate.
Consider a microprocessor-based system using an 8 MHz
clock frequency. In this example, you might determine that
the bus operates at approximately 2 MHz, random control
logic at 4 MHz, and the RAM and 110 devices at 100 kHz.
You could estimate an overall system clock to be 1 to
2 MHz, depending on the actual size of each block. Next,
you'd sum the CPO and the effective load capacitancessay 2000 and 1000 pF, respectively. The ballpark estimate
for system power is
P = (5)2 (1 MHz)(2000 pF + 1000 pF) = 75 mW. (10)
• Counters: The operating frequency for each of a counter's outputs is that of the previous stage divided by two.
The loads on lower order stages contribute less current.
So to calculate power, sum Cpo with one-halt the first
stage's load plus one-quarter the second stage's, and so
on. For decade and other modulo counters, this procedure is slightly different. In general, you can neglect outputs more than four stages removed from the clock. A
simple approximation is to sum CPO with the average
output load and use the input clock frequency.
Exceptions to the above rules are one-shot ICs and gates
configured as oscillators, which use CMOS in an essentially
linear manner. Their power consumption is not strictly attributable to negligible quiescent currents or dynamic switching
currents.
• Latches, flip flops and shift registers: For these devices, the frequency is the ICs' clock rate. The outputs typically change state at half the clock rate, so when calculating power dissipation, add Cpo to halt the output load.
It the data inputs change more slo~ly, you can modify
the effective load downward by the ratio of the data rate
to the clock rate. Again, if the outputs are disabled, no
load dissipation exits and you should use the 3-state
CPO·
Consider one-shots, some of which draw dc current continuously, some only when the output pulse is triggered (check
data sheets for the device type you're using). The culprits
are the ICs' internal linear CMOS comparators that use dc
bias circuits. HC one-shots use several deSign approaches.
One (the 'HC123A1221A1423A) uses a comparator that
shuts off after a pulse times out; the second (the 'HC4538)
leaves the comparators on at all times.
74HCD4
(a)
(b)
Rl
-f>~H~CD'C4_ _....
-fa
Xl
--C2 1C1
T -:
(c)
R2
TLlF/B12B-4
(d)
FIGURE 4. Drawing higher-than-calculated power, these CMOS oscillator configurations suffer
from "soft" logic levels at their gates' inputs. Circuits (a) through (d) are 3-inverter,
2-lnverter, Schmitt-trigger and crystal oscillators, respectively.
2-245
~r---~------------------------------------------------------------------.....
CO)
A one-shot's overall power consumption is its quiescent
MORE SPECIAL CASES: HCT
Z power plus the power consumed by its timing elements and
Because of their unique applications in TTL and NMOS sys-
«
Cpo. If the comparators turn off, you multiply the quiescent
current by the duty cycle of the output pulse. Thus, the overall expression for one-shot power consumption is'
Pos=(lcc)(Vcc)(O) + (CEXT + CL + CPo)(Vcc2)(f), -{11)
tems, 54HCT/74HCT devices have some additional traits
that you should consider in designing systems. In TTL systems, the HCT ICs' inputs are driven under worst-case conditions by TTL levels of 0.5 and 2.4V. With these input levels
applied, HCT consumes significant quiescent current: about
200 to 500 p.A per input. You must consider this dc current
when calculating power.
where Pos is the total power, 0 the one-shot's duty cycle,
CEXT the timing capacitor, CL the load on both outputs, and
f the operating frequency. In general, the CPO. term is small
at lower frequencies; you can safely set it to zero to simplify
the equation.
To see the origiRs,of this quiescent current, refer to Figure
6, which shows a typical HCT's input. With a 2.4V input
level, the n-channel transistor turns fully on; the p-channel
device turns slightly on. This scenario results in a quiescent
current dependent on the number of logic-One inputs applied. The 0.5V level is close enough to ground to cause the
n-channel transistor to turn off, so HCT ICs draw quiescent
current only when its inputs are at a high state.
What about oscillators? The circuits shown in Figure 4 draw
more current at a given operating frequency than you'd calculate using only Cpo. This is because in these applications,
the inputs to some of the gates are at "soft" logic levels for •
significant amounts of time. This causes both p: and nchannel transistors to conduct simultaneously and hence
draw dc current.
The IcC values with these logic levels are specified in the
HCT data sheets. It's specified on a per-input basis-this
allows you some flexibility in determining quiescent power
when an IC is driven by both CMOS and TTL. The specified
quiescent-current value results in calculated Icc values of
several milliamps per IC, Significantly less than that of LS
TTL circuits.
Figure 5a plots current vs input voltage for the 74HCOO gate
and gives an idea of the amount of current typically drawn
when soft logic levels are applied. The large spike at 2.3V is
the result of the output's switching. At low frequencies, the
oscillator's supply' current can be several milliamps higher
than you might expect because of the amount of dc current
drawn.
Note, however, that 'using this data-sheet approach yields
current values roughly five times higher than that actually
seen in system designs. The reason for this is that the Icc
test is spec'd at VCC=5.5V and VIN=2.4V, but even worstcase TTL output-High levels are at least 3.4V under these
conditions. Output levels can only attain a low 2.4V with
Vcc=4.5V. Moreover, both TTL and NMOS outputs typically assume levels closer to 3V (at Vcc=4.5V), lowering quiescent current more. The point is, don't let Icc specs scare
you into thinking CMOS is a power hog.
The same is true of a 74HC14 used as an oscillator. Figure
5b shows the supply current vs input voltage for the
74HC14 and the 74C14 (or C040106). Because the actual
power consumed vaires with frequency and component values, it's best to determine it empirically. As with the oneshots, the oscillator timing capacitor's contribution to power
dissipation can be expressed by P = VcdCt)f.
MM54HC/74HC logic uses bigger devices and lower transistor thresholds than metal-gate CMOS,' so it might be
more desirable to use either C04000 or MM54C174C logic
for lower power oscillators (if operating frequency and output-drive requirements permit.) .
60
!
50
t5
40
'"
B
30
'"
Vee =5V
OUTPUT
74COO
IN~UT
I'
i.-'I
r-I-
~U~n
INPlJT
Ir-r-
I'~
It
74HC14
74C14
I~
rl
IJ'I
?:;
20
8:
::0
'"
. 10
o
I,.oo~
o
~
~I\.
...
1.0
2.0
3.0
4.0
INPUT VOLTAGE (VI
Ir;e~
lee
I..'
5.0
TIME
TIME
TLlF/8128-5
(a)
(b)
(c)
FIGURE 5. "Soft" logic levels cause high currents In a 74HCOO inverter (a) and a 74HC14 connected as an oscillator
(b,c). Because the power varies with frequency and component values, it's best to determine its value empirically.
2·246
r------------------------------------------------------------.~
Z
In mixed TTL-CMOS applications, the calculation of power
consumed by the HCT logic must take into account both the
dynamic and the quiescent currents. The dynamic portion is
the same as that for HC logic-in fact, CPO is measured with
and 5V input levels to exclude any quiescent current. The
static portion is the sum of the number of TTL logic-One
inputs times their High-period duty cycle times the current
per input. For a single IC, the power consumption is
Vee
o
P,C
= (Vee)(icc)(N)(D)
INPUT~
TO INTERNAL
lOGIC
,~
+ Vcc2 f(Cpo + CLE),
(12)
where CLE is defined as before, N is the number of TTL-driven inputs and 0 is the logic-High duty cycle.
I
..J
L_
Icc is the data sheet's per-input spec. This expression can
then be one term in Equation 4. If you're using the package-level quiescent current, the terms Nand 0 drop out.
What about a situation in which HC drives HCT? In this scenario, ground and Vee levels are applied, thereby ensuring
that the po and n-channel transistors don't turn on simultaneously. You can thus determine HCT power dissipation just
as for HC by using CPO.
"N-....- ...
..,
(iiCT-
GND
TLlF/8128-6
FIGURE 6. TTL-compatible CMOS is a special case. This
schematic shows the 54HCT174HCT family's input
buffer. With a 2.4V input applied, the n-channel
transistor is fully On; the p-channel, slightly On.
"N
+ BYB
lOGIC
SUBSYSTEM SECTIONS
SUBSYSTEM SECTIONS
TLlF/8128-7
(a)
(b)
FIGURE 7. Reducing clock rate-but not throughput-this scheme allows you to reduce power by clocking a system's
n subsections only as fast as needed, instead of clocking all system blocks at the full clock frequency
2-247
~
NOW LET'S REDUCE POWER
When designing low-power CMOS systems, there are several ways to minimize power. These methods involve reducing operating frequencies, cutting system load capacitances, using fast input transition times and minimizing any dccurrent paths.
First, for low-power system implementations, it's important
not to overdesign the operating frequency. Very simply put,
it makes no sense to clock a counter at 20 MHz when 5
MHz will suffice.
ed. Figure 9 sf:lows the logic used to implement this scheme
for a CMOS /-lop system. In this method, there are two oscillators, either ~f which can feed a divide-by-two circuit that
provides a square-wave output. The flip flop's output is the
system clock. The system's /-lop can set or reset 'the flip flop
so that it can operate at either frequency.
Besides frequency reduction, there are several other methods to save power, including reducing load capacitances.
You can accomplish this by reducing wiring capacitance (especially in high-frequency sections) through good layout
practices, and by maintaining close proximity between interrelated high-frequency sections. In some instances where
you might instinctively parallel several unused inputs, you
can achieve lower load capacitance' by tying the unused
inputs to a supply. In another example, when using RC oscillators, it's best to use the smallest capacitor and the largest
resistor possible.
Note that a reduction in overall system .clock frequency
doesn't necessarily entail a reduction in throughput. For ex·
ample, consider a system consisting of four subsections,
clocked at 8 MHz (Figure 1a). Rather than clocking all sections in parallel, you can reduce power by clocking each
section only as fast as need be (Figure 1b). A second example of reducing the overall system clock rate is shown in
Figure 8.
Slow input transitions can cause extra dissipation. If an input
Signal rises slowly, it causes both input transistors to conduct for a longer time, thereby causing more current to flow.
One rule of thumb is if rise and fall times are shorter than 25
nsec, minimal current will flow. But don't go overboard. Be
aware that slow transitions are more tolerable in slower operating sections because the transitions occur less often.
Therefore, weigh the importance of the !3xtra dissipation
against the cost of speeding signals up.
In (a), a CMOS memory array is driven directly from the
CPU's address bus. Here, every memory is driven at the bus
frequency. If, however, the address is latched by each memory block only when that block is being accessed (b), then
only the block currently being accessed is clocked. This is
why some CMOS RAMs incorporate on-chip address latches.
Another way to operate a system at the minimum possible
,frequency is t6 switch the system clock. The system is thus
made to .operate at the highest frequency only when need-
It's important to point out that floating inputs can result in
unnecessary power dissipation. If inputs are open, the input
4.PAGE
4·PAGE
MEMORY
ARRAY
MEMORY
ARRAY
DATA BUS
DATA BUS
TL/F/B12B-B
(a)
(b)
FIGURE 8. latching memories' addresses (b) can reduce system power. In (a), every memory Is driven at the bus
frequency. By contrast, In (b)'s configuration, only the memory block being addresed Is clocked.
2·248
10M
,P
74C04
OSCILLATOR
1/274HC74
20Dk
n
~20PF
FROM ,p
DATA BUS DO
1/274HC74
CK
PO
l~"
ADDRESS BUS
2k
P7
74HC688
I'=lI
DO
t·~~
TO Vee OR GNO
FOR ADDRESS
SELECTION
07
~60PF
ENABLE
,pWII
TLlF/B12B-9
FIGURE 9. Switch your system's clock frequency for reduced power consumption. The circuit
shown is a software-selectable oscillator for a microprocessor system.
voltage can float to an indeterminate and intermediate level;
thus, don't float CMOS Inputs. This action can turn on both
p- and n-channel transistors, resulting in supply-current
drain. In bus-oriented systems, don't allow the bus to become completely 3-stated or float for extended periods because this will have the same effect as leaving inputs open.
P~-----~------,
AD'
Bus structures subject to prolonged 3-state conditions
should be terminated to ensure that the bus lines pull to
either Vee or ground. For short durations, the bus capacitance can maintain valid logic levels, so for short-time floating, pull-up or -down resistors might not be necessary.
Finally, make sure your design ensures solid Vee and
ground logic levels at 54HC174HC inputs. If the logic Low is
greater than O.5V or the logic High is lower than Vee-O.5V,
then the normally Off p- or n-channel transistor can actually
conduct slightly, causing additional lee to flow (similarly to
the previously discussed HCT "soft" levels).
-----+-.....-ot
AD6
AD5
-----+-.....-ot~>_-+....
AD' AD3
BE WARY OF STATIC LOADS
Previous sections discussed the effects of capacitive loads
on system power dissipation. What about resistive loads? In'
ultra-low-power systems, their contribution can be significant, so it's important to find ways to eliminate or minimize
their detrimental effects. The loads could be pull-up resistors, bus terminators, displays, relays or peripheral drivers.
Of course, the most obvious way to reduce power is to select low-power relays or displays, for example, and to make
resistor values as high as possible. In addition, you can
switch these loads out of the circuit when not needed.
Figure 10 shows a circuit that dissipates no static power;
you can use it to terminate a 3-state bus to the last active
logic level seen on the bus. This technique is useful to ensure the bus doesn't float when 3-stated. The circuit uses a
74HC244 whose input is tied to its output. If the terminating
resistors must be completely turned off, use the 3-state Enable.
-ll>-+-'
.....
-----+-.....-ot:>_-+.J
AD'
_ot
A D 1 - - - - - + -.....
ADO
MM74HC244
TLlF/B12B-10
100 n < R < 200k
FIGURE 10. Dissipating zero static power, this scheme
can serve to terminate a 3-state bus to the last active
logic level seen on the bus. To disconnect the
terminating resistors, use the 3-state Enable command.
2-249
Figure 11 illustrates a method of controlling a series of pullup resistors using the output of an HC gate or 3-state buffer.
Because HC outputs can pull up to Vee, you can use them
as an enable for many pull-ups, as long as the parallel combination of the pull-up resistors exceecls 2 kn. You can also
use the method for pull-down resistors.
R1
R2
R3
When considering whether you should add circuitry to disable pull-up resistors, remember that in CMOS systems, the
pull-ups only dissipate power when the driving output is low.
No power is consumed when the driving output is high or at
the 3-State level (disabled).
THE FINAL SOLUTION: POWER DOWN
When all else fails, the best way to reduce system power is
to shut off the system or unnecessary parts. Before you do
this, keep in mind that turning off the clock to a section of
the system is almost tantamount to turning the section off
(thanks to the ICs' low leakage currents). The advantage of
the clock-killing approach? It avoids the complications of
the power-down methods that follow.
Still, there are occasions in which parts of a system are
powered down. When all or part of a system is shut off, or
when one of several interconnected systems is powered
down, you should respect several criteria to avoid spurious
signals during the power-down period, and.to eliminate possibly fatal conditions.
One condition that requires very careful consideration is the
application of high-level Signals to unpowered HC devices.
Figure 12a shows in block form the basic concepts of powering down part of a system. In this scenario, it's possible to
apply a logic One to the unpowered CMOS logic. If this
happens to either an input (b) or a 3-state output (c). the
device will still be powered.
R4
(~i;) ~ 2:0
- - - - - -...........
TUF/8128-11
FIGURE 11. Enable or disable pull-up resistors with this
configuration. You can use an HC device's outputs to
enable several pull-ups. The scheme Is also applicable
to pull-down resistors.
MAIN _
SUPPlY-
UNPOWEREO
SUBSYSTEM
(a)
Vee=4.3V
":"
TO UNPOWERED •
Vee LINE AND
OTHER COMPONENTS
r-
~H
TO UNPOWERED
Vee LINE AND
OTHER COMPONENTS
VrN=5V
POWERED INPUT
rTO SYSTEM
GROUND
TYPICAL CMOS INPUT STAGE
TO SYSTEM
GROUND
TYPICAL CMOS OUTPIIT STAGE
TL/F/8128-12
(b)
(C)
FIGURE 12. This-basic power-up and -down system (a) presents dangers to CMOS-logic ICs. As the
Input (b) and output (c) schematics show, a logic One can actually power up the "unpowered" system,
thereby causing damage to Input and output diodes.
2·250
:: POWER-CONTROL
LOGIC
BACK-UP
SUPPLY
---
I
Vee
-_'- MAIN
SUPPLY
Vee
, OUTPUTS {
POWERED
SYSTEMS
R2
Vee
I
R1
BACK-UP _
SUPPLY - -
_ MAIN
- - SUPPLY
} INPUTS
POWEREDDOWN
SYSTEM
Vee
..... {
POWERED
SYSTEMS
.".
.".
(a)
(c)
}
INPUTS
POWEREDDOWN
SYSTEM
74HC244
I\)
'"
POWE~O~~~TROL
~
Vee
BACK-UP~
SUPPLY
-=-
~MAIN
-=-
SUPPLY
,"~,,(
POWERED
SYSTEMS
.".
(b)
1----------,
Vee
}"...
POWEREODOWN
SYSTEM
+
BACK-UP
SUPPLY--
+
MAIN
-SUPPLY
Vee
oo~,,{
POWERED
SYSTEMS
Vee
}..
"
POWEREDDOWN
SYSTEM
.".
(d)
TL/F/B12B-13
FIGURE 13. Solutions to the problems In Figure 12, these configurations protect CMOS circuits' inputs and outputs In power-down situations.
,The brute-force solution in (a) limits Input currents; (b)'s scheme forces Inputs to ground; in (c), 3-state gates disable the inputs.
In (d), 74HC4049 or -4050 level translators isolate inputs from the power supply.
9l£-NV
Je
('I)
Z
CC
.Referring again to Figures 12b and 12c, the input protection
diodes and the output parasitic diodes form a path to the
Vee pin. The voltage at this pin will pe VIN-0.7V. The "unpowered" system is really powered up by the logic signal
through these diodes. If the "unpowered" Vee line accepts
appreciable current, diode damage can (and usually does)
result.
Figure 13 shows several solutions to the signal-powered
"unpowered" problem. A resistor in series with each input
(a) limits the current to 20 mA max. This low-cost, bruteforce solution has the undesirable tendency, however, to
dissipate power from the supply.
To avoid extra power consumption, you can use the methods in Figures 13b to 13d. Upon removal of power, additional logic can force all inputs to ground (b). Altematively, 3state logic can disable the signals by presenting an open
circuit (c). The third possible solution (d) is to use a
74HC4049.or 74HC4050-drcuits that lack a Vee diode. In
this case, even when power is removed the inputs' are isolated from the power supply.
A situation analogous to the previous section's might occur
on bidirectional buses or in "party-line" media, where 3state output devices are powered down on the bus. In this
case, power down all but the 3-state buffer, as shown in
Figure 14. Because the buffers inputs are shut off, the IC
draws negligible extra power.
In addition to ensuring that power-down proceeds smoothly,
iI's important to guarantee that spurious Signals from the
subsystem that's shutting down do not cause logic errors in
the powered section. For example, battery-backed memory
• must be controlled to prevent spurious writes by the host
processor that's shutting off.
Rgure 15 Illustrates a method for eliminating spurious operation upon loss of power. First, the system detects the loss
of system power prior to the system's malfunction by comparing the system voltage to an arbitrary minimum voltage
(V21, or by directly monitoring the ac line for loss of 50 or 60
Hz. Having detected this loss, the system should perform all
IPiiWEREiiBuSiiiiIVER
-,
bookkeeping operations to prepare for power-down before
the minimum correct operating voltage (Va) is attained.
At Va, the system cannot be guaranteed to function correctly-therefore, powered logic should disable all Signals that
might affect the powered or battery-backed subsystem.
Once stable power is restored to the minimum operating
voltage (V4), the signals should be re-enabled.
Clearly, there is more to shutting off a system (while leaving
part of it powered by a backup battery) than just switching
the power supplies. The primordial design consideration
when powering down a system is to ensure that spurious
Signals do not destroy valuable data or logic conditions in
the battery-operated subsystem.
CD
VI
w
.
V2
~
V4
>
E V3
iil
i
11
14
TLlF/812B-15
TIME-+
MAX
--I
~
TABLE I. UB and B Series DC Noise linmunity
and Noise Margin (TA = 25"C)
TL/F/8129-2
(b)
FIGURE 1. Minimum and Maximum Transfer
Characteristics for (a) Inverting Logic Function and (b)
Noninverting Logic Function
Input High Voltage
VIHmin
B types
UBtypes
2·253
Test
Conditions
Input
Voltage
Vo
(V)
VDD
(V)
(V)
0.5/4.5
1/9
1.5/13.5
5
10
15
1.5
3
4
0.5/4.5
1/9
1.5/13.5
5
10
15
1
2
2.5
0.5/4.5
1/9
1.5/13.5
5
10
15
3.5
0.5/4.5
1/9
1.5/13.5
5
10
15
4
7
11
8
12.5
I:::
(")
Z
.-_ _ _.....fl 1 >10 MU
~"""--~IIII5OOD
....--+....-VOUT=O
110000
Transition Voltage=VIN·
Tl/F/B129-4
VTN
A=O, B=1
J1 + Kp/Kn
-----+-fl 1>10 MU
L...,>-<....
..---+....-VOUT=O
1>10MU
TUF/BI29-5
A=B=1
-1..------------~--+Voo
A
1>10MU
TT_.i
_'
~VOUT
B
+ ~ (Voo -
. . .---+-._
VOUT=O
TL/F/B129-6
FIGURE 2. Typical Transfer ON/OFF ReSistances for
Various Input Combinations for CD4001
2-254
IVTPI)
(4)
C04011
~:::[)o-
10
~~
NAND
VDD
2-
1+2
1
~~
1t-6--.....~· VOUT
o
o
10
V,N -INPUT VOLTAGE (VDC)
TL/F/8129-8
CD4D01
~::[)o-NOR
VDD
10
~
1
':-2
1+2
o
o
,'"
10
V,N - INPUT VOLTAGE (VIC)
TL/F/8129-9
L...I--....+-...-+--if--VOUT
10
~~
"Ii
~
~
III
~
-2
'3
~
C>
I
~
Vss
o
TL/F/8129-7
1 +2+3+4
4
C>
>
o
i
11
'U
10
V,N - INPUT VOLTAGE (VDc)
TL/F/8129-10
FIGURE 3. Allowed Voltage Transfer Curve Shifts
which Result Due to Various Input Combinations
of Multiple Input Gates
2-255
By selecting IVTPI = VTN and Kp = Kn, transition voltage can
be designed to fall midway between OV and Voo-an ideal
situation for obtaining excellent noise immunity. However, it
is not always possible to obtain equal thresliold voltages
because of process variations. Also, W/L ratio for a P-channel device must be made 2 or 3 times larger than W/L ratio
for an N-channel device to take into account mobility variations. The designer should consider these factors when designing for the best noise immunity characteristics.
In equation (4), the value of Kp/Kn substituted is obtained
from equation (3). With different gate configurations, effective Wp and Wn values change; also, Kp/Kn ratio changes
and a shift in transfer characteristics results.
For the 4-input NOR gate Ii'ke CD4002, an empirical relation
for the low noise margin VNL has been obtained, which is as
follows:
(5)
VNL::::: voo[ __l _N-. - 0.1]
1.5
+ N~
The input voltage high noise margin VNH can be calculated by:
(6)
VNH ::::: VOO[0.9 - __l-N-' ]
15
. +--.!..
N
m
Similar equations can be derived for a NAND gate.
From equations (5) and (6), one can see that the low noise
margin VNL will decrease as a function of the number of
controlled inputs, while it will increase for a NAND gate. The
input HIGH noise margin will increase as a function of the
number of controlled inputs for the NOR gate; for the NAND
gate it will decrease.
Figure 4 depicts VOUT=f (YIN) for different configurations
for NOR and NAND gates. The system designer can thus
use these facts effectively in his design and obtain the best
possible configuration f.or the desired noise immunity wit~
National's logic family.
where:
Ni = number of used inputs/ gate
Nm=total number of inputs/gate
NORMALlZliD
YOUT
v?-
'.'
NORMAUZliO
]>-
.,
o.31--------1---1=j=>-
..
O.7i---+++-t----i
7-NO-R-MA.~i1>~
?-
u
L.....-...;O...
3...-0...
4·INPUT NOR
CD4002
/~
., •
4~NPUT
NAND
C04012
Tl/F/8129-11
?....:h
~~
.".
T~/F/8129-12
FIGURE 4. Example of Transfer Voltage Variation for NOR and NAND Gates for Various Input Combinations
I. Carr, W.N., and Mize, J.P., MOSILSI Design and Application, Texas Instrum~nts Electronic Series, 1972
2·256
National Semiconductor
Memory Brief 18
John Jorgensen
Thomas P. Redfern
MM54CIMM74C Voltage
Translation/Buffering
INTRODUCTION
A new series of MM54C/MM74C buffers has been designed
to interface systems operating at different voltage levels.
In addition to performing voltage translation, the
MM54C901/MM74C901 through MM54C904/MM74C904
hex buffers can drive two standard TTL loads at
Vee = 5V. This is an increase of ten times over the two
LpTTL loads that the standard MM54C/MM74C gate can
drive. These new devices greatly increase the flexibility
of the MM54C/MM74C family when interfacing to other
logic systems.
5 mAo The total power per TTL output is then
5 mA x 12V = 60 mW. The second problem is more
serious. Currents of 5 mA or greater from a CMOS
input clamp diode can cause four-layer diode action on
the CMOS device. This, at best, will totally disrupt
normal circuit operation and, at worst, will cause
catastrophic failure.
To overcome this problem the MM74C903 and
MM74C904 have been designed with a clamp diode from
inputs to Vee only. This single dio'de provides adequate
static discharge protection and, at the same time, allows
voltages of up to -17V on any input. Since there is
essentially no current without the diode, both the high
power dissipation and 'latch up problems are eliminated.
PMOS TO CMOS INTERFACE
Since most PMOS outputs normally can pull more negative than ground, the conventional CMOS input diode
clamp from input to ground poses problems. The least
of these is increased power consumption. Even though
the output would be clamped at one diode drop (-o.6V),
all the current that flows comes from the PMOS negative
supply. For TTL compatible PMOS this is -12V. A PMOS
oUJPut designed to drive one TTL load will typically sink
To demonstrate the above characteristics, Figures 1, 2,
and 3 show typical TTL compatible PMOS circuits
driving standard CMOS with two clamp diodes, TTL
compatible PMOS driving MM74C903/MM74C904, and
the TTL compatible PMOS to CMOS system interface,
respectively.
V"
!t5V)
~I+~""'
'-1 I
I
~
TYPICAL PMOS TTL
PUSH·PUll OUTPUT
-OmA
V~D
I
I
H2VI
I
I
MM74C90J/MM74C9D4
TL/F/60J4·2
FIGURE 1
TLlF/6034·1
FIGURE 2
MM~C!lOJ/MM14C90J or
[ MMS4C9D4/MM14C904
I
FIGURE 3. PMOS to CMOS or TTL Interface
2-257
TLlf/60343
co~--~----------~------------------------------~------------------------------,
....
m
:E
Figure 5. With this diode removed the current being
CMOS TO CMOS OR TTL INTERFACE
sourced goes from about lOrnA to the leakage current
of the reverse biased input diode.
When a CMOS system which is operating at Vcc = 10V
must provide signals to a CMOS system whose Vcc = 5V,
a p(oblem similar to that found in PMOS·to·CMOS inter·
face occurs. That is, current would flow through the
upper input diode of the device operating at the lower
Vcc. This current could be in excess of lOrnA on a
typical 74C device, as shown in Figure 4. Again, this will
cause increased power as well as possible four layer diode
action.
Since the MM74C901 and MM74C902 are capable of
driving two standard TTL loads with only normal input
levels, the output can be used to directly drive TTL. With
the example shown, the inputs of the MM74C901 are in
excess of 5V. Therefore, they can drive more than two
TTL loads. In this case the device would drive four loads
with V1N = 10V. If the MM74C902 were used, the output
drive would not increase with increased input voltage.
This is because the gate of the output n·channel device is
always being driven by an internal inverter whose output
equals that of Vcc of the device.
The example used was for systems of Vcc = 1OV 'on one
system and Vcc = 5V on the second, but the MM74C901
and MM74C902 are capable of using any combination of
supplies up to l5V and greater than 3V, as long as Vcc 1
is greater than or equal to VCC2 and grounds are
common. Figure 6 diagrams this configuration.
STD CMOS
@V cc $5V
TLIF/6034·4
FIGURE 4
,..
"-IMM54C90IfMM74c9Dlorl
MM54C9DZIMM14C902
TLIFI6Q34·6
MM74CIIOlfMM14C902
@Vcc=5V
FIGURE 6. CMOS to TTL or CMOS.t. Lower VCC
TLIFI603"'·5
FIGURE 5
Using the MM74C901 or MM74C902 will eliminate this
problem. This occurs simply because these parts are
designed with the upper diode removed, as shown in
The inputs on these devices are adequately protected
with the single diode, but, as with all MOS devices,
normal care in handling should be observed.
2·258
oJ
Section 3
MM54HC/MM74HC
.-
Section Contents
MM54HCOO/MM74HCOO Quad 2-lnput NAND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC02/MM74HC02 Quad 2-lnput NOR Gate . . . . . . .... . .. . . . .. .. . . .. . . ... ... .. ....
MM54HC03/MM74HC03 Quad 2-lnput Open Drain NAND Gate ...........................
MM54HC04/MM74HC04 Hex Inverter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HCU04/MM74HCU04 Hex Inverter ....................... :.....................
MM54HC08/MM74HC08Quad2-lnputANDGate .. .. . . .. .. . ... . . .. . . ... . .. .. . ... . . ... .
MM54HC10/MM74HC10Triple3-lnputNANDGate .................. ~..................
MM54HC11/MM74HC11Triple 3-lnput AND Gate' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC14/MM74HC14 Hex Inverting Schmitt Trigger .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .
M M54HC20/MM74HC20 Dual4-lnput NAN D Gate .....................................
MM54HC27/MM74HC27Triple3-lnput NOR Gate .. .. .. .. . . . . . . .. . . . .. ... .. ..... .. . . .. .
MM54HC30/MM74HC30 B-Input NAND Gate ....... " ................... , .. ... .. . . .. .
MM54HC32/MM74HC32 Quad 2-lnput OR Gate ...............................•.......
MM54HC42/MM74HC42 BCD-to-Decimal Decoder ................................•...
MM54HC51/MM74HC51 DuaIAND-OR-lnvertGate ....................................
MM54HC58/MM74HC58 Dual AND-OR Gate ..........................................
MM54HC73/MM74HC73 Dual J-K Flip-Flops with Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC74/MM74HC74 Dual D Flip-Flop with Preset and Clear. . • . . . . . . . . . . . . . . . . . . . . . . .
MM54HC75/MM74HC75 4-Bit Bistable Latch with Q and Output .......................
MM54HC76/MM74HC76 Dual J-K Flip-Flops with Preset and Clear. . . . . . . . . . . . . . . . . . . . . . . .
MM54HC85/MM74HC85 4-Bit Magnitude Comparator .................. '.. .. .. . ..•. ...•
MM54HC86/MM74HC86 Quad 2-lnput Exclusive OR Gate ............................... '.
MM54HC107/MM74HC107 Dual J-K Flip-Flops with Clear. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .
MM54HC109/MM74HC109 Dual J-K Flip-Flops with Preset and Clear. . . . . . . . . . . . . . . . . . . . . .
,MM54HC112/MM74HC112 Dual J-K Flip-Flops with Preset and Clear. . . . . . . . . . . . . . . . . . . . . .
MM54HC113/MM74HC113 Dual J-K Flip-Flops with Preset. . . . . . . . . . . . . . . . • . . . . . . . . . . . . .
MM54HC123A/MM74HC123A Dual Retriggerable Monostable Multivibrator . . . . . . . . . . . . . . .
MM54HC125/MM74HC125TRI-STATEOuad Buffers. '" ................ , .. .. . ... . . . .. .
MM54HC126/MM74HC126TRI-STATEOuad Buffers .......................... "'." . .. .
MM54HC132/MM74HC132 Quad 2-lnput NAND Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC133/MM74HC133 13-lnput NAND Gate . . .. .. .. . .. . .. .. .. . .. . . .. ... . .. .. .. .. .
MM54HC137/MM74HC137 3-to-8 Line Decoder with Address Latches (Inverted Output) . . . . . .
MM54HC138/MM74HC138 3-to-8 Line Decoder .... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC139/MM74HC139 DuaI2-to-4 Line Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC147/MM74HC147 10-to-4LinePriorityEncoder ...............................
a
\
3·3
3-7
3-10
3-13
3-16
3-19
3-22
3-25
3-28
3-31
3-34
3-37,
3-40
3-43
3-46
3-49
3-49
3-52
3-56
3-59
3-62
3-66
3-70
3-73
3-77
3-80
3-84
3-88
3-93
3-93
3-96
3-99
3-102
3-106
3-109
3-112
Section Contents (Continued)
MM54HC149/MM74HC149 8·to·8 Line Priority Encoder ................................
3·115
MM54HC1511MM74HC151 8·Channel Multiplexer. . . ..•. ..... . .. .. .•.. . .•.. . .• ... ..•. .
3·118
MM54HC153/MM74HC153 Dual4-lnput Multiplexer. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . • . . . . .
3·121
MM54HC154/MM74HC154 4·to·16 Line Decoder. . . . . • . • . . . . . . • . • . . . . • . . . • . . . . • . . . . • . .
3·124
MM54HC15q/MM74HC155 Dual 2·to·4 Line Decoders ...•...•.......•....•.......... , . •
3·128
MM54HC157/MM74HC157 Quad 2·lnput Multiplexer. . . . . . . . . . . . . . . . . . . • . . . . • . . . . . . . .. .
3·131
MM54HC158/MM74HC158 Quad 2·lnput Multiplexer (Inverted Output) ....................
3·131
MM54HC160/MM74HC160 Synchronous Decade Counter ..............................
3·135
MM54HC161/MM74HC161 Synchronous Binary Counter •.............•......•.........
3·135
MM54HC162/MM74HC162 Synchronous Decade Counter ...•.........••...............
3·135
MM54HC163/MM74HC163 Synchronous Binary Counter ~..............................
3·135
MM54HC164/MM74HC164 8·Bit Serial·ln Parallel·Out Shift Register .....................
3·140
MM54HC165/MM74HC165 Parallei-ln Serial·Out8-Bit Shift Register. . . . . • . . . . . . . . . . . . . . . .
3·143
MM54HC173/MM74HC173TRI·STATEQuad 0 Flip·Flop .....•......•..•.•........ ,.....
3·147
M M54HC17 4/ M M74HC174 Hex 0 Flip·Flops with Clear. . . . . . . . . . . . . . . . . . . . . . . • . • . . . . • . .
3· i 51
M M54HC175/ M M74HC175 Quad D·Type Flip·Flop with Clear .............•....•.....•.•.
3·154
MM54HC181/MM74HC181 Arithmetic Logic Units/Function Generators. . . . . . . . . . . . . . . . . . .
3·158
M M54HC182/ M M7 4HC182 Look·Ahead Carry Generator. . . . . . .. • . . . . • . . . . . . . • • . . . . . . . . .
3-166
MM54HC190/MM74HC190Synchronous Decade Up/Down Counters with Mode Control .....
3·170
MM54HC191/MM74HC191 Synchronous Binary Up/Down Counters with Mode Control ......
3·170
MM54HC192/MM74HC192 Synchronous Decade Up/Down Counters .. . • . • • • . . . . • . . . . . . . .
3·177
MM54HC193/MM74HC193Synchronous Binary Up/Down Counters ..•.. . . • • . • • . • • . . . • . . .
3·177
MM54HC194/MM74HC194 4·Bh Bidirectional Shift Register. .. . . . . . . . . . . . . . . . . . . . . . . . . .
3·184
MM54HC195/MM74HC195 4·Bit Parallel Shift Register;-; . . . . . • . . . . . . • . . • . . . . . . . . . . . . . .3·188
MM54HC221A/MM74HC221A Dual Non·Retriggerable Monostable Multivibrator. . • . . . . . . . .
3·192
MM54HC237/MM74HC237 3·to·8 Decoder with Address Latches .•....•..... , ..•.. ..... .
3·197
MM54HC240/MM74HC240 Inverting Octal TRJ·STATE Buffer •...............•... ". . . . . . . . .• 3-201
MM54HC241/MM74HC241 Octal TRJ·STATE Buffer .............•..•.................•.
3·201
MM54HC242/MM74HC242 Inverting Quad TRJ·STATETransceiver ...... ". . . . . . . . . . . . . . . . . .
3·206
MM54HC243/MM74HC243 Quad TRJ·STATETransceiver .....•..•........•..•... i.......
3·206
MM54HC244/MM74HC244 Octal rRJ·STATE Buffer .. . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . • . . .
3·210
MM54HC245/MM74HC245 Octal TRJ·STATETransceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3·214
MM54HC251/MM74HC251 8·Channel TRJ·STATE Multiplexer. ; . . . . . . . . . . . . . . . . . . . . . .. . .
3·218
MM54HC253/MM74HC253 Dual4·Channel TRI·STATE Multiplexer. . . . . . . . . . . . . . . . . . . . . . . .
3-221
MM54HC257/MM74HC257 Quad 2·Channel TRI·STATE Multiplexer ..... " . . . . . . . . . . . • . . . . .
3·224
3·4
.Section Contents (Continued)
MM54HC259/MM74HC259 8·Blt Addressable Latch/3·to·8 Line Decoder. . . . . . . . . . . . . . . . . .
MM54HC266/MM74HC266 Quad 2·lnput Exclusive NOR Gate ...........................
MM54HC273/MM74HC273 Octal 0 Flip·Flops with Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC280/MM74HC280 9·Bit Odd/Even Parity Generator/Checker ....................
MM54HC283/MM74HC283 4·Bit Binary Adder with Fast Carry. • . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC298/MM74HC298 Quad 2,lnput Multiplexers with Storage. . . . . . . . . . . . . . . . . . . . • . •
MM54HC299/MM74HC299 B-Blt TRI·STATE Universal Shift Register. . . . . . . . . . . . . . . . . . . . . .
MM54HC354/MM74HC354 B-Channel TRI·STATE Multiplexers with Latches . . . . . . . . . . . . . . .
MM54HC356/MM74HC356 8·Channel TRI·STATE Multiplexers with Latches . . • . . . . . . . . . . . .
MM54HC365/MM74HC365 HexTRI·STATE Buffer ....•................................
MM54HC366/MM74HC366 Inverting Hex TRI·STATE Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC367/MM74HC367HexTRI·STATEBuffer ................. :...................
MM54HC368/MM74HC368 Inverting Hex TRI·STATE Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC373/MM74HC373 TRI·STATE Octal O·Type Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC374/MM74HC374 TRI·STATE Octal OoType Flip·Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC390/MM74HC390 Dual 4·Bit Decade Counter .................................
MM54HC393/MM74HC393 Oual4-Bit Binary Counter ...........................•......
MM54HC423A/MM74HC423A Dual Retriggerable Monostable Multivibrator . . . . . . . . . . . . . . .
. MM54HC521/MM74HC521 8·Bit Magnitude Comparator (Equality Detector) . . . . . . . . . . . . . . .
MM54HC533/MM74HC533 TRI·STATE Octal O·Type Latch with Inverted Outputs ............
MM54HC534/MM74HC534 TRI·STATE Octal O·Type Flip·Flop with Inverted Outputs. . . . . . . . . .
MM54HC540/MM74HC540 Inverting Octal TRI·STATE Buffer ......... .'..................
MM54HC541/MM74HC541 Octal TRI·STATE Buffer. . • • . • . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .
MM54HC563/MM74HC563 TRI·STATE Octal O·Type Latch with Inverted Outputs ............
MM54HC564/MM74HC564 TRI·STATE Octal O·Type Flip·Flip with Inverted Outputs ........ :.
MM54HC573/MM74HC573 TRI·STATE Octal O·Type Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC574/MM74HC574 TRI·STATE Octal O·Type Flip·Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC589/MM74HC589 8·Bit Shift Register with Input Latches and
TRI·STATESeriaIOutput ........................................................
MM54HC590/MM74HC590 B-Bit Binary Counter with TRI·STATE Output Register .. . . . . . . . . .
MM54HC592/MM74HC592 B-Bit BinaryCounterwith Input Register. . . . . . . . . . . . . . . . . . . . . .
MM54HC593/MM74HC593 B-Bit Binary Counter with Bidirectional
Input Register/Cou!')terOutputs ....•.........•...............'. . . . . . . . . .. . . . . . . . . .
3-5
3·227
3·231
3·234
3·238
3·241
3·246
3·250
3·255
3·255
3·263
3·263
3·263
3:263
3·270
3·273
3·276
3-276
3·281
3-286
3·289
3·292
3·295
3·295
3·298
3·301
3-304
3·307
3·310
3·315
3·317
3·317
Section Contents (Continued)
MM54HC595/MM74HC595 8-Bit Shift Registers with Output Latches ........... ~ ........ .
MM54HC597/MM74HC597 8-Bit Shift Registers with Input Latches ..................... .
MM54HC640/MM74HC640 Inverting Octal TRI-STATETransceiver .' ...................... .
MM54HC643/MM74HC643 True-Inverting Octal TRI-STATE Transceiver ................... .
MM54HC646/MM74HC646 Non-Inverting Octal Bus Transceiver/Registers ................ .
ty1M54HC648/MM74HC648Inve~ing O~tal Bus Transceiver/Reg~sters .................... .
MM54HC688/MM74HC688 8-Blt Magnitude Comparator (Equality Detector) .............. .
MM54HC4002/MM74HC4002 Dual4-lnput NOR Gate ...........•....... ! . . . . • . . . . • . . . . .
MM54HC4016/MM74HC4016Quad Analog Switch ................................... .
M M54HC4017/MM74HC4017 Decade Counter/Divider with 10 Decoded Outputs ........... .
MM54HC4020/MM74HC4020 14-Stage Binary Counter ................ " ... , ........•...
MM54HC4024/MM74HC4024 7-Stage Binary Counter ................................. .
MM54HC4040/MM74HC4040 12-Stage Binary Counter ................................ .
MM54HC4046/MM74HC4046 CMO~ Phase Lock Loop ..............................•..
MM54HC4049/MM74HC4049 Hex Inverting Logic Level Down Converter .................. .
MM54HC4050/MM74HC4050 Hex Logic Level Down Converter ..........•...............
MM54HC4051/MM74HC4051 8-Channel Analog Multiplexer ............... : ........... .
MM54HC4052/MM74HC4(J52 Dual4-Channel Analog Multiplexer .........•..... ! ....... .
MM54HC4053/MM74HC4053 Triple 2-Channel Analog Multiplexer ....................... .
MM54HC4060/MM74HC4060 14-Stage Binary Counter. ............................... .
MM54HC4066/MM74HC4066 Quad Analog Switch ................................... .
MM54HC4075/MM74HC4075 Triple 3-lnput OR Gate .................................. .
I'iIIM54HC4078/MM74HC4078 8-lnput NOR/OR Gate •................ , . l • • • • • • • • . • • . • • •
MM54HC4316/MM74HC4316 Quad Analog Switch with Level Translator .................. .
MM54HC4511/MM74HC4511 BCD-to-7 Segment Latch/Decoder/Driver .................. .
MM54HC4514/MM74HC4514 4-to-16 Line Decoder with Latch .......................... .
MM54HC4538/MM74HC4538 Dual Retriggeratile Monostable Multivibrator . _............. .
MM54HC4543/MM74HC4543 BCD-to-7 Segment Latch/DecoderlDriver for
Liquid Crystal Displays ................. -... : ; .................................. .
MM74HC942 300 Baud Modem (+ 5, - 5 Volt Supply) ................................. .
MM74HC943 300 Baud Modem (5 Volt Supply) ....................................... .
3-6
3-320
3-325
3-330
3-330
3-334
3-334
3-341
3-357
3-360
3-365
3-369
3-369
3-369
3-374
3-383
3-383
3-386
3-386
3-386
3-393
. 3·397
3·402
3-405
3-408
3-413
3-418
3-422
3-428
3-344
3-350
r-------------------------------------------------------------~~
~National
""-"
~ Semiconductor
A.A
!
""
5
r-\
)'
microCMOS
~
MM54HCOO/MM74HCOO
~
~
Quad 2-lnput NAND Gate
::J:
.....
""
(')
General Description
Features
These NAND gates utilize microCMOS Technology, 3,5 micron silicon gate P-well CMOS, to achieve operating speeds
similar to LS-TTL gates with the low power consumption of
standard CMOS integrated circuits. All gates have buffered
outputs. All devices have high noise immunity and the ability
to drive 10 LS-TTL loads. The 54HC/74HC logic family is
functionally as well as pin-out compatible with the standard
54LS174LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to Vee
and ground.
•
•
•
•
•
o
o
Typical propagation delay: 8 ns
Wide power supply range: 2-6V
Low quiescent current: 20 p.A maximum (74HC Series)
Low input current: 1 p.A maximum
Fanout of 10 LS-TTL loads
Connection and. Logic' Diagrams
Dual-In-Line Package
A1
TL/F/5292-1
Top View
Order Number MM54HCOOJ or MM74HCOOJ, N
See NS Package J14A or N14A
:~Y
3-7
TLlF/5292-2
Absolute Maximum Ratings
Supply Voltage (Vee)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K. 10K>
DC Output Current. per pin (lOUT)
DC Vcc or GND Current. per pin (Icc)
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
Lead Temperature (Tu
(Soldering 10 seconds) .
Operating Conditions
(Notes 1 & 2)
-0.5 to +7.0V
-1,5 to Vcc+ 1.5V
-0.5 to Vee + 0.5V
±20mA
±25mA
±50mA
-65'C to ,.: 150"C
500mW
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Min
2
Max
6
Units
V
0
Vcc
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
-
Input Rise or Fall Times
Vcc=2V
(tr• ~t>
. Vcc=4.5V
Vcc=6.0V
260'C
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=2S'C
Typ
74HC
TA=-40to8S'C
S4HC
TA=-S5to125"C
Units
Guarantsed Umlts
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2'
V
V
V
VOH
Minimum High Level
Output Voltage
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
3.84
5.34
3.7
5.2
.V
V
VIN=VIHorVIL
!IOUT!:S:20 pA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
4.5V
6.0V
4.2
5.7
3.98
5.48 .
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIH
lIoUT!:S: 4.0 mA
!IOUT!:S:5.2mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VeeorGND
6.0V
±0.1
±1.0
±1.0
pA
VIN = VIH or VIL
lIoUT!:S:4.0 mA
!IOUT!:S:5.2 mA
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
VIN=VIH
!IOUT!:S:20 pA
Maximum Quiescent VIN=VccorGND 6.0V
2.0
20
40
pA
Supply Current
IOUT=OpA
Note 1: Absolute Maximum Ratings are Ihose values beyond which damage to the device may occur.
Note 2: Unless olherwise specified all voltages are ref~re;,ced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mWrc from 65'C to 8S'C; ceramic "J" package: -12 mWI'C from 100"C to 12S'C.
Note 4: For a power supply of SV ±10% the worst case output voltages (YOH. and VoLl occur for HC at 4.SV. Thus the 4.SV values should be used when
designing with Ihis supply. Worst case VIH and VIL occur at Vcc= S.SV.and 4.SV respectively. (The VIH value at S.SV Is 3.8SV.) The worst case leakage current (liN.
ice. and loZ> occur for CMOS at the higher voltage and so the 6.0V valuas should be used.
Icc
3-8
'.
AC Electrical Characteristics Vee = 5V, TA = 25°C, CL = 15 pF, tr= tf= 6 ns
Symbol
Parameter
tpHL, tpLH
Maximum Propagation
Delay
Conditions
Typ
Guaranteed
Limit
Units
8
15
ns
AC Electrical Characteristics Vee = 2.0V to 6.0V, CL = 50 pF, tr= tf= 6 ns (unless otherwise specified)
Symbol
Paral1leter
Conditions
Vee
TA=25°C
Typ
74HC
TA= -40to 85°C
54HC
TA= -55 to 125°C
Units
Guaranteed Limits
Maximum Propagation
Delay
2.0V
4.5V
6.0V
45
9
8
90
18
15
113
23
19
, 27
23
ns
ns
ns
trLH, tTHL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
CPO
Power Dissipation
Capacitance (Note 5)
tpHL, tpLH
(per gate)
134
20
pF
Maximum Input
5
10
10
10
pF
Capacitance
Nole 5: CpO determines the no load dynamic power consumption, Po= Cpo Vr:xi2 f+ Icc Vee, and the no load dynamic current consumption, IS = Cpo Vcc f+ Icc.
CIN
.
.
-
3-9
~
C)
o
::E:
~
::&
::&
§
::E:
~
In
::&
::&
.----------------------------------------------------------------------------,
~National
\
~ Semiconductor
MM54HC02/MM74HC02 Quad 2-lnput
NOR Gate
General Description
Features
These NOR gates utilize microCMOS Technology, 3.5 micron silicon gate P-well CMOS, to achieve operating speeds
similar to LS-TTL gates with the low power consumption of
standard CMOS integrated circuits. All gates have buffered
outPl,lts, providing high noise immunity and the ability to
drive 10 LS-TTL loads. The 54HC174HC logic family is functionally as well as pin-out 'compatible with the standard
54LS174LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to Vee
and ground.
• Typical propagation delay: 8 ns
• Wide power supply range: 2-6V
• Low quiescent supply current: 20 ".A ~aximum
(74HC Series)
• Low input current: 1 ",A maximum
• High output current: 4 mA minimum
Connection and Logic Diagrams
vee
Dual-In-Llne Package
64
A4
Y3
Y4
A3
B3
14
13
12
11
10
9
8
1
2
3
4
5
6
7
Y1
A1
J
microCMOS
B1
Y2
A2·
B2
GND
TL/F/5294-1
Top View
Order Number MM54HC02J or MM74HC02J, N
See NS Package J14A or N14A
A
Y
B
TUF/5294-2
3-10
Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage (VeC>
-0.5 to + 7.0V
DC Input Voltage (VIN)
-1.5 to Vee + 1.5V
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
±20mA
Clamp Diode Current (11K, 10K)
DC Output Current, per pin (lOUT)
±25mA
±50mA
DC Vee or GND Current, per pin (IcC>
Storage Temperature Range (TSTG)
- 65'C to + 150'C
Power Dissipation (Po) (Note 3)
500mW
Lead Temp. (TO (Soldering 10 seconds)
260'C
Operating Conditions
Supply Voltage {VeC>
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Min
2
Max
6
Units
V
0
Vee
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
Vee=2.0V
(tr, ttl
Vee=4.5V
Vee=6.0V
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25'C
74HC
TA= -40 to 85'C
Typ
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
VIH
Minimum High Level •
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN=VIL
IIOUTI ,;; 20 /loA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIH orVIL
IIOUTI ';;4.0 mA
IIOUTI,;;5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VIL
IIOUTI';;4.0 mA
IIOUTI';;5.2 mA
VOL
Maximum Low Level
Output Voltage
VIN=VIHorVIL
IIOUTI';;20 /loA
liN
Maximum Input
Current
VIN=VCCorGND
6.0V
±0.1
±1.0
±1.0
/loA
IcC
Maximum Quiescent
Supply Current
VIN=VeeorGND
IOUT=O/loA
6.0V
2.0'
20
40
/loA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground,
Note 3: 'Power Dissipation temperature derating - plastic UN" package: -12 mW,'e from 6S'C to 8S'C; ceremic "J" package: -12 mWI'C from t OO'C to 12S'C,
Note 4: For a power supply of SV ±10% the worst case output voltages (YOH. and VoU occur for HC at 4.SV. Thus the 4,SV values should be used when
designing with this supply. Worst cese VIH and VIL occur at Vee = S.SV and 4,5V respactively, (The VIH value at 5,SV is 3.8SV.l The worst case leakage current (liN.
. lee. and lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
3·11
AC Electrical Characteristics Vcc=5V, TA=25"C, CL =15pF,tr =t,=6ns
Symbol
Parameter
tpHL, tpLH
Maximum Propagation
Delay
Conditions
Typ
Guaranteed
Limit
Units
8
15
ns
,
AC Electrical Characteristics Vcc= 2.0V to 6.0V, CL = 50 pF, tr =t,=6 ns (unless otherwise specified)
Symbol
Parameter
,Conditions
Vee
TA=25"C
74HC
TA= -40to8S"C
Typ
Units
Guaranteed Limits
8
90
18
15
113
23
19
'134
27
23
ns
ns
ns
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
tpHL, tpLH
Maximum Propagation
Delay
2.0V
4.5V
6.0V
45
9
trLH, tTHL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
CPO
Power Dissipation
CapaCitance (Note 5)
CIN
Maximum Input
CapaCitance
(per gate)
S4HC
TA=-5Sto125"C
20
5
pF
10
10
10
pF
,
Note 5: Cpo determines the no load dynamic power consumption, Po = Cpo Vcrll+ lee Vee. and the no load dynamic current consumption, IS = Cpo Vee 1+ IcC.
.\
\
,
3-12
~National
~ Semiconductor
microCMOS
MM54HC03/MM74HC03 Quad 2-lnput
Open 'Drain NAND Gate
General Description
Features
These NAND gates utilize microCMOS Technology, 3.5 micron silicon gate P-well CMOS, to achieve operating speeds
similar to LS-TIL gates with the low power consumption of
standard CMOS integrated circuits.. All gates have buffered
outputs. All devices have high noise immunity and the ability
to drive 10 LS-TIL loads. The 54HC/74HC logic family is
functionally as well as pin-out compatible with the standard
54LS174LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to Vee
and ground.
•
•
•
•
•
Typical propagation delay: 12 ns
Wide power supply range: 2-6V
Low quiescent current: 20 p.A maximum (74HC Series)
Low input current: 1 /-LA maximum
.
Fanout of 10 LS-TIL loads
As with standard 54HCi74HC push-pull outputs there are
diodes to both Vee and ground. Therefore the output should
not be pulled above Vee as it would be clamped to one
diode voltage above Vee. This diode is added to enhance
electrostatic protection.
Connection and
Lo~ic
Diagrams
Dual·ln·Line Package
A4
Y4
83
Y3
8
A1
TL/F/5295-1
Top View
Order Number MM54HCOSJ or MM74HC03J,N
See NS Package J14A or N14A
TL/F/5295-2
3-13
Absolute Maximum Ratings (Notes I & 2)
-0.5 to +7.0V
Supply Voltage (Vec)
DC Input Voltage (VIN)
-1.5toVcc+ I .5V
DC Output Voltage (VOUT)
-0.5 to Vce+ 0.5V
±20mA
Clamp Diode Current (11K. 10K)
±25mA
DC Output Current; per pin (lOUT)
±50mA
DC Vee or GND Current. per pin (Icel
-65·Cto +150·C
Storage Temperature Range (TSTG)
Power Dissipation (PD) (Note 3)
500mW
Lead Temp. (T (Soldering 10 seconds)
260·C
Operating Conditions
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TAl
MM74HC
MM54HC
-
u
Parameter
Conditions
Max
6
Units
V
0
Vee
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
(tr• td
Vee=2.0V
Vee=4.5V
Vee=6.0V
DC Electrical Characteristics (Note 4)
Symbol
Min
2
.
TA=25·C
Vee
. Typ
74HC
TA=-40t085·C
54HC
TA= -55to 125·C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN=VIHorVIL
IIOUTI S:20 p,A
RL =1 kO
Minimum Low Level
Output Voltage
VIN=VIH
IIOUTI S:20 p,A
RL =00
VOL
VIN=VIH
IIOUTIS:4.0 mA
IIOUTIS:5.2 mA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
(\.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
0.5
5
10
,p,A
±0.1
±1.0
±1.0
p,A
ILKG
Maximum High Level
Output Leakage Current
VIN=VIHorVIL
VOUT= Vec
6.0V
liN
Maximum Input
Current
VIN=VCeorGND
6.0V
,
Maximum Quiescent
2.0
20
40
p,A
VIN=Vee or GND 6.0V
Supply Current
IOUT=O p,A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
"
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic uN upackage: -12 mW rc from 65'C to 85'C; ceramic uJu package: -12 mWI'C from l00'C to 125"C.
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH. and VoLl occur for HC at 4.5V. Thus the 4.5Vvalues should be used when designing
with this supply. Worst case VIH and YIL occur at Vcc';' 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.1 The worst case leakage current (liN. 100 and
lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
lee
-
3-14
AC Electrical Characteristics Vcc=5V. TA=25'C. CL = 15 pF. t r =tf=6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
tpHL. tpLH
Maximum Propagation
Delay
RL =1 KO
10
20
ns
AC Electrical Characteristics
Vcc=2.0V to 6.0V. CL =50 pF. t r =t,=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=25'C
Maximum Propagation
Delay
tTHL
Maximum Output
Fall Time
CPO
CIN
Power Dissipation
-Capacitance (Note 5)
Maximum Input
Capacitance
RL =1 KO
Units
2.0V
4.5V
6.0V
63
13
11
125
25
21
158
32
27
186
37
32
ns
ns
ns
2.0V·
30
8
75
15
13
95
19
16
110
22
19
ns
ns
ns
4.SV
6.0V
(per gate)
54HC
TA= -55 to 125'C
Guaranteed Limits
Typ
tpHL. tpLH
74HC
TA= -40 to 85'C
7
20
5
pF
10
10
10
pF
Nota 5: CpO determines the no load dynamic power consumption. Po= Cpo Vcr:? 1+ IcC Vee. and the no load dynamic current consumption, IS = CpO Vee 1+ IcC.
The power dissipated by Al is not included.
3·15
~ r---------------------------------------------------------------------~----~
'8
%
~National .
t! ~ Semiconductor
:E
....
:E
~
8% MM54HC04/MM74HC04 Hex Inverter
~
an
:E
:E
General Description
Features
These inverters utilize microCMOS Technology, 3.5 micron
silicon gate P-well CMOS, to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits.
• Typical propagation delay: 8 ns
• Fan out of 10 LS-TTL loads
• Quiescent power consumption: 10 p.W maximum at
room temperature
• Typical input current: 10- 5 p.A
The MM54HC04/MM74HC04 is a triple buffered inverter. It
has high noise immunity and the ability to drive 10 LS-TTL
loads. The 54HC174HC logic family is functionally as well as .
pin-out ci$mpatible with the standard 54LS/74LS logic famiIy. All inputs are protected from damage due to static discharge by internal diode clamps to Vee and ground.
Connection and Logic Diagrams
Dual·ln·Line Package
AI
13
A1
Y1
YI
AS
Y5
Y4
A4
12
11
10
9
3
4
5
8
A2
Y2
A3
Y3
8
TUF/5069-1
Top View
Order Number MM54HC04J orMM74HC04J, N
See NS Package J14A or N14A
1 of 6 Inverters
TUF/5069-2
3-16
Absolute Maximum Ratings
Supply Voltage (VeC>
DC Inpul Voltage (VIN)
DC Outpul Voltage (VOUT)
Clamp Diode Currenl (1,K, 10K)
DC Output Currenl, per pin (lOUT)
DC Vee or GND Currenl, per pin (Icc>
Siorage Temperalure Range (TSTG)
Power Dissipalion (Po) (Nole 3)
Lead Temperalure (Tu
,
(Soldering 10 seconds)
Operating Conditions
(Noles 1 & 2)'
-0.510 +7.0V
-1.510Vee+ 1.5V
-0.510 Vee+0.5V
±20mA
±25mA
±50mA
Supply Voltage (VeC>
DC Inpul or Oulpul Voltage
(VIN, VOUT)
Operaling Temp. Range (TA)
MM74HC
MM54HC
-65'Clo +150'C
500mW
Min
2
Max
6
Units
V
0
Vee
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
Inpul Rise or Fall Times
(Ir, If}
Vee=2.0V
Vee = 4.5V
Vee=6.0V
260'C
DC Electrical Characteristics (Nole 4)
Symbol
Parameter
ConditIons
Vee
TA=25'C
Typ
74HC
TA=-40t085'C
54HC
TA= -55to 125'C
Units
Guaranteed Limits
,
V,H
Minimum High Level
,Inpul Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
. 4.2
1.5
3.15
4.2
VIL
Maximum Low Level
Inpul Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN=VIL
IIOUTI:S':20 /LA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
VIN=VIH
lIoUTI :S':4.0 mA
IIOUTI:S': 5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=Vce or GND
6.0V
±0.1
±1.0
±1.0
/LA
VIN=VIL
IIOUTI:S':4.0 rnA
lIoUTI :S': 5.2 mA
VOL
liN
Maximum Low Level
Outpul Voltage
Maximum Inpul
·Currenl
V
V
V
VIN=VIH
IIOUTI :S':20 /LA
,
V
V
V
Maximum Quiescenl V'N=VeeorGND' 6.0V
40
2.0
20
/LA
Supply Currenl
'OUT=O/LA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are relerenced to ground.
Note 3: Power Dissipation temperabJre derating - plastic UN"' package: -12 mW I'C from 65'C to 85'C; ceramic "J"' package: -12 mW rc from 1OO'C to 125"C.
Note 4: For a power supply of 5V ± 10% the worst case output voltages (VOH. and VoLl occur for HC at4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case V,H and V,L occur at Vcc= 5.5V and 4.5V respectively. (The V,H value at5.5V is 3.85V.) The worst case leakage current (liN. Icc. and
lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
ICC
3-17
,
AC Electrical Characteristics Vcc=5V. TA=25'C. CL =15 pF. t r =tf=6 ns
Symbol
Parameter
tpHL. tpLH
Maximum Propagation
Delay
Conditions
Typ
Guaranteed
Limit
Units
8
15
ns
AC Electrical Characteristics Vcc= 2.0V to 6.0V. CL = 50 pF. tr= tf= 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
-
Vee
TA=2S'C
Typ
74HC
TA= -40 to 8S'C
S4HC
TA=-SSt012S'C
Units
Guaranteed Limits
tpHL. tpLH
Maximum Propagation
Delay
2.0V
4.5V·
6.0V
55
11
9
95
19
16
120
24
20
145
.29
24
ns
ns
ns
tTLH. tTHL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
75
15
13
95
19
16
110
22
19
ns
ns
ns
CPO
Power Dissipation ,
Capacitance (Note 5)
CIN
Maximum Input
Capacitance
(per gate)
8
7
20
5
pF
10
10
10
pF
Nole 5: CpO determines the no load dynamic power consumption. Po =Cpo Vcc2 f+ lee Vee. and the no load dynamic current consumption. is =CPO Vee f+ lee.
3·18
~National
\
~ Semiconductor
J
microCMOS
MM54HCU04/MM74HCU04 Hex Inverter
General Description
logic family. All inputs are protected from damage due to
static discharge by internal diode clamps to Vee and
ground.
These inverters utilize microCMOS Technology, 3.5 micro
silicon gate P-well CMOS, to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMO~ integrated circuits.
The MM54HCU04/MM74HCU04 is an unbuffered inverter.
It has high noise immunity and the ability to drive 15 LS-TTL
loads. The 54HCUl74HCU logic family is functionally as
well as pin-out compatible with the standard 54LS/74LS
Features
• Typical propagation delay: 7 ns
• Fanout of 15 LS-TTL loads
• Quiescent power consumption: 10 ",A maximum at
room temperature
• Typical input current: 10- 5 ",A
Connection and Schematic Diagrams
Dual·lit·Line Package
vee
14
AI
AS
VB
AS
VS
A4
V4
13
12
11
10
9
8
2
3
4
S
S
7
A3
V3
VI
A2
V2
GND
Top View
Order Number MM54HCU04J or MM74HCU04J, N
See NS Package J14A or N14A
Vee
....---oy
TL/F/S296-2
3-19
TLlF/5296-1
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
-0.5 to +7.0V
Supply Voltage (Vee)
DC Input Voltage (VIN)
-1.5to,vee+ 1.5V
DC Output Voltage (VOUT)
-0.5 to Vee + 0.5V
±20mA
Clamp Diode Current (11K. 10K)
±25mA
DC Output Current. per pin (lOUT)
±50mA
DC Vee'or GND Current. per pin (Ice>
Storage Temperature Range (Tsm)
- 65'C t6 + 150'C
Power Dissipation (Po) (Note 3)
500mW
Lead Temp. (T L) (Soldering 10 seconds)
260'C
Supply Voltage (Vee>
Min
2
Max
6
Units
V
0
Vee
V
-40
-55
+85
+125
'C
·C
/
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TAl
MM74HCU
MM54HCU
I
. DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
TA=2S'C
Vcc
Typ
74HCU
TA=-40to8S'C
S4HCU
TA=-SSto12S'C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.7
3.6
4.8
1.7
3.6
4.8
1.7
3.6
4.8
V
V
V
VIL
Maximum Low Level
Input Voltage
2:0V
4.5V
6.0V
0.3
0.8
1.1
0.3
0.8
1.1
0.3
0.8
1.1
V
V
V
VOH
Minimum High Level
O~tput Voltage
VIN=VIL
IiOUTI s: 20 /J-A
2.0V
4.5V
6.0V
2.0
.4.5
6.0
1.8
4.0
5.5
1.8
4.0
5.5
1.8
4.0
5.5
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.2
0.5
0.5
0.2
0.5
0.5
0.2
0.5
0.5
V
V
V
VIN = Vee
IiOUTI s: 6.0 mA
IIOUTIS:7.8 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN.= Ve9 or GND
6.0V
±0.1
±1.0
±1.0
/J- A
VIN=GND
IIOUTI S:4.0 mA
IIOUTI s: 5.2 mA
VOL
liN
Maximum Low Level
Output Voltage
Maximum InP!Jt
Current "
VIN=VIH
IIOUTIS:20 /J-A
V
V
Maximum Quiescent VIN=VeeorGND
20
40
6.0V
2.0
/J- A .
Supply Current
IOUT=O/J-A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power DisSipation temperature derating - plastic "N" package: -12 mW/'C from 6S'C to 8S'C; ceramic "J" package: -12 mW/'C from 1OO'C to 12S'C.
Note 4: For a power supply of SV ± 10% the worst case outpu1voltagas (VOH. and VoLl occur for HC at 4.SV. Thus the 4.SV values should be used when deslgn!ng
wIIh this supply. Worst case VIH and VIL oocur at Vcc= S.SV and 4.S,{ respectively. (The VIH value atS.SV is 3.85V:) The worst case leakage current (liN. Icc. a~d
lozl occur fo~ CMOS attha higher voltage and so the 6.0V values should be used.
Icc
3-20
AC Electrical Characteristics Vee = 5V, TA = 25'C, CL = 15 pF, tr= t,= 6 ns
Symbol
Parameter
Conditions
tpHL, tpLH
Maximum Propagation
Delay
Typ
Guaranteed
Limit
Units
7
13
ns
. ,
AC Electrical Characteristics Vee = 2.0V to 6.0V, CL =50 pF, tr =t,=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=2S'C
74HCU
TA= -4Qto 8S'C
Typ
S4HCU
TA= -S5 to 12S'C
Units
Guaranteed Limits
tpHL, tpLH
Maximum Propagation
Delay
2.0V
4.5V
6.0V
49
9.9
8.4
82
16
14
103
21
18
120
24
20
ns
ns
ns
tTLH, trHL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
75
15
13
95
19
16
110
22
19
ns
ns
ns
CPO
Power Dissipation
Capacitance (Note 5)
(per gate)
8
7
"
.90
pF
Maximum Input
8
15
15
15
pF
CapacHance
Note 5: CPO determines the no loed dynamic power consumption, Po= cpo VCr:!- 1+ ICC Vee. and the no load dynamic current consumption, Is = Cpo Vee f+ Icc.
GIN'
Typical Applications
Ra""OMn
~D:
-t>
c'I
rt>--t>
Ra» R,
c, < Ca
R,
.1
R2
"
,VOUT
t-
R,
,,.:.
ca
FIGURE 2. Stable RC Oscillator
I
TLlF/5296-3
FIGURE 1. Crystal OSCillator
I~ I~>M,
R2
R,
YIN--.N-I'
0
fiGURE 3. Schmitt Trigger
,
3-21
,
TUF/5296-4
YOUT
Tl/F/5296-5
g
~ ~ National f:i ~ Semiconductor
r\
J
microCMOS
::::IE
~
B
::c
:;
::::IE
::::IE
MM54HCO~UMM74HC08
Quad2-lnput AND Gate
General Descrip~ion
Features
These AND gates utilize microCMOS Technology. 3.5 micron silicon gate P-well CMOS. to achieve operating speeds
similar to LS-TTL gates with the low power consumption of
standard CMOS integrated circuits. The HCOB has buffered
outputs. providing high noise immunity and the ability to
drive 10 LS-TTL loads. The 54HC174HC logic family is tunction8lly as well as pin-out compatible with the standard
54LS174LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to Vee
and ground.
• Typical propagation delay: 7 ns (tpHU. 12 ns (tpLH)
• Fanout of 10 LS-TTL loads
• Quiescent power consumption: 2 ",A maximum at room
temperature
• Typical input current: 10- 5 ",A
Connection Diagram
Dual-In-Llne Package
Vee
B4
A4
Y4
B3
J
A3
Y3
14
13
12
11
10
9
8
1
2
3
4
5
6
7
A1
B1
Y1
A2
B2
Y2
Top View
Order Number MM54HC08J or MM74HC08J, N
See NS Package J14A or N14A
3-22
GND
TL/F/5297 -1
Absolute Maximum Ratings (Notes 1 &2)
Supply Voltage (Vee>
DC Input Voltage (V'N)
DC Output Voltage (VOUT)
Clal'(lp Diode Current (I'K. 10K)
DC Output Current. per pin (lOUT)
DC Vee or GND Current. per pin (IcC>
Storage Temperature Range (T8TG)
Power Dissipation (Po) (Note 3)
Lead Temp. (TrJ (Soldering 10 seconds)
Operating Conditions
-0.5 to +7.0V
-1.5toVCG+1.5V
-0.5 to Vee+0.5V
±20mA
±25mA'
±50mA
-65·Cto + 150·C
Supply Voltage (Vee>
DC Input or Output Voltage
(V'N. VOUT)
Operating Temp. Range (TAl
MM74HC
MM54HC
Min
2
Max
6
Units
V
0
Vee
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
Vcc=2.0V
(tr• til
Vcc=4.5V
Vee=6.0V
I
500mW
260·C
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25"C
Typ
74HC
TA=-40t08S·C
S4HC
TA= -SSto 12S·C
Units
Guaranteed Limits
V'H
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
V'L
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
V'N=V'H
!IOUT! s: 20 /LA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V'
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=V'HorVIL
!IOUT!S:4.0 mA
!IOUT!S:5.2 mA .
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
V'N=VeeorGND
6.0V
±0.1
±1.0
±1.0
/LA
V'N=V'H
!IOUT!S:4.0 mA
lIoUT!S:5.2 mA
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
V'N = V'H or VIL
!IOUT!S:20 /LA
Maximum Quiescent VIN=VCCorGND 6.0V
40
2.0
20
/LA
Supply Current
IOUT=O/LA
Note 1: Absolute Maximum Ratings are those valu9'1 beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mWI'e from 65'C to 85·C; ceramic "J" package: -12 mWI'C from 100·C to 125·e.
Note 4: For a power supply of 5V ± 10% the worst case output voltages (VOH. and YOU occur for HC at 4.5V. Thus the 4.5V values should be used when deSigning
with this supply. Worst case VIH and VIL occur at Vcc= 5.5V and 4.5V respectively. (The VIH value at5.5V is 3.85V.) The worst case leakage current (liN. Icc. and
loz) occur for CMOS at the higher voltage and so the 6.DV values should be. used.
Icc
3·23
•
AC Electrical Characteristics Vee = 5V, TA= 25"C, CL = 15 pF,1r=t,= 6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
tpHL
Maximum Propagation
Delay, Output High to Low
12
20
ns
tpLH
Maximum Propagation
Delay, Output Low to High
7
15
ns
AC Electrical Characteristics Vee = 2.0V to 6.0V, CL = 50 pF, tr=t,= 6 ns (unless otherwise specified)
~ymbol
Parameter
Conditions
Vee
TA=2S"C
. tpLH
tTLH, tTHL
CPO
S4HC
TA=-SSto125"C
Units
Guaranteed Umits
Typ
tpHL
74HC
TA= -40 to 85"C
Maximum Propagation
Delay, Output High to Low
2.0V
4.5V
6.0V
77
15
13
121
24
20
151
30
25
175
35
30
ns
hs
ns
Maximum Propagation
Delay, Output
Low to High
2.0V
4.5V
6.0V
30
10
8
90
18
15
113
23
19
134
27
-23
ns
ns
ns
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8'
75
15
13
95
19
16
110
22
19
ns
ns
ns
Power Dissipation
. Capacitance (Note 5)
(per gate)
7
38
pF
10
Maximum Input
pF
4
10
10
Capacitance
Note 5: CPO determines the no load dynamic power consumption. Po = Cpo Vcr!- f+ lee Vee, and the no load dynamic current consumption, Is = Cpo Vee f+ lee-
CIN
,
3-24
r----------------------------------------------------------------,
~
~
~National
\
~ Semiconductor
-;
microCMOS
~
::J:
General Description
Features
•
•
•
•
•
Typical propagation delay: 8 ns
Wide power supply range: 2-6V
Low quiescent current: 20 /LA maximum (74HC Series)
Low input current: 1 /LA maximum
Fanout of 10 LS-TTL loads
Connection and Logic Diagrams
Dual·ln·Line Package
C3
B3
Y3
A3
4
A2
......
o.....
Q
These NAND gates utilize microCMOS Technology, 3.5 micron silicon gate P-well CMOS, to achieve operating speeds
similar to LS-TTL gates with the low power consumption of
standard CMOS Integrated circuits. All gates have buffered
outputs. All devices have high noise immunity and the ability
to drive 10 LS-TTL loads. The 54HC/74HC logic family is
functionally as well as pin-out compatible with the standard
54LS174LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to Vee
and ground.
B1
""
o
.....
Q
~
~
MM54HC1 O/MM7 4HC1 0
Triple 3-lnput NAND Gate
A1
UI
::J:
82
Tt/F/5153-1 .
Top View
Order Number MM54HC10J or MM74HC1OJ,N
See NS Package J14A or N14A
Y=ABC
TLlF/5153-2
3-25
Absolute Maximum Ratings
Supply Voltage (Vee)
DC Input Voltage (VIN)
DC Output Voltage (Vour)
Clamp Diode Current (11K. 10K)
DC Output Current. per pin' (lour)
DC Vee or GND Current. per pin (Icc)
Storage Temperature Range (TsrG)
Power Dissipation (Po) (Note 3)
Lead Temperature (Tu,
(Soldering 10 seconds)
Operating Conditions
(Notes 1 &2)
-0.5 to + 7.0V
-1.5 to Vcc+ 1.5V
-0.5 to Vcc+0.5V
±20mA
±25mA
±'50mA
Supply Voltage (Vcc)
DC Input or Output Voltage
(VIN.Vour)
Operating Temp. Range (TA)
MM74HC
MM54HC
- 65·C to + 1500C
500mW
Min
2
Max
6
Units
V
0
Vee
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
(tr. tf)
Vee=2.0V
Vee=4.5V
Vee=6.0V
260·C
DC Electrical Characteristics (N~te 4)
Parameter
Symbol
Conditions
Vee
TA=25·C
Typ
74HC
TA= -40to85"C
54HC
TA=-55to125"C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
I
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
Ilourl:S:20 ~A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9,
1.9
4.4(
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIH
Ilourl:S:4.0 mA
Ilourl:S:5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4,
V
V
VIN=VCCor GND
6.0V
±0.1
±1.0
±1.0
/LA
Vn,j=VIH orVIL
Iiourl:s: 4.0 mA
, Iiourl:s: 5.2 mA
VOL
Maximum Low Level
Output Voltage
\
liN
Maximum Input
Current '
VIN=VIH
Ilourl:S: 20 IJA
Maximurp Quiescent VIN=VCCorGND
20
40
6.0V
2.0
/LA
Supply Current
lour=O /LA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specffied all voltages are referenced to ground.
Note S: POwer Dissipation temperawre derating - plastic "N" package: -12 mWre from WC to 85·C; ceramic "J" package: '-12 mW'"C from 100"C to 125"C.
Note 4: For a power supply of 5V ± 10% the worst case output voltages (VOH, and Vou occur for HC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and Vil occur at Vcc= 5.5V and 4.5V respectively, (The VIH value at 5.5V is 3.85V.) The worst case leakage current (liN. Icc, and
10V occur for CMOS at the higher voltage and so the 6.0V valuas should be used.
Icc
3-26
AC Electrical Characteristics VCc=5V, TA=25'C,CL =15pF, t r =tl=6ns
Symbol
Parameter
tpHL, tpLH
Maximum Propagation
Delay
Conditions
Typ
Guaranteed
Umit
Units
8
15
ns
,
AC Electrical Characteristics Vcc=2.0V to 6.OV, CL =50 pF, tr =tl=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=25'C
74HC
TA= -40 to 85'C
Typ
54HC
TA= -55to 125'C
Units
Guaranteed Limits
tpHL, tpLH
Maximum Propagation
Delay
2'.OV
4.5V
6.OV
48
10
8
90
18
15
113
23
19
134
27
23
ns
ns
ns
tTLH, tTHL
Maximum Output Rise
and Fall Time
2.0V
4,5V
6.OV
30
8
7
,75
95
19
16
110
22
19
ns
ns
ns
CPD
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input
Capacitance
(per gate)
15
13
20
5
pF
10
10
10
pF
Note 5: CPO determines the no load dynamic power consumption, Po= CPO Vcc2 1+ Icc Vec, and the no load dynamic current consumption, Is = Cpo Vcc 1+ Icc.
(
3-27
-""
~National
\
~ Semiconductor
")
microCMOS
MM54HC11/MM74HC11
Triple 3-lnput AND Gate
General Description
Features
These AND gates utilize microCMOS Technology, 3.5 micron silicon gate P-well CMOS, to achieve operating speeds
similar to LS-TIL gates with the low power consumption of
standard CMOS integrated circuits. All gates have buffered
outputs, providing high noise immunity and the ability to
drive 10 LS-TIL loads. The 54HC/74HC logic family is func,
tionally as well as pin-out compatible with the standard
54LS174LS logic family. All inputs are protected from damage due to static discharge by 'internal diode clamps to Vee
and ground.
.
•
•
•
•
•
Typical propagation delay: 12 ns
Wide power supply range: 2-6V
Low quiescent current: 20 ,..,A maximum (74HC Series)
Low input current: 1 ,..,A maximum
Fanout of 10 LS-TIL loads
Connection and Logic Diagrams
Dual-In-Une Package
,Y1
C1
2
A1
B1
C3
3
A2
B3
4
B2
5
C2
Y2
GND
TL/F/529B-1
Top View
Order Number MM54HC11J or MM74HC11J, N
See NS Package J14A or N14A
A--t>o--C~-..,
B--I>o--C~---f
»--c>o--Y
C--I>o--C~---'''''
TLlF/529B-2
(1 OF 3 GATES)
3-28
Absolute Maximum Ratings
-0.5 to +7.0V
Supply Voltage (Vee>
DC Input Voltage (VIN)
-1.5 to Vee + 1.5V
Supply Voltage (Vee>
DC Output Voltage (Vour)
-0.5 to Vee+0.5V
DC Input or Output Voltage
Clamp Diode Current (11K. 10K)
±20mA
DC Output Current. per pin (lour)
±25mA
Operating Temp. Range (Till
MM74HC
MM54HC
-65·C to + 150·C
Power Dissipation (Po) (Note 3)
500mW
Min
2
Max
6
Units
V
0
Vee
V
-40
-55
Input Rise or Fall Times
Vee=2.0V
(tr• tt)
Vee=4.5V
Vee=6.0V
Lead Temperature (Tu
(Soldering 10 seconds)
U'I
260·C
+85
+125
·C
·C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25·C
74HC
TA= -40to 85·C
Typ
54HC
TA= -5510 125·C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage.
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
V
V
V
VIN=VIH
Ilourl~20 /kA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
.5.9
1.9
4.4
5.9
1.9
4.4
5.9
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
. 6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
Ilourl~4.0 mA
Ilourl~5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
-
VIN=VIH
Ilourl~4.0 mA
Iiourl ~ 5.2 mA
VOL
Maximum Low Level
Output Voltage
VIN = VIH or VIL
liourl~20 /kA
liN
Maximum Input
Current
VIN=VeeorGND
6.0V
±0.1
±1.0
±1.0
/k A
Icc ..
Maximum Quiescent
Supply Current
VIN=VeeorGND
lour=O /kA
6.0V
2.0
20
40
/k A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Nole 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mW I'C from 65'C to 85'C; ceramic "J" package: -12 mW I'C from 100'C to 125'C.
Nole 4: For a power supply of 5V ± 10% the worst case output voltages (VOH. and VoLl occur for HC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at Vcc~ 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (liN. Icc. and
loz) occur for CM013 at the higher voltage and so the 6.0V values should be used.
3-29
.co.
:::E:
o
....
....
.....
3:
(VIN. Vour)
±50mA
DC Vee or GND Current. per pin (Ice>
Storage Temperature Range (TSTG)
3:
3:
Operating Conditions
(Notes 1 & 2)
3:
.....
.co.
:::E:
o
....
....
AC Electrical Characteristics Vcc=5V, TA = 25°C, CL=15pF,tr =tj=6 ns
Symbol
Parameter
Conditions
tpHL, tpLH
Maximum Propagation
Delay'
Typ
Guaranteed
LImit
Units
12
20
ns
AC Electrical Characteristics
Vcc=2.0V to B.OV, CL =50 'pF, tr=t(=6 ns (unless otherwise specified)
Symbol
Parameter
Vee
Conditions
Typ
tpHL, tpLH
Maximum Propagation
Delay
tTLH, tTHL
Maximum Output Rise
and Fall Time
CPO
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input
CapaCitance
-
(per gate)
TA=25°C
74HC
TA=-40t085"C
54HC
TA= -55 to 125"C
Units
Guaranteed Limits
2.0V
4.5V
B.OV
48
18
15
125
25
21
15B
31
27
190
38
31
ns
ns
ns
2.0V
4.5V
B.OV
30
8
75
15
13
95
19
16
110
22
19
ns
ns
ns
7
35
5
pF
10
10
10
pF
Note 5: CPO determines the no load dynamic power consumption, Po = Cpo vc;c2 1+ Icc Vcr;. and the no load dynamic current consumption, Is= Cpo Vcc 1+ Icc.
/
3-30
r-------------------------------------------------------,~
~
~National
CI'I
~
~ Semiconductor
microCMOS
::c
o
....
~
~
~
MM54HC14/MM74HC14
Hex Inverting Schmitt Trigger
:ii:!'
::c
o
....
~
General Description
Features
The MM54HC14/MM74HC14 utilizes microCMOS Technology, 3.5 micron silicon gate P-well CMOS, to achieve the
low power dissipation and high noise immunity of standard '
CMOS, as well as the capability to drive 10 LS-TTL loads.
•
•
•
•
•
•
The 54HC174HC logic family is functionally and pinout compatible with the standard 54LS174LS logic family. All inputs
are protected from damage due to static discharge by internal diode clamps to Vee and ground.
Typical propagation delay: 13 ns
Wide power supply range: 2-6V
Low quiescent current: 20 /LA maximum (74HC Series)
Low input current: 1 /LA maximum
Fanout of 10 LS-TTL loads
Typical hysteresis voltage: 0.9V at Vcc=4.5V
Connection and Schematic Diagrams
Dual-In-Llne Package
TLlF/Sl0S-l
Top View
Order Number MM54HC14J or MM74HC14J,N
See NS Package J14A or N14A
Vee
A
TL/F/Sl0S-2
3-31
Absolute Maximum Ratings (Notes 1 & 2)
-0.5 to +7.0V
.. Supply Voltage (Vee>
DC Input Voltage (V,N)
-1.5toVee+ 1.5V
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
±20mA
Clamp Diode Current (1,K, lOr<>
±25mA
DC Output Current, per pin (lOUT)
±:;OmA
DC Vee or GND Current, per pin (Ice>
Storage Temperature Range (TSTG)
- 65'C to + 150'C
Power Dissipation (Po) (Note 3)
500mW
Lead Temp, (T rJ (Soldering 10 seconds)
260'C
Operating Conditions
Supply Voltage (Vee>
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Min
2
Max
6.
Units
V
0
Vee
V
:-40
-55
+85
+125
'C
'C
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25'C
VT-
VH
VOH
Positive Going
Threshold Voltage
Negative GOing
Threshold Voltage
Hysteresis Voltage
Minimum High Level
Output Voltage
liN
Maximum Low Level
Output Yoltage
Maximum Input
Current
Units
Minimum
2.0V
4.5V
6.0V
1.2
2.7
3.2
1.0
2.3
2.7
1.0
2.3
2.7
1.0
2.3
2.7
V
'V
V
Maximum
2.0V
4.5V
6.0V
1.2
2.7
3.2
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
Minimum
2.0V
4.5V
6.0V
,0.7
1.8
2.2
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V.
Maximum'
2.0V
4.5V
6.0V
0.7
1.8
2.2
1.0
2.2
2.7
1.0
2.2
2.7
1.0
2.2
2.7
V
V
V
Minimum
2.0V
4.5V
6.0V
0.5
0.9
1.0
0.2
0.4
0.6
0.2
0.4
0.6
0.2
0.4
0.6
V
V
V
Maximum
2.0V
4.5V
6.0V
0.5
0.9
1.0
1.2
2.25
3.0
1.2
2.25
3.0
1.2
2.25
3.0
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIH
IIOUTI=4.0 mA
IIOUTI=5.2 mA
4.5V
6.0V
0.2
0.2
0.26,
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VccorGND
6.0V
±0.1
±1.0
±1.0
",A
VIN=V,L
IIOUTI=20 ",A
VIN=VIL
IIOUTI=4.0 inA
IIOUTI = 5.2 mA
VOL
54HC
TA= -55 to 125'C
'Guaranteed Limits
TyP.
VT+
74HC
TA=-40toIi5'C
VIN=VIH
IIOUTI=20 ",A
V
V
I
\
V
V
V
Maximum Quiescent
40
2.0
20
VIN=Vee or GND 6.0'\,\
",A
Supply Current
IOUT=O",A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic UN" package: -12 mWI'C from 65'C to 85"C; ceramic "J" package: -12 mW/'C from 1OO'C to 125'C.
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH. and Vou occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at Vcc= 5.5V and 4.5V respectively. (The VIH value at 5.5V Is 3.85V.) The worst case leakage current (liN.
Ice. and loz) occur for CMOS at the higher voltage and so the 6.0V values should be used.
Icc
3-32
AC Electrical Characteristics
I
Symbol
I
I
Parameter
J
tpHL. tpLH
Vee=5V. T,,=25"C. CL =15 pF. t r =t,=6 ns
Maximum Propagation Delay
AC Electrical Characteristics
Symbol
Parameter
Conditions
I
Typ
L
12
I
Guaranteed Limit
J
22
I
L
Units
ns'
Vee = 2.0V to 6.0V. CL = 50 pF. tr= tf= 6 ns (unless otherwise speCified)
Conditions
74HC
TA= -40 to 85"C
TA=25"C
Vee
Typ
54HC
TA= -55to 125"C
Units
Guaranteed Limits
tpHL. tpLH
Maximum Propagation
Delay
2.0V
4.5V
6.0V
60
13
11
125
25
21
156
31
26
188
38
32
ns
ns
ns
tTLH. tTHL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
CPO
Power Dissipation
CapaCitance (Note 5)
(per gate)
Maximum Input Capacitance
CIN
Note 5: CPO determines the no load dynamic power consumption, Po
CPO Vee 1+lcc.
27
pF
5
10
10
= Cpo Vee!- 1+ lee
10
Vee, and the no load dynamic current consumption, Is
Typical Performance Characteristics
Propagation Delay vs
Power Supply
Input Threshold, VT+, VT-,
vs Power Supply Voltage
4.0
40
E:
~
3.0
'"'
Ii
v,.~
9
co 2.0
'"
t3
......'"'"
1.0
E
"...
<::
~
/ -'" Yr-
!
./
~
30
ill
~
zco
20
~
10
~
:/:.
",-
lIE
0
0
2.0
3.0
4.0
5.0
6.0
"
1"'-~
2.0
3.0
4.0
5.0
6.0
POWER SUPPLY VOLTAGE (V)
POWER SUPPLY VOLTAGE (V)
TL/F/51 05-4
TL/F/51 05-3
Typical Applications
Low Power Oscillator
R
Vee
v,. ~~,
:/lflf~
MM54Cf4/MM7CC14
-'-c
~
V,.
0
TL/F/5105-5
"
tl"'RCln VT+
I
VT-
t2"'RCln Vee-VTVee-VT+
I'"
veemrL
1
-
RCln VT+(Vee-VT-)
VT- (Vee VT+)
12"'-
-I,
0
Note: The equations assume 11 +12»tpdO+lpdl
VOUT
V$
I
TLlF/5105-6
3-33
pF
=
o
C"I
(.)
....
.....
::J:
:E
:E
r----------------------------------------------------------------------,
.'
~ Semiconductor
~National
----
\
j
microCMOS
~ MM54HC20/MM14HC20
(.)
::J:
.... Dual 4-lnput NAND Gate
&I)
:E
:E
General Description
Features
These NAND gates utilize microCMOS Technology, 3.5 micron silicon gate P-Well CMOS, to achieve operating
speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits. All gates
have buffered outputs. All devices have high noise immunity
and the ability to drive 10 LS-TTL loads. The 54HC/74HC
logiC family is functionally as well as pin-out compatible with
the standard 54LS174LS logic family. All inputs are,protected from damage due to static discharge by internal diode
clamps to Vee and ground.
•
•
•
•
•
Typical propagation delay: 12 ns
Wide power supply range: 2-6V
Low quiescent current: 20 p.A maximum (74HC Series)
'Low input current: 1 p.A maximum
Fanout of 10 LS-TTL loads
Connection and Logic Diagrams
Dual-In-Line Package
VCC
02
C2
14
13
12
1
2
3
A1
81
HC
HC
82
A2
Y2
8
4
C1
5,
01
6
Y1
7
GND
Top View
Order Number MM54HC20J or MM74HC20J, N
See NS Package J14A or N14A
TL/F/5299-2
3-34
TLlF/5299-1
Absolute Maximum Ratings (Notes 1 & 2)
-0.5 to +7.0V
Supply Voltage {Veel
DC Input Voltage (V,N)
-1.5 to Vee + 1.5V
DC Output Voltage (Vour)
-0.5toVc:;e+ 0.5V
±20mA
Clamp Diode Current {1,K. loKl
DC Output Current. per pin (lour)
±25mA
DC Vee or GND Current. per pin {Ieel
±50mA
Storage Temperature Range (TSTG)
-65'Cto +150'C
Power Dissipation (PD) (Note 3)
500mW
Lead Temp. {Tt.l (Soldering 10 seconds)
260'C
Operating Conditions
Supply Voltage {Vee>
DC Input or Output Voltage
(V,N. Vour)
Operating Temp. Range {TAl
MM74HC
MM54HC
Min
2
Max
6
Units
,V
0
'Vee
V
+85
+125
·C
'C
1000
500
400
ns
ns
ns
-40
-55
Input Rise or Fall Times
Vee=2.0V,
(tr• tl)
Vee=4.5V
Vee=6.0V
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25'C
Typ
74HC
TA=-40t085'C
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
V,H
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
V,L
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH'
Minimum High Level
Output Voltage
V,N=V,H orV,L
llourl ,,;20 p.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
V'N=V'H
IloUTI";4.0 rnA
llourl ,,; 5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
V,N=VeeorGND
6.0V
±0.1
±1.0
±1.0
p.A
V'N=V'H orV,L
Ilourl";4.0 mA
Ilourl,,;s.2 mA
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
V'N=V'H
Ilourl";20p.A
i
Maximum Quiescent V,N=VeeorGND 6.0V
2.0
20
40
p.A
Supply Current
lour=Op.A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specnied all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mW'oC from 65"C to 85°C; ceramic "J" package: -12 mW'oC from 100"C to 125°C.
Note 4: For a power supply of SV ±10% the worst case oulput voltages (YOH. and VoLl occur for He aI4.SV. Thus the 4.SV values should be used when
designing wHh this supply. Worst case VIH and VIL occur at Vee = 5,SV and 4.5V respectively. (The VIH value at 5,SV Is 3.8SV.) The worst case leakage current (liN.
Icc. and lez) occur lor CMOS at the higher voltage and so the 6.0V values should be used.
Icc
3·35
AC Electrical Characteristics Vcc = 5V, TA=25°C,CL =15 pF,t,.=tf=6 ns
Symbol
Parameter
.
Conditions
Maximum Propagation
Delay
tpHL, tpLH
Typ
Guaranteed
Limit
Units
8
15
ns
"
AC Electrical Characteristics Vcc= 2.0V to 6.0V, CL = 50 pF, tr=tf= 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25"C
Vee
Typ
Maximum Propagation
Delay
2.0V
4.5V
6.0V
trLH, tTHL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
CPO
Power Dissipation
Capacitance (Note 5)
tPHL, tpLH
,
(per gate)
,
74HC
TA=-40to85"C
54HC
TA= -55 to 125°C
Units
Guaranteed Limits
45
9
8
90
18
, 15
113
23
19
30
8
7
75
15
13
95
19
16
,
134
27
23
ns
ns
ns
110
22
19
ns
ns
ns
20
pF
Maximum Input
10
10
5
10
pF
Capacitance
Note 5: CpO detennlnes I~e no load dynamic power consumption, Po = Cpo Vcr;2 f+ lee Vee. and the no load dynamic ClJrreni consumption. Is = Cpo Vee f+ lee.
CIN
\
'-
/
-
3-36
r-------------------~------~------------------------__,~
~
CI1
~National
::c
""
~ Semiconductor
microCMOS
fJ
.....
.....
~
MM54HC27/MM74HC27
~
.....
Triple 3-lnput NOR Gate
::c
""
o
I\)
General Description
Features
These NOR gates utilize microCMOS Technology, 3.5 micron silicon gate P-well CMOS, to achieve operating speeds
similar to LS-TTL gates with the low power consumption of
standard CMOS integrated circuits. All gates have buffered
outputs, providing high noise immunity and the ability to
drive 10 LS-TTL loads. The 54HC174HC logic family is functionally as well as pin-out compatible with the standard
54LS174LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to Vee
and ground.
•
•
•
•
.....
Typical propagation delay: 8 ns
Wide operating supply voltage range: 2-6V .
Low input current: < 1 p.A
Low quiescent supply current: 20 p.A maximum
(74HC Series)
• Fanout of 10 LS-TTL Loads
Connection and Logic Diagrams
VCC
Dual-In-Line Package
Y1
C3
83
C1
13
14
12
A3
Y3·
11
•
1
A1
2
81
3
A2
4
5
82
C2
Y2
GND
TLiF/S300-1
Top View
Order Number MM54HC27J or MM74HC27J,N
See NS Package J14A or N14A '
A-I>C_.,
Y=A+B+C
......-:--I
B-~_
)D---D-- Y
c~I>o-"'"
(1013)
3-37
TLiF/S300-2
--
Absolute Maximum Ratings (Notes l' & 2)
Supply Voltage (Vee>
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K, 10Kl
DC Output Current, per pin (lOUT)
DC Vcc or GND Current, per pin (ICC)
Storage Temperature Range (TSTG) ,
Power Dissipation (Po) (Note 3)
Lead Temperature (Tu
(Soldering 10 seconds)
Operating ConditiQns
-0.5 to +7.0V
-1.5toVcc+ 1.5V
-0.5 to Vee + 0.5V
±20mA
±25mA
±50mA
- 65·C to + 150·C
500 mW,
DC Input or Output Voltage
(VIN,VOUT)
Operating Temp. Range (TAl
MM74HC
MM54HC
Parameter
260·C
Vee
' Conditions
0
-40
-55
Input Rise or Fall TImes
Vee=2.0V
(t" ttl
Vee=4.5V
Vee=6.0V
DC Electrical Characteristics (Note 4)
Symbol
Min
2
Supply Voltage (Vcc)
,
TA=25·C
Typ
74HC
TA= -40t085"C
Max
6
.
Units
V
Vee
V
+85
+125
·C
·C
1000
500
400
ns
ns
ns
54HC
TA= -55 to 125"C
Units
Guaranteed Umlts
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.11
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN=VIL
IIOUTI::::20 /LA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V ,
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIHorVIL
IIOUTI::::4.0 mA
IIOUTI :::: 5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VccorGND
6.0V
±0.1
±1.0
±1.0
/LA
VIN=VIL
l!ouTI::::4.0 mA
IIOUTI::::5.2 mA
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
VIN = VIH or VIL
IIOUTI ::::20 /LA
Maximum Quiescent VIN=VCC or GND 6.0V
40
2.0
20
/LA
Supply Current
10UT=0/LA
Note 1: Absolute Maxtmum Ratings are those values beyond which damage \0 the device may occur.
Note 2: Unless otherwise specified all voltage. are referenced \0 ground.
Note 3: Power Dissipation tempereture derating - plastic UN" package: -12 mWrC from 65"C to 85"C; ceramic uJ" package: - t 2 mWI'C from 100',C \0 t 25"C..
Note 4: For a power supply of SV ± 10% the worst case oulput voltages (VOH. and Vou occur for HC at 4.SV. Thus the 4.SiI values shOuld be used when designing
with this supply. Worst case VIH and VIL occur at VCC= S.SV and 4.SV respectively. (The VIH value at S.SV is 3.8SV.l The worst case leakage current (liN. Icc. and
lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
Icc
-
,
,.
3-38
-
AC Electrical Characteristics Vcc=5V. TA=25'C. CL =15 pF. t,.=tf=6 ns
Symbol
Parameter
tpHL. tpLH
Maximum Propagation
Delay
Conditions
Typ
Guaranteed
Limit
Units
8
15
ns
AC Electrical Characteristics Vcc=2.0V to 6.0V. CL =50 pF. t,.=tf=6 ns (unless otherwise specified)
Symbol
Parameter
Vee
C~ndltlons
74HC
TA= -40 to 8S'C
TA=2S'C
Typ
S4HC
TA= -SSto 12S'C
Units
Guaranteed LImIts
tpHL. tpLH
Maximum Propagation
Delay
2.0V
4.5V
6.0V
45
9
8
90
18
15
113
23
19
134
27
23
ns
ns
ns
tTLH. tTHL
Maximum Output Rise
and F8I1 Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
CPO
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input
Capacitance
(per gate)
36
5
pF
10
10
10
pF
Note 5: CPO determines the no losd dynamic power consumption. Po = Cpo Vee:!- 1+ ICC Vcr;. and the no load dynamiC current consumption, Is = Cpo Vcc 1+ ICC'
,
..
.
3-39.
-
~National
~ Semiconductor
microCMOS
MM54HC30/MM74HC30 a-Input NAND Gate'
General Description
Features
This NAND gate utilizes microCMOS Technology, 3.5 micron silicon gate P-well CMOS, to achieve operating speeds
similar to LS-TTL gates with the low power consumption of
standard CMOS integrated circuits. This device has high
noise immunity and the ability to drive 10 LS-TTL loads. The
54HC/74HC logic family is functionally as well as pin-out
compatible with the standard 54LS/74LS logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to Vee and ground.
•
•
•
•
•
Typical propagation delay: 20 ns
Wide power supply range: 2-6V
Low quiescent current: 20 ",A maximum (74HC Series)
Low input current: 1 ",A maximum
Fanout of 10 LS-TTL loads
Connection and Logic Diagrams
Dual-In-Line Package
vee
114
NC
G
H
113
12
NC
11
110 '
1
1
2
B
3
c
5
4
D
E
8
9
r;
A
y
NC
)0-
18
F
17
GND
TL/F/5133-1
Top View
Order Number MM54HC3OJ or MM74HC30J, N
See NS Package J14A or.N14A
D
--,,,,,-r--
')0--"'000---
Y
Y=ABCDEFGH
E-,-"'....,..........
F --'""'~--
H--'·--......,TL/F/5133-2
3-40
Abs~lute Maximum Ratings (Notes 1 & 2)
-0.5 to + 7.0V
Supply Voltage (Veel
DC Input Voltage (VIN)
-1.5 to Vee+ 1.5V
DC Output Voltage (Your)
-0.5 to Vee+0.5V
Clamp Diode Current (leo)
±20mA
DC Output Current, per pin (lour)
±25mA
±50mA
DC Vee or GND Current, per pin (Ieel .
-65'Cto + 150'C
St9rage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
500mW
Lead Temp. (TtJ (Soldering, 10 seconds)
260'C
Operating Conditions
DC Supply Voltage (Veel
DC Input or Output Voltage
(YIN, Your)
Operating Temp. Range (TA)
MM74HC
MM54HC
Min
2
Max
6
Units
V
0
Vee
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
Input Rise/Fall Times
Vee=2.0V
(tr' ttl
Vee=4.5V
Vee=6.0V
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
TA=25'C
Vee
Typ
74HC
TA= -40 to 85'C
54HC
TA = -55 to 125'C
Units
Guaranteed Limits
VIH
Minimum High Level Input
Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level Input
Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level Output
Voltage
VIN=VIHorVIL
!lourl';;;20 IJ.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIH
Ilourl';;;4mA
Ilourl';;;5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VCCorGND
6.0V
±0.1
±1.0
±1.0
IJ.A
VIN = VIH or VIL
Ilourl';;;4.0 mA
Ilourl';;;5.2 mA
VOL
Maximum Low Level Output
Voltage
VIN=VIH
Ilourl';;;20lJ.A
c
liN
Maximum Input Current
Maximum Quiescent Supply VIN=VeeorGND 6.0V
2.0
20
40
IJ.A
Current
lour=OIJ.A
Note 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to. ground.
Note 3: Power DIssipation temperature derating - plastic "N" package: -12 mW I'C from 6S'C to 8S'C; ceramic "J" package: -12 mWI'C from 100'C to 12S'C.
Note 4: For a power supply of SV ± 10% the worst case output voltages (VOH. and VoLl occur for HC at 4.SV. Thus the 4.SV values should be used when designing
with this supply. Worst case VIH and VIL occur at Vcc=S.SV and 4.SV respectively. (The VIH value at S.SV is 3.8SV.) The worst case leakage current (lIN. IcC. and
10V occur for CMOS at the higher voltage and so the 6.0V values should be used.
Icc
3·41
•
AC Electrical Characteristics Vcc=5V, TA=25°C, CL =15 pF, tr =tf=6 ns
Symbol
Parameter
Conditions
tpHL, tpLH
Maximum Propagation Delay
Typ
Guaranteed
Limit
Units
20
30
ns
AC Electrical Characteristics Vcc= 2.0V to 6.0V, CL = 50 pF, t,= tf= 6tns (unless otherwise specified)
Symbol
Parameter
Conditions
Vcc
TA=25°C
Typ
tpHL, tpLH
trLH, trHL
Maximum Propagation
Delay
Maximum Output
, Rise and FaU
Time
CPO
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input
Capacitance
74HC
TA= -40,t085"C
54HC
TA= -55 to 125°C
2.0V
4.5V
6.0V
66
23
18
160
35
30
190
42
36
220
49
42
ns
ns
ns
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
34
5
-,
Units
Guaranteed Limits
pF
10
10
10
pF
Note 5: Cpo detennlnes the no loed dynamic power consumption. Po= CPO Vee!- f+ Icc Vee. and the no load dynamic current consumption, Is = CpO Vee f+ Icc.
I
\
~
,
-
3·42
.-----------------------------------------~----------I~
~
~National
UI
\
~ Semiconductor
J
microCMOS
~
:x:
Features
These OR gates utilize microCMOS Technology, 3.5 micron
silicon gate P-well CMOS, to achieve operating speeds similar to LS-TIL gates with the low power consumption of standard CMOS integrated circuits. All gates have buffered outputs, providing high noise immunity and the ability to drive
10 LS-TIL loads. The 54HC174HC logic family is functionally as well as pin-out compatible with the standard 54LS/
74LS logic family. All inputs are protected from damage due
to static discharge by internal diode clamps to Vee and
ground.
•
•
•
•
•
o
c.:I
1\0)
Typical propagation delay: IOns
Wide power supply range: 2-6V
Low quiescent current: 20 /LA maximum (74HC Series)
Low input current: 1 /LA maximum
Fanout of 10 LS-TIL loads
Connection and Logic Diagrams
Dual-In-Line Package
A4
V4
B3
. A3
B2
V2
11
3
AI
Bl
1\0)
~
......
General Description
B4
oc.:I
.....
~
MM54HC32/MM74HC32
Quad 2-lnpu,t OR Gate
Vee
~
:x:
VI
7
A2
GND
TLlF/5132-1
Top View
Order Number MM54..,C32J or MM74HC32J,N
See NS Package J 14A or N14A
Y=A+B
A
V
B--I>C~--
TL/F/5132-2
3-43
Absolute Maximum Ratings
Operating Conditions
Supply Vo!tage (Veel
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K. 10Kl
DC Output Current. per pin (lOUT)
DC Vee or GND Current. per pin (Ieel
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
Lead Temperature (Tu
(Soldering 10 seconds)
S.upply Voltage (Veel
DC Input or Output Voltage
(VIN. VOUTj
Operating Temp. Range (TAl
MM74HC
MM54HC
Input Rise or Fall Times
(tr• tf}
Vee=2.0V
Vcc=4.5V
Vee=6.0V
(Notes 1 & 2)
-0.5 to + 7.0V
-1.5 to Vee + 1.5V
-0.5 to Vee+0:5V
±20mA
±25mA
±50mA
-65·Cto + 150·C
500mW
260·C
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
\
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vcc
74HC
TA= -40 to 8S·C
TA=25·C
Typ
S4HC
TA=-SSt012S·C
Units
Gua,ranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low.Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
!IOUT!';;;20 p.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.7
5.2
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIL
!IOUT!';;;4.0 mA'
!IOUT!';;;5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VccorGND
'B.OV
±0.1
±1.0
±1.0
p.A
VIN = VIH or VIL
!IOUT!';;;4.0 mA
!IOUT!';;;5.2 mA
VOL
liN
Maximum Low. Level
Output Voltage
Maximum Input
Current
VIN=VIL
!IOUT!';;;20 p.A
Maximum Quiescent VIN = Vee or GND 6.0V
20
2.0
40
",A
Supply Current
10UT=0",A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all' voltages are referenced to ground.
Nole 3: Power Dissipation temperature derating - plastic "N" package: -12 mWrc from 65"C to 85"C; ceramic "J" package: -12 mW/"C from 100"C to 125"C.
Note 4: For a power supply of 5V ± 10% the worst case output voltages (VOH. and VoLl occur for HC at 4.5V. Thus the 4,5V values should be used when
designing with this supply. Worst case VIH and VIL occur at Vce=5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V,) The worst case leakage current (liN.
Ice. and lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
Icc
"
/
3-44
AC Electrical Characteristics Vcc=5V, TA=25'C, CL = 15 pF, tr =tf=6 ns
Symbol
Parameter
tpHL, tpLH
Maximum Propagation
Delay
Conditions
Typ
Guaranteed
Limit
Units
10
18
ns
-
AC Electrical Characteristics
Vcc=2.0V to 6.0V, CL =50 pF, tr =tf=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=25'C
Typ
74HC
TA=-40t085'C
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
tpHL, tpLH
' Maximum Propagation
Delay
2.0V
4.5V
6.0V
30
12
9
100
20
17
125
25
21
150
30
25
ns
ns
ns
trLH, trHL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
ns
ns
ns
CPO
Power Dissipation
Capacitance (Note 5)
GIN
Maximum Input
Capacitance
(per gate)
22
19
50
5
pF
10
10
10
pF
Nole 5: cpo determines the no load dynamic power consumption, Po= CPO Vcr:!- f+ lee Vee. and the no load dynamic current consumption. IS = Cpo Vee f+ Icc;.
•
I
I
3·45
N .-----~----------------------------------------------------~---------------,
"'II'
o
:::E:
~
:E
:E
'.
~ Semiconductor
~National
~ MM54HC42/MM74HC42
:::E:
"'II'
BCD-to-Decimal Decoder
o
It)
:E
:E
General Description
This decoder utilizes microCMOS Technology, 3.5 micron
silicon gate P-well CMOS. Data on the four input pins select
one of the 10 outputs corresponding to the value of the BCD
number on the inputs. An output will go low when selected,
otherwise it remains high. If the input data is not a valid BCD
number all outputs will remain high. The circuit has high
noise immunity and low power consumption usually associated with CMOS circuitry, yet also has speeds comparable
to low power Schottky TTL (LS-TTL) circuits, and is capable
of driving 10 LS-TTL equivalent loads.
Connection Diagram
All inputs are protected frpm damage due to static discharge by diodes to Vee and ground.
Features
•
•
•
•
Typical propagation delay: 15 ns
Wide supply range: 2V -6V
Low quiescent current: 80 ".A (74HC)
Fanout of 10 LS-TTL loads
Truth Table
Dual-In-line Package
INPUTS
Vee
116
A
15
C.
B
14
D
12
13
9
11
10
I
9
P-
r<
2
3
4
o
5
4
7
6
6
~------~--------~
OUTPUTS
Inputs
No.
OUTPUTS
I
18
GND
TUF/5301-1
Top View
Order Number MM54HC42J or MM74HC42J, N
See NS Package J16A or N16E
Outputs
D C B A 0
1 2 3 4 5 6 7
8 9
0
1
2
3
4
L
L
L
L
L
L
L
L
L
H
L
L
H
H
L
L
H
L
H
L
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
5
6
7
B
9
L
L
L
H
H
H
H
H
L
L
L
H
H
L
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
INVALID
H
H
H
L
L
H
H
H
H
H.
H
L
L
H
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H = High Level, L = Low Level
Logic Diagram
TUF/5301-2
3-46
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
-0.5 to + 7.0V
Supply Voltage (Vee>
. DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K. 10K)
DC Output Current. per pin (lOUT)
DC Vee or GND Current. per pin (Ice>
Storage Temperature Range (TSTG)
-1.5 to Vee + 1.5V
Supply Voltage (Vee>
-0.5 to Vee+0.5V
±20mA
±25mA
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
±50mA
-65'C to + 150'C
Power Dissipation (Po) (Note 3)
Lead Temp. (TO (Soldering 10 seconds)
Min
2
'Max
6
Units
V
0
Vee
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
(t,-.ttl
Vee=2.0V
Vee=4.5V
Vee,,=6.0V
500mW
260'C
DC Electrical Characteristics (Note·4)
Symbol
Parameter
Conditions
Vee
TA=2S'C
74HC
TA= -40 to 8S'C
S4HC
TA= -55 to 125'C
Units
Guaranteed Limits .
Typ
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
Vil
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN= VIH or Vil
IIOUTI:S:20 ",A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIH orVll
IIOUTI:S:4.0 rnA
IIOUTI:S:5.2 rnA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = Vee or GND
6.0V
·±0.1
±1.0
±1.0
",A
VIN = Vee or GND
IOUT=O",A
6.0V
8.0
80
160
",A
VIN = VIH or Vil
IIOUTI:S:4.0 rnA
liOUTI :S: 5.2 rnA
VOL
liN
Icc
Minimum Low Level
. Output Voltage
Maximum Input·
Current
Maximum Quiescent
. Supply Current
VIN = VIH or Vil
IIOUTI:S:20 ",A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Nole 2: Unless otherwise specified all voltages are referenced to ground.
Nole 3: Power Dis,sipation temperature derating - plastic "N" package: -12 mWI'e from 6S'C to 6S'C; ceramic "J" package: -12 mWI'C from 100'C to 12S'C.
Nola 4: For a power supply of SV ± 10% the worst case output voltages (VOH. and VoLl occur for HC at 4.SV. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at Vcc= 5,5V and 4,SV respectively. (The VIH value at S.SV is 3,6SV.) The worst case leakage current (lIN.
Icc. and loz) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3-47
AC Electrical Characteristics Vcc=5V. TA=25"C. CL=15 pF. t r =tf=6ns
Symbol
Parameter
Condition!!
tpHL. tpLH
Maximum Propagation
Delay
Typ
Guaranteed
Limit
Units
15
25
ns
AC Electrical Characteristics Vee = 2.0V to 6.0V. CL = 50 pF. t, = tf = 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=25"C .
Typ
74HC
TA=-40to85"C
54HC
TA= -55 to 125"C
Units
Guaranteed Limits
tpHL. tpLH
Maximum Propagation
Delay
2.0V
4.5V
6.0V
75
17
15
150
30
26
189
38
32
224
45
38
ns
ns
ns
tTLH. tTHL
Maximum Output Rise
and Fall Time
,
2.0V
4.5V
6.0V
30
8
. 7
75
15
13
95
19
16
110
22
19
ns
ns
ns
CPO
Power Dissipation
Capacitance (Note 5)
CIN
(per package)
Maximum Input
"Capacitance
pF
5
10
10
10
pF
Note 5: CpO determines the no load dynamic power consumption. Po = Cpo Vcc21+ Icc Vee. and the no load dynamic current consumption. Is = Cpo Vee 1+ lee.
,
3-48
~National
PRELIMINARY
\
.~ Semiconductor
MM54HC51/MM74HC51
Dual AND-OR-Invert Gate
MM54HC58/MM74HC58 Dual AND-OR Gate
General Description
Features
These gates utilize microCMOS Technology, 3.5 micron silicon gate P-well CMOS, to achieve operating speeds similar
to LS-TTL gates with the low power consumption of standard CMOS integrated circuits. All gates have buffered outputs, providing high noise immunity and the ability to drive
10 LS-TTL loads. The 54HC174HC logic family is functionally as well as pin-out compatible with the standard 54LS/
74LS logic family. All inputs are protected from damage due
to static discharge by internal diode clamps to Vee and
ground:
• Typical propagation delay: 10 ns
• Wide power supply range: 2-6V
• Low quiescent supply current: 20 ".A maximum
(74 Series)
• Low input current: 1 ".A maximum
• High output current: 4 mA minimum
Connection Diagrams
Vcc
Dual-In-Line Package
C1
81
F1
E1
01
Y1
8
7
A1
A2
82
C2
02
Y2
GNO
TL/F/5302-1
Top View
Order Number MM54HC51J or MM74HC51J, N
See NS Packages J14A or N14A
Dual-In-Llne Package
VCC
C1
B1·
F1
E1
01
Y1
8
A1
A2
B2
C2
02
Y2
Top View
Order Number MM54HC58J or MM74HC58J, N
See NS Packages J14A or N14A
3-49
")
microCMOS
TL/F/5302-2
Absolute Maximum Ratings
Operating Conditions
(Notes 1 & 2)
Supply Voltage (Vee)
-0.5 to + 7.0V
DC Input Voltage (VIN)
-1.5 to Vce+1.5V
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
'±20mA
Clamp Diode Current (11K. 10K>
, ±25mA
DC Output Current. per pin (lOUT)
±50mA
DC Vee or GND Current. per pin (Ice>
- 65·C to + 150·C
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
500mW
260·C
Lead Temp. (TL> (Soldering 10 seconds)
Supply Voltage (Vee>
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Min
2
Max
6
Units
V
0
Vee
V
-40,
-55
+85
+125
·C
·C
·1000
500
400
ns
ns
ns
Input Rise or Fall Times
Vee=2.0V
(tr• ttl
Vee=4.5V
Vee=6.0V
DC Electrical Characteristics (Note 4)
,.Symbol
Parameter
Conditions
Vee
TA=25·C
Typ
74HC
TA= -40 to 85·C
54HC
TA= -55 to 125·C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Lev'!'l
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
IIOUTI~20 ",A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V.
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
O.
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIH orVIL
IIOUTI~4.0 mA
IIOUTI ~ 5.2 mA
4.5V
6.0V
0.2
0:2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VI'N=VeeorGND
6.0V
±0.1
±1.0
±1.0
",A
VIN = VIH or VIL
IIOUTI~4.0 mA
IIOUTI~5.2 mA
VOL
Maximum Low Level
Output Voltage
.
liN
Maximum Input
Current
VIN = VIH or VIL
IIOUTI~20 ",A
Maximum Quiescent VIN=VeeorGND
6.0V
2.0
20
40
",A
Supply Current
10UT=0",A
Note 1: Absolute Maximum Ratings are those values beyond which damage Ie the device may occur.
Note 2: Unless otherwise specified all voltages are referenced Ie ground.
Note 3: Power Dissipation temperature derating - plastic UNO. package: -12 mWI'e from 6S'C to 8S'C; ceramic uJu package: -12 mWI'C from 1OO'C to 125"C,
Note 4: For a power supply of SV ± 10% the worst case output voltages (YaH. and Vall occur for HC at 4.SV, Thus the 4,SV values should be used when deSigning
with this supply. Worst case VIH and VIL oocur at VCC~5,5V and 4.5V respectively. (The VIH value at S.SV is 3,85V.l The worst case leakage current (liN. Icc. and
lozl occur for CMOS at the higher voltage and so the 6,OV values should be used,
Icc
3-50
AC Electrical Characteristics Vcc=5V, TA=25'C, CL =15pF, t,=tf=6 ns
Symbol
Parameter
Conditions
tpHL, tpLH
Maximum Propagation
Delay
Typ
Guaranteed
Limit
Units
10
20
ns
AC Electrical Characteristics Vcc= 2.0V to 6.0V, CL = 50 pF, t,= tf= 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=25'C
Typ
74HC
TA= -40 to 85'C
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
tpHL, tpLH
Maximum Propagation
Delay
2.0V
4.5V
6.0V
63
'13
11
125
25
21
158
32
27
186
37
32
ns
ns
ns
tTLH, tTHL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
CPD
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input
Capacitance
(per AND-DR-Gate)
20
5
pF
10
10
10
pF
Note 5: CPO determines the no load dynamic power consumption, Po= CPO Vr;c21+ lee Vee. and the no load dynamic current consumption, Is = Cpo Vee 1+ lex;.
3-51
~ r---------------------------------------------------------------~----------__,
r-.
o
:::J:
'I:f'
r-.
:IE
:IE
.....
~National
-'J
\
microCMOS
~ Semiconductor
~_.../
~
~
r-.
o MM54HC73/MM74HC73
:::J:
'I:f'
II)
:IE
:IE
Dual J-K Flip-Flops with Clear
General Description
These J-K Flip-Flops utilize microCMOS Technology, 3.5
micron silicon gate P-well CMOS. They possess the high
noise immunity and low power dissipation of standard
CMOS integrated circuits. These devices can drive 10 LSTTL loads.
These flip-flops are edge sensitive to the clock input and
change state on the negative going transition of the clock
pulse. Each one has independent, J, K, CLOCK, and
CLEAR inputs and and outputs. CLEAR is independent
of the clock and accomplished by a low level on the input.
The 54HC/74HC logic family 'is functionally as well as pinout compatible with the standard 54LS/74LS logic family.
a
a
Connection and Logic Diagrams
All inputs are protected from damage Clue to static discharge by internal diode clamps to Vee and ground.
Features
.•
•
•
•
•
Typical propagation delay: 16 ns
Wide operating voltage range: 2-6V
Low input current: 1 /LA maximum
Low quiescent current: 40 /LA (74HC Series)
High output drive: 10 LS-TTL loads
Truth,Table
Dual-In-Llne Package ,
J1
CLK 1
01
CLR 1
K1
GND
Vec
Top View
K2
CLK 2
Inputs
02
CLR 2
Outputs
CLR
CLK
J
K
Q
Q
L
H
H
H
H
H
X
X
X
L
,l.
,l.
,l.
,l.
L
H
L
H
L
L
H
ao
H
00
L
H
X
H
X
H
L
H
TOGGLE
00
qo
J2
TL/F/5072-1
Order Number MM54HC73J orMM74HC73J, N
See NS Package J14A or N14A
Q
fill1m
K
CI:
CL
CLOCK~
CI:
T
TL/F/5072-2
3-52
CL
f
TL/F/5072-3
Absolute Maximum Ratings
Supply Voltage (VeC>
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K. 10K)
DC Output Current. per pin (lOUT)
DC Vee or GND Current. per pin (Icc>
Storage Temperature Range (T8TG)
Power Dissipation (Po) (Note 3)
Lead Temperature (Tu
(Soldering 10 seconds)
Operating Conditions
(Notes 1 & 2)
-0.5 to + 7.0V
-1.5 to Vee+ 1.5V
-O.51to Vee+0.5V
±20mA
±25mA
±50mA
-B5·C to + 150·C
500mW
Supply Voltage (VeC>
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Min
2
Max
6
Units
V
0
Vee
V
+85
+125
·C
·C
1000
500
400
ns
ns
ns
•
-40
-55
Input Rise or Fall Times
(tr• tf)
Vee=2.0V
Vee=4.5V
Vee=6.0V
260·C
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions '
Vee
TA=2S·C
74HC
TA= -40 to SS·C
Typ
54HC
TA= -55 to 125·C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
B.OV
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
O.~
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN=VIHorVIL
IIOUTI~20p.A
VIN = VIH or VIL
IIOUTI~4.0mA
IIOUTI~5.2 rnA
VOL
Maximum Low Level
Output Voltage
VIN=VIHorVIL
IloUTj~20 p.A
VIN = VIH or VIL
IIOUTI~4.0 rnA
ilOUTI ~ 5.2 rnA.
liN
Maximum Input
Current
VIN = Vee or GND
2.0V
4.5V
B.OV
2.0
4.5
B.O
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
B.OV
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
B.OV
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
4.5V
'B.OV
0.2
0.2
0.2B
0.2B
0.33
0.33
0.4
0.4
V
V
±0.1
±1.0
±1.0
p.A
40
80
p.A
B.OV
Maximum Quiescent VIN=VeeorGND B.OV
4.0
Supply Current
IOUT=Op.A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Icc
Note 2: Unless otherwise specified all Yoltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastiC "N" package: -12 mWI'C from 65'C to 85'C; ceramic"J" package: -12 mWI'C from 100'C to 125'C.
Note 4: For a power supply of 5V ± 10% the worst case output voltages (VOH, and VoLl occur for HC at 4.5,V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at Vcc=:5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (liN, Icc. and
lov occur for CMOS at the higher voltage and so the 6.0V values should be used.
..,
3·53
AC Electrical Characteristics Vcc=5V. TA=25°C.CL =15pF.tr=tf=6ns
Symbol'
Parameter
Conditions
Typ
Guaranteed Limit
Units
30
MHz
16
21
ns
Maximum Propagation
Delay Clear to Q or Q
21
26
ns
Minimum Removal TIme.
Clear to Clock
10
20
ns
Minimum Setup Time.
14
20
ns
-3
0
ns
10
16
ns
fMAX
Maximum Operating
Frequency
50
tpHL. tpLH
M~imum Propagation
Delay Clock to Q or Q
tpHL. tpLH
'REM
ts
tH
.
J or K to Clock
Minimum Hold Time
J or K to Clock
tw
Minimum Pulse Width.
Clock or Clear
AC Electrical Characteristics CL = 50 pF. tr = tf = 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=25°C
Typ
74HC
TA= -40 to 85°C
54HC
TA= -55 to 125°C
Units
Guaranteed Limits
fMAX
Maximum Operating
Frequency
2.0V
4.5V
6.0V
9
45
53
5
27
32
4
21
25
3
18
21
MHz
MHz
·MHz
tpHL. tpLH
Maximum Propagation
Delay Clock to Q or Q
2.0V
4.5V
6.0V
70
18
15
126
25
21
160
32
27
185
37
32
ns
ns
ns
tpHL. tpLH
Maximum Propagation
Delay Clear to Q or Q
2.0V
4.5V
6.0V
126
25
21
155
31
26
194
39
32
250
47
40
ns
ns
ns
tREM
Minimum Removal TIme
Clear to Clock
2.0V
4.5V
6.0V
55
11
9
100
20
17
125
25
21
150
30
25
ns
ns
ns
Minimum Setup Time
2.0V
4.5V
6.0V
77
15.4
13
100
20
17
125
25
21
150
30
25
ns
ns
ns
2.0V
4.5V
6.0V
-3
-3
-3
0
0
0
0
0
0
0
0
0
ns
ns
ns
80
16
14
·75
15
13
100
20
18
120
24
21
ns
ns
ns
95
19
16
110
22
19
ns
ns
ns
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
ts
tH
J or K to Clock
Minimum Hold TIme
J or K from Clock
,
tw
Minimum Pulse Width
Clock or Clear
2.0V
4.5V
6.0V
55
11
9
tTLH. trHL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
fr. tf
Maximum Input Rise and
Fall Time
2.0V
4.5V
6.0V
CPO
Power Dissipation
capacitance (Note 5)
(per flip·flop)
80
pF
,Maximum Input
10
10
10
pF
5
capaCitance
Note 6: Cpo determines the no loed dynamic power consumption. Po= Cpo Vex!- f+ ICC Vee. and the no load dynamic current consumption. Is = Cpo Vcc f+ Icc.
CIN
3·54
Typical Applications
N Bit Binary Ripple Counter with Enable and Reset
COUNTER ENABLE
RESET
!
...
~
Q
!
CLEAR
J~
~
!
CLEAR
Q
J~
~
Q
CLEAR
J~
'
Q
TO
NEXT BIT
K
CLOCK
Q
I--
K
CLOCK
Q
I--
K~
CLOCK
Y
Y
CLOCK
r
LSB
BIT 2
BIT 3
TL/F/S072-4
N Bit Shift Register with Clear
CLEAR
DATA
INPUT~
~
'J
!
CLEAR
Q
J
CLEAR
!
Q
J
CLEAR
Q
•••
~'
K
CLOCK
CLOCK
Q
K
CLOCK
Y
Y
Q
K
CLOCK
Q
r
TL/F/S072-S
3-55
~
.....
o
:c
~
.....
::::IE
::::IE
~
o
:c
~
an
::::IE
::::IE
r-------------------------------------------------------------------------,
~National
\
~ Semiconductor
J
microCMOS
MM54HC74/MM74HC74
Dual D Flip-Flop with Preset and Clear
General Description
The MM54HC74/MM74HC74 utilizes microCMOS Technology, 3.5 micron silicon gate P-well CMOS: to achieve operating speeds similar .to the equivalent LS-TTL part. It possesses the high noise immunity and low power consumption
of standard CMOS integrated circuits, along with the ability
to drive 10 LS-TTL loads.
This flip-flop has independent data, preset, clear, and clock
inputs and Q and Q outputs. The logic level present at the.
data input is transferred to the output during the positive-going transition of the clock pulse. Preset and clear are. independent of the clock and accomplished by a low level at the
appropriate input.
•
,.
•
•
•
Connection and Logic Diagrams
Truth Table
Vee
CLRZ
Dual-In-Line Package
PHZ
OZ
CLKZ
The 54HC174HC logic family is functionally and pinout compatible with the standard 54LS174LS logic family. All Inputs
are protected from damage due to static discharge by internal diode clamps to Vee and ground.
Features
Typical propagation delay: 20 ns
Wide power supply range: 2-6V
Low quiescent current: 40 ,..A maximum (74HC Series)
Low input current: 1 ,..A maximum
Fanout of 10 LS-TT~ loads
Inpute
QZ
ilz
Outpute
PR
CLR
CLK
D
Q
Q
L
H
L
H
L
L
H
H
H
X
X
X
X
X
X
H
L
X
H
L
HO
.H
L
·QO
L
H
HO
L
H
Ii
H
H
t
t
L
co
Note: QO= the level 01 Q before the indicated input cond~
tions were established.
.
• This configuration Is nonstsble; that Is, H will not persist
when preset and clear Inputs return to their Inactive (high)
level.
ClRl
01
ClKl
PHI
TOP VIEW
Ql
BNO
TLlF/S106-1
Order Number MM54HC74J or MM74HC74J, N
See NS Package J14A or N14A
DATA
TLlF/51D6-2
3-56
Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage (Vee)
-0.5 to +7.0V
DC Input Voltage (VIN)
-1.5toVee+ 1.5V
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
±20mA
Clamp Diode Current (11K. loKI
±25mA
DC Output Current. per pin (lOUT)
DC Vee or GND Current. per pin (Icc)
±50mA
-65·C to + 150·C
Storage Temperature Range (TSTG)
500mW
Power Dissipation (Po) (Note 3)
260·C
Lead Temp. (T L.l (Soldering 10 seconds)
Operating Conditions
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN. OUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
(tr• tf)
Vee = 2.0V
Vcc=4.5V
Vee=6.0V
Min
2
0
Max
6
Vcc
Units
V
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter,
Conditions
Vee
TA=25"C
Typ
74HC
TA=-40t085·C
54HC
TA= -55 to 125·C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage'
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3 '
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
IIOUTI:S::20 p.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.3
5.2
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
IIOUTI :S::4.0 mA
IIOUTI:S::5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VeeorGND
6.0V
±0.1
±1.0
±1.0
p.A
VIN = VIH or VIL
IIOUTI:S::4.0 mA
IIOUTI:S::5:2mA
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
VIN = VIH or VIL
IIOUTI:S::20 p.A
Maximum Quiescent· VIN=VeeorGND 6.0V
4.0
40
80
p.A
Supply Current
10UT=0p.A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specifled all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N"' package: -12 mW/'C from 6S"C to BS"C; ceramic "J"' package: -12 mW/'C from 1OO"C to 125"C.
Note 4: For a power supply of SV ± 1O%'lhe worst case output voltages (VOH. and VOLl occur for HC at 4.SV. Thus the 4.SV values should be used when designing
with this supply. Worst case VIH and VIL occur at Vcc= S.5V and 4.SV respectively. (The VIH value at5.5V is 3.B5V.) The worst case leakage current (liN. ICC. and
loil occur for CMOS at the higher voltage and so the 6,OV values should be used.
Icc
3-57
AC Electrical Characteristics
Symbol
.,
Vcc= 5V, TA;" 25·C, CL = 15 pF, tr=tl""6 ns
Parameter
Typ
Conditions
Guarimteed
limit
Units
fMAX
Maximum Operating
Frequency
50
• 30
tpHL, tpLH
Maximum Propagation
Delay Clock to Q or 0
16
30
ns
tpHL,tpLH
Maximum Propagation
Delay Preset or Clear to Q or 0
25
40
ns
tREM
Minimum Removal Time,
Preset or Clear to Clock
5
ns
ts
Minimum Setup Time
Data to Clock
20
ns
tH
Minimum Hold Time
Clock to Data
0
ns
tw
Minimum Pulse Width
Clock, Preset or Clear
16
ns
MHz
\
!i.c Electrical Characteristics CL =50 pF, tr=tj=6 ns (unless otherwise specified)
Symbol
Parameter
,
Conditions
Vee
Typ
fMAX
Maximum Operating
Frequency
tpHL, tpLH
Maximum Propagation
Delay Clock to Q or 0
2.0V
4.5V
6:0V
tpHL, tpLH
Maximum Propagation
Delay Preset Qr Clear
ToQorO
2.0V
4.5V
6.0V
tREM
Minimum Removal Time
Preset or Clear
To Clock
ts
tH
tw
TA=2S·C
S4HC
TA= -SSto 12S·C
Units
Guaranteed Limits
5
27
3.2
4
21
25
4
18
21
MHz
MHz
MHz
88
18
15
'175
35
30
221
44
37
261
52
44
ns
ns
ns
98
30..
230
46
39
290
58
49
343
69
58
ns
ns
ns
2.0V
4.5V
MV
25
5
.4
32
6
5
37
.7
6
ns
ns
ns
Minimum Setup Time
Data to Cl.ock
2.0V
4.5V
6.0V
100
20
126
25
21
149
30
25
ns
ns
ns
Minimum Hold Time
Clock to Data
2.0V
0
0
0
0
0
0
0
0
ns
ns
ns
.-
2.0V
4.5V
6.0V
74HC
TA=-40t08S·C
28
17
4.5V
6.0V
Minimum, Pulse Width
Clock, Preset or Clear
. ns
ns
ns
30
9
8
80
16
14
101
20
17
119
24
20
25
7
6
75
15
13
95
19
16
110
22
19
ns
ns
ris
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
tTLH, tTHL
Maximum Output
Rise and Fall Time
2.0V
4.5V
6.0V
t,., tj
Maximum Input Rise and
Fall Time
2.0V
4.5V
6.0V
CPO
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input
Capacitance
(per flip-flop)
b
2.0V
4.5V
6.0V
. pF
80
5
\
10
10
10
pF
Note 5: Cpo determines the no load dynamic power consumption, Po =Cpo vc;c2 f+ lee Vee. and the no load dynamic current consumption, Is = Cpo Vee f+ 100
3-58
~National
~ Semiconductor
MM54HC75/MM74HC75
4-Bit Bistable Latch with Q and Q Output
General Description
This 4-bit latch utilizes microCMOS Technology, 3.5 micron
silico!,! gate P-well CMOS. To achieve the high noise immunity and low power consumption normally associated with
standard CMOS integrated circuits. These devices can drive
10 LS-TTL loads.
This latch is ideally suited for use as temporary storage for
binary information processing, input! output, and indicatorunits. Information present at the data (0) input is transferred
output when the enable (G) is high. The
output
to the
will follow the data input as long as the enable remains high.
When the enable goes low, the information that was present
at the data input at the time the transition occurred is retained at the
output until the enable is permitted to go
high again.
a
a
a
Connection and Logic Diagrams
The 54HC174HC logic family is functionally as well as pinout compatible with the standard 54LS174LS logic family.
All inputs are protected from damage due to static dIscharge by internal diode clamps to Vee and ground.
Features
•
•
•
•
•
Typical operating frequency: 50 MHz
Typical propagation delay: 12 ns
Wide operating supply voltage range: 2-6V
Low input current: < 1 'fJoA
Low quiescent supply current 80 fJoA maximum
(74HC Series)
• Fanout of 10 LS-TTL loads
Truth Table
- Dual-tn-Line Package
10
20
2Q
ENABLE
1-2
GND
3a
30
Inputs
40
Outputa
D
G-
Q
Q
L
H
H
H
L
L
H
H
L
X
ao
00
H = High Level: L= Low Level
X
= Oon'l Care
00 = The level of 0 before Ihe transition of G
10
10
20 ENABLE
Vcc
3D
40
40
3-4
TOP VIEW
TLIF/5303-1
Order Number MM54HC75J or MM74HC75J, N
See NS Package J16A or N16E
(1 of 4 latches)
O~:::D--n
~---Q
G-
. . .-1;>0--,""'1
TO OTHER
LATCH
TL/F/530S-2
3-59
•
Absolute Maximum
Rating~ (Notes 1 & 2)
-
Operating Conditions
-0.5 to + 7.0V
Supply Voltage (Vee>
DC Input Voltage (VIN)
-1.5 to Vee + 1.5V
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
±20mA
Clamp Diode Current (11K. 10K>
±25rnA
DC Output Current. per pin (lOUT)
±50mA
DC Vcc or GND Current. per pin (Icc)
-65·C to + 150·C
Storage Temperature Range (fSTG)
Power Dissipation (Po) (Note 3)
500mW
Lead Temp. (fLl (Soldering 10 seconds)
260"C
Supply Voltage (Vee>
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (fA)
MM74HC
MM54HC
Input Rise or Fall Times
(tr. ttl Vcc=2.0V
VCC=4.5V
Vcc=6.0V
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
\
Symbol
Parameter
Conditions
Vee
TA=25·C
Typ
74HC
TA= -40 to 85·C
54HC
TA= -55 to 125"C
Units
Guaranteed Umita
VII:I
Minimum High Level
Input Voltage
2.0"
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
!IOUT!~20 p.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
'6.0V
4.2
5.7
3.98
5.48 .
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
- V
VIN = VIH or VIL
!IOUT! ~4.0 rnA
!IOUT! ~5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VeeorGND
6.0V
±O.1
±1.0
±1.0
p.A
VIN = VIH or VIL
!IOUT! ~4.0 rnA
!IOUT! ~ 5.2 mA
. VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
VIN = VIH or VIL
!IOUT!~20 ,...A
-
V
V,
Maximum Quiescent VIN=Vee or GND 6.0V
80
4.0
40
,...A
Supply Current
IOUT=O,...A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temparature derating - plastic "N" package: -12 mWre from 65·C to 8S·C; ceramic "J" package: -12 mWrC from 1OO"C to 12S·C.
Note 4: For a power supply of 5V ± 10% the worst case output voltages (YOH. and Vou occur for HC at 4.SV. Thus the 4.SV values should be used when designing
with this supply. Worst case VIH and VIL occur at Vcc= S.SV and 4.5V respectively. (The VIH value'atS.5V Is 3,85V.) The worst case leakage current (liN. Icc. and
IOZ> occur for CMOS at the higher voltage and so the 6.0V values should be used.
Icc
\,
3·60
AC Electrical Characteristics Vcc=5V, TA=25°C,CL =15pF, t,=t,,:,6ns
Typ
Guaranteed
Limit
Units
Maximum Propagation
Delay, Data to Q
14
23
ns
tpHL, tpLH
Maximum Propagation
Delay, Data to 0
10
20
ns
tpHL, tpLH
Maximum Propagation
Delay, Enable to Q
16
27
ns
tpHL, tpLH
Maximum Propagation
Delay, Enable to 0
11
23
ns
20
ns
0
ns
16
ns
Symbol
Parameter
tpHL, tpLH
Conditions
t8
Minimum Set Up Time
tH
Minimum Hold Time
tw
Minimum Pulse Width
-2
Ac Electrical Characteristics CL =50 pF, t,=t,=6 ns (unless otherwise specified)
Parameter
Symbol
Conditions
Vee
TA=2SoC
Typ
74HC
TA= -40 to 8SoC
S4HC
TA= -55 to 12SoC
Units
Guaranteed Limits
tpHL, tpLH
Maximum Propagation
Delay, Data to Q
2.0V
4.5V
6.0V
37
15
14
125
25
24
156
32
27
lBB
3B
32
ns
ns
ns
tpHL, tpLH
Maximum Propagation
Delay, Data to 0
2.0V
4.5V
6.0V
29
12
11
110
22
19
13B
2B
24
165
33
29
ns
ns
ns
tpHL, tpLH
Maximum Propagation
Delay, Enable to Q
2.0V
4.5V
6.0V
40
lB
16
145
29
25
lBl
36
31
21B
44
3B
ns
ns
ns
tpHL, tpLH
Maximum Propagation
Delay, Enable to 0
2.0V
4.5V
6.0V
36
15
14
125
25
22
156
31
2B
lBB
3B
33
ns
ns
ns
ts
Minimum Set Up Time
Data to Enable
2.0V
4.5V
6.0V
40
10
9
100
20
17
125
25
21
150
30
25
ns
ns
ns
tH
Minimum Hold Time
Enable to Data
2.0V
4.5V
6.0V
-10
-2
-2
0
0
0
0
0
0
0
0
0
ns
ns
ns
tw
Minimum Enable Pulse Width
2.0V
4.5V
6.0V
40
11
9
BO
16
14
100
20
lB
120
24
21
ns
ns
ns
trLH, tTHL
Maximum Output
Rise and Fall Time
2.0V
4.5V
6.0V
25
7
6
75
15
13
95
19.
16
110
22
19
ns
ns
ns
CPO
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input
Capacitance
I
(per commonly
clocked latched
pair)
pF
40
5
10
10
10
pF
Note 5: CPO determines the no load dynamic power consumption. Po = Cpo vcc2 1+ Icc Vee. and the no load dynamic current consumption. Is = CPO Vee 1+ Icc·
I
3·61
J?A National .
~ Semiconductor
MM54HC76/MM74HC76 Dual J-K Flip-F'ops
with Preset and Clear
General Description
These high speed (30 MHz minimum) J-K Flip-Flops utilize
microCMOS Technology, 3.5 micron silicon P-well CMOS,
to achieve, the low power consumption and high noise immunity of standard CMOS integrated circuits, along with the
ability to drive 10 LS-TTL loads.
Each flip-flop has independent J, K, PRESET, CLEAR, and
CLOCK inputs and Q and 0 outputs. These devices are
edge sensitive to the clock input and change state on the
negative going transition of the clock pulse. Clear and preset are independent of the clock and accomplished by a low
logic level on the corresponding input
Connection and Logic Diagrams
Dual-In-Llne Package
01
GND
K2
02
01
K1
The 54HC/74HClogic family is functionally as well as pinout compatible with the standard 54LS174LS logic family.
All inputs are protected from damage due to static discharge by internal diode clamps to Vee and.ground.
Features
•
•
•
•
•
Typical propagation delay: 16 ns
Wide operating voltage range
Low· input current: 1 p.A maximum
Low quiescent current: 40 p.A maximum (74HC Series)
High output drive: 10 LS-TTL loads
Truth Table
Inputs
J2
02
16
Outputs
Q
PR
ClR
ClK
J
l
Q
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
X
X
X
-l-l-l-l-
L
H
L
H
L
L
H
H
H
X
X
H
L
L
H
LO
L·
QO
00
H
L
L
H
TOGGLE
QO
00
'This is an unstable condition. and· is not guaranteed
\.
ClK1 PR1
J1,
VCC CLK 2
PR 2
CLR 2
TL/F/5074-1
Top View
Order Number MM54HC76J or MM74HC76J, N
See NS Package J16A or N16E
Q
K
CL
"- +"-
CL
t PRESETi==~===~
CLOCK~
Cl
T
__..f
Cl
T
TL/F/5074-3
TL/F/5074-2
3-62
1ill11ill1
Absolute Maximum Ratings (Notes ~. & 2)
-0.5 to + 7.0V
Supply Voltage (Vee)
DC Input Voltage (VIN)
-1.5 to Vee + 1.5V
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
±20mA
Clamp Diode Current (11K. loKl
±25mA
DC Output Currenl. per pin (lOUT)
±50mA
DC Vee or GND Currenl. per pin (Ice>
Storage Temperalure Range (T8m)
-65'Clo + 150'C
Power Dissipalion (Po) (Nole 3)
500mW
Lead Temp. (TL> (Soldering 10 seconds)
260'C
DC Electrical Characteristics
Symbol
Parameter
Operating Conditions
Supply Voltage (Vee>
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Min
2
Max
6
Units
V
0
Vee
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
Vee=2.0V
(Ir• tf)
Vee=4.5V
Vee=6.0V
(Nole 4)
Conditions
Vee
TA=25'C
Typ
74HC
TA=-40t085'C
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
IIOUTI~20 p.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4:2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
.V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
IIOUTI~4.0 mA
IIOUTI~5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = Vee or GND
6.0V
±0.1
±1.0
±1.0
/LA
VIN = VIH or VIL
IIOUTI~4.0 mA
!louTI ~ 5.2 mA
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
VIN=VIH orVIL
!louTI~20 p.A
Maximum Quiescent VIN=VeeorGND
6.0V
4
40
80
p.A
Supply Current
IOUT=O/LA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mW/'e Irom 6S'C to 8S'C; ceramic "J" package: -12 mWI"C from 100'C to 12S'C.
Note 4: For a power supply of SV ± 10% the worst case output voltages (VOH. and Vou occur lor HC at 4.SV. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at Vcc=S.SV and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (liN. IcC. and
lozl occur for CMOS at the higher vollage and so the 6.0V values should be used.
Icc
3·63
AC Electrical Characteristics Vee = 5V. TA = 25°C. cI. = 15 pF. tr= tl= 6 ns
Symbol
\
Typ
Guaranteed Limit
Units
fMAX
Maximum Operating Frequency
Parameter
Conditions
50
30
MHz
tpHL. tpLH
Maximum Propagation Delay Clock to Q or Q
16
21
ns
tpHL. tpLH
Maximum Propagation Delay Clear to Q or Q
21
26
ns
tpHL. tpLH
Maximum Propagation Delay Preset to Q or Q
23
28
ns
tREM
Minimum Removal Time
10
20
ns
ts
Minimum Setup Time J or K to Clock
14
20
ns
tH
Minimum Hold Time J or K to Clock
-3
0
ns
tw
Minimum Pulse Width Preset. Clear or Clock
10
16
ns
-
AC Electrical Characteristics CL =50 pF. tr =tl=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=25"C
74HC
TA= -40t08SoC
Typ
S4HC
TA= -55to 12SoC
Units
Guaranteed Limits
fMAX
Maximum Operating
Frequency
2.0V
4.5V
6.0V
9
45
53
5
27
31
4
21
24
3
18
20
MHz
MHz
MHz
tpHL. tpLH
Maximum Propagation
Delay Clock to Q or Q
2.0V
4.5V
6.0V
100
20
17
126
25
21
160
31
27
183
37
32
ns
ns
ns
tpHL. tpLH
Maximum Propagation
Delay Clear to Q or Q
2.0V
4.5V
6.0V
126
25
21
155
31
26
191
39
33
250
47
40
ns
ns
ns
tpHL. tpLH
Maximum Propagation
Delay. Preset to Q or Q
2.0V
4.5V
6.0V
137
27
23
165
33
28
210
41
35
240
50
40
ns
ns
ns
tREM
Minimum Removal Time
.Preset or Clear
to Clock
2.0V
4.5V
6.0V
55
11
9
100
20
17
125
25
21
150
30
25
ns
ns
.ns
Minimum Setup Time
2.0V
4.5V
6.0V
.77
15
13
100
20
17
125
25
21
150
30
25
ns
ns
ns
2.0V
4.5V
6.0V
-3
-3
-3
0
0
0
0
0
0
0
0
0
ns
ns
ns
Is
tH
J or K.to Clock
Minimum Hold TIme
,J or K from Clock
tw
Minimum. Pulse Width.
Preset; Clear or Clock
2.0V
4.5V
6.0V
55
11
'9
80
16
14
100
20
18
120
24
21
ns
ns
ns
trLH. tTHL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
'75
15
13
95
19
16
110
22
19
ns
ns
ns
tr. tl
Maximum Input Rise and
Fall Time
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
CPO
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input
Capacitance
(per flip-flop)
pF
80
5
10
I
10
pF
10
Note 5: Cpo determines the no load dynamic power consumption. Po = Cpo Vcc2 1+ Icc Vee, and the no load dynamic current consumption, IS =Cpo Vcc 1+ ICC'
-
3-64
Typical Applications
N Bit Presettable Ripple Counter with Enable and Reset
DATAC
DATAB
-
Q
PRESET
•••
CLEAR
TO
NEXT BIT
a
-
J-
KI-
CLOCK
Q
PRESET
1---
0:-
DATA A
I
!
COUNTER ENABLE
J-
CLEAR
-
a
Y
PRESET
J
CLEAR
0:-
Kr-
CLOCK
r-- Q
-
Q
0-
K
CLOCK
Y
CLOCK
RESET
BIT 3
LS8
BIT 2
TUF/5D74-4
N Bit Parallel Load/Serial Load Shift Register with Clear
DATA A
DATA
~l
1
J
PRESET
CLOCK
Y
DATA C
1
J
Q
CLEAR
K
CL.OCK
DATA B
a
PRESET
P-
1
CLEAR
K
CL.OCK
Y
J
Q
a
PRESET
p-
Q '""""--
CLEAR
K
CLOCK
• ••
0-
a-
-
Y
CL.EAR
TUF/5D74-5
3·65
~National
'
~ Semiconductor
MM54HC85/MM74HC85
4-Bit Magnitude Comparator
\ J
microCMOS
General Description
The MM54HC85/MM74HC85 is a 4-bit magnitude comparator that utilizes microCMOS Technology, 3.5 micron silicon
gate P-well CMOS. It is designed for high speed comparison
of two four bit words. This circuit has eight comparison inputs, 4 for each word; three cBscade inputs (A<8, A>8,
A=8); and three decision outputs (A<8, A>8, A=8). The
result of a Comparison is indicated by a high level on one of
the decision outputs. Thus it may be determined whether
one word is "greater than," "less than," or "equal to" the
other word. 8y connecting the outputs of the least sigr;lificant stage to the cascade inputs of the next stage, words of
greater than four bits can be compared. In addition the least
significant stage must have a high level applied to the A = 8
input, and a low level to the A<8, and A>8 inputs.
The comparator's outputs can drive 10 low power Schottky
TTL (LS-TTL) equivalent loads, and is functionally, and pin
equivalent to the 54LS85174LS85. All inputs are protected
from damage due to static discharge by diodes to Vee and
ground.
Features
•
•
•
•
•
Typical propagation delay: 27 ns
Wide operating voltage range: 2-6V
Low input current: 1 p.A maximum
Low quiescent current: 80 p.A maximum (74HC Series)
Output drive capability: 10 LS-TTL loads
Connection Diagram
Dual-In-Line Package ,
i~
,
DATAINI'UTS
A3
16
B2
15
14
•
1
A1
13
B1
12
AO
BO '
10
11
B2
A2
A1
B1
AO
AB
IN
A>B
OUT
A=B
OUT
AB, ,A>B
DATA
CASCADE INPUTS
OUTI'UTS
INPUT
TOP VIEW
at:
TLfFf5205-1
Order Number MM54HC85J or MM74HC85J, N
See NS Package J16A or N16E
Truth Table
Comparing
Inputs
Cascading
Inputs
A3,B3
A2,B2
A1,B1
AD,BD
A3> 83
A3 < 83
A3 = 83
A3 = 83
A3 = 83
A3 = B3
A3 = B3
A3 = 83
A3 = B3
A3 = 83
A3 =,83
A3 ='83
A3 = 83
X
X
X
X
X
X
X
X
X
X
X
X
A2> 82
A2 < 82
A2 = 82
A2= B2
A2 = B2
A2= 82
A2 = B2
A2 = 82
A2 = 82
'A2=B2
A2 = 82
A1
A1
A1
A1
A1
A1
A1
A1
A1
>
<
=
=
=
=
=
=
=
81
81
81
81
81
81
B1
81
81
AO>
AO<
AO ==
AO =
AO =
AO =
AO =
80
80
80
80
BO
BO
80
Outputs
AB
AB
H
L
3-66
Absolute Maximum Ratings
Operating Conditions
(Notes 1 & 2)
-0.5 to + 7.0V
Supply Voltage (Vee>
DC Input Voltage (VIN)
-1.5toVee+ 1•5V
DC Output Voltage (VOUT)
-0.5 to Vee + 0.5V
±20mA
Clamp Diode Current (11K. 10K>
DC Output Current. per pin (lOUT)
±25mA
±50mA
DC Vee or GND Current. per pin (Ice>
-65·Cto + 150·C
Storage Temperature Range (Tsm)
Power Dissipation (PD) (Note 3)
500mW
Lead Temp. (TLl (Soldering 10 seconds)
260·C
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TN
MM74HC
MM54HC
Input Rise or Fall Times
(Ir. tf) Vee = 2.0V
Vee=4.5V
Vee=6.0V
Min
2
0
Ma_x
6
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
Units '
V
V
Vee
\
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25"C
Typ
74HC
TA=-40to85"C
54HC
TA=-55to125·C
Units
-,
Guaranteed Umlta
VIHI,
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN=VIH orVIL
IIOUTI S;20 p.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or Vil
Iiourl S;4.0 mA
IIOUTI S; 5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VeeorGND
6.0V
±0.1
±1.0
±1.0
/LA
VIN=VIH orVIL
Ilourls;4.0 mA
IIOUTI s; 5.2 mA
Maximum Low Level
Output Voltage
VOL
Maximum Input
Current
liN
VIN=VIH orVIL
IIOUTI s; 20 /LA
Maximum Quiescent VIN=VeeorGND 6.0V
160
8.0
80
/LA
Supply Current
IOUT=O /LA
Nole 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plasfic "N" package: -:-12 mW/'C from 6S'C to 85'C; ceramic "J" package: -12 mW/'C from 100'C to 125'C.
Nole 4: For a power supply of 5V ± 10% the worst case output voltages (VOH. and VoLl occur for HC at 4.5V;Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at VCC=5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (lIN. 100 and
10Z> occur for CMOS at the higher voltage and so the 6.0V values should be used.
Icc
-
3-67
AC Electrical Characteristics Vcc=5V. TA=25'C. CL = 15 pF. t,=tf=6 ns
Symbol
Parameter
tpHL. tpLH
Maximum Propagation Delay Data Input to A < B or A> B
Maximum Propagation Delay A = B Input to A= B Output
20
12
Limit
36
20
Maximum Propagation Delay Cascade Input to Output
Maximum Propagation Delay Data Input to A = B
13
20
26
30
tPHL. tpLH
tpHL. tpLH
tpHL. tpLH
Conditions
Typ
Units
ns
ns
ns
ns
AC Electrical Characteristics CL ";50 pF. t,;"tf;"6 ns (unless otherwise specified)
Symbol'
Parameter
TA=2SOC
Vee
Conditions
Typ
IpHL. tpLH
Maximum Propagation
Delay Data Input to
Output
tpHL.IpLH
Maximum Propagation Delay
Data Input to A = B Output
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
100
21
18
88
18
15
63
13
11
54HC
74HC
TA=-40to85'C TA'= -55 to 125'C
Guaranteed Limits
210
42
36
175
35
30
265
53
45
Units
37
313
63
53
261
52
44
ns
ns
ns
ns
ns
ns
125
25
21
158
32
27
186
37
32
ns
ns
ns
221
44
tpHL. tpLH
Maximum Propagation Delay
A=B Input to A=B Output,
tpHL. tpLH
Maximum Propagation
Delay Cascade Input
to Output (except A = B)
2.0V
4.5V
6.0V
70
16
13
155
31
26
195
39
33
231
46
39
ns
ns
ns
tTLH. trHL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
25
7
6
75
15
13
95
19
16
110
22
19
CIN
CpO
Maximum Input Capacitance
Power Dissipation Capacitance
5
80
10
10
10
ns
ns
ns
pF .
(Note 5)
pF
Note 5: CPO determines the. no load dynamic power consumption. Po = Cpo Vrx!- 1+ lee Vee, and the no load dynamic current consumption,
Is = Cpo Vee f + lco
Typical Application
\
Cascading Comparatora
GNO- A>B,.
Vcc- A=B,.
GNO- ABw
A> BOUT
A=BOUT
A=Bw
A BOUT f-- A>B,.
. A=BOUT I-- A=B,.
A BOUT
A=BoUT E}OUWUTS
A B=AB + As
3-70
TL/F/5305-1
Absolute Maximum Ratings
Operating Conditions
(Notes 1 & 2)
-0.5 to + 7.0V
Supply Voltage (VeC>
DC Input Voltage (VIN)
-1.5 to Vee + 1.5V
DC Output Voltage (Vour)
-0.5 to Vee+0.5V
±20mA
±25mA
±50mA
Clamp Diode Current (11K. 10K>
DC Output Current. per pin (lour)
DC Vee or GND Current. per pin (ICC>
Storage Temperature Range (T8m)
Supply Voltage (Vee)
DC Input or Output Voltage
(YIN. Your)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
Vcc=2.0V
(tr• til
Vcc=4.5V
Vcc=6.0V·
-65'C to + 150'C
Power Dissipation (PD) (Note 3)
Lead Temperature (Tt.>
(Soldering 10 seconds)
500mW
260'C
Min
2
0
,Max
6
Vcc
Units
V
V
-40
-55
+85
+125
·'C
'C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
• Parameter
Conditions
Vee
74HC
TA= -40 to 85'C
TA=25'C
Typ
54HC
TA= -55 to 125'C
Units
Gl!aranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
lIourl:5:20 p.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
lIourl:5:4.0 mA
Ilourl:5:5.2mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = VIH or VIL
Iiourl ';;4.0 mA
Ilourl:5:5.2 mA
VOL
Maximum Low Level
Output Voltage
VIN = VIH or VIL
Ilourl:5:20 p.A
liN
Maximum Input
Current
VIN = Vcc or GND
6.0V
±0.1
±1.0
±1.0
p.A
Ice
Maximum Quiescent
Supply Current
VIN = Vcc or GND
lour=O p.A
6.0V
2.0
20
40
p.A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: - t 2 mWI'C from 6S'C to 8S'C; ceramic "J" package: -12 mWI'C from 1OO'C to 12S'C.
Note 4: For a power supply of SV ± 10% the worst case output voltages (VOH. and VoLl occur for HC at 4.SV. Thus the 4.SV values should be used when designing
with this supply. Worst case V,H and V,L occur at Vcc~ S.SV and 4.5V respectively. (The V,H value at S.5V is 3.8SV.) The worst case leakage current (liN. Icc. and
loz) occur for CMOS at the higher voltage and so the 6.0V values should be used.
,
3-71
AC Electrical Characteristics Vcc= 5V. TA = 25°C. CL = 15 PF. 1r=tf= 6 ns
, Symbol
tpHL. tpLH
Parameter
Conditions
Maldmum Propagation·
Delay
Typ
Guaranteed
Limit
Units
12
20
ns
,
AC Electrical Characteristics Vcc= 2,OV to 6,OV. CL = 50 pF. tr= tf= 6 ns (unless otherwise specified)
.
Symbol
Parameter
Conditions
Vee
TA=25°C
Typ
tpHL. tpLH
trLH. tTHL
CPO
CIN
74HC
TA=-40t08SOC
2.0V
4.5V
6,OV
60
12
10
120
24
20
151
30
26
Maximum Output Rise
and Fall Time
2.0V
4,5V
6.0V
30
75
15
13
95
19
16
Power Dissipation
Capacitance (Note 5)
Maximum Input
Capacitance
(par gate)
7
Units
Guaranteed Limits
Maximum Propagation
Delay
8
54HC
TA= -55 to 125°C
,
179
36
30
ns
ns
ns
110
22
19
ns
ns
ns
25
pF
"
5
10
10
10
pF
Note 5: CPO detennlnes the no load dynamic power consumption, Po= Cpo Vcc2 f+ lee Vee. and the no load dynamic current consumption, IS = Cpo Vee f+ lee,
-
3-72
-
~National
~ Semiconductor
microCMOS
MM54HC107/MM74HC107
Dual J-K Flip-Flops with Clear
General Description
Features
These J-K Flip-Flops utilize microCMOS Technology, 3.5
micron silicon gate P-well CMOS, to achieve the high noise
immunity and low power dissipation of standard CMOS inte- .
grated circuits. These devices can drive 10 LS-TIL loads.
•
•
•
•
•
These flip-flops are edge sensitive to the clock input and
change state on the negative going transition of the clock
pulse. Each one has independent J, K, CLOCK, and CLEAR
inputs and Q and outputs. CLEAR is independent of the
clock and accomplished by a low level on the input.
The 54HC174HC logic family is functionally as well as pinout compatible with the standard 54LS174LS logic family.
All inputs are protected from damage due to static discharge by internal diode clamps to Vee and ground.
Typical propagation delay: 16 ns
Wide operating voltage range: 2-6V
Low input current: 1 /LA maximum
Low quiescent current: 40 /LA (74HC series)
High output drive: 10 LS-TIL loads
a
Truth Table
Connection Diagram
Dual-In-Une Package
vcc
CLR 1
CLK 1
K2
CLR 2
CLK 2
Outputs
Inputs
J2
8
CLR
L
H
H
H
H
H
CLK'
J
K
X
X
X
.L.
.L.
.L.
.L.
L
H
L
H
L
L
H
H
H
X
X
Q
Q
L
H
00
H
L
L
H
TOGGLE
00
aD
aD
7
J1
Q1
K1
Q2
Q2
GND
TUFf5304-1
Order Number MM54HC107J or MM74HC107J, N
See,NS Package J14A or N14A .
Logic Diagram
r-----+;----~~-Q
rd1t~
CL
K
T
CL
CL
T
TLfFf5304-3
CL
CLOCK~
TLfFf5304-2
3-73
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
Supply Voltage (Vcc)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K. 10K>
DC Output Current. per pin (lOUT)
DC Vee or GND Current. per pin (Icc)
Storage Temperature Range (T8TG)
Power Dissipation (Po) (Note 3)
Lead Temperature (TLl
(Soldering 10 seconds)
Supply Voltage (Vee>
DC Input or Output Voltage '
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
(tr. til Vee=2.0V
Vee=4.5V
Vee=6.0V
-0.5 to + 7.0V
-1.5to Vee + 1.5V
-0.5 to Vee+0.5V
±20rnA
±25mA
±50mA
-65·Cto + 150·C
500mW
26O"C
' Min
2
0
-40
-55
Max
6
Vee
Units
V
V
+85
+125
·C
·C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=2S·C
Typ
74HC
TA= -40 to 8S·C
S4HC
TA= -SSto 125"C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
3.98
5.48
3.84
5.34
3.7
5.2
V
V
VIN = VIH or VIL
IIOUTIS:20 pA
VIN = VIH or VIL
IIOUTIS:4.0 mA
IIOUTI s: 5.2 mA
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
VIN = VIH or VIL
IloUTI s: 20 /LA
2.0V
4.5V
6.0V
2.0
4.5
6.0
4.5V
6.0V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
IIOUTIS:4.0 mA
IIOUTIS:5.2 rnA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VccorGND
6.0V
±0.1
±1.0
±1.0
/LA '
Maximum Quiescent VIN=Vee or GND 6.0V
4.0
40
80
pA
Supply Current
IOUT=O /LA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specHied all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mWrc from 6S'C to 85'C; ceramic "J'" package: -12 mW/'C from 1OO'C to 125'C.
Note 4: For a power supply of sv ±'10% the worst case output voltages (VOH. and Va!.> occur for HC at4.S\I. Thus the 4.SV values should be used when designing
wHh this supply. Worst case VIH and VIL occur at Voo= S.5V and 4.5V respectively. (The VIH value atS.SV is 3.85V:) The worsl caSe leakage current (liN. ICC. and
IOzJ occur for CMOS at the higher voltage and so the 6.0V values should be used.
Icc
.
3·74
3:
3:
AC Electrical Characteristics Vcc=5V, TA=25"C, CL =15 pF, tr =tf=6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
fMAX
Maximum Operating
Frequency
50
30
MHz
IPHL, tpLH
Maximum Propagation
Delay Clock to Q or Q
16
21
ns
tPHL, tpLH
Maximum Propagation
Delay Clear to Q or Q
21
26
ns
tREM
Minimum Removal Time,
Clear to Clock
10
20
ns
Minimum Setup Time,
14
20
ns
-3
0
ns
10
16
ns
ts
....::r::
CII
o.....
o
.....
.....
3:
3:
.........
::r::
o
.....
o
.....
J or K to Clock
tH
Minimum Hold Time
J or K from Clock
tw
Minimum Pulse Width,
Clock or Clear
AC Electrical Characteristics CL = 50 pF, tr=lf= 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25"C
Vee
Typ
74HC
TA= -40 to 85"C
54HC
TA= -55to 125"C
Units
Guaranteed Limits
fMAX
Maximum 0l?erating
Frequency
2.0V
4.5V
6.0V
9
45
53
5
27
31
4
21
24
3
18
20
MHz
MHz
MHz
tpHL,lpLH
Maximum Propagation
Delay Clock to Q or Q
2.0V
4.5V
6.0V
70
18
16
126
25
21
160
32
27
185
37
32
ns
ns
ns
tpHL, tpLH
Maximum Propagation
Delay Clear to Q or Q
2.0V
4.5V
6.0V
126
25
21
155
31
26
194
39
32
250.
47
40
ns
ns
ns
IREM
Minimum Removal Time
Clear to Clock
2.0V
4.5V
6.0V
55
11
9
100
20
17
125
25
21
150
30
25
ns
ns
ns
Minimum Setup Time
2.0V
4.5V
6.0V
77
15
13
100
20
17
125
25
21
150
30
25
ns
ns
ns
2.0V
4.5V
6.0V
-3
-3
-3
0
0
0
0
0
0
0
0
0
ns
ns
ns
ts
J or K to Clock
tH
Minimum Hold Time
J or K to Clock
tw
Minimum Pulse Width
Clear or Clock
2.0V
4.5V
6.0V
55
11
10
80
16
14
100
20
18
120
24
21
ns
ns
ns
tTLH,ITHL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
tr, If
Maximum Input Rise and
Fall Time
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
CPD
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input
Capacitance
(per flip-flop)
pF
80
5
10
10
10
pF
Note 5: CPO determines the no load dynamic power consumption. Po= Cpo Vcrf f+ lee Vee. and the no load dynamic current consumption. Is =Cpo Vee f+ Icc.
3-75
sr---~-----------------------------------------------------------.
.,...
o
::z:
'Oil'
Typical Applications
.....
:Ii!
:Ii!
.....
.....
CI
.,...
o
::z:
'Oil'
N Bit Binary Ripple Counter with Enable and Reset
COUNTER ENABLE
RESET
l
an
:Ii!
:Ii!
~
!
Q
CLEAR
J i--'
a
CLOCK
K I"-
ro- Q
!
CLEAR
J I"-
CLOCK
KI"-
~
Q
CLEAR
J l"-
a
CLOCK
K
•••
TO
NEXT BIT
a
l"-
Y
Y
CLOCK
BIT 2
BIT 3
LSB
TLlF/5304-4
N Bit Shift Register with Clear
CLEAR
DATA
INPUT~
l
J
CLEAR
!
Q
J
CLEAR
!
Q
~
CLEAR
Qt---
•••
K
CLOCK
CLOCK
r
a
K
CLOCK
r
a
K
CLOCK
at---
r
TLlF/5304-5
3·76
~National
----
~ Semiconductor
s:
s:
en
\
)
microCMOS
~
:::t:
(")
.....
Q
CD
......
s:
s:
.....
MM54HC1 09/MM7 4HC1 09
Dual J-K Flip-Flops with Preset and Clear
~
:::t:
(")
.....
General Description
Q
These J-K FLIP-FLOPS utilize microCMOS Technology, 3.5
micron silicon gate P-well CMOS, to achieve the low power
consumption and high noise immunity of standard CMOS
integrated circuits, along with the ability to drive 10 LS-TTL
loads.
Each flip flop has independent J, K PRESET, CLEAR and
CLOCK inputs and 0 and
outputs. These devices are
edge sensitive to the clock input and change state on the
positive going transition of the clock pulse. Clear and preset
are independent of the clock and accomplished by a low
logic level on the corresponding input.
a
The 54HC174HC logic family is functionally as well as pinout compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static discharge by internal diode clamps to Vee and ground.
Features
•
•
•
,•
•
Typical propagation delay: 20 ns
Wide operating voltage range: 2-6V
Low input current: 1 /LA maximum
Low quiescent current: 40 /LA maximum (74HC Series)
Output drive capability: 10 LS-TTL loads
Connection Diagram
VCC
Dual-In-llne Package
K2 ClK2 PR2
J2
ClR 2
116
15
j13
L
14
12
Q2
02
~
10
11
PR
Q-
J
_ ClR_
r-- K
Q
)ClK
J
- -
,-)ClK
K ClR
0
...,
PR Q1
...,
2
ClR 1
J1
I
14
J3
K1
5
7
6
ClK 1 PR 1
Q1
01
18
. GND
Top View
Order Number MM54HC109J or MM74HC109J, N
See NS Package J16A or N16E
Function Table
Inputs
outputs
PR
ClR
ClK
J
K
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
l
X
X
X
t
t
.j
t
H
L
H
L
L
H
H
L
X
X
3-77
Q
Q
H
L
L
H
H*
H*
L
H
TOGGLE
00
H
L
00
ao
ao
TL/F/S306-1
CD
·Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage {Vecl
Operating Conditions
-0.5 to + 7.0V
DC Input Voltage (VIN) .
-1.5 to Vee + 1.5V
Supply Voltage (Vecl
DC Output Voitage (VOUT)
-0.5 to Vcc+0.5V
±20mA
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TAl
MM74HC
MM54HC
Clamp Diode Current (11K. 10K>
DC Output Current. per pin (lOUT)
±25mA
±50mA
DC Vcc or GND Current. per pin (Icc)
- 65·C to + 150"C
Storage Temperature Range (TSTG)
Lead Temp.
(TO (Soldering 10 seconds)
Max
6
Units
V
0
Vcc
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
(t,. t,)
Vee=2.0V
Vcc=4.5V
Vcc= 6.0V
500mW
Power Dissipation (Po) (Note 3)
Min
2
260·C
DC Electrical Characteristics (Note 4)
Syinbol
Parameter
Conditions
Vee
TA=25·C
74HC
TA=-40to85·C
Typ
54HC
TA= -55 to 125·C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voliage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
3.98
5.48
3.84
5.34
3.7
5.2.
V
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
.V
V
V
/
VIN = VIH or VIL
IlouilS:20 )LA
VIN=VIH orVIL
/louTIS:4.0 mA
IIOUTIS:5.2 mA
VOL
Maximum Low Level
Output Voltage
VIN=VIH orVIL
IIOUTIS:20 )LA
2.0V
4.5V
6.0V
2.0
4.5
6.0
4.5V
6.0V
2.0V
4.5V
6.0V
0
0
0
VIN = VIH or VIL
/louTIS:4.0 mA
/louTI s: 5.2 mA
4.5V
6.0V
0.26
0.26
0.33
I
0.33
0.4
0.4
V
V
liN
Maximum Input
Current
VIN=VCC orGND
6.0V
±0.1
±1.0
±1.0
)LA
ICC
Maximum Quiescent
Supply Current
VIN = Vee or GND
IOUT=O)LA
6.0V
4.0
40
80
)LA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating ~ plesUc UN" package: -12 mWrc from 6S'C to 65'C; ceramic .oJ"' package: - t 2 mW /'C from tOO'C to t 25'C.
Note 4: For a power supply of SV ± t 0% the worst case output voltages (VaH. and VaLl occur for HC at 4.SV. Thus the 4.SV values should be used when designing
with this supply. Worst case VIH and VIL occur at Vee ~ S.SV and 4.5V respectively. (The VIH value at S.SV is 3.8SV.) The worst case leakage curient (liN. Icc. and
lazl occur lor CMOS at the higher voltage and so the 6.0V values should be used.
3-78
AC Electrical Characteristics Vcc= 5V. T A = 25°C. CL = 15 pF. tr= tf= 6 ns
Typ
Guaranteed
Limit'
Units
fMAX
Maximum Operating Frequency
50
30
MHz
tpHL. tpLH
Maximum Propagation
Delay. Clock to Q or Q
16
30
ns
tpHL. tpLH
Maximum Propagation
Delay. Preset or Clear to Q or Q
21
42
ns
tREM
Minimum Removal Time. Preset or Clear tei Clock
5
ns
ts
Minimum Setup Time. J or K to Clock
20
ns
tH
Minimum Hold Time. J or K to Clock
0
ns
tw
Minimum Pulse Width: Preset. Clear or Clock
16
ns
Symbol
Parameter
Conditions
9
AC Electrical Characteristics CL = 50 pF. tr= tf= 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=25°C
Typ
fMAX
Maximum Operating
Frequency
2.0V
4.5V
6.0V
tpHL. tpLH
Maximum Propagation
Delay. Clock to Q or Q
2.0V
4.5V
6.0V
tpHL. tpLH
Maximum Propagation
Delay. '=!:eset or Clear
toQorQ
2.0V'
4.5V
6.0V
tREM
Minimum Removal Time
Preset or Clear
to Clock
Minimum Setup Time
ts
J or K to Clock
74HC
TA= -40t085°C
54HC
TA= -55 to 125°C
Units
Guaranteed Limits
5
27
31
4
21
24
4
18
20
MHz
MHz
MHz
88
18
15
175
35
30
2~1
44
37
261
52
44
ns
ns
ns
115
23
20
230
46
39
"29Q
58
49
343
69
58
ns
ns
ns
2.0V
4.5V
6.0V
25
5
4
32
6
5
37
7
6
ns
ns
ns
2.0V
4.5V
6.0V
100
20
17
126
25
21
119
30
20
ns
ns
ns
0
0
0
0
0
0
0
0
0
ns
ns
ns
tH
Minimum Hold Time
Clock to J or K
2.0V
4.5V
6.0V
tw
Minimum Pulse Width
Clock. Preset or Clear
2.0V
4.5V
6.0V
30
9
8
80
16
14
100
20
18
120
24
20
ns
ns
ns
tTLH. tTHL
Output Rise and
Fall Time
2.0V
4.5V
6.0V
25
75
15
13
95
19
16
110
22
19
ns
ns
ns
tr• tf
Maximum Input Rise and
Fall Time
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
CPO
Power Dissipation
Capacitance (Note 5)
±25mA
DC Output Current, per pin (lOUT)
±50mA
DC Vee or GND Current, per pin (lee) .
-65'C to + 150'C
Storage Temperature Rang!! (TSTG)
Power Dissipation (Po) (Note 3)
500mW
Lead Temp. (TLl (Soldering 10 seconds)
260'C
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
'C
'C
Supply Voltage {Veel
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
(tr,tf} . Vee=2.0V
Vee=4.5V
Vee=6.0V
CI'I
Parameter
Conditions
Vee
74HC
TA = -40 to 85'C
TA=25'C
Typ
1000
500
400
ns
ns
ns
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIH
VIN = VIH or VIL
IIOUTI:S:20 pA
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
V
V
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
IIOUTI:S:4.0 mA
IiOUTI:s: 5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = Vee or GND
6.0V
±0.1
±1.0
±1.0
/LA
VIN = VIH or VIL
IIOUTI :s: 4.0 mA
IIOUTI :s: 5.2 mA
VIN = VIH or VIL
IIOUTI:S:20 /LA
V
Maximum Quiescent VIN = Vee or GND 6.0V
4.0
40
80
/LA
Supply Current
IOUT=O /LA
Nota 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Nota 2: Unless otherwise specified all voltages are referenced to ground.
Nota 3: Power Dissipation temperature derating - plastic "N" package: -12 mWI'e from 65'e 10 85'C; ceramic "J" package: -12 mWI'C from 1OO'C to 125'C.
Nota 4: For a power supply of 5V ± 10% the worst case output voltages (VOH. and VOU occur for HC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at VCC= 5.5V and 4.5V respectively. (The VIH value at 5.5V Is 3.85V.) The worst case leakage current (liN. Icc. and
lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
Icc
,
3-81
"
o
....
....
N
.....
3i:
DC Electrical Characteristics (Note 4)
Symbol
~
:::J:
3i:
......
~
:::J:
o....
....
N
AC Electrical Characteristics Vcc=5V, TA = 25°C, CL =15pF, tr =tf=6ns
Typ
Guaranteed Limit
Units
50
30
MHz
Maximum Propagation
Delay, Clock to Q or Q
16
21
ns
tpHL, tpLH
Maximum Propagation
Delay, Clear to Q or Q
21
26
ns
tpHL, tpLH,
Maximum Propagation
Delay, Preset to Q or Q
23
28
ns
tREM
Minimum Removal Time,
Preset or Clear to Clock
10
20
ns
Minimum Setup Time
14
20
ns
-3
·0
ns
10
16
ns
Symbol
Parameter
fMAX
Maximum Operating
Frequency'
tpHL, tpLH
Is
tH
Conditions
,
J or K to Clock
Minimum Hold Time
~
,
J or K from Clock
tw
Minimum Pulse Width
Clock Preset or Clear
AC Electrical Characteristics CL = 50 pF, tr=tf= 6 ns (unless otherwise speCified)
Symbol
Parameter
Conditions
TA=25°C
Vee
74HC
TA= -40 to 85°C
Typ
54HC
TA= -55to 125°C
Units
Guaranteed Limits
fMAX
Maximum Operating
Frequency
2.0V
4.5V
6.0V
9
45
53
5
27
31
4
21
24
3
18
20
MHz
MHz
MHz
tpHL, tpLH
Maximum Propagation
Delay, Clock to Q or Q
2.0V
4.5V
6.0V
100
20
17
126
25
21
160
32
27
183
37
32
ns
ns
ns
tpHL, tpLH
Maximum Propagation
Delay, Clear to Q or Q
2.0V
4.5V
6.0V
126
25
21
155
31
26
191
39
33
250
47
40
ns
ns
ns
tpHL, tpLH
Maximum Propagation
Delay, Preset to Q or Q
2.0V
4.5V
6.0V
137
27
23
165
33
28
210
41
35
240
50
40
ns
ns
ns
tR'EM
Minimum Removal Time
Preset or Clear
to Clock
2.0V
4.5V
6.0V
55
11
9.4
100
20
17
125
25
21
150
30
25
ns
ns
ns
Minimum Setup Time
2.0V
4.5V
6.0V
77
15
13
100
20
17
125.
25
21
150
30
25
ns
ns
ns
2.0V
4.5V
6.0V
-3
-3
-3
0
0
0
0
0
0
0
0
0
ns
ns
ns
100
20
18
120
24
20
ns
ns
ns
Is
tH
J or K to Clock
Minimum Hold Time
J or K from Clock
.
tw
Minimum Pulse Width
Preset, Clear or Clock
2.0V
4.5V
6.0V
55
11
9
80
16
14
trLH, trHL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
Ir' tf
Maximum Input Rise and
Fall Time
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
CPD
Power Dissipation
Capacitance (Note 5)
(per flip-flop)
80
pF
Maximum Input Capacitance
5
10
10
10
pF
CIN
Note 5: CPO determines the no load dynamic power consumption. Po = CPO Vee2 1+ lee Vee, and the no load dynamic current consumption, Is = CPO Vee 1+ lee.
3-82
Typical Applications
N Bit Presettable Ripple Counter with Enable and Reset .
DATAC
A
.....-
Q
J-
CLEAR
TO
NEXT BIT
Q
1
A
PRESET
•••
DATA A
DATAB
'1
I
COUNTER ENABLE
r-
A
PRESET
JI--
CLEAR
0-
Q
K- I-
CLOCK
Q
r
r-
PRESET
PQ
r
K~ ~
CLOCK
1
CLOCK
RESET
BIT 3
J
CLEAR ~
Kr- r-
CLOCK
Q
LSB
BIT 2
TUF/5307-4
N Bit Parallel Load/Serial Load Shift Register with Clear
DATA A
DATA
INPUT]
J
PRESET
Y
L
CLOCK
DATAB
l
CLEAR
K
CLOCK
r
J
.Q
Q
1
PRESET
F>-
DATAC
I
Q
CLEAR
K
CLOCK
1
Q
J
,!
PRESET
po-
Qt---
CLEAR
K
CLOCK
F>-
Q~
• ••
.--
1
CLEAR
TUF/5307-5
3-83
~ r-------------------------------------------------------------------------,
..o ~National
:r::
.J-'\J
"'It
.....
:E, ~
microCMOS
:E
Semiconductor
......
~
MM54HC113/MM74HC11.3
..- Dual J.. K Flip-Flops with Preset
o
:r::
"'It
It)
General Description
:E
:E
These high speed J-K Flip-Flops utilize microCMOS Technology. 3.5 micron silicon gate P-well CMOS. to achieve the
high noise immunity and low power dissipation of standard
CMOS integrated circuits. These devices can drive 10 LSTTL loads.
These flip-flops are edge sensitive to the clock input and
change state on the negative going transition of the clock
pulse. Each one has independent J. K. CLOCK. and PRESET Inputs and and inputs. PRESET is independent of
the clock and accomplished by a low level on the input.
a
a
The 54HC174HC logic family is functionally as well as pin-
out compatible with the standard 54LS174LS logic family.
All inputs are protected from damage due to static discharge by internal diode clamps to Vee and ground.
Features
•
•
•
•
•
Typical propagation delay: 16 ns
Wide operating voltage range: 2-6V
Low input current: 1 p.A maximum
Low quiescent current: 40 p.A (74HC Series)
High output drive: 10 LS-TTL loads
Connection Diagram and Truth Table
Dual-In-Llne Package
VCC
CLK2
KZ
JZ
02
PRZ
02
Inputs
Outputs
Q
PR
CLK
J
K
0
L
H
H
H
H
H
X
,j.
,j.
,j.
,j.
X
X
L
,14
L
H
L
L
H
H
H
X
X
H
L
00
00
H
L
H
L
TOGGLE
00
00
TL/F/5073-1
Top View
Order Number MM54HC113J or MM74HC113J, N
See NS Package J14A or N14A
Logic Diagram
K
Ci:
.... t....
CL
t PRESET-t:::=~===~
CLOCK~
___-f
GO
Ci:
CL
T
T
3-84
TL/F/5073-2
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
Supply Voltage (Vee)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K, 10K>
, DC Output Current, per pin (loUT)
-0.5 to +7.0V
-1.6 to Vcc+ 1.5V
-0.5 to Vcc+0.5V
±20mA
±25mA
±50mA
DC Vce or GND Current, per pin (Icel
-65·C to + 150·C
Storage Temperature Range (TSTG)
500mW
Power Dissipation (Po) (Note 3)
I 260.C
Lead Temp. (TL.l (Soldering 10 seconds)
Supply Voltage (Vcel
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall TImes
(t,., ttl
Vee=2.0V
Vee=4.5V
Vee=6.0V
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25"C
Typ
74HC
TA= -40 to 85·C
54HC
TA= -55to 125"C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3'
0.9
1.2
0.3
.. 0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
IIOUTI ,;; 20 p.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9 -
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIHorVIL
IIOUTI';;4.0 mA
IIOUTI ';;5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VccorGND
6.0V
±0.1
±1.0
±1.0
p.A
VIN = VIH or VIL
IIOUTI ';;4.0 mA
IIOUTI ';;5.2 mA
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
.VIN = VIH or VIL'
IIOUTI ,;;20 p.A
80
p.A
Maximum Quiescent VIN=VCCorGND 6.0V
40
4.0
Supply Current
IOUT=Op.A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Nom 3: Power Dissipation temperature derating - plastic "N'" package: -12 mW/'C from 6S'C to 8S'C; ceramic "J" package: -12 mWI'C from 100'C 10 12S'C.
Note 4: For a power supply of SV ± 10% the worst case output voltages (YOH. and VoLl occur for HC at 4.SV. Thus the 4.SV values should be used when designing
with this supply. Worst case VIH and VIL occur at Vcc~ S.SV a'hd 4.SV respectively. (The VIH value at S.SV is 3.8SV.) The worst case leakage current (liN. Icc. and
lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
Icc
3·85
.,...
.,...
o
('I)
AC Electrical Characteristics Vcc=5V, TA=25"C, CL =15 pF, t r =t,=6 ns
:J:
-=t
.....
Symbol
::E
::E
......
Conditions
Parameter
Typ
Guaranteed
Limit
Units
fMAX
Maximum Operating
Frequency
50
30
MHz
.,...
.,...
o
tpHL, tpLH
Maximum Propagation Delay,
Clock to Q or Q
16
21
ns
-=t
tpHL, tpLH
Maximum Propagatio!1 Delay,
Preset to Q or Q
23
28
ns
::E
::E
tREM
Minimum Removal Time,
Preset to Clock
10
20
ns
Minimum Setup Time,
14
20
ns
-3
0
ns
10
16
ns
('I)
:J:
II)
ts
J or K to Ciock
tH
Minimum Hold Time,
J or K from Clock
tw
Minimum Pulse Width,
Preset, Clear or Ciock
AC Electrical Characteristics CL = 50 pF, tr= t,= 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25"C
Vcc
Typ
74HC
TA=-40t085"C
Maximum Operating
Frequency
2.0V
4.5V
6.0V
9
45
53
5
27
31
4
21
24
tpHL, tpLH
Maximum Propagation
Delay, Clock to Q or Q
2.0V
4.5V
6.0V
100
20
17
125
25
33
160
32
27
tpHL, ~PLH
Maximum Propagation
Delay, Preset to Q or Q
2.0V
4.5V
6.0V
137
27
23
165
33
28
tREM
Minimum Removal Time
Preset to Clock
2.0V
4.5V
6.0V
55
11
9
Minimum Setup Time
2.0V
4.5V
6.0V
J or K to Clock
tH
Minimum Hold Time
J or K from Clock
Units
Guaranteed Limits
fMAX
ts
54HC
TA= -55 to 125"C
3
18
20
MHz
MHz
MHz
183
37
32
ns
ns
ns
206
41
35
239
47
40
ns
ns
ns
100
20
17
125
25
21
150
30
25
ns
ns
ns
77
15
13
100
20
17
125
25
21
150
30
25
ns
ns
ns
2:0V
4.5V
6.0V
-3
-3
-3
0
0
0
0
0
0
0
0
0
ns
ns
ns
.
tw
Minimum Pulse Width,
Preset, Clear or Clock
2.0V
4.5V
6.0V
55
11
9
80
16
14
100
20
18
120
24
20
ns
ns
ns
tTLH, tTHL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
tr,t,
Maximum Input Rise and
Fall Time
2.0V
4.5V
6.0V
tOOO
1000
500
400
1000
500
400
ns
ns
ns
CPO
Power Dissipation
Capacitance (Note 5)
(per flip-flop)
500
400
80
pF
10
pF
Maximum input Capacitance
5
10
10
CIN
• Note 5: CPO determines the no load dynamic power consumption. Po =Cpo vcc2 1+ Icc Vee. and the no load dynamic current consumption. Is = CPO Vcc 1+ Icc.
3-86
Typical Applications
N Bit Presettable Binary Ripple Counter with Enable
DATAC
DATAB
DATA A
COUNTER ENABLE
r--
Q
PRESET
J I--
r--
Q
PRESET
J-
r--
Q
PRESET
J i-
•••
TO
NEXT BIT
Q
CLOCK
a
K-
a
K I--
CLOCK
r
L
K-
CLOCK
CLOCK
BIT 3
BIT 2
LSB
TL/F/5073-3
N Bit Parallel Load/Serial Load Shift Register
DATA
INPUT
.¢.
J
DATA A
DATAB
PRESET
PRESET
DATAC
1
1
Q
J
J
Q
PRESET
Q
•••
L..--
CLOCK
K
CLOCK
a
K
CLOCK
r
1:
a
K
--
CLOCK
r
a
-
TL/F/5073-4
3-87
•
J?A National
~ Semiconductor
MM54HC 123A/MM74HC123A
Dual Retriggerable Monostable Multivibrator
General Description
The MM54174HC123A high speed monostable multivibra- '
tors (one shots) utilize microCMOS Technology, 3.5 micron
silicon gate P-well CMOS. They feature speeds comparable
to low power Schottky TTL circuitry while retaining the low
power and high noise immunity characteristic of CMOS circuits.
put pulse equation is simply: PW = (REXT) (CEXT); where PW
is in seconds, R is in ohms, and C is in farads. All inputs are
protected from damage due to static discharge by diodes to
Vee and ground.
Each multivibrator features both a negative, A, and a positive, B,'transition triggered input, either of which can be
used as an inhibit input. Also included is a clear input that
when taken low resets the one shot. The 'HC123 can be
triggered on the positive transition of the clear while A is
held low and B Is held high.
•
•
•
•
•
•
•
•
•
The 'HC123A is retriggerable. That is it may be triggered
repeatedly while their outputs are generating a pulse and
the pulse will be extended.
Pulse width stability over a wide range of temperature and
'supply is achieved using linear CMOS techniques. Tlie out-
C~nnection
Features
Typical propagation delay: 40 ns
Wide power supply range: 2V-6V
Low quiescent current: 80 p,A maximum (74HC Series)
Low input current: 1 p.A maximum
,Fanout of 10 LS-TTL loads
Simple pulse width formula T = RC
Wide pulse range: 400 ns to 00 (typ)
Part to part variation: ± 5% (typ)
Schmitt Trigger A & B inputs enable infinite signal input
. rise and fall limes.
!
Diagram
Dual-In-Llne Package
Timing Component
Vee:
~Q
TO
em
TERMINAL
AI
81
CLRI
Q2
Top View
Cem
Rem
CEXT
8ND
TL/F/5206-1
Order Number MM54HC123AJ or
MM74HC123AJ, N
See NS Package J16A or N16E
Truth Table
,.-"
Inputs
H
Outputs
L
Clear
A
B
Q
Q
L
L,
L
H
H
H
L
X
X
X
H
H
H
X
X
X
L
L
l'
l'
L
J,.
H
H
.f1.
.f1.
.f1.
-U-U-U-
=
=
High Level
Low Level
t =
.J. =
Transillon from Low to High
..n.=
One High Level Pulse
Transition from High to Low
"U"= One Low Level Pulse
X
3-88
=
Irrelevant
TO R/CEXT
TERMINAL
.
TL/F/5206-2
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
-0.5Vto +7.0V
Supply Voltage (Vee>
DC Input Voltage (VIN)
-1.5VtoVcc+ 1.5V
-0.5Vto Vee+0.5V
DC Output Voltage (Vour)
±20mA
Clamp Diode Current (11K, 10K>
±25mA
DC Output Current, per pin (lour)
±50mA
DC Vec or GND Current, per pin (Icc)
-65·C to + 150·C
Storage Temperature Range (TsrG)
500mW
Power Dissipation (PD) (Note 3)
Lead Temperature (TLl
260·C
(Soldering 10 seconds)
Supply Voltage (Vee>
DC Input or Output Voltage
(VIN, Your)
Operating Temp. Range (TAl
MM74HC
MM54HC
Input Rise or Fall Times
(Clear Input)
Vee=2.0V
(tr' til
Vec=4.5V
Vcc=6.0V
Min
2
0
Max
6
Vee
Units
V
V
Parameter
Conditions
Vee
TA=25·C
Typ
74HC
TA=-40t085"C
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
54HC
TA= -55 to 125·C
Units
Guaranteed Limits
VIH
Minimum High Level Input
Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level Input
Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
Iiourl s; 20 I'.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIH orVIL
Iiourl S;4 mA
Ilourls;5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
V
VIN = VIH or VIL
Iiourl s; 4.0 mA
Iiourls; 5.2 mA
VOL
Maximum Low Level
Output Voltage
VIN = VIH or VIL
Ilourls;20/LA
liN
Maximum Input Current
(Pins 7,15)
VIN=VccorGND
6.0V
±0.5
±5.0
±5.0
/LA
liN
Maximum Input Current
(all other pins)
VIN=VCC or GND
6.0V
±0.1
±1.0
±1.0
/LA
Icc
Maximum Quiescent Supply
Current (standby)
VIN=VCCorGND
lour=O /LA·
6.0V
8.0
80
160
/LA
Maximum Active Supply
80
VIN=VCC or GND 2.0V 36
Current (per
1.0
R/CEXT= 0.5Vcc 4.5V 0.33
monostable)
6.0V 0.7
2.0
Nole 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless othelWise specified all voltages are referenced to ground.
110
1.3
2.6
130
1.6
3.2
/LA
mA
mA
Icc
Note 3: Power Dissipation Temperature Derating:
Plastic '"N'" Package: -12mW/'C from 6S'C to 8S'C
Ceramic '"J'" Package: -12mWI'C from 100'C to 12S'C.
Note 4: For a power supply of SV ±10% the worst·case output voltages (YOH. Vou occur for HC at 4.SV. Thus the 4.SV values should be used when designing
with this supply. Worst·case VIH and VIL occur at VCC= S.SV and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) rhe worst·caseleakage current (liN. Icc. and
loz) occur for CMOS at the higher voltage and so the B.OV values should be used.
3-89
o....
~
:J>
......
DC Electrical Characteristics (Note 4)
Symbol
s:::
s:::
:::c
"'"
ClI
s:::
s:::
~
:::c
....o
N
~
AC Electrical Characteristics Vcc=5V, TA=25°C"CL =15pF, tr =tf'=6 ns
Typ
Limit
Units
tpLH
Maximum Trigger Propagation Delay
A, B or Clear to a
22
33
ns,
tpHL
Maximum Trigger Propagation Delay
A, B or Clear to Q
25
42
ns
tpHL
Maximum Propagation Delay, Clear to a
20
27
ns
tpLH
Maximum Propagation Delay, Clear to Q
22
33
ns
tw
Minimum Pulse Width, A, B or Clear
14
26
ns
tREM
Minimum Clear Removal Time
0
ns
tWQ(MIN)
Minimum Output Pulse Width
CEXT=28pF
REXT=2 kO
twa
Output Pulse Width
CEXT=1000pF
REXT=10 kO
Symbol
Parameter
Conditions
400
ns
10
p.s
AC Electrical Characteristics CL = 50 pF tr= tl= 6 ns (unless otherwise specified)
Symbol
.
Parameter
Vee
Conditions
T = 250C
74HC
54HC
A
TA=-40to85"C TA=-55to125"C Units
Typ
Guaranteed Limits
tpLH
Maximum Trigger Pr9pagation
Delay, A, B or Clear to a
2.0V 77
4.5V 26
6.0V 21
169
42
32
194
51
39
210
57
44
ns
ns
ns
tpHL
Maximum Trigger Propagation
Delay, A, B or Clear to
2.0V 88
4.5V 29
6.0V 24
197
48
38
229
60
46
250
67
51
ns
ns
ns
tpHL
Maximum Propagation Delay
Cleartoa
2.0V 54
4.5V 23
6.0V 19
114
34
28
132
41
33
143
45
36
ns
ns
ns
tpLH
Maximum Propagation Delay
CleartoO
2.0V 56
4.5V 25
6.0V 20
116
36
29
135
42
34
147
46
37
ns
ns
ns
tw
Minimum Pulse Width
A, B,Clear
2.0V 57
4.5V 17
6.0V 12
123
30
21
144
37
27
157
42
30
ns
ns
ns
lREM
Minimum Clear
Removal Time
2.0V
4.5V
6.0V
0
0
0
0
0
0
O'
0
0
ns
ns
ns
2.0V 30
4.5V 8
6.0V 7
75
15
13
95
19
16
110
22
19
ns
ns
ns
a
tTLH, lTHL Maximum Output
Rise and Fall TIme
~WQ(MIN)
Minimum Output
Pulse Width
CEXT=28 pF
REXT=2 kO
REXT=6 kO (Vcc=2V)
twa
Output Pulse Width
CEXT=0.1 p.F
REXT=10 kO
CIN
Maximum Input
capaCitance (Pins 7 & 15)
CIN
Maximum Input
Capacitance (other inputs)
6
Min
4.5V
Max
4.5V
3-90
p.s
ns
ns
2.0V 1.!i
4.5V 450
6.0V 380
ms
1
0.9
1
1.1
12
20
20
20
pF
10
10
10
pF
ms
Logic Diagram
0---0
Vee
V'EfZ+-----+~
V.EF1+-----+~
TL/F/5206-5
Theory of Operation
0
G)
CD
A-1l____~--~rtJl
__--n--------®
u
CLEAR
R/CEXT
LJl
I-T-1
TL/F/5206-6
a valid trigger is recognized, which turns on comparator C1 and Nchannel transistor N1
eEXT =0,1 ~F
l!; 0,8
~
a:
g
.
.
....!!!
I~
'I
~
i:5
0.6
I
0.4
~
z
~
I
~ 0.2
~
O.01~
0,1~
11'
TIMING CAPACITOR (F)
,
TLtF/5206-7
I""''
0.92
0,96
1,00
TA=25·C
REXT=10 kll
CEXT=O,1 ~F
Ii
~
=>
1000p
.;:,,56:..:5-:+~(0c::.2:..:5-:-6.,:.;Ve",e,,-)C~x
+[Vce - 0.7]2
ifi
""
1.04
1,06
J"
-1
-2
-3
-4
-5
./
1
3
4
5
,7
POWER SUPPLY (V)
OUTPUT PULSE WIOTH (ms)
TLlF/5206-8
TL/f/5206-9
Typical 1ms Pulse Width
Variation vs. Temperature
Minimum REXT VS.
Supply Voltage
1,0
0,8
~
z
\
~
~
\WORSTjCASE
"'I....
~, TYPICAL
0.2
0
... -0,2
~
-0,4
a:
~ -0.6
-0,8
-1.0
-55
........
'"'1- --
,4
5
6
POWER SUPPlY (V)
0,6
0,4
TLlF/5206-10
Nole: R and C are not sublected to tel!lpereture. The C Is polypropylene.
3-92
I'.
"'"
-15
i'o
25
.....
65
TEMPERATURE (·C)
~
105125
TL/F/5206-11
I
~National
~ Semiconductor
microCMOS
MM54HC125/MM74HC125
MM54HC126/MM74HC126
TRI-STATE ® Quad Buffers
General Description
Features
These are general purpose TRI-STATE high speed non-inverting buffers utilizing microCMOS technology, 3.5 micron
silicon gate P-well CMOS. They have high drive current outputs which enable high speed operation even when driving
large bus capacitances. These circuits possess the low
power dissipation of CMOS circuitry, yet have speeds comparable to low power Schottky TTL circuits. Both circuits are
capable of driving up to 15 low power Schottky inputs.
•
•
•
•
•
Typical propagation delay: 13 ns
Wide operating voltage range: 2-6V
Low input current: 1 )J.A maximum
Low quiescent current: 80 )J.A maximum (74HC)
Fanout of 15 LS-TTL loads
The MM54HC125/MM74HC125 require the TRI-STATE
control input C to be taken high to put the output into the
high impedance condition, whereas the MM54HC126!
MM74HC126 require the control input to be low to put the
output into high impedance.
All inputs are protected from damage due to static discharge by diodes to Vee and ground.
Connection Diagrams
Dual-In-Llne Package
VCC
14
C1
A4
C4
Y4
C3
Dual-In-Line Package
A3
13
12
11
10
9
2
3
4
5
6
A1
C2
Y1
A2
Y2
Y3
VCC
8
C4
14
7
GND
C1
A4
Y4
C3
A3
Y3
13
12
11
10
9
8
2
3
4
5
6
7
A1
C2
Y1
A2
Y2
GND
TLiF/S30B-2
TLiF/S30B-1
Top View
Top View
Order Number MM54HC125J or MM74HC125J, N
See NS Package J14A or N14A
Order Number MM54HC126J or MM74HC126J, N
See NS Package J14A or N14A
Truth Tables
Inputs
Inputs
A
C
H
L
L
H
L
X
Output
Y
H
A
C
H
L
H
H
L
X
L
Z
3-93
Output
y
H
L
Z
Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage (Vee)
-0.5 to + 7.0V
DC Input Voltage (VIN)
-1.5 to Vee + 1.5V
-0.5 to Vee+0.5V
DC Output Voltage (VOUT)
±20mA
Clamp Diode Current (11K. 10Kl
±25mA
DC Output Current. per pin (lOUT)
DC Vee or GND Current. per pin (lee)
±50mA
Storage Temperature Range (T8TG)
- 65'C to + 150"C
Power Dissipation (Po) (Note 3)
500mW
Lead Temp. (Tt.l (Soldering 10 seconds)
260'C
DC Electrical Characteristics
Symbol
Parameter
Operating Conditions
Supply Voltage (Vee>
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
Vee=2.0V
(tr• til
Vee=4.5V
Vce,,:,6.0V
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
'c
'c
1000
500
400
ns
ns
ns
,
(Note 4)
Conditions
TA=25'C
Vee
Typ
74HC
TA= -40t085"C
54HC
TA= -55to 125'C
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
VOH
Minimum High Level
Output Voltage
VIN='VIH orVIL
IIOUTI~20 I'A
VIN=VIHorVIL
IIOUTI~6.0 mA
IiOUTIQ.8mA
VOL
Maximum Low Level
Output Voltage
VIN=VIH or,VIL
IIOUTI~20 I'A
Units
Guaranteed 'Llmlts
\.
V
V
V
(
V
V
Ii
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
O'
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
±0.5
±5
±10
I'A
±1.0
±1.0
I'A
-
VIN = VIH or VIL
IIOUTI~6.0mA
IIOUTI Q.8 mA
loz
liN
Maximum TRI-STATE
Output Leakage
Current
VIN=VIHorVIL
VOUT= Vee or GND
Cn = Disabled
6.0V
Maximum Input
Current
VIN=VeeorGND
6.0V
.'
±0.1
Maximum Quiescent
160
8.0
6.0V
80
VIN=VecorGND
I'A
Supply Current
10UT=0 I'A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specHied all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastiC "'N"' package: -12 mWI"C from 65'C to 8S'C; ceramic "'J"' package: -12 mW/'C from 100'C to 125'C.
Note 4: For a power supply of SV ± 10% the worst case output voltages (VOH. and VoLl occur for HC at 4.5V. Thus the 4.SV values should be used when designing
with this supply. Worst case VIH and VIL occur at Vcc= 5.SV and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (liN. Icc. and
loz) occur for CMOS at the higher voltage and so the 6.0V values should be used.
lee
3-94
i:
i:
AC Electrical Characteristics Vee=5V. TA=25°C. CL =45 pF. tr =t,=6 ns
Parameter
Symbol
Conditions
U'I
oIioo
::z::
Typ
Guaranteed
Limit
Units
o
.....
13
18
ns
13
25
ns
U'I
.......
i:
i:
N
tpHlo IpLH
Maximum
Propagation Delay Time
IpZH
MaXimum
Oulput Enable Time to High Level
RL =1 k!l
IpHZ
Maximum
Output Disable Time from High Level
RL=1 k!l
CL =5pF
17
25
ns
tPZL
Maximum
Output Enable Time to Low Level
RL =1 k!l
18
25
ns
i:
i:
tpLZ
Maximum
Output Disable Time from Low Level
RL =1 k!l
CL=:5pF
13
25
ns
::z::
~
::z::
o.....
N
U'I
.......
U'I
oIioo
o
.....
N
CD
.......
i:
i:
.......
AC Electrical Characteristics Vee = 2.0V to 6.0V. CL = 50 pF. tr=t,= 6 ns (unless otherwise specified)
oIioo
Temperature °C
Symbol
Parameter
Conditions
Vee
54HC174HC
TA=25°C
Typ
tpHL. tpLH
Maximum Propagation
Delay Time
tpLH. tpHL
Maximum Propagation
Delay Time
tPZH. tpZL
74HC
-40t085°C
54HC
-55to 125°C
Units
Guaranteed Limits
2.0V
4.5V
6.0V
40
14
12
100
20
17
125
25
21
150
30
25
ns
ns
ns
CL=150pF
2.0V
4.5V
6.0V
35
14
12
130
26
22
163
33
28
195
39
33
ns
ns
ns
Maximum Output
Enable Time
RL =1 k!l
2.0V
4.5V
6.0V
25
14
12
125
25
21
156
31
26
188
38
31
ns
ns
ns
tpHZ. tpLZ
Maximum Output
Disable Time
RL =1 k!l
2.0V
4.5V
6.0V
25
14
12
125.
25"
21
156
31
26
188
38
31
ns
ns
ns
tPZL. tPZH
Maximum Output
Enable Time'
CL =150pF
RL =1 k!l
2.0V.
4.5V
6.0V
35
15
13
140
28
24
175
35
30
210
42
36
ns
ns
ns
tTLH. tTHL
Maximum Output
Rise and Fall Time
CL =50 pF
2.0V
4.5V
6.0V
30
60
12
10
75
90
18
15
ns
ns
ns
,
7
6
15
13
CIN
Input Capacitance
5
10
10
10
pF
COUT
Output Capacitance Outputs
15
20
20
20
pF
CPD
Power Dissipation
Capacitance (Note 5)
(per gate)
Enabled
Disabled
pF
45
pF
6
.Note 5: CPO determines the no ioad dynamic power consumption, Po = Cpo Vcc21+ IcC Vec. and the no load dynamic current consumpUon, is = Cpo Vee 1+ Icc.
3·95
::z::
o
.....
~
N
r---------------------------------------------------------------~
C")
.(.)
:z:: ~National,
~
::E
::E
~
C")
.:z::
..,.
(.)
..,
::E
::E
PRELIMINARY
~ Semiconductor
microCMOS
MM54HC132/MM74HC,132 Quad.2-lnput
NAND Schmitt Trigger
General Description
Features
The MM54HC132/MM74HC132 utilizes microCMOS Technology, 3.5 micron silicon gate P-well CMOS, to achieve the
low power dissipation and high noise immunity of standard
CMOS, as well as the capability to drive 10 LS-TTL loads.
•
•
•
•
•
•
The 54HC/74HC logic family is functionally and pinout compatible with the standard 54LS174LS logic family. All inputs
are protected from damage due to static discharge by internal diode clamps to Vee and gn;>und.
'Typical propagation delay: 12 ns
Wide power supply range: 2V -6V
Low quiescent current: 20 p.A maximum (74HC Series)
Low input current: 1 p.A maximum
Fanout of 10 LS-TTL loads
Typical hystereSis voltage: 0.9V at Vcc=4.5V
Connection and Logic Diagrams
Dual-In-Une Package
vee
B4
A4
Y4
B3
A3
Y3
8
A1
B1
Y1
A2
B2
Y2
TL/F/5309-1
Top View
Order Number MM54HC132J or MM74HC132J,N
See NS Package J14A or N14A
81 (2)
A2 (4)
82 (5)
Y=AB
(9)
A3
TL/F/5309-2 .
3-96
Absolute Maximum Ratings
Supply Voltage (Veel
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K. 10K)
DC Output Current. per pin (loUT)
DC Vcc or GND Current. per pin (Ieel
Storage Temperature Range (TSTG)
Power Dissipation (PD) (Note 3)
Lead Temperature (TLl
(Soldering 10 seconds)
-
Operating Conditions
(Notes 1 & 2)
-0.5 to + 7.0V
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
-1.5 to Vee+ 1.5V
-0.5 to Vee+0.5V
±20mA
±25mA
±50mA
-65'Cto +150'C
500mW
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
'C
'C
260'C
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25'C
74HC
TA= -40 to 85'C
Typ
VT+
VT-
VH
VOH
Positive
GOing Threshold Voltage
Negative
Going Threshold Voltage
Hysteresis Voltage
Minimum High Level
Output Voltage
Maximum Low Level
Output Voltage
Units
Guaranteed Limits
Min
Max
2.0V
1.0
1.5
0.95
1.5
0.95
1.5
V
V
Min
Max
4.5V
2.30
3.15
2.25
3.15
2.25
3.15
V
V
Min
Max
6.0V
3.0
4.2
2.95
4.2
V
V
Min
Max
2.0V
0.3
0.8
2.95
4.2
0.3 0.85
0.3
0.85
V
V
Min
Max
4.5V
0.9
2.0
0.9
2.05
0.9
2.05
V
V
Min
Max
6.0V
1.2
2.3
1.2
2.35
1.2
2.35
V
V
Min
Max
2.0V
2.0V
0.2
1.2
0.2
1.2
0.2
1.2
V
V
Min
Max
4.5V
4.5V
0.4
2.25
0.4
2.25
0.4
2.25
V
V
Min
Max
6.0V
6.0V
0.6
3.0
0.6
3.0
0.6
3.0
V
V
VIN=VIHorVIL
IIOUTI::O:20 ~A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
IIOUTI:S:4.0 mA
lOUT ::O:5.2mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VIHorVIL
IIOUTI::O:4.0 rnA
lOUT ::O:5.2mA
VOL
54HC
TA=-55t0125'C
VIN=VIH orVIL
IIOUTI::O:20 ~A
liN
Maximum Input
Current
VIN=VCCorGND
6.0V
±0.1
±1.0
±1.0
~A
Icc
Maximum Quiescent
Supply Current
VIN = Vee or GND
6.0V
2.0
20
40
~
IOUT=O~A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating -"Iastic "N" package: -12 mW/'C from 6S'C to 8S'C; cerernic "J" package: -12 mWI'C from 100'C to 12S'C.
Note 4: For a power supply ofSV ± 10% the worst case output voltages (VOH. and VoLl occur for HC at 4.SV. Thus the 4.SV values should be used when designing
with this supply. Worst case VIH and VIL occur at VCC~ S.SV and 4.SV respectively. (The VIH value at S.SV is 3.8SV.) The worst case leakage current (liN. ICC. and
loz) occur for CMOS at the higher voltage and so the B.OV values should be used.
3-97
•
AC Electrical Characteristics Vcc=5V. TA=25°C.CL =15pF.t,=t,=6ns
Symbol
Parameter
Conditions
tpHL. tpLH
Maximum Propagation
Delay
Typ
Guaranteed
Limit
Units
12
20
ns
1
AC Electrical Characteristics Vcc=2.0Vto 6.0V. CL =50 pF. t r =t,=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA;"25°C
Typ
74HC
TA=-40t085"C
54HC
TA= -55to 125°C
Units
Guaranteed Limits
Maximum Propagation
Delay
2.0V
4.5V
6.0V
63
13
11
125
25
21
158
32
27
186
37
32
ns
ns
ns
tTLH. tTHL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
CPO
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input
Capacitance
tpHL. tpLH
(per gate)
pF
5
10
10
pF
Note 5: Cpo determines !he no Iced dynamiC power consumption. Po = Cpo Vcr!- 1+ lee Vee. and the no load dynamic current consumption. IS = Cpo Vee 1+ Icc.
,
3·98
~National
~ Semiconductor
microCMOS
MM54HC133/MM74HC133
13-lnput NAND Gate
General Description
Features
This NAND gate utilizes microCMOS Technology, 3.5 micron silicon gate P-well CMOS, to achieve operating speeds
similar to LS-TIL gates with the low power consumption of
standard CMOS integrated circuits. All gates have buffered
outputs. All devices have high noise immunity and the ability
to drive 10 LS-TIL loads. The 54HC174HC logic family is
functionally as well as pin-out compatible with the standard
54LS174LS logic family. All inputs arE! protected from damage due to static discharge by internal diode clamps to Vee
and ground.
•
•
•
•
•
Typical propagation delay: 20 ns
Wide power supply range: 2-6V
Low quiescent current: 20 ",A maximum (74HC Series)
Low input current: 1 ",A maximum
Fanout of 10 LS-TIL loads
Connection and Logic Diagrams
Dual-In-Llne Package
vcc
15
116
14
y
H
K
L
M
13
12
11
110
9
1
,
p
'C,
1
A
2
B
3
c
4
D
5
E
6
F
17 18
G
GND
TLlF/5134-1
Top View
Order Number MM54HC133J or MM74HC133J, N
See NS Package J16A or N16E
A--[)<>....,
B--C~--I
c--[)<>.....I
D--[)<>....,
E--C~--I
F --r.>o-..J
. G--C>O--,
H--Doo--I
K--Doo--I
L --r.>O-..J
Tl/F/5134-2
3-99
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
Supply Voltage (Vee>
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K. 10K>
DC Output Current. per pin (lOUT)
DC Vee or GND Current. per pin (Ice>
Storage Temperature Rarge (TSTG)
Power Dissipation (Po) (Note 3)
Lead Temperature (TO
(Soldering 10 seconds)
Supply Voltage (Vee>
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TAl
MM74HC
MM54HC
Input Rise or Fall Times
Vee = 2.0V
(tr• ttl
Vee=4.5V
Vee=6.0V
-0.5 to + 7.0V
-1.5 to Vee + 1.5V
-0.5 to Vee+0.5V
±20mA
±25mA
±50mA
-65·C to + 150·C
500mW
260·C
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
·,C
·C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
TA=25·C
Vee
74HC
TA=-40to 85"C
54HC
TA= -55 to 125·C
Units
Guaranteed Limits
Typ
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0\1
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
4.5V
6.0V
VIN = VIH or VIL
IIOUTI :!: 20 p.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
.4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIH
IIOUTI :!:4.0 mA
IIOUTI :!: 5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = Vee or GND
6.0V
±0.1
±1.0
±1.0
",A
VIN =VIH or VIL
IIOUTI:!:4.0 mA
IIOUTI:!:5.2 mA
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
VIN=VIH
IIOUTI:!:20 ",A
40
Maximum Quiescent VIN=VeeorGND 6.0V
2.0
20
/LA
Supply Current
10UT=0 ",A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwisa specified all voltages are referenced to ground.
Nole 3: Power Dissipation temperature derating - plastiC "N" package: -12 mWrc from 65"C to 85"C; ceramic "J" package: -12 mWrC from 1OO"C to 125"C,
Note 4: For a power supply of 5V ± 10% the worst case output voltages (YaH. and Vou occur for HC at4,5V. Thus the 4.5V values should be usad when designing
with this supply. Worst casa VIH and VIL occur at Vcc= 5.5V and 4.5V respectively. (The VIH value at 5.5V Is 3.85V.) The worst casa leakage current (lIN. ICC. and
Iozl occur for CMOS at the higher voltage and so the 6.0V values should be usad.
Icc
3-100
AC Electrical Characteristics Vcc=5V. TA=25°C. CL =15pF. t,=t,=6ns
Symbol
Parameter
Conditions
tpHL. tpLH
Maximum Propagation Delay
Typ
Guaranteed
Limit
Units
20
30
ns
AC Electrical Characteristics Vcc= 2.0V to 6.0V. CL = 50 pF. t,=t,= 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=25°C
Typ
74HC
TA= -40to 85°C
54HC
TA= -55 to 125°C
Units
Guaranteed Limits
tPHL.
tpLH
Maximum Propagation
Delay
2.0V
4.5V
6.0V
66
23
18
160
35
30
190
42
36
220
49
42
ns
ns
ns
trLH.
tTHL
Maximum
Output Rise and
Fall Time
2.0V
4.5V
6.0V
25
7
6
75
15
13
95
19
16
110
22
19
ns
ns
ns
CPO
Power Dissipation
Capacitance (Note 5)
34
pF
Maximum Input Capacitance
10
10
10
pF
5
CIN
Nota 5: CPO determines the no load dynamic pcwer consumption. Po =Cpo Vcr:!- f+ lee Vee. and the no load dynamic current consumption. Is = CPO Vee f+ Icc-
•
.
3·101
~National
PRELIMINARY
)
\
~ Semiconductor
microCMOS
MM54HC'137/MM74HC137 3-to-8 Line
Decoder With Addr~ss Latches
(Inverted Output)
General Description
This device utilizes microCMOS Technology, 3.5 micron silicon gate P-well CMOS, to implement a three-to-eight line
decoder with latches on the three address inputs. When GL
goes from low to high, the address present at the select
inputs (A, B and C) is stored in the latches. As long as GL
remains high 1)0 address changes will be recognized. Output enable controls, Gl and G2, control the state of the
outputs independently of the select or latch-enable inputs.
All of the outputs are high unless Gl is high and G2 is low.
The HC137 is ideally suited for the implementation of glitchfree decoders in stored-address applications in bus oriented
systems.
The 54HC174HC logiC family is speed, function and pin-out
compatible with the standard 54LS174LS logic family. All
inputs are protected from damage due to static discharge by
diodes to Vee and ground.
Features
•
•
•
•
Typical propagation delay: 20 ns
Wide supply range: 2-6V
·Latched inputs for easy interfacing.
Fanout of 10 LS-TTL loads.
Connection and Functional Block Diagrams
Dual·ln·Llne Package
DATA OUTPUTS
SELECT
INPUTS
Vcc YO
Y1
Y2
Y3
Y4
Y5
Y6
Y3
DATA
OUTPUTS
YB
A
62
--
81
Y7
2
ABC
SELECT
TL/F/5310-1
INPUTS
ENABLE
{= ~;;";:}~}-~;':>:;r)---_!J~§3la:)
17} Y7
81 16}
Order Number MM54HC137J
or MM74HCI37J,N
See NS Package J16A or N16E
TL/F/5310-2
3-102
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
Supply Voltage (Vee!
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K. loKI
DC Output Current. per pin (lOUT)
DC Vee or GND Current. per pin (IcC!
Storage Temperature Range (Tsm)
Power Dissipation (PD) (Note 3)
Lead Temperature (TLl
(Soldering 10 seconds)
Supply Voltage (Vee!
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
Vee=2.0V
(tr. ttl
Vee=4.5V
Vee=6.0V
-0.5 to +7.0V
-1.5toVee+ 1.5V
-0.5 to Vee + 0.5V
±20'mA
±25mA
±50mA
-65'C to + 150'C
500mW
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
I
260'C
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
TA=25'C
Vee
74HC
TA= -40 to 85'C
Typ
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
3.98
5.48
3.84
5.34
3.7
5.2
V
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
l!ouTI';:;20 /LA
VIN=VIHorVIL
IIOUTI';:;4.0 mA
IIOUTI';:;5.2 mA
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
VIN=VIH orVIL
IIOUTI';:;20 /LA
2.0V
4.5V
6.0V
2.0
4.5
6.0
4.5V
6.0V
2.0V
4.5V
6.0V
0
0
0
VIN = VIH or VIL
IIOUTI';:;4.0 mA
IIOUTI';:;5.2 mA
4.5V·
6.0V
0.26
0.26.
0.33
0.33
0.4
0.4
V
V
VIN = Vee or GND
6.0V
±0.1
±1.0
±1.0
/LA
80
160
/LA
Maximum Quiescent VIN=VeeorGND 6.0V
8.0
Supply Current
IOUT=O /LA
Nole 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Icc
Note 2: Unless otherwise specified all voltages are referenced to ground.
Nole 3: Power Dissipation temperature derating - plastic "N" package: -12 mWI"C from 6S'C to as'c; ceramic "J" package: -12 mWI'C from 100'C to 12S'C.
Nole 4: For a power supply of SV ± 10% the worst case output voltages (VOH. and You occur for HC at4.SV. Thus the 4.SV values should be used when designing
with this supply. Worst case VIH and VIL occur at Vcc= S.SV and 4.SV respectively. (The VIH value at S.SV is 3.85V.) The worst case lea,-",ge current (liN. ICC. and
loz) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3-103
AC Electrical Characteristics Vcc=5V, TA=25"C, CL =15pF, tr=tj=6ns
Symbol
Parameter
Typ
Conditions
Guaranteed
Limit
Units
tpLH
Maximum Propagation Delay, A, B or C to any Y Output
14
29
ns
tpHL
Maximum Propagation Delay, A, B or C to any Y Output
20
42
ns
tpLH
Maximum Propagation Delay G2 to any Y Output
12
22
ns
tpHL
Maximum Propagation Delay G2 to any Y Output
15
34
ns
tpLH
Maximum Propagation Delay G1 to any Output
13
25
ns
tpHL
Maximum Propagation Delay GL to any Output
17
34
ns
.tpLH
Maximum Propagation GL to Output
15
30
ns
tpHL
Maximum Propagation Delay GL to Output
22
34
ns
Is
Minimum Setup Time at A, Band C Inputs
20
ns
tH
Minimum Hold Time at A, Band C Inputs
0
ns
tw
Minimum Pulse Width of Enabling Pulse at GL
16
ns
,
AC Electrical Characteristics CL = 50 pF, tr=tj=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=2S"C
Typ
74HC
TA=-40to8S"C
S4HC
TA=-SSto12S"C
Units
Guaranteed Limits
tpLH
Maximum Propagation Delay
A, B or C to any Y Output
2.0V
4.5V
6.0V
85
17
14
170
34
29
214
43
36
253
-51
43
ns
ns
ns
tpHL
Maximum Propagation Delay
A, B or C to any Y Output
2.0V
4.5V
6.0V
120
24
20.
240
48
41
302
60
51
358
72
61
ns
ns
ns
tpLH
Maximum Propagation Delay
G2 to any Y Output
2.0V
4.5V
6.0V
65
13
11
130
26
22
164
33
28
194
39
33
ns
ns
ns
tpLH
Maximum Propagation
Delay G1 to Output
2.0V
4.5V
6.0V
75
15
13
150
30
26
189
38
32
224
45
38
ns
ns
ns
tpHL
Maximum Propagation
Delay G1 to Output
2.0V
4.5V
6.0V
98
20
17
195
39
33
246
49
42
291
58
• 49
ns
ns
ns
tpLH
Maximum Propagation
Delay GL to Output
2.0V
4.5V
6.0V
88
18
15
175
35
30
221
37
261
52
44
ns
ns
ns
tpHL
Maximum Propagation
Delay GL to Output
2.0V
4.5V
6.0V
125
25
21
250
50
43
315
63
54
373
75
63
ns
ns
ns
tpHL
~aximum
Propagation Delay
G2, to any Y Output
2.0V
4.5V
6.0V
98
20
17
195
39
33
246
49
42
291
58
49
ns
ns
ns
Is
Minimum Setup Time
at A, Band C inputs
2.0V
4.5V
6.0V
100
20
17
125
25
21
150
30
25
ns
ns
ns
tH
Minimum Hold Time
at A, Band C inputs
2.0V
4.5V
6.0V
50
10
8
63
13
11
7S
15
13
ns
ns
ns
tTLH, tTHL
Output Rise and
Fall Time
2.0V
4.5V
6.0V
75
15
13
95
19
16
110
22
19
ns
ns
ns
tw
Minimum Pulse Width
of Enabling Pulse at GL
2.0V
4.5V
6.0V
80
16
14
100
20
18
120
24
21
ns
ns
ns
CPD
Power Dissipation
Capacitance (Note 5)
30
8
7
75
44
pF
'5
10
Maximum Input Capacitance
pF
10
10
CIN
Note 5: Cpo determines the no load dynamic power consumption. Po =Cpo Vcx;2 f+ lee Vee. and the no load dynamic current consumption. Is = Cpo Vee f+ lee.
3-104
Typical Application
STROBE DECODER ENABLE
_ _- - - - _ - - - - - . . . ,
---i-----+------.
xo--4-----+---~
XI --4-----+----,
X2--4-----+---.
INPUT
ADDRESS
I
)
::::::~::::;:~::~::::::::::~~~:::t::::::::::;:~::~:::::: O&~~XS
X5--r_-._+-r-+----~~_i-_+----~t_r__;~---
o I 2 3 4 5 6 7
o I 2 3 4 5 6 7
o I ,2 3 4 5 6 7
~-----------------~vr---------------------~
OUTPUTS
TL/F/5310-3
6·Llne to 64·Llne Decoder with Input Address Storage
Truth Table
Inputs
Enable
B A VO V1
X X H H
X X H H
V2
V3
V4
V5
V6
V7
X
C
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
L
X
X X Output corresponding to stored
GL
G1
G2
X
X
X
H
L
L
L
L
L
H
Outputs
Select
=
high level, L
=
low level. X
address L; all others, H
=
irrelevant
3·105
co
....
o
r-----------------------------------------------------------------------------------~
CO)
::E:
~
"'"
:iii
:iii
co
~National
~ Semiconductor
microCMOS
MM54HC138/MM74HC138
....
o 3-to-8 Line Decoder
::E:
CO)
~
It)
:iii
:iii
General Description
This decoder utilizes microCMOS Technology, 3.5 micron
silicon gate P-well CMOS, and is well suited to memory address decoding or data routing applications. The circuit features high noise immunity and low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low power Schottky TTL logic.
The decoder's outputs can drive 10 low power Schottky TTL
equivalent loads, and are functionally and pin equivalent to
the 54LS138174LS138. All inputs are protected from damage due to static discharge by diodes to Vee and ground.
The MM54HC138/MM74HC138 has 3 binary select inputs
(A, B, and C). If the device is enabled these inputs determine which one of the eight normally high outputs will go
low. Two active low and one active high enables (Gl, G2A
and G2B) are provided to ease the cascading of decoders.
•
•
•
•
•
Features
Typical propagation delay: 20 ns
Wide power supply range: 2V -6V
Low quiescent current: 80 p.A maximum (74HC Series)
Low input current: 1 p.A maximum
Fanout of 10 LS-TTL loads
Connection and Logic Diagrams
Dual-In-Line Package
DATA OUTPUTS
Vee
1,6
YO
1S'
Y1
Y2
14
Y3
13
Y4
12
11
Y5
9
p.
r-
1
V6'
10
2
3
,--~~---,C.
5
4
m
SELECT
m
ENA8LE
TlIPVIEW
6
01
7
Y7
OUTPUT
1
8
GND
TLiF/5120-1
Order Number MM54HC138J
or MM74HCI38J, N
See NS Package J16A or N16E
G1-..!---~L~-------I
Truth Table
Inputs
Enable
Gl
G2*
X
H
L
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
Outputs
Select
A
YO
VI
Y2
Y3
Y4
Y5
Y6
V7
X X X
.X X X
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
C
L
L
L
L
H
H
H
H
B
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
'G2~G2A+G2B
H ~ high level, L ~ low level, X ~ don't care
3-106
Absolute Maximum Ratings
Operating Conditions
(Notes 1 & 2)
-0.5 to +7.0V
Supply Voltage (Ved
Supply Voltage (Vee)
DC Input or Output Voltage
(YIN, VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
Vee=2.0V
(lr,ttl
Vee=4.5V
Vee=6.0V
-1.5 to Vee + 1.5V
DC Input Voltage (YIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K, 10K)
DC Output Current, per pin (lOUT)
DC Vee or GND Current, per pin (ICc!
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
-0.5 to Vee+0.5V
±20mA
±25mA
±50mA
-65·C to + 150·C
Lead Temp. (TL.l (Soldering 10 seconds)
500mW
260·C
Min
2
Max
6
Units
V
0
Vee
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
,
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=2S·C
74HC
TA= -40 to 8S·C
S4HC
TA=-SStoI2S·C
Units
Guaranteed Limits
Typ
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
.
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
lIoUTIs:20 /LA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34·
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
IIOUTIS:4.0 mA
IIOUTI S:5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VeeorGND
6.0V
±0.1
±1.0
±1,0
/LA
80
160
/LA
VIN = VIH or VIL
IIOUTIS:4.0 mA
IIOUTIS:5.2 mA
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
VIN = VIH or VIL
,IIOUTIS:20 /LA
Maximum Quiescent VIN = Vee or GND 6.0V
8.0
Supply Current
IOUT=O/LA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Icc
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mW I'C from 65'C to 85'C; ceramic "J" package: -12 mWI'C from 1OO'C to 125'C.
Nota 4: For a power supply of 5V ± 10% the worst case output voltages (YOH, and VOU occur for HC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at Vcc~ 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.l The worst case leakage current (liN. Icc, and
lozl occur for CMOS at the higher voltage and so the 6.0V values should be used,
3-107
.
AC Electrical Characteristics Vcc=5V. TA=25°C. CL =15 pF. t r =t,=6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
tpLH
Maximum Propagation
Delay. Binary Select to any Output
18
25
ns
tpHL
Maximum Propagation
Delay. Binary Select to any Output
28
35
ns
tPHL. tpLH
Maximum Propagation
Delay. G1 to any Output
18
25
ns
tpHL
Maximum Propagation
Delay G2A or G2B to
Output
23
30
ns
tpLH
Maximum Propagation
Delay G2A or G2B to
Output
18
25
ns
AC Electrical Characteristics CL = 50 pF. tr=t,= 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25°C
Vee
Typ
tpLH
. Maximum Propagation
Delay Binary Select to
any Output Low to High
74HC
TA=-40t085"C
54HC
TA= -55to 125"C
Units
Guaranteed Limits
2.0V
4.5V
6.0V
75
15
13
150
30
26
189
38
32
224
45
38
ns
ns
ns
tpHL
Maximum Propagation
Delay Binary Select to any
Output High to Low
2.0V
4.5V
6.0V
100
20
17
200
40
34
252
40
43
298
60
51
ns
ns'
. ns
tpHL. tpLH
Maximum Propagation
Delay G1 to any
Output
2.0V
4.5V
6.0V
75
15
13
150
30
26
189
38
32
224
45
38
ns
ns
ns
tpHL
Maximum Propagation
Delay G2A or G2B to
Output
2.0V
4.5V
6.0V
82
28
22
175
35
30
221
44
37
261
52
44
ns
ns
ns
tpLH
Maximum Propagation
Delay G2A or G2B to
Output
2.0V
4.5V
6.0V
75
15
13
150
30
26
189
38
32
224
45
38
ns
ns
ns
tTLH. tTHL
Output 'Rise and
Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
.19
16
110
22
19
ns
ns
ns
CIN
Maximum Input
Capacitance
3
10
10
10
p.F
CPD
Power Dissipation
Capacitance
{Note 5)
75
Note 5: CPO determines the no load dynamic power consumption. Po ~ Cpo vcc2 1+ lee Vee. and the no load dynamic current consumption.
3-108
p.F
Is~ Cpo Vee 1+ lee.
·~National
~ Semiconductor
microCMOS
MM54HC139/MM74HC139
Dual 2-To-4 Line Decoder
General Description
This decoder utilizes microCMOS Technology, 3.5 micron
silicon gate P-well CMOS, and is well suited to memory address decoding or data routing applications. It possesses
the high noise immunity and low power consumption usually
associated with CMOS circuitry, yet has speeds comparable
to low power Schottky TIL logic.
The MM54HC139/MM74HC139 contain two independent
one-of-four decoders each with a single active low enable
input (G1, or G2). Data on the select inputs (A1, and B1 or
A2, and B2) cause one of the four normally high outputs to
go low.
The decoder's outputs can drive 10 low power Schottky TIL
equivalent loads, and are functionally as well as pin equiva-
lent to the 54LS139174LS139. All inputs are protected from
damage due to static discharge by diodes to Vee and
ground.
Features
• Typical propagation delays Select to outputs (4 delays): 18 ns
Select to output (5 delays): 28 ns
Enable to output: 20 ns
• Low power: 40 p.W quiescent supply power
• Fanout of 10 LS-TIL devices
• Input current maximum 1 p.A, typical 10 pA
Truth Table
Connection Diagram
Dual-In-Line Package
SELECT
ENABLE
Vee
116
61
~
2YO
112
2Y1·
111
2Y2
114
B2
1t3
I
I
!
!
!
A2
15
'HC139
DATA OUTPUTS
OUTPUT
SELECT
I.......c
-
Inputs
Ito
Enable
9
p-
OUTPUT BUFFER
Outputs
Select
G
B
A
YO
Y1
Y2
Y3
H
L
L
L
L
X
X
L
L
H
H
L
H
L
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H ~ high level, L ~ low level, X ~ don't care
OUTPUT
SELECT
r--O
I
1
ENABLE
G1
12
Al
p-
OUTPUT BUFFER
J3
81
-----.,.......,
SELECT
Y
14
Y
Y
15
6
lY2
lYl
1
7
lY3,
1
8
GND
OATA OUTPUTS
TLlF/5311-1
Order Number MM54HC139J or MM74HC139J, N
See NS Package J16A or N16E
Logic Diagram
% MM54HC139/MM74HC139
ENABLE
SELECT
- - - - I ';;~r=;:==;:[J
G
{:--+. . . ...:><:-....+++-I-...-I
O~TPUTS
TLlF/5311-2
3-109
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
-0.5 to + 7.0V
Supply Voltage (Veel
DC Input Voltage (VIN)
-1.5 to Vec+1.5V
Supply Voltage (Vee)
DC Output Voltage (vOUT)
-0.5 to Vee+0.5V
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
±20mA
Clamp Diode Curreht (liK, loKI
DC Output Current, per pin (lOUT)
±25mA
DC Vee or GND Current, per pin (Ieel
±50mA
-65·C to + 150·C
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
Max
6
Units
V
0
Vee
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
Vee=2.0V
(tr, til
Vee=4.5V
Vee=6.0V
500mW
Lead Temp. (TLl (Soldering 10 seconds)
Min
2
260·C
DC Electricai Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25·C
74HC
TA= -40to85·C
Typ
54HC
TA=-55to125·C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
VOH
Minimum High Level
Output Voltage
YiN = VIH or VIL
IIOUTI:S:20 p.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3,7
5.2
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIHorVIL
IIOUTI :S:4.0 mA
IIOUTI:S:5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VIHorVIL
IIOUTI:S:4.0 mA
IIOUTI:S:5.2 mA
-VOL
Maximum Low Level
Output Voltage
V
VIN=VIHorVIL
IIOUTI:S:20 p.A
V
V
V
liN
Maximum Input
Current
VIN=VeeorGND
6.0,":
±0.1
±1.0
±1.0
p.A
lee
Maximum Quiescent
Supply Current
VIN=VeeorGND
10UT=0 p.A
6.0V
8.0
80
160
p.A
Nota 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise sp~fied all voltages are referenced to ground.
Note 3: Power Dissipation tempaneture derating - plastiC "N" package: -12 mWI'C from 6S'C to 8S'C; ceramic "J" package: -12 mWI'C from lOO'C to 12S'C.
Nota 4: For a power supply of SV ± 10% the worst case output voltages (YOH, and Vou occur for HC at4.SV. Thus the 4.SV values should be used when designing
with this supply. Worst caseVIH and VIL occur at Vee = S.SV and 4.SV respectively. (The VIH value at S.SV is 3.8SV.) The worst case leakage current (liN. Icc. and
lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
3-110
AC Electrical Characteristics
Vcc=5V, TA=25"C, CL =15 pF, t,=tf=6 ns
Typ
Guaranteed
Limit
Units
Maximum Propagation
Delay, Binary Select to any Output
4 levels of delay
18
30
ns
tpHL, tpLH
Maximum Propagation
Delay, Binary Select to any Output
5 levels of delay
28
38
ns
tpHL, tpLH
Maximum Propagation
Delay, Enable to any Output
19
30
ns
Symbol
Parameter
tpHL, tpLH
Conditions
AC Electrical Characteristics CL = 50 pF, t,=tf= 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=25"C
Typ
74HC
TA= -40 to 85"C
54HC
TA= -55to 125"C
Units
Guaranteed Limits
tpHL, tpLH
Maximum Propagation
Delay Binary Select to
any Output 4 levels of delay
2.0V
4.5V
6.0V
110
22
18
175
35
30
219
44
38
254
51
44
ns
ns
ns
tpHL, tpLH
Maximum Propagation
Delay Binary Select to any
Output 5 levels of delay
2.0V
4.5V
6.0V
165
33
28
220
44
38
275
55
47
320
64
54
ns
ns
ns
tpHL, tpLH
Maximum Propagation
Delay Enable to any
Output
2.0V
4.5V
6.0V
115
23
19
175
35
30
219
44
38
254
51
44
tTLH, tTLH
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
CIN
Maximum Input
Capacitance
3
10
10
10
I'oF
CpD
Power Dissipation
Capacitance (Note 5)
,
(Note 5)
75
,
ns
ns
ns
I'oF
Note 5: CPD determines the no load dynamic power consumption, PO=CPD Vcr? 1+lcc VeG. and the no load dynamic c!Jrrentconsumption, Is=CPD VCCf+ ICC.
'.
3-111
~
oo:r
o::z::
,----------------------------------------------------------------------------,
~National
----
~ Semiconductor
MM54HC147/MM74HC147
'"
....ooo:r 10-to-4 Line Priority Encoder
oo:r
~
:E
:E
\.
J
microCMOS
.~
::z::
oo:r
General Description
:E
:E
This high speed 10-to-4 Line Priority Encoder utilizes microCMOS Technology, 3.5 micron silicon gate P-well CMOS. It
possesses .the high noise immunity and low power consumption of standard CMOS integrated circuits. This device
is 1ully buffered, giving it a fanout of 10 LS-TTL loads.
The MM54HC147/MM74HC147 features priority encoding
of the inputs to ensure that only the highest order data line
is encoded. Nine input lines are encoded to a four line BCD
output. The implied decimal zero condition requires no input
condition as zero is encoded when all nine data lines are at
a high logic level. All data inputs and outputs are active at
the low logic level.
LI)
The 54HC/74HC logic family is functionally as well as pinout compatible with the standard 54LS174LS logic family.
All inputs are protected from damage due to static discharge by internal diode clamps to Vee and ground.
Features
• Low quiescent power consumption: 40 /JoW maximum at
25°C
• High speed: 31 ns propagation delay (typical)
• Very low input current: 10-5 /JoA typical
• Wide supply range: 2V to 6V
Connection and Logic Diagrams
Dual-in-Line Package
JNPUTS
Vcc
NC
OUTPUT
3
D
OUTPUT
9
(11)
1
A
10
9
(12)
(9)
2
A
9
4
(13)
A
3
(1)
5
4
--
6
C
INPUTS
B
4
8
. (7)
GND
B
(2)
OUTPUTS
TL/F/SO07-1
5
Top View
(3)
Order Number MM54HC147J or MM74HCI47J;N
See NS Package J16A or N16E
(6)
Truth Table
Inputs
Outputs
1 . 2
3
4
5
6
7
8 ,9
D
C
B
A
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X X X X
X X X L
X X L H
X L H H
L
H
H
H
H
L
L
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
L
H
~
L
H
L
H
H
L
H
H
H
H
High Logic Level, L
c
(4)
H
H
H
H
H
~
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
Low Logic Level, X
~
(5)
(14)
~-DO+~~--~~---------------
D
9
TL/F/S007-2
Irrelevant
•
3-112
Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage (Vecl
-0.5 to +7.0V
DC Input Voltage (VIN)
-1.5to Vcc+ 1.5V
DC Output Voltage (VOUT)
-0.5toVee+ 0.5V
±20mA
Clamp Diode Current (11K. 10Kl
±25mA
DC Output Current. per pin (lOUT)
±50mA
DC Vee or GND Current. per pin (Ieel
-65·Cto +150·C
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
500mW
260·C
Lead Temp. (Tt.l (Soldering 10 seconds)
Operating Conditions
Supply Voltage (Veel
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
Vee=2.0V
(tr.ttl
Vee=4.5V
Vee=6.0V
..
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25·C
74HC
TA= -40 to 85·C
Typ
Minimum High Level
Input Voltage
VIH
VIL
Maximum Low Level
Input Voltage
VOH
Minimum High Level
Output Voltage
VIN=VIH orVIL
IIOUTI';;20 /LA
Maximum Low Level
Output Vol~ge
Maximum Input
Current
liN
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
V
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.7
5.2
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
IIOUTI ';;4.0 mA
IIOUTI ';;5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VeeorGND
6.0V
±0.1
±1.0
±1.0
/LA
80
160
/LA
VIN = VIH or VIL
IloUTI';;20 /LA
Maximum Quiescent VIN=VeeorGND 6.0V
8.0
Supply Current
10UT=0 /LA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
~:
V.
2.0
4.5
6.0
Icc
Note
Units
Guaranteed Limits
2.0V
4.5V
6.0V
VIN = VIH or VIL
IIOUTI ,;; 4.0 mA
IIOUTI ,;; 5.2 mA
VOL
54HC
TA= -55 to 125·C
Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mWI"C from 6S'C to 8S'C; ceramic "J" package: -12 mWI'C from 1OO'C to 12S'C.
Note 4: For a power supply of SV ± 10% the worst case output voltages (VOH. and VOU occur for HC at 4.SV. Thus the 4.SV values should be used when designing
with this supply. Worst case VIH and VIL occur at Vcc= S.SV and 4.SV respectively. (The VIH value at S.SV is 3.8SV.) The worst case leakage current (liN. Icc. and
lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
3·113
AC Electrical Characteristics Vcc= 5V, TA = 25'C, CL = 15 pF; tr=tf;= 6 ns
"
Symbol
Parameter
tpHL, tpLH
Maximum Propagation
Delay
Conditions
Typ
Guaranteed
Limit
Units
31
38
ns
AC Electrical Characteristics Vee = 2.0V to 6.0V, CL = 50 pF, tr= if = 6 ns (unless otherwise specified)
Symbol
Parameter
Vcc
Conditions
TA=2S'C
Typ
74HC
TA= -40 to 85'C
S4HC
TA=-SSt012S'C
Units
Guaranteed Limits
tpHL, tpLH
Maximum Propagation
Delay
2.0V
4.5V
6.0V
181
36
31
220
44
37
275
55
47
319
64
54
ns
ns
ns
lTLH, tTHL
Maximum Output Rise
and' Fall Time
2.0V
4.5V
6.0V
30
8'
7
75·
15
13
95
19
16
110
22
19
ns
ns
ns
CPO
Power Dissipation,
Capacitance (Note 5)
(per package)
180
pF
Maximum Input
5
10
10
pF
10
,Capacitance
Note 5: CPO determines the no load dynamic power consumption. Po = Cpo Vc;c2 f + lee Vee. and the no load dynamic current consumption. Is = Cpo Vee f + Icc,
CIN
'.
J
3-114
s::
s::
U\
~National
~ Semiconductor
\ ' - -_ _
""--1../
J
microCMOS
MM54HC149/MM74HC149
8 Line to 8 Line Priority Encoder
:::J:
""s::
CD
.......
s::
.....
General Description
Features
This priority encoder utilizes microCMOS Technology, 3.0
micron silicon gate N-well CMOS. It has the high noise immunity and low power consumption typical of CMOS circuits, as well as the speeds and output drive similar to
I.,S-TTL.
This priority encoder accepts 8 input request lines, RI7 -RIO,
and outputs 8 lines, R07-ROO. Only one request output
can be low at a time. The output that is low is dependent on
the highest priority request that is low. The order of priority
is RI7 highest and RIO lowest. Also provided is and enable
input, RQE, which when high forces all outputs high. A request output is also provided, RQP, which goes low when
any Rln is active.
All inputs to this device are protected from damage due to
electrostatic discharge by diodes to Vee and ground.
•
•
•
•
"":::J:
o
.....
Propagation delay: 15 ns typical
Wide power supply range: 2-6V
Low quiescent current: 80 ,...A max (74HC Series)
Wide input noise immunity
Connection Diagram
Dual-In-Line Package
TUF/5312-1
Top View
Order Number MM54HC149J or MM74HC149J,N
See NS Package J20A or N20A
Truth Table
Inputs
outputs
0
1
2
3
4
5
6
7
RQE
0
1
2
3
4
5
6
7
RQP
X
H
X
X
X
X
X
X
X
L
X
H
X
X
X
X
X
X
L
H
X
H
X
X
X
X
X
L
H
H
X
H
X
X
X
X
L
H
H
H
X
H
X
X
X
L
H
H
H
H
X
H
X
X
L
H
H
H
H
H
X
H
X
L
H
H
H
H
H
H
X
H
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
'L
L
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H .H
H H
H H
H L
L H
H H
H H
H H
H H
H H
H
H
L
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
3-115
""
o
.....
""
CD
Absolute Maximum Ratings
Operating Conditions
Supply Voltage (Vee>
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K, 10K)
DC Output Current, per pin (lOUT)
DC Vee or GND Current, per pin (Ice>
Storage Temperature Range (TSTG)
Power Dissipation (PD) (Note 3)
Lead Temperature (TL)
(Soldering 10 seconds)
Supply Voltage (Vee>
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TIV
MM74HC
MM54HC
Input Rise or Fall Times
Vee=2.0V
(tr' tf)
Vee=4.5V
Vee=6.0V
(Notes 1 & 2)
-0.5 to +7.0V
-1.5 to Vee + 1.5V
-0.5 to Vee+0.5V
±20mA
±25mA
±50mA
-65°C to + 150°C
500mW
DC Electrical Characteristics
Symbol
Parameter
260°C
Min
2
0
Max
6
Vee'
Units
V
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
(Note 4)
Conditions
Vee
TA=25"C
Typ
74HC
TA= -40 to 85·C
54HC
TA= -55to 125°C
.Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15.
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9 '
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
IIOUTI S:20 JkA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
.3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V,
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
IIOUTIS:4.0 mA
IIOUTIS:5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VeeorGND
6.0V
±0.1
±1.0
±1.0
JkA
VIN=VIH o'rVIL
IIOUTIS:4.0 mA
IIOUTIS:5.2 mA
VOL
Maximum Low Level
Output Voltage
VIN = VIH or VIL
IIOUTIS:20 JkA
.
Maximum Input
Current
liN
-
Maximum Quiescent VIN = Vee or GND 6.0V
8.0
80
160
JkA
Supply Current
IOUT=O JkA
,
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur,
Note 2: Unless otherwise specified all vollages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N;' package: -12 mWrc from 65"C to 8S'C; ceramic "J" package: -12 mW/'C from 100'C to 125"C.
Note 4: For a power supply of sv ± 10% the worst case output voltages (VOH, and VOU occur for HC at 4.SV. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at Vcc= S.SV and 4.SV respectively. (The VIH value at S.SV is 3.8SV.) The worst case leakage current (liN, ICC, and
lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
Icc
-
AC Electrical Characteristics Vee = 5V, TA= 25°C, CL = 15 pF, tr=tf= 6 ns (Note 6)
Symbol
Parameter
tpHL, tpLH
Maximum Propagation Delay, Any Input
To Any Output
Conditions
.3-116
Typ
Guaranteed Limit
Units
20
33
ns
,
AC Electrical Characteristics Vee = 2.0V to 6.0V, CL = 50 pF, tr=tf= 6 ns (unless otherwise specified)
Symbol
Parameter
TA=25'C
Vee
Conditions
Typ
74HC
TA= -40to 85'C
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
tpHL, tpLH
Maximum Propagation
Delay Any Input To Any
Output
2.0V
4.5V
6.0V
73
25
21
205
41
35
255
51
43
310
62
53
ns
ns
ns
tTLH, tTHL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
B
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
CpD
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input
Capacitance
70
pF
5
10
10
10
pF
Note 5: CpO determines the no load dynamic power consumption, PO=CPD Vcc 2 f+ Icc Vee. and the no load dynamic current consumption, Is=CPD Vee f+ Icc.
Simplified Logic Diagram
Rfi--l>
~-LJ
-
Ri6
>-L...,I.
ROI
R06
U
';;""--1
ills .....
.....
>=1........1'
R05
1=1
R04
1=1
R03
t= 1=1
R02
U
Ri4
--I>
~;::
r-
'i7
Ai3
RfZ
~t=
.....
.....
u
~
.......
.....
iffi-{::
rr
11
'i7
.... ,... =t
ROI
~
U
ROO
iffii
-
~
......
RoE ....
~7
==I
;:r->-RQP
TLlF/5312-2
-
3-117
_
..-....
r-------------------------------------------------------------------------------~
II)
o
:c ~National
:E
:E
......
I I)
..
A.---'
~ Semiconductor
MM54HC151/MM74HC151 8-Channel
Digital Multiplexer
•
j-..<-'
'\
"'
--;
microCMO$
[;
:c General Description
II)
:E
:E
This high speed Digital multiplexer utilizes microCMOS Technology, 3.5 micron silicon gate P-well CMOS.
Along with the high noise immunity and low power dissipation of standard CMOS integrated circuits, it possesses the
ability to drive 10 LS-TTL loads. The MM54HC1511
MM74HC151 selects one of the 8 data sources, depending
on the address presented on the A, B, and C inputs. It features both true (Y) and complement rN> outputs. The
STROBE input must be at a low logic level to enable this
multiplexer. A high logic level at the STROBE forces the W
output high and the Y output low.
The 54HC174HC logic family is functionally as well as pinout compatible with the standard 54LS174LS logic family.
Dual·ln·Line Package
Vee
4
15
D4
5
D5
7
13
A
12
D6
D7
11
3
data select to output Y: 26 ns
Wide operating supply voltage range: 2-6V
Low input current: < 1 /LA maximum
Low quiescent supply current: 80 /LA maximum (74HC)
High output drive current: 4 mA minimum
Inputs
A
Select
e
B
10
9
C
B
A
8
X
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
"H
H
X
L
H
L
H
L
H
L
H
B
e
D3
D2
•
•
•
•
DATA SELECT
6
14
Features
I!I Typical propagatlon delay
Truth, Table
Connection and Logic Diagrams
DATA INPUTS
All inputs are protected from damage due to static discharge by internal diod~ clamps to Vee and ground.
D1
2
DATA INPUTS
0
-Y
W STROBEGND
OUTPUTS
H
TLlF/5313-1
Outputs
Strobe
S
y
'W
H
L
L
L
L
L
L
L
L
L
DO
01
02
03
04
05
D6
D7
H
DO
" 01
02
03
04
05
06
07
= High Level, L = Low Level, X = Don't Care
DO, 01...07
=
the level of the respective 0 input
Top View
Order N4ml!er MM54HC151J or MM74HC151J, N
See NS Package J16A or N16E
DO--i==::::;;=:::;:;lr-\
D'--+----::I:::::I::I:::r'"
A -[>o+{>o-~
D.----~---+~:I::I:::r'"
D3 ---------:I:::1::1::::I::I:::r'"
STROBE
--I>O-[)o---------------.J
3-118
TL/F/5313-2
Absolute Maximum Ratings
(Notes 1 & 2)
Operating Conditions
Supply Voltage (VeC>
--;0.5 to + 7.0V
DC Input Voltage (VIN)
-1.5 to Vee + 1.5V
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
±20mA
Clarflp Diode Current (11K, 10K>
DC Output Current, per pin (loUT)
±25mA
±50mA
DC Vee or GND Current, per pin (IcC>
- 65·C to + 150·C
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
500mW
260·C
Lead Temp. (T (Soldering 10 seconds)
Min
2
0
Supply Voltage (VeC>
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
Vcc=2.0V
(t" ttl
Vcc=4.5V
Vcc=6.0V
u
-40
-55
i:
i:
Max
6
Vee
Units
V
V
+85
+125
·C
·C
1000
500
400
ns
ns
ns
..
DC Electrical Characteristics (Note 4)
Symbol
Parameter
TA=25·C
Conditions
Vee
Typ
VIH
MinimlJm~High Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
VOH
Minimum High Level
Output Voltage
i
VIN = VIH or VIL
!louTI ,;;20 /LA
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
54HC
TA= -55to 125·C
Units
Guaranteed Limits
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIH orVIL
!louTI,;; 4.0 rnA
IIOUTI';;5.2 rnA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VceorGND
6.0V
±0.1
±1.0
±1.0
/LA
VIN = VIH or VIL
!louTI ,;; 4.0 rnA
IIOUTI';;5.2 rnA
VOL
74HC
TA= -40 to 85·C
VIN=VIH orVIL
!louTI ,;; 20 /LA
80'
Maximum Quiescent VIN=VccorGND
6.0V
8.0
160
/LA
. Supply Current
IOUT=O /LA
Nole I: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Nole 2: Unl~ss otherwise specified all voltages are referenced to ground.
Nole 3: Power Dissipation temperature derating - plastiC "N" package: -12 mWre from 65·C 10 85·C; ceramic "J" package: -12 mW rc from 1OO·C to 12S·C.
Nole 4: For a power supply of SV ± 10% tihe worsl case oulpul voltages (YOH. and VoLl occur for HC aI4.SV. Thus Ihe 4.SV values should be used when designing
with Ihis supply. Worst case VIH and VIL occur at Vcc= S.5V and 4.SV respectively. (The VIH value at S.SV Is 3.8SV.) The worst case leakage current (liN. Icc. and
loz) occur for CMOS at the higher voltage and so the 6.0V values should be used.
Icc
3·119
CIt
"..
::J:
n
.....
CIt
.....
.......
i:
i:
......
"..
::J:
n
.....
.....
CIt
AC Electrical Characteristics Vcc=5V,TA=25°C,CL=15pF,tr=tf=6ns
Typ
Guaranteed
Umlt
Units
Maximum Propagation Delay
A,BorCtoY
26
35
ns
tpHL, tpLH
Maximum Propagation Delay
A,BorCtoW
27
35
ns
tpHL, tpLH
Maximum Propagation Delay
AnyDtoY
22
29
ns
tpHL, tpLH
Maximum Propagation Delay
anyDtoW'
24
32
ns
tpHL, tpLH
Maximum Propaga~ion Delay
StrobetoY
17
23
ns
tpHL, tpLH
Maximum Propagation Delay
StrobetoW
16
21
ns
Sym~ol
Parameter
tpHL, tpLH
Conditions
AC Electrical Characteristics CL =50 pF, t r =tf=6 ns (unless otherwise &pacified)
Symbol
Parameter
Conditions
TA=25"C
Vee
Typ
74HC
TA= -40t085"C
54HC
TA= -55to 125°C
Units
Guaranteed Umlts
tPHL, tpLH
Maximum Propagation Delay
A,BorCtoY
2,OV
4,5V
6,OV
90
31
26
205
41
35
256
51
44
300
60
51
ns
ns
ns
tpHL, tpLH
Maximum Propagation Delay
A,BorCtoW
2,OV
4,5V
6,OV
95
32
27
205
41
35
256
51
44
300
60
51
ns
ns
ns
tpHL, tpLH
Maximum Propagation Delay
anyDtoY
2,OV
4,5V
6,OV
70
27
23
195
39
33
244
49
41
283
57
48
ns
ns
ns
tpHL, tpLH
Maximum Propagation Delay
anyDtoW
2,OV
4,5V
6,OV
75
29
25
185
37
32
231
46
40
268
54
46
ns
ns
ns
tpHL, tpLH
Maximum Propagation Delay
Strobe to Y
2,OV
4,5V
6,OV
50
21
18
140
28
24
175
35
30
203
41
35
ns
ns
ns
tpHL, tpLH
Maximum Propagation Delay
Strobe toW
2,OV
4,5V
6,OV
45
20
17
127
25
22
159
32
28
185
37
132
ns
ns
ns
iTLH, tTHL
Maximum Output Rise
and Fall Time
2,OV
4,5V
6,OV
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
Gpo
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input
CapaCitance
.
pF
110
(per package)
5
10
10
10
pF
Note 5: CPO determines the no load dynamic power consumption, Po = CPO vcc;2 f+ ICC Vr;c. and the no load dynamic current consumption, Is = Cpo Vcc f + Icc,
'-
3·120
~National
""'"---1;
\ '---_.../
~ Semiconductor
microCMOS
MM54HC153/MM74HC153
Dual4-lnput Multiplexer
General Description
This 4-to-1 line multiplexer utilizes microCMOS Technology,
3.5 micron silicon gate P-well CMOS. It has the low power
consumption and high noise immunity of standard CMOS
integrated circuits. This device is fully buffered, allowing it to
drive 10 LS-TTL loads. Information on the data inputs of
each multiplexer is selected by the address on the A and B
inputs, and is presented on the Y outputs. Each multiplexer
possesses a strobe input which enables it when taken to a
low logic level. When a high logic level is applied to a strobe
input, the output of its associated multiplexer is taken low.
are protected from damage due to static discharge by internal diode clamps to Vee and ground.
Features
•
•
•
•
•
Typical propagation delay: 24 ns
Wide power supply range: 2V-6V
Low quiescent current: 80 /LA maximum (74HC Series)
Low input current: 1 /LA maximum
Fanout of 10 LS-TTL loads
The 54HC/74HC logic family is functionally and pinout compatible with the standard 54LS/74LS logic family. All inputs
Connection Diagram
Dual-In-Line Package
STROBE
A
SELECT
15
114
r t
T
16
13
~
~7
DATA INPUTS
\
T T T r9
I
12
11
_L
10
1
ii A
B
.....
OUTPUT
1
•
1
~
~-
A.
~-!
STR10:E
lG
r
B jj A ~
4
,12
,133
B
SELECT
\
5
,11
,l
6
0
,
DATA INPUTS
I
OU)P:T
IV
G!:
TL/F/5107-1
Top View
Order Number MM54HC153J or MM74HC153J,N
See NS Package J16A or N16E
Truth Table
Select
Inputs
Data Inputs
Strobe
Output
B
A
CO
C1
C2
C3
G
Y
X
X
X
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
L
H
H
L
L
L
L
L
L
L
L
L
L
H
L
H
L
H
L
H
X
X
X
X
X
X
L
H
X
X
X
X
Select inputs A and B are common to both sections.
H
~
high level, L
~
low level. X
~
don't care.
3-121.
Absolute Maximum Ratings
Operating Conditions
(Notes 1 & 2)
-0.5 to +7.0V
Supply Voltage (VeC>
DC Input Voltage (VIN)
-1.5 to Vee + 1.5V
DC Output Voltage (Vour)
-0.5 to Vee+0.5V
±20mA
±25mA
Clamp Diode Current (11K. 10K)
DC Output Current. per pin (lour)
DC Vee or GND Current. per pin (ICC>
Storage Temperature Range (T8TG)
Power Dissipation (Po) (Note 3)
Supply Voltage (VeC>
DC Input or Output Voltage
(VIN. Your)
Operating Temp. Range (TA)
MM74HC
MM54HC
±50mA
-65'C to + 150'C
500mW
Max
6
Units
V
0
Vee
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
Vee=2.0V
(tr• tl)
Vee=4.5V
Vee=6.0V
Lead Temperature (h)
(Soldering 10 seconds)
Min
2
260'C
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25'C
74HC
TA= -40 to 85'C
Typ
54HC
TA= -55to 125'C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
·2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN=VIHorVIL
Ilourl:5:20 IJ-A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.3
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIH orVIL
Houri :5:4.0 mA
Ilourl:5:5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
±1.0.
±1.0
/LA
160
/LA
VIN = VIH or VIL
Ilourl:5:4.0 mA
Iiourl :5: 5.2 mA
VOL
Maximum Low Level
Output Voltage
VIN = VIH or VIL
Iiourl :5: 20 IJ-A
liN
Maximum Input
Current
VIN=VeeorGND
6.0V
±0.1'
Icc
Maximum Quiescent
Supply Current
VIN = Vce or GND
lour=O /LA
6.0V
8.0
80
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Nole 3:
Power Dissipation temperature derating-plastic "N" package: -12 mWrCfrom 65'Cto 85'C; ceramic "J" package: -12 mWrCfrom 100'Cto I 25'C.
Note 4: For a power supply of 5V ± 10% the worst case output voltages (VOH, and VaLl occur lor HC at 4.5V. Thus the 4.5Vvalues should be used when designing
with this supply. Worst case VIH and VIL occur at Vcc=5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.l The worst case leakage current (liN, Icc, and
lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
3-122
AC Electrical Characteristics Vcc=5V. TA=25°C. CL =.15 pF. t r =t,=6 ns
Symbol
Parameter
Typ
Guaranteed limit
tpHL. tpLH
Maximum Propagation Delay. Select A or B to Y
Conditions
26
30
ns
tpHL. tpLH
Maximum Propagation Delay. any Data to Y
20
23
ns
tpHL. tpLH
Maximum Propagation Delay. Strobe to Y
8
15
ns
"
Units
AC Electrical Characteristics CL = 50 pF. tr= t,= 6 ns (unless otherwise specified)
Symbol
Parameter
Vcc
Conditions
74HC
54HC
TA= -40 to 85°C TA= -55 to 125°C Units
Guaranteed Limits
TA=25°C
Typ
tpHL. tpLH Maximum Propagation
Delay. Select A or B to Y
2,OV
4.5V
6.0V
131
29
25
158
35
30
198
44
38
237
52
45
ns
ns
ns
tpHL. tpLH Maximum Propagation
Delay. any Data to Y
2.0V
4.5V
6.0V
99
22
19
126
28
23
158
35
29
189
42
35
ns
ns
ns
tpHL. tpLH Maximum Propagation
Delay. Strobe to Y
2.0V
4.5V
6.0V
50
12
10
86
19
16
108
24
20
129
29
24
ns
ns
ns
tTLH. trHL Maximum Output
Rise and Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
5
10
10
10
pF
C'N
CPD
Maximum Input Capacitance
Power Dissipation
Capacitance
(Note 5)(per package)
Outputs Enabled
pF
90
Outputs Disabled
25
pF
Nole 5: CPO determines the no load dynamic power consumption. Po = Cpo Vee 2 1+ lee Vee. and the no load dynamic current consumption. Is = Cpo Vee 1+ lee.
Logic Diagram
STROBE
lC3
r:::I
lC2
DATAl
lCl
H
lCD
2C3
-
~v
~
~Yl
2C2
DATA2
2Cl
2CD
-
~Y2
*.
STROBE
SELECT {
:
TL/F/5107-2
3-123
~ National
"
~ Semiconductor
\
"j
microCMOS
MM54HC154/MM74HC154
4-to-16 Line Decoder
General Description
This decoder utilizes microCMOS Technology, 3.5 micron
silicon gate P-well CMOS, and is well suited to memory address decoding or data routing applications. It possesses
high noise immunity, and low power consumption of CMOS
with speeds similar to low power Schottky TTL circuits.
Each output can drive 10 low power Schottky TTL equivalent loads, and is functionally and pin equivalent to the
54LS154174LS154. All inputs are protected from damage'
due to static discharge by diodes to Vee and ground.
Features
The MM54HC154/MM74HC154 have 4 binary select inputs
(A, B, C, and D). If the device is enabled these inputs determine which one of the 16 normally high outputs will go low,
Two active low enables (G1 and G2) are provided to ease
cascading of decoders with little or no external logic.
Connection Diagram
•
•
•
•
Typical propagation delay: 21 ns
Power supply quiescent current: 80 p.A (14HC)
Wide power supply voltage range: 2-6V
Low input current: 1 p.A maximum
Dual·ln·Llne Package
OUTPUTS
INPUTS
VGc ' A B C
124
23
22
D
21
20
G2 Gl-' 'IS
19
18
17
14
16
13
15
12
II'
14
13'
0-
1
2
, .0
1
3
2
4
7
6
5
4
3
5
6
8
7
9
8
10 II.r2
9 10, GNO
TL/F/5122-1
OUTPUTS
Top View
Order Number MM54HC154J or MM74HC154J, N
See NS Package J24A or N24C
Truth Table
Inputs
G1
G2
D
C
B
A
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
'L
L
L
L
H
H
H
H
H
H
H
L
L
L
L
L
L
H
L
H
L
H
H
H
L
L
H
H
H
H
H
L
L
L
L
H
H
H
L
L
H
H
H
L
H
H
H
X
X
X
H
H
X
X
X
.• All others high
3-124
H
L
L
H
H
X
X
X
L
L
H
L
H
L
H
L
H
L
H
X
X
X
Low
Output"
0
1
2
3
4
5
.6
7
8
9
10
11
12
13
14
15
-
Absolute Maximum Ratings
Supply Voltage (Vee>
Operating Conditions
(Notes 1 & 2)
-0.5to +7.0V
DC Input Voltage (VIN)
-1.5toVee+ 1.5V
Supply Voltage (VeC>
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TAi
MM74HC
MM54HC
Clamp Diode Current (11K. 10K)
DC Output Current. per pin (lOUT)
±20mA
±25mA
DC Vee or GND Current. per pin (ICC>
±50mA
Storage Temperature Range (TSTG)
-65·Cto +150·C
Power Dissipation (PD) (Note 3)
Lead Temp. (TiJ (Soldering 10 seconds)
Min
2
Max
6
Units
V
0
Vee
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
(tr• til
Vee=2.0V
Vee=4.5V
Vee=6.0V
500mW
260·C
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25·C
74HC
TA=-40to85·C
Typ
54HC
TA=-55to125·C
Units
Guaranteed Limits
-
VIH
Minimum High
Level Input
Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
VIL
Maximum Low
Level Input
Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High
Level Output
Voltage
VIN = VIH or VIL
IiOUTI ,;;20 /LA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
IiOUTI ';;4.0 mA
IIOUTI';;5.2 mA
4:5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = VIH or VIL
IIOUTI ';;4.0 mA
IIOUTI';;5.2 mA
VOL
Maximum Low
Level Output
Voltage
V
V
V
VIN = VIH or VIL
IIOUTI,;; 20 /LA
liN
Maximum
Input Current
VIN = Vee or GND
6.0V
±0.1
±1.0
±1.0
/LA
Icc
Maximum
Quiescent
Supply Current
VIN = Vee or GND
IOUT=O /LA
6.0V
8.0
80
160
p.A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless olherwise specified all vollages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mWI'C from 6S'C to 8S'C; ceramic "J" package: -12 mWI'C from 100"C to 12S'C.
Note 4: For a power supply of SV ± 10% the worst case output vollages (VOH. and VoLl occur for HC at4.SV. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at Vcc= S.SV and 4.SV respectively. (The VIH value at S.SV is 3.85V.) The worst case leakage currenl (liN. Icc. and
10Z> occur for CMOS at the higher vollage and so the 6.0V values should be used.
3·125
AC Electrical Characteristics Vcc=5V, TA=25°C,CL =15pF, t r =tf=6ns
Symbol
tpHL, tpLH
Parameter
I,
Maximum Propagation Delay,'Gf, G2 or A, B, C, 0
I
I
I
Conditions'
I
Typ
I
Guaranteed Limit
I
21
I
32
I
I
Units
ns
AC Electrical Cha~acteristics Vcc~ 2.0V to 6.0V, CL =50 pF, t r =tf=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=25"C
Typ
74HC
TA= -40 to 85"C
54HC
TA=-55to125°C
Units
Guaranteed Limits
tpHL, tpLH
Maximum Propagation
Delay, G1 or G2
orA,B,C,D
2.0V
4.5V
6.0V
63
24
20
160
36
30
190
42
35
220
46
39
ns
ns
ns
t-rLH, tTHL
Maximum Output
Rise and Fall Time
2.0V
4.5V
6.0V
25
7
6
75
15
13
95
19
16
110
22
19
ns
ns
ns
CPO
Power Dissipati,on
Capacitance (Note 5)
90
CIN
Maximum Input
Capacitance
5
pF
10
10
pF
10
Note 5: CPO determines the no loed dynamic power consumption, Po= CPO vrx! f+ Icc Vee, and the no load dynamic 'current consumption, Is = Cpo Vee f+ lee.
)
\,
I
3-126
!!i:
!!i:
Logic Diagram
UI
"":::r::o
.....
.....
""
1
""-~
UI
r-
lB
Gl
19
G2
....
....
....
....
!!i:
!!i:
......
2
""
:::r::
J "
~.
....
....
o
.....
....
3
....
4
UI
""
V
I-
...
V
.V
l-
....
...
5
....
......
6
........ .........
7
.
23 ....
....
...
r - ...
I-
....
v
....
....
I-
22 ....
....
.....
....
I-
~
...
....
....
20 ....
....
.....
.....
Vee
.....
...v
-{>o-!
....
....
......
....
10
....
11
...
13
.....
14
....
'"""
_i!4_ _
......
V
_12_ _
v
9
V
10
BND
....
V
V
11
I-
,
b-t>
'""'"
........
-v
1
~1
...
~
...
.......
b.-....D
....
....
16 1
~
,
....
171
'TL/F/5122-2
3-127
~NatiOnal
.....
PRELIMINARY
.
Semiconductor
General Description
The MM54HC155/MM74HC155 is a high speed silicon-gate
CMOS decoder/demultiplexer. It utilizes mi,?roCMOS Technology, 3", silicon gate N well CMOS and features dual 1line-to-4-line demultiplexers with independent strobes and
common binary-address inputs. When both sections are enabled by the strobes, the common address inputs sequen-.
tially select and route associated input data to the appropr~ate output of each section. The individual strobes permit
activating or inhibiting each of the 4-blt sections as desired.
Data applied to input C1 is inverted at its outputs and data
applied to C2 is true through its outputs. The inverter following the C1 data input permits use as.a 3-to-8-line decoder,
or 1-to-8-line demultiplexer, without gating.
All inputs to the decoder are protected from damage due to
electrostatic discharge by diodes to Vee and Ground.
Connect and Logic Diagrams
SELECT
STROBE
C2
G2
Vec
INPUT
~I~~
~l.
OAt:
C1
STR~E
G1
'1 il
1
SELt:T ,
INPUT
B
I"
The MM54HC155/MM74HC155 is functionally and pin
equivalent to the 54LS155/74LS155 with the advantage of
reduced power consumption.
Features
• Applications
Dual 2-to-4-line dl;lcoder
Dual 1-to-4-line demultiplexer
3-to-8-line decoder
1-to-8-line demultiplexer
• Typical propagation delay: 22 nS .
• Low quiescent current: 40 ",A maximum
.
(74HC series)
• Wide operating range: 2-6V
2·to·4·Llne Decoder
or 1·Llne to 4·llne Demultiplexer
,
Inputs
2,:
b 6. A b
la' C'
l
T'0
2Y2
1·12
i'3
_11; V
~
2Y3
A
1,6 j,. 1,.
The device is capable ",i driving 10 low power Schottky TTL
equivalent loads.
Truth Tables
OUTPUTS
,
G
"
B
i
A
ii
r r
A
A
Strobe
Data
B A
X X
G1
C1
1YO
1Y1
1Y2
1Y3
H
L
L
L
L
X
X
H
H
H
H
L
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
I
L
L
H
H
X
Gl:
OUTPUTS
G'~
OATA (1)
CI
SELECT (3)
B
B A
X X
G2
·C2
2YO
2Y1
2Y2
H
L
L
L
L
X
X
L
L
L
L
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
c(>-
L
H
L
H
X
~OUTPUT
Inputs
IY2
C1 B A
~OUTPUT
X
L
L
L
L
H
H
H
H
~OUTPUT
.vo
-~OUTPUT
.VI
STROBE (14)
~OUTPUT
H
H
H·
H
L
H
Outputs
Strobe
Select
(O)
Or Data
~OUTPUT
F= ~OUTPUT
2Y3
3·Llne·to·8·Llne Decoder
or 1·Line·to·8·Line Demultiplexer
IYO
OATA (15)
C.
G.
Dats
r--~OUTPUT
IV3
SELECT (13)
A
Strobe
'Yl
,...
Outputs
Select
L
L
H
H
X
Order Number MM54HC155J or
MM74HC155J, N
See NS Package J16A or N16E
('1
L
H
L
H
X
Inputs
TL/F/8364-1
STROBE
Outputs
Select
AJ
y
.!: J:' J: ,t: ,
-:J
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microCMOS
MM54HC155/MM74HC155 Dual 2-To-4
Line DecoderIDemultiplexers
DATA
JJ...A
~
2V.
.V3
TUF/B364-2
C
G
H
3-128
X X
L L
L H
H L
HH
L L
L H
H L
H H
G1
H
L
L
L
L
L
L
L
L
(1)' (2)
(3)
(4)
(5)
(6)
(7)
2YO 2Y1 2Y2 2Y3 1YO 1Y1 1Y2 1Y3
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
= inputs Cl and C2 connected together
= inputs Gl and G2 connected together
= high level L = low level X = don't cere
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
~
Absolute Maximum Ratings
Operating Conditions
(Notes 1 and 2)
-0.5Vto +7.0V
DC Input Voltage (VIN)
-1.5Vto Vee + 1.5V
DC Output Voltage (VOUT)
-0.5 to Vee +0.5V
Clamp Diode Current (ilK, loKI
20mA
DC Output Current, per pin (lOUT)
25mA
DC Vee or GND Current, per Pin (led
50mA
Storage Temperature Range (TSTG)
- 65'C to + 150'C
500mW
Power Dissipation (Pd) (Note 3)
Lead Temp. (TI) (Soldering 10 sec)
260'C
Supply Voltage {Ved
Supply Voltage {Ved
DC Input or Output Voltage
(VIN, VOUT)
Operating Temperature Range (TA)
MM74HC
MM54HC
Input Rise/Fall Time Vee = 2.0V
(tr, tf)
Vee = 4.5V
Vee = 6.0V
Min Max Unit
2
6
V
0
Vee
-40 +85
-55+125
1000
500
400
V
C
C
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Vee
Conditions
74HC
54HC
TA = 25'C TA = -40' to 85'C TA = - 55' to 125'C
Typ
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
3.98
5.48
3.84
5.34
3.7
5.2
V
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
0.26
0.26
0.33
0.33
0.4
0.4
V
V
±0.1
±1.0
±1.0
VIN = VIH or VIL
!IOUT! = 20 p.A
!IOUT! = 20 p.A
!IOUT! = 20 p.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
!IOUT! = 4.0 mA 4.5V
!IOUT! = $.2 mA 6.0V
VOL
Maximum Low Level
Output Voltage
VIN = VIH or VIL
!IOUT! = 20 ",A
!IOUT! = 20 ",A
!IOUT! = 20 p.A
2.0V
4.5V
6.0V
!IOUT! = 4.0 mA 4.5V
!IOUT! = 5.2 rnA 6.0V
liN
Maximum Input
Current
VIN ~ Vee or GND
6.0V·
0
0
0
' ",A
Maximum Quiescent VIN = Vee or GND
6.0V
8
80
160
",A
Supply Current
lOUT = o ",A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified, all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mWI'C from 6SoC to 8SoC.
ceramic "J" package: -12 mW/oC from 100°C to 12So.
Note 4: For a power supply of SV ± 10% the worst CBSe output voltages (YOH and VoLl occur at4.SV. Thus the 4.SV values should be used when designing with
Ihis supply. Worst casa VIH and VI. occur al Vee ~ S.SV and 4.SV respectively. (The VIH value aIS.5V is 3.85V.) The worst case leakage current (liN, lee and lozl
occur al the higher voltage and so Ihe 6.0V values should be used.
Icc
'.
3-129
AC Electrical Characteristics (Note 6) Vcc =
5V, TA = 25'C,CL = 15'PF, t,. = tf = 6ns
,
\
Guaranteed
Limit
Parameters
tpLH, tpHL
Maximum Propagation Delay
' from Inputs A, B, or C2 to
any Output
ns
tpLH, tpHL
Maximum Propagation Delay
from Inputs G1 or G2 to
any Output
ns
tpLH, tpHL
Maximum Propagation Delay
from Input C1 to any
Output
ns
Conditions
AC Electrical Charact~ristics (Note 6) CL =
50 pF, tr = tf = 6 ns (unless otherwise specified)
Typ
Symbol
Parameter
tpLH, tpHL
Maximum Propagation Delay
from Inputs A, B, or C2 to
any Output
tpLH, tpHL
tpLH, tpHL
Maximum Propagation Delay
from Inputs G1 or G2 to
any Output
Maximum Propagation Delay
from Input C1 to any
Output
Vee
Typ
Units
Symbol
Guaranteed Limits
'T = 25'C
T = 25'C
74HC
T = -!'to' to 85'C
54HC
T =-55' to 125'C
Units
10
pF
2.0V
4.5V
,
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
lTLH, lTHL
Rise and Fall Time
4.5V
6.0V'
CPO
Power Dissipation
Capacitance
2.0V
4.5V
6.0V
CIN
Minimum Input Capacitance
5
Note 5: CPC determines the no load dynamic power consumption, Pd
CPO'Vcc! + Icc.
10
10
= (CPO'Vcc"2)" + ICC + Vcc, and the no load dynamic current composition, Is =
Note 6: Typical MM5474HC AC Switching Waveforms and Test CircuHs.
"'
3·130
~National
)
\
~ Semiconductor
microCMOS
MM54HC157/MM74HC157 Quad 2-lnput Multiplexer
MM54HC158/MM74HC158 Quad 2-lnput Multiplexer
(Inverted Output)
General Description
These high speed Quad 2-to-1 Line data selector/Multiplexers utilize microCMOS Technology, 3.5 micron silicon gate
P-well CMOS. They possess the high noise immunity and
low power consumption of standard CMOS integrated circuits, as well as the ability to drive 10 LS-TTL loads.
The 54HC174HC logic family is functionally as well as pinout compatible with the standard 54LSI74LS logic family.
All inputs are protected from damage due to static discharge by internal diode clamps to Vee and ground.
Features
, These devices each consist of four 2-input digital multiplexers with common select and STROBE inputs. On the
MM54HC157/MM74HC157, when the STROBE input is at
logical "0" the four outputs assume the values as selected
from the inputs. When the STROBE input is at a logical "1"
the outputs assume logical "0". The MM54HC158/
MM74HC158 operates in the same manner, except that its
outputs are inverted. Select decoding is done internally resulting in a single select input only. If enabled, the select
input determines whether the A or B inputs get routed to
their corresponding Y outputs.
• Typical propagation delay: 14 ns data to any output
• Wide power supply range: 2-6V
• Low power supply quiescent current: 80 /-LA maximum
(74HC Series)
• Fan-out of 10 LS-TTL loads
• Low input current: 1 /-LA maximum
Connection Diagrams
--- -INPUTS
VCC STROBE 4A
T16
15
4B
14
4Y
3A
12
13
4A
G
OUTPUT INPUTS
4Y
4B
3B
11
3A
"jIB
9
lB
3
2
2A
lY
4
2B
5
G
--- --lY
18
INPUTS
2A
2B
OUTPUT INPUTS
GND
SELECT
OUTPUT
4Y
3A
3B
lB
lY
2A
28
2Y
--18
lA
TL/F/5314-1
Order Number MM54HC157J, MM54HC158J,
MM74HC157J,N or MM74HC158J,N
See NS Package J16A or N16E
Function Table
Inputs
Output V
Strobe
Select
A
B
HC157
HC158
H
L
L
L
L
X
X
L
.L
H
H
L
H
X
X
X
X
X
L
H
L
L
H
L
H
H
H
L
H
L
= High Level, L = Low Level, X = Irrelevant
3-131
4
3
lY
5
B
--2A
2B
OUTPUT INPUTS
Top View
3Y
9
10
4B
INPUTS
Top View
H
11
12
4A
2
18
2Y
13
OUTPUT
3B
3A
3Y
IA
7
14
4Y
r--S
2Y
B
15
OUTPUT INPUTS
4B
VCC STROBE 4A
3Y -
lA
lA
10
--- -INPUTS
3Y
38
r--S
SELECT
Dual-In-Line Packages
OUTPUT
P-
7
2Y
IB
GND
OUTPUT
TL/F/5314-2
Absolute Maximum Ratings (Notes 1 & 2)
. Supply Voltage (Vee)
-0.5 to +7.0V
DC Input Voltage (VIN)
-1.5toVee+ 1.5V
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
±20mA
Clamp Diode Currerit (ilK, 10K>
±25mA
DC Output Current, per pin (lOUT)
±50mA
DC Vee or GND Current, per pin (lee)
- 65·C to + 150·C
Storage Temperature Range (TSTG)
500mW
Power Dissipation (Po) (Note 3)
260·C
Lead Temp. (TiJ (Soldering 10 seconds)
Operating Conditions
Supply Voltage (Vee>
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
Vee=2.0V
(t" tf}
Vee=4.5V
Vee=6.0V
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25·C
Typ
74HC
TA= -40 to 85·C
54HC
TA = -55 to 125"C
Units
Guaranteed limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
IIOUTI:S:20 p.A
.2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
'1.9
4.4
5.9
V
V
V
.4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIH orVIL
IiOUTI:S:4.0 mA
IIOUTI:S:5.2 mA
4.5V
6.0V
0.2
0.2
·0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = Vee or GND
6.0V
±0.1
±1.0
±1.0
/LA
VIN = VIH or VIL
IIOUTI:S:4.0 mA
IIOUTI:S:5.2mA
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
VIN = VIH or VIL
IIOUTI :s: 20 /LA
Maximum Quiescent VIN = Vee or GND 6.0V
80
160
8.0
/LA
Supply Current
IOUT=O /LA
Nota 1: Absolute Maximum Ratings are those values beyond which damage to the devloe may occur.
Note 2: Unless otherwise specified all voltages are refe,enced to ground.
Nota 3: Power Dissipation temperature derating - plastic "N" package: -12 mWI'C from 65'C to 85'C; ceramic "J" peckage: -12 mW/'C from 1OO'C to 125'C.
Nota 4: For a power supply of 5V ±10% the worst case output voltages (VOH. and VoLl occur for HC at4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur·at Vcc=5.5V and 4.5V respectively. (The VIH value at 5.5V Is 3.85V.) The worst case leakage current (liN,
ICC, and loz) occur for CMOS at the higher voltage and so the 6.0V values should be used.
•
lee
.
3-132
s::
s::
U1
AC Electrical Characteristics Vcc= 5V. TA = 25°C. CL = 15 pF. t,=t,= 6 ns
"'"
::J:
Typ
Guaranteed
Limit
Units
(')
Maximum Propagation
Delay. Data to Output
14
20
ns
......
.....
tpHL. tpLH
Maximum Propagation
Delay. Select to Output
14
20
ns
s::
s::
......
tpHL. tpLH
Maximum Propagation
Delay. Strobe to Output
12
18
ns
o
.....
Symbol
Parameter
tpHL. tpLH
Conditions
.....
U1
"'"
::J:
U1
......
.....
s::
s::
U1
"'"
::J:
AC Electrical Characteristics CL =50 pF. l,=t,=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=25°C
Typ
74HC
TA= -40t085"C
54HC
TA= -55 to 125"C
o
.....
U1
Units
Guaranteed Limits
Maximum Propagation
Delay. Data to Output
2.0V
4.5V
6.0V
63
13
11
125
25
21
158
32
27
186
37
32
ns
ns
ns
tpHL. tpLH
Maximum Propagation
Delay. Select to Output
2.0V
4.5V
6.0V
63
13
11
125
25
21
158
32
27
186
37
32
ns
ns
ns
tpHL. tpLH
Maximum Propagation
Delay. Strobe to Output
2.0V
4.5V
6.0V
58
12
10
115
23
20
145
29
25
171
34
29
ns
ns
ns
t-rLH. tTHL
Maximum Output Rise
and Fall'Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
CIN
Maximum Input
Capacitance
5
10
10
10
pF
CPO
Power Dissipation
Capacitance (Note 5)
tPHL. tpLH
-
(per
Multiplexer}
pF
Note 5: CpO determines !he no load dynamic power ccnsumption. Po- CPO Vec2 f+ lee Vee. and !he no load dynamic current consumption, Is = Cpo Vee f+ Icc.
,
\
'-
3-133
CD
......
s::
s::
......
"'"
::J:
(')
.....
U1
CD
CD
ID
....
(,)
::c
':'If'
.....
::::IE
::::IE
....
CD
ID
....
Logic Diagrams
'HC157
Al
81
0
::c
~
A2
(2)
(3)
(5)
ID
::::IE
::::iii
....
.....
B2
(,)
A3
....
(6)
ID
::c
.....
(11)
~
::::IE
::::IE
83
ID
....
(,)
A4
j:::
::c
~
(10)
(14)
(13)
ID
84
::::IE
::::IE
(15)
STR08E (1)
SELECT
TL/F/5314-3
'HC158
Al
~(2L.)- - - - - - - r " ' \
B1J.:(3~)-----+--r"'"
A2,!(5~)--__________+-+-r-~
B2~(6~)-"":"'---++-r"",
A3£·(I~I)------------t-Hr'"
83~(1~0)------------1HHr
M~(1~4)------------1HHr'"
1
+-t--r
84 (1!!3L-)_ _ _ _ _
(15)
STROBE '(I!!.)..._-+-OIL...~
SELECT"'"
TUF/5314-4
3·134
~---------------------------------------------------------------.~
lI?'A National
~ Semiconductor
~
UI
PRELIMINARY
\
J
microCMOS
MM54HC160/MM74HC160 Synchronous
Decade Counter with Asynchronous Clear
MM54HC161/MM74HC161 Synchronous
Binary Counter with Asynchronous Clear
MM54HC162/MM74HC162 Synchronous
Decade Counter with Synchronous Clear
MM54HC163/MM74HC163 Synchronous
Binary Counter with Synchronous Clear
....
""......
:z:
""
o
....
m
....
.....
~
~
UI
~
......
Features
OB
Oc
1,6 1,5 j'4 j'3 j12
I
r<:
I
I
RIPPLEOA
CARRY
OUTPUT
CLEAR
OB
~
I
Truth Tables
OUTPUTS
I
0D
1"
I
1,0
LOAD
ENABLE
D
P
ENP
ENT
load
Function
X
X
X
X
L
H
H
H
H
H
X
X
X
H
L
L
L
H
L
H
H
X
X
H
H
L
H
Clear
Count & RC disabled
Count disabled
Count & RC disabled
Load
Increment Counter
9
I '1
I
I
t
t
pH
X
H
= high level, L = low level
= don" care, t = low to high transition
I
'HC162/HC163
'12 13 !4 !5 /6 1718
D EI'lABLEGND
P
DATA INPUTS
TL/F/S008-'
Order Number MM54HC160J, MM54HC161J,
MM54HC162J, MM54HC163J, MM74HC160J, N,
MM74HC161J, N, MM74HC162J, N or MM74HC163J, N
See NS Package J16A or N16E
B
CLR
I
C
CLEAR CLOCK A
CLK
Oc OD ENABLE
T
B
A
'HC160/HC161
ENABLE
T LOAD
C
3-135
ClK
ClR
ENP
ENT
load
Function
t
L
H
H
X
H
X
X
H
Clear
Count & RC disabled
Count disabled
Count & RC disabled
Load
Increment Counter
X
X
X
t
t
H
L
L
L
H
L
o
....
m
~
~
UI
The MM54HC160/MM74HC160, MM54HC1611
The MM54HC160/MM74HC160 and MM54HC1611
MM74HC161, MM54HC162/MM74HC162, and
MM74HC161 counters are cleared asynchronously. When
MM54HC163/MM74HC163 synchronous presettable countthe CLEAR is taken low the counter is cleared immediately
ers utilize microCMOS Technology, 3.5 micron silicon gate
regardless of the CLOCK.
P-well CMOS, and internal look-ahead carry logic for use in , Two active high enable inputs (ENP and ENn and a RIPhigh speed counting applications. They offer the high noise
PLE CARRY (RC) output are provided to enable easy. casimmunity and low power consumption inherent to CMOS
cading of counters. Both ENABLE inputs must be high to
with speeds similar to low power Schottky TTL. The 'HC160
count. The ENT input also enables the RCoutput. When
and the 'HC162 are 4 bit decade counters, and the 'HC161
enabled, the RC outputs a positive pulse when the counter
and the 'HC163 are 4 bit binary counters. All flip-flops are ' overflows. This pulse is approximately equal in duration to
clocked simultaneously on the low to high to transition (posthe high level portion of the OA output. The RC output is fed
itive edge) of the CLOCK input waveform.
to successive cascaded stages to facilitate easy implemenThese counters may b~preset using the LOAD input. Pre'
tation of N-bit counters.
selling of all four flip-flops is synchronous to the rising edge
All inputs are protected from damage due to static disof CLOCK. When LOAD is held low counting is disabled and
charge by diodes to Vee and ground.
the data on the A, B, C, and D inputs is loaded into the
counter on the rising edge of CLOCK. If the load input is
taken high before the positive edge of CLOCK the count
• Typical openiting frequency: 40 MHz
operation will be unaffected.
• Typical propagation delay; clock to 0: 18 ris
All of these counters may be cleared by utilizing the CLEAR
• Low quiescent current: 80 p.A maximum (74HC Series)
input. The clear function on the MM54HC162/MM74HC162
• Low input current: 1 p.A maximum
and MM54HC163/MM74HC163 counters are synchronous
• Wide power supply range: 2-6V
to the clock. That is, the counters are cleared on the posi-'
live edge of CLOCK while the clear input is held low.
RIPPLE
CARRV
Vee OUTPUT OA
:z:
""
~
General Description
Connection Diagram
.....
""......
H
H
H
X
X
L
H
H
H
H
:z:
""
o
....
m
N
.....
~
~
UI
.....
""......
:z:
""
o
....
m
w,
Absolute Maximum Ratings (Notes 1 & 2)
-0.5 to + 7.0V
Supply Voltage (Vee>
DC Input Voltage (VIN)
-1.5 to Vee + 1.5V
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
±20mA
Clamp Diode Current (11K. 10Kl
±25mA
DC Output Current. per pin (lOUT)
±50mA
DC Vee or GND Current. per pin (lee)
-65'C to + 150'C
Storage Temperature Range (TSTG)
Power Dissipation (PD) (Note 3)
500mW
Lead Temp. (TtJ (Soldering 10 seconds)
260"C
Operating Conditions
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Min
2
Max
6
Units
V
0
Vee
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
(t,. tf)
Vee=2.0V
Vee=4.5V
Vee=6.0V
DC Electrical Characteristics (Note 4)
,
Symbol
Parameter
Conditions
TA=25'C
Vee
74HC
TA= -40to8S'C
Typ
S4HC
TA= -55 to 12S'C
Units
Guaranteed Umlts
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
. 4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2.
V
V
V
VOH
Minimum High Level
Output Voltage
VIN=VIH orVIL
IIOUTIS:20 p.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V.
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
9
0
0
0.1
0.1
·0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
IIOUTIS:4.0 mA
IIOUTI s: 5.2 mA.
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = Vee or GND
6.0V
±0.1
±1.0
±1.0
p.A
VIN=VIHorVIL
IIOUTI S:4.0 mA
IIOUTI S:5.2 mA
Maximum Low Level
Output Voltage
VOL
Maximum Input
Current
liN
VIN=VIH orVIL
IIOUTI s: 20 p.A
Maximum Quiescent VIN = Vee or GND 6.0V
8.0
80
160
p.A
Supply Current
10UT=0 p.A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specffied all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mWI'C from 65'C to 85'C; ceramic "J" package: -12 mWI'C from 1OO'C to 125'C.
Note 4: For a power supply of SV ± 10% the worst case output voltages (YaH. and Vall occur for HC at 4.SV. Thus the 4.SV values should be used when designing.
wnh this supply. Worst case VIH and VIL occur at Vcc=5.SV and 4.SV respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (liN. Icc. and
IOZ) occur for CMOS at the higher voltage and so the B.OV values should be used.
lee
,
\
3-136
AC Electrical Characteristics Vcc=5V, TA=25'C, CL = 15 pF, t,=tf=6 ns
Typ
Guaranteed Limit
Units
fMAX
Maximum Operating Frequency
43
30
MHz
tpHL, tpLH
Maximum Propagation Delay, Clock to RC
30
35
ns
tpHL, tpLH
Maximum Propagation Delay, Clock to Q
29
34
ns
tpHL, tpLH
Maximum Propagation Delay, ENT to RC
18
32
ns
Maximum Propagation Delay, Clear to Q or RC
27
38
ns
Minimum Removal Time, Clear to Clock
10
20
ns
30
ns
Symbol
tpHL
, tREM
Parameter
Conditions
Is
Minimum Set Up Time Clear, Load,
Enable or Data to Clock
tH
Minimum Hold Time, Data from Clock
5
ns
tw
Minimum Pulse Width Clock,
Clear, or Load
16
ns
AC Electrical Characteristics CL =50 pF, t,=tf=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=25'C
Typ
74HC
TA= -40 to 85'C
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
fMAX
Maximum Operating
Frequency
2.0V
4.5V
6.0V
10
40
45
5
27
32
4
21
25
4
18
21
Mf-!z
MHz
MHz
tpHL
Maximum Propagation
Delay, Clock to RC
2.0V
4.5V
6.0V
100
32
28
215
43
37
271
54
46
320
64
54
ns
ns
ns
tpLH
Maximum Propagation
Delay, Clock to RC
2.0V
4.5V
6.0V
88
18
15
175
35
30
220
44
37
260,
52
44
ns
ns
ns
tpHL
Maximum Propagation
Delay, Clock to Q
2.0V
4.5V
6.0V
95
30
26
205
41
35
258
52
44
305
61
52
ns
ns
ns
tpLH
Maximum Propagation
Delay, Clock to Q
2.0V
4.5V
6.0V
85
17
14
170
34
29
214
43
36
253
51
43
ns
ns
ns
tpHL
Maximum Propagation
Delay, ENT to RC
2.0V
4.5V
6.0V
90
28
24
195
39
33
246
49
42
291
58
49
ns
ns
ns
tpLH
Maximum Propagation
Delay, ENT to RC
2.0V
4.5V
6.0V
80
16
14
160
32
27
202
40
34
236
46
41
ns
ns
ns
tpHL
Maximum Propagation
Delay, Clear to Q or RC
2.0V
4.5V
6.0V
100
32
28
220
44
37
277
55
47
328
66
55
ns
ns
ns
tREM
Minimum Removal Time
Clear to Clock
2.0V
4.5V
6.0V
125
25
21
158
32
27
186
37
32
ns
ns
ns
Is
Minimum Set Up Time
Clear, Load,
or Data to Clock
2.0V
4.5V
6.0V
150
,30
26
190
38
32
225
45
38
ns
ns
ns
Is
Minimum Set Up
Time Enable
To Clock
2.0V
4.5V
6.0V
175
35
30
220
44
37
260
52
44
ns
ns
ns
tH
Minimum Hold Time
Data from Clock
2.0V
4.5V
6.0V,
50
10
9
63
13
11
75
15
13
ns
ns
ns
tH
Minimum Hold Time
Enable, Load or Clear
to Clock
2.0V
4.5V
6.0V
0
0
0
0
0
0
0
0
0
ns
ns
ns
tw
Minimum Pulse Width
Clock, Clear, or
Load
2.0V
4.5V
6.0V
80
16
14
100
20
17
120
24
20
ns
ns
ns
3·137
I
...o r-----------------------------------------------------------------------------,
AC Electrical Characteristics
~
CD
(Continued) CL = 50 pF, t,= tf= 6 ns (unless otherwise specified)
..
%
~
......
Symbol
Parameter
Conditions
Vee
Typ
.."
:::E
:::E
~
tTLH, tTHL Maximum
Output Rise and
Fall Time
2.0V
4.5V
6.0V
t,., tf
Maximum Input Rise and
Fall Time
2.0V
4.5V
6.0V
CPO
Power Dissipation
Capacitance (Note 5)
:::E
:::E
......
CIN
Maximum Input Capacitance
..
Logic Diagrams
...
'CD
o
..
%
~
.....
.."
......
CD
o
%
74HC
54HC
TA= -40to 85·C TA= -55to 125·C Units
Guaranteed Limits
TA=25·C
(per package)
40
8
7
75
15
13
95
19
16
110
19
ns
ns
ns
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
22
90
5
pF
10
10
10
pF
Note 5: CPO determines the no load dynamic powe, consumption, Po=Cpo Vcc2 f+lee Vee. and the no load dynamic current consumption,
Is=Cpo Vee f+1ee·
.....
MM54HC160/MM74HC160 or MM54HC162/MM74HC162
~
.."
:::E
:::E
......
o
'A
14
...
CD
..
o
%
.....
~
.."
:::E
:::E
T
5
LOAD~L
(31
TLlF/SOOB-2
.
MM54HC1611MM74HC161 or MM54HC163/MM74HC163
aa
oc
ac
14
QA
CK
CUI
D
T
LOAD~L
ENP
"NT
CU!AR
~(TI~~~-'------'
.--.---------
~
.......,
.....
~(~11-C~_
tI.
(15)
o
TL/F/500B-3
3·138
Logic Waveforms
160, 162 Synchronous Decade Counters Typical Clear, Preset, Count and Inhibit Sequences
CLEAR
160
CLEAR
162
LOAD
r--+--. - - - - - - - - - - - - - r--+--. - - - - - - - - - - - - - DATA{:
INPUTS C r--+--. - - - - - - - - - - - - - r-------------D _ _-+_.....l.
CLOCK---h
160
CLOCK
162
ENABLEP _ _ _r-~r-t--------1----~r---ENABLE T _ _ _r-~
OUTPUTS{::~ ~
OC==
-t-t--4
OD= =
RIPPLEO~~---+--t';'"""+.-:!
---.t.--INHIBITCLEAR PRESET
Sequence:
(1)
(2)
(3)
(4)
TL/F/500B-4
Clear outputs to zero
Preset to BCD seven
Count to eight, nine, zero, one, two, and three
Inhibit
161,163 Synchronous Binary Counters Typical Clear, Preset, Count and Inhibit Sequences
CLEAR
161
CLEAR
163
LOAD---h
r--------------
r - - - --------------
A
B-+----" ___ -
DATA
{ C
INPUTS
D
_____________ _
1""""-+-..,.-------------~
.---I--T- - - - - - - - - - - - - -
CLOCK - - - h
161
CLOCK
183
ENABLE
p-----ir--~rt-------1----..J
ENABLE T
-----ir---I-I
OA==
~~t=j::~--~1.-_ _+-_-'-____
{
OUTPUTS
OB = =
OC_ _
OD==
RIPPLE CARRY
OUTPUT
Sequence:
(1)
(2)
(3)
(4)
---+-1=+'..::-7--+lI---INHIBlTCLEAR PRESET
TL/F/500B-5
Clear outputs to zero
Preset to binary twelve
Count to thirteen, fourteen, fifteen, zero, one and two
InhibH
3-139
i&
.....
(,)
::c
"0:1'
~National
.... ~ Semiconductor
:E
:E
microCMOS
~
MM54HC164/MM74HC164·
.....
~
.8-Bit Serial-in/Paraliel-out Shift Register
"0:1'
II)
:E
:E
General Description
The MM54HC164/MM74HC164 utilizes microCMOS Technology, 3.5 micron silicon gate P-well CMOS. It has the high
noise immunity and low consumption of standard CMOS Integrated circuits. It also ofters speeds comparable to low
power Schottky devices.
This 8-Bit shift register has gated serial inputs and CLEAR.
Each register bit is a D-type master/slave flip flop. Inputs A
& B permit complete control over the incoming data. A low
at either or both inputs inhibits entry of new data and resets
the first flip flop to the low level at the next clock pulse. A
high level on one input enables the other input which will
then determine the state of the first flip flop. Data at the
serial inputs may be changed while the clock is high or low,
but only information meeting the setup and hold time requirements will be entered. Data is serially shifted in and out
of the 8-Bit register during the positive going transition of
the clock pulse. Clear is independent of the clock and accomplished by a low level at the CLEAR input.
Connection and Logic Diagrams
The 54HC174HC logic family is functionally as well 'as pinout compatible with the standard 54LS174LS logiC family.
All inputs are protected from damage due to static discharge by internal diode clamps to Vee and ground.
Features
•
•
•
•
•
Typical operating frequency: 50 MHz
Typical propagation delay: 19 ns (clock to a)
Wide operating supply voltage range: 2-6V
Low input current: < 1 /LA .
Low quiescent supply current: 80 /LA maximum (74HC
Series)
• Fanout of 10 LS-TTL loads
Truth Table
Dual-In-Line Package
Inputs
OUTPUTS
Vec
QH
114
13
QG
12
OF
OE
11
10
CLEAR CLOCK
9
8
<
r-
H
X
i
1
2
~
SERIAL INPUTS
PA
5
6
17
Oc
OD,
GNO
4
3
Os
OUTPUTS
Outputs
...
Clear
Clock
A
B
QA
Qs
L
H
H
H
H
X
X
X
X
X
L
L
l
aAO
H
L
X
aBO
aAn
aAn
aAn
aHO
aGn
aGn
aGn
l
i
i
i
H
H
L
L
QH
X L
= High Level (steady state). L = Low Level (steady state)
= Irrelevant (any input. including transitions)
= Transition from low to high level.
aAO. aeo. aHO =
the level of aA. ae. or aH. respectively. before the
indicated steady state input conditions were established.
aAn. aGn =
TL/F/5315-1
The level of aA or aG before the most recent
the clock; indicated a one-bit shift
i
transHlon of
Top View
Order Number MM54HC164J or MM74HC164J,N
See NS Package J14A or N14A
CLOCK
SERIAL
INPUTS
I
A<>::==:[)
BO
CLEAR
OB
Qc
Qo
QG
QH
TL/F/5315-2
3-140
Absolute Maximum Ratings
Operating Conditions
(Notes 1 & 2)
-0.5 to + 7.0V
Supply Voltage (Veel
DC Input Voltage (VIN)
-1.5 to Vee + 1.5V
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
±20mA
±25mA
±50mA
-65'C to + 150'C
Clamp Diode Current (11K. 10K)
DC Output Current. per pin (lOUT)
DC Vee or GND Current. per pin (Ieel
Storage Temperature Range (T8TG)
Power Dissipation (Po) (Note 3)
Supply Voltage (Veel
DC Input or Output Voltage
(VIN. VOUT)
. Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
(tr• til
Vee=2.0V
Vcc=4.5V
Vee=6.0V
500mW
Lead Temp. (TO
(Soldering 10 seconds)
260'C
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25'C
Typ
74HC
TA= -40 to 85'C
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3 '
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN=VIHorVIL
IIOUTI~20 /LA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
IIOUTI~4.0 mA
IIOUTI~5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = Vee or GND
6.0V
±0.1
±1.0
±1.0
/LA
I
VIN=VIHorVIL
IIOUTI~4.0 mA
IIOUTI~5.2 mA
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
VIN=VIHorVIL
IIOUTI ~ 20 /LA
Maximum Quiescent VIN=VeeorGND 6.0V
160
8.0
80
/LA
Supply Current
IOUT=O /LA
Nole 1: Absolute Maximum Ratings are Ihose values beyond which damage to the device may occur.
Nole 2: Unless olherwise specified all vollages are referenced to ground.
Note 3: Power Dissipation lempereture derating - plastic uN u package: -12 mWI"C from 65'C 10 85'C; ceramic uJu package: -12 mWI"C from 100'C to 125'C.
Note 4: For a power supply of 5V ± 10% the worsl case output volleges (VOH. and Vou occur for HC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worsl case VIH and VIL occur at Vcc= 5.5V and 4.5V respectively. (The VIH value al5.5V is 3.85V.) The worst case leakage current (liN. Icc. and
lov occur for CMOS al the higher vollege and so the 6.0V values should be used.
lee
3-141
AC Electrical Characteristics Vee = 5V, TA = 25°C, CL = 15 pF, t~=tf= 6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Umlt
Units
30
MHz
fMAX
Maximum Operating
Frequency
tpHL, tpLH
Maximum Propagation
Delay, Clock to Output
19
30
ns
tpHL, tpLH
Maximum Propagation
Delay, Clear to Output
23
35
ns
tREM
Minimum Removal Time,
Clear to Clock
-2
0
ns
ts
Minimu'm Setup Time
Data to Clock
12
20
ns
tH
Minimum Hold Time
Clock to Data
1
5
ns
tw
Minimum Pulse Width
Clear or Clock
10
16
ns
,
AC Electrical Characteristics CL = 50 pF, tr= tf= 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=2SoC
2.0V
4.5V
6.0V
tPHL, tPLH
Maximum Propagation
Delay, Clock to Output
2.0V
4.5V
6.0V
tpHL, tpLH
Maximum Propagation
Delay, Clear to Output
tREM
S4HC
TA=-5Sto125"C
Units
Guaranteed LI~lts
Typ
Mliximum Operating
Frequency
74HC
TA= -40 to 8SoC
5
27
31
115
13
20
175
35
30
2.0V
4.5V
6.0V
140
28
24
Minimum Removal TIme
Clear to Clock
2.0V
4.5V
6.0V
ts
Minimum Setup Time
Data to Clock
tH
.4
24
3
18
20
MHz
MHz
MHz
218
44
38
254
51
44
ns
ns
ns
205
41
35
256
51
44
. 297
59
51
ns
ns
ns
-7
-3
-2
0
0
0
0
0
0
0
0
0
ns
ns
ns
2.0V
4.5V
6.0V
25
14
12
100
20
17
125
25
21
150
30
25
ns
ns
ns
Minimum Hold Time
Clock to Data
2.0V
4.5V
6.0V
-2
0
1
5
5
5
5
5
5
5
5
5
ns
ns
ns
tw
Minimum Pulse Width
Clear or Clock
2.0V
4:5V
6.0V
22
11
10
80
16
14
100
20
18
120
24
20
ns
ns
ns
trHL, trLH
Maximum Output
Rise and Fall Time
2.0V
4.5V
6.0V
75
15
13
95
19
16
110
22
19
ns
ns
ns
t"tf
Maximum Input Rise and
Fall TIme
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
CPO
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input
Capacitance
fMAX
(per package)
5.0V
~1
150
5
pF
10
10
10
pF
Note 5: Cpo determines the no load dynamic power consumption. Po = cpo\vcc21+ ICC Vee. and the no load dynamic current consumption. IS = CpO Vee 1+ ICC'
.
I
3-142
~National
PRELIMINARY
\ J
~ Semiconductor
microCMOS
MM54HC165/MM74HC165
Paraliel-in/Serial-out a-Bit Shift Register
General Description·
The MM54HC165/MM74HC165 high speed PARALLEL-INI
SERIAL-OUT SHIFT REGISTER utilizes microCMOS Technology, 3.5 micron silicon gate P-well CMOS. It has the low
power consumption and high noise immunity of standard
CMOS integrated circuits, along with the ability to drive 10
LS-TTL loads.
This 8-bit serial shift register shifts data from QA to QH when
clocked. Parallel inputs to each stage are enabled by a low
level at the SHIFT/LOAD input. Also included Is a gated
CLOCK input and a complementary output from the eighth
bit.
Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a CLOCK INHIBIT function.
Holding either of the CLOCK inputs high inhibits clocking,
and holding either CLOCK input low with the SHIFT/LOAD
input high enables the other CLOCK input. Data transfer
occurs on the positive going eqge of the clock. Parall~lload-
Connection Diagram
C
B
Typical propagation delay: 20 ns (clock to Q)
Wide operating supply voltage range: 2-6V
Low input current: < 1 IJoA
Low quiescent supply current: 80 IJoA maximum
(74HC Series)
• Fanout of 10 LS-TTL loads
Inputs
Internal
Output
Shlftl Clock
Parallel Outputs
QH
Clock Serial
Load Inhibit
A ••• H QA QB
PARALLEL INPUTS
D
Features
•
•
•
•
Function Table
Dual-In-Line Package
CLOCK
VCC INHIBIT
ing is inhibited as long as the SHIFT/LOAD input is high:
When taken low, data at the parallel inputs is loaded directly
into the register independent of the state of the clock.
The 54HC174HC logiC family is functionally as well as pinout compatible with the standard 54LS174LS logic family.
All inputs are protected frqm damage due to static discharge by internal diode clamps tQ Vee and ground.
A
116 115 114 11~ 112 111
SERIAL OUTPUT
INPUT
QH
J10
L
H
H
H
H
9
! I I I I I
CLOCK
INHIBIT
SHIFT I
LOAD
C
B
A
SERIAL
IN
E
2
SHIFT / CLOCK
LOAD
X
L
L
L
H
L
X
X
t
i
H
L
X
X
a ... h
X
X
X
X
a
b
h
QAO QBO
H QAN
L QAN
QAO Qeo
QHO
QGN
QGN
QHO
QH
H
CK
1
D
X
F
G
H
OH
L I I I I
13 14 15 Is 17 IB
E
F
G
~
High Level (steady stale). L
~
Low Level (steady slate)
X ~ Irrelevanl (any input. including transitions)
i
~ Transition from low to high level
OAO. Oao. OHO ~ The level of OA. Oa. or OH. respectively. before the
Indicated steady-slate input conditions were eslablished.
.
OAN. OON ~ The level of OA or 00 before the most recent
the clock; indicates a one-bit shift.
H OUTPUT GND
OH
PARALLEL INPUTS
TL/F15316-1
Top View
Order Number MM54HC165J or MM74HC165J,N
See NS Package J16A or N16E
3-143
i
transition of
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
Supply Voltage (Vee)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K. 10K>
DC Output Current. p~r pin (lOUT)
DC Vee or GND Current. per pil1 (Icc)
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
Lead Temperature (TLl
(Soldering 10 seconds)
Supply Voltage {Vee>
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TAl
MM74HC
MM54HC
Input Rise or Fall Times
(tr• tl)
Vee=2.0V
Vee,..4.5V
Vee=6.0V
-0.5 to +7.0V
-1.5 to Vee + 1.5V
-0.5 to Vee+0.5V
±20mA
±25mA
±50mA
- B5'C to + 150'C
500mW
260'C
Min
2
0
Max
6
Vee
Unl'ts
V
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
,
Parameter
Conditions
Vee
TA=25'C
Typ
74HC
TA=-40to85'C
54HC
TA= -55 to 125"C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
B.OV
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
..
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
IIOUTI:<;;20 p.A
VIN = VIH or VIL
IIOUTI :<;;4.0 mA
IIOUTI :<;; 5.2 mA
VOL
Maximum Low Level
. Output Voltage
VIN = VIH or VIL
IIOUTI:<;;20 p.A
VIN = VIH or VIL
-IIOUTI:<;;4.0rnA
IIOUTI :<;; 5.2 rnA
liN
Maximum Input
Current
VIN = Vee or GND
Vee=2-6V
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
±O.1
±1.0
±1.0
p.A
6.0V
Maximum Quiescent
Supply Current
8.0
80
160
p.A
VIN = Vee or GND 6.0V
IOUT=Op.A
Vee=2-6V
Nota 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Nota 2: Unless otherwise specified all voltages are referenced 10 ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mW/'C from 65'C 10 85'C; ceramic "J" package: -12 mW rc from 100'C to 12S'C.
Note 4: For a power supply of SV ± 10% the worst case output voltages (VOH. and VoLl occur for HC at4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at Vee = 5.5V and 4.5V respectively. (The VIH value at 5.5V Is 3.85V.) 1)'e worst case leakage current (liN. Icc. and
loz) occur for CMOS at the higher voltage and so the 6.0V values should be used.
Icc
3-144
:s:
iii:
AC Electrical Characteristics Vcc=5V. TA=25'C. CL =15 pF. t r =tl=6 ns
Symbol
Parameter
Conditions
Maximum Operating Frequency
fMAX
UI
Typ
Guaranteed Limit
Units
50
30
MHz
tpHL. tpLH
Maximum Propagation Delay H to QH or QH
15
25
ns
tpHL. tpLH
Maximum Propagation Delay
Serial Shift/Parallel Load to QH
13
25
ns
tpHL. tpLH
Maximum Propagation Delay
Clock to Output
15
25
ns
Is
Minimum Setup Time Serial Input
to Clock. Parallel or Data to Shift/Load
10
20
ns
ts
Minimum Setup Time Shift/Load to Clock
11
20
ns
Minimum Setup Time Clock Inhibit to Clock
10
20
ns
tH
Minimum Hold Time Serial
Input to Clock or
Parallel Data to Shift/Load
0
ns
tw
Minimum Pulse Width Clock
16
ns
AC Electrical Characteristics CL = 50 pF. tr= tl= 6 ns (unless otherwise specified)
Parameter
Conditions
TA=25'C
Vee
Typ
74HC
TA= -40 to 85'C
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
fMAX
Maximum Operating
Frequency
2.0V
4.5V
6.0V
10
45
50
5
27
32
4
21
25
4
18
21
MHz
MHz
MHz
tpHL. tpLH
Maximum Propag~tion
Delay H to QH or QH
2.0V
4.5V
6.0V
70
21
18
150
30
26
'189
38
33
225
45
39
ns
ns
ns
tpHL. tpLH
Maximum Propagation
Delay Serial Shift/
Parallel Load to QH
2.0V
4.5V
6.0V
70
21
18
175
35
30
220
44 \
37
ns
ns
ns
tpHL. tpLH
Maximum Propagation
Delay Clock to Output
2.0V
4.5V
6.0V
70
21
18
150
30
26
189
38
33
260
52
44
. 225
45
39
ts
Minimum Setup Time
Serial Input to Clock.
or Parallel Data to Shift/Load
2.0V
4.5V
6.0V
35
11
9
100
20
17
125
25
21
150
30
25
ns
ns
ns
Is
Minimum Setup Time
Shift/Load to Clock
2.0V
4.5V
6.0V
38
12
9
100
20
.17
125
25
21
150
30
25
ns
ns
ns
Is
Minimum Setup Time
Clock Inhibit to Clock
2.0V
4.5V
6.0V
35
11
9
100
20
17
125
25
21
150
30
25
ns
ns
ns
tH
Minimum Hold Time Serial
Input to Clock or
Parallel Data to Shift/Load
2.0V
4.5V
6.0V
0
0
0
0
0
0
0
0
0
ns
ns
ns
tw
Minimum Pulse Width.
Clock
2.0V
4.5V
6.0V
30
9
8
80
16
14
100
20
18
120
24
20
ns
ns
ns
tTHL. tTLH
Maximum Output
Rise and Fall Time
2.0V
4.5V
6.0V
30
9
8
75
15
13
95
19
16
110
22
19
ns
ns
ns
tr• tl
Maximum Input Rise and
Fall Time
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
CPO
Power Dissipation
Capacitance (Note 5)
(per package)
Maximum Input Capacitance
CIN
Note 5: CPO determines the no load dynamic power consumption,
o
......
en
....:s:
UI
iii:
.......
"'"
::x:
o
......
en
UI
Is
Symbol
"'"
::x:
Po~ CPO
100
ns
ns
ns
pF
pF
5
10
10
10
Vee< 1+ lee'Vcc, and the no load dynamic current consumption. Is~ Cpo Vee 1+ Icc.
I
3-145
10
CD
o
Logic Diagrams
::E:
•
I'
:::E
:::E
.....
CLOCK
CLOCK INHIBIT
"-~-.......
)o-~~I'JC)o____•
'"
10
CD
....
o
::E:
•
10
:::E
:::E
SIL
TL/F/5316-2
Sll
iTo:
SERIAL
INPUT
I.
t/J
t/J
PARALlH INPUTS
TL/F/5316-3
3·146
~National
\ -=;
~ Semiconductor
microCMOS
MM54HC173/MM74HC173
TRI-STATE® Quad D Flip-Flop
General Description
The MM54HC173/MM74HC173 is a high speed TRI-STATE
QUAD D TYPE FLIP-FLOP that utilizes microCMOS Technology, 3.5 micron silicon gate P-well CMOS. It possesses
the low power consumption and high noise immunity of
standard CMOS integrated circuits, and can operate at
speeds comparable to the equivalent low power Schottky
device. The outputs are buffered, allowing this circuit to
drive 15 LS-TTL loads. The large output drive capability and
TRI-STATE feature make this part ideally suited for interfacing with bus lines in a bus oriented system.
the inputs, forcing the flip flops to remain in the same state.
Clearing is enabled by taking the CLEAR input to a logic "1"
level. The data outputs change state on the positive going
edge of the clock.
The 54HC/74HC logic family is functionally as well as pinout compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static discharge by internal diode clamps to Vee and ground.
The four D TYPE FLIP-FLOPS operate synchronously from
a common clock. The TRI-STATE outputs allow the device
to be used in bus organized systems. The outputs are
placed in the TRI-STATE mode when either of the two output disable pins are in the logic "1" level. The input disable
allows the flip-flops to remain in their present states without
having to disrupt the clock. If either of the 2 input disables
are taken to a logic "1" level, the Q outputs are fed back to
•
•
•
•
•
•
Connection Diagram
Truth Table
Features
Typical propagation delay: 18 ns
Wide operating supply voltage range: 2-6V
TRI-STATE outputs
Low input current: < 1 IJ-A maximum
Low quiescent supply current: 80 IJ-A maximum (74HC)
High output drive current: 6 rnA minimum
Dual-In-Line Package
DATA INPUTS
VCC CLEAR
j'6
lD
15
CLEAR
14
2D
13
3D
12
4D
11
lD
2D
3D
4D
OUTPUT
CONTROL 10
20
30
40
4
5
....'
OUTPUT CONTROL
20
30
G2
10
Data Enable
Data Output
Clear Clock 1 - - - - - - - 1
Q
G1
G2
D
Gl
19
H
LL
L
L
L
DATA
ENABLE
CK
X
L
t
t
t
t
X
X
H
X
L
L
X
X
X
H
L
L
X
X
X
X
L
H
L
Qo
Qo
Qo
L
H
When either M or N (or both) is (are) high the output is disabled to the high-impedance state: however, sequential operation of the flip-flops is not
affected.
6 7 .18
---- -----3
10
Inputs
DATA ENABLE
INPUTS
= high level (steady state)
= low level (steady state)
i = low-to·high level transition
X = don't care (any input including tranSitions)
H
40 CLOCK GND
L
OUTPUTS
TL/F/5317-1
00 = the level of Q before the indicated steady state input conditions were established
Top View
Order Number MM54HC173J or MM74HC173J,N
See NS Package J16A or N16E
3-147
Absolute Maximum Ratings (Notes' & 2)
Operating Conditions
-0.5 to +7.0V
Supply Voltage (Vee)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K. 10K)
DC Output Current. per pin (lOUT)
DC Vee or GND Current. per pin (IcC>
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
Lead Temperature (TO
(Soldering 10 seconds)
Supply Voltage (Vce)
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or F.all Times
Vee=2.0V
(tr.tf}
Vcc=4.5V
Vee=6.0V
-'.5 to Vcc+' .5V
-0.5 to Vcc+ 0.5V
±20mA
±35mA
±70mA
-65'Cto + 150'C
500mW
260'C
Min
2
0
Max
6
Units
Vee
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
,v
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
TA=25'C
Vee
74HC
TA= -40 to 85'C
Typ
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4 .
5.9
V
V
V
3.98
5.48
3.84
5.34
3.7
5.2 _
Y
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIHorVIL
l!ouTIS::20 /J-A
VIN=VIH orVIL
IIOUTIS::6.0 mA
IIOUTIQ.8 mA
VOL
Maximum ,Low Level
Output Voltage
VIN = VIH or VIL
IIOUTI s:: 20 /J-A
2.0V
4.5V
6.0V
2.0
4.5
6.0
4.5V
6.0V
2.0V
4.5V
6.0V
0
0
0
V
'VIN=VIH or VIL
IIOUTIS::6.0 mA
IIOUTIS::7.8 mA
4.5V
6.0V
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VCC or GND
6.0V
±0.1
±1.0
±1.0
/J- A
liN
Maximum Input
Current
loz
Maximum TRI-STATE
Output Leakage
VOUT=VCC or GND
Enable=VIH
6.0V
±0.5
±5.0
±10
/LA
Icc
Maximum Quiescent
Supply Current
VIN=VCCorGND
IOUT=O/J-A
6.0V
8.0
80
160
/LA
,
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2:
Unless otherwise specified all voltages are referenced to ground,
plastic "N" package: -12 mWI'C from 65·C to 85·C; ceramic "J" package: -12 mWI'C from 100·C to 125·C,
Note 4: For a power supply of5V ± 10% the worst case output voltages (VOH. and YOU occur for HC at 4.5V. Thus the 4,5V values shoutd be used when designing
with this supply. Worst case,VIH and V,L occur at Vcc=5.5V and 4.5V respectively. (The V,H value at 5.5V is 3.85V.1 The worst case leakage current (liN. Icc. and
lozl occur for CMOS at the higher voltage and so the 6.0V values should be used:
Note 3: Power Dissipation temperature derating -
3-148
AC Electrical Characteristics Vee=5V, TA = 25°C, CL =45 pF, tr=tf=B ns
Symbol
Parameter
Conditions
fMAX
Maximum Operating Frequency •
tpHL,tpLH
Maximum Propagation
Delay: Clock to Q
tpHL
Maximum Propagation
Delay: Clear to Q
tPZH. tpZL
Maximum Output Enable Time
tpHZo tpLZ
Maximum Output Disable
Time
Typ
Guaranteed Limit
Units
45
30
MHz
31
ns
18
27
ns
RL =1 kO
18
2B
ns
RL =1 kO
CL =5pF
1B
25
ns
ts
Minimum Data Setup Time
20
ns
Is
Minimum Data Enable Setup Time
20
ns
tH
Minimum Data Hold Time
0
ns
tH
Minimum Data Enable Hold Time
0
ns
tw
Minimum Clock Pulse Width
16
ns
AC Electrical Characteristics Vee = 2.0V to B.OV, CL = 50 pF, 1,= tf= B ns (unless otherwise specified)
Symbol
Param"ter
Conditions
Vee
·TA=25°C
Typ
7.HC
TA= -40 to 85"C
54HC
TA= -55 to 125°C
Units
Guaranteed Limits
fMAX
Maximum Operating
Frequency
CL =50 pF
2.0V
4.5V
B.OV
10
45
55
5
27
32
4
21
25
4
1B
21
MHz
MHz
MHz
tpHL, tpLH
Maximum Propagation
Delay from Clock to Q
CL =50pF
CL =150 pF
2.0V
2.0V
BO
110
175
225
220
280
262
338
ns
ns
CL=50pF
CL=150pF
4.5V
4.5V
23
28
35
45
44
56
53
68
ns
ns
CL =50pF
CL=150pF
6.0V
'6.0V
21
26
30
38
38
48
45
57
ns
ns
CL =50 pF
CL=150pF
2.0V
2.0V
70
100
150
200
189
252
224
298
ns
ns
CL =50pF
CL=150pF
4.5V
4.5V
20
25
30
40
38
50
45
60
ns
ns
CL =50 pF
CL =150 pF
6.0V
6.0V
17
22
26
34
32
43
38
51
ns
ns
Maximum Output
Enable Time
RL=1 kO
CL =50pF
CL =150 pF
CL =50pF
CL =150 pF
CL =50 pF
CL =150 pF
2.0V
2.0V
4.5V
4.5V
B.OV
6.0V
70
100
20
25
17
22
150
200
30
40
26
34
189
252
38
50
32
43
224
298
45
60
38
51
ns
ns
ns
ns
ns
ns
tpHZ. tpLZ
Maximum Output Disable
Time
RL =1 kO
CL =50pF
2.0V
4.5V
6.0V
70
20
17
150
30
26
189
38
32
224
45
38
ns
ns
ns
Is
Minimum Data or Data
Enable Setup Time
2.0V
4.5V
6.0V
100
20
17
125
25
. 21
150
30
25
ns
ns
ns
tJ;lEM
Minimum Removal
Time
2.0V
4.5V
6.0V
90
1B
15
112
22
19
135
26
22
ns
ns
ns
tH
Minimum Data or Data Enable
Hold Time
2.0V
4.5V
B.OV
0
0
0
0
0
0
0
0
0
ns
ns
ns
tw
Minimum Clear or Clock
Pulse Width
2.0V
4.5V
B.OV
80
16
14
100
20
17
120
24
20
ns
ns
ns
tpHL
tpZH,tpZL
Maximum Propagation
Delay from Clear to Q
-
3·149
30
9
8
,
AC Electrical Characteristics
(Continued)
VCC=2:0V to 6.0V. CL =50 pF. t r =tl=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=25"C
74HC
54HC
TA= -40 to 85"C TA;;" -55 to 125"C Units
Typ
t-rHL. tTLH Maximum Output
Rise and Fall Time
2.0V
4.5V
6.0V
25
7
5
2.0V
4.5V
6.0V
Guaranteed Limits
60
12
10
75
15
13
90
1B
15
ns
ns
ns
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
tr.tl
Maximum Input Rise and
Fall Time
CPD
Power Dissipation Capacitance
CIN
Maximum Input Capacitance
5
10
10
10
pF
COUT
Maximum Output
Capacitance
10
20
20
20
pF
(per flop)
BO
pF
-
Note 5: Cpo determines the no load dynamic power consumption. Po=Cpo Vrxl-I+ Icc Vee. and the no load dynamic current consumption. IS=CpO Vee
,
1+ ICC.
,
/
,
,
3·150
~National
~ Semiconductor
microCMOS
MM54HC174/MM74HC174
Hex D Flip-Flops With Clear
General Description
Features
These edge triggered flip-flops utilize microCMOS Technology, 3.5 micron silicon gate P-well CMOS, to implement 0type flip-flops. They possess high nOise. immunity, low power, and ,speeds comparable to low power Schottky TTL circuits. This device contains 6 master-slave flip-flops with a
common clock and common clear. Data on the 0 input having the specified setup and hold times is transferred to the
output on the low to high transition of the CLOCK input. The
CLEAR input when low, sets all outputs to a low state.
Each output can drive 10 low power Schottky TTL equivalent loads. The MM54HC174/MM74HC174 is functionally
as well as pin compatible to the 54LS174/74LS174. All inputs are protected from damage due to static discharge by
diodes to Vee and ground.
•
•
•
•
•
Typical propagation delay: 16 ns
Wide operating voltage range: 2-6V
Low input current: 1 /LA maximum
Low quiescent current: 80 /LA (74HC Series)
Output drive: 10 LSTTL loads
a
Connection and Logic Diagrams
Dual-In-Llne Package
(3)
010-----1
(2)
Q1
02 "G--....,HH
'03 ~----I-H
1D
2D
20
30
3D
03
GNO
TUF/531B-1
04G--....,I-H
Order Number MM54HC174J or MM74HC174J, N
See NS Package J16A or N1~E
Truth Table
osG----....,HH
os
0-;..----1-11-1
06
. (Each Flip-Flop)
Inputs
Outputs
Clear
Clock
D
Q
L
H
H
H
X
X
i
i
H
L
L
H
L
X
00
L
06
CLOCK
CLEAR
H = High level (steady state)
L = Low level (steady state)
X = Don't Care
t = Transition from low to high level
00 = The level of Q before the indicated steady state
input condHions were established.
O-~O-
_ _.......
TUF/5318-2
3-151
Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage (Vee)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K. 10K)
DC Output Current. per pin (lOUT)
DC Vee or GND Currerit. per pin (lee)
Storage Temperature Range (T8m)
: Power Dissipation (Po) (Note 3)
Lead Temperature (Tt.l
(Soldering 10 seconds)
Operating Conditions'
-0.5 to + 7.0V
-1.5 to Vee + 1.5V
-0.5 to Vee+0:5V
±20mA
±25mA
±50mA
-65·Cto + 1500C
500mW
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TAl
MM74HC
MM54HC
"Input Rise or Fall Times
(fr. tf) Vee = 2.0V
Vee = 4.5V
Vee = 6.0V
260·C
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25"C
Typ
74HC
TA= -40 to 8S·C
S4HC
TA=-SSto125"C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9.
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VOL
liN
Maximum Low Level
Output Voltage
Maximuni Input
Current
VIN = VIH or VIL
IIOUTr:S:20 /LA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
VIN ~ VIH or VIL
!IOUTI:S:4.0mA
!IOUTI :s: 5.2 mA
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
VIN = VIH or VIL
!lOUT!:S:20 /LA
2.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5V
6.0V
VIN = VIH or VIL
IIOUT!:S:4.0 rnA
IIOUT!:S:5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
VIN=VCC or GND
6.0V
±0.1
±1.0
±1.0
/LA
V
V
V
Maximum Quiescent VIN=VccorGND 6.0V
8.0
80
160
/LA
Supply Current
IOUT=O /LA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Nola 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mWrC from 65"C to 85"C; ceramic "J" package: -12 mW/'C from l00'C to 125'C.
Note 4: For a power supply of 5V ± 10% Iha worst case output voltages (YOH. and VoLl ooeur for HC at 4.5V. Thus the 4.5V values should be used when
deSigning with this supply. Worst case VIH and VIL occur at VOC= 5.5V and 4.5V respectively. (The VIH value at 5.5V Is 3.85V.) The worst cass leakage current (lIN.
IOC. and IOz) occur for CMOS at the higher voltage and so the 6.0V values should ba used.
lee
".
"3-152
AC Electrical Characteristics Vcc=5V. TA=25°C.CL =15pF. t r =tf=6ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
fMAX
Maximum Operatil\g
Frequency
50
30
MHz
tpHL. tpLH
Maximum Propagation
Delay. Clock or Clear to Output
16
30
ns
tREM
Minimum Removal Time.
Clear to Clock
-2
5
ns
ts
Minimum Setup Time
Data to Clock
10
20
ns
tH
Minimum Hold Time
Clock to Data
0
5
ns
tw
Minimum Pulse Width
Clock or Clear
10
16
ns
AC Electrical Charact.eristics CL = 50 pF. tr= tf= 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=25"C
Typ
fMAX
Maximum Operating
Frequency
2.0V
4.5V
6.0V
tpHL. tpLH
Maximum Propagation
D~lay Clock or Clear to Output
2.0V
4.5V
6.0V
tREM
Minimum Removal Time
Clear to Clock
ts
74HC
TA=-40to85°C
54HC
TA= -55 to 125"C
Units
Guaranteed Umlts
5
27
31
4
21
24
3
18
20
MHz
MHz
MHz
55
18
16
165
33
28
206
41
35
248
49
42
ns
ns
ns
2.0V
4.5V
6.0V
1
1
1
5
5
5
5
5
5
5
5
5
Minimum Setup TIme
Data to Clock
2.0V
4.5V
6.0V
42
12
10
100
20
17
125
25
21
150
30
25
ns
ns
ns
tH
Minimum Hold Time
Clock to Data
2.0V
4.5V
6.0V
1
1
1
5
5
5
5
5
5
5
5
5
ns
ns
ns
tw
Minimum Pulse Width
Clock or Clear
2.0V
4.5V
6.0V
35
10
8
80
16
14
106
20
18
120
24
20
ns
ns
ns
tTLH. trHL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
tr• tf
Maximum Input Rise and
Fall Time
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
CPO
Power Dissipation
Capacitance (Note 5)
qN
Maximum Input
Capacitance
(per package)
ns
ns
ns
pF
136
5
.
10
10
10
pF
Note 5: Cpo determines the no load dynamic power consumption. Po = Cpo vccl f + lee Vee. and the no load dynamic current consumption, Is = Cpo Vee , + lee.
3-153
..... r--------------------------------------------------------------------------------,
U)
~. ~ National
.
~ .~ Semiconductor'
:::E
.
microCMOS
:::E
~
......... MM54HC175/MM74HC175
i
U)
:::E
:::E
Quad D-Type Flip-Flop With Clear
General Description
This high speed O-TYPE FLIP-FLOP with complementary
outputs utilizes microCMOS Technology, 3.5 micron silicon
gate P-well CMOS, to achieve the high noise immunity and
low power consumption of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads.
Information at the 0 inputs of the MM54HC1751
MM74HC175 is transferred to the
and Q outputs on the
positive going edge of the clock pulse. Both true and complement outputs from each flip flop are externally available.
All four flip flops are controlled by a common clock and a
common CLEAR. Clearing is accomplished by a negative
, pulse at the CLEAR input. All four outputs are cleared to a
logical "0" and all four Q outputs to a logical "1."
a
a
The 54HC/74HC logic family is functionally as well as pinout compatible with the standard 54LSI74LS logic family.
All inputs are protected from damage due to static discharge by internal diode clamps to Vee and ground.
Features
•
•
•
•
•
Typical propagation delay: 15 ns
Wide operating supply voltage range: 2-6V
Low input current: < 1 p.A maximum
Low quiescent supply current: 80 /LA maximum (74HC)
High output drive current: 4 mA minimum (74HC)
Connection Diagram
Dual-In-Wne Package
vee
40
4Q
13
4
c:LEAII
10
10
20
20
20
ONO
Top View
Order Number MM54HC175J or MM74HC175J,N
See NS Package J16A or N16E
Truth Table
(Each Flip-Flop)
Inputs
Outputs
Clear
Clock
D
Q
Q
L
H
H
H
X
X
t
t
H
L
L
H
L
H
L
H
L
X
00
00
H= high level (steady ala1e)
'L = low level (steady state)
X = irrelevant
t = transition from low to high leval
00 = the laval of Q before the Indicated
s1eady·sta1e input conditions were established
3-154
TUF/5319-1
Absolute Maximum Ratings (Notes 1 &2)
Operating Conditions
Supply Voltage (Vee)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Supply Voltage (Vee)
Clamp Diode Current (11K. 10K>
DC Output Current. per pin (lOUT)
DC Vee or GND Current. per pin (IcC>
Storage Temperature RilOge (TSTG)
Power Dissipation (Po) (Note 3)
Lead Temperature (TL>
(Soldering 10 seconds)
-0.5 to +7.0V
-1.5 to Vcc+ 1.5V
-0.5 to VCC+0.5V
±20mA
±25mA
±50mA
DC Input or Output Voltage
(VIN.VOUT)
Operating Temp. Range, (TN
MM74HC
MM54HC
-65'Cto + 150'C
500mW
Min
2
Max
6
Units
V
0
Vcc
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
(tr• tt>
Vcc=2.0V
Vcc=4.5V
Vcc=6.0V
260'C
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25'C
Typ
74HC
TA=-40to85'C
54HC
TA=-55to125'C
Units
GUaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
IIOUTI s: 20 ,...A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4:2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V,
V
V
VIN = VIH or VIL
IIOUTI s: 4.0 mA
IIOUTIS:5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0,.4
0.4
V
V
VIN=VeeorGND
6.0V
±0.1
, ±1.0
±1.0
,...A
VIN = VIH or VIL
ilOUTI S:4.0 mA
IIOUTIS:5.2 mA
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
VIN = VIH or VIL
IIOUTIS:20 ,...A
160
Maximum Quiescent VIN=VeeorGND 6.0V
8
80
,...A
Supply Current
IOUT=O,...A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note,2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mWrc from 65'C to 85'C; ceramic "J" package: - t 2 mWI"C from 100"C to 125'"C.
Note 4: For a power supply of 5V ± 10% the worst case output voltages (YOH. and VoLl occur for HC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at Vcc=5.5Vand 4.5V respectively. (The VIH value at 5,5V is 3.85V.) The worst case leakage current (liN. ICC. and
'ozl occur for CMOS al the higher voltage and so the 6.0V values should be used.
Icc
3·155
AC Electrical Characteristics Vcc=5V. TA=25°C;CL =15pF.tr =t,=6ns
Symbol
Conditions Typ
Parameter
60
35
MHz
tpHL. tpLH Maximum Propagation
Delay. Clock to Q or Q
15
25
ns
tpHL. tpLH Maximum Propagation
Delay. Reset to Q or Q
13
21
ns
fMAX
Maximum Operating
Frequency
Guaranteed
Units
Limit
tREC
Minimum Removal
Time. Clear to Clock
20
ns
Is
Minimum Setup Time. Data to Clock
20
ns
tH
Minimym Hold Time. Data from Clock
0
ns
IW
Minimum Pulse Width. Clock or Clear
16
ns
10
AC Electrical Characteristics Vee = 2.0V to 6.0V. CL = 50 pF. Ir= 1,=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25"C
Vee
74HC
TA= -4010 85°C
Typ
54HC
TA= -55 to 125"C
Units
Guaranteed Umits
fMAX
Maximum Operating
Frequency
2.0V
4.5V
6.0V
12
60
70
6
30
35
5
24
.28
4
20
24
IpHL. tpLH
Maximum Propagation
Delay. Clock to Q or Q
2.0V
4.5V
6.0V
80
15
13
150
30
26
190
38
32
225
45
38
tpHL. tpLH
Maximum Propagation
Delay. Reset to Q or Q
2.0V
4.5V
6.0V
64
14
12
125
25
21
158
32
27
186
37
32
ns
ns
ns
IREM
Minimum Removal Time
Clear to Clock
2.0V
4.5V
6.0V
100
20
17
125
25
21
150
30
25
ns
ns
ns
Is
Minimum Setup Time
Data to Clock
2.0V
4.5V
6.0V
100
20
17
125
25
21
150
30
25
ns
ns
ns
IH
Minimum Hold Time
bata from Clock
2.0V
4.5V
6.0V
0
0
0
0
0
0
0
0
0
ns
ns
ns
tw
Minimum Pulse Wid1h
Clear or Clock
2.0V
4.5V
6.0V
80
16
14
100
20
17
120
24
20
ns
ns
ns
Ir• If
Maximum Input Rise and
Fall Time
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
In.H.ITHL
Maximum
Output Rise and
Fall Time
2.0V
4.5V·
6.0V
75
15
13
95
19
16
110
ns
ns
ns
Cpo
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Inpul
Capacitance
(per
package)
30
9
8
30
9
8
{"',
22
19
,
ns
ns
ns
pF
150
5
MHz
MHz
MHz
10
10
10
pF
Nota 5: CPO detennlnes the no load dynamic ~r consumption, Po= Cpo Vrxfl f+ Icc Vr;c. and the no load dynamic current consumption, Is = Cpo Vce f+ Icc.
3·156
3:
3:
Logic Diagram
UI
:x::
""
....
......
0
01
0
0
C
CLOCK
2
3
CR
UI
......
3:
01
3:
......
01
0
....
......
:x::
""
UI
02
D
0
7
02
C
6
CR
D
0
C
11
CR
D
C
CR
10
Q
15
14
02
Q3
03
Q4
04
RESET
TLIF/5319-2
3-157
_
CD
r-----~------------------------------------------~----------------------------_,
.
~ Semiconductor
~ ~National
it
:E
:E
.....
PRELIMINARY
---
\
")
microCMOS
--
MM54HC181/MM74HC181
~ Arithmetic Logic Units/Function Generators
CD
""
an
:E
:E
General Description
These arithmetic logic units (ALU)/function generators uti- .
lize microCMOS Technology, 3.5 micron silicon gate P-well
CMOS. They possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as
well as the ability to drive 10 LS-TTL loads.
The MM54HC181/MM74HC181 are arithmetic logic unit
(ALU)/function generators that have a complexity of 75
equivalent gates on a monolithic chip. These circuits perform 16 binary arithmetic operations on two 4-bit words as
shown in Tables 1 and 2. These operations are selected by
the four function-select lines (SO, 51, 52, 53) and include
addition, subtraction, decrement, and straight transfer.
When performing arithmetic manipulations, the internal.carries must be enabled by applying a lOW-level voltage to the
mode control input (M). A full carry look-ahead scheme is
made available in these devices for fast, simultaneous carry
_generation by means of two cascade-outputs (pins 15 and
17) for the four bits in the package. When used in conjunction with the MM54HC182 or MM74HC182, full carry lookahead circuits, high:speed arithmetic operations can be performed. The method of cascading HC182 circuits with these
ALU's to provide multi-level full carry look-ahead is illustrated under typical applications data for the MM54HC1821
MM74HC182.
'
Connection Diagram
If high speed is not of importance, a ripple-carry input (Cn)
and a ripple-carry output (Cn + 4) are available. However,
the ripple-carry delay has also been minimized so that arithmetic manipulations for small word lengths can be performed without external circuitry.
Features
• Full look-ahead for high-speed operations on
long words '
• Arithmetic operating modes:
Addition
Subtraction
Shift operand a one position magnitude comparison
Plus twelve other arithmetic operations
• Logic function modes:
Exclusive-OR
Comparator
AND,NAND,OR,NOR
Plus ten other logic operations
• Wide operating voltage range: 2V -6V
• Low input'current: 1 ",A maximum
• Low quiescent current: 80 ",A maximum
Pin
Dual-In-Llne Package
INPUTS
,
OUTPUTS
,
I
\
Vcc A1
r
24
23
2
80
81
AO
A2
22
3
S3
82
21
4
S2
A3 83
20
5
.
S1
I
19
6
r
17
8
7
16
15 14
9
M
f
INPUTS
FO
\
10
F1
13
PinNas.
Function
19,21,23,2
Word A Inputs
83, 82, 81, 80
18,20,22,1
Word 8 Inputs
S3, 52, 51, SO
3,4,5,6
Function-Select
Inputs
Cn'
7
Inv. Carry Input
M
8
Mode Control
Input
F3,F2,F1,FO
13,11,10,9
Function Outputs
A=8
14
Comparator Outputs
P
15
Carry Propagate
Output
Cn +4
'16
Inv. Carry Output
G
17
Carry Generate
Output
Vee
24
Supply Voltage
GND
12
Ground
11 112
F2 GND'
•
'
OUTPUTS
Top View
Designation
A3, A2, A1, AO
\
G Cn+4 P A=8 F3
18
SO Cn
Des~gnations
TVF/5320-1
Order Number MM54HC181J or MM74HC181J, N
See NS Package J24F or N24C
3-158
General Description (Continued)
These circuits will accommodate active-high or active-low
data, if the pin designations are interpreted as shown below.
but also to provide. 16 possible functions of two Boolean
variables without the use of external circuitry. These logic
functions are selected by use of the four function-select inputs (SO, 51, 52, 53) with the mode-control input (M) at a
high level to disable the internal carry. The 16 logic functions are detailed in Tables 1 and 2 and include exclusiveOR, NAND, AND, NOR, and OR functions.
Subtraction is accomplished by 1's complement addition
where the 1's complement of the subtrahend is generated
i(1ternally. The resultant output is A-B-1, which requires
an end-around or forced carry to produce A-B.
The 181 can also be utilized as a comparator. The A=B
output is internally decoded from the function outputs (FO,
F1, F2, F3) so that when two words of equal magnitude are
applied at the A and B inputs, it will assume a high level to
indicate equality (A = B). The ALU should be in the subtract
mode with Cn=H when performing this comparison. The
A=B output is open-drain so that it can be wire-AND connected to give a comparison for more than four bits. The
carry output (Cn + 4) can also be used to supply relative
magnitude information. Again, the ALU should be placed in
the subtract mode by placing the function select inputs 53,
52, 51, SO at L, H, H, L, respectively.
These circuits have been designed to not only incorporate
all of the deSigner's requirements for arithmetic operations,
The MM54HC1 81 IMM74HC1 81 can be used with the signal
designations of either Figure 1 or Figure 2.
The logic functions and arithmetic operations obtained with
signal designations as in Figure 1 are given in Table 1; those
obtained with the signal designations of Figure 2 are given
in Table 2.
CCI
1
23
22
21
20
19
18
9
10
11
13
7
16
15
BO
A1
B1
fli2
B2
A3
B3
FO
F1
F2
F3
en
Cn +4
X
y
Active-Low Data (Table 1)
AO
BO
A1
B1
A2
B2
A3
B3
FO
F1
F2
F3
Cn
Cn +4
p
IT
Input
Cn
Output
Cn +4
Active-High Data
(Figure 1)
Active-Low Data
(Figure 2)
H
H
L
L
H
L
H
L
A,;;;B
A>B
AB
A,;;;B
17
-
Table I
17)->-(
Cn
., .,
IrlT Itlt
.2 82
A=B r---114)
HCISI
18)-
r-
M
FO
Fl
F2
F3
C n +4
It 11~;
IX)
113)11~) TTItlT
IJ,) )3)
YO
xo
Yl
Xl
A3 83
Y2 X2
Y
x
1(17) (15)
TT
V3 X3
x-17l
11;<
HCIS,
Cn
Cn+x
Cn +y
(1~1
IX)
+z
Y-(10)
Cn
J)
TLlF/5320-2
FIGURE 1
Active High Data
Selection
M=H
Logic
S3 S2 S1 SO Functions
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
....
....
The 54HC174HC logic family is speed, function, and pinout
compatible with the standard 54L5174L5 logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to Vee and ground.
2
I I I I
iii:
~
:::I:
AO
AD BO
CCI
(')
Pin Number
(231122)
:::I:
....
........
iii:
(')
ALU SIGNAL DESIGNATIONS
Active-High Data (Table 1)
12) (1)
iii:
iii:
U'I
.co.
L \ L F=A
L H F=A+
H L F=AB
H H F=O
L L F=AB
L H F=B
H L F=Ae
H H F=AB
L L F=A+
L H F=Ae
H L F=B
H H F=AB
L L F=1
L H F=A+
H L F=A+
H H F=A
M = Lj Arithmetic Operations
Cn = H (no carry)
F=A
B F=A+ B
F""A+ B
F = Minus 1 (2's Compl)
F=APlusAB
F=(A + B)PlusAB
B F=A Minus B Minus 1
F=ABMinus1
B F=APlusAB
B F=APlusB
F=(A + B) PlusAB
F=ABMinus 1
F=APlusAo
B F=(A + B) Plus A
B F=(A + B) Plus A
F=A Minus 1
'Each bit is shifted to the next more Significant position.
3-159
Cn = L (with carry)
F=A PillS 1
F=(A + B) Plus 1
F=(A + B) Plus 1
F=Zero
F=A Plus AB Plus 1
F = (A + B) Plus AB Plus 1
F=A Minus B
F=AB
F = A Plus AB Plus 1
F=A Plus B Plus 1
F= (A + B) Plus AB Plus 1
F=AB
F=A Plus A Plus 1
F=(A + B) Plus A Plus 1
F=(A + B) Plus A Plus 1
F=A
.-
CD
.-
o
::c
r-------------------------------------~----------------------------------------------I
General Description
(Continued)
(2)
~
::IE
::IE
....
(1)
(23)
(~2)
(21) (20) (19) (18)
(7)
.CD
.-
.
HC181
o
::c
A
=B
(14)
(8)
In
::IE
::IE
GO
(7)
(13)
Cn
(10)
(9)
(11)
(12)
TLlF/5320-3
FIGURE 2
Table II
Active Low Data
Selection
53
52
51
SO
M=H
Logic
Functions
L
L
L
L
L
L
L
L
H
H
H
,H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H.
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
E=A
F=AB
F=A+
F=1
F=A+
F=B
F=A+
F=A+
F=AB
F=A+
F=B
F=A+
F=O
F=AB
F";AB
F=A
M = L; Arithmetic Operations
-
B
B
B
B
B
B
Cn = L (no carry)
Cn = H (with carry)
.F=A.
F=AMinus 1
F=AB
F=AB Minus 1
F=(AB)
F=ABMinus1
F = Minus 1 (2's Compl) F=Zero
F=A Plus (A + B)
F=A Plus (A + B) Plus 1
F=AB Plus (A + B) Plus 1
F=AB Plus (A + B)
F=A Minus B Minus 1
F=AMinusB
F=A+ B
F=(A + BPlus 1
F=A Plus (A + B)
F=A Plus (A + B) Plus 1
F=A Plus B Plus 1
F='A Plus B
F=AB Plus (A + B) Plus 1
F=ABPlus(A + B)
F=(A + B) Plus 1
F=A+ B
F=A Plus A Plus 1
F=APlusA*
F=ABPlusA
F=AB Plus A Plus 1
F=ABPlusA
F = AB Plus A Plus 1
F=A Plus 1
F=A
'Each bit Is shifted to the next more significant pOSition.
Number
of
Bits
Typical
Addition Times
1 t04
5t08
9to 16
17 to 64
20ns
30 ns
30 ns
50ns
Arlthmetlcl
Logic Units
Package Count
Look Ahead
Carry Generators
Carry Method
Between
ALU's
1
0
0
1
.2t05
None
Ripple,
Full Look-Ahead
Full Look-Ahead
2
30r4
5to 16
3-160
-
Absolute Maximum Ratings (Notes 1 &2)
Supply Voltage {Veel
DC Input Voltage (VIN)
DC Output Voltage (Vour)
Clamp Diode Current (11K. 10K>
'DC Output Current. per pin (lour)
DC Vee or GND Current. per pin (Ieel
Storage Temperature Range (T8TG)
Power Dissipation (Po) (Note 3)
Lead Temperature (TLl
(Soldering 10 seconds)
i!:
i!:
(II
Operating Conditions
-0.5 to +7.0V
Supply Voltage {Veel
DC Input or Output Voltage
(VIN. Your)
Operating Temp. Range (TAl
MM74HC
MM54HC
Input Rise or Fall Times
Vee=2.0V
(tr. til
Vee=4.5V
Vee=6.0V
-1.5toVee+ l .5V
:"'0.5 to Vee+0.5V
±20mA
±25mA
±50mA
-65·Cto + 150"C
500mW
260·C
Min
2
0
Max
Vee
Units
V
V
-40
-55
+85
+125
·C
·C
6
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=2S·C
Typ
74HC
TA= -40 to 85"C
S4HC
TA= -5510 125"C
Units
. Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
InpU1 Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
(any output except
A=B)
VIN = VIH or VIL
!lour!:>:20 p.A
VIN = VIH or VIL
Iiour! :>:4.0 rnA
!lour!:>:5.2mA
ILKG
Maximum Leakage
Open Drain Output Current
(A = 8 Output)
VIN=VIH orVIL
Vour=Vce
VOL
Maximum Low Level
OutpU1 Voltage
VIN = VIH or VIL
!lour!:>:20 /l:A
liN
Maximum Input
Current
2.0V
4.5V
6.0V
2.0.
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
0.5
5.0
10
p.A
6.0V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
!IOUT!:>:4.0 mA
!IOUT!:>:5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VccorGND
6.0V
±0.1
±1.0
±1.0
p.A
.p.A
Maximum Quiescent
8.0
160
VIN=VeeorGND 6.0V
80
Supply Current
lour=Op.A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" peckage: -12 mWI"C from 6S'C 1I18S'C; ceramic "J" package: -12 mWI"C from l00'C to 125'C.
Note 4: For apower supply of sv ± 10% the worst case output voltages (YOH. and VoLl occur for HC at 4.SV. Thus the 4.SV values should be used when designing
with this supply. Worst case VIH and VIL occur at Vcc= S.SV and 4.SV respectively. (The VIH value at S.5V is 3.85V.) The worst case leakage current (liN. Icc. and
loZ> occur for CMOS at the higher voltage and so the 8.0V values sho~ld be used.
Icc
3-161
0l:Io
:::c
o.....
CO
.....
.....
i!:
i!:
..,.
0l:Io
:::c
o.....
CO
.....
.-
CD
.-
(,)
::z::
r!
::E
::E
.....
.CD
.....
(,)
::z::
r-------------------------------------------------------------------~----------------,
AC Electrical Characteristics Vee "" 5V, TA =
Typ
Guaranteed
Umlt
Unlta
13
20
ns
M=OV, SO=S3=Vee
Sl =SO=OV
(S'Ummode)
30
45
ns
Maximum Propagation
Delay from any
AorBtoCN+4
M=OV, SO=S3=OV
Sl=S2=Vee
(Ditt. mode)
30
45
ns
tpfiL, tpLH
Maximum Propagation
Delay from Cn to any F
M=OV
(Sum or
Ditt. mode)
20
30
ns
tpHLo tpLH
Maximum Propagation
Delay from any
AorBtoG
M=OV,SO=
S3 = Vee
Sl=S2=OV
(Sum mode)
20
30
ns
tpHL, tpLH
Maximum Propagation
Delay from any
AorBtoG
M=OV,SO=
.S3=OV
Sl=S2=Vee
(Dittmode)
20
30
ns
tpHL, tpLH
Maximum Propagation
Delay from any
AorBtoP
M=OV,SO=
S3=Vee
Sl=S2=OV
(Sum mode)
27
41
'ns
tpHLo tpLH
Maximum Propagation
Delay from any
AorBtoP
M=OV,SO=
S3=OV
Sl=S2=Vee
(Dittmode)
24
37
ns
tpHL, tpLH
Maximum Propagation
Delay from AI or BI to FI
M=OV,SO=
S3 = Vee
Sl =S2=OV
(Sum mode)
20
30
ns
tpHL, tpLH
M=OV,SO=
Maximum Propagation
Delay from AI or BI to FI . S3=OV·
Sl=S2=Vee
(Ditt mode)
19
29
ns
tpHL, tpLH
Maximum Propagation
Delay from AI or, BI to FI
M=Vee
(Logic mode)
25
37
ns
tpHL, tpLH
Maximum Propagation
Delay' from any
AorBtoA=B
M=OV,SO=
S3=OV
Sl=S2=Vee
(Dittmode)
25
37
ns
Symbol
Parameter
tpHL, tpLH
Maximum Propagation
Delay from Cn to Cn + 4
tpHL, tpLH
Maximum. Propagation
Delay from any
AorBtoCN+4
tpHL, tpLH
;z
::E
::E
25°C, CL = 15 pF, tr = t, = 6 ns
Conditions
3-162
AC Electrical Characteristics CL =
Symbol
Parameter
Conditions
50 pF, tr = tf = 6 ns (unless otherwise specified)
Vee
TA=25°C
74HC
54HC
TA=-40t085°C
TA= -55 to 125°C
Typ
tpHL, tpLH
Maximum Propagation
Delay from Cn to Cn + 4
tpHL, tpLH
Maximum Propagation
Delay from any
AorBtoCn +4
M=OV,SO=
S3=Vcc
S1 =S2=OV
(Sum mode)
2.0V
4.5V
6.0V
tpHL, tpLH
Maximum Propagatio~
Delay from any
AorBtoCn +4
M=OV,SO=
S3=OV
S1=52=Vcc
(Diff mode)
2.0V
4.5V
6.0V
tpHL, tpLH
Maximum Propagation
Delay from Cn to any F
M=OV
(Sum or
Diffmode)
2.0V
4.5V
6.0V
tpHL, tpLH
Maximum Propagation
Delay from any
AorBtoG
M";'OV,SO=
53=Vcc,
51 =52=OV
(Sum mode)
tpHL, tpLH
Maximum Propagation
Delay from any
AorBtoG
tpHL, tpLH
125
25
22
-.
155
31
28
190
'38
33
ns
ns
ns
250
50
43
325
63
53
375
75
65
ns
ns
ns
250
50
43
325
63
53
375
75
65
ns
ns
ns
65
22
14
150
32
28
190
40
35
225
48
42
ns
ns
ns
2.0V
4.5V
6.0V
70
20
12
175
35
30
220
44
38
263
53
45
ns
ns
ns
M=OV, 50=
S3=OV
S1=S2
(Diffmode)
2.0V
4.5V
6.0V
65
23
16
165
33
29
210
42
37
250
50
44
ns
ns
ns
Maximum Propagation
Delay from any
AorBtoP
M=OV,SO=
53 = Vcc
S1=52=OV
(5ummode)
2.0V
4.5V
6.0V
80
30
25
220
44
37
275
55
47
330
66
56
ns
ns
ns
tpHL, tpLH
Maximum Propagation
Delay from any
AorBtoP
M=OV,SO=
53=OV
S1=52=Vcc
(Diffmode)
2.0V
4.5V
6.0V
75
27
24
195
39
34
244
49
43
293
60
51
ns
ns
ns
tpHL, tpLH
Maximum Propagation
Delay from AI or BI to FI
M=OV,SO=
S3=Vcc
51 =52=OV
(5ummode)
2.0V
4.5V
6.0V
70
26
21
180
36
31
225
45
39
270
54
47
ns
ns
ns
160
32
27
200
40
34
290
48
41
ns
ns
ns.
,
.
2.0V
4.5V
6.0V
Units
Guaranteed Limits
110
35
30
tpHL, tpLH
Maximum Propagation
Delay from AI or BI to FI
M=OV,SO=
S3=OV
51 =52=VcC
(Diffmode)
2.0V
4.5V
6.0V
tpHL, tpLH
Maximum Propagation
Delay from AI or BI to FI
M=Vcc
(Logic mode)
2.0V
4.5V
6.0V
180
30
23
200
40
34
250
50
43
300
60
51
ns
ns
ns
tpHL, tpLH
Maximum Propagation
Delay from any
AorBtoA=B
M=OV,SO=
S3=OV
S1=S2=Vcc
(Diffmode)
2.0V
4.5V
6.0V
180
30
23
200
40
34
250
50
43
300
60
51
ns
ns
ns
tTLH, tTHL
Maximum Output Rise
and FaUTIme
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
CPD
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input
Capacitance
pF
5
15
15
15
pF
Note 5: CpO determines the no loed dynamic power consumption. Po= Cpo vcr! f+ lee Vee. and the no loed dynamic current consumption. IS = Cpo Vee f+ lee.
i
3-163
....
....co
o
:c
0:1'
,...
::::E
::::E
....
....
co
....
o
Parameter Measurement Information
Lpgic Mode Test Table
Parameter
Input
Under
Test
:c
0:1'
tpHL. tpLH
AI
::::E
::::E
tpHL. tpLH
91
an
SUM Mode Test Table
Parameter
Input
Under
Test
Function Inputs: S1=S2=M=Vee. SO=S3=0 V
Other Input
Same Bit
Apply
Vee'
Apply
GND
Other Data'inputs
Apply
Vee
Other Input
Same Bit
Apply
Vee
Apply
GND
None
tpHL. tpLH
BI
AI
None
Remaining
AandB
tpHL. tpLH
AI
BI
None
None
tpHL. tpLH
BI
AI
None
None
tpHL. tpLH
AI
None
BI
Remaining
B
tpHL. tpLH
BI
None
AI
Remaining
B
tpHL. tpLH
Cn
None
None
All
A
tpflL. tpLH
AI"
None
BI
Remaining
B
tpHL. tpLH
BI
None
AI
Remaining
B
Parameter
Out-ot-Phase
FI
Out-ot-Phase
Output
Under
Test·
Output
Waveform
Cn
.
FI
In-Phase
Cn
FI
In-Phase
P
In-Phase
P
In-Phase
G
In-Phase
G
In-Phase
AnyF
orCn +4
In-Phase
Cn +4
Out-ot-Phase
Cn +4
Out-ot-Phase
Output
Under
Test
Output
Waveform
FI
In-Phase
FI
Out-ot-Phase
P
In-Phase
P
Out-ot-Phase
G
In-Phase
G
Out-ot-Phase
A=B
In-Phase
A=B
Out-ot-Phase
Cn +4
oranyF
In-Phase
Cn +4
Out-of-Phase
Cn +4
In-Phase
Other Data Inputs
Apply
Vee
Remaining
AandB
BI
Input
Under.
Test
FI
None
AI
Dill Mode Test Table
Output
Waveform
Remaining
A and B. Cn
Remaining
None
None
AI
A and B. Cn
S1=S2=M=OV
Function Inputs: SO=S3= Vee
None
BI
tpHL. tpLH
-
Output
Under
Test
Apply
GND
Apply
GND
Remaining
.AandB.Cn
Remaining
A and B,Cn
Remaining
A.Cn
Remaining
A.Cn
All
B
Remaining
A.Cn
Remaining
A.Cn
Function Inputs: S1 =S2=Vee, SO=S3=M=0 V
Other Input
Same Bit
Apply
Vee
Apply
GND
Other Data Inputs
Apply
Vee
Remaining
A
tPHL. tpLH
AI
None
BI
tpHL. tpLH
BI
AI
None
Remaining
A
tpHL. tpLH
AI
None
BI
None'
tpHL. tpLH
BI
AI
None
None
tpHL. tpLH
AI
BI
None
None
tpHL. tpLH
BI
None
AI
None
tpHL. tpLH
AI
None
BI
Remaining
A
tpHL. tpLH
BI
AI
None
Remaining
A
tpHL. tpLH
Cn
None
None
All
AandB
tpHL. tpLH
AI
BI
None
None
tpHL. tpLH
BI
None
AI
None
3-164
Apply
GND
Remaining
B.Cn
Remaining
B.Cn
Remaining
A and B. Cn
Remaining
A and B.Cn
Remaining
A and B.Cn
Remaining
A and B,Cn
Remaining
B.Cn
Remaining
B.Cn
None
Remaining
A.B,Cn
Remaining'
A.B,Cn
"
s:::
s:::
en
Logic Diagram
.s:.
::J:
53 131
14)
:!
52 (5)
IS)
JC~~-----------GMY
117)
....oC»
....
......
s:::
s:::
......
.s:.
::J:
i~,~.::1)f-<::D-f-l-+H~
o....
L.b~~L)C>----------------i1Si
115) P or X
:>--t-------;r~_--F3
1'31
8~'_~0::4)-D-I++-14-4
8'-1-D-I++-14-+
I")
li, -------++-1-1...-1
1.3)
19) FO
Vee
~~17~)------------------------------------------~
GND
= PIN 24
= PIN 12
TUF/S320-4
3-165
C»
....
~National
PRELIMiNARY
~ Semiconductor
\
)
microCMOS
MM54HC182/MM74HC182
Look-Ahead Carry Generator
General Description
The MM54HC182/MM74HC182 is a high speed LOOKAHEAD CARRY GENERATOR utilize microCMOS Technology, 3.5 micron silicon gate P-well CMOS. It has the low
power consumption and high noise immunity of standard
CMOS integrated circuits, along with the ability to drive 10
LS-TTL loads.
These circuits are capable of anticipating a carry across four
binary .adders or groups of adders. They are cascadable to
perform full look-ahead across n-bit adders. Carry, generate-carry, and propagate-carry functions are provided as
shown in the pin designation table.
Carry input and output of the ALU's are in their true form,
and the carry propagate (P) and carry generate (G) are in
negated form; therefore, the carry functions (inputs, outputs,
generate, and propagate) of the look-ahead. generators are
implemented in the compatible forms for direct connection
to the ALU. Reinterpretations of carry functions as explained on the HC181 data sheet are also applicable to and
compatible with the look-ahead generator.
Features
" • TTL pinout compatible
When used in conjunction with the HC181 arithmetic logic
unit, these generators provide high-speed carry look-ahead
capability for any word length. Each HC182 generates the
look-ahead (anticipated carry) across a group of four ALU's
and, in addition, other carry look:ahead circuits may be employed to anticipate carry across sections of four lookahead packages up to n-bits. "f.!1e method of cascading circuits to perform multi-level look-ahead is illustrated under
typical application data.
.
•
•
•
•
Typical propagation delay: 18 ns (clock to 0)
Wide operating supply voltage range: 2-6V
Low input current: < 1 /LA
Low quiescent supply current: 80 /LA maximum (74HC
Series)
• Fanout of 10 LS-TTL loads
Connection Diagram
Dual·ln·Une Package
INPUTS
.
,
VCC
P2
15
/16
G2
, •
C
n
14
OUTPUTS
+
Cn x
13
12
Cn +y
11
G
,9
-
1
,
Cn+z
10
-c
G1
,
.
2
P1
3
GO
4
.
PO
5
G3-
6
P3
7
Is
ji
GND
' OUTPUT
INPUTS
TUFf5321-1
Top View
Order Number MM54HC182J or MM74HC182J, N
See NS Package J16A or N16E
3-166
~,:
Absolute Maximum Ratings (Noles 1 & 2)
Operating Conditions
Supply Vollage (Vecl
DC Inpul Voltage (VIN)
DC Outpul Voltage (VOUT)
Clamp Diode Currenl (11K, 10K)
DC OUlput Currenl, per pin (lOUT)
DC Vee or GND Current, per pin (Ieel
Slorage Temperalure Range (TSTG)
Power Dissipation (Po) (Nole 3)
Lead Temperalure
(TLl (Soldering 10 seconds)
Supply Voltage (Vee)
DC Input or Oulpul Voltage
(VIN, VOUT)
Operating Temp. Range (TAl
MM74HC
MM54HC
Inpul Rise or Fall Times
(Ir,lf)
Vee=2.0V
Vee=4.5V
Vee = 6.0V
-0.510 + 7.0V
-1.510Vee+ 1.5V
-0.510 Vee+0.5V
±20mA
±25mA
±50mA
- 65'C to + 150'C
500mW
260'C
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
'c
'c
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Nole 4)
Symbol
Parameter
Conditions
TA=25'C
Vee
74HC
TA=-40t085"C
Typ
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Vollage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Outpul Voltage
VIN = VIH or VIL
IIOUTI~20 p.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
IIOUTI~4.0 mA
IIOUTI~5.2 mA
4.5V
6.0V
0.2
0.2
'0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VeeorGND
6.0V
±0.1
±1.0
±1.0
p.A
VIN=VIH orVIL
IIOU'fI~4.0 mA
IIOUTI ~ 5.2 mA
VOL
liN
Maximum LoIN Level
Outpul Voltage
Maximum Inpul
Current
VIN = VIH or VIL
IIOUTI~20 p.A
Maximum Quiescenl VIN=VeeorGND 6.0V
80
160
8.0
/LA
Supply Currenl
IOUT=O p.A
Note 1: Absolute Maximum Ratings are 1hosa values beyond which damage to 1he device may occur.
Note 2: UnlesS otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: - t 2 mWI"C from 6S'C to 8S'C; ceramic "J" package: -12 mW/'C from 100'C to 12S'C.
Note 4: For a power supply of SV ±10% 1he worst case output voltages (YOH. and VoLl occur for HC at 4.SV. Thus the 4.SV values shouid be used when
designing with 1his supply. Worst case VIH and VIL occur at Vcc= S.SV and 4.SV respectively. (The VIH value at S.SV is 3.8SV.) The worst casa leakage current (lIN.
Icc. and 10V occur for CMOS at 1he higher voltage and so the 6.0V values should be usad.
lee
AC Electrical Characteristics Vce= 5V, TA= 25'C, CL = 15 pF, Ir=tf= 6 ns
Symbol
'.
Guaranteed Limit
Units
IpHL,lpLH
Maximum Propagation Delay· Pn 10 P
16
24
ns
IPHL,lpLH
Maximum Propagation Delay· Cn 10 any output
18
27
ns
tpHL,IpLH
Maximum Propagation Delay· Pn or Gn to any OUlpul
23
35
ns
Paranieter
Conditions
3·167
Typ'
AC Electrical Characteristics Vee = 2.0V to 6.0V, CL = 50 pF, tr= t,=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25"C
Vee
74HC
TA=-40t085°C
Typ
54HC
TA= -55 to 125"C
Units
Guaranteed Limits
tpHL, tpLH
Maximum Propagation
Delay
PntoP
2.0V
4.5V
6.0V
45
18
15
112
28
22
140
35
27
162
40
32
ns
ns
ns
tpHL, tpLH
Maximum Propagation
Delay
Cn to any output
2.0V
4.5V
6.0V
50
20
16
125
30
24
156
37
30
182
44
35
ns
ns
ns
tpHL, tpLH
Maximum Propagation
Delay
Pn or Gn to any output
2.0V
4.5V
6.0V
62
25
22
155
37
33
194
46
42
225
54
48
ns
ns
ns
trLH, trHL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
25
75
15
13
95
19
16
110
22
19
ns
ns
ns
7
6
Power Dissipation Capacitance
CPO
150
pF
10
10
10
pF
5
Maximum Input Capacitance
NO~ 5: CPO determines the no load dynamic power consumption. Po= Cpo Vcc2 1+ lee Vee. and the no load dynamic current consumption, Is= Cpo Vee 1+ leo
CIN
Logic Equations
Cn+x=YO (XO+Cn)
C n + y =Y1 [X1+YO (xo+cn)l
Cn+x=GO+PO Cn
Cn + y=G1 +P1 GO+P1 PO Cn
Cn + z =G2+P2Gl+P2P1 POCn
or
Cn + z =Y2 tX2+Y1 [X1 +YO (XO+ CnUI
~=G3+P3 G2+P3 P2 G1 +P3 P2 P1 GO
Y=Y3 (X3+Y2) (X3+X2+Y1) (X3+><.2+X1 + YO)
P=P3 P2 P1 PO
X=X3+X2+X1 +XO
FUNCTION TABLE
FOR P OUTPUT
FUNCTION TABLE FOR G OUTPUT
INPUTS
OUTPUT
INPUTS
OUTPUT
P2
P1
G
P3 P2 P1 PO
is
GO
X
X
X
X
X
L
X
X
X
L
X
L
X
L
L
X
X
L
L
L
All other combinations
X
X
X
L
L
L
L
L
L
X
X
L
H
All other
combinations
G3 G2 G1
L
X
X
X
FUNCTION TABLE
FOR Cn + x OUTPUT
INPUTS
OUTPUT
GO P3
L
L L L
All other
combinations
H
INPUTS
L
X
X
X
G1
GO
P2
Cn
H
FUNCTION TABLE
FOR C n + y OUTPUT
FUNCTION TABLE FOR Cn + z OUTPUT
G2
PO
L
X
P1
OUTPUT
PO
X
X
X
X . X
X
L
L
X
X
X
L
L
L
X
X
X
L
L
L
All other combinations
INPUTS
Cn
Cn + z
G1
X
X
X
H
.H
H
H
L
X
X
H
L
H= high level
L=low level
X= Irrelevant
Any Inputs not shown in a given table are Irrelevant with respect to that output.
3-168
GO P1
OUTPUT
PO Cn
Cn+ y
X
X X
X
L
L
X
X
X
L
L
H
All other
combinations
HH
H
L
Cn + x
H
H
L
iii:
i:
Logic Diagram
en
01:00
P
X
0
....
co
~
......
iii:
i:
......
01:00
X
0
....
ii
co
P3
~
ii3
Cn+ z
-c>c>--,
JIl ....Oo-.....
iI1 ....0o---c~.,
Pii ....Oo-.....-c»...,
_
..
.~_
·Cn+ x
oo ..~~~----~~~--------------------..-----+~__~
~ ~~----------------------------------~
Tl/F/5321-2
Typical Application
64-BIT ALU, FULL· CARRY LOOK AHEAD IN THREE LEVELS
181
A and B Inpula, and F outputs of 181 are not shown.
TLlF/5321-3
3-169
r: \
.r-------~----------------------------------------------------------------------~
en
.o
:::E:
~
:e
:e
.....
.en
.o
:::E:
;z
:e
:e
i.o
.....
...
:::E:
:e
:e
c;
en
.o
...
:::E:
II)
:e
:e
~ National
PRELIMINARY
~ Semiconductor
MM54HC190/MM74HC190 Synchronous
Decade Up/Down Counters with Mode,
Control MM54HC191/MM74HC191
Synchronous Binary Up/Down Counters
with Mode Control
~
.-
microCMOS
General Description
These high speed synchronous counters utilize microCMOS Technology, 3.0 micron silicon gate N-well CMOS.
They possess the high noise immunity and low power consumption of CMOS technology, along with the speeds of
low power Schottky TTL.
These circuits are synchronous, reversible, up/down counters. The MM54HC191/MM74HC191 are 4-bit binary counters and the MM54HC190/MM74HC190 are BCD counters .
Synchronous operation is provided by having all flip-flops
clocked simultaneously, so that the outputs change simultaneously when so instructed by the steering logiC. This mode
of operation eliminates the output cbunting spikes normally
associated with asynchronous (ripple clock) counters.
The outputs of the four master-slave flip-flops are triggered
on a low-to-high level transition of the clock input, if the
enable input is low. A high at the enable input inhibits Counting. The direction of the count is determined by the level of
the down/up input. When low, the counter counts up and
when high, it counts down.
These counters are fully programmable; thaf is, the outputs
may be preset to either level by placing a low on the load
input and entering the desired data at the data inputs. The
output will change independent of the level of the clock input. This feature allows the counters to be used as modulo-
N dividers by simply modifying the count length with the
preset inputs.
Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum count.
The latter output produces a high-level output pulse with a
duration approximately equal to one complete cycle of the
clock when the counter overflows or underflows. The ripple
clock output produces a jow-Ievel output pulse equal in
width to the lOW-level portion of the clock input when an
overflow or underflow condition exists; The counters can be
easily cascaded by feeding the ripple clock output to the
enable input of the succeeding counter if parallel clocking is
used, or to the clock input if parallel enabling is used. The
maximum/minimum count output can be used to accomplish look-ahead for high-speed operation.
Features
• Level changes on Enable or Down/Up can be made regardless of the level of the clock input
• Wide power supply range: 2-6V
• Low quiescent supply current: 80 fJ-A maximum
(74HC Series)
• Low input current: 1 p.A maximum
.Connection Diagram
Dual-In-Llne Package
RIPPLE
CLOCK
OATA
CLOCK
LIIAD
C
Load
H
H
L
H
Enable
G
Downl
Up
Clock
Function
L
.L
L
H
t
t
X
X
H
.x
X
X
Count Up
CountDown
Load
NO· Change
Asynchronous Inputs Low input to losd sets OA = A,
as = B,ac = c,andOo = 0
Order Number MM54HC190J, MM54HC191J,
MM74HC19OJ, N or MfJ)74HC191J, N
See NS Package J16A or N16E
S
OArA
B
ENABLE
a
DOWNI
UP
TLlF/5322-1
Top View
3-170
Absolute Maximum Ratings
i!!:
i!!:
Operating Conditions
(Notes 1 & 2)
-0.5 to + 7.0V
Supply Voltage (Vee>
DC Inpu~ Voltage (VIN)
-1.5 to Vee + 1.5V
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
±20mA
Clamp Diode Current (11K, 10K)
±25mA
DC Output Current, per pin (lOUT)
±50mA
DC Vee or GND Current, per pin (Ice>
Storage Temperature Range (TSTG)
- 65'C to + 150'C
Power Dissipation (Po) (Note 3)
500mW
Lead Temp. (TO (Soldering 10 seconds)
260'C
Supply Voltage (Vee>
Dc: Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
(lr,ttl
Vee=2.0V
Vee = 4.5V
Vee=6.0V
en
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
0l:Io
%
....
CD
(')
.....
C)
i!!:
i!!:
......
0l:Io
%
....
CD
(')
.....
C)
i!!:
i!!:
en
0l:Io
DC
Electri~al
Symbol
%
Characteristics (Note 4)
Parameter
Conditions
Vee
TA=25'C
Typ
74HC
TA= -40 to 85'C
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
IIOUTI';;20 p.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
·6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
IIOUTI';;4.0mA .
IIOUTI';;5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VecorGND
6.0V
±0.1
±1.0
±1.0
p.A
VIN = VIH or VIL
IIOUTI';;4.0 mA
IIOUTI ,;; 5.2 mA
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
VIN = VIH or VIL
IIOUTI';;20 p.A
Maximum Quiescent VIN=VccorGND
6.0V
8.0
80
160
p.A
Supply Current
IOUT=Op.A
Nota 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Nota 2: Unless otherwise specified all voltages are referenced to ground.
Nota 3: Power DiSSipation temperature derating - plastic "N" package: -12 mWI'C from 6S'C to 8S'C; ceramic "J" package: -12 mWI'C !rom 100'C to 12S'C.
Nota 4: For a power supply of SV ± 10% the worst case output voltages (VOH. and VoLl occur for HC at 4.SV. Thus the 4.SV values should be used when designing
with this supply. Worst case VIH and VIL occur at VCC= S.SV and 4.SV respectively. (The VIH value at S:SV is 3.8SV.) The worst case leakage current (liN. Icc. and
lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
Icc
3-171
i!!:
i!!:
......
Minimum High Level
Input Voltage
VIH
....
CD
....
.....
(')
0l:Io
%
....
CD
....
(')
,
.....
.....
G)
0
..,.
....
AC Electrical Characteristics TA = 25°C. Vee= 5.0V. t,= tf= 6 ns. CL = 15 pF (unless otherwise specified)
:::E:
::i!i
::i!i
......
Symbol
From
(Input)
Parameter
To
(Output)
Typ
Guaranteed
;\
Limit
Units
40
MHz
QA.QS
Qe.Qo
30
ns
DataA.
B.C.D
QA.QS
Qe.Qo
27
ns
Maximum Propagation Delay Time
Clock
Ripple
Clock
16
ns
tpLH. tpHL
Maximum Propagation Delay Time
Clock
24
ns
::i!i
::i!i
......
QA.QS
Qe.Qo
tpLH. tpHL
Maximum Propagation Delay Time
Clock
Max/Min
30
ns
G)
tpLH. tpHL
Maximum Propagation Delay Time
Down/Up
Ripple
Clock
29
ns
tpLH. tpHL
Maximum Propagation Delay Time
Down/Up
Max/Min
22
ns
tpHL. tpLH
Maximum Propagation Delay Time
Enable
Ripple Clock
22
ns
tw
Minimum Clock. Clear or Load
Input Pulse Width
10
ns
ts
Minimum Setup Time
.....
fMAX
Maximum Clock
Frequency
0
tpLH. tpHL
Maximum Propagation Delay Time
Load
tpLH. tpHL
Maximum Propagation Delay Time
tpLH. tpHL
:::E:
G)
.....
..,.
:::E:
Lt)
::i!i
::i!i
......
0
G)
.....
/
Conditions
0
..,.
....
0
.....
0
..,.
:::E:
Lt)
::i!i
::i!i
Data
Clock
ns
tH
Minimum Hold Time
Clock
Data
ns
Is
Minimum Setup Time
Down/Up
Clock
ns
tH
Minimum Hold Time
Clock
Down/Up
ns
ts
Minimum Setup Time
Enable
Clock
ns
tH
Minimum Hold Time
Clock
Enable
ns
ts
Minimum Setup Time
Load Inactive to Clock
~
ns
,
AC Electrical Characteristics
Symbol
Parameter
Vee = 2.0V to 6.0V. CL =50 pF. t,=tf=6 ns (unless otherwise specified)
From
To
Conditions
(Input) (Output)
Vee
TA=25°C
Typ
Guaranteed Limits
2.0V
4.5V
6.0V
10
38
40
MHz
MHz
MHz
QA.QS
Qe.Qo
2.0V
4.5V
6.0V
106
32
29
ns
ns
ns
tpLH. tpHL Maximum Propagation DataA.
Delay Time
B.C.D
QA.QS
Qe.Qo
2.0V
4.5V
6.0V
93
28
25
ns
ns
ns
tpLH. tpHL Maximum Propagation
Delay Time
Ripple
Clock
2.0V
4.5V
6.0V
62
18
16
ns
ns
ns
2.0V
4.5V
6.0V
90
27
24
fMAX
Maximum Clock
Frequency
74HC
54HC
TA = -40 to 85°C TA = -55 to 125°C Units
tpLH. tpHL Maximum Propagation
Delay Time
tpLH. tpHL Maximum Propagation
Delay Time
Load
Clock
Clock
QA.QS
Qe.Qo
3-172
I
ns
ns
ns
s::
i:
AC Electrical Characteristics (Continued)
Symbol
Parameter
From
(Input)
To
(Output)
CI"I
74HC
54HC
TA=25"C
CondlDons Vee
TA= -40 to 85"C TA= -55to 125°C Units
Typ
tpLH. tpHL Maximum Propagation
Delay Time
Clock
tpLH. tpHL Maximum Propagation
Delay Time
Down/Up
tpLH,tpHL Maximum Propagation
Delay Time
Down/Up Max/Min
tpHL, tpLH Maximum Propagation
Delay Time
Enable
Max/Min
Ripple
Clock
Ripple
Clock
Minimum Clock. Load or
Clear Input Pulse Width
tw
ts
Minimum Setup Time
tH
Data Hold Time
Clock
t r• tf
Maximum Input Rise and
Fall Time
CIN
Input CapaCitance
CPO
Power Dissipation
Capacitance (Note 5)
2.0V
4.5V
6.0V
98
30
28
ns
ns
ns
......
CD
Q
.,...,
2.0V
4.5V
6.0V
85
25
23
ns
ns
ns
i:
(')
2.0V
4.5V
6.0V
85
25
23
ns
ns
ns
....
s::
ns
ns
ns
~
20
10
8
ns
ns
ns
2.0V
4.5V
6.0V
ns
ns
ns
2.0V
4.5V
6.0V
s
ns
ns
2.0V
4.5V
6.0V
ns
ns
ns
5
10
10
pF
pF
Minimum Setup Time
Down/Up
Clock
2.0V
4.5V
6.0V
ns
ns
ns
Minimum Hold Time
Clock
Down/Up
2.0V
4.5V
6.0V
ns
ns
ns
Minimum Setup Time
Enable
Clock
2.0V
4.5V
6.0Y
ns
ns
ns
Minimum !:laid Time
CI9Ck
Enable
2.0V
4.5V
6.0V
ns
ns
ns
Minimum Setup Time
(Inactive)
Load
Clock
Note 5: CpO determines the no load dynamic power consumption, Po =
2.0V
4.5V
6.0V
Cpo Va;2 f + lee Vee. and the no load dynamic current consumption. Is - Cpo Vee f
3-173
CD
....s::
ns
ns
ns
100
100
......
2.0V 108
4.5V 33
6.0V 30
2.0V
4.5V
6.0V
trHL. tTLH Maximum Output
Rise and Fall Time
(')
Q
Guaranteed Limits
2.0V
4.5V
6.0V
Data
"""
%
ns
ns
ns
+
i:
......
"""
%
(')
s::
CI"I
"""
%
......
CD
......
s::
%
(')
......
CD
......
--....
-r-----------------------------------------~
G)
o
.....
::c
"'II'
::E
::E
Logic Diagrams
'HC190 Decade Counters
CLO
CK
114)
G)
o
::c
:;
::IE
::E
-
i
o
ENABLE o~
15)
.....
DOWN! UP
::c
~
::E
::E
i
-
~"l
.
~
-L
{>o....
.....
-
113)
~
112)
1
.-
~U
OAlA (15)
;-
~
INPUT A
OATA 11)
INPUT
•
kah
L
}-
CK
CL
~~
L
II ....
....
"'II'
o
4>
II)
[I
MAXIMIN
.
OUTPUT
I
~
o
::c
RIPPLE CLOCK
Q
CK
CL
~
•
OUTPUT
Qa
J) ~
')0-1
-........
OAtA (10)
INPUT C
I
L
.....
....
~>-
.....
1[>--:1
-:J
~
r---
~
_
....
.....
,
~~:
UTPUT
CK
CL
)-.-J
~r)
Pin (16)
lie:
I
.....
111)
OUTPUT
I
~
LOAD
CK
CL
)-.-J
.........
DATA 19)
INPUT 0
-- ~
~
TL/F/5322-2
= Vee. Pin (8) = GND
3·174
3:
3:
Logic Diagrams (Continued)
U1
oIloo
::I:
....
CD
0
'HC191 Binary Counters
CLOCK
ENABLE G
DOWN/UP
0
......
(14)
~
~
(5)
~
~~
:::Jr-
~
-
3:
3:
1
""
(")
....
oIloo
::I:
CD
0
......
.
.,J
~:
---
DATA (15)
INPUT A
--=
3:
3:
U1
(13)
.r
RIPPLE CLOCK
(12)
I
MAX/MIN
L *rh
0
~ ~CK
--
DATA (1)
INPUT B
~
I
,.
DATA (10)
INPUT C
:::::::J"'..r
. +-J
~
DATA (9)
INPUT D
I
Ir'
'-
~rh
0 0
"-
OUTPUT
Qc
-- +
1
I
J
--:f'
OUTPUT
Qs
+
D Q
-
QA
I> CK
~~CK
---'1
J. ./
I-
1D- 7~
-
OUTPUT
I
I
1
oIloo
I
s~
JD
,f)--I- 7~
.-
D Q
.... I>CK
(7)
OUTPUT
QD
+
:=::r-.J.
-
(11)
LOAD
TL/F/5322-3
Pin (16) ~ Vee. Pin (8) ~ GND
3-175
""
0
....
....
::I:
-+
~
....0CD
....
......
3:
3:
I
o
oIloo
::I:
CD
~ r-----------------------------------------------------~--~------------------------------------.
0)
~
o
..,......
Timing Diagrams
'--
:::t:
:::E
:::E
.......
'HC190 Synchronous Decade Counters
Typical Load, Count, and Inhibit Sequences
LOAD~r------------------------------
~
,0)
~
o
:::t:
..,.
an
:::E
:::E
.......
o
DATA
INPUTS
1:
:
CLOCK
0)
~
o
:::t:
..,.
.....
DOWN/UP
ENABLE
:::E
:::E
.......
o
0)
~
o
..,.an
:::t:
:::E
:::E
- --'1 7 1 8~==t==:j:t=...,
90122210987
RIPPLE CLOCK - _;...1-H-----,
!JI---COUNT UP--IINHIBIT
I
I---COUNT DOWN--I
LOAD
TLlF/5322-4
Sequence:
(1) Load (preset) to BCD seven
(2) Count up to eight, nine, zero, one and two
(3) Inhibit
(4) Count down to one, zero, nine, eigh~ and seven
'HC191 Synchronous Binary Counters
Typical Load, Count, and Inhibit Sequence
LOAD~-------------------------------
DATA
INPUTS
I:
:
CLOCK
DOWN/UP
ENABLE
RIPPLE CLOCK - _;...1-+1--,
- --'113
14 15
0
1 2
2
!JI-COUNT UP--liNffiaiTl
LOAD
2
1
0
15 14
13
I---COUNT DOWN--I
TL/F/5322-5
Sequence:
(1) Load (preset) to binary thirteen
(2) Count up to fourteen, fifteen, zero; one, and two
(3) Inhibrt
(4) Count down to one, ze,o, fifteen, fourteen, and thirteen
3·176
3:
'?"A National
~ Semiconductor
U1
microCMOS
MM54HC192/MM74HC192
Synchronous Decade Up/Down Counters
MM54HC193/MM74HC193
Synchronous Binary Up/Down Counters
3:
:r:
o
....
CD
~
3:
3:
General Description
These counters may be preset by entering the desired data
on the DATA A, DATA B, DATA C, and DATA D inputs.
When the LOAD input is taken low the data is loaded independently of either clock input. This feature allows the counters to be used as divide-by-n counters by modifying the
count length with the preset inputs.
• Typical propagation delay,
Count up to Q: 28 ns
• Typical operating frequency: 27 MHz
• Wide power supply range: 2-6V
• Low quiescent supply current: 80 ",A maximum
(74HC Series)
• Low input current: 1 ",A maximum
• 4 mA output drive
In addition both counters can also be cleared. This is accomplished by inputting a high on the CLEAR input. All 4
internal stages are set to a low level independently of either
COUNT input.
Connection Diagram
All inputs are protected from damage due to static discharge by diodes to Vee and ground.
Features
Truth Table
Count
Dual·ln·Llne Package
DATA
DATA
C
A
o
Up
Down
t
H
H
t
X
X
X
X
Clear
Load
Function
L
L
H
L
H
H
Count Up
CountDown
Clear
Load
H = high level
L
t
= low level
= transition from low·to·high
X = don't care
C..
COUNT
COUNT
DOWN
UP
.,..
U1
Both a BORROW and CARRY output are provided to enable cascading of both up and down counting functions. The
BORROW output produces a negative going pulse when the
counter underflows and the CARRY outputs a pulse when
the counter overflows. The counters can be cascaded by
connecting the CARRY and BORROW outputs of one device to the COUNT UP and COUNT DOWN inputs, respectively, of the next device.
B
J\)
......
3:
......
.,..
These high speed synchronous counters utilize microCMOS Technology, 3.5 micron silicon gate P-well CMOS, to
achieve the high noise immunity and low power consumption of CMOS technology, along with the speeds of low
power Schottky TTL. The MM54HC192/MM74HC192 is a
decade counter, and the MM54HC193/MM74HC193 is a
binary counter. Both counters have two separate clock inputs, an UP COUNT input and a DOWN COUNT input. All
outputs of the flip-flops are simultaneously triggered on the
low to high transition of either clock while the other input is
held high. The direction of counting is determined by which
input is clocked.
DATA
3:
.,...
:r:
o
....
CD
ac
Do
GND
TL/F/5011-1
Order Number MM54HC192J, MM54HC193J,
MM74HC192J, N, or MM74HC193J, N
See NS Package J16A or N16E
3-177
X
L
:r:
o....
CD
Co)
......
3:
3:
......
.,..
:r:
o....
CD
Co)
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
Supply Voltage (Vee)
-0.5 to +7.0V
DC Inpu1 Voltage (VIN)
-1.5 to Vee + 1.5V
DC Outpu1 Voltage (VOUT)
-0.5 to Vee + 0.5V
±20mA
Clamp Diode Current (11K. 10K>
±25mA
DC Output Current. per pin (lOUT)
±50mA
pC Vee or GND Current. per pin (lee)
Storage Temperature Range (T8TG)
-65'Cto + 150'C
Power Dissipation (Po) (Note 3)
500mW
Lead Temp.
(Soldering 10 seconds)
260'C
Supply Voltage (Vee>
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (Till
MM74HC
MM54HC
Input Rise or Fall TImes
(tr. ttl Vee=2V
Vee=4.5V
Vee=6.0V
(Tu
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
'ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Conditions
Parameter
'(cc
TA=25'C
Typ
74HC
TA=-40t085'C
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
VIH
Minimum High Level
,Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Inpu1 Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0:3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN=VIH orVIL
IiOUTI:S:20 poA
I
VOL
liN
Maximum Low Level
Outpu1 Voltage
Maximum Input
Current
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
$.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
'v
VIN=VIH orVIL
IIOUTI :s: 4.0 mA
Ilou'rI:S:5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VeeorGND
6.0V
±0.1
±1.0
±1.0
poA
VIN=VIHorVIL
IIOUTI:S:4.0 mA
IIOUTI :s: 5.2 mA
VIN = VIH or VIL
IIOUTI :s: 20 p.A
Maximum Quiescent VIN=VeeorGND 6.0V
8.0
80
160
poA
Supply Current
IOUT=O poA
Note 1: Absolute Maximum Ratings are 1hose values beyond which damage to 1he device may oocur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature dereting - plastic "N" package: -12 mW/'C from 65"C to 8S'C; ceramic "J" package: -12 mWI'C from 100'Cto 125"C.
Note 4: For a power supply of sv ± 10% the worst case output voHages (YOH. and VoLl occur for HC at4.SV. Thus the 4.SV values should be used when designing
with 1his supply. Worst case VIH and VIL oocur at Vcc= S.SV and 4.SV respectively. (The VIH value atS.SV is 3.8SV.l The worst case leakage current (liN. Icc. and
lozl occur for CMOS at the higher voltage and so 1he 6.0V values should be used.
lee
I
• 3-178
AC Electrical Characteristics TA=25°C, Vee =
Symbol
fMAX
tpLH
Typ
Guaranteed
Limit
Count Up
27
20
MHz
CountDown
31
24
MHz
17
26
ns
18
24
ns
16
24
ns
15
24
ns
28
40
ns
36
52
ns
30
42
ns
40
55
ns
35
47
ns
Parameter
Conditions
Maximum Clock Frequency
Maximum Propagation Delay
Low to High
tpHL
Maximum Propagation Delay
High to Low
tpLH
Maximum' Propagation Delay
Low to High
tpHL
Maximum Propagation Delay
High to Low
tpLH
Maximum Propagation Delay
Low to High
tpHL
Maximum Propagation Delay
High to Low
tpLH
Maximum Propagation Delay
Low to High
tpHL
Maximum Propagation Delay
,High to Low
tpHL
Maximum Propagation Delay
High to Low
tw
Minimum Pulse Width
tso
Minimum Setup time
tHO
Minimum Hold TIme
5.0V, tr =t,=6 ns, CL = 15 pF (unless otherwise specified)
Count Up to Carry
Count Down to
Borrow
1
CountUpOr
Down toO
Data or
Load to
0
Clear to 0
Clear
'HC192
'HC193
40
20
52
26
ns
ns
Load
'HC192
'HC193
40
10
52
20
ns
ns
' 15
22
ns
10
20
ns
-3
0
ns
10
ns
Count Up/Down
tREM
Data to Load
Clear Inactive
to Clock
Minimum Removal Time
AC Electrical Characteristics Vee =
Symbol
Parameter
Conditions
2.0V to 6.0V, CL = 50 pF, tr =t,=6 ns
Vee
TA=2SOC
Typ
fMAX
tpLH
tpHL
Units
74HC
54HC
TA=-40t08SOC TA= -55to 12SOC Units
Guaranteed LImits
Count Up
2.0V
4.5V
6.0V
5
25
29
3
18
20
2.5
14
16
2
12
13
MHz
MHz
MHz
CountDown
2.0V
4.5V
6.0V
5
27
31
4
20
23
3
16
18
2
11
12
MHz
MHz
MHz
2.0V
4.5V
6.0V
30
13
11
140
28
24
175
35
30
210
42
36
ns
ns
ns
2.0V
4.5V
6.0V
39
16
14
130
26
22
163
33
28
195
39
33
. ns
ns
ns
Maximum Clock Frequency
Maximum Propagation Delay
Low to High
Count Up
Maximum Propagation Delay to Carry
High to Low
3-179
AC Electrical Characteristics (Continued) Vee =
Symbol
Parameter
Conditions
2.0V to 6.0V, CL = 50 pF, tr=tf= 6 ns
Vee
TA=25'C
Typ
tpLH, tpHL Maximum Propagation belay
CountDown
to Borrow
tTLH,1THL Maximum Output Rise
and Fall Time
tpLH
Maximum Propagation Delay
Low to High
tpHL
Maximum Propagation Delay
High to Low
tpLH
Maximum Propagation Delay
Low to High
-
tpHL
Maximum Propagation Delay
High to Low
tpHL
Maximum Propagation Delay
High to Low
Count Up Or
Down to Q
Data or
Load to Q
CleartoQ
Minimum Setup Time
tHD
Minimum Hold Time
tREM
Minimum Removal Time
tr, tf
Maximum Count Up or Down
Input Rise & Fall Time
GIN
Input Capacitance
Gpo
Power Dissipation Capacitance (Note '5)
39
16
14
130
26
22
163
33
28
195
39
33
ns
ns
ns
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
2.0V
4.5V
6.0V
77
35
30
215
43
37
269
54
46
323
65
55
ns
ns
ns
2.0V
4.5V
6.0V
95
45
38
275
55
47
344
69
59
413
83
71
ns
ns
ns
2.0V
4.5V
6.0V
85
37
30
230
46
39
288
58
49
345
69
59
ns
ns
ns
2.0V
4.5V
6.0V
102
47
39
290
58
49
363
73
61
435
87
74
ns
ns
ns
2.0V
4.5V
6.0V
85
42
38
265
53
45
331
66
56
398
80
68
ns
ns
ns
2.0V
'HC192 4.5V
6.0V
119
42
38
260
52
45
325
65
56
390
78
68
ns
ns
ns
Load
2.0V
'HC193 4.5V
6.0V
31
10
9
100
20
17
125
25
21
150
30
,26
ns
ns
ns
2.0V
Count Up/Down 4.5V
6.0V
43
17
15
110
22
19
138
28
24
165
33
29
ns
ns
ns
2.0V
'HC193 4.5V
6.0V
70
21
19
130
26
22
163
33
28
195
39
33
ns
ns
ns
2.0V
4.5V
6.0V
30
10
9
100
20
17
125
25
22
150
30
25
ns
ns
ns
2.0V -30
4.5V -3
6.0V -3
0
0
0
0
0
,0
0
0
0
ns
ns
ns
2.0V -20
4.5V -3
6.0V -2
10
10
10
10
10
10
10
10
10
ns
' ns
ns
500
300
200
500
300
200
500
300
200
ns
ns
ns
10
10
10
pF
Clear
Iso
Guaranteed Limits
2.0V
4.5V
6.0V
Clear
or
Load
Minimum Pulse Width
tw
74HC
54HC
TA= -40 to 85'CTA= -55 to 125'C Unlta
Data
To
Load
Clear Inactive
to Clock
2.0V
4.5V
6.0V
5
100
pF
Note 6: CpO determines the no load dynamic power consumption, Po = Cpo Vcc2l+ Icc Vee. and the no load dynamic current consumption, Is = Cpo Vcc 1+ Icc.
3-180
...en====
Logic Diagrams
:::z::
Q
'"
0
....
CD
N
....
l!;
Q
........====
:::z::
....
::>
...
ON
....0
~
N
....
~
CD
u
...====
en
:::z::
0
....
CD
W
....
.
==
.....
==
...
u
~:::I
'"
(,)
GI
u
:::z::
0
....
~
0
CD
W
l!;
'1:1
III
0
GI
0
C
0
==
•
....0a.
-~
:::)
fIJ
:::I
0
C
e
.
.c
0
c
'"
'"...
l
~
N
(,)
:t
'It'
1ft
::!!
::!!
,
~
:e
0-1'>0----------1
L..::j---+t-t+---,
o
z
'"
.
"'0.
... Z
8
88
Z j ~I:
3-181
a::
c....
w
u
o
c
9
:it"
tl
>
MM54HCt921MM74HC192/MM54HC193/MM7 4HC193
ro
CO
n'
o
,
ii'
G
MM54HC193 Synchronous 4-Bit Up/DownBinary Counter
'AIN
QA
S,N
Os
C'N
Oc
10
15
06
""I
I»
CARRVOUT
12
DIN
00
l'
~
c:
:J
~
~
OA
ro
CiA
co
COU~:~
11'1-
I'
4
COUNT 0
DOWN 14
ClEAR~
I
~ ~BORROW
'------'-"-
11
.... -
- OUT
lOAO~
16
vee
Q
o---J
8
~GNO
TUF/5011-3
Logic Waveforms
'HC192 Synchronolls Decade Counters
Typical Clear, Load, and Count Sequences
CLEAR
--1l~
LOAD
A:D
DATA
____________________
.-++--+....;-------------------
-+-!---+-!:-- ------ -- -- -- -- --- -- -- -- -- -rHl--lr-; - --
r++-+...;'~----------------------------- - - - -- --
{
~-----------------
~-----------------
COUNT
UP
COUNT
DOWN
OUTPUTS { : :
Qc
-------------------
-++--H-..,
-++--H-+---------1--,
~
-:
I
QD :
_y_++--+.J
CARRY
BORROW
101
1•
I"
~-
r---"-;
CLEAR PRESET
9
0
1
~'COUNTUP
2
1 11
--1
r---
0
9
•
71
COUNT DOWN ~
TL/F/S01'-4
Sequences:
(1) Clear outputs to zero
(2) Load (preset). to BCD seven.
(3) Count up to eight, nine, carry, zero, one and two.
(4) Count down to one, zero, borrow, nine, eight, and seven.
'HC193 Synchronous Binary Counters
Typical Clear, Load, and Count Sequences
C~AR --1l~~--------------------------------~OAD
DATA{
AC:~~------------------------- ----------1
~-----------------
-------------------------------------
r++--t-i - - - - - - - - - - ---,-- - - - -
-++-i-t--,
COUNT -++-i-t--t--------i--,
DOWN
COUNT
UP
: -,
QA -
OUTPUTS
{ QB
Qc
_
1
- -I
aD: _
CARRY
BORROW
10 1 11-1
r-"'---..~
1 14
t---
15
0
1
COUNT UP
'I
---1
CLEAR PRESET
I
r--1
0
15
14
COUNT DOWN
131
-4
TL/F/SO"-S
Sequence:
(I) Clear outputs to zero.
(2) Load (preset) to binary thirteen
(3) Count up to fourteen, fifteen, carry, zero, one, and two.
(4) Count down to one, zero, borrow, fifteen, fourteen, and thirteen.
Note A: Clear overrides load data, and count inputs.
Note B: When counting uP. count-down input must be ~Igh; when counting down, count-up input must be high.
',3-183
~.National
~ Semiconductor
MM54HC194/MM74HC194
4-Bit Bidirectional Universal Shift Register
General Description
This 4-bit high speed bidirectional shift register utilizes
microCMOS Technology, 3.5 micron silicon gate P-well
CMOS, to achieve the low power consumption and high
noise immunity of standard CMOS integrated circuits, along
with the ability to drive 10 LS-TTL loads. This device operates at speeds similar to the equivalent low power Schottky
part.
This bidirectional shift register is designed to incorporate
virtually all of the features a system designer may want In a
shift register. It features parallel inputs, parallel outputs,
right shift and left shift serial inputs, operating mode control
inputs, and a direct overriding clear line. The register has
four distinct modes of operation: PARALLEL .(broadside)
LOAD; SHIFT RIGHT (in the direction QA toward Qo);
SHIFT LEFT; INHIBIT CLOCK (do nothing).
Synchronous parallel loading Is accomplished by applying
the four bits of data and taking both mode control inputs, SO
and S1, high. The data are loaded into their respective flip
flops and appear at the outputs after the positive transition
of the CLOCK input. During loading, serial data flow is inhibited. Shift right is accomplished synchronously with the rising edge of the clock pulse when SO is high and S1 is low.
Connection Diagram
Serial data for this mode is entered at the SHIFT RIGHT
data input. When SO Is low and S1 Is high, data shifts left
synchronously and new data is entered at the SHIFT LEFT
serial input. CloCking of the flip flops Is inhibited when both
mode control Inputs are low. The mode control inputs
should be changed only when the CLOCK input is high. .
The 54HC174HC logic family Is functionally as well as pinout compatible with the standard 54LSI74LS logic family.
All inputs are protected from damage due to static discharge by internal dio~e clamps to Vee and ground.
Features
•
•
•
•
Typical operating frequency: 45 M!"iz
Typical propegation delay: ns (clock to Q)
Wide operating supply vOltage'range: 2-6V
Low input current: 1 p.A maximum
• Low quiescent supply current: 160 pA maximum
(74HC Series)
• Fanout of 10 L5-TTL loads
Dual-In Une Package
Qa
Qc
QD CLOCK SI
114 1,3 1'2 11 Jl0
I I I
Qa
Oc
• SI
CLOCK
SO
A
a
I I I
1 J2' 13 14
CLEAR SHIFT
RIGHT
SERIAL
INPUT
A
a
LEFT
SERIAL
INPUT
PARALLEL INPUTS
TL/F/5323-1
Order Number MM54HC194J or MM74HC194J, N
See N8 Package J16A or N16E
outputs
I
X
L
X
X
X
X
X
X
X
H
L
X
H
L
X
X
X
t
t
tt
t
L
!6 sJ~ o!:
C
Serial
Parallel
Clear 81 82 Clock Left Right ABC 0 QA Qs Qc QD
X X
XX
H H
L H
L H
H L.
H L
L L
...
I
15
~
L
H
H
H
H
H
H
H
D
C
Function Table
Inputs
9
I
00
r: CLEAR
R
so
X
X
XXXX L
L
L
L
XXXXQAOQBOQCOQOO
abcd a b c
d
XXXX H QAnQSnOcn
X X X X L QAn'QSn QCn
X X X X QS n QCn QOn H
XXXXQSnQCnQOn L
XXXXQAOQSOQCOQoo
;3-184
H
= high level (steady state)
L - low leval (steady state)
x = Irrelevant (any Input, Including transitions)
t = transition from low to high laval
a, b. c, d = the level of steaely_te input at Inputs A. S. C. or D.
respectively.
OAl), Oao. Occ. 000 = the level of OAo 0B. Oc. or Go. respectively.
before the indicated _ely_Ie input conditions were established.
OAn. OBn. Oen. Oon = the leval of OAo OB. Oc. respectively. before
the most·recant t transition of the clock.
Absolute Maximum Ratings
Operating Conditions
Supply Voltage (Veel
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K. loKI
DC Output Current. per pin (lOUT)
DC Vee or GND Current. per pin (leel
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
Lead Temperature (TO
(Soldering 10 seconds)
Supply Voltage (Veel
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
Vee=2.0V
(tr. ttl
Vee=4.5V
Vcc=6.0V
(Notes 1 & 2)
-0.5 to + 7.0V
-1.5 to Vcc+ 1.5V
-0.5 to Vee + 0.5V
±20mA
±25mA
±50mA
-65·C to + 150·C
500mW
260·C
Min
2
0
Max
6
Units
V
V
'Vee
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
T:A=25·C·
Typ
74HC
TA=-40t085·C
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
VOH
Minimum High Level
Output Voltage
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
I
,
1.5
3.15
4.2
V
V
V
0.3
0.9
1.2
V
V
V
1.9
4.4
5.9
V
V
V
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34'
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
IIOUTI:::4.0 mA
IIOUTI:::5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VccorGND
6.0V
±0.1
±1.0
±1.0
".A
VIN=VIHorVIL
IIOUTI :::4.0 mA
IIOUTI:::5.2 mA
VOL
Units
Guaranteed Limits
VIH
VIN=VIHorVIL
l!ouTI:::20 /LA
54HC
TA= -55 to 125·C
VIN=VIH orVIL
IIOUTI:::20 /LA
'.
Maximum auies~ent VIN=VceorGND
6.0V
80
160
8.0
/LA
Supply Current
10UT=0/LA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise spacified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mW'·C from 6S·C to 8S·C; ceramic "J" package: -12 mWrc from l00"C to 12~C.
Note 4: For a power supply of SV ± 10% the worst case output voltages (VOH. and VoLl occur for HC at 4.SV. Thus the 4.SV values should be used, when designing
with this supply. Worst cese VIH and VIL occur at Vee = S.SV and 4.SV respectively. (The VIH value at S.SV is 3.8SV.) The worst case leakage current (liN. lee. and
lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
Icc
3-185
AC Electrical Characteristics Vcc= 5V, TA = 25·C, CL = 15 pF, tr= t,= 6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Umlt
Units
fMAX
rJiaximum Operating
Frequency
50
35
MHz
tpHL, tpLH
Maximum Propagation
Delay, Clock to Q
17
24
ns
tpHL
Maximum Propagation
Delay, Reset to Q
19
25
ns
tREM
Minimum Removal Time,
Reset Inactive to Clock
5
ns
ts
Minimum Setup Time
(A, B, C, D to Clock)
20
ns
ts
Minimum Setup Time
Mode Controls to Clock
20
ns
tw
Minimum Pulse Width
Clock or. Reset
9
16
ns
tH
Minimum Hold Time
any Input
-3
0
ns
AC Electrical Characteristics CL =50 pF, tr =t,=6 ns (unless otherwise sp~cified)
Symbol
Par~meter
Conditions
Vee
TA=25"C
74HC
TA=-40to85"C
Typ
54HC
TA=-55to125"C
Units
Guaranteed Limits
Maximum Operating
Frequency
2.0V
4.5V
6.0V
10
45
50
6
30
35
5
24
28
4
20
24
MHz
MHz
tpHL, tpLH
Maximum Propagation
Delay, Clock to Q
2.0V
4.5V
6.0V
145
29
25
183
37
31
216
45
37
ns
ns
ns
tpHL
Maximum Propagation
Delay, Reset to Q
2.0V
4.5V
6.0V
70
15
12
'80
15
12
150
30
26
189
37
31
216
45
37
ns
ns
ns
tTHL, trLH
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
75
15
13
95
19
16
110
22
19
ns
ns
ns
tREM
Minimum Removal Time
Reset Inactive to Clock
2.0V
4.5V
6.0V
5
5
5
5
5
5
5
5
5
ns
ns
ns
ts
Minimum Set Up Time
(A, B, C, or D to Clock)
2.0V
4.5V
6.0V
100
20
17
125
25
21
150
30
25
ns
ns
ns
ts
Minimum Set Time
Mode Controls to Clock
2.0V
4.5V
6.0V
100
20
17
125
25
21
150
30
25
ns
ns
ns
tH
Minimum Hold Time
any Input
2.0V
4.5V
6.0V
-10
"':'3
-3
0
0
0
0
0
0
0
0
0
ns
ns
ns
tw
Minimum Pulse Width
C;:lock or Reset
2.0V
4.5V
6.0V
30
89
8
80
16
14
100
20
18
120
24
20'
ns
ns
ns
tr, t,
Maximum Input Rise and
Fall Time
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
CPO
Power Dissipation
Capacitance (Note 5)
fMAX
8
7
pF
Maximum l'1put
pF
10
5
10
10
Capacitance
Note 5: CPO determines the no losd dynamic power consumption. Po= CPO vcc2 f+ lee Vee. and the no load dynamic current consumption. Is = CpO Vee f+ lco
CIN
,
3-186
Logic and Timing Diagrams'
"".....LUL INPUTS
____,-__ '"
•
~{.:~10~'~~
,.,
•
,OJ
'" __-,
+-____,-______,-__+-____,-______,-__~____~______~~~
~ .Fm~»'---~~-H~+-~~----~~-H~+-~~-----;---H~~~-------+--~-.~,I
....
SltFT
=.::'
"::,.'-----,
H'IIT
r-IH+--~f--!:":!.)'~:-Al
....".
~~.~"~"c>>-------------~--;---r---------~--+-~r---------'---+--i----------J
C~~'"~
__~~--______-----+--4---------____-+--f---__________~__+-____________~
(15)
(14)
1121
(13)
Os
Q.
Qc
00
PARAlLEL OUTPUTS
TUF/5323-2
CLOCK
MODEjso
CONTROL
INPUTS S1
CLEAR
SERlALj R
DATA
INPUTS L
PARALLEL{:
DATA.
INPUTS C
D
OUTPUTS { :
:-+-+--!
aC_
aD
:+-+-----4
-i---INHIBIT
CLEAR LOAD
CLEAR
TL/F/5323-3
3-187
U)
G)
r----------------------------------------------------------------------------,
.....
o
::J: ~National
"" ~ Semiconductor
\
. r-..
:::&
:::&
--;
mi~roCMOS
iii
MM54HC195/MM74HC195
G)
.....
o::J: 4-BitParaliel Shift Register
"":::&
U)
General Description
:::&
The MM54HC195/MM74HC195 is a high speed 4-bit SHIFT
REGISTER utilizes microCMOS Technology, 3.5 micron silicon gate P-well CMOS, to achieve the low power consumption and high noise immunity of standard CMOS integrated
circuits, along with the ability to drive 10 LS-TTL loads at LS
type speeds.
This shift register features parallel inputs, parallel outputs, JK serial inputs, SHIFT/LOAD control input, and a direct
overriding CLEAR. This shift register can operate in two
modes: PARALLEL LOAD; SHIFT from QA towards QD.
Parallel loading is accomplished by applying the four bits of
data, and taking the SHIFT/LOAD control input low. The
data is loaded into the associated flip flops and appears at
the outputs after the positive transition of the -clock input.
During parallel loading, serial data flow is inhibited. Serial
shifting occurs synchronously when the SHIFT ILOAD con-
trol input is high. Serial data for this mode is entered at the
J-K inputs. These inputs allow the first stage to perform as a
J-K or TOGGLE flip flop as shown in the truth table.
The 54HC/74HC logiC family is functionally as well as pinout compatible with the standard 54LS174LS logic family.
All inputs are protected from damage due to static discharge by internal diode clamps to Vcc and ground.
Features
•
•
•
•
•
•
Typical operating frequency: 45 MHz
Typical propagation delay: 16 ns (clock to Q)
Wide operating supply voltage range: 2-6V
Low input current: 1 p.A maximum
Low quiescent current: 80 p.A maximum (74HC Series)
Fanout of 10 LS-TTL loads
Connection Diagram
Dual-In-Une Package
OUTPUTS
r<
SHIFT/
LOAD
CLEAR
J
A
I
I J
1
CLEAR
-
SERIAL INPUTS
B
roo-
D
C
PARALLEL INPUTS
TL/F/5324-1
Top View
Order Number MM54HC195Jor MM74HC195J,N
See NS Package J16A or N16E
Function Table
Inputs
Clear Shlft/ Clock
Load
L
H
H
H
H
H
H
Outputs
Serial
Parallel
QA Qa Qc QD QD
J
K ABCD
L
L
L
H
X X X X X L
X abc d a b c
d
X X X X X QAO QBO Qco QDO
H XXXX QAO QAO QBn QCn QCn
L X X X X L QAn QBn QCn CCn
H X X X X H QAn QBn QCn CCn
L X X X X CAn QAn QBn QCn CCn
X
X
L
H
H
H
H
H
t
L
X
X
X
t
t
t
t
L
L
H
H
a
goo
3-188
H = high level (steady state)
L = low level (steady state)
X = irrelevant (any Input. Including transitions)
t = transition from low to high level
a. b. c. d = the level of steady-state Input at inputs A. B. C.
pr D. respectively.
OAO. aBO. 000. aDO = the level of OA. OB. OC. or aD.
respectively. before the indicated steady-state input conditions were established.
OAn. OB", Ocn = the level of OA. OB. Ce. respectively.
before the most-recent transition of the clock.
a=
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
-0.5 to +7.0V
Supply Voltage (Vee)
DC Input Voltage (VIN)
-1.5toVee+ 1.5V
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
±20mA
Clamp Diode Current (11K, 10K)
±25mA
. DC Output Current, per pin (lOUT)
±50mA
DC Vee or GND Current, per pin (lee)
- 65·C to + 1500C
Storage Temperature Range (T8TG)
Power Dissipation (Po) (Note 3)
500mW
260·C
Lead Temp. (TLl (Soldering 10 seconds)
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
(tr, ttl
Vee=2.0V
Vee=4.5V
Vee=6.0V
Parameter
Conditions
Vee
TA=25"C
Typ
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Level
InputVoltage
VOH
Minimum High Level
Output Voltage
,
VIN=VIH orVIL
!louTI:S:20 p.A
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
• 54HC
TA= -55 to 125·C
CD
Units
Guaranteed Limits
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7·
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
!louTI :S:4.0 rnA
IIOUTI:S:5.2 rnA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VeeorGND
6.0V
±0.1
±1.0
±1.0
p.A
Maximum Quiescent VIN=VeeorGND
6.0V
8.0
160
p.A
80
Supply Current
IOUT=Op.A
Note 1: Absolute Maximum Ratings are those value'; beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Di/lSipation temperature derating - plastiC "'N"' package: -12 mW/'C from 65'C to 85'C; ceramic "'J"' package: -12 mW/'C from 100'C to 125'C.
Note 4: For a power supply of 5V ± 10% the worst case output voltages (YOH. and You occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case V,H and V,L occur at Vcc= 5.5V and 4.5V respectively. (The V,H value at 5.5V is 3.85V.l The worst case leakage current (l,N,
IcC. and lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.'
lee
.1
3-189
UI
UI
2.0
4.5
6.0
VIN=VIHorVIL
IIOUTI:S:20 p.A
....a=
o.....
2.0V
4.5V
6.0V
VIN=VIHorVIL
IIOUTI:S:4.0 rnA
IIOUTI :s: 5.2 rnA
VOL
74HC
TA= -40t085"C
o.....
CD
...:::c.....a=
DC Electrical Characteristics (Note 4)
Symbol
...:::c==
UI
AC Electrical Characteristics Vcc=5V, TA=25°C, CL =15 pF, tr=tf=6 ns
Typ
Guaranteed Limit
Units
fMAX
Maximum Operating Frequency
45
30
MHz
'tpHL, tpLH
Maximum Propagation Delay, Clock to Q
14
24
ns
tpHL
Maximum Propagation Delay, Reset to Q
16
25
ns
tREM
Minimum Removal Time, Shift/Load to Clock
0
ns
Symbol
tREM
Parameter
I
Conditions
Minimum Removal Time, Reset Inactive to Clock
5
ns
20
ns
Minimum Setup Time, Shift/Load to Clock
20
ns
Minimum Pulse Width Clock or Reset
16
ns
Minimum Hold Time, any Input except Shift/Load
0
ns
Is
Minimum Setup Time, (A, B, C, 0, J, K to Clock)
ts
tw
tH
:
AC Electrical Characteristics CL = 50 pF, tr= tf= 6 ns (unless otherwise specified)
Symbol,
Parameter
Conditions
Vee
TA=25°C
Typ
74HC
TA= -40 to 8SOC
54HC
TA= -55 to 125°C
Units
Guaranteed Limits
fMAX
Maximum Operating
Frequency
2.0V
4.5V
6.0V
10
45
50
6)
30
35
5
24
28
4
20
24
MHz
MHz
MHz
tpHL
Maximum Propagation
\i)elay, Reset to Q
2.0V
4.5V
6.0V
70
15
12
150
30
26
189
38
32
224
45
38
ns
ns
ns
tpHL, tpLH
Maximum Propagation
Delay, Clock to Q
2.0V
4.5V
6.0V
70
15
12
145
29
25
183
37
31
216
43
37
ns
ns
ns
tTHL, trLH
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
tREM
Minimum Removal Time,
Shift Load to Clock
2.0V
4.5V
6.0V
-2
-2
-2
0
0
0
0
0
0
0
0
0
ns
ns
ns
tREM
Minimum Removal Time,
Reset Inactive to Clock
2.0V
4.5V
6.0V
5
5
5
5
5
5
5
5
5
ns
ns
ns
Is
Minimum Setuj? Time,
(A, B, C, 0, J, K to Clock)
2.0V
4.5V
6.0V
100
20
17
125
25
21
150
30
25
ns
ns
,ns
Is
Minimum Setup Time,
Shift/Load to Clock
2.0V
4.5V
6.0V
100
20
17
125
25
21
150
30
25
ns
ns
ns
tH
Minimum Hold Time
any Input except Shift/Load
2.0V
4.5V
6.0V
-10
-2
-2
0
0'
0
0
0
0
0
0
0
ns
ns
ns
tw
Minimum Pulse Width,
Clock or Reset
2.0V
4.5V
6.0V
30
10
9
80
16
14
100
20
18
120
24
20
ns
ns
ns
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
,
tr, tf
Maximum Input Rise
and Fall Time
CPO
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input Capacitance
2.0V
4.5V
6.0V
,
100
5
pF
10
Note 5: CPO determines the no load dynamic power consumption, Po ~ Cpo Vcc21+ Icc Vee,
10
10
and the no load dynamic current consumption, Is ~ CPO Vee 1+ Icc.
,
!
3-190
pF
Logic and Timing Diagrams
CLOCK
CLEARo11----~::::::::~::t:=i~+_-J--~_+--JL--+_~~
SHIFT/~
LOAD~
4
A .
OB C
Oc D
TL/F/5324-2
CLOCK
CLEAR
SERIAL
INPUTS
{J
K:::~:::::~~4-~:::::::::::::::::::::;t--;~::::::::::::::::::::
SHIFT I LOAD
PARALLEL{:
DATA
INPUTS
C ____~--------~----------------------~
D---+~----~-----------------------r--~r------------------
OUTPUTJ:~~:
1°C----+I---------+--------~
00:=-+1________+-___________...... ------001
CLEAR
LOAD
TUF/5324-3
3·191
c
....
~~
~National
~ Semiconductor
.J--'
\
)
microCMOS
:E
:E
MM54HC221A/MM74HC221'A
;C
....
N
N
o
Dual Non-Retriggerable Monostable Multivibrator
:::c
;Z General Description
:E
:E
,The MM54174HC221A high speed monostable multivibrators (one shots) utilize microCMOS Technology, 3.5 micron
silicon gate P-well CMOS. They feature speeds comparable
to low power Schottky TIL circuitry while retaining the low
power and high noise immunity characteristic of CMOS circuits.
Each multivibrator features both a negative, A, and a positive, B, transition triggered input, either of which can be
used as an Inhibit input. Also Included is a clear input that
when taken low resets the one shot. The 'HC221A can be
triggered on the pOSitive transition ofthe clear while A is
held low and B is held high.
The 'HC221 A is a non-retriggerable, and therefore cannot
be retriggered until the output pulse times out.
Pulse width stability over a wide range of temperature and
supply is achieved using linear CMOS'techniques. The output pulse equation is simply: PW = (REXT) (CEXT); where PW
Is in seconds, R is in ohms, and C is in farads. All inputs are
protected from damage due to static discharge by diodes to
Vee and ground.
Features
•
•
•
•
•
•
•
•
•
Typical propagation delay: 40 ns
Wide power supply range: 2V -6V
Low quiescent current: 80 /LA maximum (74HC Series)
Low input current: 1 fLA maximum
Fanout of 10 LS-TTL loads
Simple pulse width formula T = RC
Wide pulse range: 400'ns to 00 (typ)
Part to part variation: ± 5% (typ)
Schmitt Trigger A & B inputs enable infinite'signal input
rise or fall times
Connection Diagram
Dual-In-Llne Package
Timing Component
82
10
A2
Vee
9
I I ;
",---!-u"
CLI
D
r 1
U
.r1~.
CLR
Io-TU_ _....
TOCm
TERMINAL
I
TLlF/5325-1
Top View
Order Number MM54HC221AJ or MM74HC221AJ, N
See NS Package J16A or N16E
Truth Table
H
Inputs
Clear
Outputs
- A
B
Q
Q
L
X
X
X
H
X
X
X
L
L·
L
L
H
H
H
H
H
L
J,
t
t
L
Jl..
Jl..
Jl..
-U-U-U-
H
H
=
High Level
L = Low Level
t =
J. =
Transition from Low to High
Transition from High to Low
IL= One High Level Pulse
'1S = One Low Level Pulse
X = Irrelevant
3-192
TOR/Cot
TERMINAL
TL/F/5325-2
Absolute Maximum Ratings
Operating Conditions
(Notes 1 & 2)
-0.5Vto +7.0V
Supply Voltage (Vecl
DC Input Voltage (VIN)
-1.5VtoVee+ 1.5V
DC Output Voltage (Vour)
-0.5VtoVee+ 0.5V
±20mA
Clamp Diode Current (11K. 10Kl
±25mA
DC Output Current. per pin (lour)
±50mA
DC Vee or GND Current. per pin (lee)
- 65·C to + 150·C
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
500mW
Lead Temperature
260·C
(T Ll (Soldering 10 seconds)
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN. Vour)
Operating Temp. Range (TAl
MM74HC
MM54HC
Maximum Input Rise and FaU
Time (Clear Input)
Vee=2.0V
Vee=4.5V
Vee=6.0V -
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25·C
Typ
74HC
TA= -40 to 85"C
54HC
TA= -55to 125·C
Units
Guaranteed Umlts
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
Ilourl:S:20 p,A
VIN=VIH OrVIL
Iiourl :s: 4.0 mA
Iiourl :s: 5.2 mA ~
VOL
Maximum Low Level •
Output Voltage
VIN=VIHorVIL
Ilourl:S:20 p,A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
0.1
0.1
0.1
V
V
V
2.0V '/0
4.5V
0
6.0V
0
VIN = VIH or VIL
Ilourl:S:4.0 rnA
Ilourl:S:5.2 mA
4.5V
6.0V
0.2
0.2
0.1
0.1
0.1
0.1
- 0.1
0.1
0.26
0.26
0.33
0.33
0.4
0.4
V
V
liN
Maximum Input Current
(Pins 7.15)
VIN=VccorGND
6.0V
±0.5
±5.0
±5.0
p,A
liN
Maximum Input Current
(aU other pins)
VIN = Vce or GND
6.0V
±0.1
±1.0
±1.0
p,A
IcC
Maximum Quiescent Supply
Current (standby)
VIN=VecorGND
10ur=0 p,A
6.0V
8.0
80
160
p,A
Maximum Active Supply
Current (per monostable)
VIN = Vee or GND
R/CEXT = 0.5Vec
2.0V 36
80
110
130
p,A
4.5V 0.33
1.0
1.3
mA
1.6
6.0V 0.7.
2.0
2.6
3.2
mA
Note 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power DISSipation temperature derating - plastic "N" package: -12 mWI"C from 6S'C to 85"C; ceramic "J" package: -12 mWI"C from l00'C to 125"C.
Note 4: For a power supply of SV ± 10% the worst-case output voltages (YOH. and VOU occur for HC at 4.5V. ThU~ the 4.5V values should be used when
del.ignlng with this supply. Worst-case VIH and VIL occur at Vce=S.sv and 4.5V respectively. (The VIH value at 5.SV is 3.85V.l The worst-case leakage current (liN.
Ice. and lozl occur for CMOS at the higher voltage and so the 6.DV values should be used.
Icc
3-193
AC Electrical Characteristics Vee = 5V. TA = 25"C. CL = 15 pF. tr=t,= 6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
tpLH
Maximum Trigger Propagation
Delay A. B or Clear to Q
22
36
ns
tpHL
Maximum Trigger Propagation
Delay A. B or Clear to Q
25
42
ns
tpHL
Maximum Propagation Delay Clear to Q
20
31
ns
tpLH
Maximum Propagation Delay Clear to Q
22
33
ns
tw
-Minimum Pulse Width A. B or Clear
14
26
ns
0
ns
tREM
Minimum Clear Removal Time
twa(MIN)
Minimum Output Pulse Width
CEXT=28 pF
REXT=2 kO
twa
Output Pulse Width
CEXT= 1000 pF
REXT=10kO
400
ns
10
p.s
I
AC Electrical Characteristics CL = 50 pF. tr=tf= 6 ns(unless otherwise specified)
Symbol
Parameter
Vee
Conditions
74H~
54HC
T = 25°C'
A
TA= -40 to 85°C TA= -55 to 125°C Units
Typ
Guaranteed Limits
tpLH
Maximum Trigger Propagation
Delay A. B or Clear to Q
2.0V 7i
4.5V 26
6.0V 21
169
42
32
194
51
39
210
57
44
ns
ns
ns
tpHL
Maximum Trigger Propagation
Delay A. B or Clear to Q
2.0V 88
4.5V 29
6.0V 24
197
48
38
229
60
46
250
67
51
ns
ns
ns
tpHL
Maximum Propagation
Delay Clear to Q
2.0V 54
4.5V 23
6.0Y 19
114
34
28
132
41
33
143
45
36
ns
ns
ns
tpLH
Maximum' Propagation
Delay Clear to Q
2.0V 56
4.5V 25
6.0V 20
116
36
29
13542
34
147
46
37
ns
ns
ns
tw
Minimum Pulse Width
A. B.Clear,
2.0V 57
4.5V 17
6.0V 12
123
30
21
144
37
27
157
42
30
ns
ns
ns
tREM
Minimum Clear
Removal Time
2.0V
4.5V
6.0V
0
0
0
0
0
0
0
0
0
-ns
ns
ns
2.0V 30
4.5V 8
6.0V 7
75
15
13
95
19
16
110
22
19
ns
ns
ns
trLH. trHL Maximum Output
Rise and Fall Time
twa(MIN) Minimum Output
Pulse Width
twa
Output Pulse Width
,
- CEXT=28pF
REXT=2kO
REXT=6 kO (VCC=2V)
CEXT = 0.1 p.F
REXT=10kO
2.0V 1.5
4.5V 450
6.0V 380
Min 4.5V
Max 4.5
p.s
ns
ns
1
0.9
1
1.1
CIN
Maximum Input
Capacitance (Pins 7 & 15)
12
20
CtN
Maximum Input
Capacitance (other inputs)
6
3-194
10
ms
ms
)
20
10
20
pF
10
pF
•
:s:::
:s:::
Logic Diagram
c.n
~
::I:
oN
N
.....
»
.......
:s:::
:s:::
.....
~
::I:
oN
N
.....
CLEAR ........-..r--JO...._ _ _~~_ _ _ _--'
:too
Vee
Vee
t
-.eO----'----+++---+---+--i
'1::.
Cm
TL/F/5325-5
Theory of Operation
CD
A-1l~
0 CD
__~~___rtJl~~n~
____~___
CD
u
CLEAR
VREF'
R/Cm
LJ
_ ......1
I-T-I
~I
__
I~~----In....~1
~T-I
I-T-I
L
I-T-I
TUF/5325-6
CD POSITIVE EDGE TRIGGER
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K. 10K>
I
DC Output CUrrent. per pin (lOUT)
DC Vee or GND Current. per pin (ICC)
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
Lead Temperature
(TLl (Soldering 10 seconds)
Supply Voltage (Vcc)
DC input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
Vee=2.0V
(tr• tf)
Vee=4.5V
Vce=6.0V
-0.5 to +7.0V
-1.5toVee+ 1.5V
-0.5 to Vcc+0.5V
±20mA
±25mA
±50mA
- 65·C to + 150·C
SOOmW
260·C
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
·C
,·C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
,
Conditions
Vee
TA=25"C
Typ
74HC
TA=-40to8S·C
S4HC
TA=-SSto125"C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1,.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
lIoUTI ~20 /LA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2:0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V.
VIN = VIH or VIL
IIOUTI~4.0 mA
IIOUTI~5.2 mA
·4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V'
V
VIN=VccorGND
6.0V
±0.1
±1.0
'±1.0
/LA
VIN=VIHorVIL
IIOUTI~4.0 mA
IIOUTI~5.2 mA
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
VIN = VIH or VIL
IIOUTI ~ 20 /LA
V
V
Maximum Quiescent VIN=VeeorGND
p.A
160
6.0V
8.0
80
Supply Current
IOUT=O /LA
Note 1: Absolule Maximum Ratings are Ihose values beyond which damage 10 the devloe may occur.
Note 2: Unless Olh4rwise specified all vollages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mWI'C from 65'C to 8S'C; oeramic "J" package: -12 mWl'C from 1OO'C to 12S'C.
Note 4: For a power supply of SV ±10% the worst case output voltages (YOH. and VOU occur for HC at 4.SV. Thus the 4.SV values should be used when
designing with this s)lpply. Worst case VIH and VIL occur at Vce= S.6V and 4.SV .... spectively. (The VIH value at 5.5V is 3.85V.l The worst case leakage current (liN.
Ice. and lozl occur for CMOS at the higher vol",ge and so the 6.0V values should be used.
Icc
3-198 '
AC Electrical Characteristics Vee = 5V, T A = 25'C, CL = 15 pF, tr= tf= 6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
tpLH
Maximum Propagation Delay A, B or C to any Y Output
20
41
ns
tpLH
Maximum Propagation Delay A, B or C to any Y Output
16
32
ns
tpLH
Maximum Propagation GL to any Y Output
22
44
ns_
tpHL
Maximum Propagation Delay GL to any Y Output
17
33
ns
ns
tpLH
Maximum Propagation Delay G1 or G2 to Output
16
35
tpHL
Maximum Propagation Delay G1 or G2 to Output
14
25
ns
Is
Minimum Set Up Time at A, Band C Inputs
10
20
ns
tH
Minimum Hold Time at A, Band C Inputs
-3
0
ns
tw
Minimum Pulse Width of Enabling Pulse at GL
9
_16
ns
AC Electrical Characteristics CL =50 pF, tr=tf= 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25'C
Vee
Typ
74HC
TA= -40 to 85'C
54HC
, \
TA= -55to 125'C
Units
Guaranteed Limits
tpLH
Maximum Propagation
Delay, A, B or C to any Y Output
2.0V
4.5V
6.0V
100
24
20
235
47
40
296
59
50
350
70
60
ns
ns
ns
tpLH
Maximum Propagation
Delay, A, B or C to any Y Output
2.0V
4.5V
6.0V
80
19
17
185
37
31
233
47
40
276
55
47
ns
ns
ns
tpLH
Maximum Propagation
GL to any Y Output
2.0V
4.5V
6.0V
125
25
20
250
50
43
315
63
54
373
75
63
ns
ns
ns
tpHL
Maximum Propagation Delay
GL to any Y Output
2.0V
4.5V
6.0V
95
19
16
190
38
32
239
48
41
283
75
48
ns
ns
ns
tpLH
Maximum Propagation
Delay, G1 or G2 to Output
2.0V
4.5V
6.0V
100
20
17
200
40
34
'252
50
43
298
60
51
ns
ns
ns
tpHL
Maximum Propagation
Delay G1 or G2 to Output
2.0V
4.5V
6.0V
73
15
12
145
2S
25
183
37
31
216
43
37
ns
ns
ns
Is
Minimum Set Up Time
at A, Band C Inputs
2.0V
4.5V
6.0V
100
20
17
125
25
21,
150
30
25
ns
ns
ns
tH
Minimum Hold Time
at A, Band C Inputs
2.0V
4.5V
6.0V
0
0
0
0
0
0
0
0
0
ns
ns
ns
tw
Minimum Pulse Width
of Enabling Pulse at GL
2.0V
4.5V
6.0V
30
10
9
80
16
14
100
20
18
120
24
20
ns
ns
ns
tTLH, tTHL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
CpO
Power Dissipation
Capacitance (Note 5)
75
CIN
Maximum Input
Capacitance
5
pF
10
10
10
pF
Note 5: CPO determines the no load dynamic power consumption, Po =Cpo vee2 f + lee Vee, and the no load dynamic current consumption, Is =Cpo Vee 1+ Icc·
3·199
B Functional Block Diagram
::c
~
::Ii
::Ii
(11
A .....oCII.::>--rl~_
...
I
an
::Ii
::Ii
~P--'"
:.<2IHp"tlr\--r'~--.I"+*=I~l:fl
SELECT
INPUTS
I(
DATA
OUTPUTS
Y4
INPUTS
ENABLE
"
{= ~:::~~~~~:t:)-...;..__Jd:~§§i{)
(81
81
TVF/5326-a
Typical Application "
8lROIE
DEl:ODER ENABLE
XI
XI
X2
I
OL
e
8
I
A
D2 81
HC2J7
" INPUT
YOY1
ADDRESS
yf Y3
~
Y4
VI VI Y7
I I I
v
I,
•
I
X3
X4
XI
}=
IEGIIERS
I
T I
I I
OL"
e
I
r
8
A
D2 81
GL
e
Hem
YOY1 Y2 Y3
Y4
8
A
02 81
OL
e
I
8 A
HC2J7
VI Y6 Y7
I 'I I 1"1 I J
I
I
YI Y7
11!I~Ll,l!
YO Y1 Y2 Y3 Y4 VI
D2 81
Hem
YOY1Y2Y3nftVlY7
JIl,l!l~AL
~~----------------------~y'------------------------'~
OUTPUTI
TVF/5326-3
6-Une to 64-Llne Decoder with Input Add..... Storage
"
3-200
~National
~ Semiconductor
PRELIMINARY
\ -=-;
C
microCMOS
MM54HC240/MM74HC240
Inverting Octal TRI-STATE® Buffer
MM54HC241/MM74HC241 Octal TRI-STATE Buffer
General Description
Features
These TRI-STATE buffers utilize microCMOS Technology,
3.5 micron silicon gate P-well CMOS. They possess high
drive current outputs which enable high speed operation
even when driving large bus capacitances. These circuits
achieve speeds comparable to low power Schottky devices,
whiie retaining the advantage of CMOS circuitry, i.e., high
noise immunity and low power consumption. Each has a
fanout of tr 5 LS-TTL equivalent inputs.
The MM54HC240/MM74HC240 is an inverting buffer and
has two active low enables (1<3 and 2(3). Each enable independently controls 4 buffers. MM54HC241/MM74HC241 is
a non-inverting buffer that has one active low enable and
one active high enable, each again controlling 4 buffers.
Neither device has Schmitt trigger inputs.
•
•
•
•
•
Typical propagation delay: 12 ns
TRI-STATE outputs for connection to system buses
Wide power supply range: 2-6V
Low quiescent supply current: 80 p.A (74 Series)
Output current 6 mA
All inputs are protected from damage due to static discharge by diodes to Vee and ground.
Connection Diagrams Dual-In-Line Packages
Vce
2G
lYl
2A4
lY2
2A3
lY3
2A2
1Y4 2Al
Vee
2G
lYl
2A4
lY2
2A3
lY3
2A2
lY4· 2Al
lG
lA 1
2Y4
lA2
2Y3
lA3
2Y2
lA4
2Y 1 GND
lG
lAl
2Y4
lA2
2Y3
lA3
2Y2
lA4
2Yl GND
TL/L/5020-2
TUU5020-1
Top View
Top View
Order Number MM54HC240J, MM74HC240J, N
See NS Package J20A or N20A
Order Number MM54HC241J, MM74HC241J, N
See NS Package J20A or N20A
Truth Tables
('HC240)
('HC241)
1G
1A
1Y
2G
2A
2Y
1G
1A
1Y
2G
2A
2Y
L
L
H
H
L
H
L
H
H
L
L
L
H
H
L
H
L
H
H
L
Z
L
L
L
H
Z
L
L
L
H
Z
Z
H
L
H
L
L
H
H
Z
H
H
L
Z
H
H
Z
Z
H = high level, L = low level, Z = high impedance
3-201
Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage (Vee)
Operating Conditions
-0.5 to + 7.0V
DC Input Voltage (VIN)
Supply Voltage (VeC>
DC Input or Output Voltage
(VIN. Your)
Operating Temp. Range (TA>
MM74HC
MM54HC
Input Rise or Fall Times
Vee=2.0V
(t,. til
Vee=4.5V
Vee=6.0V
-1.5 to Vee + 1.5V
-0.5 to Vee+0.5V
±20mA
±35mA
±70mA
DC Output Voltage (Vour)
Clamp Diode Current (11K. 10K>
DC Output Current, per pin (lour)
DC Vee or GND Current. per pin (IcC>
Storage Temperature Range (TSTG)
Power Dissipation (Po) {Note 3)
-65·Cto + 150"C
500mW
Lead Temp. (Tu (Soldering 10 seconds)
260"C
Min
-2
Max
6
0
Vee
UnlJs
V
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25·C
Typ
74HC
TA=-40t085·C
54HC
TA= -55 to 125"C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
Iiourl s: 20 !LA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIHorVIL
lIourlS:6.o mA
Iiourl S:7.8 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = VIH or VIL
IlourlS:6.0 mA
IlourlS:7.8 mA .
Maximum Low Level
Output Voltage
VOL
I
I
2.0V
4.5V
6.0V
VIN = VIH or VIL
IlourlS:20 p.A
liN
Maximum Input
Current
VIN=VeeorGND
6.0V
±0.1
±1.0
±1.0
p.A
loz
Maximum TRI-STATE
Output Leakage
Current
VIN=VIH orVIL
VoUr=VeeorGND
G=VIH. G=VIL
6.0V
±0.5
±5
±10
p.A
Maximum Quiescent
Supply Current
VIN=VeeorGND
10ur=0p.A
6.0V
0
lee
\
8.0
80
160
p.A
Nota 1: Absolute Maximum Ratings are thosa values beyond which damage to the device meyoccur.
Nata 2: unless otherwisa specnied all voltages are referenced to ground.
Nate 3: Power Dissipation temperature derating - plastic "N" package: -12 mWI'C from 65'C to 8S'C; ceramic "J" package: -12 mWI'C from 1OO'C to 12S'C.
Note 4: For a power supply of SV ±10% the worst casa output voltages (VOH. and VoLl occudor HC at 4.SV. Thus the 4.SV valuss should be uSed when
designing with this supply. Worst casa V,H and V'L occur at Vcc= S.5V and 4.5V respectively. (The V'H value atS.5V is 3.85V.) The worst casa leakage current (liN.
Icc. and lov occur for CMOS af the higher voltage and so the 6.0V values should be used.
,
3-202
AC Electrical Characteristics MM54HC240/MM74HC240Vcc=5V. TA=25'C. Ir =lf=6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed Limit
IpHL.lpLH
Maximum Propagation Delay
CL =45pF
12
18
ns
tpZH. tpzL
Maximum Enable Delay
10 Active Output
RI:.=1 kO
CL=45pF
14
28
ns'
tpHZ. tpLZ
Maximum Disable Delay
from Active Output
RL =1 kO
CL =5pF
13
25
ns
Units
'AC Electrical Characteristics MM54HC240/MM74HC240
Vcc=2.0V to 6.0V. CL =50 pF. t r =lf=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25"C
Vee
Typ
IpHL. tpLH
IpZH.lpZL
Maximum Propagation
Delay
Maximum Output Enable
Time
tpHZ. tpLZ
Maximum Output Disable
TIme
ITLH. ITHL
Maximum Output
Rise and Fa,1I Time
CPO
Power Dissipation
Capacitance (Note 5)
74HC
TA=-40t085'C
54HC
TA= -55to 125'C
Units
Guaranteed Limits
CL =50pF
CL =150 pF
2.0V
2.0V
55
80
100
150
126
190
149
224
ns
ns
CL =50 pF
CL=150pF
4.5V
4.5V
12
22
20
30
25
38
30
45
ns
ns
CL =50pF
CL=150pF
6.0V
6.0V
11
28
17
26
21
32
25
38
ns
ns
RL =1 kO
'CL =50pF
CL =150pF
2.0V
2.0V
75
100
150
200
189
252
224
298
ns
ns
CL =50pF
CL =150 pF
4.5V
4.5V
15
20
30
40
38
50
45
60
ns
ns
CL =50pF
CL=150pF
6.0V
6.0V
13
17
26
34
32
43
38
51
ns
ns
RL =1 kO
CL =50pF
2.0V
4.5V
6.0V
75
15
13
150
30
26
189
38
32
224
45
38
ns
ns
ns
60
12
10
75
15
13
90
18
15
ns
ns
ns
2.0V
4.5V
6.0V
I
(per buffer)
G=VIH
G=VIL
pF
pF
12
50
CIN
Maximum Input Capacitance
5
10
10
10
pF
COUT
Maximum Output Capacitance
10
20
20
20
pF
3-203
•
AC Electrical Characteristics MM54HC241/MM74HC241 Vcc=5V. TA=25"C. tr=t,=6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed Limit
Units
tpHL. tpLH
Maximum Propagation Delay
CL =45pF
13
20
ns.
tPZH. tPZL
Maximum Enable Delay to
Active Output
RL =1 kO
1G
17
28
ns
CL=45pF
2G
17
28
ns
Maximum Disable Delay
from Active Input
RL =1 kO
1G
15
25
ns
CL =5pF
2G
13
25
ns
tpHZ. tpLZ
AC Electrical Characteristics MM54HC241/MM74HC241
Vee = 2.0V to 6.0V. CL =50 pF. t r =tf=6 ns (unless otherwise specified)
Symbol
Parameter
Vee
Conditions
TA=25"C
Typ
tpHL. tpLH Maximum Propagation
Delay
tpZH. tpZL Maximum Output Enable
Time
,
tpHZ. tpLZ Maximum Output Disable
Time
2.0V 58
2.0V 83
CL =50pF
CL=150pF
CIN
Power Dissipation
Capacitance (Note 5)
Guaranteed Limits
115
165
145
208
171
246
ns
ns
CL =50pF
CL =150 pF
4.5V
. 4.5V
14
17
23
33
29
42
34
49
ns
ns
CL =50 pF
CL=150pF
6.0V
6.0V
10
14
20
28
25
35
29
42
ns
ns
RL =1 kO
CL =50pF
CL=150pF
2.0V 75 150
2.0V 100 200
189
252
224
298
CL =50pF
CL=150pF
4.5V 15
4.5V 20
30
40
38
50
45
60
ns
ns
CL =50pF
CL=150pF
6.0V
6.0V
13
17
26
34
. 32
43
38
51
ns
ns
RL =1 kO
CL =50 pF
2.0V
4.5V
6.0V
75
15
13
150
30
26
189
38
32
224
45
38
ns
ns
ns
60
12
10
75
15
13
90
18
15
ns
ns
ns
trLH. trHL Maximum Output
Rise and Fall Time
CPO
74HC
54HC
TA= -40 to 85"C TA= -55 to 125"C Units
2.0V
4.5V
6.0V
(~er buffer)
G=VIL. G=VIH
G=VIH. G=VIL
pF
pF
12
50
Maximum Input Capacitance
5
Maximum Output Capacitance
. ns
ns
10
10
..
10
pF
pF
10
20
20
20
COUT
Note 5: Cpo determines the no load dynamic power consumption. Po=Cpo Vccfl f+lcc Vee. and the no load dynamic current consumption.
Is=Cpo Vee f+lcc·
3·204
Logic Diagrams
•
.'"'"
..
..
N
N
...o
N
o
;,J:
IS!
12
3·205
~National
~ Semiconductor
microCMOS
MM54HC242/MM7 4HC~42
,Inverting Quad TRI-STATE® Transceiver
MM54HC243/MM74HC243 Quad TRI-STATE Transceiver
General Description
These TRI-STATE bidirectionai inverting and non-inverting
buffers utilize microCMOS Technology, 3.5 micron silicon
gate P-well CMOS, and are intended for two-way asynchronous communication between data buses. They have high
drive current outputs which enable high speed operation
when driving large bus capacitances. These circuits pos. sess the low power dissipation and high noise immunity associated with CMOS circuits, but speeds comparable to low
power Schottky TTL circuits. They can also drive 15 LS-TTL
loads.
The MM54HC242/MM74HC242 is a non-inverting buffer
and the MM54HC243/MM74HC243 is an inverting buffer.
Each device has one active high enable (GBA), and orie
active low enable (GAB). GBA enables the 'A outputs and
GAB enables the B outputs. This device does not have
Schmitt trigger inputs.
All inputs are protected from damage due to static discharge by diodes to Vee and ground.
Features
•
•
•
•
•
•
Typical.propagation delay: 12 ns
TRI-STATE outputs
Two way asynchronous communication
High output current: 6 rnA (74HC)
Wide power supply range: 2-EW
Low quiescent supply current: 80 ",A (74HC)
Connection Diagrams
Dual-In-Line Package
Vee
GaA
Ne
18
28
Dual-In-Line Package
38
48
Vee
GSA
Ne
. 18
28
3B
GAB
Ne
1A
2A
3A
4A
48
GND
TL/L/SOI9-1
Top View
Order Number MM54HC242J, MM74HC242J, N
See NS Package J14A or N14A
TL/L/p!l19-2
Top View
Order Number MM54HC243J, MM74HC243J, N
See NS Package J14A or N14A
Truth Tables
'HC242
'HC243
Control Inputs
Data Port Status
Control Inputs
GAB
GBA
A
B
GAB
GBA
A
B
H
L
H
L
H
H
L
L
OUTPUT
Isolated
Isolated
Input
Input
Isolated
Isolated.
OUTPUT
H
L
H
L
H
H
L
L
OUTPUT
Isolated
Isolated
Input
Input
Isolated
Isolated
OUTPUT
3-206
Data Port Status
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
-0.5to +7.0V
Supply Voltage (Veel
DC Input Voltage (VIN)
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
(tr, tf)
Vee=2.0V
Vee=4.5V
Vee=6.0V
-1.5 to Vee + 1.5V
DC Output Voltage (VOUT)
Clamp Diode Current (11K, 10K>
DC Output Current, per pin (lOUT)
DC Vee or GND Current, per pin (Ieel
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
-0.5 to Vee+0.5V
±20mA
±35mA
±70mA
- 65·C to + 150·C
500mW
260·C
Lead Temp. (Tt.l (Soldering 10 seconds)
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25·C
Typ
74HC
TA= -40to 8SOC
54HC
TA= -55 to 125·C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage.
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN=VIHorVIL
IIOUTI';;20 p.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0Y
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
'v
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
IIOUTI';;6.0 mA
IIOUTIQ.8 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = VIH or VIL
IIOUTI';;6.0 mA
IIOUTI';;7.8mA
VOL
Maximum Low Level
Output Voltage
VIN;" VIH or VI[
IIOUTI';;20 p.A
V
liN
Maximum Input
Current
VIN=Vee or GND
6.0V
±0.1
±1.0
±1.0
p.A
loz
Maximum TRI-STATE
Output Leakage Current
VOUT=VeeorGND
GAB=VIH, GBA= VIL
6.0V
±0.5
±5.0
±10
p.A
80
160
Maximum Quiescent
p.A
6.0V
8.0
VIN=Vee or GND.
Supply Current
10UT=0 p.A
Nota 1: Absolute Maximum Ratings o/e those values beyond which damage to the device may occur.
,.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Nota 3: Power Dissipation temperature derating - plastic "N" package: -12 mW rc from 6S'C to 8S'e; ceramic "J" package: -12 mWrc from 1OO'C to 12S'C.
Note 4: For a power supply of SV ± 10% the worst case output voltages (VOH. and Vou occur for HC at 4.SV. Thus the 4.SV values should be used when
designing with this supply. Worst esse VIH and VIL occur at Vee = S.SV and 4.SV respectively. (The VIH value at S.SV is 3.85V.) The worst case leakage current (liN.
Icc. and loz) occur for CMOS at the higher voltage and so the 6.0V values should be used.
Icc
(
3-207
Ell
AC Electrical Characteristics (MM54HC242/MM74HC242)
Vcc=5V. TA=25'C. t r =tf=6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed Umlt
Units
tpHL. tpLH
Maximum Propagation Delay
CL=45pF
12
18
ns
tpZH. tpZL
Maximum Output Enable
Time to Active Output
RL = 1kG
CL=45pF
17
28
ns
tpHZ. tpHL
Maximum Output Disable
Time from Active Output
RL=1 kG,
CL =5 pF
15
25
ns
I
AC Electrical Characteristics (MM54HC242/MM74HC242. MM54HC243/MM74HC243)
Vcc=2.0V to 6.0V. CL =50 pF. t,=tf=6 ns (unless otherwise specified)
TA=25'C
Symbol
Parameter
Conditions
Vee
Typ
74HC
TA=-40to85"C
54HC
TA= -55 to 125"C
Units
Guaranteed Umlts
CL =50pF
CL =150pF
2.0V ' 55
2.0V 80
100
150
126
190
149
224
ns
ns
CL =50pF
CL=150pF
4.5V
4.5V
12
22
20
30
25
38
30
45
ns
ns
CL =50pF
CL =150 pF
6.0V
6.0V
11
18
17
26
21
32
25
38
ns
ns
RL =1 kG
CL=50pF
CL =150 pF
2.0V
2.0V
75
100
150
200
189
252
224
298
ns
ns
CL =50pF
CL=150pF
4.5V
4.5V
15
30
30
40
38
50
45
60
ns
ns
.
CL =50 pF
CL =150 pF
6.0V
6.0V
13
17
26
34
32
43
38
51
ns
ns
tpHZ. tpLZ
Maximum Output,Disable
Time from Active Output
BL=1 kG
CL =50pF
2.0V
4.5V
6.0V
75
15
13
150
30
26
189
38
32
224
45
38
ns
ns
ns
tTLH. tTHL
Maximum Output.
Rise and Fall
Time
60
12
10
75
15
13
90
18
15
ns
ns
ns
CPO
Power Dissipation
Capacitance (Note 5)
tpHL. tpLH
tpZH; tPZL
Maximum Propagation
Delay
Maximum Output Enable
Time to Active Output
2.0V
4.5V
6.0V
(per buffer)
G=VIH. G=VIL
G=Vllo G=VIH
pF
pF
12
50
CIN
Maximum Input Capacitance
5
10
10
10
pF
COUT
Maximum Output CapaCitance
10
20
20
20
pF
3-208
Logic Diagrams
MM54HC242/MM74HC242
MM54HC243/MM74HC243
4A
o----f
1---o4B
4A
o----f
1----04B
3A
o----f
3B
3A
o----f
1---o3B
2AO---I
1----02B
2A
1---o2B
Vee
.....-
.....-~-olB
.....-olB
•
Vee
lA
+-.
o-t.....
lA
GAB
GAB
GBA
GBA
TL/Ll5019-3
3·209
o-t.....+-..
TL/L/5019-4
~
~
IN
U
:::t:
~
.....
:E
:E
......
~
~
IN
U
:::t:
r-------------------------------------------------------------------------------------,
~National
~ Semiconductor
microCMOS
MM54HC244/MM74HC244
Octal TRI-STATE® Buffer
~
It)
:E
:E
General Description
Features
These TRI-STATE buffers utilize microCMOS Technology,
3.5 micron silicon gate P-well CMOS, and are general purpose high speed non-inverting buffers. They possess high
drive current outputs which enable high speed operation
even when driving large bus capacitances. These circuits
achieve speeds comparable to low power Schottky devices,
while retaining the advantage of CMOS circuitry, i.e., high
noise immunity, and low power consumption. All three devices have a fanout of 15 LS-TTL equivalent inputsi
The MM54HC244/MM74HC244 is a non-inverting buffer
and has two active low enables (1 G and 2G). Each enable
independently controls 4 buffers. This device does not have
Schmitt trigger inputs.
•
•
•
•
•
Typical propagation delay: 14 ns
TRI-STATE outputs for connection to system buses
Wide power supply range: 2-6V
Low quiescent supply current: 80 /LA (74 Series)
Output current: 6 mA
All inputs are protected from damage due to static discharge by diodes to Vee and ground.
Connection Diagram
Dual-In-Line Package
Vee
2G
lYl
2A4
lG
lA 1
2Y4
lA2
2Y3
lA3
lY3
2A2
lY4
2Y2
lA4
2Yl GND
Top View
Order Number MM54HC244J or MM74HC244J,N
See NS Package J20A or N20A
Truth Table
'HC244
H
1G
1A
1Y
2G
2A
2Y
L
L
H
H
L
H
L
H
L
H
Z
Z
L
L
H
H
L
H
L
H
L
H
Z
Z
~
high level, L
~
low level, Z
~
3-210
high impedance
2Al
TLlF/5327-1
Absolute Maximum Ratings
Operating Conditions
'Supply Voltage (Veel
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K, 10Kl
DC Output Current, per pin (loUT)
DC Vee or GND Current, per pin (Ieel
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Nole 3)
Lead Temperalure (TLl
(Soldering 10 seconds)
Supply Voltage (Veel
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
(Ir, til· Vee=2.0V
Vee=4.5V
Vee=6.0V
(Notes 1 & 2)
-0.5 to +7.0V
-1.5 to Vee+1.5V
-0.5 to Vee+0.5V
±20mA
±35mA
±70mA
-65'Cto +150'C
500mW
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
260'C
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25'C
74HC
TA= -40t08SOC
54HC
TA= -55 to 125'C
Units
VIH
Minimum High Level
Inpul Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Inpul Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
1.9
4.4
5.9
V
V
V
VIN = VIH or VIL
IIOUTI,;;; 20 p.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
IIOUTI ';;;6.0 rnA
IIOUTI';;;7.8 rnA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0;33
0.4
0.4
V
V
VIN=VIH orVIL
IIOUTI';;;6.0 mA
IIOUTI ';;;7.8 rnA
VOL
Maximum Low Level
Outpul Voltage
VIN=VIH orVIL
IIOUTI';;;20 p.A
,
liN
Maximum Input
Current
VIN=VeeorGND
6.0V
±0.1
±1.0
±1.0
p.A
loz
Maximum TRI-STATE
Outpul Leakage
Current
VIN=VIH,orVIL
VOUT= Vee or GND
G=VIH
6.0V
±0.5
±5
±10
p.A
p.A
Maximum Quiescent
6.0V
8.0
80
160
VIN=VeeorGND
Supply Current
10UT=0 p.A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the devica may occur.
Note 2: Unless otherwise specified all voltages are reierencad to ground.
Note 3: Power Dissipation temperature derating - plastiC "N" package: -12 mWI'C lrom 65'e to 85'C; ceramic "J" package: -12 mWI'C from 100"C to 125·C.
Note 4: For a power supply 015V ± 10% the worst case output voltages (VOH. and VoLl occur lor HC at 4.5V. Thus the 4.5V values should be used when designing
wHh this supply. Worst case VIH and VIL occur at Vee = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (liN. Icc. and
lozl occur lor CMOS at the higher voltage and so the 6.0V values should be used.
Icc
3-211
I
Guaranteed Limits
TyP
•
'.
AC Electrical Characteristics MM54HC244/MM74HC244
Vcc=5V, TA = 25°C, 1,=tf=6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Umlt
Units
tpHL, ~PLH
Maximum Propagation
Delay
CL = 45pF
14
20
ns
tpZH, tpZL
Maximum Enable Delay
10 Active Output
RL = 1 kO
CL = 45pF
17
28
ns
Maximum Disable Delay
frc;»m Active Outpul
RL = 1 kO
CL = 5pF
15
25
ns
- IpHZ,lpLZ
AC Electrical Characteristics Vee = 2.0V-6.0V, CL = 50 pF, t,=tf= 6 ns (unless otherwise specified)
,
Symbol
Parameter
Conditions
Vee
TA=25°C
Typ
tpHL, tpLH
tpZH, tPZL
Maximum Propagalion
Delay
Maximum Output Enable
Time
tpHZ, tpLZ
Maximum Output Disable
Time
ITLH' ITHL
Maximum Output
Rise and Fall TIme
CPO
Power Dissipation
Capacitance (Note 5)
74HC
TA=-40to85°C
54HC·
TA= -55to 125°C
Units
Guaranteed Limits
CL =50pF
CL=150pF
2.0V
2.0V
58
83
115
165
145
208
171
246
ns
ns
CL =50pF
CL =150 pF
4.5V
4.5V
14
17
23
33
29
42
34
49
ns
ns
CL=50pF
CL=150pF
6.0V
6.0V
10
14
20
28
25
35
29
42
CL =50pF
CL =150pF
2.0V
2.0V
75
100
750
200
189
252
224
298
ns
ns
CL=50pF
CL =150pF
4.5V
4.5V
15
30
30
40
38
50
45
60
ns
ns
CL =50 pF
CL =150 pF
6.0V
6.0V
13
17
26
34
32
43
38
51
ns
ns
RL = 1 kO
CL=50 pF
2.0V
4.5V
6.0V
75
15.
13
150
30
26
189
38
32
224
45
38
ns
ns
ns
60
12
10
75
15
13
90
18
15
ns
ns
ns
-
ns
ns
RL = 1 kO
2.0V
4.5V
6.0V
"
(per buffer)
G=VIH
G=VIL
pF
pF
12
50
CIN
Maximum Input
Capacitance
5
10
10
10
pF
GoUT
Maximum Output
Capacitance
10
20
20
20
pF
Note 5: Cpo determines the no load dynamic power consumption, Po =Cpo vcc2 f+ Icc Vc:i;; and the no load dynamic current consumption, IS =Cpo Vcc f+ ICC'
3-212
..
..
....
i:
i:
Logic Diagram
UI
'HC244
::E:
n
N
2A4
2Y4
.
.
i:
i:
....
2A3
2Y3
2A2
2V2
%
n
N
2V1
2G
1A4
1V4
1A3
1V3
1A2
1Y2
Vee
.L---+_-o 1Y1
1A1
TUF/5327-2
3-213
~ r---------------------------------~----------------------------------------_,
~
(.)
:::t:
j:!
::::E
::::E
.....
~
~
(.)
:::t:
~National
\
~ Semiconductor
----'J
'''---'-/
microCMOS
MM54HC245/MM74HC245
Octal TRI-STATE® Transceiver
"'=I'
~
::::E
::::E
General Description
This TRI-STATE bidirectional buffer utilizes microCMOS
Technology, 3.5 micron silicon gate P-well CMOS, and is
intended for two-way asynchronous communication between data buses. It has high drive current outputs which
enable high speed operation even when driving large bus
capacitances. This circuit possesses the low power consumption and high noise immunity usually associated with
CMOS circuitry, yet has speeds comparable to low power
Schottky TIL circuits.
'
This device has an active low enable input G and a direction
control input, DIR. When DIR is high, data flows from the A
inputs to the B outputs. When DIR is low, data flows from
the B inputs to the A outputs. The MM54HC2451
MM74HC245 transfers true data from one b,us to the other.
This device can drive up to 15 LS-TIL Loads, and does not
have Schmitt trigger inputs. All inputs are protected from
damage due to static discharge by diodes to Vee and
ground.
Features
•
•
•
•
Typical propagation delay: 13 ns
Wide power supply range: 2-6V
Low quiescent current: 80 p.A maximum (74 HC)
TRI-STATE outputs for connection to bus oriented
systems
• High output drive: 6 mA (minimum)
,. Same as the '645
Connection Diagram
Dual-In-Llne Package
ENABLE
Vee
DIR
Ii
Bl
B2
A2
AI
A3
B3
B4
B5
B6
A4
AS
A6
A7
B7
A8
Top View
Order Number MM54HC245J or MM74HC245J, N
See NS Package J20A or N20A
I
Truth Table
Control
Inputs
H
G
DIR
L
L
H
L
H
X
Operation
B data to A bus
A data to B bus
Isolation
= high level, L = low level, X = Irrelevant
3-214
B8
GND
TL/F/5165-1
Absolute Maximum Ratings (Notes 1 &2)
Operating Conditions
Supply Voltage (Vcc)
DC Input Voltage DIR and G pins (VIN)
Supply Voltage (Vee)
-0.5 to + 7.0V
-1.5 to Vee+ 1.5V
-0.5 to Vee + 0.5V
DC Input/Output Voltage (VIN' VOUT)
±20mA
Clamp Diode Current (leo)
±35mA
DC Output Current, per pin (loUT)
±70mA
DC Vee or GND Current, per pin (Icc)
Storage Temperature Range (TSTG)
-65'Cto + 150'C
Power Dissipation (Po) (Note 3)
500mW
260'C
Lead Temp. (TU (Soldering 10 seconds)
DC Electrical Characteristics
Symbol
Parameter
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TAl
MM74HC
MM54HC
Min
2
Max
6
Units
V
0
Vcc
V
-40
-55
+85
+125
'c
'c
1000
500
400
ns
ns
ns
Input Rise/Fall Times
Vee=2.0V
(tr,tf)
Vee=4.5V
Vee=6.0V
(Note 4)
. 'Condltlons
Vee
TA=25'C
Typ
74HC'
54HC
TA= -40 to 8SOC TA= -55to 125'C Units'
Guaranteed Limits
VIH
' Minimum High Level Input
Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level Input
Voltage
2.0V
4.5V
6.0V.
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level Output
Voltage
VIN=VIH orVIL
IIOUTI s: 20 J-LA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V,
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
IIOUTI S:6.0 mA
IIOUTI S:7.8 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = Vee to GND
VIN = VIH or VIL
IIOUTIS:6.0 mA
IIOUTIS:7.8 mA
VOL
Maximum Low Level Output
Voltage
VIN = VIH or VIL
IIOUTI s: 20 J-LA
liN
Input Leakage
Current (G and DIR)
6.0V
±0.1
±1.0
±1.0
J-LA
loz
Maximum TRI-STATE Output VOUT= Vee or GND 6.0V
Leakage Current
Enable G = VIH
±0.5
±5.0
±10
J-LA
Maximum Quiescent Supply VIN = Vee or GND
160
6.0V
8.0
80
J-LA
Current
10UT=0 ".A
Note 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mWI'C from 6S'C to 8S'C; ceramic "J" package: -12 mWI'C from 1DO'C 10 12S'C.
Note 4: For a power supply of SV ± 10% the worst case output voltages (YaH. and VOU occur for HC at4.SV. Thus the 4.SV values should be used when designing
with this supply. Worst case VIH and VIL occur at vcc-S.5V and 4.5V respectively. (The VIH value at S.SV is 3.85V.) The worst cese laakage current (liN. Icc. and
lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
ICC
3-215
•
AC Electrical Characteristics
Symbol
Vcc=5V. TA=25"C. t,.=tf=6ns
Conditions
Parameter
'Guaranteed
Limit
Typ
Units
tpHL. tpLH
Maximum Propagation Delay
CL = 45pF
13
17
ns
tPZH. tpZL
Maximum Output Enable Time
RL = 1 kn
CL=45pF
33
42
ns
tpHZ. tpLZ
Maximum Output Disable Time
RL = 1 kn
CL = 5pF
32
42
ns
AC Electrical Characteristics
Symbol
Parameter
Vcc= 2.0V to 6.0V. CL = 50 pF. tr=tf= 6 ns (unless otherwise specified)
Conditions
Vee
TA=25DC
Typ
tpHL.
tpLH
tpZH.
tpZL
Maximum Propagation Delay
Maximum Output Enable
,
lime
74HC
TA= -40 to 85DC
54HC
TA= -55 to 125D C
Units
Guaranteed Limits
CL=50pF
CL = 150pF
2.0V
2.0V
29
38
72
96
88
116
96
128
ns
ns
CL=50pF
CL = 150pF
4.5V
4.5V
14
18
18
24
22
29
24
32
ns
ns
CL=50pF
CL = 150pF
6.0V
6.0V
14
18
18
24
22
29
24
32 '
ns
ns
CL = 50pF
CL = 150pF
2.0V
70
2.0V ' 80
184
216
224
260
240
284
ns
ns
CL = 50pF
CL = 150pF
4.5V
4.5V
35
41
46
54
56
65
60
71
ns
ns
CL=50pF
CL = 150pF
6.0V
6.0V
31
36
41
47
50
' 57
54
62
ns
ns
RL = 1 kn
tpHZ.
tpLZ
Maximum Output Disable
Time
RL = 1 kn
CL=50pF
2.0V
4.5V
6.0V
47
33
31
172
43
41
208
52
50
224
56
54
ns
ns
ns
trLH. trHL
Output Rise and Fall Time
CL=50pF
2.0V
4.5V
6.0V
20
6
5 '
60
12
10
75
15
13
90
18
15
ns
ns
ns
CPO
Power Dissipation
Capacitance (Note 5)
G =VIL
G=VIH
CIN
Maximum Input Capacitance
5
10
10
10 •
pF
CIN/OUT
Maximum Input/Output
Capacitance. A or B
15
20
20
20
pF
pF
pF
100
12
Note 5: Cpo determines the no load dynamic power consumption. Po =Cpo V~ 1+ ICC Vcc. and the no load dynamic current consumption. Is =Cpo Vce 1+ Icc.
3-216
lii:
lii:
Logic Diagram
U1
""0
""
.......
lii:
::I:
A8
B8
I\,)
U1
A7
B7
lii:
-..J
""0
""
::I:
B8
At
I\,)
U1
A5
B5
A4
B4
A3
B3
A2
B2
Vee
"'-HH-<>B1
ENABLE
~O-----------~r-~
r...c~"""""'------o DIR
3-217
TLlF/5165-2
.~
..
,--------------------------------------------------------------------------------,
.
(.)
:c ~National
..... ~ Semiconductor
:E
.....-
:E
&n
N
(.)
:c
:;
:E
:E
\'--_""":"'_.......,..J)
microCMOS
MM54HC251/MM74HC251
8-Cha·nnel TRI-STATE® Multiplexer
General Description
This 8-channel digital multiplexer with TRI-STATE outputs
utilizes microCMOS Technology, 3.5 micron silicon gate Pwell CMOS. Along with the high noise immunity and low
power consumption of standard CMOS integrated circuits, it
possesses the ability to drive 10 LS-TIL loads. The large
output drive capability and TRI-STATE feature make this
part ideally suited for interfacing with bus lines in a bus oriented system;
This multiplexer features both true (y) and complement (W)
outPl,lts as well as a STROBE input The STROBE must be
at a low logic level to enable this device. When the STROBE
input is high, both outputs are in the high impedance state.
When enabled, address information on the data select inputs determines which data input is routed to the Y and W
Connection and Logic Diagrams
outputs. The 54HC174HC logic family is speed, function, as
well as pinout compatible with the standard 54LS174LS logic family. All inputs are protected from damage due to static
discharge by internal diode clamps.to Vee and ground.
Features
• Typical propagation delay
Data select to Y: 26 ns
• Wide supply range: 2-6V
• Low power supply quiescent current: 80 ",A maximum
(74HC) .
• TRI-STATE outputs for interface to bus oriented
systems
Truth Table
Dual-ln-L1ne Package
DATA INPUTS
B
C
10
D40SD607
A
Select
9
B
03
02
Inputs
DATA SELECT
C
01
DO
Y
W
S
Y
W STROBE GND
8
3
-.DATA INPUTS
OUTPUTS
TLlF/532B-1
Outputs
C
B
A
Strobe
S
X
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
H
L
L
L
L
L
L
L
L
,
Y
W
Z
DO
01
02
03
04·
05
06
07
Z
00
01
02
03
04
05
06
07
= high logic level, L = logic level
X = Irrelevant, Z = high impedance (off)
DO, 01 . . . 07 = the level of the respective 0 input
H
Top View
Order Number MM54HC251J or MM74HC251J, N
See NS Package J16A or N16E
0,--1---=1=1:::1",....,A -i;:>o"~oo--t
oz-----Hd::I:::r""""\
o. -----t:t:t:t:t:r'-
TL/F/532B-2
3-218
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
-0.5 to + 7.0V
Supply Voltage (Vecl
DC Input Voltage (VIN)
-1.5 to Vee+1.5V
Supply Voltage (Vee)
Clamp Diode Current (11K, 10Kl
DC Output Current, per pin (lOUT)
DC Vee or GND Current, per pin (lee)
-0.5 to Vee+0.5V
±20mA
±25mA
±50mA
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
-65'C to + 150'C
500mW
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TAl
MM74HC
MM54HC
Input Rise or Fall Times
(tr, tf)
Vee=2.0V
Vee=4.5V
Vee=6.0V
DC Output Voltage (VOUT)
Lead Temp. (Tu (Soldering 10 seconds)
260'C
Min
2
Max
6
Units
V
0
Vee
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter.
Conditions
TA=25'C
Vee
74HC
TA=-40to85'C
54HC
TA=-55to125'C
Units
Guaranteed Limits
Typ
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN=VIH orVIL
IIOUTI~20 IJ-A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIH orVIL
IIOUTI~4.0 mA
IIOUTI ~ 5.2 rnA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = VIH or VIL
IIOUTI~4.0 mA
IIOUTI~5.2 mA
VOL
Maximum Low Level
Output Voltage
VIN=VIH orVIL
IIOUTI~20 IJ-A
liN
Maximum Input
Current
VIN = Vee or GND
6.0V
±0.1
±1.0
±1.0
IJ-A
loz
Maximum TRISTATE Leakage
Current
Strobe = Vee
VouT=VeeorGND
6.0V
±0.5
±5
±10
IJ-A
IcC
Maximum Quiescent
Supply Current
VIN=VeeorGND
10UT=01J-A
6.0V
8.0
80
160
IJ-A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specHied all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N"' peckage: -12 mW/'C Irom 65'C to 85'C; ceramic "J" package: -12 mWI'C from 100'Cto 125'C.
Note 4: For a power supply 015V ±10% the worst case output voltages (YOH. and Vou occur lor
at 4.5V. Thus the 4.5V values should be used when designing with
this supply. Worst case VIH and VIL occur at Vee = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (liN. lee. and IOV occur lor
CMOS at the higher voltage and so the 6.0V values should be used.
He
3-219
•
.....
an
N
o
AC Electrical Characteristics Vee = 5V, TA = 25°C, CL = 15 pF, tr =t,=6 ns
::E:
.~
Symbol
:E
:E'
......
.....
an
N
o
tpHL, tpLH
an
:E
:E
...
::E:
Typ
Guaranteed
Limit
Units
Maximum Propagation Delay
A, BorCtoY
26
35
ns
tpHL, tpLH
Maximum Propagation
Delay, A, B or C to W
27
35
ns
tpHL, tpLH
Maximum Propagation
Delay, Any D to Y
22
29
ns
tpHL, tpLH
Maximum Propagation
Delay, Any D to W
24
32
ns
tpZH, tPZL
Maximum Output Enable
Time, W Output
RL=1k
CL =50pF
19
27
, ns
tpZH, tPZL
Maximum Output Enable
Time, Y Output
RL=1k
CL=50pF
19
26
ns
tpHZ, tpLZ
Maximum Output Disable TIme
WOutput
RL=1k
CL =5pF
26
40
ns
tpHZ, tpLZ
Maximum Output Disable Time
YOutput
RL =1k
CL =5pF
27
35
ns
Parameter
.
Conditions
AC Electrical Characteristics
Symbol
Parameter
CL =50 pF, \=t,=6 ns (unless otherwise specified)
Conditions
Vee
TA=25°C
Typ
74HC
TA=-40to85°C
Units
Guaranteed Limits
Maximum Propagation Delay
A,BorCtoY
2.0V
4.5V
6.0V
90
31
26
205
41
35
256
51
44
tpHL. tpLH
Maximum Propagation
Delay. A, B or C to W
2.0V
4.5V
6.0V
95
32
27
205
41
35
256
51
44
tpHLo tpLH
Maximum Propagation
Delay. any D to Y
2.0V
4.5V
6.0V
70
27
23
195
39
33
244
49
41
tpHL. tpLH
Maximum Propagation
Delay. any D to W
2.0V
4.5V
6.0V
75
29
25
185
37
32
231
46
40
2.0V
4.5V
6.0V
45
21
18
150
30
26
tpHL, tpLH
54HC
TA=-55to125"C
300
60
51
ns
ns
ns
300
60
51
ns
ns
ns
283
57
48
ns
ns
ns
268
54
46
ns
ns
ns
188
38
33
218
l
I
,
Maximum Output Enable Time
WOutput
RL =1k'
38
ns
ns
ns
tPZH. tPZL
Maximum Output Enable Time
YOutput
RL=1k
2.0V
4.5V
6.0V
45
21
18
145
29
25
181
36
31
210
42
36
ns
ns
ns
tpHZ. tpLZ
Maximum Output Disable TIme
WOutput
RL =1k
2.0V
4.5V
.6.0V
60
29
25
22P
44
37
275
55
46
319
64
54
ns
ns
ns
tpHZ. tpLZ
Maximum Output Disable Time
YOutput
RL =1k
2.0V
4.5V
6.0V
60
30
26
195
39
33
244
49
41
283
57
48
ns
ns
ns
trHL. tTLH
Maximum Output Rise
and Fall TIme
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
CPO
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input
CapaCitance
tpZH, tpZL
(per package)
44~
110
S
pF
10
10
10
pF
I
Note 5: Cpo determines the no load dynamic power consumption, Po~Cpo Vcc2 !+lee Vee, and the no load dynamic current consumption, Is=Cpo Vccf+lee,
3-220
~National
~ Semiconductor
J
\
microCMOS
MM54HC253/MM74HC253
Dual 4-Channel TRI-STATE® Multiplexer
General Description
The MM54HC253/MM74HC253 utilizes microCMOS Technology, 3.5 micron silicon gate P-well CMOS, to achieve the
low power consumption and high noise immunity of standard CMOS integrated circuits, along with the capability to
drive 10 LS-TTL loads. The large output drive and TRISTATE features of this device make it ideally suited for interfacing with bus lines in bus organized systems. When the
output control input is taken high, the multiplexer outputs
are sent into' a high impedance state.
When the output control is held low, the associated multiplexer chooses the correct output channel for the given input signals determined by the select A and B inputs.
The 54HC174HC logic family is functionally and pinout compatible with the standard 54LS174LS logic family. All inputs
are protected from damage due to static discharge by internal diode clamps to Vee and ground.
Features
•
•
•
•
•
Typical propagation delay: 24 ns
Wide power supply range: 2V-6V
Low quiescent current: 80 !JA maximum (74HC Series)
Low input current: 1 ,.,.A maximum
Fanout of 10 LS-TTL loads
Connection Diagram
Dual-In-Llne Package
DUTPUT
CDNTROL
A
T2G
SELECT
V1CC
16
15
DATA INPUTS
zr
14
13
,
DUTPUT
T T T Y9 .
I
12
•
lD
11
I
B ii A
I
~
.,..-
.......
B I A ~
'J
2
OJp:T
B
CONTROL SELECT
lG
3
lJ3
.
z4
I!:.
11,5
DATA INPUTS
TDPVIEW
I
OU!:T
G1:
lY
TUF/5108-1
Order Number MM54HC253J or MM74HC253J, N
See NS Package J16A or N16E
Truth Table
Select
Inputs
Data Inputs
Output
Control
Output
B
A
CO
C1
C2
C3
G
y
X
X
X
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
X
X
X
X
X
X
.X
X
X
X
X
X
X
X
X
H
L
L
L
L
L
L
L
L
Z
L
H
L
H
L
H
L
H
X
X
X
X
X
X
L
H
X
X
X
X·
L
H
X
X
,
L
H
Select inputs A and B are common to both sections.
H
= high level, L = low level, X = irrelevant, Z = high Impedance (off).
3-221
i
Absolute Maximum Ratings
Operating Conditions
(Notes 1 & 2)
-0.5 to +7.0V
Supply Voltage (Vee)
DC Input Vol~ge (VIN)
-1.5 to Vee + 1.5V
Supply Voltage (VeC>
DC Output Voltage (VOUT)
-0.5 to Yee+0.5V
±20mA
DC Input or Output Voltage
Clamp Diode Current (11K. 10K)
DC Output Current. per pin (lOUT)
±25mA
DC Vee or GND Current. per pin (IcC>
±50mA
Storage Temperature Range (T8TG)
Operating Temp. Range (TA)
MM74HC
MM54HC
500mW
Lead Temperature (T L.l
(Soldering 10 seconds)
Max
6
Units
V
0
Vee
.V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
(VIN. VOUT)
-65'C to + 150'C
Power Dissipation (Po) (Note 3)
Min
2
Input Rise or Fall Times
(tr • ttl
Vee=2.0V
Vee=4.5V
Vee=6.0V
260'C
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Vee
Conditions
TA=25'C
74HC
TA= -40 to 85'C
Typ
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
VOH
Minimum High Level
Output Voltage
Maximum Low Level
Output Voltage
-
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.4B
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIHorVIL
IIOUTI :;;4.0 rnA
IIOUTIS:5.2 rnA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = VIH or VIL
IIOUTIS:4.0 rnA
IIOUTIS:5.2 mA
VOL
Units
Guaranteed Limits
VIH
VIN = VIH or VIL
IIOUTIS:20 ",A
54HC
TA= -55to 125'C
VIN = VIH or VIL
IIOUTIs:20 ",A
liN
Maximum Input
Current
VIN=VeeorGND
6.0V
±0.1
±1.0
±1.0
",A
loz
Maximum TRI-STATE
Output Leakage
Current
Strobe = Vee
VOUT= Vee or GND
6.0V
±0.5
±5.0
±10
",A
IcC
Maximum Quiescent
Supply Current
VIN = Vee or GND
10UT=0",A
6.0V
B.O
BO
160
1;LA
Note 1: Absolute Maxlmu", Ratings are those values
beyo~d
which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Powar Dissipation temperature derating - plastiC "N" package: -12 mWre from 6S'C to 8S'C; ceramic "J" package: -12 mWI'C from 100'C to 12S'C.
Note 4: For a pewer supply of 5V ± 10% the worst case output voitages (VOH, and VoU occur for HC at 4.SV. Thus the 4.SV values should be used when designing
with this supply. Worst case VIH and VIL occur at Vcc~ S.SV and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (lIN, Icc, and
IOz) occur for CMOS at the higher voltage and so the 6.0V values should be used.
t
3-222
AC Electrical Characteristics Vee = 5V, TA = 25'C, tr=t,= 6 ns, CL = 15 pF
Typ
Guaranteed Limit
Units
tPHL, tpLH
Maximum Propagation
Delay, Select A or B to Y
24
30
ns
tpHL, tpLH
Maximum Propagation
Delay, any Data to Y
18
23
ns
tpZH' tPZL
Maximum Output Enable Time
Y Output to a Logic Level
RL =1k
13
18
ns
tpHz, tpLZ
Maximum Output Disable Time
Y Output to High Impedance State
Rl.;=1k
18
27
ns
Symbol
Parameter
Conditions
AC Electrical Characteristics CL = 50 pF, tr =t,=6 ns (unless otherwise specified)
:
Symbol
Parameter
Conditions
Vee
TA=25'C
Typ
74HC
54HC
TA= -40 to 85'C TA= -55to 125'C Units
Guaranteed Limits
tpHL, tpLH
Maximum Propagation
Delay, Select A or B to Y
2.0V
4.5V
6.0V
131
29
24
158
35
30
198
44
38
237
53
45
ns
ns
ns
tpHL, tpLH
Maximum Propagation
Delay, any Data to Y
2.0V
4.5V
6.0V
99
22
19
126
28
23
158
35
29
189
42
35
ns
ns
ns
tpZH, tPZL
Maximum Output Enable Time
RL =1 kO
2.0V
4.5V
6.0V
63
14
12
90
20
17
113
25
21
135
30
26
ns
ns
ns
tpHZ, tpLZ
Maximum Output Disable Time
RL =1 kO
2.0V
4.5V
6.0V
90
20
17
135
30
25
169
38
31
203
45
38
ns
ns
ns
tTHL, tTLH
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
5
10
10
10
pF
CIN
Maximum Input Capacitance
(per package)
Outputs Enabled
pF
90
pF
Outputs Disabled
25
Note 5: CPO determines the no load dynamic power consumption, Po ~ Cpo Vcr!- f + ICC Vee, and the no load dynamic current consumption, IS ~ CpO Vee f+ IcC.
CPD
Power Dissipation
Capacitance (Note 5)
I
Logic Diagram
DUTPU~
CONTROL
--i>o-
10
~I~t·
['"
lCl
DATAl
Vee
:-~ :::Do-II ~
lCl
lCD
~~I
r
lC2
DATAl
lCl
2CO
-(
A
......
.....
~o.....
OUTPUT
CDHTR~
}"
·~I
-1>0-
":"
;1>o-~
TlIF/51 08-2
3-223
I·~
National
.- ~ Semiconductor
:E
:E
~..
In
:E
:E
MM54HC257/MM74HC257
Quad 2-Channel TRI-STATE® Multiplexer
General Description
This QUAD 2-TO-1 line data selector/multiplexer utilizes
microCMOS Technology, 3.5 micron silicon gate P-well
CMOS. Along with the high nOise immunity and low poWer
dissipation of standard CMOS integrated circuits, it possesses the ability to drive LS-TTL loads. The large output
drive capability coupled with the TRI-STATE feature make
this device ideal for interfacing with bus liries in a bus organized system. When the OUTPUT CONTROL input line is
taken high; the outputs of all four multiplexers are sent into
a high impedance state. When the OUTPUT CONTROL line
is low, the SELECT input chooses whether the A or B input
is used.
'
The 54HC/74HC logic family is speed, function, and pin-out
compatible with the standard 54LS174LS logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to Vee and ground.
Features
•
•
•
•
Typical propagation delay: 12 ns
Wide power supply range: 2V-6V
Low quiescent current: 80 IJ.A maximum (74HC Series)
TRI-STATE outputs for connection to system buses.
Connection and logic Diagrams
OUTPUT(1S)
CONTROL(2)
1A :....:.._ _ _ _ _ _
Dual·ln·Llne Package
INPUTS
OUTPUT _ _
Vee CONTROL 4A
4B
16
15
G
14
4A
13
4B
INPUTS
OUTPUT _ _ OUTPUT
4Y
3A
3B
3Y
12
4Y'
11
3A
-;~
+-______-r~
1B (~3)~____
10
2A
(;..;S)'--____+-____-t--r"""""\
2B
(;..;6)'------t------t--r~
'3B
3Y
3A (_11~)_____r------~r_,
3B (~10~)_____r------~r_,
-+______+-1,"\
4A (,_14..;.)____
SELECT 1A
18
1Y
2A
2B
2Y
GNO
- - OUTPUT - - OUTPUT
INPUTS
INPUTS
-+______+-1,"\
4B (;..;13..;.)____
TLlF/S329-1
Top VIew
Order Number MM54HC257J or MM74HC257J, N
See NS Package J16A or N16E
TLlF/S329-2
Truth Table
Inputs
Output
Control
H
L
L
L
L
Select
X
L
L
H
H
A
B OutputY
X X
L X
H X
X L
X H
Z
L
H
L
H
H = high level, L = low level, X = Irrelevant, Z
3-224
= high Impedance, (off)
Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage (VeC>
Operating Conditions
-0.5to +7.0V
DC Input Voltage (VIN)
-1.5 to Vee + 1.5V
Supply Voltage (VeC>
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TAl
MM74HC
MM54HC
Clamp Diode Current (11K. 10K>
±20mA
DC Output Current. per pin (lOUT)
±35mA
DC Vee or GND Current. per pin (Icc>
±70mA
Storage Temperature Range (TSTG)
- 65'C to + 150'C
Power Dissipation (Po) (Note 3)
Lead Temp.
Max
·6
Units
V
0
Vee
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
(tr• ttl
Vee=2.0V
Vee=4.5V
Vee=6.0V
500mW
(TL> (Soldering 10 seconds)
Min
2
260"C
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25'C
74HC
TA=-40t085'C
Typ
54HC
TA= -55to 125'C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
6.0\1
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
'V
V
2.0V
4.5V
6.0V
0
0
'0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
/IOUT/:S:6.0 mA
/IOUTI:S:7.8mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = VIH or VIL
/IOUT/:S:20 /LA
VIN = VIH or VIL
ilOUT/ :S: 6.0 mA
/IOUT/:S:7.8 mA
Maximum Low Level
Output Voltage
VOL
\
VIN = VIH or VIL
/IOUT/:S:20/LA
2.0V
4.5V
liN
Maximum Input
Current
VIN = Vce or GND
6.0V
±0.1
±1.0
±1.0
/LA
loz
Maximum TRI-STATE
Output Leakage
VOUT=VccorGND
OC=VIH
".
6.0V
±0.5
±5.0
±10
/LA
Icc
Maximum Quiescent
,
Supply Current
VIN=VccorGND
IOUT=O /LA
6.0V
8.0
80
160
/LA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specHied all voltages are referenced to ground.
Note 3: Power Dissipation tempemture demting - plastic "N" package: -12 mW I'C from 65'C to 85'C; cemmic "J" package: -12 mWI'C from 1OO'C to 125'C.
Note 4: For a power supply of 5V ± 10% the worst case output voltages {YOH, and Vou occur for HC at 4.5V. Thus the 4.5V values should be used when
deSigning with this supply. Worst case VIH and VIL occur at Vcc= 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.l The worst case leakage current (liN.
Icc. and lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
\
3-225
•
AC Electrical Characteristics Vcc=5V, TA=25°C, tr=tf=6ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
tpHL, tpLH
Maximum Propagation
Delay, Select to any Y Output
CL =45pF
12
18
ns
tpHL, tpLH
Maximum Propagation
Delay, A or B to any Y Output
CL =50pF
13
21
ns
tPZH: tPZL
Maximum Output Enable
Time, any Y Output to a Logic Level
RL =1 kO
CL =45pF
17
28
ns
tpHZ, tpLZ
Maximum Output Disable
Time, any YOutput to a High Impedance State
RL =1 kO
CL =5 pF
15
25
ns
"
AC Electrical Characteristics Vcc= 2.0V to 6.0V, CL = 50 pF, tr=tf= 6 ns (unless otherwise specified)
Sy,!,bol
Parameter
Conditions
Vee
TA=25"C
Typ
tpHL, tpLH
ipHL, tpLH
tpZH, tPZL
Maximum Propagation
Delay, Select to any
YOutput
Maximum Propagation
Delay, A or B to any
YOutput
Maximum Output
Enable Time,
any Y Output to a Logic Level
54HC
TA= -55to 125"C
Units'
Guaranteed Limits
CL =50 pF
CL =150pF
2.0V
2.0V
50
70
100
150
125
,189
CL =50pF
CL =150 pF
4.5V
4.5V
10
15
20
30
CL =50pF
CL =150pF
6.0V
6.0V
9
13
CL =50pF
CL =150 pF
2.0V
2.0V
CL =50pF
CL =150 pF
CL =50 pF
CL=150pF
150
224,
ns
ns
25
38
30
45
ns
ns
17
26
21
32
25
38
ns
ns
50
70
100
150
125
190
150
221
ns
ns
4.5V
4.5V
10
15
20
30
29
,38
30
45
ns
ns
6.0V
6.0V
10
17
17
26
21
32
25
38
ns
ns
CL =50pF
CL =150pF
2.0V.
2.0V
75
100
150
200
189
252
224
298
ns
ns
CL =50pF
CL=150pF
4.5V
4.5\1
15
20
30
40
38
50
45
60
ns
ns
CL=50pF
CL =150 pF
6.0V
6.0V
13
17
26
34
32
43
38
51
ns
ns
75
15
13
150
30
26
189
38
32
224
45
38
ns
ns
ns
60
12
10
75
15
13
90
18
15
ns
ns
ns
RL =1 kO
tpHz,tpLZ
Maximum Output Disable
Time, any Y Output to a High
Impedance State
RL =1 kO
CL =50pF
·2.0V
4.5V
6.0V
tTHL, trLH
MaXimum Output Rise
and Fall Time
CL =50pF
2.0V
4.5V
6.QV
CPD
Power Dissipation
Capacitance (Note 5)
(permux)
Enable
Disabled
CIN
74HC
TA= -40 to 85°C
30
8
Maximum Input
capacitance
5
,',
10
10
10
,pF
pF
pF
Note 5: Cpo determineslhe no load dynamic power consumption, Po= CpD Vee2 1+ lee Vee, and the no load dynamic current consumption. Is = CPD Vee 1+ lee.
3-226
~National
\
~ Semiconductor
j
microCMOS
MM54HC259/MM74HC259
8-Bit Addressable Latch/3-to-8 Line Decoder
General Description
This device utilizes microCMOS Technology, 3.5 micron silicon gate P-well CMOS, to implement an 8-bit addressable
latch, designed for general purpose storage applications in
digital systems.
The MM54HC259/MM74HC259 has a single data input (D),
8 latch outputs (Q1-Q8), 3 address inputs (A, B, and C), a
common enable input (E), and a common CLEAR input. To
operate this device as an addressable latch, data is held on
the D input, and the address of the latch into which the data
is to be entered is held on the A, B, and C inputs. When
ENABLE is taken low the data flows through ,to the addressed output. The data is stored when ENABLE transitions from low to high. All unaddressed latches will remain
unaffected. With enable in the high state the device is deselected, and all latches remain in their previous state, unaffeqted by changes on the data or address inputs. To eliminate the possibility of entering erroneous data into the latches, the enable should be held high (inactive) while the address lines are changing.
Connection Diagram
If enable is held high and CLEAR is taken low all eight latches are cleared to a low state. If enable is low all latches
except the addressed latch will be cleared. The addressed'
latch will instead follow the D input, effectively implementing
a 3-to-8 line decoder.
All inputs are protected from damage due to static discharge by diodes to Vee and ground.
Features
•
•
•
•
Typical propagation delay: 18 ns
Wide supply range: 2-6V
Low input current: 1 p.A maximum
Low quiescent current: 80 p.A maximum (74HC Series)
Latch Selection Table
Dual-In-Line Package
Select Inputs
OUTPUTS
EN- DATA
VCC CLEAR ABLE IN
f 1,5 1,4 1,3
16
~
1
I
12 1 14
3
ABC
00
LATCH SELECT
5
01
6
02
OUTPUTS
7
03
.1.s
Clear
G
H
H
L
.L
L
H
L
H
Each
Other
Output
D
QiD
D
L
QiD
QiD
L
L
A
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
0
1
2
3
4
5
6
7
D = the level at the data inpul
GND
TL/F/5006-1
Truth Table
Outputs of
Addressed
Latch
B
H = high level. L = low level
Top View
Order Number MM54HC259J or MM74HC259J,N
See NS Package J16A or N16E
Inputs
C
Latch
Addressed
Function
Addressable Latch
Memory
8-Une Decoder
Clear
3-227
QIO the level of OJ (i = O. 1 .•• 7. as appropriate) before the indicated steady-state in. put conditions were established.
•
.'
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
-0.5to·+7.0V
Supply Voltage (Vee)
DC Input Voltage (VIN)
-1.5 to Vee + 1.5V
DC Output 'l(oltage (VOUT)
-0.5 to Vee+0.5V
±20mA
Clamp Diode Current (11K. 10K)
DC Output Current. per pin (lOUT)
DC Vee or GND Current. per pin (IcC>
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
Supply Voltage (Vee>
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA>
MM74HC
MM54HC
Input Rise or Fall Times
(tr• tf)
Vee=2.0V
Vee=4.5V
Vee=6.0V
±25mA
±50mA
- 65·C to + 150·C
500mW
Lead Temperature (Tt.>
(Soldering 10 seC?nds)
260"C
Min
2
Max
6
0
Vee
Units
V
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
TA=25·C
Vee
Typ
74HC
TA=-40t085·C
54HC
TA= -55 to 125·C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V.
V
V
VIL
Maximum Low Level
Input Voltage :
2.0V
4.5V
6.0V
0.3
0'.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN=VIH orVIL
IIOUTI S:20 p.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0'
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIHorVIL
IIOUTI S:4.0 mA
IIOUTIS:5.2 mA
4.5V
B.OV
0.2
0.2
0.26
0.2B
0.33
0.33
0.4
0.4
V
V
VIN=Vee or GND
6.0V
±0.1
±1.0
±1.0
p.A
VIN = VIH or VIL
IIOUTIS:4.0 mA
IIOUTI s: 5.2 mA
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
VIN=VIH or.vIL
IIOUTI s: 20 p.A
Maximum Quiescent VIN=VeeorGND
B.OV
8.0
80
160
p.A
Supply Current
IOUT=O p.A .
Note 1: Absolute Maximum Ratings are those values beyond which damage to lI)e device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Nole 3: Power DiSSipation temperature derating - plastic "N" package: -12 mWI"e from 6S'C to 8S'O, ceramic "J" package: -12 mW/'C from 100'C to 12S'C.
Nole 4: For a: power supply of SV ± 10% the worst case output voltages (VOH. and Vall occur for HC at 4.SV. Thus the 4.SV values should be used when designing
with this supply. Worst case VIH and VIL occur at Vcc= 5.SV and 4.SV respectively. (The VIH value at S.SV is 3.8SV.) The worst case leakage current (liN. ICC. and
lov occur for CMOS at the higher voltage and so the 6.0V values should be used.
lee
3-228
AC Electrical Characteristics (Vee = 5.0V, TA= 25°C, tr=tf= 6 ns, CL = 15 pF unless otherwise specified.)
Symbol
Parameter
Conditions Typ
Guaranteed
Limit
Units
tpHL, tpLH
Maximum Propagation Delay
Data to Output
18
32
ns
tpHL, tpLH
Maximum Propagation Delay
Select to Output
20
38
ns
tpHL, tpLH
Maximum Propagation Delay
Enable to Output
20
35
ns
tpHL
Maximum Propagation Delay
Clear to Output
17
27
ns
tw
Minimum Enable Pulse Width
10
16
ns
tw
Minimum Clear Pulse Width
10
16
ns
tr, tf
Maximum Input Rise and Fall TIme
500
ns
ts
Minimum Setup Time Select or
Data to Enable
15
20
ns
tH
Minimum Hold Time Data or
Address to Enable
-2
0
. ns
AC Electrical Characteristics tr =tf=6 ns, CL=50 pF, Vee=2.0V-6.0V
Symbol
Parameter
Conditions
Vee
TA=25°C
Typ
74HC
TA= -40 to 85°C
54HC
TA=-55t0125°C
Units
Guaranteed Limits
tpHL, tpLH
Maximum Propagation Delay
Data to Output
2.0V
4.5V
6.0V
60
19
17
180
37
32
225
46
40
250
52
45
ns
ns
ns
tpHL, tpLH
Maximum Propagation Delay
Select to Output
2.0V
4.5V
6.0V
72
21
18
220
43
37
275
54
46
310
60
52
ns
ns
ns
tpHL, tpLH
Maximum Propagation Delay
Enable to Output
2.0V
4.5V
6.0V
65
27
23
200
40
35
250
50
44
280
58
50
ns
ns
ns
tpHL
Maximum Propagation Delay
Clear to Output
2.0V
4.5V
6.0V
50
18
16
150
31
26
190
39
32
210
44
37
ns
ns
ns
tw
Minimum Pulse Width
Clear or Enable .
2.0V
4.5V
6.0V
80
16
14
100
20
18
120
24
20
ns
ns
ns
ts
Minimum Setup Time Address
or Data to Enable
2.0V
4.5V
6.0V
100
20
15
125
25
19
150
28
25
ns
ns
ns
tH
Minimum Hold Time Address or
Data to Enable
2.0V
4.5V
6.0V
-10
-2
-2
·0
0
0
0
0
0
0
0
0
ns
ns
ns
trLH, tTHL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
19
ns
ns
ns
5
10
10
10
pF
C'N
CPQ
.
Input Capacitance
22
pF
Power Dissipation
(per package)
80
Capacitance (Note 5)
Nota 5: Cpo determines the no load dynainic power consumption, Po =Cpo Vee!- f+ Icc Vee, and the no load dynamiC current consumption, Is =CposVCCSf+ ICC.
3-229
•
o~ Logic Diagram
:::c
~
.....
==
==
'"
0
m
C\I
o
:::c
~
~
1.1)
==
==
...-- D
E
a
I
CL l-
I'"'"
,..
r--.
.....- D
E
J
~
,..
~
D
E
J
a
CL I-
a
D
h-
a
E
CL
~.
-- D
E
~
I
as
CL I-
~
~
I'"'"
F
~
C
~
~
D
E
F
a
CL f-
~
B
~
...-- D
f
A
a
CL H
----{>c>- rl>
a
E
CL f-
D
E
CL f-
01
~
I....-
~
J
a
00
~
CLEAR
Tl/F/S006-2
3-230
~National
1-"""""'\)
microCMOS
~ Semiconductor
MM54HC266/MM74HC266 Quad 2-lnput
Exclusive NOR Gate
General Description
Features
This exclusive NOR gate utilizies microCMOS Technology,
3.5 micron silicon gate P-well CMOS, to achieve operating
speeds similar to equivalent LS-TTL gates while maintaining
the low power consumption and high noise immunity characteristic of standard CMOS integrated circuits. These
gates are fully buffered and have a fanout of 10 LS-TTL
loads. The MM54HC/MM74HC logic family is functionally as
well as pin out compatible with the standard 54LS174LS
logic family. However, unlike the 'LS266, which Is an open
collector gate, the 'HC266 has standard CMOS push-pull
outputs. All inputs are protected from damage due to static
discharge by internal diode clamps to Vee and ground.
•
•
•
•
•
•
Typical propagation delay: 9 ns
Wide operating voltage range: 2-6V
Low input current: 1 /-LA maximum
Low quiescent current: 20 /-LA maximum (74 Series)
Output drive capability: 10 LS-TTL loads
Push-pull output
Connection Diagram
Dual-In-Llne Package
vee
B4
V3
A4
B3
A3
8
7
3
2
A1
V1
B1
V2
B2'
A2
GND
TopYlew
Order Number MM54HC266J or MM74HC266J, N
NS Package J14A or N14A
See
Truth Table
Inputs
Outputs
A
B
Y
L
L
H
H
L
H
L
H
H
L
L
H
Y=Ai""!i=AB + AS
3-231
TL/F/S330-1
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions·
-0.5 to + 7.0V
Supply Voltage (Vee)
DC Input Voltage (VIN)
-1.5 to Vee + 1.5V
DC Output Voltage (VOUT)
-0.5 to Vee + 0.5V
±20mA
Clamp Diode Current (11K. 10K)
±25mA
DC Output Current. per pin (lOUT)
±50mA
DC Vee or GND Current. per pin (Ieel
Storage Temperature Range (TSTG)
-65'Cto + 150'C
Power Dissipation (PD) (Note 3)
.500mW
Lead Temp. (TL> (Soldering 10 seconds)
260'C
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
Vee,=2.0V
(tr. tf)
Vee=4.5V
Vee=6.0V
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Conditions
Parameter
Vee
TA=25'C
74HC
TA=-40to85'C
Typ
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4,2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
,V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
IIOUTI~20 ",A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
IIOUTI ~ 4.0 mA
116uTI~5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = Vee or GND
6.0V
±0.1
±1.0
±1.0
",A
VIN=VIH orVIL
IIOUTI ~ 4.0 mA
IIOUTI ~ 5.2 mA
VOL
liN
Maximum Low Level
Ou1puf Voltage
Maximum Input
Current
VIN = VIH or VIL
IIOUTI~20",A
Maximum Quiescent VIN=VeeorGND 6.0V
20
40
2.0
",A
Supply Current
IOUT=O",A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise speclfoed all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic UN" package: -'2 mWI'C from 85°C to 85°C; ceramic "J" package: -12 mWI'C Irom 1Oo-C to 125°C.
Note 4: For a power supply 015V 0% the worst case output voltages (YOH. and Vou occur lor HC at 4.5V. Thus the 4.5V values should be used when deSigning
with this supply. Worst case VIH and VIL occur at Vcc= 5.5V and 4.5V respectively. (The VIH value at 5,5V is 3.85V.) The worst case leakage current (liN. Icc. and
loz) occur lor CMOS at the higher voltage and so the 6.0V values should be used.
lee
±,
I
".
"
3-232
,
AC Electrical Characteristics Vee=5V, TA=25'C, CL =15 pF, I r =lf=6 ns
Symbol
Parameter
Conditions
tpHL, tpLH
Maximum PrQpagation
Delay
Parameter
Conditions
Guaranteed
Limit
Units
12
20
ns
.
AC Electrical Characteristics Vee =
Symbol
.Typ
2.0V to 6.0V, CL = 50 pF, tr = tf = 6ns (unless otherwise specified)
Vee
TA=25'C
Typ
74HC
TA= -40 to 85'C
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
IpHL,lpLH
Maximum Propagalion
Delay
2.0V
4.5V
6.0V
60
12
10
120
24
20
151
30
26
179
36
30
ns
ns
ns
tTHL, trLH
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
75
15
13
95
19
16
110
22
19
ns
ns
ns
CPO
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input
Capacitance
(per gate)
8
7
pF
25
5
10
10
10
pF
Note 5: CPO determines the no load dynamic power consumption, Po= CPO Vee! f+ lee Vee, and the no load dynamic current consumption, Is = Cpo Vee f+ Icc-
3-233
•
.... r----------------------------------------------------------------------------,
~
~ '~National
'
~ ~ Semiconductor
PRELIMINARY
\
J
microCMOS
:::E
......
~
.... MM54HC273/MM74HC273 Octal 0
'(\I
o
Clea~
...::c
Flip-Flops With
:::E
:::E
General Description
Features
These edge triggered flip-flops utilize microCMOS Technology, 3.0 micron silicon gate N-well CMOS, to implement 0type flip-flops. They possess high noise immunity, low power, and speeds comparable to low power Schottky TTL circuits. This device contains 8 master-slave flip-flops with a
common clock, and common clear. Data on the 0 input having the specified setup and hold times is transferred to the Q
output on the low to high transition of the CLOCK input. The
CLEAR input when low, sets all outputs to a low state.
Each output can drive 10 low power Schottky TTL equivalent loads. The MM54HC273/MM74HC273 is functionally
as well as pin compatible to the 54LS273174LS273. All inputs are protected from damage due to static discharge by
diodes to Vee and ground.
•
•
•
•
•
Ln
Connection Diagram
\ICc
eo
Typical propagation delay: 18 ns
Wide operating voltage range
Low input current: 1 /LA maximum
Low quiescent current: 80 /LA (74 Series)
Output drive: 10 LS-TTL loads
Dual-In-Llne Package
ID
7D
80'
7Q
ID
5D
50
CLOCK
11
10
CWR
tQ
ID
3Q
3D
Top View
prder Number MM54HC273J or MM74HC273J, N
,See NS Package J20A or N20A
Truth Table
(Each Flip-Flop)
Inputs
Outputs
Clear
Clock
D
Q
L
H
H
H
X
X
i
t
H
L
L
H
L
Qo
X
L
H = high level (sleady slate)
L = low level (sleady slate)
X = don't care
t = transition from low to high level
00 = the level of before the indicated sleady slale '
input conditions were eslablished
a
3-234
aHD
TL/F/5331-1
Absolute Maximum Ratings (Notes 1 and 2)
-0.5 to +7.0V
Supply Voltage (Vee>
DC Input Voltage (VIN)
-1.5 to Vee + 1.5V
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
±20mA
Clamp Diode Current (11K. 10K)
±25mA
DC Output Current. per pin (lOUT)
±50mA
DC Vee or GND Current. per pin (Ice>
Storage Temperature Range (Tsm)
- 65'C to + 150'C
Power Dissipation (Po) (Note 3)
500mW
Lead Temp. (TLl (Soldering 10 seconds)
260'C
Operatigg Conditions
Supply Voltage {Vee>
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
Vee=2.0V
(tr• tf)
Vee=4.5V
Vee=6.0V
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25'C
74HC
TA= -40 to 85'C
Typ
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN=VIH orVIL
IIOUTI~20 p-A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
IloUTI~4mA
IIOUTI~5.2mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
VIN=VeeorGND
6.0V
±0.1
±1.0
±1.0
p-A
80
160
p-A
VIN = VIH or VIL
IIOUTI~4.0 mA
IiOUTI~5.2 mA
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
VIN = VIH or VIL
IIOUTI~20 p-A
Maximum Quiescent VIN = Vee or GND 6.0V
8
Supply Current
IOUT=Op-A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Icc
V
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mW I'C from 65'C to 85'C; ceramic"J" package: -12 mW/'C from 100'C to 125'C.
Note 4: For a power supply of 5V ± 10% the worst case output voltages (VOH. and VoLl occur for HC at4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at Vcc= 5.5V and 4.5V respectively. (The VIH value at5.5V is 3.85V.) The worst case leakage current (liN. Icc. and
loz) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3·235
AC Electrical Characteristics Vcc=5V,TA=25°C,CL=15pF,tr =tf=6ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
fMAX
Maximum Operating
Frequency
50
30
MHz
tpHL,·tpLH
Maximum Propagation
Delay, Clock to Output
18
27
ns
tpHL
Maximum·Propagation
Delay, Clear to Output
18
27
ns
tREM
Minimum Removal Time,
Clear to Clock
10
20
ns
ts
Minimum Setup Time
Data to Clock
10
20
ns
tH
Minimum Hold ~ime
Clock to Data
-2
0
ns
tw
Minimum Pulse Width
Clock or Clear
10
16
ns
I
AC Electrical Characteristics CL = 50 pF, tr= tf= 6 ns (unless otherwise specified)
Symbol
Parameter
'Condltions
TA=25°C
Vee
Typ
fMAX
Maximum Operating
Frequency
2.0V
4.5V
6.0V
tpHL, tpLH
Maximum Propagation
Delay, Clock to Output
2.0V
4.5V
6.0V
tpHL
Maximum Propagation
Delay, Clear to Output
tREM
74HC
TA= -40 to 85"C
54HC
TA= -55 to 125°C
Units
Guaranteed Limits
5
27
31
4
21
24
3
18
20
MHz
MHz
MHz
50.
21
19
160
32
27
200
40
33
240
48
40
ns
ns
ns
2.0V
4.5V
6.0V
50
21
19
160
32
27
200
40
33
240
48
40
ns
ns
ns
Minimum Removal Time
Clear to Clock'
2.0V
4.5V
6.0V
30
10
9
100
20
17
125
25
21
150
30
25
ns
ns
ns
ts
Minimum Setup :rime
Data to Clock
2.0V
4.5V
6.0V
30
10
9
100
20
125
25
21
150
30
25
ns
ns
ns
tH
Minimum Hold Time
Clock to Data
2.0V
4.5V
6.0V
-10
-2
-2
0
0
0
0
0
0
0
0
0
ns
ns
ns
tw
Minimum Pulse Width
Clock or Clear
2.0V
4.5V"
6.0V
30
10
8
80
16
14
100
20
18
120
24
20
ns
ns
ns
tr, tf
Maximum Input Rise and
Fall Time, Clock
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
tTHL, tTLH
Maximum Output Rise
and,Fall Time
2.0V
4.5V
6.0V
75
15
13
95
19
16
110
22
19
ns
ns
ns
CpO
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input
Capacitance
(per package)
30
8
7
17
pF
175
5
,
10
10
10
pF
Note 5: Cpo determines the no load dynamic power consumption. Po= CPO Vcc2 f+ Icc Vee. and the no load dynamic current consumption. Is = CPO Vee f+ Icc.
3·236
Logic Diagram
D1 (3)
Q2
D3~-++-I
Q4
D8~;""+""-I
.
CLOCKo-o..(11~)--of ~)D-""MI>
CLEAR 0.:(:.;:,.1)_
.......
.»_+__..1
TLlF/5331-2
3-237
~National
\.
~ Semiconductor
MM54HC280/MM74HC280
9-Bit .odd/Even Parity Generator/Checker
General Description
Features
The MM54HC280/MM74HC280 utilizes microCMOS Technology, 3.5 micron silicon gate P-well CMOS, to achieve the
high noise immunity and low power consumption ot'standard CMOS integrated circuits. It possesses the ability to
drive 10 LS-TIL loads.
•
•
•
•
•
This parity generator/checker features odd/even outputs to
facilitate operation of either odd or even parity applications.
The word length capability is easily expanded by cascading
devices. The 54HC174HC logic family is speed, function,
and pinout compatible with the standard 54LS174LS family.
All inputs are protected from damage due to static discharge by internal diode clamps to Vee and ground.
o
Typical propagation delay: 28 ns
Wide power supply range: 2V-6V
Low quiescent current: 80 p.A maximum (74HC)
Low input current: 1 p.A maximum
Fanout of 10 LS-TIL loads
Connection Diagram
Dual-In-Line Package
INPUTS
Ie
0'
Vc
14
G
13
,
12 •
H,
INPUTS
11
10
INPUT
1:
EVEN
I
1:
ODD ,
OUTPUTS
TDPVIEW
TUF/5121-1
Order Number MM54HC280J or MM74HC280J, N
See NS Package J14A or N14A
Function Table
Outputs
Numbers of Inputs A
H
)
microCMOS
thru 1 that are High
l: Even
0,2,4,6,8
1,3,5,7,9
H
L
L
H
= high level, L = low level
3-238
l: Odd
!
Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage (Veel
-0.5 to +7.0V
DC Input Voltage (VIN)
-1.5 to Vee+1.5V
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
±20mA
Clamp Diode Current (11K. 10K!
±25mA
DC Output Current. per pin (lOUT)
±50mA
DC Vee or GND Current. per pin (ieel
Storage Temperature Range (TSTG)
-65'C to + 150'C
500mW
Power Dissipation (PD) (Note 3)
Lead Temp. (TLl'(Soldering 10 seconds)
260'C
DC Electrical Characteristics
Symbol
Parameter
Operating Conditions
Supply Voltage {Veel
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TAl
MM74HC
MM54HC
Input Rise or Fall Times
Vee=2.0V
(tr• tf)
Vee=4.5V
Vee=6.0V
Min
2
0
Max
Vee
Units
V
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
6
(Note 4)
Conditions
Vee
TA=25'C
74HC
TA= -40 to 85'C
Typ
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
VIH
Minimum High Level
input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3..15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
IIOUTI:S:20/LA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V·
V
V
VIN = VIH or VIL
IIOUTI:S:4.0mA
IIOUTI:s: 5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
±1.0
/LA
160
/LA
VIN = VIH or VIL
IIOUTI :S:4.0 mA
IIOUTI:S:5.2 mA
VOL
Maximum Low Level
Output Voltage
VIN=VIHorVIL
IIOUTI:S:20 /LA
liN
Maximum Input
Current
VIN = Vee or GND
6.0V
±0.1
±1.0
Icc
Maximum Quiescent VIN = Vee or GND
Supply Current
. IOUT=O /LA
6.0V
8.0
80
..
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Not.e 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mW rc from 6S'e to 8S'C; ceramic "J" package: -12 mW I'e from 100'C to 12S'C.
Note 4: For a power supply of sv ± 10% the worst case output voltages (VOH. and Vou occur for He at 4.SV. Thus the 4.SV values should be used when
designing with this supply. Worst case VIH and VIL occur at Vcc= S.SV and 4.SV respectively. (The VIH value at S.SV is 3.8SV.) The worst case leakage current (liN.
Icc. and loz) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3-239
5
AC Electrical Characteristics Vcc=5V,TA=25°C,CL=15pF,t,.=t,=6ns·
:::E:
Typ
Guaranteed
Limit
Units
Maximum Propagation
Delay, Data to l: Even
28
35
ns
Maximum Propagation
Delay, Data to l: Odd
28
35
ns
"0'
Symbol
Parameter
::::&
::::&
tpHL, tpLH
fIiI
tpHL, tpLH
.....
C;
o
:::E:
;7;
::::&
::::&
COnditions
AC Electrical Characteristics Vcc=2.0V to 6.0V, CL = 50 pF, t r =t,=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=25°C
Typ
tpHL, tpLH
Maximum Propagation
Delay, Data to l: Even
2.0V
4.5V
B.OV
103
,21
tpHL, tpLH
Maximum Propagation
Delay, Data to l: Odd
2.0V
4.5V
B.OV
tTLH, lTHL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
CPO
Power Dissipation
Capacitance (Note 5)
74HC
TA=-40t08SoC
54HC
TA= -55 to 125°C
Units
Guaranteed Limits
17
205
41
35
258
52
44
305
61
52
ns
ns
ns
103
21
17
205
41
35.
258
52
44
305
61
52
ns
ns
ns
30
8
75
15
13
95
19
16
110
22
19
ns
ns
ns
7
pF
10 .
Maximum Input Capacitance
5
10
10
pF
CIN
Note 6: Cpo determines the no load dynamic power consumption, Po= Cpo Vc;c2 f+ lee Vee. and the no load'dynamic current consumption. IS = Cpo Vee f+ lee.
Logic Diagram
Vee-pin 14
}OO-D.o-::.& !: 000
o 11
F 13
}OO-D~5 !:EVEN
'HC280
3-240
TLlF/5121-2
~National
PRELIMINARY
\
~ Semiconductor
)
microCMOS
MM54HC283/MM74HC283
4-Bit Binary Adder with Fast Carry
General Description
Features
This full adder performs the addition of two 4-bit binary numbers utilizing microCMOS Technology, 3.5 micron silicon
gate P-well CMOS. The sum (l:) outputs are provided for
each bit and the resultant carry (C4) is obtained from the
fourth bit. These adders feature full internal look ahead
across all four bits. This provides the system ,designer with
partial look-ahead performance at the economy and reduced package count of a ripple-carry implementation.
• Full-carry look-ahead across the four bits
• Systems achieve partial look-ahead performance
with the economy of ripple carry
• Wide supply range: 2V to 6V
• Low quiescent power consumption: 8 p.A at 25'C
• Low input current: < 1 p.A
The adder logic, including the carry, is,Jmplemented in its
true form meaning that the end-around carry can be accomplished without the need for logic or level inversion. All inputs are protected from damage due to static discharge by
internal diode clamps to Vee and ground.
Connection Diagram
Dual-in-Line Package
~3
A3
83
14
15
A4
13
B4
12
11
2:4
C4
10
-
-
2
1
2:2
9
3
B2
A2
4
2:1
5
A1
7
6
B1
CO
Top View
Order Number MM54HC283J or MM74HC283J, N
See NS Package J16A or N16E
I
.'
3-241
/8
GND
TL/F/5332-1
Absolute Maximum Ratings (Notes 1 & 2)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K. 10K)
DC Output Current. per pin (lOUT)
DC Vee or GND Current. per pin (IcC>
Storage Temperature Range (TSTG)
Power Dissipation (PD) (Note 3)
Operating Conditions
-0.5 to + 7.0V
Supply Voltage (VeC>
-1.5 to Vee+ 1.5V
Supply Voltage (VeC>
-0.5 to Vee+1.5V
±20 mA
±25 mA
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA) .'
MM74HC
MM54HC
±50mA
- 65'C to + 150'C
500mW
Lead Temperature (T Ll
(Soldering 10 seconds)
Min
2
Max
6
Units
V
0
Vee
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
(tr• tf)
Vee=2.0V
Vee=4.5V
Vee=6.0V
260'C
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25'C
74HC
TA= -40 to 85'C
Typ
54HC
TA=-55t0125'C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
'0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
I!OUT[,;;20 /LA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
[IOUT[';;4.0mA
[IOUT[';;5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = VIH or VIL
[IOUT[';;4.0 mA
[IOUT[';;5.2 mA
VOL
Maximum Low Level
Output Voltage
VIN = VIH or VIL
[IOUT[ ,;; 20 /LA
liN
Maximum Input
Current
VIN=VeeorGND
6.0V
±0.1
.±1.0
±1.0
/LA
Icc
Maximum Quiescent
Supply Current
VIN=VeeorGND
IOUT=O /LA
6.0'1
8.0
80
160
/LA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating ~ plastic "N" package: -t2 mWrC from 6SoC to 8SoC; ceramic "J" package: -12 mWrCfrom 100°C to 12SoC.
Note 4: For a power supply of sv ± 10% the worst case output voltages (VOH. and VoLl occur for HC at 4.5V. Thus the 4.SV values should be used when designing
with this supply. Worst case VIH and VIL occur at Vcc~ S.SV and 4.SV respectively. (The VIH value at S.SV is 3.8SV.) The worst case leakage current (lIN. Icc. and
loz) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3·242
AC Electrical Characteristics Vcc =
5V. T A = 25'C. CL = 15 pF. Ir = If = 6 ns
Typ
Guaranteed
Limit
Units
Maximum Propagation
Delay From CO to ~ 1 or ~2
18
27
ns
tpHL. tpLH
Maximum Propagation
Delay From CO to ~3
18
27
ns
tpHL. tpLH
Maximum Propagation
Delay From CO to ~4
20
30
ns
tpHL. tpLH
Maximum Propagation
Delay From A1 or81 to~1
17
26
ns
tpHL. tpLH
Maximum Propagation
Delay From CO to C4
22
32
ns
tpHL. tpLH
Maximum Propagation
Delay From A1 or 81 to C4
22
32
ns
Symbol
Parameter
IpHL. tpLH
Conditions
AC Electrical Characteristics CL =
Symbol
Parameter
Conditions
,
50 pF. tr = tf = 6 ns (unless otherwise specified)
Vee
TA=25'C
Typ
74HC
TA= -40 to 85'C
54HC
TA= -55to 125'C
Units
Guaranteed Limits
tpHL. tpLH
Maximum Propagation
Delay From CO to ~ 1 or ~2
2.0V
4.5V
6.OV
60
21
18
150
30
26
188.
37
32
225
45
39
ns
ns
ns
tpHL. tpLH
Maximum Propagation
Delay From CO 10 ~3
2.0V
4.5V
6.0V
60
21
18
150
30
26
188
37
32
225
45
39
ns
ns
ns
tpHL. tpLH
Maximum Propagation
Delay From CO to ~4
2.0V
4.5V
6.0V
65
24
19
162
34
28
202
43
35
243
51
42
ns
ns
ns
tpHL. tpLH
Maximum Propagation
Delay From A1 or 81 to
2.0V
4.5V
6.0V
60
22
18
150
33
27
188
41
34
225
50
41
ns
ns
ns
~1
tpHL. tpLH
Maximum Propagation
Delay From CO to C4
2.0V
4.5V
6.OV
70
26
21
175
39
32
219
49
40
263
59
46
ns
ns
ns
tpHL. tpLH
Maximum Propagation
Delay From A1 or 81 to C4
2.0V
4.5V
6.OV
70
26
21
175
39
32
219
49
.40
263
59
46
ns
ns
ns
tTHL. tTLH
Maximum Output
Rise and Fall Time
2.0V
4.5V
6.0V
28
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
CIN
Maximum Input
Capacitance
6
10
10
10 .
pF
CPO
Power Dissipation
Capacitance (Note 5)
5.0V
150
Note 5: CPO determines the no load dynamic power consumption. Po = Cpo Vcr!- f+ Icc Vee. and the no load dynamic current consumption.
Is = CPO vce f+lee·
3-243
pF
~
:so
::c
r----------------------------------------------------------------------------,
Truth Table
~
:::E
:::E
....
~
:so
::c
.an
:::E
:::E
c_
Output
Input
When
When
CO=L
CO=H
When
When
C2=L
C2"=H
A11A3 B11 B3 A21A4 B21B4 !'11!.3 !.21!.4 c21c4 !.11 !.3 !.21!.4 c21c4
L
L
L
L
L
L
L
'H
L
L
LL
H
L
L
L
H
L
L
H
H
L
L
H
L
L
L
H
L
L
H
H
L
L
L
H
L
H
H
L
L
L
H
L
L
H
H
H
L
L
L
H
L
H
H
L
L
L
H
H
-H
H
H
L
L
L
H
l
L
H
H
H
L
H
H
H
L
L
L
H
L
L
L
H
L
H
L
H
H
L
L
H
H
H
L
L
L
H
L
H
H
H
L
L
H
L
H
L
H
L
L
H
H
,H
L
H
H
L
H
L
H
H
L
L
H
H
L
H
L
L
L
H
H
H
L
H
L
H
H
H
L
H
L
H
H
H
L
H
H
H
HL
H
H
H
H
H
H
H
H
H = high level, L = low level
Note: Input condRions at AI, 81, A2, 82, and CO are used to determine outputs l: 1 and l:2 and the value of the
Internal carry C2. The values at C2, A3, 83, A4, and 84 are then used to determine outputs l:3, l:4, and C4
3·244
Logic Diagram
'HC283
~
_____
(II)C4
B4
A4....:.;~-L_
B3
A3-'-_......_
B1
A1-_-L_
TL/F/5332-2
3·245
~National
PRELIMINARY
~ Semiconductor
r:: :J
I:
microCMOS
MM54HC298/MM74HC298
Quad 2-lnput Multiplexers With Storage
General Description
These high speed quad two input multiplexers with storage
utilize microCMOS Technology, 3.5 micron silicon gate
P-well CMOS: Both circuits feature high noise immunity and
low power consumption associated with CMOS circuitry,
along with speeds comparable to low power Schottky TIL
logic.
These circuits are controlled by the signals WORD SELECT
and CLOCK. When the WORD SELECT input is taken low
Wore! 1 (A1, B1, C1 and D1) is presented to the inputs of the
flip-flops, and when WORD SELECT Is high Word 2 (A2, B2,
C2 and D2) is presented to the inputs of the flip-flops. The
selected word is clocked to the output terminals on the negative edge of the clock pulse.
All inputs are protected from damage due to static discharge by diodes to Vee and ground.
Features
• Typical propagation delay,
clock to output: 20 ns
• Wide power supply range: 2V -6V
• Low quiescent current
80 ,..A maximum (74HC Series)
• Low input current 1 ,.A maximum
Connection and Logic Diagrams
Dual-In-Une Package
OUTPUTS
DATA
WORD INPUT
,-----------.., •
VCC
QA
Qs
15
116
Qc
14
QD
13
CLOCK SELECT
12
11
10
1
9
-
r-
S2
C1
,
2
A2
3
A1
4
.
S1
5
6
D2
C2
7
Is
D1,
GND
DATA INPUTS
TLlF/5334-2
Top View
TLIF/5334-1
Order Number MM54HC298J or MM74HC298J, N
See NS Package J16A or N16E'
Truth Table
Inputs
Word
Clock QA
Select
L
H
.J,
.J,
X
H
H = High Level (steady state)
L = Low Level (steady state)
Outputs
a1
Qs Qc
QD
b1
c1
d1
b2 c2
d2
QAO Qeo Qeo QDO
a2
X = Don't care (any input, including translUons)
J. = Transition from high to low leval
a1, 82, etc. = The leval of stesdy-state input at A1, A2, etc.
= The level of QAo Oe. etc. entered on the most recent
transition of 1he clock Input.
QAO, Qeo. etc.
3-246
J.
Absolute Maximum Ratings
Operating Conditions
(Notes 1 & 2)
-0.5 to + 7.0V
Supply Voltage (Vee>
DC Input Voltage (VIN)
-1.5toVee+ 1.5V
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
±20mA
Clamp Diode Current {11K. 10K>
±25mA
DC Output Current. per pin (lOUT)
±50mA
DC Vee or GND Current. per pin {Ice>
Storage Temperature Range (TSTG)
- 65'C to + 150'C
Power Dissipation (Po) (Note 3)
500mW
Lead Temp. (Tu (Soldering 10 seconds)
260'C
Supply Voltage (Vee>
DC Input or Output Voltage
(VIN.VOUT)
Operating Temp. Range (TAl
MM74HC
MM54HC
Input Rise or Fall Times
Vcc=2.0V
(tr. ttl
Vee=4.5V
Vee=6.0V
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25'C
Typ
74HC
TA= -40 to 85'C
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN=VIH orVIL
IIOUTI";20",A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
IloUTI";4mA
IIOUTI ,,; 5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = Vee or GND
6.0V
±0.1
±1.0
±1.0
",A
VIN=VIHorVIL
HOUTI ";4.0 rnA
IIOUTI ,,; 5.2 mA
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
VIN = VIH or VIL
IIOUTI";20",A
Maximum Quiescent VIN=VeeorGND 6.0V
80
160
8.0
",A
Supply Current
10UT=0",A
Note 1: Absolute Maximum Ratings are those value. beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mWI'C from 6S'C to 8S'C; ceramic "J" package: -12 mWI"C from 1OO"'C to 125"C.
Note 4: For a power supply of SV ± 10% the worst case oulputvoltages (YOH. and VoLl occur for HC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at Vee = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.l The worst case leakage current (liN. Icc. and
lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
Icc
3-247
•
AC Electrical Characteristics Vcc=5V, TA=25"C,CL =15pF, t,=t,=6ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
tpLH
Propagation Delay Time,
Low-to-!"ligh Level Output
21
32
ns
tpHL
Propagation Delay Time,
High-to-Low Level Output
15
32
ns
tw
Width of Clock Pulse,
High or Low Level
10
16
ns
tSETUP
Setup Time
ns
tHOLO
I
Hold Time
Data
5
20
Word Select
10
20
Data
-2
0
Word Select
-2
0
ns
AC Electrical Characteristics CL =50 pF, t,=t,=6 ns
Symbol
Conditions
Parameter
Vee
54HC174HC
TA = 25°C
Typ
74HC
TA=-40t085"C
54HC
TA= -55 to 125°C
Units
Guaranteed Limits
tpLH
Propagation Delay Time
Low-to-High Level
Output
2.0V
4.5V
6.0V
75
25
20
185
37
31
231
46
39
278
56
47 .
ns
ns
ns
tpHL
Propagation Delay TIme
HigMo-Low Level
Output
2.0V
4.5V
6.0V
75
25
20
185
37
31
231
46
39
278
56
47
ns
ns
ns
tw
Width of Clock Pulse
High or Low Level
2.0V
4.5V
6.0V
35
10
9
80
16
14
100
20
18
120
24
21
ns
ns
ns
lTHL' lTLH
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
90
8
7
75
15
13
95
19
16
110 ,
22
19
ns
ns
ns
tsETUP
Setup Time
2.0V . 35
4.5V
5
6.0V
4
100
20
17
125
25
21
150
30
25
ns
ns
ns
2.0V
4.5V
6.0V
40
10
9
100
20
17
125
25
21
150
30
25
ns
ns
ns
2.0V
4.5V
6.0V
-10
-3
-2
0
0
0
0
0
0
0
0
0
ns
ns
ns
2.0V
4.5V
6.0V
-10
-3
-2
0
0
0
0
0
0
0
0
0
ns
ns
ns
Data
Word
Select
tHOLO
Hold Time
Data
Word
Select
CPO
CIN
Power Dissipation
Capacitance (Note 5)
pF
Maximum Input
capaCitance
pF
5
10
10
10
Note 5: CPO determines the no Iced dynamic power consumption. Po = Cpo Vcr?- + lee Vee. and the no load dynamic current consumption. is = Cpo Vee' +
lee·
3-248
Typical Applications
Figure 1 illustrates a BCD shift register that will shift an entire 4-bit BCD digit in one clock pulse.
Another function that can be implemented with the
MM54HC298/MM74HC298 is a register that can be designed specifically for supporting multiplier or division operations. Figure 2 is an example of a one place/two place shift
register.
When the word select input Is high and the registers are
clocked, the contents of Register 1 is transferred (shifted) to
Register 2, etc. In effect, the BCD digits are shifted one
position. In a~dition, this application retains a parallel-load
capability which means that new BCD data can be entered
into the entire register with one clock pulse. This arrangement can be modified to perform the shifting of binary data
for any number of bit locations.
When word select is low and the register is clocked, the
outputs of the arithmetic/logic units (ALU's) are shifted one
place. When word select is high and the registers are
clocked, the data is shifted two places.
PARALLEL LOAD
I
L
,WI
"--'---
A1
A2
OA
B1
B2 HC21a Oa
C1 REG 1
C2
Oc
D1
D2 CLOCK
CLOCK
I
-
-
ws
ws
A1
A2
OA
B1
B2 HC21a OB
C1 REG 2
C2
LA1
A2
OA
B1
B2 HC2sa Oa
:-..- C1 REG 2
C2
Oc
D1
D2 CLOCK 00
-
Oc
D1
D2 CLOCK OD
00
WORD
SELECT
'J'
'(
-------
'(
---
-------DIGIT 2
DIGIT 1
DIGIT 3
TUF/5334-3
•
FIGURE 1
---- -- -- ALU
181
FO
I I
F1
F2
QA
FO
I
F1
F2
F3
T
A1 A2 81 82 C1 C2 D1 D2
d~'-*
HC298
Os
ALU
181
F3
A1 A2 81 82 C1 C2 D1 D2
roC > CLOCK
---- -- -- -
Oc
ao
I
QA
HC298
Os
WS
Oc
-
QD
WORD
SELECT
CLOCK
TUF/S334-4
FIGURE 2
3-249
~National
\
~ Semiconductor
")
microCMOS
MM54HC299/MM74HC299
8-Bit TRI-STATE® Universal Shift Register
General Description
This S-bit TRI-STATE shift/storage register utilizes microCMOS Technology,.3.5 micron silicon gate P-well CMOS.
Along with the low power consumption and high noise immunitY of standard CMOS integrated circuits, it has the ability to drive 15 LS-TTL loads. This circuit also features operating speeds comparable to the equivalent low power
Schottky device.
permits data applied to the input/output lines to be clocked
into the register. Reading out of the register can be done
while the outputs are enabled in any mode. A direct overriding 'CLEAR input is provided to clear the register whether
the outputs are enabled or dis~bled.
The 54HC174HC logic family is functionally as well as pinout
compatible with the standard 54LS174LS logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to Vee and ground.
The MM54HC299/MM74HC299 features multiplexed inputs/ outputs to achieve full S-bit data handling in a single
20-pin package. Due to the large output drive capability and
TRI-STATE feature, this device is ideally suited for interfacing with bus lines in a bus oriented system.
Features
• Typical operating ,frequency 40 MHz
• Typical propagation delay:, 20 ns' ,
,iii Low quiescent current: SO /LA maximum (74HC)
• High output drive for bus applications
• Low quiescent current: 1 /LA maximum
Two function select inputs and two output control inputs are
used to choose the mode of operation as listed in the function table. Synchronous parallel loading is accomplished by
taking both function select lines SO and S1 high. This places
the TRI-STATE outputs in E\ high impedance state, which
Connection Diagram
Dual-In-Llne Package
SHIFT
Vee ' Sl
Izo
LEFT
SL
19
18
Sl
)~
SL
OH"
17
lIii
H/OH F/OF DIDo BlOB CLOCK
16
15
14
13
12
SR
GlOo E/OE CIOe A/IJA
R
• J,2
~3
SO
11
H/OH FlOF O/OD BlOB CK
SO
G
SHIFT
RIGHT
SR
iii:
l-
CLEAR
.ro
4
5
6
7
8
9
G/Oo E/OE C/Qc AlOA OA' CLEAR GND
ouTPUT
CONTROLS
TOP VIEW
Order Number MM54HC299J or MM74HC299J,N
See NS Package J20A or N20A
3-250
TLlF/52D7-1
o
Operating. Conditions
AJ:lsolute Maximum Ratings (Notes 1 & 2)
Supply Voltage (Vee)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (leo)
DC Output Current, per pin (lOUT)
-0.5 to +7.0V
-1.5toVee+ 1.5V
-0.5 to Vee+0.5V
±20mA
Supply Voltage (Veel
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TA)
..
MM74HC
MM54HC
Input Rise or Fall Times
(tr, til
Vee=2.0V
Vee=4.5V
Vee=6.0V
±25 mA (QA" QH')
±35 mA (others)
±70mA
DC Vee or GND Current, per pin (Ieel
Storage Temperature Range (TSTG)
-65'Cto + 150'C
Power Dissipation (Po) (Note 3)
500mW
Lead Temp. (Tu (Soldering 10 seconds)
260'C
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25'C
Typ
74HC,
TA=-40t085'C
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
VIH
Minimum High Level Input
Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1:5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level Input
Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN=VIH orVIL
!Iour! ,,;20 /LA
QA' & QH' Outputs
A/QA thru H/QH Outputs
VOL
Maximum Low Level
Output Voltage
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
VIN = VIH or VIL
1i0UT! ,,; 4.0 mA
!IOUT!";5.2 mA
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
V
VIN=VIHorVIL
!IOUT!";6.0 mA
!IOUT!";7.8mA
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIH' orVIL
!loUT!";4mA
!IOUT! ";5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
.0.33
0.4
0.4
V
V
V
VIN=VIHorVIL
!loui'!";6mA
!IOUT!Q.8mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
V
VIN = VIH or VIL
!IOUT!";20/LA
.
QA' and QH' Qutputs
A/QA thru H/QH Outputs
liN
Maximum Input Current
VIN=VeeorGND
6.0V
±0.1
±1.0
±1.0
/LA
loz
Maximum TRI-STATE Output
VOUT=VeeOr
GND
G=VIH
6.0V
±0.5
±0.5
±1.0
/LA
Leakage Currrent
Maximum Quiescent Supply
160
8.0
80
VIN=VccorGND 6.0V
/LA
Current
10UT=0/LA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mWI'C from 6S'C to 8S'C; ceramic. "J" package: -12 mWI'C from 1OO'C to 12S·C.
Note 4: For a power supply of SV ±10% the worst-case output voltages (VOH. and VoLl occur fQr HC at 4.SV. Thus the 4.SV values should be used when
designing wHh this supply. Worst-case VIH and VIL occur at Vcc= S.SV and 4.SV respectively. (The VIH value at S.SV is 3.8SV.) The worst·case leakage current (liN.
Icc. and lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
Icc
3-251
•
•
AC Electrical Characteristics Vcc=5V, TA=25'C,tr =tf=6 ns, CL=45 pF '
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
fMAX
Maximum Operating
Frequency
40
25
MHz
tpHL,tpLH
Maximum Propagation
Delay, Clock to QA' or QH'
25
35
ns
tpHL
Maximum Propagation
Delay, Clear to QA' or QH'
39
40
ns
tpHL,tpLH
Maximum Propagation
Delay, Clock to QA -QH
CL =45pF
25
35
ns
tpHL
Maximum Propagation
Delay, Clear to QA -QH
CL =45pF
28
40
ns
tpZL,tpZH
Maximum Enable TIme
,CL =45pF
RL =1 kO
10 _
35
ns
tpHZ,tpLZ
Maximum Disable TIme
CL =5pF
RL =1 kO
18
25
ns
ts
Minimum Setup
Time
Select
20
ns
Data
20
Minimum Hold
Time
Select
0
Data
0
tH
tw
Minimum Pulse Width
tREM
Clear Removal Time
12
ns
20
ns
10
ns
AC Electrical Characteristics CL =50 pF,tr =tf=6 ns unless otherwise specified
Symbol
Parameter
Conditions
Vee
TA=25'C
Typ
fMAX
Maximum Operating Frequency
2.0V
4.5V
6.0V
tpHL,tpLH
Maximum Propagation
Delay, Clock to QA' or QH'
2.0V
4.5V
6.0V
tpHL
Maximum Propagation
Delay, Clear to QA' or QH'
tpHL,tpLH
Maximum Propagation
Delay, Clock to QA-QH
,
tpHL
Maximum Propagation
Delay, Clear to QA -QH
-
74HC
TA=-40to85'C
I
54HC
TA=-55to125'C
,
Units
Guaranteed Limits
5
25
29
4
20
23
3.5
18
20
MHz
MHz
MHz
15
27
25
170 '
38 •
35
210
48
44
240
54
49
ns
ns
ns
2.0V
4.5V
6.0V
70
30
26
200
38
250
55
46
280
62
52
ns
ns
ns
CL =50pF
CL=150pF
2.0V
2.0V
65
100
170
206
210
260
240
295
ns
ns
CL ";'50pF
CL=150pF
4.5V
4.5V
27
34
38
46
48
57
54
66
ns
ns
CL =50pF
CL=150pF
6.0V
6.0V
25
31
35
39
44
49
49
55
ns
ns
CL =50pF
CL=150pF
2.0V
2.0V
70
110
200
236
250
295
280
325
ns
ns
CL =50 pF
CL =150pF
4.5V
4~5V
30
37
44
52
55
65
62
75
ns
ns
CL =50pF
CL =150pF
6.0V
6.0V
26
32
38
46
46
57
52
64
ns
ns
3-252
44
AC Electrical Characteristic (Continued) CL = 50 pF, tr= tf= 6 ns unless otherwise specified
Symbol
Parameter
Conditions
Vee
TA=25°C
Typ
tpZH, tpZL MaximumQutput Enable
74HC
54HC
TA= -40 to 85°C TA= -55to 125"C Units
Guaranteed Limits
RL =1 kO
CL =50 pF
CL =150 pF
2.0V
2.0V
70
90
160
220
200
275
225
310
ns
ns
CL =50pF
CL =150 pF
4.5V
4.5V
22
30
32
44
40
55
45
62
ns
ns
CL =50 pF
CL =150 pF
6.0V
6.0V
19
24
28
47
34
47
38
51
ns
ns
2.0V
4.5V
6.0V
70
22
19
160
32
28
200
40
34
225
45
38
ns
ns
ns
140
28
25
ns
ns
ns
tpHZ, tpLZ Maximum Output Disable Time RL =1 kO
CL=50pF
ts
Minimum Setup Time,
Data Select SL or SR
2.0V
4.5V
6.0V
100
20
17
125
25
21
tH
Minimum Hold Time,
Data Select SL or SR
2.0V
4.5V
6.0V
0
0
0
0
0
0
0
0
0
ns
ns
ns
tREM
Minimum Clear Removal Time
2.0V
4.5V
6.0V
10
10
10
10
10
10
10
10
10
ns
ns
ns
tw
Minimum Pulse Width,
Clock and Clear
2.0V
4.5V
6.0V
100
20
17
125
25
21
140
28
25
ns
ns
ns
t,., tf
Maximum Input Rise
and Fal/Time
500
500
500
ns
60
12
10
75
15
13
90
18
15
ns
ns
ns
tTHL, tTLH Maximum Output Rise
and Fal/ Time, Clock
2.0V
4.5V
6.0V
CPO
Power Dissipation
Capacitance
CIN
Maximum Input Capacitance
Capacitance
Outputs Enabled
Outputs Disabled
pF
pF
240
110
5
10
10
pF
10
Maximum TRI-STATE
15
20
20
pF
20
Output Capacitance
Nole 5: CPO determines the no load dynamic power consumption, Po=Cpo Vrxl- f+lee Vee, and the no load dynamic current consumption,
Is=Cpo Vee f+lee·
COUT
Function Table
Inputs
Mode
Function
Clear Select
S1
Output
Control
Clock Serial A/OA B/OB C/Oe D/OD E/OE F/OF G/OG H/OH OA' Ow
SO G1t G2t
X
L
L
X
Clear
L
L
Hold
H
H
L
L
X
Shift Right
H
H
Shift Left
Load
L
L
L
L
X
L
L
L
L
L
L
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
H
X
X
outputs
Inputs/Outputs
SL SR
X
X
X
X
X
X
LorH X
X
i
X
i
i
i
i
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
QAO'
QAO
QBO
QBO
Qco
Qce
QDO
QDO
QEO
QEO
QFO
QFO
QGO
QGO
QHO
QHO
H
H
H
L
QAn
QAn
QBn
QBn
QCn
QCn
QDn
QDn
QEn
QEn
QFn
QFn
QGn
QGn
H
L
QGN
QGN
QBn
QBn
QCn
QCn
QDn
QDn
QEn
'QEn
QGn
QGn
QHn
QHn
H
H
QBn
QBn
H
a
b
c
d
QFn
QFn
e
9
h
a
h
X
X
X X
H
L
f
L
L
L
L
QAO QHO
QAO QHO
L
tWhen one or both controls are high the eight inpuVoulput terminals are disabled to the high·impedance state; however, sequential operation or clearing of
the register Is not affected.
3-253
•
C»
C»
N
o
:c
.-
r-------------------------------------------------------------------------------~
Logic Diagram
r:==:
....
::IE
::IE
.....
~
o
:c
:;
::IE
::IE
ClK12
(>0
ClR9
~
SHIFT 11
RIGHT
SR
....-'..--
IEMUX
lO
~
• R
--
H
SR
01--
I
I
ClK
m
D
O~~
ti
Sl
H
m
ClK
0
I--
a
D
[
r-t>~
SR
7
I I I
DEMUX
LD
.....
""-r.-
R
Sl
.....
13
""-r.-
R
B/O,
I I I
H
m
CLK
0
DEMUX
'-SR
~
H
.....
A
~()1L()J
B
8R
~
D
9J
~
SR
;01 L
l~
LD
lD
~
Jl
SR
DETAil OF DEMUX
a~
""-r.-
R
~ c/ae
I I I
H
m
ClK
0
-0
Sl
a~
t!!- D/a.
a~
.
r.-
R
I I I
H
DEMUX
--
D
Sl
DEMUX
0
C
lD
01--
m
ClK
of-- -
D
a
a
Sl
R
.....
.",,-
5
Ellie
!o.,
I I I
H
m
CLK
0
2D
DEMUX
-Vee
1D
-GNO
SO
1
.....
~
1 19
......
.....
I A Jo--
I .....~
t ...
P,
SR
B
0
f-- 0
a~
Sl
~ ....
R
I I I
I
H
eli
CLK
GDEMUX
---rc\c
~
lD
0-
D
Sl
i~P- ..!. Glilo
R
t....
i'oo.
,
.1!. FlO.
D
,..-
1 I I
I
SR
I
2
3
]
I
H
eli
CLK
~.
0
~
)0-
f-L...--
DEMUX
lD
~
Sl
01-- D
R
I
11
\
..-.
h...
""'r.-
17
16
a.'
H/a.
.....
SHIFT 18
LEFT
..-
TLlF/5207-2
3-254
.
~ Semiconductor
~National'
r'\
)
microCMOS
MM54HC354/MM74HC3541
MM54HC356/MM74HC356
a-Channel TRI-STA,TE® Multiplexers with Latches
General Description
The MM54HC354/MM74HC354 and MM54HC356/
MM74HC356 utilize microCMOS Technology, 3.5 micron silicon gate P-well CMOS. They exhibit the high noise immunity and low power dissipation of standard CMOS integrated
circuits, along with the ability to drive 15 LS-TTL loads. Due
to the large output drive capability and the TRI-STATE feature, these devices are ideally suited for interfacing with bus
lines in a bus organized system.
These data selectors/multiplexers contain full on-chip binary decoding to select one of eight data sources. The data
select address is stored in transparent latches that are enabled by a low level address on pin 11, SC. Data on the 8
input lines is stored in a parallel input! output register which
in the MM54HC354/MM74HC354 is composed of 8 transparent latches enabled by a low level on pin 9, DC, and in
the MM54HC356/MM74HC356 is composed of 8 edge-triggered flip-flops, clocked by a low to high transition on pin 9,
ClK. Both true (Y) and complementary (W) TRI-STATE outputs are available on both devices.
'
The 54HC/74HC logic family is functionally as well as pinout compatible with the standard 54LS174LS-TTL logic family. All inputs are protected from damage due to static discharge by internal diode clamps to Vee and ground.
Features
• Transparent latches on data select inputs
• Choice of data registers:
Transparent ('354)
Edge-triggered ('356)
• TRI-STATE complementary outputs with fanout
of 15 LS-TTL loads
• Typical propagation delay:
Data to output (,354): 32 ns
Clock to output (,346): 35 ns •
• Wide power supply range: 2V-6V
II Low quiescent supply current: 80 poA maximum
• Low input current: 1 poA maximum
Connection Diagram
Dual-In-Line Package
OUTPUT
ENABLES
OUTPUTS
Vee
Y
W
63
iI2
SELECT
iii
SO
Sl
(SC)
SELECT
82 CONTROL
11
10
~
~
~
~
~
H
m
~
om
~
- - - - - - _ - - - - - - CONTROL!
DATA
CLOCK
INPUTS
(ire/ClK)
TL/F/5208-1
Top View
Order Number MM54HC354J, MM54HC356J,
MM74HC354J,N or MM74HC356J,N
See NS Package J20A or N20A
3-255
•
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
Supply Voltage (Vee)
-0.5Vto +7.0V
DC Input Voltage (VIN)
-1.5V to Vee + 1.5V
DC Output Voltage (VOUT)
-0.5Vto Vee+0.5V
±20mA
Clamp Diode Current (leo)
±35mA
DC Output Current. per pin (lOUT)
±70mA
DC Vee or GND Current. per pin (Icc>
Storage Temperature Range (TSTG)
-65'C to + 150'C
Power Dissipation (Po) (Note 3)
500mW
Lead Temp. (TLl
(Soldering 10 seconds)
260'C
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
Vee=2.0V
(tr. tf)
Vee=4:5V
Vee=6.0V
Min
2
0
Max
6'
Vee
Units
V
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
.DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=2S'C
Typ
VIH
Minimum High Level Input
Voltage
VIL
Maximum Low Level Input
Voltage
VOH
Minimum High Level Output
Voltage
,
VIN = VIH or VIL
IIOUTI:<>20 ".A
MaxilT)um Low Level Output.
Voltage
Guaranteed Limits
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2\
1.5
3.15
4.2.
V
V
V
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9·
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN =VIH or VIL
IIOUTI:<>6.0mA
IIOUTI:<>7.8 mA
4.5V
6.0V
0.2
0.2
0:26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VeeorGND
VIN = VIH or VIL
IIOUTI :<> 6.0 mA
IIOUTI:<>7.8mA
VOL
74HC
S4HC
TA=-40to8S'C TA=-SSto12S'C Units
VIN=Vn-l°rVIL
IIOUTI<20 ".A
I
~
liN
Maximum Input Current
6.0V
±0.1
±1.0
±1.0
".A
loz
Maximum TRI-STATE Output VOUT=VeeorGND
Leakage Current
6.0V
G1=VIH
±0.5
±5.0
±10
".A ..
Maximum Quiescent Supply
80
160
6.0V
8.0
VIN=Vee or GND
".A
Current
10UT=0".A
Note 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specHied all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N".package: -12 mW/oC from ~5"C to 85°C; ceramic "J" package: -12 mW/oC from 100"C to 125°C.
Note 4: For a power supply of 5V ± 10% the worst case output voltages (VOH. and VoLl occur for HC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case V,H and V,L occur at Vcc=5.5V and 4.5V respectively. (The V,H value at5.5V Is 3.85V.) The worst csseleakage current (liN. ICC. and
lozl occur for CMOS at the higher voltage and so the 8.0V values should be used.
Icc
t
3-256
AC Electrical Characteristics Vcc= 5V, TA = 25'C, tr=tf= 6 ns
MM54HC354/MM74HC354
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
tpHL, tpLH
Maximum Propagation
Delay DO-D7 to either Output
CL =45 pF
32
46
ns
tpHL, tpLH
Maximum Propagation
Delay DC to either Output
CL =45pF
38
53
ns
tpHL, tpLH
Maximum Propagation
Delay SO-S2 to either Output
CL =45 pF
40
56
ns
tpHL, tpLH
Maximum Propagation
Delay SC to either Output
CL =45pF
42
58
ns
tpZH, tPZL
Maximum Output Enable Time
RL =1 kO
CL =45pF
17
24
ns
tpHZ, tpLZ
Maximum Output Disable Time
RL =1 kO
CL =5 pF
23
32
ns
Is
Minimum Setup Time
00-07 to DC, SO-S2 to SC
3
10
ns
tH
Minimum Hold Time
00-07 to ~C, SO-S2 to SC
0
5
ns
tw
Minimum Pulse Width, SC or DC
10
15
ns
Conditions
Typ
Guaranteed
Umit
Units
MM54HC356/MM74HC356
Symbol
Parameter
tpHL, tpLH
Maximum Propagation
Delay ClK to either Output
CL =45 pF
35
50
ns
tpHL, tpLH
Maximum Propagation
Delay SO-S2 to either Output
CL =45pF
40
56
ns
tpHL, tpLH
Maximum Propagation
Delay SC to either Output
CL =45pF
42
58
ns
tpZH, tpZL
Maximum Output Enable Time
RL =1 kO
CL = 45.pF
17
24
ns
tPHZ, tpLZ
Maximum Output Disable Time
RL =1 kO
CL=5pF
23
32
ns
Is
Minimum Setup Time
\
00-07 to ClK, SO-S2 to SC
3
10
ns
tH
Minimum Hold TIme
00-D7 to ClK, SO-S2 to SC
0
5
ns
Minimum Pulse Width, SC or ClK
10
15
ns
tw
,
AC Electrical Characteristics MM54HC354/MM74HC354 (Continued)
VCC=2.0-6.0V. CL =50 pF. t r =tf=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=25"C
Typ
tpHL. tpLH
tpHL. tpLH
Maximum Propagation
Delay 00-07 to either Output
Maximum Propagation
Delay DC to either Output
tpHL. tpLH
tPZH. tPZL
Maximum Propagation
Delay SO-52 to either Output
Maximum Propagation
Delay SC to either Output
Maximum Output Enable Time
I
tpHZ. tpLZ
Maximum Output Disable Time
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
CL =50 pF
CL=150pF
2.0V
2.0V
90
100
235
275
294
344
352
412
ns
ns
CL =50 pF
CL=150pF
4.5V
4.5V
35
40
47
55
59
68
70
83
ns
ns
CL =50 pF
CL=150pF
6.0V
6.0V
26
32
40
46
50
58
ns
ns
CL =50pF
CL=150pF
2.0V
2.0V
115
125
270
310
337
387
60
69
,405
465
54
62
68
78
82
93
ns
ns
CL =50pF
CL =150 pF
tpHL. tpLH
74HC
TA=-40t085"C
'4.5V 40
4.5V . 46
ns
ns
CL =50pF
CL =150 pF
6.0V
6.0V
32
38
46
52
58
66
69
78
ns
ns
CL =50pF
CL =150 pF
2.0V
2.0V
120
130
285
325
356
406
427
488
ns
ns
CL =50pF
CL =150 pF
4.5V
4.5V
42
50
57
65
71
81
86
97
ns
ns
CL =50pF
CL=150pF
6.0V
6.0V
34
40
48
55
60
69
72
82
ns
'ns
CL =50pF
CL =150 pF
2.0V
2.0V
120
110
300
340
375
425
450
510
ns
ns
CL =50pF
CL =150 pF
4.5V
4.5V
45
52
60
68
75
85
90
102
CL =50pF
CL =150 pF
6.0V
6.0V
36
42
51
58
64
72
77
87
ns
ns
. ns
ns
RL=1 kO
CL =50pF
CL =150pF
2.0V
2.0V
50
60
125
165
156
206'
188
248
ns
ns
CL =50pF
CL =150 pF
4.5V
4.5V
18
25
25
33
31
41
38
49
ns
ns
CL =50 pF
CL =150pF
6.0V
6.0V
15
21
21
28
26
35
32
42
ns
ns
RL =1 kO
CL =50pF
2.0V
4.5V
6.0V
68
24
20
165
33
28
206
40
35
248
46
42
,
ns
ns
ns
Is
Minimum Setup Time
00-07 to DC. SO-52 to SC
2.0V
4.5V
6.0V
6
3
3
50
10
10
60
13
13
75
15
15
ns
ns
ns
tH
Minimum Hold Time
00-07 to DC. SO-52 to SC
2.0V
4.5V
6.0V
0
0
0
5
5
5
5
5
5
5
5
5
ns
ns
ns
tw
Minimum Pulse Width
SCorDC
2.0V
4.5V
6.0V
30
10
10
80
16
15
100
20
18
120
27
20
ns
ns
ns
trLH. trHL
Maximum Output Rise
anti Fall Time
CL =50pF
2.0V
4.5V
6.0V
25
7
6
60
12
10
75
15
13
90
18 '
15
ns
ns
ns
CPO
Power Dissipation Capacitance
(Note 5)
(per package)
Active
TRI-STATE
CIN
pF
pF
150
50
Maximum Input Capacitance
5
Maximum Output Capacitance
15
10
10
10
pF
pF
20
Note 5: CPO determines the no load dynamic power conSllmption, Po= CPO vee? 1+ lee Vee. and the no load dynamic current conSllmptiQn, IS = CPO Vee 1+ lee,
COUT
3-258
20
20
,
AC Electrical Characteristics MM54HC356/MM74HC356 (Continued)
Vcc=2.0-6.0V, CL =50 pF, t r =t,=6 ns (unless otherwise specified) ,
Symbol
Parameter
Conditions
Vee
TA=25°C
Typ
,tpHL, tpLH
tpHL, tpLH
tpHL, tpLH
tpZH, tPZL
Maximum Propagation
Delay ClK to either Output
Maximum Propagation
Delay SO-52 to either Output
Maximum Propagation
Delay SC to either Output
Maximum Output Enable Time
74HC
TA= -40 to 85°C
54HC
TA= -55to 125°C
Units
Guaranteed Limits
CL =50pF
CL=150pF
2.0V
2.0V
100
110
225
295
318
369
338
442
ns
ns
CL =50pF
CL =150 pF
4.5V
4.5V
36
42
51
59
63
73
76
90
ns
ns
CL =50pF
CL =150 pF
6.0V
6.0V
28
34
43
50
53
63
64
75
ns
ns
CL =50 pF
CL =150 pF
2.0V
2.0V
120
130
285
325
356
406
427
488
ns
ns
CL=50 pF
CL=150pF
4.5V
4.5V
42
50
57
65
71
81
86
97
ns
ns
CL =50pF
CL =150 pF
6.0V
6.0V
34
40
48
55
60
69
72
82
ns
ns
CL =50pF
CL=150pF
2.0V
2.0V
120
110
300
340
375
425
450
510
ns
ns
CL =50pF
CL=150pF'
4.5V
4.5V
45
52
60
68
75
85
90
102
ns
ns
CL =50pF
CL =150 pF
6.0V
6.0V
36
42
51
58
64
72
77
87
ns
ns
RL =1 kG
CL =50pF
CL =150 pF
2.0V
2.0V
50
60
125
165
156
206
188
248
ns
ns
CL =50pF
CL =150 pF
4.5V
4.5V
18
25
25
33
31
41
38
49
ns
ns
CL =50pF
CL =150 pF
6.0V
6.0V
15
21
21
28
26
35
32
42
ns
ns
RL=1 kG
CL =50pF
2.0V
4.5V
6.0V
68
24
20
165
33
28
206
41
35
248
49
42
ns
ns
ns
tpHZ, tpLZ
Maximum Output Disable Time
ts
Minimum Setup TIme
00-07 to ClK, SO-52 to SC
2.0V
4.5V
6.0V
6
3
3
50
10
10
50
' 10
10
50
10
10
ns
ns
ns
tH
Minimum Hold Time
00-07 to ClK, SO-52 to SC
2.0V
4.5V
6.0V
0
0
0
5
5
5
5
5
5
5
5
5
ns
ns
ns
tw
Minimum Pulse Width
SCto ClK
2.0V
4.5V
6.0V
30
10
10
80
16
15
100
20
18
120
24
20
ns
ns
ns
t r, tf
Maximum Clock Input
Rise and Fall Time
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
60
12
10
75
15
13
90
18
15
ns
ns
ns
,
tTLH, ITHL
Maximum Output Rise
and Fall Time
CL =50pF
CPO
Power Dissipation Capacitance
(Note 5)
(per package)
Active
TRI-STATE
2.0V
25
4.5V ' 7
6.0V
6
150
50
pF
pF
CIN
Maximum Input Capacitance
5
10
10
10
pF
COUT
Maximum Output Capacitance
15
20
20
20
pF
Note 5: CPO determines the no load dynamic power consumption. Po=Cpo Vccl- f+lee Vee. and the no load dynamic current consumption.ls=Cpo Vee f+lee.
3-259
•
Function Table
Inputs
8electt·
Data
Control
'HC354
Clock
'HC356
Output
Enables
Outputs
81
S2
SO
DC
ClK
G1
G2
G3
W
Y
X
X
X
X
X
X
X
X
X
H
X
X
X
H
X
X
L
L
L
l
L
L.
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
t
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
l
L
l
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
H
H
H
H
H
Z
Z
Z
50
50n
51
01n
52
02n
03
03 n
04
04 n
05
55 n
06
56 n
07
57 n
:z
X
X
X
X
X
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
HorL
t
HorL
t
HorL
t
HorL
t
HorL
t
HorL
t
HorL
t
HorL
i;
H
H
H
H
H
H
H
H
/H
H
Z
Z
00
O~n
01
01 n'
02
02n
03
03 n
04
04 n
05
05 n
06
06 n
07
07 n
=: high level (steady state)
H
L=
X=
Z=
t
low level (steady state)
irrelevant (any input, Including transitions!
high-impedance state (off state)
= transition from low to high leyel
DO ... 07 = the level steady-state Inputs at inputs DO through 07, respectively, at the time of the low-tohigh clock transition in the case of 'HC356
DOn .. ~ 07n = the level of steady state Inputs at inputs DO through 07, raspectively, before the most
recent low-to-high transition of data control or clock.
tThis column shows the input address sat-up with Slliow.
3-260
Logic Diagram
'tfC354,
D7.;.1_ _-4_-I
TLiF/5208-2
3-261
to
In
o
r----------------------------------------------------------------------------,
Logic Diagram
:::I:
~
to-
'HC356
:E
:E
......
3l
o
CO)
:::I:
~
In
:E
:E
;;:
In
CO)
o
:::I:
~
to-
:E
:E
......
~
~
o
:::I:
~
In
:E
:E
D3 .:5____~-_I
D4...;4_ _~-_I
-+_-1
05.:3_ _
05 .:2~_~1-_I
Dl.;.l_ _~I-_I
TL/F/5208-~
3-262
~National
~ Semiconductor
-;
\
microCMOS
MM54HC365/MM74HC365 Hex TRI-STATE® Buffer
MM54HC366/MM74HC366 Inverting HexTRI-STATE Buffer
MM54HC367/MM74HC367 Hex TRI-STATE Buffer
MM54HC368/MM7 4HC368 Inverting Hex TRI-STATE Buffer
General Description
These TRI-STATE buffers are general purpose high speed
inverting and non-inverting buffers that utilize microCMOS Technology, 3.5 micron silicon gate P-well CMOS.
They have high drive current outputs which enable high
speed operation even when driving large bus capacitances.
These circuits possess the low power dissipation of CMOS
circuitry, yet have speeds comparable to low power
Schottky TTL circuits. All 4 circuits are capable of driving up
to 15 low power Schottky inputs.
The MM54174HC366 and the MM54174HC368 are inverting
buffers, where as the MM54/74HC365 and the MM54/
74HC367 are non-inverting buffers. The MM54174HC365
and the MM54174HC366 have two TRI-STATE control inputs (G1 and G2) which are NORed together to control all
Connection Diagrams
_
~
16
~
15
M
M
14
n
~
13
~
M
12
n
six gates. The MM54/74HC367 and the MM54174HC368
also have two output enables, but one enable (G1) controls
4 'gates and the other (G2) controls the remaining 2 gates.
All inputs are protected from damage due to static discharge by diodes to Vee and ground.
Features
•
•
•
•
•
Dual-In-Line Packages/Top Views
~
11
M
A4
Vee
Y4
16
10
~
00
TLlF/S209-1
Order Number MM54HC365J, MM74HC365J, N
See NS Package J16A or N16E
_
~
~
Gi
U
M
M
~
~
M
U
Typical propagation delay: 15 ns
Wide operating voltage range: 2V-6V
Low input current: 1 /LA maximum
Low quiescent current: 80 /LA maximum (74 Series)
Output drive capability: 15 LS-TTL loads
~
11
A4
Gi
~
15
Y6
M
14
n
M
~
Y5
M
13
12
n
A4
11
M
Y4
10
~
00
TLlF/S209-2
Order Number MM54HC366J, MM74HC366J, N
See NS Package J16A or N16E
_
"
~
~
W
~
AI
TL/F/S209-3
Order Number MM54HC367J, MM74HC367J, N
See NS Package J16A or N16E
M
U
M
M
n
~
M
U
~
~
n
~
11-
~
A4
"
W
~
00
, TLlF/S209-4
Order Number MM54HC368J, MM74HC368J, N
See NS Package J16A or N16E
3-263
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
-0.5 to +7.0V
Supply Voltage (Vee)
DC Input Voltage (VIN)
-,1.5 to Vec+ 1.5V
Supply Voltage (Vec)
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA)
'MM74HC
MM54HC
Clamp Diode Current (11K. 10K>
±20mA
DC Output Current. per pin (lOUT)
±35mA
DC Vee or GND Current. per pin (Ieel
±70mA
-65·Cto + 150·C
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
Lead Temp. (TLl (Soldering 10 seconds)
Min
2
Max
6
Units
V
0
Vee
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
(t,. tf)
Vee=2.0V
Vee=4.5V
Vee=6.0V
500mW
,260·C
DC Electrical Characteristics (Note 4)
Symbol
Vee
Conditions
Parameter
TA=25·C
Typ
\
74HC
54HC
TA= -:40 to 85·C TA=-55t0125·C
Units
Guaranteed Limits
VIH
Minimum High Level Input
Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level input
Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level Output
Voltage
2.0V '2.0
4.5V 4.5
f).OV 6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIHorVIL
IloUTIS:6.0 mA
IIOUTI S:7.8 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VeeorGND
VIN = VIH or VIL
IIOUTIS:20 /LA
VIN = VIH or VIL
IIOUTIS:6.0 mA
IIOUTIs:7.8 mA
VOL
Maximum Low Level Output
Voltage
VIN = VIH or VIL
Ii0UTI S:20 /LA
~
,
liN
Maximum Input Current
6.0V
±0.1
±1.0
±1.0
",A
10Z
Maximum TRI-STATE Output VOUT=Vceor GND 6.0V
, G=VIH·
,
Leakage Current
±0.5
±5.0
±10
",A
Icc
Maximum Quiescent Supply
Current
8.0
80
160
",A
VIN = Vee or GND
IOUT=O",A
6.0V
Note 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground. '
Note 3: Power Dissipation temperature derati~g - plastiC "N" package: -12 mWI"C from 65'C to 85'C; ceramic" J" package: -12 mWI"C from 1OO"C to 125'C.
Note 4: For a power supply of 5V ± 10% the worst case output voltages (VoH. and Vou occur for HC at4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at Vcc=5.5V and 4.5V respectively, (The VIH value at5.5V is 3,85V,) The worst case leakage current (liN. loe. and
10Z> occur for CMOS at the higher voltage and so the 6,OV values should be used.
3-264 •
AC Electrical Characteristics MM54HC365/MM74HC365
Vcc=5V. TA=25'C. tr =t,=6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
tPHL. tpLH
Maximum Propagation
Delay
CL =45pF
15
22
ns
tpZH. tpZL
Maximum Output Enable
Time
RL=1 kO
CL =45pF
29
40
ns
tpHZ. tpt.Z
Maximum Output Disable
Time
RL=1 kO
CL =5pF
25
36
ns
\
-
AC Electrical Characteristics MM54HC365/MM74HC365
Vcc=2.0-6.0V. CL =50 pF. t r =t,=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
74HC
TA= -40 to 85'C
TA=25'C
Typ
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
tpHL. tpLH
Maximum Propagation
Delay
CL =50pF
CL =150pF
CL =50pF
CL =150 pF
CL =50pF
CL=150pF
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
35
45
14
17
11
15
105
135
24
29
19
24
130
166
30
36
24
30
150
205
36
45
26
36
ns
ns
ns
ns
ns
ns
tPZH. tPZL
Maximum Output Enable
Time
RL =1 kO
CL =50 pF
CL =150 pF
CL=50 pF
CL =150 pF
CL =50pF
CL=150pF
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
90
98
31
36
25
29
230
245
44
53
35
41
267
306
55
66
43
51
345
367
66
60
52
62
ns
ns
ns
ns
ns
ns
tPHZ. tpLZ
Maximum Output Disable
Time
RL =1 kO
CL =50pF
2.0V
4.5V
6.0V
58
26
22
175
44
37
218
55
46
260
66
55
ns
ns
ns
trHL. tTLH
Maximum Output Rise
and Fall Time
CL =50pF
2.0V
4.5V
6.0V
25
7
6
60
12
10
75
15
13
90
18
15
ns
ns
ns
CPD
Power Dissipation
Capacitance (Note 5)
Any Enabled
A Input
Any Disabled
A Input
-
45
pF
8
pF
CIN
Maximum Input
Capacitance
5
10
10
10
pF
COUT
Maximum Output
Capacitance
10
20
20
20
pF
Note 5: CPO determines the no load dynamic power consumption. Po =Cpo Vcr;2
,+ Icc Vee.
and the no load dynamic current consumption. Is = CPO Vcc 1+ Icc.
Truth Table
'HC365
Inputs
Output
G2
A
Y
H
X
X
H
L
L
X
X
Z
Z
H
L
H
L
G1
L
L
AC Electrical Characteristics
(Continued) MM54HC366/MM74HC366
Vcc=5V. TA=25°C. tr=tj=6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
tpHL. tpLH
Maximum Propagation
Delay
CL =45pF
12
·18
ns
tPZL. tPZH
Maximum Output Enable
Time
RL =1 kO
CL =45 pF
29
40
ns
tpHZ. tpLZ
Maximum Output Disable
Time
RL =1 kO
CL =5pF
25
36
ns
AC Electrical Characteristics
MM54HC366/MM74HC366
Vcc=2.0-6.0V. CL =50 pF. tr=tj=6 ns !unless otherwise specified)
Symbol
Parameter
Conditions
Vcc
74HC
TA= -40 to 85"C
TA=25"C
Typ
54HC
TA= -55to 125"C
Units
Guaranteed Limits
tpHL. tpLH
Maximum Propagation
Delay
CL=50pF
CL=150pF
CL =50pF
CL=150pF
CL =50 pF
CL =150 pF
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
33
43
12
16
10
14
82
107
19
26
16
22
102
134
24
32
20
27
125
160
30
39
24
33
ns
ns
ns
ns
ns
ns
tPZH. tPZL
Maximum Output Enable
Time
RL =1 kO
CL =50pF
CL=150pF
CL =50pF
CL=150pF
CL =50pF
CL=150pF
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
90
98
31
38
25
29
230
245
44
53
35
41
287
306
55
66
43
51
345
367
66
80
52
62
ns
ns
ns
ns
ns
ns
ns
I
tpHZ. tpLZ
Maximum Output Disable
Time
RL =1 kO
CL =50pF
2.0V
4.5V
6.0V
58
26
22
175
44
37
218
55
46
260
66
55
ns
ns
ns
tTHL. tTLH
Maximum Output Rise
and Fall Time
CL =50pF
2.0V
4.5V
6.0V
25
7
6
60
12
10
75
15
13
90
18
15
ns
ns
ns
CPO
Power Dissipation
Capacitance (Note 5)
Any Enabled
A Input
Any Disabled
A Input
45
pF
6
pF
CIN
Maximum Input
Capacitance
5
10
10
10
pF
COUT
Maximum Output
Capacitance
10
20
20
20
pF
Note 5: CPO determines the no load dynamic' power consumption. Po = Cpo Vee! 1+ Icc Vee. and the no load dynamic current consumption, IS = CPO Vee f+ Icc;.
Truth Table
'HC366
Inputs
Output
G2
A
Y
H
X
X
H
X
X
Z
Z
L
L
L.
L
H
L
L
H
G1
.
3-266
AC Electrical Characteristics
(Continued) MM54HC367/MM74HC367
Vcc=5V. TA=25'C. t,=tf=6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
tpHL. tpLH
Maximum Propagation
Delay
CL =45pF
13
22
ns
tpZL. tpZH
Maximum Output Enable
Time
RL =1 kO
CL =45 pF
23
37
ns
tpHZ. tpLZ
Maximum Output Disable
Time
RL =1 kO
CL =5pF
25
33
ns
AC Electrical Characteristics
MM54HC367/MM74HC367
Vcc=2.0-6.0V. CL =50 pF. t,=tf=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=25'C
Typ
74HC
TA= -40 to 85'C
54HC
TA = -55 to 125'C
Units
Guaranteed Limits
tpHL. tpLH
Maximum Propagation
Delay
CL =50pF
CL=150pF
CL =50 pF
CL =150pF
CL =50pF
CL =150pF
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
35
45
14
17
11
15
105
135
24
29
19
24 .
130
168
30'
36
24
30
150
205
36
45
28
36
ns
ns
ns
ns
ns
ns
tpZH. tpzL
Maximum Output Enable
Time
RL =1 kO
CL =50pF
CL =150 pF
CL =50pF
CL=150pF
CL =50pF
CL=150pF
2.0V
2.0V
4.5V
4.5V
6.01i
6.0V
69
75
24
29
22
26
172
187
38
46
35
42
216
233
47
57
43
52
250
280
57
69
52
63
ns
ns
ns
ns
ns
ns
ns
tPHZ, tpLZ
Maximum Output Disable
Time
RL =1 kO
CL =50pF
2.0V
4.5V
6.0V
47
22
19
117
35
31
146
44
39
220
52
46
ns
ns
ns
tTHL. tTLH
Maximum Output Rise
and Fall Time
CL =50 pF
2.0V
4.5V
6.0V
25
7
6
60
12
10
75
15
13
90
18
15
ns
ns"
ns
CPD
Power Dissipation
Capacitance (Note ~)
Any Enabled
A Input
Any Disabled
A Input
CIN
COUT
Maximum Input
Capacitance
45
pF
8
pF
5
10
10
10
pF
10
20
20
20
pF
-
Maximum Output
Capacitance
Note 5: CPO determines the no load dynamic power consumption. Po = Cpo vcdl , + lee Vee. and the no load dynamic current consumption. Is = Cpo vcc , + Icc.
:
Truth Table
'HC367
Inputs
Output
G
A.
Y
H
L
X
H
Z
H
L
L
L
3-267
AC Electrical Characteristics (Continued) MM54HC368/MM74HC368
Vcc=5V. TA=25'C. t,.=t,=6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
tpHL. tpLH
Maximum Propagation
Delay
CL =45pF
11
18
ns
tpZL. tpZH
Maximum Output Enable
Time
RL =1 kfl
CL =45pF
23
37
ns
tPHZ. tpLZ
Maximum Output Disable
Time
RL =1 kfl
CL =5pF
19
33
ns
AC Electrical Characteristics MM5.4HC368/MM74HC368
Vcc=2.0-6.0V. CL =50 pF. t r =t,=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=25"C
Typ
74HC
TA= -40 to 85'C.
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
tpHL. tpLH
Maximum Propagation
Delay
CL =50pF
CL=150pF
CL =50 pF
CL=150pF
CL =50pF
CL=150pF
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
33
43
12
16
10
14
82
107
19
26
16
22
102
134
24
32
20
27
125
160
30
39
24
33
ns
ns
ns
ns
ns
ns
tPZH. tPZL
Maximum Output Enable
Time
RL =1 kfl
CL =50pF
CL=150pF
CL =50pF
CL=150pF
CL =50 pF
CL=150pF
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
69
75
24
29
22
26
172
187
38
46
35
42
216
233
47
57
43
52
250
280
57
69
52
63
ns
ns
ns
ns
ns
ns
ns
tpHZ. tpLZ
Maximum OutputDisable
Time
RLO" 1 kfl
CL =50 pF
2.0V
4.5V
6.0V
47
22
19
117
35
31
146
44
39
220
52
46
ns
ns
ns
tTHL.lTui
Maximum Output Rise
and Fall Time
CL =50'pF
2.0V
4.5V
6.0V
25
7
6
60
12
10
75·
15
13
90
18
15
ns
ns
ns
CPO
Power Dissipation
Capacitance (Note 5)
Any Enabled
A Input
Any Disabled
A Input
45
pF
6
pF
CIN
Maximum Input
Capacitance·
5
10
10
10
pF
COUT
Maximum Input
Capacitance
10
20
20
20
pF
Note 5: CPO determines the no load dynamic power consumption, Po= CPO Vc;c2 f+ lee Vee, and the no load dynamic current consumption, Is = CPO Vee f+ lee.
Truth Table
'HC368
Inputs
Output
G
A
Y
H
X•
Z
L
L
H
L
L
H
,
3-268
Logic Diagrams
MM54HC366/MM74HC366
MM54HC365/MM74HC365
TO OTHER
TO OTHER
5 BUFFERS
5 BUFFERS
110FT--
~--
"oF6
I
I
I
y
I
A-+---1><~""'+--+L'"
A
TLlF/5209-6
TLlF/5209-5
MM54HC3671MM74HC367
MM54HC368/MM74HC368
TO OTHER
TO OTHER
BUFFERS
BUFF£RS
fiomR-
~--,IDF4OR
l' OF 2
" OF 2
I
I
I
I
I
y
I
y
A
TLlF/5209-7
TL/F/5209-8
3·269
~National
~ Semiconductor
MM54HC373/MM74HC373
TRI-STATE® Octal D-Type Latch
General Description
These high speed octal Ootype latches utilize
microCMOS Technology, 3.5 micron silicon gate P-well
CMOS. They possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as
well as the ability to drive 15 LS-TTL loads. Due to the large
output drive capability and the TRI-STATE feature, these
devices are ideally suited for interfacing with bus lines in a
bus organized system.
When the LATCH .ENABLE Input is high, the Q outputs will
follow the 0 inputs. When the LATCH ENABLE goes low,
data at the b inputs will be retained at the outputs until
LATCH ENABLE returns high again. When a high logic level
is applied to the OUTPUT CONTROL input, all outputs go to
a high impedance state, regardless of what signals are pres-
ent at the ot~er inputs and the state of the storage elements.
The 54HCI74HC logic family is speed, function, and pin-out
compatible with the standard 54LS174LS logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to Vee and ground.
Features
•
•
•
•
•
Typical propagation delay: 18 ns
Wide operating voltage range: 2 to 6 volts
Low input current: 1 p.A maximum
Low quiescent current: 80 p.A maximum (74 Series)
Output drive capability: 15 LS-TTL loads
Connection Diagram
Dual-In-Una Package
LATCH
ENABLE
OUTPUT
80
80
70
70
60
60
50
50
6
10
10
20
20
30
3D
40
4Q
GNO
CONTROL
TLlF/5335-1
Top View
Orcier Number MM.54HC373J.or MM74HC373J,N
See NS Package J20A or N20A
Truth Table
Output
Control
Latch
Enable
Data
L
L
L
H
H
H
L
L
H
X
X
X
373
Output
H = high level. L = low level
00 = level of output before steady·state input
condHions were established.
Z = high Impedance
H
L
Qo
Z
3-270
Absolute Maximum Ratings (Notes 1& 2)
Operating Conditions
Supply Voltage (VeC>
-0.5 to + 7.0V
DC Input Voltage (VIN)
-1.5 to Vee + 1.5V
-0.5 to Vee+0.5V
DC Output Voltage (VOUT)
±20mA
Clamp Diode Current (11K. 10K>
±35mA
DC Output Current. per pin (lOUT)
±70mA
DC Vee or GND Current. per pin (IcC>
Storage Temperature Range (TSTG)
- 65'C to + 150'C
Power Dissipation (PD)
500mW
Lead Temp. (T (Soldering 10 seconds)
260'C
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN.VOUT)
Operating Temp. Range (TAl
MM74HC
MM54HC
Input Rise or Fall Times
(tr• til
Vee=2.0V
Vee=4.5V
Vee=6.0V
u
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
DC Electrical Characteristics
Symbol
Parameter
Conditions
TA=25'C
Vee
Typ
74HC
TA=-40t08S'C
54HC'
TA= -S5to 12S'C
Units
Guaranteed Limits
VIH
·Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
1i0UTI S:20 p.A
VIN = VIH or VIL
IiOUTIS:6.0 mA
IIOUTI S:7.8 mA
VOL
Maximum Low Level
Output Voltage
VIN = VIH or VIL
1i0UTI s: 20 p.A
2.0V
4.5V
6.0V
2.0
4 .•5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
,
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIH orVIL
IIOUTIS:6.0 mA
IIOUTIS:7.8 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
liN
Maximum Input
Current
VIN = Vee or GND
6.0V
±O.1
±1.0
±1.0
p.A
loz
Maximum TRI·STATE
Output Leakage
Current
VIN=VIH orV,L. OC=V,H
VOUT=VeeorGND
6.0V
±0.5
±5
±10
p.A
Maximum Quiescent
6.0V
8.0
80
160
p.A
V'N=VeeorGND
Supply Current
10UT=0p.A
Nate 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Nate 2: Unless otherwise specified all voltages are referenced to ground.
Nate 3: Power Dissipation temperature derating - plastic "N" package: -12 mWI"C from 6S'C to 8S'C; ceramic "J" peckage: -12 mW/'C from 100'C to 125'C.
Nate 4: For a power supply of SV ± 10% the worst case output voltages (VOH. and Vall occur for HC at 4.5V. Thus the 4.SV values should be used when
designing with this supply. Worst case VIH and VIL occur at Vcc= 5.SV and 4.5V respectively. (The VIH value at S.5V is 3.85V.) The worst case leakage current (liN.
Icc. and lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
Icc
3·271
AC Electrical Characteristics Vcc=5V, TA=25'C, t r =tf=6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed Limit
Units
tpHL, tpLH
Maximum Propagation Delay, Data to Q
CL =45 pF
18
25
ns
tpHL, tpLH
Maximum Propagation Delay, Clock to Q
CL =45 pF
21
30
ns
tpZH, tPZL
Maximum Output Enable Time
RL =1 kn
CL =45 pF
20
28
ns
tpHZ, tpLZ
Maximum Output Disable Time
RL =1 kn
CL =5pF
18
25
ns
ts
Minimum Set Up Time
5
ns
tH
Minimum Hold Time
10
ns
tw
Minimum Pulse Width
16
ns
9
AC Electrical Characteristics Vcc=2.0-6.0V, CL =50 pF, tr =tf=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25'C
Vee
Typ
tpHL, tpLH
tpHL,lpLH
tpZH, tPZL
Maximum Propagation
Delay, Data to Q
Maximum Propagation
Delay, Clock to Q
Maximum Output Enable
Time
\
74HC
TA= -40 to 85'C
54HC
TA = -55 to 125'C
Units
Guaranteed Limits
CL =50pF
CL =150pF
2.0V
2.0V
50
80
150
200
188
250
225
300
ns
ns
CL =50 pF
CL =150pF
4.5V
4.5V
22
30
30
40
37
50
45
60
ns
ns
CL =50pF
CL =150pF
6.0V
6.0V
19
26
26
35
31
44
39
53
ns
ns
CL =50pF
CL =150pF
2.0V
2.0V
63
110
175
225
220
280
263
338
ns
ns
CL =50 pF
CL =150 pF
4.5V
4.5V
25
35
35
45
44
56
52
68
ns
ns
CL =50pF
CL =150 pF
6.0V
6.0V
21
28
30
39
37
49
45
59
ns
ns ,
CL =50 pF
CL =150pF
2.0V
2.0V
50
80
150
200
188
250
225
300
ns
ns
CL =50pF
CL =150pF
4.5V
4.5V
21
30
30
40
37
50
45
60
ns
ns
CL =50pF
CL =150pF
6.0V
6.0V
19
26
26
35
31
44
39
53
ns
ns
RL =1 kn
CL =50pF
2.0V
4.5V
6.0V
50
21
19
150
30
26
188
37
31
225
45
39
ns
ns
ns
RL =1 kn
tPHZ, tpLZ
Maximum Output Disable
Time
ts
Minimum Set Up Time
2.0V
4.5V
6.0V
5
2
2
25
5
5
31
6
6
38
8
8
ns
ns
ns
tH
Minimum Hold Time
2.0V
4.5V
6.0V
20
6
6
50
10
10
60
13
13
75
20
20
ns
ns
ns
tw
Minimum Pulse Width
2.0V
4.5V
6.0V
30
10
9
80
16
14
100
20
18
120
24
20
ns
ns
ns
tTHL, tTLH
Maximum Output Rise
and Fall Time, Clock
CL =50pF
2.0V
4.5V
6.0V
25
7
6,
60
12
10
75
15
13
90
18
15
ns
ns
ns
CPD
Power Dissipation
Capacitance (Note 5)
(per latch)
OC=Vcc
OC=GND
CIN
pF
pF
30
50
Maximum Input Capacitance
5
Maximum Output Capacitance
15
10
10
10
pF
pF
20
Note 5: CPO determines the no load dynamic power consumption, Po=Cpo Vee2 f+ lee Vee, and the no load dynamic curren.t consumption, Is=Cpo Vee f+ Icc.
COUT
20
20
I
3·272
~National
~ Semiconductor
microCMOS
MM54HC37 4/MM7 4HC37 4
TRI-STATE® Octal D-Type Flip-Flop
General Description
These high speed Octal D-Type Flip-Flops utilize microCMOS Technology, 3.5 micron silicon gate P-well CMOS.
They possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as
the ability to drive 15 LS-TIL loads. Due to the large output
drive capability and the TRI-STATE feature, these devices
are ideally suited for interfacing with bus lines in a bus organized system.
These devices are positive edge triggered flip-flops. Data at
the D inputs, meeting the setup and hold time requirements,
are transferred to the 0 outputs on positive gOing transitions
of the CLOCK (CK) input. When a high logic level is applied
to the OUTPUT CONTROL (OC) input, all outputs go to a
high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.
The 54HC174HC logic family is speed, function, and pinout
compatible with the standard 54LS174LS logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to Vee and ground.
Features
•
•
•
•
•
•
Typical propagation delay: 20 ns
Wide operating voltage range: 2-6V
Low input current: 1 /LA maximum
Low quiescent current: 80 /LA maximum
Compatible with bus-oriented systems
Output drive capability: 15 LS-TIL loads
Connection Diagram
Dual-In-Line Package
80
80
70
70
60
60
50
OUTPUT 10
CONTROL
10
20
20
30
30
40
vee
50
~LOCK
TLIF/S336-1
Top View
Order Number MM54HC374J or MM74HC374J, N
See ~S Package J20A or N20A
Truth Table
Output
Control
L
L
L
H
= high Level, L = Low Level
= don't Care
t = transition from low·to·high
H
Clock
Data
Output
t
t,
H
L
H
L
L
X
X
00
X
X
Z = high impedance state
00= the level of the output before steady state
input conditions were established
Z
3-273
Absolute Maximum Ratings (Notes 1 &2)
-0.5 to + 7.0V
Supply Voltage (Vee)
DC Input Voltage (VIN)
-1.5to Vee + 1.5V
DC Output Voltage (VOUT)
-0.5 to Vec+0.5V
±20mA
Clamp Diode Current (11K. 10K)
±35mA
DC Output Current. per pin (lOUT)
±70mA
DC Vee or GND Current. per pin (Icel
- 65·C to + 150·C
Storage Temperature Range (TSTG)
500mW
Power Dissipation (Po)
260·C
Lead Temp. (TLl (Soldering 10 seconds)
Operating Conditions
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (Till
MM74HC
MM54HC
Input Rise or Fall Times
Vee=2.0V
(t,. ttl
Vee=4.5V
Vee=6.0V
Parameter
Conditions
Max
6
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
Vec
,
DC Electrical Characteristics
Symbol
Units'
V
V
Min
2
0
Vee
TA=25·C
Typ
74HC
TA= -40 to 85·C
54HC
TA= -55 to 125·C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3'
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
-
VIN=VIHorVIL
IIOUTI 5: 20 pA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V.
6.0Y
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
IIOUTI5:6.0 mA
IIOUTIS:7.8 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = VIH or VIL
IIOUTI 5:6.0 mA
IIOUTI 5:7.8 mA
VOL
Maximum Low Level
Output Voltage
VIN = VIH or VIL
IIOUTI 5: 20 p.A
liN
Maximum Input
Current
VIN=VeeorGND
6.0V
±0.1
±1.0
±1.0
p.A
loz
Maximum TRI-STATE
Output Leakage
Current
VIN=VIH.OC=VIH
VOUT=VeeorGND
6.0V
±0.5
±5
±10
p.A
Maximum Quiescent
6.0V
160
p.A
'8.0
80
VIN=Vecor GND
Supply Current
10UT=0 p.A
Nola 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Nole 2: Unless otherwise specified all voltages are referenced to 'ground.
Nole 3: Power Dissipation temperature derating - plastic "N" package: -12 mWI'C from 6S'C to 8S'C; ceramic "J" package: -12 mWI'C from 100'C to 12S'C.
Nole 4: For a power supply of SV ± 10% the worst case output voltages (VOH. and VoLl occur for HC at 4.SV: Thus the 4.SI( values should be used when deSigning
with this supply. Worst case VIH and VIL occur at Vcc= S.SV and 4.SV respecfively. (The VIH value at 5.SV is 3.85V.I The worst case leakage current (liN. ICC. and
lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
Icc
3-274
AC Electrical Characteristics Vee=5V, TA=25°C, t r =tf=6 ns
Symbol
Parameter
Conditions
Typ
Guaranteeq
Limit
Units
50
35
MHz
ns
fMAX
Maximum Operating
Frequency
tpHL, tpLH
Maximum Propagation
Delay Clock to Q
CL=45pF
20
32
tpZH, tPZL
Maximum Output Enable
Time
RL = kO
CL =45pF
19
28
ns
tpHZ, tpLZ
Maximum Output Disable
Time
RL = kO
CL =5pF
17
25
ns
ts
Minimum Setup Time
20
ns
tH
Minimum Hold Time
5
ns
tw
Minimum Pulse Width
16'
ns
9
AC Electrical Characteristics Vee = 2.0-6.0V, CL = 50 pF, tr=tf= 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=25°C
Typ
fMAX
Maximum Operating
Frequency
CL =50pF
2.0V
4.5V
6.0V
tpHL, tpLH
Maximum Propagation
Delay, Clock to Q
CL=50pF
CL =150 pF
2.0V
2.0V
CL =50pF
CL =150 pF
CL =50pF
CL =150pF
tpZH, tPZL
Maximum Output Enable
Time
74HC
TA= -40 to 85°C
54HC
TA= -55 to 125°C
Units
Guaranteed Limits
6
30
35
5
24
28
4
20
23
MHz
MHz
MHz
68
110
180
230
225
288
270
345
ns
ns
4.5V
4.5V
22
30
36
46
45
57
48
69
ns
6.0V
6.0V
20
28
31
40
39
50
46
60
ns
ns
CL =50pF
CL =150 pF
2.0V
2.0V
50
80
150
200
189
250
225
300
ns
ns
CL =50 pF
CL =150 pF
4.5V
4.5V
21
30
30
40
37
50
45
60
ns
ns
CL =50pF
CL =150 pF
6.0V
6.0V
19
26
26
35
31
44
39
53
ns
ns
RL =1 kO
CL =50 pF
2.0V
4.5V
6.0V
50
21
19
150
30
26
189
37
31
225
45
39
ns
ns
ns
ns
RL =1 kO
IpHZ, tpLZ
Maximum Output Disable
Time
ts
Minimum Setup Time
2.0V
4.5V
6.0V
100
20
17
125
25
21
150
30
25
ns
ns
ns
IH
Minimum Hold Time
2.0V
4.5V
6.0V
25
15
5
31
5
5
38
5
5
ns
ns
ns
Iw
Minimum Pulse Width
2.0V
4.5V
6.0V
30
9
8
80
16
14
100
20
18
120
24
20
ns
ns
ns
trHL, tTLH
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
25
7
6
60
12
10
75
15
13
90
18
15
ns
ns
ns
tr, If
Maximum Input Rise and
Fall Time, Clock
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
CPO
Power Dissipation
Capacitance (Note 5)
-,
CL =50pF
2.0V
4.5V
6.0V
(per flip-flop)
OC=Vee
OC=GND
30
50
pF
pF
pF
10
Maximum Input Capacitance
5
10
10
CIN
Note 5: CPO determines the no load dynamic power consumption, Po= CPO Vr:;c21+ Icc Vee. and the 'no load dynamic current consumption. Is=Cpo Vee 1+ Icc.
3-275
~National
~ Semiconductor
microCMOS
MM54HC390/MM74HC390
Dual 4-Bit Decade Counter
MM54HC393/MM74HC393
Dual 4-Bit Binary Counter
General Description
These counter circuits contain independent ripple carTy
counters and utilize microCMOS Technology, 3.5 micron silicon gate P-well CMOS. The MM54HC390/MM74HC390 incorporate dual decade counters, each composed of a divide-by-two and a divide-by-five counter. The divide-bY-two
and divide-by-five counters can be cascaded to form dual
decade, dual bi-quinary, or various 'combinations up to ,a
single
divide-by-100
counter.
The
MM54HC3931
MM74HC393 contain two 4-bit ripple carTy binary counters,
which can be cascaded to create a single divide-by-256
counter.
Each of the two 4-bit counters is incremented on the high to
low transition (negative edge) of the clock input, and each
has an independent clear input. When clear is set high all
four bits of each counter are set to a low level. This enables
count truncation and allows the implementation of divide-byN counter configurations.
Each of the counters outputs can drive 10 low power
Schottky TTL equivalent loads. These counters are func-
tionally as well as pin equivalent to the 54LS390174LS390
and the 54LS393/74LS393, respectively. All inputs are protected from damage due to static discharge by diodes to
Vee and ground. .
.
Features
•
•
•
•
•
Typical operating frequency: 50 MHz
Typical propagation delay: 13 ns (Ck to QA)
Wide operating supply voltage range: 2-6V
Low input current: < 1 /J-A
Low quiescent supply current: 80 /J-A maximum
(74HC Series)
• Fanout of 10 LS-TTL loads
Connection Diagrams
Dual·ln·Llne Package
VCC
16
2A
2 OUTPUT
CLEAR 2QA
2a
.'
Dual·ln·Llne Package
OUTPUTS
2Qa
OUTP.UTS
2QC
VCC
15
2
2A CLEAR 2QA
2Qa
CLEAR
A
QA
Qa
QC
8
1~
1
1QA 1a
CLEAR OUTPUT
1Qa
1QC
1QO
1A
OUTPUTS
TL/F/5337-1
QD
7
2
GNO
2QC
1
1QA 1Qa 1QC 1QO GNO
CLEAR -~-_ _- - OUTPUTS
TL/F/5337-2
Top View
TopVlew
Order Number MM54HC390J or MM74HC390J, N
See NS Package J16A or N16E
Order Number MM54HC393J or MM74HC393J, N
See NS Package J14A or N14A
. 3-276
Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage (VeC>
Operating Conditions
-0.5 to + 7.0V
DC Input Voltage (V,N)
-1.5 to Vee + 1.5V
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
±20mA
±25mA
Clamp Diode Current (1,K. '0K)
. DC Output Current. per pin (lOUT)
DC Vee or GND Current. per pin (IcC>
Storage Temperature Range (TSTG)
Supply Voltage (VeC>
DC Input or Output Voltage
(V,N. VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
Vee=2.0V
(tr. ttl
Vee=4.5V
Vee=6.0V
±50mA
-65·Cto + 150·C
Power Dissipation (Po) (Note 3)
Lead Temp. (TO (Soldering 10 seconds)
500mW·
260·C
Min
2
Max
6
0
Vee
Units
V
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25·C
74HC
TA= -40 to 85hC
Typ
. 54HC
TA= -55to 125·C
Units
Guaranteed Limits
V,H
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
V,L
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
Y,N = V,H or V,L
!louTI :s: 20 /LA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
'0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
V,N=V,H orV,L
IIOUTI:S:4.0 rnA
IIOUTI:S:5.2 rnA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
Y,N = Vec or GND
6.0V
±0.1
±1.0
±1.0
/LA
80
160
/LA
V,N=V,H orV,L
IIOUTI:S:4.0 rnA
IIOUTI:S:5.2 rnA
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
Y,N = V,H or V,L
IIOUTI:S:20/LA
Maximum Quiescent Y,N = Vee or GND
6.0V
8.0
Supply Current
IOUT=O /LA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
lee
Nole 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mWI'C from 6S'C to 8S'C; ceramic "J" package: -12 mWI'C from l00'C to 12S'C.
Note 4: For a power supply of SV ± 10% the worst case outputvollages (VOH. and VoLl occur for HC at4.SV. Thus the 4.SVvalues should be used when designing
with this supply. Worst case VIH and VIL occur at Vcc=S.5V and 4.5V respectively. (The VIH value at5.5V is 3.8SV.l The worst case leakage current (liN. Icc. and
lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
3·277
.
AC Electrical Characteristics
MM54HC390/MM74HC390
Vcc=5V. TA=25°C. CL =15 pF. t r =tf=6 ns
Typ
Guaranteed Limit
Units
fMAX
Maximum Operating Frequency. Clock A or B
50
30
MHz
tpHL. tpLH
Maximum Propagation Delay. Clock A to OA Output
12
20
ns
tpHL. tpLH
Maximum Propagation Delay. Clock A to Oc
(OA Connected to Clock B)
32
50
ns
tpHL. tpLH
Maximum Propagation Delay. Clock B to Os or 00
15
21
ns
tpHL. tpLH
Maximum Propagation Delay. Clock B to Oc
20
32
ns
Symbol
Conditions
Parameter
tpHL
Maximum Propagation Delay. Clear to any Output
15
28
ns
tREM
Minimum Removal Time. Clear to Clock
-2
5
ns
tw
Minimum Pulse Width. Clear or Clock
10
16
ns
AC Electrical Characteristics CL = 50 pF. tr= tf= 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=25°C
Typ
54HC
TA= -55to 125°C
Units
Guaranteed Limits
5
27
31
4
21
24
3
18
20
MHz
MHz
MHz
45
15
13
120
24
21
150
30
26
180
35
31
ns
ns
ns
2.0V
4.5V
6.0V
100
35
30
290
58
50
360
72
62
430
87
75
ns
ns
ns
2.0V
4.5V
6.0V
50
16
13
130
26
22
160
33
28
195
39
33
ns
ns
ns
fMAX
Maximum Operating
Frequency
2.0V
4.5V
6.0V
tpHL. tpLH
Maximum Propagation
Delay. Clock A to OA
2.0V
4.5V
6.0V
tpHL. tpLH
Maximum Propagation
Delay. Clock A to Oc
(OA Connected to Clock B)
tpHL. tpLH
Maximum Propagation
Delay. Clock B to Os or
00
74HC
TA= -40 to 85°C
tpHL. tpLH
Maximum Propagation
Delay. Clock B to Oc
2.0V
4.5V
6.0V
60
20
17
185
37
32
230
46
40
280
55
48
ns
ns
ns
tpHL
Maximum Propagation
Delay. Clear to any 0
2.0V
4.5V
6.0V
55
17
15
165
33
28
210
41
35
250
49
42
ns
ns
ns
tREM
Minimum Removal Time
Clear to Clock
2.0V
4.5V
6.0V
25
5
5
25
5
5
25
5
5
ns
ns
ns
tw
Minimum Pulse Width
Clear or Clock
2.0V
4.5V
6.0V
30
10
9
130
16
14
100
20
18
120
24
20
ns
ns
ns
tTHL. tTLH
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
tr.tl
Maximum Input Rise
and Fall Time
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
CpO
Power Dissipation
Capacitance (Note 5)
"
2.0V
4.5V
6.0V
(per counter)
55
pF
Maximum Input Capacitance
5
10
10
10
pF
CIN
Note 5: CpD determines the no load dynamic power consumption, PD=CPD Vee2 f+lcc Vee, and the no load dynamic current consumption, IS=CPD Vee f+lee.
3-278
AC Electrical Characteristics MM54HC393/MM74HC393
Vcc=5V. TA=25'C. CL =15 pF. 1r =11=6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed Limit
Units
fMAX
Maximum Operating Frequency
50
30
MHz
tpHL. tpLH
Maximum Propagation Delay. Clock A to OA
13
20
ns
tpHL. tpLH
Maximum Propagation Delay. Clock A to Os
19
35
ns
tpHL. tpLH
Maximum Propagation Delay. Clock A to Oc
23
42
ns
tpHL. tpLH
Maximum Propagation Delay. Clock A to 00
27
50
ns
tpHL
Maximum Propagation Delay. Clear to any 0
15
28
ns
tREM
Minimum Removal Time
-2
5
ns
tw
Minimum Pulse Width Clear or Clock
10
16
ns
AC Electrical Characteristics CL = 50 pF. tr =tl= 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25'C
Vee
Typ
Maximum Operating
Frequency
2.0V
4.5V
6.0V
tpHL. tpLH
Maximum Propagation
Delay Clock A to OA
2.0V
4.5V
6.0V
tpHL. tpLH
Maximum Propagation
Delay Clock A to Os
tpHL. tpLH
74HC
TA=-40t085'C
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
5
27
31
4
21
24
3
18
20
MHz
MHz
45
15
13
120
24
21
150
30
26
180
35
31
ns
ns
ns
2.0V
4.5V
6.0V
68
23
20
190
38
32
240
47
40
285
57
48
ns
ns
ns
Maximum Propagation
Delay Clock A to Oc
2.0V
4.5V
6.0V
90
30
26
240 48
41
300
60
51
360
72
61
ns
ns
ns
tpHL. tpLH
Maximum Propagation Delay
Clock to 00
2.0V
4.5V
6.0V
100
35
30
290
58
50
360
72
62
430
87
75
ns
ns
ns
tpHL
Maximum Propagation
Delay Clear to any 0
2.0V
4.5V
6.0V
54
18
15
165
33
28
210
41
35
250
49
42
ns
ns
ns
tREM
Minimum Clear Removal
Time
2.0V
4.5V
6.0V
25
5
5
25
5
5
25
5
5
ns
ns ns
tw
Minimum Pulse Width
Clear or Clock
2.0V
4.5V
6.0V
30
10
9
80
16
14
100
2018
120
24
20
ns
ns
ns
tTHL. tTLH
Maximum Output Rise
and Fail Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
t r• tl
Maximum Input Rise
and Fail Time
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
fMAX
CPO
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input Capacitance
(per counter)
-
pF
42
5
10
10
10
pF
Nota 5: CPO determines the no load dynamic power consumption. Po=Cpo Vcc1-1+ ICC Vce. and the no load dynamic current consumption. Is=Cpo Vee 1+ Icc.
3-279
Logic Timing Waveforms
I
4
I
5·1
6
'I
7 18
I
9
1 10 I
11
I 12 I
13
I
14
I
15
I· 0 1
CLOCK A
1...-_...11
OB_-~,-:_ _ _-'
390
I·
.....' ----_......
.....' --------------'
OC-,
OD-'
OB
-j
,
393
Oc --I
I
I
OD
,
-1
L
L
L
TLlF/5337-3
3-280
~National
---,
~ Semiconductor
\,--_..../J
microCMOS
MM54HC423A/MM74HC423A
Dual Retriggerable Monostable Multivibrator
General Description
The MM54174HC423A high speed monostable multivibrators (one shots) utilize microCMOS Technology, 3.5 micron
silicon gate P-well CMOS. They feature speeds comparable
to low power Schottky TTL circuitry while retaining the low
power and high noise immunity characteristic of CMOS
circuits.
Each multivibrator features both a negative, A, and a positive, S, transition triggered input, either of which can be
used as an inhibit input. Also included is a clear input that
when taken low resets the one shot. The 'HC423A cannot
be triggered from clear.
The 'HC423A is retriggerable. That is, it may be triggered
repeatedly while its outputs are generating a pulse and the
pulse will be extended.
Pulse width stability over a wide range of temperature and
supply is achieved using linear CMOS techniques. The output pulse equation is simply: PW = (REXT) (CEXT); where PW
is in seconds, R is in ohms, and C is in farads. All inputs are
protected from damage due to static discharge by diodes to
Vee and ground.
Features
•
•
•
•
•
•
•
•
•
Typical propagation delay: 40 ns
Wide power supply range: 2V-6V
Low quiescent current: 80 ",A maximum (74HC Series)
Low input current: 1 ",A maximum
Fanout of 10 LS-TTL loads
Simpie pulse width formula T = RC
Wide pulse range: 400 ns to 00 (typ)
Part to part variation: ±5% (typ)
Schmitt Trigger A & B inputs allow infinite rise and fall
times on these inputs
Connection Diagram
Dual-In-Llne Package
V~6
REXT1
CjJ5
~2.
Cj,'4
.12
I I
a
CLR
TImIng Component
Cl!'2
.11
~
CLR
a
i' I I
TO CEXT
TO R/CEXT
TERMINAL
TERMINAL
TL/F/533B-l
Top VIew
Order Number MM54HC423AJ or MM74HC423AJ, N
See NS Package J16A or N16E
Truth Table
Inputs
H
Outputs
s·
Clear
A
L
X
X
X
H
X
X
X
Q
Q
L
L
L
L
H
H
H
l..J
l..J
,H
L
t
.n...
H
.J..
H
..J1..
=
High Level
L = Low Level
t =
'" =
.n.. =
l.J" =
Transition from Low to High
Transition from High to Low
One High Level Pulse
One Low Level Pulse
X = Irrelevant
3-281
TLlF/533B-2
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
-0.5Vto +7.0V
Supply Voltage (VeC>
DC Input Voltage (VIN)
-1.5VtoVee+ 1.5V
DC Output Voltage (VOUT)
-0.5V to Vee+0.5V
±20mA
Clamp Diode Current (11K, 10K>
±25mA
DC Output Current, per pin (lOUT)
±50mA
DC Vee or GND Current, per pin (IcC>
-65·C to + 150·C
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
500mW
Lead Temp. (T (Soldering 10 seconds)
260"C
Supply Voltage.(Vee)
DC Input or Output Voltage
. (VIN,VOUT)
Operating Temp. Range (TAl
MM74HC
MM54HC
Min
2
0
Max
6
Vee
-40
-55
+85
+125
·C
, ·C
1000
500
400
ns
ns
ns
Maximum Input Rise and Fall Time
(Clear Input)
Vee=2.0V
Vee=4.5V
Vee=6.0V
u
Units
V
V
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
TA=25·C
Vee
Typ
VIH
Minimum High Level Input
Voltage
2.0V
4.5V
6.0V
VIL
Maximum Low Level Input
Voltage
2.0V
4.5V
6.0V
YOH
Minimum High Level
Output Voltage
,
VOL
Maximum Low Level
Output Voltage
VIN = VIH or VIL
II0UTIs: 20/LA
~
2.0V
4.5V
6.0V
VIN = VIH or VIL
IIOUTI s: 4.0 mA
ilOUTI s: 5.2 mA '
4.5V
6.0V
VIN=VIH OrVIL
ilOUTI S:20 /LA
I
2.0
4.5
6.0
2.0V
4.5V
6.0V
0
0
0
74HC
TA=-40t085·C
54HC
TA=-55 to 125·C Units
Guaranteed Limits
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
3.96
5.46
3.84
5.34
3.7
5.2
V
V
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
,
VIN=VIHorVIL
IloUTIS:4mA
IIOUTIS:5.2 mA
4.5V
6.0V'
0.26
0.26
0.33
0.33
0.4
0.4
V
V
V
liN
Maximum Input Current
(Pins 7,15)
VIN=VeeorGND
5.0V
0.5
5.0
5.0
p.A
liN
Maximum Input Current
(all other pins)
VIN = Vee or GND
6.0V
±0.1
±1.0
±1.0
/LA
Icc
Maximum Quiescent Supply
Current (standby)
VIN = Vee or GND
IOUT=O/LA
6.0V
8.0
80
160
/LA
Maximum Active Supply
Current (per
monostable)
VIN = Vee or GND
R/CEXT= 0.5Vee
2.0V
4.5V
6.0V
Icc
I
36
0.33
0.7
80
1.0
2.0
110
1.3
2.6
130
1.6
3.2
/LA
rnA
mA
Nota 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Nota 3: Power Dissipation Temperature Derating: Plastic "N" Package: -12mwre from 6S'C to 8S'C Ceramic "J" Package: -12mW/'C from 100'0 to 125'C
Note 4: For a power supply of sv ± 10% the worst-case output voltages (YOH, Vou occur for HC at 4.SV. Thus the 4.5V values should be used when designing
with this supply. Worst-case VIH and VIL occur at Vcc=5.5V and 4.5V respectively. [The VIH value at 5.5V Is 3.85V.) The worst-case leakage current (liN. Icc. and
lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
3·282
AC Electrical Characteristics Vcc=5V, TA=25'C, CL =15 pF, tr =tf=6 ns
Typ
Limit
Units
tpLH
Maximum Trigger Propagation
Delay, A, B to Q
22
33
ns
tpHL
Maximum Trigll..er Propagation
Delay, A, B to Q
25
42
.
ns
tpHL
Maximum Propagation Delay,
CleartoQ
20
27
ns
22
33
ns
14
26
ns
0
ns
Symbol
Maximu~Propagation
tpLH
Conditions
Parameter
I
Delay,
CleartoQ '
tw
Minimum Pulse Width, A, B or
Clear
tREM
Minimum Clear Removal Time
iwa(MIN)
Minimum Output Pulse Width
CEXT=2B pF
REXT=2 kG
twa
Output Pulse Width
CEXT= 1000 pF
REXT=10kG
400
ns
10
f.£s
AC Electrical Characteristics CL = 50 pF tr= tf= 6 ns (Unless otherwise specified)
Symbol
Parameter
Vee
Conditions
_,
74HC
' 54HC
TA-25 C TA= -40 to 85'C TA= -55 to 125'C Units
Typ
Guaranteed Limits
tpLH
Maximum Trigger Propagation
Delay, A, B or Clear to Q
2.0V 77
4.5V 26
6.0V 21
169
42
32
194
51
39
210
57
44
ns
ns
ns
tpHL
Maximum Trigger prop~ation
Delay, A, B or Clear to
2.0V BB
4.5V 29
6.0V 24
197
4B
3B
229
60
46
250
67
51
ns
ns
ns
tpHL
Maximum Propagation
Delay, Clear to Q
2.0V 54
4.5V 23
6.0V 19
114
34
2B
132
41
33
143
45
36
rls
ns
ns
tpLH
Maximum prop~ation
Delay, Clear to
'
2.0V 56
4.5V 25
6.0V 20
116
36
29
135
42
34
147
46
37
ns
ns
ns
tw
Minimum Pulse Width
A, B,Clear
2.0V 57
4.5V 17
6.0V 12
123
30
21
144
37
27
157
42
30
ns
ns
ns
tREM
Minimum Clear
Removal TIme
2.0V
4.5V
6.0V
0
0
0
0
0
0
0
0
0
ns
ns
ns
twa(MIN) Minimum Output
Pulse Width
twa
Output Pulse Width
trLH, trHL Maximum Output Rise
and Fall Time
2.0V 1.5
4.5V 450
6.0V 3BO
CEXT=2B pF
RExr=2 kG
REXT=6 kG (Vcc=2V)
CEXT=0.1 f.£F
REXT=10kG
.
0
0
0
J
f.£s
ns
ns
Min 4.5V
1
0.9
Max 4.5V
ms
ms
1
1.1
2.0V 30
4.5V B
6.0V 7
75
15
13
95
19
16
110
22
19
ns
ns
ns
CIN
Maximum Input
Capacitance (Pins 7 & 15)
12
20
20
20
pF
CIN
Maximum Input
Capacitance (other inputs)
6
10
10
10
pF
3-2B3 '
Logic Diagram
Vee
11
CUAR----~~J~~------~--------~
TL/F/5338-5
Theory of Operation
000
A-ll~
__~____rtJl~~n~_____
CD
B
u
®
11--....1
CLEAR
R/Coo
Q
I
LJ
I
- ......I-T-1 I--T-1~ NEGATIVE EDGE TRIGGER
(!)
LJl___
I-T-/
POSITIVE EDGE RE.TRIGGER (PULSE LENGTHENING)
CI> RESET PULSE SHORTENING
CI> POSITIVE EDGE TRIGGER
TL/F/5338-8
FIGURE 1
3..284 ; ~
Theory of Operation
TRIGGER OPERATION
As shown in Figure 1 and the logic diagram before an input
RETRIGGER OPERATION
The 'HC423A is retriggered if a valid trigger occurs @ foltrigger occurs, the one-shot is in the quiescent state with the
lowed by another trigger @ before the Q output has returned to the quiescent (zero) state. Any retrigger, after the,
output low, and the timing capacitor CEXT completely
timing node voltage at pin or has begun to rise from VREF1,
charged to Vee. When the trigger input A goes from Vee to
but has not yet reached VREF2, will cause an increase in
GND (while inputs B and clear are held to Vec'J a valid trigger is recognized, which turns on, comparator C1 and Noutput pulse width T. When a valid retrigger is initiated @,
Channel transistor N1 CD. At the same time the output latch
the voltage at the R/CEXT pin will again drop to VREFI before progressing along the RC charging curve toward Vee.
is set. With transistor N1 on, the capacitor CEXT rapidly discharges toward GND until VREFI is reached. At this point
The Q output will remain high until time T, after the last valid
retrigger.
the output of ,comparator C1 changes state and transistor
N1 turns off. Comparator C1 then turns off while at the
Because the trigger-control circuit flip-flop resets shortly afsame time comparator C2 turns on. With transistor N1 off, ' ter Cx has discharged to the reference ,voltage of the lower
the capacitor CEXT begins to charge through the timing rereference circuit, the minimum retrigger time, trr is a function
sistor, REXT, toward Vee. When the voltage across CEXT
of internal propagation delays and the discharge time of Cx:
equals VREF2, comparator C2 changes state causing the
RESET OPERATION
output latch to reset (0 goes low) while at the same time
These one shots may be reset during the generation of the
disabling comparator C2. This ends the timing cycle with the
output pulse. In the reset mode of operation, an input pulse
one-shot in the quiescent state, waiting for the next trigger.
on clear sets the reset latch and causes the capacitor to be
A valid trigger is also recognized when trigger input B goes
fast charged to Vee by turning on transistor Q1 @. When
from GND to Vee (while input A is at GND and input clear is
the voltage on the capacitor reaches VREF2, the reset latch
at Vee®.)
will clear and then be ready to accept another pulse. If the
It should b~ noted that in the quiescent state Coo is fully
clear input is held low, any trigger inputs that occur will be
charged to Vee causing the current through resistor REXT to
inhibited and the' Q and Q outputs of the output latch will not
be zero. Both comparators are "off" with the total device
change. Since the Q output is reset when an input low level
current due only to reverse junction leakages. An added
is detected on the Clear input, the output pulse T can be
feature of the 'HC423A is that the output latch is set via
made significantly shorter than the minimum pulse width
the input trigger without regard to the capacitor voltage.
specification.
Thus, propagation delay from trigger to 0 is independent of
the value of CEXT, REXT, or the duty cycle of the input waveform.
o
Typical Output Pulse Width va.
TIming Components
Typical Distribution 01 Output
Pulse Width, Part to Part
10m
~ 1.2
iii
..'"
..,..
a::
a:: 1.0
CI
u..
O.B
Vcc-5V
fA=25'C
REXT =10 kll
CEXT=O.1 pf
II "i\
CI
iii
0.6
'" 0.4
Ii!
IE
...2!:
~
::!
10DOp
0.01~
0.1~
0.2
0
Typlcallma Pulle Width
Variation va. Supply
I
~
CI
iii
.ill
.
!fj
J
\
I~'
0.92
TIMING CAPACITOR (F)
"
TL/F/5338-7
=c
1.0
O.B
0.6
0.4
0.2
ill
0
~
~
\
\WORST~ASE
...
i
-0.2
u ,...0.4
a::
~ -0.6
-O.B
-1.0
-55
.........
"- -TYPICAL
1
4
POWER SUPPLY (V)
7
TL/F/5338-9
Typlcallml Pulse Width
Variation va. Temperature
\
""
/.
TLlF/5338-8
Minimum REXT va.
Supply Voltage
"k
..".
-1
a: -2
~ -3
-4
-5
0.96 1.00 1.04 1.06
OUTPUT PULSE WIDTH (ms)
1~
,
z
TA=25'C
REXT=10 kll
CEXT =0.1 ~F
POWER SUPPLY (V)
TL/F/5338-1D
Note: Rand C are not subjected 10 temperature. The C is polypropylene.
3-285
"
I"
....
i"'ooo
-15
25
65
TEMPERATURE ('C)
....
105125
TLlF/5338-11
~National
~ Semiconductor
micro CMOS
MM54HC521/MM74HC521
8-Bit Magnitude Comparator (Equality Detector)
Ge.neral Description
This equality detector utilizes microCMOS Technology, 3.5
micron silicon gate P-well CMOS, to compare bit for bit two
8-bit words and indicates whether or not they are equal. The
P = Q output indicates equality when it is low. A single active
low enable is provided to facilitate cascading of several
packages and enable comparison of words greater than 8
bits.
This device is useful in memory block decoding applications, where memory block enable signals must be generated from computer address information.
compatible to the 54LS688174LS68B. All inputs are protected from damage due to static discharge by diodes to Vee
and ground.
Features
•
•
•
•
Typical propagation delay: 20 ns
Wide power supply range: 2-6V
Low quiescent current: 80 p.A (74 Series)
Large output current: 4 mA (74 Serie.s)
The comparator's output can drive 10 low power Schottky
equivalent loads. This comparator is functionally and pin
Connection and Logic Diagrams
Dual-In-Line Package
Vce P = 0
07
P7
06
P6
05
~5
04
P4
07
11
G
PO
00
P1
01
P2
02
P3
03
)O-Dco-{~(~l.;;.) -P.-0
GND
Tl/F/6126-1
Top View
Order Number MM54HC521J or MM74HC521J,N
See NS Package J20A or' N20A
Truth Table
Inputs
Data
G
(1)
Enable
P,Q
G
P= Q
P>Q
P
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K, 10K)
DC Output Current, per pin (lOUT)
DC Vee or GND Current, per pin (Ice>
Storage Temperature Range (T8TG)
Power Dissipation (Po) (Note 3)
Lead Temperature (T Ll
(Soldering 10 seconds)
Supply Voltage (Vee>'
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
(tr, tt)
VCC=2.0V
Vcc=4.5V
VCC=6.0V
-0.5 to +7.0V
-1.5 to Vee+ 1.5V
-0.5 to Vee+0.5V
±20mA
±25mA
±50mA
- 65·C to + 150·C
500mW
260·C
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25·C
Typ
74HC
TA= -40 to 85·C
54HC
TA= -55 to 125·C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
M~imum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN=VIHorVIL
l!ouTI";20 ,...A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
IIOUTI";4.0 mA
IIOUTI";5.2mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = VIH or VIL
IIOUTI";4.0 mA
l!ouTI";5.2 mA
VOL
Maximum Low Level
Output Voltage
VIN = VIH or VIL
IIOUTI";20 ,...A
liN
Maximum Input
Current
VIN=VeeorGND
6.0V
±0.1
±1.0
±1.0
,...A
Icc
Maximum Quiescent
Supply Current
VIN=VCCor GND
IOUT=O",A
6.0V
8.0
80
160
,...A
1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Unless otherwise specified all voltages are referenced to ground.
NOIe 3: Power Dissipation tamperature derating - plastic "'N"' package: -12 mWI"e from 6S'C to 8S'C; ceramic "'J"' package: -12 mW/'C from 1000C to 125'C.
Note 4: For a power supply of SV ± 10%' the worst case output voltages (VOH. and VoLl occur for HC at 4.SV. Thus the 4.SV values should be used when
designing with this supply. Worst cas. VIH and VIL occur at Vcc= 5.SV and 4.SV respeCtively. (The VIH value at S,SV is 3.85V.) The worst case leakage current (liN.
Icc. and lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
Note
NOle 2:
.
3·287
AC Electrical Characteristics
Vcc=5V. TA=25°C.CL =15 pF. tr =tf=6 ns
Typ
Guaranteed
Umlt
Units
Maximum Propagation
Delay. any P or Q to Output
21
30
ns
Maximum Propagation
Delay. Enable to any Output
14
20
ns
Symbol
Parameter
tpHL. tpLH
tpLH. tpHL
Conditions
AC Electrical Characteristics
Vcc=2.0V to S.OV. CL =50 pF. tr =tf=6 ns (unless otherwise specified)
,
Symbol
Parameter
Conditions
Vee
TA=25°C
74HC
TA= -40 to 85°C
Typ
54HC
TA=-55to125"C
Units
Guaranteed Limits
tPfjL. tpLH
Maximum Propagation
Delay
2.0V
4.5V
6.0V
60
22
19
175
35
30
220
44
38
263
53
45
ns
ns
ns
tpHL. tpLH
Maximum Propagation
Delay
2.0V
4.5V
6.0V
45
15
13
120
24
20
150
30
25
180
36
30
ns
ns
ns
iTHL. tTLH
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
75
11)
13
95
19
16
110
22
19
ns
'ns
ns
CPO
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input
Capacitance
.
45
5
10
pF
10
10
pF
Note 5: Cpo determines the no load dynami~ power consumption. Po= Cpo VcCJ. f+ Icc Vee. and the no load dynamic current consumption. Is = CPO Vee f+ lee.
,
3·288
~National
~ Semiconductor
microCMOS
MM54HC533/MM74HC533
TRI-STATE® Octal D-Type Latch
with Inverted Outputs
General Description
These high speed OCTAL D-TYPE LATCHES utilize
microCMOS Technology, 3.5 micron silicon gate P-well
CMOS. They possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as
well as the ability to drive 15 LS-TTL loads. Due to the large
output drive capability and the TRI-STATE feature, these
devices are ideally suited for interfacing with bus lines in a
bus organized system.
When the LATCH ENABLE input is high, the Q outputs will
.follow the inversion of the D inputs. When the LATCH ENABLE goes low, data at the D inputs will be retained at the
outputs until LATCH ENABLE returns high again. When ahigh logic level is applied to the OUTPUT CONTROL input,
all outputs go to a high impedance state, regardless of what
signals are present at the other inputs and the state of the
storage elements.
The 54HC/74HC logic family is speed, function, and pin-out
compatible with the standard 54LS/74LS logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to Vee and ground.
Features
•
•
•
•
•
•
Typical propagation delay: 13 ns
Wide operating voltage range: 2 to 6 volts
Low input current: 1 p.A maximum
Low quiescent current: 80 p.A, maximum (74HC Series)
Compatible with bus-oriented systems
Output drive capability: 15 LS-TTL loads
Connection Diagram
Dual-In-Line Package
. vcc
eo
OUTPUT
CONTROL
80
70
60
10
20
3D
50
sa
40
LATCH
ENABLE
G
GNO
TLlF/5339-1
Top View
Order Number MM54HC533J or MM74HC533J, N
See N~ Package J20A or N20A
Truth
T~ble
Output
C,!-Ilt rol '
L
L
L
H
Latch
Enable
G
H
H
L
X
Data
H
L
X
X
Output
H
= high level, L = low level
00 = level of output before steedy-state input conditions
L
H
were established.
Z
00
Z
3-289
= high impedance
Absolute Maximum Ratings
Operating Conditions
(Notes 1 & 2)
Supply Voltage {Veel
-0.5 to +7.0V
-1.5'to Vee + 1.5V
DC Input Voltage (VIN)
:
-0.5 to Vee+0.5V
DC Output Voltage (VOUT)
±20mA
Clamp Diode Current (11K. 10K>
±35mA
DC Output Current. per pin (lOUT)
±70mA
DC Vee or GND Current. per pin (Ieel
-65·Cto + 150·C
Storage Temperature Range (TSTG)
500mW
Power Dissipation (Po)
260·C
Lead Temp. (TL.l (Soldering 10 seconds)
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TAl
MM74HC
MM54HC
Input Rise or Fall Times
Vee=2.0V
(tr• til
Vee=4.5V
Vee=6.0V
:
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
DC Electrical Characteristics
Parameter
Symbol
Conditions
Vee
TA=25"C
Typ
74HC
TA=-40to85·C
54HC
TA=-55to125·C
,
Guaranteed Limits
Units
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2'
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
,
VOL
Maximum Low Level
Output Voltage
VIN = VIH or VIL
IIOUTI~20 p.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
'3.98
5.4B
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIH orVIL
IIOUTI~6.0 mA
·IIOUTI~7.8 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN,= VIH or VIL
IIOUTI ~ 6.0 mA
IIOUTI~7.8 rnA
VIN=VIH orVIL
IIOUTI~20p.A
liN
Maximum Input
Current
VIN=VeeorGND
6.0V
±0.1
±1.0
±1.0
p.A
IOZ
Maximum TRI-STATE
Output Leakage
Current
VIN = VIH or VIL. OC = VIH
VOUT=Vee or GND
6.6v
±0.5
±5
±10
p.A
Maximum Quiescent
160
6.0V
B.O
BO
p.A
VIN=Vee or GND
Supply Current
IOUT=Op.A
Not. 1: Absolute Maximum Ratings are those values beyond which damage to the device may occu~.
Note 2: Unless otherwise specified all voltages are referenced 10 ground.
Nota 3.: Power Dissipation temperature derating - plastic "N" package: -12 mWI'C from 65'C to 85'C; ceramic "J" paci
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K. 10K>
DC Output Current. per pin (lOUT)
DC Vee or GND Current. per pin (lee)
Storage Temperature Range (T8TG)
Power Dissipation (Po) (Note 3)
Lead Temperature (Tt.>
(Soldering 10 seconds)
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA>
MM74HC
MM54HC
Input Rise or Fall Times
(tr• tf)
Vee=2.0V
Vee=4.5V
Vee=6.0V
-0.5 to +7.0V
-1.5 to Vee + 1.5V
-0.5 to Vee+0.5V
±20mA
±35mA
±70mA
-65'Cto + 150'C
500mW
260'C
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25'C
Typ
74HC
54HC
TA= -40 to 85'C TA= -55 to 125'C Units
Guaranteed Limits
di
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
3.15
4.2
1.5
3.15
4.2
V
V
V
Vil
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Outpu1 Voltage
VIH
VIN = VIH or Vil
IIOUTI~20 p.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or Vil
IIOUTI~6.0 mA
IIOUTI~7.8 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = Vee or GND
6.0V
±0.1
±1.0
±1.0
p.A
6.0V
±0.5
±5
±10
p.A
VIN = VIH or Vil
IlciuTI~6.0 mA
IIOUTI~7.8 mA
VOL
Maximum Low Level
Output Voltage
VIN = VIH or Vil
IIOUTI~20 p.A
liN
iMaximum Input
Current
loz
Maximum TRI-STATE VIN = VIH or Vil. OC = VIH
Output Leakage
VOUT=Vee or GND
Current
Maximum Quiescent
160
p.A
6.0V
80
8.0
VIN=Vee or GND
Supply Current
IOUT=O p.A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic '"N'" package: -12 mW/'C from 65'C to 65'C; ceramic '"J'" package: -12 mW/,C from 1OO'C to 125'C.
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and Vall occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and Vll occur at Va; =5.5V and 4.5V respectively. (The VIH value at 5.5V Is 3.85V.) The worst case leakage current (liN.
Ia;. and loz) occur for CMOS at the higher voltage and so the 6.0V values should be used.
lee
,
3-293
AC Electrical Characteristics Vcc=5V. TA=25°C. t r =tl=6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed Umlt
Units
35
MHz
fMAX
Maximum Operating Frequency
tpHL. tpLH
Maximum Propagation Delay Clock to 0
CL =45pF
23
32
ns
tPZH. tPZL
Maximum Output Enable Time
RL =1 kO
CL=45pF
21
28
ns
tpHZ. tpLZ
Maximum Output Disable Time
RL=1 kO
CL=5pF
19
25
ns
,
ts
Minimum Setup Time
10
20
ns
tH
Minimum Hold Time
0
5
ns
fw"·
Minimum Pulse Width
9
16
ns
AC Electrical Characteristics Vcc=2.0-6.0V. CL =50 pF. 1,-=tl=6 ns (unless otherwise specified)
Symbol
fMAX
tpHL. tpLH
tPZH. tPZL
Parameter
Maximum Operating
Frequency
Conditions
,
Vee
TA=25°C
Typ
CL =50 pF
2.0V
4.5V
6.0V
CL=50pF
CL =150pF
2.0V
2.0V
CL =50pF
CL =150pF
CL =50pF
CL =150pF
Maximum Output En~fe Time
54HC
TA= -55 to 125°C
Units
Guaran1eed Limits
6
30
35
5
24
28
4
20
23
MHz
MHz
MHz
68
110
180
230
225
288
270
345
ns
ns
4.5V
.4.5V
22
30
36
46
45
57
48
69
ns
ns
6.0V
6.0V
20
28
31
40
39
50
46
60
ns
ns
CL =50pF
CL=150pF
2.0V
2.0V
50
80
150
200
189
250
225
300
ns
ns
CL =50pF
CL =150pF
4.5V
4.5V
21
29
30
40
37
50
45
60
ns
ns
CL =50pF
CL =150pF
6.0V
6.0V
19
25
26
35
31
44
39
53
ns
ns
RL =1 kO
CL =50 pF
2.0V
4.5V
6.0V
50
21
19
150
30
26
189
37
31
225
45
39
ns
ns
ns
l
Maximum Prop~ation
Delay. Clock to Q
74HC
TA=-40t085°C
RL =1 kO
tpHZ. tpLZ
Maximum Output Disable Time
ts
Minimum Setup Time
2.0V
4.5V
6.0V
100
20
17-
'125
25
21
150
30
25
ns
ns
ns
1H
Minimum Hoid Time
2.0V
4.5V
6.0V
5
5
5
5
5
5
5
5
5
ns
ns
ns
fw
Minimum Pulse Width
2.0V
4.5V
6.0V
80
16
14
100
20
18
120
24
20
ns
ns
ns
tTHL. tTLH
Maximum Output Rise
and Fall Time
60
12
10
75
15
13
90
18
15
ns
ns
ns
1,-. tl
Maximum Input Rise and Fall Time
Clock
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
CPD
Power Dissipation
Capacitance (Note 5)
CIN
CL =50pF
2.0V
4.5V
6.0V
(per flip-flop)
OC=Vcc
OC=Gnd
25
7
6
30
50
Maximum Input Capacitance
5
pF
pF
10
10
10
pF
Maximum Output Capacitance
pF
15
20
20
20
COUT
Note 5: CPO determines the no load dynamic power consumption. Po= Cpo Vet:!- f+ Icc Vee. and the no load dynamic current consumption, Is = CpO Vcc f+ Icc.
3-294
~National
PRELIMINARY
\
~ Semiconductor
)
microCMOS
MM54HC540/MM74HC540
Inverting Octal TRI-STATE® Buffer
MM54HC541/MM7'4HC541
Octal TRI-STATE Buffer
General Description
These TRI-STATE buffers utilize microCMOS Technology,
3.5 micron silicon gate P-well CMOS. They possess high
drive current outputs which enable high speed operation
even when driving large bus capacitances. These, circuits
achieve speeds comparable to low power Schottky devices,
while retaining the advantage of CMOS circuitry, i.e., high
noise immunity, and low power consumption. Both devices
have a fanout of 15 LS-TIL equivalent inputs.
The MM54HC540/MM74HC540 is an inverting buffer and'
the MM54HC541/MM74HC541 is
non-inverting buffer.
The TRI-STATE control gate operates as a two-input NOR
such that if either G1 or G2 are high, all eight outputs are in
the high-impedance state.
a
Connection Diagrams
In order to enhance PC board layout, the 'HC540 and
'HC541 offers a pinout having inputs and outputs on opposite sides of the package. All inputs are protected from damage due to static discharge by diodes to Vee and ground.
Features
•
•
•
•
•
Typical propagation delay: 12 ns
TRI-STATE outputs for connection to system buses
Wide power supply range: 2-6V
Low quiescent current: 80 /J-A maximum (74HC Series)
Output current: 6 mA
Dual-In-Llne Package
Vee
iff
Yl
Y2
Y3
V4
iii
Al
A2
A3
A4
AS
A&
V6
Y7
YB
A7
AS
GND
TL/F/5341-1
Top View
Order Number MM54HC54OJ or MM74HC540J, N
See NS Package J20A or N20A
Dual-In-Llne Package
Vee
G2
Yl
Y2
V3
Y4
YS
Y&
Y7
YB
iii
Al
A2
A3
A4
AS
AS
A7
A8
GND
TUF/5341-2
Top View
Order Number MM54HC541J or MM74HC541J, N
See NS Package J20A or N20A
3-295
,
Absolute Maximum Ratings (Notes 1 & 2)
-0.5 to +7.0V
Supply Voltage (Vee)
DC Input Voltage (VIN)
-1.5toVee+ 1.5V '
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
±20mA
Clamp Diode Current (Ico)
±35mA
DC Output Current, per pin (lOUT)
±70mA
DC Vee or GND Current, per pin (ICC)
-65·C to + 150·C
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
500mW
260·C
Lead Temp. (TLl (Soldering 10 seconds)
Operating Conditions
Supply Voltage (Vee>
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
VCC=2.0V
(t" ttl
Vee=4.5V
Vee=6.0V
U~lts
Min
2
0
Max
6
Vee
V
V
-40
-55
+85
+125
·C
' ·C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
TA=25"C
Vee
Typ
74HC
TA= -40t085"C
54HC
TA= -55 to 125·C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5 (
3.15
4.2
V
V
V
VIL
Maximum low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN=VIH orVIL
IiOUT!:S:20 p,A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.W
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
!IOUT!:S:6.0 mA
!IOUT!:S:7.8 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
Ok
0.4
V
V
VIN = VIH or VIL
IiOUT!:S:6.0 mA
!IOUT!:S:7.8mA
VOL
Maximum Low Level
Output Voltage
VIN=VIH orVIL
!IOUT! :s: 20 p.A
liN
Maximum Input
Current
VIN= Vee or GND'
6.0V
±0.1
±1.0
±1.0
p,A
IOZ
Maximum TRI-STATE
Output Leakage
Current
VIN=VIHorVIL, G=VIH
VouT=VccorGND
6.0V
±0.5
±5
±10
p,A
Maximum Quiescent
6.0V
8.0
80
160
p,A
VIN=VeeorGND
Supply Current
IOUT=Op,A
Note 1: Absolute Maximum Ratings are 1hose values beyond which damage to the device may occur.
No1a ,2: Unless otherwise specified all voltages are referenced to ground.
No1a 3: Power Dissipation temperature derating - plastic "N" package: -12 mWI"C from 6S·C to 8S·C; ceramic "J" package:' -12 mWI"C from 1OO·C to 12S·C.
Nota 4: For a power supply of SV ± 10% the worst case output voltages (YOH, and VoU occur for HC at4.5V. Thus the 4.SV values should be used when designing
with this supply. Worst case VIH and VIL occur at VCC= S.SV and 4.SV respectively. (The VIH value atS.SV Is 3.85V.) The worst case leakage current (liN. ICC. and
IOZ> occur for CMOS at the higher voltage and so the 6.0V values should be used.
lee
.
,
3-296
AC Electrical Characteristics Vcc=5V. TA=25'C. tr =tf=6 ns
Parameter
Symbol
Conditions
Typ
, Guaranteed
Limit
Units
tPHL. tpLH
Maximum Propagation
Delay (540)
CL =45 pF
12
18
ns
tpHL. tpLH
Maximum Propagation
Delay (541)
CL =45 pF
14
20
ns
tPZH. tPZL
Maximum Output Enable
Time
RL= k!l
CL =45pF
17
28
ns
tpHZ. tpLZ
Maximum Output Disable
Time
RL= k!l
CL=5 pF
15
25
ns
AC Electrical Characteristics Vcc=2.0V to 6.0V. CL =50 pF. tr =tf=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25'C
Vee
Typ
tpHL. tpLH
tpHL. tpLH
tPZH. tPZL
Maximum Propagation
Delay (540)
Maximum Propagation
Delay (541)
Maximum Output Enable
Time
74HC
TA= -40 to 85'C
54HC
TA= -55to 125'C
Units
Guaranteed Limits
CL =50pF
CL =150 pF
2.0V
2.0V
55
83
100
150
126
190
149
224
ns
ns
CL =50pF
CL=150pF
4.5V
4.5V
12
22
20
30
25
38
30
45
ns
ns
CL =50pF
'6.0V
CL=150pF 6.0V
11
18
17
26
21
32
25
38
ns
ns
CL =50pF
CL=150pF
2.0V
2.0V
58
83
115
165
145
208
171
246
ns
ns
CL =50pF
CL=150pF
4.5V
4.5V
14
17
23
33
29
42
34
49
ns
ns
CL =50pF
CL=150pF
6.0V
6.0V
11
14
20
28
25
35
. 2942
ns
ns
CL =50pF
CL =150 pF
2.0V
2.0V
75
100
150
200
189
252
224
298
ns
ns
CL =50pF
CL =150 pF
4.5V
4.5V
15
30
30
40
38
50
45
60
ns
ns
CL =50pF
CL=150pF
6.0V
6.0V
13
17
26
34
32
43
38
51
ns
ns
2.0V
4.5V
6.0V
75
15
13
150
30
26
189
38
32
224
45
38
ns
ns
ns
2.0V
4.5V
6.0V
25
7
6
60
12
10
75
15
13
90
18
15
ns
ns
ns
I
RL =1 k!l
tpHZ. tpLZ
Maximum Output Disable
Time
RL =1 k!l
CL =50 pF
trHL. trLH
Maximum Output Rise
and Fall Time
CL =50 pF
CPO
Power Dissipation
Capacitance (Note 5)
OC=Vcc
OC=GND
CIN
Maximum Input
Capacitance
--
pF
pF
10
50
5
10
10
10
pF
pF·
Maximum Output Capacitance
20
20
20
15
Note 5: Cpo determines the no loed dynamic power consumption, Po= Cpo Vcc;2 1+ IcC Vce. and the no load dynamic current consumption, 15 = CPO Vee 1+ Icc.
GoUT
,
3-297
~ r--------------------------------------------------------------------------------,
:g
(,)
:::c
~National·
\
~
~ Semiconductor
~
MM54HC563/MM74HC563
TRI-STATE® Octal O-Type Latch with Inverted Outputs
:IE
:IE'
'Oil'
."
:IE
:IE
")
microCMOS
General Description
These high speed octal Ootype latches utilize
microCMOS Technology, 3.5 micron silicon gate P-well
CMOS. They possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as
well as the ability to drive 15 LS-TTL loads. Due to the large
output drive capability and the TRI-STATE feature, these
devices are ideally suited for interfacing with bus lines in a
bus organized system.
When the LATCH ENABLE (LE) input is high, the Q outputs
will follow the inversion of the 0 inputs. When the LATCH
ENABLE goes low, data at the 0 inputs will be retained at
the outputs until LATCH ENABLE returns high again. When
. a high logic level is applied to the OUTPUT CONTROL (OC)
input, all outputs go to a high impedance state, regardless
of what signals are present at the other inputs and the state
of the storage elements.
.
The 54HC/74HC logic family is speed, function and pin-out
compatible with the standard 54LS/74LS logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to Vee and ground.
. Features
•
•
•
•
•
•
•
Typical propagation delay: 13 ns
Wide operating voltage range: 2 to 6 volts
Low input current: 1 p.A maximum
Low quiescent current: 80 p.A maximum (74 Series)
Compatible with bus-oriented system~
Output drive capability: 15 LS-TTL loads
Functionally compatible with '580
Connection Diagram
Dual-In-Llne Package
Vee
lD
OUTPUT 1D
2D
3D
4D
50
&0
7i1
LATCH
8i1 ENA8LE
5D
6D
7D
8D
GND.
Tl/F/S210-1
Top' View
CONTROL
Order Number MM54HC563J or MM74HC563J, N
See NS Package J20A or N20A
Truth Table
Output
Control
Latch
Enable
L
L
L
H
H
H
L
X
Data
Output
H
L
L
H
00
X
X
Z
= high level, L = low level
00= level of output before steady-state input
H
conditions were established
Z
= high impedance
3-298
Absolute Maximum Ratings (Notes 1 & 2)
-0.5 to +7.0V
Supply Voltage (Vee>
DC Input Voltage (VIN)
-1.5 to Vee + 1.5V
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
±20mA
Clamp Diode Current (Ice>
DC Output Current, per pin (lOUT)
±35mA
±70mA
DC Vee or GND Current, per pin (Ice>
-65·Cto +150·C
Storage Temperature Range (T8TG)
Power Dissipation (Po) (Note 3)
500mW.
260·C
Lead Temp. (TO (Soldering 10 seconds)
Operating Conditions
Supply Voltage (Vee>
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TAl
MM74HC
MM54HC
Min
2
Max
6
Units
V
0
Vee
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
(tr, ttl
Vee=2.0V
Vee=4.5V
Vee=6.0V
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25·C
Typ
74HC
54HC
TA= -40 to 85·C TA=-55t0125·C Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level Input
Voltage
2.0V
4.5V
6.0V
0.3
0.9·
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN=VIH orVIL
lJouTI::;;20 poA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIHorVIL
IIOUTI::;;6.0 mA
IIOUTI::;;7.8mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = Vee or GND
VIN = VIH or VIL
IIOUTI ::;; 6.0 mAo
IIOUTI::;;7.8mA
VOL
Maximum Low Level
Output Voltage
VIN=VIHorVIL
lJouTI ::;; 20 poA
liN
Maximum Input Current
6.0V
±0.1
±1.0
±1.0
poA
loz
Maximum TRI-STATE Output Voui" = Vee or GND 6.0V
Leakage Current
OC=VIH
±0.5
±5.0
±10
poA
160
poA
Maximum Quiescent Supply VIN = Vee or GND
8.0
80
Current
IOUT=O poA
Note 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic UN" package: -12 mWr'C from 65'C to B5'C; ceramic uJ" package: -12 mWI'e from 100'C to 125'C.
Note 4: For a power supply of 5V ± 10% the worst case outputvoltages (VOH, and VoLl occur for HC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at VCC= 5.5V and 4.5V respectively. (The VIH value a15.5V is 3.B5V.) The worst case leakage current (liN. ICC. and
lozl occur for CMOS at the higher voltage and so the B.OV values should be used.
Icc
,
3-299
AC Electrical Characteristics Vcc=5V. TA=25°C. t r =tf=6 ns
Guaranteed
Limit
Units
12
19
ns
12
20
ns
RL =1 kG
CL =45pF
13
25
ns
RL =1 kG
CL =5 pF
11
20
ns
10
'2
15
ns
5
ns
10
16
ns
Symbol
Parameter
Conditions
Typ
tpHL. tpLH
Maximum Propagation Delay. Data to Q
CL =45pF
~PHL. tpLH
Maximum Propagation Delay. LE to Q
CL =45pF
tPZH. tPZL
Maximum Output Enable Time
tpHZ. tpLZ
Maximum Output Disable Time
ts
Minimum Set Up Time
tH
Minimum Hold Time
Minimum Pulse Width
two
AC Electrical Characteristics Vcc=2.0-6.0V.tr=tf=6 ns
Symbol
Parameter
Conditions
Vee
TA=25°C
Typ
tpHL. tpLH
tpHL. tpLH
tPZH. tPZL
/'
Maximum Prop,!gation
Delay. Data to Q
Maximum PrQPagation
Delay. LE to Q
Maximum Output Enable
Time·
74HC
TA= -40 to 85°C
,54HC
TA=-55t0125°C
Units
Guaranteed Limits
CL =50 pF
CL=150pF
2.0V
2.0V
45
58
110
150
138
188
165
225
ns
ns
CL =50pF
CL =150pF
4.5V
4.5V
14
21
22
30
28
38
33
40
ns
ns
CL =50 pF
CL=150pF
6.0V
6.0V
12
19
19
26
24
33
29
39
ns
ns
CL =50 pF
CL=150pF
2.0V
2.0V
46
60
115
155
143
194
173
233
ns
ns
CL =50pFCL=150pF
4.5V
4.5V
14
21
23
31
29
47
35
47
ns
ns
CL =50 pF
CL =150pF
6.0V
6.0V
12
19
20
27
25
34
30
41
ns
ns
C L =50 pF
CL =150pF
2.0V
2.0V
55
67
140
180
175
225
210
270
ns
ns
CL =50pF
CL=150pF
4.5V
4.5V
15
24
28
36
35
45
42
54
ns
ns
CL =50pF
CL=150pF
6.0V
6.0V
14
22
24
31
30
39
36
47
ns
ns
RL =1 kG
CL =50pF
2.0V
4.5V
6.0V
40
13
12
'125
25
21
156
31
27
188
38
32
ns
ns
ns
30
10
9
75
15
13
95
19
16
110
22
19
ns
ns
ns
25
5
4
31
6
5
38
7
6
RL =1 kG
tpHZ. tpLZ
Maximum Output Disable
Time
Is
Minimum Set Up Time
,Data to LE
2.0V
4.5V
6.0V
tH
Minimum Hold Time
LEtoData
2.0V
4.5V
6.0V
tw
Minimum Pulse Width. LE
or Data
2.0V
4.5V
6.0V
30
9
8
80
16
14
100
20
18
120
24
20
ns
ns
ns
iTLH. tTHL
Maximum Output Rise
and Fall Time
CL =50 pF
2.0V
4.5V
6.0V
25
7
6
60
12
10
75
15
13
90
18
15
ns
ns
ns
CPO
Power Dissipation Capacitance
(Note 5) (per latch)
OC=Vcc
OC=GND
CIN
Maximum Input Capacitance
,
30
50
5
10
10
.
ns
ns
ns
pF
pF
10
pF
Maximum Output Capacitance
15
20
20
20
pF
Note 5: CPO determines the no load dynamic power consumption. Po =CPO Vcr:! f + ICC Vee. and the no load dynamic current consumption. IS =CPO Vee f+ Icc.
COUT
3·300
.
~National
\
~ Semiconductor
")
microCMOS
MM54HC564/MM74HC564
TRI-STATE® Octal O-Type Edge-Triggered
Flip-Flop with Inverted Outputs
General Description
These octal D-type flip-flops utilize microCMOS Technology, 3.5 micron silicon gate P-well CMOS. They possess the
high noise immunity and low power consumption of standard CMOS integrated circuits as well as the ability to drive
15 LS-TTL loads. Due to the large output drive capability
and the TRI-STATE feature, these devices are ideally suited
for interfacing with bus lines in a bus organized system.
These devices are positive edge triggered flip-flops. Data at
the b inputs, meeting the set-up and hold time requirements, are transferred to the 0 outputs on positive going
transitions of the CLOCK (CK) input. When a high logic level
is applied to the OUTPUT CONTROL (OC) input, all outputs
go to a high impedance state, regardless of what signals are
present at the other inputs and the state of the storage
elements.
The 54HC174h!C logic family is speed, function, and pinout
compatible with the standard 54LS174LS logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to Vee and ground.
Features
•
•
•
•
•
•
•
Typical propagation delay: 15 ns
Wide operating voltage range: 2V-6V
Low input current: 1 p.A maximum
Low quiescent current: 80 p.A maximum (74HC Series)
Compatible with bus-oriented systems
Output drive capability: 15 LS-TTL loads
Functionally compatible with 54174LS576
Connection Diagram
Dual·ln·Llne Package
10
20
30
4li
50
6li
7Q
ao
OUTPUT lD
CONTROL
2D
3D
4D
5D
6D
7D
8D. GND
Vee
CLOCK
Tl/F/52"-'
Order Number MM54HC564J or MM74HC564J, N
See NS Package J20A or N20A
Truth Table
Output
Control
L
L
L
H
Clock
Data
Output
t
t
H
L
X
X
L
H
L
X
H
X
~
~
J-iigh Level, L - Low Level
Don't Care
TransHion from low-to·high
t
~
Z
~
High Impedance State
00
~
The level of the output before steady state
00
'z
Input conditions were established
3-301
Absolute Maximum Ratings
Operating Conditions
(Notes 1 &2)
Supply Voltage (Vee)
-0.5 to + 7.0V
DC Input Voltage (VIN)
-1.5 to Vcc+ 1.5V
-0.5 to Vcc+0.5V
DC Output Voltage (VOUT)
±20mA
Clamp Diode Current (11K. 10K>
DC Output Current. per pin (lOUT)
±35mA
DC Vee or GND Current. per pin (lee)
±70mA
Storage Temperature Range
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K. 10K)
DC Output Current, per pin (lOUT)
DC Vee or GND Current, per pin (lee)
Storage Temperature Range (Tsm)
Power Dissipation (PD) (Note 3)
Lead Temperature (TLl
(Soldering 10 seconds)
Operating Conditions
-0.5 to +7.0V
-1.5to Vee + 1.5V
-0.5 to Vee + 0.5V
±20mA
±35mA
±70mA
-65'C to + 150'C
500mW
260'C
Supply Voltage {Vee>
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
. Input Rise or Fall Times
(t,., tf)
Vee=2.0V
Vee=4.5V
Vee=6.0V
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25'C
Typ
74HC
54HC
TA= -40 to 85'C TA= -55to 125'C Units
Guaranteed Limits
VIH
Minimum High Level Input
Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level Input
Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level Output
Voltage
V
V
V
VIN = VIH or VIL
IIOUTI s: 20 /LA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
,0.1
0.1
0.1
0.1
V
V
V
VIN=VIH orVIL
IloUTI s: 6.0 mA
IIOUTIS:7.8 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = Vee or GND
VIN = VIH or VIL
IIOUTIS:6.0 mA
IIOUTI s: 7.8 mA
VOL
Maximum Low Level Output
Voltage
VIN = VIH or VIL
IIOUTI S:20 /LA
,
liN
Maximum Input Current
6.0V
±0.1
±1.0
'±1.0
/LA
loz
Maximum TRI-STATE Output VOUT= Vee or GND
6.0V
Leakage Current
OC=VIH
±0.5
±5.0
±10
/LA
Maximum Quiescent Supply
VIN=VeeorGND
Icc
, 80
Current
160
6.0V
8.0
IOUT=O /LA
/LA
Note 1: Ab'!"lute Maximum Ratings are those values beyond which damage to the device mayoccur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mW/'C from 6S'C to 8S'C; ceramic "J" package: -12 mWI'C from 1OO'C to 12S'C.
Note 4: For a power supply of SV ±10% the worst-case output voltages (YOH. and VoLl occur for HC at 4.SV. Thus the 4-SV values should be used when
designing with this supply. Worst-case VIH and VIL occur at Vcc= S.SV and 4.SV respectively. (The VIH value at 5.SV is 3.85V.) The worst-case leakage current (liN.
Icc. and loz) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3-305
AC ,Electrical Characteristics Vcc=5V. TA=25°C. t r =tf=6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
tpHL. tpLH
Maximum Propagation Delay. Data to Q
CL =45pF
12
19
ns
tpHL. tpLH
Maximum Propagation Delay. LE to Q
CL =45 pF
12
20
ns
tpZH. tpZL
Maximum Output Enable Time
RL =1 kG
CL =45 pF
13
25
ns
tpHZ. tpLZ
Maximum Output Disable Time
RL =1 kG
CL =5pF
11
20
ns
ts
Minimum Set Up Time. Data to LE
10
15
ns
tH
Minimum Hold Time. LE to Data
2
5
ns
tw
Minimum Pulse Width. LE or Data
10
16
ns
Units
AC Electrical Characteristics
Symbol
tpHL. tpLH
tpHL. tpLH
Parameter
Maximum Propagation
Delay Data to Q
Maximum Propagation
Delay. Latch Enable to Q
i
tPZH. tPZL
Maximum Output Enable
Time
Conditions
-
TA=25°C,
Vee
Typ
74HC
TA=-40to.85"C
54HC
TA=-55to125"C
Units
Guaranteed Limits
CL =50pF
CL=150pF
2.0V
2.0V
45
58
110
150
138
188
165
225
ns
ns
CL =50pF
CL =150 pF
4.5V
4.5V
14
21
22
30
28
38
33
40
ns
ns
CL=50pF
CL =150 pF
6.0V
6.0V
12
19
19
26
24
33
29
39
ns
ns
CL =50pF
CL =150 pF
2.0V
2.0V
46
60
115
155
143
194
173
233
ns
ns
CL =50pF . 4.5V
CL =150pF 4.5V
14
21
23
31
29
47
35
47
ns
ns
CL =50pF
CL =150pF
6.0V
6.0V
12
19
20
27
25
34
30
41
ns
ns
CL =50pF
CL =150pF
2.0V
2.0V
55
67
140
180
175
225
210
270
ns
ns
CL =50 pF
CL =150pF
4.5V
4.5V
15
24
28
36
35
45
42
54
ns
ns
CL =50 pF
CL =150pF
6.0V
6.0V
14
22
24
31
30
39
36
47
ns
ns
RL =1 kG
CL =50pF
2.0V
4.5V
6.0V
40
13
12
125
25
21
156
31
27
188
38
32
ns
ns
ns
30
10
9
75
15
13
95
19
16
110
22
19
ns
, ns
ns
25
5
4
31
6
5
38
7
6
ns
ns
ns
RL =1 kG
n
tpHZ. tpLz
Maximum Output Disable
Time
ts
Minimum Set Up Time
DatatoLE
2.0V
4.5V
6.0V
tH
Minimum Hold Time
LEto Data
2.0V
'4.5V
6.0V
tw
Minimum Pulse Width LE.
or Data
2.0V
4.5V
6.6v
30
9
8
80
16
14
100
20
18
120
24
20
ns
ns
ns
tTLH. tTHL
Maximum Output Rise
and Fall Time. Clock
CL '7'50pF
2.0V·
4.5V
6.0V
25
7
6
60
'12
10
75
15
13
90
18
15
ns
ns
ns
CPD
Power Dissipation Capacitance
(Note 5) (per latch)
OC=Vcc
OC=GND
CIN
Maximum Input Capacitance
5
10
10
10
pF
GoUT
Maximum Output
Capacitance
15
20
20
20
pF.
pF
pF
30
50
Note 5: CPO determines the no load dynamic power consumption, Po ~ CPO Vee! f + Icc Vcr:;. and. the no load dynamic cUrrent consumption, IS ~ Cpo.vCc f+ ICC.
3·306
J?A National
~.Semiconductor
microCMOS
MM54HC574/MM7 4HC57 4
TRI-STATE® Octal D-Type Edge-Triggered Flip-Flop
General Description
These high speed octal D-type flip-flops utilize microCMOS
Technology, 3.5 micron silicon gate P-well CMOS. They
possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the
ability to drive 15 LS-TTL 10o\lds. Due to the large output
drive capability and the TRI-STATE feature, these devices
are ideally suited for interfacing with bus lines in a bus organized system.
These devices are positive edge triggered flip-flops. Data at
the D inputs, meeting the set-up and hold time requirements, are transferred to the 0 outputs on positive going
transitions of the CLOCK (CK) input. When a high logic level
is applied to the OUTPUT CONTROL (OC) input, all outputs
go to a high impedance state, regardless of what signals are
present at the other inputs and the state of the storage
elements.
The 54HC174HC logic family is speed, function, and pinout
compatible with the standard 54LS174LS logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to Vee and ground.
features
•
•
•
•
•
•
Typical propagation delay: 13 ns
Wide operating voltage range: 2V-6V
Low input current: 1 p.A maximum
Low quiescent current: 80 p.A maximum
Compatible with bus-oriented systems
Output drive capability: 15 LS-TTL loads
Connection Diagram
Dual-In-Llne Package
Vee
10
20
30
40
50
60
70
80
CLOCK
OUTPUT 1D
CONTROL
2D
3D
40
5D
60
70
80
GNO
TL/F/5213-1
Top View
Order Number MM54HC574J or
MM74HC574J, N
See NS Package J20A or N20A
Truth Table
Output
Cont~ol
L
L
L
H
Clock
Data
Output
t
t
H
L
H
L
X
X
00
X
L
high level, L ~ low level
don't care
t ~ transition from low-to·hlgh
Z ~ high impedance state
H
X
~
=
00 ~ the level of the output before steady state
input conditions were established
Z
3-307
'.
Absolute Maximum Ratings
Supply Voltage (Vee)
DC Input Voltage (VIN)
. DC Output Voltage (VOUT)
Clamp Diode Current (11K, 10K)
DC Output Current, per pin (lOUT)
DC Vee or GND Current, per pin (IcC>
Storage Temperature 'Range (T8TG)
Power Dissipation (Po) (Note 3)
Lead Temperature (TLl
(Soldering 10 seconds)
Operating Conditions
(Notes 1 &2)
-0.5 to + 7.0V
-1.5toVee+ 1.5V
-0.5 to Vee+0.5V
±20mA
±35mA
±70mA
-65'C to + 150'C
500mW
Supply Voltage (VeC>
DC Input or Output Voltage
(VIN,VOUT)
Operating Temp. Range (TAl
MM74HC
MM54HC
Input Rise or Fall Times
(t,., t,)
Vee=2.0V
Vee=4.5V
Vec.=6.0V
260'C
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
74HC
54HC
TA= -40t085'C TA= -55to 125'C Units
TA=25'C
Typ
Guaranteed Limits
VIH
Minimum High Level Input
Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level Input
Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0:9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level Output
Voltage
VIN = VIH or VIL
IIOUTIS:20 /JoA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIHorVIL
IIOUTI s: 6.0 mA
IIOUTIS:7.8 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VeeorGND
6.0V
±0.1
±1.0
±1.0
poA
6.0V
±0.5
±5.0
±10
p.A
VIN = VIH or VIL
IloUTI S:6.0 mA
IIOUTI s: 7.8 mA
-VOL
Maximum Low Level Output
Voltage
-
VIN = VIH or VIL
IloUTI s: 20 poA
liN
Maximum Input Current
loz
Maximum TRI-STATE Output VOUT= Vee or GND
Leakage Current .
OC=VIH
.'
Maximum Quiescent Supply VIN = Vee or GND
6.0V
8.0
Current
80
160
p.A
IOUT=O/JoA
I
Note 1: Maximum Ratings are those val~es beyond which damag~ to the device may occur.
Nole 2: Unless othelWise specified all voltages ara referenced to ground.
Nola 3: Power Dissipation temperature derating - plastic "N" package: -12 mWI"C from 65'C to 85'C; ceramic "J" package: -12 mW {'C from l00'C to 125'C.
Nole 4: For a power supply of 5V ± 10% the worst·case output voltages (VOH. and Vou occur for HC at 4.5V. Thus the 4.5V values should be uSed when
designing wnh this supply. Worst-case VIH and VIL occur at Vee = 5.5V and 4.5V respactively. (The VIH value at 5.5V Is 3.85V.) The worst-case leakage current (liN.
Icc. and loz) occur for CMOS at the higher voltage and so the 6.0V values should be used. ,
' .
lee
,
3-308
AC Electrical Characteristics Vcc=5V, TA=25'C, t r =tf=6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
fMAX
Maximum Operating Frequency
50
35
MHz
tpHL, tpLH
Maximum Propagation Delay, Clock to Q
CL =~5pF
12
20
ns
tpZH, tPZL
Maximum Output Enable Time
RL =1 kn
CL =45pF
13
25
ns
tpHZ, tpLZ
Maximum Output Disable Time
RL =1 kn
CL =5 pF
11
20
ns
ts
Minimum Setup Time, Data to Clock
20
ns
tH
Minimum Hold Time, Clock to Data
0
ns
tw
Minimum Pulse Clock Width
16
ns
8
AC Electrical Characteristics Vcc=2.0-6.0V, CL =50 pF, t r =tf=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25'C
Vee
Typ
fMAX
Maximum Operating Frequency
CL =50 pF
2.0V
4.5V
6.0V
tpHL, tpLH
Maximum Propagation
Delay, Clock to Q
CL =50pF
.CL =150pF
2.0V
2.0V
CL =50 pF
CL =150pF
tpZH, tPZL
Maximum Output Enable
Time
"
74HC
TA= -40 to 85'C
.
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
6
30
35
5
24
28
4
20
23
MHz
MHz
MHz
40
51
115
155
143
194
173
233
ns
ns
4.5V
4.5V
13
19
23
31
29
47
35
47
ns
ns
CL =50pF
CL =150pF
6.0V
6.0V
12
18
20
27
25
34
30
41
ns
ns
RL =1 kn
CL =50pF
CL=150pF
2.0V
2.0V
45
59
140
180
175
225
210
270
ns
ns
CL =50pF
CL =150 pF
4.5V
4.5V
14
20
28
36
35
45
42
54
ns
ns
CL =50 pF
CL =150pF
6.0V
6.0V
12
18
24
31
30
39
36
47
ns
ns
RL =1 kn
CL =50pF
2.0V
4.5V
6.0V
35
12
10
125
25
21
156
31
27
188
38
32
ns
ns
ns
IpHZ, tpLZ
Maximum Output Disable Time
Is
Minimum Setup Time
Data to Clock
2.0V
4.5V
6.0V
100
20
17
125
25
21
150
30
25
ns
ns
ns
tH
Minimum Hold Time
Clock to Data
2.0V
4.5V
6.0V
0
0
0
0
0
0
0
0
0
ns
ns
ns
tTHL, tTLH
Maximum Output Rise
and Fall Time
tw
CL =50 pF
2.0V
4.5V
6.0V
25
7
6
60
12
10
75
15
13
90
18
15
ns
ns
ns
Minimum Clock Pulse Width
2.0V
4.5V
6.0V
30
9
8
80
16
14
100
20
18
120
24
20
ns
ns
ns
tr,tf
Maximum Clock Input Rise
and Fall Time
2.0V
4.5V
6.0V
1000
500
'400
1000
500
400
1000
500
400
ns
ns
ns
CPO
Power Dissipation Capacitance
(Note 5) (per latch)
CIN
Maximum Input Capacitance
5
10
.10
10
pF
GoUT
Maximum Output Capacitance
15
20
20
20
pF
OC=VCC
OC=GND
30
50
pF
pF
Note 5: CPO determines the no load dynamic power consumption, Po= Cpo Vcc2 f+ Icc Vee, and the no load dynamic current consumption, Is = CPO Vcc f+ Icc.
3-309
•
~
..,...
II)
o
::c
:IE
:IE
....m
CD
..
II)
o
::c
II)
:IE
:IE
~National
PRI'LIMINARY r::~
~ Semiconductor
.
microCMOS
MM54HC589/MM74HC589
8-Bit Shift Registers with Input Latches
and TRI-STATE® Serial Output
General Description
Features
This high speed shift register utilizes microCMOS Technology, 3.5 micron silicon gate P-well CMOS, to achieve the high
noise immunity and low power consumption of standard
CMOS integrated circuits, as well as the ability to drive 15
LS-TTL loads. .
The 'HC589 comes in a 16-pin package and consists of an
8-bit storage latch feeding a parallel-in, serial-out 8-bit shift
register. Data can also be entered serially the shift register
through the SER pin. Both the storage register and shift
register have positive-edge triggered clocks, RCK and SCK,
respectively. SLOAD pin controls parallel LOAD or serial
shift operations for the shift register. The shift register has a
TRI-STATE output to enable the wire-ORing of multiple devices on a serial bus.
The 54HC/74HC logic family is speed, function, and pin-out
compatible with the standard 54LS174LS logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to Vee and ground.
•
•
•
•
•
•
Connection Diagram
8-bit parallel storage register inputs
Wide operating voltage range: 2V-6V
Shift register has direct overriding load
Guaranteed 'shift frequency. . . DC to 30 MHz
Low quiescent current: 80 /LA maximum (74HC Series)
TRI-STATE output for 'Wire-OR'
. Truth Table
Dual-in-Line Package
8..1.
'-'
RCK
t
t
~A
D..!.
r1i SER
E..i.
~SLDAD
Fi
~RCK
G.!.
.!lSCK
H.l.
l!!.tiE
GND..!.
LOH
Function
X
,X
X
Data loaded to input latches
X
L
H
Data loaded from inputs to
shift register
No
clock
edge
X
L
H
X
X
X
L
Serial output in high
impedance state
X
t
H
H
Shift register clocked
ON·=On_1,OO=SER
~VCC
c..l.
SCK SLOAD OE
.
TL/F/536B-l
Top View
Order Number MM54HC589J or MM74HC589J,N
See NS Package J16A or N16E
3-310
Data transferred from
input latches to shift
register
Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage (Veel
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K. 10K>
DC Output Current. per pin (lour)
DC Vee or GND Current. per pin (Icc)
Storage Temperature Range (TsrG)
Power Dissipation (Po) (Note 3)
Lead Temperature (TLl
(Soldering 10 seconds)
Operating Conditions
-0.5 to +7.0V
Supply Voltage (Veel
DC Input or Output Voltage
(VIN. Vour)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
Vcc=2.0V
(tr. tf)
Vcc=4.5V
Vee=6.0V
-1.5 to Vee+1.5V
-0.5 to Vee+0.5V
±20mA
±25mA
±50mA
-65·C to + 150·C
500mW
26Q·C
Min
2
0
Max
6
Vcc
Units
V
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=2S·C
74HC
TA=-40to85"C
Typ
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
VOH
Minimum High Level
Output Voltage
..
VOL
Maximum Low Level
Output Voltage
~,
VIN = VIH or VIL
!lour!';;20 ",A
VIN=VIHorVIL
!lour!';;4.0 mA
!Iour! ,;; 5.2 mA
VIN=VIHorVIL
!lourl';;20 ",A
VIN=VIHorVIL
Ilourl';;4.0 mA
-liourl ,;; 5.2 mA
liN
Maximum Input
Current
VIN=VCC or GND
S4HC
TA=-SSto12S·C
Units
Guaranteed Limits
2.0"
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
2.0V
4.5V
6.0V
0.3
0.9
'1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
3.98
5.48
3.84
5.34
3.7
5.2
V
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
4.5V
6.0V
0.26
0.26
0.33
0.33
0.4
0.4
V
V
6.0V
±0.1
±1.0
±1.0
",A
80
160
",A
2.0V
4.5V
6.0V
2.0
4.5
6.0
4.5V
6.0V
2.0V
4.5V
6.0V
0
0
0
Maximum Quiescent VIN = Vee or GND 6.0V
8.0
Supply Current
lour=O",A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Icc
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mW/'C from 6S'C to 8S'C; ceramic "J" package: -12 mWI'C from 1OO'C to 12S'C.
Note 4: For a power supply of SV ±10% the worst case output voltages (VOH. and VoLl occur for HC at 4.SV. Thus the 4.SV values should be used when
designing with this supply. Worst case VIH and Vic occur at Vce=5.SV and 4.SV respectively. (The VIH value at S.SV Is 3.8SV.) The worst case leakage current (liN.
Ice. and lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
3·311
AC Electrical Characteristics Vcc= 5V, TA= 25"C, CL = 15 pF, t,c=t,= 6 ns
Typ
Guaranteed Limit
Units
50
30
MHz
Maximum Propagation Delay from SCK to OH' ,
30
ns
tpHL, tpLH
Maximum Propagation Delay from SLOAD to OH'
30
ns
tpHL, tpLH
Maximum Propagation Delay from LCK to OH'
SLOAD = logic '0'
25
45
ns
tpZH, tPZL
Output Enable Time
RL =1 kG
18
28
ns
tpHZ, tpLZ
Output Disable Time
RL =1 kG, CL =5pF
19
25
ns
Is
Is
Is
Minimum Setup Time from RCK to SCK
10
20
ns
- Minimum Setup Time from SER to SCK
10
20
ns
Minimum Set4P Time from Inputs A thru H to RCK
10
20
ns
tH
Minimum Hold Time
0
5
ns
tw
Minimum Pulse Width SCK, RCK, SLOAD
8
16
ns
Symbol
Parameter
fMAX
Maximum Operating Frequency for SCK
tpHL, tpLH
Conditions
,-
AC Electrical Characteristics Vee = 2.0-6V, CL = 50 pF, tr =t,=6 ns (unleSs otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=25°C
Typ
Unite
Guaranteed Umlts
,4
21
25-
4
18
21
MHz
MHz,
MHz
62
20
18
175
35
30
220
43
37
266
52
45
ns
ns
ns
2.0V
4.5V
6.0V
120
31
28
225
45
38
284
57
48
335
67
57
ns
ns
ns
Maximum Propagation'
Delay from RCK to OH
2.0V
4.5V
6.0V
80
25
,21
210
42
36
265
53
45
313
53
ns
ns
ns
Maximum Propagation
Delay RCK to OH
2.0V
4.5V
6.0V
80
25
21
210
52
44
265
66
56
313
77
66
ns
ns
ns
RL =1 kG
2.0V
4.5V
6.0V
70
22
20
150
30
26
189
38
32
224
45
38
ns
ns
ns
RL =1 kG
2.0V
4.5V
6.0V
70
22
20
150
30
26
189
38
32
224
,,45
38
ns
ns
ns
Maximum Operating
F~equency for SCK
2.0V
4.5V
6.0V
tpHL, tpLH
Maximum Propagation
Delay from SCK or SLOAD
toOH
2.0V
4.5V
6.0V
tpHL, tpui
Maximum Propagation
Delay from SCK or SLOAD
,
toOH
tpHL, tpLH
54HC
TA=-55to125"C
5
27
32
fMAX
tpHL, tpLH
74HC <;,
TA=-40to85"C
CL=150pF
CL =150pF
63
tpZH, tPZL
Output Enable Time
tpHZ, tpLZ
Output Disable Time
Is
Minimum Setup Time
from RCK to SCK
2.0V
4.5V
6.0V
100
20
17
125
25
22
150
30
25
ns
ns
ns
Is
Minimum Setup Time
from SER to SCK
2.0V
4.5V
6.0V
100
20
17
125
25
22
150
30
25
ns
ns
ns
Is
Minimum Setup Time
from Inputs A thru H
toRCK
2.0V
4.5V
6.0V
100
20
17
125
25
,22
150
30
25
ns
ns
ns
1H
Minimum Hold Time'
2.0V
4.5V
6.0V
5
5
5
5
5
5
5
5
5
ns
ns
' ns
,
-5
0
1
3-312
-
AC Electrical Characteristics
(Continued)
VCc=2.0-6V, CL =50 pF, t r =t,=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
74HC
54HC
TA = -40 to 85°C TA= -55to 125°C Units
TA=25"C
Typ
tw
t r, t,
Minimum Pulse Width
SCK, RCK, SLOAD, SLOAD
2.0V
4.5V
6.0V
Maximum Input Rise and
Fall Time, Clock
2.0V
4.5V
6.0V
tTHL, trLH Maximum Output
Rise and Fall Time
2.0V
4.5V
6.0V
CPO
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input Capacitance
30
9
8
25
6
5
Guaranteed Limits
80
16
14
100
20
17
120
24
20
ns
ns
ns
1500
500
400
1500
500
400
1500
500
400
ns
ns
ns
60
12
10
75
15
12
90
18
15
ns
ns
ns
pF
5
10
10
10
pF
Maximum Output Capacitance
15
20
20
20
pF
COUT
Nole 5: Cpo determines the no load dynamic power ccnsumption, Po=Cpo Vee!- f+1ee Vee. and the· no load dynamic current consumption,
Is=Cpo Vee sf+1cc·
Logic Timing Diagram
1lE
---,
MM54HC589/MM74HC589
I
L-I
SiJ!AIj
SCK
n
RCK
I
SER
A
~ D~N'T' C~R~'m
~DON'TCARE~
B
~ DON'T CARE ~
~DON'TCARE~
C
~ DON'T CARE ~
~DON'TCAREW~
D
~ DDN'T CARE ~
~DON'TCAREW"~
E
~ DON'T CARE m
~DON'TCARE~
F
~ ~&~'T CAREm
.,
G
mDDN'T,~~REm
&&A~T CARE
H
~~ON'TmEE
~p~;r CAR~
OH'
f(@.HN~
...
Do;tt'dA~~
" .
,
I
TL/F/5368-3
I
3-313
Functional Block Diagram
(positive logic)
MM54HC589/MM74HC589
OUTPUT ENABLE 10
SER . : . ; ; . . . - - - - - - - - - - - - - - - - - - .
STAGE A
RCK
PARALLEL
DATA
INPUTS
C~2,_ _ _ _-t
D3
---
------
----t
L
______
______
L------~~------4
~~
~
L ______ !!!E!, _______ -I
..;;.6-------4L ______
_____ --I
~~
G
I ---
STAGEG"
--SrAGEH--
----t
I
I
I
I
I
I
L____ _________ _.lI
I
~
TL/F/5368-2
3-314
~National
iii:
iii:
PRELIMINARY
CJI
\
~ Semiconductor
")
microCMOS
MM54HC590/MM74HC590
a-Bit Binary Counter with
TRI-STATE® Output Register
"":::E:o
CJI
CD
.....
C)
iii:
iii:
.......
""
oCJI
:::E:
CD
C)
General Description
These counters are implemented using an advanced 3.0
micron silicon gate N-well microCMOS process to achieve
high performance. These devices retain the low power and
high noise immunity of CMOS logic, while offering the high
speed operation and large output drive typically associated
with bipolar circuits.
The MM54HC590/MM74HC590 contain an 8-bit binary
counter which feeds an 8-bit register. The counter is incremented on the rising edge of the CCK input, provided that
clock enable, CCKEN, is low. When the counter increments
to the all ones condition, ripple carry out, RCO, will go low.
This enables either synchronous cascading of the counters
by connecting the ROO of1he first stage to the CCKEN of
the second, or clocking both circuits in parallel. Ripple cascading is accomplished by connecting the RCO of the first
to the CCK of the second stage. A clear input is also provided which will reset the counter to the all zeros state.
The output register is loaded with the contents of the counter on the rising edge of the register clock, RCK. The outputs
of this register feed TRI-STATE outputs which are enabled
when the enable input, G, is taken low. This enables connection of this part to a system bus.
The MM54HC590/M~74HC590 are functional, speed and
pin equivalent to the equivalent LS-TTL circuit. Its inputs are
protected from damage due to the electrostatic discharge
by diodes from Vee to ground.
Features
•
•
•
•
Wide power supply range: 2.0V to 6.0V
High input noise immunity
High output current drive: 6.0 mA min
Low quiescent power consumption: 80 p.A (74HC)
Connection Diagram
Dual-In-Line Package
Q8- 1
U
16
...... Vcc
Qc- 2
15 --QA
QD- 3
14 ~ii
1le-4
13 ~RCK
QF- 5
12 ~CCKEN
QG- 6
11 i-CCK
QH- 7
10 i-CCLR
GND- B
9
TOP VIEW
,
-RCli
TL/F/5772-1
Order Number MM54HC59OJ or MM74HC590J, N
See NS Package J16A or N16E
3-315
m
o
Lo9 i9 Diagram
:::a::::
t!
"
......
--V
::Ii
::Ii
.....
~
RCK
~
.~
:::a::::
'OS'
U)
::Ii
::Ii
cc.
11~
1!..........0[>.
Jc- ~
--;=:
Ln
~
R
~
~
~
~
r......
~(
0
r+1
0
~
0
~
0
~
0
~
0
.~ ~ .
4
.
r
-......
15
1
-
M
.
...... r
2
FLl·
..... r
3
aD
R1
.r
.....
-
•
~1
.r
......
5
~1
.
r
- .....
8
D
~
-±1
~1
.
...... r
7
D
TL/F/5772-2
3-316
~National
PRELIMINARY
\.
~ Semiconductor
)
microCMOS
MM54HC592/MM74HC592
.S-Bit Binary Counter with Input Register
MM54HC593/MM74HC593· S-Bit Binary Counter
with Bidirectional Input Register/Counter Outputs
General Description
These counters are implemented using an advanced 3.0
micron silicon gate N-well microCMOS process to achieve
high performance. These devices retain the low· power and
high noise immunity of CMOS logic, while offering the high
speed operation and large output drive typically associated
with bipolar circuits.
The MM54HC592/MM74HC592 and the MM54HC593/
MM74HC593 contain an 8-bit register which feeds an 8-bit
binary counter. The counter is incremented on the rising
edge of the CCK input, provided that clock enable, CCKEN,
is low. When the counter increments to the all ones condition, ripple carry out, RCO, will go low. This enables either
synchronous cascading of the counters .by connecting the
RCO of the first stage to the CCKEN of the second, or
clocking both circuits in parallel. Ripple cascading is accomplished by connecting the RCO of the first to the CCK of the
second stage. A clear input is also provided which will reset
the counter to the all zeros state.
The input register is loaded on the rising edge of the register
clock, RCK. The outputs of this register feed the counter.
The counter is loaded with the register's contents when the
clock load, CLOAD, input is taken low.
The 'HC592 differs from the 'HC593 in that the latter device
has bidirectional input/output pins. The TRI-STATEIB> outputs of the counter can be enabled and are active when
e·nable input, G, is taken low and input G is taken high. The
outputs of the counter then appear on the register inputs.
This enables connection of this part to a system bus. The
'HC593 also has a second clock enable pin, CCKEN, which
is active high and it also has an active loIN register clock
enable, RCKEN.
The MM54HC592/MM74HC592 and the MM54HC593/
MM74HC593 are functional, speed and pin equivalent to the
equivalent LS-TTL circuit. Their inputs are protected from
damage due to electrostatic discharge by diodes from Vee
to ground.
Features
•
•
•
•
Wide power supply range: 2.0V to 6.0V
High input noise immunity
High output current drive: 6.0 mA min
Low quiescent power consumption: 80 p.A (74HC)
Connection Diagrams
Dual·ln·Llne Package
MM54HC592/MM74HC592
16
Dual-In-Llne Package
MM54HC593/MM74HC593
AIDA
20
19
Vee
Vee
15
A
Blaa
14
CLOAO
C/ae
ii
0100
RCKEN
CCK
E/aE
RCK
CCLR
F/aF
CCKEN
G/CIa
CCKEN
H/Ib!
CCK
CLOAO
CCLR
RCK
CCKEN
H
GNO
RCO
TOP VIEW
TL/F/5773-1
Order Number MM54HC592J, MM54HC593J,
MM74HC592J, N or MM74HC593J, N
See NS Package J16A, J20A, N16E or N20A
GNO
10
RCO
TOP VIEW
TL/F/5773-2
3-317
~
Logic Diagrams
MM54174HC592
:J:
;:!:
::e,
::e
~
m
o
CClR
CCKEN
:J:
~
5!l
C\i
(1)
CCK
ClOAD
RCK
'"
"~
""~
(14)
(1~
....
II)
o
......
~
1-"'"
1D
"01'
......
::e
::e
f-cl> C)
N
(1)
II)
o
B
~RCO
-roo--
~
(15)
:J:
~
(I)
~
D
l
~R
a
'---
L-
,.......-,
r -"~
1D
:J:
~
L....ol>r
~
4r
"01'
-C1
II)
'---
::e
::e
C
r---""I
(2)
10
'-<=1> Cl
'---
0
I"""----J
(3)
10
~Ra
~
f0
~I>r
'""
~R a
L-
1.rJ~t4r
-Cl
'---
E
r---""I
(4)
1D
~I>Cl
I...-
F
,.......-,
(5)
1D
..2.ot>1...-'
C1
~R
a
L-
r~
M
~
.....
t-
I""'j
~
...
~I>r
~R
A
~
Ff
a
~
r---"'1
~D
It-
I>T
~R
~.
Q
~
,
G
~
(6)
1D
,
~I>C1
l...-
H
(7)
-'
1D
L...-<: I> Cl
L-
L-
~
0
LOI>T
~R
l
.... t:
Q
I...-
1
1
1
J
~
o
~I>T
L--c R
l
t-
a
~
TLlF/5773-4
3-318
Logic Diagrams (Continued)
MM54174HC593
(19)
(IB)
CCKEN
CCKEN
CC K
CLDA
o
RCKE
~i~
.rvo(14)
-
(9)
(17)
N ji6)
RCK
AI OA
...
(13)
(1)
.J;I
U
RCO
~GATING FOR RCK
IS SIMILAR IN DETAIL
TO THAT SHOWN FOR
CCK
~
~
10
"""0
L
L...oI>T .
+
......c I>Cl
I--
~R
0
(2)
IJ-=-,r10
----
-q>Cl
IOc
(3)
I.,.J~I-qT
---0 R
r---'!'
~ 0
~R
---..---
......cI>Cl
(5)
E/De
10
I-
D
~
~
~
10
L
L-oI>T
L...-..
O/DD (4)
it
*
....... '*
10
~I>Cl
0
L...-..
~
'*
-
l....-
f"
lOa
-
o
L
~R
D
~J>T
~
~
A
~
i-
~
j
Ff
~
~
,
l-"'~I-
*
1-*
- 1-*
4T
~Cl
I--
FlO,
(6)
(7)
~
o
10
LCI>T
~ R
~I>Cl
l......-
r
o
L.;;~T
~R
(B)
~
10
L-o ~Cl
I--
D
L.....
~.
D r-
~
'
~0~*
L--o
L...ol> T
R
:J
L
I....-
r
H/OH
L
L...-..
~
10
0
I--
~
~I>Cl
~
G/Do
~R
~t:.
:J
,
D
L...-..
TL/F/5773-3
3-319
:!4
U) ~---------------------------------------------------------------------------,
5 ~Nal1onal
PRELIMINARVL::
.... ~ Semiconductor
.....
::E
%
.
::E
~....
%
U)
::E
::E
.
I:
microCMOS
MM54HC595/MM74HC595
a-Bit Shift Registers with Output Latches
General Description
Features
This high speed shift register utilizes microCMOS Technology, 3.5 micron silicon gate P-well CMOS. This device possesses the high noise immunity and low power consumption
of standard CMOS integrated circuits, as well as the ability
to drive 15 LS-TIL loads.
This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage
register has 8 TRI-STATE outputs. Separate clocks are
provided for both the shift register and the storage register.
The shift register has a direct-overriding clear, serial input,
and serial output (standard) pins for cascading. Both the
shift register and storage register use positive-edge triggered clocks. If both clocks are connected together, the
shift register state will always be one clock pulse ahead of
the storage register.
The 54HC/74HC logic family is speed, function, and pin-out
compatible with the standard 54LS174LS logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to Vee and ground.
• Low quiescent current: 80 '/JoA maximum (74HC Series)
• Low input current: 1 /JoA maximum
• 8-bit serial-In, parallel-out shIft regIster
with storage
• Wide operating voltage range: 2V -6V
• Cascadable
• Shift register has direct clear
• Guaranteed shift frequency: DC to 30 MHz
Connection Diagram
Truth Table
Dual-In-Llne Package
a..L
-
'-/
~vcc
Qc..!.
.!!QA
Qu"!'
..!.
.!i SER
.!!.ii
OF..!.
.!!.RCK
Qui
~SCK
QH .1.
~$CLR
QE
~Q'H
GNO.!.
TLlF/5342-1
Top VIew
Order Number MM54HC595J or MM74HC595J, N
See NS Package J16A or N16E
,
\
3-320
RCK
SCK
SCLR
G
FunctIon
X
X
X
1
QA thru QH=TRI-STATE
X
X
L
X
Shift Register cleared
Q'H=O
X
t
H
X
Shift Register clocked
QN=Qn.l, Qo=SER
t
X
H
X
Contents of Shift
Register transferred
to output latches
Absolute Maximum Ratings
DC Input Voltage (VIN)
-1.5 to Vee + 1.5V
DC Output Voltage (VOUT)
Clamp Diode Current (11K, 10K)
DC Output Current, per pin (lOUT)
-0.5 to Vee+0.5V
±20mA
±35mA
±70mA
DC Vee or GND Current, per pin (Ieel
Storage Temperature Range (TSTG)
Power Dissipation (PD) (Note 3)
DC Electrical Characteristics
Parameter
Supply Voltage (Veel
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
(tr,tf)
Vee=2.0V
Vee=4.5V
Vee=6.0V
-65'C to + 150'C
500mW
260'C
Lead Temp. (T L.l (Soldering 10 seconds)
Symbol
Operating Conditions
(Notes 1 & 2)
-0.5 to + 7.0V
Supply Voltage (Veel
Min
2
0
Max
6
Units
V
Vee
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
(Note 4)
Conditions
TA=25'C
Vee
74HC
TA= -40 to 85'C
Typ
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN=VIH orVIL
IIOUTI =S: 20 ",A
QH'
QA thruQH
VOL
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
VIN=VIH orVIL
!IOUT! =S: 4.0 rnA
lOUT =S:5.2mA
4.5V
6.0V
4.2
5.2
3.98
5.48
3.84
5.34
3.7
5.2
V
V
VIN=VIHorVIL
!IOUT!=S:6.0 rnA
lOUT =S:7.8 rnA
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
Maximum Low Level
Output Voltage
VIN=VIHorVIL
IIOUTI=S:20 ",A
QH'
VIN = VIH or VIL
!IOUT!=S:4 rnA
lOUT =S:5.2 rnA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = VIH or VIL
!IOUT! =S:6.0 rnA
lOUT =S:7.8 rnA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
±0.1
±1.0
±1.0
",A
QAthruQH
liN
Maximum Input
Current
VIN = Vee or GND
6.0V
loz
Maximum TRI-STAiE
Output Leakage
~OUT=Vee or GND
6.0V
±0.5
±5.0
±10
",A
Maximum Quiescent
Supply Current
VIN = Vee or GND
10UT=0 ",A
6.0V
8.0
80
160
",A
lee
•
G=VIH
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mW /'C from 65'C to 85'C; ceramic"J" package: -12 mW/'C from 1OO'C 10 125'C.
Nole 4: For a power supply of 5V ±10% the worst case output voltages (YOH. and VoU occur for HC aI4.5V. Thus Ihe 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at Vce = 5.5V and 4.5V respectively. (The VIH value a15.5V is 3.85V.) The worst case leakage current (liN.
Icc. and loz) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3-321
~
r------------------------------------------------------------------------------------------,
m AC Electrical Characteristics Vee = 5V. TA = 25°C. t,= tf= 6 ns
o
:E:
,....
~
Typ
Guaranteed
Limit
Units
50
30
MHz
CL =45pF
12
20
ns
Maximum Propagation
Delay. RCK to OA thru OH
CL =45 pF
18
30
ns
tpZH. tpZL
Maximum Output Enable
Time from G to OA thru QH
RL =1 k!l
CL =45 pF
17
28
ns
tpHZ. tpLZ
Maximum Output Disable
Time from G to OA thru QH
RL= k!l
CL =5pF
15
25
ns
ts
Minimum Setup Time
from SER to SCK
20
ns
ts
Minimum Setup Time
from SCLR to SCK
20
ns
ts
Minimum Setup Time
from SCK to RCK
(See Note 5)
40
ns.
tH
Minimum Hold Time
from SER to SCK
0
ns
tw
Minimum Pulse Width
ofSCKorRCK
16
ns
Symbol
Parameter
:s
:s
"-
fMAX
Maximum Operating
Frequency of SCK
o
tpHL. tpLH
Maximum Propagation
Delay. SCK to OH'
tpHL. tpLH
~
m
:E:
~
~
:s
:s
Conditions
Note 5: This setup time ensures the register will see stable data from the shift.register outputs. The clocks may be connected together in which case the storage
register state will be one clock pulse behind the shift register.
3·322
AC Electrical Characteristics Vcc=2.0-6.0V, CL =50 pF, t r =t,=6 ns (unless otherwise specified)
Symbol
Parameter
TA=25D C
Vee
CL =50pF
2.0V
4.5V
6.0V
10
45
50
5
27
32
4
21
25
4
18
21
MHz
MHz
MHz
CL =50 pF 2.0V
CL=150pF 2.0V
58
83
115
165
145
208
171
246
ns
ns
CL =50pF 4.5V
CL =150pF 4.5V
14
17
23
33
29
42
34
49
ns
ns
CL =50pF 6.0V
CL =150pF 6.0V
10
14
20
28
25
35
29
42
ns
ns
150
200
188
225
225
250
ns
ns
Typ
fMAX
Maximum Operating
Frequency
tpHL, tpLH Maximum Propagation
Delay from SCK to QH'
CL =50pF 2.0V 70
tpHL, tpLH Maximum Propagation
Delay from RCK to QA thru QH CL =150pF 2.0V 105
tpZH, tPZL Maximum Output Enable
from G to QA thru QH
tpHZ, tpLZ Maximum Output Disable
Time from G to QA thru QH
74HC
54HC
TA= -40 to 85D C TA= -55to 125D C Units
Guaranteed Limits
Conditions
CL =50pF 4.5V
CL =150pF 4.5V
21
28
30
40
38
50
45
60
ns
ns
CL =50pF 6.0V
CL =150pF 6.0V
18
26
26
34
33
43
39
51
ns
ns
RL =1 kO
CL =50pF 2.0V 75
CL =150pF 2.0V 100
150
200
189
252
224
298
ns
ns
CL =50 pF 4.5V
CL =150pF 4.5V
15
20
30
40
38
50
45
60
ns
ns
CL =50pF 6.0V
CL=150pF 6.0V
13
17
26
34
32
43
38
51
ns
ns
2.0V
4.5V
6.0V
75
15
13
150
30
26
189
38
32
224
45
38
ns
ns
ns
RL =1 kO
CL=50pF
ts
Minimum Setup Time
from SER to SCK
2.0V
4.5V
6.0V
100
20
17
125
25
21
150
30
25
ns
ns
ns
ts
Minimum Setup TIme
from SCLR to SCK
2.0V
4.5V
6.0V
100
20
17
125
25
21
150
30
25
ns
ns
' ns
ts
Minimum Setup TIme
from SCK to RCK
2.0V
4.5V
6.0V
200
40
34
250
50
42
300
60
50
ns
ns
ns
tH
Minimum Hold Time
SERtoSCK
2.0V
4.5V
6.0V
0
0
0
0
0
0
0
0
0
ns
ns
ns
tw
Minimum Pulse Width
of SCK or RCLK
2.0V
4.5V
6.0V
80
16
14
100
20
18
120
24
22
ns
ns
ns
t r, tf
Maximum Input Rise and
Fall TIme, Clock
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
60
12
10
75
15
13
90
18
15
ns
ns
ns
tTHL, tTLH Maximum Output
Rise and Fall Time
30
9
8
25
7
6
2.0V
4.5V
6.0V
CPO
Power Dissipation
Capacitance, Outputs
Enabled (Note 6)
CIN
Maximum Input
Capacitance
5
10
10
10
pF
GoUT
Maximum Output
Capacitance
15
20
20
20
pF
§=Vcc
G=GND
90
150
pF
pF
Note 6: CPO determines the no load dynamic power consumption. Po=Cpo Vee< f+lee Vee. and the no load dynamiC current consumption.
15= Cpo Veef+loo
3·323
Logic Diagram
(positive logic)
RCK
SER
PARAUEL
DATA OUTPUTS
'°----01
SERIAL DATA
OUTPUT
mil ..
TL/F/5342-3
3-324
~National
PRELIMINARY
~ Semiconductor
r: \
~
microCMOS
MM54HC597/MM74HC597
a-Bit Shift Registers with Input Latches
General Description
Features \
This high speed shift register utilize microCMOS Technology, 3.5 micron silicon gate P-well CMOS. It has the high
noise immunity and low power consumption of standard
CMOS integrated circuits, as well as the ability to drive 10
LS-TTL loads.
The 'HC597 comes in a 16-pin package and consists of an
B-bit storage latch feeding a parallel-in, serial-out B-bit shift
register. Both the storage register and shift register have
positive-edge triggered clocks. The shift register also has
direct load (from storage) and clear inputs.
The 54HC174HC logic family is speed, function, and pin-out
compatible with the standard 54LSI74LS logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to Vee and ground.
•
•
•
•
•
Connection Diagram
Truth Table
Dual-In-Llne Package
B...!..
V
RCK SCK SLOAD SCLR
t
t
~A
D.l.
~
SER
rll SLDAD
~
F..!.
Function
X
X
X
Data loaded to input latches
X
L
H
Data loaded from inputs to
shift register
No
clock
edge
X
L
H
X
X
L
L
Invalid logic, state of
shift register indeterminate
when signals removed
Vee
c..l.
e.J.
RCK
Data transferred from
input latches to shift
register
G..!.
;n
H..l
.!!!. SCLA
X
X
H
L
Shift register cleared
..!.
X
t
H
H
Shift register clocked
On=On-1,Oo=SER
GND
-,
~
B-bit parallel" storage register inputs
Wide operating voltage range: 2V -6V
Shift register has direct overriding load and clear
Guaranteed shift frequency. . . DC to 30 MHz
Low quiescent current: BO /LA maximum
..!.
SCK
QH
TUF/5343-1
Top View
Order Number MM54HC597J or MM74HC597J, N
See NS Package J16A or N16E
3-325
Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage (Vee)
DC Input Voltage (VIN)
,
bC Output Voltage N.OUT)
Clamp Diode Current (11K. 10K)
DC Output Current. per pin (lOUT)
DC Vee or GND Current. per pin {IcC>
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)'
Lead Temp. (Tt.l (Soldering 10 seconds)
Operating Conditions
-0.5 to + 7.QV
-1.5toVee+ 1.5V
-0.5to'Vee+ 0.5V
±20mA
)±25mA
±50mA
- 65·C to + 150·C
..
500mW
260"C
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN.VOUT)
Operating Temp. Range (TAl
MM74HC
MM54HC
Input Rise or Fall TImes
Vee=2.0V
(tn ttl
Vee=4.5V
Vee=6.0V
Min
2
0
Max
6
Vee
Units
V-
-40
-55
+85.
+125
·C
·C
1000
500
400
ns
ns
ns
V
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25·C
74HC
TA = -'40 to 85·C
Typ
54HC
TA= -55 to 125"C
Units
Guaranteed Limits
VIH·
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
IIOUT!:5:20 p.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
'6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1 0.1
0.1
VIN = VIH or VIL
IIOUT! :5: 4.0 mA
!IOUT!:5:5.2mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = VIH or VIL
!IOUT! :5:4.0 mA
!IOUT! ':5: 5.2 mA
VOL
~aximum Low Level
Output Voltage
VIN = VIH or VIL
IIOUT!:5:20 p.A
'V
V
V
liN
Maximum Input
Current
VIN=vee or GND
6.0V
±0.1
±1.0
±.1.0
p.A
lee
Maximum Quiescent
Supply Current
VIN=VeeorGND
IOUT=Op.A
6.0V
8.0
80
160,
p.A
Note 1: Absolute Maximum Ratings are those values beyond which damage io the device may occur.
Note 2: Unless otherwise specified all voltages are re(erenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" psckage: -12 mW/'C from 65'C to 85'C; ceremic "J" package: -12 mW/'C from 100'C to 125'C.
Note 4: For a pewer supply of 5V ± 10% the worst case output voltages (VOH. and You occur for HC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at Voo = 5.5V and 4.5V respectively. (The VIH value al 5.5V is 3.85V.) The worst case leakage current (liN. 100. and
Iozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
,
-
3·326
AC Electrical Characteristics Vcc= 5V, TA = 25°C, CL = 15 pF, t r =tf=6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
fMAX
Maximum Operating
Frequency for SCK
50
30
MHz
tpHL, tpLH
Maximum Propagation
Delay from SCK to QH
20
30
ns
tpHL, tpLH
Maximum Propagation
. Delay from SLOAD to QH
20
30
ns
tpHL, tpLH
Maximum Propagation
Delay from RCK to QH
25
45
ns
SLOAD = 10gic'0'
tpHL
Maximum Propagation
Delay from SCLR to QH
20
30
ns
tREM
Minimum Removal TIme,
SCLRtoSCK
10
20
ns
Is
Minimum Setup Time
from RCt< to SCK
30
40
ns
ts
Minimum Setup Time
from SER to SCK
10
20
ns
Is
Minimum Setup Time
from Inputs A thru H
toRCK
10
20
ns
,
tH
Minimum Hold Time
-2
0
ns
tw
Minimum Pulse Width
SCK, RCK,
SLOAD
10
16
ns
scm
AC Electrical Characteristics Vcc= 2.0-6.0V, CL = 50 pF, tr= tf= 6 ns (unless otherwise specified)
v
Symbol
Parameter
Conditions
TA=25°C
Vee
Typ
74HC
TA= -40t085"C
54HC
TA= -55 to 125°C
Units
Guaranteed Limits
4
Maximum Operating
Frequency for SCK
2.0V
4.5V
6.0V
10
45
50
5
27
32
21
25
4
18
21
MHz
MHz
MHz
tpHL, tpLH
Maximum Propagation
Delay from SCK to QH
2.0V
4.5V
6.0V
62
20
18
175
35
30
220
44
38
263
53
45
ns
ns
ns
tpHL, tpLH
Maximum Propagation
Delay from SLOAD to QH
2.0V
4.5V
6.0V
65
20
18
175
35
30
220
44
38
263
53
45
ns
ns
ns
tpHL, tpLH
Maximum Propagation
Delay from RCK to QH
2.0V 120
4.5V . 30
6.0V
28
250
50
43
312
65
53
375
75
65
ns
ns
ns
175
35
30
220
44
38
263
53
45
ns
ns
ns
fMAX
SLOAD = Logie '0'
tpHL
Maximum Propagation
Delay from
to QH
2.0V
4.5V
6.0V
tREM
Minimum Removal TIme
SCLRtoSCK
2.0V
4.5V
6.0V
100
20
17
125
25
21
150
30
25
ns
ns
ns
ts
Minimum Setup Time
from RCK to SCK
2.0V
4.5V
6.0V
200
40
34
250
50
42
300
60
50
ns
ns
ns
Is
Minimum Setup Time
from SER to SCK
2.0V
4.5V
6.0V
100
20
17
125
25
21
150
30
25
ns
ns
ns
scm
,
3·327
66
20
18
AC Electrical Characteristics (Continued) CL =50 pF. fr=tf=6 ns (unless othelwise specified)
. Synibol
Parameter
Conditions
Vee
TA=25"C
74HC
TA=-40t085"C
Typ
Minimum Setup TIme
from Inputs A thru H
toRCK
2.0V
4.5V
6.0V
100
20
tH
Minimum Hold Time
2.0V
4.5V
6.0V
tw
Minimum Pulse Width
SCK. RCK. SCLR. SLOAD
2.0V
4.5V
6.0V
fr. tf
Maximum Input Rise and
Fall Time
2.0V
4.5V
6.0V
trHL. trLH
Maximum Output
Rise and Fall Time
2.0V
4.5V
6.0V
CPO
Power Dissipation
Capacitance (Note 5)
CjN
Maximum Input
Capacitance
CoUT
Maximum Output
capacitance
30
10
8
Units
Gusranteed Umlts
ts
30
9
8
54HC
TA= -55 to 125"C
17
125
25
21
150
30
25
ns
ns
ns
0
0
0
0
0
0
0
0
0
ns
ns
ns
100
20
18
120
24
20
ns
ns
ns
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
75
15
13
95
19
16
110
22
19
ns
ns
ns·
80 .
16
14
pF
,.5
10
10
10
pF
15
20
20
20
pF
Note 5: CPO determines the no load dynamic power consumption. Po= Cpo va:;2 f+ Icc Vee. and the no load dynamic current consumption,
(
Is =Cro Vcc f+ Icc·
eo
.
. ,
,
3-328
.----------------------------------------------------------------.~
~
Functional Block Diagram (Positive Logic)
en
~
::J:
o
m
....
....
~
....~
~
::J:
o
en
---,
....
CCI
I
I
I
I
I
1
I
---..J
STAGE B
I
1
B .:.,1_ _ _ _-t-+-I
I
I
I
PARALLEL DATA
INPUTS
c ,:,2_ _ _ _--11
D3
- - -
1
I
- - - "'i
- - ;;G;;'
I------~G;;;;.-------,
E4
,------~G;;;-------_,
F5
,- -
0 6
I-------;;G~-------...,
-
---
-
-
-
~o;;;.
- - - - - --_,
--mGEH*
--
H7
---,
1
I
1
1
I
1
I
.
.
1
1
~---------------~
• NOTE: Stages C thru G (not shown In detail) are identical to stages A and B above.
3-329
TL/F/5343-3
r:
~ National
~ Semiconductor
~
\
~roc!.roS
MM54HC640/MM74HC640
Inverting Octal TRI-STATE® Transceiver
MM54HC643/MM74HC643
True-Inverting Octal TRI-STATE Transceiver
General Description
These TRI-STATE bi-directional buffers utilize microCMOS
Technology, 3.5 micron silicon gate P-well CMOS, and are
intended for two-way asynchronous communication between data buses. They have high drive current outputs
which enable high speed operation even when driving large
bus capacitances. These circuits possess the low power
consumption and high noise immunity usually associated
with CMOS circuitry, yet have speeds comparable to low
power Schottky TTL circuits.
Each device has an active enable G and a direction control
input, DIR. When DIR is high, data flows from the A inputs to
the B outputs. When DIR is low, data flows from the B inputs
to the A outputs. The MM54HC640/MM74HC640 transfers
inverted data from one bus to other and the MM54HC6431
MM74HC643 transfers inverted data from the A bus to the B
bus and true data from the B bus to the A bus .
These devices can drive up to 15 LS-TTL Loads, and all
inputs are protected from damage due to static discharge by
diodes to Vee and ground.
Features
•
•
•
•
Typical propagation delay: 13 ns
Wide power supply range: 2-6V
Low quiescent current 80 p.A maximum (74 HC)
TRI-STATE outputs for conneciion to bus oriented
systems
• High output drive: 6 mA (min)
. Connection Diagrams
Dual-In-~Ine
Dual-In-Llne Package
Package
ENABLE
Yee
G
DlR
'1
ENABLE
81
A2
B2
A3
83
So,
85
86
A4
A5
A6
A7
87
A8
88
Vee
G
GND
CIR
A1
81
A2
82
83
A3
A4
84
A5
TLlFI5344-1
85
B6
A6
A7
87
A8
BB
GND
TLlFI5344-2
Top View
Top View
Order Number MM54HC64OJ or MM74HC640J,N
See NS Package J20A or N20A
Order Number MM54HC643J or MM74HC643J,N
See NS Package J20A or N20A
Truth Table
Control
Inputs
H
Operation
G
DIR
640
643
L
L
B data to A bus
B data to A bus
L
H
. A data to B bus
A data to B bus
H
X
Isolation
= high level. L = low level, X = Irrelevant
3-330
Isolation
Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage (Vee>
DC Input Voltage DIR and G pins (VIN)
DC Output Voltage (VIN' VOUT)
Clamp Diode Current (leD)
DC Output Current, per pin (lOUT)
DC Vee or GND Current, per pin'(lce)
Storage Temperature Range (TSTG)
Power Dissipation (PD) (Note 3)
Lead Temperature (TLl
(Soldering 10 seconds)
Operating Conditions
-0.5 to + 7.0V
-1.5 to Vee+ 1.5V
-0.5 to Vce+0.5V
±20mA
±35mA
±70mA
-65'C to + 150'C
500mW
Supply Voltage (Vee>
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TpJ
MM74HC
MM54HC
Input Rise/Fall Times
Vee=2.0V
(lr, til
Vee=4.5V
Vee=6.0V
260'C
Min
2
Max
6
Units
V
0
Vee
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25'C
Typ
74HC
54HC
TA= -40to 85'-C TA= -55to 125'C, Units
Guaranteed Limits
VIH
Minimum High Level Input
Voltage
2.0V
4.5V
6.0V
'1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level Input
Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level Output
Voltage
VIN = VIH or VIL
IIOUTI ~20 p.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
,0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
IIOUTI ~ 6.0 mA
IIOUTI Q.8 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VeeorGND
p.A
VIN = VIH or VIL
IIOUTI ~ 6.0 mA
IIOUTI Q.8 mA
VOL
Maximum Low Level Output
, Voltage
VIN = VIH or VIL
IIOUTI ~20 p.A
liN
Input Leakage
Current (G and DIR)
6.0V
±0.1
±1.0
±1.0
IOZ
Maximum TRI-STATE Output VOUT=Vce or GND 6.0V
Leakage Current
Enable G= VIH
±0.5
±5.0
±10
,
p.A
Maximum Quiescent-Supply VIN = Vee or GND
8.0
80
160
p.A
6.0V
Current
IOUT=Op.A
Note 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - ptastic UN" package: -12 mW/'C from 65'e to 85'C; ceramic "J" package: -12 mW/'C from 100'C to 125'C,
Note 4: For a power supply of 5V ±10% the worst case outputvottages (VOH. and Vou occur forJHC at4.5V, Thus the 4.5Vvalues should be used when designing
wHh this supply. Worst case VIH and VIL occur at Vcc= 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3,85V.) The worst case leakage current (liN. Icc. and
lozl occur for CMOS at the higher voHage and so the 6.0V values should be used.
IcC
3-331
I
AC Electrical Characteristics Vcc=5V, TA=25°C, t r =tf=6 ns
Symbol
Conditions
Parameter
I
Typ
Guaranteed
LImit
Units
tpHL, tpLH
Maximum Propagation Delay
CL =45 pF
13
17
ns
tpZH, tPZL
Maximum Output Enable Time
Rl =1 kO
CL =45 pF
33
42
ns
tpHZ, tpLZ
!"Iaximum Output Disable Time
Rl=1 kO
Cl =5 pF
32
42
ns
AC Electrical Characteristics Vee = 2.0V to 6.0V, CL = 50 pF, tr= tf= 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=25°C
Typ
tpHL,
tpLH
tpzH,
Maximum Propagation Delay
Maximum Output Enable
tPZL
tpHZ,
tpLZ
Maximum Output Disable
Time
74HC
TA= -40 to 85°C
54HC
TA= -55to 125"C
Units
Guaranteed LImits
Cl =50pF
CL=150pF
2.0V
2.0V
29
36
72
96
66
116
96
126
ns
ns
CL =50pF
CL =150 pF
4.5V
4.5V
14
16
16
24
22
29
24
32
ns
ns
CL =50pF
Cl =150 pF
6.0V
6.0V
14
16
16
24
22
29
24
32
ns
ns
CL =50 pF
CL =150pF
2.0V
2.0V
70
80
164 .
216
224
260
240
284
ns
ns
,CL =50 pF
CL =150 pF
4.5V
4.5V
35
41
46
54
56
65
60
71
ns
ns
CL =50 pF
CL =150pF
6.0V
6.0V
31
36
41
47
50
57
54
62
ns
ns
RL =1 kO
CL =50 pF
2.0V
4.5V
6.0V
47
33
31
172
43
41
206
52
50
224
56
54
ns
ns
ns
2.0V
4.5V
6.0V
20
6
5
60
12
10
75
15
13
90
18
15
ns
ns
ns
RL =1 kO
trHL, trLH
Output Rise and Fall Time
CL =50pF
CPO
Power Dissipation
Capacitance (Note 5)
G';"VIL
G=VIH
CIN
Maximum Input Capacitance
5
10
10
10
pF
CIN/OUT
Maximum Input/Output
Capacitance, A or 8
15
20
20
20
pF
"
120
12
pF
pF
Nata 5: CpO determines the no load dynamic power consumption, Po= CpO Vr:;c2 1+ ICC Vee. and the no load dynamic current consumption, Is= CPO Vcc 1+ Icc.
0
I
3-332
!i!:
!i!:
en
Logic Diagrams
'HC640
"..
::r:
'HC643
A8
B8
A8
B8
A7
B7
A7
B7
0Q)
"..
CI
......
A6
B6
A6
86
A5
B5
A5
B5
A4
B4
A4
B4
A3
B3
A3
B3
!i!:
!i!:
.....
"..
::r:
0Q)
"..
CI
......
!i!:
!i!:
en
"..
::r:
0Q)
A2
B2
B2
A2
"..
Co)
......
!i!:
!i!:
.....
"..
::r:
0Q)
Vee
Vee
"..
Co)
AI
Bl
Vee
AI
Bl
":"
ENABLE
ENABLE
aO-------4H--.......
L.o<:I...-----~DIR
TUF/5344-5
3-333
a~--------~~--~
LoO....- - - - - - o D I . R
TUF/5344-6
\"--__
----,../J
MM54HC646/MM74HC646 Non-Inverting
Octal Bus Transceiver/Registers
MM54HC648/MM74HC648
Inverting Octal Bus Transceiver/Registers
microCMOS
General Description
These transceivers utilize microCMOS Technology, 3.5 micron silicon gate P-well CMOS, and contain two sets of TAISTATE~ outputs, two sets of D-type flip-flops, and control
circuitry designed for high speed multiplexed transmission
of data.
Six control inputs enable this device to be used as a latched
transceiver, unlatched transceiver, or a combination of both.
As a latched transceiver, data from one bus is stored for
later retrieval by the other bus. Alternately real time bus
data (unlatched) may be directly transferred from one bus to
another.
Circuit operation is determined by the G, DIA, CAB, CBA,
SAB, SBA control inputs. The enable input, G, controls
whether any bus outputs are enabled. The direction control,
DIA, determines which bus is enabled, and hence the direction data flows: The SAB, SBA inputs control whether the
latched data (stored in 0 type flip flops), or the bus data
(from other bus input pins) is transferred. Each set of flip-
flops has its own clock CAB, and CBA, for storing data. Data
is latched on the rising edge of the clock.
Each output can drive up·to 15 low power Schottky TTL
loads. These devices are functionally and pin compatible to
their LS-TTL counterparts. All inputs are protected from
damage due to static discharge by diodes to Vee and
ground.
Features
•
•
•
•
•
Typical propagation'delay: 14 ns
,TAl-STATE outputs
Bidirectional communication
Wide power supply range: 2-6V
Low quiescent supply current: 160 p.A
maximum (74HC)
• High output current: 6 mA (74HC) .
Connection Diagram
Dual·ln·Une Package
CLOCK
~
SELECT
BA ENABLE
~
U
~
H
H
~
M
~
~
n
Order Number MM54HC646J,
MM54HC648J, MM74HC646J, N or
MM74HC648J, N
.
See NS Package J24F or N24C
13
1.
CLOCK
DIR
AS
SELECT
AB
A1
A2
A3
At
A5
AI
A7
AS
GND
TLIFI5345-2
1
-
I
I
I
I
I
I
i
i ,-,
I II i
- I L
L_-'j
IS)
DIll
L
IHI 111 1131
I 'W CIA
L
X
X
121
IAlI
X
(2tJ
llA
L
:1~1~=m:l
H
I.
X
II
L
I
I
I
X
•
xt
til 121, til
Dill I
CAl
X
x
x
Real-Time Transfer
Bus Bto Bus A
I
I
I
I II
I I I
II
I
x
""1
I
(231
f
I
III
r:u SAIl
xx
x
I
(J2)
lilA
xx
x
Storage from
A,B,orAandB
Real·Time Transfer
BusAtoBusB
3-334
11112111'1
IIIR
L
11'
N
L
L
CAl
X
It
121)
CIA
X
x
12)
W
X
H
Pit
IIA
H
X-
TLIFI5345~;
Transfer Stored Data
toAorB
Absolut~ Maximum Ratings (Notes 1 & 2)
-0.5 to + 7.0V
Supply Voltage {Veel
DC Input Voltage (VIN)
-1.5toVee+ 1.5V .
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
±20mA
Clamp Diode Current (11K, 10Kl
±35mA
DC Output Current, per pin (lOUT)
±70mA
DC Vee or GND Current, per pin (Ieel
-65·C to + 150·C
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
500mW
260·C
Lead Temp. (TL.l (Soldering 10 seconds)
Parameter
Conditions
Supply Voltage {Veel
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TtV
MM74HC
MM54HC
Input Rise or Fall TImes
(tr, ttl
Vee=2.0V
Vee=4.5V
Vee=6.0V
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+B5
+125
·C
·C
1000
500
400
ns
ns
ns
,
DC Electrical Characteristics (Note 4)
Symbol
Operating Conditions
74HC
TA= -40 to 8S·C
TA=2S·C
Vee
Typ
S4HC
TA= -SSt012S·C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
IIOUTI:S;20 p.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.96
5.46
3.84
5.34
3.7
5.2
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIH orVIL
jIOUTj:S;6.0 mA
lOUT :S;7.8mA
4.5V
6.0V
0.2
0.2
0.26.
0.26
0.33
0.33
0.4
0.4
V
V
6.0V
±0.1
±1.0
±1.0
p.A
6.0V
±0.5
±5.0
±10
p.A .
VIN = VIH or VIL
jIOUTj:S;6.0 mA
lOUT :S;7.BmA
Maximum Low Level
Output Voltage
VOL
VIN = VIH or VIL
IIOUTI:S;20 p.A .
liN
Maximum Input Current
VIN=VeeorGND
loz
Maximum TRI-STATE
Output Leakage
~OUT=VecorGND
G=VIH
V
Maximum Quiescent
6.0V
B.O
BO
160
p.A
VIN = Vee or GND
Supply Current
IOUT=O p.A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specHled all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mW'·C from 65'C to 85'C; ceramic "J" package: -12 mW'·C from 100'C to 125'C.
Note 4: For a power supply of 5V ± 10% the worst case output voltages (VOH. and VoLl occur for HC at4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at Vee = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.l The worst case leakage current (liN. lee. and
lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
Icc
Truth Table
Inputs
G DIR
'X
X
H
H
L
L
L
L
X
X
X
CAB
t
X
t
X, HorL
L
X
L
X
X
X
Data 1/0
Operation or Function
CBA
SAB
SBA
A1 ThruA8
B1 Thru B8
'ALS646, 'ALS647
'AS646
'ALS648, 'ALS649
'AS648
X
X
X
X
X
X
X
X
Input
Not Specified
Not Specified
Input
Store A, B Unspecified
Store B, A Unspecified
Store A, B Unspecified
Store B, A Unspecified
Input
Input
Store A and B Data
Isolation, hold storage
Store A and B Data
Isolation, hold storage
Output
Input
Real-Time B Data to A Bus
Stored B Data to A Bus
Real-Time B Data to A Bus
Stored B Data to A Bus
t
t
HorL
X
X
X
X
X
L
H
H
X
L
X
Real-TIme A Data to B Bus Real-TIme A Data to B Bus
Input
Output
H
X
H
X
Stored A Data to B Bus
Stored A Data to B Bus
H = High Level L = Low Level X = Irrelevant t = low-Io-hlgh level transition
The data output functions I.e.. data at the bus pins may be enabled or disabled by various signals at the G and DIR Inputs. Data input functions Bre always enabled.
The data output functions i.e., data at the bus pins will be stored on every low-ta-high transition on the clock Inputs.
3-335
•
AC Electrical Characteristics MM54HC646/MM74HC646
Vcc=5V, TA=25°C, tr =tf=6 ns
Symbol
Parameter
Conditions
,
TyP
Guaranteed
Limit
Units
45
30
MHz
fMAX
Maximum Operating
Frequency
tpHL. tpLH
Maximum Propagation
Delay. A or B Input
to B or A Output
CL =45 pF
14
25
ns
tpHL, tpLH
Maximum Propagation
Delay. CBA or CAB
Input to A or B Output
CL =45pF
31
40
ns
tpHL, tpLH
Maximum Propagation
Delay. SBA or SAB Input to A
or B Output. with A or B high
CL =45pF
35
50
ns
tpHL. tpLH
Maximum Propagation
Delay. SBA or SAB Input to A
or B Output: with A or Blow
CL =45pF '
35
50
- ns
tpZH. tPZL
Maximum Enable
Time G or DIR Input to
AorBOutput
RL =1 kO
CL =45pF
18
33
ns
tpHZ. tpLZ
Maximum Disable
Time. G or DIR Input to
AorBOutput
RL =1 kO
CL =5pF
17
30
ns
I
AC Electrical Characteristics MM54HC646/MM74HC646
Vcc=2.0-6.0V. CL =50 pF, t r =tf=6 ns(unless otherwise specified)
.'
Symbol
Parameter
Conditions
TA=25"C
Vee
Typ
fMAX
, tpHL. tpLH
Maximum Operating
Frequency
CL =50 pF
2.0V
4.5V
6.0V
Maximum Propagation
Delay, A or B Input
to B or A Output
CL =50pF
CL =150pF
2.0V
2.0V
CL =50pF
CL =150pF
"
tpHL. tpLH
tpHL. tpLH
Maximum Propagation
Delay, CBA or CAB
Input to A or B Output
Maximum Propagation
Delay. SBA or SAB
Input to A or B Output.
with A or B high
74HC
TA= -40 to 85"C
54HC
TA= -55 to 125°C
Units
Guaranteed Limits
5
27
31
4
21
24
3
18
20
MHz
MHz
MHz
60
80
180
200
189
250
225
300
ns
ns
4.5V
4.5V
21
30
30
40
37
50
45
60
ns
ns
CL=50pF
CL =150pF
6.0V
6.0V
18
22
26
35
31
44
39
53
CL =50pF
CL =150pF
2.0V
2.0V
110
150
220
270
275
338
330
405
ns
ns
CL =50 pF
CL =150pF
4.5V
4.5V
31
40
44
55
54
68
66
81
ns
ns,
Cl =50pF
CL =150pF
6.0V
6.0V
28
34
38
47
47
59
57
71
ns
CL =50pF
CL =150pF
2.0V
2.0V
180
210
290
340
363
425
435
510
ns
ns
CL =50pF
CL =150pF
4.5V
4.5V
39
47
58
68
72,
85
87
102
ns
ns
CL;=50 pF
CL =150pF
6.0V
6.0V
34
39
50
58
63
72
75
87
ns
ns
\
~
3-336
,
ns
ns
ns
AC Electrical Characteristics
(Continued) MM54HC646/MM74HC646
Vcc=2.0-6.0V, CL =50 pF, t r =tf=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25'C
Vee
Typ
tPHL, tpLH
tpZH, tPZH
Maximum Propagation
Delay, SBA or SAB
Input to A or B Output,
with A or BLow
Maximum Output Enable
Time, G Input or DiR to A or B
Output
74HC
TA= -40 to 85'C
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
CL =50pF
CL =150 pF
2.0V
2.0V
180
210
290
340
363
425
435
510
ns
ns
CL =50pF
CL =150 pF
4.5V
4.5V
39
47
58
68
72
85
87
102
ns
ns
CL =50 pF
CL=150pF
6.0V
6.0V
34
39
50
58
63.
72
75
87
ns
ns
CL =50pF
CL=150pF
2.0V
2.0V
80
120
175
225
21'9
281
263
338
ns
ns
CL =50pF
CL=150pF
4.5V
4.5V
23
31
35
45
44
56
53
68
ns
ns
CL =50pF
CL=150pF
6.0V
6.0V
21
27
30
38
37
48
45
57
ns
ns
85
23
21
175
35
30
219
44
37
263
53
45
ns
ns
ns
RL =1 kG
tpHZ, tpLZ
Maximum Output Disable
TIme, G Input to A or B
Output
RL =1 kG
CL =50pF
2.0V
4.5V
6.0V
irHL, tTLH
Maximum Output Rise
and Fall Time
CL =50pF
2.0V
4.5V
6.0V
SO
12
10
75
15
13
90
18
15
ns
ns
ns
Is
Minimum Setup Time
2.0V
4.5V
S.OV
100
20
17
125
25
21
150
30
25
ns
ns
ns
tH
Minimum Hold Time
2.0V
4.5V
6.0V
0
0
0
0
0
0
0
0
0
ns
ns
ns
tw
Minimum Pulse Width
of Clock
,
2.0V
4.5V
6.0V
80
16
14
100
20
18
120
24
21
ns
ns
ns
tr, tf
Maximum Input Rise and
Fall Time
2.0V
4.5
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
CPO
Power Dissipation
Capacitai'l<;e (Note 5)
CIN
Maximum Input
Capacitance
5
10
10
10
pF
COUT
Maximum Input
Capacitance
15
20
20
20
pF
pF
3-337
AC Electrical Characteristics
MM54HC648/MM74HC648
Vcc=5V, TA=25°C, t r =t,=6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
44
30
MHz
fMAX
Maximum Operating
Frequency
tpHL, tpLH
Maximum Propagation
Delay, A or B Input
to B or A Output
CL =50 pF
14
25
ns
tpHL, tpLH
Maximum Propagation
Delay, CBA or CAB
Input to A or B Output
CL =50pF
31
40
ns
tpHL, tpLH
Maximum Propagation
Delay, SBA or SAB Input to A
or B Output, with A or B high
CL =50pF
35
50
ns
tpHL, tpLH
Maximum Propagation
Delay, SBA or SAB Input to A
or B Output, with A or Blow
CL =50pF
35
50
ns
tpzH, tPZL
Maximum Enable
Time G Input to
Aor BOutput
RL =1 kO
CL =45pF
18
33
ns
tpHZ, tpLZ
Maximum Disable
Time, G Input to
AorB Output
RL =1 kO
CL =5pF
17
30
ns
,'I
AC Electrical Characteristics
MM54HC648/MM74HC648
Vcc=2.0-6.0V, CL =50 pF, 1,-=t,=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=25°C
Typ
fMAX
Maximum Operating
Frequency
CL =50pF
2.0V
4.5V
6.0V
tpHL, tpLH
Maximum Propagation
Delay, A or B Input
to S or A Output
CL =50pF
CL =150pF
2.0V
2.0V
CL =50pF
CL =150pF
tpHL, tpLH
tpliL, tpLH
Maximum Propagation
Delay, CBA or CAB
Input to A or B Output
Maximum Propagation
Delay, SSA or SAB
Input to A or B Output,
with A or B high
74HC
TA= -40 to 85°C
54HC
TA=-55to125°C
Units
Guaranteed Limits
5
27
31
4
21
24
3
18
20
MHz
MHz
MHz
60
80
180
200
189
250
225
300
ns
ns
4.5V
4.5V
21
30
30
40
37
50
45
60
ns
ns
CL =50pF
CL =150pF
6.0V
6.0V
18
22
26
35
31
44
39
53
ns
ns
CL =50pF
CL =150pF
2.0V
2.0V
110
150
220
270
275
338
330
405
ns
ns
CL =50pF
CL=150pF
4.5V
4.5V
31
40
44
54
55
68
66
81
ns
ns
CL =50 pF
CL =150pF
6.0VI
6.0V
28
34
38
47
47
59
57
71
ns
ns
CL =50pF
CL =150pF
2.0V
2.0V
180
210
290
340
363
425
435
510
ns
ns
CL =50pF
CL =150pF
4.5V
4.5V
39
47
58
68
72
85
87
102
ns
ns
CL =50pF
CL =150pF
6.0V
6.0V
34
39
50
58
63
72
75
87
ns
ns
AC Electrical Characteristics MM54HC648/MM74HC648 (Continued)
VCC~2.0-6.0V, CL =50 pF, t r =tf=6 ns (unless otherwise specified)
TA=25'C
Symbol
Parameter
Conditions
Vee
74HC
TA= -40 to 85'C
Typ
tpHL, tpLH
tpZL, tPZL
Maximum Propagation
Delay, SBA or SAB
Input to A or B Output,
with A or Blow
Maximum Output Enable
Time, G Input or DIR to A or B
Output
tpHZ, tpLZ
Maximum Output Disable
Time, G Input to A or B
Output
tTHL, tTLH
Maximum Output Rise
and Fall TIme
54HC
TA = -55 to 125'C
Units
Guaranteed Limits
CL =50 pF
CL=150pF
2.0V
2.0V
180
210
290
340
363
425
435
510
ns
ns
CL =50pF
CL=150pF
4.5V
4.5V
39
47
58
68
72
85
87
102
ns
ns
CL =50pF
CL =150 pF
6.0V
6.0V
34
39
50
58
63
72
75
87
ns
ns
CL =50pF
CL=150pF
2.0V
2.0V
80
120
175
225
219
281
263
338
ns
ns
CL =50pF
CL=150pF
4.5V
4.5V
23
31
35
45
44
56
53
68
ns
ns
CL =50pF
CL =150 pF
6.0V
6.0V
21
27
30
38
37
48
45
57
ns
ns
RL =1 k!l
CL =50pF
2.0V
4.5V
6.0V
85
23
21
175
35
30
219
44
37
263
53
45
ns
ns,
ns
2.0V
4.5V
6.0V
60
12
10
75
15
13
90
18
15
ns
ns
ns
RL =1 k!l
CL =50pF
ts
Minimum Set Up Time
2.0V
4.5V
6.0V
100
20
17
125
25
21
150
30
25
ns
ns
ns
tH
Minimum Hold Time '
2.0V
4.5V
6.0V
0
0
0
0
0
0
0
0
0
ns
ns
ns
tw
Minimum Pulse Width
of Clock
2.0V
4.5V
6.0V
80
16
14
100
20
18
120
24
21
ns
ns
ns
t,., tf
Maximum Input Rise and
Fall TIme
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
ns
ns
ns
,
500
400
CPO
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input capacitance
5
10
10
10
pF
GoUT
Maximum Output
Capacitance
15
20
20
20
pF
pF
Note 5: CPO determines the no load dynamic p0w.er consumption. Po=Cpo. Vcrf!-l+lcc. and the no load dynamic current consumption. IS=CPD Vee 1+ lee.
Note 6.: Refer to back of this section for Typical MM54/74HC AC Switching Waveforms and Test Circuits.
3-339
MM54HC646/MM74HC646/MM54HC648/MM74HC648
-d
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~~---~------------------------------~~
7-------____________________
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AA9 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
______
______________ ______________
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OIR 3 ,
G" 2 1 - - -....' .....
TB.
T'B=DE
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r~
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c~
---<><:}---,
CB.
~ CLOCKAB
C'B~
Ca.
~
CLOCKBA
TUF/5345-3
~National
~ Semiconductor
microCMOS
MM54HC688/MM74HC688
I
8-Bit Magnitude Comparator (Equality Detector)
General Description
This equality detector utilizes microCMOS Technology, 3.5
micron silicon gate P-well CMOS, to compare bit for bit two
8-bit words and indicates whether or not they are equal. The
P = Q output indicates equality when it is low. A single active
low enable is provided to facilitate cascading of several
packages and enable comparison of words greater than 8
bits.
This device is useful in memory block decoding applications, where memory block enable Signals must be generated from computer address information.
The comparator's output can drive 10 low power Schottky
equivalent loads. This comparator is functionally and pin
compatible to the 54LS688/74LS688. All inputs are protected from damage due to static discharge by diodes to Vee
and ground.
Features
•
•
•
•
•
Typical propagation delay: 20 ns
Wide power supply range: 2-6V
Low quiescent current: 80 ",A (74 Series)
Large output current: 4 mA (74 Series)
Same as 'HC521
Connection and Logic Diagrams
Dual-In-Llne Package
Vcc P
=
0
07
P7
06
P6
05
Q7
PS
04
P4
Q6
p..(')o--ooo-:-;;(19;:.) -P=-0
10
G
PO
00
P1
01
P2
02
P3
03
GND
TL/F/S018-1
Top View
Order Number MM54HC688J or MM74HC688J, N
See NS Package J20A or N20A
Truth Table
Inputs
Data
G 11)
Enable
TL/F/S018-2
P,Q
G
P=Q
P=Q
P> Q
P
±25mA
DC 0\J1put Current. per pin (lOUT)
±50mA
DC Vee or GND Current. per pin (lee)
-65·C to + 1500e
Storage Temperature Range (TSTG)
500mW
Power Dissipation (Po) (Note 3)
260·C
Lead Temp. (T (Soldering 10 seconds)
Operating Conditions
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
(tr. tf)
Vee=2.0V
Vee=4.5V
Vee=6.0V
u
,
Min
2
0
Max
6
Vee
Units
V
V
·-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
"
'DC Electrical Characteristics
(Note 4)
Symbol
Parameter
Conditions
Vee
TA=25·C
Typ
74HC
TA= -40 to 85·C
54HC
TA= -55to 12SOC
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V.
V
V
VOH
Minimum High Level
Output Voltage
V
V
V
VIN = VIH or VIL
IIOUTI";20 p.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
VIN=VIH orVIL
!louTI";4.0 rnA
IIOUTI ,,; 5.2 rnA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = Vee or GND
6.0V
±0.1
±1.0
±1.0
/LA
VIN=VIH orVIL
IIOUTI";4.0 rnA
!louTI ,,; 5.2 rnA
VOL·
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
VIN = VIH or VIL
!louTI";20 /LA
~
V
V
V
V
V
Maximum Quiescent VIN=VeeorGND 6.0V
8.0
80
160
/LA
Supply Current
10UT=0/LA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power DissipallOn temperature derating - plastic "N'.' package: -12 mW/'C from 6S'C to 8S'C; ceramic "J" package: .-12 mW/'C from 1OO'C to 125'C.
Note 4: For a power supply of SV ± 10,," the worst esse output voltages (VOH, and Vou ooeur for HC at4.SV. Thus the 4.SV values should be used when designing
with this supply. Worst esse VIH and VIL occur at Vcc=S.SV and 4.SV respectively. (The VIH value atS.SV Is 3.8SV.) The worst case leakage current (liN, ICC, and
loz) occur for CMOS at the higher vollage and so the 6.0V values should be used.
IcC
3-342
AC Electrical Characteristics
Vcc=5V. TA=25·C. CL =15 pF. t r =t,=6 ns
Typ
Guaranteed
Limit
Units
Maximum Propagation
Delay. any P or Q to Output
21
30
ns
Maximum Propagation
Delay. Enable to any Output
14
20
ns
Symbol
Parameter
tpHL. tpLH
tpLH. tpHL
Conditions
AC Electrical Characteristics
Vcc=2.0V to 6.0V. CL=50 pF. t r =t,=6 ns (unless otherwise specified)
I
Symbol
Parameter
Conditions
Vee
TA=2S·C
74HC
TA= -40t08S·C
Typ
S4HC
TA= -55 to 125·C
Units
Guaranteed Limits
tpHL. tpLH
Maximum Propagation
Delay
2.0V
4.5V
6.0V
SO
22
19
175
35
30
220
44
38
263
53
4S
ns
ns
ns
tpHL. tpLH
Maximum Propagation
Delay
2.0V
4.5V
S.OV
45
15
13
120
24
20
150
30 .
25
180
36
30
ns
ns
ns
tTHL. tTLH
Maximum Output Rise
and FaUTIme
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
CPO
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input
Capacitance
45
5
pF
10
10
10
pF
Nota 5: CPO determines the no load dynamic power consumption, Po = Cpo Vcr:! f+ lee Vee, and the no load dynamic current consumption, Is =CPO Vee f+ lee.
\
,
,
3-343
•
t: ":::1
~ r-------~------------------------------------------------------~----------__,
....
~ ~National
PRELIMINARY
~ ~ Semiconductor
:::&
microCMOS
:::&
·MM74HC942 300 Baud Modem
General Description
Features
The MM74HC942 is a full duplex low speed modem. It provides a 300 baud bidirectional serial interface for data communication over telephone lines and other' narrow bandwidth channels. It is Bell 103' compatible;
The MM74HC942 utilizes microCMOS Technology, 2 layers
of polysilicon and 1 layer of metal P-well CMOS. Switched
capacitor techniques are used to perform analog signal
processing.
• Drives 600.0. at 0 dBm
• All filters on chip
• Transmit level adjustment comp~tible with universal
service order code
• TIL and CMOS compatible logic
• All inputs protected against static damage'
• ± 5V supplies
• Low power consumption
• Full duplex answer or Originate operation
• Analog loopback for self test
• Power down mode
MODULATOR SECTION
The modulator contains a frequency synthesizer and a sine
wave synthesizer. It produces a phase coherent frequency
.
shift keyed (FSK) output
LINE DRIVER AND HYBRID SECTION
The line driver and hybrid are designed to facilitate connection to a 600.0. phone line. They can perform two-to-fourwire conversion and drive the line at a maximum of 0 dBm.
DEMODULATOR SECTION
The demodulator incorporates anti-all~sing filters, a receive
filter, limiter, discriminator, and carrier detect circuit. The
nine pole receive filter provides 60 dB of transmitted tone
rejection. The discriminator is fully balanced for stable
operation.
.
Applications
•
•
•
•
•
•
•
•
Built-in low speed modems
Remote data collection
Radio telemetry
Credit verification
Stand-alone modems
Point-of-sale terminals
Tone signalling systems
Remote process control
Connection and Block Diagrams
GND
Vaa
XTALD
ITALS
Dual·ln·Une Package
DSI
!LA
ALB
lIND
CD
EXI
CDT
TXA
-
RlCD
TIA-f.---1
RKAI
Vee
-CDA
081-t--....- ....- - - - ,
&QT.
XTALD
8
18
ofJ.
XTALB
•
12
vas
me
10
TID
"TLlF/5348-1
TXA-t--...........(
01-+-===:....----
Top View
Order Number MM74HC942J, N
See NS Package J20A or N20A
IlXAI-t----I
CDA
eDT
Fnc
Tl/F/534B-2
3-344
Absolute Maximum Ratings (Notes 1 & 2)
-0.5 to +7.0V
Supply Voltage (VeC>
+0.5 to -7.0V
Supply Voltage (Vss)
DC Input Voltage (VIN)
Vss-1.5 to Vee + 1.5V
DC Output Voltage (VOUT)
Vss-0.5 to Vee+0.5V
±20mA
Clamp Diode Current (11K. 10K)
±25mA
DC Output Current. per pin (lOUT)
±50mA
DC Vee or GND Current. per pin (IcC>
Storage Temperature Range (TSTG)
-65'Cto +150'C
500mW
Power Dissipation (PD) (Note 3)
Lead Temp. (TO
(Soldering 10 seconds)
Operating Conditions
Supply Voltage (VeC>
Supply Voltage (Vss)
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HC
Input Rise or Fall Times
(tr• tf)
Crystal frequency
Min
4.5
-4.5
Max
5.5
-5.5
0
Vee
Units
V
V
V
-40
+85
'C
500
3.579
ns
MHz
260'C
DC Electrical Characteristics
Symbol
74HC
T= -40 to 85'C
T=25'C
Conditions
Parameter
Typ
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
3.15
3.15
V
VIL
Maximum Low Level
Input Voltage
1.1
1.1
V
VOH
Minimum High Level
Output Voltage
VIN=VIHorVIL
IIOUTI = 20 /-LA
IIOUTI=4.0 mAo Vee=4.5V
Vee- 0.1
3.98
Vee- 0.1
3.7
V
V
Maximum Low Level
Voltage
VIN=VIHorVIL
IIOUTI=20 /LA
IIOUTI =4.0 mAo Vee=4.5V
0.1
0.26
0.1
0.4
V
V
liN
Maximum Input
Current
VIN=VeeorGND
±0.1
±1.0
/-LA
loz
OutputTRI-STATEI!>
Leakage Current
RXD and CD Outputs
ALB=SQT=Vee
±5
/LA
ICC. Iss
Maximum Quiescent
Supply Current
VIN=VCC. VIL =GND
ALB or SQT=GND
Transmit Level = -9 dBm
12.0
mA
300
/-LA
VOL
Power Down Supply Current
Vee
8.0
ALB = SQT = Vee
VIH = Vee. VIL =GND
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
ICC. Iss
Note 2: Unless otherwise specified all voltages
afB
12.0
referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mWI'C from 6S'C to 8S'C; ceramic "J'. package: -12 mW I'C from 1OO'C to 12S'C.
'The demodulator specifications apply to the MM74HC942 operating with a modulator having frequency accuracy. phase iiller and harmonic content equal to or
beller than the MM74HC942 modulator.
,
3-345
•
AC Electrical Characteristics
Unless otherwise specified, all specifications apply to the MM74HC942 over the range -40·C to +8S·C using a Vee = +SV
±10%, a Vee = -SV ±10% and a 3.S79MHz ±0.1% crystal."
Symbol ·1
Parameter
Conditions
1
Min
1
Typ
1
1 Max
1 Units
TRANSMITTER
FCE
Carrier Frequency Error
Power Output
I
Vee=5.0V
I
RL =1.2kG
4
Hz
-1.S.
0
dBm
':"10.5
-9
dBm
-S6
dBm
RTLA = 0
-3
RTLA = 5.49 kG
-12
-S2
2nd Harmonic Energy
RECEIVE FILTER AND HYBRID
I
SO
Hybrid Input h'l'Ipedance
(Pins 15 and 1S)
FTLC Output impedance
5
Adjacent Channel Rejection
RXA2=GND TXA=GNDorVcc
Input to RXA 1
10
SO
SO
kG
kG
dB
DEMOi:)uLATOR (INCORPORATING HYBRID, RECEIVE .FILTER AND DISCRIMINATOR)
-;-48
Carrier Amplitude
}
SNR = 30 dB
Input = -38 dBm
Baud Rate = 300 Baud
Bit Jitter
Bit Bias
Alternating 1-0 Pattern
Carrier Detect Trip Points
CDA=1.2V
I
I
VCC=5.0V
Carrier Detect Hysteresis
100
dBm'
/JoS
S
10
%
Off to On
-45
-42
-40
dBm
On to Off
-47
-45
-42
dBm
2
3
4
dB
Vee=5V
AC Specification Circuit
..
-9
200
3.5795 MHz ± 0.1%
SUPPLIES Vee= +5V
Vaa= -5V
rD~
,
RTLA
Vee
-
~
TLA
TXA
RXA2
600
TXO ~DATAINPUT
MM74HC942
TEST
OUTPUT
=p
INPUT
RXD
--+ DATA· OUTPUT
6DO
RXAl
COT
CDA
.L,
10"I-'F
3-346
r·
.LOl F
~
FTLC
.-LO.l~F
ltlO'll
TL/F/S348-3
3:
Description of Pin Functions
3:.
......
Pin
No.
0
2
.a:o.
:::t:
Name
Function
DSI
Driver Summing Input: Thill may be used to
transmit externally generated tones such as
dual tone multifrequency (DTMF) dialing sig·
nals.
Analog Loop Back: A logic high on this pin
causes the modulator output to be connect·
ed to the demodulator input so that d~ta is
looped back through the entire chip. This is
used as a chip self test. If ALB and SaT are
simultaneously held high the chip powers
down.
Carrier Detect: This pin goes to a logic low
when carrier is sensed by the carrier detect
circuit.
CD
ALB
3
CD
4
COT
Carrier Detect Timing: A capaCitor on this
pin sets the time interval that the carrier
must be present before the CD goel? low.
5
RXD
6
Vee
7
bOA
Received Data: This is the data output pin.
Positive Supply Pin: A + 5V supply is recom·
mended.
Carrier Detect Adjust: This is used for adjustment of the carrier detect threshold. Carrier detect hysteresis is set at 3 dB.
8
XTALD
Crystal Drive: XTALD and XTALS connect
to a 3.5795 MHz crystal to generate a crystal locked clock for the chip. If an external
circuit requires this clock XTALD should be
sensed. If a suitable clock is already available in the system, XTALD can be driven.
9
XTALS
10
FTLC
Crystal Sense: Refer to Pin 8 for details.
Filter Test/Limiter Capacitor: This is connected· to a high impedance output of the
receive filter. It may th)Js be used to evalu-
ate filter performance. This pin may. also be
driven to evaluate the demodulator. RXA 1
and RXA2 must be grounded during this
test.
For normal modem operation FTLC is AC
grounded via a 0.1 JJ.F bypass capaCitor.
Transmitted Data: This is the data input. .
11
12
TXD
Vee
Negative Supply: The recommended supply
is -5V.
13
alA
Originatel Answer mode select: When logic
high this pin selects the originate mode of
operation.
14
SaT
Squelch Transmitter: This disables the modulator when held high. The EXI input remains active. If SaT and ALB are simultaneously held high the chip powers down.
15
RXA2
Receive Analog # 2: RXA2 and RXA 1 are
analog inputs. When connected as recommended they produce a 6000. hybrid.
16
RXA1
Receive Analog # 1: See RXA2 for details.
17
TXA
Transmit Analog: This' is the output of the
line drivei'.
18
EXI
19
20
GND
TLA
External Input: This is a high impedance input to the line driver. This input may be used
to transmit externally generated tones.
When not used for this purpose it should be
grounded.
Ground: This defines the chip OV.
Transmit Level Adjust: A resistor from this
pin to Vee sets the transmit level.
Functional Description
THE LINE INTERFACE
INTRODUCTION
A modem is a device for transmitting and receiving serial
data over a narrow bandwidth communication channel. The
MM74HC942 uses frequency shift keying (FSK) of an audio
frequency tone. The tone may be transmitted over the
switched telephone network and other voice grade channels. The MM74HC942 is also capable of demodulating
FSK signals. By suitable tone allocation and considerable
Signal processing the MM74HC942· is capable of transmitting and receiving data simultaneously.
The line interface section performs two to four wire conver·
sion and provides impedance matching between the mo.
dem and the phone line.
THE LINE DRIVER
The line driver is a power amplifier for driving the line. If the
modem is operating as an originate modem, the second harmonics of the transmitted tones fall close to the frequencies
of the received tones and degrade the received signal to
noise ratio (SNR). The line driver must thus produce low
second harmonic distortion.
The tone allocation by the MM74HC942 and other Bell 103
compatible modems is shown in Table I. The terms "originate" and "answer" which dllfine the frequency allocation
come from use with telephones. The modem on the end of
the line which initiates the call is called the originate modem. The other modem is the answer modem.
THE HYBRID
The voltage on the telephone line is the sum of the transmitted and received signals. The hybrid subtnicts the transmit·
ted voltage from the voltage on the telephone line. If the
telephone line was matched to the hybrid impedance, the
output of the hybrid would be only the received signal. This
rarely happens because telephone line characteristic impedances vary considerably. The hybrid output is thus a
mixture of transmitted and received signals.
TABLE I. BELL 103 Allocation
Data
Originate Modem
Answer Modem
Transmit
Receive
Transmit
Receive
Space
1070Hz
2025Hz
2025Hz
1070Hz
Mark
1270Hz
2225Hz
2225Hz
1270Hz
3-347
.a:o.
N
~
~
. (I)
r-----------.----------------------------------------------------------------------~
o
Functional Description
~
THE DEMODULATOR SECTION
::E
::E
The Receive Filter
::J:
.....
(Continued)
frorn TLA to VCC. With a 5.5k resistor the line driver trans·
mits a maximum of - 9 dBm. Since most lines from a phone
installation to the exchange provide 3 dB of attenuation the
maximum level reaching the exchange will be -12 dBm.
This is the maximum level permitted by most telephone
companies. Thus with this programming the MM74HC942
will interface to most telephones. This arrangement is called
the "permissive arrangement." The disadvantage with the
permissive arrangement is that when the loss from a phone
to the exchange exceeds 3 dB, no compensation is made
and SNR may be unnecessarily degraded.
The demodulator recovers the data from the received sig·
nals. The signal irom the hybrid is a mixture of transmitted
signal, received signals and noise. The first stage of the
receive filter is an anti·alias filter which attenuates high fre·
quency noise before sampling occurs. The signal then goes
to the second stage of the receive filter where the transmit·
ted tones and other noise are filtered from the received sig·
nal. This is a switched capacitor nine· pole filter providing at
least 60 dB of transmitted tone rejection. This also provides
high attenuation at 60 Hz, a common noise component.
SNR can be maximized by adjusting the transmit level until
the level at the exchange reaches -12 dBm. This must be
done with the cooperation of the telephone company. The
programming resistor used is specific for a given installation
and is often included in the telephone jack at the installa·
tion. The modem is thus programmable and can be used
with any jack correctly wired. This arrangement is called the
universal registered jack arrangement and is possible with
the MM74HC942. The values of resistors required to pro·
gram the MM74HC942 follow the most common code in
use; the universal service order code. The required resistors
are given in Table II.
The Discriminator
The first stage of the discriminator is a hard limiter. The hard
limiter removes from the received signal any amplitude
modulation which may bias the demodulator toward a mark
or a space. It compares the output of the receive filter to the
voltage on the 0.1 ",F capacitor on the FTLC pin.
The hard limiter output connects to two parallel bandpass
filters in the discriminator. One filter is tuned to the mark
frequency and the other to the space frequency. The out·
puts of these filters are rectified, filtered and compared. If
the output of the mark path exceeds the output of the space
path the RXD output goes high. The opposite case sends
RXD low.
TABLE II. Universal Service Order Code Resistor Values
Line
Loss
(dB)
,0
The demodulator is implemented using precision switched
capacitor technique~. The highly critical comparators in the
limiter and discriminator are cluto·zeroed for low offset.
Transmit
Level
(dBm)
Programming
Resistor (RTLA)
(Ohms)
-12
-11
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
Open
19,800
9,200
5,490
3,610
2,520
1,780
1,240
866
562
336
150
0
1
2
3
4
5
6
7
8
9
10
11
12
Carrier Detector
The output of the discriminator is meaningful only if there is
sufficient carrier being received. This is established in the
carrier detection circuit which measures the signal on the
line. If this exceeds a certain level for a preset period (ad·
justable by the COT pin) ine CD output goes low indicating
that carrier is present. Then the carrier detect threshold is
lowered oy 3 dB. This provides hysteresis ensuring the CD
output remains stable. If carrier is lost CD goes high after
the preset delay and thO trIrGshold is increased by 3 dB.
MODULATOR SECTION
The modulator consists oi a frequency synthesizer and a
sine wave synihesizei'. ThG fr9ljUency produces one of four
tones depending on Ihe 0; A and TXD pins. The frequencies
are synthesized to high precision using a crystal oscillator
and variable dual mooulus counte ... The counters used reo
spond quickly to data ctlanges. introducing negligible bit jit·
ter while maintaining plla~G coherence.
CARRIER DETECT THRESHOLD ADJUSTMENT
The carrier detect threshold is directly proportional to the
voltage on CDA. This pin is connected internally to a high
impedance source. This source has a nominal Thevenin
equivalent voltage of 1.2V and output impedance of 100 kf!.
By forcing the voltage on CDA the carrier detect threshold
may be adjusted. To find the voltage required for a given
threshold the following equation may be used;
The sine wave synthesizer uses switched capacitors to
"look up" Ihe voltages 01 ti,e sine wave. This sampled sig·
nal is then further pr()c;essed by switched capacitor and
continuous filters to ensure the high spectral purity required
by FCC regulations.
VeDA = 244 X VON
VeDA = 345
x VOFF
CARRIER DETECT TIMING ADJUSTMENT
Applications Information
COT: A capacitor on Pin 4 sets the time interval that the
carrier must be present before CD goes low. It also
sets the time interval that carrier must be removed
before CD returns high. The relevant timing equations
are:
TRANSMIT LEVEL ADJUSTMENT
The transmitted power levels of Table II refer to the power
delivered to a coon load Irom the external 600f! source
impedance. The voltage on the load is half the TXA voltage.
This should be kept in mind when designing interface cir·
cuits which do not match the load and source impedances.
T COL "" 6.4 X CeOT
T eOH '" 0.54 x CeoT
for CD going low
for CD going high
Where T COL & T eOH are in seconds, and CeOT is in ",F.
The transmit leve~ is programmable by placing a resistor
3-348
Applications Information (Continued)
DESIGN PRECAUTIONS
Power supplies to digital systems may contain high amplitude spikes and other noise. To optimize performance of the
MM74HC942 operating in close proximity to digital systems,
supply and ground noise should be minimized. This involves
attention to power supply design and circuit board layout.
Power supply decoupling close to the device is recommended. Ground loops should be avoided. For further discussion
of these subjects see the Audio/Radio Handbook published
by National Semiconductor Corporation.
Interface Circuits for MM74HC942 300 Baud Modem
2 WIRE CDNNECTION
4WIREtONNECTIDN
,
r
r--,
.IA
COMMUNICAnON
CHANNEL
OR
PHONEUNE
[J
"-
I
L.
I
I
I
I
I
RIAl
""
or
""
""
I
I
I
0"
RIAl
I
CO••UNICAT1DN
CIIANNB.
I
.J
••
...
.IA
:"
RIAl
""
RIAl
....
L. :'.11..: .J
TLiF/5348-4
CcOT and ATLA should ba chosen to suH the application. See the Applications Infonnation for mora details.
. Complete Acoustically C~upled 300 Baud Modem
TLA
SQT
150k
MODE SELECT
ALB
EXI
D/~
RlIA2
RXAI
OJIIBINATE
ANSWER
MM7IHC942
,
+5V
TRANSMITTED
DATA
RECEIVED
DATA
~
330
LED
+5V
CARRIER
DETECT
INDICATION
TLiF/6348-5
Note: The efficiency of the acoustic coupling will sat the valves of AI and A2.
3-349
•
~ ~------------------------~--~---------------------------------------------,
-a'
~ ,~National
PRELIMINARY
,t:!:
~ Semiconductor
::&
microCMOS
::&
MM74HC943 300 Baud Modem
General Description
Features
The MM74HC943 is a full duplex low speed modem. It provides a 300 baud bidirectional serial interlace for data communication over telephone lines and other narrow bandwidth channels. It is Bell 103 compatible.
The MM74HC943 utilizes microCMOSTechnology, 2 layers
of polysilicon and 1 layer metal P-well CMOS. Switched capacitor techniques are used to peform analog signal processing.
•
•
•
•
MODULATOR SECTION
The modulator contains a frequency synthesizer and a sine
wave synthesizer. It 'produces a phase coherent frequency
shift keyed (FSK) output.
•
•
•
'.
•
•
5V supply
Drives 6000 at - 9 dBm
All filters on chip
Transmit level adjustment compatible with universal
service order code
TIL and CMOS compatible logic
All inputs protected against static damage
Low power consumption
Full duplex answer or originate operation
Analog loopback for self test
Power down mode
Applications
LINE DRIVER AND HYBRID SECTION
The line driver and hybrid are designed to facilitate connection to a 6000 phone line. They can perform two to four wire
conversion and drive the line at a maximum of - 9 dBm.
DEMODULATOR SECTION
The demodulator incorporates anti-aliasing filters, a receive
filter, limiter, discriminator, and carrier detect circuit. The
nine-pole receive filter provides 60 dB of transmitted tone
rejection. The discriminator is fully balanced for stable
operation.
•
•
•
•
•
•
•
•
Built-in'low speed modems
Remote data collection
Radio telemetry
Credit verification
Stand-alone modems
Point-of-sale terminals
Tone signaling systems
Remote process control
Connection and Block Diagrams
Vee
UNO
GNDA
XTALD
XTALS
Dual-In-Line Package
DSI
TLA
ALB
19
GNDA
Cl!
18
EXI
CDT
11
TXA
RXD
16
RXA1
VCC
15
RXA2
CDA
14
SOT
XTALU
Dill
XTALS
GNU
mc
TXU
10
TOP'VIEW
TLA
D81-+--.........._ - - . ,
TlIA-+--......<
EXI-+....:::==---RXA2 -+_w......--Y>IV--......rir--I
TL/F15349-1
Order Number MM74HC943J
or MM74HC943N
. See NS Package J20A or N20A
RlIA' -+----1
CDA
CDT
mc
TL/F/5349-2
3-350
Absolute Maximum Ratings (Notes 1 & 2)
-0.5 to +7.0V
Supply Voltage (Veel
DC Input Voltage (VIN)
-1.5 to Vee + 1.5V
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
±20mA
Clamp Diode Current (11K, 10K)
±25mA
DC Output Current, per pin (lOUT)
DC Vee or GNo Current, per pin (Ieel
±50mA
Storage Temperature Range (TSTG)
-65"C to + 150"C
Power Dissipation (Po) (Note 3)
500mW
Lead Temp. (TO (Soldering 10 seconds)
260"C
Operating Conditions
Supply Voltage (Veel
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TA)
MM74HC
Input Rise or Fall Times
(tr, tf)
Crystal frequency
Min
4.5
0
Max
5.5
Vee
Units
V
V
-40
+85
"C
500
3.579
ns
MHz
DC Electrical Characteristics Vee=5V ±10% (unless otherwise specified)
. Symbol
Parameter
74HC
TA= -40 to 8S"C
TA=2S"C
Conditions
Typ
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
3.15
3.15
V
VIL
Maximum Low Level
Input Voltage
1.1
1.1
V
VOH
Minimum High Level
Output Voltage
VIN=VIHorVIL
IIOUTI=20 /LA
IIOUTI=4.0 rnA, Vee=4.5V
Vee- 0.1
3.84
Vee- 0.1
3.7
V
V
Maximum Low Level
Voltage
VIN = VIH or VIL
IIOUTI=20 /LA
IIOUTI=4.0 rnA, Vee=4.5V
0.1
0.33
0.1
0.4
V
V
liN
Maximum Input
Current
VIN = Vee or GND
±0.1
±1.0
/LA
loz
Output TRI-STATE®
Leakage Current,
RXD and CD Outputs
ALB=SQT=Vee
±5
/LA
Icc
Maximum Quiescent
Supply Current
VIH = Vee, VIL =GND
ALBorSQT=GND
Trl\nsmit Level = -9 dBm
8.0
10.0
rnA
1.0
2.0
rnA
VOL
IGNOA
. Analog Ground Current
300
ALB=SQT=Vec
/LA
VIH = Vee, VIL =GND
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mW rc from 65·C to 85·C; ceramic "J" package: -12 mWrc from 1OO"C to 125·C.
'The demodulator specifications apply to the MM74HC943 operating with a modDlalor having frequency accuracy, phase jitter and harmonic content equal to or
better than the MM74HC943 modulator.
Icc
Power Down Supply Current
Vec-EE
3-351
AC Electrical Characteristics
Unless otherwise specified, all specifications apply to the MM74HC943 over the range -40"C to
± 10%, and a 3.579 MHz ± 0.1 % crystal.·
Symbol
I
I
Parameter
I
Conditions
+ 85°C using a Vee of + 5V
Min
I
Typ
I
Max
I
Units
TRANSMITTER
FCE
.,
Carrier Frequency Error
Power Output
I RTLA = 54900
VCc=5.0V
RL =1.2 kO
-12
2nd Harmonic Energy
4
Hz
-10.5
-9
dBm
-62
-56
dBm
RECEIVE FILTER AND HYBRID
Hybrid Input Impedance
(Pins 15 and 16)
50
FTLC Output Impedance
5
Adjacent Channel Rejection
kO
10
50
60
RXA2=GNDA, TXD=GNDorVee
Input to RXA 1
kO
dB
DEMODULATOR (INCORPORATING HYBRID, RECEIVE FILTER AND DISCRIMINATOR)
-48
Carrier Amplitude
5NR = 30 dB
Input = -38 dBm
Baud Rate = 300 Baud
Bit Jitter
Bit Bias
Alternating 1-0 Pattern
Carrier Detect Trip Points
CDA=1.2V
I
I
Vee=5.0V
Carrier Detect Hystereisis
}
100
-12
dBm
200
,..,5
5
10
%
Off to On
-45
-42
-40
dBm
On toOfi
-47
-45
-42
dBm
2
3
4
dB
Vee=5.0V
AC Specification Circuit
3.5795 MHz ± 0.111
SUPPLIES Vee = +5V
rD~
RTLA
Uk
.
600
10~
~
TXO
"I
RXAI
RXO
CDT
'CDA
0:-
0:-
0:-
0:-
I+-- DATA INPUT
r--+ DATA OUTPUT
~.mc
~
±,,~±.,,'=t,
TEST '"
INPUT
..L 1oo pF f " 1 pF
/
TEST
OUTPUT
+5V
2. 2k
MM74HC943
600
.
ONOA
TLA
roo- TXA
~ RXA2
Vee
.,
GNOA
TLlF/5349-3
3-352
Description of Pin Functions
Pin
No.
1
2
Name
Function
DSI
Driver Summing Input: This input may be
used to transmit externally generated tones
such as dual tone multifrequency (DTMF) di·
aling signals.
Analog Loop Back: A logic ,high on this pin
causes the modulator output to be connected to the demodulator input so that data is
looped back through the entire chip. This is
used as a chip self test. If ALB and SaT are
simultaneously held high the chip powers
down.
Carrier Detect: This pin goes to a logic ,low
when carrier is sensed by the carrier detect
circuit.
Carrier Detect Timing: A capacitor on this
pin sets the time interval that the carrier
must be present before the CD goes low.
Received Data: This is the data output pin.
ALB
3
CD
4
CDT
5
6
7
8
RXD
Positive Supply Pin: A + 5V supply is recommended.
Carrier Detect Adjust: This is used for adjustment of the carrier detect threshold. Carrier detect hysteresis is set at 3 dB.
Vee
CDA
XTALD
9
XTALS
10
FTLC
Crystal Drive: XTALD and XTALS connect
to a 3.5795 MHz crystal to generate a crystal locked clock for the chip. If an external
circuit requires this clock XTALD should be
sensed. If a suitable clock is already available in the system. XTALD can be driven.
Crystal Sense: Refer to pin 8 for details.
Filter Test/Limiter Capacitor: This is connected to a high impedance output of the
receiver filter. It may thus be used to evalu-
11
12
13
TXD
GND
OlA
14
SaT
1"5
RXA2
ate filter performance. This pin may also be
driven to evaluate the demodulator. RXA 1
and RXA2 must be grounded during this
test.
For normal modem operation FTLC is AC
grounded via a 0.1 J.tF bypass capacitor.
Transmitted Data: This is the data input.
Ground: This defines the chip OV.
Originatel Answer mode select: When logic
high this pin selects the originate mode of
operation.
Squelch Transmitter: This disables the modulator when held high. The EXI input remains active. If SaT and ALB are simultaneously held high the chip powers down.
Receive Analog #2: RXA2 and RXA1 are
analog inputs. When connected as recommended they produce a 600n hybrid.
16
RXA1
Receive Analog # 1: See RXA2 for details.
17
TXA
18
EXI
19
GNDA
Transmit Analog: This is the output of the
line driver.
External Input: This is a high impedance input to the line driver. This input may be used
to transmit externally generated tones.
When not used for this purpose it should be
grounded to GNDA.
Analog Ground: Analog signals within the
chip are referred to this pin.
20
TLA
Transmit Level Adjust: A resistor irom this
pin to Vee sets the transmit level.
Functional Description
INTRODUCTION
A modem is a device-for transmitting and receiving serial
data over a narrow bandwidth communication channel. The
MM74HC943 uses frequency shift keying (FSK) of audio frequency tone. The tone may be transmitted over the
switched telephone network and other voice grade channels. The MM74HC943 is also capable ,of demodulating
FSK signals. By suitable tone allocation and considerable
signal processing the MM74HC943 is capable of transmitting and receiving data simultaneously.
THE LINE INTERFACE
The line interface section performs two to four wire conversion and provides impedance matching between ttlO modem and the phone line.
THE LINE DRIVER
The line driver is a power amplifier for driving the line. If the
modem is operating as an originate modem, the second harmonics of the transmitted tones fall close to the frequencies
of the received tones and degrade the received signal to
noise ratio (SNR). The line driver must thus produce low {
second harmonic distortion.
The tone allocation used by the MM74HC943 and other Bell
103 compatible modems is shown in Table I. The terms
"originate" and "answer" which define the frequency allocation come from use with telephones. The modem on the
end of the line which initiates the call is called the originate
modem. The other modem is the answer modem.
THE HYBRID
The voltage on the telephone line is the sum of the transmitted and received signals. The hybrid subtracts the transmitted voltage from the voltage on the telephone line. If the
telephone line was matched to the hybrid impedanoe, the
output of the hybrid would be only the received signal. This
rarely happens because telephone line characteristic impedances vary considerably. The hybrid output is thus a
mixture of transmitted and received Signals.
TABLE I Bell 103 Tone Allocation
Data
Originate Modem
Answer Modem
Transmit
Receive
Transmit
Receive
Space
1070Hz
2025Hz
2025Hz
1070Hz
Mark
1270Hz
2225Hz
2225Hz
1270Hz
3-353
F,unctional Description
(Continued)
impedance. The voltage on the load is half the TXA voltage.
This should be kept in mind when designing interface circuits which do not match the load and source inpedances.
THE DEMODULATOR SECTION
The Receive Filter
The demodulator recovers the data from ,the received sig,nals. The signal from the hybrid is a mixture of transmitted
signal, received signals and noise. The first stage of the
receive filter is an anti-alias filter which attenuates high frequency noise before sampling occurs. The signal then goes
to the second stage of the receive filter where the transmitted tones and other noise are filtered from the received signal. This is a switch capacitor nine pole filter providing at
least 60 dB of transmitted tone rejection. This also provides
high attenuation at 60Hz, a common noise component.
The transmit level is programmable by placing a resistor
from TLA to Vee. With a 5.5k resistor the line driver transmits a maximum of -9 dBm. Since most lines from a phone
installation to ,the exchange provide 3 dB of attenuation the
maximum level reaching the exchange will be -12 dBm.
This is the maximum level permitted by most telephone
companies. Thus with this programming the MM74HC943
will interface to most telephones. This arrangement is called
the "permissive arrangement." The disadvantage with the
permissive arrangement is that when the loss from a phone
to the exchange exceeds 3 dB, no compensation is made
and SNR may be unnecessarily degraded.
The Discriminator
The first stage of the discriminator is a hard limiter. The hard
limiter removes from the received signal any amplitude
modulation which may bias the demodulator toward a mark
or a space. It compares the output of the receive filter to the
voltage on the 0.1 p.F capacitor on the FTLC pin.
TABLE II. Universal Service Order Code Resistor Values
The hard limiter output connects to two parallel bandpass
filters in the discriminator. One filter is tuned to the mark
frequency and the other to the space frequency. The outputs of these filters are rectified, filtered and compared. If
the output of the mark path exceeds the output of the space
path the RXO output goes high. The oppOSite case sends
RXO low.
Line
Loss
(dB)
Transmit
Level
(dBm)
Programming
Resistor (RTLA)
(0)
0
1
2
3
-12
-11
-10
-9
Open
19,800
9,200
5,490
CARRIER DETECT THRESHOLD ADJUSTMENT
The carrier detect threshold is direcUy proportional to the
voltage on COA. This pin is connected internalfy to a high
impedance source. This source has a nominal Thevenin
equivalent voltage of 1.2V and output impedance of 100 kO.
The demodulator is implemented using precision switched
capaCitor techniques The highly critical comparators in the
limiter and discriminator are auto-zeroed for low offset.
Carrier Detector
The output of the discriminator is meaningful only if there is
sufficient carrier being received. This is established in the
carrier detection circuit which measures the signal on the
line. If this exc,eeds a certain level for a preset period (adjustable by the COT pin) the CD output goes low indicating
that carrier is present. Then the carrier detect threshold is
lowered by 3 dB. This provides hysteresiS ensuring the CD
output remains stable. If carrier is lost CD goes high after
the preset delay and the threshold is increased by 3 dB.
By forcing the voltage on COA the carrier detect threshold
may be adjusted. To find the voltage required for a given
threshold the following equation may be used:
VCDA=244 X VON
VCDA=345 X VOFF
CARRIER DETECT TIMING ADJUSTMENT
COT: A capacitor on Pin 4 sets the time interval that the
carrier must be present before CD goes low. It also
sets the time interval that carrier must be removed
before CD returns high. The relevant timing equations
are:
MODULATOR SECTION
The modulator consists of a frequency synthesizer and a
sine wave synthesizer. The frequency synthesizer produces
one of four tones depending on the O/A and TXO pins. The
frequencies are synthesized to high preCision using a crystal
oscillator and variable dual modulus counter.
TCDL '" 6.4 X CCDT for CD going low
TOOH .. 0.54 X CcDT for CD going high
Where TCi)[ & TeDH are in seconds, and CCDT is in p.F.
DESIGN PRECAUTIONS
The counters used respond quickly to data changes, intrQducing negligible bit jitter while maintaining phase coherence.
Power supplies to digital systems may contain high amplitude spikes and other noise. To optimize performance ofthe
MM74HC943 operating in close prOximity to digital systems,
supply and ground noise should be minimized. This involves
attention to power supply design and circuit board layout.
Power supply decoupling close to the device is recommended. Ground loops should be avoided. For further discussion
of these subjects see the Audio/Radio Handbook published
by National Semiconductor Corporation.
The sine wave synthesizer uses switched capaCitors to
"look up'~ the voltages of the sine wave. This sampled signal is then further processed by switched capaCitor and
continllous filters to ensure the high spectral purity required
by FCC regulations.,
Applications Information
TRANSMIT LEVEL ADJUSTMENT
The transmitted power levels of Table II refer to the power
delivered to a 6000 load from the external 6000 source
3-354
.-----------------------------------------------------------------,~
Applications Information (Continued)
....~
.
~
:::t:
oCD
Interface Circuits for MM74HC943 300 Baud Modem
~
Co)
2 Wire Connection
r
..,
Uk
GNOA
TXl
I
COMC~~::~ION
:f~
OR
I
r°,.F1,·F
RIl2
I
Uk
':"
Vee
&DO
RIAl
MM74HC943
RTLA
1),,(
TLA
TID
I
L
+6V
-:::~T
DATA
OUTPUT
RID
.J
J T FL"F
CC
"'
D1
. •
':"
GNOA
Tl/F/5349-4
4 Wire Connection
+sv
r--,
Uk
10,.1'
: EJrc·0
600
'"
I
I
L
COMC~~:~:[ION
DR
PHONE LINE
:
I
...J
+
':"
Vee
MM74HC943
RTLA
TLA
6DO
':"
Uk
100,.1'11,.1'
1:ICE':"0.1,.1'
I
GNOA
TIA
0.1 ,.I'
TXD
DATA
INPUT
RXD
DATA
OUTPUT
TLlF/5349-5
CCDT and RTLA should be chosen to suit the application. See the Applications Inlonnation lor more details.
3-355
~
~
r------------------------------------------------------------------------------------------,
Complete Acouatlcally Coupled 300 Baud Modem
o
::c
"IiI'
+5V
"""
:IE
:IE
TLA
lSOk
saT
DSI
D.l.F
Rl
EXI
RXA2
O/X
ORIGINATE •
ANSWER
MM74HC943
RXAI
,
+5V
TRANSMITTED
OATA
RECEIVED
DATA
lk
T
FTlC
1 F
•
'flI
0.1 pi'
GNDA
330
lED
+5V
CARRIER
DETECT
INDICATION
UK
TLlF/5349-6
Nota: The efficiency of the acoustic coupling will set the values of Rl and R2.
3-356
~National
~ Semiconductor
microCMOS
MM54HC4002/MM74HC4002
Dual 4-lnput NOR Gate
General Description
Features
These NOR gates utilize microCMOS Technology, 3.5 micron silicon gate P-well CMOS, to achieve operating speeds
similar to LS-TTL gates with the low power consumption of
standard CMOS integrated circuits. All gates have buffered
outputs, providing high noise immunity and the ability to
drive 10 LS-TTL loads. The 54HC17 4HC logic family is functionally as well as pin-out compatible with the standard
54LS174LS logic family. The 54HC4002/74HC4002 is functionally equivalent and pin-out compatible with the
CD4002B. All inputs are protected from damage due to static discharge by internal diode clamps to Vee and ground.
•
•
•
•
•
Typical propagation delay: 8 ns
Wide power supply range: 2V-6V
Low quiescent current: 20 /LA maximum (74HC Series)
Low input current: 1 /LA maximum
Fanout of 10 LS-TTL loads
Connection Diagram
Vee
14
Y2
Dual·ln·Line Package
A2
82
C2
13
1
Y1
81
12
11
3
4
C1
D2
9
5
D1
8
7
NC
TOP VIEW
Y=A+B+C+O
Order Number MM54HC4002J or MM74HC4002J, N
See NS Package J14A or N14A
3·357
NC
GND
TL/F/5154-1
Absolute Maximum Ratings (Notes 1 i
Supply Voltage (Vee) ,
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K. 10Kl
DC Output Current. per pin (lOUT)
DC Vee or GND Current. per pin (IcC>
Storage Temperalljre Range (TSTG)
Power Dissipation (Po) (Note 3)
Lead Temp. (Tu (Soldering 10 seconds)
Operating Conditions
2)
-0.5 to + 7.0V
-1.5 to Vee + 1.5V
-0.5 to Vee + 0.5V
±20mA
±25mA
±50mA
-65·C to + 150·C
Supply Voltage (VeC>
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TAl
MM74HC
MM54HC
Input Rise or Fall Times
Vee=2.0V
(tr• tt)
Vee=4.5V
Vee=·6.0V
500mW
260·C
Parameter
Conditions
Vee
Max
6
Vee
Units
V
V
-40
-55
+85
+125
'C
·C
1000
500
400.
ns
ns
ns
,
,
DC Electrical Characteristics (Note 4)
Symbol
Min
2
0
TA=25"C
Typ
74HC
TA= -40 to 85·C
54HC
TA= -55 to 125·C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9·
1..2
V
V
V
'VOH
Minimum High Level
Output Voltage
VIN=VIHorVIL
IIOUTI ~ 20 p.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
IloUTI~4mA
IIOUTI~5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
V
VIN = Vee or GND
6.0V
±0.1
±1.0
±1.0
",A
".
VIN = VIH or VIL
IIOUTI~4.0 mA
IIOUTI ~ 5.2 mA
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
,
VIN=VIHorVIL
IIOUTI~20p.A
Maximum Quiescent VIN=Vee or GND
40
p.A
6.0
2.0
20
Supply Current
10UT=0 p.A
Note I: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voHages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mW/'C from 6S'C to 8S'C; ceramic "J" package: -12 mWrc from IOO'C to 125"C.
Nole 4: For a power supply of 5V ±IO% the worst cesa output voltages (VOH. and VoU occur fo(HC at 4.SV. Thus the 4.SV values should ba used when
designing with this supply. Worst case VIH and VIL occur at Vcc= S.SV and 4.5V respectively. (The VIH value at S.5V is 3.8SV.) The worst case leakage current (liN.
Icc. and loz) occur for CMOS at the higher voltage and so the 6.0V values should be used.
Icc
3-358
AC Electrical Characteristics Vee = 5V, TA = 25'C, CL = 15 pF, t,= t,= 6 ns
Symbol
Parameter
Conditions
tpHL, tpLH\
Maximum Propagation
Delay
Typ
Guaranteed
Limit
Units
11
20
ns
AC Electrical Characteristics Vee=2.0Vto 6.0V, CL =50pF, t,=t,=6 ns
Symbol
Parameter
Conditions
TA=25'C
Vee
Typ
74HC
TA= -40 to 85'C
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
tpHL, tpLH
Maximum Propagation
Delay
2.0V
4.5V
6.0V
40
12
10
120
24
20
151
30
26
179
36
30
ns
ns
ns
tTLH, tTHL
Maximum Output
RiseardFall
Time
2.0V
4.5V
6.0V
.30
10
9
75
15
13
95
19
16
110
22
19
ns
ns
ns
CPD
Power Dissipation
Capacitance (Note 5)
C,N
Maximum Input
Capacitance
(per gate)
25
5
pF
10
10
10
pF
Nole 5: CPO determines the no load dynamic power consumption, Po ~ Cpo Vce? f+ Icc Vee, and the no loa~ dynamic current consumption, Is ~ Cpo Vee f + Icc.
3-359
.... r----------------------------------------------------------------------------,
U)
~
o
::c
"=I'
.....
'?'A National
~ Semiconductor
::E
::E
.....
.... MM54HC4016/MM74HC4016
U)
~
o
::c
"=I'
\I)
::E
::E
Quad Analog Switch
General Description
Features
These devices are digitally controlled analog switches implemented in microCMOS Technology, 3.5 micron silicon
gate P-well CMOS. These switches have low "on" resistance and low "off" leakages. They are bidirectional
switches, thus any analog input may be used as an output
and vice-versa. The '4016 devices allow control of up to
12V (peak) analog signals with digital control signals of the
same range. Each switch has its own control input which
disables each switch when low. All analog inputs and outputs and digital inputs are protected from electrostatic damage by diodes to Vee and ground.
•
•
•
•
•
•
Connection Diagram
Truth Table
Typical switch enable time: 15 ns
Wide analog input voltage range: 0-12V
Low "on" resistance: 500 typo
Low quiescent current: 80 /LA maximum (74HC)
Matched switch characteristics
Individual switch controls
Dual-In-Line Package
vee
11/0
lcn
1011
4CTL
20/1
41/0
21/0
40/1
30/1
2CTL3Cn
31/0
Input
Switch
CTL
1/0-0/1
L
H
"OFF"
"ON"
GND
Tl/F/5350-1
Top View
Order Number MM54HC4016J or MM74HC4016J, N
See NS Package J14A or N14A
Schematic Diagram
TLiF/5350-2
3-360
Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage (Vecl.
Operating Conditions
-0.5 to +15V
DC Control Input Voltage (VIN)
-1.5to Vce+ 1.5V
DC Switch I/O Voltage (VIO)
-0.5 to Vee+ 0.5V
±20mA
±25mA
±50mA
-65·C to + 150·C
Clamp Diode Current (11K, 10K)
DC Output Current, per pin (lOUT)
DC Vee or GND Current, per pin (Icel
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
Lead Temp. (TL! (Soldering 10 seconds)
Supply Voltage (Vecl
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TAl
MM74HC
MM54HC
Input Rise or Fall Times
Vee=2.0V
(t" til
Vee=4.5V
Vee=6.0V
500mW
260·C
Min
2
Max
12
Units
V
0
Vee
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25·C
Typ
74HC
S4HC
TA= -40 to 8S·C TA= -SSto 12S·C Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
9.0V
12.0V
1.5
3.15
6.3
8.4
1.5
3.15
6.3
8.4
1.5
3.15
6.3
8.4
V
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
9.0V
12.0V
0.3
0.9
1.8
2.4
0.3
0.9
1.8
2.4
0.3
0.9
1.8
2.4
V
V
V
V
RON
Maximum 'ON' Resistance VeTL=VIH, Is=1.0 mA 4.5V 100
(See Note 5)
9.0V 50
Vls=VeetoGND
(Figure 1)
12.0V 30
170
85
70
200
105
85
220
120
100
2.0V 100
VeTL =VIH, Is=1.0 mA 4.5V 40
9.0V 35
VIS = Vee or GND
(Figure 1)
12.0V 20
180
80
60
40
215
100
75
60
240
120
80
70
15
10
10
20
15
15
20
15
15
n
n
n
n
n
n
n
n
n
n
±0.1
±1.0
±1.0
p.A
±600
±800
±1000
±600
±800
±1000
nA
nA
nA
±150
±200
±300
±150
±200
±300
nA
nA
nA
20
BO
160
40
160
320
p.A
p.A
p.A
RON
Maximum 'ON' Resistance VeTL =VIH
Matching
Vls=VcctoGND
liN
Maximum Control
Input Current
VIN = Vee or GND
Vee=2-6V
liZ
Maximum Switch 'OFF'
Leakage Current
Vos=VeeorGND
Vls=GNDorVee
VeTL =VIL (Figure 2)
l~.OV
±60
±80
±100
liZ
Maximum Switch 'ON'
Leakage Current
Vos=VceorGND
VeTL =VIH
(Figure 3)
5.5V
9.0V
12.0V
±40
±50
±60
Maximum Quiescent
Supply Current
VIN=VeeorGND
IOUT=O .uA
4.5V
9.0V
12.V
5.5V
9.0V
10
5
5
5.5V
2.0
9.0V
B.O
12.0V
16.0
Nole 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Icc
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mWI'C from 6S'C to 8S'C; ceramic "J" package: -12 mWI'C from 100'e to 12S'C.
Note 4: For a powe, supply of SV ± 10% the worst case on resistances (RON) occurs for HC at 4.SV. Thus the 4.SV values should be used when designing with
this supply. Worst case VIH and VIL occur at Vee = S.SV and 4.SV respectively. (The VIH value at S.SV is 3.8SV.) The worst case leakage current occur for CMOS at
the higher voltage and so these values should be used.
Nole 5: At supply voltages (Vee-VEE) approaching 2V the analog switch on resistance becomes extremely non·llnear. Therefore it Is recommended that these
devices be used to transmit digital only when using these supply voltages.
3-361
AC Electrical Characteristics Vee = 2.0V-6.0V. CL =50 pF (unless otherwise specified)
Symbol
Parameter
74HC
TA= -40to8SoC
TA=2SoC
Condltlon$
Vee
Typ
tpHL. tpLH
Maximum Propagation
, Delay Switch In to
Out
tPZL. tpZH
Maximum Switch Turn
"ON" Delay
tpHZ. tpLZ
,
fMAX
Maximum Switch Turn
"OFF" Delay
RL =1 kO
RL = 1 kO
Maximum Switch
Frequency Response
20 log{VIIVO)= -3 dB
S4HC
TA=-SSto12SoC
Units
Guaranteed Umlts
2.0V
4.5V
9.0V
12.0V
25
5
4
3
50'
10
8
?
62
13
12
11
75
15
14
13
ns
ns
ns
ns
2.0V
4.5V
9.0V
12.0V
32
8
6
5
100
20
12
10
125
25
15
13
150
30
18
15
ns
ns
2.0V
4.5V
9.0V
12.0V
45
15
10
8
168
36
32
30
210
45
40
38
252
54
48
45
4.5V
9.0V
35
40
MHz
MHz
80
mVp_p
JlS
ns
ns
ns
ns
ns
Cross Talk Control
to Switch
(Figure?)
4.5V
Cross Talk Between
any Two Switches
{Frequency at - 50 dB)
(Figure 8)
4.5V
MHz
Switch Feedthrough
Input to Output
F=5MHz
F=10MHz
4.5V
4.5V
dB
dB
pF
CIN
Maximum Control
Input Capacitance
5
CIN
Maximum Switch
Input Capacitance
15
pF
CIN
Maximum Feedthrough
Capacitance
VCTL=GND
5
pF
CPO
Power Dissipation
Capacitance
(per switch)
15
pF
10
10
.
Typical Performance Characteristics
Typical "On" Resistance
Versus Input Voltages ('4016)
180
g
150
~ 120
.~
,
z
i!
Z:
~
~
90
60
Ve =4.5V
~
~~ ;~=gIO~
30
' Vee=12.OV
0
0
2
4
6
lT
B
INPUT VOLTAGE (V)
3-362
10
12
TLlF/5350-17
10
AC Test Circuits and Switching Time Waveforms
Ven -vee - - - - - .
VeTL=OV - - - - - .
1 OF 4
SWITCHES
1/0
VIS
011
1--.....- -
AMMETER
1 OF 4
SWITCHES
VIS = GND OR Vee
GND
~
Vos
0/11----- Vos=VeeORGND
GNO
'::"
L----{_l-----'
TLlF/5350-4
FIGURE 2. "OFF" Channel Leakage Current
TLlF/5350-3
FIGURE 1. "ON" Resistance
1 OF 4
SWITCHES
Vls=Vee
TOONO
0111----
Vos (OPEN)
GND
TL/F/5350-5
·FIGURE 3. "ON" Channel Leakage Current
Vee
Vee----+-.Jp~-_L
VIS
ov---"'-I
t-...- - - - - V o s
liD
Voo-----+_---
Vos
OV---TLlF/5350-7
TLlF/5350-6
FIGURE 4. tpHL> tpLH Propagation Delay Time Signal Input to Signal Output
Vee
VCTL-----.
CONTROL
Vee
110 S~I~~H~S 011 l-+-vos
VEE
IpZL
Vee
IpLZ
vec~IPZL
50%
OV~PZL
Yoo
90%
IpLZ
~
v::~PLZ
10%
VOL
VOL
FIGURE 5. tpZL. tpLZ Propagation Delay Time Control to Signal Output
3-363
TL/F/5350-9
,
~
..-
g
o
r-------------------------------------------------------------------------,
AC Test Circuits and Switching Time Waveforms
(Continued)
:::E:
•....
....
VeTL
g
Vls=Vee
:E
:E
~
..-
Vee
tpZH
vee~
50%
CONTROL
Vos
o
:E
.~
OV
II)
VEE
vee~
50%
VOH~
10%
":'
Voo
OV
VOH
RL
1k
:::E:
•
:E
tpHZ
OV
TL/F/5350-11
TLlF/5350-10
FIGURE 6. tpZH,tpHZ Propagation Delay Time Control to Signal Output
t r=6ns
11=6.0
VeTL
ve
OV
vee
IN/OUT S~I~~:ES OUT/IN
AIH
Vos
GNO
Al
Boon
":'
BOon
":'
J
CL
50
Vos
+
CROSSTALK
t
PF
TLlF/5350-13
":'
TLlF/5350-12
FIGURE 7. Crosstalk: Control Input to Signal Output
VeTL(1I-Vec---....,
Vee
Boon
_-'\I~---1IN/OUT S~I~~:ESOUT/INI-~,...-VOSll)
GNO
TL/F/5350-14
TL/F/5350-15
VCTLlZ)-OV----....,
IN/OUT S~I~~:ESOUTIINI-~,...-VoS(Z)
TLlF/5350-16
FIGURE 8: Crosstalk Between Any Two Switches
3-364
~National
PRELIMINARY
~ Semiconductor
'"
J
microCMOS
MM54HC4017/MM74HC4017
Decade CounterIDivider with 10 Decoded Outputs
General Description
The MM54HC4017/MM74HC4017 is a 5-stage Johnson
counter with 10 decoded outputs that utilizes microCMOS
Technology, 3.5 micron silicon gate P-well CMOS. Each of
the decoded outputs is normally low and sequentially goes
high on the low to high transition of the clock input. Each
output stays high for one clock period of the 10 clock period
cycle. The CARRY output transitions low to high after OUTPUT 10 goes low, and can be used in conjunction with the
CLOCK ENABLE to cascade several stages. The CLOCK
ENABLE input disables counting when in the high state. A
RESET input is also provided which when taken high sets all
the decoded outputs low except output O.
The MM54HC4017IMM74HC4017 is functionally and pinout
equivalent to the CD4017BM/CD4017BC., It can drive
up to 10 low power Schottky equivalent loads. All inputs are
protected from damage due to static discharge by diodes
from Vee and ground.
Features
•
•
•
•
•
Wide power supply range: 2-6V
Typical operating frequency: 30 MHz
Fanout of 10 LS-TTL loads
Low quiescent current: 80 IJ-A (74HC Series)
Low input current: 1.0 IJ-A
Connection Diagram
Dual-In-Llne and Flat Package
u
DECODED OUTPUT "5"
..L
.!!.
Vee
DECODED OUTPUT "1"
...!..
l!.
RESET
DECODED OUTPUT ''0''
2.
..!
...!
.!!.
CLOCK
DECODED OUTPUT "2"
DECODED OUTPUT "Ii"
E.
CLOCK ENABLE
.!!.
CIIRRY·OUT
..!
..!.
~
OECDDED DUTPUT "g"
DECODED OUTPUT "3"
r!!-
DECDDED OUTPUT "4"
GND
..!.
.L
DECODED OUTPUT "."
OECODEO OUTPUT "7"
TDP VIEW
TLlF/5351-1
Order Number MM54HC4017J or MM74HC4017J,N
See NS Package J16A or N16E
3-365
Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage {Veel
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K. 10K)
DC Output Current. per pin (lOUT)
DC Vee or GND Current. per pin (Ieel
Storage Temperature Range (T8TG)
Power Dissipation (Po) (Note 3)
Lead Temperafure (T Ll
(Soldering 10 seconds)
Operating Conditions
-0.5 to +7.0V
Supply Voltage {Veel
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TAl
MM74HC
MM54HC
Input Rise or Fall Times
Vee=2.0V
(tr• til
Vee=4.5V
Vee=6.0V
-1.5 to Vee + 1.5V
-0.5 to Vee+0.5V
±20mA
±25mA
±50mA
- 65'C to + 150'C
500mW
260'C
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
TA=25'C
Vee
Typ
74HC
TA= -40 to 85'C
54HC
TA= -55to 125'C
Units
Guaranteed Limits
VIH
Minimum High Level,
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V,
V
V
, VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
IIOUTI~20 IlA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
IIOUTI ~4.0 mA
IIOUTI~5.2mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VeeorGND
6.0V
±0.1
±1.0
±1.0
IlA
VIN = VIH or VIL
IIOUTI~4.0mA
IIOUTI~5.2 mA
VOL
liN
Maximum Low Level
Output Voltage
Maximum input
Current
V
VIN = VIH or VIL
IIOUTI~20 IlA
-
Maximum Quiescent VIN=VeeorGND 6.0V
80
160
8.0
IlA
Supply Current
IOUT=O IlA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device mey occur.
Note 2: Unless otherwise specified all voltages are referenced to ground,
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mwre from 6S'C to 8S'C; ceramic "J" package: -12 mWI'C from 100'C to 12S'C.
Note 4: For a power supply of SV ± 10% the worst case output voltages (VOH. and Vou occur for HC at 4.SV. Thus the 4,SV values should be used when
designing with this supply. Worst case VIH and 'ilL occur at Vee =S.SV and 4.SV respectively. (The VIH value at S.SV is 3.8SV.) The worst case leakage current (liN.
ICC. and loz) occur for CMOS at the higher voltage and so the 6.0V values should be used,
Icc
I
3·366
AC Electrical Characteristics
Symbol
Vcc=5V, TA=25'C, CL= 15 pF, t,=tl=6 ns
Parameter
Conditions
Typ
Guaranteed
Limit
Units
Measured with
respect to carry line
50
30
MHz
fMAX
Maximum Clock Frequency
tpHL, tpLH
Maximum Propagation
Delay, Enable to Carry-Out Line
26
44
ns
tpHL, tpLH
Maximum Propagation
Delay Enable Decode-Out Lines
27
44
ns
tpHL, tpLH
Maximum Propagation
Delay, Reset or Clock to Decode Out
23
40
tpHL, tpLH
Maximum Propagation
Delay, Reset or Clock to Carry Out
23
40
ns
ts
Minimum Clock Inhibit to Clock
Set-UpTime
12
20
ns
Minimum Clock or Reset Pulse Width
8
16
ns
Minimum Reset Removal Time
20
10
ns ,
tw
,
tREM
AC Electrical Characteristics
Symbol
Parameter
Vcc=2.0-6.0V, CL =50 pF, t,=tl=6 ns (unless otherwise specified)
Conditions
Vee
_,
74HC
54HC
TA-25 C TA= -40 to 85'C TA= -55to 125'C Units
Typ
fMAX
Maximum Clock Frequency
\
ns
I
Measured with
2.0V
respect to carry line 4.5V
6.0V
Guaranteed Limits
4
20
23
3
16
18
3
13
15
MHz
MHz
MHz
tpHL, tpLH Maximum Propagation
Delay, Enable to Carry-Out Line
2.0V 89
4.5V 25
6.0V 20
250
50
43
312
63
54
375
75
65
ns
ns
ns
tpHL, tpLH Maximum Propagation
Delay, Enable to Decode Out Line
2.0V 90
4.5V 25
6.0V 20
250
50
43
312
63
54
375
75
65
ns
ns
ns
tpHL, tpLH Maximum Propagation
Delay, Reset or Clock to Decode Out
2.0V 82
4.5V 22
6.0V 18
230
46
39
288
58
49
345
69
59
ns
ns
ns
tpHL, tpLH Maximum Propagation
Delay, Reset or Clock to Carry Out
2.0V 82
4.5V 22
6.0V 18
230
46
39
288
58
49
345
69
59
ns
ns
ns
tw
Minimum Reset or Clock Pulse
Width
2.0V 30
4.5V 9
6.0V 8
80
16
14
100
20
18
120
24
21
ns
ns
ns
tREM
Minimum Reset Removal Time
2.0V
4.5V
6.0V
100
20
17
125
25
21
150
30
25
ns
ns
ns
Is
Minimum Clock Inhibit
to Clock Set-Up Time
2.0V
4.5V
6.0V
50
10
9
63
13
11
75
15
13
ns
ns
ns
2.0V 30
4.5V 8
6.0V 7
75
15
13
95
19
16
110
22
19
ns
ns
ns
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
tTHL, tTLH Maximum Output Rise
and Fall Time
t"tl
Minimum Input Rise and Fall Time
CPD
Power Dissipation
Capacitan'ce (Note 5)
2.0V
4.5V
6.0V
(per package)
pF
10
10
pF
10
Maximum Input Capacitance
5
CIN
Note 5: CPO dete,mlnes the no load dynamic powe, consumption, Po~CPO Vcc2 1+ Icc Vee. and the no load dynamic current consumption, Is ~ CpO Vee 1+ Icc.
3-367
Logic and Timing Diagrams
MM54HC4017/MM74HC4017
,'-:'5"
. ".
"1"
"3"
caUT
TERMINAL NO.' = GND
TERMINAL NO. 1&" Vee
"0"
"a"
..."
"2"
"C"
TlIF/535' -2 ,
CLOCK
RESET
CLOCK
"\
________________________11L--
ENABLE
"0"
"'"
"2"
_ _ _ _-J~~______________________~r-tL
"3"
~~
__________
______
r
-J~~
"4"
"5"
''8''
"7"
______________
_________________________
J~~
________________
______________________
J~L__
__________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
--J~~
______________________
-Jr-}~
"." ________________________
"g"
CARRV·
OUT
\~
________________
______________
~Jr-}~
___________
____________JI
TLlF/535'-3
3·368
J?'A National
~ Semiconductor
.
\
")
microCMOS
MM54HC4020/MM74HC4020
14-Stage Binary Counter
MM54HC4024/MM74HC4024
7-Stage Binary Counter
MM54HC4040/MM74HC4040
12-Stage Binary Counter
General Description
The MM54HC4020/MM74HC4020, MM54HC40241
MM74HC4024, MM54HC4040/MM74HC4040, are high
speed binary ripple carry counters. These counters are implemented utilizing microCMOS Technology, 3.5 micron silicon gate P-well CMOS, to achieve speed performance similar to LS-TTL logic while retaining the low power and high
noise immunity of CMOS.
The 'HC4020 is a 14 stage counter, the 'HC4040 is a 12stage counter, and the 'HC4024 is a 7-stage counter. All
these devices are incremented on the falling edge (negative
transition) of the input clock, and all their outputs are reset
to a low level by applying a logical high on their reset input.
These devices are pin equivalent to the CD4020, CD4024
and CD4040 respectively. All inputs are protected from
damage due to static discharge by protection diodes to Vee
.and ground.
Features
•
•
•
•
•
Typical propagation delay: 16 ns
Wide operating voltage range: 2-6V
Low input current: 1 p.A maximum
Low quiescent current: 80 p.A maximum (74HC Series)
Output drive capability: 10 LS-TTL loads
Connection Diagrams
Dual-In-Line Packages
~c
,'0
011
15
010
14
09
0'
13
12
RESET
CLOCK
11
10
Ne
01
13
01
12
02
11
Ne
-
012
013
014
QS
05
07
7
04
.I'
CLOCK
GND
-
RESET
~c
J10
011
15
OtO
14
0'
07
00
TOP VIEW
TLlF/5216-1
TDPVIEW
09
13
12
RESET
CLOCK
11
10
Q1
r-
Q12
06
05
07
Q4
TOP VIEW'
03
7
Q2
J..'
GND
TLlF/5216-3
Order Number MM54HC4020J, MM54HC4024J, MM54HC4040J,
MM74HC4020J, N, MM74HC4024J, N or MM74HC4040J, N
See NS Package J14A, J16A, N14A or N16E
3-369
Ne
03
10
05
Q4
G!:
TL/F/5216-2
Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage (Ved
DC Input Voltage (V,N)
DC Output Voltage (Vour)
Clamp Diode Current (leo)
DC Output Current, per pin (lour)
DC Vee or GND Current, per pin (Ieel
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
Lead Temperature'(TLl
. (Sold~ring 10 seconds)
Operating Conditions
-0.5 to + 7.0V
Supply Voltage (Ved
DC Input or Output Voltage
(V'N, Your)
Operating Temp. Range (TAl
MM74HC
MM54HC
Input Rise or Fall Times
(tr, tt)
Vee=2.0V
Vee=4.5V
Vee=6.0V
-1.5toVce+ 1.5V
-0.5 to Vee + 0.5V
±20mA
±25mA
±50mA
- 65·C to + 150·C
500mW
260"C
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
·C
·C
1000
SOO
400
ns
ns
ns
DC Electrical Characteristics (Note'4)
Symbol
Parameter
Conditions
TA=2S·C
Vee
Typ
V,H
V,L
VOH
2.0V
4.5V
6.0V
,3.15
Maximum Low Level Input
Voltage
2.0V
4.5V
6.0V
Y,N = V,H or V,L
Ilourl';;20 p.A
V,N = V,H or V,L
Ilourl';;4.0 mA
Ilourl';;5.2 mA
VOL
Maximum Low Level Output
Voltage
V,N = V,H or V,L
Ilourl';;20 p.A
54HC
TA= -55 to 125"C
Units
Guaranteed Limits
Minimum High Level Input
Voltage
Minimum High Level Output
Voltage
74HC
TA= -40 to 85·C
1.5
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
,
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
2.0V
4.SV
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2 3.98
5.7 ·5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
Y,N = V,H or V,L
Iiourl ';;4.0 mA
Iiourl,;; 5.2 mA
4.5V
6.0V
0.2
0.2
.26
.26
0.33
0.33
0.4
0.4
V
V
V'N=VeeorGND
6.0V
±0.1
±1.0
±1.0
p.A
"
liN
Maximum Input Current
8.0
80
160
p.A
Maximum Quiescent Supply V,N=VeeorGND 6.0V
Current
lour=Op.A
Note 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified aU vollages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic ,uN" package: -12 mWI'C from 6S'C to 85'C; ceramic uJ" package: -12 mW/'C from 100'C to 125'C.
Note 4: For a power supply of 5V ± 10% the worst case output vollages (VOH. and VOl) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case V,H and V,L occur at Vee = S.SV and 4.SV respectively. (The V,H value at S.SV Is 3.8SV.) The worst case leakage current (liN.
IcC. and lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
Icc
,
3·370
AC Electrical Characteristics Vee = 5V, TA = 25°C, CL = 15 pF, tr= tf= 6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
50
30
MHz
17
35
ns
fMAX
Maximum Operating Frequency
tpHL, tpLH
Maximum Propagation
Delay Clock to Q
tpHL
Maximum Propagation
Delay Reset to any Q
16
40
ns
tREM
Minimum Reset
Removal Time
10
20
ns
tw
Minimum pulse Width
10
16
ns
(Note 5)
AC Electrical Characteristics Vee = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25°C
Vee
74HC
TA= -40 to 85°C
Typ
fMAX
Maximum Operating
Frequency
tpHL, tpLH
Maximum Propagation
Delay Clock to Q1
54HC
TA= -55to 125°C
Units
Guaranteed Limits
2.0V
4.5V
6.0V
10
40
50
6
30
35
5
24
28
4
20
24
MHz
MHz
MHz
~.OV
4.5V
6.0V
80
21
18
210
42
36
265
53
45
313
63
53
ns
ns
ns
TpHL, tpLH
Maximum Propagation
Delay Between Stages
from Q n to Q n + 1
2.0V
4.5V
6.0V
80
18
15
125
25
21
156
31
26
188
38
31
ns
ns
ns
tpHL
Maximum Propagation
Delay Reset to Q
('4024 only)
2.0V
4.5V
6.0V
80
21
18
210
42
36
265
53
45
313
63
53
ns
ns
ns
tpHL
Maximum Propagation
Delay Reset to any Q
('4020 and '4040)
2.0V
4.5V
6.0V
72
24
20
240
48
41
302
60
51
358
72
61
ns
ns
ns
tREM
Minimum Reset
Removal Time
2.0V
4.5V
6.0V
100
20
16
126
25
21
149
50
25
ns
ns
ns
tw
Minimum Pulse Width
2.0V
4.5V
6.0V·
90
16
14 '
100
20
18
120
24
20
ns
ns
ns
trLH, tTHL
Maximum
Output Rise
and Fall Time
2.0V
4.5V
6.0V
95
19
16
110
22
19
ns
ns
ns
.lr, tf
Maximum Input Rise and
Fall Time
1000
500
400
1000
500
400
ns
ns
ns
..
CPO
CIN
. Power Dissipation
Capacitance (Note 6)
Maximum Input
Capacitance
30
10
9
75
15
13
1000
500
400
(per package)
1
pF
55
5
10
10
10
. Note 5: Typical Propagation delay time to any output can be calculated using: tp = t7+ 12(N-l) ns; where N is the number of the output,
pF
Cw, at Vee=5V.
Not. 6: CPO determines the no load dynamic power consumption, Po = cpo Vec2 f+ lee vee, and the no load dynamic current consumption, Is = Cpo Vee f+ lee.
3·371
Logic Diagrams
MM54HC4020/MM74HC4020
014
013
012
011 "
09
010
Q8
TUF/5216-S
MM54HC4024/MM74HC4024
CLOCK
RESET
02
01
03
, D6
05
04
07
TL/F/S216-6
MM54HC4040/MM74HC4040
012
01
02
03
04
05
all
010
os
OB
07
06
TUF/5216-7
3-372
Timing Diagram
3-373
m
..".
~
r---------------------------------------------------------------~
.
:J:
~ Semiconductor
....
:::E
o
~National
PRE;LIMINARY
\'--__
----,../J
..".
microCMOS
:::E
.....
m MM54HC4046/MM74HC4046
..".
~
o
CMOS Phase Lock Loop
:J:
:; 'Gene.ral Description
:::E
:::E
The MM54HC4046/MM74HC4046 is a low power phase
lock loop utilizing 3.5p. silicon-gate p-well microCMOS technology to obtain high frequency operation both in the phase
comparator and VCO sections. This device contains a low
power linear voltage controlled oscillator (VCO), a source
follower, and three phase comparators. The three phase
comparators have a common signal input and a common
comparator input. The signal input has a self biasing amplifier allowing signals to be either capacitively coupled to the
phase comparators with a small signal or directly coupled
with standard input logic levels. This device is similar to the
CD4046 except that the Zener diode of the metal gate
CMOS device has been replaced with a third phase comparator.
Phase Comparator I is an exclusive OR (XOR) gate. It provides a digital error signal that maintains a 90 phase shift
between the VCO's center frequency and the input signal
(50% duty cycle input waveforms. This phase detector is
more susceptible to locking onto harmonics of the input frequency than phase comparator I, but provides better noise
rejection.
between them. This comparator is more susceptible to
noise throwing the loop out of lock, but is less likely to lock
onto harmonics than the other two comparators.
In a typical application all three comparators feed an external filter network which in turn feeds the VCO input. This
input is a very high impedance CMOS input which also
drives the source follower. The VCO's operating frequency
is set by three external components connected to the Cl A,
Cl B, Rl and R2 pins. An inhibit pin is provided to disable
the VCO and the source follower, providing' a method of
putting the IC in a low power state.
The source follower is a MOS transistor whose gate is connected to the VCO input and whose drain connects the Demodulator outpUt. This output normally is used by tying a
resistor from pin 10 to ground, and provides a means of
looking at the VCO input without loading down modifying the
characteristics of the PLL filter.
Features
(VCC=4.5V)
• Low dynamic power consumption:
20 MHz
• Maximum VCO operating frequency:
(Vcc=4.5V)
.
• Fast comparator response time (Vcc=4.5V)
Comparator I:
. 20 ns
Comparator II:
25 ns
20 ns,
Comparator III:
• VCO has high linearity and high temperature stability
Phase comparator III is an SR flip-flop gate. It can be used
to provide the phase comparator functions and is similar to
the first comparator in performance.
Phase comparator II is an edge sensitive digital sequential
network. Two signal outputs are provided; a comparator output and a phase pulse output. The comparator output is a
TRI-STATEc~t>_~
(15) PHASE COMPARATOR
FROM INPUT
(FIGURE 3)
III OUTPUT
®
FROM INPUT CIRCUIT
(FIGURE 3) ----I....."
TL/F/5352-11
FIGURE 8. Phase Comparator III Logic Diagram
nL______.n
. . _____
SIGNALIN~....._ _ _ _ _....
n
n
COMPARATOR IN_ _ _ _......_ _ _ _ _ _....
rL
10_ _ _ _ _ _..1.
COMPARATOR III
OUT
¥CO IN
TL/F/5352-12
FIGURE 9. Typical Waveforms for Phase Comparator III
3-381
....r
I::~~ ~~C~~~
o
------r"""
(131 PHASE COMPARATOR II
OUTPUT
(11 PHASE PULSES
OUTPUT
FRO~::U~~I~~~~ - - - - - - L - . J
(8)
TUF15352-14
FiGURE 6. Logic Diagram for Phase Comparator II
SIGNALIN
..Il___.....n. ._ . . . n
. . .___
COMPARATOR
IN
COMPARATOR II
OUT
_Il. ____ .........~'-----_- __ --
VCOIN
_J
PHASE
PULSES
-U
"'---~--------------
u
FIGURE 7. Typical Phase Comparator II Output Waveforms
3-382
TUF15352-13
J?A National
~ Semiconductor
J---'
\
)
microCMOS
MM54HC4049/MM74HC4049
Hex Inverting Logic Level Down Converter
MM54HC4050/MM74HC4050
Hex Logic Level Down Converter
General Description
The MM54HC4049/MM74HC4049 and the MM54HC40501
MM74HC4050 utilize microCMOS Technology, 3.5 micron.
silicon gate P-well CMOS, and have a modified input protection structure that enables these parts to be used as logic
level translators which will convert high level logic to a low
level. logic while operating from the low logic supply. For
example, 0-15V CMOS logic can be converted to 0-5V
logic when using a 5V supply. The modified input protection
has no diode connected to Vee, thus allowing the input volt. age to exceed the supply. The lower zener diode protects
the input from both positive and negative static voltages. In
addition each part can be used as a simple buffer or inverter
without level translation. The MM54HC4049/MM74HC4049
is pin and functionally compatible to the CD4049BMI
CD4049BC and the MM54HC4050/MM74HC4050 is compatible to the CD4050BM/CD4050BC
Features
•
•
•
•
Typical propagation delay: 8 ns
Wide power supply range: 2V-6V
Low 9uiescent supply current: 20 p.A maximum (74HC)
Fanout of 10 LS-TIL loads
Connection Diagrams
Dual-In-Line Package
NC
16
L=r:
15
NC
14
K =E
13
12
Dual-In-Line Package
J=
E
11
0
o
-NC
16
10
L=F
15
F
NC
14
K =E
13
12
E
11
J=0
o
10
. 1
vcc
G =A
A
H=B
I =C
GNO
VOD
G= A
A
TOP VIEW
H=B
I =C
C
GND
TOP VIEW
TLlF/5214-1
Order Number MM54HC4049J, MM54HC4050J,
MM74HC4049J,N or MM74HC4050J,N
See NS Package J16A or NI6E'
3-383
TLlF/5214-2
Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage (Vcc)
-0.5 to +7.0V
DC Input Voltage (VIN)
-1.5 to + 18V
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
-20mA
Clamp Diode Current (IZK. 10K>
DC Output Current. per pin (lOUT)
±25mA
±50mA
DC Vee or GND Current. per pin (Icc)
Storage Temp. Range (TSTG)
- 65'C to + 150"C
Power Dissipation (Po) (Note 3)
500mW
Lead Temp. (TU (Soldering 10 seconds)
260'C
Operating Conditions
Supply Voltage (Vee>
Min
2
6
Units
V
15
V
Max
DC Input Voltage
0
(VIN)
DC Output Voltage
0
(VOUT)
Operating Temp. Range (TAl
-40
MM74HC
-55
MM54HC
Vcc
V
+85
+125
'c
'c
Input Rise or Fall Times
(tr. tf) Vee=2.0V
Vcc=4.5V
Vcc=6.0V
1000
500
400
ns
ns
ns
. DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25'C
Typ
74HC
54HC
TA= -4O"C to 85"C TA=-55"Cto 125'C Units
Guaranteed Limits
VIH
Minimum High Level Input
Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level Input
Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
-
VIN = VIH or VIL
IIOUTI:S;20 ",A
VIN = VIH or VII:
l1oUTI:S;4.0 mA
IIOUTI:S;5.2 mA
VOL'
Maximum Low Level
Output Voltage
VIN = VIH or VIL
IIOUTI :s; 20 ",A
VIN = VIH or VIL
IloUTI:S;4mA
l10UTI :s; 5.2 mA
liN
Maximum Input Current
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1.
0.1
0.1
0.1
0.1
0.1
V
V
V
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
±0.1
±0:5
±1.0
±5
±1.0
±5
p.A
p.A
VIN=VeeorGND 60V
6.0V
VIN=15V
Maximum Quiescent Supply VIN=VccorGND 6.0V
40
2.0
20
",A
Current
IOUT=O",A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all wltages are referenoed to ground.
Note 3: Power Dissipation temperature derating - plastic "'N"' package: -12 mWrC from 6S'C to 85"C; ceramic "'J'" package: -12 mW/'C from 100"C to 125"C.
Note 4: For a power supply of SV ± 10% the worst case output voltages (VOH and YOU occur for HC at 4.5V. Thus the 4.5V values should be used when
deSigning with this supply. Worst case VIH and VIL occur at Voo= 5.5V and 4.SV respectIVely. (fhe VIH value at 5.5V Is 3.85V.) The worst case leakage current (liN.
Ice. lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
ICC
3-384
AC Electrical Characteristics Vee=5V. TA=25·C. CL =15pF. t r =tf=6ns
Symbol
Parameter
tpHL. tpLH
Maximum Propagation Delay
Conditions
Typ
Guaranteed
Limit
Units
8
15
ns
AC Electrical Characteristics Vee = 2.0V 10 6.0V. CL = 50 pF. Ir= If= 6 ns (unless otherwise specffied)
Symbol
Parameter
Conditions
Vee
TA=25·C
Typ
tpHL. tpLH
tTHL. tTLH
2.0V
4.5V
6.OV
30
10
9
85
Maximum Output
Rise and Fall
Time
2.0V
4.5V
6.OV
25
CPO
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input
Capacitance
(per gate)
6
54HC
TA= -55· to 125·C
15
100
20
18
130
26
22
ns
ns
ns
75
15
13
95
19
16
110
22
19
ns
ns
ns
17
-
25
5
Units
Guaranteed Limits
Maximum Propagation
Delay
7
74HC
TA = -40· to 85·C
pF
10
10
10
pF
Note 5: CPO determines the no load dynamic power consumption, Po = Cpo vcc2 f + lee Vee, and the no load dynamic current consumpllon, Is = Cpo Vee f + Icc.
,
3-385
~
...
........
~
,----------------------------------------------------------------------------,
PRELIMINARY
o ~National
:r:
~ Semiconductor
-
"'--1
\'-------'/
microCMOS
:::E
:::E
.....
MM54HC4051/MM74HC4051
.~
a-Channel Analog Multiplexer
o
:r: MM54HC4052/MM74HC4052
10
:::& Dual 4-Channel Analog Multiplexer
:::&
~ MM54HC4053/MM74HC4053
10
o Triple 2-Channel Analog Multiplexer
~
10
...
...
........ . General Description
o
:r:
:::E
:::&.
~
10
~
o
:r:
...
10
:::&
:i!
.....
....
10
~
o
:r:
........
:::&
:::&
.....
....
...
o
10
o
:r:
;OX
:::&
:::E
These multiplexers are digitally controlled analog switches
a pair of 4-channel multiplexers. The binary code placed on
implemented in microCMOS Technology, 3.5 micron silicon
the A, and B select lines determine which switch in each 4
channel section is "on", connecting one of the four inputs in
gate P-well CMOS. These switches have low "on" resistance and low "off" leakages. They are bidirectional
each section to its common output. This enables the impleswitches, thus any analog input may be used as an output
mentation of a 4-channel differential multiplexer.
and vice-versa. Also these switches contain lin!larization cirMM54HC4053/MM74HC4053: This device contains 6
cuitry which lowers the on resistance and increases switch " switches whose outputs are connected together in pairs,
linearity. These devices allow control of up to ±6V (peak)
thus implementing a triple 2 channel multiplexer, or the
analog signals with digital control signals of 0 to 6V. Three
equivalent of 3 single-pole-double throw configurations.
supply pins are provided for Vee, ground, and VEE. This
Each of the "A, B, or C select lines independently controls
enables the connection of 0-5V logic signals when
one pair of switches, selecting one of the two switches to be
Vcc=5V and an analog input range of ±5V when
"on".
VEE = 5V. All three devices also have an· inhibit control
which when high will disable all switches to their off state.
All analog inputs and outputs and digital inputs are protected from electrostatic damage by diodes to Vee and ground.
• Wide analog input voltage range: ± 6V
• Low "on" resistance: 50 typo (VCC-VEE=4.5V)
MM54HC4051/MM74HC4051: This device connects together the outputs of 8 switches, thus achieving an 8 chan30 typo (VCC-VEE=9V)
nel Multiplexer. The binary code placed on the A, B, and C
• Logic level translation to enable 5V logic with ± 5V
select lines determines which one of the eight switches is
analog Signals
"on", and connects one of the eight inputs to the common
• Low quiescent current: 80 p.A maximum (74HC)
output.
• Matched Switch characteristic
MM54HC4052/MM74HC4052: This device, connects together the outputs of 4 switches in two sets, thus achieving
Features
Connection Diagrams
Dual-In-Llne Packages
IN/OUT
7i.Y75:
10
1
5
Y4
VI GUinN.!!......!!
IN/OUT
INiiiiiT
INH
VEE
TL/F/5353-1
Top View
TLlF/5353-3
TL/F/5353-2
Top View
Order Number MM54HC4051J, MM54HC4052J, MM54HC4053J,
MM74HC4051J, N, MM74HC4052J, N or MM74HC4053J, N
See NS Package J16A or N16E
3-386
Top View
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
Supply Voltage (Vee)
Min
2
Supply Voltage {Vcel
Supply Voltage (VEE)
0
DC Input or Output Voltage
0
(VIN, VOUT)
Operating Temp. Range (TAl
-40
MM74HC
-55
MM54HC
Input Rise or Fall Times
Vcc=2.0V
(tr,tll
Vcc=4.5V
Vcc=6.0V
-0.5 to + 7.5V
+0.5to -7.5V
Supply Volta~e (VEE)
Control Input Voltage (VIN)
-1.5toVee+ 1.5V
Switch 1/0 Voltage (Via)
VEE-0.5 to Vee+0.5V
±20mA
Clamp Diode Current (I.IK' 10K)
±25mA
Output Current, per pin (lOUT)
±50mA
Vcc or GND Current, per pin (Icel
Storage Temperature Range (T8TG)
-65'Cto + 150'C
500mW
Power Dissipation (Po) (Note 3)
Lead Temp. (TLl (Soldering 10 seconds)
260'C
i!i:
iii:
en
Max
6
-6
Vcc
Units
V
V
V
-1:10
:r:
o
-1:10
o
en
.....
.....
i!i:
i!i:
.....
-1:10
+85
+125
'C
'C
:r:
1000
500
400
ns
ns
ns
.....
.....
o
-1:10
o
en
:s::::
i!i:
DC Electrical Characteristics (Note 4)
en
-1:10
Symbol
Conditions
Parameter
VEE
T =25'C
74HC
54HC
TA= -40 to 85'C TA= -55 to 125'C Units
Vee A
Typ
VIH
VIL
RON
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
200
100
90
250
125
112
300
150
135
100 230
40 110
20 90
15 80
290
138
110
100
350
165
135
120
15
10
10
20
15
15
20
15
15
n
n
n
n
n
n
n
n
n
n
±0.1
±'1.0
±1.0
p.A
±60
±100
±600
±1000
±600
±1000
nA
nA
Maximum "ON" Resistance
(See Note 5)
VCTL =VIH, 18=1.0 mA GND 4.5V 40
-4.5V 4.5V 30
VIS = Vcc to VEE
(Figure 1)
-6.0V 6.0V 20
Maximum "ON"Resistance
Matching
VCTL =VIH
Vls=VcctoGND
liN
Maximum Control
Input Current
VIN = Vcc or GND
Vee=2-6V
112
Maximum Switch "OFF"
Leakage Current
(Switch Input)
Vas = Vee or GND
Vls=GNDorVcc
VINH"; VIH (Figure 2)
112
Maximum Switch
"ON" Leakage·
Current
2.0V
4.5V
4.5V
6.0V
GND 4.5V 10
-4.5V 4.5V 5
-6.0V 6.0V 5
GND 6.0V
-6.0V 6.0V
Vos=VccorGND
HC4051 VINH=VIL
(Figure 3)
GND 6.0V
-6.0V 6.0V
p.A
p.A
VOs=VccorGND
HC4052 VINH=VIL'
(Figure 3)
GND 6.0V
-6.0V 6.0V
p.A
p.A
GND 6.0V
p.A
VOs=VccorGND
HC4053 VINH=VIL
-6.0V 6.0V
p.A
(Figure 3)
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3i Power Dissipation temperature derating - plastic "N" package: -12 mW/'C from 65'C to B5'C; ceramic "J" package: -12 mWI'C from 1OO'C to 12S'C.
Note 4: For a power supply of SV ± 10% the worst case on resistances (RON) occurs for HC at 4.SV. Thus the 4.SV values should be used when designing with
this supply. Worst case VIH and VIL occur at Vee= S.SV and 4.SV respectively. (The VIH value at S.SV is 3.BSV.) The worst case leakage current occur for CMOS at
the higher voltage·and so the S.SV values should be used.
Note 5: At supply voltages (Vee-VES approaching 2V the analog switch on resistance becomes extremely non·linear. Therefore it is recommended that these
devices be used to transmit digital only when using these supply voltages.
3-387
o
~
en
.....
N
Minimum High Level
Input Voltage
GND
VCTL =VIH, Is=1.0 mA GND
-4.5V
VIS=VCC or VEE
-6.0V
(Figure 1)
RON
Guaranteed Limits
:r:
iii:
iii:
.....
-1:10
:r:
o
-1:10
o
en
N
.....
i!i:
iii:
en
-1:10
:r:
o
-1:10
o
en
Co)
.....
iii:
iii:
.....
-1:10
:r:
o
~
en
Co)
DC Electrical Characteristics (Note 4) (Continued)
Symbol
Parameter
T~=2SoC
Conditions
VEE
Vee
Typ
liZ
Icc
Maximum Switch
"OFF" Leakage
Current (Common
Pin)
74HC
S4HC
TA= -40 to 8SoC TA= -SSto 12SoC Units
Guaranteed Limits
Vos=VccorGND GND 6.0V
HC4051 Vls=GNDorVcc -6.0V 6.0V
VINH=VIH
pA
pA
Vos=VccorGND GND 6.0V
HC4052 Vls=GNDorVcc -6.0V 6.0V
VINH=VIH
p.A
p.A
Vos=VccorGND GND 6.0V
HC4053 Vls=GNDorVcc -6.0V 6.0V
VINH=VIH
p.A
p.A
Maximum Quiescent
Supply Current
VIN=VccorGND
IOUT=O p.A
,8
16
GND 6.6v
-6.0V 6.0V
80
160
160
320
p.A
p.A
AC Electrical Characteristics Vcc=2.0V-6.0V Vee=OV-6V. CL =50 pF (unless otherwise specified)
Symbol
Parameter
,Conditions
TA=2SoC
VEE
Vee
74HC
S4HC
TA= -40 to 8S"C TA=-SSt012SoC
Typ
tpHL. tpLH
Maximum Propagation
Delay Switch In to
Out
tPZL. tPZH
Maximum Switch Tum
"aNn Delay
tpHZ. tpLZ
fMAX
Units
Guaranteed Limits
GND
GND
-4.5V
-6.0V
2.0V
4.5V
4.5V
6.0V
25
5
4
3
GND
GND
-4.5V
-6.0V
2.0V
4.5V
4.5V
6.0V
92
18
16
15
ns
ns
ns
ns
Maximum Switch Turn
"OFFnDelay
GND
GND
-4.5V
-6.0V
2.0V
4.5V
4.5V
6.0V
65
28
18
16
ns
ns
ns
Minimum Switch
Frequency Response
20 log (WVo)=3 dB
GND 4.5V
-4.5V 4.5V
30
35
MHz
MHz
(Figure 7)
-4.5V 4.5V
180
mVp.p
Cross Talk Between
(Figure 8)
any Two Switches
(Frequency at - 50 dB)
-4.5V 4.5V
Cross Talk Control
to Switch
Feed Through. Switch
Input to Output
CIN
Maximum Control
Input Capacitance
CII'!
Maximum Switch
Input Capacitance
CIN
Maximum Feedthrough
Capacitance
RL=1 kO
50
10
8
7
75
15
14
13
ns
ns
ns
ns
MHz
..
F=5MHz
F=10MHz
5
Input
4051 Common
4052 Common
4053 Common
62
13
12
11
-
10
dB
dB
10
pF
10
15
90
45
30
pF
5
pF
..
3·388
Truth Tables
'4051
'4052
uON"
Input
Inputs
Channel
Inh
C
B
A
H
X
X
X
None
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H.
L
H
L
H
L
YO
Y1
Y2
Y3
Y4
Y5
Y6
H
L
H
Inh
H
L
L
L
L
B
H
H
Input
"ON" Channels
A
X X
L
L
'4053
L
H
L
H
X
y
None
None
OX
1X
2X
3X
OY
1Y
2Y
3Y
"ON" Channels
Inh C B A
H
L
L
L
L
L
L
L
L
Y7
X X X
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
b
C
a
None None None
CX
CX
CX
CX
CY
CY
CY
CY
BX
BX
BY
BY
BX
BX
BY
BY
AX
AY
AY
AY
AY
AY
AY
AY
AC Test Circuits and Switching T',f1le Waveforms
Vee
Ven=VIH _ _ _...,
IIntanal)
Ven =vl1 _ _ _--,
11l1li1111)
TEST
SWITCH
VIS--.....-iV
0/11-....- - Vas
CONTROL
AMMETER
VEE
y
Vee
TEST
SWITCH
t----
Vos a Vee OR GNO
VEE
TL/F/5353-5
TL/F/5353-4
. FIGURE 1. "ON" Resistance
FIGURE 2. "OFF" Channei Leakage Current
Vos (OPEN)
TL/F/5363-6
FIGURE 3. "ON" Channel Leakage Current
Vee
Vee---+-:r.~-""IIl
VIS
y
OV-~..Jrr
I-+----VOI
va.
VOO'-----+,.--...
ov----'
TLlF/5353-7
FIGURE 4. tpHL. tPLH Propagation Delay Time Signal Input to Signal Output
3-389
~ r---------------------------------------------------------------------------------~
II)
o
'Ot'
o
AC Test Circuits and Switching Time Waveforms
(Continued)'
:::E:
t!
:iii
:iii
~
II)
IpLZ
Vee:
VCC~'PZL
IpLZ
Y.,'y
50%
o
OV~PZL
I-+-VOI
(5
:::E:
VOO
II)
VOL
W
.
VDO
90%
.
'Ot'
:iii
:iii
.....
10%
VOL
TL/F/5353-8
FIGURE 5. tPZL. tpLZ Propagation Delay Time Control to Signal Output
C'I
II)
o
'Ot'
o
IpZH
VeTL
:::E:
IpHZ
vee~
50%
t!
:iii
:iii
OV~.
tnH
1-+---.-V05
.....
C'I
VOH
o
OV
II)
10%
Vee
~ 50%
.
~~
v::~r::,.
~
OV
VOD
.
'Ot'
o
TL/F/5353-9
:::E:
FIGURE 6. tPZH. tpHZ Propagation Delay Time Control to Signal Output
'Ot'
II)
:iii
:iii
......
....
VCTL----.,
1,=6 ••
V------+-~
II)
o'Ot'
Vee
o
t!
==
:iii
......
VEE
RIN
600n .
....
~
o
--~
Ve
OV---~
10F4
IN/OUTSWITCHESOUTIIN I--t'---~""-VDS
:::E:
__
J
CL
50
PF
Vos.
-~'Y;:----IF
+
CROSSTALK
t
TLlF/5353-10
FIGURE 7. Crosstalk: Control Input to Signal Output
:::E:
'Ot'
II)
VCTL(1I''' Vce ...·~.--.,
==
:iii
600!!
t-+-VOS(I}
VIS(l}
VCTl(21- 0V - - - _
11-....-VOS(2}
:&Oll
TL/F/5353-11
FIGURE 8. Crosstalk Between Any Two Switches
3·390
i:
i:
en
Logic Diagrams
"'0%"
MM54HC4051/MM74HC4051
CHANNEL IN/OUT
"'en"
I
Vee
V1
V&
V5
Y3
V4
Y2
0
....
......
YO
VI
i:
i:
.......
"'0%"
BINARY
TO
10F8
DECODER
WITH
INHI81T
LOGIC
LEVEL
CONVERSION
"'en"
....
......
0
COMMON
OUTIIN
i:
i:
en
"'%"
INH
0
"'en"
0
III)
6ND
......
VEE
TL/F/5353-19
MM54HC4052/MM74HC4052
"'%"
X CHANNELS IN/OUT
I
X3
lIZ
XI
xu
i:
i:
.......
\
0
"'en"
0
III)
......
Vee
i:
i:
en
A
BINARY
TO
10F4
DECODER
WITH
INHIBIT
LOGIC
LEVEL
CONVERSION
"'0%"
"'en0 "
COMMON Y
oUTIIN
Co)
......
i:
i:
.......
"'%"
"'en"
0
YO
6ND
rt
YZ
0
Y3
YCHANNELS INloUT
VEE
TL/F/5353-20
MM54HC4053/MM74HC4053
LOGIC
LEVEL
CONVERSION
~
,
V"
IN/OUT
I
CY
ex
BY
, BX
\
AY
AX
INH
TL/F/5353-21
3·391
Co)
Typical Performance Characteristics
90
Q
TypIcal "On" ResIstance
vslnput Voltage
II
75
i-'
w
.. 60
~.
...fa 45
~ 30
15
-6
VCCi4.~v
~
,;
.
II
f-!- ... ~ ~i9.0V
~
io-'
-4· -2
Vrrr ....
0
2
4
INPUT VOLTAGE (VOLTS)
Vee
= -Vee
3-392
TL/F/5353-18
~National
~ Semiconductor
microCMOS
MM54HC4060/MM74HC4060
14 Stage Binary Counter
General Description
The MM54HC4060/MM74HC4060 is a high speed, binary
ripple carry counter. These counters are implemented utilizing microCMOS Technology, 3.5 micron silicon gate P-well
CMOS, to achieve speed performance similar to LS-TTL
logic while retaining the low power and high noise immunity
of CMOS.
The 'HC4060 is a 14-stage counter, which device increments on the falling edge (negative transition) of the input
clock, and all their outputs are reset to a low level by applying a logical high on their reset input. The 'HC4060 also has
two additional inputs to enable easy connection of either an
RC or crystal oscillator:
This device is pin equivalent to the CD4060. All inputs are
protected from damage due to static discharge by protection diodes to Vee and ground.
Features
•
•
•
•
•
Typical propagation delay: 16 ns
Wide operating voltage range: 2-6V
Low input current: 1 IJ-A maximum
Low quiescent current: 80 IJ-A maximum (74 Series)
Output drive capability: 10 LS-TTL loads
Connection and Logic Diagrams
Dual-In-Line Package
Vee
010
15
116
aB
14
09
RESET
13
12
CLOCK CLOCK 1 CLOCK 2
11
10
9
r--
1
2
3
012
013
014
4
06
5
05
6
07
7
04
IB
GNO
TL/F/5354-1
Top View
Order Number MM54HC4060J or MM74HC4060J, N
See NS Package J16A or N16E
013
012
01D
,3-393
09
os
07
TUF/5354-2
Absolute Maximum Ratings
Operating Conditions
Supply Voltage (Vecl
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (leo)
DC Output Current. per pin (lOUT)
DC Vcc or GND Current. per pin (lee)
Storage Temperature Range (T8TG)
Power Dissipation (Po) (Note 3)
Lead Temperature (TLl
(Soldering 10 seconds)
Supply Voltage (Vee)
DC Input or butput Voltage
(VIN. VOUT)
Operating Temp. Range (TAl
MM74HCT
MM54HCT
Input Rise or Fall Times
Vee=2.0V
(tr• til
Vee=4.5V
Vee=6.0V
(Notes 1 & 2)
-0.5 to +7.0V
-1.5 to Vee + 1.5V
-0.5 to Vee+0.5V
±20mA
±25mA
±50mA
- 65·C to + 150·C
500mW
2600C
DC Electrical Characteristics
Symbol
Parameter
Min
2
0
Max
6
Units
V
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
Vee
..
(Note 4)
Conditions
Vee
TA=25·C
Typ
74HC
54HC
TA= -40 to 85"C TA= -55 to 125·C Units
Guaranteed Limits
VIH
Minimum High Level
Voltage
2.0V
4.5V
6.0V
1.5
3.. 15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level Input
Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level Output
Voltage
1.9
4.4
5.9
V
V
V
VIN = VIH or VIL
1i6uTI~20 p.A
Except Pins VIN=VIH orVIL
11 & 12
IiOUTI ~4.0 mA
IIOUTI~5.2 mA
Pins 11 &
12
VOL
Maximum Low Level Output
Voltage
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.98
5.48
VIN=VIH orVIL
IiOUTI = 0.4 rnA
IIOUTI = 0.52 mA
VIN = VIH or VIL
IIOUTI~20 p.A
3.r
5.2
V
V
3.84
5.34
3.7
5.2
V
V
0.1
0.1
0.1
V
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN = VIH or VIL
IiOUTI = 0.4 mA
Ilourl=0.52 mA
0.26
0.26
0.33
0.33
0.4
0.4
V
V
Except Pins VIN = VIH or VIL
11 & 12
IIOUTI~4.0 mA
IIOUTI~5.2 mA
Pins 11 &
12
2.0V
4.5V
6.0V
.)
liN
Maximum Input Current
VIN=VCC or GND 6.0V
±0.1
±1.0
±1.0
p.A
Icc
Maximum Quiescent Supply
Current
VIN=VCcorGND
6.0V.
IOUT=Op.A
8.0
80
160
p.A
. Note 1: Maximum Ratings are those values beyond which damag\l to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating: plastic "N" package: -12 mW/'C from 6S'C to 8S'C ceramic "J" package: -12 mWrC from 100'C to 12SOC
Note 4: For a power supply 01 sv ± 10% the worst case output voltages (YOH. and VOU occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at Vee = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current
(liN. lee. and loz) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3·394
AC Electrical Characteristics
Vcc=5V, TA=25"C, CL =15 pF, t r =tf=6 ns
Parameter
Symbol
Typ
Conditions
fMAX
Maximum Clock Frequency
tpHL, tpLH
Maximum Propagation
DeiaytoQ4'
tpHL, tpLH
Guaranteed
Limit
Units
30
MHz
40
20
ns
Maximum Propagation
Delay to any Q
16
40
ns
tREM
Minimum Reset
Removal Time
10
20
ns
tw
Minimum Pulse Width
10
1-6
ns
(Note 5)
AC Electrical Characteristics Vcc=2.0V to 6.0V, CL=50 pF, tr =tf=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25'C
Vee
Typ
fMAX
Maximum Operating
Frequency
2.0V
4.5VO
6.0V
tpHL, tpLH
Maximum Propagation
Delay Clock to Q4
2.0V
4.5V
6.0V
tpHL
Maximum Propagation
Delay Reset to ani Q
2.0V
4.5V
6.0V
tpHL, tpLH
Maximum Propagation
Delay Between Stages
Qn toQ n+l
TA74HC
TA= -40 to 85'C
TA54HC
TA= -55to 125'C
Units
Guaranteed Limits
6
30
35
5
24
28
4
20
24
MHz
MHz
MHz
120
42
35
300
60
47
375
75
59
450
90
62
ns
ns
ns
72
24
20
240
48
41
302
60
51
358
72
61
ns
ns
ns
2.0V
4.5V
6.0V
125
25
21
156
31
26
188
38
31
ns
ns
ns
tREM
Mimimum Reset
Removal Time
2.0V
4.5V
6.0V
100
20
17
125
25
21
150
30
25
ns
ns
ns
tw
Mimimum Pulse Width
2.0V
4.5V
6.0V
80
16
14
100
20
17
120
24
20
ns
ns
ns
Ir,lf
Maximum Inpul Rise and
Fall Time
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
trHL, trLH
Maximum Outpul Rise
and Fall Time
2.0V
4.5V
6.0V
75
15
13
95
19
16
110
22
19
ns
ns
ns
CPO
Power Dissipation
Capacilance (Nole 6)
CIN
Maximum Inpul
capacilance
(per package)
30
10
9
pF
55
5
10
10
10
pF
r
Note 5: Typical Propagation delay time to any output can be calculated using: tp 17+ 12(N-l) ns; where N is the number of the output, Ow, at Vee=5V.
Note 6: CPO determines U.e no load dynamic powe, consumption, Po = Cpo Vcr:?- f+ Icc Vce, and the no load dynamic current consumption,
Is = CPO Vee f + Icc-
3·395
Kt;is
fa cr
cj
CI:
......
cr
CI
~
a
...............
cr
CII
CII
CII
cr
C;
-N
c;
0
..
-
c;
C;
'
3-396
~National
---
~ Semiconductor
\
J
microCMOS
MM54HC4066/MM74HC4066
Quad Analog Switch
General Description
Features
These devices are digitally controlled analog switches utilizing microCMOS Technology, 3.5 micron silicon gate P-well
CMOS. These switches have low "on" resistance and low
"off" leakages. They are bidirectional switches, thus any
analog input may be used as an output and visa-versa. Also
the' 4066 switches contain linearization circuitry which lowers the "on" resistance and increases switch linearity. The
'4066 devices allow control of up to 12V (peak) analog signals with digital control signals of the same range. Each
switch has its own control input which disables each switch
when low. All analog inputs and outputs and digital inputs
are protected from electrostatic damage by diodes to Vee
and ground.
•
•
•
•
•
•
Connection Diagram
Truth Table
Typical switch enable time: 15 ns
Wide analog input voltage range: 0-12V
Low "on" resistance: 30 typo ('4066)
Low quiescent current: 80 p,A maximum (74HC)
Matched switch characteristics
Individual switch controls
Dual-In-llne Package
Vcc
1110
1CTL
1011
4CTI.
20/1
41/0
2110
4011
2CTL
3011
3CTL
JItO
Input
Switch
Cll
1/0-0/1
L
H
"OFF"
"ON"
GND
TL/F/5355-1
Top View
Order Number MM54HC4066J or MM74HC4066J, N
See NS Package J14A or N14A
Schematic Diagram
011
CONTROL
TL/F/5355-2
3-397
Absolute Maxi'mum Ratings (Notes 1 & 2)
-0,5 to +15V
Supply Voltage (Vee>
DC Control Input Voltage (V,N)
-1.5 to Vcc+ 1.5V
DC Switch I/O Voltage (V,O)
VEE-0.5 to Vcc+0.5V
±20mA
Clamp Diode Current (1,K, 10K)
DC Output Current, per pin (lOUT)
±25mA
DC Vcc or GND Current, per pin (Ieel
±50mA
- 65·C to + 150·C
Storage Temperature Range (TSTG)
500mW
Power Dissipation (PD) (Note 3)
Lead Temperature (TL.l
(Soldering 10 seconds)
260·C
Operating Conditions
Supply. Voltage (VCO)
DC Input or Output Voltage
(V'N, VOUT)
Operating Temp. Range (TAl
MM74HC
MM54HC.
Input Rise or Fall Times
(t,., til
Vcc=2.0V
Vee=4.5V
Vee=9.0V
Min
2
0
Max
12
Vee
Units
V
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25·C
Typ
74HC
54HC
TA= -40 to 85·C TA= -55 to 125·C Units
Guaranteed Limits
V,H
Minimum High Level
Input Voltage
2.0V
4.5V
,9.0V
12.0V
1.5
3.15
6.3
8.4
1.5
3.15
5.3
8.4
1.5
3.15
6.3
8.4
V
V
V
V
N:IL
Maximum Low Level
Input Voltage
2.0V
4.5V
9.0V
12.0V
0.3
0.9
1.8
2.4
0.3
0.9
1.8
2.4
0.3
0.9
1.8
2.4
V
V
V
V
RON
Maximum "ON" Resistance VCTL =V'H, Is= 1.0 mA
(See Note 5)
V'S=Vcc to GND
(Figure 1)
4.5V 100
9.011 50
12.0 . 30
170
85
70
200
105
85
220
110
90
2.0V 120
VCTL =V'H, Is= 1.0 mA 4.5V 50
9.0V 35
V'S = Vcc or GND
(Figure 1)
12.0V 20
180
80
60
40
215
100
75
60
240
120
80
70
15
10
10
20
15
15
20
15
15
n
n
n
n
n
n
n
n
±0.1
±1.0
±1.0
/J- A
RON
Maximum "ON" Resistance VCTL =V'H
Matching
V,s=VcctoGND
4.5V
9.0V
12.0V
10
5
5
a
n
liN
Maximum Control
Input Current
V'N=VCCorGND
Vee=2-6V
liZ
Maximum Switch "OFF"
Leakage Current
Vas = Vee or GND
V,s=GNDorVcc
VeTL = V,Lo--- y
F-_....'
G-_-..
H -..... TLlF/5135-2
3-405
Operating Conditions
Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage (VCe>
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K. 10K)
DC Output Current. per pin (lOUT)
DC Vee or GND Current. per pin (Ice>
Storage Temperature Range (TSTG)
Power Dissipation (Pb) (Note 3)
Lead Temperature (Tt.l
(Soldering 10 seconds)
-0.5 to +7.0V
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TAl
MM74HC
MM54HC
Input Rise or Fall TImes
(tr• tl)
Vce=2.0V
Vee=4.5V
Vce=6.0V
-1.5 to Vcc+ 1.5V
-0.5 to Vee+0.5V
±20mA
±25mA
±50mA
-65·C to + 150·C
500mW
260·C
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vcc
;
TA=2S·C
Typ
74HC
TA=-40to8S·C
S4HC
TA=-SSto12S·C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
!IOUT!';;20 /JoA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIHorVIL
!loUT!';;4mA
!loUT!';;5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VecorGND
6.0V
±0.1
±1.0
±1.0
/JoA
VIN = VIH or VIL
!IOUT!';;4.0 rnA
!IOUT!';;5.2mA
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
VIN=VIHorVIL
!lOUT!';;20 /JoA
40
Maximum Quiescent VIN = Vee or GND 6.0V
2.0
20
/Jo A
,
Supply Current
IOUT=O/JoA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device mayoccur.
Nole 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Powo-~
TL/F/5369-2
3-408
Absolute Maximum Ratings (Notes 1 &2)
-0.5 to + 7.5V
Supply Voltage (Vee)
Supply Voltage (VEE)
+0.5 to -7.5V
DC Control Input Voltage (VIN)
-1.5 to Vee + 1.5V
DC Switch I/O Voltage (VIO)
VEE-0.5 to Vee+0.5V
±20mA
Clamp I:liode Current (11K. 10K>
±25mA
DC Output Current. per pin (lOUT)
±50mA
DC Vee or GND Current. per pin (Ieel
Storage Temperature Range (TSTG)
-65'Cto + 150'C
Power Dissipation (Po) (Note 3)
500mW
Lead Temperature (TLl
260'C
(Soldering 10 seconds)
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Operating Conditions
Supply Voltage (Veel
Supply Voltage (VEE)
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TAl
MM74HC
MM54HC
Input Rise or Fall Times
(le. t,) Vee=2.0V
Vee=4.5V
Vee=6.0V
Min
2
0
0
Max
6
-6
Vee
Units
V
V
V
-40
-55
+85
+125
'C
'C
1000
500
400
ns
ns
ns
•
VEE
Vee
TA=25'C
Typ
74HC
54HC
TA= -40 to 85"C TA= -55to 125"C Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
RoN
Minimum "ON" Resistance VCTL =VIH.ls=1.0mA GND 4.5V 100
-4.5V 4.5V 40
(See Note 5)
VIS = Vee to VEE
(Figure 1)
-B.OV B.OV 30
170
85
70 4
200
105
85
220
110
90
180
80
60
40
215
100
75
60
240
120
80
70
15
10
10
20
15
15
20
15
15
n
n
n
n
n
n
n
n
n
n
±1.0
/LA
GND 2.0V 100
VcITL =VIH.ls= 1.0 mA GND 4.5V 40
-4.5V 4.5V 50
VIS = Vec or VEE
(Figure 1)
-B.OVo B.OV 20
RON
Maximum "ON" Resistance VCTL=VIH
Matching
Vls=VeetoGND
liN
Maximum Control
Input Current
VIN=VeeorGND
liZ
Maximum Switch "OFF"
Leakage Current
VOS=Vccor GND
VIS = GND or Vee
VCTL =VIL (Fig 2)
ilZ
Maximum Switch "ON"
Leakage Current
Vos=VccorGND
VCTL=VIH
(Figure 3)
GND 4.5V 10
-4.5V 4.5V 5
-6.0V 6.0V 5
6.0V ±0.1
±1.0'
GND 5.5V
-B.OV B.OV
±60
±100
±600
±1000
±600
±1000.
nA
nA
GND 5.5V
-B.OV B.OV
±40
±60
±150
±300
±150
±300
nA
nA
Maximum Quiescent
GND B.OV
2.0
20
40
VIN=VeeorGND
/LA
160
Supply Current
-6.0V B.OV
8.0
80
/LA
IOUT=O IJ.A
Note 1: Absolute Maximum RaUngs are those value. beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mW/,C from 65'C to 65'C; ceramic "J" package: -12 mW/'C from 1OO'C to 125'C.
Note 4: For a power supply of 5V ± 10% the worst case on resistances (RON) occUrs for HC at 4.5V. Thus the 4.5V values should be used when designing with
this supply. Worst case VIH and VIL occur at Vee=5.5V and 4.5V respectively. (The VIH value at 5.5V Is 3.65V.) The worst case leakage current occurs for CMOS
at the higher voltsge and so the 5.5V values should be used.
Note 5: At supply voltsges (Vee-Yes approaching 2V the analog switch on reslstsnce becomes extremely non-Unear. Therefore It Is recommended that these
devices be used to transmit digital only when uSing these supply voltsges.
Icc
3·409
AC Electrical Characteristics Vcc= 2.0V-6.0V. VEE = OV-6V. CL = 50 pF (unless otherwise specified)
Symbol
Parameter
Conditions
VEE
Vee
TA=25"C
74HC
54HC
TA=-40to85"C
TA=-55to125"C
Typ
tpHL. tpLH
tPZL. tPZH
Maximum Propagation
Delay Switch In to
Out
Maximum Switch Tum
"ON" Delay
(Control)
RL=1 kO
Maximum Switch Tum
"OFF" Delay
(Control)
RL=1 kO
:
GND
GND
-4.5V
-6.0V
2.0V
4.5V
4.5V
6.0V
GND
GND
-4.5V
-6.0V
2.0V
4.5V
4.5V
6.0V
GND
GND
-4.5V
-6.0V
2.0V
4.5V
4.5V
6.0V
Units
Guaranteed LImits
50
10
8
7
63
13
12
11
75
15
14
13
ns
ns
ns
ns
65
35
32
30
206
43
39
37
250
53
48
45
ns
ns
ns
ns
45
15
10
8
250
50
44
375
75
66
66
, ns
ns
ns
25
:5
4
3
44
312
63
55
55
tPZL. tPZH
Maximum Switch
Turn "ON", Delay'
(Enable)
GND
GND
-4.5V
-6.0V
2.0V
4.5V
4.5V
6.0V
35
20
19
18
205
41
38
36
256
52
48
45
308
62
57
54
ns
ns
ns
ns
tpLZ. tpHz
Maximum Switch
Turn "OFF" Delay
(Enable)
GND
GND
-4.5V
-:-6.0V
2.0V
4.5V
4.5V
6.0V
48
18
13
11
265
330
67
59 '
59
400
79
70
70
ns
ns
ns
ns
GND
-4.5V
4.5V
4.5V
30
35
tpHZ. tpLZ
fMAX
Minimum Switch
Frequency Response
20 log(VIIVO)=3 dB
II(
~3
47
47
"
MHz
MHz
.
,.
mVp.p·
Cross Talk Control
to Switch
(Figure 7)
-4.5Y
4.5V
Cross Talk Between
(Figure 8)
-4.5V
4.5V
MHz
GND
GND
4.5V
4.5V
dB
dB
100
any Two Switches
(Frequency at - 50 d~)
Feedthrough. SwHch
Input to Switch
Output
'10
CIN
Maximum Control
Input Capacitance
CIN
Mmamum Switch
Input Capacitance
Input
15
pF
CIN
Maximum Feedthrough
Capacitance
VCTL =GND
5
pF
CpO
Power Dissipation
Capacitance
15
pF
5
10
pF
10
/
3-410
iii:
iii:
AC Test Circuits and Switching Time Waveforms
....
o....
(II
::t:
Vee
Co)
.....
CD
Ven =V(ft - - -......
......
VIS
--+-41/0
10F4
SWITCHES
iii:
iii:
.......
::t:
....
0/11--....- - Vos
2
Co)
110
1 Of 4
SWITCHES
.....
CD
011 t - - - - VOI-YccOIiGNO
VEE
TUF/5369-3
TUF/5369-4
FIGURE 1. "ON" Resistance
FIGURE 2. "OFF" Channel Leakage Current
Vee
CONTROL
Vee
1 OF 4
SWITCHES
011 t - - - - Vos
VEE
VEE
TLlF/5369-5
FIGURE 3. "ON" Channel Leakage Current
YCTL-YIH
vee
VIS
VII
OV
vos
Voo
Vos
OV
TL/F/5369-6
FIGURE 4. tpHu tpLH Propagation Delay Time Signal Input to Signal Output
'PZL
VCTL---'
vec~IRL
50%
t-+-VOI
ov~•.
~
VDO
VOL
TUF/5369-7
FIGURE 5. tpzu tpLZ Propagation Delay Time Control to Signal Output
3-411
U)
.-
~
o
r----------------------------------------------------------------------------,
AC Test Circuits and Switching Time Waveforms (Continued)
::t:
....
......
:iii
:iii
......
tPZH
'eTL
tpHZ
vee~
50%
U)
.-
....
CO)
RL
o
....
an
OV
VEE
:iii
:iii
10%
VOH
lk
::t:
vee~50%
OV~H
1-+--...-V08
~~
v::~r::%
ov
Voo
.--~
TLlFI5369-8
FIGURE 6. tpZH. tpHZ Propagation Delay Time Control to Signal Output
VeTL-----,
Vee
0:~-~-=-8-n-'~~:K-l-::J.~~-90%-~1{ .-.•
Ve
IN/OUT S~I~~:ESOUTIINI-...........- -....~-Vos
J50
'EE
CL
PF
----1·y,:---IF •t
Vos
CROSSTALK
TL/F/5369-9
FIGURE 7. Crosstalk: Control Input to Signal Output
v"
8000
CGNTROL
v"
IN/OUT S~I~~$OUTIIN
'DlUI
YEE
:&0
'IS(II
':"
.,..
'EE
VII(1)
v"
WerLlII-·'
CONTROL
v"
lli/OUT ~~:fSOUTIIN
'EE
'EE
V"I2I
ftL
8000
.,..
FIGURE 8: Crosstalk Between Any Two Switches
Typical Performance Characteristics
TypicaI 4 ·ON"· Resistance
Vs. Input Voltage
90
75
~
60
)~
45
30
15
-6
.
-...- 1-'0 ....
....... 1"- ...
i-" -f-
-4 -2 0
2
4
INPUT VOLTAGE ('OLTS)
6
Vee= -Vee
TL/F/5369r 17
3-412
~
TLlF/5369-10
~National
PRELIMINARY
j
~\
~ Semiconductor
microCMOS
MM54HC4511/MM74HC4511
BCD-to-7 Segment Latch/Decoder/Driver
This high speed latch/decoder/driver utilizes microCMOS.
Technology, 3.5 micron silicon gate P-well CMOS. It has the
high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive
10 LS-TTL loads. The circuit provides the functions of a 4bit storage latch, an 8421 BCD-to-seven segment decoder,
and an output drive capability. Lamp test (LT), blanking (Si),
and latch enable (LE) inputs are used to test the display, to
turn-off or pulse modulate the brightness of the display, and
to store a BCD code, respectively. It can be used with seven-segment light emitting diodes (LED), incandescent, fluorescent, gas discharge, or liquid crystal readouts either directly or indirectly.
Applications include instrument (e.g., counter, DVM, etc.)
display driver, computer/calculator display driver, cockpit
display driver, and various clock, watch, and timer uses.
The 54HC174HC logic family is speed; function, and pinout
compatible with the standard 54LS174LS logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to Vee and ground.
•
•
•
•
Latch storage of input data
Blanking input
Lamp test input
Low power consumption characteristics of CMOS
devices
• Wide operating voltage range: 2 to 6 volts
• Low input current: 1 /LA maximum
• Low quiescent current: 80 /LA maximum over full temperature range (74 Series)
Connection Diagram
Truth Table
Dual-In-Line Package
INPUTS
116 115 114 113 112 111' 110 19
x
L
L
L
L
11 P 13
14
15 16 P 18
8
81
LE
C
LT
D
A
OUTPUTS.
LE BI LT DeB A a b c d e f
x x
L
H
H
H
H
L H
L
L
L
L
GND
TOP VIEW
H
H
H
H
L H
L H
TUF/5373-1
Order Number MM54HC4511J or MM74HC4511J, N
See NS Package J16A or N16E
L
L
L
L
L
H
H
H
H
H
H
H
g DISPLAY
L x x x X H H H H H H H
H X X X X L L L L L L L
H L L L L H H H H H H L
H L L L H L H H L L L L
H L L H L H H L H H L H
H L L H H H H H H L L H
H L H L L L H H L L H H
H L H L H H L H H L H H
H L H H L L L H H H H H
H L H H H H H H L L L L
HHLLLHHHHH H H
H HLLHHHHLL Ii H
H HLHLLLLLLLL
H H L. H H L L L L L L L
H HHLLLLLLLLL
H HHLHLLLLLLL
H HHHLLLLLLLL
H HHHHLLLLLLL
H X X X·X
8
o
1
2
3
4
5
6
7
8
9
x= Don't care
• = Depends upon the BCD code applied during the 0 to 1 transition of LE.
3-413
....U\
....
.....
:x
Features
bed.
:x
o.c.
i:
i:
.....
.c.
General Description
Veelg.
i:
i:
U\
.c.
2
U\
....
....
•
Absolute Maximum Ratings (Notes 1 and 2)
Operating Conditions
-0.5 to +7.0V
Supply Voltage (VeC>
DC Input Voltage (VIN)
Supply Voltage (VeC>
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
-1.5 to Vee + 1.5V
DC Output Voltage (VOUT)
Clamp Diode Current (11K. 10K>
DC Output Current. per pin (loUT)
DC Vee or GND Current. per pin (IcC>
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
-0.5 to Vee+0.5V
±20mA
±25mA
±50mA
-65·Cto +150·C
Lead Temp. (T U (Soldering 10 seconds)
Min
2
Max
6
0
Vee
Units
V
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
Vee=2.0V
(t,. tt)
Vee=4.5V
Vee=6.0V
500mW
260·C
DC Electrical Characteristics (Note 4)
Symbol
Paramet!!r
Conditions
Vee
TA=25·C
Typ
74HC
TA= -40 to 85·C
54HC
TA=-55to125·C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1;5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
'V
VOH
Minimum High Level
Output Voltage
VIN=VIH orVIL
IIOUTls20p.A
2.0V
4.5V
6.0V
2.0
4.5
.6.0
1.9
4.4
5.9
1.9
4.4
5.9.
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0:1
0.1
0.1
0.1
0.1
V
V
V
VIN=VIH orVIL
IIOUTls4.0 mA
ilOUTI s 5.2 mA
4.5V
6.0V
0.2.
0.2
0.26
0.26
0.33
0.33
0,4
0.4
V
V
VIN=VeeorGND
6.0V
±O.1
±1.0
±1.0
p.A
VIN = VIH or VIL
IIOUTIS7.5 mA
IIOUTls9.75 mA
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
VIN=VIH orVIL
IIOUTls20p.A
Maximum Quiescent VIN = Vee or GND
6.0V
80
160
8.0
p.A
Supply Current
IOUT=O,..A
I
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voHages are reterenced to ground.
Note 3: Power Dissipation temperature derating - plastic UN" package: -12 mWrc from 6S"C to 8S"C; ceramic uJu package: -12 mWrc from 1ocrc to 12S"C.
Note 4: For a power supply of SV ± 10% the worst case outpui voltages (YOH. and You occur for HG at 4.SV. Thus the 4.SV values should be used wheh
designing with this supply. Worst case VIH and VIL occur at Vcc= S.SV and 4.SV respectively. (The VIH value at S.SV is 3.8SV.) The worst case leakage current (liN.
Icc. and lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
Icc
3·414
s::
s::
AC Electrical Characteristics Vee = 5V. TA =25'C. CL = 15 pF. tr=tf= 6 ns
UI
.a:.
:::E:
Typ
Guaranteed
Limit
Units
Maximum Propagation
Delay from Inputs A thru D to any Output
60
120
ns
Maximum Propagation
Delay from Bi to any Output
60
120
ns
tpHL. tpLH
Maximum Propagation
Delay from LT to any Output
60
120
ns
ts
Minimum Setup Time
Inputs A thru D to LE
10
20
ns
tH
Minimum Hold Time
Inputs A thru D tei LE
-3
0
ns
tw
Minimum Pulse Width
for LE
16
ns
Symbol
Parameter
tpHL. tpLH
tPHL. tpLH
Conditions
o
.a:.
UI
......
......
.....
s::
s::
......
.a:.
:::E:
o
.a:.
UI
......
......
AC Electrical Characteristics CL = 50 pF. tr= tf= 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
Vee
TA=25'C
Typ
74HC
TA= -4Dt085'C
54HC
TA= -55to 125'C
Units
Guaranteed Limits
tpHL. tpLH
Maximum Propagation
Delay from Inputs
A thru D to any Output
LE=OV
LT=Vee
Bi=vee
2.0V
4.5V
6.0V
300
60
51
600
120
102
756
151
129
894
179
152
ns
ns
ns
tpHL. tpLH
Maximum Propagation
Delay from Bi to
any Output
LT=Vce
2.0V
4.5V
6.DV
300
60
51
600
120
102
756
151
129
894
179
'152
ns
ns
ns
tpHL. tpLH
Maximum Propagation
Delay from LT to
any Output
BI=OV,
2.0V
4.5V
6.0V
300
60
51
600
120
102
756
151
129
894
179
152
ns
ns
ns
Is
Minimum Setup Time
Inputs A thru D to LE
2.0V
4.5V
6.0V
100
20
17
126
25
21
149
30
25
ns
ns
ns
tH
Minimum Hold Time
Inputs A thru D to LE
2.0V
4.5V
6.0V
0
0
0
0
0
0
0
0
0
ns
ns
ns
tw
Minimum Pulse Width
for LE
2.0V
4.5V
6.0V
80
16
14
100
20
17
120
24
20
ns
ns
ns
tr• tf
Maximum Input Rise and
Fall Time
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
CPO
Power Dissipation
Capacitance (Note 5)
pF
Maximum Input
10
10
pF
5
10
Capacitance
Note 5: CPO determines the no load dynamic power consumption. Po = Cpo vec2 f + Icc Vce. and the no load dynamic current consumption. Is =Cpo Vee f + Icc. .
CIN
3-415
~ r-------------------------------------~--------------~----------------------------__,
~
&I)
zs
~
:IE
:IE
..
"
~
~
&I)
o
:3:
:;
INPUTS
A, B, C, D (Pins 7,1,2, 6)-8CD data inputs. A (pin 7) is the
least-significant data bit and D (pin 6) is the most significant
bit. Hexadecimal data A-F at these inpu~s will cause the
outputs to assume a logic low, offering an alternate method
of blanking the display.
OUTPUTS
a-g-Decoded, buffered outputs. These outputs, unlike the
4511, have CMOS drivers, which will produce typical CMOS
output voltage levels.
:IE
:IE
CONTROLS
iii (Pin 4)-Active-low display blanking input. A logic low on
this input will cause all outputs to be held at a logic low,
thereby blanking the display. LT is the only input that will
override the 81 input.
LT (Pin 3)-Active-low lamp test. A low logic level on this
input causes all outputs to assume a logiC high. This input
allows the user to test all segments of a-display, wi!h a
single control input. This input is independent of all other
inputs.
.
LE (Pin 5)-Latch enable input. This input controls the 4-bit
transparent latch. A logiC high on this input latches the data
present at the A, 8, C and D inputs; a logic low allows the
data to be transmitted through the latch to the decoder.
Output Characteristics (Vcc=5V)
-25 ...-..,."=,.,,.--.,.....-=-,,-==
25
~
~
0-
......ifi
20
~
.
::>
15
10
!iii -20 1-"""--"7/1-=-1--
--~--~-,
B -15 I-l~A'-(;"..p.!';:"~::::1
,.
~
Ii! -10
li-H~T+--+--+-t
!
~
"""'f------'!
co
I
-5
0-
~
s
$I
4
2
1
4
Yo-OUTPUT VOLTAGE (VI
1
Yo-OUTPUT VOLTAGE (VI
TLlF/5373-2
TL/F/5373-3
'The expected minimum curves are not guarantees, but are design aids.
Typical Applications
He
4511
•
••
R
He
4511
75011
TLlF/5373-4
Typical Common cathode LED Connection
TLlF/5373-5
Incandescent Bulb Driving Circuit
3-416
3:
3:
Logic Diagram
U1
""o
:::r:
""
lE
U1
.....
.....
......
5
3:
3:
......
:::r:
""o
""
.....
.....
(2') A
U1
lE
(2')
A
B
lE
•
lE
(2')
D
lE
TL/F/5373-6
TLIF/5373-7
Segment Identification
1m b
a
e'~~c
3-417
TLIF/5373-8
r::
.... ,----------------------------------------------------------------------------,
~
II)
~
o
::J:
~
~National
PRELIMINARY
~ Semiconductor
,,~
microCMOS,
:IE
:IE
~
.... MM54HC4514/MM74HC4514
II)
~
o
::J:
~
II)
:IE
:IE
4-to-16 Line Decoder with Latch
General Description
This utilizes microCMOS Technology, 3.5 micron silicon
gate P·well CMOS decoder, which is well suited to memory
address decoding or data routing application. It possesses
high noise immunity and low power dissipation usuallyassociated with CMOS circuitry, yet speeds comparable to low
power Schottky TTL circuits. It can drive up to 10 LS-TTL
loads.
The MM54HC4514/MM74HC4514' contain a 4-t0-16 line
decoder and a 4-bit latch. The latch can store' the data on
the select, inputs, thus allowing a selected output to remain
high even though the select data has changed. When the
LATCH ENABLE input to the latches is high the outputs will
change with the inputs. When LATCH ENABLE goes low
the data on the select inputs is stored in the latches. The
. four select inputs determine which output will go high pro·
vided the INHIBIT input is low. If the INHIBIT input is high all
, outputs are held low thus disabling the decoder.
The MM54HC4514/MM74HC4514 is functionally and pinout
equivalent to the CD4514BM/CD4514BC and the.
MC1451BAlMC1451BC. All inputs are protected against
'damage due to static discharge diodes from Vee and
ground.
Features
•
•
•
•
Typical propagation delay: 18 ns
Low quiescent power:.80 p.A maximum (74HC Series)
Low input current 1 p.A maximum
Fanout of 10 ,LS.TTL loads (74HC Series)
Connection Diagram
Truth Table
Dual-In-Llne Package
INPUTS
Voo 'INHIBIT IN 0
IN C\ '510
IN I~ ~ ~
..
Datalnputa
.
OUTPUTS
m
511
w
sa
S9
u
n
514
K
815
~
812
«
813 '
~
L
L
L
L
L
H
L
H
SO
S1
S2
S3
H
L
L
L
L
L H L L
L H L H
L H H L
S4
H
H
H
H
H
H
L
L
L
H L
L
L
H
L
H
H
H
H
H
L
L
L
L
H H
Top View
x
H
X X X X Outputs=O
Order Number MM54HC4514J or MM74HC4514J,N
See NS Package J24A or N24A
L
L
XXXX
.
H
H
4-TD-16 DECODER
.......-+1
H
10
INPUTS
DeB A
L
L
L,
L
LATCH
IN A
Inhibit
H
H
H
H
,
STROBE
LE
INS
.
87
56
55
54
S3
51
82
11
SO
.r
Vss
L
L
L
L
L
L
L
L
L
H
H
Selected
Output
High
H
H L H L
H, L H H
L
L
H H L H
H H H
L
H
H
H
H
OUTPuTS
3418
S5
S6
S7
, S8
S9
S10
S11
S12
S13
S14
815
All
Latched
Data
Absolute Maximum Ratings (Notes 1 and 2)
Operating Conditions
Supply Voltage (VeCl
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (ilK, 10K)
DC Output Current, per pin (lOUT)
DC Vee or GND Current, per pin (Ice>
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
Lead Temperature (Tt.>
(Soldering 10 seconds)
Supply Voltage (Vee>
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TAl
MM74HC
MM54HC
Input Rise or Fall Times
(tr, tf)
Vee=2.0V
Vee=4.5V
Vcc=6.0V
-0.5 to +7.0V
-1.5toVee+ 1.5V
-0.5 to Vee+0.5V
±20mA
±25mA
±50rnA
-65·C to + 150·C
500mW
260·C
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=25·C
74HC
TA= -40 to 85·C
Typ
VIH
VIL
I
VOH
liN
Units
Guaranteed Limits
Minimum High Level Input
Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
Maximum Low Level Input
Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
Minimum High Level Output
Voltage
VIN = VIH or VIL.
IIOUTI ~20 /LA
Maximum Low Level Output
Voltage.
Maximum Input Current
I
2.0V
4.5V
6.0V
2.0.
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
IIOUTI~4.0 mA
IIOUTI ~ 5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VccorGND
6.0V
±0.1
±1.0
±1.0
/LA
VIN = VIH or VIL
IIOUTI ~4.0 mA
IIOUTI ~ 5.2 rnA
VOL
54HC
TA= -55 to 125·C
VIN = VIH or VIL
IIOUTI~20 ,..A
Maximum Quiescent Supply VIN=VccorGND 6.0V
8.0
80
160
Icc
/LA
Current
IOUT=O,..A
Note 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless othelWise specifiGd all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic UN" packlige: -12 mWrc frrim 65°C to 85"C; ceramic uJ" package: -12 mW'oC from 100'C to 125°C.
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH. and Vou occur for HC at 4.SV. Thus the 4.5V values sho~ld be used when
designing with this supply. Worst case VIH and VIL occur at Vcc=5.5V and 4.5V respectively. (The VIH value at 5.5V Is 3.85V.) The worst case leakage current (liN.
Icc. and lozl occur for CMOS at the higher voltage and so the 6.0V values should be used.
3·419
AC Electrical Characteristics Vcc=5V. TA = 25·C. CL = 15 pF. t,.=t,= 6 ns
Symbol
Parameter
Conditions
TyP
Guaranteed
Umlt
18
30
ns
tpHL
. Maximum Propagation Delay LE to Output
18
30
ns
tpLH
Maximum Propagation Delay LE to Output
24
40
ns
tpHL
Maximum Propagation Delay Inhibit to Output
16
30
ns
tpLH
Maximum Propagation Delay Inhibit to Output
24
40
ns
Is
Minimum Setup Time. Date to LE
20
ns
tH
Minimum Hold Time. LE to Data
5
ns
tw
Minimum Pulse Width. Latch Enable
16
ns
tpHL. tpLH
Maximum Propagation Delay Data to Output
Units
AC Electrical Characteristics Vcc=2.0V-6.0V. CL =50 pF. t,.=t,=6 ns (unless otherwise specified)
Symbol
Conditions
Parameter
Vee
TA=25"C
Typ
tpHL. tpLH
Maximum Propagation
. Delay Data to Output
74HC
TA= -40 to 85"C
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
2.0V
4.5V
6.0V
80
18
16
175
35
30
220
44
38
263
53
45
ns
ns
ns
tpHL
Maximum Propagation_
Delay LE to Output
2.0V
4.5V
6.0V
80
19
17
175
35
30
220
44
38
263
53
45
ns
ns
ns
tpLH
Maximum Propagation
Delay LE to Output
2.0V
4.5V
6.0V
120
27
22
230
46
39
290
58 .
343
69
58
ns
ns
ns
Maximum Propagation
Delay Inhibit to Output
2.0V
4.5V
6.0V
70
18
16
175
35
30
220
38
263
53
45
ns
ns
ns
tpLH
Maximum Propagation
Delay Inhibit to Output
2.0V
4.5V
6.0V
120
27
22
230
46
39
290
58
49 .
343
69
58
ns
ns
ns
ts'
Minimum Setup Time.
DatatoLE
2.0V
4.5V
6.0V
100
20
17
125
25
21
150
30
25
ns
ns
ns
tH
Minimum Hold Time.
LEtoData
2.0V
4.5V
6.0V
5
5
5
5
5
5
tw
Minimum Pulse Width.
Latch Enable
2.0V
4.5V
6.0V
80
16
. 14
100
20
17
CPO
Power Dissipation
Capacitance
CIN
Maximum Input
Capacitance
tpHL
-
49
44
-
5
• 5
5
ns
ns
ns
120
24
20
ns
ns
ns
pF
5
10
. 10
10
pF
Note 6: CPO determines the no load dynamic power consumption. Po= Cpo vrx;2 f+ Icc Vee. and the no load dynamic current consumption. Is = Cpo Vcc f+ Icc.
~
3-420
!iii:
!iii:
Logic Diagram
CI'I
,f:Io
:::c
0
,f:Io
CI'I
~HllllS0
....!iii:
Anl! 9 81
:::c
,f:Io
!iii:
.....
,f:Io
0
,f:Io
liBCl!IO S2
CI'I
,f:Io
ABeD B S3
INA 2
ABeD 7 S4
AleD 6 S5
liBcl! 5 S6
INB 3
ABCD 4 S7
DATA
nco 18 SS
INC
21
I"C 0 17 S9
ABCD 19 811
IND 22
UTCH I
llIeD 14812
ENAB~
ABCD 13 S13
ABeD 16 S14
INHIBIT 23
ABCD 15
S15
Tl/F/5215-2
3-421
~National
LA
\'--__
--,./J
~ Semiconductor
microCMOS
MM54HC4538/MM74H,C4538 Dual
Retriggerable Monostable Multivibrator
General Description
The MM54HC4538/MM74HC4538 high speed monostable
multivibrators (one shots) are implemented in microCMOS Technology, 3,5 micron silicon gate P-well CMOS.
They feature speeds comparable to low power Schottky
TIL circuitry while retaining the low power and high noise
immunity characteristic of CMOS circuits.
'
Each multivibrator features both a negative, A, and a positive, B, transition triggered input, either of which can be
used as an inhibit input. Also included is a clear input that
'when taken low resets the one shot. The 'HC4538 is retriggerable. That is, it may be triggered repeatedly while their
outputs are generating a pulse and the pulse will be extended.
Pulse width stability over a wide range of temperature and
supply is achieved u~,ing linear CMOS techniques. The out-
put pulse equation is simply: PW = 0.7(R) (C) where PW is in
seconds, R is in ohms, and C is in farads. This device is pin
compatible with the CD4528, and the CD4538 one shots. All
inputs are protected from damage due to static discharge by
diodes to Vee and ground.
'
Features
•
•
•
•
•
Schmitt trigger on A and B inputs
.wide power supply range: 2-6V
Typical trigger propagation delay: 32 ns
Fanout of 10 LS-TIL loads (74HC)
Low input current: 1 /LA max
Connection and Block Diagrams
Dual-In-Llne Package
YIlD
TIB
T28
CDS
AsBa
INPUT INPUT
AA
8A
INPUT INPUT
TOPVIEW •
Os
O,UT
1ia
Cx
OUT
Vss
QA
OUT
TL/F/5217-1
10
1 2 -....._
11-___,
Order Number MM54HC4538J or MM74HC4538J,N
See NS Package J16A or N16E
Co
Truth Table
Inputs
Clear
L
X
X
H
H
B
X
X
L
a
Q
L
L
L
H
H
H
L
,J,
t
H
J'1...
J'1...
'1...f'
'1...f'
X
H
X
H = High Level
L = Low Level
t = Transition from Low to High
.J, = Transilion from High to Low
9
13-...........:.--...1
Outputs
·A
RX
RX AND Cx ARE EXTERNAL COMPONENTS
TL/F/5217-2
.I1. = One High Level Pulse
'l.f = One Low Level Pulse
X = Irrelevant
3-422
Absolute Maximum Ratings (Notes 1 and 2)
Supply Voltage
DC Input Voltage (VIN)
DC Output Voltage
DC Output Current. per pin (lour)
DC Vee or GND Current. per pin (lee)
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
Lead Temperature (T tJ
(Soldering 10 seconds)
Operating Conditions
-0.5to +7.0V
-1.5 to Vcc+ 1.5V
-0.5 to Vcc+ 0.5V
±20mA
±25mA
±50mA
--'65·Cto + 150·C
500mW
Supply Voltage (VeC>
DC Input or Output Voltage
(VIN. Your)
Operating Temp. Range (TAl
MM74HC
MM54HC
Input Rise or Fall Times
(Reset only)
(tr• til
Vee=2.0V
Vcc=4.5V
Vee=6.0V
260·C
Min
2
0
Max
6
Vee
Units
V
V
-40
-55
+85
+125
·C
·C
1000
500
400
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
TA=25·C
Vee
Typ
74HC
54HC
TA= -40 to 8S·C TA= -SSt012S·C Units
Guaranteed Limits
VIH
Minimum High Level Input
Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level Input
Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level Output VIN = VIH or VIL
Voltage
!lour!";;20 p.A
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
3.98
5.48
3.84
5.34
3.7
5:2
V
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
!lour!";;4.0 mA
!lour!";;5.2mA
VOL
Maximum Low Level Output VIN = VIH or VIL
Voltage
!lour!";;20 p.A
2.0V
4.5V
6.0V
2.0
4.5
6.0
4.5V
6.0V
2.0V
4.5V
6.0V
0
0
0
VIN = VIH or VIL
!lour!";;4.0 mA
!lour!";;5.2 mA
4.5V
6.0V
0.26
0.26
0.33
0.33
0.4
0.4
V
V
liN
Maximum Input Current
(Pins 2. 14)
VIN = Vee or GND
6.0V
fO.5
±5.0
±10
p.A
liN
Maximum Input Current
(all other pins)
VIN=VeeorGND
6.0V
±O.1
±1.0
±1.0
p.A
Maximum Quiescent Supply VIN=VeeorGND
Current
p.A
6.0V 100 150
400
250
IOUT=O,..A
Pins 2 and 14 = 0.5Vee
Note 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation Temperature Derating: Plastic "N" Package: -12mWI'C from 65'C to 85'C Ceramic "J" Package: -12mW/'C from 100'C to 125'C
Note 4: For a power supply of 5V ±10% the worst case output voltages (YOH. and Vou occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case'VIH and VIL occur at Vee = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current
(lIN. Icc. and lozl occur for CMOS al the higher vollage and so the 6.0V values should be used.
Icc
3-423
•
AC Electrical Characteristics Vcc=5V, TA=25'C, CL =15pF, t,.=tf=6 ns
Typ
Limit
tpLH
Maximum Propagation Delay A, or B to Q
Parameter
23
45
ns
tpHL
Maximum Propagation Delay A, or B to Q
26
50
ns
ns
Symbol
,
Conditions
Units
Maximum Propagation Delay Clear to Q
23
45
tpLH
Maximum Propagation Delay Clear to Q
26
50
ns
tw
Minimum Pulse Width A, B or Clear
10
16
ns
tpHL
AC Electrical Characteristics CL = 50 pF, tr=tf= 6 ns (unless ~therwise specified)
Symbol
Parameter
Vcc
Conditions
TA=25'C
Typ
74HC
TA=-40t085'C
54HC
TA= -55 to 125'C
Units
Guaranteed Limits
tpLH
Maximum Propagation
Delay A, or B to Q
2.0V
4.5V
6.0V
100
25
21
250
50
43
315
63
. 54
'373
75
6;3
ns
ns
ns
tpHL
Maximum Propaaation
Delay A, or B to Q
2.0V
4.5V
6.0V
110
28
23
275
55
47
347
69
59
410
82
70
ns
ns
ns
tpHL
Maximum Propagation
Delay Clear to Q
2.0V
4.5V
6.0V
100
25
21
250
50
43
315
63
54
373
75
63
ns
ns
ns
tpLH
Maximum Propagation
Delay Clear to Q
2.0V
4.5V
6.0V
110
28
23
275
55
47
347
69
59
410
82
70
ns
ns
ns
tTLH, trHL
Maximum Output
Rise and Fall
TIme
2.0V
4.5V
6.0V
30
10
8
75
15
13
95
19
16
110
22
19
ns
ns
ns
t,., tf
Maximum Input
Rise and Fall
Time (Reset only)
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
tw
Minimum Pulse Width
A, B,Clear
2.0V
4.5V
6.0V
80
16
14
101
20
119
24
20
ns
ns
ns
twa
Output Pulse Width
twa
twa
Output Pulse Width
Output Pulse Width
J
Cx=12P~
Rx=1 kO
Cx=100pF
Rx=10kO
Cx=1000pF
Rx=10kO
3.0V
5.0V
283
147
190
120
ns
ns
Max
3.0V
5.0V
283
147
400
185
ns
ns
Min
3.0V
5.0V
1.2
1.0
,..,s
,..,s
Max
3.0V
5.0V
1.2
1.0
,...s
,...s
Min
3.0V
5.0V
10.5
10.0
9.4
9.3
,..,s
,..,s
Max 3.0V
5.0V
10.5
10.0
11.6
11.7
,..,s
,..,s
CIN
Maximum Input
Capacitance (Pins 2 & 14)
25
CIN
Maximum Input
Capacitance (other inputs)
5
CPO
Power Dissipation
Capacitance (Note 5)
4twa
Pulse Width Match
Between Circuits in
Same Package
(per one shot)
Note 5: CPO determines the no load dynamic consumption, Po
17
Min
pF
10
10
10
150
pF
±1
%
= Cpo Vcc2t+ Iqc Vee. and the no load dynamic current consumption. Is = Vee f +
3·424
pF
lee.
Logic Diagram
-D~, LATCH
,
•
R~LA~
_
_
__
.J
TUF/5217-3
Circuit Operation
The 'HC4538 operates as follows (refer to logic diagram). In
the quiescent state, the extemal timing capacitor, ex, is
charged to Vee. When a trigger occurs, the Q output goes
high and ex discharges quickly to the lower reference voltage (VREF Lower = % Vee). ex then charges, through Rx,
back up to the upper reference voltage (VREF Upper = %
Veel, at which pOint the one-shot has timed out and the Q
output goes low.
The output of the trigger-control circuit is low (#3), and transistors Ml, M2, and M3 are turned off. ·The external timing
capacitor, ex, is charged to Vee (#4), and the upper reference circuit has a low output (# 5). Transistor M4 is turned
on and transmission gate T1 is turned off. Thus the lower
reference circuit has Vee at the noninverting input and a
, resulting low output (#6).
In addition, the output of the trigger-control reset circuit is
low.
The following, more detailed description of the circuit operation refers to both the logic diagram and the timing diagram.
TRIGGER OPERATION
QUIESCENT STATE
The 'HC4538 is triggered by either a rising-edge signal at
input A (#7) or a falling-edge signal at input B (#8), with the
unused trigger input and the Reset input held at the voltage
levels shown;n the Truth Table. Either trigger signal will '
cause the output of the trigger-control circuit to go high
(#9).
In the quiescent state, before an input trigger appears, the
output latch is high and the reset latch is high (# 1 in logic
diagram).
.
Thus the Q output (pin 6 or 10) of the monostable multivibrator is low (#2, timing diagram).
3-425
CD
r-----------~--------------------------------------------------------------------,
CO)
~
(.)
Timing Diagram
.....
%
:IE
:IE
;0
CO)
an
.(.)
%
~
:IE
:IE
rS0
QUIESC--ENT;.:.:.°r'>-----TRIGGER
CYCLE_r=TRIGGER CYCLE
TE,
(A INPUT)
(B INPUT)
I1._ _ _ _-+-_______
TRIGGER INPUT A
(PIN40R 12)
"
hi'
REser
~hj'
t- ,--RErRIGGER-j
-I
"
I
I _
~
's'LJ
TRIGGER INPUT B
(PIN 50R 11)
\V
TRIGGER-CONTROL
f.'\
CIRCUIT OUTPUT __"V;;:3~_
~~
____~r1~______~
@
Rx/Cx INPUT
-~@~2-."
(PIN 20R 14)
____
______r1___
VIIeF UPPER
UPPER REFERENCE
'5'
CIRCUIT __"V,;;;;._.....
®
~
~r-l
n
n
~
U
LOWER REFERENCE
CIRCUIT _ _ _ _......._ _ _ _ _ _ _ _....._ _ _ _ _ _ _ .._ _. . . . , j
_ _ _ _ __
RESErINP\IT----------------------~"!!20.,Ur--------.....- 'ell
(PIN 3 OR 13)
@U
REser LATCH
TL/F/5217-4
Circuit Operati.on
(Continued)
The trigger-control circuit going high simultaneously initiates
three events. First, the output latch goes low, thus taking
the Q output of the 'HC4538 to a high state (# 10). Second,
transistor M3 Is turned on, which allows the external timing
capacitor, Cx, to rapidly discharge toward ground (# 11).
(Note that the voltage across Cx appears at the input of the
upper reference circuit comparator.) Thii-d, transistor M4 is
turned off and transmission gate T1 is turned on, thus allowing the voltage across Cx to also appear at the input of the
lower reference circuit comparator.
.
gle, taking the Q output of the 'HC4538 to a low state (#19),
and completing the time-out cycle.
When Cx discharges to the reference voltage of the lower
reference circuit (# 12), the outputs of both reference circuits will be high (# 13).. The trigger-control reset circuit
goes high, resetting the trigger-control circuit flip-flop to a
low state (# 14). This turns transistor M3 off again, allowing
Cx to begin to charge back up toward Vee, with a time
constant t = RxCx (#15). In addition, transistor M4 is
turned on and transmission gate T1 is turned off. Thus a '
high voltage level is applied to .the input of the lower reference circuit comparator, causing its output to go low (# 16).
The monostable multivibrator may be retriggered at any
time after the trigger-control circuit goes low.
RESET OPERATION
A low voltage applied to the Reset pin always forces the Q
output of the 'HC4538 to a low state.
The timing diagram illustrates the case in which reset occurs (# 20) while Cx is charging up toward the reference
voltage of the upper reference circuit (# 21). When a reset,
occurs, the output of the reset latch goes low (# 22), turning
on transistor M1. Thus Cx is allowed to quickly charge up to
Vee (#23) to await the next trigger signal.
RETRIGGER OPERATION
In the retriggerable mode, the 'HC4538 may be retriggered
during timing out of the output pulse at any time after the
trigger-control circuit flip-flop has been reset (# 24). Because the trigger-control circuit flip-flop resets shortly after
ex has discharged to the reference voltage of the lower
reference circuit (# 25), the minimum retrigger time, tIT is a
funCtion of internal propagation delays and the discharge
time of Cx:
t (ns) .. 72
IT
When Cx charges up to the reference voltage of the upper
reference circuit (# 17), the output of the upper reference
circuit goes low (# 18). This causes the output latch to tog-
3-426
+ Vee(volts). Cx(pF)
30.5"
at room temperature
Circuit Operation (Continued)
POWER-DOWN CONSIDERATIONS
§ 0.76
Large values of Cx may cause problems when powering
down the HC4538 because of the amount of energy stored
in the capacitor. When a system containing this device is
powered down, the capacitor may discharge from Vcc
through the input protection diodes at pin 2 or pin 14. Current through·the protection diodes·must be limited to 30 mA;
therefore, the tum-off time of the Vee power supply must
not be faster than t = VcceCx/(30 mAl. For example, if
Vec = 5V and Cx = 15 JLF, the Vee supply mustturn off no
faster than t = (15V)e(15 JLF)/30 mA = 2.5 ms. This is
usually not a problem because power supplies are heavily
filtered and cannot discharge at this rate. .
TA",2S0C
~ 0.74
8
1:
0.72
j
~ 0.70
~
0.68
~ 0.64
I
".0.62
I
I
....
J
"
2
5
Vee - POWER SUPPLY VOLTAGE (V)
TlIF/5217-5
When a more rapid decrease of Vec to zero volts occurs,
the HC4538 may sustain damage. To avoid this possibility,
use an external clamping diode, OX, connected from Vee to
the Cx pin.
3-427
~ .-----------------------------------------------~---------------------------,
"11:1'
~
o
:J:
"11:1'
"':::IE
.
~National
...........,.
~ Semiconductor
\'-----/J
microCMOS'
::IE
MM54HC4543/MM74HC4543
BCD-to-7 Segment Latch/Decoder/Driver
"11:1'
o
:J: for Liquid Crystal Displays
"11:1'
.~
"11:1'
U)
U)
::IE
::IE
Generbl Description
The MM54HC4543/MM74HC4543 BCD-to-7 segment
latch/decoder/driver utilize microCMOS Technology, 3.5
micron silicon gate P-well CMOS, and can be used either as
a high speed decoder or as a display driver. This circuit
contains a 4-bit latch, BCD-to-7 segment decoder, and 7
output drivers. Data on the input pins flow through to the
output when the LATCH ENABLE (LE) is high and is latched
on the high to low transition of the LE input. The PHASE
input (PH) controls the polarity of the 7 segment outputs.
When PH is low the outputs are true 7 segment, and when
PH is high the outputs are inverted 7 segment. When the
PHASE inpulis driven by a liquid crystal display (LCD) backplane waveform the segment pins output the correct segment waveform for proper LCD AC drive voltages.
In addition a BLANKING INPUT (BI) is provided, which will
blank the display.
Connection Diagram
Features
•
•
•
•
•
•
Typical propagation delay: 60 ns
Supply voltage range: 2-6V
Maximum input current: 1 /LA
Maximum quiescent supply current: 80 /LA (74HC)
Display blanking
Low dynamic power consumption
Truth Table
Dual-In-Llne Package
e
deb
Inputs
9
a
115 114 113 112 111 110
9
2
LE
c
3
B
5
4
D
A
8
Ph
7
BI
TLiF/S128-1
Top View
Order Number MM54HC4543J or MM74HC4543J, N
See NS Package J16A or N16E
.
",,;;,.
.,-,
.
Display Format
•
,,-, -, "-:1-,
,rl ----,rl'-,'I'-IJ'-I-'
'-'1'-'
-'-
9
TLiF/S128-2
g Display
X H
L
X X X X L L L L L L L
Blank
H
H
H
H
L'
L
L
L
L
L
L
L
L L L L H H H H H H L
LLLHLHHLLLL
LLHLHHLHHLH
LLHHHHHHLLH
0
1
H
H
H
H
L
L
L
L
L
L
L
L
LHLLLHHLLHH
LHLHHLHHLHH
LHHLHLHHHHH
LHHHHHHLLLL
4
5
H
H
H
L
L
L
H
L
L
L
L
L
HLLLHHHHHHH
HLLHHHHHLHH
HLHLLLLLLLL
HLHHLLLLLLL
8
9
Blank
Blank
H
H
H
H
L
L
L
L
L
L
L
L
HHLLLLLLLLL
HHLHLLLLLLL
HHHLLLLLLLL
HHHHLLLLLLL
Blank
Blank
Blank
Blank
L
L 'L
t
J -,
o
Outputs
LE BI Ph" D C B A abc d e f
1
iii
iii
1
The MM54HC4543/MM74HC4543 are functionally and pinout equivalent to the CD4543BC/CD4543BM and the
MC14543BAlMC14543BC. All inputs are protected from
damage due to static discharge by diodes to Vee and
ground.
.
t
H
2
3
6
7
X X X X
••
••
t
Inverse of Output
Combinations
Above
Display
as
above
x - don't care
t = same as above combinations
• = for liquid crystal readouts, apply a square wave to Ph .
.. = depends upon the BCD code previously applied when LE-H
3-428
Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage (VeC>
-0.5 to + 7.0V
DC Input Voltage (VIN)
-1.5 to Vee + 1.5V
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
±20mA
Clamp Diode Current (11K. loKl
DC Output Current. per pin (lOUT)
±25mA
±50mA
DC Vee or GND Current. per pin (IcC>
- 65·C to + 150·C
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
500mW
260·C
Lead Temp. (TL> (Soldering 10 seconds)
Operating Conditions
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HC
MM54HC
Input Rise or Fall Times
Vee=2.0V
(tr.tf)
Vee=4.5V
Vee=6.0V
Min
2
0
Max
6
-40
-55
+85
+125
·c
1000
500
400
ns
ns
ns
Vee
Units
V
V
·C
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=2S·C
74HC
TA= -40 to 8S·C
Typ
S4HC
TA= -55 to 12S'C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
4.5V
6.0V
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
V
VOH
Minimum High Level
Output Voltage
VIN=VIHorVIL
IIOUTI :S:20 ].LA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = ViH or VIL
IIOUTI:S:O.4mA
IIOUTI :s: 0:52 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN=VeeorGND
6.0V
±0.1
±1.0
±1.0
p.A
80
160
p.A
VIN = VIH or VIL
/lOUT I :S: 0.4 mA
/louTI:s:0.52 mA
VOL
liN
Maximum Low Level
Output Voltage
Maximum Input
Current
VIN=VIH or VIL
IIOUTI:S:20 p.A
Maximum Quiescent VIN=VeeorGND 6.0V
8.0
Supply Current
IOUT=Op.A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Icc
Nota 2: Unless otherwise specified all voltages are referenced to ground.
Nole 3: Power Dissipation temperature derating - plastic "N" package: -12 mW/·C from 65·C to 85·C; ceramic "J" package: -12 mWI"C from 100·C to 125·C.
Nota 4: For a power supply of 5V ± 10% the worst case output voltages (YaH. and Vall oocur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at Vcc= 5.5V and 4.5V respectively. (The VIH v8Jue at 5.5V is 3.85V.) The worst case leakage current (liN.
ICC. and lozl oocur for CMOS at the higher voltage and so the 6.0V values should be used.
3·429
AC Electrical Cha~acteristics Vcc= 5V, TA = 25'C, CL = 15 pF, t r =t,=6 ns
Symbol
Parameter
tpHL, tpLH
Maximum Propagation
Delay Data LE, BI, Ph to Output
ts
Minimum Setup Time
LEto Data
tH
tw
Conditions
Typ
Guaranteed
Limit
Units
60
100
ns
20
ns
10
ns
16
ns
Minimum Hold Time
. Data to LE
Minimum LE Pulse Width
,
AC Electrical Characteristics CL = 50 pF, tr= t,= 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25'C
Vee
Typ
tpHL, tpLH
Maximum Propagation
Delay ~ata LE, Ph, 81 to Output
2.0V
4.5V
6.0V
ts
Minimum Setup Time
LEtoData
tH
74HC
TA= -40 to 85'C
54HC
TA= -55to 125'C
Units
Guaranteed Limits
600
120
102
760
151
129
895
179
152
ns
ns
ns
2.0V
4.5V
6.0V
100
20
17
125
25
21
150
30
25
·ns
ns
ns
Minimum Hold Time
Data to LE
2.0V
4.5V
6.0V
50
10
9
63
13
11
75
15
13
·ns·
tw
Minimum LE Pulse Width
2.0V
4.5V
6.0V
80
16
14
100
20
17
120
24
20
ns
ns
ns
CPD
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input
Capacitance
300
60
51
ns
ns
pF
5
10
10
10
pF
,
Note 5: CPO determines the no load dynamic power consumption. Po = Cpo Vcr;2 ,+ ICC Vee. and the no load dynamic current consumption. Is = CPO Vee , + lee.
0
..
3·430
Logic
A
5
~iagram
Lsa'"
a3
c2
o
4
L..
...
, I ...
..
~~
...
....
..
...
...
.. ~
~
.....
I ..
.
I ...
...
~
MSa'"
I '"
t
I
r~
1 .... . .
.Jl
h1c
'"
I~
.....
~ L
J
rn
.....
-
8-\.
J
n
~
~
~
~
-r---.
I'
I
.,~
tL
=f):
~,
~
I ...
h
J
,-l...)
I
~'"
al
......
.......
t---'
~
I
~
II
~
~
~
FL-'
~I-
'"
I
Ph·
I
...
---1
~
___ I
Exclusive OR
~
,---------LE
1
..
...
..
:Lc:P
Vee =-= Pin 1&
GND
'"
=
Pin8
I
....
""
I
TL/F/5l2B-3
Typical Applications
4 Digit LCD Display
I- I
r-
I-I
BP
-I
-I
I-
I- I
r-
I-I
BP
I- I
-
I
r-
BP
r-- BP
1111
I
abc
d
e
f
9
abc
LE
Latch Enable
e
f
BI
A B C
LE
D
ABC D
LE
I
1
1
BI
ABC
D
LE
I
i
i
I
e
f
9
L.- Ph
~ Ph
BI
abc d
abcdefg
9
' - Ph
' - Ph
Blanking
d
I- I
I
I
BI
A BCD
I
Data {
Inp~ts
, ... ...
~
~
Rl
Back Plane
~
....
Cl
R2
I
or Phase
CI ~ 0.047 pF
R1 ~ R2 ~ lOOk!!
TLlF/512B-4
3-431
Section 4
MM54HCTI
MM74HCT
Section Contents
MM54HCTOO/MM74HCTOO Quad 2-lnput NAND Gate ................................. .
MM54HCT04/MM74HCT04 Hex Inverter ............................................ .
MM54HCT05/MM74HCT05 Hex Open Drain Inverter .................................. .
MM54HCT08/MM74HCT08QuadANDGate ......................................... .
MM54HCT34/MM74HCT34 Non·lnverting Gate ...................................... .
MM54HCT74/MM74HCT74 Dual D Flip-Flops with Preset and Clear ...................... .
MM54HCT76/MM74HCT76 Dual J-K Flip-Flops with Preset and Clear .................... .
MM54HCT109/MM74HCT109 Dual J-K Flip-Flops with Preset and Clear .................. .
MM54HCT112/MM74HCT112 Dual J-K Flip-Flops with Preset and Clear .................. .
MM54HCT138/MM74HCT138 3-to-8 Line Decoder .................................... .
MM54HCT139/MM74HCT139 DuaI2-to-4 Line Decoder ................................ .
M M54HCT1491 M M74HCT149 8-Li ne to 8-Line Priority Encoder ......................... .
MM54HCT155/MM74HC"F155 DuaI2-to-4 L,ine Decoder/Demultiplexers .................. .
MM54HCT157/MM74HCT157 Quad 2-lnput Multiplexer ................................ .
MM54HCT158/MM74HCT158 Quad 2-lnput Multiplexer(lnverted Output) .................. .
MM54HCT164/MM74HCT164 8-Bit Serial-ln/Paraliel-Out Shift Register .................. .
MM54HCT191/MM74HCT191 Synchronous Binary Up/Down Counters with Mode Control ... .
MM54HCT193/MM74HCT193 Synchronous Binary UplDown Counters ...... : ............ .
MM54HCT240/MM74HCT240 Inverting Octal TRI-STATE Buffer ......................... .
MM54HCT241/MM74HCT241 OctaITRI-STATEBuffer ................................. .
MM54HCT244/MM74HCT2440ctaITRI-STATEBuffer ............................... , ..
M M54HCT245/M M74HCT245 Octal TRI-STATE Transceiver ............................. .
MM54HCT257/MM74HCT257 Quad 2-Channel TRI-STATE Multiplexer .................... .
MM54HCT273/M M74HCT273 Octal D Flip-Flop with Clear ............................. .
,MM54HCT299/MM74HCT299 8-Bit TRI-STATE Universal Shift Register ................... .
MM54HCT323/MM74HCT323 8-Bit TRI-STATE Universal Shift Register ................... .
MM54HCT373/MM74HCT373 TRI-STATE Octal D-Type Latch ..........................•.
MM54HCT374/MM74HCT374 TRI-STATE Octal D-Type Flip-Flop ......................... .
MM54HCT521/MM74HCT521 8-Bit Magnitude Comparator(Equality Detector) ............ .
MM54HCT533/MM74HCT533 TRI-STATE Octal D-Type Latch ............................ .
MM54HCT534/MM74HCT534 TRI-STATE Octal D-Type Flip-Flop ......................... .
MM54HCT540/MM74HCT540 Inverting Octal TRI-STATE Buffer ......................... .
MM54HCT541/MM74HCT541 Inverting Octal TRI-STATE Buffer ......................... .
MM54HCT563/MM74HCT563 TRI-STATE Octal D-Type Latch with Inverted Outputs ......... .
MM54HCT564/MM74HCT564 TRI-STATE Octal D-Type Flip-Flop with Inverted Outputs ...... .
MM54HCT573/MM74HCT573 TRI-STATE Octal D-Type Latch ............................ .
MM54HCT574/MM74HCT574 TRI-STATE OctalD-Type Flip-Flop ........................ .
MM54HCT590/MM74HCT590 8-Bit Binary Counter with TRI-STATE Output Register ........ .
MM54HCT592/MM74HCT592 8-Bit BinaryCounterwith Input.Register ................... .
MM54HCT593/MM74HCT593 8-Bit Binary Counter with Bidirectional Input
Register/CounterOutputs ..................................................... .
MM54HCT640/MM74HCT640 Inverting Octal TRI-STATE Transceiver ..................... .
MM54HCT643/MM74HCT643 True-Inverting Octal TRI-STATETransceiver ................. .
MM54HCT688/MM74HCT688 8-Bit Magnitude Comparator(Equality Detector) ............ .
4·3
4-5
4-7
4-9
4-12
4-15
4-18
4-21.
4-24
4-21
4-27
4-30
4-33
4-36
4-39
4-39
4-43
4-46
4-52
4-57
4-57
4-57
4-61
4-65
4-68
4-71
4-73
4-75
4-75
4-80
4-83
4-83
4-88
4-88
4-91
4-94
4-97
4-100
4-103
4-105
4-105
4-108
4-108
4-111
Ell
lI?'A National
~ Semiconductor
PRELIMINARy.......
r-'
"--'"
\
)
microCMOS
MM54HCTOO/MM74HCTOO
Quad 2 Input NAND Gate
General Description'
The MM54HCTOO/MM74HCTOO are NAND gates fabricated
using microCMOS Technology, 3.0 micron silicon gate Nwell CMOS, which provides the inherent benefits of
CMOS-low quiescent power and wide power supply range.
These devices are input and output characteristic and pinout compatible with standard DM54LS174LS logic families.
All inputs are protected from static discharge damage by
internal diodes to Vee and ground.
devices. These parts are also plug-in replacements for LSTTL devices and can be used to reduce power consumption
in existing designs.
Features
•
•
•
•
MM54HCTIMM7 4HCT devices are intended to interface between TTL and NMOS components and standard CMOS
TTL, LS pin-out and threshold compatible
Fast switching: tpLH, tpHL = 14 ns (typ)
Low power: 10 p.Wat DC
High fan out, 10 LS-TTL loads
Connection and Logic Diagrams
Dual-In-Line Package
A4
Y4
83
Y3
8
'.
A1
TUF/5356-1
Top View
Order Number MM54HCTOOJ or MM74HCTOOJ, N
See NS Package J14A or N14A
(1 of 4 gates)
TLIF/5356-2
4-5
Absolute Maximum Ratings (Notes 1 & 2)
-0.5 to + 7.0V
Supply Voltage (Vee)
DC Input Voltage (VIN)
-1.5 to Vee+ 1.5V
~0.5 to Vee + 0.5V
DC Output Voltage (VOUT)
±20mA
Clamp Diode Current (11K, 10K>
DC Output Current, per pin (lOUT)
±25mA
±50mA
DC Vee or GND Current, per pin (Ieel
-65'Cto + 150"C
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
500mW
260'C
Lead Temp. (T (Soldering 10 seconds)
Operating Conditions
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TA>
MM74HCT
MM54HCT
Symbol
5.5
Units
V
0
Vee
.V
-40
-55
+85
+125
'c
500
ns
'C
Vee=5V ±10% (unless otherwise specified)
TA=25'C
Conditions
Parameter
. Max
Input Rise or Fall Times
(t" ttl
u
DC Electrical Characteristics
Min
4.5
74HCT
TA= -40 to 85'C
Typ
54HCT
TA= -55to 125"C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0
2.0
2.0
V
VIL
Maximum Low Level
Input Voltage
0.8
0.8
0.8
V
VOH
Minimum High Level
Output Voltage
Vee- 0.1
3.7
4.7
V
V
V
0.1
0.4
0.4
V
V
V
Maximum Low Level
Voltage
VOL
VIN=VIH orVIL
IIOUTI = 20 ",A
IIOUTI=4.0 mA, Vee=4.5V
IIOUTI=4.8 mA, Vee=5.5V
Vee
4.2
5.2
Vee- 0.1
3.98
4.98
VIN=VIH
IIOUTI=20",A
IIOUTI=4.0 mA, Vee=4.5V
IIOUTI=4.8 mA, Vee=5.5V
0
0.2
0.2
0.1
'0.26
0.26
0.1
0.33
0.33
. Vee- 0.1
3.84
4.84
,
I
liN
Maximum Input
Current
VIN=VecorGND,
VIH orVIL
±0.1
±1.0
±1.0
",A
.Icc
Maximum Quiescent
Supply Current
VIN = Vee or GND,
IOUT=O",A
2.0
20
40
p.A
VIN = 2.4V or 0.5V (Note 4)
mA
AC Electrical Characteristics Vee = 5.0V; t,= t,=6 ns, CL = 15 pF, TA = 25'C (unless otherwise noted)
Symbol
tPLH, tpHL
L
I
I
Parameter
Maximum Propagation Delay
Conditions
I
I
I
Typ
12
I
Guaranteed Umlt
I
J
I
18
Units
ns
AC Electrical Characteristics Vee=5.0V± 10%, t,=t,=6 ns, CL = 50 pF (unless otherwise noted)
,
Symbol
Parameter
Conditions
TA=25'C
Typ
74HCT
TA= -40 to 85'C
54HCT
TA=-55to 125'C
tpLH, tpHL
Maximum Propagation Delay .
14
20
25
30
tTHL, tTLH
Maximum Output Rise & Fall Time
8
15
19
22
Cpo
Power Dissipation Capacitance
CIN
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
(Note 5)
20
Units
Guaranteed Limits
ns
ns
pF
10
pF
Input Capacitance
5
10
10
Absolute Maximul\1 Ratings are those values beyond which damage to the device may occur.
Unless otherwise specified all voltages are referenced to ground.
Power Dissipation temperature derating - plastic "N" package: -12 mW I'C from 6S'C to 8S'C; ceramic "J" package: -12 mWrc from 1OO'C to 125'C.
This is measured per input with all other Inputs held at Vee or ground:
Cpo determines the no load dynamic power consumption. Po = Cpo Vec21+ Icc Vee. and the no load dynamic current consumption. Is = Cpo Vee f + lee.
4·6
.
~ Semiconductor
~National
PRELIMINARY
\
MM54HCT04/MM74HCT04 Hex Inverter
General Description
Features
The MM54HCT04/MM74HCT04 are logic functions fabricated by using microCMOS Technology, 3.0 micron silicon
gate N-well CMOS, which provides the inherent benefits of
CMOS - low quiescent power and wide power supply range,
but are input and output characteristic as well as pin-out
compatible with standard DM54LS174LS devices. The
MM54HCT04/MM74HCT04, triple buffered, inverting hex inverters, feature low power dissipation and fast switching
times. All inputs are protected from static discharge by internal diodes to Vee and ground.
MM54HCTIMM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS
devices. These parts are also plug-in replacements for LSTTL devices and can be used to reduce power consumption
in existing designs.
..
•
•
•
•
TTL. LS pin-out and threshold compatible
Fast switching: tpLH, tpHL = 12 ns (typ)
Low power: 10 p.W at DC. 2.5 mWat 5 MHz
High fanout: ~ 10 LS loads
Inverting. triple bufferE!d
Connection Diagram
A6
13
1
Al
2
VI
va
AS
12
11
rJ>o-
1>0-
--;
microCMOS
VS
A4
10
9
V4
8
r{>o-
3
4
S
6
17
A2
V2
A3
V3
GND
Top View
Order Number MM54HCT04J or MM74HCT04J,N
See NS Package J14A or N14A
4-7
TL/F/5357-1
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditic:ms
-0.5 to + 7.0V
Supply Voltage (Vee>
DC Input Voltage (VIN)
-1.5toVee+ 1•5V
Supply Voltage (Vee)
DC Output Voltage (Vour)
-0.5 to Vee + 0.5V
DC Input or Output Voltage
±20mA
Clamp Diode Current (11K. 10K>
DC 0\ltput Current. per pin (lour)
±25mA
DC Vee or GND Current. per pin (lee)
±50mA
Storage Temperature Range (T8TG)
Operating Temp. Range (TAl
MM74HCT
MM54HCT
500mW
Lead Temp. (TtJ (Soldering 10 seconds)
Max
5.5
Units
V
0
Vee
V
-40
-55
+85
+125
'C
'C
500
ns
(VIN.Vour)
-65'C to + 150'C
Power Dissipation (Po) (Note 3)
Min
4.5
Input Rise or Fall Times
(tr• tf)
260'C
DC Electrical Characteristics Vee=5V ±10% (unless otherwise specified)
Symbol
TA=25'C
Conditions
Parameter
Typ
74HCT
TA= -40 to 85'C
;
54HCT
TA= -55to l25'C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0
2.0
2.0
V
VIL
Maximum Low Level
Input Voltage
0.8
0.8
0.8
V
VOH
Minimum High Level
Output Voltage
Vee- O.l
3.84
4.84
Vee- 0.1
3.7
4.7
V
V
V
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
VOL
liN
lee
,
VIN=VIL
0ur l=20P.A
l'lour
=4.0 mAo Vee = 4.5V
,lour=4.8mA.Vee=5.5V
Maximum Low Level
Voltage
VIN=VIH
Maximum Input
Current
VIN=VeeorGND.
VIHorVIL
±0.1
±1.0
±1.0
p.A
Maximum Quiescent
Supply Current
VIN=VeeorGND
lour=Op.A
2.0
20
40
p.A
.
l'0urj=20/LA
lour =4.0mA. Vee=4.5V
lour =4.8 mAo Vee=5.5V
0
0.2
0.2
VIN = 2.4V or 0.5V (Note 4)
AC Electrical Characteristics
Symbol
Parameter
tpLH. tpHL
Maximum Propagation
Delay
Parameter
mA
Vee = 5.0V. tr = tf = 6 ns CL = 15 pF. T A = 25'C (unless otherwise noted)
Conditions
AC Electrical Characteristics
Symbol
Vee ' Vee-OJ
4.2
3.98
5.2
4.98
Typ
Guaranteed
Limit
Units
10
18
ns
Vee=5.0V± 10%.Ir=tf=6 ns. CL =50 pF (unless otherwise noted)
Conditions
TA=25'C
Typ
74HCT
TA=-40t085'C
54HCT
TA= -55 to l25'C
tpLH. tpHL
Maximum Propagation Delay
14
20
25
30
trHL. trLH
Maximum Output Rise & Fall Time
8
15
19
22
Cpo
Power Dissipation Capacitance
(Note 5)
20
Units
Guaranteed Limits
ns
ns
pF
Input Capacitance
pF
5
10
10
10
CIN
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all vo~age. are referenced to ground,
Note 3: Power Dissipation temperature derating - plastic "N" pacllage: -12 mW re' from 65'C to B5'C; ceramic "J" packaga: -12 mWI'C from 100'C to 125'C.
Note 4: This is measured per input with all other inputs held at Vee or ground.
Note 5: CPO determines the no load dynamic power consumption. Po =Cpo Vc;c2 1+ lee Vee. and the no load dynamic current consumption, Is =Cpo Vee f + Icc.
" .
4-8
'?'A National
~ Semiconductor
PRELIMINARY
\
")
microCMOS
MM54HCT05/MM74HCT05
Hex Inverter (Open Drain)
General Description
MM54HCTIMM7 4HCT devices are intended to interface between TIL and NMOS components and standard CMOS
devices. These parts are also plug-in replacements for LSTIL devices and can be used to reduce power consumption
in existing designs.
The MM54HCT05/MM74HCT05 are logic functions fabricated by using microCMOS Technology, 3.0 micron silicon
gate N-well CMOS, which. provides the inherent benefits of
CMOS-low quiescent power and wide power supply range.
These devices are also input-output characteristically and
pin-out compatible with standard DM54LS/DM74LS logic
families. The MM54HCT05/MM74HCT05 open drain Hex
Inverter requires the addition of an external resistor to perform a wire-NOR function.
All inputs are protected from static discharge damage by
internal diodes to Vee and ground.
Features
•
•
•
•
Open drain for wire-NOR function
LS-TIL pinout and threshold compatible
Fanout of 10 LS-TIL loads
Typical propagation delays:
tpLH (with 1 kO resistor) 10 ns
tpHL (with 1 kO resistor) B ns
Connection Diagram
Dual·ln·Llne Package
Vee
14
AI
13
Y6
12
A5
A4
Y5
11
Y4
8
10
III
2
M
n
3
~
6
4
~
~
~
7
~
TLIFI5358-1
Top View
Order Number MM54HCT05J or MM74HCT05J, N
See NS Package J 14A or N14A
Logic Diagram
Typical Application
Vee:
_
h- _
~, _,:m
A~8
TLIFI5358-3
Note: Can be extended to more than 2 inputs.
4-9
Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage (Vee)
Operating Conditions
-0.5 to + 7.0V
DC Input Voltage (VIN)
-1.5 to Vee + 1.5V
DC Output Voltage (VOUT)
-0.5 to Vcc+ 0.5V
Clamp Diode Current (11K, 10Kl
±20mA
DC Output Current, per pin (lOUT)
±25mA
DC Vee or GND Current, per pin (lee)
±50mA
Storage Temperature Range (T8TG)
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TAl
MM74HCT
MM54HCT
Input Rise or Fall Times
(It-, tf)
-65·Cto + 150·C
Power Dissipation (Po) (Note 3)
Min
4.5
0
Max
5.5
Vee
Units
V
V
-40
-55
+B5
+125
·C
·C
500
ns
500mW
Lead Temperature (TJ
(Soldering 10 seconds)
260"C
DC Electrical Characteristics
Symbol.
Parameter
(Vee = 5V ~ 10%, unless otherwise specified)
TA=2S·C
Conditions
Typ
74HCT
TA=-40to85"C
S4HCT
TA=-SSto125"C .Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0
2.0
2.0
V
VIL
Maximum Low Level
Input Voltage
O.B
O.B
O.B
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL, RL = 1 kO
IIOUTI=20 p.A
Vee
Vcc- 0.1
Vcc- 0.1
Vee- 0.1
V
VOL
Maximum Low Level
Voltage
VIN=VIH
IIOUTI=20 p.A
ilOUTI=4.0 rnA, Vcc=4.5V
IIOUTI=4.8 rnA, Vcc=5.5V
0
0.2
0.2
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
liN
Maximum Input
Current
VIN = Vee or GND,
VIHorVIL
±0.1
±1.0
±1.0
p.A·
ILKG
Minimum High Level
Output Leakage
Current
VIN=VIH orVIL, VOUT=Vee
0.5
5.0
10
p.A
Icc
Maximum Quiescent
Supply Current
VIN = Vee or GND
IOUT=Op.A
2.0
20
40
p.A
rnA
VIN=2.4VorO.5V
(Note 4)
Note 1: Absolute Maximum Ratings are thoss values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Pawsr Dissipation temperature derating - plastic uN u package: -12 mWrc from 65"C to 85"C: ceramic uJu package: -t2 mWrc from 1OO"C to t25"C.
Note 4: This Is measured per input with all other Inputs held at vee or ground.
4·10
AC Electrical Characteristics
Symbol
Parameter
Vee = 5V, TA = 25°C, CL = 15 pF, tr=tf= 6 ns unless otherwise noted.
Conditions
Typ
Guaranteed
Limit
Units
tpHL
Maximum Propagation Delay
RL =1 kn
8
15
ns
tpLH
Maximum Propagation Delay
RL=1 kn
9
16
ns
AC Electrical Characteristics
~ymbol
Parameter
Vee = 5V ± 10%, CL = 50 pF, Ir= tf= 6 ns unless otherwise specified
Conditions
TA=25°C
Typ
74HCT
TA= -40 to 85°C
54HCT
TA= -55 to 125°C
Units
Guaranteed Limits
tpHL
Maximum Propagation
Delay
RL =1 kn
10
22
28
33
ns
tpLH
Maximum Propagation
Delay
RL =1 kn
12
20
25
30
ns
tTHL
Maximum Output
Fall Time
10
15
19
22
ns
CpO
Power Dissipation
Capacitance (Note 5)
CtN
Maximum Input
Capacitance
(per gate)
RL=oo
20
5
pF
10
10
pF
Note' 5: CpO detennines the no loed dynamiC power consumption. Po= CPO Vc;c2 1+ lee Vee. and the no load dynamic current consumption. Is = Cpo Vee 1+ Icc.
,
4·11
co
r-----------------------------------------------------------------------------,
~ ~National
.
.... ~ Semiconductor
:::&i
PRELIMINARY
:c
'0:1'
:::&i
.....
~
:c
"
)
microCMOS·
MM54HCT08/MM74HCT08 .
Quad 2-lnput AND Gate
'0:1'
II)
:::&i
:::&i
General Description
The MM54HCT08/MM74HCT08 are logic functions fabricated by using microCMOS Technology, 3.0 micron silicon
gate N-well CMOS, which provides the inherent benefits of
CMOS-low quiescent power and wide power supply range.
These devices are input and output characteristic and pinout compatible with standard DM54LS174LS logic families.
All inputs are protected from static discharge damage by
internal diodes to Vee and ground.
MM54HCTIMM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS
devices. These parts are also plug-in replacements for LSTTL devices and can be used to reduce power consumption
in existing designs.
Features
•
•
'.
•
TTL, LS pin-out and threshold compatible
Fast switching: tpLH, tpHL = 12 ns (typ)
Low power: 10 p.Wat DC
High fan-out, 10 LS-TTL loads
Connection and Logic Diagrams
Dual-ln-L1ne Package
84
A4
Y4
83
A3
Y3
TLlF/5754-1
Order Number MM54HCT08J or MM74HCT08J,N
See NS Package J14A or N14A
Tl)F/5754-2
4-12
Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage (Vee)
Operating Conditions
-0.5 to +7.0V
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K, 10K)
DC Outp'ut Current, per pin (lOUT)
DC Vee or GND Current, per pin (lee)
Storage Temperature Range (T8TG)
, Power Dissipation (Po) (Note 3)
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN, VOUT)
Operating Temperature Range (TAl
MM74HCT
MM54HCT
Input Rise or Fall Times
(t,., til
-1.5 to Vee + 1.5V
-0.5 to Vee +0.5V
±20mA
±25mA
±50mA
- 65·C to + 150·C
Lead Temperature (TLl (Soldering 10 seconds)
500mW
260·C
Min
4.5
0
Max
5.5
Vee
Units
V
V
-40
-55
+85
+125
·C
·C
500
ns
DC Electrical Characteristics Vee=5V ±10% (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25·C
Typ
74HCT
TA= -40 to 85·C
54HCT
TA=-55to125·C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0
2.0
2.0
V
VIL
Maximum Low Level
Input Voltage
0.8
0.8
0.8
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
IIOUTI=20 p.A
IIOUTI=4.0 mA, Vee=4.5V
IiOUTI=4.8 mA, Vee=5.5V
Vee
4.2
5.2
Vee- 0.1
3.98
4.98
Vee- 0.1
3.84
4.84
Vee- 0.1
3.7
4.7
V
V
V
Maximum Low Level
Voltage
VIN=VIH
IIOUTI=20 p.A
IIOUTI=4.0 mA, Vee = 4.5V
IIOUTI=4.8 mA, Vee=5.5V
0
0.2
0.2
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
Maximum Input
Current
VIN=VeeorGND, VIHorVIL
±0.1
±1.0
±1.0
p.A
2.0
20
40
p.A
VOL
liN
Icc
Maximum Quiescent
" Supply Current
VIN=VeeorGND
IOUT=Op.A
VIN = 2.4V or 0.5V (Note 4)
mA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
,
Note 2: Unless otherwise specified all voltages are referenced to ground.
(
Note 3: Power Dissipation temperature derating - plastic "N" package -12 mWf'C from 65'C to 85'0. ceramic "J" package 12 mW/'C from l00'e to 125"C.
Note 4: This is measured per input wilh all other inPuts held at Vee or ground.
4-13
AC Electrical Characteristics Vcc= 5.0V, tr= tj= 6 ns, CL = 15 pF, TA= 25°C
Symbol
tpLH, tpHL
I
I
Parameter
.Maximum Propagation Deiay
I
1
Conditions
I
J
TyP
12
I
1
Guaranteed LImit
20
I
I
Units
ns
. AC Electrical Characteristics Vcc=5.0V±10%,tr =tj=6ns,CL=50pF
Symbol
Parameter
Conditions
TA=2S0C
Typ
74HCT
TA= -40 to 8SoC
S4HCT
TA= -SSto 12SoC
tpLH, tpHL
Maximum Propagation Deiay
15
24
30
35
trHL, tTLH
Maximum Output Rise & Fall Time
8
15
19
22
Cpo
Power Dissipation Capacitance
CIN
Input Capacitance
(Note 5)
ns
ns
38
5
Units
Guaranteed LImits
pF
10
10
10
pF
Note 5: CPO determines the no load dynamic power consumption. Po = Cpo Vrx? 1+ Icc Vcc and the no load dynamic current consumption. IS = Cpo Vee 1+ Icc.
-
'.
4·14
~National
PRELIMINARY
~ Semiconductor
microCMOS
MM54HCT34/MM74HCT34 Non-Inverter
General Description
Features
The MM54HCT34174HCT34 are logic functions fabricated
by using microCMOS Technology, 3.0 micron silicon gate Nwell CMOS, which provides the inherent benefits of CMOS low quiescent power and wide power supply range, but are
input and output characteristic as well as pin-out compatible
with standard DM54LS174LS devices. The MM54HCT341
MM74HCT34 feature low power dissipation and fast switching times. All inputs are protected from static discharge by
internal diodes to Vee and ground.
•
•
•
•
TTL, LS pin-out and threshold compatible
Fast switching: tpLH, tpHL = B ns (lyp)
Low power: 10 p.W at DC, 2.5 mW at 5 MHz
High fanout: ;;, 10 LS loads
MM54HCTIMM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS
devices. These parts are also plug-in replacements for LSTTL devices and can be used to reduce power consumption
in existing designs.
Connection Diagram
Dual-In-Line Package,
Vcc
14
A6
Y6
13
2
A1
V1
A5
12
3
A2
11
4
V2
VS
10
5
A3
A4
9
6
V3
V4
8
7
GND
Top View
Order Number MMS4HCT34J or MM74HCT34J, N
See NS Package J14A or N14A
4-15
TLlF/5359-1
Opera'ting Conditions
Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage (Vee) ,
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K. loKI
DC Output Current; per pin (lOUT)
DC Vee or GND Current. per pin (leel
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
LE!ad Temperature (TLl
(Soldering 10 seconds)
-0.5 to + 7.0V
-1.5 to Vee + 1.5V
-0.5 to Vee + 0.5V
±20mA
±25mA
±50mA
-65·C to + 150"C
500mW
Parameter
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TAl
MM74HCT
MM54HCT
Min,·
4.5
Max
5.5
Units
V
0
Vee
V
-40
-55
+85
+125
·C
·C
500
ns
Input Rise or Fall Times
(tr• til
260"C
DC Electrical Characteristics
Symbol
Supply Voltage (Vee)
Vee = 5V ± 10% (unless otherwise specified)
TA=25"C
Conditions
Typ
74HCT
54HCT
TA= -40 to 85"C 'TA= -55to 125"C
Units
Guaranteed Limits
VIH
Minimum High Level
Inpu~ Voltage
2.0
2.0
2.0
V
VIL
Maximum Low Level
Input Voltage
0.8
0.8
0.8
V
VOH
, Minimum High Level
Output Voltage
VIN=VIL
IIOUTI = 20 p.A
IIOUTI=4.0 mAo Vee=4.5V
lIoUTI=4.8 mAo Vee=5.5V
Vee
4.2
5.2
Vee- 0.1
3.98
4.98
Vee- O.1
3.84
4.84
Vee- 0.1.
3.7
4.7
V
V
V
Maximum Low Level
Voltage
VIN=VIH
IIOUTI=20p.A
IIOUTI=4.0 mAo Vee=4.5V
IIOUTI=4.8 mAo Vee=5.5V
0
0.2
0.2
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
liN
Maximum Input
Current
VIN = Vee or GND,
VIHorVIL
±O.1
±1.0
..l,.1.V
-,-on
p.A
lee
Maximum Quiescent
Supply Current
ViN=VeeorGND.
lOUT = 0 p.A
2.0
20
40
p.A
VOL
r
.,
VIN = 2.4V or 0.5V (Note 4)
mA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified ali voltages are referenced to ground.
Note 3: P~wer Dissipation tempareture derating - plastic "N" package: -12 mWI'C from 65'C 10 85'C; ceramic "J" package: -12 inW/'C from l00'C·1o 125'C.
Note 4: This is measured par Input with ali other inputs held at Vee or ground.
.
4-16
AC Electrical Characteristics
. Symbol
Parameter
tpLH, tpHL
Conditions
Typ
Guaranteed
Limit
Units
10
20
ns
Maximum Propagation
Delay
AC Electrical Characteristics
Symbol
Vee = 5.0V, tr= tf= 6 ns, CL = 15 pF, TA= 25"C (unless otherwise noted)
Parameter
Vee= 5.0V ± 10%, tr= tf= 6 ns, CL = 50 pF (unless otherwise noted)
Conditions
TA=25"C
Typ
74HCT
TA= -40 to 85"C
54HCT
TA= -55 to 125"C
Units
Guaranteed Limits
tpLH, tpHL
Maximum Propagation Delay
10'
22
29
33
ns
tTHL, tTLH
Maximum Output Rise & Fall Time
8
15
19
22
ns
CPO
Power Dissipation Capacitance
CIN
Note 5:
Input Capacitance
(Note 5)
20
5
pF
10
10
10
pF
Is = Cpo Vee f + Icc-
Cpo determines the no load dynamic power consumption. Po = Cpo Vcr;2 f + lee Vee. and the no load dynamic current consumption.
(
4-17
r:: :J
r----------------------------------------------------------------.
~ ~National
PRELIMINARY
I:
~
~ ~ Semiconductor
:E
microCMOS
:E
~ MM54HCT74/MM74HCT74
ti Dual D Flip-Flop with Preset and Clear
:::E:
~
LI)
:E
:E
General Description
The MM54HCT74/MM74HCT74 utilizes microCMOS Technology, 3.0 micron silicon gate N-well CMOS, to achieve
,operaticm speeds similar to the equivalent LS-TTL part. It
possesses the i'Jigh noise immunity and low power consumption of standard CMOS integrated circuits, along with
the ability to drive 10 LS-TTL loads.
This flip-flop has independent data, preset, clear, and clock
inputs and 0 and Q outputs. The logic level present at the
data input is transferreq to the output during the positive-going transition of the clock pulse. Preset and clear are independent of the clock and accomplished by a low level at the
appropriate input.
The 54HCT174HCT logic family is functionally and pin-out
compatible with the standard 54LS174LS logic family. All
Connection and Logic Diagrams
inputs are protected from damage due to static discharge by
internal diode clamps to Vee and ground.
MM54HCTIMM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS
devices. These parts are also plug-in replacements for LSTTL devices and can be used to reduce power consumption
in existing designs.
Features'
•
•
•
•
•
Typical propagation delay: 20 ns
Low quiescent current 40 p.A maximum (74HCT Series)
Low input current 1 p.A maximum
Fanout of 10 LS-TTL loads
Meta-stable hardened
Truth Table
Dual-In-llne Package
ClRt
02
CW
PH2
a2
CLR
ClK
D
Q
Q
L
H
L
H
H
H
L
L
H
H
H
X
X
X
X
X
X
H
L
HO
L
H
HO
t
t
H
L
L
H
L
X
H
L
00
H
I
CLK1
01
elKl'
PHl
outputs
Inputs
PR
Qo
co
Nota:
= the level of Q before the indicated Input conditions were esiabllshed.
"This configuration Is" nonstable; that Is. H will not persist
when preset and clear InpUls return to their Inactive (high)
level.
P
GNO
TDPVlEW
TL/F/5360-1
Order Number MM54HCT74J or MM74HCT74J,N
See NS Package J14A or N14A
PR
CLR
CL
'ClK
-t>o--t>~ CL
~------~f~------~~
TLlF/5360-2
4-18
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
-O.S to + 7.0V
Supply Voltage (Veel
DC Input Voltage (VIN)
-1.S to Vee + 1.SV
Supply Voltage (Veel
DC Output Voltage (Vour)
-o.S io Vee+O.SV
DC Input or Output Voltage
(VIN, Vour)
Operating Temp. Range (Till
MM74HCT
MMS4HCT
Clamp Diode Current (11K, 10K)
±20mA
DC Output Current, per pin (lour)
±2SmA
DC Vee or GND Current, per pin (Ieel
±SOmA
-6S·Cto +1S0·C
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
Lead Temp. (TO (Soldering 10 seconds)
Min
4.S
Max
S.S
Units
V
0
Vee
V
-40
-SS
+8S
+12S
·C
·C
SOO
ns
Input Rise or Fall Times
(tr, til
SOO,mW
260·C
DC Electrical Characteristics Vee = sv ± 10% (unless otherwise specified)
Symbol
Parameter
Conditions
TA=2S·C
Typ
74HCT
TA= -40 to 85"C
54HCT
TA= -55to 125·C
Units
Guaranteed LImits
VIH
Minimum High Level
Input Voltage
2.0
2.0
2.0
V
VIL
Maximum Low Level
Input Voltage
0.8
0.8
0.8
V
VOH
Minimum High Level
0\ltput Voltage
VIN = VIH or VIL
lIourl = 20 p.A
Ilourl=4.0 mA, Vee=4,SV
liourl = 4.8 mA, Vee = S.SV
Vee
4.2
S.2
Vee- 0.1
3.98
4.98
Vee- 0.1
3.84
4.84
Vec- 0.1
3.7
4.7
V
V
V
Maximum Low Level
Voltage
VIN=VIH orVIL
Ilourl=20 p.A
Ilourl=4.0 mA, Vec=4.SV
Ilourl=4.8 mA, Vcc=S.SV
0
0.2
0.2
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
liN
Maximum Input
Current
VIN=VCcorGND,
VIHorVIL
±0:1
±1.0
±1.0
p.A
Icc
Maximum Quiescent
Supply Current
VIN=VeeorGND
lour=O p.A
4.0
40
80
p.A
VIN=2.4VorO.SV (Note 4)
0.3
0.4
O.S
mA
VOL
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic UN" package: -12 mW'"C from 65"C to 85"C; ceramic "J" package: -12 mWI"C from 100"'(; to 125"C.
Note 4: This is measured per pin. All other inputs are held at Vee Ground.
4·19
•
AC Electrical Characteristics Vcc=5V. TA=25'C.CL =15pF.t,.=tf=6ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
, Units
fMAX
Maximum Operating
Frequency from Clock
toQorQ
50
30
MHz
tpHL. tpLH
Maximum Propagation
Delay Clock to Q or Q
18
30
ns
tpHL. tpLH
Maximum Propagation
Delay from Preset or
Clear to Q or Q
18
'30
ns
tREM
Minimum Removal Time.
Preset or Clear to Clock
20
ns
1$
Minimum Setup Time
Data to Clock
20
ns
tH
Minimum Hold Time
Clock to Data
-3
0
ns
tw
Minimum Pulse Width
Clock. Preset or Clear
8
16
ns
,
AC Electrical Characteristics Vcc= 5.0V ±10%. CL = 50 pF. tr= tf= 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25"C
Typ
fMAX
Maximum Operating
Frequency
27
tpHL. tpLH
Maximum Propagation
Delay from Clock to
QorO
21
35
tpHL. tpLH
Maximum Propagation
Delay from Preset or
Clear to Q or 0
21
iREM
74HCT
TA=-40t085"C
54HCT
TA= -55to 12sOC
Guaranteed Limits
21 '
Units
18
MHz
44
52
ns
35
44
52
I'IS
Minimum Removal TIme
Preset or Clear to Clock
20
25
30
ns
1$
Minimum Setup Time
Data to Clock
20
25
30
ns
tH
Minimum Hold Time
Clock to Data
-3
0
0
0
ns
tw
Minimum Pulse Width
Clock. Preset or Clear
9
16
20
24
ns
tr• tf
Maximum Clock Input
Rise and Fall TIme
500
500
500
ns
tTHL. trLH
Maximum Output
Rise and Fall Time
15
19
22
ns
CPO
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input
Capacitance
(per flip-flop)
pF
30
5
10
10
10
Note 5: Cpo determines the no load dynamic power consumption, Po = CPO Vcc2 1+ ICC Vee;. and the no load dynamic current consumption, IS = CPO Vcc
4-20
, pF
,+ ICC.
'?A National
PRELIMINARY
,..~
r---
~ Semiconductor
"-A
\.
")
microCMOS
MM54HCT76/MM74HCT761
MM54HCT112/MM74HCT112
Dual J-K Flip-Flops with Preset and Clear
General Description
These flip-flops utilize silicon gate microCMOS technology.
They have input threshold and output drive similar to LSTTL with the low standby power of CMOS.
These flip-flops have independent J, K, preset, cleat and
clock inputs and
and
outputs. The flip-flops are edgetriggered and change state on the negative-going transition
of the clock pulse. Preset and clear are independent of the
clock and accomplished by a low logic level on the corresponding input.
All inputs to this device are protected from damage due to
electrostatic discharge by diodes to Vee and ground.
a
a
MM54HCT/MM74HCT devices are intended to interface
. TTL and NMOS components to CMOS components. When
there is a LS-TTL equivalent, these parts can be used as
plug-in replacements to reduce system power consumption
in existing designs.
Features
• Typical propagation delay: 20 ns
• Low quiescent current: 80 /LA maximum (74HCT series)
• Fanout of 10 LS-TTL loads
Connection Diagram
K1
Dual·ln·line Package
GND
K2
02
01
J2
01
16
III
ClK 1 PR 1
ClR 1
J1
VCC ClK 2
PR 2
ClR 2
TUF/5762-1
Order Number MM54HCT76J, MM74HCT76J,N, MM54HCT112J or MM74HCT112J,N
See NS Package J16A or N16E
Truth Table
Inputs
Outputs
PR
ClR
ClK
J
K
Q
Q
L
H
L
H
H
H
H
H
L
L
H
H
H
X
X
X
X
X
X
X
X
X
H
L
H*
L
H
H*
J.
J.
J.
J.
L
H
L
H
L
L
00
H
X
H
H
H
H
H
X
ao
H
L
H
L
Toggle
00
ao
Note: CO = the level of Q before the indicated Input conditions were established.
·This configuration is nonstable; that is, it will not persist when preset and
clear inputs return to their inactive (high) level.
'
4-21
I
Absolute Maximum Ratings (Notes 1 and 2)
Supply Voltage (Vecl
-0.5Vto +7.0V
DC Input Voltage (VIN)
-1.5Vto Vee + 1:5V
-0.5Vto Vee+0.5V
DC Output Voltage (VOUT)
±20mA
Clamp Diode Current (11K, 10K>
±25mA
DC Output Current, per Pin (lOUT)
DC Vee or GND Current, per Pin (lee)
±50mA
-65·C to + 150·C
Storage Temperature Range (TSTG)
500mW
Power Dissipation (Pol (Note 3)'
Lead Temperature (Tu
(Soldering, 10 seconds)
2600C
Operating Conditions
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TAl
MM74HCT
MM54HCT
Input Rise or Fall Times
(t,., tf)
Min
4.5
Max
5.5
Units
V
0
Vee
V
-40'
-55
+85
+125
·C
·C
500
ns
DC Electrical Characteristics Vee = 5V ± 10% unless otherwise specified
Symbol
Parameter
Conditions
74HCT
TA= -40·C to 85·C
TA=25·C
Typ
VIH
Minimum High
Level Input
Voltage
2.0
VIL
Maximum Low
Level Input
Voltage
Minimum High
Level Output
Voltage
0.8
VOH
VOL
-
Maximum Low
Level Voltage
54HCT
TA= -55·Cto 125·C
Guaranteed Limits
2.0
Units
2.0
V
0.8
0.8
V
VIN=VIH orVIL
!,OUTI = 20 p.A
•
lOUT =4.0 mA, Vee=4.5V
lOUT =4.8 mA, Vee=5.5V
Vee
4.2
5.2
Vee- 0.1
3.98
4.98
Vee- O.1
3.84
4.84
Vee- 0.1
3.7
4.7
V
V
V
VIN = VIH or VIL
IIOUTj = 20 IJoA
lOUT =4.0 mA, Vee=4.5V
lOUT =4.8 mA, Vc.e=5.5V
0
0.2
0.2
0.1
0.26
0.26
±0.1
0.1
0.33
0.33
±1.0
0.1
0.4
0.4
±1.0
V
V
V
Maximum Input
Current
Maximum
Quiescent
Supply Current
VIN=VeeorGND,
IJoA
VIHorVIL
4.0
40
80
lee
VIN=Vee!?rGND
IJoA
IOUT=O p.A
VIN=2.4VorO.5V (Note 4)
mA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specifiSd all vollsges are referenced to ground.
Note 3: Power dissipation temperature derating-plastic "N" package: -12 mWl'e from 65"C to 8S'C; ceramic "J" package: -12 mWI'e from 1OO'C to 12S'C.
Note 4: Measured per pin, all other inputs held at Vee or GND.
liN
AC Electrical Characteristics Vee = 5V, TA = 25~C, CL = 15 pF, tr= tf= 6 ns
Typ
Guaranteed
Limit
Units
Maximum Operating Frequency
50
30
MHz
18
30
tpHL, tpLH
Maximum Propagation Delay from Clock to Q or Q
Maximum Propagation Delay from Preset or Clear
toQorQ
18
30
20
ns
10
-3
20
ns
0
16
ns
ns
Symbol
fMAX
tpHL, tpLH
-
Parameter
tREM
Minimum Removal Time; Preset or Clear to Clock
Is
Minimum Set-Up Time J or K Clock
tH
Minimum Hold Time Clock to J or K
Minimum Pulse Width Clock, Preset or Clear
tw
Conditions
8
4-22
ns
~
ns
AC Electrical Characteristics Vee = 5V ± 10%. CL = 50 pF. tr= tf= 6 ns unless otherwise specified
Parameter
Symbol
Conditions
74HCT
TA= -40'C to 85'C
TA=25'C
Typ
fMAX
Maximum Operating
Frequency
tpHL. tpLH
Maximum Propagation
Delay from Clock to Q
ora
tpHL.tpLH
Maximum Propagation
Delay from Preset or
Clear to Q or a
tREM
Minimum Removal
Time Preset or Clear to
Clock
Minimum Setup Time
ts
54HCT
TA= -55'Cto 125'C
Units
Guaranteed Limits
27
22
18
MHz
22
35
44
52
ns
22
35
44
52
ns
20
25
30
ns
10
20
25
30
ns
-3
0
0
0
ns
J or K to Clock
tH
Minimum Hold Time
Clock to J or K
tw
Minimum Pulse Width
Clock. Preset or Clear
16
20
24
ns
tr• tf
Maximum Clock Input
Rise and Fall Time
500
500
500
ns
tTHL. tTLH
Maximum Output Rise
and Fall Time
15
19
22
ns
Cpo
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input
Capacitance
pF
(Per Flip-Flop)
10
5
10
pF
10
!
Note 5: CPO determines the no load dynaamic power consumption. Po~Cpo VecJ f+lce Vee. and the no load dynamic current consumption. Is~Cpo Vee
f+lee·
Logic Diagram
......
Q
CL
J
Ii
Q
-L
PR---oi>
::::r
-
K
CLR
"rh-~~
illT
.
T
Ci:
Ci:
...L
,
illy
y
TCL
cr
CLK~CL
T
......
ii
TLlF/5762-2
4-23
~ Semiconductor
PRELIMINARY
~National
--
A......
J1.-A.
')
\
microCMOS
MM54HCT1 09/MM7 4HCT1 09
Dual,J-K Flip-Flops with Preset and Clear
General Description
These high speed J-R FLIP-FLOPS utilize microCMOS
Technology, 3.0 micron silicon gate N-well CMOS. They
possess the low power consumption and high noise immunity of standard CMOS integrated circuits, along with the abili. ty to drive 10 LS-TIL loads.
.,
Each flip flop has independent J, R, PRESET, CLEAR, and
CLOCK inputs and
and
outputs. These devices are
edge sensitive to the clock input and change state on the
positive going transition of the clock pulse. Clear and preset
are independent of the clock and accomplished by a low
logic level on the corresponding input. '
a
a
MM54HCTIMM74HCT devices are intended to interface between TIL and NMOS components and standard CMOS
devices. These parts are also plug-in replacements for LSTIL devices and can be used to reduce power consumption
in existing designs.
Features
•
•
•
•
Typical propagation delay: 20 ns
Low input current: 1 jJ-A maximum
Low quiescent current: 40 jJ-A maximum (74HCT Series)
Output drive capability: 10 LS-TIL loads·
The 54HCT174HCT logic family is functionally as wen as
pin-oot compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to Vee and ground.
Connection and Logic Diagrams
Function Table
Dual-In-Line Package
vcc
CLR 2
J2
K2
CLK 2 PR 2
Inputs
Q2
10
,
J1
K1
CLK 1 PR 1
Q1
61,
PR
CLR
CLK
J
K
L
H
L
H
L
L
X
X
X
X
X
X
H
L
HO
L
H
HO
H
H
t
X
X
X
L
H
H
L
L
L
H
H
H
H
Q
Q
H
H
t
t
t
H
L
H
H
ao
Co
H
H
H
L
X
X
L
00
TOGGLE
ao
Order Number MM54HCT109J or MM74HCT109J,N
See NS Package J16A or N16E
8
CLR 1
Outputs
Q2
ONO
TLlF/5361-1
Q
J
_.r'"'_
CL
~
ill
-,-
0--,.._
a
_.r'"'_
r
C[
ii -",,-_
cr
.L
ill
,-
CL
r
CL
CLK~c[
Q
TL/F/5361-2
4-24
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
-0.5 to +7.0V
Supply Voltage (VeC>
DC Input Voltage (V,N)
-1.5toVee+ 1.5V
Supply Voltage (Vee)
DC Output Voltage (VOUT)
-0.5 to Vee+ 0.5V
DC Input or Output Voltage
(V'N, VOUT)
Operating Temp. Range (TAl
MM74HCT
MM54HCT
Clamp Diode Current (1,K, 10K>
DC Output Current, per pin (lOUT)
±20mA
±25mA
DC Vcc or GND Current, per pin {IcC>
±50mA
-65·Cto + 150·C
Storage Temperature Range (TSTG)
Lead Temperature (TLl
(Soldering 10 seconds)
Max
5.5
Units
V
0
Vee
V
-40
-55
+85
+125
·C
·C
500
ns
Input Rise or Fall Times
(tr, ttl
500mW
Power Dissipation (Po) (Note 3)
Min
4.5
260·C
I
DC Electrical Characteristics Vee=5V ±10% (unless otherwise specified)
Symbol
Parameter
Conditions
TA=2S·C
74HCT
TA= -40 to 8S·C
S4HCT
TA=-SSt012S·C
Units
Guaranteed Limits
Typ
V,H
Minimuni High Level
Input Voltage
2.0
2.0
2.0
V
V,L
Maximum Low Level
Input Voltage
0.8
0.8
0.8
V
VOH
Minimum High Level
Output Voltage
V'N = V'H or V'L
IIOUTI =20 /LA
IloUTI =4.0 mA, Vee=4.5V
IIOUTI=4.8 mA, Vee=5.5V
Vee
4.2
5.2
Vee- 0.1
3.98
4.98
Vee- O.1
3.84
4.84
Vee- O.1
3.7
4.7
V
V
V
Maximum Low Level
Voltage
V'N = V,H or V'L
IloUTI=20 /LA
IIOUTI=4.0 mA, Vee=4.5V
IIOUTI=4.8 mA, Vcc=5.5V
0
0.2
0.2
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
Maximum Input
Current
Y,N =Vee or GND,
±0.1
±1.0
±1.0
/LA
Maximum Quiescent
Supply Current
V,N=VeeorGND
lOUT = 0 /LA
4.0
40
80
/LA
VOL
"N
Icc
V,H orV'L
rnA
V'N = 2.4V or 0.5V (Note 4)
Nota 1: Absolute Maximum Ratings are those va'ues beyond which damage to the device may occur.
'Note 2: Unless otherwise specHied all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mW I"C from 6S"C to 8S"C; ceramic "J" package: -12 mW I"C from 100"C to 12S"C.
Note 4: Measured per pin. all other inputs held at Vee or GND.
4·25
AC Electrical Characteristics Vcc=5V, TA=25°C, CL =15 pF, tr =t,=6 ns
Symbol
Parameter
Conditions Typ
Guaranteed
Limit
Units
fMAX
Maximum Operating
Frequency
50
30
MHz
tpHlo tpLH
Maximum Propagation
Delay from Clock to a pr a
18
30
ns
tpHL, tpLH
Maximum Propagation
Delay from Preset or Clear to a or a
18
30
ns
tREM
Minimum Removal Time,
Preset or Clear to Clock
20
ns
ts
Minimum Setup Time
JorKClock
10
20
ns
tH
Minimum Hold Time
Clock to J or R
-3
0
ns
tw
Minimum Pulse Width
Clock, Preset or Clear
8
16
ns
i
.
AC Electrical Characteristics Vee = 5.0V ± 10%, CL = 50 pF, tr=t,= 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25°C
Typ
fMAX
Maximum Operating
Frequency
tpHlo tpLH
Maximum Propagation
Delay from Clock to
aora'
tpHL, tpLH
Maximum Propagation
Deiay from Preset
or Clear to a or a
tREM
Minimum Removal Time
Preset or Clear to Clock.
is
Minimum Setup Time
J or K to Clock
tH
Minimum Hold Time
Clock to J or R
tw
74HCT
TA=-40"to85"C
54HCT
TA=-55°to125"C
Units
Guaranteed Limits
27
22
18
MHz
22
35
44
52
ns
22
35
44
52
ns
20
25
30
ns
10
20
25
30
ns
-3
0
0
0
ns
Minimum Pulse Width
Clock, Preset or Clear
16
20
24
ns
tr, t,
Maximum Input Rise and
Fall Time
500
500
500
ns
trHL, tTLH
Maximum Output
Rise and Fall Time
15
19
22
ns
CPO
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input
Capacitance
(per flip-flop)
pF
5
10
10
10
pF
Nate 5: Cpo determines the no loed dynemic power consumption, Po = Cpo Vee2 1+ lee Vee, and the no loed dynamic current consumption, Is = Cpo Vee 1+ lee.
4·26
~------------------------------------------------------------,~
~National
~
PRELIMINARY
(II
\
~ Semiconductor
J
microCMOS
Connection Diagram
~
the 54LS138174LS138. All inputs are protected from damage due to static discharge by diodes to Vee and ground.
MM54HCT/MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS
devices. These parts are also plug-in replacements for LSTTL devices and can be used to reduce power consumption
in existing deSigns.
Features
•
•
•
•
•
TTL input compatible
Typical propagation delay: 20 ns
Low quiescent current: 80 /LA maximum (74HCT Series)
Low input current: 1 /LA maximum
Fanout of 10 LS-TTL loads
Logic Diagram
Dual-In-Une Package
OATAOUTl'UTS
Vee
116
'VO
15
VI
Y2
1.
Y3
13
V4
12
Y5
11
15 YO
V8'
10
I
14 Y1
13 Y2
,....
pl' Y4
I
2
,A
3
C,
•
5
I
mm
81
7
Y7
DUTPUT
BEIEr
1
8
BND
TDPVllW
TLlF/5362-1
Order Number MM54HCT138J
or MM74HCT138J, N
See NS Package J16A, N16E
01
8
TL/F/5362-2
Truth Table
Inputs
Enable
Outputs
Select
G1 G2' C
B A YO Y1 Y2 Y3 Y4 Y5 Y6 Y7
X
H
L
H
H
H
H
H
H
H
H
X
X X X
X X X
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
H
H
L
H
H
H
H
H
H
H
Co)
i!!:
General Description
The decoders' output can drive 10 low power Schottky TTL
equivalent loads and are functionally and pin equivalent to
....~
~
MM54HCT138/MM74HCT138
3-to-8 Line Decoder
This decoder utilizes microCMOS Technology, 3.0 micron
silicon gate N-well CMOS, and are well suited to memory
address decoding or data routing applications. Both circuits
feature high noise immunity and low power consumption
usually associated with CMOS circuitry, yet have speeds
comparable to low power Schottky TTL logic.
The MM54HCT138/MM74HCT138 have 3 binary select inputs (A, B, and C). If the device is enabled these inputs
determine which one of the eight normally high outputs will
go low. Two active low and one active high enables (G1,
G2A and G2B) are provided to ease the cascading decoders.
:::c
""
H
H
H
L
H
H
H
H
H
H
'G2=G2A+G2B
H = high level L = low level X = don·. care
4-27
H H
H H
H H
H H
L ,H
H
L
H H
H H
H H
H H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
.....
:::c
""
....~
Co)
c»
Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage (Vecl
Operating Conditions
-0.5 to + 7.0V
DC Input Voltage (VIN)
-1.5toVee+ 1.5V
Supply Voltage (Vee)
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
±20mA
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HCT
MM54HCT
Clamp Diode Current (11K. loKI
DC Output Current. per pin (loUT)
±25mA
DC Vee or GND Current. per pin (Ieel
±50mA
Storage Temperature Range (T8TG)
- 65·C to + 150·C
Power Dissipation (Po) (Note 3)
Min
4.5
.0
Max
5.5
Units
V
Vee
V
-40
-55
+85
+125
·C
·C
500
ns
input Rise or Fall Times
(t,. tf)
500mW
Lead Temperature (Tu
(Soldering 10 seconds)
260·C
DC Electric::al Chara_cteristics Vee=5V ±10% (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25"C
74HCT
TA= -40 to 85·C
Typ
54HCT
TA= -55 to 125·C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0
2.0
2_0
V
VIL
Maximum Low Level
Input Voltage
0.8
0.8
0.8
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
IIOUTI = 20 /LA
IIOUTI=4.0 mAo Vcc=4.5V
IIOUTI =4.8 mAo Vee=5.5V
Vee
4.2
5.2
Vee- O.l
3.98
4.98
Vcc- 0.1
3.84
4.84
Vee- O.l
3.7
4.7
V
V
V
Maximum Low Level
Voltage
VIN=VIH orVIL
IIOUTI = 20 /LA
IIOUTI=4.0 mAo Vee=4.5V
IIOUTI =4.8 mAo Vee= 5.5V
0
0.2
0.2
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
liN
Maximum Input
Current
VIN = Vee or GND.
VIH orVIL
±0.1
±1.0
±1.0
;.tA
Icc
Maximum Quiescent
Supply Current
VIN = Vee or GND
IOUT=O /LA
8.0
80
160
/LA,
VOL
VIN = 2.4V or 0.5V (Note 4)
mA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless oth,erwise specified all voltages are referenced to ground,
Note 3: Power Dissipation temperature derating - plastic "N" Package: -12 mWloe from 65°C to 85:e; ceramic" J" package: -12 mW1°C from 1OO"G to 125"e.
Note 4: This is measured per input pin. All other inputs are held at Vee or ground.
\
.'
4-28
AC Electrical Characteristics TA = 25 C, Vcc= 5.0V, tr=t,= 6 ns, CL = 15 pF (unless otherwise specified)
D
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
20
35
ns
tpHL
Maximum Propagation Delay, A, B, or C to Output
tpLH
Maximum Propagation Delay, A, B, or C to Output
13
25
ns
tpHL
Maximum Propagation Delay, Gl to Y Output
14
25
ns
tpLH
Maximum Propagation Delay, Gl to Y Output
13
25
ns
tpHL
Maximum Propagation Delay, G2A or G2B to Y Output
17
30
ns
tpLH
Maximum Propagation Delay, G2A or G2B to Y Output
13
25
ns
AC Electrical Characteristics
Symbol
Parameter
Vcc= 5V
Conditions
± 10%, CL = 50 pF, tr =t,=6 ns (unless otherwise specified)
TA=25D C
Typ
74HCT
TA= -40 to 8SD C
S4HCT
T=-SStoI2SDC
Units
Guaranteed Limits
tpHL
Maximum Propagation Delay
A, B, or C to Output
24
40
50
60
ns
tpLH
Maximum Propagation Delay
A, S, or C to Output
18
30
38
45
ns
tpHL
Maximum Propagation Delay
Gl to Y Output
17
30
38
45
ns
tpLH
Maximum Propagation Delay
Gl to Y Output
20
30
38
45
ns
tpHL
Maximum Propagation Delay
G2A or G2B to Y Output
23
35
43
52
ns
tpLH
Maximum Propagation Delay
G2A or G2B to Y Output
18
30
38
45
ns
iTHL, tTLH
Maximum Output
Rise and Fall TIme
15
19
22
ns
CIN
Input Capacitance
5
10
10
pF
CPO
Power Dissipation
Capacitance
pF
(Note 5)
Note 5: CPO determines the no load dynamic power consumption, Po =Cpo vcr? 1+ Icc Vee. and the no load dynamic current consumption. Is = CPO vcc 1+ Icc·
.
4·29
r:: :1
mr-----------------------------------------------------------~--_.
CO)
~t!
~National
i....
MM54HCT139/MM74HCT139
Dual 2-To-4 Line Decoder
:::5
:::5
ti:::E:
•:::5
II)
:::5
PRELIMINARY
~ Semiconductor
I:
micro CMOS
General Description
The MM54HCT139/MM74HCT139 is a high speed silicongate CMOS decoder that is well suited to memory address
decoding or data routing applications. It possesses an input
threshold and output drive similar to LS-TTL and the low
standby of CMOS logic.
The device is comprised of two independent one-of-four decoders each with a single active low enable input (G1 or
G2). Data on the select inputs (A1, 81 or A2, 82) cause one
of the four normally high outputs to go low.
device is capable of driving 10 low power Schottky TTL
equivalent loads.
The MM54HCT139/MM74HCT139 is functionally and pin
equivalent to the 54LS139/74LS139 and can be used as a
plug-in replacement to reduce system power consumption
in existing systems.
Features
All inputs to the decoder are protected from damage due to
electrostatic discharge by diodes to Vee and ground. The
• Typical propagation delays: 20 ns
• Low quiescent current: 40 IJ.A maximum (74HCT Series)
• Fanout of 10 LS-TTL loads
Connection Diagram
Truth Table
Dual-In-Line Package
SELECT
DATA DUTPUTS
,
II.
lD
OUTPUT
SELECT
'HCT139
Inputs
2Y3
9
Enable
OUTPUT BUFFER
~--~LJ~--------~
OUTPUT
SELECT
•
Outputs
Select
G
B
A
YO
Y1
Y2
Y3
H
L
L
L
L
X
X
L
L
H
H
L
H
L
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
.L
H=high level, L=low level, X=don't care
OUTPUT BUFFER
ENABLE
GJ
! TL/F15363-1
Top View
Order Number MM54HCT139J or MM74HCT139J, N
See NS Package J16A or N16E
Logic Diagram
Yz MM54HCT139/MM74HCT139
ENABLE
SELECT
G---",
;:~r:;:=~Fl[)
{:_-+. . . . ~~-...
OUTPUTS
++-t-I-.J
TL/F/5363-2
4-30
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
-0.5 to +7.0V
Supply Voltage (Vee)
Supply Voltage {Veel
. -1.5 to Vee+1.5V
DC Input Voltage (VIN)
DC Output Voltage (Vour)
DC Input or Output Voltage
(VIN. Your)
Operating Temp. Range (TA)
MM74HCT
MM54HCT
-0.5 to Vee + 0.5V
20mA
Clamp Diode Current (11K. 10K>
DC Output Current. per Pin (lour)
25mA
DC Vee or GND Current. per Pin (Ieel
50mA
Storage Temperature Range (TsrG)
-65'Cto + 150'C
Max
Units
4.5
5.5
V
0
Vee
V
-40
-55
+85·
+125
C
C
500
ns
Input Rise/Fall Time
(tr• til
500mW
Power Dissipation (Po) (Note 3)
Min
Lead Temp. (TO
(Soldering 10 seconds)
300'C
DC Electrical Characteristics (Note 4)
Typ
Symbol
VIH
Parameter
Conditions
Maximum Low Level
Input Voltage
VOH
Minimum High Level VIN=VIH orVIL
Output Voltage
Ilourl=20jJ.A
Ilourl=4.0 mAo Vee=4.5V
Ilourl=4.8 mAo Vce=5.5V
Maximum Input
Current
Icc
Maximum Quiescent VIN=VeeorGND
Supply Current
10ur=0 jJ.A (Note 4)
Note 1:
Note 2:
Note<3:
Note 4:
Vee
Maximum Low Level VIN=VIH orVIL
Output Voltage
Iiourl = 20 jJ.A
Ilourl=4.0 mAo Vec=4.5V
Ilourl=4.8 mAo Vee=5.5V
liN
Guaranteed Limits
T=25'C T=25'C
Minimum High Level
Input Voltage
VIL
VOL
Vee
VIN = Vee or GND
VIN = VIH or VIL
74HCT
54HCT
Units
T= -40 to 85'C T= -55 to 125'C
V
V
2.0
2.0
2.0
0.8
0.8
0.8
V
V
Vee-· 1
3.98
4.98
Vee-·1
3.84
4.84
Vee-· 1
3.7
4.7
V
V
V
0.10
0.26
0.26
0.10
0.33
0.33
0.1
0.4
0.4
V
V
V
±0.1
±1.0
±1.0
jJ.A
4
40
80
, jJ.A
VIN = 2.4V or 0.5V
jJ.A
300
400
440
lour = 0 jJ.A (Note 4)
Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Unless otherwise specified all voltages are referenced to ground.
Power Dissipation temperature derating: plastic "N" package: -12 mW/"Ofrom 65"0 to 65"0; ceramic "J" package: -12 mW/'C from 100"0 to 125"0.
Measured per input, other inputs at Vee or GND.
,
4-31
•
AC Electrical Characteristics (Vcc, temperature and loading of LS-TTL)
Vcc=5V, TA=25°C, CL =15 pF, tr =t,=6 ns
Typ
Guaranteed
Limits
Units
Maximum Propagation
Delay, Binary Select
to any Output
18
30
ns
Maximum Propagation
Delay, Enable to any
Output
18
30
ns
Symbol
Parameter
tpLH, PHL
tpLH, PHL
Conditions
AC Electrical Characteristics
(Full range of Vcc and temperature) Vcc=5V
± 10%, CL =50 pF (unless otherwise specified)
Typ
Guaranteed Limits
TA=25°C
TA=25°C
74HCT
TA"" -40 to 8SOC
54HCT
TA=-55t0125°C
Units
Maximum Propagation Delay,
Binary Select to any Output
20
35
44
51
ns
tpLH, PHL
Maximum Propagation Delay,
Enable to any Output
21
35
44
51
ns
tTLH, THL
Maximum Output Rise
and Fall Time
9
15
19
22
ns
CpD
Power Dissipation
Capacitance
Symbol
Parameter
tpLH, PHL
Conditions
pF
Note 5
Minimum Input Capacitance
10
10
10
pF
5
CIN
Note 5: CPO determines the no loed dynamic power consumption. Po=(CPD Vee 2) f+lec Vee. and the no load dynamic curre.nt consumption.
Is=Cpo Vee f+lee·
I
,
"
I
:
4-32
JI?'A National
~ Semiconductor
microCMOS
MM54HCT149/MM74HCT149
8 Line to 8 Line Priority Encoder
General Description
This priority encoder is implemented in microCMOS Technology, 3.0 micron silicon gate N-well CMOS. It has the high
noise immunity and low power consumption typical of
CMOS circuits, as well as the speeds and output drive similar to LS-TTL.
This priority, encoder accepts input request lines, R17RIO, and outputs e lines, R07-ROO. Only one request output can be low at a time. The output that is low is dependent
on the highest priority request input that is low. The order of
priority is RI7 highest and RIO lowest. Also provided is an
enable input, RaE, which, when high, forces all outputs
high. A request output is also provided, Rap, which goes
low when any Ai is active.
e
MM54HCTIMM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS
devices. These parts are also plug-in replacements for LSTTL devices and can be used to reduce power consumption
in existing designs.
Features
•
•
•
•
•
All inputs to this device are protected from damage due to
electrostatic discharge by diodes to Vee and ground.
Typical propagation delay: 20 ns
Low quiescent current: 80 p.A maximum (74HCT Series)
Low input current: 1 p.A maximum
Fanout of 10 LS-TTL loads
Internal switched pull up resistors provided to reduce
power consumption
Connection Diagram
Dual-In-Line Package
TLIF/5364-1
Top View
Order Number MM54HCT149J or MM74HCT149J,N
See NS Package J20A or N20A
4-33
Absolute Maximum Ratings (Notes 1 & 2)
-0.5 to +7.0V
Supply Voltage (Vee>
DC Input Voltage (VIN)
-1.5 to Vee + 1.5V
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
±20rnA
Clamp Diode Current (11K. 10K)
±35-mA
DC Output Current. per pin (lOUT)
±70mA
DC Vee or GND Current. per pin (Ieel
- 65·C to + 150·C
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
500mW
Lead Temp. (TtJ (Soldering 10 seconds)
26O"C
Operating Conditions
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TAl
MM74HCT
MM54HCT
Input Rise or Fall Times
(tr. tf}
Min
4.5
0
Max
5.5
Vee
Units
V
V
-40
-55
+85
+125
·C
·C
500
ns
DC Electrical Characteristics Vee = 5V ± 10% (unless otherwise specified)
Symbol
Parameter
TA=25·C
Conditions
Typ
74HCT
54HCT
TA= -40 to 85·C TA= -55 to 125"C Units
Guaranteed Limits .
VIH
Minimum High Level
Input Voltage
2.0
2.0
2.0
V
VIL
Maximum Low Level
Input Voltage
0.8
0.8
0.8
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
IIOUTI=20 p.A
Vee Vee- 0•1
3.98
IIOUTI = 4.0 rnA. Vee = 4:5V 4.2
4.98
IIOUTI=4.8 rnA. Vee=5.5V 5.2
Vee- 0•1
3.84
4.84
Vee- 0.1
3.7
4.7
V
V
V
Maximum Low Level
Voltage
VIN = VIH or VIL
IIOUTI = 20 p.A
IIOUTI=4.0 rnA. Vee=4.5V
IIOUTI=4.8 rnA. Vee=5.5V
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
Maximum Input Current VIN = Vee or GND.
VIHorVIL
±0.1
±1.0
±1.0
p.A
Maximum Quiescent
Supply Current
8.0
80
160
p.A
VOL
liN
-lee
0
0.2
0.2
VIN=VeeorGND
IOUT=Op.A
VIN = 2.4V or 0.5V (Note 4)
rnA
Note 1: 'Absolute Maxi"1um Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise spectfled all voltages are referenced to ground.
Nota 3: Power Dissipation temperature derating - plastic "N" package: -12 mW/'e from 65"C to 85'C; ceramic "J" package: -12 mW/'C from 100'e to 125"C.
Note 4: Measured per input. other Inputs held at Vee or GND.
Truth Table
Inputs
o
,
1 234 5 6 7
XXXXXXXX
HHHHHHHH
X X X X X X X L
X X X X X X L H
XX.xXXLHH
X X X X L H H H
X X X L H H H H
X X L H H H H H
X L H H H H H H
L H H H H H H H
Outputs
RQE 0 1 2 3 4 5 6 7 RQP
H
L
L
L
L
L
L
L
L
L
HHHHHHHH
HHHHHHHH
H H H H H H H L
HHHHHHLH
HHHHHLHH
HHHHLHHH
HHHLHHHH
H H L H H H H H
H L H H H H H H
L H H H H H H H
4-34
H
H
L
L
L
L
L
L
L
L
AC Electrical Characteristics Vcc=5V, TA=25°C,CL =15pF,tr =t,=6 ns
Symbol
Typ
Guaranteed Limit
tpHL, tpLH
Maximum Propagation Delay Any Input to RQP
Parameter
Conditions
20
38
ns
tpLH, tpHL
Maximum Propagation Delay Any Input to Any Other Output
20
34
ns
Units
AC Electrical Characteristics Vcc=5V±10%, CL =50 pftr=t,=6 ns (unless otherwise specified)
Symbol
_ °
74HCT
54HCT
Conditions TA-25 C TA = -40 to 85°CTA= -55to 125°C Units
Typ
Guaranteed Limits
Parameter
tpHL, tPLH Maximum Propagation Delay RQE to any Output
17
42
52
63
ns
tpLH, tpHL Maximum Propagation Delay Rln to ROn (same Output)
18
40
50
60
ns
tTHL, tTLH Maximum Output Rise and Fall Time
Power Dissipation Capacitance
Gpo
10
15
19
22
GIN
(Note 5)
50
Maximum input Capacitance
5
ns
pF
10
10
10
pF
Note 5: CPO determines the no load dynamic power consumption. Po = Cpo Vr;c2 f+ Icc Vee. and the no load dynamic current consumption. Is = Cpo Vcc f+ Icc.
Simplified Logic Diagram
jjjj
iii&
.....
~7rLJ
V"
.....
to'"
r-t-'
~7
iii5
Ri4
-RI3
....
R05
=I
iili4
r-:~ ~
R03
=:I
R02
~
.....
.....,~
to'"
r-r
'li 7
1Ti~
'"" t:::
....
jjjj
to'"
r--t
'U
.....
~.
r--r--
u
...
to'"
ROI
.....,-t
~7
R06
R
~
.....
R07
'"" '"" >-1
'-
iiDii
iiiii .....
to'"
.>-1
.....
RQEto'"
~7
~
;:r-.;-RDP
TL/F 15364-2
4-35
~ r---------------------------------------~----------------------------------_,
~
ti
:::t:
'Oil'
I"-
:!
:!
......
~
~
ti
:::t:
'Oil'
~
:!
:!
~National
PRELIMINARY
~ Semiconductor
MM54HCT15.5/MM74HCT155
Dual 2-to-4 Line DecoderIDemultiplexers
r---
J
\
microCMOS
General Description
The MM54HCT155/MM74HCT155 is a high speed silicon
gate CMOS decoder/demultiplexer. It features dual 1-to-4
line demultiplexers with independent strobes and common
binary address inputs. When both sections are enabled by
the strobes, the common address inputs sequentially select
and route associated input data to the appropriate output of
each section. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied
to input C1 is inverted at its outputs and data applied to C2
is "non-inverted" at its outputs. The inverter following the
C1 data input permits use as a 3-to-8 line decoder, or 1-to-8
line demultiplexer, without gating.
All inputs to the decoder are protected from damage due to
electrostatic discharge by diodes to Vee and ground. The
device is capable of driving 10 loW' power Schottky TTL
equivalent loads.
'
Connection Diagram
The MM54HCT155/MM74HCT155 is functionally and pin
equivalent to the 54lS155174lS155 and can be used as a
plug-in replacement to reduce system power consumption
in existing systems.
Features
_ Applications:
Dual 2-to-4 line decoder
Dual 1-to-4 line demultiplexer
3-to-8 line decoder
1-to~B line demultiplexer
_ Typical propagation delay: 22 ns
_ low quiescent current: 80 /LA maximum (74HCT Series)
Truth Tables
2-TO-4 LINE DECODER OR 1-TO-4 LINE DEMULTIPLEXER
Dual-In-Line Package
Inputs
Select
Outputs
Strobe
Data
B
A
G1
C1
1YO
1Y1
1Y2
1-Y3
X
X
X
l
l
H
H
l
H
l
H
H
l
l
l
l
X
X
X
H
l
H
H
H
H
H
H
l
H
H
H
H
H
H
l
H
H
H
H
H
H
L
H
H
H
H
H
l
Inputs
Select
Outputs
Strobe
Data
B
A
G2
C2
2YO
2Y1
2Y2
2Y3
X
X
X
l
l
H
H
l
H
l
H
H
l
l
l
l
X
X
X
H
l
H
H
H
H
H
H
l
H
H
H
H
H
H
l
H
H
H
H
H
H
l
H
l
l
l
l
H
TLlF/5759·1
Order Number MM54HCT155J or MM74HCT155J, N
See NS Package J16A or N16E
3-TO-S LINE DECODER OR 1-TO-S LINE DEMULTIPLEXER
Inputs
Outputs
Strobe
Select
(0)
or Data
IC = inputs Cl and C2 connected together
IG=inputs G1 and G2 connected together
H = high level
L=low level
X = don't care
4-36
IC B A
IG
X XX
H
L
l
l
l
l
l
l
L
l
l
l
l
H
H
H
H
l
l
H
H
l
l
H
H
l
H
l
H
l
H
l
H
(1)
(2)
(3)
(4)
(5)
(6)
(7)
2YO 2Y1 2Y2 2Y3 1YO 1Y1 1Y2 1Y3
H
l
H
H
H
H
H
H
H
H
H
l
H
H
H
H
H
H
H
H
H
l
H
H
H
H
H
H
H
H
H
l
H
H
H
H
H
H
H
H
H
l
H
H
H
H
H
H
H
H
H
l
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
Absolute Maximum Ratings
(Notes 1 and 2)
Operating Conditions
-0.5Vto +7.0V
Supply Voltage (Vee>
DC Input Voltage (VIN)
-1.5VtoVee+ 1.5V
DC Output Voltage (Vour)
-0.5Vto Vee+0.5V
Clamp Diode Curre'nt (11K, 10K)
±20mA
DC Output Current, per Pin (lour)
±25mA
DC Vee or GND Current, per Pin (Ieel
Storage Temperature Range (TSTG)
Supply Voltage (Vee>
DC Input or Output Voltage
(VIN, Vour)
Operating Temp. Range (TA)
MM74HCT
MM54HCT
Input Rise/Fall Time
(tr, ttl
50mA
-65·Cto + 150·C
Power Dissipation (Po) (Note 3)
500mW
u
Min
4.5
Max
5.5
Units
V
0
Vee
V
-·40
-55
+85
+125
·C
·C
500
ns
Lead Temp. (T
300·C
(Soldering, 10 seconds)
DC Electrical Characteristics Vee= 5V ± 10% unless otherwi~e specified
Typ
Symbol
Parameter
Conditions
Guaranteed Limits
Vee
TA=25·C TA=25·C
74HCT
54HCT
TA= -40"C to 85·C TA= -55·C to 125·C
Units
VIH
Minimum High
Level Input
Voltage
2.0
2.0
2.0
V
VIL
Maximum High
Level Input
Voltage
0.8
0.8
0.8
V
VOH
Minimum High VIN = VIH or VIL
Level Output
Iiourl = 20 p.A
Voltage
Ilourl=4.0 mA, VQe=4.5V
Ilourl=4.8 mA, VCC=5.5V
Vee- 0.1
3.98
4.98
Vee- 0.1
3.84
4.84
Vee- 0.1
3.7
4.7
V
V
V
0.10
0.26
0.26
0.10
0.33
0.33
0.1
0.4
0.4
V
V
V
±0.1
±1.0
±1.0
p.A
8
80
160
p.A
VOL
Vee
Maximum Low VIN = VIH or VIL
Level Output
!lour I = 20 p.A
Voltage
Ilourl=4.0 mA, Vee=4.5V
!lour I =4.8 mA, Vee=5.5V
liN
Maximum
Input Current
Icc
Maximum
VIN=Vee or GND
Quiescent
lour= 0.0 p.A (Note 4)
Supply Current
VIN=2.4VorO.5V
lour= 0.0 p.A (Note 4)
VIN=VeeorGND
VIN = VIH or VIL
mA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Nole 2: Unless otherwise specnied, all voltages are referenced to ground.
Nole 3: Power dissipation temperature deratings: plastic N package: -12 mWI'C from 6S'C to 8S'C; ceramic J package: -12 mWI'C from 1OO'C to 12S'C.
Nole 4: Measured par input, other inputs at Vee or GND.
"
4-37
•
AC Electrical Characteristics
Vee. temperature and loading of LS-TTL; Vee=5V. TA=25'C. CL = 15 pF. t,=tj=6 ns
Symbol
Condlti~ns
Parameter
Typ
Guaranteed
Limits
Units
tpLH. tpHL
Maximum Propagation Delay from Inputs A. B. or C2 to any Output
'19
30
ns
tpLH. tpHL
Maximum Propagation Delay from Inputs G1 or G2 to any Output
24
35
ns
tpLH. tpHL
Maximum Propagation Delay from Input C1 to any Output
25
35
ns
AC Electrical Characteristics
Full range of Vee and temperature; Vee=5V± 10%. CL =50 pF unless otherwise specified
Typ
Symbol
Parameter
Guaranteed Limits
Conditions
T=2S'C
74HCT
T= -4!)"C to 8S'C
54HCT
T= -SS'C to 12S'C
Units
T=2S'C
tpLH. tpHL
Maximum Propagation Delay
from Inputs A. B. or C2 to
any Output
21
35
44
51
ns
tpLH. tpHL
Maximum Propagation Delay
from Inputs G1 or G2 to any
Output
26
40-
50
60
ns
tpLH. tpHL
Maximum Propagation Delay
from Input C1 to any Output
27
40
50
60
ns
tTLH. trHL
Maximum Output Rise and
Fall Time
15
19
22
ns
CPO
Power Dissipation
Capacitance
CIN
Minimum Input Capacitance
,
Note 5
10
5
pF
/
10
10
pF
Note 5: CPO determine. the no load dynamic powe, consumption. Po=Cpo Vcc2l+lcc. and the no load dynamic current consumption.ls=Cpo Vee 1+ Icc.
Logic Diagram
STROBE (?)
"~
DATA (I)
CI
SELECT (3)
B
~'OUTPUT
,
lYO
~OUTPUT
lYI
r-~ OUTPUT
1_....
1Y2
'V
~OUTPUT
IY3
SELECT (13)
A
Ib-.
.....
-
~OUTPUT
2YO
~)OUTPUT
2Y1
DATA (15)
C2
~)OUTPUT
STROBE (14)
G2
-~)OUTPUT
2Y2
2Y3
TL/F/5759-2
"
4-38
r::: \~. I
a:::
~National
PRELIMINARY
~ Semiconductor
~roc~
MM54HCT157/MM74HCT157 Quad
2-lnput Multiplexer
MM54HCT158/MM74HCT158
Quad 2-lnp'ut Multiplexer (Inverted Output)
:I:
3
~
....a:
The 54HCT/7 4HCT logic family is functionally as well as
pin-out compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to Vee and ground.
• Typical propagation delay: 14 ns data to any output
• Power supply range: 5V±10%
• Low power supply quiescent current: 80 /LA maximum
(74HCT Series)
• Fanout of 10 LS-TTL loads
• Low input current: 1 JAoA maximum
• Completely TTL compatible
Dual-in-Line Package
vce
-- --
STROBE 4A
]16
15
G
OUTPUT INPUTS
4B
14
13
4A
4B
4Y
3A
12
11
4Y
3A
3Y
lB
2
SELECT
10
2A
IV
3
4
2B
5
--- -lA
lB
INPUTS
lY
2A
"116
II
15
14
13
4B
4Y
3A
4Y
3A
2
GND
SELECT
OUTPUT
3
2A
4
2B
5
lB
lY
2A
2B
OUTPUT INPUTS
7
2Y
OUTPUT
Order Number MM54HCT157J, MM54HCT158J, MM74HCT157J, N or MM74HCT158J, N
See HS Package J16A or N16E _
Inputs
H
Strobe
Select
H
X
L
L
L
L
L
L
~
High Level, L
H
H
~
OutputY
A
X
L
H
X
X
Low Level, X
B
HCT1S7
X
X
X
L
H
L
H
H
L
L
H
L
H
H
L
~
4-39
Irrelevant
HCT1S8
P-
2Y
Top View
Function Table
II
3B
8
-- -lA
INPUTS
TUF/5741-1
Top View
lY
:lY
10
3Y
lB
OUTPUT
3B
11
12
-S
lA
2Y
OUTPUT- INPUTS
4B
'4A
G
f--
7 /8
2B
OUTPUT INPUTS
STROBE 4A
2Y
6
-- -INPUTS
vce
3Y
3B
r--s
lA
Dual-In-Llne Package
OUTPUT
3B
a:::
UI
~
:I:
...~
UI
Features
Connection Diagrams
INPUTS
~
~
General Description
These high speed QUAD 2-to-1 line data selector/multiplexers utilize microCMOS Technology, 3.0 micron silicon gate
N-well CMOS. They possess the high noise immunity and
low power consumption of standard CMOS integrated circuits, as well as the ability to drive 10 LS-TTL loads.
These devices each consist of four 2-input digital multiplexers with common select and STROBE inputs. On the
MM54HCT1571MM74HCT157, when the STROBE input is
at logical "0" the four outputs assume the values as selected from the inputs. When the STROBE input is at a logical
"1" the outputs assume logical "0". The MM54HCT158/
MM74HCT158 operates in the same manner, except that its
outputs are inverted. Select decoding is done internally resulting in a single select input only. If enabled,' the select
input determines whether the A or B inputs get routed to
their corresponding Y outputs.
."
3
18
GND
TL/F/5741-2
....ata:::
a:::
.....
~
:I:
...i~
Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage (Vee>
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K. 10K>
DC Output Current. per pin (lOUT)
DC Vee or GND Current. per pin (Icc)
Storage Temperature Range (T8TG)
Power Dissipation (Po) (Note 3)
Operating Conditions
-0.5 to + 7.0V
-1.5to Vcc+ 1.5V
-0.5 to Vcc+0.5V
±20mA
±25mA
±50mA
-65·C to + 1500C
500mW
Supply Voltage (Vecl
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TAl
MM74HCT
MM54HCT
Input Rise or Fall Times
(Ir. tl)
~
Lead Temperature (Tu
(Soldering. 10 seconds)
MIl'!
4.5
0
Max
5.5
Vcc
Units
V
V
-40
-55
+85
+125
·C
·C
500 .
ns
260·C
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
Vee
TA=2S·C
Typ
)
74HCT
TA=-40t085"C
54HCT
TA= -55 to 125"C Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0
2.0
2.0
V
VIL
Maximum Low Level
Input Voltage
0.8
0.8
0.8
V
VOH
Minimum High Level
Output Voltage
4.4
4.4
4.4
V
VOL
Maximum Low Level
Voltage
VIN = VIH or VIL
IIOUTI";20,..A
4.5V
VIN = VIH or VIL
IJouTI ";4;0 mA
IIOUTI";4.8 mA
4.5V
5.5V
4.2
5.2
3.98
4.98
3.84
4.84
3.7
4.7
V
V
VIN = VIH or VIL
IIOUTI = 20 ,..A
IIOUTI=4.0 mA
IIOUTI=4.8 mA
4.5V
5.5V
0
0.2
0.2
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
.V
VIN=VCCorGND
6.0V
±0.1
±1.0
±1.0
,..A
8.0
80
1.60
,..A
liN
Maximum Input
Current
Icc
Maximum Quiescent VIN=VCCor GND
Supply Current
10UT'=0 ,..A
VIN = 2.4V or 0.5V (Note 4)
. mA
Note 1: Absoluta Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -t2 mW/'C from 65"C to 85'C; ceramic "J" peckage: -12 mW/'C from 100'C to 125'C.
Note 4: For a power supply oI5V ±10% \he worst case output voltages (YaH. and Vou occur for HCT at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at Va:; = 5.5V and 4.5V respectivaly. (The VIH value at 5.5V Is 3.85V.) The worst case leakage current (lIN.
Icc. and lov occur for CMOS at the higher voltage and so the 6.0V values should be used.
4-40
AC Electrical Characteristics Vcc=SV, TA=2S0C, CL = 15 pF, tr =t,=6 ns
Typ
Guaranteed
Limit
Units
Maximum Propagation
Delay, Data to Output
14
20
ns
tpHL, tpLH
Maximum Propagation
Delay, Select to Output
14
20
ns
tpHL, tpLH
Maximum Propagation
Delay, Strobe to Output
12
.' 18
ns
Synibol
Parameter
tpHL, tpLH
Conditions
AC Electrical Characteristics Vee = sv ± 10%, CL = 50 pF, tr= tf= 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25°C
Vee
Typ
74HCT
TA=-40 to 85°C
54HCT
TA= -55 to 125°C
Units
Guaranteed Limits
Maximum Propagation
Delay, Data to Output
13
25
32
37
ns
tpHL, tpLH
Maximum Propagation
Delay, Select to Output
13
25
32
37
ns
tpHL, tpLH
Maximum Propagation
Delay, Strobe to Output
12
23
29
34
ns
trLH, trHL
Maximum Output Rise
and Fall Time
8
15
19
22
ns
CIN
Maximum Input
Capacitance
5
10
10
10
pF
tpHL, tpLH
CpO
Note 5:
Power Dissipation
pF
CapaCitance (Note 5)
CPO determines the no load dynamic power consumption, Po= Cpo Vcc;21+ lee Vee, and the no load dynamic current consumption, Is = Cpo Vee 1+ lee,
-
"
4·41
~
...t;
Logic' Diagrams
'HCT157
::J:
....:::E
"Oil'
:::E
......
CD
Ln
ti
i
--1
Al ~(!!2)_ _ _ _ _ _ _ _
Bl
I-_r
J(~3)_ _ _ _ _ _ _ _
A2..!(5~)------H--r
::J:
"Oil'
Ln
B2~(6!!..)-------lH.
j:::
A3 j(l!!!l)---_ _ _
:::E
:::E
rH
Ln
..-
.£(l~o)------rH
t;
B3
r:!:
Ml(1~4)---~--t-t_r_~
::J:
:::E
:::E
j:::
f(1~3)_ _ _ _ _ _ri-1~
B4 ...:.
Ln
..-
t;
::J:
(15)
--+-o'-~
STROBE 1(1:!..)....
SELECT-
"Oil'
Ln
:::E
:::E
TLlF/5741-3
'HCT158
(2)
Al
(3)
Bl
(5)
A2
(6)
B2
A3
B3
A4
B4
(11)
(10)
(14)
(13)
(15)
STROBE (1)
SELECT
TLlF/5741-4
4-42
~National
PRELIMINARY
~ Semiconductor
\ ' - -_ _
"'----1...//
microCMOS
MM54HCT164/MM74HCT164
8-Bit Serial-in/Paraliel-out Shift Register
General Description
The MM54HCT164/MM74HCT164 utilizes microCMOS
Technology, 3.0 micron silicon gate N-well CMOS. It has the
high noise immunity and low consumption of standard
CMOS integrated circuits. It also offers speeds comparable
to low power Schottky devices.
This 8-bit shift register has gated serial inputs and CLEAR.
Each register bit is a D-type master/slave flip flop. Inputs A
& B permit complete control over the incoming data. A low
at either or both inputs inhibits entry of new data and resets
the first flip flop to the low level at the next clock pulse. A
high level on one input enables the other input which will
then determine the state of the first flip flop. Data at the
serial inputs may be changed while the clock is high or low,
but only information meeting the setup and hold time requirements will be entered. Data is serially shifted in and out
of the 8-bit register during the positive going transition of the
clock pulse. Clear is independent of the clock and accomplished by a low level at the CLEAR input.
Connection Diagram
The 54HCT/74HCT logic family is functionally as well as
pin-out compatible with the standard 54LS/74LS logic famiIy. All inputs are protected from damage due to static discharge by internal diode clamps to Vee and ground.
MM54HCT /MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS
devices. These parts are also plug-in replacements for. LSTTL devices and can be used to reduce power consumption
in existing designs.
Features
•
•
•
•
•
Typical propagation delay: 20 ns
Low .quiescent current: 40 p.A maximum (74HCT Series)
Low input current: 1 p.A maximum
Fanout of 10 LS-TTL loads
TTL input compatible
Truth Table
Dual-In-Line Package
Inputs
OUTPUTS
h.
I.
13
11
10
9
;-
'K
•
1
B
~
4
3
:~A
SERIAL INPUTS
Os
5
6
Qc
109
OUTP.tITS
Outputs
...
Clear
Clock
A
B
QA
QB
L
H
H
H
H
X
X
X
X
X
L
L
L
QAO
H
L
H
X
L
QBO
QAn
QAn
QAn
QHO
QGn
QGn
QGn
L
i
i
i
H
L
L
X
QH
H ~ High Level (steady state), L ~ Low Level (steady state)
X = Irrelevant (any input, including transitions)
t ~ Transition from low to high level.
QAO, Qeo, QHO ~ the level of QA, Qe, or QH, respectively, before the
indicated steady state input conditions were established.
j7
QAn, QGn ~ The level of QA or QG before the most recent
the clock; indicated a one·bit shift.
GND
t
transition of
TL/F/5765-1
Top View
Order Number MM54HCT164J or MM74HCT164J, N
See NS Package J14A or N14A
Logic Diagram
CLOCK
SERIAL
INPUTS
I <>:==:[)
A
80
CLEAR
Qs
QC
QD
QE
QF
QG
QH
TL/F/5765-2
4-43
Absolute Maximum Ratings
Supply Voltage (Veel
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K. 10K)
DC Output Current. per pin ~IOUT)
DC Vee or GND Current. per pin (lee)
Storage Temperature Range (T8m)
Power Dissipation (Po) (Note 3)
Lead Temperature (TO
(Soldering 10 seconds)
Operating Conditions
(Notes 1 & 2)
-0.5 to + 7.0V
-1.5 to Vee 1.5V
-0.5 to Vec+ 0.5V,
±20mA
±25mA
±50mA
-65·Cto + 150·C
500mW
+
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TA)
MM74HCT
MM54HCT
Input Rise or Fall Times
(tr• tl).
Min
4.5
0
Max
5.5
Vee
Units
V
V
-40
-55
+B5
+125
·C
·C
500
ns
260·C
DC Electrical Characteristics Vee=5V ±10% (Unlessothe~isespecified)
Symbol
Parallleter
Conditions
TA=25"C
74HCT
TA=-40to85"C
Typ
S4HCT
TA= -SSto 12S·C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0
2.0
2.0
V
VIL
Maximum Low Level
Input Voltage
O.B
O.B
O.B
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
IIOUTI=20p.A
IIOUTI=4.0 mAo Vee=4.5V
ilOUTI=4.B mAo Vee=5.5V
Vee
4.2
5.2
Vee- 0.1
3.9B
4.9B
Vee- 0.1
3.B4
4.B4
Vee- 0.1
3.7
4.7
V
V
V
Maximum LOw Level
Voltage
VIN = VIH or VIL
Ilourl=20p.A
ilOUTI=4.0 mAo Vee=4.5V
IIOUTI=4.B mAo Vee=5.5V
0
0.2
0.2
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
1Ii-l
Maximum Input
Current
¥IN = Vee or GND
±0.1
±1.0
±1.0
Icc
Maximum Quiescent
Supply Current
VIN = Vee or GND
lour=Op.A
,B.O
BO
160
VOL
.. A
,.~
p.A
mA
VIN = 2.4V or 0.4V (Note 4)
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all vollages are referenced to ground.
Nota 3: Power Dissipation temperature dereting - plastic "N" package: -12 mW'"C from 65"C to 65"C; ceramic "J" package: - t 2 mW'"C from 100"C to 125"C.
Note 4: This is measured per pin. All other Inputs are held at Voo ground.
,
4-44
AC Electrical Characteristics
Symbol
Parameter
Vee = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns
Conditions
Typ
Guaranteed
Limit
Units
fMAX
Maximum Operating
Frequency from Clock
toQorQ
50
30
MHz
tpHL, tpLH
Maximum Propagation
Delay Clock to Q or Q
20
32
ns
tpHL, tpLH
Maximum Propagation
Delay from Clear to Q
24
36
ns
tREM
Minimum Removal Time,
Preset or Clear to Clock
20
ns
ts
Minimum Set Up Time
Data to Clock
20
ns
tH
Minimum Hold Time
Clock to Data
0
5
ns
tw
Minimum Pulse Width
Clock, Preset or Clear
10
18
ns
AC Electrical Characteristics
Vee = 5.0V±10%,CL = 50 pF, tr = tf = 6ns(unlessotherwisespecified)
TA=2SoC
Symbol
Parameter
Conditions
Typ
fMAX
Maximum Operating
Frequency
tpHL, tpLH
Maximum Propagation
Delay from Clock to
Q
tpHL, tpLH
Maximum Propagation
Delay from Clear to Q
tREM
74HCT
TA=-40to8SoC
S4HCT
TA=-SSto12SOC
Units
Guaranteed Limits
27
21
18
MHz
23
37
46
54
ns
27
41
51
61
ns
Minimum Removal Time
Clear to Clock
20
25
30
ns
ts
Minimum Setup Time
Data to Clock
20
25
30
ns
lH
Minimum Hold Time
Clock to Data
0
5
0
0
ns
tw
Minimum Pulse Width
Clock, or Clear
10
18
22
27
ns
t r, tf
Maximum Input Rise and
Fall Time
500
500
500
ns
trHL, trLH
Maximum Output
Rise and Fall Time
15
19
22
ns
Cpo
Power Dissipation ,
Capacitance (Note 5)
(per flip-flop)
pF
Maximum Input
10
pF
5
10
10
Capacitance
Note 5: CRO determines the no load dynamic power consumption, Po = Cpo Vcc2 f+ lee Vee. and the no load dynamic current consumption. Is = Cpo Vee f+ Icc-
CIN
4-45
~
0»
,-------------------------------------------------------------------------------------,
~
ti ~National
::c
PRELIMINARY
\' - - _ .---...,)
J
'OS'
~ Semiconductor
.....
microCMOS
:E
:E
.... MM54HCT191/MM74HCT191
0»
~
...
~
.(.)
X
'OS'
Synchronous Binary Up/Down
Count,rs with Mode Control
II)
:E
:E
General Description
These high speed synchronous counters utilize microCMOS
technology, 3.0 micron silicon gate N-well CMOS. They possess the high noise immunity and low power consumption of
CMOS technology, along with the speeds of low power
Schottky TTL. These circuits are synchronous, reversible,
up/down counters. The MM54HCT191/MM74HCT191 are
4-bit binary counters.
Synchronous operation is provided by having all flip,flops
clocked simultaneously so that the outP4ts change simultaneously when so instructed by the steering logic. This mode
of operation eliminates the output counting spikes normally
associated with asynchronous (ripple clock) counters.
The outputs of the four master-slave flip-flops are triggered
on a low-to-high level transition of the clock input, if the
enable input is low. A high at the enable input inhibits counting. The direction of the count Is determined by the level of
the down/up input. When low, the counter counts up and
when high, it counts down.
These counters are fully programmable; that is, the outputs
may be preset to either level by plaCing a low on the load
input and entering the desired data at the data inputs. The
output will change independent of the level of the clock input. This feature allows the counters to be used as divide by
N dividers by simply modifying the count length with the
piaset inputs.
Connection Diagram
Two outputs have been made available to perform the cascading function; ripple clock and maximum/minimum count.
The latter output produces a high level output pulse with a
duration approximately equal to one complete cycle of the
clock when the counter overflows or underflows. The ripple
clock Ou1put produces a low level output pulse equal in
width to the low level portion of the clock input when an
overflow or underflow condition exists. The counters can be
easily cascaded by feeding the ripple clock output to the
enable input of the succeeding counter if parallel clocking is
used, or to the clock input if parallel enabling is used. The
maximum/minimum count output can be used to accomplish look-ahead for high speed operation.
MM54HCT/MM74HCT devices are intended to interface be·
tween TTL and NMOS components and standard CMOS
devices. These parts are also plug-in replacements for LSTTL devices can be used to reduce power consumption in
existing designs.
Features
• Level changes on Enable or Down/Up can be made
regardle!ls of the level of the clock.
• Low quiescent supply current: 80 /LA maximum
(74HCT Series)
• Low input current: 1 /LA maximum
• TTL compatible inputs
Truth Table
Dual-In-Llne Package
DATA
Vee
A
RIPPl£
CLDCK
CLOCK
MAXI
MIN
LDAD
DATA
DATA
C
D
LOad
Enable
G
Down/
Up
H
H
L
H
L
L
X
H
L
H
X
X
Clock
Function
t
t
CQuntUp
CountDown
Load
No Change
X
X
Order Number MM54HCT191J
or MM74HCT191J, N
See NS Package J16A or N16E
I
DATA
B
4
D.
ENABLE
DOWN I
G
UP
DO
GND
TL/F/5744-1
4-46
Absolute Maximum Ratings (Notes 1 and 2)
--0.5Vto + 7.0V
Supply Voltage (Ved
DC Input Voltage (VIN)
-1.5VtoVee + 1.5V
DC Output Voltage (VOUT)
-0.5V to Vee + 0.5V
±20mA
Clamp Diode 9urrent (11K. 10K)
±25mA
DC Output Current. per Pin (lOUT)
±50mA
DC Vee or GND Current. per Pin (led
-65·Cto + 150·C
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
500mW
lead Temperature (TLl
260·C
(Soldering. 10 seconds)
DC Electrical Characteristics Vee =
Symbol
Parameter
Conditions
Operating Conditions
Supply Voltage (Ved
DC Input or Output Voltage
. (VIN. VOUT)
Operating Temp. Range (TA)
MM74HCT
MM54HCT
Input Rise or Fall Times
(tr• tt)
Min
4.5.
Max
5.5
Units
V
0
Vee
V
-40
-55
+85
+125
·C
·C
500
ns
5V ± 10% unless otherwise specified
TA=25"C
Typ
74HCT
S4HCT
TA= -40·C toSS·C TA= -SS·Cto 12S·C Units
Guaranteed Limits
VIH
Minimum High level
Input Voltage
2.0
2.0
2.0
V
VIL
Maximum low level
Input Voltage
0.8
0.8
0.8
V
VOH
Minimum High level VIN =
Output Voltage
IIOUTI
IIOUTI
IIOUTI
VIH or VIL
= 20/J-A
Vee Vee- 0.1
3.98
= 4.0 mAo Vee = 4.5V 4.2
4.98
= 4.8 mA. Vee = 5.5V 5.2
Vee- 0.1
3.84
4.84
Vee- 0.1
3.7
4.7
V
V
V
Maximum low level VIN =
Voltage
IIOUTI
!louTI
IIOUTI
VIH or VIL
0
= 20/J-A .
= 4.0mA. Vee = 4.5V 0.2
= 4.8 mAo Vee = 5.5V 0.2
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0;4
0.4
V
V
V
±0.1
±1.0
±1.0
/J-A
8
80
160
/J- A
VOL
liN
Maximum Input
Current
lee
Maximum Quiescent VIN = Vee or GND
Supply Current
lOUT = O/J-A
VIN = Vee or GND.
VIH orVIL
VIN = 2.4V or 0.5V (Note 4)
mA
Note 1: Absolute Maximum Ratings are those values bayond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power dissipation temperature derating-plestic "N" package: -12 mW/'C from 65'C to 85'C; ceramic "J" package: -12 mWI'C from 100'C to 12S'e.
Note 4: Measured per pin, all other inputs held at Vee or GND.
4-47
AC Electrical Characteristics
Symbol
Parameter
TA = 25°C, Vcc = 5.0V, tr = tf = 6ns,CL = 15 pFunless otherwise specified
From
Input
To
Output
Conditions
Typ
Guaranteed
Limits
·40
Units
fMAX
Maximum Clock Frequency
tpLH, tpHL
Maximum Propagation
Delay Time
Load
QA,QB
Qc,Qo
30
MHz
ns
tpLH, tpHL
Maximum Propagation
Delay Time
Data A,
B,C;D
QA,QB
Qc,Qo
27
ns
tpLH, tpHL
Maximum Propagation
Delay Time
Clock
Ripple Clock
16
ns
tpLH, tpHL
Maximum Propagation
Delay Time
Clock
QA,QB
Qc,Qo
24
ns
tPLH, tpHL
Maximum Propagation
Delay Time
Clock
Max/Min
30
ns
tpLH, tpHL
Maximum Propagation
Delay Time
Down/Up
Ripple Clock
29
ns
tpLH, tpHL
Maximum Propagation
Delay Time
Down/Up
Max/Min
22
ns
tpHL, tpLH
Maximum Propagation
Delay Time
Enable
Ripple Clock
22
ns
tw
Minimum Clock or Load
Input Pulse Width
10
ns
Is
Minimum Set-Up Time
Data
Clock
ns
tH
Minimum Hold Time
Clock
Data
ns
Is
Minimum Set-Up Time
Down/Up
Clock
ns
tH
Minimum Hold Time
Clock
Down/Up
ns
Is
Minimum Set-Up Time
Enable
Clock
ns
tH
Minimum Hold Time
Clock
Enable
ns
Is
Minimum Set-Up Load
Inactive to Clock
ns
,.
\
-
,
4-48
AC Electrical Characteristics Vcc=5V ±10%. CL =
Symbol
Parameter
From
Input
To
Output
Conditions
TA=2S·C
Typ
fMAX
Maximum Clock
Frequency
50 pF. t, = tf = 6 nsunless otherwise specified
74HCT
S4HCT
TA= -40·Cto 8S·C TA= -SS·Cto 12S·C Units
Guaranteed Limits
38
MHz
tpLH. tpHL Maximum Propagation Delay Time
Load
QA.Qa
Qc.Qo
32
ns
tpLH. tpHL Maximum Propagation Delay Time
DataA.
B,C,D
QA.Qa
Qc,Qo
28
• ns
tpLH, tpHL Maximum Propagation Delay Time
Clock
Ripple
Clock
18
ns
tpLH, tpHL Maximum Propagation Delay Time
Clock
QA,Qa
Qc,Qo
27
ns
tpLH, tpHL Maximum Propagation Delay Time
Clock
Max/Min
33
ns
tpLH, tpHL Maximum Propagation Delay Time
Down/Up
Ripple
Clock
30
ns
tpLH, tpHL Maximum Propagalion Delay Time
Down/Up Max/Min
25
ns
25
ns
tpHL,lpLH Propagation Delay
Time
tw
Enable
Ripple
Clock
Minimum Clock, or
Load Input Pulse
ns
Is
Minimum Set-Up Time
Data
Clock
tH
Minimum Hold Time
Clock
Data
10
ns
ns
tTHL, tTLH Maximum Output
Rise and Fall Time
ns
Is
Minimum Set-Up Time Down/Up'
tH
Minimum Hold Time
Clock
Down/Up
ns
Is
Minimum Set-Up Time
Enable
Clock
ns
Clock
Enable
ns
tH
Minimum Hold Time
Is
Minimum Set-Up Load
Inactive to Clock
tr, tf
Maximum Clock Input
Rise and Fall Time
CIN
Input Capacitance
Clock
ns
ns
~
Power Dissipation
Capacitance (Note 5)
Note 5: CPO determines the no load dynamic power consumption, Po
ns
CPO
~
5
pF
100
pF
Cpo Vee2 1+ lee Vee, and the no load dynamic current consumption, IS ~ Cpo Vee 1+ Icc.
4-49
•
Timing Diagram
HCT191 Synchronous Binary Counter Typical Load, Count, and Inhibit Sequence
LOAD
A
DATA
INPUTS
,..-jo--I""I-----------------------~-------------------------------~---------------+--+.1-----------------------,..-+--1-1-----------------------L ______________________ _
,..-jo--I""I------~-----------------
~---~-------~-------~---
CLOCK
DOWN/UP
ENABLE
RIPPLE CLOCK _
H
...J
_113
14
15
15
i-----CDUNT up----~~-INHIBIT
LOAD
Sequence:
(1) Load (pre.et) to binary thirteen.
(2) Count up to fourteen, fifteen, zero, one, and two.
14
13
I-----CDUNT DDWN-----I.!
TL/F/5744-2
(3) Inhibit.
, (4) Count down to one, zero, mteen, fourteen, and thirteen.
4-50
Logic Diagram
HCT191
CLOCK
ENABLE G
DOWN/UP
(14)
~
~
(5)
T
~~
1
]
.....
1
-
----,
~
(13)
"\.
(12)
"\
I
DATA (15)
INPUT A
-
MAX/MIN
"\.
L
L ~h
t-
1
~.
DATA (1)
INPUT B
HIPPLE CLOCK
-
-
~I>CK
OUTPUT
OA
T
-
I
,rr- +h
+
-
~~,
0 0
D 0
.... 1> CK
OUTPUT
OB
1
-""""""'\.
-
DATA (10)
INPUT C
~D
---,
"\
~D-1
DATA (9)
INPUT D
~h
PH
D 0
~ CK
t-
(6)
OUTPUT
Oc
T
I
~,
LDAD
.1
I
---r'
-
~D--~~~
--
1
(11)
CK
OUTPUT
OD
-TTL/F/5744-3
4-51
.
~ Semiconductor
~National
PRELIMINARY
r:: \
~
microCMOS
MM54HCT193/MM74HCT193
Synchronous Binary Up/Down Counters
General Description
These high speed synchronous counters utilize microCMOS
technology;3.0 micron silicon gate N-well CMOS to achieve
the high noise immunity and low power consumption of
CMOS technology, along with the speeds of low power
Schottky TIL. The MM54HCT193/MM74HCT193 is a binary counter having two separate clock inputs, an UP COUNT
input and a DOWN COUNT input. All outputs of the flip-flops
are !!imultaneously triggered on the low-to-high transition of
either clock while the other input is held high. The direction
of counting is determined by which input is clocked.
This device has TIL compatible inputs. It can drive 15 LSTIL loads.
This counter may be preset by entering the desired data on
the DATA A, DATA B, DATA C, and DATA D inputs. When
the LOAD input is taken low, the data is loaded independently of either clock input. This feature allows the counter
to be used as a divide-by-n counter by modifying the count
length with the preset inputs.
Both a BORROW and CARRY output are provided to enable cascading of both up and down counting functions. The
. BORROW output produces a negative-going pulse when
the counter underflows and the CARRY outputs a pulse
when the counter overflows. The counter can be cascaded
by connecting the 'CARRY and BORROW 'outputs of one
device to the COUNT UP and COUNT DOWN inputs, respectively, of the next device.
All inputs are protected from damage due to static discharge by diodes to Vee and ground..
Features
eo
• Low quiescent supply current:
p.A maximum (74HCT
Series)
• Low input current: 1 p.A maximum
• TIL compatible inputs
In addition,the HCT191 can also be cleared. This is accomplished by inputting a high on the CLEAR input. All 4 internal .
stages are set to a low level independently of either COUNT
input.
Connection Diagram
Truth Table
Dya!-!n-l!n!! Pac".!!ge
DATA
A
Count
DATA
C
Up
Down
t
H
H
t
X
X
X
X
Clear
Load
Function
L
L
H
L
H
'H
Count Up
CountDown
Clear
Load
= high level
= lowlev.1
f = transition from low-to·high
H
L
X = don't care
DATA
B
0,
OA
COUNT
DOWN
COUNT
UP
OND
TL/F/5742-1
Order Number MM54HCT193J
or MM74HCT193J,N
See NS Package J16A or N16E
4-52
X
L
Absolute Maximum Ratings
Operating Conditions
(Notes 1 and 2)
-0.5Vto +7.0V
Supply Voltage {VeC>
DC Input Voltage (VIN)
-1.5V to Vee + 1.5V
DC Output Voltage (VOUT)
-0.5V to Vee + 0.5V
Clamp Diode Current (11K. 10K>
DC Output Current. per Pin (lOUT)
±20mA
DC Vee or GND Current. per Pin(lec>
±50mA
Storage Temperature Range (TSTG)
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TAl
MM74HCT
MM54HCT
Input Rise or Fall Times
(t,. tl)
±25mA
-65'Cto + 150'C
500mW
Power Dissipation (Po) (Note 3)
Min
4.5
Max
5.5
Units
V.
0
Vee
V
-40
-55
+85
+125
'C
'C
500
ns
Lead Temperature (Tu
(Soldering. 10 seconds)
260'C
DC Electrical Characteristics Vee =
Symbol
Parameter
5V ± 10% unless otherwise specified
Conditions
TA=25"C
74HCT
54HCT
TA= -40"Ct085"C TA= -55'C to 125'C Units
Typ
Guaranteed Umits
VIH
Minimum High Level
Input Voltage
2.0
2.0
2.0
V
VIL
Maximum Low Level
Input Voltage
0.8
0.8
0.8
V
VOH
Minimum High Level VIN =
Output Voltage
IIOUTI
IiOUTI
IIOUTI
VIH or VIL
= 20 p.A
Vee Vee- 0.1
3.98
= 4.0 rnA. Vee = 4.5V 4.2
4.98
= 4.8 rnA. Vee = 5.5V 5.2
Vee- 0.1
3.84
4.84
Vee- 0.1
3.7
4.7
V
V
V
Maximum Low Level VIN =
Voltage
IIOUTI
IIOUTI
IIOUTI
VIH or VIL
= 20 p.A
= 4.0 rnA. Vee = 4.5V
= 4.8 rnA. Vee = 5.5V
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
±0.1
±1.0
±1.0
p.A
4.0
40
80
p.A
VOL
liN
Maximum Input
Current
lee
Maximum Quiescent VIN = Vee or GND
Supply Current
lOUT = Op.A
0
0.2
0.2
VIN = Vee or GND.
VIHorVIL
VIN = 2.4V or 0.5V (Note 4)
100
p.A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced \0 ground.
Note 3: Power dissipation temperature deratin!r-Plastic "N" package: -12 mW I'C from 65'C to 85'C; ceramic "J" package: - 12 mW/'C from 100"C to 125'C.
Note 4: Measured per pin, all other Inputs held at Vee or GND.
4·53
AC Electrical Characteristics
(Note 6) Vee
Symbol
, fMAX
= 5V, TA = 25°C, CL = 15 pF, t, = tf = 6 ns (unless otherwise specified)
Parameter
From
(Input)
To
(Output)
Maxiplum Clock
Frequency
Conditions
Typ
Guaranteed
Limit
Units
MHz
tpLH, PHL
Maximum Propagation
Delay Time
Load
qA,QB,
QC,QD
ns
tpLH, PHL
Maximum Propagation
Delay Time
Data A,
B,C,D,
QA,QB,
QC,QD
ns
tpLH, PHL
Maximum Propagation
Delay Time
Count-Up
or-Down
QA,QB,
QC,QD
ns
tpLH, PHL
Maximum Propagation
Delay Time
Qount-Up
Carry
ns
tpLH, PHL
Maximum Propagation
Delay Time
Count-On
BO,rrow
ns
it;>LH,PHL
Maximum Propagation
Delay Time
Clear
QA,QB,
QC,QD
ns
tw
Width of Count, Clr,
or Load Input Pulse
ns
Is
Minimum Setup Time
Data to Load-LH
ns
tH
Minimum Hold Time
Data after Load-LH
ns
Is
Minimum Setup Time
Load Inactive before
Count LH transition
ns
ts
Minimum Setup Time
e!r Inactive before
Count LH transition
ns
iH
Minimum Hold Time
Count-Up High after
Count-On LH trans.
ns
tH
Minimum Hold Time
Count-On High after
Count-Up LH trans,
ns
Is
Minimum Setup Time
,Enable to Clock-LH
ns
4-54
AC Electrical Characteristics (Note 6)
Vee = 5V, ±10%, CL = 50 pF (unless otherwise specified)
Symbol
fMAX
Parameter
_.
74HC
54HC
T=25·C
From
To
T -,25 C T= -40· to 85·C T= -55· to 125·C Units
(Input) (Output)
Typ
Guaranteed Limits
Maximum Clock Frequency
MHz
tpLH, PHL Maximum Propagation
Delay Time
Load
QA,QB,
QC,QD
ns
tpLH, PHL Maximum Propagation
Delay Time
Data A
QA,QB,
QC,QD
ns
tpLH, PHL Maximum Propagation
Delay Time
Count~Up
QA,QB
or-Down QC,QD
ns
tpLH, PHL Maximum Propagation
Delay Time
Count-Up
carry
ns
tpLH, PHL Maximum Propagation
Delay Time
CountDown
Borrow
ns
tpLH, PHL Maximum Propagation
Delay Time
Clear
QA,QB
QC,QD
ns
two
Width of Count, Clear, or
Load Input Pulse
ns
Is
Minimum Setup TIme Data
before Load-LH
ns
tH
Minimum Hold Time Data
after Load-LH
ns
Is
Minimum Setup Time Load
Inactive before Count LH
transition
ns
ts
Minimum Setup Time Clear
Inactive before Count LH
transition
ns
tH
Minimum Hold TIme Count-Up
high after Count-Down LH
transition
ns
tH
Minimum Hold Time Count-Dn
high after Count-Up LH
transition
ns
lTLH, THL Output Rise or Fall Time
tr,f
Maximum Input Rise or Fall
Time
CpO
Power Dissipation
capacitance
ns
ns
,
pF
pF
Minimum Input capaCitance
CIN
Note 5: Cpo delermines the no load dynamic power consumption, Cpo' Vcc"2)'f + ,lcc'Vcc, and the no load dynamic current consumption, I. = Cpo'
Vcc'f +.
Note 6: Refer to Section 1 for Typical MM54/74HCT AC Switchforms and Test Circuits.
4-55
•
MM5.4HCT193/MM74HCT193
MM54HCT193/MM74HClr193 Synchronous 4·Bit Up/Down Binary Counter
AIN
1S
BIN
OA
OB
1)2
Oc
CIN
10
06
CARRY OUT
12
DIN
9
Qo
07
..
1.:
....
QO
'"'"
aD
s
COU~~O
COUNT ~
I'
11'1
DOWN 14
ClEAR~
I
11
LOAD o----t.-,;
9
o--J
L.......==I
~
'------£...,.01-
..... -
BORROW
- OUT
16
vee
8
rGNO
TLlF/5742-2
J?)I National
~ Semiconductor
microCMOS
MM54HCT240/MM74HCT240
Inverting Octal TRI-STATE® Buffer
MM54HCT241/MM74HCT241 Octal TRI-STATE Buffer
MM54HCT244/MM74HCT244 Octal TRI-STATE Buffer
General Description
These TRI-STATE buffers utilize microCMOS Technology,
3.0 micron silicon gate N-well CMOS, and are general purpose high speed inverting and non-inverting buffers. They
possess high drive current outputs which enable high speed
operation even when driving large bus capacitances. These
circuits achieve speeds comparable to low power Schottky
devices, while retaining the low power consumption of
CMOS. All three devices are TTL input compatible and have
a fanout of 15 LS-TTL equivalent inputs.
buffer. Each device has two active low enables (1G and
2G), and each enable independently controls 4 buffers.
MM54HCT241/MM74HCT241 is also a non-inverting buffer
similar to the 244 except that the 241 has one active high
enable, each again controlling 4 buffers.
All inputs are protected from damage due to static discharge by diodes to Vee and Ground.
MM54HCTIMM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS
devices. These parts are also plug-in replacements for LSTTL devices and can be used to reduce power consumption
in existing designs.
•
•
•
•
•
The MM54HCT240/MM74HCT240 is an inverting buffer
and the MM54HCT244/MM74HCT244 is a non-inverting
Connection Diagrams
Vce
20
lYl
2A4
1Y2
2A3
lY3
10
lAl
2Y4
lA2
2Y3
lA3
2Y2
Features
TTL input compatible
Typical propagation delay: 14 ns
TRI-STATE outputs for connection to system buses
Low quiescent current: 80 /LA
Output current: 6 mA
Dual-In-Llne Packages
2Al
lA4 2Yl GND
TLlF/5365-1
lOlA I
2Y4
'''2
2Y3
IA3
2Y2
'''4 2Y1 GND
TLlF/5365-2
Top View
. Top View
Order Number MM54HCT24OJ or MM74HCT240J, N
Order Number MM54HCT241J or MM74HCT241J, N
Vcc
20
10
IAI
2Y4
lA2
2Y3
2A3
lY3
2A2
IY4 2A 1
lA3
2Y2
lA4
2Y1 GND
TL/F/5365-3
Top View
Order Number MM54HCT244J or MM74HCT244J, N
See NS Package J20A or N20A
4-57
Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage (Vee>
-0.5 to +7.0V
DC Input Voltage (VIN)
-1.5 to Vee + 1.5V
-0.5 to Vee+0.5V
DC Output Voltage (VOUT)
±20mA
Clamp Diode Current (11K, 10K>
±35mA
DC Output Current, per pin (lOUT)
±70mA
DC Vee or GND Current, per pin (ICe>
Storage Temperature Range (T8TG)
-65'C to + 150'C
Power Dissipation (Po) (Note 3)
500mW
Lead Temp. (TU (Soldering 10 seconds)
260'C
Operating Conditions
Supply Voltage (Vee>
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (Till
MM74HCT
MM54HCT
Input Rise or Fall Times
(tr' tt)
Min
4.5
0
Max
5.5
Vee
Units
V
V
-40
-55
+85
+125
'C
'C
500
ns
DC Electrical Characteristics
Vee=5V ± 10% (unless otherwise specified)
74HCT
TA= -40 to 8S'C
TA=2S'C
Parameter
Symbol
Conditions
Typ
S4HCT
TA=-SSt012S'C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0
2.0
2.0
V
VIL
Maximum Low Level
Input Voltage
0.8
0.8
0.8
V
VOH
Minimum High Level
Output Voltage
VIN-EE=VIH orVIL
IIOUTI =20 /A-A
IIOUTI=6.0 mA, Vee=4.5V
IIOUTI=7.2 mA, Vee=5.5V
Vee
4.2
5.2
Vee- 0.1
3.98
4.98
Vee- 0.1
3.84
4.84
Vee- 0.1
3.7
4.7
V
V
V
Maximum Low Level
Voltage
VIN = VIH or VIL
IIOUTI=20 ,..,A
IIOUTI=6.0 mA, Vee=4.5V
IIOUTI=7.2 mA, Vee=5.5V
0
0.2
0.2
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
±0.1
±1.0
±1.0
,..,A
±0.5
±5.0
±10
,..,A
8.0
80
160
,..,A
1.0
1.3
.1.5
mA
VOL
Maximum Input
VIN = Vee or GND,
Current
VIHorViL
loz
Maximum TRI-STATE
Output Leakage
Current
VOUT= Vee or GND
G=VIH
G=VIL
Icc
Maximum Quiescent
Supply Current
VIN=vee or GND
16uT=0,..,A
liN
VIN = 2.4V or 0.5V (Note 4)
0.6
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Nole 2: Unless otherwise specified all voltages are referenced to ground.
Nole 3: Power Dissipation temperature derating - plastic "N" package: -12 mWrc from 65'C to,85'C; ceramic "J" package: -12 mW/'C trom 1OO'C to 125'C.
Nole 4: Measured per input. All other inputs at Vee or GND.
,,;.
Truth Tables
'HCT240
'HCT241
'HCT244
1G
1A
1V
2G
2A
2V
1G
1A
1Y
2G
2A
2V
1G
1A
IV
2G
2A
2V
L
L
H
H
L
H
L
H
H
L
Z
Z
L
L
H
H
L
H
L
H
H
L
Z
Z
L
L,
H
H
L
H
L
H
L
H
Z
Z
L
L
H
H
L
H
L
H
Z
Z
L
H
L
L
H
H
L
H
L
H
L
H
Z
Z
L
L
H
H
L
H
L
H
L
H
Z
H=high level, L= low level, Z = high impedance
4-58
Z
AC Electrical Characteristics MM54HCT240/MM74HCT240, MM54HCT241IMM74HCT241,
MM54HCT244/MM74HCT244 Vee = 5.0V, tr. = tf = 6 ns, TA = 25'C (unless otherwise specified)
Symbol
Parameter
Conditions
Typ
Guaranteed
Limits
Units
tpHL, tpLH
Maximum Output
Propagation Delay
CL =45pF
14
18
ns
tpZL, tP:ilH
Maximum Output
Enable Time
CL =45pF
RL = 1 kn
20
30
ns
tpLZ, tpHZ
Maximum Output
Disable Time
CL =5 pF
RL= 1 kn
16
25
ns
AC Electrical Characteristics
MM54HCT240/MM74HCT240, MM54HCT241IMM74HCT241,
MM54HCT244/MM74HCT244 Vee = 5.0V ± 10%, tr = tf = 6 ns (unless otherwise specified)
TA=25'C
Symbol
Parameter
Conditions
Typ
tpHL, tpLH
Maximum Output
Propagation Delay
CL =50pF
tpZH, tpZL
Maximum Output
Enable Time
RL = 1 kn
tpHZ, tpLZ
Maximum Output
Disable Time
tTHL. trLH
Maximum Output
Rise and Fall Time
C'N
COUT
14
CL =150 pF
74HCT
TA= -40 to 85'C
54HCT
TA= -55to 125'C
20
25
30
ns
ns
20
28
35
42
21
30
38
45
ns
26
42
53
63
ns
RL = 1 kn
CL =50 pF
16
25
32
38
ns
CL =50 pF
6
12
15
18
ns
Maximum Input
Capacitance
10
15
15
15
pF
Maximum Output
Capacitance
15
20
20
20
pF
I CL=50pF
I CL =150 pF
(per buffer)
5
90
G=Vee.G=GND
G=GND, G=VeC
Note 5: CPO determine. the no load dynamic power consumption, Po ~ Cpo Vcr? f + lee Vee,and the no load dynamic current consumption, Is
,
. f+lee·
CPO
Units
Guaranteed Limits
Power Dissipation
Capacitance (Note 5)
4-59
pF
pF
~ Cpo
Vee
• r-------------------------------------------------------------------------,
~
:::E:
Logic Diagrams
'HCT241
'HCT240
o....-,r------=r
;:!:
,.,
::E
::E
....
,.,
~
,.,
"2
..
,•. 0----jL,________--1
'"
. ,o----t===:=J
.,
•
:::E:
an
•
::E
::E
'"
,
zye
0----1'--------.
.....-
•
~
:::E:
•r-..
::E
....::E.•
..,
'"
'"
'"
~
:::E:
an
•
::E
:E
c:;
•
~
:::E:
•
::E
r-..
ill
---D_..J
TUF/5365-4
:E
....
Q
•
e
:::E:
•an
::E
::E
TUF/5365-5
'HCT244
2.'
()O----f---------lt---o
IV'
,., <>---t===:=J
'.2o---t===:=J
'"
2.'
o------i-.-_____~
."
~
0----£><>--
.•, O----L,________--1
",
'"
Vee
TUF/5365-6
4·60
~National
~ Semiconductor
micro CMOS
MM54HCT245/MM74HCT245
Octal TRI-STATE® Transceiver
General Description
This TRI-STATE bi-directional buffer utilizes microCMOS
Technology, 3.0 micron silicon gate N-well CMOS, and is
intended for two-way asynchronous communication between data buses. It has high drive current outputs which
enable high speed operation even when driving large bus
capacitances. This circuit possesses the low power con, sumption of CMOS circuitry, yet has speeds comparable to
low power Schottky TIL circuits.
This device is TIL input compatible and can drive up to 15
LS-TIL loads, and all inputs are protected from damage due
to static discharge by diodes to Vee and ground.
MM54HCTIMM74HCT devices are intended to interface between TIL and NMOS components and standard CMOS
devices. These parts are also plug-in replacements for LSTIL devices and can be used to reduce power consumption
in existing designs.
Features
• TIL input compatible
• Octal TRI-STATE outputs for JLP bus applications:
6 mA, typo
• High speed: .16 ns typical propagation delay
• Low power: 80 JLA (74HCT Series)
MM54HCT245/MM74HCT245 has one active low enable input (G), and a direction control (DIR). When the DIR input is
high, data flows from the A inputs to the B outputs. When
DIR is low, data flows from B to A.
Connection Diagram
Dual-In-Llne Package
ENABLE
vee
DIR
G
A1
B2
B1
A2
A3
B3
B4
B5
B6
A4
A5
AS
A7
B7
AS
Top View
Order Number MM54HCT245J or MM74HCT245J, N
See NS Package J20A or N20A
Truth Table
Control
Inputs
Operation
G
DIR
245
L
L
B data to A bus
L
H
A data to B bus
H
X
isolation
H = high level L = low level,
4-61
X=
irrelevant
BS
GND
TLIFI5366-1
Absolute Maximum Ratings (Notes 1 &2)
Supply Voltage
DC Input Voltage
DC Output Current, per pin (lOUT)
DC Vcc or GND Current, per pin (Icc)
Storage Temperature Range (T8TG)
Power Dissipation (PD) (Note 3)
Lead Temperature (Tu
(Soldering 10 seconds)
Operating Conditions-
-0.5 to + 7.0V
-1.5 to Vcc+ 1.5V
-0.5 to Vcc+ 0.5V
±20mA
±35mA
±70mA
-65'Cto + 150'C
500mW
Supply Voltage
DC input or Output Voltage
MM74HCT
MM54HCT
Input Rise or Fall TImes
Min
4.5
0
Max
5.5
Vcc
Units
V
V
-40
-55
+85
+125
'c
'c
(tr, tt>
. 500
ns
260'C
DC Electrical Characteristics
DC Output Current. per Pin (lOUT)
±25mA
±50mA
DC Vee or GND Current. per Pin (Ieel
- 65·C to + 150·C
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
500mW
Lead Temperature (T
260·C
(Soldering. 10 seconds)
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TAl
MM74HCT
MM54HCT
Input Rise or Fall Times
(lr. tf)
u
DC Electrical Characteristics Vee =
Symbol
Parameter
Conditions
Min
4.5
Max
5.5
Units
V
0
Vee
V
-40
-55
+85
+125
·C
·C
500
ns
5V ± 10% unless otherwise specified
TA=25"C
Typ
74HCT
54HCT
TA= -40·Cto 85'C TA= -55'Cto 125·C Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0
2.0
2.0
V
VIL
Maximum Low Level
Input Voltage
0.8
0.8
0.8
V
VOH
Minimum High Level VIN =
Output Voltage
ilOUTI
IIOUTI
ilOUTI
VIH or VIL
= 20 p.A
Vee Vee- 0.1
3.98
= 4.0 mAo Vee = 4.5V 4.2
4.98
= 4.8 mAo Vee = 5.5V 5.2
Vee- 0.1
3.84
4.84
Vee- 0.1
3.7
4.7
V
V
V
Minimum Low Level
Voltage
VIN =
IIOUTI
IIOUTI
ilOUTI
VIH'orVIL
0
= 20 p.A
= 4.0 mAo Vee = 4.5V 0.2
= 4.8 mAo Vee = 5.5V 0.2
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
liN
Maximum Input
Current
VIN = Vee or GND.
VIHorVIL
±0.1
±1.0
±1.0
p.A
lee
Maximum Quiescent VIN = Vee or GND
Supply Current
lOUT = Op.A
8
80
160
p.A
VOL
VIN = 2.4V or 0.5V (Note 4)
mA
Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specHied all voltages are referenced to ground.
Note 3: Power dissipation temperature derating-plastic UN U package: -12 mWI"e from 65'e to 85"C; ceramic UJ" package: -12 mW I'C from 100'C to 125"C.
Note 4: Measured per pin. all other Inputs held at Vee or GNO.
.
Note 1: Absolute
-
4-69
•
AC Electrical Characteristics Vee =
Typ
Guaranteed
Limits
Units
Maximum Operating Frequency
50
30
MHz
Parameter
Symbol
fMAX
5V, TA = 25·C, CL = 15 pF, tr = tf = 6 ns
Conditions
tpHL, tpLH
Maximum Propagation Delay from Clock to Q
18
30
tpHL, tpLH
Maximum Propagation Delay from Clear to Q
18
30
tREM
Minimum Removal Time, Clear to Clock
Is
Minimum Set-Up Time D to Clock
10
tH
Minimum Hold Time Clock to D
tw
Minimum Pulse Widlh Clock or Clear
AC Electrical Characteristics Vee =
Symbol
Parameter
Conditions
5.0V
± 10%, CL =
TA=25·C
Typ
fMAX
Maximum Operating
Frequency
IpHL,lpLH
Maximum Propagalion
Delay from Clock 10 Q
tpHL, tpLH
' Maximum Propagation
. Delay frolT! Clear 10 Q
ns
20
ns
20
ns
-3
5
ns
8
16
ns
50 pF, tr = If = 6 ns unless otherwise specified
74HCT
TA= -40"Cto 85"C
54HCT
TA= -55·Cto 125·C
Units
Guaranteed Limits
27
22
18
MHz
22
35
44
52
ns
22
35
44
52
ns
20
25
30
Minimum Removal
Time Clear to Clock
IREM
ns
,
ns
#
Is
Minimum Set-Up Time
DtoClock
10
20
25
30
ns
tH
Minimum Hold Time .
C!ocktoD
-3
5.
5
5
ns
tw
Minimum Pulse Width
Clock or Clear
16
20
24
ns
Ir• If
Maximum Inpul Rise
and Fall Time, Clock
500
500
500
ns
ITHL, tTLH
Maximum Output Rise
and Fall Time
15
19
22
ns
CPO
Power Dissipation
CapaCitance (Note 5)
CIN
Note
pF·
(Per FIiP:Flop)
Maximum Input
5
10
10
10
Capacitance
5: CpO determines the no loed dynamic power consumption, Po = Cpo Vee?- f + lee Vee, and the no load dynamic current Consumption, Is =
4-70
pF
Cpo Vee?- f
+ 100
~National
PRELIMINARY
---
~ Semiconductor
\
J
microCMOS
MM54HCT299/MM74HCT299
8-Bit TRI-STATE® Universal Shift Register
General Description
This a-bit TRI-STATE shift/storage register utilizes microCMOS technology, 3.0 micron silicon gate N-well CMOS.
Along with the low power consumption and high noise immunity of standard CMOS integrated circuits, it has the ability to drive 15 LS-TTL loads. This circuit also features operating speeds comparable to the equivalent low power
Schottky device.
The MM54HCT299/MM74HCT299 is TTL input compatible.
It features multiplexed inputs/outputs to achieve full a-bit
data handling in a single 20-pin package. Due to the large
output drive capability and TRI-STATE feature, this device is
ideally suited for interfacing with bus lines in a bus oriented
system.
Two function select inputs and two output control inputs are
used to choose the mode of operation as listed in tl)9 function table. Synchronous parallel loading is accomplished by
taking both function select lines, SO and S1, high. This
places the TAl-STATE outputs in a high impedance state,
which permits data applied to the input! output lines to be
clocked into the register. Reading out of the register can be
done while the outputs are enabled in any mode. A direct
overriding CLEAR input is provided to clear the register
whether the outputs are enabled or disabled.
.
The MM54HCT/MM74HCT devices are intended to intElrface between TTL and NMOS components and standard
CMOS devices. These devices are also plug-in replacements for LS-TTL devices and can be used to reduce power
consumption in existing deSigns.
.
All inputs are protected from damage due to· static discharge by diodes to Vee and ground.
Features
•
•
•
•
TAl-STATE 110
Output drive capability: 15 LS-TTL loads
Cascadable for n-bit word lengths
Clock-independe~t clear
Connection Diagram·
Dual-In-Llne Package
SHIfT
LEFT
¥eTe
20
51
19
SL
lB
SI
SL
aH'
HlaH
F/aF
0100
B/aa
CLOCK
SHIfT
RIGHT
SR
u
"
~
~
"
u
HlaH
F/aF'
DIDo
B/a8
Glaa
E/aE
C/Qc
AlIIA
4
B/Da
5
E/OE
6
Clae
n
CK
-so
SR
G
•
1
SO
I--
CLEAR
B
IIA'
9
CLEAR
OUTPuT
CONTROLS
110
GND
TUF/5746-1
Order Number MM54HCT299J or MM74HCT299J, N
See NS Package J20A or N20A
4-71
, Function Table
Inputs/Outputs
Inputs
Mode
Clear
Function
Select
S1
SO
Output
Control
Clock Serial A/QA 8/QB C/Qc D/QD E/QE F/QF G/QG H/QH QA' QH'
G1t G2t
"
SL SR
X
X
X
X
X
X
L
L
L
L
L
L
X
X
X
X
X
X
L
L
X
X
X
X
X
X
OAO
OAO
OSO
'OSO
Oeo
Oeo
000
000
X
X
H
L
H
L
OAn
OAn
OSn
OSn
Oen
H
L
X
X
OSn
OSn
OCn
OCn
X
X
a
b
Clear
L
L
L
X
L
H
L
X
H
L
L
X
L
L
X
Hold
H
H
L
,L
X
X
L
L
L
L
H
H
L
L
H
H
L
L
L
L
Shift Left
H
H
H
H
L
L
L
L
L
L
Load
H
H
H
X
X
t
t
t
t
t
, Shift Right
Outputs
L
L
L
L
L
L
L
L
L
X
L
L
' L
X
X
X
OEO
OEO
OFO
OFO
'OGO
OGO
OHO
OHO
Oen
OOn
OOn
OEn
OEn
OFn
OFn
OGn
OGn
H
L
OGn
OGn
OOn
OOn
OEn
OEn
OFn
OFn
OGn
OGn
OHn
OHn
H
L
OSn
OSn
H
L
,c
d
e
f
g
h
a
h
L
L
L
OAO OHO
OAO OHO
tWhen on,! ,or both controls are high, the eighllnputloutput terminals are elissbled to the high Impedance state; however, sequential operation or clearing 01 the
reglstar Is not affected, •
-
.
4-72
0
~National
PRELIMINARY
~ Semiconductor
\
~
microCMOS
MM54HCT323/MM74HCT323
a-Bit TRI-STATE® Universal Shift Register
General Description
This S-bit TRI-STATE shift/storage register utilizes microCMOS technology, 3.0 micron silicon gate N-well CMOS.
Along with the low power consumption and high noise immunity of standard CMOS integrated circuits, it has the ability to drive 15 LS-TTL loads. This circuit also features operating speeds comparable to the equivalent low power
Schottky device.
The MM54HCT323/MM74HCT323 is TTL input compatible.
It features multiplexed inputs/ outputs to achieve full S-bit
data handling in a single 20-pin package. Due to the large
output drive capability and TRI-STATE feature, this device is
ideally suited for interfacing with bus lines in a bus oriented
system.
Two function select inputs and two output control inputs are
used to choose the mode of operation as listed In the function table. Synchronous parallel loading is accomplished by
taking both function select lines, SO and S1, high. This
places the TRI-STATE outputs in a high impedance state,
which permits data applied to· the input/output lines
to be clocked into the register. Reading out of the register
can be done while the outputs are enabled in any mode. A
synchronous CLEAR input is provided to clear the register
whether the outputs are enabled or disabled.
The MM54HCT/MM74HCT devices are intended to interface between TTL and NMOS components and standard
CMOS devices. These devices are also plug-in replacements for LS-TTL devices and can be used to reduce power
consumption in existing designs:
All inputs are protected from damage due to static discharge by diodes to Vee and ground.
Features
•
•
•
•
TRI-STATE I/O
Output drive capability: 15 LS-TTL loads
Cascadable for n-bit word lengths
Synchronous clear
Connection Diagram
Dual-In-Llne Package
SHIFT
LEFT
SI
SL
18
•
1
so
18
SI
SL
QH'
~
HIGH
F/IIF
~
~
D/QD
BIlla
u
u
CLOCK
n
UN
H/QH
F/Qf
D/IIa
BIlla
GIIIa
Ell!(
CIlia
AIDA
DA
CLEAR
4
BIlla
5
E/Qe
6
C/Qe
A/QA
B
QA'
9
CLEAR
SHIFT
RIGHT
SR
n
CK
so
SR f0-
G
A
!2
.iii
3
1
IIf
,
7
OUTPUT
CONTRDLS
.vo
UND
TLlF/5745-1
Order Number MM54HCT323J or MM74HCT323J,N
See NS Package J20A or N20A
4-73
Function Table
Inputs/Outputs -
Inputs
Mode
Clear
Function
Select
S1
Clear
L
L
L
Output
Control'
Clock
SO G1t G2t
X
L
L-
X
L
L
L
L
H
A/QA B/Qa C/Qc D/Qo E/QE F/QF G/QG H/QH QA'
QH'
SL SR
f
f
f
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OAO
OAO
OBO
OBO
Oeo
Oeo
ODO
ODO
OED
OED
OFO
OFO
OGO
OGO
OHO
OHO
X
X
H
L
H
L
OAn
OAn
OBn
OBn
Oen
Oen
ODn
ODn
QEn
OEn
OFn
OFn
QGn
OGn
H
L
OGN
QGN
H
L
X
X
OBn
OBn
Oen
Qen
ODn
ODn
OEn
OEn
OFn
OFn
OGn
OGn
OHn
OHn
H
L
OBn
OBn
H
H
X
X
H
H
L
L
X
L
L
X
X
L
L
Shift Right
H
H
L
L
H
H
L
L
L
L
Shift Left
H
H
H
H
L
L
L
L
L
L
f
f
f
f
f
Hold
Serial
Outputs
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
OAO OHO
OAO OHO
L
Load
H
H
H
X
X
X X
b
c
d
e
f
g
h
h
a
a
t· When one or both controls are high, the eight input/output terminals are disabled to the high impedance state; however, sequential operation or clearing of the
register is not affected.
,
4-74
~National
PRELIMINARY
~ Semiconductor
\'-----...,.../)
microCMOS
MM54HCT373/MM74HCT373
TRI-STATE® Octal D-Type Latch
MM54HCT374/MM7 4HCT37 4
TRI-STATE Octal D-Type Flip-Flop
General Description
The MM54HCT373/MM74HCT373 octal Ootype latches and
MM54HCT374/MM74HCT374 Octal Ootype flip flops utilize
microCMOS Technology, 3.0 micron silicon gate N-well
CMOS, which provides the inherent benefits of low power
consumption and wide power supply range, but are LS-TTL
input and output characteristic & pin-out compatible. The
TRI-STATE outputs are capable of drivil"]g 15 LS-TTL loads.
All inputs are protected from damage due to static discharge by internal diodes to Vee and ground.
When the MM54HCT373/MM74HCT373 LATCH ENABLE
input is high, the Q outputs will follow the 0 inputs. When
the LATCH ENABLE goes low, data at the 0 inputs will be
retained at the outputs until LATCH ENABLE returns high
again. When a high logic level is applied to the OUTPUT
CONTROL input, all outputs go to a high impedance state,
regardless of what signals are present at the other inputs
and the state of the storage elements.
The MM54HCT374/MM74HCT374 are positive edge triggered flip-flops. Data at the 0 inputs, meeting the setup and
hold time reqUirements, are transferred to the Q outputs on
positive going transitions of the CLOCK (CK) input. When a
high logic level is applied to the OUTPUT CONTROL (OC)
input, all outputs go to a high impedance state, regardless
of what Signals are present at the other inputs and the state
of the storage elements.
MM54HCT/MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS
devices. These parts are also plug in replacements for LSTTL devices and can be used to reduce power consumption
in existing designs.
Features
•
•
•
•
•
•
TTL input characteristic compatible
Typical propagation delay: 20 ns
Low input current: 1 IJ-A maximum
Low quiescent current: BO IJ-A maximum
Compatible with bus-oriented systems
Output drive capability: 15 LS-TTL loads
Connection Diagram
Dual·ln·Llne Package
OUTPUT
ENABLE
~
m
~
~
~
~
~
~
Q
10
1D
2D
2Q
3Q
3D
40
40
Gl«J
Vee
80
8D
70
7Q
eo
so
50
50
CLOCK
OUTPUT
10
1D
aD
2Q
3D
3D
40
40
GND
COtmlOl.
CONTROL
TL/F/5367-2
TUF/5367-1
Top View
Top View
Order Number MM54HCT373J, MM54HCT374J,
MM74HCT373J, N, or MM74HCT374J, N
See NS Package J20A or N20A
4·75
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
-0.5 to +7.0V
Supply Voltage (Vee)
DC Input Voltage (VIN)
-1.5 to Vee + 1.5V
Supply Voltage (Vee>
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
±20mA
DC Input or Output Voltage
(VIN. VQUT)
Operating Temp. Range (TAl
MM74HCT
MM54HCT
Clamp Diode Current (11K. 10K>
DC Output Current. per pin (lOUT)
±35mA
DC Vee or GND Current. per pin (lee)
±70mA
Storage Temperature Range (TSTG)
-65"C to + 150"C
Power Dissipation (Po) (Note 3)
Max
5.5
Units
V
0
Vee
V
-40
-55
+85
+125
"C
"C
500
ns
Input Rise or Fall Times
(tr• tf)
500mW
Lead Temp. (TU (Soldering 10 seconds)
Min
4.5
260"C
DC Electrical Characteristics Vee = 5V ± 10% (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25"C
Typ
74HCT
TA= -40t085"C
54HCT
TA= -55 to 125"C
Units
Guaranteed Limits
VIH
Minimum High Level "
Input Voltage
2.0
2.0
2.0
V
VIL
Maximum Low 'Level
Input Voltage
0.8
0.8
0.8
V
VOH
Minimum High Level
Output Voltage
VIN= VIH or VIL
IIOUTI = 20 p.A
IIOUTI = 6.0 mAo Vee = 4.5V
IIOUTI=7.2 mAo Vee=5.5V
Vee
4.2
5.7
Vee- 0.1
3.98
4.98
Vee- 0.1
3.84
4.84
Vee- 0•1
3.7
4.7
V
V
V
Maximum Low Level
Voltage
VIN = VIH or VIL
IIOUTI = 20 p.A
IIOUTI = 6.0 mAo Vee=4.5V
IIOUTI=7.2 mAo Vee=5.5V
0
0.2
0.2
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
liN
Maximum Input
Current
VIN=vee or GND.
VIHorVIL
±0.1
±1.0
±1.0
p.A
IOZ
Maximum TRI-STATE
Output Leakage
Current
VOUT= Vee or GND
Enable=VIH orVIL
±0.5
±5.0
±10
p.A
Icc
Maximum Quiescent
Supply Current
VIN=VeeorGND
IOUT=O"p.A
8.0
80
.160'
p.A
VIN = 2.4V or 0.5V (Note 4)
1.0
1.3
1.5
mA
VOL
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages ere referenced to ground.
Note 3: Power Dissipation temperature derating Note
4:
plastic "N" package: -12 mWrC from 65"C to 85'C; ceramic "J" package: -12 mWrC from 100'C to 125"C.
Measured per pin. All others tied to Vee or gro~nd.
4-76
AC Electrical Characteristics
MM54HCT373/MM74HCT373
Vcc=5.0V, tr=t,=6 ns TA=25'C (unless otherwise specified)
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
tpHL, tpLH
Maximum Propagation Delay
Data to Output
CL =45pF
18
25
ns
tpHL, tpLH
Maximum Propagation Delay
Latch Enable to Output,
CL=45pF
21
30
ns
tpZH, tpZL
Maximum Enable Propagation Delay
Control to Output
CL =45pF
RL=1 kO
20
28
ns
tpHZ, tpLZ
Maximum Disable Propagation Delay
Control to Output
CL =5pF
RL =1 kO
18
25
ns
tw
Minimum Clock Pulse Width
16
ns
ts
Minimum Setup Time Data to Clock
5
ns
tH
Minimum Hold Time Clock to Data
10
ns
AC Electrical Characteristics MM54HCT373/MM74HCT373
Vcc=5.0V ±10%, t r=t,=6 ils (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25'C
74HCT
54HCT
TA= -40 to 85'C TA= -55 to 125'C
Typ
Units
Guaranteed Limits
tpHL, tpLH
Maximum Propagation
Delay Data to Output
CL =50pF
CL=150pF
22
30
30
40
37
50
45
60
ns
ns
tpHL, tpLH
Maximum Propagation Delay
Latch Enable to Output
CL =50 pF
CL =150pF
25
32
35
45
44
56
53
68
ns
ns
tpZH, tpZL
Maximum Enable Propagation
Delay Control to Output
CL =50pF
CL =150pF
RL =1 kO
21
30
30
40
37
50
45
60
ns
ns
tpHZ, tpLZ
Maximum Disable Propagation
Delay Control to Output
CL =50pF
RL =1 kO
21
30
37
45
ns
tw
Minimum Clock Pulse Width
16
20
24
ns
ts
Minimum Setup Time Data to Clock
5
6
8
ns
tH
Minimum Hold Time Clock to Data
10
13
20
ns
CIN
Maximum'lnput CapaCitance
10
10
10
pF
20
20
20
pF
COUT
Maximum Output CapaCitance
CPO
Power Dissipation CapaCitance (Note 5)
pF
pF
G=Vcc
G=GND
"
Truth Table
'373
Output
Control
LE
Data
L
L
L
H
H
H
L
X
H
L
X
X
'374
373
Output
573
Output
Output
Control
H
L
00
L
H
00
Z
Z
L
L
L
H
H = high level, L = low level
00 ;. level of output before steady·state Input conditions
Clock
Data
Output
(374)
Output
(534)
t
,t
H
L
X
X
H
L
00
Z
L
H
00
Z
L
X
H = High Level, L = Low Level
X = Don't Care
t = Transition from low·to·hlgh
Z = High impedance state
00 = The level of the output before staady state Input conditions
were established.
were established,
Z = high Impedance
4-77
AC Electrical Characteristics MM54HCT374/MM74HCT374
Vcc=5.0V. tr=tf=6 ns TA=25°C (unless otherwise specified)
Symbol
Parameter
·Condltlons
Typ
Guaranteed
Limit
Units
fMAX
Maximum Clock Frequency
50
30
MHz
tpHL. tpLH
Maximum Propagation Delay
to Output
CL =45pF
20
32
ns
tPZH. tPZL
Maximum Enable Propagation Delay
Control to Outpu1
CL =45 pF
RL=1kG
19
28
ns
tpHZ. tpLZ
Maximum Disable Propagation Delay
Control to Output
CL =5pF
RL =1 kG
17
25
ns
tw
Minimum Cloc~ Pulse Width
20
ns
ts
Minimum Setup Time Data to Clock
5
ns
tH
Minimum Hold TIme Clock to Data
16
ns
-
AC Electrical Characteristics MM54HCT374/MM74HCT374
Vcc=5.0V ±10%. t,=tf=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25"C
Typ
Maximum Clock Frequency
. 74HCT
54HCT
TA= -40to85°C TA= -55 to 125°C Units
Guaranteed Limits .
30
24
20
MHz
tpHL. tpLH Maximum Propagation Delay
toOLltput
CL =50pF
22
CL =150pF 30
36
46
45
57
48
69
ns
ns
tPZH. tpZL Maximum Enable Propagation
Delay Control to Output
CL =50 pF
21
CL =150 pF 30
RL =1 kG
30
40
37
50
45
60
ns
ns
tpHZ. tpLZ Maximum Disable Propagation
Delay Control to Output
CL =50pF
RL =1 kG
30
37
45
ns
fMAX
21
.
tw
Minimum Clock Pulse Wi«;ith
16
20·
24
ns
ts
Minimum Setup TIme Data to Clock
20
25
30
ns
lH
Minimum Hold Time Clock to Data
5
5
5
ns
CIN
Maximum Input Capacitance
10
10
10
pF
GoUT
Maximum Ou1put Capacitance
20
20
20
pF
CPD
Power Dissipation Capacitance (Note 5) G=Vcc
G=GND
pF
pF
Note 5: CPO dete,mines the no load pawe,consumption, Po=Cpo Vr;;c2 f+lee Vee, and the no load dynamic current consumption, Is=Cpo Vee f+ Icc-
4-78
i:
i:
Logic Diagrams
10
CI'I
""::::E:
20
3D
MM54HCT373/MM74HCT373
40
50
~
Co)
60
70
.....
....i:
80
Co)
i:
.....
""::::E:
~
Co)
.....
Co)
......
i:
i:
LATCH
ENABLE
(LEI
CI'I
""::::E:
(')
-I
OUTPUT
CONTROL
(OCI.
Co)
.....
1Q
2Q
4Q
3Q
5Q
8Q
7Q
8Q
Tt/F/5367-4
....
""
i:
i:
.....
""::::E:
~
Co)
10
.....
MM54HCT374/MM74HCT374
40
30
50
20
60
70
""
80
CLOCK
(CK)
OUTPUT
CONTROL
(OC)
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
TL/F/5367-5
4·79
,- .-------------------~----------------------------------------------------------~
e ~National
N
~ ~ Semiconductor
\
~J
~_..../
microCMOS
:Ii!
~ MM54HCT521/MM74HCT521
~ 8-Bit Magnitude Comparator
~ (Equality Detector)
ID
I
General Description
This equality detector utilizes microCMOS Techno'iogy, 3.0
micron silicon gate N-well CMOS to compare bit for bit two
8-bit words and indicate whether or not they are equal. The
P = Q output indicates equality when it is low. A single active
low enable is provided to facilitate caScading of several
packages and enable comparison of words greater than 8
bits.
This device is useful in memory block decoding applications, where memory block enable Signals must be generated from computer address information.
The comparator combines the low power consumption of
CMOS, but inputs are compatible with TIL logic levels, and
the output can drive 10 low power Schottky equivalent
loads.
MM54HCTIMM74HCT devices are intended to interface betWeen TIL and NMOS components and standard CMOS
devices. These parts are also plug in replacements for LSTIL devices and can be used to reduce power consumption
in existing designs.
All inputs are protected from damage due to static discharge by diodes to Vee and ground.
Features
•
•
•
•
TIL input compatible
Typical propagation delay: 20 ns
Low quiescent current: 80 p.A maximum (74HCT Series)
Large output current: 4 mA
Connection and Logic Diagrams
Vcc P
=a
Dual-In-Une Package
07
P7
06
P6
05
P5
04
P4
11
»-I(;>o--t::>o""(1",",,") -.=-0
10
PO
00
P1
01
P2
02
P3
03
GNO
TL/F/6122-1
Top View
Order Number MM54HCT521J or MM74HCT521J,N
See NS Package J20,A or N20A '
Truth Table
Inputs
ii
Oats
Enable
P,Q
G
P=Q
P>Q
P
DC Input Voltage (VIN)
-1.5 to Vee + 1.5V
Supply Voltage (Vee)
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TAl
MM74HCT
MM54HCT
DC Output Current. per pin (lOUT)
±20mA
±35mA
DC Vee or GND Current. per pin (ICe>
±70mA
Clamp Diode Current (11K. 10K>
Storage Temperature Range (TSTG)
- 65·C to + 150·C
Power DiSSipation (Po) (Note 3)
0
Vee
Units
V
V
.-
-40
-55
+85
+125
·C
·C
500
ns
260·C
DC Electrical Characteristics Vee =
Parameter
Max
5.5
Input Rise or Fall Times
(tr. t,)
500mW
Lead Temp. (Tu (Soldering 10 seconds)
Symbol
-
Min
4.5
5V ±10% (unless otherwise specified)
Conditions
74HCT
TA= -40 to 85"C
TA=25"C
Typ
54HCT
TA=-55to125"C
Units
Guaranteed Umlts
VIH
Minimum High Level
Input Voltage
2.0
2.0
2.0
V
VIL
Maximum Low Level
Input Voltage
0.8
0.8
0.8
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
ilOUTI=20/LA
ilOUTI=6.0 mAo Vcc=4.5V
ilOUTI=7.2 mAo VcC=5.5V
Vee
4.2
'5.2
Vee- 0.1
3.98
4.98
VCC- 0.1
3.84
4.84
Vee- 0•1
3.7
4.7'
V
V
V
Maximum Low Level
Voltage
VIN=VIH orVIL
IIOUTI=20 /LA
ilOUTI=6.0 mAo VCC=4.5V
ilOUTI=7.2 mAo VcC=5.5V
0
0.2
0.2
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
Maximum Input
VIN=VCtor GND.
ViHorVIL
±0.1
±1.0
±1.0
/LA
±0.5
±5.0
±10
/LA
8.0
80
160
/LA
VOL
liN
Current
loz
Maximum TRI·STATE
Output Leakage
Current
VouT=VeeorGND
Enable=VIH
IcC
Maximum ,Quiescent
Supply Current
VIN=VCCorGND
10UT=0/LA
mA
VIN = 2.4V or 0.5V (Note 4)
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specHled all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mWrC from 65'C to 85"C; ceramic "J" package: -12 mWrC from l00'C to 125'C.
Note 4: Measured per pin. All others tied to Vee or ground,
.
AC Electrical Characteristics MM54HCT533/MM74HCT533
Vcc=5.0V. t r =tf=6 ns. TA=25'C (unless otherwise specified)
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
tpHL. tpLH
Maximum Propagation Delay
Data to Output
CL =45 pF
18
25
ns
tpHL. tpLH
Maximum Propagation Delay
Latch Enable to Output
CL =45pF
21
30
ns
tpZH. tPZL
Maximum Enable Propagation Delay
Control to Output
CL =45 pF
RL =1 kO
20
28
ns
tPHZ, tpLZ
Maximum Disable Propagation Delay
Control to Output
CL=5pF
RL =1 kO
18
25
ns
tw
Minimum Clock Pulse Width
16
ns
ts
Minimum Setup Time Data to Clock
5
ns
tH
Minimum Hold Time Clock to Data
10
ns
AC Electrical Characteristics MM54HCT533/MM74HCT533
Vcc=5.0V ±10%. tr=tf=6"ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25'C
Typ
74HCT
TA=-40t085"C
54HCT
TA= -55 to 125'C
Units
Guaranteed Limits
tpHL. tpLH
Maximum Propagation
Delay Data to Output
CL=50pF
CL=150pF
22
30
30
40
37
50
45
60
ns
ns
tpHL. tpLH
Maximum Propagation Delay
Latch Enable to Output
CL =50pF
CL =150 pF
25
32
35
45
44
56
53
68
ns
ns
tPZH. tPZL
Maximum Enable Propagation"
Delay Control to Output
CL =50pF
CL =150 pF
RL =1 kO
21
30
30
40
37
50
45
60
ns
ns
tpHZ. tpLZ
Maximum Disable Propagation
Delay Control to Output
CL =50pF
RL=1 kO
21
30
37
45
ns
tw
Minimum Clock Pulse Width
16
20
24
ns
is
Minimum Setup Time Data to Clock
5
6
8
ns
tH
Minimum Hold Time Clock to Data
10
13
20
ns
CIN
Maximum Input Capacitance
10
10
10
pF
COUT
Maximum Output Capacitance
20
20
20
pF
CPO
Power Dissipation Capacitance (Note 5)
G=Vcc
G=GND
4-85
,
pF
pF
AC Electrical Characteristics MM54HCT534/MM74HCT534
Vcc=5.0V. t r =tf=6 ns. TA=25°C (unless otherwise specified)
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
fMAX
Maximum Clock Frequency
50
30
MHz
tpHL. tpLH
Maximum Propagation Delay
to Output
CL =45 pF
20
32
ns
tPZH. tpZL
Maximum Enable Propagation Delay
Control to Output
CL =45 pF
RL =1 kO
19
28
ns
tpHi. tpLZ
Maximum Disable Propagation Delay
Control to Output
CL=5pF
RL =1 kO
17
25
ns
-
tw
ts
Minimum Clock Pulse Width
20
ns
Minimum Setup TIme Data to Clock
5
ns
lH
Minimum Hold TIme Clock to Data
16
ns
,
AC Electrical Characteristics MM54HCT534/MM74HCT534
Vcc=5.0V ±10%. tr=tf=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA=2SoC
Typ
Guaranteed Limits
24
20
MHz
tpHL. tpLH Maximum Propagation Delay
to Output
CL =50pF 22
CL=150pF 30
36
46
45
57
48
69
ns
ns
tPZH. tpZL Maximum Enable Propagation
Delay Control to Output
21
CL =50pF
CL=150pF 30
RL=1 kO
30
40
37
50
45
60
ns
ns
tpHZ. tpLZ Maximum Disable Propagation
CL=50pF
RL =1 kO
21
30
37
45
ns
fMAX
Maximum Clock Frequency
74HCT
S4HCT
TA=-40to85"C TA=-SSto12SoC Units
Delay Control to Output
30
tw
Minimum Clock Pulse Width
16
20
24
ns
ts
Minimum Setup Time Data to Clock
20
.25
30
ns
tH
Minimum Hold Time Clock to Data
5
5
5-
ns
CIN
Maximum Input Capacitance
10
10
10
pF
CoUT
Maximum Output Capacitance
20
20
20
pF
Cpo
Power Dissipation Capacitance (Note 5) G=VCC
G=GND
pF
pF
Note 5: Cpo determines the no load power consumption. Po=Cpo vex? 1+ lee Vee. and the no load dynamic current consumption, Is=Cpo Vee 1+ lee.
,
4-86
3:
3:
Connection Diagram
c.n
~
::I:
0
Dual-In-Llne Package
Vee
80
8D
7D
ro
50
6D
SD
sa
....
LATCH
ENABLE
c.n
Co)
G
.....
Co)
3:
3:
....
~
::I:
0
....c.n
Co)
Co)
.....
3:
3:
c.n
~
::I:
~
c.n
Co)
.co.
.....
3:
OUTPUT
CONTROL
TL/F/6123-1
....3:
~
Top View
::I:
~
c.n
Co)
~
Order Number MM54HCT533J or MM74HCT533J, N
See NS Package J20A or N20A
vee
au
BD
7D
Dual-In-Line Package
7Q
6li
6D
5D
50
CLOCK
III
TUF/6123-2
Top View
Order Number MM54HCT534J or MM74HCT534J, N
See NS Package J20A or N20A
4·87
~ r-------------------------------~----------------------------------------------_.
~ '?A National
:J:
~
PRELIMINARY
\
~ Semiconductor
J
microCMOS
:::E
:::E
.....
MM54HCT540/MM74HCT540
Inverting Octal TRI-STATE® Buffer
G
:J: MM54HCT541/MM74HCT541
'Oil'
an
:::E Octal TRI-STATE Buffer
~
:::E
c:; General Description
~
:J:
. 'Oil'
.....
:::E
:::E
.....
~
~
~
an
:::E
::E
These TRI-STATE buffers utilize microCMOS Technology,
3.0 micron silicon gate N-well CMOS, and are general purpose high speed inverting and non-inverting buffers. They
possess high drive current outputs which enable high speed
operation even when driving large bus capacitances. These
circuits achieve speeds comparable to low power Schottky
devices, while retaining the low power consumption of
CMOS. 90th devices are TIL input compatible and have a
fanout of 15 LS-TIL equivalent inputs.
MM54HCTIMM74HCT devices are intended to interface between TIL and NMOS components and standard CMOS
devices. These parts are also plug-in replacements for LSTTL devices and can be used to reduce power consumption
in existing designs.
The MM54HCT540/MM74HCT540 is an inverting buffer
and the MM54HCT541/MM74HCT541 is a non-inverting'
buffer. The TRI-STATE control gate operates as a two-input
NOR such that if either G 1 or G2 are high, all eight outputs
are in the high-impedance state.
In order to enhance PC board layout, the 'HCT540 and
'HC1541 offers a pinout having inputs and outputs on opposite sides of the package. All inputs are protected f(om damage due to static discharge by diodes to Vee and ground.
Features
•
•
•
•
•
TTL input compatible.
Typical propaga~ion delay: 12 ns
TRI-STATE outputS for connection to system buses
Low quiescent current: 80 p.A
Output current: 6 rnA
Connection Diagrams
Dual-In-Llne Package
iii
~
I
nI
nI
~
"
H
~
n
~
A1
A2
A3
A4
A5
A6
A7
AI
GND
I
iii
~
Y1
Y2
Y3
Y4
Y5
YI
n
A1
A2
A3
A4
A5
AI
A7
AI.
ya
GNO
TL/F/6D40-2
TUF/6D40-1
Top View
Top View
Order Number MM54HCT540J, MM54HCT541J, MM74HCT540J, N or MM74HCT541J, N
.
See NS Package J2~A or N20A
4-88
Absolute Maximum Ratings (Notes 1 8. 2)
Operating Conditions
-0.5 to + 7.0V
Supply Voltage (VeC>
DC Input Voltage (VIN)
-'1.5 to Vee + 1.5V
Supply Voltage (Vee)
DC Output Voltage (VOUT)
- 0.5 to Vee + 0.5V
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TAl
MM74HCT
MM54HCT
Clamp Diode Current (11K. 10K>
±20mA
DC Output Current. per pin (lOUT)
±35mA
DC Vee or GND Current. per pin (IcC>
±70mA
\
-65·C to + 150'C
Storage Temperature Range (T8TG)
Power Dissipation (Po) (Note 3)
Max
5.5
Units
V
0
Vee
V
-40
-55
+85
+125
·C
·C
500
ns
Input Rise or Fall Times
(tr• tf)
500mW
lead Temp. (TtJ (Soldering 10 seconds)
Min
4.5
260'C
,
DC Electrical Characteristics Vee = 5V ± 10% (unless otherwise specified)
Parameter
Symbol
TA=25'C
Conditions
Typ
74HCT
TA= -40 to 85'C
54HCT
TA= -55 to 125'C
Unite
Guaranteed Limits
VIH
Minimum High level ,
Input Voltage
2.0
2.0
2.0
V
VIL
Maximum Low Levei
Input Voltage
0.8
0.8
0.8
V
VOH
Minimum High Level
Output Voltage
VIN=VIH orVIL
IiOUTI=20Jl-A
116uTI=6.0 mAo Vee=4.5V
IIOUTI=7.2 mAo Vee=5.5V
Vee
4.2
5.2
Vee- 0.1
3.98
4.98
Vee- 0.1
3.84
4.84
Vec- 0.1
3.7
4.7
V
V
V
Maximum Low Level
Voltage
VIN = VIH or VIL
IIOUTI = 20 Jl-A
IIOUTI = 6.0 mAo Vee = 4.5V
IiOUTI=7.2 mAo Vee=5.5V
0
0.2
0.2
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
liN
Maximum Input
Current
VIN=VeeorGND
±0.1
±1.0
±1.0
/LA
loz
Maximum TRI·STATE
Output Leakage
Current
VOUT=VecorGND
G=VIH
±0.5
±5.0
±10
p.A
Icc
Maximum Quiescent
Supply Curr!!nt
VIN=VecorGND
10UT=OJl-A
8.0
80
160
Jl-A
1.0
1.3
1.5
nA
VOL
VIN = 2.4V or 0.4V (Note 4)
Note 1:
Nota 2:
Note 3:
Nota 4:
0.6
Absolute Maximum Ratings are those values beyond which damage to tihe davice may occur.
Unless otiherwise specified all vollsges are referenced to ground.
Power Dissipation temperature derating - plastic "N'" package: -12 mW/'C from 65'C to 85'C; ceramic ••J'" package: -12 mW/'C from'l OO'C to 125'C.
Measured per input. All otihar inputs at Vcc or GND.
AC Electrical Characteristics MM54HCT540/MM74HCT540
Vee=5.0V. tr =tf=6 ns. TA=25·C. (unless otherwise specified)
Symbol
Parameter
Conditions
Typ
Guaranteed
Limits
Unite
tpHL. tpLH
Maximum Output
Propagation Delay
CL=45 pF
12
18
ns
tpZL. tPZH
Maximum Output
Enable Time
'CL =45pF
RL =1 kO
14
28
ns
, tpLZ. tpHz
Maximum Output
Disable Time
CL =5pF
RL =1 kO
13
25
ns
4·89
•
AC Electrical Characteristics MM54HCT540/MM74HCT540
Vcc'=5.0V ± 10%. l,-=t,=6 ns (unless otherwise specified)
Symbol
Parameter
74HCT
TA= -40t085"C
TA=25"C
Conditions
Typ
tpHL. tpLH
tpZH. tpZL
tpHZ. tpLz
Maximum Output
Propagation Delay
Units
Guaranteed Limits
CL =50pF
12
20
25
30
ns
CL=150pF
22
30
38
45
ns
ns
Maximum Output
Enable Time
RL = 1 k.!l
Maximum Output
Disable Time
IrHL. tTLH - Maximum Output
Rise and Fall Time
54HCT
TA= -55 to 125°C
I CL =50pF
15
30
38
45
20
40
50
60
ns
RL =1 k.!l
CL =50pF
15
30
38
45
ns
CL =50pF
6
12
15
18
ns
I CL =150 pF
C,N
Maximum Input
Capacitance
5
10
10
10
pF
GoUT
Maximum Output
Capacitance
15
20
20
20
pF
CPD
Power Dissipation
Capacitance (Note 5)
(per output)
AC Electrical Characteristics
12
50
§.=Vcc
G=GND
pF
pF
MM54HCT541/MM74HCT541
Vcc=5.0V. t r =t,=6 ns. TA=25'C. (unless otherwise specified)
Symbol
Parameter
Conditions
Typ
Guaranteed
Limits
Units
tpHL. tpLH
Maximum Output
Propagation Delay
CL =45 pF
13
20
ns
tPZL. tPZH
Maximum Output
Enable Time
CL =45 pF
RL = 1 k.!l
17
28
ns
tpLZ. tpHZ
Maximum Output
Disable Time
CL =5pF
RL = 1 k.!l
15
25
ns
AC Electrical Characteristics
MM54HCT541/MM74HCT541
Vcc=5.0V ±10%. tr =t,=6 ns (unless otherwise specified)
Symbol
Parameter
TA=25'C
Conditions
Typ
tpHL. tpLH
Maximum Output
Propagation Delay
74HCT
-TA= -40 to 85°C
54HCT
TA= -55 to 125'C
Units
Guaranteed Limits
CL =50pF
14
23
29
34
CL=150pF
17
33
42
49
ns
17
30
38
45
ns
I CL=50pF
I CL =150pF
ns
tPZH. tPZL
-Maximum Output
Enable Time
RL = 1 k.!l
22
40
50
60
ns
tpHZ, tpLZ
Maximum Output
Disable Time
RL =1 kO
CL =50pF
17
30
38
45
ns
tTHL. tTLH
Maximum Output
Rise and Fall Time
CL =50pF
6
12
15
18
ns
CIN
Maximum Input
Capacitance
5
10
10
10
pF
GoUT
Maximum Output
Capacitance
15
20
20
20
pF
pF
12
G=Vcc
G=GND
45
pF
Note 5: CPO determines the no load dynamic power consumption. Po= Cpo Vee!- 1+ lee Vee. and the no load dynamic current consumption. Is = Cpo Vee 1+ lee.
CPD
Power Dissipation
Capacitance (Note 5)
(per output)
,
4-90
~National
PRELIMINARY
~ Semiconductor
\
~
microCMOS
MM54HCT563/MM74HCT563
TRI-STATE® Octal D-Type Latch with
Inverted Outputs
General Description
These high speed octal Ootype latches utilize microCMOS
Technology, 3.0 micron silicon gate N-well CMOS. They
possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as 'well as the
ability to drive 15 LS-TTL loads. Due to the large output
drive capability and the TRI-STATE feature, these devices
are ideally suited for interfacing with bus lines in a bus organized system.
When the LATCH ENABLE (LE) input is high, the 0 outputs
will follow the inversion of the 0 inputs. When the LATCH
ENABLE goes low, data at the 0 inputs will be retained at
the outputs until LATCH ENABLE returns high again. When
a high logic level is applied to the OUTPUT-CONTROL (OC)
input, all outputs go to a high impedance state, regardless
of what signals are present at the other inputs and the state
of the storage elements.
The 54HCT/74HCT logic family is speed, function and pinout compatible with the standard 54LS174LS logic family.
All inputs are protected from damage due to static discharge by internal diode clamps to Vee and ground.
Features
•
•
•
•
•
•
Low input current: 1 ,...A maximum
Low quiescent current: 80 p.A maximum (74 Series)
Compatible with bus-oriented systems
Output drive capability: 15 LS-TTL loads
TTL input characteristic compatible
Functionally compatible with 54174LS580
Connection Diagram
Dual-In-Llne Package
V~
~
~
~
~
~
~
~
LATCH
~ ~U~
11
10
OUTPUT 10
CONTROL
20
3D
40
50
6D
70
8D
GNO
TL/F/S041-1
Order Number MM54H'CT563J or MM74HCT563J,N
See NS Package J20A or N20A
Truth Table
Output
Control
Latch
Enable
L
L
L
H
H
H
L
X
Data
Output
H
L
L
H
·00
Z
X
X
H
= high level, L = low level
= level of output before steady·state input
00
conditions were established
Z
X
4-91
= high impedance
= don't care
Op~rating
Absolute Maximum Ratings (Notes 1 &12)
Supply Voltage (Vee)
Conditions
-0.5 to + 7.0V
DC Input Voltage (VIN)
-1.5 to Vee + 1.5V
Supply Voltage (Vee)
DC Output Voltage (VOUT)
-0.5 to Vee+0.5V
±20mA
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TAl
MM74HCT
MM54HCT
Clamp Diode ~urrent (11K, 10K>
DC Output Current, per pin (lOUT)
DC Vee or GND Current, per pin (Icc>
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
Lead Temperature (Tu
(Soldering 10 seconds)
±35mA
±70mA
- 65'C to + 150'C
500mW
Parameter
Max
5.5
Units
V
0
Vee
V
-40
-55
+85
+125
'C
'C
500
ns
Input Rise or Fall TImes
(tr, t,)
2600C
DC Electrical Characteristics
Symbol
Min
4.5
Vee=5V ±10% (unless otherwise specified)
TA=25"C
Conditions
Typ
74HCT
TA=-40to8S'C
54HCT
TA=-55to125"C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0
2.0
2.0
V
VIL
Maximum Low Level
Input Voltage
0.8
0.8
0.8
V
VOH
Minimum High Level
Output Voltage
VIN=VIHorVIL
!IOUT!=20 p.A
!IOUT!=6.0 mA, Vee=4.5V
ilOUT!=7.2 mA, Vee=5.5V
Vee
4.2
5.7
Vee- 0.1
3.98
4.98
Vee-0.1
3.84
4.84
Vee- 0.1
3.7
4.7
V·
V
V
Maximum Low Level
Voltage
ViN=VIHorVIL
!IOUT! = 20 p.A
!IOUT!=6.0mA, Vee=4.5V
!IOUT!=7.2 mA, Vee=5.5V
0
0.2
0.2
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
liN
Maximum Input
Current
VIN=VeeorGND, VIH orVIL
±0.1
±1.0
±1.0
p.A
loz
Maximum TRI-STATE
Output Leakage
Current
VOUT=vee or GND
OC=VIH
±0.5
±5.0
±10
p.A
Icc
Maximum Quiescent
Supply Current
VIN=VeeorGND
10UT=0p.A
8.0
80
160
p.A
VOL
VIN = 2.4V or 0.4V (Note 4)
mA
Note 1: Absolute Maximum Ratings are those vatues beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating - plastic "N" package: -12 mW I'C from 65'C to 85'C; ceramic "J" package: -12 mW
Note 4: Measured per pin. All others tied to Vee or ground.
4-92
rc from 100'C to 125'C.
.
AC Electrical Characteristics MM54HCT563/MM74HCT563
Vcc=5.0V. tr =tf=6 ns TA=25'C (unless otherwise specified)
Symbol
Conditions
Propagation Delay
CL =45pF
ns
tpHL. tpLH
Maximum Propagation Delay
Latch Enable to Q
CL =45 pF
ns
tPZH. tPZL
Maximum Output Enable Time
CL =45pF .
RL = 1 kn
ns
tpHZ. tpLZ
Maximum Output Disable Time
CL =5pF
RL =1 kO
ns
tw
Minimum Pulse Width LE or Data
ns
Is
Minimum Setup Time Data to LE
ns
tH
Minimum Hold Time LE to Dala
ns
tpHL. tpLH
Maximu~
Typ
Guaranteed
Limit
Parameter
Units
DatatoQ
AC Electrical Characteristics MM54HCT563/MM74HCT563
Vcc=5.0V ± 10%. t r =tf=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25'C
Typ
74HCT
TA= -40to 85'C
54HCT
TA = -55 to 125'C
Units
Guaranteed Limits
tpHL. tpLH
Maximum Pro~gation
Delay Data to Q
CL =50pF
CL =150 pF
22
30
ns
ns
tpHL. tpLH
Maximum Propallation Delay
Latch Enable 10 Q
CL =50 pF
CL =150 pF
25
32
ns
ns
tPZH. tPZL
Maximum Output Enable Time
CL =50 pF
CL=150pF
RL =1 kO
21
30
ns
ns
ipHZ.lpLZ
Maximum Output Disable Time
CL =50 pF
RL =1 kn
21
ns
tw
Minimum Pulse Width LE or Data
ns
ns
Is
Minimum Setup Time Data to LE
tH
Minimum Hold TIme LE to Data
ns
CIN
Maximum Input Capacitance
pF
COUT
Maximum Output Capacitance
CPO
Power Dissipation Capacitance (Note 5)
pF
OC=Vcc
OC=GND
4-93
pF
pF
~National
PRELIMINARY
~ semiconductor
r: ::J
I:
. microCMOS
MM54HCT564/MM74HCT564
TRI-STATE ® Octal D-Type Flip-Flop
with Inverted Outputs
General Description
These octal Ootype flip-flops utilize microCMOS Technology, 3.0 micron silicon gate N-well CMOS. They possess the:
high noise immunity and low power consumption of standard CMOS integrated circuits as well as the ability to drive
15 LS-TTL loads. Due to the large output drive capability
and the TRI-STATE feature, these devices are ideally suited
for interfacing with bus lines in a bus organized system.
These devices are positive edge triggered flip-flops. Data at
the 0 inputs, meeting the set-up and hold time requirements, are transferred to the 0 outputs on positive going
transitions of the CLOCK (CK) input. When a high logic level
is applied to the OUTPUT CONTROL (OC) input, all outputs
go to a high impedance state, regardless of what signals are
present at the other inputs and the state of the storage
elements.
Connection Diagram
Vee
111
OUTPUT 10
CONTROL
The 54HCTI74HCT logic family is speed, function, and pinout compatible with the standard 54LS174LS logic family.
All inputs are protected from damage due to static discharge by internal diode clamps to Vee and ground.
Features
..
•
•
•
•
•
Low input current: 1 /LA maximum
Low quiescent current: 80 /LA maximum (74 Series)
Compatible with bus-oriented systems
Output drive capability: 15 LS-TTL loads
TTL input characteristic compatible
Functionally compatible with 54LS576174LS576
Dual-In-Llne Package
2iI 311 .to 511 611 711
ail CLOCK
2D
6D
30
40
50
6D
70
GNO
TLlF/6D42-1
Top View
Order Number MM54HCT564J or MM74HCT564J, N
See NS Package J20A or N20A
Truth Table
Output
Control
L
L
L
H
Clock
Data
Output
t
t
H
L
L
H
b.
X
X
X
H = High Level, L = Low Level
00
X
Z
Don't Cere
= Transition from low-to-high
Z =. High Impedance State
00 = The level of the output before steady state
Input conditions were established
=
t
4-94
Absolute Maximum Ratings (Notes 1 & 2)
Supply Voltage (Vee>
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K, 10K>
DC Output Current, per pin (lOUT)
DC Vee or GND Current, per pin (lee)
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
Lead Temperature (TL>
(Soldering 10 seconds)
Operating Conditions
-0.5 to +7.0V
-1.5toVee+ 1.5V
-0.5 to Vee+0.5V
±20mA
±35mA
±70mA
-65·C to + 150·C
500mW
Supply Voltage (Vee>
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TN
MM74HCT
MM54HCT
Input Rise or FaU Times
(tr, tf)
Min
4.5
0
Max
5.5
Vee
Units
V
V
-40
-55
+85
+125
·C
·C
500
ns
260·C
DC Electrical Characteristics
Vee = 5V ± 1.0% (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25·C
74HCT
TA= -40 to 85·C
54HCT
TA= -55to 125·C
Units
Guaranteed Limits
TyP
VIH
Minimum High Level
Input Voltage
2.0
2.0
2.0
V
VIL
Maximum Low Level
Input Voltage
0.8
0.8
0.8
V
VOH
Minimum High Level
Output Voltage
VIN=VIH orVIL
IIOUTI=20 p.A
IIOUTI =6.0 mA, Vee=4.5V
IIOUTI = 7.2 mA, Vee = 5.5V
Vee
4.2
5.2
Vee- 0.1
3.98
4.98
Vee- 0.1
3.84
4.84
Vee- O.1
3.7
4.7
V
V
V
Maximum Low Level
Voltage
VIN = VIH or VIL
IIOUTI=20 p.A
ilOUTI = 6.0 mA, Vee= 4.5V
IIOUTI=7.2 mA, Vee=5.5V
0
0.2
0.2
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
p.A
VOL
,
\
liN
Maximum Input
Current
VIN = Vee or GND,
VIAorVIH
±0.1
±1.0
±1.0
loz
Maximum TRI-STATE
Output Leakage
Current
VOUT=VeeorGND
OC=VIH
±0.5
±5.0
±10
Icc
Maximum Quiescent
Supply Current
VIN=VeeorGND
10UT=0 p.A
8.0
80
160
Nole 1:
Note 2:
Note 3:
Note 4:
_.
p.A
p.A
mA
VIN = 2.4V or 0.5V (Note 4)
Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Unless otherwise specifled all vol18ges are referenced to ground.
Power Dissipation temperature derating - plastiC "N" package: -12 mW"C from 65'C to 65'C; ceramic "J" package: -12 mWrc from 1OO"C to 125·C.
Measured per pin. All others tied to Vee or ground.
4-95
•
AC
EI~ctrical
Characteristics MM54HCT564/MM74HCT564
Vcc=5.0V. tr =tf=6 ns. TA=25'C (unless otherwise specified)
Symbol
Parameter
Conditions
Typ
Guaranteed
LImit
Units
fMAX
Maximum Clock Frequency
50
MHz
tpHL. tpLH
Maximum Propagation Delay
Clock to Q
CL =45pF
20
ns
tPZH. tpZL
Maximum Enable Propagation Delay
Output Enable Time
CL =45pF
RL =1 kO
19
ns
tpHZ. tpLZ
Maximum Disable Propagation Delay
Output Disable Time
CL =5 pF
RL =1 kO
17
ns
tw
Minimum Clock Pulse Width
ns
Is
Minimum Setup Time Data to Clock
ns
tH
Minimum Hold Time Clock to Data
ns
AC Electrical Characteristics MM54HCT564/MM74HCT564
Vcc=5.0V ± 10%. tr=tl':=6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA=25'C'
Typ
74HCT
TA=-40tu85'C
54HCT
TA= -55to 125'C
Units
Guaranteed Limits
fMAX
Maximum Clock
Frequency
tpHL. tpLH
Maximum Propagation Delay
ClocktoQ
CL =50 pF
CL =150 pF.
22
30
ns
ns
tpZH. tPZL
Maximum Enable Propagation
Output Enable Time
CL =50pF
CL=150pF
RL =1 kfl
21
30
ns
ns
,tpHZ. tpLZ
Maximum Disable Propagation
Output Disable Time
CL =50 pF
RL =1 kO
21
ns
MHz
tw
Minimum Clock Pulse Width
ns
ts
Minimum Setup TilTle Data to Clock
ns
tH
Minimum Hold Time Clock to Data
ns
tr• tf
Maximum Clock Input
Rise and Fall Time
ns
tTHL. tTLH
Maximum Output Rise
and Fall Time
CL =50 pF
ns
GIN
Maximum Input Capacitance
pF
COUT
Maximum Output Capacitance
pF
Gpo
Power Dissipation Capacitance (Note 5)
OC=Vcc
OC=GND
Note 5: Cpo determines the no load power consumption, PO=Cpo Vcr!- f+lee Vee, and the no load dynamic current consumption, IS=CPD Vee f+ ICC.
4-96
pF
pF
~National
PRELIMINARY
~ Semiconductor
t: ":1
micro CMOS
MM54HCT573/MM74HCT573
TRI-STATE® Octal D-Type Latch
General Description
These high speed octal Ootype latches utilize microCMOS
Technology, 3.0 micron silicon gate N-well CMQS. They
possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the
ability to drive 15 LS-TIL loads. Oue to the large output
drive capability and the TRI-STATE feature, these devices
are ideally suited for interfacing with bus lines in a bus 'organized system.
.
When the LATCH ENABLE(LE) input is high, the outputs
will follow the 0 inputs. When the LATCH ENABLE goes
low, data at the 0 inputs will be retained at the outputs until
LATCH ENABLE returns high again. When a high logic level
is applied to the OUTPUT CONTROL (OC) input, all outputs
go to a high impedance state, regardless of what signals are
present at the other inputs and the state of the storage
elements.
MM54HCTIMM74HCT devices are intended to interface between TIL and NMOS components and standard CMOS
a
devices. These parts are also plug in replacements for LSTIL devices and can be used to reduce power consumption
in existing designs.
All inputs are protected from damage due to static discharge by diodes to Vee and ground.
Features
•
•
•
•
•
TIL input characteristic compatible
Low input current: 1 /LA maximum
Low quiescent current: 80 p.A maximum
Compatible with bus-oriented systems
Output drive capability: 15 LS-TIL loads
)
Connection Diagram
Dual-In-Llne Package
Vee
1Q
OUTPUT 10
CONTROL
2Q
3Q
4Q
5Q '
6Q
7Q
LATCH
8Q ENA8LE
20
3D
40
50
60
70
80
UNO
Top View
Order Number MM54HCT573J or MM74HCT573J, N
See NS Package J20A or N20A
Truth Table
Output
Control
Latch
Enable
L
L
L
H
H
H
L
Data
Output
H
L
H
L
X
X
00
Z
X
H = high level, L = low level
00 = level of output before steady-state input
conditions were established.
Z =' high impedance
X = Don't care
4-97
TLlF/6126-1
Absolute Maximum Ratings (Notes 1 & 2)
-0.5 to + 7.0V
Supply Voltage (Veel
DC Input Voltage (VIN)
-1.5toVee+ 1.5V
-0.5 to Vee+0.5V
DC Output Voltage (VOUT)
±20mA
Clamp Diode Current (11K, loKI
±35mA
DC Output Current, per pin (lOUT)
±70 inA
DC Vee or GND Current, per pin (Ieel
- 65°C to + 150·C
Storage Temperature Range (TSTG)
500mW
Power Dissipation (PD) (Note 3)
260·C
Lead Temp. (T Ll (Soldering 10 seconds)
Operating Conditions
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TA)
MM74HCT
MM54HCT
Input Rise or Fall Times
(tr, ttl
Min
4.5
0
Max
5.5
Vee
Units
V
V
-40
-55
+B5
+125
·C·
·C
500
ns
DC Electrical Characteristics
Vee=5V ± 10% (unless otherwise specified)
Symbol
Parameter
Conditions'
TA=25°C
Typ
74HCT
TA= -40 to 85·C
54HCT
TA= -55 to 125·C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0
2.0
2.0
V
VIL
Maximum Low Level
Input Voltage
O.B
O.B
O.B
V
VOH
Minimum High Level
Output Voltage
VIN=VIHorVIL
IIOUTI = 20 /LA
IIOUTI=6.0mA, Vec=4.5V
IIOUTI =7.2 mA, Vee=5.5V
Vee
4.2
5.2
Vee- O,1
3.9B
4.9B
Vee- 0.1
3.B4
4.B4
Vee- 0.1
3.7
4.7
V
V
V
Maximum Low Level
Voltage
VIN=VIHorVIL
IIOUTI=20/LA
IiOUTI =6.0 mA, Vee=4.5V
IIOUTI=7.2 mA, Vee=5.5V
0
0.2
0.2
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
!IN
Maximum Input
Current
ViN=VcccrGND,
VIJ,I orVIL
±O.1
...
DC Output Current, per pin (lOUT)
DC Vee or GND Current, per pin (lee)
Storage Temperature Range (TSTG)
Power Dissipation (Po) (Note 3)
Lead Temperature (TO
(Soldering 10 seconds)
Parameter
Supply Voltage (Vee>
DC Input or Output Voltage
(VIN' VOUT)
Operating Temp. Range (TA)
MM74HCT
MM54HCT
Input Rise or Fall Times
(tr, ttl
Min
4.5
0
Max
5.5
Vee
Units
V
V
-40
-55
+85
+125
'C
'C
500
ns
,
260'C
DC Electrical Characteristics Vee=5V
Symbol
Operating Conditions
-0.5 to + 7.0V
-1.5toVee+ 1.5V
-0.5 to Vee+0.5V
±20mA
±35mA
±70mA
-65'Cto + 150'C
500mW
±10% (unless otherwise speCified)
Conditions
TA=25'C
Typ
74HCT
TA=-40t085'C
54HCT
TA= -55 to 125'C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0
2.0
2.0
V
VIL
Maximum Low Level
Input Voltage
0.8
. 0.8
0.8
V
VOH
Minimum High Level
Output Voltage
VIN=VIH orVIL
itouTI=20~
IIOUTI=6.0 mA, Vee=4.5V
IIOUTI =7.2 mA, Vee=5.5V
Vee
4.2
5.2
Vee- 0.1
3.98
4.98
Vee- O.1
3.84
4.84
Vee- 0.1
3.7
4.7
V
V
V
Maximum Low Level
Voltage
VIN=VIH orVIL
IIOUTI=20 /LA
IIOUTI=6.0 mA, Vee=4.5V
IlOUT I =7.2 mA, Vee=5.5V
0
0.2
0.2
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
liN
Maximum Input
Current
VIN=Vee or GND,
VIHorVIL
±0.1
±1.0
±1.0
/LA
loz
Maximum TRI·STATE
Output Leakage
Current
VOUT= Vee or GND
OC=VIH
±0.5
±5.0
±10
/LA
lee
Maximum Quiescent
Supply Current
VIN=VeeorGND
IOUT=O/LA
8.0
80
160
/LA
VOL
Note 1:
Note 2:
Note 3:
Note 4:
VIN=2.4Vor 0.5V (Note 4)
mA
Absolute Maximum Ratings are those values beyond which damage to the device may occur.
I
Unless olherwise specified all voltages are referenced to ground.
Power Dissipation temperature derating - plastic "N" package: -12 mWf-C from 65"C to 8SoC; ceramic "J" package: -12 mWf'C from IOO"C to 12SoC.
Measured per pin. All others tied to Vee or ground.
"
4·101
AC Electrical Characteristics Vcc=5V. TA=25°C. t r =tf=6ns
Symbol
Maximum Operating Frequency .
'MAX
tpHL. tpLH
Conditions
Parameter
. Maximum Propagation Delay. Clock to Q
Typ
Guaranteed
Limit
Units
50
MHz
CL =45 pF
12
ns
tpZH. tPZL
Maximum Output Enable Time
RL =1 k!l
CL =45pF
13
ns
tpHZ. tpLZ
Maxlmum Output Disable Time
RL =1 k!l
CL =5pF
11
ns
is
Minimum Setup Time
ns
tH
Minimum Hold Time
ns
tw
Minimum Pulse Width
ns
AC Electrical Characteristics Vee = 5V ± 10%. CL = 50 pF. tr=tf= 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
74HCT
TA=-40to85°C
TA=25"C
Typ
'MAX
tpHL. tpLH
Maximum Operating Frequency
tpZH. tpZL
Maximum Output Enable Time
tpHZ. tpLZ
Maximum Propagation
Delay. Clock to Q
Maximum Output Disable Time
I
54HCT
TA= -55 to 125°C
Units
Guaranteed Limits
MHz
CL =50pF
CL =150 pF
13
19
ns
ns
CL =50pF
CL =150pF
14
20
ns
ns
RL =1 k!l
GL =50 pF
12
ns
RL =1 k!l
ts
Minimum Setup Time
Data to Clock
ns
lH
Minimum Hold Time
Clock to Data
ns
trHL. trLH
Maximum Output Rise
and Fall Time
tw
Minimum Clock Pulse Width
tr.tf
Maximum Clock Input Rise
and Fall Time
CPO
Power Dissipation CapaCitance
(Note 5)
CIN
Maximum Input Capacitance
CL =50pF
7
ns
9
ns
.
9C=Vee
OC=GND
ns
30
50
pF
pF
5
pF
Maximum Output CapaCitance
pF
15
Nota 5: CpO determines the no load dynamic power consumption, Po= CPO Vcc2 f+ lee Vee. and the no load dynamic current consumption. Is = CPO Vee f+ lee.
COUT
,
4·102
,
~National
~ Semiconductor
MM54HCT590/MM74HCT590
a-Bit Binary Counter with TRI-STATE® Output Register
General Description
These counters are implemented using an advanced 3.0
micron silicon gate N-well microCMOS process to acheive
high performance. These devices retain the low power of
CMOS logic, while offering the high speed operation and
large output drive typically associated with bipolar circuits.
This device is input compatible with 54LS174LS and other
TIL output compatible circuits, and may be used as a lower
power direct replacement for the LS equivalent device.
The MM54HCT590/MM74HCT590 contain an B-bit binary
counter which feeds an B-bit register. The counter is incremented on the rising edge of the CCK input, provided that
clock enable, CCKEN, is low. When the counter increments
to the all ones condition ripple carry out, RCO, will go low.
This enables either synchronous cascading of the counters
by connecting the RCO of the first stage to the CCKEN of
the second, or clocking both circuits in parallel. Ripple cascading is accomplished by connecting the RCO of the first
to the CCK of the second stage. A clear input is also provided which will reset the counter to the all zeros state.
The output register is loaded with the contents of the counter on the rising edge of the register clock, RCK. The outputs
of this register feed TRI-STATE outputs which are enabled
when the enable input, G, is taken low. This enables connection of this part of a system bus.
The MM54HCT590/MM74HCT590 are functional, speed
and pin equivalent to the equivalent LS-TIL circuit, and may
be used as a direct replacement for the equivalent LS-TIL
IC. Its inputs are protected from damage due to electrostatic
discharge by diodes from Vee to ground.
Features
• Wide power supply range: 4.5V to 5.5V
• Guaranteed TIL compatible input logiC levels: 2.0V and
O.BV
• High output current drive: 6.0 mA min
• Low quiescent power consumption: 80 /LA (74HCT)
Connection Diagram
•
Dual-In-Llne Package
QB- 1
U
16~VCC
Qc- 2
15 r-IIA
Qo- 3
14r- G
QE- 4
13
~RCK
QF- 5
12
~CCKEN
Qa- 6
11 r-CCK
QH- 7
10 -CClR
GND- 8
9-liCO
TOP VIEW
TLlF/576B-l
Order Number MM54HCT590J or MM74HCT590J, N
See NS Package J16A or N16E
4-103
(:)
G)
&n
I-
Logic Diagram
0
.......
:c
:E
:E
.....
'1 14
RCK 13
0
G)
12
0
...
:c
RiIlII
12
1m!
&n
:E
::E
CCK 11
IS 0.
~-+
______________-__~7~
TLlF/5768-2
4-104
PRELIMINARY
~National
~ Semiconductor
microCMOS
MM54HCT592/MM74HCT592
a-Bit Binary Counter with Input Register
MM54HCT593/MM74HCT593 a-Bit Counter
with Bidirectional Input Register/Counter Outputs
General Description
These counters are implemented using an advanced 3.0
micron silicon gate N-well microCMOS process to achieve
high peformance. These devices retain the low power of
CMOS logic, while offering the high speed operation and
large output drive typically associated with bipolar circuits.
This device is input compatible with 54LS174LS and other
TTL output compatible circuits, and may be used as a lower
power direct replacement for the LS equivalent device.
The MM54HCT592!MM74HCT592 and the MM54HCT593!
MM74HCT593 contain an S-bit register which feeds an S-bit
binary counter. The counter is incremented on the rising
edge of the CCK input, provided that clock enable, CCKEN,
is low. When the counter increments to the all ones condition, ripple carry out, RCO, will go low. This enables either
synchronous cescading of the counters by connecting the
RCO of the first stage to the CCKEN of the second, or
clocking both circuits In parallel. Ripple cascading is accomplished by connecting the ROO of the first to the CCK of the
second stage. A clear input is also provided which will reset
'
the counter to the all zeros state.
The input register is loaded on the rising edge of the register
clock, RCK. The outputs of this register feed the counter.
The counter is loaded with the register's contents when the
clock load, CLOAD, input is taken low.
The 'HCT592 differs from the 'HCT593 in that the latter device has bidirectional input/output pins. The TRI-STATE@
outputs of the counter can be enabled and are active when
enable input, G, is taken low and input G is taken high. The
outputs of the counter then appear on the register inputs.
This enables connection of this part to a system bus. The
'HCT593 also has a second clock enable pin, CCKEN,
which is active high and it also has an active low register
clock enable, RCKEN.
The MM54HCT592!MM74HCT592 and the MM54HCT593!
MM74HCT593 are functional, speed and pin equivalent to
the equivalent LS-TTL circuit and may be used as a direct
replacement for the equivalent LS-TTL IC. Their inputs are
protected from damage due to electrostatic discharge by
diodes from Vee to ground.
Features
• Wide power supply range: 4.5V to 5.5V
• Guaranteed TTL compatible input logic levels: 2.0V and
O.SV
• High output current drive: 6.0 mA min
• Low quiescent power consumption: SO p.A (74HCT)
Connection Diagrams
Dual-In-Llne Package
GND
16
Vee
15
A
Dual-In-Llne Package
AIDA
20
BIUB
19
Clae
18
ii
DIaD
17
RCKEN
Ellie
16
RCK
Vee
14
ClOAD
13
,RCK
12
CCKEN
11
CCK
10
CClR
F/IJF
15
CCKEN
RCO
GIGo
14
CCKEN
HlaH
13
CCK
CLDAD
12
ffiii
11
iiCii
TDPVIEW
Tl/F/5769-1
MM54HCT592/MM74HCT592
Order Number MM54HCT592J, MM54HCT593J,
MM74HCT592J, N or MM74HCT593J, N
See NS Package J16A, J20A, N16E or N20A
GND
10
TOP VIEW
Tl/F/5769-2
MM54HCT593/MM74HCT593
4-105
•
~ r-------------------------------------------------------------------~-----,
m
ti:I:
..,......
:::iE
:::iE
~
en
It)
ti
:I:
..,.
It)
:::iE
:::iE
......
,<'I
Logic Diagrams
HCT592
CCLR (10)
~I~
-
I--
(11)~
(14)
(13)
en
,
.....
.----
-"-
V
,....-
I
It)
ti:I:
..,.
.....
(15)
10
~ I> Cl
~
;;;
en
It)
...--
r---
0
(1)
~
(.)
..,.
~R
M
10
~
f---<;
It)
(2)
r--10
........c ~Cl
io..-
(3)
~~Cl
io..-
(4)
10
i...-
~ I> Cl
io..-
0,
>T
L
R
a
-o
~
--- ~~
10
L
a
-o
L
>1
R
-
a
-
a
-
o
L
a
...-o
L
I>T
R
a
~
~
...--
...--
10
~ I> Cl
io..-
~
....
f-
~M
o
L
1>1
R
a
~
M
1
1
1
1
t::t
R"
Lr-
>T
R
-
f'
>T
R
0
~ ~Cl
(7)
-
L...C >T
r---c R
...-10
(6)
~~
~
~ I> Cl
(5)
~~
r--10
a
~
r--~ I> Cl
:I:
:::iE
:::iE
Lr-
L......c ~T
:::iE
:::iE
(9)
~f- f-.I
FI
I-
;::r
.....
L-I::
f-
'"--TL/F/5769-3
4-106
Logic Diagrams (Continued)
HCT593
G (19)
ii
CClR
CCKEN
CCKEN
CCK
ClOAO
RCKEN
RCK"
AlO.
(18)
(12)
~Ii
(14)
(13)
J-.....
.r-...
(9)
(17)
(16)
(1)
-LG2 In
2
-
J
-
I
I-
(2)
r---
lD
~ t> Cl
BlOB
(11)
GATING FOR RCK
IS SIMILAR IN DETAil
TO THAT SHOWN FOR
CCK
D
l
L......c I> T
---c
l~
R
I-
0
L....-
r---
L.(D
ll-
I>T
~ ~Cl
L....-
CIOe
(3) .
(4)
L....-
(5)
JlD
~ I> Cl
I-
FIDF
(6)
l~
I> Cl
f-o I
-
GIOG
(7)
r--D
lro;;-
~R
HIDH
(8)
I> Cl
L..-
Jro;;l-..(
>Cl
L....-
I-
0
""-
r--D
l
L.....c t> T
---c
~~
R
0
-
l
D
>T
R
1:.:;; -
I-
0
D
>T
l
-
Q
~R
J-
r---'
~ D LJ-
,
~
l
L.....c t> T
f~
~I>Cl
0
""-
l~
I> Cl
~ L....-
DIOD
~R
~T
~R
Q
L....-
1:.:;;~J-
~R
0
""-
4-107
~
*
'*
'*
'~*
*
*
,~
r-
M
M
M
t-I:::t
~
~
Ff
1
1
~1
t:
1
TLfF15769-4
•
~National
~ Semiconductor
MM54HCT640/MM74HCT640
Inverting Octal TAI-STATE® Transceiver
MM54HCT643/MM74HCT643
True-Inverting Octal TAl-STATE Transceiver
General Description
TheSe TRI-STATE bi-directional transceivers utilize
microCMOS Technology, 3.0 micron silicon gate N-well
CMOS, and are intended for two-way asynchronous communication between data buses. They have high drive current outputs which enable high speed operation even when
driving large bus capacitances. These circuits possess the
low power consumption of CMOS circuitry, yet have speeds
comparable to low power Schottky TTL circuits.
MM74HCT640 transfers inverted data from one bus to the
other. The MM54HCT643/MM74HCT643 transfers inverted
Qata from the A bus to the B bus and non-inverted data from
the B bus to the A bus.
MM54HCTIMM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS
devices. These parts are also plug-in replacements for LSTTL devices and can be used to reduce power consumption
in existing designs.
All devices are TTL input compatible and can drive up to 15
LS-TTL loads, and all inputs are protected from damage due
to static discharge by diodes to Vee and ground.
Both the MM54HCT640/MM74HCT640 and the
MM54HCT6431 MM74HCT643 have one active low enable
input (G), and a direction control (DIR). When the DIR input
is high, data flows from the A inputs to the B outputs. When
DIR is low, data flows from B to A. The MM54HCT6401
Features
• TTL input compatible
• Octal TRI-STATE outputs for ,...p bus applications:
6 mA, typical
• High speed: 16 ns typical propagation delay
• Low power: 80 p.A maximum (74HCT)
Connection Diagram
Dual·ln·Una Packages
ENABLE
Vee
DlR
iI
"1
ENABLE
I'
A2
82
A3
83
A4
..
A5
85
86
A6
A7
17
A8
88
Vee
ii
GNO
DIR
A'
8'
A2
Tl/F/5370-1
82
A3
B3
A4
..
AS
BS
88
All
A7
B7
All
88
GND
TVF/5370-2
Top View
Order Number MM54HCT64OJ or MM74HCT640J, N
Sea NS Package J20A or N20A
Top VI_
Order Number MM54HCT643J or MM74HCT643J, N
see NS Package J20A or N20A
Truth Table
Control
Inputs'
Operation
G
DIR
640
643
L
L
B data to A bus
B data to A bus
L
H
A data to B bus
A data to B bl,ls
H
X
Isolation
Isolation
H=high lavel, L=low lavel, X=Irrelevant
4-108
Absolute Maximum Ratings (Notes 1 &2)
Supply Voltage (Vcel
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (11K. 10K)
DC Output Current. per pin (lOUT)
DC Vee or GND Current. per pin (lee)
Storage Temperature Range (T8TG)
Power Dissipation (Po) (Note 3)
Lead Temperature (Til
(Soldering 10 seconds)
Operating Conditions
-0.5to +7.0V
-1.5toVcc+ 1.5V
-0.5toVcc+ 0.5V
±20mA
±35mA
±70mA
- 65"C to + 150"C
500mW
Supply Voltage (Vee)
DC Input or Output Voltage
(VIN. VOUT)
Operating Temp. Range (TAl
MM74HCT
MM54HCT
Input Rise or Fall Times
(Ir. tf)
Min
4.5
0
Max
5.5
Vee
Units
V
V
~40
+85
+125
"C
"C
500
ns
-55
260"C
DC Electrical Characteristics Vee = 5V ± 10% (unless otherwise specified)
Parameter
Symbol
TA=25"C
Conditions
Typ
74HCT
TA=-40t085"C
54HCT
TA= -55 to 125"C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0
2.0
2.0
V
VIL
Maximum Low Level
Input Voltage
0.8
0.8
0.8
V
VOH
Minimum High Level
Output Voltage
VIN = VIH or VIL
IIOUTI=20 p.A
IIOUTI=6.0mA. Vee=4.5V
IIOUTI= 7.2mA. Vee=5.5V
Vcc
4.2
5.2
Vcc-0.1
3.98
4.98
Vcc·0.1
3.84
4.84
Vee·0.1
3.7
4.7
V
V
V
Maximum Low Level
Voltage
VIN = VIH or VIL
IIOUTI=20p.A
IIOUTI=6.0mA. Vcc=4.5V
IIOUTI=7.2mA. Vee=5.5V
0
0.2
0.2
0.1
0.26
0.26.
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
liN
Maximum Input
Current
VIN = Vee or GND.
VIHorVIL
±0.1
±1.0
±1.0
p.A
loz
Maximum TRI·STATE
Output Leakage
Current
VOUT= VCC or GND
Enable G = VIH
±0.5
±5.0
±10
p.A
Icc
Maximum Quiescent
Supply Current
VIN=VeeorGND
10UT=0p.A
8
80
160
p.A
VOL
Not. 1:
Note 2:
Note 3:
Not. 4:
1.5
VIN=2.4Vor 0.5V
0.6
1.0
1.3
p.A
(Note 4)
Absolute Maximum Ratings are thoSe values beyond which damage to the device may occur.
Unless otherwise specified all Yoltages are referenced to ground.
Power Dissipation temperature derating - plastic "N" package: -12 mWrC from 65'C to 65'C; ceramic "J" package: -12 mW/'C from 1OO'C to 125'C.
Measured pe; input. All other Inputs held at Vee or ground.
AC Electrical Characteristics MM54HCT640/MM74HCT640
Vee = 5.0V. Ir= tf = 6 ns. TA= 25"C (unless otherwise specified)
Symbol
Parameter
Conditions
Typ
Guaranteed
Limits
Units
tpHL. tpLH
Maximum Output
Propagat!on Delay
CL =45 pF
16
20
ns
tPZL. tPZH
Maximum Output
Enable Time
CL =45 pF
RL=1 kG
29
40
ns
tpLZ. tpHZ
Maximum Output
Disable Time
CL=5pF
RL =1 kG
20
25
ns
4·109
•
AC Electrical Characteristics MM54HCT640/MM74HCT640
Vcc=5.0V ± 10%. t,.=t,=6 ns (unless otherwise specified)
Symbol
Parameter
TA=25"C
Conditions
Typ
tpHL. tpLH
Maximum Output
Propagation Delay
74HCT
TA= -40to85"C
54HCT
TA=-55to125"C
Units
Guaranteed Limits
CL =50pF
17
23
29
34
ns
Cl =150pF
24
30
38
45
ns
31
42
53
63
ns
35
49
62
74
ns
I Cl=50pF
I Cl=150pF
Maximum Output
Enable TIme
Rl =1kO
tpHZ.tpLZ
Maximum Output
Disable TIme
Rl =1kO
Cl =50pF
21
30
38
45
ns
trHl. trlH
Maximum Output
Rise and Fall Time
Cl =50pF
8
12
15
18
ns
CIN
Maximum Input
Capacitance
10
15
15
15 ,
pF
GoUT
Maximum Outputl
Input CapaC;itance
20
25.
25
25
pF
CPO
Power Dissipation
Capacitance (Note 5)
tPZH. tpzL
.
(per output)
'7
100
G=Vcc
G=GND
pF
pF
AC Electrical Characteristics Mtv154HCT643/MM74HCT643
Vcc=5.0V. t r =t,=6 ns. TA=25°C (unless otherwise specified)
Symbol
Parameter
Conditions
Typ
Guaranteed
Limits
Units
tpHl. tplH
Maximum Output
Propagation Delay
Cl =45pF
16
20
ns
tPZl. tPZH
Maximum Output
EnabieTlme
Cl =45 pF
Rl=1 kO
29
40
ns
tpLZ. tPHZ
Maximum Output
Disable TIme
Cl =5pF
Rl =1 kO
20
25
ns
AC Electrical Characteristics MM54HCT643/MM74HCT643
Vcc=5.0V
Symbol
I'
± 10%. t,.=t,=6 ns (unless otherwise specified)
Parameter
TA=2So C
Conditions
Typ
74HCT
TA= -40to8S~C
54HCT
TA=-55to125"C
Units
Guaranteed Limits
Maximum Output •
Propagation Delay
Cl=50pF
17
23
29
34
ns
Cl =150pF
24
30
38
45
ns
Maximum Output
Enable TIme
Rl =1 kO
31'
·42
53
63
ns
35
49
62
74
ns
tpHZ. tpLZ
Maximum Output
Disable TIme
Rl =1 kO
Cl =50pF
21
30
38
45
ns
ns
trHl. trLH
Maximum Output
Rise and Fall TIme
Cl =50pF
8
12
15
18
ns
CIN
Maximum Input
Capacitance
10
15
15
15
pF
COUT
Maximum Output!
Input CapaCitance
20
25
25
25
pF.
tpHlo tpLH
tpZH. tpZl
7
100
Note 5: Cpo determines the no load power consumption. Po=CpoVcc;21 +ICCVCC. The no load dynamic current consumption. Is=CpoVcc +Icc.
CpO
Power Dissipation
CapaCitance (Note 5)
(per output)
I Cl=50pF
I Cl=150pF
-
§=Vcc
G=GND
4-110
pF
pF
~National
~ Semiconductor
MM54HCT688/MM74HCT688
8-Bit Magnitude Comparator (Equality Detector)
General Description
This equality detector utilizes microCMOS Technology. 3.0
micron silicon gate N-well CMOS to compare bit for bit two
B-bit words and indicate whether or not they are equal. The
P = Q output indicates equality when it is low. A single active
low enable is provided to facilitate cascading of several
packages and enable comparison of words greater than 8
bits.
This device is useful in memory block decoding applications. where memory block enable signals must be generated from computer address information.
The comparator combines the low power consumption of
CMOS. but inputs are compatible with TTL logic levels. alld
the output can drive 10 low power Schottky equivalent
loads.
MM54HCTIMM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS
devices. These parts are also plug in replacements for LSTTL devices and can be used to reduce power consumption
in' existing designs.
All inputs are protected from damage due to static discharge by diodes to Vee and ground.
Features
•
•
•
•
•
TTL input compatible
Typical propagation delay: 20 ns
Low quiescent current: 80 p.A maximum (74HCT Series)
Large output current: 4 mA
Same as HCT521
Connection and Logic Diagrams
Dual-In-Llne Package
vee P
=0
07
P7
06
P6
05
P5
04
P4
07
ii
PO
00
PI
01
P2
02
P3
Jo-IDo-L)oo",-10.;.) -P=-0
GND
TL/F/5371-1
Top View
Order Number MM54HCT688J or MM74HCT688J, N
See NS Package J20A or N20A
Truth Table
Inputs
Data
Enable
P,Q
G
P=Q
P>Q
P
(')
8........
ns
ns
aJ
s:
ns
o
pF
8........
pF
aJ
o
Typical Performance Characteristics
20
~
w
"
,.'"'"~
l; 10
~
1
vOO' 5t
5
0
'"
,.~'"
OD
~-
" \I~-r(.
~
2" -
II
0
~
J
J
1
,.'"
r
L
V,
~
5
10
15
V, -INPUT VOLTAGE (VI
BOTH INPUTS
~. 15
~.,
,.
~
10
voo'15l
VOO = 10l
J,
v.
l;
'"
,.'"
1
10
"m
Vor5V
I
~
~
"'..,
g:.5
0
5
10
z
~
~
~~w
I
~i=
I'~
3'" 100
~
0
0
20
400
C04011B
TA =25 C
CL' 50pF
300
~
,,:0;
~
.9-
15
TL/F/5939-7
'"
Cl=50pF
300
-
"I
FIGURE 3. Typical Transfer
Characteristics
TA =25'C
IW
5
10
15
VOO - SUPPLY VOLTAGE (VI
TLIFI5939-a
FIGURE 4. Typical Tranofe,
Characteristics
2"
ONE INPUT DNL Y
CD40018
'"
~~
.... 200
20
":"vssTi
VI -INPUT VOLTAGE (Vj
400
z
.9-
10
5
15
V, -INPUT VOLTAGE (VI
BOTH INPUTS
0
FIGURE 2. Typical Transfer
Characteristics
u
I,
~,: Va
v,
Voo' 5V
5
20
"'>"'''
....
Vo
vss~;
5
0
~
~:
'00
TlIFI593!J.6
,
20
~
I
voo'lol
10
~
r
1
0
TI../F/S939·5
C04001B
Tr 25' C
....
TA" 25 C
voo'15l
15
"....
"'"1
,.'"
; va
"
20
FIGURE 1. Typical Transfer
Characteristics
'"
,.~
vs;~f
voo =5l
5
~
1
vOO'lL
10
CD40D18
TA=25'C
voo'llv
15
0
5
10
15
V, -INPUT VOLTAGE (VI
ONE INPUT ONL V
20
CD4D118
CD4011B
TA'25'C
Voo '10V
~
'"
,.'"
20
J
Voo '15V
20
~S
Iw
200
~ ;PHl'
3'" 100
tPI~~
.9-
;
0
0
5-15
20
TLlF15939·10
TLIF/5939-9
FIGURE 5
-
10
15
5
VOO -SUPPLY VOLTAGE (VI
FIGURE 6
•
(.)
........
III
~
c
CJ
:e
III
....
....
~
(.)
cS
'Typical Performance Characteristics (Cont'd.)
200
~
C040018
TA = 25"C
>'"
~..s
~!
~I-
150
6>
~~
!:e>
:~
~~
><
I-
~
'VOO -15V
50
,e>
"1
~g:
0
III
....
o
0
~
....
III
ic
CJ
"'~
"
,",
25
voJ~
~S
~~ 100
~z
~~
Ie>
",0:
~~
VOO -15V
J
0
100
15
VOO =10V
-
50
~
50
~.
~e>
--
50
",0:
~~
~
0
0
~
VOOI-l0~ ~
50
1.5
'"
:<
::l
~'"
~
e>
C04001B
'\
C04011B
(See Application Note AN·9O
Propagation Delay)
1.0
~
z
;;;
~
~
'W
::l
L
30
VOO -15V
18
~
10
I
6
I~
!?
2
0
130
~
110
2
4
B
::l
10
>
50
I
30
10
0
'"
I-
:'"
8 10 12 14 16 18 20
./
./
90
I-
rr
""
-:::::::- i-"'"
0
25
..s
~
~
g
~
0:
_ _ VOO-l0V
~
0 2
::l
I
V
~~
_VOO=5J-
4
'"
H~04001B
CD4011B'
>
I-
,../
~
50
0
V
I
,.,.
28
'"
VCC-15V'
20 18 16 14 12 10
VOUTIV)
~rt'J
o
c- C- VCC -10V
22
36
8 10 12 14 16 18 20
VCc'- 5V-"
24
32
8
6
4
2
0
VCC - VOUT IV)
TLlFI5939-'8
TL/F/5939·17
FIGURE 13
FIGURE 14
~
)
,
.
5·16
15
100
CL - LOAD CAPACITANCE I,F)
10
14
18
.,.......
.....TlIF/5939-16
2
6
I
!?
6
V
FIGURE ·12,
u
II
./
. / .........:
E-
VOO - POWER SUPPLY IV)
C0400iB
C04011B
I
150
~
0
0
100
15
TLIF/5939·15
38
14
170
FIGURE 11
34
26
22
190
!i;::l!
1!i
~
c--
0.5
I
e>
100
]
E
TlIFI5939-14
i'"
50
25
TLlFI5939-13
tr"1f"20ns
TA -25'C
FIGURE 10
..
=15V
VOO
FIGURE 9
0:
15
-
~
CL - LOAD CAPACITANCE I,F)
U
CL - LOAD CAPACITANCE I,F)
.sI-
-
0
l-
VOO ~ 15V
25
50
0
~
100
.,.. ~
~j:::
~~
.!of
V
VOD =5V
1-<
2.0
~
.s
150
5i=
~~
Ie>
100
TUF/5939·t2
C04011B
TA-25'C
6:;:
~~
e>c
~g
~~
"'>
"'<
FIGURE 8
200
~]
6!
1-1-
150
100
15
50
TUFI5939-11
FIGURE 7
~
~
C04011B
TA -25'C
3:]'
e>-
CL - LOAD CAPACITANCE I.F)
CL - LOAD CAPACITANCE I,F)
C
CJ
:!E
-- --=
C0400iB
TA -25'C
~]
Vo,!:~
'-
100
200
200
~
~
,
(')
c
~National
a
s:
~ Semiconductor
o
~
CD4002M/CD4002C Dual 4·lnput NOR Gate
CD4012M/CD4012C Dual 4·lnput NAN D Gate
o
N
s>
General Description
Features
These NOR and NAND gates are monolithic complemen·
tary MOS (CMOS) integrated circuits. The N· and
P·channel enhancement mode transistors provide a
symmetrical circuit with output swings essentially equal
to the supply voltage. This results in high noise immunity
over a wide supply voltage range. No DC power other
than that caused by leakage current is consumed during
static conditions. All inputs are protected against static
discharge and latching conditions.
• Wide supply voltage range
Connection Diagrams
• Low power
• High noise immunity
Automotive
Data terminals'
Instrumentation
Medical Electronics
•
•
•
•
s:
0.45 Voo (typ.)
~....
N
CD4012
TOP VIEW
Tt.IF/594C).2
TUF/5940-1
Order Number CD4002MJ, CD4002CJ,
CD4012MJ or CD4012CJ
See NS Package J14A
Order Number CD4002MN, CD4002CN,
CD4012MN or CD4012CN
See NS Package N14A
5·17
o
o
Alarm system
Industrial controls
Remote metering
Computers
Dual·ln·Line Packages
CD4002
N
3.0Vto15V
10nW(typ.)
Applications
•
•
•
•
o
c
8
....
Absolute Maximum Ratings
(Note 1)
Voltage an Any Pin
Vss - 0.3V to Vee + 0.3V
Operating Temperature Range
-55·C to +125·C
CD4002M, CD4012M
CD4002C, CD4012C
-40·C to +85·C
DC Electrical CharacteristiC's
-
-65·C to +150·C
Storage Temperature Range
Package Dissipation
500mW
Operating Vee Range
Vss +3.0V to Vss+ 15V
Lead Temperature (Soldering, 10 seconds)
260·C
CD4002M, CD4012M
Limits
Sym
Parameter
2SoC
-SS"C
Conditions
Min
Max
Min
12S"C
Typ
Max
Min
Units
Max
IL
Quiescent Device
Current
Vee =5.0V
Vee=10V
0.05
0.1
0.001
0.001
0.05
0.1
3.0
6.0
"A
"A
Pe
Quiescent Device
Vee = 5.0V
Dissipation/Package Vee=10V
0.25
1.0
0.005
0.01
0.25
1.0
15
60
"W
"W'
VOL Output Voltage !,.ow
Level
0.05
0.05
Vee = 5.0V, VI = Vee, 10 = OA
Vee = 10V, VI = Vee, 10 = OA
VOH Output Voltage High Vee = 5.0V, VI = Vss, 10 = OA
Level
Vee = 10V, VI = Vss, 10 = OA
4.95
9.95
4.95
9.95
0
0.05
0
0.05
5.0 .
0.05
0.05
V
V
10
4.95
9.95
V
V
VNL Noise Immunity
(All Inputs)
Vee = 5.0V, Vo = 3.6V, 10 = OA
Vee = 10V, Vo = 7.2V, 10 = OA
1.5
3.0
1.5
3.0
2.25
4.5
1.4
2.9
V
V
VNH Noise Immunity
(All Inputs)
Vee = 5.0V, Vo = 0.95V, 10 = OA
Vee = 10V, Vo = 2.9V, 10 = OA
1.4
2.9
1.5
3.0
2.25
4.5
1.5
3.0
V
V
leN Output Drive Current Vee = 5.0V, Vo = 0.4V, VI = Vee
N·Channel (4002)
Vee = 10V, Vo = 0.5V, VI = Vee
(Note 2)
0.5
1.1
0.40
0.9
1.0
2.5
0.28
0.65
mA
mA
ieP Output Drive Current Vee = 5.0V, Vo = 2.5V, VI = Vss
P·Channel (4002)
Vee = 10V, Vo = 9.5V, VI = Vss
(Note 2)
-0.62
-0.62
-0.5
-2.0
-0.5
-1.0
-0.35
-0.35
mAo
. mA
leN Output Drive Current Vee = 5.0V,Vo = 0.4V, VI = Vee
N·Channel (4012)
Vee = 10V, Vo = 0.5V, VI = Vee'
(Note 2)
0.31
0.63
0.25
. 0.5
0.5
0.6
0.175
0.35
mA
mA
leP Output Drive Current Vee = 5.0V, Vo = 2.5V, VI = Vss
P·Channel (4012)
Vee = 10V, Vo = 9.5V, VI = Vss
(Note 2)
-0.31
-0.75
-0.25
-0.6
-0.5
-1.2
-0.175
-0.4
mA
mA
II
10
Input Current
pA
,
,
'"
-'
5·18
..
DC Electrical Characteristics
-
CD4002C, CD4012C
Limits
Sym
Parameter
-400C
Conditions
Min
Max
25°C
Min
Units
85°C
Typ
Max
Min
Max
IL
Quiescent Device
Current
Voo=5.0V
Voo=10V
0.5
5.0
0.005
0.005
0.5
5.0
15
30
,.,A
,.,A
Po
Quiescent Device
Dissipation/Package
Voo=5.0V
Voo=10V
2.5
50
0.025
0.05
2.5
50
75
300
,.,W
,.,W
VOL Output Voltage Low
Level
Voo = 5.0V, VI = Voo, 10 = OA
Voo = 10V, VI = Voo, 10 = OA'
0.05
0.05
0
0
0.05
0.05
0.05
0.05
V
V
VOH Output Voltage High
Level
Voo = 5.0V, VI = Vss, 10 = OA
Voo = 10V, VI = Vss, 10 = OA
4.95
9.95
4.95
9.95
5.0
10
4.95
9.95
V
V
VNL Noise Immunity
(All Inputs)
Voo = 5.0V, Vo .. 3.5V, 10 = OA
Voo = 10V, Vo .. 7.2V, 10 = OA
1.5
3.0
1.5
3.0
2.25
4.5
1.4
2.9
V
V
VNH Noise Immunity
(All Inputs)
Voo = 5.0V, Vo " 1.5V, 10 = OA
Voo = 10V, Vo" 3.5V, 10 = OA
1.4
2.9
1.5
3.0
2.25
4.5
1.5
3.0
V
V
IoN Output Drive Current
N·Channel (4002)
(Note 2)
Voo = 5.0V, Vo = 0.4V, VI = Voo
Voo = 10V, Vo =·0.5V, VI = Voo
0.35
0.72
0.3
0.6
1.0
2.5
0.24
0.48
rnA
rnA
IoN Output Drive Current
N·Channel (4012)
(Note 2)
Voo = 5.0V, Vo = 0.4V, VI = Voo
Voo-= 10V, Vo = 0.5V, VI = Voo
0.145
0.3
0.12
0.25
0.5
0.6
0.095
0.2
rnA
rnA
loP Output Drive Current
P·Channel (4002)
(Note 2)
Voo = 5.0V, Vo = 2.5V, VI = Vss
Voo = 10V, Vo = 9.5V, VI = Vss
-0.35
-0.3
-0.3
-0.25
-2.0
-1.0
-0.24
-0.2
rnA
rnA
loP Output Drive Current
P·Channel (4012)
(Note 2)
Voo=5.0V, Vo=2.5V, VI = Vss
Voo = 10V, Vo = 9.5V, VI = Vss
-0.145
-0.35
-0.12
-0.3
-0.5
-1.2
-0.095
-0.24
rnA
rnA
II
Input Current
10
5·19
pA
~
....
i
c
o
~
....
N
ic
o
I
o
~
§c
o
AC Electrical Characteristics
TA = 25·C, CL = 15pF, and Input rise and fall times = 20ns .
Typical temperature coefficient for all values of Voo = 0.3%I·C
Parameter
Syml
CD4002M
I
Conditions
I
Min
I
Typ
I
Max
I
Units
tpHL Propagation Delay Time High to Low Level
Voo=5.0V
Voo=10V
35
25
50
40
ns
ns
Propagation Delay Time Low to High Level
Voo=5.0V
Voo=10V
35
25
50
40
ns
ns
. Voo= 5.0V
Voo=10Y
Voo= 5.0V
Voo=10V
65
35
65
35
175
75
125
70
ns
ns
ns
ns
Any Input
5.0
tpHL Propagation Delay Time High to Low Level
Voo=5.0V
Voo=10V
35
25
120
65
ns
ns
Propagation Delay Time Low to High Level
Voo=5.0V
Voo 10V
=:
35
25
80
55
ns
ns.
tTHL Transition Time High to Low Level
Voo=5.0V
Voo=10V
65
35
300
125
ns
ns
tTLH Transition Time Low to High Level
Voo=5.0V
Voo=10V
65
35
200
115
ns
ns
C1N
Any Input
5.0
tpLH
tTHL Transition Time High to Low Level
tTLH Transition Time Low to High Level
C1N
Input Capacitance
pF
CD4002C
tpLH
Input Capacitance
pF
AC Electrical Characteristics
TA =25·C, CL=15pF, and input rise and fall tlmes=20ns.
Typical temperature coefficient for all values of Voo =0.3%I·C
Parameter
syml
I
Conditions
CD4012M
I
Min
l
Typ
I
Max
I
Units
tpHL Propagation Delay Time High to Low Level
Vo o =5.0V
Voo=10V
50
25
75
40
ns
ns
Propagation Dalay Time Low to High Levei
Voo=5.0V
Voo=10V
50
75
40
ns
ns
tpLH
tTHL Transition Time High to Low Level
25
Voo =5.0V
Voo=10V
50
75
125
75
ns
ns
100
60
ns
ns
tTLH
Transition Time Low to High Level
Voo=5.0V
Voo=10V
75
40
C1N
Input Capacitance
Any Input
5.0
Voo= 5.0V
Voo=19V
50
25
100
50
ns
Voo=5.0V
Voo=10V
50
25
100
50
ns
ns
tTHL Tr\lnsition Time High to Low Level
Voo=5.0V
Voo=10V
75
50
150
100
ns
ns
tTLH
Transition Time Low to High Level
Voo= 5.0V.
Voo=10V
75
40
125
75
ns
ns
CIN
Input Capacitance.
Any Input
5.0
pF
CD4012C
tpHL Propagatic:>n Delay Time High to Low Level
tpLH
Propagation Delay Time Low to High Level
n~
pF
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits. The table of "Electrir.al
Characteristics" provides conditions for actual device operation.
Note 2: IoN and loP are tested one output at a time.
5·20
o
c
~National
~
~ Semiconductor
OJ
s:
o
CP4002BM/CD4002BC Dual 4-lnput NOR Gate
CD4012BM/CD4012BC Dual 4-lnput NAND Gate
~
~
OJ
Sl
General Description
Features
These dual gates are monolithic complementary MOS
(CMOS) integrated circuits constructed with N-and
P·channel enhancement mode transistors. They have
equal source and sink current capabilities and conform.
to standard B series output drive. The devices also have
buffered outputs which improve transfer characteristics
by providing very high gain. All inputs are protected
against static discharge with diodes to Voo and Vss.
- Wide supply voltage range
3.0V to 15V
_ High noise immunity
0.45 Voo (typ.)
_ Low power TTL
fanout of 2 driving 74L
compatibility
or 1 driving 74LS
- 5V-10V-15V parametric ratings
- Symmetrical output characteristics
- Maximum input leakage 11'A at 15Vover full temperature range
g
-110'
~
N
~
0C
-110
r-----------------------------------------------------------~------------------~~
qonnection Diagrams
N
Dual·ln·Line Packages
CD4002BM/CD4002BC
OJ
o
CD4012BM/CD4012BC
•
TLlF/5941·'
Tl/F/5941·2
Order Number CD4002BMJ, CD4002BCJ,
CD4012BMJ or CD4012BCJ
See NS Package J14A
Order Number CD4002BMN, CD4002BCN,
CD4012BMN or CD4012BCN .
See NS Package N14A
5·21
\
Absolute Maximum Ratings (Notes 1 and 2)
Recommended Operating Conditions .
(Note 2)
Voo Supply Voltage
-0.5V to +18V
VIN Input Voltage
-0.5 to Vo oO.5 V
-65"C to +150"C
Ts Storage Temperature Range
Po Package Dissipation
500mW
260°C
TL Lead Temperature (soldering, 10 seconds)
Voo Supply Voltage
VIN Input Voltage
TA Operating Temperature Range
CD4002BM, CD4012BM
CD4002BC, CD4012BC
3.0 to 15V
OVtoVooV
-55"C to +125°C
-40"C to +85"C
\
DC Electrical Characteristics
Sym Parameter
100 Quiescent
(Note 2) -
CD4002BM, CD4012BM
-ssoc
Conditions
Min
Max
25"C
Min
125"C
Typ
Max
Min
Max
Units
Voo = 5.0 V, VIN=VOOorVss
Voo = 10 V, VIN = Voo or Vss
Voo= 15 V, VIN=VOOor Vss
0.25
0.5
1.0
0.004
0.005
0,006
0.25
0.5
1.0
7.5
15
30
,..A
,..A
,..A
VOL Low Level
Output Voltage
Voo=5.0V
Voo=10V
Voo 7 15V
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
VOH High Level
Output Voltage
Voo=5.0V
Voo=10V
Voo=15V
VIL Low Level
Input Voltage
Voo=5.0V, Vo=O.5Vor 4.5V
Voo=10V, Vo=1.0Vor 9.0V
V oo =15V, Vo =1.5Vor 13.5V
VIH High Level
Input Voltage
Voo = 5.0 V, Vo=0.5Vor 4.5V
Voo=10V, Vo=1.0V or 9.0V
VDo=15V. Vo=1.5Vor 13.5V
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.50
8.25
3.5
7.0
11.0
V
V
IOL Low Level
Output Current
(Note 3)
Voo=5.0V, Vo=0.4V
Voo=10V, Vo=0.5V
Voo=15V, Vo =1.5V
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.2
8.0
0.36
0.90
2.4
mA
mA
mA
IOH High Level
Output Current
(Note 3)
Voo=5.0V, Vo=4.6V
Voo=10V, Vo=9.5V
Voo=15V, Vo=13.5V
-0.64
-1.6
-4.2
-0.51
-1.3
-3.4
-0.88
-2.2
-8.0'
-0.36
-0.90
-2.4
mA
mA
mA
Device Current
liN
Input Current
4.95
9.95
14,95
4.95
9.95
14.95
1.5
-3.0
4.0
2.25
4.50
6.75
/
,
,
5·22
4.95
9.95
14.95
1.5
3.0
4.0
-10- 5 -0.10
105
0.10
-0.10
0.10
Voo=15V, VIN=OV
Voo =15V, VIN =15V
5.0
10
15
V
V
V
1.5
3.0
4.0
V
V
V
V
-1.0
1.0
,..A
,..A
DC Electrical Characteristics
Sym Parameter
(Note 2) -
Conditions
2SOC
-40"C
Min
Max
Min
85°C
Typ
Max
Min
Max
Units
Voo = 5.0 V, VIN = Voo or Vss
Voo = 10 V, VIN = Voo or Vss
Voo = 15 V, VIN = Voo or Vss
1.0
2.0
4.0
0.004
0.005
0.006
1.0
2.0
4.0
7.5
15
30
J.lA
J.lA
J.lA
VOL Low Level
Output Voltage
Voo=5.0V
Voo=10V
Voo=15V
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
VOH High Level
Output Voltage
Voo=5.0V
Voo=10V
Voo=15V
VIL Low Level
Input Voltage
Voo=5V, Vo=0.5V or 4.5V
Voo=10V, Vo=1.0Vor 9.0V
Voo =15V, Vo=1.5Vor 13.5V
VIH High Level
Input Voltage
Voo = 5.0 V, Vo=0.5Vor 4.5V
Voo=10V, Vo=1.0V or 9.0V
Voo=15V, Vo=1.5Vor 13.5V
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
V
V
V
10L Low Level
Output Current
(Note 3)
Voo = 5.0 V, Vo=0.4V
Voo=10V, Vo=0.5V
Voo=15V, Vo=1.5V
0.52
1.3
3.6
0.44
1.1
3.0
0.88
2.2
8.0
0.36
0.90
2.4
rnA
rnA
rnA
10H High Level
Output Current
(Note 3)
Voo=5.0V, Vo=4.6V
Voo=10V, Vo=9.5V
Voo = 15V, Vo =13.5V
-0.52
-1.3
-3.6
-0.44
-1.1
-3.0
-0.88
-2.2
-8.0
-0.36
-0.90
-2.4
rnA
rnA
rnA
100
liN
Quiescent
Device Current
CD4002BC, CD4012BC
Input Current
4.95
9.95
14.95
1.5
3.0
4.0
5.0
10
15
4.95
9.95
14.95
2.25
4.50
6.75
1.5
3.0
4.0
-10 5
10-5
-0.3
0.3
Voo=15V, VIN="OV
Voo=15V, VIN=15V
.AC Electrical Characteristics
4.95
9.95
14.95
V
V
V
1.5
3.0
4.0
-0.3
0.3
-1.0
1.0
V
V
V
J.lA
J.lA
TA=25"C, CL=50pF, unless otherwise noted.
Typ
Max
Units
tpHL
Propagation Delay, High to Low Level
Voo=5.0V
Voo=10V
Voo=15V
125
60
45
250
100
70
ns
ns
ns
tpLH
Propagation Delay, Low fo High Level
Voo=5.0V
Voo=10V
Voo=15V
125
60
45
250
100
70
ns'
ns
ns
Voo=5.0V
Voo=10V
Voo=15V
100
50
40
200
100
80
ns
ns
ns
7.5
pF
Symbol
Parameter
tTHL, tTLH Transition Time
Conditions
Min
CIN
Average Input Capacitance
Any Input
5.0
Cpo
Power Dissipation Capacity (Note 4)
Any Gate
20
pF
Nole 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not
meant to Imply that the devices should be operated at these limits. The tables of "Recommended Operating Conditions" and "Electri·
cal Characteristics" provide conditions for actual device operation.
Nole 2: Vs"s=OV unless otherwise specified.
Nole 3: 10L and 10H are tested one output at a time.
Nole 4: Cpo determines the no load AO power consumption of any OMOS device. For complete explanation see 5401740 Family
Characteristics, Application Note AN-90.
5-23
o
.
~National
.~ ~ Semiconductor
;
o
~ CD4006BM/CD4006BC 1S-Stage Static Shift Register
§ General Description
C
o
Features
The CD4006BM/CD4006BC 18-stage static shift
register Is comprised of four separate shift register
sections, two sections of four stages and two sections
of five stages. Each section has an independent data
input. Outputs are available at the fourth stage and the
fifth stage of each section. A common clock signal Is
used for all stages. Data is shifted to the next stage on
the negative·going transition of the clock. Through
appropriate connections of inputs and outputs, multiple
register sections of 4, 5, 8, and 9 stages, or Single regis·
ter sections of 10, 12, 13, 14, 16, 17, and 18 stages can be
implemented using one package.
• Wide supply voltage range
• High noise Immunity
Logic Diagrams
Connection Diagram
3.0Vto 15V
0.45 Voo (typ.)
fan out of 2 drYing 74L
or 1 driving 74LS
• Low power TTL
compatibility
• Low clock Input capacitance
6 pF (typ.)
10 MHz (typ.) (with Voo = 10V)
• Medium speed
• Low power
• Fully static operation
Dual·ln·Line Package
r
-{>o--
OUTPUT
IF4TH OR
5TH STAGE
I
TO NEXT STAGE
0"
FROM
PREVIOUS
STAGE
(DR DATA
IF 1ST STAGE)
TUFI5942·1
DATA 1
NC
CLOCK
DATA 2
DATA J
DATA 4
Vss
TOP VIEW
TLIF!5942-3
Order Number CD4006BMJ or CD4006BCJ
See NS Package Jl:4A
Order Number CD4006BMN or CD4006BCN
See NS Package N14A
r-f,
TtL
-H if!
I
I
~f-J
C[
·1,
I .I+-I
-HI .i.
Truth Table
L-f.....lI
CL
TUF/5942·2
D
CL'"
0+1
0
~
0
1
--"L
1
X
~
NC
x = Don't care
6. == Level change
NC = No change
TL.IFI5942-4
5·24
Absolute Maximum Ratings
Recommended Operating Conditions
(Notes 1 and 2)
(Note 2)
Voo DC Supply Voltage
-0.5to+18Voc
VIN Input Voltage
-0.5 to Voo + 0.5 Voc
-65·C to +150·C
Ts Storage Temperature Range
Po Package Dissipation
500mW
260·C
TL Lead Temperature (Soldering, 10 seconds)
Voo DC Supply Voltage
VIN Input Voltage
TA Operating Temperature Range
CD4006BM
CD4006BC
DC Electrical Characteristics
Sym Parameter
+3.0to+15V
OtoVoo Voc
-55·C to +125·C
-40·C to +85·C
-55°C
Typ
Max
5.0
10
20
150
300
600
IJA
IJA
IJA
VOL Low Level
Output Voltage
Voo =5.0V
Voo=10V
Voo=15V
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
VOH High Level
Output Voltage
Vo o =5.0V
Voo=10V
Voo=15V
VIL Low Level
Input Voltage
Voo=5.0V, Vo =0.5Vor 4.5V
Voo=10V, Vo = 1.0V or 9.0V
Vo o =15V, Vo =1.5Vor 13.5V
VIH High Level
Input Voltage
Voo = 5.0 V, Vo =0.5Vor 4.5V
Voo= 10 V, Vo= 1.0 V Dr 9.0 V
Voo =15V, Vo=1.5V or 13.5V
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.50
8.25
3.5
7.0
11.0
V
V
V
10L Low Level
Output Current
(Note 3)
Voo=5.0V, Vo=0.4V
Vo o =10V, Vo=0.5V
Voo =15V, Vo=1.5V
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
IOH High Level
Output Current
(Note 3)
Voo=5.0V, Vo =4.6V
Vo o =10V, Vo=9.5V
Voo =15V, Vo=13.5V
-0.64
-1.6
-4.2
-0.51
-1.3
-3.4
-0.88
-2.25
-8.8
-0.36
-0.9
-2.4
Voo =15V, VIN=OV
Voo=15V, VIN=15V
-0.1
-0.1
-10 5
10-5
rnA
rnA
rnA
rnA
rnA
rnA
IJA
IJA
liN
Input Current
DC Electrical Characteristics
Sym Parameter
100 Quiescent
Device Current
VOH High Level
Output Voltage
Voo=5.0V
Voo=10V
Vnn=15V
Input Voltage
VIH High Level
Input Voltage
1.5
3.0
4.0
5.0
10
15
2.25
4.50
6.75
0.1
4.95
9.95 '
14.95
V
V
V
1.5
3.0
4.0
1.5
3.0
4.0
-1.0
0.1
1.0
V
V
V
Min
20
40
80
0.005
0.010
0.015
20
40
80
150
300
600
IJA
IJA
IJA
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
4.95
9.95
14.95
5·25
5.0
,0
15
2.25
4.5
6.75
3.5
7.0
11
2.75
5.5
8.25
Min
Units
Max
1.5
3.0
4.0
3.5
7.0
11
85°C
Typ
Max
4.95
9.95
14.95
Voo = 5.0 V, Vo=0.5V or 4.5V
Voo =10V, Vo= 1.0Vor 9.0V
Voo =15V, Vo =1.5V or 13.5V
Voo=5.0V, Vo =0.5Vor 4.5V
Voo = 5.0 V, Vo = 1.0 V 0(9.0 V
Voo=15V, Vo =1.5Y.or 13.5V
,25OC
-400C
Min
Voo = 5.0 V, VIN = Voo or Vss
Voo = 10 V, VIN = Voo or Vss
Voo = 15 V, VIN = Voo or Vss
Vo o -5.0V
Voo=10V
Voo=15V
4.95
9.95
14.95
Max
CD4006BC (Note 2)
Conditions
VOL Low Level
Output Voltage
VIL Low Level
4.95
9.95
14.95
Min
Units
0.005
0.010
0.015
Max
Min
1250C
5.0
10
20
Quiescent
Device Current
Min
250C
Voo = 5.0 V, VIN = Voo or Vss
Voo = 10 V, VIN = Voo or Vss
Voo = 15 V, VIN = Voo or Vss
100
c
a
s:
OJ
(=)
c
~
iOJ
CD4006BM (Note 2)
Conditions
o
Max
4.95
9.95
14.95
1.5
3.0
4.0
V
V
V
1.5
3.0
4.0
3.5
7.0
11
V
V
V
V
V
V
o
DC Electrical Characteristics
Sym Parameter
(cont'd) CD4006BC (Note 2)
-40°C
Conditions
Min
25°C
Max
Min
Typ
85"C
Max
Min
Max
Units
IOL low level
Ou'tput Current
(Note 3)
Voo = 5.0 V, Vo=O.4V
Voo =10V, Vo=0.5V
Voo=15V, Vo=1.5V
0.52
1.3
3.6
0.44
1.1
3.0
0.88
2.25
8.8
0.36
0.9
2.4
mA
mA
mA
IOH High Level
Output Current
(Note 3)
VIL=OV, VIH =Voo
Voo=5.0V, Vo=4.6V
Vo o=10V, Vo=9.5V
Voo=15V, Vo=13.5V
-0.52
-1.3
-3.6
-0.44
-1.1
-0.3
-0.88
-2.25
-8.8
-8.8
-0.36
-0.9
-2.4
mA
mA
mA
liN, Input Current
Voo=15V, VIN=OV
Voo=15V, VIN =15V
-10- 5
10-5
-0.3
0.3
AC Electrical Characteristics
-0.3
0.3
p.A
p.A
-1.0
1.0
CD4006BM/CD4006BC TA = 25°C, CL = 50 pF, unless otherwise noted
Typ
.Max
tpLH, tpHL Propagation Delay Time (tpLH =tPHU
Voo=5.0V
Voo=10V
Voo=15V
200
100
80
400
200
150
ns
ns
ns
tTLH, tTHL Transition Time (tTLH = tTHLl
Voo'=5.0V
Voo=10V
Voo=15V
100
50
40
200
100
80
ns
ns
ns
Voo=5.0V
Voo=10V
Voo=15V
100
45
35
200
100
70
ns
ns
ns
15
15
15
p's
P.s
P.s
100
50
40
ns
ns
ns
110
70
ns
ns
ns
Symbol
tWL,tWH
Conditions
Parameter
Minimum Clock Pulse Width (tWL=tWH)
tRCL, tFCL Clock Rise and Fall Time (tRCL = tFcLl
tsu
tH
fCL
CL
Min
Voo=5.0V
Voo=10V
Voo=15V
Minimum Set-up Time
Minimum Hold Time
' Maximum Clock Frequency
50
Voo=5.0V
Voo=10V
Voo=15V
25
20
Voo=5.0V
Voo=10V
VDD=15V
55
35
30
2.5
5.0
7.0
Voo=5.0V
, Voo=10V
Voo=15V
Input Capacitance
Data Input
ClK Input
60
Units
5.0
12
16
MHz
MHz
MHz
5.0
7.5
pF
pF
Nole 1: "Absolute Maximum Ratings" are those values beyond which the safety of the' device cannot be guaranteed; they are not
meant to Imply that the devices should be operated at these limits. The tables of "Recommended Operating Conditions" and
"Electrical Characteristics" provide conditions for actual device operation.
Nole 2: Vss = 0 V unless otherwise specified.
Nole 3: 10L and 10H are tested one output at a time.
Switching Time Waveforms
VDD
--1'1- -~
:'~'
9B%
CLOCK vss'O%
90%,
'0%
'0%
10%
tWH---tWL-
DATA
'--":f
":..j:
v..
VDD
-j
,0'
-I
-.
1-'''" :,'
-IsETUP
'0%
90%
10%.ifsO
%
OUTPUT
,v"
'sETUP
I--
t pLH
t.=t,"'20ns
-I
90.
50.
-
--tTHL
'0'
tpHL
TLIF/5942-5
5·26
.
~ Semiconductor
~National·
CD4007M/CD4007C Dual Complementary Pair
Plus Inverter
General Description
Features
The CD4007M/CD4007Cconsists of three complementary
pairs of N- and P-channel enhancement mode MOS transistors suitable for series/shunt applications. All inputs
are protected from static discharge by diode clamps to
Voo and Vss·
- Wide supply voltage range
_ High noise immunity
For proper operation the voltages at all pins must be
constrained to be between Vss -0.3V"and Voo + 0.3V at
ali times.
Connection Diagram
Dual-In-Line Package
VOD
14
13
12
11
10
Vss
TDP VIEW
TUFI5!M3-1
Note: All P-channel substrates are connected to VOO
. and all N-channal substrates are connected to VSS-
Order Number CD4007MJ or CD4007CJ
See NS Package J14A
Order Number CD4007MN or CD4007CN
See NS Package N14A
5-27
3.0Vto 15V
0.45 Vcc (typ.)
Absolute Maximum Ratings
(Note 1)'
Voltage at Any Pin
Vss - 0.3V to Voo + 0.3V
Operating Temperature Range
- 55·C to + 125·C
CD4007M
-40·C to +85·C
CD4007C
DC Electrical Characteristics -
Storage Tempeature Range
-65·Cto +150·C
Package Dissipation
500mW
.
Operating Voo Range
Vss +3.0Vto Vss + 15V
Lead Temperature (Soldering, 10 seConds)
260·C
CD4007M,
Limits
Sym
Parameter
Conditions
-55°C
Min
Typ
25°C
Max Min
Typ
Units
125°C
Max Min
Typ
Max
IL
Quiescent Device
Current
Voo =5.0V
Voo=10V
0.05
0.1
0.001 0.05
0.001 0.1
3.0
6.0
,.,A
,.,A
Po
Quiescent Device
Dissipation/Package
Voo,=5.0V
Voo=10V
0.25
1.0
0.005 0.25
0.001 1.0
15
60
,.,W
,.,W
VOL
Output Voltage Low
Level
Vo o =5.0V
Voo=10V
0.05
0.05
0.05
0.05
V
V
VOH
Output Voltage High
Level
Voo =5.0V
Voo=10V
4.95
9.95
4.95
9.95
5.0
10
4.95
9.95
V
V
VNL
Noise Immunity
(All inputs)
Voo= 5.0V, Vo=3.6V
Voo = 10V, Vo = 7.2V
1.5
3.0
1.5
3.0
2.25
4.5
1.4
2.9
V
V
VNH
Noise Immunity
(All inputs)
Voo = 5.0V, Vo=0.95V
Vo o =10V, Vo=2.9V
1.4
2.9
1.5
3.0
2.25
4.5
1.5
3.0
V
V
IoN
Output Drive Current
N·Channel
Voo=5.0V, "o=0.4V, V,=Voo
Voo= 10V, Vo =0.5V, V,=Vo o
0.75
1.6
0.6
1.3
1.0
2.5
0.4
0.95
mA
mA
loP
Output Drive Current
P-Channel
Voo = 5.0V, Vo = 2.5V, V, = Vss
Voo = 10V, Vo = 9.5 V, V,;" Vss
-1.75
-1.35
-1.0
':'0.75
mA
mA
I, .
Input Current
0
0
0.05
0.05
-1.4 -4.0
-1.1 -2.5
10
DC Electrical, Characteristics -
pA
CD4007C
Limits
Sym
Parameter
Conditions
-40°C
Min' Typ Max Min
25°C
Typ
Max Min
Units
85°C
Typ Max
IL
Quiescent Device
Current.
Voo =5.0V
Voo=10V
0.5
1.0
0.005 0.5
0.005 1.0
15
30
,.,A
Po
Quiescent Device
Dissipation/Package
Vo o =5.0V
Voo=10V
2.5
10
0.025 2.5
0.05 10
75
300
,.,W
,.,W
VOL
Output Voltage Low
Level
Voo=5.0V,
Voo=10V
0.05
0.05
0.05
0.05
V
V
VOH
Output Voltage High
Level
Voo =5.0V
Voo=10V
4.95'
9.95
4.95
9.95
5.0
10
4.95
9.95
V
V
VNL
Noise Immunity
(All inputs)
Voo=5.0V, Vo=3.6V
Voo = 10V, Vo = 7.2V
1.5
3.0
1.5
3.0
2.25
4.5
1.4
2.9
V
V
VNH
Noise Immunity
(All inputs)
Voo=5.0V, Vo=0.95V
Voo = 10V, Vo = 2.9V
1.4
2.9
1.5
3.0
2.25
4.5
1.5
3.0
V
V
IoN
Output Drive Current
N-Channel
Voo=5.0V, Vo=0.4V, V,=Voo
Voo = 10V, Vo = 0.5V, V, = Voo
0.35
1.2
0:3
1.0
1.0
2.5
0.24·
0.8
mA
mA
loP
Output Drive Current
P·Channel
Voo = 5.0V, Vo = 2.5V, V, = Vss
Vo o =10V, Vo=9.5V, V,=Vss
-1.3
-0.65
-1.1 ~4.0
-0.55 -2.5
-0.9
-0.45
mA
mA
I,
Input Current
0
0
10
0.01
0.01
,.,A
pA
Nole 1: This device should not be connected to circuits with the power on because high transient voltages may cause permanent damage.
5·28
o
AC Electrical Characteristics
- CD4007M TA = 25°C and C L =15pF and rise and fall times=20ns.
Typical temperature coefficient for all values of Voo = 0.3%IOC
Parameter
Conditions
Typ
Max
Units
tpLH = tpHL Propagation Delay Time
Voo =5.0V
Voo=10V
35
20
60
40
ns
ns
tTLH = tTHL Transition Time
Voo =5.0V
Voo=10V
50
30
75
40
ns
ns
Any Input
5.0
Symbol
Input Capacitance
C1
Min
pF
AC Electrical Charac.teristics
CD4007C TA = 25°C and C L =15pF and rise and fall times=20ns.
Typical temperature coefficient for all values of Voo = 0.3%I"C
.-.
Parameter
Conditions
Typ
Max
Units
tpLH = tpHL Propagation Delay Time
Voo =5.0V
Voo=10V
35
20
75
50
ns
ns
tTLH = tTHL Transition Time
Voo =5.0V
Voo = 10V
50
30
100
50
ns
ns
Any Input
5
Symbol
,
Input Capacitance
C1
Min
pF
AC Test Circuits
VDD
VDD
J
J'4.Z
INPUT
-£1'H
J
I
N
1.
4
J
OUTPUT
.
HOUT.UT
I
N
INPUT
TUF15943·2
INPUT
.~~
..
10%
\PHI.
VDD
10%
tpLH
-
90%
50%
"\ 10%
OUTPUT
Vss
tTHL-
_t,
90%1~
50%
50%
VSS
I-
1-
I
50%
10%.,11
tTLH- _
90%
l-
t.. =1, = 20n5
TLlFI5943-5
5·29
t5pF
TUF/5943-4
Switching Time Waveforms
-I
N
OUTPUT
1J
TUFI5943-3
I-t,
8.13
6
I
15pF
9
-j
\1.n
J'4
~C'
1. J
INPUT 10
15pF
VDD
14. 11
c
§......
-oc
3:
~
o......
o
(.)
,
!
~National
~ ~ Semiconductor
(.)
~ CD4008BM/CD4008BC 4-Bit Full Adder
§
(.)
General Description
Features
The CD4008B types consist of four full-adder stages with
fast look-ahead carry provision from stage to stage. Circuitry Is Included to provide a fast "parallel-carry-out" bit
to permit high-speed operation In arithmetic sections
using several CD4008B's. CD4008B inputs include the
four sets of bits to be added, A1 to A4 and B1 to B4, in
addition to the "Carry In" bit from a previous section.
CD4008Boutputs Include the four sum bits, 51 and 54,
In addition to the high-speed "parallel-carry-out" which
may be utilized at a succeeding CD4008B section.
• Wide supply voltage range
All inputs are protected from damage due to static discharge by diode clamps to Voo and GND.
3.0Vto15V
0.45 Vee (typ.)
• High noise Immunity
fan out of 2 driving 74L
or 1 driving 74L5
• Low power TTL
compatibility
• 4 sum outputs plus parallel look-ahead carry-output
• Quiescent current specified to 15V
• Maximum inpu~ leakage of l"A at 15V (full package
temperature range)
Block Diagram
Truth Table
HIGHSPEED
PAR. CARRY
1---""";';"'0 Co !CARRY OUT!
8'
83
ii2 _4
~~~~-r~---------+I
81 ~~f-+""'-----------+I
AI o-.:..--1~-------------+I
.2
Ai
Bi
Ci
CO
SUM
0
0
1
0
0
0
1
1
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
1
1
0
1
1
1
0
1
1
.1
1
1
1
1
81
CllCARRY INI o.::._~-----------------1
TLrF/5944-1
Connection Diagram·
Dual·ln-Line Package
.. 1
1& Voo
83 2
1. B4
A3 3
l' Co ICARRY OUTI
Order Number CD4008BMJ or CD4ilO8BCJ
See NS Package J16A
Order Number CD4008BMN or CD4008BCN
See NS Package N16E
10 51
AI 7
CIICARRY INI
Vss •
70PVIEW
TL/FI5944-2
5-30
Absolute Maximum Ratings
(Notes 1 and
Recommended Operating Conditions
21
(Note
Voo de Supply Voltage
-0.5 to +18 Voe
VIN Input Voltage
-0.5 to Voo +0.5 Voe
~5°e to +1500 e
TS Storage Temperature Range
500mW
Po Package Oissipation
2S0°C
TL Lead Temperature (Soldering, 10 secondsl
DC Electrical Characteristics
21
Voo de Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
e04008BM
eD40088C
CD4008BM (Note
IDO
VOL
CONDITIONS
PARAMETER
Quiescent Device Current
Low Level Output Voltage
VOO
VOO
VOO
VOH
VIL
High Level Output Voltage
Low Level Input Voltage
2SOC
10L
High Level Input Voltage
Low level Output Current
(Note 3)
= 5V, VIN = VOO or VSS
= 10V, VIN = VOO or VSS
= 15V, VIN = VOO or VSS
High Level Output Current
(Note 3)
Input Current
20
O.oS
0.05
0.05
4.95
4.95
VOO = ISV
14.95
9.95
14.95
S.
10
= 15V, Vo = 1.5V or 13.5V
3.5
7.0
3.5
7.0
vorl = 15V, Vo = 1.5V or 13.5V
11.0
11.0
VOO = 5V, Vo = O.4V
VOO = loV, Vo = 0.5V
0.64
0.51
1.6
4.2
1.3
ISO
300
600
O.OS
0.05
0.05
0.05
0.05
0.05
4.95
UNITS
I'A
I'A
I'A
V·
V
V
V
V
9.95
14.9S
V
I.S
3.0
4.0
V
V
V
3.5
V
7.0
11.0
V
V
0.88
0.36
0.9
2.4
mA
mA
3.4
2.25
8.8
-3.0
Vo "3.5
Vo "7.0
0.4
0.5
2.5
9.5
5
10
5
10
5
10
5
10
3.75
10
,5 -1:85
10 -0.9
3
4
8
10
-1.25 -1.75
-0.6 -0.8
10
Input Current
2.25
4.5
2.25
4.5
2.25
4.5
2.4
6.4
-1
-0.48
pA
10
Note 1: This device should not be connected to circuits with the power on because high transient voltage may cause permanent damage.
Note 2: ION and lOP are tested one output at a time.
AC Electrical Characteristics TA = 25°C, CL=15pF, unless otherwise noted
Typical Temperature Coefficient for all values of Vee; 0.3%tc
LIMITS
TEST
CONOITIONS
CHARACTERISTIC
Propagation Delay Time
High to Low Lpwl
~tpHL'
Vee - Voo
C040XXM
Vaa
(VOLTSI
5'
10
Vee'" 10V
Vee - 5V
low 10 High level !IPLH)
Vee'" 5V
TranSitIon Time
Hlgh-to~LOW Level {tn-old
low-to-HIgh Level (tTLHI
Input CapacItance (Cd
Vee
=:
5
10
5
10
Voo
Vee" Voo
TYP
MAX
MIN
TYP
MAX
-
15
-
10
55
30
15
10
40
10
25
10
35
50
25
80
55,
-
50
25
100
70
15
30
-
15
40
20
16
80
45
40
125
100
20
16
80
50
5
.60
50
-
-
Veo = lOV
50
-
Any Input
Typical Applications
v" v,.
v"
va'
v",
UNITS
MIN
-
5
10
Vee"< Vee
C040XXC
-
5
·,V
v"
TTl
TLIF/5945-5
':'
5-34
-
-
-
70
160
120
-
rnA
rnA
rnA
rnA
n,
n'
n,
n,
of
~Nationai
~ Semiconductor
CD4013BM/CD4013BC Dual D Flip-Flop
General Description
Features
The CD4013B dual D flip·flop Is a monolithic comple·
mentary MOS (CMOS) Integrated circuit constructed with
N· and P·channel enhancement mode transistors. Each
flip·flop has independent data, set, reset, and clock
outputs. These devices can be
inputs and "0" and
used for shift register applications, and by connecting
''0'' output to the data input, for counter and toggle ap·
plicatlons. The logic level present at the "D" Input Is
transferred to the 0 output during the posltive-golng
transition of the clock pulse .. Setting or resetting Is Independent of the clock and Is accomplished by a high level
on the set or reset line respectively.
• Wide supply voltage range
"cr'
• High noise immunity
• Low power TTL
compatibility
3.0Vto 15V
0.45 Voo (typ.)
fan out of 2 driving 74L
or 1 driving 74LS
Applications
•
•
•
•
Automotive
Data terminals
Instrumentation
Medical electronics
• Alarm system
• Industrial electronics
• Remote metering
• Computers
Connection Diagram
Dual·1 n·Lina Package
oz
VDD
L4
U2
13
CLOCK2
12
ReSET 2
11
DATAZ
I
I
F/F
F/F
1
2
I
'":I
Ql
r
I
SETZ
19
L
10
Order Number CD4013BMJ or CD4013BCJ
See NS Package J14A
Order Number CD4013BMN or CD4013BCN
See NS Package N14A
I
4
CLOCK 1
RESET 1
p
DATAl
SET 1
Vss
TOP VIEW
TUF/546-1
Truth Table
CLt
D
R
S
Q
f
.r
0
0
0
"\...
x
x
x
x
0
0
0
x
x
x
1
0
D.
1
0
0
0
0
Q
0
Q
1
0
Nochl!.nge
t • Lev.. change
x • Don't care CM8
5-35
•
o
In
Absolute Maximum Ratings
ic
o
(Notes 1 and 2)
(Note 2)
Voo de Supply Voltage
-0.5 to +18 Voc
VIN Input Voltage
-0.5 to VOO +0.5 VOC
--6SoC to +150°C
TS Storage Temperature Range
Po Package Dissipation
SOOmW
260·C
TL Lead Temperature (Soldering, 10 seconds)
Voo de Supply Voltage
V I N I nput Voltage
T A Operating Temperature Ranga
C04013BM
C04013BC
,....
('I)
:E
In
('I)
,....
ic
o
DC Electrical Characteristics
Recommended
PARAMETER
VOL
Quiescent Device Current
Low Level Output Voltage
Voo = 5V, V1N = Voo or Vss
Voo= 10V, VIN=VOO or Vss
Voo.=15V, VIN=VOOorVss
VIL
High Level Output Voltage
Low Level Input Voltage
VOO = 5V
Von= 10V
4.95
9.95
VOO = 15V
IOL
Low Level Output Current
(Note 3)
12SoC
2S·C
MIN
TYP
MAX
MIN
MAX
1.0
2.0
4.0
1.0
2.0
4.0
30
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
UNITS
I'A
I'A
I'A
60
120
0.05
14.95
4.95
4.95
9.95
9.95
14.95
14.95
,
IIOI<1.0I'A
1.5
1.5
3.0
3.0
4.0
. VOO = 15V, Vo = 1.5V or 13.5V
High Level Input Voltage
MAX
V
V
V
IIOIc>----I
,
Cl.o--t:><>-----+--------ir-------+-----'
R.'O'·--[>~----_--------_--------~------~
5-44
TLIFI594a..3
Absolute Maximum Ratings
o
c
Recommended Operating Conditions
~
(Notes 1 and 2)
VOO
VIN
TS
Po
TL
DC Supply Voltage
-0.5to +18VOC
Input Voltage
-0.5 to VOO + 0.5 Vnc
Storage Temperature Range -65to +150·C
Package Dissipation
500mW
Lead Temperature
(Soldering, 10 seconds)
260·C
VOO
VIN
TA
DC Supply Voltage
+3to +15VOC
Input Voltage
OtoVOOVOC
Operating Temperature Range
C04015BM
-55·Cto +125·C
C04015BC
-40·Cto +85·C
....
U'I
III
3:
(;
c
~
....
U'I
III
o
PC Electrical Characteristics
(Note 2) -
C04015BM
-55°C
Min
Max
Conditions
25°C
Typ
125°C
Min
Max
Sym
Parameter
100
Quiescent
Device Current
Voo = 5V, VIN = Voo or Vss
Voo = 10V, VIN = VDO or Vss
Voo =15V, VIN=VOOorV ss
VOL
'Low Level
Output Voltage
VOO=5V}
VOO=10V \IOL\=1/LA
VOO= 15V
VOH
High Level
Output Voltage
VOO=5V}
VOO=10V \IOL\ =1/LA
VOO=15V
VIL
Low Level
Input Voltage
VOO=5V, Vo = 0.5V or 4.5V
VOO = 10V, Vo = 1.0V or 9.0V
VOO=15V, VO=1.5Vor 13.5V
VIH
High Level
In put Voltage
VOO=5V, Vo = 0.5V; or 4.5V
VOO = 10V, Vo = 1.0V or 9.0V
VOO=15V, VO=1.5Vor 13.5V
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.50
8.25
3.5
7.0
11.0
V
V
V
IOL
Low Level
Output Current
(Note 3)
VOO=5V, ,VO=O.4V
VOO=10V, VO=0.5V
VOO=15V, VO=1.5V
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
rnA
rnA
rnA
IOH
High Level
Output Current
(Note 3)
VOO=5V, VO=4.6V
VOO = 10V, Vo = 9.5V
VOO = 15V, Vo = 13.5V
-0.64
-1.6
-4.2
-0.36
-0.9
-2.4
rnA
rnA
rnA
liN
Input Current
VOO=15V, VIN=OV .
VOO = 15V, VIN = 15V
Max
Units
5
10
20
0.005
0.010
0.015
5
10
20
150
300
600
Il A
Il A
Il A
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
4.95
9.95
14.95
4.95
9.95
14.95
1.5
3.0
4.0
5
10
15
2.25
4.50
6.75
4.95
9.95
14.95
1.5
3.0
4.0
-0.51 -0.88
-1.3 -2.25
-3.4 -8.8
-0.1
0.1
5·45
Min
-10- 5 -0.1
10- 5
0.1
V
V
V
1.5
3.0
4.0
-1.0
1.0
V
V
V
Il A
Il A
o
£D
DC Electrical Characteristics
o
Sym
Parameter
100
Quiescent
Device Current
V oo =5V, VIN=VOOorVss
V oo =10V, VIN=VOOorVss
Voo = 15V, VIN = Voo or Vss
VOL
Low Level
Output Voltage
VOO=5V
VoO=10V
VOO=15V
VOH
High Level
Output Voltage
VOO=5V
VOO=10V
VOO=15V
r.n
,..
i
c
~
£D
r.n
,..
ic
(.)
(Note 2) -
C040158C
-40°C
Condltlo!!s
Min
Max
25°C
85°C
Max
20
40
80
0.005
0.010
0.015
20
40
80
150
300
600
,..A
,..A
,..A
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
4.95
9.95
14.95
5
10
15
Min
Max
Units
Typ
4.95
9.95
14.95
Min
V
V
V
4.95
9.95
14.95
V
V
Low Level
.Input Voltage
VOO = 5V, Vo = 0.5Y. or 4.5V
VOO=10V, VO=1.0Vor 9.0V
VOO = 15V, Vo = 1.5V or 13.5V
VIH
High Level
Input Voltage
VOO=5V, Vo = 0.5V; or 4.5V
VOO = 10V, Vo = 1.0V or 9.0V
VOO = 15V, Vo = 1.5V or 13.5V
'3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.50
8.25
3.5
7.0
11.0
V
V
V
IOL
Low Level
Output Current
(Note 3)
VOO=5V, VO=0.4V
VOO = 10V, Vo = 0.5V
VOO = 15V, Vo = 1.5V
0.52
1.3
3.6
0.44
1.1
3.0
0.88
2.25
8.8
0.36
0.9
2.4
mA
mA
mA
IOH
High Level
Output Current
(Note 3)
VOO=5V, VO=4.6V
VOO = 10V, Vo = 9.5V
VOO = 15V, Vo = 13.5V
-0.52
-1.3
-3.6
-0.36
-0.9
-2.4
mA
rnA
rnA
liN
Input Current
VOO = 15V, VIN = OV
VOO = 15V, VIN = 15V
VIL
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
-0.44 -0.88
-1.1 -2.25
-3.0 -8.B
-0.3
0.3
-10- 5 -0.3
10- 5
0.3
1.5
3.0
4.0
V
V
-1.0
1.0
,..A
,..A
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed, they are not
meant to imply thanhe devices should be operated at these limits. The tables of "Recommended Operating Conditions" and
"Electrical Characteristics" provide conditions for actual device operation.
Note 2: VSl:);;; OV unless otherwise specified.
Note 3: 10H and 10L are tested one output at a time.
o'
546
o
AC Electrical Characteristics
Symbol
TA=25'C, CL=50pF; RL=200K, tr=tf=20ns,unless otherwise specified.
Parameter
Units
Conditions
tpHl, tPlH
Propagation Oelay Time
VOO=5V
VOO=10V
VOO=15V
230
80
60
350
160
120
ns
ns
ns
tTHl, tTlH
Transition Time
VOO=5V
VOO=10V
VOO=15V
100
50
40
200
100
80
ns
ns
ns
VOO=5V
VOO=10V
VOO=15V
160
60
50
250
110
85
ns
ns
ns
15
15
15
I'S
I'S
I'S
100
40
30
ns
ns
ns
. Minimum Clock Pulse-Width
Clock Rise and Fall Time
VOO=5V
VOO=10V
VOO=15V
tsu
Minimum Oata Set-Up Time
VOO=5V
VOO=10V
VOO=15V
fel
Maximum Clock Frequency
VOO=5V
VOO=10V
VOO= 15V'
CIN
Input Capacitance
Clock Input
Other Inputs
7.5
5
10
7.5
pF
pF
tpHl(R)
Propagation Oelay Time
VOO=5V
VOO=10V
VOO=15V
200
100
80
400
200
160
ns
ns
ns
tWH(R)
Minimum Reset Pulse Width
VOO=5V
VOO=10V
VOO=15V
135
40
30
250
80
60
ns
ns
ns
trel, t,el
m
:s::
Clocked Operation
tWl,tWM
~....
UI
50
20
15
2
4.5
6
3.5
8
11
MHz
MHz
MHz
Reset Operation
5-47
o
~
....
UI
m
o
o
~ ~National
~ ~ Semiconductor
o
~ CD4016BM/CD4016BC Quad Bilateral Switch
m
co
..... General Description
~
CJ
The CD4016BM/CD4016BC is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-far-pin compatible with CD4066BM/
CD4066BC.
Features
3V to 15V
Wide supply voltage range
Wide range of digital and analog switching ±7.5 VPEAK
400n (typ.)
"ON" resistance for 15V op"eration
Matched "ON" resistance over 15V
signal input
aRON=10n (typ.)
0.40/0 distortion (typ.)
• High degree of linearity
, @fIS= 1 kHz, VIS=5Vp_p,
•
•
•
•
Voo-VSS= 10V, RL = 10 kn
• Extremely low "OFF" switch leakage
0.1 nA (typ.)
@Voo - Vss= 10V
TA=25°C
• Extremely high control input impedance
1012n
• Low crosstalk between switches
- 50 dB
@fI5=0.9MHz,RL=
• Frequency response, switch ",ON"
'40 MHz
(typ.)
(typ.)
1 kn
(typ.)
Applications
• Analog signal switching/multiplexing
• Signal gating
• Squelch control
• Chopper
• MOdulator/Demodulator
• Commutating switch
• Digital,signal switching/multiplexing
• CMOS logic implementation
• Analog-to-digital!digital-to-analog conversion
• Digital control of frequency, impedance, phase, and analog-signal gain
Schematic and Connection Diagrams
Dual-In-Llne Package
~
OUT/IN-4-~21-- II~_==~~::.
.,orr-LJ
CONTROL--~P---..fbo
....
......
1
OUTIIN -1P-.....,
I N / O U T - - I l f - OUTIIN
INIOUT
INIOUT
CONTROL 8
CONTROL C-"i-----.,
r-----t-::... DUTIIN
INIOUT
VSS
TOP VIEW
TL/F/5661-1
Order Number CD4016BMJ or CD4016BCJ
NS Package J14A
Order Number CD4016BMN or CD4016BCN
NS Package N14A
5·48
o
Absolute Maximum Ratings
c
Recommended Operating
Conditions (Note 2)
(Notes 1 and 2)
VOO Supply Voltage
-0.5Vto +18V
VIN Input Voltage
- 0.5V to Voo + 0.5V
TS Storage Temperature Range
-65'Cto + 150'C
Po Package Dissipation
500mW
Lead Temperature (Soldering, 10 seconds)
260'C
~
....
Q)
3Vto 15V
Voo Supply Voltage
VIN Input Voltage
TA Operating Temperature Range
CD4016BM
CD4016BC
OVtoVoo
-S5'C to + 125'C
-40'C to +85'C
m
s::
(;
a....
Q)
m
o
DC Electrical Characteristics CD4016BM (Note 2)
Parameter
Symbol
-55'C
. Conditions
100
125'C
25'C
Units
Typ
Max
0.25
0.5
1.0
0.01
0.Q1
0.Q1
0.25
0.5
1.0
7.5
15
30
p.A
p.A
p.A
Ve=Voo, Vls=VssorVoo
Voo=10V
Voo=15V
600
360
250
200
660
400
960
600
0
0
RL=10kOto Voo-Vss
2
Ve=Voo
Voo=10V, VIS=4.75 to 5.25V
Voo=15V, VIS=7.25 to 7.75V
1870
775
850
400
2000
850
2600
1230
0
0
Min
Quiescent Device Current Voo=5V, VIN=VOOorVss
Voo=10V, VIN=VOOorVss
Voo=15V, VIN=VOOorVss
Max
Min
Min
Max
Signal Inputs and Outputs
RON
aRON
liS
"ON" Resistance
RL = 10 kO to Vco;Vss
a "ON" Resistance
Between any 2 of
4 Switches
(In Same Package)
RL=10kOto Voo-Vss
2
Ve=Voo, VIS""VSS to Voo
Voo=10V
Voo=15V
Input or Output Leakage
Switch "OFF"
Ve=O, Voo=15V .
Vls=15Vand OV,
Vos=OVand 15V
15
10
±50
±0.1
0
0
±50
±500
nA
-
Control Inputs
VILe
VIHe
liN
Low Level Input Voltage
High Level Input Voltage
Input Current
VIS=VSS and Voo
Vos = Voo and V"ss
Ils= ± 10 p.A
Voo=5V
Voo=10V
Voo=15V
Voo=5V
Voo=10V
Voo=15V
0.9
0.9
0.9
(see Note 6 and
FigureS)
3;5
7.0
11.0
3.5
7.0
11.0
±0.1
Voo-Vss= 15V
VOO~VIS~VSS
Voo~Ve~Vss
549
0.5
0.5
0.5
0.7
0.7
0.7
3.5
7.0
11.0
±10-5
±0.1
V
V
V
V
V
V
±1.0
p.A
(.)
III
CO
,...
~
(.)
DC Electrical Characteristics CD4016BC (Note 2) (Continued)
Parameter
Symbo!
Min
im
100
~(.)
Signal Inputs and Outputs
CO
,...
-4C)"C
Conditions
RON
ARON
Quiescent Device Current Voo=5V. VIN=VOOorVSS
Voo=10V. VIN=VOOOrVSS
Voo=15V. VIN=VooorVSS
"ON" Resistance
A"ON" Resistance
Between ~ny 2 of
4 Switches
(In Same Package)
Input or Output Leakage
Switch "OFF"
liS
RL=10kfltoYoO ·ySS
2
VC=VOO. VIS=VSSorVoO
Voo=10V
Voo=15V
RL=10kflto VOO-VSS
2
VC=Voo
Voo=10V. Vls=4.75t05.25V
Voo=15V. VIS=7.25 to 7.75V
25"C
85"C
Units
Typ
Max
1.0
2.0
4.0
0.01
0.01
0.01
1.0
2.0
4.0
7.5
15
30
jJA
p.A
jJA
610
370
275
200
660
400
840
520
fl
fl
1900
790
850
2000
850
2380
1080
fl
fl
Max
Min
400
Max
Min
RL=10kflto Voo;Vss
Vc=Voo. VIS=VSStoVoo
VoO=10V
Voo=15V
15
10
±0.1
±50
Vc=O. Voo= 15V
VIS=OVor 15V.
VOS= 15V'or OV
fl
fl
±50
±200
nA
0.7
0.7
0.7
0.4
0.4
0.4
V
V
V
Control Inputs
VILC
VIHC
liN
Low Level Input Voltage
High Level Input Voltage
Input Current
VIS = VSS and Voo
Vos=Voo and Vss
IIS=±10jJA
Voo=5V
Voo=10V
Voo=15V
Voo=5V
VOO=10V
VoO=15V
0.9
0.9
·0.9
(see Note 6 and
FigureS)
3.5
7.0
11.0
3.5
7.0
11.0
±0.3
VCC-VSS= 15V
V
V
V
3.5
7.0
11.0
±10-5
±1.0
±0.3
jJA
VOO~VIS~VSS
Voo~Vc~VSS
A"C Electrical Characteristics TA = 25°C. tr= tf= 20 ns and Vss = OV unless otherwise specified
Symbol
Parameter
tpHL. tPLH
Propagation Delay Time
Signal Input to Signal Output
tPZH. tpZL
tpHZ. tpLZ
Propagation Delay TIme
Control Input to Signal
Output High Impedance to
Logical Level
Propagation Delay Time
Controllnput to Signal
Output Logical Level to
High Impedance
Sine Wave Distortion
Typ
Max
Units
Vc=Voo. CL =50 pF. (Figure 1)
RL =200k
Voo=5V
Voo=10V
Voo=15V
58
27
20
100
50
40
ns
ns
ns
RL = 1.0 kfl. CL =50 pF. (Ftgures2
landS)
Voo=5V
Voo=10V
VoO=15V
20
18
17
50
40
35
ns
ns
ns
15
11
10
0.4
40
25
22
ns
ns
ns
%
Conditions
. RL = 1.0 kfl. CL =50 pF. (Figures 2
andS)
Voo=5V
Voo=10V
Voo=15V
Vc=Voo=5V. VSS=-5
RL =10 kfl. VIS=5 Vp_P. f= 1 kHz.
(Figure 4)
5-50
Min
0
.,.C
AC Electrical Characteristics (Continued)
.....
0)
0
TA=25'C, tr=tf=20 ns and Vss=OV unless otherwise specified
Symbol
CondlUons
Parameter
Frequency Response - Switch
"ON" (Frequency at -3 dB)
Feedthrough - Switch "OFF"
(Frequency at - 50 dB)
Crosstalk Between Any Two
Switches (Frequency at -50 dB)
Crosstalk; Control Input to
Signal Output
Maximum Control Input
Typ
Min
CIN
Signal Output CapaCitance
VOO=10V
Feedthrough CapaCitance
Vc=OV
Units
40
VC=VOO=5V, VSS= -5V,
RL = 1 kll, VIS = 5 Vp.p,
20 Logl0 VOslVOS (1 kHz) -dB,
(Figure 4)
Voo=5V, Vc=Vss= -5V,
RL = 1 kll, VIS = 5 Vp.p,
20 Logl0 (VOSlVlsl= -50 dB,
(F/{/ure4)
VOO=VC(A)= 5V; VSS= VC(B) = -5V,
RL = f kIlVIS(A) = 5 Vp.p,
20 Logl0 (VOS(B)IVOS(A»= -50 dB,
(Figure 5)
Voo= 10V, RL = 10 kll
RIN= 1 kll, VCC= 10V Square Wave,
CL = 50 pF (Figure 6)
RL = 1 kll, CL = 50 pF, (F/{/ure 7)
VOS(I)=YaVos(1 kHz)
Voo=5V
Voo=10V
Voo=15V
MHz
1.25
MHz
0.9
MHz
150
mVp.p
6.5
8.0
9.0
MHz
MHz
MHz
4
pF
4
pF
0.2
pF
7.5
5
Control Input CapaCitance
pF
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are nat meant to Imply that the devices
ahauld be operated at these limits. The tables of '"Recommended Operating Conditions" and "Electrical Characteristics'" provide conditions for actual device
operation.
Hote 2: Vss = OV unless olhelwlsa specified.
Note 3: These devices should nat be connected to circuits with the power '"ON".
Note 4: In all casas. there Is approximately 5 pF of probe and jig cepacltence on the output; however, this capacltence is included in CL wherever it Is specified.
Note 5: VIS Is the voltage at the Inlout pin and Ves Is the voltage at the out/in pin. Vo Is the voltage at the control input.
Note 8: If the awilch Input Is hald at Voo. V,HC is the control input level that will causa the awilch output to meet the standard '"B'" saries VOH and IOH output levels.
If the analog awiIch input Is connected to Vss. V,HC is the control input 1eveI- which allows the switch to sink standard '"B" series IIOHI. high lavel current, and still
melntain a VOL " '"B'" sarles. These currents are shown In FIgure 8.
AC Test Circuits and Switching Time Waveforms
v,.v•• ~
vi"
CONTROL
VII
VaD
~
...
~
...,
J
v••
v's.
OV
IIIIOUT ':I::EI OUTn.t-.....- -......- v••
I ..1.".,..I~R_'
1 r
VIS
~.
"as
M
Figure 1. tpLH. tpLH Propagation Delay
T
vc~
CO.TROL
~IS· "00
V~D
~
'1m
C"·'
'
- /srt.
~'. -
ov----J
nme Signal Input ,to Signal Output
IPZH
1_v.
_I
IM/OUT ':'~~:ES OUT/'llt-.....- -......
Vss
v..
"
1..1.
lID.'"
Cl
flL
: q:y
..
v••
,
IV
.
,
v•• ~v••
•
v~PHZ
v••
.v
...
TL/H/5661-2
FIGURE 2. ~. tpHZ Propagation Delay nme Control to Signal Output
5·51
to
-.,.
3:
0
C
Signal Input Capacitance
Cos
Max
0
.....
0)
to
0
o
m
CD
,..
AC Test Circ.uits and Switching Time Waveforms (Continued)
~
o
tPZL
~
IpZl
m
VDD~
..
,..
CD
'V~
. . .Zl
~
c
Vou
o
VOL
11\%
•
'Pl'
VDD~...
.V~
_I~~_
.
VDD
,
VDl
FIGURE 3. tpZH. tpHZ Propagation Delay Time Control to Signal Output
,
VC---.,
v,s
'N/OUT
"':'~~:ES OUTflNt--1I~-Vos
Vss
-5V
VC~YDD
for distortion and frequency response tests
VC~ Vss
for feedthrough test
FIGURE 4. Sine Wave Distortion. Frequency Response and Feedthrough
VCIAI' VOD - - -..
IN/OUT
S~I~~:ES OUTlINt-.....- - VOSiA)
·L
lk
511
VCI.,· Vss - - - - . ,
V,SI.'·DV
INIDUT
SV:'~~H4ES OUTflNI-.....--VosIBI
VSS
-5V
FIGURE 5. Crosstalk Between Any Two Switches
VC----.,
'_20_"'_1-t-~t=_.....,1
VOO _ "
Vc
OV _ _ _ _
~1C9~
r 20",
."'L
'I'
IN/OUT ":'~~H~ES OUTIINt--1_---1_-Vos
Vss
RL
10k
VOS
I
CROSSTALK
j
TLlH/5~1-3
FIGURE 6: Crosstalk - Control to Input Signal Output
5·52
AC Test Circuits and Switching Time Waveforms
T
VC~
CONTROL
1"~-1'~
... .11"
VDD
..
Ve
·,s·VOO- IN/OUT S~'~~:ES OUTIIN
.~
,
DV
YOD'
(Continued)
I..
--Ilf
VOS
J
VSS
.lCl
50
~
..
RL
PF
1
-,VOS.lkHI
Vas
'::"
T
TL/H/5661-4
FIGURE 7. Mal!imum Control Input Frequency
Switch Input
Temperature
Range
Switch Output
VOS(V)
lis (mA)
Voo
VIS
TLOW
25'C
THIGH
5
5
10
10
15
15
0
5
0
10
0
15
0.25
-0.25
0.62
-0.62
-1.8
0.2
-0.2
0.5
-0.5
1.5
-1.5
0.14
-0.14
0.35
-0.35
1.1
-1.1
5
5
10
10
15
15
0
5
0
10
0
15
0.2
-0.2
0.5
-0.5
1.4
-1.4
0.16
-0.,16
0.4
-0.4
1.2
-1.2
0.12
-0.12
0.3
-0.3
1.0
-1.0
MILITARY
COMMERCIAL
I.B
Min
Max
0.4
4.6
0.5
9.5
1.5
13.5
0.4
4.6
0.5
9.5
1.5
13.5
FIGURE 8. CD4016B Switch Test Conditions for VIHC
Typical Performance Characteristics
'ON' Resistance vs. Signal
Voltage TA = 25'C
'ON' Resistance Temperature
Variation for Voo-VSS= 10V
'ON' Resistance Temperature
Variation for VDO-VSS= 15V
gOO
~
~
~
z
~
~'
z
?
800
600
''I
-1
500
V
400
300
.......z 200
z
...c= 100
Oi gOO
1\ Voo - Vss; lOV
\
700
~
~ 800
~
~
. If, ~
(II 1\\\
700
e soo
~ t::....
Voo - Vss; 15V
~
~
r-
~
z
..... 1-'
~
•
-8 -6 -. -2 0 2
SIGNAL INPUT (V,s)(V)
6
8
6DD
400
3DD
200
100
Vi
~I'l
I" ::::::,
-8 -6 -4 -2
...z
.00
.
iii
co
@
..... @
0 2 4
S'GNAL INPUT IVlsliVI
6
+85'C
+2,'C
?
.......z
z
c
...=
100
+125'C
: ::::~, 7
@
.]~
t....
~~
......
1'..'"
~
'.. /
./
"'\:
j
/
'/
300
Z 200
'" "': =:~:~
~
500
~
'/ \'
~ 1:\ ~
,~+125'C
1[";
g:
...~
k:: 7
@
@
-..;;
I
-8 -6 -. -2 0 2 4'
SIGNAL INPUT (VIS)(V)
8
""
~~
-'O'C
-55'C
6
8
TL/H/5661-5
,
5·53
Typical Applications
4 Input Multiplexer
CHANNEL 1
CHANNEL 2
COMMON
CHANNEL 3
CHANNEL 4
3 2 1
CONTROL
Sample/Hold Amplifier
OUTPUT
INPUT
TLlH/5661-6
Special Considerations
supply voltages, ~5V, the CD4016B's on resistance becomes non-linear_ It is recommended that at 5V, voltages
on tile in/out pins be maintained within about 1V of either
Voo or Vss; and that at 3V the voltages on the in/out pins
should be at Voo or VSs for reliable operation.
The CD4016B is composed of 4, two-transistor analog
switches. These switches do not have any linearization or
compensation circuitry for "RON" as do the CD4066B's. Because of this, the special operating considerations for
the CD4066B do not apply to the CD4016B, but at low
5-54
~National
~ Semiconductor
CD4017BM/CD4017BC Decade Counter/Divider with
10 Decoded Outputs
CD4022BM/CD4022BC Divide-by-8 Counter/Divider with
8 Decoded Outputs
General Description
Features
The CD4017BM/CD4017BC is a 5-stage divide-by-10
Johnson counter with 10 decoded outputs and a carry
out bit_
• Wide supply voltage range
• High noise immunity
• Low power
TTL compatibility
The CD4022BM/CD4022BC is a 4-stage divide-by-8
Johnson counter with 8 decoded outputs and a carryout bit_
These counters are cleared to their zero count by a
logical "1" on their reset line_ These counters are advanced on the positive edge of the clock signal when the
clock enable signal is in the logical "0" state_
.The configuration of the CD4017BM/CD4017BC and
CD4022BM/CD4022BC permits medium speed operation
and assures a, hazard free 'counting sequence. The 10/8
decoded outputs are normally in the logical "0" state
and go to the logical "1" state only at their respective
time slot. Each decoded output remains high for 1 full
clock cycle. The carry·out signal completes a full cycle
for every 10/8 clock input cycles and is used as a ripple
carry signal to any succeeding stages.
•
Medium speed operation
•
•
Low power
Fully static operation
3.0Vto 15V
0.45 VDD (typ.)
fan out of2
driving 74L
or 1 driving
74LS
5.0 MHz (typ.)
with 10V VDD
l~W(typ.)
Applications
• Automotive
• Instrumentation
• Medical electronics
• Alarm systems
• Industrial electronics
• Remote metering
Connection Diagrams
DECODED OUTPUT "5"
DECOOED OUTPUT "I"
DECODED OUTPUT "0"
DECODED OUTPUT "2"
DECODED OUTPUT
CD4022B
Dual-In-Line Package
..!.
..!.
..l
..!
U
.~ •• ' ~
~UTPUT "3"
..!.
.2.
VSS
...!.
DECODED OUTPUT "7"
OECODED
CD4017B
Dual·ln·Lina Package
.!!.
.!!.
.!!.
.!.!.
.!!.
.!!.
.!.!!.
.!...
liDO
DECODED OUTPUT "I"
RESET
DECODED DUTPUT "0"
..!.
..!.
..l
CLOCK
DECODED DUTPUT "2"
CLOCK ENABLE
'4
OECODED DUTPUT"5" ...;;.
CARRY-OUT
DECODED DUTPUT "8"
DECODED OUTPUT "9"
NC
DECODED OUTPUT "4"
DECODED OUTPUT ''3''
..!.
..!.
.2.
OECODED OUTPUT "8"
Vss
...!.
U
.!!.
.!.!.
.!!.
VDD
RESET
CLOCK
CLOCK ENABLE
CARRY·OUT
~
DECODED OUTPUT "4"
~
DECODED OUTPUT •..,"
~
NC
TLIF/5950-2
TlIFI5950-1
TOP VIEW
Order Number CD4017BMJ, CD4017BCJ, CD4022BMJ
or CD4022BCJ
See NS Package J16A
.!!.
.!!.
TOP VIEW
Order Number CD4017BMN, CD4017BCN, CD4022BMN
or CD4022BCN
See NS Package N16E
5-55
Absolute Maximum Ratings
Recommended Operating Conditions
(Notes 1 and 2)
(Note 2)
voo dc Supplv Voltage
-0.5 to +18 VOC
VIN Input Voltage
-0.5 to VOO +0.5 VOC
TS Storage Temperature Range
--£5°C to +150°C
Po Package Dissipation
500mW
TL Lead Temperature (Soldering, 10 seconds)
260°C
VOO'dc SupplV Voltage
VIN Input Voltage
. T A Operating Temperature Range
C04017BM, C04022BM
C04017BC, C04022BC
./
+3 to+15 VOC
OtoVOO VOC
-55°C to +125°C
--40~C to +85°C
,
DC Electrical Characteristics CD4017BM, CD4022BM (Note 2)
SYM
-5SoC
PARAMETER
MIN
100
VOL
Quiescent Oevice Current
Low Level Output Voltage
High Level Output Voltage
(Note 3)
p.A
p.A
0.05
V
0.05
V
VOO = 15V.
0.05
0
0.05
0.05
V
IIOI<1.0p.A
= 5V
= 15V
4.95
4.95
5
4.95
V
9.95
9.95
14.95
10
15
9.95
14.95
V
14.95
V
IIOI<1.0I'A
= 15V. Vo = 1.5Vor 13.5V
1.5
1.5
1.5
V
3.0
3.0
3.0
V
4.0
4.0
4.0
V
IIOI<1.0p.A
= 5V. Vo =0.5V or 4.5V
= 10V. Vo = 1.0V or 9.0V
Vee = 15V. Vo = 1.5V or 13.5V
VOO = 5V. Vo = OAV
3.5
7.0
11.0
11.0
0.64
VOO = 10V. Vo = 0.5V
High Level Output Current
= 15V. Vo = 1.5V
VOO = 5V. Vo =4.6V
(Note 3)
VOO = 10V. Vo = 9.5V
Input Current
20
0.05
VOO = 15V. Vo = 13.5V
liN
p.A
300
600
'0.05
VOO
IOH
150
10
0
VOO
VOO
Low Level Output Current
5
0.5
1.0
.0
VOO
IOL
0.3
0.05
VOO = 5V. Vo = 0.5V or 4.5V
VOO = 10V. Vo = 1.0V or 9.0V
High Level Input Voltage
5
10
20
MIN
UNITS
MAX
. 0.05
VOO
VIH
MAX
TYP
VOO = 10V
VOO= 10V
Low Leve( Input Voltage
MIN
1I01<1.0p.A
VOO
VIL
MAX
VOO = 5V, VIN = VOO or VSS
VOO = 10V. VIN = VOO or VSS
VOO = 15V. VIN = VOD or VSS
VOO = 5V
VOH
• 12SoC
2Soc
CONDITIONS
VOO = 15V. VIN
VOO = 15V. VIN
'.
3.5
V
7.0
V
0.51.
0.88
0.36
1.6
4.2
1.3
3.4
2.25
8.8
0.9
rnA
rnA
2.4
rnA
-0.25
-0.2
-0.5
-0.36
-0.14
rnA
-0.9
-3.5
-0.35
rnA
rnA
3.5
7.0
-0.62
-1.8
=OV
= 15V
-1.5
11.0
-10-5
10-;-5'
-0.1
0.1
V
,
-1.1
-0.1
0.1
-1.0
p.A
1.0
I'A
DC Electrical Characteristics CD4017BC, CD4022BC (Note 2)
SYM
100
PARAMETER
Quiesce,nt Device· Current
CONOITIONS
VOO = 5V
VOO = 10V
VOO
VOL
Low Level Output Voltage
-40°C
MIN
= 15V
VOO =.15V
Hig~
Level Output Voltage
MIN
TYP
MAX
MIN
MAX
UNITS
20
0.5
I'A
1.0
20
40
150
40
300
I'A
80.
5.0
80
600
I'A
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
V
V
0.05
0.05
V
IIOI<1.0I'A
VOO= 5V
VOO = 10V
VOH
a5"c
25°C
MAX
IIOI<1.0I'A
VOO= 5V
4.95
4.95
VOO = 10V
9.95
9.95
5
10
14.95
14.95
15
VOO = 15V
,
5·56
-
4.95
V
9.95
14.95
V
V
DC Electrical Characteristics (Cont'd.) CD4017BC, CD4022BC (Note 2)
-4o'c
CONDITIONS
PARAMETER
SYM'
MIN
MAX
85°C.
2S'C
MIN
MAX
TYP
MIN
UNITS
MAX
(
VIL
VIH
IOL
IOH
low Level Input Voltage
lIol<1.0pA
High Level Input Voltage
1.5
1.5
1.5
V
VDO = 10V. Vo = 1.0V or 9.0V
VDO = 15V, Va = 1.5V or 13.5V
3.0
3.0
4.0
3.0
V
4.0
V
4.0
IIOI<1.0/iA
VOO = 5V, Va = 0.5V or 4.5V
3.5
3.5
3.5
VDO = 10V, Vo = 1.0V or 9.0V
7.0
7.0
7.0 •
V
VOO = 15V, Va = 1.5V or 13.5V
11.0
11.0
11.0
V
Low Level Output Current
VOO = 5V, Va = OAV
0.S2
(Note 31
VOO = 10V, Va = 0.5V
1.3
0.44
1.1
0.36
0.9
mA
mA
.'
High Level Output Current
(Note 31
liN
VDO = SV, Va = O.SV or 4.SV
Input Current
0.88
2.25
V
VOO = lSV, Va = 1.5V
3.6
3.0
8.8
2.4
mA
VOD = 5V, Va = 4.6V
VOO = 10V, Va = 9.5V
-{l.2
-{l.16
-{l.12
mA
-{l.5
-{lA
-{l.36
-{l.9
-{l.3
mA
VOO = 15V, Va = 13.5V
-1.4
-1.2
-3.5
-1.0
-10 5
10-5
-{l.3
VOO = 15V, VIN = OV
VOO = 15V, VIN = 15V
0.3
mA
-{l.3
-1.0
0.3
1.0
pA
pA
to
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed, they are not meant
imply
that the devices should be operated at these limits. The table of "Recommended Operating Conditions" and "Electrical Characteristics" provides
conditions for actual device operation.
Note 2: VSS = OV unless otherwise specified.
Note 3: IOL and IOH are tested one output at a time.
AC Electrical Characteristics TA=25'C, CL=50pF, RL=200k, t,CL and tfCL=20ns,
unless otherwise
specified
PARAMETER
SYM
CONDITIONS
MIN
TYP
MAX
UNITS
CLOCKED OPERATION
'PHL, 'PLH
Propagation Delay Time:
Carry Out line
Carry Out Line
Oecode Out Lines
lTLH, tTHL
VOO = 5V
415
800
ns
VOO = 10V
160
320
VOO = 15V
'130
250
ns'
ns
VOO = 5V }
VOO = 10V CL = 15 pF
240
480
ns
85
170
ns
VOO= 15V
70
140
ns
VOO =5V
500
1000
ns
VOO = 10V
200
400
ns
VOO = 15V
160
320
ns
VOO =5V
200
360
VOO = 10V
100
180
ns
ns
VOO = 15V
80
130
ns
VOO = 5V
100
200
ns
50
100
ns
40
80
Transition Time Carry Out
and Oecode Out Lines
tTLH
'THL
VOO = 10V
VOO = 15V
l
ns
fCL
Maximum Clock Frequency
VOO = 5V
Measured with
VOO = 10V. Respect to Carry
VOO = 15V Output Line
tWL,tWH
Minimum Clock Pulse
VOO = 5V
125
250
ns
Width
VOO= 10V
45
90
ns
VOO = 15V
35
70
ns
20
15
/is
/is
ps
'rCL, tfCL
Clock Rise and Fall Time
1.0
2.5
3.0
VOO= 5V
VOO= 10V
VOO = 15V
tsu
CIN
MHz
MHz
2
5
6
MHz
5
Minimum Clock Inhibit
VOO = 5V
120
240
ns
Oata Set·Up Time
VOO = 10V
40
80
ns
VOO = 15V
32
65
ns
5
7.5
pF
Average I nput Capacitance
5-57
AC Electrical Characteristics (Cont'd.)
TA = 25°C. CL = 50 pF. RL = 200k;trCL and tfCL'= 20 ns. unless otherwise specified.
SYMBOL
UNITS
TVP
MAX
VOO = 5V
415
800
n,
VOD= 10V
160
320
VOO = 15V
130
250
n,
n,
240
85
70
480
170
CONDITIONS
PARAMETER
MIN
RESET OPERATION
tpHL
Propagation Delay Time:
Carry Out Line
Carry Out Line
VOO = 5V
VOO = 10V
J CL = 15 pF
VOO = 15V
tWH
tREM
500
VOO = 5V
VOO= 10V
Decode Out Lines
'140
1000
400
VOO = 15V
200
160
Minimum Reset Pulse
VOO = 5V
200
400
Width
VOO= 10V
70
140
VOO = 15V
55
110
Minimum Reset Removal
VOO = 5V
75
150
Time
VOO= 10V
30
60
VOO = 15V
25
50
Timing Diagrams
320
CD4017B
CLOCK
RESET
.
,
CLOCK
ENABLE
''0''
." .
,
"2"
n
..,.
"'--
n
~
,
r--7L
r
~
,~
"4"
n
"5"
n
''S''
"7"
n
''S''
''9''
CARRY·
n
n
I
\
OUT
TLIF/S95Q.3
CD4022B
CLOCK
\
RESET ,
,
CLOCK
ENABLE
n
..•.. ~
. ," --1"71
r--\
~
n
'"2 •• ~
''3''
...
",.
"
."
n
I
n
..
''}'.
CARRY·
OUT
r;-
,
,\
n
n
n
n.
,
n
I
5·58
n.
n.
f"7LI TLIFI5950-4
n,
n,
n,
n,
n,
n,
n,
n,
n,
n,
n,
n,
0
c
Logic Diagrams
0l:Io
0
....
m
"""
3:
CD4017B
"7"
"I"
,-
"3"
0
C
0l:Io
0
....
m
"""
CLOCK
S>
COUT
C
1
0
C
C
1
1
0
C
1
0
C
1
0
C
0l:Io
0
N
N
m
3:
0
C
0l:Io
0
N
N
TERMINAL NO. a '" GNU
TERMINAL NO. 16 = Vou
TL.IF/595()'S
"0"
"z..
""
",.
"4"
TERMINAL NO. 16 '" Vou
TERMINAL NO. B" GNU
"4"
"'"
5-59
''G''
""
COUT
TlIF/5950-6
m
0
()
ra
c:o
....
~National
ra
CD4018BM/CD4018BC Presettable Divide-by-N Counter
~
i
....c:o
i
c
()
~ Semiconductor
General Description
Features
The CD4018B consists of 5 Johnson counter stages. A
bufferedQ output from each stage, "CLOCK", "RESET",
"DATA", "PRESET ENABLE", and 5 individual "JAM"
inputs are provided. The counter is advanced one count
at the positive clock signal transition. A high "RESET"
signal clears the counte'rs to an "ALL ZERO" condition,
A high "PRESET ENABLE" signal allows Information on
the "JAM" inputs to preset the counter. Anti·lock gating
is provided to assure the proper counting sequence.
• Wide supply voltage range
• High noise im'm,unity
• Low power TTL
compatibilit~
3.0Vto 15V
0.45 Voo (typ.)
fan out of 2 driving 74L
or 1 driving 74LS
• Fully static opera!ion
Applications
• Fixed and programmable divide-by-10, 9, 8, 7, 6, 5, 4,
3,2 counter
• Fixed and programmable counters greater than 10
• Programmable decade counters
• Divide by "N" counters/frequency synthesizers
Logic Diagram
JAM I
JAM'
JAM]
Tl/F/5951·'
Connection Diagram
Dual-In-Line Package
PRESET
ENABLE
JAM
VOD
I"
RESET
CLOCK
"
"
lis
04
5
12
"
11
10
JAM
4
,
Order Number CD4018BMJ or CD4018BCJ
See NS Package J16A
-
I
DATA
Order Number CD4018BMN or CD4018BCN
See NS Package N16E
,
JAM
I
,
JAM
,
•
i1z
.,
-
TOP VIEW
5
•
Ii,
1
I'
TLiF/5951·2
5-60
n
Recommended Operating Conditions c
Absolute Maximum Ratings (Note 1)
~
....
(Notes 1 and 2)
(Note 2)
VOO de Supply Voltage
~.S to +18 VOC
VIN Input Voltage
~.S to VOO + O.S VOC
TS Storage Temperature Range
-1lSoC to +lS0°C
Po Package Dissipation
I
SOOmW'
T L Lead Temperature (Soldering, 10 seconds)
260°C
VOO dc Supply Voltage
VIN Input Voltage
T A 9perating Temperature Range
C04018BM
C04018BC
DC Electrical Characteristics
SYM
100
VOL
VOl-!
VIL
PARAMETER
Quiescent Device Current
Low Level Output Voltage
High Level Output Voltage
Low Level Input Voltage
laL
IOH
liN
High Level Input Voltage
CD4018BM (Note 2)
MIN
25°C
MAX
0.3
0.5
lS0
300
fJ.A
VOO = 10V, VIN = VOO or VSS
5
10
VOO = 15V, VIN = VOO or VSS
20
1.0
20
600
fJ.A
MAX
MIN
VOL
VOH
VIL
VIH
MIN
MAX
fJ.A
IIOI=
AMBIENT TEMPERATURE
TA
300
> ZSD
~
§ 200
~
150
r.:======--;--:r-,
AMBIENTTEMPERATURE
~
25"C "I 1
,.
"
I L"t'
f--t;;-i--"lD :15VH-+-+--I
f--+-+-+-++-+-+-I--jH
TA :
i _~~OV~.-l""'I"-~--+-1
100
~ 5°~~~~llo~otl:l~i~-~'
%
20
40
60
BO
CL ... LOAD CAPACITANCE I,F}
External Connections for Divide by
10,9,8,7,6,5,4,3,2, Operation
05]
~~
10
B
6
4
2
Divide BV 9
02
01
~
0 " L....L..I-.l-..J...-I......l..-L-..!._L...J
40
60
BO
100
0
20
CL ... LOAD CAPACITANCE I,F}
TlIFI59S1-3
CLOCK
RESET
~~~~~~~~~~~~~lL~UL~~L~L~
f--1\4-+-+-++-I--+-+-+-I-++-II-++-H-+-+-+-+-+
PRESET
Connected" Back
To "DATA"'nput
JAM 1
JAM 2
~4:::[)- CONNECTED TO "DATA" INPUT
n.
JAMJ
III
,
DDNT CARE UNTil PRESET GOES HIGH
TLIFI5951·5
.,
I-f-
.2
I-f--
f-
JAMS
~:::[)-CONNECTED TO "OATA"INPUT
n.
1/4MMS4C08lMM14COB
TLlF/5951·6
Divide By 5
-f-
JAM4
1/4MMS4COB/MM14coa
Divide BV 7
TLIFI595H
Timing Diagram
External Connections
Divide BV
Divide BV
Divide BV
Divide BV
Divide BV
100
::::[)-CONNECTEDTD"DATA"INPUT
-f-
14-l-f-+
I'-+-t-f-+
1'--
H-+-+-+-I
a,
~-+-H--f
t....
,_+_
J
••
a.
1/4MM54COa/MM14Coa
TLIF/5951-7
TUF/5951·9
Note. "Data" input tied to OS for decade counter configuration.
I
Divide By 3
::::[)-CONNECTEO TO "DATA"INPUT
1I4MM54CQI/MM74CDB
TUFt5951·B
5-63
o
~National
~ ~ Semiconductor
;
o
~CD CD4019BM/CD4019BC Quad AND-OR Select Gate
,....
~
General Description
Features
()
The CD4019BM/CD4019BC is a complementary MOS
quad AND-OR select gate_ Low power and high noise
margin over a wide voltage range is possible through
implementation of Nand P-channel enhancement mode
transistors_ These complementary MOS (CMOS) transistors provide the building blocks for the 4 "AND-OR
select" gate configurations, each consisting of two
2-input AND gates driving a single 2-input OR gate_
Selection is accomplished by control bits KA and KBAll inputs are protected against static discharge damage_
• Wide supply voltage range
• High noise immunity
• Low power TTL
compatibility
c
3V to 15V
0_45 VDD (typ_)
fan out of 2
driving 74L
or 1 driving 74LS
Applications
•
•
•
•
AND-OR select gating
Shift-right/shift-Ieft registers
True/complement selection
AND/OR/EXCLUSIVE-OR seleqtion
Connection Diagram
Dual-In-Line Package
Voo
A4
K,
04
03
02.
01
KA
Order Number CD4019BMJ or CD4019BCJ
See NS Package J16A
. Order Number CD4019BMN or CD4019BCN
See NS Package N16E
TOP VIEW
TUFI5952·1
Schematic Diagram
VDD
K,o----If-+-+-+-..
Schematic diagram for 1 of 4 identical stages
5-64
TLIFf5952·2
Absolute Maximum Ratings
Recommended Operating Conditions
o
~
...
o
(Notes 1 and 2)
(Note 2)
voo Supply Voltage
-0.5 to +18V
VIN Input Voltage
-0.5 to VOO + O.5V
TS Storage Temperature Range
-65°C to +150°C
Po Package Dissipation
500mW
TL Lead Temperature (Soldering, 10 seconds)
260°C
VOO Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
C04019BM
C04019BC
CD
3to 15V
OtoVOOV
-55°C to +125°C
-40°C to +8SO C
tv
s:
(;
C
...
01:00
o
CD
tv
o
DC Electrical Characteristics CD4019BM (Note 2)
SYM
100
VOL
VOH
VIL
VIH
-55°C
PARAMETER
Quiescent Device Current
Low Level Output Voltage
High Level Output Voltage
Low Level Input Voltage
High Level Input Voltage
CONDITIONS
MIN
125°C
MAX
MIN
MAX
UNITS
0.25
0.03
0.25
7.5
0.5
0.05
0.5
15
I'A
VOO = 15V
1.0
0.07
1.0
30
I'A
Vao = 5V
0.05
0
0.05
0.05
V
Vao= 10V
0.05
0
0.05
0.05
Vao = 15V
0.05
0
0.05
0.05
V
V
I'A
1101< 11'A
1101< 1 I'A
Vao = 5V
4.95
4.95
5
4.95
Vao = 10V
9.95
9.95
10
9.95
V
VOO = 15V
14.95
14.95
15
14.95
V
V
Vao = 5V, Vo = 0.5V or 4.5V
1.5
2
1.5
1.5
V
VOO= 10V, VO= lVor9V
3.0
4
3.0
3.0
V
VOO = 15V, Vo = 1.5V or 13.5V
4.0
6
4.0
4.0
V
VOO = 5V,
Vo = 0.5V or 4.5V
Vo = O.4V
3.5
V
7.0
V
3.5
3.5
7.0
7.0
3
6
11.0
11.0
9
11.0
V
0.64
0.51
1
0.36
mA
Low Level Output Current
VOO = 5V,
(Note 3)
Voa = 10V, Vo = 0.5V
1.6
1.3
2.5
0.9
mA
Voa = 15V, Vo = 1.5V
4.2
3.4
10
2.4
mA
High Level Output Current
Voa = 5V,
(Note 3)
VOO
= 10V,
= 4.6V
-0.25
-0.2
-0.4
-0.14
mA
Vo = 9.5V
-0.62
-1.8
-0.5
-1.5
-1.0
-0.35
-1.1
mA'
Vo
= 13.5V
VIN = OV
VOO = 15V, Vo
liN
TYP
VOO = 10V
VOO'= 15V, Vo = 1.5V or 13.5V
10H
25°C
MIN
VOO = 5V
VOO = 10V, Vo = lVor 9V
10L
MAX
Input Current
= 15V,
Voa = 15V,
VOO
-0.10
0.10
VIN = 15V
5·65
-3.0
-10 5
10-5
mA
-0.10
-1.0
I'A
0.10
1.0
I'A
DC Electrical Characteristics CD4019BC (Note 2)
SYM
Quiescent Device Current
100
Low Level Output Voltage
VOL
High Level Output Voltage
VOH
2SOC
-40°C
CONDITIONS
PARAMETER
MIN
VOO = SV
VOO = 10V
VOO = 15V
MAX
1
2
4
IIOI...
Order Number CD4020BMN, CD4020BCN, CD4040BMN,
CD4040BCN, CD4060BMN or CD4060BCN
See NS Package N16E
Vss
7
D12
Q13
Q14
D&
Qs
Q7
11.4
.1 8
VSS
TUFI5953-1
CD4040BM/CD4040BC
T
1&
Ql1
15
QIO
14
lis
13
D9
12
RESET
11
CD4060BM/CD4060BC
91
lis
Dl
14
9
10
D9
13
RESET
12
¢Ii
91
11
90
10
VDD
VDD
)-
-
)~
I-
Vss
Vss
&
D12
D6
D5
D7
11.4
D3
P .IVssB
7
D2
D12
D13
D14
DS
D5
D7
11.4
.I B
Vss
TL.IFI5953-3
TUF/59S3-2
5-67
i
m
o
•
Recommend~d
Absolute Maximum Ratings
Operating Conditions
(Notes 1 and 2)
-0.5Vto+18V
Voo Supply Voltage
V ,N Input Voltage
-0.5V to Voo + 0.5V
_65°C to +150°C
Storage Temperature Range
Ts
Package Dissipation
500mW
Po
Lead Temperature (soldering. 10 seconds)
260°C
TL
DC Electrical Characteristics
SYM
100
Voc
Low Level Output Voltage
+3V to +15V
V ,N - I nput Voltage
OV to Voo
Operating Temperature Range.
CD40XXBM
CD40XXBC
TA
-55°C to +125°C
_40°C to +85°C
CD40XXBM (Note 2)
_55°C
CONDITIONS
PARAMETER
Quiescent Device Current
Voo Supply Voltage
MIN
MAX
VoO = 5V, VIN = VOO or Vss
Voo = 10V, VIN = Voo or VSS
VOo = l5V, VIN = VOo or VSS
5
Voo = 5V
Voo = 10V
Voo = 15V
0.05
0.05
0.05
High Level Output Voltage
V'c
Low Level Input Voltage
.Voo=5V, Va = 0.5V or 4.5V
Voo = 10V, Va = 1.0V or 9.0V
Voo =.15V, Vo = 1.5V or 13.5V
V ,H
High Level Input Voltage
loc
Low Level Output Current
(See Note 31
Voo = 5V, Vo = 0.5V or 4.5V
Voo = 10V, Va = 1.0V or 9.0V
Voo = 15V, Va = 1.5V or 13.5V
Voo = 5V, Va=O.4V
Voo = 10V, Vo = 0.5V
Voo = 15V, Va = 1.5V
10H
High Level Output Current
(See Note 3)
Voo = 5V, Va = 4.6V
Voo = 10V, Va = 9.5V
Voo = 15V, Va = 13.5V
liN
Input Current
Voo = 15V, V ,N = OV
Voo = 15V, V ,N = 15V
Voo = 5V
Voo = 10V
Voo=15V
TYP
10
20
4.95
9.95
14.95
V OH
+25°C
MIN
0
0
0
+125°C
MAX
2
4
6
MAX
UNITS
5
10
20
150
300
600
'I1 A
I1A
I1A
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
4.95
9.95
14.95
4.95 5
9.95 10
14.95 15
1.5
3.0
4.0
MIN
1.5
'3.0
4.0
V
V
V
1.5
3.0
4.0
V
V
V
3.5
7.0
11.0
3.5
7.0
11.0
3
6
9
3.5
7.0
11.0
V
V
V
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mA
mA
mA
-0.51 -0.88
-1.3 -2.25
-3.4 -8.8
-0.36
-0.9
-2.4
mA
mA
mA
-0.64
-1.6
-4.2
-0.10
0.10
10- 5 -0.10
10- 5
0.10
1.0
1.0
I1A
pA
Note 1: "Absolute Maximur,n Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to
imply that the devices should be operated at these limits. The tables of "Recommended Operating Conditions" and "Electrical Characteristics"
provide conditions for actual device operation.
Note 2: VSS = OV unless otherwise specified.
Note 3: Data does not apply to oscillator points <1>0 and To of Co4060BM/Co4060BC. IOH and IOL are tested one output at a time.
,
5·68
DC Electrical Characteristics
40XXBC (Note 2)
+2SoC
,_40°C
Quiescent Device Current
lee
Low Level Output Voltage
VOL
CONDITIONS
PARAMETER
SYMBOL
V OH
High Level Output Voltage
V ,L
Low Level Input Voltage
20
40
80
~
5V
10V
15V
0.05
0.05
0.05
~
5V
~
Vee
Vee
Vee
~
Vee
Vee
Vee
MAX
5V, VIN ~ VDD or VSS
lOV, VIN =VDD or VSS
15V, VIN =VOO or VSS
VDD
VDD
VDO
Vee
Vee
Vee
MIN
~
~
~
4.95
9.95
14.95
= 10V
= 15V
~
~
~
5V, Vo
10V, Vo
15V, Vo
MIN
TVP
+8SoC
MAX
0
0
0
1.5
3.0
4.0
0.5V or 4.5V
1.0V or 9.0V
= 1.5V or 13.5V
~
MAX
UNITS
20
40
80
150
300
600
pA
pA
pA
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
4.95
9.95
14.95
4.95 5
9.95 10
14.95 15
~
MIN
2
4
6
V
V
V
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
V ,H
High 'Level Input Voltage
Vee = 5V, Vo = 0.5V or 4.5V
Vee = 10V, Vo = 1.0V or 9.0V
Vee = l5V, Vo = 1.5V or 13.5V
3.5
7.0
11.0
3.5
7.0
11.0
3
6
9
3.5
7.0
11.0
V
V
.V
10L
Low Level Output Current
.ISee Note 3)
Vee = 5V, Vo=O.4V
Vee = 10V, Vo = 0.5V
Vee = 15V, Ve = 1.5V
0.52
1.3
3.6
0.44
1.1
3.0
0.88
2.25
8.8
0.36
0.9
2.4
mA
mA
mA
10H
High Level Output Current
(See Note 3)
Vee = 5V, Vo = 4.6V
Vee = 10V, Vo = 9.5V
Vee = 15V, Vo = 13.5V
-0.52
-1.3
3.0
-0.44 -0.88
2.25
3.0
8.8
-0.36
-0.9
-2.4
mA
mA
mA
I nput Current
Vee = 15V, V,N = OV
Vee = 15V, Y'N = 15V
liN
AC Electrical Characteristics
-1.1
10. 5 -0.30
-0.30
0.30
10. 5
0.30
-1.0
1.0
pA
pA
CD4020BM/CD4020BC, CD4040BM/CD4040BC
T A = 25°C, CL = 50pF, R L = 200k, tr = tf = 20ns, unless otherwise noted.
SYMBOL
tpHL11 tpLH1
tpHLI t pLH
PARAMETER
TVP
MAX
Propagation Delay Time to a,
Veo = 5V
Voo = 10V
Voo = 15V
250
100
75
550
210
150
ns
ns
ns
Interstage Propagation Delay Time
Voo = 5V
Voo = 10V
Voo = 15V
150
60
45
330
125
90
ns
ns
ns
from an to On+'
CONDITIONS
MIN
UNITS
t THL, tTLH
Transition Time
Voo = 5V
Voo = 10V
Voo = 15V
100
50
40
200
100
80
ns
ns
ns
tWL, tWH
Minimum Clock Pulse Width
Voo = 5V
Voo = 10V
Voo = 15V
125
50
40
335
125
100
ns
ns
ns
t reL , t lCL
Maximum Clock Rise and Fall Time
Voo = 5V
Voo = 10V
Voo = 15V
no limit
no limit
no limit
ns
ns
ns
fCL
Maximum Clock Frequency
Voo= 5V
Voo=10V
Voo = 15V
tpHLIR)
Reset Propagation Delay
Voo = 5V
Voo = 10V
Voo=15V
200
100
80
450
210
170
ns
ns
ns
tWHIR)
Minimum Reset Pulse Width
Voo = 5V
Voo = 10V
Voo = 15V
200
100
80
450
210
170
ns
ns
ns
C'n
Average Input Capacitance
Any Input
5
7.5
pF
Cpd
Power Dissipation Capacitance
1.5
4
5
4
10
12
50
5·69
MHz
MHz
MHz
pF
AC Electrical Characteristics CD4060BM/CD4060BC TA = 25°C, Ci.=50pF, RL=200k, t,=t,=20ns,
unless otherwise noted
TYP
MAX
Vee= 5V
Vee= 10V
Vee= 15V
550
250
200
1300
525
400
ns
ns
ns
CONDITIONS
PARAMETER
SYMBOL
tpH L4, tpLH4
Propagation Delay Time to 0 4
MIN
UNITS
t pHL, tPLH
I nterstage Propagation Delay Time
from On to On+1
Vee = 5V
Vee = 10V
Vee = 15V
150
60
45
330
125
90
ns
ns
ns
tTHL, tTLH
Transition Time
Vee = 5V
Vee = 10V
Vee = 15V
100
50
40
200
100
80
ns
ns
ns
t WL, tWH
Minimum Clock Pulse Width
Veo = 5V
VbO = 10V
Voo= 15V
170
65
50
500
170
125
ns
ns
ns
.trCL' tfCL
Maximum Clock Rise and FaU Time
Voo = 5V
Voo = 10V
Veo= 15V
no limit
no limit
no limit
ns
ns
ns
fCL
Maximum Clock Frequency
Veo=5V
Voe= 10V
Voe = 15V
tPHL(RI
Reset Propagation Delay
Vee= 5V
Vee= 10V
Vee = 15V
200
100
80
450
210
170
ns
ns
ns
tWH(RI
Minimum Reset Pulse Width
Voo= 5V
Vee= 10V
Vee= 15V
200
100
80
450
210
170
ns
ns
ns
Cln
Average I nput Capacitance .
Any Input
5
7.5
pF
Cpd
Power Dissipation Capacitance
1
3
4
MHz
MHz
MHz
3
8
10
pF
50
CD4060B Typical Oscillator Connections
RC Oscillator
12
HESET-.
~
11
......
......
.....
10
H2
Crystal Oscillator
Y
12
REm_
TO COUNTER
STAGES
~
...
15M2
11
9
R1
It-
32.718kHz
10pF
TUF/595304
...........
~~
10
I'"" TO COUNTER
,C\
R
330k
~D~ ~39pf
':"
.;
TUFI5953-6
5·70
STAGES
~------------------------------------------~o
Schematic Diagrams
c
~
CD4020BM/CD4020BC Schematic Diagram
¢.
1:0
s:
(;
c
~
1:0
o
'h
c
~
1:0
s:
(;
c
TUF/5953·6
CD4040BM/CD4040BC Schematic Diagram
~
1:0
.P
o
c
8
~
1:0
s:
(;
c
[!]
=
~
~
VSS
1:0
o
TLiF/595J.7
CD4060BM/CD4060BC Schematic Diagram
[!]
= Vss
G
-Voo
,.
TUF/5953·8
5·71
~National
~ Semiconductor
.,.. CD4021BM/CD4021BC a·Stage Static Shift Register
i
o
o
,General Description
The CD4021BM/CD4021BC is an a-stage parallel input/
serial output shift register_ A parallel/serial control input
enables individual JAM inputs to each of a stages_ Q
output are available from the sixth, seventh, and eighth
stages_ All outputs have equal source and sink current
capabilities and conform to standard "B" series output
drive_
'
All inputs are protected against static discharge with
diodes to Vee and Vss -
Features
• Wide supply voltage range: _3_0V to 15V
• High noise immunity: 0.45 Vee (typ,)
fan out of 2 driving
• Low power TTL compatibility
74L or 1 driving 74LS
When the parallel/serial control input is in the logical
"0" state,data is serially shifted into the register syn.chronously with the positive transition of the clock_ • 5V-10V-15V parametric ratings
When the parallel/serial control is in the logical "1" • Symmetrical output characteristics
state, data is jammed into each stage of the register, • Maximum input leakage 1/J.A at 15Vover full temperaasynchronously with the clock.
ture range
Connection Diagram
Truth Table
Dual-In-Line Package
'7
L6
OUT
5'
15
PARI
SER
CO NT
BUF
PAR IN
VOO
13
14
SER
IN
07
12
CLK
11
CL·
9
10
X
X
X
X
I-
I
II', I,
I, I. I, I. I,
B
06
DB
P~R
~~~
~~~
,4
3
2
1,
~
X
X
X
X
0
~
1
-----
Paraileil
Serial
Control
X
Q1
(Internal)
P(1
Pin
0
0
0
1
0
0
0
1
1
1
0
1
0
1
Qn
1
1
1
1
1
1
0
0
0
X
X
X
X
X
X
0
Qn l
1
C nol
Ql
an
o
*'Level change
X:;;: Don't care case
I
I'
I
Order Number CD4021 BMJ or CD4021 BCJ
See NS Package J16A
VSS
PAR IN
TOP VIEW
Serial"
Input
Order Number CD4021 BMN or CD4021 BCN
See NS Package N16E
TUF15954-1
Logic Diagram
PARALLELISERIAL 9
CONTROL
[J
P(i
CL
PS
ii
PS ......- - - - - '
5-72
TLIF/5954·2
No
Change
o
Absolute Maximum Ratings (Notes 1 & 2)
Recommended Operating Conditions
(Note 2)
voo Supply Voltage
-0.5to +18V
- 0.5 to VOO + 0.5V
-65°Cto + 150°C
VIN Input Voltage
IS Storage Temperature Range
Po Package Dissipation
TL lead Temperature (Soldering, 10 seconds)
N
....
VOD Supply Voltage
3to15V
VIN Input Voltage
OtoVOO
TA Operating Temperature Range
C04021BM
C04021BC
500rnW
260'C
c
~
- 55°C to + 125°C
- 40°C to + 85°C
to
3:
(5
~....
N
to
DC Electrical Characteristics
SYM
Parameter
(Note 2) -
o
CD4021BM
-55'C
Conditions
100
Quiescent Device Current
Voo=5V. V,N=VOOorVss
Von = 10V, YIN::: Von or Vss
Vgg = 15V, Y,N = Voo or Vss
I
I
25'C
125'C
Units
Typ
Max
5
10
20
0.1
0.2
0.3
5
10
20
150
300
600
~A
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
Max
Min
Min
Min
Max
~A
~.
VOL
low level Output Voltage
VOH
High level Output Voltage
V,L
low level Input Voltage
Voo =5V, Vo =0.5V or 4.5V
Voo= 10V, Vo= 1.0V or 9.0V
Voo= 15V, Vo= 1.5V or 13.5V
V,H
High level Input Voltage
V oo =5V, V o =0.5Vor4.5V
Voo =10V, Vo =I.0Vor9.0V
V oo =15V, Vo =I.5Vor 13.5V
3.5
7.0
11.0
3.5
7.0
11.0
3
6
9
3.5
7.0
11.0
V
V
V
Low Level Output Current
Voo =5V, Vo=0.4V
Voo =10V, Vo=0.5V
V oo =15V, Vo=I.5V
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.2
8
0.36
0.90
2.4
rnA
rnA
rnA
-0.64
-1.6
-4.2
-0.51
-1.3
-3.4
-0.88
-2.2
-8
_10- 5
10- 5
-0.36
-0.90
-2.4
rnA
rnA
rnA
10L
(Note 3)
Voo=5V
Voo=10V Ilol
-10
I
oS
10
V11
!
TLlFI5954·5
0.---------------------------------------------------------------,
~ ~National
~ ~ Semiconductor
i
~
i
c CD4023M/CD4023C Triple 3-lnput NAND Gate
o~ CD4025M/CD4025C Triple 3-lnput NOR Gate
~
g General Description
Features
o
These triple gates are monolithic complementary. MaS • Wide supply voltage range
3.0Vto15V
(CMOS) integrated circuits constructed with N- and
0.45 Voo (typ.)
• High noise immunity
CW)
P-channel enhancement mode transistors. All inputs
are protected against static discharge with diodes to • 5-10V parametric ratings
Voo and Vss.
• Low Power
C _________________________________________________________________
01
1
i
i
Connection Diagrams
Dual-In-Line Packages
CD4023M/CD4023C
CD4025M/CD4025C
Voo
Voo
II, I,~,I,
II, I, ~.I.
p
Vss
TOP VIEW
TOP VIEW
TUF/5955-1
TLIFI5955-2
Order Number CD4023MJ, CD4023CJ, CD4025MJ. or CD4025CJ
See NS Package J14A
Order Number CD4023MN, CD4023CN, CD4025MN or CD4025CN
See NS Package N14A
5-76
o
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
CD4023M, CD4025M
CD4023C, CD4025C
~
(Note 1)
Storage Temperature Range
-6S"C to +150"C
Package Dissipation
500mW
Operating Voo Range
Vss+ 3.0V to Vss +15V
Lead Temperature (Soldering, 10 seconds)
260°C
Vss- toVo o +0.3V
-55"C to +125"C
-55"C to +125"C
-40"C to +85"C
DC Electrical Characteristics
-
Co)
-o
3:
~
~
CD4023M, CD4025M
o
Limits
Sym
Parameter
Conditions
-55°C
Po
125°C
Typ
Max
0.05
0.1
0.001
0.001
0.05
0.1
3.0
6.0
,..A
,..A
Quiescent Device
Voo=5.0V
Dissipation/Package Voo= 10V
0.25
1.0
0.005
0.01
0.25
1.0
15
60
,..W
0.05
0.05
0
0
0.05
0.05
0.05
0.05
V
V
Quiescent Device
Current
VOL Output Voltage Low
Level
Voo=5.0V, VI =Voo, 10=OA
Voo = 10V, VI = Voo, 10 = OA
VO H Output Voltage High Voo=5.0V, VI=VSS , 10=OA
Level
Voo = 10V, VI =Vss, 10 =OA
Max
Min
Min
Max
4.95
9.95
4.95
9.95
5.0
10
4.95
9.95
V
V
Voo=5.0V, Vo =3.6V, 10=OA
Voo =10V, Vo=7.2V, 10=OA
1.5
3.0
1.5
3.0
2.25
4.5
1.4
2.9
V
V
VNH Noise Immunity
(All Inputs)
Voo=5.0V, Vo=0.95V, 10=OA
Voo =10V, Vo=2.9V, 10=OA
1.4
2.9
1.5
3.0
2.25
4.5
1.5
3.0
.v
IoN Output Drive Current Voo = 5.0 V, Vo = 0.4 V, VI = Voo
N·Channel (4025)
Voo = 10V, Vo = 0.5 V, VI = Voo
(Note 2)
0.5
1.1
0.40
0.9
1.0
2.5
0.28
0.65
mA
mA
loP Output Drive Current Voo = 5.0 V, Va = 2.5V, VI = Vss
P·Channel (4025)
Voo =10V, Vo =9.5V, VI=Vss
(Note 2)
-0.62
-0.62
-0.5
-0.5
-2.0
-1.0
-0.35
-0.35
mA
mA
IoN Output Drive Current Voo = 5.0 V, Va = 0.4 V, VI = Voo
N·Channel (4023)
Voo = 10V, Vo=0.5V, VI=Voo
(Note 2)
0.31
0.63
0.25
0.5
0·.5
0.6
0.175
0.35
mA
mA
loP Output Drive Current Voo = 5.0 V, Vo = 2.5 V, VI = Vss
P·Channel (4023)
Voo =10V, Va=9.5V, VI=Vss
(Note 2)
-0.31
-0.75
-0.25
-0.6
-0.5
-1.2
-0.175
-0.4
mA
mA
Input Current
10
.
5·77
c:n
3:
o
c
~
,..Iiv
VNL Noise immunity
(All Inputs)
II
~
Units
Voo=5.0V
Voo=10V
Min
IL
25°C
o
V
pA
I
•
DC Electrical Characteristics
-
CD4023C, CD4025C
Limits
Sym
Parameter
-40"C
Conditions
Min
Max
25"C
Min
Units
85°C
Typ
Max
Min
Max
IL
Quiescent Device
Current
Voo=5.0V
Voo=10V
0.5
5.0
0.005
0.005
0.5
5.0
15
30
,..A
,..A
Po
Quiescent Device
Voo=5.0V
Dissipation/Package Voo'=10V
2.5
50
0.025
0.05
2.5
50
75
300
,..W
,..W
0.01
0.Q1
0
0
0.01
0.Q1
0.05
0.05
.V
VOL Output Voltage Low
Level
Voo = 5.0V, VI =Voo , 0 =OA
Voo =10V, VI=VOO, lo=OA
VOH Output Voltage High Voo=5.0V, VI=VSS, lo";OA
Level
Voo=10V, VI=VSS, lo=OA
II
4.99
9.99
4.99
9.99
5.0
10
Input Current
4.95
9.95
10
V
V
V
pA
VNL Noise Immunity
(All Inputs)
Voo=5.0V, Vo=3.6V, lo=OA
Voo =·10V, Vo=7.2V, lo=OA
1.5
3.0
1.5
3.0
2.25
4.5
1.4
2.9
V
V
VNH Noise Immunity
(All Inputs)
Voo = 5.0 V, V.=0.95V, lo=OA
Voo =10V, Vo=2.9V, lo=OA
1.4
2.9
1.5
3.0
2.25
4.5
1.5
3.0
V
V
IoN Output Drive Current Voo = 5.0 V, Vo = 0.4 V, VI = Voo
N·Channel (4025)
Voo =10V, Vo=0.5V, VI=VO O
(Note 2)
0.35
0.72
0.3
0.6
1.0
2.5
0.24
0.48
mA
mA
loP Output Drive Current Voo = 5.0 V, Vo = 2.5 V, VI = Vss
P·Channel (4025)
Voo=10V, Vo=9.5V, VI=Vss
(Note 2)
-0.35
-0.3
-0.3
-0.25
-2.0
-1.0
-0.24
-0.2
mA
mA
IoN Output Drive Current Voo = 5.0 V, Vo = 0.4 V, VI = Voo
N·Channel (4023)
Voo=10V, Vo=0.5V, VI=VOO
(Note 2)
0.145
0.3
0.12
0.25
0.5
0.6
0.095
0.2
mA
mA
loP Output Drive Current Voo = 5.0 V, Vo = 2.5 V, VI = Vss
P·Channel (4023)
Voo = 10V, Vo = 9.5 V, VI = Vss
(Note 2)
-0.145
-0.35
-0.12
-0.3
-0.5
-1.2
-0.095
-0.24
mA
mA
II
Input Current
10
Note 1: "Absolute Maximum Ratings are those values beyond which the safety of the daviee C8nl10t
~ gua!'ant!~d.
pA
They are not meant to Imply th=.t the
devices should be operated at these limits. The tables of "Recommended Operating Conditions" and "Electrical Characteristics" provide conditions for
actual device operation.
Note 2: ION and lOP are tested one output at a time.
5·78
AC Electrical Characteristics TA '" 25·C, CL = 15 pF, and input rise and fall times = 20 ns.
Typical temperature coefficient for all values of Voo =0.3%I·C
Sym
I
Parameter
CD4025M
IConditions I
Min
I
Typ
I
Max
I
Units
tpHL Propagation Delay Time High to Low Level
Vo o =5.0V
Voo=10V
35
25
50
40
ns
ns
Propagation Delay Time Low to High Level
Voo= 5.0V
Voo=10V
35
25
40
70
ns
ns
Voo=5.0V
Voo=10V
Voo =5.0V
Voo=10V
65
35
65
35
125
70
175
75
Any Input
5.0
tpHL Propagation Delay Time High to Low Level
Voo=5.0V
Voo=10V
35
25
80
55
ns
ns
Propagation Delay Time Low to High Level
Voo= 5.0V
Voo=10V
35
25
120
65
ns
ns
tTHL Transition Time High to Low Level
Voo=5.0V
Voo=10V
65
35
200
115
ns
ns
tTLH Transition Time Low to High Level
Voo =5.0V
Voo=10V
65
35
300
125
ns
ns
C, '
Any Input
5.0
tpLH
tTHL Transition Time High to Low Level
tTLH Transition Time Low to High Level
Input Capacitance
C,
ns
' ns
ns
ns
pF
CD4025C
tpLH
Input Capacitance
pF
AC Electrical Characteristics TA =25·C, CL =15pF, and input rise and fall times=20ns.
Typical temperature coefficient for all values of Voo = 0.3%I·C
Sym
I
Parameter
CD4023M
IConditions I
Min
I
Typ
I
Max
I
Units
tpHL Propagation Delay Time High to. Low Level
Vo o =5.0V
Voo= 10V
50
25
75
. 40
ns
ns
tpLH Propagation Delay Time Low to High Level
Voo =5.0V
Voo=10V
50
25
75
40
ns
ns
tTHL Transition Time High to Low Level
Vo o =5.0V
Voo=10V
75
50
125
75
ns
ns
tTLH Transition Time Low to High Level
Voo=5.0V
Voo=10V
75
40
100
60
ns
ns
Any Input
5.0
tpHL Propagation Delay Time High to Low Level
Voo=5.0V
Voo=10V'
50
25
100
50
ns
ns
Propagation Delay Time Low to High Level
Voo=5.0V
Voo= 10V
50
25
100
50
ns
ns
tTHL Transition Time High to Low Level
Voo= 5.0V
Voo=10V
75
50
150
100
ns
ns
tTLH Transition Time Low to High Level
Voo= 5.0V
Voo=10V
75
40
125
75
ns
ns
Any Input
5.0
C,
Input Capacitance
pF
CD4023C
tpLH
C,
Input Capacitance
5·79
pF
~National
~ Semiconductor
($
a:I
CD4023BM/CD4023BC Buffered Triple 3-lnput
NAND Gate
CD4025BM/CD4025BC Buffered Triple 3-lnput
NOR Gate
ic
General Description
('I)
o
Features
These triple gates are monolithic complementar-y MaS
(CMOS) integrated circuits constructed with N- and
a:I P-channel enhancement mode transistors. They have
~ equal source and sink current capabilities and conform
o to standard B series output drive. The devices also have
oo:r buffered outputs which improve transfer characteristics
C
by providing very high gain. All inputs are protected
against static discharge with diodes to Voo and Vss.
• High noise immunity
• 5V-10V-15V parametric ratings
• Symmetrical output characteristics
• Maximum input leakage 11'A at 15 V over full temperature range
Dual·ln-Line Packages
CD4025BM/CD4025BC
CD4023BM/CD4023BC
'(
fan out of 2 driving 74L
or 1 driving 74LS
• Low power TTL
compatibility
o
Connection Diagrams
3.0Vto 15V
0.45 Voo (typ.)
• Wide supply voltage range
~
y
I
·1
Vss
Vss
TOP VIEW
TOP VIEW
Order Number CD4023BMJ, CD4023BCJ, CD4025BMJ
or CD4025BCJ
See NS Package J14A
Order Number CD4023BMN, CD4023BCN, CD4025BMN
or CD4025BCN
See NS Package N14A
5-80
Recommended Operating Conditions
Absolute Maximum Ratings (Notes 1 and 2)
voo
VIN
TS
Po
TL
+5 Voc to +15 Voc
Voo DC Supply Voltage
V IN Input Voltage
OVoc to Voo Voc
TA Operating Temperature Range
-55°C to +125°C
CD4023BM, CD4025BM
_40°C to +85°C
CD4023BC, CD4025BC
DC Supply Voltage
-0.5 VOC to +18 VOC
Input Voltage
-0.5 Voc to Voo + 0.5 Voc
_65°C to +150°C
Storage T emperatu re Range
Package Dissipation
500mW
Lead Temperature (soldering, 10 seconds) 260°C
DC Electrical Characteristics - CD4023BM, CD4025BM
SYM
CONDITIONS
PARAMETER
(Note 2)
_55°C
MIN
MAX
+25°C
MIN
+125°C
TYP
MAX
MIN
MAX
UNITS
Voo = 5 V
Voo= 10V
Voo= 15V
0.25
0.5
1.0
0.004
0.005
0.006
0.25
0.5
1.0
7.5
15
30
/lA
/lA
/lA
VOL Low Level Output Voltage VOO = 5 V
Voo = 10V
Voo= 15V
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
100 Quiescent Device Current
VOH High Level Output Voltage Voo = 5 V
Voo= 10V
Voo=15V
4.95
9.95
14.95
V IL
Low Level I nput Voltage
Voo=5V. VO=4.5V'}
Voo=10V.Va=9.0V Ilal-+ OUTPUT
TL/FI5957-4
• } TO NEXT
STAGE
'-------------------
~
5·84
TlIF/5957.3
Flip-flop logic (1 of 7 identical stagesl.
Absolute Maximum Ratings
Recommended Operating Conditions
(Notes 1 and 2)
(Note 2)
VOO de Supply Voltage
V, N Input Voltage
VOO de Supply Voltage
Y,N Input Voltage
T A Operating Temperature Range
C040248M
C04024BC
-0.5 to +18 VOC
-o.S to VOO +O.S VOC
~5°C to +lS0°C
Ts Storage ~emperature Range
Po Package Dissipation
SOOmW
TL Lead Temperature (Soldering, 10 seconds)
260°C
+3 to +15 VOC
Oto VOO VOC
-SSoC to +12SoC
-40° C to +8So C
DC Electrical Characteristics CD4024BM (Note 2)
-55°C
SYM
PARAMETER
UNITS
MIN
100
VOL
VOH
VIL
VIH
Quiescent Device Current
Low Level Output Voltage
High Level Output Voltage
Low Level Input Voltage
High Level Input Voltage
liN
MIN
TYP
MAX
MIN
MAX
5
0.3
5
150
I'A
10
0.5
10
300
I'A
VOO = 15V
20
0.7
20
600
I'A
VOO = SV
0.05
0.05
0.05
0.05
0.05
V
VOO = 15V
0.05
a
a
a
0.05
VOO = lOV
O.OS
0.05
V
1101< lilA
V
1I01<1I'A
VOO = 5V
4.95
4.95
5
4.9S
V
VOO= 10V
9.95
9.95
10
9.95
V
VOO= 15V
14.95
14.95
15
14.95
V
1101< lilA
VOO = 5V, Vo = 0.5V or 4.5V
VOO = 10V, Va = 1.0V or 9.0V
1.5
2
1.5
1.S
V
3.0
4
3.0
3.0
V
VOO = 15V, Va = 1.5V or 13.5V
4.0
6
4.0
4.0
V
1101< lilA
Vo = 0.5V or 4.5V
3.5
3.5
3
3.5
V
VOO = 10V, Va = 1.0V or 9.0V
7.0
7.0
6
7.0
VOO = 15V, Va = 1.5V or 13.5V
11.0
11.0
9
11.0
V"
V
VOO = 5V, Va = O.4V
VOO = 10V, Va = 0.5V
0.64
0.51
0.88
VOO = 15V, Va = 1.5V
High Level Output Current
INate 3)
Low Level Output Current
INate 3)
10H
MAX
VOO = 5V
VOO = 10V
VOO= 5V,
10l
12SoC
25°C
CONDITIONS
Input Current
0.36
rnA
2.25
0.9
rnA
4.2
1.3
'3.4
8.8
2.4
rnA
VOO = 5V, Vo = 4.6V
-{l.64
-{l.51
-{l.88
-{l.36
rnA
VOO = 10V, Vo = 9.5V
-1.6
-1.3
-2.25
-{l.9
rnA
VOO = 15V, Vo = 13.5V
-4.2
-3.4
-8.8
1.6
-10 5
10-5
-{l.10
VOO = 15V, V,N = OV
VOO = 15V, Y,N = 15V
0.10
rnA
-2.4
-{l.10
-1.0
I'A
0.10
1.0
I'A
DC Electrical Characteristics CD4024BC (Note 2)
-40°C
.SYM
PARAMETER
VOL
VOH
Quiescent Device Current
Low Level Output Voltage
High Level Output Voltage
25°C
MIN
TYP
-
85°C
UNITS
MIN
100
,
CONOITIONS
MAX
MAX
MIN
MAX
VOO = 5V
20
0.3
. 20
150
I'A
VOO= 10V
40
0.5
40
300
I'A
VOO = 15V
60
0.7
80
600
I'A
VOO = 5V
0.05
0.05
V
0.05
0.05
0.05
V
VOO = 15V
0.05
a
a
a
0.05
VOO = 10V
0.05
0.05
V
1101< lilA
1101< lilA
VOO = 5V
4.95
4.95
5
4.95
VOO = lDV
9.95
9.95
10
9.95
VOO = 15V
14.95
14.95
15
14.95
5·85
V
V
V
•
DC Electrical Characteristics (Coned.) CD4024BC (Nole 2)
VIL
VIH
IOL
Low Level Input Voltage
High Level Input Voltage
Low Level Output Current
(Note 3)
IOH
liN
High Level Output ~urre~t
(Note 3)
Input Current
UNITS
CONOITIONS
PARAMETER
MIN
IIOI>-[:><>tr=::f:=t========i=f=F=======i=~F======:::;"
ENABLE
CLOCK
~ ~ ~iiiIII~~
••
DECADE~
BlNARV·
.,
112
5-94
113
Absolute Maximum Ratings
Recommended Operating Conditions
(Notes 1 and 21
(Note 21
vee de Supply Voltage
-{J.S to +18 Vec
VIN Input Voltage
-{J.S to Vee + O.S Vec
TS Storage Temperature Range
-6S'C to +IS0'C
Po Package Dissipation
SOOmW
TL Lead Temperature (Soldering, 10 secondsl
2S0'C
Vee de Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
Ce40298M
Ce4029BC
3to ISVec
Vec
o to Vee
-6S'C to +12S'C
-40'C to +8S'C
DC Electrical Characteristics CD4029BM (Note 2)
SYM
lee
PARAMETER
Quiescent Device Current
-5SC
MAX
MIN
CONelTIONS
VOH
VIL
VIH
IOL
IOH
Low Level Output Voltage
High Level Output Voltage
Low Level Input Voltage
High Level Input Voltage
MAX
12S C
MIN
MAX
UNITS
S
S
150
p.A
Vee = 10V
10
20
10
300
p.A
20
SOO
p.A
0.05
0.05
0.05
0.05
V
0.05
0.05
V
5
1I0klp.A
Vee = 5V
0.05
Vee = 10V
0.05
Vee = 15V
0.05
a
a
a
V
IIOI = 10V
VOO = 15V
High Level Output Voltage
2S'C
TYP
VOO = IOV
VOO = 5V
VOO~
VOH
MIN
0.05
0.05
a
0
0.05
O.OS
0.05
0.05
V
V
0.05
a
0.05
0.05
V
IIOI0,
DATA OUT (0)
ONE STAGE __________ J
~Cl
12'
Ci
[::>o.!
Ci
DELAYED CLOCK
DUTICLol
Cl
TLIFI5962·1
T
f
Dual-In-Line Package
RECIRCULATE IN
16
CLOCK IN
NC
NC
NC
NC
NC
NC
DATA our (0)
DATA
VDD
DATA IN
Order Number CD4031 BMJ or CD4031 BCJ
See NS Package J16A
Order Number CD4031 BMN or CD4031 BCN
See NS Package N16E
NC
Oiif (01
MODE CONTROL
gE~~~~oUT (Clal
Vss
TOP VIEW
TUFI5962·2
5-103
(')
Absolute Maximum Ratings
~
Recommended Operating Conditions
(Notes 1 and 2)
(Note 2)
-0.5Vto+18V
Voo Supply Voltage
-0.5 V to Voo + 0.5 V
VIN Input Voltage
_65°C to +150°C
Storage Temperature Range
Ts
Package Dissipation
500mW
Po
Lead Temperature (Soldering, 10 seconds)
260°C
TL
Voo Supply Voltage
V'IN' Input Voltage
TA Operating Temperature Range
CD4031BM
CD4031BC
+3 V to +15V
OV to Voo
_55°C to +125°C
-40°C to +85°C
DC Electrical Characteristics (Note 2) CD4031BM
_55°C
SYM
100
PARAMETER
CONDITIONS
Quiescent Device Current
Voo = 5V, VIN = Vol'> or Vss
Voo = 10V, VIN = Voo or VSS
Voo = 15V, VIN = Voo or VSS
VOL Low Level Output Voltage Voo = 5 V }
Voo = 10V VIH = Voo, VIL = OV,
Voo=15V
1101 < lilA
VOH Higb Level Output Voltage V OO =5V}
Voo = 10V VIH = Vo o, VIL = OV,
Voo=15V
1101 < 1 /lA
VIL
VIH
IOL
IOL
Low Level Input Voltage
Voo=5V, Vo=0.5Vor4.5V }
Voo= 10V, Vo= 1.0Vor9.0V
Voo = 15V, Vo = 1.5V or 13.5V
1101 <"l/lA
Voo=5V, Vo=0.5Vor4.5V }
Voo = 10V, Va = 1.0Vor 9.0V
Voo= 15V, Vo = 1.5Vor 13.5V
1101 < lilA
liN
MAX
5
10
20
0.01
0.01
0.02
5
10
20
150
300
600
/lA
/lA
/lA
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
.V
V
4.95
9.95
14.95
4.95 5
9.95 10
14.95 15
MAX
V
V
V
4.95
9.95
14.95
2.25
4.5
6.75
1.5
3.0
4.0
MIN
UNITS
TYP
MIN
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.5
8.25
3.5
7.0
11.0
o Output
Low Level Output Current, Vao=5V, VO= 0.4 V
= Voo
Vaa = 10V, Vo = 0.5V }VIH
V IL = OV
(Note 3)
Vaa = 15V, Vo = 1.5 V
'2.3
5.1
10.5
1.9
4.2
8.8
3.8
8.4
17
1.3
2.8
6.1
rnA
rnA
mA
b.ow Level Output Current, Vaa=5V, Vo=O.4V
Vaa=10V,Vo=0.5V }VIH = Vaa
VIL = OV
(Note 3)
Voa= 15V, VO= 1.5V
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
rnA
rnA
mA
High Level Output Current, Vaa=5V, VO=4.6V }
_
_
VIH=VOa
All Outputs
Vaa- 10V,Vo-9.5V VIL=OV
(Note 3)
VOO= 15V, VO= 13.5V
-0.64
-1.6
-4.2
-0.51 -0.88
-2.25
-3.4 -8.8
-0.36
-0.9
-2.4
High Level Input Voltage
Q and C La Outputs
IOH
+125°C
+25°C
MAX
MIN
Input Current
-1.3
_10.5 -0.1
10.5 0.1
-0.1
0.1
Voa = 15V, VIN = OV
Vaa = 15V,VIN = 15V
V
V
V
mAo
mA
rnA
-1.0
1.0
Truth Tables!
MODE CONTROL (data selection)
MODE
DATA RECIRCULATE
CONTROL
IN
IN
EACH STAGE
DATA INTO
FIRST STAGE
0
0
X
0
0
1
X
1
1
X
0
0
1
X
1
1
x = irrelevant
NC = no change
~;::.
Low to High level transition
~= Hig~ to Low level transition
5·104
On
CL
an
0
~
0
1
~
1
X
"'--
NC
IlA
IlA
o
C
DC Electrical Characteristics (Note 2) CD4031BC
SYM
100
-40·C
CONDITIONS
PARAMETER
Quiescent Device Current
0l:Io
oCo)
MIN
Voo = 5V, VIN = Voo or Vss
Voo = 10V, VIN = Voo or VSS
Voo = 15V, VIN = Voo or VSS
VOL Low Level Output Voltage VOO7 5V }
Voo = 10V VIH = Vo o , VIL = OV, 1101 < lilA
Voo=15V
VOH High Level Output Voltage VDo=5V}
Voo = 10V VIH = Vo o , VIL = OV, 1101 < lilA
Voo=15V
Low Level Input Voltage
MAX
+2S·C
MIN
+8S·C
TYP
MAX
20
40
80
0.01
0.01
0.02
20
40
80
150
300
600
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05 .
0.05
0.05
4.95 5
9.95 10
14.95 15
4.95
9.95
14.95
MAX
4.95
9.95
14.95
UNITS
IlA
IlA
IlA
V
V
V
V
V
V
\
2.25
4.5
6.75
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.5
8.25
3.5
7.0
11.0
Q Output
Low Level Output Current, Voo=5V, VO=O.4V}v -V
VoO=10V,VO=0.5V
IH:: DO
VIL - OV
(Note 3)
Voo = 15V, Vo = .1.5 V
1.8
4.0
8.7
1.6
3.5
7.5
3.8
8.4
17
1.3
2.8
6.1
rnA
rnA
rnA
I:.ow Level Output Current, Voo=5V, VO=O.4V}
_
_
VIH = Voo
Vo o -l0V,Vo-0.5V VIL=OV
(Note 3)
Voo = 15V, Vo = 1.5 V
0.52
1.3
3.6
0.44
1.1
3.0
0.88
2.25
8.8
0.36
0.9
2.4
rnA
rnA
rnA
IOH
High Level Output Current, VoO=5V, VO=4.6V}
_
_
VIH=VOO
All Outputs
Vo o -l0V,VO-9.5V VIL=OV
(Note 3)
Vo o =15V,Vo=13.5V
-0.52
-1.3
-3.6
-0.44 -0.88
-2.25
-1.1
-3.0 -B.B
-0.36
-0.9
-2.4
rnA
rnA
rnA
liN
I nput Current
VIL
VIH
IOL
IOL
High Level Input Voltage
1.5
3.0
4.0
MIN
Voo=5V, Vo=0.5Vor4.5V }
Voo = 10V, Vo = 1.0 V or 9.0V
1I01-~
>-~~
!
I
I
!
I
I
I
I
I
I
I
7 STAGES
SAME AS
STAGE 1
L
II
I
I
I
T
-
pKt:
....
-...r
-~
IL- _ _ _ _ _ _ _ _
-----~-
16
AI
5·110
I
I
I
I
I
I
1-..1
I
I
I
I
I
I
l'TBT91!°1!'1/21P
A2 AJ A4 AS A6 A7 ,AS
TLlFI596l-3
r-------------------------------------------------------------------'o
C
Switching Time Waveforms and Test Circuits
~
~
Synchronous Operation
CLOCK
OJ
A ENABLE
s:::
oc
~
PIS
AlB
I
AIS
n
n
SERIAL
OATA
AI
OJ
o
A2
AJ
A4
n
A5
A6
n
Al
A8
n
~
________________
~r-UnL
tt,CL
'=
tf,CL = 20n$
TlIFI5963·5
Bl
B2
BJ
Asynchronous Operation
B4
B5
VOO-:'A'OR'iVSO%"::-r-----""\,
DATA
o INPUTS
B6
81
B8
I
I
VOO""IFOii"'A'-DATA
U PUTS
I_BOATALINESAREOUTPUTS_I_I
A DATA
LINES ARE
OUTPUTS
TLIFI5963-6
TLlFI596J..4
tPZH~tPHZ
(B
}---~-.... OUTPUT
AlB
PORT CONTROL)
(B
~.~
PORT CONTROL)
AE OR AlB
PORT CONTROL
(A
AE DR AlB
(A PORT CONTROL)
AE. AlB
VOH
o
A OR B OUTPUT
TlIF/5963-8
TLIF/5963·7
VOO
tpZl
(B
AlB
PORT CONTROL)
(8 PORT CONTROL)
(A
AE OR AlB
PORT CONTROL)
(A
AlB
j - - -....---OUTPUT
AE DR AlB
PORT CONTROL)
50%
-I
VOO
VOL _ _ _ _..... I__
A DR B OUTPUT
A DR B OUTPUT
TL/FI5983·10
TLIFI5963·9
5·111
(J
In
~
C')
Applications
16·Bit parallel in/parallel out, parallel in/
serial out, serial in/parallel out, serial in/
serial out register
0
~
VDD
VDD
0
-
H
(J
.:E
In
SERIAL
DATA
~
C')
A·PARALLEL
A·PARALLEL
DATA
SI
SI
DATA
VDD
0
VDD
~
AlB
CD40J4B
CD40J4B
0
AlS
(J
CL
B·PARALLEL
DATA
B·PARALLEL
DATA
PIS
PIS
SERIAL
DATA
SERIAL
DATA
________
______________________
Pffl~-r+---~-----------------------+~--~------------------~
Affl~~+-------------------
~~
~
CL~--~----------------------------~----------------------~
TL/F/5963·11
16-Bit serial in/gated parallel out register
"A" ENABLE ~-.....- - - - - - - - - - - - - - - - - .
AE
"A" PARALLEL
SERIAL
DATA
DATA
SI
SI
AlB
"A" PARALLEL
DATA
AlB
CD40J4B
CD4DJ4B
AlS
CL
"':"
CL •
"B" PARALLEL
DATA
"B" PARALLEL
DATA
PIS
SERIAL
SERIAL
DATA
DATA
AlB
CL
TLlFI5963·12
II
Frequency and Phase Comparatpr
---1--"-""'"
VDD
SI
AlB
CD4034B
B DATA
VDD
L.._ _ _ _ _ _ _ _ _ _ _
~
OUTPUT
TL/F/5963·13
5·112
Applications
(Cont'd.)
12 - - - - - ,
1""---'
CLOCK
P / S - - - - -...
OUTPUT - - - - - - - - - - - - - ,
1.....1 - - - - - 1 1 >
12-----.·1~---------
«WHEN '1"'12, tw IS PROPORTIONAL TO THE PHASE OF 11 WITH RESPECT TO 12
TUFI5963-14
Shift Right/Shift Left with Parallel Inputs
SHIFT LEFT OUTPUT
"A', ENABLE
SHI FT LEFT!
SHIFTRIGHT
-
SHIFT RIGHT
INPUT
.p-;
lIE
PIS
~ ~P~LL~OA4Jr
popREG.1
C04034B
AlE 1
i...-+
AE 1
8
SI
"+
PIS
'"'- PIS
r--- AIS
_AlS
CLOCK
-
r+
CL
AlSPA RALLEL
ENTRY
AlB 1
-J,.:
~
-!-
A·PARALLEL DATA
_B
VD~£
PIS
REG.3
CD4034B
PIS
r--
; - - CL
B PARALLEL DATA
_8
4t t t t t t t t
.2
~rEG
CD4D34B
B
~
~
SHIFT LEFT·
~UT
AIS
C
A
A·PARALLEL DATA
SI
VDDL AlS
AIS
A/Ol_
AlE 1"""-
r
; ; ; - - SI
8
CL
8
I
rtrtrt1rt1
SHIFT";G HT
OUTPUT
SI
AlB 1
AlE 104--
"A" PARALLEL OATA
-
B
........
8
REG.4
CD4034B
CL
A/Bl_
B PARALLEL DATA
4t t t t t. t t t
TL/FI5963-15
A "High" ("Low") on the Shift Left/Shift Right input
allows serial data on the Shift Left Input (Shift Right
Input) to enter the register on the positive transition
of the clock signal. A "high" on the "A" Enable Input
disables the "A" parallel data lines on Registers 1 and 2
and enables the "A" data lines on Registers 3 and 4
*Shift left input must be disabled (juring parallel entry.
5·113
and allows parallel data into Registers 1 and 2. Other
logic schemes may be used in place of registers 3 and 4
for parallel loading.
When parallel inputs are not used Registers 3 and 4 and
associated logic are not required.
Truth Table
"
AlB A/S
OPERATION·
"A" ENABLE
PIS
0
0
0
X
Serial
Synchronous Serial data input, A- and B-Parallel data outputs disabled.
0
0
1
X
Serial
Synchronous Serial data input, B·Paraliel data output.
0
1
0
0
Parallel
0
1
0
1
Parallel
B Asynchronous Parallel data inputs, A·Parallel data outputs disabled.
0
1
1
0
Parallel
A·Paraliel data inputs disabled, B·Parallel data outputs, synchronous data recirculation.
A·Paraliel data inputs disabled, B·Parallel data outputs, asynchronous data recirculation ..
X
MOOE
B Synchronous Parallel data inputs, A·Paraliel data outputs disabled.
0
1
1
1
Parallel
1
0
0
X
Serial
Synchronous :;ierial. dat~ input, A-Parallel data output.
1
0
1
X
Serial
Synchronous Serial data input, B-Parallel data output.
1
1
0
0
Parallel
1
1
0
1
Parallel
B Asynchronous Parallel data input, A·Paraliel data output.
1
1
1
0
Parallel
A Synchronous Parallel data input, B-Parallel data output.
1
1
1
1
Parallel
A Asynchronous Parallel data'input, B·Parallel data output.
B Synchronous Parallel data input, A·Paraliel data output.
= Don't Care
* For synchronous operation
(serial mode or when A/S = 0 in parallel mode), outputs change state at positive transition of the clock.
5-114
r-------------------------------------------------------~n
C
~National
;a:.
~
~ Semiconductor
CD
i:
(;
CD4035BM/CD4035BC 4-Bit Paraliel-ln/Paraliel-Out
Shift Register
~
CD
o
General Description
Features
The C04035B 4-blt parallel-In/parallel-out shift register
Is a monllthlc complementary MOS (CMOS) Integrated
circuit constructed with P- and N-channel enhancement
mode transistors. this shift register Is a 4-stage clocked
serial register having provisions for synchronous parallel
Inputs to each stage and serial Inputs to the first stage
via JK logic. Register stages 2, 3, and 4 are coupled In a
serial "0" flip-flop configuration when the register is In
the serial mode (parallel/serial control low).
• Wide supply voltage range
3.OVto 15V
0.45 Voo (typ.)
• High noise Immunity
fan out of 2drlvlng 74L
or 1 driving 74LS
• Low'powerTTL
compatibility
• 4-stage clocked operation
• Synchronous parallel entry on all 4 stages
• JK Inputs on first stage
Parallel entry via the "0" line of each register stage is
permitted only when the parallel/serial control Is "high".
• Asynchronous true/complement control on all outputs
In the parallel or serial mode, information Is transferred
on positive clock transitions.
• Static flip-flop operation; master/slave configuration
• Reset Control
• Buffered outputs
When the true/complement control Is "high", the true
contents of the register are available at the output terminals. When the true/complement control Is "low", the
outputs are the complements of the data In the register.
The true/complement control functions asynchronously
with respect to the clock signal.
Applications
JK Input logic Is provided on the first stage serial Input to
• Automotive
• Alarm systems
minimize logic requirements particularly In counting and
sequence-generation applications. With JK Inputs connected together, the first stage becomes a "0" flip-flop.
An asynchronous common reset Is also provided.
• Data terminals
• Industrial controls
• Instrumentation
• Remote metering
• Medical electronics
• Computers
5"W (typ.) (ceramic)
• Low power dissipation
t05MHz
• Highspeed
Logic Diagram
PARALLEL
INPUT -1
9
PARALLEL 7
SERIAL
caNTRallPtsl
J
ClaCK
.....---+_...,--....- - _ +_
<>----c)c>---~_.,....-
_.-___1p__--_H--.r._-...,
o·--;f-cl...J
6
<>----[)o--------+---;----+---+----t---+----'
---i.>C>-----""-_--+---____t-____---;------'
5
RESET0
TRuElca~~~i 0.'------------...,.+-------~I_------rl-------,
?
9,.
al
OJ
PIS = 0 = serial mode
Input to output is:
T/C =1 = true outputs
a) A bidirectional low impedance when control input 1 is low
and control input 2 is high.
*TG = transmission gate
1
b) An open circuit when control input 1 is high and control input 2 is low.
TUF/5984-t
5-115
o
a:I
Lt)
C")
~
o
o
ia:I
Lt)
C")
o
.oo:t
'0
o
Absolute Maximum Ratings (Notes 1 and 2)
Operating Conditions (Note 2)
-0.5 to +18V
VOO de Supply Voltage
-0.5 to VOO + 0.5V
VIN Input Voltage
~5"c to +150'C
TS Storage Temperature Range
Po Package Dissipation
500mW
TL Lead Temperature (Soldering, 10 seconds)·
260°C
VOO de Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
C040358M
C04035BC
3 to 15V
OtoVOOV
-55'C to +125°C
-40°C to +B6°C
DC Electrical Characteristics C04035BM (Note 2)
SYM
100
VOL
VOH
VIL
VIH
10l
10H
liN
--55°C
PARAMETER
CONOITIONS
Quiescent Device Current
low level Output Voltage
High l-evel Output Voltage
low level Input Voltage
High level Input Voltage
MIN
Vob = 5V, VIN = VDO 'or VSS
VOO = 10V, VIN = VOO or VSS
VOO = 15V, VIN = VOO or VSS
25°C
MAX
MIN
MIN
MAX
UNITS
MAX
5
0.3
5
150
pA
10
0.5
10
300
pA
20
1.0
20
600
pA
IIOI<1.0pA
VOO = 5 V
0.05
0
0.05
0.05
V
VOO= 10V
0.05
O·
0.05
0.05
V
VOO = 15V
0.05
0
0.05
0.05
V
1101< 1.0llA
V
VOO = 5V
4.95
4.95
5
4.95
VOO = 10V
9.95
9.95
10
9.95
V
VOO = 15V
14.95
14.95
15
14.95
V
1101 < 1.0llA
VOO = 5V,
Va = 0.5V or 4.5V
1.5
1.5
1.5
V
VOO = 10V,
Va = 1.0V or 9.0V
3.0
3.0
3.0
V
VOO = 15V,
Va .= 1.5V or 13.5V
4.0
4.0
4.0
V
1101 < 1.0 IlA
VOO = 5V,
Va = 0.5V or 4.5V
3.5
3.5
3.5
V
VOO = 10V,
Va = 1.0V or 9.0V
7.0
7.0
7.0
V
VOO = 15V,
Va = 1.5V or 13.5V
11.0
11.0
Low Level Output Current
VOO = 5V,
Va = O.4V
0.64
0.51
(Note 3)
VOO = 10V,
VO= 0.5V
1.6
VOO = 15V,
Va = ~.5V
4.2
High Level Output Current
VOO = 5V,
Va = 4.6V
-0.25
(Note 3)
VOO = 10V,
Va = 9.5V
-0.62
VOO = 15V,
VO= 13.5V
-1.8
Input Current
125°C
TYP
VOO = 15V,
VIN = OV
VOO = 15V,
VIN = 15V
11.0
V
0.88
0.36
mA
1.3
2.25
0.9
mA
3.4
8 ..8
2.4
mA
-0.2
0.36
-0.14
rnA
-0.5
-1.5
0.9
-0.35
-1.1
mA
-3.5
rnA
-0.1
-10--5
-0.1
-1.0
pA
0.1
10-5
0.1
1.0
IlA
DC Electrical Character,stics C04035BC (Note 2)
SYM
100
Val
VOH
Vll
VIH
-40°C
PARAMETER
CONOITIONS
Quiescent Device Current
Low level Output Voltage
High level Output Voltage
,
low level Input Voltage
High level Input Voitage
MIN
VOO = 5V, VIN = VOO or VSS
VOO = 10V, VIN = VOO or VSS
VOO = 15V, VIN = VOO or VSS
MAX
85°C
25°C
MIN
TYP
MAX
MIN·
MAX
UNITS
20
0.5
20
150
40
1.0
40
300
IlA
pA
80
5.0
80
600
pA
1101<11lA
VOO = 5V
0.05
0
0.05
0.05
V
VOO = 10V
0.05
0
0.05
0.05
V
VOO = 15V
0.05
0
0.05
0.05
V
1101< lilA
VOO = 5V
4.95
4.95
5
4.95
V
VOO = 10V
9.95
9.95
10
9.95
V
VOO = 15V
14.95
14.95
15
14.95
V
1101<11lA
VOO = 5V,
Va = 0.5V or 4.5V
1.5
1.5
1.5
VOO = 10V,
Va = 1.0V or 9.0V
3.0
3.0
3.0
V
V
VOO = 15V,
Va = 1.5V or 13.5V
4.0
4.0
4.0
V
1101< 1 IlA
VOO = 5V,
Va = 0.5V or 4.5V
3.5
3.5
3.5
V
VOO= 10V,
Va = 1.0V or 9.0V
7.0
7.0
7.0
V
VOO = 15V,
Vo = 1.5V or 13.5V
11.0
11.0
11.0
V
5·116
DC Electrical Characteristics (Cont'd.) CD4035BC (Note 2)
-40°C
SYM
PARAMETER
MIN
85°C
25°C
MAX
MIN
TYP
MAX
MIN
MAX
UNITS
Low Level Output Current
VOO = 5V.
Vo = O.4V
0.52
0.44
0.88
0.36
mA
(Note 3r
VOO = 10V.
Vo = 0.5V
1.3
1.1
2.25
0.9
mA
VOO = 15V.
Vo = 1.5V
3.6
3.0
8.8
2.4
mA
High Level Output Current
VOO = 5V.
Vo = 4.6V
-0.2
-0.16
-0.36
-0.12
mA
(Note 3)
VOO = 10V.
Vo = 9.5V
-0.4
-0.9
-0.3
mA
VOO = 15V.
Vo = 13.5V
-0.5
-1.4
VOO = 15V.
VIN = OV
VOO = 15V.
VIN = 15V
IOL
IOH
CONDITIONS
Input Current
liN
-l.?
-3.5
mA
-1.0
-0.3
-10 S
-0.3
-1.0
p.A
0.3
lO-S
0.3
1.0
p.A
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed, they are not meant to imply
that the devices should be operated at these limits. The table of "Recommended Operating Conditions" and "Electrical Characteristics" provides
conditions for actual device operation.
Note 2: VSS = OV unless otherwise specified.
Note 3: IOH 8IJd IOL are tested one output at a time.
AC Electrical Characteristics
T A = 2Soc. CL = 50 pF. R L = 200k. tr and tf = 20 ns. unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VOO = 5V
250
500
ns
VOO = 10V
100
200
ns
VOO = 15V
75
150
ns
Transition Time High
VOO = 5V
90
175
ns
Low to High
VOO = 10V
50
75
ns
VOO = 15V
40
60
ns
Transition Time
VOO = 5V
135
270
ns
Low to High
VOO = 10V
70
140
ns
VOO = 15V
60
120
ns
CLOCKEO OPERATION
tPHL. tPLH
tTHL
tTLH
tWL.tWH
trCL. tfCL
ts
ts
Propagation Delay Time
Minimum Clock Pulse Width
Clock Rise and Fall Time
Minimum Set·upTime
J/K Lines
,
Parallel·ln Lines
I
ts
fMAX
CIN
PIS Control
Maximum Clock Frequency
Input Capacitance
335
135
VOO = 10V
165
50
ns
VOO = 15V
100
40
ns
VOO = 5V
15
p.s
VOO = 10V
10
p.s
VOO = 15V
5
p.s
Voo = 5V
250
500
ns
VOO = 10V
100
200
ns
VOO = 15V
80
160
ns
VOO = 5V
250
500
ns
VOO = 10V
100
200
ns
VOO = 15V
80
160
ns
VOO = 5V
100
200
ns
VOO = 10V
40
80
ns
VOO ~ 15V
35
60
twH
Propagation Oelay Time
Minimum Reset Pulse Width
ns
VOO = 5V
1.5
2.5
MHz
VOO= 10V
3
6
MHz
VOO=,15V
5
9
Any Input
5
MHz
7.5
pF
-
RESET OPERATION
tPHL. tPLH
ns
VOO = 5V
VOO = 5V
300
500
ns
VOO = 10V
150
200
ns
VOO = 15V
85
150
ns
VOO=5V
75
250
ns
VOO = 10V
30
'110
ns
VDO = 15V
25
80
ns
5·117
•
Truth Table
tn (OUTPUTS)
tn - 1 (INPUTS)
CL
J
K
R'
f
f
f
f
f
0
x
I
'X
On-l
an
0
0
a
X
0
0
I
x
0
0
I
'0
I
0
0
X'
I
0
X
X
0
°n-l
X
X
I
X
~~~~lE
0n-l
°n-l
I
I
.On-l
0
Switching Time Waveforms
CLOCK
INPUT
J·K
INPUT _ _ _ _ _ _..J
'IS
INPUT
____________
5Q%
~------+_-JI
i----I- lsn·uPH
'" --------f-,----....::....--+----J
INPUT
9D%
1D.
t,HL
TIe Input Low
tpLH
IPLH
TUFI5964-3
Reset Input Low
Connection. Diagram
Dual-In-Line Package
PARALLEL INPUTS
TRUE/COMPLEMENT OUTPUTS
Vou
/..
r-
D2J02
.
"
"4
Q4JG4 1
12
"
11
-
2
TIC
•
"
.
1
-
01/Q1
Q3J03
3
4
-
J
K
5
RESET
•
CLOCK
,
PIS
I'
Vss
~
TRUE/COMPLEMENT
SERIAL
OUTPUT
INPUTS
TOP VIEW
TUF/5964-2
Order Number CD4035BMJ or CD4035BCJ
See NS Package J16A .
Order Number CD4035BMN or CD4035BCN
See NS Package N16E
5-118
.--------------------------------------------------------.n
c
~National
.~ Semiconductor
~
.-.
CD4041M/CD4041C Quad True/Complement Buffer
§
.....
~
n
General Description
Features
The CD4041M/CD4041C is aquad true/complement buffer
consisting of N- and P-channel enhancement mode transistors having low-channel resistance and high current
(sourcing and sinking) capability. The CD4041 Is intended
for use as a buffer, line driver, or CMOS-to-TTL driver.
• Wide supply voltage range
All inputs are protected from static discharge by diode
clamps to Vee and Vss.
o
• High noise immunity
3.0Vto 15V
40% Vee (typ.)
• True output
High current source and sink capability
8 mA (typ.) @ Va = 9.5 V, Vee = 10 V
3.2mA(typ.)@Vo=0.4V,Vee =5V(twoTTLIoads)
• Complement output
Medium current source and sink capability
3.6 mA (typ.) @ Vo = 9.5 V, Vee = 10 V
1.6mA(typ.)@Vo=0.4V,Vee=5V
Connection and Schematic Diagrams
Dual-In-Line Package
VOO
114
13
00UT
00UT
12
11
10
CoiiT
COUT
9
B
-
Order Number CD4041MJ or CD4041CJ
See NS Package J14A
-
1
2
AOUT
-AOUT
3
4
5
BOUT
-BO.UT
TOP VIEW
Order Number CD4041MN or CD4041CN
See NS Package N14A
P
6
Vss
TL/FI5965-1
1 of 4 Identical Units
voo
VOO
INPUT
VOO
o-....W'll-HH
TRUE
OUTPUT
Vss
Vss
VOU
COMPLEMENT
OUTPUT
Vss
5-119
TlIFI5965·2
.
(J
,..
§
Absolute Maximum Ratings
Recommended Operating Conditions
c
(Notes 1 and 2)
(Note 2)
i,..
voo Supply Voltage
--O-......-I.;>O--;
.....- - - C L
CL
TlIFI5966-2
TUFI~-4
5-123
o
Absolute Maximum Ratings
Recommended Operating Conditions
(Notes 1 and 2)
(Note 2)
-{).5V to +18V
VDD Supply Voltage
-{).5V to V DO + 0.5V
V,N Input Voltage
TS Storage Temperature Range
-65°C to +150°C
Po Package Dissipation
500mW
260"C
T L Lead Temperature (Soldering, 10 seconds)
V DO Supply Voltage
V,N Input Voltage
T A Operating Temperature Range
CD4042BM
CD4042BC
3V to 15V
OVto VDD
-65°C to +125°C
-40°C to +85°C
DC Electrical Characteristics CD4042BM (Note 2)
-55°C
SYM
100
VOL
CONDITIONS
PARAMETER
Quiescent Device Current
Low Level Output Voltage
MIN
= 5V
= 10V
VOO = 15V
High Level Output Voltage
10L
Low Lev,el Output Current
(Note 4)
1
30
/lA
2
60
/lA
4
0.02
4
120
/lA
VDD
0.05
0
0.05
0.05
V
VDD
0.05
0
0.05
0.05
V
0.05
0
0.05
0.05
V
1101 < 1 /lA, V,H
= VDD, V,L = OV
1101 < 1 /lA, V,H
= VDD, V,L = OV
;
4.95
4.95
5
4.95
V
9.95
9.95
10
9.95
V
14.95
14.95
15
14.95
V
ilOI
3.5
3.5
2.75
3.5
V
VDD
7.0
7.0
5.5
7.0
V
11.0
11.0
8.25
11.0
V
High Level Output Current
V,H = VDD, V,L = OV
(Note 4)
VDD = 5V,
Vo = 4.6V
= 10V, Vo = 9.5V
VDD = 15V, Vo = 13.5V
VDD
'iN
Input Current
UNITS
0.02
0.64
0.51
0.88
'0.36
rnA
1.6
1.3
2.25
0.9
rnA
4.2
3.4
8.8
2.4
rnA
-0.64
-0.51
-0.88
-0.36
rnA
-1.6
-1.3
-2.25
-0.9
rnA
-3.4
-8.8
VDD = 15V, Vo = 1.5V
10H
MAX
0.02
= 5V; Vo = 0.5V or 4.5V
= 10V, Vo = 1V or 9V
VDD = 15V, Vo = 1.5V or 13.5V
High Level Input Voltage
MIN
1
= 5V
= 10V
VDD = 15V
V,H
125°C
MAX
2
VDD
Low Level Input Voltage
TYP
VOO
VDD
V,L
MIN
VOO
= 5V
= 10V
VDD = 15V
VOH
25°C
MAX
-4.2
VDD = 15V, V,N =OV
VDD
= 15V, V,N = 15V
-2.4
rnA
-{).1
-10 5
-{).1
-1.0
/lA
0.1
10-5
0.1
1.0
/lA
DC Electrical Characteristics CD4042BC (Note 2)
-40°C
SYM
IDD
VOL
PARAMETER
CONDITIONS
Quiescent Device Current
Low Level Output Voltage
MIN
High Level Output Voltage
MIN
MAX
UNITS
0.02
4
30
/lA
8
0.02
B
60
/lA
VDD = 15V
16
·0:02
16
120
/lA
1101 < 1 /lA, V,H = VDD, V,L
= OV
VDD
0.05
a
0.05
0.05
V
VDD
0.05
0
0.05
0.05
V
0.05
0
0.05
0.05
V
1101 < 1 /lA, V,H
VOD
\
85°C
MAX
4
= VUO, V,L = OV
4.95
'9.95
VOD = 10V
Low Level Input Voltage
TYP
VDD = 10V
VDD = 5V
V,L
MIN
VDD = 5V
= 5V
= 10V
VDD = 15V
VOH
25°C
MAX
= 15V
14.95
4.95
5
4.95
V
9.95
10
9.95
V
14.95
15
14.95
V
1I01<1/lA
VDD = 5V,
Vo = 0.5V or 4.5V
VDD = 10V, Vo = lV or 9V
VDD = 15V, Vo
= 1.5V or 13.5V
5-124
1.5
2.25
1.5
1.5
V
3.0
4.5
3:0
3.0
V
4.0
6.75
4.0
4.0
V
DC
Elec~rical
.
Characteristics (Cont'd.) CD4042BC (Note 2)
-40"C
PARAMETER
SYM
CONOITIONS
High Level Input Voltage
V,H
MIN
10L
(Note 4)
HIgh Level Output Current
'OH
(Note 4)
Input Current
liN
MIN
85'C
TYP
MAX
MIN
UNITS
MAX
1101< lilA
= 5V. Va = 0.5V or 4.5V
= 10V, Va = IV or 9V
VOO = 15V, Va = 1.5V or 13.5V
V,H = VO~. V,L = OV
VOO = 5V. Va = O.4V
Voo = 10V, Va = 0.5V
VOO = 15V, Va = 1.5V
V,H = VOO, V,L = OV
VOO = 5V, Va = 4.6V
VOO = 10V, Va = 9.5V
VOO = 15V, Va = 13.5V
VOO = 15V, V,N = OV
VOO = 15V, V,N = 15V
Voo
VOO
Low Level Output Current
MAX
25"C
3.5
3.5
2.75
3.5
V
7.0
7.0
5.5
7.0
V
11.0
11.0
8.25
11.0
V
0.52
0.44
0.88
0.36
mA
1.3
1.1
2.25
0.9
mA
3.6
3.0
8.8
2.4
mA
-0.52
-0.44
--{J.88
-1.1
-2.25
-0.36
--{J.g
mA
-1.3
-3.6
-3.0
-8.8
-2.4
mA
mA
--{J.3
-10-5
--{J.3
-1.0
IlA
0.3
10-5
0.3
1.0
IlA
. AC Electrical Characteristics TA = 25°C, C L =50pF, RL=200k, Input 1,=t,=20ns,
unless otherwise specified
SYMBOL
tPHL, tpLH
tPHL' tPLH
tpHL. tpLH
tPHL, tPLH
tH
tsu
tw
'THL. 'TLH
C,N
PARAMETER
CONOITIONS
=5V
VOO = lQV
VOO = 15V
VOO = 5V
VOO = 10V
VOO = 15V
VOO = 5V
Vaa = 10V
Voa = 15V
Voa = 5V
Voa = 10V
Voa = 15V
Vaa = 5V
Vao = 10V
Vaa = 15V
Vaa = 5V
Vaa = 10V
Vao = 15V
Vaa = 5V
Vaa = 10V
Vaa = 15V
Vao = 5V
Vaa = 10V
Voa = 15V
Propagation Delay Time Data In to Q
Propagation Delay Time Data In to
VOO
Q
Propagation Delay Time Clock to Q
Propagation aelay Time Clock to Q
Minimum Hold Time
Minimum Set-Up Time
Minimum Clock Pulse Width
Transition Time
Any Input
Input Capacitance
MIN
TVP
MAX
175
350
UNITS
ns
75
150
ns
60
120
ns
150
300
ns
75
150
ns
50
100
ns
250
500
ns
100
200
ns
80
160
ns
250
500
ns
115
230
ns
90
180
ns
60
'120
ns
30
60
ns
25
50
ns
0
50
ns
0
30
ns
0
25
ns
100
200
ns
50
100
ns
30
60
ns
125
250
ns
60
125
ns
50
100
ns
5.0
7.5
pF
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The tables of "Recommended Operating Conditions" and "Electrical Characteristics" provide
conditions for actual d~vice operation.
Note 2: VSS = OV unless otherwise specified.
Note 3: Being a latch. the C040428M/Ca4042BC is not clock ,ise and fall time sensitive.
Note 4: IOl and IOH are tested one output at a time.
5-125
Switching Time Waveforms
Voo---------------------------------------------POLARITV
-----------------------------
CLOCK
DATA
Voo
o OUTPUT
Vss
tpHl
VOO
iiOUTPUT
Vss
TlIF/5966-5
\
5-126
r----------------------------------------------------------,o
~
~National
~ Semiconductor
m
s::
(;
CD4043BM/CD4043BC Quad TRI·STATE®
NOR RIS Latches
CD4044BM/CD4044BC Quad TRI·STATE
NAND RIS Latches
General Description
Features
CD4043BM/CD4043BC are quad cross-couple TRI-STATE
CMOS NOR latches, and CD4044BM/CD4044BC are quad
cross-couple TRI-STATE CMOS NAND latches. Each
latch has a separate Q output and individual SET and
RESET inputs. There is a common TRI-STATE ENABLE
input for all four latches. A logic "1" on the ENABLE
input connects the latch states to the Q outputs. A logic
"0" on the ENABLE input disconnects the latch states
from the Q outputs resulting in an open circuit condition on the Q output. The TRI-STATE feature allows
common bussing of the outputs.
•
•
•
•
•
•
~
m
Sl
o
Wide supply voltage range
3 V to 15 V
Low power
100 nW (typ.)
High noise Immunity
U.45 VDD (typ.)
Separate SET and RESET inputs for each latch
NOR arid NAND configuration
TRI-STATE output with common output enable
Multiple bus storage
Stobed register
Four bits of independent storage with output enable
General digital logic
Schematic and Connection Diagrams
CD4044BM/CD4044BC
CD4043BM/CD4043BC
ENABLE~:
TUFI5967·2
ENABLE~:
CD4044BM/CD4044BC
TUFI5961-1
Dual-I n-Line and Flat Package.
R3
S3
03
Q2
RZ
51
Vss
CD4043BM/CD4043BC
Dual-In-Line and Flat Package.
54
\loa
Ne
SJ
R3
Q3
Q2
Q4
Q4
SI
01'
ENABLE
TOP VIEW
TL.IF/5967·3
CD4043BM/CD4043BC
S
REO
0
DC
DC
1
1
NC
1
1
1
0
M
R
x
x
o
0
NC
1
~
1
0
0
1
{;
0
0
0
1
1
o
a
E
0
S
x
Rl
ENAILE
TOP VIEW
TL/F/5967-4
Order Number CD4043BMN, CD4043BCN,
CD4044BMN or CD4044BCN
See NS Package N16E
CD4044BM/CD4044BC
x
51
Order Number CD4043BMJ, CD4043BCJ, CD4044BMJ
or CD4044BCJ
See NS Package J16A
52
Truth Table
Nt
OC
NC
X
tJ.
-
5-127
TRI-5TATE
No change
-
Don't care
-
Dominated by 5=1 input
Dominated by R=O input
Il.ll -
(;
~
m
o
Applications
•
•
•
•
~
m
s::
Absolute Maximum Ratings
Recommended Operating Conditions
(Notes 1 and 2)
(Note 2)
Voo Supply Voltage
-Q.5to+18V
VIN Input Voltage
-0..5 to Voo + 0..5 V
Ts Storage Temperature Range
-65·C to +15Q·C
5QQmW
Po Package Dissipation
26Q·C
TL Lead Temperature (Soldering, 10. seconds)
Voo Supply Voltage
VIN Input Voltage
TA Operating Temperature Range
CD4Q43BM, CD4Q44BM
CD4Q43BC, CD4Q44BC
. DC Electrical Characteristics
VOL Low Level
Qutput Voltage
1101" 1 "A, VIL=OV, VIH=VOO
Voo=5.QV
Voo=1QV
Voo=15V
VOH High Le'l'el
Output Voltage
1101 .. 1"A, VIL=QV, VIH=VOO
Voo=5.QV
'Voo=1QV
Voo=15V
VIL Low Level
. inpu~ Voltage
1101" 1"A
Voo = 5.QV, Vo=Q.5Vor 4.5V
Voo = 10. V, Vo = 1.QVor 9.QV
Voo = 15V, Vo = 1.5V or 13.5V
VIH High Level
Input Voltage
1101 ..
Voo =
Voo =
Voo =
10L Low Level
Output Current
VIL=QV, VIH=VOO
Voo = 5.0. V, Vo =Q.4V
Voo=1QV, Vo=Q.5V
Voo=15V, Vo=1.5V
VIL-QV, VIH-VOO
Voo=5.QV, Vo=4.6V
Voo=1QV, Vo=9.5V
Voo=15V, Vo=13.5V
input Current
1"A
5.0. V, Vo =Q.5V or 4.5V
5.0. V, Vo =1.QV or 9.QV
15V, Vo = 1.5V or 13.5V
Max
Typ
Max
5.0.
10.
20.
0..0.1
0..0.1
0..0.2
5.0.
10.
20.
150.
30.0.
60.0.
"A
"A
"A
0..0.5
0..0.5
0..0.5
0.
0.
0.
0.:0.5
0..0.5
0..0.5
0..0.5
0..0.5
0..0.5
V
V
V
4.95
9.95
14.95
,
Min
4.95
9.95
14.95
1.5
3.0.
4.0.
Max
4.95
9.95
14.95
5.0.
10.
15
2.25
4.5
6.75
Min
1.5
3.0.
4.0.
V
V
V
1.5
3.0.
4.0.
V
V
V
3.5
7.0.
11
3.5
7.0.
11
2.75
5.5
8.25
3.5
7.0.
11
V
V
V
0..64
1.6
4.2
0..51
1.3
3.4
1.0.
2.6
6.8
0..36
0..9
2.4
mA
mA
mA
-0..64
-1.6
-4.2
-0..51
-1.3
-3.4
-0..4
-1.0.
-3.0.
-0..36
-0..9
-2.4
mA
mA
mA
-10. 5
10.-5
-0..1
0..1
Voo=15V, VIN=QV
Voo=15V, VIN=15V
DC Electrical Characteristics
Sym Parameter
125'C
Units
Min
Voo = 5V, VIN = Voo or Vss
Voo = 1QV, VIN = Voo or Vss
Voo=15V, VIN=VOOorVss
liN
25'C
Conditions
100 Quiescent
Device Current
10H High Level
Output Current
-55·C to +125·C
-4Q·C to +85·C
CD4Q43BM/CD4Q44BM (Note 2)
-55'C
Sym Parameter
3.0. to 15V
Qto Voo V
-0..1
0..1
-1.0.
1.0.
"A
"A
CD4Q43BC/CD4Q44BC (Note 2)
-4C'C
Conditions
Min
ioo Quiescent
Device Current
Voo =5V, VIN=VOOorVss
Voo=1QV, VIN=VOOorVss
Voo = 15V, VIN = Voo or Vss
VOL Low Level
Output Voltage
1101 .. 1 "A, VIL=QV, VIH=VOO
Voo=5.QV
Voo=1QV
Voo=15V
VOH High Level
Output Voltage
1101 .. 1 "A, VIL=QV, VIH=VOO
Voo=5.QV
Voo=1QV
'.
Voo=15V
4.95
9.95
14.95
5-128
Max
25·C.
Min
Typ
85'C
Max
Min
Units
Max
20.
40.
80.
0..0.1
Q.Q1.
0..0.2
20.
40.
80.
150.
30.0.
60.0.
"A
"A
"A
0..0.5
0..0.5
0..0.5
0.
0.
0.
0..0.5
0..0.5
0..0.5
0..0.5
0..0.5
0..0.5
V
V
V
4.95
9.95
14.95
5.0.
10.
15
4.95
9.95
14.95
V
-.\VV
DC Electrical Characteristics
CD4043BC/CD4044BC (cont'd)
-40°C
Sym
Parameter
25°C
Units
Min
Max
Min
Typ
Max
2.25
4.5
6.75
1.5
3.0
4.0
Low Level
Input Voltage
1101"
VIH High Level
Input Voltage
1101"
10l Low Level
Output Current
(Note 3)
Vil = OV, VIH = Voo
Voo = 5.0V, Vo = 0.4 V
Voo=10V, Vo=0.5V
Voo=15V, Vo=1.5V
Vil - OV, VIH = Voo
Voo;5.0V, Vo=4.6V
Voo=10V, Vo=9.5V
Voo=15V, Vo=13.5V
-0.52
-1.3
-3.6
-0.44 -0.32
-1.1
-0.8
-3.0
-2.4
Voo = 15V, VIN = OV
Voo=15V, VIN=15V
-0.3
0.3
-0.3
0.3
Vil
10H High Level
Output Current
(Note 3)
liN
Input Current
85°C
Conditions
11'A
Voo = 5.0V, Vo = 0.5V or 4.5V
Voo = 10V, Vo = 1.0V or 9.0V
Voo=15V, Vo=1.5V or 13.5V
11'A
Voo = 5.0V, Vo =0.5V or 4.5V
Voo = 5.0V, Vo = 1.0V or 9.0V
Voo=15V, Vo=1.5Vor 13.5V
AC Electrical Characteristics
1.5
3.0
4.0
3.5
7.0
11
3.5
7.0
11
0.52
1.3
3.6
0.44
1.1
3.0
0.88
2.2
6.0
Min
Max
1.5
3.0
4.0
3.5
7.0
'11
V
V
V
0.36
0.9
2.4
mA
mA
mA
-0.36
-0.9
-2.4
mA
mA
mA
-1.0
1.0
I'A
I'A
TA = 25"C, C L = 50 pF, RL = 200 k, Input tr = tf = 20 ns, u'nless otherwise noted.
Typ
Max
Units
tpLH, tpHL Propagation Delay S or R to Q
Voo=5.0V
Voo=10V
Voo=15V
175
75
60
350
175
120
ns
ns
ns
tpZH, tpHZ Propagation Delay Enable to Q (High)
Voo=5.0V
Voo = 10V
Voo=15V
115
55
40
230
110
80
ns
ns
ns
Symbol
V
V
V
Parameter
Conditions
Min
tpZL, tpLZ
Propagation Delay Enable to Q (Low)
Voo=5.0V
Voo = 10V
Voo=15V
100
50
40
200
100
80
ns
ns
ns
tTHL, tTLH
Transition Time
Voo=5.0V
Voo= 10V
Voo= 15V
100
50
40
200
100
eo
ns
ns
ns
two
Minimum SET or RESET Pulse Width
Voo=5.0V
Voo=10V
Voo=15V
80
40
20
160
80
40
ns
ns
ns
C IN
Input Capacitance
5.0
7.5
pF
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed; .they are not
meant to imply that the devices should be operated at these limits. The tables of "Recommended Operating Conditions" and
"Electrical Characteristics" provide conditions for actual device operation.
Note 2: VSS = 0 V unless otherwise specified.
Note 3: 10H and 10L are tested one output at a time.
.
I
.5·129
Timing Waveforms
CD4043B
CD4044B
20ns
J,.,,""""-------
Voo
SET
SET
VOO
VSS
VSS
VOO
RESET
RESET
VSS
VSS
VOU
YoO
VSS
VSS
TLlF/5967·5
TUFI596N!
tPLH
Enable Timing
,..-----"'"
-:
>H~t
____
ENABLE
~~U%
t~:O~~_
-
VOO
~;..~:
~ VsS
~f.-50%tPLZ::
90%
_____
VOO
~
10%
VsS
TLIF/5967·7
5·130
.--------------------------------------------------------,n
c
~National
S
ru
~ Semiconductor
i:
n
CD4046BM/CD4046BC Micropower Phase-Locked Loop
i
General Description
The CD4046B micro power phase-locked loop (PLL) consists of a low power, linear, voltage-controlled oscillator
(VCO), a source follower, a zener diode, and two phase
comparators_ The two phase comparators have a common signal input and a common comparator Input_ The
signal input can be directly coupled for a large voltage
signal, or capacitively coupled to the self-biasing amplifier at the signal input for a small voltage slgnal_
Phase comparator I, an exclusive OR gate, provides a
'digital error signal (phase compo lOut) and maintains 90'
phase shifts at the VCO center frequency. Between signal input and comparator input (both at 50% duty cycle),
it may lock onto the signal input frequencies that are
close to harmonics of the VCO center frequency.
Phase comparator II is an edge-controlled digital memory
network. It provides a digital error signal (phase compo II
Out) and lock-in signal (phase pulses) to indicate a locked
condition and maintains a 0' phase shift between signal
Input and comparator input.
The INHIBIT input, when high, disables the VCO and
source follower to minimize standby power consumption.
The zener diode Is provided for power supply regulation,
if necessary.
Features
3.0Vto 18V
• Wide supply voltage range
70l'W (typ.) at
fa =10kHz, Veo = 5V
• Low dynamic
power consumption
1.3MHz (typ.) at Vee = 10V
• VCO frequency
0.06%I·C at Vee = 10V
• Low frequency drift
with temperature
1% (typ.)
• High VCO linearity
Applications
• FM demodulator and modulator
• Frequency synthesis and multiplication
• Frequency discrimination
The linear voltage-controlled oscillator (VCO) produces
an output signal (VCO Out) whose frequency is determined by the voltage at the VCO IN input, and the capacitor and resistors connected to pin C1A, C1 B , Rl and R2.
• Data synchronization and conditioning
The source follower output of the VCOIN (demodulator
Out) Is used with an external resistor of 10 kQ or more.
• FSK modulation
• Voltage-to-frequency conversion
• Tone decoding
• Motor speed control
Block and Connection Diagrams
Dual-In-Line Package
16
PHASE PULSES
Voo
PHASE COMP lOUT
COMPARATOR IN
A3
VCD OUT
INHIBIT
C1
LOW
1+-"1---r-<>-----~ :~EA
Vss
Vss . . .~A2,..,.~1~21-1
TOP VIEW
TLfF/5968-2
INHIBITO"':~-.....- - - - I
Order Number CD4046BMJ or CD4046BCJ
See NS Package J16A
Vss
ZENER
TLIF/5968-1
FIGURE',
5-131
Order Number CD4046BMN or CD4046BCN
See NS Package N16E
m
n
Absolute Ma,ximum Ratings
Recommended Operating Conditions
(Notes 1 and 2)
(Note 2)
Voo OC Supply Voltage
VIN Input Voltage
Voo OC Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
C04046BM
C04046BC
-{).S to +18 VOC
-{).S to VOO + O.S VOC
TS Storage Temperature Range
-65°C to +150°C
Po Package Dissipation
SOOmW
TL Lead Temperature (Soldering, 10 seconds)
260°C
3to ISVOC
OtoVOOVOC
-SSOC to +12So C
-40° C to +8So C
"-
DC Electrical Characteristics CD4046BM (Note 2)
-55°C
Parameter
Sym
Min
100 Quiescent Device Current
Max
125°C
25°C
Conditions
Typ
Min
Min
Max
Max
Units
~N5=VOO, ~N14=VO~
PIN 3, 9= VSS
VOO= 5V
VOO= 10V
VOO=15V
5
10
20
0.005
0.01
0.015
5
10
20
150
300
600
pA
pA
p.A
PIN 5 = VOO, PIN 14 = Open
PIN 3,2 = VSS
VOO = 5V
VOO= 10V
VOO=15V
45
450
1200
5
20
50
35
350
.900
185
650
1500
p.A
p.A
p.A
VOL Low Level Output Voltage
VOO= 5V
VOO = 10V
VOO = 15V
0.05
0.05
0.05
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
VOH High Level Output Voltage
VOO = 5V
VOO= 10V
VOO=15V
VIL Low Level Input Voltage
Comparator and Signal In
VOO = SV, Vo = O.SV or 4.SV
VOO= 10V VO= lVor9V
VOO= 15V VO= 1.5Vor13.5V
VIH High Level Input Voltage
Comparator and Signal In
VOO = 5V,
= O.SVor 4.5V
VOO=10V, o=lVor9V
VOO=15V, Vo=1.5Vor13.5V
3.5
7.0
11.0
3.5
7.0
11.0
2.75·
5.5
8.25
3.5
7.0
11.0
V
V
V
IOL Low Level Output Current
(Note 4)
VOO=SV, VO=OAV
VOO = 10V, Va = O.SV
VOO = 1'5V, Vo = 1.5V
0.64
1.6
4.2
O.Sl
1.3
0.88
2.25
8.8
0.36
0.9
2.4
mA
mA
mA
IOH High Level Output Current
(Note 4)
VOO= 5V, VO=4.6V
VOO = 10V, Va = 9.5V
VOO = 15V, Vo = 13.5V
-0.64
-1.6
-4.2
-O.Sl
-1.3
-0.88
-2.25
-8.8
-0.36
-0.9
-2.4
mA
mA
mA
,
liN
Input Current
I
4.95
9.95
14.95
ve
All Inputs Except Signal Input
VOO=14V, VIN=OV
VOO=15V, VIN=15V
CIN
I nput Capacitance
Any Input, (Note 3)
PT
Total Power Oissipation
fo = 10kHz, Rl = 1 MU
R2 =~, VCOIN = VOO/2
VOO= 5V
VOO= 10V
VOO=15V
a
4.95
9.95
14.95
l.S
3.0
4.0
2.25
4.S
6.25
304
-304
-0.1
0.1
5
10
15
-10-5
10-5
0.07
0.6
2.4
5·132
4.95
9.95
14.95
1.5
3.0
4.0
-0.1
0.1
V
V
V
1.5
3.0
4.0
V
V
V
-1.0
1.0
p.A
p.A
7.5
pF
mW
mW
mW
DC Electrical Characteristics
CD4046BC (Note 2)
_40°C
Sym
Parameter
100 Quiescent Device Current
VOL Low Level Output Voltage
1
VOH High Level Output Voltage
VIL Low Level Input Voltage
Comparator and Signal In
Conditions
Min
Max
25°C
Min
85°C
Typ
Max
Min
Max
Units
PIN 5 = VOO, PIN 14 = VOO,
PIN 3,9 = VSS
VOO= 5V
VOO= 10V
VOO=15V
PIN 5 = VOO, PIN 14 = Open,
PIN 3,9 = VSS
VOO= 5V
VOO= 10V
VOO=15V
20
40
80
0.005
0.01
0.015
20
40
80
150
300
600.
IlA
p.A
p.A
70
530
1500
5
20
50
55
410
1200
205
710
1800
IlA
IlA
IlA
VOO= 5V
VOO= 10V
VOO=15V
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
4.95
9.95
14.95
VOO = 5V
VOO= 10V
VOO=15V
VOD~5V, VO~0.5Vor4.5V
4.95
9.95
14.95
2.25
4.5
6.25
1.5
3.0
4.0
VOO = 10V Va = I.Var 9V
VOO = 15V, Va = 1.5Var 13.5V
5
10
15
4.95
9.95
14.95
1.5
3.0
4.0
V
V
V
V
V
V
1.5
3.0
4.0
V
V
V
VIH High Level Input Voltage
Comparator and Signal In
VOO = 5V, Vo = 0.5V or 4.5V
VOO = 10V, Vo=IVar9V
VOO = 15V, Vo = 1.5Var 13.5V
3.5
7.0
11.0
3.5
7.0
1.. 0
2.75
5.5
8.25
3.5
7.0
1..0
V
V
V
IOL Low Level Output Current
(Note 4)
'{DO = 5V, VO=O.4V
VOO = 10V, Vo = 0.5V
VOO = 15V, Vo = 1.5V
0.52
1,3
3.6
0.44
1.1
3.0
0.88
2.25
8.8
0.36
0.9
2.4
mA
mA
mA
IOH High Level Output Current
VOO = 5V, Va = 4.6V
VOO= 10V, Va = 9.5V
VOO = 15V, VO=13.5V
-0.52
-1.3
-3.6
-0.44
-'1.1
-3.0
-0.88
-2.25
-8.8
-0.36
-0.9
-2.4
mA
mA
mA
(Note 4)
liN
Input Current
All Inputs Except Signal Input
VOO=15V, VIN = OV
VOO = 15V, VIN = 15V
CIN
Input Capacitance
Any Input, (Note 3)
PT
Total Power Dissipation
fa = 10 kHz, Rl = 1 M!l
R2 = -, VCOIN = VOO/2
VOO = tv
VOO = 10V
VOO = 15V
-0.3
0.3
-0.3
0.3
7.5
0.07
0.6
2.4
Note 1: "Absolute Maximum Ratings" are those
the devices should be operated at these- limits.
-10-5
lQ-5
-1.0
1.0
p.A
p.A
pF
mW
mW
mW
value~ beyond whIch the safety of the deVice cannot ,be guaranteed.
They are not meant to Imply that
The table of "Recommended Operating Conditions" and "Electrical Characteristics" provides conditions for
actual deVice operation.
Note 2: VSS = OV unless otherwise specified.
Note 3: Capacitance IS guaranteed by pen odic testmg.
Note 4: IOH and IOL are tested one output at a time.
5·133
(J
CD
I
AC Electrical Characteristics CD4046BM/CD4046BC fA = 25°C, CL = 50pF
Symbol
iCD
ic
I
Parameter
I Min I
Conditions
Typ
Max
Units
VCOSection
(J
Operating Current
100
fMAX
Maximum Operating Frequency
(J
Linearity
Temperature·Frequency Stability
No Frequency Offset, fMlN =0
Frequency Offset, fMIN '" 0
VCOIN
Input Resistance
VCO
Output Outy Cycle
~ VCO Output Transition Time
tTHL
fo = 10kHz, Rl = I MU
R2 = -, VCOIN = VOO/2
VOO= SV
VOO= 10V
VOO= ISV
Cl - 50 pF, Rl - 10kU,
R2 = -, VCOIN = VOO
VOO= SV
VOO= 10V
VOO= 1SV
VCOIN = 2.SV =to.3V,
Rl:> 10kU, VOO = SV
VCOIN = SV ±2.SV,
Rl:>4ookU, VOO = 10V
VCOIN = 7.SV ±SV,
Rl:>1 MU, VOO= ISV
%f'Ccxl/f. VOO
R2=VOO=SV
VOO= 10V
VOO= ISV
VOO= SV
VOO'; 10V
VOO=ISV
VOO=
VOO=
VOO=
VOO=
VOO=
VOO=
VOOVOO=
VOO=
20
90
200
0.4
0.6
1.0
IJ.A
IJA
MHz
MHz
MHz
0.8
1.2
1.6
I
%
I
%
I
%
0.12-0.24
0.04-0.08
0.01S-0.03
0.06-0.12
O.OS-O.1
0.03-0.06
%f'c
%/oC
%/oC
%1 C
%/oC
%/oC
106
106
106
50
50
50
-90
SV
10V
15V
SV
10V
1SV
SV
10V
ISV
IJA
"
SO
4S
200
100
80
M12
M12
M12
%
%
~
ns
ns
ns
Phase Comparators Section
RIN Input Resistance
Signal Input
Comparator Input
AC·Coupled Signal Input Voltage
Sensitivity
1
0.2
0.1
VOO= SV
VOO = 10V
VOO=1SV
VOO= 5V
VOO= 10V
VOO= 15V
CSERIES = 1000 pF
f = 50 kHz
VOO= 5V
VOO = tov
VOO= 15V
3
M!!
M!!
M!!
Mil
Mil
M12
0.7
0.3
106
106
106
200
400
700
400
800
1400
mV
mV
mV
Demodulator Output
VCOIN VOEM
Offset Voltage
Linearity
RS:>10kU,VOO=SV
RS :>10 k12, VOO = 10V
RS:> 50 kU, VOD = ISV
RS:>SOk12
VCOIN = 2.S ±0.3V, VOO = SV
VCOIN = S ±2.SV, VDO = 10V
VCOIN = 7.S ±5V, VOO = 1SV
I.S0
I.S0 ,
1.50
'2.2
2.2
2.2
0.1
0.6
0.8
V
V
V
%
%
%
Zener DIode
Vz
RZ
Zener Diode Voltage
C04046BM
CD4046BC
Zener Dynamic Resistance
6.7
6.3
IZ = SOIJA
IZ= lmA
5·134
7.0
7.0
100
7.3
7.7
V
V
12
.-------------------------------------------------------------------'0
Phase Comparator State Diagrams
I
OJ
PHASE COMPARATOR I
INPUT STATE
COMPARATOR
IN
~
SIGNAL
IN
s:
o
o
~
11
gc:n
10
OJ
o
I
PHASE COMP lOUT
I
0
1
PHASE COMPARATOR II
INPUT STATE
COMPARATOR
tiN.
SIGNAL
IN
TRI·STATE,!)
PHASE COMP II OUT
PHASE PULSES
FIGURE 2
TUF15968-3
Typical Waveforms
PHASE COMPARATOR I
SIGNAll~
COMPARATOR IN
PHASE COMP lOUT
VCOIN
(lOW PASS FilTER OUTPUT)
VOO
VSS
-r---1
...J
L-Jr---1'---
VOH - r - - - 1
r---1
VOl----l
L-J
L.....
n
VOH-n
VOl...J L.J
W
n
n
L.J L.....
~::~
TlIFI59684
FIGURE 3. Typical Waveform Employing Phase Comparator I in Locked Condition
PHASE COMPARATOR II
SIGNAllN
VOD~
VSS
COMPARATOR IN
VOH
VOL
-r---1
r---1
--I
L-J
L.....
PHASE PULSES. VOH - - , . - - - - ,
VOl----U
U
r--
PHASE COMP II 0 UT V O H = r - - - - - - t r VOL
VCOIN VOH~
(lOW PASS FilTER OUTPUT) VOl-
TLIFf5968-5
FIGURE 4. Typical Waveform Employing Phase Comparator" in !-ocked Condition
5·135
Typical Performance Characteristics
Typical Frequency Offset vs
Cl for R2 = 10 k!l. 100 k!l
and 1 M!l
Typical Center Frequency vs
Cl for Rl = 10 k!l. 100 k!l
and 1 M!l
10 7
g
>
":>
::i
107
106
g
105
~
:;i 104
e:
'"....w
~
_0
101
I
104
e:
103
'"
102
I
~
1
10-5 10-4 10-3 10-2 10-1
10 102
Cl - VCO TIMING CAPACITOR I"FI
FIGURE 5a
Typical
106
10 5
~
:;i
103
102
Typical fMAX/fMIN vs
R2/Rl
101
10-5 10-4 10-3 10-2 10-1 1
10
102
0.01
0.1
FIGURE 5b
TLlFI5968-6
veo Power Dissipation
FIGURE 5c
TLIF/5966·7
Typical veo Power Dissipation
at fMIN vs R2
at Center Frequency vs R1
102
10
R2/Rl
Cl - VCO TIMING CAPACITOR ("FI
TliF/S96s-a
Typical Source Follower
~
Power" Dissipation vs RS
7
!:
"'§j§'FI'fF~§l~V~;ZS~
- 10 F
TA=25c C
~
106
Ci
105
'"~
104
~
~~~
=
~
103
SUPPLY
VOLTAGE
VOO' 15V
102
~
~
I
,p
Rl (kill
~ ~-'VCOIN = VOO/2, HI = R2 = 00
10
10t:::rt
IlIillllllillll!l:j!l1
5VI==FF
110
102
R21krlJ
FIGURE 6a
FIGURE 6b
TLIFI5968·9
103
104
RS-(knl
FIGURE6c
TLIFI5966-10
TlIF/5968-"
Typical veo Linearity vs
Rl and Cl
103
10 2
102
g
g
~
"':5
>
....
10
"':5
z
TA =25"C
VOO = 15V, VCOIN = 7.5V ±5V, R2 =00
E= % LINEARITY = 10 - f(7.5VJ
'0
~;50PF
100pF
10
0.001 ~F
0.01, 0.1 ~F
'"
:::;
:::;
fo =
0.1
10-1
1(2.51/1 + fl7.5VJ
2
+-+-H-HN"'"=I
fo'"
0.1
10-1
10
Rl (k!lJ
1(2.5VJ + f112.5VJ
2
10
Rl (k!ll
TLJFI5968-12
TUFI5968-13
FIGURE 7
Note, To obtain approximate total power dissipation of PLL system for no-signal input: Phase Comparator I, Po (Total)
Po (RS); Phase Comparator II, Po (Total) = Po (fMINI.
5·136
= Po (fo ) + Po
(fMIN) +
o
c
Design Information
In addition to the given design information, refer to
Figure 5 for Rl, R2 and C1 component selections_
This information is a guide for approximating the value
of external components for the CD4046B in a phaselocked-loop system_ The selected external components
must be within the following ranges: R 1, R2 2 10 kn,
RS2 10 kn, C12 50 pF_
VCO WITHOUT OFFSET
R2 =
~0 '"rL '·-60
21L
fo
'MIN
21l
.
I:D
o
VCO WITH OFFSET
R2= =
0-----.,
AsfABlEo.::---~----.,
+ TRIGGER
0"-.....-::---...,
-TRIGGER
EXT RESET
TLIFISOO9-3
*Special input protection circuit to permit larger input-voltage swings.
Truth Table
TERMINAL CONNECTIONS
FUNCTION
INPUT PULSE
TOVOO
Astable Multivibrator
Free-Running
True Gating
Complement Gatfng
Monostable Multivibrator
Positive-Edge Trigger
Negative-Edge Trigger
Retriggerable
External Countdown'
TOVss
4,5,6,14 7,8,9,12
4,6,14
7,8,9,12
5,7,8,9, 12
6,14
4,14
4,8,14
4, 14
14
5,6,7,9,12
5,7,9,12
5,6,7,9
5, 6, 7, 8, 9, 12
TO
5
4
8
6
8,12
(See Figure)
OUTPUT PULSE
FROM
10, II, 13
10, II, 13
10, II, 13
10,11
10,11
10,
~~i~! SL
(See Figure)
TLlFI5969-4
5-141
tA(10, 11)
tA(13)
=4.40
= 2_20
tM(10, 11)
Implementation of External Countdown Option,
0-----------'
PERIOD OR
PULSE WIDTH
RC
RC
= 2.48 RC
Ii
Note: External resistor between terminals 2 and 3. External capacitor between terminals 1 and 3.
* Typical
TYPICAL OUTPUT
(See Figure)
Typical Performance Characteristics
a,
a,
§!
....
~
0
"
15
~
.
0
0
2
10
'd"
-I
1\8
Monostable Mode Operation
~
~ t- l-iAoIZ5 C-
..
I"'"
!.
'"
t-
!O
t'-.
I~
-5
~
1\
10
B ,
t
E
5-
"..,..I'.
iA .125·b
I\A
'"~
1\
II
15
~
1
1\.1i\.
'"~
0
0
1\
kt
t
i.
Typical a,
Pulse Width
Accuracy vs Supply Voltage
Typical a,
Osc aut Period
Accuracy vs Supply Voltage
(Astable Mode Operation)
1-1-
1-1-
~
0
....."
~
E
....
0
1"'''I'\.
-5
w
~
10
10
15
TUF/5969-8
TLIF/5969·5
R
tM
C
22k
100 pF
B
7 ItS
C
60 ItS
22k
220k
100pF
100 pF
0
E
550 ItS
'220k
1000 pF
5.5 ms
2.2M
1000 pF
10 pF
B
22k
220k
0
1 kHz
220k
1000 pF
E
100 Hz
2.2M
1000 pF
100 pF
a
a, a and Osc Out
Typical
C.
10 pF
2 ItS
22k
100 kHz
R'
A
A 1000 kHz
C 10 kHz
15
VOO - SUPPLY VOLTAGE IV)
VOO - SUPPLY VOLTAGE IV)
fO,a
r-
J"..
Typical a and Pulse Width
Accuracy vs Temperature
Period Accuracy vs Temperature
Astable Mode Operation
.
Monostable Mode Operation
g
10
!~_
15
'"~
10
t
"
~
"
~
-5
-5
j;
~ -10
-10
-65 -35
-5
25
55
85
115 145
-65 -35 -5 25 55 85 115 145
TA - AM81ENTTEMPERATURE I'C)
TA - TEMPERATURE (UCI
TLIFI59B9-8
TUFI5969-7
fa,a
R
R
C
A
2 liS
22k
10 pF
22k
100 pF
B
7 ItS
22k
100 pF
220k
100pF
C
60 ItS
220k
100 pF
220k
1000 pF
0
5501'"
220k
1000 pF
22k
B 100 kHz
C 10 kHz
1 kHz
tM
10 pF
A 1000 kHz
0
C
Timing Diagram
Monostable Mode
Astable Mode
OSCOUT~
Q~
I
+TRIGGER
I
..J"l____..JnL____
OSCOUT~
~-tA~
L
TUF/5969·9
TUFf5969-10
Rotrigger Mode
+TRIGGER
RETRIGGEO
n
n'
---I L......J
~
'OSCOUT~
L
TUF/5969-11
5-142
o
i
o
i.
~National
~ Semiconductor
OJ
s:
CD4048BM/CD4048BC TRI·STATE® Expandable
8-Function 8-lnput Gate
OJ
o
General Description
Features
The CD4048BM/CD4048BC is a progammable 8·input
gate. Three binary control lines Ka , Kb , and Kc determine
the 8 different logic functions of the gate. These func·
tions are OR, NOR, AND, NAND, OR/AND, OR/NAND,
AND/OR, and AND/NOR. A fourth input, K.J, is a TRI·
STATE control. When K.J Is high, the output Is enabled;
when,K.J is low, the output Is a high Impedance. This
feature enables the user to connect the device to a com·
mon 'bus line. The Expand input permits the user to in·
crease the number of gate inputs. For example, two 8·
input CD4048's can be cascaded into a 16·input multi·
function gate. When the Expand input is not used, it
should be connected to Vss. All inputs are buffered and
protected against electrostatic effects.
• Wide supply voltage range
3.0Vto 15V
0.45 Voo (typ.)
• High noise immunity
• High sink and source current capability
• TTL compatibility
drives 1 standard TTL load
at Vco...=5V,
over full temperature range
• Many logic functions in one package
Logic Diagram
Vee
= (16)
VSS = (8)
TlIF1597()..1
Dual·1 n-Line Package
Connection Diagram
INPUTS
I..
fUNCTION CONTROL
---------,
K~
15
14
1l
12
11
Kc
10
Order Number CD4048BMJ
or CD4048BCJ
See NS Package J16A
r-
Order Number CD4048BMN
or CD404BBCN
See NS Package N16E
1
OU:PUT
2
TRI~~ATE
CONTROL
)
4
,
INPUTS
TOPVIEW
5·143
1
6
.....
, H_ _ _- - - - - '
I'
Kb
Vss
FUNCTION
CONTROL
TUF/S970·2
(,)
a:I
~
C
o
ia:I
~
Absolute Maximum Ratings
Recommended Operating Conditions
(Notes 1 and 2)
(Note 2)
voo Supply Voltage
VOO Supply Voltage
VIN Input Voltage
-o.5V to +1 BV
VIN Input Voltage
-o.5V to VOO + 0.5V
--65°C iO +150°C
TS Storage Temperature Range
Po Package Dissipation
500mW
TL Lead Temperature. (Soldering, 10 sec~ndsl
260°C
3V to 15V
OV to VOO
T A Operating Temperature Range
-55°C to +125°C
-40°C to +85°C
C0404BBM
C0404BBC
C
o
DC Electrical Characteristics CD4048BM (Note 2)
SYM:
100
VOL
VOH
• VIL
VIH
lac
PARAMETER
Quiescent Device Current
Low Level Output Voltage
High Level Output Voltage
Low Level Input Voltage
High Level Input Voltage
Low Level Output Current
(Note 3)
10H
-55°C
CONDITIONS
MIN
liN
MIN
TYP
MAX
MIN
MAX
UNITS
VOO = 5V
5.0
0.01
5.0'
150
/lA
VOO= 10V
10
0.01
10
300
/lA
VOO = 15V
20
am
20
600
/lA
V
1101 < 1 /lA. VIH = VOO, VIL = OV
VOO= 5V
0.05
0
0,05
0.05
VOO = 10V
0.05
0
0.05
0.05
V
VOO = 15V
0.05
a
0,05
0,05
V
1I0i < 1 /lA, VIH = VOO, VIL = OV
VOO = 5V
4,95
4.95
5
4.95
V
VOO = 10V
9.95
9.95
10
9.95
V
VOO= 15V
14.95
1.4.95
15
14.95
V
1I01<1/lA
VOO = 5V, Va = 0.5V or 4,5V
1.5
2,25
1.5
1.5
VOO = 10V, Va = 1V or 9V
3.0
4.5
3.0
3,0
V
VOO = 15V, Va = 1.5V or 13,5V
4.0
6,75
4.0
4.0
V
V
1101<1/lA
VOO = 5V, Va = 0.5V or 4,5V
3.5
3.5
2,75
3.5
V
VOO = 10V, Va = 1V or 9V
7.0
7.0
5.5
7.0
V
VOO= 15V, VO= 1.5Vor 13.5V
11.0
11,0
B.25
11.0
V
VIH = VOO: VIL = OV
VOO=5V, V6=0.4V
2.B
2,3
4.0
1.6
mA
VOO = 10V, Va = 0.5V
6.4
5.2
11
3.6
mA
VOO = 15V, Va = 1.5V
14
11,5
23
8.0
mA
High Level Output Current
VIH = VOO, VIL = OV
(Note 3)
VOO = 5V,
Va = 4.6V
-2.B
-2,3
-4.0
-1.6
mA
Voo= 10V, VO=9,5V
-6.4
-14
-5.2
-11
-3.6
mA
-11.5
-23
-B.O
VOO = 15V, Va = 13,5V
IOZ
12Soc
25°C
MAX
-0,2
TAI·STATE Leakage
VOO= 15V, VO=OV
Current
VOO = 15V, Va = 15V
0.2
0.002
0.2
Input Current
VOO = 15V, VIN = OV
-0.1
-10-5
0.1
10-5
VOO = 15V, VIN = 15V
mA
--{).002 -{).2
-2
/lA
2
/lA
--{).1
-1.0
/lA
0.1
1.0
/lA
DC Electrical Characteristics CD4048BC (Note 2)
SYM
PARAMETER
MIN
100
VOL
Quiescent Device Current
Low Level Output Voltage
MAX
8SoC
2SoC
-40°C
CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
VOO = SV
20
0.01
20
lS0
/lA
VOO = 10V
40
0,01
40
300
/lA
VOO = 15V
BO
am
BO
600
/lA
VOO=5V
0.05
0.05
V·
0.05
0.05
0.05
V
VOO = 15V
0.05
a
a
a
0.05
VOO= 10V
0,05
0.05
V
1101 < 1 /lA, VIH = VOO, VIL = OV
5·144
DC Electrical Characteristics (Cont'd.) CD4048BC (Note 2)
VOH
VIL
High Level Output Voltage
Low Level Input Voltage
CONDITIONS
High Level Input Voltage
10H
ITL
liN
MIN
TYP
8SoC
MAX
MIN
MAX
UNITS
4.95
4.95
5
4.95
V
Voo = 10V
9.9S
9.9S
10
9.95
V
Voo = lSV
14.9S
14.9S
lS
14.95
V
1101< lfJ.A
1.5
2.25
1.5
1.5
V
VOO = 10V. Va = 1V or 9V
Va = 0.5V or 4.5V
3.0
4.5
3.0
3.0
V
VOO = 15V. Va = 1.5Vor 13.5V
4.0
6.75
4.0
4.0
V
1101< 1 fJ.A
3.5
3.5
2.75
3.5
V
VOO = 10V, Va = lV or 9V
7.0
7.0
5.5
7.0
V
VOO = 15V, Va = 1.5Vor 13.5V
11.0
11.0
8.25
11.0
V
Va = 0.5V or 4.5V
Low Level Output Current
VIH = VOO, VIL = OV
(Note 31
VOO = 5V,
Va = OAV
2.3
2.0
4.0
1.6
rnA
VOO = lOV, Va = 0.5V
5.2
4.5
11
3.6
rnA
VOO = 15V, Va = 1.5V
11.5
9.8
23
8.0
rnA
High Level Output Current
VIH = VOO, VIL = OV
(Note 3)
VOO = 5V,
Va = 4.6V
-2.3
-2.0
-4.0
-1.6
rnA
VOO = 10V, Va = 9.5V
-5.2
-4.5
-11
-3.6
rnA
VOO = 15V, Va = 13.5V
-11.5
-9.8
-23
-8.0
rnA
-0.6
-{l.005
-0.6
-2
VOO = 15V, Va = 15V
0.6
0.005
0.6
2
VOO = 15V, VIN = OV
-0.3
-10-5
-0.3
-1.0
iJA
0.3
10-5
0.3
1.0
iJA
TR I·STATE Leakage
VOO= 15V, VO=OV
Current
Input Current
MAX
1101 < 1 fJ.A. VIH = Voo. VIL = OV
Voo = SV,
10L
MIN
Voo = 5V
Voo = SV.
VIH
2Soc
-40°C
PARAMETER
SYM
VOO = 15V, VIN = 15V
iJ A
iJA
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The tables of uRecommended Operating Conditions" and IIElectrical Characteristics" provide
conditions for actual device operation.
.
Note 2: VSS = OV unless otherwise specified.
Note 3: IOH and IOL are tested one output at a time.
AC Electrical Characteristics
T A =25°C, CL=50pF,
RL =200kQ,
and t r =t,=20ns,
unless otherwise specified
SYMBOL
tPHL, tpLH
PARAMETER
Propagation Delay Time
tPLZ, t PHZ Propagation Delay Time, Kd to
tPZL, tPZH
tTHL, tTLH
TYP
MAX
UNITS
VOO = 5V
CONDITIONS
MIN
425
850
ns
VOO = 10V
200
400
ns
VOO = 15V
160
320
ns
RL = 1.0kn
High Impedance (From Active
VOO = 5V
175
350
ns
Low or High Level)
VOO = 10V
125
250
VOO = 15V
100
200
ns
ns
Propagation Oelay Time, Kd to
RL = 1.Okn
Active High or Low Level
VOO = 5V
225
450
ns
(From High Impedance)
VOO = 10V
100
200
ns
VOO = 15V
70
140
ns
VOO = 5V
100
200
ns
Output Transition Time
CIN
I nput Capacitance
COUT
TRI·STATE Output
VOO = 10V
50
100
ns
VOO = 15V
40
80
ns
Any Input
5
7.5
pF
22.5
pF
Capacitance
5·145
o
III
§
Truth Table
OUTPUT
FUNCTION
o
o
:EIII
~
o
CONTROL INPUTS
Ka
Kb
Kc
Kd
BOOLEAN
EXPRESSION
NOR
J=A+B+C+o+E+F+G+H
OR
J=A+B+C+o+E+F+G+H
OR/AND
J = (A + B + C + DI " (E + F + G + HI
OR/NAND
J=(A+B+C+ol" (E+F+G+HI
AND
J=A"B"C"o"E"F'G'H
NAND
J=A'B'C'o'E"F'G'H
ANo/NOR
J = (A ' B ' C ' 01 + (E ' F " G ' HI
AND/OR
J = (A ' B ' C ' 01 + (E ' F ' G " HI
Hi-Z
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
1
1
0
1
X
X
X
1
1
1
UNUSED
INPUTS
1
1
1
VSS
1
1
1
VSS
1
1
Voo
VSS
VSS
VDo
VDo
VDD
X
0
- . logIC: 0 - low level, 1 = hIgh level, X - "relevant, EXPAND mput tIed to VSS.
PosItIve
AC Test Circuits and Switching Time Waveforms
Logic Propagation Delay Time Tests
VOo
Voo
16
INPUT
OV
INPUTS
OUT J
T
-=
Voo
CL
OUTPUT J
OV
'THL
TUF/597Q-3
TLIFI597().4
TRI-STATE Propagation Delay Time Tests
voo
voo
Voo
TRI-STATE
Kd
CONTROL
RL
TRI-STATE
Kd
CONTROL
2
OUT J
OUTPUT J
CL
"*
-=
TlIFI5971).5
Voo
TlIF/5970·6
Voo
TCR~~i~~~
TRI·STATE
CONTROL Kd
Kd
2
OV
g
2
=
Output Transition Time vs
,.
600
500
>=
400
z~ 200
i
...
200
~
100
~
1::
~
100
I
:c
~
VCC < 5V
;i
300
~
~
300 . - - - - - , - - - , - - - , - - - - - ,
~
'>=
;3
,Load Capacitance
.g
:c
I:'
0
0
50
100
150
200
CL - LOAD CAPACITANCE (pFI
50
200
100
CL - LOAD CAPACITANCE (pFI
Tl/FI5970-10
TlIF/597D-9
5-146
Basic Logic Configurations
NOR
NAND
OR
A~.
•
,
C
D
EXPA.~
=001
TUFI597CJ.l1
= 101
TUFf597().12
AND
TUF/597o-13
OR/AND
OR/NAND
.~
.j~'
EXPA.D--------r-~
EXPAND---------~
=100
=011
TUF/597().15
TLIF/597().14
TL/F/597().16
AND/OR
AND/NOR
E X P A N D - - - - - - - - -.....
E X P A N D - - - - - - - - -.....
= 111
= 110
·A
TUFI5970-IB
TLIFI597().17
Actual Circuit Configurations
NOR
OR
EXPAND-----..:;;;:j
NAND
EXPAND-------I
EXPAND
------:::i
=001
TUFI597o-19
= 101
TLIFI597()'21
TLlF/S970-20
AND
OR/AND
EXPANO------i
OR/NAND
f~PAND------i
EXPAND------i
E
E
F
=100
=010
AND/OR
TUFI5970-24
AND/NOR
fXPAND-----..:;;;:j
= 111
= 011
TUF/597().23
TLlF/591'O-22
EXPAND-------I
= 110
TUF/59JO.25
5·147
TLlFI5970·26
o
m Truth Table for EXPAND Feature
§
c
o
:i
m
i
o
COMBINED
OUTPUT
FUNCTION
FUNCTION
NEEDED AT
EXPAND INPUT
NOR
OR
AND
NAND
OR/AND
OR/NAND
AND/NOR
AND/OR
OR
OR
NAND
NAND
NOR
NOR
AND
AND
OUTPUT BOOLEAN
EXPRESSION
J
J
J
J
J
J
J
J
(A + B + C + D + E + F + G + H) + (EXP)
(A + B + C + D + E + F + G + H) + (EXP)
(ABCDEFGH) • (EXP)
(ABCDEFGH) • (EXP)
(A + B + C + D) • (E + F + G + H) • (EXP)
(A + B + C 'I- D) • II: + F + G + H) • (EXP)
= (ABCD) + (EFGH) + (EXP)
= (ABCD) + (EFGH) + (EXP)
=
=
=
=
=
=
Note. Positive logic is assumed. (EXP) represents the logic level present at thelEXPAN 0 input.
Typical Applications of EXPAND Feature
16·lnput NOR Gate
OUTPUT
12·lnput OR/AND Gate
Voo
Voo
OUTPUT
voo
Xl
X2
X3
X4
Output = (A + B + C + D) • (E +
G + H) • (X 1 "" X2 + X3 + X4) F +
OuW~-A1+~+m+D1+El+F1+G1+
H1 + A2 + 62 + C2 + D2 + E2 + F2 + G2 + H2
TL.IF/5970-27
5·148
TLIF/597().28
o
c
~National
~c:
~ Semiconductor
to
is:
CD4049UBM/CD4049UBC Hex Inverting Buffer
CD4050BM/CD4050BC Hex Non-Inverting Buffer
o
General Description
Features
i
These hex buffers are monolithic complementary MOS
(CMOS) Integrated circuits constructed with N- and Pchannel enhancement mode transistors. These devices
feature logic level conversion using only one supply
voltage (Voo). The input signal high level (V1H ) can exceed
the Voo supply voltage when these devices are used for
logic level conversions. These devices are intended for
use as hex buffers, CMOS to DTLlTTL converters, or as
CMOS current drivers, and at Voo = 5.0V; they can drive
directly two DTLlTTL loads over the full operating temperature range.
3.0Vto 15V
• Wide supply voltage range
• Direct drive to 2 TTL loads at 5.0V over full temperature range
P
o
c:
• Hi~h source and sink current capability
• Special input protection permits input voltages greater
than Voo
• CMOS hex inverter/buffer
• CMOS to DTLlTTL hex converter
~
c
• CMOS current "sink" or "source" driver
g:
• CMOS high-to-Iow logic level converter
o
to
CD4050BM/C04050BC
Dual-In-Line Package
16
NC
14
15
Dual-In-Line Package
K= E
13
12
NC
"
L=F
16
lD
15'
NC
14
K =E
13
12
J= 0
11
10
• 2
voo
G=A
A
H=B
to
Applications
CD4049UBM/CD4049UBC
L'i'
8g:
is:
(5
Connection Diagrams
NC
to
I=C
Voo
G=A
A
H=B
Vss
1= C
TOP VIEW
TOP VIEW
Order Number CD4049UBMJ, CD4049UBCJ,
CD40S0BMJ or CD40S0BCJ
See NS Package J16A
Order Number CD4049UBMN, CD4049UBCN,
CD40S0BMN or CD40S0BCN
See NS Package N16E
,
5-149
TLIF15971·2
Absolute Maximum Ratings
Recommended Operating Conditions
(Notes 1 and 2)
(Note 2)
-o,6V to +18V
voo Supply Voltage
VIN' Input Voltage
-o,5V to +18V
VOUT Voltage at Any Output Pin
-o,5V to VOO + O,5V
TS Storage Temperature Range
~5°Cto+150°C
Po Package Oissipation
500mW
TL'Lead Temperetu!e (Soldering, 10 seconds)
26o"C
VOO Supply Voltage
VIN Input Voltage
VOUT Voltage at Any Output Pin
TA Oparating Temperature Range
C04049M, C04050BM
C04049C,C04050BC
3V to 16V
OV to 15V
Oto VOO
-55°C to +126"C
~oC to+86"c
,
\
DC Electrical Characteristics CD4049M/CD4050BM (Note 2)
SYM
100
VOL
PARAMETER'
Quiescent Device Current
Low Level Output Voltage
CONOITIONS
-55°C
.MIN
25°C
MAX
VOO = SV
VOO= 10V
VOO = 15V
VIL
High Level Output Voltage
Low Level Input Voltage
(C040S0BM Only)
VIL
Low Level Input Voltage
(C04049UBM Only)
VIH
IOL
IOH
VIH = Voo, VIL = 0,
lIol
o
c
8c.n
N
III
oc
pF
pF
pF
8c.n
0.2
pF
s>
110
140
70
pF
pF
pF
N
III
c
8c.n
Co)
III
s:
oc
RL =10 kn
Ils= 1 kHz
Vls=5Vp.p
VEE=VSI=OV
10V
0.04
%
8c.n
Co)
III
Frequency Response, Channel
"ON" (Sine Wave Input)
RL =1 kn, VEE=OV, VIS = 5Vp.p,
20 10glO VosIVIS = -3 dB
10V
40
MHz
Feedthrough, Channel "OFF"
RL =1 kfl, VEE=VSS=OV, VIS=5Vp_p,
20 10glO VosIVIS= -40 dB
10V
10
MHz
Crosstalk Between Any Two
Channels (frequency at 40.. dB)
RL =1 kfl, VEE=VSS=OV, VIS(A)=5Vp_p
20 IOg10 Vos(B)lVls(A) = - 40 dB (Note 3)
10V
3
MHz
Propagation Delay Signal
Input to Signal Output
VEE=VSS=OV
CL =50pF
OV
10V
15V
25
15
10
10V
65
5V
10V
15V
500
180
120
55
35 •
25
ns
ns
ns
Control Inputs, A, B, C and Inhibit
Control Input to Signal
Crosstalk
.....
III
30
15
8
Sigoallnputs (VIS) and Outputs (Vos)
tpHL
tpLH
8
c.n
o
CD4051
CD4052
CD4053
Sine Wave Response
(Distortion)
3:
oc
s:
Output Capacitance
(common OUT liN)
CD4051.
CD4052
CD4053
III
VEE=VSS=OV, RL = 10 kfl at both ends
01 channel.
Input Square Wave Amplitude = 10V
Propagation Delay Time from
VEE=VSS=OV
Address to Signal Output
CL =50 pF
(channels "ON" or "OFF")
Nola 3: A, 8 are two arbitrary channels with A turned "ON" imd 8 "OFF".
tpHL,
tpLH
5·157
mV(peak)
1000
360
240
ns
ns
ns
o
(,)
m
~
Block Diagrams
CD4051BM/CD4051BC
(,)
:E
m
16
~
(,)
om
A
~
~
10
(,)
LOGIC
LEVEL
CONVERSION
im
~
~
COMMON
OUTflN
BINARY
TO
1 OF B
OECOOER
WITH
INHIBIT
c
(,)
INH
v..
VEE
CD4052BM/CD4052BC
X CHANNELS IN/OUT
2
0
L-----rroJ-...~~~~~~N x
A
COMMON Y
OUT/IN
10
LOGIC·
LEVEL
CONVERSION
INH
BINARY
TO
10F4
DECODER
WITH
INHIBIT
Vss
Tl/F/5882-2
5-158
Block Diagrams (Continued)
CD4053BM/CD4053BC
IN/OUT
Voo
ty
ell
by
hx
OUT/lrl
A
lD
ax OR ilY
BINARY TO
1 OF 2
DECODER
WITH INHIBIT
11
15
OUTIIN
b. OR by
4
OUrllN
LOGIC
LEVEL
CONVERSION
tIC
OR ty
INH
V.,
VEE
TL/F/5662-3
Truth Table
"ON" CHANNELS
INPUT STATES
INHIBIT
0
0
0
0
0
0
0
0
1
C B A
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
...
CD4051B
CD4052B
CD4053B
0
1
2
3
OX,OY
1X,1Y
2X,2Y
3X,3Y
eX,bx,ax
eX,bx,ay
ex, by, ax
eX,by,ay
ey,bx,ax
ey,bx,ay
eY,by,ax
ey,by,ay
NONE
45
6
7
NONE
*Don't Care condition.
5-159
NONE
Switching Time Waveforms
VDD
If
ADDRESS
INPUTS
A,Bo, C VDD
,---VDO
IPLH
--..:
VOS
I
I
I
I
VDD
I
I
I
SIGNAL INPUT TO SIGNAL OUTPUT
I
I
VOS
I
I
ADDRESS TO SIGNAL OUTPUT
VDD
IN/DUTo,
OUT/IN
ANY CHANNEL
INHIBIT
VDD
VDD
90%
1Kn
0
IN/OUT 0'
OUT/IN
OUT/IN 0'
IN/OUT
IpZL
VDO
.~50PF
VOS
0
TLlF/5662-4
5·160
Special Considerations
In certain applications the external load-resistor current may
include both Voo and signal-line components. To avoid
dr.awing Voo current when switch current flows into IN/OUT
pin, the voltage drop across the bidirectional switch must
not exceed O.6V at TA';;: 25°C, or O.4V at TA> 25°C (calculated from RON values shown). No Voo current will flow
through RL if the switch current flows into OUT/IN pin.
Typical Performance Characteristics
"ON" Resistance as a
Function of Temperature for
VOO-VEE= 1SV
"ON" Resistance vs Signal
Voltage for TA = 25°C
S
1
IS
w
""c
400
.
:5
1
IS
I II L LI
300
t! ~
250
~
i..
P
1111 II
350
""
JEll .15J
i
200
400
350
300
250
200
a:
'50
~
w
""~
C
'DO
50
,0
VDD~"'0V
i..
P
JJ.W.Hi.
V
Vu" 15V
~
w
"""~
DD -
-.
-6
-4 -2
0
2
4
6
8
'50
TA = +125"C
'00
TAo = +25°t
50
0
-8
400
350
IS
""
=
,....,..,.,TT"..,.....,..,...TTTT-n
300
H-++-H+H-++++-Hrl-l
H-++-H+H-++++-Hrl-l
250
H-++-H+H-++++-Hrl-l
0
2
4
6
8
j J'lnl
400 rT"T"l"""T"f. . . .rr-rT"1rT
1
H-H-H+t-+lo'9'.-+-+-H'-+-t
TA-t'-t"-j25r"CH
5 lOD H-H-H-+tF+-+++
~
I~
~ zoo H-TA+.+,-t12-15.-1C+H-+t;;;l;d+H
z '50 f-t-+-t::t;;jo+-f-I-t9-++-H--H
: 'DO [-,TiA ' '-.!:' :',.2:;:,5':;.C""+O+19:±"I-t-lH
50 II
is
T.=-55'C
o
a
-4 -2
"ON" Resistance as a
Function of Temperature for
VOO-VEE=SV
Function of Temperature for
VOO-VEE= 10V
S
-6
SIGNAL VOLTAGE IV"IIVI
S'GNAL VOLTAGE IV"IIVI
"ON" Resistance as a
1
TA = _55°C
~
350
:+)+.J+5~+ilc
250 I-t-t-++t-f-t-t+\-+r
200 I+H-H+.~~It-I-Hr-H
p
I+H-HmH-H\-I~ ',,'Js-b
Ii Irf
~
IIII
IIII
150
~ '::
n
oL-J...I-L...1..J--'-L..J....L..L..I.-l....L..J1...I..J
-8 -6 -4 -2
-8-6-4-202468
SIGNAL VOLTAGE IV"IIVI
0
2
4
6
8
SUPPLY VOLTAGE IV"IIVI
TLIFI5662-5
5·161
•
"
o
III
~ ~National
c
o
~ Semicon~uctor
:EIII CD4066BM/CD4066BC Quad Bilateral Switch
~
~ General Description
c
o
\'
The CD4066BM/CD4066BC is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-for-pin compatible with CD4016BM/
CD4016BC, but has a much lower "ON" resistance. and
"ON" resistance is relatively constant over the input-signal
range.
Features
3V to 15V
• Wide supply voltage range
0.45 Voo (typ.)
• High noise immunity
• Wide range of digital and
±7.5 VPEAK
analog switching
800
• "ON" resistance for 15V operation
4RON=50 (typ.)
• Matched "ON" resistance
over 15V signal input
• "ON" resistance flat over peak-to-peak signal range
• 'High "ON"/"OFF"
65 dB (typ.)
@ fis= 10kHz. RL = 10 kO
output voltage ratio
• High degree linearity
0.1% distortion'(typ.)
High degree linearity
@ fis = 1 kHz, Vis= 5Vp-p.
High degree linearity
Voo-Vss= 10V, RL = 10 kO .
• Extremely low "OFF"
0.1 nA (typ.)
switch leakage
@ Voo-Vss=10V, TA=25°C
10120(typ.)
• Extremely high control input impedance
• Low crosstalk
-50 dB (typ.)
@ fis=0.9 MHz, R'L =lkO
between switches
• Frequency response, switch "ON"
40 MHz (typ.)
Applications
• Analog signal switching/multiplexing
• Signal gating
• Squelch control
• Chopper
• Modulator/Demodulator
• Commutating switch
• Digital signal switching/multiplexing
• CMOS logic implementation
• Analog-to-digital! digital-to-analog conversion
• Digital control of frequency, impedance. phase. and analog-signal-gain
Schematic and Connection Diagrams
,
"
CONTROL
Dual-In-Llne Package
IN/OUT,
Order Number CD4066BMJ or
CD4066BCJ
NS Package Number J14A
INIOUT
Order Number CD4066BMN or
CD4066BCN
NS Package Number N14A
CONTROL C ""'t--=~
Yss
TL/F/5665-1
Top View
5-162
(')
Recommended Operating
Conditions (Note 2)
Absolute Maximum Ratings
(Notes 1 and 2)
-0.5Vto +18V
VOO Supply Voltage
VIN Input Voltage
TS Storage Temperature Range
Po Package Dissipation
-0.5V to Voo + 0.5V
-65°C to
+ 15O"C
500mW
TL Lead Temperature (Soldering. 10 seconds)
Voo Supply Voltage
3Vto 15V
VIN Input Voltage
TA Operating Temperature Range
CD4066BM
OVto Voo
300"C
- 55°C to + 125°C
CD4066BC
-40"Cto +85°C
i
IX!
s:
o
~
IX!
(')
DC Electrical Characteristics, CD4066BM (Note 2)
Parameter
Symbol
-55"C
Conditions
Min
100
Quiescent Device Current
25"C
Maxi
Min
125°C
Typ
Max
Min
Units
Max
Voo=5V
VoO=10V
Voo=15V
0.25
0.5
1.0
0.01
0.01
0.01
0.25
0.5
1.0
7.5
15
30
p.A,
p.A
p.A
RL=10k{}to Voo-Vss
2
Vc=Voo. VIS=VSS to Voo
Voo=5V
Voo=10V
Voo=15V
2000
400
220
270
120
80
2500
500
280
3500
550
320
{}
Signal Inputs and Outputs
RON
ARON
"ON" Resistance
A"ON" Resistance
Between any 2 of
4 Switches
liS
Input or Output Leakage
Switch "OFF"
RL = 10 k{} to Voo-VSS
2
Vc=Voo. VIS=VSStoVoo
Voo=10V
Voo=15V
{}
10
5
Vc=O
VIS= 15Vand OV.
Vos=OVand15V
{}
{}
{}
±50
±0.1
±50
±500
nA
1.5
3.0
4.0
2.25
4.5
6.75
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
Control Inputs
VILC
Low Level Input Voltage
VIS = Vss and VooVos = Voo and Vss
Ils= ±10p.A
Voo=5V
Voo=10V
Voo=15V
VIHC
High Level Input Voltage
Voo=5V
Voo= 10V (see note 6)
Voo=15V
liN
Input Current
Voo-Vss=15V
VOO<::VIS<::VSS
Voo<::Vc<::Vss
3.5
7.0
11.0
3.5
7.0
11.0
±0.1
V
V
V
3.5
7.0
11.0
2.75
5.5
8.25
±10-5
±1.0
±0.1
p.A
DC Electrical Characteristics CD4066BC (Note 2)
Symbol
Parameter
Conditions
-40"C
Min -
100
Quiescent Device Current
Max
1.0
2.0
4.0
Voo=5V
VoO=10V
VOO=15V
5-163
85"C
25°C
Min
Typ
Max
0.01
0.01
0.01
1.0
2.0
4.0
Min
Units
Max
7.5
15
30
' p.A
p.A
p.A
DC Electrical Characteristics
Symbol
Parameter
(Continued) CD4066BC (Note 2)
-40"C
Conditions
Min
Max
25"C
Min
85°C
Typ
Max
270
120
80
·2500
500
280
Min
Units
Max
Signal Inputs and Outputs
RON
'V
V
RL=10kOto 00; SS
"ON" Resistance
,
ARON
liS
,
Vc=Voo. Vss to Voo
Voo=5V
Voo=10V
Voo=15V
2000
450
250
3200
520
300
0
0
0
A"ON" Resistance
RL=10kOto Voo;Vss
Between Any 2 of
4 Switches
Vcc=Voo. VIS=VSSto Voo
Voo=10V
Voo=15V
-
Vc;"'O .
±50
±0.1
±50
±200
nA
VIS = VSS and Voo
Vos=VooandVss
IIS= ±10p.A
Voo=5V
Voo=10V
Voo=15V
1.5
3.0
4.0
2.25
4.5
6.75
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
Input or Output Leakage
Switch "OFF"
10
5
0
0
Control Inputs
VILC
Low Level Input Voltage
VIHC
High Level Input Voltage
Voo=5V
Voo= 10V (See note 6)
Voo=15V
liN
Input Current
Voo-VSS= 15V
VOO:2:VIS:2:VSS
Voo:2:Vc:2:VSS.
AC Electrical
Parameter
tpHL. tpLH
Propagation Delay Time Signal
Input to Signal Output
tpHZ. tpLZ
3.5
7.0
11.0
±0.3
2.75
5.5
8.25
3.5
7.0
11.0
±10- 5
±0.3
V
V
V
±1.0
p.A
.
Characteristics'TA= 25°C. tr = t, = 20 ris and Vss = OV unless otherwise specified
Symbol
tPZH. tpZL
3.5
7.0
11.0
Conditions
Vc = Voo. CL = 50 pF. (Figure 1)
RL =200k
Voo=5V
Voo=10V
Voo=15V
Propagation Delay Time
Control Input to Signal
Output High Impedance to
Logical Level
RL = 1.0 kO. CL = 50 pF. (Figures 2 and 3)
Voo=5V
Voo=10V
Voo=15V
Propagation Delay Time
Control Input to Signal
Output Logical Level to
High Impedance
Sine Wave Distortion
RL = 1.0 kO. CL = 50 pF. (Figures 2 and 3)
Voo=5V
Voo=10V
Voo=15V
VC=Voo=5V. VSS= -5V
RL = 10 kO. VIS=5Vp_p• f= 1 kHz.
(Figure 4)
Vc=Voo=5V. VSS= -5V.
RL =1 kO. Vls=5Vp•p•
20 Log10 VoslVos (1 kHz)-dB ••
(Figure 4)
Frequency Response'Switch
"ON" (Frequency at -3 dB)
Min
5-164
Typ
Max
Units
25
15
10
55
35
2~
ns
ns
ns
.125
60
50
ns
ns
ns
125
60
50
0.1'
ns
ns
ns
%
40
MHz
,-
o
c
AC Electrical Characteristics (Continued) TA = 25°C, tr=tf= 20 ns and VSS = OV unless otherwise noted
Symbol
Parameter
Conditions
Feedthrough - S~itch "OFF"
(Frequency at -50 dB)
Min.
Voo=5.0V. VCc=VSS~ -5.0V.
RL = 1 kn. V'S = 5.0Vp-p• 20 Logl0.
VoslV,S= -50 dB. (Figure4)
VOO=VC(A)=5.0V; VSS=VC(B)=5.0V,
RL 1 kn. V'S(A) = 5.0 Vp.p. 20 LoglO.
VOS(B)IV'S(A)= -50 dB (FigureS)
Voo= 10V. RL=10 kn. R'N= 1.0 kn.
Vcc= 1OV Square Wave. CL = 50 pF
(Figure 6)
RL = 1.0 kn. CL =50 pF. (Figure 7)
VOS(I) = 1f2 Vos(1.0 kHz)
Voo=5.0V
Voo=10V
Voo=15V
Crosstalk Between Any Two
Switches (Frequency at -50 dB)
Crosstalk; Control Input to
Signal OulP'!t
Maximum Control Input
Typ.
Max.
Units
m
s::
(;
0.9
MHz
150
mVp•p
6.0
B.O
B.5
MHz
MHz
MHz
C's
Signal Input Capacitance
B.O
pF
COS
Signal Output Capacitance
Voo=10V
B.O
pF
C,OS
Feedthrough Capacitance
Vc=OV
0.5
C'N
Control Input Capacitance
pF
5.0
7.5
pF
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should
be operated at these limits. The tables of "Recommended Operating Conditions" and "Electrical Characteristics" provide conditions for actual device operation.
Note 2: Vss=OV unless otherwise specified.
Note 3: These devices should not be connected to circuits with the power "ON".
Note 4: In all cases, there is approximately 5pF of probe and jig capacitance in the output; however. this capacitance is included in CL wherever it is specified.
Note 5: V'S is the voltage at the in/out pin and Vos is the voltage at the outlin pin. Vc is the voltage at the control input.
Note 6: Conditions for V,HC:
a) V'S=VOO, 10S=standard B series IOH
b) V'S=OV, IOL = standard B serieslOL.
AC Test Circuits and Switching Time Waveforms
V"VDD
vI"
I
CDNTROL
VIS
"'ITt... --'I--t---....
I 1..
r
1011l.T toF4
~
-"I"
Voo
I
Voo
DUTlIN
J~'F
II'io
SD"o
VIS
-'P,. C'P.'
IV
VDS
-:..
vos
"'
VOD
/_
DV----J
FIGURE 1. tpHl> tpLH Propagation Delay Time Signal Input to Signal Output
tpZH
CONTROL
INIQUT
VOO
r
J
I-L..
10f. OUY/llilll--t---....
t-.DS
SWITCHES
I~'F
~t
VDD~
'V~."ZMVDM
DV
'"
VDD~'DD
'V~"'Z.
...
'0.
IV
FIGURE 2. tPZH. tpHz Propagation Delay Time Control to Signal Output
IPZL
V'----.I
T
'00
tpLZ
".,
,
...
VDD~
'·~-."ZL.-'
Voo
VD'
""
.
VDD~
...
"
VDD
~
,,,
VD'
FIGURE 3. tpZl> tpLZ Propagtlon Delay Time Control to Signal Output
5·165
8
en
en
1.25
-"LZ.
TL/F/5665-2
~
en
en
m
o
I4.C Test Circuits and Switching Time Waveforms (Continued)
,,·
/'\
E
vc---.,
UV
IN/OUT ':'~~H·U
··.:L3:;1~
OUT/I.~_--VDl
-'''--~
VIS
Vc=Voo for distortion and frequency response tests
Vc=Vss lor feedlhrough lesl
\
-5V
FIGURE 4. Sine Wave Distortion, Frequency Response and Feedthrough
Velll' VOO - - - . ,
;.IOUT
':'~~:ES oUTn.~-'--vDlIIl
Vss
-5V
Velll" Vss - - - - . . ,
,
IOF.
INIOUT SWITCHES OUTIIN
VOSIII
RL
"
-5V
FIGURE 5. Crosstalk Between Any Two Switches
VC----.,
VOO
Ve
VOO
r
"'l
_~"_2D_"_I-+-~t~::-----.l
K"·'
av _ _ _ _
II" 2On.
IIIDUT ~:EI OUM.t-....~--~P--voa
Vos
FIGUI:IE 6. Croaatalk: Control Input to Signal Output
VII
Ve
IV
Vos
1
RL
Il
":'
vue ....
¥II
I
T
TLlF/!i685-3
FIGURE 7. Maximum Control Input Frequency
5·166
r-----------------------~----------------------------------------'o
Typical Performance Characteristics
"ON" Resistance as a Function
"ON" Resistance vs Signal
a 400
~
~
~
350
Voltage for TA = 25'C
1-+++
11-fI-lIHI~II+-H-++-f-lH-f
250
.'5J7H-++-++H
JoU JJ
..iiir..
150 I+++++++-tv
g
100
F'
~
~
§
J !H!!+!+-H
!-++-t-++H
I-H-+
3UII
200
of Temperature for
VOo-Vss= 15V
1-++t-HI+.tcl-HtH-HH-I
v
~·II
JJ..U.Hi.
50 r+~~~~~VO~O~-~V~SS~.~'5Hv
0 L..L.J...J.....LJU-L!..J....I..J...J....L'-.U
-8-6-4-202468
~
lOO
z
.~
Z50
~
200
..4
100
400
~ 3511
~
z
~
-
r..
300
250
200
;
50
TA·+~
;5
0
TA"'-55°C
~
5D
5
, SIGNAL VOLTAGE (VIS) (V)
"ON" Resistance as a Function
"ON" ReSistance as a Function
of Temperature for
Voo-Vss=10V
of Temperature for
VOD- VsS=5V
r-r-m--r-T7T.,.,...,...T'1T'"m
'"
z'"
H-+++l-f-ll++++++l'-H
H-+t-t-!-Hl-t-H+++
I' +H
H-+++l-f-lH-+++++l'-H
1++++l+-lI-t-H-bIod-1+1
co
5
~
u
z
0
F'
~
~
""
"
1;
TA=-5S"C
o
Z
4
&
,11111
350
TA"
8
SIGNAL VOLTAGE (VIS) (V)
+1ZS~C
300
lI\ 11111
250
TA ~ +Z5'C
..
-rr~.:.:+2;.\:;,C++-Mfl::;/;I'\:'t-l+l
-8 -& -4 -Z
400
~
iii zoo
l. 150
150 H-+-t:±;;j~""f"I-+++l+l
100
aJ
o
-8-&-4-202468
TA' +125"C
~
~
en
en
TA-+,!!C
SIGNAL VOLTAGE IVIS) IV)
a
(;
t+++++-f-lH-+++++l-H
1++t++-HI++++++l1-H
t+++++-f-lH-+++++l-H
t+++++-f-lH-+++++lH-t
~ 150
10V
tD
s:
400 rrTT"T""T..,...,rrTT-rr-n""T"1
~ 350
:~~.'J5"~
III I I
100
! ! II!
50
0
-8
11111
-&
-4 -Z
0
2
4
&
8
SUPPLY VOLTAGE (VIS) (V)
TL/F/5665-4
Special Considerations
In applications where separate power sources are used 'to
drive Voo and the signal input, the Voo current capability
should exceed Voo/RL (RL = effective external load of the 4
CD4066BM/CD4066BC bilateral switches). This provision
avoids any permanent current flow or clamp action of the
Voo supply when power is applied or removed from
CD4066BM/CD4066BC.
In certain applications, the external load-resistor current
may inClude both Voo and signal-line components. To avoid
drawing Voo current when switch current flows into terminals I, 4, B or II, the voltage drop across the bidirectional
switch must not exceed 0.6V at TA,;;25'C, or O.4V at
TA>25'C (calculated' from RON values shown).
No Voo current' will flow through RL if the switch current
flows into terminals 2,3,9 or 10,
5·167
i
o
~ ~National
§c ~ Semiconductor
(J
:Ettl CD4069UBM/CD4069UBC Inverter Circuits
:::)
mGeneral Description
~
o
The CD4069UB consists of six inverter circuits and is
manufactured using complementary MOS (CMOS) to
achieve wide power supply operating range, low power
consumption, high noise immunity, and symmetric controlled rise and f~11 times.
All inputs are protected from damage due to static discharge by diode clamps to "00 and Vss.
Features
3.0Vto 15V
• Wide supply voltage range
This device is intended for all general purpose Inverter
applications where the special characteristics of the
MM74C901, MM74C903, MM74C907, and CD4049A Hex Inverter/Buffers are not required. In those applications requiring larger noise immunity the MM74C14 or MM74C914
Hex Schmitt Trigger is suggested.
O.45Vpo typo
• High noise immunity
fan out of 2 driving 74L
or 1 driving 74LS
• Low power TTL
compatibility
• Equivalent to MM54C04/MM74C04'
Schematic and Connection' Diagrams
Dual-I n-line Package
Voo
14
, . . - - - - - - -..........-0 Voo
13
II
.12
10
VOUT
......'-----+-*'-o VSS
TLIF/5975-1
Vss
TO. VIEW
TUF15975·2
Order Number CD4069UBMJ or CD4069UBCJ
See ~S Package J14A
Order Number CD4069UBMN or CD4069UBCN
See NS Package N14A
AC Test Circuits and Switching Time Waveforms
VIN~VOUT
VOO --+::ir-:::,....--=i.
INPUT
Vss
ICL.50PF
voo----;;;;~I
OUTPUT
Vss---~r~------~
'TLH
TLIFJ5975-3
TLIF/5975-4
5·168
o
Absolute Maximum Ratings
Recommended Operating Conditions
(Notes 1 and 2)
(Note 2)
Voo de Supply Voltage
-0.5 to +18 Voe
VIN Input Voltage
-0.5 to VOO +0.5 Voe
TS Storage Temperature Range
-65'e to +150'e
Po Package Oissipation
500mW
TL Lead Temperature (Soldering, 10 seconds)
260'e
Voo de SupplV Voltage
VIN Input Voltage
T A Operating Temperature Range
e04069M
e0406ge
3to15Voe
O.to VOO Voe
-55'e to +126'e'
-4o'e to +85'e
c
~
m
c:
OJ
s:
(=)
C
~
DC Electrical Characteristics
SYM
IpO
CD4069M
OJ
(Note 2)
o
-55'e
PARAMETER
Quiescent Device Current
m
c:
CONDITIONS
MIN
VOO= 5V,
25°e
MAX
MIN
TYP
125°e
MAX
0.25
0.25
0.5
1.0
MAX
UNITS
7.5
I1A
0.5
15
I1A
1.0
30
I1A
VIN = VOO or VSS
VOO = 10V,
MIN
,
VIN = VOO or VSS
VOO=15V.
VIN = VOO or VSS
VOL
VOH
VIL
Low Level Output Voltage
High Level Output Voltage
Low Level Input Voltage
1101<
lilA
VOO = 5V
0.05
0.05
V
0.05
a
a
0.05
VOO = 10V
0.05
0.05
V
VOO = 15V
0.05
0
0.05
0.05
V
1101<
lilA
VOO = 5V
4.95
4.95
5
4.95
V
VOO=10V.
9.95
9.95
10
9.95
V
VOO = 15V
14.95
14.95
15
14.95
V
1101<
lilA
1.0
1.0
1.0
V
VOO = 10V. Va = 9V
2.0
2.0
2.0
V
Voo = 15V. Va = 13.5V
3.0
3.0
3.0
V
VOO = 5V,
VIH
High Level Input Voltage
1101<
lilA
4.0
4.0
4.0
V
Voo = 10V. Va = IV
B.O
8.0
B.O
V
Voo= 15V. Vo= 1.5V
12.0
12.0
12.0
V
Vo = O.4V
0.64
0.51
0.88
0.36
0.9
rnA
rnA
rnA
Voo = 5V,
10L
10H
liN
VO= 4.5V
Va =0.5V
Low Level Output Current
VOO= 5V.
(Note 3)
VOO = 10V. Va = 0.5V
1.6
1.3
2.25
Voo = 15V. Va = 1.5V
4.2
3.4
B.B
2.4
-{l.64
-{l.51
-{l.BB
-{l.36
-2.25
-{l.9
Va =4.6V
High Level Output Current
VOO = 5V.
(Note 3)
VOO = 10V. Vo = 9.5V
-1.6
-1.3
VOO = 15V. Vo = 13.5V
-4.2
-3.4
I nput Current
-{l.10
VOO = 15V. VIN = OV
0.10
VOO = 15V. VIN = 15V
5-169
-2.4
-8.8
-10-5
10-5
-{l.10
-1.0
0.10
1.0
,
rnA
rnA
rnA
I1A
I1A
DC Electrical Characteristics CD4069C (Note 2)
SYM
100
-40°C
PARAMETER
CONDITIONS
auiescent Oevice Current
MIN
25°C
MAX
VOO= 5V,
1.0
VIN = VOO or VSS
VOO = 10V,
VIN = VOO or VSS
VOO = 15V,
,
MIN
TYP
85°C
MAX
,
MIN
UNITS
MAX
1.0
7.5
,J1.A
2.0
2.0
15
J1.A
4.0
4.0
30
J1.A
VIN = VOO or VSS
VOL
Low Level Output Voltage
IIOI
g
..
fjliilll!l!i!l~I!~1!
~. . . . .
5.0
10
~
40
i - - ~.IISP~
40
"coz
3D
"
20
co
~
I
,
_CL 'SOpF
- , ....
-
~ISP~
~
~
......f-""
"z
:i"
f-""
~
TA'2S'C
VOO·3V
!Ej:
.....
SjE Ai TEr ciRcl lT
ISO
Vo~.:~
100
VOO'I~
50
""'I'
~
If
10
I'
VOO :r;~v
,", , ,
20
20
-SO -2S 0 25 SO 7S 100 12S
-
17' ~SEEACTESTCIRCUIT
-
SO
100
ISO
CL - LOAD CAPACITANCE (pFI
AM81ENTTEMPERATURE ('CI
Tl/F15975-9
TUFJ5975-8
5·171
o
c:
I:D
TLlFI5975-7
vs Load Capacitance
]
3:
o
AMBIENT TEMPERATURE ('CI
Propagation Delay Time
Ambiant Temperature
j:
20
TUFJ597S-6
Propagation Delay vs
.s>
_r-
-50 -25 0 25 60 75 100 125
TL/F/5975·5
~
- T I I
I I I
[ [ [
INPUT FREQUENCY (HzI
V~O .'IOvl
I-- I-- -
i - - -~L'l~
IS
VIN(VI
SO
I
60
z
"j:
":;:'"
-S
I:D
I
i- SEE AC Ti ST ~IRCrIT - I- -
>
g
VOO • ISV
10
r-JDo~svl
80
or·---------------------------------------------------------------,
~ ~ National.
.
~ ~ Semiconductor
o
iCD CD4070BM/CD4070BC Quad 2-lnput
~
ic
EXCLUSIVE-OR Gate
.
o General Description
Features
Employing complementary MOS (CMOS) transistors to
achieve wide power supply operating range, low power
consumption, and high noise margin, this gate provides
basic functions used in the implementation of digitaliniegrated circuit systems. The N- and P-channel enhancement mode transistors provide a symmetrical circuit with
output swing essentially equal to the supply voltage. No
DC power other than that caused by leakage current is
consumed during static condition. All inputs are protected from damage due to static discharge by diode
clamps to Voo and Vss.
.3.0Vto 15V
0.45 Voo typo
fan out of 2 driving 74L
or 1 driving 74LS
• Wide supply voltage range
• High noise immunity
• Low power TTL
compatibility
.• Pin compatible to CD4030A
• Equivalent to MM54C861MM74C86 and MC14507B
Connection Diagram
Dual-I n-line Package
Order Number CD4070BMJ or CD4070BCJ
See NS Package J14A
Order Number CD4070BMN or CD4070BCN
See NS Package N14A
4
J=A0B
Vss
K=c0D
TDPVIEW
TUF/S976-1
Typical Performance Characteristics
Truth Table
Propagation Delay Time
vs Load capacitance
INPUTS
50
100
150
LDAD CAPACITANCE I,F)
TUFJ5976-2
5-172
OUTPUTS
y
A
B
L
L
L
L
H
H
H
L
H
H
H
L
Absolute Maximum Ratings
Recommended Operating Conditions
(Notes 1 and 2)
. VOO DC Supply Voltage
--{l.S to +18 VOC
VIN Input Voltage
--{l.S to VOO +O.S VOC
T S Storage Temperature Range
-£SOC to +IS0°C
PD Package Dissipation
SOOmW
. 260°C
TL Lead Temperature (Soldering, 10 seconds)
(Note 2)
Voo DC Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
C04070BC
C04070BM
3tolSVOC
Oto VOO VOC
-40° C to +8So C
-SSoC to +12SoC
DC Electrical Characteristics CD4070BM (Note 2)
25°C
-55°C
SYM
Mlr.
100
Quiescent Device Current
I
VOL
Low Level Output Voltage
= SV,
= VOO or VSS
VOO = 10V,
VIN = VOO or VSS
Vbo = ISV,
VIN = VOO or VSS
VOO
VOO
= SV
= 10V
= 15V
VOO
VOO
Low L'evel Input Voltage
VOO
VOO
High Level Input Voltage
VOO
= 10V
= 15V
= SV,
= 10V.
= lSV,
liN
= SV,
= 10V,
UNITS
0.25
0.2S
7.S
/lA
O.S
O.S
15
/lA
1.0
1.0
30
/lA
0.05
0
0.05
0.05
V
0.05
0
0.05
0.05
V
O.OS
0
0.05
0.05
V
4.95
4.95
5
4.95
V
9.95
9.9S
10
9.95
V
14.95
14.9S
15
14.9S
V
= 4.5V
= 9V
Va = 13.5V
1.S
1.S
1.5
V
Va
3.0
3.0
3.0
V
4.0
4.0
4.0
V
Va
= O.SV
Va = IV
,
3.5
3.5
3.5
V
7.0
7.0
7.0
V
11.0
11.0
11.0
V
0.64
O.SI
0.88
0.36
mA
VOO = 10V, Va = 0.5V
1.6
1.3
2.25
0.9
VOO = 15V, Va = 1.5V
4.2
3.4
8.8
2.4
rnA
-0.64
-O.Sl
-0.88
-0.36
mA
9.SV
-1.6
-1.3
-2.25
~0.9
mA
-4.2
-3.4
-8.8
-2.4
Low Level Output Current
Voo = 5V,
(Note 3)
Va = O.4V
Va = 4.6V
High Level Output Current
VOO = SV,
(Note 3)
VOO = 10V, Va
Input Current
MAX
Va
Voo= lSV, Vo= 1.5V
10H
MIN
1i01<11'A
VOO
10L
MAX
110'/< lilA
VOO
VIH
TYP
1101
'"
..
~
~
J
~>
OD
~
'",
C040818
TA-2n
VOO _115V
5
VOO -
>
0
~-
VOO -10V
0
~
",ss~/
sJ
"
J
~
'",
-
15
VOO -10V
10
voo-J
5
'"
>
f
's
10
15
VI-INPUT VOLTAGE (VI
ONE INPUT ONLY
vol-15v
0
0
20
..
~
~
15
J
;'!
~
>~
::
'"'",
...
>-
10
VOO -10V
~"
",.sf)
I
"
r
1'.ill
5
0
0
300
~"
:J~
0:>
ZOO
I
~
,~
=
~
e-
100
o
~]
'1
IS
10
S
VI -INPUT VOLTAGE (VI
ONE INPUT ONLY
20
400
C040BlB
TA - 25~C
CL- 50 of
300
~~
"'''
~5
:!~
200
~ 'pHL
,~
1'-. tPHL
0
_
TUF/5977-7
~
\
...>'"
Vo
FIGURE 3. Typical Transfer
Characteristics
;;
\
~~
20
~~V~~~D
Voo - SV
0
~
;::
C04011B
TA - 2SoC
CL -50 OF
5'" 100
5
10
15
VOO - SUPPLY VOLTAGE (V)
IP\~ .....
.9-
& tPLH
TUF/5977-8
FIGURE 4. Typical Transfer
Characteristics
ZO
400
'"~~
Vor5V
5
10
15
VI -INPUT VOLTAGE (VI
BOTH INPUTS
S
0
10
5
IS
VI -INPUT VOLTAGE (VI
BOTH INPUTS
'DO
VI,:
~
'",
>-'"
I
VOO -10V
10
TUFI5977~
"'"
~
J,
~"
",.sf)
I"
~
>
~
C04071B
TA - Z5"C
VOO - 15l
15
FIGURE 2. Typical Transfer
Characteristics
C04011B
Tr 2SOC
VL-15V
.'"
~
L
TUFI5977-5
FIGURE 1. Typical Transfer
Characteristics
20
20
C040818
TA -Z5'C
=
20
0
0
10
15
S
Voo -SUPPLY VOLTAGE (V)
TUFI~-'O
TL/FI5917-9
FIGURE 5
5-179
20
FIGURE 6
Typical Performance Characteristics
200
200
~
CD40718
~..5.
-
-P.t --
-
~~
6>
~~
~'"
~.l
~~«
>
I-
--
50 t - - - VDO -lDV
~
Ie
~'"
~D.
75
50
100
~e
V~D -15V
25
-
VDD-5V _ _
"'''
r-VDD -IOV
-
I
ISO
100
VDD -15V
25
CL - LOAD CAPACITANCE (pFI
50
j
ee
~"
~
~~
Ie
",,,,
I-~
~~
~
100
.90
0
100
,] -190
~
~
1.0
50
:;
0
'"
"''''
C04071B
C04081B - r (See ApplicatIOn Note AN-gO
Propagation Delay)
\
r'\.
0.5
~g:
~
I
100
75
o
e
~
CL - LOAD CAPACITANCE (pFI
2
4
6
1tH-
~
22
18
14
~
I
10
6
'"
2
l-
o
VO~
--
I
70
~
50
V
~ '~
f
"w
'"'"
"
~
<>
-f:.~ VO~ o5J4
6
V
----
~ I-""""
50
25
0
"'"'"
~
5
0:
~
r- CD4071B
CD40818
I
'"e
~CC'-5L, ~"I10
'J
r- r-
VCC -IOV
I
22
28
32
VCC -15V
20 18 16 14 12 10
8 10 12 14 16 18 20
V
24
36
8
6
4
2
0
VCC - VOUT (VI
VOUT (VI
TLIF15977-18
TLlFI5977-11
FIGURE 14
FIGURE 13
5·180
75
100
TLlFI5977-16
FIGURE 12
14
18
/'
.--
CL - LOAD CAPACITANCE (pFI
I-
//
2
./.
./. ......-::: ~
3D
:5
".s
-15V
I- -VOO-IOV
o
80
TLIF/5977-15
L
i:
en
I-
I
./.
/
FIGURE 11
3B
34
:3
150
130
lID
5
l-
B 10 12 14 16 18 20
TLlF/5977-14
..§.
~
CD4071B
CD40B1B
170
VOO - POWER SUPPLV (VI
FIGUR.I; 10
100
TlIFI5977-13
tr= tf= 20ns
e
50
75
FIGURE9
~z
5
«
"
50
25
CL - LOAD CAPACITANCE (pFI
TA-25°C
g
~ i=
25
50
~~
1.5
z
;::
<;
0
100
~'"
5i=
w
150
I-
~~
~S
;Ow
2.0
u::
C040818
TA "25'C
~:3
~~
"''''
:i=
CD40818
TA-25°C
150
TlIFI5977-12
"'>
I-
",w
FIGURE 8
200
"'6§
>,.
---
75
TLlF/5977-11
~
w
;g
CL - LOAO CAPACITANCE (pFI
FIGURE 7
:s:
200
~
CD40718
TA = 25"C
>-;
TA -25 C
(Cont'd.)
.
~ Semiconductor
~National
CQ4072BM/CD4072BC Dual 4-lnput OR Gate,
CD4082BM/CD4082BC Dual 4-lnput AND Gate
General Description
Features
These dual gates are monolithic complementary MOS
(CMOS) integrated circuits constructed with N-and
P-channel enhancement mode transistors. They have
equal source and sink current capabilities and conform
to standard B series output drive. The devices also have
buffered outputs which improve transfer characteristics
by providing very high gain. -All inputs are protected
against static discharge with diodes to Voo and Vss.
3.0Vto 15V
• Wide supply voltage range
0.45VDD (typ.) ~
• High noise immunity
fanout of 2.driving 74L ~
• Low power TTL
compatibility
or 1 driving 74LSa;
• 5V-10V-15V parametric ratings
• Symmetrical output characteristics
• Maximum input leakage 1",A at 15V over full temperac
ture range
g
s::
o
~
CO
I\)
OJ
o
Connection Diagram
CD4072BM/CD4072BC
CD4082BM/CD4082BC
TLlF/591a·l
TUF/5978-2
Order Number CD4072BMJ, CD4072BCJ, CD4082BMJ
or CD4082BCJ
See NS Package J14A
Order Number CD4072BMN, CD4072BCN,
CD4082BMN or CD4082BCN
See NS Package N14A
5-181
Absolute Maximum Ratings (Notes 1 and 2)
Voo
VIN
Ts
Po
TL
-0.5 V to +18 V
Supply Voltage
Input Voltage
-0.5 to VooO.5 V
Storage Temperature Range
-65°Cto+150"C
Package Dissipation
500mW
Lead Temperature (soldering, 10 seconds)
260°C
Recommended Operating Conditions
(Note 2)
3.0to 15V
OVtoVooV
Voo Supply Voltage
VIN Input Voltage
TA Operating Temperature Range
CD4072BM, CD4082BM
CD4072BC, CD4082BC
-55°C to +125°C
-40°C to +85°C
.
DC Electrical Characteristics
(Note 2) -
CD4072BM, CD4082BM
,
Sym Parameter
-55"C
Conditions
Min
Max
125"C
25"C
Min
Typ
Max
Min
Max
Units
100 Quiescent
Device Current
Voo=5.0V
Voo=10V
Voo=15V
0.25
0.5
1.0
0.004
0.005
0.006
'0.25
0.5
1.0
7.5
15
30
,..A
,..A
,..A
VOL Low Level
Output Voltage
Voo=5.0V
Voo=10V
Voo=15V
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.95
V
V
V
VOH High Level
Output Voltage
Voo=5.0V
Voo=10V
Voo=15V
VIL Low Level
Input Voltage
Voo=5.0V, Vo =0.5Vor 4.5V
Voo = 10V, Vo =1.0V or 9.0V
Voo = 15V, Vo =1.5V or 13.5V
VIH High Level
Input Voltage
Voo = 5.0 V, Vo =0.5V or 4.5V
Voo =10V, Vo = 1.0Vor 9.0V
Voo =15V, Vo =1.5V or 13.5V
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.50
8.25
3.5
7.0
11.0
V
V
V
10L Low Level
Output Current
(Note 3)
Voo=5.0V, Vo=0.4V
Voo=10V, Vo=0.5V
Voo=15V, Vo=1.5V
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.2
8.0
0.36
0.90
2.4
mA
mA
mA
IOH High Level
Output Current
(Note 3)
Voo=5.0V, Vo=4.6V
Voo =10V, Vo=9.5V
Voo=15V, Vo,",13.5V
-0.64
-1.6
-4.2
";'0.51
-1.3
-3.4
-0.88
-2.2
-8.0
-0.36
-0.90
-2.4
mA
mA
mA
liN
Input Current
4.95
9.95
14.95
4.95
9.95
14.95
1.5
3.0
4.0
-0.10
0.10 .
Voo=15V, VIN=OV
Voo =15V, VIN=15V
5.0
10
15
4.95
9.95
14.95
-
2.25
4.50
6.75
1.5
3.0
4.0
-10- 5 -0.10
10-5
0.10
V
V
V
1.5
3.0
4.0
-1.0
1.0
V
V
V
,..A
,..A
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not
meant to imply that the devices should be operated at these limits. The tables of "Recol11mended Operating Conditions" and "Electrical Characteristics" provide conditions for, actual device operation.
Note 2: Vss = OV unless otherwise specified.
Note 3: I OL end IOH are tested one output at a time.
,
5-182
,---
DC Electrical Characteristics
Sym Parameter
(Note 2) -
Conditions
CD4072BC, CD4082BC
-40·C
Min
2S·C
Max
Min
8S·C
Typ
Max
Min
Max
Units
100 Quiescent
Device Current
Voo=5.0V
Voo=10V
Voo=15V
1.0
2.0
4.0
0.004
0.005
0.006
1.0
2.0
4.0
7.5
15
30
I'A
I'A
I'A
VOL Low Level
Output Voltage
Voo=5.0V
Voo=10V
Voo=15V
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
VOH High Level
Output Voltage
Voo =5.0V
Voo=10V
Voo=15V
VIL Low Level
Input Voltage
Voo = 5V, Va =0.5V or 4.5V
Voo=10V, Vo=1.0Vor 9.0V
Voo = 15V, Va =1.5V or 13.5V
VIH High Level
Input Voltage
Voo = 5.0 V, Va =0.5Vor 4.5V
Voo = 10V, Va =1.0V or 9.0V
Voo = 15V, Va = 1.5V or 13.5V
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.50
8.25
3.5
7.0
11.0
V
V
V
10L Low Level
Output Current
(Nbte3)
Voo = 5.0V, Va = 0.4 V
Voo = 10V, Va =0.5V
Voo=15V, Vo=1.5V
0.52
1.3
3.6
0.44
1.1
3.0
0.88
2.2
8.0
0.36
0.90
2.4
mA
mA
mA
10H High Level
Output Current
(Note 3)
Voo=5.0V, Vo=4.6V
Voo=10V, Vo=9.5V
Voo =15V, Va =13.5V
-0.52
-1.3
-3.6
-0.44
-1.1
-3.0
-0.88
-2.2
-8.0
-0.36
-0.90
-2.4
mA
mA
mA
liN
Input Current
4.95
9.95
14.95
4.95
9.95
14.95
1.5
3.0
4.0
V~o =15V, VIN = OV
,
4.95
9.95
14.95
2.25
4.50
6.75
1.5
3.0
4.0
-10- 5
-0.3
0.3
Voo = 15V, VIN = 15V
5.0
10
15
V
V
V
1.5
3.0
4.0
-0.3
0.3
10-5
V
V
V
-1.0
1.0
I'A
I'A
-.
AC Electrical Characteristics
TA = 25°C, CL = 50 pF, unless otherwise noted.
Typ
Max
Units
tpHL
Propagation Delay, High to Low Level
Voo=5.0V
Voo=10V
Voo=15V
125
60
45
250
100
70
ns
ns
ns
tpLH
Propagation Delay, Low to High Level
Voo=5.0V
Voo=10V
Voo=15V
125
60
45
250
100
70
ns
ns
ns
Voo =5.0V
Voo=10V
Voo=15V
100
50
40
200
100
80
ns
ns
ns
7.5
pF
Symbol
Parameter
Conditions
tTHL, tTLH Transition Time
Min
CIN
Average Input Capacitance (Note 4)
Any Input
5.0
Cpo
Power Dissipation Capacity (Note 5)
Any Gate
20
pF
Note 4: Capacitance is guaranteed by periodic testing.
Note 5: Cpo' determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family
Characteristics, Application Note AN-90.
I
5-183
(J
m
~
Q
~National
~ Semiconductor
(J
!
CD4073BM/CD4073BC Double Buffered Triple 3-lnput
rAND Gate
~ CD4075BM/CD4075BC Double Buffered Triple 3-lnput
<:(J OR Gate
~
~ General Description
Features
~
These triple gates are monolithic complementary MOS • Wide supply voltage range
3.0Vto 15V
(CMOS) Integrated circuits constructed with N- and
0.45 Voo typo
• High noise Immunity
(J P-channel enhancement mode translstors_ They have • Low power TTL
fan out of 2 driving 74L
equal source and sink current capabilities and conform
compatibility
or 1 driving 74LS
to standard B series output drive_ The devices also have • 5V - 10V - 15V parametric ratings
~ buffered outputs which Improve transfer characteristics • Symmetrical output characteristics
by providing very high gain_ All inputs are protected • Maximum Input leakage 1",A at 15 V over full temperaagainst static discharge with diodes to Voo and Vs s ture range
(J~----------------------------------------------------------~
im
~
Conn~ction
Diagrams
Dual-In-Line Packages
C04075B Triple 3-lnput OR Gate
CD4073 Triple 3·lnput AND Gate
Vss
V55
TOP VIEW
TOP VIEW
Order Number CD4073BMJ, CD4073BCJ,
CD4075BMJ or CD4075BCJ
See NS Package J14A
Order Number CD4073BMN, CD4073BCN,
CD4075BMN or CD4075BCN
See NS Package N14A
5·184
TUFI5979-2
Absolute Maximum Ratings (Notes 1 and 2)
Operating Conditions
Voo DC Supply Voltage
-0.5Voc to+ 18V oc
-0.5 Voc to Voo + 0.5 Voc
VIN Input Voltage
_65°C to +150°C
Storage Temperatu re Range
TS
500mW'
Package Dissipation
Po
h Lead Temperature (soldering, 10 seconds) 260·C
Voo DC Supply Voltage
+5 Voc to +15 Voc
OVoc to Voo Voc
VIN Input Voltage
Operating Temperature Range
TA
-55°C to +125°C
CD4073BM/CD4075BM
_40°C to +85°C
CD4073BC/CD4075BC
(Note 2)
DC Electrical Characteristics CD4073BM/CD4075BM (Note 2)
SYM
PARAMETER
_55°C
CONDITIONS
100 Qu iescent Device Current
MIN
VOO = 5V, VIN = VOO or VSS
VOO = 10V, VIN = VOO or VSS
VOO = 15V, VIN = VOO or VSS
VOL Low Level Output Voltage VOO=5V}
VOO= 10V 1I01
VT-
I
GUARANTEEO MAXIMUM
~
-VOO"'0V
+tVT
*ANVIHPUT
o
I I I
I I I
......
I- ~
20 l -
-
~
t-
I I I
10
GUARANTEEO MINIMUM
I I I
15
10
I
L
t- TA "25'C I I I
40
15
10
INPUT VOLTAGE (VI
VOO (VI
TL/FI5982·8
TLfFI59B29
Guaranteed Trigger Threshold
Voltage vs V 00
~
-;!.
11
10
>
t.
....~
~
">
~
....'"
~
Guarantaad Hysteresis vs VOO
GUARANTEED HVSTERESIS-(VT') (VT'
' ..L, rf1'IIA
r- (MA~
,,,,,,..,,,,,.,,,
TA"UC
"DO
''''S:>-'::hi..1 fj.LiVf1j~
..
".I;'~
'lJl-,r.J).
fJI
'&/'fJ.
~.t ~
~
(MAX)
11:11 f'I1T1~{/,
r-
}
j!JfjJ.
TA "25'C
~
}VT+
~
- l -I- (0.4 VoBJ.
~
~
VT~
"......
i..-"
!;;
;2
(MI~1
I
~
,*ANYINPUT
....
.*MINIMUMHVSTEflESISSPREADD.1VOD
10
V
(~A,il
--
(TVPI
-,..-"
l-
...... iM:;; I(O. IVool10
15
VoO(VI
15
1100 (VI
TL/FI5982·1Q
TlIF/5982-11
Input and Output Characteristics
Output Characteristic
Voo
VOHJl
~
VOL
>:I.
ORIVER
VIHJl
VOL
>:I.
V,H(M,NI"VT+(M,NIV,L(MAXI" VT-(MAXI
T---
Input Characteristic
_VNMH_ - -
____
1_ -- ========"
LOAO
TLIF/5982·11
VNMH = VOH-VIL(MAX) '" VOO-VIL(MAX) = VOO - VT-(MAX)
AC Test Circuits and Switching Time Waveforms
rtf
.
VOO
Y,N
OV
~
90%
50%
10%
•
trLH
Voo
VOUT
OV-----r-r,~~------+-J
tpHL
tpLH
TUFI5982·12
5-203
•
o
~ ~National
§c ~ Semiconductor
o
~
al
~
§
CD4094BM/CD4094BC 8·Bit Shift Register/Latch
with TRI·STATE® Outputs
c General Description
o
Features
The CD4094BM/CD4094BC consists of an a·bit shift regis·
ter and a TRI·STATE a·bit latch. Dat'a is shifted serially
through the shift register on the positive transition of the
·clock. The output of the last stage (as) can be used to
cascade several devices. Data on the as output is trans·
ferred to a second output, as, on the following negative
clock edge.
• Wide supply voltage range
• High noise immunity
3.0Vto 1aV
0.45 Voo (typ.)
fan out of 2 driving 74L
or 1 driving 74LS
• Low power TTL
compatibility
• TRI·STATE outputs
Th~ output of each stage of the shift 'register feeds a
latch, which latches data on the negative edge of the
STROBE input. When STROBE is high, data propagates
through the latch to TRI·STATE output gates. These
gates are enabled when OUTPUT ENABLE is taken high.
Connection Diagram
Dual·ln·Line Package
STROBE
16
DATA
15
CLOCK
14
VDD
OUTPUT
ENABLE
05
01
13
06
07
02
12
03
11
08
04,
10
D's
-I
Order Number CD4094BMJ or CD4094BCJ
See NS Package J16A
Order Number CD4094BMN or CD4094BCN
See NS Package N16E
Os
Vss
TOP VIEW
TUF15983-1
Block or Logic Diagram
Os
5·204
Absolute Maximum Ratings
Recommended Operating Conditions
(Notes 1 and 2)
(Note 2)
Voo Supply Voltage
-0.5 to +18 Voe
VIN Input Voltage
.-0.5 to Voo + 0.5 Voe
-65°C to +150°C
Ts Storage Temperature Range.
Po Package Dissipation
500mW
TL Lead Tempe!ature (Soldering, 10 seconds)
260°C
Voo DC Supply Voltage
VIN Input Voltage
TA Operating Temperature Range
CD4094BM
CD4094BC
DC Electrical Characteristics
Sym
100
Quiescent
Device Current
Max
Min
Voo=5.0V
Voo=10V 1101" 1.01'A
Voo = 15V
VOH High Level
Output Voltage
VOO=5.0V}
Voo= 10V 1101" 11'A
Voo=15V
0.05
0.05
0.05
4.95
9.95
14.95
0
0
0
4.95
.9.95
14.95
VIL
Low Level
Input Voltage
Voo=5.0V, Vo=0.5V or 4.5V
Voo = 10V, Vo = 1.0V or 9.0V
Voo=15V, Vo=1.5Vor 13.5V
VIH
High Level
input Voltage
Voo=5.0V, Vo=0.5Vor 4.5V
Voo=10V, Vo=~.OV or 9.0V
Voo=15V, Vo;=1.5Vor 13.5V
3.5
7.0
11.0
3.5
7.0
11.0
10L
Low Level
Output Current
(Note 3)
Voo = 5.0 V, Vo = 0.4 II
Voo=10V, Vo=0.5V
Voo=15V, Vo=1.5V
0.64
1.6
4.2
0.51
1.3
3.4
10H
High Level
Output Current
(Note 3)
Voo=5.0V, Vo = 4.6V
Voo=10V, Vo=9.5V
Voo= 15 V, Vo= 13.5 V
-0.64
-1.6
-4.2
-0.51
-1.3
-3.4
liN
Input Current
Voo=15V, VIN=OV
Voo = 15V, VIN = 15V
loz
TRI·STATE Output
Leakage Current
Voo= 15 V, VIN=O Vor15 V
Sym
Parameter
Max
Max
Units
5.0
10
20
150
300
600
I'A
I'A
I'A
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
5.0
10.0
15.0
1.5
3.0
4.0
Min
V
V
V
4.95
9.95
14.95
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
3.5
7.0
11.0
V
V
V
0.88
2.25
8.8
0.36
0.9
2.4
mA
mA
mA
0.88
2.55
iI·8
-0.36
-0.9
-2.4
mA
mA
mA
-0.1
0.1
-0.1
0.1
1.0
1.0
I'A
I'A
0.3
±0.3
±9
p.A
CD4094BC (Note 2)
Conditions
100
Quiescent
Device Current
Voo=5.0V
Voo=10V
Voo=15V
VOL
Low Level
Output Voltage
VOO=5.0V}
Voo=10V 1101" 1.0"A
Voo=15V
VOH High Level
Output Voltage
Typ
5.0
10
20
VOL Low Level
Output Voltage
125°C
25°C
-55°C
Min
Voo=5.0V
Voo=10V
Voo=15V
DC Electrical Characteristics
-55°C to +125°C
-40°C to +85°C
CD4094BM (Note 2)
Conditions
Parameter
+3.0 to +15 Voe
Oto Voo Voe
VOO=5.0V}
Voo = 10V 1101" 1"A
Voo=15V
-40°C
Nlin
Max
25°C
Min
Typ
20
40 80
0
0
0
4.95
9.95
14.95
VIL
Low Level
Input Voltage
Voo =5.0V, Vo= 0.5V or 4.5V
Voo = 10V, Vo = 1.0V or 9.0V
Voo=15V, Vo=1.5Vor 13.5V
VIH
High Level
Input Voltage
Voo = 5.0 V, Vo = 0.5 V or 4.5 V'
Voo=10V, Vo=1.0V or 9.0V
Voo=15V, Vo=1.5V or 13.5V
3.5
7.0
11.0
3.5
7.0
11.0
10L
Low Level
Output Current
(Note 3)
Voo=5.0V, Vo=O.4V
Voo=10V, Vo=0.5V
Voo=15V, Vo=1.5V
0.52
1.3
3.6
0.44
1.1
3.0
0.05
0.05
0.05·
Units
"A
"A
"A
V
V
V
V
V
V
4.95
9.95
14.95
1.5
3.0
4.0
0,88
2.25
8.8
Max
150
300
600
0.05
0.05
0.05
5.0
10.0
15.0
1.5
3.0
4.0
5·205
Min
20
40
80
0.05
0.05
0.05
4.95
9.95
14.95
85°C
Max
1.5
3.0
4.0
V
V
V
3.5
7.0
11.0
V
V
V
0.36
0.9
2.4
mA
mA
mA
(J
m
~
DC Electrical Characteristics
Sym
Parameter
(cont'd) CD40948C (Note 2)
-40"C
Conditions
Min
.(J
im
i
iOH High Level
Output Current
(Note 3)
Voo = 5.0V, Vo =4.6V
Voo=10V, Vo=9.5V
Voo =15V, Vo =13.5V
liN Input Current
Voo=15V, VIN=OV
Voo=15V, VIN=15V
loz TRI-STATE Output
Leakage Current
Voo= 15 V, VIN=O Vor15 V
c
(J
AC Electrical Characteristics
Symbol
-0.52
-1.3
-3.6
25°C
Min
Typ
-0.44
-1.1
-3.0
0.88
2.55
8.8
-0.3 .
0.3
1
,
85°C,
Max
Min
Max
-0.36
-0.9
-2.4
Units
mA
mA
mA
-0.3
0.3
-1.0
1.0
,..A
,..A
1
10
p.A
TA:= 25°C, CL = 50 pF
Parameter
Conditions
tpHL, tpLH Propagation Delay Clock to as
tpHL, tpLH Propagation Delay Clock to Parallel Out
tpHL, tpLH Propagation Delay Strobe to Parallel Out·
I
tpHZ
Propagation Delay ~9h Level to High Imped~nce
tpLZ
Propagation Delay Low Level to High Impedance
tPZH
Propagation Delay High Impedance to High Level
tPZL
Propagation Delay High Impedance to Low Level
tTHL, tTLH Transition Time
Set·up Time Data to Clock
/
tr, tf
Maximum Clock Rise and Fall Time
tpc
Minimum Clock Pulse Width
tps
Minimum Strobe Pulse Width
Typ
Max
Units
300
125
95
230
110
75
600
250
190
460
220
150
ns
ns
ns
ns
ns
ns
Voo=5.0V
Voo=10V
Voo= 15V
Voo=5.0V
Voo=10V
Voo=15V
420
195
135
290
145
100
840
390
270
580
290
200
ns
ns
ns
ns
ns
ns
Voo=5.0V
Voo = 101i
Voo=15V
Voo=5.0V
Voo=10V
Voo.=15V
140
75
55
·140
75
55
280
150
110
280
150
110
ns
ns
ns
ns
ns
ns
Voo=5.0V
Voo=10V
Voo=15V
Voo=5.0V
Voo=10V
Voo=15V
140
75
55
140
75
55
100
50
40
40
20
10
280
150
110
280
150
110
ns
ns
ns
ns
ns
ns
200
100
80
ns
ns
ns
ns
ns
ns
Voo=5.0V
Voo=10V'
Voo=15V
Voo=5.0V
Voo=10V
Voo=15V
tpHL, tpLH Propagation Delay Clock to as
tsu
Max
Voo=5.0V
Voo=10V
Voo=15V
Voo=5.0V
Voo=10V
Voo=15V
Voo=5.0V
Voo=10V
Voo=15V
Voo=5.0V
Voo=10V
Voo=15V
Voo=5.0V
Voo=10V
Voo=15V
I
80
40
20
1
1
1
200
100
83
200
80
70
100
50
40
100
40
35
3.0
6.0
8.0
ms
ms
ms
ns
ns
ns
ns
ns
ns
1.5
MHz
Voo=5.0V
3.0
MHz
Voo=10V
4.0
MHz
Voo=15V
Input Capacitance
pF
5.0
7.5
Any Input
CIN
Nole 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed; they are not
meant to imply that the devices should be operated at these limits. The tables of "Recommended Operating Conditions". and
"Electrical Characteristics" provide conditions for actual device operation.
Nole 2: Vss = 0 V unless otherwise specified.
Note 3: 10H and 10L are tested one output at a time.
fMAX
Maximum Clock Frequency
Min
5·206
•
(')
C
Timing Diagram
S
CD
~
aJ
-n
3:
VOO
CLOCK
c~
Vss
0
VOO
aJ
CD
~
\1.....:..---1/' I
su
DATA]
STROBE
ENABLE
OUTPUT
01
,_t
1t;~1
I
--=1:-
-I
I
\
VSS
I
,
VOO
VSS
I
VOO
t - t PHL
VSS
1
1\
tPHL~o%~~1
~-tPLH
tPLH
~_ _ _ _ _ _ _ _ _ _ _ _ _ _- - J
Os
1~:-tPLH
VOO
VSS
VOO
VSS
1{~'
O'S _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J/50%
VOo
VSS
TUF!5983-3
Test Circuits and Timing Diagrams for TRI-STATE
OUTPUT
ENABLE
CLOCK
".....---VOO
50%
STROBE
50%
OATA
OUTPUT
ENABLE
TUFI598J.4
STROBE
DATA
50%
t-1-kQ........-o OUTPUT
!-t
I
PHZ
OUTPUT
ENABLE
CLOCK
.r_---VOO
50%
f; ::
50pF
o- - l 9 0 %
....
' - - - ~vss
'
OUTPUT
ENABLE
-I
-1PZH
lL/F/5983-7
TUFI5983·6
5·207
n
Logic Truth Table
Clock
..r
'\..
..r
..r
f
\..
Parallel Outputs
Serial Outputs
Output
Enable
Strobe
Data
Q1
QN
QS·
Q'S
0
X
X
Hi-Z
Hi-Z
07
NoChg.
0
X
X
Hi-Z
Hi-Z
No Chg.
07
1
0
X
NoChg.
1
1
0
0
ON-1
1
1
1
1
ON-1
07
07
07
1
1
1
NoChg. NoChg.
NoChg.
NoChg.
No Chg. NoChg., NoChg.
x=Don't Care
• At the positilie clock edge, information in the 7th shift register stage is
transferred to 08 and Os.
5-208
07
(')
is:
~National
~ Semiconductor
aI
o
CD4099BM/CD4099BC a·Bit Addressable Latch
General Description
Features
The CD4099B is an B-bit addressable latch with three
address. inputs (AO-A2), an active low enable input (Ei,
active high clear input (Cl), a data input (D), and eight
outputs (QO-Q7).
- Wide supply voltage range
Data Is entered into a particular bit in the latch when that
bit is addressed by the address inputs and the enable (E)
is low. Data entry Is inhibited when enable (E) is high.
- Low power TTL
compatibility
When clear (Cl) and enable (E) are high, all outputs are
low. When clear (Cl) is high and enable (E) is low, the
channel demultlplexlng occurs. The bit that is
addressed has an active output which follows the data
input while all unaddressed bits are held low. When operating in the addressable latch mode (E = CL = low),
changing more than one bit of the address could
impose a transient wrong address. Therefore, this
should only be done while in the memory mode
(E = high, CL = low).
- Serial to parallel capability
~
<0
aI
3.0Vto 15V
_ High noise immunity
0.45 VDD (typ.)
fan out of 2 driving 74l
or 1 driving 74LS
- Storage register capability
- Random (addressable) data entry
- Active high demultiplexing capability
- Common active high clear
Connection Diagram
CD4099B
Dual-In-Line Package
U
07....!..
r!!
VDD
~06
CL2.
r!!- 05
02E..!
AD..!.
~03
AI..!.
r!l- 02
A2....!...
.!.!!..Ol
...!.
~OD
Vss
Order Number CD4099BMJ or CD4099BCJ
See NS Package J16A
r!-!-04
Order Number CD4099BMN or CD4099BCN
See NS Package N16E
TlIF/5984·1
TOP VIEW
Truth Table
MODE SELECTION
E
CL
L
L
ADDRESSED
LATCH
UNADDRESSED
LATCH
MODE
Holds Previous Data
Addressable Latch
Holds Previous Data
Reset to "0"
Reset to "0"
Memory
H
L
Follows Data
Holds Previous Data
L
H
follows Data
H
H
Reset to "0"
5-209
Demultiplexer
Clear
()
Absolute Maximum Ratings
Recommended Operating Conditions
-(Note 2)
(Notes 1 and 2)
.Voo DC Supply Voltage -0.5 to +18 Voc
VIN Input Voltage
-0.5 to Voo + 0.5 Voc
-65°C to +150°C
Ts Storage Temperature Range
500mW
Po Package Dissipation
TL Lead Temperature (Soldering, 10 seconds)
260°C
DC Electrical Characteristics
.
-55°C to +125°C
-40°C to +85°C
CD4099BM.(Note 2)
-55OC
Sym Parameter
3.0to 15Voc
Oto Voo Voc
Voo DC Supply Voltage
VIN Input Voltage
TA Operating Temperature Range
CD4099BM
CD4099BC
Conditions
Min
Max
125°C
25°C
Min
Typ
Max
Min
Max
Units
100 Quiescent
Device Current
Voo =5V, VIN=VOOorVss
V oo =10V, VIN=VOOorVss
Voo = 15V, VIN = Voo or Vss
5.0
10
20
0.02
0.02
0.02
5.0
10
20
150
300
600
"A
"A
"A
VOL Low Level
Output Voltage
1101.;; 1"A
Voo=5.0V
Voo=10V
Voo=15V
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
VOH High Level
Output Voltage
1101.;; 1"A
Voo=5.0V
Voo=10V'
Voo=15V
VIL Low Level
Input Voltage
Voo =5.0V, Vo =0.5V or 4.5V
Voo = 10V, Vo = 1.0V or 9.0V
Voo=15V, Vo=1.5Vor 13.5V
VIH High Level
Input Voltage
Voo=5.0V, Vo =0.5Vor 4.5V
Voo=10V, Vo=1.0V or 9.0V
Voo =15V, Vo =1.5Vor 13.5V
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.5
·8.25
3.5
7.0
11.0
10L Low Level
Output Current
(Note 3)
10H High Level
Output Current
(Note 3)
Voo =5:0V, Vo=0.4V
Voo =10V, Vo=0.5V
Voo=15V, Vo=1.5V
Voo-5.0V, Vo-4.6V
Voo=10V, Vo=9.5V
Voo =15V, Vo = 13.5V
0.64
1.6
4.2
0.64
-1.6
-4.2
0.51
1.3
3.4
0.51
-1.3
-3.4
0.88
2.25
8.8
0.88
-2.25
-8.8
0.36
0.9
2.4
0.36
-0.9
-2.4
liN
Input Current
5.0
10
15
2.25
4.5
6.75
-10-5
10-5
-0.1
0.1
4.95
9.95
14.95
V
V
V
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
mA mA
mA
mA
mA
mA
-1~0
1.0
-0.1
0.1
V
V
V
"A
"A
CD4099BC (Note 2) .
-40·C
Conditions
100 Quiescent
Device Current
Voo = 5V, VIN = Voo or Vss
Voo = 10V, V IN = Voo or Vss
Voo = 15V, VIN = Voo or Vss
VOL Low Level
Output Voltage
Ilol';;1"A
Voo =5.0V
Voo=10V
Voo=15V
-
4.95
9.95
14.95
1.5
3.0
4.0
Voo=15V, VIN=OV
Voo =15V, VIN=15V
DC Electrical Characteristics
Sym Parameter
4.95
9.95
14.95
VOH High Level
Output Voltage
1101 .. 1"A
Voo=5.0V
Voo=10V
Voo=15V
VIL Low Level
Input Voltage
Voo = 5.0 V, Vo = 0.5 or 4.5 V
Voo=10V, Vo=1.0Vor9.0V
Voo=15V, Vo=1.5Vor 13.5V
VIH High Level
Input Voltage
Voo = 5.0 V, Vo=0.5Vor 4.5V
Voo = 10V, Vo = 1.0V or 9.0V
Voo = 15V, Vo = 1.5V or 13.5V
Min
Max
25°C
0.02
0.02
0.02
20
40
80
150
300
600
"A
"A
"A
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
1.5
3.0
4.0
5·210
5.0
10
15
2.25
4.5
6.75
3.5
7.0
11.0
2.75
5.5
8.25
Max
,
20
40
80
4.95
9.95
14.95
Min
Units
Max
4.95
9.95
14.95
3.5
7.0
11.0
850C
Typ
"Min
4.95
9.95
14.95
1.5
3.0
4.0
V
V
V
1.5
3.0
4.0
3.5
7.0
11.0
V
V
V
V
V
V
DC Electrical Characteristics
Sym Parameter
(cont'd) CD40998C (Note 2)
-4O"C
Conditions
Min
Max
25"C
Min
Typ
85"C
Max
Min
Max
Units
IOL Low Level
Output Current
(Note 3)
Voo=5.0V, Vo=0.4V
Voo=10V, Vo=0.5V
Voo=15V, Vo=1.5V
0.52
1.3
3.6
0.44
1.1
3.0
0.88
2.25
8.8
0.36
0.9
2.4
mA
mA
mA
IOH High Level
Output Current
(Note 3)
Voo=5.0V, Vo=4.6V
Voo=10V, Vo=9.5V
Voo=15V, Vo =13.5V
-0.52
-1.3
-3.6
-0.44
-1.1
-3.0
-0.88
-2.25
-8.8
-0.36
-0.9
-2.4
mA
mA
mA
liN
Input Current
AC Electrical Characteristics
Symbol
-0.30
0.30
Voo=15V, VIN=OV
Voo=15V, VIN=15V
-10-5 -0.30·
10-5
0.30
-1.0
1.0
,..A
,..A
TA = 25°C, CL = 50pF, RL = 200k, Input tr =tf =20ns, unless otherwise noted.
Typ
Max
Units
tpHL, tpLH Propagation Delay Date to Output
Parameter
Voo=5.0V
Voo=10V
Voo=15V
Conditions
200
75
50
400
150
100
ns
ns
ns
tpLH, tpHL Propagation Delay Enable to Output
Voo=5.0V
Voo=10V
Voo=15V
200
80
60
400
160
120
ns
ns
ns
Voo=5.0V
Voo=10V
Voo=15V
350
160
130
450
200
150
ns
ns
ns
tpLH, tpHL Propagation Delay Address to Output
Voo=5.0V
Voo=10V
Voo=15V
175
80
65
225
100
75
tTHL, tTLH Transition Time (Any Output)
Voo=5.0V
Voo=10V
Voo=15V
100
50
40
200
100
80
ns
ns
ns
tWH, TWL Minimum Data Pulse Width
Voo=5.0V
Voo=10V
Voo=15V
100
50
40
200.
.100
80
ns
ns
ns
tpHL
Propagation Delay Clear to Output
Min
ns
ns
ns
tWH, tWL
Minimum Address Pulse Width
Voo=5.0V
Voo=10V
Voo=15V
200
100
65
400
200
125
ns
ns
ns
tWH
Minimum Clear Pulse Width
Voo=5.0V
Voo=10V
Voo=15V
75
40
25
150
75
50
ns
ns
ns
tsu
Minimum Set·Up Time Data to E
40
20
15
Minimum Hold Time Data to E
80
40
30
120
60
50
ns
ns
ns
tH
Voo=5.0V
Voo=10V
Voo=15V
Voo=5.0V
Voo=10V
VQo=15V
tsu
Minimum Set·Up Time Address to E
Voo=5.0V
Voo=10V
Voo=15V
50
30
20
ns
ns
ns
tH
Minimum Hold Time Address to E
15
10
5
ns
ns
ns
Cpo
Power Dissipation Capacitance
Voo=5.0V
Voo=.10V
Voo=15V
Per Package
(Note 4)
CIN
Input Capacitance
60
30
25
-15
0
0
-50
-20
-15
100
Any Input
ns
ns
ns
pF
7.5
5.0
pF
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed; they are not
meant to Imply that the devices should be operated at these limits. The tables of "Recommended Operating Conditions" and "Electri·
cal Characteristics" provide conditions for actual device operation.
Note 2: Vss 0 V unless otherwise specified.
Nota 3: IOH and IOL are tested one output at a time.
Nota 4: Dynamic power dissipation (Po) Is given by: Po (Cpo + CD Vcc2f + Po; where CL load capacitance; f frequency of opera·
tlon; for further detailS, see application note AN·90, "54C/74C Family Characteristics".
=
=
=
5·211
=
(,)
ID
§
Logic Diagram
CD4099B
C
(,)
iID
~
(,)
5·212
o
Switching Time Waveforms
~--------~H---------~
I
OJ
3:
AD,A1,A2
oc
~
OJ
o
DATA
CLEAR
aD
a7
5-213
~National
~ Semiconductor
CD40106BM/CD40106BC Hex Schmitt Trigger
.General Description
Features
The C040106B Hex Schmitt Trigger is a monolithic
complementary MOS (CMOSI integrated circuit constructed with Nand P-channel enhancement transistors_
The positive and negative-going threshold voltages,
VT+ and VT _, show low variation with respect to
temperature (tvP ·0_0005vfc at VOO = 10VI, and
hysteresis, VT+ - VT_ ;:: 0.2 VOO is guaranteed_
All inputs are protected from damage due to static
discharge by diode clamps to VOO and VSS.
• Wide supply voltage range
• High noise immunity
• Lowpower
TTL compatibility
3Vto 15V
0.7 VOO (typ.1
fan out of 2
driving 74L
or 1 driving
.
74LS
0.4 VOO tvP
0_2 VOO guaranteed
• Equivalent to MM54C14/MM74C14
• Equivalent to MC14584B
• Hysteresis
Schematic Diagram
SWitching Time Waveforms
Voo
INPUT
Vss
INPUT
voo
OUTPUT
OUTPUT
Vss
,,-1f=2Dos
TUFI5985-3
Connection Diagram
Dual-I n-line Package
Order Number CD40106BMJ or CD40106BCJ
See NS Package J14A
Voo
Order Number CD40106BMN or CD40106BCN
See NS Package N14A
\
v,.
TOP VIEW
TLIFI5885-2
5-214
Absolute Maximum Ratings
Recommended Operating Conditions
(Notes 1 and 2)
(Note 2)
Voo dc Supply Voltage
-D.5 to +18 VOC
VIN Input Voltage
-D.5 to Voo +0.5 VOC
TS Storage Temperature Range
-65°C to +150°C
Po Package Dissipation
500mW
TL Lead Temperature (Soldering, 10 sec!'lnds)
260°C
Voo dc Supply Voltage
VIN Input Voltage
TA Operating Temperature Range
CD40106BM
C040106BC
3 to 15 VOC
OtoVoo VOC
--55°C to +125°C
-40° C to +85" C
o
c
8
....
g
CD
3:
(;
c
8....
o
en
OJ
o
DC Electrical Characteristics CD40106BM (Note 2)
'-55°C
SYM
100
VOL
VOH
VT-
VT+
VH
IOL
IOH
"N
PARAMETER
Quiescent Device Current
Low Level Output Voltage
High Level Output Voltage
CONDITIONS
MIN
25°C
MAX
MIN
TYP
125°C
MAX
MIN
MAX
UNITS
VOO= 5V,
Y,N = VOO or VSS
1.0
1.0
30
J1.A
VOO = 10V,
VIN = VOO or VSS
2.0
2.0
60
J1.A
VOO = 15V,
Y,N = VOO or VSS
4.0
4.0
120
J1.A
IIOI
o
8.....
(7)
.....
D:I
s:
(;
~
o
.....
.....
(7)
,D:I
.r>
o
c
~
.....
~
D:I
ENABLET~~------------------------------
__________________________________________
s:
~
Tl,IF/5986-2
CD40161 B, CD40163B Clear is Synchronous for the CD40163B
(;
c
~
.....
~
D:I
.r>
(')
CARRY
OUTPUT
c
~
.....
(7)
w
D:I
s:
(;
8.....
(7)
w
D:I
(')
ENABL£ T
_~
_____________________________________________________________________.,
TLIF/5985-3
5-221
(.)
m Logic Waveforms
~
"""
i
c'
o
CD40160B, ••• CD40162B Decade Counters
CD40161 B, - CD40163B Binary Counters
C'l"E'ARL-J
~~r-------------------------------UlA]~----------------------------
I
UlA]~r-------------------------~--
.:e
"A~'--__________________________
INA~,--
~
"'~'---------------------------~'----------------------------
I·B _____________________________________
CD
~o
cS
m
~
"""
~
(.)
iCD
~
"""
i,
c
(,)
_ _ _ _ _ _ _ _ _ _ __
I.C...r-----J'--__________________________
INC
IND ______--'_____________________________
IND~'--_ _ _ _ _ _ _ _ _ _ __
E.ABlEP.-====~========~~=.=~
-===:;----
ENABLE p ________-'....________________
ENABLE T ________-'
ENABLE T_
CLOCK
CLOCK
DA
DA
DB
DC~'--
_ _ _ _ _ _ _ _ _ ___
DD ________--'r----1~
___________________
CA"Y ____________..Jr-lL.____________________
CARRY ____________..Jr-lL.____________________
13
14
,15
TtIF/!i9B6-4
TUF/59B8-5
Switching Time Waveforms
cS
CD
."""
co
~
o
iCD
\~
"""
~
o
cS
m
~
"""
~
o
:CDe
i
i"""
c
tpHL CLEAR FOR CD40160B AND CD40161B ONLY
TUF/598&-6
Note 1: All input pulses are from generators having
the following characteristics: tr =tf =20 ns PRRS:
1 MHz duty cycle 50%, ZOUT'''' 5On.
Note 2: All times are measured from 50% to 50%.
s:
o
Cascading Packages
CDU.T~~--------------~~--------------~------------
TUFI598&o7
5-222
~National
~ Semiconductor
CD40174BM/CD40174BC Hex 0 Flip-Flop
CD40175BM/CD40175BC Quad 0 Flip-Flop
General Description
The C040174B consists of six positive-edge triggered
Ootype flip-flops; the true output from each flip-flop
are externally available_ The C040175B consists of
four positive-edge triggered Ootype flip-flops; both the
true and complement outputs from each flip-flop are
externally available_
All inputs are protected from static discharge by diode
clamps to VOO and VSS.
Features
• Wide supply voltage range
• High noise immunity
• Low power TTL
compatibility
All flip-flops are controlled by a common clock and a
common clear. Information at the 0 inputs meeting the
set-up time requirements is transferred to the 0 outputs
'on the positive-going edge of the clock pulse. The clearing operation, enabled by a negative pulse at Clear
input, clears all Q outputs to logical "0" and D's
(CQ40175B only) to logical "1,"
•
•
3Vto 15V
0.45 VOO (typ.)
fan out of 2
driving 74L
or 1 driving
74LS
Equivalent to MC14174B, MC14175B
Equivalent to MM74C174, MM74C175
Connection Diagrams
CD40174B
Dual-In-Line Package
CD40175B
Dual-In-Line Package
Voo
116
DB
D5
Q5
D4
04
CLOCK
CLEAR
Q1
Dl
D2
Q2
D3
03
\"ss
TOP VIEW
TOP VIEW
TLIF/5987·'
Order Number CD40174BMJ, CD40174BCJ,
CD40175BMJ or CD40175BCJ
See NS Package J16A
TLtFI59S7·2
Switching Time Waveforms
VDD
Order Number CD40174BMN, CD40174BCN,
CD40175BMN or CD40175BCN
See NS Package N16E
vss--""""'''''I"I
VDD-!-,!,=-f-=-.l
Truth Table
DATA
INPUTS
OUTPUTS
CLEAR
CLOCK
D
0
0*
L
X
X
L
H
H
H
L
X
t
---+r.;;:;------
CLOCK
t
t
H
H
L
H
H
L
L
H
H
X
H
L
X
NC
NC
NC
NC
Vss-!-1'=~f-~~
VDD----f------i-.}=QORO
V~-----~---T
= High level
= Low level
= Irrelevant
tTHl
VDD -----f-----::=i
DOR jj
= Transition from low to high level
NC
= No change
•
=
tTlH
V,,---------"'''--1<--
Q for CD40175B only
t r =tf=20ns
5-223
TUF/5987-3
Recommended Operating Conditions
Absolute Maximum Ratings
I
(Note 2)
(Notes 1 and 2)
. Voo dc Supply Voltage
-0.5 to +18 VOC
VIN Input Voltage
-0.5 to VOO + 0.5 VOC
-65°C to +l50°C
TS Storage Temperature Range
500mW
Po Package Dissipation
260°C
TL Lead Temperature, (Soldering, 10 seconds)
3to15VOC
OtoVOO VOC
VOO dc Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
C040XXXBM
C040XXXBC
-55°C to +125"C
-'10° C to +85° C
DC Electrical Characteristics CD40174BM/CD40175BM (Note 2)
SYM
PARAMETER
-55°C
CONDITIONS
MIN
100
VOL
VOH
VIL
Quiescent Device Current
Low Level Output Voltage
High Level Output Voltage
25°C
MAX
1.0
30
p.A
60
p.A
VOO = 15V, VIN = Voo or Vss
4.0
4.0
120
p.A
1I01--------
ClEAR--.....
TlfF15988-2
5-226
Absolute Maximum Ratings
Recommended Operating Conditions
(Notes 1 a,nd 2)
(Note 2)
VOO de Supply Voltage
~.5to+18VOC
VIN Input Voltage
~.5 to VOO + O.S VOC
TS Storage Temperature Range
-a5"c to +15O"C
Po Package Oissipation
500mW
TL Lead Temperature, (Soldering,10 seconds)
26o"C
VOO de Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
, C040192BM,CD40193BM
C040192BC,.C040193BC
3to15VOC
OtoVOO VOC
-5S·C to +125"C
-4o"C to +8S·C
DC Electrical Characteristics (Note 2) CD40192BM/CD40193BM
SYM
PARAMETER
CONDITIONS
~·c
MIN
25·C
MAX
MIN
TYP
125·C
MAX
MIN
MAX
UNITS
lee
Quiescent Oevice Current
VDe = 5V, VIN = Vee or VSS
Vee = 10V, VIN = Vee or Vss
Vee = 15V, VIN = Vee or Vss
5
10
20',
S
10
20
150
300
600
p.A
I'A
I'A
VOL
Low Level Output Voltage
Vee = SV
Vee = 10V
Vee= 15V
0.05
0.05
0.05
0.05
0.05
0.05
O.OS
0.05
0.05
V
V
V
VOH
High level Output Voltage
VeD = 5V
Vee= 10V
Vee = ISV
Vil
low level Input Voltage
Vee = 5V, Vo = O.SV or 4.5V
Vee = 10V, Vo = IV or 9V
Vee = ISV, Vo = 1.5V or 13.SV
VIH
High level Input Voltage
Vee=5V, Vo = 0.5V or 4.5V
Vee = 10V, Vo = IV or9V
Vee· ISV, Vo = i.sv or 13.5V
3.5
7.0
11.0
3.5
7.0
11.0
IOl
Low Level Output Current
Vee = SV, VO=0.4V
Vee = 10V, Vo = 0.5V
VeD= 15V, VO= 1.5V
0.64
1.6
4.2
O.SI
l.3
3.4
-(l.64
-1.6
-4.2
-(l.51
-1.3
-3.4
(Note 3)
IOH
High Level Output Current
(Not. 3)
liN
Input Current
Vee = 5V, VO=4.6V
Vee = 10V, Vo = 9.5V
Vee= 15V, VO= 13.5V
4.9S
9.95
14.95
4.95
9.95
14.95
4.9S
9.9S
14.95
I.S
3.0
4.0
Vee = 15V, VIN = OV
Vee = 15V, VIN = 15V
V
V
V
I.S
3.0
4.0
V
V
V
3.S
7.0
11.0
V
V
V
0.88
2.25
8.8
0.36
0.9
2.4
rnA
rnA
rnA
-(l.88
-2.25
-8.8
-(l.36
-(l.9
-2.4
rnA
rnA
rnA
-10 5
10-5
-(l.1
0.1
I.S
3.0
4.0
-(l.1
-1.0
1.0
0.1
p.A
p.A
DC Electrical Characteristics (Note 2) CD40192BClCD40193BC
SYM
PARAMETER
CONDITIONS
2S0C
-40"C
MIN
MAX
MIN
TYP
85"C
MAX
MIN
MAX
UNITS
leo
Quiescent Device Current
VOO = SV, VIN = Veo or VSS
VOO = 10V, VIN = Veo or Vss
Veo = 15V, VIN = Voe or Vss
20
40
80
20
40
80
150
300
600
I'A
VOL
Low Level Output Voltage
Vee = SV
VOO = 10V
Vee = 15V
O.OS
0.05
O.OS
O.OS
O.OS
0.05
O.OS
0.05
0.05
V
V
V
VOH
High Level Output Voltage
VOO = 5V
Vee = 10V
VOO = 15V
Vil
Low Level Input Voltage
VIH
High Level Input Voltage
lal
Low Level Output Current
(Not. 3)
laH
Hi9h Level Output Current
(Note 3)
liN
Input Current
=O.SV or 4.5V
= IV or 9V
= I.SV or 13.5V
Voe = 5V, Va =O.SV or 4.5V
VOO = 10V. Va = IV or 9V
Veo = 15V. Va = 1.5Vor 13.5V
Vee = 5V. Va =O.4V
Veo = 10V. Vo =0.5V
Veo = 15V. Va = I.SV
VOO =5V, Vo =4.6V
Voe =10V. Va =9.5V
Voe =15V. Vo = 13.SV
Vee =15V. VIN =OV
Voo = ISV. VIN = ISV
4.95
9.95
14.95
Vee =5V, Va
Vee = 10V, Va
Voe = 15V. Va
4.95
9.9S
14.95
4'.95
9.95
14.95
1.5
3.0
4.0
1.5
3.0
4.0
3,5
7.0
11.0
3.5
7.0
11.0
0.52
1.3
3.6
0.44
1.1
3.0
-(l.52
-1.3
-3.6
-(l.44
-1.1
-3.0
-0.3
,0.3
5-227
I'A
pA
V
V
V
1.5
3.0
4.0
V
V
V
3.5
7.0
11.0
V
V
V
0.88
2.25
8.8
0.36
0.9
2.4
rnA
rnA
rnA
-(l.88
-2.25
-8.B
-(l.36
-(l.9
-2.4
rnA
rnA
rnA
-IO-S
10-5
-0.3
0.3
-1.0
1.0
/JA
"A
II
ur-----------------------------------------------------------------------------~
C
(;)
ial
~
....
~
C
,0
unless otherwise specified .
tpLH
or
-
ns
Or Count Down To 0
VDD; 10V
100
160
ns
80
130
ns
VDD; 15V
Fro,~
Count Up
(;)
120
200
ns
VDD; 10V
50
80
ns
VDD; 15V
40
65
ns
Propagation Delay Time From Count
VDD; 5V
120
200
ns
Down To Borrow
VDD; 10V
50
80
ns
VDD; 15V
40
65
ns
Time Prior To Load That Data Must
VDD; 5V
100
160
ns
Be Present
VDD; 10V
30
50
ns
VDD; 15V
25
40
ns
ns
:::E
al
~
....
~
(;)
tpHL
tpLH
or
Propagation Delay Time From Clear
VDD; 5V
ToO
VDD; 10V
Propagation Delay Time From Load
ToO
tpHL
tTLH
or
Output Transition Time
tTHL
fCL
tRCl
or
Maximum Count Frequency
,
Maximum Co'unt Rise Or Fall Time
tfCl
tWH,tWl
tWH
tWl
CIN
,
VDD; 5V
tpHL
tsu
UNITS
400
Propagation Delay Time
i
c
MAX
250
To Carry
tpHL
TYP
VDD; 5V
tpLH
en
MIN
Propagation Delay Time From Count Up
or
6al
....
CONDITIONS
tpHL
tpLH
or
N
PARAMETER
SYMBOL
Minimum Count Pulse Width
Minimum Clear Pulse Width
Minimum Load Pulse Width
Average Input Capacitance
130
220
60
100
ns
VDD; 15V
50
80
ns
VDD; 5V
\tDD; 10V
VDD; 15V
300
480
ns
120
190
ns
95
150
ns
VDD; 5V
100
200
ns
VDD; 10V
50
100
ns
VDD; 15V
40
80
ns
\
VDD; 5V
2.5
4
MHz
VDD; 10V
6
10
MHz
VDD; 15V
7.5
12.5 -
MHz
VDD; 5V
15
Jls
VDD; 10V
5
JlS
VDD; 15V
1
Jls
VDD; 5V
120
200
ns
VDD= 10V
35
80
ns
VDD= 15V
28
65
ns
VDD = 5V
300
480
ns
VDD = 10V
120
190
ns
VDD = 15V
95
150
ns
100
160
ns
VDD= 10V
40
65
ns
VDD= 15V
.32
55
ns
5
7.5
pF
10
15
pF
.
VDD = 5V
Load and Data
Inputs (A,B,C,Dl
Count UP. Count
Down and Clear
CPD
Power Dissipation Capacity
100
(Note 41
pF
are
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed; they
not meant to imply
that the devices should be operated at these limits. The table of "Recommended Operating Conditions" and "Electrical Characteristics" provides
conditions for actual device operation.
Note 2: VSS = OV unless otherwise specified.
Nota 3: IOH and IOl are tested one output at a time.
Note 4: CpO determines the no load ae power consumption of any CMOS device. For complete explanation, see 54C/74C Family Characteristics
application note, AN-90.
.
_ _ _ _ _ _ _ _. _ ._ _ _ _ _ • _ _ _ _ _ _ _ _ _•......J
5·228
.
.~
AC Electrical Characteristics TA = 25°C, C L = 50 pF, RL = 200 kQ, Input tr = tf = 20 ns,
_
~
~
~
o
c
8
....
fS
Schematic Diagrams
CD40192BM/CD40192BC Synchronous 4-Bit Up/Down Decade Counter
CARRV OUT
DIN
00
,
7
OJ
s:
(;
c
8....
CD
I\)
OJ
~o
o
QD
~
QD
o....
CD
Co)
ctI
s:
(;
c
8.....
TLlFI5988·3
CD
rvss
VOD!U
8
Co)
ctI
o
CD40193BM/CD40193BC Synchronous 4-Bit Up/Down Binary Counter
DrN
,
00
7
TlIF/59884
rvss
VOO!U
8
5-229
Timing Diagrams
,IO
CD40192BM/CD4\l192BC
CLEAR~!-
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
LOAD
DATA
r++--H----------------A:~!--r++--I-i' - ----
~---------------
.-+-+--+-.-----------------
~---------------I
~---------------
COUNT
UP
-----------------
--t-t--++---,
COUNT--+_r~~-_r-------_+__,
DOWN
OUTPUTS
l::~=:
QC _ _
I
DO:
CARRY
-!-1:--++--+...J
--I-1'''-++-t---,
BORROW
SEQUENCE
ILLUSTRATED
CLEAR
COUNT DOWN
PRESET
Sequence:
1. Clear outputs to zero.
2. Load (pre~etl to BCD seven.
3. Count up to eight, nine, carry,
TLfF/598B-S
z~ro.
one and two.
4. Count down to one, zero, borra./V, nine, eight and seven.
)
CD40193BM/CD40193BC
CLEAR
-..flf--------------_-----'--
LOAD
~================
~-------------~-
.-+-+--+...,'- - - - - - - - - - - - - - - - COUNT
UP
--t-+-i-t---,
COUNT--+-r-~-_r-------_t__,
DOWN
CARRY
BORROW
13
SEQUENCE
ILLUSTRATED
CLEAR PRESET
14
o
15
COUNT UP
15
14
131
COUNT DOWN--1
Sequence:
1. Clear outputs to zero.
TUF/59(18.6
2. Load (preset) to binary thirteen.
3, Count up to fourteen, fifteen, carry, zero, one and two.
4. Count down to one, zero, borrow, fifteen, fourteen and thirteen.
5-230
r---------------------------------------------------------------,o
~
~National
~ Semiconductor
Co)
C:J
:s:
o
~
CD4503BM/CD4503BC Hex
Non-Inverting TRI·STATE® Buffer
Q
Co)
C:J
o
General Description
Features
The CD4503B is a hex non-inverting TRI-STATE buffer
with high output current sink and source capability_ TRISTATE outputs make it useful in bus-oriented applications_ Two separate disable inputs are provided_ Buffers
1 through 4 are controlled by the disable 4 input. Buffers
5 and B.are controlled by the disable 2 input. A high level
on eittter disable input will cause those gates on its control line to go into a high impedance state.
• Wide supply voltage range
3.0 VDe to 18 VDe
• TRI-STATE outputs
• Symmetrical turn onlturn off delays
• Symmetrical output rise and fall times
• Pin-for-pin replacement for MM80C97 and MC14503
Schematic and Connection Diagrams
Dual-In-Line Package
VDO
0lS2
INs
OUT 6
INs
OUT 5
IN4
OUT 4
INn'----tI--~-l.---I
J-OUTn
TO
OTHER
WAFERS
9
vss
TUFI5989-'
TLIF/59S9-2
TOP VIEW
Order Number CD4503BMJ or CD4503BCJ
See NS Package J16A
Order Number CD4503BMN or CD4503BCN
See NS Package N16E
Truth Table
Disable
Input
Out
0
0
0
1
0
1
X
1
TRI-STATE
In
x~
Don't Car.
5-231
Absolute Maximum Ratings
Recommended Operating Conditions
(Notes 1 and 2)
(Note 2)
-0.5V to +18V
VOO - Supply Voltage
VIN - Input Voltage
-0.5V to +0.5V
_65°C to +150°C
TS - Storage Temperature F;!ange
Po - Power Dissipation
500mW
TL - Lead Temperature (soldering, 10 seconds)
260°C
T A - Operating Temperature Range
C04503BM
C04503BC
3V to 15V
VOO - Supply Voltage
-55°C to +125°C
_40°C to +85°C
DC ,Electrical Characteristics C04503BM (Note 2)
+2Soc
_55°C
Sym
Units
Min
IDD Quiescent Device Current
VOL Low Level Output Voltage
VOH High Level Output Voltage
VIL Low Level Input Voltage
I
VIH High Level Input Voltage
IOL
Low Level Output Current
(Note 3)
IOH High Level Output Current
(Note 3)
VDD = 5V,
VIN = VDD or VSS
VDO = 10V,
VIN = VOD or VSS
VDD = 15V,
VIN = VDD or VSS
VIN = VDD or 0
VDD = 5V
VDD = 10V
VDD = 15V
Input Curreflt
Max
Min
VIN = VDD or 0
VDD = 5V
VDO = 10V
VDD = 15V
Max
Min
Max
1
30
/lA
2
2
60
/lA
4
4
120.
/lA
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
4.95
9.95
14.95
VDO= 5V,
Vo = 4.5V or 0.5V
VOO = 10V,
Va = 9.0V or 1.0V
VOO= 15V,
Va = 13.5V or 1.5V
Typ
1
0.05
0.05
0.05
0
0
0
4.95
9.95
14.95
~5
4.95
9.95
14.95
10
15
V
V
V
1.5
2.25
1.5
1.5
V
3.0
4.50
3.0
3.0
V
4.0
6.75
4.0
4.0
V
VOO= 5V,
VO= 0.5V or 4.5V
VDO = 10V;
Va = 1.0V or 9.0V
VOO=·15V,
Va = 1.5Vor 13.5V
3.5
3.5
2.75
3.5
V
7.0
7.p
5.5
7.0
V
11.0
11.0
8.25
11.0
V
VDD
VDD
VDD
VDD
2.80
3.00
7.85
19.95
2.30
2040
6.35
16.10
2.55
2.75
7.00
25.00
1.60
1.75
4045
11.30
mA
mA
mA
mA
= 4.5V, VOL = OAV
= 5.0V, VOL = 004 V
= 10V, VOL = 0.5V
= 15V, VOL = 1.5V
-1.28
VDD = 5V, VOH = 4.6V
VDO = 10V, VOH = 9.5V -3.20
VDD = 15V, VOH = 13.5V -8.20
IOZ TRI-STATE Leakage Current VOD = l5V
liN
+125°C
Conditions'
Parameter
VDD = 15V
-1.02
-2.60
-6.80
-1.76
-4.5
-17.6
-0.72
-1.8
-4.8
mA
mA
mA
±0.1
±10-4
±0.1
±1.0
/lA
±0.1
±10-4
±O.l
±1.0
/lA
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The tables of "Recommended Operating Conditions" and "Electrical Characteristics" provide
conditions for actual device operation.
Note 2: VSS = OV unless otherwise specified.
Note 3: IOH and IOl are tested one output at a time.
5-232
DC Electrical Characteristics C04503BC (Note 2)
+25·C
-40·C
Parameter
Sym
Min
IOD Quiescent Device Current
+85°C
Conditions
Max
Min
Typ
4
VOO = 5V,
VIN = VOO or VSS
VOO= 10V,
VIN = VOO or VSS
VOO = 15V,
8
,
16
Max
Min
. Max
Units
4
30
J'.A
8
60
J'.A
16
120
J'.A
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
VIN = VOO or VSS
VOL Low Level Output Voltage
VOH High
~evel
Output Voltage
VIL Low Level Input Voltage
VIH High Level Input Voltage
VIN = VOO or 0
VOO = 5V
VDO = 10V
VOO = 15V
0.05
0.05
0.05
VIN = VDO orO
VOD = 5V
VOO = 10V
VOD = 15V
4.95
9.95
14.95
VOO= 5V,
Va = 4.5V or 0.5V
VOO= 10V,
Va = 9.0V or 1.0V
VOO = 15V,
Va = 13.5Vor 1.5V
VOO= 5V,
Va = 0.5V or 4.5V
VOO= 10V,
Va = 1.0V or 9.0V
VOO = 15V,
Va = 1.5V or 13.5V
Input Current
1.5
2.25
1.5
1.5
V
3.0
4.50
3.0
3.0
V
4.0
6.75
4.0
4.0
V
3.5
V
7.0
7.0
5.5
7.0
V
11.0
11.0
8.25
11.0
V
2.30
2.5
6.5
16.50
1.95
2.10
5.45
13.80
2.65
2.75
7.0
25.00
1.60
1.75
4.45
11.30
mA
mA
mA
mA
-1.04
VOO = 5V, VOH "" 4.6V
VOO = 10V, VOH = 9.5V . -2.60
VOO = 15V, VOH = 13.5V -7.2 .
liN
V
V
V
2.75
IOH High Level Output Current
(Note 3)
TRI·STATE Leakage Current
4.95
9.95
14.95
3.5
VOD
VOO
VOO
VOO
ITL
4.95
9.95
14.95
3.5
IOL Low Level Output Current
(Note 3)
= 4.5 V, VOL = 0.4 V
= 5.0V, VOL = 0.4 V
= 10V, VOL = 0.5V
= 15V, VOL"" 1.5V
0
0
0
VDO = 15V
VOO = 15V
-0.88
-2.2/
-6.0
-1.76
-4.50
-17.6
mA
mA
mA
-0.7
-1.8
-4.8
±0.3
±10-4
±0.3
±1.0
J'.A
±0.3
±1O-5
±0.3
±1.0
J'.A
AC Electrical Characteristics C04503B
TA = 25°C, CL = 50 pF, R L = 200 kn, Input tr = tf = 20 ns, unless otherwise specified.
Symbol
,
Parameter
Conditions
Min
Typ
Max
Units
tPHL, tPLH
Propagation Oelay Time
VOD = 5V
VOO = 10V
VOD = 15V
75
35
25
100
40
30
ns
ns
ns
tPLZ, tPHZ
Propagation Delay Time, Logical Level to High Impedance State
VDD = 5V
VOO = 10V
VOO=15V
80
40
35
125
90
70
ns
ns
ns
tpZL, tpZH
Propagation Oelay Time, High Impedance State to Logical Level
VOO=5V
VOO= 10V
VOD = 15V
95
40
35
175
80
70
ns
ns
ns
tTLH
Output Rise Time
VOO = 5V
VOO = 10V
VOO = 15V
45
23
18
80
40
35
ns
ns
ns
tTHL
Output Fall Time
VOO = 5V
VOO = 10V
VDD = 15V
45
23
18
80
40
35
ns
ns
ns
5·233
AC Test Circuits and SWitching Time Waveforms
CMOS to CMOS
\ TLIF/5989-3
TlfFI5989-4
tpHZ and tpZH
tPLZ and tpZL
Voo
!
'b"'~'
INPUT
TUFI5989-5
-
I.Ok OUTPUT
TLIF/5989-6
tPHZ
VOO
t~LZ
VOO
6L
DISABLE
ov
VOH
DISABLE
ov
-
OV
tPLZ
Voo
90%
OUTPUT
1m rI~Y
OUTPUT
VOL
TLfFI5989-8
TL/F/59f39.7
tpZH
tpZL
~OO
VOO~5
"....:~r.n-,O%
DISABLE
OV
VOO
t,m\
90%
OUTPUT
OUTPUT
VOL
OV----
TLIF/S989-10
TL/F/5981J.9
Note: Oelays measured with input t r, tl .;; 20 ns.
5-234
r--------------------------------------------------------,o
o
~National
t;;
....
~ Semiconductor
o
III
s::
o
~....
CD4510BM/CD4510BC BCD Up/Down Counter
CD4516BM/CD4516BC Binary Up/Down Counter
o
III
f)
o
General Description
The CD4510BM/CD4510BC and CD4516BM/CD4516BC
are monolithic CMOS up/down counters which count in
BCD and binary, respectively.
All inputs are protected against static discharge by
diode clamps to both Voo and Vss.
The counters count up when the up/down input is at
logical "1" and vice versa. A logical "1" preset enable
signal allows information at the parallel inputs to preset
the counters to any state synchronously with the clock.
The counters are advanc;ed one ·count at the positive·
going edge ofthe clock if the carry in, preset enable, and
reset inputs are at logical "0". Advancement is inhibited
when any of these three inputs are at logical "1". The
carry out signal Is normally at logical "1" state and goes
to logical "0" when the counter reaches its maximum
count In the "up" mode or its minimum count in the
"down" mode, provided the carry input is at logical "0"
statEl' The counters are cleared asynchronously by
applying a logical "1" voltage level at the reset input.
Features
Connection Diagram
Dual~ln~Line
~
en
....
(7) .
III
s::
3.0Vto 15V
• Wide supply voltage range
0.45 Voo (typ.)
• High noise immunity
fan out of 2 driving 74L
or 1 driving 74LS
• Low power TTL
compatibility
o
~....
(7)
III
o
• Parallel load "jam" inputs
• Low quiescent power dissipation
0.25 "W/package
(typ.) @ Vee = 5.0 V
• Motorola MC14510, MC14516 second source
Package
PARALlel INPUTS
, P3
Q3
CLOCK
•
P2'
13
14
15
QZ
UP/DOWN RESET
11
12
10
Order Number CD4510BMJ,
CD4510BCJ, CD4516BMJ
or CD4516BCJ
See NS Package J16A
Order Number CD4510BMN,
CD4510BCN, CD4516BMN
or CD4516BCN
See NS Package N16E
PRESET
• P4
Q4
ENABLE
PI
PARALLEL INPUTS
Truth Table
CARRY
IN
Ql
CARRY
OUT
TOP VIEW
TLIFI599().1
PRESET
ENABLE
CARRY
IN
X
1
X
Reset to zero
0
0
0
0
01
X
X
X
X
x
Set to P1, P2, P3, P4
0
0
1
Count up
0
Count down
x
x
No change
No change
J
J
. ""\..
X
0
0
0
0
X
J '" positive transition
""'\...
X
II
UP/DOWN
OUTPUT
FUNCTION
RESET
CLOCK
negative transition
= don't care
5·235
•
o
Ie
co
....
Il)
C!i
o
iIe
Absolute Maximum Ratings
Recommended Operating Conditions
(Notes 1 and 2)
(Note 2)
VOO de Supply Voltage
~.5V to +ISV
VIN Input Voltage
~.5V to VDD +0.5V
TS Storage Temperature Range
...£5°C to +150°C
Po Package Dissipation
500mW
TL Lead Temperature (Soldering, 10 seeoncis)
260°C
VDD de Supply Voltage
VIN Input Voltage
TA Operating Temperature Range
CD4510BM, C045f6BM
CD4510BC, CD4516BC
3V to 15V
Oto VOD
:;55°C to +125°C
-40°C to +S5°C
....co
Il)
C!i
o
cS
DC Electrical Characteristics CD4510BMICD4516BM (Note 2)
Ie
SYM
Il)
~
IDD
o
;0-
PARAMETER
Quiescent Device Current
c
o
iIe
o....
VOL
Low Level Output Voltage
C!i
o
VOH
VIL
High Level Output Voltage
Low Level Input Voltage
High Level Input Voltage
High Level Output Current
(Note 3)
liN
Input Current
MIN
MAX
UNITS
5
150
0.1
10
300
J1.A
VOD = 15V, VIN = VDO or VSS
20
0.15
20
600
J1.A
V
J1.A
VIH=VDO, VIL=OV,IIOI< 1 J1.A
5V ,:
0.05
0
0.05
0.05
VDO = 10V
0.05
0
0.05
V
VDD = 15V
0.05
0
OW
0.05
0.05
V
0
VIH = VDD, VIL = OV, 1101< 1 J1.A
VDD = 5V
4.95
4.95
5
4.95
V
VDD = 10V
9.95
9.95
10
9.95
V
VDD = 15V
14.95
14.95
15
14.95
V
1I01--
CI
ClK 01
02
.I
I
.
OJ
04
I
I,
R
ClK
Q1
02
OJ
04
en
CD
i:
-
0
C
olio
....
en
.! ! .! L
J
OUTPUTS
CLOCK
RESET
TUFf5990-3
Ripple Clocking
UP/DOWN
PRESET
ENABLE
.
PARAllEL INPUTS
U/O
CLOCK
....
(II
(II
R
OUTPUTS
r
Sl
0
colio
PE
"
I
PI
P2
I f
PJ
P4
CI
U/O
CO
R
ClK
Q1
02
J
I
OJ
.
04
l
PARAllEL INPUTS
P-It
PE
'I
I
PI
P2
T J'
PJ
CI
CO
R
ClK
I IJ
01
",I
OUTPUTS
02
OJ
.
RESET
---1)-
TO NEXT
STAG E
P-
04
I I
OUTPUTS
-
P4
"
~
:0TL/F/599I).4
5·239
CD
0
o
a:I
,..
CD
Schematic Diagrams
~
c
o
~
a:I
CD
,..
TOGGLE LOGIC ITU
e
r-------,
II)
"lit
I
cS
PRESET I
ENABLE
a:I
o,..
II)
"lit
I
l _____:
C
o
-----H
CARRY IN 0.'
'CARRY
OUT
C
o
~
o
,..
a:I
VDD~16
VSSa8
II)
g
o
, .,
11
14
Q2
Q3
2 .,
TLIF/5990-5
FIGURE 1. CD4510
TOGGLElOGIC(TL!
e
.------,
I
I
L
PRESET 1
ENABLE
----1>-...,..-1
CARRY IN 0.'
I
I
_____1
} CARRY
OUT
,
.,
11
140.l
QZ
*Flip-flop toggles at the positive-going edge of clock lei if Toggle Enable
ITEI is at logical "'" and Preset Enable IPEI is at logical "0"
FIGURE 2. CD4516
5-240
1 ••
TUFI5990-6
logic Waveforms
CD4510BM/CD4510BC
CLOCK
iLfL fl- ll-fI-fI- L fl-Lfl-LfI- rL L
rL L
r-rf.
CARRV IN
i
UP/DOWN
-,
i
I
I
I
i
I
J2
i
I
I
I
I
I I
JJ
1..-
f--
'--
1..-
'--
.2
r-
i'--
..-
1'---
,I
!
I
I
I
1'---
I
,
i
..-
I
I
I
J.
r-
1'---
1.--
1.-I....-
I
!
CARRY OUT
o
COUNT
1
Z
J
• , ,
7
•
IY ,
I
, I
7
5
I
I
J
•
.-- 1'--- ,.......,
in
1'---
,
-
I
I
!
.J
••
I
In
I
i
:
I
JI
.,
!
I
,
RESET
PRESET
ENABLE
ll- L ll- L rL
,
Z
1
!
I
I
1
:
i
I
0
rr1.-- f---,
r-1.-- ,.......,
....-
It,- , ,
0
7
TI../F/5900·7
CD~516BM/CD4516BC
CLOCK
rt- fl... rt- Il-rt- rL rL fl... rL fl- lLIL:Lrt- IL rL rt- rr-rL~n..rt-n-
CARRY IN
I
UP/DOWN
PRESET
ENABLE
,
1
h
r r--
I
I
RESET
I
1
JI
!
I
JZ
:
1
I
J4
01
OZ
-
1'--
r-.
1'--
.-- " -1.--
1"-
1.--
I"-~
1'--
r--
I
:
-
OJ
COUNT
'--
~
i
7
, ,
10
II
12
IJ
14
I~
,
•
i
7
, I
I
I
I
, ,
n. r--
,II
I
04
CARR\' OUT
i
I
JJ
,
I
4
J
I
2
~
nt--1
i
,
0
17
15
!
0
TUFI5990-8'
5-241
(J
In
,..
,.. ~NatiOnal
~
Semiconductor
(J
~
,..
,.. CD4511BM/CD4511BC BCD-to-7 Segment
~ Latch I Decoderl Driver
In
,
(J
General Description
Features
The CD4511BM/CD4511BC BCD-to-seven segment latch/
decoder/driver is constructed with complementary MOS
(CMOS) enhancement mode devices and NPN bipolar
output drivers in a single monolithic structure. The circuit provides the functions of a 4-bit storage latch, an
8421 BCD-to-seven segment decoder, and an output drive
capability. Lamp test (LT), blanking (BI), and latch enable
(LE) inputs are used to test the display, to turn-off or pulse
modulate the brightness of the display, and to store a
BCD code, respectively. It can be used with seven-segment light emitting diodes (LED), incandescent, fluorescent, gas discharge, or liquid crystal readouts either
directly or indirectly.
• Low logic circuit power dissipation
Applications include instrument (e.g., counter, DVM, etc.)
display driver, computer/calculator display driver, cockpit
display driver, and various clock, watch, and timer uses.
'\
• High current sourcing outputs (up to 25mA)
• Latch storage of code
• Blanking input
• Lamp test provision
• Readout blanking on all illegal Input combinations
• Lamp Intensity modulation capability
• Time share (multiplexing) facility
• Equivalent to Motorola MC14511
,
,
Connection Diagram
INPUTS
Dual-In-Line Package
• ..2.
U
.!!..VOD
2.!...
.!!.,
c2.
iT....!.
"..!
LE.l
.!!.a
0.1
.1!.c
• ..2.
.!!.d
Vss..!.
l....
l
TLIF/5991·1
Order Number CD4511BMJ or CD4511 BCJ
See NS Package J16A
.
c
d
e
f
9
DISPLAY
1
1
1
1
1
1
1
B
0
1
0
1
1
0
0
0
1
0
1
.0
1
0
1
1
1
0
1
0
0
1
1
1
0
1
0
1
1
0
1
0
0
0
1
0
0
1
0
1
1
0
1
BI
LT
D
C
B
A
X
X
X
X
X
X
X
0
1
0
1
X
X
X
X
1
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
0
0
1
0
1
1
1
1
0
1
0
0
0
0
1
1
0
1
0
1
0
0
0
0
1
1
X
0
1
0
1
0
0
0
0
J
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
X
0
0
1
1
1
1
X
1
OUTPUTS
b
LE
0
0
0
0
E..b
TOP VIEW
,
Truth Table
1
1
1
1
1
0
0
0
0
0
o
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
.
X
0
0
1
0
1
0
0
0
0
0
0
0
1
0
1
2
3
4
1
1
5
1
1
0
0
1
1
0
6
7
0
1
1
1
1
0
0
0
8
9
0
0
0
0
0
0
0
0
x = Don't ears
·Oepends upon the BCD code applied during the 0 to 1 tranSition of LE
Order Number CD4511BMN or CD4511BCN
See NS Package N16E
Displav
Segment Identification
.
,
·[-:-/b
·f
d ,.
In1/121:1ILfISlb171Blql
•
•
1
2
3
S
6
1
6
9
Tl!IF/5991·2
TLIFI5991·3
5-242
Absolute Maximum Ratings
Recommended
Ope~ating
(Notes 1 and 2)
(Note 2)
VDD dc Supply Voltage.
VIN Input Voltage
VDD dc Supply Voltage
VIN Input Voltage
.TS Storage Temperature Range
T A Operating Temperature Range
-Q.5V to +18V
-Q.5V to VDD +O.5V
--65"C to +150"C
PD Package Dissipation
500mW
. TL Lead Temperature ISoldering. 10 seconds)
260"C
Conditions
o
c
~
.....
.....
CD
s::
CI1
3V to 15V
OtoVDD
~5"C
CD4510BM. CD4516BM
CD4510BC.C04516BC
to +125"C
-40"C to +85"C
(;
c
C1
.....
.....
CD
o
DC Electrical Characteristics CD4511BM
Sym
Min
100
Quiescent
Voo =5V, VIN=VOOor Vss
Supply Current Voo = 10V, VIN = Voo or Vss
Voo = 15V, VIN = Voo or Vss
VOL
Output Voltage Voo=5V
Logical "0"
Voo=10V
Level
Voo=15V
V OH
Output Voltage Voo=5V
Logical "1"
Voo=10V
Level
Voo=15V
~L
Low Level
Input Voltage
Voo = 5V, VOUT= 3.8Vor 0.5V
Voo= 10V, Vour= 8.8Vor 1.0V
Voo= 15V, Vour= 13.8Vor 1.5V
VIH
High Level
Input Voltage
Voo =5V, Vour =0.5Vor3.8V
Voo= 10V, Vour = 1.0V or 8.8V
Voo= 15V, VOUT= 1.5V or 13.8V
Voo= 5V, IOH=OmA
VOH . Output
(Source) Drive Voo= 5V, IOH=5mA
Voltage
V oo =5V,l oH =10rnA
Voo = 5V, IOH = 15 rnA
Voo = 5V, IOH = 20 rnA
Voo =5V, IOH=25 rnA
-
Voo= 10V, IOH=O rnA
Voo = 10V, IOH = 5 rnA
Voo= 10V, IOH = 10 rnA
Voo= 10V, IOH = 15 rnA
V oo =10V, IOH=20 rnA
Voo. = 10V, IOH = 25 rnA
V oo =15V, IOH=O rnA
Voo = 15V, IOH = 5 rnA
Voo= 15V, IOH= 10 rnA
V oo =15V,l oH =15rnA
V oo =15V,l oH =20rnA
V oO =15V, IOH=25 rnA
IOL
Low Level
V oo=5V, VoL =0.4V
Output Current V oo =10V, VoL =0.5V
V oo =,5V, Vo L =1.5V
liN
Input Current
Voo=15V, VIN=OV
V oo =15V, VIN =15V
+ 125°C
+ 25°C
-55°C
Conditions
Parameter
Max
Min
Typ
Max
5
10
20
0.Q1
0.01
4.1
9.1
14.1
0
0
0
4.1
9.1
14.1
1.5
3.0
4.0
Min
Units
Max
5
10
20
150
300
600
~
~
~
0.Q1
0.Q1
0.05
0.05
V
V
V
4.1
9.1
14.1
4.57
9.58
14.59
2
4
6
V
V
V
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
3.5
7.0
11'.0
3.5
7.0
11.0
3
6
9
3.5
7.0
11.0
V
V
V
4.1
4.1
4.1
3.9
3.9
3.4
3.4
4.57
4.24
4.12
3.94
3.75
3.54
V
V
V
V
V
V
9.1
9.1
9.1
9.0
9.0
8.6
8.6
9.58
9.26
9.17
9.04
8.9
8.75
14.1
14.1
14.0
14.0
13.6
13.6
0.64
1.6
4.2
0.51
1.3
3.4
I
-0.10
0.10
Nola 1: Devices should not be connected with power on.
5·243
14.59
14.27
14.18
14.07
13.95
13.8
3.5
3.0
8.6
B.2
14.1
10- 5
V
V
V
V
V
V
13.6
,
0.88
2.25
8.B
_10- 5
V
V
V
V
V
V
13.2
0.36
0.9
2.4
-0.10
0.10
,
:"1.0
1.0
rnA
rnA
rnA
~
/LA
o
ED
.,..
.,.. DC Electrical Characteristics CD4511BC
~
,
c
o
~
ED
.,..
.,..
~
Parameter
Conditions
Min
Max
Quiescent
Voo=5V
Supply Clirrent VOD = 10V
Voo=15V
20
40
80
VOL
Output Voltage V oD =5V
Logical ;'0"
Voo=10V
Level
Voo=15V
0.01
0.01
VOH
Output Voltage Voo=5V
Logical "1"
Voo= 10V
~evel
Voo = 15V
V IL
Low Level
Input Voltage
100
c
o
+ 25·C
-40·C
Sym
V IH
:
VOH
Min
0
0
0
4.1
9.1
14.1
4.1
9.1
14.1
1.5
3.0
4.0
Voo = 5V, VOUT = 3.8V or 0.5V
Voo= 10V, VouT =8.8Vor 1.0V
Voo= 15V, VOUT= 13.8Vor 1.5V
2
6
3.5
7.0
11.0
Output
(Source) Drive
Voltage
4.1
4.1
3.6
3.6
2.8
2.8
9.1
9.1
8.75
8.75
8.1
8.1
14.1
14.1
13.75
13.75
13.1
13.1
0.52
1.3
3.6
0.44
1.1
3.0
IOH=O rnA
IOH =5 rnA
iOH = 10 rnA
IOH = 15 rnA
IOH =20 rnA
IOH = 25 rnA
Voo = 10V, IOH = 0 rnA
V Do =10V,IOH=5rnA
Voo = 10V, IOH = 10 rnA
Voo = 10V, IOH = 15 rnA
Voo = 10V, IOH = 20 rnA
Voo = 10V, IOH = 25 rnA
Voo = 15V, IOH = 0 rnA
Voo= 15V, IOH =5 rnA
Voo =15V,loH=10rnA
. Voo=15V, IOH=15 rnA
V DD = 15V, IOH = 20 rnA
V oo =15V, IOH=25 rnA
IOL
Low Level
V oo =5V, VOL =O.4V
Output Current V DO =10V, VoL =0.5V
VDO=15V, VoL =1.5V
liN
.Input Current
,
-0.30
0.30
Voo=15V, VIN=OV I
Voo=15V, V IN =15V
3.5
7.0
11.0
+ 85·C
Max
Min
150
300
600
,.A
,.A
0.01
0.01
0.05
0.05
V
V
V
1.5
3.0
4.0
V
V
V
1.5
3.0
4.0
S·
9
4.57
4.24
4.12
3.94
3.75
3.54
.
V
V
V
4.1
V
V
V
V
V
V
2.5
V
V
V
V
V
V
9.1
8.45
7.8
14.1
14.59
14.27
14.18
14.07
13.95
13.8
V
V
V
V
V
V
13.45
'.
,12.8
0.88
2.25
8.8
0.36
0.9
2.4
rnA
rnA
rnA
p.A
-1.0
1.0
-0.30
0.30
,.A
"
,
,
5·244
V
V
V
3.5
7.0
11.0
3.3
9.58
9.26
9.17
9.04
8.9
8.75
10- 5
p.A
4.1
9.1
14.1
3
_10- 5
Units
Max
20
40
80
4.57
9.58
14.59
4
High Level
V 00 = 5V, VOUT = 0.5V or 3.8V
Input Voltage' Voo = 10V, VOUT = 1.0V OF 8.8V
Voo= 15V, VOUT= 1.5Vor 13.8V
Voo=5V,
Voo =5V,
Voo = 5V,
Voo = 5V,
Voo=5V,
Voo = 5V,
Typ
o
C
AC Electrical Characteristics
./:10
........
tD
UI
TA" 25°C and CL " 50 pF. typical temperature coefficient for all values of VDD " 0.3%rC.
SYM
PARAMETER
CONDITIONS
CD4511BX
MIN
TYP
MAX
UNITS
C,N
Input Capacitance '
V'N=O
5.0
7.5
pF
tr
Output Rise Time (Figure la)
VDD" 5V
VDD= 10V
VDD = 15V
40
30
25
80
60
50
ns
ns
ns
tf
Output Fall Time (Figure la)
VDD" 5V
VDD" 10V
VDD" 15V
125
75
65
250
150
130
ns
ns
ns
tpLH
Turn-Off Delay Time (Data) (Figure la)
VDD" 5V
VDD" 10V
VDD" 15V
640
250
175
1280
500
350
ns
ns
ns
tpHL
Turn-On Delay Time (Data) (Figure la)
VDD" 5V
VDD" 10V
VDD" 15V
720
290
195
1440
580
400
ns
ns
ns
tPLH
Turn-Off Delay Time (Blank) (Figure la)
VDD" 5V
VDD" 10V
VDD" 15V
320
130
100
640
260
200
ns
ns
ns
tPHL
Turn-On Delay Time (Blank) (Figure la)
VDD" 5V
VDD" 10V
VDD" 15V
485
200
160
970
400
320
ns
ns
ns
tpHL
Turn·Off Delay Time (Lamp Test) (Figure la)
VDD" 5V
VDD" 10V'
VDD" 15V
313
125
90
625
250
180
ns
ns
tpHL
Turn-On Delay Time (Lamp Test) (Figure la)
VDD" 5V
VDD" 10V
VDD" 15V
313
125
90
625
250
180
ns
ns
ns
tSETUP
Setup Time (Figure lb)
VDD" 5V
VDD= 10V
VDD" 15V
180
76
40
tHOLD
Hold Time (Figure 1b)
VDD" 5V
VDD" 10V
VDD" 15V
0
0
0
PWLE
Minimum Latch Enable Pulse Width (Figure le)
VDD" 5V
VDD" 10V
VDD" 15V
520
220
130
5·245
-
90
38
20
ns
ns
ns
-90
-38
-20
ns
ns
ns
260
110
65
ns
ns
ns
:s:
oc
........~
tD
o
(,)
m Switching Time Waveforms
~
~
II)
lal
~
C
-m
INPUT
(,)
::E
v,,
OUTPUT
~
ov
.In
~
(bl
C
VDO
LE
(,)
v" ___________,,.-;'.::;O.::.;'::.":.;";.'_
OUTPUT
ov _ _ _ _ _ _ _ _ _..J'~_.!2!'.!!.O~__
21irs
2O"
LE
(STROBED)
v•• - - - - i
1V------1"""::;......,.
TUF,.,...
FIGURE 1.
'_.
Typical Applications
Light Emitting Diode (LEDI Readout
v,,
VDO
COMMON
COMMON
ANODE LED
CATHODE LED
TUFISQ91.e
'TUF/598t·5 '
Liquid ,Crystal (LCI Readout
Ga. Discharge Readout
'DD
APPROPRIATE
VOLTAGE
TUF/99'-7
DlrICt de IInn.f LC:S Ro1ltCDmlllllldad 'Of lifI.t LC mtfoutl.
5-246
.-----------------------------------------------------------------.n
~
....
....
Typical Applications (Cont'd.)
m
Fluorescent Readout
Incandescent Readout
i:
v••
n
c
v••
~
....
....m
DIRECT
(LOW BRIGHTNESS)
n
TLIF/5991-9
··A fll.mant p'.. Wlrm reslstof is rtCommended III reduce filament
dlilfm.1 slIocll and incllase tlteefftctlve cold resu:tlnce Dflh.
faJ.enL
TUFI5991·10
5-247
o
~
c~
o
II?A National
~ Semiconductor
~
CD4512BM/CD4512BC 8-Channel Buffered Data Selector
....
General Description
Features
The CD4512BM/CD4512BC buffered 8-channel data selector Is a complementary MOS'(CMOS) circuit constructed
with N- and P-channel enhancement mode transistors.
This data selector is primarily used as a digital signal
multiplexer selecting 1 of 8 Inputs and routing the signal
to a TRI-STATE@output. A high level at the Inhibit input
forces a low level at the output. A high level at the Output
Enable (OE) input forces the output into the TRI-STATE
condition. Low levels at both the Inhibit and (OE) inputs
allow normal operation.
• Wide supply voltage range
m
('I
II)
~
c
o
3.0V-15V
0.45 Voo (typ.)
• High noise immunity
• TRI-STATE output
• Low quiescent power dissipation
.0.25"W/package
(typ.) @ Vcc=5.0V
• Plug-in replacement for Motorola MC14512
Connection Diagram and Truth Table
Dual-In-Line Package
ADDRESS INPUTS
'i:
i
A'
14
15
13
INHIBIT
II
12
X7
10
Order Number CD4512BMJ or CD4512BCJ
See NS Package J16A
Order Number CD4512BMN or CD4512BCN
See NS Package N16E
2
I
3
4
5
7
6
, JB
XO
XI
X2
Xl
X4
X5
X6
VSS
TDPVIEW
TL.IFf5993-1
ADDRESS INPUTS
CONTROL
INPUTS
OUTPUT
C
B
A
INHIBIT
OE
Z
O'
0
0
0
XO
0
0
1
0
0_
1
0
0
0
0
Xl
0
0
1
1
0
0
X3
1
0
0
0
0
X4
1
0
1
0
0
X5
1
1
0
0
1
1
1
0
0
0
X6
X7
0
0
0
0
0
0
1
0
0
0
1
Hi-Z
,
X2
o= Don't care
Hi-Z = TRI-8TATEcondition
Xn
= Data at input n
\
5-248
o
Absolute Maximum Ratings
Recommended Operating Conditions
(Notes 1 & 2)
(Note 2)
Voo Supply Voltage
-0.5 to +18 Voe
VIN Input Voltage
-0.5 to Voo + 0.5 Voe
Ts Storage Temperature Range
-65°C to +150°C
Po Package Dissipation
500mW
260°C
TL Lead Temperature (Soldering, 10 seconds)
Voo DC Supply Voltage
VIN Input Voltage
TA Operating Temperature Range
CD4512BM
'CD4512BC
DC Electrical Characteristics
Sym Parameter
3.0to 15Voe
Oto Voo Voe
Max
Min
125°C
Typ
Max
Min
Max
Units
J.tA
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
.fJ.A
fJ.A
VOL Low Level
Output Voltage
Voo=5.0V
Voo=10V
Voo=15V
lIoLi <1 p.A
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
VOH High Level
Output Voltage
Voo=5.0V
Voo=10V
Voo = 15V
IloHI <1 p.A
VIL Low Level.
Input Voltage
Voo=5.0V, Vo=0.5V
Voo = 10V, Va = 1.0V
Voo=15V, Vo=1.5V
VIH High Level
Input Voltage
Voo=5.0V, Vo=4.5V
Voo=10V, Vo=9.0V
Voo= 15V, Va = 13.5V
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.50
8.25
3.5
7.0
11.0
V
V
V
10L Low Level
Output Current
(Note 3)
Voo=5.0V, Vo=O.4V
Voo=10V, Vo=0.5V
Voo=15V, Vo=1.5V
0.64
1.6
4.2
0.51
1.3
3.4
0.78
2.0
7.8
0.36
0.9
2.4
mA
mA
mA
IOH High Level
Output Current
(Note 3)
Voo=5.0V, Vo=4.6V
Voo=10V, Vo=9.5V
Voo = 15V, Vo = 13.5V
-0.25
-0.62
-1.8
-0.14
-0.35
-1.1
mA
mA
mA
liN Input Current
Voo=15V, VIN=OV
Voo=15V, VIN=15V
-0.1
0.1
-10 5
10-
-0.1
0.1
-1.0
1.0
fJ.A
fJ.A
loz TRI·STATE
Output Current
Voo=15V, Vo=OV
Voo = 15V, Vo = 15V
±0.1
-10- 5
10-5
±0.1
±3.0
J.tA
4.95
9.95
14.95
4.95
9.95
14.95
·1.5
3.0
4.0
5.0
10.0
15.0
2.25
4.50
6.75
4.95
9.95
14.95
V
V
V
1.5
3.0
4.0
-0.2
-0.5
-1.5
1.5
3.0
4.0
V
V
V
fJ.A
CD4512BC (Note 2)
Conditions
100 Quiescent
Device Current
Voo = 5V, VIN = Voo or Vss
Voo =10V, VIN=VOOorVss
V oo =15V, VIN=VOOorVss
VOL Low Level
Output Voltage
V oo =5.0V
Voo = 10V
Voo=15V
VOH High Level
Output Voltage
Voo=5.0V
Voo=10V } i10HI <1 p.A
Voo=15V
VIL Low Level
Input Voltage
Voo=5.0V, Vo=0.5V
Voo=10V, Vo= 1.0Vor 9.0V
VDo=15V, Vo=1,5Vor 13.5V
VIH High Level
Input Voltage
Voo=5.0V, Vo=4.5V
Voo=10V, Vo=9.0V
Voo=15V, Vo=1.5Vor 13.5V
-40"C
Min
IloLi <1 p.A
Max
25°C
Min
20
40
80
0.005
0.010
0.015
20
40
80
150
'300
600
J.tA
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
4.95
9.95'
14.95
5.0
10.0
15.0
2.25
4.50
6.75
3.5
7.0
11.0
2.75
5.50
8.25
Min
Max
Units
Max
1.5
3.0
4.0
5·249
85°C
Typ
4.95
9.95
14.95
3.5
7.0
11.0
".
....
en
ttl
25°C
Voo =5V, VIN=VOOorVss
Voo = 10V, VIN = Voo or Vss
Voo =15V, VIN=VOOorVss
Sym Parameter
C
o
100 Quiescent
Device Current
DC Electrical Characteristics
ttl
s:
N
-55°C
Min
N
(;
-55°C to +125°C
-40°C to +85°C
CD4512BM (Note 2)
Conditions
~
....
en
4.95
9.95
14.95
1.5
3.0
4.0
fJ.A
V
V
V
1.5
3.0
4.0
3.5
7:0
11.0
fJ.A
V
V
V
V
V
V
oa::I
N
.....
U')
~
DC Electrical Characteristics
(cont'd) CD45128C (Note 2)
-4QOC
Sym
Parameter
Conditions
Min·
Min
Typ
0.52
1.3
3.6
0.44
1.1
3.4
0.78
2.0
7.8
-0.2
-0.5
-1.4
-0.16
-0.4
-1.2
o
:E
a::I
N
.....
~
C
o
250C
Max
850C
Max
Min
Max
Units
10l Low Level
Output Current
(Note 3)
Voo = 5.0V, Vo=O.4V
Voo =10V, Vo=0.5V
Voo =15V, Vo=1.5V
IOH High Level
Output Current
(Note 3)
Voo = 5.0 V, Vo=2.5V
Voo =10V, Vo=9.5V
Voo = 15V, Vo = 113.5V
liN Input Current
Voo=15V, VIN=OV
Voo=15V, VIN=15V
-0.3
0.3
:-10-5
10-5
-0.3
0.3
-1.0
1.0
"A
f.!A
loz TRI·STATE
Output Current
Voo=15V, Vo=OVor 15V
±1.0
±10-5
±1.0
±7.5
f.!A
AC Electrical Characteristics
Symbol
0.36
0.9
2.4
mA
mA
mA
-0.12
-0.3
-1.0
mA
mA
mA
TA=25 D C, t,=tl=20 ns, Cl=50 pF
Parameter
Conditions
tpHl
Propagation Delay
High·to·Low Level
Voo=5.0V
Voo=10V
Voo=15V
tplH
Propagation Delay
Low·to·High Level
C04512BC
C04512BM
Min
Typ
Max
225
75
57
Vo o =5.0V
Voo=10V
Voo=15V
tTHl, tTlH Transition Time
Units
Typ
Max
500
175
130
225
75
57
-750
200
150
ns
ns
ns
225
75
57
500
175
130
225
75
57
750
200
150
ns
ns
ns
Voo=5.0V
Voo=10V
Voo=15V
70
35
25
175
75
55
70
35
25
175
75
55
ns
ns
ns
tpHZ, tpLZ Propagation Delay into
TRI·STATE from Logic Level
Voo=5.0V
Voo=10V
Voo=15V
50
25
19
125
75
60
50
25
19
125
75
60
ns
ns
ns
tpZH, tPZl Propagation Delay to Logic
Level from TRI·STATE
Vo o =5.0V
Voo=10V
Voo=15V
50
25
19
125
75
60
50
25
19
125
75
60
ns
ns
ns
.
Min
"
CIN
Input Capacitance
(Note 4)
7.5
15
7.5
15
pF
COUT
TRI·STATE Output
Capacitance
(Note 4)
7.5
15
7.5
15
pF
Cpo
Power Dissipation Capacity
(Note 5)
150
150
pF
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not
meant to imply that the devices should be operated at these limits. The tables of "Recommended Operating Conditions" and
"Electrical Characteristics" provide conditions for actual device operation.
Note 2: Vss = OV unless otherwise specified.
Note 3: IOH and IOl are tested one output at a time.
Note 4: Capacitance guaranteed by periodic testing.
Note 5: CPO determines the no load AC power of any CMOS device. For comt;llete explanation, see 54C/74C Family Characteristics
application note AN-gO.
5-250
o
~....
Logic Diagram
N
C.
m
o-'l_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.....,
3!:
n
""'----"':'::0
A
XD
~
....
N
CI'I
DISABLE
.....----...:.::0 INHIBIT
m
o
XI
X2
Xl
X4
X6
Vss
X6
Xl
INPUT
+
.
-INPUT~DUTPUT
TRA~SMISSIDN
26
GATE
TUFI5993-2
Typical Application
Serial Data Routing Interface
DATA BUS
---I~~~RIAL
.....
INPUTI
OBI
DB6
DBS
BSERIAL
INPUTS
SC/MP II
CD4S12
TL/FI5993-3
5·251
1 .
OUTPUT
III
AC Test Circuit and Switching Time Waveforms
VOO
INPUT
OUTPUT
(TESTS 1 ANO 2)
OUTPUT
(TEST 3)
1----0 Vss
-=-
TlIFJS993-5
TUF/5993·4
INPUT CONNECTIONS FOR t r , tf, tpLH, tpHL
A
XO
1
PG
GND
VDD
2
GND
PG
3
GND
GND
VDD
PG
TEST
INHIBIT
TRI-STATE AC Test Circuit and Switching Time Waveforms
,
TEST
S1
S2
S3
S4
tPHZ
Open
Closed
Open
tPLZ
Closed
Open
Closed
Open
Closed
tpZL
Closed
Open
Open
Closed
tPZH
Open
Closed
Closed
Open
5-252
~--------------------------------------------------------------'O
~.....
~National
~ Semiconductor
0l:Io
IX!
s::
o
CD4514BM/CD4514BC, CD4515BM/CD4515BC
~....
4-Bit Latched/4-to-16 Line Decoders
0l:Io
IX!
s>
General Description
Features
The CD4514B and CD4515B are 4-to-16 line decoders with
latched inputs implemented with complementary MOS
(CMOS) circuits constructed with N- and P-channel enhancement mode transistors. These circuits are primarily
used in decoding applications where low power dissipation and/or high noise immunity is required.
• Wide supply voltage range
The CD4514B (output active high option) presents a logical "1" at the selected output, whereas the CD4515B
presents a logical "0" at the selected output. The input
latches are R-S type flip-flops, which hold the last input
data presented prior to the strobe transition from "1" to
"0". This input data is decoded and the corresponding
output is activated. An output inhibit line is also available.
II! Low quiescent power dissipation
• High noise immunity
• Low power TTL
compatibility
IN A
0.45 VDD (typ.)
~
.....
fan out of 2
driving 74L
s::
0.025I'W/package
@ 5.0Voc
IX!
• Plug-in replacement for MC14514, MC14515
A Bcii 11
)O-~»-[>O'::"'::":""::...o
so
ABCD 9 S1
ABeD 8SJ
)o--cxr~~A~.~C~D~7M
A if c I'i 6 S!i
___---l
)O-~>O--C~A~.~C~D~5 S6
ABC jj 457
INC
21
o-V>O-T~)
___---l
)O--C>O--Cx>A~.~~~O~1B sa
ABC 0 11
)O--C>o-~~~~OS8
r1-'=F~~~~~~>o--Dxr-~A!.!C!O~'O
IN 0
"
O--D>O-T~)
}---.....
___---l
ii
ABC 0 16
iNHIBIT023--[>c....._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
510
511
58
59
514
......I,...j~==*=*=I.....;1O---j;xr;.;»""A..;•..;C..;0~,5 :::
TLIF/5994·1
Dual-In-Lin" Package
Von INHIBIT IN 0 IN C
ABC 0 19 S10
l~r;)-__--l-++-H...t:?={>-I:>O"""-[>O";;"":'' :' ' :'-oS11
STROBE
515
812
513
Order Number CD4514BMJ,
CD4514BCJ, CD4515BMJ
or CD4515BCJ
See NS Package J24A
Order Number CD4514BMN,
CD4514BCN, CD4515BMN
or CD4515BCN
See NS Package N24A
10
STROBE IN A IN B
57
56
55
S4
TOP VIEW
$3
51
52
11
SO
~.....
(')
-f
.O-'"D>O-T~)
o
• Input impedance = 1012Q typically
r-I-+-'F=!=:r")O-l'>o..-f>o,...:i\:..;.::.;"t"::...-::..o0'0 S2
IN
IX!
C1I
o-i>o--~}.....__
3
C1I
• Single supply operation
Logic and Connection Diagrams
,
(')
3.0Vt015V
12
Vss
TL/F/5994-2
5-253
Absolute Maximum Ratings
Recommended Operating Conditions
(Notes 1 and 2)
(Note 2)
voo OC Supply Voltage
--{J.5V to+18V
VIN Input Voltage
-0.5V to VOO + 0.5V
TS Storage Temperatura Range
~5°C to +150°C
Po Package Oissipation
500mW
TL Lead Temperature (Soldering, 10 seconds)
260°C
Voo OC Supply Voltage
VIN Input Voltage
T A Operating Temperature Range
C04514BM, C04515BM
C04514BC, C04515BC
DC Electrical Characteristics
SYM
100
VOL
VOH
VIL
VIH
10L
IOH
PARAMETER
Quiescent Device Current
Low Level Output Voltage
High Level Output Voltage
Low Level Input Voltage
High Level Input Voltage
CD4514BM, CD4515BM (Note 2)
-55°C
CONDITIONS
MIN
MAX
VOL
TYP
125°C
MAX
MIN
MAX
UNITS
0.005
5.0
150
J1.A
10.0
0.010
10.0
300
J1.A
20.0
0.015
20.0
600
J1.A
VOO = 5V, VIL = OV
0.05
a
0.05
0.05
V
VOO= 10V
VOO= 15V
0.05
a
0.05
0.05
V
0.05
a
0.05
0.05
V
VIH = V 0'0, 1101 < I/lA
VIH = Voo, 1101 < 1 J1.A
VOO = 5V, VIL = OV
4.95
4.95
5.0
4.95
V
VOO = 10V
9.95
9.95
10.0
9.95
V
VOO= 15V
14.95
14.95
15.0
14.95
V
Vo = 0.5V or 4.5V
VOO = 5V,IIoi < l/lA
1.5
2.25
1.5
1.S
VOO = 10V, Va = 1.0V or 9.0V
3.0
4.50
3.0
3.0
V
VOO = ISV, Vo = 1.SV or 13.5V
4.0
6.75
4.0
4.0
V
V
Va = O.SV or 4.5V
V
3.5
3.5
2.75
3.5
7.0
7.0
5.50
7.0
V
VOO = lSV, Va = I.SV or 13.5V
11.0
11.0
8.25
11.0
V
Low Level Output Current
VOO = 5V, Va = 0.4V
0.64
0.51
0.88
0.36
mA
(Note 3)
VOO = 10V, Va = 0.5V
1.6
1.3
2.25
0.90
mA
VOO = 15V, Va = 1.SV
4.2
3.4
8.80
2.40
mA
VOO = 5V, Va = 4.6V
VOO = 10V, Va = 9.5V
--{J.64
-0.51
--{J.88
mA
-1.6
-1.3
-2.25
-0.36
--{J.90
VOO = 15V, Va = 13.5V
-4.2
-3.4
-B.80
-2.40
mA
High Level Output Current
Input Current
VOO = 15V, VIN = OV
DC Electrical·Characteristics
100
25°C
MIN
S.O
VOO = SV, VIN = VOO or VSS
Voo = 10V, VIN = Voo or VSS
VOO = lSV, VIN = VOO or VSS
PARAMETER
-10-5
--{J.l
-1.0
/lA
O.l
10-5
0.1
1.0
/lA
Quiescent Device Current
Low Level Output Voltage
CD4514BC, CD4515BC (Note 2)
.
-40°C
CONDITIONS
MIN
Voo = 5V, VIN = Voo or VSS
Voo = 10V, VIN = Voo or Vss
Voo = lSV, VIN = Voo or Vss
mA
--{J.l
VOO = lSV, VIN = lSV
SYM
-55"c to +125°C
-40° C to +85° C
VOO = SV, 1101 < l/lA
VOO = 10V, Va = 1.0V or 9.0V
(Note 3)
liN
3V to 15V
OtoVOO
MAX
85°C
25°C
MIN
MIN
MAX
UNITS
TYP.
MAX
20
40
. 0.005
0.010
20
150
/lA
40
300
/lA
80
0.Q15
80
600
/lA
VIL = OV, VIH = VOO,
lIol 0.01 fJ.F use
PWout = 0.2 RxCx In [VOO - VSSl
Cx = 10,000pF, Rx = 10kn
VOO = 5.0V
15 " 29
45
fJ.S
VOO = 10.0V I
10
37
90
fJ.S
VOO = 15.0V
15
42
95
fJ.S
6
25
%
VOO= 10.0V
8
35
%
VOO= 15.0V
8
35
%
VOO = 5.0V
325
600
ns
VOO = 10.0V
90
225
ns
VOO= 15.0V
60
170
VOO = 5.0V
7.0
fJ.S
VOO= 10.0V
6.7
fJ.S
VOO = 15.0V
6.7
fJ.S
VOO = 5.0V
0
Pulse Width Match Between Circuits in the
, Same Package
Cx = 10,000pF, Rx = 10kn
Reset Propagation Oelay, tPLH, tPH L
Cx = 15 pF, Rx = 5.0 kn
I
Cx = 1000pF, Rx = 10kn
Minimum Retrigger Time
Cx = 15pF, Rx = 5.0kn
Cx = 1000 pF, Rx = 10 kn
,
VOO = 5.0V
,
VOO = 10.0V
0
VOO = 15.0V
0'
VOO = 5.0V
0
VOO= 10.0V
0
VOO = 15.0V
0
,
5-278
ns
ns
o
Logic Diagram
c
(Y.. of Device Shown)
E
'DD
aI
t\.
.. 1
s:::
~
(;
ex
--if-l
I
'~'
11
i
Q
•
CD
CD
3------~~----_[>O------~
o
4.
TLIFJ5998-3
fT
D, , - . _ 2 D "
90%
VIN
Veo
10%
DV
DUTY CYCLE =' 50%
TUFI599B-4
Figure 1. Power Dissipation Test Circuit and Waveforms
VDD
Input Connections
CD
A
B
tPLH. tPH L. t r• tf.
PWout.PWin
VDD
PGl
VDD
tpLH. tpHL. t r• tf.
PWout. PWin
VDD
VSS'
PG2
tPLH(R). tPHL(R). PWin
PG3
PGl
PG2
Characteristics
·Cx-15pF
·CL;15pf
fIJc=i.Okn
TLlf159!J8.5
"INCLUDES CAPACITANCE Of PROBES.
WIRING, AND FIXTURE PARASITIC.
NOTE: AC TEST WAVEFORMS FOR PG1,
PG2, AND PGJ ON NEXT PAGE.
PGI.-.....fL
PG2'~
PG3.~
TUFI5998-6
Figure 2. AC Test Circuit
5-279
t,
PWIN
Co
----r----------r------------~7i1
trr
n
TLIFI5996-7
Figure 3. AC Test Waveforms
~
.1.15
f- FOR All VALUES OF Voo 3V TO 18V-1;7-
~1'10"
~ 1.05
~
1.0 .n ............ .
::::i 0.95
!
0.90
il
0.85
-60 -40 -20
20
40
60
80 100 120 140
TA. AMBIENT TEMPERATURE ('Cl
TL/F/5998-8
Figure 4. Normalized Pulse Width vs Tempa"rature
5000.0
1000.0
j
..=...
100.0
Ii
~
10.0
f
1.0
100
1.000
10.000
100.000
Cx, EXTERNAL CAPACITANCE (oFI
1,000,000
TUF/5998-9
Figur.5. Pulse Width vs
5·280 -
ex
~National
~ Semiconductor
CD4529BM/CD4529BC Dual 4-Channel or Single 8Channel Analog Data Selector
General Description
Features
The CD4529B is a dual 4-channel or a single 8-channel
analog data selector, implemented with complementary
MOS (CMOS) circuits constructed with N- and P-channel
enhancement mode transistors. Dual 4-channel or 8-channel mode operation is selected by proper input coding, with
outputs Z and W tied together for the single 8-bit mode. The
device is suitable for digital as well as analog applications,
including various 1-of-4 and 1-of-8 data selector functions.
Si'nce the device is analog and bidirectional, it can also be
used for dual binary to 1-of-4 or single 1-of-8 decoder applications.
3.0V to 15V
• Wide supply voltage range
0.45 Voo (typ.)
• High noise immunity
0.005 j.tW/package
• low quiescent
(typ.) @ 5.0 Voc
power dissipation
• 10 MHz frequency operation (typ.)
• Data paths are bidirectional
• Unear ON resistance [120 n (typ.) @15V)
• TRI-STATE«> outputs (high impedance disable strobe)
• Plug-in replacement for MC14529B
Connection Diagram
Logic Diagram
Dual-In-Line Package
waD
STy
YI
Y\
'2
Yl
W
.0
IT.
X2
XI
XI
v.
Xl
I
I
XI
1.' VIEW
Order Number CD4529BCJ, N or CD4529BMJ, N
See NS Package J16A or N16E
Truth Table
STx STy B A
Z
W
1
XO
X1
X2
X3
YO
Y1
Y2
Y3
,1
0
0
0
0
0
0
0
0
0
0
0
0
0
x=
0
'0 0
0 1
0
XO
X1
X2
X3
0
0
YO
Y1
Y2
Y3
0
1
0
X X
xz
•
.. •
Dual
4-Channel
Mode
2 Outputs
}
Single
8-Channel Mode
1 Output
(Z and W
tied together)
VI
"
v, II
.. "
II
VI
High
Impedance
(TRI-STATE)
TL/F/5999-1
Don't care
5-281
Absolute Maximum Ratings
Recommended Operating
Conditions (Note 2)
(Notes 1_ and 2)
VOO DC Supply Voltage.
VIN Input Voltage
-0.5Vto +18V
,
-0.5V·to Voo +,0.5V
TS Storage Temperature Range
Po Package Dissipation
TL Lead Temp. (Soldering, 10 seconds)
Voo DC Supply Voltage
3Vto15V
VIN Input Voltage
TA Operating Temperature Range
CD4529BM
CD4529BC
-65°C to + 150"C
500mW
260"C
OtoVoo
-55"Cto + 125°C
-40°C to +85°C
DC Electrical Characteristics CD4529BM (Note 2)
Symbol
Parameter
-55°C
Conditions
Min
100
VOL
VOH
Quiescent Device
Current Voo = 5V
,
Voo = 10V
Voo = 15V
Low Level Output Voltage VIL = OV, VIH = Voo, 1101
Voo = 5V
Voo = 10V
Voo = 15V
< 1 p.A
High Level Output Voltage VIL = OV, VIH = Voo, 1101
Voo = 5V
Voo = 10V
Voo = 15V
< 1 p.A
VIL
Low Level Input Voltage
(Note 3)
Voo = 5V
Voo = 10V
Voo = 15V
VIH
High Level Input Voltage
(Note 3)
Voo = 5V
Voo = 10V
Voo = 15V
liN
Input Current
Voo = 15V
VIN = OV
VIN = 15V
RON
10FF
ON Resistance
Input to Output Le!lkage
Current
25°C
1.0
1.0
2.0
0.001
0.002
0.003
1.0
1.0
2.0
60
60
120
p.A
p.A
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
O.OS
V
V
V
Min
4.95
9.95
14.95
1.5
3.0
4.0
-0.1
0.1
5.0
10.0
15.0
2.25
4.50
.6.75
3.5
7.0
11.0
3,.5
7.0
11.0
Min
Max
4.95
.9.95
14.95
1.5
3.0
4.0
2.75
5.50
8.25
1.5
3.0
4.0
3.5
7.0
11.0
-10- 5 -0.1
10-5
0.1
5-282
p.A
V
V
V
V
V
V
V
V
V
-1.0
1.0
p.A
p.A
400
400
400
165
100
155
480
480
480
640
640
640
n
n
n
240
240
240
135
75
100
270
270
270
400
400
400
n
n
n
400
400
400
165
100
160
480
480
480
640
640
640
n
n
n
250
250
250
135
75
110
270
270
270
400
400
400
n
n
n
-
Vss = -5V, Voo = 5V, VIN = 5V,
VOUT = -:5V
Vss = -SV, Voo = SV, VIN = -5V,
VOUT = 5V
Vss = -7.SV, Voo = 7.5V, VIN = 7.SV,
VOUT = -7.5V
. Vss = -7.5V, Voo = 7.5V,
VIN = -7.5V, VOUT = 7.5V
Unit.
.Max
4.95
9.95
14.95
Voo = 5V, Vss = -5V
VIN = 5V
VIN = -5V
VIN = ±0.25V
Voo ='7.5V, Vss = -7.5V
VIN = 7.5V
VIN = -7.5V
VIN = ±0.25V
Voo = 10V, Vss = OV
VIN = 10V
VIN = 0.25V
VIN = 5.6V
Voo = 15V, Vss = OV
VIN = 15V
VIN = 0.25V
VIN = 9.3V
125"C
Typ
Max
±125
±0.001 ±125
±12S0 nA
±125
±0.001 ±125
±1250 nA
±2S0
±0.0015 ±250
±2500 nA
±250
±0.O015 ±250
±2500 'nA
o
DC Electrical Characteristics CD4529BC (Note 2) (Continued)
Symbol
Parameter
-40"C
Conditions
Min
.100
VOL
VOH
Quiescent Device Current Voo = 5V
Voo = 10V
Voo = 15V
<
High Level Output Voltage Vll = OV, VIH = Voo, 1101
Voo = 5V
Voo = 10V
Voo = 15V
< 1 p.A
Low Level Input Voltage
(Note 3)
Voo = 5V
Voo = 10V
Voo = 15V
VIH
High Level Input Voltage
(Note 3)
Voo = 5V .
Input Current
Voo = 15V
VIN = OV
VIN = 15V
liN
RON
10FF
ON Resistance
Input-Output Leakage
Current
85"C
Units
Typ
Max
0.001
0.002
0.003
5.0
5.0
110.0
70
70
140
p.A
p.A
p.A
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
Min
Max
1 p.A
0.05
0.05
0.05
4.95
9.95
14.95
4.95
9.95
14.95
1.5
3.0
4.0
3.5
7.0
11.0
Voo = 10V
Voo = 15V
Voo = 5V, Vss = -5V
VIN = 5V
VIN = -5V
VIN = ±0.25V
Voo = 7.5V, Vss = -7.5V
VIN = 7.5V
VIN = .7.5V
VIN = ±0.25V
Voo = 10V, Vss = OV
VIN = 10V
VIN =,O.25V
VIN = 5.6V
Voo = 15V, Vss = OV
VIN = 15V
VIN = 0.25V
VIN = 9.3V
Vss =
VIN =
VIN =
Vss =
VIN =
VIN =
Min
5.0
5.0
10.0
Low Level Output Voltage Vll = OV, VIH = Voo, 1101
Voo = 5V
Voo = 10V
Voo = 15V
VIL
Max
25"C
-5V, Voo = 5V
5V, VOUT = -5V
-5V, VOUT = 5V
-7.5V, Voo = 7.5V
7.5V, VOUT = -7.5V
-7.5V, VOUT=7.5V
5.00
10.00
15.00
2.25
4.50
6.75
3.5
7.0
11.0
4.95
9.95
14.95
1.5
3.0
4.0
2.75
5.50
8.25
V
V
V
1.5
3.0
4.0
3.5
7.0
11.0
V
V
V
V
V
V
-0.3
0.3
-10- 5
10-5
-0.3
0.3
-1.0
1.0
p.A
p.A
410
410
410
165
100
155
480
480
480
560
560
560
(}
135
' 75
350
350
350
(}
100
270
270
270
410
410
410
165
100
160
480
480
480
560
560
560
(}
250
250
250
135
75 .
350
350
350
(}
110
270
270
270
±125
±125
±0.001
±0.001
±125
±125
. ±500
±500
nA
nA
±250
±250
±0.0015 ±250
±0.0015 ±250
±1000
±1000
nA
nA
250
250
250
,
(}
(}
(}
(}
(}
(}
(}
(}
Note 1: "Absolute Maximum Ratings"' are those values beyond which the safety of the device cannot be guaranteed. Except for "'Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The tables of "'Recommended Operating Conditions" and "Electricaf Characteristics" provide conditions for actual device operation.
Note 2: Vss = OV unless otherwise specified.
Note 3: Switch OFF is defined as 1101 ,; 10 "A, switch ON as defined by RON specification.
5·283
~
-
m
3:1
0/
C
~""m
o
AC Characteristics CD4529BM/CD4539BC
TA = 25°C, RL = 1 kfi, tr = tf = 20 ns, unle$s otherwise specified.
Symbol
tPLH, tpHL
tpLH, tpHL
'MAX
Parameter
VIN to Your Propagation Delay
Control to Output Propagation Delay
Maximum Control Input Pulse Frequency
Crosstalk, Control to Output
Noise Voltage
Sine Wave (Distortion)
ILOSS
Insertion Loss,
Your
ILOSS = 20 L09l0VIN
BW
Bandwidth, -3dB'
Feedthrough and Crosstalk,
Your
20 Logl0--= -50db
VIN
Typ
Max
Units
OV,CL = 50pF
5V
10V
15V
Conditions
20
10
8
40
20
15
ns
ns
ns
VIN = Voo or Vss, CL = 50 pF
VIN s: 10V
Voo = 5V
Voo = 10V
Voo = 15V
200
80
50
400
160
120
ns
ns
ns
Vss =
Voo =
Voo =
Voo =
Min
Vss = OV,CL = 50pF
Voo = 5V
Voo = 10V
Voo = 15V
Rour = 10 kfi, CL = 50 pF, Vss = 0
Voo = 5V
Voo = 10V
Vpo = 15V
f = 100Hz, Vss = OV
Voo = 5V
Voo = 10V
Voo = 15V
f = 100 kHz, Vss = OV
Voo = 5V
Voo = 10V
Voo = 15V
VIN = 1.77Vrmspentered
at OV, RL = 10 kfi, f = 1 kHz,
Vss = -5V, Voo = 5V
VIN = 177Vrms Centered
at OV, Vss = -5V, Voo = 5V
RL=1kfi
RL=10kfi
RL = 100kfi
RL = 1 Mfi
VIN = 177Vrms Centered
at 0 Vdc, Vss ;= -5V, Voo = 5V
RL = 1 kfi
RL= 10kfi
RL = 100kfi
RL = 1 Mfi
Vss = -5V, Voo = 5V
RL = 1 kfi
RL = 10kfi
RL=100kfi
RL = 1 Mfi
5·284
5
10
12
MHz
MHz
MHz
5.0
5.0
5.0
mV
mV
mV
24
25
30
nVNcycle
nVNcycle
nVNcycle
12
12
15
0.36
nVNcycle
nVNcycle
nVNcycle
%
2.0
0.8
0.25
0.Q1
I
dB
dB
dB
dB
35
28
27
26
MHz
MHz
MHz
MHz
850
100
12
1.5
kHz
kHz
kHz
Khz
Test Circuits and Switching Time Waveforms
Output Voltage
f1
RON Characteristics ,
Noise Voltage
UT
.
Va
'" -"
VII
Va
VDD
ClUAI-TECH
MODEL
Z2U
OR EOUIV
-
Frequency Response
Crosstalk
VIS
AURI
VOD
C'\-Z.SVdC
VIN -
X. Y INPUT
IVde
~-Z_5Vde
Propagation Delay
Turn-ON Delay Time
STX. STy.
ADR I
VDD
VIS
STX. Sfy
ADA!
VIS
IPlH
VOUT
Your
VIN· VDD
Vx - IVde
TL/F/5999-2
5-285
Typical Performance Characteristics
Typical RON vs VIN
zsa
voo -sv
ISO
~
1ZS
~
:; zoo
u
z
c
t;
~
z
".,,
"
a:
Typical Noise Characteristics
3S
V~SI- ~st
22S
m
~
'"
~>
Vss - -I.IV
I.SV
100
voo -
IS
SO
ITIII
IIIII
ZS
a
-.
..
v~~I!I!Lll
K
30
21
IOVdC~
ZO
1\
II
lVoIe
10
II
II
~
is
IIIII
a
-6-4-Z0Z46.
10
VIN - INPUT VOLTAGE tVd,)
100
n
1010
10lI0
f - FREQUENCY (Hri
Typical Insertion Lossl
Bandwidth Characteristics
RL
~
, Mil AND 100 k!l
~
t!
::
~
~
-2
-4
-6
5
-.
~
-10
'"
lOOk
1M
10M
IDOM
liN -INPUT FREQUENCY (Hl)
TL/F/5999-3
5-286
( .
(')
~National
~ Semiconductor
i
i
to
s:
(;
CD4538BM/CD4538BC Dual Precision Monostable
to
(')
General Description
Features
The CD4538B is a dual, precision monostable multivi·
brator with independent trigger and reset controls. The
device is retriggerable and resettable, and the control
inputs are internally latched. Two trigger inputs are pro·
vided to allow either rising or falling edge triggerin'g. The
reset inputs are active low and prevent triggering while
active. Precise control of output pulse·width has been'
achieved using linear CMOS techniques. The pulse dura·
tion and accuracy are determined by external compo·
nents Rx and Cx. The device does not allow the timing
capacitor to discharge through the timing pin on power·
down condition. For this reason, no external protection
resistor is required in series with the timing pin. Input
protection from static discharge is provided on all pins.
• Wide supply voltage range
3.0V to 15V
• High noise immunity
0.45 Vee (typ.)
fan out of 2 driving 74L
• Low power
TTL compatibility
or 1 driving 74LS
• New Formula: PWOUT = RC
(PW in seconds, R in Ohms, C in Farads)
• ±1.0% pulse-width variation from part to part (typ.)
• Wide pulse·width range
11-'s to 00
• Separate latched reset inputs
• Symmetrical output sink and source capability
• Low standby current
5 nA (typ.)
@ 5Voc
• Pin Compatible to CD4528B
Block and Connection Diagrams
Cx
Dual·ln·Line Package
RX
r-HI-4_"""~- VOO
Cx
C045388M
C045388C
RX
...-...-lIH_"'II"""-
VOO
T1A
16
VOO
T2A
15
T18
COA
14
T28
AAINPUT
13
BAINPUT
12
COB
AaINPUT
DAOUT
11
BBINPUT
DAOUT
10
aBOUT
iiBOUT
Vss
14
12 ___.........
TOP VIEW
10
TUFI6000-2
11-___'",
Co
Order Number CD4538BMJ or CD4538BCJ
See NS Package J16A'
13-------1
Order Number CD4538BMN or CD4538BCN
See NS Package N16E
RX AND Cx ARE EXTERNAL COMPONENTS
VOo=Pln 16
Vss = Pin 8
TUFI6000-1
Truth Table
Inputs
Clear
L
X
X
H
H
A
X
.H
X
=
Outputs
B
X
X
L
L
~
t
H
Q
Q
L
L
L
H
H
.n
n
H High Level
L = Low Level
t = Transition from Low to High
~ = Transition from High to Low
n = One High Level Pulse
u=One Low Levei'Pulse
X = Irrelevant
H
u
u
5·287
Absolute Maximum Ratings
Recommended Operating Conditions
(Notes 1 and 2)
Voo QC Supply Voltage
-0.5Vto +18Voc
VIN Input Voltage
-0.5 to Voo+0.5Voc
-65·Cto +150·C
Ts Storage Temperature Range
Po Package Dissipation
/
500mW
T L Lead Temperature (soldering, 10 seconds)
260·C
(Note 2)
Voo DC Supply Voltage
VIN Input Voltage
TA Operating Temperature Range
CD4538BM,
CD4538BC
+3\0 +15Voc
. OtoVoo Voc
-55·Cto +125·C
-4O·Cto +85·C
,
DC Electrical Characteristics (Note 2) -
CD4538BM·
Parameter
Conditions
100
Quiescent
Device Current
Voo=5V } VIH=VOO
Voo=10V VIL=VSS
Voo = 15 V All outputs open
VOL
Low Level
Output Voltage
Voo=5V }
Voo=10V 1101 < 1",A
Voo = 15V VIH = Voo, VIL = Vss
VOH
High Level
Output Voltage
Voo: 5 V } 1101 < 1",A
Voo-10V
Voo = 15 V VIH = Voo, VIL = Vss
Sym
-55°C
Min
25°C
125°C
Units
Typ
Max
5
10
20
0.005
0.010
0.015
5
10
20
150
300
600
",A
",A
",A
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
.V
Min
Max
4.95
9.95
14.95
4.95
9.95
14.95
5
10
15
Min
Max
V
4.95
9.95
14.95
V
V
Low Level
Input Voltage
1101 < 1",A
Voo=5V, Vo=0.5V or 4.5V
Voo = 10V, Vo= 1.0V or 9.0V
Voo= 15V, Vo= 1.5V or 13.5V
High Level
Input Voltage
1101 < 1",A
Voo=5V, Vo = 0.5 V or 4.5 V
Voo = 10V, Vo = 1.0V or 9.0V
Voo= 15V, Vo= 1.5V or 13.5V
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.50
8.25
3.5
7.0
11.0
V
V
V
IOL
Low Level
Output Current
(Note 3)
Voo=5V, VO=0.4V}
VIH=VOO
Voo=10V, Vo=0.5V
VIL=VSS
Voo=15V, Vo=1.5V
0.64
1."6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mA
rnA
mA
10H
High Level
Output Current
(Note 3)
Voo=5V, Vo=4.6V }
VIH=VOO
Voo= 10V, Vo=9.5V
VIL=VSS.
Voo=15V, Vo=13.5V
-0.6,4
-1.6
-4.2
-0.36
-0.9
-2.4
mA
mA
mA
liN
Input Current,
pin 2 or 14
Voo=15V, VIN=OVor 15V
±0.02
±10- 5 ±0.05
±0.5
",A
liN
Input Current,
. other inputs
Voo= 15V, VIN=OVor 15V
±0.1
±10- 5 ±0.1
±1.0
",A
VIL
-
VIH
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0'
• -0.51 -0.88
-1.3 -2.25
-3.4 -8.8
1.5
3.0
4.0
(
5·288
V
V
V
DC Electrical Characteristics
Syrn
Parameter
(Note 2) -
CD4538BC
-40°C
Conditions
Min
Max
25°C
Min
85°C
Min
Units
Typ
Max
20
40
80
0.005
0.010
0.015
20
40
80
150
300
600
,..A
,..A
,..A
0.05
'0.05
0.05·
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
Max
100
Quiescent
Device Current
Voo= 5V } VIH "'Voo
Voo=10V VIL=VSS
Voo = 15 V All outputs open
VOL
Low Level
Output Voltage
Voo=5V }
Voo = 10V 1101 < 1,..A
Voo=15V VIH=VOO, VIL=VSS
VOH
High Level
Output Voltage
Voo=5V }
Voo = 10V 1101 < 1,..A
Voo=15V VIH=VOO, VIL=VSS
VIL
Low Level
Input Voltage
1101 < 1,..A
Voo=5V, Vo= 0.5V or 4.5V
Voo= 10V, Vo = 1.0V or 9.0V
Voo=15V, Vo=1.5Vor 13.5V
High Level
Input Voltage
1101 < 1,..A
Voo=5V, Vo =0.5V or 4.5V
Voo=10V, Vo=1.0Vor9.0V
Voo=15V, Vo=1.5Vor 13.5V
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.50
8.25
3.5
.1.0
11.0
V
V
V
10L
Low Level
Output Current
(Note 3)
Voo=5V, Vo=0.4V } VIH =Voo
Voo=10V, Vo=0.5V V
V
Voo=15V, Vo=1.5V
IL= ss
0.52
1.3
3.6
0.44
1.1
3.0
0.88
2.25
8.8
0.36
0.9
2.4
rnA
rnA
rnA
loli
High Level
Output Current
(Note 3)
Voo=5V, Vo=4.6V }
Voo=10V, Vo=9.5V
VIL=VSS
Voo=15V, Vo=13.5V
-0.52
-1.3
-3.6
-0.44 -0.88
-1.1 -2.25
-3.0 -8.8
-0.36
-0.9
-2.4
rnA
rnA
rnA
liN
Input Current,
pin 2 or 14
Voo= 15V, VIN =OV or 15V
±0.02
±10-5 ±0.05
±0.5
,..A
liN
·Input Current,
other inputs
Voo=15V, VIN=OV or 15V
±0.3
±10-5 ±0.3
±1.0
,..A
VIH
4.95
9.95
14.95
4.95
9.95
14.95
1.5
3.0
4.0
5
10
15
2.25
4.50
6.75
V
V
V
4.95
9.95
14.95
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed, they are not
meant to imply that the devices shouJd be operated at these limits. The tables of "Recommended Operating Conditions" and
"Electrical Characteristics" provide conditions for actual device operation.
Note 2: VSS = 0 V unless otherwise specified.
Note 3: 10H and 10L are tested one output at a time.
5·289
AC Electrical Characteristics TA=25°C. CL =50pF. and t;=t,=20ns unless otherwise specified.
Symbol
Typ
Max
Units
Voo=5V
Voo=10V
Voo=15V
100
50
40
200
100
80
ns
ns
ns
Trigger Operation A or B to 0 ora
Voo=5V
Voo=10V
Voo=15V
300
150
100
600
300
220
ns
ns
ns
Reset Oper!.tlon Co to 0 or 0
Voo=5V
Voo=10V
Voo=15V
250
125
95
500
250
190
ns
ns
ns
A. B. or Co
Voo=5V
Voo=10V
Voo=15V
35
30
25
70
60
50
ns
ns
ns
Minimum Retrlgger Time
Voo=5V
Voo=10V
Voo=15V
0
0
0
0
ns
ns
ns
Pin 2 or 14
other Inputs
10
5
7.5
pF
pF
Parameter
Conditions
tTLH. tTHL
Output Transition Time
tpLH. tpHL
Propagation Dell10Y Time
tWL. tWH
tRR
Minimum Input Pulse Width
Input Capacitance
CIN
PWOUT
Min
Output Pulse Width (0 or 0)
(Note: For typical distribution.
see Figure 9)
Pulse Width Match between
circuits in the same package
Cx=0.1,..F. Rx= 100kQ
I
Rx=100kQ
Cx=0.002,..F
Voo=5V
Voo=10V
Voo=15V
208
211
216
226
230
235
244
248
254
,..s
,..s
,..s
Rx=100kQ
Cx=0.1,..F
Voo=5V
Voo=10V
Voo=15V
8.83
9.02
9.20
9.60
9.80
10.00
10.37
10.59
10.80
ms
ms
ms
Rx=1ookQ
Cx=10.0,..F
Voo=5V
Voo=10V
Voo=15V
0.87
0.89'
0.91
0.95
0.97
0.99
1.03
1.05
1.07
s
s
s
Rx=100kQ
Cx=0.1,..F
Voo=5V
Voo=10V
Voo=15V
Cx
I
External Timing Resistance
External Timing Capacitance
%
%
5.0
.
kQ
0
No Limit
pF
Operating Conditions
Rx
%
:1:1
±1
±1
'The maximum usable resistance Rx Is a function of the le.akage of the Capacitor Cx• leakage of the CD4538B. and leakage due
to board layout. surface reSistance. etc.
LogiC Diagram
\liD
\liD
I
I
I
........
Q1
L
'x~
I
I
t-CX:+:
I
1&
---t;'
12
21'4,
~tt5)
L--l
"::"
" 4(121
"Ef1
ENABLE
+
-
"EF2
~F:
=L)-
ENABLE
"::" Vss
~'1101
0"",,'
LATCH
t
J
_I s
.R
D~7('1
'---
~
CONTROL
5(111
CD 3(13)
'
s
~
•
.
r-
C2
RESET LATCH
D"I_
TUFI6000-3
Figure 1
5·290
,
I
Theory of Operation
CD
A__~rl~
@
@,
____________~~~__~rl~_'____
B
®
u
CD
LJ
o__---JI
I-T-I
---..,
IIA t---~:-""1
dAl------i
Qat----i
IlA 1---<>-----;
Oa
VSS
TUFf6000·11
TUF/SOOO-12
INPUT CONNECTIONS
CHARACTERISTICS
CO
A
a
IPlH. IPHL. trLH. trHL.
PWOUT. tWH. twL
Voo PGl Voo
tpLH. tPHL. trLH. trHL.
PWOUT. twH. tWL
.tPLH(R). tPHL(R).
tWH. tWL
Voo VSS PGZ
"INCLUDES CAPACITANCE OF PROBES.
WIRING. AND FIXTURE PARASITIC
NOTE: SWITCHING TEST WAVEFORMS
FOR PG1. PG2. PG3
ARE SHOWN IN FIGURE 6.
.,
PG3 PGl PGZ
20n,-
PG1=~
II
_20n,
I~I-VIN---:110 %
PG2=~
¥oo
~ OV
OUTY CYCLE=50% •
TlIF/6000·14
TUF/6000·13
Figure 8. Power Dissipation Test Circuit and Waveforms
Figure 7. Switching Test Circuit
5·293
u.------------------------------------------------------------,
m
I
u
im
co
t-
NORMALIZING PULSE
~~:l~kg
CX-O.lI1F
~
~
f-- f-~OD~5.6v
1\
1.00
1.04
_1 LI
1.08
-10
OUTPUT PULSE WIDTH
(NORMALIZED TO MEAN VALUE FOR EACH VoD)
1 I
~
-
~
VOD=15V
..........
r
70
110
150
TUF/6000-16
Figure 12. Typical Pulse Width Error
Versus Temperature
J
2~~~~~:- ;:;;;f-""
....
3D
TA. AMBIENT TEMPERATURE ('C)
TUF/6OO().1S
Figure 9. Typical Normalized Distribution of Units for
Output Pulse Width
I
l....-
I I 1
~
0.96
t-
f;;!:- VoO=15V
\
IL
0.92
RX=100kll
Cx=.002~F
r- -~DO~10~
1/
U
L I I
WIDTHS
'iDo"SV T.9.8 ..s
""..
oOlOV T.10m,
r .... m.
'iDO-15V
......r
,
2~~~~~:f -'::;po
, , ....
VoO=10V
1
-p Ko=5.0V
5 6 7 89m n n rn "
VDD. SUPPLY VOLTAGE (VOLTS)
~
TLIFI6OO()..17
Figure 10. Typical Pulse Width Variation as a
Function of Supply Voltage VDD
70
110
150
TA. AMBIENT TEMPERATURE ('C)
"1m.
OUTPUT DUTY CYCLE (%)
TUF/6QOO.18
Figure 13. Typical Pulse Width Error
Versus Temperature
TUFfSIJOO..19
Figure 11. Typical Total Supply Current Versus
Output Duty Cycle, Rx=100kQ, CL=50pF,
Cx = 100 pF, One Monostable Switching Only
5-294
10m.
100m.
TIMING RC PRODUCT
1 SEC.
TUFI6OQO.20
Figure 14. Typical Pulse Width Versus Timing
RC Product
.---------------------------------------------------------------'0
c
~National
~
.....
~ Semiconductor
I:D
3:
CD4541BM/CD4541BC Programmable Timer
?i
c
~
General Description
-'="
.....
The CD4541B Programmable Timer is designed with a
16'stage binary counter, an integrated oscillator for use
with an external capacitor and two resistors, output
control logic, and a special power·on reset circuit. The
special features of the power-on reset circuit are first,
no additional static power consumption and second,
the part functions across the full voltage range (3·15V)
whether power-on reset is enabled or disabled.
• Oscillator frequency range
Timing and the counter are initialized by turning on
power, if the power-on reset is enabled. When the power
is already on, an external reset pulse will also initialize
the timing and counter. After either reset is accom·
plished, the oscillator frequency is determined by the
external RC network. The 16'stage counter divides the
oscillator frequency by any of 4 digitally controlled
division ratios.
• Operates as 2" frequency divider or single transition
timer
i::
DC to 100kHz
I:D
• Oscillator may be bypassed if external clock is avail·
able (apply external clock to pin 3)
• Automatic reset initializes all counters when power
turns on
• External master reset totally independent of auto·
matic reset operation
• Q/Q select provides output logic level flexibility
• Reset (auto or master) disables oscillator during
resetting to provide no active power dissipation
• Clock conditioning circuit permits operation with
very slow clock rise and fall times
• Wide supply voltage range - 3.0V to 15V
Features
• High noise immunity -.0.45VDD(tyP.)
• 5V·10V·15V parametric ratings
Available division ratios 28 , 210, 213, or 216
•
• Increments on positive edge clock transitions
• Built·in low power RC oscillator (±2% accuracy over
temperature range and ±10% supply and ±3% over
processing @ < 10 kHz)
• Symmetrical output characteristics
• Maximum input leakage 11'Aat 15Vover full tempera,
ture range
• High output drive (pin 8) min. one TTL load
Logic Diagram
A 12------------------~------~~--------------,
B 13------------------------~t_--------------~
[)4>--so
RiC
1
etc 2
RS
3
AUTO RESET
5
------------1
10
6
MASTER
RESET
VOD=PIN 14
VSS=PIN 7
Connection Diagram
SELECT
TLIF/6001·1
Dual·ln·Line Package
RS
14
13
12
A
N.C.
11
N.C.
AR
10
MODE
MR
9
Ric
Clc
N.C. - NOT CONNECTED
Q~Q
MODE
VOO
oiii
SELECT
a
Vss
TOP VIEW
TUF/6001·2
5·295
'Order Number CD4541BMJ
or CD4541BCJ
See NS Package J14A
Order Number CD4541BMN
or CD4541BCN
See NS Package N14A
o
Absolute Maximum Ratings
Recommended Operating Conditions
(Notes 1 &2)
(Note 2)
Supply Voltage, Voo
-0.5 to +18V
Input Voltage, VIN
-0.5 to Voo + 0.5V
-65·Cto+150·C
Storage Temperature Range, Ts
Package Dissipation, Po
500mW
260·C
Lead Temperature, TL (soldering, 10 seconds)
DC Electrical Characteristics
(Note 2) -
Supply Voltage, Voo
Input Voltage, VIN
Operating Temperature Range
CD4541BM
CD4541BC
100
Parameter
Quiescent Device Current
VOL Low Level Output Voltage
VOH High Level Output Voltage
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
10L
Conditions
Min
Voo =5V, VIN=VOOorVss
Voo = 10V, VIN = Voo or Vss
Voo =15V, VIN=VOOorVss
Voo=5V
Voo= 10V
Voo = 15V
1101 < 1,.,A
Voo=5V
Voo=10V
Voo = 15V
1101 < 1,.,A
-55·C to +125·C
-40·C to +85·C
CD4541BM
-55°C
Sym
3to 15V
OtoVoo
25°C
Max
125°C
Max
5
10
20
0.005
0.010
0.015
5
10
20
150
300
600
,.,A
,.,A
,.,A
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
4.95
9.95
14.95
1.5
3.0
4.0
Max
4.95
9.95
14.95
5
10
15
2
4
6
Min
Units
Typ
4.95
9.95
14.95
Min
1.5
3.0
4.0
V
V
V
1.5
3.0
4.0
V
V
V
Voo = 5V, Vo = 0.5V or 4.5V
Voo = 10V, Vo = 1.0V or 9.0V
V oo =15V, Vo =1.5Vor 13.5V
Voo = 5V, Vo = 0.5V or 4.5V
Voo = 10V, Vo = 1.0V or 9.0V
Voo = 15V, Va = 1.5V or 13.5V
3.5
7.0
11.0
3.5
7.0
11.0
3
6
9
3.5
7.0
11.0
V
V
V
Low Level Output Current
(Note 3)
Voo = 5V, Va = 0.4V
Voo = 10V, Va = 0.5V
Voo = 15V. Va = 1.5V
2.85
4.96
19.3
2.27
4.0
15.6
3.6
9.0
34.0
1.6
2.8
10.9
mA
mA
mA
10H
High Level Output Current
(Note 3)
Voo = 5V, Va = 2.5V
Voo = 10V. Vo = 9.5V
Voo=15V. Vo =13.5V
7.96
4.19
16.3
6.42
3.38
13.2
4.49
2.37
9.24
mA
mA
mA
liN
Input Current
Voo= 15V. VIN =OV
Voo=15V. VIN =15V
DC Electrical Characteristics
(Note 2) -
-0.10
0.10
100
Parameter
Quiescent Device Current
VOL Low Level Output Voltage
VOH High Level Output Voltage
Conditions
Min
Voo =5V, VIN=VOOorVss
Voo = 10V, VIN = Voo or Vss
Voo =15V, VIN=VOOorVss
Voo=5V
Voo = 10V
Voo=15V
11 0 1< 11'A
Voo=5V
Voo=10V
Voo = 15V
1101 < 11'A
-1.0
1.0
,.,A
,.,A
CD4541BC
-40°C
Sym
13.0
8.0
30.0
-10 5 -0.10
10-5 0.10
25°C
85°C
Units
Typ
Max
20
40
80
0.005
0.010
0.015
20
40
80
150
300
600
,.,A
,.,A
,.,A
0.05
0.05
0:05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
Max
4.95
9.95
14.95
Min
4.95
9.95
14.95
Min
Max
4.95
9.95
14.95
5
10
15
V
V
V
1.5
3.0
4.0
VIL
Low Level Input Voltage
Voo=5V. Vo=0.5Vor 4.5V
Voo = 10V, Va = 1.0V or 9.0V
Voo=15V. Vo =1.5Vor 13.5V
VIH
High Level Input Voltage
Voo =5V, Vo=0.5Vor 4.5V
Voo = 10V. Va = 1.0V or 9.0V
Voo= 15V, Va = 1.5V or 13.5V
3.5
7.0
11.0
3.5
7.0
11.0
3
6
9
3.5
7.0
11.0
V
V
V
10L
Low Level Output Current
(Note 3)
Voo =5V, Va =0.4V
Voo = 10V, Vo = 0.5V
Voo =15V, Vo =1.5V
2.32
3.18
12.4
1.96
2.66
10.4
3.6
9.0
34.0
1.6
2.18
8.50
mA
mA
mA
5·296
1.5
3.0
4.0
2
4
6
1.5
3.0
4.0
V
V
V
o
DC Electrical Characteristics
(Note 2) -
c
CD4541BC (Cont'd)
-55°C
Parameter
Sym
Conditions
IOH High Level Output Current
(Note 3)
Input Current
liN
Min
Voo =5V, Vo =2.5V
Voo = 10V, Vo = 9.5V
Voo = 15V, Vo = 13.5V
Max
Sym
Min
5.1
2.69
10.5
-0.3
0.3
125°C
Typ
4.27
2.25
8.8
Voo= 15V, VIN=OV
Voo = 15V, Vn.i = 15V
AC Electrical Characteristics
25°C
Min
Max
13.0
8.0
30.0
-10 5 -0.3
10-5
0.3
Max
3.5
1.85
7.22
mA
mA
mA
-1.0
1.0
JAA
JAA
TA =25°C, CL=50pF (refer to test circuits)
Parameter
Conditions
Min
Typ
Max
Units
hlH
Output Rise Time
Voo=5V
Voo=10V
Voo=15V
50
30
25
200
100
80
ns
ns
ns
tTHl
Output Fall Time
Voo=5V
Voo=10V
Voo=15V
50
30
25
200
100
80
ns
ns
ns
Turn"()ff, Turn-On Propagation Delay,
tplH,
tpHl Clock to (28 Output)
Voo=5V
Voo=10V
Voo=15V
1.8
0.6
0.4
4.0
1.5
1.0
JAS
JAs
JAs
Turn-On, Turn-Off Propagation Delay,
tpHl,
tpLH Clock to (2 16 Output)
Voo=5V
Voo=10V
Voo=15V
3.2
1.5
1.0
8.0
3.0
2.0
tWH(Cl) Clock Pulse Width
Voo=5V
Voo=10V
Voo=15V
JAS
JAS
JAs
ns
ns
ns
1.0
3.0
4.0
MHz
MHz
MHz
a
a
fCl
Clock Pulse Frequency
tWH(R)
MR Pulse Width
CI
Cpo
Power Dissipation Capacitance (Note 4)
400
200
150
200
100
70
2.5
6.0
8.5
Voo=5V
Voo=10V
Voo= 15V
Voo=5V
,Voo=10V
Voo=15V
Any Input
Average Input Capacitance
400
200
150
170
75
50
ns
ns
ns
5.0
7.5
pF
100
pF
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of
"Electrical Characteristics" provides conditions for actual device operation.
Note 2: Vss = OV unless otherwise specified.
Note 3: IOH and IOL are tested one output at a time.
Note 4: CPO determines the no load AC power consumption of any CMOS device. For complete explanation, see 54C/74C family
characteristics application note AN-90.
Truth Table
Division Ratio Table
A
B
Number of
Counter Stages
n
0
0
13
8192
0
1
10
1024
1
0
8
256
1
1
16
65536
Stete
Pin
0
5
Auto Reset Operating
Auto Reset Disabled
6
Timer Operational
Master Reset On
9
Output Initially Low
after Reset
Output Initially High
after Reset
10
Single Cycle Mode
1
Recycle Mode
5-297
~
m
s::
-4
Units
Count
2"
o
c
~
.j:o,
-4
m
o
o
~ Operating Characteristics
Q~
o
:i
m
~
-:::
Q
o
With Auto Reset pin set to a "0" the counter circuit is initialized by turning on power. Or with power already on,
the counter circuit is reset when the Master Reset pin is
set to a "1". Both types of reset will result in synchronously resetting all counter' stages independent of
counter state.
The RC oscillator frequency is determined by the external
RC network, Le.:
f=
23~
C
if(1kHz~f~100kHz)
.
te te
and Rs ::: 2 Rtc where Rs .. ,10 kQ
The time select inputs (A and B) provide a two-bit address
to output anyone of four counter stages (211, 210, 2 13, and
216). The 2n counts as shown in the Division Ratio Table
represent the a output of the Nth stage of the counter.
When A is "1", 216 is selected for both states of B.
However, when B is "0", normal counting is interrupted
and the 9th counter stage receives its clock directly from
the oscillator (i.e., effectively outputting 28).
The ala select output cbntrol pin provides for a choice
, of output level. When the counter is in a reset condition
and aia select pin is set to a "0" the a output Is a "0".
,Correspondingly, when aia select pin is set to a "1" the
a output is a "1".
When the mode control pin Is set to a "1", the selected
count is continually transmitted to the output. But, with
mode pin "0" and after a reset condition the RS flip-flop
resets (see Logic Diagram), counting commences and
after 2n -:-1 counts the RS flip-flop sets which causes the
output to change state. Hence, after another 2n - 1
counts the output will not change. Thus, a Master Reset
pulse must be applied or a change In the mode pin level
Is required to reset the single cycle operation.
Power Dissipation Test Circuit
and Waveform
Switching Time Test Circuit
and Waveforms
Voo
Voo
TLIF/600J-3
RS
RS
TL/FIBOO1-5
•
Q
TUF/6001-6
5-298
o
c
....~
CD
-o
3:
Oscillator Circuit Using RC Configuration
....CD~
r
-·IJ.
3~
I"
I
....,..QI_
o
.J,
~:>-t-o(l-o""-.....--r) TO CLOCK
. ~.V
~ CIRCUIT
INTERNAL
RESEl'
L ______
_ -----(
2
r
RS
cte RTC
TUF/6001-7
Typical RC Oscillator
Cnaracteristics
12.0
~
z0
4.0
w
0
~
:;
0
>-
<>
zw
-4.0
:::>
0
w
u.
oc
-8.0
-12.0
RC Oscillator Frequency as a
Function of RTC and C
~"L,~~ .
8.0
~
~~
oc
o
-
VOD=5V
VDD=10V
/
100~~
I=Sam
l=l~V=
tr
.... ..........
-, ...
:::::·~l:
...... .... ••"S.. ......
.... ......
-
N
:z:
~-
..
1
10.0'11111
l=
-,1.°gftlRlm
:5
!!od
C
2
D
•
LD
1
lifiL
PHASE
""'"Do-De>-'
I1tIl
-l-~
l
TUF/6002-3
*Transmission gates
Typical Applications.·
Liquid Crystal (LC) Readout
Incandescent Readout
APPROPRIATE
VOLTAGE
•
CD4543B
CD4543B
"""'"-4
OUTPUT 1-0-....
Ph
':" Vss
iLIFI6002-4
TUFI6002-5
Light Emitting Diad. (LED) Readout
VDD
CD4541B
DUTPUT
I-o-....""\,--.
Ph
CD'S03a
OUTPUT 1-00-'lN.,......
TUF/60()2.6
Note. Bipolar transistors may be added for gain (for Vee $ 10V or lOUT ~ 10 mAl
5·303
Typical Applications
(Continued)
Fluorescent Readout
Ga. Discharge Readout
APPROPRIATE
VOLTAGE
C045438
DUTPUT
1-0---.,
'"
Vss
CD454JB
DUTPUT
FILAMENT
SUPPl'!
_
VSS OR APPROPRIATE
-
VOLTAGE BELOW VSS
I-o-.......y,~--I
'"
":" VSS
TUF/6Q02.8
TUF/6Q02·7
3 1/2·Digit DVM with LCD Display
L
~
",I"IU
I .---
I-+-,....
","11"1
'---
BI
CD4543
LDA
. - - 81
BCD
-+- .....
LDA
tD4543
..r;::_
BCD
'"
~~
CD4643
ABC
0
ABC
DOEp--
I
VDDle>----IAA
?~
x-
.'4C916
LE
tl
UlIlllfNq.
D3 D2 D' DD
1.-.- SIGN
Ibcd"g
ADC35DI/ADC3701
DFLr----
3.9M,
31IIIk
TUF/6002-9
Display 9.999 when overflowed. All digits can also be blanked at overflow by tying OFL to BI on the CD4543's
5·304
Switching ~ime Waveforms
CPD Measurement Waveforms
A, BAND C
r-
VOH-~
ANV OUTPUT
-../
""--/'
VOL
TUF/6002-fO
Inputs 81 and Ph low, and inputs 0 and LD high. f in respect
to a system clock.
All outputs connected,to respective CL loads.
Dynamic Signal Waveforms
(bl Inputs D. Ph and BI low. and inputs A and B high
(allnputs D. Ph and Bilow. and inputs A. Band LD high
=:l~0'" .
---!20"'1-
VDD--------~r-~...Dm.------------~
',:
'~--:'lG.
'.
VOO ------;:::".L
LO
VS,-----------r~~-----------------------
';r-H
VOD------f--/----------~
C
VOL----------~r_~------------~l~O~~
=I
--l IIf
Vss
I,
,VOH------------------------------~""_____
TLIF/6002·11
VOL-----------------------------TL/Ff6002·12
-------------D
(cl Data DCBA strobe into latches
LO VDD
V,S -------------
50%
PWLO
5-305
_____________
-
TLIFI6002-,3
~National-
~ Semiconductor
CD4723BM/CD4723BC Dual 4-Bit Addressable Latch
CD4724BM/CD4724BC 8·Bit. Addressable, Latch
General Description
The CD47238 is a dual 4-bit addressable latch with common control inputs, including two address inputs (AO, A1),
an active low enable input (E), and an active high clear
input (CL). Each latch has a data Input (D) and four outputs (00·03). The CD47248 Is an B·bit addressable latch
with three address inputs (A()'A2), an active low enable
input (E), active high clear input (CL), a data input (D)
and eight outputs (OO·07)t
Data is entered into a particular bit in the latch when that
Is addressed by the address inputs and the enable (E) 15
low. Data entry is inhibited whim enable (E) is high.
When clear (CL) and enable (E) are high, all outputs are
low. When clear (CL) is high and enable (E) is low, the
channel demultiplexing occurs. The bit that is
addressed has an active output which follows the data
input while all unaddressed bits are held low. When operating In the addressable latch mode (E = CL = low),
changing more than one bit of the address could
impose a transient wrong address. Therefore, this
should only be done ,while In the memory mode
(E = high, CL = low).
Features
3.0Vto 15V
• Wide supply voltage range
0.45 VDD (typ.)
• High noise Immunity
fan out of 2 driving 74L
or 1 driving 74LS
• Low power TTL
compatibility
• Serial to parallel capability
• Storage register capability
• Random (addressable) data entry
• Active high demultiplexing capability
• Common active higl) clear
Connection Diagrams
CD4723B
CD4724B
Dual-ln·Line Package _
U
Dual-in-Line Pac;,kage
U
~VDD
AD ..!.
Al.l
~.!.:CL
Al.l
.!.!..CL
D,.2.
r!!-.
AZ .2.
.!!..
OD,...!
r!!- Db
OO...!
..!!.D
01,..!.
..!!. D3b
01.:l.
lZ";';"0)
OZ,...!.
.!!.uz
, b
OZ...!.
..!.!..06
AD..!.
.!.!..Voo
\
03,.2.
.!.!..Olb
03.2.
..!!.03
vss..!.
.LoDb
vss..!.
.L 04
TOP VIEW
TOP VIEW
TUF/6003·1
Order Number CD4723BMJ, CD4723BCJ,
CD4724BMJ or CD4724BCJ
See NS Package J16A
Order Number CD4723BMN, CD4723BCN,
CD4724BMN or CD4724BCN
See NS Package N16E
TLIF/6003-2
\
Truth Table
MODE SELECTION
e-
Cl
ADDRESSED
lATCH
UNADDRESSED
lATCH
MODE
l
l
Addressable Latch
l
Follows Data
Holds Previous Data
Holds Previous Data
H
Holds Previous Data
Memory
L
H
Follows Data
H
H.
Reset to "0'"
Reset to "0"
Reset to "0"
Clear
5·306
Demultiplexer
Absolute Maximum Ratings
Recommended Operating Conditions
(Notes 1 and 2)
(Note 2)
Voo DC Supply Voltage
-0.5 to +18Voc
VIN Input Voltage
-0.5 to Voo + 0.5 Voc
-65·Cto +150·C
Ts Storage Temperature Range
500mW
Po Package Dissipation
260·C
TL Lead Temperature (Soldering, 10 seconds)
Voo DC Supply Voltage
VIN Input Voltage
TA Operating Temperature Range
CD4723BM/CD4724BM
CD4723BC/CD4724BC
3.0 to 15Voc
OtoVooVoc
-55·C to +125·C
-40·C to +85·C
DC Electrical Characteristics CD4723BM/CD47~4BM (Note 2)
Sym Parameter
Conditions
-55°C
Min
Max
25°C
Min
5.0
10
20
150
300
600
/AA
/AA
/AA
0.05
0.05
·0.05
0.05
0.05
0.05
V
V
V
Voo=5.0V
Voo=10V
Voo=15V
5.0
10
20
0.02
0.02
0.02
VOL Low Level
Output Voltage
1101" 1/AA
Voo=5.0V
Voo=10V
Voo=15V
0.05
0.05
0.05
0
0
0
VOH High Level
Output Voltage
1101"1/AA
Voo=5.0V
Voo=10V
Voo=15V
VIL Low Level
Input Voltage
Voo = 5.0 V, Vo=0.5Vor 4.5V
Voo =10V, Vo= 1.0V or 9.0V
Voo=15V, Vo =1.5V or 13.5V
VIH High Level
Input Voltage
Voo = 5.0 V, Vo=0.5Vor 4.5V
Voo=10V, Vo=1.0Vor9.0V
Voo=15V, Vo=1.5Vor 13.5V
10L Low Level
Output Current
(Note 3)
10H High Level
Output Current
(Note 3)
Voo = 5.0V, Vo = 0.4 V
Voo=10V, Vo=0.5V
Voo=15V, Vo=1.5V
Voo=5.0V, Vo=4.6V
Voo=10V, Vo =9.5V
Voo =15V, Vo =13.5V
Input Current
Min
Units
Max
100 Quiescent
Device Current
liN
12S"C
Typ
Max
.'
4.95
9.95
14.95
4.95
9.95
14.95
1.5
3.0
4.0
5.0
10
15
2.25
4.5
6.75
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.5
8.25
0.64
1.6
4.2
-0.64
-1.6
-4.2
0.51
1.3
3.4
-0.51
-1.3
-3.4
0.88
2.25
8.8
-0.88
-2.25
-8.8
Voo'=15V, VIN=OV .
Voo =15V, VIN = 15V
-10- 5
10-5
-0.1
0.1
4.95
9.95
14.95
V
V
V
1.5
3.0
4.0
1.5
3.0
4.0
\
V
V
V
3.5
7.0
11.0
V
V
V
0.36
0.9
2.4
-0.36
-0.9
-2.4
mA
mA
mA
mA
mA
mA
-0.1
0.1
-1.0
1.0
/AA
/AA
DC Electrical Characteristics CD4723BC/CD4724BC (Note 2)
Sym Parameter·
Conditions
-40"C
Min
Ml!x
25°C
Min
85°C
Typ
Max
Min
Max
Units
100 Quiescent
Device Current
Voo=5.0V
Voo=10V
Voo=15V
20
40
80
0.02
0.02
0.02
20
40
80
150
300
600
/AA
/AA
/AA
VOL Low Level
Output Voltage
1I01"1/AA
Voo=5.0V
Voo=10V
Voo=15V
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
VOH High Level
Output Voltage
1101 .. 1/AA
Voo=5.0V
Voo=10V
Voo=15V
VIL Low Level
Input Voltage
Voo = 5.0 V, Vo = 0.5 or 4.5 V
Voo =10V, Vo =1.0Vor 9.0V
Voo = 1SV, Vo = 1.5 V or 13.5 V
VIH High Level
Input Voltage
Voo=5.0V, Vo =0.5Vor 4.5V
Voo = 10V, Vo = 1.0V or 9.0V
Voo=15V, Vo =1.5Vor 13.5V
4.95
9.95
14.95
4.95
9.95
14.95
1.5
3.0
4.0
3.5
7.0
11.0
5·307
5.0
10
15
2.25
4.5
6.75
3.5
7.0
11.0
2.75
5.5
8.25
4.95
9.95
14.95
1.5
3.0
4.0
V
V
V
1.5
3.0
4.0
3.5
7.0
11.0
V
V
V
V
V
V
DC Electrical Characteristics (Cont'd.) CD4723BC/CD4724BC (Note 2)
Sym Parameter
-400c
Conditions
Min
Max
25"C
Min
Typ
85"C
\
Max
'Mln
Max
Units
10L Low Level
Output Current
(Note 3)
Voo=5.0V, Vo=0.4V
Voo =10V, Vo=0.5V
Voo = 15V,.Vo = 1.5V
0.52
1.3
3.6
0.44
1.1
3.0
0.88
2.25
8.8
0.36
0.9
2.4
mA
mA
mA
10H High Level
Output Current
(Note 3)
Voo=5.0V, Vo=4.6V
Voo = 10V, Vo = 9.5 V
Voo=15V, Vo=13.5V
-0.52
-1.3
-3.6
-0.44
-1.1
-3.0
-0.88
-2.25
-8.8
-0.36
-0.9
-2.4
mA
mA
mA
liN
Input Current
AC Electrical Characteristics
Symbol
:-0.30
0.30
Voo=15V, VIN=OV
Voo = 15V, VIN = 15V
-10-5 -0.30
10-5
0.30
-1.0
1.0
/J. A
/J. A
TA = 25°6, CL = 50pF, RL = 200k, Input tr =tr =20ns, unless otherwise noted.
Parameter
Conditions
Typ
Max
Units
Voo=5.0V
Voo=10V
Voo=15V
Voo=5.0V
Voo=10V
Voo=15V
200
75
50
200
80
60
400
150
100
ns
ns
ns
400
160
120
ns
ns
ns
Voo=5.0V
Voo=10V
Voo=15V
Voo =5.0V
Voo=10V
Voo = 15V
175
. 80
65
350
160
130
ns
ns
ns
225·
100
75
450
200
150
ns
ns
ns
tTHL, tTLH Transition Time (Any Output)
Voo=5.0V
Voo=10V
Voo=15V
100
50
40
tWH, TWL Minimum Data Pulse Width
Voo=5.0V
Voo=10V
Voo=15V
100
50
40
200
100
80
200
100
80
ns
ns
ns
ns
ns
ns
tpHL, tpLH Propagatior) Delay Date to Output
tpLH,tpHL Propagatidn Delay Enable to Output
tpHL
Propagation Delay Clear to Output
tpLH, tpHL Propagation Delay Address to Output
Min
tWH, tWL
Minimum Address Pulse Width
Vo o =5.0V
Voo=10V
Voo=15V
200
100
65
400
200
125
ns
ns
ns
tWH
Minimum Clear Pulse Width
Voo=5.0V
Voo=10V
Voo=15V
75
40
25
150
75
50
ns
ns
ns
Voo=5.0V
Voo=10V
Voo=15V
Voo =5.0V
Voo=10V
Voo=15V
Vo o =5.0V
Voo=10V
Voo=15V
40
20
15
80
40
30
ns
ns
ns
60
30
25
-15
0
0
-50
-20
-15
120
60
50
ns
ns
ns
50
30
20
ns
ns
ns
15
10
5
ns
ns
ns
pF
7.5
pF
tsu
. Minimum Set-Up Time Data to E
tH
Minimum Hold Time Data to E
tsu
Minimum Set-Up Time Address to E
tH
Minimum Hold Time Address to E
Cpo
Power DIssipation Capacitance
CIN
Input Capacitance
Voo=5.0V
Voo=10V
Voo=15V
Per Package
(Note 4)
Any Input
100
5.0
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed; they are not
meant to Imply that the devices should be operated at these limits. The tables 01 "Recommended Operating Condillons" and "Electri·
cal Characterlsllcs" provide conditions for actual device operallon.
Note 2: Vss = OV unless otherwise specified.
Nole 3: 10H and 10L are tested one output at a time.
Nole 4: Dynamic powerdissipallon (Po) isgiven by: Po = (Cpo + CLl Vcc2f + PQ; where CL = load capacitance; I = frequency 01 operation; lor
lurther detailS, see application note AN·90, "54C/74C Family Characteristics".
5-308
,
(
Logic Diagrams
.
TLIF/6003·3
5·309
Logic Diagrams (Cant'd.)
CD4724B
Q2
03
04
05
06
01
TWFI600H
5·310
Switching Time Waveforms
I-----IWH - - - - - - I
AD,Al.A2
'VIH,
DATA
CLEAR
aD
tPHL
a7
TUF/6003·5
!
1
.1
I
I
5·311
Section 6
MM54CXXXI
MM74CXXX
Section Contents
M M54COOI M M7 4COO Quad 2-lnput NAN D Gate .......................................
MM54C02/MM74C02Quad2-lnputNORGate.........................................
MM54C04/MM74C04 Hex Inverter .... -. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54C08/MM74C08Quad2-lnputANDGate.........................................
MM54C10/MM74C10Tripie 3-lnput NAND Gate .......................................
MM54C14/MM74C14 Hex Schmitt Trigger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M M54C201 M M7 4C20 Dual4-lnput NAN D Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54C30/MM74C30 8-lnput NAND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54C32/MM74C32 Quad 2-lnput OR Gate ..... : . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .
MM54C42/MM74C42 BCD-to-Decimal Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54C48/MM74C48 BCD-to-7-Segment Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .
MM54C73/MM74C73 Dual J-K Flip-Flops with Clear ............. :. . . . . . . . . . . . . . . . . . . . . .
MM54C74/MM74C74 Dual D Flip-Flop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54C76/MM74C76 Dual J-K Flip-Flops with Clear and Preset ..........................
MM54C83/MM74C83 4-Bit Binary Full Adder ............................... ',' . . . . . ... .
MM54C85/MM74C85 4-Bit Magnitude Comparator ............................... , . . . .
MM54C86/MM74C86 Quad 2-lnput EXCLUSIVE-OR Gate ............ , . '........... , . . . . . .
MM54C89/MM74C89 54-Bit (16 x 4) TRI-STATE Random Access Memory. . . . . . . . . . . . . . . . . .
MM54C90/MM74C90 4-Bit Decade Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54C93/MM74C93 4-Bit BinaryCounter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54C95/Mfy174C95 4-Bit Right-ShiftiLeft-Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54C107/MM74C107 Dual J-K Flip-Flops with Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54C150/MM74C150 16-Line to 1-Line Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54C151/MM74C151 8-Channel Digital Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54C154/MM74C154 4-Line to 16-Line Decoder/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . .
MM54C157/MM74C157Quad2-lnput Multiplexer ................ :.....................
M M54C1601 M M7 4C160 Decade Counter with Asynchronous Clear .......................
MM54C161/MM74C161 Binary Counter with Asynchronous Clear ........................
MM54C162/MM74C162 Decade Counter with Synchronous Clear ........................
MM54C163/MM74C163 BinaryCounter with Synchronous Clear .........................
MM54C164/MM74C164 8-Bit Parallel-Out Serial Shift Register ..........................
MM54C165/MM74C165 Parallel-Load 8-Bit Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M M54C1731 M M7 4C173 TRI-STATE Quad D FI i p-Flop .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54C174/MM74C174 Hex D Flip-Flop .............................................
MM54C175/MM74C175Quad D Flip-Flop............................................
MM54C192/MM74C192 Synchronous4-Bit Up/Down Decade Counter. . . . . . . . . . . . . . . . . . . . .
MM54C193/MM74C193 Synchronous 4-Bit Up/Down Binary Counter. . . . . . . . . . . . . . . . . . . .. .
MM54C195/MM74C195 4-Bit Register ..............................................
M M54C200/M M74C200 256-Bit (256 x 1) TRI-STATE Random Access Memory ..............
MM54C221/MM74C221 Dual MonostableMultivibrator.................................
MM54C240/MM74C240 Octal Buffers and Line Drivers with TRI-STATE
Outputs (Inverting). . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54C244/MM74C244 Octal Buffers and Line Drivers with TRI-STATE
Outputs (Non-Inverting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .
M M54C373/MM74C373 Octal Latch with TRI-STATE Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . .
M M54C374/M M7 4C374 Octal D-Type Fli p-Flop with TRI-STATE Outputs. . . . . . . . . . . . . . . . . . . .
6-2
6-5
6-5
6-5
6-9
6-5
6-12
6-5
6-15
6-18
6-20
6-22
6-27
6-30
6-27
6-34
6-38
6-41
6-44
6-48
6-48
6-52
6-27
6-54
6-59
6-63
6-66
6-68
6-68
6-68
6-68
6-73
6-77
6-81
6-84
6-87
6-90
6-90
6-94
6-97
6-101
6-105
6-105
6-110
6-110
Section Contents (Continued)
MM54C901/MM74C901 Hex Inverting TTL Buffer
MM54C902/MM74C902 Hex Non-Inverting Buffers
MM54C903/MM74C903 Hex Inverting PMOS Buffer
MM54C904/MM74C904 Hex Non-Inverting PMOS Buffers
MM54C905/MM74C905 i'2-Bit Successive Approximation Register
MM54C906/M M74C906 Hex Open Drai n N-Channel Buffer
MM54C907/MM74C907 Hex Open Drain P-Channel Buffer
MM54C909/MM74C909 Quad Comparator
MM54C910/MM74C910 256-Bit (64 x 4) TRI-STATE Random Access Memory
M M54C914/M M74C914 Hex Schmitt Trigger with Extended Input Voltage
MM54C915/MM74C915 7-Segment-to-BCDConverter
MM54C9~2/MM74C922 16-Key Keyboard Encoder
MM54C923/MM74C923 20-Key Keyboard Encoder
MM54C932/MM74C932 Phase Comparator
MM54C941/MM74C941 Octal Buffers/Line Receivers/Line Drivers with
TRI-STATEOutputs
MM54C989/MM74C989 64-Bit (16 x 4) TRI-STATE Random Access Memory
MM70C95/MM80C95 TRI-STATE Hex Buffers
MM70C96/MM80C96TRloSTATE Hex Inverters
MM70C97/MM80C97TRloSTATE Hex Buffers
MM70C98/MM80C98 TRI-STATE Hex Inverters
MM72C19/MM82C19TRI-STATE 16-Line to 1-Line Multiplexer
MM74C908 Dual CMOS30Voit Relay Driver
MM74C911 4-Digit LED Display Controller
MM74C912 6 Digit BCD LED Display Controller Driver
MM74C917 6-Digit Hex LED Display Controller Dr,iver
MM74C918 Dual CMOS30Voit Relay Driver
MM74C925 4-Digit Counter with Multiplexed 7-Segment Output Driver
MM74C926 4-Digit Counter with Multiplexed 7-SegmentOutput Driver
MM74C927 4-Digit Counter with Multiplexed 7-Segment Output Driver
MM74C928 4-Digit Counter with Multiplexed 7-Segment OutputDriver
MM74C945 41/2-Digit LCD Up Counter/Latch Driver
MM74C946 4-Digil LCD Up-Down Counter/LalchlDriver
MM74C947 4-Digil LCD Up-Down Counter/Latch/Driver
o'
M M74C956 4 Character LED Alphanumeric Display Controller Driver (17-Segment)
MM78C29/MM88C29 Quad Single-Ended Line Driver
MM78C30/MM88C30 Dual Differential Line Driver
0000
0
0
000
0
0
000
0
0
0
0
0
000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
000
000
000
0
000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
000
0
0
0
0
0
0
0
0
0
0
000
0
0
0
0
000
0
0
0
0
0
0
0000000000000000000000000000000
0
0
0
0
0
0
0
000
000
0
0
0
0
0
0
0
000
0
0
0
0
000
0
0
0
0
0
000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
0
0
0
0
0
000
0
000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
000
000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
000000000000000000000000000000000
000000:
0
0
000000000000000000000000000
000000000000000000000000000000000000
00
000
0
0
000
000
0
0
0
0
0
000
0
0
0
0
0
0
000
0
0
0
0
0
0000000000000000000000000000000000000000000000000000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000000000000000000000000000000000000000
00000000000000000000000000000000:
000
000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000
0
0
0
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
000000000000000000000000000000000000000000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00000000
0
000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
000000000000000000000000000000000000000000
0
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000
0
0
0
0
0
0
0
0
0
0
0
0
..
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
000
0
0
0
0
0
00
000
00000
63
0
000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00000000
6-117
6-117
6-117
6-117
6-121
6-126
6-126
6-129
6-134
6-138
6-141
6-145
6-145
6-151
6-155
6-160
6-164
6-164
6-164
6-164
6-54
6-169
6-173
6-180
6-180
6-169
6-186
6-186
6-186
6-186
6-190
6-197
6-190
6-204
6-208
6-208
3:
3:
~National
~
~ Semiconductor
8
3:
3:
MM54COO/MM74COO Quad 2-lnput NAND Gate
MM54C02lMM74C02 Quad '2-lnput NOR Gate
MM54C04lMM74C04 Hex Inverter
MM54C10/MM74C10 Triple 3-lnput NAND Gate
MM54C20/MM74C20 Dual 4-lnput NAND Gate
......
~
o
o
P
3:
3:
c.n
~
g
General Description
Features
These logic gates employ complementary MOS (CMOS)
to achieve wide power supply operating range, low
power consumption, high noise immunity and symmetric
controlled rise and fall times. With features such as this
the 54C/74C logic family is close to ideal for use in digital
systems. Function and pin out compatibility with series
54174 devices minimizes design time for those designers
already familiar with the standard 54/74 logic family.
• Wide supply voltage ~ange
• High noise immunity
All inputs ai'e protected Trom damage due to static discharge by diode clamps.to Vcc and GND.
• Low power
TTL compatibility
N
3.0Vto 15V
• Guaranteed noise margin
1.0V
0.45 Vcc (typ.)
• Low power
consumption
10 nW/package (typ.)
fan out of 2
driving 74L
3:
3:
......
~
o0
~N
3:
3:
~
oo
r---------------------------------------------------------------------------~~
3:
3:
~
Connection Diagrams
oo
Dual-In-Line Packages
MM54COO/MM74COO
MM54C02/MM74C02
MM54C04/MM74C04
~~
3:
3:
~
o......
o
3:
3:
......
~
TOP VIEW
TOPVIEW
Tl'FI58771
Order Number MM54COOJ,
MM74COOJ, MM54COON
or MM74COON
See NS Package J14A or N14A
TOP VIEW
TLlF158772
Order Number MM54C02J,
MM74C02J, MM54C02N
or MM74C02N
See NS Package J14A or N14A
MM54Cl0/MM74Cl0
lLlFIS877.J
Order Number MM54C04J,
MM74C04J, MM54C04N
orMM74C04N
See NS Package J14A or N14A
MM54C20/MM74C20
o......
~O
3:
3:
c.n
-~
3:
3:
......
i1
~
TOP VIEW
TOP VIEW
TLlF158?7.4
TUFI5871S
Order Number MM54Cl0J,
MM74Cl0J, MM54Cl0N
or MM74Cl0N
See NS Package J14A or N14A
Order Number MM54C20J,
MM74C20J, MM54C20N
or MM74C20N
See NS Package J14A or N14A
6-5
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
54C
74C
Storage T!!mperature Range
- 0.3V to Vee + 0.3V
Operating Vee Range
Maximum Vee Voltage
Package DIssipation
Lead Temperature (Soldering, 10 seconds)
-55·C to +125·C
-40·C to +85·0.
-65·Cto +150'C
3.0V t~15V
18V
500mW
3OO·C
DC Electrical Characteristics
Minimax limits apply across the guaranteed temperature range unless otherwise noted.
Symbol
I
Parameter
I
Conditions
I
Min
Max
Typ
Units
CMOS to CMOS
VIN(1)
Logical "1" Input Voltage
Vee =5.0V
Vee=10V
VIN(O)
Logical "0" Input Voltage
Vee=5.0V
Vee=10V
VOUT(1)
Logical "1" Output Voltage
Vee = 5.0V, 10= -10"A
Vee = 10V, 10 = ';"1O"A
VOUT(O)
Logical "0" Output Voltage
IIN(1)
Logical "1" Input Current
Vee = 5.0V, 10= +10"A
Vee =10V,lo=+10"A
Vee -15V, VIN-15V
IIN(O)
Logical "0" Input Current
Vee -15V, VIN - OV
Icc
Supply Current
Vee=15V
V
V
3.5
8.0
1.5
2.0
4.5
9.0
V
V
0.005
-1.0
V
V
0.5
1.0
V
V
1.0
"A.
15
"A
-0.005
"A
0,01
Low Power to CMOS
VIN(1)
Logical "1"lnput Voltage
VIN(O)
Logical "0" Input Voltage
VOUT(1)
Logical "1" Output Voltage
VOUT(O)
Logical "0" Output Voltage
' 54C, Vee=4.5V
74C, Vee = 4.75V
54C, Vce=4.5V
74C, Vce =4.75V
54C, Vcc-4.5V,.lo:'" -1O"A
74C, Vcc =4.7SV, 10= -10"A
Vee- 1.5
Vee -1.5 '
V
V
0.8
0.8
V
V
·4.4
4.4
0.4
0.4
54C, Vec=4.5V, 10= +10"A
74C, Vec = 4.75 V, 10= +10"A
V
V
V
V
CMOS to Low Power
VIN(1)
Logical "1" Input Voltage
VIN(O)
Logical "0" Input Voltage
VOUT(1)
VOUT(O)
54C, Vcc=4.5V
74C, Vce =4.75V
54C, Vcc=4.5V
74C, Vcc=4.75V
4.0
4.0
Logical "1" Output Voltage
54C, Vcc=4.5V, 10= -360"A
74C, Vec = 4.75V, 10= -360"A
2.4
2.4
Logical "0" Output Volta.ge
54C, Vcc= 4.5V, 10 = 360"A
74C, Vcc = 4.75V, 10 = 360 "A
.
V
V
1.0
1.0
V
V
V
V
0.4
0.4
V
,V
Output Drive (See 54C/74C Family Characteristics Data Sheet) (short circuit current)
ISOURCE
Output Source Current
ISOURCE
Output Source Current
ISINK
Output Sink Current
ISINK
Output Sink Current
Vcc = S.OV, VIN(O) = OV
TA =25'C, VOUT=OV
Vec = 10V, VIN(O) = OV
TA = 25'C, VOUT = OV
Vec - 5.0V, VIN(1) - S.OV
TA =2S·C, VOUT=Vec
Vcc -10V, VIN(1) -10V
TA=25'C, VOUT=VCC •
6·6
-1.75
mA
-8.0
mA
1.75
mA
8.0
mA
AC Electrical Characteristics
Symbol
3:
3:
TA = 25'C, C L = 50pF, unless otherwise specified.
Parameter
Conditions
U1
Typ
Min
Units
Max
ns
ns
90
50
30
3:
3:
Input Capacitance
Vcc=5.0V
VCC-10V
(Note 2)
6.0
pF
Power Dissipation Capacitance
(Note 3) Per Gate or Inverter
12
pF
0""'"
60
35
ns
ns
9
3:
3:
Input Capacitance
Vcc =5.0V
Vcc -10V
(Note 2)
7.0
pF
Power Dissipation Capacitance
(Note 3) Per Gate
18
pF
60
MM54C10lMM74C10
Propagation Delay Time to
Logical "1" or "0"
CPO
0
0
MM54COOIMM74COO, MM54C02IMM74C02, MM54C041MM74C04
Propagation Delay Time to
Logical "1" or "0"
~
0
100
70
MM54C20lMM74C20
~
0
U1
~
0
0
N
3:
Propagation Delay Time to
Logical "1" or "0"
70
40
Input Capacitance
Vcc =5.0V
Vcc- 10V
(Note 2)
Power Dissipation Capacitance
(Note'\3) Per Gate
115
80
ns
ns
9
30
:s:
pF
0""'"
pF
~N
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
~
0
3:
3:
U1
~
0
Nole 3: Cpo determines the no load'ac power consumption of any CMOS device. For complete explanation see 54CI74C Family Charac·
teristics application note - AN·90.
-
Typical Performance Characteristics
0""'"
0
Nole 2: Capacitance is guaranteed by periodic testing.
~
~
0
Power Dissipation vs Frequency
MM54COO/MM74COO,
MM54C02/MM74C02,
MM54C04/MM74C04
Guaranteed Noise Margin
Over Temperature vs Vee
Gate Transfer Characteristics
15V
15
10'
GUARANTEED OUTPUT "1" lEVEL
GU;AN;~EO
~
V'N (1)
13.5
12.5
""
.~
4.05
105
0.45
5.0
10
15
~
~~
:;;:"
10V
4.S0V
2,5
1.5
ill
c
~
~
0
3:
3:
~L o!SpF
10'
Vc<:."IOV
0""'"
.....
~
"\~ ~~
10'
~O
C,=IUpf
Vec ·50V
10
10'
10'
'0'
10'
105
INPUT FREQUENCY (Hz)
TLlFI587Hl
Propagation Delay vs
Ambient Temperature
MM54COO/MM74COO,
MM54C02/MM74C02,
MM54C04/MM74C04
MM54COO/MM74COO,
MM54C02/MM74C02,
MM54C04/MM74C04
150
~
~
60 - - 40
2D
--
_I-'"
o f--- --50 -25 0
c'C~
~
~
100
20=
Vcc=30V'~
-f
---:~-l
-+++-
3:
3:
SEE ACTEST
-.~./
50
Vee -15V
-f--
25 50 15 100 125
AMBIENT TEMPERATURE (DC)
-50 -25 0
25 50 15 100 125
AMBIENT TEMPERATURE (OC)
20
100
50
150
Cl -lOA,D CAPACITANCE (pF)
I
TLlF!5877-9
TLlFl5877·11
6-7
~
N
H--f-V+~li-+-Vce ~ 5i~
20
0""'"
0
CIRCUIT
1.. 1 + -
~
-
i
·c,I~~:;.=-
U1
0
0
rr±"'+:t,---'-,_"TT~...,.r_-':.•T""A~"2=5"'-C~-'
-
3:
3:
N
Propagation Delay Time vs
Load Capacitance
MM54COO/MM74COO,
MM54C02/MM74C02,
MM54C04/MM74C04
]
U1
-
TLlFI5877·6
Propagation Delay vs
Ambient Temperature
3:
3:
~
10 4
15V
.f'>o
0.....
.lA·ZIC
- POW£ROISSIP.o.TiONFOR
OTHER OEVICES IS ~IVEN
HYP,,-IC,+["oIIVLLI't
~
2
(O)@INPUTS'OV 1N (1)
V1N 10) _________
1.45
~
a
o
OUTPUT "0" LEVEL
V OUT
3:
3:
[II
Typical Performance Characteristics
(Cont'd)
Propagation Delay Time us
Propagation Delay Time VI
Load Capacitance
Load Capacitance
MM54C10/MM74C10
MM54C20IMM74C20
_ -:\50
oS
,
!
~
~
Vcc' 5.0V
I-"
150
Vee'
50
,
IE
.5:~
• 'II!.
Vcc =3.OV
100
~
Vee
TA "25 D C
SEE AC TEST CIRCUIT
!
>
lDO
"z
."5:~
A
TA -Z5°C
Vcc -3.0V qSEEACTESTCl RCUIT
~
~OV
V'1~
50
,
IE
Vee -1&V
Vee -15V
J.
J.
0
50
150
100
0
50
TLIF/58n.12
CMOS to CMOS
1'f-
-''I
.9,
t·
9
50%
V'N
OV
Vee
VOUT
150
TLIF/5877·13
Switching Time Waveforms and AC Test Circuit·
Vee
100
C, - LOAD CAPACITANCE (pF)
C, - LOAD CAPACITANCE (pF)
50%
.1
--
~~{
r-.l
F50%
50%
OV
NOTE: DELAVS MEASURED WITH INPUT I" If :s; 20 ns.
TLIFI5877-14
6·8
~National.
~ Semiconductor
MM54C08lMM74C08 Quad 2-lnput AND Gate
General Description
Features
Employing complementary MOS (CMOS) transistors to
achieve wide power supply operating range, low power
consumption and high noise margin, these gates provide basic functions used in the implementation of digital integrated circuit systems. The Nand P-channel
enhancement mode transistors provide a symmetrical
circuit with o'utput swing essentially equal to the supply
voltage. No dc power other than that caused by leakage
current is consumed during static condition. All inputs
are protected from damage due to static discharge by
diode clamps to Vcc and GND.
• Wide supply voltage range
3.0Vto 15V
1.0V
• Guaranteed noise margin
0.45 Vcc (typ.)
• High noise immunity
fan out of 2
driving 74L
• Lowpower
TTL compatibility
• Low power
consumption
10 nW/package (typ.)
Connection Diagram and Truth Table
Dual-In-Line Package
INPUTS
28
2Y
GND
TOI'V.EW
TLlFIS878·1
Order Number MM54C08J or MM74C08J
See NS Package J14A
Order Number MM54C08N or MM74C08N
See NS Package N14A
6·9
Y
B
L
L
L
L
H
L
H
L
L
H
H
H
H = High Level
2A
OUTPUT
A
L= Low Level
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
MM54COB, MM54CB6
MM74COB, MM74CB6
Storage Temperature Range
(Note
1)
Package Qisslpation
Operating Vee Range
Absolute Maximum Vee
Lead Temperature (Soldering, 10 seconds)
- 0.3V to Vee + 0.3V
-55·Cto +125·C
-
g
V
Vee "3.0V
100
H+-+++-I7I''+ Vee = 5.0V
"=
i~
Vee" lOV
50
,
..
1-+-I"'f=t-HVcc" 15V
o
IUD
50
150
C, - LOAD CAPACITANCE I.FI
TLlFI5B7B·2
AC Test Circuit
NOTE: DELAVS MEASURED WITH INPUT t •• t," 20 ns
TL/F/S878-3
Switching Time Waveforms
.-
I-~
-1-~
~ ~~=3~::-~ ~c'O%
....
VOUT
&0%
5Q%
DV
Tl.IFI5878·4
6-11
~National
~ Semiconductor
MM54C141MM74C14 Hex Schmitt Trigger
General Description
Features
The MM54C14/MM74C14 Hex Schmitt Trigger is a mono· • Wide supply voltage range
lithic complementary MOS (CMOS) integrated circuit
constructed with Nand P-channel enhancement tran· • High noise immunity
sistors. The positive and negative going threshold volt·
ages, VT+ and VT _, show low variation with respect to
temperature (typ. 0.0005 V/·C at Vcc = 10V), and hystere· • Lowpower
TTL compatibility
sis, VT+ - VT_ ;;. 0.2Vcc is guaranteed:
Connection Diagram
Dual·ln·Line Package
Vee
GND
Order Number MM54C14J or MM74C14J
See NS Package J14A
Order Number MM54C14N or MM74C14N
See NS Package N14A
6·12
0.70VCc!typ.)
0.4 Vce (typ.)
0.2 Vee guaranteed
0.4 Veetyp.
0.2 Vce guaranteed'
All inputs are protected from damage due to static dis· • HystereSiS
charge by diode clamps to Vee and GND.
TOP VIEW
3.0Vt015V
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
MM54C14
MM74C14
Storage Temperature Range
- 0.3V to Vee + 0.3V
Package Dissipation
Operating Vee Range "
Absolute Maximum Vee
Lead Temperature (Soldering, 10 seconds)
-55·Cto +125·C
-40·Cto +B5·C
-65·Cto +150·C
500mW
3.0Vto 15V
1BV
300·C
DC Electrical Characteristics
Minimax limits apply across the guaranteed temperature range unless otherwise noted.
I
CMOS to CMOS
Symbol
Parameter
I
Conditions
I
Min
I
Typ
I Max I Units
VT+
Positive Going Threshold Voltage
Vee=5V
Vee -10V
Vee=15V
3.0
6.0
9.0
3.6
6.B
10.0
4.3
B.6
12.9
V
V
V
VT_
Negative Going Threshold Voltage
Vee=5V
Vee -10V
Vee -15V
0.7
1.4
2.1
1.4
3.2
5.0
2.0
4.0
6.0
V
V
V
VT+ -VT_
Hysteresis
Vee- 5V
Vee- 1OV
vee -15V
1.0
2.0
3.0
2.2
3.6
5.0
3.6
7.2
10.8
V
V
V
VOUT(l)
Logical "1" Output Voltage
Vee =5V, 10= -101'A
Vee -10V, 10- 1Ol'A
4.5
9.0
VOUT(O)
Logical "0" Output Voltage
Vee = 5V, 10 = +101'A
Vee -10V, 10 - +1OI'A
IIN(l)
Logical "1" Input Current
Vee -15V, VIN-15V
IIN(O)
Logical "0" Input Current
Icc
Supply Current
Vee = 15V, VIN = OV
Vee =15V, VIN =OV/15V
Vee - 5V, VIN - 2.5V (Note 4)
Vee -10V, VIN - 5V (Note 4)
Vee -15V, VIN - 7.5V (Note 4)
I
V
V
0.005
-1.0
' 0.5
1.0
V
V
1.0
I'A
-0.005
0.05
20
200
600
I'A
15
I'A
I'A
I'A
I'A
CMOS/LPTTL Interface
VIN (l)
Logical "1" Input Voltage
Vee=5V
VIN(O)
Logical "0" Input Voltage
Vee=5V
VOUT(l)
Logical "1" Output Voltage
54C, Vee - 4.5 V, 10 - -3601'A
74C, Vee - 4.75V, 10 - -3601'A
'VOUT(O)
Logical "0" Output Voltage
54C, Vee=4.5V, 10 = 360l'A
74C, Vee-4.75V, 10-3601'A
V
4.3
0.7
V
V
V
2.4
2.4
0.4
0.4
V
V
Output Drive (See 54C/74C Family Characteristics Data Sheet) (short circuit current)
'SOURCE
Output Source Current
(P-Channel)
Vee =5V, VOUT=OV
TA =25·C
-1.75
-3.3
rnA
'SOURCE
Output Source Current
(P-Channel)
Vee =10V, VOUT=OV
TA =25·C
-B.O
-15
rnA
ISINK
Output Sink Current
(N-Channel)
Vee =,5V, VouT~Vee
TA =25·C
1.75
3.6
rnA
.ISINK
Output Sink Current
(N-Channel)
Vee = 10V, VOUT = Vee
TA =25·C
8.0
16
rnA
6-13
....
~r-----------------------------------------------------------------------------.
o
AC Electrical Characteristics
TA =2S0C, CL =50pF, unless otherwise specified.
~I--------.----------------------,r-----~--------------r--------r----~----~------I
Symbol
Parameter
Conditions
Min
Typ
Max
Units
80
0
ns
pF
~I--~--~----------------~----------------r-----~~--r---~~--I
~
220
400
ns
tpoo, tPD1
Oi
~:==~~~====~~~~~~~~~~~~~~:~:::~~:=~~~~~~t~~~~~~~========t========~=~~~=~=~:~=~=~~~==i
2
__ ______ ____ ______
__ ____________
______
I
P
~I
CIN
__ Cpo
S.O
~~
~
~
~
~~
~
L-____
~~
~
____
L-~
__
~
~
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device 'cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Noie 3: Cpo determines the no ioad ac power consumption of any CMOS device. For complete explanation see 54C174C Family Charac·
teristics application note - AN-gO.
Note 4: Only one of the six inputs is at 1/2 Vee, the others are either at Vee or GND.
Typical Applications
Low Power Oscillator
vee - - - - - - - . - - - - - - - -
tl""RCln~
v,.
-t2vcc~
tz""ACln vee-vT_
Vee -VT+
t,~
o
VOUT
VI
t
TL/F/5879·2
Not.: Thllquations assume 1, + 12 » tpdO + tpd1
Typical Performance Characteristics
Typical Transfer Characteristics
Vee
Guaranteed Trip Point Range
20
V,.
15
INPUT
12.9
~
.."'
15
"
~...
10
w
!:;
>
VOLTAGE
V,
2:.
V,.
Vee
'Tv,_
==
w
5V
"''"
"
!:;
>
V,.
~
'""
!!
VT +'
10
15
INPUT VOLTAGE (V)
10
20
TUF/5B79-3
OV
Vee
5
4.3
3.0
2.0
0.7
0
OUTPUT
VOLTAGE
10
1&
Vee (V)
OV
TLIF/5S79-4
Note: For more information on output drive characteristics, power dissipation, and propagation delayst see AN-gO.
6·14
TL/F/5879-5
~National
~ Semiconductor
MM54C30/MM74C30 a-Input NAND Gate
General Description
Features
The logic gate employs complementary MOS (CMOS) to
achieve wide power supply operating range, low power
consumption and high noise immunity. Function and
pin out compatibility with series 54/74 devices minimizes design time for those designers familiar with the
standard 54/74 logic family.
_ Wide supply voltage range·
All inputs are protected from damage due to static dis·
charge by diode clamps to Vee and GND.
- Low power
TTL compatibility
3.0Vto 15V
_ Guaranteed noise margin
1.0V
_ High noise immunity
0.45 Vee (typ.)
fan outof 2
driving 74L
Logic and Connection Diagrams
Dual·ln-Line Package
I ..
1,3
11
11
I,D
i8
\9
L
ll--r-'2-~--'
Jo
8
OUTPUT
r-
TLlFI5880·1
,
2
3
4
5
I'
6
GNO
TOP VIEW
TL/F/5880·2
Order Number MM54C30J or MM74C30J
See NS Package J14A
Order Number MM54C30N or MM74C30N
See NS Package N14A
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
MM54C30
MM74C30
Storage Temperature Range
(Note 1)
Package Dissipation
Operating Vee Range
Absolute Maximum Vee
Lead Temperature (Soldering, 10 seconds)
-,O.3Vto Vee +0.3V
-55·C to + 125·C
-40·C to +85OC
-65·C to + 150·C
500mW
3.0Vt015V
18V
300·C
J
DC Electrical Characteristics
MinImax limits apply across temperature range unless otherwise noted.
Symbol
I
Parameter
CMOS to CMOS
VIN(1)
Logical "1" Input Voltage
VIN(O)
Logical "0" Input Voltage
VOUT(1)
Logical "1" Output Voltage
- VOUT(O)
Logical "0" Output Voltage
'.
IIN(1)
IIN(O)
Icc
Logical "1" Input Current
Logical "0" Input Current
Supply Current
I
Conditions
I
Min
I
I
Typ
Max
3.5
8.0
Vee=5.0V
Vee- 1OV
Vee =5.0V
Vee- 1OV
0.5
1.0
V
V
V
V
V
V
0.005
-0.005
1.0
I'A
0.01
15
I'A
I'A
0.8
0.8
V
V
V
V
0.4
0.4
V
V
V
V
4.5
9.0
-1.0
Vee-15V, VIN-OV
Vee- 15V
Units
V
V
1.5
2.0
Vee=5.0V, 10= -101'A
Vee -10V, 10 - -1OI'A
Vee = 5.0V, 10 = +101'A
Vee-10V, 10- +101'A
'Vee -15V, VIN -15V
I
CMOSILPTTL Interface
V1N(1)
Logical "1" Input Voltage
54C, Vec=4.5V
74C, Vee-4.75V
VIN(O)
Logical "0" Input Voltage
54C, Vee=4.5V
74C, Vee-4.75V
VOUT(1)
Logical "1" Output Voltage
VOUT(O)
Logical "0" Output Vpltage
54C,
74C,
54C,
74C,
Yc~-1.5
Vee- 1.5
2.4
2.4
Vee = 4.5V, 10= -3601'A
Vee-4.75V, 10--36OI'A
Vee=4.5V, 10 = 360 l'A
Vee = 4.75V, 10 = 360l'A
Output Drive (See 54C174C Family Characteristics Data Sheet) (short circuit current)
Output Source Current
(P·Channel)
Output Source Current
(P·Channel)
Vee=5.0V, VOUT=OV
TA =25·C
Vee = 10V, VOUT = OV
TA =25·C
ISINK
Output, Sink Current
(N-Channel)
Vee='5.0V, VOUT=Vec
TA=25·C
ISINK
Output Sink Current
(N-Channel)
Vee - 10V, VOUT - Vee
TA =25·C
IsouReE
IsouReE
-1.75
-3.3
mA
-15
mA
1.75
3.6
mA
8.0
16
mA
i
-8.0
,
6·16
AC' Electrical Characteristics
:s::
:s::
U'I
TA = 25°C, CL =50pF, unless otherwise specified.
~
o
--~----+----------------------+---------------------+--------4-~~~----~------I~
Parameter
Symbol
Conditions
Propagation Delay Time to
Logical "1" or "0"
Min
Typ
Max
Units
125
180
ns
Vcc=5.0V
55
90
ns
Vcc- 1OV
Input Capacitance
(Note 2)
4.0
pF
CIN
~~-----r~--~~~~~--~----~~--~~~~----------~-------4--~--+-----~--=---I~
Power Dissipation Capacitance
(Note 3) Per Gate
26
pF
Cpo
~
tpd
~~~~~--------------~----------+-~~~--~~-r~~---I~
:s::
:s::
o
(,)
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Cpo determines the no load ac power consumption of any CMOS device. For complete explanation see 54C/74C Family Charac·
terlstics application note - AN-gO.
Typical Performance Characteristics
Propagation Delay Time vs
Load Capacitance
50
·100
150
CL -LOAD CAPAC1TANCE.i pf}
TLIF/58BO·3
SWitching Time' Waveforms
Vee
-1'1,0.9
50%
V,"
OV
Vee
VOUT
.1
~~{
AC Test Circuit
~II'-
0.9,,\,.
50%
--
50%
OV
NDTE: DELAYS MEASURED WITH INPUT Ir• I, '" 20 ns.
r-
V'N~VOUT
.1
.
CL "'50 pF
*
50%
TI.IFIS88G-4
....
6·17
TLlFI5880·5
o
~ ~ National
:E
:E
~
~
.
~ Semiconductor
MM54C32/MM74C32 Quad 2-lnput OR Gate
:E
:E
General· Description
Features
Employing complementary MOS (CMOS) transistors to
achieve low power and high noise margin, these gates
provide the basic functions used in the Implementation
of digital integrated circuit systems. The Nand
P·channel enhancement mode transistors provide a
symmetrical circuit with output swings essentially
equal to the supply voltage. This results in high noise
immunity over a wide supply voltage range. No dc power
other than that caused by leakage current is consumed
during static conditions. AII·inputs are protected against
static discharge damage.
• Wide supply voltage range
• Guaranteed noise margin
fan out of 2
driving 74L
• Lowpower
TTL compatibility
Dual·ln·L1ne Package
Vee
13
12
11
10
4
GND
TOPVIEW
TL/F/5881·1
Order Number MM54C32J or MM74C32J
Sea NS Package J14A
Order Number MM54C32N or MM74C32N
See NS Package N14A
6-18
1.0V
0.45 Vee (typ.)
• High noise immunity
Connection Diagram
14
3.0Vto 15V
Absolute Maximum Ratings (Note 1)
Voltage at Any Pin
Operating Temperature Range
MM54C32
MM74C32
Storage Temperature Range
-0.3V to Vcc + 0.3V
-55·Cto +125·C
-40·C to +S5·C
-65·C to + 150·C
Package Dissipation
500mW
Operating Vcc Range
3.0Vto 15V
Absolute Maximum Vcc
1SV
Lead Temperature (Soldering, 10 seconds)
300·C
DC Electrical Characteristics
Minimax limits apply across temperature range unless otherwise noted'.
Symbol
I
Parameter
I
Conditions
I
Min
I
I
Typ
Max
I
Units
CMOS to CMOS
VIN(1)
Logical "1" Input Voltage
VIN(O)
Logical "0" Input Voltage
VOUT(1)
Logical "1" Output Voltage
VOUT(O)
Logical "0" Output Voltage
IIN(1)
Logical "1" Input Current
Vcc -15V, VIN -15V
IIN(O)
Logical "0" Input Current
Vcc=15V, VIN=OV
Icc
Supply Current
Vcc -15V
Vcc =5.0V
Vcc- 1OV
Vcc- 5.OV
Vcc- 1OV
3.5
S.O
Vcc-5.OV, 10 - - 1O IlA
Vcc -10V, 10 - -101lA
Vcc=5.0V,10=10IlA
Vcc -10V, 10 -IOIlA
4.5
9.0
V
V
1.5
2.0
V
V
0.005
-1.0
V
V
0.5
1.0
V
V
1.0
IlA
IlA'
15
IlA
-0.005
0.05
CMOS/LPTTL Interface
VIN(1)
VIN(O)
VOUT(1)
VOUT(O)
Logical "1" Input Voltage
MM54C32
MM74C32
Vcc=4.5V
Vce- 4.75V
Logical "0" Input Voltage
MM54C32
MM74C32
Ve·c=4.5V
Vee- 4.75V
Logical "1" Output Voltage
MM54C32
MM74C32
Vec=4.5V, 10= -3601lA
Vee-4.75V, 10- -3601lA
Logical "0" Output Voltage
MM54C32
MM74C32
Vcc = 4.5V, 10 = 360llA
Vee - 4.75V, 10 - 360llA
V
V
Vce-1.5
Vee-l.tI
O.S
0.8
2.4
2.4
V
V
V
V
0.4
0.4
V
V
Output Drive (See 54C/74C Family Characteristics Data Sheet) (short circuit current)
ISOURCE
Output Source Current
(P-Channel)
Vec = 5.0V, VOUT='OV
TA =25·C
-1.75
ISOURCE
Output Source Current
(P-Channel)
Vec =10V, VOUT=OV
TA=25°C
-s.o
ISINK
Output Sink Current
(N-Channel)
Vee = 5.0V, VOUT = Vec
TA =25°C
ISINK
Output Sink Current
(N·Channel)
Vec = 10V, VOUT = Vee
TA = 25°C
AC Electrical Characteristics
Symbol
Parameter
tpd
Propagation Delay Time to
Logical "1" or "0"
CIN
Cpo
Input Capacitance
Power Dissipation Capacitance
-3.3
mA
-15
mA
1.75
3.6
mA
B.O
16
mA
TA ~25°C, CL =50pF, unless otherwise specified.
Typ
Max
Units
.Vee =5.0V
Vee- 1OV
Any Input (Note 2)
SO
35
150
70
ns
ns
5
pF
Per Gate (Note 3)
15
pF
Conditions
Min
Note 1: "Absolute Maximum. Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Cpo determines the no load ac power consumption of any CMOS device. For complete explanation see 54C/74C Family Charac·
teristics application note - AN-eO.
6-19
~ ~National
::i
::i
~
~ Semiconductor
MM54C421MM74C42 BCD-to-Declmal Decoder
::i
::i
General Description
The MM54C421MM74C42 one-of-ten decoder is a monolithic complementary MOS (CMOS) integrated circuit
constructed with N- and P-channel enhancement transistors_ This decoder produces a logical "0" at the output corresponding to a four bit binary input from zero to
nine, and a logical "1" at the other outputs. For binary
inputs from ten to fifteen all outputs are logical "1".
5OnW(typ.)
• Lowpower
10 MHz (typ.)
with 10V Vee
• Medium speed operation
Applications
Features
• Supply voltage range
power TTL
• Tenth
compatible
0.45 Vee (typ.)
• High noise Immunity
• Automotive
Data terminals
• Instrumentation
• Medical electronics
3Vto 15V
drive 2 LPTTL loads
• Alarm systems
• Industrial electronics
Remote metering
Com.puters
•
•
•
Schematic arid Connection Diagrams
Dual-In-Line Package
l
..
C
D
.
,
" " " " " " "
1
,
, ,
.
r
. . . 'J
6
GNO
TL/FI5881·2
Order Number MM54C42J or ~M74C42J
See NS Package J16A
TlIFI5882·1
Order Number MM54C42N or MM74C42N
See NS Package N16E
Truth Table
INPUTS
DeB A
0 0 0
0 0 1
0 , 0
0 1 1
0 1 0 0
o 1 0 1
o 1 1 0
o 1 11
o
o
o
o
1 0 0 0
1
1
1
1
1
1
1
o
o
o
1
1
1
1
0 1
1 0
1 '.
0 0
0 1
1 0
11
OUTPUTS
o,
o1
1 0
11
11
11
11
11
11
11
11
11
11
1 1
11
11
11
2 3 4 56 7 8 9
111111 11
1 1 1 1 1 1 1 1
o 1 1 1 1 1 11
1 0 1 1 1 1 11
1 1 0 , 1 1 1 1
11 1 0 1 1 1 1
11 1 1 0 1 1 1
11 1 1 1 0 1 1
11 1 1 1 1 0 1
11 111 1 1 0
11 111111
11 1 11111
11 11111 T
11 111111
, 1 111111
11 111111
6-20
Absolute Maximum Ratings (Note 1)
Voltage at Any Pin (Note 1)
Operating Temperature Range
MM54C42
MM74C42
Storage Temperature Range
-0.3V to Vcc + 0.3V
DC Electrical Characteristics Min 1m ax
Symbol
Package Dissipation
Operating Vcc Range
Absolute Maximum Vcc
Lead Temperature (Soldering, 10 seconds)
-55·C to +125·C
-40·C to +85·C
-65·C to +150·C
500mW
3.0V to 15V
18V
300·C
limits apply across temperature range unless otherwise n<;lted.
Parameter
Conditions
Min
Typ
Max
Units
CMOS to CMOS
Logical "1" Input Voltage
Vcc=5.0V
Vcc=10V
VIN(O)
Logical "0" Input Voltage
Vcc=5.0V
Vcc- 1OV
VOUT(1)
Logical "1" Output Voltage
Vcc=5.0V, 10= -1Of'A
Vcc -10V, 10- -10f'A
VOUT(O)
Logical "0" Output Voltage
Vcc=5.0V,lo=10f'A
Vee- 1OV,10-10f'A
IIN(l)
Logical "1" Input Current
Vec=15V, VIN =15V
IIN(O)
Logical "0" Input Current
Vec -15V, VIN-OV
Icc
Supply Current
Vee=15V
VIN(l)
-
3.5
8.0
V
V
1.5
2.0
4.5
9.0
V
V
V
V
0.5
1.0
-1.0
0.05
V
V
1.0
f'A
300
f'A
300
f'A
CMOS/LPTTL Interface
VIN(l)
Logical "1" Input Voltage
54C, Vec = 4.5 V
74C, Vee-4.75V
VIN(O)
Logical "0" Input Voltage
54C, Vee=4.5V
74C, Vec -4.75V
VciUT(l)
Logical "1" Output Voltage
54C, Vee = 4.5V, 10 = -360f'A
74C, Vee=4.75V, 10= -360f'A
VOUT(O)
Logical "0" Output Voltage
54C, Vcc=4.5V, 10 = 360 f'A
74C, Vcc-4.75V, 10-360f'A
V
V
Vcc- 1.5
Vee- 1.5
0.8
0.8
2.4
2.4
V
V
V
V
0.4
0.4.
V
V
Output Drive (See 54C/74C Family Characteristics Data Sheet) TA = 25·C (short circuit current)
ISOURCE
Output Source Current
Vcc = 5.0V, VIN(~) = OV, VOUT = OV
-1.75
ISOURCE
Output Source Current
Vcc - 10V, VIN(O) = OV, VOUT = OV
-8.0
ISINK
Output Sink Current
Vcc = 5.0V, VIN(l) = 5.0V, VOUT = Vcc
1.75
mA
ISINK
Output Sink Current
Vcc = 10V, VIN (1) = 10V, VOUT = Vcc
8.0
mA
AC Electrical Characteristics
Symbol
mA
mA
TA = 25·C, CL = 50 pF, unless otherwise specified.
Parameter
Conditions'
Min.
Typ.
Max.
Units
200
90
300
140
ns
ns
tpd
Propagation Delay Time to
Logical "0" or "1"·
CIN
Input Capacitance
(See note 2)
5
pF
CpD
Power Dissipation Capacitance
(See note 3)
50
pF
Vc c =5.0V
Vcc- 1OV
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Nole 3: CpD determines the no load ac power consumption of any CMOS device. For complete explanation see 54CI74C Family Charac·
teristi?s application note - AN-90.
6·21
~ ~National
51
:IE
I
:::E
:::E
~ Semiconductor
MM54C48/MM74C48 BCD-to-7 Segment Decoder
General Description
Features
The MM54C48/MM74C48 BCD·to·7 segment decoder
is a monolithic complementarY MOS (CMOS) integrated
circuit constructed with N· and P·channel enhancement
transistors. Seven NAN D gates and one driver are con·
nected in pairs to make binary·coded decimal (BCD)
data and its complement available to the seven decoding
AND·OR·INVERT gates. The remaining NAND gate and
three input buffers provide test blanking input/ripple·
l blanking output, and ripple·blanking inputs.
3.0V to 15V
• Wide supply voltage range
1.0V
• Gua~anteed noise margin
0.45 Vee (typ.)
• High noise immunity
fan out of 2
• Low power
driving 74L
TTL compatibility
• High current sourcing output (up to 50 mAl
• Ripple blanking for leading or trailing zeros (optional)
• Lamp test provisio"1
Connection Diagram
Dual·ln-Llne
Pac~age
OUTPUTS
Vee
I"
'f
"
14
13
12
11
10
•
r-
1
2
3
LAMP
------....
INPUTS .
TEST
4
RB
5
RS
OUTPUTI INPUT
BLANKING
INPUT
TOP VIEW
1
6
D
A
-------
I'
GND
INPUTS
TLiF/SB83.1
Order Number MM54C48N or MM74C48N
See NS Package N16E
Order Number MM54C48J or MM74C48J
See NS Package J16A
Numerical Designations
and Resultant Displays
Segment Identification
TLIFI5883-2
TLIFI5883-3
6-22
Absolute Maximum Ratings (Note 1)
Voltage at Any Pin
Operating Temperature Range
MM54C4B
MM74C4B
Storage Temperature Range
Package Dissipation
Operating Vee Range
Absolute Maximum Vee
Lead Temperature (Soldering, 10 seconds)
-0.3Vto Vee +0.3V
-55·Cto +125·C
-40·Cto +B5·C
-65·Cto +150·C
500mW
3.0Vto 15V'
1BV
300·C
DC Electrical Characteristics
MinImax limits apply across temperature range unless otherwise noted.
Symbol
I
I
Parameter
Conditions
I
Min
I
Typ
I
Max
I Units
CMOS to CMOS
VIN(1)
Logical "1" Input Voltage
Vee=5.0V
Vee- 1OV
VINIO)
Logical "0" Input Voltage
Vee=5.QV
Vec- 1OV
VOUTI1)
Logical "1" Output Voltage
(RB Output Only)
Vee=5.0V, 10= -10"A
Vee -10V,10--10"A
VOUTIO)
Logical "0" Output Voltage
Vee = 5.0V, 10= +10"A
Vee-10V, 10- +1O"A
IIN(1)
Logical "1" Input Current
Vee = 15.0V, VIN = 15V
IINIO)
Logical "0" Input Current
Vee-15V, VIN-OV
Icc
Supply Current
Vee- 15V
3.5
B.O
V
V
1.5
2.0
4.5
9.0
V
V
0.5
1.0
0.005
-1.0
V
V
1.0
-0.005
0.05
V
V
"A
"A
300
"A
CMOS/LPTTL Interface
-
VIN(1)
Logical "1" Input Voltage
54C, Vee =4.5V
74C, Vee-4.75V
VINIO)
Logical "0" Input V'?ltage
54C, Vee=4.5V
74C, Vee~4.7PV
VOUT(1)
Logical "1" Output Voltage
(RB Output Only)
54C, Vee=4.5V, 10= -50"A
74C, Vee-4.75V, 10- -50"A
VOUTIO)
LQgical "0" Output Voltage
54C, Vee=4.5V,10=360"A
74C, Vee-4.75V, 10-360"A
V
V
Vee -1.5
Vee 1.5
O.S
O.S
2.4
2.4
V
V
V
V
0.4
0.4
V
V
-O.SO
-4.0
rnA
rnA
Output Drive (See 54C/74C Family Characteristics Data Sheet)
IsouReE
Output Source Current
(P·Channel) (RB Output Only\
Vee=4.75V. VOUT=0.4V
Vee-10V. VouT =0.5V
ISINK
Output Sink Current
(N·Channel)
Vee = 5.0V. VOUT = Vee
TA -25·C
1.75
3.6
rnA
ISINK
Output Sink Current
(N·Channel)
Output Source Current
(NPN Bipolar)
Vee = 10V. VOUT = Vee
TA =25·C
Vee - 5.0V. VOUT - 3.4
Vee - 5.0V. VOUT - 3.0
Vee -10V, VOUT -S.4
Vee - 10V. VO UT - S.O
S.O
16
rnA
-20
-50
-65
-50
-65
rnA
rnA
rnA
rnA
'-
-20
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Cpo determines the no load ac power consumption of any CMOS device. For complete explanation see 54C/74C Family Charac·
teristics application note - AN-gO.
6·23
AC Electrical Characteristics
Symbol
TA = 2S·C. CL = so pF. unless otherwise specified.
Parameter
Conditions
Typ
Max
Units
tpdO. tpd1
Propagation Delay to a "1" or "0" on
Segment Outputs from Data Inputs
Vcc=S.OV
Vcc- 1OV
.Min
4SO
160
1SOO
SOO
ns
ns
tpdO
Propagation Delay to a "0" on
Segment Outputs from RB Input
Vcc- S.OV
Vcc- 1OV
SOO
180
1600
SSO
ns
ns
tpdO
Propagation Delay to a "0" on
Segment Outputs from Blanking Input
Vcc=S.OV
Vcc- 1OV
3S0
140
1200
4SO
ns
ns
tpd1
Propagation Delay to a "1" on
Segment Outputs from Lamp Test
Vcc=S.OV
.Vcc- 1OV
4SO
160
1S00
SOQ
ns
ns
tpd1
Propagation Delay to' a "1" on RB
Output from RB Input
Vcc=S.OV
Vcc- 1OV
600
2S0
2000
800
ns
ns
tpdO
Propagation Delay to a "0" on RB
Output from RB Input
Vcc=S.OV
Vcc- 1OV
140
SO
4SO
1S0
ns
ns
Typical Applications
Typical Connection Utilizing the Ripple-Blanking Feature
BCD DATA'
INPUT
r-' I
RBI
RBOI
BI
r-
RBI
[3r .
1 "L::1
1
------
-
Blanking Input Connection Diagram
RBB~I t - - RBI RBol
RBO/SI
81
81
'--r-
r--
r--I_I
-+-£>o---i
'I
·T L---l
IlSE..!!
'--MM74C'06
':"'
TLlF/5883·4
SEGMENT
OUTPUTS
TLlFI5883-5
(When R80/sll$ forctd low, all segment outpull are off
rega,dlessof thestllte of any other inputcondillon)
TO DISPLAY READOUTS
(Fust three stages will blank leading ~erDS. the fourth
stlIglwrll nOI blank zeros)
,
Light Emitting Diode (LED) Readout
vee
v"
t
-~~
? U~
-=1.
t
\
:JS
-J~
COMMON
CATHODE LED
v·1.1
~'-
v
I--
t
? Uq
-=1.
':'
TLIF/5883·6
6·24
I--
.
~ '- -1.1V
~,
COMMON
ANODE LED
':'
TL.IFI5B83-7
Typical Applications
(Cont'd)
Incandescent Readout
Fluorescent Readout
Vee
Vee
DIRECT
(lOW BRIGHTNESS)
--A Mament pre·warm resistor IS recommended to redllce filament
IhermalshockandmcreasetheelfectlvecoldreSlstanceofthe
'Ililment.
TL/F/5883·8
Liquid Crystal (LCI Readout
Gas Discharge Readout
APPROPRIATE
VOL TAGE
Vee
TLlFI5883·10
Orrectdcdrtveof LC'snot recommended lorltfe of lC re.wouts.
Truth Table
DECIMAL
OR
FUNCTION
INPUTS
LT
RBI
0
C
H
aI/Root
B
A
.
b
,
OUTPUTS
d
f
•
H
L
L
L
L
H
H
H
H
H
H
H
X
L
L
H
L
H
H
L
L
L
L
X
L
L
L
H
H
H
H
H
H
L
H
H
L
H
H
X
L
L
H
L
H
H
H
H
H
H
L
L
H
H
H
X
X
L
L
H
H
L
L
L
L
H
H
H
L
L
H
H
L
L
H
H
H
H
X
L
H
H
"
H
H
L
H
L
L
H
H
H
H
H
7
H
X
L
H
H
H
H
H
H
H
L
L
L
.L
8
9
H
X
H
L
L
H
H
H
H
H
H
H
X
H
L
L
L
H
H
H
H
H
H
H
L
L
H
H
10
11
H
X
H
L
H
L
H
L
L
L
H
H
L
H
H
X
H
L
H
H
H
L
L
H
H
L
L
H
12
13
14
15
H
X
H
H
L
H
L
H
L
H
X
H
H
H
H
L
L
L
H
L
L
H
H
H
H
H
X
H
H
L
H
L
H
L
H
L
L
L
H
H
H
H
H
X
H
H
H
H
H
L
L
L
L
L
L
L
X
X
X
X
L
L
L
L
L
L
L
L
H
L
L
H
L
H
H
L
H
L
L
L
H
L
H
0
1
2
3
4
5
6
BI
RBI
X
X
H
L
L
L
L
L
LT
L
X
X
X
X
X
H
.
H
L
NOTE
1
1
H
2
3
4
H "'" high leve'l, L "" low level, X "" irrelevant
Note 1: The blanking input (SII must be open when output functions 0-15 are desired. The ripple-blanking input (RBII must be high, if blanking
of a decimal zero is not desired.
Note 2: When a low logic level is applied directly to the blanking input (BI), all segment outputs are tow rE:gardtess of the level of any other input.
Note 3: When ripple-blanking input (RBO and inputs A, B, C, and 0 are at a low level with the lamp-test input high, all segment outputs go low
and the ripple-blanking output (RBOI goes to a low level (response condition!.
Note 4: When the blanking input/ripple-blanking output (SI/RBO) is open and a low is applied to the lamp-test input, all segment outputs are high.
tOne BI/RBO is wire-AND logic serving as blanking Input (80 and/or ripple-blanking output {RBOL
6-25
r------------------------------------------------------------------------,
~ ~National
~
~ ~ Semiconductor
:E
MM54C73/MM74C73, MM54C76/MM74C76,
t:::
~ MM54C107/MM74C107 Dual J-K Flip-Flops with
~ Clear and Preset
:E
:E General Description
These dual J-K flip-flops are monolithic complementary
MaS (CMOS) integrated circuits constructed with N-and
P-channel enhancement transistors. Each flip-flop has
independent J, K, clock and clear inputs and Q and Q
outputs. The- MM54C76/MM74C76 flip flops also include
preset inputs and are supplied in 16 pin packages.
These flip-flops are edge sensitive to the clock input
and change state on the negative going' transition of the
clock pulses. Clear or preset is independent of the clock
and is accomplished by a low level on the respective input.
Features
3Vto 15V
- Supply voltage range
drive 2 LPTTL loads
- Tenth power TTL
compatible
- High noise immunity
0.45 Vcc (typ.)
- Low power
50 nW (typ.)
- Medium speed operation
10MHz (typ.)
with 10V supply
Applications
- Automotive
_ Alarm systems
- Data terminals
- Industrial electronics
- Instrumentation
- Remote metering
- Medical electronics
- Computers
Logic and Connection Diagrams
MM54C73/MM74C73'and MM54C107/MM74C107
mm
Transmission Gate
n
CL
ctOCK~,
fi
CL
T
TlIF/5884·2
. MM54C76/MM74C76
TLIF/5B84·4
CL
LI
CL~CK~
MM54C73/MM74c73
CLOClA
1
MM54C107/MM74C107
MM54C76/MM74C76
h-;:====¥-
CIU~4 1
'. '
..
'. '
CL DCK I ~
lD ~.
'.
TlIFI5884·5
Note. A loglc"O" on cJear sets Oto logic "D."
Order Number MM54C73J,
MM74C73J, MM54C73N
orMM74C73N
See NS Package J14A or N14A
TlIFI58846
Note: Aloglc"O"onclearsetsOtologlc"O."
Order Number MM54C107J,
MM74C107J, MM54C107N
or MM74C107N
See NS Package J14A or N14A
6-26
'1:==,,:::...._
..---.::::t
Tl/F/5B8H
Note 1: A logiC "0" on dear sets 0 to a logiC "0 •
NOle2: A loglc"O" on presetsels0toa logic "1."
Order Number MM54C76J,
MM74C76J, MM54C76N
or MM74C76N
See NS Package J16A or N16A
Absolute Maximum Ratings
Voltage at Any Pin (Note 1)
Operating Temperature Range
MM54CXX
MM74CXX
Storage Temperature
Package Dissipation
Lead Temperature (Soldering, 10 seconds)
Operating Vcc Range
Vcc!Max)
-0.3Vto Vcc +0.3V
-55·Cto 125·C
-40·Cto +B5·C
-65·Cto 150·C
500mW
300·C
+3Vto15V
1BV
DC Electrical Characteristics Minimax limits apply across temperature range unless otherwise noted.
Symbol
I
Parameter
CMOS to CMOS
I
I
Conditions
VIN(1)
Logical "1" Input Voltage
Vcc =5.0V
Vcc- 1OV
VIN(O)
Logical "0" Input Voltage
Vcc =5.0V
Vcc- 1OV
VOUT(1)
Logical "1" Output Voltage
Vcc=5.0V
Vcc- 1OV
VOUT(O)
Logical "0" Output Voltage
Vcc=5.0V
Vcc- 1OV
IIN(1)
Logical "1" Input Current
Vcc=15.0V
IIN(O)
Logical "0" Input Current
Vcc=15.0V
Icc
Supply Current
Vcc=15.0V
Min
I
Typ
I
I Units
Max
3.5
B.O
V
V
1.5
2.0
V
V
4.5
9.0
V
V
0.5
1.0
1.0
-1.0
0.050
Low Power TTL to CMOS Interface
,
VIN(1)
Logical "1" Input Voltage
54C, Vcc =4.5V
74C, Vcc=4.75V
VIN(O)
.Logical "0" Input Voltage
54C, Vc c =4.5V
74C, Vcc =4.75V
VOUT(1)
Logical "1" Output Voltage
54C, Vcc = 4.5V, 10 = -360,..A
74C, Vcc=4.75V, 10= -360,..A
VOUT(O)
Logical "0" Outp':!t Voltage
54C, Vcc=4.5V, 10 = 360,..A
74C, Vcc= 4.75V, 10 = 360,..A
60
V
V
.'
,..A
,..A
,..A
V
Vcc- 1.5
O.B
2.4
V
V
0.4
V
1
Output Drive (See 54C/74C Family Characteristics Data Sheet) (short circuit current)
ISOURCE
Output Source Current
Vcc = 5.0V, VIN(O) = OV
TA =25·C, VOUT=OV
-1.75
mA
iSOURCE
Output Source Current
Vcc = 10V, VIN(O) = OV
TA =25·C, VOUT=OV
-B.O
mA
iSINK
Output Sink Current
Vcc = 5.0V, VIN (1) = 5.0V
TA = 25·C, VOUT = Vcc
1.75
mA
i SINK
Output Sink Current
Vcc -10V, VIN (1) -10V
TA = 25·C, VOUT =Vcc
B.O
mA
"
6·27
"
AC Electrical Characteristics TA=25°C, CL =50pF, unless otherwise noted.
Parameter
Symbol
Min.
Conditions
Max.
Typ.
Units
CIN
input Capacitance
Any Input
tpdo, tpdl
Propagation Delay Time to a
Logical "0" or Logical :'1" from
Clock to Q or Q
Vcc - 5.OV
Vcc=10V
180
70
300
110
ns
ns
tpdO
Propagation Delay Time to a
Logical "0" from Preset or Clear
Vc c =5.0V
Vcc=10V
200
80
300
130
ns
ns
tpd
Propagation Delay Time to a
Logical "1" from Pres~t or Clear
Vc c=5.0V
Vcc=10V
200
80
.300
130
ns
ns
ts
Time Prior to Clock Pulse that
Data must be Present
Vcc=5.0V
Vcc=10V
110
45
175
70
ns
ns
tH
Time after Clock Pulse that J
and K must be Held
Vcc =5.0V
Vcc=10V
-40
-20
0
0
ns
ns
tpw
Minimum Clock Pulse Width
tWL=twH
Vcc =5.0V
Vcc=10V
120
50
190
80
ns
ns
tpw
Minimum Preset and Clear
Pulse Width
Vcc =5.0V
Vcc=10V
90
40
130
60
ns
ns
fMAx
Maximum Toggle Frequency
Vcc =5.0V
Vcc=10V
t" tf
Clock Pulse Rise and Fall Time
Vcc =5.0V
Vcc=10V
5
2.5
7.0
pF
4.0
11.0
MHz
MHz
15
5
I'S
lAS
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Capacitance Is guaranteed by periodic testing.
Note 3: Cp~ determines the no load ac power consumption of any CMOS device. For complete explanation see 54C/74C Family Charac·
,
terlstlcs application note - AN-90.
AC Test Circuit
Tru.h Table
f
1'v
INPU~S
l-"~'H~
--C CLOCK
-
K P"ESET Q
.)v" -:1
tn+1
Preset
Clear
On
On
J
K
0
o·
0
0
0
0
0
On
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
1
1
'Qn
+Qn
tn
c,
CL
":'"
H~
1
~
an
tn :;: bit time before clock pulse.
t,,+l :;: bit time after clock pulse.
TUF/5884-8
* No change in output from
previous state.
.-
,
,
6·28
Typical Applications
Ripple Binarv Counters
74C Compatibility
....>-----__...______--,
C~~~~i~------
CLOCK------------------..J
TLlF15884-9
Guaranteed Noise Margin as a
Function of Vee
Shift Registers
_-fj--Q]
OATA _ _. . .
INPUT
15V
r:::=======::::---,
1J5
125
>------....- - - - - - . . J
405
305
C l O C K - - - - -.....
TLIF15B84-11
V'N (0) -_
""
25
145
15
045
4.S0V
lDV
lSV
TlIF/588412
Switching Time Waveforms
III
CMOS to CMOS
CLOCK
-,
JarlC
Jor K
Oor
il
50%
OV--------+-------J
v"
Q or
iii
----+---"""'
1,••0 - -
50%
OV-------------------,-t,
~
I, " 20 ns
TL/FI5884·13
6·29
.
~ Semiconductor
~National
MM54C74/MM74C74 Dual D Flip-Flop
General Description
The MM54C74/MM74C74 dual D flip flop is a
monolithic
complementary
MOS
(CMOS)
integrated circuit constructed with N· and
P·channel enhancement transistors. Each flip flop.
has independent data, preset, clear and clock
inputs and Q and o--.
--
-
-
.'I1'll~
A. (1) -
::r:L.D-l:4(15)
., 141
1l!2
~
A'131~./>o---~+-lf.-l--+-+---h:LjO-:-----,
D-!:J(2)
::: 1fr:!
Coltl)
_ _ _ _ _. , -_ _ _ _
~
J
-1
.--.0
/ .......
}JO-----.
~>O---t --.o-~~D-" ~,
-'
./
(91
TL.IFI6035·'
6·34
Absolut~
Maximum Ratings (Note 1)
Voltage at Any Pin
Operating Temperat!Jre Range
MM54CB3
MM74CB3
Storage Temperature Range
-55'C to 125'C
-40'C to +B5'C
-65'Cto +150'C
DC Electrical Characteristics
Symbol
I
Parameter
CMOS to CMOS
VIN(1)
Package Dissipation
Operating Vee Range
Absolute Maximum Vee
Lead Temperature (Soldering, 10 seconds)
-0.3V to Vee + 0.3V
Logical "1" Input Voltage
500mW
3Vto 15V
1BV
300'C
Minimax limits apply across temperature range unless otherwise noted.
I
Conditions
I
Min
I
Typ
I
Max
B.O
1.5
2.0
VIN(O)
Logical "0" Input Voltage
Vec =5.0V
Vee=10V
VOUT(1)
logical "1" Output Voltage
Vee = 5.0V, 10 = -10,..A
Vee = 10V, 10 = -10,..A
VOUT(O)
Logical "0" Output Voltage
Vec = 5.0V, 10 = + 10l'A
Vec=10V,lo=+10,..A
IIN(1)
Logical "1" Input Current
Vce =15V, VII!I=15V
IINIO)
Logical "0" Input Current
Vec =15V, VIN=OV
Icc
Supply Current
Vce=15V
4.5
9.0
V
V
V
V
0.005
-1.0
Units
V
V
3.5
Vee=5.0V
Vec=10V
I
0.5
1.0
V
V
1.0
I'A
-0.005
0.05
I'A
300
I'A
CMOSILPTTL Interface
VIN(1)
Logical "1" Input Voltage
54Q, Vee = 4.5V
74C, Vee = 4.75V
VIN(O)
Logical "0" Input Voltage
54C, Vce=4.5V
74C, Vee = 4.75V
VOUT(1)
Logical "1" Output Voltage
54C, Vce=4.5V, 10= -360,..A
74C, Vee = 4.75V, 10 = -36OI'A
VOUT(O)
Logical "0" Output Voltage
54C, Vee=4.5V, 10 = 360l'A
74C, Vee=4.75V, 10 = 360,..A
Vee- 1.5
Vee- 1.5
V
V
O.B
O.B
2.4
2.4
V
V
V
V
0.4
0.4
V
V
Output Drive (See 54C/74C Family Characteristics Data Sheet) (short circuit current)
IsouReE
Output Source Current
(P-Channel)
Vce=5.0V, VOUT=OV
TA =25'C
-1.75
-3.3
mA
IsouReE
Output Source Current
(P-Channel)
Vee = 10V, VOUT = OV
TA =25'C
-B.O
-15
mA
ISINK
Output Sink Current
(N-Channel)
Vee = 5.0V, VOUT = Vee
TA =25'C
1.75
3.6
mA
ISINK
Output Sink Current
(N-Channel)
Vee = 10V, VOUT = Vee
TA =25'C
B.O
16
mA
Note 1: "Absolute Maximum Ratings" are those values beyond .which the safety of the device cannot be guaranteed. Except for
"Operating Temperature F:lange" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Capacitance Is guaranteed by periodic testing.
Note 3: Cpo determines the no load ac power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note - AN-90.
6-35
o~ AC Electrical Characteristics TA = 25°C, CL =50pF, unless otherwise specified.
~I--------r-------------------.---------~------~-r------~-----r----'-----Condition·s
Parameter
Symbol
Min
Typ
Max
Units
pO
200
80
ns
ns
~1--~--1----------------+----------------+-----4-~~~--+---
Propagation Delay from Co
V =5.0V
120
::E
(i)
cc
Vcc=10V
tpd1
to C4
Propagation Delay from Sum
tpd1
450
oml--~----~~--~~~~--~--~~~-----------------+-------+--~--~--~~----I
Vcc= 5.0V
250
ns
90
150
ns
Inputs to C4
Vcc=10V
;Z
~I-------+------~----------~~---------------+------+-----~---+-----I
~
tpd1
Propagation Delay from Co to
Sum Outputs
Vcc=5.0V
Vcc=10V
350 '
125
550
200
ns
ns
tpd1
Propagation Delay from Sum
Inputs, to Sum Outputs
Vcc =5.0V
Vcc=10V
300
90
550
150
ns
ns
CI~
Cpo
Input Capacitance,
Any Input (Note 2)
5.0
pF
Power Dissipation Capacitance
Per Package (Note 3)
120
pF
SWitching Time Waveforms
Connection Diagram
Dual·ln·Line Package
C4
84
16
15
13
"
AI
81
GTND
CO
12
10
11
-
r-20",
--j
-20"
v" -_.--I!-.),.
1"-0'-.---'-O%.,j\
:/50%
INPUT
50%'
10%
OV~
-I ~""
-+'",""...'"",-""'0"'"%' I
I ~O%
Vee --- ---
-
OUTPUT
lOr.
OV
1-',
50%
10%
-1-"
Illputs mu.t he lied to appropriate logic level.
A4
82
83
A3
A2
TliF/B035-2
Order Number MM54C83J or MM74C83J
See NS Package J16A
Order Number MM54C83N or MM74C83N
, See NS Package N16E
Truth Table
OUTPUT
COH:~
~
INPUT
.
,
)
H
-:=
WHEN
~C~:~
WHEN
C2=L
C2=H
L
L
L
L
L
L
L
H
L
L'
H
L
L
L
H
L
L
L
H
L
L
H
L
L
H
L
L
L
H
L
H
H
L
L
L
H
L
H
H
L
L
L
H
L
L
H
L
H
H
L
H
L
H
L
H
H
L
L
L
H
L
H
H
L
H
H
L
L
L
H
H
H
H
L
L
L
H
H
L
H
L
L
L
H
L
H
L
H
H
L
H
L
L
H
H
H
L
L
L
H
L
H
L
H
H
H
L
L
L
H
H
H
L
H
L
L
H
H
L
H
L
L
H
H
L
L
H
H
L
H
H
L
H
H
H
L
H
L
H
H
L
H
H
H
H
L
H
L
H
H
H
H
H
L
H
H
H
H
H
H
high level, L = low level
Note: Input conditions at A3, A2, 82 and CO are used to determine outputs E1 and :E2 and the
value of the internal carry C2. The values at C2, A3, 83, A4, and 84 are then used to determine
outputs ~3, ~4, and C4.
6·36 \
Typi~al
Applications
..
APPLICATION
CASCADING
Connect the MM54C83/MM74C83' in the following
manner to implement a dual single bit full adder.
Connect the MM54C83/MM74C83 in the following
manner to implement full adders with more than 4 bits.
CINfOIl 11
AIBlTt)
B(BIT1)
BIT2
A,
B,
"
~(EUT 11
"
Cour 1BIT2)
LSB
----
"
'.
~IBIT2)
I
-=
Co
AIBIT 11
A,
B(B1111
B,
A(BIT21
A,
aiSIT2)
B,
A (BIT 3)
A,
B IBIT 3)
B,
A(81T41
A.
8(8114)
B.
"
'IBIT1)
~z
, IBIT2)
"
~
(BIT3)
~
IB114)
"
~
(BIT 51
"
~
(BIT 6)
"
~
{BIT 1)
MM54CBl
OR
MM14C83
'.
C.
Cour (BIT 2)
CO
TLIF16035·4
A(BITSI
A,
B (BITS)
B,
A IBIl 6)
A,
B ISIT6)
B,
MM54C83
OR
AIBIT7)
A,
BIBIl1)
B,
I A IBIT BI
MSB
I B(BIT8)
MM74C83
A.
'.
B.
~(B'T81
C.
CouTlea)
ITO NEXT PACKAGE)
TLIF/6035·5
'.
6-37
~ ~National
~ Semiconductor
:::E
:::E
-~ MM54C851MM74C85 4-Bit Magnitude Comparator
II)
,
:::E
.
:::E General Description
Features
The MM54C851MM74C85Is a four-bit magnitude comparator which will perform comparison of straight binary
or BCD codes. The circuit consists of eight comparing
Inputs (AO, A1, A2, A3, BO, B1, B2, B3), three cascading
Inputs (A> B, A < B and A B), and three outputs (A> B,
A < B and A = B). This device compares two four-bit
words (A and B) and determines whether they are
"greater than," "less than," or "equal to" each other by
a high level on the appropriate output. For words greater
than four-bits, units can be cascaded by connecting the
outputs (A> B, A < B, and A = B) of the least significant
stage to the cascade Inputs (A> B, A < B and A = B) of
the next-significant stage. In addition the least significant stage must have a high level voltage (VIN (l) applied
to the A = B input and low level voltages (VIN(O) applied
, to A> B and A < B Inputs.
=
• Wide supply voltage range
3.0Vto 15V .
1.0V
• Guaranteed noise margin
.. High noise Immunity
• Lowpower
TTL compatibility
0.45 Vee (typ.)
fan out of 2
driving 74L
• Expandable to 'N' stages
• Applicable to binary or BCD
• Low power pinout54L85174L85
Logic Diagram
TUFf!588&-1
6-38
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
MM54C85
MM74C85
Storage Temperature Range
I
Package Dissipation
Operating Vcc Range
Vcc
Lead Temperature (Soldering, 10 seconds)
-55·C to +125·C
-40·C to +85·(';
-65·C to +150·C
DC Electrical Characteristics
Symbol
(Note 1)
-0.3V to Vcc + 0.3V
Parameter
CMOS to CMOS
Logical "1" Input Voltage
VIN(1)
Minimax limits apply across temperature range unless otherwise noted
I
Conditions
I
Min
Vcc =5.0V
Vcc=10V
I
Typ
I
Max
3.5
8.0
VIN(O)
Logical "0" Input Voltage
Vcc- 5.OV
Vcc=10V
VOUT(1)
Logical "1" Output Voltage
Vcc = 5.0V, 10= -10"A
Vcc=10V, 10= -10"A
VOUT(O)
Logical "0" Output Voltage
Vcc = 5.0V, 10= +10"A
Vcc=10V, 10= +10"A
IIN(1)
Logical "1" Input Current
Vcc = 15V, VIN = 15V
IIN(O)
Logical "0" Input Current
Vcc -15V, VIN=OV
Supply Current
Icc
CMOS/LPTTL Interface
500mW
3.0Vt015V
18V
300·C
V
V
1.5
2.0
4.5
9.0
VIN(1)
Logical "1" Input Voltage
54C, Vcc=4.5V
74C, Vcc=4.75V
V1N(O)
Logical "0" Input Voltage
54C, Vcc = 4.5 V
74C, Vcc=4.75V
VOUT(1)
Logical "1" Output Voltage
54C,.Vcc=4.5V,10=--360"A
74C, Vcc = 4.75V, 10= -360"A
0.5
1.0
V
V
1.0
"A
-0.005
0.05
Vcc=15V
V
V
V
V
0.005
-1.0
I Units
"A
300
"A
V
V
-Vcc- 1:5
Vcc- 1.5
0.8
0.8
V
V
V
V
2.4
2.4
VOUT(O)
Logical "0" Output Voltage
ISOURCE
Output Source Current
(P-Channel)
Vcc = 5.0V, VOUT = OV
TA =25·C
-1.75
-3.3
mA
ISOURCE
Output Source Current
(P-Channel)
Vcc=10V, VOUT=OV
TA =25·C
-8.0
-15
mA
ISINK
Output Sink Current
(N-Channel)
Vcc = 5.0V, VOUT = Vcc
TA =25·C
1.75
3.6
mA
ISINK
Output Sink Current
(N-Channel)
Vcc = 10V, VOUT = Vcc
TA =25·C
8.0
16
mA
0.4
0.4
54C, Vcc = 4.5 V, 10 = 360 "A
74C, Vec = 4.75V, 10 = 360"A
Output Drive (See 54C/74C Family Characteristics Data Sheet) (short circuit current)
AC Electrical Characteristics
Symbol
Parameter
V
V
TA = 25·C, CL = 50 pF, unless otherwise specified.
Typ
Conditions
Min
Max
Units
250
100
600
300
ns
ns
500
250
ns
ns
Propagation Delay from any A
or B Data Input to any
Data Output
Vcc=5.0V
Vcc= 10V
tpd
Propagation Delay Time from
any Cascade Input to
any Qutput
Vcc =5.0V
Vcc=10V
200
100
CIN
Input Capacitance
Any Input
5.0
pF
Cpo
Power Dissipation Capacitance
(Note 3) Per Package
45
pF
tpd
..
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Cpo determines the no load ac power consumption of any CMOS dey ice. For complete explanation see 54C/74C Family Characteristics application note - AN-90.
6-39
Typical Applications
Connection Diagram
Four Digit Comparator
-LONGER WORD COM'ARISON-
Dual·ln·Line Package
COMPARING TWO t"IIT WORDS
WORD a
'0"
WORDA
!
BZ
!.
INPUTS
A2
OUTPUT A=B
~LSD"
"LSD"
13
A>B
CASCADING
.
INPUTS
,
A8
12 AB3
x
A3B2
x
x
A3 - B3
A2< B2
A3 - B3
A3'" 83
A2" B2
A3' ~3
A3 = B3
A2 - B2
A2 = B2
A3' B3
A2· B2
A3' B3
A2
A3· B3
A3 c B3
A2 = B2
A2 • B2
Al
A1
A1
Al
Al
Al
>81
< B1
= B1
"131
= 81
~ 81
A1 ' B1
A1 = B1
A1 = B1
A1 • B1
= B2
A3' B3
A2 • B2
A2 • B2
A3' B3
A2· B2
A2 • B2
H .. high level. L --low level, X
~
OUTPUTS
A-B
AO, BO
A>B
AB
ABO
X
X
X
L
H
H
L
X
L.
L
AO-
g
100
1-+4-+-+++-+++-+++-+-+-1
"
o
Vee
~
i
50
=:
10V
I-+-1"'R++-+- Vee'" 15V
I
J
100
50
150
LOAD CAPACITANCE (pF)
AC Test Circuit
NOTE: DELAYS MEASURED WITH INPUT t,-, I,
~
20
11$
TLIF15687·3
Switching Time Waveforms
Vee
_-+~t~t.----::--1~ ~ t,
1/90%
V,N
If 50%
10%
OV----'
90%
50%
1
--I I-- to!
Vee
----t-r---___.
Y50%
VOUT
50%
OV
TLlF/5857·4
6·43
~
i:! ~National
:E ~ Semiconductor
:E
m
~
MM54C89/MM74C89 64-Bit TRI·STATEID
; Random Access ReadlWrite Memory
:E
General Description
The MM54C89/MM74C89 is a 16·word by 4·bit random ac·
cess read/write memory. Inputs to the memory consist of
four address lines, four data input lines, a write enable line
and a memory enable line. The four binary address inputs
are decoded internally to select each of the 16 possible
word locations. An internal address register, latches the
address information on the po'sitive to negative transition
of the memory enable input. The four TRI·STATE data out·
put lines working in conjunction with the memory enable
input providi3, for easy memory expansion.
Read Operation: The complement of the information
which was written into the memory is non-destructively
read out at the four outputs. This is accomplished by
selecting the desired address and bringing memory
enable low and write enable high.
When the device is writing or disabled the output
assumes a TRI·STATE (Hi·z) condition.
Features
Address Operation: Address inputs must be stable tSA
prior to the positive to negative transition of memory
enable. It Is thus not necessary to hold address informa·
tion stable for more than tHA after the memory Is
enabled (positive to negative transition of memory enable).
Note: The timing is different that the DM7489 in that a
positive to negative transition of the memory enable
must occur for the memory to be selected.
Write Operation: Information present at the data inputs
Is written Into the memory at the selected address by
bringing write enable and memory enable low.
• Wide supply voltage range
3.0Vto 15V
• Guaranteed noise margin
1.0V
• High noise immunity
0.45 Vce (typ.)
fan out of 2
driving 74L
• Low power'
TTLcompatibility
100nW/package (typ.)
• Low power consumption
130 ns (typ.) at Vee = 10V ..
• Fast access time
• TRI·STATE output
Logic and Connection Diagrams
DATA
DATA
DATA
INPUT! OUTPUTIINPUTZ
DATA
iilliPiif'Z
OATA
DATA
DATA
INPUT] iiUfiiij'fJ I1'U14
DATA
Dual·ln·Line ,Package
ifiJ'ffii'f4
"
ADDRESSINPUTA 1
~mm2
wmTErnmr
ADDRESS INPUT B
14. ADDRESSINPurc
3
"
DATA IN'UT I 4
iiA'fA0UfiiITf1 5
WRTfE
EiiAiTE
11 DATA oirnuT4
DATAOUfPT.iTZ 7
ENABLE
ADDRESS INPUT 0
12DATAINPUT4
DATAINPUT2 6
MEMiiRi
v~
111 DATAINPUT,3
5 IJmlfOTllUTl
GNO
INPUT A
TOP VIEW
TlIF/5888·2
Order Number MM54C89J or
MM74C89J
See NS Package J16A'
INPUTB
Order Number MM54C89N or
MM74C89N
See NS Package N16E
INPUTe
TL/FI5SSB-l
6·44
Absolute Maximum Ratings (Note 1)
Voltage at Any Pin
Operating Temperature Range
MM54CB9
MM74CB9
Storage Temperature Range
- 0.3Vto Vcc + 0.3V
-55'Cto +125'C
-40'C to +B5'C
DC Electrical Characteristics
Symbol
Parameter
1
Package Dissipation
Operating Vcc Range
Absolute Maximum Vcc
Lead Temperature (Soldering, 10 seconds)
500mW
3.0Vto 15V
1BV
300'C
Minimax limits apply across temperature range, unless otherwise noted.
Conditions
1
I·
Min
1 Typ
1 Max 1 Units
CMOS to CMOS
V,N(1)
Logical "1" Input Voltage
V,NIO)
Logical "0" Input Voltage
VOUT(1),
Logical "1" Output Voltage
VOUTIO)
Logical "0" putput Voltage.
I'N(1)
I,NIO)
Logical "1" Input Current
loz
Icc
Logical "0" Input Current
Output Current in High
Impedance State
Supply Current
Vcc=5.0V
Vcc=10V
Vcc=5.0V
Vcc=10V
Vcc=5.0V, 10= -10,..A
Vcc =10V, 10= -10,..A
3.5
B.O
1.5
2.0
4.5
9.0
V
V
V
0.5
1.0
Vcc=5.0V, 10= +10,..A
Vcc=10V, 10= +10,..A
Vcc=15V, V,N=15V
Vcc = 15V, Y,N = OV
Vcc=15V, V=15V
Vcc = 15V, Vo = OV
V
V
-0.005
1.0
V
V
. ,..A
-1.0
-0.005
1.0
-1.0
0.005
-0.005
,..A
,..A
,..A
0.05
300
,..A
Vcc=15V
CMOS/LPTIL Interface
V'N (1)
Logical "1" Input Voltage
V,NIO)
Logical "0" Input Voltage
VOUTI1}
Logical "1" Output Voltage
VOUTIO)
Logical "0" Output Voltage
54C,
74C,
54C,
,74C,
Vcc=4.5V
Vcc = 4.75V
Vcc -4.5V
Vcc =4.75V
54C, Vcc-4.5V, 10- -36OI'A
74C, Vcc = 4.75V, 10 = -360,..A
V
V
Vc c - 1.5
Vcc- 1.5
O.B
O.B
V
V
V
V
0.4
0.4
V
V
2.4
2.4
54C, Vcc=4.5V, 10= +360,..A
74C, Vcc=4.75V, 10= +360,..A
Output Drive (See 54C/74C Family Characteristics Data Sheet) (short circuit current)
ISOURCE
Output Source Current
(P·Channel)
ISOURCE
Output Source Current
(P·Channel)
Output Sink Current
(N·Channel)
Vcc,= 5.0V, VOUT = OV
TA =25'C
Vcc = 10V, VOUT = OV
TA =25'C
Vcc - 5.0V, VOUT - Vcc
TA =25'C
Output Sink Current
(N·Channel)
Vcc -10V, VOUT - Vcc'
TA =25'C
ISINK'
IsiNK
AC Electrical Characteristics
Symbol
Parameter
-1.75
-3.3
rnA
-B.O
-15
rnA
1.75
3.6
rnA
B.O
16
rnA
TA =25'C"CL=50pF, unless otherwise noted.
Conditions
tpd
Propagation Delay from
Memory Enable
Vcc=5.0V
Vcc=10V
tACC
Access Time from
Address Input
tsA
Address Setup Time
tHA
Address Hold Time
tME
Memory Enable Pulse Width
tME
Memory Enable Pulse Width
Vcc=5.0V
Vcc=10V
Vcc=5.0V
Vcc=10V
Vcc=5.0V
Vcc=1OV
Vcc=5.0V
Vcc=10V
Vcc=5.0V
Vcc=10V
6·45
Min
Typ
Max
Units
270
100
350
130
500
220
650
2BO
ns
ns
ns
ns
ns
ns
150
60
60
40
400
150
250
90
400
150
200
70
ns
ns
ns
ns
ns
ns
. AC Electrical Characteristics (Cont'd.) TA = 25·C, CL = 50 pF, unless otherwise noted.
Symbol
tWE
Parameter
Write Enable Setup Time
for a Read
Write Enable Setup 1 ime
for a Write
Write Enable Pulse Width
tHO
uala Input HOla lime
tso
Data Input Setup
tSR
tws
Conditions
Vcc=5.0V
Vcc=10V
Vcc- 5.OV
I
Vcc=10V
Vcc-5.OV, tws- O
Vcc'= 10V, tws = 0
vcc -' :>.Ov
Vcc=10V
Vcc- 5•OV
Vcc=10V
Vcc-5.OV, CL-5.0pF, RL-10k
Vcc= 10V, CL=5.0pF, RL=10k
Min
0
0
Typ
Max
tME
tME
300
100
50
25
' 50
25
160
60
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
i ns
ns
Propagation Oelay from a Logical
180
300
"1" or logical "0" to the High
-85
120
Impedance State from
Memory Enable
. Propagation Delay from a Logical
180
300
Vcc-5.OV, CL-5.0pF, RL=10k
ns
t'H, tOH,
"1" or Logical "0" to the High
Vcc=10V, CL=5.0pF, RL=10k
85
120
ns
Impedance State from
Write Enable
C1N
Input Capacity
Any Input (Note 2)
5.0
pF
output {Japaclty
Any Output (Note 2)
6.5
pF
{JOUT
Power Dissipation Capacity
(Note 3)
230
pF
Cpo
Nole 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Range" they are not meant to Imply that the devices should be operated at these limits. The table of "Electrical Charac··
terlstlcs" provides conditions for actual device operation.
Nole 2: Capacitance Is guaranteed by periodic testing.
Nole 3: CPO determines the no load AC power consumption of any CMPS device. For complete explanation see 54C/74C Family Char·
. acterlstics application note, AN-90.
t'H, tOH,
AC Electrical Characteristics (Guaranteed across the specified temperature range, CL = 50 pF)
Parameter
MM54C89
TA=55"Cto +125"C
Conditions
Min
Max
MM74C89
TA = -45°C to +85"C
. Min
Units
Max.
tpo
Vcc = 5.0V
Vcc=10V
Vcc=15V
700
310
250 .
600
265
210
ns
ns
ns
tACC
Vc c=5.0V
Vcc=10V
Vcc=15V
910
400
320
780
345
270
ns
ns
ns
tSA
Vcc= 5.0V
Vcc=10V
Vcc=15V
210
90
70
180·
80
60
ns
ns
ns
tHA
Vc e=5.0V
Vce=10V
Vee=15V
80
55
45
70
50
40
ns
ns
ns
tME
Vee=5.0V
Vce=10V
Vce=15V
560
210
170
480
180
150
ns
ns
ns
tME
Vee=5.0V
Vce=10V
Vee.=15V
560
.210
110
480
180
150
hs
ns
ns
tWE
Vee=5.0V
Vee=10V
Vee=15V
420
140
110
360
120
100
ns
ns
ns
tHO
Vce=5.0V
Vce=10V
Vce=15V
70
35
30
60
30
25
ns
ns
ns
tSA
Vce=5.0V
Vce=10V
Vee=15V
70
35
30
80
30
25
ns
ns
ns
t'H, tOH,
\
420
170
135
Vee = 5.0V
Vee = 10V, CL = 5.0pF
'Vce=15V, RL=10kQ
6-46
380
145
115
ns
ns
ns
Truth Table
ME
WE
L
L
L
H
H
OPERATION
CONDITION OF OUTPUTS
Write
TRI-STATE
H
Read
Complement of Selected Word
L
H
InhIbit, Storage
TRI STATE
Inhibit. Storage!
TRI-STATE
AC Test Circuits
tOH
TLlF/5S8a·3
TLlFIS8B8·4
Switching Time Waveforms
tOH
v~
,v __ /m"
=:j '" f---
TLIF/58BB·S
TLIFI5BB86
Read Cycle
Write Cycle
ENA.BTI
""""'"
ADDRESS
ADDRESS
INPUT
MEMORY
V~----~-r--------'
ENABLE
v" _________.........
INPUT
V,, _ _ _ _ _ _
~
w~rn
[MAiLE
..,..OUT
\ C c t - - - - - - - - -.
-- ----- -- ---+,----
CONDITION ____
, _ _ _ _ _ _TRISTATE
"'c__.'-'-,cc
V,, _______________,
DATA
INPUf
~
TliF/58SS·S
Tl!FI58BB·7
Read Modify Write Cycle
...... V",---t7""------,
ENABLE
V,, _ _ _ _---.
ADDRESS
INPUT
.-----'
-==:l
tpd
ce
mAliUf v - - - - -
--TAISTAT~COND:::: _
,-------------
,....!RI STATE CONDITION
•
J. ----.-,--
E~~~,-----:-yHL""
,.
DATA
NOTE: .. ·60115
lj"ltJns
TLIF/S6BS·9
6-47
~ ~National
~ Semiconductor
:::&
~ MM54C9OIMM74C90 4-Bit Decade Counter
~ MM54C931MM74C93 4-Bit Binary Counter
~
General Description
i
The MM54C90/MM74C90 decade counter and the
MM54C931MM74C93 binary counter and complementary
MOS (CMOS) Integrated circuits constriJcted with N and
P-channel enhancement mode transistors. The 4-blt·
decade counter 'can reset to zero or preset to nine by
applying appropriate logic level on the Ro1, Roz, R91 and
R9Z inputs. Also, a separate flip-flop on the A-bit enables
the user to operate it as a dlvide-by-2, 5 or 10 frequency
counter. The 4-bit binary counter can be reset to zero by
applying high logic level on inputs R01 and Roz, and a
separate flip-flop on the A-bit enables the user to operate it as a divide-by-2, -8, or -16 divider. Counting
occurs on the negative going edge of the Input pulse.
g
;::.
:::&
:IE
-
i
~
...
:::&
:::&
All Inputs are protected against static discharge damage.
Features
3Vto 15V
- Wide supply voltage range
_ Guaranteed noise margin
1V
0.45 Vcc (typ.)
- High noise immunity
fan out of 2
,driving 74L
- Low power
TTL compatibility
- The MM54C93/MM74C93 follows the
MM54L93/MM74L93 Pinout
Logic and Connection Diagrams
MM54C90/MM74C90
Dual·ln·Line Package
A,"
I"
MM54C90/MM74C90
~
a,
ao
Ne
"
12
"
"
,
.,
-
-
"
B,"
2
R"
,
R"
4
,
Ne
I'
6
R"
R"
TOP VIEW
TLfF/5889.2
Order Number MM54C90J or MM74C90J
See NS Package J14A
Order Number MM54C90N or MM74C90N
See NS Package N14A
MM54C93/MM74C93
Dual-ln',Line Package
A'N
I"
MM54C93/MM74C93
a.
A.
ao
eLK
Q
....
~
TlIFI58B9·3
"
12
a,
GNa
"
10
B,.
,
B
-
r-
1
R~
ao
a,
2
,
Ne
4
v~
rDPVIEW
,
Ne
6
Ne
I'
Ne
TLIFIS889-4
Order Number MM54C93J or MM74C93J
See NS Package J14A .
Order Number MM54C93N or MM74C93N
See NS Package N14A
6-48
Absolute Maximum Ratings
Voltage at Any Pin (Note 1)
Operating Temperature Range
MM54C90, MM54C93
MM74C90, MM74C93
Package Dissipation
-55'Cto +125'C
-40'Cto +S5'C
500mW
DC Electrical Characteristics
Symbol
I
Operating Vcc Range :
3V to 15V
Absolute Maximum Vcc
1SV
Storage Temperature Range
-65'C to +150'C
Lead Temperature (Soldering, 10 seconds)
300'C
-0.3V to Vcc + 0.3V
Parameter
CMOS to CMOS
Minimax limits apply across temperature range unless otherwise noted
I
Conditions
VIN(1)
Logical "1" Input Voltage
Vc c=5.0V
Vcc=10V
VIN(O)
Logical "0" Input Voltage
Vcc- 5.OV
Vcc=10V
VOUT(1)
Logical "1" Output Voltage
Vcc= 5.0V, 10= -101'A
VcC =10V, 10= -101'A
VOUT(O)
Logical "0" Output Voltage
IIN(1)
Logical "1" Input Current
Vcc=5.0V, 10= +1OI'A
Vcc =10V, 10= +1OI'A
Vcc -15V, VIN -15V
IIN(O)
Logical "0" Input Current
Vcc=15V, V1N=OV
Icc
Supply Current
Vcc=15V
I
Min
I
Typ
I
Max
3.5
S
V
V
1.5
2
V
V
V
V
0.5
1
V
V
1
I'A
300
I'A
4.5
9
0.005
-1
I Units
-0.005
0.05
I'A
CMOS/LPTTL Interface
VIN(1)
VIN(O)
VOUT(1)
VOUT(O)
Logical "1" Input Voltage
MM54C90, MM54C93
MM74C90, MM74C93
Vcc=4.5V
Vcc =4.75V
Logical "0" Input Voltage
MM54C90, MM54C93
MM74C90, MM74C93
Vcc=4.5V
Vcc=4.75V
Logical "1" Output Voltage
MM54C90, MM54C93
MM74C90, MM74C93
Vcc=4.5V, 10= -3601'A
Vcc=4.75V, 10= -36OI'A
Logical "0" Output Voltage
MM54C90, MM54C93
MM74C90, MM74C93
Vcc=4.5V, 10 = 360l'A
VcC=4.75V, 10 = 360l'A
V
V
Vc c- 1.5
Vcc- 1.5
O.S
O.S
2.4
2.4
V
V
V
V
0.4
0.4
V
V
Output Drive (See 54C/74C Family Characteristics Data Sheet) (short Circuit current)
ISOURCE
Output Source Current
(P·Channel)
ISOURCE
Output Source Current
(P·Channel)
Output Sink Current
(N-Channel)
ISINK
ISINK
Output Sink Current
(N-Channel)
AC Electrical Characteristics
Symbol
tpdO, tpd1
tpdO, tpd1
tpdO, tpd1
Parameter
Propagation Delay Time from
AIN to OA
Propagation Delay Time from
AjN to Os (MM54C93/MM74C93)
Propagation Delay Time from
AIN to Os (MM54C90/MM74C90)
Vcc=5.0V, VOUT=OV
TA =25'C
Vcc=10V, VOUT=OV
TA=25'C
Vcc - 5.0V, VOUT - Vee
TA =25'C
Vec = 10V, VOUT = Vec
TA =25'C
-1.75
-3.3
mA
-S
-15
mA
1.75
3.6
mA
S
16
. mA
TA = 25'C, CL = 50 pF, unless otherwise specified.
Typ
Max
Vee=5.0V
Vee=10V
200
SO
400
150
ns
ns
Vce=5.0V
Vee=10V
Vec -5.0V
Vee=10V
450
160
S50
300
SOO
300
ns
ns
Conditions
6-49
Min
450
160
Units
ns
ns
AC Electrical Characteristics (Cont'd.) TA = 25'C, CL = 50 pF, unless' otherwise specified.
Typ
Max
Units
tpdO, tpd1
Propagation Delay Time from
.6.IN to Oc (MM54C93/MM74C93)
Vcc=5.0V
Vcc=10V
500
200
1050
400
ns
ns
tpdO, tpd1
Propagation Delay Time from
AIN to Oc (MM54C90/MM74C90)
Vcc- 5.OV
Vcc=10V
500
200
1000
400
ns
ns
~N
Propagation Delay Time from
to 0 0 (MM54C93/MM74C93)
Vcc=5.0V
Vcc=10V
600
250
1200
500
ns
ns
tpdO, tpd1
Propagation Delay Time from
AIN to 0 0 (MM54C90/MM74C90)
Vcc=5.0V
Vcc=10V
450
160
800
300
ns
ns
tpdO, tpdl '
Propagation Delay Time from
R01 or R02 to OA. OB, Oc or 0 0
(M M54C93/MM74C93)
Vcc- 5.OV
Vcc=10V
150
75
300
150
ns
ns
tpdO, tpdl
Propagation Delay Time from
Rot or R02 to OA, Os, Oc or 00
(MM54C90IMM74C90)
Vcc- 5.OV
Vcc=10V
200
75
400·
150
ns
ns
tpdO, tpdt
Propagation Delay Time from
Rgt or R92 to OA or 0 0
(M M54C90/M M74C90)
Vc c=5.0V
Vcc=10V
250
100
500
200
ns
ns
tpw
Min. R01 or R02 Pulse Width
(MM54C93/MM74C93)
Vcc=5.0V
Vcc=10V
600
300
250
125
ns
ns
tpw
Min. Rot or R02 Pulse Width
(M M54C90/MM74C90)
Vcc=5.0V
Vcc=10V
600
300
250
125
ns
ns
tpw
Min. Rgt or Rg2 Pulse Width
(MM54C90/MM74C90)
Vcc=5.0V
Vcc=10V
500
250
200
100
ns
ns
tr,tf
Maximum Clock Rise and
Fall Time
Vcc=10V
Vcc=10V
tw
Minimum Clock Pulse Width
Vcc- 5 .O V
Vcc=10V
250
100
f MAX
Maximum Clock Frequency
Vcc=5.0V
Vcc=10V
2
5
CIN
Input Capacitance
Any Input (Note 2)
Cpo
Power Dissipation Capacitance
Per Package (Note 3)
Symbol
Parameter
tpdO, tpdt
Condillons
Min
,
15
5
",s
,..s
100
50
ns
ns
MHz
MHz
5
pF
45
pF
Nole 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Nole 2: Capacitance is guaranteed by periodic testing.
Nole 3: Cpo determines the no load ac power consumption of any CMOS device. For complete explanation see 54C/74C Family Charac·
teristics application note - AN-gO.
AC Test Circuits
MM54C90/MM74C90
MM54C93/MM74C93
vr'
vr,
CLOCK
f
JLo-
R"
•
D.
R~
-L..~'F
R"
T
lie
R~
-L~'F -=-
D,
--L- SOpF
A"
D,t----
R"
D,
R~
lie
~~'F
..
...l...SOPF
--L- SOPf
A"
D'j:L,
11
-
.t.
T
SOpF
T":'
T
":'
CIDckr",.n,f,lIllmll,=lt=2Dns
1,:tt"20ns
TL./FI5889-6
TL/F/5889-5
6·50
SWitching Time Waveforms
,
r-,"1
____ ...I
'--------------
NDle 1: MM54C!lD, MM74C9D .nd MMS4C!ll. MM74C!l3
lie lolld hne waveforms. Dashed hne WlVlforms ~re lor
MM54C901MM74C9D only,
TLIFIS8S9·7
Truth Tables
MM54C90/MM74C90 4·Bit Decade Counter
MM54C93/MM74C93 4·Bit Binary Countar
BCD Count Sequence
COUNT
00
OUTPUT
Oc OB
Binary 'Count Sequence
COUNT
OA
00
OUTPUT
Qc °B
QA
0
L
L
L
L
0
L
L
L
L
1
2
3
4
L
L
L
L
L
L
H
1
H
L
2
L
L
L
H
L
L
H
L
H
H
3
l.
L
H
H
L
L
L
4
L
L
H
L
L
H
H
L
H
L
L
5
H
H
H
L
5
6
L
H
H
L
L
H
H
H
H
H
7
L
H
H
H
L
L
L
L
L
H
8
9
H
L
L
L
L
L
H
10
H
L
H
L
L
H'
11
'H
12
H
H
L
L
13
H
H
L
H·
14
H
H
H
L
15
H
H
H
H
6
7
8
9
Output OA
IS
H
L
L
connected 10
Input
B for
BCD count.
H = High
lev~1
L = Low level
X = Irrelevant
H
H
Output QA
IS connected to Input B for
brnary count seQuence
Reset/Count Function Table
H" High level
RESET INPUTS
L = Low level
OUTPUT
RD. RD2 Re. R92
H
H
H
H
L
X
X
X
X
H
X
L
H
L
X
L
L
L
X
L
X,
X
X
L
X
L
L
X
QO
L
L
H
X= Irrelevant
Oc °B QA
L
L
L
L
L
L
Reset/Count Function Table
L
L
RESET INPUTS
RD.
RD2
H
COUNT
COUNT
COUNT
COUNT
6·51
H
H
L
X
X
L
QO
L
OUTPUT
QC OB
L
L
COUNT
COUNT
OA
L
~.------------------------------------------------------------------,
~ ~National
:E
:E
~
~
:E
:E
~ Semiconductor
MM54C951MM.14C954-Bit Right-Shift Left-Shift Register
General Description
Features
This 4-blt shift register is a monolithic complementary
MOS (CMOS) integrated circuit composed of four 0 flip
flops. This register will perform right-shift or left-shift
operations dependent upon the logical input level to the
mode control. A number of these registers may be connected In series to form an N-bit right-shift or left-shift
register.
• Medium speed operation
When a logical "0" level is applied to the mode control
Input, the output of each flip flop Is coupled to the 0 input of the succeeding flip flop. Right-shift operation is
performed by clocking at the clock 1 Input, and serial
data entered at the serial input, clock 2 and parallel
Inputs A through 0 are inhibited. With a logical "1" level
applied to the mode control, outputs to succeeding
stages are decoupled and parallel loading Is possible,
or with external interconnection, shift-left operation can
be accomplished by connecting the output of each flip
flop to the parallel input of the previous flip flop and
serial data is entered at input D.
•
•
•
•
10MHz(typ.)
Vee = 10V, CL =50pF
0.45 Vee (typ.)
100nWI (typ.)
Drive 2 LTIL loads
3Vto 15V
• High noise Immunity
• Lowpower
• Tenth power TIL compatible
Ii Wide supply voltage range
Synchronous parallel load
Parallel inputs and outputs from, each flip flop
Negative edge triggered clocking
The MM54C95/MM74C95 follows the
MM54L95/MM74L95 Pinout.
Applications
Data terminals
• Instrumentation
• Automotive
• Medical electronics
•
Ii Alarm systems
• Remote metering
•
Industrial electronics
• Computers
Block and Connection Diagrams
SEAIAl ""'"'. . .--:<_--'.
CLOCK 2
lSHIFT..--,rL"'--,
INPUT
~Mc
_
MDDECONTRDl~MC
Cl'OeK1
A-SIIIFT
IN.UTI OUTPUT I
IN'UTC
OUTPUle
11II'U10 OUTPUTD
Modecontrol"'Oforrillhtshiit
Modeconlrol=1forleftshiftorparillelload
o!!-CNO
TLlFI589()'2
TlIFI5890·1
TUF/5890-3
Dual-In-Line Package
Function Table
INPUTS
MODE
CONTROL
CLOCKS
2 ILl
1 (RI
SERIAL r:---,::,PA::.:AA:::L:o:LE:::L--,::--i
a,
Oc
aD
aAO
a"
a"
ODD
h
,H
OUTPUT
A
A
SERIAL
IIII,Ut
,UU1
I
OU1'I'ut
C
OUTPUT
I.
OUT'UT
II
CLOCl.t
L.sHlft
OUTPUTS
aA
a,"
a.o
L'
INPUT
H
L
a.,
aAO
a.D
aAO
aAO
d
Oe"
a"
6A"
a."
a..
a"
a"
a"
a"
Oon
a"
a,"
a,"
OeD
a"
a"
a"
a"
aDO
a,"
"'aDOaDO"
aDO
0,,0
aDO
IN'Ut
C
V~"
TO'YIEW
IlWut
II
MODl
ClOtlll
CONTAOllI$1tIFT
TLlFI5890-4
Undefmed
OpeutmgCood,tlons
'Shoftlngleh reqo,resexternal connect.on of De to A. Cle 10 e. ~nd aD 10 C Se",,1 dala os entered ilt,nput 0
H-h.ghlevel (steadystatel.L-lowlevel (steadystateI,X-,rrelevanl (any Input.lrlcludmg tra'lSlt,onsl
I -trilnSltlon from h,gtI to low level. , "transltlonfromlowtoh,glilevel
I. b. c. d .. the level oillteady-Uale mput at InPots A. e. C or D. respectively
0AO. 0BO. Oco. DOO - the ~el of DA. CIa. Cle. or 00. respe<:tlvelv. before the ,nd,cated neady·nale 'npul conditions were estlbhshed
DAn. 0Bn. DCn. Dan" the level of DA. DB. Cle.or Da. respectIvely. before the molt-recent Itr8n$ll.on of the clock
6-52
Order Number MM54C95J or
MM74C95J
See NS Package J14A
Order Number MM54C95N or
MM74C95N'
See NS Package N14A
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
MM54C95
MM74C95
Storage Temperature
(Note 1)
-0.3 V to Vee+0.3 V
-55'C to +125'C
-40'C to +B5'C
-65'C to +150'C
DC Electrical Characteristics
Sym
I
Minimax limits apply across temperature range unless otherwise noted
I
Parameter
CMOS to CMOS
'.
Conditions
I
Min
Vee =5.0V
Vee=10V
Vee -5.0V
Vee=10V
3.5
B.O
Logical "1" Output Voltage
Vee=5.0V
Vee = 10V
4.5
9
VOUT(O)
Logical "0" Output Voltage
IIN(l)
Logical "1" Input Current
Vee=5.0V
Vee=10V
Vee=15V
IIN(O)
Logical "0" Input Current
Vee=15V
Icc
Supply Current
Vee- 15V
VIN(l)
Logical "1" Input Voltage
VIN(O)
Logical "0" Input Voltage
VOUT(l)
1BV
500mW
+3Vto+15V
300'C
Maximum Vee Voltage
Package Dissipation
Operating Vee Range
Lead Temperature (Soldering, 10 sec.)
I
I
Typ
Max
I
Units
V
V
V
V
0.5
1
V
V
1
"A
-1
"A
0.050
300
"A
Low Power TTL/CMOS Interlace
VIN(l)
Logical "1" Input Voltage
VIN(O)
Logical "0" Input Voltage
VOUT(l)
Logical "1" Output Voltage
VOUT(O)
Logical "0" OiJtput Voltage
54C,
74C,
54C,
74C,
54C,
74C,
54C,
74C,
,
Vee = 4.5 V
Vee=4.75V
Vec = 4.5 V
Vee=4.75V
Vec = 4.5 V,
Vec=4.75V,
Vee - 4.5 V,
Vcc = 4.75V,
Vce -1.5
Vee -1.5
O.B
O.B
10 = 360 "A
10 = 360 "A
10-360"A
10 = 360 "A
2.4
2.4
0.4
0.4
V
V
V
V
V
V
V
V
Output Drive (See 54C/74C Family Characteristics Data Sheet)
Vee = 5.0 V, VIN(O) = 0 V
TA=25'C, VOUT=OV
Vee=10V, VIN(O)=OV
TA =25'C, VOUT=OV
Vee = 5.0V, VIN(l) = 5.0V
TA == 25'C, VOUT = Vee
Vec=10V, VIN (1)=10V
TA = 25'C, VOUT = Vee
IsouReE Output Source Current
IsouReE Output Source Current
ISINK
Output Sink Current
ISINK
Output Sink Current
AC Electrical Characteristics
Sym
-1.75
mA
-B.O
mA
1.75
mA
B.O
mA
TA = 25'C, CL = 50 pF, unless otherwise noted.
Parameter
Conditions
Min
Typ
Max
Units
200
BO
400
160
ns
ns
tpd
Propagation Delay Time to a Logical
"0" or Logical '!1" from Clock to Q or Q
Vee =5.0V
Vee=10V
tso, tSl
Time Prior to Clock Pulse that Data
must be Preset
Ve e =5.0V
Vee=10V
60
25
30
10
ns
ns
tHO, tHl
Time After Clock Pulse that Data must
be Held
Vee=5.0V
Vce=10V
25
10
10
50
ns
ns
tpw
Minimum Clock Pulse Width (tWL=tWH)
Vee =5.0V
Vee=10V
100
50
J
ns
ns
tSM
Time Prior to Clock Pulse that Mode
Control must be Preset
Vce=5.0V
Vce=10V
200
100
100
50
ns
ns
f MAX
Maximum Input Clock Frequency
3
6.5
5
10
MHz
MHz
CIN
Cpo
Input Capacitance
Vee=5.0V
Vee=10V
Any Input. (Note 2)
Power Dissipation Capacitance
(Note 3)
Note 1: "Absolute MaxImum Ratings" ate those values beyond whiCh. the safety 01 the device cannol be guaranteed. Except for
"Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits. The table of "Electncal
Characteristics" provides conditions for actual device operation.
Note 2: Capacttance is guaranteed by periodiC testmg.
Note 3: Cpo determines the no load AC power consumption of any CMOS device. For complete explanation see 54C174C Family
Characteristics application note AN-gO.
6·53
~
oCD
CI1
V
V
1.5
2.0
s:
s:
~
fJCI1
s:
s:
5
pF
100
pF
en
'9"'"
~::t ~National
~ Semiconductor
::t
a;
'9"'"
oN
~ MM54C150/MM74C150 16-Line to 1·Line Multiplexer
~ MM72C19/MM82C19 TRI·STATE® 16-Line to 1·Line '
!
~
Multiplexer
~
General Description
-
The MM54C150/MM74C150 and MM72C19/MM82C19
multiplex 16 digital lines to 1 output. A 4·blt address
code determines the particular 1-of-16 Inputs which Is
routed to the output. The data Is Inverted from Input to
output.
~
'9"'"
~
SE
::t
All Inputs are protected from damage due to static
'discharge by diode clamps to Vee and GND.
,Features
• Wide supply voltage range
'. Guaranteed noise margin
• High noise Immunity
A strobe override places the output of MM54C1501
MM74C150 in the logical "1" state and the output of
MM72C19/MM82C19 in the high-Impedance state.
• TTL compatibility
Connection Diagram
Dual·ln-Line Pllckage
DATA INPUTS
VCC • E8
124
E9
23
EIO
22
21
Ell
20
EI2
DATA SELECT
EI3
19
18
EI4
17
EI5
\
16
i
A
15
14
10
11 .112
13
.-
E7
E5
E4
E3
E2
EI
EO STB OUTPUT D GND
'....- - - - - - .•. _ - - - - - '
DATA
DATA INPUTS
SELECT
TL.IFI5891·1
Order Number MM54C15OJ, MM74C150J, MM72C19J
orMMB2C19J
See NS Package J24A
Order Number MM54C150N, MM74C150N, MM72C19N
orMM82C19N
See NS Package N24A
6·54
3.0Vto 15V
1.0V
0.45 Vee (typ.)
Drive 1 TTL Load
/ Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
MM54C150, MM72C19
MM74C150, MM82C19
Storage Temperature Range
(Note 1)
Package Dissipation
Operating Vee Range
Vee
Lead Temperature (Soldering, 10 sec.)
-0.3 V to Vee+0.3 V
-55·C to +125·C
-40·C to +85·C
-65·C to +150·C
500mW
3.0Vto 15V
18V
300·C
~
DC Electrical Characteristics
Symbol
Minimax limits apply across temperature range unless otherwise noted
Parameter
Conditions
Min
Typ
Max
Units
CMOS to CMOS
V1N (1)
Logical "1" Input Voltage
Vee =5.0V
Vee=10V
VIN(O)
Logical "0" Input Voltage
Vee -5.0V
Vee=10V
VOUT(l)
Logical "1" Output Voltage
Vee =5.0V,lo=-1OflA
Vee =10V, 10=-1OflA
VOUT(O)
Logical "0" Output Voltage
Vee =5.0V, 10 =+1O"A
Vee =10V, '0=+1OflA
IIN(l)
Logical "1" Input Current
Vee = 15V, VIN = 15V
IIN(O)'
Logical "0" Input Current
Vee=15V, V1N=OV
-1.0
-0.005
loz
Output Current in High
Impedance State
MM72C19JMM82C19
Vee = 15V, Vo=15V
Vee 15V, Vo=O~
0.005
-0.005
1.0
-1.0
flA
flA
0.05
300
flA
Icc
Supply Current
3.5
8.0
V
V
1.5
2.0
=
4.5
9.0
V
V
0.5
1.0
0.005
Vee=15V
V
V
1.0
V
V
flA
flA
TTL Interface
V1N (1)
Logical "1" Input Voltage
54C,72C
74C,82C
Vee=4.5V
Vee =4.75V
VIN(O)
Logical "0" Input Voltage
54C,72C
74C,82C
Vee=4.5V
Vee =4.75V
VOUT(l)
logical "1" Output Voltage
54C, 72C . Vee = 4.5 V, lo=-1.6mA
74C,82C VeC=4.75V,l o =-1.6mA
VOUT(O)
Logical "0" Output Voltage
54C,72C
74C,82C
V
V
Vee -1.5
Vee -1.5
0.8
0.8
V
V
V
V
2.4
2.4
0.4
0.4
Vee=4.5V, lo=1.6mA
Vee=4.75V,lo=1.6mA
V
V
Output Drive (Short Circuit Current)
IsouReE
Output Source Current
(P-Channel)
Vee=5.0V, VOUT=OV, TA =25·C
-4.35
-8
mA
IsouReE
Output Source Current
(P-Channel)
Vce =10V, VOUT=OV, TA =25·C
-20
-40
mA
ISINK
Output Sink Current
(N·Channel)
Vee = 5.0 V, VOI)T = Vee, TA = 25·C
4.35
8
mA
ISINK
Output Sink Current
(N-Channel)
Vee = 10 V, VOUT = Vee, TA = 25·C
20
.40
mA
6-55
AC ,Electrical Characteristics
Symbol
TA = 25 D C, CL = 50 pF, unless otherwise noted.
Parameter
Conditions
Min
Typ
Max,
Units
tpdO, tpdt Propagation Delay Time to a
Logical "0" or Logical "1",
from Data Inputs to Output
Vee =5.0V
Vee = 10V
Vee = 5.0 V, CL = 150 pF
Vee =10V, CL=150pF
250
110
290
120
600
300
650
330
ns
ns
ns
ns
tpdO, tpdt Propagation Delay Time to a
Logical "0" or Logical "1"
from Data Select Inputs to
Output
Vee=5.0V
Vee=10V
290
120
650
330
ns
ns
tpdo, tpdt Propagation Delay Time to a
Logical "0" or Logical "1"
from Strobe to Output
MM54C150/MM74C150
Vee =5.0V
Vee=10V
120
55
300
150
ns
ns
ttH, tOH
Delay from Strobe to High
Impedance State
MM72C19/MM82C19
Vee=5.0V, RL =10k, CL=5pF
Vee =10V, RL =10k, CL=5pF
80
60
200
150
ns
ns
tH1 , tHO
Delay from Strobe to Logical
"1" Level or to Logical "0"
Level (from High Impedance
State)
MM72C19/MM82C19
Vec=5.0V, RL =10k, CL =5pF
Vee =10V, 'RL=10k, CL=5pF
80
30
250
120
ns
ns
CIN
Input Capacitance
COUT
Output Capacitance
MM72C19/MM82C19
Cpo
Power Dissipation
Capacitance
5.0
pF
' (Note 2)
Any Input, (Note 2)
11.0
pF
(Note 3)
100
pF,
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range': ihey are not meant to imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Cpo determines the no load AC power consumption of any CMOS device. For complete explanation see'54C/74C Family
Characteristics application note AN-90.
"
\
I
6·56
Truth Table
MM54C150/MM74Cl50
INPUTS·
OUTPUT
0
C
B
A
STROBE
'0
E1
E2
E3
'4
E5
,.
E7
EB
'9
E10
E12
E13
E14
E15
X
x
x
'"
X
I
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
x
x
X
1
X
x
x
x
x
x
x
x
I
x
x
x
0
x
x
x
0
x
x
x
0
x
x
x
0
x
,x
x
0
x
x
x
x
0
0
0
0
1
0
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
0
0
I
0
X
'1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
1
0
0
0
0
1
0
0
x
x
0
0
I
1
0
X
1
0
0
I
1
0
X
X
X
1
X
X
X
X
X
X'
X
X
X
X
X
X
0
0
1
0
0
0
x
x
x
x
x
x
x
x
x
x
X
1
0
0
0
x
x
0
1
x
x
x
0
x
x
X
1
X
X
X
X
X
X
X
X
X
X
X
0
0
1
0
1
0
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
1
0
1
0
I
0
X
X
X
X
X
I
X
X
X
X
X
X
X
X
X
X
0
0
1
I
0
0
x
x
x
x
x
x
x
X
1
(")
0
x
x
x
0
x
x
0
I
x
x
x
I
x
x
x
0
1
X
X
X
X
X
X
0
0
I
1
1
0
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
1
0
1
1
1
0
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
0
x
x
x
x
x
x
x
0
x
x
x
x
x
x
X
1
X
1
X
X
X
X
X
X
X
0
-s:
s:
X
W
x
0
x
x
x
x
x
x
x
x
x
x
x
x
X
1
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
0
x
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
0
0
0'."
1
0
0
0
0
x
x
x
x
x
x
x
x
1
0
0
1
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
1
1
0
0
1
0
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
0
1
0
1
0
0
x
x
x
X
1
x
x
x
x
x
x
x
x
x
0
x
x
0
0
x
x
x
1
x
x
x
0
x
x
x
1
X
1
X
X
X
X
X
0
I
0
I
1
0
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
1
1
0
I
1
0
X
X
X
X
X
X
X
X
1
X
X
X
0
1
1
0
0
0
x
x
x
x
x
x
X'
X
X
X
X
X
0
X
X
X
1
1
1
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
0
1
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
1
1
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
0
X
X
X
X
1
1
1
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
1
I
1
1
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
0
1
1
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
I
1
1
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
I
0
1
~
I'
1
.
s:
s:
~
....(")C1'I
9
s:
s:
~
....
CD
00
N
....o
CD
For MM72C19/MM82C19 thIS would be HI-Z. everything else IS the same,
Switching Time Waveforms
CMOS to CMOS
vcc--=I~Ir;;,;-,------:,;,;,'""lI
,V __--";;,;,J
',1
Vcc-----,
50%
. VOUl
'V ______________\ ______________--J
vee
DISABLE
INPUT
DISABLE
\ 0 , 5V CC
OISABLE
---Q---1I-=~,Ok-l"- c
OV---=I.~
OUTPUT
JL
Vcc-----;
0.1 Vee
OUTI'UT
ov _ _ _ _ _--=",...__
TlIF15891·3
"'' :'--=-:&
0.5
=Sd="
Vcc
OISABLE
tHO
Vcc-----r-------0.5 Vee
DISABLE
DISABLE
vcc=t
ov:vcc
OV
OUTPUT
* " cL
Vee
--j-
OV
INPUT
s:
s:
i!
o....
'H'
Vee
OUTPUT
--------..--j---'--
OUTPUT
TLlF15891·4
Note: Delays measured with input t r . tf ~ 20 ns.
OV
0.1 Vee
6-57
-------_,~
_ __
TLlF/5691·5
~~----------~--------------~--------------~
o
&:I
MM54C150/MM74C150
Logic Diagrams
:E
:E
.,..
0)
o
C\I
.....
:E
:E
o
.,..
o
t!
Lt)
:E
:E
~
.,..
~:E
:E
m-j»o-t+1+--H±-l--i-STROBE
--I>o-f-H+--+++l=---------.-J
TLlFI5891·6
MM72C19/MM82C19
EO~~
E1-t»-ffi
E15
STROBE
-[>O-++I+--H-1--1--i--
--I>o-f-H+--+++l=---------.-J
6-58
~------------------------~--------~------I~
~
~National
.~ Semiconductor
~....
....
Ut
i:
i:
MM54C151/MM74C151 8-Channel Digital Multiplexer
General Description
~....
Features
The MM54C151/MM74C151 multiplexer is a monolithic - Supply voltage range
complementary MOS (CMOS) Integrated circuit con- , _ Tenth power TTL compatible
structed with N- and P-channel enhancement transistors. _ High noise immunity
This data selector/multiplexer contains on-chip binary
decoding. Two outputs provide true (output Y) and complement (output W) data. A logical "1" on the strobe input
forces W to a logical "1" and Y to a logical "0".
All inputs are protected against electrostatic effects.
3Vto 15V
drive 2 LPTTL loads
0.45 Vee (typ.)
50nW (typ.)
- Lowpower
Applications
-
Automotive
Data terminals
Instrumentation
Medical electronics
- Alarm systems
- Industrial electronics
- Remote metering
- Computers
logic and Connection Diagrams
D,
DATA
INPUTS
OUTPUT ,WI
D.
D.
D.
D,
~r
UROIE
TLIFI5B92·'
Dual-In-Line Package
Order Number MM54C151J or
MM74C151J
See NS Package J16A
D,
Order Number MM54C151N or
MM74C151N
See NS Package N16E
TO. VIEW
TLlF15B92·2
6-59
....
Ut
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
MM54C151
MM74C151
Storage Temperature Range
(Note 1)
-55·C to +125·C
-40·C to +85·C
-65·C to +150·C
DC Electrical Characteristics
Symbol
18V
500mW
3Vto 15V
300·C
Maximum Vcc Voltage
Package Dissipation
Operating Vcc Range
Lead Temperature (Soldering, 10 sec.)
-0.3 V to Vcc+0.3 V
MinImax limits apply across temperature range unless otherwise noted
Parameter
Conditions
Min
Typ
Max
Units
CMOS to CMOS
3.5
8
VIN(1)
Logical "1" Input Voltage
Vcc =5.0V
Vcc=10V
VIN(O)
Logical "0" Input Voltage
Vcc·=5.0V
Vcc=10V
VOUT(1)
Logical "1" Output Voltage
Vcc = 5.0 V, 10=-1O)JA
Vcc = 10V, 10 = -10)JA
VOUT(O)
Logical "0" Output Voltage
Vcc =5.0V,l o =+10)JA
Vcc=10V, 10=+10)JA
IIN(1)
Logical "1" hiput Current
Vcc=15V, VIN =15V
IIN(O)
Logical "0" Input Current
Vcc -15V, VIN-OV
Icc
Supply Current
Vcc=15V
V
V
1.5
2
V
V
4.5
9.0
V
V
0.5
1.0
1.0
-1.0
VIN(1)
Logical "1" Input Voltage
54C
74C
Vcc =4.5V
Vcc =4.75V
VIN(O)
Logical "0" Input Voltage
54C
74C
Vcc=4.5V
Vcc =4.75V
VOUT(1)
Logical "1" Output Voltage
54C
74C
Vcc -4.5V, 10--36O flA
Vcc = 4.75 V, 10 = -360 flA
VOUT(O)
Logical "0" Output Voltage
54C
74C
Vcc =4.5V, 10 = 360flA
VCC=4.75V, 10 = 360flA
Vcc- 1.5
Vcc -1.5
)JA
)JA
0.05
CMOS to LPTIL Interface
V
V
300
"
)JA
V
mA
0.8
. 0.8
V
V
2.4
2.4
V
V
0.4
0.4
V
V
.
Output Drive (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
.
ISOURCE
Output Source Current
Vcc=5.0V, VIN(O)=OV
TA = 25·C, VOUT = 0 V
ISOURCE
Output Source Current
Vcc =10V, VIN(O)=OV
TA = 25'C, VOUT = 0 V
ISINK
Output Sink Current
Vcc = 5.0V, VIN(1) = 5.0V
TA = 25·C, Your = Vee
1.75
mA
ISINK
Output Sink Current
Vee = 10 V, VIN (1) = 10 V
TA = 25·C, VOUT = Vee
8.0
mA
-1.75
mA
-8.0
mAO
,
i
-.
6·60
AC Electrical Characteristics
Symbol
TA = 25°C, CL = 50pF, unless otherwise noted.
Parameter
Conditions
Typ
Max
Units
lpdO,.tpdl
Propagation Delay Time to a
Logical "0" or Logical "1" from
Data to Y
Vcc=5.0V,
Vcc=10V
Min
170
80
270
130
ns
ns
tpdO, tpdl
Propagation Delay Time to a
Logical "0" or Logical "1" from
Data to W
Vee = 5.0 V,
Vcc=10V
200
90
300
140
ns
ns
tpdO, tpdl
Propagation Delay Time to a
Logical "0" or Logical "1" from
Strobe or Data Select to Y
Vee = 5.0 V,
Vcc=10V
240
110
360
170
ns
ns
C IN
Input Capacitance
(Note 2)
5.0
pF
Cpo
Power Dissipation Capacitance
(Note 3)
50
pF
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Cpo determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family
Characteristics application note AN-SO.
,
SWitching Time Waveforms
,~"'oo '~4
ov
Ipd,
Vee
\
OUTPUT (VI
Vee
I
-
Ipdl-
50%
10%
10%
I,
-
90%
50%
OV---'
I r • tf =
J
_lpdQ
90%
DATA INPUT
DATA SELECT
STROBE
~
50%
\
-
ov
IpdO--
--
r--
20 ns
It
I-TL./FI5892·3
6·61
-
AC Test Circuit
,
Vee
y
·i,,·. ·,
OUTPUT(W)
"dI
OUTPUT (V)
'i"'"''
GNO
.J:.
Tl.fFI5892·4
,
Truth Table
OUTPUTS
INPUTS
B
A
STROBE
DO
01
02
03
04
05
06
07
Y
W
x x
X
1
X
X
X
X
X
X
X
X
0
1
0
0
0
0
0
x
x
x
x
x
x
x
0
1
0
0
0
0
1
X
X
X
X
X
X
X
1
0
0
0
1
0
X
0
X
X
X
X
X
X
0
1
0
0
1
0
X
1
X
X
X
X
X
X
1
0
0
1
0
0
0
x
x
x
x
x
0
1
1
0
0
x
x
·X
0
X
1
X
X
X
X
X
1
0
0
1
1
0
X
X
X
0
X
X
X
X
0
1
0
1
1
0
X
X
X
1
X
X
X
X
1
0
x
x
x
0
x
x
x
0
1
X
1
X
·X
X
1
0
X
0
1
?<
1
0
C
1
0
0
0
1
0
0
0
x
x
x
x
1
0
1
0
X
X
X
X
X
0
X
1
0
1
0
X
X
X
X
X
1
X
1
1
0
0
x
x
0
1
0
x
x
x
0
x
x
0
1
x
x
x
1
x
x
X
1
X
1
0
1
1
1
0
X
X
X
X
X
X
X
0
0
1
1
1
1
0
X
X
X
X
X
X
X
1
1
0
,
6·62
~National
~ Semiconductor.
MM54C154/MM74C154 4-Line to 16-Line
Decoderl Demultiplexer
General Description
Features
The MM54C154/MM74C154 one of sixteen decoder is a
monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement
transistors. The device is provided with two strobe
inputs, both of which must be in the logical "0" state for
normal operation. If either strobe input is in the logical
"1" state, all 16 outputs will go to the logical "1" state.
•
•
•
•
Supply voltage range
Tenth power TTL compatible
High noise margin
High noise immunity
3Vto 15V·
drive 2 LPTTL loads
1 V guaranteed
0.45 Vee (typ.)
Applications
To use the product as a demultiplexer, one of the strobe .• Automotive
inputs serves as a data input terminal, while the other
• Data terminals
strobe input must be maintained in the logical "0" state.
The information will then be transmitted to the selected • Instrumentation
output as determined by the 4-line input address.
• Medical electronics
• Alarm systems
• Industrial electronics
• Remote metering
• Computers
Logic and Connection Diagrams
Dual-ln·Llne Package
OUTPUTS
TOP VIEW
INPUTS
Tl.lFI5893·2
Order Number MM54C154J or
MM74C154J
See NS Package J24A
Order Number MM54C154N or
MM74C154N
See NS Package N24A
6·63
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
MM54C154
MM74C154
Storage Temperature Range
(Note 1)
-0.3 V to Vee+0.3 V
-55'C to +125'C
-40'C to +85'C
-65'C to +150'C
DC Electrical Characteristics
18V
500mW
3Vto 15V
300'C
,.
Minimax limits apply across temperature range unless otherwise noted
Parameter
Symbol
Maximum Vee Voltage
Package Dissipation
Operating Vee Range
Lead Temperature (Soldering, 10 sec.)
Conditions
Min
Typ
Max
Units
CMOS to CMOS
VIN(1)
Logical "1" Input Voltage
Vee =5.0V
Vee = 10V
VIN(O)
Logical "0" Input Voltage
Vee =5.0V
Vee=10V
VOUT(1)
Logical "1" Output Voltage
Vee=5.0V,10=-10I'A
Vee = 10V, 10 = -1OI'A
VOUT(O)
Logical "0" Output Voltage
Vee = 5.0 V, 10=+1OI'A
Vee =10V, 10=+1O I'A
IIN(1)
Logical "1" Input Current
Vee = 15V, VIN = 15V
IIN(O)
Logical "0" Input Current.
Vee = 15V, VIN=OV
Icc
Supply Current·
Vee=15V
3.5
8.0
V
V
1.5
2.0
V
V
4.5
9.0
V
V
0.005
-1.0
0.5
1.0
V
V
1.0
I'A
-0.005
0.05
I'A
300
I'A
CMOS to LPTTL Interface
VIN(1)
Logical "1" Input Voltage
54C
74C
Vee=4.5V
Vee=4.75V
'VIN(O)
Logical "0" Input Voltage
54C
74C
Vee=4.5V
Vee=4.75V
VOUT(1)
Logical "1" Output Voltage
54C
74C
Vee=4.5V, 10=-1OOI'A
Vee=4.75V,10=-100I'A
VOUT(O)
Logical "0" Output Voltage
54C
74C
Vee=4.5V, 10 = 360l'A
Vee = 4.75 V, 10 = 360l'A
V
V
Vee- 1.5
Vee- 1.5
0.8
0.8
V
V
2.4
2.4
V
V
0.4
0.4
V
V
Output Drive (Sa,e 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
IsouReE
Output Source Current
Vee = 5.0 V, VIN(O)=OV
TA = 25'C, VOUT = OV
-1.75
mA
IsouReE
Output Source Current
Vee =10V, VIN(O)=OV
TA = 25'C, VOUT = OV
-8.0
mA
ISINK
Output Sink Current
Vee=5.0V, VIN(1)=5.0V
TA = 25'C, VOUT = Vee
1.75
mA
ISINK
Output Sink Current
Vee = 10 V, VIN (1) = 10 V
TA = 25'C, VOUT = Vee
8.0
mA
,
'.~
-
6-64
AC Electrical Characteristics
Symbol
TA =25°C, CL =50pF, unless otherwise noted.
Parameter
Conditions
Typ
Max
Units
tpdQ
Propagation Qelay to a Logical
"0" From Any Input to Any Output
Vee=5.0V,
Vee=10V
Min.
275
100
400
200
ns
ns
tpdQ
Propagation Delay to a Logical
"0" from G1 or G2 to Any Output
Vee = 5.0V,
Vee=10V
275
100
400
200
ns
ns
tpdl
Propagation Delay to a Logical
"1" from Any Input to Any Output
Vee=5.0V,
Vee=10V
265
100
400
200
ns
ns
tpdl
Propagation Delay to a Logical
"1" from G1 or G2 to Any Output
Vee=5.0V,
Vee=10V
265
100
400
200
ns
ns
CIN
Input Capacitance
(Note 2)
5.0
pF
Cpo
Power Dissipation Capacitance
(Note 3)
60
pF
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Cpo determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family
Characteristics application note AN-SO.
Switching Time Waveforms
VCC
~ ov
'~F
~UTPUT
A. 8. C OR 0
ANY
.50%
61
5011
,·t
5011
OR62~01l
5011
Vee
OV
tpdOf
tPd'f.:
Vee - - - - _
5011 ::e
ANY OUTPUT
OV
Vee
~Oll
5011
_ .
OV
TlIFI5893-3
t r =tf=20ns
TL/FI5B93·4
Truth Table
INPUTS
Gl G2
OUTPUTS
0
C
B
A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
15
L
L
L
L
H
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
L
L
H
H
H
H
L
H
H
H
H
H
·H
H
H
H
H
H
L
L
L
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
H
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
L
H
L
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X"" "Don't Care" Condition
6-65
....t;
~National'
~
,...
:IE
:IE
~ Semiconductor
~
.
~ MM54C157/MM74C157
:IE
.
:IE General Description
Quad 2-lnput Multiplexers
Features
These multiplexers are monolithic complementary MOS
(CMOS) Integrated circuits constructed with N- and
P-channel enhancement transistors. They consist of
four 2-input multiplexers with common select and enable
inputs. When the enable Input Is at logical "0" the four
outputs assume the values as selected from the inputs.
When the enable Input is at logical "1", the outputs
assume logical "0". Select decoding Is done internally
resulting in a single select Input only.
• Supply voltage range
3Vto 15V
• High noise Immunity
0.45 Vcc (typ.)
50nW (typ.)
• Lowpower
drive 2 LPTIL loads
• Tenth power TIL compatible
Logic and Connection Diagrams
Dual·ln·Line Package
Vee:
ENABLE
31'.
38
JV
.A
48
4V
SElECT
11'.
11
1Y
2"
28
2Y
UNO
I.o!--...............
,,0:...+-1-4"'_
3A
14
38
13
..
11
TOP VIEW
TLIF/6894·2
10
Order Number MM54C157J or
MM74C157J
See NS Package J16A
Order Number MM54C157N or
MM74C157N
See NS Package N16E
TLIFJ5B94·'
Truth Table
Guaranteed Noise Margin as a
Function of VCC
74L Compatibilitv
15V
ENABLE
SELECT
A
B
OUTPUTY
1
X
X
X
0
0
0
0
x
0
0
0
1
X
1
0
1
X
0
0
0
1
X
1
1
13.5
"""""'",.." , lZ.5
4.05
3.05
TI../F/5894-3
V1N (0)
2.5
~~~~~§§:~~~9·'·5
1.45
0.45 '---'-_ _-L._ _- - - '
'.50V
10V
15V
Vee
TUFI5at.4-4
6-66
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range.
MM54C157
MM74C157
Storage Temperature Range
(Note 1)
-0.3 V to Vee+0.3 V
-55'C to +125'C
-40'C to +B5'C
-65'C to +150'C
DC Electrical Characteristics
Symbol
I
Parameter
CMOS to CMOS
Maximum Vee Voltage
Package Dissipation
Operating Vee Range
Lead Temperature (Soldering, 10 sec.)
1BV
500mW
3Vt015V
300'C
Minimax limits apply across temperature range unless otherwise noted
I
Conditions
VIN(l)
Logical "1" Input Voltage
Vee=5.0V
Vee = 10V
VIN(O)
Logical "0" Input Voltage
Vee =5.0V
Vee=10V
VOUT(l)
Logical "1" Output Voltage
VOUT(O)
Logical "0" Output Voltage
IIN(l)
Logical "1" Input Current
IIN(O)
Logical "0" Input Current
Vce=5.0V
Vee = 10V
Vee =5.0V
Vee=10V
Vee- 15V
Vee =15V,
Icc
Supply Current
Vee = 15V
I
Min
I Typ I
Max
3.5
B
V
V
1.5
2
4.5
9.0
-1.0
I Units
V
V
V
V
0.005
-0.005
0.05
0.5
1.0
1.0
V
V
. "A
"A
60
"A
CMOS to Tenth Power Interface
VIN(l)
Logical "1" Input Voltage
VIN(O)
Logical "0" Input Voltage
54C . Vee=4.5V
74C Vee =4.75V
54C Vee =4.5V
74C Vce =4.75V
, VOUT(l)
Logical "1" Output Voltage
54C
74C
Vee=4.5V, 10=-360"A
Vee =4.75V, 10 = -360 "A
VOUT(O)
Logical "0" Output Voltage
54C
74C
Vee=4.5V, 10 = 360 "A
Vee = 4.75 V, 10 = 360 "A-
V
Vee -1.5
Vee -1.5
O.B
O.B
2.4
2.4
V
V
V
V
0.4
0.4
V
V
Output Drive (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
IsouReE
Output Source Current
Vee=5.0V, VIN(O)=OV
TA =25'C, VOUT=OV
-1.75
rnA
IsouReE
Output Source Current
Vee = 10 V, VIN(O) = 0 V
TA = 25'C, VOUT = 0 V
-B.O
rnA
ISINK
Output Sink Current
Vee = 5.0 V, VIN (1) = 5.0 V
TA = 25'C, VOUT = Vee
1.75
rnA
ISINK
Output Sink Current
Vee = 10 V, VIN(l) = 10 V
TA = 25'C, VOUT = Vee
B.O
rnA
AC Electrical Characteristics
Symbol
TA = 25'C, CL = 50 pF, unless otherwise specified.
Parameter
Typ
Max
Units
tpdO, tpdt
Propagation Delay from
Data to Output
Vee.=5.0V
Vee = 10V
150
70
250
110
ns
ns
tpdO, tpdl
Propagation Delay from
Select to Output
Vee=5.0V
Vee = 10V
Propagation Delay from
Enable to Output
CIN
Cpo
Input Capacitance
Vee=5.0V
Vee = 10V
(Note 2)
300
130
300
130
ns
. ns
tpdO, tpdl
1BO
BO
1BO
BO
5
20
Power Dissipation
Capacitance
. Conditions
(Note 3)
Min
ns
ns
pF
pF
Note 1: '"Absolute Maximum Ratings'" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Cpo determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family
Characteristics application note AN -90.,
6·67
~r---------~----------------~~-----------------------------------'
co
....
~National
:E
MM54C160/MM74C160 Decade Counter with
Asynchronous Clear
MM54C161/MM74C16t BinarY Counter with
ASynchronous Clear
. ,
MM54C162/MM74C162 Decade Counter with
Synchronous Clear
MM54C163/MM74C163 Binary Counter with
Synchronous Clear
~ ~ Semiconductor
~
~
:E
:E
~
~
:E
:E
....~
I
General Description
be used to enable successive cascaded 'stages. logic
transitions at the enable P or T inputs can occur when
the clock is high or low.
These (synchronous presettable up) counters are monolithic complementary MOS (CMOS) integrated circuits
constructed with N- and P-channel enhancement mode
:E transistors. They feature an Internal carry lookahead for
:E fast counting schemes and for cascadi ng packages
.... without additional gating_
~
CD
Features
.... A low level at the load input disables counting and
~ causes the outputs to agree with the data input after the
,... next positive clock edge. The clear function for the C162
:E and C163 is synchronous and a low level at the clear input
:E sets all four outputs low after the next positive clock
;:: edge. The clear function for the C160 and C161 is asyn~ chronous and a low level at the clear input sets all four
(,) outputs low regardless of the state of the clock.
;7;
:E
:E
i
1 V guaranteed
• High noise margin
0.45 Vcc (typ.)
• High noise immunity
drives 2 LPTTL loads
• Tenth power TTL compatible
3Vto 15V
• Wide supply voltage range
• Internal look-ahead for fast counting schemes
Counting Is enabled when both count enable inputs are
• Carry output for N-bit cascading
high. Input T is fed forward to also enable the carry out.
. • Load control line
The carry output is a positive pulse with a duration approximately equal to the positive portion of Q A and can
• Synchronously programmable
.... r---------------------------------------------------------------------------4
~
Dual-in-Line Package
:E Connection Diagram
:E
fA....
(,)
u
CLEAR-
1
16
r-v,c
CLDCK-
Z
15
r-~l~~~
1
14r-o....
1111 ... _
oo:r
~Na_ 4
urn..
1Nc_ S
121-0..:
LI)
Order Number MM54C160J, MM74C160J,
MM54C161J, MM74C161J, MM54C162J,
MM74C162J, MM54C163J or MM74C163J
See NS PaCkage J16A
III-DD
:E
:E
ENAILEP_J
CND-I
LogiC Waveforms
9~U1AD
TlIF/5895·'
Order Number MM54C160N, MM74C160N,
MM54C161N, MM74C161N, MM54C162N,
MM74C162N, MM54C163N or
MM74C163N
See NS Package N16E
C161, --- C163 Binary Counters
CLEARL.......Jr----------------lD. .D~-:--------------
C160, --- C162 Decade Counters
ClE,IIR"l..-.Jr-----------------
.
~o o~---------------
... ...r-!'--_____________
".
_____________
IN • ..J""I'--_____________
_____________
..J""I~
'"',-----------",...r-!L-_ _ _ _ _ _ __
"·...r-!L'_ _ _ _ _ _ __
'''..J""I~
...-------------------
ENAILfP~
eM"llf'~
tNAllET~
ENAIL(T~
ClOC1(~
CLDtK~
a.~
o.~
I
~~-------------CARRY __--:----::-'r-IL-:--:-:--:--:--,:1
•
,
1
1
!
J
1
I
I
TLfFf5895.2
CAARY-:---::---::--,r-I,:--:--:-:--:-:-~
II
13
14'5
II
1
,
J
I
1
3
TLIFI58Q5.3
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
MM54C160/1/2/3
MM74C160/1/2/3
Storage Temperature Range
(Note 1)
-0.3 V to Vcc+0.3 V
-55·C to +125·C
-40·C to +85·C .
-65·C to +150·C
18V
500mW
3Vto 15V
300·C
Maximum Vcc Voltage
Package Dissipation
Operating Vcc Range
Lead Temperature (Soldering, 10 sec.)
DC Electrical Characteristics Minimax limits apply across temperature ran'ge unless otherwise noted
Symbol
Parameter
Units
Conditions
CMOS to CMOS
VIN(1)
Logical "1" Input Voltage
Vcc=5.0V
Vcc=10V
VIN(O)
Logical "0" Input Voltage
Vcc=5.0V
Vcc=10V
VOUT(1)
Logical "1" Output Voltage
Vcc = 5.0V, 10 = -1OflA
Vcc =10V, 10=-1OflA
VOUT(O)
Logical "0" Output Voltage
Vcc-5.0V,10-+10flA
Vcc=10V, 10=+1OflA
IIN(;)
Logical "1" Input Current
Vcc =15V, VIN =15V
IIN(O)
Logical "0" Input Current
Vcc- 15V, VIN-OV
Icc
Supply Current
Vcc- 15V
V
V
3.5
8.0
1.5
2.0
V
V
4.5
9.0
0.5
1.0
0.005
1.0
V
V
1.0
0.005
0.05
V
V
flA
flA
300
flA
CMOS to LPTTL Interface
VIN(1)
Logical "1" Input Voltage
54C
74C
Vcc=4.5V
Vc c =4.75V
VIN(O)
Logical "0" Input Voltage
54C
74C
Vcc=4.5V
Vcc =4.75V
VOUT(1)
Logicali "1" Output Voltage
54C
74C
Vcc=4.5V, 10=-36O flA
Vcc=4.75V,10=-360flA
VOUT(O)
Logical "0" Output Voltage
54C
74C
Vcc=4.5V, 10=+360flA
Vcc = 4.75 V, 10=+36OflA
V
V
Vcc -1.5
Vcc -1.5
0.8
0.8
2.4
2.4
V
V
V
V
0.4
0.4
V
V
Output Drive (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
ISOURCE
Output Source Current
Vcc = 5.0 V, VIN(O) = 0 V
TA =25·C, VOUT=OV
1.75
mA
ISOURCE
Output Source Current
Vcc-10V, VIN(O) - OV
TA =25·C, VOUT=OV
8.0
mA
ISINK
Output Sink Current
Vcc = 5.0 V, VIN(1) = 5.0 V
TA = 25·C, VOUT = Vcc
1.75
mA
ISINK
Output Sink Current
Vcc = 10 V, VIN(1) = 10 V
TA = 25·C, VOUT = Vcc
8.0
mA
- 6-69
AC Electrical Characteristics
TA = 25°C, CL = 50 pF, unless othe\"Wise noted.
Typ
Max
Units
tpd
Propagation Delay Time from Clock to Q
Vee=5.0V
Vee = 10V
250
100
400
160
ns
ns
tpd
Propagation Delay Time from Clock to Carry Out
Vee=5.0V
Vee=10V
290
120
450
190
.ns'
ns
tpd
Propagation Delay Time from T Enable to Carry Out
Vee=5.0V
Vee = 10V
180
70
290
120
ns
ns
tpd
Propagation Time from Clear to Q
(C160 and C161 only)
Vee=5.0V
Vee = 10V
190
80
300
150,
ns
ns
ts
Time prior to Clock that Data or Load must be Present
Vee=5.0V
Vee = 10V
120
30
ns
ns
ts
Time prior to Clock that Enable P or T must be Present
Vee=5.0V
Vee=10V
170
70
280
120
ns
ns
ts
Time prior to Clock that Clear must be Present
(162, 163 only)
Vee=5.0V
Vee = 10V
120
50
190
80
ns
ns
tw
Minimum Clock Pulses Width
Vee=5.0V
Vee=10V
90
35
170
70
ns
ns
t" tf
Maximum Clock Rise or Fall Time
15
5.0
I'S
I'S
fMAX
Maximum Clock Frequency
Vee=5.0V
Vee = 10V
Cpo
Power Dissipation Capacitance
Note 3
95
pF
C IN
Input Capacitance
Note 2·
;i.0
pF
Sym
Parameter
Min
Conditions
. Vee=5.0V
Vee = 10V
2.0
5.5
MHz
MHz
3.0
8.5
Note 1: "Absolute Maximum Ratings"' are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range"' they are not meant to Imply that the devices should be operated at these limits. The table of "Electrical
Characteristics"' provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Cpo determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family
Charact~ristics application note AN-90.
,
I
i
\
I
6-70
Logic Diagrams
MM74C160. MM74C162; Cle.r is Synchronous for the MM74C162
CARRY
OUTPUT
CLEAR
CLOCK
LOAD
3:
3:
~
o.....
en
N
ENABLEP
3:
3:
~
ENA8LET~~----------------------------------_--J
TLlF/5895·4
o.....
MM74C161. MM74C163; Clear is Synchronous for the MM74C163
~
3:
3:
CARRY
OUTPUT
U'I .
~
.....
en
Co)
3:
3:
~
o
.....
en
Co)
ENABLET~~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _""
6-71
Mr-------------------------------------------------------------~-------,
~
o
Switching Time Waveforms
~
::E
::E
, CLEAR
C;
LOAD
....CD
~
INPUT
::E
::E
fi
....
o.
ENABLE'
ORT
~
::E
::E
CLOCK
....o~
OUTPUT
~
.::E
::E
tpdCLUAfll1
C160lndC161 om.,
TliF/5895·6
Note 1: Allm,ut pulses are flom g!nerators hiving thelollowing charKuristics: t,. = tt s
20 ns PRR:S; 1 MHz duty cvcle:S; 50%. ZoUT "" 50u.
Note 2: All limes .re measured from 50% 10 SO%,
Cascading Packages
+V
+V
'O.OT-----I:>c>---....-f--+-+-~~_+-....-t_-------_t-......-t_-4-+---'
D.
D,
D,
D,
TLlF/5896·1
Truth Table
Dual-In-Line Package
Serial Inputs A and B
Order Number MM54C164J or
MM74C164J
See NS Package J14A
Order Number MM54C164N or
MM74C164N
See NS Package N14A,
6-73
OUTPUT
In
In+l
A
B
QA
1
0
1
1
1
1
0
0
0
0
0
0
TLIF/5896-2
INPUTS
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
MM54C164
MM74C164
Storage Temperature Range
(Note 1)
-0.3 V to Vee+0.3 V
-55°C to +125"C
-40"C to +B5"C
-65°C to +150"C
DC Electrical Characteristics
Symbol
Absolute Maximum Vee
Package Dissipation
Operating Vee Range
lead Temperature (Soldering, 10 sec.)
lBV
500mW
3Vto 15V
300°C,
Minimax limits apply across temperature range unless otherwise noted
Parameter
Conditions
Min
Typ
Max
Units
CMOS to CMOS
3.5
B.O
VIN(1)
logical "1" Input Voltage
Vee;= 5.0V
Vee=10V
VIN(O)
logical "0" Input Voltage
Vee =5.0V
Vee=10V
VOUT(1)
logical "1" Output Voltage
Vee = 5.0V, 10 = -10"A
Vee = 10 V, 10 = -10"A
VOUT(O)
logical "0" Output Voltage
Vee =5.0V,10=+10"A
Vee =10V, 10=+10"A
V
V
1.5
2.0
IIN(1)
logical "1" Input Current
Vee = 15V, VIN = 15V
IIN(O)
logical "0" Input Current
Vee = 15V, VIN=OV
Icc
Supply Current
Vee=15V
4.!)
9.0
V
V
0.005
-1.0
V
V
0.5
1.0
V
V
1.0
"A
-0.005
0.05
"A
,300
"A
CMOS to LPTTL Interface
VIN(1)
logical "1" Input Voltage
54C
74C
Vee=4.5V
Vee = 4.75 V
VIN(O)
logical "0" Input Voltage
54C
74C
Vee=4.5V
Vee=4.75V
logical "1" Output Voltage
54C
74C
Vee=4.5V, 10=-360"A
Vee=4.75V,10=-360"A
logical "0" Output Voltage
54C
74C
Vee=4.5V, 10 = 360"A
Vee=4.75V, 10 = 360 "A
VOUT(1)
VOUT(O)
Vee -l.5
Vee -l.5
V
v
O.B
O.B
V
V
Output Source Current
V
0.4
0.4
V
V
IsouReE
Output Source Current
ISINK
Output Sink Current
ISINK
Output Sink Current
=
=
Vee = 5.0 V, VIN(O) 0 V
TA 25°C, VOUT 0 V
-1.75
mA
Vee = 19 V, VIN(P) = 0 V
TA 25°C, VOUT = 0 V
-B.O
mA
1.75
mA
B.O
mA
=
=
Vee =5.0 V, VIN(1) =5.0 V
TA = 25°C, VOUT = Vee
=
Vee = 10 V, VIN(1) 10 V
TA 25°C, VOUT = Vee
=
,
.,
6·74
i
V
2.4
2.4
Output Drive (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
IsouReE
,
I
AC Electrical Characteristics
Sym
TA = 25'C, CL = 50pF, unless otherwise noted.
Parameter
Typ
Max
Units
tpd1
Propagation Delay Time to a Logical "0" or a
Logical "1" from Clock to Q
Vee=5.0V
Vee=10V
Conditions
Min
230
90
310
120
ns
ns
tpdO.
Propagation Delay Time to a Logical "0" from
Clear to Q
Vcc =5.0V
Vec=10V
280
110
380
150
ns
ns
ts
Time Prior to Clock Pulse that Data Must be
Present
Vee=5.0V
Vee=10V
200
80
110
30
ns
ns
tH
Time After Clock Pulse that Data Must be Held
Vee=5.0V
Vee=10V
0
0
0
0
ns
ns
fMAX
Maximum Clock Frequency
Vee =5.0V
Vee=10V
2.0
5.5
3
8
MHz
MHz
tw
Minimum Clear Pulse Width
Vee=5.0V
Vee=10V
tn tf
Maximum Clock Rise and Fall Time
Vee =5.0V
Vee = 10V
C IN
Input Capacitance
Any Input (Note 2)
Cpo
Power Dissipation Capacitance
(Note 3)
150
55
250
90
ns
ns
,..s
.,..s
15
5.0
5
pF
140
pF
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Capacitance Is guaranteed by periodic testing.
Note 3: Cpo determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family
Characteristics application note AN-90.
I
Logic Waveforms
u
tltAR~
{'
KRIAl
INPUTS
~
tlOC.-
,. --
~ ..fU1..1LJl..
-,.:-1
IIUTPUTS
',::1
'.::1
..--L..JI I
r-LJI
r---:-l I
.. ::]
.. ::J
..
I II
Il a : : '
,.::]
;
n
eLJ",.
CLJAR
TUF/5896-3
Switching Time Waveforms
CMOS to CMOS
..
uv
.:i"r:Jf:-~".
•.D:
DV~ ""
v",
DATA
ov
1.5V
D~.--j"r-
Jf,.
""'
l
IsETI.I'1
IHOLDI
lSETUPO
tHOLDO
v~~50.
DV --j.,~
Vo<
• DV
DATA
•
-j,t
-j"r,
v"
CLOCK
TTL to CMOS
,.
v"
[
'SETUP 1
\seTuP 0
•.DV'14
"..'"
[
-1,
.
H__,'"
DV __
Vo<
DV
-""-/""
v"
_ ....-\0'"
I.5V
..
1t
.
'''' ,
1.SV
IV''"'
1.5V
tHOLD!
....
~
t.["
1.5V
""-1., .
-"',-f·'v
___ tpolll_~.5V
'v
... "'It-ZIlIlS
TLIFI5B96-4
TLIF/5896-5
6-75
AC Test Circuit
INPUTS {
CLOCK
TUFI5896.&
Typical Applications·
Vee
Guaranteed Noise Margin as a Function of
=:--:=====-,
15V r-____
74C Compatibility
13.5
12.5
v,,
iii
;
'"
~
4.05
3.05
~~~2.5
1.5
1.45~
TLIFI5896-7
0.45 1 -_ _- ' -_ _----1
4.50V
10V
15V
Vee
TLlF/5896·8
6·76
s:
s:
~National
~
~ Semiconductor
...
o
-ss::
0)
U1
M~54C165/MM74C165
...~
Parallel· Load 8·Bit Shift Register
m
General Description
Features
The MM54C165/MM74C165 is an 8-bit serial shift register
which shifts data from QA to QH when clocked. Parallel
inputs to each stage are enabled by a low level at the
shiftlload input. Also included is a gated clock input and
a complementary output from the eighth bit.
• Wide supply voltage range
Clocking is accomplished through a 2-input NOR-gate
permitting one input to be us.ed as a clock-inhibit function. Holding either of the clock ;inputs high. inhibits
clocking; and holding either clock input low with the
shiftlload high enables the other clock input. Data transfer occurs on the positive edge of the clock. The clock
inhibit input should be changed to a high level only while
the clock input is high. Parallel loading is inhibited as
long as the shiftlload input is high. When taken low, data
at the parallel inputs is loaded directly into the register
independent of the state of the clock.
o
3.0Vto 15V
1.0V
• Guaranteed noise margin
0.45 Vee (typ.)
• High noise immunity
• Low power TTL compatibility
fan out of 2
driving 74L
• Direct overriding load
• Gated clock inputs
• Fully static operation
Connection and Block Diagrams
Dual-In-Line Package
PARALLElIN~UTS
Order Number MM54C165J or
MM74C165J
• See NS Package J16A
Order Number MM54C165N or
MM74C165N
See NS Package N16E
SHIFTI
LOAD
PARAllEl
J~J>UTS
TOP VIEW
TLlF15897·1
CLOCK
CLOCK.NH.BIT
TlIFI5897·2
~Lo---,-----~------~----
__ ____ ______ ____
~
~
~
~~~
____-,
~O---+-~--~--'---~-1----~~---+--~--+--'---4--~--~
I'ARALLHINPUTS
6-77
.,
TUFI5897-3
II
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
MMS4C16S
MM74C16S
Storage Temperature Range
(Note 1)
Absolute Maximum Vcc
Package Dissipation
Operating Vcc Range
Lead Temperature (Soldering, 10 sec.)
-0.3Vto Vcc +0.3V
-SS·C to +12S·C
-40·C to +BS·C
-6S·C to +1S0·C
1BV
SOOmW
3Vto 1SV
300·C
.
DC Electrical Characteristics Minimax liinlts apply across temperature range unless «?therwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS to CMOS
3.S
B.O
VIN(')
logical "1" Input Voltage
Vcc=S.OV
Vcc=10V
VIN(O)
Logical "0" Input Voltage
Vcc=S.OV
Vcc=10V
VOur(1)
Logical "1" Output Voltage
Vcc - S.OV, 10- 10"A
Vcc = 10V, 10 = -10"A
Vour(O)
logical "0" Output Voltage
Vcc = S.OV, 10=+10"A
Vce = 10V, 10 = +10"A
IIN(')
Logical "1" Input Current
Vcc= 1SV, VIN = 1SV
IIN(O)
L~gical
Vc c =1SV, VIN =OV
Icc
Supply Current
"0" Input Current
V
V
1.S
2.0
4.S
9.0
V
V
O.OOS _
-1.0
O.S
1.0
V
V
1.0
"A
-O.OOS
O.OS
Vec- 1SV
V
V
"A
300
"A
CMOS to LPTIL Interface
Logical "1" Input Voltage
54C Vcc=4.SV
74C Vcc =:4.7SV
VIN(O)
logical "0" Input Voltage
S4C
74C
Vcc=4.SV
Vcc=4.7SV
Vour(,)
Logical "1" Output Voltage
54C
74C
Vcc=4.SV, 10=-360"A
Vcc = 4.7SV, 10=-360"A
VOUT(O)
Logical "0" Output Voltage
S4C
74C
Vcc=4.SV, 10-360"A
Vcc=4.7SV, 10 = 360"A
VIN(')
V
Vec- 1•S
Vec- 1.S
v
O.B
O.B
"2.4
2.4
V
"V
V
V
0.4
0.4
V
V
Output Drive (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
ISOURCE
Output Source Current
(P·Channel)
ISOURCE
Output Source Current
(P·Channel)
ISINK
Output Sink Current
(N·Channel)
ISINK
Output Sink Current
(N·Channel)
.
Vcc=S.OV
TA =2S"C, VOUT=OV
-1.7S
":3.3
mA
Vcc=10V
TA =2S·C, VOUT=OV
-B.O
-1S
mA
Vcc=S.OV
TA = 2S·C, Vour = Vce
1.7S
3.6
mA
Vcc- 1OV
TA = 2S·C, Vour = Vec
B.O
16
mA
,
-,
6·78
AC Electrical Characteristics
Symbol
s:
s:
TA = 25'C. CL = 50 pF. unless otherwise noted.
Parameter
Conditions
Min
Typ
Max
Units
~
0
.....
tpdO. tpdl
Propagation Delay Time to a Logical "0" or
Logical "1" from Clock or Load to Q or Q
Vee =5.0V
Vee = 10V
200
80
400
200
ns
ns
tpdO. tpdl
Propagation Delay Time·to ~Logical "0" or
Logical ':1" from H to Q or Q
Vee=5.0V
Vee = 10V
200
80
400
200
ns
ns
-sms::
ts
Clock Inhibit Set·up Time
Vee -5.0V
Vee=10V
150
60
75
30
ns
ns
0.....
ts
Serial Input Set·up Time
Vee =5.0V
Vee = 10V
50
30
.25
15
ns
ns
tH
Serial Input Hold Time
Vee =5.0V
Vee = 10V
50
30
0
0
ns
ns
ts
Parallel Input Set·up Time
Vee=5.0V
Vee=10V
150
60
75
30
ns
ns
tH
Parallel Input Hold Time
Vee =5.0V
Vee=10V
50
30
0
0
ns
ns
tw
Minimum Clock Pulse Width
Vee =5.0V
Vee=10V
70
30
200
100
ns
ns
tw
Minimum Load Pulse Width
Vee=5.0V
Vee = 10V
85
30
180
90
ns
ns
f MAX
Maximum Clock Frequency
Vee =5:0V
Vee=10V
2.5
5.0
trot,
Maximum Clock Rise and Fall Time
Vee=5.0V
Vee = 10V
10
5.0
C IN
Input Capacitance
(Note 2)
5.0
pF
Cpo
Power Dissipation Capacitance
(Note 3)
65
pF
6.0
12
MHz
MHz
I'S
I'S
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" tney are not meant to imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Cpo determines the no load AC power consumption of any CMOS device. For complete explanation see 54CJ74C Family
Characteristics application note AN-90.
Switching Time Waveforms
V,,
CLOCK
INHIBIT
CLOCK
05Vcc
av
v"
(I5V cc
av -
...
-
Vcc-~-,
SERIAL
INPUT
OSVcc
av
v"
DV
F. H
INPUTS
05Vcc
SHIFT!
D5~::--r-'-
lOAD
.,
",
-D;'41'~"
-- !_--II>"[
v"
D5Vcc
,i ,
_I
av
!__ ,~,
v,,--t
~___. __
-] . . 11---
tpdQ
D5V cc
'v
NOleA The remallling ,IX dala and the
NilleS Puor!a te,t, high level dati
IS
s~lJalll1put
are ID .....
Joaded IIlto H II1Pllt
TLIFI5897-4
6·79
.....
~
Q)
U'I
~
,..
~
Truth Table
:::E
:::E
is,..
INPUTS
SHIFT!
LOAO
CLOCK
INHIBIT
CLOCK
~:::E
:E
SERIAL
PARALLEL
A •.• H
INTERNAL
OUTPUTS
aA
OUTPUT
aB
aH
L
x
X
a ... h
a
b
h
H
L
L
X
X
CAO
CBO
CHO
H
L
t
t
t
H
X
H
H
L
H
H '
X
CAo
CGo
L
X
L
CAo
CGo
X
.X
CAO
aBO
CHO
H:. V'N(1). L == VIN(O)
x = irrelevant
f ;:: transition from VIN(OJ to VIN(11
a ... h = the level at data inputs A thru H
CAO. 0ao. OHO '" the level of 0A. 0B or 0H. before the mdlcated mput conditIons were established
0An. ClGn = the level of OA or CG before ~he most recent I tnms,t,on of the clock.
Logic Waveforms
CLOCK
ClOCKINHI8rT;;~;;t=============
SHIFT/LOAD
DATA
f.--t''---f-------------
OUTPUT IlK
OUTPUTDtt
--j_ _ _ _ _ SER1ALSHIFT
__ - . - - - _
TI..IFI5897·5
6·80
~National
~ Semiconductor
MM54C173/MM74C173 TRI-STATE® Quad D Flip-Flop
General Description
Features
The MM54C173/MM74C173 TRI-STATE quad 0 flip flop
is a monolithic complementary MOS (CMOS) integrated
circuit constructed with N- and P-channel enhancement
transistors. The four D-type flip flops operate synchronously from a common clock. The TRI-STATE output allows the device to be used in bus-organized systems.
The outputs are placed in the TRI-STATE mode when
either of the two output disable pins are in the logic "1"
level. The input disable allows the flip flops to remain in
their present states without disrupting the clock. If
either of the two input disables are taken to a logic "1"
level, the Q outputs are fed back to the inputs and in
this manner the flip flops do not change state.
- Supply voltage range
- Tenth power TTL compatible
- High noise immunity
Clearing is enabled by taking the input to a logic "1"
level. Clocking occurs on'the positlve-going transition.
-
3Vto 15V
Drive 2 LPTTL loads
0.45 Vee (typ.)
Low power
Medium speed operation
High Impedance TRI·STATE
Input disable without gating the clock
Applications
-
Automotive
Data terminals
Instrumentation
Medical electronics
-
Alarm systems
Industrial electronics
Remote metering
Computers
Logic and Connection Diagrams
Dual-In-Line Package
DATAl"""
OIA...
!
...C<
.1'1,1'10------++-;-.,
0\,11"\,110\,11'1,11 OUll'UTOUTPUTOUTPUT OUTPUT
DISAILEDISABLE
A
C,
leo
TLIFI5898·2
Order Number MM54C173J or
MM74C173J
See NS Package J16A
OUTPUle
.IPUTOo-----+t--r,
Order Number MM54C173N or
MM74C173N
See NS Package N16E
Truth Table
OUTPUT 0 ,
(Both Output Disables Low}
tn+l
In
OUlPIIT!
DATA INPUT DISABLE
' . .IU
TL/F/5898-1
6-81
Logic "1" on One or Both Inputs
Logic "0" on Both Inputs
Logic "0" on Both Inputs
DATA
INPUT
X
OUTPUT
I
On
I
0
0
, Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
MM54C173
MM74C173
Storage Temperature Range
(Note 1)
-55·C to +125·C
-40·C to +85·C
-65·C to +150·C
DC Electrical Characteristics
Symbol
MinImax
1i~lts
apply across temperature range unless otherwise
Min
Conditions
Parameter
18V
500mW
3Vto 15V
300·C
Maximu,m Vcc Voltage
Package Dissipation
Operating Vec Range
Lead Temperature (Soldering, 10 sec.)
-0.3 V to Vcc + 0.3 V
Typ
Max
note~
Units
CMOS to CMOS
Logical "1" Input Voltage
Vcc =5.0V
Vcc=10V
VIN(O)
Logical "0" Input Voltage
Vcc =5.0V
Vce=10V
VOUT(l)
Logical "1" Output Voltage
Vcc =5.0V
Vee=10V
VOUT(O)
Logical "0" Output Voltage
Vee=5.0V,
Vce= 10V
IIN(l) .
Logical "1" Input Current
Vec= 15V
IIN(O)
Logical "0" Input Current
loz
Output Current in High
Impedance State
Vec = 15 V; Vo = 15 V
Vcc= 15V, Vo=OV
Supply Current
Vce=15V
Icc
V
V
3.5
8.0
VIN (l)
1.5
2.0
4.5
9.0
V
V
V
V
0.5
1.0
0.005
1.0
V
V
IJA
1.0
0.005
0.001
0.001
1.0
-1.0
IJA
IJA
0.05 '
300
IJA
IJA
Low Power TTL/CMOS Interface
Logical "1" Input Voltage
54C
74C
Vec =4.5V
Vcc =4.75V
VIN(O)
Logical "0" Input Voltage
54C
74C
Vec =4.5V
Vec =4.75V
VOUT(l)
Logical "1" Output Voltage
54C
74C
Vec=4.5V, 10=-36O IJA
Vcc = 4.75 V, 10 =-36OIJA.
VOUT(O)
Logical "0" Output Voltage
54C
74C
Vcc=4.5V, 10 = 360IJA
Vcc =4.75V, 10 = 360IJA
tpdO, tpdl
Propagation Delay Time to
a Logical "0" or Logical
"1" from Clock
VIN(l)
V
Vcc -1.5
Vcc-1.5
v
0.8
0.8
2.4
2.4
V
V
0.4
0.4
Vcc=5.0V, CL =50pF,
TA=25·C
V
V
500
V
V
ns
Output Drive (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
ISOURCE
Output Source Current
ISOURCE
Output Source Current
ISINK
Output Sink Current
ISINK
Output Sink Current
Vcc = 5.0 V, VIN(O) = 0 V
TA = 25·C, VOUT = OV
-1.75
mA
-8.0
mA
Vcc = 5.0 V, VIN (l) = 5.0 V
TA = 25·C, VOUT = Vcc
1.75
mA
Vec = 10V, VIN(1) = 10V
TA = 25·C, VOUT = Vec
8.0
mA
Vcc=10V, VIN(O)=OV
, TA ",,25·C, VOUT=OV
,
6-82
AC Electrical Characteristics
$:
$:
TA = 25'C, CL = 50 pF, unless otherwise noted.
c.n
~
Symbol
Parameter
Min
Conditions
Typ
Max
Units
tpdO, tpdl
Propagation Delay Time to a Logical "0" or
Logical "1" from Clock to Output
Vee=5.0V
Vee=10V
220
80
400
200
ns
ns
ts
Input Data Set-up Time
Vee- 5.OV
Vee = 10V
40
15
80
30
ns
ns
tH
Input Data Hold Time
Vee=5.0V
Vee = 10V
0
0
ns
0
ns
Vee=5.0V
Vee = 10V
Vee- 5.OV
Vee = 10V
100
35
0
0
200
70
0
0
ns
ns
ns
ns
0
Input Disable Set-up Time, ts DISS
tH
Input Disable Hold Time, tH DISS
tlH, tOH
Delay from Output Disable to High Impedance
State (from Logical "1" or Logical "0" Level)
Vee = 5.0V, RL = 10 k
Vee = 10V, RL = 10k
170
70
340
140
ns
ns
tHl
Delay from Output Disable to Logical "1"
Level (from High Impedance State)
Vee=5.0V
Vee=10V
170
70
340
140
ns
ns
tHO
Delay from Output Disable to Logical "0"
Level (from High Impedance State)
Vee=5.0V
Vee=10V
170
70
340
140
ns
ns
tpdO, tpdl
Propagation Delay from Clear to Output
Vee- 5.OV
Vee = 10V
240
90
490
180
ns
ns
fMAX
Maximum Clock Frequency
Vee=5.0V
Vec=10V
tw
Minimum Clear Pulse Width
Vee=5.0V
Vee = 10V
tr, tf
Maximum Clock Rise and Fall Time
Vee- 5.OV
Vee = 10V
CIN
Input Capacitance
(Note 2)
Cpo
Power Dissipation Capacitance
(Note 3)
4.0
12
MHz
MHz
150
70
ns
ns
10
5.0
1'5
1'5
5.0
pF
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Cpo determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family
Chara'cteristics application note AN -90.
Switching Time Waveforms
-'.
~
I
90:.'.
CLEAR
50%
10%
•_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
I
OUTPUT
+-,,-,,~-5O~~5O%----,,-,,~-5O~~5O%----I
DISABLE
__ I
DATA
i
INPUT
I
-----l
,---tH OISS
I
50%
ISOATA-~
!
DATA
OUTPUT
50%
I--
tSOATA---i
50%
S-
-
~90%-Fb~'""" ~. 1---'"0""
!
I
CLOCK
r--..
.JA".,
~
tH QISS
I'
r-
50%
--f----..J
--I '~:
~.
~
" ,-~
10%
50%
--~ ,~,
_ _ _ _ _ _ _ _ _ _ _ _- J
50%
r--
-
SOl'.
--j
,~, I---
-
TLlF15898·3
6-83
....
.....,
Co)
3:
$:
.....,
~
.........,
()
ts
3.0
7.0
(')
Co)
~National
~ Semiconductor
MM54C174/MM74C174 Hex.O Flip-Flop
General Description
Features
The MM54C174/MM74C174 hex 0 flip-flop is a monolithic
complementary MOS (CMOS) integrated circuit constructed with N- and P-ohannel enhancement transistors.
All have a direct ciear input. Information at the 0 inputs
meeting the setup time requirements is transferred to the
Q outputs on the positive-going edge of the clock pulse.
Clear is independent of ciock and accomplished by a low
level at the ciear input. All inputs are protected by diodes
To Vee and GND.
• Wide supply voltage range
3.0Vto 15V
tOV
• Guaranteed noise margin
0.45 Vee (typ.) .
• High noise immunity
fan. out of 2
driving 74L
• Low power TTL compatibility
Logic and Connection Diagrams
DATA
mm
----.J
C L E A R - - - - - - - - - -....
Ci
CL
60
50
50
Ci
CL
TL/F/5899-1
40
TlfFI5899-2
40
CLOCK
OUTPUT
INPUTS
CLEAR
10
10
20
20
TOP VIEW
30
lUF/5899-3
Truth Table
Dual·ln·Line Package
60
CI
l'
CLOCK~
Vee
Cl
30
GNO
TUFI58~
Order Number MM54C174J or MM74C174J
See NS Package J16A
Order Number MM54C174N or MM74C174N
See NS Package N16E
6-84
CLEAR
CLock
0
a
L
x
X
H
H
L
H
H
t
t
H
L
L
X
Q
L
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
MM54C174
MM74C174
Storage Temperature Range.
(Note 1)
-55'C to +125'C
-40'C to +85'C
-65'C to +150'C
DC Electrical Characteristics
Symbol
Package Dissipation
Operating Vee Range
Absolute Maximum Vee
Lead Temperature (Soldering, 10 sec.)
-0.3 V to Vee + 0.3 V
500mW
3.0Vto 15V
18V
300'C
Minimax limits apply across temperature range unless otherwise noted
Parameter
Conditions
Min
Typ
Max
Units
CMOS to CMOS
VIN(1)
Logical "1" Input Voltage
i
3.5
8.0
Vee=5.0V
Vee=10V
V
V
1.5
2.0
VIN(O)
logical "0" Input Voltage
Vee=5.0V
Vee=10V
VOUT(')
Logical "1" Output Voltage
Vee=5.0V,1 0 --10"A
Vee=10V,lo=-10"A
VOUT(O)
Logical "0" Output Voltage
Vee- 5.OV,lo-+10"A
Vee = 10V, 10 = +10"A
IIN(')
Logical "1" Input Current
Vee=15V, VIN =15V
IIN(O)
logical "0" Input Current
Vee=15V, VIN=OV
Icc
Supply Current
Vc;e- 15V
4.5
9.0
V
V
0.005
-1.0
V
V
0.5
1.0
V
1.0
"A
-0.005
0.05
V
"A
300
"A
CMOSILPTTL Interface
Logical "1!' Input Voltage
54C
74C
Vee=4.5V ,
Vce=4.75V
VIN(O)
Logical "0" Input Voltage
54C
74C
Vee=4.5V
Vee=4.75V
VOUT(')
Logical "1" Output Voltage
54C
740
Vee = 4.5 V, 10=-360"A
Vee 4.75 V, 10=-360"A
VOUT(O)
Logical "0" Output Voltage
54C
74C
Vee = 4.5 V, 10 = 360"A
Vee = 4.75 V, 10 = 360"A
VIN(,)
Vee -1.5
Vee -1.5
V
v
0.8
0.8
=
2.4
2.4
V
V
V
V
0.4
0.4
V
V
Output Drive (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
IsouReE Output Source Current
(P-Channel)
Vee =5.0V
TA=25'C, VOUT=OV
-1.75
-3.3
mA
IsouReE Output Source Current
(P-Channel)
Vee=10V
TA=25'C, VOUT=OV
-8.0
-15
mA
ISINK
Output Sink Current
(N-Channel)
Vee=5.0V
TA = 25'C, VOUT = Vee
1.75
3.6
mA
ISINK
Output Sink Current
(N-Channel)
Vee=10V
TA = 25'C, VOUT = Vee
8.0
16
mA
6-85
~
.....
~:E
:E
~
.....
~
:E
:E
AC Electrical Characteristics
Symbol
TA = 25°C, CL = 50pF, unless otherwise noted.
Parameter
Conditions
Min
Typ
Max
Units
tpd
Propagation Delay Time to a Logical
"0" or Logical "1" from Clock to Q
Vcc=5.0V
Vcc=10V
150
70
300
110
ns
ns'
tpd
Propagation Delay Time to a Logical
"0" from Clear
Vcc =5.0V
Vcc=10V
110
50
300
110
ns
ns
tSl, tso Time Prior to Clock Pulse that Data
must be Present
Vc c- 5.OV
Vcc= 10V.
75
25
tHl, tHO Time after Clock Pulse that Data
must be Held
Vcc -5.0V
Vcc =,10V
Vcc =5.0V
Vcc=10V
0
0
tw
Minimum Clock Pulse Width
tw
Minimum Clear Pulse Width
Vcc =5.0V
Vcc=10V
t" tf
Maximum Clock Rise ancl Fall Time
fMAX
Maximum Clock Frequency
Vcc =5.0V
Vcc= 10V
Vcc =5.0V
Vcc=10V
CIN
Input Capacitance
Cpo
Power Dissipation Capacitance
ns
ns
-10
-5.0
ns
ns
50
35
,250
100
ns
ns
65
35
140
70
ns
ns
15
5.0
>1200
>1200
2.0
5.0
6.5
.12
MHz
MHz
Clear Input (Note 2)
Any Other Input
11
5.0
pF
pF
Per Package (Note 3)
95
pF
j.lS
j.IS
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table ilf "Electrical,
Characteristics" provides conditions for actual device operation.
'-Note 2: Capacitance Is guaranteed by periodic testing.
Note 3: Cpo determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family
Characteristics application note AN -90.
Switching Time Waveforms
AC Test Circuit
CMOS to CMOS
v,,---+T::;:;----CLOCK
ov--='-''"I
INPUT
DATA
. INPUT
CLOCK
DATA
fl:JF/5899-6
DATA
ov---1-1".:.:;:;.-t-9
v" -----+-----~50%
ov----t---..J
Vee
----t---""'
ov---------'-1,:'I,"20ns
TL/F/5899-5
'6·86
~National
~ Semiconductor
MM54C175/MM74C175 Quad D Flip-Flop
General Description
The MM54C175/MM74C175 consists of four positiveedge triggered 0 type flip-flops implemented with
monolithic CMOS technology_ Both are true and complemented outputs from each flip-flop are externally
available. All four flip flops are controlled by a common
clock and a common clear. Information at the 0 inputs
meeting the set-up time requirements is transferred to
the a outputs on the positive-going edge of the clock
pulse. The clearing operation, enabled by a negative
pulse at Clear Input, clears all four a outputs to logical
"0" and a's to logical "1".
All inputs are protected from static discharge by diode
clamp~ to Vee and GND.
Features
3.0Vto 15V
• Wide supply voltage range
• Guaranteed noi~e margin
1.0V
• High noise immunity
0.45 Vee (typ.),
fan out of 2
driving 74L
• Low power TTL compatibility
Connection Diagram and Truth Table
Dual-In-Line Package
Vee
4Q
40.
4D
3D
3D
3Q
CLOCK
Each Flip·Flop
INPUTS
CLEAR
H
L
10
10
ZD
2Q
TOP VIEW
GND
TLIFIS900·'
D
Q
Q
L
X
X
L
H
H
H
H
L
H
t
t
L
L
H
H
H
X
NC
NC
H
L
X
NC
NC
- High level
= Low level
t
= Irrelevant
= TranSition from low to hIgh level
NC
= No change
X
CLEAR
OUTPUTS
CLOCK
Order Number MM54C175J or MM74C175J
See NS Package J16A
Order Number MM54C175N or MM74C175N
See NS Package N16E
Logic Diagram
Typical One of Four
CL
HUt,
C[
TlIF/5900.3
CI
CLOCK--t>~CL
CLEAR
CL
TL/FI5900·2
6-87
TLlF/5900·4
\
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
MM54C175
MM74C175
Storage Temperature Range
(Note 1)
-0.3 V to Vee + 0.3 V
-55·C to +125·C
-40·C to +85·C
-65·C to +150·C
DC Electrical Characteristics
Symbol
Package Dissipation
Operating Vee Range
Absolute Maximum Vee
Lead Temperature (Soldering, 10 sec.)
500mW
3Vto 15V
18V
300·C
Minimax limits apply across temperature range unless otherwise noted
Parameter
Conditions
Min
Typ
Max
Units
CMOS to CMOS
3.5
8.0
VIN(')
Logical "1" Input Voltage
Vee=5.0V
Vee=10V
VIN(O)
Logical "0" Input Voltage
Vee =5.0V
Vce=10V
VOUT(,)
Logical "1" Output Voltage
Vcc =5.0V,lo=-1O"A
Vce =10V,l o =-1O"A
VOUT(O)
Logical "0" Output Voltage
Vec =5.0V,l o =+10"A
Vee =10V,l o =+10"A
IIN(')
Logical "1" Input Current
Vec = 15V, VIN = 15V
IIN(O)
Logical "0" Input Current
Vee=15V, VIN=OV
Icc
Supply Current
Vee=15V
V
V
1.5
2.0
4.5
9.0
V
V
0.005
-1.0
V
V
0.5
1.0
V
V
1.0
"A
-0.005
0.05
"A
300
"A
CMOS/LPTTL Interface
,
VIN(')
Logical "1" Input Voltage
54C
74C
Vce=4.5V
Vca =4.75V
vIN(O)
Logical "0" Input Voltage
54C
74C
Vce=4.5V
Vce =4.75V
VOUT(,)
Logical "1" Output Voltage
54C
74C
Vee=4.5V, 10:=-360"A
Vee = 4.75V, 10=-360"A
VOUT(O)
Logical "0" Output Voltage
54C
74C
Vce=4.5V, 10 = 360"A
Vcc=4.75V, 10 = 360 "A
V
v
Vee- 1.5
Vee -1.5
0.8
0.8
2.4
2.4
V
V
.V
V
0.4
0.4
V
V
Output Drive (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
IsouReE Output Source Current
(P·Channel)
Vee =5.0V
TA = 25·C, VOUT = 0 V
-1.75
-3.3
rnA
ISOURCE Output Source Current
(P·Channel)
Vee=10V
TA = 25·C, VOUT = OV
-8.0
-15
rnA
ISINK
Output Sink Current
(N·Channel)
Vee=5.0V
TA = 25·C, VOUT = Vee
1.75
3.6
rnA
ISINK
Output Sink Current
(N-Channel)
Vce=10V
TA = 25·C, VOUT = Vee
8.0
16
rnA
~
.
6-88
AC Electrical Characteristics
TA = 25°C, CL =50pF, unless otherwise noted.
Parameter
Sym
Conditions
Min
1
Typ
Max
Units
Vcc =5.0V
Vcc=10V
190
75
300
110
ns
ns
Propagation Delay Time to a Logical
"0" from Clear to Q
Vcc -5.0V
Vcc=10V
180
70
300
110
ns
ns
tpd
Propagation Delay time to a Logical
"1" from Clear to Q
Vcc =5.0V
Vcc=10V
230
90
400
150
ns
ns
ts
Time Prior to Clock Pulse that Data
must be Present
Vcc =5.0V
Vcc=10V
100
40
tH
Time After Clock Pulse that Data
must be Held
Vcc=5.0V
Vcc=10V
0
0
tw
Minimum Clock Pulse Width
Vcc=5.0V
Vcc=10V
130
45
250
100
ns
ns
tw
Minimum Clear Pulse Width
Vcc =5.0V
Vcc=10V
120
45
250
100
ns
ns
tr
Maximum Clock Rise Time
Vcc =5.0V
Vcc=10V
15
5.0
450
125
I'S
I'S
tf
Maximum Clock Fall Time
Vcc=p·OV
Vcc=10V
15
5.0
50
50
I'S
I'S
fMAX
Maximum Clock Frequency
Vcc- 5.OV
Vcc=10V
2.0
5.0
3.5
10
MHz
MHz
CIN
Input Capacitance
Clear Input (Note 2)
Any Other Input
10
5.0
pF
pF
Cpo
Power Dissipation Capacitance
Per Package (Note 3)
130
pF
Propagation Delay Time to a Logical
"0" or Logical "1" from Clock to Q
ora
tpd
tpd
45
16
ns
ns
-11
-4
ns
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: CpO determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family
Characteristics application note AN-90.
-
Switching Time Waveforms
CMOS to CMOS
--1"1-90"
v"
CLOCK
ov
toJ
50%
,j"r
DATA
90%
10%
1£%
ve:Jf90%
ov 10"
"I.
50%
50%
,,',
DATA
QDR
i'1
'H'
V~91\:
OV-i"~%
Vee
f.[
50%
50"
10"
-i.,
"'-IPdl--/SrWt
OV
Vee
OOR iI
I
tH,1
'--'.,.-\'''
OV
I.: 1,'" ZO n5
TUF/5900-5
6·89
~r---------------------------------~-------------------------------'
en
....
~National ..
~:E ~ Semiconductor
-.... MM54C192/MM74C192 Synchronous 4·Bit Up/Down
:E
en
.~
~
:E
:E
sf
....
Decade Counter
MM54C193/MM74C193 Synchronous 4·Bit Up/Down
Binary Counter
~
Features
:E General Description
:E
i....
These up/down counters are monolithic complementary
MOS (CMOS) iritegrated circuits. The MM54C192 and
MM74C192 are BCD counters, while the MM54C193 and
MM74C193 are binary counters.
:E
Counting up and counting down Is performed by two
count inputs, one being held high while the other is
clocked. The outputs change on the positive·going
transition of this clock.
~:E
1 V guaranteed
• High noise margin
drive 2 LPTTL loads
• Tenth power TTL compatible
3Vto 15V
• Wide supply range
• Carry and borrow outputs. for N-bit cascading
• Asynchronous clear
0.45 Vce (typ.)
• High noise Immunity
These counters feature preset inputs that are set when
load is a logical "0" and a clear which forces all outputs
to "0" when it is at a logical "1". The counters also have
carry and borrow outputs so that they can be cascaded
'
using no external Circuitry.
Connection Diagram
Dual·ln-Line Package
INP~TS
INPUTS
OUTPUTS
,......--.---. ,......--.---.
D~TA
I"
ClEAR BORROW CARRY
"
13
14
LOAD
DATA
C
11
12
10
,
Order Number MM54C192J,
MM74C192J, MM54C193J or
MM74C193J
See NS Package J16A
rOrder Number MM54C192N,
MM74C192N, MM54C193N or
MM74C193N
,
DATA
B
INPUT
1
Ila
,
~
__________
OUTPUTS
\
,
4
COUNT
DOWN
See NS Package N16E
•
Oc:
COUNT
UP
7
DD
~
I
I'
GND
OUTPUTS
INPUTS"
TOP VIEW
TlIFI5901·1
Cascading Packages
Guaranteed Noise Margin as
A Function of Vee
>__-------
LOAO--.....- - - - - - -....
15V
.-:::======;;---,
13.'
12.5
U.
CLOCK
TO NEXT
STAGE
DOWN
CLOCK
•.OS
,.OS
1.45
OA.
OUTPUTS
LV§"~"~'
~~~~~~ •.•1.5
~
'-----'-----'
4.SOV
OUTPUTS
CLEAR--.....-------~>__-------
6-90
TL./FI5901-2
IOV
15V
TL/F/5901·3
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
MMS4C1S4
MM74C1S4
Storage Temperature Range
(Note 1)
-SS·C to +12S·C
-40·C to +BS·C
-6S·C to +1S0·C
DC Electrical Characteristics
Symbol
Maximum Vee Voltage
Package Dissipation
Operating Vee Range
Lead Temperature (Soldering, 10 sec.)
-0.3 V to Vee+0.3 V
1BV
SOOmW
3Vto 1SV
300·C
Minimax limits apply across temperature range unless otherwise noted
Parameter
Conditions
Min
Typ
Max
Units
CMOS to CMOS
3.S
B.O
VIN (1)
Logical "1" Input Voltage
Vee=S.OV
Vee=10V
VIN(O)
Logical "0" Input Voltage
Vee=S.OV
Vee=10V
VOUT(')
Logical "1" Output Voltage
Vee = S.OV, 10=-10,..A
Vee = 10V, 10 = -10,..A
VOUT(O)
Logical "0" Output Voltage
Vee = 5.0 V, 10=+10,..A
Vee = 10V, 10 =+10,..A
IIN(')
Logical "1" Input Current
Vee =1SV, VIN =1SV
IIN(O)
Logical "0" Input Current
Vee=1SV, VIN=OV
Icc
Supply Current
Vee=1SV
V
V
1.S
2.0
4.S
9.0
V
V
O.OOS
-1.0
V
V
O.S
1.0
V
V
1.0
,..A
-O.OOS
0.05
,..A
300
,..A
CMOS to LPTTL Interface
VI~(')
Logical "1" Input Voltage
S4C
74C
Vee =4.SV
Vee = 4.7SV
VIN(O)
Logical "0" Input VOltage
S4C
74C
Vee=4.SV
Vee =4.7SV
VOUT(')
Logical "1" Output Voltage
S4C
74C
Vee=4.SV, 10=-100,..A
Vee =4.7SV,10=-100,..A
VOUT(O)
Logical "0" Output Voltage
S4C
74C
Vee=4.SV, 10 = 360,..A
Vee=4.7SV, 10 = 360,..A
V
V
Vee- 1.S
Vee- 1.S
O.B
O.B
2.4
2.4
V
V
V
V
0.4
0.4
V
V
Output Drive (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
IsouReE
Output Source Current
IsouReE Output Source Current
Vee = 5.0V, VIN(O)=OV
TA =2S·C, VOUT=OV
-1.7S
mA
Vee = 10 V, VIN(O) = 0 V
TA =2S·C, VOUT=OV
-B.O
mA
ISINK
Output Sink Current
Vee = S.O V, VIN(') = S.O V
TA =2S·C, VOUT = Vee
1.7S
mA
ISINK
Output Sink Current
Vee = 10 V, VIN(') - 10 V
TA =2S·C, VOUT=Vee
B.O
mA
,
6·91
,AC Electrical Characteristics
TA=25°C, CL =50pF, unless otherwise noted.
Typ
Max
Units
250
100
120
50
120
50
100
30
300
120
100
40
300
120
120
35
4
10
400
160
200
80
200
80
160
50
480
190
160
65
480
190
200
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
15
5
I's
I's
pF
pF
5
100
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Cpo determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family
Ch'aracteristlcs application note AN-gO.
Timing Diagrams
CLEAR-- 1l1--'-1
MM54C193/MM74C193
MM54C192/MM74C192
CLEAR-Ill=:;-;===============
LDAD-
I--H
LDA'-:-
'ATAl:~ r-:;::================ 'ATAI:,~ ~~~~_=_= =_:~_-~_'~_~_=_= =_=~_~_~~_=~~~
;~ ~~~~~~~~~~~~~~~~~~
I' -
COUNT
DOW
': : .-,. . . .
r-...,,--,,--,
Ilc
-I
:=t-t-
"':- I-BOAROW
SEQUENCE
I
L..r--
L.----I
O/U1l'U11
'
13
'-'
1,--,,--,
::=~ If-r--,'-' '-' ~=~
Dc ::t- H
_,
15
0
I
2
I
II .15
14
Clelr outputs to zero.
Lo.d(preset)tobinBrythimen.
Count lip to fourteen, fifteen, ~Irrv,zero. one .nd two.
Count doWII to one, zero, borroww, flhaen, fourteen, .nd thirteen.
I
U
1
6oRRow--H-H--t------1--t---,
o
1
8
9
0
I
2
I
0
13
ILL~~~!~;~
r----COUNT OOWN-
TLiF/5901-4
CLEAR
PRESET
---COUNTUP____
9
'8
7
r-COUNTDOWN-
NOlfl: CII.fOUtputsto'zlfo.
NOli II: Lo.d(Pmtt)to 8CDsrftll.
NObill: Counl upto eight.,lIine,Clrry,zero,cme, Ind two.
Nata IV: COllnt dl1Wll to ODe, zero, borrow, nine, eight, ami seven.
NOTE A: Cleafoverrideslo.d.d.h,.ndcountinputs.
NOTE B. When counting up, count down input nnln b. high; when couDtinl down, count·up input must bl high.
6-92
rr-
.r---Lr-
',-
14
r-
'-'r'-
--~t-
CARRV
lliAR PRESET f----- COUNT UP - Note I:
Natali:
Note III:
Note IV:
r--...,',--,,--,
DOIW' - -
u
o
~~
COUNT
I
CARRY
ILLUSTRATED
r -
~~h '-'~
L---...J
.J
1,--,,--,
~-===============
cau~~..rLrULIU
LJ1..n..J1..nI-
I
-i
:::~rl--
OUTPUTS
-~
lIUlSUlJ
cou~~
TLlFI5901-5
3:
3:
Schematic Diagrams
U1
~
o....
MM54C192 Synchronous 4-Bit Up/Down Decade Counter
CD
N
CARRY OUT
3:
3:
~
o....
CD
~N
3:
3:
U1
b
....
CD
Co)
Vcc!-J
TLlF15901·6
8
~GND
3:
3:
~
o....
CD
Co)
MM54C193 Synchronous 4-Bit Up/Down Binary Counter
vcx:~
TLlF/5901·7
8
~GND
6·93
II)
~ ~ National
.
~:E ~ Semiconductor
:E
i
p
~:E
:E
MM54C195/MM74C195 4-Bit Registers
General Description
Features
The MM54C195/MM74C195 CMOS 4-blt registers feature
parallel inputs, parallel outputs, J-K serial Inputs, shift/
load control input and Ii direct overriding clear. The following two modes of operation are possible:
• Medium speed operation
Parallel Load
Shift in direction Q A towards QD
Parallel loading Is accomplished by applying the four bits
of data and taking the shift/load control of input low. The
data is loaded into the associated flip-flops anr;! appears
at the o·utputs after the positive transition of the clock input. During parallel loading, serial data flow is Inhibited.
Serial shifting is accomplished synchronously when the
shlftlload control input is high. Serial data for this mode
is entered at the J-K inputs. These Inputs allow the first
stage to perform as a J-K, 0, or Hype flip flop as shown
In the truth table.
•
•
•
•
•
•
•
•
•
•
•
8.5MHz (typ.) with 10V
supply and 50pF load
0.45 Vcc (typ.)
100nW(typ.)
drive 2 LPTTL loads
3Vt015V
High noise immunity
Lowpower
Tenth power TTL compatible
Supply voltage range
Synchronous parallel load
Parallel Inputs and outputs from each flip-flop
Direct overriding clear
J and K Inputs to first stage
Complementary outputs from last stage
Positive-edge triggered clocking
Diode clamped Inputs to protect against static charge
Applications
•
•
•
•
Automotive
Data terminals
Instrumentation
Medical electronics
•
•
•
•
Alarm systems
Remote metering
Industrial electronics
Computers
Schematic and Connection
Diagrams
'\
.
,
ClOCK
CLEAR
o-.!--~====::::+=±:::::+:..j~-L-~~...l.-+--I-...J
SHIFT/LOAD~
...
PIN. TO GNO
PIN l&TD V<;c:
..
c
TUFI5902·,
Dual·ln-Line Package
TUFI59Q2·2
Order Number MM54C195J or
MM74C195J
See NS Package J16A
Order Number MM54C195N or
MM74C195N
See NS Package N16E
6·94
Absolute Maximum Ratings
"Voltage at Any Pin
Operating Temperature Range
MM54C195
MM74C195
Storage Temperature Range
(Note 1)
-0.3 V to Vee + 0.3 V
-55·C to +125·C
-40·C to +S5·C
-65·C to +150·C
DC Electrical Characteristics
Symbol
500mW
3.0Vto 15V
1SV
300·C
Package Dissipation
Operating Vee Range
Absolute Maximum Vee
Lead Temperature (Soldering, 10 sec.)
MinImax limits apply across temperature range unless otherwise noted
Parameter
Conditions
Typ
Min
Max
Units
CMOS to CMOS
VIN(1)
Logical "1" Input Voltage
Vee =5.0V
Vee=10V
VIN(O)
Logical "0" Input Voltage
Vee =5.0V
Vee=10V
VOUT(1)
Logical "1" Output Voltage
VOUT(O)
Logical "0" Output Voltage
IIN(1)
Logical "1" Input Current
Vee- 15V
IIN(O)
Logical "0" Input Current
Vee- 15V
Icc
Supply Current
Vee- 15V
V
V.
3.5
S.O
1.5
2.0
V
V
4.5
9.0
Vee =5.0V
·Vee = 10V
V
V
Vee- 5.OV,
Vee = 10V
0.005
1.0
0.5
1.0
V
V
1.0
IJA
300
IJA
0.005
IJA
0.05
CMOS/LPTTL Interface
VIN(1)
. Logical "1" Input Voltage
54C
74C
Vee=4.5V
Vee =4.75V
VIN(O)
Logical "0" Input Voltage
54C
74C
Vee=4.5V
Vee =4.75V
VOUT(1)
Logical "1" Output Voltage
54C
74C
Vee=4.5V, 10--36O IJA
Vee=4.75V,10=-360IJA
VOUT(O)
Logical "0" Output Voltage
54C
.74C
Vee=4.5V, 10 = 360"A
Vee = 4.75 V, 10 =360"A
V
Vee -1.5
Vee -1.5
v
O.S
O.S
2.4
2.4
V
V
V
V
.
0.4
0.4
V
V
Output Drive (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
'lsouReE Output Source Current
Vee = 5.0 V, VIN(O)=OV
TA = 25·C, VOUT = 0 V
-1.75
mA
ISouReE Output Source Current
Vee =10V, VIN(O)=OV
TA =25·C, VOUT=OV
-S.O
mA
ISINK
Output Sink Current
Vee = 5.0 V, VIN (1) = 5.0 V
TA = 25·C, VOUT = Vee
1.75
mA
ISINK
Output Sink Current
Vee -10V, VIN(1)-10V
TA = 25·C, VOUT = Vee
S.O
mA
Truth Table
Guaranteed noise Margin as
a Function of
INPUTS AT
J
K
to
15V
OUTPUTS AT tn+1
aA
aB
aC
00
00
L
H
OM
G An
GS "
aCo
L
L
L
GAil
as"
CCn
OCr>
H
H
H
G An
GSn
Q Cn
Qcn
H
L
GAn
OAn
a sn
Oen
OCn
4.05
3.05
US
GUARANTEED OUTPUT "O"lEVEL
Your (0)@INPUTS = VIN (1)
.
'-".
=~
4.S0V
IOV
V"
6-95
13.5
12.5
(1)
V,.IDI__....,
1.45
Note. H - HIGH lEVEL. L LOW LEVEL
'n - blilime before clock pulse
'ntl bit time afler clock puis!'
QAn . State of QA at t"
~
VIN
aCo
Vee
GUARANTEED OUTPUT "1" LEVel
2.S
I.S
15V
TL/F/5902-3
•
AC Electrical Characteristics
Sym
TA = 25'C. CL = 50 pF. unless otherwise noted.
Typ
Max
Units
tpd
Propagation Delay Time to a Logical "0" or
Logical "1" from Clock to Q or 0
Vcc=5.0V
Vcc=10V
150
75
300
130
ns
ns
tpd
Propagation Delay Time to a Logicar"O" or
Logical "1" from Clear to Q or <:I
Vcc=5.0V
Vcc=10V
150
50
300
130
ns
ns
ts
Time Prior to Clock Pulse that Data must be
Present
Vcc =5.0V
Vcc=10V
80
35
200
70
ns
ns
ts
Time Prior to Clock Pulse that Shift/Load must
be Present
Vcc~5.0V
Vcc= 10V
110
60
150
90
ns
ns
tH
Time After Clock Pulse that Data must be Held
Vc c =5.0V
Vcc=10V
-10
-5.0
0
0
ns
ns
tw
Minimum Clear Pulse Width (tWL=twH)
Vcc=5.0V
Vcc=10V
100
50
200
100
ns
ns
tw
Minimum Clear Pulse Width
Vcc=5.0V
Vcc=10V
90
40
130
60
ns
ns
tr• tf
Maximum Clock Rise and Fall Time
Vc c =5.0V
Vcc=10V
5.0
2.0
2.0
5.5
Parameter
Conditions
(
f MAX
Maximum Input Clock Frequency
Vcc -5.0V
Vcc=10V
C IN
Input Capacitance
Cpo
Power Dissipation Capacitance
Min
I'S
1'8
3.0
8.5
MHz
MHz
(Note 2)
5.0
pF
(Note 3)
100
pF
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation ..
Note 2: Capacitance is guaranteed by periodic .testing.
Note 3: Cpo determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family
Characteristics application note AN-gO.
Switching Time Waveforms
TTL to CMOS
CMOS to CMOS
Vee
CLUCK
OV
,:~1"~~t-
Vc~
"t:_
DATA
90%
&0%
10%
OV
Vee
,
90%
DATA
10%
OV
_~It
'''-Jtt
.
90%
.50J'>
.
90\\
10%
OV
's,
'H ,
Is 0
IH 0
I,
90%
1.5V
~I'
1<..,
~.
IH 0
4.0V
90%
10%
--l
10%
1.5V
ts 1
Is 0
50%
50%
10%
1.1__
OV
Co
~1"~
4V
90%
10%
90%
L
OV
1.5V
10%
I,~
1.5V
90%
ID%.,jl
--1 t,
4.0V
Vee
I---t....,
Qodi
50%
OV
OV
Vee
4.0V
r----- ',.,
Qodi
OV
tr
'"
r--- '""
OV
tl" 20n$
1--'-'''''
I.5V
t,::' tf "'20ns
TLlFI5902-4
TUFf5902·5
6·96
~National
Z1II Semiconductor
MM54C200/MM74C200 256-Bit TRI·STATE®
Random Access Read/Write Memory
General Description
The MM54C200/MM74C200 is a 256-bit random access
read/write memory. Inputs consist of eight address lines
and three chip enables. The eight binary address inputs are
decoded internally to select each of the 256 locations. The.
internal address register, latches, and address information
are on the positive to negative edge of CE3. The TRI·STATE
data output line, working in conjunction with CE 1or CE2 in·
puts, provides for easy memory expansion.
Address Operation: Address inputs must be stable tSA
prior to the positive to negative transition of ~. It is
therefore unnecessary to hold address information
stable for more than tHA after the memory is enabled
(positive to negative transition).
Holding either CE1, CE2, orCE3 at a high level forces the
output into TRI·STATE. When used in bus·organized sys·
tems, CE:1, or CE2, a TRI·STATE control provides for fast
access' times by not totally disabling the chip.
Write Operation: Data is written into the memory with
CE3 low and WE low. The state of CE1 or CE2 has no
effect on the write cycle. The output assumes TRI·STATE
with WE low.
Features
Note: The timing is different from the DM74200 in that a
positive 10 negative transition of the CE3 must occur for
the memory to be selected.
Read Operation: The data is read out by selecting the
proper address and bringing CE3 low and WE high.
•
•
•
•
Wide supply voltage range
Guaranteed noise margin
High noise immunity
TTL compatibility
• Low power
• Internal address register
3.0Vt015V
1.0V
0.45 Vee (typ.)
fan out of 1
driving standard TTL
500 nW (typ.)
Logic and Connection Diagrams'
ADDRESS
IIII'UTD
TRI.sTAT£
ADDRESS
INPUTC
ADDRESS
INPU' ,
III
ADDIIESS
INPUT A
Dual·ln·Llne Package
E::~
__ ____________ __ __
~
DA~::_+
~
~
~--~~-L--L-~-L~--~~
____________+ __+-__-./
ADDRESS 1
INPUT A
ADDRESS 2
IN,UtB
15 ADDRESS
.,
INPUTC
_
3
CE,
-CE,
-CE,
X·DECODER
'6 Vee
DATA
14 ADDRESS
INPUTH
13 DATA IN
~
12 WAITE
ENABLE
11 ADDRESS
INPUlG
10 ADDRESS
6
OUT
ADDRESS 7
INPUlD
GND I
2S1·BIT
INPUTF
9 ADDRESS
IN,UI£
TOP VIEW
MEMORY ARRAY
TLIFI5903-2
'Order Number MM54C200J or
M'M74C200J
See NS Package J16A
Order Number MM54C200N or
MM74C200N
See NS Package N16E
nIF/5903-1
6·97
Absolute Maximum Ratings
,
Voltage at Any Pin
Operating Temperature Range
MMS4C200
MM74C200
Storage Temperature Range
(Note 1)
-0.3 V to Vcc + 0.3 V
-SS·C to +12S·C
-40·C to +8S·C
-6S·C to +1S0·C
DC Electrical Characteristics
Symbol
I
500mW
3.0Vto 1SV
18V
300·C
Min/max limits apply across temperature range unless otherwise noted
I
Parameter
CMOS to CMOS
Package Dissipation
Operating Vcc Range
Absolute Maximum Vee
Lead Temperature (Soldering, 10 seco'nds)
I
Conditions
VIN (l)
Logical "1" Input Voltage
Vee=S.OV
Vee =10V'
VIN(O)
Logical ".0" Input Voltage
Vee- S.OV
Vee = 10V
VOUT(1)
Logical "1" Output Voltage
Vc e=S.OV,lo=-10,..A
Vcc =10V,lo=-1O,..A
VOUT(O)
Logical "0" Output Voltage
Vee=S.OV,l o =+10,..A
Vee=10V, io =+10,..A
iIN (l)
Logical "1" Input Current
Vee = 1SV, VIN = 1SV
IIN(O)
Logical "0" Input Current
Vee=1SV, VIN=OV
Icc
Supply Current
Vec=1SV
Min
I
Typ
I
Max
3.S
8.0
V
V
1.S
2.0
4.S
9.0
V
V
V
V
O.OOS
-1.0
I Units
O.S
1.0
V
V
1.0
,..A
-O.OOS
0.10
,..A
600
,..A
CMOS/TTL Interface
VIN (l)
Logical "1" Input Voltage
S4C
74C
Vee=4.SV
Vee=4.7SV
VIN(O)
Logical "0" Input Voltage
S4C
74C
Vee=4.SV
Vee=4.7SV
VOUT(1)
Logical "1" Output Voltage
S4C
74C
Vce=4.SV, lo=-1.6mA
Vcc =4.7S,lo=-1.6mA
VOUT(O)
Logical "0" Output Voltage
S4C
74C
Vee=4.SV, 10=1.6mA
Vee=4.7S,l o =1.6mA
Vee- 1.S
Vee- 1.S
V
V
0.8
0.8
2.4
2.4
V
V
V
V
0.4
V
Output Drive (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
ISOURCE
Output Source Current
(P-Channel)
Vce = 5.0 V, VOUT=OV
TA =2S·C
-4.0
-1.8
-6.0
mA
inA
IsouReE
Output Source Current
(P-Channel)
Vec=10V, VOUT=OV
TA =2S·C
-16.0
-1.S
-25
mA
mA
ISINK
Output Sink Current
(N-Channel)
Vee = 5.0 V, VOUT = Vee
TA =2S"C
5.0
B.O
mA
ISINK
Output Sink Current
(N-Channel)
Vee = 10 V, VOUT - Vee
TA=·C
20
30
mA
,r
I
\
.
6·98
AC Electrical Characteristics
Parameter
Sym
TA =25 G C, CL =50pF, unless otherwise specified.
Typ
Max
Units
tACC
Access Time from Address
Vcc =5.0V
Vcc=10V
Conditions
Min
450
200
900
400
ns
ns
tpd
Propagation Delay from CE3
Vc c -5.0V
Vcc=10V
360
120
700
300
ns
ns
tpCE1 Propagation Delay from CE 1 or CE2
Vcc =5.0V
Vcc=10V
250
85
700
200
ns
ns
tSA
Address Setup Time
Vcc =5.0V
Vcc=10V
200
100
80
30
ns
ns
tHA
Address Hold Time
Vcc=5.0V
Vcc=10V
50
25
15
5.0
ns
ns
tWE
Write Enable Pulse Width
Vcc=5.0V
Vcc=10V
300
150
160
70
ns
ns
tCE
CE3 Pulse Widths
Vcc=5.0V
Vcc=10V
400
160
200
80
ns
ns
CIN
Input Capacity
COUT Output Capacity in TRI·STATE
Cpo Power Dissipation Capacity
Any Input (Note 2)
5.0
pF
(Note 2)
9.0
pF
(Note 3)
400
pF
C L =50pF
Sym
Parameter
Conditions
MM54C200
MM74C200
TA =-55°C to +125°C TA = -45"C to +85°C
Min
Max
Min
Units
Max
tACC
Access Time from Address
Vc c=5.0V
Vcc=10V
1200
520
1100
480
ns
ns
tpd
Propagation Delay from CE3
Vcc=5.0V
Vcc=10V
950
400
850
360
ns
ns
Propagation Delay from
VCC= 5.0V
Vcc=10V
650
300
600
275
ns
ns
tpdCE1
0E1 or CE2
tSA
Address Setup Time
Vcc= 5.0V
Vcc=10V
250
120
250
120
ns
ns
tHA
Address Hold Time
Vcc=5.0V
Vcc= 10V
100
50
100
50
ns
ns
tWE
Wiffii Enable. Pulse Width
Vcc= 5.0V
Vcc=10V
450
225
400
200
ns
ns .,
tCE
Disable Pulse Width
Vcc=5.0V
Vcc=10V
500
250
460
230
ns
ns
tHO
Data Hold Time
Vcc= 5.0V
Vcc=10V
50
25
50
25
ns
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Tempe(ature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Cpo determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Char·
acteristics application note, AN-gO.
6·99
III
Switching Time Waveforms
Read and Write Cycles Using CE3 ICE, = CE2 = logic 0)
r-----.. .
Vee
---~----------
--------------------OV
-t----+~-t_ t"A
r-----------------
ADDRESS
INPUT
Vee
'----------------OV
~---------Vee
' -______-J' _ _ _
~
___
OV
r-----Vee
OATA
IN
j
~---------J'--------OV
:=-v--------------\
--"
,
- TRI:sTm -
TRI·STATE
Vee
•
.
'------OV
TLlFI5903-3
Read and Write Cycles Using CE3 and CE, lor CE2)
/~-----------vee
\
1'-----'·-
---OV
r-~---~-----------Vee
-------------OV
--------------Vee
ADDRESS
INPUT
' - - - - - - - - - - - - OV
~---Vee
I
~
DATA
IN
' -________, _______ OV
. \\....-----J/o:ee
-y'ffi _______
. :___
-Vee
.
_________
TRI·STATE
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ OV
TRI·STATE
Note: Used for fast access time in bused systems.
6-100
TLIF/5903-4
~National
~ Semiconductor
MM54C221/MM74C221 Dual Monostable Multivibrator
General Description
The MM54C221/MM74C221 dual monostable multivibrator is a monolithic complementary MOS integrated circuit. Each multivibrator features a negative-transtiontriggered input and a positive-transit ion-triggered input,
either of which can be used as an inhibit input, and a
clear Input.
Pulse stability will be limited by the accuracy of external
timing components. The pulse width is approximately
defined by the relationship tW(OUT) '" CEXT R EXT • For
further information and applications, see AN-138.
Features
4.5Vto 15V
1.0V
0.45 Vee (typ.)
fan out of 2
driving 74L
• Wide supply voltage range
Once fired, the output pulses are independent of further
transitions of the A and B inputs and are a function of the
external timing components CEXT and REXT' The pulse
width is stable over a wide range of temperature and Vee.
• Guaranteed noise margin
• High noise immunity
• Low power TIL compatibility
Connection Diagrams
Dual-In-Line Package
VTC
1 R/rCEXT 1
CrT
15
l!4
16
,.
13
Timing "Component
Vee
~*'m t"'"
TO CEXT
TERMINAL
TO R/C EXT
TERMINAL
I~
TLiF/5904-1
IB
,n
1 eLR
2.
./'I' J'
2 CEXT
2 A/CEXT
GND
TOP VIEW
TlIF/59042
Order Number MM54C221J or MM74C221J
See NS Package J16A
Order Number MM54C221N or MM74C221N
See NS Package N16E
Truth Table
INPUTS
OUTPUTS
A
B
Q
Q
H
L
L
X
X
L
H
t
CLEAR.
X
H
X
L
H
X
X
L
L
H
H
L
t
H
j
H
SL
SL
""Lf"
""Lf"
6-101
j
=:.
=:
High I\!vel
Low level
Transition from low to high
'" TransitIOn from high to low
=:.
_JL : One high level pulse
L.r = One low level pulse
X'" Irrelevant
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
MM54C221
MM74C221
Storage Temperature Range
(Note 1)
-0.3 V to Vee + 0.3 V
-55·C to +125·C
' -40·C to +S5·C
-65·C to +150·C
.DC Electrical Characteristics
Symbol
500inW
4.5Vto15V
1SV
Package Dissipation
Operating Vee Range
Absolute Maximum Vee
REXT~ SO Vee (Q)
Lead Temperature (Soldering, 10 sec.)
300·C
Maximin limits apply across temperature range, unless otherwise noted.
Conditions
Parameter
Min
Typ
Max
Units
CMOS to CMOS
Logical "1" Input Voltage
Vee=5.0V
Vee=10V
VIN(O)
Logical "0" Input Voltage
Vee =5.0V
Vee='10V
VOUT(l)
Logical "1" Output Voltage
Vee=5.0V,lo=-1OI'A
Vee =10V,lo=-10I'A
VOUT(O)
Logical "0" Output Voltage
Vee=5.0V,lo=+1OI'A
Vee =10V, 10 = +10I'A
1.5
2.0
IIN(l)
Logical "1" Input Current
Vee = 15V, VIN =15V
IIN(O)
Logical "0" Input Current
Vee=15V, VIN=OV
Icc
Supply Current (Standby)
Vee = 15 V, REXT = 00,
01,02= Logic "0" (Note 3)
Icc
Supply Current
(During Output Pulse)
Leakage Current at R/CEXT Pin
V
V
3.5
S.O
VIN(l)
4.5
9.0
V
V
0.5
1.0
0.005
-1.0
V
V
,..A
I'A
300
I'A
15
mA
2.0
mA
0.Q1
Vee = 15 V, VeExT = 5.0 V
1.0
-0.005
0.05
Vee = 15V, 01 = Logic "1",
02 = Logic "0" (Figure 4)
Vee = = 5.0V, 01 = Logic "1 ",
, 02 = Logic "0" (Figure 4)
V
V
3.0
,..A
CMOS/LPTTL Interface
VIN(l)
Logical "1" Input Voltage
54C
74C
Vee=,,·5V
Vee = 4.75 V
VIN(O)
Logical "0" Input Voltage
54C
74C
Vee=4.5V
Vee=4.75V
VOUT(l)
Logical "1" Output Voltage
54C
74C
Vee=4.5V, 10=-36O I'A
Vee = 4.75 V, 1,0 = -36OI'A
VOUT(O)
Logical "0" Output Voltage
54C
74C
Vee=4.5V, 10 = 360 l'A
Vee = 4.75 V, 10 = 360l'A
V
V
Vee- 1.5
Vee-, 1.5
O.S
O.S
V
V
,V
V
2.4
2.4
0.4
0.4
V
V
Output Drive (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
IsouReE Output Source Current
,
(P·Channel)
Vee=5.0V
TA =25·C, VOUT=OV
-1.75
mA
IsouReE Output Source Current
(P·channel)
Vee=10V
TA = 25·C, VOUT = 0 V
-S.O
mA
ISINK
Output Sink Current
(N·channel)
Vee =5.0V
TA = 25·C, VOUT = Vee
1.75
mA
ISINK
Output Sink Current
(N·channel)
Vee=10V
TA = 2S·C, VOUT = Vee
S.O
mA
,
• .
6-102
.
AC Electrical Characteristics
Sym
Parameter
TA = 25°C, C L "" 50 pF, unless otherwise noted.
Conditions
Min
Typ
Max
Units
tpd A,B
Propagation Delay from Trigger
Input (A,B) to Output a,
Vee=5.0V
Vee=10V
250
120
500
250
ns
ns
tpd eL
Propagation Delay from_Clear
Input (Cl) to Output a, a
Vee - 5.OV
Vee=10V
250 "
120
500
250
ns
ns
ts
Time Prior to Trigger Input (A,B)
that Clear must be Set
Vee -5.0V
Vee=10V
150
60
50
20
ns
ns
tW(A,B)
Trigger Input (A,B) Pulse Width
Vee =5.0V
Vee=10V
150
70
50
30
ns
ns
tW(eL)
Clear Input (Cl) Pulse Width
Ve e =5.0V
Vee=10V
150
70
50
30
ns
ns
tW(OUT)
a or a Output
Vee = 5.0 V, REXT = 10 k,
CEXT=OpF
Vee = 10 V, REXT = 10 k,
CEXT=OpF
Vee = 15 V, REXT = 10 k,
CEXT=OpF
Vee = 5.0 V, .REXT = 10 k,
CEXT=1000pF (Fig. 1)
Vee -10V, REXT -10k,
CEXT =1000pF (fig. 1)
900
ns
350
ns
320
ns
a
Pulse Width
Vee = 15V, REXT= 10k,
CEXT =1000pF (Fig. 1)
Vee-5.OV, REXT-10k,"
(Fig. 2)
CEXT=0.1I'F
Vee = 10 V, REXT = 10 k,
(Fig. 2)
CEXT =0.1I'F
Vee = 15 V, REXT -10 k,
(Fig. 2)
CEXT =0.1I'F
RON
CIN
ON Resistance of Transistor
between R/CEXT to CEXT
Vee = 5.0 V (Note 4)
Vee = 10 V (Note 4)
Vee = 15 V (Note 4)
Output Duty Cycle
R = 10k, C = 1000pF
R=10k, C=0.1I'F
(Note 5)
Input Capacitance
R/CEXT Input (Note 2)
Any Other Input (Note 2)
.-
9.0
10.6
12.2
1'5
9.0
10
11
I'S
8.9
9.8
10.8
,..5
900
1020
1200
1'5
900
1000
1100
I'S
900
990
1100
,..S
50
25
16.7
150
65
45
Q
90
90
%
%
25
pF
pF
15
5.0
Q
Q
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note" 3: In Standby (Q = Logic "0") the power dissipated equals the leakage current plus Vee/REXT.
Note 4: See AN-138 for detailed explanation of RON.
Note 5: Maximum output duty cycle = REXT I REXT + 1000.
6·103
~ r---------------------------------------------------------------------------------------------------~
~
o
t!
:E
:E
-B
~
;,;
:E
:E
Typical Performance Characteristics
w
ffi
A
~
~
1.0
w
~lllvee~'5V~
~
S
" 0.6
'.8
~
e:.
Vcc=10V
Vee = 15V
0.4
0% Point pulse width:
At Vee" 5V.
Tw = 10.6p5
At Vee" lOV.
Tw:: lOps
At Vee;; 15V.
Tw " 9.Bps
~
fA =25 C
§
~::~ : ~~':F
~
~~. ~f§i~~~§~f§3
0.8
0.6
~
0.4 I-f-:i±tt::±::btjj;h'Vcc::
5V
-Vee lOV
!;:;!
98% of units
=
~
tlj=t~~~~j=~~~ttj=t:tj
0
o±prj::l:tj;j±tj::ttj
1.0
w
Percentageofunitswlthm '4%:
At Vee = 5V.
90% of units
At Vee = lOV, 95% of umts
At Vee:: 15V.
~ ~.2
'"
S8fEafE3
~::; : ;::.TpF
~++=~:t;tj=t::l:tj::ttj
T =25C
1-+++-I
-55
25
50
'25
'00
OUTPUT DUTV CYCLE (%) TlIF/5904-6
TA - AMBIENT TEMPERATURE ( C) TUFJ5904·S
Figure 4. Typical Power Dissipation
per Package
Figure 3. Typical Variation in
Output Pulse Width vs Temperature
Switching Time Waveforms
v" ----:"d-I
o
A INPUT
I-
90%,'
50%
10%
-
-11-~O%
1
'
50%
18%
'w. -
BINPUT
' -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
"--1
9O%~j
I- -
o
1_"
t;h,"'O%,.--------------...
50~.
58%
10%
~ 50%
10%
J-
'---'
Vee _ _f - -_ _ _- _
••'-rr--_--:::.,-d.-I I--- -1.b,,-r---1-_+-_ _
11
90%
CLEAR
o
o
50%
10%
_ "D'
_I "0'1:- - . ,,'
r--
ve:====~~+-~-J-+!r50-%-----.. ~50%
'500%%\
-
"D' \----;-'w'Dun
ee ------..
oV
o
-50%
'1
----1-
--tWIQUTI--
l,=tl=20n5
'
90%
50%
10%
:::::-'m-
,\s'l..5001_%_ _ _---J I
-I"~,, i-=-
r\50%
I
II'I..~,,_..___....J
l----r'
TL/F/5904-7
6-104
91% of umts
98% of Units
~National
~ Semicondvctor
.
MM54C240/MM74C240 Inverting
MM54C244/MM74C244 Non-Inverting
Octal Buffers and Line Drivers with TRI-STATE® Outputs
General Description
Features
These octal buffers and line drivers are monolithic
complementary MOS (CMOS) integrated circuits with TAl·
STATE outputs. These outputs have been specially de·
signed to drive highly capacitive loads such as bus·oriented
systems. These devices have a fan·out of 6 low power
Schottky loads. A high logic level on the output disable con·
trol input G makes the outputs go into the high impedance
state. For improved TIL input compatibility see MM74C941.
•
•
•
•
•
•
•
•
•
·Logic and Connection Diagrams
Wide supply voltage range (3V to 15V)
High noise immunity (0.45 Vee typ)
Low power consumption
High capacitive load drive capability
TAI·STATE outputs
Input protection
TIL compatibility
20'pln dual·in·line package
High speed 25ns (typ.) @ 10V, 50pF (MM74C244)
MM54C240/MM74C240 Dual·ln·Line Package
MM54C240/MM74C240
vcc
oDB
oA'
184
oA2
IB3
oA3
IB2
oA4
IBI
ooA
IAI
084
IA2
oB3
IA3
oB2
IA4
OBI
GND
CONTROLS ONE OF
EIGHT DEVICES
,-------:-1
CONTROLS FOUR OF
EIGHT DEVICES
I
Vec
rL ---· I
OUTPUT
DiSABlE
--- .......
I
I
I
I
I~~~~----IH--..
TOP VIEW
TL/F/5905-1
TLlF/5905-2
Order Number MM54C240J, MM74C240J,
MM54C240N or MM74C240N
See NS Package J20A or N20A
MM54C2441MM74C244 Dual·ln·Line Package
MM54C244/MM74C244
vcc
oDB
oAI
184
oA2
IB3
oA3
IB2
oA4
IB'
CONTROLS FOUR OF
EIGHT DEVICES
rL ---·
.><>-iH......;----'1cHHI ....
OUTPUT
DISABLE
--_ .......
DATA
INPUT
TUF/5905-3
TOP VIEW
TUF/S905-4
Order Number MM54C244J, MM74C244J,
MM54C244N or MM74C244N
See NS Package J20A or N20A
6·105
Absolute Maximum Ratings (Note 1)
Voltage at Any Pin
Operating Temperature Range
MM54C240, MM54C244
MM74C240, MM74C244
Storage Temperature Range
-0.3VtoVee +0.3V
Package Dissipation
500mW
3Vt015V
18V
300·C
, Operating Vee Range
Absolute Maximum Vee
Lead Temperature (Soldering, 10 seconds)
-55·C to + 125·C
-40·Cto +85·C
-65·Cto + 150·C
DC Electrical Characteristics Minimax limits apply across temperature range, unless otherwise noted.
Symbol
Conditions
Parameter
CMOS TO CMOS
.
VIN(1)
Logical "1" Input Voltage
Vee = 5.0V
Vee=10V
VIN(O)
Logical "0" Input Voltage
Vee =5.0V
Vee=10V
VOUT(1)
Logical "1" Output Voltage
Vee=5.0V, 10= -1OI'A
Vee =10V, 10= -1OI'A
VOUT(O)
Logical "0" Output Voltage
Vee =5.0V,10= 1O I'A
Vee = 10V, 10 = 10 I'A
loz
TRI·STATE Output Current
Vee =10V,OD=VIH
IIN(1)
Logical "1" Input Current
Vee = 15V, VIN =15V
IIN(O)
Logical "0" Input Current
Icc
Supply Current
Units
V
V
3.5
8.0
1.5
2.0
Vee = 15V, VIN=OV
V
V
V
V
4.5
9.0
0.5
1.0
0.005
-1.0
±10
I'A
1.0
I'A
-0.005
0.05
. Vee=15V
V
V
I'A
300
I'A
CMOS/LPTIL INTERFACE
V
V
VIN(1)
Logical "1" Input Voltage
54C, Vee =4.5V
74C, Vee = 4.75V
VIN(O)
Logical "0" Input Voltage
54C, Vee =4.5V
74C, Vee =4.75V
VOUT(1)
Logical "1" Output Voltage
54C, Vee = 4.5V, 10 = - 450 I'A
74C, Vee = 4.75V, 10 = - 450 I'A
Vee- 0.4
Vee- O.4
V
V
54C, Vee = 4.5V, 10 = - 2.2 mA
74C, Vee=4.75V, 10= -2.2 mA
2.4
2.4
V
V
VOUT(O)
Logical "0" Output Voltage
Vee -1.5
Vee -I.5
0.8
0.8
0.4
0.4
54C, Vce = 4.5V, 10 = 2.2 mA
74C, Vee = 4.75V, 10 = 2.2 mA
V
V
V
V
OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
ISOUReE
ISINK
.output Source Current
(P·Channel)
Output Sink Current
(N·Channel)
Vee = 5.0V, VOUT=OV
TA =25·C
-14.0
..
-30.0
mA
Vee =10V, VOUT=OV
T A =25·C·
-36.0
-70.0
mA
Vee=5.0V, VouT=Vec
TA = 25·C
12.0-
20.0
mA
Vec=IOV, VOllT=Vce
TA =25·C
48.0
70.0
mA
6·106
AC Electrical Characteristics TA=25°C, C L =50 pF, unless otherwise specified.
Symbol
t pd (1)' tpd(O)
Typ
Max
Units
Vee=5V. C L =50 pF
Vce= 10V. C L = 50 pF
Vee= 5V. C L = 150 pF
Vee= 10V, C L = 150 pF
60
40
80
60
90
70
110
90
ns
ns
ns
ns
Vee=5V, C L =50 pF
Vee= 10V, C L = 50 pF
Vee=5V, C L = 150 pF
Vee=10V,C L =150pF
45
25
60
40
70
50
90
70
ns
ns
ns
ns
Parameter
Conditions
Propagation Delay
(Data In to Out)
M M54C240/M M7 4C240
M M54C244/M M 74C244
Min
Propagation- Delay Output
Disable to High Impedance
State (from a Logic Level)
Ve~=5V
Vee= 10V
45
35
80
60
ns
ns
Propagation Delay Output
Disable to Logic Level
(from High Impedance State)
R L = 1k, C L =50 pF
V ee d5V
Vee= 10V
50
30
90
60
ns
ns
tT(HL)' tT(LH)
Transition Time
Vee=5V. C L =50 pF
Vee= 10V, C L =50 pF
Vee= 5V. C L = 150 pF
Vee= 10V. C L = 150 pF
45
30
75
50
80
60
140
100
ns
ns
ns
ns
Cpo
Power Dissipation
Capacitance
(Output Enabled Per Buffer)
M M54C240/M M7 4C240
M M54C244/M M7 4C244
t 1H, tOH
tHl, tHO
RL = 1k, C L =50 pF
(See Note 3)
(Output Disabled Per Buffer)
M M54C240/M M 74C240
M M54C244/M M 74C244
100
100
pF
pF
10
0
pF
pF
CIN
Input Capacitance
(Any Input)
VIN=OV. f=iMHz. TA =25'C
10
pF
Co
Output Capacitance
(Output Disabled)
VIN=OV. f=1MHz. TA=25°C
10
pF
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Range" they
are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: CPD determines the n'o load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics appli·
cation note, AN·9O.
Typical Application
CONTROL OR MICROPROGRAM ROM/PROM
OR
MEMORY ADDRESS REGISTER
~M;wtt
I
MM74C244
OUTPUT
DISABLE
~
L __
~
rtR ~-rY.tYRR-'
I
~
-- -- -_.- -- --
I--
SYSTEM AND/OR MEMORY ADDRESS BUS
6-107
_. __ J
J
OUTPUT
DISABLE
TLlF/5905-5
Truth Tables
MM54C240/MM74C240
ODA IA
ODB IB
OA
X
Z
X
Z
0
1
0
1
1
0
0
1
1
1
0
0
OB
X
Z
X
Z
0
1
0
1
MM54C2441MM74C244
ODA IA
1
OA
1
X
Z
1
X
Z
0
0
6
0
1
'1
ODB IB
1
1
0
0
OB
X
Z
X
Z
0
0
1
1
~High
o ~Low
X == Don't Care
Z
~ TRI·STATE
Typical Performance Characteristics
N·Channel Output Drive
@ 25°C
120
~
100
P·Channel Output Drive
@ 25°C
0
~~15V
-10
".5....
1/
80
".5"
E'"
Vec -10V
'I
VVCC ~ 5V
20
0
-40
~
"'"::0a:
-50
0
-60
12
Vec = 15
~
15
VOUT IV)
9
12
J
6
TLiF/5905-7
MM54C240/M M7 4C240
Propagation Delay Vs.
Load Capacitance
MM54C244/MM74C244
Propagation Delay Vs.
Load Capacitance
150
150
!
oS
>-
--
100
"c
;:
;;
~
c
g:
0
VCC - VOUT (V)
TLIF/S905·6
~
C>
,
II I
-80
15
-1
" 1/
VCC = loV
-100
9
6
!-'
If
-90
3
I
5V
V
-10
1i:
I
~
-JO
ffi
a:
60
40
Vee
-20
-
50
>
g
~
-
I
C
s-
vec
~
100
~
;:
'"'"~
10V
r
~
c
VCC- 1
s-
o
0
0
50
100
150
0
CL - LOAD CAPACITANCE (pF)
~
------
50
I
~
VCC'j15V
50
100
150
CL - LOAD CAPACITANCE (pF)
TLIFI5905-9
TLIFI5905-8
6·108
AC Test Circuits and Switching Time Waveforms
CMOS to CMOS
Vee--------i-~~------------~~
0.1
DV-----"
VINo--(>o--rVOUT
'-t
vee_tP~1
~eL~5DPF
VOUT
TLIF15905-10
\0%
5Df
OV---------------~---------------J
TL/FJ5905·11
Vee
DISABLE
INPUT-Q--r-r0UTPUT
OISABLE-
lL~lk
DV
TeL"oPF
':"
Jo.
.,.-----------
-
I
--1
-=-
DISABLE
5v ee
vee
0.5 Vee +
DV
Hl
tlH
VOH -------,I
VOH
OUTPUT
OUTPUT
TLiF/5905-12
DV
~
D.5VOH
-------------=---
I
DV
TLlF/5905-13
Note: VOH is defined as the DC output high voltage when the device is loaded
with a 1 kO resistor to ground.
gJ.
vee •
RL 1k
DISABLE
vceT
0.5 Vee
DISABLE
ov
INPUT
OUTPUT
DISABLE
T e L ~50pF
OUTPUT
veek
Vee
0.5
OV
~~
vee~
--r-
TlIF/5905·14
VOL
0.1 IVee - VOL)
tHO
Vee---------"""">1-:--~-OUTPUT
VOL---------------......- -
TL/F/5905·15
Note: VOL is defined as the DC output low voltage when the device is loaded
with a 1 kll resistor to VCC.
Note: Delays measured with input t r • tf" 20 ns
6-109
~
~ National
~ ~ Semiconductor
(W)
MM54C373/MM74C373 TRI-STATE® Octal D-Type Latch
~ MM54C374/MM74C374 TRI-STATE Octal D-Type Flip-Flop
::E
~::E
::E
~
~
(J
::::t
:-=
:;
-=
C;;
~
II)
....
::E
::E
General Description
Features
The MM54C373/MM74C373, MM54C374/MM74C374 are
integrated, complementary MOS (CMOS), 8-bit storage
elements with TRI-STATE outputs_ These outputs have
been specially designed to drive highly capacitive loads,
such as one might find when driving a bus, and to have
a fan-out of 1 when driving standard TTL_ When a high
logic level is applied to the OUTPUT DISABLE input, all
outputs go to a high impedance state, regardless of
what signals are present at the other inputs and the
state of the storage elements_
• Wide supply voltage range
The MM54C373/MM74C373Is an 8-bit latch_ When LATCH
ENABLE is high, the Q o·utputs will follow the D Inputs_
When LATCH ENABLE goes low, data at the D inputs,
which meets the set-up and hold time requirements, will
be retained at the outputs until LATCH ENABLE returns
high again.
• Eight storage elements in one package
3.0Vt015V
0.45 Vee (typ.)
• High noise immunity
• Low power consumption
fan-out of
1 driving standard TTL
• TTL compatibility
• Bus driving capability
• TRI-STATE outputs
• Single CLOCK/LATCH ENABLE and OUTPUT DISABLE
control Inputs
• 20-pln dual-in-line package with 0.300" centers takes
half the board space of a 24-pln package
The MM54C374/MM74C374 is an a-bit, D-type, positiveedge triggered flip-flop. Data at the D inputs, meeting the
set-up and hold lime requirements, Is transferred to the Q
outputs on positive-going transitions of the CLOCK input.
Both the MM54C373/MM74C373 and the MM54C3741
MM74C374 are being assembled in 20-pin dual-in-line
packages with 0.300" pin centers.
Connection Diagrams
MM54C373/MM74C373
Dual-In-Line Package
MM54C374/MM74C374
Dual-In-Line Package
OUTPUT
OISABLE
Vcc
Vcc
01
DB
01
DB
01
08
01
H---F--08
02
01
02
H--+,--01
02
01
02
01
03
06
03
06
03
H--oF--06
04
05
04
H--~-05
DS
04
D&
04
GNO
LAi'CH
11
10
D&
GNO
ENABLE
TOP VIEW
CLOCK
TOP VIEW
TLIF/5906·'
TLrF/5908·2
Order Number MM54C373J or MM74C373J
See NS Package J20A
Order Number MM54C374J or MM74C374J
See NS Package J20A
Order Number MM54C373N or'MM74C373N
See NS Package N20A
Order Number MM54C374N or MM74C374N
See NS Package N20A
6-110
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
MM54C373
MM74C373
Storage Temperature Range
(Note 1)
-55·C to +125·C
-40·C to +85·C
-65·C to +150·C
DC Electrical Characteristics
Symbol
500mW
3Vto 15V
18V
300·C
Package Dissipation
Operating Yee Range
Absolute Maximum Vee
Lead Temperature (Soldering, 10 sec.)
-0.3 V to Vee + 0.3 V
Minimax limits apply across temperature range unless otherwise noted
Parameter
Conditions
Min
Typ
Max
Units
CMOS to CMOS
VIN(1)
Logical "1" Input Voltage
Vee =5.0V
Vee = 10V
VIN(O)
Logical "0" Input Voltage
Vee =5.0V
Vee=10V
VOUT(1)
Logical "1" Output Voltage
Vee = 5.0 V, 10=-1OI'A
Vee = 10 V, 10 = -1OI'A
VOUT(O)
Logical "0" Output Voltage
Vee = 5.0 V, 10=+1OI'A
Vee=10V,lo=+10I'A
IIN(1)
Logical "1" Input Current
Vee = 15V, VIN = 15V
IIN(O)
Logical "0" Input Current
Vee = 15V, VIN=OV
loz
TRI-STATE Leakage Current
Icc
Supply Current
Vee = 15V, Vo=15V
_ Vee = 15V, Vo=OV
-
3.5
8.0
V
V
1.5
2.0
4.5
9.0
V
V
V
V
0.005
0.5
1.0
V
V
1.0
I'A
-1.0
-0.005
1.0
-1.0
0.005
-0.005
I'A
I'A
0.05
300
I'A
Vee=15V
I'A
CMOSILPTTL Interface
Vee -1.5
Vee -1.5
V
V
VIN(1)
Logical "1" Input Voltage
54C
74C
Vee=4.5V
Vee=4.75V
VIN(O)
Logical "0" Input Voltage
54C
74C
Vee =4.5V
Vee=4.75V
VOUT(1)
Logical "1" Output Voltage
54C
74C
Vee=4.5V, 10=-36OI'A
Vee = 4.75 V, 10 = -36OI'A
vee -o.4
V
V
54C
74C
Vee = 4.5V, 10=-1.6mA
Vee=4.75V,10-1.6mA
2.4
2.4
V
V
54C
74C
Vee=4.5V, 10= 1.6mA
Vce=4.75V,lo=1.6mA
VOUT(O)
Logical "0" Output Voltage
0.8
0.8
Vee- 0.4
0.4
0.4
V
V
V
V
Output Drive (Short Circuit Current)
IsouReE Output Source Current
Vec = 5.0V, VOUT=OV
TA =25·C (Note 4)
IsouReE
Output Source Current
Vee =10V, VOUT=OV
TA=25·C (Note 4)
ISINK
Output Sink Current
(N-Channel)
ISINK
Output Sink
(N·Channel)
Cur~ent
-12
-24
mA
-24
-48
mA
Vee = ~.O V, VOUT = Vee
TA =25·C (Note 4)
6.0
12
mA
Vee = 10 V, VOUT = Vee
TA=25·C (Note 4)
24
48
mA
6-111
•
AC Electrical Characteristics
MM54C373/MM74C373 TA = 25°C, CL = 50pF, tr = t, = 20ns, unless otherwise notedo
Symbol
Conditions
Parameter
Min
Typ
Max
Units
tpdO, tpd1
Propagation Delay, LATCH ENABLE
to Output
Vee = 500 V, CL =50pF
Vee"" 10V, CL = 50pF
Vee = 500 V, CL =150pF"
Vee =10V, CL =150pF
165
70
195
85
330
140
390
170
ns
ns
ns
ns
tpdo, tpd1
Propagation Delay Data In to Output
LATCH ENABLE = Vee
Vee=500V, CL=50pF
Vee = 10V, CL = 50pF
Vee = 500 V, CL = 150 pF
Vee = 10V,.CL = 150pF
155
70
185
85
310
140
370
170
ns
ns
ns
ns
tHoLO=Ons
Vee =500V
Vee=10V
70
35
140
70
ns
ns
tSET-UP
fMAX
Minimum Set-Up Time Data In to
CLOCK/LATCH ENABLE
Maximum LATCH ENABLE
Frequency
305
405
Vee=500V
Vee=10V
607
900
MHz
MHz
tPWH
Minimum LATCH ENABLE Pulse
Width
Vee=500V
Vee=10V
75
55
t r, tf
Maximum LATCH ENABLE Rise and
Fall Time
Ve e =500V
Vee=10V
NA
NA
t1H, tOH
Propagation Delay OUTPUT
DISABLE to High Impedance State
(from a Logic Level)
RL = 10k, CL = 5pF
Vee =500V
Vee=10V
105
60
210
120
ns
ns
Propagation Delay OUTPUT
DISABLE to Logic Level
(from High Impedance State)
RL = 10k, CL =50pF
Vee =500V
Vee=10V
105
45
210
90
ns
ns
Vee 500 V, CL =50pF
Vee = 10V, CL =50pF
Vee = 500 V, C L = 150pF
Vee = 10V, C L = 150pF
65
35
110
70
130
70
220
140
ns
ns
ns
ns
tH1' tHO
tTHL, tTLH Transition Time
=
150
110
ns
ns
I'S
I's
CLE
Input Capacitance
LE Input (Note 2}
705
10
pF
COD.
Input Capacitance
OUTPUT DISABLE Input
(Note 2)
705
10
pF
C'N
COUT
Input Capacitance
Any Other Input (Note 2)
500
705
pF
Output Capacitance
High Impedance State
(Note 2)
10
15
pF
CPO
Power Dissipation Capacitance
Per Package (Note 3)
200
.'
-
6 0112
pF
AC Electrical Characteristics
MM54C374/MM74C374 TA=25 D C, CL=50pF, t r =tf=20ns, unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
300
130
360
160
ns
ns
ns
ns
tpdO, tpdl
Propagation Delay, CLOCK to
Output
Vee=5.0V, CL =50pF
Vee = 10V, CL =50pF
Vee = 5.0 V, CL =150pF
Vee = 10V, CL = 150 pF
150
65
180
80
tSET·UP
Minimum Set-Up Time Data In to
CLOCK/LATCH ENABLE
tHOLO = Ons .
Vee =5.0V
Vee=10V
70
35
140
70
ns
ns
Vee =5.0V
Vee=10V
70
50
140
100
ns
ns
tpWH,tpWL Minimum CLOCK Pulse Width
3.5
5.0
MHz
MHz
7.0
10
f MAX
Maximum CLOCK Frequency
Vee=5.0V
Vee=10V
tlH, tOH
Propagation Delay OUTPUT DISABLE
to High Impedance State
(from a Logic Level)
RL =10k, CL=50pF
Ve e=5.0V
Vee=10V
105
60
210
120
ns
ns
Propagation Delay OUTPUT DISABLE
to logic Level
(from High Impedance State)
RL=10k, CL =50pF
Vee=5.0V
Vee=10V
105
45
210
90
ns
ns
tTHL, tTLH
Transition Time
Vee=5.0V, C L =50pF
Vee = 10V, CL = 50pF
Vee = 5.0 V, CL = 150pF
Vee =10V,C L =150pF
65
35
110
70
130
70
220
140
ns
ns
ns
ns
tr,tf
Maximum CLOCK Rise and Fall Time
Vee = 5.0 V
Vee = 10 V
CeLK
Input Capacitance
CLOCK Input (Note 2)
7.5
10
pF
Coo
Input Capacitance
OUTPUT DISABLE Input
(Note 2)
7.5
10
pF
C IN
Input Capacitance
Any Other Input (Note 2)
5.0
7.5
pF
COUT
Output Capacitance
High Impedance State
(Note 2)
10
15
pF
Cpo
Power Dissipation Capacitance
Per Package (Note 3)
250
tHl, tHO
15
5.0
!,s
!,s
>2000
>2000
pF
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Cpo determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family
Characteristics application note AN-90.
Note 4: These are peak output current capabilities. Continuous output current is rated at 12mA max.
6-113
Typical Performance Characteristics
MM54C373/MM74C373
Propagation Delay, LATCH
ENABLE to Output vs Load
Capacitance
MM54C373/MM74C373
Propagation Delay, Data I n to Output
vs Load Capacitance
~
z
200
VCC - 5V
>-
VCC - 5V
;::
~
~
100
'"go
Vcc -loV
C>
100
VCF - lOV
!!r
nil
0
0
0
50
100
.,
'"
!!r
--+VCC-15 V
0
50
100
TUFI5908-5
MM54C373/MM74C373,
MM54C374/MM74C374 Output
Source Current vs VCC - VOUT
0
:;;
..s
'"z
~
0.25
60
VCC - 10V
. '"
-50
vEd
-60
. VCC - 5V
-70
II
0
15
j
[I
0
10
~ -40
g;
II
40
10
5
..s
Vec -10V
50
20
0
Vee' 5V
-20
:;; -3D
30
~
,I
-10
80
70'
0
150
100
'CL - LOAD CAPACITANCE (pFI
Vee -15V
90
0.5
50
0
100
c
'"
c
!i
Vcc-lOV
150
MM54C373/MM74C373,
MM54C374/MM74C374
Output Sink Current vs VOUT
0.75
5
~
100
1'UF!5906-4
w
~
~
VCC' 5V
CL - LOAO CAPACITANCE (pFI
TLIFI5906·3
MM54C373/MM74C373,
MM54C374/MM74C374
Change in Propagation Delay per pF of
, Load Capacitance (L'.tPD/pF) vs Power
Supply Voltage
~
~:v~Cj 115V
0
150
CL -LOAD CAPACITANCE (pFI
zoo
I
'"
V1cc-15V
'"z
'"
~
~
I
I
..."5
~
200
C>
;::
~
!
Joo
:g
.s>
iii
i
MM54C374/MM74C374
Propagation Delay, CLOCK to Output
vs Load Capacitance
Joo
Joo
.s>
~
TA=25°C
2
4
-80
6
Vec - POWER SUPPLY VOLTAGE (VI
8
10
12
14
16
16
14
12
VOUT (VI
10
8
6
4
2
0
Vce - VOUT (VI
Tllf/5906-8
TL./FI5906·7
TL/F/5906·6
Truth Tables
MM54C374/MM74C374
MM54C373/MM74C373
OUTPUT
DISABLE
L
LATCH
ENABLE
H
L
.H
D
Q
OUTPUT
DISABLE
.H
H
L
~
H
,H
L
L
L
~
L
L
CLOCK
D
Q
L
H
X
= low logic level
= high logic level
= irrelevant
......r-=
Q
Q
L
L
X
Q
L
L
X
H
X
X
Hi,Z
L
H
X'
.Q
H
X
X
Hi·Z
Hi-Z
low to high logic level transition
= preexisting output level
= high impedance output state
Typical Applications
I
Simple, Latching, Octal, LED Indicator Driver with Blanking
For Use As Data Display, Bus Monitor,
IlP Front Panel Display. Etc.
Data Bus I nterfacing Element
BLANKING
CONTROL
~
...,r--
TRI·STATE DATA BUS
MM54"'3I
MM74C37J
OR'
MM54CJ74/
MM74C314
"'r
~
I
""<.7
,,(.7
PERIPHERAL DEVICE
I
TL/F/59Q6..9
.
DATA
1.
,
--
01
0'
D3
04
00
T
.
MM54C373/1
MM74C37J
OR
MM54C314/
MMl4C314
0----,
-
_
--
6·114
Vec
MM54CJ7JI
MM7:~J73
05
MMS4C374!
06
MM74CJ74
07
DB
CLKfU GND
o--J
CONTROL
ClOCKING/LATCHIN~
v¥
~
01
0'
03
..
05
06
07
08
~ ~~ ~~ ~~ ~~ t~ ,1I~ r:-'
.".
.".
.".
.".
.".
.".
.".
.". TL/F/S90610
Logic Diagrams
MM54C373/MM74C373 (1 of B Latches)
ii
G
-L..
---t>o--Lt>J
D
OUTPUT
DISABLE
00
-L..
-I~f-,-
-II:£-,-
T
f
ii
TLIF/5906·11
MM54C374/MM74C374 (1 of B Flip-Flops)
CLoCK
OUTPUT
DISABLE
~CL
.
~OD
CL
CL
-L..
-1~!-,-
--L-
-IiI-,-
CL
CL
T
f
TLIF159()6.12
TRI·STATE Test Circuits and Switching Time Waveforms
VCC
OUTPUT
DISABLE
VCC
OUTPUT
DISABLE
Q :::
OUTPUT
GNO
--1-"-1=""':-·-9D%
50%
-=CJ-:~IH
~
---------==
tHl-
1;-
-----1'50%
TLlF15906-14
TL/f/5906·13
tHO. CL = 50 pF
DUTPUT
DISABLE
GNO
OH
OUTPU~
vcc
-~
10%
VOL
TUF15908-15
TL/FJ5906-16
6-115
Switching Time Waveforms
MM54C373/MM74C373
DATA
IN
GND
VCC
LATCH
ENABLE
GND
OUTPUT DISABLE
= GND
TLIF/5906·17
MM54C374/MM74C374
DATA
IN
GND
CLOCK
GNO
VCC
Q
. OUTPUT
GND
OUTPUT DISABLE
=
GND
TLIFI5906·18
6·116
~National
~ Semiconductor
MM54C901/MM74C901 Hex Inverting TTL Buffer
MM54C902/MM74C902 Hex Non-Inverting TTL Buffer
MM54C903/MM74C903 Hex Inverting CMOS Buffer
MM54C904/MM74C904 Hex Non-Inverting CMOS Buffer
General Description
Features
These hex buffers employ complementary MOS to
achieve wide supply operating range, low power consumption, and high noise immunity. These buffers provide direct interface from PMOS Into CMOS or TTL and
direct interface from CMOS to TTL or CMOS operating
at a reduced Vcc supply. For specific applications see
MOS Brief 18 in the back of this catalog.
• Wide llupply voltage range
3.0Vto 15V
1.0V
• Guaranteed noise margin
0.45 Vcc (typ.)
• High noise immunity
• TTL compatibility
fan out of 2
driving standard TTL
Connection and Logic Diagrams
Dual-ln·Line Package
Dual·ln-Line Package
MM54C901/MM74C901
MM54C902/MM74C902
MM54C903/MM74C903
MM54C904/MM74C904
rO'VIEW
'"
'"
TLIFI5909-2
TLlF15909-1
Order Number MM54C901J, MM74C901J,
MM54C903J, MM74C903J, MM54C901N,
MM74C901N, MM54C903N or MM74C903N
See NS Package J14A or N14A
Order Number MM54C902J, MM74C902J,
MM54C904J, MM74C904J, MM54C902J1/,
MM74C902N, MM54C904N or MM74C904N
See NS Package J14A or N14A
MM54C901/MM74C901
CMOS to TTL Inverting Buffer
MM54C903/MM74C903
PMOS to TTL or CMOS Inverting Buffer
MM54C902/MM74C902
CMOS to TTL Buffer
MM54C904/MM74C904
PMOS to TTL or CMOS Buffer
6-117
_/
Absolute 'Maximum Ratings
Voltage at Any Pin
Voltage at any Input Pin·
MM54C901/MM74C901
M M54C902/MM74C902
MM54C903/MM74C903
MM54C904/MM74C904
Storage Temperature Range
Package Dissipation
(Note 1)
-0.3 V to Vee + 0.3 V
-0.3Vto+15V
-O.3Vto+15V
Vee -17Vto Vee +0.3V
Vee -17V to Vee + 0.3V
-65·C to +150·C
500mW
DC Electrical Characteristics
Symbol
I
Parameter
CMOS to CMOS
VIN(l)
VIN(O)
VOUT(l)
VOUT(O)
IIN(l)
IIN(O)
Icc
Operating Temperature Range
MM54C901, MM54C902,
MM54C903, MM54C904
MM74C901, MM74C902,
MM74C903, MM74C904
Operating Vee Range
Absolute Maximum Vee
Lead Temperature (Soldering, 10 sec.)
Logical "1" Input Voltage
Logical "0" Input Voltage
Logical "1" Output Voltage
Logical "0" Output Voltage
Logical "1" Input Current
Logical "0" 'Input Current
Supply Current
-55·C to +125·C
-40·9 to +85·C
3.0Vto 15V
laV
300·C
Minimax limits apply across temperature range unless otherwise noted
I
Conditions
Ve e=5.0V
Vee=10V
Vee =5.0V
Vee=10V
Vce = 5.0 V, 10 = -lOI'A
Vee =10V, 10= -lOI'A
Vee=5.0V,
Vee = 10V
Vee - 15 V, VIN -15 V
Vee -15V, VIN-OV
Vee- 15V
I
'IIIin
I
Typ
I
Max
3.5
8.0
1.5
2.0
4.5
9.0
1.0
0.005
0.005
0.05
0.5
1.0
1.0
15
I
Units
V
V
V
V
V
V
V
V
,..A
,..A
,..A
TTL to CMOS
VIN (1)
Logical "1" Input Voltage
54C
74C
Vee=4.5V
Vee =4.75V
VIN(Q)
Logical "0" Input Voltage
54C
74C
Vee=4.5V
Vee =4.75V
Vee -l.5
Vec -1.5
V
V
0.8
0.8
V
V
CMOS to TTL
VIN(l)
VIN(O)
VOUT(l)
VOUT(O)
Logical "1" Input Voltage
MM54C901, MM54C903
MM54C902, MM54C904
MM74C901, MM74C903
Mrvi74C902, MM74C904
Logical "0" Input Voltage
MM54C901, MM54C903
MM54C902, MM54C904
MM74C901, MM74C903
MM74C902, MM74C904
Logical "1" Output Voltage
Logical "0" Output Voltage
MM54C901, MM54C903
MM54C902, MM54C904
MM74C901, MM74C903
MM74C902, MM74C904
4.0
Vee- 1.5
4.25
Vee -1.5
Vee =4.5V
Vee =4.5V
Vee=4.75V
Vee =4.75V
Vee ",4.5V
Vee =4.5V
Vee =4.75V
Vee =4.75V
54C Vee- 4.5V, 10 --800,..A
74C Vee = 4.75 V, 10 = -BOO,..A
Vee=4.5V,
Vee=4.5V,
Vee = 4.75V,
Vee = 4.75 V,
V
V
V
V
1.0
1.5
1.0
1.5
V
V
V
V
V
V
0.4
0.4
0.4
0.4
V
V
V
V
2.4
2.4
10=2.6mA
10=3.2mA
10=2.6mA
10=3.2mA
Output Drive (See 54C/74C f'amily Characteristics Data Sheet) (Short Circuit Current)
(MM54C901/MM74C901, MM54C903/MM74C903)
0utput Source Current
IsouReE (p·Channel)
Output Source Current
IsouReE (P-Channel)
Output Sink Current
ISINK
(N'Channel)
Output Sink Current
ISINK
(N·Channel)
Vee = 5.0V, VOUT=OV
TA = 25°C, VIN=OV
Vee =10V, VOUT=OV
. TA = 25°C, VIN=OV
Vee = 5.0V, VOUT = Vee
TA = 25°C, VIN = Vee
Vee = 5.0 V, VOUT = 0.4 V
TA = 25°C, VIN = Vee
6-118
-5.0
rnA
-20
mA
9.0
mA
3.8
mA
.
-....
.
....
.
i:
DC Electrical Characteristics (cont'd) Minimax limits apply across temperature range unless otherwise noted i:
Symbol
Parameter
Min
Conditions
Units
Max
Typ
Output Drive (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
(MM54C902lMM74C902, MM54C902/MM74C902)
Vee = 5.0V, VOUT =OV
TA = 25'C, VIN = Vee
Vee -10V, VOUT - OV
TA = 25'C, VIN = Vee
Vee = 5.0 V, VOUT = Vee
TA =25'C, VIN=OV
IsouReE Output Source Current (P-Channel)
IsoUReE Output Source Current (P-Channel)
ISINK
Output Sink Current (N-Channel)
ISINK
Output Sink Current (N-Channel)
Ac
Electrical Characteristics
Symbol
I
Vee - 5.0 V, VOUT - 0.4 V
TA = 25'C, VIN = OV
I
I
Conditions
MM54C901/MM74C901, MM54C903/MM74C903
tpd1
Propagation Delay Time to a Logical "1"
tpdO
Propagation Delay Time to a Logical "0"
C IN
Input Capacitance
Power Dissipation Capacity
Cpo
0
-5.0
mA
-20
mA
, 9.0
mA
3.8
mA
I
Typ
Max
Vee=5.0V
Vee=10V
Vee=5.0V
Vee = 10V
Any Input (Note 2)
(Note 3) Per Buffer
38
22
21
13
14
30
70
30
35
20
Vee =5.0V
Vee = 10V
Vee =5.0V
Vee=10V
Any Input (Note 2)
(Note 3) Per Buffer
57
27
90
40
90
40
I Units
ns
ns
ns
ns
pF
pF
Propagation Delay Time to a Logical "1"
tpdo
Propagation Delay Time to a Logical "0"
CIN
Cpo
Input Capacitance
Power Dissipation Capacity
54
25
5.0
50
ns
ns
ns
ns
pF
pF
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to Imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions' for actual device operation.
Note 2: Capacitance Is guaranteed by periodic testing.
Note 3: Cpo determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family
Characteristics application note AN-gO.
F
NOTE. Vee
~
Vee
IIDD .: 1111
0
I\)
i:
i:
~
0
CD
0
jIo)
.
.
.. [II
-.
..
.
i:
i:
0
CO
0
Co)
i:
s::
.....
(")
CO
0
~
:s:
i:
U1
CO
~~~
TTL
PMOS
~
:s:
U1
0
CMOS to TTL or CMOS at a Lower Vce
PMOS to CMOS or TTL Interface
•
i:
0
Typical Applications
J- y
"
0
U1
MM54C902lMM74C902, MM54C904/MM74C904
tpd1
(")
CD
CO
I
Min
i:
i:
.....
0
TA = 25'C, C L = 50 pF, unless otherwise noted.
Parameter
en
(")
CD
OR
CMOS
_\
~
GND
~+~
1T
Vee
Y
'"
OR
CMOS
--T--
':"
1··..C..'..:'4C..
-!.
-
NOTEVCC1_VCCJ
MM!i4C9041MM14C9Q4
TTL
CMOS
CMOS to CMOS
Vce
Y'"'
v,"
OY
TCL"SOPF
Y"
Note: Delays meil'Sured with mput t" I,
~
Y,~
20 ns.
OY
TLIF15909·9
~---
-"r
/.:''"
':"1 (
'"
-jooI-o:~
'"
01
~F
'"
TLIFI5909·10
6-119
(")
CO
\
TLIF/59098
AC Test Circuit and SWitching Time Waveforms
.....
TY'"
LIMM~c901IMM14CgOl
011
MMS4C9021MMJ4C902
TL/F/S909-7
y'"o--Vr
1
\"---T-
Vcc:.: ISV
i:
i:
0
Typical Performance Characteristics
Typical Propagation Delay to a
Typica' Propagation De'ay to a
Logica' "1" for the MM54C901/
MM74C901 and MM54C903/
MM74C903
Logica' "0" for the MM54C901/
MM74C901 and MM54C903/
MM74C903
250
I
226
I,,>l>~ 1-1-
200
~O9/
175
]
j.
V
150
125
./
100
1/
15
50
25
o
Voo· ,OV --:
Voo=15V
o
20 40 60 80100120140160180200
~
~ !;;;;
~
20 40 60 80 100120140160180200
c, (,F)
c, (,F)
Tl./F/59QS.12
TlIF/590S-11
Typical Propagation Delay to a
Logica' "0" for the MM54C902/
MM74C902 and MM54C904/
MM74C904
250
..I .3,O~
225
--
200
175
g
j.
150
~~
Typical Propagation Delay to a
Logica' "1" for the MM54C902/
MM74C902 and MM54C904/
MM74C904
250
..... f-
225
200
f-f--
175
125
100
]
150
j.
125
f-l-, ..~
,">'
~QQ
,
~~
100
75
50
o
20 40 60 80 lOU 120 140 160 lSD 200
V~)'0~ FoVoo '" 15V- r-
25
Voo -15V
o
t- I-
50
Voo':: 10V
25
Voo
75
Voo '" 5.0V
o
2040 6080 100120140160180200
c, (pF)
c, (,F)
TLIFI5909-14
TUF/5909·13
6·120
~National
~ Semiconductor
MM54C905/MM74C90512-Bit Successive Approximation
Register
General Description
The MM54C905/MM74C905 CMOS 12-bit successive
approximation register contains all the digit control and
storage necessary for successive approximation analogto-digital conversion_ Because of the unique capability
of CMOS to switch to each supply rail without any offset
voltage, it can also be used in digital systems as the
control and storage element in repetitive routines_
High noise immunlty
•
Low power TTL
com pati bili ty
fan out of 2
driving 74L
• Operates in START/STOP or continuous .conversion
mode
•
Drive ladder switches directly. For 10 bits or less
with 50k/100k R/2 R ladder network
3_0V to 15V
Connection Diagram
0.45' Vee typ
• Provision for register extension or truncation
Features
• Wide supply voltage range
1.0V
• Guaranteed noise margin
•
Dual-In-Line Package
v
Tce
N
0.11
NC
n
u
011
~
Q10
Q9
ro
08
01
a
~
"
n&
a
CP
NC
a
a
13
Order Number MM54C905J or
MM74C905J
See NS Package J24A
Order Number MM54C905N or
MM74C905N
See NS Package N24A
9
~
00
00
rn
~
v
M
~
10
~
,11
0
.lIZ
~D
TUF15910·1
Truth Table
TIME
INPUTS
OUTPUTS
o
X
4
5
10
11
12
13
14
011
.010
09
08
07
06
05
04
03
02
01
00
X
X
X
H
011
01.0
09
08
07
06
05
04
03
02
01
00
L
x
x
x
x
X
x
x
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
H
H
X
L
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
X
X
cc
DO
H
011
010
09
08
07
06
05
04
03
02
01
00
X
011
011
011
011
011
011
011
011
011
011
011
011
011
L
010
010
010
010
010
010
010
010
010
010
010
010
H
L
09
09
09
09
09
09
09
09
09
09
09
X
H
NC
NC
08
H
H
H
H
H
H
H
08
08
08
07
07
07
07
07
07
07
07
07'
06
06
06
06
06
06
06
06
L
05
05
05
05
05
05
05
04
04
03
03.
04
04.03
04
03
04
03
02
02
02
02
01
01
01
00
NC
NC
NC
NC
NC
NC
NC
NC
DB
08
08
08
08
DB
H"" High level
L = Law level
X.= Don't care
NC "" No change
6-121
NC
H
H
H
H
H
H
H
DO
NC
Absolute Maximum Ratings (Note 1)
Voltage at Any Pin
Operating Temperature Range
MM54CS05
MM74CS05
Storage Temperature Range
Package Dissipation
Operating Vee Range
Absolute Maximum Vee
Lead Temperature (Soldering, 10 seconds)
-0.3V to Vee + 0.3V
-55'Cto +125'C
-40'Cto +B5'C
-65'Cto +150'C
.,
500mW
3.0Vto 15V
16V
300'C
-
DC Electrical Characteristics
Minimax limits apply across temperature range unless otherwise noted.
Parameter
symbol.1
CMOS to CMOS
Conditions
1
VIN(1)
Logical "1" Input Voltage
Vee=5.0V
Vee=10V
VIN(O)
Logical "0" Input Voltage
Vee=5.0V
Vee=10V
,
1
Min
1
Typ
1 Max
3.5
B.O
V
V
1.5
2.0
VOUT(1)
Logical "1" Output Voltage
Vee =5.0V, 10 = -101'A
Vee =10V, 10= -1OI'A
VOUT(O)
Logical "0" Output Voltage
Vee = 5.0V, 10 = 1Ol'A
Vee = 10V, 10 = 10l'A
IIN(1)
Logical "1" Input Current
Vee = 15V, VIN = 15V
IIN(O)
Logical "0" Input Current
Vee = 15V, VIN = OV
Icc
Supply Current
Vee=15V
4.5
S.O
V
V
V
V
0.005
-1.0
1 Units
0.5
1.0
V
V
1.0
I'A
-0.005
0.05
I'A
300
I'A
CMOSILPTTL Interface
VIN (1)
VIN(O)
VOUT(1)
,
VOUT(O)
Logical "1" Input Voltage
MM54CS05
MM74CS05
Vee = 4.5V
Vee =4.75V
Logical "0" Input Voltage
MM54CS05
MM74CS05
Vee =4.5V
Vee =4.75V
Logical "1" Output Voltage
MM54CS05
MM74CS05
Vee=4.5V,10=-360I'A
Vee = 4.75V, 10 = -36OI'A
Logical "0" Output Voltage
MM54CS05
MM74CS05
Vee = 4.5V, 10 = 360l'A
Vee=4.75V, 10 = 360l'A
Vee -1.5
Vee -1.5
V
V
O.B
O.B
2.4
2.4
V
V
V
V
0.4
0.4
V
V
Output Drive (See 54C/74C Family Characteristics Data Sheet)
IsouReE
Output Source Current
(P-Channel)
Vee = 5.0V, VOUT = OV
TA = 25'C
-1.75
-3.3
mA
IsouReE
Output Source Current
(P·Channel)
Vee = 10V, VOUT = OV
TA = 25'C
-B.O
-15
mA
ISINK
Output Sink Current
(N-Channel)
Vee = 5.0V, VOUT = Vee
TA =25'C
1.75
3.6
mA
ISINK
Output Sink Current
(N·Channel)
Vee = 10V, VOUT = Vee
TA =25'C
Vee=10V±5%
B.O
16
mA
RsouReE
Q11-QO Outputs
VOUT = Vee - 0.3V
TA =25'C
RSINK
Q11-QO Outputs
Vee=10V±5%
VouT =0.3V
TA =25'C
6·122
150
350
Q
BO
230
Q
AC Electrical Characteristics TA=25°C, CL =50pF, unless otherwise specified.
Typ
Max
Units
tpd
Propagation Delay Time from
Clock Input to Outputs
(00-011) (tpd(Q»
Vcc=5.0V
Vcc=10V
200
80
350
150
ns
ns
tpd
Propagation Delay Time from
Clock Input to DO (tpd(DO»
Vcc=5.0V
Vcc=10V
180
70
325
125
ns
ns
tpd
Propagation Delay Time from
Register Enable (E) to Output
(011) (tpd(E»
Vcc =5.0V
Vcc=10V
190
75
350
150
ns
ns
tpd
Propagation Delay Time from
Clock to CC (tpd(CC»
Vcc=5.0V
Vcc=10V
190
75
350
0.50
ns
ns
ts
Data Input Set-Up Time
Vcc=5.0V
Vcc=10V
80
30
ns
ns
ts
Start Input Set-Up Time
Vcc=5.0V
Vcc=10V
80
30
ns
ns
tw
Minimum Clock Pulse Width
Vcc =5.0V
Vcc 10V
250
100
t r, tf
Maxlillum Clock Rise and Fall Time
Vcc= 5.0V
Vcc=10V
fMAX
Maximum Clock Frequency
Vcc= 5.0V
Vcc=10V
Parameter
Symbol
Conditions
Min
=:
125
50
ns
ns
15
5.0
2.0
5.0
CCK
Clock Input Capacitance
Clock Input (Note 2)
C IN
Input Capacitance
Any other Input (Note 2)
CpO'
Power Dissipation Capacitance
(Note 3)
"s
lIS
4.0
10
MHz
MHz
10
pF
5
pF
100
pF
Note 1: "Absolute Maximum Ratings" are Ihose values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Cpo determines the no load ac power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note - AN-90.
Typical Performance Characteristics
RSOURCE vs Temperature
RSINK vs Temperature
600
500
.•
-
~cc Lo.
600
r,5l
500
400
S
S
z
0:.
~
300
i
~~
200~
~
~
~
~
~
100
~
~
0:
400
300
200
100
_Lll++
...,...
0
-55 -35 -15 5
0
-55 -35 -15 5 25 45 65 85 105 125
~
~~
III
25 45 65 85 105 125
TA -AM8IENTTEMPERATURE I"CI
TA - AM81ENT TEMPERATURE ("CI
eThese points are guaranteed by automatic testing.
• These points ara guaranteed by automatic testing. '
TUFf5910·3
TL/F/5910·2
6-123
U).------------------------------------------------------------------------------------.
§
t!
:E
:E
Timing Diagram
CP
rgm
~:E
:E
-
E
011
--.-,
I
::-::J.L-__________________________
.o,o~
O.~~
OB=.=,]
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
LJ
Ul=:J
=-=--.J
06
05=.J
=--..-l
04
LJ
LJ
OJ~
02:..==J
0' =---::J
LJ
LJ
oo=.=.J
cc~
Do
TUF/5910-4
Switching Time Waveforms
v,, _ _ _",,"\
v,,-----------i----------+r-t-----.....
v,,-_ _ _ _--j-'-,
__ tpd_
~----_j_---_
011
v,,-------t~-r-------1~
010
'--_ _ _-t--t'·-Ir--'_
J
v"------------------------+---,-_____j_,,
Do
TLlF/5910·5
6-124
USER NOTES FOR AID CONVERSIO·N
The register can be used with either current switches
that require a low voltage level to turn the switch ON or
current switches that require a high voltage level to turn
the switch ON. If current switches are used which turn
ON with a low logic level, the resulting digit output from
the register is active low. That is, a logic "1" is represented
as a low voltage level. If ·current switches are used which
turn ON with a high logic level, the resulting digit
output is active high. A logic "1" is represented as a high
voltage level.
range +1/2 LSB and using the complement of the MSB
Q11 as the sign bit.
If the register is truncated and operated in the continuous conversion mode, a lock-up condition may oc~ur
on power-ON. This situation can be overcome by making
the START input the "OR" function of CC and the
appropriate register output.
The register, by suitable selection of register ladder
network, can be used to perform either binary or
BCD conversion.
For a maximum error of ±1/2 LSB, the comparator must
be biased. If current switches that require a high voltage
level to turn ON are used, the comparator should be
biased +1/2 LSB and if the current switches require a
low logic level to turn ON, then the comparator must be
biased -1/2 LSB.
The register outputs can drive the 10 bits or less with
.50k/100k R/2R ladder network directly for Vee ~ 10V
or ~igher. In order to drive the 12-bit 50k/100k ladder
network and have the ±1/2 LSB resolution, the
MM54C902/MM74C902 or MM54C904/MM74C904 is
used as buffers. three buffers for MSB (Q11), two buffers
for Ql0, and one buffer for Q9.
The register can be used to perform 2's complement
conversion by offsetting the comparator one half full
Typical Applications
12-Bit Successive Approximation A-to-D Converter, Operating in Continuous
Mode, Drives the 50kl100k Ladder Network Directly
12-Bit Successive Approximation A-to-O Converter
Operating in Continuous 8-Bit Truncated Mode
VRH -lDV~;=::;;t__________________f=::;--l
E
Vee
CP
011
0
S-
no
Do
ec
MM54C905/MM14CgaS
VA(F
-10V~;:+-
_________+::;-;;;-;;;;;;;:;;-]
-=-
.
MM54C905/MM14C90S
~
010
09
08
OJ
06
05
D~_~1/4MM54C]2
EVce
~~
CLOCK
CC
04
"' "
t:::::::)'
,UT
QATAOUT
~
~~,
lOOk
PARALLEL DATA OUT
lOOk
L___R~_"_LA_O_O'_"_--"~.
R-51ll<
l
DATA
PARALlEL
SERIAL
"i :;:"'c.'T·...:';:.'-"r:-'-:;"i-T",""':"r'-"r-'-:;'r'-' • OUT
c..::;UI,,-'Ul::.'
SERIAL
lOOk
1I4MM54C909
RlRlADDER
~~"'~_M_M~_e_90_9__~__________________________~
ANALOG INPUT-"""_-;
COMPARATOR
TLIF/59106
SOk
1/
ANAlOGtNPUT-""""'''''""---j
TUF15910·7
Definition of Terms
CP: Register clock input.
all: Complement of register MSB ourput_
cc:
Qi (i
Conversion complete-this
output remains at
VOUT (1) during a conversion and goes to VOUT(O) when
conversion is complete.
0: Serial data input-connected to comparator output in
A-to-D applications.
E: Register enable-this input is used to expand the
length of the register. When E is at V 1N (I) Ql1 is forced
to VOUT (IL and inhibits conversion. When not used for
expansion E must be connected to V1N(0) (GND)_
.
all: True register MSB output.
~
0 to 11): Register outputs.
S:
Start input-holding start input at V1N(0) for at least
one clock period will initiate a conversion by setting
MSB (Ql1) at VOUT(O) and all ,other output (Ql0-QO)
at VOUT (I)' If set-up time requirements are met, a conversion may be initiated by holding start input at V1N(0)
for less than one clock period.
DO: Serial data output-D input delayed by one clock
period.
6-125
'111
.....
~ ~ National .
~
Semiconductor
::E
~
a
MM54C906/MM74C906 Hex Open Drain N-Channel Buffers
MM54C907/MM74C907 Hex Open DrainP-Channel Buffers
2
::E
i
::E
::E
~;7;
:E
General Description
Features
These buffers employ monolithic CMOS technology
in achieving open drain outputs. The MM54C906/
MM74C906 consists of six inverters driving six N-channel
devices; and the MM54C907/MM74C907 consists of six '.
inverters driving six P-channel devices. The open drain
feature of these buffers makes level shifting or wire
AND and wire OR functions by just the addition of
pull-up or pull-down resistors. All inputs are protected
from static discharge by diode clamps to Vcc and to
ground.
• ' Wide supply voltage range
:E~
3.0V to 15V
1.0V
• Guaranteed noise margin
0.45 Vee (typ.)
• High noise immunity
• High current sourcing and sinking open drain outputs
________________________________________________~____~
Connection and Logic Diagrams
Dual-In-Line Package
Vee
TOP VIEW
TL/F/5911·1
Order Number MM54C906N, MM74C906N, MM54C907N
or MM74C907N
See NS Package N14A
Order Number MM54C906J, MM74C906J, MM54C907J
or MM74C907J
See NS Package J14A
MM54C906/MM74C906
MM54C9.07/MM74C907
Vee
~OUTPUT
"'''-i>o-i
"M-i>o-i,
d
~OUTPUT
TUFJ5911-3
TI..IFI5911·2
!6-126
Absolute Maximum Ratings (Note 1)
Voltage at Any Input Pin
Voltage at any Output Pin
MMS4C906/MM74C906
MM54C907/MM74C907
Operating Temperature Range
MMS4C906/MMS4C907
MM74C906/MM74C907
. -0.3VtoVee +0.3V
-6S·Cto +lS0·C
Storage Temperature Range
SOOmW
Package Dissipation
3.0Vto lSV
Operating Vee Range
18V
Absolute Maximum Vee
300·C
Lead Temperature (Soldering, 10 seconds)
-0.3Vto +18V
Vee -18 to Vee + 0.3V
-SS·Cto +12S·C
-40·Cto +8S·C
DC Electrical Characteristics
MinImax limits
Parameter
Symbol
CMOS to CMOS
I
I
apply,acro~s temperature range unless otherwise noted.
Conditions
VIN(1)
Logical "1" Input Voltage
Vee=S.OV
Vee=10V
VINIO)
Logical "0" Input Voltage
IIN(1)
Logical "1" Input Current
Vee=S.OV
Vee=10V
Vee =lSV, VIN=lSV
IINIO)
Icc'
Logical "0" Input Current
Supply Current
Output Leakage
MMS4C906
MM74C906
MMS4C907
MM74C907
I
Min
I
Typ
I
Max
3.S
8.0
Vee = lSV, VIN = OV
Vee = lSV, Output Open
V
V
1.S
2.0
V
V
1.0
,..A
lS
,..A
O.OOS
S
,..A
O.OOS
S
,..A
O.OOS
S
,..A
O.OOS
S
,..A
O.OOS
-1.0
I Units
-O.OOS
O.OS
,..A
.'
Vee=4.SV, VIN=Vee-1.S
Vee=4.SV, Vo uT =18V
Vee =4.7SV, VIN=Vee -l.S
Vee = 4.7SV, VouT=18V
Vee=4.SV, VIN=1.0V+0.1Vee
Vee=4.SV, VouT=Vee-18V
Vee = 4.7SV, VIN=1.0V+0.1Vee
Vee=4.7SV, VoUT =Vee -18V
CMOS/LPTTL Interlace
VIN(1)
Logical "1" Input Voltage
54C, Vee=4.SV
74C, Vee =4.7SV
VINIO)
Logical "0" Input Voltage
S4C, Vee=4.SV
74C, Vee =4.7SV
V
V
Vee- 1.S
Vee- 1.S
0.8
0.8
V
V
Output Drive Current
MMS4C906
MM74C906
MM74C907
MM74C907
.
MM54C906/MM74C906
MM54C907/MM74C907
Vee=4.SV, VIN=1.0V+0.1Vee
Vee=4.SV, VOUT=O.SV
Vee=4.SV, VouT=1.0V
2.1
4.2
8.0
12
mA
mA
Vee =4.7SV, VIN = 1.0V+ 0.1 Vee
Vee = 4. 7S V, VOUT = O.S V
Vee = 4.7SV, VOUT=1.0V
2.1
4.2
8.0
12
mA
mA
-1.0S
-2.1
-l.S
-3.0
mA
mAo
-1.05
-2.1
-1.5
-3.0
mA
mA
4.2
8.4
-20
-30
mA
mA
-2.1
-4.2
-4.0
-8.0
mA
mA
Vee=4.SV, VIN=Vee-1.SV
Vee=4.SV, VOUT=Vee-O.SV
Vee=4.SV, VouT=Vee-1.OV
Vee =.4.7SV, VIN = Vee -1.5V
Vec=4.75V, VouT=Vee-0.5V
Vee =4.7SV, VOUT=Vee- 1.OV
Vee = 10V, VIN = 2.0V
Vee=10V, VouT =0.5V
Vee = 10V, VOUT = 1.0V
Vee = 10V, VIN = 8.0V
Vee = 10V, VOUT = 9.5 V
Vee = 10V, VOUT = 9.0V
6·127
AC Electrical Characteristics TA = 25°C, C L = 50 pF, unless otherwise specified.
Symbol
tpd
MM54C907/MM74C907
tpd
Units
Vc~=5.0V, R=10k
Vcc =10V, R=10k
Vce = 5.0V, (Note 4)
Vee = 10V, (Note 4)
150
75
150+0.7RC
75+0.7RC
ns
ns
ns
ns
Vee = 5.0V, (Note 4)
Vee = 10V, (Note 4)
Vcc=5.0V, R=10k
Vcc = 10V, R = 10k
150+0.7RC
75+0.7RC
150
75
ns
ns
ns
ns
Conditions
Propagation Delay Time to a
Logical "0"
MM54C906/MM74C906
Propagation Delay Time to a
Logical "1"
MM54C906/MM74C906
MM54C907/MM74C907
CIN
input Capacity
COUT
Output Capacity
Cpo
Power Dissipation Capacity
Typ
Max
Parameter
Min
(Note 2)
5.0
pF
I(Note 2)
20
pF
30
pF
(Note 3) Per Buffer
Note 1: "Absolute Maximum Ratings'\ are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides 'conditions for actual device operatilln.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Cpo determines the no load ac power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note, AN-90. (Assumes outputs are open ,)
Note 4: "C" used in calClJlating propagation includes output load capacity (Cu plus device output capactly (COUT)'
Typical Applications
Wire AND Gate
Wire OR Gate
"[JJ. ~.
~j'.'.'
f
MM14C9D1
MM54C9061
MM74C906
.
Note: Can be extended 10 more than 2 IRputs.
Note: CanblutendedtomorlthanZinputs.
TL/F/591,·5
TL!F/59".4
CMOS or TTL to PMOS I "tarface
CMOS or TTL to CMOS at a Higher VCC
1 +J+l
I
T--
vcc ,"='
CMOS
TOT"l
GND
Ir--i1~~'"
MM;C9~'
MM14C'06
,
CMOS
T
-
V,C02
I
r4l_--...I
TUFI5911·7
TL/F15911-6
6-128
~National
~ Semiconductor
.MM54C909/MM74C909 Quad Comparator
General Description
Features
The MM54C909/MM74C909 contains four independent
bipolar voltage comparators designed to operate from
standard 54C/74C power supplies. The output allows
current sinking only, thus the wire OR function is pos·
sible using a common resistor pull·up.
• Wide supply voltage range
Not only does the MM54C909/MM74C909 function as a
comparator lor analog inputs, but also has many applica·
tions as a voltage translator and buffer when interfacing
the 54C/74C family to other logic systems.
• Low input offset current
input offset voltage
• Low
Large common mode
• input
voltage range
Large
• differential input voltage range
• TTL compatibility
3.0Vto 15V
fan out of 1 driving 74
lee = 8OO,..A (typ.)
at Vee = 5.0 Voe
250nAmax.
• Low power consumption
• Low input bias current
±50nAmax.
±5.0mVmax.
OVto Ve~-1.5V
Vee
Connection Diagram
Dual·ln·Llne Package
OUTPUT 3 OUTPUT 4
GND
INPUT 4+
I
INPUT 4-
INPUT 3"
INPUT 3-
14
Order Number MM54C909J or
MM74C909J
See NS Package J14A
Order Number MM54C909N or
MM74C909N
See NS Package N14A
OUTPUT 2
OUTPUT 1
V't
INPUT 1-
INPUT 1+
INPUT 2-
INPUT 2+
TOP VIEW
TLIF1591l-1
Typical Applications
(v+ = 5.0 V DC)
Ground Referenced Thermoucoupla
CMOS/TTL to MOS Logic Converter
in Single Supply System
v'
+5.DVoc
5.1.
100k
vo
TLIF/5913·2
TUF15913·3
6·129
Absolute Maximum Ratings
Voltage at My Pin
Operating Temperature Range
MM54C909
MM74C909
Storage Temperature Range
(lIIote 1)
Package Dissipation (Notes 2 and 3)
Operating Vee Range
Absolute Maximum Vee
Input Current (V IN < -{).3V) (Note 4)
Lead Temperature (Soldering, 10 seconds)
-0.3V to Vee + 0.3V
-55°C to +125°C
-40°C to +85°C
-65°C to +150°C
500 mW
3.0V to 15V
18V
50mA
300°C
DC Electrical Characteristics
Min/max limits apply across temperature range, unless otherwise noted. (Vee = +5.0 VDC)"
PARAMETER
CONDITIONS
MIN
TYP
MAX
±2 .
±9
±5
Input Offset Voltage INote 9)
TA
Input Bias Current'
TA
= 25°C
= 25°C, With
Output in
25
Linear Range
(I'NI+) Or I,NI-)) INote 5)
Input Offset Current
(I'NI+' - I,NI-))
TA
= 25°C
Input Common Mode Voltage
INote 6)
TA
= 25°C
±5
0
0
Supply Current (Icc)
TA - 25°C, RL
On All Outputs
Voltage Gain
TA
= 25°C,
RL
==
800
2 15 krl
200
UNITS
mV
mV
250
400
nA
nA
±150
±50
nA
nA
Vee 2
VeC1.5
V
V
2000
IJA
~ V/mV
OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet)
Output Sink Current (lsINK)
MM54C909
MM74C909
Vee
Vee
= 4.50V
= 4.75V,
V 'NH
V1N(l)
Output' Leakage Current
2
1.6
V OUT
3.2
rnA
= OAV
1.0 Voe
= 0 Voc
V1N(t) ~ 1.0 VOCI V 1N (_)
= 0 V oc ,
1
IJA
V OUT = 15 Voe
V IN (.)
V OUT
Oifferentiallnput Voltage (Note 8)
2' 1.0 Vae,
V 1NH = 0 V oc ,
nA
0.1
= 5 V oe , T A = 25"C
All Y,N'S
2
15
0 Voe
V
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: For operating at high temperatures, the MM74C909 must be derated based on +125°C maximum junction temperature and a thermal
resistance of +175~1C/W which applies to the device soldered in a printed circuit board, operating in a still air ambient. The MM54C909 must be
derated based on a +150°C maximum junction temperature. The low bias dissipation and the ON-OFF characteristic o{the outputs keeps the chip
dissipation very small (Pd < 100 mW), provided the output sink current is within specified limits.
Note 3: Short circuits fro; the output to V+ can cause excessive heating and eventual destruction. The maximum output current is approximately
20 mA independent of the magnitude of Vi.
Note 4: This input current will only exist when the voltage at any of the input leads is driven negative. There is a lateral NPN parasitic transistor
action on the IC chip. The transistor action can cause the output voltages of the comparators to go to the V+ voltage level (or to ground for a large
overdrive) for the time duration that an input is driven negative. This is not destructive and normal output states will reestablish when the input
voltage, which was negative, again returns to a value greater than -O.3V.
Note 5: The direction of the input curre~t is out of the IC. This current is essentially constant, independent of the state of the output so no loading
change exists on the reference or input lines.
Note 6: The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than O.3V. The upper end of
the common-mode voltage range is V+ - 1.5V, but either or both inputs can go ~o +15V without damage.
Note 7: The response time specified is for a 100 mV input step with 5.0 mV overdrive. For larger overdrive signals 3.00 os can be obtained, see
typical performance characteristics section.
Note 8: The positive excursions of the input can equal VCC supply voltage level, and if the other input voltage remains within the common·mode
voltage range, the comparator will provide a proper output state. The low input voltage state must not be less than -O.3V.
Note 9: At output switch point, Va = 1.4 VOC, RS = on with V+ from 5 VOC to 30 VOC and over the full input common mode range (OVDC)
to V+ ±1.5 VOCI.
6-130
AC Electrical Characteristics
RL = 5.1 kn, V RL = 5.0 V oc , unless otherwise specified.
PARAMETER
CONDITIONS
TYP
MIN
MAX
UNITS
Large Signal Response Time
V'N = TTL Swing
VAEF = l.4Voc
300
ns
Response Time
TA = 25°C (Note 7)!
1.3
lAS
Typical Performance Characteristics
Response Time for Various
Input Overdrives .... Positive
Transition
...
'"'"
I-
c:>
6
5
4
I- •
>",>
3
~
CI
2
1
...
100
> z
~>
50
0
~E
...
INPUT OVERDRIVE -100 mV
r".
I
'"'"
II
l-
c:>
>-
n 5mVI
'20mV
1 IIII
0
'"1->
"'CI_
"
Response Time for Various
Input Overdri ves - Negative
Transition
~~
~
"~=
,
1/:
-~
'"
::S
'".
,
f-r-~A'r~-
~E
CI-
> z
~>
I
!i
0
0.5
1
1.5
6.0
5.0
4.0
3.0
2.0
1.0
I
1f'=
5.0 mV" INPUT OVERDRIVE
.'2~
I
r~
100 mY
'~'-
,
-
0
I I I
I I I
0
-50
ii' l25-~I I
·100
2
0,5
0
TIME IjJsec)
I,D
1.5
2.0
TIMEwsec)
TL/FJ5913-4
TL.lFI5913.~
Application Hints
The MM54C909/MM74C909 is a high gain, wide bandwidth device; which, like most comparators, can easily
oscillate if the output lead is inadvertently allowed to
capacitively couple to the inputs via stray capacitance.
This shows up only during the output voltage transition
intervals as the comparator changes states. Power supply
bypassing is not required to solve this problem. Standard
PC board layout is helpful as it reduces stray input·
output coupling. Reducing the input resistors to < 10 kn
reduces the feedback signal levels and finally, adding
even a small amount (1 to 10 mV) of positive feedback
(hysteresis) causes such a 'rapid transition that oscilla·
tions due to stray feedback are not possible. Simply
socketing the I/C and attaching resistors to the pins will
cause input-output oscillations during the small transition intervals unless hysteresis is used. If the input
signal is a pulse waveform, with relatively fast rise and
fall times, hysteresis is not required.
It is usually unnecessary to use a bypass capacitor across
the power supply line.
The d'ifferential input voltage may be larger than V+
without damaging the device. Protection should be pro·
vided to prevent the input voltages from going negative
more than -{I.3 V oc (at 25°C). An input clamp diode
and input resistor can be used as shown in the applications section.
-
Many outputs can be tied together to provide an output
OR'ing function. An output "pull-up" resistor can be
connected to any available power supply voltage within
the permitted supply voltage range and there is no
restriction on this voltage due to the magnitude of the
voltage which is applied to the V+ terminal of the
MM54C909/MM74C909 package. The output can also
be used as a simple SPST switch to ground (when a
"pull-up" resistor is not used). The amount of current
which the output device can sink is limited by the drive
available (which is independent of V+) and the gain of
the output device. When the maximum current limit
is reached (approximately 16 mAl. the output transistor
will come out of saturation and the output voltage will
rise very rapidly.
All pins of any unused comparators should be grounded.
The bias network of the MM54C909/MM74C909 establishes an Icc current which is independent of the
magnitude of the power supply voltage over the range of
from 3.0V to 15V.
Typical Applications
(Continued) (V+ = 5.0 Vocl
Driving CMOS
Basic Comparator
Non·lnverting Comparator with Hysteresis
+S.OVoc
v'
Y'
"VIN 00-
7~
_MMl4C909
~ Vo
~~
~
~_
tVREFo--
TlIF/5913-ti
12
I
I
I
I
~
6-131
+VREF
10.
¥4MMS4CXX
'V IN
TlIF15913-7
I
[;>
3.0k
~vo
10M
TL.IF/S913-l1
Typic;:al Applications
(Continued) (V+ = 5.0 Vocl
Visible Voltage Indicator
Driving T!L
+5V DC
+SDV Dc
360
TLlFI591310
IDO
5V Logic to CMOS Operating at V CC '" 5V
~~
/J
r----1~--....- JV
50V
Vee' isv
HlDk
tV REF
J
100
CMOS DEVICE
v"
Note FormverllllgbuffelleversemputconnectlDn.
/-1''-;''
/J
TlIF15913·11
Inverting Comparator with Hysteresis
+VREF2
V'
IDO
Jk
1M
V'o--'II""~H
1M
1M
IDO
TLlFI59139
Hi Voltage Inverting PMOS to CMOS or TTL
R2
lOOk
R1
lOOk
51'
ANY CMOS OR
TTl DEVICE
TRIP POINT _ -Vee Rl
R2
Nnt~
For non
ulv~rtll1q
bllflpr reverse Input £onnectml1
TLlF15913·13
6·132
Typical Applications
(Continued) (V+
=
5.0 Voe!
Squarewave Oscillator
Crystal Controlled Oscillator
V·
V·
4Jk
lOOk
200k
V:JLf
20k
lOOk
1100kHz
V;I1S1
Vo
Vo
lOOk
lOOk
v' G--'I/'w....-....JW\r-_...J
IOllk
ZOOk
TLlF15913·14
TLlF15913·15
Two-Decade High-Frequency
veo
V·
lOOk
lOOk
30k
30k
51k
We
10
FREQUENCY
CONTROL
VOLTAGE
INPUT
OD1.F
01,.,F
> .....0-. . .-0 OUTPUT 1
T
10k
OUTPUT Z
10k
50k
V'!2
V+,,+3GV oc
+250 mVoc < Vc < +5D VDC
lOU Hi <'0 < 100 kHz
TLiF/5913·18
Pulse Generator
Remote.. Temperature Sensing
v+
V·
15Vocl
01
Rl
1M
15k
lN914
5.1k
lDk
4.3k
01
R1
lN914
lOOk
5DD
lN914
100
80pF
P
1M
1M
+15 Vee
G--'VII'v.....H
TL/FIS913-18
1M
1M
·For large ratios o. RlIR2,
01 can be omitted.
TlIF/5913·17
6·133
....O'-------~---------------------------------------------------------,
~ ~National
i ~ Semiconductor
:::E
o MM54C910/MM74C910 256 Bit TRI-STATE®
....
Random Access Read/Write lVIemory
~:::E
:E
General Description
,The MM54C910/MM74C910 is a 64 1I'!0rd by 4·bit random
access memory. Inputs consist of six address lines, four
data input lines, a WE, and a ME line. The six address lines
are internally decoded to select one of the 64 word loca·
tions. An internal address register latches the address in·
formation on the positive to negative transition of ME. The
TRI·STATE outputs allow for easy memory expansion.
Address Operation: Address inputs must be stable (tSA)
prior to the positive to negative transition of ME, and
(tHA) after the positive to negative transition of ME. The
address register holds the information and stable address
inputs are not needed at any other time.
Write Operation: Data is written into memory at the
selected address if WE goes low while ME is low. WE
must be held low for tWE and data must remain stable
tHO after WE returns high.
Read Operation: Data is nondestructively read from a
memory location by an address operation with WE held
high.
Outputs are in the TRI·STATE (Hi·Z) condition when the
device is writing or disabled.
Features
- Supply voltage range
3.0Vt05.5V
- High noise immunity
0.45 Vee (typ.)
- TTL compatible fan out
1 TTL load
- Input address register
- Low power consumption
250 nW/package (typ.)
(chip enabled or disabled)
- Fast access time
250 ns (typ.) at 5.0V
_ TRI·STATE outputs
_ High voltage Inputs
Logic and Connection Diagrams
o IfH
0 Dun DIN2
0 DUll OlN3
0 DUll DIN4
Input Protection
DOUT4
Dual·ln·Line Package
'iiJUlIMfiiDIfY
Vee
0 Dun
DIM3
0 1N4 0 OUT4!flAiI1!
ENAm
At
AD
"
D Dun
DIM2
a INI
0 DUT1
AI
AA
AF
AE
TOP VIEW
Order Number MM54C910J or
MM74C91OJ
See NS Package J18A
TLIFIS914·'
6·134
Order Number MM54C910N or
MM74C910N
See NS Package N18A
GNO
TLIFI5914-l
Absolute Maximum Ratings
Operating Conditions
(Note 1)
Voltage at any Output Pin
-0.3 V to Vee + 0.3 V
-0.3Vto +15 V
Voltage at any Input Pin
500mW
Package Dissipation
3.0Vto 5.5V
Operating Vee Range
1.5Vto 5.5V
Standby Vee Range
6.0V
Absolute Maximum Vee
300·C
Lead Temperature (Soldering, 10 seconds)
Supply Voltage {Vee!
MM54C910
MM74C910
Temperature (TA)
MM54C910
MM74C910
Min
Max
Units
4.5
4.75
5.5
5.25
V
V
+125
+85
·c
-55
-40
·C
DC Electrical Characteristics
Min 1m ax limits apply across the temperature and power supply range indicated
Symbol
Parameter
Conditions
VIN(l)
Logical "1" Input Voltage
Full Range
VIN(O)
Logical "0" Input Voltage
Full Range
IIN(l)
Logical "1" Input Current
VIN=15V
VIN =5.0V
'IIN(O)
Logical "0" Input Current
VIN=OV
VOUT(l)
Logical "1" Output Voltage
10=-150",A
10=-400",A
VOUT(O)
loz
Logical "0" Output Voltage
Output Current in High
Impedance State
10=1.6mA
Vo -5.0V
Vo=OV
lee
Supply Current
Vee =5.0V
AC Electrical Characteristics
Symbol
Min
Typ
Max
.
0.005
0.005
-1.0
0.8
V
2.0
1.0
",A
",A
-0.005
flA
V
V
Vee- 0.5
2.4
-1.0
Units
V
Vce- 1.5
0.005
-0.005
0.4
1.0
V
flA
flA
5.0
300
flA
TA =25·C, Vee=5.0V, CL =50pF
Typ
Max
Units
tAee
Access Time from Address
250
500
ns
tpd
Propagation Delay from ME
180
360
ns
tSA
Address Input Set-Up Ti"me
140
70
ns
tHA
Address Input Hold Time
20
10
ns
Parameter
Conditions
Min
tME
Memory Enable Pulse Width
200
100
ns
tM'E
Memory Enable Pulse Width
400
200
ns
tso
Data Input Set-Up Time
0
tHO
Data Input Hold Time
30
15
ns
tWE
Write Enable Pulse Width
140
t lH, tOH
Delay to TRI·STATE (Note 4)
ns
ns
70
100
200
ns
Capacitance
CIN
Input Capacity
Any Input (Note 2)
5.0
pF
COUT
Output Capacity
Any Output (Note 2)
9.0
pF
Cpo
Power Dissipation Capacity
(Note 3)
350
pF
..
6·135
AC Electrical Characteristics
Symbol
(eont'd) TA = 25 D C, Vec =5.0V, CL = 50pF
MM54C910
TA = -55"C to +125"C
Vcc = 4.5V to 5.5V
Parameter
Min
MM74C910
TA = -400C to +85"C
Vec =4.75V to 5.25V
Min
Units
tAce
Access Time from Address .
Max
860
Max
700
tpdl, tpdO
Propagation Delay from
ME
660
ns
540
tSA
Address Input Set·Up Time
200
160
ns
ns
tHA
Address Input Hold Time
20
20
ns·
tME
Memory Enable Pulse Width
280
260
ns
t~
Memory Enable Pulse Width
750
600
ns
tso
Data Input Set-Up Time
0
O·
ns
tHo
Data Input Hold Time
50
50
ns
tWE
Write Enable Pulse Width
200
180
t 1H, tOH
Delay to TRI-STATE (Note 4)
ns
200
200
ns
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of
"Electrical Characteristics" provides conditions for actual device operation.
Note 2: Capacitance Is guaranteed by periodic testing.
Note 3: CPO determines the no load AC power consumption for any CMOS device. For complete explanation see 54C/74C Family
Characteristics application note AN-gO.
Note 4: See AC test circuits for tlH, tOH'
Typical Performance Characteristics
Truth Table
Typical Access Time vs Ambient
Temperature
450
400
I
350
]
300
!
Z50
~
4.5V
5V
...
...
ME
WE
OPERATION
L
L
L
H
H
L
H
H
Write
Read
Inhibit, Store
Inhibit, Store
...
I--'
I--'
5.5V
ZOO
150
"
.
OUTPUTS
TRI·STATE
Data
TRI,STATE
TRI·STATE
100
50
0
-55 -25
5
35
65
95
125
FREE AIR TEMPERATURE reI
TLIF169'4·4
AC Test Circuits
-.L"
l'
..----DOl
DOl
v
T t
R,
-
-$"
l
R,
".
1--R~ "'Ok
CL :l0pF
.
r---
.L'"
l~
$"
R,
DOl
All Other AC Tests
t1H
tOH
•
l·t"
ltc,
"
."
'"
OM
1--AL =111:
Ct. ~ 10pF
1',1,
J"l
TUFIS914·6
TLIF/5914·5
6-136
.--~DQlDO'h:
T"
T'"
':"
":'
~~r-r.
T"
T"
':"
CL =50pF
':"
TLIF15914·7
Switching Time Waveforms
Read Cycle
(See Note 1)
Write Cycle
(See Note 1)
v~
iiOOlRi
EfiAi[i
V~
ADDRESS
I.PUT
V~
IlilIilt
mill
V~
DATA
OUT
TlIF15914·8
TL/FIS914·9
Read Modify Write Cycle
ISee Notel)
tOH
v,, _ _ _ _ _,
ADDRESS
INPUT
LA1CHEDADDRESS
E~V~------------------------~>c'
v,, _ _ _ _ _ _ _ _ _ _ _....
DATA
IN
X
_ _ _ _ _- , -_ _ _ _ _J.
,._ _ _ _
'~-!8
~
Vee
DATA OUT
TLIF/5914.'O
'-.- - - - -
IhI.l:lIlIIIJRYlJiIIIlIIlIS1l1.braughth'llhfDltyEn... DUClllld' ..... n ... ry •• dIIlllChlllll ..
1111.Z: 1, .. t,-lD.,lorlllmpMll.
6-137
o
0.1 Vee
- __ TRI·STATE
TUF/5914·11
~ ~National
~ ~ Semiconductor
-::e,.. MM54C914/MM74C914 Hex Schmitt Trigger with
o:t'
§
Extended Input Voltage
It)
::e
::e
General Description
Features
The MM54C914/MM74C914 is a monolithic CMOS Hex
Schmitt trigger with special input protection scheme.
This scheme allows the input voltage levels to exceed
•
Vee'or ground by at least 10V (Vee - 25V to GND +
25V). and is valuable for applications involving voltage
level shifting or mismatched power supplies.
•
Special input protection.
•
Wide supply voltage range
The positive and negative·going threshold voltages. VT+
and V T -. show low variation with respect to temperature
(typ 0.0005V/oC at Vee ~ 10V). And the hysteresis.
VT+ - V T -;::: 0.2 Vee is guaranteed.
•
High noise immunity
•
Low power TTL
compatibility
Connection Diagram
0.45 Vee (typ.)
Hysteresis
0.2 Vee guaranteed.
GNO
Order Number MM54C914J or
MM74C914J
See NS Package J14A
Tl/F/5917·'
Order Number MM54C914N or
MM74C914N
See NS Package N14A
Special Input Protection
INPUT
--"""'.--/-+ TO GATE
BV" 25V
for the diodes.
6·138
-=
TlIF15917·2
3.0V to 15V
0.70 Vee (typ.)
fan out of 2
driving 74L
Dual·ln·Line Package
TOPVIEW
Extended Input
Voltage Range
Absolute Maximum Ratings
Voltage at Any Input Pin
Voltage at Any Other Pin
Operating Temperature Range
MMS4C914
MM74C914
-6S·Cto +1S0·C
Storage Temperature Range
SOOmW
Package Dissipation
3.0Vto 1SV
Operating Vce Range
1BV
Absolute Maximum Vce
300·C
Lead Temperature (Soldering, 10 seconds)
Vee-2SVto GND+2SV
-0.3 V to Vee + 0.3 V
-SS·Cto +12S·C
-40·C to +BS·C
DC Electrical Characteristics Minimax limits apply across temperature range unless otherwise noted
Symbol
I
Parameter
CMOS to CMOS
I
Conditions
I
Min
I
Typ
I
Max
I
Units
VT+
Positive Going Threshold Voltage
Vec=5.0V
Vee=10V
Vee=1SV
3.0
6.0
9.0
3.6
6.B
10
4.3
B.6
12.9
V
V
VT'-
Negative Going Threshold Voltage
Vee = 5.0V
Vec=10V
Vce=1SV
0.7
1.4
2.1
1.4
3.2
5.0
2.0
4.0
6.0
V
V
VT+ -VT_
Hysteresis
Vee = 5.0V
Vcc=10V
Vec=15V
1.0
2.0
3.0
2.2
3.6
5.0
3.6
7.2
10.B
V
V
V
VOUT(l)
Logical "1" Output Voltage
Vee =5.0V,lo=-10",A
Vee = 10V, 10 = -10",A
VOUT(O)
Logical "0" Output Voltage
Vee =5.0V,l o =+10",A
Vee = 10V, 10 = +10",A
IIN(l)
Logical "1" Input Current
Vee =15V, VIN=2SV
IIN(O)
Logical "0" Input Current
Vee = 15V, VIN = -10V
Icc
Supply Curren~
Vee = 15V, VIN = -10V/25V
Vee =5.0V, VIN = -2.5V (Note 4)
Vec = 10V, VIN = 5.0V (Note 4)
Vee = 15V, VIN = 7.5V (Note 4)
,
4.S
9.0
V
V
O.S,
1.0
0.005
-100
5.0
",A
300
",A
",A
",A
",A
0.7
V
-0.005
O.OS
20
200
600
V
V
",A
CMOS/LPTTL Interface
VIN(l)
Logical "1" Input Voltage
Vec=5.0V
VIN(O)
Logical "0" Input Voltage
Vee=5.0V
VOUT(1)
Logical "1" Output Voltage
S4C, Vee=4.SV, 10=-360",A
74C, Vee = 4.7SV, 10= -360",A
VOUT(O)
Logical "0" Output Voltage
54C, Vee = 4.5V, 10 = 360 ",A
74C, Vee = 4.75V, 10 = 360"A
V
4.3
2.4
2.4
V
V
0.4
0.4
V
V
Output Drive (See 54C/74C Family Characteristics Data Sheet) (short circuit current)
IsouReE
Output Source Current
(P-Channel)
Vee = 5.0V, VOUT = OV, TA = 25·C
-1.75
-3.3
mA
ISOURCE
Output Source Current
(P-Channel)
Vee=10V, VOUT=OV, TA =25·C
-B.O
-15
mA
ISINK
Output Sink Current
(N·Channel)
Vee = 5.0V, VOUT = Vce
TA =25·C
1.75
3.6
mA
ISINK
Output Sink Current
(N·Channel)
Vee =10V, VouT=Vec, TA=25·C
B.O
16
mA
)
6-139
,..
~.-----------------------------------------------------------------------------,
en
AC Electrical Characteristics TA = 25'C, CL = 50pF, unless other,wise specified.
t!1--------.------------------------------------.--------------.----.----.-----.----Parameter
Conditions
Min
Typ
Max
Units
Symbol
o
~I--~---~-----------------------------------------+---------------~---~~~----+----
~
Cpd
Propagation Delay from Input to Output
Vcc =5.0V
220
400
ns
~
80
200
ns
,..
Vcc=10V
f31--------+---------------------------------~----~-------+----+----+----4----~
CIN
Input Capacitance
Any Input (Note 2)
5.0
pF
CpD
Power Dissipation Capacitance
(Note 3) Per Gate
20
pF
~~I-------J--------------------------------L-----------~--~--~L---~---~
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Qperating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Cpo determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Charac·
teristics application note, AN-90.
GND.
Note 4: Only one Input is at 1/2 Vcc , the others are either at Vce
0,
Typical Application
GND 1
GND 2
NDte. Vee1..-VCC2
GND 1 'GNO 2
TlIF15917-3
Typical Performance Characteristics
T~pical
Transfer Characteristics
Guaranteed Trip Point Range
20
?:
'"
~"
>
...
...
15
Vee:: 15V
15
V,_
V,.
?:
w
MM54C14 -55"C TO +125 'C
MM74C14 -40 C TO +85' C
*MINIMUM HYSTERESIS
SPREAD (= 0.2 Vee!
v"
12.9
v,
10
'"
~
10
~
~
>
~
~
0
10
15
20
INPUT VOL TAGE IV)
v,.
INPUT
VOLTAGE
OV
5
43
3.0
2.0
0.7
0
V"
10
15
OUTPUT
VOLTAGE
Vee (V)
OV
TlIF/5917·4
TLlF/5917·5
6·140
TlIF15917·6
r----------------------------------------------------.~
~
.
~ Semiconductor
~National
~
o
.....
'CD
en
MM54C915/MM74C915 7-Segment-to-BCD Converter
3:
General Description
oCD
~
~
The MM54C915/MM74C91!j is a monolithic complementary MaS (CMOS) integrated circuit, constructed
with Nand P-channel enhancement-mode transistors,
This circuit accepts 7-segment information and converts
it into BCD information, The true state of the Segment
inputs can be selected by use of the 1nvert/Non-invert
c,?ntrol pin. A logical "0" on the Invert/Non-invert
control pin selects active high true decoding at the
Segment inputs, A logical "1" on the Invert/Non-invert
control· pin selects active low true decoding at the
Segment inputs, In addition to 4 TTL compatible BCD
outputs, an Error output and Minus output are available. The Error output goes to an active "1" whenever a
non-standard 7-segment code appears at the Segment
inputs. The BCD outputs are forced into a TRI-STATE®
condition when an error is detected, This allows the
user to program his own error code by tying the BCD
outputs to VCC or Ground via high value resistors
(~ 500k), The BCD outputs may also be forced into.
TRI·STATE by a logical "1" on output enable (OE).
The Minus output goes to a logical "1" whenever a
minus code is detected and is useful as a microprocessor
interrupt, The BCD outputs are in a flow-though
condition when Latch Enable (LE) is at a logical "0",
and latched when LE is at a logical "1 ", The inputs will
not clamp signals to the positive supply, allowing simple
level translation from MaS to TTL.
Features
•
•
•
•
,;
Wide supply range
High noise immunity
TTL compatible fan out
Selectable active true inputs
TR I-STATE outputs
3V-15V
0.45 Vee (typ.)
1 TTL load
• On-chip latch
• Error output.
• Minus output
Logic and Connf:)ction Diagrams
1-------1 ~~-~
MINUS
.2 0
,,1
SEGMENT
INPUTS
C22
1-+--<~---1
:><>-+--o ERRO R
I----c ~~~B~t
TLiF/5918·1,
Dual-In-Line Package
SEGMENT INPUTS
J"
INVERT MINUS
a \ CONTROL OUT
Vee
11
16
15
14
1J
lE
12
D 23
C 22
11
-
10
Order Number MM54C915J or
MM74C915J
See NS Package J18A
I--
Order Number MM54C915N or
. MM74C915N
See NS Package N18A
1
2
3
4
5
'---:SE::G:::M::EN~f:::,N~pu:::r~s--,9;.,. E~~~R
TOPVIEW
6-141
6
m
1
8
.20
821
19
GN~
.....
en
Absolute Maximum Ratings
Voltage at Any Output
Voltage at Any Input
Operating Temperature Range
MM54C915
MM74C915
- 0.3V to VCC + 0.3V
- 0.3V to 18V
-55°C to +125°C
-40° C to +85° C
DC Electrical Characteristics
SYMBOL
Storage Temperature Range
-65°C to +150°C
Package Dissipation
500mW
4.0V to 15V
Operating VCC Range
Maximum VCC
18V
Lead Temperature, (Soldering, 10 seconds)
300°C
PARAMETER
Minimax limits apply across temperature ;ange, unless otherwise noted.
CONDITIONS
MIN
TYP
MAX
UNITS
CMOS TO CMOS
VIN(1)
VIN(O)
.
Logical "l"lnput Voltage
Logical "0" Input Voltage
VCC = 5V
VCC= 10V
3.5
8
VCC= 15V
12.5
V
VCC= 10V
2
V
VCC= 15V
2.5
V
IIN(O)
Logical "0" Input Current
VIN = OV
VOUT(l)
Logical "1" Output Voltage
10= 10llA
ICC
Logical "0" Output Voltage
Supply Current
V
1.5
VIN = 15V
VOUT(O)
V
VCC = 5V
Logical "1" Input Current
IIN(l)
V
0.005
-1
1
-0.005
Il A
Il A
VCC= 5V
4.5
V
VCC = 10V
9
VCC = 15V
13.5
V
V
10= 10llA
VCC = 5V
0.5
VCC=10V'
1
V
VCC = 15V
1.5.
V
V
VCC = 5V
0.25
0.75
1
2.5
rnA
VCC = 10V
VCC = 15V
1.00
3
rnA
rnA
CMOSITTL INTERFACE
VIN(l)
VIN(O)
VOUT(l)
Logical "1" Input Voltage
MM54C915
VCCi' 4.5V
VCC-1.7
V
MM74C915
Vec = 4.75V
.VCC·-1.7
V
Logical "0" Input Voltage
MM54C915
VCC = 4.5V·
0.8
V
MM74C915
VCC = 4.75V
0.8
V
Logical "1" Output Voltage
MM·54C915
MM74C915
VOUT(O)
L~gical "0" Output Voltage
10 = -3601lA
VCC = 4.5V
2.4
V
VCC = 4.75V
2.4
V
10 = 1.6 rnA
MM54C915
VCC = 4.5V
0.4
V
MM74C915
VCC = 4.75V
0.4
V
OUTPUT DR.IVE (Short Circuit Current)
ISOURCE
Output Source Current
TA = 25°C, Vo = OV,
(Note 2)
P·Channel
-1.75
-8
-3.3
rnA
-15
rnA
-15
-25
rnA
Vce= 5V
5
8
rnA
VCC ='lOV
20
30
rnA
VCC = 15V
30
50
rnA
Vec= 5V
,
ISINK
Output Sink Current
N·Channel
VCC= 10V
Vec = 15V
T A = 25°C, Vo = VCC
(Note 2)
6·142
AC Electrical Characteristics TA =25°C
CONDITIONS·
SYMBOL
PARAMETER
tpdO. tpdl
Propagation Delay Time to
eL = 50 pF
Logical "0" or a Logical "1"
Vee = 5V
Vee = 10V
Vee = 15V
tOH. t1H
tHO. tH1
ts
tH
MAX
UNITS
500
1000
ns
300
600
ns
300
600
ns
TYP
MIN
Propagation Delay Time From
R L = 10k. e L - 10 pF
Logical "0" or Logical "1"
Vee = 5V
110
200
ns
into High Impedance State
Vee= 10V
75
130
ns
Vee = 15V
60
110
n~
Propagation Delay Time From
RL = 10k. CL = 50 pF
High Impedance State to a
Vee = 5V
150
250
ns
Logical "0" or Logical "1"
Vee = 10V
80
140
ns
Vec = 15V
70
125
ns
Input Data Set·Up Time
CL = 50 pF
Input Data Hold Time
Vec = 5V
500
1000
ns
Vec = 10V
300
600
ns
Vee = 15V
300
600
ns
CL = 50 pF
Vee = 5V
-150
0
ns
Vee= 10V
-100
0
ns
Vee = 15V
-100
0
ns
CIN
I nput Capacitance
Any Input. (Note 3)
5
eOUT
TR I·STATE Output Capaci·
Any Output. (Note 3)
10
pF
7.5
pF
tance
Noto 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they 'are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: These specifications apply to transient operation. It is not meant to imply that the device should be operated at these limits in sustained
operation.
Note 3: Capacitance is guaranteed by periodic testing.
Truth Table
CHARACTER
AT SEGMENT
INPUTS
0
BCD OUTPUTS
D
C
B
A
23 22 21
20
0
0
0
0
~
0
0
0
0
0
2
0
0
0
0
0
1
::I
1
1
0
0
1
1
~
lj
5
Ij
b
"!
11
9
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
1
x
x
x
All other input
X
X
X
combinations
X
X
X
~
-
X"" represents TRI-8TATE condition
6-143
0
1
1
0
1
0
1
0
0
1
0
1
1
1
X
X
X
NON·BCD
OUTPUTS
ERROR
MINUS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
SEGMENT IDENTIFICATION
•
f~~~b
.~:~c
d
~ .---------------------------~------------------------------------------------.
,...
~
Typical Applications
t:!
:!E
:i
Multiplex 7·Segment to Straight BCD
,...
~
SEGMENT INFORMATION
en
LSI PART
W/MULTIPLEXED
)·SEGMENT
INFORMATION
~:!E
~
n OIGIT LINES )
....
:E
1 OF n
MULTIPLEXER
)
....
SEG
INPUTS
--+
LATCH
ENABLE
....
BCO
STRAIGHT BCD
OUTPUTS
....
MM54C915
MINUS
ERROR
i t
~
OIGIT
SELECT
TL'I>I5918·3
Memory Expansion from 7..segment Outputs
f-+ MINUS
f-+ ERROR
j,.
LSI PART
W/MULTIPLEXEO
)·SEGMENT
INFORMATION
SEGMENT INFORMATION
....
n OIGIT LlNEV
1 OF n
MULTIPLEXER
)
....
~
SEG
INPUTS
MM54C915
"~~
A
J
WE
START
---to
STOP ~.-
~
\
2n
1---1
BCD
LATCH
ENABLE
DATA INPUTS·
~ }'"""~
CDUNTER
2m
COUNTER
BCD
INPUTS
2nm X 4
RAM
)
TLIF1591&4
6·144
~National
~ Semiconducto,
MM54C922/MM74C92216-Key Encoder
MM54C923/MM74C923 20-Key Encoder
General Description
These CMOS key encoders provide all the necessary
logic to fully encode an array of SPST switches. The
keyboard scan can be implemented by either an external
clock or external capacitor. These encoders also have on·
chip pull·up devices which permit switches with up to
50 H2 on resistance to be used. No diodes in the switch
array are needed to eliminate ghost switches. The
internal debounce circuit needs only a single external
capacitor and can be defeated by omitting the capacitor.
A Data Available output goes to a high level when a
valid keyboard entry has been made. The Data Available
output returns to a low level when the entered key is
released, even if another key is depressed. The Data
Ayailable will return high to indicate acceptance of the
new key after a' normal debounce period; this two key
roll over is provided between any two switches.
provide for easy expansion and bus operation and are
LPTTL compatible.
Features
• 50 kn maximum switch on resistance
• On or off chip clock
• On chip row pull-up devices
• 2 key roll-over
•
Keybounce elimination with single capacitor
•
Last key register at outputs
• TRI-STATE outputs LPTTL compatible
3V to 15V
• Wide supply range
An internal register remembers the last ke~ pressed
even after the key is released. The TRI-STATE' outputs
•
Low power consumption
\
Connection Diagrams
Dual-I "-Line Package
18
ROWYI
ROWYl
16 DATA our 8
ROWY4
15DATAOUTC
OSCILLATOR
14 DATA OUT 0
13 DDiPUffNA8Lf
KEVBDUNCE MASK
11 COLUMN XI
COLUMN X3
10 COLUMN X2
GND
ROWYZ
19 OATAOUTA
ROWYl
18 DATA our B
ROWV4
11 DATA OUT C
ROWY5
16 DATA OUT 0
OSCILLATOR
15DATAOUTE
14 OUTPUT ENABLE
KEYBOUNCE MASK
12 DATA AVAILABLE
COLUMN X4
20 Vee
ROWYI
v""
11 DATAOUTA
RDWY2
II
Dual-In-Line Package
COLUMN X4
13 DATA AVAILABLE
COLUMN Xl
12 COLUMN XI
GND 10
11, COLUMN X2
TOP VIEW
TUF/6037·1
TOP VIEW
TUF/603H
Order Number MM54C922J or MM74C922J
See NS Package J18A
Order Number MM54C923J or MM74C923J
See NS Package J20A
Order Number MM54C922N or MM74C922N
See NS Package N18A
Order Number MM54C923N or MM74C923N
See NS Package N20A
6-145
Absolute Maximum Ratings
Voltage at Any Pin
(Note 1)
Vee - O.3V to Vee + O.3V
MM54C922, MM54C923
MM74e922, MM74C923
Storage Temperature Range
Operating Vee Range
Vee
-ss"e to +12soe
-40°C to +8SoC
-£SoC to +lS0°C
DC Electrical Characteristics
SYMBOL
PARAMETER
500mW
3V to 15V
18V
300°C
Package 0 issipation
Operating Temperature Range
Lead Temperature (Soldering, 10 seconds)
MiniMax limits apply across temperature range unless otherwise specified,
CONDITIONS
MIN
TYP
MAX
UNITS
CMOS TO CMOS
VT+
VT_
VIN(l)
VIN(O)
Positive·Going Threshold Voltage at
Vee = SV,
IIN~0.7mA
3
3.6
4.3
V
Osc and KBM Inputs
Vee = 10V, liN ~ 1.4 mA
6
6.8
8.6
V
Vee = lsV, IIN~2.1mA
9
10
12.9
V
·0.7
1.4
2
V
Negative·Going Threshold Voltage at
Vee = SV,
Osc and KBM Inputs
Vee = 10V, liN ~ 1.4 mA
1.4
3.2
4
V
Vee = 15V, liN ~ 2.1 mA
2.1
5
6
V
Logical "1" Input Voltage, Except
Vee = SV,
3.5
4.S
V
Osc and kBM Inputs
Vce = 10V,
8
9
V
Vce=15V,
12.5
13.5
liN ~0.7 mA
Vee=SV,
O.S
1.S
Osc and KBM Inputs
Vee = 10V,
1
2
Vee = 15V,
Irp
VOUT(l)
VOUT(O)
Aow Pull·Up Current at Yl, Y2, Y3,
Vee = 5V,
Y4 and Y5 Inputs
Vee = 10V
Vee = 15V
Logical "1" Output Voltage
Logical "0" Output Voltage
1.5
-2
V I N=O.l Vee
10 =-10IlA
-10
-20
IlA
-22
-45
IlA
4.S
V
Vee = 10V, 10 = -lOIlA
9
V
Vee=15V, 10=-lOIlA
13.S
Vee = 5V,
Vee = 5V,
V
10 = 10llA
Column "ON" Aesistance at
Vee = 5V,
Xl, X2, X3 and X4 Outputs
Vee = 10V, Va = IV
Va = 0.5V
Vee = lSV, Va = 1.SV
IIN(ll
V
IlA
.
0.5
V
1
V
1.5
V
sao
1400
Q
300
700
Q
20Q
sao
0.55
1.1
mA
Vee=lSV, 10= lallA
ICC
.2.5
V
V
-5
Vee = 10V, 10 = 10IlA
Aon
V
Logical "0" Input Voltage, Except
Q
Supply Current
Vee = 5V,
Osc at OV, (one Y low)
Vee = 10V
1.1
1.9
mA
Vee= lSV
1.7
2.6
mA
Vee = lSV, VIN = lSV
0.005
1.0
IlA
Logical "1" Input Current at
Output Enable
IIN(O)
Logical "0" Input Current at
Vee = lSV, VIN = OV
-1.0
-{l.OOS
IlA
Output Enable
CMOS/LPTTL INTEAFAeE
VIN(l)
VIN(O)
VOUT(ll
Logical "1" Input Voltage, Except
54e, Vee = 4.SV
Vee- 1.S
V
Osc and KBM Inputs
74e, Vee = 4.75V
Vee- 1.5
V
Logical "0" Input Voltage, Except
54e, Vee = 4.5V
0.8
Osc and KBM Inputs
74e, Vee = 4.75V
0.8
Logical "1" Output Voltage
S4e, Vee = 4.SV,
V
V
2.4
V
2.4
V
10 = -3601lA
74e, Vee = 4.75V,
10 = .-36OIlA
VOUT(O)
Logical "0" Output Voltage
54e, Vee = 4.5V,
0.4
V
0.4
V
10 = 360llA
74e, Vee = 4.75V,
10 = 360~A
6-146
DC e,lectrical Characteristics
(Cont'd.)
MinIMax limits apply across temperature range unless otherwise specified.
SYMBOL
I
I
PARAMETER
CONDITIONS
OUTPUT DRIVE (See'54CI74C Family Characteristics Data Sheet) (Short Circuit Current)
I
MIN
I
TYP
I
MAX
I
UNITS
ISOURCE
Output Source Current (P·Channel)
VCC = 5V. VOUT = OV.
TA = 25°C
-1.75
-3.3
mA
ISOURCE
Output Source Curren~ (P·Channel)
VCC = 10V, VOUT = OV,
TA = 25°C
-8
-15
mA
ISINK
Output Sink Current (N·Channel)
VCC = 5V. VOUT = VCC.
TA=25°C
1.75
3.6
mA
ISINK
Output Sink Current (N·Channel)
VCC = 10V. VOUT = VCC.
TA = 25°C
8
'6
mA
AC Electrical Characteristics
SYMBOL
t pdO,tpdl
tOH,l1H
TA=25°C, C L =50pF, unless otherwise noted
CONDITIONS
PARAMETER
TYP
MAX
UNITS
Propagation Delay Time to
CL = 50 pF, (Figure 11
Logical "0" or Logical "'"
from DA.
VCC =5V
60
150
ns
VCC = 10V
35
80
ns
VCC = 15V
25
60
ns
Propagation Delay Time from
RL = 10k, CL = 10pF (Figure 2)
Logical "0" or Logical "1"
VCC = 5V RL = 'Ok
VCC = 10V CL = 10 pF
80
200
ns
65
150
ns
VCC = 15V
50
110
ns
ns
ns
into High Impedance State
tHO.tHl
MIN
Propagation Delay Time from
RL = 10k, CL = 50 pF, (Figure 2)
High Impedance State to a
VCC = 5V
100
250
Logical "0" or Logical "'"
VCC = .10V CL = 50 pF
55
125
RL = 10k
VCC = '5V
40
90
ns
CIN
Input Capacitance
Any Input, (Note 2)
5
7.5
pF
COUT
TR I·STA TE Output Capacitance
Any Output; (Note 2)
'0
pF
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to implv that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Switching Time Waveforms
Vee
~
ANY KEY
D-
ifij'fjiUf
E""NASIE
.rIM.
D
D
DATA OUT
-- -
VOL
DATA
~ TRI·STATE
0.5 Vee
V
I-t,'D
-
OUTPUT
ENABLE
I-t,..
Vee
OUTPU~
J ...;---- /
I
13
I D.'Vee
-
ve:
T2 -
11-
Vee
DATA
D
tOH
Vee
ANV OTHER
KEY
AVAILABLE
vee~
0.5 Vee
, \o.,vee
vee~
D.' Vee .
0
VOH
DATA OUT
!D"vee
D
~
911%
_ _ _ ,!,R,!:.STATE
D
T1 ~ T2 '" RC, T3 '" 0.7 RC where R '" 10k and C i. external
capacitor at KBM input.
TL/FI6037-4
TUF/6037·3
FIGURE 1
FIGURE2
6-147
Block Diagram
10k
TAl STATE
,---------0 ~~~;:~l
ENABLE
CK
2 TO 4 DECODER
ACllVE LOW OUTPUTS
Xl
X'
XI
X2
KEY
,DETECT
V"
CK
INTERNAL
C
OUTPUTS
CK
spsr
ENCODING
lOGIC
SWITCH --
AND
2·KEY
ROLL OVER
CK
KEY
ARRAY
CK
MSB
TLIF/60J7·5
Truth Table
SWITCH
POSITION
10
Vl,Xl
Vl,X2 Yl,X3 Vl,X4 V2.Xl
V2,X2 Y2,X3 Y2,X4 va,Xl
11
12
va,X2 V3,X3 V3,X4
V4,Xl
13
14
15
16
Y4,X2 Y4,X3 Y4,X4 V5*.Xl
17
18
19
VS*.X2
VS*.X3
YS*.X4
o
A A
T
A
B
C
' 0
o 0
~ e*
'Omit for MM54C922/MM74C922
Typical Performance Characteristics
Typical Ron vs VOUT at Any
X Output
Typical I rp vs V I N at Any
Y Input
3D
or
TA ~25 C
;,
.3
....-
25
....
z
'"
"'"u
"
"
~
~
~
20
L
15
/
//
ot-
'z"
ffi
2.5
I
1
u
~
!;
~
Vee'" lOV
1.5
c
z
'~"
8
Vee'" 5V
10
15
TA =26°C
pee "3V
3.5
w
~
10
o
Vee" 15V
0.5
o
I
I
I L
L
5V
~
10V
.....
o
10
15V
15
VOUT IV)
TlIF/6031·7
TLlF/803Ui
6·148
I
Typical Performance Characteristics1(Cont'd.)
Typical Debounce Period
vs CKBM
Typical FSCAN vs COSC
~
10k .
._
I
1k
'"z
~
--
F
V
0.1
Q
Q
~
100
V
0.01
z
~
Q
Q
10 L-l....l..LllWL.....L-LLl.illlL-.l.J...l.IJLWJ
0.1
10
0.01
1/
0.001
0.1
10
100
TLlF16037-9
TLJFI6037·8
Typical Applications·
Synchronous Handshake IMM74C922)
Synchronous Data Entry Onto Bus IMM74C922)
~_ 10C
r
~'0C
________~MM~7(4~C9~2~2~--1
X4
MM74C922
KBM
X4 KBM
,..-----4X3
.-----IX3
·DATA AVAILABLE
SYSTEM
CLOCK ~-+---l-----I
ISEE NOTE 3)
J
2
f
7
6
5
4
B
A
9
B
FED
C
0
(INVITATION)
SYSTEM
.
CLOCK~4---l---L~
(SEE NOTE 3)
TLlF/6037-1~
TlIFI6037·1"
O~tputs
are enabled when valid entry is made and
go'into TRI·STATE when key is released.
Asynchronous Data Entry Onto Bus IMM74C922)
IOC
MM74C922
KBM
*"
1-____...
TO DATA BUS
1----..... DATA AVAILABLE
1/674C04
TLlF16037·12
Outputs are in TRI-STATE until key is pressed, then data is placed on bus.
When key is released, outputs return to·TRI-STATE.
No~
rate
3: The keyboard may be synchronously sc~nned by omitting the capacitor at csc. and driving ose. directly if the system clock
lower than 10 kHz.
IS
6·149
Typical Application
(Cont'd.)
Expansion to 32 Key Encoder (MM74C922)
+5V
I
Xl
Vce
KBM
OSC
X2
X3
I
MM74C922
g
DA I--DATA AVAILABLE
X4
0
-1
2
3
Vl
4
5
6
7
V2
B 1--01
V3
C r--02
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
F-- F-- ~~ ~lN914
~In
,~
V4
10C
A r--DO
GND
01--03
TO DATA
BUS
-4.
04
MM74C20
l00kQ
.
Vce
TUF/6037·13
Theory of Operation
The MM74C922/MM74C923 Keyboard Encoders im·
plement all the logic necessary to interface a 16 or 20
SPST key switch matrix to a digital system. The encoder
will convert a key switch closer to a 4(MM74C922) or
5(MM74C923) bit nibble. The designer can control both
the keyboard scan rate and the key debounce period by
altering the oscillator capacitor, COSE, and the key
bounce mask capacitor, CMSK. Thus, the MM74C9221
MM47C923's performance can be optimized for many
keyboards.
The keyboard encoders connect to a switch matrix that
is 4 rows by 4 columns (MM74C922) or 5 rows by 4 columns (MM74C923). When no keys are depressed, the row
inputs are pulled high by internal pull-ups and the column
outputs sequentially output a logic "0". These outputs
are open drain and are therefore low for 25% of the time
and otherwise off. The column scan rate is controlled by
the oscillator input, which consists of a Schmitt triggef
oscillator, a·2·bit counter, and a 2-4-bit decoder.
When a key is depressed, key 0, for example, nothing
will happen when the X1 input is off, since Y1 will remain
high. When the X1 column is scanned, X1 goes low and
Y1 will go low. This disables the counter and keeps X1
low. Y1 going low also initiates the key bounce circuit
timing and locks out the other Y inputs. The key code to
be outputted is a combination of the frozen counter value
and the decoded Y inputs. Once the key bounce circuit
times out, the data is latched, and the Data Available
(DAV) output goes high.
If, during the key closure the switch bounces, Y1 input
will go high again, restarting the scan and resetting the
key bounce circuitry. The key may bounce severai' times,
but as soon as the switch stays low for a debounce
period, the closure is assumed valid and the data Is
latched.
A key may also bounce when it Is released. To ensure
that ·the encoder does not recognize this bounce as
another key closure, the,debounce circuit must time out
before another closure is recognized.
The two key roll over feature can be illustrated by assuming a key is depressed, and then a second key Is
depressed. Since all scanning has stopped, and all
other Y inputs are disabled, the second key is not recognized until the first key is lifted and the key bounce circuitry has reset.
The output latches feed TRI-STATE, which are enabled
when the Output Enable (OE) input is taken low.
6-150
~National
~ Semiconductor
MM54C9321MM74C932 Phase Comparator
General Description
Features
The MM74C932/MM54C932 consists of two independent
output phase comparator circuits. The two phase com·
parators have a common signal input and a common
comparator input. The signal input can be directly
coupled for a large voltage signal, or capacitively coupled
to the self·biasing amplifier at the signal input for a small
voltage signal.
•
Wide supply voltage range
•
Convenient mini·DIP package
• TRI-STATE® phase-comparator output (comparator
II)
200 mV input voltage (signal in) sensitivity(typical)
•
Phase comparator I, an exclusive-OR gate, provides a
digita1 error signal (phase compo lout) and maintains
90 0 phase shifts at the VCO center frequency. Between
signal input and comparator input (both at 50% duty
cycle), it may lock onto the signal input frequencies that
are close to harmonics of the VCO center frequency.
Phase comparator II is an -edge·controlled digital
memory network. It provides a digital error signal (phase
compo II out) and lock in signal (phase pulses) to indio
cate a locked condition and maintains a 0 0 phase shift
between signal input and comparator input.
Block and Connection Diagrams
SIGNAL
VCC
'is
IB
PHASE
COMPARATOR I
COMPARAT~~
}-____---i*"z_ PHASE·COMP lOUT
)
1 __
.-;
- - ' 3 ; - _ + _.....
~NC
PHASE
5
L:r COMP~FATORI'
GNO...!
PHASE COMP II OUT
_ _---i*-'1_ PHASE PULSES
TUF/5921·1
Dual·1 n·Line Package
PHASEPULSESOB VCC'
PHASE COMP lOUT
2
7
COMPARATOR IN
3
6
NC
SIGNAL IN
GNO
4
5
PHASE COMP II OUT
TOP VIEW
TLlF15921·2
Order Number MM54C932N or MM74C932N
See NS Package NOSE
6·151
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
MM54e932
MM7.. e932
Storage Temperature Range
Note 1
-O.3V to Vee + O.3V
Package Dissipation
Operating Vee Range
Absolute Maximum Vee
Lead Temperature (Soldering, 10 seconds)
-55°e to+125°e
_40 o e to +85°e
-65°e to +150O e
500mW
3V to 15V
18V
3000 e
DC Electrical Characteristics
Symbol
ICC
Max
Units
0.005
0.01
0.015
150
300
600
p.A
p.A
p.A
PIN 6 = Open,
PIN 3 = GNO
Vee = 5V
Vee = 10V
Vee = 15V
5
20
50
205
710
1800
p.A
p.A
p.A
0
0
0
0.05
0.05
0.05
V
V
V
Conditions
Parameter
Quiescent Device Current
PIN 5.= Vee, PIN8-Vee,
PIN 3 = OV
Vee = 5V
Vee = 10V
Vee = 15V
Min
-TVp
VOL
Low Level Output 'Voltage
Vee=5V
Vee= 10V
Vee=15V
VOH
High Level Output Voltage
Vee = 5V
Vee= 10V
Vee=15V
VIL
Low Le~el Input Voltage
Comparator and Signal
Vee = 5V, Va = 0.5V or 4.5V
Vee = 10V, Va ~1 V or 9V
Vee = 15V, Vo= 1.5Vor 13.5V
VIH
High Level Input Voltage
Comparator and Signal
Vee=5V, VO=0.5Vor4.5V
Vee = 10V, Va = IV or 9V
Vee = 15V, Vo= 1.5Vor 13.5V
3.5
7.0
11.0
IOL
Low Level Output Current
Vee= 5V, Va = 0.4V
Vee = 10V, Va = 0.5V
Vee= 15V, Va = 1.5V
0.36
0.9
2.4
0.88
2.25
8.8
mA
mA
mA
IOH
High Level Output Current
Vee= 5V, Va = 4.6V
Vee = 10V, Va = 9.5V
Vee= 15V, Va = 13.5V
-0.36
-0.9
-2.4
-0.88
-2.25
-8.8
mA
mA
mA
liN
Input Current
All Inputs Except Signal Input
Vee = 15V, VIN=OV
Vee=15V, VIN=15V
4.95
9.95
14.95
CIN
Input Capacitance
Any Input
Po
Total Power Dissipation
fo= 10kHz, Rl = 1 MH
R2 = -, VeOIN = Vee/2
Vee= 5V
Vee= 10V
Vee=15V
V
V
V
5
10
15
1.5
3.0
4.0
V
V
V
V
V
V
-10':5
10-5
0.07
0.6
2.4
-1.0
1.0
p.A
p.A
7.5
pF
mW
mW
mW
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
6·152
s::
s::
Electrical Characteristics
SYMBOL
Conditions
Parameter
Typ
Min
Max
Units
en
~
0
CO
Phase Comparators
Co)
I\)
RIN
Input Resistance Signal Input
Comparator Input
AC Coupled Signal Input
Voltage Sensitivity
1.0
0.2
0.1
3.0
0.7
0.3
Mn
Mn
Mn
Vce = SV
Vce= 10V
VCC= ISV
106
106
106
Mn
Mn
Mn
CSERIES = 1000pF
f = SOkHz
Vce= SV
VCC= 10V
VCC= ISV
200
400
700
VCC=SV
VCC= 10V
VCC=ISV
Phase Comparator State Diagrams
PHASE COMPARATOR I
INPUT STATE
COMPARATOR
~N
SIGNAL
IN
~
11
10
.
I '
I
PHASE COMP lOUT
TL./F/5921·3
PHASE COMPARATOR II
INPUT STATE
tiN
COMPARATOR
SIGNAL
IN
PHASE COMP II OUT
PHASE PULSES
TL.IFI5921-4
Figure 1
6-153
400
800
1400
mV
mV
mV
s::
iI:
.....
~
0
CO
Co)
I\)
Typical Waveforms
I'HASE COMPARATOR I
SIGNAL IN
COMPARATOR IN
PHASE COMP lOUT
VCOIN
(LOW PASS FILTER OUTPUT)
TL.lFI~9215
Figure 2. Typical Waveform Employing Phase Comparator I in Locked Cond(tion
PHASE COMPARATOR II
SIGNAL IN
COMPARATOR IN
VCC-n
Ov
VOH
VOL
...,
---I L---....J
-r---1
r---1
L-...J
----l
.
L.-
L-
PHASE PULSES
VOH~
PHASE COMP II OUT
VOH-n--VOL ----L.I--
VOL--
·VCOINVOH~
(LOW PASS FILT.ER OUTPUT) VOL -
'\
TLIFI5921-6
Figure 3. Typical Waveform Employing Phase C~mparator II in Locked Condition
Typical Phase· Locked Loop
p~~~~ r-----,
FILTER
OUT
TlIFI592H
6·154
~National
~ Semiconductor
MM54C941/MM74C941 Octal Buffers/Line Receiversl
Line Drivers with TRI-STATEID Outputs
General Description
Features
These octal buffers and line drivers are monolithic
complementary MOS (CMOS) integrated circuits with TRISTATE outputs_ These outputs have been specially de"signed to drive highly capacitive loads such as busoriented systems. These devices have a fan-out of 6 low
power Schottky loads. When Vee = 5V, inputs can accept
true TTL high and low logic levels.
• Wide supply voltage range (3V to 15V)
•
•
•
•
Low power consumption
TTL compatibility (Improved on the inputs)
High capacitive load
TRI-STATE outputs
• Input protection
• 20-pin dual-in-line package
• High output drive
Connection and Logic Diagrams
Dual-In-Llne Package
OAl
VCC
002
001
IAI
OA2
IB4
IB2
1A3
1A2
IBl
IA4
OB2
DB3
084
OA4
OAa
IB3
GNO
OBI
TUF/5923-1
TOP VIEW
Order Number MM54C941J or MM74C941J
See NS Package J20A • .
Order Number MM54C941N or MM74C941N
See NS Package N20A
CONTROLS ONE OF
EIGHT DEVICES
, - - - -- --- - -- -- --- - - -.,
~~~~g~I~~~
r-----------,I
II
I OUTPUT
II
I DI~.~~,LE
I
I
I
I
I
:
VCC
I I
L~~
I
II
I
OUTPUT
DISABLE
•
_________
~:
DATA
INPUT
DATA
•
• SPECIAL TTL LOGIC LEVEL CONVERTER
I
I
~I
*-----"~
I
(~EN vec:; 5V) -
- - - - - -
I
I
oJ
TI..IFI5923-2
6-155
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
MM54C941
MM74C941
Storage Temperature Range
(Note 1)
0.3Vto Vee + 0.3V
-55'Cto +125'C
-40'Cto +85'C
-65 'C to + 150 'C
DC Electrical Characteristics
Symbol
I
Parameter
CMOS to CMOS
-
500mW
3.0Vto 15V
18V
300'C
Package Dissipation
Operating Vee Range
Vee
Lead Temperature (Soldering, 10 seconds)
Minimax limits apply across temperature range, unless ot!1erwise noted.
I
Conditions
VIN(l)
Logical "1" Input
Voltage
Vee =5.0V
Vee=10V
VINIO)
Logical "0"
Input Voltage
Vee =5.0V
Vee=10V
VOUT(1)
Logical "1"
Output Voltage
Vee = 5.0V, 10 = - 10 I'A
Vee = 10V, 10 = -1OI'A
VOUT(O)
Logical "0"
Output Voltage
Vee = 5.0V, 10= +1OI'A
Vee =10V, 18= +1OI'A
IIN(l)
Logical "1"
Input Current
Vee = 15V, VIN = 15V
IIN(O)
Logical "0"
Input Current
Vee = 15V, VIN = OV
Icc
Supply Current
Vee = 15V
loz
TRI-STATE Leakage
Vee =15V, VOUT=OVor 15V
I
Min
I
Typ
I
I
Max
2.5
8.0
V
V
0.8
2.0
V
V
4.5
9.0
V
V
0.005
-1.0
Units
0.5
1.0
'V
V
1.0
I'A
-0.005
0.05
I'A
300
I'A
±10
I'A
CMOS/TTL Interface
VIN(l)
Logical "1"
Input Voltage
54C, Vee = 4.5 V
74C, Vee =4.75V
VIN(O)
Logical "0"
Input Voltage
54C, Vee=4.5V
74C, Ve e =4.75V
VOUT(l)
Logical "1"
Output Voltage
54C,
74C,
54C,
74C,
Logical "0" Output
Voltage
54C, Vee = 4.5V, 10 = +2.2mA
74C, Vee = 4.75V, 10= +2.2mA
-'--VOUT(O)
Vee=4.5V, 10= -4501'A
Vee = 4.75V, 10= -4501'A
Vee = 4.5V, 10 = -2.2mA
Vee=4.75V, 10= -2.2mA
V
V
Vee- 2.5
Vee- 2.5
0.8
0.8
V
V
V
V
V
V
Vee- 0.4
Vee -O.4
2.4
2.4
0.4
0.4
V
V
Output Drive (See 'S4C/74C Family Characteristics Data Sheet)
IsouReE
----_.-
Output Source
i-Current (P-Channel)
Vee = 5.0V, VOUT = OV
TA=25'C
-' 14.0
-30.0
mA
IsouReE
Output Source
Current (P-Channel)
Vee = 10V, VOUT = OV
TA=25'C
-36.0
-70.0
mA
ISINK
Output Sink
Current (N-Channel)
Vee = ii.ov, VOUT = Vee
TA = 25'C
+12.0
+20.0
mA
ISINK
Output Sink
Current (N-Channel)
Vee = 10V, VOUT :' Vee
TA =25'C
+48.0
+70.0
6-156
\
mA
,AC Electrical Characteristics TA =25"C, CL=50pF, unless otherwise specified.
Parameter
Conditions
Typ
Max
Units
tpd1 , tpdO
Propagation Delay (Data
INto OUT)
Vcc=5.0V, CL=50pF
V ee =10V, CL=50pF
Vee = 5.0V, CL = 150 pF
Vee = 10V, CL = 150 pF
70
35
90
45
140
70
160
90
ns
ns
ns
ns
tlH, tOH
Propagation Delay Output
Disable to Logic Level (from
High Impedance State) (from a
Logic Level)
RL =lkQ, CL =50pF
Vee=5.0V
Vee=210V
100
55
200
110
ns
ns
Propagation Delay Output
Disable to Logic Level (from
High Impedance State)
RL =lkQ, CL=50pF
Vee =5.0V
Vee=10V
100
55
200
110
ns
ns
Vee = 5.0V, CL = 50 pF
Vee =10V, CL=50pF
Vee=5.0V, CL=150pF
Vee = 10V, CL = 150 pF
50
30
80
50
100
60
160
100
ns
ns
ns
ns
Symbol
t H1 , tHO
tTHL, tTLH Transition Time
Power Dissipation Capacitance
(Output Enabled per Buffer)
(Output Disabled per Buffer)
(See Note 3)
CIN
Input Capacitance
(Any Input)
Co
(Output Capacitance)
(Output Disabled)
Cpo
Min
100
10
pF
pF
(See Note 2)
VIN=OV, f=lMHz
TA =25"C
10
pF
VIN =Ov, f = 1 MHz,
TA =25"C
10
pF
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Range" they are not meant to im~ly that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Cpo determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note, AN-gO.
II
Truth Table
OD1
OD2
0
0
0
1
1
0
0
1
0
1
Input Output
0
1
X
X
X
1 =High
O=Low
X = Don't Care
Z=TRI-STATE
6-157
0
1
Z
Z
Z
P·Channel Output Drive
@ 25°C
N·Channel Output Drive
qb 25°C
0
120
V
100
I,.i'l
z
in
40
20
0
!
--
1/
60
~
V
i
f- VCC=10V
i'l
~
u
~
~
f- r-vec=L
4
5
-30
-40
-50
-60
12
14
-80
Vec -15V
.J...H1"
15
15
12
9
6
3
TlIFI5923·4
propa~ation
b.lpD ~er pF of Load
Capac lance
Delay vs.
apacitance
200
0.4
150
0.3
ii
i
100
50
i~ 0.2
~
-~=
Vec
10V
~
0.1
i::=--
VCCt'5V
0
50
100
150
5
0
2110
10
-
15
VCC - POW£R SUPPLY VOlTAGE (V)
CL (pfl
TLiF/59Z3·S
TLIFI5923-6
Applications
CONTROL OR MICROPliOORAM ~OM/PROM
OR
MEMORY ADDRESS REGISTER
I
C!i41
DUTPUTCDNTRDL-
0
Vce -VOUT(V)
TlIF/S923-3
Load
II
V
-70
-"100
8 10
VOUT (VI
V
VCC=10V
-90
j I
2
Vee _5V
-20
V
lBO
II
-10
Vee=15V
7f 7f 71
r
::D
7
1
[ tTf 7( 7(7
SYSTEM AND/OR MEMORY ADDRESS BUS
TL/F/5923·1
6·158
AC Test Circuits and Switching Time Waveforms
tpdO. tpd1 '
CMOS to CMOS
Vee
0.9
0,9
V,.
0,1
0,1
OV
'r
Vee
TlIF159~3B
~{
,
50%
VOUT
OV
50%
TLIF15923·9
t1H and tH1
tH1
Vee
"NPUT~OUTPUT
DISABLE
J
'-= IkU
DISABLE
DISABLE Vee * , vee
5
OV
C,'5,F
-
VOH --------,I
TLIF/5923-10
tHI--
VOH----------1--,.~I--OUTPUT
DUTPUT
OV
0.5 VOH
--------="....--
oV----,-----.-
TLIF15923-11
NOTE: VOH IS DEFINED AS THE DC OUTPUT HIGH VOLTAGE
WHEN THE DEVICE IS LOADED WITH A 1 kU RESISTOR
TO GROUND,
tOH and tHO
tOH
Vee
Vee
INPUT
DISABLE
~*"
DISABLE
DISABLE
OV
OUTPUT
~e
TLlFJS923-12
___________
~-+----L--
Vee
C,' 5 ,F
OUTPUT
OUTPUT
Vo ,
VOL - - - - - - - - - - - - - - - - ' ' - - - 0.1 (Vee - VaLl
NOTE: Vo, IS DEFINED AS THE DC DUTPUTLOW VOLTAGE
WHEN THE DEVICE IS LOADED WITH ~ 1 kU RESISTOR
TO Vee-
Note: Delays measured with input t .. I, "5 20 ns
6-159
TLlF/5923·13
~ National·,
~ Semiconductor
MM54C989/MM74C~89 64·Bit (16
x 4) TRI·STATE®
RAM
General Description
The MM54C989/MM74C989 is a 16-word by 4-bit
random access read/write memory. Inputs to the memory
consist of 4 address lines, 4 data input lines, a write'
enable line and a memory enable line. The 4 binary
address inputs are decoded internally to select each of
the 16 possible word locations. An internal address
register latches the address information on the positive
to negative transitio~ of the memory enable input. The 4
TRI-STATE data output lines working in conjunction
with the memory enable input provides for easy memory
expansion.
Address Operation: Address inputs must be stable tSA
prior to the positive to negative transition of memory
enable. It is thus not necessary to hold address informa·
tion stable for more than tHA after the memory is
enabled (positive to negative transition of memory
enable).
Note. The timing is different than the DM7489 in that
a positive to negative transition of the memory enable
must occur for the memory to be selected.
Write Operation: Information present at the data inputs
is written into the memory at the selected address by
bringing write enable and memory enable low.
Read Operation: The complement of the information
which was written into the memory is non-destructively
read out at the 4 outputs. This is accomplished by
selecting the desired address and bringing memory enable
low and write enable high.
When the device is writing or disabled the output assumes
a TRI-STATE (Hi-Z) condition.
Features
\
3.0V to 5.5V
• Wide supply voltage range
1.0V,
• Guaranteed noise margin
•
High noise immunity,
0.45 VCC (typ.)
•
Low power TTL
compatibility
•
Input address register
•
Low power consumption
•
Fast access time
fan out of 2
driving 74L
250 nW/package (typ.)
@VCC~5V
140 ns (typ.) at VCC
~
5V
• TRI-STATE output
Logic and Connection Diagrams
DATA
iiAfA DATA DATA DATA fiA'fA DATA DATA
INPUT 1 OUTPUT 1 INPUT 2 OUTPUT 2 INPUT 3 OUTPUT 3 INPUT 4 OUTPUT 4
Dual-in-Line Package
-,
ADOAESS
INPUT A
1
16 Vee
15 ADDRESS
INPUTB
14 AODAESS
INPUTe
13 ADDAESS
INPUT 0
12 DATA
INPUT 4
ElmIT
Wl!1Tl[
3
tNAB[[
DATA 4
1NPUT1
DATA 5
WRITE
1JllffilT,
ENABLE
111lAfA
i!iffiilif'
DATA 6
INPUT 2
iiM 7
MiMOiiY
ENABLE
~
10 DATA
INPUTJ
0ii'fPifi'2
• I!lrni
1!1ITI'IIT3
GND
INPUTA
TOP VIEW
TL.lFI5925·2
Order Number
MM54C989J or MM74C989J
See NS Package J16A
INPUTB
Order Number
MM54C989N or MM74C989N
See NS Package N16A
INPUTC
INPUTB
6-160
f
Absolute Maximum Ratings
Operating Conditions
(Note 1)
Voltage at Any Pin
Supply Voltage (VCCI
MM54C989
MM74C989
--{).3V to VCC + 0.3V
Package Dissipation
500mW
Absolute Maximum Vee
7.0V
Lead Temperature (Soldering, 10 seconds)
300°C
Temperature (TAl
MM54C989
MM74C989
MIN
MAX
UNITS
4.7
4.75
5.5
5.25
V
V
+125
+85
°c
°c
-55
-40
Operating VCC Range
3.0V to 5.5V
Standby VCC Range
1.5V to 5.5V
-
DC Electrical Characteristics
MM54C989/MM74C989
(Minimax limits apply across the temperature and power supply range indicated).
PARAMETER
SYMBOL
VIN(l)
Logical "I" Input Voltage
VIN(O)
Logical "0" I nput Voltage
CONDITIONS
MIN
TYP
MAX
UNITS
V
VCe-l .5
0.8
1
IIN(l)
Logical "I" Input Current
VIN = 5V
IIN(O)
Logical "0" I nput Current
VIN = 0
VOUT(l)
Logical "1" Output Voltage
10 = -360Ji.A
2.4
V
10 = -150Ji.A
VCC-0.5
V
VOUT(O)
Logical "0" Output Voltage
10 = 360Ji.A
10Z
Output Current in High Impedance State
VO= 5V
ICC
Supply Current (Active)
VO= 0
0.005
V
-1
-(l.005
Ji.A
0.4
0.005
-1
ME= 0,
1
-{l.005
0.05
Ji.A
V
Ji.A
Ji.A
150
Ji.A
3
Ji.A
VCC = 5V
ICC
Supply Current (Stand·By)
AC Electrical Characteristics
ME= 5V
MM54C989/MM74C989
T A = 25°C, VCC = 5V, CL = 50 pF
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
tACC
Access Time F rom Address
140
500
ns
tPD
Propagation Delay From ME
110
360
ns
tSA
Address Input Set-Up Time
140
30
ns
tHA
Address I nput Hold Time
20
15
ns
tME
Memory Enable Pulse Width
200
80
ns
tME
Memory Enable Pulse Width
400
100
ns
ns
tSD
Data Input Set-Up Time
0
tHO
Data Input Hold Time
30
20
ns
tWE
Write Enable Pulse Width
140
70
ns
llH, tOH
Delay to TRI-STATE ,CL = 5 pF, RL = 10k, (Note 4)
100
CIN
Input Capacity, Any Input, (Note 2)
5
pF
COUT
Output Capacity, Any Output, (Note 2)
8
pF
CPO
Power Dissipation Capacity, (Note 3)
350
pF
200
ns
CAPACITANCE
6-161
AC Electrical Characteristics
(Continued)
=-55°C to +125°C, VCC = 4.5V to 5.5V. CL = 50 pF
MM74C989: TA = -40°C to +85°C, VCC = 4.75V to 5.25V. CL = 50 pF
MM54C989: TA
SYMBOL
MM54C989
PARAMETER
MM74C989
MAX
MIN
MIN
UNITS
MAX
tACC
Access Time From Address
500
620
ns
tPD1, tpDO
Propagation Delay From ME
350
430
ns
tSA
Address Input Set· Up Time·
150
140
ns
tHA
Address Input Hold Time
50
60
ns
tME
Memory Enable Pulse Width
250
310
ns
tME
Memory Enable Pulse Width
520
400
ns
tSD
Data Input Set·Up Time
0
0
ns
tHD
Data input Hold Time
60
50
ns
!WE
Write Enable Pulse Width
220
180
ns
tl H, tOH
Delay to TRI-STATE®, (Note 4)
~
200
ns
200
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of th~ device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: CPO determines the no load AC power consumption for any CMOS devi,ce. For complete explan~tion see 54C/74C Family Characteristics
application ngte, AN-SO.
Note 4: See AC test circuit for tlH. tOH.
Truth Table
ME
WE
OPERATION
CONDITION OF OUTPUTS
TRI-STATE
L
L
Write
L
H
Read
H
L
Inhibit, Storage
H
H
Inhibit. Storage
Complement of Selected Word
.
TRI-STATE
TRI-STATE
\
AC Test Circuits
All Other AC Tests
tlH
toH
VCC'
q
~
:~ 10k
I
DATA
OUTPUT
DATA
DUTPUT
-"-SOpF
T'
TlIF15925·3
...
,.~ f""
~
":'
TlIF/5925·4
6-162
DATA
OUTPUT
..L'SOPF
J'
•
TLlF15925·5
Switching Time Waveforms
Read Cycle (Note 1)
Write Cycle (Note 1)
vcc----t--.r----....
"ii"E"MDlfl
EiiAii:E
MEMORY
ENABLE
vcc---h----'""'"'\.
vcc------,
ADDRESS
INPUT
ADDRESS
INPUT
~ VCC--------------1~------
m
.------------TRI.STATE" CONDITION
TUFf5925·6
TL/F15925-7
Read-Modify-Write Cycle (Note 1)
-
tOH
vcc---t-,----"'\.
ENABLE
AODRESS
vcc-----......
LAtCHED AODRESS
INPUT
J
PD
~
vee
lAce
0-_____ ~.!!.A!!.' !!''!!''2!!N__
0.1 Vee
TUF15925-9
TRI·STATE CONDITION
- - - - -
L
Q
')c
xOW!
WJiiiE
ENABLE
DA~:
.':jE;
vcc-------------~
v ------------cc
DATA
iliff
vee
o
0.1 Vee
- - - TRI-STATE
TL/F15925-B
Note 1: MEMORY ENABLE must be brought high for tME ns between every address change.
Note 2: tr = If = 20 ns for all inputs.
6-163
TL/FI5925·10
•
~,National
~ Semiconductor
MM70C95/MM80C95, MM70C97/MM80C97 TRI·STATE®
Hex Buffers
MM70C96/MM80C96, MM70C98/MM80C98 TRI·STATE
Hex Inverters
~
o
i
:E
:E
General Description
Features
These gates are monolithic complementary MOS (CMOS)
integrated circuits constructed with N- and P-channel
enhancement mode transistors. The MM70C95/MM80C95
and the MM70C97/MM80C97 convert CMOS or TTL outputs to TRI-STATE outputs with ,no logic inversion,
the MM70C96/MM80C96 and the MM70C98/MM80C98
provide the logical opposite of the input signal. The
MM70C95/MM80C95 and the MM70C96/MM80C96 have
common TRI-STATE controls for all six devices. The
MM70C97/MM80C97 and the MM70C98/MM80C98 have
two TRI-STATE controls; one for two devices_and one for
the other four devices. Inputs are protected from damage
due to static discharge by diode clamps to Vcc and GND.
- Wide supply voltage range
CD Connection Diagrams
f3
~
:E
:E
'N,
OUTs
IN,
1.0V
-_High noise immunity
0.45 Vcc (typ.)
drive 1 TTL Load
- TTL compatible
Applications
Typical propagation delay
into 150pF load is 40ns.
- Bus drivers
(Dual-In-Line Packages)
MM7OC951MMBOC95
0lS2
3.0Vto 15V
- Guaranteed noise margin
OUTs
MM7OC961MMBOC96
'.,
ati'
f3
2
:E
:E
iii
f3
~
:E
:E
TOPVIEW
TOP VIEW
TLIFI5907.'
Order Number MM70C95J, MM70C95N,
MMBOC95J or MMBOC95N
See NS Package J16A or N16E
MM7OC971MMBOC97
MM70C9BIMMBOC9B
018 4
TOPVIEW
TLIFI5907.2
Order Number MM70C96J, MM70C96N,
MMI!OC96J or MMBOC96N
See NS Package J16A or N16E
TL/F/5907-3
IN)
OUT 1
IN2
OUT 2
TOPVIEW
Order Number MM70C97J, MM70C97N,
MMBOC97J or MM80C97N
See NS Package J16A or N16E
IN J
OUT J
GNO
TLIFI5907·4
Order Number MM70C9BJ, MM70C98N,
MM80C98J or MMBOC9BN
See NS Package J16A or N16E
6-164
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature Range
MM70CXX
MM80CXX
s:
s:
(Note 1)
-0.3 V to Vee + 0.3 V
-55'C to +125'C
-40'C to +85'C
Storage Temperature Range
Package Dissipation
Power Supply Voltage (Vee)
Lead Temperature (Soldering, 10 sec.)
-65'Cto+150'C
500mW
18V
300'C
~
(")
-ss::
CO
U1
~
oCO
.SJ1
:s::
DC Electrical Characteristics
Symbol.
MinImax limits apply across temperature range unless otherwise noted
Parameter
Conditions
Min
Typ
Max
Units
CMOS to CMOS
VIN(l)
Logical "1" Input Voltage
VIN(O)
Logical "0" Input Voltage
VOUT(l)
,
Logical "1" Output Voltage
3.5
8.0
Vee=5.0V
Vee = 10V
Vee=~·OV
1.5
2.0
Vee=10V
4.5
9.0
Vee=5.0V
Vee = 10V
VOUT(O)
Logical "0" Output Voltage
Vee =5.0V,
Vee=10V
IIN(l)
Logical "1" Input Current
Vec = 15V
IIN(O)
Log ical "0" Input Current
loz
Output Current in High
Impedance State
Vce=15V, Vo=15V
Vee=15V, Vo=OV
Supply Current
Vcc = 15V
Icc
V
V
en
V
V
1.0
"A
-0.005
0.005
-0.005
1.0
-1.0
0.01
15
"A
"A
"A
"A
TTL Interlace
VIN(l)
VIN(O)
Logical "1" Input Voltage
70C
80C
Vec =4.5V
Vee =4.75V
Volta~e
70C
80C
Vee =4.5V
Vee =4.75V
Vee =4.5V, 10=-1.6mA
Vee =4.75V,1 0 =-1.6mA
70C
Vee =4.5V, lo=1.6mA
Vee =4.75V,l o =1.6mA
Logical "0" Input
VOUT(l)
Logical "1" Output Voltage
70C
80C
VOUT(O)
Logical "0" Output Voltage
aoc
V
V
Vee -1.5
Vee -1.5
0.8
0.8
2.4
2.4
V
V
V
V
0.4
0.4
-ss::
CO
0.5
1.0
-1.0
~
~
en
V
V
V
V
0.005
s:
V
V
o
oCO
s:
s:
......
o
oCO
-ss::
......
CO
o
oCO
......
~
s:
s:
......
o
oCO
-ss::
CO
~
oCO
CO
Output Drive (Short Circuit Current)
ISOURCE Output Source Current
'Vcc=5.0V, VIN (1)=5.0V
TA = 25'C, VOUT = 0 V
-4.35
mA
ISOURCE Output Source Current
Vec = 10V, VIN (l) = 10V
TA=25'C, VOUT=OV
-20
mA
ISINK
Output Sink Current
Vee =5.0V, VINIO)=OV
TA = 25'C, VOUT = Vee
4.35
mA
ISINK
Output Sink Current
Vcc = 10 V, VINIO) = 0 V
TA = 25'C, VOUT = Vee
20
mA
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: Cpo determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family
Characteristics application note AN-gO.
,
6·165
AC Electrical Characteristics
Symbol
TA = 25°C, CL =50pF, unless otherwise noted.
Parameter
Conditions
Min
Typ
Max
Units
60
25
70
35
100
40
150
75
ns
ns
ns
ns
85
40
95
45
160
80
210
110
ns
ns
ns
ns
80
50
100
70
70
50
135
90
180
125
125
90
170
125
ns
ns
ns
ns
ns
ns
ns
ns
200
ns
ns
ns
ns
ns
ns
ns
ns
tpdO, tpdl Propagation Delay Time to a Logical "0" or
Logical "1" from Data Input to Output
Vcc=5.0V
Vcc=10V
Vcc=5.0V
Vcc=10V
MM70C95/MM130C95, MM70C97/MM80C97
MM70C96/MM80C96, MM70C98JMM80C98
tpdO, tpdl Propagation Delay Time to a Logical "0" or
Logical "1" from Data Input to Output
Vcc=5.0V,
Vcc =10V,
Vcc=5.0V,
Vcc = 10V,
MM70C95/MM80C95, MM70C97/MM80C97
MM70C96/MM80C96, MM70C98/MM80C98
tlH, tOH
Delay from Disable Input to High Impedance
State, (from Logical "1" or Logical "0")
RL = 10k, GL = 5.0pF
Vcc =5.0V
Vcc=10V
Vcc=5.0V
Vcc=10V
Vc e=5.0V
Vee=10V
Vee=5.0V
Vee=10V
MM70C95/M M80C95
MM70C96/MM80C96
MM70C97/MM80C97
MM70C98/MM80C98
tHl, tHO
CL=150pF
CL =150pF
CL =150pF'
CL = 150pF
Delay from Disable Input to Logical "1"
Level (from High Impedance State)
90
70
RL =10k, CL =50pF
MM70C95/MM80C95
MM70C96/MM80C96
MM70C97/MMaOC97
MM70C98/MM80C98
Vce =5.0V
Vee=10V
Vce =5.0V
Vee = 10V
Vee =5.0V
Vcc=10V
,Vce=5.0V
Vee=10V
120
50
130
60
95
40
120
50
90
225
110
175
80
200
90
CIN
Input Capacitance
Any Input (Note 2)
5.0
pF
COUT
Output Capacitance TRI·STATE
Any Output (Note 2)
11
pF
Cpo
Power Dissipation Capacitance
(Note 3)
60
pF
Truth Table!)
.
MM7OC95/MM8OC95
DISABLE
DIS,
0
0
0
1
1
INPUT
DIS2
0
0
1
0
1
MM7OC96/MM8OC96
INPUT
OUTPUT
0
1
X
X
X
0
1
DISABLE
DIS,
0
0
0
1
1
H·z
H·z
H·z
MM7OC97/MM8OC97
DISABLE
DIS4'
INPUT
DIS2
INPUT
0
0
X
1
0
0
1
X
0
1
X
X
INPUT
DIS2
INPUT
OUTPUT
0
0
1
0
1
0
1
X
X
X
1
0
H·z
H·z
H·z
MM7OC98/MM8OC98
DISABLE
DIS4
OUTPUT
, 0
1
0
0
X
1
H·z·
H-z**
'Output 5·6 only
• 'Output 1·4 only
X = Irrelevant
6·166
INPUT
0182
0
0
1
X
INPUT
OUTPUT
0
1
X
X
1
0
H.. z·
H·z·*
:s:
:s:
.....
Typical Performance Characteristics
0
Propagation Delay VI
Load Capacitance
~
160
!...
Vee - 3.OV
!
~
...;:;'"
100
"z
";::
~
Vee
'"
co
~
"',!!;!.
"'"
=:
"
~
Vee:::l lOV
I
0
0.50
0
CD
,91
:s:
0.25
3:
~
~
~
t"'T"
J.
c.n
3:
3:
Q)
0.75
~
50
lE
CD
...z
T.·25'C
SEE AC TEST CIR CUlT
>
0
Il.tpd/pF vs
Power Supply Voltage,
~
Vee:l 15V
0
-
1
50
:;;
150
100
CL - LOAD CAPACITANCE
5.0
IpFI
10
Vee -POWER SUPPLY VOLTAGE
TLlF159D7·5
:s:
:s:
CO
P-Ch.nne' Output Ori.e
@
0
0
25°C
CD
100
1111
90
III
-10
Vee'" 15V
80
~
60
.s
Vee'" lOV
60
H-t .
40
j
II
30
. 20
~ h~d~
10
0
2
4
6
Vee
-3~
-50
VOUT
12
14
16
0
0
-::s:.....s:
i-'"
M
-70
10
:s:
:s:
.....
=lOV
CD
1111
-80
8
CD
~
I-'
-40
-1;0
III
0
Vee" 5V
111
-20
70
.
CD
IVI
TUF/5907-6
N..channel Output Drive @ 2SoC
..s~
J
CD
15
16
14
IV)
12
CO
0
10
8
6
4
2
0
0
CD
~
.....
Vee - VOUT (V)
:s:
TLIFI5907·8
TlIF/5907·7
3:
Schematic Diagrams
.....
MM70C95/MM8OC95 TRI-8TATE
r--------,
ONE Of SIX DEVICES
1
--I+I:;.r~
-+,..;."T_.-_-___
INJIO-'_ _
CONTROLS FOR All
SIX DEVICES
DIst!
V-01-...........
0-+-"--'"
" LI _ _ _ _ _ _ -1-II 11...-_
I
_ _"'"
_ _ -1I
DIst!
_
" IL _ _ _ _ _ _ -1
IL _ _ _ _"'"
_ _ -.J
TlIF/5907·1D
TlIFI5907·9
MM70C97/MM80C97 TRI-8TATE
MM7OC98IMM80C98 TR'·STATE
r--------,
r--------,
ONE OF TWO/FOUR DEVICES
1
IN/I
o-----+----H.-I.~
ONE Of TWO
TRI·STATE CONTROLS
r---
DISJ2
~
"':-''i',,_-+-I
2
I
I
V 18n)
T- = T A + 7.2 O,A [IDA 2 (Duty Cycle A I + lOB 2 (Duty CycleB I]
I
The output "ON" resistance, RON, is a function of the
junction temperature, T j , and is given by:
RON = 9 (Tj - 25) (0.008) + 9
(1)
1-0.0720,A [loA2(DutyCycleAI+loB2(DutyCycieBI]
Equations (1). (4). and (6b) can be used in an iterative
method to determine the output current, output resistance and junction temperature.
and Tj is given by:
(2)
where T A = ambient temperature, OjA = thermal resistance, and POAV is the average power dissipated within
the device. P OAV consists of normal CMOS power
terms (due to leakage currents, internal capacitance,
switching, etc.) which are insignificant when compared
to the power dissipated in the outputs. Thus, the output
power term defines the allowable limits of operation and
includes both outputs, A and B, Po is given by:
2
Po = lOA
2
RON + lOB
RON,
(3)
_______
.J
OUTPUT A
OUTPUTS
Vl
TLlFf5912·10
For example, let Vee = 15V, R LA = 1DOn, R LS = 1Don,
V L = OV, TA = 25°C, OjA = 110°C/W, Duty CycleA=
50%, Duty Cycles = 75%_
Assuming RON = 11 n, then:
where 10 is the output current, given by:
15
11 + 100
(4)
135.1 mA,
V L is the load voltage.
135.1 mA
lOB
The average power dissipation, POAV , is a function of
the'duty'cycle:
POAV = lOA 2 RON (Duty CycleA) +
(5)
and
T = TA+7.2 OjA [I OA 2 (DutyCycle A I+l oB 2 (DutyCycieBI]
I
1 - 0.072 OjA [IDA 2 (Duty Cycle A I + lOB 2 (Duty CycieB I]
IOB2 RON (Duty CycleB)
25 + i7.21 (1101 [(0.1351)2 (0.51 + (0:1351)2 (0.751]
where the duty cycle is the % time in the current source
state_ Substituting equations (1) 'and (5) into(?) yields:
Tj = T ... + OjA [9 (Tj - 25) (0.008) + 9]
,(6a)
T,=
T, = 52.6°C
and RON = 9 (Tj - 25) (0.008) + 9 =
[lOA 2 (Duty CycleA) + IOB2, (Duty CycleB)]
simplifying:
-1--~(O~.O-7-2~1~(1-10~1~[~(O-.1~3~5-1"12~(~0.~5~1-+~(0~.~13~5~1~12~(~0.~75~1]
9 (52.6 - 25) (0.008) + 9 = 1m
Applications
(See AN-l77 for applications.) .
6-172
:s::
:s::
~National
~
~ Semiconductor
C')
CD
.....
.....
MM74C911 4-Digit Expandable Segment
Display Controller
General Description
The MM74C911 display controller is an interface element
with memory that drives a 4-digit, 8-segment LED display_ The MM74C911 allows individual control of any
segment in the 4-digit display. The number of segments
per digit can be expanded without any external
components. For example, two MM74C911's can be
cascaded to drive a 16-segment alpha-numeric display.
The digit outputs directly drive the base of the digit
transistor when the control pin labeled Digit Input
Output, DiD, is low. When 010 is high, the digit lines
turn into inputs and the internal scanning multiplexer
is disabled.
When any digit line is forced high by an external device,
usually another MM74C911, the data information for
that digit is presented to the output. In this manner,
16-segment alpha· numeric displays, 24 or 32-segment
displays, or an array of discrete LED's can be controlled by the simple cascading of expandable segment
display controllers. All inputs except digit inputs are
TTL compatible and do not clamp input voltages above
The display controllers receive data information through
8 data lines a, b ... DP, and digit information through
2 address inputs K 1 and K2. The input data is written
into the register selected by the address information
when Chip Enable, CE, and Write Enable, WE, are low
and is latched when either CE or WE return high. Data
hold time is not required.
vcc·
Features
• Direct segment drive (100 mA·typ) TRI-STATE
• 4 registers addressed like RAM
• Internal oscillator and scanning circuit
• Direct base drive to digit transistor
• Segment expandability without ·external components
• TTL compatible inputs
• Power saver mode-5/lW (typ.)
A self·contained internal oscillator sequentially presents
the stored data to high drive (100 mA typ) TR I-STATE®
output drivers which directly drive the LED display.
The drivers are active when the control pin labeled Segment Output Enable, SOE, is low and go into TRI-STATE
when SOE is high. This feature allows for duty cycle
brightness control, or for disabling the output drive
for power conservation.
Truth Tables
Connection Diagram
Dual-In-Line Package
we..J
.2
•
u
Input Control
~CE
CE
~K2
b.2
~KI
c~
t--Sop
25
d...1
~Sg
e-.!!
~Sf
f-2
tE-vcc
g.2
~S.
OP-.!
~Sd
ollr...!.!!
~Sc
DIGIT
ADDRESS
K2
Kl
WE
OPERATION
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
Write digit 1
1
Latch digit 1
1
a
Write digit 2
1
1
Latch digit 2
1
a
Write digit 3
1
a
a
1
Latch digit 3
1
1
a
Write digit 4
1
1
1
Latch digit 4
1
X
X
X
Disable writing
Output Control
010
SOE
04
R
DIGIT LINES
03
02
OPERATION
01
GNO...2:!
~Sb
1
R
01 0E
a
a
a
r!l-S.
1
~m
a
a
a
a
a
Digits are now inputs
1
1
Display digit 1
1
r!!-04
1
1
1
1
1
a
a
a
a
a
a
a
a
a
a
Display digit 2
03.!!
a
a
a
a
a
02 11
a
a
a
a
a
TOPVIEW
1
1
TLt'F/5915·1
R
R
R
R
R
R
Disable segment outputs
Refresh display
Display digit 3
Display digit 4
Power saver mode
R = Refresh (digit lines sequentially pulsedl
Order Number MM74C911N
See NS Package N28B
x = Don't care
6-173
II
Absolute Maximum Ratings
Voltage at Any Pin Except Inputs
Voltage at Any Input Except Digits
Operating Temperature Range, T A
Storage Temperature Range
-0.3V to VCC + 0.3V
-0.3V to +15V
-40°C to +85°C
_65°C to +150°C
DC Electrical Characteristics
SYMBOL
(Notes 1 and 2)
PARAMETER
Package Dissipation
' Refer to PD(MAX) vs T A Graph
Operating VCC Range
3V to 6V
Absolute Maximum VCC
6.5V
Lead Temperature (Soldering, 10 seconds)
300°C
Min/max limits apply at _40°C ~ T J S +85°C, unless otherwise noted
CONDITIONS
MIN
TYP
MAX
UNITS
1.5
V
1.0
/lA
VIN(l)
Logical "1" Input Voltage
VIN(O)
Logical "0" Input Voltage
IIN(l)
Logical "1" Input Current
VCC = 5V, VIN = 15V
IIN(O)
Logical "0" 'I nput Current
VCC = 5V, VIN = OV
ICC
Supply Current (Normal)
VCC = 5V. Outputs Open
0.50
2.5
rnA
ICC
Supply Current (Power Saver)
VCC = 5V, SOE, 010 = "1",
1
600
pA
0.03
10
/lA
0.8
V
VCC = 5V
3.0
V
0.005
-1.0
-0.005
/lA
0'1, 02, 03, 04 = "0"
lOUT
TRI·STATE Output Current
VO=5V
VO=OV
-10
-0.03
CMOS/LPTTL INTERFACE
VIN(1)
Logical "1" Input Voltage
VCC = 4.75V
VIN(O)
Logical "0" Input Voltage
VCC= 4.75V
V
VCC-2.O
OUTPUT DRIVE
ISH
IDH
High Level Segment Current
High Leve'l Digit Current
VCC = 5V, Vo = 3.4V
TJ = 25°C
-60
-100
rnA
TJ = 100°C
-40
-60
mA
VCC = 5V, Vo = 3V
TJ = 25°C
-10
-20
mA
TJ = 100°C
-7
-10
mA
VCC= 5V, VO= lV
VOUT(l)
Logical "1" Output Voltage,
TJ = 25°C
-15
-40
mA
TJ = 100°C
-10
-15
mA
VCC = 5V, 10 = -360/lA
4.6
V
Any Digit
VOUT(O)
Logical "0" Output Voltage,
VCC = 5V, 10 = 360 /lA
0.4
V
Any Output
°JA
Thermal Resistance
(Note 3)
100
°C/W
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Range".
they are not meant to imply that the device should be operated at these limits. The table of "Electrical Characteristics" provides conditions for
actual device operation.
Note 2: All voltage reference to ground.
Note 3: OJA measured in free-air with device soldered into printed circuit board.
6·174
AC Electrical Characteristics
SYMBOL
3:
3:
~
VCC = 5V, tr = tf = 20 ns, CL = 50 pF
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0
ns
.....
tcw
Chip Enable to Write Enable Set-Up Time
TJ = 25°C
35
15
TJ = 125°C
50
20
ns
tAW
Address to Write Enable Set-Up Time
TJ=25°C
35
15
ns
TJ = 125°C
50
20
ns
tww
Write Enable Width
TJ = 25°C
400
225
ns
TJ=125°C
450
250
ns
tow
Data to Write Enable Set-Up Time
two
W,rite Enable to Data Hold Time
tWA
Write Enable to Address Hold Time
twc
Write Enable to Chip Enable Hold Time
t1 H, tOH
tH1.lHO
tDl, too
tlB
fMUX
COUT
Logical "1", Logicai "0" Levels intoTRI-STATE
TJ = 25°C
390
225
ns
TJ = 125°C
430
250
ns
TJ = 25°C
0
-10
ns
TJ=125°C
0
-15
ns
TJ=25°C
0
-10
ns
TJ=125°C
0
-15
ns
TJ = 25°C
55
30
ns
TJ = 125°C
75
40
ns
RL = 10k, CL = 10 pF
TJ = 25°C
275
500
ns
TJ=125°C
325
600
ns
TRI-STATE to Logical "1" or Logical "0"
RL = 10k, CL = 50 pF
Levels
T J = 25°C
325
600
ns
TJ = 125°C
375
700
ns
Propagation Delay From Digit Input to
TJ = 25°C
500
1000
ns
Segment Output
TJ = 125°C
700
1400
ns
Interdigit Blanking Time
TJ = 25°C
5
10
TJ = 125°C
10
20
f-Ls
TJ = 25°C
525
Hz
TJ = 125°C
375
Hz
Multiplex Scan Frequency
f-Ls
Input Capacitance
(Note 4)
5
7_5
pF
TRI-STATE Output Capacitance
(Note 4)
30
50
pF
Note 4: Capacitance guaranteed by periodic testing.
Switching Time Waveforms
TRI-STATE Waveforms
Write Data Waveforms
ADDRESS Vcc - - - - - . , - - - - - - - - - - - - - - . . ~--'--Kl, Kl
ADDRESS
o _ _---J '--_ _ _ _
_ VAUD
_ _ _ _- J ' - -_ __
CE Vee
o
Vee
.
!
o
iITO
SEGMENT
~ 'ew r-
~r
--------t----..-t=
-I
GN0---150
5
%
-1'OHvcc---,_---
OR DIGIT
OUTPUTS
------_t--+~---------_t-J
111%
TRI-STATf:
VOL
-'WA
o ------_t----~-~------~J
DATA Vee
Sa-SOP
Vcc
SOl OR
'Wel~
----+""""'\
CD
.....
Vcc
mOR
-'WD
I!llJ
DATA VALID
---~--_t---'
SEGMENT
OR DIGIT
'ow---
OUTPUTS
'-------"'0
TLlF15915·2
6-175
50"
".----:1", r
VON
'
'0% , - - TRI-STATE~)
GNll-----~---TLIF/5915-]
[II
Switching Time Waveforms
(Continued)
Multiplexing Output Waveforms
OIGITN
Ir-___I
~
Read Data Waveforms
I
ANY DIGIT
(NOTE 1)
-I i'"
I
DIGIT N+l
ANY SEGMENT
T= Iffmull
TLIFJ5915·5
TLlF15915·4
Note 1: All other digit lines are at a low level. DTO at a high level.
Functional Description
The MM74C911 display controller is manufactured on
standard metal gate CMOS technology. A single 5V
74 series TTL supply can be used for power and should
be bypassed at the VCC pin to suppress current transients.
written into. In normal operation, the internal multiplexer scans the registers and refreshes the display. In
cascaded operation, '1 MM74C911 serves as a master
refresh device and cascaded MM7 4C911's are slaved
to it through digit lines operating as inputs.
The digit outputs directly drive the base of a grounded
emitter digit transis.tor without' the need of a Darlington
configuration. If an MM74C911 is driving a digit transistor and also supplying digit information to a cascaded
MM74C911, base resistors are needed in the digit transistors to provide an adequate high level to the digit
inputs of the cascaded MM74C911.-
The MM74C911 appears to a microprocessor as memory
and to the user as a self-scan display. Since every segment is under microprocessor control, great versatility
is obtained.
Low power standby operation occurs with both SOE
and D 10 inputs high. This condition forces the
MM74C911 to a quiescent state typically drawing less
than, 1 Jl-A of supply current with a standby supply
voltage as low as 3V.
As seen in the block diagram, these display controllers
contain four 8-bit registers; anyone may be randomly
Block Diagram
Kl
K2
u------~----~
,
DP
D2
D4
~------~--------mo
TL/F/591&-6
6-176
Typical Performance Characteristics
:<
:<
oS
~
oS
...
.,~
...Ci
30
~
...
'"
60
~
C
90
I
w
I
24
u
w
u
~
16
.,'"
=>
!!'
120
3.0
3.5
4.0
4.5
VoUT (VI
32
5.0
VOUT (VI
TLIF15915-1
Power Dissipation vs.
Temperature for
Plastic Packages
TUFI5915·6
Power Dissipation vs.
Temperature for
Ceramic Packages
40
VCC' 5V
TA'25'C
(NOTE 21
:<
oS
i
...z
I
32
2.0
1.00
\
~
~
24
0.75
~
~
16
0.50
1\
w
~
~ 0.25
w
'"
\
~
!
\
;\
0.5
JA
Thermal Resistance
(Note 3)
°elW
100
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Range" they are not meant to imply that the device should be operated at these limits. The table of "Electrical Characteristics" provides '
conditions for actual device operation.
Note 2: All voltages reference to ground.
Note 3: E>JA measured in free air with device soldered into printed circuit board.
AC Electrical Characteristics
SYMBOL
tew
tAW
tww
Vee = 5V, tr = tf = 20 ns, eL = 50 pF
MIN
TYP
Chip Enable to Write Enable
TJ = 25°C
35
15
ns
Setup Time
TJ = 125°C
50
20
ns
Address to Write Enable
TJ = 25°C
35
15
ns
Setup Time
TJ= 125°C
50
20
ns
Write Enable Width'
TJ = 25°C
400
225
ns
TJ = 125°C
450
250
ns
PARAMETER
CONDITIONS
6·181
MAX
UNITS
AC Electrical Characteristics
SYMBOL
(Continued) VCC = 5V, tr = tf = 20 ns, CL = 50 pF
PARAMETER
CONDITIONS
Data to Write Enable Setup Time
tow
Write Enable to Data Hold Time
two
Write Enable to Address Hold Time
tWA
twc
t1H, tOH
225
MAX
ns
TJ=125°C
430
250
ns
TJ = 25°C
0
-10
ns
TJ=125C
0
-15
ns
TJ = 25°C
0
-10
ns
TJ = 125°C
0
-15
ns
UNITS
TJ = 25°C
50
30
ns
Hold Time
TJ = 125°C
75
40
ns
Logical "1", Logical "0" Levels
RL = 10k, TJ = 25°C
275
500
ns
lnto TRI-STATE
CL = 10 pF, TJ = 125°C
325
600
ns
RL = 10k, TJ = 25°C
325
600
ns
CL - 50pF, TJ = 125°C
375
700
ns
Logical "0" Level
Interdigit Bl,anking Time
Multiplex Scan Frequency
fMUX
TYP
390
Write Enable to Chip Enable
tH1,tHO _ TRI-STATE to Logical "1" to
tlB
MIN
TJ = 25°C
TJ=25°C
5
10
/15
TJ=125°C
10
20
/1S
Hz
TJ = 25°C
350
TJ= 125°C
250
Hz
CIN
I nput Capacitance
Note 4
5
7,5
pF
COUT
TR I-STATE Output Capacitance
Note 4
30
50
pF
Note 4: Capacitance is guranteed by periodic testing.
Switching Time Waveforms
ADDRESS
Vee
~~5~
AOORESSVAUO
Kl.K2.KJ
0
Vee
CE
0
WC
\.
-I
lew
'
r-
1J-
0
-I
--tAWDATA Vee
a,b,c,d,OP
OUTPUTS
'0"1-
--1
",----
10%
TRI·STATE
-tWA
~r
Vee
WE
SEGMENT
~
f-tWD
DATA VALID
0
~--'OW---
SEGMENT
OUTPUTS
---1
50
%
~-
,01'
t
TRI.STATE' •
...... _ _ _ _
'ww
,
TLlF15916·2
TL/FI5916·3
Multiplexing Output Waveforms
I
DIGITN
~
T
I
S
-I itlB
DIGIT N+l
T" l/fmu)(
I
I
L
TLIF15916·4
6-182
,
Functional Description
,-,
,-,
Character Font
I -,
-, '-I ,- -, ::1 ,-, ~, r cl
Hi·Z
Ll
II::
MM74C912
Hi·Z
LI
I -I -I
II::
X
X
X
X
X
0
0
0
0
0
0
Input A 2 0
Data B 21
C 22
D 23
DP
Output Enable SOE
::I
C C
::1 '-I7 ::1
1::1
1
0
0
0
0
0
0
0
0
0
0
CI CI CI
I CI
C
::1 CI
MM74C917
0
0
0
0
0
0
-I CI CI
CI
I 1::1 ::1 1::1
0
0
1
0
0
0
0
0
0
L
1
1
0
0
0
0
0
0
0
0
0
0
0
0
- 0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
I- I- II:: 1- 1-.
0
0
0
0
0
1
0
Segment Identification
TLlF/59165
The MM74C912, MM74C917 display controllers are
manufactured using metal gate CMOS technology. A
single 5V 74 series TTL supply can be used for power
and should be bypassed at the VCC pin.
As seen in the block diagram, these display controllers
contain six 5·bit registers; anyone of which may be
randomly written. The internal multiplexer scans the
registers and refreshes the display. This combination of
write only memory and self·scan display makes the
display controller a "refreshing experience" for an over·
burdened microprocessor.
All inputs are TTL compatible; the segment outputs
drive the LED display directly through current limiting
resistors. The digit outputs are designed to directly drive
the base of a grounded emitter digit transistor without
the need of a Darlington configuration.
Block Diagram
Wl-----;:::==[)o-----,
SOE
s.
s,
s,
CE
"
S,
"s,
s".
D1
02
OJ
D.
0'
d.
os;
Tl/FI5916·6
6-183
~.-----------------------------------------------------------------------~
f3..-
~
:E.
:E
C\i
..0)
o
~
:E
:E
Typical Performance Characteristics
ISH vs VOUT
IOH vs VOUT
II
Vee'" 5V
".s...
ISEE NOTE 1)
30
:>
...
~
T)125;-
:>
...z
0
60
I
90
./'"
I
u
lZ0
:>
'"
El
/"VI
".s...
~
:>
...
:>
...c;
v,.J~zn
/
10
0
c;
15
I
w
u
'"
:>
0
V
ZO
~
150
Z.5
3.0
3.5
4.0
4.5
5.0
1.0
VOUT IV)
Z.O
3.0
4.0
TLfF/5g1a-8
TLlF15916·7
Power Dissipation'vs.
Temperature for
Plastic Packages
IAVG vs RUM
1,00
1\
~
z
~ 0,75
:iis
0.50
w
Power Dissipation vs.
Temperature for
Ceramic ,Packages
~
15
\
~
~
:ia
'\
I
~
~ 0.25
10
ZO
30
-50 -25
40
5.0
VOUTIV)
25
50
75
AMBIENT TEMPERATURE
SEGMENT RESISTOR (OHMS) TlIF15916-9
I
\
1.5
\
1.0
"
0,5
-55 -25
100 125
re)
Z.O
0
25
50
75 100 125
AMBIENT TEMPERATURE I'C)
TLlF15916·10
Tl/FJ5916·11
Note 1: Segment outputs if shorted to ground will exceed maximum power dissipation of the device.
Note 2: VeE is the saturation voltage of the digit drive transistor.
Segment Output Structure
Digit Output Structure
Vee
RS
TO TAI-STATE0\
CIRCUIT
Rs
SEGMENT
DUTPUT
~
TO DIGIT
MUl rlPLEXER
TlIF15916-13
Input Protection
Vee
ANV~n
INPUT
TLiF/5916-12
BV'''V!
BV", 1V
':" ':"
TLIF15916·14
6·184
~---------------------------------------------------,~
Typical Application
~
~
Q
....
j')
~
~
ADDRESS
DECODE
RILO
~p
ADDRESS
BUS
r
Al
AD
8x30Q
CE
SDP
Sg
Sf
S.
Sd
Sc
Sb
Sa
WE
K3
K2
Kl
,-, i,
,-, ,-,
,-,. ,--,.,--,. _.
.- .
NSB5921
U
-
U
U
"
-
U
MM74C9121
MM74C917
01
04
D3
~p
DATA 02
BUS
01
DO
OP
d
02
03
04
05
06
TUF/591B-15
6·185
~
(")
....
...,
CD
~National
'
~ Semiconductor
MM74C925, MM74C926, MM74C927, MM74C928 4-Digit
Counters with Multiplexed 7-Segment Output Drivers
General Description
carry·out is an overflow indicator which is high at
2000, and 'it goes back low only when the counter is
reset. Thus, this is a 3 1/2·digit counter.
These CMOS counters consist of a 4·digit counter, an
internal output latch, NPN output sourcing drivers for
a 7·segment display, and an internal multiplexing'
circuitry with four multiplexing outputs. The multi·
plexing circuit has its own free·running oscillator,
and requires no external clock. The counters advance
on negative edge of clock. A high signal on the Reset
input will reset the counter to zero, and reset the carry·
out low. A low signal on the Latch Enable input will
hitch the number in the counters into the internal out·
put latches. A high signal on Display Select input will
select the number in the counter to be displayed; a low
level signal on the Display Select will select the number
in the output latch to be displayed.
Features·
3V to 6V
Wide supply voltage range
1V
Guaranteed noise margin
0.45 Vee (typ.)
High noise immunity
High segment sourcing current
40 mA
@V ee - 1.6V, Vee = 5V
• Internal multiplexing circuitry
•
•
•
•
Design Considerations
The MM74C925 is a 4·decade counter and has Latch
Enable, Clock and Reset inputs.
Segment resistors are desirable to minimize power
dissipation and chip heating. The DS75492 serves as a
good digit driver when it is desired to drive bright
displays. When using this driver with a 5V supply at
room temperature, the display can be driven without
segment resistors to full illumination. The user must use
caution in this mode however, to prevent overheating of
the device by using too high a supply voltage or by
operating at high ambient temperatures.
The MM74C926 is like the MM74C925 except that it
has a display select and a carry·out used for cascading
counters. The carry·out signal goes high at 6000,
goes back low at 0000.
The MM74C927 'is like the MM74C926 except the
second most significant digit divides by 6 rather than 10.
Thus, if the clock inpu,t frequency is 10Hz, the display
would read tenths of seconds and minutes (i.e., 9:59.9).
The input protection circuitry consists of a series resistor,
and a diode to ground. Thus input signals exceeding
Vee will not be clamped. This input signal should not be
allowed to exceed 1 5V.
'
The MM74C928 is like the MM74C926 except the most
significant digit divides by 2 rather than 10 and the
Connection Diagram (Dual·ln·Line Packages)
CURl
OUT RESET
ClOC.Pout
tc..,
TL/F15919·2
Order Number MM74C925N
See NS Package N16E
Order Number MM74C926N,
MM74C927N or MM74C928N
See NS Package N18A
Order Number MM74C925J
See NS Package J16A
Order Number MM74C926J,
MM74C927J or MM74C928J
, See NS Package J18A
Functional Description
Asynchronous, active high
Reset
Display
Select~
Segment Output
High, displays output of counter
Low, displays output of latch
Digit OutPlJt '
Latch Enable
High, flow through condition
Low, latch condition
Clock
Negative edge sensitive
Carry·out
6·186
Current sourcing with 40 mA @
VOUT = Vee - 1.6V (typ.)
Also, sink capability = 2 LTTL
loads
Current sourcing with 1 mA @
VOUT = 1.75V. Also, sink capa:
bility = 2 LTTL loads
2 LTTL loa9s. See carry·out
waveforms.
Absolute Maximum Ratings
(Note 1)
Voltage at Any, Output Pin
Gnd - 0.3V to Vee+0.3V
Voltage at Any Input Pin
Gnd - 0.3V to +lSV
--40°C to +8SoC
Operating Temperature Range (T A)
"'-6SoC to +lS0°C
Storage Temperature Bange
DC Electrical Characteristics
SYMBOL
Package Dissipation
Refer to PD(MAX) vs T A Graph
Operating Vee Range
3V to 6V
6.SV
Vee
Lead Temperature (Soldering, 10 seconds)
300°C
MinImax limits apply at --40°C 5 T j
PARAMETER
CONDITIONS
5 +8SoC, unless otherwise noted.
MIN
TYP
MAX
UNITS
CMOS TO CMOS
V 1N {1)
Logical "1" Input Voltage
Vee = 5.0V
VINIO)
Logical "0" Input Voltage
Vee = 5,OV
V OUT(lI
Logical "1" Output Voltage
Vee = 5.0V. 10 = -10'j.(A
V
3.5
1.5
V
V
4.5
(Carry·out and Digit Output
Only)
VOUT(OI
Logical "0" Output Voltage
Vee = 5.0V, 10 = 10,j.(A
IINI1I
Logical "I" Inp'ut Current
Vee = 5.0V, VIN = 15V
IIN(OI
Logical "0" Input Current
Vee = 5.0V. VIN = OV
lec
Supply Current
Vee = 5.0V. Outputs Open Circuit.
0.005
-1.0
0.5
V
1.0
j.(A
j.(A
-0.005
20
1000
j.(A
VIN = OV or 5V
CMOS/LPTTL INTERFACE
V INI1I :
Logical "'" Input Voltage
Vee =4,75V
VINla)
Logical "0" Input Voltage
Vee = 4,75V
VOU T(1)
Logical "'" Output Voltage
(Carry·Out and Digit
Vee =4.75V,
V
Vcc-2.0
0.8
V
V
2.4
10 = -360j.(A
Output Only)
VOUTIO)
Logical "0" Output Voltage
0.4
Vee = 4.75V.
V
10 = 360j.(A
OUTPUT DRIVE
VOUT
Output Voltage (Segment
Sourcing Output)
RON
Output Resistance (Segment
lOUT = -65 rnA, Vee = 5V. T j = 25°C
lOUT = -40 rnA. Vee = 5V
{ To = 'OO°C
T; = '50°C
Vcc-2.0
Vee -1.6
V ec -2
lOUT = -65 rnA. Vee = 5V. TI = 25°C
Sourcing Output)
10UT.= -40 rnA. Vee = 5V
{ T, = 'OO°C
T j = , 50°C
Output Resistance (Segment
Vee-'·3
V ee -1.2
V ee -l.4
V
V
V
20
32
30
40
35
50
0.6
0.8
n
n
n
%I"c
Output) Temperature Coefficient
ISOURCE
Output Source Current
Vee =4.75V. V OUT = 1.75V. T j = , 50°C
-1
-2
rnA
Vee = 5V, V OUT = OV. T j = 25°C
-1.75
-3.3
rnA
1.75
3.6
rnA
(Digit Output)
ISOURCE
Output Source Current
(Carry-out)
ISINK
Output Sink Current
Vee = 5V, V OUT = Vee. T j = 25°C
(A(( Outputs)
6 1A
Thermal Resistance
(Note 4)
MM74C925
MM74C926, MM74C927, MM74C928
75
100
°C/W
70
90
°C/W
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for, "Operating
Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides
conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3:. CPO determines the' no load ac power consumption of any CMOS device. For complete explanation see 54CI14C Family Characteristics
application n9te. AN·90.
Note 4: OjA measured in free-air with device soldered into printed circuit board.
6·187
•
AC Electrical Characteristics
SYMBOL
TA=25°C, CL =50pF, unless otherwise noted
PARAMETER
= 5,OV,
TYP
2
4
MHz
1,5
3
MHz
= 25°C
Tj = 100°C
250
100
320
125
ns
= 25°C
T, = 100°C
250
100
ns
T,
Square Wave Clock
tr,tf
Maximum Clock Rise or Fall Time
tWA
Reset Pulse Width
V~e
Vee
Latch Enable Pulse Width
tWLE
MIN
= 25°C
T, = 100°C"
CONDITIONS,
Vee
Maximum Clock Frequency
f MAX
Vee
MAX
= 5,OV,
UNITS
}1s
15
T,
= 5,OV
T,
= 5,OV
ns
320
125
ns
T,
2500
1250
ns
0
-100
Wait Time
= 25°C
T, = 100°C
0
-100
ns
tSET(R.LEI
Reset to Latch Enable Set-Up Time
Ti
= 25°C
320
160
ns
Tj
=100°C
400
200
ns
f MUX
1000
Hz
C'N
5
pF
tSET(CK,LEI Clock to Lateh Enable Set-Up. Time
Latch Enable to Reset
tLR
Vee
= 5.0V
Vee
= 5,OV
= 25°C
T, = 100°C
T,
Vee
= 5,OV
Multiplexing Output Frequency
Vee
=S,OV
Input Capacitance
Any Input (Note 2)
Typical Performance Characteristics
1
Typical Segment Current vs
Output Voltage
tOO , - - , - - , , - - , , , - , - - - ,
~
~
""~
~
'"
~
il
.
~
80
f--t-f-H'F-t--t---i
Maximum Power Dissipation
vs Ambient Temperature
.,
f--H---I.f-
40
f--t-/j'--t--t--t---i
20 f-~~-t--t--t---i
1600
~ 2000
: 1800
~ 1600
1400
~ 1200
~ 1000
'"
~
.x
:iii:
I
Typical Average Segment
Current vs Segment Resistor
Value
I
II
I· L ' L
II
MM74C926/MM74C927/MM74C928
MM74C925
800
600
400
~ 200
0:
~
5.0
40
3D
20
10
1
0_ 40 -20
0
20
40
60
80
Til. - AMBIENT TEMPERATURE ("CI
V OUT (V)
TLlF15919·3
tOO
10
20
MM74C925
40
50
60
70
=
Voltage across digit
MM74C926
RESET
V"
CARRY·
CLOCK
I+------t"<> CLOCK
OUT
LATCH
ENABLE
DISPLAY
SELECT
LATCH
ENABLE
AOUT
BOUT
COUT
DOUT
AOUT
BOUT
COUT
OOUT
GNO
GND
TlIF15919-6
TlIF15919·7
MM74C928
MM74C927
0"'+--....--<11---....- - ,
V"
CLOCK
DISPLA Y
SELECT
30
SEGMENT RESISTOR (nl TLlFI59195
Note. Vo
driver.
Logic and Block Diagrams
RESET
ns
ns
.§ 2200
~
60
3200
.-...!cLr--L,.--''-,--L,.--''-"l-----i.J
RESET
CARRY·
OUT
1+-------+"<> CLOCK
DISPLAY
SELECT
LATCH
ENABLE
LATCH
ENABLE
AOUT
BOUT
COUT
DOUT
AOUT
'NO
GND
BOUT
COUT
BOUT
TlIF15919-9
6-188
Segment Output Driver
FROM
DECODER
I nput Protection
INPUTn..-.AAAS
~
7V
TL/F/5919·11
TL/F/5919·10
Segment Identification
Common Cathode LED Display
MM74C926
MM14C925
M"14C927
MM74C92B
BV
~l~
OUTPUT
12 3'-1
!~~~~
67 a9
"
TL/FI5919-12
TLIFI5919·13
Switching Time Waveforms
Input Waveforms
Multiplexing Output Waveforms
1
CLOCK
r-l
'r-l
I
--.l 'L-J
L-J
____rlSl
t'lml
n
1-7IJ2T-II--IIJ2T
B,",
j--II$ETIR.LEI
1
Aoo'J!L..--_----I1
tSET,CKLE,l--1
LATCH
ENABLE
Carrv·Out Waveforms
_
MM14C!l26
CARRY·our
....
- -------
------'n
MM14C921
CARRY·OUT
COUT
RESET
CLOCK..Il.Jl.
'---
n.rLrL
r----I
---1
L-
COUNT
COUNT
5999-6000
9999-0000
r----I
----I
L-
COUNT
COUNT
5599-6000
9599-0000
DOUT
T~ If'MUX
TLIF/5919·14
TUF/5919-15
6-189
TUF/5919-16
I
.....
~
:E
:E
PRELIMINARY
~National
~ Semiconductor
Ilf
~
MM74C945, MM74C947 4-Digit Up/Down
~ Counter/Latch/Decoder Driver
:E
:E
General Description
Features
The MM74C945, MM74C947 are4-dlgltcounters fordlrectIy driving LCD displays. The MM74C945 contains a
4-decade up/down counter, output latches, counter/latch
select multiplexer and 7-segment decoders. Also Included
are the backplane oscillator/driver, segment drivers and
display blanking circuitry.
•
•
•
•
•
The MM74C947 differs from the MM74C945 In that It has
no counter/latch multiplexer, but provides true leading
zero blanking. All leading zeroes are automatically
blanked except the least significant digit, which can be
optionally blanked.
4-decade up/down count
Direct 4-digit drive for high contrast and long display life
Carry/borrow out for cascading counters
Schmitt trigger clock input
MM74C945 has display select to allow viewing of
counter or latch
• Store and reset Inputs allow operation as frequency or
period counter
• MM74C947 has true ripple blanking; least significant
digit may be optionally blanked
Both devices provide 28-segment outputs to drive a 4-diglt
display. Segment and backplane waveforms are generated internally, but can also be slaved to an external
signal. This facilitates cascading of multiple displays.
Connection Diagrams
Dual-In-Llne Package
Dual-In-Line Package
vcc
VCC
01
El
El
Cl
Gl
Gl
Bl
Fl
Fl
BACKPLANE
BACKPLANE
A2
A2
GNO
B2
STORE
C2
RESET
D2
CLOCK
D2
CLOCK
E2
ENABLE
E2
ENABLE
BLANKING
G2
LEADING ZERO OUTPUT (LZO)
SelECT
F2
LEADING ZERO INPUT (LZ,)
A3
CARRY
A3
CARRY
B3
UP/DOWN
C3
F4
D3
G4
03
E3
E4
E3
G3
04
G3
I
UP/DOWN
F4
F3
C4
F3
A4
B4
A4
TOP VIEW
25
16
17
E4
18
04
19
C4
20
B4
TOP VIEW
TL/FfS098-1
Order Number MM74C947N
See NS Package N40A
Order Number MMT4C945N
See NS Package N40A
6-190
G4
TLlF/5098·2
Absolute Maximum Ratings (Note 1)
Voltage at Any Pin
Operating Temperature Range
MM74C945/MM74C947
Storage Temperature Range
Package Dissipation
-0.3VtoVcc+ 0.3V
Operating Vcc Range
Absolute Maximum Vcc
Lead Temperature (Soldering, 10 seconds)
-40·Cto +85·C
-65·Cto +150·C
500mW
3.0Vt06.0V
6.5V
300·C
DC Electrical Characteristics Min'/max limits apply across temperature range, unless otherwise noted.
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
VT+ Positive Going Threshold
Voltage (Clock Only)
Vcc= 5V, VIN (0-5) V
2.5
2.9
3.25
V
VT- Negative Going Thresh91d
Voltage (Clock Only)
Vcc = 5V, VIN (5-0) V
1.5
2.2
2.4
V
Hysteresis (VT+ - VT':')
(Clock Only)
Vcc=5V
0.1
0.7
1.75
V
3.5
1.5
V
Logical "1" Input Voltage (VIN(l»
Vcc=5V
Logical "0" Input Voltage (VIN(O»
Vcc=5V
Logical "1" Output Voltage
(VOUTI1» (LZO and Carry)
Vcc= 5V, 10= -10p.A
Logical "0" Output Voltage
(VOUTIO» (LZO and Carry)
Vcc =5V, 10= +10 p.A
Clock Input Current IIIN I
Vcc = 5V, VIN = 5V/OV
Input Current @ Pins 29, 31, 33
and 34 (Note 2)
Vcc =5V, VIN=OV
Oscillator Input Current (Iosd
Vcc = 5V, VIN = OVl5V
Vcc = 5V, VIN = OV/5V
Oscillator Input Voltage
VIH(OSC)
VILIOSC)
DC Offset Voltage (Note 4)
When Driving Oscillator
Pin with External Signal
V
4.5
0.005
-2.0
Supply Current (IcC> (Note 3)
V
0.5
V
1.0
p.A
-12
-25
p.A
±1
±10.0
p.A
10
60
p.A
Vcc- 0.2
V
V
25
mV
0.2Vcc
Vcc=5V
CMOS/LPTTL INTERFACE
Logical "1:' Input Voltage
(VIN (1)
Vcc =4.75V
Logical "0" Input Voltage
(VIN(O»
Vcc =4.75V
Logical "1" Output Voltage
(VOU!(1) (LZO and Carry)
Vcc = 4.75V, 10 = - 360 p.A
Logical "0" Output Voltage
(VOUTlO» (LZO and Carry)
Vcc= 4.75V, 10=360 p.A
Vcc -1.5V
V
0.8
2.4
V
V
0.4
V
OUTPUT DRIVE (SHORT CIRCUIT CURRENT)
Output Source Current
(lsOURCE) (LZO and Carry)
Vcc =5V, VOUT=OV
TA =25·C
1.75
2.7
mA
Output Sink Current
(lSINK) (LZO and Carry)
Vcc = 5V, VOUT = 5V
TA = 25·C
1.75
3.2
mA
Output Source Current
(ISOURCE) (Segment Outputs)
Vcc= 5V, VOUT=OV
TA =25·C
1.4
2.0
mA
Output Sink Current
(I SINK ) (Segment Output)
Vcc= 5V, VouT =5V
TA =25·C
1.4
2.2
mA
Output Source Current
(lsoURCE) (Backplane Output)
Vcc= 5V, VOUT=OV
TA =25·C
12.6
15.0
mA
Output Sink Current
(ISINK> (Backplane Output)
Vcc= 5V, VouT =5V
TA =25·C
12.6
20.0
mA
6·191
AC Electrical Characteristics Tj = 25°C, C L= 50 pF, unless otherwise specified.
Symbol
Parameter
Conditions
tpdO, tpdl
Propagation Delay Clock to Carry
Vcc=5.0V
fCLK
Maximum Clock Frequency
Vcc =5.0V
tr, tf
Clock Ihput Rise or Fall Time
VCC= 5.0V
Min
2
Typ
Max
375
600
Units
ns
3
MHz
,
No Limit
tWA
Reset Pulse Width
Vcc=5.0V
WO
120
ns
tws
Store Pulse Width
Vcc=5.0V
150
80
ns
tSU(CK. S)
Clock to Store Set·Up Time
VCC= 5.0V
500
270·
ns
tSA
Store to Reset Wait Time
Vcc.=5.0V
280
170
ns
tSU(E. CK)
Enable to Clock Set·Up Time
Vcc=5.0V
140
80
ns
tRA
Reset Removal
Vcc=5.0V
50
0
ns
tSU(U/D. CK)
f BP
Up/Down to Clock Set·Up Time
VCC= 5.0V
300
190
ns
Backplane Output Frequency
Pin 36 Floating,
Vcc=5V
85
Hz
CIN
Input Capacitance
Logic Inputs (Note 2)
5
pF
trfs
Segment Rise/Fall Time
Cload = 200 pF
0.5
,"s
trfb
Backplane Rise/Fall Time
Cload = 5000 pF
1.5
,"s
fosc
Oscillator Frequency
Pin 36 Floating,
Vcc=5V
11
kHz
Nota 1: "Absolute Maximum Ratings" are those values: beyond which the safety of the device cannot be guaranteed. Except for "Operaling Range" they are
not meant to imply that the devices should be operated at these, limits. The table of "Electrical Characteristics" provides conditions for actual device
operation. ,
Note 2: Does not apply to backplane and oscillator pins.
Note 3: Display blanked. See Test Circuit. .
Note 4: DC of.fset voltage is the effective DC voltage the LCD will have between any segment and the backplane.
AC Waveforms
r
CLOCK
.'~
90%
OV
10%
t r- - .
Vee
STORE
p
50%
~- j - ~
~I tws - -
r--tRR----':\
.
- twR
-tSU(CK. S)--..
Vee
50~1f50%
RESET
ov
-tsR-
-tpd'-I
,
Vee
,
CARRY
50%
'.'
-tPd'-l
------(IF NO RESET) ~-- ""'\
ov
-I
Vee
ENABLE
UP/DOWN
\
V::
'0
\s0~/50%
•
OV
OV
50%
=3
-
IsUIUIU,
,
\50%
-tsuIE,eKI
50%
eKI
TLlF/S09a·3
;
6·192
Typical Characteristics
Backplane Frequency as a
Function of Oscillator
Capacitor (Cose)
Backplane Frequency as a
Function of Supply Voltage
120
N"
:.
>'"ffi
g 100
~
ffi
fii
Il:
w
~
".
!;!
i
A;
opF =
80
22 pF
60
40
-
0.----
100
80
24
3V TO 6V CURVES
INSIDE BAND
r--
m
w
60
~
40
..:
'"
I
20
z
.
\
".
220 pF
A;
o
1
20
!!!
16
>-
::>
57 pF
20
Operating Supply Current
(IsS> as a Function of Supply
Voltage (VDD)
o
1
~
W7f1'C
8::
~
,
::>
i
.Y
o
5D
100
150 -
200
o
CDSC-OSCILLATOR CAPACITANCE (pF)
'lnD-SUPPLY VOLTAGE (V)
"
VDD-SUPPLY VDLTAGE (V)
Tl/F/S098·13
TLIFISOOS-12
TUF/5098-11
.fA
A~
'" 12
i:l
y.........:::::~
o
-~f1'CJ
25°C
Test Circuit
Segment Identification
5Y
....------1+
11111-------,
---------------,I
Y+
osc
...----'''I BP
TUFJ5098-14b
Tr
36
35
Timing Diagrams
MM74C945
MM74C947
Carry Out Timing (Up Mode)
CLOCK
CARRY
COUNT
I
I
9997
999B
9999
DODD
Carry Out Timing (Down Mode)
CLOCK
CARRY
COUNT
l-_---"-_ _
0002
0001
~
0000
9999
TL./F/5Q98.6
• Each segment to backplane with 200 pF capacitor.
6-193
Block Diagrams
MM74C945
DIGIT 1 (LSD)
DIGIT 2
DIGIT 3
DIGIT 4 (MSD)
BLANKING ----+--"""1r--;jr---....---;l----1>---;jr---,
SELECT ----'t---"""1r-....,r---....---''t----1---'''ir---,
STORE
---t---r-"""1r~r--;--
....-;--;---1>--;--;--,
ClOCK
II~L."T"-"T.J
CARRY
-I1--...--r-;---4~-;-I-;-I-....-;--t---'
up/iITiWN
...-----....J
RESET _____...._____.....
~-----
OSCILLATOR
-----~l.-,.~I OSCILLATOR
~&~~,
______. . .
~~~~~LANE
MM74C94?
~IGIT
1 (LSD)
0lGIT3
DIGIT 2
DIGIT 4 (MSO)
LEADING
ZERO IN
IlZ!)
~ORE-~r---f--~---r--"""1r---f--~
ENABLE
CARRY
CLOCK
UP/DOWN
-iHf--. .-+-+-..........- i - - - i - -....-+-+---'
~ ~r-----...-----~~-----....- - - - - - - '
OSCILLATOR """1r--r---+
MASTER/
SLAVE
DETECTOR
6·194
Pin Description
Backplane In/Out-When the oscillator Input Is grounded
this pin is an input allowing an external device to generate
a backplane waveform. When the oscillator input is left
open this pin Is an output supplying backplane drive for
the display.
etc. digits can be driven with several counters. The maximum fanout of a master backplane driver is limited by its
total capacitive load, which is the sum of the slaved
backplane Input capacitances and the display backplane
capacitance. (The MM74C947 oscillator pin controls the
least significant digit blanking as weil.)
Oscillator-The oscillator frequency may be lowered by
tying a capacitor (Cosel to this pin. On the MM74C947,
when the oscillator pin is open, the LSD is inhibited from
blanking when leading zero blanking is enabled. If this pin
is grounded, the backplanes on both parts become inputs,
slaving the device to an external backplane.
An on-board oscillator/divider generates the segment!
backplane waveforms. Its output frequency Is typically
85 Hz, but may be lowered by connecting an external ca~
pacltor (Cosel between the oscillator pin and ground. The
oscillator pin may also be driven by an external waveform
but the input low level must not go to ground or else the
backplane pin will be put in the slave (input) mode (see
V1H(OSC) and VIL{OSC) specifications).
Store-This input controls the on-chip latches. VVhen low,
the latches are In flow-through mode (latch outputs follow
counter), but when taken high, the data on the counter outputs are stored in the latches.
Counter Circuitry Description
Reset-When low, counters are reset to zero.
The MM74C945, MM74C947 are 4-decade up/down counters. The direction of the count is controlled by the up/down
Input. A high level on this pin causes the counter to count
up. The counter advances on the negative clock edge. The
carry output is high for one clock period during a count of
9999 in up mode, or during a count of 0000 in down mode.
The carry is designed to allow cascading of several circuits in either ripple carry or synchronous modes:
Clock-Advances counters on negative edge.
Enable-When low, halts counter operation.
Leading Zero Input (LZI)-(MM74C947) When high,
enables leading zero blanking.
Leading Zero Output (LZO)-(MM74C947) This output
goes high when the latch contents equal zero, LZI is high
and the oscillator pin is open.
Reset and Enable controls are provided to 'allow period
and frequency measurements. The Reset control clears
the counter when low and the Enable control disables
counting when taken low.
Blanklng-(MM74C945) When high, blanks display.
Select-(MM74C945) When high, the contents of the
counter are displayed. When low, the contents of the latch
are displayed.
The counter chain feeds a series of 4-bit flow-through
latches. These latches enable the display to follow the
counter when the Store input is low. When the Store pin is
taken high the data on the counter outputs at this time
become latched and the display will remain unchanged.
(Assuming the latch display is selected on MM74C945.)
Carry-This output goes high when 9999 is reached (up)or
0000 is reached (down).
Up/Down-When high, the counter counts up. When low,
the counter counts down.
A1-G1- Digit 1 segment outputs.
On the MM74C945 the latch outputs "feed a multiplexer
which selects either the latch outputs or counter outputs
for display. This allows an intermediate count to be stored
in the latches while the counter continues to be displayed.
This is equi)lalent to a stopwatch lap feature.
A2-G2-Digit 2 segment outputs.
A3-G3-Digit 3 segment outputs.
A4-G4-Digit 4 segment outputs.
Application Hints
The output of the MM74C945's multiplexer feeds a decoder
which converts 4-bit Input to 7-segment outputs. A blanking control Into these decoders blanks the display.'
Display Circuitry Description
On the MM74C947 the latch outputs feed the decoders
directly, but these decoders have a special ripple blanking
capability that enables all leading zeroes except. the least
significant digit (LSD) to be blanked, even when counters
are cascaded. Thus when the entire counter reads zero, in~
stead of blanking all digits, the LSD will remain on. (When
mu Itiple counters are cascaded, all except the least significant counter will blank entirely on zeroes.) This feature is
properly implemented by configuring the least significant
device as the master (oscillator pin ungrounded) thereby
inhibiting LSD blanking.
The MM74C945 and MM74C947 have 28 segment outputs
capable of directly driving 4 digits of 7 segments. Both the
segment and backplane drivers are designed to provide
matched rise and fall times eliminating possible DC components In the driving waveforms which 'could degrade
display life (I.e., DC offset voltage).
The backplane drive'r can be disabled by grounding the
oscillator pin. This enables the segment output waveforms to be synchronized to an external signal applied to
the backplane pin. Several devices can then be driven by a
single master backplane waveform which can be generated by another MM74C945, MM74C947 or an external
oscillator. Thus single backplane displays with 8, 12, 16,
T.he outputs of the decoders for both devices control the
segment drivers, which in turn enable display operation.
6-195
Typical Applications
Ripple Carry Cascading-MM74C945
1-11-113 I-I
I=II~
...,.,..I 1=1
CI EII::II-I
[] _I [][]
II
"C"LAN~ ~
CARRY
CARRV
----. iffiET
-..
r---
CARRY
r---
mET
r+
STORE
MSD(SLAVEIMM74C945
srORE
r"
ENABLE
OSCILLATOR
•
SELECT
CLOC\(
BLANKING
I+-
..
LSD (MASTER)·
BACKPLANE
~
--i
UM74C945
CLOCk
ENABLE
OSCILLATOR
SELECT
BLANKING
I
-=l=-
I
COUN
INPU
"ii"E"SET
,
,
,
~TDR
COUNTENABL
SELEt T
DISPLAYBLANKIN
TLIFIMIIB
Synchronous Cascading-MM74C945
1-11-11-1 CI
I=II=II:J
...,.,.. I~
131-11-113
I 1=11=11
11
CARRY
-
----.
r"
CARRY
iiEm
MSDISLAVE)·
MM74C9C5
STORE
.-'~
CARRY
Rml
LSD (MASTER)*
BACKPLANE
SELECT
r+
BLANKI~~A8LE
--i
MM74C945
STORE
ENABLE
CLOCK
OSCILLATOR
~
CLOCt<
OSCILLATOR
SELECT
BLANKING
:I.
T
ENA8 LE
J
-=l=iiEsET
STOR
,
CD UN T
,
INPUT SELEt T
DISPLAYBLANKIN
TlIF/
Ripple Cascading-MM74C947
1::11::113 B ~
1=11=1 CII=I
I_I CII_II_I
----.
CARRY
-..
..
. J
41"-
II
CARRY
. 'AC"LANE
iiEsif
j -
MSD{SLAVEI**
MM74C1141
-r+
STtIRE
CLOCK
ENABLE
OSCILLATOR
LZI
LZO
-=l=-
v!c
!
+-
r"
CARRY
BACKPLANE
FiESEf
LSD (MASTERj**
MM74C141
STOne
CLOCk
ENABLE
OSCILLATOR
LZI
LZO
I
i
I
--i
:l.
INPU
iiiSET
,
STOR
COUNTENABlE
TlIFf5O!I8
Synchronous Cascading-MM74C947
CICIBEI
1_11_1
_I ~
1::1 01=18
1_101_1
II
CARRY
----.
,.
r"
~.".~
r--r-+
STORE
LZI
ENABLE
LZO
CLOCK
OSCILLATOR
v!c
!
CARRY
iiESff
MSO (SLAVE)**
MM14C947
STO,RE
CLOCK
OSCILLATOR
-=l=-
..
CARRY
BACKPLANE
RESET
LSD (MASTER)**
MMl4C941
ENABLE
I
LZI
LZO
i
I
f-t
bu.
T
ENAB LE
'" "'To correctly implement leading zero blanking.
: the least significant device must b e the master.
iiEsET
STOR
41"-
,
COUNTINPU T
TLiFf
* Master/slave selection is arbitrary and dependent only on which oscillator pin is grounded.
6·196
r----------------------------------------------------------.~
~·National
PRELIMINARY
~
~ Semiconductor
~
MM74C946 4112~Digit Counter/Decoder/Driver
for LCD Displays
General Description
Features
The MM74C946 is a 4'12-diglt CMOS counter which contains a counter chain, decoders, output latches, LCD seg. ment drivers, count inhibit and backplane oscillator/driver
circuitry. This device also contains leading zero blanking
and a carry output to increase flexibility and facilitate
cascading of multiple 4-digit sections ..
• Low power operation:;-Iess than 100 ",W quiescent
• Direct 4'12-digit 7-segment display drive for higher contrast and long display life
This device provides 29 segment outputs to drive a standard 4 'I2-digit liquid crystal display. An on-chip backplane
oscillator/driver is also provided. This can be disabled by
grounding the oscillator pin, thus allowing the device to be
slaved to an external backplaAe signal via the backplane
pin.
• True count inhibit disables first counter stage
• Carry output for cascading 4-digit blocks
• Schmitt trigger on the clock input allows operation in
noisy environments or with slowly changing inputs
Connection Diagram
• Pin compatible to Intersil's ICM7224
• Siore and Reset inputs permit operation as frequency or
period counter
• Leading zero blanking input and output for correct
leading zero blanking with cascaded devices
• On-chip backplane oscillator/driver which can be disabled to permit slaving of multiple devices to an external
backplane signal
Dual-ln-Line'Package
01
VCC
El
Cl
Gl
Bl
Fl
Al
OSCILLATOR
BACKPLANE
A2
GNO
B2
STORE
C2
Rm'f
02
CLOCK
MM74C946
G2
ENABLE
LEADING ZERO OUTPUT (LZO)
F2
LEADING ZERO INPUT (LZI)
AJ
CARRY
Yo-DIGIT
E2
!S
BJ
CJ
F4
OJ
G4
EJ
E4
GJ
04
FJ
. A4
B4
C4
TOP VIEW
TLIF/5102.1
Order Number MM74C946N
See NS Package N49A
6-197
Absolute Maximum Ratings (Note 1)
Voltage at Any Pi n
Operating Temperature Range
MM74C946
Storage Temperature Range
-0.3VtoVee + 0.3V
Package Dissipation
Operating Vee Range
Absolute Maximum Vee
Lead Temperature(Soldering, 10 seconds)
-40·Cto +85·C
-65·Cto +150·C
500mW
3.0Vt06.0V
6.5V
300·C
DC Electrical Characteristics Minimax limits apply across temperature range, unless otherwise noted.
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
VT+ Positive Going Threshold
Voltage (Clock Input)
Vee = 5V, VIN (0-5) V
2.5
2.9
3.25·
V
VT- Negative GOing Threshold
Voltage (Clock Input)
Vee = 5V, VIN (5-0) V
1.5
2.2
2.4
V
Hysteresis (VT+ - VT-)
(Clock Input)
Vee=5V
0.1
0.7
1.75
V
Logical "1" Input Voltage (VIN(t»)
Vee=5V
3.5
Logical "0" Input Voltage (VIN(O»)
Vee=5V
Logical "1" Output Voltage
(VOUT(1)) (LZO and Carry)
Vee = 5V, 10= -1O/LA
Logical "0" Output Voltage
(VciUT(O») (LZO and Carry)
Vee = 5V, 10= +10/LA
Clock Input Current IIIN I
Vee = 5V, VIN =5V/OV
Input Current @ Pins 29, 31, 33
and 34 (Note 2)
Vee = 5V, VIN=OV
Oscillator Input Current (losO
Vee = 5V, VIN = OV/5V
Supply Current (Ieel (Note 3)
Vee = 5V, VIN = OVl5V
When Driving Oscillator
Pin with External Signal
Oscillator Input Voltage
VIH(OSe)
VIL(OSe)
DC Offset Voltage (Note 4)
V
1.5
-2.0
.
0.5
V
0.005
1.0
/LA
-12.0
-25.0
/LA
±1.0
±10.0
p.A
10
60
p.A
Vee- 0.2
V
V
25
mV
0.2 Vee
Vee=5V
V
V
4.5
CMOSILPTTL INTERFACE
Logicar"1" Input Voltage
(VIN(t»)
Logical "0" Input Voltage
(VINIOI)
Logical "1" Output Voltage
(VOUTI1l ) (LZO' and Carry)
Logical "0" Output Voltage
(VOUT(O») (LZO and Carry)
V·
Vee - 1.5V
Vee = 4.75V
0.8
Vee=4.75V
Vee = 4.75V;l o = -360/LA
Vee = 4.75V, 10 = 360·JLA
2.4
V
V
0.4
V
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Range" they are
not meant to Imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: These Input pins have pull·ups to Vee.
Note 3: See test circuit. Display blanked.
.Note 4: DC offset voltage Is the effective DC voltage the LCD will have between any segment and the backplane.
,
6-198
DC Electrical Characteristics
(Continued)
Min/max limits apply across temperature range, unless otherwise noted.
I
Parameter
I
Conditions
OUTPUT DRIVE (SHORT CIRCUIT CURRENT)
Min
I
I
Typ
Max
I
Units
Output Source Current
(I SOURCE) (lZO and Carry)
Vcc= 5V, VOUT";OV
TA =25"C
1.75
2.7
mA
Output Sink Current
(I SINK) (lZO and Carry)
VCC= 5V, VouT=5V
TA =25"C
1.75
3.2
mA
Output Source Current
(I SOURCE) (Segment Outputs)
Vcc= 5V, VOUT=OV
TA = 25"C
1.4
2.0
mA
Output Sink Current
(I SINK) (Segment Outputs)
Vcc =5V, VouT =5V
TA =25"C
1.4
2.2
mA
Output Source Current
(I SOURCE) (Backplane Output)
VCC= 5V, VOUT=OV
TA =25"C
12.6
15.0
mA
Output Sink Current
(I SINK) (Backplane Output)
VCC= 5V, VouT =5V
TA =25"C
12.6
20.0
mA
Output Source Current
(ISOURCE) (V.-Digit)
VCC= 5V, VOUT=OV
TA =25"C.
2.8
3.4
mA
Output Sink Current
(ISINi- 100
w
:::>
C>
~
80
opF
60
22 pF
z
EE
w
5
"-
....
""
'".L
.!!1
20
o
,2
3
4
40~...~:__-+----11---)
5
.!!1
6
7
Voo-;-SUPPLY VOLTAGE (V)
1
'"
'"B
20
121--+-+-+-hOO~-1
~
~
8
~
4
en
'".L
220 pF
1
60
'"~
57 pF
24 .----...-...,..--.-----...-...,..----,
!Z
161--+--l--+--/---i:HIf-l
w
C>
5"- 40
..:
801---+--+----11---)
ffi
::::>
w
....
'"w
Operating Supply Current
(Iss) as a Function 01
Supply Voltage (Voo)
Backplane Frequency as a
Function of Oscillator
Capacitor (Cosel
Backplane Frequency as a
Function of Supply Voltage
0'--........._'---'-_'---'----'
50
100
150
200
Cosc-OSCILLATOR CAPACITANCE (pF)
TL/F/5102·7
TLlF15102·8
6-201
o
1
2
3
4
5
6
Voo-SUPPLY VOLTAGE (V)
TUFIS102·9
~
;:!
::E
::E
Control Pin Description
Backplane In/Out-When the oscillator pin is grounded
this pin is an input allowing an external device to generate
the backplane waveform. When the oscillator pin is left
open this pin is an output supplying backplane drive for
an LCD.
then goes Iowan the next count. Thuscounters may be
cascaded in a ripple carry mode or synchronous mode by
using the enable input. .
The counter can be inhibited from responding to clock input pulses by taking the enable input low, thus freezing
the counter to its state prior to-the event.
Oscillator-The oscillator frequency may be lowered by
tying a capacitor (Case) between this pin and ground. If
this pin is grounded the backplane pin becomes an input.
The counter outputs feed a series of flow-through latches.
When the store Input is low, the latch outputs follow their
inputs. When the store Input is taken high, the contents of
the counter are stored in the latches and are displayed.
Store Input-This controls the latches. When low, the
latches are in flow·through mode (latch outputs follow
counter), but when taken high data on counter outputs is
stored in latches and displayed.
The latch outputs feed 4 BCD to 7-segment decoders
which include circuitry to provide leading zero blanking.
When the leading zero input is low or the V.-digit is set,
leading zero blanking is inhibited. When the leading zero
input is high, all leading zeroes will be blanked. A leading
zero output is provided to allow correct blanking of all
leading zeroes in multiple device designs. This output will
be high when all 4 digits are blanked. (Remember the
leading zero inpui must be high and the V.-digit must be
reset.)
Reset Input-When low, counters are reset to zero.
Clock Input-Advances counter on negative edge.
Enable Input-When low, halts counter operation.
Leading Zero Input (LZI)-When high, enables leading
zero blanking.
Leading Zero Output (LZO)-This signal goes high when
counter equals zero and LZI is high.
Carry Output-Goes high for one clock period when count
of 9999 is reached.
Display Circuitry Description
The MM74C946 has 29 segment outputs capable of directly driving 4 digits of 7 segments plus an additional
V.-digit of 2 segments. The segment and backplane
drivers are deSigned to provide matched rise and fall times
eliminating possible DC components in the driving waveforms which could degrade display life (i.e., DC offset
voltage).
A1-G1- Digit 1 segment outputs.
A2-G2-Digit 2 segment outputs.
A3-G3- Digit 3 segment ou·tputs.
A4-G4-Digit 4 segment outputs.
V.-Diglt Output-Goes high when count goes from 9999
to 0000 and stays high until Reset goes low.
The backplane driver can be disabled by grounding the
oscillator pin. This enables the segment output waveforms to be synchronized to an external signal applied to
the backplane pin. This allows several devices to be driven
by a single master backplane waveform which can be generated by another MM74C946 or an external oscillator.
Thus single backplane displays with 8, 12, 16, etc. digits
can be driven by multiple counters. The maximum fanout
of a master backplane driver is limited by its total capacitive load which is the sum of the slaved backplane Input
capacitances and the display backplane capacitance.
Application Hints
Coun~er Circuitry
Description
The MM74C946 contains a 4-digit resettable synchronous
counter with a Schmitt trigger on the clock Input. An additional 0 flip-flop clocked by the counter carry out provides
a true V. -digit, or it can be used to indicate an overflow
condition. The counters increment on the negative clock
edge. The V.·digit sets on the negative clock edge which
increments the counter past 9999. It can be reset only
when the counter Is reset by taking the reset pin to ground.
The counter and carry output operation is independent of
the state of the V.·digit flip-flop.
An on-board oscillator/divider generates the segment!
backplane waveforms. Its output frequency typically is
85 Hz, but may be slowed by connecting an external
capacitor between the oscillator pin. and ground. The
oscillator pin may also be driven by an external waveform
but the input low level must not go to ground or else the
backplane will be put in the slave mode (see V1H (osC) and
V1L (OSC) specifications).
The carry output goes high on the negative edge of the
clock when the transition from 9998 to 9999 occurs and
6-202
Typical Applications
Ripple Carry·Cascading
1-11-11-11-1
1=11=11=11=1
11-11-11-11-1
11=11=11=11=1
11
CARRY
CARRY OUT
r---+
r-+
...
. BACKPLANE
RffiT
---.
~
CLOCK
LZI
v!c
I I
CARRY
--+
STORE
ENABLE
OSCILLATOR
1r
~
MSO (SLAVEI*
MfoI14C946
LZO
~
I+-
...
BACKPLANE
RESET
LSO (MASTER)"
MM14C946
STORE
CLOCK
ENABLE
OSCILLATOR
I
.1
LZI
LZO
f
I
r--+
~
COU NT
INPU T
RESET
STaR E
TUFI510
COUNT ENABL E
Synchronous Cascading
EI
1-11-11-11-1
1=11=11=11=1
11-11-11-1
11=11=11=1 ::I
...,r
5l
CARRY OUT
CARRY
;---+
---.
r-+
BACKPLANE
RESET
STORE
~
LZI
.I
VCC
ENABLE
LZO
lJ
IJ
MSO (SLAVEI*
MM14C94B
CLOCK
OSCILLATOR
~
1..-
CARRY
~
RESET
r-+
r+
STORE
BACKPLANE
LSO (MASTER)"
MM14C946
ENABLE
CLOCK
OSCILLATOR
I
.1
LZI
r
LZO
I
~
(1,
NT
ENAB LE
RESET
STORE
TLIF/5102·5
COUNT INPUT
• Master/slave selection Is arbitrary and dependent only on which oscillator pin Is grounded.
6-203
~'National
.
~ Semiconductor
MM74C956 4-Digit, 17-Segment Alpha-Numeric Display
Driver, with Memory, Decoder, and LED Drivers
General-Description
The MM74C956 monolithic LED irtelligent .display driver
circuit is manufactured using standard complementary
MOS technology. The convention and speed of the data
entry procedure is designed to be microprocessor bus and
TTL compatible with no '(Iterface circuitry required.
The integrated circuit has memory to store four 7-bit ASCII
words corresponding to the four digits, an ASCII to
17-segment alpha-numeric ROM decoder, multiplexing
and drive circuitry to drive four 17-segment digits. It
has direct drive capabilities of 2.5 mA/segment average
current.
The cursor function will cause all segments of a digit to be
lit but will not write over t!:1e contents of the memory corresponding to that digit. Therefore, when the cursor is
erased, the original character will reappear at that digit
location.
Features
•
•
•
•
The internal memory can be written asynchronously . •
through the 7-bit data bus (00-06) into the digii location
addressed by the 2-bit address bus (AO, A1). For multiple
•
chip circuits, two chip select inputs (CE1, CE2) can be
•
decoded or a one-of-n decoder can be used for displays
•
incorporating more than four MM74C956's.
•
•
Microprocessor bus compatible
All inputs are TTL compatible; 5V power supply
On-chip memory
On-chip decoder converts from standard 7·bit ASCII to
alpha-numeric
On-Chip multiplexing with LED segment and digit
drivers
Independent and asynchronous digit access
Independent cursor function: can be disabled
Display clear function
Display blank function
Two chip select inputs for multiple chip systems
Block and Connection Diagrams
AI
01
Gl
Dual-In-Line Package
DIGIT OUTPUTS
SEGMENT OUTPUTS
DIG
1
OP
DIG
3
40 Von
SEG l
39 SEG C
SEG 02
SEG M
3B SEG G2
SEG E
37 SEG Gl
SEG J
36 SEG 01.
SEG 8
35 SEG H
3.
SEG F
33
SEG I
l2
SEG A2
31
SEG A1
30
CUE
29_
CE2
28
SEG K
SEG OP
OSO
Bl
06
05
10
MM74C956
11
12
D.
27
17
IB
23
19
22
20
21
02
01
DO
ITR
DIG 0
VSS
CONTROL/ADDRESS
INPUTS
.
TOPVIEW
ASCII/CURSOR DATA
INPUTS
TlIF15924·1
WE
DIG 3
DIG 2
DIG 1
TLIF15924·2
Order Number MM74C956N
See NS Package N40A
Segment
Designation
6-204
eEl
AD
20
AI
25 _
CU
2.
03
Absolute Maximum Ratings (Note 1)
Voltage at Any Pin
Operating Temperature Range
MM74C956
Storage Temperature Range
Package Dissipation
Operating Vcc Range
- 0.3V to Vee + 0.3V
-40'Cto +85'C
-65'Cto +150'C
700mW
4.5Vto5.5V
6.0V
300'C
Vee
Lead Temperature (Soldering, 10 seconds)
DC Electrical Characteristics TA =25'C
Symbol
Parameter
Conditions
Typ
Min
VIN(1)
Logical "1" Input Voltage
Vee =5.0V
VIN(O)
Logical "0" Input Voltage
Vee =5.0V
IIN(1)
Logical "1" Input Current
Vee = 5V, VIN = 5V
IIN(O)
Logical "0" Input Current
Vee =5V, VIN=OV
Icc
Supply Current
Vee=5V Ii.P TA =25'C
All Outputs Open
All Inputs (j} 5V
Max
Units
0.8
V
2.4
V
0.005
-100.0
1.0
25.0
0.5
p.A
p.A
1.0
mA
14.8
mA
OUTPUT DRIVE (Notes 2 and 3)
Peak Output Source Current (lsouReE)
(P·Channel Segment Driver with 1 Segment On)
Vee = 5.0V, VOUT = 1.9V
TA,=25'C
Peak Output Source Current (lsouReE)
(P,Channel Segment Driver with 17 Segments
On)
Vee= 10V, VouT =3.3V
TA =25'C
4.2
mA
Peak Output Sink Current (I SINK )
(N-Channel Digit Driver with 3 Segments On)
Vee = 5.0V. VOUT = 0.25V
TA =25'C
18.5
mA
Peak Output Sink Current (lSINK)
(N-Channel Digit Driver with 17 Segments On)
Vee= 10V. VOUT= 1.3V
TA =25'C
172.0
mA
AC Electrical ~haracteristics TA =25'C, Vee =5.0V
Symbol
Conditions
Min
tw
Write Pulse Width
Parameter
All Inputs Swing from OV-4V
240
ns
t DS
Data Set-Up Time
All Inputs Swing from OV-4V
100
ns
tDH
t AS
Data Hold Time
All Inputs Swing from
50
ns
Address Set-Up Time
All Inputs Swing from OV-4V
300
ns
tAH
Address Hold Time
All Inputs Swing from OV-4V
0
ns
l"eLR
Clear Time
All Inputs Swing from OV-4V
1
P.s
OV'~4V
Typ
Max
Units
Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. Except for Operating Range they are not
meant to imply that the devices should be operated at these limits. The table of Electri'cal Characteristics provides conditions for actual device operation.
Note 2: Average drive current".. peak drive current..,.. 4.
Note 3: CurrentJsegment is dependent upon total number of segments on. Maximum current occurs with 1 segment on; minimum current occurs with 17
segments on.
Timing Diagram for data access
I
m.rn
'AS
4
LI
l:U, ADD
J
0
4
WE
0
tw
{
J
~~'OS-
4
~~'OH
00-0&
0
TLlf/5924-4
6-205
Functional Description
Entry into Data Memory
Blanking the Display
To en~r an ASCII code, the CE1 and CE2 inputs must be
low, CU must be high. When the address is set up at AO
and A1, tlie WE cango low, at which time the internal RAM
will respond to the data inputs (00-06). Note that the data
'
need not be set up prior to the WE transition.
Display blanking can be realized by using the BL input. By
taking BL low, the display will be disabled while leaving
the contents of the data and cursor memory unchanged. A
flashing display will occur if BI. is pulsed. The display
is blanked by BL regardless of whether a cursor or character is being displayed.
All digits can be cleared by holding the CLR input low for
the specified interval.
Illegal Code
If an illegal ASCII code is entered into the data memory
(i.e., 06 = 05) the display will automatically be blanked for
the corresponding digit.
Entry Into Cursor Memory
This is accomplished by setting the CE1 and CE2 inputs
as well as the CD input low. The cursor memory consists
of 4 bits corresponding to the four digits, each one ad- ,
dressable by way of the AO and A1 inputs. Once the
address is stable, the WE input must go low aFld the
cursor memory will respond to the DO input. That is, if DO is
high, a cursor will be written and if DO is low, the cursor will
be erased. CLR will not erase a cursor. Acursorwill onlybe
displayed when CUE is high and the cursor function can
be bypassed by tying CUE low. A flashing cursor can be
implemented by pulsing CUE; this results in alternately
displaying the cursor and the character originally written
In that digit. CUE will not alter the contents of either the
cursor or data memory.
OSD Pin
Taking the OSO pin high disables the Internal oscillator
and prohibits normal multiplex scanning. This pin is
pulled low internally and is primarily meant to be used in
testing the part only. This pin should be grounded or left
open in normal operation.
Clearing the Display
Pulsing the CLR pin low forthe specified time will clear all
internal data memories while leaving the cursor memories
unchanged.
TABLE I. DATA AND CURSOR ENTRY FUNCTION EXAMPLE
Assume Initially 06 = 1 and 05 - DO = 0 for all Internal digit memories. Cursor memory is cleared. Table is
intended to be read in sequence.
---
-
- -
BL CEl CE2 CUE CU WR CLR Al AO
0
x x x x
D6 D5 04 03 02 01 DO
X
1
X X
X
X
X
X
X
X
X
X
X
X
X
X
X
DIG
,3
DIG
2
DIG
1
--,
--,
eu
c::--,
0_'
-, ,;J
0_'
CU
-7,
--,
eu ,;J eu
--,
-,
0
X
X
X
1
X X
X
0
1
X
X
X
1
X X
X
X
X
X
X
X
X
0
0
x
X
1
1
X X
X
X
X
X
X
X
X
0
0
X
1
0
1
o
LU
1
0
1
0
0
0
1
1
1
>a:
1
0
a x
OJ
1
a
1
1
a
0
1
1
0
1
0
0
Ct,
Z
X
X
X
X
X
X
0
X X
X
X
X
X
X
X
X
1
0
0
X
1
0'
1
o0
1
0
0
0
0
1
1
0
0
X
1
a
1
0 1
1
0
a
0
a
a
1
0
1
0
0
X
1
0
1
1 0
1
0
0
0
0
1
1
1
0
0
X
1
0
1
1 1
1
0
0
0
1
0
0
_U
_U
1
1
Z
0
1,
(,)
1
:::>
'j::
z
II.
l-
w
~
icC
c
1
0
0
1
0
0
1
0 0
x x x x x
X
1
1
0
0
1
0'
0
1
0 1
X
X
X
1
1
0
a
1
a
0
1
1 1
X
X
1
0
0
1
0
o'
1
1 0
X
X
1
X
X
0
1
1
1
X X
X
X
Z
:::>
1
X
X
1
1
1
1
X X
X
X
>a:
I-
1
0
a
1
a
0
1
o
1
0
0
0
0
0
1
1 0
a:
1
X
X
1
1
1
1
X X
x x x x x x 0
X X X X X ,x a
X X X X X x x
1/1
0
x 'x
X
1
1
1
X X
X
X
X
X
X
X
:::>
1
X
X
1
1
1
1
X X
X
X
X
X
X
1
X
X
1
1
X
0
X X
X
X
X
X
1
0
0
1
0
0
1
1 1
X
X
X
1
0
0
1
0
0
1
0 1
X
X
X
Z
0
j::
(,)
II.
zw
0
a:
(,)
0
X=donlcare
6-206
X
X
X
X
X
X
X
1
X
X
X
X
1
X
X
X
X
X
X
X
X
X
X
OJ
:-,
CU
--, C,]
--,
'I'
i
DIG
0
,-:
C,J
--, '--'
0_'
[j
,--,
,--,
-rl
-,-,
-,-,
_,_,
~
~
IT'
_'J
~
!WI
@
-,-,
,-,-L_
,-L_
,-'-,-L_
L_
IS0
IGSI
,--
'-IS0
I,!ISI
~
,--
]3
-,-,
_0
Fi
lJ
_U
~
~
~
~
~
!WI
@
~
li Fi
_L
~
~
-n
_0
09
L_
~
X
"'"
X
X
-~
X
X
X
~
'--
X
X
X
0
X
X
X
0
,-,--
F~
-0
_U
L_
_L'
Fi
~
!WI
@
~
~
,--,
,--,
Fi
Fi
C'
"
Functional Description (Continued)
TABLE II. ROM OUTPUT FONT FOR ASCII TO ALPHA·NUMERIC DECODING
Character Set
DO
01
02
L
L
L
H
L
L
L
H
L
H
H
L
•
"
"
:0
\
/
1"
06 05 04 03
L
H
L
L
L
H
L
H
L
H
H
L
L
H
H
H
H
L
L
L
H
L
L
H
H
L
H
L
H
L
H
H
,
L
·L
H
H
L
H
ee
_u '-'~
/u
L
H
H
H
H
H
"
/
e~,
-:- -- .
,-, ,, :t -, u, :; -,,
'~'-- :t,-,u
-:',
-0 '-=t --, -,-, ,-- ,-, -- ,eeU :::: _0 '-- _U E: , c;
, , -,- -,- ,-\,/ , , , ,'\ ,--,,
,--,
:::, '-'---, ,'e:t-' ~; '---,-, '--, ,, '/,\' '/\','--,
, -1 '-,- " " --,, -/
\
\'/
/
/
/
/
/
\
~-
-~
,\/1
/
'-~,
\/
/\
\
\/
~-
/\
Typical Application
~P
""'"'
C
LOGIC
~PWRITE
!
----+ CUE
----+ Cii
----+ CLR
----+ Bi.
{
.. WE
STROBE
~P
ADDRESS
BUS
==
==
-==
ADDRESS
DECODE
f--+
CE2
f--+
Cf1
•
•
~P
DATA
BUS
----+
----+
----+
----+
----+
----+
--+
.,.7. .,.7. .,.7. .,.7.
h-
SEGMENT
OUTPUTS
)
r
17·SEGMENT ALPHA·NUMERIC DISPLAY
LIKE HEWLETT PACKARD HDSP·65D4
OR TEXAS INSTRUMENTS HDSP·6504
DIG 1
DIG 2
DIG 3
DIG 4
I
MM74C956
A7
'Z'S' 'Z'S' 'Z'S' 'Z'S'
DIG 0
AO
06
DIG 1
05
04
DIG 2
03
02
DIG 3
/
01
DO
TUFJS924·S
6·207
g
~ ~National
:IE ~ Semiconductor
:IE
~ MM78C29/MM88C29 Quad Single·Ended Line Driver
o MM78C30/MM88C30 Dual Differential Line Driver
~
:IE General Description
:IE
gf
o
i
:IE
:IE
gj
o00
....
:IE
:IE
The MM78C30/MM88C30 is a dual differential line driver
that also performs the dual four-input NAND or dual fourinput AND function_ The absence of a clamp diode to Vce
in the input protection circuitry of the MM78C30/MM88C30
allows a CMOS user to interface systems operating at
different voltage levels. Thus, a CMOS digital signal
source can operate at a Vee voltage greater than the Vee
voltage of the MM78C30 line driver. The differential output of the MM78C30/MM88C30 eliminates ground-loop
errors.
The MM78C29/MM88C29 is a non-inverting single-wire
transmission line driver. Since the output ON resistance
is a low 20Q typ., the device can be used to drive lamps,
relays, solenoids, and clock lines, besides driving data
lines.
Features
3.0Vto 15V
• Wide supply voltage range
0.45 Vee (typ.)
• High noise immunity
20Q (typ.)
• Low output ON resistance
Logic and Connection Diagrams
1/2 MM78C30(MM88C30
1/4 MM78C29/MM88C29
INPUT 1
INPUT '1
INPUT]
INPUT 4
AND
OUTPUT
INPUT
OUTPUT
NAND
OUTPUT
TLIFI59081
Ne
I~·
"
Dual-In-Llne Package
Dual-In-Line Package
MM78C29/MM88C29
MM78C30/MM88C30
IN,
12
Ne
"
INlI!
10
•
•
-
r--
1
Ne
J"
1
IN,
J
Nt
•
IN,
TOPYI(W
,
DUll
•
OU1,
"
11
"
IN.II
10
8 AND
I! NAto/O
OUT
OUT
,
r-
,.-
I'
1
GNO
,
1
)
,
,
1Nu
A AND
A IIIAND
OUl
OUT
•
.I'
CiNO
TOPIJ!EW
TUFI59083
Order Number MM78C29J or MM88C29J
See NS Package J14A
Order Number MM78C30J or MM88C30J
See NS Package J14A
Order Number MM78C29N or MM88C29N
See NS Package N14A
Order Number MM78C30N or MM88C30N
See NS Package N14A
6-208
Absolute Maximum Ratings
Voltage at Any Pin (Note 1)
Operating Temperature Range
MM7BC29/MM7BC30
MMBBC29/MMBBC30
Storage Temperature
Package Dissipation
Operating Vee Range
Sym
I
Parameter
I
SOmA
2SmA
1S0'C
300'C
MinImax limits apply across temperature range unless otherwise noted
Conditions
VIN(1) Logical "1" Input Voltage
Vee=5.0V
Vee=10V
VIN(O) Logical "0" Input Voltage
Vee=S.OV
Vee=10V
I
Min
I
Typ
I
Max
3.5
B.O
IIN(1)
Logical "1" Input Current
Vee=1SV, VIN =15V
IINtOI
Logical "0" Input Current
Supply Current
Vee = 15V, VIN=OV
Vee- 1SV
Icc
1BV
Absolute Maximum Vee
Average Current at Output
MM78C30/MMB8C30
MM78C29/MMBBC29
Maximum Junction Temperature, lj
Lead Temperature (Soldering, 10 sec.)
-SS'C to +12S'C
-40'C to +8S'C
-6S'C to +1S0'C
SOOmW
3.0Vto 1SV
DC Electrical Characteristics
CMOS to CMOS
(Note 1)
-0.3V to Vee + 16 V
-1.0
I
Units
V
V
1.5
2.0
V
V
O.QOS
1.0
JJA
-O.OOS
O.OS
100
JJA
JJA
Output Drive
Output Source Current
MM7BC29/MM7BC30
. MMBBC29/MMBBC30
MM7BC29/MM88C29
MM7BC30/MM88C30
Output Sink Current
MM7BC29/MM7BC30
VOUT= Vee -1.6V,
Vce ~ 4.5 V, lj = 2S'C
lj = 12SOC
-S7
-32
-BO
-SO
rnA
rnA
VOUT= Vee -1.6V,
Vee ~ 4.7SV, lj =2S'C
lj = BS'C
-47
-32
-BO
-60
rnA
rnA
VOUT = Vee - O.BV
Vee ~ 4.SV
-2.0
-20
rnA
11
B.O
20
14
rnA
rnA
22
16
40
28
rnA
rnA
9.S
8.0
22
18
rnA
rnA
19
15.5
40
33
rnA
rnA
VOUT = 0.4 V, Vee = 4.S0 V,
lj = 2S'C
lj = 12S'C
VOUT - 0.4 V, Vee - 10 V,
lj =2S'C
lj = 12S'C
MM88C29/MM88C30
VOUT = 0.4 V, Vee = 4.75 V,
lj = 25'C
lj = 85'C
VOUT - 0.4 V, Vee = 10 V,
lj =2S'C
lj = 12S'C
Output Source Resistance
MM78C29/MM78C30
MM88C29/MM88C30
VOUT = Vee -1.6V,
Vee ~. 4.S V, lj = 2S'C
lj = 12S'C
20
32
28
50
Q
VOUT = Vee -1.6V,
Vee ~ 4.7SV, lj =2S'C
lj = 85'C
20
27
34
50
Q
Q
6·209
Q
DC Electrical Characteristics
(cont'd)
MinImax limits apply across temperature range, unless otherwise noted.
,
Sym
Parameter
Output Sink Resistance
MM78C29/MM78C30
MM88C29/MM88C30
BJA
Typ
Max
Units
1i = 25°C
1i = 125°C
20
28
36
50
Q
Your - 0.4 V, Vee -10 V,
1i = 25°C
1i = 125°C
10
14
18
25
Q
Your = 0.4 V, Vee = 4.75 V,
1i = 25°C
1i = 85°C
18
22
41
50
Q
,Vour = 0.4 V, Vee = 10 V,
1i = 25°C
1i = 85°C
10
12
21
26
Q
Conditions
Your = 0.4 V, Vee = 4.50 V,
Q
Q
%I·C
%I·C
Thermal Resistance
MM78C29/MM78C30
(D· Package)
100
°C/W
MM88C29/MM88C30
(N'Package)
150
·C/W
Parameter
tpd
Propagation Delay Time to
Logical "1" or "0"
MM78C29/MM88C29
MM78C30/MM88C30
Cpo
Q
0.55
0.40
Sym
CIN
Q
Output Resistance
Temperature Coefficient
Source
Sink
AC Electrical Characteristics
tpd
Min
Differential Propagation Delay
Time to Logical "1" or "0"
MM78C30/MM88C30
TA =25·C, CL=50pF
Conditions
Min
(See Figure 2)
Vee =5.0V
Vee=10V
Vcc =5.0V
Vcc=10V
-
Typ
Max
Units
80
35
200
100
ns
ns
110
50
350
150
ns
ns
400
150
ns
ns
RL = 100 Q, C L = 5000 pF
(See Figure 1)
Vcc =5.0V
Vcc=10V
Input Capacitance
M M78C291 M M88C29
MM78C30/MM88C30
(Note 3)
(Note 3) •
5.0
5.0
pF
pF
Power Dissipation Capacitance
MM78C29/MM88C29
MM78C30/MM88C30
(Note 3)
(Note 3)
150
200
pF
pF
Nole 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for
"Operating, Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical
Characteristics" provides conditions for actual device operation.
Note 2: Capacitance Is guaranteed by periodic testing.
Nole 3: Cpo determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family
Characteristics application note AN-90.
,
"
6-210
Typical Performance Characteristics
MM78C29/MM88C29
Typical Propagation Delay vs
Typical Propagation Delay vs
Load Capacitance
70
125
T1 "25°C._f- IJ ..... ,...,~r-
65
,.
i!i
~
~
g:
L_
Vee "'10V
]: 115
g
105
95
85
75
~"'I -II-I-I-I-t--t--H
200
400
600
800
30 f-""'t-+---+----I--I-++++---l
zoo
'000
LOAD CAPACITANCE. CL (pF)
400
600
~
i§i
~
15
H-I-+++-l- 1"'1
V~~
400
I-t--t--+-+--tV~,..q-l-lH
~~
65 1-1-f-1/--j,A-+i'~""":".tpdO
t--
i :: I-Jf,l<-J.4i'-t-t-l-l-l-lH
50
200
400
600
800
600
!
300
5
200 H-1I¥1+-I-H-+H++-i---l
~
t-
~
JOO
200
tC"
2
4
6
8
10
12
Vee;:: tOV
400
0:
HVt--+-i+-t-H-+H++-i-l
SVH+t-I++-H--l
1000
V c '" 5V
'DO
14
2
4
6
TL.IFI5908·9
I
v.
....J r--"':L._.,~~AND OUTPUT
1--::
La-!
t,
1/2 MM78C30
6
1=
'"~
v,"~
100
~~
_ .... SOOOpF
--;~~,...-..J~NANDOUTPUT
t2
OV
....
VA-VB
TLIFI5908·12
TUF/5908·11
FIGURE 1
II'~
VO'
,:f
1!L
r~r-!:'·:.L..-t5L-1P-O,~~~PUT
INPUTS
1/4MM78C29
112MM7BC30
c,
1'-'""';'
La-!
*
1_
--L c,OUTPUT
J
TLIFI5908-13
TLIFIS9C8·14
FIGURE 2
6·211
10
12
14
TLIFI5908·10
AC Test Circuits
vcc
B
TYPICAL VCC-VOUT (V)
TYPICAL VOUT (V)
,.y
toDD
Vcc"~
5
~
'DO
TLIFI5908-8
INPUTS
800
500
H++-i-+-I-H-+H++-i---l
LOAD CAPACITANCE. CL (oF)
r
600
Typical Source Current vs
Output Voltage
".sj
~V~~~+-~-+~~
o
400
TLIFIS906·7
500
70
200
LOAD CAPACITANCE, CL (pF)
Typical Sink Current vs
Output Voltage
90
80
o
1000
TL.IFI59D8·6
MM78C30/MM88C30
Typical Propagation Delay vs
Load Capacitance
85
800
LOAD CAPACITANCE, CL (pFI
TL.IF/59Q8.5
,.
MM78C30/MM88C30
Typical Propagation Celay vs
Load Capacitance
MM78C29/MM88C29
Load Capacitance
0
C")
0
co
co
::E
::E
Typical Applications
-
Digital Data Transmission
Cl
0
O.Ol~F
C")
(NOTE 11
0
v"
CO
.....
::E
:E
0)
INPUT
('Ii
0
LINE DRIVER AND RECEIVER (NOTE 3)
I
OUTPUT
CO
CO
':"
::E
::E
en
('Ii
-
Notel' EKaClvalue depends on lme length.
NoteZ. Opl10nal to cllntlol respOlise time.
Note J: Vee 10 4.SV to 5.SV for the OS1820
STROBE
TLIF/590B·15
0
CO
.....
::E
::E
V"
V"
qUTPUT
INPUT [
':"
lLlFIS908·16
V"
V"
SINGLE·WIRE TRANSMISSION LINE (NOTE 1)
14
INPUT
1/6MM78CZ91
MM8BCZ9
OUTPUT
OUTPUT
TLIFIS90B·17
Typical Data Rate vs Transmission Line Length
10,000
!
ETA~25C
"l'!oI.U1 ~
1000
Cc
,b
"'$11
~
!;;
"'~
It-c,,,
....... '0"
lOU
"oo.~
c
;'l
;:
'5"
10
~
10
100
1000
LENGTH OF TRANSMISSION LINE IFTI
Notl! 1: The transmISSion Ime used was "22 gauge unshlerded tWisted pair
(40ktermmatlon).
Notl! 2: The curves generated assume that both dnven are driVing equ,l
Imes, and that the maximum power IS 500 mWfpackage.
TlIF15908·18
6-212
Section 7
LSI/VLSI
•
Section Contents
MM5034, MM5035 Octal80·Bit Static Shift Register ................................... .
MM5307 Baud Rate Generator/Programmable Divider ................................. .
MM5368 CMOS Oscillator DividerCircuit ........................................... .
MM5369 Series 17 Stage OscillatoriDivider .......................................... .
MM53107 SeriEis 17·StageOscillatoriDivider ......................................... .
MM53126 Infra Red Transmitter ................................................... .
MM53226 Infra Red Transmitter ................................................... .
MM5437 Noise Generator ........................................................ .
MM5450, MM5451 LED Display Drivers ............................................. .
MM5452, MM5453 Liquid Crystal Display Drivers. : .......................... '......... .
MM5480 LED Display Driver ...................................................... .
MM5481 LED Display Driver ...................................................... .
MM5483 Liquid Crystal Display Driver .............................................. .
MM5484, MM5485 16·Segment LED Display Driver, 11 Segment LED Display Driver ......... .
MM5486 LED Display Driver ...................................................... .
MM54240 Asynchronous Receiver/Transmitter Remote Controller ....................... .
MM58167A Microprocessor Real Time Clock ........................................ .
MM58174A Microprocessor ReCiI Time Clock ........................................ .
MM58201 Multiplexed LCD Driver .................................................. .
MM58241 High Voltage Display Driver ............................................... .
MM58242 High Voltage 20 Output Vacuum Fluorescent Display Driver .................... .
MM58248 High Voltage 35 Output Vacuum Fluorescent Display Driver .................... .
MM58250 Infra Red Transmitter ................................................... .
MM58274 Microprocessor Real Time Clock .......................................... .
MM58341 High Voltage 32 Output Vacuum Fluorescent Display Driver ................... .
MM58342 High Voltage 20 Output Fluorescent Display Driver ........................... .
MM58348 High Voltage 35 Output Vacuum Fluorescent Display Driver .................... .
MM58438 32·Bit LCD Display Driver ............................................... .
MM58538 Multiplexed LCD8·Row/26·Column Driver .................................. .
MM58539 Multiplexed LCD34·Column Driver ........................................ .
MM58540 Multiplexed LCD 32·Row/32·Column Driver ................................. .
MM58548 Multiplexed LCD 16·Row/16·Column Driver ................................. .
7·2
7·3
7·6
7·11
7·14
7·17
7·19
7·24
7·29
.7·32
7·37
7·43
7·47
7·51
7·54
7·57
7·62
HO
7·78
7·85
7·90
7·95
7·100
7·105
7·113
-7·126
7·131
7·136
7·141
7·145
7·150
7·155
7·160
~National
~ Semiconductor
MM5034, MM5035 Octal80-Bit Static Shift Register
General Description
The MM5034 octal 80-bit shift register is a monolithic
MOS integrated circuit utilizing N-channellow threshold
enhancement mode and ion·implanted depletion mode
devices.
The MM5035 is a 20·pin version of the MM5034 with
the TR I·ST ATE output select feature omitted, for a
simple data'in/data out operation.
Features
The MM5034 is designed for use in computer disp.lay
peripherals. All inputs and outputs are TTL compatible.
The clocks and recirculate logic are internal to reduce
system component count, and TRI·STATE® output
buffers provide bus interface, Because' of its N·channel
characteristics, single 5V power supply operation is
required.
• Single 5V power supply
• Internal clocks
• High speed and static operation
• TRI·~TATE output buffer
• Recirculate and output select independent
• TTL compatible
Simple interface to the NSC CRT DP8350 controller
and character generator to incorporate an entire CRT
terminal is feasible with the MM5034.
Applications
• CRT displays
• Computer peripherals
The MM5034 is available in a 22-lead dual·in·1 ine pack·
age.
Connection Diagrams
Dual-in-Line-Package
Dual-in-Line-Package
22 VOO
RECIRCULATE
20 VOO
RECIRCULATE
OUTPUT 8
21 INPUT 8
OUTPUT 8
19 INPllT 8
OUTPUT7
20 INPUT7
OUTPUT 7
18 INPUT7
OUTPUT 6
19 INPUT 6
OUTPUT 6
17 INPUT 6
18
OUTPUT 5
MM5034
OUTPUT 4
16
OUTPUT 3
15
OUTPUT 2
14
OUTPUT 1
OUTPUT SELECT
17
10
13
12
11
VSS
TOP VIEW
MM5035
16 INPUT 5
INPUT 5
OUTPUT 5
INPUT 4
OUTPUT 4
15 INPUT 4
INPUT 3
OUTPUT 3
14 INPUT 3
INPUT 2
OUTPUT 2
13INPUT2
INPUT 1
OUTPUT 1
12 INPUT 1
10
NC
11 CLOCK IN
VSS
TOP VIEW
CLOCK IN
Order Number MMS03SN
See NS Package N20A
TLlFI689().1
Order Number MMS034N
See NS Package N22A
7-3
Tl/F/6890·2
•
Absolute Maximum Ratings
Supply Voltage
Input Voltage
Power Dissipation
-65°C to +150°C
Storage Temperature Range
300°C
.Lead Temperature (Soldering, 10 seconds)
7VDC
7 VDC
750mW
Electrical Characteristics
PARAMETER
Clock Input
Logical "1" Input Voltage
Logical "0" Input Voltage
VDD = 5V ±5%, TA = O°c to +70°C
CONDITIONS
Outputs
Logical "1" Output Voltage
Logical "0" Output Voltage
TRI-&TATE Output Current
Supply Current
UNITS
0.8
V
V
0.8
V
V
2.2
.
VIN = 5V
VIN = 2.5V
5.0
pA
pF
5.0.
8.0
VOUT= 5V
0.4
-5.0
VOUT= OV
5.0
V
V
pA
pA
90
rnA
IOUT=100pA
lOUT = 1.6 mA
2.4
2.8
0.25.
60
3.0
10,000
0
125
125
(Figure 1)
(Note 1)
Output Rise and Fall Time (tr, tfl
Set-Up Time
Hold Time
Output Enable Time
Output Disable Time
(::Iock Rise and Fall Time
Output Delay, (tPDI
Note 1: The clock input mus~
,
.
Timing
Clock Frequency
Clock Pulse Width High
Clock Pulse Width Low
MAX
2.2
,
Data and Control Inputs
Logical "1" Input Voltage
Logical "0" Input Voltage
Data, Clock and Control Inputs
Logical "1" Input Current
Input Capacitance
TYP
MIN
(Figure 1)
(Figure 1)
DO
40
50
80
185
185
5.0
185
100
0
(Figure 1)
(Figure 1)
(Figure 1)
(Figure 1)
MHz
ns
ns
ns
ns
ns
ns
ns
ps
ns
be at a low level for DC storage. Minimum pulse width assumes 10 ns tr and tf.
Recirculate and TRI·STATE Operation
output of the last 'shift cell back fo the input of the first
shift cell for each of the 8 registers.
Recirculate is used to maintain data in the shift register
after it has been loaded. While the shift register is being
loaded, Recirculate must be at a logical "O~'. When the
loading is completed, Recirculate should be brought to a
logical "1 ". This disables the data input and feeds the
For the output to be in the TRI-STATE mode outputselect should be at the logical '1.' level.
7-4
AC Test Circuits and Switching Time Waveforms
[]j,
DUT
*SOIiF
TLlF16890·3
OUTPUT DATA LINE
tpDO
[l
m'"·'
'v----.---------.,r---------
RECIRCULATE
CONTROL
DV----·---------' 't------'---
'v-------------.:r---------
DUTPurffim
Dv------------Jl--------_
TLlF/68904
TLIFI68905
FIGURE 1
Typical Application
VIDEO
INTERFACE
~~~~~~~~ III
ATT.RIBUTE
TD
DECODE
I
~~~--....I
I
I
II
VIDEO
OUTPUT
I
I
I
~~~~~~~~~~~~~ill~~~~~~~~~~---'-:::.:::----_==~~--------l==~~tll}THREE.TERMINAL
VERTICAL
SYNC
FIGURE 2. CRT System Diagram USil1'!J the MM5034, 'MM5035 as a Line Buffer with DMA
7·5
MONITOR
•
!
I
~National
~ Semiconductor
MM5307 Baud Rate Generator/Programmable Divider'
General Description
The National Semiconductor MM5307 baud rate
generator/programmable divider is a MaS/LSI P-channel
enhancement mode device. A master clock for the device
is generated either externally· or by an on-chip crystal
oscillator (Note 4). An internal ROM controls a divider
circuit which produces the output frequency. Logic
levels on the four control pins select between sixteen
output frequencies. The frequencies are chosen from
the following possible divisors: 2N, for 3 :::; N :::; 2048;
2N + 1 and 2N + 0.5 for 4 :::; N :::; 2048. Also one of the
sixteen frequencies may be gated from the external
frequency input. The MM5307AA is supplied with the
divisors shown in the Control Table.
Applications
Features
• UART clocks
• On-chip crystal oscillator
• System clocks
• Choice of 16 output frequencies from 1 crystal
• Electrically programmable counters
• External frequency input pin
• Internal ROM allows generation of other frequencies
on order
• Bipolar compatibility
• 0.01% accuracy (typ) exclusive of crystal
• 1 MHz master clock frequency
Schematic and Connection Diagrams
A
ROM
Dual-In-Line Package
EXTERNAL FRED.
RESET
>----1
NC
PROGRAMMABLE
DIVIDER
OUTPUT.
MULTIPLEXER
-<
L-_ _ _ _ _ _
OUTPUT
Vss
~~~iL
EXTERNAL 5
CLOCK
CRYSTAL
...---+-----c>---~ "OUT
EXTERNAL ) _____+1
CLOCK r
~~
VGG
CRYSTAL
TOP VIEW
........-r----'
TUFI691)5.2
TL.lF/690501
Order Number MM5307N
See NS Package N14A
Vss
7-6
Absolute Maximum Ratings
Voltage at Any Pin With Respect to VSS +O.3V to VSS - 20V
Power Dissipation
700mW
-65°C to +150°C
Storage Temperature Range
Operati~g
O°C to +70°C
Temperature
300°C
Lead Temperature (Soldering, 10 seconds)
DC Electrical Characteristics
TA within operating range, Vss = 5V ±5%, VGG = -12V ±5%, unless otherwise specified.
SVM
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
All Inputs (Except Crystal Pins)
VIH
Logical High Level
VSS-l.5
VSS+0.3
.v
VIL
Logical Low Level
VSS-18
VSS-4·2
0.5
IlA
7.0
pF
Leakage
VIN = -10V, TA = 25°C,
V
All Other Pins GND
Capacitance
VIN=OV,f= 1 MHz,
All Other Pins GND, (Note 11
External Clock Duty Cycle
Capacitance Measured Across
40%
60%
f = 1 MHz, (Note 3)
5.0
pF
VSS-4·6
V
Crystal Pins
Output Levels
= -0.5 mA
VOH
Logical High Level
ISOURCE
VOL
Logical Low Level
ISINK = 1.6 mA
IGG
Power Supply Current
VSS-2.6
V
VSS
f = 1 MHz
35
mA
AC Electrical Characteristics
T A within operating range Vss
SVM
= 5V ±5%, VGG = -12V ±5%, unless otherwise specified.
PARAMETER
CONDITIONS
Master Frequency
0.8
tA
Access Time
CL = 50 pF, (Note 2)
tRD
Reset Delay Time
f
RPW
Reset Pulse Width
too
Output Delay, From Reset
Output Duty Cycle
MIN
TVP
MAX
UNITS
1.0
MHz
16
= Master Clock Frequency
500 + 4/f
T
= Output Period
ns
ns
500 + 4/t
=0.5T ± lIt
Ils
\
500 + 4/t
0.5T -lIt
0.5T+l/f
ns
f = Master Frequency
Note 1:
Capacitance is guaranteed by periodic measurement.
Note 2: Access time is defined as the time from a change in control inputs (A, B. C, D) to a stable output frequency. Access time is a function of
frequency. The following formula may be used to calculate maximum access time for any master frequency: T A =2.8/ls + l/f x 13, f is in MHz.
Note 3: The MM5307 is designed to operate with a 921.6 kHz parallel resonant crystal. When ordering the crystal a value of loed capacitance (eLI
must be specified. This is the capacitance "seen" by the crystal when it is operating in the circuit. The value of CL should match the capacitance
measured at the crystal frequency across the crystal input pins on the MM5307. Any mismatch will be reflected as a very small error in the
operating frequency. To achieve maximum accuracy, it may be necessary to add a small trimmer capacitor across the terminals.
Note 4:' Jf the crystal osciliator is used Pin 5 (external clock) is connected to VSS. If an external clock is used Pin 7 is connected to \.iSS.
7-7
•
~
Control Table
==
==
Input Freq: 921.6 kHz Master Clock
NOMINAL BAUD RATES
(OUTPUT FREQUENCY/161
CONTROL PINS
A
B
C
D
AA
AB
FAG
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
50
75
110
134.5
150
300
600
900
1200
1800
2400
3600
4800
7200
9600
50
200
110
134.5
150
300
600
900
1200
1800
2400
3600
4800
75
9600
50
75
110
134.5
150
300
600
.1050
1200
45.5
2400
56.9
4800
66.7
9600
DIVISOR
FORAA
1152
768
524
428.5
384
192
96
64
48
32
24
16
12
8
6
EXTERNAL FREQ
Positive Logic: 1 = VH
O=VL
Typical Applications
Internal Oscillator
EXTFREO-.....-'"!
NC
OUTPUT--,-=-!
External Clock
14 "OUT
13
. EXTFREQ-'-'-.!.j
Vss (TO OPERATE)
VGG (TO RESET)
NC
12 VGG
14 "OUT
13
Vss (TO OPERATE)
VGG ITO RESET)
OUTPUT---'-:!.j
11 A
10
EXT CLOCK IN .....--4-.!:.I
B D
TL/F16905-3
Vss
Vss
7-8
• TUFI6905-4
Application Hints
3) Reset (pin 13) must be at VSS to operate. It may be
necessary to take this to GND or VGG to reset the
ROM select circuit. An option is to tie ¢ out (pin 14)
to external Freq In (pin 1), if not otherwise used.
4) An interesting application might use two MM5307's
in series to generate additional frequencies, i.e., with
one programmed from the 921.6 kHz to 800 Hz out,
a second could divide that by 16 to give a 50 Hz
crystal controlled signal.
5) MM5307 AA divisors are on the data sheet. AB
divisors are the same as the AA except: 1) Code 0010
is divided by 288 -> 32 kHz out, 200 baud; 2) Code
1110 is divided by 768 -> 1.2 kHz, 75 baud.
The external clock is brought in on pin 5 and pin 7 is
tied to Vss to enable the external clock input. Pin 6
can be left open; however, this may cause some current
flow that can be eliminated by connecting pin 6 to VDD.
1) To use the MM5307 with an external clock, hook
it up as follows:
EXTERNAL CLOCK
The MM5307 does not always generate an output when
the power is up, even though the oscillator seems to be
operating properly. In order to eliminate this problem,
it is necessary to reset the chip at power "ON". This can
be done manually, with a reset signal by a host system,
or automatically by using RIC timing elements. The
reset is done internally, when program inputs change.
When using an RIC combination for auto resetting,
the time constant must be several times larger than
that of the power supply. For example, most lab power
suppl ies take at least 0.5 sec for the voltage to reach
90% of full level. A 10 kn resistor and 300 /1F capacitor
combination should be adequate for most applications.
TlfFI690S·5
2) To use a crystal directly:
vss
-1V1-"--i
CLOCK TO INTERNAL
CIRCUITRY
TO
vss TO ENABLE XTAL
OSCILLATION
TUF/6905·6
*Component values should be selected based on crystal used.
vss ---I,+--....-ID 1-....--1 r-vss
Vss
POWER SUPPLY TIMING
VOLT AGE
I-
MANUAL
RESET
1-_ _-'AC;Tc:P,:;OW;;.E;;R;.:UP
·2V RESET h,<'----~,....-
THRESHOLD
~~--~---------">:
(1.5 SEC
TIME
TLIFI6905·8
TLlFI6905·7
7-9
~
Timing Diagrams
:E
:E
¢Z
A,B.CorD
OUTPUT
1111111111111111111111111111111111111111111111111111111111111
____,,~+~II~--------------~----------------------------------+9011
----+---'r'-....J"----------:'-~I!/li..._--'\_----.J~--~===:i:if'""'f'~------~--~--~
RESET
TUF/6905-9
~1~EXTCLDCK
OUTPUT (2N DIVISOR)
OUTPUT (2N + 1 DIVISOR)
OUTPUT 12N + 0.6 DIVISOR)
Vss
....,....,
VGG-I
••••••
L.J L-..:
---,
---,
---,
n
.J W
N
n L ........ ruL........JULS .....f"l..Jl....
N
N
N+l
N
N+O.5
N
L-
N
N
N+l
N+l
N-0.5
L
TUFf6905.10 ;
7-10
~National
~ Semiconductor
MM5368 CMOS Oscillator Divider Circuit
General Description
Features
The MM5368 is a CMOS integrated circuit generating
50 or 60 Hz, 10 Hz, and 1 Hz outputs from a 32 kHz
crystal (32,768 Hz). For the 60 Hz selected output the
input time base is divided by 546.133, for the 50 Hz
mode it is divided by 655.36. The 50/60 Hz output is
then divided by 5 or 6 to obtain a 10Hz output which
is further divided to obtain ij 1 Hz output. The 50/60 Hz
select input can be floated for a counter reset.
• 50/60 Hz output
• . 1 Hz output
• 10Hz output
• Low power dissipation
• Fully static operation
• Counter reset
• 3V-15V supply range
• On-chip oscillator - tuning and load capacitors
are the only required external components besides
the crystal. (For operation below 5V it may be
necessa~y to use an - 1 Mn pull up on the oscillator
output to insure start-up.)
Block and Connection Diagrams
O~~~6_..._....,
----t..VSS
1M
DECODE
&
SELECT
lOGIC
1+_ _ _ _ _ _ _ _+
____+
J
~o~~~~~
10 Hz
OUTPUT
41Hz
OUTPUT
COUNTER RESET
(ON·CHIP)
TL/FI6133-1
FIGURE 1
Dual-In-Line Package
50/60 Hz OUT
VOD
7
Order Number MM536BN
See NS Package NOBE
50/60 Hz SELECT
OSC IN
5
OSC OUT
TOP VIEW
FIGURE 2
7-11
TL/FI613J-2
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
-0.3V to VOO + 0.3V
, OU Cto +70°C
-65°C to +150°C
Maximum VOO Voltage'
16V
3V:$ VOO:$ 15V
Operating VOO Range
Lead Temperature (Soldering, 10 seconds)
300°C
,
Electrical Characteristics TA within operating range, VSS ~ OV
,
I
PARAMETER
CONOITIONS
Quiescent Current Orain
VOO
Operating Current Orain
fiN
fiN
~
~
~
15V; 50/60 Select Floating
32 kHz, VOO
32 kHz, VOO
Maximum Input Frequency
VOO
VOO
~
~
3V
15V
Output Current Levels
Logical-"l", Source
VOO
~
5V
VOH
~
VSS + 2.7V
~
~
Logical "0", Sink
VOL ~ VSS + O.4V
VOO ~ 9V
Logical "1", Source
VOH
Logical "0", Sink
VOL ~ VSS + O.4V \
Input Current Levels
Logical "1" (lIH)
Logical "1" (lIH)
Logical "0" (II Ll
Logical "0" (II Ll
Functional Description
~
MIN
3V
15V
TYP
MAX
10
/lA
50
1500
/lA
64
500
kHz
kHz
-400
/lA
400
/lA
/lA
-1500
VSS + 6.7V
UNITS
1500
/lA
/lA
50/60 Select Input
VOO
VOO
~
50
~
3
20
'3V, VIN ?0.9VOO
15V, VIN ;?0.9VOO
VOO ~ 3V, VIN:$ O. lV OO
VOO ~ 15V, VIN:$ O.lVOO
1
/lA
mA
/lA
mA
(Figure 1)
cycle. In the 50 Hz mode the 50/60 select input is tied
to VSS. The 50 Hz output waveform can be seen in
Figure 3. The 10Hz output has an approximate 40%
duty cycle and the 1 Hz output has an approximate 50%
duty cycle.
The MM5368 initially divides the input time base by
256. From the resulting frequency (128 Hz for 32 kHz
crystal) 8 clock periods are dropped or eliminated during
60 Hz operation and 28 clock periods are eliminated
during 50 Hz operation. This frequency is then divided
by 2 to obtain a 50 or 60 Hz output. This output is not
periodic from cycle to cycle; however; the waveform
repeats itself every second. Straight divide by 5 or 6 and
10 are used to obtain the 10 Hz output and ,~he 1 Hz
outputs.
For the 50/60 Hz select input floating, the counter chain
is held reset, except for the initial toggle flip-flop which
is needed for the reset function. A reset may also occur
when the input is switched (Figure 4). To insure the
floating state, current sourced from the input must be
limited to 1.0 /lA and current sunk by the input must
be limited to 1.0/lA for VOO ~ 3V.
The 60 Hz mode is obtained by tying pin 7 to VOO. The
60 Hz output waveform can be seen in Figure 3. The 10
Hz and 1 Hz outputs have an approximate 50% duty
7·12
Timing Diagrams
60Hz
OUTPUT
,,
1.8ms_:
: L(
I
:,
,
PHASESHIFT~O
,)-.-1
EVERYB CLOCKS DUE TO
ELIMINATION OF 1 INPUT CLOCK I. e, 128 Hz CLOCK)
1 ClOCI{DROPPED
[
rEVERY 5'28 H, CLOCKS
50Hz
OUTPUT
L(
PHASE SHIFTEDJ TIMES/SEC
DUE TO ELIMINATION Of 3
12B Hz CLOCKS
Tl/FI6133·3
FIGURE 3. 50/60 Hz Output
VDD
16kHz
RESET
-----IlL...-__..JnL-__.J
50{60
SELECT
TLIF/6133·4
TLlF/6133·5
FIGURE 4. 50/60 Select and Reset
Typical Applications
RESET
LATCH
13
18 Vss
.-_...._ -___""1
NS81B61
50/60 '
H,
MM5J68 10 Hz
1"'-__""','
MM14C921
•
IH'
Vss
11
10
8 ,,'_ _ _ _- - /
* If the crystal used is a microwatt type an R value will
be required to limit power to the crystal.
av
5V
10V
A
~
0
A~100K·
A
~
aaOK
TLlF16133-6
FIGURE 5. 10 Minute (9:59.9) Timer
7-13
!
.
~ ~ Semiconductor
, U)
~ National
MM5369 Series 17 Stage Oscillator/Divider
General Description
Features
The MM5369 is a CMOS integrated circuit with 17
binary divider stages that can be used to generate a
precise reference from commonly available high frequency quartz crystals. An internal pulse is generated
by mask programming the combinations of stages 1
through 4, 16 and 17 to set or reset the individual stages.
The MM5369 is advanced one count on the positive
transition of each clock pulse. Two buffered outputs
are available: the crystal frequency for tuning purposes
and the 17th stage output. The MM5369 is available
in an 8-lead dual-in-line epoxy package.
• Crystal oscillator
• Two buffered outputs
Output 1 crystal frequency
Output 2 fuil division
• High speed (4 MHz at VDD = 10V)
• Wide supply range 3-15V
• Low power
• Fully static operation
• 8 lead dual-in-line package
• Low current
Options
3.58 MHz to 60 Hz
3.58 MHz to 50 Hz
3.58 MHz to 100 Hz
• MM5369AA
• MM5369EYR
• MM5369EST.
i
/
Connection and Blo~k Diagrams
Dual-In-Line Package
TUNER
OUTPUT OSC OUT DSC IN
Vou
Is
6
7
5
OSC OUT
OSC IN
r
r-
DIVIDER
OUTPUT
TUNER
OUTPUT
2
1
DIVIDER
Vss
3
NC
14
TUFI6134·2
NC
OUTPUT'
TOPVIEW
TLIFf6134·1
FIGURE 2
FIGURE 1
Order Number MM5369N
See NS Package NOSE
7-14
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Package Dissipation
-0.3V to VDD +0.3V
O°C to +70°C
-65°C to +150°C
500mW
Maximum VCC Voltage
Operating VCC Range
Lead Temperature (Soldering, 10 seconds)
16V
3Vto 15V
300°C
Electrical Characteristics
T A within operating temperature range, VSS = GND, 3V
PARAMETER
~
VDD ~ 15V unless otherwise specified.
CONDITIONS
VDD = 15V
Operating Current Drain
VDD = 10V, fiN = 4.19 MHz
Frequency of Oscillation
VDD = 10V
VDD = 6V
Output Current Levels
TYP
MAX
10
IlA
1.2
2.5
mA
DC
4.5
MHz
DC
2
MHz
MIN
Quiescent Current Drain
UNITS
VDD = 10V
'VO= 5V
Logical "I" Source
500
IlA
Logical "0" Sink
500
IlA
Output Voltage Levels
VDD = 10V
10 = 10IlA
Logical "1"
V
9.0
1.0
Logical "0"
V
Note: For 3.58 MHz operation, VOO must be;:: 10V.
Functional Description
. A connection diagram for the MM5369 is shown in
Figure 1 and a block diagram is shown in Figure 2.
DIVIDER
A pulse is generated when divider stages 1 through 4, 16
and 17 are in the correct state. By mask options, this
pulse is used to set or reset individual stages of the
counter. Figure 4 shows the relationship between the
duty cycle and the programmed modulus.
TIME BASE
A precision time base is provided by the interconnection
of a 3,579,545 Hz quartz crystal and the RC network
shown in Figure 3 together with the CMOS inverterl
amplifier provided between the OSC IN and the OSC
OUT terminals. Resistor R 1 is necessary to bias the
inverter for class A amplifier operation. Capacitors C1
and C2 in series provide the parallel load capacitance
required for precise tuning of the quartz crystal.
OUTPUTS
The Tuner Output is a buffered output at the crystal
oscillator frequency. This output is provided so that the
crystal frequency can be obtained without disturbing the
crystal oscillator. The Divide Output is the input frequency divided by the mask programmed number. Both
,outputs are push-pull outputs.
The network shown provides> 100 ppm tuning range
when used with standard crystals trimmed for CL =
12 pF. Tuning to better than ±2 ppm is easily obtainable.
7-15
•
Functional Description
(Continued)
110
100
90
,------1">0-----,
OSCIN- ~ -
-
-
-
-
-
-OS&OUT
-
~
E
>
R1
20M
~
*""-1k
:;:
0
1
+-;----11 1-----+
-It. 01
.. TS-J6PF
3.,J,,,: ~H'
'- C2
Cl:12pF
TJOPF
C
VOO OR VSS (10VI ....- - - - - - - - - - - - - '
,
I
80
70
60
50
/
.-
40
30
20
IO
l-
V
V
_r- V
0
10 ·20
0
*To be selected based on xtal use9
30
40
50
60
70
DUTY CYCLE (%)
TlIF/6134-4
FIGURE 3. Crystal Oscillator Network
F.IGURE 4. Plot of Divide-By vs Duty Cycle
,,
--
- - f.-- -
voo - 10V
,
/'
~
~'.875
I
I
I
".,84==l
COUNTS---!-COUNTS
--59.6S9COUNTS--------i
TL/F/6134·6
MHz
TlIF/6134·5
FIGURE 5. Typical Current Drain vs Oscillator Frequency
FIGURE 6. Output Waveform for Standard MM5369AA
7-16
~National
~ Semiconductor
MM53107 Series 17·Stage Oscillator/Divider
General Description
Features
The MM53107 is a low threshold voltage CMOS
integrated circuit with 17 binary divider stages that can
be used to generate a precise reference from a 2.097152
MHz quartz crystal. An internal pulse is generated by the
combinations of stages 1-4. 16 and 17 to set or reset
the individual stages. The MM53107 is advanced one
count on the positive transition of each clock pulse. One
buffered output is available: the 17th stage 60 Hz output. The MM53107 is available in an S·!ead dual-in-line
epoxy package.
•
Input frequency--2.097152 MHz
•
•
Output frequency-60Hz
Crystal oscillator
•
•
High speed (2 MHz at VDD ~ 2.5V)
Wide supply '-ange 2.5V-6V
•
•
•
Low power (0.5 mW @ 2 MHz/2.5V)
Fully static operation
S-Iead dual-in-line package
Block and Connection Diagrams
Dual-In-Line Package
VOD
Ne
OSC OUT OSC IN
DIVIDER
OUTPUT
MM53107
t
voo
FIGURE 1
Tl.'F/fi142-\
DIVIDER
Vss
NO
NO
OUTPur
TOPVIEW
FIGURE 2
Typical Perlormance Characteristics
Order Number MM53107N
See NS Package N08E
Typical Current Drain vs
Oscillator Frequency
600
r-'-~--'--'--~rrr--'
550
500
450
~
~
400
350
'< 300 f---+--j---H'A---/-+.I'-11---I
.3
250 1---+-t~--tl'---j.'7"h'-+--I
200
150 f---+-t-4:1hM-T-'
100
50
L-~~-LL--L~
voo IVI
7-17
__~~
TLlF16142-3
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Package Dissipation
-o.3V to VCC + 0.3V
O°C to +70°C
-ti5°C to +150°C
500mW
Maximum VCC Voltage
Operating VCC Range
"Lead Temperature (Soldering, 10 seconds)
7V
2.5V to 6V
300°C
,
Electrical Characteristics
TA withi~ ciperating temperature range; Vss = Gnd, 2.5V'::; VOO'::; 6V unl,ess otherwise specified.
PARAMETER
CONDITIONS
MIN
Quiescent Current Drain
VOO=,6V
Operating Current Drain
VOO= 2.5V, fiN = 2.1 MHz
Frequency of Oscillation
VOO= 2.~V
VOO= 6V
dc
dc
VOO=4V,
100
100
Output Current Levels
Logical "1 .. Source
Logical "0 " Sink
MAX
UNITS
10
VOUT=2V
Output Voltage Levels
Logical "1"
Logical "0"
TVP
VOO=6V loSource = 10 JJA
loSink = -10JJA
JJA
200
JJA
2.1
4.0
MHz
MHz
JJA
JJA
V
V
5.0
1.0
Functional Description
A connection diagram for the, MM53107 is shown in
Figure 2 and a block diagram is shown in Figure 1.
The network shown provides> 100 ppm tuning range
when used with standard crystals trimmed for CL =
'12 pF. Tuning to better than ±2 ppm is easily obtainable.
DIVIDER
A pulse is generated when divider stages 1-4, 16 and 17
are in the correct state. This pulse is used to set or reset
individual stages of the counter, the modulus of the
counter is 34,952 to provide 60 Hz.
TIME BASE,
A precision time base is provided by the interconnection
of a 2,097,152 Hz quartz crystal and .the RC network
'shown in Figure 3 together with the CMOS inverter/
amplifier provided between the Osc In and the Osc Out
terminals. Resistor R 1 is necessary to bias the inverter
for class A amplifier operation. Capacitors C1 and C2
in series provide the parallel load capacitance required
for precise tuning of the quartz crystal.
OSCIN-
f-----,
-----
f-
RI
20M
OUTPUT
The Divide Output is the input frequency divided by
34,952. The output is a push-pull output.
-OSC OUT
I
'~lk
2.168
I
L:~
32,184
TUFIS142·5
I [] I
-r-
[tCI
5- 3&pF
Voo ORVSS
2,O~1,'52IHZ
CL = 12 pF
-'-C2
T
30PF
)
"'1'0 be selected based on the crystal used
TUF16142-4
FIGURE 3. Crystal, Oscillator Natwork
FIGURE 4. Duty Cycle for MM53107
,
,
7-18
.
~ Semiconductor
~National
MM53126 Infrared Remote Control Transmitter
General Description
The MM53126 is an infrared remote control transmitter
circuit using low threshold N·channel enhancement and
depletion 'devices. This versatile circuit is ideal for
sophisticated TV/HiFi consumer applications. The
transmission of information is achieved using bursts of
pulse code modulated infrared light. Each burst con·
sists of a fixed number of constant amplitude pulses
with binary coded spaces. This system allows high
pulse current drive to the transmitter diodes, and also
high data integrity with noise immunity. The circuit
features very low quiescent current drain guaranteeing
long battery life.
•
•
•
•
Pin compatible with ITT 1050/1250
0.1 % IR drive ensures long battery life
6·bit data word, 2·bit address word
Simple RC oscillator only requires 3 external
components
• Keyswitch requirements allow use of low cost
keyboard
• Simple interface to high current IR diodes
• Double key depression detection
Applications
Features
•
•
•
•
•
•
•
•
•
64 commands to 4 addresses
Simple interface to Standby 9V battery
'One·Shot' word transmission capability
Very low standby current - 1OI'A typical
Remote control of TV
Remote control of HiFi
Remote machine control
Remote ASCII keyboard
Serial keyboard encoder
Block Diagram
COLUMN INPUTS
ROW INPUTS
.ADORESS INPUTS
0--:
o---i
ADDRESS
DECODE
TLIFI699B·'
Figure 1
7-19
~
~
:E
:E
I
1
Absolute Maximum Ratings
Voltage at Any Pin
. Storage Temperature
Lead Temperature (Soldering 10 seconds)
Electrical Characteristics
Sym
/
Parameter
Voo Supply Voltage
Supply Current
100
-0.5 to 12V
-65°C t~ ~~:~
TA = o·c, Vss = OV, Voo = 6.5V to 7.5V, unless otherwise specified.
Conditions
Typ
Min
6.5
10
Voo=9V No. key depressed
Voo = 7V Valid key depressed
(See Figure 5)
Oscillator Frequency
Output Logic Levels
Serial Out Logic "0"
Logic "1"
160
Cr=47pF 2%
RT=33k 1%
Rs=33k 5%
(See Figure 5)
1 Sink=0.2mA
1 Source=0.2mA
Max
Units
7.5
V
20'
10
mA
220
kHz
0.2
V
V
1.0
Connection Diagram
Functional Description
The block diagram of the MM53126Is shown In Figure 1.'
A connection diagram is shown in Figure 2.
The MM53126 operates using a simple 8 x 8 keyboard'
giving 64 different commands. The two inputs FA and FB
are address Inputs which allow a total of 256 messages
to be transmitted. These· commands are transmitted
using pulse position modulation. See Figure 4.
Dual-In-Llne Package
VSS-~ !--VDD.
The row and column circuitry recognizes when a single
row Is connected to a single column and removes the reset
from the circuit. This activates the oscillator whose frequency is determined by the external components CT, RT
and Rs. If a row input is connected to a column input for
greater than 40k clocks the message is transmitted uSing
14 pulses of data. For the period that the row is c6nnected
to the column the message is transmitted eve'ry 40k
clocks.
OSC CT- 2
23 ~COLA
OSC RT- 3
22 ~COLB
OSC RS- 4
21 ~COLC
IIR OUTPUT- 5
20 ~COLD
6
ADDRESS FA -
7
18!--COL F
ROWH- 8
17~COLG
Releasing the Row-Column connection powers down the
. circuit to a standby condition of very low current consumption to conserve battery power. If the key contact
Is released during the transmission of a message,
the circuit will complete the transmission before powering down.
MM53126
19 ~COLE
ADDRESS FB -
RDWG- 9
16~COLH
ROWF- 10
15!--ROW A
ROWE- 11
14!--ROW B
ROW 0 - 12
13~ROWC
Top View
TLIFI6998-2
Figure 2
Order Number MM53126N
See NS Package N24A
The multi-key depression detection circuit Inhibits the
output if more than one key is depressed.
The encoder provides at the output, via the parallel to
serial converter, one of 64 codes (see Table 1). One of four
addresses may be selected (see Table 2) giving a total of
256 commands that may be transmitted.
Typical Keyboard Specifications
7-20
RON
5k max
ROFF
300k
min
Format of Transmitted Signal:
The information is transmitted in coded groups of infra·
red ·Iight pulses. The binary value of a single bit is
. represented by the time space between leading edges
of two consecutive pulses. With an input oscillator
frequency of 200kHz a time T/:::'100l's is defined as the
unit space (1T) representing a binary zero, a double
space (2T) represents a binary one. See Figure 3.
n
,.
Eleven pulses are required for each word consisting of 4
bits for address and 6 bits for data. Each word is
preceded by a calibration and start pulse at intervals of
1T and 3T respectively. A stop pulse is transmitted 3T
after the last data pulse.
n
+
T!:>1DD~S
LOGIC '0'
-n-1D~S
T!:>2DD~S
.,
LOGIC '1'
TL/F/6998·3
All times are related to an input oscillator frequency of approximately 200 kHz
Figure 3
ADDRESS
I
3T
.PREPULSE
In I
\
FB
FA
AD
I~~ I
2T
I
FIXED
r-'-1
A2
2T
I
A3
2T
I'~~ I :; I
D2
D3
2T
2T
3T
/
CALIBRATION
PULSE
STOP PULSE
Format of message 001100 to address 1101
Figure 4
7·21
TlIF16998·4
Tabla 1. Instruction Tabla
Row Input
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
50.
51.
52.
53.
54.
55.
56.
57.
58.
59.
60.
61.
62.
63.
64.
a b c d a
x
x
x
x
x
x
x
x
x
x
x
x·
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
f
9 h
A
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
B
"
x
x
x
x
x
x
x
x
Column Input
C D E F
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
7·22
x
x
x
x
x
x
x
x
G
x
x
x
x
x
x
x
x
H
x
x
x
x
x
x
x
x
-Binary Coda
6 Bit Data
MSB
LSB
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 1
0 0 1 0
0 0 1 0
0 0 1 1
0 0 1 1
0
0
0
0
0
0
0
0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 O.
1 0
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1.
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1.
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
O.
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Intarnatlonal
REF 6 Bit
ASCII Coda
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
@
A
B
C
D
E
F
G
H
I
J
K
L
M
N
0
P
a
R
S
T
U
V
W
X
Y
Z
[
\
I
A
..!
SP
#
$
%
&,
(
~
+,
/
0
1
2
3
4
5
6
7
8
9
:
,
<
=
.>
?
3:
3:
(11
Address Decoding
....
Co)
FA
FB
1
1
0
0
1
0
1
0
Address
1 1
1 1
1 0
1 0
I\)
(I)
1
0
1
0
Address 1100 enables one shot mode which allows the message to be transmitted only once for each key
depression.
Table 2
Typical Application Diagram
(256 code transmitter with visual "feedback)
lan
f~
:=:9V
-!
~ ~;~753
r-
C
Bxa MATRIX KEYBOARD
RT
RS -
10 kl1
KEYBOARD
ACTIVE LED
~TlP30
t'-.
t'-.
0.3n
t'-.t'-.
t'-.
I\.
t'-.
t'-.
~~
27011
~'"!?
-
,
INFRARED
DlOOES
XCITDN
xc-aaO-B
GE F5Dl
~
IDUTPUK
+9V
~
I
I
FA
2N2222
FB
t
-<.-
TYPICAL KEYSWITCH
TLIF16998·5
"If not required LED can be replaced by three 1N914 diodes
Oscillator Typical Values
Cr
RT
Rs
47pF 2% polystyrene or silver mica
1 % metal oxide
5%
Figure 5
7-23
CD
~ ~ National
.
~ ~ Semiconductor
MM53226 Infrared Remote Control Transmitter
General Description
The MM53226 is an infrared remote control transmitter
circuit using low threshold N-channel enhancement and
depletion devices. This versatile circuit is ideal for
sophisticated TV/HiFi consumer applications. The
transmission of information is achieved using bursts of
pulse code modulated Infrared light, each burst consists of a fixed number of constant amplitude pulses
with binary coded spaces. This system allows high
pulse current drive to the transmitter diodes, and also
high data Integrity with noise Immunity. The circuit
features very low quiescent current drain guaranteeing
long battery life.
• 0.1 % IR drive ensures long battery life
• 6-blt data word, 2-bit address word
• Simple RC oscillator only requires 3 external
components
• Keyswitch requirements allow use of low cost
keyboard
• Simple'interface to high current IR diodes
• Double key depression detection
Applications
Features
•
•
•
•
64 commands to 4 addresses
Simple Interface to Standby 9V battery
Very low standby current- 10l'A typical
Pin compatible with ITT 1050/1250
•
•
•
•
.•
Remote control of TV
Remote control of HIFI
Remote machine control
Remote ASCII keyboard
Serial keyboard encoder
Block Diagram
COLUMN INPUTS
ROW INPUTS
ADDRESS INPUTS
TUF/6999·'
Figure 1
7-24
,----------------------.-----------------,3:
3:
Absolute Maximum Ratings
Voltage at Any Pin
Storage Temperature
. Lead Temper~ture (Soldering, 10 seconds)
Electrical Characteristics
~
-0.5 to 12V
~5°C to i50°C
300°C
c:n
TA = o·c, Vss = OV, Voo = 6V to i0V unless otherwise speeHied.
-----
Sym
Parameter
Voo Supply Voltage
100 Supply Current
Oscillator Frequency
Output Logic Levels
Serial Out Logic "0"
Logic "1"
Conditions
Min
Typ
-
---.---.--
Units
10
V
20
10
I'A.
mA
220
kHz
0.2
V
V
6
Voo = 9V No key depressed
10
Voo = 7V Valid key depressed
(See Figure 5)
CT -47pF 2%
RT =33k 1%
Rs=33k5%
(See Figure 5)
--------".- - ------
Max
160
-
1 Sink=0.2mA
1 Source = 0.2mA
1.0
-.---- ----
Connection Diagram
Functional Description
The block diagram of the MM53226 is shown in Figure 1.
A connection diagram is shown in Figure 2.
Dual·ln·line Package
The MM53226 operates using a simple B x B keyboard
giving 64 different commands. The two inputs FA and FB
are address inputs whi.ch allow a total of 256 messages
to be transmitted. These commands are. transmitted
using pulse position modulation. See Figure 4.
Vss- 1
24 ....... Von
OSr,CT'- 2
23 -COLA
OSC RT- 3
22 r--COL B
21 -COL C
OSCRs- 4
The row and column circuitry recognizes when a single
row is connected to a single column and removes the reset
from the circuit. This activates the oscillator whose frequency is determined by the external components CT, RT
and Rs. If a row input is connected to a colunin input for
greater than 40k clocks the message is transmitted using
14 pulses of data. Forthe period that the row is connected
to the column the message is transmitted every 40k
clocks.
Releasing the row·column connection powers down the
circuit to a standby condition of very low current con·
sumption to conserve battery power. If the key contact
is released during the transmission of a message
the circuit will complete the transmission before power·
ing down.
20 -COLO
I/R OUTPUT -
5.
AOORESS FB -
6
AODRESS FA -
7
18 _COL F
ROWH- 8
17-COLG
MM53226
19 r-- COL E
ROWG- 9
16 -COLH
ROWF- 10
15 r--ROWA
ROW E- 11
14 -ROW B
ROWO-12
13-ROWC
TLlFI6999·2
Top View
Figure 2
Order Number MM53226N
See NS Package N24A
The multi·key depression detection circuit inhibits the
output if more than one key is depressed.
The encoder provides at the output, via the parallel to
serial converter, one of 64 codes (see Table 1). One of four
addresses may be selected (see Table 2) giving a total of
256 commands that may be transmitted.
Typical Keyboard Specifications
7·25
RON
5 kU max
ROFF
300 kU min
•
Format of Transmitted Signal:
The information is transmitted in coded groups of infrared light pulses. The binary value of a single bit is
represented by the tll)'le space between'leading edges
of two consecutive pulses. With an Input oscillator
frequency of 200kHz a time T6.1001's is defined as the.
unit space (1n representing a binary zero, a double
space (2n represents a binary one. See Figure 3.
n
~I
Eleven pulses are required for each word consisting of 4
bits for address an'd 6 bits for- data. Each word Is
prece,ded by a calibration and start pulse at intervals of
1T and 3T respectively. A stop pulse is transmitted 3T
after the last data pulse.
n
-n-l0~S
------ L--------J'I
T6100~S
T6200~S
LOGIC '0'
LOGIC 'I'
TLIFI6999·3
All times are related to an Input oscillator frequency of approximately 200kHz.
Figure 3
ADDRESS
I
PREPULSE
CALIBRATION
STOP PULSE
PULSE
TL/FIil999-4
Format of message 001100 to address 1101
Figure 4
'7-26
Table 1. Instruction Table
1.
2.
3.
4.
5.
6.
'7.
8.
9.
10..
11.
12.
13.
14.
15.
16.
a b
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Row Input
c d e f
9 h
x
x
B
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
41.
42.
43.
44.
45.
46.
47.
48.
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
.x
x
x
x
x
x
x
x
x
x
x
a
a
a
a
a
a
a
a
a a a
a a 1
a 1 a
a 1 1
1 a a
1 a 1
1 1 a
@
1
1
G
1·
1
1
1
1
1
1
1
a a a
a a 1
a 1 a
a 1 1
1 a a
1 a 1
H
1
1
1
1
1
1
1
a a
a a
a "'a
a a
a 1
a 1
a 1
a 1
1 a
1 a
1 a
1 a
1
x
x
1
1
1
1
x
1
x
1
1
x
x
1
1
x
1
1
1
x
x
x
x
x
x
x
x
x
x
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
1
x
x
x
57.
58..
59.
60.
61.
62.
63.
64.
x
x
x
x
\
x
x
x
x
x
x
7·27
x
x
x
x
x
.x
International
REF 6 Bit
ASCII Code
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
1
1
x
49.
50..
51.
52.
53.
54.
55.
56.
x
x
x
x
x
x
x
x
x
x
33.
34.
35.
36.
37.
38.
39.
40..
x
x
H
x
x
x·
x
x
x
x
25.
26.
27.
28.
29.
30..
31.
32.
x
G
Binary Code
6 Bit Data
MSB
LSB -
)<
x
17.
18.
19.
20..
21.
.22.
23.
24.
A
Column Input
C 0 E F
1
1
1
1
f
1
1
1
1
1
1
1
1
0
1
a a
a 1
1 a
1 1
0 a
a 1
1. a
a
a
a
0.
a
a
a
a
a a a
a a 1
a 1 a
a '1 1
1 a 0
1 a 1
1 1 a
1
1
1
a a a
a a 1
a 1 a
a 1 1
1 a 0
1 a 1
1 1 a
1
1
1
a
a
a
a
a
a
a
a
a a a
a a 1
a 1 a
a 1 1
1 a a
1 a 1
1 1 a
1
1
1
a a a
a a 1
a 1 a
a 1 1
1 a a
1 a 1
1 1 a
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
J
K
L
M
N
0
p
Q
R
S
T
u
v
x
y
z
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
1
F
W
1
1
E
1
1
1
1
0
a a
a 1
1 a
1 1
a a
a 1
1 a
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A
B
C
1
1
1
1
1
1
1
1
1
1
[
\
1
A
-
SP
!
"
#
$
%
&,
(
)
*
+
/
a
1
2
3
4
5
6
7
8
9
:
,
<
=
>
?
•
co
N
N
CO?
Address Decoding
U)
:E
:E
FA
1
1
0
0
Address
MSB
LSB
0 0 0 0 Note 1
1 1 1 0
1 0 0 1
0 0 0 0
FB
1
0
1
0
Note 1: When a key is depressed with FA =FB = 1 the first message is transmitted with address 0000, all following
messages are transmitted with address 1111 for as long as the key is depressed.
Table 2
Typical Application Diagram
(256 code transmitter with visual "feedback)
IS!l
-:-9Y
ci
T
,!.
8x8 MATRIX KEYBOARD
"'-
. fl
RT
f
~~~753
Rs -
10 kll
r KEYSOARD
ACTIVE LED
0.31l
~TIP30
I"\.I"\.
I"\.
K
I"\. 1"\."1"\.1"\.
I"\.
~~~
2701l
INFRA·
RED
~,.~ DIODES
XCITON
XC·880·S
GE F501
-r--'l./
K
IOUTPU
~
r-;e.
r
2N2222
500~F
+9Y
t.. I
FB
IFA
l.
...
TUF/6999-5
*If not required Keyboard Active LED can be replaced by three 1N914 diodes
Oscillator Typical Values
CT 47pF 2% polystyrene or silver mica
RT 1 % metal oxide
Rs 5%
Figure 5
7·28
.
~ Semiconductor
~National
MM5437 Digital Noise Source
General Description
Features
The MM5437 device is a monolithic metal gate NMOS integrated circuit which may be used as a digital noise source or
a pseudo-random number generator. The part is designed
to produce a broadband white noise signal with uniform
noise quality and output amplitude. Two outputs are provided. The first, OUT 1, is sequence-limited to reduce
"thumps." The· other output, OUT 2, is the last stage of the
shift register when.CONTROL 2 is left floating or is pulled
up. Typical cycle time is one minute. Data is clocked in and
out on the rising edge of the clock.
•
•
•
•
•
•
•
•
•
•
•
•
Applications
•
•
•
•
Electronic musical rhythm instrument sound generators
Music synthesizer white and pink noise generators
Room acoustics testingl equalization
Pseudo-random number generator
Internal self-contained oscillator
Single supply voltage range of 4.5V to 11 V
TIL compatible at 5V
Normal and sequence-limited ou1puts
Low power consumption
One minute cycle time
External loading and clocking capability
Automatic reset for all-zeros state
Uniform noise quality
Uniform noise amplitude
Eliminate noise preamps
Single component insertion
Block and Connection Diagrams
DUTZ/DATA IN
OUT 1
CONTROL 1
INT/EXT CLK
TL/F/5260-1
CONTROL 1
INTERNAL/EXTERNAL CLOCK
CONTROL 2
OUT 2/DATA IN
TLlF/5260-2
Top View
Order Number MM5437N
See NS Package Number N08E
7·29
•
Absolute Maximum Ratings indicate limits beyond which
damage to the device may occur.
Absolute Maximum Ratings
Operating Supply Voltage, Voo
12V
- 65·C to + 150·C
Storage Temperature, TS
Operating Temperature, TA
- 40·C to + 85·C
. ±12mA
DC Output Current, per pin
Lead Temp. (Soldering, 10 seconds)
+300"C
DC Electrical Characteristics TA within operating range, Vss = OV, Voo = 11V, unless specified
Parameter
Conditions
Min
Supply Voltage (Voo)
Supply Current (100)
Output Voltage Levels
Logic '0'
Logic '1'
Voo
Voo
Max
= 4.5V (No load)
= 11V (No load)
IOl = + 1.6 mA, Voo = 4.5V
IOH;= -400 p.A, Voo = 4.5V
Input Voltage Levels
Logic '0'
Logic '1'
Input Currents
Logic '0'
Logic '1'
Typ
4.5
Vss
2.4
Units
11
V
4
5
mA
mA
0.4
Voo
V
V
0.8
2.0
VIN
VIN
V
= 0.4V
= 2.4V
200
200
p.A
p.A
Half Power Point"
30
140
kHz
Cycle Time
25
110
sec.
'Half Power Point = 0.45 (Shift Aegister Clock Frequency)
.
ACTiming
-40·C ~ TA ~ +85·C
4.5V ~ Voo ~ 11V
Parameter
Min
ts
Symbol
Data Set Up Time Prior to Clock
100
tH
Data Hold Time After Clock
100
tc20V
CONTROL 2 to Data Out Valid
tclKOV
Clock to Data Out Valid
tpH
Clock Pulse Width High
1.5
tpl
Clock Pulse Width Low
1.5
tr , tf
Input Rise and Fall Times
Max
Units
ns
ns
100
700
ns
ns
p.s
p.s
220
' ns
Inputs/Outputs
OUT 1: An output pin for the sequence-limited output from
the shift register.
INT/EXT CLK: An input/output pin. See CONTROL 1 for
description.
OUT 2/DATA IN: An input/output pin. See CONTROL 2 for
description.
CONTROL 1: A mode switch input, which when held at a
logic "1" or left floating, gates the internal o!jlCillator onto
the INTIEXT CLK pin. When CONTROL 1 is at a logic "0",
the shift register can be driven externally through the INTI
EXT CLK pin.
CONTROL 2: A mode switch input, which when held at a
logic "1" or left floating, gates the last stage of the shift
register onto the OUT 2/DATA IN pin. When CONTROL 2 is
at a logic "0", the shift register can be loaded externally
through the OUT 2/DATA IN pin.
7·30
Timing Diagrams
CUI
DATA
IN -"''T~-------~
DATA
OUT _ _-+-_"I~~
'-________'" ,,______
________-'" ___________J
,,_ __
TL/F/5260-3
\.
OUT2
60
)(
J
20
o
OV
TL/F/5260-5
60
fJ
T=25'C
50
-
Voo=5V
Voo=8V
Voo=8V
30
10
--iiiiiL-:JI!"--_.
TL/F/5260-4
Voo=I1V
40
Voo
i-tc2Dv
T=25'C
50
i
ANY
INPUT
VAUOOATA
~5V
,,"VoO-)1~-
10
o
04681012
I""'02481012
VouT (VI
VOUT (VI
TLlF/52eo-7
TL/F/5260-6
FIGURE 2.ISOURCE vs VOUT
FIGURE 1.ISINK vs VOUT
Typical Applications
5 OUT 2/0ATA INi-_ _ _ _ _.....
SERIAL
TO
PARALLEL
3k
MM OUTI
5437
CLOCK
--_--I
TL/F/5260-9
TLlF/5260-B
FIGURE 4. Pseudo-Random Number Generator
FIGURE 3. Pink NOise Generator
7·31
•
~National
~ Semiconductor
MM5450, MM5451 LED Display Drivers
General Description
The MM5450 and MM5451 are monolithic MaS integrated
circuits utilizing N-channel metal-gate low threshold,
enhancement mode, and ion-implanted depletion mode
devices. They are available in 40-pin molded or cavity dualin-line packages. A single pin controls the LED display
brightness by setting a reference current through a
variable resistor connected to Voo.
".
• Wide power supply operation
• TTL compatibility
• 34 or 35 outputs, 15mA sink capability
• Alphanumeric capability
Applications
Features
• cops ™or microprocessor displays
• Continuous brightness control
• Industrial control indicator
• Serial data input
• No load signal required
• Relay driver
• Digital clock, thermometer, counter, voltmeter
• Enable (on MM5450)
• Instrumentation readouts
Block Diagram
VOO
OUTPUT 34
OUTPUT 1
--=.,.....,,---4
BRIGHTNESS ~...
CONTROL
24
18
bA~AU~~~;~~ ~::~~~: ....---=t-,
SEOR~~~ ....- - - = H
---...:.;.H
CLOCK ....
>------'
TLlF/6136·'
FIGURE 1
Connection Diagrams (Dual-In-Line Packages)
40
Vss
39
OUTPUT BIT 17
38
OUTPUT BIT 16
31
OUTPUT BIT 15
36
OUTPUT BIT 14
35
OUTPUT BIT 13
OUTPUT BIT 12
OUTPUTBITl1
OUTPUT BIT 10
OUTPUTBIT 9
OUTPUT BIT 8
10
11
MM5450
OUTPUT BIT 1
OUTPUT BIT 6
OUTPUT BITS
OUTPUT BIT 4.
OUTPUT BIT 3
OUTPUT BIT2
OUTPUT BIT 1
BRIGHTNESS CONTROL
15
16
17
18
19
OUTPUT BIT 18
Vss
OUTPUT 81T 19
OUTPUT BIT 17
OUTPUT BIT20
OUTPUT BIT 16
OUTPUT BIT 21
OUTPUT BIT 15
OUTPUT BIT 22
OUTPUT BIT 14
OUTPUT BIT 23
OUTPUTBIT 13
OUTPUT BIT 24
OUTPUTBIT 12
OUTPUT BIT25
OUTPUT BIT 11
OUTPUT BIT26
OUTPUT BIT 10
OUTPUT BIT21
OUTPUT BIT9
OUTPUT BIT 28
OUTPUT BIT 8
OUTPUT BIT 29
OUTPUT BIT 7
OUTPUTBIT 30
OUTPUTBIT6
OUTPUT BIT 31
OUTPUT BITS
OUTPUTBIT 32
OUTPUT 8114
OUTPUT BIT 33
OUTPUT 81T 3
OUTPUT BIT34
OUTPUT 81T 2
I!iiTlITNliliIT
OUTPUT BIT 1
BRIGHTNESS CONTROL
DATA IN
20
CLOCK IN •
VOO
TOP VIEW
FIGURE 2a
40
39
38
31
36
35
34
33
32
10
11
31
MM5451
29
28
21
26
25
24
18
23
19
22
20
21
VOO
TOP VIEW
TLIF/S138-2
Order Number MM5450N or MM5451N
See NS Package N40A
7-32
30
FIGURE 2b
OUTPUT BIT 18
OUTPUT BIT 19
OUTPUT BIT 20
OUTPUT BIT 21
OUTPUT BIT 22
OUTPUT BIT 23
OUTPUT BIT 24
OUTPUT BIT25
OUTPUT BIT 26
OUTPUT BIT21
OUTPUT BIT 28
OUTPUT BIT 29
OUTPUT 81T 30
OUTPUT BIT 31
OUTPUT 81T 32
OUTPUT BIT 33
OUTPUT BIT 34
OUTPUT BIT 35
DATA IN
CLOCK IN
TL./FI6136·3
Absolute Maximum Ratings
Vol tage at Any Pi n
Operating Temperature
Storage Temperature
560 mW at +85°C
1W at +25°C
+150°C
Junction Temperature
300°C
Lead Temperature (Soldering, 10 seconds)
Power Dissipation
VSS to VSS+ 12V
-25°C to +85°C
-65°C to +150 o C
Electrical Characteristics TA within operating range, Voo =4.5V to 11.0V, Vss =OV unless otherwise specified.
Conditions
Pjlrameter
Min
Power Supply'
PO)Ner Supply Current
Input Voltages
Logical "0" Level (Vd
Logical "1" Level (V H )
± 10 I'A Input Bias
4.75", V oo '" 5.25
Voo> 5.25
Brightness Input Voltage (Pin 19)
VouT=3.0V
VOUT lV (Note 3)
Brightness Input 0 I'A
Brightness Input 100 I'A
Brightness Input 750 I'A
=
Input Current
Units
V
7
rnA
-0.3
2.2
Voo-2
0.8
Voo
Voo
V
V
V
0
0.75
rnA
10
15
10
25
I'A
rnA
I'A
rnA
rnA
4.3
V
±20
%
=
=
=
0
0
2.0
15
=750 I'A
3.0
2.7
Output Matching (Note 1)
Clock Input
Frequency, Ie
High Time, th
Low Time, tl
Max
11
Excluding Output Loads
Brightness Input (Note 2)
Output Sink Current
Segment OFF
Segment ON
Typ
4.75
4
(Notes 5 and 6)
500
kHz
950
950
ns
ns
Data Input
Set·Up Time, tos
Hole Time, tOH
300
300
ns
ns
Data Enable Input
Set·Up Time, tOES
100
ns
•
Note 1: Output matching is calculated as the percent variation {IMAX + IMIN)/2.
Note 2: With a fixed resistor on the brightness input pin, some variation in brightness will occur from one device to another. Maximum brightness input current can be 2 rnA as long as Note 3 and junction temperature equation are complied with.
Note 3:. See Figures 5, 6 and 7 for Recommended Operating Conditions and limits. Absolute maximum for each output should be limited to 40 rnA.
Note 4: The VOUT voltage should be regulated by the user. See Figures 6 and 7 for allowable VOUT vs lOUT operation.
Note 5: AC Input waveform specification for test purpose: t r s20 ns, tfs20 ns, f;:::: 500 kHz, 50% ± 10% duty cycle.
Note 6: Clock input rise and fall times must not exceed 300 ns.
Functional Description
Both the MM5450 and the MM5451 are specifically
designed to operate 4 or 5·digit alphanumeric displays
with minimal interface with the display and the data
source. Serial data transfer from the data source to the
display driver is accomplished with 2 signals, serial
data and clock. Using a format of a leading "1" fol·
lowed by the 35 data bits allows data transfer without
an additional load signal. The 35 data bits are latched
after the 36th bit is complete, thus providing non·
multiplexed, direct drive to the display. Outputs change
only if the. serial data bits differ from the previous
time. Display brightness is determined by control
of the output current for LED displays. A 0.001 capa·
citor should be connected to brightness control,' pin
19, to prevent possible oscillations.
A block diagram is shown in Figure 1. For the MM5450
a DATA ENABLE is used instead of the 35th output.
The DATA ENABLE input is a metal option for the
MM5450. The output current is typically 20 times
greater than the current into pin 19, which is set by
an external variable resistor. There is an internal limiting
resistor of 400n nominal value ..
Figure 4 shows the input data format. A start bit of
logical "1" precedes the 35 bits of data. At the 36th
clock a LOAD signal is generated synchronously with
the high state of the clock, which loads the 35 bits of
the shift registers into the latches. At the low state of
the clock a RESET signal is generated which clears all
7·33
Functional Description
(Continued)
For appl ications where a lesser number of outputs are
used, it is possible to either increase the current per
output, or operate the part at higher than 1 V VOUT.
The following equation can be used for calcuJations.
the shift registers for the. next set of data. The shift
registers are static master·slave configuration. There
is no clear for the master portion of the first shift
register, thus allowing continuous operation.
Tj = (VOUT) (lLED) (No. of segments) (124°CIW) + TA
There must be a complete set of 36 clocks or the shift
.
registers will not clear.
where:
Tj'= junction temperature +150°C max
When the chip first powers ON an internal power ON
reset signal is generated which resets all registers and al,l
latches. The START bit and the first clock return the
chip to its normal operation.
VOUT = the voltage at the LED driver outputs
ILED = the LED current
124°C/W = thermal coefficient of the package
TA = ambient temperature
Figure 2 shows the pin··out of the MM5450and MM5451.
Bit 1 is the first bit following the start bit and it will
appear on pin 1 B. A logical "1" at the input will turn
on the appropriate LED:
The above equation was used to plot Figure 5, Figure 6,
and Figure 7.
Figure 3 shows the tirning relationships between data,
clock and DATA ENABLE. A max clock frequency of
0.5 MHz is assumed.
1r-==!t--90%
--~~10%
DATA ENABLE
(MM5450)
TL/F/6136-4
FIGURE 3
CLOCK
r-l
~AD
(INTERNAL)---------""-----'
....._ -
r1
RESET
( I N T E R N A L ) - - - - - - - - - - - - - - -.., - - - - - '
'-TlIF1613f)..5
FIGURE.4. Input Data Format
7·34
Typical Applications
1.0
~
z
0
i=
~
2.5
0.0
06
-0
'"
ill
C
'"
~
't
2.0
'~
0.4
>
1\ J '\
1.5
"""
~
«'Q
(1
<[
.§
~"''''
""% "-'~
1.0
110
TA '05"&
Tj" 150"& (MAXI
~
B
...
...'"
~'"~I'-
'"
0
0.5
0.2
100
90
DO
70
60
50
40
30
20
10
-
--I
JOUT~1VHTA}05"C
VOUT·I.5V _
\
J.:
'\
:,
r-
II
VOUT = 2V
r-...'
--
f-
r-....
r- ::::- ....:
~
~
0
0
20
40
60
DO
12
100
16
20
24
28
10
ILED (mAl
TEMPERATURE ( &1
Tl.fF16136-6
15
20
30
34
TL/F/6136-a
TI..fF/6136·7
FIGURE 5
25
NUMBER OF SEGMENTS
FIGURE 6
FIGURE 7
RAW DC
>9V
lk
t.V
1
FIGURE 8. Typical Application of Constant
Current Brightness Control
5V
FIGURE 9. Brightness Control Varying the Duty Cycle
7·35
•
~
~
r-----------------------------------------------------------------------------------,
Typical Applications
::E
:IE
(Continued)
, Basic Electronically Tuned Radio System
~
LED DISPLAY
::E
::E
AM/5-:-1n
::JU
FMI
}-34--1
MM64611
DISPLAY
DRIVER
COPS
ELECTRONIC
TUNING
CONTROLLER
KEYBOARD
PLL
SYNTHESIZER
111
STATION
DETECT. ETC.
TUFJ8136-11
\
Duplexing 8 Digits with One MM5450
~,
CI
I~I
CI
I~I
CI CI
I~I I~I
1_1.1_1.1_1.1_1.1_1.1_1.1_1.1_1.
MM645D
CLOCK IN ~----.....
DATA IN ~-----..... ........M~~voo
BRIGHTNESS
CONTROL
TlIFre136-12
lOOk
TYP
7-36
~National
~ Semiconductor
MM5452, MM5453 Liquid Crystal Display Drivers
General Description
The MM5452 is a monolithic integrated circuit utilizing
CMOS metal gate, low threshold enhancement mode
devices. It is'available in a40·pin molded package. The chip
can drive up to 32 segments of LCD and can be paralleled to
increase this number. The chip is capable of driving a
4 1/2·digit 7·segment display with minimal interface be·
tween the display and the data source.
The MM5452 stores the display data in latches after it is
clocked in, and holds the data until new display data is
received.
• DATA ENABLE (MM5452)
• Wide power supply operation
• TTL compatibility
• 32 or 33 outputs
• Alphanumeric and bar graph capability
• Cascaded operation capability
Applications
• cOPS™ or microprocessor displays
• Industrial control indicator
Features
• Digital clock, thermometer, counter, voltmeter
• Serial data input
• Instrumentation readouts
• No load signal required
• Remote displays
Block and Connection Diagrams
oATOAU~~~~~~ l~~~!~~\
.....- - - - - - ' - i i - - - - - - - ,
s~~~~ .....-----..::..ji----'----f ~>-------_1:TI:~~~~~~
CLOCK .....- - - - - " " - l i - - - - - - - f
>---------..
'::"
FIGURE 1
Dual·ln·Line Package
vss
OUTPUT BIT 11
OUTPUT BIT 16
OUTPUT BIT 15
OUTPUT BIT 14
OUTPUT BIT 13
OUTPUTBIT 12
OUTPUT BIT 11
OUTPUT "BIT 10 I 9
OUTPUT BIT9 10
OUTPUT BIT B
OUTPUT BIT1
OUTPUT BIT6
OUTPUT BITS
OUTPUT BIT4
OUTPUT BIT 3
OUTPUT BIT 2
OUTPUT BIT 1
OSC IN
voo
11
MM5452
12
13
14
15
16
11
18
19
20
OUTPUT BIT lB
OUTPUT BIT 19
OUTPUT BIT 20
OUTPUT BIT 21
OUTPUT BIT 22
OUTPUT BIT 23
OUTPUTBIT24
OUTPUTBIT 25
OUTPUTBIT26
OUTPUTBIT 21
vss
OUTPUT BIT 11
OUTPUT BIT 16
OUTPUT BIT 15
OUTPUT BIT 14
OUTPUT BIT 13
OUTPUT BIT 12
OUTPUT BIT 11
OUTPUT BIT 10
OUTPUT BIT 9
OUTPUT BIT 8
OUTPUT BITl
OUTPUT BIT 6
OUTPUTBITS
OUTPUTBIT4
OUTPUTBIT 3
OUTPUT BIT2
OUTPUT BIT 1
OSC IN
voo
OUTPUT BIT 28
OUTPUT BIT 29
OUTPUT BIT,30
OUTPUTBIT 31
OUTPUT BIT 32
DATA ENABLE
BACKPLANE IN
BACKPLANE OUT
DATA IN
21
CLOCK IN
TOP VIEW
FIGURE 2a
MM5453
13
14
15
16
11
18
19
20
TLlF16137·2
Order Number MM5452D, MM5453D,
MM5452N or MM5453N
See NS Package D40C or N40A
7-37
TLIFI6137·'
Dual·ln·Line Package
TOP VIEW
FIGURE 2b
40
OUTPijT BIT 18
39 OUTPUT BIT 19
38
OUTPUT BIT20
OUTPUT BIT21
OUTPUT BIT22
OUTPUT BIT 23
OUTPUTBIT 24
OUTPUTBIT25
oUTPUTBIT26
31 OUTPUTBIT21
3D
OUTPUT BIT28
29
OUTPUTBIT29
28
OUTPUTBITJO
21
OUTPUTBIT 31
26
OUTPUT BIT 32
25
OUTPUT BIT 33
24 BACKPLANE IN
23 BACKPLANE OUT
22
DATA IN
21
CLOCK IN
TLIF16137·3
•
Absolute Maximum Ratings
Voltage at Any Pin
Power Dissipation
Vss to Vss + 10V
O·Cto + 70·C
Operating Temperature
Storage Temperature
300 mW at + 70·C
350 mW at +25·C
Junction Temperature
- 65· to + 150 ·C
+ 150·C
Lead Temperature (Soldering, 10 seconds)
300·C
Electrical Characteristics TA within operating range, Voo = 3.0V to 10V, Vss = OV; unless otherwise specified:
,-
Parameter
Conditions
Min
Power Supply
Power Supply CUrrent
3
Excluding Outputs
OSC = Vss , BP IN @ 32 Hz
Voo = 5V, Open Output.s, No Clock
Clock Frequency
Typ
Max
Units
10
V
40
10
J.lA
J.lA
500
kHz
0.1 Voo
0.8
V
V
Voo
Voo
V
V
Input Voltages
Logical '0' Level
Logical '1' Level
V oo <4.75
Voo~4.75
-0.3
-0.3
V oo >5.25
Voos5.25
0.8 Voo
2.0
Output Current Levels
Segments
Sink
V oo =3V, VouT =0.3V
Source
V oo =3V, VouT=Voo-0.3V
-20
20
J.lA
J.lA
Backplane
o
Sink
Vo =3V, V ouT =0.3V
Source
Voo = 3V, VOUT = Voo - 0.3V
-320
320
Output Offset Voltage
Segment Load 250 pF
Backplane Load 8750 pF (Note 1)
Clock Input
Frequency, f
(Notes 2 and 3)
c
J.lA
J.lA
±50
mV
500
kHz
High Time, th
950
ns
Low Time, tl
950
ns
Data Input
Set-Up Time, tos
Hold Time, tOH
300
300
ns
ns
Data Enable Input
Set-Up Time, tOEs
100
ns
Not. 1: This parameter is guaranteed (not 100% production tested) over operating temperature and supply voltage ranges. Not to be used In a.A. testing.
Not.2: AC Input waveform fortest purpose: t r ,,20 ns, tf,,20 ns, f =500 kHz, 50%:!: 10% duty cycle.
Not. 3: Clock Input rise and fall times must nol exceed 300 ns.
7-38
Functional Description
The MM5452 is specifically designed to operate 4 1/2-dlglt
7-segmentdisplayswith minimal interface with thedisplay
and the data source_ Serial data transfer from the data
source to the display driver is accomplished with 2 signals,
serial data and clock_ Since the M M5452 does not contain a
character generator, the formatting of the segment information must be done prior to inputting the data to the
MM5452_ Using a format of a leading "1" followed by the 32
data bits allows data transfer without an additional load
signal. The 32 data bits are latched after the 36th clock is
complete, thus providing non-multiplexed, direct drive to
the display_ Outputs change only iftheserial data bits differ
from the previous time_
Figure 4 shows the input data format A start bit of logical
"1" precedes the 32 bits of data At the 36th clock a LOAD
signal is generated synchronously with the high state of
the clock, which loads the 32 bits of the shift registers into
the latches. At the low state of the clocka RESET signal is
generated which clears all the shift registers for the next
set of data. The shift registers are static master-slave configuration. There is no clear for the master portion of the
first shift register, thus allowing continuous operation.
If the clock is not continuous, there must be a complete set
of 36 clocks otherwise the shift registers will not clear.
Figure 2a shows the pin-out of the MM5452. Bit 1 is the first
bit following the start bit and it will appear on pin 18.
A block diagram is shown in Figure 1. For the MM5452 a
DATA ENABLE is used instead of the 33rd output If the
DATA ENABLE signal is not required, the33rd output can be
brought out This is the MM5453 device.
Figure 3 shows the timing relationships between data,
clock and DATA ENABLE.
CLOCK
DATA
DATA ENABLE --------~I
(MM5452)
Tl/FI61J7·4
FIGURE 3
•
36
CLOCK
BIT 35
START BIT 1
DATA
BIT 36
---_B4WB_I.6.iW@$41
n
n
LOAD _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ..._ _ _ _ _ _ _ _ _ _...
(INTERNAL)
~
.._ _ _ _ __
(INTERNAL) _ _ _ _ _ _ _ _ _ _ _ _ _-.;,..., ..
, _ _ _ _ _ _ _ _ _ _ _ _..... L _ _ _ __
TLlFI61375
FIGURE 4_ Input Data Format
7-39
Figure 5 shows a typical application. Note how the input
data maps to the output pins and the display.The MM5452
and MM5453 do nol have format restrictions, as all outputs
are controllable. This application ..assumes a specific
display pinout. Different display/driver connection patterns will, of course, yield a different input data format.
Segmen 1 Identilicaiion
l-:-/b
".l2]0
d
I
BP
1
Fl
GT
I
AT
I
81
G2
F2
A2
82
G3
FJ A3
83 G4 F4 A4
I l-I l-I l-I l-I
I./~/./~/./~/./~I
1 OP El 01 ClOP E2 02 C2 OP E3 03 C3 OP E4· 04 C4 B4
~
L
-
r--
-
-
-
'--'---
"--.
-=-
Vss
18
17
19
16
20
~
21
~I~
24
14
13
12
11
25
10
26
27
9
MM5453
8
--
.-
1...-.....-
'-~-.---.-~
29
6
30
5
31
4
32
3
BACKPLANE OUT
2
BACKPLANE IN
-.
Lr
DATA FORMAT
TIME-lEFTniD
DECIMAL
T
T
33
1
.
28
7
DATA IN
CLOCK IN
l-
lnpul
FIGURE 9. Analog Display
7-42
~National
~ Semiconductor
MM5480 LED Display Driver
General Description
The MM5480 is a monolithic MOS integrated circuit utilizing N-channel metal gate low threshold, enhancement
mode and ion-implanted depletion mode devices_ It utilizes the MM5451 die packaged in a 28-pin package making it idllal for a 3V2 digit display_ A single pin controls the
LED display brightness by setting a reference current
through a variable resistor connected either to Voo or to a
separate supply of 11V maximum_
• Wide power supply operation
• TTL compatibility
• Alphanumeric capability
• 3 V. digit displays
Applications
• cOPS or microprocessor displays
• Industrial control indicator
Features
• Continuous brightness control
• Relay driver
• Digital clock, thermometer, counter, voltmeter
• Instrumentation readouts
• Serial data input
• No load signal required
Block Diagram
Voo
--::-=-::---.
OUTPUT 23
OUTPUT 1
BRIGHTNESS r-....
CONTROL
Figure 1
Connection Diagram
TL/F/6138-1
Dual-In-Llne Package
28
27
26
Vss
OUTPUT BIT 11
OUTPUT BIT 10
OUTPUT BIT 9
OUTPUT BIT B
OUTPUT BIT 7
OUTPUT BIT 6
OUTPUT BIT 5
OUTPUT BIT 4
OUTPUT BIT 3
OUTPUT BIT 2
OUTPUT BIT 1
BRIGHT. CONT.
Voo
TOP VIEW
Figure 2
7-43
OUTPUT BIT 12
OUTPUT BIT 13
OUTPUT BIT 14
OUTPUT BIT 15
OUTPUT BIT 16
OUTPUTBIT 17
OUTPUT BIT 18
OUTPUT BIT 19
OUTPUT BIT 20
OUTPUT BIT 21
OUTPUT BIT 22
OUTPUT 81123
DATA IN
CLOCK
TLlF/6138·2
Order Number MM5480N
See NS Package N28B
Absolute Maximum Ratings
Voltage at Any Pin
Storage Temperature
Power Dissipation
Vss to Vss + 12V
-65·Cto +150·C
490mWat'+85·C
940mWat +25·C
Electrical Characteristics
Symbol
Parameter
Voo
Power Supply
100
Power Supply Current
VIL
VIH
Input Voltages
Logical "0" Level
Logical "1" Level
IBR
10H
10L
TA = - 25·C to
Junction Temperature~
Lead Temperature (Soldering, 10 seconds)
+ 85·C, Voo = 4.75V to 11.0V, Vss = OV unless otherwise specified
Conditions
Min
VIBR
Brightness Input Voltage
(Pin 19)
OM
Output Matching (Note 1)
Typ
4.75
Excluding Output Loads
± 10 p.A Input Bias
4.75:sV oo :s5.25
V oo >5.25
Brightness Input Current
(Note 2)
Output Sink Current
(Note 3)
Segment OFF
Segment ON
+150·C
300·C
Max
Units
11
V-
7
mA
0.8
-0.3
2.2
Voo-2
Voo
Voo
V
V
V
0
0.75
mA
10.0
p.A
10.0
4.0
25.0
I'A
mA
mA
4.3
V
±20
%
Max
Units
500
kHz
I
VouT =3.0V
V ouT =1V
Brightness Input = 0 p.A
Brightness Input = 100 p.A
Brightness Input = 750 I'A
0
2.0
15.0
Input Current = 750 p.A
3.0
AC Electrical CharacteristicsTA =
-25·Cto
2.7
+ 85·C, Voo=5V±0.5V
Symbol
Parameter
Conditions
Min
fc
Clock Input Frequency
(Notes 5 and 6)
DC
th
High Time
950
ns
tl
Low Time
950
ns
tos
tOH
Data Input
Set-UpTime
Hold Time
300
300
ns
ns
Typ
Not. 1: Output matching is calculated as the percent variation from (IMAX + IMIN)12,
Nota 2: With a fixed resistor on the brightness Input pin some variation in brightness will occur from one device to another. Maximum brightness Input current
can be 2 rnA as long as Note 3 and junction temperature equation are complied with.
Not. 3: Absolute maximum for each output should be limited io 40 mAo
Not. 4: The VOUTvoltage should be reQulated by the user.
Note 5: AC Input waveform specification for test purpose: t r s20 "S, tfs20 ns, f =500 kHz, 50% ± 10% duty cycle.
Note 6: Clock Input rise and fall times must not exceed 300 ns ..
r
\.
7-44
Functional Description
The MM5480 Is specifically designed to operate 3Y2·digit
alphanumeric displays with minimal interface with the
display and the data source. Serial data transfer from the
data source to the display driver is accomplished with 2
signals, serial data and clock. Using a format of a leading
"1" followed by the 35 data bits allows data transfer with·
out an additional load signal. The 35 data bits are latched
after the 36th bit is complete, thus providing non·multi·
plexed, direct drive to the display. Outputs change only if
the serial data bits differ from the previous time. Display
brightness is determined by control of the output current
for LED displays. A 0.0011'F ceramic or mica disc capacitor should be connected to brightness control, pin 13, to
prevent pos~ible oscillations.
There must be a c'omplete set of 36 clocks or the shift
registers will not clear.
When the chip first powers ON an internal power ON'
reset signal is generated which resets all registers and
all latches. The START bit and the first clock return the
chip to its normal operation.
Figure 5 shows the Output Data Format for the 5480.
Because it uses only 23 of the possible 35 outputs, 12 of
the bits are 'Don't Cares'.
Figure 3 shows the timing relationships between data and
clock. A maximum clock frequency of 0.5 MHz is assumed.
A block diagram is shown in Figure 1. The output current
is typically 20 times greater than the current into pin 13,
which is set by an external variable resistor. There is an
internal limiting resistor of 400Q nominal value.
For applications where a lesser number of outputs are
used, it is possible to either increase the current per
output, or operate the part at higher than 1V VOUT. The
following equation can be used for calculations.
Figure 4 shows the input data format. A start bii of logi'
cal "1" precedes the 35 bits of data. At the 36th clock a
LOAD signal is generated synchronously with the high
state of the clock, which loads the 35 bits of the shift
registers into the latches. At the low state of the clock a
RESET signal is generated which clears all the shift registers for the next set of data. The shift registers are
static master·slave configuration. There is no clear for
the master portion of the first shift register, thus allow·
ing continuous operation.
Ti = (VOUT) (lLEO) (No. of segments) (132'C/W) + TA
where:
Ti =junction temperature + 150'C max.
VOUT = the voltage. at the LED driver outputs
ILEO = the LED current
132 'C/W = thermal coefficient of the package
TA = ambient temperature
'-=="""-90%
-----'=10%
DATA
TLlF/613B-3
Figure 3
36
lSUl...f1..
CLOCK
START
DATA
LOAD
(INTERNALI---------------,I-,
n
----.....I ...--_
RESET
r-1
(INTERNAL)---------------,-----.J
L..TUf16136-4
Figure 4. Input Data Format
TLIFI6138-5
Figure 5. Output Data Formal
7-45
••
!
Functional Description
(Continued)
::i
::i
RAW DC
>9V
lk
IlV
1
Figure 6. Typital Application of Constant Current Brightness Control
5V
, Figure 7. Brightness Control Varying the Duty Cycle
i
Basic 3 Y. ·Diglt Interface
Safe Operating Area
1.0 r----r~_r-~==:__"1
II
0.8 1---t~~~!5.
I -::J -::J
IL _I
0.4
01...---1.'=""""""''''''''''''''''''''''--'
o 20 40
60
80
100
TEMPERATURE ('CI
TlIF/6138-a
CLOCK·
7·46
DATA
TLIFI613B·9
~National
~ Semiconductor
MM5481 LED Display Driver
General Description
The 5481 Is a monolithic MaS integrated circuit utilizing
N-channel metal gate low threshold, enhancement mode
and ion-implanted depletion mode devices_ It utilizes
the MM5450 die packaged in a 20-pin package making it
ideal for a 2 digit display_ A single pin controls the LED
display brightness by setting a reference current through
a variable resistor connected either to Vee or to a separate supply of 11V maximum_
• Wide power supply operation
• TTL compatibility
• Alphanumeric capability
• 2 digit LED driver
Features
Applications
• Continuous brightness control
• COPS or microprocessor displays
• Serial data input
• No load signal required
• Industrial control indicator
• Relay driver
• Instrumentation readouts
• Data enable
Block and Connection Diagrams
OUTPUT 14
VDD
OUTPUT 1
BRIGHTNESS
CONTROL
SE:l~k--!.:.f--r>---1
L-;------.-....
CLOCK
--'+-1>-_.......
-::Figure 1
Dual-In-Line Package
OUTPUT BIT 8
OUTPUT BIT7
OUTPUT BIT 6
OUTPUT BIT 5
OUTPUT BIT 4
OUTPUTBIT3
OUTPUT BIT 2
OUTPUT BIT 1
MM54Bl
BRIGHT CONTR.
Voo
10
20
19
18
17
16
15
14
13
12
11
TLlF16139-1
OUTPUT BIT 9
OUTPUT BIT 10
OUTPUT BIT 11
OUTPUT BIT 12
OUTPUT BIT 13
Vss
OUTPUT BIT 14
DATA ENABLE
DATA IN
CLOCK
TOP VIEW
Figure 2
Order Number MM5481N
NS Package N20A
7-47
TUF16139-2
Absolute Maximum Ratings
Voltage at Any Pin
Storage Temperature
Power Dissipation
Vss to Vss + 12V
-65°Cto +150°C
450mWat +85°C
860mWat +25°C
Electrical Characteristics
Symbol
Power Supply
100
Power Supply Current
Vil
V IH
Input Voltages
Logical "0" Level
Logical "1" Level
Conditions
Min
'IOH
IOl
Output Sink Current
(Note 3)
Segment OFF
Segment ON
V IBR
Brightness Input Voltage
(Pin 19)
OM
Output Matching (Note 1)
4.75
± 10 p.A Input Bias
4.75:5 V 00:5 5.25
V oo >5.25
11
. 7
Units
V
mA
"':0.3
0.8
2.2
Vpo-2
Voo
Voo
V
V
V
0
0.75
mA
,
VOUT = 3.0V
VOUT= 1V (Note 4)
Brightness Input,= 0 p.A
Brightness Input = 100 p.A
B'rightness Input == 750 p.A
0
2.0
15.0
Input Current = 750 p.A
3.0
2.7
10.0
p.A
10.0
4.0
25.0
p.A
mA
mA
4.3
V
±20
%
Max
Units
500
kHz
- 25°C to + 85°C, VDO''' 5V ± 0.5V
Parameter
. Clock Input Frequency
fc
Max
,
AC Electrical Characteristics T A ~
Symbol
Typ
Excluding Output Loads
Brightness Input Current
(Note 2)
ISR
+150°C
300°C
TA = - 25°C to + 85°C, VOO = 4.75V to 11.0V, Vss = OV unless otherwise specified
Parameter
Voo
Junction Temperature
Lead Temperature (Soldering, 10 seconds)
Conditions
(Notes 5 and 6)
Min
Typ
DC
th
High Time
950
ns
tl
Low Time
950
ns
tos
tOH
Data Input
Set-Up Time'
Hold Time
300
300
ns
ns
Data Enable Input
Set-UpTime
100
ns
tOES
Note 1: Output matching is calculated as the percent variation from IMAX + IMIN/2.
NOle 2: With a fixed resistor on the brightness input pin some variation in brightness will occur from one device to another. Maximum brightness input current
oan be 2 rnA as long as Note 3 and j~nction temperature equation are complied with.
Note 3: Absolute maximum for each output should be limited to 40 mAo
Note 4: The VOUT voltage should be regulated by the user.
~ote
5: AC input waveform specification for test purpose: t(:5 20 os, tf:S 20 ns, f = 500 kHz, 50% ± 10% duty cycle.
Note 6: Clock input rise and fall times must not exceed 300 ns.
7-48
Functional Description
The MM5481 uses the MM5450 die which is packaged to
bperate 2·digit alphanumeric displays with minimal inter·
face to the display and the data source. Serial data
transfer from the data source to the display driver is ac·
complished with 2 signals, serial dllta and clock.·Using a
format of a leading "1" followed by the 35 data bits allows
data transfer without an additional load signal. The 35
data bits are latched after the 36th bit is complete, thus
providing non·multiplexed, direct drive to the display. Out·
puts change only i(the serial data bits differ from the
previous time. Display brightness is determined by control
of the output current for LED displays. A 0.0011'F capaci·
tor should be connected to brightness control, pin 9, to
prevent possible oscillations ..
There must be a complete set of 36 clocks or the shift
registers will not clear.
When the chip first powers ON an internal power ON
reset signal is generated which resets all registers and
all latches. The START bit and the first clock return the
chip to its normal operation.
Figure 5 shows the Output Data Format for the MM5481.
Because it uses only 14 of the possible 34 outputs, 20 of
the bits are 'Don't Cares'. Note that only alternate groups
of 4 outputs are used.
Figure 3 shows the timing relationships between data,
clock, and data enable. A maximum clock frequency of
0.5MHz is assumed.
A block diagram is shown in Figure 1. The output current
is typically 20 times greater than the current into pin 9,
which is set by an external variable resistor. There is an
internal limiting resistor of 400Q nominal value.
For applications where a lesser number of outputs are
used, it is possible to either increase the current per
. output, or operate the part at higher than 1V VOUT. The
following equation can be used for calculations.
Figure 4 shows the input data format. A start bit of logi·
cal "1" precedes the 35 bits of data. At the 36th clock a
LOAD signal is generated synchronously with the high
state of the clock, which loads the 35 bits of the shift
registers into the latches. At the low state of the clock a
RESET signal is generated which clears all the shift reg·
isters for the next set of data. The shift registers are
static master·slave configuration. There is no clear for
the master portion of the first shift register, thus allow·
ing continuous operation ..
Tj = (VOUT) (ILEO) (No. of segments) (145 'C/W) + TA
where:
T] = junction temperature + 150'C max.
VOUT = the voltage at the LED driver outputs
ILEO =the LED current
145'C/W thermal coefficient of the package
TA = ambient temperature
=
r-==!\--90%
......_---'... ---~=10%
DATA
DATA ENABLE - - - - ' \ .
Figure 3. Timing
.
36
1..JL.rUL..
CLOCK
START
DATA
\
LOAD
(INTERNAL)
n
-------------------~------- '-~-
1-IL
RESET _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
. (INTERNAL)
TLlFt6139·4
Figure 4. Input Data Format.
Figure 5. Output Data Format
7·49
TLIF/6139·5
!=e
Functional Description (Continued)
=e
RAW DC
>9V
1k
2400
I:l.V
l~
PIN 9
5V
20
MM5481
TL/Ff6139-6
Figure 6. "TYpical Application of Constant Current Brightness Control
5V
10
MM74HC123
j
10",
L
Q
9
MM5481
15
-=
TUFt6139-7
Figure 7. Brightness Control Varying the Duty Cycle .
Safe Operating Area
Basic Electronically Tuned Television System
1.0
!:
z
0.8
;:::
0.6
illco
0.4
..
LEO DISPLAY
CI
...
0:.
w
iI:
...
CI
0.2
0
0
20
40
60
30
100
TEMPERATURE tOe)
TUF/6139-9
TL/Ff6139-8
7-50
~National
~ Semiconductor
MM5~3
Liquid Crystal Display Driver
General Description
The MM5483 is a monolithic integrated circuit utilizing
CMOS metal-gate low-threshold enhancement mode
devices. It is available in a 40-pin molded package. The
chip can drive up to 31 segments of LCD and can be cascaded to increase this number. This chip is capable of
driving a 4Y2-digit 7-segment display with minimal interface between the display and the data source.
• Wide power supply operation
The MM5483 stores the display data in latches after it is
latched in, and holds the data until another load pulse is
received.
Applications
• TTL compatibility
• 31 segment outputs
• Alphanumeric and bar graph capability
• Cascade capability
• COPSTM or microprocessor displays
• Industrial control indicator
• Digital clock, thermometer, counter, voltmeter
Features
• Instrumentation readouts
• Serial data input
• Remote displays
• Serial data output
Block and Connection Diagrams
VDD """"1P---.,
LOAD -';~:j-----I>----C:~~~!::~
SERIAL
DATA --2!r-----[>---{j~~~§~a
CLOCK
DATA OUT
.-......=.+----D-------'
TLlFf6140·'
Figure 1
Dual-in·Llne Package
40
39
3B
37
36
Vss
OUTPUT BIT 16
OUTPUT BIT 15
OUTPUT BIT 14
OUTPUT BIT 13
OUTPUT BIT 12
OUTPUT BIT 11
OUTPUT BIT 10
OUTPUT BIT 9
OUTPUT BIT B
OUTPUT BIT 7
OUTPUT BIT 6
OUTPUT BIT 5
OUTPUT BIT 4
OUTPUT BIT 3
OUTPUT BIT 2
OUTPUT BIT 1
DATA OUT
OSC IN
VoD
'.
10
11
12
13
14
15
16
17
18
19
20
MM5483
24
23
22
21
TOP VIEW
Figure 2
7-51
OUTPUT BIT 17
OUTPUT BIT 18
OUTPUT 81T 19
OUTPUT BIT 20
OUTPUT BIT 21
OUTPUT BIT 22
OUTPUT BIT 23
OUTPUT BIT 24
OUTPUT BIT 25
OUTPUT BIT 26
OUTPUT BIT 27
OUTPUT BIT 28
OUTPUT 81T 29
OUTPUT 81T 30
OUTPUT BIT 31
LOAD
BACKPLANE IN
8ACKPLANE OUT
DATA IN
CLOCK IN
TLIF16140-2
Order Number MM5483N
. See NS Package N40A
•
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Power DIssipation
300mWat +85·C
350mWat +25·C
Junction Temperature
+150·C
Lead Temperature (Soldering, 10 seconds)
300·C
Vss to Vss +10V
-40·C to +85·C
-65·Cto +150·C
DC Electrical Characteristics
TA within operating range, Voo=3.0V to 10V, Vss=OV, unless
otherwise specified.
Parameter
Min
Conditions
Max
Units
10
V
9
17
35
15
25
45
,..A
,..A
,..A
1.5
2.5
,..A
0.9
Typ.
3.0
.Power Supply
Power Supply Current
R=1M, C=470pF,
Outputs Open
Voo =3.0V
Voo =5.0V
Voo=10.0V
OSC·=OV, Outputs Open,
BPIN=32Hz, Voo=3.0V
Input Voltage Levels
Logic "0"
logic "1"
Logic "0"
Logic "1"
Load, Clock, Data
Voo= 5.0V
Voo= 5.0V
Voo= 3.0V
Voo= 3.0V
2.4
2.0
V
V
V
V
Segments and Data Out
Sink
Source
Voo = 3.0V, VouT=0.3V
Voo = 3.0 V, VOUT=2.7V
20
20
,..A
,..A
BPOUT
Sink
Source
Voo=3.0V, VOUT= 0.3V
Voo=3.0V, VOUT=2.7V
320
320
,..A
,..A
0.4
Output Current Levels
AC Electrical Characteristics Voo ",4.7V, v~s = OV unless otherwise specified.
Symbol
Parameter
Min
fc
Clock Frequency, Voo=3V
tCH
Clock Period High
tCL
Clock Period Low
I
I
(Notes 1,2) .
Typ
Max
Units
500
kHz
500
ns
500
ns
300
ns
tos
Data Set-Up Before Clock
tOH .
Data Hold Time After Clock
100
ns
tLW
Minimum Load Pulse Width
500
ns
tLTC
Load to Clock
400
tcoo
Clock to Data Valid
ns
400
750
ns
Note': AC Inpul waveform specification for lesl pu,pose: 1,,,20 n8.lf,,20 ns. f = 500 kHz. 50%., 10% duly cycle.
Note 2: Clock Input ,I.e and fall limes musl nol exceed 300 ns.
Note 3: Oulpul offsel vollage is %50 mV wllh CSEGMENT=250 pF, CBP = 8750 pF.
Functional Description
A block diagram for the MM5463 is shown in Figure 1
and a package pinout 15 shown in Figure 2. Figure 3
shows a possible 3-wire connection system with a typical signal fomat for Figure 3. Shown in Figure 4, the load
input Is an asynchronous Input and lets data through from
the shift register to the output buffers any time It is high.
The load Input can be connected to Voo for 2-wlre control as shown In Figure 5, In the 2-wlre control. mode, 31
bits (or less depending on the number of segments
used) of data are clocked into the MM5483 in a short
time frame.(with less than 0.1 second there probably will
be no noticeable flicker) with no more clocks until new
information Is to be displayed. If data was slowly
clocked in, it can be seen to "walk" across the display
In the 2-wire mode. An AC timing diagram can be seen In
Figure 6. It should be noted that data out is not a TTL- .
compatible output.
..
7-52
1M
LOAD
DATA
---1-----.. . . --- ---
CLOCK - - - -....
LOAD
--_
TLlF16140·3
Figure 3. Three·Wire Control Mode
~;-L.JLn.rL
CLOCK
I~:~~ I
LOAD
BIT 1
I
BIT 2
I
I
I
__________________
I
g
I
BIT 3D
I
I
BIT 31
I
n L-
~(,I~--------~I
T1ME-
TlIF1614D·4
Figure 4. Data Format Diagram
LCD DISPLAY
1M
19
DATA OUT
LOAD
21
..
25
VDD
DATA
CLOCK - - - - - - - - - - - - - - - - - - - - - -
Figure 5. Two-Wire Control Mode
TLlF/6140·5
I-ICH-I-ICL-I
CLOCK
-I
I-IDs· 1
-I
I-IDH
DATA~
,
LOAD
I - I L W - I -ILTC
1 \"'______
1..JX.-------..X'-_____
-IICDD
D~~~ _ _ _
Figure 6. Timing Diagram
7-53
TlIF161406
II)
,
~NaHonal
~ ~ Semiconductor
!
! MM5484, MM5485 16-,11-Segment LED Display Drivers
~
General Description
The MM5484, MM5485 are low threshold N-channel
metal gate circuits using low threshold enhancement
and Ion Implanted depletion devices. the MM5484 Is
available in a 22-pln molded'package and Is capable of
driving 16 LED segments while the MM5485 Is available
In a 16-pin molded package and Is capable of driving 11
LED segment outputs.
• TTL compatibility
• No load signal required
• Non multiplex display
• 2'i. digit capabllity-MM5484
1'1. digit capabllity-MM5485 .
Applications
Features
• COPSTM or microprocessor displays
• Serial data input
• Wide power supply operation
• 16 or 11 outputs, 15mA sink capability
• Instrumentation readouts
• Industrial control Indicator
• Relay driver
• MM5484 Is cascadeable
Block and Connection Diagrams
16 SEGMENT OUTPUTS
11 SEGMENT OUTPUTS
ENABLE 0-_----1
ENABLE 0-..,...----1
DATA
OUT
CLOCK
CLOCK_-"'L..._
DATA IN 0---------1
DATA IN
TliF/6141·1
Figure 1. MM5484
TUF/6141·2
Figure 2. MM5485
Dual-In-Line Package
Dual·ln·Line Package
013
22
012
014
21
011
05
04
015
20
010
06
03
016
19
09
07
02
DATA OUT
18
ENABLE
Voo
17
CLOCK IN
OATAIN
16
Vss
01
15
08
08
02
14
07
09
03
13
06
04
12
05
\
Vss
CLOCK IN
4 MM5485 13
12
5
ENABLE'
11
10
Voo
011
010
TOP VIEW
TOP VIEW
01
DATA IN
TUF/6141~
TLIF/6141·3
Order Number MM5485N
See NS Package N16E
Order Number MM5484N
See NS Package·N16E
7-54
Absolute Maximum Ratings
Voltage at LED outputs
Voltage at other pins
Operating Temperature
Storage Temperature
Maximum Power Dissipation
MM5484
MM5485
Lead Temperature (Soldering, 10 seconds)
Vss -0.5VtoVss+12V
Vss -0.5VtoVss+l0V
-40·Ct085·C
-40·C to 150·C
DC Electrical Characteristics
Voo = 4.5 to 9V, TA = -40·C to 85·C unless otherwise specified
Conditions
Parameter
Min
Supply Voltage
Supply Current
Typ
Max
Units
5
9
10
V
mA
2.4
Voo+0.5
V
0
0.8
±1
7.5
,.A
4.5
Logic One
Input High Level VIH
Logic Zero
Input Low Level VIL
Input Current
Input Capacitance
500mW
400mW
300·C
High or Low Level
V
pF
Outputs
Data Output Voltage
High Level VOH
Low Level VOL
Segment Off (logic zero on
Input)
(Only for MM5484)
10ur=0.lmA
lour = -O.lmA
Vour=12V
REXT =400Q
Voo-0.5
V
V
0.5
50
,.A
1.0
V
,
Output Current
Segment On (logic one on
input)
Output Voltage
0.5
lour = 15mA
Voo~6V
AC Electrical Characteristics
Symbol
Parameter
(See Figure 3.) Voo = 4.5 to 9V, TA = -40·C to 85·C unless otherwise specified
Conditions
Min
Typ
Max
Units
0.5
MHz
fc
Clock Frequency
th
High Time
0.95
tl
Low Time
0.95
p.5
tS1
Data Setup Time
0.5
p's
tH1
Data Hold Time
0.5
p's
tS2
Enable'Setup Time
0.5
p's
tH2
Enable Hold Time
0.5
p's
tpd
Data Ou~ Delay
p's
0.5
p's
Note 1: Under no condition should the power dissipated by the segment driver exceed 50mW nor the entire chip power dissipation
exceed 500mW for the MM5484 and 400mW for the MM5485.
Note 2: AC input waveform specification for test purpose: t r s20 ns, tfs20 ns, f = 500 kHz, 50% ± 10% duty cycle.
Note 3: Clock input rise and fall times must not exceed 500 ns.
7-55
•
Functional Description
TheMM5484 and MM5485 are designed to drive LED displays directly. Serial data transfer from the data source
to the display driver Is accomplished with 3 sig'nals,
DATA IN, CLOCK and ENABLE. The signal ENABLE acts
as an envelope and only while this signal Is at a logic '1'
do"the circuits recognize the clock signal.
For the MM5484, data is output from the serial DATA
OUT pin on the falling edge of clock so cascading is
made simple with race hazards eliminated.
The MM5485 Is essentially a metal mask option of the
MM5484 where only 11 segments are used. However, the
MM5485 contains a 12-bit shift register and so when
entering new data to this device 12 clock pulses should
be Input with the data in a 'don't care' state for the 12th
clock pulse. See Figure 2.
When the chip first powers on, an internal power on
reset Signal is generated which resets the SR and
latches to zero so that the display will be off.
While ENABLE is high, data on the serial data input Is
transferred and" shifted in the internal shift register on
the rising clock edge, i.e. a logic '.0' to I?gic '1' transition.
When the ENABLE signal goes to a low (I?glc zero state),
the contents of the shift register is latched and the display will show the new data. While new data is being
loaded Into the SR the display will continue to show the
old data.
Timing Diagram
.
CLOCK
"
ENABLE - - - - - -
DATA IN _ _ _ _ _J
-l
I;:tPd
1 -------,\. .______
DATA o u T - - -_ _ _ _ _ _ _ _ _......
TLIF16141·5
Figure 3
7-56
~National
~ Semiconductor
MM5486 LED Display Driver
General· Description
The MM5486 Is a monolithic MOS integrated circuit
utilizing N-channel metal-gate low-threshold, enhancement mode and ion-implanted depletion mode devices.
It is available In a 40-pin molded dual-in-line package.
A Single pin controls the LED display brightness by setting a reference current through a variable resistor connected to Vee.
• Wide power supply operation
• TTL compatibility
• 33 outputs, 15mA sink capability
• Alphanumeric capability
Applications
• COPSTM or microprocessor displays
Features
• Industrial control indicator
• Continuous brightness control
• Relay driver
• Digital clock, thermometer, counter, voltmeter
• Serial data input/output
• ~xternal load input
• Cascaded operation capability'
• Instrumentation readouts
• Reference MOS Brief #1
Block and Connection Diagrams
":"
•
TLlF16142·1
Figure 1
VSS
OUTPUT BIT 16
OUTPUT BIT 15
OUTPUT BIT 14
OUTPUT BIT 13
OUTPUT BIT 12
OUTPUT BIT II
OUTPUT BIT 10
OUTPUT BIT 9
OUTPUT BIT 8
OUTPUT BIT 7
OUTPUT BIT 6
OUTPUT BIT 5
OUTPUT BIT 4
OUTPUT BIT 3
OUTPUT BIT 2
OUTPUT BIT 1
DATA OUT
BRIGHTNESS CONTROL
Voo
40
39
3B
37
36
35
34
33
32
10
MM5486
11
12
13
14
15
16
17
18 _
19
20
TOP VIEW
Figure 2
7-57
31
30
29
28
27
26
25
24
23
22
21
OUTPUT BIT 17
OUTPUT BIT 18
OUTPUT BIT 19
OUTPUT BIT 20
OUTPUT BIT 21
OUTPUT BIT 22
OUTPUT BIT 23
OUTPUT BIT 24
OUTPUT BIT 25
OUTPUT BIT 26
OUTPUT BIT 27
OUTPUT BIT 28
OUTPUT BIT 29
OUTPUT BIT 30
OUTPUT BIT 31
OUTPUT BIT 32
OUTPUT BIT 33
LOAD
DATA IN
CLOCK IN
TlIFI6142·2
Order Number MM5486N
See Package N40A
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Jemperature
Power Dissipation
Junction Temperature
Lead Temperature (Soldering, 10 seconds)
Vss to Vss+12V
-25·C to +85·C
-65·C to +150·C
560mWat +85·C
1Wat +25·C
Electrical Characteristics
+150·C
300·C
TA within operating range, Voo=4.75V to 11.0V, Vss=OV,
unless otherwise specified.
Symbol
Parameter
Voo
Power Supply
100
Power Supply Current
V,l
Input Voltages
Logic "0" Level
Logic "1" Level
V'H
IBR
Brightness input (Note 2)
10H
10l
Output Sink Current (Note 3)
Segment OFF
Segment ON
10
Maximum Segment Current
V,BR
Brightness Input Voltage (Pin 19)
OM
Output Matching (Note 1)
VOL
VOH
Data Output
Logical "0" Level
Logical "1" Level
fc
th
t,
Clock Input
Frequency
High Time
Low Time
tos
tOH
tOEs
Conditions
Min
Typ
Units
11
V
7
mA
-0.3
2.2
Voo-2
0.8
Voo
Voo
V
V
V
0
0.75
4.75
Excluding Output Loads
± 10 p.A Input Bias
4.75$V oo $5.25
Voo> 5.25
Max
VouT =3.0V
VOUT = lV (Note 4)
Brightness Input = 0 p.A
Brightness Input = 100 p.A
Brightness Input = 750 p.A
0
2.0
15
Input Current = 750 p.A
3.0
2.7
.
mA
10
p.A
10
4
25
p.A
mA
mA
40
mA
4.3
V
±20
%
0.4
Voo
V
V
500
950
950
kHz
ns
ns
Data Input
Set·Up Time
Hold Time
300
300
ns
ns
Data Enable Input
Set·Up Time
100
ns
IOUT=0.5 mA
IOUT= 100 p.A
Vss
2.4
(Notes 5 and 6)
Note 1: Output matching Is calculated as the percent variation (IMAX + IMIN)12.
Note 2: With a fixed' resistor on the brightness input pin, some variation In brightness will occur from one device to another. Maximum brightness Input cur·
rent can be 2 mA as long as Note 3 and junction temperature equation are complied with.
Note 3: Absolute maximum for each output should be limited to 40 mAo
Note 4: The VOUT voltage should be regulated by the user. See Figures 6 and 7for allowable. VOUT vs lOUT operation.
Note 5: AC Input waveform specification for test purpose: tr s20 ns, tfs20 ns, f = 500 kHz, 50% ± 10% duty cycle.
Note 6: Clock Input rise and fall tlmes'must not exceed 300 ns.
,
7·58
i:
i:
Functional Description
The MM5486 Is specifically designed to operate fourdigit· alphanumeric displays with minimal Interface with
the display and the data source. Serial data transfer
from the data source to the display driver Is accomplished with 3 signals, serial data, clock, and load. The
33 data bits are latched by a positive-level load signal, thus
providing non-multiplexed, direct drive to the display.
When load is high, the data in the shift registers is displayed on the output drivers. Outputs change only if the
serial data bits differ from the previous time. Display
brightness Is determined by control of the output current
for LED displays. A 0.001 I'F capacitor should be connected to brightness control, pin 19, to prevent possible
oscillations. The output current is typically 20 times
greater than the current into pin 19, which is set by.an external variable resistor. There is an Internal limiting
resistor of 40011 nominal vallie.
When the chip first powers ON, an internal power ON
reset signal is generated which resets all registers and
latches. The leading clock returns the chip to its normal
operation.
Figure 3 shows the timing relationship betweeri data,
clock and data enable. A maximum clock frequency of
0.5MHz Is assumed.
For applications where a lesser number of outputs are
used, it is possible to either increase the current per
output, or operate the part at higher than 1 V VOUT ' The
following equation can be used for calculations:
TJ = (VOUT) (ILEO) (No. of segments) (124 ·C/W) + TA
where:
TJ = junction temperature
+ 150·C max.
VOUT = the voltage at the LED driver outputs
A block diagram is shown in Figure 1.
ILEO = the LED current
Figure 4 shows the input data format. Bit "1" is the first
bit into the data input pin and It will appear on pin 17. A
logical "1" at the input will turn on the appropriate LED.
The load signal latches the 33 bits of the shift registers
into the latches. The data out pin allows for cascading
the shift registers for more than 33 output drivers.
124·C/W = thermal coefficient of the package
TA = ambient temperature
The above equation was used to plot Figure 6, Figure 7,
and Figure 8.
Vl=-___
~
tdhbtf
CLOCK VH
DATA
i
~~
_ _ _--J
-
Itr
90%
10%
\
-
90%
..... 10%
f'---I------YlYH
Ids
TUF16142-3
Figure 3
LEADING
CLOCK' 1
CLOCK
BIT 1
LOAD
I
BIT 32
BIT 33
~~~
RESETj1
(INTERNAL}
....._ _ _ _ _ _ _ _ _ _ _ _ _- - - - - - - - _
TL./FI6142-4
"This leading clock Is necessary only after power ON.
Figure 4. Input Data Format
YOD
CLOCK
--...I
RESET _ _ _ _ _ _ _.J
(INTERNAL}
TUF/6142-5
Figure 5
7-59
II
! Typical Applications
:&
:&
1.0
.---.----.r---,----,.--.,
2.5
.~ ~8~-+~~-;5~~~roM~'r~
\'
2.0
~~~~ ~~JJ
z
S!
f
i:
!;
.. 0.41---+~
I
~
0.2
o
20
~
~
r-
o
o
40
.t
...
1.0
0.5
o
110
j
TA - B5°C
100' j - - --, VOUTjl.0V
90
:< BO
~
70 j - - r - Vou+=dv
I
I
.,.,ffi 60 r--VoUT=2V
:>
50
M~X lOUT = 40 mA
~~
40
'\
3D
:>
r-...; r--.
'" 20
10
...
[\
-~~~ ~~Q~
r"r-:
~. ~~
,,~
~ 1.5
0.6
11
.!.J
TA=B5°C
Tj=150°C (MAX.)
12
TEMPERATURE (OC)
16
20
24
28
o
ILED (mA)
TUF/61 .. 2-6
0'
5
10
15
r-.
20
TUF/S142-7
Figure 6
30
34
TUF16142-8
Figure 7
Figure 8
RAW DC
>9V
lk
AV
1
Figure 9. Constant Current Brightness Control
5V
Figure 10. Brightness Control Varying the Duty Cycle
7-60
25
NUMBER OF SEGMENTS
Typical Applications (Continued)
Basic Electronically Tuned Radio System
LED DISPLAY
AM
Ie -11-1
FMI CI::I LI
""M"
I=L-----r--r-r-----'
STATION
DETECT. ETC.
PLL
SYNTHESIZER
TUFI6142·'1
Duplexing 8 Digits with One MM5486
l~lllllllllllill
I~./~./~/./~./~/./~/./~/.IZI.
••
MM5486
CLOCK IN ....- - - -....
DATA IN ....- - - - - . . . L-'\j~~""'VOO
BRIGHTNESS
CONTROL
TLIF/6142·12
LOAD ....- - - - - - - - - - . . . . , . - -.....
"This driver has 7 segments only.
7-61
;
~National
~ ~ Semiconductor
MM54240 Asynchronous Receiver/Transmitter.
Remote Controller
General Description
The MM54240 is a monolithic MOS integrated circuit utilizing N-channellow-threshold, enhancement mode and ionimplanted depletion mode devices. The circuit is designed
for processor-type remote control appl ications. The data
transmission consists.of a pulse·width modulated serial
data stream of 18 bits. This stream consists of 7 address
bits, 1 command bit, 8 data bits, 1 parity bit and 1 dummy
bit in that order.
The MM54240 can be operated in two modes; namely
"master" and "slave". The master interfaces to a processor bus, and is capable of polling and controlling 128
slave circuits. The slave circuits are interfaced to remote
data sources and/or data destinations.
Applica~ions
The MM54240 finds application in transmitting data to
and receiving data from remote A-OlD-A, remote micro-
processor units, remote digital transducer or remote data
peripheral devices.
Features
• Supply voltage range - 4.75V to 11.5V single supply
• Low quiescent current - 5.0 mA maximum
J
• On-chip oscillator based on inexpensive R:C
components
• Pulse width modulation techniques minimize error and
'
maximize frequency tolerance
• Mode input for either master or slave operations
• Chip select (CS) input in the master mode
• Selectable output port options in the slave mode
• Transmit/receive control output (CS) in the slave mode
Functional Block, Diagram
DATA PORTS
00-01
Pin Conflgurallon
vss
07 (MSB)
3
06
05
6
04
03
7
02
01
DO (LSB)
10
+--C)VDD
~VSS
fS
MODE
TUF/6144-1
Order Number MM54240N
See NS Package N24C
7-62
Serial
11
Mode
12
13
CS
14
A/C1
15
W/C2
16
S
17
esc
18
A6(MSB)
19
A5
20
A4
21
A3
22
A2
23
A1'
AO(LSB)
24
vOO
Absolute Maximum Ratings (exceeding these ratings
could result in permanent damage to the device)
Voltage on Any Pi n
with Respect to Vss
Operating Temperature
-0.5Vto +12.0V
Storage Temperature
-65'Cto +150'C
Lead Temperature (Soldering, 10 seconds)
300'C
- 40'C to + 85'C
Electrical Characteristics TA within operating range, Vss=OV
Symbol
Parameter
Conditions
Typ
Min
Voo
Supply Voltage
100
Supply Current, Quiescent
Voo =4.75V to 11.5V
VIL
VIH
V IH
Input Voltage
Logic "0"
Logic "1"
Logic "1"
V oo =4.75V to 11.5V
Voo = 4.75V to 5.25V
Voo = 5.25V to 11.5V
0
2.4
V o o-2.85
10L
10H
10H
IOH
105
Output Current (00-07)
VOL=0.4V
VOH=2.4V
.VoH=0.5 Voo
VOH = 0.6 Voo(Weak V OH )
Short Circuit Output Current
V oo =4.75V to 11.5V
Voo=4.75V to 5.25V
Voo= 5.25V to 11.5V
Voo =4.75V to 11.5V
V oo =4.75V to 5.25V
2.0
200
200
0.5
IOL
Output (CS Slave)
VoL =0.5V
Voo = 4.75V to 11.5V
0.4
F
F
Frequency RC Input
For a Fixed (RCh (Note 1)
For a Fixed (RC)2 (Note 1)
V oo =4.75V to 7.0V
Voo=7.0V to 11.5V
200
200
10L
ILEAK
Output Current (Serial)
V OL =O.4V
Open-Drain Leakage'
Voo = 4.75V to 11.5V
V oo =4.75V to 11.5V
2.0
IlL
Internal Input Pull-Up Resistors; CS, MO,de
VIN=VSs
V oo =4.75V to 11.5V
15
\
4.75
Max
Units
11.5'
V
5.0
mA
0.8
V
V
V
Voo
Voo
30
5
mA
p.A
p.A
p.A
mA
mA
400
400
600
600
kHz
kHz
10
mA
p.A
100
p.A
Nolel: (RC)1 or (RC)2: suggested R1 kO-10 kll, suggested C 50 pFd-500 pFd.
II
Typical Application
CONTROL
LOGIC
l
IIlI
WAIT
r....
ADDRESS 7
1"-
CS
!!
S RIC!
~
A..
v+
I
~
r--
~
r
MASTER
MM54240
PROCESSOR
.
r-+-
.~
A
DATA 8 /
'I
SLAVE",
MM54Z40
Wli
r
'-WlC2
SLAVE #128
MM54240
1rl+
~
£-=
~
~
PERIPHERAL
I
l'
ADDRESS
STRAPPED
J...
-y
PERIPHERAL
I
T
~
DSC
v+
p:
v+
Tl.1F/6144·2
7-63
Circuit Description
The MM54240 consists of four major logic blocks: Sequential pontrol, Shift Register, PWM Encoder and PWM
Decoder.
receiving a transmission. The slave that is addressed will
keep CS high until it completes the transmission to the
master.
Data Ports (00-07): The data ports are bidirectional and
have three output levels (high, low and weak pull-up). The
weak pull-up mode is only available when the MM54240 is
a slave device. For the master circuit, the outputs are con·
figured with standard high and low states coincident with
properly enabled CS and R. This permits direct interface or
buffered interface with the standard bus structure of a
processor system. The first three data ports (~O, 01, 02)
also serve as status pins coincident with enabled CS and
S'* For the slave circuit, specialized input and output op·
tions are available by selecting the C1 and C2 inputs. The
data port can "still be read even if it is configured as an output port.
'
Read/Control 1 (R/C1): In the master mode, while CS is
active low, this input can be used to initiate either of the
following three operations depending upon the present
status of the circuit.
Address Ports (AO-A6): The address ports are for the
input of address information into the MM54240. For the
master circuit, the input must be valid during the R andW
command strobes. For the slave circuit, a unique hardwired code must be on the address ports. This code is the
address of the slave circuit for addressing purposes. No
internal pull·ups are provided.
1. To initiate a read command
2. To enable output ports if transmission received is
valid
3. To terminate read command if transmission received
is incorrect (if master is in state4 awaiting data from
slave, a dummy read will set master to initialize)
In the slave mode, this input, together with W/C2, selects
the specialized output port configuration.
'
Write/Control 2 (W/C2): In the master mode, while CS is
active low, this input can be used to initiate a write command. In the slave mode, this input, together with RlC1,
selects the specialized output port confipuration.
Status (S): In the master mode, while CS is active low, this
input enables circuit status information to be output at the
first three data ports. The other five data ports will be at
logic "0". In the slave mode, this input sets all the output
(00-07) latches to the logic "1" state. In the slave mode,
status cannot be interrogated.
Mode: This input is low for slave and high (or open) for
master selections. An internal pull-up resistor is provided.
Chip Select (CS): This pin has an internal pull·up resistor
to Voo. In the master mode, CS is an irJput and has to be
,pulled low before the R, Vii, or S strobes can be acknowl·
·edged. When CS is a logic high, the data port pins are high
impedance. In the slave mode, CS is an output. It is a logic
"0" when the circuit is expecting to receive a transmission. CS is intended only for controlling a transceiver buffer device. During the receive mode, CS will produce a
high-going pulse when the dummy bit is received, but prior
to the internal address compare. Thus, all slaves (addressed or not addressed) will produce this pulse when
asc:
This input is for connection to a resistor-capacitor
circuit for the on-chip oscillator. Frequency tolerance is'
specified for two voltage ranges. In a master-slave
system, if no one circuit has a frequency more than a factor of 2 different from any other circuit, then, valid
transmission is guaranteed. Nominal setting is 400 kl:Jz.
Serial: Input and output pin for serial transmission. Output has open-drain configuration.
"The other data ports will output'logi9 "0".
Data Format
1. Serially transmitted data
'1 ADDRESS BITS
TLIF16144·3
2. Pulse width modulation coding
LOGIC "0"
LOGIC "1"
TUF/6144·4
A bit is equivalent to 96 clocks of the R-C oscillator frequency i.e.; when R-C frequency
1 word = 4.32 ms.
7-64
=400 kHz, 1 bit =240 ",5,
Circuit Description (Continued)
Slave Circuit Logic Flow Diagram
TLlFf6144-5
SPECIALIZED OUTPUT OPTIONS FOR SLAVE CIRCUITS
C1
C2
1
0
0
1
1
0
1
0
Description
AI1'8 pins are high impedance input ports
All 8 pins are standard low impedance output ports
01-04 are standard low impedance output ports
05-08 are high impedance input ports
- Logic "0" outputs are low impedance output ports
Logic "1" outputs are weak pull-ups to VDD
* In this option, the slave data ports can be connected in a wired-OR configuration with
open-collector or open-drain outputs on the peripheral.
Master Circuit Logic Flow Diagram
II
TLlF16144-6
MASTER CONFIGURATION STATE CHART
Status Register
02
0
0
0
0
1
1
1
1
01
0
0
1
1
0
0
1
1
DO
0
1
0
1
0
1
0
1
Description
Not used
In process of transmitting to slave during write slave mode
Valid daia received from slave
Not used
Awaiting data from slave during read slave mode
In process of transmitting to slave during read slave mode
Invalid data received from slaveInitialization/idle condition ,
"This state is entered if address or parity do not match_
7-65
Timing Diagram Description '
~'~~~~~-J
VIL,VOL-----
-
-r~;~~----
-----
-
lPO
------
,'
Ipo
TlIF16144-7
Symbol
Parameter
Min
Max
Units
tos
tOH
tpv
tpF
Data and Address Set-Up Time
Data and Address Hold Time
Serial Port Valid
Serial Port Float
Oulput Data Valid
Output Data Float
Overlap Requirement
Delay Between Master-Slave Transr,nission
CS • Function'
Rise and Fall Time
-
2
5
-
lose
lose
lose
lose
tov
tOF
t,
t2
t3
tpo
-
5
1733
1.0
-
0
ns
-
none
0.2
3
-
ILS
, 1.4
100
ms
tose
ns
OSCILLATOR CALCULATIONS
Conditions:
V=5V±5%
F ... 400 kHz
- 40·CsT s85·C
F=~
RC
where 0.8s Ks 1.4
Master Write Operation'
W/C2
AO-A6
00-07
SERIAL
REAOy-----..j-----IIEVIlICE TRANSMITIING - - ' - - - - i - - - - - D E V I C E READY
TLlF/6144·B
7-66
-t
§"
:s"
ea
C
;"
ea
;
3
c
Master Read Operation
m
cs
()
:::I"
-0
0"
R/Cl
::l
()
o
;::.
oj"
S
t:
CD
B
....~
AD-AS
00-07
SERIAL
DEVICE READY
IpF
I"
1-----12-1
DEVICE TRANSMITTING
WAITING
RECEIVE·-I
DATA READY"
•
I
TlIFJ6144·9
t1-there Is no overlap requirement for cHIP SELECT
t2-delay between master-slave transmission 0.2 rns to 1.4 rns
t3-minimum duration is 3 cycles of oscillator clock
* During "waiting to receive" state, CS coupled with RiC1 will force device into the device ready state.
* * If address or parity do not match, the data invalid state is entered. CS coupled with RiC1 will force device into the device ready state.
otl:tSWW
II
~
Typical Applications
Microprocessor Interface to Master
:E
:E
ADDRESS
DECODE
cs
'-------+--------::::;;;~:=~~------+lA6-AO
pP
5V
ij
Note: The timeout of the
5Vo-+---I
one-shot should
be~6'clock
periods of the MM54240 oscillator
TLlF/6144·10
Microprocessor Interface to Master
AODRESS
DECODE
ADDR BUS
0-0 CS
l
pP
DATA BUS
~
L
PORT A
PORT B
PORT C
Al INS8255
5V
CS
MM54240
RICI
W/C2
'-+c
Viii RESET
SYSTEM
POWER ON
RESET
A6-AO
~~ S-
07-00
iiii
WRITE
07-00
AD
DSC f-<
ILl
~
TL/Ff6144·11
\
Note: The INS8255Is specified by the mlcroprocessbrto operate In mode O. Port A Is configured as Input or ~utput. Ports Band Care
conflgure'~ as output only. Load ports A and B prior to loading port C.
Master to Slave (Short-Distance)
MODE
":'
5V
5V
MASTER
k
SLAVE
2.6k
":'
":'
TL/F/6144-,2
7-68
Typical Applications (Continued)
Master to Slave (Long Heul)
5V
5V
5V
5V
l80e
MASTER
MM54240
SERIAL
TIR
FROM .COMPUTER
>-_...._..J
TLIF/6144·13
•
7-69
~ ~National
:g
~ Semiconductor
::E
:IE
MM58167A Microprocessor Real Time Clock
General Description
The MM58167A is a low threshold metal gate CMOS circuit
that functions as a real time clock in bus oriented micro·
processor systems. The device includes an addressable
real time counter, 56 bits of RAM, and two interrupt out·
puts. A POWER DOWN input allows the chip to be disa·
bled from the rest of the system for standby low power
operation. The time base is a 32,768 Hz crystal oscillator.
Features
• Microprocessor compatible (8·bit data bus)
• Milliseconds through month counters
• 56 bits of RAM with comparator to compare the real
time counter to the RAM data
• 2 INTERRUPT OUTPUTS with 8 possible interrupt
Signals
• POWER DOWN input that disables all Inputs and out·
puts except for one of the interrupts
• Status bit to Indicate rollover during a read
• 32,768 Hz crystal oscillator
• Four·year calendar (no leap year)
• 24-h~ur clock
Functional Description
Real Time Counter
The real time counter is divided into 4·bit digits with 2
digits being accessed during any read or write cycle. Each
digit represents a BCD number and is defined in Table I.
Any unused bits are held at a logical zero during a read and
ignored during a write. An unused bit is any bit not neces·
sary'to provide a full BCD number. For example tens of
hours cannot legally exceed the number 2, thus only 2 bits
are necessary to define the tens of hours. The other 2 bits
in the tens o,f hours digit are unused. The unused bits are
designated in Table I as dashes.
Interrupts and Comparator
There are two interrupi outputs. The first and most flexible
is the INTERRUPT OUTPUT (a true high signal). This out·
put can be programmed to provide 8 different output '
signals. They are: 10 Hz, 1 Hz, once per minute, once per
hour, once a day, once a week, once a month, and when a
RAMlreal time counter comparison occurs. To enable the
output a one is written Into the interrupt control register at
the bit location corresponding to the desired output
'frequency (Figure 1). Once one or more bits have been set
in the interrupt control register, the corresponding
counter's rollover to its reset state will clock the Interrupt
status register and cause the Interrupt outP,ut to go high.
To reset the interrupt and to Identify which frequency
caused the interrupt, the Interrupt status register is read.
Reading this register places the contents of the status
register on the data bus. The Interrupting frequency will be
Identified by a one In the respective bit pOSition. Removing
the read will reset the interrupt.
The second interrupt is the STANDBY INTERRUPT (open
drain output, active lOW). This Interrupt occurs when
enabled and when a RAMlreal time counter comparison
occurs. The STANDBY INTERRUPT Is enabled by writing a
one on the DO line at address 16 H or disabled by writing a
zero on the DO line. This Interrupt Is not triggered by the
edge of the compare Signal, but rather by the level. Thus If
the compare is enabled whim the STANDBY INTERRUPT
Is enabled, the interrupt will turn on Immediately.
Connection Diagram
Dual·ln·Llne Package
cs...!.
The addressable portion of the counter is from mililsec·
onds to months. The counter itself is a ripple counter. The
ripple delay is less than 60l's abovE!4.0V and 300 I's at 2.0V.
RAM
u
.!!.VOD
ifij...!
.!!.~
\'iii...!
E..D7
JiiiV....!
!!.oOB
AD...!
~05
AI..!.
.!!.04
MM51167A
56 bits of RAM are contained on·chip. These can be used
for any necessary power down storage or as an alarm
latch for comparison to the real time counter. The data In
the RAM can be compared to ,the real time counter on a
digit basis. The only digits that are not compared are the
unit ten thousandths of seconds and tens of days of the
week (these are unused in the real time counter). If the two
most significant bits of any RA'M digit are ones, then this
RAM location will always compare.
A2...!..
.!!.D3
A3....!.
1!.02
A4..!
.!!.01
OSCIN.!.!!.
.!!.. DO
.!!. sTANDBY INTERRUPT
OSC OUT..!!
vss..!!
.!!.INTERRUPT
• .L--_ _ _ _ _ _....- OUTPUT
The RAM is formatted the same as the real time counter, 4
bits per digit, 14 digits, however there are no unused bits.
The unused bits in the real time counter will compare only
to zeros in the RAM.
TOP VIEW
Order Number MMSB167AN
See NS Package N24A
7·70
TI..fFf6148-1
.Absolute Maximum Ratings
Voltage at All Pins
Operating Temperature
Vss - 0.3V to V oo + 0.3V
O·C to 70·C
6.0V
300·C
Voo-Vss
Lead Temperature(Soldering, 10 seconds)
- 65·C to 150·C
Storage Temperature
Electrical Characteristics Vss = OV, 0·C$TA $70·C
Conditions
Min
Max
Units
Outputs Enabled
POWER DOWN Mode
4.0
2.0
5.5
5.5
V
V
10
p.A
20
p.A
5
mA
0.8
Voo
V
V
1
p.A
0.4
1
V
V
V
p.A
0.4
10
V.
p.A
Parameter
Supply Voltage
Voo
Voo
Supply Current
100 , Static
100 , Dynamic
100 , Dynamic
Outputs TRI·STATE®
fiN = ~C, Voo = 5.5V
Outputs TRI·STATE
f 1N =32 kHz, Voo =5.5V
VIH~ Voo - 0.3V
VIL $ Vss + 0.3V
Outputs TRI·STATE
fiN = 32 kHz, Voo = 5.5V
VIH = 2.0V, VIL = 0.8V
Input Voltage
Logical Low
Logical High
0.0
2.0
Input Leakage Current
VSS$VIN$VOO
Output Impedance
Logical Low
Logical High
I/O and INTERRUPT OUT
Voo = 4.5V, 10L = 1.6 mA
Voo = 4.5V, 10H = - 400 p.A
10H= -10p.A
VSS$VOUT$VOO
TRI·STATE
Output Impedance
Logical Low, Sink
Logical High, Leakage
-1
.
2.4
0.8 Voo
-1
ROY and STANDBY INTERRUPT
(Open Drain Devices)
Voo = 4.5V, 10L = 1.6 mA
VOUT$Voo
,
Functional Description (Continued)
TABLE I. Real Time Counter Format
Counter Addressed
00
Units
01 02
Max
BCO
Code
03
Tens
05 06
0
04
05
06
07
9
9
04
05
06
07
9
9
04
05
06
-
5
-
5
-
0
1/10,000 of Seconds
(OOH) .
-
-
-
-
Hundredths and Tenths Sec
(01H)
DO
01
02
03
Seconds
(02 H)
DO
01
02
03
Minutes
(03 H)
DO
01
02
03
9
04
05
06
DO
01
02
03
9
04
05
-
Hours
(04H)
,
Day of the Week
(05H)
DO
01
02
-
7
-
-
Day of the Month
(06 H)
DO
01
02
03
9
04
05
-
Month
(07H)
DO
01
02
03
9
04
-
-
(- )'indicates ~nused bits
7·71
Max
BCO
Code
04
t17
2
3
1
•
Functional Description (Continued)
TABLE II. Address Codes and Functions
A4
A3
A2
Ai
AO
Function
0
0
0
0
0
Counter-Ten Thousandths of Seconds
0
0
0
0
1
Counter- Hundredths and Tenths of Seconds
0
0
0
1
0
Counter-Seconds
0
0
0
1
1
CQunte~ -
0
0
1
0
0
Counter- Hours
0
0
1
0
1
Counter-Day of Week
0
0
1
1
0
0
0
1
1
1
Minutes
Counter- Day of Month
"
Counter-Month
RAM-Ten Thousandths of Seconds
0
1
0
0
0
0
1
0
0
1
-0
1
0
1
0
0
1
0
1
1
RAM-Minutes
0
1
1
0
0
RAM-Hours
0
1
1
0
1
RAM - Day of Week
0
1
1
1
0
RAM-Day of Month
RAM-Hundredths and Tenths of Seconds
\
RAM-Seconds
0
1
1
1
1
RAM.....-Months
1
0
0
0
0
Interrupt Status Register
1
0
0
0
1
Interrupt Control Register
1
0
0
1
0
Counters Reset
1
0
0
1
1
RAM Reset
1
0
1
0
0
Status Bit
1
0
1
0
1
1
0
1
1
0
1
1
1
1
1
,
GO Command
"
STANDBY INTERRUPT
Test Mode
All others unused
\
I
.r-
7·72
Functional Description (Continued)
The comparator is a cascaded exclusive NOR. Its output is
latched 61 P.s after the rising edge of the 1 kHz clock signal
(input to the ten thousandths of seconds counter). This
allows the counter to ripple through before looking at the
comparator. For operation at less than 4.0V, the thousandths of seconds counter should not be included in a compare because of the possibility of having a ripple delay
greater than 61 p.s. (For output timing see Interrupt
Timing.)
rippling, invalid data may be read from the counter. If the
status bit is set following a counter read, the counter
should be reread.
The status bit appears on DO when address 14H is read. All
the other data lines will be zero. The bit is set when a
logical one appears. This bit should be read every time a
counter read or after a series of counter reads are done.
The trailing edge of the read at address 14H will reset the
status bit.
Power Down Mode
Oscillator
The POWER DOWN input is essentially a second chip
select. It disables all inputs and outputs except for the
STANDBY INTERRUPT. When this input is at a logical
zero, the device will not respond to any external signals. It
will, however, maintain timekeeping and turn on the
STANDBY INTERRUPT if programmed to do~The
programming must be done before the POWER DOWN input goes to a logical zero.) When switching Voo to the
standby or power down mode, the POWER DOWN input
should go to a logical zero at least 1 fJ.S before Voo is
switched. When switching V DO all other inputs must remain between Vss - 0.3V and Voo + 0.3V. When restoring
VOD tothe normal operating mode, it is necessary to insure
that all other inputs are at valid levels before switching the
POWER DOWN input back to a logical one. These precautions are necessary to insure that no data is lost or altered
when changing to or from the power down mode.
The oscillator used is the standard Pierce parallel resonant oscillator. Externally, 2 capacitors, a 20 M{l resistor
and the crystal are required. The 20 M{l resistor is' connected between OSC IN and OSC OUT to bias the internal
inverter in the linear region. For micropower crystals a
resistor in series with the oscillator output may be
necessary to insure the crystal is .not overdriven. This
resistor should be approximately 200 k{l. The capacitor
values should be typically 20 pF-25 pF. The crystal frequency is 32,768 Hz.
The oscillator input can be externally driven, if desired. In
this case the output should be left floating and the input
levels should be within 0.3V of the supplies.
A ground line or ground plane between pins 9 and 10 may
be necessary to prevent interference of the oscillator by
.
the A4 address.
Counter and RAM Resets; GO Command
Control Lines
The counters and RAM can be reset by writing all1's (FF) at
address 12H or 13H respectively.
The READ, WRITE, and CHIP SELECT signals are active
low inputs. The READY signal is an open drain output. At
the start of each read or write cycle the READY line (open
drain) will pull low and will remain low until valid data
from a chip read appears on the bus or data on the bus is
latched in during a write. READ and WRITE must be
accompanied by a CHIP SELECT (see Figures 3 and 4 for
read and write cycle timing).
During a read or write, address bits must not change while
. chip select and control strobes are low.
A write pulse at address 15 H will reset the thousandths,
hundredths, tenths, units, and tens of seconds counters.
-This GO command is used for precise starting olthe clock.
The data on the data bus is ignored during the write. If the
seconds counter is at a value greater than 39 when the GO
is issued, the minute counter will increment; otherwise the
minute counter is unaffected. This command is not necessary to start the clock, but merely a convenient way to
start precisely at a given minute.
Test Mode
Status Bit
The test mode is merely a mode for production testing. It
allows the counters to count at a higher than normal rate.
In this mode the 32 kHz oscillator input is connected
directly to the ten thousandths of seconds counter. The
chip select and write lines must be low and the address
must be held at 1FH.
The status bit is provided to inform the user that the clock
is in the process of rolling over when a counter is read. The
status bit is set if this 1 kHz clock occurs during or after
any counter read. This tells the user that the clock is rippling through the real time counter. Because the clock is
7-73
•
Standby Interrupt
Typical Characteristics
Functional Description (Continued)
1.5
D,O
WRITE
DNLY
IN 0
,1
I
IN 0
D,3
. 0,2
J J
INO
D,5
OJ
1
IN
INO
o
I
INO
D,6
I
I
IN 0
Y
IN
0
INTERRUPT
CONTROL
REGISTER
AOORESS'llH
lIMIN
IfHDUR
1/SEC
1/0AY
101SEC
I
CDMPARE~l
C
READ
ONLY
oD
1 I I
CaD
CaD
Ca 0
I I I
COD
C aD
C
~
I
CaD
r
0
r- llMDNTH
C 0
~
V
0
0.5
1.0
1.5
VOUT (V)
INTERRUPT
STATUS
TL/FI6146-3
14
REGISTER
a
""
ADDRESS- 10H
L
I I
0.5
~
V
oS
llWEEK
I
/
1.0
.3
12
"
'"i'
<
10
z
I
/
/
8
>
INTERRUPT
INTERRUPT
LOGIC
r+ fAUC;o;~~
LDGIC HIGH)
":3
~
6
0:
4
....>
/
2
0
1
2
Sym
6
5
TUFI6148-4
FIGURE 2. Typical Supply
Current vs Supply Voltage
During Power Down
0·CsTA s70·C, 4.5VsVoos5.5V, Vss=OV
Parameter
(V)~
TLlF/6148-2
FIGURE 1. Interrupt Register Format
Interrupt Timing
4
3
VDD
Min
Max
Units
tiNTON
Status Register Clock to INTERRUPT
OUTPUT (Pin 13) High (Note 1)
5
JlS
tSBYON
Compare Valid to STANDBY INTERRUPT
(Pin 14) Low (Note 1)
5
JlS
t)NTOFF
Trailing Edge of Status Regist~r
Read to INTERRUPT OUTPUT Low
5
Jls
tSBYOFF
Trailing Edge of Write Cycle
(DO = 0; Address = 16H) to STANDBY
INTERRUPT Off (High Impedance State)
5
Jls
\
Note 1: The status register clocks are: the corresponding counter's rollover to Its reset state orthe compare becoming valid. The compare becomes valid61
after the 1/10,000 of a second counter Is clocked, if the real time counter data matches the RAM data.
Read Cycle Timing
Sym
JlS
0·CsTAs70·C;4.5VsVoos5.5V, Vss=OV
Parameter
Min
Max
tAR
tesR
Chip Select to Read'Strobe
tRRY
Read Strobe to Ready Strobe
150
ns
tRyO
Ready Strobe to Data Valid
800
ns
tAD
Address Bus Valid to Data Valid
1050
ns
tRH
Data Hold Time From Trailing Edge of Read Strobe
tHZ
Trailing Edge of Read Strobe to TRI·STATE Mode
tRYH
Read Hold Time after Ready Strobe
100
Units
Address Bus Valid to Read Strobe
ns
ns
0
ns
0
250
tRA
Addre.ss Bus Hold Time from Trailing Edge of Read Strobe
tRYOV
Rising Edge of Ready to Data Valid
ns
50
ns
100
Note 2: If tAR = 0 and Chip Select, Address Valid or Read are coincident then they must exist for 1050 ns.
7·74
ns
0
ns
Write Cycle Timing
0·C",TA ",70·C, 4.5V",V oo ",5.5V, Vss=OV
Parameter
Sym
Min
Units
Max
100
ns
0
ns
tAW
Address Valid to Write Strobe
tcsw
Chip Select to Write Strobe
tow
Data Valid before Wriie Strobe
tWRY
Write Strobe to Ready Strobe
150
ns
tRY
Ready Strobe Width
800
ns
tRYH
Write Hold Time after Ready Strobe
two
Data Hold Time after Write Strobe
..__ tWA
0
ns
110
ns
50
ns
Address Hold Time after Write Strobe
Note 3: If data changes while
ns
100
Cs and WR are low, then they must remain coincident for 1050 ns after the data change to ensure a valid write.
Oata bus loading is 100 pF.
Ready output loading is 50 pF and 3 k!l pull-up.
Input and output AC timing levels:
Logical one =2.0V
Logical zero = O.BV
Read and Write Cycle Timing Diagrams
x==
ADDRESS VALID
AO-M==><
tAR
cs
r- tRA -
!-tCSR--r-tRRY-
\
Rii
J
!--tRVtt-
.\
RDY
t1
tRVD
_tRYDV
_tRH_
DO-Dl
DATA VALID
_tHZ_
tAD
TLlF16148·5
FIGURE 3. Read Cycle Timing
X
ADDRESS VALID
AO-M = = > <
I
tAW
-twA-I
cs
_tRVH ___
I - - t c s w - - -twRY-
\
Wli
RDY
1---tDW---
DO-Dl
<
I
\
---tRY---
DATA VALID
II
)
TLlFf6t46·6
FIGURE 4. Write Cycle Timing
.'
-twD-
7·75
•
Typical Applications
SYSTEM
ADDRESS BUS
SYSTEM DATA
BUS
.........
....~
8
....J::.
STANDBY
_
BATTERY
A5
CHIP
SELECT
lDGIC
A6
A7
IIN4148
2
Rli
J~ Wi!
Wi!
4
RDY
AD
5
AI
6
A2
7
A3
8
A4
9
NOTE4
10
RI
11
CI
.... r-...
71"'"""'
":::-
XTAl
D5 20
T
5V
Ik
10k
.
D¢ 19
IB
D3
17
D2
16
01
15
DO
SIDBY INT 14
MM58167A
A2
A3
A4
DSC IN
OSC OUT
"SS
HUt~
32,768 Hz
D6 21
AD
12
R2
-200k
IOPTlONAl}
2N2907
PWR DDWN IFROM SYSTEM}
D7 22
RDY
AI
~3V
lOOk
,
24
VDD
PWR DiiWN 23
.l.. CS
AD
~~
~ ~3V±1 0%
2N2222
•
'::'
5k
~
{OPERATIONAL DURING
PWifilllWN CDNDITIDN}
INTr!L
'::'
R1 =20 M!l±20%
-20 pF
'::'
SYSTEM
INTERRUPT
(NORMAL POWER ON
SYSTEM INTERRUPT)
C1 =6 pF-36 pF
R2 to be selected
based on crystal us ed:
--
TlIFI61 '&7
Note 4: A ground line or ground plane guard trace should be included b~tween pins 9 and 10 to Insure the oscillator is ~ot disturbed by the address line.
FIGURE 5. Typical Connection Diagram
5V
SYSTEM
ADDRESS BUS
-=+
lOOk
STANDBY
BATTERY'
'~3V
VDD= 5V
~~f::-...._:;;AO:..-.;;A;:.4......,~_ _ _...;5:..-~9 AO-A4
5
D:;;~~~_-...;.15:..-.:;22=-! DO-D7
MM58167A
2jjjj
Wi!
INT
OUT
13
RDY
4
DBO-DB7
8238
1I0R
IIOW
25
27
26
24
MEMW
MEMii
INTERRUPT
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _~RE~A:;;O;:.V_ _ _ _ __4~~20~k~VOD
TLIF/6148·8
Note 5: Must use 8238 or equivalent logic to Insure advanced IJOW pulse; so that the ready output of the MM58167A Is valid by the end of <1>2 during the T2
mlcrocycle.
Nota 6: t2",tRS8060 + t0L8238 +tWRY58167A' .
FIGURE 6. 8080 System Interlace with Battery Backup
7-76
Block Diagram
8 BITS
:;; 39.5
~
29.5
+"
~ 19.5
9.5
" " - - - - ' - - - - - ' - - - - L - - - - ' - -... IOUT (,.AI
200
400
600
BOO
TLIFI5600·3
FIGURE 3a. Output Impedance Off
3.3 kO TYPICAL
AT +25·C. VDlS = -4DV
2.3 kll MAX
AT -40·C. VOIS = -55V
5·
o .::__-'___......1._ _ _-'-_ _ _- ' - _. .
lOUT (mAl
o
FIGURE 3b. Output Impedance On
TUFI560G-4
Timing Diagrams
For the purposes of AC measurements, VIH
=2.4V, VIL ::;;O.BV.
TLlF1560Q·5
FIGURE 4. Clock and Data Timings
C~CK 50%~-~~~r-+---~--~~----~~--~-------
DATA IN 50%
MMOUT
:t:v-t::t::t=~C-====~~====~C-=:
50%~--+-~-1--~-------~~----------~-----
tfSt:::!:~::-'II _ _ _' " ' - - - - - '
ENABLE 50% ~--II\:======J------~\:====:
B~~~~
50%
VOO
========i,,---"\f-----",i::=======
----·r---'
DISPLAY
OUTPUT
VOIS----J
TLIF/560D-S
FIGURE 5. MM58241 Timings (Data Format)
7·93
•
;
. ~ Typical Application
:Ii
:Ii
32-OIGIT MULTIPLEXED
5 x 7 DOT MATRIX
VACUUM FLUORESCENT
(VF) DISPLAY
CLOC K8
I
I
------
35 ANODES
r-----,
MM58248
DISPLAY DRIVER
MM58241
DISPLAY DRIVER
32 GRIDS
DATA 8
DATA 1-"·
CLOCK 1
1
ENABLE 1
BLANK 1
I
MICROPROCESSOR
DATA
OUT 1
TlIFI56QO·7
FIGURE 6_ Microprocessor-Controlled Word Processor
7-94
~National
~ Semiconductor
MM58242 High Voltage Display Driver
General Description
Features
The MM58242 is a monolithic MOS integrated circuit utilizing CMOS metal gate low threshold P and N-channel
devices. It is available both in 28-pin molded dual·ln-line
packages or as dice. The MM58242 is particularly suited
for driving high voltage (60V max) vacuum fluorescent (V F)
displays (e.g., a 20-digit alphanumeric or dot matrix
display).
•
•
.•
•
•
•
•
•
•
Applications
•
•
•
•
•
•
COPSTM or microprocessor·driven displays
Instrumentation readouts
Industrial control indicator
Digital clock, thermostat, counter, voltmeter
Word processor text displays
Automotive dashboards
Direct interface to high voltage display
Serial data input
No external resistors required
Wide display power supply operation
LSTTL compatible Inputs
Software compatible with NS display driver family
Compatible with alphanumeric or dot matrix displays
Display blanking control input
Simple to cascade
Block and Connection Diagrams
OUTPUT
20
OUTPUT
1
Dual·ln·Line Package
VSS (OV)
I+-oi+-VOIS
28
OUTPUT 13
OUTPUT 10
OUTPUT 14
OUTPUT 9
OUTPUT 15
OUTPUT 8
OUTPUT 16
OUTPUT 7
OUTPUT 17
OUTPUT 6
OA~~_...._ ..
CLOCK -+t-l"
MM58242
OUTPUT 18
OUTPUT 5
OUTPUT 19
OUTPUT 4
OUTPUT 20
OUTPUT 3
10
BLANKING CONTROL
OUTPUT 2
11
ENABLE
OUTPUT 1
12
OATA OUT
YOIS
13
DATA IN
Voo (5V)
ENABLE - - - - - '
OUTPUT 12
OUTPUT 11
...1_4_ _ _ _ _ _- '
CLOCK
TUFJ79:z4.1
TOP VIEW
FIGURE 1
FIGURE 2
Order Number MM58242N
See NS Package N28B
7-95
TUF17924·2
II
Absolute Maximum Ratings
Operating Conditions
Voltage at Any Input Pin
Voltage at Any Display Pin
Supply Voltage (V oo)
Vss=OV
Display Voltage (V OIS)
Temperature Range
Min
Voo + 0.3Vto Vss - 0.3V
Voo to Voo - 62.5V
62.5V
Voo + IVolsl
Storage Temperature
-65·Cto + 150·C
Power Dissipation
500mWat + 85·C
Junction Temperature
130·C
Lead Temperature (Soldering, 10 seconds)
260·C
4.5
-55
-40
Max
Units
5.5
-25
V
V
·C
+85
DC Electrical Characteristics TA =
Symbol
- 40·C to + 85·C, VOO = 5V ± 0.5V, Vss= ov unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Power Supply Currents
100
VIN = VSS or VOO , VSS = OV, V OIS Disconnected
150
p.A
lOIS
V oo =5.5V, VSS= OV, VDls= -55V
All Outputs Low
10
mA
0.8
V
Input Logic Levels
DATA IN, CLOCK
ENABLE, BLANK
VIL
Logic '0'
VIH
Logic '1'
(Note 1)
2.4
V
Data Output Logic Levels
VOL
Logic '0'
lour=400p.A
VOH
Logic '1'
lour= -10 p.A
Voo-0.5
VOH
Logic '1'
lour= -500p.A
2.8
liN
Input Currents
DATA IN, CLOCK
ENABLE, BLANK
VIN = OV or Voo
-10
C IN
Input Capacitance
DATA IN, CLOCK
ENABLE, BLANK
Display Output Impedances
V oo =5.5V, Vss=OV
ROFF
'Output Off (Figure 3a)
VOls= -25V
VOIS = -40V
VOIS = -55V
RON
Output On (Figure 3b)
VDlS = -25V
VDlS = -40V
VOIS = -55V
VOOL
Display Output Low Voltage
Voo = 5.5V, lour = Open Circuit,
-55VsV ols s -25V
V
0.4
V
V
60
70
80
3.0 .
2.6
2.3
Nole 1: 74LSTTL VOH=2.7V @ lour= -400 "A, TTL VOH =2.4V @ lour= -400 "A.
7·96
VDlS
10
p.A
15
pF
400
550
650
4.0
3.7
3.4
kO
kO
kO
kO
kO
kO
VDls+4
V
,
i:
AC Electrical CharacteristicsTA =
Parameter
s::
81
-40°Cto + 85°C, Voo=5V±0.5V
Conditions
Min
Typ
Max
Units
~
N
Clock Input
Frequency, fc
High Time, tH
Low Time, tL
(Notes 3 and 4)
300
300
kHz
ns
ns
Data Input
Set-Up Time, tos
Hold Time, tOH
100
100
ns
ns
Enable Input
Set-Up Time, t ES
Hold Time, tEH
100
100
ns
ns
Data Output
CLOCK Low to Data Out
Time, tcoo
800
CL =50pF
500
ns
Note 2: For timing purposes, the signals ENABLE and BLANK can be considered to be totally independent of each other.
Note 3: AC input waveform specification for test purposes: t r s20 ns, t,:::;;20 ns, f =800 kHz, 50% ± 10% duty cycle.
Note 4: Clock input rise and fall times must not exceed 5,...s.
Functional Description
When the chip first powers on, an internal reset is
generated, resetting all registers and latches. The chip
returns to normal operation on application of ENABLE,
and so all interface signals should be inactive at power on.
This product is specifically designed to drive multiplexed
or non-multiplexed high voltage alphanumeric or dot
matrix vacuum fluorescent (VF) displays. Character
generation is done externally in the microprocessor, with a
serial data path to the display driver. The MM58242 uses
three signals, DATA IN, CLOCK and ENABLE, where
. ENABLE acts as an external load signal. Display blanking
can be achieved by means of the BLANKING CONTROL
input, and a logic '1' will turn off all sections of the display.
A block diagram of the MM582~iiS shown in Figure 1.
In Figure 5, the ENABLE signal acts as an envelope, and
only while this signal is at a logic '1' does the circuit accept CLOCK input signals. Data is transferred and shifted
in the internal shift register on the rising clock edge, i.e.,
'0'-'1' transition. When the ENABLE signal goes low, the
contents of the shift registers are latched, and the display
will show new data. During data transfer, the display will
show old data. DATA OUT is also provided on the
MM58242 being output on.the falling edge. At anytime, the
display may be blanked under processor control, using the
BLANKING CONTROL input.
Figure 2 shows the pinout of the MM58242 device, where
output 1 (pin 12) is equivalent to bit 1 (i.e., the first bit of
data to be loaded into the shift register following ENABLE
high). A logic '1' at the input will turn on the corresponding
display digit/segment/dot output.
A significant reduction in discrete board components can
be achieved by use of the MM58242, because external
pull·down resistors are not required. Due to the nature of
the output stage, both its on and off impedance values
vary as a function of the display voltage applied. However,
Figures 3a and 3b show that this output impedance will reo
main constant for a fixed value of display voltage.
Figure 6 shows a schematic diagram of a microprocessorbased system where the MM58242 is used to provide the
grid drive for a 40-digit 2 line 5 x 7 multiplexed vacuum
fluorescent (VF) display. The anode drive in this example is
provided by another member of the high voltage display
driver family, namely the MM58248, which does not require
an externally generated load signal.
Figure 4 demonstrates the critical timing requirements
between CLOCK and DATA IN for the MM58242.
7-97
,.
~
Functional Description (Continued)
:IE
:IE
+B5'C
+25'C TYPICAL
-40'C
59.5
_ 49.5
>
.
::;; 39.5
~ 29.5
~ 19.5
9.5
I E . . . - - . . . . . L - - - - ' - - - - ' - - - - - ' - - _ I O U T (,.A)
200
600
400
BOO
TLfFI1924-3
FIGURE 38. Output Impedance Off
3.3 kn TYPICAL
AT + 25'C. VOIS = -40V
2.3 kn MAX
AT -4Q'C, VOIS = -55V
00· " ' - - - - " ' - - - - - - " - - - · - ' 3 ' - - - - - ' - - - lOUT (mA)
TUF/7924-t
FIGURE 3b. Output Impedance On
Timing Diagrams
CLOCK
DATA IN
:i
'OS ..5_0_"_ _
Forthe purposes of AC measurements: VIH = 2.4V, VIL =O.SV.
TUFI79Z4·5 .
FIGURE 4. Clock and Data Timings
CLOCK 50% -+-#--+~-I----,#_-~---'--1r-T---
OMAOUT
50"=t~~~~~~::::::~~;:::::::~~:::::
l-=t=~;::====="JC==~\:====
lliS:
ENABLE 50%
B~=:~~~
r=-\________
50% _ _ _ _ _ _ _ _
VOO
-----r---'"'"
DISPLAY
OUTPUT
VOIS---J
FIGURE 5. MM58242 Timings (Data Format)
7·98
TUFf7924-6
Typical Application
40·DlGIT BY 2·LlNE
5 x 7 MULTIPLEXED
DOT MATRIX VACUUM
FLUORESCENT (VF)
DISPLAY
20
GRIDS
35
ANODES
ANODES
CLOCK 8
I
I
----
---35
MM58248
DISPLAY
DRIVER 1
I
I
I
~
DATA 81
20
GRIDS
----
----
I
MM58248
DISPLAY
DRIVER 2
MM58242
DISPLAY
DRIVER 1
OUT
FA
I
DATA 82
DATA 22
MM58242
DISPLAY
DRIVER 2
1
I
CLOCK 2
DATA 21
MICROPROCESSOR
ENABLE
BLANK
TLIF/7924-7
FIGURE 6. Microprocessor·Controlied Word Processor
•
7·99
i~ ~
National
.
~ Semiconductor
MM58248 High Voltage Display Driver
General Description
Features
The MM58248 is a monolithic MOS integrated circuit utilizIng CMOS metal gate low threshold P and N-channel
devices. It is available both In 40-pin molded dual-In-line
packages or as dice. The MM58248 is particularly suited
for driving high voltage (60V max)vacuum fluorescent (VF)
displays (e.g., a 5 x 7 dot matrix display).
•
•
•
•
•
•
•
•
Applications
•
•
•
•
•
•
Dire~t interface to high voltage display
Serial data input
No external resistors required
Wide display power supply operation
LSTTL compatible Inputs
Software compatible with NS display driver family
Compatible with alphanumeric or dot matrix displays
No load signal required
COPSTM or microprocessor-driven displays
Instrumentation readouts
Industrial control indicator
Digital clock, thermostat, counter, voltmeter
Word processor text displays
Automotive dashboards
Bloc.k and Connection Diagrams
OUTPUT
35
Dual-In-Line Package
OUTPUT
1
Vss (OV)
VDlS
OUTPUT 17
OUTPUT 16
OUTPUT 15
OUTPUT 14
OUTPUT 13
OUTPUT 12
OUTPUT 11
OUTPUT 10
OUTPUT 9
OUTPUT 8
OUTPUT 7
OUTPUT 6
OUTPUT 5
OUTPUT 4
OUTPUT 3
OUTPUT 2
OUTPUT 1
VDlS
DATA IN
CLOCK
You (5V)
10
11
12
13
14
15
16
17
18
19
20
MM58248
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OUTPUT 18
OUTPUT 19
OUTPUT 20
OUTPUT 21
OUTPUT 22
OUTPUT 23
OUTPUT 24
OUTPUT 25
OUTPUT 26
OUTPUT 27
OUTPUT 28
OUTPUT 29
OUTPUT 30
OUTPUT 3f
OUTPUT 32
OUTPUT 33
OUTPUT 34
OUTPUT 35
DATA IN
CLOCK
TOP VIEW
TUFt5599-2
TLIF/5599-1
FIGURE 1
FIGURE 2
Order Number MM58248N
See NS Package N40A
7-100
Absolute Maximum Ratings
Operating Conditions
Voltage at Any Input Pin
Voltage at Any Display Pin
Supply Voltage (Voo)
Vss=OV
Display Voltage (VOIS)
Temperature Range
Min
Voo + 0.3Vto Vss - 0.3V
Voo to Voo - 62.5V
62.5V
Voo + IVDlsl
-65·Cto + 150·C
Storage Temperature
Power Dissipation
500 mW at + 85·C
130·C
Junction Temperature
260·C
Lead Temperature (Soldering, 10 seconds)
DC Electrical Characteristics TA =
Symbol
4.5
-55
5.5
-25
-40
+85
Units
V
V
·C
.,
- 40·C to + 85·C, Voo = 5V ± 0.5V, Vss =
Parameter
Max
Conditions
ov unless otherwise spe~ified
Min
Typ
Max
Units
Power Supply Currents
100
V IN = Vss or V oo , Vss = OV, V OIS Disconnected
150
p.A
I DIS
V oo =5.5V, Vss=OV, V OIS = -55V
All Outputs Low
10
mA
Input Logic Levels
DATA IN, CLOCK
Vil
Logic '0'
VIH
Logic '1'
liN
Input Currents
~ATA IN, CLOCK
C IN
Input Capacitance
DATA IN, CLOCK
Display Output Impedances
V oo =5.5V, Vss=OV
ROFF
Output Off (Figure 3a)
VDlS = -25V
VDlS = -40V
VOIS = -55V
RON
Output On (Figure 3b)
VOIS= -25V
VDls= -40V
VOIS = -55V
V OOl
Display Output Low Voltage
Voo=5.5V, 10UT=Open Circuit,
-55V:5Vo ls:5 -25V
(Note 1)
VIN=OVorV oo
0.8
V
2.4
V
-10
10
p.A
15
pF
400
550
650
4.0
3.7
3.4
kO
kO
kO
kO
kO
kO
VOls+4
V
60
70
80
3.0
2.6
2.3
,
Note 1: 74lSTIl VOH =2.7V @ 10UT= -400 .A, TIL VOH =2.4V @ 10UT= -400 .A.
7·101
VOIS
•
AC Electrical CharacteristicsTA =
/
Parameter
-40·Cto
+ 85·C, VDD =5V±0.5V
Conditions
Clock Input
Frequency, fc
High Time, tH
Low Time, tL
(Notes 2 and 3)
Data Input
Set-Up Tlme,otos
Hold Time, tOH
C L=50pF
Min
Typ
Max
Units
1.0
300
300
MHz
ns
ns
100
100
ns
ns
Nole 2: AC Input wavelorm specification lor test purposes: t r , tfs20 ns, 1=1 MHz, 50% ± 10% duty cycle.
Nole 3: Clock Input rise and fail times must not exceed 5 pS.
Functional Description
data to be loaded into the shift register following the start
bit. A logic '1' at the input will turn on the corresponding
display digit/segment/dot output.
This product is specifically designed to drive multiplexed
or non-multiplexed high voltage alphanumeric or dot
matrix vacuum fluorescent (VF) displays. Charactergenerat ion is done externally in the microprocessor: with a '
serial data path to the display driver. The MM58248 uses
two signals, DATA IN and CLOCK, with a format of a
leading '1' followed by the 35 data bits, hence allowing
data transfer without an additional signal. A block
diagram of the MM58248Is shown in Figure 1.
A significant reduction In discrete board components can
be aChieved by the use of the MM58248, because external
pull-down resistors are not required. Due to the nature of
the output stage, both its on and off impedance values
vary as a function of the display voltage applied. However,
Figures 3a and 3b show that this outputJmpedance will remain constant for a fixed value of display voltage.
F/gure 2 shows the pind(lt of the MM58248 device, where
output 1 (pin 18) is equivalent to bit 1, i.e., the first bit of
+85'C
+Z5'C TYPICAL
-4o'C
59,5
E 49,5
~ 39.5
"+ Z9,5
~
19.5
E.:.---L.---..L...----l----1..--.IOUT (pAl
800
400
600
zoo
TL/F/5599·3
FIGURE 3a_ Output Impedance Off
3,3 k!l TYPICAL
AT +Z5'C, VOls=-4oV
2,3 k!l MAX
AT -40'C, VDlS = -55V
o £=---_---1._,--_-'-_ _ _.1...-_ _---1._...
lOUT (mAl
o
TlIF/5599·4
FIGURE 3b_ Output Impedance On
7-102
Functional Description (Continued)
Figure 4 demonstrates the critical timing requirements
between CLOCK and DATA IN lor the MM58248.
When the chip first powers on, an internal reset is generated, resetting all registers and latches. The chip' returns
to normal operation on application of the start bit and the
first clock pulse, and so all interface signals should be inactive at power on.
In Figure 5, a start bit of logic '1' precedes the 35 bits of
data, each bit being accepted on the rising edge of
CLOCK, i.e., a '0'-'1' transition. At the 36th clock, a LOAD
signal is generated synchronously with the high state of
the clock, thus loading the 35 bits of the shift register into
the latches. At the low state of the clock, a RESET signal is
generated, clearing all bits of the shift register for the next
set of data. Hence, a complete set of 36 clock pulses is
needed for the MM58248, or the shift register will not clear.
If, at any given time, it is required that the display be
cleared under microprocessor control, i.e., without power
on reset, then the following flushing routine may be used.
Clock in 36 'zeroes', followed by a 'one' (start bit), followed
by 35 'zeroes'. This procedure will completely blank the
display.
Figure 6 shows a schematic diagram of a microprocessorbased system where the MM58248 is used to provide the
anode drive for a 32·digit 5 x 7 dot matrix vacuum fluorescent (VF) display. The grid drive in this example is provided
by another member of the high voltage display driver family, namely the MM58241, which has the additional
features of a BLANKING CONTROL pin, a DATA OUT pin,
and an ENABLE (external load signal) pin.
Timing Diagrams
TlIF/5599-5
For the purposes of AC measurement, VIH;; 2.4V, VIL =O.BV
FIGURE'4. Clock and Data Timings
START
START
CLK 35
ClK
CLK 1
ClK 2
ClK 33
CLK 3
ClK 34
ClK 35
ClK
CLOCK
DATA IN
n
lOAD
(INTERNAL)
Jl
RESET
(INTERNAL)
---Jn 1___________....._______......
....._ _ _ _ _ _ _ _ _ _ _ _ _- - - - - - . .
n
:~~
VDlS
....._ _ _ __
____
/
------...1
\ , . - - - - - - - - -.....
rLlF15599-6
FIGURE 5. MM58248 Timings (Data Format)
7·103
~
Typical 'Application
:E
:E
32-01GIT MULTIPLEXED
5 x 7 DOT MATRIX
VACUUM FLUORESCENT
(VF) DISPLAY
I
I
35 ANODES
CLOC K8
32 GRIDS
------
~------
MM58248
DISPLAY DRIVER
MM58241
DISPLAY DRIVER
t
DATA 8
DATAl
CLOCK 1
1
ENABLE 1
BLANK 1
MICROPROCESSOR
DATA
OUT 1
TLlF15599·7
FIGURE 6. Microprocessor·Controlied Word Processor
7·104
iC
PRELIMINARY iC
~National
I
~ Semiconductor
MM58250 Infrared Transmitter
General Description
Features
The infrared transmitter is designed to drive an infrared
LED (only one external npn transistor Is required) with
data encoded In a pulse-width-modulated (pwm) format.
To get a better signal-to-noise-ratio the pwm scheme
amplitude modulates a 38kHz carrier_ The data to be
transmitted is input in two ways_ The primary data input
·mode (MS = 1) is through a 4-by-8 single-contact
keyboard which is interpreted by on-chip logic_ The
second input mode (MS = 0) is the direct input mode_ In
this mode a five-bit parallel word and a load pulse are
applied to the inputs. The five-bit word is then converted
to the pwm format and transmitted.
•
•
•
•
•
•
•
•
The chip is designed for battery operation, so it employs
a number of power-saving techniques. The chip is implemented in CMOS, so the supply current required by the
logic is low. The oscillator can be disabled, allowing the
stand-by current to be less than 11lA. Although the continuous transmission of the data stream Is possible, the
repetition rate of the continuous transmission is restricted, and the majority of the codes transmittable are
repeated only three times. (Twelve outputs can be repeated continuously for analog functions such as
volume and channel scanning).
Up to 32 functions decoded and transmitted
Single-contact scanned keyboard
Low standby current (CMOS)
455kHz on-Chip oscillator
Wide power supply range (3V-10V)
Keyboard or direct load modes
Direct load mode TTL compatible
38kHz carrier for improved signal-to-noise-ratio
• High current output stage
Applications
• TV remote control transmitter
• 5-bit wireless asynchronous transmitter
Block Diagram
KEYBOARD,
C3
C2
Cl
CD
INT
I
KEYBOARD
SCAN
-
R7
6
COUNTER
R5
CS
I I
R4
R3
R2
INPUT MODE SELECTOR
Rl
RO
•
r
r-
r-
MS
KEYDET~ 1-~
.........
~Rt =EH+
R6
lACK
·1
ENCODER
I
I·
....
,
SHIFT REGISTER
AND
PCM CONTROL
INTERRUPT
~
RI
o
II OUTPUT,f
SHAPING
MODULATOR
.L
-!~
IROUT
TlIFI6149·'
7-105
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Package Dissipation
-0.3 V to Voo +C.3V
O·Cto 70·C
-65·C to +150·C
500mW
Electrical Characteristics
Sym
Voo = 3.0V to 10V, TA"; ±
Parameter
Conditions
Power Supply
Voo Supply Voltage
Voo Supply Current (Active)
Voo Supply Current (Standby)
OSCillator, Frequency·
IR
IR
Output Voltage
Logic "0"
Logic "1"
150/'A Sink
10mA Source
MS=O, 4.5", Voo'" 5.5
Direct Mode
-10
Logic "0"
Logic "1"
Ro·R7
MS
Output Current
Cg,C1
Logic "1" Source
"1" Source
Logic. "0" Sink
"0" Sink
Output Current
Collnt (Open Drain)
Logic "1"
Logic "0"
Typ
Max
Units
10
5
1
V
mA
/'A
kHz
0.6
V
V
Voo-l.4
Input Levels
Input Current
Min
455
Voo-l.4V
Ro-Ra, MS
R7
o·c to 70·C unless otherwise specified.
3.0
Output Current
(Note: no short·clrcult
protection)
Input Current
12V
300·C
-20mA
Voo-Vss
Lead Temperature (Soldering, 10 seconds)
DC Current a~ IR Output
-20
mA
0.5
V
V
2.4
MS=O, 4.5V'" Voo'" 5.5V
Direct Mode
OV",VIN"'VOO
VIN=0.4V
-1
0.06
1.0
0.6
/'A
mA
MS=1,3.0V",Voo",10V
Keyboard Mode
V 1N =0.4V
OV",V1N"'VOO
0.024
-1
1.6
1
mA
,..A
MS=l
Voo=3V, Vour=Voo-1V
Voo=10V, Vour= Voo-l V
Voo=3V, Vour=0.4V
Voo=10V, Vour=0.5V
-40
-150
260
1.6
/'A
/'A
/'A
mA
MS=0,4.5V",VoO,,,,5.5V
1
O",Vour"'Voo
\(oUT=0.4V
2.5
··Determlned by external components.
7·106
/'A
mA
The divide·by·slx prescaler can be by·passed by applying a logic "0" to A71 when Asl = "1" and MS = "0". The
bY'pass is implemented by setting an AS-flip·flop that
controls the multiplexing of the main clock line from the
output of the divide·by-six prescaler to the output of the
oscillator, by-passing the divide·by-six prescaler. The
AS·flip·flop Is reset by the main internal reset which is
made active at the end of the transmit cycle, begun
before the by·pass was activated. If the MM58250 is
waiting for a new Input, switching A7/10w will have no
effect.
Connection Diagram
Dual·ln·Line Package
R2-1
18-Rl
R3- 2
R4"';" 3
17-RO
IROUT -
16 -VSS
15-C3
4
VOO- 5 MM58250 14-C2
R5/CS -
6
13-Cl
R6/IACK -
7
12 -
CO/INT
R7- 8
11 -
OSC OUT
MS-9
10 -OSCIN
TOP VIEW
The second special mode forces the main internal reset
active. This causes the chip to load in new data to be
transmitted and initializes the chip to the beginning of
the word cycle it was currently in or in the word cycle
folowing it, depending on where in the word cycle the
reset occurred. If a transmit cycle has been completed
this mode has no effect. A transmit cycle consists of
three word cycles. If no new data is loaded, the
MM58250 will go into its idle state within 45ms. See
Figures 9·11 for examples of how to use these features.
TL.IFI6149·2
Order Number MM58250N
See NS Package N18A
Pin Definitions
Mode Select (MS): This pin selects between the two
modes of the MM58250's operation.
CO/-C3/: .
Keyboard Mode (MS = 1):
Co/·C3I: These outputs are normally low when MM58250
is waiting for a new input contact closure to occur. A
contact closure causes the low signal on the column In·
puts to be passed to the appropriate row input. This In·
put going low initiates the transmit cycle. As the
transmit cycle begins, the oscillator is enabled and
begins to oscillate within 6ms. As soon as the oscillator
is enabled all the column outputs are switched to the
logic "1" state. 40.9ms later, as clocked by the on·chip
oscillator, these outputs are individually switched to
the logic "0" state (see Figure 5) and the row inputs are
sampled. If the sampling of the row inputs does not
show any of these Inputs low (see Figure 6b), the
transmit cycle is aborted. If any of the row inputs is low,
the binary representation'of the low row input and the
binary representation of the low column output are
stored In the tran~rT'!it buffer. If the low row input was
Ao/, All, A2/; ~6T. 'or A71 the outputs CO/,C31 all switch low,
50 internal logic can detect when all keyboard switches
have been opened. This feature allows the MM58250 to
terminate transmission after three Iterations (see
Figure 6a) of the output data, even when a contact
closure exists longer than the time required to transmit
the data three times.
MS = "0": Parallel input mode. This mode is designed to
allow five bits of data to be written to the MM58250 in a
parallel fashion with all the appropriate handshaking sig·
nals required to facilitate interfacing a microprocessor.
MS="l": Keyboard Input mode. Data is input from a
keyboard configured as a matrix of four column conduc·
tors and eight row conductors separated at each point of
the matrix by a single c6ntact.
Ro/-R7/:
Keyboard Mode (MS = 1):
Ro/·R7/: Act as row inputs for a scanned column key·
board.lnternal to the MM58250, these are encoded such
that If just one input is low during a scan of the column
outputs, (see the discussion of plns'Co/,C31) a parallel·ln·
serial·out transmit buffer is loaded with the binary rep·
resentation of the low row Input and the scanning col·
umn. [[he binary number loaded Is equal to the decimal
number in the pin name, i.e. binary 5 Is stored for the As
input.) In addition A3I·As/ cause the MM58250 to contino
uously transmit the data stored In Its transmit buffer
(see Figure 6) as long as a switch closure exists.
Parallel Mode (MS=O):
Parallel Mode (MS = 0):
CoI·C3I: In the parallel mode only one of the column
outputs Is still used. This output is used as the Col strobe
in the keyboard mode. It is used in this mode as an active
low processor interrupt (INTI). This output is designed to
drive one TTL input with a 10k pullup resistor. It is reset by
the lACK pin. When A5/CS is a logic 1, this signal goes low
after the last transmission is complete.
Ro/·R4: These five inputs act as a parallel, non·inverting,
5·bit data entry path.
Rs/·CS/: This active low Input is used to latch In the data
at the Ao/·A41 inputs, as well as beginning the transmit
cycle. The part will continue to transmit as long as this
input is low and continue to transmit two to three trans·
mit cycles after the input switches to logic "1", depend·
Ing on where (see Figures 7 and 8) in the transmit cycle
the logic change occured. (Note: the data on Ao/·A4'
should be held stable a minimum of 60ms.)
Rs/·IACK: This input is used to reset
active high. (See Figure 7)
IROUT: This is the output that provides the drive signal
for the transmission (see Figures 3 and 4). IAOUT provides at least 10mA of current, sufficient to drive a
single npn transistor hard enough to provide the 200mA
of drive current for the infra·red diodes. The data is
output in a serial mode with Ii start bit and a stop bit bracketing the five data bits. The pwm format used has a 1.6ms
bit time with a 75% duty cycle for a '1' and a 25% duty cycle for a '0'. The start and stop bits are zeros.
th~ INTI signal. It is
R7/: A71 enables two functions that were designed to
facilitate the testing of the MM58250 quickly that might
prove useful to some users.
7-107
•
0
LI)
f8
:::liE
:::liE
Timing Specification
Input Timing
Min
Microprocessor Mode
Data Set-up Time
Data Hold Time
CS (minimum pulse width)
lACK (minimum pulse width)
0
50
250
250
Max
All of the following data is based on an oscillator frequency = 455kHz and will vary as the oscillator frequency
varies.
Units
s
ms
ns
ns
Olltput Timing
Oscillator Start up
(Subject to external
components)
Keyboard Switch Specifications
ms
9
Bounce
40 ms max
RON
500 max
ROFF
1 MOmin
Timing Diagrams
~
-.J
I
"0"
-16 CYCLES38 kHz
_42214_
"I"
- - - - - - 4 8 CYCLES-------I
OF 38 kHz
1-------l,266ms-------o_1
TI..IF/614IJ.3
Figure 2_ Bit Timing
I
SWITCH CONTACT OR CS = "0"
IROUT .
OSCILLATOR START-UP 0-9 ms
I
/
0........,:,
OATA WORO
OSCILLATOR ON
W$A
'
-------.40.51mS-----..,.~II-~1.39mS-1
1------40.09ms-----.j.11-21114
OEBOUNCE TIME
SCAN TIME
1_-------:----60.76ms----------1
TLlF16149-4
Figure 3_ 113 Transmit Cycle
.
5T;1,BIT
I
(
LSbmm
ML
i
5~IT
~I~~_~~~~WOO~~I~~~L~~~I~~~L
COLUMN DATA
ROW OATA
TLlF16149·5
Figure 4_ Data Word
7-108
-Timing Diagrams (COnlinU~d)
COLUMN OUTPUTS'
U
co
-I
COLUMN SELECT TIME
I- 26.37,..
U
C1
u
C2
-----211~S
C3
/ .......
____
-••
'ALL COLUMN OUTPUTS
GO LOW IF A SWITCH
CLOSURE IS NOT SENSED
OR IF A NON-CONTINUOUS
KEY IS SENSED.
-_I.~
TLIF/6149·6
Figure 5. Column Scan Timing
OPEN
SWITCH
CLOSED
lIlfl
~
RX WHERE
X=0,1.2,6.7
CXX=1-3
FOR RX ABOVE
J
H
n
~~n~
IROUT
RXWHERE
X=3,4,5
J
CX )(:1-3
FOR RX ABOVE
J
U
u
U
u
__~rl~______________
u
n
n
IROUT
n
n
TL/F/6149-7
Figure 6a. Typical Transmit Cycles
OPENlJUU
SWITCH
CLOSED
cx
J
I
II
IROUT
TUF/6149-&
Figure 6b. Aborted Transmit Cycle
7-109
..
•
I
Timing Diagrams (Continued)
:E
:E
II
--'nL___'. .nL__----'nL_____~I~I---------
IROUT _ _ _ _
lACK
TlIF16149-9
Figure 7. Interrupt Timing
~ ~~--------'
nL.__. .nL.__. .nL.__. .n. .________
IROUT _ _ _........
TlIFJ6149-10
Figure 8. Typical Microprocessor Transmit Cycle
MS~
MS _ _
. .
MS
R7~
R7~
8&~
R&
U
R7~
II
TLIF/6149-13
R5~
TL/FI6149-11
II
R5U
1-&.7ms-1
TLIF16149-12
Figure 9. Reset Chip to Beginning of
Transmit Cycle
Figure 10. Complete Reset
7·110
Figure 11. 6X Speed up of
Transmit Cycle
Transmitter Functions
#
I
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 '
17
18 .
19
20
21
22
23
24
25
26
27
28
29
30
31
16
8
Code
4
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
x
x
x
x
1
2
Row
3 4
5 6
7
0
Column
1 2 3
o Direct Entry
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
·x
x
x
x
x
x
x
1
1
1
1
1
1
1•
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
x
x
x
x
x
x
x
7·111
1 Direct Entry
2 Direct Entry
3 Direct Entry
4 Direct Entry
5 Direct Entry
6 Direct Entry
7 Direct Entry
8 Direct Entry
9 Direct Entry
Memory Up
On/Off
Slow Up
Slow Down
Search Up
Mute
Analog I Down
Analog I Up
Analog II Down
Analog II Up
Analog III Down
Analog III Up
Analog IV Down
Analog IV Up
Notes
x
x
x
x
x
Note 1: Three transmissions.
Note 2: Continuous transmission.
Function
x
x
Not
Defined
.
1
x
X
•
I
:IE
:IE
Typical Applications
x 8 SINGLE CONTACT
KEYPAD
I
RO
Rl
R2
R3
R4
R5
R6
R7
CO
Cl
C2
C3
-
i
CERAMIC
RESONATOR
OSC IN
5CFl
OSC OUT
I120PF
T
5=120 PF,
MM58250
±
,
...... 01
6800
I
Q~01
Q~02
1000 ,.F
V
IROUT
MS
3.911
~
'r
---9Y
BATTERY
01 : 2N6714, E01702
CFl : Murata CSB455A
Kyocera KBR455B
01,02: Xclton XC·BBO·B
NECSE303A
G.E. F501
Figure 12
9V
I
I
L ___ .J
~~~:~
--1+----1
.
.
'
J
14
15
I
1000 pF
lN914
-----~I~------...
600 pF
.":" lOOk
lN914
TLfF16149·15
Figure 13. Quick Checkout Circuit
7·112
~National
~ Semiconductor
MM58274 Microprocessor Compatible Real Time Clock
General Description
Features
The MM58274 is fabricated using low threshold metal gate
CMOS technology and is designed to operate in bus oriented microprocessor systems where a real time clock and
calendar function are required. The on-chip 32.768 kHz
crystal controlled oscillator will maintain timekeeping
down to 2.2V to allow low power standby battery operation.
This device is pin compatible with the MM58174A but continues timekeeping up to tens of years. Faster access times
are also. offered.
• Same pin-out as MM58174A
• Timekeeping from tenths of seconds to tens of years in
independently accessible registers
Applications
•
•
•
•
•
Point of sale terminals
Teller terminals
Word processors
Data logging
Industrial process control
• Leap year register
• Hours counter programmable for 12 or 24-hour operation
• Buffered crystal frequency output in test mode for easy
oscillator setting
• Data-changed flag allows simple testing fortime rollover
• Independent interrupting timer with open drain output
• Fully TTL compatible
• Low power standby operation (10,..Po at 2.2V)
• Low cost 16-pin DIP
Block Diagram
•
FIGURE 1
7-113
Operating Conditions
Absolute Maximum Ratings (Note 1)
DC Input or Output Voltage
DC Input or Output Diode Current
- 0.3Vto Voo + 0.3V
±5.0mA
-65'Cto + 150'C
Supply Voltage, Voo
6.5V
Power Dissipation, Po
500mW
Lead Temperature (Soldering, 10 seconds)
260'C
DC Input or Output Voltage
'Storage Temperature, TSTG
Electrical Characteristics Voo = 5V ± 10%, T =
Symbol
Parameter
Min
Max
Units
4.5
2.2
5.5
5.5
V
V
0
-40
Voo
85
'c
Operating Supply Voltage
Standby Mode Supply Voltage
Operating Temper~ture Range
- 40'C to
Conditions
V
+ 85'C unless otherwise stated
Min
Typ
Max
Units
V
2.0
VIH
High Level Input
Voltage (except
XTAL IN)
VIL
Low Level Input
Voltage (except
XTAL IN)
VOH
High Level Output
Voltage (OBO-OB3)
IOH = -'!-O/LA
IOH= -1.6 rnA
Voo-0.1
3.7
V
V
VOH
High Level Output
Voltage (INT)
IOH= -20/LA
(In Test Mode)
Voo-0.1
V
VOL
Low Level Output
Voltage (DBO-OB3,
INT)
IOL=20/LA
IOL= 1.6 rnA
IlL
Low Level Input Current
(ADO-AD3, DBO-DB3)
IlL
0.8
V
0.1
0.4
V
V
VIN = Vss (Note 2)
-80
/LA
Low Level Input Current
(WR,RD)
VIN = Vss (Note 2)
-190
/LA
IlL
Low Level Input Current
(CS)
VIN = Vss (Note 2)
-550
/LA
IOZH
Output High Level
Leakage Current (INT)
VOUT=VOO
2.0
/LA
100
Average Supply Current
Voo = 2.2V (Standby Mode)
Voo = 5.0V (Active Mode)
4
10
1
/LA
rnA
CIN
Input Capacitance
5
10
pF
COUT
Output Capacitance
(Outputs Disabled)
10
pF
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. All voltages referenced to ground unless,otherwise
noted.
Note 2: The DBO-083 and ADO-A03Iines all have active P-channel pull-up transistors which will source current. The CS, RD, and WR lines have internal pullup resistors to VOD'
7·114
AC Switching Characteristics
READ TIMING: DATA FROM PERIPHERAL TO MICROPROCESSOR Voo
=5V ± 0.5V, C L =100 pF
-
Commercial
Specification
Symbol
Parameter
= -40°C to + 85°C
TA
Units
Typ
Max
tAD
Address Bus Valid to Data Valid
500
850
teso
Chip Select On to Data Valid
250
425
ns
tRO
Read Strobe On to D,ata Valid
250
425
ns
Min
ns
tRW
Read Strobe Width (Note 3)
tRA
Address Bus Hold Time from Trailing Edge
of Read Strobe
0
ns
tcsH
Chip Select Hold Time from Trailing Edge
of Read Strobe
0
ns
tRH
Data Hold Time from Trailing Edge
of Read Strobe
100
250
tHZ
Time from Trailing Edge of Read Strobe
Until OIP Drivers are TRI·STATE'"
200
250
DC
WRITE TIMING: DATA FROM MICROPROCESSOR TO PERIPHERAL Voo
ns
340
=5V ± 0.5V
CommercIal
Specification
Symbol
Parameter
TA
= -40°C to +85°C
Min
tAW
Address Bus Valid to Write Strobef
(Note 4)
ns
Typ
600
Units
Max
ns
"
tcsw
Chip Select On to Write Strobe f
350
175
ns
tow
Data Bus Valid to Write Strobe f
600
400
ns
tww
Write Strobe Width
350
ns
twcs
Chip Select Hold Time Following
Write Strobe f
0
ns
tWA
Address Bus Hold Time Following
Write Strobe f
0
ns
two
Data Bus Hold Time Following
Write Strobe f
200
ns
Nota 3: Except for special case restriction: with Interrupts programmed, max read strobe width of control,reglster (ADOR 0) is 30 ms. See section on Interrupt
Programming.
Note 4: AI/limings measured to the trailing edge 01 write strobe (data latched by the trailing edge 01 WR),
Note 5: Input test waveform p~ak voltages are 2.4V and O.4V, Output Signals are measured to their 2.4V and O.4V levels.
/
.
7-115
I
•
,i:!
f8
Switching Time Waveforms
:E
:E
Read Cycle Timing (Note 5)
, . . - - - - - - - - - - - - - - - " " " ' " \ , ~---2.4V
1'----------------1
A3-AO
1----IcSD-----I
"'---0.4V
2.4V
11-------
2.4V
---+---''-t-------0.4V
03-00
---;-----------<1
Write Cycle Timing (Note 5)
_ - - - - - - - - - - - - - - - - . . . . . " ~---2.4V
A3-AO
AOORESS VALlO
1'----------------""""'1
i-------lcsw------t--tWA
"'----0.4V
03-00--+----_(1
~-----~,-~---~
Functional Description
Connection Diagram
The MM58274 is a bus oriented microprocessor real time
clock. It has the same pin·out as the MM58174A while
offering extended timekeeping up to units and tens of
years. To enhance the device further, a number of other
features have been added including: 12 or 24 hours count·
ing, a testable data·changed flag giving easy error·free
time reading and simplified interrupt control.
Dual·ln·Line Package
cs
16
Voo
iiii
15
XTALIN
Wii
14
XTALOUT
DB3
INT
DB2
ADO
DB1
A buffered oscillator signal appears on the interrupt out·
put when the device is in test mode. This allows for easy
oscillator setting when the device is initially powered up in
a system.
AD1
10
DBO
AD2
The counters are arranged as 4·bit words and can be randomly accessed for time reading and setting. The count- .
ers output in BCD (binary coded decimal) 4·bit numbers.
Any register which has less than 4 bits (e.g., days of week
uses only 3 bits) will return a logic 0 on any unused bits.
When written to; the unused inputs will be Ignored. ,
AD3
VSS
TOP VIEW
TLiB/5602.&
TLI8/5602·2
FIGURE 2
Order Number MM58274N
See NS Package N16E
7·116
Functional Description
(Continued)
Writing a logic 1 to the clock start/stop control bit resets
the internal oscillator' divider chain and the tenths of
seconds counter. Writing a logic 0 will start the clock timing from the nearest second. The time then updates every
100 ms with all counters changing synchronously. Time
changing during a read is detected by testing the data- '
changed bit of the control register after completing a
string of clock register reads.
When the chip is enabled Into test mode, the oscillator is
gated onto the interrupt output pin giving a buffered oscillator output that can be used to set the crystal frequency
when the device is installed in a system. For further information see the section on Test Mode.
Interrupt delay times of 0.1s, 0.5s, 1s, 5s, 10s, 30s or 60s
can be selected with single or repeated interrupt outputs.
The open drain output is pulled low whenever the interrupt
timer times out and is cleared by reading the control
register.
The crystal oscillator is divided down in three stages to pro·
duce a 10 Hz frequency setting pulse. The first stage is a
non· integer divider which reduces the 32.768 kHz input to
30.720 kHz. This is further divided by a 9-stage binary ripple
counter giving an output frequency of 60 Hz. A 3-stage
Johnson counter divides this by six, generating a 10 Hz output. The 10Hz clock is gated with the 32.768 kHz crystal fre·
quency to provide clock setting pulses of 15.26 "s duration.
The setting pulse drives all the time registers on the device
which are synchronously clocked by this signal. All time
data and the data-changed flag change on the falling edge
of the clock setting pulse.
Divider Chain
CIRCUIT DESCRIPTION
The block diagram in Figure 1 shows the internal structure
of the chip. The 16-pin package outline is shown in Figure 2.
Crystal Oscillator
This consists of a CMOS inverter/amplifier with an on·chip
bias resistor. Externally a 20 pF capacitor, a 6 pF-36 pF
trimmer capacitor and a crystal are required to complete
the 32.768 kHz timekeeping oscillator circuit.
Data-Changed Flag
The data-changed flag is set by the clock setting pulse to
indicate that the time data has been altered since the
clock was last read. This flag occupies bit 3 of the control
register where it can be tested by the processor to sense
data-changed. It will be reset by a read of the control
register. See the section, "Methods of Device Operation",
for suggested clock reading techniques using this flag.
The 6 pF-36 pF trimmer fine tunes the crystal load impedance, optimizing the oscillator stability. When properly
adjusted (i.e., to the crystal frequency of 32.768 kHz), the
circuit will display a frequency variation with voltage of
less than 3 ppmlV.
(SEE APPLICATIONS NOTES)
DB3
R1
3.3k
DB2
DB1
~
iii:
DBa
'"~
"'
AD3
AD2
AD1
ADO
ifjf
TL/BI5602-3
* Resistor is only used with Ni·CAD cells. Omit for lithium, silver or other primary cells.
FIGURE 3. Typical System Connection Diagram
7-117
Functional Description
(Continued)
When 24·hour mode is programmed, the tens of hours reg·
Ister reads out two bits of data and the two most signlfl·
cant bits are set to logic O. There is no AM/PM Indication
and bit 1 of the clock setting register will read out a logic O.
Seconds Counters
There are three counters for seconds:
In both 12/24·hour modes, the units of hours will read out
four active data bits. 12 or 24-hour mode Is selected by bit 0
of the clock setting register; logic 0 for 12·hour mode, logic 1
for 24-hour mode.
a) tenths of seconds
b) units of seconds
c) tens of seconds.
The registers are accessed at the addresses shown in
Table I. The tenths of seconds register is reset to 0 when
the clock start/stop bit (bit 2 of the control register) is set
to logic 1. The units and tens of seconds are set up by the
processor, giving time setting to the nearest second. All
three registers can be read by the processor for time
output.
Days Counters
There are two days counters:
a) units of days
b)' tens of days.
The days counters will count up to 28, 29, 30 or 31 depend·
ing on the state of the months counters and the leap year
counter. The microprocessor has full read/write access to
these registers.
Minutes Counters
There are two minutes counters:
a) units of minutes
Months Counters
b) tens of minutes.
There are two months cou.nters:
Both registers may be read to or written from as required.
a) units of months
Hours Counters
b) tens of months.
There are two hours counters:
Both these counters have full read/write access.
a) units of hours
b) tens of hours.
Years Counters
Both counters may be accessed for read or write opera·
tions as desired.
There are two years
counte~s:
a) units of years
In 12·hour mode, the tens of hours register has only one ac·
tive bit and the top three bits are set to logic O. Data bit 1 of
the clock setting register is the AM/PM indicator; logic 0
indicating AM, logic 1 for PM.
b) tens of years.
Both these counters have full read/write access. The
years will count up to 99 and roll over to 00.
TABLE I. Address Decoding of Real·Tlme Clock Internal Registers
-
)
Register Selected
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Control Register
Tenths of Seconds
Units Seconds
Tens Seconds
Units Minutes
Tens Minutes
Units Hours
Tens Hours
Units Days
Tens Days
Units Months
Tens Mon\hs
Units Years
Tens Years.
Day of Week
Clock Setting/
,Interrupt Register,s
Address (Binary)
AD3 AD2 AD1 ADO
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(Hex)
Access
0
1
2
3
4
5
Split Read and Write
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
6
7
8
9
A
B
C
D
E
F
•
7·118
Functional Description
(Continued)
Dily of Week Counter
The day of week counter increments as the time rolls from
23:59 to 00:00 (11:59 PM to 12:00 AM in 12-hour mode). It
counts from 1 to 7 and rolls back to 1. Any day of the week
may be specified as day 1.
The AM/PM indicator returns a logic 0 for AM and a logic 1
for PM. It is clocked when the hours counter rolls from
11 :59 to 12:00 in 12-hour mode. In 24-hour mode this bit is
set to logic O.
The 12/24·hour mode set determines whether the hours
counter counts from 1 to 12 or from 0 to 23. It also controls
the AMI PM indicator, enabling it for 12·hour mode and
forcing it to logic 0 for the 24·hour mode. The 12/24-hour
mode bit is set to logic 0 for 12-hour mode and it is set to
logic 1 for 24·hour mode.
Clock Setting Reglsterllnterrupt Register
The interrupt select bit in the control register determines
which of these two registers is accessible to the proces·
sor at address 15. Normal clock and interrupt timing
operations will always continue regardless of which regis·
ter is selected onto the bus. The layout of these registers
is shown in Table II.
IMPORTANT NOTE: Hours mode and AM/PM bits cannot
be set in the same write operation. See the section on
Initialization (Methods of Device Operation) for a suggested setting routine.
The clock setting register is comprised of three separate
functions:
All bits in the clock setting register may be read by the
processor.
a) leap year counter: bit.s 2 and 3
The interrupt register controls the operation of the timer
for interrupt output. The processor programs this register
for single or repeated interrupts at the selected time
intervals.
b) AM/PM indicator: bit 1
c) 12/24·hour mode set: bit 0 (see Table IIA).
The leap year counter is a 2·stage binary counter which is
clocked by the months counter. It changes state as the
time rolls over from 11:59 on December 31 to 00:00 on
January 1.
The lower three bits of this register set the time delay
period that will occur between interrupts. The time delays
that can be programmed and the data words that select
these are outlined in Table liB.
The counter should be loaded with the 'number of years
since last leap year' e.g., if 1980 was the last leap year, a
clock programmed in 1983 should have 3 stored in the leap
year counter. If the clock is programmed during a leap
year, then the leap year counter should be set to O. The con·
tents of the leap year counter can be read by the !,P.
Data bit 3 of the interrupt register sets for either single or
repeated interrupts; logic 0 gives single mode,loglc 1 sets
for repeated mode.
Using the Interrupt is described in the Device Operation
section.
TABLE IIA. Clock Setting Register Layout
Data Bits Used
DB3 DB2 DB1 DBD
Function
Leap Year Counter
AMIPM Indicator (12-Hour Mode)
X
X
X
X
12/24-Hour Select Bit
Comments
Access
o Indicates a Leap Year
R/W
R/W
O=AM 1 =PM
oin 24-Hour Mode
0= 12·Hour Mode
1 = 24·Hour Mode
TABLE liB. Interrupt Control Register
Function
Comments
Control Word
DB3 DB2 DB1 DBD
No Interrupt Interrupt output cleared,
X
0
0
D
startlstop bit set to 1.
1
0.1 Second
0/1
0
0
0.5 Second
0/1
1
0
0
1 Second
1
1
0/1
0
DB3 = D for single interrupt
0
5 Seconds
011
1
0
DB3 = 1 for repeated interrupt
011
1
10 Seconds
1
0
1
30 Seconds
0/1
1
0
60 Seconds
011
1
1
1
Timing Accuracy: single interrupt mode (all time delays): ± 1 ms
Repeated Mode: ± 1 ms on initial timeout, thereafter synchronous
with first interrupt (i.e., timing errors do not accumulate).
7-119
R/W
•
i
~
Functional Description
(Continued)
A logic 0 in the interrupt select bit makes the clock setting
register available to the processor. A logic 1 selects the in·
terrupt register.
Control Register
There are three registers which control different opera·
tions of the clock:
The Interrupt start/stop bit controls the runnfng of the'in:
terrupt timer. It Is programmed in the same way as the
clock start/stop bit; logic 1 to halt the interrupt and reset
the timer, logiC 0 to start interrupt timing.
a) the clock setting register
b) the interrupt register
c) the control register.
When no Interrupt is programmed (interrupt control regis·
ter setto 0), the interrupt start/stop bit is automatically set
to a logic 1. W.hen any new Interrupt is subsequently programmed, timing will not commence until the start/stop
bit Is loaded with '0.
The clock setting and interrupt registers both reside at
address 15, access to one or the other being controlled by
the interrupt select bit; data bit 1 of the control register.
The clock setting register programs the timekeeping of
the clock. The 12/24-hour mode select and the AM/PM in·
dicator for 12·hour mode occupy bits 0 and 1, respectively.
Data bits 2 and 3 set the leap year counter.
In the single interrupt mode, interrupt timing stops when a
timeout occurs. The processor restarts timing by writing
logiC 0 into the start/stop bit.
The interrupt regisier controls the operation of the inter·
rupt timer, selecting the required delay period and either
single or repeated interrupt.
In repeated interrupt mode the interrupttimer continues to
count with no intervention by the processor necessary.
Interrupt timing may be stopped in either mode by writing
a logic 1 into the Interrupt start/stop bit. The timer Js reset
and can be restarted in the normal way, giving a full time
delay period before the next interrupt.
The control register is responsible for controlling the
operations of the clock and supplying status information
to the processor. It appears as two different registers; one
with write only access and one with read only access.
In general, the control register is set up such that writing
O's into it will start anything that is stopped, pull the clock
out of test mode and select the clock setting registerpnto
the bus. In other words, writing 0 'will maintain normal
clock operation and restart Interrupt timing, etc.
The write only register consists of a bank of four latches
which control the internal processes of the clock.
The read only register contains two output data latches
which will supply status information for the processor.
Table III shows the mapping olthe various control latches
and status flags in the control register. The control
register is located at address O.
The read only portion of the control register has two status
outputs:
Since the MM58274 keeps real time, the time data
changes asynchronously with the processor and this may
occur while the processor is reading time data out of the
clock.
The write only portion of the control register contains four
latches:
A logic 1 written into the test bit puts the device into test
mode. This allows setting of the oscillator frequency as well
as rapid testing of the device registers, if required. A more
complete description is given in the Test Mode section. For
normal operation the test bit Is loaded with logic O.
Some method of warning the processor when the time
data has changed must thus be included. This Is provided
f,or by the data·changed flag located in bit 3 of the control
register. This flag is set by the clock setting pulse which
also clocks the time registers. Testing this bit can tell the
processor whether or not the time has changed. The flag is
cleared by a read of the control register but not by any
write operations. No other register read has any effect on
the state of the data'changed flag.
The clock start/stop bit stops the timekeeping olthe clock
and resets to 0 the tenths of seconds counter. The time of
day may then be written into the various clock registers
and the clock restarted synchronously with an external
time source. Timekeeping is maintained thereafter.
A logic 1 written to the start/stop bit halts clock timing.
Timing is restarted when the start/stop bit is written with a
10glcO.
Data bit 0 is the interrupt flag. This flag Is set whenever the
ihterrupt timer times out, pulling the interrupt output low.
In a polled interrupt routine the processor cim test this
flag to determine if the MM58274 was the interrupting
device. This interrupt flag and the interrupt output are both
. cleared by a read of the control register.
The interrupt select bit determines which of the two
registers mapped onto address 15 will be accessed when
this address is selected.
TABLE III. The Control Registe~ Layout
Access (addrO)
DB3
DB2
DB1
DBD
Read From:
Data·Changed Flag
0
0
Interrupt Flag
Write To:
Test
0= Normal
1 = Test Mode
Clock Start/Stop
Interrupt Select
Interrupt Start/Stop
O=Clock Run 0= Clock Setting Register ' 0 == Interrupt Run
1 = Cloc~ Stop
1 = Interrupt Register
1 = Interrupt Stop
7·120
Functional Description
(Continued)
Both of the flags and the interrupt output are reset by the
trailing edge of the read strobe. The flag information is
held latched during a control register read, guaranteeing
that stable status information will always be read out by"
the processor.
steps are recommended when the device is set up (all
numbers are ,decimal):
1) Disable interrupt on the processor to allow oscillator
setting. Write 15 into the control register: The clock and interrupt start/stop bits are set to 1, ensuring that the clock
and interrupt timers are both halted. Test mode and the interrupt register are selected.
Interrupt timeout is detected and stored internally if it
occurs during a read of the control 'register, the interrupt
output will then go low only after the read has been
completed. ,
2) Write 0 to the interrupt register: Ensure that there are no
interrupts programmed and that the oscillator will be
gated onto the interrupt output.
A clock setting pulse occurring during a control register
read will not affect the data-changed flag since time data
read out before or after the control read will not be af·
fected by the time change.
3) Set oscillator frequency: All timing has been halted and
the oscillator is buffered out onto the interrupt line.
4) Write 5 to the control register: The clock is now out of
test mode but is stili halted. The clock setting register is
now selected by the interrupt select bit.
METHODS OF DEVICE OPERATION
Test Mode
5) Set 12/24 Hours Mode: Write to the clock setting
register to select the hours counting mode required.
National Semiconducior uses test mode for functionally
testing the MM58274 after fabrication and again after
packaging. Test mode can also be used to set up the
oscillator frequency when the part is first commissioned.
6) Load Real·Time Registers: All time registers (including
Leap Years and AM/PM bit) may now be loaded in any
order. Note that when writing to the clock setting register
to set up Leap Years and AM/PM, the Hours Mode bit must
not be altered from the value programmed in step 5.
Figure 4 shows the internal clock connections when the
device is written into test mode. The 32.768 kHz oscillator
is gated onto the interrupt output to provide a buffered output for initial frequency setting. This signal is driven from
a TRI-STATEoutput buffer, enabling easy oscillator setting
in systems where interrupt is not normally used and there
is no external resistor on the pin.
7) Write 0 to the control register: This operation finishes
the clock initialization by starting the time. The final can·
trol register write should be synchronized with an external
time source.
If an interrupt is programmed, the 32.768 kHz output is
switched off to allow high speed testing of the interrupt
timer. The interrupt output will then function as normal.
In general, timekeeping should be halted before the time
data is altered in the clock. The data can, however, be
altered at any time if so desired. Such may be the case if
the user wishes to keep the clock corrected without having to stop and restart it; i.e., winterlsummer time chang·
ing can be accomplished without halting the clock. This
can be done in' software by sensing the state of the datachanged flag and only altering time data just after the tilJle
has rolled over (data·changed flag set).
The clock start/stop', bit can be used to control the fast
clocking of the time registers as shown in Figure 4.
MM58274 Initialization
When it is first installed and power is applied, the device
will need to be properly initialized. The following operation
CLOCK
START/STOP
BIT
XTALIN
XTAL OUT - - - - . .
INT OUT
FIGURE 4_ Test Mode Organization
7-121
~
:IE
:IE
Functional Description
(Continued)
Reading the Time Registers
Using the data-changed flag technique supports microprocessors with block move facilities, as all th~ necessary
time data may be read sequentially and then tested for validity as shown below.
Single Interrupt Mode:
When appropriate, write 0 or 2 to the control register to
restart the interrupt timer.
Repeated Interrupt Mode:
1) Read the control register, address 0: This is a dummy
read to reset the data-changed flag (DCF) prior to reading
the time registers.
2) Read time registers: All desired time registers are read
out in a block.
Timing continues, synchronized with the control register
write which originally started interrupt timing. No further
intervention is necessary from the prpcessor to maintain
timing.
3) Read the control register and test DCF: If DCF is cleared
(logic 0), then no clock setting pulses have occurred since
step 1. All time data is guaranteed good and time reading is
complete.
In either mode interrupt timing can be stopped by writing 1
into the control register (interrupt startlstop set to 1). Timing for the full delay period recommences when the Interrupt startlstop bit is again loaded with 0 as norma,l.
If DCF is set (logic 1), then a time change has occurred
since step 1 and time data may not be consistent. Repeat
steps 2 and 3 until DCF is clear. The control read of step 3
will have reset DCF, automatically repeating the step 1
action.
Interrupt Programming
IMPORTANT NOTE: Using the interrupt timer places a
constraint on the maximum Read Strobe width which may
be applied to the clock. Normally all registers may be read
from with a tRW down to DC (i.e., CS and RD held continuously low). When the interrupt timer is active however,
the maximum read strobe width that can be applied to the
control register (Addr 0) is 30 ms.
The interrupt timer generates interrupts at time Intervals
which are programmed Into the interrupt register. A single
Interrupt after delay or repeated interrupts may be programmed. Table liB lists the different time delays and the'
data words that select them in the interrupt register.
This restriction is to allow the interrupt timer to properly
reset when it times out. Note that it only affects reading of
the control register-all other addresses in the clock may
be accessed with DC read strobes, regardless of the state
of the interrupt timer. Writes to 'any address are unaffected.
Once the Interrupt register has been used to set up the delay time and to select for single or repeat, it takes no further
part In the workings of the interrupt system. All activity by
the processor then takes'p'ace,'n the control register.
NOTES ON AC TIMING REQUIREMENTS
Although the Switching Time Waveforms show Microbus
control signals used for clock access, this does not
preclude the use of the MM58274 in other non'Microbus
systems. Figure 5 is a simplified logic diagram showing
how the control signals are gated internally to control access to the clock registers, From this diagram it Is clear that
CS could be used to generate the internal data transfer
strobes, with RD and WR inputs set up first. This situation is
illustrated in Figure 6.
Initializing:
1) Write 3 to the control register (ADO): Clock timing continues, interrupt register selected and interrupt timing
stopped.
2) Write Interrupt control word to address 15: The interrupt register is loaded with the correct word (chosen from
Table liB) for the time delay required and for single or
repeated Interrupts.
.
The internal data busses of the MM58274 are fully CMOS,
contributing to the flexibility of the control inputs. When
determining the suitability of any given control signal pattern for the MM58274, the timing specifications in AC
Switching Characteristics should be examined. As long as
these timings are met (or exceeded) the MM58274 will function correctly.
3) Write 0 or 2 to the control register: Interrupt timing com,mences. Writing 0 selects the clock setting register onto
the data bus; writing 2' ~eaves the Interrupt register
selected. Normal timekeeping remains unaffected.
On Interrupt:
When the MM58274 is connected to the system via a pe-,
ripheral port, the freedom from timing constraints allows
for very simple control Signal generation, as in Figure 7.
For reading (Figure 7a), Address, CS and RD may be activated simultaneously and the data will be available at
the port afte~ tAD-max (850 ns). For writing (Figure 7b), the
address and data may be applied simultaneously and CS
and WR strobed together.
Read the control register and tesi for Interrupt Flag (bit 0).
If the flag Is cleared (logic 0), then the device is not the
source of the Interrupt.
'
If the flag is set (logic 1), then the clock did generate an Interrupt. The flag Is reset and the interrupt output Is cleared by
the control register read that was used to test for Interrupt.
7-122
Functional Description
(Continued)
110 BUFFERS
..
""
DATA BUS
0"
EXTERNAL
SIGNALS
READ
WRITE DATA BUS
rl>
~
·READ DATA BUS
(INTERNAL
..II TRI·STATE BUS)
~
I
LATCH
DATA
STROBE
WRITE
WR
..,..
•p
ADDRESS BUS
ADDRESS
DECODER
r-}
~1
f-+:
"'III
,.
REAl·TIME
COUNTER LATCHES
ACCESS
ENABLE
+
~-.ADDRESS
ENABLES
f-+ I ~~~~~::S
MM5B274
f:::J
TLlB/5602·7
FIGURE 5. MM58274 Microprocessor Interface Diagram'
ADDRESS
BUS
==x
C
•
I
\
\
Viii
DATA
BUS
WRITE ACCESS CYCLE
'---I
'---I
CS
iiii
X
READ ACCESS CYCLE
@
DATA
f
{
WRITE
DATA
}TLIBI5602-S
FIGURE 6. Valid MM58274 Control Signals USing Chip Select Generated Access Strobes
i
Functional Description
(Continued)
:E
:E
ADDR:~~ _ _ _",X",___A_D_DR_E_SS_1_ _ _X,,___AD_D_R_ES_S_2_ _ _X",___
r
I
iiii
D:J~-------4~~~~~~~~~~~V_A_LlD_D_A_m_l_~~~""~~__V_A_LlD_D_A_m_2_ _~
TL/F15602·11
a. Port Generated Read Access-2 Addresses Read Out
ADDRESS
BUS
X
X
ADDRESS 1
\J
\..J
CS
DATA
BUS
(
X
WRITE DATA 1
X
\J
\J
\
WR
ADDRESS 2
WRITE DATA 2
)
TLlF/5602-12
b. Port Generated Write Access-2 Addresses Written To
FIGURE 7. Simple Port Generated Control Signals
7·124
Functional Description
(Continued)
APPLICATION NOTES
2) Read control register ADO: This is a dummy read to
reset the data-changed flag.
Time Reading Using Interrupt
3) Read control register ADO until data-changed flag is
set.
In systems such as point of sale terminals and data loggers, time reading is usually only required on a random demand basis. Using the data-changed flag as outlined in
the section on methods of operation is ideal for this type
of system. Some systems, however, need to sense a
change in real time; e.g., industrial timers/process controllers, TVNCR clocks, any system where real time is
displayed.
Time Reading with Very Slow Read Cycles
If a system takes longer than 100 ms to complete reading
01 all the necessary time registers (e.g., when CMOS processors are used) or where high level interpreted language
routines are used, then the data-changed flag will always
be set when tested and isol no value. In this case, the time
registers .themselves must be tested to ensure data
accuracy.
In single interrupt mode the processor is responsible for
initiating each timing cycle and the timed period is accurate to ± 1 ms.
The technique below will detect both time changing
between read strobes (I.e., between reading tens of
minutes and units of hours) and also time changing during
read, which can produce invalid data.
In repeated Interrupt mode the period from the initial processor start to the first timeout is also only accurate to ± 1 ms.
The following interrupts maintain accurate delay periods
relative to the first timeout. Thus, to utilize interrupt to control time reading, we will use repeated interrupt mode.
1) Read and store the value of the lowest order time
register required.
2) Read out all the time registers required_ The registers
may be read out in any order, simplifying software
requirements.
In repeated mode the timt;! period between interrupts is exact, which means that timeouts will always occur at the
same point relative to thd internal clock setting pulses. The
case for 0.15 interrupts is shown in Figure A-1. The same is
true for other delay periods, only there will be more clock
setting pulses between each interrupt timeout. If we set up
the interrupt timer 50 that interrupt always times out just
after the clock setting pulse occurs (Figure A-2), then there
is 'no need to test the data-changed flag as we know that the
time data has just changed and will not alter again for
another 100 ms.
3) Read the lowest order register and compare it with the
value stored previously in step 1. If it is still the same, then
all time data is good. If it has changed, then store the new
value and go back to step 2.
In general, the rule is that the lirst and last reads must both
be 01 the lowest order time register. These two values can
then be compared to ensure that no change has occurred.
This technique works because for any higher order time
register to change, all the lower order registers must also
change. If the lowest order register does not change, then
no higher order register has changed either.
This can be achieved as outlined below:
1) Follow steps 1 and 2 of the section on interrupt programming. In step 2 set up for repeated interrupt.
I
n
_ 1 , 16 i'S
-100ms-
~
PULSES
_""~_ _ _ _ _""~_ _ _ _ _" ' I ' -_ _
-tDELAy-j
-tDELAy-j
UI
INTERRUPT
O/P
INTERRUPT
SERVICED
U'I
INTERRUPT
SERVICED
TLfB/5602·7
FIGURE A-1. Time Delay from Clock Setting Pulses to Interrupt is Constant
1----:100ms~
J
.;::
4) vyrite 0 or 2 to control register. Interrupt timing
commences.
The interrupt timer on the MM58274 can generate interrupts synchronously with the time registers changing,
using software to provide the initial synchronization.
INTERNAL
CLOCK
SETTING
PULSES
s:
s:
~
~
u
L
TLfB15602·8
FIGURE A·2. Interrupt Timer Synchronized with Clock Setting Pulses
7-125
•
~ r---------------------------------------------------~------------------------------I
!
~
~National
~ Semiconductor
MM58341 High Voltage Display Driver
General Description
Features
The MM58341Is a monolithic MOS Integrated circuit utilizing CMOS metal gate low threshold P and N-channel
devices. It is available both in 40-pin molded dual-in-line
packages or as dice. The MM58341 is particularly suited
for driving high voltage (35V max) vacuum fluorescent (VF)
displays, (e.g., a 32-digit alphanumeric or dot matrix
display).
-
•
•
•
•
•
•
•
•
•
Applications
•
•
•
•
•
•
Direct Interface to high voltage display
Serial data Input
No external resistors required
Wide display power supply operation
LSTTL compatible inputs
Software compatible with NS display driver family
Compatible with alphanumeric or dot matrix displays
Display blanking control input
Simple to cascade
COPSTM or microprocessor-driven displays
Instrumentation readouts
Industrial control indicator
Digital clock, thermostat, counter, voltmeter
Word processor text displays
Automotive dashboards
Block and Connection Diagrams
OUTPUT
32
OUTPUT
Dual-In-Line Package
1
1+--i+-VDlS
Vss lOY)
OUTPUT 17
OUTPUT 16
OUTPUT 15
OUTPUT 14
OUTPUT 13
OUTPUT 12
OUTPUT 11
OUTPUT 10
OUTPUT 9
OUTPUT 8
OUTPUT 7
OUTPUT 6
OUTPUT 5
OUTPUT 4
OUTPUT 3
OUTPUT 2
OUTPUT 1
VO/s
CLOCK -#-1"
Vno 15V)
10
11
12
13
14
15
16
17
18
19
2D
MM58341
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OUTPUT 18
OUTPUT 19
OUTPUT 20
OUTPUT 21
OUTPUT 22
OUTPUT 23
OUTPUT 24
OUTPUT 25
OUTPUT 26
OUTPUT 27
OUTPUT 28
OUTPUT 29
OUTPUT 30
OUTPUT 31
OUTPUT 32
BLANKING CONTROL
ENABLE
DATAOUT
DATA IN
CLOCK
TOP VIEW
ENABLE - - - -.....
TLlF/56C3-1
FIGURE 1
TL/F/5603-2
FIGURE 2
Order Number MM58341N
See NS Package N40A
7-126
s::
Absolute Maxiinum Ratings
Operating Conditions
Voltage at Any Input Pin
Voltage at Any Display Pin
Supply Voltage (Voo)
Vss=OV
Display Voltage (V OIS )
Temperature Range
Min
Voo + 0.3Vto Vss - 0.3V
Voo to Voo - 36.5V
36.5V
Voo + IVolsl
-65·Cto +150·C
. Storage Temperature
500mWat +85·C
Power Dissipation
130·C
Junction Temperature
260·C
Lead Temperature (Soldering, 10 seconds)
DC Electrical Characteristics TA =
Symbol
- 40·C to
Parameter
Max
4.5
-30
-40
5.5
-10
+85
I
Units
V
V
·C
+ 85·C, VOO = 5V ± 0.5V, Vss = ov unless otherwise specified
Conditions
Min
Typ
Max
Units
Power Supply Currents
100
VIN=VSSorVoo, VSS= OV, VOIS Disconnected
150
p.A
lOIS
Voo = 5.5V, Vss = OV, VOIS = - 30V,
All Outputs Low
10
mA
Input Logic Levels
DATA IN, CLOCK
ENABLE, BLANK
VIL
Logic '0'
VIH
Logic '1'
0.8
(Note 1)
V
V
2.4
Data Output Logic Levels
VOL
Logic '0'
lOUT '" 400 p.A
VOH
Logic '1'
IOUT= -10p.A
VOH
Logic '1'
liN
Input Currants
DATA IN, CLOCK
ENABLE, BLANK
CIN
Input Capacitance
DATA IN, CLOCK
ENABLE, BLANK
Display Output Impedances
V oo =5.5V, Vss=OV
ROFF
Output Off (Figure 3a)
VOIS = -10V
VOIS = -20V
VOIS = -30V
RON
Output On (Figure 3b)
Vols= -10V
VOIS = -20V
VOIS = -30V
VOOL
Display Output Low Voltage
Note 1: 74LSTILVOH=2.7V @IOUT=
-400~,
0.4
V
Voo-0.5
V
IOUT= -500p.A
2.8
V
VIN = OV or VOO
-10
55
60
65
700
600
500
Voo = 5.5V, lOUT = Open Circuit,
-30VsV Dls s -10V
TILVOH=2.4V@ IOUT=
VOIS
10
p.A
15
pF
250
300
400
k!l
k!l
k!l
800
750
680
!l
!l
V ols +2
V
•
{l
-400~.
-
7·127
'P"
~
18
::Ii!
::Ii!
AC Electrical CharacteristicsTA =
-40·Cto
Parameter
Conditions
Clock Input
Frequency, fc
High Time, tH
Low Time, tL
Data Input
Set-Up Time, tos
Hold Time, tOH
+ 85·C, Voo;;, 5V ±0.5V
Min
Typ
Max
Units
800
300
300
kHz
ns
ns
100
100
ns
ns
100
100
ns
ns
(Notes 3 and 4)
-.
Enable Input
Set-Up Time, tES
Hold Time, tEH
Data Output
Clock Low to Data Out
Tlme,tcoo
CL =50 pF
. 500
ns
Note 2: Nole that, lor timing purposes, the signals ENABLE and BLANK can be considered to be totally independent 01 each other.
Note 3: AC inpul wavelorm specllicatlQn lor lest purpose: t r ,,20 ns, 11,,20 ns, f= BOO kHz, 50% ± 10% duty cycle.
Note 4: Clock Inpul rise and lall limes musl nol exceed 5 ps.
Functional Description
This product Is specifically designed to drive multiplexed
or non·multlplexed high voltage alphanumeric or dot
matrix vacuum fluorescent (VF) displays. Character
generation Is done externally In the microprocessor, with a
serial data path to the display driver. The MM58341 uses
three signals, DATA IN, CLOCK and ENABLE, where
ENABLE acts as an external load signal. Display blanking
can be achieved by means of the BLANKING CONTROL
Input. and a logic '1' will turn off all sections of the display.
A block diagram of the MM58341 Is shown In Figure 1.
Figure 4 demonstrates the critical timing requirements
between CLOCK and DATA IN for the MM58341.
When the chip first powers on, an internal reset is generated, resetting all registers and latches. The chip returns
to normal operation on application of ENABLE, and so all
interface signals should be inactive at power on.
In Figure 5, the ENABLE signal acts as an envelope, and
only while this signal is at a logic '1' does the circuit accept CLOCK input signals. Data is transferred and shifted
in the internal shift register on the rising clock edge, I.e.,
'0'-'1' transition. When the ENABLE signal goes low, the
contents of the shift registers are latched, and the display
'will show new data. During data transfer, the display will
show old data. DATA OUT Is also provided on the
MM58341, being output on the failing edge. At any time,
the display may be blanked under processor control, using
the BLANKING CONTROL Input.
Figure 2 shows the pinout of the MM58341 device, where
output 1 (pin 18) Is equivalent to bit 1 (I.e., the first bit of
data to be loaded Into the shift register following ENABLE
high). A logic '1' at the Input will turn on the corresponding
• display dlglt/segmentldotoutput.
A significant reduction In discrete board components
can be achieved by use of the MM58341, because external
pull-down resistors are not required. Due to the nature of
the output stage, both its on and off Impedance values
~ary as a function of the display voltage applied. However,
Figures 3a and 3b show that this output Impedance will remain constant for a fixed value of display voltage.
Figure 6 shows a schematic diagram of a microprocessorbased system where the MM58341 Is used to provide the
grid drive for a32-dlglt 5 x 7 dot matriX vacuum fluorescent
(V F) display. The anode drive In this example Is provided by
another member of the high voltage display driver family,
namely the MM58348, which does not !requlre an externally generated load signal.
7-128
Functional Description (Continued)
+85·C
34.5
-40·C
S 24.5
~
+
~ 14.5
"""0-_-'-_ _-'-_ _-'-_ _-'-_ _......._ _....1.... . lOUT
100
200
300
400
600
500
(pAl
TL/FI5603·,3
FIGURE 3a. Output Impedance Off
AT60011+2S·TYPICC, ALVDlS = -20V
1.0
400D
MAX
AT -40·C.
VDIS = -30V
§!:
~ 0.5
o _=_--''--__......L_ _ _--'-_ _ _..J..._ _ _ _
o
O.S
1.S
IGUT(mAI
TlfF/5603-4
FIGURE 3b. Output Impedance On
Timing Diagrams
TL/FJ5603-5
For the purposes of AC measuremenls, V,H = 2.4V, VIL = O.BV.
FIGURE 4. Clock and Data TimIngs
CLOCK SO%
-I---I--+""'c--I--+-~.---_#---'tr_---
DATAIN SD% :E)E~~~=aE====~E====3E=
MmOUT SO%=t~~~~~~====~E:====:3~==:
IES:
IEH
ENABLE 50%
______..I'
_____
~
,r-----~\
~\,,
~,,
B~~:~~~ SO%:::::::::::::::::J~~---~\~~~~:.:.:.:.:.:.:.:.=_=_::_=_
VOD---TYPI
CAL
DISPLAY
OUTPUT
VDlS---, TLiF/S603-6
FIGURE 5. MM58341 Timings (Data Format)
7·129
•
~
Typical Application
:IE
:IE
32-DlGIT MULTIPLEXEO
5 x 7 DOT MATRIX
VACUUM FLUORESCENT
(VF) OISPLAY
I
I
35 ANODES
32 GRIDS
------
~------
MM58348
DISPLAY DRIVER
CLOC K8
MM58341
DISPLAY DRIVER
DATA1~
DATA 8
CLOCK 1
1
ENABLE 1
8LAN~
1
~
MICROPROCESSOR
DATA
OUT 1
TL/FI5603·7
FIGURE 6. Microprocessor-Controlled Word Processor
7-130
.
~ Semiconductor
~National
MM58342 High Voltage Display Driver
General Description
Features
The MM58342 is a monolithic MOS integrated circuit utilizing CMOS metal gate low threshold P and N·channel
devices. It is available both in 28-pin molded dual-in-line
packages or as dice. The MM58342 is particularly suited
fordriving high voltage (35V max) vacuum fluorescent (VF)
displays (e.g., a 20-digit alphanumeric or dot matrix
display).
• Direct interface to high voltage display
Applications
Serial data input
No external resistors required
Wide display power supply operation
LSTTL compatible inputs
Software compatible with NS display driver family
Compatible with alphanumeric or dot matrix displays
Display blanking control input
• Simple to cascade
• COPSTM or microprocessor-driven displays
•
•
•
•
•
•
•
•
..
•
•
•
Instrumentation readouts
Industrial control indicator
Digital clock, thermostat, counter, voltmeter
Word processor text displays
Automotive dashboards
Block and Connection Diagrams
OUTPUT"
20
OUTPUT
1
Dual·ln·Line Package
BLANKING
CONTROL
VDlS
DATA
IN
DATA
OUT
CLOCK
ENABLE
Vss 10Vl
2B
OUTPUT 12
OUTPUT 11
27
OUTPUT 13
OUTPUT 10
26
OUTPUT 14
OUTPUT 9
25
OUTPUT 15
OUTPUT B
24
OUTPUT 16
OUTPUT 7
23
OUTPUT 17
OUTPUT 6
22
OUTPUT 1B
OUTPUT 5
21
OUTPUT 19
OUTPUT 4
20
OUTPUT 20
OUTPUT 3
10
19
BLANKING CONTROL
OUTPUT 2
11
1B
ENABLE
OUTPUT 1
12
17
DATA OUT
Vms
13
16
DATA IN
VoD 15Vl
14
15
CLOCK
TOP VIEW
FIGURE2
FIGURE 1
Order Number MM58342N
See NS Package N28B
7-131
TLJF17925·2
•
Absolute Maximum Ratings
Operating Conditions
Voltage at Any Input Pin
Supply Voltage (V OO)
VSs=OV
Display Voltage (V OIS)
Max
Units
4.5
5.5
V
-30
-40
-10
V
·C
Min
Voo + 0.3Vto Vss -0.3V
Voltage at Any Display Pin
VOO to VOO - 36.5V
36,5V
Voo + IVols'l
Storage Temperature
Power Dissipation
Junction Temperature
+85
,
260·C
Lead Temperature (Soldering, 10 seconds)
,
DC Electrical Characteristics TA =
- 40·C to + 85··C, VOO = 5V ± 0.5V, VSS =
Parameter
Symbol
Temperature Range
-65·Cto + 150·C
500mWat +85·C
130·C
Conditions
ov unless otherwise specified
Min
Typ
M/lx
Units
Power Supply Currents
100
VIN = Vss or V oo , Vss = OV, VDlS Disconnected
150
p.A
I DIS
V oo=5.5V, VSS= OV, VDls= -30V
All Outputs Low
10
mA
0.8
V
Input Logic Levels
DATA IN, CLOCK
ENABLE, BLANK
VIL
Logic '0'
VIH
Logic '1'
(Note 1)
V
2.4
Data Output Logic Levels
VOL
Logic '0'
IOUT=400p.A
VOH
Logic'1'
IOUT= -10p.A
Voo-0.5
VOH
Logic '1'
lOUT = - 500 p.A
2.8
liN
Input Currents
DATA IN, CLOCK
ENABLE, BLANK
VIN = OV or Voo
-10
C IN
Input Capacitance
DATA IN, CLOCK
ENABLE, BLANK
Display Output Impedances
V oo =5.5V, Vss=OV
ROFF
Output Off (Figure 3a)
V Dl s=-10V
V OIS = -20V
V DlS = -30V
RON
,
Output On (Figure 3b)
0.4
Display Output Low Voltage
Notal: 74LSTTL VOH =2.7V
@
V oo =5.5V, IOUT=Open Circuit,
-30VsV Dls s -10V
IOUT= -400 "A, TTL VOH=2.4V
@
V
700
600
500
VDlS= -30V
VOOL
V
55
60
65
V OIS = -10V
V DlS =' -20V
IOUT= -400"A,
7·132
VOIS
V
10
p.A
15
pF
250
300
400
kO
800
750
680
0
V ols +2
V
\<0
kO
0
0
AC Electrical Characteristics T;.. =
Parameter
- 40'C to
i:
i:
+ 85'C, Voo = 5V ± 0.5V
Conditions
Min
8J
Typ
Max
Units
~
N
Clock Input
Frequency, f c
High Time, tH
Low Time, tL
(Notes 3 and 4)
300
300
kHz
ns
ns
. Data Input
Set-Up Time, tos
Hold Time, tOH
100
100
ns
ns
Enable Input
Set-Up Time, tES
Hold Time, tEH
100
100
ns
ns
Data Output
CLOCK Low to Data Out
Time, tcoo
800
CL =50 pF
500
ns
Note 2: For timing purposes, the signals ENABLE and BLANK can be considered to be totally independent of each other.
Nate 3: AC input waveform specification tor test purposes: t r • tfs20 ns, f:::; 800 kHz, 50% ± 10% duty cycle.
Note 4: Clock input rise and fall times must not exceed 5",s.
Functional Description
This product is specifically designed to drive multiplexed
or non·multiplexed high voltage alphanumeric or dot
matrix vacuum fluorescent (VF) displays. Character
generation is done externally in the microprocessor, with a
serial data path to the display driver. The MM58342 uses
three signals, DATA IN, CLOCK and ENABLE, where
ENABLE acts as an external load signal. Display blanking
can be achieved by means of the BLANKING CONTROL
input, and a logic '1' will turn off all sections of the display.
A block diagram of thl! MM58342 is shown in Figure 1.
When the chip first powers on, an internal reset is
generated, resetting all registers and latches. The chip
returns to normal operation on application of ENABLE,
and so all interface signals should be inactive at power on.
In Figure 5, the ENABLE signal acts as an envelope, and
only while this signal is at a logic '1' does the circuit accept CLOCK input signals. Data is transferred and,shifted
in the internal shift register on the rising clock edge, i.e.,
'0'-'1' transition. When the ENABLE signal goes low, the
contents of the shift registers are latched, and the display
will show new data. During data transfer, the display will
show old data. DATA OUT is also provided on the
MM58342 being output on the falling edge. At any time, the
display may be blanked under processor control, using the
BLANKING CONTROL input.
Figure 2 shows the pinout of the MM58342 device, where
output 1 (pin 12) is equivalent to bit 1 (i.e., the first bit of
data to be loaded into the shift register following ENABLE
high). A logic '1' at the input will turn on the corresponding
display digit/segment/dot output.
A significant reduction in discrete board components can
be achieved by use of the MM58342, because external
pull·down resistors are not required. Due to the nature of
the output stage, both its on and off impedance values
vary as a function of the display voltage applied. However,
Figur!ls 3a and 3b show that this output impedance will remain constant for a fixed value of display voltage.
Figure 6 shows a schematic diagram of a microprocessorbased system where the MM58342 is used to provide the·
grid drive for a 40-digit 2 line 5 x 7 multiplexed vacuum
fluorescent (VF) display. The anode drive in this example is
p.rovided by another member of the high voltage display
driver family, namely the MM58348, which does not require
an externally generated load signal.
Figure 4 demonstrates the critical timing reqUirements
between CLOCK and DATA IN for the MM58342.
7-133
•
I
Functional Description (Continued)
:E
:E
+~
-40'C
34.5
a 24.5
>
+
Q
~
14.5
..." - - - ' - - - - ' - - - - ' - - - - ' - - - - ' - - - - " -. . lOUT (,.A)
100
200
300
400
500
600
TLIFI7925-3
FIGURE 3a. Output Impedance Off
600(1 TYPICAL
AT +25'C, VDlS = -20V
1.0
400(1 MAX
AT -40'C, VDlS = -30V
~
~
~ 0.5
_=-_......J~
__
.....L_ _ __"__ _ _- ' - _ : _ - - _
0.5
IOUTlmA)
1.5
FIGURE 3b. Output Impedance On
Timing Diagrams
~~~----~~-')(~~~-------
DATA IN
Forthe purposes of AC measurements, VIH = 2.4V, VIL =O.8V.
TLIFI792Mi
FIGURE 4. Clock and Data Timings
CLOCK 5011 -+--I---t~,__+--+-~k---~'----'r----
DATA IN 50% -+. .+---t--t-+-lll--------Jlf-------lll----
DATA DUT 50% -+-+---t-t-E-------Jlf-------,E----
1ESt:::t::t:""I"'___ "'_--
ENABLE 50%
j~t=~C======-J~==~~====:
B~~~~~ 5OII::======:::Jf~~---~"========
VDD - - - - - ,_______
DISPLAY
OUTPUT
Vms--FIGURE 5. Timings (Data Format)
7·134
TUF/7925-f1 '
Typical Application
40-DI6IT BY 2-LlNE
5 x 7 MUlTIPLEXED
DOT MATRIX VACUUM
FLUORESCENT (VF)
DISPLAY
---35
CLOCK 8
I
I
----
20
GRIDS
35
ANODES
ANODES
MM58348
DISPLAY
DRIVER 1
I
I
I I
DATA 81
i
20
GRIDS
----
I
MM58348
DISPLAY
DRIVER 2
MM58342
DISPLAY
DRIVER 1
----
FA
OUT
I
DATA 82
DATA 22
MM58342
DISPLAY
DRIVER 2
1
I
CLOCK 2
OATA 21
MICROPROCESSOR
ENABLE
BLANK
TLIF/7925·7
FIGURE 6. Microprocessor-Controlled Word Processor
,.
7-135
i~ ~National
~ Semiconductor
P~ElIMINARY
MM58348 High Voltage Display Qriver
General Description
Features
The MM58348Is a monolithic MOS integrated circuit utilizing CMOS metal gate low threshold P and N-channel
devices. It is available both in 40'pin molded dual-in-line
packages or as dice. The MM58348 is particularly suited
for driving high voltage (35V max) vacuum fluorescent (VF)
displays (e.g., a 5 x 7 dot matrix display).
•
•
•
•
•
•
•
•
Applications
• COPSTM or microprocessor-drlven displays
•
•
•
•
•
Direct interface to high voltage display
Serial data input
No external resistors required
Wide display power supply operation
LSTTL compatible inputs
Software compatible with NS display driver family
Compatible with alphanumeric or dot matrix displays
No load signal required
Instrumentation readouts
Industrial control indicator
Digital clock, thermostat, counter, voltmeter
Word processor text displays
Automotive daShboards
Block and Connection Diagrams
OUTPUT
35
Dual-In-Line Package
OUTPUT
1
ViliS
OATA IN
CLock
VSS lOY)
OUTPUT 17
OUTPUT 16
OUTPUT 15
OUTPUT 14
OUTPUT 13
OUTPUT 12
OUTPUT 11
OUTPUT 10
OUTPUT 9.
OUTPUT 8
OUTPUT7
OUTPUT 6
OUTPUT 5
OUTPUT 4
OUTPUT 3
OUTPUT 2
OUTPUT 1
YoIS
Yon (5V)
10
11
12
13
14
15
16
17
18
19
20
MM58348
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OUTPUT 18
OUTPUT 19
OUTPUT 20
OUTPUT 21
OUTPUT 22
OUTPUT 23
OUTPUT 24
OUTPUT 25
OUTPUT 26
OUTPUT 27
OUTPUT 28
OUTPUT 29
OUTPUT 30
OUTPUT 31
OUTPUT 32
OUTPUT 33
OUTPUT 34
OUTPUT 35
DATA IN
CLOCK
TOP VIEW
TUFJ5eOl·2
TUFI5601·1
FIGURE 1
FIGURE 2
Order Number MM58348N
See NS Package N40A
7·136
Absolute Maximum Ratings
Operating Conditions
Voltage at Any Input Pin
Voltage at Any Display Pin
Supply Voltage (V DO)
Vss=OV
Display Voltage (VDlS)
Temperature Range
Min
Voo + 0.3Vto Vss - 0.3V
Voo to Voo - 36.5V
36.5V
Voo + IVDlsl
Storage Temperature
-65·Cto + 150·C
Power Dissipation
500 mW at + 85·C
Junction Temperature
130·C
Lead Temperature (Soldering, 10 seconds)
260·C
DC Electrical Characteristics TA =
Symbol
- 40·C to + 85·C, Voo = 5V ± 0.5V, VSS =
Parameter
Conditions
Max
5.5
-10
4.5
-30
-40
Unl~s
V
V
·C
+85
ov unless otherwise specified
Min
Max
Units
150
/LA
10
rnA
0.8
V
10
/LA
15
pF
250
300
400
kfl
kfl
kfl
800
750
680
fl
fl
fl
Vols +2
V
Typ
Power Supply Currents
100
VIN=VSSor Vo o , V oo=5.5V, VSS= OV,
VDlS Disconnected
I DIS
V oo=5.5V, Vss=OV, VDlS = -30V,
All Outputs Low
Input Logic Levels
DATA IN, CLOCK
(Note 1)
VIL
Logic '0'
VIH
Logie '1'
liN
Input Currents
DATA IN, CLOCK
C IN
Input Capacitance
DATA IN, CLOCK
Display Output Impedances
V oo =5.5V, Vss=OV
ROFF
Output Off (Figure 3a)
V Dls =-10V
V OIS = -20V
VDlS = -30V
RON
Output On (Figure 3b)
Vols =-10V
VDlS = -20V
VOIS = -30V
VOOL
Display Output Low Voltage
Voo = 5.5V, lOUT = Open Circuit,
-30VsV ol ss -10V
.
Nol.1: 74LSTTL VOH =2.7V
V
2.4
@
-10
VIN = OV or Voo
10UT= -400pA, TTL VOH =2.4V
@
,
55
60
65
700
600
500
10UT= -400 pA.
7·137
VDlS
•
I
:E
:E
AC Electrical CharacteristicsTA =
Parameter
-40·C.to
+ 85·C, Voo =5V±0.5V
Conditions
Clock Input
Frequency, fc
High Time, tH
. Low Time, tL
Min
Typ
Max
Units
1.0
300
300
MHz
ns
ns
100
100
ns'
ns
(Notes 2 and 3)
Data Input
Set-Up Time, tos
Hold Time, tOH
Nole 2: AC Input waveform specification for lesl purpose: I r s20 ns. IfS20 ns, f = 1 MHz, 50% ± 10% duly cycle..
Note 3: Clock Inpul rise and fall limes musl not exceed 5,s.
Functional Description
data to be loaded Into the shift register following the start
bit). A logic '1' at the input will turn on the corresponding
display digit/segmentldot output.
This product is specifically designed to drive multiplexed
or non-multipJexed high ·voltage alphanumeric or dot
matrix vacuum fluorescent (VF) displays. Character generation is done externally in the microprocessor, with a
seriai data path to the display driver. The MM58348 uses
two signals, DATA IN and CLOQK, with a format of a
leading '1' followed by the 35 data bits, hence allowing
data transfer without an additional signal. A block
diagram of the MM58348 is shown in Figure 1.
A significant reduction in discrete board components
can be· aChieved by use of the MM58348, because external
pull·down resistors are not required. Due to the nature of
the output stage, both Its on and off Impedance values
vary as a function of the display voltage applied. However,
Figures 3a and 3b show that this output impedance will remain constant for a fixed value of display voltage.
Figure. 2 shows the pinout of the MM58348 device, where
output 1 (pin 18) is equivalent to bit 1, (i.e., the first bit of
+85'C
-4O'C
34.5
l24.5
+
~
14.5
o ...."---_'--_---'_ _---'-_ _--'-_ _-'-_ _...J... . lOUT v.A)
o
100
200
300
400
500
600
TLIF/5601·3
FIGURE 3a_ Output Impedance Off
8000 MAX
AT +85'C, VOIs=-10V
1.0
6000 TYPICAL
AT +25'C, VOIS= -20V
E
i.
400IlMAX
AT -4O'C, VOIS = -30V
0.5
o
-=---'-...-----'----'------'----_
0.5
o
1.5
FIGURE 3b. Output Impedance On
7-138
IoUTlmA)
TUF/5601..01
Functional Descrjption
3:
3:
(Continued)
Figure 4 demonstrates the critical timing requirements
between CLOCK and DATA IN for the MM58348.
When the chip first powers on, an Internal reset is gener·
ated, resetting all registers and latches. The chip returns
to normal operation on application of the start bit and the
first clock pulse, and so all interface signals should be In·
active at power on.
In Figure 5, a start bit of logic '1' precedes the 35 bits of
data, each bit being accepted on the rising edge of
CLOCK, i.e., a '0'-'1' transition. At the 36th clock, a LOAD
signal is generated synchronously with the high state of
the clock, thus loading the 35 bits of the shift register into
the latches. At the low state of the clock, a RESET signal is
generated, clearing all bits of the shift register forthe next
set of data. Hence, a complete set of 36 clock pulses is
needed for the MM58348, or the shift register will not clear.
If, at any given time, it is required that the display be
cleared under microprocessor control, i.e., without power
on reset, then the following flushing routine may be used.
Clock in 36 'zeroes', followed by a 'one' (start bit), followed
by 35 'zeroes'. This procedure will completely blank the
display.
;
i50
Figure 6 shows a schematic diagram of a microprocessorbased system where the MM58348 is used to provide the
anode drive for a 32·diglt 5 x 7 dot matrix vacuum fluorescent (VA display. The grid drive In this example is provided
by another member of the high voltage display driver family, namely the MM58341, which has the additional
features of a BLANKING CONTROL pin, a DATA OUT pin,
and an ENABLE (external load signal) pin.
Timing Diagrams
Tl.IFI5801·5
For the purpose of AC measurement, VIH = 2.4V, V,L = O.BV
FIGURE 4. Clock and Data Timings
START
eLK
eLK 35
eLK 1
eLK 2
eLK 3
eLK 33
eLK 34
eLK 35
START
CLK
CLOCK
DATA IN
n.._____
--.Jr-11____________....._______......n..____
n I_____________,______
LOAD
(INTERNAL)....J
RESET
(INTERNAL)
/
~~:~;~
OUTPUT
YDIS
~
~
'------------.-------'
TL/F/5601-6
FIGURE 5. MM58348 Timings (Data Format)
7-139
•
I
Typical Application
:&
::E
32-DIGIT MULTIPLEXED
5x7 DOT MATRIX
VACUUM FLUORESCENT
(VF) DISPLAY
1-----35 ANODES
I
I
1-----32 GRIDS
MM58348
DISPLAY DRIVER
CLOC K8
DATA 8
MM58341
DISPLAY DRIVER'
t
DATA 1
CLOCK I,
1
ENABLE 1
BLANK 1
MICROPROCESSOR
DATA
OUT 1
TLIFI5601-7
FIGURE 6_ Microprocessor-Controlled Word Processor
7-140
~National
PRELIMINARY
~ Semiconductor
s::
s::
I
MM58438 32·Bit LCD Display Driver
General Description
The MM58438 is a CMOS metal gate circuit which is capable of driving up to 32 LCD segments and is available in
a 40-pin molded package. In addition, MM58438 dice is
available for PCB module assembly systems. The circuit
requires a minimum of interface between data source and
display and can be cascaded where larger displays are
required.
•
•
•
•
TTL compatibility
Non-multiplex display
Compatible with HLCD 0438, HLCD 0438A
Stable oscillator only requires one external component
Applications
Features
•
•
•
•
•
•
•
•
•
Serial data input
32 segment outputs
Cascaded operation capability
Alphanumeric and bar graph capability
cOPS ™ or microprocessor displays
Instrumentation readouts
Digital clock, thermometer, counter, voltmeter displays
Industrial control indicator
Serial to parallel converter
Connection and Block Diagrams
Dual-In-Line Package
40
39
38
37
36
35
34
33
32
VDD
LATCH
SEG 32
SEG 31
SEG 30
SEG 29
SEG 28
SEG 27
SEG 26
SEG
SEG
SEG
SEG
25
24
23
22
SEG
SEG
SEG
SEG
21
20
19
18
SEG 17
SEG 16
SEG 15
10
11
12
13
14
31
30
29
28
27
15
16
17
18
19
26
25
24
23
22
21
20
CLOCK
BACKPLANE
DRIVER
SEG 1
SEG 2
SEG 3
32 SEGMENT DRIVERS
Vss
DATA OUT
DATA IN
III
SEG 4
SEG 5
LCD q,
BACKPLANE
SEG 6
SEG 7
SEG 8
LATCH 0
SEG 9
SEG 10
SEG 11
CLOCK 0
DATA OUT
DATA IN 0
TLIFI61512
SEG 12
SEG 13
SEG 14
TOP VIEW
FIGURE 1
Order Number MM58438N
See NS Package N40A
7-141
Absolute Maximum Ratings
Voltage at Any Pin
Veo Supply Voltage
Operating Temperature
Vss ':"0.3VtoVee +0.3V
18V
-40·Cto +85·C .
Storage Temperature
-65·Cto +150·C
Lead Temperature (Soldering', 10 seconds)
300·C
DC Electrical Characteristics Voe = 3.0V to 15V, TA =
- 40·C to + 85·C unless otherwise specified.
\
Parameter
Conditions
Typ
Min
Supply Voltage Vee
Max
3.0
Supply Current lee
Oscillating or Driven Mode, Vee = 5V
Input High Level VIH
Vee = 4.5V to 5.5V
Vee = 5.5V to 15V
Input Low Level VIL
Vee = 4.5V to 5.5V
Vee = 5.5V to 15V
15
V
60
p.A
2.4
0.5 Vee
Vee
Vee
V
V
0
0
0.8
0.1 Voe
V
V
Input Current (Any Input)
Input Capacitance
i
Units
±10
p.A
10
pF
,
Output Current Levels
Segments
Sink
10L
Source
IOH
Vee = 4.5V, VO UT = 0.2V
Vee = 4.5V, VOUT = Vee - 0.2V
Backplane
Sink
Source
20
20
p.A
p.A
Vee = 4.5V, VouT =0.2V
Vee = 4.5V, VouT=Vee-0.2V
320
320
p.A
p.A
Vee = 4.5V, Vo uT =0.5V
Vee = 4.5V, VouT=Vee-0.5V
100
<\
IOL
IOH
Data Output
(.> Sink
Source
-100
Note 1: Output offset voltage with segment capacitance = 250 pF and backplane capacitance = 8750 pF is
AC Electrical Characteristics Vee = 3.0V to 15V, TA =
Parameter
Conditions
Min
±
p.A
p.A
50 mY.
- 40·C to + 85·C unless otherwise specified (Figure 2)
Typ
Max
Units
tl Data Hold Time
0.1
p's
t2 Data Set·Up Tjme
0.1
p's
t3 Latch Pulse Width
1
p's
t4 Clock to Latch Time
0.1
p's
tpd Data Out Delay
Clock Frequency f
DC
Clock Period t( = l/f)
500
ns
500
kHz
2
Backplane Frequency
C EXT =47 pF
Oscillator Stability
Vee=5V
Note 2: Vee rise time (OV to 5V) must not exceed 5 ms.
p's
100
Hz
±50
.
7-142
%
.---------------------------------------------------~~-----.~
s:
Functional Description
The connection diagram for the'MM58438 is shown on the
first page. The circuit is designed to drive LCD displays
directly. Serial data transfer from the data source to the
display driver is accomplished with 3 signals, SERIAL
DATA, CLOCK and LATCH.
logic and sets the BACKPLANE to a logical high level. If
the circuit is in the oscillating mode the LCD cp pin is connected to a capacitor which is held low by a high impedance internal pull down transistor. If the circuit is in the
. driven mode the LCD cp pin is connected to the previous
BACKPLANE output and is forced high by this low impedance output. When the first LATCH pulse goes to a
logic '1: the level on the LCD cp pin is internally latched
which indicates to the rest of the logic whether the circuit
is driven or oscillating.
The MM58438 uses a latch mode of microprocessor data
transfer whereby the signal LATCH acts .as a latch to the
input data (Figure 2). Data is input to and output from the
internal shift register on the negative clock edge (i.e., a
logic '1' to logic '0' transition) while the LATCH pin is held
low. The contents of tlie shift register are latched to the
output latches and display drivers on the logic '0' to logic
'1' transition of the LATCH pin when it is pulsed high.
The oscillator on the oscillating device starts as soon as
the LATCH pin goes to a logic '1:
In the driven mode, the BACKPLANE frequency is in phase
with the input frequency on the LCD cpo
The MM58438 can be cascaded when a larger display is
required where it can be considered to be driven or
oscillating.
To ensure the correct latching of this function, the LATCH
input must be held at a logic '0' level for a minimum of
10 "s at power on.
rln the oscillating mode, the BACKPLANE frequency is determined by the capacitor connected to the LCD cp pin.
When two circuits are cascaded the second LCD cp input is
driven by the first backplane output.
Once the initial conditions on power up have been obeyed,
the circuit can be used as serial to parallel converters with
the polar-ity of the output data determined by the logic
level on the LCD cp input. A logic '1' on the LCD cp input
produces inverted data.'
When the circuit is first powered on, an internal power on
reset signal is generated which primes the mode detect
Timing Diagram
CLOCK
LATCH
DATA IN
DATA OUT
TLlF/6151·3
FIGURE 2
7-143
i
_
Typical Application
32 SEGMENTS
32~S
DATA OUT
BP
MM58438
DATA
DATA IN
DATA
COP42D CLOCK
LATCH
I
t
ir-
DATA IN
LCD rJ>
MM58438
f-
II
LCD rJ>
l.
CLOCK
BACKPLANE
47PF
TUF/6151-4
FIGURE 3. S4-Segment Display Cascading Two MM58438s
0
7·144
'?'A National
~ Semiconductor
PRELIMINARY
MM58538 Multiplexed LCD Driver
General Description
The MM5B53B is a monolithic integrated circuit utilizing
CMOS metal-gate, low threshold P- and N-channel devices,
which drives an B row by 26 column dot matrix LCD array
directly under the control of an external microprocessor.
The MM5B53B can be used with an MM5B539 to drive a
display that has up to B rows and an arbitrary number of
columns. Data is input serially from the microprocessor
which will service the drivers in response to an interrupt
signal.
• Simple 3 line interlace to microprocessor
• Interrupt output
The circuit is available in a 40-pin molded dual-in-line package or dice.
• Toys and games
• Word processor text displays
• Automotive dashboards
•
•
•
•
Low power
Wide supply voltage range
On chip oscillator
Compatible with HLCD 053B
Applications
Features
• Drives up to B rows and 26 columns
• Expandable to larger displays with MM5B539
• Flexible organization allows any display pattern
Block a'nd Connection Diagrams
Dual-In-Llne Package
Voo----+
Vou
DATA IN
CLK
LCDO
CLK
LCDO
VSS
INTERRUPT
COL 26
COL 25
COL 24
COL 23
COL 22
COL 21
COL 20
COL 19
COL 18
COL 17
COL 16
COL 15
COL 14
COL 13
LCD
WAVEFORM
GENERAliON
38
37
36
35
34
33
32
10
11
12
13
14
15
16
MM58538
17
18
19
20
21
ROW 1
ROW 2
ROW 3
ROW 4
ROW 5
ROW 6
ROW 7
ROW 8
COL 1
COL 2
COL 3
COL 4
COL 5
COL 6
COL 7
COL 8
COL 9
COL 10
COL 11
COL 12
TOP VIEW
TL/F/5728-2
INTERRUPT
TL/F/5728-1
FIGURE 1
7·145
FIGURE 2
Absolute Maximum Ratings (Note 1)
Operating Conditions
DC Input or Output Voltage
Storage Temperature, Tstg
Storage Voltage, Voo
Power Dissipation
Lead Temperature
(Soldering, 10 seconds)
Operating Supply Voltage
DC Input or Output Voltage
Operating Temperature Range
MM58539
-0.3V to Voo+0.3V
- 65·C to 1500C
18V
500mW
Min
3
0
Max
15
Voo
Units
V
V
-40
85
·C
260·C
DC Electrical Characteristics
Symbol
Parameter
T = -4lrCto7lrC
Conditions .
Min
VIH
VIL
VIH
VIL
High Level Input
Voltage (except
LCDO)
Low Level Input
Voltage (except
LCDO)
High Level Input
. Voltage, LCDO
Low Level Input
Voltage, LCDO
All Voo (Note 2)
Voo = 5V
Voo = 15V
Typ
0.75Voo
V
3.75
11.25
V
V
All Voo (Note 2)
Voo = 5V
Voo = 15V
All Voo (Note 2)
Voo = 5V
Voo = 15V
All Voo (Note 2)
Voo = 5V
Voo = 15V
Units
Max
0.25Voo
V
1.25
3.75
V
V
0.9Voo
V
4.5
13.5
V
V
Voo-15
O· 1Voo
V
-10
0
0.5
1.5
V
V
Voo
V
VOH
High Level Row
Output Voltage
lOUT = OILA
VOL
Low Level Row
Output Voltage
lOUT = OILA
VOH
Unselected Row
Output Voltage
lOUT = OILA
VOH
High Level Column
Output Voltage
lOUT = OILA
VOL
Low Level Column
Output Voltage
lOUT = OILA
ROUT
Row or Column
Output Impedance
lOUT = ± 1OILA
Voo = 5.6v,
40
kO
VOFF
Average DC offset
Any Display Element·
lOUT = OILA
(Note 2)
100
mY'
VOL
Low Level Interrupt
Output Voltage
lOUT = 100ILA
0.1
V
liN
Input Current
VIN = VssorVoo
100
Quiescent Supply
Current
Voo = 5.0V,
RIN
Input Resistance,
LCDO Inputs
Voo = 5.0V
CIN
V
Vss
0.5Voo
V
0.68VOD
V
0.32Voo·
V
1.0
Input Capacitance
5
:
5
ILA
400
ILA
3.0
MO
. 10
pF'
Note 1: Absolute Maxtmum Ratings are those values beyond which damage to the device may occur. All Voltages referenced to ground unless otherwise noted.
Note 2: Guaranteed (but not 100% production tested) oyer the operating temperature and supply voltage ranges. These limlls are not used to calculate outgoing
Auailly levels.
.
7·146
AC Electrical Characteristics
Symbol
VDD= S.OV. CL =
Parameter
Conditions
fMAX
Clock Frequency
ts
Setup TIme Data to .
Clock
(Failing Edge)
tH
Hold Time Clock to
Data
(Failing Edge)
tPHL. tpLH
tr• tf
fose
so pF. and TA = 2S"C. tr=tf= 20 ns
Min
Typ
DC
Max
Units
1.5
MHz
300
ns
100
ns
Propagation
Delay LCDO to
Interrupt
300
ns
Maximum Clock
Input Rise and
Fall Time
200
ns
Oscillator
Frequency
Rose=1.2Mfi
Cose=470pF
Vcc=5.0V
Vee=: 1S.0V
2.9
3.6
kHz
kHz
Switching Waveforms
Data Setup and Hold
-lI'MAX-
CLOCK
9011 - 9 0 1 1
5011
5011
10%
lOll
~
r;:---,15OI1
--t ..
~-I
1+ ..
"
~
I-~
CIa:::
5011
-1M
~
50%
1M
TL/F/5728-5
Interrupt Propagation Delay
LCDO
INTERRUPT
j~c
,
TL/F15728-6
\
(
7-147
•
I
:::I
:::I
Functional Description
A block diagram of the MM58538 LCD driver is shown in
Figure 1. Connection diagrams are shown in Figure 2.
MICROPROCESSOR INTERFACE
Figure 3 shows some typical waveforms for the microprocessor interface. All character or pattern generation is done
externally by the processor. Data is loaded into the shift
register on the falling edge of the clock. A data logic '1' on a
coincident row/column causes a segment to be visible. On
the next rising edge of the interrupt signal, a parallel transfer
from the shift register to the latches occurs and the row and
column outputs change accordingly. This Interrupt signal
also acts as a refresh request and new data must be loaded
before the next Interrupt sigrial. The output locations correspond to a clockwise advancing shift register. Pin 40 is the
last bit of data loaded and pin 7 is the first bit loaded.
I
I
MM58539
DATA
I
~
DATA
MM51538 ClK
MM58538
DATA
---111111111111111111
MM51539 ClK
ROW AND COLUMN OUTPUTS
Waveforms for both selected and deselected row and column outputs are .shown for an MM58538 together with an
MM58539 (slave column driver) in Figure 3. Rows generated from the MM58538 are out of phase with Interrupt if selected and at mid point voltage otherwise; levels are Voo,
Vss and Voo/2. Columns generated from both the
MM58538 and the MM58539 are in phase with Interrupt if
selected and out of phase if not selected;. levels are
0.32Voo and 0.68Voo. Backplanes, i.e., rows, should be addressed sequentially and individually. If the supply voltage
has to be altered to optimise LCD contrast or for temperature compensation it is recommended that all positive supply terminals be connected together and the negative supply varied.
~
~
~
111111111111111111
1I11111111111111111
IIIIIIIIIIIIIIIIIIL
11111111111111111111
11111111111111111111
11111111111111111111
lCDO
(MM585381
INTERRUPT
(MM51538)
--1
lCDO
(MM58539)
--1
INTERRUPT
(MM58539)
-.J
I
DESElECTEO -
•
-.J
I
I
-OESElECTED-
,
ON
ON.
TYPICAL
COLUMN
SELECTED
I
TYPICAL ROW
I
-Val
OFF
I
-Vuo
0.5 Vuo
I
-O.SIY••
0.32 Yo.
TL/F/572B-3
FIGURE 3. Typical Waveforms
7·148
3i:
s::
Functiorial Description (Continued)
LCDOINPUT
This input can be used in two modes:
1 Oscillating Mode
When ,this pin is connected with an external resistor and
capacitor in parallel to Vss, this input operates as an RC
oscillator. This frequency is divided by two to provide a
50% duty cycle and will then appear at the Interrupt output as a frequency of approximately 1/RC, where R
should exceed 1 MO.
The Interrupt output frequency should be greater than the
minimum no-flicker frequency (approximately 30 Hz) multiplied by the number of backplanes used.
2 Driven Mode
In this mode, the Interrupt output will follow the waveform
input on the LCDO pin.
LCDO of a driven mode device should preferably be connected to the Inte~rupt output of the previous oscillating
device. If driven from an external source"it must be a 50%
± 1% duty cycle waveform to maintain low DC offset on
the display.
MODE DETECTION
The mode of operation is achieved automatically in the following manner. When the circuit is first powered on, ari internal power-an-reset Signal is generated which primes the
mode detect logic. This signal sets all the row outputs to
8~
the Deselected state, all the Column outputs to the off state
and the Interrupt output high. If the circuit is in the Oscillating mode, the LCDO pin is held low by the external oscillator
resistor. If the circuit is in the driven mode, the LCDO pin is
held high by the low impedence Interrupt output of the previous device. When the first clock pulse goes to a logic '1',
the level on the LCDO pin is internally latched, which indicates to the rest of the logiC whether the circuit is driven or
oscillating.
_
The oscillator on the oscillating device starts as soon as the
clock pin goes high.
In the Driven mode, the Interrupt frequency is in phase with
the input frequency on LCDO.
CASCADING
Figure 4 shows an application where two or more LCD drivers are cascaded. Only a single resistor and capacitor are
needed to provide frequency control for all circuits. The Interrupt output frorn the 'master' oscillating circuit is connected to the LCDO input of the other 'slave' circuits, with the
'slave' Interrupt going to the microprocessor. It would also
be possible to connect all LCDO inputs to a common drive
signal.
The interface to the microprocessor can be done by having
a common clock and separate data bus lines or vice versa.
DOT MATRIX lCO
....
--=f r
MM58538
lCOO
DISPLAY
GROUND
INT
DATA
....
....
IJio..
""
~p-!.
MM58539
lCOO
r
INT
DATA
ClK
""
34
COlS
34
COlS
26
COlS'
4
i
~
~
ClK
15
1
I
Irl!
•
MM5B539
lCDO
DATA
J
ClK
1
DATA CLK
MICROCOMPUTER
SYSTEM
I:TERRUPT
COP420
TL/F/5728-4
FIGURE 4. Typical Application Diagram
7-149
~r-----------------------~------------------------------------------------'
(II)
.
5i
I
~ National
~ Semiconductor
PRELIMINARY
MM58539 Multiplexed LCD Driver
General Descriptior:t
The MM58539 is a monolithic integrated circuit utilizing
CMOS metal-gate, low threshold P- and N-channel devices,
which can drive up to 34 columns of a dot matrix LCD array
directly under the control of an external processor. The
MM58539 should be used with an MM58538 or MM58548
to drive a display that has up to 8 or 16 rows and an arbitrary number of columns. Data is input serially from the microprocessor which will service the drivers in response to ari
interrupt signal.
The circuit is available in a 40-pin molded dual-in-line package or dice.
Features
•
•
•
•
•
•
•
Flexible organization allows any display pattern
Simple 3 line interface to microprocessor
Interrupt output
Low power
Wide supply voltage range
On chip oscillator
Compatible with HLCD 0539
Applications
• Toys and games
• Word processor text displays
• Automotive dashboards
• Drives up to 34 columns
• Used with the MM58538 or MM58548 for expanding to
larger displays
Block and Connection Diagrams
VDD---+
Dual·ln·Llne Package
ClK
VDD
40
COLl
DATA IN
ClK
lCDO
39
col. 2
38
37
36
35
34
33
32
COL3
COL 4
COL 5
COL 6
COL 7
COL I
COL 9
COl 10
COL 11
COL 12
COL 13
COL 14
COL 15
COL 16
COL 17
COL 18
COL 19
COL 20
Vss
LCOO
TL/0/6167-1
FIGURE 1
INTERRUPT
COL 34
COL 33
COL 32
COL 31
COL 30
COL 29
COL 21
COL 27
COL 26
COL2S
COL 24
COL 23
COL 22
COL 21
10
11
12
MM58539
19
20
21
TOP VIEW
TL/0/6167-2
FIGURE 2
7-150
Absolute Maximum Ratings
DC Input or Output Voltage
Storage Temperature, TSTG
Supply Voltage, Voo
Power Dissipation, Po
Lead Temperature
(Soldering, 10 seconds)
Operating Conditions
(Note 1)
- 0.3V to VOO + 0.3V
-65' to 150'C
18V
500mW
Operating Supply Voltage
DC Input or Output Voltage
Operating Temperature Range
MM58539
MIn
3
0
Max
15
Voo
Units
V
V
-40
85
'C
260'C
DC Electrical Characteristics
Symbol
Parameter
TA
Conditions
Min
V,H
V,L
V,H
V,L
High Level Input
Voltage (except
LCDO)
Low Level Input
Voltage (except
LCDO)
High Level Input
Voltage, LCDO
Low Level Input
Voltage, LCDO
All Voo (Note 2)
Voo = 5V
Voo = 15V
All Voo (Note 2)
Voo = 5V
Voo = 15V
All Voo (Note 2)
Voo
Voo
= 5V
= 15V
All Voo (Note 2)
Voo = 5V
Vee = 15V
=
-40'Cto70'C
Typ
Units
Max
V
0.75Voo
3.75
11.25
0.25Voo
1.25
3.75
V
V
V
V
V
V
0.9Voo
4.5
13.5
V
V
Voo-15
-10
0
0.1 Voo
0.5
1.5
V
V
V
VOH
High Level Column
Output Voltage
lOUT =·O,.A
0.68Voo
V
VOL
Low Level Column
Output Voltage
lOUT
= O,.A
0.32Voo
V
ROUT
Column
Output Impedance
lOUT = ± 10,.A
Voo=5.0V
VOFF
Average DC Offset
Any Display Element
VOL
Low Level Interrupt
Output Voltage
lOUT
liN
Input Current
100
R'N
Quiescent Supply
Current
Input Resistance,
LCDOlnputs
C'N
Input Capacitance
40
KO
lOUT = O,.A
(Note 2)
100
mV
=
0.1
V
5
400
,.A
3.0
MO
10
pF
100,.A
Y,N = Vss or Voo
Voo = 5.0V
Voo
=
1.0
5.0V
5
,.A
Not. 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. All Voltages referenced to ground unless otherwise noted.
Not. 2: Guaranteed (but not 100% production tested) over the operating temperature and supply voltage ranges. These limits are not used to calculate outgoing
quality levels.
7-151
•
~
It)
~
~
~
AC Electrical Characteristics
Symbol
fMAX
ts
TH
IpHL.lpLH
I,. If
fosc
Voo
Parameter
Clock Frequency
Setup Time Data 10 Clock
Hold Time Clock 10 Data
Progagation
Delay LCDO 10
Int.Oul
Maximum Clock
Input Rise and
Fall Time
Oscillalor
Frequency
= 5.0V. CL = 50 pF. TA = 25·C. fr, If = 20 ns
Conditions
Min
DC
300
100
(Falling Edge)
(Falling Edge)
Rose = 1.2MO
Goes = 470pF
Vee = 5.0V
Vee = 15.0V
Typ
Max
1.5
300
Units
MHz
ns
ns
ns
200
ns
2.9
3.6
Timing Waveforms
-lItMAX-
CLOCK
90%
50%
~
Ir-DATA
r---'!
10%
50%
90%
10%·
~
150%
\50%
ll'-'~_ __
I-IS:::
I- - 1-_
F
~50%
/50%
~~IH~
-IH
, 50%
~----
LCDD
INTERRUPT
TL/O/6167 -8
7·152
kHz
kHz
Functional Description
A block diagram of the MM58539 LCD driver is shown in
Figure 1. Connection diagrams are shown in Fl{Jure 2.
MICROPROCESSOR INTERFACE
Figure 3 shows some typical waveforms for the microprocessor interface when the' MM58539 is used with the
MM58538 to provide row and column information. All character or pattern generation is done externally by the processor. Data is .loaded into the shift register on the falling edge
of the clock. A data logic "1" on a coincident row/column
causes a segment to be visible. On the next rising edge of
the interrupt signal, a parallel transfer from the shift register
to the . latches occurs and the row and column outputs
change accordingly. This Interrupt signal also acts as a refresl1 request and new data must be loaded before the next
Interrupt Signal. The output locations correspond to a clockwise advancing shift register. Pin 40 is the last bit of data
loaded and pin 7 is the first bit loaded.
I MM58S31 I MM58539 I
IWffMMJ
DATA
DATA
ROW AND COLUMN OUTPUTS
Waveforms for both selected and deselected row and column outputs are shown for an MM58539 together with an
MM58538 in Figure 3.
Rows generated from the MM58538 are out of phase with
Interrupt if selected and at midpoint voltage otherwise; levels are Voo, Vss and Voo/2. Columns generated from both
the MM58538 and the MM58539 are in phase with Interrupt
if selected and out of phase if not selected; levels are
0.32Voo and 0.e8Voo. Backplanes, ie rows, should be addressed sequentially and individually. If the supply voltage
has to be altered to optimise LCD contrast or for temperature compensation it is recommended that all positive supply terminals be connected together and the negative supply varied.
DATA
~
~
~
MM58531CLK --11111111111111111'--01_.....111111"""""11'--01._.....1111111111"""1111'--01_.....IIIIIIIIIIIIIIIIIIIL
MM58539CLK_---'II"'''"IIIIII"1I1
11111111111111111111
1111111111111111111....
1 __
LCDD
(MM58S3I)
INTERRUPT ..J
(MM58531)
(MM58~3~ ..J
INTERRUPT . I
(MM58539)
--I
DESELECTED
TYPICAl
COLUMN
..J
SELECTED
DN
..
J
I
I
I
TYPiCALRDW
-DESELECTED-
.
ON
OFF
I
I
0.5VallYo.
Vo.
0.58 Yo.
0.31 V..
TLlD16167-3
FIGURE 3. Waveforms
7·153
•
I
:::liE
:::liE
Functional Description (Continued)
LCDOINPUT
This input can be used in two modes:
1 Oscillating Mode
When this pin is connected with an external resistor and
capacitor in parallel to VSS, this input operates as an AC
oscillator. This frequency is divided by two to provide a
50% duty cycle and will then appear at the Interrupt output as a frequency of approximately 1lAC, where A
should exceed 1 MO.
The Interrupt output frequency should be the minimum noflicker frequency (greater than approximately 30Hz) multiplied by the number of backplanes used.
2 Driven Mode
In this mode, the Interrupt output will follow the .waveform
input on the LCDO pin.
LCDO of a driven mode device should preferably be connected to the Interrupt output of the previous oscillating
device. If driven from an external source, it must be a 50%
± 1% duty cycle waveform to maintain low DC offset on
the display.
MODE DETECTION
The mode of operation is achieved automatically in the following manner. When the circuit is first powered on, an internal power-on-reset signal is generated which primes the
.mode detect logiC. This signal sets all the Aow outputs'to
8~
the Deselected state, all the Column outputs to the Off state
and the Interrupt output high~ If the circuit is in the Oscillating mode, the LCDO pin is held low by the external oscillator
resistor. If the circuit is in the driven mode, the LCDO pin is
held high by the low impedance Interrupt output of the previous device. When the first clock pulse goes to a logiC "1",
the level on the LCDO pin is internally latched, which indicates to the rest of the logic whether the circuit-is driven or
oscillating.
The oscillator on the oscillating device starts as soon as the
clock pin goes high.
'
In the Driven mode, the Interrupt frequency is in phase with
the input frequericy on LCDO.
CASCADING
Figure 4 shows an' application where two or more LCD drivers are cascaded. Only a single resistor and capacitor are
needed to provide frequency control for all circuits. The Interrupt output from the "master" OSCillating circuit is connected to the LCDO input of the other "slave" Circuits, with
the "slave" Interrupt going to the microprocessor. It would
also be possible to connect all LCDO inputs'to a common
drive signal.
The interface to the microprocessor can be done by having
a common clock and separate data bus lines or vice versa.
DDT MATRIX LCD
"" ~
""
..
~
34
COlS
26
COlS
~
34
CDLS
I
', 4
'1-
T
MM58538
lCOO
r
INT
OATA
~po!.
ClK
INT
DATA
p!. ~
ClK
15
1
T
OISPLAY
GROUND
MM58539
lCOO
MM58539
lCOO
.r
L
OATA ClK
1
_IIl
OATA ClK
MICROCOMPUTER
SYSTEM
COP420
ItTERRUPT
-
TL/D/6167-4
FIGURE 4. Typical Application Diagram
7-154
~National
~ Semiconductor
MM58540 Multiplexed LCD Driver
General Description
Features
The MM58540 is a monolithic Integrated circuit utilizing
CMOS metal-gate, low threshold P and N-channel devices_
It can be externally programmed to drive either 32 rows or
32 columns under control of the ROW/COL pin_ A high
level selects all rows and a low level all columns_ Two
MM58540s with opposite selections can therefore be used
to drive a 32 x 32 display. Data can be input serially from
the microprocessor provided that CLKEN is high. This is
done in response to an interrupt signal.
•
•
•
•
The circuit is available in either40-pin molded dual-in-line
packages or dice.
Drives either 32 rows or 32 columns
Cascadable for larger displays
Flexible organization allows any display pattern
Simple 4-line interface to microprocessor
• Interrupt output
•
•
•
•
Low power
.Wide supply voltage range
On-chip oscillator
Compatible with HLCD 0540
j
Applications
• Toys and games
• Word processor text displays
• Automotive dashboards
Block and Connection Diagrams
Voo----'
Dual-ln·Line Package
VSST
Voo
Vss
DATA I N - - - - - - - - - + I
INTERRUPT
ROW/COL
ClKEN
SEG 32
SEG 31
SEG 3D
SEG 29
SEG 28
SEG 27
SEG 26
SEG 25
SEG 24
SEG 23
SEG 22
SEG 21
lOAD
LCD
32 OUTPUT DRIVERS
-ROW/COL
INTERRUPT
SEG 1
SEG 2
SEG 3
SEG 4
SEG 5
SEG 6
SEG 7
SEG 8
SEG9
SEG 10
SEGll
SEG 12
SEG 13
SEG 14
SEG 15
SEG16
SEG 17
SEG 18
SEG 19
SEG 20
40
39
38
37
36
35
DATA IN
ClK
LCD
MM58540
10
11
12
13
14
15
16
17
18
19
20
34
33
32
31
3D
29
28
27
26
25
24
23
22
21
TOP VIEW
32 OUTPUTS
TL/F/560,4.2
TliF/S604-1
FIGURE2
FIGURE 1
Order Number MM58540N
See NS Package N40A
7-155
•
~
Absolute Maximum Ratings (Note 1)
- 0.3V to Voo + 0.3V
-65·Cto 150·C
DC Input or Output Voltage
Storage Temperatllre, T STG
Supply Voltage, Voo
Power Dissipation, Po
Lead Temperature (Soldering, 10seconds)
DC Electrical Characteristics T =
Symbol
VIH
Operating Conditions
Operating Supply Voltage
DC Input or Output Voltage
Operating Temperature Range
18V
500mW
260·C
V
·C
Parameter
Conditions
Min
All Voo (Note 2)
0.75 Voo
V
3.75
11.25
\ .
V
V
High Level Input Voltage, LCDO
Typ
All Voo (Note 2)
All Voo (Note 2)
Voo=5V
, 'V oo =15V
J
V
Voo
85
0
-40
High Level Input Voltage (except LCDO)
Voo=5V
Voo=15V
V IL
Units
15
,
Lqw Level Input Voltage (except LCDO)
V IH
Mal(
3
- 40·C to 70·C
Voo=5V
Voo=15V
V IL
Min
Low Level Input Voltage, LCDO
All Voo (Note 2)
Voo=5V
Voo=15V
Max
Units
0.25 Voo
V
1.25
3.75
V
V
0.9Voo
V
4.5
13.5
V
V
Voo-15
-10
0
0.1 Voo
V
0.5
1.5
V
V'
VOH
High Level Row Output Voltage
10UT=01'A
VOL
Low Level Row Output Voltage
10UT=01'A
VOH
Unselected Row Output Voltage
10UT=01'A
0,5Voo
V
VOH
High Level Column Output Voltage
lOUT = O'I'A
O,68Voo
V
VOL
Low Level Column Output Voltage
10UT=01'A
0.32Voo
ROUT
Row or Column Output Impedance
10UT= ± 1O I'A
V oo =5.0V
40
kll
VOFF
Average DC Offset
Any Display Element
IOUT=O !#1
INTII1..J
..J
INT#2..J
LC1IH2
ro~C:~
I
-OESELE~CTE-:-O- . . . I-SELE~CTEo~=t===~O:ESE:LEC:TEO:=-=-=-:~~~~
.
r
TYPICAL
I
I
I
I
I
I
. COL #2 - I---ON~===l---~===t====:;!
I
ONOFF -~-t::.==::::;:--I
OFF
FIGURE 3
Vo.
ROW/COL
MM58540 #1
32 ROWS
'----.LC1I
-VDlS
-VOIS
FIGURE 4
7-158
OOT
MATRI
LCO X
32x32
\
SWitching Waveforms
Data Setup and Hold
CLOCK
OATA
TLlF/5604·5
Interrupt Propagation Delay
LCOD
INTERRUPT
TL/F/5604·6
7-159
i~ ~
National" .
~ Semiconductor
MM58548 Multiplexed LCD Driver
·General Description
Features
The MM58548 is a monolithic integrated circuit utilizing
CMOS metal-gate, low threshold P and N-channel devices.
. It drives a 16-row by 16-column dot matrix LCD array directly under control of an external microprocessor.. The
MM58548 can be used with an MM58539 to drive a display
that has up to 16 rows and an arbitrary numberof columns.
Data Is Input serially from the microprocessor which will
service the drivers in response to an interrupt signal.
•
•
•
•
The circuit is available in either 40-pin molded dual-in-line
packages or dice.
Drives up to 16 rows and 16 cblumns
Expandable to larger displays with MM58539
Flexible organization allows any display pattern
Simple 3-line interface to microprocessor
• Interrupt output
•
•
•
•
Low power
Wide supply voltage range
On-chip oscillator
Compatible with HLCD 0548
Applications
• Toys and games
• Word processor text displays
• Automotive dashboards
Block and Connection Diagrams
Voo-'-'
CLKEN
vssy
CLK
Dual-In-Line Package
Voo
DATA IN
DATA IN
CLK
LCD
Vss
INTERRUPT
NC
CLKEN
C16
C15
C14
C13
C12
C11
C1D
~
LOAD
LCD--+
LCD
AC
CIRCUIT
16RDW
DRIVERS
16 COLUMN
DRIVERS
C9
C8
C7
C6
( C5
INTERRUPT
8
9.
1D
11
12
13
14
15
16
17
18
19
2D
MM58548
R1
40
39
38
37
36
35
34
33
32
31
30
29
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
28
27
26
25
24
23
22
21
R16
C1
C2
C3
C4
TOP VIEW
TLlF15605-1
TUF/5605-2
FI.GURE2
Order Number MM58548N
See NS Package N40A
FIGURE 1
7-160
Absolute Maximum Ratings (Note 1)
Operating Conditions
DC Input or Output Voltage
Operating Supply Voltage
DC Input or Output Voltage
Operating Temperature Range
Min
- 0.3Vto Voo+0.3V
-65'Ct0150'C
Storage Temperature, TSTG
Supply Voltage, Voo
• Power Dissipation, Po
Lead Temperature(Soldering, 10seconds)
~8V
Parameter
Low Level Input Voltage (except LCDO)
Typ
Min
Max
All Voo (Note 2)
0.75 Voo
V
3.75
11.25
V
V
All Voo (Note 2)
Voo=5V
Voo=15V
V IH
High Level Input Voltage, LCDO
All Voo (Note 2)
Low Level Input Voltage, LCDO
All Voo (Note 2)
0.25 Voo
V
1.25
3.75
V
V
V
4.5
13.5
V
V
Voo-15
-10
0
Voo=5V
Voo=15V
,
Units
0.9 Voo
Voo=5V
Voo = 15V
VIL
V
'C
Conditions
Voo=5V
Voo=15V
VIL
V
Voo
85
- 40'C to 70'C
High Level Input Voltage (except LCDO)
VIH
Units
15
500mW
260'C
DC Electrical Characteristics T =
Symbol
Max
3
0
-40
0.1 Voo
V
0.5
1.5
V
V
Voo.
V
VOH
High Level Row Output Voltage
i 10UT=0/LA
VOL
Low Level Row Output Voltage
IOUT=O/LA
VOH
Unselected Row Output Voltage
IOUT=O JLA
0.5 Voo
V
VOH
High Level Column Output Voltage
lour=O/LA
0.68 Voo
V
VOL
Low Level Column Output Voltage
IOUT=O/LA
0.32 Voo
ROUT
Row or Column Output Impedance
lour= ±10/LA
V oo =5.0V
40
kll
VOFF
Average DC,Offset
Any Display Element
lour=O/LA
100
mV
VOL
Low Level Interrupt Output Vollage
lour= 100 /LA
0.1
V
liN
Input Currenl
VIN = Vss or Voo
5
/LA
100
Quiescent Supply Current
V oo =5.0V
RIN
Input Resistance, LCDO Inpuls
V oo =5.0V
CIN
Input Capacitance
V
Vss
1.0
5
Note 1: Absolute Maximum Ratings are those values
noted.
beyon~
which damage to the device may occur.
.
AII.~oltages
V
400
/LA
3.0
Mil
10
pF
referenced to ground unless otherwise
Note 2: Guaranteed (but not 100% production tested) over the operating temperature and supply voltage ranges. These limits are not used to calculate out·
going quality levels.
AC Electrical Characteristics Voo = 5.0V, C L = 50 pF, TA = 25'C, I, = If = 20 ns
Symbol
Parameter
Conditions
Min
f MAX
Clock Frequency
ts
Sel·Up Time Dala .to Clock
(Falling Edge)
300
tH
Hold Time Clock to Data
(Falling Edge)
100
tpHL, tpLH
Propagation Delay LCDO to Interrupt Out
t"tf
Maximum Clock Input Rise and Fall Time
fosc
Oscillator Frequency
Typ
DC
Rosc=1.2 Mil
Cosc =470 pF
Vec =5.0V
Vee = 15.0V
,
7-161
Max
Units
1.5
MHz
ns
ns
2.9
3.6
300
ns
200
ns
kHz
kHz
•
i
::I!l
::I!l
Functional Description
The interrupt output frequency should be the minimum noflicker frequency (approximately 30 Hz) multiplied by the
number of backplanes used.
A block diagram of the MM58548 LCD driver is shown in
Figure 1. A connection diagram is shown in Figure 2.
2) Driven Mode
MICROPROCESSOR INTERFACE
In this mode, the interrupt output will follow the waveform
input on the LCD pin.
Figure 3 shows some typical waveforms for the microprocessor Interface. All character or pattern generation is done
externally by the processor. Data ,is loaded into the shift
register on the falling edge of the clock. A data logic '1' on
a coincident row/column causes a segment to be visible.
On the next rising edge of the interrupt signal, a parallel
transfer of data from the shift register to the latches occurs and the row and column outputs change accordingly.
This interrupt signal also acts as a refresh request and
new data must be loaded before the next interrupt signal.
The output locations correspond to a clockwise advancIng shift register. Pin 40 Is the last bit of data loaded and
pin 9 Is the first bit loaded.
LCD of a driven mode device should preferably be connected to the interrupt output of the previous oscillating
device. I! driven from an exterrialsource, It must be a 50%
± 1% duty cycle waveform to maintain low DC offset on
the display.
MODE DETECTION
The mode of operation is achieved automatically In the
following manner. When the circuit is first powered on, an
internal power-on-reset signal is generated which primes
the mode detect logic. This signal sets all the row outputs
to the deselected state, all the column outputs to the'off
state and the interrupt output high. I! the circuit is in the
oscillating mode, the LCD pin is held low by the external
oscillator resistor. I! the circuit Is In the driven mode, the
LCD pin Is held high by the low impedance interrupt out·
put of the previous device. When the first clock pulse goes
to a logic '1', the level on the LCD pin is internally latched,
which indicates to the rest of the logic whether the circuit
is driven or oscillating. The oscillator on the oscillating
device starts as soon as the clock pin goes high.
ROW AND COLUMN OUTPUTS
Waveforms for both selected and deselected row and column outputs are shown in Figure 3. Rows are out of phase
with interrupt If selected and at midpoint voltage other·
wise; levels are Voo , Vss and Voo/2. Columns are in phase
with interrupt If selected and out of phase if not selected;
levels are 0.32 Voo and 0.68 Voo. Backplanes, i.e., rows,
should be addressd sequentially and' individually. I! the
supply voltage has to be altered to optimize LCD contrast
or for temperature compensation, it is recommended that
all positive supply terminals be connected together and
the negative supply varied.
In the driven mode, the Interrupt frequency Is In' phase with
the input frequency on LCD.
CASCADING
Figure 4 shows an application where;! or more LCD drivers
are cascaded. Only a single resistor and capacitor are
needed to provide frequency control for all circuits. The interrupt output from the 'master' oscillating circuit is con·
nected to the LCD input of the other 'slave' circuits, with
the 'slave' interrupt going to the microprocessor. It would
also be possible to connect all LCD inputs to a common
drive signal.
LCD INPUT
This input can be used in two modes:
1) Oscillating Mode
When this pin is connected with an external resistor and
capacitor in parallel to Vss, this input operates as an RC
oscillator. This frequency is divided by two to provide a
50% duty cycle and will then appear at the interrupt output
as a frequency of approximately 1/RC, where R should exceed 1MO.
CLOCKEN
--_.....
The interface to the microprocessor can be done by having
a common clock and data with separate clock-enable
lines or by holding CLKEN high and having a common
clock and separate data bus lines or vice-versa.
32 DATA BITS
~~'"*"*''"*''*' __....~''''eMM!A~~'"*''*''"*''*'__........
' ' ' ' ' "*''*' ' ' ' ' ' ' ' ' ' ' ' "' ___
DATA _ _ _ _
. . . .
32 CLOCK PULSES
CLOCK _ _ _1111111111111111111111111111111 1
_ _____11111111111111111111111111111111______11111111111111111111111111111111___
r
INTERRUPT
DESELECTED
TYPICAL
ROW
ON
TYPICAL
COLUMN
·1·
SELECTED
-I'
ON
I
FIGURE 3
7-162
-I-
DESELECTED
-I·
OFF
-
L
TLlF/5605·3
Functional Description
Switching Waveforms
(Continued)
Data Setup and Hold
CLOCK
pP SYSTEM
COP420
16 ROWS
MM58548 I-iiiiiiiii"'~
16x16
DOT MATRIX
LCD
DATA
'------tINT
...--.----tLCDq,
TLIF/560S·5
16 COLUMNS
Interrupt Propagation Delay
LCDO
-VDIS
TlIF15605-4
INTERRUPT
FIGURE 4
•
7-163
Section 8
Appendicesl
Physical Dimensions
Section Contents
Introduction to the Reliability MilitarylAerospace Programs ... '. . . . . . . . . . . . . . . . . . . . . . . . . .
Radiation Hardened Technologies from National Semiconductor ........................
" ,Commercial Quality Enhancement Programs. . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . .
Silicon Gate Reliability Report ...................... '.' . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Metal Gate Reliability Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8·2
8·3
8·17
8·33
8·37
8·49
8·71
INTRODUCTION TO THE RELIABILITY
MILITARY/AEROSPACE PROGRAMS
History
neutron irradiation, shock and acceleration
tests, visual radiography, and dimensional tests,
to mention only a few. In the electrical test sec·
tion, there are tests to examine load conditions,
power supplies, short circuit currents, and other
tests. Each of these tests is designed to look at
specific reliability and quality concerns that
affect semiconductor products.
In the mid 1960's the various government agen·
cies responsible for semiconductor reliability
saw that screenable defects were resulting in an
in·equipment failure rate of about 1% per thou·
sand hours. In·depth failure analysis allowed
them to determine what the predominate failure
mechanisms were. The Solid State Applications
Branch of the Air Force's Rome Air Development
Center (RADC) was assigned the task of devel·
oping a screening procedure which would reo
move the infant mortality failures which had led
to the high failure rate previously' encountered.
Working closely with other semiconductor reli·
ability experts, the RADC staff developed MIL·
STD·883, which was first issued in 1968. The
objective of MIL·STD·883 was to create an eco·
nomically feasible, standardized integrated cir·
cuit screening flow which would achieve an in·
equipment failure rate of 0.08% per thousand
hours for Class Band 0.004% per thousand
hours for Class A (which was later superseded
by Class S). Over the years this standard has
grown 'and matured with a' number of new test
methods added as reliability information and
failure analysis results became more detailed.
These developments have, led to one of the
strongest and most comprehensive screening
specs available, MIL·STD·883.
Screening Flows
The overall reliability requirements for a system
depend upon a number of factors, including
cost·effectiveness. For example, a deep space
probe, where component replacement is impos·
sible once the system is launched, requires very
high reliability, despite the inherent cost of com·
plex screening. On the other hand, a ground·
based radio unit can use a less stringent reliabil·
ity testing sequence, since a failed component
can be easily replaced at moderate cost. In line
with this range of needs, MIL·STD·883 estab·
lished three distinct product assurance levels to
provide reliability commensurate with the prod·
uct's intended application. The three levels are
Class S (intended for critical applications, such
as space), Class B (intended for less critical ap·
plications, such as airborne or ground systems),
and Class C (intended for easily replaceable
systems, which has since been eliminated).
Purpose and Structure
National and MIL·M·38510
MIL·STD·883 states: this standard establishes
uniform methods and procedures for testing mi·
croelectronic devices, including basic environ·
mental tests to determine resistance to deleteri·
ous effects of natural elements and conditions
surrounding military and space operations, and
physical and electrical tests. What does this
mean to the semiconductor user? To understand
this, one must subdivide MIL·STD·883 into two
primary areas: 1) Detailed how·to specifications
(methods 1001 through 4007) and 2) Screening
and qualification andlor quality conformance
testing requirements (methods 5001 through
5009). By examining each of these areas the
thrust of MIL·STD·883 will become apparent.
A major thrust exists among integrated circuit
users, suppliers, and the U.S. Government to
avoid proliferation of military procurement spec·
ifications by turning instead to standardized
high reliability microcircuits. National Semicon·
ductor endorses and supports this trend.
One major program to which National is heavily
committed is the JAN MIL·M·38510 IC program.
This is a standardization program administered
by the U.S. Defense Department which allows a
user to purchase a broad line of standard prod·
ucts from a variety of qualified suppliers.
There is only one MIL·M·38510 program. National
is committed to supplying only OPL devices,
and discourages any "pseudo·38150" alternates.
Detailed How·to Specifications
Mll·STD·883 is a collection of environmental,
mechanical, visual, and electrical test methods.
These methods define tests which enable manu·
facturers and users to screen for specific reli·
ability concerns. The tests covered include
moisture resistance, high temperature storage,
'There are two lev~ls specified wit"hin MIL·M·
38510 - Classes Sand B. Class S is typically
specified for space flight applications, while
Class B is used for aircraft and ground systems.
8·3
MI L·M·3.851 0
• Since MIL-M·38510 is a standard program, procurement lead times wi" be shorter. With a
large number of programs using JAN devices,
distributors and manufacturers are able to
establish inventories of JAN devices. National
in particular is committed to maintaining finished goods and work-in-process inventories
to support our customers' needs.
The Defense Electronic Supply Center (DESC)
administers the integrated circuit standardiza·
tion program known as MIL·M·38510 (sometimes
referred to as the JAN IC Program). The specifi·
cation set used to define the program consists
of four documents: general specification MIL·M·
38510, which is an overall definition of the pro·
cessing and testing to be performed; detail
specifications (referred to as "slash sheets:'),
each of which defines the performance paramo
eters for a unique generic device or a family of
devices; MIL·STD-883, which defines specific"
screening procedures; and MIL·STD-976, which
defines line certification requirements.
o
Spare parts, wi" be readily available without
excessive minimum order requirements.
o
Standard parts with volume requirements wi"
remain in production longer.
o
Device markings' are consistent from one
manufacturer to another.
When a user orders a MIL-M-38510 device, he is
guaranteed that he wi" get a device fully con·
formant with the detail specification and which
has also met a" of the general testing and processing requirements. DESC requires semiconductor suppliers to become formally qualified
under the MIL-M-38510 program and to be listed
on the current Qualification Products List (QPL)
before they are allowed to lega"y ship JAN
devices.
• The program is extremely cost-effective. A
user can purchase a few devices for engineering evaluation and prototyping and know that
they wi" be identical to the devices he wi" get
d.uring production. When the, cost factors associated with spec. writing, supplier qualification, maintaining voluminous parts control
documentation, and the more intangible benefits of devjce availability are totaled, use of
JAN ICs is overwhelmingly the most costeffective approach.
Advantages to the User
Advantages to the Supplier
The JAN 38510 program has numerous advantages for the integrated circuit user.
What motivates a supplier like National Semiconductor to be so heavily committed to the,
MIL-M·38510 program? National has the broadest range of reliability'processed products available in the semiconductor industry. A program
such as MIL-M-38510 helps to standardize the
processing required and to minimize the number
of individual user specifications. This allows
National to concentrate more resources on this
program, thereby improving product quality and
availability.
o
A single explicit specification eliminates
guesswork concerning device electrical characteristics or processing flow.
o
The rigorous schedule of quality conformance
testing that is a mand~tory part of the MIL·M38510 program assures the user of long-term
stability.
o
Since the electrical characteristics of the
devices are at jeast as tight as the "standard
industry data sheet" parameters, device performance wi" meet the vast majority of
system design requirements. Additionally,
min.lmax. limits replace many data sheet
typicals, making circuit design and worst.case
design analysis decisions easier.
o
The user is spared the expense of researching
and preparing his own procuremen.t
document.
o
The user is spared the expense of qualification testing. The QPL tells him which suppliers have qualified the device he requires.
o
The QPL gives the user a choice of qualified
suppliers for devices that are fully interchangeable. In addition, the presence of several sources guarantees competitive pricing
that is typically lower than for devices to a
user's own specifications.
.
.
The Most Frequently Asked Questions and
Answers about MIL·M-38510
There are many questions which are frequently
asked regarding the MIL-M-38510 program. We
would like to answer some of them.
Q. WHAT MUST A MANUFACTURER DO TO GET
HIS PARTS LISTED ON THE QPL?
'
A. There are two things which a manufacturer is
required to do. First, he must get his facilities
(including wafer fab, assembly, and rei processing areas) certified by DESC. This requires that each fab area used for QPL devices must be approved. Second, for each
specific device and package combination
listed on the QPL, the manufacturer must
perform extensive qualification testing and
provide detailed device information to DESC.
This data is typically supplied iii two phCi~es.
8·4
In the first phase, the manufacturer must
supply detailed information concerning the
device construction and electrical characteristics. Once this data has been verified by
. DESC to confirm that the manufacturer's device meets the MIL-M-38510 requirements,
·the manufacturer is listed on Part II of the
QPL. At this point the manufacturer is legally
able to supply full JAN qualified devices
meeting ALL of the MIL-M·38510 requirements. The manufacturer must then perform
the full qualification testing of Method 5005
of MIL-STD-883 as specified in paragraph 4.4
of MIL-M-38510. Once this data has been
reviewed and accepted by DESC, the manufacturer is listed on Part I of the QPL.
Q. HOW IS A JAN QPL DEVICE MARKED?
A. Tables I and II explain the details of the marking for JAN ICs.
TABLE I. MIL·M·38510 Part Marking
~~§!Q/~~~XYYY
L
the Lead Finish
A = Solder Dipped
B=Tin Plate
C = Gold Plate
X = Any lead finish above
is acceptable
'--------- the Device Package (see
Table II)
' - - - the Screening Level S or B
Q_ IS THERE ANY DIFFERENCE IN DEVICES
. PRODUCED WHILE A MANUFACTURER IS
LISTED ON PART II OF THE QPL AND THOSE
PRODUCED AFTER PART I QUALIFICATION
IS COMPLETED?
L---the Device Number on the
Slash Sheet
' - - - - - t h e Slash Sheet Number
L------MIL-M-385810
A. There is absolutely no difference. A supplier
must meet all of the device screening and
quality conformance requirements no matter
what his QPL status.
' - - - - - - - - - T h e JAN prefix (which
may be applied only to a
fully conform ant device
per paragraphs 3.6.2.1 'and
3.6.7 of MIL-M-38510)
Q. HOW DOES A USER KNOW WHAT DEVICES
ARE COVERED BY SLASH SHEET SPECIFICATIONS?
TABLE II. JAN Package Codes
A. Supplement 1 to MIL-M-38510 contains a listing of the slash sheet specifications and a
cross reference to the generic part type. This
is updated as new slash sheets are released.
National's Reliability Handbook also contains a cross reference.
38510
PACKAGE
DESIGNATION
A
B
C
D
E
F
Q. HOW CAN A USER OBTAIN COPIES OF THE
QPL,SUPPLEMENT 1 OF MIL-M-38510, MILM-38510 ITSELF, AND MIL-STD-883?
G
A. Copies of these and other related documents
may be obtained from:
H
I
J
K
M
P
Naval Publications and Forms Center
5801 Tabor Avenue
Philadelphia, PA 19120
(212) 697-2179
Q
R
S
Q. WHAT ABOUT THOSE DEVICES FOR WHICH
NO DETAIL SPECIFICATION EXISTS?
V
W
A. The ultimate aim of a standardization program must be to furnish all parts. Requests
for addition of a part to MIL-M-38510 should
be made to DESC Directorate of Engineering,
Dayton, Ohio 45444, indicating a need for
slash sheets andlor suppliers to be qualified
for the additional devices. National has a
form (available through local sales offices)
which may be used for this purpose. In addition, if only some parts are available, a user
can still see significant savings on those that
are available.
~}
MICROCIRCUIT INDUSTRY
DESCRIPTION
14-pin 114" x 114" (metal) flatpack
14-pin 3/16" x 1/4" flatpack
14-pin 1/4" x 314" dual-in-line
14-pin 1/4" x 3/8" (ceramic) flatpack
16-pin 1/4" x 7/B" dual-in-line
16-pin 1/4" x 3/8" (metal or ceramic)
flatpack
B-pin TO-99 can or header
10-pin 114"x 1/4" (metal) flatpack
10-pin TO-100 can or header
24-pin 1/2" x 1-1/4" dual-in-line
24-pin 3/B" x 5/B" flatpack
12-pin TO-101 can or header
B-pin 1/4" x 3/B" dual-in-line
40-pin B116" x 2-1116" dual-in-line
26-pin 1/4" x 1-1116" dual-in-line
20-pin 1/4" x 112" flatpack
1B-pin 3/B" x 1-15/16" dual-in-line
22-pin 318" x 1-1/8" dual-in-line
Unassigned - Reserved for
identifying special packages whose
dimensions are carried in the detail
specifications.
Q. ARE DEVICES CALLED "M38510, JAN PROCESSED, JAN EQUIVALENT, ETC." REALLY
QPL PRODUCTS?
A_ Absolutely not. There is only one QPL product - it is a JM38510 marked device. "JAN
Equivalent" is expressly forbidden by para8-5
product requirements, will have a date code
that is earlier than the date he is placed ori
the QPL. However," the manufacturer may not
begin to assemble and test unless he has a
line certification and an approval to proceed
with qualification.
.
graphs 3.1 and 3.6.7 of MIL-M·38510. MIL·M38510 does provide for the production of
devices when no qualified sources exist, but
this may t;>e done only with prior DESC ap·
proval, and products produced under this
provision must meet all requirements of MILM-38510 other than qualification.
Q. WHAT IS THE RELATIONSHIP BETWEEN
MIL-M-38510 AND MIL-STO-883?
Q. HOW LONG CAN A SUPPLIER REMAIN ON
PART II OF THE QPL?
A. MIL-M-38510 defines complete program
requ irements and the detail device electrical performance parameters. The device
processing requirements are specified in
MIL-STD-883.
A. For Class B, a manufacturer can remain on
Part II for two years or until 90 days after
another supplier becomes qualified for the
same device package, screening level, and
lead finish combination on Part I of the QPL.
Class S devices may remain on Part II for one
year after another manufacturer reaches
Part I.
Q. SUPPOSE DEVICES ARE KEPT ON A MANUFACTURER'S OR DISTRIBUTOR'S SHELVES
FOR A PERIOD OF TIME; MUST THEY EVER
BE RETESTEI) TO VALIDATE THAT THEY
STILL MEET SLASH SHEET CHARACTERISTICS?
Q. WHEN ANOTHER SUPPLIER OBTAINS PART
I QUALIFICATION, ARE THE OTHER QUALI·
FlED SUPPLIERS REMOVED FROM PART II
IMMEDIATELY?
A. Yes. Devices held by a manufacturer or by his
authorized distributor which have a date
code older than 36 months ·must be retested
by the manufacturer in accordance with
Group A sampling requirements prior to shipment to a customer or return. to inventory.
A. No. The supplier is given 90 days before
being removed from Part II for a Class B devjce and one year for a Class S device. During
that time a supplier may legally accept orders
for those devices. After the end of the 90·day
or one year period, he may no longer accept
orders but may complete and ship those orders received prior to that time, no matter
how long it takes him to complete them.
Q. WHY SHOULD A USER SPECIFY "X" IN
. THE LEAD FINISH DESIGNATION FOR A
PART TYPE?
A. A manufacturer who receives an order for a
specific lead finish for which he is qualified
but has no inventory at the time of order may
not be able to fill the order in a timely manner, even though he might have substantial
inventory of another lead finish. Unless a
user has a specific reason for wanting a particular lead finish, he should allow his suppliers the flexibility of shipping whatever
finish is available. .
Q. IS A SUPPLIER. EVER REMOVED FROM
PART I QUALIFICATION?
A. Generally not. As long as a supplier continues to manufacture the device, maintains appropriate facility approvals, and submits all
required reports and information to DESC
within stipulated time limits, he will retain
QPL I listing. Violation of these requirements
can be cause for removal from QPL.
Q. WHAT DATA IS A MANUFACTURER REQUIRED TO SHIP WITH A JAN PART?
Q. CAN AN AUTHORIZED DISTRIBUTOR SHIP
JAN DEVICES FROM HIS SHELVES IF THE
MANUFACTURER HAS LOST HIS QPL LISTING FOR THOSE DEVICES?
A. A certificate of conformance is all that is required. However, he must_ retain all data for
three years.
A. Yes. As long as those devices were ordered
by the authorized distributor while the manufacturer had QPL listing for those devices,
the distributor may subsequently ship those
devices from his shelves.
Q. CAN A DEVICE FOR WHICH THERE I.S NO
SLASH SHEET BE PROCESSED TO MIL-M38510?
A. Since MIL-M-38510 invokes a combination of
the processing requirements of MIL-STD-883
and the detail device performance parameters contained in each individual slash
sheet, the answer is obviously no. However,
National's 883B/RETSTM program does provide parts which meet all of the screening
requirements of the .MIL-STD-883. specifica'
tion and which have been subjected to all of
the MIL-M-38510 controls (except for
domestic assembly).
Q. CAN A MANUFACTURER LEGALLY SHIP
JAN QPL MATERIAL HE ASSEMBLED AND
TESTED BEFORE HE RECEIVED A QPL
LISTING?
A. Yes. The manufacturer must assemble and
screen parts to prove his ability to comply
with the specifications before he can be
. placed on QPL. As a result, his first lot of
material, which is fully conformant to QPL
8-6
TABLE III. Sample MIL·M·38510 Listing
GOVERNMENT DESIGNATION
DEVICE
TYPE*
DEVICE
CASE
LEAD MATERIAL
CLASS OUTLINE
AND FINISH
TEST REPORT
NUMBER
'MANUFACTURER'S NAME
~38510/008
01
S only
A
C
38510·953-81
National Semiconductor Corp.
01
02
B
C
D
A
B
38510-953-81
38510-30-7T
National Semiconductor Corp.
03
B
C
A
B
38510-520-83
National Semiconductor Corp.
"'M38510" is the military deSignator for MIL-M-38510, The QPL shows this notation even though the parts are fully qualified devices and are
'
marked JM38510/XXXXXYYy.
O. HOW IS AN INSPECTION LOT DEFINED?
Q. WHAT DOES A QPL LISTING LOOK LIKE
AND HOW DO YOU READ IT?
A. For Class B devices, each inspection lot shall
consist of microcircuits of a single device
type, in a single package type and lead finish,
or may consist of inspection sublots of several different device types, in a single package type and lead finish, defined by a single
detail specificatio,n. Each inspection lot shall
be manufactured on the same production
line(s) through final seal by the same production techniques, and to the same device
design rules and case with the same material
requirements, and sealed within the same
period not exceeding 6 weeks.'
A. Sample QPL listings are shown in Table III.
JM38510/00801SAC
JM38510/00801 BCA
JM38510/00801 BCB
J M3851 0/00801 BDA
JM38510/00801 BDB
)
JM385101,D0802BCA
JM38510/00802BCB
JM38510/00802BDA
JM38510/00802BDB \
JM38510/00803BCA
JM38510/00803BCB
O. WHAT IS NATIONAL SEMICONDUCTOR'S
COMMITMENT TO MIL-M-38510?
Q. WHAT QUALITY CONFORMANCE TESTS
ARE CONDUCTED? ARE ALL DEVICES IN
A GENERIC FAMILY EVENTUALLY SUBJECTED TO QUALITY CONFORMANCE
'
TESTING?
A. National Semiconductor is convinced that
the level of standardization offered by a program like MIL-M-38510 is the key to long-term
military component procurement viability.
We have a corporate cOl1lmitment to MIL-M38510. We believe that the program will be of
significant benefit in lessening the problem
of product obsolescence, for the volume provided will help to keep many key devices in
production. We believe that the program will
make possible the procurement of devices in
small quantities with reasonable lead times
for long-term spares or field maintenance
requirements.
A. For B level devices quality conformance
tests must be conducted as follows:
Group A-Each inspection lot or sublot.
Group B-Each inspection lot for each pack- '
age. type and lead finish on each
detail specification.
Group C-Periodically at 3-month intervals
on one device type or one inspection lot from each mircocircuit
group in which a manufacturer has
qualified device, types (die related
tests).
National Semiconductor. will continue to
maintain a broad base of line certifications
and an extensive list of Class B and Class S
device qualifications: We will continue to
work with the Department of Defense, concerned users, and other semiconductor manufacturers to update and redefine the applicable specifications. We feel that this level of
support is essential if MIL-M-38510 is to remain the strongest standardization, program
available.
'
Group D-Periodically at a 6-month interval
for each package type for which a
manufacturer holds qualifications
(package related tests).
Different devices within a generic family are
chosen for successive quality conformance
tests until all of the devices have been subjected to testing. The sequence is then repeated. The manufacturer must submit attribu'tes data to DESC for all quality conformance tests performed.
In addition, we will continue to add capacity
and to build up substantial inventories of a
large spectrum of products to ensure the
8·7
ufacturer. We have tried to emulate MIL·M-38510
to the fullest extent possible, with the same production controls, calibration schedules, rework
and resubmission procedures, operator certification requirements, and all of the other key elements of MIL·M·38510. The procedures that we
employ in the production of MIL-M-38510 devices are used for all of the military devices we
manufacture.
availability and the lead times. that are
needed for key military programs.
National Mil/Aero Standardization
Programs
Your customer has imposed upon you requirements for product reliability that you must
meet on every single component you buy. In
most cases, these requirements mandate that
you buy JAN MIL-M-38510 parts where they are
available, and that all other devices must be as
,close to JAN as is achievable. We don't consider
this unreasonable. In fact, we believe that this is
the only reasonable and intelligent approach.
Our 883S/RETS microcircuits are processed
through a screening flow that matches the MIL-M·
38510 Class S flow exactly. Our commitment to
MIL·M·38510 Class S is such that once qualified
for a given device type we will sell that part only
as a JAN Class S part. Class S QPL listing will
result in the immediate removal from production
of the 883S/RETS version of the device.
To meet this objective, we designed our 883B/
RETS program around requirements that were
already imposed for the MIL-M-38510 program.·
We realize that there are many so-called standardization programs available in the marketplace which lack the c~mpliance that you need.
Our 883B/RETS program is totally compliant. We
invite you to make this comparison between
what we offer and what you need. Our screening
flow, our 5% PDA, our quality conformance test
frequency, and the other items that you consider
important, match exactly the requirements
defined in MIL:M-38510.·· If they did not, we
could not offer Total Standardization.
National's Commitment
But compliance flows are obviously meaningless unless the capacity is in place to support
them. We have the industry's largest screening
capacity. Over the/past few years we have reinvested substantial sums in additional capital
equipment in both buildings and the equipment
with which to fill those buildings. Our Tucson,
Arizona plant was the first plant in the entire in·
dustry to be totally dedicate9 to the production
of military integrated circuits. We will continue
to add capacity for military assembly and test,
even during those periods when others turn
away from the military marketplace in pursuit of
what they view to be the more attractive com·
mercial market. We feel that a commitment to
the needs of the military/aerospace user com·
munity should not be based upon the conditions
encountered in the commercial marketplace. We
have no plans for other than a continued longterm commitment to military/aerospace component production and screening. And we will not
deviate from the highest standards of quality
and reliability in our execution of that commitment. There are no shortcuts to semiconductor
reliability. It can only be achieved through rigid
adherence to established standards.
Standardization provides the manufacturing efficiencies needed by the semiconductor manufacturers if they are to meet military semiconductor
needs. To the user, standardization offers the
highest guarantee of quality and reliability
through production consistency and uniformity.
The most significant benefit of standardization
to the Department of Defense, however, is that it
ensures the availability of component level
spares to key programs with the pricing, delivery, and reliability needed for, the field support
and maintenance of our key defense electronics
systems.
National's MIL·M·38510 Emphasis
To implement this view of standardization, we
have based our entire approach to military
screening upon the Class S and Class B require·
ments of MIL·M·38510. We are convinced that to
do less than this would be to provide an inferior
product, one that does not meet the true needs
of the Department of Defense. Our 883B/RETS
microcircuits are processed through the most
comprehensive and compliant Class B screen·
ing program offered by any semiconductor man-
However, we also acknowledge the quite obvious fact that through refinement and redefinition, standards are subject to change. As those
changes occur, we will update our current procedures to reflect the changes that find their way
into MIL-M-38510 and MIL-STD-883. We will,
where our understanding of semiconductor reliability and screening indicates the need, actively
pursue those changes that we feel wil,1 allow our
industry to provide a beUer product to the sys·
tems manufacturers. We will also steadfastly
resist those changes which we feel sacrifice reli
ability to the less important question of
expediency.
'Requirements that were subsequently incorporated into MIL·
STO·883
'
"and MIL·STD·883.
8-8
National's Standard Programs
Ordering to Control Specifications
MIL-M-38510 is the key military standardization
program for ICs. National is equally committed
to the support of the requirements of the space
segment of the market for MIL-M-38510 Class S
devices. To support these needs we have established dedicated Class S assembly and test
facilities. The realization that users could not
obtain all the device types they required through
these programs led National's Military/Aerospace Products Group to the development of
two of the strongest and most compliant inhouse programs in the industry. National programs for 883B/RETS and 883S/RETS microcir·
cuits provide the systems manufacturer with an
easy mechanism for obtaining those devices not
listed on the MIL-M-38510 QPL. In response to
·other user needs, National also developed a program for radiation hardened devices (both
CMOS and linear), a comprehensive program for
radiation susceptibility testing for Class S
devices, and a program for the production cif
devices in leadless chip carriers (LCCs).
We also acknowledge the fact that many military
systems manufacturers must, for contractual
purposes, maintain their own specifications for
many of the devices that they purchase. We have
no objection to the use of contractor prepared
procurement specifications, for we have found
that the majority of these documents are written
in compliance with the requirements of MIL-M38510. Where this is true, we have found that
they are also totally compatible with our inhouse standardization programs. Where drawings submitted to National differ from the
requirements outlined in MIL-M-38510, we welcome the opportunity to work with our customers to develop specifications which do meet the
intent of MIL-M-38510.
Where customer specifications and our 883BI
RETS product specifications correspond, we
have the ability to expedite delivery by adding
the customer part number in addition to the
basic 883B/RETS part number. Customers who
understand our program and wish to use the program in their parts procurement may order by
placing "M/O" after their part number on their
purchase order, thus allowing us to mark their
part number on our 883B/RETS devices without
the lengthy delay normally required for a comprehensive specifications review cycle. We have
tried to provide programs that offer the maximum level of flexibility within the constraints of
standardization.
RETS and Burn·ln
One of the primary advantages of MIL-M-38510 is
its clear definition and standardization of electrical test and burn-in requirements. One of the
major drawbacks seen in the standard reliability
screening programs of most semiconductor
manufacturers is that electrical testing is invariably performed. to some document that is not
available to the user. The user has the right to
know what he is buying. At National that testing
is never vague or undefined. Both in-house programs (883B/RETS and 883S/RETS) are based
upon a document called the RETS (an acronym
for Reliability Electrical Test Specification. The
RETS is a simplified but complete description of
the testing performed as part of National's standard Rei electrical test programs, and is controlled by our QA department. The burn-in circuits and electrical test parameters· for the MILM-38510 Class S and Class B devices produced
by National Semiconductor are defined by the
applicable detail specification.
Standardization is the key to cost-effective procurement of high reliability semiconductor devices. National Semiconductor Corporation is
committed to that standardization.
Military Processing: A Corporate Commitment
The National Semiconductor Military/Aerospace
Products Division draws upon the total resources of National Semiconductor. National is
one of the world's largest manufacturers of
semiconductor products, offering the largest
number of product types available from any single source in the industry. This product line is
growing faster than that of any other worldwide
semiconductor manufacturer. Each new product
is carefully evaluated for possible military/aerospace usage potential, and new product designs
must comply with the reliability and quality constraints required by that segment of the industry. All new product designs are targeted to
full
military temperature
range operation.
.
.
Ordering ICs from National.
Ordering National Semiconductor High Reliability integrated circuits is very simple. National
sales offices and sales representatives "can provide price and delivery information on our entire
line of JM38510 Class B, JM38510 Class S, 883BI
RETS and 883S/RETS microcircuits. A large
percentage of these devices are available from
inventory at either the factory or at one of our
many distributors.
In addition, a dedicated Reliability Engineering
Department within the Military/Aerospace Prod-
8-9
tion products. As a result of all this innovation,
National has become the only company in the
entire semiconductor industry capable of providing high reliability devices from all of the
following product lines:
ucts Division coordinates burn-in circuit design,
test tape development, te'st fixturing, support
documentation, and new product release paperwork to ensure the earliest possible introduction
, of fully compli'ant 883B/RETS versions of the
new products introduced by the company.
linear
hybrid
CMOS logic
Megarad CMOS logic
bipolar, memory
MOS RAMs
CMOS RAMs
MOS,EPROMs
CMOS EPROMs
MOS EEPROMs
data acquisition devices
standard TIL
low power TTL
low power Schottky
standard Schottky
interface devices
bipolar microprocessors
MOS microprocessors
CMOS microprocessors
- COPSTM microcontrollers
high-speed CMOS Schottky
advanced low power Schottky
advanced Schottky
We are able to do this well, for National is no newcomer to this business. Founded in Danbury,
Connecticut in 1959, National acquired an entire
new management team in 1967 and moved corporate headquarters to Santa Clara, California.
The new management team focused its attention on the-transistor product line, and rapidly
made that, line profitable. Then the company's
talents were turned to, the development of linear,
digital, and MOS integrated circuits - the
fastest-growing segments of the semiconductor
marketplace. Finally, an OEM representative and
distributor network was established to develop
and service a broad customer base,and facilities were added around the world to provide
competitive products to worldwide markets.
The Reliability Test Department was initially
formed in 1968 and reported at that time to the
Director of Quality Assurance. The Rei Department developed the same rapid growth rate that
the company as a whole had shown. From a
small staff occupying several thousand square
feet in Santa Clara, these reliability test operations grew until today they employ over 3000
people worldwide. Well over 200,000 square feet
are devoted to the testing and assembly of high
reliability products. During 1981, the Military/
Aerospace Products Group became the Military/
Aerospace Products Division. The company is
currently involved 'in a number of military research' and development programs, Including a
Phase I VHSIC contract.
National Semiconductor has wafer fabrication
plants in Santa Clara, California; Salt Lake City,
Utah; Arlington, Texas; and Danbury, Connecticut. Many of these fabrication plants, along with
our assembly and test lines in Santa Clara, California and Tucson, Arizona, have been fully certified fo.r the production of Class S and Class B
MIL-M-38510 circuits.
To support the requirements of the Class S marketplace, we have our own SEM and radiation
testing facilities. Our screening capabilities are
backed up by one of the most extensive failure
analysis labs in the industry.
VHSIC involvement was natural since National's
technological leadership has enabled the company to consistently be one of the major suppliers of military/aerospace semiconductors.
Having cohtinued to develop a high technology
image through the development olf Megarad
hardened CMOS and linear device types, and the
development of TRI-CODETM logic, National is
now expanding technology frontiers in the areas
of memory, microprocessor, and data acquisi-
National is the leader in the military/aerospace
integrated circuit market. We have achieved that
leadership by offering an unmatched combination of technology, product breadth, understanding, commitment and capacity.
8-10
883B/883S/RETS Screening Flows
WAFER FABRICATION &
DEVICE ASSEMBLY
WAFER LOT ACCEPTANCE
PER METHOO 5007
NOTE 2
PRECAP VISUAL INSPECTION
MIL-STO-BB3 METHOD 2010
CONDITION B
ASSEMBLY
DIE SHEAR
TESTING
NOTE 2
SEALING
ASSEMBLY
BOND PUll
TESTING
NOTE 2
STABLlLlZATION BAKE
MIL-STO-BB3 METHOD 100B
CONDITION C
100% NON-OESTRUCTIVE BON~
PULL TESTING (METHOD 20231
I
PRECAP VISUAL INSPECTION
(METHOD 2010. CONO AI
TEMPERATURE CYCLING
MIL-STD-883 METHOD 1010
CONDITION C
SEALING
CONSTANT ACCELERATION
MIL-STO-BB3 METHOO 2001
CONOITION E (Yl ONLYI
STABILIZATION BAKE
(METHOD 100B. CONO Ci
FINE LEAK TEST
MIL-STO-BB3 METHOD 1014
CONOITION A OR B
TEMPERATURE CYCLING
(METHOD 100B. CONO CI
CONSTANT ACCELERATION
(METHOD 2001. CONO. EI
Yl AXIS ONLY
GROSS LEAK TEST
MIL-STO-883 METHOO 1014
CONDITION C
PINO (METHOD 20201 CONO: A
INTERIM ELECTRICALS AT
+ 25°C DC PER RETS
(AT MANUfACTURER-S OPTIONI
NOTE 3
SERIALIZATION
INTERIM ELECTRICAL TEST
BURN-IN TEST MIL-STO-BB3
25°C DC
REAO-ANO-RECORO
ALL PARAMETERS
METHOD 1015. CONDITION A, B.
COR O. 160 HOURS AT 125°C
OR EOUIVALENT
NOTE 7
STATIC I BURN-IN
24 HRS - 125'C
INTERIM ELECTRICALS
25'C OC PER RETS
POA=5%
VIN=VDUT=O
INTERIM
ELECTRICAL TEST
25'C DC
COMPUTE ~s
POA PER NOTE 4
FINAL ELECTRICAL TEST
PER NSC RETS
+ 125°C. -55°C DC
(INCLUOES FUNCTIONAL
TESTS + 25°C AC
NOTE 7
STATIC II BURN-IN
24 HRS - 125°C
OUALITY CONFORMANCE TESTING
GROUP A - EACH SUBLOT
GROUP B - EACH LOG
GROUP C - EVERY 90 DAYS PER
MICROCIRCUIT
GROUP
GROUP 0 - EVERY 6 MONTHS
PER PACKAGE TYPE
YIN=VOUT=VCC
INTERIM
ELECTRICAL TEST
25'C OC
COMPUTUs
POA PER NOTE 4
NOTE 1
DYNAMIC BURN-IN
240 HRS - 125°C
VIN=VOUY=O TO Vee
AT 100 kHz
EXTERNAL VISUAL
MIL-STO-BB3 METHOO 2009
NATIONAL OFF-THE-SHELF
INVENTORY PROGRAM
INTERIM ELECTRICAL TEST
(POST BURN-INI DC 25'C
POA=5%
FIGURE 1. National's 883B/RETS Class B
Screening Flow
DRIFT
(~I
CALCULATION
NOTES 5. 7
NOTE 5
FINAL ELECTRICAL TESTS
DC AT 125 11 C -55°C
INCLUDING FUNCTIONAL TESTSI
25°C AC
NOTES:
1_ ALL METHODS REFERENCED ARE MIL-STO-BB3 TEST METHODS.
2. THESE TESTS ARE PERFORMED ON A SAMPLE BASIS. ALL OTHER
TESTS ARE PERFORMED 100%.
3. ACCEPTANCE CRITERIA SHALL BE IN ACCORDANCE WITH
MIL-M-3B510.
4. THE POA FOR STATIC I AND STATIC II BURN-IN SHALL BE 5%
TOTAL.
5. THE PDA INCLUDES .l FAILURES,
6. GROUP A AND BOND PULL AND DIE SHEAR TESTING OF GROUP B
MAY BE PERFORMEO ON-LINE.
7. ALL ELECTRICAL TESTING SHALL BE IN ACCOROANCE WITH THE
APPLICABLE RETS OR THE APPLICABLE MIL-S-3B510 OETAIL
SPECIFICATION.
FINE LEAK TEST
(METHOD 1014. CONO. BI
GROSS LEAK TEST
(METHOD 1014. CONO CI
X-RAY INSPECTION
(METHOD 20121
QUALITY CONFORMANCE TESTS
(METHOD 5005. GROUP A.
GROUP B. AND GROUP 01
EXTERNAL VISUAL
(METHOD 20091
FIGURE 2. National's 883S/RETS Class S
Screening Flow
8-11
NOTE 7
NOTES 2. 6
CD40XX, 54CXX Product Availability
The following list of products represents what is currently
available for 883B. As new products are brought on board,
notification will take place through news releases. For further data on the products and families, please contact
your local sales office.
PACKAGE CROSS REFERENCE
NSC
ORDER NUMBER
RCA EQUIVALENT
DESIGNATION
MOTOROLA EQUIVALENT
DESIGNATION
PACKAGE
CD40XXMJ/883B
CD40XXAF
MC140XXAL
Cavity DIP (J)
For B series, NSC order number is CD40XXBMXf883B.
INDUSTRYID
"
CD4001 BMJ/883
CD4002BMJ/883
CD4006BMJ/883
CD4007MJ/883
CD4008BMJ/883
CD4009MJ/883
CD40106BMJ/883
CD4011 BMJ/883
CD4012BMJ/883
CD4014BMJ/883
CD4015BMJ/883
CD4016BMJ/883
CD40160BMJ/883
CD40161 BMJ/883
CD40162BMJ/883
CD40163BMJ/883
CD40174BMJ/883
CD40175BMJ/883
CD40192BMJ/883
CD40193BMJ/883
CD4020BMJ/883
CD4021 BMJ/883
CD4023BMJ/883
CD4025BMJ/883
CD4030MJ/883
CD4034BMJ/883
CD4035BMJ/883
CD4040BMJ/883
CD4041 MJ/883
CD4043BMJ/883
CD4044MJ/883
CD4046BMJ/883
CD4049UBMJ/883
CD4060BMJ/883
CD4066BMJ/883
CD4069MJ/883
CD4070BMJ/883
CD4071 BMJ/883
CD4072BMJ/883
CD4073BMJ/883
CD4075BMJ/883
CD4076BMJ/883
CD4081 BMJ/883
CD4089BMJ/883
CD4093BMJ/883
CD4099BMJ/883
Cb4503BMJ/883
CD4510BMJ/883
CD4511 BMJ/883
NSCID
INDUSTRYID
MM4601 BJ/883
MM4602BJ/883
MM4606BJ/883
MM4607AJ/883
MM4608BJ/883
MM4609AJ/883
MM54C14J/883
MM4611 BJ/883
MM4612BJ/883
MM4614BJ/883
MM4615BJ/883
MM4616BJ/883
MM54C160J/i383
MM54C161J/883
MM54C162J{883
MM54C163J/883
MM54C174J/883
MM54C175J/883
MM54C192J/883
MM54C193J/883
MM4620BJ/883
MM4621BJ/883
MM4623BJ/883
MM4625BJ/883
MM4630AJ/883
MM4634BJ/883
MM4635BJ/883
MM4640BJ/883
MM4641AJ/883
MM4643BJ/883
MM4644AJ/883
MM4646BJ/883
MM4649UBJ/883
MM4660BJ/883
MM4666BJ/883
MM54C04J/883
MM54C86J/883
MM4671 BJ/883
MM4672BJ/883
MM4673BJ/883
MM4675BJ/883
MM54C173J/883
MM4681BJ/883
MM4689BJ/883
MM4893BJ/883
MM4699BJ/883
MM14503BMJ/883
MM14510BMJ/883
MM14511 BMJ/883
6-12
NSCID
CD4512BMJ/883
CD4514BMJ/883
CD4515BMJ/883
CD4516BMJ/883
CD4518BMJ/883
CD4519BMJ/883
CD4520BMJ/883
CD4522BMJ/883
CD4526BMJ/883
CD4528BMJ/883
CD4529BMJ/883
CD4538BMJ/883
CD4541 BMJ/883
CD4543BMJ/883
CD4723BMJ/883
CD4724BMJ/883
MM14512BMJ/883
MM14514BMJ/8S3
MM14515BMJ/883
MM14516BMJ/883
MM14518BMJ/883
MM14519BMJ/883
MM14520BMJ/883
MM14522BMJ/883
MM14526BMJ/883
MM14528BMJ/883
MM 14529BMJ/883
MM 14538BMJ/883
MM14541BMJ/883
MM14543BMJ/883
. MM14723BMJ/883
MM14724BMJ/883
MM54COOJ/883
MM54C02J/883
MM54C04J/883
MM54C08J/883
MM54C10J/883
MM54C107J/883
MM54C14J/883
MM54C150J/883
MM54C151J/883
MM54C154J/883
MM54C157J/883
MM54C160J/883
MM54C161J/883
MM54C162J/883
MM54C163J/883
MM54C164J/883
MM54C165J/883
MM54C173J/883
MM54C174J/883
MM54C175J/883
MM54C192J/883
MM54C193J/883
MM54C195J/883
MM54C20J/883
MM54C200J/883
MM54C221J/883
MM54C240J/883
MM54C244J/883
MM54C30J/883
MM54C32J/883
MM54C373J/883
MM54C374J/883
MM54COOJ/883
MM54C02J/883
MM54C04J/883
MM54C08J/883
MM54C10J/883
MM54C107J/883
MM54C14J/883
MM54C150J/883
MM54C151J/883
. MM54C154J/883
MM54C157J/883
MM54C160J/883
MM54C161J/883
MM54C162J/883
MM54C163J/883
MM54C164J/883
MM54C165J/883
MM54C173J/883
MM54C174J/883
MM54C175J/883
MM54C192J/883
MM54C193J/883
MM54C195J/883
MM54C20J/8S3
MM54C200J/883
MM54C221J/883
MM54C240J/883
MM54C244J/883
MM54C30J/883
MM54C32J/883
MM54C373J/883
MM54C374J/883
INDUSTRYID
MM54C42J/883
MM54C48J/883
MM54C73J/883
MM54C74J/883
MM54C76J/883
MM54C83J/883
MM54C85J/883
MM54C86J/883
. MM54C89J/883
MM54C90J/883
MM54C901J/883
MM54C902J/883
MM54C903J/883
MM54C904J/883
NSCID
INDUSTRYID
MM54C42J/883
MM54C48J/883
MM54C73J/883
MM54C74J/883
MM54C76J/883
MM54C83J/883
MM54C85J/883
MM54C86J/883
MM54C89J/883
MM54C90J/883
MM54C901J/883
MM54C902J/883
MM54C903J/883
M M54C904J/883
MM54C905J/883
MM54C906J/883
MM54C907J/883
MM54C909J/883
MM54C910J/883
MM54C914J/883
M M54C915J/883
MM54C922J/883
MM54C923J/883
MM54C93J/883
MM54C941J/883
MM54C95J/883
MM54C989J/883
8·13
NSCID
MM54C905J/883
MM54C906J/883
MM54C907J/883
MM54C909J/883
MM54C910J/883
MM54C914J/883
MM54C915J/883
MM54C922J/883
M M54C923J/883
MM54C93J/883
MM54C941J/883
MM54C95J/883
MM54C989J/883
54HC/54HCT Product Availability
The following list of products represents what is currently
available for 883B. As new products are brought on board,
notification will take place through news releases. For fur·
ther data on the products and families, please contact
your local sales office.
PACKAGE CROSS REFERENCE
NSC ORDER NUMBER
MOTOROLA EQUIVALENT DESIGNATION
PACKAGE
54HC/HCTXXJ/883B
54HC/HCTXXBCAJC
Cavity DIP (J·14)
54HC/HCTXXJ/883B
54HC/HCTXXJ/883B
54HC/HCTXXBEAJC
54HC/HCTXXBRAJC
Cavity DIP (J·16)
Cavity DIP (J·20)
54HC/HCTXXJ/883B
54HC/HCTXXBJAJC
Cavity DIP (J·24)
INDUSTRYID
MM54HCU04J/883
MM54HCOOJ/883
MM54HC02J/883
MM54HC03J/883
MM54HC04J/883
MM54HC08J/883
MM54HC10J/883
MM54HC107J/883
MM54HC109J/883
MM54HC11J/883
MM54HC112J/883
MM54HCl13J/883
MM54HC123AJ/883
MM54HC125J/883
MM54HC132J/883
MM54HC133J/883
MM54HC137J/883
MM54HC138J/883
MM54HC139J/883
MM54HC14J/883
MM54HC147J/883
MM54HC149J/883
MM54HC151J/883
MM54HC153J/883
MM54HC154J/883
MM54HC155J/883
MM54HC157 J/883
MM54HC158J/883
MM54HC160J/883
MM54HC161J/883
MM54HC162J/883
MM54HC163J/883
MM54HC164J/883
MM54HC165J/883
MM54HC173J/883
MM54HC174J/883
MM54HC175J/883
MM54HC181 J/883
MM54HC182J/883
M M54HC190J/883
MM54HC191J/883
MM54HC192J/883
MM54HC193J/883
MM54HC194J/883
MM54HC195J/883
MM54HC20J/883
NSCID
INDUSTRYID
MM54HCU04J/883
MM54HCOOJ/883
MM54HC02J/883
MM54HC03J/883
MM54HC04J/883 .
MM54HC08J/883
MM54HC10J/883
MM54HC107J/883
MM54HC109J/883
MM54HC11 J/883
MM54HC112J/883
MM54HC113J/883
MM54HC123AJ/883
MM54HC125J/8B3
MM54HC132J/BB3
MM54HC133J/BB3
MM54HC137J/883
MM54HC13BJ/BB3
MM54HC139J/883
MM54HC14J/BB3
MM54HC147J/BB3
MM54HC149J/8B3
MM54HC151J/B83
MM54HC153J/BB3
MM54HC154J/883
MM54HC155J/BB3
MM54HC157J/BB3
MM54HC15BJ/883
MM54HC160J/BB3
MM54HC161 J/8B3
MM54HC162J/883
MM54HC163J/BB3
MM54HC164J/B83
MM54HC165J/BB3
MM54HC173J/883
MM54HC174J/883
MM54HC175J/883
MM54HC181J/BB3
MM54HC182J/883
MM54HC190J/883
MM54HC191J/883
MM54HC192J/883
MM54HC193J/883
MM54HC194J/883
MM54HC195J/883
MM54HC20J/883
MM54HC221AJ/B83
MM54HC237 J/883
MM54HC240J/883
MM54HC241J/883
MM54HC242J/883
MM54HC243J/883
MM54HC244J/883
MM54HC245J/883
MM54HC251J/B83
MM54HC253J/8B3
MMp4HC257 J/883
MM54HC259J/883
MM54HC266J/883
MM54HC27 J/883
MM54HC273J/883
MM54HC280J/883
MM54HC283J/883
M M54HC298J/883
MM54HC299J/883
M M54HC30J/883
MM54HC32J/883
MM54HC354J/883
MM54HC356J/883
MM54HC365J/883
MM54HC366J/883
MM54HC367J/883
MM54HC368J/883
M M54HC373J/883
MM54HC374J/883
MM54HC390J/883
MM54HC393J/883
MM54HC4002J/883
MM54HC4016J/883
MM54HC4017J/883
MM54HC4020J/883
MM54HC4024J/883
MM54HC4040J/883
MM54HC4046J/883
MM54HC4049J/883
MM54HC4050J/883
MM54HC4051J/883
MM54HC4052J/883
M M54HC4053J/883
MM54HC4060J/883
MM54HC4066J/883
MM54HC4075J/883
8·14
NSCID
MM54HC221 AJ/883
MM54HC237J/883
MM54HC240J/883
MM54HC241 J/883
MM54HC242J/883
MM54HC243J/883
MM54HC244J/883
MM54HC245J/883
MM54HC251 J/883
MM54HC253J/883
MM54HC257J/883
MM54HC259J/883
MM54HC266J/883
MM54HC27 J/883
MM54HC273J/883
MM54HC28OJ/883
MM54HC283J/883
MM54HC298J/883
MM54HC299J/883
MM54HC30J/883
MM54HC32J/883
MM54HC354J/883
MM54HC356J/883
MM54HC365J/883
MM54HC366J/883
MM54HC367J/883
MM54HC3€\8J/883
MM54HC373J/883
MM54HC374J/883
M M54HC390J/883
MM54HC393J/883
MM54HC4002J/883
MM54HC4016J/883
MM54HC4017J/883
MM54HC4020J/883
MM54HC4024J/883
MM54HC4040J/883
MM54HC4046J/883
MM54HC4049J/883
MM54HC405OJ/883
MM54HC4051J/883
MM54HC4052J/883
MM54HC4053J/883
MM54HC4060J/883
MM54HC4066J/883
MM54HC4075J/883
INDUSTRY ID
NSCID
INDUSTRYID
M M54HC4078J/883
MM54HC42J/883
MM54HC423AJ/883
MM54HC4316J/883
MM54HC4511 J/883
MM54HC4514J/883
MM54HC4538J/883
MM54HC4543J/883
MM54HC51J/883
MM54HC521 J/883
MM54HC533J/883
MM54HC534J/883
MM54HC540J/883
MM54HC541 J/883
MM54HC563J/883
MM54HC564J/883
MM54HC573J/883
MM54HC574J/883
MM54HC58J/883
MM54HC589J/883
MM54HC590J/883
MM54HC592J/883
MM54HC593J/883
MM54HC595J/883
MM54HC597 J/883
MM54HC640J/883
MM54HC643J/883
MM54HC646J/883
MM54HC648J/883
MM54HC688JI883
MM54HC73J/883
MM54HC74JI883
MM54HC75J/883
MM54HC76J/883
MM54HC86J/883
MM54HCTOOJ/883
MM54Hc'T04J/883
MM54HCT05JI883
:v1M54HCT08J/883
MM54HC4078J/883
MM54HC42J1883
MM54HC423AJ/883
MM54HC4316J/883
MM54HC4511J/883
MM54HC4514J/883
MM54HC4538J/883
MM54HC4543J/883
MM54HC51 J/883
MM54HC521J/883
MM54HC533J/883
MM54HC534J/883
MM54HC540J/883
MM54HC541J/883
MM54HC563J/883
MM54HC564J/883
MM54HC573J/883
MM54HC574J/883
MM54HC58J/883
MM54HC589J/883
MM54HC590J/883
MM54HC592J/883
. MM54HC593JI883
MM54HC595J/883
MM54HC597J/883
MM54HC640J/883
MM54HC643J/883
MM54HC646J/883
MM54HC648J/883
MM54HC688J/883
MM54HC73J/883
MM54HC74JI883
MM54HC75J/883
MM54HC76J/883
MM54HC86JI883
MM54HCTOOJ/883
M M54HCT04JI883
MM54HCT05J/883
MM54HCT08J/883
MM54HCT109J/883
MM54HCTl12J/883
MM54HCT138J/883
MM54HCT139J/883
MM54HCT149J/883
MM54HCT155J/883
MM54HCT157 J/883
MM54HCT158J/883
MM54HCT164J/883
MM54HCT191J/883
M M54HCT193J/883
MM54HCT240J/883
MM54HCT241 J/883
MM54HCT244J/883
MM54HCT24.5J/883
MM54HCT257 J/883
MM54HCT273J/883
MM54HCT299J/883
MM54HCT34J/883
MM54HCT373J/883
MM54HCT374J/883
MM54HCT521J/883
MM54HCT533J/833
M M54HCT534J/883
M M54HCT540J/883
M M54 HCT541 J/883
MM54HCT563J/883
M M 54HCT564J/883
MM54HCT573J/883
M M54HCT57 4J/883
MM54HCT590J/883
MM54HCT592J/883
MM54HCT593J/883
MM54HCT640J/883
MM54HCT643J/883
MM54HCT688J/883
MM54HCT74J/883
MM54HCT76JI883
8·15
NSCID
MM54HCT109J/882
MM54HCTl12J/883
MM54HCT138J/883
MM54HCT139J/883
MM54HCT149J/883
MM54HCT155J/883
MM54HCT157 J/883
MM54HCT158J/883
MM54HCT164J/883
MM54HCT191J/883
MM54HCT193J/883
MM54HCT240J/883
MM54HCT241 J/883
MM54HCT244J/883
MM54HCT245J/883
MM54HCT257J/883
MM54HCT273J/883
MM54HCT299J/883
MM54HCT34J/883
MM54HCT373J/883
MM54HCT374J/883
MM54HCT521 J/883
MM54HCT533J/883
MM54HCT534J/883
MM54HCT540J/883
MM54HCT541 J1883
MM54HCT563J/883
MM54HCT564JI883
MM54HCT573J/883
MM54HCT574J/883
MM54HCT590J/883
MM54HCT592J/883
MM54HCT593J/883
MM54HCT640J/883
MM54HCT643J/883
MM54HCT688J/883
MM54HCT74J/883
MM54HCT76J/883
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8-17
RADIATION HARDENED TECHNOLOGIES
FROM NATIONAL SEMICONDUCTOR
For many years, military, aerospace and satellite
programs have depended on bipolar transistor,
and integrated circuit technology in the fabrication of airborne systems. Development of bipolar technology is an outgrowth, in part, of avionics and space applications needs .. Despite
their relatively high immunity or resistance to
high levels of both constant and burst radiation
in the form of gamma rays, x-rays, cosmic rays,
and so on, bipolar devices have two drawbacks:
a susceptibility to damage from neutron fluxes,
and high power consumption, which adds to the
power supply requirements and subtracts from
the usable payload of spacecraft and missiles.
In addition, recent decreases in bipolar feature
sizes and changes in bipolar design and fabrication techniques have led to bipolar devices
which exhibit the same level of susceptibility to
ionizing radiation that had historically been
seen in MOS devices. The spacecraft and missile industry has long needed a radiation hardened logic technology with low power consumption that would readily lend itself to reliable
fabrication processes with reasonable repeatability. The purpose of this brochure is to provide some information to the potential user regarding National Semiconductor's solutions to
radiation problems.
CMOS Radiation Hardened Products
ened CMOS logic products utilizing a radiation
hardening process that is compatible with volume processing. Products hardened to withstand 10 megarads [devices capable of tolerating total dose radiation of 107 rads (Si)] are the
result of an intensive multi-year research and development program in cooperation with Sandia
Laboratories (Albuquerque, NM). This program
has enabled Nati.onal Semiconductor to offer
radiation hard versions of virtually our entire
metal-gate CMOS product line.
Devices ranging in complexity from simple
gates to large scale integration (LSI) random
access memories have been hardened using the
processes we developed. The achievement of
this level of radiation resistance in a mass pro. duct ion CMOS process required that we implement major modifications to the basic commercial process, in the gate oxidation, substrate and
P-tub surface concentrations, and metallization.
We-are currently in the process of research and
development efforts aimed at extending these
radiation improvements into complex metal gate
devices (such as analog-to-digital converters "and gate arrays), and into silicon ·gate processes. This will enable us to provide radiation
hardened devices within our 54HC logic family,
.our microCMOS memories and microprocessors,
and our microCMOS gate arrays.
Over the years, the development of sophisticated space, satellite and military systems and
mission requirements fostered an active search
for a radiation hardened logic circuit technology
that consumes less power and offers a higher
degree of circuit integration on a single silicon
chip. Metal oxide semiconductor (MOS) devices,
particularly complementary MOS (CMOS), provided just such an alternative. But standard
CMOS devices, even those qualified to MIL-M38510 (JAN) requirements, proved sensitive to
relatively low levels of gamma (or total dose)
radiation, as low in many cases as 3 x 103 rads
(Si)t. Early generations of mass-producible specifically radiation hardened CMOS devices were
able to withstand oniy 105 rads (Si), while many
space, satellite and missile systems require circuitry resistance levels at least ten times higher,
106 rads (Si).
.
Bipolar vs_ CMOS
Bipolar devices and CMOS devices respond differently to different forms of radiation as a result of basic differences in both structure and
operation. As Figure 1 shows, bipolar devices
depend upon the diffusion of minority carriers
for current flow through the base region. When
bipolar devices are subject to neutron irradiation, the resulting crystal damage decreases
minority carrier lifetime, causing severe performance degradation. On the other hand, bipolar
devices are usually relatively insensitive to surfac·e effects resulting from charge buildup in the
oxide layer. Thus ionizing radiation has little effect on many bipolar structures. However, some
National Semiconductor developed a solution to
this problem: a complete line of megarad hard1. One rad (Si) is the quantity of any type of ionizing radiation
which Imparts 100 ergs of energy per gram of silicon.
883BIRETS™, 883SIRETS™ are trademarks of National
Semiconductor Corporation.
FIGURE 1_ Bipolar IC Transistor
8-18
recently developed bipolar technologies contain
unhardened parasitic MOS structures as a result
of the oxide isolations and walled emitter processes that they utilize.
age turns off the device. In the alternative mode,
depletion, current flows despite the gate voltage
being zero, because sufficient charge is present
at the silicon/silicon-dioxide interface to induce
a conductive path between the device source
and drain regions. The P-channel MOS transistor
is similar to the N-channel alternative, except
that negative voltage applied to the gate, with
respect to source, induces a positively charged
conductive path between source and drain to
.
turn the device Qn.
CMOS devices (see Figure 2) are surface effect
devices. The equivalent operating elements,
gate, source and drain, are at the surface, and
the flow of current occurs horizontally across
the device, very close to the silicon/silicondioxide interface. Their characteristics are determined by electrostatic conditions at the silicon/silicon·dioxide interface. Carriers originate
in the source region, and CMOS devices depend
upon majority carriers for their operation. They
are therefore not seriously affected by the
minority carrier lifetime degradation resulting
from neutron irradiation. They are, however, susceptible to charge in the oxide or at the oxidesubstrate interface. Although gamma radiation
will ionize both the oxide and the substrate, the
resulting ionic charge cannot become trapped in
the relatively conductive substrate as easily as it
can be trapped in the insulating oxide. CMOS
devices are therefore much more susceptible
than bipolar devices to degradation from gamma
radiation.
Conventional CMOS logic circuits are produced
with only enhancement mode N- and P-channel
devices. The process is designed to give turn on
(threshold) voltage values for both types of devices which insure proper circuit performance.
Figure 3 illustrates the cross section of a CMOS
structure connected in a simple inverter configuration. To form the standard metal gate CMOS
structure, a lightly doped P-tub is formed by diffusion into an N-type substrate with the tub becoming the substrate for the N-channel transistor. The N + and P + impurities are diffused into
P-tub and N-substrates to become the N- and Pchannel transistors' source and drain regions,
respectively. These diffusions also serve as contacting regions to the positively biased N-substrate and the normally grounded P-tub regions
(V DD and Vss , respectively).
VIN
Voo
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FIGURE 2. CMOS IC Transistor
CMOS IC Transistor Structures
\II
SUBSTRATE
FIGURE 3. CMOS Transistor Structure in Simple
Inverter Configuration
Complementary MOS, or CMOS, combines two
types of MOS devices, P-channel and N-channel
structures, into a single functioning unit. The
lower power dissipation and high stability resulting from this complementary combination is
particularly attractive in the design of portable
battery-powered electronic units, or for applications where a battery provides standby power.
A gate oxide is grown such that a thin film of dielectric oxide material bridges all source/drain
regions. Finally, contact apertures are etched to
the source/drain regions and an aluminum film
evaporated and etched to form gate electrodes,
contacts to device terminals, and interconnecting conductor lines.
MOS structures, both N- and P-types, perform in
two modes; enhancement and depletion. In an
N-channel enhancement mode MOS device, for
example, the gate controls the current flow between the source and drain. In this device, when
a positive voltage is applied to the gate with respect to the source, a field is set up across the
gate dielectric, producing a negatively charged
conductive path, a channel, between the source
and the drain. This is known as an enhancement
mode device because zero gate to source volt-
Effects of Ionizing Radiation
A CMOS transistors' radiation resistance is
primarily determined by formation of the gate
structures in both P-channel and N-channel devices. The gate structures are used to turn the
MOS devices on or off; that is, to enable or prevent a flow of current from the source to the
8-19
drain. Ionizing radiation induces unwanted positive charge into the gate oxide structure, resulting in lower threshold voltages for both actual
circuit devices and parasitic field oxide devices
by as much as 30V or more. Figure 4 shows the
charge buildup mechanisms in an N-channel
gate oxide during irradiation under worst-case
bias. In establishing a radiation hardened CMOS
process, it is necessary to incorporate processing steps which minimize' these radiationinduced shifts in critical locations of the IC
structure.
CMOS Process Modification
Gate Oxidation
To minimize both the radiati<;>n-induced positive
oxide charge and formation of Si·Si0 2 interface
states, a dry oxidation step is used. The gate
oxide is thermally grown in a dry oxygen atmo·
sphere at 1000·C, followed by a nitrogen anneal
at 850·C. This cycle has been empirically found
to produce oxides having a high degree of resis·
tance to ionizing radiation effects as well as ex·
cellent pre·radiation MOS characteristics. 2 The
need to thermally grow gate oxides at 1000·C in
dry oxygen for optimal radiation hardness is one
of the more intriguing aspects of this experimentally deduced cycle.
+ 10V
Metallization
A by-product of the E·beam aillminum evapora·
tion process commonly used in commercial IC
fabrication is soft X·radiation. This radiation pro·
duces the same type of positive charge in the
gate oxide and interface states which a radiation
hardened oxide should resist. Although these
harmful effects in the gate oxide can be removed
by an anneal cycle, the annealled devices are
significantly less resistant to subsequent ionizing radiation. Use of a non·E-beam metallization
technique circumvents the problem of high
threshold shifts due to irradiation under zero
and negative gate bias assoc,iated with soft
X·ray damage. For this reason, induction heated
evaporation of aluminum is used to fabricate
radiation hardened CMOS products.
FIGURE 4. Charge Buildup Mechanisms in an
N·Channel Gate Oxide during
Irradiation under Worst·Case Bias
The impact of radiation-induced oxide charge on
operating CMOS devices is to decrease the Nchannel threshold vollage, VTN , and increase the
magnitude of the P-channel threshold voltage,
VTP ' The most serious problem occurs when sufficient reduction' in VTN ' occurs to cause the
N'channel device to go from enhancement to de·
pletion mode operation. This results in exces-,
sive power supply current drain and loss of cir·
cuit functionality. The most severe stress on an
N·channel device occurs when its gate is positively biased during irradiation. This causes positive charge in the oxide to be driven closer to
the Si-Si0 2 interface where it is more effective
in causing. inversion at the P-type substrate
surface.
Substrate and P·Tub Surface
The deleterious effect of ionizing radiation on
VTN and VTP values in a CMOS device can be
minimized through process modification. In anticipation of these threshold voltage shifts, radio
ation hardened CMOS devices are designed with
the initial value of VTN as high as possible and
VTP as close to zero as possible without sacrificing pre·radiation circuit performance. Both the
substrate resistivity and the P·tub surface concentration have been modified with the initial
. value of VTN being increased to 1.8 volts from
the standard value of 1.3 volts and VTP being
changed from the standard - 1.7 volts to -1.3
volts.
In normal operation, positive bias cannot appear
between the gate and substrate of P·channel
devices because the substrate is already at the
most positive circuit potential, Voo. The absolute value of VTP always increases with exposure
to irradiation, and the magnitude of the shift is
usualiy smaller than the VTN shift. The effect of
the VTN is less deleterious to circuits, however,
since the devices will never reach' depletion
mode.
2. W. R. Dawes, Jr., G. F. Derbenwich and B. L. Gregory, "Pro·
cess Technology for Radiation Hardened CMOS Integrated
Circuits," IEEE Journal of Solid State Circuits, SC-ll, No.4,
p. 459, August 1976.
8·20
Performance Characteristics
toward its initial value as dose level is increased
even further while increases in VTP still remain
within reasonable limits for satisfactory circuit
operation.
Extended Total Dose Rate [to 108 Rads (Si)]
Data generated in the course of our testing indio
.cates that the resistance of our CMOS products
extends at least one order of magnitude above
the 107 level we now offer. Figure 5 illustrates
measured shifts from pre·irradiation values in
P·and N·channel threshold voltage, VTP and VTN ,
respectively, up to total dose levels of 108 rads
(Sil. Of special interest is the change in slope of
the VTN versus dose characteristic at levels just
above the 106 rads (Si). At this level, a reduction
in the net positive charge trapped in the gate
oxide is observed. This causes VTN to return
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The distributions of the VTN and VTP data are
found to be normal both before and after irradia·
tion. The mean value of VTN and VTP ' and the
standard deviation from the mean for both N·
and P·channel devices, remain fairly constant
from the unirradiated state through 106 rads (Sil
dosage. The values shown remain well above the
300mV VTN lower limit, below which the device
would tend toward N·channel depletion mode
behavior with a risk of lost circuit functionality
as well as excessive supply current drain.
3
2
,
NORMALIZED
,.:.
PRE.R~D VTN
........~-
...
CI>
C
//
,//
-------
------
~
... "
CI>
~
>
0
...
-1
..,
-2
...co
-3
co
Q.
>
c
c
,.:.
NORMALIZED PRE·RAD VTP
----;,;,;:.:-----,
CI>
~
, '
.........~,
,,
X
--- X±lu
105
106
TOTAL DOSE (RADS Si)
FIGURE 5. Variation
of VTN and VTP with Radiation
Figure 6 illustrates the supply quiescent current
(Iss) variation as a fun.ction of dose. Since Iss is a
function of die size, curves have been plotted for
three levels of integration, SSI, MIS, and LSI. In
all cases, the leakage level at 106 rads (8i) does
not increase by mor.e than an order of magnitude
from the initial value. The 30ILA reading at 106
rads (8i) for LSI is far below the high tempera·
ture (125°C) specification of 600ILA for standard
devices. Similar comparisons can be made for
MSI and 881.
10'
LSI
10'
L----...:..---....:::------
MSI
,"mAl 11 nA AVG
INmAl 5 nA AVG
551
5
10'
DOSE (RAOS III
FIGURE 6. Iss vs. Dose
8·21
6
7 8 9 10'
Hardness Assurance and Reliability
Figure 7 illustrates circuit propagation delay,
t po, as a function of dose. The plot, similar to
Figure 6, is divided into three categories (LSI,
MSI, and SSI). The propagation delay value at 106
rads (Si) for all three categories increased
roughly 20-25% from the initial value, well with·
in desirable operating tolerances. In Figures 5
through 7, the biasing conditions during irradia·
tion were: Voo= 10V, V,N = 10V, Vss=OV.
Sampling plans have been established to ensure
radiation hardness to 105, 106, or 107 rads (Si), as
applicable,. since ionizing radiation degrades IC
performance and irradiated devices cannot be
used for production (thus making 100% screening impossible). In addition, an ongoing program
has been established to evaluate the reliability
characteristics' of radiation hardened CMOS
circuits. 476 devices of the CD4001AD·RH;
CD4011AD·RH, and MM54C200·RH types were
initially tested and operated for over 800,000
hours without a failure. This corresponds to a
failure' rate less than 0.125%/1000 hours at
125°C with a 60% confidence level. The continuo
ing testing is aimed at verifying 10,000 hours per
device of reliable operation~
C,=50pF
250
lSi
INmAl
220•• AVG.
200
MSI
INmAl
;;; 150
160 •• AVG.
!!.
J
100
551
IIIITlAl
50
Table I outlines National Semiconductor's Radi·
, ation Hardness Assurance Sampling Plan, which
Is totally compliant with MIL-STD·883, Method
1019. This plan is used to assure hardness of
devices built from a given wafer or inspection
lot. Sample devices are assembled in accor·
dance with sampling plan A or B. Sample de·
vices are tested, irradiated; and retested, and
must pass the appropriate post-radiation elec·
trical limits for the lot to be qualified. The pro·
duction units are capable of meeting MIL-M·
38510 electrical test limits, when available, as
well as National's RETS limits.
65 •• AVG.
4
10'
5
6
7 8 9 10'
DOSE (RADS II)
FIGURE 7. t pD vs. Dose
TABLE I. Hardness Assurance Plan
I.
Plan A - Class B only: Qualification to 1 X 105, 1 X 106 , or 1 x 107 rads (Si)
Sample Size per QCI Inspection Lot
Accept Level
Reje<.:t Level
II. Plan B - Class B or S: Qualification to 1 X 105, 1 X 106, or 1 x 107 rads (Si)
Sample
Sample Size (Devices/Wafer)
,
Accept Level
,
Reject Level
III. Product Flow (per MIL·STD-883, Method 1019):
A. Assemble sample pevices in appropriate production package.
B. Read-and·record electrical parameters (pre-radiation).
C. Irradiate to applicable total gamma dose.
D. Read·and-record electrical parameters (post·radiation).
E. Evaluate perform'ance per applicable specification.
8·22
11
o Rejects
1 Reject
Each.wafer
4
oRejects per wafer
1 Reject per wafer
TABLE II·A. Pre· and Post·Radiation Specification 105 Rads (Si)
LIMITS (Note 1)
PARAMETER
Voo
CONDITIONS
-55°C
Min
MClX
+25°C
Min
Max
+.125°C
Min
UNITS
Max
Gate
5
10
15
0.02
0.04
.0.D75
0.02
0.04
0.075
0.2
0.4
0.75
p.A
Buffer F/F
5
10
15
0.3
0.4
0.5
0.3
0.4
0.5
3.0
4.0
5.0
p.A
0.3
0.4
0.5
0:3
0.4
0.5
3.0
4.0
5.0
p.A
10
20
40
10
20
40
150
300
600
p.A
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
V
100
VIN = Voo or Vss
All Valid Input Combinations
MSI
5
10
15
LSI
5
10·
15
VOL
5
10
15
V IN = Voo or Vss
1101 < 10p.A
VOH
5
10
15
V IN = Voo or Vss
1101 < 10p.A
Buffered
5
10
15
VO= 0.5V, 4.5V
VO= 1V, 9V, 1101
VO= 1.5V, 13.5V
Unbuffered
5
10
15
VO;'1.5V,3.5V
VO=3V,7V 1101
VO=4V,11V
5
10
15
5
10
15
VO = 0.5V, 4.5V
VO= 1V, 9V 1101
VO= 1.5V, 13.5V
VO = 1.5V, 3.5V
VO=3V,7V 1101
VO=4V,11V
15
V IN = OV or 15V
Any Valid Condition
V IL
Buffered
V IH
Unbuffered
liN
IOLlloH
t pLH , tpHL
t TLH , tTHL
Functionality
4.95
9.95
14.95
< 10p.A
< 10p.A
< 10p.A
< 10p.A
4.95
9.95
.14.95
4.95
9.95
14.95
V
1.5
3.0
4.0
1.5
3.0
4.0
1.5
3.0
4.0
V
1.5
3.0
4.0
1.5
3.0
4.0
1.5
3.0
4.0
V
3.5
7.0
11
3.5
7.0
11
3.5
7.0
11
3:5
7.0
11
±10
3.5
7.0
11
3.5
7.0
11
±10
V
V
±45
Per Applicable Rei Electrical
Test Spec (RETS)
Published Data Sheet Limit
Per Applicable Rei Electrical
Test Spec (RETS)
Published Data Sheet Limit
Devices Will Pass Functional Test per Applicable Truth Table
Note 1: For further device parameters, see individual device specifications.
Note
These limits allow no degradation from the published data sheet limits.
2:
8·23
nA
TABLE II-B. Post-Radiation Specification 106 Rads (Si)
LIMITS (Note 1)
PARAMETER
Voo
CONDITIONS
-55°C
Min
Max
+25°C
Min
Max
+ 125°C
UNITS
Min' Max
Gate
5
10
15
0.5
0.75
1.0
0.5
0.75
1.0
5.0
7.5
1.0
p.A
Buffer F/F
5
10
15
0.25
0.5
1.0
0.25
0.5
1.0
5.0
7.5
10.0
,p.A
3.0
4.0
5.0
3.0
4.0
5.0
30.0
40.0
50.0
p.A
25
50
100
25
50
100
300
400
500
p.A
0.25
0.25
0.25
0.25
0.25
0.25
0.25
0.25
·0.25
V
100
MSI
5
10
15
V IN = Vss or V.oo
All Valid Input Combinations
5
10
15
5
10
15
V IN = Vss or Voo
1101 < 10p.A
5
10
15
V IN = Vss or Voo
1101 < 10p.A
Buffered
5
10
15
VO = 0.5V, 4.5V
VO = iV, 9V, 110 I < 10p.A
VO = 1.5V, 13.5V
1.0
2.0
2.5
1.0
2.0
2.5
1.0
2.0
2.5
V
Unbuffered
5
10
15
VO= iV,4V
' VO = 2V, BV 110 I < 10p.A
VO = 2.5V, 12.5V
1.0
2.0
2.5
1.0
2.0
2.5
1.0
2.0
2.5
V
5
10
15
5
10
15
VO = 0.5V, 4.5V
VO= iV, 9V 1101 < 10p.A
VO= 1.5V, 13.5V
VO= iV, 4V
VO=2V, BV 1101 < 10p.A
VO = 2.5V, 12.5V
15
V IN = OV or 15V
Any Valid Condition
LSI
VOL
VOH
VIL
Buffered
VIH
Unbuffered
liN
10L/IoH
t pLH , t pHL
t TLH , tTHL
Functionality
4.75
9.75
14.75
4.75
9.75
14.75
4.0
B.O
12.5
4.0
B.O
12.5
4.75
9.75
14.75
4.0
B.O
12.5
4.0
B.O
12.5
± 100
V
4.0
B.O
12.5
4.0
B.O
12.5
± 100
V
V
± 100
Per Applicable Rei Electrical
Test Spec (RETS)
Minimum Limit is 75% of Published
Data Sheet Limit
Per Applicable Rei Electrical
Test Spec (RETS)
Maximum Limit is 125% of Published
Data Sheet Limit
Devices Will Pass Functional Test per Applicable Truth Table
Note 1: For other device parameters, see individual device specifications.
8·24
nA
TABLE II·C. Post·Radiation Specification 107 Rads (Si)
LIMITS (Note 1)
PARAMETER
Voo
Gate
5
10
15
3.0
4.0
5.0
3.0
4.0
5.0
10
15
20
}LA
Buffer F/F
5
10
15
3.0
4.0
5.0
5,0
7.5
10.0
3.0
4.0
5.0
5.0
10
20
}LA
5.0
7.5
19·0
50
100
200
0.5
0.5
0.5
50
75
100
}LA
100
CONDITIONS
VIN=VSSorVoo
All Valid Input Combinations
5
10
15
MSI
-55°C
Min Max
+25°C
Min Max
5
10
15
5
10
15
VIN = Vss or Voo
1101 < 10}LA
5
10
15
VIN=V SS orVoo
1101 < 10}LA
Buffered
5
10 .
15
VO = 0.5V, 4.5V
VO=1V,9V, 1101 < 10}LA
VO= 1.5V, 13.5V
1.0
2.0
2.5
1.0
2.0
2.5
1.0
2.0
2.5
V
Unbuffered
5
10
15
VO= iV, 4V
VO=2V, BV 1101 < 10}LA
VO = 2.5V, 12.5V
1.0
2.0
2.5
1.0
. 2.0
2.5
1.0
2.0
2.5
V
5
10
15
5
10
15
VO = 0.5V, 4.5V
VO= iV, 9V 1101 < 10}LA
VO= 1.5V, 13.5V
VO= 1V, 4V
VO=2V, BV 1101 < 10}LA
VO= 2.5V, 12.5V
15
VIN = OV or 15V
Any Valid Condition
LSI
VOL
V OH
V IL
'.
Buffered
VIH
Unbuffered
liN
IOLlloH
t pLH , t pHL
t TLH , tTHL
Functionality
50
100
200
0.5
0.5
0.5
+ 125°C UNITS
Min Max
4.5
9.5
14.5
4.5
9.5
14.5
4.0
B.O
12.5
4.0
B.O
12.5
4.5
9.5
14.5
4.0
B.O
12.5
4.0
B.O
12.5
± 100
500
750
1000
0.5
0.5
0.5
V
V
± 100
Per Applicable Rei Electrical
Test Spec (RETS)
Minimum Limit is 65% of Published
Data Sheet Limit
Per Applicable Rei Electrical
Test Spec (RETS)
Maximum Limit is 140% of Published
Data Sheet Limit
Devices Will Pass Functional Test per Applicable Truth Table
Note 1: For other device parameters, see individual device specifications.
8-25
V
V
4.0
B.O
12.5
4.0
B.O
12.5
± 100
}LA
nA
TABLE III.
Post.R~diation Specification Comparison (25°C)
LIMITS (Note 1)
105 Rads
(Si)
CONDITIONS
106 Rads
(Si)
107 Rads
(Si)
UNITS
PARAMETER
Voo
Gate
5
10
15
0.02
0.04
0.075
0.5
0.75
1.0
3.0
4.0
5.0
p,A
Buffer F/F
5
10
15
0.3
0.4
0.5
0.25
0.5
1.0
3.0
4.0
5.0
p,A
MSI
5
10
15
0.3
0.4
0.5
3.0
4.0
5.0
5.0
7.5
10.0
p,A
LSI
5
10
15
10
20
40
25
50
100
50
100
200
p,A
0.05
0.05
0.05
0.25
0.25
0.25
0.5
0.5
0.5
V
Min
100
VIN=V SS or Voo
All Valid Input
,Combinations
VOL
5
10
15
VIN = Vs's or Voo
1101 < 10p,A
,V OH
5
10
15
VIN=VSSorVoo
1101 < 10p,A
Buffered
5
10
15
Unbuffered
5
10
15
V IL
Buffered
V IH
Unbuffered
liN
5
10
15
5
10
15
15
4.95
9.95
14.95
va = 0.5V,
4.5V
VO=1V,9V, 1101
VO= 1.5V, 13.5V
VO= Note 2
Max
4.75
9.75
14.75
Min
Mlix
4.5
9.5
14.5
V
10p,A
1.5
3.0
4.0
1.0
2.0
2.5
1.0
2.0
2.5
V
1101. <
10p,A
1.5
3.0
4.0
1.0
2.0
2·9
1.0
2.0
2.5
V
4.5V
VO= 1V, 9V 1101
VO= 1.5V, 13.5V
<
10p,A
1101 <
10p,A
3.5
7.0
11
3.5
7.0
11
VIN = OV or 15V
Any Valid Condition
IOLlioH
t pLH , t pHL
t TLH , tTHL
Per Applicable Rei Electrical
Test Spec (RETS)
4.0
8.0
12.5
4.0
8.0
12.5
4.0
8.0
12.5
4.0
8.0
12.5
±10
Per Applicable Rei Electrical
Test Spec (RET$)
Functionality
Min
<
va = 0.5V,
VO= Note 2
Max
±100
75%
of
Data
Sheet
Data
Sheet
Limit
Data
Sheet
V
V
±100
nA
60%
of
Data
Sheet
125%
of
Data
Sheet
140%
of
Data
Sheet
Devices Will Pass Functional Test per Applicable Truth 'Table
Nole 1: All 105 rads (Si) limils allow no degradation from published dala sheet limits.
Nole2: AI 105 rads (Si), VO will be 10% or 90% of Voo; all06 cirl07 rads (Si), VO will b,e lVor4Vat VOO=5V, 2VorBV at VOO= 10V, and
2,5V or 12,5V at VOO= 15V, /
8·26
vertical NPN which comprise the Schottky diode
are normally prevented from becoming forwardbiased by the circuit metallization. Because of
this, the Schottky diode will be in the off state
during normal circuit operation and will pose no
threat to reliable circuit performance.
Dose Rate Performance
When CMOS ICs are subjected to large bursts of
ionizing radiation, hole-electron pairs are created in the silicon substrate. The resultant current flowing through the high resistivity P- and
N-substrates can cause voltage differences
which may impair circuit performance in one of
. the following ways.
Sufficiently high values of burst radiation can
cause currents to flow through substrate resistances, RN _ and Rp _, to cause forward-biasing
of the parasitic PNP and NPN emitter-base junctions and turn on the Schottky diode. The excessive flow of supply current which accompanies
turn-on of the Schottky diode has been found to
occur in the range of 108 to 10 1 rads (Si)/sec on
many CMOS circuits.
One: LATCH-UP
A CMOS circuit contains the structural elements
required to form a four-layered Schottky diode
switching device as illustrated in Figure 8. The
emitter-base junctions of the lateral PNP and
N-CH
P-CH
DRAIN
DRAIN
N-
FIGURE 8_ Cross Section of CMOS Circuit Elements which May
Lead to Latch-Up during Ionizing Radiation Bursts
VDD
The basic circuit required for latch-up to occur is
illustrated in Figure 9. It consists of a parasitic
. bipolar NPN and PNP transistor sharing a common collector-base junction. The two requirements necessary for turn on of this device are:
P+
t-----eN-
1. The product of the common emitter current
gains of the two devices, (3 and (3PNP must
satisfy the relationship ((3NPN) ((3PNP) ~ 1, and
p- . .----~
2. The emitter-base junction of the two transistors must remain forward-biased to about
0.6V or greater after the NPNP device has
been turned on.
L..------4N+
In normal operation, condition No.1 may be met,
but condition No.2 will not be met, permitting
latch-up-free operation.
Vss
FIGURE 9_ Latch·Up Equivalent Circuit for
Bulk CMOS Structure
8-27
This problem .can be completely eliminated by
reducing to less than unity the product of the
common emitter current gains of the NPN and
PNP devices comprising the Sphottky diode.
One technique which has been successfully employed to eliminate the latch-up problem has
been the use of neutron irradiation to lower
minority carrier lifetime in the silicon substrate
which directly affects parasitic bipolar current
gains. As the values in Table IV indicate, neutron
treatment of parts which exhibit latch-up at
3 x 108 and 3 x 109 rads (Si)/sec resulted in latchup-free operation up to the limit of the burst simulationequipment, 10 10 rads (Si)/sec.
TABLE IV. Latch-Up Performance
DOSE REQUIRED FOR LATCH-UP
DEVICE
Voo
CD4006
CD4011
CD4012
CD4053
MM54C200
10V
10V
10V
10V
5V
CONTROL
(NON-NEUTRON TREATED)
NEUTRON TREATED*
>9.4x 109
>9.4x 109
3.1 x 109
>9.4x 109
2.0 X 109
>2.4x 109
3.2x 108
>9.4x 109
>2.2x 10 10
>B.Bx 1011
- Neutron treated parts were subjected to a neutron flux of 1X 10 14 neutrons (fast)/cm 2.
....
UNITS
Rads (Si)/sec
Rads (SI)/sec
Rads (Si)/sec
Rads (Si)/sec
Rads (Si)lsec
By treating wafers with neutron fluxes on the
order of 10 14/cm 2, this enhanced circuit performance is obtained without sacrificing parametric performance. This is illustrated in Figures 10
and 11, which plot supply drain and propagation
delay, respectively, versus neutron flux and
show no significant Clegradation at the 1014/cm2
level.
.
Another very successful method that has been
used to reduce susceptibility to dose rate induced latch-up has been to use low resistivity
substrate material with a high reSistivity epitaxial layer. This structure introduces a low impedance shunt across RN _ in Figure 9, and hence
prevents latch-up. Using this technique, devices
can be supplied which do not 'latch-up even
when exposed to do'se rates of 1012 rads/sec.
'~%~E
Two: DATA·UPSET
•
~/1
I
10 15--,
10'"
This effect results in the loss of stored data in a
circuit after being subjected to burst radiation. It
is typically of most concern in circuits such as
memories and shift registers, where stored data
bits are not directly coupled to circuit inputs.
The problem is again caused by electron hole
pair generation during ionizing burst radiation
exposure. The resulting photo currents can
cause a current flow across. a normally reversebiased PN junction. This current flow can upset
the logic level stored at a node associated with
the PN junction.
10 '6
NEUTRON FLUX
(n/cm 2 )
DEVICE USED: MM54C200DIRH
(256·BIT RAM)
FIGURE 10. Device Quiescent Supply Current vs.
Neutron Flux
Table V shows the effect that neutron treatment
of an MM54C200D/RH 256-bit static RAM has on
the dose rate at which upset occurs. The effect
of neutron fluxes on data upset is not nearly as.
dramatic as it is in the case of latch-up. Although
neutron fluxes in excess of 1015/cm 2 cause significant alterations in semiconductor material
properties and circuit electrical parameters, Figures 10 and 11 indicate that the circuits tested
would still meet data sheet requirements after
irradiation in excess of 2 x 1015/cm2. At this level
the tolerance to data upset exhibits about a
NEUTRON FLUX
(nlem 2)
DEVICE USED: MM54C200D/RH
(256·8IT RAM)
FIGURE 11. Propagation Delay vs. Neutron Flux
8-28
TABLE V. Data Upset Performance
DOSE RATE NEEDED TO INDUCE DATA UPSET
NEUTRON FLUX
(N·FAST/cm 6)
CD4006D
18·BIT SHIFT REGISTER
Voo= 10V
o (control)
4.7 x 108
4.7 x 108
1 x 10 14
1 x 10 15
1 x 1016
MM54C200D (MEMORY ENABLED)
256·BIT RAM, Voo=5V
1.76x 108
2.00 x 108
5.00 x 108
1.17x 109
-
-
threshold improvement over untreated devices.
Almost an entire order of magnitude improv'e·
ments in data upset tolerance can be obtained
with treatment at 1016/cm 2 if the user can toler·
ate the degraded propagation delay and in·
creased supply current drain occurring at this
level.
UNITS
Rads (Si)/sec
Rads (Si)/sec
Rads (Si)/sec
Rads (Si)/sec
current {3 degradation is surface leakage across
the emitter-base junction. This surface leakage,
like MOS characteristics, Is related to the oxide
and interface charges which are induced by high
levels of radiation.
The solution to linear radiation problems, however, is quite different from what we have described above for CMOS devices. Total modification of the fabrication process is needed in order
to achieve rnegarad hardness on linear devices.
We have developed megarad versions of the
LM108A and LM101A. We have extensive research and development currently underway in
this area, for we feel that a broad line of rad hard
linear devices is essential if systems designers
are to achieve total systems hardness.
Rad Hard CMOS Reliability
Radiation hardness, however, is of no value to
the system user if it is accomplished at the sac·
rifice of device reliability. To confirm device reli·
ability, each of 476 units from five lots were sub·
jected to 2.016 hours of burn-in at 125°C. The
total device hours were 804,384, which represents a projected 0.11 %/1000 hours failure rate
at a 60% confidence level. This falls well within
the reliability requirements of even the most
stringent programs.
Ordering Information
, National Semiconductor's Radiation Hardened
CMOS devices are available in three different
levels of hardness, one of which is sure to satisfy the needs of your program. The levels av~il
able are 1 x 105 rads (Si), 1 x106 rads (Si), and
1 x 107 rads (Si), with post-radiation test limits as
defined in Table II-A, II-B, or II-C of this brochure
(as applicable). Each of these can be obtained in
either a bottom-brazed flatpack or in a side·
brazed dual-in-line package, both of which have
solder-sealed lids. In addition, these devices
may be obtained with either Class S or Class B
screening.' National Semiconductor's 883B/
RETS and 883S/RETS microcircuits (which are
described in more detail in' other brochures) are
fully compliant with the 100% screening reqUirements of Method 5004 and MIL·STO-883 for
the applicable screening level and have met the
applicable quality conformance requirements of
Method 5005 of MIL·STO-883.
In addition to this initial sampling, 100% burn-in
screening, as well as operating life testing, has
been performed on many lots that have been
produced for various customers. The results of
this additional testing have continued to demonstrate that rad hard devices are reliable. 10,000·
hour life tests are currently underway to further
establish long-term reliability. The results of this
testing and further testing across our entire rad
hard product line will be added to the existing
data as they become available.
Radiation Hardened Linear Devices
Altho,ugh most bipolar logic devices tend to be
inherently hard when exposed to total·dose
gamma radiation, many bipolar linear devices
will begin to degrade when exposed to relatively
low levels of such radiation. The causes are sim'ilar to those seen inMOS radiation exposurerelated failures. Linear devices are more susceptible to low current {3 degradation than most
bipolar technologies. A major cause of of low
"National Semiconductor has qualified a number of Radiation
Hardened devices in accordance with MIL·M·38510, and
8·29
Ordering is quite simple. Parts may be ordered
using one of the following part number struc·
tures (as applicable).
L
J M38510 H 055 03 SF C
..
Lead Finish
A= Solder DIP
B=Tin plate
C = Gold plate
.
L
CI)4093BM W I R H 8 S
Screening Level
S=Class S
B= Class B
.
Radiation Hardness Level
5 = 1 X 105 rads (Si)
6 = 1 X 106 rads (Si)
7 = 1 X 107 rads (Si)
Package Type
A= 14·pin metal flat
C= 14·pin dual·in·line
D= 14·pin ceramic flat
E= 16·pin dual·in·line
F = 16·pin flat
Scre"ning Level
S=Class 5
B=Class B
Indicates Hardness Type
H = Total dose hardened
E = Dose rate hardened
'---Device on Detail
Specification
Indicates Radiation Hardened
Device
L--_ _ _
' - - - - - Package Type
J = Side·brazed DIP
W = Bottom·brazed flat
E = Leadless chip carrier
Detail Specification
Number
' - - - - - - Radiation Level
M = 2500 rads (Si)
D = 1 X 104 rads (Si)
R· = 1 X 105 rads (51)
H = 1 X 106 rads (Si)
No Mll·M-38510 indicator
exists for 107 rads
' - - - - - - - - Basic Device
' : - - - - - : - - Mll·M·38li10
'------~---JAN
In addition, we are willing to evaluate contractor·
prepared prints for radiation hardened devices.
Mark
ity test program. The intent of this program is to
provide, in advance of actual assembly of product, radiation tolerance data which will allow the
user to determine whether those devices meet
the radiation limits required by his program.
Since the testing need not be done to a specific
limit, this program is able to provid.e specific
device data for those programs whose radiation
tolerance limits are classified. Details on this
program will be provided on request.
Radiation Susceptibility Testing
Natiqnal Semiconductor has also recognized
that there is a need on some programs for data
relative to the actual hardnes.s level of the prod·
uct used, ,even where that product has not been
specifically hardened. To address that need,
Na~ional has developed a radiation susceptibil·
)
8·30
NATIONAL SEMICONDUCTOR'S MEGARAD RADIATION HARDENED PRODUCT LIST
The following device types were released as of December 1,1983 by National Semiconductor as radiation hardened products to the 105 , 106 , 107 rads (Si) levels. These parts will be processed to National's
883SIRETS™ or 883BIRETS™ flow in the bottom-brazed flat ("F"), side-brazed dual-in-line ("0"), or ceramic
("J") and ("W") package configurations. This list supersedes and replaces all previously published lists.
IN DEVELOPMENT
CD4006B MSI
Cb4030B MSI
MM54COO SSI
MM54C02 SSI
MM54C08 SSI
MM54C10 SSI
MM54C20 SSI
MM54C30 SSI
MM54C32 SSI
MM54C221 MSI
RAD HARD CMOS
DEVICE
SERIES
DEVICE
SERIES
DEVICE
SERIES
CD4000MSI
CD4001 SSI
CD4002 SSI
CD4006 MSI
CD4007 SSI
CD4008MSI
CD4009 SSI
CD4010 SSI
CD4011 SSI
CD4012 SSI
CD4013MSI
CD4014 MSI
CD4015 MSI
CD4016 MSI
CD4017 MSI
CD4018 MSI
CD4019 SSI
CD4020 MSI
CD4021 MSI
CD4022 MSI
CD40239S1
CD4024 MSI
CD4025 SSI
CD4027 MSI
CD4028 MSI
CD4029MSI
A
CD4030 SSI
CD4031 MSI
CD4034 MSI
CD4035 MSI
CD4040 MSI
CD4041 SSI
CD4042MSI
CD4043MSI
CD4044 MSI
CD4046 MSI
CD4047 MSI
CD4048 SSI
CD4049 SSI
CD4050 SSI
CD4051 MSI
CD4052 MSI
CD4053 MSI
CD4066 SSI
CD4069 SSI
CD4070 SSI
CD4071 SSI
CD4072 SSI
CD4073 SSI
CD4075 SSI
CD4076 MSI
CD4081 SSI
A
AlB
B
AlB
CD4082 SSI
CD4093 SSI
CD4094 MSI
CD4099 MSI
CD40106 SSI
CD40160 MSI·
CD40161 MSI
CD40162 MSI
CD40163 MSI
CD40174 MSI
CD40192 MSI
CD40193 MSI
CD4510 MSI
CD4512 MSI
CD4514 MSI
CD4516 MSI
CD4518 MSI
CD4520 MSI
CD4528 MSI
CD4538B MSI
CD4584SS1
CD4724 MSI
MM54C04 SSI
MM54C14 SSI
MM54C42 MSI
MM54C85 MSI
MM54C86 SSI
CD4515 MSI
B
AlB
AlB
A
AIUB
AlB
A
A
AlB
AlB
AlB
AlB
AlB
AlB
AlB
AlB
AlB
AlB
AlB
AlB
AlB
AlB
AlB
AlB
AlB
AlB
AlB
A
AlB
AlB
AlB
B
B
AlB
A/UB
AlB
AlB
AlB
AlB
AlB
AIUB
B
B
B
B
B
B
B
B
8
B
8
8
B
8
8
B
B
B
B
8
B
B
B
B
B
B
B
DEVICE
MM54C89 MSI .
MM54C160 MSI
MM54C161 MSI
MM54C162 MSI
MM54C163 MSI
MM54C173 MSI
MM54C174 MSI
MM54C175 MSI
MM54C192 MSI
MM54C193 MSI
MM54C200 LSI
MM54C240 MSI
MM54C244 MSI
MM54C374 MSI
MM54C901 SSI
MM54C902 SSI
MM54C903 SSI
MM54C904 SSI
MM54C905 MSI
MM54C906 SSI
MM54C907 SSI
MM54C914 MSI
MM54C941 MSI
MM70C95 SSI
MM70C96 MSI
MM70C97 SSI
MM70C98 MSI
MM78C29 MSI
MM78C30 MSI
For additional information regarding these or National's upcoming radiation hardened products, please
contact Military/Aerospace Marketing at (408) 721-6670 - Mailstop 16-184.
8·31
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National's A + Program
A + Program: A comprehensive program that utilizes
National's experience gained from participation in the
many Military/Aerospace programs.
A program that not only assures high quality but also increases the reliability of molded integrated circuits.
The A + program is intended for users who cannot perform
incoming inspection of ICs or do not wish to do so, yet need
significantly better than usual incoming quality and higher
reliability levels for their standard integrated circuits.
The concept of reliability, on the other hand, refers to how
well a part that is initially good will withstand its environment. Reliability is measured by the precentage of parts that
fail in a given period 'of time.
Thus the difference between quality and reliability means
the ICs of high quality may, in fact be of low reliability, while
those of low quality may be of high reliability.
Improving the Reliability of Shipped Parts
The most important factor that affects a part's reliability is
its construction: the materials used and the method by
which they are assembled.
Reliability cannot be tested into a part. Still, there are tests
and procedures that an IC vendor can implement which will
subject the IC to stresses in excess of those .that it will endure in actual use, and which will eliminate marginal, shortlife parts.
In any test of reliability the weaker parts
normally fail
first. Further, stress tests will accelerate, or shorten, the
time of failure of the weak parts. Because the stress tests
cause weak parts to fail prior to shipment to the user, the
population of shipped parts will in fact demonstrate a higher
reliability in use.
Users who specify A + processed parts will find that the
program:
• Eliminates incoming electrical inspection.
• Eliminates the need for, and thus the added cost of, independent testing laboratories.
• Reduces the cost of reworking assembled boards.
• Reduces field failures.
• Reduces equipment down time.
• Reduces the need for excess inventories due to yield
loss incurred as a result of processing performed at independent testing laboratories.
will
The A+ Program Saves You Money
It is a widely accepted fact that down-time of equipment is
costly not only in lost hours of machine usage but also costly in the repair and maintenarice cycle. One of the added
advantages of the A + program is the burn-in screen, which
is one of the most effective screening procedures in the
semiconductor industry. Failure rates as a result of the burnin can be decreased many times. The objective of burn-in is
to stress the device much higher than it would be stressed
during normal usage.
Reliability vs. Quality
The words "reliability" and "quality" are often used interchangeably, as though they connoted identical facets of a
product's merit. But reliability and quailty are different, and
IC users must understand the essential difference between
the two concepts in order to evaluate properly the various
vendors' programs for products improvement that are generally available, and National's A + program in particular.
National's A + Program
National has combined the successful B + program with the
Military/ Aerospace processing specifications and provides
the A + program as the best practical approach to maximum quality and reliability on molded devices. The following
flow chart shows how we do it step by step.
SEM
Randomly selected wafers are taken from production regularly and subjected to SEM analysis.
Epoxy B Processing for All Molded Parts
At National, all molded semiconductors, including
ICs, have been built by this process for some time
now. All processing steps, inspections, and QC
monitoring are designed to provide highly reliable
products. (A reliability report is available that gives,
in detail, the background of Epoxy B, the reason for
its selection at National, and reliability data that
proves its success.)
The concept of quality gives us information about the population and faulty IC devices among good devices, and generally relates to the number of faulty devices that, arrive at a
user's plant. But looked at in another way, quality can instead relate to the number of faulty ICs that escape detection at the IC vendor's plant.
It is the function of a vendor'S Quality Control arm to monitor
the degree of success of that vendor in reducing the number of faulty ICs that escape detection. Quality Control does
this by testing the outgoing parts on a sampled basis. The
Acceptable Quality Level (AQL) in turn determines the stringency of the sampling. As the AQL decreases it becomes
more difficult for defective parts to escape detection, thus
the quality of the shipped parts increases.
Six Hour, 1S0'C Bake
This stress places the die bond and all wire bonds
into a combined tensile and shear stress mode, and
helps eliminate marginal bonds and electrical connections.
.
Five Temperature Cycles (70'C to 100'C)
Exercising each device over a 100' temperature
range provides an additional die and package
stress.
8·33
~
o
::E
National's A + Program
(Continued)
~
:c
.!!!
Ci)
a::
.c
Here are the QC sample plans used in our A + test program:
High Temperature (100'C) Functional Electrical
Test
en
:f
A high temperature test with voltages applied
places the die under the most severe stress possible. The test is actually performed at 100'C-15'C
higher than the commercial ambient limit. All devices are thoroughly exercised at the 100'C ambient.
Test
Electrical Functionality
Parametric, DC
Parametric, AC
Electrical Functionality
Parametric, DC
Mecnanical
Critical
Major
Electrical Testing
Every device is tested at 25'C for functional and DC
parameters.
Burn-In Test
Each device is burned-in for 160 hours at a minimum junction temperature of + 125'C or under
equivalent conditions of time and temperature, as
established by a time-temperature regression curve
based on 0.96eV activation energy. All burn-in done
under steady-state conditions unless otherwise
specified.
DC Functional and Parametric Tests
These room-temperature functional and parametric
tests are the normal, final tests through which all
National products pass.
Thermal Shock Monitor
Samples from each package type
are selected at random each
week and submitted to cycles of
liquid to liquid thermal shock -65'C to + 150'C. In
addition, samples are selected every four weeks
and subjected to 2000 temperature cycles of O'C to
+ 25'C.
o
Tighter-than-normal QC Inspection Plans
Most vendors sample inspect outgoing parts to a
0.3% AQL. When you specify the A+ program, we
sample your parts to a 0.035% AQL at room temperature and 0.05% AQL at TA Max. This eight
times tightening (from 0.3 to 0.035% AQL) coupled
with three 100% electrical tests, dramatically reduces the number of "escapes" and allows us to
guarantee the AQLs listed below.
Ship Parts
8·34
Temperature
25'C. }
25'C
2~C
At each temperature}
extreme.
AQL
0.035%
~1%
0.05%
0.01%
0,28%
National's B + Program
B + Program: a comprehensive program that assures high
quality and high reliability of molded integrated circuits.
The B + program improves both the quality and the reliability of National's digital, linear, and CMOS Epoxy B integrated
circuit products. It is intended for the manufacturing user
who cannot perform incoming inspection of ICs, or does not
wish to do so, yet needs significantly-better-than-usual incoming quality and reliability levels for standard ICs.
Quality Improvement
When an IC vendor specifies 100 percent final testing of its
parts then, in theory, every shipped part should be a good
part. However, in any population of mass-produced items
there does exist some small percentage of defective parts.
One of the best ways to reduce the number of such faulty
parts is, simply, to retest the parts prior to shipment. Thus, if
there is a one percent chance that a bad part will escape
detection initially, retesting the parts reduces that probability
to only 0.01 percent. (A comparable tightening of the
group's sampled-test plan ensures the maintenance of the
improved quality leveL)
Integrated circuit users who specify B + processed parts
will find that the program:
• Eliminates incoming electrical inspection.
ac
• Eliminates the need for, and thus the added cost of, independent testing laboratories.
National's B + Program Gets It All Together
We've stated that the B + program improves both the quality and the reliability of National's molded integrated circuits,
and pointed out the difference between those two concepts.
Now, how do we bring them together? The answer is in the
B + program processing, which is a continuum of stress and
inspecdouble testing. With the exception of the final
tion, which is sampled, all steps of the B + process are
performed on 100 percent of the program parts. The following flow chart shows how we do it, step by step.
• Reduces the cost of reworking assembled boards.
• Reduces field failures.
• Reduces equipment down time.
Reliability Saves You Money
ac
With the increases population of integrated circuits in modern electronic systems has come an increased concern with
IC failures in such systems.
And rightly so, for at least two reasons.
First of all, the effect of component reliability on system
reliability can be quite dramatic. For example, suppose that
you, as a system manufacturer, were to choose an IC that is
99 percent reliable. You would find that if your system used
only 70 such ICsl the overall reliability of the system's IC
portion would be only 50 percent. In oiher words: only one
ou! of two of your systems would operate. The result? A
system very costly to produce and probably very difficult to
.
sell.
SEM
Randomly selected wafers are taken from production regularly and subjected to SEM analysis.
Epoxy B Processing for All Molded Parts
At National, all molded semiconductors, including
ICs, have been built by this process for some time
now. All processing steps, inspections, and
monitoring are designed to provide highly reliable
products. (A reliability report is available that gives,
in detail, the background of Epoxy B, the reason for
its selection at National, and reliability data that
proves its success.)
Secondly, whether the system is large or small you cannot
afford to be hounded by the spectre of unnecessary maintenance costs. Not only because labor, repair, and rework
costs have risen-and promise to continue to rise-but also
because field replacement may be prohibitively expensive. If
you ship a system that contains a marginally-performing IC,
an IC that later fails in the field, the cost of replacement may
be-literally-hundreds of times more thaI") the cost of the
failed IC itself.
ac
Six Hour, 150'C Bake
Improving The Reliability of Shipped Parts
This stress places the die bond and all wire bonds
into a combined tensile and shear stress mode, and
helps eliminate marginal bonds and electrical connections.
The most important factor that affects a part's reliability is
its construction: the materials used and the method by
which they are assembled.
Now, it's true that reliability cannot be tested into a part.
Still, there are tests and procedures that an IC vendor can
implement, which will subject the IC to stresses in excess of
those that it will endure in actual use, and which will eliminate most marginal, short-life parts.
High Temperature (100'C) Functional Electrical
Test
A high temperature test such as this with voltages
applied places the die under the most severe stress
possible. The test is actually performed at 100'C-
In any test for reliability the weaker parts will normally fail
first. Further, stress tests will accelerate, or shorten, the
time to failure of the weak parts. Because the stress tests
cause weak parts to fail prior to shipment to the user, the
population of shipped parts will in fact demonstrate a higher
reliability in use.
Five Temperature Cycles (70'C to 100'~)
ExerCising each device over a 100' temperature
range provides an adCjitional die and package
stress.
8-35
National's B + Program
(Continued)
15·C higher than the commercial ambient limit. All
.devices are thoroughly exercised at the 100"C ambient. (Even though Epoxy B processing has virtually eliminated thermal intermittents, we perform this
test to ensure against even the remote possibility of
such a problem. Remember, the emphasis in the
B + program is on the elimination of those marginally-performing devices that would otherWise lower
field reliability of the parts.)
DC Functional !lnd Parametric Tests
These room-temperature functional and parametric
tests are the normal, final tests through which all
National products pass.
Thermal Shock Monitor
Samples from each package type are
selected at random each week and
submitted to 100 cycles of liquid to liquid thermal shock - 65·C to + 150·C.
In addition, samples are selected every
four weeks and subjected to 2000 temperature cycles of O·C to + 25·C.
Tlghter-than-normal QC Inspection Plans
Most vendors sample inspect outgOing parts to a
0.3% AQL. When you specifY the B+ program, we
sample your parts to a 0.035% AQL at room tem- .
perature and 0.05% AQL at TA Max. This eight
times tightening (from 0.3 to 0.035% AQL) coupled
with two 100% electrical tests, dramatically reduces the number of "escapes" and allows us to guarantee the AQLs listed below.
Ship Parts
Here are the QC sampling plans used in our B + test program:
Test
Electrical Functionality
Parametric, DC
Parametric, AC
Electrical Functionality
Parametric, DC
Mechanical
Critical
Major
Temperature
25·C }
25·C
25·C
At each temperature -}
extreme.
AQL
0.035%
0.1%
0.05%
0.01%
0.28%
8-36
~ RELIABILITY
REPORT
~
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::2
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~
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g:
Reliability of
;:;:
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CD
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High Speed CMOS Logic
National
Semiconductor
8·37
-.
o...
.. ~RELIABILITY REPORT
.. r------------------------------------------------------------------------------------------,
o
c..
INTRODUCTION
Ii.
Until recently, the primary reasons for the popularity of CMOS logic circuits have been low power dissipation, tolerance to wider
variations in power supply voltage, and the flexibility of using a broader range of power supplies. Although the acceptance of
CMOS in logic applications has been increasing over the past decade, its growth has been limited by its inherently slower speed
compared with its bipolar counterparts.
.~
The metal gate technology, from which all of the popular CMOS families were built, typically yielded a 90 ns propagation delay
for a buffered gate, and a guaranteed maximum more than double that, whereas, the bipolar equivalents in the popular low
power Schottky family provided typical delay of 8 ns with maximums of 15. Under real-world demands of increasingly faster
computer processing times, many systems simply could not use CMOS and at the same time meet system specifications.
>:5
:is
~
..
CD
as
CJ
c
The arrival of the silicon gate process allowed CMOS to make its largest technological improvement since its inception. By
employing this process, National Semiconductor has been able to increase CMOS speeds to the point where they are now equal
to LS speeds, while still maintaining the earlier power dissipation and supply voltage attractiveness.
~
Series 54HC/74HC High Speed CMOS was announced in the summer of 1981 and will include, when fully developed, nearly 200
logic devices. Many of these devices will be equivalents to those functions popular today in both "LS'~ and "4000" families.
o
en
8-38
~RELIABILITY
REPORT
KEY FEATURES OF THE SERIES 54HC174HC FAMILY
•
•
•
•
LS speeds at CMOS power
Operation over a 2V to 6V power supply range
Output sink and source capability of 4 mA
AC guarantees across the applicable temperature range
HIGH SPEED (HC) CMOS DEVICE FABRICATION
High Speed CMOS wafer fabrication is designed to produce reliable, high performance devices which require minimum handling
restrictions. At National Semiconductor, these objectives are achieved through the use of advanced materials, process innovations, and rigorous controls.
'
This high speed logic family represents an advanced 3.5 micron, single metal, polysilicon gate, oxide-isolated CMOS process.
This process makes use of advanced technologies, including extensive use of ion implantations to tightly control substrate
profiles.
National's HC processing permits the fabrication of MOS transistors with threshold voltages on the order of one-half that of the
more conventional metal gate process. Coupled with thinner gate oxides and self-aligning gates, these lower threshold voltages
allow higher speed circuit operation with lower supply voltages. In addition, the threshold voltage distribution from run to run is
much tighter, so that long term uniformity of device characteristics is assured.
Figure 1 represents the cross section of the HC process employed at National.
HeMOS INVERTER
FIGURE 1. HCMOS Cross Section
8·39
...o
ItRELIABILITY REPORT
-.-------------------~----------~----------------------------------------------------~
c. ACCELERATED LIFE TEST
Accelerated life testing at elevated temperatures is a principal method of simulating long-term operation within a short period of
time. This method is particularly useful because it provides a means of accelerating time-to-failure of temperature sensitive
»
failure mechanisms. As a result, data is gathered for failure rate predictions at any operating field ambient.
/!
:a
==
.!!
The following tests have been conducted at an ambient temperature of 125"C with devices biased at a maximum voltage of 5.5
volts. Complete functional and parametriq testing to data sheet specifications is performed at reported data pOints.
Ci)
a:
CD
HIGH TEMPERATURE BIAS RELIABILITY TEST RESULTS
12S"C OPERATION AT 5_5 VOLTS
.~
c
.~
Ci5
CERDIP, GLASS SEALED HERMETIC DIP, J
Device
'-
MM54HC04J
MM54HC04J
MM54HC139J
MM54HC164J
MM54HCOOJ
MM54HC390J
MM54HC393J
MM54HC04J
MM54HC174J
SS
168 Hours
500 Hours
1000 Hours
51
360
200
192
256
189
127
324
255
1(1)
1 (2)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Stopped
Stopped
0
I
0
0
0
0
Rei lot /I
RBC71305
RBC72012
RBC72177
RBC72178
RBC72196
RBC72223
RBC72224
RBC72346
RBC72348
o·
Actual Failure Rate ='2/1,757,664 device-hours
=0.11% per 1000 hrs. at 125"C.
Notes: (1) Parametric Failure
(2) Gate Oxide Rupture
M DIP EPOXY MOLDED, N
Device
Rei lot /I
SS
168 Hours
500 Hours
1000 Hours
MM54HC04N
MM54HC04N
MM54HC04N
MM54HCOON
MM54HC164N
MM54HC688N
MM54HC393N
MM54HC390N
MM54HC349N
72011
72064
72065
72084
72142
72320
72339
72347
72349
358
384
384
120
256
122
104
64
108
0
0
0
0
0
0
1 (1)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Actual Failure Rate = 1/1,900,000 device-hours
= 0.05% per 1000 hrs. at 125"C.
Notes: (1) Parametric Failure
Quiescent current leakages were measured on molded pieces of two lots subjected to both HTOpL and T&H. Measurements
'
were conducted before and after testing. Results are listed in Table I.
8-40
_RELIABILITY REPORT
~
TABLE I
Average Icc Shifts for Lots
MM54HC04A RBC72064 and RBC72065
(Units In Nanoamps)
n'
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C)
II)
Test
Leg
SS
Average At
Hours
HTOpL
A
48
48
48
48
4
21
0
0
3
25
2
0
48
48
48
48
2
17
16
18
19
12
14
18
48
48
48
0
0
0
0
0
0
48
48
48
0
0
0
0
0
0
B
C
D
A
T&H
B
C
D
A
HTOpL
B
C
A
T&H
B
C
o
Average At
1000 Hours
g;
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TABLE II
VT Shifts After 1000 Hours Burn-In
(Units In Volts)
Pre
Post
Avg.
Avg.
Avg.
Lot
Leg
SS
VTN
VTP
VTN
VTP
72012,J
A
48
48
48
48
.387
.347
.394
.350
.579
.570
.570
.567
.390
.402
.440
.336
.580
.580
.580
.580
48
48
48
48
.470
.530
.400
.471
.580
.580
.527
.519
.472
.499
.467
.518
.570
.571
.570
.575
48
48
48
48
.428
.453
.380
.402
.580
.579
.529
.526
.423
.448
.412
.453
.572
.570
.570
.572
B
C
D
'72064,N
A
B
C
D
72065,N
A
B
C
D
8·41
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Threshold voltage measurements were also read before and after on one lot of cerdip and two lots of molded DIPs. Results are
listed in Table II.
Avg.
( j)
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~RELIABILITY
REPORT
_r-----------~------------------------------------------------------------------------,
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RESULTS
HC high temperature bias failure rates are calculated and derated at 8S'C and 4S'C operating environments for molded dual-inline packages. The Arrhenius relationship is employed to compute the equivalent derated failure rate using an activation energy
of loOeV. An average confidence limit of 60% is reported for these derated figures as seen in Table III.
:s
Table III
High Temperature Operating Ufe Test
TA = 12S'C, Vee = S.SV Static
60% Confidence Level
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Device
Lots
Qty
Dev.
Hours
# Fall
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Various
9
1,900
1,900,000
1
x=
X@
X@
X@
12S'C
8S'C
4S'C
0.1032
0.0039
6.7100xl0- 5
Failure Rate; %/1000 Hours at Temperature.
(This data can be further extrapolated to lower temperatures using a 1.0eV activation energy as illustrated in the failure rate
versus temperature plot of Figure 2.)
0.1
1000/OK
2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9
re-"T"""--r--.---r--r......,r--...--"T"""--r--.---r~......,r--'1
0.01
u.i
=
=
co
co
co
.....
~
e-
0.001
~
~
c
=
=
~
:)
......
....c
0.0001
0.00001 ......._ _"""-_ _-'-_...-l......._ _ _......_ ......
125
o
85
50
25
TEMPERATURE (DC)
FIGURE 2. Failure Rate vs Temperature
8·42
~RELIABILITV
REPORT
TEMPERATURE HUMIDITY BIAS TEST (THB)
The steady state humidity test at 85'C and 85% relative humidity is the most common temperature/humidity test in use today.
This is an accelerated test; that is, it involves stress levels considerably in excess of the field-use levels encountered by a
device. The test is intended to trigger moisture-related failure mechanisms occurring over a period of months or years in the
field. Results are seen below.
Device
Rei Lot #
SS
168 Hours'
500 Hours
1000 Hours
MM54HC04N
MM54HC04N
MM54HC04N
MM54HCOON
MM54HC393N
MM54HC04N
MM54HC390N
RBC72011
RBC72064
RBC72065
RBC72084
RBC72339
RBC73025
RBC72347
340
192
192
96
95
225
. 48
0
0
1 (1)
0
2 (1, 2)
0
0
0
0
0
1(1)
0
0
0
0
0
1 (1)
0
1 (3)
0
0
Cumulative Percent Failures at 1000 Hrs. = 6/1188 = 0.51%
Note: 1. Parametric Failures
2. Continuity Failures
3. Functional Failure
BIASED PRESSURE POT TEST
Another commonly used test is the "pressure cooker" test. This test is usually performed with devices in an operating mode
while being exposed to saturated steam (100% RH). The most common condition is 115'C. At saturation, this temperature
corresponds to a water vapor pressure of 1489mm Hg (28.8 psia). Due to its severity, this test is destructive to virtually all plastic
packages. It creates failure mechanisms which would never be triggered at temperature and humidity extremes found in even
the most severe application. For this reason, the test is limited to a relative few number of hours, and results are interpreted on a
purely qualitative, comparative basis.
Biased Pressure Pot Test Results
TA=115'C, Vee = 5.5V
Device
Rei Lot #
SS
96 Hours
192 Hours
MM54HC04N
MM54HC04N
MM54HCOON
MM54HC04N
MM54HC174N
RBC72064
RBC72065
RBC72084
RBC73025
RBC73024
75
75
75
148
54
0
0
0
0
0
0
0
0
0
1
IMPROVED INPUT PROTECTION
The Single most prevalent cause of "infant mortality" field failures in CMOS microcircuits is generally gate oxide damage. This
can result from any transient voltage condition, such as electrostatic discharge (ESD), inductive spikes, etc. An improved input
protection circuitry which takes full advantage of the HC silicon gate process has been carefully designed to reduce the
susceptibility of these HC circuits to oxide ruptures due to large static voltages.
In conjunction with the input protection, the output parasitic diodes also protect the circuit from large static voltages occurring
between any input, output, or supply pin.
8·43
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ItRELIABILITY REPORT
r-----------------------------------------------------------~----------------------------_,
Figure 3 shows a schematic of the input protection network employed. The network consists of three elements: a polysilicon
resistor, a diode connected to Vee, and a distributed diode resistor connected to ground. This HC process utilizes the polyresistor to more effectively isolate the input diodes than the diode resistor used in metal gate CMOS. This resistor will slow down
incoming transients and also helps to dissipate some of the energy. Connected to the resistor are the two diodes which clamp
the input spike and prevent large voltages from appearing across the transistor. These diodes are larger tha'l those used in
metal gate CMOS, to enable greater current shunting and make them less susceptible to damage. The input network is ringed by
Vee and ground diffusions, which prevent the substrate currents caused by these transients from affecting other circuitry.
The parasitic output diodes that isolate the output transistor drains from the substrate are also important in preventing damage.
They clamp large voltages that appear across the output pins. These diodes are also ringed by Vee and ground diffusions to
again shunt substrate currents, thus preventing damage to other parts of the circuit.
c
Vee
·0
.2
i75
OUTPUT
DIODES
DIODE
POLYSILICON
RESISTOR
INPUT-...JtV'\I\r-....-'\j"".,~
DIFFUSED DIODE
RESISTOR
FIGURE 3. InpufProtection Network
HIGH SPEED LOGIC INPUT PROTECTION ZAP TEST
Input gates of twenty MM54HCOO were subjected to a high voltage (VZAP) burst in order to test input protection circuits. The
inputs under test were subjected to a voltage pulse from a 100 pF source charged to 1000V and 2000V respectively, according
to the test circuit shown in Figure 4.
RI
Tli DEVICE
UNDER TEST
POWER
SUPPLY
R1
=current limiting resistor; R2 = 1.Sk
FIGURE 4. High Speed Logic Input Protection VZAP Test
8-44
~RELIABILITY
REPORT
~
Each input under test was subjected to a sequential VZAP accordingly:
Positive
(1)
(2)
(3)
(4)
(5)
(6)
Negative
input
Voo
Vss
Input
Input
Output
Voo
Input
Input
Vss
Output
Input
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VZAP six times (6X) for each conditicln.
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ZAP results appear in Table iV.
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TABLE IV
VZAP Test Results
o
Parameter
Condition 1
Condition 2
Voltage
Capacitance
Energy Discharged
Result
1000V
100 pF
50",J
0/20·
2000V
100pF
200JJ.J
0/20·
·Input leakages equal to or less than 4 nA.
HIGH SPEED LOGIC HTOPL BUY-OFF .
In addition to ongoing long-term reliability studies and audits, National does an initial 168 hours high temperature bias design
buy-off on every single HC product type before it is released into production. The primary reason behind this program is to
assure the capture of any design-related reliability problem which might pass through all electrical tests. Accelerated conditions
are the same as previously mentioned, i.e., TA=125°C, Vee = 5.5 volts, burn-in time is 168 hours.
Device
SS
Results at 168 Hours
MM74HCOON
MM74HC02N
MM74HC04N
MM74HCU04N
MM74HC08N
MM74HC10J
MM74HCllJ
MM74HC14N
MM74HC73J
MM74HC76J
MM74HC86J
MM74HC107J
MM74HCl12J
MM74HC113J
MM74HC139N
MM74HC147N
MM74HC151N
MM74HG.160J
MM74HC161J
MM74HC164N
MM74HC174N
MM74HC192N
MM74HC193N
MM74HC242N
MM74HC251J
MM74HC253N
MM74HC259N
MM74HC266J
MM74HC390N
MM74HC393N
MM74HC688N
45
50
50
50
-'19
50
50
48
50
50
50
50
40
50
45
50
50
50
50
45
45
50
49
50
50
50
50
50
49
50
50
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8·45
-...
ItRELIABILITY REPORT
..... r------------------------------------------------------------------------------------------,
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HANDLING AND TEST GUIDE
Introduction
All CMOS low threshold devices are susceptible to damage by the electrostatic discharge (ESD) of energy through the devices:
Although all CMOS devices have input protection networks which are effective in a large number of device·handling situations,
they are not effective in 100% of the cases (please refer to specific devices in National's CMOS Databook).
In order to be totally safe, proper handling procedures must be uSed to eliminate damage and subsequent yield loss caused by
static electrical charges. It is the purpose of this application guide to outline proper handling procedures for CMO~ devices.
General Handling Procedures
1. The leads of CMOS devices must be in contact with conductive material to avoid build·up of static charge. Containers used for
transporting or storing CMOS components should be made of such material or lined with antistatic protection. Rails for
handling and shipping MOS devices must be made of electrically conductive material or be made static-free by an appropriate
surface coating. In no case will CMOS devices be inserted into polystyrene foam or other high dielectric materials. Any surface
coating which is not at ground potential must not come in direct contact with device pins.
2. Devices must be packed in conductive containers, rails or envelopes for storing. In addition, devices must be kept at ground
potential and should never come in contact with nonconductive plastics.
3. All electrical equipment must be hard-wired to ground. Soldering iron tips, metal parts of fixtures and tools, and aU handling
systems must be grounded.
\
Cleaning
1. Devices should be cleaned by a solvent which will assure complete removal of foreign matter, flux, residual matter, etc., from
the exterior of the package.
2. A static neutralizing ion blower should be used when manually cleaning devices or subassemblies with brushes.
3. All automatic cleaning should be grounded.
4. All cleaning baskets should be grounded.
Assembly
1. Subassembly modules and printed circuit boards should be manufactured and handled using the same procedures as those
'
described above for individual CMOS devices.
2. CMOS parts should be the last to be inserted into printed circuit boards or systems so as to avoid overhandling.
3. Circuit boards containing CMOS devices which are being transported between work stations and test areas should be
contained in antistatic material or have all board terminals shorted together using a conductive shorting bar. Only handling
trays of conductive material should be used.
4. All automatic insertion equipment, solder machines, metallic parts of conveyor systems, and soldering irons should be
grounded.
'
8-46
~RELIABILI'TY
REPORT
Note: These precautions should be taken until the subassembly is inserted into the complete system in which the proper
voltages are applied. Subassemblies should never be constructed, fixtured, stored, or transported in polystyrene or any other
high dielectric materials.
General Operating Procedures
The National CMOS product line is comprised of many different device types for a variety of applications. The following
operating procedures apply in a general sense to all CMOS devices, but reference to device specification sheets is still
necessary to assure correct operating values.
.
A. Before making any physical connections or applying any external signal sources, be sure that all power supplies are off. Be
sure, also, to observe proper static ground conditions.
B. Power supplies should be turned up slowly to the necessary voltages so as to avoid rapid supply changes.
C. After power supplies have been turned on, apply external input signals.
Note: Failure to perform the power-on procedure in this order can result in damage to CMOS Circuitry.
D. To power down, remove input signals, then turn power supplies off slowly.
E. If CMOS devices are operated at an elevated environmental temperature, allow devices to reach room temperature before
they are powered down.
F. Do not leave' inputs to any CMOS device unused. For NAND gates, the unused inputs should be tied to Voo; unused inputs to
NOR gates should be tied to ground.
Testing
1. Use grounded metallic fixtures where possible. Any surface that is not at ground potential should not come into direct contact
with device pins.
2. Use a static-neutralizing ion air blower when running automatic handlers. Use conductive handling trays when transferring
devices.
3. Do not insert devices or boards with power turned on.
4. Ensure that AC signals do not cause excessive current leakage.
Electrical Failure Modes Caused by Improper Handling
If proper handling techniques are not followed, the generation of static electrical discharges may damage the CMOS devices,
resulting in inoperable or degraded parts. Typical failure modes are:
a. Shorted or open gates
b. Shorted input protection diodes
c. Open metal paths in the device input circuitry
d. Degraded device characteristics
The presence of these failure modes can be detected, easily using a transistor curve tracer.
8·47
~
RELIABILITY REPORT
A New Era in CMOS Logic
.Molded Dual·ln-Line
Package Reliability
National
Semiconductor
8-49
.. ~
r-----------------------------------------------------------------------------------,
..
o
RELIABILITY REPORT
c.
FOREWORD
a:
This report describes reliability data for National's integrated metal gate 54C/74C and CD4000 CMOS logic families in
Epoxy B molding compound. National's approach to achieving the highest reliability is presented through a discussion
of design; device fabrication and the Epoxy B package processing flow. A detailed description of environmental tests in·
cludes Accelerated Life Test, Analysis of Failure Mechanisms, Arrhenius Modeling, High Temperature Bias with Tem·
perature and Humidity Acceleration, Biased Pressure Pot and Electrostatic Sensitivity (ESD). Results for all of these
tests, as well as a compa(ison of National's products to competitive products in these tests is presented in a compre·
hensive manner. Tips on general handling procedures are also provided to help the user maintain the integrity of the
product during the manufacturing cycle.
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TABLE OF CONTENTS
Section
II
III
IV
V
VI
Title
Page
A New Era in CMOS Logic MDIP Reliability
Device Fabrication
Molded Package Processing Flow Chart
Environmental and Life Test Data of CD4XXXC and MM74CXXN
Electrostatic Sensitivity of National's Input Protection Network
Handling Guide for CMOS
8-51
8-53
8·5.6
8·57
8-65
8-67
8-50
~
RELIABILITY REPORT
I. A NEW ERA IN CMOS LOGIC MDIP RELIABILITY
National Semiconductor's task force of key design, process, product, test, and reliability personnel has constantly
investigated every step in the production of CMOS-with one primary objective: improved quality and reliability. Every
step-design, input protection, wafer fabrication passivation, molded assembly, and electrical testing was researched.
Each area was evaluated, fine tuned, and re·evaluated until the final product was put on life test and shown to be the
most reliable CMOS in the industry. For the first time, the data gathered shows that this improved CMOS product com·
pares favorably with bipolar logic reliability. The following is a summary of the improvements, as well as the results.
A. Design, Excluding Input Protection
National is not content with simply providing the best molded package in the industry. The gate structure of our CMOS ICs
has been redesigned to provide insurance against mobile ionic contaminant (principally sodium) penetration into the gate
oxide. This achievement alone provides an order of magnitude improvement to the reliability of our CMOS circuits.
B. Input Protection
The single most prevalent cause of "infant mortality" field failures in CMOS microcircuits is gate oxide damage. This can
result from any transient voltage condition, i.e., electrostatic discharge (ESD), electrical noise, inductive spikes, etc. Just
how easily the devices can be destroyed is a function of the pin·to-pin impedance of the device and the thickness of the in·
sulating oxide layers exposed to the electrostatic charge. The CMOS gate structure is more susceptible than bipolar struc·
tures because it presents very high impedance and very thin (easily ruptured) oxide to the electrostatic charge.
Protection against damage is provided by National's input protection circuitry, which limits the voltage impressed on
the gate oxide. Just how effective this circuitry is depends on several design variables. National has optimized this protective circuitry through closely controlled doping levels, exact junction depths and other process controls, which lead
to extremely consistent zener action of the circuitry. In addition, the layout of the input protection network (Figure 1)
provides symmetrical protection against both positive and negative-going voltage spikes. Thus, the chance for failure
caused by gate oxide rupture is drastically reduced.
This new generation CMOS is protected from voltage transients 3 to 4 times higher than its predecessor. Translated to
field performance, this means an absolute minimum of "infant mortality" failures in the operation of CMOS devices in
their end-use environment.
. - - - - -....- - - - - -....-VDD
INPUT--1_....I\N_-.....-~~.....
--
FIGURE 1. National's Improved Protection Network
C. Improved Die Passivation
As in any molded package system, there is a small probability that moisture will penetrate into the interior of the
package via the molding compound-to-frame interface and, to a lesser degree, via diffusion through the bulk of the
molded package. Since metal gate CMOS devices are subject to an 18V potential and have very low power dissipation, it
is possible for moisture to be absorbed on the surface of the die. In addition, moisture usually contains impurities from
various sources:
a. flux residues from tin dipping operation
b. ions leached from the molding compound
c. phosphorous penta-oxide present in the phospho-silicate glass passivation, which, combined with moisture, will
produce phosphoric acid, an etch ant of aluminum according to the following reactions:
2P 20 5 + 6H 20 -4H 3 P0 4
A + H 3P0 4 -A P0 4 + 312 H2 t
8-51
t:
o
~
RELIABILITY REPORT
.-------------------------------~------------~~---------------------------------------,
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Through its continuing effort to improve reliability performance, National recently developed and introduced an improved CMOS Logic passivation technology (Figure 2). This truly unique and proprietary passivation scheme has led to
a virtually defect-free passivation which consistently meets and exceeds National's passivation defect criteria for
pinholes, cracks and voids-the toughest standard in the industry. In addition, this improved passivation scheme offers
the ability to absorb liquid contaminants onto its surface, thus preventing or inhibiting the final pel')etration into the
interior of the active integrated circuit area .
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TL/F/6017·2
FIGURE 2_ National's CMOS Logic Passivation Scheme
The major advantages of this improved'passivation scheme are as follows:
1.
2.
3.
4.
5.
6.
Exceedingly hi,gh purity passivation composition
Defect densities less than 0.01 per 1000 mils 2
Wafer fabrication process which easily covers irregular contours and other common defects
Inhibits moisture penetration to the surface of the die
Highly resistant to heat
Its thick resilient layer provides superior mechanical integrity and prevents passivation pinholes, cracks, and voids
commonly associated with wafer fabrication, assembly and molding mechanical stresses.
D. Assembly
In its never-ending quest for improved reliability, National has also focused its attention to the molded assembly technology and made major improvements in this area. A close in'spection of our improved m_olded package (Figure 3) will
reveal:
a. A die attach whose temperatures are well below those associated with gold-silicon eutectic conditions.
b. Frame has an increased surface area which improves frame-to-epoxy adhesion, thus minimizing the chance of
moisture penetration.
.
c. Frames are perforated to allow epoxy to pass through the frame fingers during the molding operation, thus forming a
"locking" mechanism. This will prevent frame finger movement during the trim and form operation ..
d. Gold wire bonding temperatures havelbeen drastically reduced by using thermosonic bonding ratherthan commonly
used thermocompression bonding.
All of the aforementioned improvements have been combined and the result is superior reliability performance for
National molded CMOS Logic products.
IMPROVED PASSIVATION
FIGURE 3. Improved Molded Package Construction
8-52
~
RELIABILITY REPORT
II. DEVICE FABRICATION
CMOS wafer fabrication is designed to produce reliable, high·performance devices which require minimum handling
restrictions. At National Semiconductor, these objectives are achieved through the use of advanced materials, process
innovations, and rigorous process controls.
The substrate material used in the CMOS process is [1·0·0] orientation N-type silicon rather than the commonly selected
[1.1-1] orientation type. Coupled with controlled processing, this substrate permits the fabrication of MOS transistors
with threshold voltages up to half as low as that produced on [1·1-1] orientation silicon. Lower threshold voltages allow
higher·speed circuit operation with lower supply voltages. In addition, the threshold voltage distribution from run to run
_ is much tighter so that long term uniformity of device characteristics is assured.
The stability of CMOS characteristics depends directly on the level of contamination in the gate oxide. National's pro·
prietary oxidation procedure and cleaning methods are capable of producing ultra·clean oxides. In order to ensure low
levels of oxide contamination in production, all production oxidation and evaporation systems are monitored on a
regular basis using the capacitance voltage method. A MOS capacitor is fabricated and drifted under + 15V bias at
300'C for two minutes. The shift in the C·V plot is a measure of the ionic contam·ination in the oxide under evaluation.
This method is also used for investigations of process changes and innovations. These measurements assure rapid de.
tection and correction of production process difficulties before contaminated material can leave the wafer processing
area.
An additional check on stability is performed on completed wafers. Fields of ± 2 x 106V/cm are applied to C-V test dots
(patterned onto the device die) while the wafer is heated to 300'C for two minutes, then cooled to room temperature. The
C-V shift is measured before and after heating for both bias conditions. The maximum permissible shift in threshold
voltage is OAV with typical shifts running less than 0.15V.
Moreover, National's CMOS devices have a double-input diode protection network designed to prevent catastrophic
failures caused by positive or negative-going voltage transients. This effective input protection network, coupled with
excellent oxide integrity, reduces the handling restrictions required on CMOS devices. A detailecl guide to the handling
requirements of CMOS parts is given in the last section of this report.
Figur(Js 4 through 16 offer a pictorial representation of National's CMOS device fabrication. (Please note that the drawings are not to scale.)
SiD,
TLlFI6017-4
FIGURE 4. Initial OXidation, Thermally Grown Silicon Dioxide Layer on Silicon Substrate Surface
SiD,
•
TL/F16011·5
FIGURE 5. P-Mask and Formation of P-Well Tub in which N-Channel Devices wit.1 be Located
SiD,
TLlFlb01Hi
FIGURE 6. P-Well OXidation, Thermally Grown Silicon Dioxide Layer-over P-Well Area
8-53
~
RELIABILITY REPORT
..... r----------------------------------------------------------------------------------------,
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FIGURE 7. P + Mask and Formation of Low Resistance P + Type Pockets in P-Well and N·Substrate
p+
:E
TlIF/6017·8
FIGURE 8. P + Oxidation, Thermally Grown Silicon Dioxide Layer over P + type Pockets
TUF/6017·9
FIGURE 9. N + Mask and Formation of L-ow Resistance N + Type Pockets in P·Well and N·Substrate
TlIF/6017·10
FIGURE 10. N + Oxidation, Thermally Grown Silicon Dioxide Layer over N + Type Pockets
TlIFI6017·11
FIGURE 11. Composite Mask and Openings tb Nand P·Channel Devices
8-54
~
RELIABILITY REPORT
TLlFI6017·12
FIGURE 12. Gate Oxidation, Thermally Grown Silicon Dioxide Layer over Nand P·Channel Devices
FIGURE 13. Contact Mask and Openings to Nand P·Channel Devices
TLlF/601?14 '
FIGURE 14. Metallization, Metal Mask, Resulting in Gate Metal and Metal Interconnects
TLlFI6017·15
FIGURE 15. Passivation Va pox, Deposited Silicon Dioxide over Entire Die Surface
8-55
~
RELIABILITY REPORT
voo
-C *
P-~~~:~~~ISTOR
INPUT (+V.O)
.
OUTPUT (O.+V)VOO
N-CHANNEL
MOS TRANSISTOR
.
TliF/6017·17
FIGURE 16_ Basic CMOS Inverter Circuit
111_ MOLDED PACKAGE PROCESSiNG FLOW CHART
1. Sorted Wafers are Received ,
All dice on wafers have been 100% electronically tested. Electrical rejects are marked with an ink spot.
2_ 100% Diamond Saw-Through, Plunge-Up Die Attach
Inked dice are removed.
3_ Optical Die Sort
100% optical microscope inspection at 100 x to remove potentially unreliable dice.
4. Quality Control Surveillance-First Check
.
Verification that the optical die sort was performed according to written specificatio~s.
5. Ole Attach
Attachment of die to lead frame with a polymer.
6_ Quality Control Surveillance,
Verification that the die attach operation Was performed according to written specifications.
J
GoldWIre
I
7_ Lead Bond
Thermosonic ball-bonding of gold wire to die and lead frame ..
8-56
~
RELIABILITY REPORT
8. Quality Control Surveillance
Several times eac~ shift, samples are checked from each bonding machine and from each operator's work.
9. Quality Assurance Lead Bond Pull Test
Samples by lot from each operator are checked a minimum of twice per shift. All bonds are pulled to destruction.
The force required to break the bond, and the location of the break, are recorded for process·control purposes.
10. Pre·Mold Optical Sort
100% optica,l microscope inspection at 30 x for assembly defects. Devices are inspected for wafer processing
anomalies, assembly work damage, completeness, and accuracy of assembly.
11. Quality Control Surveillance
Samples of each optical sorter's work are inspected to criteria which meet or exceed the applicable requirements of
MIL-STD-883B, Method 2010.
Molding
Compound
I
12. Mold and Cure
Thermosetting plastic is transfer molded around the completed assembly. The plastic is then cured to insure
mechanical and chemical stability.
13. Trim and Form Leads
Frame supports are removed and leads formed to desired configuration.
14. Quality Control Surveillance
•
Visual and mechanical quality are continuously monitored.
15. Mark Package
Devices are marked with National's part number, a date code (signifying mold week), and the National logo.
16. Clip Rails
Lead-frame rails are removed, leaving finished devices ready for test.
17. Electrical Test
I
100% electrical test on all data sheet parameters.
18. Quality Assurance Acceptance
Each lot of finished devices is sample inspected and tested by quality assurance inspectors for compliance with
specifications.
19. Pack and Ship
Each shipment is inspected by quality assurance to be sure that the right devices are going in the right quantity to
the right customer.
IV. ENVIRONMENTAL AND LIFE TEST DATA OF CD4XXXC AND MM74CXXN
Accelerated Life Test
Testing at elevated temperatures is the principal method used to simulate long-term operation within a short period of
time. This method is particularly useful because it provides a means of accelerating time-to·failure of temperature sensitive failure mechanisms. As a result, data are gathered for failure rate predictions at any operating field ambient.
I
Like all system hardware-mechanical, electrical, and electronic-the reliability of CMOS logic conforms to the well
known "bathtub" curve, a plot failure rate versus time. As shown in Figure 17, the four concepts associated with this
curve are infant mortality rate, useful life failure rate, useful life, and wearout failure rate.
EARLY
USEFUL WEAROUT
... LIFE +1- LIFE -I-TIMETIME
6w
t:
=
w
=
':3
ii:
I
-INFANT
MORTALITY
USEFUL
•
)
LIFE
~~
FAILURE
~
RATE
10
11
WEAWjjOUT
FAILURE
RATE
12
TUF/6017-1e
FIGURE 17. Reliability Life Curve
8·57
-... ~ ·RELIABILITY REPORT
o
Infant Mortality: These are the devices that fail in the early life of the product, the period to tol1. Since the failure rate is
Co decreasing rapidly during this period,and the period is short (dependent upon temperature), the infant mortality is exQ)
a: pressed as the percentage of devices that fail from to to t1. The infant mortality portion of the curve is shaded because
>::
:c
.!2
Qi
a:
-"
Q)
1"0
-
iii
Q)
:i!:
infant mortality is strongly influenced by numerous handling variables such as system-induced voltage transients,
temperature, environment, mechanical stresses, etc., and therefore varies widely.
Useful Life Failure Rate: The percentage of devices that fail per-unit-time duiing the flat portion of the curve (t1 tot2), extending from the end of infant mortality to the onset of wearout. Usually expressed as percent per 1000 hours
(sometimes per million hours or FITS), this statistic can also be stated as mean time between failure (MTBF), which is
simply the reciprocal of the failure rate.
Useful Life: This is the period extending from the end of infant mortality to the onset of wearout, t1 to t2, at which point
the failure rate begins to increase again. The useful life is usually expressed in hours. Although there is insufficient data
to define a true useful life in most cases, the minimum life of a device usually suffices to assure adequate design
margins. The useful life may be as short as several months but usually extends for decades if adequate design margins
are applied. Temperature plays a major role in triggering the onset of wearout mechanisms; but other stresses, such as
pressure, mechanical stress, thermal cycling and electrical loads, also play important roles.
Failure Mechanisms
As may be judged from the previous discussion" the failure mechanisms which occur in microcircuits are a function of
application and device processing.
As shown in Table I, the main system stress factors contriputing to infant mortality are electrical transients and noise,
mechanical maltreatment and excessive temperatures. Most infant failures resulting from these causes occur in three
stress-producing phases:
1. device burn-in,
2. card assembly and handling,
3. initial system test and operation.
Although device burn-in can serve as an indicator of infant mortality, the carefully controlled burn-in tests seldom
resemble the broad range of conditions (especially electrical noise) encountered in actual use. Field reliability data is
therefore taken as the best source of infant mortality. This data is readily available and accurate.
TABLE I. Some Common Infant Mortality Failure Mechanisms
Defect
Stress Factors
Thin or defective oxide (masking and oxidation)
• System electrical noise
• System power interruptions
• Inductive loading
Open wire bonds
Assembly defects
• Ultrasonic exposure during
card assembly
• Excessive temperature
Failure Mechanism
Oxide ruptures
Lifted die bonds
Assembly defects
• Excessive temperature
Fused Die Metallization Shorts
Inadequate spacing between adjacent stripes
• System electrical noise
• System power interruptions
Metallization opens
Inadequate stripe width and/or thickness
(mask;'ng and evaporation)
• Inductive loading
Corrosion of wire bonds and/or
die metallization
Seal leaks (defective encapsulation)
• Handling damage
• Excessive solder heat
during card assembly
8-58
~
RELIABILITY REPORT
Table II lists the activation energies for some common long·term failure mechanisms. All are essentially wearout
mechanisms that have been discussed at length in the literature. The dramatic acceleration effect of temperature on
these failure mechanisms is illustrated in Figure 18, which shows failure rate versus junction temperature for various
activation energies. For instance, a mechanism with 0.99 eV activation energy is accelerated 800 times when junction
temperature is increased from 50'C to 125·C. This means that a 1,000 hour life test at 125'C is equivalent to 800,000
hours operation at 50·C.lf an increase in failure rate (onset of wearout) was not observed during the test, the 1,000 hour
test would substantiate a minimum useful life greater than 90 years.
TABLE II. Common Wearout Failure Mechanisms
Failure Mechanism
Activation Energy
Electromigration in aluminum
conductors (glassed, large
grain)
Intermetallic growth in goldl
aluminum bond systems
Wire arid wire bond failures
during thermal cycling
'Slow trapping-charge
injection
Charge accumulationmobile ions
1.2 eV
;:; 1,000,000
...~
!.,
100,000
10,000
~
w
100
w
10
~
a fatigue mechanism
""
:3
if
1.0-1.3 eV
.ECHAN'SM
0.7.V
~TD ~~sUNEAR
1,000
i!:.
0.99-1.04 eV
wi~r.~ 71(.
II IIII
W
J.IIII
DEVICES
r- ~
V~
-""
~
, i-"" ~..v
7rTFORBIPOLAR
LOGIC
1
30 50 70 90 120
160
200
JUNCTION TEMPERATURE ('C)
1.0-1.35 eV
TUF/6017·19
FIGURE 1B. Failure Rate as a Function
of Junction Temperature
Thermal Resistance-Its Impact on Microcircuit Reliability
Nearly all microcircuit failure mechanisms are accelerated by temperature, but the impact temperature has on ac·
celerating a system failure is a direct function of the failure's thermal activation energy. Thus, the measure'ot the effi·
ciency of the packaging·die system in removing heat from the active region is important in estimating how reliably that
circuit will perform. The unit of measure to be used in estimating the active junction temperature of a microcircuit is its
thermal resistance (0 JA)'
An exact measurement of the thermal resistance of microprocessors is not possible to obtain for most chips. Therefore,
special test packages are commonly monitored to calculate typical package resistance values for reliability models.
Acknowledging that the actual circuit thermal resistance is a function of many factors, it is nevertheless possible to
presume certain general facts about thermal resistance and then apply them to our microcircuits. These facts are sum,
marized in Figure 19 for 14·lead packages.
In using the data in the tables, it is necessary to apply the equation:
TJ";POXOJA+TA
where T J is the circuit temperature at the active junction region and Po is the average power consumed during circuit
operation in the active junction region. OJA is the thermal resistance from the active junction region to the environ·
ment of the device's use system. At National Semiconductor, thermal resistance testing is done in still air, with either
socket mount or a printed circuit board mounting. A generalized curve showing the effects of increasing air flow
across the package is shown in Figure 20.
111111
140
1.0
I III
14·LEAD (N) PLASTIC
120 ~ ... ~ALLOY 42 FRAME)
........
~
0.9
....
. \\ \..
ffi
100
80
q;:
'" 60
14-LEAo (N) PLASTIC ..
40
(CoprE~ L~~ I~~~ME)
20
E
i2
!5
".
lk
10k
DIE SIZE (MILS)
0.8
:E
0.7
IIIIII
0
1
.......
0.5
5Dk
0
-
200 400 600 800 1000
AIR FLOW (LINEAR FEET IMINUTE)
TL./F/60t7·21
TLlF/6017·20
FIGURE 19. Typical Thermal
Impedance (OJ'u as a Function of
Die Size
......... ....
FIGURE 20. Graph Showing Typical Proportionate
Decrease in Package Thermal Resistance as a Function
of Chamber or System Air Flow
8·59
~
RELIABILITY REPORT
The Arrhenius Model
The time and temperature dependence' of virtually all long-term semiconductor failure mechanisms is a well established fact. The occurrence of this failure dependency can be represented by the Arrhenius Model. This model includes
the effect of temperature and activation energy of the failure mechanism, permitting it to be used to characterize failure
modes and predict reliability at normal operating temperatures based on tests performed at above-normal device junc.tion temperatures_
Originally developed in the 1880's to describe chemical reaction rates, the Arrhenius Model was adapted to accelerated
life testing after researchers theorized that chemical processes were the primary cause of degradation of electronic
parts_ And, since temperature was comf'l1only used in electronics accelerated testing, the Arrhenius Model was applied
and found to fit the data. The model was subsequently a validated design tool and a useful adjunct to the state-of-the-art
of accelerated life testing technology_
As applied to accelerated life testing of semiconductors, the Arrhenius Model assumes the following formula for.defining the lifetime or MTBF at a given temperature stress level when the MTBF at a second temperature stress level is
known_ (See Equation 1.)
Equation 1:
Ea
t1 =t2exPK
[1fl- 1'21]
where: t1 = MTBF at junction temperature T1
t 2 = MTBF at junction temperature T2
T = Junction temperature in oK
Ea = Thermal activation energy in electron volts (eV)
K = Boltzman's constant (8.617 X 10- 5 eV/oK)
Acceleration Factor F
. The acceleration factor F is the factor by which the failure rate can be acclerated by increased temperature. This factor
can be readily derived by expressing the failure rate as the reciprocal of MTBF, then reducing the Arrhenius equation to
the following form:
Equation 2:
hl
= F =exp~
A2
K
[.!. -.!.]
T2
T1
where: f
= Acceleration factor
>.. 1 = Failure rate at junction temperature T1
>"2 = Failure rate at junction temperature T2
Junction Temperature
In calculating the field reliability of a semiconductor device, it is first necessary to calculate the junction temperature
both for the reliability test and for actual field operating conditions. In general, the junction temperature will depend on
the ambient temperature, cooling, package type, operating cycle times, supply voltage and current. In these terms, the
junction temperature, TJ, is given as:
Equation 3:
TJ = 'iA + (Icc x Vec)(At) (()JA)
where: TJ = Junction temperature
TA = Ambient temperature
lec = Supply current
Vee = Supply voltage
At = Air flow factor (0.75)
() JA = Package thermal resistance
Activation Energy
Given the temperature and failure rate for a specific reliability test, the remaining unknown is the activation energy, Ea.
To derive a simple formula for E, we take the natural log of the failure rate:
Equation 4:
Ea [1
In1-ln2=K
fl-1'21 ]
As the slope of the straight line resulting from Equation 4, the activation energy serves as a convenient means of characterizing the failure mechanisms. If the activation energy is known, or can be estimated, the acceleration factor can be
determined, allowing field failure rate and useful life to be calculated from the accelerated life tests_
8-60
~
RELIABILITY REPORT
Application of Life Test Data
The life test data presented can be used to fully establish the reliability characteristics of National's CMOS logic prod·
ucts. Using the Arrhenius formulas, the acceleration factors can be calculated for any given operating junction temper·
ature and used to determine failure versus time (the characteristic "bathtub" curve) or long·term failure rate.
Cumulative Total: 6/3,961
Total Device Hours: 3,961,000
Average Failure Rate at 125'C: 0.15%/1000 hours
From Equation 2, Page 8·60:
45
125
318
398
o...
Ea/KT
0.7 eVI(8.617 x 10 -5 eVI'K)(398'K) = 20.41075
Substituting:
Ea
20.41075
Ea
exp KT = 5.13477
F=170
Therefore:
a. The acceleration factor between the temperature 45'C and 125'C with an activation energy of 0.7 eV is 170 times.
b. The projected failure rate at 45'C is thus: 0.15%11000 hrs. + 170 =0.0009%11000 hrs.
B. Calculating E. from Experimental or Published Data.
Example: Calculate Ea used in Steady State Life, Method 1005.3, MIL·STD·883S, 4 Nov. 1980.
Let t1 = 125'C, t2 = 85'C.
From Equation 1, Page 8·60:
t1 =t2
exp~
[';
-~]
Rearranging:
In t1·- In t2]
Ea = K [ 11T1 _ 11T2
t1 = 2 x 104 hrs. at 125'C
t2 = 5 X 105 hrs. at 85'C
Therefore:
Ea =8.617 X 10- 5 eV/'K
g
::;
'<
-
- 1'1
0.7 eV/(8.617 x 10 -5 eV/'K)(318'K) = 25.54552
KT = 25.54552 -
I»
CD
::a
Calculating:
KO
CD
"C
1]
Given: Ea = 0.7 eV
K = Soltzman's constant (8.614 x 10- 5 )
T = Absolute temperature in 'K (C' + 273)
CO
2?.
C)
::a
m.
;'
A. Acceleration Factor at any Field Temperature
Example: Calculate failure rate at desired field temperature (T t ) of 45'C.
},,1
Ea [1
~ =F=exP"K 1'2
i:
!.
In 2 x 104 hrs. -In 5 x 105 hrs.
(0.0025125 'K) - (0.0027933 'K)
In2x104 =9.90349 .
In 5 x 105 = 13.12236
Substituting:
Ea = 8.617 X 10- 5 eV/'K [9.90349 -13.12236]
-2.808x 10- 4 'K
= 0.99 eV (or commonly used 1.0 eV)
8·61
t
~
RELIABILITY REPORT
r-------------------------------------~--~----------------------~--------~~
Temperature and Humidity Bias Tests
CD The THB (temperature·humidity·bias) test is now the standard test for evaluating package and IC integrity. It uses above·
normal stress levels to trigger within hours moisture·related failure mechanisms that would require years in the field .
•_~ National Semiconductor runs the THB test at 85·C, 85% RH, and with maximum Voo applied. When used with a valid
life·acceleration model, this "85/85" test provides the following information:
&.
a:
:s
.!
CD
IX:
CD
-;
CJ
'ii
a;
::E
1. Valid life acceleration factors .
2. Lifetime in operation or in storage.
3. Worst·case field failure rates.
Temperature and Humidity Acceleration Factors
Various models have been proposed for the THB tests, but the Peck and Zierdt model appears to be the most useful and
valid. It provides independent temperature and humidity predictors and appears to be substantiated by work done by
other investigators. This model has therefore been used to derive life acceleration factors fortemperature and humidity.
These are plotted in Figures 21 and 22 with selected factors listed in Figures 23 and 24. In using these curves, all other
variables must be kept constant, particularly bias voltage and power dissipation, since chip temperature and voltage
gradient both have a first order effect on electrolysis rate. To allow these curves to be used with various levels of internal
heating, Figure 25 provides relative humidity correction for changes in chip temperature.
TABLE III. High Temperature Bias Reliability Test 'Results Continuous Operation at 1SV, 12SoC, 1000 Hours
Device
Rei Lot Number
Date Code
E3046
21025
E3051
E3052
12102/91179
91178
91144
12101/91143
12099/91180
12100/91181
71314
11486
71352
71347
71346
11473
72034
72047
92271
92272
72165
72163
72161
72160
72333
72334
72335
72277
72278
72279
72372
72373
72374
72375
72376
8101
8101
8104
8105
8107
8115
8121
8121
. 8124
8124
8137
8143
8145
8145
8145
8146
8201
8201
8202
8206
8220
8220
8220
8220
8225
8225
8225
8228
8228
8228
8250
8250
8250.
825Q
8250
MM4612B
MM4613B
MM4613B
MM4611B
MM74C901
MM74C373
MM4625
MM4612
MM4627
MM4629
MM4601B
MM74C902
MM74C924
MM4681B
MM4611B
MM74C04
. MM74C04
MM4613B
MM74C02
MM74C02
MM46B1B
MM4611B
MM4601B
MM4601B
MM4611B
MM4611B
MM4611B
M~4681B
M 74C04
MM5613B
MM74C04N
MM5601BN
MM5611BN
MM5673BN
MM5681BN
Notal: Parametric failure
Nota 2: Gate oxide rupture
8·62
Sample
Size
100
100
100
100
90
100
83
100
100
100
90
94
126
231
231
75
240
292
BO
80
90
90
90
90
90
90
90
120
150
99
90
90
90
90
90
1000 Hrs.
0
1 (Note 1)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3 (Note 1)
1 (Note 2)
0
0
0
0
0
0
0
0
0
0
1 (Note 1)
0
0
0
0
0
0
~
RELIABILITY REPORT
TABLE IV. Temperature-Humidity Bias Test Results
Continuous Operation at 15V, 85·C, 85% ReI. Hum., 1000 Hours
Device
Rei Lot Number
Date Code
MM4612B
MM4613B
MM4613B
MM4611B
MM74C901
MM74C373
MM4625
MM4612
MM4627
MM4629
MM4601B
MM74C902
MM4611B
MM4681B
MM74C04
MM74C04
MM4613B
MM74C02
MM74C02
MM4681B
MM4611B
MM4601B
MM4601B
MM5681BN
MM74C04N
MM5611BN
MM5611BN
MM5611BN
MM74C04N
MM5601BN
MM5611BN
MM5673BN
E3046
21025
E3051
E3052
12102/91179
91178
91144
12101/91143
12099/91180
12100/91181
71314
11486
71346
71347
11473
72034
72047
92271
92272
72165
72163
72161
72160'
72277
72278
72333
72334
72335
72372
72373
72374
72375
8101
8101
8104
8105
8107
8115
8121
8121
8124
8124
8137
8143
8145
8145
8146
8201
8201
8202
8206
8220
8220
8220
8220
8228
8228
8225
8225
8225
8250
8250
8250
8250
Sample
Size
100
75
87
100
100
100
100
100
100
100
90
94
231
231
75
300
340
80
80
90
90
90
90
120
150
90
90
90
120
120
120
120
1000 Hrs.
0
2
0
0
0
0
0
0
1
a
2
a
1
a
a
1
2
1
a
a
1
a
a
0
0
0
2
a
0
0
0
0
Cumulative Total: 13/3,863
Cumulative Percent Failures at 1000 Hrs: 0.336%
100
100,000
i
~
;I'. 10,000
Ii!
e 1000
~
...
~
.....
:g
L
....
I:l
~
-
f--SLOPE =0.54OV I--
/
10
!.
:IE
"
100
'"
15-
15-
u..
:IE
1
90
"
80
~
70 60 50 40 3D
TEMPERATURE I'C)
20
10
1
10
,~
"
15
20 30 40 50
100
PERCENT RELATIVE HUMIDITY
TUF/6017·23
TL.IF/6017·22
FIGURE 21. Corrosion Failure Rate vs Junction
Temperature (Constant Relative Humidity)
FIGURE 22. Corrosion Failure Rate vs Relative
Humidity (Constant Temperature)
8·63
RELIABILITY REPORT
..... •;-----------------------------------------------------------------------------------,
8.
~
>-
:a
==
.!
~
.!
as
CJ
'ii
Temperature (OC)
Field
Laboratory
Laboratory
Acceleration
30
55
30
55
85
85
5x
5x
24x
;;:
'"
1.0
~
>'"
0-"-
is'''
-'"
:E ...
0.1
""=='"
w~
TlIFI6017·24
3:§
FIGURE 23. Humidity Acceleration Factors
",,,,
~~
"';;:
0.01
"-
1)
Relative Humidity (%)
:IE
Field
Laboratory
Laboratory
Acceleration
65
50
20
15
12
85
85
85
85
85
3x
lOx
700x
2,800 x
6,000)(
'"
...
'" 0.001 L..LL.£.J....a.......t::....J<::...J.......L.....L....L...J
o 10 20 30 40 50 60 70 80 90 100
TEMPERATURE (OC)
TLIFI6017·26
FIGURE 2S. Lines of Constant Percent Relative
Humidity for Varying Temperature and Absolute
Humidity
FIGURE 24. Temperature Acceleration Factors
Worst·Case Acceleration Factors
Worst-case field conditions are encountered in the Gulf Coast states, where the typical mean daytime temperature is
30·C and the relative humidity is 65%. Using Figures 21 through 24, we can calculate the temperature and humidity acceleration factors. For a non-operating circuit, we can read directly from Figures 22 and 23. The temperature acceleration factor is FT = 25, and the humidity acceleration factor is F H = 4. The life acceleration factor is therefore:
F = 4 x 25 = 100. Hence, one hour of 85/85 testing is equivalent to 100 hours under worst-case field conditions (nonoperating). Since the chip temperature increases when the device is operating,'the relative humidity is reduced and the
life acceleration factor is increased, resulting in impro)led reliability when the device is operating.
Biased Pressure Pot Test
Another commonly used test is the "pressure cooker" test. This test is usually performed with devices in an operating
mode while being exposed to saturated steam (100% RH). The most common condition is 115°C. At satyration, this
temperature corresponds to a water vapor pressure of 1489 mm Hg (28.8 psia). Due to its severity, this test is destructive
to virtually all plastic packages. It creates failure mechanisms which would never be triggered at temperature and
humidity extremes found in even the most severe application. For this reason, the test is limited to a relatively few
number of hours, and results are interpreted on a purely qualitative, comparative basis.
TABLE V. Bias Pressure Pot Test Results
Continuous Operation at 15V, TA = 11SoC, Rei. Hum.';' 100%,192 Hours
Device
Rei Lot Number
Date Code
MM4601B
MM4611B
MM4681B
MM4681B
MM74C04N
MM4601B
MM4611B
MM4681B
RBC72160
RBC72163
RBC7216S
RBC72277
RBC72372
RBC72373
RBC72374
RBC72376
8220
8220
8220
8228
8;150
8250
8250
8250
8-64
Sample
Size
·59
60
58
120
180
100
100
100
192 Hrs.
1
1
0
2
4
1
1
0
~
RELIABILITY REPORT
V. ELECTROSTATIC SENSITIVITY OF NATIONAL'S INPUT PROTECTION NETWORK
Figure 26 shows a schematic of National's improved protection network employed. The network consists of two
elements; three diodes connected to Vss and two distributed diode resistors connected to Vcc(*). This Vee resistor
network will slow down incoming voltage transients and will also help dissipate some of the·energy. Both sets of diodes
will clamp an input spike and prevent large voltages (>35V) from appearing across the transistor. These diodes are
larger than those used previously in metal gate CMOS to enable greater'current shunting and make them less suscep·
tible to damage. The input network is ringed by Vee and ground diffusions which prevent substrate currents caused by
.
transients from affecting other circuitry.
The inherent output diodes (~) that isolate the output transistor drains from the substrate are also important in prevent·
ing damage. They clamp large voltages that appear across the output pins. These diodes are also ringed by Vee and
ground diffusions to again shunt substrate currents and prevent damage to other parts of the circuit.
Vee
INPUT ~,"""",W'v-....-
....----4
OUTPUT
TLlFI6017·27
\
FIGURE 26. National's Improved Protection Network
:,'.
Five different CMOS logic devices were selected for high voltage (VZAP) testing; their logic functions and truth tables are
shown in Figures 27 through 31.
TOP VIEW
TOP VIEW
TLIFI6017-2S
TRUTH TABLE
TRUTH TABLE
Inputs
A
B
0
0
1
0
1
0
1
1
TLIFI6017·29
Inputs
B
A
0
0
1
0
0
1
1
1
Output
C
1
0
0
0
Output
C
1
1
1
0
FIGURE 28. Logic Diagram and Truth Table for
CD4011BM/CD4011BC, Quad 2·lnput NAND Buffered B
Series Gate
FIGURE 27. Logic Diagram and Truth Table for
CD4001 BM/CD4001 BC, Quad 2·lnput NOR Buffered B
Series Gate
8·65
...o
a.
/l.
~
RELIABILITY REPORT
~ r---------------------------------------------~------~--------------------------------_,
ii2
02
CLOCK 2
RESET 2
CLOCK 1 RESET 1
DATA 1
>-
:is
==
.!
"G)
a:
.!
ftS
"a;
Ci
Vss
TOP VIEW
TUF/6017-30
:!E
SET 1
VSS
TOP VIEW
TRUTH TABLE
Inputs
A
B
0
0
1
0
1
0
'1
1
TUFI6017-31
TRUTH TABLE
Inputs
Output
C
0
0
0
1
Clt
0
0
1
X
X
X
No change
X
X
X
X
t =Level change
X = Don't care case
FIGURE 29. logic Diagram and Truth Table lor
CD4081 BM/CD4081 BC, Quad 2·lnput and Buffered B
Series Gate
R
0
0
0
1
0
1
S
0
0
0
0
1
1
Outputs
Q
Q
0
1
1
0
a
Q
0
1
1
1
,0
1
"
FIGURE 30. logic Diagram and Truth Table lor
CD4013BM/CD4013BC, Dual 0 Fllp·Flop
TL/FI6011-32
Terminal No.8
=GND
Terminal No. 16 = VDD
FIGURE 31. logic Diagram lor CD4017BM/CD4017BC, Decode Counter/Divider with 10 Decoded Outputs
8·66
~
RELIABILITY REPORT
r---~~===-==~==~~~~~-=~~---------------------.~
High voltage testing (VZAP ) was conducted. Detail specifications applicable to aforementioned devices. This VZAP test
is considered to represent an equivalent circuit describing the human body model and is shown in Figure 32.
!.
e.
Each input under test was subjected to a sequential VZAP according to Table VI. In addition, each input was subjected to
high voltage testing six times (6 x) for each condition. Ten (10) commercial samples of each device type were subjected
to VZAP '
Ci)
!2.
(1)
Input is same pin number in every mode. Output is associated output to input under test in applicable mode.
~
Testing was conducted by electrical testing for all DC and functional parameters at 25°C per published data specification limits, before and after VZAP testing. Results appear in Table VII.
Di'
g;
National's improved input protection network makes it possible for its devices to withstand high voltage discharges :::;:
without affecting their electrical performance.
'<
Rl
+
HIGH
VOLTAGE
POWER
SUPPLY
'~~,
.
R,2"
~
Rl:;; 25 MO; represents protective charging resistance.
TO DEVICE
UNDER TEST
R2:;; 1.5 kO; represents equivalent human body resistance.
C1 :;; 100 pF; represents equivalent human body capacitance.
51:;; Hg relay; means of transferring VZAP to device under test.
VZAP= lOOOV, 2000V charge on Cl.
-
FIGURE 32. Input Protection VZAP Test Conditions
TABLE VI. Sequential VZAP Test Modes
Mode
1
2
3
4
5
6
Positive Terminal
Negative Terminal
Input
Voo
Input
Input
Voo
Vss
Input
Input
Output
Vss
Output
Input
TABLE VII_ VZAP Test Results
Total Energy Discharge
CD4001BC
CD4011BC
CD4081BC
CD4013BC
CD4017BC
1000V
2000V
50!,J
0/10
0/10
0/10
0/10
0/10
200!,J
0/10
0/10
0/10
0/10
0/10
VI. HANDLING GUIDE FOR CMOS
Introduction
All CMOS low-threshold devices are susceptible to damage by the electrostatic discharge (ESD) of energy through the
devices. Ths is because the gate oxide thickness of ~uch devices is in the range of 1,000 A to, 1, 100A, which limits the
maximum voltage that can be applied (to the input of the device) to 80V with a reasonable safety factor. (For a fuller
description of ESD and its possible latent effects on microcircuits, see National Semiconductor's Reliability Physics
Brief, RPB·02, July 1978 and Reliability Physics Brief, RPB·07, January 1980.) Although all CMOS devices have input protection networks which are effective in a large number of device·handling situations, they are not effective in 100% of
the cases (please refer to specific devices in National's 1984 CMOS Databook).
In order to be totally safe, proper handling procedures must be used to eliminate damage and subsequent yield loss
caused by static electrical charges. It is the purpose of this application guide to outline proper handling procedures for
CMOS devices.
8·67
if
'&...
-
~
RELIABILITY REPORT
CMOS Latch-up Free Operation
Latch-up Is a common problem encountered by first time users of CMOS logic components_ However, if some fundamental precautions are laken, latch-up free system operation can be easily achieved.
Typical CMOS structures have"many adjacent closely spaced junction diffusions, which under normal operation, will
be reversed-biased. Figure 33 shows the cross section of two CMOS FETs showing the parasitic transistors connected as a PNPN SCR (silicon controlled rectifier). If one or more of the PN junctions becomes forward-biased, the
SCR will be triggered and the result appears to be a short between Voo and Vss. This "latch-up" will continue until
power Is removed or the device is burned up.
Voo
RI
Vss
TLiF/6017.35
TUF/6017-34
FIGURE 33_ A Cross Section 01 Two CMOS FETs Showing the Parasitic Transistors and Equivaient Circuit
The most common way that these parasitics come into play is to cause an input or output junction to become forwardbiased. The voltage required to activate the parasitic SCR decreases as operating temperature increases and is between 0.4V and 0.5V at 125 D C. This undesired forward-biasing can be caused by noise on Voo and Vss lines, or noise on
the input/output Signals, or from a combination of power supply and signal noise.
Latch-up free operation can be achieved by maintaining all input and output levels within a range of - 0.3V minimum
and Voo + + 0.3V maximum. The following precautions will ensure this.
1. Voo and Vss should be applied before any input or output signal is applied.
2. Voo and Vss noise must be minimized through adequate capacitive decoupling, power supply regulation, and good
board layout with respect to power distribution. Ground (Vss) differences must be controlled to keep input and output
signals from violating the Vss - 0.3V minimum.
3. Signal overshoot(and undershoot) should be controlled to stay within the stated min-max range (transients of IV for
50 ns can cause latch-up with some device types).
General Handling Procedures
1. The leads of CMOS devices must be in contact with conductive material to avoid build-up of static charge. Containers used for transporting or storing CMOS components should be made of such material or lined with antistatic
protection. Rails for handling and shipping MOS devices must be made of electrically conductive material or be
made static-free by an appropriate surface coating. In no case will CMOS devices be inserted into polystyrene foam
or other high dielectric materials. Any surface coating which is not at ground potential must not come in direct contact with device pins.
2. Devices must be packed in conductive containers, rails or envelopes for storing. In addition, devices must be kept at
ground potential and should never come in contact with nonconductive plastics.
3. All electrical equipment must be hard-wired to ground. Soldering iron tips, metal parts of fixtures and tools, and all
handling systems must be grounded.
Cleaning
1. Devices should be cleaned by a solvent which will assure complete removal of foreign maller, flux, residual maller,
etc., from the exterior of the package.
2. A static neutralizing ion blower should be used when manually cleaning devices or subassemblies with brushes.
3. All automatic cleaning should be grounded.
4. All cleaning baskets should be grounded.
8-68
~
RELIABILITY REPORT
Assembly
1. Subassembly modules and printed circuit boards should be manufactured and handled using the same procedures
as those described above for individual CMOS devices.
2. CMOS parts should be the last to be inserted into printed circuit boards or systems so as to avoid overhandling.
3. Circuit boards containing CMOS devices which are being transported between work stations and test areas should
be contained in antistatic material or have all board terminals shorted together using a conductive shorting bar. Only
handling trays of conductive material should be used.
4. All automatic insertion equipment, solder machines, metallic parts of conveyor systems, and soldering irons should
be grounded.
Note: These precautions should be taken until the subassembly is inserted into the complete system in which the
proper voltages are applied. Subassemblies should never be constructed, fixtured, stored, or transported in polystyrene
or any other highly dielectric materials.
General Operating Procedures
The National CMOS product line is comprised of many different device types for a variety of applications. The following
operating procedures apply in a general sense to all CMOS devices, but reference to device specification sheets is still
necessary to assure correct operating values.
A. Before making any physical connections or applying any external Signal sources, be sure that all power supplies are
off. Be sure, also, to observe proper static ground conditions.
B. Power supplies should be turned up slowly to the necessary voltages so as to avoid rapid supply changes.
C. After power supplies have been turned on, apply external input signals.
Note: Failure to perform the power-on procedure in this order can result in damage to CMOS circuitry.
D. To power down, remove input Signals, then turn power supplies off slowly.
E. If CMOS devices are operated at an elevated environmental temperature, allow devices to reach room temperature
before they are powered down.
F. Do not leave inputs to any CMOS device unused. For NAND gates, the unused inputs should be tied to Voo; unused
inputs or NOR gates should be tied to ground.
Testing
1. Use grounded metallic fixtures where possible. Any surface that is not at gr.ound potential should not come into
direct contact with device pins.
2. Use a static-neutralizing ion air blower when running automatic handlers. Use conductive handling trays when
transferring devices.
3. Do not insert devices or boards with power turned on.
4. Ensure that AC signals do not cause excessive current leakage.
Electrical Failure Modes Caused by Improper Handling
If proper handling tachniques are not followed, the generation of static electrical discharges may damage the CMOS
devices, resulting in inoperable or degraded parts. Typical failure modes are:
a.
b.
c.
d.
shorted or open gates
shorted input proteytion diodes
open metal paths in the device input circuitry
degraded device characteristics
The presence of these failure modes can be detected easily
usi~g
a transistor curve tracer.
REFERENCES
D. S. Peck and C. H. Zierdt, Jr.; "Temperature-Humidity Acceleration of Metal·Electrolysis Failure in Semiconductor
Devices"; 11th Annual Reliability Physics Symposium, Las Vegas, Nevada, April 1973.
R. W. Lawson; "The Accelerated Testing of Plastic Encapsulated Semiconductor Components"; 12th Annual Reliability
Physics Symposium, Las Vegas, Nevada, April 1974.
H. Koelmans; "Metallization Corrosion in Silicon Devices by MOisture·lnduced Electrolysis"; 12th Annual Reliability
Physics Symposium, Las Vegas, Nevada, April 1974.
8·69
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