1984_National_Logic_Databook_Volume_2 1984 National Logic Databook Volume 2

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LOGIC
DATABOOK
VOLUME II

Introduction to Bipolar Logic
Advanced· Low Power Schottky
Advanced Schottky

II

Low Power Schottky

•

Schottky

•

TTL

ell

Low Power

•

Appendices/
Physical Dimensions

3

III
Ell

r:-

U.

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4

Int roduction

Introduction Bipolaire

This volume of the 1984 Logic Databook contains complete
information on National Semiconductor's extensive bipolar
logic families. Included in this publication are National's
newer 5V bipolar families, AS and ALS, designed for use
together in systems where both high speed and low power
are important considerations. The AS family provides the
fastest saturated logic circuits on the market, whereas
ALS, at only one milliwatt per gate, minimizes power
dissipation. Together, the two technologies provide the optimum powerlspeed solution. Additionally, the ALS/AS circuits are guaranteed over a ± 10% power supply range for
both AC and DC.

Cette edition 1984 du Databook Logique contient une information exhaustive sur les families logiques bipolaires
de National Semiconductor. Dans cet ouvrage, figurent
les plus nlcentes families bipolaires 5 V de National,la AS
et la ALS, concues toutes les deux pour etre utiJisees dans
les systemes ou se posent des problemes de vitesse et de
consommation.
La famille AS regroupe les circuits les plus rapides du
marc he en logique saturee, tandis que la familieALS, avec
une consommation de seulement 1 mW par porte, permet
de minimiser la consommation. A elles deux, ces deux
technologies fournissent Ie meilleur rapport consommation/vitesse. De plus, les circuits ALS/AS sontgarantis 11
la tension d'alimentation 11 plus ou moins 10% que ce soit
en alternatif ou en continuo

Einleitung
Dieser Band des Logik-Dalenbuchs 1984 enthalt die
vollstandigen Informationen uber das umfangreiche
Spektrum der' bipolaren L.:ogikfamilien von National
Semiconductor. Enthalten sind in diesem Buch auch die
neueren 5-V-Bipolar-Familien von National, die AS- und
ALS-Typen, die beide fur die Verwendung in Systemen
konzipiert sind, bei denen tiohe Arbeitsgeschwindigkeit
und g~ringe Stromaufnahme eine wichtige Rolle spielen.
Die AS-Familie ist die schnellste Logik-Typenreiche in
gesattigter Schaltungstechnik auf dem Markt, wahrend
die ALS-Familie mit nur 1 mW pro Gattor eine sehr geringe
Verlustleistung aufweist. Insgesamt bieten die beiden
Schaltungstechniken eine optimale L6sung in bezug auf
das Geschwindigkeits-Leistungs-Verhaltnis. Daruber
hinaus sind die Gleich- und WechselspannungsParameter uber einen Betriebsspannungs-Bereich von
± 10% garantiert.

Introduzione
II volume LOGIC DATABOOK 1984 contiene informazioni
complete sulle famiglie logiche bipolari della National
Semiconductor. Nella pubblicazione vengono descritte Ie
nuovissime famiglie AS ed ALS. Progettate per essere
utilizzate in sistemi, ove velocita e ridotti assorbimenti
siano caratteristiche di primaria importanza. La famiglia
AS e constituita da circuiti logici satura ti, i piu veloci
presenti oggi sui mercato; Ie ALS, peraltro, con una dissipazione di un solo milliwatt per gate, e realizzata per
minimizzare gli assorbimenti. Le due famiglie, insieme,
rappresentano la soluzione ottimale per velocita/assorbimento. Oltre a cio, i dispositivi AS/ALS hanno i parametri
sia AC che DC, caraterizzati da una variazione della tensione di alimentazione ± 10%.

5

,

Table of Contents
Section 1-lntroduction to Bipolar LogiC
Guideto Bipolar Logic FamiliesSeiection _'_ .................... _............. _. . . . . . .
ICDeviceTesting ..........•.........•.................. '.........................
Glossary of Terms "... "........................ ;. .. . .. . . .. . . .. . . . .• . . .. . . . .. . • . . . . .
Application Notes
AN-363 Designing with TIL. ....•...........•............................ :.......
AN-372 Designer's Encyciopediaof Bipolar One-Shots .... : . . .. . . . . . . . . . . . . . . . . . . . . . .
Functional Index/Selection Guide ....... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TestWaveforms ...............................'..................................

1-3
1-9
1-17
1-22
1-25
1-42
1-67

Section 2-Advanced Low Power Schottky
Buffersl Drivers
DM54/74ALS28 Quad 2-lnput NOR Buffers ....•.....................•.......•.•..•...
DM54/74ALS33 Quad 2-lnput NOR Buf(ers with Open-Collector Outputs .................. .
DM54/74ALS37 Quad 2-lnput NAND Buffers ....................•.....................
DM54/74ALS38 Quad 2-lnput NAND Buffers with Open-Collector Outputs ................ .
DM54/74ALS40 Dual4-lnput NAND Buffers ..••...........•.•.........................
DM54/74ALS2400ctal TRI-STATE Inverting Buffers/Line Drivers/Line Receivers ......•.....
DM54/74ALS241 Octal TRI-STATE Buffers/Line Drivers/Line Receivers ...•.•..............
DM54/74ALS244 Octal TRI-STATE Buffers/Line Drivers/Line Receivers ...•................
DM54/74ALS465 Octal TRI-STATE Buffers/Bus Drivers ......•..................•.•.....
DM54/74ALS466 Octal TRI-STATE Inverting Buffers/Bus Drivers ......................... .
DM54/74ALS467 Octal TRI-STATE Buffers/Bus Drivers ................................ .
DM54/74ALS468 Octal TRI-STATE Inverting Buffers/Bus Drivers: ........ ,' ..•.......•.....
DM54/74ALS804 Hex 2-lnput NAND Line Driver ..•. "....•...........•......•...........
DM54/74ALS805 Hex 2-lnput NOR Line Driver ..............•........ " ................ .
DM54/74ALS808 Hex 2-lnput AND Line Driver ..•.•.....•...........•..................
DM64/74ALS832 Hex 2-lnputOR Line Drivers ..............•....................•.....
DM54/74ALS1000 Quad 2-1 nput NAN D Buffer (ALS37) ...•...........•....•.............
DM54/74ALS1002 Quad 2-lnput NOR Buffer (ALS28) .•...........•.....................
DM54/74ALS1003 Quad 2-lnput NA'ND Buffer with Open-Collector Outputs .......•........
DM54/74ALS1004 Hex Inverting Buffer ..•..•............•...........................
DM54/74ALS1005 Hex Inverting Buffer with Open-Collector Outputs ....•.. ~ ........... ' .. .
DM54/74ALS1008Quad 2-lnput AND Buffers ••.......•...•...........................
DM54/74ALS1010Triple3-lnput NAND Buffers ....................................... .
DM54/74ALS1011Triple3-lnputAND Buffers ........................................ .
DM54/74ALS1020 Dual4·lnput NAND Buffers (ALS40) .....••.....................•...••
DM54/74ALS1 032 Quad 2·lnput OR Buffers .......................................... .
DM54/74ALS1034 Hex Non·lnverting Buffers ..................•............•.........
DM54/74ALS1035 Hex Non·lnvertlng Buffers with Open·ColiectorOutputs ... ; ............ .
DM54/74ALS1240 Octal TRI·STATE-Invertlng Bus Drivers/Receivers ...................... .
DM54/74ALS1241 Octal TRI·STATE Bus Drivers/Receivers .•.............•.....•........
DM54/74ALS1244 Octal TRI·STATE Bus Drivers/Receivers ..•.............•.............

2-46
2-52
2-54,
2-56
2-58
2-141
2-141
2-147
2-184
2-184
2-184
2-184
2-241
2-243
2-245
2-253
2-271
2-273
2-275
2-277
2-279
2-281
2-283
2-285
2-287
2-289
2-291
2-293
2-295
2-295
2-303

Comparators
DM54/74ALS518 Octal8-Bit Identity Comparator with Open-Collector Outputs. . . . . . . . . . . . . .
DM54/74ALS519 OctalS-Bit Identity Comparator with Open-Collector Outputs. . . • . . . . . . . . . .
DM54/74ALS520 Octal8-Git Identity Comparator • . . . . • . . . • • . . • • . . • . . . . . . . . . . . . . . . . . . . .
DM54/74ALS521 OctalS-Bit Identity Comparator ....••......••••-.........•.••......•. '.
DM54/74ALS522 Octal8-Bit Identity Comparator with Open-Collector Outputs. . • . . . . . . . • . . .

6

2-188
2-188
2-188
2·188
2-188

Table of Contents (Continued)
DM54/74ALS677
DM54/74ALS678
DM54/74ALS679
DM54/74ALS680
DM54/74ALS689

16-Bit to 4-Bit Address Comparator with Enable .........................
16-Bitto 4-Bit Address Comparator with Latch .........................
12-Bit to 4-Bit Address Comparator with Enable ..................... . . .
12-Bit to 4-Bit Address Comparator with Latch .........................
8-Bit Comparator with Open-Collector Outputs . . . . . . . . . . . . • . . . . . . . . . . . .

2-228
2-228
2-233
2-233
2-238

DM54/74ALS160 Synchronous 4-Bit Decade Counter with Asynchronous Clear . . . . . . . . . . . . .
DM54/74ALS161 Synchronous 4-Bit Binary Counter with Asynchronous Clear. . . . . . . . . . . . . .
DM54/7 4ALS162 Synchronous 4-BitDecade Counter with Synchronous Clear ........... . . .
DM54/74ALS163 Synchronous 4-Bit Binary Counter with Synchronous Clear . . . . . . . . . . . . . . .
DM54/74ALS168 Synchronous 4·Bit Up/Down Decade Counter ..........................
DM54/74ALS169 Synchronous 4-Bit Up/Down Binary Counter ...........................
DM54/74ALS190 Synchronous 4-Bit Up/Down Decade Counter ..........................
DM54/74ALS191 Synchronous 4-Bit Up/Down Binary Counter ...........................
DM54/74ALS192 Synchronous 4-Bit Up/Down Decade Counter with
Clear and Dual Clo,ck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74ALS193 Synchronous 4-Bit Up/Down Binary Counter with
Clear and Dual Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-103
2-103
2-103
2-103
2-118
2-118
2-126
2-126

Counters

2-134
2-134

Decoders/ Encoders
OM54/74ALS131 3 to 8 Line Decoder with Address Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74ALS137 3 to 8 Line Decoder/Demultiplexerwith Address Latches ................
DM54/74ALS138 3 t08 Line Decoder/Demultiplexer. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-7.7
2-87
2-91

Error Correction/Detection Circuits
DM54/74ALS632 TRI;STATE 32-Bit Error Detection and Correction Circuit ..............
DM54/74ALS633 32-Bit Error Detection and Correction Circuit
with Open-Collector Outputs ................................................
DM54/74ALS634 TRI-STATE32-Bit Error Detection and Correction Circuit ..............
DM54/74ALS635 32-Bit Error Detection and Correction Circuit with
Open-Collector Outputs .......... :, ........................................

request data sheet

request data sheet
request data sheet

request data sheet

Flip-Flops
DM54/74ALS74 Dual Positive-Edge-Triggered D Flip-Flops with Preset and Clear. . . . . . . . . . . .
DM54/74ALS109 Dual Positive-Edge-Triggered J-K Flip-Flops with Preset and Clear. . . . . . . . . .
DM54/74ALS112 Dual Negative-Edge-Triggered J-K Flip-Flops with Preset and Clear. . . . . . . . .
DM54/74ALS113 Du~1 Negative-Edge-Triggered J-K Flip-Flops with Preset .................
DM54/74ALS114 Dual Negative-Edge-Triggered J-K Flip-Flops with Preset,
Common Clear, arid Common Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74ALS174 Hex D Flip-Flops with Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74ALS175 Quad D Flip-Flops with Clear and Complementary Outputs ...............
DM54/74ALS273 Octal Positive-Edge-Triggered D Flip-Flops with
Clear and Buffer Outputs .......................................................
DM54/74ALS374 Octal TRI-STATE Positi~e-Edge-Triggered D Flip-Flops ...................
DM54/74ALS534 Oc~al TRI-STATE Inverti~g Positive-Edge-Triggered D Flip-Flops. . . . . . . . . . . .
DM54/74ALS564 Octal TRI-STATE Inverting Positive-Edge-Triggered D Flip-Flops. . . . . . . . . . . .
DM54/74ALS574 Octal TRI-STATE Positive-Edge-Triggered D Flip-Flops ...................
DM54/74ALS576 Oc~al TRI-STATE Inverting Positive-Edge-Triggered D Flip-Flops. . . . . . . . . . . .
DM54/74ALS874 Dual TRI-STATE 4-Bit Positive-Edged-Triggered D Flip-Flops. . . . . . . . . . . . . . .
DM54/74ALS876 Dual4-Bit Inverting Positive-Edge-Triggered D Flip-Flops ............ ',' . . .
7

2-60
2-65
2-68
2-71
2-74
2-123
2-123
2-163
2-180
2-195
2-202
2-209
2-212
2-259
2-263

Table of Contents (Continued)
Gatesllnverters
DM54/74ALSOOQuad 2-lnput NAND Gates .....................................•.....
DM54/74ALS01 Quad 2-lnput NAND Gates with Open-Collector Outputs ..•....•...•.......
DM54/74ALS02 Quad 2-lnput NOR Gates ....................' .............. : ........ ..
DM54/74ALS03 Quad 2-lnput NAND Gates with Open-Collector Outputs ...•.........•.....
DM54/74ALS04 Hex Inverters ......................•..............•..•.............
DM54/74ALS05 Hex Inverters with Open-Collector Outputs ...........•.............•..•
DM54/74ALS08 Quad 2-lnput AND Gates .............•........•...............•.•...
DM54/74ALS09 Quad 2-lnput AND Gates with Open-Collector Outputs ................•...
DM54/74ALS10Triple 3-lnput NAND Gates .....................................•.....
DM54/74ALS11Triple 3-lnput AND Gates .......................................... ..
DM54/74ALS12 Triple 3-lnput NAND Gates with Open-Collector Outputs .................. .
DM54/74ALS13 Dual 4-'lnput Schmitt Trigger NANDGates. ; ............................ :
DM54/74ALS14 Hex Schmitt Trigger Inverters ...•......•..•.........•.................
DM54/74ALS15Triple3-lnput ANO Gates with Open-Collector Outputs ........•...........
DM54/74ALS20 Dual4-lnput NAND Gates ........................................... .
DM54/74ALS21 Dual4-lnput AND Gates .................•......•........•........•..
DM54/74ALS22 Dual.4-lnput NAND Gates with Open-Collector Outputs ...........•••...••
DM54/74ALS27Triple3-lnput NOR Gates ........................•...•...............
DM54/74ALS30 8-lnput NAND Gate ............................................... .
DM54/74ALS32 Quad 2-lnput OR Gates ...................................•..........
DM54/74ALS86 Quad 2-lnput Exclusive-OR ......................................•....
DM54/74ALS132 Quad 2-lnput Schmitt Trigger NAND Gates ............................ .
DM54/74ALS133 13-lnput ~ANDGate ..............•.............. , ............... .
DM54/74ALS136 Quad Exclusive-OR Gates with Open-Collector Outputs ................. .
DM54/74ALS810 Quad 2-lnput Exclusive NOR Gates .................... " .............. .
DM54/74ALS811 Quad 2-lnput Exclusive NOR Gates with Open-Colh~ctorOutputs .......... .

2-9'
2-11
2-13
2-15
2-17
2-19
2-21
2-23
2-25
2-27
2-29
2-31
2-33
2-36
2-38
2-40
2-42
2-44
2-48'
2-50
2-63
2-80
2-83
2-85
2-247
2-250

Latches
DM54/74ALS373 Octal TRI-STATE Transparent D Latches . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . .
DM54/74ALS533 Octal TRI-STATE Inverting Transparent D Latches ......•.........•....•.
DM54/74ALS563 Octal TRI-STATE Inverting Transparent D Latches .......................
DM54/74ALS573 Octal TRI-STATE-Transparent D Latches. . . . . . . • . . . . . . . . . . . . . . . . . . . . . . .
DM54/74ALS580 Octal TRI-STATE Inverting Transparent D Latches .............•.........
DM54/74ALS873 Dual TRI-STATE4-BitTransparent D Latches .......•.... ~ . . . . . . . . . . . . . . .
DM54/74ALS880 Dual4-Bitlnverting Transparent D Latches. . . . . . • . . . . . . . . . . . . . . . . . . . . . .

2-177
2-192
2-199
2-206
2-216
. 2-255
2-267

Multiplexers/Demultiplexers
DM54/74ALS151 1 of8 Line DataSelector/Multiplexer . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74ALS 153 Dual 1 of 4 Li ne Data Selectors/M u Iti plexers ...........................
DM54/74ALS157 Quad 2 to 1 Line Data Selectors/Multiplexers. . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74ALS158 Quad 2to 1 Line Inverting Data Selectors/Multiplexers. . . . . . . . . . . . . . . . . . .
DM54/74ALS251 TRI-STATE 1 of 8 Line Data Selector/Multiplexer
with Complementary Outputs ................... ; . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74ALS253 Dual TRI-STATE 1 of 4 Data Selectors/Multiplexers ......................
DM54/74ALS257 Quad TRI-STATE2 to 1 Line Data Selectors/Multiplexers. . . . . . . . . . . . . . . . . .
DM54/74ALS258 Quad TRI-STATE2 to 1 Line Inverting DataSelectors/Multiplexers . . . . . . . . . .
DM54/74ALS352 Dual 1 of 4 Line Inverting Data Selectors/Multiplexers ................... :
DM54/74A~S353 Dual TRI-STATE 1 of 4 Line Data Selectors/Multiplexers ..................

8

2-94
2-97
2-100
2-100
2-152
2-156
2-159
2-159
2-171
2-174

Table of Contents (Continued)
Registers
DM54/74ALS165 8·Bit Paralielln/Serial Out Shift Register with
Complementary Outputs .......................................................
DM54/74ALS166 8·Bit Parallel or Serial In/Serial Out Shift Register
with Complementary Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74ALS299 8·Bit Universal Shift/Storage Register with
TRI·STATEOutputs ............................................................

2·110
2·114
2·166

Trallsceivers
DM54/74ALS242 Quad TRI·STATE Inverting Bus Transceivers. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2·144
DM54/74ALS243 Quad TRI·STATE Bus Transceivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2·144
DM54/74ALS245 Octal TRI·STATE Bus Transceivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2·150
DM54/74ALS620 Octal TRI·STATE Inverting Bus Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2·219
DM54/74ALS621 Octal Bus Transceivers with Open·Coliector Outputs ....................
2·222
DM54/74ALS622 Octal Inverting Bus Transceivers with Open·Collector Outputs. . . . . . . . . . . . .
2·222
DM54/74ALS623 Octal TRI·STATE Bus Transceivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2·225
DM54/74ALS638 Octal Inverting Bus Transceivers with TRI·STATE
and Open·Coliector Outputs ......... ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. request data sheet
DM54/74ALS639 Octal Bus Transceivers with TRI·STATE and
Open·Coliector Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. request data sheet
DM54/74ALS640 Octal TRI·STATE Inverting Bus Transceivers. . . . . . . . . . . . . . . . . . . . . . .. request~atasheet
DM54/74ALS641 Octal Bus Transceivers with Open·Collector Outputs . . . . . . . . . . . . . . .. request dalasheet
DM54/74ALS642 Octal Inverting Bus Transceivers with
Open·Coliector Outputs ......................................... '.......... , request data sheet
DM54/74ALS643 Octal TRI·STATETrue and Inverting Bus Transceivers ................ request data sheet
DM54/74ALS644 Octal True a,nd Inverting Bus Transceivers
with Open·Coliector Outputs ................... , , . , ..... , . . . . . . . . . . . . . . . . . .. request dala sheet
DM54/74ALS645 Octal TRI·STATE Bus Transceivers ... ,., .... " ..... , ............. requestdalasheet
DM54/74ALS1242 Quad TRI·STATE Inverting Bus Transceivers ...... , ............ , , . . . . . .
2·299
DM54/74ALS1243 Quad TRI·STATE Bus Transceivers, ................. , .... , . , . , , .. , . . .
2·29~
DM54/74ALS1245 TRI·STATE Bus Transceivers .. , .... , .................... , .. , .. , .. , . .
2·306
DM54/74ALS1620 Octal TRI·STATE Inverting Bus Transceivers ... , ......... ',' . , ...... , . . .
2·309
DM54/74ALS1621 Octal Bus Transceivers with Open·Collector Outputs .... ,..............
2·312
DM54/74ALS1622 Octal Inverting Bus Transceivers with Open·ColiectorOutputs ......... , . .
2·312
DM54/74ALS1623 Octal TRI·STATE Bus Transceivers .. , .. , .. , .. , ... , . , . . . . . . . . . . . . . . . . .
2·315
DM54/74ALS1638 Octal Inverting Bus Transceivers with Open·Collector and
, TRI·STATEOutputs , ... , .......... , .. " ....... ".,.............................
2·318
DM54/74ALS1639 Octal Bus Transceivers with Open·Collector
and TRI·STATE Outputs .. , ........ : .... , .......................... , ...... ,.,....
2·318
DM54/74ALS1640 Octal TRI·STATE Inverting Bus Transceivers ...... , .. , . . . . . . . . . . . . . . . . .
2·322
DM54/74ALS1641 Octal Bus Transceivers with Open·Collector Outputs ....... , .. , ... ,....
2·326
DM54/74ALS1642 Octal Inverting Bus Transceivers with Open·Coliector Outputs. , ... , .... , ,
2·326
DM54/7 4ALS1643 Octal TRI·STATE True and Inverting Bus Transpeivers ...... ,............
2·322
DM54/74ALS1644 Octal True and Inverting Bus Transceivers with Open·ColiectorOutputs . . . .
2·326
DM54/74ALS1645 Octal TRI·STATE Bus Transceivers .. , . , , ..... , .. , .. , . . . . . . . . . . . . . . . . .
2·322

9

Table of ~ontents (Continued)
Section 3-Advanced Schottky
Arithmetic Functions
DM54/74AS181 B Arithmetic Logic Unit/Function Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS182 Look-Ahead Carry Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS280 9-Bit Parity Generator/Checker ..... : . . . .. . .. . . . . . . .. . . . . . • .. .. . . .•. . .
DM54/74AS282 Look Ahead Carry Generator with Selectable Carry Inputs .............•...
DM54/74AS286 Parity Generator/Checker ......•....•....•..........................
DM54/74AS881 B 4-Bit Arithmetic Logic Unit/Function Generator. . . . . . • . . . . . . . . . . . . . . . . .

3-85
3-93
3-129
3-132
3-136
3-256

Buffersl Drivers
DM54/74AS230 Octal TRI-STATE Bus Drivers/Receivers with
True and Inverting Outputs .. . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . •
DM54/74AS231 Octal TRI-STATE Inverting Bus Drivers/Receivers. . . . . . . . . • . . . . . . . . . . . . . . .
DM54/74AS240 Octal TRI-STATE Inverting Buffers/Une Drivers/Line Receivers .............
DM54/74AS241 Octal TRI-STATE Buffers/Line Drivers/Line Receivers. . . . . . . . . . . . . . . . . . . . .
DM54174AS244 Octal TRI:STATE Buffers/Line Drivers/Line Receivers. . . . . . . . . . . . . . . . . . . . .
DM54/74AS804A Hex 2-lnput NAND Line Driver ........................•.............
DM54/74AS805A Hex 2-lnput NOR Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS808A Hex2-lnputANDLineDriver........................................
DM54/74AS832A Hex2-lnputORLineDriver ................. : ............-...........
DM54/74AS1000 Quad 2-lnput NAND Drivers ...................................... , . .
DM54/74AS1004 Hex Inverting Drivers. . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . • . . • . . . . . . . . . .
DM54/74AS1008 Quad 2-lnput AND Drivers. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS1032 Quad 2-lnput OR Drivers ............... .' . . . . . . . . . . . . • . . . . . . . . . . . . . . .
DM54/74AS1034 Hex Non-Inverting Drivers. . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS1036Quad2-lnput NOR Drivers .. .i ......... , ................ , .......... ;. .

3-102
3-102
3-105
3-105
3-105
3-204
3-206
3-208
3-216
3-267
3-269
3-271
3-273
3-275
3-277

Counters
DM54/74AS160 Synchronous 4-Bit Decade Counter with Asynchronous Clear ..............
DM54/74AS161 Synchronous4-Bit Binary Counter with Asynchronous Clear ..........• _. . . .
DM54/74AS162 Synchronous 4-Bit Decade Counter with Synchronous Clear ...............
DM54/74AS163 Synchronous4-Bit Binary Counter with Synchronous Clear .......•....•...
DM54/74AS168 Synchronous 4-Bit UpJDown Decade Counter .. '. . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS169 Synchronous 4-Bit Up/Down Binary Counter .............................
DM54/74AS264 Counter Look Ahead Carry Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-70
3-70
3-70
3-70
3-77
3-77 3-124

Decorers/Encoders
DM54/74AS131 3 to 8 Line Decoder/Demultiplexer with Address
Storage Register ................' .............................. , . . . . . . . . . . . . . . .
DM54/74AS137 3 to 8 Line DecoderlDemultiplexerwith Address Latches .................
DM54/74AS138 3to8LineDecoderJDemultiplexer....................................

3-49
3-54
3-57

Flip-Flops
DM54/74AS74 Dual Positive-Edge-Triggered D F'lip-Flops with Preset and Clear. . . . . . . . . . . . .
DM54/74AS109 Dual Positive-Edge-Triggered J-K Flip-Flops with Preset and Clear. . . . . . . . . . .
DM54/74AS112 Dual Negative-Edge-Triggered J-K Flip-Flops with Preset arid Clear. . . . . . . . . .
DM54/7 4AS113 Dual_ Negative-Edge-Triggered J-K Flip-Flops with Preset . . . . . . . . . . • . . . . . . .
DM54/74AS114 Dual Negative-Edge-Triggered J-K Flip-Flops
with Preset, Common Clear, and Common Clock ................................ ;...
10

3-29
3-37
3-40
3-43
3-46

Table of Contents (Continued)
DM54/74AS174 Hex D Flip-Flops with Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS175 Quad D Flip-Flops with Clear and Complementary Outputs ................
DM54/74AS374 Octal TRI-STATE Positive-Edge-Triggered D Flip-Flops. . . . . . . . . . . . . . . . . . . . .
DM54/74AS534 Octal TRI-STATE Inverting Positive-Edge-Triggered D Flip-Flops. . . . . . . . . . . . .
DM54/74AS574 Octal TRI-STATE Positive-Edge-Triggered D Flip-Flops. . . . . . . . . . . . . . . . . . . . .
DM54/74AS575 Octal TRI-STATE Positive-Edge-Triggered D Flip-Flops
with Synchronous Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS576 Octal TRI-STATE Inverting Positive-Edge-Triggered D Flip-Flops. . . . . . . . . . . . .
DM54/74AS577 Octal TRI-STATE Inverting Positive-Edge-Triggered
D Flip·Flops with Synchronous Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS874 Dual TRI-STATE 4-Bit Positive-Edged-Triggered
D Flip-Flops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS876 Dual4-Bit Inverting Positive-Edge-Triggered D Flip-Flops. . . . . . . . . . . . . . . . . .
DM54/74AS878 Dual4-Bit Positive-Edge-Triggered D Flip-Flops with Synchronous Clear. .. . . .
DM54/74AS879 Dual 4-Bit Inverting Positive-Edge-Triggered
D Flip-Flops with Synchronous Preset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-82
3-82
3-150
3-157
3-164
3-167
3-170
3-174
3-236
3-240
3-244
3-248

Gatesflnverters
DM54/74ASOO Quad 2-lnput NAND Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS02 Quad 2-lnput NOR Gates ............................... ;.............
DM54/74AS04 Hex Inverters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS08 Quad 2-lnput AND Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS10Triple3-lnput NAND Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS11 Triple3-lnputANDGates..............................................
DM54/74AS20 Dual4-lnput NAND Gates . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .
DM54/74AS21 Dual4-lnput AND Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS27 Triple 3-lnput NOR Gates .............................................
DM54/74AS30 8-lnput NAND Gate .................................................
DM54/74AS32 Quad 2-lnputOR Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS34 Hex Non-Inverter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS86 Quad 2-lnput Exclusive-OR Gates. . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS136 Quad Exclusive-OR Gates with Open-Collector Outputs. . . . . . . . . . . . . . . . . . .
DM54/74AS810Quad 2-lnput Exclusive NOR Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS811 Quad 2-lnput Exclusive NOR Gates with Open Collector Outputs. . . . . . . . . . . .

3-5
3-7
3-9
3-11
3-13
3-15
3-17
3-19
3-21
3-23
3-25
3-27
3-32
3-52
3-210
3·213

Latches
DM54/74AS373 Octal TRI-STATE Transparent D Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS533 Octal TRI-STATE Inverting Transparent D Latches ........................
DM54/74AS573 Octal TRI-STATE Transparent D Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS580 Octal TRI-STATE Inverting Transparent D Latches ........................
DM54/74AS841 10-Bit Bus Interface D-Type Latches with TRI-STATE Outputs ...............
DM54/74AS842 10-Bit Inverting Bus Interface D-Type Latches
with TRI-STATE Outputs ........................................................
DM54/74AS843 9-Bit Bus Interface D-Type Latches with TRI·STATE Outputs ........•......
DM54/74AS844 9-Bit Inverting Bus Interface D-Type Latches with
TRI-STATE Outputs .:..........................................................
DM54/74AS845 8-Bit Bus Interface D-Type Latches with TRI·STATE Outputs ...............
DM54/74AS846 8-Bit Inverting Bus Interface D-Type Latches
with TRI-STATE Outputs ........................................................
DM54/74AS873 Dual TRI-STATE 4-Bit Transparent D Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS880 Dual4-Bit Inverting Transparent D Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11

3-147
3-154
3-161
3-178
3-218
3-218
3-222
3-222
3-227
3-227
3-232
3-252

Table of Contents (Continued)
Multiplexers/Demultiplexers
DM54/74AS151 8-Lineto 1-Line Data Selector/Multiplexer .......• :.. .•. . . ••. . .••. . .•. . .
DM54/74AS153 4-Line to 1-Line Data Selectors/Multiplexers ..... _•................ _. . . .
DM54/74AS157 Quad 2to 1 Line Data Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS158 Quad 2to 1 Line Inverting Data Selectors/Multiplexers. . . • . . . . . . . . . . • . . . . .
DM54/74AS251 TRI·STATE 8-Line to 1-Line Data Selector/Multiplexer with
'
,Complementary Outputs ..........................•.................. _. ; . .• .. . .
DM54/74AS253 Dual TRI-STATE 4-Line to 1·Line Selectors/Multiplexers ...................
DM54/74AS257 Quad TRI-STATE 2to 1 Line DataSelectors/Multiplexers .........• _....... _
DM54/74AS258 Quad TRI-STATE2to 1 Line Inverting Data Selectors/Multiplexers. . . . • . . . . . .
DM54/74AS352 Dual4-Line to 1-Line Inverting Data Selector/Multiplexer ..... . . . . . . . . . . . . •
DM54/74AS353 Dual TRI-STATE4-Line to 1-Line Data Selector/Multiplexer ..•.•.. _•.. ___ . . •

3-60
3-63
3-66
3-66
3-113
3-117
3-120
3-120
3-141
3-144

Registers
DM54/74AS95 4-Blt Parallel Access Shift Register ................•................. , .
DM54/74AS194 4-Bit Bidirectional Universal Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS195 4-Bit Parallel Access Shift Registers .•..................•.•...........

3-34
3-97
3-100

Transceivers
DM54/74AS242 Octal TRI-STATE Inverting Bu~ Transceivers. . . . . . . . . • . . . . . . . . . . . . • . . . . . .
DM54/74AS243 Octal TRI-STATE Bus Transceivers. . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS245 Octal TRI-STATE Bus Transceivers .........•.......•..... _. _. . . . . . . . . . .
DM54/74AS6200ctal TRI-STATE Inverting Bus Transceiver . . . . .•. .. . .. . . .. . • .•. . . ... . .• .
- DM54/74AS621 Octal Bus Transceivers with Open Collector Outputs. . . . . . . . . . . . . . . . . . . . . .
DM54/74AS622 09tallnverting Bus Transceivers with Open Collector Outputs. . . . . . . . . . . . . .
DM54/74AS623 Oqtal TRI-STATE Bus Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . .
DM54/74AS638 Octal Inverting Bus Transceivers with
OpenColleatorandTRI-STATEOutputs ..•............................. _...........
DM54/74AS639 Octal Bus Transceivers with Open Collector
andTRI-STATEOutputs ................................•.... ,'...................
DM54/74AS640 Octal TRI-STATE Inverting Bus Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS641 Octal Bus Transceivers with Open-Collector Outputs ....... ,.............
DM54/74AS642 Octal Inverting Bus Transceivers with Open-Collector Outputs. . . . . . . . . . . . . .
DM54/74AS643 Octal TRI-STATE True and Inverting Bus Transceivers. . . . . . . . . . . . . . . . . . • . . .
DM54/74AS644 Octal True and Inverting Bus Transceivers with
Open-Collector Outputs . _..................................... :. . . . . . . . . . . . . . . .
DM54/74AS645 Octal TRI-STATE Bus Transceivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS646 Octal TRI-STATE Bus Transceivers/Registers. . . . . . • . . . . . . . • . . . . . . . . . . . . .
DM54/74AS648 Octal TRI-STATE Inverting Bus Transceivers/Registers. . . . . . . . . . . . . . . . . . . .
DM54/74AS651 Octal TRI-STATE Inverting Bus Transceivers/Registers. . . .. . . . . . • . . . . . . . . .
DM54/74AS652 Octal TRI·STATE Bus Transceivers/ Registers ... ',' .•............ " . . . . . . . .
DM54/74AS2620 Octal TRI-STATE Inverting Bus Transceivers/MOS Drivers. . . . . . . . . . . . . . . . .
DM54/74AS2623 Octal TRI-STATE Bus Transceivers/MOS Drivers ................. ,'. . . . . . .
DM54/74AS2640 Octal TRI-STATE Inverting Bus Transceivers . . . . . • . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS2643 Octal TRI-STATE True and Inverting Bus Transceivers. . . . . . . . . . . . . . . . . . . . .
DM54/74AS2645 Octal TRI-STATE Bus Transceivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12

3-105
3-105
3-111
3-181
3-181
3-181
3-181
3-186
3-186
3-189
3-189
3-189
3-189
3-189
3-189
3-194
3-194
3-199
3-199
3-279
3-2793-282
3-282
3-282

Table of Contents (Continued)
Section 4-Low Power Schottky
Arithmetic Functions
DM54/74LS83A 4-Bit Binary Adders with Fast Carry •. . . . . . . . . . . . . . . . . • . . . . . . . • . . . • . . . .
DM54/74LS283 4·Bit Binary Adders with Fast Carry. . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . .

4-93
. 4·298

Buffersl Drivers
DM54/74LS26 Quad 2-lnput NAND Buffers with High-Voltage
Open-Collector Outputs ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . • . . . . . . • . . . . . . . . .• .
DM54/74LS37 Quad 2-lnput NAND Buffers. . . . . . . . . • • . . • . • . . . • • . • . . . . . . . . . . . . . . . . . . . •
DM54/74LS38 Quad 2-lnput NAN D Bufferswith Open·Coliector Outputs. . . . • . . • . . . . . . . . . . .
DM54/74LS40 Dual4-lnput NAND Buffers. . . • . . • . . . . . . . . • . . . . . . . . • . . . . . . . . . . . . . . . . . . .
DM54/74LS125A Quad TRI·STATE Buffers .•..........•.........•......•.......•......
DM54/74LS126A Quad TRI-STATE Buffers. . .. . .. . . .•. . . .. •. . .•. . .••. .•.. .•. . . .. . . ....
DM54/74LS240 Octal TRI-STATE Inverting Buffers/Line Drivers/Line Receivers •...........•
DM54/74LS241 Octal TRI·STATE Buffers/Line Drivers/Line Receivers. • . . . . . . . • . . . . . . . . . . .
DM54/74LS244 Octal TRI·STATE Buffers/Line Drivers/Line Receivers .....•.......•.......
DM54/74LS365A HexTRI-STATE Buffers/Bus Drivers. • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS366A Hex TRI-STATE Inverting Buffers/Bus Drivers. . . . • . . . . . . . . . • . . . . . . . . . . .
DM54/74LS367A HexTRI·STATE Buffers/Bus Drivers. . . . . . . • . . • . • . . • • . . . . . • . . . • . . . . . . .
DM54/74LS368A HexTRI·STATE Inverting Buffers/Bus Drivers. . . • . • . . . . . . . . • . . • . . . . . . . .
DM54/74LS465 (DM71/81 LS95A) Octal TRI-STATE Buffers/Bus Drivers .....•..............
DM54/74LS466 (DM71181 LS96A) Octal TRI·STATE Inverting Buffers/Bus Drivers. . . . . . . . . • . . .
DM54/74LS467 (DM71/81 LS97A) Octal TRI-STATE Buffers/Bus Drivers ...........•........
DM54/74LS468 (DM71/81 LS98A) Octal TRI·STATE Inverting Buffers/Bus Drivers. . . . • . . • • • . . .

4·41
4-49
4-51
4-53
4·140
4-143
4·255
4-255
4-261
4·320
4·323
4-326
4-329
4-348
4-348
4-348
4-348

Comparators
DM54/74LS85 4·Bit Magnitude Comparators. . . . . . . . . • . . . . • . . . • . . . . . . . . . • . • . • . • • . • . . .

4·97

Counters
DM54/74LS90 Decade Counter. . . . . . . . . . . . . • . • . . . . . . . . . • • . . . • . . . • . . • . . . . . . . . . . . . . . .
DM54/74LS92Divideby12Counter ... ,.............................................
DM54/74LS93 4-Bit Binary Counter . . • . . . . . • . . • . . . . . . . . • • • . . • . . . . . . . • . . • . . . . . . . . . .. .
DM54/74LS160A Synchronous 4·Bit Decade Counter with Asynchronous Clear •....•....••
DM54/74LS161A Synchronous 4·Bit Binary Counter with Asynchronous Clear ••...•...•...
DM54/74LS162A Synchronous 4-Bit Decade Counter with Synchronous Clear. • • . . . . . . • . . . .
DM54/74LS163A Synchronous 4·Bit Binary Counter with Synchronous Clear. . • • . . . . . • . . . . .
DM54/74LS168A Synchronous 4-BitUp/Down Decade Counter. . • . . . . . • . . . . . • . . . . . . . . . • •
DM54/74LS169A Synchronous4-Bit Up/Down Binary Counter . .••. .••. .•. .. ....•.... ....
DM54/74LS190 Synchronous4-BitUp/Down Decade Counter with Mode Control. • . . . • • . . . • •
DM54/74LS191 Synchronous4·BitUplDown Binary Counter with Mode Control .••.•••.. ••..
DM54/74LS192 Synchronous 4-Bit Up/ Down Decade Counter with Dual Clock . . • . . • . • . . . . . .
DM54/74LS193Synchronous4-Bit Up/Down Binary Counter with Dual Clock..... ...••. . .. .
DM54/74LS196 4·Bit Presettable Decade (Bi·Quinary) Counter ...••...........•.•...•..•
DM54/74LS197 4·Bit PresettableBinaryCounter. . . . • . • . • . . • . . . • • . . • . . • . . • . . . • . . • . • . . •
DM54/74LS290 4·BIt Decade Counter. • . . . . . . • . . . . • . . . • • . . . . . . . . • • . . . • . . . . . • . . • . • . . •
DM54/74LS293 4-Bit Binary Counter . . • . • .. . . . . • • • • . • • . . . . • . •• . .. . • • . . . . . . . . . • • . .. . •
DM54/74LS390 Dual4·Bit Decade (Bi·Quinary) Counter • • • . . . . . • . . • . • . . . . . . . . • . . . • • . • . . .
DM54/74LS393 Dual4·Bit Binary Counter ....•...••...•.•. : . • • • . . • • . • . . • . . • . • . . . • . . . .

13

4-104
4·104
4-104
4·178
4·178
4·178
4·178
4-200
4-200
4·221
4-221
4-227
4·227
4·242
4·242
4-302
4-306
4-341
4-345

Table of Contents (Continued)
Decoders/Encoders
DM54/74LS42 BCD to Decimal Decoder .............................................
DM54/74LS47 BCD to 7-Segment Decoder/Driverwith Open-Collector Out'puts .............
DM54/74LS48 BCD to 7-Segment Decoder/Driver with Internal
Pull-Up Resistor Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS49 BCD to 7-Segment Decoder/Driver with Open-Collector Outputs .............
DM54/74LS138 3t08LineDecoder/Demultiplexer ............................ ;',......
DM54/74LS139 Dual2 to 4 Line Decoders/Demultiplexers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS154 4to 16 Line DecoderlDemultiplexer ............................'.. .. . . .
DM54/74LS155 Dual2to 4 Line Decoders/1 t04 Line Demultiplexers. . . . . . .. . . . . . . . • . . . . . .
DM54/74LS156 Dual 2 to 4 Line Decoders/1to 4 Line Demultiplexers
with Open-Collector Outputs ........... : ........,................................
DM54/74LS247 BCD to 7-Segment Decoder/Driver with Open-Collector Outputs ..........•.
DM54/74LS248 BCD to 7-Segment Decoder/Driver. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .
DM54/74LS249 BCD to 7-Segment Decoder/Driverwith Open-Collector Outputs ............

4-55
. 4-58
4-58
4-58
4-152
4-152
4-165
4-168
4-168
4-267
4-267
4-267

Flip-Flops
DM54/74LS73A Dual Negative-Edge-Triggered J-K Flip-Flops with Clear ..................
DM54/74LS74A Dual Positive-Edge-Triggered 0 Flip-Flops with Preset and Clear ...........
DM54/74LS76A Dual Negative-Edge-Triggered J-K Flip-Flops with Preset and Clear ... : . . . . .
DM54/74LS78A Dual Negative-Edge-TriggerE!d J-K Flip-Flops with
Common Clear and Common Clock ..... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .
DM54/74LS107A Dual Negative-Edge-Triggered J-K Master-Slave Flip-Flops with Clear. . . . . .
DM!54/74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset and Clear ....... ,'.
DM54/74LS1'12A Dual fi!egative-Edge-Triggered J-K Flip-Flops with Preset and Clear. . . . . . . .
DM54/74LS113A Qual Negative-Edge-Triggered J-K Flip-Flops with Preset ................
DM54/74LS114A Dual Negative-Edge-Triggered J-K Flip-Flops
with Preset, Common Clear, and Common Clock ....................................
DM54/74LS174 Hex 0 Flip-Flops with Clear ............... .'. : . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS175 Quad 0 Flip-Flops with Clear and Complementary Outputs. . . . . . . . . . . . . . . . .
DM54/74LS374 Octal TRI-STATE Positive-Edge-Triggered 0 Flip-Flops ........•...........

4-73'
4-76
4-83
4-90
4-116
4-119
4-122
4-125
4-128
4-216
4-216
4-332

Gates/Inverters
DM54/74LSOO Quad 2-lnput NAND Gates ............................................
DM54/74LS01 Quad 2-lnput NAND Gates with Open-Collector Outputs. . . . • . . . . . . . .. . . . . . .
DM54/74LS02 Quad 2-lnput NOR Gates .................... : . . . . . . . . . . . . . . . . . . . • . . . . .
DM54/74LS03 Quad 2-lnput NAND Gates with Open-Collector Outputs. ; . . . . . . . . . . . . • . . . . .
DM54/74LS04 Hex Inverters .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS05 Hex Inverters with Open-Collector Outputs . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . .
DM54/74LS08Quad 2-lnputAND Gates .................................... _.........
DM54/74LS09 Quad 2-lnput AND Gates with Open-Collector Outputs .....•.........•.....
DM54174LS10Triple3-lnput NAND Gates ....................... : .................... ,
DM54/74LS11Triple3-lnputANDGates..............................................
DM54/74LS12Triple 3-lnput NAND Gates with Open-Collector Outputs. . . . . . . . . . . . . . . . . • . .
, DM54/74LS13 Dual4-lnput Schmitt Trigger NAND Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS14 Hex Schmitt Trigger Inverters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS15 Triple 3-lnput AND Gates with Open-Collector Outputs ....................•
·DM54/74LS20 Dual 4-lnput NAND Gates .............................................

14

4-5
4-7
4-9
4-11
4-13
4-15
4-17
4-19
4-21
4-23
4-25
4-27
4-30
4-33
4-35

Table of Contents (Continued)
DM54/74LS21 Dual4-lnput AND Gates ..............................................
DM54/74LS22 Dual4-lnput NAND Gates with Open-Collector Outputs . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS27 Triple 3-lnput NOR Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS30 8-lnput NAND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS32 Quad 2-lnput OR Gates ...... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS51 Dual2-Wide 2-lnput AN D-OR-INVERT Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS54 4-WideAND-OR-INVERTGates. . . .. .. .. . . . . .. . ... ..... . .... . .. . . .. . .. .
DM54/74LS55 2-Wide4-lnputAND-OR-INVERTGates .................................
DM54/74LS86 Quad Exclusive-OR Gates . . . . . .. . . . . . . .. . .. . . . .. . . . .. . . .. . . .. . . . . . . . . .
DM54/74LS132 Quad 2-lnput SchmittTrigger NAN D Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS136 Quad Exclusive-OR Gates with Open-Collector Outputs ... . . . . . . . . . . . . . . . .
DM54/74LS266 Quad Exclusive-NOR Gates with Open-Collector Outputs . . . . . . . . . . . . . . . . . .
DM54/74LS386 Quad Exclusive-OR Gates ......................................... , . .

4-37
4-39
4-43
4-45
4-47
4-67
4-69
4-71
4-101
4-146
4-149
4-292
4-338

Latches
DM54/74LS75 A-Bit Bistable Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LSn 4-Bit Bistable Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . .
DM54/74LS259 8-Bit Serial In to Parallel Out Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS279 QuadS-R Latches ......... " .... , ......... , .•... " ... ,. . .. . . .. . . . ..
DM54/74LS373 Octal TRI-STATE Transparent D Latches

4-80
4-87
4-289
4-295
4-332

Multiplexers/Demultiplexers
DM54/74LS151 1 of 8 Line Data Selector/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS153 Dual 1 of4LineDataSelectors/Multiplexers.............................
DM54/74LS157 Quad 2 to 1 Line DataSelectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . •
PM54/74LS158 Quad 2 to 1 Line Inverting Data Selectors/Multiplexers ....................
DM54/74LS251 TRI-STATE 1 of 8 Line Data Selector/Multiplexer with
Comp.lementary Outputs ..................•....................................
DM54/74LS253 Dual TRI-STATE 1 .
IOZl VB VOZl
(TRI·STATE ISINK!
Typical LS Device Curve

VClAMP vs IClAMP
Typical LS Device Curve

J'"
I

10

J

16
20
-1.6

1

ICLAMP vClAMP
-lBmA

.iI

-l.SV

I
-1,2

IOZ
IOZl -20pA
IOZH
20pA

IOZH
0
lOll

-10
-20
-0,8

o

-0,4

VCLAMP (V)

0,5 1,0 1,5 2,0 2,5 3,0 3,5
Voz (V)

TlIF16731·20

r:::t:"

TlIF/6731·23

Vee =MAX
Vce = MIN

iJN:::t.YT\.IF/6731-21

INPUT

Vee=MIN

J

-----+---

OUTPUT CONTROL -1>0-...

Rl

iJl

TLIFJ6731·25
TLIF/6731·22

1·14

VOZ
O.4V
2,7V

HIGH LEVEL OUTPUT CURRENT (OPEN-COLLECTOR
DEVICES ONLy)

AC SWITCHING CHARACTERISTICS
The AC switching characteristics are generally measured in
units of time (commonly in nanoseconds), and define how
long it takes forthe signal to propagate from the input to the
output. The definitions used in determining the pass/fail
status of each limit are not the same for AC as they are for
DC. The distinction lies in the fact that for DC operation
there exists one characteristic V·I curve on which the device
must operate. Devices are good if they operate on the correct side of the limit, and bad if they operate on the wrong
side of the limit. When dealing with certain AC parameters
(fMAX, tSET-UP, tHOLD, tRELEASE, t pw), the device can, and
usually does, operate on both sides of the databook limit.
The limit really implies a boundary that all devices are
guaranteed to exceed. Depending upon the parameter, the
device will either operate at all values above and some
below the limit, or it will operate at all values below and
some above the limit. In each case, the device is only
guaranteed to operate for all values on one side of the limit.
Although-the device will also operate beyond the limit, it is
not guaranteed to. Furthermore, device operation beyond
the limit is not considered a failure. For instance, take the
fMAX parameter with a min limit of 25 MHz. All devices are
guaranteed to operate at all frequencies below 25 MHz and
will operate in excess of 25 MHz, although this is not
guaranteed. Now, take the example of tSET-UP with a
minimum limit of 25 ns. All of the devices are guaranteed to
operate with a set-up time of 25 ns and longer, and will
operate with set·up times below 25 ns, although this is not
guaranteed either. Be aware that both of these specifications are listed in the minimum column in the databook, but
the Interpretation of what is failing differs significantly.

ICEX Is tested with the output in the high state. Vcc is set to
5.0V and the specified voltage (5.5V for LS) is applied to the
output. The inputs are at the threshold values (O.BV and
2.0V, depending upon the logic to put output in the high
state) and the resulting ICEX leakage current is measured.

ICEX'vs VOUT
(Open·Coliector Device)
Typical LS Device Curve

250 ...-..................,.----r--r--,.---,
200 1--+-+--11--+-+-+--1
150

I--+--+~I-+--+-+--I

1 100 1--+--+--11-+--+-+--1

I!

ICEX

vOUT

250.A

5.5V

501--~+-+--1--+--+-~

-50

I-...I-....L.--I._I.-..J.......l--J

o

3

4

6

7

VOUT (V)
TL/F/6731·26

Propagation delays (called prop delays and denoted by
the symbols tpHL and tpLH) are specified as maximum
limits, and guarantee the maximum time one must wait to
Insure that the correct data has appeared at the device's
output. Prop delay specifications often show "typical"
limits. These "typical" limits are representative of the
general distribution of a manufacturer and not of anyone
lot of product purchased. Each propagation delay is
specified from one input to one output only.

Vee = MAX

.. ""{=?-.' VO~T=MAX
TLIF/6731·27

Input set· up and hold times (including tRELEASE! specify
how long one Input must be stable at a particular logic
level prior to an action occurring at another input. For ex·
ample, take the DM54/74LS74 positive·edge·triggered D
flip-flop. The "set·up 1" specification defines how long a
logic "1" must be present and stable at the DATA input
prior to the positive edge of the CLOCK to insure that the
device will recognize that data as a "1." There also exists a
"hold 1" specification which specifies how long a logiC
"1" must be held after the active edge of CLOCK for the
device to recognize that logic "1." Both the set·up and hold
times must always be met or the device will not necessarIly bring in the proper data. Set-up times are generally
positive, while hold times may be either positive or negative, usually negative. The meaning of a negative hold time
is that the data may be removed from the input prior to the
active edge of CLOCK, and the CLOCK will still bring in the
desired data. Set-up and hold times are specified as
minimum values, since this defines the minimum time
data must be stable prior to any change at the CLOCK in·
put. Removing the data sooner than the minimum time
may cause Improper action on the part of the device.

Vee MAX

VOUT=MAX

TLIF/6731·28

1-15

o
c

~

Cr
CD
c;}

UI

S·

c.c

tRELEASE is specified on devices where there Is an input
that must be set inactive prior to the active edge of
CLOCK. Such inputs are usually overriding inputs like
CLEAR and PRESET. With CLEAR active, it will preventthe
device from switching on ihe CLOCK signal. tRELEASE is
defined as the time it takes for the CLEAR input to
"release" the device for clocking action, and is specified
as a minimim. This represents the maximum delay required between CLEAR going Inactive and the active edge
of CLOCK to insure proper device operation.
All devices that have a CLOCK input also have a.speclficatlon that defines the maximum speed.that the CLOCK can
be driven, called f MAX. This specification is defined as a
minimum specification and states that all of the devices
will be able to operate at frequencies up to 25 MHz. Forthe
DM54/74LS7 4 with an f MAX of 25 M Hz, all of the devices are
guaranteed to operate at all clock frequencies, up to and
including 25 MHz. Although no devices are guaranteed to

operate above fMAX (only below it), most devices will
operate beyond the maximum specification. The
minimum limit does not state that the device will not
operate below fMAxorthat any devices that do are bad, but
rather that all the deviceS will operate up to the limit.
Table IV shows the direction of the tighter testing for the
more common AC parameters. All prop delays (those AC
parameters that have the symbols t pLH or tpHU have simple min/max limits. The device is guaranteed to operate
within the bounds of the min/max limits, and any operation outside these limits denotes a device failure. tSET.UP,
tHOLD, f MAX, and tRELEASE parameters have IImtts that
denote guaranteed operation boundaries (I.e., the device
is guaranteed to operate up to the boundary) but no
gu.arantee is made concerning the device operation (or
lack of it) beyond the boundary.
For detailed information on the AC waveforms, please see
the test waveforms in this section.

TABLE IV. Looser/Tighter AC Test Limits Example: DM74LS74
Test

From

fmax(min)
tPLH(max)
tPHL(max)
tW(mln)
tW(min)
tSET·UP(min)
tSET.UP(mln)
tHOLD(mln)

CLR,PRE,CLK
CLR,PRE,'CLK
CLOCK HIGH
PRE, CLR LOW
DATA HIGH
DATA LOW
All DATA

Looser
24
26
31
21
26
21
21
1

1-16

Nominal
25
25
30
20
25
20
20
0

Tighter
26
24
29
19
24
19
19
-.1

Units
MHz
ns
ns
ns
ns
ns
ns
ns

.--------------------------------------------------------------.~

Glossary of Terms

0'
t/)

DC Operating Conditions and Characteristics

Q)

t/)

GENERAL DEFINITIONS
I: Current is the flow of electric charge from one potential to another through a conductor_ The unit of measure
is the Ampere, or Amp, abbreviated A. One Amp is equal
to the current flowing through one ohm of resistance
when one volt is applied across that resistance. Common
units found in the semiconductor industry are the milliampere, abbreviated mA, equal to 0.001 A and the microampere, abbreviated /lA, equal to 0.000001A. Negative
current is defined as current flowing out of a device terminal and positive current is defined as current flowing
into a device terminal.

IT - Current at Negative-going Threshold Point: The current flowing out of a transition-operated (Schmitt trigger)
input when a voltage equal to the negative going threshold voltage is applied to the input.

OUTPUT CURRENT PARAMETERS
IcEx Output Leakage Current: The current flowing into
an open collector output when input conditions have
been applied that, according to the product specification, will cause the output to be in the logic high state.
This test checks the reverse breakdown of the output
transistor.

V: Voltage, or the electromotive force which causes current to flow through a conductor. One Ampere of current
flowing through one ohm of resistance develops a potential difference of one volt across that resistance. The unit
of measure is the Volt, abbreviated V, and a common unit
is the millivolt, abbreviated mV, equal to O.OOlV.

10(011) Oil-State Output Current: The current flowing
into an output with input conditions applied that, according to the product specification, will cause the output
switching element to be in the off state,

INPUT CURRENT PARAMETERS

NOTE: This parameter is usually specified for open collector outputs intended to drive devices other than logic
circuits" such as displays. Any leakage current applied to
a display may cause the display to be activated.

II Maximum High Level Input Current: Current flowing
into an input when that input has the maximum voltage
specified for the family applied to it. This test is used to
guarantee the minimum reverse breakdown voltage of
the input structure.

10H High Level Output Current: The current flowing out
of an output with input conditions applied that, accord,
ing to the product specification, will establish a logic
high level at the output. This test guarantees the current
sourcing (drive) capability of the output and the fan-out
specified for the family.

IIH High Level Input Current: The current flowing into an
input when that input has a high level voltage equal to
the minimum high level output voltage specified for the
family. This test is used to check the emitter-to-emitter
leakage and the inverse transistor action of a multiemitter transistor input, the input leakage of a diode,
PNP transistor, or CoB short type of input, and to guarantee the fan-in specified for the family.

10l Low Level Output Current: The current flowing into
an output with input conditions applied that, according
to the product specification, will establish a logic low
level at the output. This test guarantees the current sinking capability of the output and the fan-out specified for
the family.

11K' In~ut

Clamp Current: The current flowing out of an
input when that input is pulled below ground. This test is
used to guarantee the integrity of the input clamp diode.
The input clamp diode is used to limit the voltage swings
on the input by clamping the negative excursions to a
,level equal to one diode drop below ground. This serves
to reduce ringing on an incoming signal. Pulling the input
below ground for an extended length of time can cause
parasitic transistor action to occur between adjacent
tanks on the die which can cause erroneous data to occur on the outputs of the device. To prevent this, voltages
on the inputs during operation (other than high speed
ringing) should be limited to no more than 0.5V below
ground at all times.

los Output Short-Circuit Current: The current out of an
output when that output is shorted to ground, or another
specified potential, with input conditions applied that,
according to the product specification, will establish a
logic high level at the output.
,Ioz High-Impedance State Output Current: These tests
guarantee that the device will not excessively load a bus
line when the device output is put into the TRI-STATE®
mode.
10ZH (or IsINK!: The current flowing into an output with Input conditions applied to the output control pin such that
the output is in the high impedance state and input conditions applied to the other inputs that, according to the
product specification, will establish a logic low level at the
output.

III Low Level Input Current: The current flowing out of
an input when a low level voltage equal to the maximum
low level output voltage specified for the family is applied to the input. This test is used to check the input
pull up resistor on an MET or a diode input and to guarantee the specified fan-in of the family.

10Zl (or ISOURCe!: The current flowing out of an output with
input conditions applied to the output control pin such
that the output is in the high impedance state and Input
conditions applied to the other inputs that, according to
the product specification, will establish a logic high level
at the output.

IT + Current at Positive-Going Threshold Point: The current flowing out of a transition-operated (Schmitt trigger)
input when a voltage equal to the positive going threshold voltage is applied to the input.

1-17

- 1000 pF

Yes
Yes

Yes
Yes

None
None

5
5

180
260

tw= KRC
K=0.45

5

tw= KRC.(l +0.7/R)
K=0.55

DM54123
DM74123

Two
Two

Yes
Yes

Yes
Yes

None
None

5

25
50

tw= KRC.(l + 0_7/R)
K=0.34

DM54LS123
DM74LS123

Two
Two

Yes
Yes

Yes
Yes

None
None

5
5

180
260

tw= KRC
K=0.45

DM54LS221
DM74LS221

Two
Two

No
No

Yes
Yes

1.4
1.4

70
100

tw=KAC
K=0.7

DM8601
DM9601

One
One
Two
Two

Yes
Yes

No
No

None
None

5
5

tw= KAC.(l + 0.7/A)
K=0.32

Yes
Yes

Yes
Yes

None
None

5

25
50
25
50

DM8602
DM9602

0
0

1000
1000

5

tw= KAC.(l + 1IA)
K=O.31

'The above timing equations hold for all combinations of AEXT and CEXT for all cases of CEXT > 1000 pF within specified limits on the
AEXT and CEXT'

1-25

III

~

"'Z"
CO)

1000 pF. For cases where
the CEXT <1000 pF, use the graphs
shown below.

105
R=50K

TA=25°C
Vcc=5,OV
R=50K

104

..s~

R=5K

=R=25K

......

103

"'R~1.4K"

102
10 L-...L.Ll..llIJ:.tL.....L...L.I..LlJllJJ
10
100
1000

~R=5~
10
10

1000

100
CEXT (pF)

CEXT (pF)

TUFI7508-10

TUF17508-9

DM74123

DM74LS221

DM74LS123

'J~.~~:~

TA=25°C
Vee =5,OV ,

....

....

UA

r==

F==J:R,;,,'
10

L -......w...!..L.1.w...--l....I....JL..U.WJ

10

100

1000

10
10

100

1000

TUf'f7508-11

TUFn508·12

1·28

10
.10

=~=1.4K

100

1000

CEXT (pF)

CEXT (pF)

CEXT (pf)

R=5K

~ ~50K

1='
t:;R=1

R=100K
A'

I

TUFn5Q8..13

Typical Output Pulse Width Variation vs Ambient Temperature
The graphs shown below demonstrate the typical shift in the device
output pulse widths as a function of
temperature. It should be noted that
these graphs represent the temperature shift of the device after being
corrected for any temperalure shift
in the timing components. Any shift
in these components will result in a
corresponding shift in the pulse
width, as well as any shift due to the
device itself.

DM74121

DM9602

10

.

Rm=5K
Cm = 1000 pF
Vee=5.0V

5

.....

w

z

...
~

r.......

0

~

I

~

~I . . . . .r - -

I I

-5

II

....
~

51"

:z:

0

z

I

~

~

~I

I

I

i

i1

TliF17508·14

TLlFI7508·15

DM74123

10

10 ,-,--,-,r-,--,-,--,

O~

I

I I
-10
-60 -30 0 30 60 90 120 150
AMBIENT TEMPERATURE ('C)

DM74LS123

I

Rm=10K
Cm = 1000 pF
Vee=5.0V -

I
I
I
-10
-60 -30 0 30 60 90 120 150
AMBIENT TEMPERATURE ('C)

74LS221
Rm=10K
I I
Cm = 1000 pF
5 . Vee=5.0V - ! - - - - - - I

:

i I

-5

i

""-

!

~

i

I

I

I

I"-J

...
...

Rm= 10K
Cm=1000 pF
5 . Vee=5.0V

Rm=10K
Cm = 1000 pF
Vee=5.0V

w

-

z

:z:

0

-~

~

~

V

i

!

i

,~

.

~

-

5

r---...

_.- c--.

..

-5

-5 ~-------------I

.
z

..

,_. r -

~
~

o

i
I"
- 5 f----;'---+----l'----j

I
-60 -30 0 30 60 90 120 150
AMBIENT TEMPERATURE ('C)

I i
-10
-60 -30 0 30 60 90 120 150
AMBIENT TEMPERATURE ('C)

-10 '---'------'---------'
-60 -30 0 30 60 90 120 150
AMBIENT TEMPERATURE ('C)

TUF17508-16

TUF!7508-17

TUFf7508·18

-10 ,---,-I_______---'____...J

Typical Output Pulse Width Variation vs Supply Voltage
The following graphs show the dependence of the' pulse width on Vee.
As with any IC applications, the
device should be properly bypassed
so that large transient switching currents can be easily supplied by the
bypass capacitor. Capacitor values
of 0.001 p.F to 0.10 p.F are generally
used for the Vee bypass capacitor.

DM9602

DM74121

10

.

10

Rm=10K
CeXT = 1000 pF
TA=25'C
5 -

~

Z

5

or--

~

~

V

--

Rm=5K
CexT=1000 pF

..

r- TA=25'C

...:z:

i

--

---

0

~

~

-5

-10

-10
4

4.5

5

5.5

6

4

4.5

Vee (V)

5

DM74123

:

!

!

..J...=-::":L. __

~--:

r

-5

-10

j
I

i--

l

~------~-----'--~

4

4.5

5

5.5

DM74LS221

10

.

ReXT = 10K
CeXT = 1000 pF
TA=25'C

5

~

Z

...:z:

0

f-.--

~

6

TLJF/7SOB-20

DM74LS123

t--

.

5.5

Vee IV)
rUFI7SOB·t9

1 0 , - - - -__- - . - - .
Rm=10K
I
Cm=1000pF
I
TA=25'C
r---

--

--

w

z

I

-5

5

~

-5

10

-

..

Rm =5K
Cm=1000 pF
TA=25'C

5

w

Z

...:z:

0

~

~

-5

-10

-10
4

4.5

5

5.5

6

Vee (V)

Vee (VI
TLIF/750B·21

4.5

5

5.5

6

Vee (V)
TUFI750B-22

1-2(1

4

TUFI7508-23

Typical "K" Coefficient Variation vs Timing Capacitance
For certain one-shots, the "K" coefficient is not a constant, but varies
as a function of the timing capacitor
CEXT' The graphs below detail this
characteristic.

DM9602

DM74121
TA=25°C
Vcc= 5.0V

TA=25°C
Vee=5.0V

1\

10

10
0.1

1.0
UK U COEFFICIENT

10

1.0
UK" COEFFICIENT

0.1

TlJFI7508-24

DM74123

10
0.1

1.0
UK" COEFFICIENT

TLlFf75Q8-25

DM74LS221

DM74LS123
TA=25°C
Vee-5 .OV

TA-25°C
Vee-5.0V

10
0.1

10

TA-25°C
Vcc=5.0V

1.0
UK" COEFFICIENT

10

1\

10
0.1

1.0

10

UK" COEFFICIENT
TUFI7508-28

TUFI7508-27

Typical Output Pulse Width vs Minimum Timing Resistance
The plots shown below demonstrate
typical pulse widths and limiting values of the true output as a function
of the external timing resistor, REXT'
This information should evaporate
those years of mysterious notions
and numerous concerns about operating one-shots with lower than recommended minimum REXT values.

. DM74121

DM9602

ttt

TA-25°C
1--Ee,Vcc=5.0V
CEXT-1000 pF

TA-25°C
~ Vcc-5.OV

Cexr-1000 pF

I

10
100

1000
REXTIII)

10000

III

1000

III

10000

REXTIO)
TUF/750S02'

1-30

10
100

TUFnS08-30

DM74LS123

DM74123
105

105

10'

!

103

~

10'

DM74LS221

_ __ _ _

~f.t'j111

TA=25"C.
Vee = 5.0V:
Cm= 1000 pF
I

~TA=25"C

W --

Vee=5.0!.
104 ~Cm=moo pF

i!

II
I I 1'1

;

103

i.11

!!; : II!!I
:l::i

10'

Vee=5.0V
CEXT = 1000 pF

==--.-

~-~-!1!_II~!k!11
10'

--

t

10
100

10

1000

10000

1000

Rm (11)

100

10000

1000

Rm (n)
TUFn508-31

TUFnS0s.33

Connection Diagrams
54121 (J, WI; 74121 (N)

'121 One·Shots
Inputs

Outputs

A1

A2

8

Q

Q

L

X
L
X

H
H
L

L
L
L
L

H
H
H
H

H
H

H

X

~

~
~

H
~

H
H
H

L
X

X
L

t
t

..rt..
..rt..
..rt..
..rt..
..rt..

Vee

NC

NC

NC

Al

Rml
Cm

CEXT

Clear

A1

A2

81

82

Q

Q

L

X

X

X
X
X
X
H
H
H

H

H

X
X
X
X
X

L
L
L
L
L

H

t

X
X
X
L
H
H

H
H

X
X

X
X
L
X

H
H

..rt..
..rt..

LJ"
LJ"

H

L

H

t

H

..rt..
..rt..
..rt..
..rt..
..rt..
..rt..
..rt..

LJ"
LJ"
LJ"
LJ"
LJ"
LJ"
LJ"

H

H
H
H
H

t
t
H
L

t

X
X
X
H

L
L
L

H

H
H

t
t

~
~

H

L

H
X

H
H

H
H
H
H

X

L

H

H

~
~

GNU

A2

TOP VIEW

Outputs

Inputs

NC

LJ"
LJ"
LJ"
LJ"
LJ"

'122 Retriggerable One·Shots with Clear

L
L
L

10000

Rm(ll)
TUFnS08-32

Function Tables

X
X

-

TUFf750B-34

54LS122 (J, WI; 74LS122 (N)

H

H

=HIGH Level
=Transition from LOW·te-HIGH

= LOW Level

~ = Transilion from HIGH·lo·LOW
..rL= One HIGH Lovel Pulse
'1J" = One LOW Level Pulse
X = Don't Care

Al

1·31

A2

81

82
TOP VIEW

ClR

GNO
TLlF17508-35

III

~

Z


TUFI7508-41

FIGURE 8. Noise Discriminator

1-33

Nr-----------------------------------------------------------------------------,

_______n___

"'"
Z

C")

o...-L..:.)OTti;><:~ +SEP elK

TUFn508-59

FIGURE 16. FM Data Separator (Continued)

Phase· locked Loop veo (Figure 17)
positive"or negative·golng phase error will be applied to
the op·amp to effect a change in the VCO frequency.
Figure 17 illustrates the process of phase·error detection and correction when synchronizing to a data bit pat·
tern. The rising edge of each pulse at DATA+ PLO clocks
the one-shot lOW and the phase detector FF HIGH.
Since both outputs are still bucking each other, no
change will be observed at the phase·error summing
node. When the one·shot times out, if this occurs after
the 2F clock has reset the phase detector FF to a LOW
output, a positive pulse will be seen at the summing
node until both the one-shot and the FF are reset. Any
positive pulse will be reflected by a negative change in

The circuit shown in Figure 17 represents the VCO in
the data separation part of a rotational memory storage
system which generates the bit rate synchronous
clocks for write data timing and for establishing the
read data windows.
The op·amp that performs the phase·lock control oper·
ates by having its inverting input be driven by two
sources that normally buck one another. One source is
the one·shot, the other source is the phase detector flip·
flop. When set, the one·shot, through an inverter, sup·
plies a HIGH·level voltage to the summing node of the
op·amp and the phase detector FF, also through an inverter, supplies a cancelling lOW-level input.
It is only when the two sources are out of phase with
each other, that is one HIGH and the other lOW, that a

1-39

0

that a clamping circuit be connected to the output of the
op-amp to prevent the veo' control voltage from going
negative or, more positive than necessary. A back-to, back diode pair connected between the op-amp and the
veo is highly recommended, for it will present a high
impedance to the veo input during locked mode. This
way, stable and smooth operation of the PLO circuit is
assured.

the op-amp output, which is integrated and reduces the
positive control voltage at the veo input In direct proportion to the duration of the phase-error pulse. A negative phase-error pulse occurs when the phase detector
FF remains set longer than the one-shot.
Negative phase-error pulse causes the Integrated control voltage to swing positive in direct proportion to the
duration of the phase-error pulse. It Is recommended

2F Bit Rate Synchronous Read/Write Clock
Vee

READ
READ DATA
ENABLE
lOCAL OSCillATOR

IImJ

Vee
oATA+PlO

~r-------------------~~D3
O-S

ClK

03

2F

'il3

TUFn508-60

BIT CEll
NRZoATA

I

MFM DATA

YCD 12F)

n. ._________

HRRDR _ _ _ _...

~.....___. . . .,

U--

LIlI
TL/Fn5Ofl.61

FIGURE 17. Phase·Locked Loop Voltage Controlled Oscillator
1-40

A FINAL NOTE

It is hoped that this brief note will clarify many pertinent
and subtle pOints on the use and testing of one-shots. We
invite your comments to this application note and solicit
your constructive criticism to help us improve our service
to you.
ACKNOWLEDGEMENT

The author wishes to thank Stephen Wong, Bill Llewellyn,
Walt Sirovy, Dennis Worden, Stephen Yuen, Weber Lau,
Chris Henry and Michelle Fong for their help and
guidance.

1-41

~r-----------------------------------------------------------------------------~

'0

'5

CJ

c

o

~

i
i'0

.5
1i
c
o

::::
u

Functionallndex/Selection Guide
It

Several methods are used to represent typical values. For propagation delay typical values, the average of the typical values of the two delays afe used.
[ tPHL(TYP)

~ tPLH(TYP) ]

For power dissipation, the average of the typical values of current for all states the outputs can achieve Is used. (ICCL, ICCH' ICcz). This current value is
multiplied by nominal supply voltage (5V), and in some case divided by the number of gates, bits, etc. All other typical values are singular typlcals.

Adders

Description

Device Type·

Single 4·Blt
Full Adders

54/74LS283
54f74S283
54/74LS83A
54/7483

c

.z

Typ'
Carry
Time
(ns)

Typ'
Add
Time
(ns)

Typ'
Power
Dlss.
IBlt
(mW)

Mil

Com

12
8.5
12
12

15
11
15
20

24
110
24
73

J,W
J,W
J,W
J,W

N
N
N
N

Package
Avail.

Page

4·298
5·147
4·93
6·113

Arithmetic Logic Units, Carry Look·Ahead Generators

Description

4·Blt ALUI
Function
. Generators

Carry
Look·Ahead
Generator

Device Type

Typ'
Carry
Time
(ns)

Typ'
Add
Time
(ns)

Typ'
Power
Dlss.
Total
(mW)

Mil

Com

54f74A5181B
54f745181
54/74181
54f745381
54/74A5881 B

5
7
12.5
10
5

5
14
18
12
5

675
600
455
525
675

J
J,W
J,W
J,W
J

N
N
N
N
N

3·85
5·100
6·245
5·165
3·256

5
9
6
6

N/A
N/A
N/A
N/A

115
345
140
130

J
J,W
J
J

N
N
N
N

3·93
5·108
3-124
3·132

54f74A5182
54f745182
54/74A5264
54/74A5282

Package
Avail.

Page

BufferslClock Drivers with Totem·Pole Outputs

Description

Device Type

Low·
Level
Output
Current
(mA)

Dual 4·lnput
NAND Buff.ers

54AL540
74AL540
54L540
74L540
54/74540
54/7440
54AL51020
74AL51020

12
24
12
24
60
48
12
24

-1
-2.6
-1.2
-1.2
-3
-1.2
-1
-2.6

4
4
10
10
4
10.5
4

3.5
3.5
4.3
4.3
44
26
3.6
3.6

54AL537
74AL537
54L537
74L537
54/7437
54AL51 000
74AL51 000
54A51 000
7.4A51000

12
24
12
24
48
12
24
40
48

-1
-2.6
-1.2
-1.2
-1.2
-1.
-2.6
-40
-48

5
5
10
10
10.5
5
5
2
2

5
5
4.3
4.3
27
3.5
3.5
8.5
8.5

Quad 2·lnput
NAND Buffers

High·
Level
Output
Current
(mA)

1·42

Typ'
Prop.
Delay
Time
(ns)

Typ'
Power
Diss.
IGate
(mW)

"4

Package
Avail.
Mil

Page

Com

J
N

J,W
J,W
J,W
J

N
N
N
N

J
N

J,W
J,iN
J
J
J

N
N
N
N
N

2·58
2·58
4·53
4·53
5·33
6·63
2·287
2·287
2·54
2·54
4·49
4·49
6·62
2·271
2·271
3·267
3·267

"c

::s
n

BufferslClock Drivers with Totem·Pole Outputs (Continued)

O·

Low· .
Level
Output
Current
(rnA)

High·
Level
Output
Current
(rnA)

Typ·
Prop.
Delay
Time
(ns)

Typ·
Power
Diss.
IGate
(mW)

54ALS28
74ALS28
54ALS1002
74ALS1002
54AS1036
74AS1036

12
24
12
24
40
48

-1
-2.6
-1
-2.6
-40 .
-48

3.7
3.7
3.7
3.7
2
2

4.5
4.5
4.5
4.5
9.7
9.7

J

54ALS1032
74ALS1032
54AS1032
74AS1032

12
24
40
48

-1
-2.6
-40
-48

5.5
5.5
2.5
2.5

5.7
5.7
14
14

J

54ALS1008
74ALS1008
54AS1008
74AS1008

12
24
40
48

-1
-2.6
-40
-48

5.6
5.6
2.5
2.5

4.7
4.7
12
12

J

Triple
3·lnput NAND

54ALS1010
74ALS1010

12
24

-1
-2.6

4
4

3.6
3.6

J

Triple
3·lnpul AND

54ALS1011
74ALS1011

12
24

-1
-2.6

6.4
6.4

4.75
4.75

J

Hex Buffers

54ALS1034
74ALS1034
54AS1034
74AS1034

12
24
40
48

-12
-15
-40
-48

4.5
4.5
2.5
2.5

4.6
4.6
11.9
11.9

J

54ALS1004
74ALS1004
54AS1004
74AS1004

12
24
40
48

-12
-15
-40
-48

2.6
2.6
1.7
1.7

. 3.3
3.3
8.5
8.5

J

Description

Quad 2·lnpul
NOR Buffers

Quad 2·lnpul
OR

Quad 2·lnpul
AND

Hex Inverter
Buffers

Device Type

Package
Avail.
Mil

Page

Com
2·46
2·46
2·273
2·273
3·277
3·277

N

J
N

J
N

2·289
2·289
3·273
3·273

N

J
N

N

2·281
2·281
3·271
3·271

N

2·283
2·283

N

2·285
2·285

N

J

2·291
2·291
3·275
3·275

N

J
N

2·277
2·277
3·269
3·269

N

J
N

,

Buffers/Clock Drivers with Open·Coilector Outputs

, Description

Quad 2·lnpul
NAND Buffers

,

Device Type

54ALS38
74ALS38
54LS38
74LS38

54/7438
54LS26
74 LS26

54/7426
54L26
74L26
54ALS1003
74ALS1003

(V)

Low·
Level
Output
Current
(rnA)

Typ·
Prop.
Delay
Time
(ns)

5.5
5.5
5.5
5.5
5.5
15
15
15
15
15
5.5
5.5

12
24
12
24
48
4
8
16
2
3.6
12
24

14.5
14.5
15
15
12.5
16
16
13.5
33
33
14.5
14.5

High·
Level
Output
Voltage

1-43

Typ·
.' Power
Dlss.

Package
Avail.

Page

IGate.
(mW)

Mil

3.5
3.5
4.3
4.3
24.4
2
2
10
1
1
3.5
3.5

J

Com
N

J,W
J,W
J,W
J,W
'J,W

N
N
N
N
,

N

J
N

2·56
2·56
4·51
4·51
6·64
4·41
4·41
6·54
7·23
7·23
2·275
2·275

::s
!!..

5'
c.
~

~

-O~·
::s

Q

c

a:
CD

CD

"0
·s

Buffers/Clock Drivers with Open·Coliector Outputs (Continued)

CJ

c
o

i

Description

Davice Type

Jj

i

"0

.5
fti
c
o

5.5
5.5

12
24

13.5
13.5

4.5
4.5

J

30
40

21
21
21
21
4.6
4.6

J,W

40
12
24

13
13
13
13
12.5
12.5

30
40
30
40
12
24

12.5
12.5
12.5
12.5
12.5
12.5

26
26
26
26
3.3
3.3

J,W

54ALS33
74ALS33

Hex Buffersl
Drivers

5407
7407
5417
7417
54ALS1035
74ALS1035

30
30
15
15
5.5
5.5

5406
7406
5416
7416
54ALS1005
74ALS1005

30
30
15
15
5.5
5.5

13c
~

LL
Hex Inverter
Buffersl
Drivers

Typ·
Power
Diss.
/Gate
(mW)

Low·
Level
Output
Current
(mA)

Quad 2·lnput
NOR Buffers

,

Typ·
Prop.
Delay
- Time
(ns)

High·
. Level
Output
Voltage
(V)

30

Package
Avail.
Mil

Page

Com

'N
N

J,W
N

J
N
N

J,W
N

J
N

2-52
2-52
6-30
6-30
6-48
6-48
2-293
2-293
6-28
6-28
6-46
6-46
2-279
2-279

Buffer Gates with TRI·STATE'" Totem·Pole Outputs

Max
Sink
Current
(mA)

Typ·
Prop.
Delay
Time
(ns)

o

Typ·
Power
Diss.
IGate
(mW)

,Description

Device Type

Max
Source
Current
(mA)

Quad Buffers

54LS125A
74LS125A
54125
74125
54LS126A
74LS126A
54126
74126

-1
-2.6
'-2
-5.2
-1
-2.6
-2
-5.2

12
24
16
16
12
24
16
16

10
10
11
11
10
'\0
11
11

14.4
14.4
40
40
14.4
14.4
45
45

J,W

,54LS365A
74LS365A
54365
74365
54LS367A
74LS367A
54367
74367

-1
-2.6
-2
-5.2
-1
-2.6
-2
-5.2

12
24
32
32
12
24
32
32

10
10
10.5
10.5
10
10
12
1,2

10.8
10.8
51.6
51.6
10.8
10.8
51.6
51.6

J,W

54LS366A
74LS366A
54366
74366
54 LS368A
74LS368A
54368
74368
70L98
80L98

-1
-2.6
-2
-5.2
-1
-2.6
-2
-5.2
-1
-1

12
24
32
32
12
24
32
32
2
3.6

10
10
10.5
10.5
10
10
10.5
10.5
30
30

10.8
10.8
51.6
51.6
10.8
10.8
51.6
51.6
3
3

J,W

Hex Buffers

Hex Inverter
Buffers

1-44

Package
Avail.
Mil

Page

Com
N

J,W
N

J,W
N

J,W
N
N

J,W
N

J,W
N

J,W
N
N

J,W
N

J,W
N

J,W
N

J,W
N

4-140
4-140
6-157
6-157
4-143
4-143
6-160
6-160.
4·320
4-320
6-309
6-309
4-326
4-326
6·315
6-315 .
4-323
4-323
6-312
6·312
4-329
4·329
6-318
6-318
7-91
7-91

Buffer Getes with TRI-8TATE Totem·Pole Outputa (Continued)
Max
Sink
Current
(mA)

Typ·
Prop.
Delay
Time
(na)

Typ·
Power
Dlaa.
IGate
(mW)

Deacrlptlon

Device Typa

Max
Source
Current
(mA)

Octal Buffers

54AL5465
74AL5465
54L5465
74L5465
54AL5467
74AL5467
54L5467
74L5467

-12
-15
-2.6
-5.2
-12
-15
-2.6
-5.2

12
24
12
24
12
24
12
24

6.6
6.6
14.5
14.5
6.6
6.6
14.5
14.5

8.6
8.6
10
10
9.1
9.1
10·
10

54AL5466
74AL5466
54L5466
74L5466
54AL5468
74AL5468
54L5468
74L5468

-12
-15
-2.6
-5.2
-12
-15
-2.6
-5.2

12
24
12
24
12
24
12
24

4.8
4.8
9.5
9.5
4.7
4.7
9.5
9.5

7.5
7.5
8
8
7.5
7.5
8
8

12·lnput NAND
Gate/Buffer

54/745134

-6.5

20

4.5

45

J,W

Quad Inverter
Transceivers

54AL5242
74AL5242
54A5242
74A5242
54L5242
74L5242
545242
745242

-12
-15
-12
-15
-12
-15
-12
-15

12
24
48
64
12
,24
48
64

5.6
5.6
3.5
3.5
11
11
4.5
4.5

16.3
16.3
33.8
33.8
31.8
31.8
112.5
112.5

J

54AL5243
74AL5243
54A5243
74A5243
54L5243
74L5243
545243,
745243

-12
-15
-12
-15
-15
-15
-12
-15

12
24
48
64
12
24
48
64

6
6
4
4
12
12
5
5

23.3
23.3
45.8
45.8
34.5
34.5
139.6
139.6

54A5231
74A5231
54AL5240
74AL5240
54A5240
74A5240
54L5240
74L5240
545240
745240
545940
745940
54AL51240
74AL51240

-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15

40
48
12
24
48
64
12
24
48
64
48
64
8
16

3.5
3.5
2.6
2.6
3.5
3.5
10
10
5
5
5
5
9
9

18.5
18.5
6.5
6.5
19.2
. 19.2
14.2
14.2
56.3
56.3
56.3
56.3
5.9
5.9

Octal Inverter
Buffers

Quad
Transceivers

Octal Inverter
Bus Buffers/
Drivers

1·45

Package
Avail.
Mil

Page

Com

J,W
N

J,W
N

J,W
N

J,W
N

2·184
2·184
4·348
4·348
2·184
2·184
4·348
4·348

N

2·184
2·184
4·348
4·348
2·184
2·184
4·348
4·348

N

5·60

J,W
N

J,W
N

J,W
N

J,W

N

J
N

J,W
N

' J,W
N

J
N

J
N

J,W
N

J,W
N

J
N

J
N

J
N

J,W
N

J,W
N

J,W
N

J
N

2·144
2·144
3·105
3·105
4·258
4·258
5·128
5·128
2·144
2·144
3·105
3·105
4·258
4·258
5·128
5·128
3·102
3·102
2·141
2·141
3·105
3·105
4·255
4·255
5·125
5·125
5·169
5·169
2·295
2·295

Buffer Gates with TRI·STATE Totem·Pole Outputs (Continued)

Description

Device Type

Octal Bus
Buffersl
Drivers

\

Octal
Transceivers

Max
Source
Current
(mAl

Max
Sink
Current
(mAl

Typ·
Prop.
Delay
Time
(nsl

Typ·
Power
Dlss.
IGate
(mW)

54ALS241
74ALS241
54AS241
74AS241
54LS241
74LS241
54S241
74S241
54ALS244
74ALS244
54AS244
74AS244
54LS244
74LS244
54S244
745244
54S941
74S941
54ALS1241
74ALS1241
54ALS1244
74ALS1244

-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15

12
24
48
64
12
24
48
64
12
24
48
64
12
24
48
64
48
64
12
24
12
24

4.3
4.3
4
4
10
10
5
5
4.3
4.3
4
4
10
'10
5
5
5
5
9
9
9
9

8.6
8.6
24.6
24.6
14.2
14.2
67.2
67.2
8.5
8.5
24.1
24.1
24.6
24.6
67.2
67.2
67.2
67.2
5.9
5.9
5.9
5.9

54ALS245
74ALS245
54AS245
74AS245
54LS245
74LS245
54ALS623
74ALS623
54AS623
74AS623
54ALS645
74ALS645
54AS645
74AS645
54LS645
74LS645
54ALS1243
74ALS1243
54ALS1245
74ALS1245
54ALS1623
74ALS1623
54ALS1645
74ALS1645

-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15

12
24
32
48
12
24
12
24
48
64
12
24
48
64
12
24
8
16
8
16
8
16
8
16

9
9
5.5
5.5
8
8
9
9
5
5
5
5
5.5
5.5
8
8
7
7
9
9
7.5
7.5
7.5
7.5

21.7
21.7
49.1
49_1
36.3
36.3
20
20
49.2
49.2
21.7
21.7
49.2
49.2
36
36
19
19
14
14
8.9
8.9
14.4
14.4

• Request Data Sheet

1-46

Package
Avail.
Mil

Page

Com
2·141
2-141
3-105
3-105
4-255
4-255
5-125
5:125,
2-147
2-147
3-105
3-105
4-261
4-261
5-125
5-125
5-169
5-169
2-295
2-295
2-303
2-303

J
N

J
N

J,W
N

J,W
N

J
N

J
N

J,W
N

J,W
N

J,W
N

J
N

J
N

J

2-150
2-150
3-111
3-111
4-264
4-264
2-225
2-225
3-181
3-181

N

J
N

J,W
N

J
N

J
N

J

*
*

N

J
N

J,W
N

J
J
J
J

N
N
N
N

J
N

~

3-189
3-189
4-354
4-354
2-299
2-299
2-306
2-306
2-315
2-315
2-322
2-322

."

-.
C

Buffer Gatel with TRI·STATE Totem·Pole Outputl (Continued)

Description

Max
Sink
Current
(mA)

Typ·
Prop.
Delay
Time
(nl)

Typ·
Power
Disl.
IGate
(mW)

O·

Mil

-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15

12
24
48
64
12
24
48
64
12
24
8
16
8
16

8
8
5.5
5.5
5
5
4
4
5
5
7.5
7.5
5.5
5.5

14.6
14.6
32.7
32.7
15.4
15.4
32,9
32.9
10.9
10.9
11.3
11.3
11.3
11.3

J

54AS230
74AS230
54ALS643
74ALS643
54AS643
74AS643
54ALS1643
74ALS1643

-12
-15
-12
-15
-12
-15
-12
-15

48
64
12
24
48
64
8
16

3.5
3.5
5
5
4
4
8
8

20.8
20.8
19.4
19.4
44.4
44.4
13.8
13.8

J

Octal Trans·
celvers with
Register
Storage

54AS646
74AS646
54AS652
74AS652

-12
-15
-12
-15

32

93.8
93.8
93.8
93.8

J

32
48

5
5
5
5

Octal Inverter
Transceivers
with Register
Storage

54AS648
74AS648
54AS651
74AS651

-12
-15
-12
-15

32
48
32
48

6
6
6
6

81.3
81.3
81.3
81.3

J

Octal Inverting
Transcelversl
MOS Drivers

5417 4AS2620
54/74ALS2640
54/74AS2640

-2

1

4.5

38.3

-2

1

5.5

34.6

Octal Bus
Transcelversl
MOS Driilers
with True and
Inverting
Outputs

54/74ALS2643
54/74AS2643

Octal Bus
Transceiversl
MOS Drivers

5417 4AS2623
54/74ALS2645
54/74AS2645

Octal
Transceivers
with Open
Collector Outputs

54AS621
74AS621
54AS641
74AS641

N/A
N/A
N/A
N/A

Octal Inverter
Transceivers
with Open
Collector Outputs

54AS622
74AS622
54AS642
74AS642

N/A
N/A
N/A
N/A

48
64
48
64

Octal Trans·
celvers with
True and
Inverting
Outputs

-2
-2

48

N

J
N

J

*
*

N

N

3·102
3·102

N
N

J
N

J

J
N

J
N

J
N
N

J
N

*
*

3·189
3·189
2·322
2·322
3·194
3·194
3·199
3·199

N

3·194
3·,194
3·199
3·199

J
J
J

N
N
N

3·279
2·330
3·282

J
J

N
N

2·322
3·282

J
J
J

N
N
N

3·279
2·322
3·282

N

J

1

5.5

47

48
64
48
64

13
13
11
11

52
52
42
42

J

13
13
12
12

27
27
28
28

J

N

J
N
N

J
N

3'

~

2-219
2-219
3-181
3-181

3-189
3-189
2·299
2·299
2·309
2·309
2·322
2·322

J

e.
Q.

Com

N

5.5

1-47

Page

J

1

'Request Data Sheet

51

~

Package
Avail.

54ALS620
74ALS620
54AS620
74AS620
54ALS640
74ALS640
54AS640
74AS640
54ALS1242
74ALS1242
54ALS1620
74ALS1620
54ALS1640
74ALS1640

Octal Inverter
Transceivers

,

Device Type

Max
$ourc"
Currant
,(mA)

~

n

3·181
3·181
3·189
3·189
3·181
3·181
3·189
3·189

g;
CD

2O·

=

G')

c
is:
CD

~

~

r-----------------------------------------------------------------------------,
Buffer Gatel with Open·Coliector Outputl

C!J
High·
Level
Output
Voltage

C

o

:;::

u

~

Delcrlptlon

Device Type

Jj
~

"C

.5
"i
c
o

M
Octal Trans·
celvers with
Open·Collector
Outputs

~
c

:s

LL.

Octal Inverter
Transceivers
with Open·
Collector
Outputs ,

Octal Trans·
celvers with
True and
Inverting
Open·Coliector
Outputs

54ALS621
174ALS621
54ALS641
74ALS641
54ALS1621
74ALS1621
54ALS1641
74ALS1641

Typ·
Prop.
Delay
Time
(nl)

Max
Sink
Current
(mA)

23
23
17.5·
17.5
18
18
18
18

Typ·
,Power
IGate
(mW)

12
. 24
12
24
8
16
8
16

54ALS622
74ALS622
54ALS642
74ALS642
54ALS1622
74ALS1622
54ALS1642
74ALS1642

5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5

12
24
12
24
8
16
8
16

22
22
20
20
19
19
19
19

7.8
7.8
6.6
6.6
9.7
9.7
12.5
12.5

54ALS644
74ALS644
54ALS1644
74ALS1644

5.5
5.5
5.5
5.5

12
24
8
16

19.8
19.8
23
23

12.8
12.8
13.8
13.8

,

Mil

Page

Com

J

16.9
16.9
18.1
18.1
8.4
8.4
14.4
14.4

5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5

•

Package
Avail.

0188.

N

2·222
2·222

N

*
.*

J
J

N

2·312
2·312
2·326
2·326

N

2·222
2·222

N

'. J
J
J

*
*

N

J

2·312
2·312
2·326
2·326

N

J
N

J

*
*

N

J

2·326
N

2~326

Package
Avail.

Page

Buffer Gat!ts with TRI·STATE and Open Collector Outputs
High·
Level
Output
Voltage

Max
Source
Current
(mA)

Max
Sink
Current
(mA)

Typ·
Prop.
Delay
Time
(ns)

Typ·
Power
Dlss.
IGate
(mW)
18.3
18.3
44 .

Description

Device Type

Octal
Transceivers

54ALS639
74ALS639
54AS639
74AS639
54ALS1639
74ALS1639

5.5
5.5
5.5
5.5
5.5
5.5

-12
-15
-12
-15
-12
-15

12
24
48
64
8
16

10
10
7
7
14
14

44
14.4
. 14.4

54ALS638
74ALS638
54AS638
74AS638
54ALS1638
74ALS1638

5.5
5.5
5.5
5.5
5.5
5.5

-12
-15
-12
-15
-12
-15

12
24
.48
64
8
16

10
10
5.1
5.1
13.5
13.5

12.3
12.3
28.3
28.3
14.4
14.4

M

Octal
Inverter
Transceivers

·Request Data Sheet

1·48

Mil

Com

J
N

J
N

J
N

J
N

J
N

J
N

*
*

3·186
3·186
2·318
2·318

*
*

3·186
3·186
2·318
2·318

Code Converters
Typ'
Prop.
Delay
Time
(ns)

Typ'
Power
Diss.
Total
(mW)

Package
Avail.

Description

Device Type

Mil

Com

6·Bit Binary to 6·Bit
BCD Converters

54/74185A
8899

25
31

280
350

J,W

N
N

6·253
6·381

6·Bit BCD to 6·Bit
Binary or 4·Line to
4·Line BCD 9's/BCD
10's Converters

54/74184
8898

25
31

280
350

J,W

N
N

6·253
6·381

Page

Comparators
Typ'
Prop.
Delay
Time
(ns)

Typ'
Power
Diss.
Total
(mW)

Package
Avail.

Description

Device Type

Mil

Com

4·Bit
Magnitude
Comparator

54/74LS85
54/7485
54174L85
72/8200

20
21
70
20

52
275
20
175

J,W
J,W
J,W
J,W

N
N
N
N

4·97
6·117
7·54
6·334

71/8131

20
20
21

250
250
205

J,W
J,W
J,W

N
N
N

6·326
6·329
6·332

6·Bit
Magnitude
Comparators

7118136
7118160

Page

8·Bit
Idimtity
Comparator

54/74ALS520
54174ALS521

13.5
13.5

60
60

J
J

N
N

2·188
2·188

8·Bit Identity
Comparator
with Open·
Coilector
Outputs

54/74ALS518
54174ALS519
54/74ALS522
54/74ALS689

18.2
18
19
11

55
55
45
60

J
J
J
J

N
N
N
N

2·188
2·188
2·188
2·238

10-Bit
Magnitude
Comparators

71/8130

21

240

J,W

N

6·324

12·Bit
Address
Comparator

54174ALS679
54/74ALS680

18
18

85
67

J
J

N
N

2·233
2·267

16·Bit
Address
Comparator

54174ALS677
·54174ALS678

22
18

10.5
85

J
J

N
N

2·228
2·228

,

:

1-49

Counters, Asynchronous (Ripple Clock)/Negative·Edge·rriggered
'Typ·

Description

Device Type

Count
Freq.
(MHz)

Power
Parallel
Load

Clear

Package
Avail.

Diss.

Page

Total

(

(mW)

Mil

Com

54/74S197
54/74197
54/74LS293

32
32
6
35
30
100
40
32

None
None
None
Yes
Yes
Yes
Yes
None

High
High
High
Low
Low
Low
Low
High

39
160
20
150
60
375
240
45

J,W
J,W
J,W
J,W
J,W'
J,W
J,W
J,W

N
N
N
N
N
N
N
N

Decade

54/74 LS90
54/7490A
54/74L90
54/74176
54/74LS196
54/74S196
54/74LS290

32
32
6
35
30
109
32

Set-Io-9
Set-Io-9
Set-Io-9
Yes
Yes
Yes
None

High
High
High
Low
Low
Low
High

40
160
20
150
60
375
45

J,W
J,W
J,W
J,W
J,W
J,W
J,W

N
N
N
N
N
N
N

4-104
6-124
7-60
6-233
4-242
5-119
'4-302

Divide by 12

54/74LS92
54/7492A

32
32

None
None

High
High

39
160

J,W
J,W

N
N

4-104
6-124

Dual4-Bil
Decade

54/74LS390

25

None

High

75

J,W

N

4-341

Dual4-Bil
Biliary

54/74LS393

25

None

High

75

J,W

N

4-345

4-Bil Binary

54/74LS93
54/7493A
54/74L93
54/74177
~4/74LS197

4-104
6-124
7-60
6-233
4-242
5-119 '
6-282
4-306

Counters, Synchronous/Posltlve·Edge·Triggered
Typ·'

Description

Device Type

Count
Freq_
(MHz)

4-Bil Binary

54/74ALS161
54/74AS161
54/74LS161A
54/74S161
54/74161A
54/74ALS163
54/74AS163
54/74LS163A
54/74S163
54/74163A
75/8556
93/8316
76L76

25
25
40
25
25
25
40
25
25
25
6

Power
Parallel,
Load

Clear

Sync
Sync
Sync
Sync
Sync
Sync
Sync
Sync
Sync
Sync
Syl)c
Sync
Sync

Async-L
Async-L
Async-L
Async-L
Async-L
Sync-L
·Sync-L
Sync-L
' Sync-L
Sync-L
Sync-L
Async-L
Async-L

1-50

Package
AV,ail.

Diss.

Page

Total
(mW)

Mil

Com

60
200
93
475
305
60
200
93
475
93
375
305
33

J
J
J,W
J,W
J,W
J
J
J,W
J,W
J,W
J,W
J,W
J,W

N
N
N
N
N
N
N

~
N
N
N
N
N

2-103
3-70
4-178
5-87
6-202
2-103
3-70
4-178
5-87
,6-202
6-366
6-426
7-121

~

-

Counters, Synchronous/Positlve·Edge·Triggered (Continued)

:::J

(')

Description

4·Bit Binary
Up/Down

Decade

Decade
Up/Down

I

Modulo-N
Divider

Device Type

54/74ALS169.
54/74AS169
54/74LS169A
54/74ALS191
54/74LS191
54/74191
54/74ALS193
54/74LS193
54/74193
54/74L193
75/85L63
54/74ALS160
54/74AS160
54/74LS160A
54/74S160
54/74160A
54/74ALS162
54/74AS162
54/74LS162A
54/74S162
54/74162A
93/8310
76/86L75

Count
Freq.
(MHz)
25
25
25
20
20
25
25
20
6
6
25
25
40
25
25
25
40
25
25
6

Parallel
Load

C)"
:::J

Package
Avail.

Page
Com
N
N
N
N
N
N
N
N
N
N
N

2·118
3-77
4-200
2-126
4-221
6-259
2-134
4-227
6-265
7-82
7-111

None
None
None
None
None
None
Async-H
Async-H
Async-H
Async-H
Async-H

75
230
100
60
90
325
. 60
85
325
40
40

J
J
J
J
J,W
J,W
J
J,W
J,W
J,W
J,W

Sync
Sync
Sync
Sync
Sync
Sync
Sync
Sync
Sync
Sync
Sync
Sync

Async-L
Async-L
Async-L
Async-L
Async·L
Sync-L
Sync-L
Sync-L
Sync-L
Sync-L
Async-L
Async-L

_60
200
93
475
305
60
200
93
475
305
305
33

J
J
J,W
J,W
J,W
J
J
J,W
J,W
J,W
J,W
J,W

N
N
N
N
N
N
N
N
N
N
N
N

2-103
3-70
4-178
5-87
6-202
2-103
3-70
4-178
5-87
6-202
6-411
7-121

None
None
None
None
None
None
Async·H
Async-H
Async·H
Async-H
Async-H

75
230
100
110
100
325
60
85
325
40
40

J
J
'J,W
J
J,W
J,W
J
J,W
J,W
J,W
J,W

N
N
N
N
N
N
N
N
N
N
N

2-118
3-77
4-200
2-126
4-221
6-259
2-134
4-227
6-265
7-82
7-111

None

250

J,W

N

6-346

25
20
20
20
20
25
20
6
6

Sync
Sync
Sync
Async
Async
Async
Async
Async
Async
Async
Async

75/8520

15

Sync

)

1-51

!..
S"
0.

Mil

Sync
Sync
Async
Async
Async
Async
Async
Async
Async
Async
Async

54/74ALS168
54/74AS168
54/74LS168A
54/74ALS190
54174LS190
54174190
54/74ALS192
54/74LS192
54/74192
54/74L192
75/85L60

25

Clear

Typ·
Power
Diss.
Total
(mW)

~

en
CD
CD

-o·

(')

:::J
C)

c'

0:
CD

CD
"C

·s

Data Selectors/Multiplexers

C!'

c

o

tiCD
Jj

~

"C

.E

Typ' Prop. Delay
Time (ns)

Type
01
Output

Data
Inver.
Output

54174ALS157
54174AS157
54174LS157
54174S157
54174157
54/74L157A
54174ALS257
54/74AS257
54/74LS257B
54174S257
9318322
71181L22
7118123
71181L23

Standard
Standard
Standard
Standard
Standard
Standard
TRI·STATE
TRI·STATE
TRI·STATE
TRI·STATE
Standard
Standaro
TRI·STATE
TRI·STATE

NIA
NIA
NIA
NIA
NIA
NIA
NIA
NIA
NIA
NIA
NIA
NIA
NIA
NIA

4.3
3.5
9
5
9
40
4.2
3.5
12
5
9
40
9.5
40

Quad 2 to 1
Line
(Inverting)

54174ALS158
54174AS158
54174LS158
54/74S158
54174ALS258
54174AS258
54174LS258B
54174S258

Standard
Standard
Standard
Standard
TRI·STATE·
TRI·STATE
TRI·STATE
TRI·STATE

4.2
2.5
7
4
4.2
3
12
4

Quad 2 to 1
Line with
Storage

54174LS298

Standard

Dual 4 to 1
Line

54174ALS153
54174AS153
54174LS153
54174S153
54/74153
54174ALS253
54174AS253
54174LS253 I
54174S253
54174253
9318309
54/74ALS352
54174AS352
54174LS352
54/74ALS353
54174AS353
54/74LS353

Description

Quad 2 to 1
Line

'ii
c
o

tic
~

LL.

Dual 4 to 1
Line (Inverting)

Device Type

Data
to
Out

From
Enable

Typ'
Power
Diss.
Total
(mW)

Package
Avail.

Page

Mil

Com

6
4
12
41
14
60
NIA
NIA

39
95
49
250
150
15
33
83
50
320
150
15
200
20

J
J
J,W
J,W
J,W
J,W
J
J
J,W
J,W
J,W
J,W
J,W
J,W

N
N
N
N
N
N
N
N
N
N
N
N
N
N

2·100
3·66
4·173
5·82
6·199
7·7,2
2·159
3·120
4·283
5·138
6·437
7·94
6·321
7·94

N/A
NIA
NIA
NIA
NIA
N/A
N/A
NIA

6.1
4
12
7
6
4.5
12
14

11.5
78
24
195
29.2
58.5
35
280

J
J
J,W
J,W
J
J
J,W
J,W

N
N
N
N
N
N
N
N

2·100
3·66
4·173
5·82
2·159
3·120
4·283
5·138

NIA

20

NIA

65

J,W

N

4·310

Standard
Standard
Standard
Standard
Standard
TRI·STATE
TRI·STATE
TRI·STATE
TRI·STAT!=
TRI·STATE
Standard

NIA
NIA
NIA
NIA
NIA
NIA
NIA
NIA
NIA
NIA
12

16.5
8.7
14
6
10.5
8
5
15
6
13.5
20

14.5
7.6
22
9.5
20
4.5
5.5
25
12
20
20

37.5
105
31
225
170
35
116.7
38
275
170
135

J
J
J,W
J,W
J,W
J
J
J,W
J,W
J,W
J,W

N

N
N
N
N
N
N
N
N

2·97
3·63
4·162
5·79
6·187
2·156
3·117
4·280
5·135
6·302
6·408

Standard
Standard
Standard
TRI·STATE
TRI·STATE
TRI·STATE

6
3
15
6
3
15

N/A
NIA
NIA
NIA

4.5
4.5
18
4.5
6
15

32.5
122.5
31
37.5
130
38

J
J
J,W
J
J
J,W

N
N
N
N
N
N

2·171
3·141
4·314
2·174
3·144
4·317

1·52

6.3
5.5
14
8
14
60 .

N

N

Data Selectors/Multiplexers (Continued)

Description

8 to 1 Line

16 to 1 Line

Device Type

54/74ALS151
54/74AS151
54/74LS151
54/74S151
54/74151A
54/74ALS251
54/74AS251
54174LS251
54/74S251
54/74251
93/8312
54/74150

Typ· Prop. Delay
Time (ns)
Data
to
Out

From
Enable

Typ·
Power
Dlss.
Total
(mW)

Mil

Com

9.3
2.8
11
4.5
8
9.4
2.8
17
4.5
11
9.

7.8
3.5
18
8
16
7.6
3.5
21
8
18
16

11
5
27
9
22
7
4.5
21
14
17
17

37.5
130
30
225
145
47
140
35
275
155
135

J
J
J,W
J,W
J,W
J
J
J,W
J,W
J,W
J,W

N
N
N

11

N/A

18

200

J,W

Type
of
Output

Data
Inver.
Output

Standard
Standard
Standard
Standard
Standard
TRI·STATE
TRI·STATE
TRI·STATE
TRI·STATE
TRI·STATE
Standard
Standard

Package
Avail.

Page

N
N
N

2·94
3·60
4·158
5·75
6·179
2·152
3·113
4·276
5·131
6·298
6·422

N

6·179

N
N
N
N
N

Decoders/Demultiplexers

Type
of
Output

Typ·
Select
Time
(ns)

Typ·
Enable
Time
(ns)

Typ·
Power
Diss.
Total
(mW)

Mil

Com

22
7.5
18
21
·33
33

19
6
15
16
26
18

34
300
30
250
31
250

J,W
J,W
J,W
J,W
J,W
J,W

N
N
N
N
N
N

4·152
5·68
4·168
6·194
4·168
6·194

Package
. Avail.

Page

Description .

Device Type

Dual 2 to 4
Line

54/74LS139
54/74S139
54/74LS155
54/74155
54/74LS156
54/74156

3 to 8 Line

54/74ALS138
54/74LS138
54/74S138
54/74AS138
72/8223

Totem
Totem
Totem
Totem
Totem

8.5
22
8
5.4
25

9
21
7
5.5
N/A

25
31
225
80
140

J
J,W
J,W
J
J,W

N
N
N
N
N

2·91
4·152
5·68
3·57
6·341

3 to 8 Line
Decoder with
Address
Register

54/74ALS131
54/74AS131

Totem
Totem

8.5
5.4

10
5.5

25
80

J
J

N

N

2·77
3·49

3 to 8 Line <
Decoder with
Address
Latch

54/74ALS137
54/74AS137

Totem
Totem

11
7

10
5.5

25
80

J
J

N
N

2·87
3·54

4 to 10 Line
SCDto
Decimal

54/74LS42
54/7442
54/74L42A
93/8301

Totem
Totem
Totem
Totem

17
17
67
20

N/A
N/A
N/A
N/A

35
140
15
125

J,W
J,W
J,W
J,W

N
N
N
N

4·55
6·71
7·27
6·405

4 to 16 Line

54/74LS154
54/74154
93/8311

Totem
Totem
Totem

23
19.5
19.5

19
17.5
17.5

45
170
170

J,W
J,W
J,W

N
N
N

4·165
6·190
6·418

1 of 10
Decoder

93/8301

Totem

19.5

N/A

125

J,W

N

6·405

Totem
Totem
Totem
Totem
Open·Collector
Open·Coliector .

..
1·53

Decoder/Drivers, Display

Output
Sink
Current
(mA)

Off·.
State
Output
Voltage
(V)

Typ·
Power
Dlss.
Totsl
(mW)

Package
Avail.

Blanking

Description

Device Type

Mil

Com

BCD to
7·Segment
Decoderl
Drivers

5417446A
54LS47
74LS47
5417447A
54LS48
74LS48
5417448
54LS49
74LS49
54LS247
74LS247
54LS248
74LS248
54LS249
74LS249

40
12
24
40
2
6
6.4
4
8
12
24
2
6
4
8

30
15
15
15
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5

320
35
35
320
125
125
265
40
40
35
35
125
125
40
40

Ripple
Ripple
Ripple
Ripple
Ripple
Ripple
Ripple
Direct
Direct
Ripple
Ripple
Ripple
Ripple
Direct
Direct

J,W
J,W

N

N

6·77
4·58
4·58
6·77
4·58
4·58
6·77
4·58
·4·58
4-267
4·267
4·267
4·267
4·267
4·267

BCD to
Decimal
Decoderl
Driver

5417442
54/7445
54174141
54174145

16
80
7
80

5.5
30
60
15

140
215
80 .
215

Invalid
Invalid
Invalid
Invalid

J,W
J,W
J,W
J,W

N
N
N
N

6·71
6·74
6·166
6·169

Nixie Driver

54/7441 A

7

70

105

None

J,W

N

6·68

N
N

J,W
J,W

N
N

J,W·
J,W

N

J,W
N

J,W
N

J,W

Page

Error Detection/Correction

Description

Device Type

32·Blt
Parallel

Byt.Wrlte

54174ALS632
54174ALS633
54/74ALS634
54/74ALS635

Ves
Ves
No
·No

Typ·
Clear

Preset

'MAX

(MHz)

54/7470
54/74L71
54/7472
54/74L72
75/8512
75/8544
76/8613

TRI·STATE
Open·Coliector
TRI-STATE
Open·Coliector

Page

Mil

Com

J
J
J
J

N
N
N
N

*
*
*
*

-

Fllp·Flops, Gated

Device Type

Package
Avail.

Output

Ves
Ves
Ves
Ves
Ves
No.
No

Ves
Ves
Ves
Ves
No
No
Ves

35
11
20
20
28
N/A
30

Data
Setup
Time
(ns)

Data
Hold
Time
(ns)

Typ·
Power
Dlss.
/FF(mW)

Mil

Com

20
0
20
0
15
N/A
24

0
0
0
0
0
N/A
0

65
3.8
45
3.8
110
44
73

J,W
J,W
J,W
J,W
J,W
J,W
J,W

N
N
N
N
N
N
N

, • Request Data Sheet

1·54

Package
Avail.

Page

6·95
7·36
6·98
7·39
6·343
6·356
6·373

Flip·Flops, Single and Dual J·K Edge Triggered
Typ·
Device Type

Clear

Preset

'MAX

(MHz)
54/74LS73A
54/74 LS76A
54/74LS78A
54/74LS107A
54/74ALS109

54/74AS109
54/74LS109A

54/74109
54/74ALS112
54/74AS112
54/74LS112A

54/74S112
54/74ALS113
54/74AS113
54/74LS113A

54/74S113
54/74ALS114
54/74AS114
54/74LS114A

54/74S114
90/8024

Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes

No
No
No
No
Yes
Yes
Yes
Yes
Yes

No

45
45
45
45
50
125
33
33
40
200
45
125
40
200
45
125
40
175
45
125
40

Yes
Yes

No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes'
Yes
Yes
Yes

Data
Setup
Time
(ns)

Data
Hold
Time
(ns)

Typ·
Power
Dlss.
IFF(mW)

Mil

Com

25
20
20
20
15
3
25
10
25

5
0
0
0
0
1
0
6
0

20
6
25

0
0
0

20
6
25

0
0
0

20
6
15

0
0
10

10
10
10
10
6
28.8
10
45
6
95
10
75
6
95
10
75
6
95
10 ,
75
45

J,W
J,W
J,W
J,W
J
J
J,W
J,W
J
J
J,W
J,W
J
J
J,W
J,W
J
J
J,W
J,W
J,W

N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N

Package
Avail.

Page

4-73
4-83
4-90
4-116
2-65
3-37
4-119
6-145
2-68
3-40
4-122
5-48
2-71
3-43
4-125
5-52
2-74
3-46
4-128
5-55
6-397

Flip·Flops, Dual 0 Edge Triggered with Preset and Clear
Typ·
'MAX

Device Type
54/74ALS74
54/74AS74
54/74 LS74A

54/74574
54/7474
54/74L74

(MHz)
30
125
33
110
25
6

Data
Typ·
Data
Setup' ,Hold
Power
Time
Time
Dlss.
(ns)
(ns) IFF(mW)
15
2
20
3
20
50

0
1
0
2
5
15

6
26.3
10
75
43
4

1-55

Package
Avail.
Mil

J
J
J"W

j,w

J,W
J,W

Page
Com
N
N
N
N
N
N

2-60
3-29
4-76
5-41
6-104
7-45

Fllp·Flop,Oc;:tal 0 Edge Triggered with TRI·STATE Outputa
Typ·
Device Type

'MAX

(MHz)
50
200
50
100
50,
200
50
50
200
160
50
160
160
50
160
50
160
160
160

54/74ALS374

54/74AS374
54/74LS374
54/745374'
54/74ALS534

54/74AS534
54/74ALS564
54/74ALS574

54/74AS574
54/74AS575
54/74ALS576

54/74AS576 '
54/74AS577
54/74ALS874
541'74AS874
54/74ALS876

54/74AS876
54/74AS878
54/74AS879

,

Data
Setup
Time
(na)

Data
Hold
Time
(na)

Typ·
Power
Dlaa.
IFF(mW)

10
3
20
5
10
3
15
15
3
3
15
3
3
15
2.5
15
2.5
3
3

4
3
0
2
0
2
4
4
3
3
4
3
"3
4
1
4
1
3
3

10.8
50.3
15.9
60.9
10.4
50.3
8.5
8.5
50.4
53
8.5
52.5.
50.4
10.8
62.5
10.8

Package
Avail.
Com

J
J
J,W
J,W
J
J
J
J
J
. J

N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N

J
J
J
J
J
J
J
J
J

58
62.5
59

Typ·
Clear

Presel

'MAX

(MHz).

54/7473 '
54/74L73
54/7476
54/74L78
54174107.

No
No

Yes
Yes.
No

Yes
Yes
Yes
Yes
Yes

2·180
3·150
4·332
5·158
2·195
3·157
2·202
2·209
3·164
3·167
2·212
3·170
3.174
2·259
3·236
2·263
3·240
3·244
3·248

,

Fllp·Flopa, Single and Dual, Pulae Triggered

Device Type

Page

Mil

35
11
20
11
20

Dala
Selup
Time
(na)

Data
Hold
Time
(na)

Typ·
Power
Dlas.
IFF(mW)

Mil

Com

0
0
0
0
0

0
0
0
0
()

50.0
3.8
50.0
3.8
50.0

J,W
J,W,
J,W
J,W
J,W

N
N
N
N
N

Package
,
Avail.

Page

6·101
7·42
6·110
7·51
6·142

Galea, AND with Totem,Pole Outputa

Deacrlptlon

Dual 4·lnput

Device Type

54174ALS21
54174AS21

54/74LS21
Triple 3·lnput

54174ALS11
54174AS11

54/74LS11
54/74511
5417411
54174L11
Quad 2·lnput

54/74ALS08

54/74AS08
54/74LS08
54/74508
5417408
54174L08

-

Typ·
Prop.
Delay
Tlme(na)

Typ·
Power
Dlaa.
IGale(mW)

Mil

Com

9
3.3
7.8

2.2
12.5
4.5

J
J
J,W

N
N
N

2·40
3·19
4·37

9
3.3
7.8
4.8
11
42.5

2.1
12.9
4.3
31
18
2

J
J
J,W
J,W
J,W
J,W

N
N
N
N
N
N

2·27
3·15
4·23
5·21
6·38
' 7·19

6.5
3.3
7.8
4.8
15
45

2.2
12.9
4.3
31
19
2

J
J
J,W
J,W
J,W
J,W

N
N
N
N
N
N

2·21
3·11
4·17
5·15
6·32
7·15

1·56

Package
Avail.

Page

Gates, AND with Open· Collector Outputs

Description

Device Type

Typ·
Prop.
Delay
Time(ns)

Typ·
Power
Dlss.
IGate(mW)

Mil

Com

Triple 3·lnput

54/74AL515
54/74L515
54/74515

'17
19
6

1.5
4.3
28

J
J,W
J,W

N
N
N

2·36
4·33
5·23

Quad 2·lnput

54/74AL509
54/74L509
54/74509
54/7409

17
19
6.5
18.5

2.2
4.3
31
19.4

J
J,W
J,W
J,W

N
N
N
N

2·23
4·19
5·17
6·34

Typ·
Prop.
Delay
Time(ns)

Typ·
Power
Diss.
IGate(mW)

Mil

Com

Package
Avail.

Page

Gates, AND·OR·INVERT with Totem·Pole Outputs

Description

Device Type

Package
Avail.

Page

2·Wide 4·lnput

54/74L555
54/74L55

7.5
43

2.75
1.5

J,W
J,W

N
N

4-71
7·34

Dual2·Wide
2·lnput

54/74L551
54/74551
54/7451
54/74L51

7.5
3.5
10.5
43

2.75
28
14
1.5

J,W
J,W
J,W
J,W.

N
N
N
N

4·67
5·35
6·88
7·30

4·Wide 4·2·3·2
Input

54/74564

3.5

29

J,W

N

5·37

4·Wide 2·lnput

54/7454

10.5

23

J,W

N

6·93

4·Wide 2·3·3·2
Input

54/74L554
54/74L54

11
43

4.5
1.5

J,W

N
N

4·69
7·32

JW

Gates, AND·OR·INVERT with Open· Collector Outputs

Description

4·Wide 4·2:3·2

Device Type

54/74565

Typ·
Prop.
Delay
Time(ns)

Typ·
Power
Diss.
IGate(mW)

Mil

Com

5.5

36

J,W

N

Package
Avail.

Page

5·39

Gates, Expandable

Description

Device Type

Typ·
Prop.
Delay
Tlme(ns)

Typ·
Power
Diss.
IGate(mW)

Mil

Com

Package
Avail.

Page

Dual2·Wide
AND·OR·INVERT
Gates

54/7450

10.5

14

J,W

N

6·85

4·Wide AND·OR·
INVERT Gates

54/7453

10.5

23

J,W

N

6·90

1·57

CD

:2

cS
c
o

i

fI)

~

Gates, NAND and Inverters with Open·Collector Outputs
,

Description

CO
c

o

:uc

Typ'
Power
Diss.
IGate(mW)

Mil

Com

Package
Avail.

Page

Dual 4·lnput
NAND Gates

54174AL822
54174L822,
54174822

19
10
5

1.3
2
17.5

J
J,W
J,W

N
N
N

2·42
4·39
5·27

Triple 3·lnput
NAND Gates

54174AL812
54174L812

18
21

1.3
2

J
J,W

N
N

2·29
4·25

Quad 2·lnput
NAND Gates

54174AL801
54174L801
5417401
54174L01
54i74AL803
54174L803
54174803
5417403
54174L03
9018012C

17
21
32
41
17
22
7
10
41
20

1.3
2
10
1
1.3
2
17.5
22
1
11

J
J,W
J,W
J,W
J
J,W
J,W
J,W
J,W
J,W·

N
N.
N
N
N
N
N\
N
N
N

Hex Inverters

54174AL805
54174L805
54174805
5417405
54174L05

18
21
7
22
46

1.5
2
17.5
10
1.2

J
J,W
J,W
J,W
J,W

N
N
N
N
'N

"CI

.E

Device Type

Typ'
Prop.
Delay
Tlme(ns)

&!

2·11
4·7
6·18
7·5
2·15
4·11
5·9
6·22
7·9
6·393
2·19
4·15
5·13
6·26
7·13

Gates, NAND and Inverters with Totem·Pole Outputs

Description

Device Type

Typ'
Prop.
Delay
TIme(ns)

Typ'
Power
DIss.,
IGate(mW)

Mil

Com

Package
Avail.

Page

Dual 4·lnpul
NAND Gates

54174AL820
54174A820
54174L820
54174820
5417420
54174L20
9004C

6.5
2
8
4.5
10
33
10

1.3
8.7
2
19
10
1
11

J
J
J,W
J,W
J,W
J,W
J,W

,N
N
N
N
N
N
N

2·38
3·17
4·35
5·25
6·50
7·21
6·391

Triple 3·lnput
NAND Gates

54174AL810
54174A810
54174L810
54174810
5417410
54174L 10
9003C

7
2
8
4.5
10
33
10

1.3
14 '

J
J
J,W
J,W
J,W
J,W

N
N
N
N
N
N
N

2·25
3·13
4·21
5·19
6·36
7·17
6·389

54174AL800
54174ASOO
54174L800
54174800
5417400
54174LOO
9002C

3.5
2
8
4.5
10
33
10

1.25
8
2
19
10
1
11

J
J
J,W
J,W
J,W
J,W
J,W

N
N
N
N
N
N
N

2·9
3·5
4·5
5·5
6·16
7·3
6·387

Quad 2·lnput
NAND. Gates

2
19
10
1
11

1·58

j,w

Gates, NAND and Inverters with Totem·Pole Outputs (Continued)

Description

Device Type

Typ·
Prop.
Delay
Tlme(ns)

Typ·
Power
Dlss.
IGate(mW)

Mil

Com

Package
Avail.

Page

Hex Inverters

54/74AL504
54174A504
54174LS04
54174504
54/7404
54/74L04
9016C

3.5
2
8
4.5
10
33
10

1.5
7.1
2
19
10
1
11

J
J
J,W
J,W
J,W
J,W
J,W

N
N
N
N
N
N
N

2·17
3·9
4·13
5·11
6·24
7·11
6·395

8-lnput NAND
Gates

54/74AL530
54/74A530
54/74L530
54/74530
54/7430
54/74L30

6.5
2
10
4.5
10
33

1.9
9.8
2.4
19
10
1

J
J
J,W
J,W
J,W
J,W

N
N
N
N·
N
N

2-48
3-23
4-45
5-29
6-58
7-25

13-lnput NAND
Gate

54/74AL5133
54/745133

7
6

2
19

J
J,W

N
N

2-83
5-58

Hex
Non-Inverter

54/74AS34

4.5

12

J

N

3-27

Typ·
Prop_
Delay
Time(ns)

Typ·
Power
Dlss.
IGate(mW)

115

1.8

Gates, NAND with Passive Pull-Ups

Description

Quad 2-lnput

Device Type

80L06

Package
Avail.
Mil

Page

Com
N

7-89

Gates, Exclusive NOR, OR with Open·Coliector Outputs

Description

Device Type

Typ·
Prop.
Delay
Tlme(ns)

Typ·
Power
Dlss_
IGate(mW)

Package
Avail.

Page

Mil

Com

Quad 2-lnput
EXClusive NOR
Gates

54174LS266
54/74AL5811
54174A5811

10

18
9.1

J,W
J
J

N
N
N

4-292
2-250
3-213

Quad 2-lnput
Exclusive OR
Gates

54/74L5136
541745136
54/74ALS136
54/74A5136

18
12

7.6
63

J,W
J,W
J
J

N
N
N
N

4-149
5-66
2-85
3-52

Gates, Exclusive NOR with Totem·Pole Outputs

Description

Device Type

Typ·
Prop.
Delay
Tlme(ns)

Typ·
Power
Dlss.
IGate(mW)

Mil

Com

Quad 2-lnput
Exclusive NOR
Gates

54174ALS810
54174AS810

N/A
N/A

N/A
N/A

J
J

N
N

1-59

Package
Avail.

Page

2-247
3-210

CI)

't:I

·5

Gates, NOR with Totem·Pole Outputs

CJ

c
o

n

Typ·
Prop.
Delay
Time(ns)

Typ·
Power
Dlss.
IGate(mW)

Mil

Com

54/7425

10.5

23

J,W

N

6-52

54/74ALS27
54/74AS27

5.5
2
10
8.5

2.5
12.2
4.5
22

J
J
J,W
J,W

N
N
N
N

2-44
3-21
4-43
6-56

5
2
10
5
10
33

1.9
10.1
.2.75
29
14
1.5

J
J
J,W
J,W
J,W
J,W

N
N
N
N
N
N

2-13
3-7
4-9
5-7
6-20
7-7

Description

Device Type

-

Dual 4-lnput
NOR Gate with
Strobe

a;

Triple 3-lnput
NOR Gates

CI)

~

)(
CI)

't:I
C
C

54/74LS27
54/7427

o

;:

u

c

.!

Quad 2-lnput
NOR Gates

54/74ALS02 .
54/74AS02
54/74 LS02

54/74S02
54/7402
54/74L02

Quad 2-lnput
OR Gates

Typ·
Prop.
Delay
Tlme(ns)

Typ·
Power
Dlss.
IGate(mW)

Mil

Com

2.8
14.9
5
35
24

J
J
J,W
J,W
J,W

N
N
N
N
N

2-50
3-25
4-47
5-31
6-60

7

3.75

54/74LS386

10
9
14
30
10

7.5
62.5
41
7.5
7.5

J
J
J,W
J,W
J,W
J,W'
J,W

N
N
N
N
N
N
N

2-63
3-32
4-101
5-45
6-121
7-57
4-338

54/74S135

8.5

82

J,W

N

5-63

Package
Avall_

Page

Device Type

54/74ALS32
54/74AS32
54/74LS32

5.5
3.5 .
10
5
12

54/74S32
54/7432
Quad 2-lnput
Exclusive
OR Gates

54/74ALS86
54/74AS86
54/74LS86

54/74S86
54/7486
54/74L86
Quad Exclusive
OR/NOR Gates

Page

I

Gates, OR with Totem·Pole Outputs

Description

Package
Avail.

Package
Avail.

..

Page

Latches

Description

Device Type

Addressable
Latches

54/74LS259

DG (Clocked)
Latches

54/74LS75

54/74259
93/8334
54/7475
54/74L75A
54/74LS77

Outputs

Typ·
Prop.
Delay
Time
(ns)

Typ
Power
Diss.
Total
(mW)

Mil

Com

Low
Low
Low

Q
Q
Q

17
21
21

110
150
280

J,W
J,W
J,W

N
N
N

4-289
6-306
6-440

4
4
4
4

None
None
None
None

Q,Q
Q,a
Q,a
Q

11
15
52
10

32
160
17.5
35

J,W
J,W
J,W
J,W

N
N
N
N

4-80
6-107
7-48
4-87

No.
of
Bits

Clear

8
8
8

§,R Latches

54/74LS279

4

None

Q

12

19

J,W

N

4-295

TRI-STATE
Countersl
Latches

75/85L52
75/85L54

4
4

High
High

Q
Q

95
95

38
38

J,W
J,W

N
N

7-104
7-104

Dual4-Bit
Latches

54/74ALS880
54/74AS880

4
4

None
None

Q
a

9
6

88.3
391.5

J
J

N
N

2-271
3-252

1-60

Latches (Continued)

Outputs

Typ·
Prop.
Delay
Time
(ns)

Typ
Power
Dlss.
Total
(mW)

Mil

Low

Q

12

50

J

N

2·163

8
8
8
8
8
8
8

None
None
None
None
None
None
Low

Q
Q
Q
Q
Q
Q
Q

10
6
12
9
4.5
4.3

70
300
120
525
68.3
293
218

J
J
J,W
J,W
J
J
J

N
N
N
N
N
N

N

2·177
3·147
4·332
. 5·158
2·206
3·161
3·227

8
8
8
8
8
8

None
None
None
None
None
Low

Q
Q
Q
Q
Q
Q

10
5
13
9
4.5
4.8

75.8
328
68.3
68.3
330
222

J

J
J
J
J
J

N
N
N
N
N
N

2·192
3·154
2·199
2·216
3·178
3·227

10
4.5

68.3
330

J
J
J

N
N
N

2·255
3·232

4.3

251

J

N

3·222

Device Type

No.
of
Bits

Clear

Octal Latch

54/74ALS273

8

TRI·STATE
Octal
Latches

54/74ALS373

. Description

54/74AS373
54/74LS373
54/74S373
54/74ALS573

54/74AS573
54/74AS845
TRI·STATE
Inverting
Octal
Latches

54/74ALS533

54/74AS533
54/74ALS563
54/74ALS580

54/74AS580
54/74AS846

17

Package
Avail.

Page

Com

Oual4·Bit
TRI·STATE
Latches

. 54/74ALS873

54/74AS873

4
4

Low
Low

Q
Q

9·Bit Bus
Interface
Latches
with TRI·
STATE
Outputs

54/74AS843

9

Low

Q

9·Blt
Inverting
Bus Interface
Latches
with TRI·
STATE
Outputs

54/74AS844

9

Low

Q

4.8

242

J

N

3·222

10·Bit Bus
Interface
Latches
with TRI·
STATE
Outputs

54/74AS841

10

Low

Q

4.3

250

J

N

3·218

10·Bit
Inverting
Bus Interface
Latches
withTRI·
STATE
Outputs

54/74AS842

10

Low

Q

4.3

260

J

N

3-218

.. -

o

o

o

o

1·61

Line Drivers
Low·
Level
Output
Current
(mA)

High.
Level
Output
Current
(mA)

Typ·
Prop.
Delay
Time
(ns)

Typ·
Power
Dlss.
IGate
(mW)

Package
Avail.

Description

Device Type

Mil

Com

Dual 4-lnput
NAND

54/74S140

60

-40

4

43.B

J

N

5-73

Hex 2-lnput
NAND

54ALSB04
) 74ALSB04
54ASB04A
74ASB04A

12
24
40
4B

-1
-2.6
-40
-4B

2.7
2.7
2
2

3.3
3.3
7.7
7.7

J
J
J
J

N
N
N
N

2-241
2-241
3-204
3-204

Hex 2-lnput
NOR

54ALSB05
74ALSB05
54ASB05A
74AS805A

12
24
40
4B

-12
-15
-40
-4B

3
3
1.6
1.6

4.1
4.1
9.6
9.6

J
J
J
J

N
N
N
N

2-243
2-243
3-206
3-206

Hex 2-lnput
AND

54ALSBOB
74ALSBOB
54ASB08A
74ASB08A

12
24
40
48

-12
-15
-40
-4B

4,3
4.3
3
3

4.6
4.6
10.6
10.6

J
J
J
J

N
N
N
N

2-245
2-245
3-20B
3-20B

Hex 2-lnput
OR

54ALSB32
74ALSB32
54ASB32A
74ASB32A

12
24
40
48

-12
-15
-40
-4B

4
4
2.50
2.50

5.6
5.6
12.9
12.9

J
J
J
J

N
N
N
N

2-253
2-253
3-216
3-216

I

Page

Multipliers
Package
Avail.

Device
Type

Description

4-Blt by 4-Blt Parallel
Binary Multipliers

7B/8875A
7B/BB75B

Page

Mil

Com

J,W
J,W

N
N

6-376
6-376

One Shots, Re~rlggerable

,

No. of
Inputs

Clear

Output
PulseRange (ns)

Typ·
Total
Power
Diss.
(mW)

. Dlr_

Package
Avail.

Description

Device Type

POS

Neg

Mil

Com

Single

54174LS122
96/8601

2
2

2
2

Yes
Yes

45 ns-Inf.
50 ns-inf.

30
90

J,W
J,W

N
N

4-131
6-444

Dual

54/74LS123
54174123
96/8602

1
1
1

1
1
1

Yes
Yes
Yes

90 ns-inf.
45 ns-inf.
72 ns-Inf.

60
230
195

J,W
J,W
J,W

N
N
N

4-135
6-152
6-44B

1-62

Page

r--------------------------------------------------------------------------,~

C
:::I

One Shots with Schmltt·Trlgger Inputs

Description

Device Type

2.

No. of
Inputs

Dlr.
Clear

Output
Pulse
Range(ns)

,Typ·
Total
Power
Dlss.
(mW)

cr
:::I

!!.

Package
Avail.
Page
Mil

Com

Single

54/74121

1

2

Yes

40ns·28 s

90

J,W

N

6·148

Dual

54LS221
74LS221

1
1

1
1

Yes

20ns,·49 s
20ns·49 s

65
23

J,W

N
N

4·250
4·250

Pos

Neg

S"
c.
~

~

-o·
CD

n

:::I

C)

Parity Generators/Checkers

Description

Device Type

C

a:
CD

Typ·
Prop.
Delay
Tlme(ns)

Typ·
Power
Diss.
Total(mW)

Mil

Com

Package
Avail.

Page

8·Bit Odd/Even
Parity
Generators/
Checkers

54/74180

35

170

J,W

N

6·242

9·Bit Odd/Even
Parity
Generators/
Checkers

54174S280
72/8220
54/74AS280

13
34
7.3

335
130
135

J,W
J,W
J

N
N
N

5·143
6·337
3·129

9·Bit Parity
Generator
Checker with
Bus Driver
Parity
I/O Port

54174AS286 ,-

9.3

160

J

N

3·136

Device Type

Typ·
Prop.
Delay
Tlme(ns)

Typ·
Power
Dlss.
Total(mW)

54/74148
93/8318

12
12

190
190

J,W·
J,W

N
N

6·172
6·433

54/74147

10

225

J,W

N

6·172

Priority Encoders

Description

Cascadable
'Octal Priority
Encoders
Full BCD
Priority
Encoders

1·63

Package
Avail.
Mil

Page
Com

Reg.lster Fllas
Typ·
Address
Time
(ns)

Typ·
Read
Enable
Time
(ns)

Data
Input
Rate
(MHz)

Typ·
Power
Diss.
Total
(mW)

Mil

Com

15
15

20
20

125
635

J,W
J,W

N
N

4·208
6·220

19
19

20
30

135
400

J,W
J,W

N
N

4·357
6·352

Deacrlptlon

Device Type

4 Words of
4 Bits

54/74LS170
74170

27
30

4 Words of,
4 Bits with
TRI·STATE
Outputs

54/74LS670
75/8542

24
24

Package
Avail.

Page

Registers, Other

Description

Device Type

Typ·
Clock
Freq.'
(MHz)

Asyn.
Clear

Typ·
Power
Dlss.
Total (mW)

Mil

Com

J,W
J,W
J,W

N
N
N

' 7·100
4·212
6·224

Package
Avail.

Page

Quad Bus
Buffer
Registers

75/85L51
54/74173

.311.._, .-_. f- - Higtl

28
85
250

Quad O·Type
Registers

54/74ALS175

54/74AS175
54/74LS175
54/745175
54/74175

60
160
40
90
40

Low
Low
Low
Low
Low'

47.5
395
55
300
150

J
J
J,W,
J,W
J,W

N
N
N
N
N

2·123
3·82
4·216
5·96
6·228

Quad,
Multiplexers
with Storage

54/74LS298
54/74L98

30
15'

None
None

65
30

J,W
J,W

N
N

4·310
7·69

Hex O·Type
'Registers

54/74A LS174
54/74AS174
54/74LS174
54/745174
54/74174

60
160
40
90,
40

Low
Low
Low
Low
Low

50
395
80
450
225

J
J
J,W
J;W
J,W

N
N
N
N
N

2·123
3·82
4·216
,5·96
6·228

8·Bit
Universal
Shlft/Storage
Registers

54ALS299
74ALS299

30
40
60
22

Low
Low
Low
None

100
100
700
400

J
J
J,W
J,W

N
N
N
N

2·166
2·166
5·152
6·359

50
200
50
100
50
200
40
,160
160
50
160
160
50
160
50,
160
160
160

None
None
None
None
None
None
None
None
None
None
None
None
Low
Low
None
None
Low
Low

86
402
128
487
83
328
68
403
383
68
420
420
87
500
87
500
500
500

J
J
J
J,W
J

N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N

2·180
3·150
4·332
5·158
2·195
3·157
2·209
3·164
3:167
2·212
3·170
3·174
2·259
3·236
2·263
3·240
3·244
3·248

.octal O·Type
Registers

54/74LS173A

54/745299
75/8546
54/74ALS374

54/74AS374
54/74LS374
54/745374
54/74ALS534

54/74AS534
54/74ALS574

54/74AS574
54/74AS575
54/74ALS576

54/74AS576
54/74AS577
54/74ALS874

54/74AS874
54/74ALS876

54/74AS876
54/74AS878
54/74AS879

15
40

High
High~

1·64

J
J
J
J
J
J
J
J
J
J
J
J
J

."
C
::::J

-

Registers, Other (Continued)

Description

n

Typ·
Clock
Freq.
(MHz)

Device Type

Typ'
Power
Diss.
Total (mW)

Asyn.
Clear

Package
Avail.

Page

Mil

Com

8·Bit Dual
Rank Shift
Register

54/74LS952
54/74LS962

36
36

None
None

305
305

J.W
J.W

N
N

4·361
4·367

Successive
Approximation
Registers

2502C
2503C
2504C

21
21
21

None
None
None

325
300
450

J.W
J.W
J,W

N

N
N

6·5
6·5
6·5

0"
::::J
2!.
S"
c.
~

en
C1I

CD

-

n

0"
::::J

G')

C

c::C1I
Registers, Shift

Description Device Type

No.
of
Bits

Typ'
Shift
Freq.
(MHz)

Ser.
Data
Input

Asyn.
Clear
S·R

S·L

Load

Hold

D·
D
D
D
D

Low
Low
Low
Low
Low

x
x
x
x
x

x
x
x
x
x

x
x
x
x
x

x
x

D
D
D
D

x

x
x
x

x

39
35
39

J.i(
J.i(
J.i(
J.j(
J.i(
J-K

None
None
None
None
Low
Low
Low
Low
Low
Low

Modes

Typ'
Power
Dlss.
Total
(mW)

Mil

Com

75
450
195
133
360

J,W
J,W
J,W
J
J,W

N
N
N
N
N

4·234
5·112
6-274
3-97
6-289

195
24
130
240
70
375
195
360
356

J,W
J,W
J
J,W
J,W
J,W
J
J,W
J,W
J,W

N
N
N
N
N
N
N
N
N
N

6-133
7-(l6
3-34
6-137
4-238
5-116
3-100
6-278
6-289
6-401

30
125
200
30
80
110
360
80

J,W
J,W
J,W
J,W
J
J,W
J,W
J

N
N
N
N
N
N
N

7-125
4-192
6-212
7-78
2-110
4-196
6-216
2-214

Package
Avail.

Page

Parallel·ln
Parallel·
Out (Bidir·
ectional)

54174LS194A
54/74S194
54/74194
54/74AS194
54/74198

4
4
4
4
8

Parallel·ln
Parallel·
Out

5417495
54/74L95
54174AS95
54/7496
54/74LS195A
54/745195
54/74AS195
54/74195
54174199
93/8300

4
4
4
5
4
4
4
4
8
4

76/86L90
54174LS165
54/74165
54/74L165A
54/74ALS165
54/74LS166
54/74166
54/74ALS166

8
8
8
8
8
8
8
8

14
30
20
14
60
35
35
60

D
D
D
D
D
D
D
D

None
None
None
None
None
Low
Low
Low

54174LS164

8

36

Low

x

80

J,W

N

4-189

54174164

8

36

Low

x

175

J,W

N

6-208

54/74L164A

8

14

Low

x

30

J,W

N

7·75

76/86L70

8

14

Gated
D
Gated
D
Gated
D
Gated

Low

x

30

J,W

N

7-118

Parallel·ln
Serial·Out

Serial·ln
ParallelOut

25

90
36·
35
36
14
15
39
90

x
x
x
x

x
x
x·
x

x
x
x
x

x
x

1-65

x
x
x
x
x
x
x

x

x
x
x

x

x

x

x
x
x
x

x
x

x

x

x
x

x

x

x

x

x
x

x

x

D

x

x
x

x

N

Schmitt·Trlggers with Totem·Pole Outputs

Description

Device Type

Typ"
Prop.
Delay
Time (ns)

Typical"
Hysteresis
(V)

Package
Avail.

Page

Mil

Com

Dual 4·lnpul
NAND Schmitt
Triggers

54174LS13
54/7413
54174ALS13

15
16.5

0.8
0.8
0.8

J,W
·J,W
J

N
N
N

4·27
6·40
2·31

Quad 2·lnpul
NAND Schmitt
Triggers

54/74LS132
54/74132
54/74ALS132

15
15

0.8
0.8
0.8

J,W
J,W
J

N
'N
N

4·146
6·164
2·80

Hex Schmitt
Trigger
Inverlers

54/74LS14
54/7414
54/74ALS14

15
15

0.8
0.8 '
0.8

J,W
J,W
J

N
N
N

4·30
6·43
2·33

.

1·66

DM54/74, 5451745 Test Waveforms
Parameter Measurement Information
Load Circuit for
ai-State
Totem-Pole Outputs

;~,~~

FROM OUTPUT
UNDER TEST

H

CL
(5•• Nole A)

Load Circuit for
Open-Collector Outputs

f

Load Circuit for
TRI-STATE Outputs

VCC

VCCRL

L

FROM OUTPUT
UNOER TEST

(See Nol. 8)

J -: -

I

TEST
POINT

(5
CL•• Nol. A)

Nole A. CL Includes probe and jig capacitance.
Note 8. All dIodes are 1N91S or 1N3064.

•

Input Waveform
3V

54/74 tr ~ 7 ns, tf S 7 ns
54S/74S tr S 2.5 ns, tf S 2.5 ns

OV

Generator: Zout = 50 !l
PRR S 1 MHz

Voltage Waveforms
Setup and Hold Times

Voltage Waveforms
Pulse Widths

HIGH'LEVEL~V
'SV
I 1.
.
I

3V

TIMING
INPUT

/.,

-----'4~~-------ov

PULSE

I

DATA~:
-t----1.5 v
1.5 V

I

~'W---.j

~tsetup....r--thOld--+f

~~--y

3Y

LOW-LE'!'EL
PULSE

INPUT

1 5 II
.

15V
•

OV

Voltage Waveforms
Propagation Delay TImes

Vo.ltage Waveforms
Enable and Disable Times, TRI-STATE Outputs

INPUT~1.SV
--~:------3V
I

.

I
I
l.-IPLH --l
I

I....PHASE
OUTPUT

I

ov

I
I

J

I

1.5 II

I

I

1.5 II

I

,
r

(See Not. C)

.~I
IVOH
1.5 Y

- - - - - VOL

52 OPEN

i---'PZH--!

t- tPLH --l

1.5 V

~~ ~ ~~ ~ ~ ~ ~ ~ ~ ~~. ov
-1~~--~~~~~-~ -~.

r-'PLZ-I

WAVEFORM 1 ---+'--S-'-C-LO-S-EO-"'-t - - - - "'" 4.5 Y

VOL

I

I

'---------

:_tPZL~

-.L---VOH

t

I

r- tPHL ~
OUT·Of·PHASE
OUTPUT
(See Nole E)

ENABLING)

r- tPHL----4

~
:

~3V

OUTPUT
~
CONTROl,.
(LOW-LEVEL
I 1.5 II

I

WAVEFORM2~1OPEN
11.SY
82 CLOSED

I
I

S'AND
S2CLOSED

i
y---,t.. ~ '.SV
---+j-......j.---,.---.v
OL

~tPHZ~

0.5 y O.5Y

------,L-l-----VOH

_ _ _ _ _ _ .",OV

(See Not. C)

I
I

,.51 AND
S2CLOSED

~

,.SV
.

Nota C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the oulput control. Waveform 2 is for an output With
internal conditions such thai the output is high except when disabled by the oulput control.
Note D. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily.
Note E. When measuring propagation delay times of TRI·STATEoutputs, switches 51 and S2 are closed.

1-67

DM54L/74L, 54LS/74LS Test Waveforms
Parameter Measurement Information
Load Circuit for
Bi-State
Totem-Pole Outputs

Load Circuit for
Open-Collector Outputs

TRI-STATE Outputs

TEST
POINT

H

:~VCCRL

FROM OUTPUT
UNDER TEST

CL

I":'":'

tRsLI

L

FROM OUTPUT
UNDER TEST

(s;,;;';t; 8)1

(See Note A)

-f:

vCC

VCC

I

+........(S.e Note B)

FROM OUTPUT _ ....._ _....
UNDER TEST
~

TEST
,POINT

Ski! ..

I

CI*

Ir

"::" CL
(See Note A)

(5•• Note CII

-J.-

Nota A. Cl includes probe and jig capacitance.

Note B. AU diodes are lN916 or lN3064.
Note C. C1 (30 pF) is used for testing Series 54Lf74l devices only.

Input Waveform
3V

ov

90%
10%

,

,I

I
I

I

,

I

I

, 10%

I

I

54LSI74LS: tr :;:; 6 ns, tf :;:; 6 ns
54L174L gates and inverters: tr :;:; 60 ns, tf :;:; 60 ns
54L174L flip-flops and MSI: tr :;:; 25 ns, tf :;:; 25 ns

~If

r--I- Ir

Generator:
, Zout ~ 50 Q
PRR:;:; 1 MHz

Voltage Waveforms
Setup and Hold Times
~

nMING

4~3~

INPUT _ _ _ _...

_______

Voltage Waveforms
Pulse Widths
3V

HlGH-LEVEL~
PULSE
I 1.3 V
1.3 V I

,

,

OV

1-.....p..I-..... """'1

I+--IW--l

3V
DATA~:
-t---1.3 V
1.3 V

~'W-y

LOW-LEVEL
PULSE

INPUT

13 V
•

, 3V
•

OV

Voltage Waveforms
Propagation Delay Times

Voltage Waveforms
Enable and Disable Times, TRI-STATEOutputs

~
1.3V
13V
I
I
.

---------3V

INPUT

I

I.

r

i
I

r

I

,

3V

I
,-'PHL -I

(See

Note F)

:

11.3V

I

,
t-'PLH

.:

OUT·OF-PHASE
OUTPUT

~VOH

::E:OC:~11

:::

~~.-- ~

~~:ED

- - - - - VOl.

!-'PLZ-I
'"=

'I 1.3 V

5' OPEN

~

(SH Note DI _ _ _ _..:5;:;2..:C;;;LOSE=D;;.....S JaMOd MOl pa:>UBAp"

c

i:

~National

a

U1

~

Semiconductor

ro
o

(J)

-

DM54ALSOOA/DM74ALSOOA Quad 2-lnput NAND Gates

»
c

General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic NAND function.

Supply Voltage
Input Voltage:
Operating Free Air Temperature Range
DM54ALS
DM74ALS
Storage Temperature Range

Features
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.

•

Advanced OXide-Isolated. Ion-Implanted Schottky TTL
Process.

•

Functionally and Pin For Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.

•

Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.

Connection Diagram

48

4A

4Y

1Y

2A

38

3A

3Y

Y=AB

28

2Y

74ALSOOA (J,N)

2·9

Output

A

B

Y

L
L
H
H

L
H
L
H

H
H
H
L

H = High Logic Level
L = low Logic Level

GND

TL/F/6270·1

54ALSOOA (J)

(J)

o
o

»

fII
Inputs

18

-55°C to 125°C
O°C to 70°C
-65°C to 150°C

»r-

Function Table

8

1A

7V
7V

3:
~

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual·ln·Line 'Package
Vee

(Note 1)

Recommended Operating Conditions
DM54ALSOOA
Parameter
Supply Voltage, VCC
High Level Input Voltage, VIH

....

DM74ALSOOA

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

Unit
V
V

2

Low Level Input Voltage, VIL

1,0.8

0.8

V

High Level Output Current, 10H

-0.4

-0.4

mA

Low Level Output Current, 10L

4

8

mA

Max

Unit

-1.5

V

Electrical Characteristics over recommended operating free air temperat'ure range.
All typical values are measured at Vee = 5V, TA = 25°C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage>

VCC = 4.5V, II = -18 mA

VOH

High Level Output
Voltage

10H = -0.4mA
VCC = 4.5 to 5.5V

VOL

Low Level Output
Voltage

VCC = 4.5V

Min

Typ

V

VCC-2

54/74ALS
10L = 4 mA

0.25

0.4

V

74ALS
10L = 8 mA

0.35

0.5

V

II

Max High Input Current

VCC = 5.5V, VIH = 7V

0.1

mA

IIH

High Level Input Current

VCC = 5.5V, VIH = 2.7V

20

/lA

IlL

Low Level Input Current

VCC = 5.5V, VIL = 0.4V

-0.1

mA

10

Output Drive Current

VCC = 5.5V

Vo = 2.25V

-112

mA

ICC

Supply Current

VCC = 5.5V

Outputs High

0.43

0.85

mA

Outputs Low

1.62

3.0

mA

-30

SWitching Characteristics over recommended operating free air temperature range (Note .1).
All typical values are measured at Vee = 5V, TA = 25°C.
DM54ALSOO
Parameter

Conditions

TpLH, Propagation
delay time. Low to
high level output

VCC = 4.5 to 5.5V
RL = 50012,
CL = 50 pF.

TPHL, Propagation
delay time. High to
low level output

DM74ALSOO
Typ

Max

Unit

Max

Min

3

14

3

11

ns

2

10

2

8

ns

Min

Note 1: See Section 1 for test waveforms and output load.

2·10

Typ

~National

~ Semiconductor
DM54LS01/DM74LS01 Quad i-Input NAND Gates
with Open-Collector Outputs
.
General Description

Features

This device contains four independent gates each of
which performs the logic NAND function. The opencollector outputs require external pull-up resistors for
proper logical operation_

•
•

Pull·Up Resistor Equations
R

MAX =

Vee (Min) - VOH
N1 (IOH) + N2 ,(IIH)

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
• Advanced OXide-Isolated, lon-Implanted Schottky TTL
Process.
• Functionally and Pin For Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.
• Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.

Absolute Maximum Ratings

Where:

N1 (loH) = total maximum output high current
for all outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for
all inputs tied to pull-up resistor
N3 (lid total maximum input low current for
all inputs tied to pull-up resistor

=

Supply Voltage
Input Voltage
Off State (High Level)
Output Voltage
Operating Free Air Temperature Range
DM54ALS
DM74ALS
Storage Temperature Range

(Note 1)
7V
7V
7V

-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beypnd
which the safety of the device can not be guaranteed. The device should
not be operated at these limits, The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual-In-Line Package
Vee

4Y

48

4A

3Y

38

3A

Y=AB
Inputs

Output

A

B

Y

L
L
H
H

L
H
L
H

H
H
H
L

H ; High Logic Level

1Y

1A

18

2Y

2A

28

L = Low Logic Level

GND

TL/F/6174-1

54ALS01 (J)

74ALS01 (J,N)

2-11

/

~
,...

Recommended Operating Conditions
DM54ALS01

==
:IE

Parameter

' I""

Supply Voltage, VCC

c

~
..J

DM74ALS01

Min

Nom

Max

Min

Noni

Max

4.5

5

5.5

4.5

5

5.5

V
V

2

2

High Level Input Voltage, VIH

Unit

~

Low Level Input Voltage, VIL

0.8

0.8

V

c

High Level Output Voltage, VOH

5.5

5.5

V

Low Level Output Current, IOL

4

8

mA

:IE

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee
Symbol

=5V, TA =25°C.

Parameter

Conditions

VIK

Input Clamp Voltage

VCC

=

IOH

High Level Output
Current

VCC
VOH

= 4.5V
= 5.5V

VOL

Low Level Output
Voltage

VCC

=

=

4.5V, II

Min

=

Typ

-18 mA

4.5V

Max

Unit

-1.5

V

100

pA

54/74ALS
IOL = 4mA

0.25

0.4

·V

74ALS
IOL = 8mA

0.35

0.5

V

0.1

mA

II

Max High Input Current

VCC

IIH

High Level Input Current

VCC = 5.5V, VIH :... 2.7V

20

/LA

IlL

Low Level Input Current

VCC = 5.5V, VIL = 0.4V

-0.1

mA

ICC

Supply Current

VCC

=

5.5V, VIH = 7V

5.5V

Outputs High

0.43

0.85

mA

Outputs Low

1.62

3.0

mA

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V, TA

=25°C.
DM54ALS01

Parameter

Conditions

TPLH, Propagation
delay time. Low to
high level output

VCC = 4.5 to 5.5V
RL = 2KD,
CL = 50 pF.

TpHL, Propagation
delay time. High to
low level output

Min

Typ

DM74ALS01

Typ

Unit

Max

Min

23

59

23

54

ns

4

29

4

28

ns

Note 1: See Section 1 for test waveforms and output load.

2-12

Max

~National

D Semiconductor
DM54ALS02/DM74ALS02 Quad 2-lnput NOR Gates
General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic NOR function.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS
DM74ALS
Storage Temperature Range

Features
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and Vcc'Range.

•

Advanced Oxide-Isolated, lon-Implanted Schottky TIL
Process.
• Functionally and Pin For Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart,
,. Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.

Connection Diagram

7V
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the

"Electrical Characteristics" table are not guaranteed at the absolute
'maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Dual·ln·Llne Package
Vee

Y4

Y3

84

B3

A3

Y=A+B

8

Inputs

=

7

Y1

A1

Y2

A2

B2

74ALS02 (J,N)

2·13

Output

A

B

Y

L
L
H
H

L
H
L
H

H
L
L
L

H High Logic Level
L = Low Logic Level

GND

TL/F/6175·1

54ALS02 (J)

(Note 1)

•

~

r

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,0

Switching Specifications at 50 pF,
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
• Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
• Functionally and Pin For Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.
• Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.

Absolute Maximum Ratings

RMIN= Vee (Max) - VOL
IOL - N3 (IIU

c

Supply Voltage
Input Voltage
Off State (High Level)
Output Voltage
Operating Free Air Temperature Range
DM54ALS
DM74ALS
Storage Temperature Range

(Note 1)

7V
7V
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Connection Diagram
Dual-In-Line Package
Vee

84

A4

Y4

83

A3

Y=AB

Inputs

A

B

L
L
H
H

L
H
L
H

'H = High Logic Level

7
A1

81

Y1

A2

B2

Y2

L;;: Low Logic Level

GND

TLIFI6176-1

54ALS03A (J)

74ALS03A (J,N)

2-15

Output
i

Y
H
H
H
L

~

'~.---------------------------------------------------------------~

~

.....
~

Recommended Operating Conditions
DM54ALSQ3A

~

Parameter

c

Supply Voltage. VCC

DM74ALS03A

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5,5

Unit

:::IE

~

~:::IE
c

High Level Input Voltage. V,H

2

V
V

2

Low Level Input Voltage. V,L

0,8

0.8

Vi

High Level Output Voltage. VOH

5,5

5.5

V

Low Level Output Current. IOL

4

8

mA

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA=2S D C.
Symbol

Parameter

Conditions

Min

Typ

Max

Unit
V

V,K

Input Clamp Voltage

VCC = 4.5V,I' = -18 mA

-1.5

IOH

High Level Output
Current

VCC = 4.5V, VOH = 5.5V

100

p.A·

VOL

Low Level Output
Voltage

VCC = 4.5V

54/74ALS
IOL=4mA

0.25

0.4

V

74ALS
IOL=8mA

0.35

0.5

V

Max High Input Current

VCC = 5.5V, V,H = 7V

0.1

mA

"
IIH

High Level Input Current

VCC = 5.5V. V,H = 2.7V

20

p.A

IlL

Low Level Input Current

VCC = 5.5V. V,L = 0.4V

-0.1

mA

ICC

Supply Current

VCC = S.5V

Outputs High

0.43

0.85

mA

Outputs Low

1.62

3.0

mA

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V, TA = 25 DC.
DMS4ALS03A
Parameter
TpLH. Propagation
delay time. Low to
high level output

Conditions
Vce = 4.5 to 5.5V
RL = 2K n,
CL = SOpF.

TpHL, Propagation
delay time. High to
low level output

Min

DM74ALS03A
Min

23

59

23

54

ns

5

26

5

22

ns

2·16

Typ

Unit

Max

Note 1: See Section 1 for lesl waveforms and outpul load.

Typ

Max

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Semiconductor

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-

DM54ALS04A/DM74ALS04A Hex Inverters
General Description

Absolute Maximum Ratings

This device contains six independent gates each of
which performs the logic INVERT function.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS
DM74ALS
Storage Temperature Range

Features
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
.
• Advanced Oxide-Isolated, lon-Implanted .Schottky TTL
Process.
• Functionally and Pin For Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.
• Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.
_

Connection Diagram

vee

,,6

Y6

13

AS
11

12

Function Table

1
A1

ri>o2

Y1

A4

3
A2

Y4

Y=A

8

9

4>0-

{>o-

ri>o-

Y5
10

-£>0-

ri>o-

4
Y2

5
A3

6
Y3

Input

Output

A

Y

L
H

H
L

H = High Logic Level

17

L;:: Low Logic Level

GND

TLlF/6177-1

54ALS04A (J)

7V
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual-ln·Line Package

. -1~4

c
3:

(Note 1)

74ALS04A (J,N)

2-17

~
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Recommended Operating Conditions
'DM74ALS04A

DM54:ALS04A
Parameter
Supply Voltage, VCC
High Level Input Voltage, VII-i

Min

Nom

4.5

5

Max

Min

Nom

Max

5.5

4.5

5

5.5

2

V
V

2

Low Level Input Voltage, VIL

Unit

0.8

0.8'

V

High Level Output Current, 10H

-0.4

-0.4

mA

Low Level Output Current, 10L

4.

8

mA

Max

Unit

-1.5

V

. Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25·C.
Symbol

Parameter

Conditions

=

Min

=

VIK

Input Clamp Voltage

VCC

VOH

High Level Output
Voltage

10H = -0.4mA
VCC =4.5 to 5.5V

VOL

Low Level Output
Voltage

VCC

=

4.5V, II

Typ

-18 mA

V

VCC-2

4.5V

54/74ALS
10L = 4mA

0.25

0.4

V

74ALS
10L = 8mA

0.35

0.5

V

0.1

mA

II

Max High Input Current

VCC

=

5.5V, VIH = 7V

IIH

High Level Input Current

VCC

=

5.5V, VIH

=

2.7V

20

,.A

IlL

Low Level Input Current

VCC

=

5.5V, VIL

=

O.4V

-0.1

mA

10

Output Drive Current

VCC

=

5.5V

Vo

-112

mA

ICC

Supply Current

VCC

=

5.5V

Outputs High

0.65

1.1

mA

Outputs Low

2.4

4.2

mA

=

-30

2.25V

SWitching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee

=5V, TA =25·C.
DM74ALS04A

DM54ALS04A
Parameter
TpLH, Propagation
delay time. Low to
'high level output

Conditions
(VCC = 4.5 to 5.5V
RL = 500 n, .
CL = 50 pF.

TpHL, Propagation
delay time. High to
low level output

Min

Max

Unit

Max

Min

3

14

3

11

ns

2

12

2

8

ns

Note 1: See Section 1 for test waveforms and output toad.

2·18

Typ

Typ

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~Nat1onal

E
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~ Semiconductor

r-

DM54ALS05A1DM74ALS05A Hex Inverters
with Open Collector Outputs
General Description

Features

This device contains six independent gates each of
which performs the logic INVERT function. The opencollector outputs require external pull-up resistors for
proper logical operation.

•
•

P411·Up Resistor Equations

•
•

s::

~
l>

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range;
Advanced OXide-Isolated. Ion-Implanted Schottky TTL
Process.
Functionally and Pin For Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.

R

Vcc (Min) - VOH
Nt (IOH) + N2 (IIH)

•

R

Vcc(Max)-VOL
IOL - N3(IIIJ

Absolute Maximum Ratings

MAX =

MIN=

Nt (IOH) = total maximum output high current
for all outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for
all inputs tied to pull-up resistor

Where:

=

N3 (111.1 total maximum input low current for
all inputs tied to pull-up resistor

Supply Voltage
Input Voltage
Off State (High Level)
Output Voltage
Operating Free Air Temperature Range
DM54ALS
DM74ALS
Storage Temperature Range

.~efine

the

conditlon~

for actual device operation.

Function Table

Dual-ln·Line Package
vee

V6

A6

114

13

12

V5

A5

11

10

V4

A4

9

Y=A

8

Input

Output

A
L
H

2

1
AI

VI

3
A2

4
V2

5
A3

6
V3

H

17

TL/F/6178-1

54ALS05A (J)

=High Logic Level

L = Low Logic Level

GND

74ALS05A (J,N)

2-19

~

Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.
(Note 1)
7V
7V
7V

-55°C to 125°C
DoC to 70°C
-65°C to 150°C

Nola 1: The "Absolute Maximum Aatings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions"table will

Connection Diagram

~

H

L

!II

~

r-

CJ)

o

00

-55°C to 125°C
DoC to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the devic~ can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Diagram

(Note 1)

Recommended Operating Conditions
DM74ALS08

DM54ALS08
Parameter
Supply Voltage. VCC
High Level Input Voltage. VIH

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

Unit
V
V

2
0.8

0.8

V

High Level Output Current. 10H

-0.4

-0.4

mA

Low Level Oiltput Current. 10L

4

8

mAo

Max

Unit

-1.5

V

Low Level Input Voltage. VIL

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V. TA = 25°C.
Symbol

) Parameter

VIK

Input Clamp Voltage

VCC = 4.5V. II = -18 mA

VOH

High Level Output
Voltage

10H = -O.4mA
VCC = 4.5 to 5.5V

VOL

Low Level Output
Voltage

VCC = 4.5V

Conditions

Min

Typ

V

VCC- 2
c

54/74ALS
10L = 4mA

0.25

0.4

V

74ALS
10L = 8mA

0.35

0.5

V

0.1

mA

20

/LA

-0.1

mA

-112

mA

II

Max High Input Current

VCC = 5.5V:VIH = 7V

IIH

High Level Input Current

VCC = 5.5V. VIH = 2.7V

IlL

Low Level Input Current

VCC = 5.5V. VIL = O.4V

10

Output Drive Current

VCC = 5.5V

Vo

ICC

Supply Current

VCC = 5.5V

Outputs High

1.3

2.4

mA

Outputs Low

2.2

4

mA

i

-30

= 2.25V

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee=5V. TA=25°e.

, Parameter

DM54ALS08
Conditions

Min

Typ

DM74ALS08
Max

Min

Typ

Max

Unit

TpLH. Propagation
delay time. Low to
high level output

Vce = 4.5 to 5.5V
RL = 500 n.
CL = 50 pF.

4

16

4

14

ns

TpHL. Propagation
delax time. High to
low level output

,

3

12

3

10

ns

Note 1: See Section 1 for lesl wavelorms and oulpulload.

2·22

r---------------------------------------------------------------'c

s:

~National

~

~ Semiconductor

Ii)

-

DM54ALS09/DM74ALS09 Quad 2-lnput AND Gates
with open Collector Outputs

i
c
s:
:ii!
~

General Description

Features

fg

This device contains four independent gates each of
which performs the logic AND function. The opencollector outputs require external pull-up resistors for
proper logical operation.

•
•

Pull·Up Resistor Equations

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
• Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
• Functionally and Pin For Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.
• Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.

Absolute Maximum Ratings

RMIN= Vee (Max) - VOL
10L - N3 (IIU

Where:

r-

N1 (I OH) = total maximum output high current
for all outputs tied to pull-up resistor
N2 (lIH) = total maximum input high current for
all inputs tied to pull-up resistor
N3 (lIU = total maximum input low current for
all inputs tied to pull-up resistor

Connection Diagram

'Supply Voltage
Input Voltage
Off State (High Level)
Output Voltage
Operating Free Air Temperature Range
DM54ALS
.
DM74ALS
Storage Temperature Range

V4

7V
-55°C to 125°C
O°C to 70°C
-65°C~0 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric valUes defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

B3

A3

V3

Y=AB

8

Inputs

Al

Bl

VI

A2

B2

V2

74ALS09 (J,N)

2-23

Output

A

B

Y

L
L
H
H

L
H
L
H

L
L
L
H

H= High Logic Level
L= Low Logic Level

GND

TL/F/6179·1
54ALS09 (J)

(Note 1)
7V
7V

Dual-In-Line Package
A4

co

II

Recommended Operating Conditions
DM74ALS09

DM54ALS09
Parameter

-

Supply Voltage, VCC

High Level Input Voltage, VIH

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

Unit
V
V

2

Low Level Input Voltage, VIL

0.8

O.S·

V

High Level Output Voltage, VOH

5.5

5.5

V

Low Level Output Current, IOL

4

8

mA

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25°C.
Symbol

Max

Unit

VIK

Input Clamp Voltage

Parameter

VCC = 4.5V, II = -18 mA

Conditions

Min

Typ

-1.5

V

IOH

High Level Output
Current

VCC = 4.5V, VOH = 5.5V

100

I'A

VOL

Low Level Output
Voltage

VCC = 4.5V

54/74ALS
IOL = 4 mA

0.25

0.4

V

74ALS
IOL'= 8 rnA

0.35

0.5

V

II

Max High Input Current

VCC = 5.5V, VIH = 7V

0.1

rnA

IIH

High Level Input Current

VCC = 5.5V, VIH = 2.7V '

20

I'A

IlL

Low Level Input Current

VCC = 5.5V, VIL = O.4V

-0.1

'mA

ICC

Supply Current

VCC = 5.5V

Outputs High

1.3

2.4

mA

Outputs Low

2.2

4

rnA

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee =5V, TA=25°C.
DM54ALS09
Parameter
TpLH, Propagation
delay time. Low to
high level output

Conditions
VCC'= 4.5 to 5.5V
RL = 2Kn,
CL = 50 pF.

TpHL, Propagation
delay time. High to
low level output

Min

Typ

DM74ALS09
Max

Min

Typ

23

59

23

54

5

17

5

15

Max

Unit

ns

.'

Note 1: See Section 1 for test waveforms and output load.

2·24

ns

c

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DM54ALS10A/DM74ALS10A Triple 3-lnput NAND Gates

:r>
c

General Description

Absolute Maximum Ratings

This device contains three independent gates each of
which performs the logic NAND function.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS
DM74ALS
Storage Temperature Range

Features
•
•

Switching !3pecifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.

•

Advanced OXide-Isolated, lon-Implanted Schottky TTL
Process.

•

Func'tionally and Pin For Pin Compatible with Schottky
and Low Power Schottky TIL Counterpart.

•

Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.

Connection Diagram

Function Table

Y1

C1

2
B1

Y=ABC

3
A2

C2

Y2

B

C

Y

X
X
L

X
L
X

L
X
X

H
H
H

H

H

H

L

L = Low Logic Level

GND

X = Either low or High Logic Level

TLlF/6180·1

54ALS10A (J)

Output

A

H; High Logic Level

B2

~

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...I.

-55°C to 125°C
O°C to 70°C
-65°C to 150°C

o

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fII

Inputs

A1

7V
7V

Note 1: Th~ "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions tor actual device operation.

Dual·ln·Une Package
Vcc

(Note 1)

74ALS10A (J,N)

2·25

~
,.. Recommended Operating Conditions
~

Parameter

c

Supply Voltage, VCC

:e

~
,..

cHigh Level Input Voltage, VIH

~

Low Level Input Voltage, VIL

~
1.1)

:e
c

DM74ALS10A

DM54ALS10A



General Description

Features

This device contains three independent gates each of
which performs the logic NAND function. The opencollector outputs require external pull-up resistors for
proper logical operation.

•
•

Pull·Up Resistor Equations

~
.....

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
• Advanced Oxide-Isolated. Ion-Implanted Schottky TIL
Process.
• Functionally and Pin For Pin Compatible with Schottky
and Low Power Schottky TIL Counterpart.
• Improved AC Performance Over Schottky and Low
Power Schottky Counterparts ..

Absolute Maximum Ratings (Note 1)
I

Where:

N, (IOH) = total ·maximum outpuf high current
for all outputs tied to pull-up resistor
N2 (IIH) total maximum input high current for
all inputs tied to pull-up resistor
N3 (111) = total maximum input low current for
all inputs tied to pull-up resistor

=

Connection Diagram

Supply Voltage
Input Voltage
Off State (High Level)
Output Voltage
Operating Free Air Temperature Range
DM54ALS
DM74ALS
Storage Temperature Range

7V
7V
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for aclual device operation.

Function Table

Dual-In-Llne Package
Vcc

C1

Y1

C3

B3

A3

Inputs

A1

B1

A2

B2

C2

Y2

B

C

y

X
X

X

L

L

L
H

X

X
X

H

.H

H
H
H
L

H = High Logic Level

GND

=
=

L Low Logic Level
X Either Low or High Logic Level

TLIFI61S2·1

54ALS12A (J)

Output

A

74ALS12A (J,N)

2-29

~

·Recommended Operating Conditions
DM74ALS12A

DM54ALS12A
Parameter
Supply Voltage, VCC
High Level Input Voltage, VIH

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2
0.8

High Level Output Voltage, VOH

..

5.5

Low Level Output Current, IOL

V
V

2

Low Level Input Voltage, VIL

Unit

0.8

V

5.5

V

,)

4

8

mA

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vcc=5V, TA = 25°C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.5V;11

IOH

High Level Output
Current

VCC = 4.5V, VOH = 5.5V

VOL

Low Level Output .
Voltage

VCC

=

Typ

Min

= ·-18mA

4.5V

Max

Unit

-1.5

V

100

,.A

54/74ALS.
IOL = 4 mA

0.25

0.4

V

74ALS
IOL = 8mA

0.35

0.5

V

II

Max High Input Current

VCC = 5.5V, VIH

= 7V

0.1

mA

IIH

High Level Input Current

VCC = 5.5V, VIH

= 2.7V

20

,.A

IlL

Low Level Input Current

VCC

= 5.5V, VIL =

-0.1

mA

VCC

=

ICC

5.5V

O.4V
Outputs High

0.32

0.6

mA

Outputs Low

1.2

2.2

mA

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at ':oIcc = 5V, TA = 25°C.
DM74ALS12A

IDM54ALS12A
Parameter

Conditions

TPLH, Propagation
delay time. Low to
high level output

VCC = 4.5 to 5.5V
RL = 500n,
,
CL = 50 pF.

TPHL, Propagation
delay time. High to
low level output
Notet: See Section 1 for test waveforms and output load.

Min

Typ

23

5

'.

Typ

Unit

Max

Min

59

23

54

ns

22

5

18

ns

""ax

.---------------------------------------------------------------'0
s::
PRELIMINARY en
~ National
.

:=r-

~ Semiconductor

...

CJ)

DM54ALS13/DM74ALS13 Dual4-lnput NAND Gates with
Schmitt Trigger Inputs
General Description

Absolute Maximum Ratings (Note 1)

This device contains two independent gates, each of
which performs the logic NAND function. Each input has
hysteresis which increases the noise immunity and transforms a slowly changing input signal to a fast changing,
jitter·free output.

Supply Voltage
Input Voltage
Storage Temperature

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full
temperature and Vee range
• Advanced oxide·isolated, ion-implanted Schottky TTL
process
• Functionally and pin-for-pin compatible with Schottky
and low power Schottky TTL counterparts

7V
7V
-65'Cto +150'C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

• Improved AC performance over Schottky and low
power Schottky counterparts

Connection Diagram

Function Table

Dual-ln·Line Package

V
f4

D2

13

C2

12

NI~

11

B2

"

T9

h
,
AI

B1

DM54ALS13 (J)

V=ABCD

"

•
Inputs

Output

A

B

C

D

v

x

X

L

l

L

X
X
L
X

H

H

X
X
X
H

H
H
H
H
L

X
X

X

X
H

H = High Logic Level
L= Low Logic Level
X = Either Low or High Logic Level

4

C1

DM74ALS13 (N)

This document contains Information on a product under devel'opment. NSC reserves the right to change or discontinue this product without notice.

2-31

~

o

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~

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...
Co)

Recommended Operating Conditions
Symbol

DM74ALS13

DM54ALS13

Parameter
\

Min

Typ

Max

Min

Typ

Max

5

5

Units

Vee

Supply Voltage

4.5

5.5

4.5

5.5

V

VT+

Positive·Going Input
Threshold Voltage (Note 1)

1.4

2

1.4

2,

V

VT_

Negative-Going Input
Threshold Voltage (Note 1)

0.7

1.2

0.8

1.2

V

Hys

Input Hysteresis (Note 1)

0.5

10H

High Level Output Current

10l

Low Level Output Current

·TA

Free Air Operating
Temperature

0.5

V

-0.4

-0.4
8

mA

70

·C

4
-55

125

0

mA

Electrical Characteristics over recommended operating free air temperature (un'less otherwise noted)
Symbol

Parameter

Conditions

Min

Typ
(Note 2)

Units

Max
-1.5

V

VI

Input Clamp Voltage

Vee=Min, 11= -18mA

VOH

High Level Output
Voltage

Vee = Min
10H=Max.
VI=VT-Min

DM54

Vee- 2

3.4

V

DM74

Vee- 2

3.4

V

Low Level Output
Voltage

Vee=Min
10l=Max
VI=VT+Max

DM54

0.25

0.4

V

DM74

0.35

0.5

V

IT+

Input Current at
Positive-Going
Threshold

Vee=5V, VI=VT+

IT_

Input Current at
Negative-Going
Threshold

Vee=5V, VI=VT_

II

Input Current at Max
Input Voltage

Vee = Max, VI=7V

0.1

rnA

IIH

High Level Input
Current

Vee = Max, VI=2.7V

20

p.A

III

Low Level Input
Current

Vee = Max, VI = O.4V

-0.1

rnA

10

Output Drive
Current

Vee=Max, Vo =2.25V

-112

rnA

leeH

Supply Current with
Outputs High

Vee=Max

4

rnA

I eel

Supply Current with
Outputs Low

Vee = Max

4

rnA

VOL

0.03

rnA

0.034

rnA

.

-30

SWitching Characteristics over recommended operating free air temperature range
DM54ALS13
Symbol

Parameter

Conditions

\

tplH
tpHl

Min

Propagation Delay Time, Vee = 4.5V to 5.5V,
Low to High Level Output Rl =2k!l,
Propagation Delay Time, C l =50pF

High to Low Level Output
Nole 1: vee = 5V.
Nole 2: All typlcals are at Vee=5V, TA=25·e.

Typ
(Note 2)
8

DM74ALS13
Max

Min

Typ
(Note 2)

Units
.Max

8

ns

13

ns

.'

13

,

2-32

.
~ Semiconductor
~National

PRELIMINARY

c
s::

~r

...

CJ)

-s::
-1:10

C

DM54ALS14/DM74ALS14 Hex Inverters with
Schmitt Trigger Inputs

;
r

...

CJ)

-1:10

Absolute Maximum Ratings (N~te 1)

General Description
This device contains six independent gates, each of which
performs the logic INVERT function. Each input has
hysteresis which increases the noise immunity and transforms a slowly changing input signal to a fast changing,
jitter-free output.

Features

Supply Voltage
Input Voltage
Storage Temperature

7V
7V

-65'Cto +150'C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute

• SWitching specifications at 50 pF
• Switching specifications guaranteed over full
temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process'
• Functionally and pin-for-pin compatible with Schottky
and low power Schottky TTL counterparts

maximum ratings. The "Recommended Operating Conditions" table will
detrne the conditions for actual device operation.

• Improved AC performance over Schottky and low
p~wer Schottky counterparts

Connection Diagram

Function Table

Dual:ln-Line Package

Input

A

Output
y

L

H

H

L

H = high logic level

L = low logic level

VI

'2

V2

.J

VJ

TLlF16183-1

DM54ALS14 (J)

DM74ALS14 (N)

This document contains information on a produc:t under development. NSC reserves the right to change or discontinue this product without notice.,

2-33

Recommended Operating C.onditions
DM54ALS14

Parameter

Symbol

DM74ALS14

Min

Typ

Max

Min

Typ

Max

5

5

Units

Vee

S\Jpply Voltage

4.5

5.5

4.5

5.5

V

VT+

Positive·Going Input
Threshold Voltage (Note 1)

1.4

2

1.4

2

V

VT _

Negative-Going Input
Threshold Voltage (Note·1)

0.7

1.2

0.8

1.2

V

Hys

Input Hysteresis (Note 1)

0.5

IOH

High Level Output Current

IOl

Low Level Output Current

TA

Free Air Operating
Temperature

0.5

V

-0.4

-0.4

4
-55

125

0

mA

8

mA

70

·C

Electrical Characteristics over recommended operating free.air temperature' (unless otherwise noted)
Symbol

Parameter

Conditions

Min

Typ
(Note 2)

Max

Units

VI

input Clamp
Voltage

Vee = Min, II = -18 mA

VOH

High Levei Output
Voltage

Vee = Min
ioH=Max
Vll=Max

Low Level Output
Voltage

Vee = Min
10l= Max
VIH=Min.

IT+

Input Current at
Positive-Going
Threshold

Vee=5V, VI=VT+

0.03.

mA

IT_

'Input Current at
Negative-Going
Threshold

Vee = 5V, VI =VT_

0.034

mA

II

Input Curreni at Max
Input Voitage

Vee = Max, VI =7V

0.1'

mA

i lH

High Level Input
Current

Vee = Max, VI=2.7V

20

/LA

ill

Low Level Input
Current

Vee.= Max, VI =0.4V

-0.4

mA

-112

mA

VOL

DM54
DM74

-1.5

V

Vee- 2 .

3.4

V'

Vee- 2

3.4

V

DM54

0.25

0.4

V

DM74

0.35

0.5

V

\

10

Output Drive
Current

Vee = Max, Vo = 2.25V

leeH

Supply Current with
Outputs High

Vee=Max

12

mA

leel

Supply Current with
Outputs Low

Vee= Max

12

mA

Notal: Vee = 5V.
Note 2:. All typicals are at Vee = 5V. TA = 25·e.

2-34

-30

Switching Characteristics over recommended operating free air temperature range
DM54ALS14
Symbol

Parameter

Conditions
Min

Propagation Delay Time, Vee = 4.5V to 5.5V,
Low to High Level Output R L =2k!l,
Propagation Delay Time, C L = 50 pF

tpLH
tpHL

Typ
(Note 3)

DM74ALS14
Max

Typ
(Note 3)

Min

8

8

ns

8

8

ns

High to Low Level Output
Note 3: All typicals are at

Vce =5V, TA = 25°e.

-

j

.

,.

2-35

Units
Max

.
~ Semiconductor
~National

DM54ALS15/DM74ALS15 Triple 3-lnput AND Gates
with Open Collector Outputs .
I

General Description

Features

This device contains three independent gates each of
which performs the logic AND function. The opencollector outputs require external pull-up resistors for
proper logical operation.

•
•
•
•

Pull·Up Resistor Equations
•

.

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
Advanced Oxlde-Isoiated, lon-Implanted Schottky TTL
Process.
.
Functionally and Pin For Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.
Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.

Absolute Maximum Ratings
RMIN= VcclMax)-VOL
10L - N3 (Ill)

Where:

N1 (IOH) = total maximum output high current
for all outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for
all inputs tied to pull-up resistor
N3 (Ill) = total maximum input low current for
all inputs tied to pull-up resistor

Connection Diagram

Supply Voltage
Input Voltage
Off State (High Level)
Output Voltage
Operating Free Air Temperature Range
DM54ALS
DM74ALS
Storage Tempe~ature Range

7V
7V
7V
-55°C to 125°C
O°C to 70°C
-65°C te;> 150·C .

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table
Y=ABC

vCC
114

Dual-In-Line Package
C1
V1
C3
83
A3
13
11
10
112
19

1
A1

2
81

3
A2

V3

4
82

5

C2

~
Is

17

V2

A

B

C

Y

X
X

X

L

L

L
H

X

X
X

H

H

L
L
L
H

H = High Logic Level
L = Low logic Level
X = Either Low or High Logic Level

"

GND

TLiF/6183-1
54ALS15 (J)

Output

Inputs

8

~

bJ

(Note 1)

74ALS15 (J,N)

2-36

,--------------------------------------------------------------------,0
:s:

Recommended Operating Conditions
DM74ALS15

DM54ALS15
Parameter
Supply. Voltage. Vce
High Level Input Voltage. V,H

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

Unit
V
V

2

Low Level Input Voltage. V,L

0.8

0.8

V

High Level Output Voltage. VOH

5.5

5.5

V

Low Level Output Current. IOL

4

8

mA

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vcc = 5V. TA = 25°C.
Symbol

Parameter

Conditions

Typ

Max

Unit

V,K

Input Clamp Voltage

VCC = 4.5V. " = -18 mA

-1.5

V

IOH

High Level Output
Current

VCC = 4.5V. VOH = 5.5V

100

p.A

VOL

Low Level Output
Voltage

VCC = 4.5V

Min

54/74ALS
IOL = 4 mA

0.25

0.4

V

74ALS
IOL = 8 mA

0.35

0.5

V

Max High Input Current

VCC = 5.5V. V,H = 7V

0.1

mA

"
IIH

High Level Input Current

VCC = 5.5V. V,H = 2.7V

20

p.A

IlL

Low Level Input Current

VCC = 5.5V. V,L = O.4V

-0.1

mA

ICC

. Supply Current

VCC = 5.5V

Outputs High

1.0

1.8

mA

Outputs Low

1.66

3.0

mA

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vec = 5V. TA = 25°C.
DM74ALS15

DM54ALS15
Parameter
TPLH. Propagation
delay time. Low to
high level output

Conditions
VCC = 4.5 to 5.5V
RL = 2K n.
CL = 50 pF.

TPHL. Propagation
delay time. High to
low level output

Typ

Typ

Min

20

50

20

45

ns

6

23

6

20

ns

Note 1: See Section 1 for test waveforms and output load.

2·37

Max

Unit

Max

Min

~

-.~
UI

o

:s:
~

:r>
I"'"

en

UI

~National

D Semiconductor
DM54ALS20A/DM74ALS20A Dual ~·Input NAND Gates
General Description

Absolute Maximum Ratings

This device contains two independent gates each of
which performs the logic NAND function.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS
DM74ALS
Storage Temperature Range

Features
• Switching Specifications at 50 pF.
• Switching Specifications Guaranteed Over f'ull
Temperature and VCC Range.
• Advanced Oxide-Isolated. Ion-Implanted Schottky TTL
Process.
• Functionally and Pin For Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.
• Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.
.

Connection Diagram

(Note 1j
7V
7V

-55°C to 125°C
O~C to 70°C
-65°C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not,be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Dual·ln·Llne Package
VCC
114

02
13

.

1
A1

2
B1

C2
12

NC
111

B2
10

A2

e
Inputs

h
13
NC

4
C1

5
01

Y=ABCD

Y2

19

.

~
yI16

D

Y

X
X
X

X
X

X

L

L

l
X

X
X

X
X
X

H

H

H

H
H
H
H
L

H = High Logic Level
L= Low Logic Level
X = Either Low or High Logic Level

74ALS20A (J, N)

2-38
':,;,,;,.

C

17

GNO

\

.. ;

B

L
H

TL/F/6184·1

54ALS20A (J)

Output

A

-----------------------------------------------------------------------.0
:s:
Recommended Operating Conditions
C11

Supply Voltage, VCC
High Level Input Voltage, VIH

Min

Nom

4.5

5

~

DM74ALS20A

DM54ALS20A
Parameter

Max

Min

Nom

Max

5.5 .

4.5

5

5.5

2

Unit
V
V

2
0.8

V

High Level Output Current, 10H

-0.4

'-0.4

mA

Low Level Output Current"IOL

4

8

mA

Low Level Input Voltage, VIL

0.8

l>

r-

en
N
o

-:s:o
l>

~

l>

r-

en
N

o

l>

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25'C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC

VOH

High Level Output
Voltage

10H ~ -O.4mA
VCC = 4.5 to 5.5V

VOL

Low Level Output
Voltage

VCC

~

~

4.5V, II

Min
~

Max

Unit

-1.5

V

Typ

-18 mA

V

VCC-2

4.5V

54/74ALS
10L ~ 4 mA

0.25

0.4

V

74ALS
10L ~ 8 mA

0.35

0.5

V

II

Max High Input Current·

VCC

~

5.5V, VIH

~

7V

0.1

mA

IIH

High Leverlnput Current

VCC

~

5.5V, VIH

~

2.7V

20

/lA

IlL

Low Level Input Current

VCC

~

5.5V, VIL

~

O.4V

-0.1

mA

10

Output Drive Current

VCC = 5.5V

Vo

-112

mA

VCC = 5.5V

Outputs High

0.22

0.4

mA

Outputs Low

0.81

1.5

mA

ICC

-30

= 2.25V

Switching Characteristics over recommended operating free air temperature range (Note 1).
=5V, TA =25'C.

All typical values are measured at Vee

DM54ALS20A
Parameter

Conditions

TpLH, Propagation
delay time. Low to
high level output

VCC ~ 4.5 to 5.5V
RL ~ 500 n,
CL ~ 50 pF.

TpHL, Propagation
delay time. High to
low level output
~ote1:

Min

Typ

Min

3

13

3

11

ns

3

12

3

10

ns

2-39

Max

Unit

Max

See Section 1 for test waveforms and output load.

Typ

DM74ALS20A

~.----------------------------------------------------------------------------------,

~ ~National
~ a Semiconductor

:!l

~ DM54ALS21/DM74ALS21 DuaI4-li1put AND Gates

~
-I

~
:!l
c

General Description

Absolute Maximum Ratings (Note 1)

This device contains two independent gates each of
which performs the logic AND function.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS
DM74ALS
Storage Temperature Range

Features
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and Vec Range.
• Advanced OXide-Isolated, lon-Implanted Schottky TTL
Process.
• Functionally and Pin For Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.
•

7V
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C.

Note 1: The ·"Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will

define the conditions for actusl device operation.

Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.

Connection Diagram

Function Table

Dual·ln·Line Package
02

C2

13

12

B2

NC

111

10

A2

Y2

19

Y=ABCD

8

Inputs
B

C

D

Y

X

X
L
X
X

L

X
L

X
X
L
X

L
L
L
L

H

H

H

X

2

Al

81

4

13
NC

54ALS21 (Jr

Cl

5
01

16
Yl

17

Output

A

X
X
X
H

H ':' High LogiC Level
L = Low Logic Level
X= Either L?w or High Logic Level

GNO
TL/F/6185·1

74ALS21 (J,N)

2-40

H

Recommended Operating Conditions
DM54ALS21
Parameter

Supply Voltage
High Level Input Voltage. VIH

DM74ALS21

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

2

Unit

V
V

0.8

0.8

V

High Level Output Current. 10H

-0.4

-0.4

mA

Low Level Output Current. 10L

4

8

mA

Max

Unit

-1.5

V

Low Level Input Voltage. VIL

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V. TA = 25·C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.5V.11

VOH

High Level Output
Voltage

10H = -O.4mA
Vee 4.5 to 5.5V

VOL

Low Level Output
Voltage

VCC = 4.5V

Min

=

V

VCC-2

=

=

Typ

-18 mA

54/74ALS
10L = 4mA

0.25

0.4

V

74ALS
10L = 8mA

0.35

0.5

V

0.1

mA

20

p.A

-0.1

mA

-112

mA

II

Max High Input Current

VCC

IIH

High Level Input Current

VCC = 5.5V. VIH

IlL

Low Level Input Current

VCC = 5.5V. VIL = O.4V

10

Output Drive Current

VCC

=

5.5V

Vo = 2.25V

ICC

Supply Current

VCC

=

5.5V

Outputs High

0.67

1.2

mA

Outputs Low

1.10

2

mA

5.5V. VIH = 7V

=

2.7V

-30

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V. TA = 25·C.

.

I

Parameter

Conditions

TpLH. Propagation
delay time. Low to
high level output

VCC = 4.5 to 5.5V
RL = 50011.
CL = 50 pF.

TpHL. Propagation
delay time. High to
low level output

DM74ALS21

DM54ALS21
Min

Typ

Typ

Max

Unit

Max

Min

6

30

6

26

ns

3

12

3

10

ns

,

Nole 1: See Seclion 1 for lesl waveforms and oulpul load.

2-41

~National

~ Semiconductor
I

DM54ALS22B/DM74ALS22B Dual 4-lnput NAND Gates
with Open Collector Outputs
General Description

Features

This device contains two independent gates each of
which performs the logic NAND function. The opencollector outputs require external pull-up resistors for
proper logical operation.

•
•
•
•

Functionally and Pin For Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.

•

Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.

Pull·Up Resistor Equations
Vcc (Min) - VOH
R
MAX =
N, (IOH) + N2 (IIH)

Absolute Maximum Ratings

VcclMax)-VOL
R
MIN=
10L - N3 (11Ll

Where:

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.

N, (IOH) = total maximum output high current
for all outputs tied to pull-up resistor
N2 (lIH) total maximum input high current for
all inputs tied to pull-up resistor
N3 (11Ll = total maximum input low current for
all inputs iied to pull-up resistor

=

(Note 1)

Supply Voltage
7V
7V
Input Voltage
Off State (High Level)
·7V
Output Voltage
Operating Free Air Temperature Range
-55°C to 125°C
DM54ALS
DM74ALS
O°C to 70°C
-65°C to 150°C
Storage Temperature Range
Nol8 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table arB not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual-In-Llne Package

1

D2

C
14

13

C2
12

NC
111

82
A2
10
19

h

,
(

1
A1

Y=ABCD

Y2
8

2
81

13
NC

4

C1

5

D1

Inputs

~.
1&
Y1

C

D

Y

X
X
X

X
X

X

L

L

L

X

X
X

X
X
X

H

H

H

H
H
H
H
L

H =High Logic Level
L =Low Logic Level
X =Eilher Low or High Logic Level

TLiF/6186-1

54ALS22B (J)

B

L
H

17
GND

Output

A

74ALS22B (J,N)

2-42

r-------~-----------------------------------------------------------,c

s::

Recommended Operating Conditions
DM54ALS22B
Parameter
Supply Voltage
High Level Input Voltage, VIH

DM74ALS22B

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

0.8

V

:I>

5.5

5.5

V

4

8

mA

0.8

.

Low Level Output Current, IO.L

.

V

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vce =5V, TA = 25°C.
Max

Unit

VIK

Input Clamp Voltage

VCC = 4.5V, II = -18 mA

-1.5

V

IOH

High Level Output
Current

VCC = 4.5V, VOH = 5.5V

100

p.A

. VOL

Low Level Output
Voltage

VCC = 4.5V

Symbol

Parameter

Conditions

Min

Typ

54/74ALS
IOL = 4mA

0.25

0.4

V

74ALS
IOL=8mA

0.35

0.5

V

II

Max High Input Current

VCC = 5.5V. VIH = 7V

0.1

mA

IIH

High Level Input Current

VCC = 5.SV. VIH = 2.7V

20

p.A

IlL

Low Level Input Current

VCC·= 5.SV. VIL = O.4V

-0.1

mA

ICC

Supply Current

VCC = 5.5V

Outputs High

0.22

0.4

mA

Outputs Low

0.80

1.5

mA

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V. TA = 25°C.
DM54ALS22B
Parameter

Conditions

Min

Typ

DM74ALS22B
Max

Min

Typ

Max

Unit

TpLH. Propagation
delay time. Low to
high level output

VCC = 4.5 to 5.5V
RL = 2K n.
CL = 50 pF.

TpHL. Propagation
delay time. High to
low level output
Note 1: See

Se~tion

23

~O

23

45

ris

4

21

4

18

ns

1 for test waveforms and output load.

2·43

~

V

2

High Level Output Voltage, VOH

~

-

2

Low Level Input Voltage, VIL

Unit

CD
C

s::
~

~

CD

~r-----------------------------------------------------------------------,

~ ~National
~

::it

a

Semiconductor

e DM54ALS27 /DM7 4ALS27 Triple 3-lnput NOR Gates

~

~
::it
c

General Description .

Absolute Maximum Ratings

This device contains three independent gates each of
which performs the logic NOR function.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS
. DM74ALS
Storage Temperature Range

Features
• ~witching Specifications at 50 pF.
• Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
• Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
• Functionally and Pin For Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.
• Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.

Connection Diagram

Y1

C1

define the conditions for actual device operation.

FUnction Table ,

C3
12

83

A3

11

Y3

y = A+B+C

8

Inputs

2
A1

81

345
A2

54ALS27 (J)

82

C2

7V
7V
-55°C to 125°C
ODC to 70 DC
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those value. beyond
which the safety of the device can nol be guaranteed. The device should
not be operated at these limits. The paramelric values defined In Ihe
"Electrical Characteristics" table are not guaranteed al the absolute
maximum ratings. The "Recommended Operating Conditions" table will

Dual-In-Llne Package

Vce

(Note 1)

Output

A

B

C

Y

H
X
X

X
H
X

X
X
H

L
L
L

L

L

L

H

H = High Logic Level
L Low Logic Level
X = Either Low or High Logic Level

=

Y2
GND
TL/F/6187-1

74ALS27 (J,N)

2-44

Recommended Operating Conditions
DM74ALS27

DM54ALS27
Parameter
Supply Voltage
High Level Input Voltage, VIH

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

Unit
V
V

2
0.8

0.8

V

High Level Output Current, IOH

-0.4

-0.4

mA

Low Level Output Current, IOL

4

8

mA

Max

Unit

-1.5

V

Low Level Input Voltage, VIL

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vce = 5V, TA = 25°C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.5V, II = -18 mA

High Level Output

IOH = -0.4mA
Vee = 4.5 to 5.5V

VOH

Vol~age

VOL

Low Level Output
Voltage

Min

Typ

V

VCC-2

Vec = 4.5V

54/7lIALS
IOL = 4mA

0.25

0.4

V

74ALS
IOL=8mA,

0.35

0.5

V

II

Max High Input Current

Vec = 5.5V, VIH = 7V

0.1

mA

IIH

High Level Input Current

VCC = 5.5V, VIH = 2.7V

20

p.A

IlL

Low Level Input Current

VCC ,= 5.5V, VIL = 0.4V

-0.1

mA

10

Output Drive Current

VCC = 5.5V

Vo = 2.25V

-112

mA

ICC

Supply Current

VCC = 5.5V

Outputs High,

0.97

1.8

mA

2

4

mA

-30

Outputs, Low

Switching Characteristics over recommended operating free air temperature range (Note 1).
6,11 typical value!:! are measured at Vec=5V, TA=25°C.
DM74ALS27

DM54ALS27
Parameter

Conditions

TpLH, Propagation
delay time. Low to
high level output

VCC = 4.5 to 5.5V
RL = 500 n,
CL = 50pF.

TpHL, Propagation
delay time. High to
low level output

Max

Unit

Min

4

22

4

15

ns

3

10

3

9

ns

Note': See Section' for test waveforms and output load,

2·45

Typ

Typ

Max

Min

~ II?'A National
CI:
~

~ Semiconductor

::E

c DM54ALS2~A1DM74ALS28A Quadruple 2-lnput NOR Buffers

~

~
::E
c

General Description

Absolute Maximum Ratings (Note 1)

This device contains four independent gates each of
which performs the logic NOR function.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS28A
DM74ALS28A
Storage Temperature Range

Features
•
•
•
•
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
Functionally and Pin For Pin Compatible with LS TTL
Counterpart. ,
Improved AC Performance Over LS28.
Improved Line Receiving Characteristics.

Connection Diagram

7V
7V
-55·C to 125·C
, O·Cto 70·C
-65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are Ihose valuee beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limit •• The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the condilions for actual device operation.

Function Table

Dual·ln·Llne Package

y=A+i'
14

Inputs

'B

Y

L
L

L

H

H

L
L
L

H
H

IY

IA

18

2A

28

TUF/61B8-1

54ALS28A (J)

L

H

H = High Logic Level
L = Low Logic Level

SND

74ALS28A (J,N)

2·46

Output

A

.--------------------------------------------------------------------,0

~.

Recommended Operating Conditions
DM74ALS28A

DM54ALS28A
Parameter

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

Supply Voltage, VCC
High Level Input Voltage, VIH

2

Unit
V
V

2

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Current, 10H

-1

-2.6

mA

Low Level Output Current, 10L

12

24

mA

Max

Unit

-1.5

V

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vcc =5V, TA =25'C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC

VOH

High Level Output
Voltage

VCC = 4.5V
VIL = VILMAX

10H
VOL

Low Level Output
Voltage

=

Min

=

4.5V, II

=-

Typ

-18 rnA
54ALS
10H= -1mA

2.4

3.2

V

74ALS
10H = -2.6mA

2.4

3.3

V

54/74ALS

4OOItA

VCC = 4.5V
VIH = 2V

V

VCC-2

54/74ALS
10L = 12mA

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

II

Max High Input Current

VCC

=

5.5V, VIH

=

7V

0.1

rnA

IIH

High Level Input Current

VCC

=

5.5V, VIH

=

2.7V

20

' itA

IlL

Low Level Input Current

VCC

=

5.5V, VIL

=

0.4V

-0.1

rnA

10

Output Drive Current

VCC

=

5.5V

-112

rnA

ICCH

Supply Current

Outputs High

VCC

=

5.5V, VI

=

1.7

2.8

mA

ICCL

Sup~ly Current

Outputs Low VCC

=

5.5V, VI

= 4.5V

4.8

9

rnA

Vo

=

-30

2.25V
OV

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vcc=5V, TA=25'C.
DM54ALS28A
Parameter

Conditions
~

TpLH, Propagation
delay time. Low to
high level output

VCC = 4.5 to 5.5V
RL = 500n,
CL = 50 pF.

TpHL, Propagation
delay time. High to
low level output

Min

DM74ALS28A
Unit

Min

2

10

2

8

ns

2

10

2

7

ns

2-47

Typ

Max

Max

Note 1: See Section 1 for test waveforms and output load.

Typ

r-

~

o
3:

~
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S

~National

a

'
Semiconductor

DM54ALS30A/DM74ALS30A Blnput NAND Gate
General Description

Absolute Maximum. Ratings

This device contains a single gate which performs the
logic NAND function.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS
DM74ALS
Storage Temperature Range

Features
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
• Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
• Functionally and Pin For Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.
• Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.

7V
7V
-55°C to 125°C
OoC to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

I

Function Table

Connection Diagram
Dual·ln·Line Package
vee
114

NC

H

NC

G

12

113

11

110

y

Ne

Y=ABCDEFGH

8

19

)0-

1
A

2
B

3

e

·4
D

~Is.
5

E

F

H

17

Inputs

Output

A thru H

Y

All Inputs H

L

One or More
Input L

H

=High Logic Level

L = Low logic Level

GND

TLlF/6189·1

54ALS30A (J)

(Note 11.

74ALS30A (J,N)

o

2-48

c

s:
en

Recommended Operating Conditions
DM54AlS30A
Parameter

DM74AlS30A

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Unit

t

r0C/)
Co)

Supply Voltage, VCC
High Level Input Voltage, VIH

2

V
V

2

o

-»
c

s:

;

0.8

0.8

V

High Level Output Current, 10H

-0.4

-0.4

mA

r0C/)

Low Level Output Current, 10l

4

8

mA

»~..

Max

Unit

-1.5

V

low Level Input Voltage, Vil

Electrical Characteristics over recommended operating free air temperature range.
All typical values ar~ measured at Vee = 5V, TA = 25°C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC

VOH

High level Output
Voltage

10H = -O.4mA
VCC = 4.5 to 5.5V

, VOL

Low Level Output
Voltage

VCC

=

=

4.5V,11

Typ

Min

=

-18 mA

V

VCC-2

4.5V

54/74ALS
10L = 4 mA

0.25

0.4

V

74ALS
10L = 8 mA

0.35

0.5

V

II

Max High Input Current

VCC

=

5.5V, VIH

=

7V

0.1

mA

IIH

High Level Input Current

VCC

=

5.5V, VIH

=

2.7V

20

,.,A

IlL

Low Level Input Current

VCC

=

5.5V, VIL

=

O.4V

-0.1

mA

10

Output Drive Current

VCC

=

5.5V

Vo

-112

mA

ICC

Supply Current

VCC

=

5.5V

Outputs High

0.22

0.36

mA

0.54

0.90

mA

=

-30

2.25V

I

Outputs Low

Switching Characteristics over recommended operating free air temperature range (Note 1).
~II

typical values are measured at Vee = 5V, TA =25°C.
DMS4ALS30A

Parameter

Conditions

TPLH, Propagation
delay time. Low to
high level output

VCC = 4.5 to 5.5V
RL = 500 n,
Ci.. = 50 pF.

TpHL, Propagation
delay time. High to
low level output

Typ

Max

Unit

Min

3

12

3

10

ns

3

15

3

12

ns

Note 1: See Section 1 for test waveforms and output load.

2-49

Typ

DM74ALS30A
Max

Min

N,---------------------------------------------------~------_.

~ ~National

~ ~ Semiconductor
:E

-c DM54ALS32/DM74ALS32 Quad 2-lnput OR Gates
~

(J)

....I

~
:E
c

General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic OR function.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS
DM74ALS
Storage Temperature Range

Features
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.

•

Advanced Oxi~e-Isolated, lon-Implanted Schottky TTL
Process.

•

Functionally and Pin For Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.

•

Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.

1:

Connection Diagram

Function Table

Y=A+B
Inputs

Y1

A2

B2

Y2

TLIF16190·1

54ALS32 (J)

B

Y

L
L
H
H

L
H
L
H

L
H
H
H

L = Low Logic Level

GND

74ALS32 (J,N)

2·50

Output

A

H = High Logic Level

7
B1

7V
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Nota
The "Absolute Maximum Ratings" afe those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will'
define the conditions for actual device operation.

Dual·ln·Line Package

A1

(Note 1)

Recommended Operating Conditions
DM54ALS32
Parameter
Supply Voltage
High Level Input Voltage. VIH

DM74ALS32

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

2

Low Level Input Voltage. VIL

Unit
V
V

0.8

0.8

V

High Level Output Current. 10H

-0.4

-0.4

mA

Low Level Output Current. 10L

4

8

mA

Max

Unit

-1.5

V

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25°C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.5V, II = -18 mA

VOH

High Level Output
Voltage

10H = -0.4mA
V CC = 4.5 to.5.5V

VOL

Low Level Output
Voltage

VCC = 4.5V

Min

Typ

V

VCC-2

54/74ALS
10L = 4 mA
74ALS
10L = 8 mA

,

0.25

0.4

V

0.35

0.5

V

II

Max High Input Current

VCC = 5.5V, VIH = 7V

0.1

mA

IIH

High Level Input Current

,Vee = 5.5V, VIH = 2.7V

20

J.l.A

IlL

Low Level Input Current

VCC = 5.5V, VIL = 0.4V

-0.1

mA

10

Output Drive Current

VCC = 5.5V

Vo = 2.25V

-112

mA

ICC

Supply Current

VCC = 5.5V

Outputs High

1.9

4

mA

Outputs Low

2.6

4.9

mA

-30

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V, T A = 25°C.
DM54ALS32
Parameter

Conditions

TpLH, Propagation
delay time. Low to
high level output

VCC = 4.5 to 5.5V
RL = 50012,
CL = 50 pF.

TpHL. Propagation
delay time. High to
low level output

DM74ALS32
Typ

Max

Unit

Max

Min

3

16

3

14

ns

3

13

3

12

ns

Min

Note 1: See Section 1 for test waveforms and output load.

2·51

Typ

a'?A National
Semiconductor
~ ~
~

:E

c DM54ALS33AJDM74ALS33A Quadruple 2-lnput NOR Buffers

a
~

with Open-Collector Outputs

~ General Description

Features

:E

•
•

."

c

This device contains four Independent gates each of which
performs the logic NOR function. The open·collector outputs require external pull-up resistors for proper logical
operation.
.

Pull·Up Resistor Equations

•
•
•
•

R

MIN=

Where:

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
Advanced, Oxide-Isolated, lon-Implanted Schottky TTL
Process.
Functionally and Pin For Pin Compatible with LS TTt:
Counterpart.
Improved AC Performance Over LS33.
Improved Line Receiving Characteristics.

Absolute Maximum Ratings

Vee (Max)- VOL
10L- N3 (lIU

N1 (IOH) = total maximum output high current
for all outputs tied to pull-up resistor
N2 (lIH) total maximum Input high current for
all inputs tied to pull-up resistor
N3 (Ilu = total maximum input low current for
all Inputs tied to pull-up resistor

=

Supply Voltage
Input Voltage
Off State (High Level)
Output Voltage
Operating Free Air Temperature Range
DM54ALS33A
DM74ALS33A
Storage Temperature Range

(Note 1)
7V
7V
7V

-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Note 1: The "AbsQlute Maximum Ratings" are those values beyond
which"the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed" at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define" the conditions for actual device operation.

Connection· Diagram

Function Table

Dual-In-Llne Package

Y=A+B

14

1I1puts
B

Y

L
L
H
H

L
H
L
H

H
H
H
L

=
=

H High Logic Level
L Low Logic Level
TUFfS191·1

. 54ALS33A (J)

74ALS33A (J, N)

2-52

Output

A

,----------------------------------------------------------------------,0
3:

Recommended Operating Conditions
,DM54ALS33A
Parameter
Supply Voltage, VCC
High Level Input Voltage, VIH

DM74ALS33A

Min

Nom

Max

Min

Nom

Max

4.5

5

S.S

4.5

5

5.5

V
V

2

2

Unit

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Voltage, VOH

5.5

5.5

V

12

24

mA

t
~o

I"'"

3:
~

J>

~.

Low Level Output Current, IOL

~

Electrical Characteristics over recommended opera!ing free air temperature range.
All typical values are measured at Vcc = 5V, TA = 25°C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC

=

4.5V, II

=

IOH

High Level Output
Current

VCC

=

4.5V, VOH

VOL

Low Level Output
Voltage

VCC = 4.5V
VIH = 2V

Min

=

Max

Unit

-1.5

V

100

/lA

Typ

-18 mA
5.5V

54/74ALS
IOL = 12mA

0.25

0.4

V

74ALS
IOL = 24mA

0.35

0.5

V

II

Max High Input Current

VCC

=

5:5V, VIH

=

7V

0.1

mA

IIH

High Level Input Current

VCC

=

5.5V, VIH

= 2.7V

20

/lA

IlL

Low Level Input Current

VCC

=

5.5V, VIL

=

-0.1

mA

ICCH

Supply Current

Outputs High

ICCL

Supply Current

Output~

0.4V

VCC

=

5.5V, VI

=

OV

1.7

2.8

mA

Low VCC

=

5.5V, VI

=

4.5V

4.8

9

mA

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vce = SV, TA

=2S0C.
DM74ALS33A

DM54ALS33A
Parameter
TPLH, Propagation
delay time. Low to
high level output

Conditions
VCC - 4.5V to 5.5V
RL = 667!l
CL = 50 pF

TPHL, Propagation
delay time. High to
low level output

Min

Typ

Typ

Max

Min

Max

S

40

S

33

2

18

2

12

Unit

ns
ns

Note 1: See Section 1 for test waveforms and output load.

2-S3

•

II?JI National '
~ Semiconductor
DM54ALS37A1DM74ALS37A
Quadruple 2-lnput NAN D Buffers
General Description

Absolute Maximum Ratings

This devl.ce 'contains four Independent gates each of
which performs the logic NAND function.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS37A
DM74ALS37A
Storage Temperature Range

Features
•
•
•
•
•
•

Switching Specifications at 50 jJF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
Advanced, Oxide-Isolated, lon-Implanted Schottky TTL
Process.
Functionally and Pin For Pin Compatible with LS TTL
Counterpart.
Improved At Performance Over LS37.
Improved Line Receiving Characteristics.

Connection Diagram

B4

A4

Function Table

Y4

83

A3 .

Inputs

81

Y1

A2

82

Y2

GND

B

Y

L
L

L

H

H
H

L

H
H
H

H

L

H = High Logic Level
L

TUFfB'92·'

54ALS37A (J)

74ALS37A (J,N)

2-54

Output

A

7
A1

7V
7V
-55·C to 125·C
O·C ta-70·C
-65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not jluaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual·ln-Llne Package
vee

(Note 1)

=Low Lagle Level

,-----------------------------------------------------------------------,0

3:

Recommended Operating Conditions
DM54ALS37A
Parameter

DM74ALS37A

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Supply Voltage, VCC

2

High Level Input Voltage, VIH

2

Unit

ten
-~
r-:'

Co)

V
V

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Current, 10H

-1

-2.6

mA

. Low Level Output Current, 10L

12

2~

mA

Max

Unit

-1.5

V

o
3:

i:!

~

~
~

Co)

Electrical Characteristics over recommended operating free air te~perature range.
All typical values are measured at Vee = 5V, TA = 25"C.

Symbol

Parameter

Conditions

Min

VIK

Input Clamp Voltage

VCC = 4.5V, II = -18 rnA

VOH

High Level Output
Voltage

VCC = 4.5V
VIL = VIL MAX

VOL

Low Level Output
Voltage

Typ

54ALS
10H = -1mA

2.4

3.2

V

74ALS
10H = -2.6mA

2.4

3.3

V

V

10H = -4001tA

54/74ALS

VCC = 4.5V
VIH = 2V

54/74ALS
10L = 12mA

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

VCC-2

II

Max High Input Current

-VCC = 5.5V, VIH = 7V

0.1

mA

IIH

High Level Input Current

VCC = 5.5V, VIH = 2.7V

20

/LA

IlL

Low Level Input Current

VCC = 5.5V, VIL - O.4V

-0.1

rnA

10

Output Drive Current

VCC = 5.5V

-112

rnA

ICCH

Supply Current

Outputs High

0.86

1.6

rnA

ICCL

Supply Current

Outputs Low VCC = 5.5V, VI = 4.5V

4.0

7.8

rnA

Vo = 2.25V

-30

VCC = 5.5V, VI = OV

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee =5V, TA=25"C.

DM74ALS37A

DM54ALS37A
Parameter
TPLH, Propagation
delay time. Low to
high level output

Conditions
VCC = 4.5 to 5.5V
RL =
CL = 50 pF

soon

TpHL, Propagation
delay time. High to
low level output

Max

Unit

Min

2

10

2

8

ns

2

10

2

7

ns

Note 1: See Section 1 for test waveforms and output load.

2-55

Typ

Typ

Max

Min

fI

~ ~National

~ ~ Semiconductor
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~

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Q

DM54ALS38A1PM74ALS38A Quadruple 2-lnput
NAN D Buffers with Open-Collector Outputs
General Description

Features

This device contains four independent gates each of
which perform~ the logic NAND function. The opencollector outputs require external pull-up resistors for
proper logical operation.
'.

•
•

Pull·Up Resistor Equations
R

MAX =

R

MIN=

Where:

Switching Specifications at 50 pF.
Switching'Specifications Guaranteed Over Full
Temperature and VCC Range.
• Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
• Functiona!ly and Pin For Pin Compatible with LS TTL
Counterpart.
•
•

Vcc(Mln)-VOH
N, (IOH) + N2 (IIH)

Improved AC Performance Over LS38.
Improved Line Receiving Characteristics.

Absolute Maximum Ratings

VcC
r

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Voltage, VOH

5.5

5.5

V

en

Low Level Output Current, IOL

12

24

mA

~

Max

Unit

-1.5

V

100

/LA

Co)

Electrical Characteristics over recommended operating free air temperature range.
All typical-values are,measured at Vee = 5V, TA = 25"C.
Symbol

Parameter

Min

.Conditions

VIK

Input Clamp Voltage

VCC

=

4.5V, II

=

IOH

High Level Output
Current

VCC

=

4.5V, VOH

VOL

Low Level Output
Voltage

VCC
V IH

= 4.5V
= 2V

Typ

-18 mA

=

5.5V

54/74ALS
IOL = 12mA

0.25

0.4

V

74ALS
IOL = 24mA

0.35

0.5

V

II

Max High Input Current

VCC

=

5.5V. VIH

=

7V

0.1

mA

IIH

High Level Input Current

VCC

=

5.5V. VIH

= 2.7V

20

!LA

IlL

Low Level Input Current

VCC

=

5.5V. VIL = O.4V

,..,0.1

mA

ICCH

Supply Current

Outputs High VCC

=

5.5V. VI

=

OV'

0.86

1.6

mA

ICCL

Supply Current

Outputs Low VCC

=

5.5V. VI

=

4.5V

4.0

7.8

mA

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V. TA = 25"C.
DM54ALS38A
Parameter
TpLH. Propagation
delay time. Low to
high level output

Conditions
VCC = 4.5 to 5.5V
RL = 667
CL = 50 pF

n.

TpHl.. Propagation
delay time. High to
low level output

Min

Typ

DM74ALS38A
Max

Min

Typ

Max

Unit

5

40

5

33

ns

2

18

2

12

ns

Note 1: See Section 1 for test waveforms and output load.

2-57

j

~ ~National

~
~ Semiconductor
j:!:
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~

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c

DM54ALS40AlDM74ALS40A Dual4-lnput NAND Buffers
General Description

Absolute Maximum Ratings

This device contains two independent gates each of
which performs the logic NAND function.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS40A
DM74ALS40A
Storage Temperature Range

Features
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
• Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
•
•
•

Functionally and Pin For Pin Compatible with LS TTL
Counterpart.
Improved AC Performance Over LS40.
Improved Line Receiving Characteristics.

Connection Diagram

(Note 1)
7V
7V

-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Nota 1: The "Absolute Maximum Ratings" are those values beyond
which thelsafety of the device can not be guaranteed. The device should
not be operated 'at these~limits. The parametric values defined in the
"Electrical Characteristics" tlable are not guaranteed at the absolute
. maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Dual-In-Line Package

vee
114

D2
13

C2
12

B2

NC

j,1

10

A2

Y2

\9

Y=ABCD

8

~
1

2

A1

B1

J:

4
C1

5

D1

~
Ie 17
Y1

Output

Inputs

GND

A

B

C

D

Y

X

X

L

X

X

X
L
H

L

X
L
X
X
H

H
H
H
H
L

X
H

X
X
X
H

H = High Logic Level
L = Low Logic Level

TL/F/6194·1

X = Either Low or High Logic Level

54ALS40A (J)

74ALS40A (J,N)

2·58

r----------------------------------------------------------------------.c

3l:

Recommended Operating Conditions
DM74ALS40A

DM54ALS40A
Parameter

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Supply Voltage, VCC

Unit
V

~

r-

~

C
2

High Level Input Voltage, V,H

V

2

Low Level Input Voltage, V,L

0.8

0.8

V

High Level Output Current, 10H

-1

-2.6

mA

Low Level Output Current, 10L

12

24

mA

Max

Unit

-1.5

V

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25°C.
Sym

Parameter

V,K

Input Clamp Voltage

VOH

High Level Output
Voltage

Conditions

Low Level Output
Voltage

=

4.5V,I'

-18 mA

VCC = 4.5V
V,L = V,LMAX

10H
VOL

=

. VCC

=-

Typ

Min

54ALS
10H = -1mA

2.4

3.2

V

74ALS
10H = -2.6mA

2.4

3.3

V

54/74ALS

400itA

VCC = 4.5V
V,H = 2V

=

54/74ALS
10L = 12mA

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

0.1

mA

20

/LA

-0.1

mA

-112

mA

0.43

0.8

mA

2.4

3.9

mA

Max High Input Current

VCC

=

5.5V, V,H

"
',H'

High Level Input Current

VCC

=

5.5V, V,H = 2.7V

IlL

Low Level Input Current

VCC

= 5.5V, VIL =

10

Output Drive Current

VCC = 5.5V

ICCH

Supply Current

Outputs High

ICCL

Supply Current

Outputs Low VCC

7V

O.4V
Vo

VCC

V

VCC- 2 :

=

= 2.25V

5.5V, VI

=

-30

OV

= 5.5V, VI = 4.5V

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical
values are measured at Vee = 5V, TA = 25°C .
. ..
DM74ALS40A

DM54ALS40A
Parameter

Conditions

TpLH, Propagation
delay time. Low to
high level output

VCC = 4.5 to 5.5V
RL = 500n,
CL = 50 pF.

TpHL, Propagation
delay time. High to
low level output

Min

Typ

Typ

Max

Unit

Max

Min

2

10

2

8

ns

2

10

2

7

ns

Nole1: See Section 1 for test waveforms and outpulload.

2·59

3l:

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~

~

.
Semiconductor

~National

a

DM54ALS74A/DM74ALS74A Dual D Positive-EdgeTriggered Flip-Flops with Preset and Clear
I

General Description

•

The DM54ALS74 is a dual ed~e-triggered flip-flops. Each
flip-flop has individual D. clock. clear and preset inputs. and
also complementary a and 0 outputs.
Information at input D is transferred to the a output on the
positive going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly
related to the transition time of the positive going pulse.
When the clock input is at either the high or low level. the D
input signal has no effect.
Asynchronous preset and clear inputs will set or clear a
output respectively upon the application of low level Signal.

Features
•

Advanced Oxide-Isolated. Ion-Implanted Schottky TTL
Process.
• Functionally and Pin-For-Pin Compatible with Schottky
and LS TTL Counterpart.
• Improved AC Performance Over LS74 at .
Approximately Half the Power.

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS
DM74ALS
Storage Temperature Range

• Switching Specifications Guarimteed Over Full
Temperature an~ VCC Range.

Dual·ln·Llne Package
02

ClK2

PR2

02

01

ClK 1 PR 1

01

Inputs

02

7
'CLR 1

01

GNO

Outputs

PR

CLR

CLK

0

Q

L
H
L
H
H
H

H
L
L
H

X
X
X

X
X
X
H
L
X

H
L
H*
H
L
aO

H
H

i
i
L

Q

L
H
H*
L.
H
00

L = Low State. H = High Stale. X = Don't Care
1 - Positive Edge Transition
00 - Previous Condition 01 0
• - This condition is non stable; H will not persist when preset and clear Inputs return to their Inactive (high) level. The output levels In this condition are
not guaranteed to meet the VOH specification.

TUU6109·1

54ALS74A (J)

-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Function Table

Connection Diagram
CLR2

7V
7V

Nota 1: The "Absolute Maximum Ratings" arG those values beyond
which Ihe salely 01 Ihe device can nol be guaranteed. The device should
not be operated at these limits. The parametric values dell ned In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Condltlons"table wilt
define the conditions lor actual device operation.

Switching Specifications at 50 pF.

vcc

(Note 1)

74ALS74A (J,N)

2-60

Recommended Operating Conditions
DM54ALS74A
Parameter
Supply Voltage, VCC
High Level Input Voltage, V,H

DM74ALS74A

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Low Level Input Voltage, V,L
High Level Output Current, 10H

V
V

2

2

Unit

0.8

0.8

V

-0.4

-0.4

mA

B

mA

34

MHz

Low Level Output Current, 10L

4

Clock frequency, fCLOCK

0

Width of Clock Pulse, TW

Pulse Width TW,
Preset & Clear
Data Setup Time, TSU

30

0

High

16.5

14.5

ns

Low

16.5

14.5

ns

Low

15

15

ns

Data

151

151

ns

PRE or CLR
Inactive

101

101

ns

01

01

ns

Data Hold Time, TH

The (1) arrow indicates the positive edge of the Clock is used for reference.

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vcc = 5V, TA = 25'C.
Parameter

Conditions

V,K

Input Clamp Voltage

VCC=4.5V, II = -1B mA

VOH

High Level Output
Voltage

10H = -400"A
VCC = 4.5 to 5.5V

VOL

Low Level Output
Voltage

VCC = 4.5V
V,H = 2V

Symbol

II

IIH

Max High
Input Current

Clock, D

High Level
Input Current

Clock, D

Min

Typ

Low Level
Input Current

54/74ALS
10L = 4mA

0.25

0.4

V

74ALS
10L = BmA

0.35

0.5

V

0.1

mA

0.2

mA

20

"A

40

"A

-0.2

mA

-0.4

mA

-112

mA

4

mA

VCC = 5.5V, V,H = 7V

VCC = 5.5V, V,H = 2.7V

VCC=5.5V, V'L=0.4V

Preset, Clear
10

Output Drive Current

VCC=5.5V, VO=2.25V

ICC

Supply Current

VCC = 5.5V

2-61

V
V

Preset, Clear

Clock, D

Unit

VCC-2

Preset, Clear
IlL

Max
-1.5

-30
2.4

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = SV, TA =2S"C.

-

Parameter

From

To

Min

TPLH

TPLH

Typ

Max

Preset
or clear

a

Clock

a

VCC = 4.5V to 5.5V
RL = 5000
CL=50pF

TPHL

Typ

Max

Unit
MHz

3

15

3

13

ns

5

17

5

15

ns

5

18

5

16

ns

5

20

S

18

ns

Note 1: See Section 1 for test waveforms and outpulload.

Logic Diagram
PRESET--;=~~=::rl

ct.UR -Tr;:::::::::t-.J~"'-;::::j

2-62

Min
34

30

FMAX

TpHL

DM74ALS74A

DM54ALS74A

Conditions

c

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C1I

D Semiconductor

tr-

DM54ALS86/DM74ALS86 Quad 2-lnput Exclusive-OR Gates

-

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General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic exclusive-OR function_

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS
DM74ALS
Storage Temperature Range

Features
•
•

Switching Specifications at 50 pF.
SWitching Specifications Guaranteed Over Full
Temperature and VCC Range.
• Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
• Functionally and Pin For Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.
•

Function Table

Dual-In-Line Package

Y=Ae B=AB+Aii
Inputs

7

A1

81

Y1

82

Y2

GND

TLlF16195·1

54ALS88(J)

7V
7V
-55°C to 125°C
DoC to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.

Connection Diagram

(Note 1)

74ALS86 (J, N)

2-63

OutP!lt

Y

A

B

L

L

L

L

H

H

H

L

H

H

H

L

~
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en

~
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Recommended Operating Conditions
Parameter

c

Supply Voltage

:!E

I

DM74ALS86

DM54ALS86

~

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

·5

5.5

High Level Input Voltage, VIH

2

Unit
V
V

2

...I

~
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c

Low Level Input Voltage, VIL

0.8

0.8

V

. High Level Output Current, 10H

-0.4

-0.4

mA

Low Level Output Current, 10L

4

8

mA

Max

Unit

-1.5

V

Electrical Characteristics over recommended operati.ng free air temperature range.
All typical values are measured at Vee = 5V, TA = 25°C.

Symbol

Parameter

Conditions

= 4.5V,

=

VIK

Input Clamp Voltage

VCC

VOH

High Level Output
Voltage

10H = -O.4mA
Vee 4.5 to 5.5V

VOL

Low Level Output
Voltage

Vec

II

Typ

-18 mA

= 4.5V

VCC

= 5.5V, VIH =

'. 54/74ALS
10L = 4mA

0.25

0.4

V

74ALS
10L = 8mA

0.35

·0.5

V

0.1

mA

20

p.A

-0.1

mA

-112

mA

5.9

rnA

7V

IIH

High Level Input Current

Vee

= 5.5V, VIH = 2.7V

IlL

Low Level Input Current

Vee

= 5.5V,

10

Output Drive Current

VCC

= 5.5V

ICC

Supply Current

Vee

= 5.5V ,All inputs at 4.5V

VIL

V

VCC-2

=

. Max High Input Current

II

Min

I

=

0.4V

.vo = 2.25V

-30
3.9

SWitching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V, TA = 25°C.

Parameter

Conditions

DM74ALS86

DM54ALS86
Min

Typ

Max'

Min

Typ

Unit

Max

Aor BtoV

3

22

3

17

ns

tPHL. Propagation
Delay Time. High to
Low'Level Output

Other Input Low

2

14

2

12

ns

tpLH. Propagation
Delay Time. Low to
High Level Output

Aor Bto V

3

22

3

17

tPHL. Propagation
Delay Time. High to
Low Level Output

Other Input High

t PLH, Propagation
Delay Time, Low to
High Level Output

(Note 2)

2

Note 1: See Section 1 for test waveforms and output load.
Note 2:

ns
\

vec =4.5 to 5.5V,RL= 500n,eL= 50 pF

2-64

12

2

10

ns

.---------------------------------------------------------------.0

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'?'A National
a Semiconductor

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.....

o

DM54ALS109A/DM74ALS109A Dual J-K Positive-EdgeTriggered Flip-Flops with Preset and Clear
General Description

Features

The DM54ALS109A is a dual edge·triggered flip flop. Each
flip flop has individual J, R, clock, clear and preset inputs,
and also complementary and outputs.

I!'

a

a

a

Information at input J or K is transferred to the output on
the positive going edge of the clock pulse. Clock triggering
occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive going pulse.
When the clock input is at either the high or low level, the J,
K input signal has no effect.

a

Asynchronous preset and clear inputs will set or clear
output respectively upon the application of low level signal.

The J K design allows operation as a D flip flop by tying the J
and K inputs together.

•
•

~

-s::
o

~

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.

•

Functionally and Pin For Pin Compatible with Schottky
and LS TTL Counterpart.

•

Improved AC Performance Over LS109 at
Approximately Half the Power.

Absolute Maximum Ratings

(Note 1)
7V
7V

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS
DM74ALS
Storage Temperature Range

-55 D C to 125 D C
ODe to 70 DC
-65°C to 150 D C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits, The parametric values defi~ed in the.
'''Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings, The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual·ln·Line Package
VCC
116

CLR2

J2

K2

14

115

113

12

02

10

111

L

·1

02

ClK 2 PR 2

!

PR
J

QIQh

K

~

I>ClK
J

PR
Q

0

I>ClK

_ ClR_

L-.-.-

K

ClR

0

~

I
1
ClR 1

2
Jl

9

14
15
-'3
ClK 1 PR 1
Kl

6

01

7

01

CLR

Inputs
CK

J

K

Q

L
H
L
H
H
H
H
H

H
L
L
H
H
H
H
H

X
X
X
1
1
1
1
L

X
X
X
L
H
L
H
X

X
X
X
L
L
H
H
X

H
L
H
L
H*
H*
L
H
TOGGLE
00
00
H
L
00
00

Q

L ~ Low State, H ~ High State, X ~ Don't Care
I = Positive Edge Transition. 00 = Previous Condition of a
• This condition is nonstable; it will not persist when present and clear inputs
return to their inactive (high) level. The output levels in this condition are not
guaranteed to meet the VOH specification.

IS
GND

TLlF/6196·1

54ALS109A (J)

Outputs

PR

74ALS109A (J,N)

2-65

»
ren
.....

o
co

»

~
,..
en

Recommended Operating Conditions
DM54ALS109A

...I

Parameter

:i

r!
c

Supply Voltage, VCC

~
,..

High Level Input Voltage, VIH

.ClK
...- K
I>CLK
J

PR

01-

'-- K

on

ClR

at---

y

I
1

ClR 1

2
J1

15
PR 1

6
01

7

'01

Is

CLR

L
H
L
H
H
H
H
H

H
L
L
H
H
H
H
H

Inputs
CK

J

K

Q

X
X
X

X
X
X

X
X
X

•
•

L
H
L
H

H
H
L
L

H

X

X

H
L
L
H
H*
H*
L
H
TOGGLE
00
aO
H
L
00
00

••

Outputs

Q

L - Low State, H - High State, X - Don't Care
1= Negative Edge Transition, QO = Previous Condition of Q
• This condition is n'onstable; it will not persist when present and clear inputs
return to their inactive (high) level. The output levels in this condition are not
guaranteed to meet the VOH specification,

GND

TLlF/6197-1

54ALS112A (J)

PR

74ALS112A (J, N)

2-68

Recommended Operating Conditions
DM54ALS112A
Parameter
Supply Voltage,

)Icc

DM74ALS112A

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5.

High level Input Voltage, VIH

2

2

Unit
V
V

O.B

O.B

V

High Level Output Current, 10H

-0.4

-0.4

mA

Low Level Output Current, 10L

4

B

mA

30

MHz

Low Level Input Voltage, VIL

Clock Frequency, fCLOCK

25

0

0

Clock High

20

16.5

ns

Clock Low

20

16.5

ns

15

.10

ns

Pulse Width TW

Pulse Width TW, Preset or Clear Low

J arK

251

221

PRE or CLR
inactive

221

201

01

01

ns

Data Setup Time, TSU

Data Hold Time, TH
The

ns

(h arrow indIcates the negative edge, of tbe Clock IS used for reference.

Electrical Characteristics over recommended operating free air temperature r.ange.
All typical values are measured at Vee = 5V, TA = 25"C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC=4.5V,II= -1BmA

VOH

High Level Output
Voltage

10H = -0.4 mA
VCC = 4.5 to 5.5V

VOL

Low Level Output
Voltage

VCC = 4.5V
VIH = 2V

II

Max High Input Current

Min

r

Typ

High Level
Input Current

Clock, J, K

Low Level
Input Current

Clock, J, K

-1.5

V
V

54{74ALS
10L = 4mA

0.25

0.4

V

74ALS
10L = BmA

0.35

0.5

V

0.1

mA

VCC=5.5V, VIH=7V J, K, ClK

0.2
20

VCC = 5.5V, VIH = 2.7V

~A

40

Preset, Clear
IlL

Unit

VCC -2

PREorCLR
IIH

Max

-0.2

VCC=5.5V, VIL=0.4V

mA

-0.4

Preset, Clear
10

Output Drive
Current

Va =

VCC

=

ICC

Supply Current

VCC

=

-30

5.5V
2.25V

2.5

5.5V

2-69

-112

mA

4.5

mA

~
.... SWitching Characteristics over recommended operating free air temperature range (Note 1).

!i

All typical values are measured at Vcc =5V, TA=25"C.

.

c(

~

:IE

-c~....

!i
~

':&

c

DM74ALS112A

, DM54ALS112A
Parameter

From

To

Conditions

Min

TPHL

Max

Preset
or clear

Oor

Q

TPLH

VCC = 4.5V to 5.5V
RL = 500!2
CL = 50 pF

Oor

Clock

Q

TpHL

Min

MHz

3

15

ns

4

22

4

18

ns

3

18

3

15

ns

5

23

5

19

ns

ii

PR~------"----~

K-===~
'
TLfF/6197-2

2·70

Unit

20

Logic Diagram

elK

Max

3

Note1:--See Seclion 1 for ,Iesl waveforms and oulpulload.

Q

Typ

30

25

FMAX
TpLH

Typ

.---------------------------------------------------------------,0

:s:

~National

(J1
~

D Semiconductor

»
.(J)
..&.
..&.

DM54ALS113A/DM74ALS113A Dual J-K Negative-EdgeTriggered Flip-Flops with Preset
General Description

Features

The DM54ALSl13A is a dual edge-triggered flip-flop_ Each
flip-flop has individual J, K, clock, and preset inputs, and
also complementary a and Q outputs_

•
•

Information at input J or K is transferred to the a output on
the negative going edge of the clock pulse_ Clock triggering occurs at a voltage level of the clock pulse and is not
directly related to the transition time of the positive going
pulse_ When the clock input is at either the high or low
. level, the J, K input signal has no effect.

•

Asynchronous preset inputs will set a output upon the application of low level signal.
The JK design allows operation as a 0 flip-flop by tying the
J and K inputs together.

•
•

-:s:~o

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
Functionally and Pin For Pin Compatible with Schottky
and LS -TTL Counterpart.
Improved AC Performance Over LSl13 at
Approximately Half the Power.

Absolute Maximum Ratings

(Note I)
7V
7V

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS
DM74ALS
Storage Temperature Range

-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Note 1: The "Absolute MaxImum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maxImum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual-In-Line Package
Vee

114

ClK2

K2

13

J2

12

PR 2

11

Inputs
02

02
9

110

8

6
'-

I-

L

:

9
ClK 1

2
Kl

3
Jl

14
PR 1

6

5
01

-

01

P

GND

TLlF/6198·1

54ALS113A (J)

CK

J

K

Q

L
H
H
H
H
H

X

X
L

X
H
H
L
L
X

H
L
L
H
TOGGLE
00
00
H
L
00
00

I
I
I
I

H
L
H

H

X

=Low Siale, H =High Siale, X =Don't Care

I = Negalive Edge Transilion, 00 = Previous Condilion of 0
I-

1

Outputs
Q

PR

74ALS113A (J, N)

2-71

~
.(J)
..&.
..&.

Co)

»

~
,...
,...

en
....I

 'LK
~tSELECT
INPUTS

.'

'DOt-

r- 1>'"
'----

"

r--

CI

.---,

r;-

I>m

R

D

~

y"
V"
V"
V"

0

11

"

DATA
DUTPUTS

YO

Vi

'----

CLOCK

ENAILE
INPUTS

r;-

.!.-...[:>o-

'1 V7

r~
6

G1

9 "6

r;-

r....
~

TLlFf6200-2

2-79

Unit

ns

en
.....
(,.)

-.....
c
3:
~

3>

~
.....
.....
(,.)

~National

PRELIMINARY

~ Semiconductor

DM54ALS132/DM74ALS132 Quad 2-lnput NAN 0 Gates with
Schmitt Trigger Input$ .
General Description

Absolute Maximum Ratings (Note 1)

This device contains four independent gates, each of
which performs the logic NAND function. Each input has
hysteresis which increases the noise immunity and transforms a slowly changing input signal to a fast changing,
jitter·free output.

Supply Voltage
Input Voltage
Storage Temperature

Features
• Switching specifications at 50 pF
, • Switching specifications guaranteed over full
temperature and VCC range
• Advanced oxide·isolated, ion-implanfed Schottky TIL
process
• Functionally and pin-for-pin compatible with Schottky
and low power Schottky TIL counterparts
• Improved AC performance over Schottky and low
power Schottky counterparts

Connection Diagram

7V
7V
-65·Cto + 150·C

Nota 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Dual-ln·Llne Package

Inputs
A
L
L
H
H

B
L
H
L
H

Output
y
H
H
H
L

H = high logic level

L

TL/F/6Iro7-1

DM54ALS132 (J)

This document contains

Infor~atlo~

=low logic level

DM74ALS132 (N)

on a pro~uct under development. NSC reserves the right to change or discontinue this product without notice.

2-80

·

Recommended Operating Conditions
Symbol

Parameter

DM54ALS132

DM74ALS132

Min

Typ

Max

Min

Typ

Max

5

5

Units

Vee

Supply Voltage

4.5

5.5

4.5

5.5

V

VT+

Positive-Going Input
Threshold Voltage (Note 2)

1.4

2

1.4

2

V

VT_

Negative-Going Input
Threshold Voltage (Note 2)

0.7

1.2

0.8

1.2

V

Hys

Input Hysteresis (Note 2)

0.5

V

0.5

10H

High Level Output Current

-0.4

10L

Low Level Output Current

4

TA

Free Air Operating
Temperature

-55

-0.4

125

0

mA

8

mA

70

·C

Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol

Parameter

Conditions

Min

Typ
(Note 3)

Max
-1.5

Units

VI

Input Clamp
Voltage

Vee=Min, 11= -18 mA

VOH

High Level Output
Voltage

Vee=Min
IOH=Max
VI=VT-Min

DM54

Vee- 2

3.4

V

DM74

Vee- 2

3.4

V

Low Level Output
Voltage

Vee = Min
10L=Max
VI=VT+Max

DM54

0.25

0.4

V

DM74

0.35

0.5

V

DM74

0.25

0.4

V

VOL

IOL=4mA
Vee=Min

V

IT'

Input Current at
Positive-Going
Threshold

Vee = 5V, VI=VT+

0.03

mA

IT_

Input Current at
Negative-Going
Threshold

Vee=5V, VI=VT_

0.034

mA

II

Input Current at Max
Input Voltage

Vee = Max, VI = 7V

0.1

mA

IIH

High Level Input
Current

Vee = Max, VI=2.7V

20

p.A

IlL

Low Level Input
Current

Vee = Max, VI=O.4V

-0.1

mA

10

Output Drive
Current

Vee = Max, Vo=2.25V

-112

mA

leeH

Supply Current with
Outputs' High

Vee=Max

8

mA

leeL

Supply Current with
Outputs Low

Vee=Max

8

mA

Note 2: Vee=5V.
Note 3: All typicals are at Vee = 5V, TA =25"e.

2-81

-30

SWitching Characteristics over recommended operating free air temperature range·
DM54ALS132

DM74ALS132

Symbol

Parameter

tpLH

Propagation Delay Time,
Low to High Level Output

S

8

ns

tpHL

Propagation Delay Time,
High to Low Level Output

11

11

ns

Typ

Min

2·82

Max

Min

Typ

Max

Units

~National

~ Semiconductor
DM54ALS133/DM74ALS133 13-lnput NAND Gate
General Description

Absolute Maximum Ratings

This device contains a single gate which performs the
logic NAND function.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS
DM74ALS
Storage Temperature Range

Features
•
•
•
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
.
Advanced Oxide·lsolated, lon·lmplanted Schottky TTL
Process.
Functionally and Pin For Pin Compatible with Schottky
and Low Power Schottky TIL Counterpart.
Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.

(Note 1)
7V
7V

-55·C to 125·C
O·C to 70·C
-65·C to 150·C

Nole 1: The "Absolute Maximum Ralings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

•
Connection Diagram

Function Table

Dual·ln·Llne Package
vee

1

16

M

K

L

15

14

J

13

11

Y

1
2

B

3

e

5

4

D

E

6
F

JoH
L

17 18

G

GND

TLIFI6201,1

54ALS133 (J)

=ABCDEFGHIJKLM

9

1

10

r;
A

Y

H

12

74ALS133 (J,N)

2-83

Inputs

Output

A thru'M

Y

All Inputs H
One or More
Input L

L
H

=High Logic Level
=Low Logic Level

Recommended Operating Conditions
DM74ALS133

DM54ALS133
Parameter
Supply Voltage
High Level Input Voltage, VIH

Min

Nom

Max

Min

Nom

4.5

5

5.5

4.5

5

2

Max
- 5.5

2

Low Level Input Voltage, VIL

Unit
V
V

0.8

0.8

V

High Level Output Current, 10H

-0.4

-0.4

mA

Low Level Output Current, 10L

4

8

mA

Max

Unit

-1.5

V

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V,
Symbol

TA = 25"C.

Parameter

Min

Conditions

=

=

VIK

'Input Clamp Voltage

VOH

High Level Output
Voltage

10H = -0.4mA
VCC = 4.5 to 5.5V

VOL

Low Level Output
Voltage

VCC - 4.5V

VCC

4.5V, II

Typ

-18mA

V

VCC-2

54/74ALS
10L = 4mA

0.25

0.4

V'

74ALS
10L = 8mA

0.35

0.5

V

0.1

mA

II

Max High Input Current

VCC

=

5.5V, VIH

= 7V

IIH

High Level Input Current

VCC

=

5.5V, VIH

=

2.7V

20

p.A

IlL

Low Level Input Current

VCC

=

5.5V, VIL

=

O.4V

-0.1

mA

10

Output Drive Current

VCC

=

5.5V

Vo

-112

mA

ICC

Supply Current

VCC

=

5.5V

Outputs High

0.24

0.34

mA

Outputs Low

0.56

0.8

mA

=

-30

2.25V

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee =5V,

TA = 25"C.
DM54ALS133

Parameter
TPLH, Propagation
delay time. Low to
high Level Output

Conditions
VCC = 4.5 to 5.5V
RL = 500O,
CL = 50pF.

TPHL, Propagation
delay time. High to
low Level Output

Min

Typ

DM74ALS133

Typ

Min

3

14

3

11

ns

5

28

5

25

ns

Note 1: See Section 1 for test waveforms and output load.

2-84

Max

Unit

Max

~-----------------------------------------------------------------'C

i:.

~National

~

~ Semiconductor

r-

m
....
~

-c

DM54ALS1361 DM74ALS136 Quad 2-lnput
Exclusive-OR Gates with Open-Collector Outputs

i:
~

~

General Description
This device contains four independent gates, each of
which performs the logic exclusive-OR function. The
open-collector outputs require external pull-up resistors
. for proper logical operation.

Pull-Up Resistor Equations
R
MAX =

R
MIN =

~
....

Features

VCC(mln)-VOH

N1 (l oH )+ N2 (IIH)
V C9(max) - VOL
IOL - N3 (I III

• Switching specifications at 50 pF
• SWitching specifications guaranteed over full
temperature and Vcc range
• Advanced oxide-isolated, ion-implanted Schottky TTL
prpcess
• Functionally and pin-for-pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low
power Schottky counterparts

Absolute Maximum Ratings (Note 1)

Where N1 (loH = total maximum output high current for all
outputs tied to pull-up resistor.
N2 (IIH) = total maximum input high current for all
inputs tied to pull-up resistor.
N3 (I III = total maximum input low currentfor all inputs tied to pull-up resistor.

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature

Connection Diagram

Function Table

7V
7V
7V

-65·Cto

B4

A4

Y4

B3

Y3

Y=AeB
Output

Inputs

A
L
L
H
H

B
L
H
L
H

H = high logic level
L = low logic level

A1

81

DM54ALS136 (J)

+ 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrlcal Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual·ln·Line Package
Vee

~

DM74ALS136 (N)

2-85

Y
L
H
H
L

•

Recommended Operating Conditions
Symbol

Parameter

DM54ALS136

DM74ALS136
Units

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

V

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.8

0.8

VOH

High Level Output Voltage

5.5

5.5

V

IOL

Low Level Output Current

4

8

mA

TA

Free Air Operating
Temperature

70

·C

2

V

2

-55

125

0

Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol

Parameter

Conditions

Typ
(Note 2)

Min

VI

Input Clamp
Voltage

Vee = Min,ll= -18 mA

leEx

High Level Output
Current

Vee = Min, Vo = 5.5V
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee=Mln
10L=Max
VIL=Max
VIH=Mln

II

Input Current at Max
Input Voltage

IIH

Max

Units

-1.5

V

100

f.lA

OM 54/74ALS

0.25

0.4

V

OM 74ALS

0.35

0.5

V

Vee = Max, VI=7V

0.1

mA

High Level Input
Current

Vee = Max, VI=2.7V

20

~

IlL

Low Level Input
Current

Vee = Max, VI=0.4V

Icc

Supply Current

Vee = Max (Note 2)

-0.1

mA

5.9

, mA

3.9

Switching Characteristics over recommended operating free air temperature range
DM54ALS136
Symbol

Parameter

Conditions

Min

Typ

DM74ALS136

Typ

. Units

Max

Min

20

55

20

50

ns

(Note 2)

(Note 2)

Max

tpLH

Propagation Delay Time,
Low to High Level Output

Vee = 4.5V to 5.5V,
RL=2 kll,
CL=50 pF

tpHL

Propagation Delay Time,
High to Low Level Output

Other Input Low

3

18

3

15

ns

tpLH

Propagation Delay Time,
Low to High Level Output

Vee=4.5V to 5.5V,
RL =2kll,
C L =50 pF

20

55

20

50

ns

tpHL

Propagation Delay Time,
High to Low Level Output

Other Input High

3

15

3

12

ns

Nole 2: Aillypicals are at vee = 5V, TA=25"e.
Nole 3: ICC Is measured with all Inputs at 4.5V and the outputs open.

2·86

,

r---------------------------------------------------------------~c

s:

~National

~

~ Semiconductor

~
....

-s:
Co)

......

DM54ALS137/DM74ALS137
3-Line to 8-Line Decoder/Demultiplexer
with Address Latches

c

~

roo
....

General Description

Co)

......

The ALS137 is a three-line to eight-line decoder/demultiplexer with latches on the three address inputs. When the
latch-enable input (GL) is low, the ALS137 acts as a decoder/demultiplexer. When GL goes from Ie to high, the address present at the select inputs (A, B, and C) is stored in
the latches. Further address changes are ignored as long
as GL remains high. The output enable controls, G1 and G2,
control the state of the outputs independently of the select
or latch-enable inputs, All of the outputs are high unless G1
is high and G2 is low. The ALS137 is ideally suited for implementing glitch-free decoders in strobed (stored-address)
applications in bus-oriented systems.

Features
•
•

Combines Decoder and 3-Bit Address Latch.
Incorporates 3 Enable Inputs to Simplify Cascading.

•

Low Power Dissipation ... 28 mW Typ.

•

Switching Specifications Guaranteed over Full
Temperature and VCC Range.
Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.

•

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS137
DM74ALS137
Storage Temperature Range

7V
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Connection Diagram
Dual·ln·Line Package

Inputs

Outputs

OATA OUTPUTS

vee
181

A

I

YO
15

YI
14

Y2
13

\

Y4

Y3
12

Enable

11

Y5

Y8

YI

Y2

Y3

Y4

Y5;~
Y8

C

GI

G2

GI

Y7

r1A:O

GL G1 G2 C

B

A

YO Y1 Y2 Y3 Y4 Y5 Y6 Y7

X
X

X
X

H
H

H
H

H
H

H
H

H
H

H
H

H
H

H
H

9

10

X
X

X

H

L

X

X
X

L
L
L
L

H
H
H
H

L
L
L
L

L
L
L
L

L
L
H
H

L
H
L
H

L
H
H
H

H
L
H
H

H
H
L
H

H
H
H
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
L
L

H
H
H
H

L
L
L
L

H
H
H
H

L
L
H
H

L
H
L
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
H
H
H

H
L
H
H

H
H
L
H

H
H
H
L

H

H

L

X

X

X

Output corresponding to stored
address, L; all others, H

L.
I

2

3

A
B
C
~
SELECT

4
GL

5

G2

8
61

'--------v-----

7
Y7
OUTPUT

:!o

ENABLE
TL/F/6202·1

54ALS137 (J)

Select

L

74ALS137 (J,N)

2-87

~

Low State, H

~

High State, X

~

Don't Care

~r-----------------------------------------------------------------------------~

~ Recommended Operating Conditions

.

...I



r-

15

4

TPLH

4

12

(,)

G2

......
\

TPHL

VCC = 4.5 to 5.5V
RL = 500 {l
CL = 50 pF.

TpLH

....

CJ)

5

18

5

15

5

21

5

17

5

19

5

15

7

27

7

22

7

25

7

20

G1
TpHL
TpLH
GL
TpHL
Note 1: See Section 1 for test waveforms and output load.

Logic Diagrams

,.:...l......~>_-r"'\

DATA

OUTPUTS

c'

=:t:t,

'--t=t'
"PUTS::~_

fNA8LE{GL 4

"
TLlF/6202·2

2-89

.....
('I)

....

en
.....



~
....

Co)

CO

~

.... Recommended Operating Conditions
~
~
Min
;! Parameter
::E
c

i....
~

Supply Voltage

Nom

Max

Min

Nom

Max

5

5.5

4.5

5

5.5

4.5

High Level Input Voltage, VIH

DM74ALS138

DMS4ALS138

2

V
V

2

Low Level Input Voltage, VIL

Unit

O.S

O.S

V

~

High Level Output Current, IOH

-0.4

-0.4

mA

c

Low Level Output Current, IOL

4

S

mA

Max

Unit

-1.5

V

:E

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25°C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.5V, II = -lSmA

VOH

High Level Output
Voltage

IOH= -0.4mA
VCC = 4.5 to 5.5V

Low Level Output
Voltage

VCC = 4.5V

VOL

Min

Typ

V

VCC-2
'.

54/74ALS
IOL = 4m~

0.25

0.4

V

74ALS
IOL = SmA

0.35

0.5

V

II

Max High Input Current

VCC= 5.5V, VIH = 7V

0.1

mA

IIH

High Level Input Qurrent

VCC = 5.5V, VIH = 2.7V

20

/lA

IlL

Low Level Input Current

VCC = 5.5V, VIL = 0.4V

-0.1

mA

10

Output Driv~ Current

VCC = 5.5V

-112

mA

ICC

Supply Current

VCC = 5.5V

10

mA

-30

Vo = 2.25V

5

Function Table
Enable
Inputs·

Select
Inputs

Outputs

G1

G2*

C

B

A

YO

Y1

Y2

Y3

Y4

YS

Y6

Y7

X

H

L
H
H
H
H.

X

X
X

X
X

X
X

L
L
L
L

L
L
H

L
H
L

H
H
L
H
H

H

H
H
H
H
L
H

H
H
H
H
H
L

H
H
H
H
H
H

H
H
H
H
H
H

L
L

L

H

H
H
H
H

H
H

H
H

L

H
H
H

H

H
H
H
H

L

H
H

H
H
H
H

H
H
H
H
H
H
L

H
H
H

H

H
H
H
L
H
H

H

L

H
H
H
H

L
L
L
L
L
L
L
L

H
H
H
H

L

H
H
H
H,
H

2·92

H
H
H

'H
H
H

H

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vcc =5V, TA = 25'C.
DM74ALS138

DM54ALS138
Parameter

From (Input)

Conditions

TpLH

Typ

Typ

Max

Min

6

27

6

22

6

22

6

18

4

20

4

17

5

20

5

17

Min

Max

A,B,C
VCC = 4.5 to 5.5V
RL = 500n
CL = 50 pF.

TpHL
TpLH

Enable
TpHL
Nate 1: See Section 1 for test waveforms and output load.

Logic Diagram

15 Yo

,....f

""

~
EIIABLE
INPUTS

{.~
GU 4

.,

13 Y2

r-- t::I

12Y3

~

ii •

r-r

.
.
'

SELECT
INPUTS

'

,3

DATA
OUTPUTS

~Y4

-t>o....

...

~"
-v

-"

...

......

...

K

1DY5

r-r

~YII

r-r

~ '"
Tl/L1611,·2

•

2-93

Unit

ns

.-r-----------------------------------------------~--------------------------------_,

It)

Cii
~National
...I
~
,...

::i

Q

a

Semiconductor

DM54ALS151/DM74ALS151

.It).- Data Selector/Multiplexer
~

~
::i
Q

8~Line

to 1-Line

General Description
This Data Selector/Multiplexer contains full on-chip decoding to select one-of-eight data sources as a result of a
unique three-bit binary code at the Select inputs. Two complementary outputs provide both inverting and non-inverting buffer operation. A Strobe input is provided which.
when at the high level. disables all data inputs and forces
the Y output to the low state and the W output to the high
state. The Select input buffers incorporate internal overlap
.features to ensure that select input changes do not cause
invalid output transients.

•
•

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
OM54ALS151
OM74ALS151
Storage Temperature Range
Lead Temperature
(Soldering. 10 seconds)

Features
•
•

Pin and Functional Compatible with LS Family
Counterpart.
Improved OutP'Jt Transient Handling Capability.

Advanced OXide-isolated. Ion-Implanted Schottky TTL
process.
Switching Performance is Guaranteed Over Full
Temperature and VCC Supply Range.

(Note 1)
7V
7V

-55~C

to 125·C
O·C to 70·C
-65°C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric value. defined In the
"Electrical Characteristics" table ar~ not guaranteed at the absolute
maximum ratings. The "Recommended Operating Condltlons"table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual-In-Line Package
Inputs

031~~--------~~

~VCC
15

02 2
DATA
INPUTS
01.

3

iJ4

14 05
DATA
INPUTS
13 D6

DO 4

OUTPUTY 5

OUTPUT W

STROBE S

....
....
"
A

t-

i

......

11 SELECTA

~

10 SELECTS

"

....

~GNO...!

\..

C
'---

\.t
....

9

B

A

S

X
L
L
L
L

X
L
L

X
L

H
L
L
L
L'
L
L
L
L

H
H
L
L
H
H

H
L
H
L
H·
L
H

H = High Level L = Low Level X = Oon't Care
DO thru 07 = the level of the respective 0 input

SELECT C

TL/F/6203·1

54ALS151 (J)

C

H
H
H
1i

12 07

A

Outputs
Strobe

Select

74ALS151 (J,N)

2-94

y
L
DO
01
02
03
04
05
06
07

W
H

DO
01
[)2

D3
04
05
[)6

D7

c

s:
en

Recommended Operating Conditions
DM54ALS151
Parameter
Supply Voltage, VCC
High Level Input Voltage, VIH
Low Level Input Voltage, VIL

DM74ALS151

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

Unit

-

V

C

V

2

~
en
.....
en
.....

r-

s:
~

0.8

0.8

V

High Level Output Current, 10H

-1

-2.6

mA

Low Level Output Current, 10L

12

24

mA

Max

Unit

l>
r-

en
.....
en.
.....

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25'C.
Symbol

Parameter

Conditions

Min

VIK

Input Clamp Voltage

VCC

= 4.5V, liN = -18mA

VOH

High Level Output
Voltage

VCC

= 4.5V, 10H = Max

VOL

'.

Low Level Output
Voltage

I OH = - 400 I'A, VCC = 4.5 to 5.5V
VCC

= 4.5V

2.4

Typ

--1.5

V
V

3.2

V

VCC-2

54ALS/74ALS
10L = 12mA

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

fII

II

Input Current at
Max Input Voltage

VCC

= 5.5V, VIN = 7V

0.1

mA

IIH

High Level Input Current

VCC

= 5.5V, VIN = 2.7V

20

I'A

IlL

Low Level Input Current

VCC

= 5.5V, VIN =

-0.1

mA

10.

Output Drive Current

VCC

= 5.5V, VOUT = 2.25V

-112

mA

ICC

Supply Current

VCC=5.5V

12

mA

MV
-30
7.5

Date Inputs = 4.5V
Select Inputs = 4.5V
Strobe Inputs = 4.5V

2-95

\

....
....

Lt)

~

j~

""

'_PUTI

D41f1

~

"

...

~

i

c
TL/F/6203·2

2-96

~National

a

Semiconductor

DM54ALS153/DM74ALS153 Dual 4-Line to 1-Line
Data Selector/Multipl.exer
General Description

Absplute Maximum Ratings

This Data Selector/Multiplexer contains full on-chip decoding to select one-of-four data sources as a result of a
unique two-bit binary code at the Select inputs. Each'of the
two Data Selector/Multiplexer circuits have their own separate Select, Data, and Strobe inputs and a non-inverting
output buffer. The Strobe inputs, when at the high level, disable their associated data inputs and force the corresponding output to the low stCjte. The Select input buffers
incorporate internal overlap features to ensure that select
input changes do not cause invalid output transients.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS153
DM74ALS153
Storage Temperature Range
Lead Temperature
(Soldering, 10 seconds)

Advanced Oxide-Isolated, lon-Implanted Schottky TTL
process.

•

Switching Performance is Guaranteed Over Full
Temperature and VCC Supply Range.

•

Pin and Functional Compatible with LS Family
Counterpart.

•

Improved Output Transient Handling Capability.

7V
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C
+300°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric. values defined In the

Features·
•

(Note 1)

"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function :"fable

Dual·ln·Line Package

STROBE GI

SELECT B

I

...

Z

...rlf

IC3..1

ICZoJ.
D~T~

INPUTS
1C1..3.

ICO.,!

DUTPUTYI 1

.....

....

15 STROBEGZ

~

.....

-

Select
Inputs

jlLvcc

)a..

14 SELECT ~

""

rB

B

i

i

A

A

i

i

~J
.......

GND..J

fLZC3

r - jlLzcz
DATA

Strobe

Output

B

A

CO

C1

C2

C3

G

y

X
L
L
L
L
H
H
H
H

X
L
L
H
H
L
L
H
H

X
L
H

X
X
X
L
H

X
X
X
X

X
X
X

X
X
X

L
H

X

X
X

L
H

H
·L
L
L
L
L
L
L
L

L
L
H
L
H
L
H
L
H

X
X
X
X
X
X

X

X

X
X
X

INPUTS

r - flLzCI

Select inputs A and B are common to both sections
H = High Level, L = Low Level, X = Don't Care

T~
...

~ZCO
9 OUTPUTYZ

TL/F/6204·1

54ALS153 (J)

Data Inputs

74ALS153 (J,N)

2·97

~r---------------------------~-------------------------------------------------------,
U')

....

~

c(

t!:

':!

-....
c

~

Recommended Operating Conditions
DM54ALS153
Pa.rameter
Supply Voltage, VCC

DM74ALS153

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V
V

U')

High Level Input Voltage, VIH

~

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Current, 10H

-1

-2.6

mA

Low Level Output Current, 10L

12

24

rnA

Max

Unit

-1.5

V

~:!
c

2

Unit

2

Electrical Characteristics over recommended operating free air temperature range,
All typical values an;! measured at Vcc =5V, TA = 25°C.
Symbol

Parameter

Conditions

Min

VIK

Input Clamp Voltage

VCC

=

4.5V,IIN

=

VOH

High Level Output
Voltage

VCC

=

4.5V, 10H

=

Max

10H = - 400 p.A, VCC = 4.5 to 5.5V
VOL

Low Level Output
Voltage

VCC

=

Typ

-18mA

4.5V

2.4

V

3.2

V

VCC-'2

54/74ALS
10L = 12mA

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

II

Input Current at
Max Input Voltage

VCC

=

5.5V, VIN

=

7V .•

0.1

mA

IIH

High Level Input Current

VCC

=

5.5V, VIN

=

2.7V

20

p.A

IlL

Low Level Input Current

VCC

=

5.5V, VIN

=

0.4V

-0.1

mA

10

Output Drive Current

VCC

=

5.5V, VOUT

-112

rnA

ICC

Supply Current

VCC=5.5V

14

rnA

=

2.25V

-30
7.5

Date Inputs = 4.5V
Select Inputs =4.5V
Strobe Inputs ='4.5V

2-98

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V, TA = 25°e.
DM54ALS153
Parameter

From

To

Select

Y

Conditions

tpLH, Low to high Level Output
tpHL, High to low Level Output
tPLH, Low to high Level Output
Data

Y

tpHL, High to low Level Output

Vee =
4.S to S.SV
eL = 50 pF
RL = SOO U

tpLH, Low to high Level Output
Strobe

Typ

DM74ALS153
Min

5

25

5

21

ns

5

25

5

21

ns

3

12

3

10

ns

4

18

4

15

ns

5

22

5

18

ns

5

22

5

18

ns

Note 1: See Section 1 for test waveforms and output load.

Logic Diagram
ICD

---"---<'I>'------=::t:::::lh
--!--------+-J::::j::=l1-'

IC'

-.!.--------F~$~D

DATAl

IC2

~f

Max

y

tpHL, High to low Level Output

STROBE IH

Typ

Unit

Max

Min

4

,:r-C>-1-----+-+

.co ...:::,"-------++:1:::::1=:::::lf--.,.

'e, -':.:..'-------++8±:::::lf--.,.
DATA 2

.e. -'::..'-------i:=t==I=::E::::::jh

'e3 ~'3=:;:====~!~~~b

STROBEG2_ 15

TLfF/6204·2

2-99

~National

PRELIMINARY

D Semiconductor
DM54ALS/DM74ALS157,158 Quad 2-Line to 1-Line
Data Selectors/Multiplexers
General Description
These data .selectors/multiplexers contain inverters and
drivers to supply full on-chip data selection to the four output gates. A separate strobe input is provided. A 4-bit word
is selected from one of two sources and is routed to the
four outputs. The ALS 157 presents true data whereas the
ALS 158 presents inverted data to minimize propagation
delay time.

Features
•
•

Switching Specifications at 50 pF.
SWitching Specifications Guaranteed Over Full
Temperature and VCC Range.
• Advanced OXide-Isolated, lon-Implanted Schottky TTL
Process.
• Functionally and Pin for Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.
•

Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.

•
•
•
•

Expand any data input point.
Multiplex dual data buses.
General four functions of two variables (one variable is
common).
Source programmable counters.

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS
DM74ALS
Storage Temperature Range

7V
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Rallngs" are those values bsyond
which the safety of the device can not bs guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratlngs:The "Recommended Operallng Conditions" table will
define the conditions for actual device operallon.

Function Table

Connection Diagram
Dual·ln·Llne Package
INPUTS

,..;....-Vcc STROBE 4A
"116

15

G

14

4A

13

4B

-

OUTPUT INPUTS

4B

4Y
12

4Y

3A

11

3A

1A

SELECT

Inputs

3Y

10

9

. 3B
3Y-

:--S

1

OUTPUT

3B

1B

3

2

1A

1Y

1B

tNPUTS

2A

4

1Y

2B

5

2A

6
2B

OUTPUT INPUTS

2Y

OutputY

Strobe

Select

A

B

ALS157

ALS158

H
L
L
L
L

X

X

L
L
H
H

L
H

X
X
X

X
X

L
H

L
L
H
L
H

H
H
L
H
L

H - High Level, L - Low Level, X - Don't Care

Is

7
2Y

GND

OUTPUT

TL/F/6205-1

54ALS157 (J)
54ALS158 (J)

74ALS157 (J,N)
74ALS158 (J,N)

This document contains Information on a product under development. NSC reserves the right to change or discontinue this product without notice.

2·100

c

:s:

Recommended Operating Conditions
DM54ALS157,158
Para.meter
Supply Voltage, VCC
High Level Input Voltage, VIH

DM74ALS157,158

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

2

Unit
V
V

Low Level Input Voltage, VIL

0.8

0.8

V

High level Output Current, 10H

-1

-2.6

mA

low level Output Current, 10l

12

24

mA

Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.5V, II = -18mA

VOH

High Level Output
Voltage

10H = - 0.4 mA, Vec = 4.5 to 5.5V

II

IIH

IlL

Max High Input Current

High Level Input Current

low level Input Current

Min

Vce

5.5V, VIH

Vec = 5.5V, Vil

10

Output Drive Current

Vce

= 5.5V

ICC

Supply Current

Vec

=

Max

Unit

-1.5

V
V

3.3

54/74ALS
10l = 12 mA

0.25

0.4

V

74AlS
10l = 24 mA

0.35

0.5

V

Aor B

0.1

mA

AlB orG

0.1

Aor B

20

AlB or G

20

= 5.5V, VIH = 7V

Vec =

Typ

Vec-2
2.4

10H=Max

= 4.5V

......

~
:I>

ren
.....

(J1

:-I
C

r-

Symbol

Vce

-:s:c
~

All typical values are measured at Vee = 5V, TA = 25'C.

low level Output
Voltage

~
.....
(J1

s:

Electrical Characteristics over recommended operating free air temperature range.

VOL

~

= 2.7V
= O.4V
Vo

5.5V

2·101

AorB

-0.1

AIBorG

-0.1

= 2.25V

-112

-30

,.,A

mA

mA

54/74AlS157

7.8

mA

54/7 4AlS 158

2.3

mA

en
.....

-s:
~
C

;r-

en
.....
(J1

CO

!~

Switching Characteristics over recommended operating tree air temperature range (Note 1).
All typical values are measured at Vee = 5V. TA = 25°C.

o-.J
SlROIE ~15-::.....-_ _ _ _0_..........J

TLIF16205·3

TLIF16205·2

2-102

~National

D Semiconductor
DM54ALS/DM74ALS160A, 161A, 162A, 163A
Synchronous Four-Bit Counters
General Description

Features

These synchronous presettable counters feature an internal
carry look ahead for application in high speed counting
designs. The ALS160A and ALS162A are four-bit decade
counters, while the ALS161A and ALS163A are four-bit
binary counters. The ALS160A and ALS161A clear asynchronously, while the ALS162A and ALS163A clear synchronously. The carry output is decoded to prevent spikes
during normal counting mode of operation. Synchronous
operation is provided by having all flip-flops clocked
simultaneously so that outputs change coincident with
each other when so instructed by count enable inputs and internal gating. This mode of operation eliminates the output
counting spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of
the clock input waveform.

•
•

These counters are fully programmable, that is, the outputs
may be preset to either level. As presetting is synchronous,
setting up a low level at the load input disables the counter
and causes the outupts to agree with set up data after the
next clock pulse regardless olthe levels of enable input. Low
to high transitions at the load input are perfectly acceptable
regardless of the logic levels on the clock or enable inputs.
The ALS160A and ALS161A clear function is asynchronous.
A low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load or enable
inputs. These two counters are provided with a clear on
power-up feature. The ALS162A and ALS163A clear function
is synchronous; and a low level at the clear input sets all four
of the flip-flop outputs low after the next clock pulse,
regardless of the levels of enable inputs. This synchronous
clear allows the count length to be modified easily, as
decoding the maximum count desired can be accomplished
with one external NAND gate. The gate output is connected
to the clear input to synchronously clear the counter to all
low outputs. Low to high transitions at the clear input of the
ALS162A and'ALS163A are also permissible regardless of
the levels of logic on the clock, enable or load inputs.

•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
Advanced Oxide-Isolated, lon-Implanted Shottky TTL
Process.
Functionally and Pin For Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.

•

Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.

•
•
•

Synchronously programmable.
Internal look ahead for fast counting.
Carry output for n-bit cascading.

•
•

Synchronous counting.
Load control line.

•

ESD inputs.

Absolute Maximum Ratings

(Note 1)
7V
7V

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS
DM74ALS
Storage Temperature Range

-55·C to 125·C
O·C to 70·C
-65·C to 150·C

Nota 1: The "Absolute Maximum Ratings" are those values beyond

which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametriC values defined in the

"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram
Dual-In-Line Package
RIPPLE
CARRY
VCC OUTPUT OA

The carry look ahead circuitry provides for cascading
counters for nbit synchronous application without additional gating. Instrumental in accomplishing this function
are two count enable inputs (P and and a ripple carry output. Both count enable inputs must be high to count. The T
input is fed forwllrd to enable the ripple carry output. The ripple carry output thus enabled will produce a high level output pulse with a duration approximately equal to the high
level portion of QA output. This high level overflow ripple
carry pulse can be used to enable successive cascaded
stages. High td low level transitions at the enable P or Tinputs of the ALS160A through ALS163A may occur regardless
of the logic level on the clock.

OUTPUTS
OB

Oc

00

ENABLE
T
LOAD

10

9

n

RIPPLEOA
CARRY
OUTPUT
CLEAR
. CK

OB

Oc
LOAD

A

B

C

CLEAR CLOCK A

B

C

B

2

The ALS160A through ALS163A feature a fully independent
clock circuit. Changes made to control inputs (enable P or T,
or load) that will modify the operating mode will have no effect until clocking occurs. The function of the counter
(whether enabled, disabled, loading or counting) will be dictated solely by the conditions meeting the stable set-up and
hold times.

DATA INPUTS

54ALS160A (J)
54ALS161A (J)
54ALS162A (J)
54ALS163A (J)
2-103

ENABLE
0
P

0 ENABLEGND
P
TL/F/6206-t

74ALS160A (J,N)
74ALS161A (J,N)
74ALS162A (J,N)
74ALS163A (J,N)

Recommended Operating Conditions
DM54ALS
160A, 161A, 162A, 163A

Parameter

Supply Voltage

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

Low Level Input Voltage, VIL
High Level Output Current, IOH

0.8

-0.4

-6.4

25

0

tSETUP, Set-Up Time Data;
A,B,C,D

V

0

V
mA

8

mA

30

MHz

201

151

ns

251

201

ns

301

251

ns

201

151

ns

ILow

201

151

ns

!High

101

101

ns

IALS160A/161A
IALS162A/163A

Load
Clear (Only for
162A and 163A)

0.8

4

Low Level Output Current, IOL
Clock Frequency, fCLOCK

Unit

V

2

2

High Level Input Voltage, VIH

En P, Enl

DM74ALS
160A, 161A, 162A, 163A

Set-Up 1
(Only for 160A
and 161A)

Clear Inactive

10

4

10

4

ns

tHOLD, Hold Time

Data;
A,B,C,D

01

-3

01

-3

ns

En P, En T

01

-3

01

-3

ns

Load

01

-4

01

-4

ns

Clear
(Only for 162A and 163A)

01

-7

01

-7

ns.

-4

0

-4

ns

Hold 0
(Only for 160A
and 161A)

Clear

0

Width of Clock or
Clear Pulse, tw

CLK High or Low

20

16.5

ns

ALS160A/161A
CLR Low

20

15

ns

20

15

ns

Width of
Load Pulse

Note 1: The symbol (t) indicates that the rising edge of the clock Is used as reference.

2·104

~-------------------------------------------------------------'C

Electrical Characteristics
All typical values are measured at Vce
Symbol

s::
en

over recommended operating free air temperature range.

Parameter
Input Clamp Voltage

VCC = 4.5V, II = -18mA

VOH

High level Output
Voltage

10H = -O.4mA
VCC = 4.S to 5.5V

VOL

low level Output
Voltage

VCC

High level Input Current

VCC = 5.5V.
Vil = O.4V

Output Drive Current

VCC

=

5.5V

ICC

Supply Current

VCC

=

S.5V

v
V

~

r-

.....

4.5V

10

Unit

C/)

VCC = 5.5V
VIH = 2.7V

low level Input Current

Max
-1.5

VCC-2

VCC = 5.5V,
VIH = 7V

Max High Input Current

Typ

Min

Conditions

=

-cs::
~

=SV, TA =2S·C.

54/74AlS
10l = 4mA

0.25

0.4

V

74AlS
10l = 8mA

0.35

0.5

V

lOAD, ClK
ENT

0.2

mA

Others

0.1

DATA. ClR. EN P

20

elK. lOAD. EN T

40

}>

p.A

-0.1

lOAD.ENT

-0.2

=

2.25V

C

s::
en

-s::
~

c

~

r-

C/)

.....
en
.....

DATA. ClR.
ClK. EN P

Vo

en
o

mA

}>

c
-30
12

s::

en

-112

mA

21

mA

afJI
s::
~

r-

Switching Characteristics

C/)

.....

over recommended operating free air temperature range (Note 1).

en

All typical values are measured at Vee = 5V, T A = 25·C.

N

DM54ALS
160A, 161A, 162A, 163A
Parameter

From

To

Conditions

Min

Typ

Max

}>

DM74ALS
160A, 161A, 162A, 163A
Min

Typ

Max

C

Unit

s::
en

-s::c
~

fmax.
Max. clock freq.
TplH. Propagation
delay time. low to
high level output.

Clock

TpHl. Propagation
delay time. High to
low level output.
TplH. Propagation
delay time. Low to
high level output.

Ripple
Carry

TpLH. Propagation
delay time. Low to
high level output.
(Only for 160A, 161A)

En T

8

26

ns

8

30

7

25

7

23

ns

4

18

4

15

ns

6

20

6

17

ns

3

16

3

13

ns

3

20

3

17

ns

~

»r-

C/)

VCC ~ 4.5
to 5.5V
RL = 500 U
CL = 50 pF

Clock

TpHl. Propagation
delay time. High to
low level output.

MHZ

30

25

Ripple
Carry

TpLH, Propagation
delay time. Low to
high level output.
(Only for 162A, 163A)
2-105

.....

en
(,,)

»

~ Switching Characteristics (Continued) over recommended operating free air temperature range (Note 1).

CD
~

en
...I

All typical values are measured at Vee = 5V, TA = 25·C.
DM54ALS
160A,161A,162A,163A

c(

~

Parameter

-c

::i

~
::i

c

~

. From

To

TpHL. Propagation
delay time. Low to
high level output.

En T

Ripple
Carry

TpHL. Propagation
delay time. High to
low level output.
(Only for 160A, 161A)

Clear

Conditions

Typ

DM74ALS
160A, 161A, 162A, 163A

Typ

Max

Min

3

16

3

13

ns

Any Q

8

27

8

24

ns

Ripple
Carry

11

31

11

28

~

en

...I

Nole I: See Section 1 for test waveforms and output load .

~

::i Logic Diagrams

c

"'I:t

U)

:IE

ALS160A

C

~~J
\.1
, _ .. .

"

C

Unit

Max

Min

=tY-

"

RIPPLE
CARRY

TLI F16206·2

2·106

c

s::
en

Logic Diagrams (Continued)

-s::
olio

C

ALS161A

~
»
r-

en

...A.

0)

C

14 0"

~
C

DATAA 3

s::
en

-s::

.0li0

C

~

»
r-

DATAB 4

en

CLEAR I

...A.

0)
...A.

~
CLOCK

C

2

"
BATIIC

Oc

s::
en

-s::

5

olio

C

~
»
r-

LOAD 9

en

ENP 1

...A.

0)
I\)

DATA 0 6

~
IS

RIPPLE
CARRY

ENl lO

C

s::
en

-s::
olio

TLlF/6206·3

C

~

»
ren
...A.

0)

W

»

2·107

•

DM54/DM74ALS160A, DM54/DM74ALS161A, DM54/DM74ALS162A, DM54/DM74ALS163A
r-

'cc;"8
c

S

~

a

~

-~

~

i

-, I~ ~

tJ

s

5

~

,'7

::

a

N

iii"

ce

~

~

;

,

3

(I)

''7

'0
o
;:l
5"

I~~

c:

~

I .-+---+-I+-I-H-+.......,
):0.

r-H---If++I-If++++..........

. )J~.)

~

~

)

r

)

L...---....l>~: :

L.-

'-----t

'7

:!)

U;

jl"

;!

~

~.

L-

e
~

!!i

=
Ii'

.

4~

:I --f:, L] - 4:, L.]

L~'7

, '7

;: ;

w

If

Ii'

~

7:;:
~

c

s:
en

Logic Diagrams (Continued),

-s:
~

C

ALS163A

~

»
r
en

14O"

""'m"
Q

]>

DATA" 3

C

s:en

-s:
~

13

Oa

C

~
»
r

DATA B 4

en

CLOCK 2

"
DATA C 5

""'"
m
""'"
]>

,.
-

C

s:
en
~

C

LOAD
11 00

15 RIPPLE
CARRY

'.

10

s:
~
»
r
en

""'m"
I\)
]>
C

TL/F/6206-5

s:
en

~

C

s:
~
»
r
en

""'"
m

~

2-109

~

~

PRELIMINARY

II?'A National

~ Semiconductor
::& DM54ALS165/DM74ALS165 a-Bit Paralielln/Serial Out
c
is Shift Register

C1I

ns

-55

C1I

C

MHz

Data

TA

~
....

ns

SH/lD

....
en

mA

ClK low
tsu

r-

CJ)

en

DM54ALS165/DM74ALS165

i5"
c

Ai"

ea

;

3
PARALLEL

INPUTS

~
~

N

Timing Diagram

Typical Shift, Load, and Inhibit Sequences

elK

elK INH

SER

INHIBIT--1-----------

lOAD

TL.lFI6712-3

2-113

~

PRELlMI'NARY

~ ~National
« ~ Semiconduc~r
t!:
~

is....

DM54ALS166/DM74ALS166 8-J:lit Parallel Load
Shift Registers

~ General Descrip~ion


o

Data;
A,B,C,D

Width of Clock Pulse, TW

10

~

PI

Vce = 5.5V, Vo = 2.25V

-0.2
-30
15

Vec = 5.5V

Note 1: The symbol (1) Indicates that the rising edge of the clock Is used as reference.

2-119

-112

mA

25

mA

~fJI

ren
.....

m
m

m

m·
Ci.i

Switching Characteristics over recom~ended operating free air temperature range (Note 1).
All typical values are measured at Vcc = 5V, TA = 25°C .

...J

~

::2

-,..
c

m
en

CD

en

...J
Lt)
==

::2

c

mOO

DM54ALS168B,169B
Parameter

From

To

Conditrons

Min

fmax,
Max. clock freq.
TpLH, Propagation
delay time. Low to
high level output.
TpHL, Propagation
delay time. High to
low level output.
TpLH, Propagation
delay time. Low to
high level output.

Typ

Max

25

Clock

Clock

Ripple
Carry

AnyQ

VCC = 4.5
to 5.5V
RL = 500 I}
CL = 50 pF

DM74ALS168B,169B
Min

Typ

Unit

Max

MHz

30.

3

15

3

13

ns

6

22

6

18

ns

2

15

2

13

ns

,..

TpHL, Propagation
delay time. High to
low level output.

5

20

5

16

ns

~
::2

TpLH, Propagation
delay time. Low to
high level output.

2

15

2

12

ns

m

TpHL, Propagation
delay time. High to
low level output.

3

16

3

13

ns·

5

21

5

18

5

2'1

CD

en
...J

c

00
CD

,..

en
...J

TpLH, Propagation
delay time. Low to
high level output.

==
::2

TpHL, Propagation
delay time. High to
low level output.

Lt)

c

EnT

Ripple
Carry

ufo
(Note
2)

Ripple
Carry

ns
\

5

18

ns

NOTE 1: Se~ Section 1 for test waveforms and output load.
NOTE 2: Propagation delay time from up/down to ripple carry must be measured with the counter at either a minimum or a maximum count. As the logic level
of the up/down input is changed, the ripple carry output will follow. If the count is minimum (0), the ripple carry output transition will be in phase. If the count is
maximum (9 for ALS168B or 15 for AlS169B), the ripple carry output will be out of phase.

2-120

-------------------------------------------------------1
Logic Diagrams
DM54ALS/DM74ALS168B

r-

oo
....
Q)

co

UfU

-s:
ttl
C

~

»
roo
....
Q)

co
CLOCK
DATAA

ttl

====>O-~+~=~=--------~=~t~~=i

C

s:
U1
»
roo
....
.j::oo

54ALSI68
4BITDECAO£
UPIDDWNCDlJNHR

Q)

co

-s:
ttl
C

~

r-

oo
....
Q)

co
ttl

OATH

.2..._ _ _ _ _

~~£~~~=~~===:[)

LOAD

OAiAD

EN!'

IU

15

"I

fleD

~==~~~--------------TLlF/6207-2
2-121

m

~
,...
en
...J

Logic Diagrams (Continued)
DM54ALS/DM74ALS1698

~

:E

o

U/O

1

...

....

1 ....

:

...

iii
~
,...

en

...J

I

:E

c

.

L.d

OATAA

"

14

....

OA

"....

13

Lnl~"

==

II)

m-

aCeSL

3

~r-

OO

,...
en
...J
CD

CLOCK

2

"v

~

~

:E

-,...
c

~l~~r
-

S4AlS lli9
4 BIT BINARY
UP/DOWN COUNTER

m
00

CD

en
...J

OAns

4

==

Et:r--

~l-

~

~l-

II)

:E

c

DATAC

ENP

7

12
QC

LO!~~r

5

LOAD 9

os

...."

....

....

~

~
....
00

li>1~"
~r-

r'--"

L

6

..d.

DATA 0

~
EMf

10

"

-

15

L

'--

RGD

"'"'"'

I
TL/F/6207-3

2-122

c

s::

~National

U'I

>
r-

D Semiconductor

OO
.....

......

-s::

DM54AlS/DM74AlS174,175
Hex/Quad D Flip-Flops with Clear
General Description
These positive-edge-triggered flip-flops utilize TTL circuitry
to implement D-type flip~flop logic. Both have an asynchronous clear input, and the quad (175) version features complementary outputs from each flip-flop.
Information at the D inputs meeting the setup time requirements is transferred to the outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is
at either the high or low level, the D input signal has no effect at the output.

a

Features
•
•

Advanced Oxide-Isolated lon-Impianted Schottky TTL
Process.
Pin and Functional compatible with LS family
counterpart.

.;:;.

C

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Free Air Temperature.Range
DM54ALS174/175
DM74ALS174/175
Storage Temperature Range
Lead Temperature
(Soldering, 10 seconds)

06

05

05

04

CLEAR

01

01

02

02

03

CLOCK

03

GNO

'"

••

TLlLl6112-1

74ALS174 (J,N)

54ALS174 (J)

54ALS175 (J)

Function Table
Outputs

Inputs'
Clear

Clock

L
H
H
H

X

X

I

H
L

L

X

D

.

Q

G*

L
H
L

H
L
H
00

aO

C

s:

U'I

>
r-

(Note 1)
7V
7V

-55°C to 125°C
DoC to 70°C
-65°C to 150°C

H ~ high level (steady state)
L ~ low level (steady state)
X = don't care
T = transition from leVi to high level
Qo ~ th~ level of Q before the Indicated
steady-state input conditions were
established.
- applies to 54ALS175/74ALS175 only

2-123

D1

'3

"

"

"

74ALS175 (J,N)

OO
.....

......

-s::
U?

C

~

:J>

Dual-In-Line Package
Q4

......

~,f:>.

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual-In-Line Package
06

r-

OO
.....

a

Connection Diagrams

Vce

~

:J>

• Typical clock frequency maximum is 80 MHz.
• Switching performance guaranteed over full
temperature and VCC supply range.
• 54ALS174 contains six flip-flops with separate D
inputs and a outputs.
• 54ALS175 contains four flip-flops with separate D
. inputs and both and Q outputs.

CLOCK

'"
TLlLl6112-2

~fII
~

~
T""

~

«
t!

:::E

-c

Recommended Operating Conditions
DM74ALS174,175

DM54ALS174,175
Parameter
Supply Voltage, VCC

~

High Level Input Voltage, VIH

~

. Low Level Input Voltage, VIl~

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

Unit
V
V

2

T""

0.8

0.8

V

-0.4

mA

~:::E

High Level Output Current, 10H

-0.4

c

Lpw Level Output Current, 10L

4

"t

Pulse Width, tw

Clock
High or Low

8

12.5

10

Clear
Low

15

10

Data Input

151

101

Clear
Inactive State

81

61

Data Hold Time, tHOLD (Note 1)

01

01

~

Clock Frequency, fCLOCK

0

",0

Note 1: The.symbol

T""

~

«
t!

:::E

Setup Time, tSETUP (Note 1)

c

~
en
. ...I

mA
. ns

ns

T""

:::E

40

ns

0

50

MHz

Max

Unit

-1.5

V

I Indicates that the rising edge of the clock Is used as reference.

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at'Vee= 5V, TA = 25°C.
Symbol

Parameter

Conditions

VIK

input Clamp Voltage

VCC=4.5V, liN = -18mA

. VOH

High Level Output
Voltage

10H= -400/LA
VCC = 4.5 to 5.5V

VOL

Low Level Output
Voltage

VCC

=

4.5V

Min

Vce- 2

Typ

V

Vee-1.6

10L

=

4mA

DM54/74

0.25 .

0.4

10L

=

8mA

DM74

0.35

0.5

V

II

Inp'ut Current at
Max Input Voltage

VCC

=

5.5V, VIN

=

7V

0.1

mA

IIH

High Level Input
Current

Vce

=

5.5V, VIN

=

2.7V

20

/LA

IlL

Low Level Input
Current

Vec

=

5.5V, VIN

=

O.4V

-0.1

mA

Output Drive Current

VCC

=

5.,sV, V

-112

mA

Supply Current

VCC=·5.5V
Clock=4.5V
Clear=GND
D Inputs = 4.5V

mA

I 10·

ICC

.

=

-30

2.25V

2·124

ALS174

11

19

ALS175

8

14

--------------------------------~----------------------------------.c

s:
tr-

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vcc

(It

=5V. TA =25°C.
54ALS174,175

Parameter

Conditions

fMAX. Maximum
Clock Frequency

RL = 500n
CL = 50pF

40

tPLH. Propagation Delay Time.
Low to high Level Output
From Clear (175 Only)

RL = 500 n
CL = !?OpF

5

tpHL. Propagation Delay Time.
High to low Level Output
From Clear

RL = 500 n
CL = 50pF

8

tPLH. Propagation Delay Time.
Low to high Level Output
From Clock

RL = 500 n
CL = 50pF

3

tpHL. Propagation Delay Time.
High to low Level Output
From Clock

RL = 5110 n
CL = 50pF

5

Min

Typ

74ALS174,175
Max

Min

Typ

Unit

Max

50

20

MHz

5

18

ns

en
~

~

c

s:

~
l>

r-

en

-...
~

26

8

ns

23

c

s:
17

15

3

ns

20

17

5

ns

2

01

01

DI

CLEAII

CLEAR

Q

01

02

02

D2
CLOCK

.

02

CLEAR 'ij

•
D3

12

0

10

03

CLOCK

"

10

11

II

Q4

CLEAR

D4
05

13

CLOCK

15

13

03

Q4

CLDCK
14
CLEAR 'ij

Q4

CLEAR

"

..

15

TLlF/6112·4
O.

54ALS175/74ALS175

CLOCK

CLOCK

CLEAR
CLEAR

1

TLlF/6112·3

54ALS174/74ALS174

2·125

lii
-...

..Ao

(It

CLOCK

5

~

~
l>

CLOCK

". •

.-s:c
-...

(It

Logic Diagrams
1\

ten
r-

Nota 1: See Section 1 for test waveforms and output load.

DI

~

~
en

~-----------------------------------------------------------------------------------,

~ ~National

~ ~ Semiconductor
~ DM54ALS190JDM74ALS190, DM54ALS191J DM74ALS191
,..~ Synchronous 4·Bit UpJ Down Decade and Binary Counter
~ General Description

~

::i

c

g
~

~


r-

8

30

8

25

f1s

en
....
CD

5='

O·
G

RCO

t pHL , Propagation
Delay Time, High
to Low Level
Output

4

21

4

18

ns

4

21

4

18

ns

s:

U1

~
ren
....

-s:....
CD

o

~

l>

~
....

Note 1: See Section 1 for test waveforms and output load.

Note 2: All typical values are at

Vee =5V, TA =25"e.

CD
....

2-129

-'
---

_r-----------------------------------------------~-----------------------------

CD

o...I Logic Diagrams (positive logic)
~
.....

ALS190

:!

(12)

c

I
~RCD

C J)

(13)

o...I
~

,~

ffiij

::E
Q

g

-

.~

MAl(fMI~

(4)

DIU

~<>-

ClK

1!!Lt>

I

~-~

~

1~~~'~,----+4~

~~~~----~LJ)--

 Cl

Q

H

i

-

. A,

~

"""'"

.......

<
'lit.

10

~fI
J
I""-

it)

s

:E

c

]~~
'

~ 0..

~ lie

Cl

"""'"

lD

~

~fl

..A,
~

T
~
S

(10)

~

~

~ Dc

Cl

"""'"

lD

~tti~~~+---~~--~..A--_~~~~
~-

Ttt1;::t::t:I:t:t:t::[:)i>------++l---:..-----...:...+-.ofs

.;,;(9.:..)

---

,-

- I
~Oo
(7)

-

L-~~~~-+------4----..A--,--~~~
~
Pin numbers shown are for J and N packages.

,

1
TL/F/6208-2

2-130

c

s:

logic Diagrams (Continued) (positive logic)

~

ALS191

&;
....

I

CO

(12)

}--'---~MAX/MIN

ec

s:
~

---rJ"o...

:J>

1 .........~

&;
....

~~(4~)_ _-i~~~~r+~+'~1~1~"_
-~-~~.I~
__~
D/jj~o--

-----v

CO

P
c

s:

L....----o:~I)_

U1

14)

CLK ~ O--~~~~-r~r---------------~-r~r---------------'

t

.....

r

en
....

CO
....
C
s:

~

:J>
r

en
....

....
CO

S
---Dc
~T--1~::t:~~tt:1=::[=)o----------t+t------------------t-of~
(6)

~~~~r-~~------H~l
.I
S
---Do
~T--1~::t:~~tt:1=::[=)o----------t+t-------~---------t-of~
(7)

1.....0

Cl

L----------~~?I---------T__-----~---.---~~~
""'I"
Pin number. shown are for J and N packages.

I
TL/F/62OB·3

2-131

!II

~ r-----------------~----------------------------------------------------------------------_,

en
~

~

Timing Diagrams

«

~

'ALS190 Typical Load, Count, and Inhibit Sequences

::e
c

Illustrated below Is tlte following sequence:

~

1. Load (preset) to BCD seven.

0)
~

~

~

2. Count up to eight, nine (maximum), zero. one, and two.

3. Inhibit.
4. Count down to one, zero (minimum), nine, eight, and seven.

::e
c

i

~
«
~
::e
c

A

B

i

C

~

r-

0

~

::e
c

~

L.

U)

...I

-

L.

DATA
INPUTS

CLOCK

DIU

Cffij

QB

OUTPUTS

MAXIMIN

.....,
9

2

.jl••-INHIBIT

i-----""'COUNT U P - - - -......

I--------~.:-~
TUF/620&-4

2-132

r--------------------------------------------------------------------------.c
s::
C1I

Timing Diagrams (Continued)

tr-

'ALS191 Typical Load, Count, and Inhibit Sequences

en
....
CD

!2

Illustrated below is the following sequence:

c

1. Load (presel) to binary thirteen.

s::

2. Count up to fourteen, fifteen (maximum), zero. one, and two.
3. Inhibit.

~
r-

l>

4. Count down to one, zero (minimum), fifteen, fourteen, and thirteen.

en
....

CD

P

c
A

I..

.-

s::

~

-

r-

en
....

DATA
INPUTS

....

CD

C

I..

s::

~
l>

I..

~
....

....

ClK

CD

DIU

ffiN

IIA

aB

---,

OUTPUTS

,- ......
ac
aD

......

MAXIMIN - - - ,

m

_......
I

13

~

14

2

15
COUNT UP

-I-

15
INHIBIT

14

13

I------CDUNT DDWN------I

lOAD
TL/F/620B·5

2·133

~

~ ~National


• Functional and pin compatible with the DM54/74LS
counterpart
• Improved switching performance with less power
dissipation compared with the DM54/74LS counterpart
• SWitching response specified into 500n and 50 pF load
• Switching response specifications guaranteed over
full temperature and Vee supply range
• PNP input design reduces input loading
• Low level drive current:
54ALS = 12 mA, 74ALS =24 mA, 74ALS-1 =48 mA

~bsolute

Maximum Ratings

Supply Voltage, Vee
Input Voltage
Output Voltage
Storage Temperature Range

7V
7V

5.5V

+ 150'C

• Advanced low power oxide·isolated ion-implanted
Schottky TTL process

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagrams

Function Table

Features

Dual-In-Line Package

Dual-ln·Line Package

16

20

Vee

16

20

Vee

1A1

19

26

1A1

19

2G

2Y4

18

1Y1

2Y4

18

1Y1

1A2

17

2A4

1A2

17

2A4

G

G

Data
Buffer
Output

H
L

L
H

Active
TRI-STATE

2Y3

16

1Y2

2Y3

16

1Y2

1A3

15

2A3

1A3

15

2A3

2Y2

14

1Y3

2Y2

14

1Y3

1A4

13

2A2

1A4

13

2A2

2Y1

12

1Y4

2Y1

12

1Y4

11

2A1

GND

11

2A1

GND

1D
TOP VIEW

TLIF/6210-1

DM54ALS240A (J)
DM74ALS240A (J, N)

10

TLIF/6210-2

TOP VIEW

DM54ALS241A (J)
DM74ALS241A (J, N)

2-141

Enable
Input

j
tJ

:s::
C11

$:

r

~
.....

l>

(Note 1)

- 65'Cto

r

tJ

:s::

~

r'

~fJI

l>

Recommended Operating Conditions
Symbol
Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

10H

High Level Output Current

10L

TA

DM54ALS240A,241A

Parameter

Min
4.~

DM74ALS240A, 241A .

lYP

Max

Min

1YP

Max

5

5.5

4.5

5

5.5

2

Units
V
V

2
0.8

0.8

-12

-15

mA

Low Level Output Current

12

24

mA

DM74ALS240A·1, DM74ALS241A-1

-

48

mA

70

·C

Operating Free Air Temperature

-55

125

0

V

Electrical Characteristics over recommended operating free air temperature range(unless otherwise specified)
Symbol

Parameter

Conditions

VIK

iput Clamp
Voltage

Vee = 4.5V, 11= -18mA

VOH

High Level
Output

Vee = 4.5V to 5.5V 10H= -0.4mA
Vee = 4.5V

Low Level
Output Voltage

DM74ALS240A,241A

Min

Min

Typ

Max

Typ

-1.5

10H= -3mA
10H=Max

VOL

DM54ALS240A,241A

Max
-1.5

Units
V

Vee- 2

Vee- 2

V

2.4

2.4

V

2

2

V

Vee=4.5V
10L = 54ALS (Max)

0.25

0.4

0.25

0.4

10L = 74ALS (Max)

-

-

0.35

0.5

V

0.1

0.1

mA

20

20

p.A

-0.1

-0.1

mA

-112

mA

V

Input Current at
Max Input
Voltage

Vee=5.5V, VI =7V

IIH

High Level
Input Current

Vee = 5.5V, VI=2.7V

IlL

Low Level Input
Current

Vee = 5.5V, VIL=0.4V

10

Output Drive
Current

Vee = 5.5V, Vo=2.25V

10ZH

High Level
TRI·STATE
Output Current

Vee = 5.5V, Vo=2.7V

20

20

p.A

10ZL

Low Level
TRI·STATE
Output Current

Vee =5.5V, Vo=0.4V

-20

-20

p.A

Icc

Supply Current

Vee = 5.5V, ALS240A
Outputs High

II

,

-30

-112

,

-30

4

10

4

10

mA

Outputs Low

13

23

13

23

mA

Outputs TRI·STATE

14

25

14

25

mA

Vee = 5.5V, ALS241A
Outputs High

9

17

9

15

mA

Outputs Low

15

28

15

26

mA

Outputs TRI·STATE

17

32

17

30

mA

2·142

'ALS240A Switching Characteristics over recommended operating free air temperature range
Parameter

From
(Input)

To
(Output)

tpLH

A

Y

tpHL
tPZH

y

G

tPZL
tpHz

54ALS240A

Conditions

Min

V cc == 4.5V to 5.5V,
C L =50pF,
R1 =5000,
R2 = 5000,
T A = Min to Max

tpLZ

Max

Min

Typ

Units
Max

2

12

2

9

ns

2

11

2

9

ns

5

15

5

13

ns

5

20

5

18

ns

2

12

2

10

ns

3

18

3

12

ns

y

G

74ALS240A

Typ

'ALS241 A SWitching Charact~ristics over recommended operating free air temperature range
Parameter
tpLH

From
(Input)

To
(Output)

A

Y

tpHL
tPZH

1G

y

1G

Y

tPZL
tpHZ

Min
Vee = 4.5V to 5.5V,
C L =50 pF,
R1 =500n,
R2=500n,
T A = Min to Max

tpLZ
tPZH

y

2G

tpzL
tpHZ

Y

2G

74ALS241A

54ALS241A

Conditions

tpLZ

Typ

Max

Typ

Min

Units
Max

3

14

3

11

ns

3

13

3

10

ns

7

25·

7

21

ns

7

25

7

21

ns

2

12

2

10

ns

3

20

3

15

ns

7

25

7

21

ns

7

25

7

21

ns

2

12

2

10

"s

3

20

3

15

ns

Logic Diagrams
DM54174ALS241A

DM54174ALS240A

lG.!...o[>-

lil..!..ol>--

lAl.y:>::

lA2.y:>::

m.y:>::

lA4 8

lAl~
lA2~

18 lYl

16 1Y2

14 1Y3

lA3y>=

~IY4

1114 8

2il~

2Al~
- 2A2~

18 1Yl

16 lY2

14

lY3

12 1Y4

2G~
9

2Al~
2A2~

2Yl

7 2Y2

2A3~

5 2Y3

2A4~

3 2Y4
TUF/6210·3

2·143

2A3~
2A4~

9

7

5

2Yl

2Y2

2Y3

3 2Y4
TLlF162,0-4

~National

~ Semiconductor
DM54ALS242A/DM74ALS242A,
DM54ALS243A/DM74ALS243A
Quad Bi~Directionaf Bus .Drivers
General Description
These octal TRI-STATE@ bus drivers are designed to provide ' • Functional and pin compatible with the DM54/74LS
the designer with flexibility in Implementing a bus interface
counterpart
with memory, microprocessor, or communication systems. • Improved. switching performance with less power
The ALS242A has inverting buffers, while the ALS243A has
dissipation compared with the DM54/74LS counterpart
non-inverting buffers. The direction enable gating is con• Switching response specified into 5000 and 50 pF load
figured with separate control over either buffer direction
and the two control buffers are complementary. Connect- • Switching response specifications guaranteed over
full temperature and Vee supply range
ing these control' inputs to one common line implements
single line direction control, while individual control can put • PNP input design reduces input loading
both buffer directions into TRI-STATE simultaneously • Low level drive current:
54ALS= 12 mA, 74ALS=24 mA, 74ALS-1 =48 mA
(disabled state) or put both buffer directions into the active
state (data latch state). The TRI-STATE circuitry contains a
Absolute Maximum Ratings (Note 1)
feature that maintains the buffer outputs in TRI-STATE (high
impedance state) during power supply ramp·up or ramp- Supply Voltage, Vee
7V
down. This eliminates bus glitching problems that arise
Input Voltage
during power-up and power-down.
7V
Dedicated Inputs
The -1 versions of the DM74ALS devices are identical to
5.5V
1/0 Ports
their standard versions except that the recommended
- 65·C to + 150·C
Storage Temperature Range
·maximum 10l is increased to 48 mAo There are no -1 verNote 1: The "Absolute Maximum Ratings" are those values beyond
sions of the DM54ALS devices.

which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Features
• Advanced low power oxide-isolated ion-implanted
Schottky TTL process

Connection Diagram

Dual-In-Line Package
nA8- 1

u

14 I""" Vee

13 --G8A

NC- 2

Al- 3

12 -NC

A2- 4

11-81

A3- 5

10 -82

A4- 6

9 1"""83

GNO- 7

8 -84
TLlF/6211-1

,TOP VIEW

DM54ALS242A (J)
DM54ALS243A (J)

DM74ALS242A (J, N)
DM74ALS243A (J, N)

Function Table

,

Inputs
GAB

GBA

L
H
H
L

L
H
L
H

'ALS242A

'ALS243A

Ato-B
Bto A
Isblation
Latch A and B
(A=B)

Ato B
BtoA
Isolation
Latch Aand B
(A=B)

2-144

-

~

Recommended Operating Conditions
Symbol
Vcc

Supply Voltage

VIH

High Level Input Voltage

VJL

Low Level Input Voltage

10H

High Level Output Current

10L

TA

DM74ALS242A, 243A

DM54ALS242A, 243A

Parameter

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

2

Units
V
V

2
0.8
-12

0.8

V

-15 r

mA

Low Level Output Current

12

24

mA

DM74ALS242A·1, DM74ALS243A-1

-

48

mA

70

,OC

Operating Free Air Temperature

-55

125

0

Electrical Characteristics over recommended operating free air temperature range (unless otherwise specified)
Symbol

Parameter

Conditions

VIK

Input Clamp.
Voltage

Vcc = 4.5V, II = -18 mA

VOH

High Level
Output

Vcc = 4.5V to 5.5V
Vcc=4.5V

Low Level
Output Voltage

DM74ALS242A,243A

Min

Min

Typ

Max

Typ

-1.5

10H= -0.4 mA
10H= -3mA
10H=Max

VOL

DM54ALS242A, 243A

Max
-1.5

Units
V

Vcc- 2

Vcc- 2

V

2.4

2.4

V

2

2

V

Vcc =4.5V
lOL = 54ALS (Max)

0.25

0.4

0.25

0.4

V

IOL = 74ALS (Max)

-

-

0.35

0.5

V

0.1

0.1

mA

20

20

p.A

-0.1

-0.1

mA

-112

mA

II

Input Current at
Max Input
Voltage

Vcc=5.5V,
VI = 7V (5.5V for I/O Ports)

IIH

High Level
Input Current

Vcc=5.5V, VI=2.7V

IlL

Low Level Input
Current

Vcc =5.5V, VIL =0.4V

10-

Output Drive
Current

Vc c=5.5V, Vo=2.25V

lOZH

High Level
TRI-STATE
Output Current

Vcc =5.5V, Vo=2.7V

20

20

p.A

10ZL

Low Level
TRI-STATE
Output Current

Vcc= 5.5V, Vo=0.4V

-20

-20

p.A

Icc

Supply Current

Vcc = 5.5V, ALS242A
Active Outputs High

10

20

10

16

mA

Active Outputs Low

14

26

14

21

mA

Outputs TRI-STATE

15

27

15

22

mA

,
-30

-112

-30

Vcc=q.5V, ALS243A
Active Outputs High

15

30

15

25

mA

Active Outputs Low

20

35

20

30

mA

Outputs TRI-STATE

21

37

21

32

mA

2-145

~

•ALS242A Switching Characteristics

<:>-...4-----..:.:.

A3 ....;..----t.....-i~>O-......+----......:...B3

A3...;;...------~.-~~--.~----~B3

---------1~~~>O~~--------~B4

A4 - - - - -.....-:---1 ~~-....I_---.....;;.. B4

2-146

r------------------------------------------------------------------,c

3:

~National

~

~ Semiconductor

b)

DM54ALS244A/DM74ALS244A Octal TRI·STATE®

BU$

~

Driver c

3:

i!

»

r-

General Description
This octal TRI-STATE bus driver is designed to provide the
designer with flexibility in implementing a bus interface
with memory, microprocessor, or communication systems. The output TRI-STATE gating control Is organized
into two separate groups of four buffers, and both control
inputs enable the respective outputs when set logic low.
The TRI-STATE circuitry contains a feature that maintains
the buffer outputs in TRI-STATE (high impedance state)
during power supply ramp-up or ramp-down.1"his eliminates bus glitching problems that arise during power-up
and power-down.
The -1 versions of the DM74ALS devices are identical to
their standard versions except that the recommended
maximum 10L is increased to 48 mA. There are no -1 versions of the DM54ALS devices.

Features

• Improved switching performance with less power
dissipation c~mpared with the DM54/74LS counterpart
• Switching response specified into 5000 and 50 pF load
• Switching response specifications guaranteed over
full temperature and Vec supply range
• PNP input design reduces input loading
• Low level drive"current:
54ALS= 12 mA, 74ALS=24 mA, 74ALS-1 =48 mA

Absolute Maximum Ratings
Supply Voltage, Vee
Input Voltage
Output Voltage
Storage Temperature Range

(Note 1)

7V
7V
5.5V
-55·Cto + 150·C

Not. 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the

• Advanced low power oxide-isolated ion-implanted
Schottky TTL process
• Functional and pin compatible with the DM54/74LS
counterpart

"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connectic;m Diagram

Function Table

Dual-In-Line Package
li!- 1

U

2ot-Vcc

1Al- 2

19 t-2G

2Y4- 3

18 t-1Y1

lA2- 4

17r-2A4

2Y3- 5

16 t-1Y2

lA3- 6

15 t-2A3

2Y2- 7

14 t-1Y3

1A4- 8

131-2A2

2Y1- 9

12r-1Y4

GNo-L.:1.;.O_ _ _ _1;.;.J1r-2A1
TLlF16212·1

TOP VIEW

DM54ALS244A (J)

1G or2G

Data
Buffer
Outputs

L
H

Active
TRI-STATE

Enable
Input

DM74ALS244A (J, N)

2-147

I

•

Recommended Operating Conditions
Symbol
Vee

DM54ALS244A

Parameter
Supply Voltage

DM74ALS244A

Units

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

.5.5

V

0.8

0.8

V

VIH

. . High Level Input Voltage .

Vil

Low Level Input Voltage

IOH

High Level Output Current

-12

-15

mA

10l

Low Level Output Current

12

24

mA

DM74ALS24.4A-1

-

48

mA

70

·c

TA

2

Operating Free Air Temperature

2

-55

125

V

0

Electrical Characteristics over recommended operating free,air temperature range (unless otherwise specified)
Symbol

Parameter

DM54ALS244A

Conditions

Min

VIK

Input Clamp
Voltage

Vcc=4.5V, 11= -18 mA

VOH

High Level
Output

Vee = 4.5V to 5.5V 10H= -0.4mA
Vee = 4.5V

Low Level
Output Voltage

DM74ALS244A

Max

Min

Typ

10H;" -3mA

Max
':"1.5

-1.5

IOH=Max
VOL

Typ

Units
V

Vcc- 2

Vee- 2

V

2.4

2.4

V

2

2

V

Vcc= 4.5V
IOl = 54ALS (Max)

0.25

0.4

0.25

0.4

10l = 74ALS (Max)

-

-

0.35

0.5

V

V

II

Input Current at
Max Input
Voltage

Vee = 5.5V, VI =7V

0.1

0.1

mA

IIH

High Level
Input Current

Vcc=5.5V, VI=2.7V

20

20

p.A

III

Low Level Input
Current

Vec=5.5V, Vll=0.4V

-0.1

-0.1

mA

10

Output Drive·
Current

Vee = 5.5V; Vo=2.25V

-112

mA

IOZH

High Level
TRI-STATE
Output Current

Vcc=5.5V, Vo=2.7V

20

20

p.A

IOZl

Low Level
TRI-STATE
Output Current

Vcc= 5.5V, Vo=0.4V

-20

-20

I,A

Icc

Supply Current

Vee = 5.5V
Outputs High

9

15

9

15

mA

Outputs Low

15

24

15

24

mA

Outputs TRI-STATE

17

27

17

27

mA

-30

2-148

-112

-30

r-----------------------------------------------------------------------,c

3:

Switching Characteristics over recommended operating free air temperature range (Note 1).
Parameter

From
(Input)

To
(Output)

tpLH

A

Y

tpHL
tPZH

G

y

tPZL
tpHZ

G

Conditions
Vcc = 4.5V to 5.5V,
C L =50 pI",
R1 =5000,
R2 = 5000,
TA = Min to Max

y

tpLZ

U1

~

74ALS244A

54ALS244A

r-

Max

Min

3

13

3

10

ns

3

13

3

10

ns

~

7

25

7

20

ns

3:

7

25

7

20

ns

2

12

2

10

ns

3

18

3

13

ns

Min

Typ

Nole 1: See Section 1 for test waveforms and output load.

Logic Diagram
Iii
>_-+~1;.B 1Y1
>_-+~16;'1Y2
>_-+~14';"IY3
> _ _~12';"IY4

>--+"""';;"2Y1

>_-+----'7;,..2Y2

>_-+----'S;,..2Y3

> _ _----'3;,..2Y4
TLlF16212·2

2-149

Typ

Max

Units

C

~
l>

r-

i

rate internal
. overlap features to ensure that select input changes do not
cause invalid output transients.

•
•

Improved Output Transient Handling Capability.
Output Control Circuitry Incorporates Power-Up TriState Feature.

Absolute Maximum Ratings

(Note 1)

7V
Supply Voltage, VCC
7V
Input Voltage
Operating Free Air Temperature Range
-55°C to 125°C
DM54ALS251
O°C to 70°C
DM74ALS251
-65°C to +1-50°C
Storage Temperature Range
Lead Temperature
(Soldering, 10 seconds)

Features
•

Advanced Oxide-Isolated lon-Implanted Schottky TTL
Process.
• Switching Performance is Guaranteed Over Full
Temperature and VCC Supply Range.
• Pin and Functional Compatible with LS Family
Counterpart.

Note 1: The "Absolute Maximum Ratings" are those values beyo'ld
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric. values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum rallngs. The "Recommended Operating Condillons" table will
define the conditions for actual device operation.

Functi(;m Table

Connection Diagram
Dual·ln·Llne Package

Outputs

Inputs
l!-vCC

14 D5
DAn

INPUTS .

13 D6

12 D1

;;~
•
~

~

A

\I

I"":" SELECT A

B~
8

1

~

C1

~

.....

10 SELECTB

9 SELECTC

TLlF/6214·1
54ALS251 (J)

C

B

A

S

Y

X
L
L
L
L

X
L
L

X
L

H

Z

Z

DO

00

H
H
H
H

L
L

H

H
H

H

L
L
L
L
L
L
L
L

H
H

H

L
H.

L
L

01
02
03
04
05
06
07

H - High Logic Level, L - Low Logic Level, X - Don't Care
Z - High Impedance (Off)
DO thru 07 - The Level of the Respective 0 Input

c~

'---

Strobe

Select

74ALS251 (J,N)

2·152

W

Of

D2

D3
154
05
Dll
07

.-------------------------------------------------------~-------------,c

s:
en

Recommended Operating Conditions

Supply Voltage, VCC

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

0.8

Low Level Input Voltage, VIL

-1

High \-evel Output Current, 10H

12

Low Level Output Current, 10L

Electrical Characteristics

Unit

V
V

2

2

High Level Input Voltage, VIH

~

DM74ALS251

DM54ALS251
Parameter

0.8

V

-2.6

mA

24

mA

Max

Unit

-1.5

V

over recommended operating free air temperature range.

All typical values are measured at Vcc = 5V, TA = 25 C.
D

Symbol

Parameter

Conditions

VJK

Input Clamp Voltage

VCC = 4.5V, liN = -18mA

VOH

High Level Output
Voltage

VCC = 4.5V, 10H = Max

Min

2.4

10H = 400 !LA, VCC = 4.5 to 5.5V
VOL

Low Level Output
Voltage

VCC = 4.5V

Typ

V

3.2

V

VCC-2

54ALS/74ALS
10L = 12mA

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

II

Input Current at
Max Input Voltage

VCC = 5.5V, VIN = 7V

0.1

mA

IIH

High Level Input Current

VCC = 5.5V, VIN = 2.7V

20

!LA

IlL

Low Level Input Current

VCC.= 5.5V, VIN = 0.4V

-0.1

mA

.10

Output Drive Current

VCC = 5.5V, VOUT = 2.25V

-112

mA

10ZH

Off-State Output
Current, High Bias

VCC = 5.5V, VOUT = 2.7V

20

!LA

10ZL

Off-State Output
Current, Low Bias

VCC = 5.5V, VOUT =O.4V

-20

!LA

ICC

Supply Current

VCC=5.5V
Data Inputs = 4.5V
Select Inputs = 4.5V
Control Inputs = 4.5V

mA

2-153

-30

Enabled

7

10

Disabled

9.4

14

r-

~

en
...10

-s:
C

~
l>
r-

en
N

en
...10

T-r-------------------------------------------------------------------~------------------~

Il)

~


1-Line Data Selector/Multiplexer
General Description.

•

This Data Selector/Multiplexer contains full on~chip decoding to select one-ol-Iour ,data sources as a result 01 a
unique two-bit binary code at the Select Inputs. Each 01 the
two Data Selector/Multiplexer circuits have their own separate Select, Data, and Output Control inputs and a non-inverting TRI-STATE output buffer. The Output Control inputs, when at the high level, place the corresponding output In the high impedance Off state. In order to prevent bus
access conflicts, output disable times are shorter than
output enable times. The Select input buffers incorporate
internal overlap features to ensure that select input
changes do not cause invalid output transients.

Absolute Maximum Ratings

Pin and Functional Compatible with LS Family
Counterpart.
• Improved Output Transient Handling Capability.
• Output Control Circuitry Incorporates Power-Up
TRI-STATE Feature

.• Advanced O~ide-Isolated lon-Implanted Schottky TTL
Process.
• Switching Performance is Guaranteed Over Full
Temperature and VCC Supply Range.

\

Nole 1: The "Absolute' Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for act"al device operation.

Function Table

Connection Diagram
Dual·ln-Llna Package

91

1

Select
Inputs

to.

.

.if

SELECT B-"t-iJD--t--,

......

.---

'ta..
.......

1C3.J 1--1- ;--

15

~~L
G2

14 SELECT A

'---

r-- 1-......

j,I--HH--fi

OUTPUTYI 7

~....T

fL2C3

I- f- tlL2C2

I-- -

>Ili'Mrs

;!Llel

9 OUTPUT Y2

TLlF/~215·1

54ALS253 (J)

Output
Control

Output

A

CO

C1

C2

C3

G

y

X

X

X

L
L
H
H
L
L
H
H

L
H

X
X
X
X
X
L
H

X
X
X
X
X
X
X

X
X

L
H

H
L
L
L
L
L
L
L
L

Z

L
L
L
L
H
H
H
H

X
X
X

X
X
X
X
X
X

L
H

X
X
X
X

i

L
H
L
H
L
H
L
H

Address inputs A and B are common to both 'sections
H - High Level. L - Low Level, X - Don't Care. Z - High Impedance

f--~2CO

T..i...

Data Inputs

B

...

lCOjl--

(Note 1)

7V
Supply Voltage, VCC
7V
Input Voltage
Operating Free Air Temperature Range
-55°C to 125°C
DM54ALS253
0° to 70°C
DM74ALS253
-65°C to +150°C
Storage Temperature Range
Lead Temperature
(Soldering, 10 seconds)

Features

c~%Va~I

to

74ALS253 (J,N)

2-156

Recommended Operating Conditions
DM54ALS253
Parameter
Supply Voltage, VCC
High Level Input Voltage, VIH

Min
4.5

DM74ALS253

Nom

Max

Min

Nom

Max

5

5.5

4.5

5

5.5

2
0.8

High level Output Current, 10H

-1

Low level Output Current, 10l

Electrical Characteristics

12

Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.5V, liN = -18mA

VOH

High level Output
Voltage

VCC = 4.5V, 10H

Min

=

Max

10H = 400 p.A,. VCC = 4.5 to 5.5V
low level Output
Voltage

0.8

V

-2.6

mA

24

mA

Max

Unit

-1.5

V

over recommended operating free air temperature range (Note 1)

Symbol

VOL

V
V

2

Low level Input Voltage, Vil

Unit

VCC

=

2.4

3.2

V
V

VCC-2

54/74AlS
10l = 12mA

4.5V

Typ

74AlS
10l = 24mA

0.25

0.4

V

0.35

0.5

V

II

Input Current at
Max Input Voltage

VCC = 5.5V, VIN = 7V

0.1

mA

IIH

High level Input Current

Vee = 5.5V, VIN = 2.7V

20

p.A

III

low level Input Current

VCC

=

5.5V, VIN

-0.1

mA

10

Output Drive Current

VCC

=

5.5V, VOUT c= 2.25V

-112

mA

10ZH

Off-State Output
Current, High Bias

Vec = 5.5V, VOUT

2.7V

20

p.A

10Zl

Off-State Output
Current, low Bias

VCC

5.5V, VOUT =0.4V

-20

p.A

ICC

Supply Current

Vce = 5.5V
Output High
Output low
Disabled

=

=

O.4V

=

-30

mA
6.5
6.5
7.5

2·157

12
12
14

·~

Switching Characteristics over recommended operating free air temperature range (Note 1).

...I

All typical values are measured at Vee = 5V. TA = 25°C.

---I~

2CO~I::..O--------++-±-+--r'""\

2CI..!.I1:.-,.....--------1H-t.....f---r"""""\
DATA 2

2C2~1~2-------"""'"'iFlF==t:::fl
2C3~13::....-------__1~t==::{:=:)
OUTPUT
CONTROL

-<0------------------'

~1;.5
62

TLIF16215·2

2·158'

~National

D Semiconductor
DM54ALS/DM74ALS257, 258 TRI·STATE® Quad
1·of·2·Line Data Selectors/Multiplexers
General Description

•

These data selectors/multiplexers contain inverters and
drivers to supply full on-chip data selection to the four TRISTATE outputs that can interface directly with data lines of
bus-organized systems. A 4-bit word selected from one of
two sources is routed to the four outputs. The ALS257 presents true data whereas the ALS258 presents inverted data
to minimize propagation delay time.
This TRI-STATE output feature means that n-bit (paralleled)
data selectors with up to 258 sources can be implemented
for data buses. It also permits the use of standard TTL registers for data retention throughout the system.

Features
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.

•

Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
Functionally and Pin for Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.

•

Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.

• TRI-STATE Buffer-Type Outputs Drive Bus Lines Directly.
•
•
•

Expand any data input point.
Multiplex dual data buses.
General four functions of two variables (one variable is
common).

•

Source programmable counters.

Absolute Maximum Ratings

(Note 1)
7V
7V

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS
DM74ALS
Storage Temperature Range

-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those vaiues beyond
which the salety 01 the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will

define the conditions for actual device operation.

Function Table

Connection Diagram
Dual·ln·Line Package
OUTPUT ~ OUTPUT ~ OUTPUT
VCCCONTROL4A
48
4Y
3A
38
3Y

-I~e

bs 114 b3 112 111 bo
~
G

I I
4A

48

~
4Y

I I
3A

S

Select

A

B

ALS257

ALS258

H
L
L
L
L

X
L
L
H
H

X
L
H
X
.X

X
X
X
L
H

Z
L
H
L
H

Z
H
L
H
L

38

18

lY

I I

Y

\2

\4

2A

28

2Y

I I

Y
\5 \e \7 \s
2Y
GND
SELECT lA
18
2A
28
lY
'iNPUTS OUTPUT 'INPUTs' OUTPUT
1

Output
Control

3Y
lA

\3

H

=

HIgh Level, L

Z

~

High Impedance (off)

TL/F/6227·1

54ALS258 (J)

Output Y

Inputs

9

74ALS258 (J,N)

2·159

=

Low Level, X .... Don't Care

•

m Recommended Operating Conditions
,

Cit

a
30

40

+
-

7

0

5

20

0

r-c >mi

--w-

8

0

6

.30

0

f-Cii

9

ClR 0

40

~

50

-

-

13

0

>Cii

12

ClR 0

50

---T"

r-60 14

0

r<

Cii

--w-

0

15 60

,..-70

17

r-c

0

~Cii
0

16 70

---%L
,..-80 f8

0

f-c
CLOCK
CLEAR

11

.loI>o-

....

"

Cii

=r
0

19

ao

TlIF/8216-2

2·165

~ ~National
c(

t!

PRELIMINARY

~ Semiconductor

:E

c DM54ALS299/DM74ALS299 TRI-STATE®8-Bit Universal

I~
:E

c

Shift/Storage Registers
General Description
This Schottky TIL 8-bit universal register features multiplexed inputs/outputs to achieve full 8-bitdata handling in
a single 20-pin package. Two function-select inputs and
two output-control inputs can be used to choose the
modes of operation listed In the function table.
Synchronous para"el loading is accomplished by taking
both function-select lines, SO and S1, high. This places the
TRI-STATE outputs in a high-impedance state, which permits data that is applied on the Input/output lInes to be
clocked into the register. Reading out of the register can
be accomplished while the outputs are enabled In any
mode. A direct overriding input is provided to clear the
register whether the outputs are enabled or off.

• Can be cascaded for N-bit word lengths
• Applications:
Stacked or push-down registers
• Switching specifications at 50 pF
• Switching specifications guaranteed over full
temperature and Vcc range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functiona"y and pin-for-pin compatible with Schottky
and LS TTL counterpart

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

Features
II Multiplexed inputs/outputs provide improved bit
density
• Four modes of operation:
Hold (Store)
Shift Left
Shift Right
Load Data
• Operates with outputs enabled or at l:Ii-Z
• TRI-STATE outputs drive bus lines directly

"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual·ln·Llne Package
SHIFT
SHIFT
LEFT
RIGHT
SL Qw H/OHF/OFD/QDB/QacLocK SR

S1

120 b9 118 117 116 115 114

j13

12·11

I
S1

r-

SL

SR

r,
. :n,.

G/QG E/QE C/QC A/QA QA'CLEAR

--

112
SO

Qw H/QH F/QF D/QD BIOs CK

SO
G

G1

1.3

G2

7V
7V
-65·Cto + 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the

Connection Diagram

vCC

(Note 1)

4
5
6
7
8
9110
G/OG E/QE C/QC A/QA QA' CLEAR GND

OUTPUT
CONTROLS

TLIF16217·1

DM54ALS299 (J)

2·166

DM74ALS299 (N)

Function Table
Inputs
Mode

Inputs/Outputs

Function Output
Clear Select Control Clock
S1

SO G1t G2t

Serial
SL

SR

Outputs

A/QA S/QS C/QC D/QD E/QE F/QF G/QG H/QH

QA'

QH'

L
L

L
L

X
X

X
X

X
X

L
L

L
L

L
L

L'
L

L
L

L
L

L
L

L
L

L
L

L
L

L
L

L
L

X

X

X
X

X
X

OAO
OAO

OBO
OBO

OCO
OCO

000
000

OEO
OEO

OFO
OFO

OGO
OGO

OHO
OHO

OAO
OAO

OHO
OHO

L
L

H
H

L
L

L
L

X
X

H
L

H
L

OAn
OAn

OBn
OBn

OCn
OCn

OOn
OOn

OEn
OEn

OFn
OFn

OGn
OGn

H
L

OGn
OGn

H
H

H
H

L
L

L
L

L
L

t
t
t
t

H
L

X OBn
X -OBn

OCn
OCn

OOn
OOn

OEn
OEn

OFn
OFn

OGn
OGn

OHn
OHn

H
L

OBn
OBn

H
L

H

H

H

X

X

t

X

X

b

c

d

e

I

g

h

a

h

Clesr

L
L

Hold

H
H

L

L

X

Shill Righi

H
H

Shill Left
Losd

X

L

L

X

L

a

tWhen one or both output controls are high the eight input/output terminals are disabled to the high-impedance slate; however, sequential operation or clearing of the register is not affected.
a ... h = the level of the steady-state input at inputs A through H, respectively. These data are loaded into the flip-flops while the flip-flop outputs are isolated
from the Input/output terminals.

2-167

DM54ALS299/DM74ALS299

b

CD

c;'

c

i'..
II)

51

:I

so

~~
SHIFT

(18) RIGHT
SERIAL

SHIFT
(11)
LEFT
SERIAL
INPUT

INPUT

~I
(121

CLOCK

(17)

QA; (8)

QH'

(9)

CLEAR

OUTPUT
CONTROLS

{G1~
(3)

Jn

~

G21(7)
A/OA

1(13)

BlaB

1(6)
C/Oc

1(14)
D/Qn

1(5)
E/QE

1(15)
F/QF

1 (4)
G/QG

1(16)
H/QH

TlfF/6217·2

Recommended Operating Conditions
Symbol

DM54ALS299

Parameter

Vee

Supply Voltage

V,H

High Level Input Voltage

DM74ALS299

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

2

2

Units
V
V

V,L

Low Level Input Voltage·

0.8

0.8

10H

High Level Output
Current

QA' orQ H'

-0.4

-0.4

mA

Q A thru Q H

-1

-2.6

mA

10L

Low Level Output Current

QA' or Q H '

4

8

mA

Q A thru QH

12·

24

mA

30

MHz

f eLOCK

Clock Frequency

tw

Pulse Width

tsu

Data Set·Up Time

0

25

0

V

Clock High or Low

20

16.5

Clear Low

10

10

ns

251

201

ns

181

161

ns

71

61

ns

151

151

ns

01

01

ns
..C

Select
Serial or
Parallel Data

I High

I Low

CLR Inactive
tH

Data Hold Time

TA

Operating Free Air Temperature

-55

125

ns

0

70

The (r) arrow indicates the positive edge of the Clock is used for reference.

Electrical Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

V,K

Input Clamp Voltage

Vee = 4.5V, I, = -18 mA

V OH

High Level Output Voltage

10H = - 400 I'A, Vee = 4.5 to 5.5V

VOL

Low Level Output Voltage

Min

Typ
(Note 3)

Max
-1.5

V
V

Vee- 2

2.4

Units

V

3.2

10H=Max

QA thru QH

Vee=4.5V
V,H =2V

54/74ALS
IOL=4 mA

0.25

0.4

V

Q A' or QH'

74ALS
101 =8mA

0.35-

('.5

V

Vee=4.5V

54/74ALS
10L= 12 mA

0.25

0.4

V

QAorQH

74ALS
IOL=24 mA

0.35

0.5

V
mA

I,

Max High Input Current

Vee = 5.5V, V,H = 7V

0.1

I'H

High Level Input Current

Vee = 5.5V, V,H = 2.7V

20

I'A

I'L

Low Level Input Current

Vee=5.5V,
V,L =O.4V

-0.2

mA

Output Drive.1 Vee=5.5V
Current

Vo=2.25V

10

Icc

Supply Current

Vee=5.5V

ISO, Sl, SR, SL

-0.1

mA

QA' or QH'

-15

-70

mA

Q A thru QH

-30

-112

mA

All Others

Outputs High

15

28

mA

Outputs Low

22

38

mA

Disabled

23

40

mA

2·169

•

Switching Characteristics over recommended operating free air temperature range (Note 1)
From
(Input)

Symbol

Parameter

fMAX

Maximum Clock Frequency
(Note 2)

tpLH

Propagation Delay Time,'
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

Clear

tpLH

Propagation Delay Time,
Low-to-High Level Output

Clock

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpzH

Output Enable Time to
High Level

tPZL

Output Enable Time to
Low Level

tpHZ

Output Disable Time
from High Level

tpLZ

Output Disable Time
from Low Level

tPZH

Output Enable Time to
High Level

tpzL

Output Enable Time to
Low Level

tpHZ

Output Disable Time
from High Level

tpLZ

Output Disable Time
from Low Level

-To
(Output)

DM54ALS299
Typ
(Note 3)

Min

Max

Min

Typ
(Note 3)

Max

' 30

25

Units

MHz

5

20

5

15

ns

8

21

8

18

ns

QA' or QH'

6

29

6

22

ns

QA thru QH

4

15

4

13

ns

7

25

7

19

ns

Q A thru Q H

6

29

6

22

ns

G1, G2 QA thru QH

6

21

6

16

ns

8

26

8

_ 22

ns

1

10

1

8

ns

5

23

5

15

ns

7

21

7

17

ns

8

26

8

22

ns

1

16

1

12

ns

3

20

3

15

ns

Clock QA' or QH'

Clear

131, G2 QA thru QH

50,51 QA thru QH

50,'51

QA thru Q H

Note 1: See Section 1 for test waveforms and output load.
Note 2: Fo'r testing fMAX. all outputs are loaded simultaneous~y.

Note 3:

DM74ALS299

All typical values are at VCC:5V, TA :25'C_

.
2-170

r-----~------------------------------------~------------------,c

s:

.
Semiconductor

~National

D

(J'I

~

r

C/)

(0)
(J'I

-s:

DM54ALS352/DM74ALS352 Dual4-Une to 1-Une
Data Selector/Multiplexer

N

C

General Description

Absolute Maximum Ratings

This Data Selector/Multiplexer contains lull on-chip decoding to select one-aI-lour data sources as a result 01 a
unique two-bit binary code at the Select inputs. Each of the
two Data Selector/Multiplexer circuits have their own separate Select, Data, and Strobe inputs and an inverting output
buffer. The Strobe inputs, when at the high level, disable
their associated data inputs and force the corresponding
output to the high state. The Select input buffers incorporate internal overlap features to ensure that select input
changes do not cause invalid output transients.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS352
DM74ALS352
Storage Temperature Range
Lead Temperature
(Soldering, 1D seconds)

Features
•

Advanced Oxide-isolated lon-implanted Schottky TTL
process.

•

Switching performance is guaranteed over full
temperature and Vee supply range.

•

Pin and lunctional compatible with the LS Family
counterpart.

•

Improved output transient handling capability.

Connection Diagram

»~

(Note 1)
7V
7V

-55°C to 125°C
DOC to 7Doe
-65°C to 15Doe

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed, The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Dual-In-Line Package

DATA INPUTS

STROBE B
1G SELECT

Select
Inputs

Strobe

Output

B

A

CO

C1

C2

C3

G

V

X

X

X

L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H

L
H

X
X
X

X
X
X
X
X
L
H

X
X
X
.X
X
X
X

X
X

L
H

H
L
L
L
L
L
L
L
L

H
H
L
H
L
H
L
H
L

X
X
X
X
X
X

L
H

X
.X
X
X

Select Inputs A and 8 are common to both sections
H ~ High Level, L ~ Low Level, X ~ Don't Care

DATA INPUTS
TLlF/6218·1

54ALS352 (J)

Data Inputs

74ALS352 (J,N)

2-171

~
(0)
(J'I

N

~
~

-

I

01>-1-

10

~

)--

2Cl 11
~

DATA 2
2C2

12

-1

9 OUTPUT
Y2

' - l"'::'"-1

2C3 13
15

STROBE 62

}-

Jo.

-v

TLfFf6218·2

2-173

•

~National

a

Semiconductor

DM54ALS353/DM74ALS353 TRI-STATEf> Dual 4-Line to
1- Line Data Selector/Multiplexer
General Description

•

This Data Selector/Multiplexer contains full on-chip decoding to select one-of-four data sources as a result of a
unique two-bit binary code at the Select Inputs. Each of the
two Data Selector/Multiplexer circuits have their own separate Select, Data, and Output Control inputs and an inverting TRI-STATE output buffer. The Output Control inputs,
when at the high level, place the corresponding output in
the high impedance Off state. In order to prevent bus access conflicts, output disable times are short~r than output
enable times. The Select input buffers incorporate internal
overlap features to ensure that select input changes do not
cause invalid output transients.

•
•

Features
•
•

Advanced Oxide-isolated lon-implanted Schottky TIL
process.
Switching performance is guaranteed over full
temperature and VCC supply range.

Connection Diagram

Pin and functional compatible with LS Family
counterpart.
Improved output transient handling capability.
Output Control circuitry incorporates power-up TRISTATE feature.

Absolute Maximum Ratings (Note 1).
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
, DM54ALS353
-55°C to +125°C
DM74ALS353
O°C to +70°C
Storage Temperature Range'
-65°C to +150°C
Lead Temperature
+300°C
(Soldering, 10 seconds)
Nate 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametriC values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Dual·ln·Llne Package
Select
Inputs

DATA INPUTS

OUTPUT

B

CONTROL SELECT
1G

DATA INPUTS

54ALS353 (J)

TL/F/6219·1

Output
Control

Data Inputs

B

A

CO

C1

C2

C3

G

X
L
L
L
L
H
H
H
H

X
L'
L
H
H
L
L
H
H

X
L
H
X
X
X
X
X
X

X
X

X
X
X
X
X
L
H
X
X

X
X
X
X
X
X
X
L
H

H
L
L
L
L
L
L
L
L

X
L
H
X
X
X
X

Address Inputs A and B are common to both sections
H High Level, L Low Level, X Don't Care
Z High Impedance State

=
=

74ALS353 (J,N)

2·174

=

=

Output

y
Z
H
L
H
L
H
L
H
L

c

:!l:

Recommended Operating Conditions

c.n

DM54ALS353
Parameter

DM74ALS353

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Unit

,.en~
(0)

Supply Voltage, VCC
High Level Input Voltage, VIH

2

V

2

Low Level Input Voltage, VIL

0.8

High Level Output Current, 10H
Low Level Output Current, 10L

V

0.8

V

-1

-2.6

mA

12

24

mA

Max

Unit

-1.5

V

!l)

c.n

(0)

c

:!l:
~

,.en»
(0)

Electrical Characteristics

over recommended operating free air temperature range.

All typical values are measured at Vee =5V, TA =25'C.
Symbol

Parameter

Conditions

VIK

,Input Clamp Voltage

VCC = 4.5V, liN = -18mA

Min

VOH

High Level Output
Voltage

VCC = 4.5V, 10H = Max
IOH = - 400 I'A, VCC = 4.5 to 5.5V

VOL

Low Level Output
Voltage

VCC = 4.5V

2.4

Typ

V

3.2

V

VCC- 2

54ALS/74ALS
10L = 12mA

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

II

Input Current at
Max Input Voltage

VCC = 5.5V, VIN = 7V

0.1

mA

IIH

High Level Input Current

VCC = 5.5V, VIN = 2.7V

20

I'A

IlL

Low Level Input Current

VCC = 5.5V, VIN = O.4V

-0.1

mA

10

Output Drive Current

VCC = 5.5V, VOUT = 2.25V

-112

mA

10ZH

Off-State Output
Current, High Bias

VCC = 5.5V, VOUT = 2.7V

20

IlA

10ZL

Off-State Output
Current, Low Bias

VCC = 5.5V, VOUT = O.4V

-20

IlA

ICC

Supply Current

VCC = 5.5V

mA

-30

All Inputs at 4.5V

8

13

All Inputs at GND

7

12

2-175

c.n

(0)

~r----------------------------------------------------------------------------'

r.t)

~~

~
:!:

-

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V, i

A

= 25'C.

From

To

DM74ALS353

DM54ALS353
Parameter

Conditions

Min

Typ

Typ

Max

Unit

Max

Min

5

28

5

24

ns

5

24

5

21

ns

4

21

4

18

ns

3

15

3

13

ns

3

15

3

13

ns

3

19

2

16

ns

tHZ. Output Disable Time
From High Level

2

12

2

10

ns

tLZ. Output Disable Time
From Low Level

2

16

2

14

ns

Q

~
r.t)

~

~
:!:

tPLH. Low to high Level Output
Select
tPHL. High to low Level Output

"

tPLH. Low to high Level Output

Data
tPHL. High to low Level Output
y

Q

tZH. Output Enable Time
to High Level
tZL. Outpu~ Enable Time
to Low Level

VCC =
4.5 to 5.5V
CL = 50 pF
RL = 500!l

Output
Control

Note 1: See Section 1 for test waveforms and.output load.

Logic Diagram
OUTPUT ~I--O-....-CI>_ _--t......

--------++±---t....r"'\

2CO ..!1~O

2Cl.:.I1: . . - - - - - - - - - - 1 H - t - + - r " " " " " \
DATA 2

9 OUTPUT

2C2...!1~2-~------i=::t==:t=::r)

2C3.:.13~----------1C:1==::{:J
OUTPUT -,;1;.5- - < 0 - - - - - - - - - - - - - - - - - - '
CONTROL G2

2·176

Y2

r---------------------------------------------------------------.c

s:
U'I

'?"A National

>

D Semiconductor

fii
w

DM54ALS373/DM74ALS373 Octal
D-Type Transparent Latches

-s:

General Description

Features

l>

These a-bit registers feature totem-pole TRI-STATE'" outputs designed specifically for driving highly-capacitive or
relatively low-impedance loads_ The high-impedance state
and increased high-logic-level drive provide these registers with the capability of being connected directly to and
driving the bus lines in a bus-organized system without
need for interface or pull-up components. They are particularly attractive for implementing buffer registers, 1/0 ports,
bidirectional bus drivers, and working registers.
The eight latches of the ALS373 are transparent D-type
latches meaning ~hat while the enable (G) is high the a outputs will follow the data (D) inputs. When the enable is taken
low the output will be latched at the level of the data that
was set up.

• Switching Specifications at 50 pF.
• Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
• Advanced Oxide-Isolated. Ion-Implanted Schottky TIL
Process.
• Functionally and Pin For Pin Compatible with LS TIL
Counterpart.
• Improved AC Performance Over LS373 at
Approximately Half the Power.
• TRI-STATE Buffer-Type Outputs Drive Bus Lines Directly.

~
w

A buffered output control input can be used to place the
eight outputs in either a normal logic state (high' or low logic
levels) or a high impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS373
DM74ALS373
Storage Temperature Range

~

w

C

~

Absolute Maximum Ratings (Note 1)

The output 'control does not affect the internal operation of
the latches. That is. the old data can be retained or new data
can be entered even while the outputs are off.

Connection Diagram
Dual-In-Line Package
ENABLE

Vee

80

OUTPUT
CONTROL

10

10

-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Nole I: The "Absolute Maximum Ratings" are Ihose values beyond
which the safety of the device can not be guaranteed. The device should
nOI be operaled at these limits. The parametric values defined In the
"Electrlcal·Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

80

7V
7V

70

70

60

60

50

50

G

20

20

30

30

40

40

GNO
TL/F/6220-1

54ALS373 (J)

74ALS373 (J,N)

2-177

fii

~ Recommended Operating Conditions

C")

~

DM74ALS373

DM54ALS373

----::..30
B

Hf---cIl>----::..4D
5D 13

IZ 50

50 -''''-----+--I
15 60

7D 11

70

19

BO

L
L
L
H

H
H
L

x

a

5 '0

16

Enable
G

0

SO 18

ENABLE G..:;"'----{>O-....

TLfF/6220·2

2-179

Output
Q

H
L

H
L

X
X

ao

L = Low State, H = High State, X = Don't Care
Z = High Impedance State
00 = Previous Condition of

" -.::'---+--I

4D

Output
Control

Z

~

~

c(

t:!

~National

a

Semiconductor

~

DM54ALS374/DM74ALS374 Octal D-Type~ Edge-Triggered Flip-Flops
C")

~

Features

General Description
~
II)
:IE

c

These 8·blt registers feature totem'pole TRI-5TATE
r-

en
~

~

The (1) arrow indicates the positive edge of the Clock is used for reference.

fII

2-181

~r---------------------------------------------------------------------~
.....

C")

~

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, T A = 25°C.

---~

10

3

, 2

'!--I----<>t>-----'- 10
20

4

•

3D

L1Z 00

20

Output

Output
Control

Clock

D

L
L
L
H

1
1
L
X

H
L
X

00

X

Z

Q

H
L

Low State, H - High State, X - Don't Care
Positive Edge Transition
High Impedance State
- Previous Condition of 0

7

30

40

8

9

50

40

13
12

'0

60 14
15

"

•

80

17
16

70

BD 18

CLOCK

"

80

TLlL/6113·2

2·183

o-J

Bl

~

_1~

16

18

•

__;;~________________~

~
TLIF/6114-3

2-191

TLlF/6114·4

~National

D Semiconductor

-

DM54ALS533/DM74ALS533
~ Octal D-Type Transparent Latches with TRI-STATE® Outputs

~
r-

en
CJ1
Co)
Co)

The (.) arrow IndIcates the negatIve edge of the enable IS used for reference.

Electrical Characteristics

over recommended operating free air temperature range.

All typical values are measured at Vee = 5V, TA = 25°C.

Min

Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC

VOH

High Level Output
Voltage

VCC ~ 4.5V
VIL ~ VIL MAX

10H
VOL

Low Level Output
Voltage

~

~

4.5V II

~

Typ

-18mA

- 4OOI'A

Unit

V

54ALS
10H ~ -1mA

2.4

3.2

V

74ALS
10H ~ -2.6mA

2.4

3.3

V

54/74ALS

VCC ~ 4.5V
VIH ~ 2V

Max

-1.5

V

VCC -2

54/74ALS
10L ~ 12mA

0.25

0.4

V

74ALS
10L ~ 24mA

0.35

0.5

V

II

Max High Input Current

VCC

~

5.5V VIH

~

7V

0.1

mA

IIH

High Level Input Current

VCC

=

5.5V'VIH

~

2.7V

20

I'A

IlL

Low Level Input Current

VCC~.

5.5V VIL

~

O.4V

-0.1

mA

10

Output Drive Current

VCC

5.5V

-112

mA

10ZH

Off -State Output
Current, High Level
Voltage Applied

VCC ~ 5.5V VIH
Vo ~ 2.7V

20

I'A

10ZL

Off-State Output
Current, Low Level
Voltage Applied

VCC ~ 5.5V VIH = ~V
Vo ~ O.4V

-20

I'A

ICC

Supply Current

VCC = 5.5V
Outputs Open

=

54/74ALS
Vo = 2.25V
~

-30

2V

Outputs High

10

17

mA

Outputs Low

17

26

mA

Outputs Disabled

18.5

28

mA

2-193

•

~r-----------------------------~---------------------------------------.

~
~

:E
c

~

Lt)

o-I

~
:E

c

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vcc =5V, TA=25°C.
DM54ALS533
Parameter
. TpLH

From
Data

To

Conditions

Min

Typ.

4

Any 0

DM74ALS533
Typ

Unit

Max

Min

Max

24

4

19

ns

TPHL

4

14

4

13

ns

TpLH

5

28

5

23

ns

4

21

4

18

ns

4

19

4

17

ns

Enable

AnyO

TpHL
TpZH
TPZL

Output

TPHZ

Control

VCC = 4.5V to 5.5V
RL = 500 n
CL = 50 pF

Any 0

TpLZ

4

20

4

18

ns

2

12

·2

10

ns

3

22

3

16

ns

NoIel: See Section 1 for test waveforms and output foad.

Logic Diagram

ID

Function Table

'

..

H--aI>-..J...,Q

3D

7

HI---aD--"-.o

.. B

H---'aI>--=- 'Q

15

ei

7D 11

18

70'

ID 18

1180

Enable
G

D

L
L
L
H

H
H
L
X

H
L
X
X

L - Low state. H - High State, X - Don't Care
Z - High Impedance State
00 - Previous Condition of 0

.. "
.. "

Output
Control

1 --[>0-....1
ENOlE 8.:1:...

TLI F16222·2

2·194

Output

Q
L
H
'00
Z

r---------------------------------------------------------------.c

:s:

~National

a

(J1

~

Semiconductor

ren

(J1
(,.)
~

-:s:

DM54ALS534/DM74ALS534
Octal D-Type Edge-Triggered Flip-Flops
with TRI-STATE® Outputs
General Description

Features

These B-bit registers feature totem-pole TRI-STATE outputs designed specifically for driving highly-capacitive or
relatively low-impedance loads_ The high-impedance state
and incr.eased high-logic-level drive provide these registers with the capability of being connected directly to and
driving the bus lines in a bus-organized system without
need for interface or pull-up components_ They are particularly attractive for Implementing buffer registers, 11.0 ports,
bidirectional bus drivers, and working registers.

•
•

The eight flip-flops of the ALS534 are edge-triggered inverting D-type flip-flops. On the positive transition of the clock,
outputs will be set to the complement of the logic
the
states that were set up at the 0 inpiJts.

a

A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.

c

~

:I>

~
(J1

Switching Specifications at 50 pF.
SWitching Specifications Guaranteed Over Full
Temperature and Vee Range.
Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.

•

• TRI-STATE Buffer-Type Outputs Drive Bus Lines Directly.

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS534
DM74ALS534
Storage Temperature Range

(Note 1)
7V
7V

-55°C to 125°C
ooe to 70°C
-65°C to 150°C

Nole I: The "Absolute Maximum Ratings" are those value. beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operallon.

Connection Diagram
Dual-ln·Line Package

TLtLt6223·1

54ALS534 (J)

(,.)
~

74ALS534 (J,N)

2-195

fII

i

....I
III(

Recommended Operating Conditions
DM54ALS534

~

Parameter

c

Supply Voltage, VCC

:&

~

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

High Level Input Voltage, VIH

High Level Output Current, IOH

c

Low Level Output Current, IOL

-1
12
0

Clock frequency, fCLOCK
Width of Clock Pulse, TW

Data Setup Time, TSU
Data Hold Time, TH

2
0.8

Low Level Input Voltage, VIL

~

:&

DM74ALS534

Min

30

0

Unit
V
V

0.8

V

-2.6

mA

24

,mA

35

MHz

High

16.5

14

ns

Low

16.5

14

ns

101

101

ns

01

01

ns

The (t) arrow indicates the positive edge of the Clock is used for reference.

2·196

.--------------------------------------------------------------,0
:s::
en

Electrical .characteristics over recommended operating free air temperature range.
All typical values are measured at Vcc = 5V, T A = 25°C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.5V, II = -18mA

VOH

High Level Output

VCC = 4.5V
VIL = VIL MAX

Typ

Min

Max

Unit

-1.5

V

:tr
rn
en

w

~

Voltage

VOL

Low Level Output
Voltage

54ALS
10H = -1mA

2.4

3.2

V

74ALS
10H = -2.6mA

2.4

3.3

V

V

10H = -400!LA

54/74ALS

VCC = 4.5V
VIH = 2V

54/74ALS
10L = 12mA

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

VCC -2

I

II

Max High Input Current

VCC =5.5V VIH = 7V

0.1

mA

IIH

High Level Input Current

VCC = 5.5V VIH = 2.7V

20

!LA

IlL

Low Level Input Current

VCC = 5.5V VIL = 0.4V

All Others

-0.2

mA

CLK,OC

-0.1
-112

mA

VCC = 5.5V VIH = 2V
Vo = 2.7V

20

!LA

Off-State Output
Current, Low Level
Voltage Applied

VCC = 5.5V VIH = 2V
Vo = O.4V

-20

!LA

Supply Current

VCC = 5.5V
Outputs Open

10

Output Drive Current

VCC = 5.5V

10ZH

Off-State Output
Current, High Level
Voltage Applied

10ZL

ICC

-30

54/74ALS
Vo = 2.25V

,
Outputs High

11

19

mA

Outputs Low

19

28

mA

Outputs Disabled

20

31

mA

SWitching Characteristics over recolT)mended operating free air temperature range (Note 1).
All typical values are measured at Vcc = 5V, TA =25°C.
DM74ALS534

D!\II54ALS534
Parameter

From

To

Conditions

Min

'ryp

Max

Min

Typ

Max

FMAX

30

TpLH

3

15

3

12

ns

5

18

5

16

ns

5

19

5

17

ns

7

20

7

18

ns

2

12

2

10

ns

2

16

2

14

ns

Clock

AnyQ

TpHL
TpZH
TpZL

Output
Control

AnyQ

VCC = 4.5V to 5.5V
RL = 500 n
CL = 50 pF

TpHZ
TPLZ

I

Note 1: See Section 1 for test waveforms and output load.

2-197

35

Unit
MHz

o
:s::
~

»
r
~
~

Logic Diagram

Function Table

OUTPUTCONTROL~--~----,

,....::..-------1

2D

Output
Control

Clock

D

1
1

H
L
X
X

L
L
L
H

H----C()----'- 10

L
X

L - Low State, H - High State, X - Don't Care
t = Positive Edge Transition
Z - High Impedance State
00 - Previous Condition of

4

a

,,-'-----+--1

4D

'0

"

12

14

15

17

16

80 18

19

50

"
7D

50

'0

70

'0

CLOCK 11

TL/Ll6223-2

'"

2-198

Output

Q
L
H

00
Z

r---------------------------------------------------------------,c

s::

~National

U'I

:;r-

D Semiconductor

en

U'I

-cs::
en
Co)

DM54ALS563/DM74ALS563 Octal D-Type
Transparent Latches with TRI-STATE® Outputs

~

»
r-

General Description

Features

These B-bit registers feature totem-pole TRI-STATE outputs designed specifically for driving highly-capacitive or
relatively low-impedance loads_ The high-impedance state
and increased high-logic-level drive provide these registers with the capability of being connected directly to and
driving the bus lines in a bus-organized system without
need for interface or pull-up components_ They are particu- .
larly attractive for implementing buffer registers, 1/0 ports,
bidirectional bus drivers, and working registers_

•
•

The eight inverting latches of !he ALS563 are transparent
D-type latches meaning that while the enable (G) is high the
Q outputs will follow the complement of the data (D) inputs.
When the enable is taken low the output will be latched at
the complement of ihe level of the data that was set up.

Absolute Maximum Ratings

A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
the latches. That is, the old data can be retained or new data
can be entered even while the outputs are off.

en

Switching Specifications at 50pF.
U'I
en
Switching Specifications Guaranteed Over Full
Co)
Temperature and Vee Range.
Advanced. Oxide-Isolated. Ion-Implanted Schottky TTL
Process.
.
TRI-STATE Buffer-Type Outputs Drive Bus Lines Directly_

•
•

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS563
DM74ALS563
Storage Temperature Range

(Note 1)
7V
7V

-55°C to 125°e
ooe to 70 0 e
-65°e to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safely of the device can not be guaranteed. The device should

not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Dual-In-Llne Package

T LI F16225-1

DM54ALS563 (J) DM74ALS563 (J, N)

2-199

m Recommended Operating Conditions
...I

DM54ALS563

,==
.....

Parameter

Q

Supply Voltage, VCC

::E

~

Nom

Max

Min

Nom

Max

4,5

5

5,5

4,5

5

5,5

High Level Input Voltage, VIH

2

High Level Output Current, 10H

c

Low Level Output Current, IOL

. Unit
V
V

2
0,8

Low Level Input Voltage, VIL

~.

:i

DM74ALS563

Min

-1
12

0,8

V

-2,6

mA

24

mA

Width of Enable Pulse, High or Low

15

15

ns

Data Setup Time, TSU

101

101

ns

Data Hold Time, TH

101

101

ns

The (I) arrow indicates the negative edge of the enable is used for reference.

Electrical Characteristics over recommended operating free air temperature range,
All typical values are measured at Vcc = 5V, T A = 25 D C,
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC

VOH

High Level Output
Voltage

VCC = 4,5V
VIL = VII:' MAX

10H
, VOL

Low Level Output
Voltage

Min

Typ

= 4,5V II = -18mA

= - 4OOIlA

VCC = 4,5V
VIH = 2V

Max

Unit

-1,5

V

54ALS
10H = -lmA

2.4

3,2

V

74ALS
10H = -2,6mA

2.4

3,3

V

54/74ALS

V

VCC -2

54/74ALS
10l = 12mA

0,25

0.4

V

74AlS
10L = 24m A

0,35

0,5

V

II

Max.High Input Current

VCC

= 5,5V VIH = 7V

0.1

mA

IIH

High Level Input Current

VCC

= 5,5V VIH = 2,7V

20

IlA

ILL

Low Level Input Current

VCC

= 5,5V VIL = MV

-0,1

mA

10

OutPlJt Drive Current

VCC

= 5,5V

-112

mA

IOZH

Off-State Output
Current, High level
Voltage Applied

VCC = 5,5V VIH
Vo = 2,7V

= 2V

20

IlA

IOZl

Off-State Output
Current, Low Level
Voltage Applied

VCC = 5,5V VIH
Va = O.4V

= 2V

-20

IlA

ICC

Supply Current

VCC = 5,5V
Outputs Open

54/74AlS
Va = 2,25V

-30

Outputs High

10

17

mA

Outputs Low

15

24

mA

Outputs Disabled

15,5

27

mA

2-200

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vcc = 5V, TA = 25°C.
DM74ALS563

DM54ALS563
Parameter

From

To

Data

AnyO

Conditions

Min

Typ

Max

Min

Typ

Unit

Max

3

21

3

18

ns

TpHL

3

15

3

14

ns

TpLH

8

29

8

22

ns

8

22

8

21

ns

4

21

4

18

ns

4

21

4

18

ns

2

10

2

8

ns

3

15

3

13

ns

TpLH

Enable

AnyO

TPHL
TPZH
TpZL

Output

TpHZ

Control

VCC = 4.5V to 5.5V
RL = 500!l
CL = 50 pF

AnyO

TpLZ
Note 1: See Section 1 for test waveforms and output load.

Logic Diagram

1D

'

2D

J

"

4

4D

5

50

50

Function Table

L
L
L
H

H
H
L

X

a

16

40

15

50

14

60

13

7ii

6

1

+----+---1
11

I---ct>---'-'Q
ENABtE G

Enable
G

D
H
L

X
X

L - low State. H - High State. X - Don·t Care
Z - High Impedance State
00 - Previous Condition of

lO-'-----+--l

an

Output
Control

"':':"---I>cr-'

TlIF16225·2

2·201

Output

Q
L
H
00
·Z

~

~,....

it)

~ National

a

Semiconductor

:E

c DM54ALS564/DM74ALS564 Octal D-Type
~ Edge-Triggered Flip-Flops with TRI-STATE® Outputs

~

!:E
c

General Description

Features

These B-bit registers feature totem-pole TRI-STATE outputs designed specifically for driving highly-capacitive or
relatively low-impedance loads. The high-impedance state
and increased high-logic-level drive provide these registers with the capability of being connected directly to and
driving the bus lines in a bus-organized system without
need for interface or pull-up components. They are particularly attractive for implementing buffer registers, 1/0 ports,
bidirectional bus drivers, and working registers.

•
•

The eight flip-flops of the ALS564 are edge-triggered inverting D-type flip-flops. On the positive transition of the clock,
the Q outputs will be set to the complement of the logic
states that were set up at the D inputs.

Absolute Maximum Ratings

A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and Vee Range.
• Advanced Oxide-Isolated, lon-Implanted Schottky TIL
Process.
• TRI-STATE Buffer-Type Outputs Drive Bus Lines Directiy.

Suppiy Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS564
DM74ALS564
Storage Temperature Range

(Note 1)
7V
7V

-55°e to 125°e
to 70 0
-65°e to 1.50o e

ooe

e

Nole 1: The "Absolute Maximum Ratings" .are those value. beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric. values defined In the
"Eleclrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actus I device operation.

Connection ·Diagram

Dual-In-Llne Package

TLlF16225·1

DM54ALS564 (J) DM74ALS564 (J, N)

2-202

Recommended Operating Conditions
DM54ALS564
Parameter

Supply Voltage, VCC
High Level Input Voltage, VIH

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2
0.8
-1

High Level Output Current, IOH
Low Level Output Current, IOL

12
0

Clock frequency, fCLOCK

Data Setup Time, TSU
Data Hold Time, TH

25

0

Unit

V
V

2

Low Level Input Voltage, VIL

Width of Clock Pulse, TW

DM74ALS564

0.8

V

-2.6

mA

24

mA

30

MHz

High

16.5

14

ns

Low

16.5

'14

ns

151

151

ns

41

01

ns

The (1) arrow Indlcat~s the positive edge of the Clock IS used for reference.

•

2-203

~
en

:;!

Electrica, Characteristics over recommended operating free air temperature range.
All typical values are measured at 'Icc = 5'1, TA = 25°C.

~

Symbol

Parameter

Conditions .

c

'11K

Input Clamp Vqltage

'ICC = 4.5'1, II = -18mA

VOH

High Level Output
Voltage

'ICC = 4.5V
VIL = VIL MAX

:IE

~

~

~

10H

:IE

c

VOL

Low Level Output
Voltage

=

Min

Typ

Max

Unit

-1.5

V

54ALS
10H = -1mA

2.4

3.2

V

74ALS
10H = -2.6mA

2.4

3.3

V

54/74ALS

-400!LA

VCC = 4.5V
VIH = 2V

V

VCC -2

54/74ALS
10L = 12mA

0.25

0.4

V

74ALS,
10L = 24mA'

0.35

0.5

V

II

Max High Input Current

VCC = 5.5V, VIH = 7V

0.1

mA

IIH

High Level Input Current

VCC=5.5V, VIH=2,7V

20

!LA

IlL

Low Level Input Current

VCC=5.5V, VIL=0.4V

-0.2

mA

10

Output Drive Current

VCC

-112

mA

10ZH

Off-State Output
Current. High Level
Voltage Applied

VCC = 5.5V, VIH = 2V
Vo = 2.7'1

20

!LA

10ZL

Off-State Output
~urrent, Low Level
Voltage Applied

VCC=5.5V, VIH =2V
Vo = O.4V

-20

!LA

ICC

Supply Current

VCC = 5.5V
Outputs Open

=

54/74ALS
Vo = 2.25V

5.5V

-30

Outputs High

10.5

17

mA

Outputs Low

15

24

mA

Outputs Disabled

16

27

mA

2·204

Switching Characteristics

over recommended operating free air temperature range (Note 1)
DM74ALS564

DM54ALS564
Parameter'

From

To

Conditions

Min

Typ

Max

Min

25

FMAX
TPLH

Clock

AnyO

TpHL
Output
Control

TpZH
TpZL

AnyO

Vce = 4,5V to 5,5V
RL = 500 n
CL = 50 pF

Typ

Unit

Max

30

MHz

4

15

4

14

ns

4

1,5

4

14

ns

4

21

4

18

ns

4

21

4

18

ns

TpHZ

2

10

2

8

ns

TpLZ

3

15

3

13

ns

Notal: See Section t for test waveforms and output load,

Logic Diagram

Function Table
Output
Control
L

10

'

, L

L
H

20

3D

4

4D

5

50

~O

16

'Q

a

'
15 5Q

60

7

7D

14

60'

13

iq

12

sO'

8

80 '

CLOCK

0

1
1
L
X

H
L
X
X

L ~ Low State, H ~ High State, X - Don't Care
I = Positive Edge Transition
Z ~ High Impedance State
00 - Previous Condition of

J
18

Clock

..;."'----1>0--1
TLlF/6225·2

2·205

' Output

Q
L
H
00
Z

~r------------------------------------------------------------------------,

~«

~National

a

Semiconductor

t!
:E DM54ALS573/DM74ALS573 Octal D-Type Transparent
c
Latches with TRI-STATE® Outputs

~

U)

...I

~
:E
c

General Description

Features

These B·bit registers feature totem·pole TRI·STATE out·
puts designed specifically for driving highly·capacltive or
relatively low·impedance loads. The high·lmpedance state
and increased high·logic·level drive provide these regis·
ters with the capability of being connected directly to and
driving the bus lines in a bus·organized system without
need for Interface or pull·up components. They are particu,
larly attractive for Implementing buffer registers, 1/0 ports,
bidirectional bus dr.ivers, and working registers.
The eight latches of the ALS573 are transparent O-type
latches meaning that while the enable (G) is high the Q outputs will follow'the data (0) inputs. When the enable is taken
low the output will be latched at the level of the data that
was set up.

•
•

A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines sign ificantly.
The output control does not affect the internal operation of
the latches. That is, the old data can be retained or new data
can be entered even while the outputs are off.

•
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and Vee Range.
Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
Functionally Equivalent with LS373.
Improved Ae Performance Over LS373 at
Approximately Half the Power.

• TRI·STATE Buffer·Type Outputs Drive Bus Lines
Directly.

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS573
OM74ALS573 .
Storage Temperature Range

(Note 1)
7V
7V

-55°C to 125°C
ooe to 70°C
-6Soe to IS00e

Note 1: The "Absolute Maximum Ratings" are those values bayond
which the safety of the device can not ba guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guarantead at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Dual·ln·Llne Package

TLlF/6226-1

54ALS573 (J)

74ALS573 (J,N)

2·206

Recommended Operating Conditions
DM74ALS573

DM54ALS573
Parameter

Min

Nom

Max

4.5

5

5.5

Supply Voltage, VCC
High Level Input Voltage, VIH

Min.
4.5

Nom

Max

5

5.5

2·

2

Unit
V
V

-.
0.8

Low Level Input Voltage, VIL

-1

High Level Output Current, 10H
Low Level Output Current, 10L

12

0.8

V

-2.6

mA

24

mA

Width of Enable Pulse, High or Low

15

15

ns

Data Setup Time, TSU

101

101

ns

71

71

ns

Data Hold Time, TH

The (.) arrow mdlcates the negatIve edge of the enabJe IS used for reference.

Electrical Characteristics

over recommended operating free air temperature range.

All typical values are measured at Vee = 5V, TA = 25°C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.5V, II = -18mA

VOH

High Level Output
Voltage

VCC ~ 4.5V
ViL ~ VIL MAX

10H
VOL

Low Level Output
Voltage

~

-400/iA

VCC ~ 4.5V
VIH ~ 2V

Min

54ALS
10H ~ -1mA

2.4

74ALS
10H ~ -2.(jmA

2.4

54/74ALS

Typ

Max

Unit

-1.5

V

3.2

V

3.3

V

V

VCC -2

54/74ALS
10L ~ 12mA

0.25

0.4

V

74ALS
10L ~ 24mA

0.35

0.5

V

II

Max High Input Current

VCC = 5.5V, VIH = 7V

0.1

mA

IIH

High Level Input Current

VCC = 5.5V, VIH = 2.7V

20

/i A

IlL

Low Level Input Current

VCC=5.5V, VIL=0.4V

-0.1

mA

10

Output Drive Current

VCC

-112

mA

10ZH

Off-State Output
Current, High Level
Voltage Applied

VCC = 5.5V, VIH = 2V
,
Vo ~ 2.7V

20

/i A

10ZL

Off-State Output
. Current, Low Level
Voltage Applied

VCC = 5.5V, VIH = 2V
Vo ~ O.4V

-20

/i A

ICC

Supply Current

ycc

~

5.5V

c= 5.5V
Outputs Open

54/74ALS
Vo ~ 2.25V

-30

Outputs High

10

17

mA

Outputs Low

15

24

mA

Outputs Disabled

15.5

27

mA

2·207

C"')

t;
Switching Characteristics over recommended operating free air temperature range (Note 1).
UJ
..J

«

~
::2:

c

C"')

~

All typical values are measured at Vcc = 5V, TA = 25°C.

DM54ALS573
Parameter

To

Data

AnyQ

Conditions

Min

Typ

DM74ALS573

Max

Min

Typ

Unit

Max

2

15

2

14

ns

TPHL

2

15

2

14

ns

TpLH

8

25

8

'20

ns

TpLH

~
IJ)

TpHL

::2:

TPZH

c

From

Enable

TpZL

Output

TpHZ

Control

VCC = 4.5V to 5.5V
RL = 500 n
CL = 50 pF

AnyQ

AnyQ

iPLZ

8

22

8

19

ns

4

21

4

18

ns

4

21

4

18

ns

2

12

2

10

ns

2

15

2

12

ns

Nota 1: See Section 1 for test waveforms and output load.

Logic Diagram'

Function Table
Output
Control

Enable

L
L
L
H

H
H
L
X

G

0

Output
Q

H
L
X
X

H
L
Qo·
Z

10-'------1

L - Low State, H - HIgh State, X - Don't Care
Z - High Impedance State
00 - Previous Condition of 0

19

10

18

20

17

30

" -=-----+-1
30..:.'--:_ _+--1

4D -"5_ _ _-1--1
16 40

5'

-=------+-1

6D

-'------1-1
Hf---<>I>----'I4.:... 6Q

10

-=-----+-1

8D

-'------t--i
12

80

ENABLE G..:.lI,---{)o-...J

TL/F/6226·2

2-208

~National

D Semiconductor
DM54ALS574/DM74ALS574 Octal D-Type
Edge-Triggered Flip-Flops with TRI-STATE® Outputs
General Description

Features

These 8-bit registers feature totem-pole TRI-STATE outputs designed specifically for drivirig highly-capacitive or
relatively low-impedance loads_ The'high-impedance state
and increased high-logic-level drive provide these registers with the capability of being connected directly to and
driving the bus lines in a bus-organized system without
need for interface or pull-up components. They are particularly attractive for implementing buf.fer registers, I/O ports,
bidirectional bus drivers, and working registers.

•
•

The eight flip-flops of the ALS574 are edge-triggered Dtype flip-flops. On the positive transition of the clock, the 0
outputs will be set to the logic states that were set up at the
D inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines sig'
nificantly.
The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and Vee Range.
Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
Functionally Equivalent with LS374.
Improved Ae Performance Over LS374 at
Approximately Half the Power.

•
•
•

• TRI-STATE Buffer-Type Outputs Drive Bus Lines
Directly.

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS574
DM74ALS574
Storage Temperature Range

(Note 1)

7V
7V
-55°e to 125°e
ooe to 70 0 e
-65°e to 150 0 e

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table arB not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram
Dual-ln·Line Package

54ALS574 (J)

74ALS574 (J,N)

Function Table
Output
Control

Clock

L
L
L

i

L

H

X

• L - Low State. H

r=

=

High State. x

D

H
L
X
X

=

Output
Q

H
L

00
Z

Don't Care

Positive Edge Transition

Z = High Impedance State
00 - Previous COndition of

a
2·209

TLil/6110-1

t!
It)

~

c(

Recommended Operating Conditions
DM54ALS574

t!

Parameter

c

Supply Voltage, VCC

:!E

~

~

,

High Level Input Voltage, V,H

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Low Level Input Voltage, V,L

0.8

High Level Output Current, IOH

c

Low Level Output Current, IOL

-1
12
30

0

Clock frequency, fCLOCK
Width of Clock Pulse, TW

'0

50

'0

70

-2.6

mA

24

mA

35

MHz

Low.

16.5

14

151-

151

ns

41

01

ns

~L~'----~>----'

30

V

14

The (I) arrow indicates the positive edge of the Clock is used for reference.

20

0.8

16.5 -

Data Hold Time, TH

'0

V

High

Data Setup Time, TSU

Logic Diagram

0

Unit

V

2

2

~

:!E

DM74ALS574

Min

2
19

TO

II

2Q

17

30

16

40

15

50

14

60

'3

7Q

3

•

5

•

7

8

80 9

CLOCK ...:,':....'---{>O-~

f----cI>--~'2O"8Q

TLlL/6110·2

2·210

ns
ns

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vcc = 5V, TA = 25°C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC =4.5V, II = -18mA

VOH

High Level Output
Voltage

VCC = 4.5V
VIL = VIL MAX

VOL

Low Level Output
Voltage

Min

Typ

54ALS
10H = -lmA

2.4

3.2

74ALS
10H = -2.6mA

2.4

3.3

Max

Unit

-1.5

V
V

.'

V

10H = -400/lA

54/74ALS

VCC = 4.5V
VIH = 2V.

54/74ALS
10L = 12mA

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

V

VCC -2'

II

Max High Input Current

VCC = 5.5V, VIH = 7V

0.1

mA

IIH

High Level Input Current

VCC = 5.5V, VIH = 2.7V

20

/lA

IlL

Low Level Input Current

VCC = 5.5V, VIL = O.4V

-0.2

mA

10

Output Drive Current

VCC = 5.5V

-112

mA

10ZH

Off-State Output
Current, High Level
Voltage Applied

VCC = 5.5V, VIH = 2V
Vo = 2.7V

20

/lA

10ZL

Off-State Output
Current, Low Level
Voltage Applied

VCC = 5.5V, VIH =2V
Vo = O.4V

-20

/lA

ICC

Supply Current

VCC = 5.5V
Outputs Open

-30

54/74ALS
Vo = 2.25V

Outputs High

11

18

mA

Outputs Low

17

27

mA

Outputs Disabled

17

28

mA

Switching Characteristics ~ver recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V, TA = 25°C.
DM74ALS574

DM54ALS574
Parameter

From

To

Conditions

Min

Typ

Max

Min

Typ

Max

Unit
MHz

FMAX

30

TpLH

4

15

4

14

ns

4

15

4

14)

ns

4

21

4

18

ns

4

21

4

18

ns

2

12

2

10

ns

2

15

2

12

ns

Clock

AnyQ

TpHL
TPZH
TpZL
TpHZ
TpLZ

..

Output
Control

AnyQ

Output
Control

Any Q

VCC = 4.5V to 5.5V
RL = 500 f!
CL = 50 pF

Note 1: See Section 1 for test waveforms and output load.

2·211

35

~National

a

Semiconductor

DM54ALS576/DM74ALS576 Octal' D-Type
Edge-Triggered Flip-Flops with TRI-STATE® Outputs
General Description

Features

These B-bit registers feature totem-pole TRI:STATE outputs designed specifically for driving highly-capacitive or
relativE'ly low-impedance loads. The high-impedance state
and increased high-logic-level drive provide these registers with the capability of being connected directly to and
driving the bus lines in a bus-organized system without
'need for interface or pull-up components. They are particularly attractive for implementing buffer registers,110 ports,
bidirectional bus drivers, and working registers.

•
•

The eight flip-flops of the ALS576 are edge-triggered inverting D-type flip-flops. On the positive transition of the clock,
the
outputs will be set to the complement of the logic
states that were set up at the D inputs.

Absolute Maximum Ratings

a

A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state th~ outputs neither load nor drive the bus lines significantly.
The output control do~s not affect the internal operation of
the flip-flops. That is, -the old data can be retained or new
data can be entered even while the outputs are off.

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and Vee Range.
• Advanced Oxide-Isolated, lon-Implanted Schottky TIL
Process.
• TRI-STATE Buffer-Type Outputs Drive Bus Lines
Directly.

(Note 1)

7V
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature Range
-55°e to 125°e
DM54ALS576
ooe to 70 0 e
DM74ALS576
. -65°e to 150 0 e
Storage Temperature Range
Nole 1: The "Absolute Maximum Ratings" are those values beyond
, which the safety of the device can not be guaranteed. The device.should
nol be operated at these limits. The parametric. values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Condltions"table will
define the conditions for actual device operation.

Connection Diagram

Dual-In-Llne Package

TLfF/6228-1

54ALS576 (J)

74ALS576 (J,N)

2-212

c

s:

Recommended Operating Conditions

(11

DM74ALS576

DM54ALS576
Parameter

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Unit

~

r-

OO
(11

Supply Voltage, VCC
High Level Input Voltage, VIH

2

V

2

Low Level Input Voltage, VIL

0.8
-1

High Level Output'Current, IOH

V

........

-s:
Q)

C

~

0.8

V

-2.6

mA

r-

24

mA

Q)

30

MHz

OO
(11

Low Level Output Current, IOL

12

Width of Clock Pulse, TW

Data Setup Time, TSU .
Data Hold Time, TH

25

0

Clock frequency, fCLOCK

0

High

20

16.5

ns

Low

20

16.5

ns

151

151

ns

41

01

ns

The (0 arrow Indicates the positive edge'of the Clock IS used for reference.

2·213

........

U)r----------------------------------------------------------------------------

It;
~
c(

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vcc = 5V, TA = 25 D C.

~

Symbol

:e

Parameter

Conditions

c

VIK

Input Clamp Voltage

VCC=4.5V, 11= -18mA

~

VOH

High Level Output
Voltage

VCC = 4.5V
VIL = VIL MAX

Lt)

en
...I

~

:e
c

10H
VOL

Low Level Output
Voltage

Min

= -400"A

,.

Max

Unit

-1.5

V

54ALS
IOH = -1mA

2.4

3.2

V

74ALS
10H = -2.6mA

2.4

3.3

V

54/74ALS

VCC = 4.5V
VIH = 2V

Typ

V

VCC -2

54/74ALS
IOL = 12mA

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

0.1

mA

20

"A

-0.2

mA

-112

mA

"A

II

Max High Input Current

VCC=5.5V, VIH=7V

IIH

High Level Input Current

VCC=5.5V, VIH=2.7V

IlL

Low Level Input Current

VCC=5.5V, VIL='0.4V

10

Output Drive Current

VCC

IOZH

Off-State Output
Current, High Level
Voltage Applied

VCC = 5.5V, VIH = 2V
Va = 2.7V

20

IOZL'

Off-State Output
Current, Low Level
Voltage Applied

VCC = 5.5V, V,H = 2V
Vo = O.4V

-20

ICC

Supply Current

VCC = 5.5V
Outputs Open

= 5.5V

.

54/74ALS
Va = 2.25V

-30

. "A

Outputs High

10

17

mA

Outputs "Low

15

24

mA

Outputs Disabled

16

27

mA

2·214

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are

me~sured

at Vcc = 5V, TA = 25°C.
DM54ALS576

Parameter

From

To

Conditions

Min

FMAX
TpLH

Clock

AnyQ

TpHL
Output
Control

TpZH
TpZL

AnyQ

VCC = 4.5V to 5.5V
RL = 500!l
CL = 50 pF

I

Typ

DM74ALS576

Max

Min

Typ

Unit

Max

MHz

25

30

4

15

4

14

ns

4

15

4

14

ns

4

21

4

18

ns

4

21

4

18

ns

TpHZ

2

10

2

8

ns

TpLZ

3

15

3

13

ns

Note 1: See Section 1 for test waveforms and output load.

Logic Diagram

Function Table

~~~~:,~'----~>---~

lD

2D

2

3D

4

4D

'

20'

" '0
"

6

"

7

70

'

"

'Q

12

BO'

Clock

0

L
L
L
H

1
1
L
X

H
L
X

L ~ Low State. H ~ High State, X
1 = Positive Edge Transition
Z ~ High Impedance State
00 = Previous Condition of 0

J
18

Output
Control

,o'....:':....----+--I
ClOCK..;'.:...'--.r--.-J

TLlF/6228·2

2-215

X
~

Don't Care

Output

Q
L
H
00
Z

•

~ ~National
~ D Semiconductor
~
2:

-

c DM54ALS580/DM74ALS580 Octal D-Type
~

~
..J

~2:
c

Transparent Latches with TRI-STATE® Outputs
General

Descripti~n

Features

These 8-bit registers feature totem-pole TRI-STATE, outputs designed specifically for driving highly-capacitive or
relatively low-impedance loads. The high-impedance state
and increased high-logic-level drive provide these regis• ters with the capability of being connected directly to and
driving the bus lines in a bus-organized system without
need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
The eight inverting latches of the ALS580 are transparent
D-type latches meaning that while the enable (G) is high the
Q outputs will follow the complement of the data (D) inputs.
When the enable is taken low the output will be latched at
the complement of the level of the data that was set up.
A buffered output control 'input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
the latches. That is, the old data can be retained or new data
can be.entered even while the outputs are off.

•
•
•

Switching Specifications at 50pF.
Switching Specifications Guaranteed Over Full
Temperature and Vee Range.
Adv'anced, Oxide-Isolated, lon-Implanted Schottky TTL
Process.

• TRI-STATE Buffer-Type Outputs Drive Bus Lines
Directly.

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS580
DM74ALS580
Storage Temperature Range

(Note 1)

7\;
7V
-55°C to 125°C
ooe to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Rallngs" are those values beyond
which the safety of the device can not be guaranteed. The device shoutd
not be operated at these limits. Ttie parametric vatues defined In the
"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommended Operallng Condltlons"table will
define the conditions for actual device operation.

Connection Diagram
Dual-In-Line Package

TLlF/6229-1

54ALS580 (J)

74ALS580 (J,N)

2-216

c

Recommended Operating Conditions

3:
UI

DM54ALS580
Parameter

DM74ALS580

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Supply Voltage, VCC
High Level.lnput Voltage, VIH

2

r-

V

-c

V

2

~

Unit

en
UI
CO

o

3:

~

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Current. 10H

-1

-2.6

mA

r-

Low Level Output Current, 10L

12

24

mA

CO

en

UI

Width of Enable Pulse, High or Low

15

15

ns

Data Setup Time, TSU

101

101

ns

Data Hold Time, TH

101

101

ns

The (.) arrow Indicates the negative edge of the enable IS used for reference.

Ele,ctrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vce = 5V, TA = 25'C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC=4.5V,II= -18mA

VOH

High Level Output
Voltage

VCC = 4.5V
VIL = VIL MAX

VOL

Low Level Output
Voltage

Min

Typ

Max

Unit

-1.5

V

54ALS
10H = -lmA

2.4

3.2

V

74ALS
10H = -2.6mA

2.4

3.3

V

10H = -400",A

54/74ALS

VCC =.4.5V
VIH = 2V

54/74ALS
10L = 12mA

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

V

VCC -2

II

Max High Input Current

VCC = 5.5V, VIH = 7V

0.1

mA

IIH

High Level Input Current

VCC = 5.5V, VIH = 2.7V

20

",A

IlL

Low Level Input Current

VCC=5.5V, VIL=O.4V

-0.1

mA

10

Output Drive Current

VCC = 5.5V

-112

mA

10ZH

Off-State Output
Current, High Level
Voltage Applied

Vce = 5.5V, VIH = 2V
Vo == 2.7V

20

",A

10ZL

Off-State Output
Current, Low Level
Voltage Applied

VCC=5.5V, VIH =2V
Vo = O.4V

-20

",A

ICC

Supply Current

VCC = 5.5V
Outputs Open

54/74ALS
Vo = 2.25V

-30

Outputs High

10

17

mA

Outputs Low

15

24

mA

Outputs Disabled

15.5

27

mA

. 2-217

o

·M
Switching Characteristics
~

over recommended operating free air temperature range (Note 1).

All typical values are measured at Vcc = 5V, TA = 25"C.

---~

,
to

2

'I 20

0
11

30

.. ~-------+--1
'6 00
5D

6

6D

7

Enable

L
L
L
H

H
H
L

H
L

X

'X

G

D

X

L - Low State, H = High State, X - Don't Care
Z = High Impedance State
00 = Previous Condition of 0

10 3

3D

Output
Control

" '0

70...!..-------+--1

10..;;·-------1---1
1-----0[>-----''''-10
ENABLE G -,-',--'--11>0-'

TLIF16229-2

2-218

Output
~

L
H
00
Z

r----------------------------------------------------------,c

s:

~National

;r-

~ Semiconductor·

I-

DM54ALS620A/DM74ALS620A Octal TRI·STATE®
Bus Transceiver

c

s:
~
l:o

General Description
This advanced low power Schottky device contains 8 pairs
of TRI-STATE logic elements configured as an octal bus
transceiver. It is designed for use In memory, microprocessor systems and in asynchronous bidirectional
data buses. Data transmission from the A bus to the B bus
or from the B bus to the A bus is selectively controlled by
(GBA and GAB) the enable inputs. These inputs are also
used to disable the devices so that the buses are effectively isolated.

• Local bus-latch capability
• Switching response specified into 50011/50 pF
• Switching specifications guaranteed over full
temperature and Vcc range
• Low output Impedance to drive terminated
transmission lines to 1331l

The dual-enable configuration gives the A LS620A !!Ie capability to store data by simultaneous enabling of GBA and
GAB. Each output reinforces its input in this transceiver
configuration. Thus, when both control inputs are enabled
and all other data sources to the two sets of bus lines are
at high impedance, both sets of bus lines will remain at
- their last logic states.

SupplyVollage, Vcc
Input Voltage
Storage Temperature Range
- 65·C to
Lead Temperature (Soldering, 10 seconds)

Features
• TRI-STATE outputs on A and B buses

Function Table

Dual-In-Line Package
IIBA

lB

2B

3B

4B

5B

6B

7B

BB

Enable Inputs
GBA

GAB

Operation

L

L

B Data to A Bus

H

H

Ii. Data to B Bus

H

L

Hi-Z

L

H

B Data to A Bus
A Data to B Bus

TOP VIEW

54ALS620A (J)

7V
7V
+ 150·C
+ 300·C

Note 1: The "Absolute MaxImum. Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will .
define the conditions for actual device operation .

Vee

~

Absolute Maximum Ratings (Note 1)

• Ad,vanced oxide-isolated, ion implanted Schottky
process

Connection Diagrams

i

TUFI6230-1

74ALS620A (J, N)

2-219

"-

Recommended Operating Conditions
Symbol

DM54ALS620A

Parameter

DM74ALS620A

Min

Typ

Max

4.5

5

5.5

Units

Min

Typ,

Max

4.5

5

5.5

V

0.8

0.8

V

"

Vee

Supply Voltage

VIH

High Level'lnput Voltage

VIL

Low Level Input Voltage

10H

High Level Output Current

-12

-15

mA

10L

Low Level Output Current

12

24

mA

48

mA

70

·C

2

2

V

DM74ALS620A·1,Option Only
TA

Operating Free Air Temperature

-55

125

0

Electrical Characteristics over recommended operating free air temperature range.
All typic!!1 values are measured at Vee = 5V, TA = 25·C.
Symbol

Parameter

Conditions

VIK

Input Clamp
Voltage

Vee = 45V, liN = -18 mA

VOH

High Level"
Output Voltage

Vee = 4.5V, 10H = - 3 mA
Vee = 4.5V, 10H = Max
10H= -0.4mA,
VOL = 4.5V to 5.5V

VOL

Low Level
Output Voltage

Vee = 4.5V

Max

Min

Typ

2.4

-1.5
2.4

3.2

Max

3.2

Units
V
V

2

2

V

Vee- 2

Vee- 2

V
0.25

0.4

V

IOL=24 mA

0.35

0.5

V

For 74ALS·1
Option Only
IOL=48 mA

0.35

0.5

V

0.1

mA

Input Current at
Max Input
Voltage

Vee =5.5V, VIN =7V
(VIN = 5.5V for A or B Ports)

IIH

High Level.
Input Current

Vee='5.5V,
VIN=2.7V

' 'lW Level Input

Vee = 5.5V,
VIN =0.4V

Current

Typ

-1.5

0.25

IOL=12mA

II

IlL

DM74A1S620A

DM54ALS620A
Min

0.4

0.1

Aor B Ports

20

20

mA

Control Inpuis

20

20

rnA

A or B Ports

-0.1

-0.1

rnA

Control Inputs

-0.1

-0.1

rnA

-112

rnA

10

Output Drive
Current

Vee = 5.5V, VouT =2.25V

Icc

Supply Current

Vee = 5.5V

-30

-112

-30

Output High

24

39

24

34

rnA

Output Low

25

49

31

44

rnA

TRI·STATE

27

52

33

47

rnA

2·220

Switching Characteristics over recommended operating free air temperature range (Notes 1 and 2)
All typical values are measured at vcc= 5V, TA=25°C.
Symbol
tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

Min

~
A

B

~

B

tpZL

Output Enable Time to Low Level

tpzH

Output Enable Time to High Level

tpLZ

Output Disable Time from Low Level

tpHZ

Output Disable Time from High Level

tpZL

DM54ALS620A

Circuit
Configuration

Parameter

A

~

GBA

, Output Enable Time to Low Level

OUT

A

'~

GAB.

tpZH

Output Enable Time to High Level

tpLZ

Output Disable Time from Low Level

tpHZ

Output Disable Time from High Level

OUT·

B

Nole 2: Swllching characteristic conditions are

,

,

2-221

Typ

Max

Units

Min

2

12

2

10

ns

2

12

2

10

ns

2

12

2

10

ns

2

12

2

10

ns

5

31

5

25

ns

3

23

3

17

ns

3

22

3

18

ns

2

14

2

12

ns

5

31

5

25

ns

3

23

3

18

ns

3

22

3

18

ns

2

14

2

12

ns

VCC =4.5V to 5.5V, RL = soon, CL = 50 pF.

-

DM74ALS620A

Max

Nole I: ,See Section 1 for test waveforms and output load.

Typ

~National

~ Semiconductor
DM54ALS621 AI DM74ALS621 A,
DM54ALS622A/DM74ALS622A
Octal Open Collector Output Bus Transceivers
General Description

Features

These advanced low power Schottky devices contain 8
pairs of logic elements configured as octal bus
transceivers. They are designed for use In memory, microprocessor systems and In asynchronous bidirectional
data buses. Data transmission from the A bus to the B bus
or from the B bus to the A bus Is selectively controlled by
(GBA and GAB) the enable Inputs. These inputs are also
used to disable the devices so that the buses are effectively isolated.
.
The dual-enable configuration gives the ALS621A and
ALS622A the capability to store data by simultaneous
enabling of GBA and GAB. Each output reinforces its in·
put In this transceiver configuration. Thus, when both control Inputs are enabled and all other data sources to the
two sets of bus lines are at high Impedance, both sets of
bus lines will remain at"thelr last logic states.

• Advanced oxide-isolated, ion Implanted Schottky
process
• Choice of true or Inverting logic
• Open collector outputs on A and B buses
• Local bus-latch capability
• Switching response specified Into soon/so pF
• Switching specification guaranteed over full
temperature and Vcc range
• Low output impedance to drive terminated
. transmission lines to 133n

Absolute Maximum Ratings (Note 1)
SupplyVoltage, Vcc
Input Voltage
Storage Temperature Range
- 6S·C to
Lead Temperature (Soldering, 10 seconds)

Pull·Up Resistor Equations
Vcc(Mln)~VOH

= NI (IOH) + N2 (IIH)
Vcc (Max) - VOL
RMIN = 10L - N3 (IIU
Where: NI (IOH) =total maximum output high current

Note I: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Condltlons"table will
define the conditions for actual device operation,

RMAX

for all outputs tied to pull-up resistor

=
=

N2 (lIH) total maximum Input high current for
all Inputs tied to pull-up resistor
N3(IIU total maximum Input low currentfor all
Inputs tied to pull-up resistor·

Connection Diagrams
~

w

Dual·ln·Llne Package
n H 0
~
"

fu~

~

~

~

u

~

~

n

~

~

54ALS621A(J)

Function Table

Dual·ln·Llne Package

e

~

fu

~

n'H

rn

w

~

~

~

u

0

~

9

n

~

~

~

~

TOP VIEW

TlIFI8231:,

TDPV1EW

-7V
7V
+ 1S0·C
+ 300·C

74ALS621A(J, N)

54ALS622A (J)

Enable Inputs

Operation

GBA

GAB

ALS621A

L
H
H
L

L
H
L
H

BData to A Bus
Ii Data to B Bus

ALS622A
B Data to A Bus
A Data to B Bus

'HI

Hi

B Data to A Bus

B Data to A Bus
A Data to B Bus

AData to B Bus
2-222

e

rn

TL{F/U3t.2

74ALS622A (J, N)

Recommended Operating Conditions
Symbol

DM74ALS621A
DM74ALS622A

DM54ALS621A
DM54ALS622A

Parameter

Units

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

V

Vcc

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.8

0.8

V

VOH

High Level Output Voltage

5.5

5.5

V

IOL

Low Level Output Current

12

24

mA

48

mA

70

DC

2

2

V

DM74ALS621A·1 and
DM74ALS622A·10ptions
Only
TA

-55

Operating Free Air Temperature

125

0

Electrical Characteristics over recommended operating free air tempera;ure range.
All typical values are measured at Vcc= 5V, TA=25 DC.

Symbol

DM54ALS621A
DM54ALS622A

Conditions

Parameter

Min
VIK

Input Clamp
Voltage

Vcc = 4.5V, liN = ~ 18 mA

IOH

High Level
Output

Vcc = 4.5V, VOH = 5.5V

VOL

Low Level
Output Voltage

Vcc=4.5V

Typ

DM74ALS621A
DM74ALS622A
Max

Min

Typ.

Units

Max

-1.5

-1.5.

V.

0.1

0.1

mA

0.25

0.4

V

IOL=24mA

0.35

0.5

V

For 74ALS·1
Option Only
IOL=48 mA

0.35

0.5

V

0.25

IOL=12mA

0.4

II

Input Current at Vcc= 5.5V, VIN =7V
Max Input
(VIN = 5.5V for A or B Ports)
Voltage

0.1

0.1

mA

IIH

High Level
Input Current

A or B Ports

20

20

p.A

Control Inputs

20

20

p.A

-0.1

-0.1

mA

IlL

Icc

Vcc= 5.5V,
VIN=2.7V

Low Level Input Vcc=5.5V,
Current
VIN =0.4V

Control Inputs

-0.1

mA

ALS621A
Vcc=5V
Supply Current

Outputs
High

29

45

29

40

mA

Outputs
Low

35

53

35

48

Outputs
High

11

20

11

15

Outputs
Low

20

33

20

28

.,
ALS622A
Supply Current

Vcc= 5.5V

A or B Ports

2·223

-0.1

Switching Characteristics over recommended operating free air temperature (Notes 1 and 2)
All typical values are measured at Vee = 5V, TA = 25°C.

Symbol

Parameter

DM54ALS621A
DM54ALS622A

Circuit Configuration

Min

Propagation Delay Time,
Low to High Level Output

10

45

10

33

ns

tpHL'

Propagation pelay Time,
High to Low Level Output

5

24

5

20

ns

tpLH
tpHL
tpLI·i
tpHL
tpLH
tpHL

Propagation Delay Time,
Low to High Level Output

10

45

10

33

ns

5

24

5

20

ns

10

47

10

39

ns

OUT

12

40

12

35

ns

~

10

47

10

39

ns

12

;40

12

35

'ns

18

42

18

35

ns

5

23

5

19

ns

18

42

18

35

ns

5

23

5

19

ns

8

45

8

38

ns

OUT

10

40

10

35

ns

~0;'

18

45

18

38

ns

10

40

10

35

ns

~

,

Propagation Delay Time,
High to Low Level Output
Propagation Delay Time,
Low to High Level Output
Propagation Delay Time,
High to Low Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

tpLH

Propagation Delay Til)1e,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output
Propagation Delay Time,
Low to High Level Output
Propagation Delay Time,
High to Low Level Output

tPLH'

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

OUT

Max

ALS621A

Propagation Delay Time,
Low to High Level Output

Propagation Delay Time,
Low to High Level Output

tPHL'

IN

IN

Propagation Delay Time,
High to Low Level Output

tpLH

tpLH

~

Typ

Typ

Units

Max

Min
tpLH

DM74ALS621A
DM74ALS622A

OUT

ALS621A

~
ilaA

,

A

ALS621A
GAa

a

OUT

ALS621A

~
IN

OUT

ALS622A

~out

IN

ALS622A

~
iBA

A

ALS622A

GAB

ALS622A

Nole1: See Section 1 for test waveforms and output load.
Note 2: Switching characteristic conditions are

Vee::;: 4.5V to 5.5V, RL =500U, CL::;: 50 pF.

I

.
2·224

r---------------------------------------------------------------'c

3:

~National

U1

~

~ Semiconductor

i

DM54ALS623A/DM74ALS623A Octal TRI·STATE®
Bus Transceiver

!!c
3:

~
l>

General Description

r-

This advanced low power Schottky device contains 8 pairs
of TRI-STATE logic elements configured as an octal bus
transceiver. It is designed for use in memory, microprocessor systems and in asynchronous bidirectional
data buses. Data transmission from the A bus to the B bus
or from the B bus to the A bus is selectively controlled by
(GBA and GAB) the enable inputs. These inputs are also
used to disable. the devices so that the buses are effectively isolated.

• Local bus-latch capability
• SWitching response specified into 5000/50 pF
• Switching specifications guaranteed over full
temperature and Vee range
• Low output impedance to drive terminated
transmission lines to 1330

The dual·enable configuration gives the ALS623A the capability to store data by simultaneous enabliJlg of GBA and
GAB. Each output reinforces its input in this transceiver
configuration. Thus, when both control inputs are enabled
and all other data sources to the two sets of bus lines are
at high impedance, both sets of bus lines will remain at
their last logic states.

Absolute Maximum Ratings (Note 1)

Features
.' Advanced oxide-isolated, ion implanted Schottky
process
• TRI-STATE outputs on A and B buses

Connection Diagrams

G8A

20

19

18
18

~

I' 'T

Supply Voltage, Vee
7V
7V
InputVoltage
Storage Temperature Range
- 65'Cto + 150'C
Lead Temperature (Soldering, 10 seconds)
+ 300'C
Nota 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

28

117
I

38

4B

L6

15

5B
14

68

78

13

12

BB
11

I

Enable Inputs
t-

lli'7 I~ '71~ 71u '71~7 III '7 1~7 lu~

1 ~J3
2

W

~

Dual-In-Line Package

T
,

~

U

14 15
~ !

'-

'-

'-

r

r

r

1'6

M
TOP VIEW

'-

P 18 19

J10

~

TL/F18449·1

54ALS623A (J)

GAB

ALS623A

L

L

B Data to A Bus

H

H

A Data to B Bus

H

L

Hi-Z

L

H

B Data to A Bus

AData to B Bus

r:-

L A~

Operation

GBA

. 74ALS623A (J, N)

2-225

,

fII

Recommel1ded Operating Conditions
Symbol

DM54ALS623A

Parameter

"

Vee

Supply Voltage

V,H

High Level Input Voltage

V,L

Low Level Input Voltage

IOH
IOL

,
TA

DM74ALS623A '

Min

1YP

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

2

2

Units
V
V

0.8

0.8

High Level Output Current

-12

-15

mA

Low Level Output Current

12

24

mA

48

mA

70

°C

DM74ALS623A-1 Option Only
Operating Free Air Temperature

-55

125

0

V

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25°C.
Symbol

Parameter

V,K

Input Clamp
Voltage

VOH

High Level
Output Voltage

Conditions

Vee =4.5V, IOH =; -3 mA

IOH= -0.4 mA"
VOL = 4.5V to 5.5V
VOL

'I,

Low Level
Output Voltage

Typ

Vee = 4.5V

Max

Min

Typ

2.4

2.4

3.2

Max
-'1.5

-1.5

Vee = 4.5V, I'N= -18mA

Vee = 4.5V, IOH=Max

DM74ALS623A

DM54ALS623A
Min

3.2

Units
V
V

2

2

V

Vee- 2

Vee- 2

V
0.25

0.4

V

IOL=24 mA

0.25

0.35

0.5

V

For 74ALS-1,
Option Only
IOL=48mA

0.35

0.5

V

0.1

0.1

mA

10L= 12 mA

0.4

Input ,Current at
Max Input
Voltage

Vee = 5.5V, V,N=7V
(V,N = 5.5V for A or B Ports)'

High Level
Input Current

Vee=5.5V,
V'N=2.7V

Aor B Port!!

20

20

mA

Control Inputs

20

20

mA'

Low Level Input
Current

Vee = 5.5V,
V,N =0.4V

A or B Ports

-0.1

-0.1

mA

Control Inputs

-0.1

-0.1

mA

10

Output Drive
Current

Vee = 5.5V, VOUT = 2.25V

-112

mA

Icc

Supply Current

Vee = 5.5V

I'H
I,L

-30

-112

-30

Output High

32

48

32

43

mA

Output Low

39

55

39

50

mA

TRI-STATE

42

60

42

55

mA

2-226

Switching Characteristics over recommended operating free air temperature range (Notes 1 and 2)
All typical values are measured at Vee = 5V, TA=25°C.
Symbol
tpLH

Propagation Delay Time,
Low to High level Output

tpHL

Propagation Delay Time,
High to low level Output

tpLH

Propagation Delay Time,
. low to High level Output

tpHL

Propagation Delay Time,
High to low level Output

tpzL

Output Enable Time to low level

tpZH

Output Enable Time to High level

tpLZ

Output Disable Time from low level

tpHZ

Output Disable Time from High level

tPZL

Output Enable Time to low level

tPZH

Output Enable Time to High level

tpLZ

Output Disable Time from low level

tpHZ

Output Disable Time from High level

DM54ALS623A

Circuit
Configuration

Parameter

Min

Typ

Max

Units

Min

2

15

2

13

ns

3

13

3

11

ns

2

15

2

13

ns

3

13

3

11

ns

5

25

5

22

ns

.

5

25

5

22

ns

D~

2

23

2

19

ns

2

19

2

16

ns

5

25

5

22

ns .

5

25

5

22

ns

2

23

2

19

ns

2

19

2

16

ns

IN~DUT

~
ii

~

D~T

Note 1: See Section 1 for test waveforms and output load.
Note 2: Switching characteristic conditions are Vee = 4.5V to 5.5V,

DM74ALS623A

Max

IN~DUT

G

Typ

RL= 5000, eL = 50 pF.

)

2·227

~ ~National
ct

t!

::E

Q

~

~::E
Q

.....:

~

.....
::E
==
Q

~

==

Il)

:i
Q

PRELIMINARY

~ Semiconductor

DM54ALS677/DM74ALS677, DM54ALS678/DM74ALS678
Address Comparators
General Description

Features

The 'ALS677 and 'ALS678 address comparators simplify
addressing of memory boards andlor other peripheral
devices. The four P inputs are normally hard, wired with a
preprogrammed address. An internal decoder determines
what input information applied to the 16 A Inputs must be
low or highito cause a low state' at the output (Y). For ex·
ample, a positive-logic bit combination of 0111 (decimal 7)
at the P in~ut determines that Inputs A1 through A7 must
be low and that inputs A8 through A16 must be high to
cause the dutput to go low. Equality of the address applied
at the A inputs to the preprogrammed address is indicated
by the output being low.

•
•
•
•

The 'ALS677 features an enable input (<3). When G is low,
the device is enabled. When G Is high, the device is dis·
abled and the output is high, regardless of the A and P inputs. The' ALS678 features a transparent latch and a I/:Itoh
enable Input (C). When C is high, the device is in the
, transparent mode. When C is low, the previous logic state
of Y is latdhed.

'ALS677 Is a 16-bit to 4-bit comparator with enable'
'ALS678 is a Hi-bit to 4-bit comparator with latch
SWitching specifications at 50 pF
Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Switching specifications guaranteed over full
temperature and Vcc range

Absolute Maximum Ratings (Note 1)
7V

Supply Voltage,
Input Voltage
Storage Temperat,ure Range

7V
- 6S'Cto + 1S0'C

NOI. 1: The "Absolule Maximum Rallngs" are those values beyond
which Ihe safely of Ihe device ,cannol be guaranteed. The device should
nol be operaled al these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" tabie will
define the conditions for actual device operation.

Connection Diagrams
,?ual.ln.Line Package

Dual-In-Line Package
Vee

Al

24

Vee

A2

24

It

A2

23

C

A3

Y

A3

2~

Y

A4

P3

A4

2~

P3

A5

P2

A5

20

P2

AS

Pl

A6

19

P1

Al

A7

18

PO

A7

18

PO

AS

17

A16

A8

17

A16

A9

16

A15

A9

16

A15

15

A14

Al0

10

15

A14

Al0

, 'All

11

14

A13

All

11

14

A13

GNU

12

13

A12

GNU

12

13

A12

TOP ViEW

TDPVIEW
TLIFI6236·1

DM54ALS677 (J)

TL/F 16236·2

DM54ALS678 (J)

DM74ALS677 (J, N)

DM74ALS678 (J, N)

This document contains information on a product under development. NSC reserves the right to change or discontinue this product without notice.

2·228

Function Table·
G

C

P3

P2

P1

PO

A1

Inputs Common to 'ALS677 and 'ALS678
Output
Y
A2 A3 A4 AS A6 A7 A8 A9 A10 A11 A12 A13 A14 A1S A16

L
L
L
L

H
H
H
H

L
L
L
L

L
L
L
L

L
L
H
H

L
H
L
H

H
L
L
L

H
H
L
L

H
H
H
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
L
L
L

L
L
L
L

H
H
H
H

L
L
L
L

H
H
H
H

L
L
H
H

L
H
L
H

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

H
L
L
L

H
H
L
L

H
H
H
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
L
L
L

L
L
L
L

H
H
H
H

H
H
H
H

L
L
L
L

L
L
H
H

L
H
L
H

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

H
L
L
L

H
H
L
L

H
H
H
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
L
L
L

L
L
L
L

H
H
H
H

H
H
H
H

H
H
H·
H

L
L
H
H

L
H
L
H

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

H
L
L
L

H
H
L
L

H
H
H
L

H
H
H
H

L
L
L
L

L

H

'ALS677 'ALS678

H
L

All Other Combinations

H

'ALS677: Any Combination

H

'ALS678: Any Combination

Latched

'ALS677
(23)

'ALS678

(ADDRESS CDMP)
p", 1

=1

C20

&.t>

PO

PO
p",

P1

P1

P2
P3

p", 3

P2

p",

P3

A1

A1
p", 5

A2
A3

A4
AS
A6
A7
AS
A9

A10

(3)

Z3
(4)

Z4

(5)
(6)

Z6
Z7

Z8
(9)

Z9

(10)

A3

p",

A4

A13
(1S)
Z14
(16)

Z15

(17)

Z16

(19)
(20)
(21)
(1)
(2)

p", 1

='1

&.

1
p",

p",
p",

Z1

Z2
Z3

p", 5
p",

(4)
p", 7

AS
p",

p", 8

A6

p", 9

A7

p", 10

A8

10
p", 11

A9

(7)
Z7

p.<:!: 9

(S)

Z8
(9)

zg

(10)
A10

Z10
(11)

A11

Z11
(13)

12
p", 13

A14

A16

p",

11
p", 12

A12

(1S)

(3)

(8)

A11

A15

A2

Z5
(7)

(ADDRESS CDMP)

(23)

A12

Z12
(14)

13
p", 14

A13

Z13
(1S)

A14

14
P= 15
15

A15
A16
16

Z14
(16)
Z15
(17)

Z16

p", 10
10

p", 11
11
p", 12
12
p", 13
13
p", 14
14
p= 15
15
16

TUF/6236·4

TLlF/6236·3

2-229

co
.....
<0

en

Logic Diagrams (Positive Logic)

...I



A~:~

(16)
A15 120 )
P'tmt>
A16 121 )
P3llil!>

c

!>
TLlF16236·5

Pin numbers shown are for JT and NT packages.

2-230

TUF/6236-6

Recommended Operating Conditions
Symbol

DM54ALS677,678

Parameter

Vee

Supply Voltage

V1H

High Level Input Voltage

VIL

Low Level Input Voltage

10H

High Level Output Current

DM74ALS677, 678

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

2

V

-1

10L

Low Level Output Current
Operating Free Air Temperature
Range

V

2
0.8

TA

Units

12
-55

125

0.8

V

-2.6

mA

24

mA

70

"C

0

'Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee =5V, TA =25"C.
Symbol

Parameter

Conditions

Min

VIK

Input Clamp Voltage

VCC = 4.5V, liN = -18mA

VOH

High Level Output
Voltage

VCC = 4.5V, IOH = Max
IOH

VOL

= - 400 p.A, Vee =4.5 to 5.5V

VCC = 4.5V

Low Level Output
Voltage

2.4

Typ

Max

Unit

-1.5

V
V

3.2

VCC-2

V

(

54ALS
IOL = 12mA

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

II

Input Current at
Max Input Voltage

VCC = 5.5V, VIN = 7V

0.1

mA

IIH

High Level Input Current

VCC = 5.5V, VIN = 2.7V

20

p.A

IlL

Low Level Input Current

VCC = 5.5V, VIN = 0.4V

-0.1

mA

10

Output Drive Current

VCC = 5.5V, VOUT = 2.25V

-112

mA

33

mA

ICC

ALS677

Vec = 5.5V

Supply Current

,

ALS678

I

t

"

2-231

,
-30
0

18.2
17

Swit~hing

Characteristics over recommended operating free air temperature range (Note 1).

All typical values are Iileasured at Vcc = 5V, TA = 25°C.
Symbol

Parameter

tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

tpLH

Propagation Delay Time, G
Low to High Level Output (ALS667)

tpHL

Propagation Delay Time,
High to Low Level Output

tpLH

Propagation Delay Time, C
Low to High Level Output (ALS678)

tpHL

Propagation Delay Time,
High to Low Level Output

From
AnyP

DM54ALS677, 678 DM74ALS677,678

To

Conditions

y

Vee = 4.5V to 5.5V,
C L =50 pF,
R L =500fl

,

Typ

Max

Min

Typ

Max

4

18

28

4

18

25

ns

8

18

40

8

18

35

ns

5

14

26

5

14

22

ns

5

14

35

5

14

30

ns

3

10

15

3

10

13

ns

5

10

30

5

10

25

ns

y

Any A

Units

Min

y

y

14

14

ns

14

14

ns

Note 1: See Section 1 for test waveforms and output load.

,

Typical Application Information
The 'ALS677 and 'ALS678 can be wired to recognize any
one of 2 16 -1 addresses. The number of "lows" in the address determines the input pattern for the P inputs. Then
those system address lines that are low in the address to
,be recognized are, connected to the lowest numbered A inputs of the address comparator and the system address
lines that are high are connected to the highest numbered.
A inputs,
For example, assume the comparator is to enable a device
when the 16-bit system address is:
A10
A15
A14
A13
A12
A11
A9
A8
H'
H
H
L
H
L
L
L
A7
A6
A5
A4
A3
A2
A1
AO
H
H
L
L
H
H
H
H

Since the address contains 6 lows and 10 highs, the
following connections are made:
P3 to OV, P2 to Vee, P1 to Vee, and PO to OV.
System address IinesA13, A12, A9, A8, A5, and A4to comparator inputs A 1 through A6 in any convenient order.
The remaining ten system address lines to comparator inputs A7 through A16 in any convenient order.
The output provides an active·low enabling signal.
The following circuit is a modulo-N synchronous counter.
The 'ALS163 is connected to provide a lOW-level clear
signal when N = FEFF I6•

,

,

Modulo·N Synchronous Counter
15 12
8
4
0
FEFF1& = HHHH HHHL HHHH HHHH

.

4
'ALSI63
CTR 16

~
CLK

CLK

'ALS677
AODRESS
COMP

L!t::.
lR
Vee

Cl/+

0-7
8
9-15

---'pj"

B

LI
,7 \ .

PO

,15

*

EN

0
P

MAX COUNT

(P_l)
Al
A2-A16
TlIFf6236· 7

2-232

~National

PRELIMINARY

~ Semiconductor
DM54ALS679/DM74ALS679, DM54ALS680/DM74ALS680
Address Comparators
General Description

Features

The 'ALS679 and 'ALS680 address comparators simplify
addressing of memory boards and/or other peripheral
devices. The four P inputs are normally hard wired with a'
preprogrammed address. An internal decoder determines
what input information applied to the 12 A inputs must be
low or high to cause a low state at the output (Y). For ex·
ample, a positive·logic bit combination of 0111 (decimal 7)
at the P input determines that inputs A1 through A7 must
be low and ihat inputs A8 through A12 must be high to
cause the output to go low. Equality of the address applied
at the A inputs to the preprogrammed address is indicated
by the output being low.
The 'ALS679 features an enable input (G). When Gis low,
the, device is enabled. When G is high, the device is dis·
abled and the output is high, regardless of the A and Pin·
puts. The 'ALS680 features a transparent latch and a latch
enable input (C). When C is high, the device is in the
transparent mode. When C is low, the previous logical
state of Y is latched.

• 'ALS679 is a 12·bit to 4·bit comparator with enable
• 'ALS680 is a 12·bit to 4·bit comparator with latch
• Switching specifications at 50 pF
• Advanced oxide·isolated, ion·implanted Schottky TTL
process
• Switching specifications guaranteed over full
temperature and Vcc range

Absolute Maximum Rating!) (Note 1)
Supply Voltage

7V

Input Voltage
Storage Temperature Range

7V
-65·Cto+150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety dtthe device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagrams
Dual·ln·Line Packages

A1

20

Vee

A1

A2

19

Ii

A2

A3

18

A4

17

AS

Vee

A3

Y

P3

A4

P3

16

P2

A5

P2

A6

15

PI

A6

PI

A7

14

PO

A7

14

PO,

A8

13

A12

AS

13

A12

A9

12

All

A9

12

All

11

AID

GND

11

AID

GND

10

10
TOP VIEW

TOP VIEW
TLlF/6237·1

DM54ALS679 (J)

TLJF/6237·2

DM54ALS680 (J)

DM74ALS679 (J, N)

DM74ALS680 (J, N)

This document contains information on a product under development. NSC reserves the right to change or discontinue this product without notice.

2·233

/

Recommended Operating Conditions
Symbol

DM54ALS679, 680

Parameter

Vee

Supply Voltage

VIH

High Level Input Joltage

VIL

Low Level Input Voltage

IOH

High Level Output Current

IOL

Low Level Output Current

TA

Operating Free Air, Temperature
Range

DM74ALS679,680

Units

,Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

-V

0.8

V

2

2

V

0.8
-1

-2.6

mA

24

mA

70

·C

12
-55

125

0

Electrical Characteristics over recommended operating free air tempera~ure range.
All typical values are measured at Vee = 5V, TA =25·C.
Symbol

Parameter

Conditions

Min

VIK

Input Clamp Voltage

VCC

=

4.5V, liN

=

VOH

High Level Output
Voltage

VCC

=

4.5V, IOH

=

Max

IOH = -400p.A, VCC=4.5 to 5.5V
VOL

Low Level Output
Voltage

VCC

=

Typ

-18mA

4.5V

2.4

Max

Unit

-1.5

V

3.2

V
V

VCC-2

54ALS
IOL = 12mA

0.25

0.4

V

74ALS
IOL = 24mA

0.35

0.5

V

II

Input Current at
Max Input Voltage

VCC

=

5.5V, VIN

=

7V

0.1

rnA

IIH

High Level Input Current

VCC

=

5.5V, VIN

=

2.7V

20

p.A

IlL

Low Level Input Current

VCC

=

5.5V, VIN

=

O.4V

-0.1

rnA

10

Output Drive Current

VCC

=

5.5V, VOUT

-112

rnA

ICC

Supply Current

VCC

= S.5V

28

rnA

=

,

2-234

2.25V

-30

ALS679

-12.6

ALS680

13.4

c
3:

Function Table
'ALS679

Inputs Common to 'ALS679 and' ALS680

G

'ALS680
C

P3

P2

P1

PO

A1

A2

A3

A4

AS

A6

A7

A8

A9

L
L
L
L

H
H
H
H

L
L
L
L

L
L
L
L

L
L
H
H

L
H
l.,
H

H
L
L
L

H
H
L
L

H
H
H
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
L
.L
L

L
L
L
L

H
H
H
H

L
L
L
L

H
H
H
H

L
L
H
H

L
H
L
H

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

H
L
L
L

H
H
L
L

H
H
H
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
L
L
L

L
L
L
L

H
H
H
H

H
H
H
H

L
L
L
L

L
L
H
H

L
H
L
H

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

H
L
L
L

H
H
L
L

H
H
H
L

H
H
H
H

L
L
L
L

L
L
L

H
H
H

H
H
H

H
H
H

L
L
H

L
H
L

L
L
L

L ·L
L
L
L· L

L
L
L

L
L
L

L
L
L

L
L
L

L
L
L

H
L
L

H
H
L

H
H
H

L
L
L

L*
L·
L*

L

H

H

H

H

H

L

L

L

L

L

L

L

L

L

L

L

L

·L

H

L

Output
A10 A11 A12

All Other Combinations

H
L

Y

H

'ALS679: Any Combination

H

'ALS680: Any Combination

Latched

'ALS680 .

'ALS679
(19)

EN

PO

(ADDRESS CDMP)
(P ASSUMEO;< 12, 13, 14)

p" 1

J

=1

P2
(17)
(1)
Al

C20

&1>

(2)
A2

p",

(4)

A4

Z4

p"

A5
(6)
A6

Z2

p", 5

Z3

p" 7

A5

Z6

7

A6

Z7
(8)
Z8

A8

A2
A3

Z5
(7)

A7

p" 4

A4

(5)

3

ZI

Al

Z3_

&

p", 3

P3

Z2
(3)

A3

P2

p" 4

=1

p",

PI

p",

p" 1

J

PO

ZI

(ADDRESS COMP)
(PASSUMEO;<12, 13, 14)

(19)

p",

PI

P3

,

en

en

CD
"""

C

3:

:i::!

l>

r
en
en

JD
"""
C

i:
en
~
l>
r

en

en

-s:
CO

0

C

:i::!

0.
l>
r

en

en
co

Logic Symbols

ii

en
~
l>
r

Z4
(5)

Z5

p", 6
p", 7

(6)
Z6
(7)

p" 8

A7

p",

Z7

(8)

p", 9

Z8

AB

(9)

p" 9

(9)
A9

A9

Z9

AID

Z10

10

AID

10

All

Z11

p" 11

All

p", 11

A12

Z12

p", 12

p" 10

p", 10

(13)

11

A12

Z12

11

p", 12
12

12
TLlF16237·3

(:or

TLlF/6237·4

-The three shaded rows of the function table show combinations that would normally not be used in address comparator applications. The logic symbols
above are not valid for these combinations In which P 12, 13, and 14.lt symbols valid for all combinations are required, starting with the fourth Exclusive·OR
from the bottom, change P",9 to P =9 ... 11/13 ... 15, p", 10 to P = 10/11114115, and P",11 to P = 11/15.
Pm numbers shown are for J and N packages.

=

2·235

SWitching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V, TA = 25°C.
Symbol

Parameter

Conditions

To

From

tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

tpLH

Propagation Delay Time, G
Low to High Level Output (ALS679)

tpHL

Propagation Delay Time;
High to Low Level Output

tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

Any P

Y

DM54ALS679, 680

Vee =4.5V to 5.5V,
C L =50 pF,
R L =50011

y

Max

Min

Typ

Max

4

18

28

4

18

25

ns

8

18

40

8

18

35

ns

5

14

26

5

14

22

ns

5

14

35

5

14

30

ns

3

10

15

3

10

13

ns

5

10

30

·5

10

25

ns

y

C
(ALS680)

Units

Typ

y

Any A

DM74ALS679,680

Min

14

14

ns

14

14

ns

Nola I: See Section 1 for test waveforms and oulpulload.

Typical Application Information
The 'ALS679 and 'ALS680 can be wired to recognize any
one of 212 addresses. The number of "lows" in the address
determines the input pattern for the P inputs. Then those
system address lines that are low In the address to be
recognized are connected to the lowest numbered A in·
puts of the address comparator and the system address
lines that are high are connected to the highest numbered
A inputs.

Since the address contains 410ws and 8 highs, the following connections are made:
P3 to OV, P2 to Vee, P1 to OV, and PO to OV.
System address lines A9, A8, A5, and A4 to comparator inputs A 1 through 1>,4 in any convenient order.
The remaining eight system address lines to comparator
inputs A5 through A 12 in any convenient order.

For example, assume the comparator Is to enable a device
when the 12-bit system address is:
All Al0 A9
H
H
L

A8
L

A7
H

A6
H

A4

A5
L

A3 'A2
H
H

L

Al
H

The output provides an active-low enabling signal.
The following circuit is a register bank decoder that examines the 14 most significant bits (AO through A13) of a
20-bit address to select banks corresponding to the hex
addresses.l0000, 10040, 10080, and 100CO..

AO
H

Register Bank Decoder
0

'ALS679
ADDRESS
CDMP

ilr---.. EN

MEMER_

PO
PI

Vee

P2

AO-A2
A4-All SYSTEM
ADDRESS
LINES
AD (MSB)
TO A19

11
,

A3_

~

1,,1

4
LLLL
LLLL
LLLL
LLLL

. 12
8
LLLL
LLLL
LHLL
LLLL
LLLL
HLLL
LLLL
HHLL

16
LLLL
LLLL
LLLL
LLLL

~

AI-All

----I::::. 1l" XIY 0

A12

1

A13_
A12_
A14-A19-' I

= LLLH
= LLLH
= LLLH
= LLLH

10000,6
1004il16
10080,6
100CO'6

A
B

,6

2
3

1000016

}.'~'

1004016
1008016

REGISTERS

100C016
~

SO-S5
TLfF/6237·7,

,
2-237

~National

~ Semiconductor

DM54ALS689/DM74ALS6898-Bit Comparator
General Description

Absolute Maximum Ratings

This comparator performs an "equal to" comparison of two
eight-bit words with provision for expansion or external enabling. The matching of the two 8-bit input pius a logic LOW
on the EN input produces the output A = B. The ALS 689
has an open collector output for wire AND cascading.

Supply Voltage
Input Voltage
Offstate Output Voltage
Operating Free Air Temperature Range
DMS4ALS689
DM74ALS689
Storage Temperature Range

Features
•
•

Switching Specifications at SO pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.

•

Advanced Oxide-Isolated, lon-Implanted Schottky TIL
Proce,ss.

•

Functionally and Pin for Pin Compatible with LS Family
TIL Counterpart.

•

Improved Output Transient Handling Capability.

(Note 1)

7V
7V
7V
:....SS·C to 12S·C
O·C to 70·C
-6S·C to 1S0·C

Nol. 1: The "Absolute Maximum Rallngs" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operaled at these limits. The parametric values defined In the
"Electrical Characteristics" table are nol guaranleed at the absolute
maximum ratings. Tha "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Connection Diagram
Dual·ln·Llne Package
vee

I

A-I

87

A?

8a

Aa

85

AS

84

A4

I

I

I

I

I

I

I

I

I

19

18

17

la

15

14

13

12

11

to

I

I

I

I

I

I

I

I

80

AI

81

AZ

8Z

A3

83

11111

Inputs
Data

A=B

L
L
H

A=B
k;cB

L
H
H

X

H - High Level. L - Low Level, X - Don't Care

TUF16238-1

54ALS689 (J)

Output

EN

74ALS689 (J,N) ,

2·238

Recommended Operating Conditions
DM54ALS6B9
Parameter
Supply Voltage, VCC
High Level Input Voltage, VIH

DM74ALS6B9

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

Unit
V
V

2

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output V;oltage, VOH

5.5

5.5

V

Low Level Output ClJrrent, IOL

12

24

mA

Electrical Characteristjcs over recommended operating free air temperature range.
. All typical values are measured at Vcc =5V, TA =25'C.

Min

Symbol

Parameter

VIK

Input Clamp Voltage

Conditions
VCC

IOH

High Level Output
Current

VCC=5.5V, VOH=5.5V

VOL

Low Level Output
Voltage

VCC

=

=

4.5V, II

=

Typ

-18mA

4.5V

Max

Unit

-1.5

V

0.1

mA

.

54/74ALS
IOL = 12mA

0.25

0.4

V

74ALS
IOL = 24mA

0.35

0.5

V

II

Max High Input Current

VCC

=

5.5V, VIH

=

7V

0.1

mA

IIH

High Leyel Input Current

VCC

=

5.5V, VIH

=

2.7V

20

f.LA

IlL

Low Lel.lel Input Current

VCC

=

5.5V, VIL

=

O.4V

-0.1

mA

ICC

Supply Current

VCC

=

5.5V

19

mA

12

2-239

•

i

...I

o--J .

A2~
7 -

B2

A7~

B7..!!.....-[>o-l .
~1

__~~~______________~

* Output is open collector
TLIF/6238-2

2·240

Unit

ns

Note 1: llee Section 1 for test waveforms and output load.

~

Typ

May.

Max

Min

~National

D Semiconductor
DM54ALS804/DM74ALS804 Hex 2-I'nput NAND Drivers
General Description

Absolute Maximum Ratings

These devices contain six independent 2-input drivers,
each of which performs the logic NAND function, The-1
option which has an increased IOL maximum to 48 mA is
available in the commercial (DM74) part only,

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS
DM74ALS
Storage Temperature Range

Features

(Note 1)
7V
7V

e

- 55 c C to 125 c
ocC to 70 c e
-65 c e to 150 c e

Note 1: The "Absolute Maximum Ratings" are those values beyond

•
•
•
•
•

Switching Specifications at 50 pF,
Switching Specifications Guaranteed Over Full
Temperature and VCC Range. .
Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.

which the safety of the device can not be guaranteed. The device should

not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Functionally and Pin for Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.
Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.

Connection Diagram
Dual-In-Line Package

IA

IB

IV

1A

5B

5A

5V

48

4A

18

11

3A

38

3V

4V

TLlFI6239·'

54ALS804 (J)

74ALS804 (J,N)

Function Table
Y=AB
Inputs

Output

A

B

Y

L
L

L

H

H
H

L

H
H
H

H

L

H = High Logic Level
L = Low Logic Level

2-241

~

.Recommended Operating Conditions

«

Parameter

c

Supply Voltage. VCC

:E

§
==
:E
c

. II)

DM74ALSB04

DM54ALSB04

~

High Level Input Voltage. VIH
Low Level Input Voltage. VIL

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V
V

2

2

Unit

0.8

0.8

V

-12

-15

mA

~

High Level Output Current. 10H

24

I

mA

12

Low Level Output Current. 10L

48·
• Applies for the DM74ALS804·1 option only.

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V. TA = 25°C.
Symbol

Parameter

Con~itions

VIK

Input Clamp Voltage

VCC = 4.5V. 11= -18mA

VOH

High Level Output
Voltage

10H

Min

= - 0.4mA, VCC =4.5 to 5.5V

VOL

Low Level Output
Voltage

=Max, VCC =4.5V

.

VCC = 4.5V

Max

Unit

-1.5

V
V

VCC-2

10H= -3mA. VCC=4.5V
10H

Typ

2.4

V

2

V

54/74ALS
10L = 12mA

0.25

0.4

V

74ALS (Note 2)
10L = 24mA

0.35

0.5

V

II

Max High Input Current

VCC = 5.5V. VIH = 7V

0.1

mA

IIH

High Level Input Current

VCC = 5.5V. VIH =.2.7V

20

I'A

IlL

Low Level Input Current

VCC = 5.5V, VIL = 0.4V

-0.1

mA

10

Output Drive Current

VCC = 5.5V

Vo = 2.25V

-112

mA

ICC

Supply Current

VCC = 5.5V

Outputs High

0.9

2.5

mA

7

12

mA

-30

,

Outputs Low

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V, TA = 25°C.
DM74ALS804

DM54ALS804
Parameter

Conditions

TpLH. Rropagation
delay time. Low to
high level output

VCC = 4.5 to 5.5V
RL = 500 n.
CL = 50 pF.

TpHL. Propagation
delay time. High to
low level output

Min

Typ

Typ

Max

Unit

Max

Min

2

8

2

6

ns

2

9

2

7

ns

Notel: See Section 1 for test waveforms and output load.
Note 2: IOL = 48 mA for the ·1 option.

2·242

-

'?A National

a

Semiconductor

DMS4ALS80S/DM74ALS80S Hex 2-lnput NOR Drivers
General Description

Absolute Maximum Ratings

These devices contain six independent 2·input drivers,
each of which performs the logic NOR function. The ·1
option which has an increased IOL to 48 mA Is available
in the commercial (DM74) option only.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DMS4ALS
DM74ALS
Storage Temperature Range

Features
•

Switching Specifications at SO pF.

•

Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.

•
•

Functionally and Pin for Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.

•

Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.

(Note 1)
7V
7V

":SSOC to 12SoC
O°C to 70°C
-6SoC to lS0°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" lable are not guaranteed al the absolute
maximum ratings. The "Recommended Operating Conditions" table will·
define the conditions for actual device operation.

Connection Diagram
Dual·ln·L1na Package

vee

6B

6A

6Y

5B

5A

5Y

4B

4A

IA

IB

IY

ZA

ZB

ZY

3A

3B

3Y

4Y

TLIF16240·1

54ALS805 (J)

74ALS805 (J,N)

Function Table
Y=A+B
Inputs

Output

A

B

Y

L
L
H
H

L
H
L
H

H
L
L
L

=
=

H High Logic Level
L Low Lagle Level

·2·243

Recommended Operating Conditions
DM54ALSB05
Parameter
Supply Voltage. VCC

,

High Level Input Voltage. VIH

DM74ALSB05

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

Unit
V
V

2
0.8

0.8

V

High Level Output Current. IOH

-12

-15

mA

Low Level Output Current. IOL

12

Low Level Input Voltage. VIL

24
mA
48'
'Applies for the DM74ALS805·1 option only.

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vcc.=5V. TA= 25·C.

Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.5V. II = -18mA

VOH

High Level Output
Voltage

I OH = - O.4mA, VCC = 4.5 to 5.5V

".

Min

IOH = Max, VCC = 4.5V
Low Level Output
Voltage

VCC = 4.5V

Max

Unit

-1.5

V
V

VCC-2

IOH = - 3mA, VCC = 4.5V

VOL

Typ

2.4

V

2

V

54/74ALS
IOL = 12mA

0.25

0.4

V

74ALS (Note 2)
IOL = 24mA

0.35

0.5

V

II

Max High Input·Current

VCC = 5.5V. VIH = 7V

0.1

mA

IIH

High Level Input Current

VCC = 5.5V. VIH = 2.7V

20

IJ.A

IlL

tow Level Input Current

VCC =5.5V. VIL = O.4V

-0.1

mA

Ie

Output Drive Current .

VCC = 5.5V

Vo = 2.25V

-112

mA

ICC

Supply Current

VCC = 5.5V

Outputs High

2

4

mA

Outputs Low

8

14

mA

-30

SWitching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at \/cc= 5V, TA= 25·C.

r
Parameter

Conditions

TPLH. Propagation
delay time. Low to
high LevelOutput

VCC = 4.5 to 5.5V
RL = 500 n.
CL = 50 pF

TpHL. Propagation
delay time. High to
low Level Output

DM54ALSB05

DM74ALSB05
Min

2

8

2

6

ns

2

9

2

7

ns

Nole 1: See Section 1 for test waveforms and output load.
Note 2: IOL =48mA for the·1 option.

2·244

Typ

Typ

Max

Unit

Max

Min

c

~National

:s:tTl

DM54ALS808/DM74ALS808 Hex 2-lnput AND Drivers

en
(X)
o(X)

a

:=r-

Semiconductor

General Description

Absolute Maximum Ratings

These devices contain six independent 2-input drivers,
each of which performs the logic AND function_ The-1
option which has an increased IOL to 48 mA is available
in the commercial (DM74) option only.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS
DM74ALS
Storage Temperature Range

Features
Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
• Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
• Functionally and Pin for Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.
• Improved AC Performance Over Scho~tky and Low
Power Schottky Counterparts.

are

Connection Diagram
Dual-in-Line Package
68

6A

18

IY

6Y

48

4A

38

3Y

I

IA

(Note 1)
7V
7V

-55°C to 125°C
DOC to 7DoC
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" arB those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristlcs" table
not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

•
•

vee

-:s:c

3A

TLlF/6241-1

54ALS808 (J)

74ALS808 (J,N)

Function Table
Y=AB

Inputs

Output

A

B

Y

L
L
H
H

L
H
L

L
L
L

H

H

H = High Logic Level
L.;:: Low Logic Level

2-245

~r-

en
(X)
o(X)

~


General Description

Features

These dual 4-bit registers feature totem-pole TRI-STATE
outputs designed specifically for driving highly-capacitive
or relatively low-impedance loads. The high-impedance
state and increased high-logic-level drive provide these
registers with the capability of being connected directly to
and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, 1/0
ports, bidirectional bus drivers, and working registers.

•
•

Switching Specifications at 50 pF.
.......
Switching Specifications Guaranteed Over Full
Co)
Temperature and Vee Range.
• Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
• TRI-STATE Buffer-Type Outputs Drive Bus Lines Directly.
• Space Saving 300 Mil Wide Package.

The eight latches of the ALS873 are transparent D-type
latches meaning that while t~e enable (G) is high the outputs will follow the data (D) inputs. When the enable is taken
low the output will be latched at the level of the data that
v.vas set up.

Absolute Maximum Ratings

a

r-

~

A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The out Rut control does not affect the internal operation of
the latches. That is, the old data can be retained or new data
can be entered even while the outputs are off.

(Note 1)

7V
7V

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS873
DM74ALS873
Storage Temperature Range

-55°e to 125°e
ooe to 70 0 e
-65°e to 1500 e

Nole 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric, values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Oiagram
Dual-In-Llne Package

v"

"

IC!J[

£MAILE

I'
"

fiiC

101

"

1'1

10'
21

102

103

20

13

I.

21

I'

18

104

54ALS873 (J)

201

'0'

17

202

74ALS873 (J,N)

2-255

ENABLE

"

16

'"

24
15

I'

20.

"

I.

12

'NO
TL/F/6243-1

~

I'

~

r---------------------------------------------------------------------Recommended Operating Conditions

Ie:(

DM54ALS873

DM74ALS873

t!

Parameter

o

Supply Voltage. VCC

I'

High Level Input Voltage. VIH

~
II)

Low Level Input Voltage. VIL

0.8

0.8

V

High Level Output Current. IOH

-1

-2.6

mA

Low Level Output Current. IOL

12

24

mA

:E
C;;

~

:E

o

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5·

4.5

5

5.5

I

Pulse Width. TW,

Data Setup Time. TSU
Data Hold Time. TH

2

I
I

2

Unit

V
V

Enable High

15

15

Clear Low

15

15

10.

10.

ns

7!

7!

ns

The (I) arrow indicates the negative edge of the enable is used for reference,

2·256

ns

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25 D C.

Symbol

Parameter

Conditions

Min

VIK

Input Clamp Voltage

VCC = 4.5V, II = -1BmA

VOH

High level Output
Voltage

VCC = 4.5V
Vll = Vll MAX
10H=Max

VOL

low level Output
Voltage

204

Typ

Max

Unit

-1.5

V
V

3.2

10H = -4001'A
VCC=4.5V to 5.5V

54/74AlS

VCC = 4.5V
VIH = 2V

54/74AlS
10L = 12mA

0.25

004

V

74AlS
10l = 24mA

0.35

0.5

·V

V

VCC -2

II

Max High Input Current

VCC = 5.5V, VIH = 7V

0.1

mA

IIH

High level Input Current

VCC = 5.5V, VIH = 2.7V

20

I'A

III

low level Input Current

VCC = 5.5V, Vll = 0.4V

-0.1

mA

10

Output Drive Current

VCC

- 112

mA

10ZH

Off-State Output
Curr~nt, High level
Voltage Applied

VCC=5.5V, VIH =2V
Vo = 2.7V

20

I'A

10Zl

Off-State Output
Current, low level
Voltage Applied

VCC = 5.5V, VIH = 2V
Vo = OAV

-20

I'A

ICC

SUPl?ly Current

VCC = 5.5V
Outputs Open

=

5.5V

Vo

=

2.25V

-30

Outputs High

11

21

mA'

Outputs low

16

29

mA

Outputs Disabled

20

31

mA

2·257

~r----------------------------------------------------------------------------

.....

~c(
~

:E

c

~

~
:E
c

Switching Characteristics over recommended operat~ng free air temperature range (Note 1).
All typical values are measured at Vcc = 5V, TA = 25°C.
DM54ALS873
Parameter

To

From

TpLH

Conditions

Any 0

Data

TpHL
TpLH

Enable

Any 0

TpHL
TpZH
TpZL

Output

TPHZ

Control'

VCC = 4.5V to 5.5V
RL = 500 {j
CL = 50 pF

Any 0

TpLZ
Clear

TpHL

Typ

Min

Any 0

DM74ALS873

Typ

Max

Unit

Max

Min

2

15

2

14

ns

2

15

2

14

ns

8

25

8

21

ns

8

22

8

21

ns

4

21

4

18

ns

4

21

4

18

ns

2

12

2

10

ns

2

15

2

12

ns

6

23

6

20

ns

Note 1: See Section 1 for test waveforms and output load.

Function Table

Logic Diagram
1

"m'~"~C>o-...,

1~%Va~_2~c>--+

__--...,

1 CLE.. _I~I>-...,

101-'---+-+--1

4

5
20 103

ID4

IS
'9 f04

201

1

18 201

202

8
11

203

202

9
18 203

",..:1::..'--+-+--1
15

~g~~~~I~I~>-_+-

2. ENABLE-"'''=--iC>o-.J

EN

~

X
X
H
L
X

X
X
H
H
L

H
L
L
L
L

a

21102

lD3

D

X
L
H
H
H

L = Low State, H = High State. X
Z = High Impedance State
00 = Previous Condition of

22101

102

CiJi

204

___~
TlIF16243-2

2·258

= Don't Care

Q

Z
L
H
L
00

r-----------------------------------------------------------------~c

s:

.
Semiconductor

~National

a

U1

:;ren

co
~

-

DM54ALS874/DM74ALS874 Dual4-Bit D-Type
Edge-Triggered Flip-Flops with TRI-STATE® Outputs
General Description

Features

These dual 4-bit registers feature totem'pole TRI-STATE
outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide
these registers with the capability of being connected
directly to and driving the bus lines in a bus-organized
system without need for Interface or pull-up components.
They are particularly attractive for Implementing buffer
registers,lIO ports, bidirectional bus drivers, and working
registers.

•
•

•
•

The outPUt control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can.be entered even while the outputs are off.

101

Space Saving 300 Mil Wide Package.
Asynchronous Clear

Absolute Ms:o-..,

~:~l=:~ -'~I>--+-----.

,o'-'---+-+--I
n
102

21102

'01-"'----+-+--1
20 103
'd• ...;''----+-+--1
It

I-~I>--'O.

2Dl...!...-----I

m

201

-''----+-+--1
17 202

203 -''----+-+--1
"203
204 10

15 204

---.1

2 CLOCK...!':.,'

TLlF16244·2

2·262

r-----------------------------------------~--~---------------------.c

3:

II?A National
D Semiconductor

~
~.......

en

DM54ALS876JDM74ALS876
Dual 4-Bit D-Type Edge-Triggered Flip-Flops
with TRI-STATE® Outputs
General Description

C

3:
~
»r-

~
.......

Features

These inverting dual 4·bit registers feature totem'pole
TRI·STATE outputs designed specifically for driving
highly·capacitive or relatively low·impedance loads. The
high·impedance state and increased high·logic·level drive
provide these registers with the capability of being
connected directly to and driving the bus lines in a bus·or·
ganized system without need for interface or pull·up com·
ponents. They are particularly attractive for Implementing
buffer registers, 1/0 ports, bidirectional bus drivers, and
working registers.

•
•
•
•
•
•

The eight flip-flops of the ALS876 are edge-triggered inverting D-type flip-flops. On the positive transition of the clock,
the Q outputs will be set to the complement of the logic
states that were set up at the D inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output cbntrol does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and Vee Range.
Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
TRI·STATE Buffer·Type Outputs Drive Bus Lines Directly.
Space Saving 300 Mil Wide Package.
Asynchronous Preset.

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS876
DM74ALS876
Storage Temperature Range

(Note 1)
7V
7V

-55°C to 125°C
DoC to 70°C
-65°C to 150°C

Nole 1: The "Absolute Maximum Ratings" are those values beyond
which the safely of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Condltlons"lable will
define the conditions for actual device operation.

Connection Diagram
Dual-In-Line Package
'ee
2'

leLK

23

lot

iii
22

101

",

iOz

"

102

19

103

10.

2,1
18

202
11

2,3
16

20'
15

201

202

203

10
204

12

GNO

TLI F16245· 1

54ALS876 (J)

74ALS876 (J,N)

2·263

en

fe

~

. Recommended Operating Conditions

..J

ct
;:!
:i!:

DM54ALS876
Parameter

c

Supply Voltage, Vec

"""
en

co

High Level Input Voltage, VIH

..J

Low Level Input Voltage, VIL

co

~

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

2

Unit

V
V

0.8

0.8

V

5.5

5.5

V

High Level Output Current, IOH

-1

-2.6

mA

Low Level Output Current, IOL

12

24

mA

High Level Output Voltage, VOH

:i!:

c

DM74ALS876

Min

,

,
25

0

Clock frequency, fCLOCK

0

30

MHz

High

20

16.5

Low

20

16.5

Low

10

10

ns

151

151

ns

Data Hold Time, TH

41

01

ns

Preset Inactive, TSU

101

101

ns

Width of Clock Pulse, TW

Width of Preset Pulse, TW
Data Setup Time, TSU

The (1) arrow indicates the positive edge of the Clock is used for reference.

~.

2-264

ns
ns

c

3:

Electrical Characteristics over recommended operating free air temperature range.

c.n

;,....

All typical values are measured at Vc c=5V, TA=25"C.

Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC

VOH

High Level Output
Voltage

Min

. VCC = 4.5V
VIL = VILMAX

VCC = 4.5V
VIH = 2V

Low Level Output
Voltage

Max

Unit

-1.5

V

54/74ALS
10H = -1mA

2.4

3.2

V

74ALS
10H = -2.6mA

2.4

3.3

V

54/74ALS
10H = -400",A
VCC = 4.5V to 5.5V
VOL

Typ

= 4.5V II = -18mA

V

VCC -2 .

54/74ALS
10L = 12mA

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

II

Max High InpufCurrent

VCC

= 5.5V VIH = 7V

0.1

mA

IIH

High Level Input Current

VCC

= 5.5V VIH = 2.7V

20

",A

IlL

Low Level Input Current

VCC

= 5.5V VIL = 0.4V

Data, CLK

-0.2

mA

All Others

-0.2

10

Output Drive Current

VCC

10ZH

Off-State Output
Current, High Level
Voltage Applied

VCC = S.5V VIH
Vo = 2.7V

10ZL

Off-State Output
Current, Low Level
Voltage Applied

. VCC = 5.5V VIH
Vo = O.4V

ICC

Supply Current

-

= 5.5V

VCC = 5.5V
Outputs Open

-112

mA

= 2V

20

",A

= 2V

-20

",A

-30

54/74ALS
Vo = 2.25V

Outputs High

14

21

mA

Outputs Low

19

30

mA

Outputs Disabled

20

32

mA

:

"

/

2-265

~
.....

en
C

3:
~

l>
,....

en

CD
.....
en

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vcc = 5V, TA = 25"C.
DM74ALS876

DM54ALS876
Parameter

From

To

Conditions

Min

Typ

Max

Min

TpLH

Clock

AnyO

TpHL
Output
Control

TpZH
TpZL

AnyO

VCC = 4.5V to 5.5V
RL = 500 n
CL = 50 pF

TPHZ
TpLZ
Preset

TpHL

Any 0

Max

30

25

FMAX

Typ

Unit
MHz

4

15

4

14

ns

4

15

4

14

ns

4

21

4

18

ns

4

21

4

18

ns

2

12

2

10

, ns

2

15

2

12

ns

5

20

5

17

ns

Note 1: See Section 1 for test waveforms and output load.

Logic Diagram

Function Table

1 CLOCK ...:':...3-;)00----,

IPiiE ..;''-<>1>-,

,D1-'---+-+--I

102

4

ID3

II

lD •

0

CLK

OC

X
L
H
H
H

X
X
H
L
X

X
X
i
i
L

H
L
L
L
L

L ~ Low State. H ~ High State. X
I = Positive Edge -;-..:::~sition
Z ~ High Impedance State
00 ~ Prev,ous Condition of

a

..;''----+-+--1

,D1-'------i

'02 _''--_-+-+--1

ZD3

PRE

9

16

203

--+-+--1

204...:',,-0

2 CLOCK ...:':....-1:)00---'

TLlF/6245·2

.2·266

~

Don't Care

Q

Z
L
L J
H
00

.-----------------------------------------------------~c

~

~National

a

U1

;

Semiconductor

lii
co

co
o

DM54ALS880/DM74ALS880
Dual 4-Bit D-Type Transparent Latches
with TRI-STATE® Outputs
General Description

Features

These dual 4-blt I nvertlng registers feature totem-pole
TRI-STATE outputs designed specifically for driving
highly-capacitive or relatively low-Impedance loads. The
high-Impedance state and Increased high-logic-level drive
provide these registers with the capability of being
connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing
buffer registers, 1/0 ports, bidirectional bus drivers, and
working registers.

•
•
•

C

~

~

l>

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and Vee Range.
Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.

• TRI-STATE Buffer-Type Outputs Drive Bus Lines Directly.
•

The eight inverting latches of the ALSBBO are transparent
D-type latches meaning that while the enable (G) Is high the
outputs will follow the complement of the data (D) inputs.
When the enable Is taken low the output will be latched at
the complement of the level of the .data that was set up.

a

A buffered output control input can be used to place the
eight outputs In either a normal logic state (high or low logic
levels) or a high-Impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines signlficantly.
The output control does not affect the Internal operation of
the latches. That is, the old data can be retained or new data
can be entered even while the outputs are off.

Space Saving 300 Mil Wide Package.

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALSBBO
DM74ALS880
Storage Temperature Range

(Note 1)
7V
7V

-55°C to 125°C
ooe to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table arj! not guaranteed at the absolute
maximum rallngs. The "Recommended Operallng Condllions"table will
define the condilions for actual device operation.

Connection Diagram
Dual-In-Llne Package

TLI F 16248-1

54ALS880 (J)

74ALS880 (J,N)

2-267

lii
~

Recommended Operating Conditions
DM74ALS880

DM54ALS880

Parameter

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Supply Voltage, VCC

2

High Level Input Voltage, VIH

High level Output Current, IOH

-1

I

12

low level Output Current, IOl
Pulse Width, TW

V
V

2
0.8

low level Input Voltage, Vil

Unit

0.8

V

-2.6

mA

24

mA
ns

Enable High

15

15

Preset low

15

15 .

Data Setup Time, TSU

101

101

ns

Data Hold Time, TH

10!

10!

ns

The (I) arrow indicates the negative edge of the enable is used for reference.

2·268

--------------------------------------------------------------~c

:s:

Electrical Characteristics over recommended operating free air temperature range.

(J1

All typical values are measured at Vee = 5V, TA = 25·C.

Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC=4.5V, 11= -18mA

VOH

High Level Output
Voltage

VCC = 4.5V
VIL = VIL MAX

Min

Low Level Output
Voltage

VCC = 4.5V
VIH = 2V

Max

Unit

-1.5

V

54/74ALS
10H = -1mA

2.4

3.2

V

74ALS
10H = -2.6mA

2.4

3.3

V

54/74ALS
10H = -400!LA
VCC=4.5V to 5.5V
VOL

Typ

V

VCC -2

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

II

Max High Input Current

VCC=5.5V, VIH=7V

0.1

mA

IIH

High Level Input Current

VCC=5.5V, VIH=2.7V

20

!LA

IlL

Low Level Input Current

VCC = 5.5V, VIL = 0.4V

-0.1

mA

10

Output Drive Current

VCC = 5.5V

-112

mA

10ZH

Off-State Output
Current, High Level
Voltage Applied

VCC=5.5V, VIH=2V·
Vo = 2.7V

20

!LA

10ZL

Off-State Output
Current, Low Level
Voltage Applied

VCC=5.5V, VIH=2V
Vo = O.4V

-20

!LA

ICC

Supply Current

VCC = 5.5V
Outputs Open

-30

Outputs High

14

21

mA

Outputs Low

19

29

mA

Outputs Disabled

20

31

mA

2·269

co
co
o

-:s:
c

~
l>

ren
CO
CO

o

54/74ALS
10L = 12mA

54/74ALS
Vo = 2.25V

:=b;

or-----------------------------------------~---------------------------

~
....

--,

101

3

4

lD'''':'~---+-+--l
20

1'03

1D4 6

"'-'------\
.,,-"'-----+-+--1

203

0

EN

"O"e

Q

X
L
HH
H

X
X
H
L
X

X
X
H
H
L

H
L
L
L
L

Z
L
L
H

= Low State. H = H'gh State. X =
£ - High Impedance State _
00 = Previous Condition of 0
L

102

PRE

9

204 10

15 ~4

~~~~~'~>---+-------~
2 ElfABLE""";:'"-0----'

TLt F16248·2

2-270

Don·t Care

~O

.------------------------------------------------------------------,0

3:

~National

~ Semiconductor

~

DM54ALS1000A/DM74ALS1000A
Quadruple 2-lnput NAN D Buffers

-~

~
....

o
3:

General Description

Absolute Maximum Ratings

These devices contain four" independent 2-input bufferl
drivers each of which performs the logic NAND function.
The 'ALS1000A is a bufferldriver version of the 'ALSOOA.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS1000A
DM74ALS1000A
Storage Temperature Range

Features
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.

•

Advanced Oxide-Isolated, lon-Implanted Schottky TIL
Process.

•

Improved Line Receiving Characteristics.

Connection Diagram

4A

4Y

define the conditions for actual device operation.

Function Table

38

3A

3Y

B

Inputs

18

1Y

2A

28

2Y

B

Y

L
L
H
H

L
H
L
H

H
H
H
L

L = low Logic Level

GND
Tl/F/6249-1

54ALS1000A (J)

74ALS1000A (J, N)

2-271

Output

A

H; High Logic Level
1A

~

7V
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will

Dual·ln·Line Package
48

~

(Note 1)

....~

o
o

~

§....

Recommended Operating Conditions
Parameter

:!!

t!

Supply Voltage, VCC

~....

High Level Input Voltage, VIH



(Note 1)
7V
7V

~
.....

o

I§

-55°C to 125°C
O°C to 70°C· .-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Improved Line Receiving Characteristics.

Connection Diagram

Function Table

Dual-In-Line Package

Vee

V4

B4

V3

B3

Y=A+B

,A3

8

Inputs

B

Y

L
L

L

H

H

L
L
L

H
H

=

7
V1

A1

V2

A2

B2

TLIF/6250-1

54ALS1002A (J)

L

H

H High Logic Level
L;;: Low Logic Level

GND

74ALS1002A (J,N)

2-273

Output

A

•

Recommended Operating Conditions
DM54ALS1002A
Parameter
Supply Voltage, Vec

DM74ALS1002A

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Unit
V

"

2

High Level Inl?ut Voltage, VIH

V

2

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Current, IOH

-1

-2.6

.mA

Low Level Output Current, IOL

12

'24

mA

Max

Unit

-1.5

V

,

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vcc= 5V, TA~25°C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC=4.5V, 11= -18mA

VOH

High Level Output
Voltage

VCC = 4.5V
VIL = VILMAX

IOH = -400"A
Vec=4.5V to 5.5V
VOL

Low Level Output
Voltage

Typ

Min

Vec = 4.5V
VIH = 2V

54/74ALS
IOH = -1mA

2.4

3.2

V

74ALS
IOH = -2.6mA

2.4

3.3

V

54/74ALS

.

V

VCC -2

54/74ALS
10L = 12mA'

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

II

Max High Input Current

Vec=5.5V, VIH=7V

0.1

mA

IIH

High Level Input Current

Vec=5.5V, VIH=2.7V

20

/LA

IlL

Low Level Input Current

Vec=5.5V, VIL=0.4V

-0.1

mA

10

Output Drive Current

Vec = 5.5V

-112

mA

ICCH

Supply Current

Outputs High Vce = 5.5V, VI = OV

1.7

2.8

mA

IceL

Supply Current

Outputs Low VCC = 5.5V, VI = 4.5V

5.6

9

mA

-30

Vo = 2.25V

,

Switching Charac,teristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vce = 5V, TA = 25°C.
DM74ALS1002A

DM54ALS1002A
Parameter

Conditions

TpLH, Propagation
delay time. Low to
high Level Output

Vce = 4,5 to 5.5V
RL = 500O,
CL = 50pF.

TpHL, Propagation
delay time. High to
low Level Output

Min

Typ

,

2

2

Note 1: See Section 1 for test waveforms and output load.

2·274

.

Typ

Max

Unit

Max

Min

10

2

8

ns

11

3

7

ns

~National

~ Semiconductor

DM54ALS1003A/DM74ALS1003A
Quadruple 2-lnput NAN D BufferS
with Open-Collector Outputs
General Description

Features

These devices contain four Independent 2-lnput buffers,
each of which performs the logic NAND function. The
outputs require an external pull-up resistor for proper
logical operation. The 'ALS1003A is a buffer version of
the 'ALS03A.

•
•

Pull·Up Resistor Equations

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
• Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
• Functionally and Pin For Pin Compatible with LS TTL
Counterpart.
• Improved Line Receiving Characteristics.

Absolute Maximum Ratings
VCy (Max) - VOL
RMIN = 10L - N3 (JIU

Where:

N1 (IOH) = total maximum output high current
for all outputs tied to pull-up resistor
N2 (JIH) total maximum Input high current for
all inputs tied to pull-up resistor
N3 (JIU = total maximum input low current for
all inputs tied to pull-up resistor

=

Supply Voltage
Input Voltage
Off State (High Level) Output Voltage
Operating Free Air Temperature Range
DM54ALS1003A
DM74ALS1003A
Storage Temperature Range

Dual·ln-L1ne Package

Y='U
Inputs

7
A1

81

Y1

82

Y2

B

Y

L
L
H
H

L
H
L
H

H
H
H
L

=

74ALS1003A (J,N)

2-275

Output

A

H = High Logic Level
L Low Logic Level

GND

TLiF/6251·1

54ALS1003A (J)

7V
7V
7V
-55·C to 125·C
O·C t070·C
-65·C to 150·C

Note 1: The '"Absolute Maximum Ratings'" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
'"Electrical Characteristics'" table are not guaranteed at the absolute
maximum ratings. The '"Recommended Operating Conditions'" table will
define the conditions for actual device operation.

Function Table

Connection Diagram

(Note 1)

Recommended Operating Conditions
DM74ALS1003A

DM54ALS1003A
Parameter
Supply. Voltage, VCC
High Level Input Voltage, VIH

,

Min

Nom

Max

4.5

5

5.5

2

Min

Nom

Max

5

5.5

·4.5

Unit
V

V

2

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Voltage, VOH

5.5

5.5

V

Low Level Output Current, 10L

12

24

mA

Electrical Characteristics over recor:nr:nended operating free air temperature range.
. All typical values are measured at Vee = 5V, TA = 25°C.
Parameter

Conditions

Max

Unit

VIK

Input Clamp Voltage

VCC;"4.5V, II = -18mA

-1:5

V

10H

High Level Output
Current

VCC,';'·4.5V
VOH = 5.5V .

100

,.A

VOL

Low Level Output
Voltage

.

Min

Typ

Symbol

VCC = 4.5V
VIH = 2V

54/74ALS
10L = 12mA

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

Max High Input Current .

VCC=5.5V, VIH=7V

0.1

mA

IIH

High Level Input Current

VCC = 5.5V,YIH = 2.7V

20

,.A

IlL

Low Level Input Current .

VCC=5.5V, VIL=0.4V

-0.1

mA

-112

mA

"11

"J,

"

=

=

-30

10

Output Drive Current

VCC

ICCH

Supply Current

Outputs High VCC

=

5.5V, VI

=

OV

0.86

1.6

mA

ICCL

Supply Current

Outputs Low VCC

=

5.5V, VI

=

4.5V

4.8

7.8

mA

Vo

5.5V

2.25V

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V, TA = 25°C.
DM54ALS1003A
Parameter
TpLH, Propagation
delay time. Low to
high Level Output

Conditions
VCC = 4.5 to 5.5V
RL = 667n,
. CL = 50 pF.

TpHL, Propagation
delay time. High to
low Level Output

Min

Typ

DM74ALS1003A

Typ

Unit

Max

Min

5

40

5

33

ns

2

18

2

12

ns

Nole 1: See Section 1 for test waveforms and output load.

2·276

Max

~----~--------------------------------------------------------~c

i:

~National

;

~ Semiconductor

~
.-

g

-c

DM54ALS1004/DM74ALS1004 Hex Inverting Drivers
General Description

Absolute Maximum Ratings

These devices contain six independent 2-input drivers,
each of which performs the logic Inverter/complement
function. The' ALS1004 is a driver version of the 'ALS04A.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS
DM74ALS
Storage Temperature Range

Features
•
•
•
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
Advanced OXide-Isolated. Ion-Implanted Schottky TTL
Process.
Functionally and Pin for Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.
Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.

-55°C to 125°C
O°C to 70°C
-65°C to 150°C

define the conditions for actual device operation. .

TliF/6252·1

74ALS1004 (J,N)

Function Table

H

7V
7V

Note 1: The "Absolute Maximum Ratings" are those values beyond

Dual-In-Line Packa,ge

(J)

(Note 1)

Which the safety of the device can not be guaranteed. The device should
not b.a operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will

Connection Diagram

54A~S1004

i:

Input

Output

A

y

L
H

H
L

=High Logic Level

L = Low Logic Level

2-277

;

!!l

g

Recommended Operating Conditions
DM54ALS1004
Parameter
Supply Voltage, VCC
High Level Input Voltage, VIH

DM74ALS1004

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

Unit
V
V

2
0.8

0.8

V

High Level Output Current, 10H

-12

-15

mA

Low Level Output Current, 10L

12

24 ,

mA

Max

Unit

-1.5

V

Low Level Input Voltage, VIL

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vcc =5V, TA=25°C.
Symbol

Parameter

Min

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V, II = -18mA

VOH

High Level Output
Voltage

10H = - 0.4mA, Vee = 4.5 to 5.5V

VOL

.

Low Level Output
Voltage

V

Vee- 2
2

10H = Max, VCC = 4.5V

2.4

10H - - 3m A, Vee - 4.5V
Vee = 4.5V

Typ

54/74ALS
10L = 12mA

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

II,

Max High Input Current

Vce = 5.5V, VIH = 7V

0.1

mA

IIH

High Level Input Current

Vce = 5.5V, VIH = 2.7V

20

!LA

IlL

Low Level Input Current

Vee = 5.5V, VIL = 0.4V

-0.1

mA

Output Drive Current

Vee = 5.5V

Vo = 2.25V

-112

mA

Supply Current

Vee = 5.5V

Outputs High

0.84

3

rnA

Outputs Low

7

12

,10
ICC

)

-30

mA

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V, TA = 25°C.
DM54ALS1004
Parameter

Conditions

TpLH, Propagation
delay time. Low to
high Level Output

Vee = 4.5 to 5.5V
RL = 50011,
eL = 50 pF.

TPHL, Propagation
delay time. High to
low Level Output
Note 1: See Section 1 for test waveforms and output load,

Typ

DM74ALS1004
Typ

Max

Unit

Max

Min

1

9

1

7

ns

1

8

1

,6

ns

Min

r------------------------------------------------------------------,c

3:

~National

;

~ Semiconductor

bi...a.
o
o

DM54ALS1005/DM74ALS1005 Hex Inverting Drivers
with Open CollectC)r Outputs
General Description

Features

These devices contain six Independent drivers, each of
which performs the logic INVERT/Complement function.
The outputs req'uire external pull-up resistors for proper
logic operation. The 'ALS1005 is a driver version of the
'ALS05A.

•
•

VcC
~

~ Semiconductor

.....

DM54ALS1010A/DM74ALS1010A
Triple 3-lnput NAND Buffers

C

.....
~

-s:
C

General Description

Absolute Maximum Ratings (Note 1)

These devices contain three independent 3·input buffers,
each of which performs the logic NAND function. The
'ALS1010A is a buffer option of the 'ALS10A.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS1010A
DM74ALS1010A
Storage Temperature Range

Features
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.

•

Advanced Oxide·lsolated, lon-Implanted Schottky TTL
Process.

•

Improved Line Receiving Characteristics.

Connection Diagram

7V
7V
-55·C to 125·C
O·C to 70·C
-65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Dual·ln·Llne Package

V1

Vcc . C1

C3

83

A3

V3

Inputs

2
A1

81

3
A2

B

C

y

L

X

H

X
X
H

X
X

X
H

L

H

H

L

L

L = low logic level

82

V2

=

GND

H high logic level

TUF16255·1

54ALS1010A (J)

Output

A

X = either low or high logic level

74ALS1010A (J,N)

2·283

H

~
»

r-

CJ)
.....
C
.....

~

~

~
,...

Recommended Operating Conditions
DM54ALS1010A

~

Parameter

:::E

t!

Supply Voltage, VCC

c

~
,...

High Level Input Voltage, VIH
Low Level Input Voltage, VIL

0.8

0.8

V

~

High Level Output Current, 10H

-1

-2.6

mA

Low Level Output Current, 10L

12

24

mA

Max

Unit

-1.5

V'

c::c

o
,...

~
an
~

DM74ALS1010A

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

Unit
V
V

2

Electrical Characteristics over recommended operating free air temperature range.
Ail typical values are measured at Vcc= 5V, TA=25°C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC=4.5V,II= -18mA

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

Min

VCC = 4.5V
' VIL = VIL MAX

Typ

'54/74ALS
10H = -1mA

2.4

3.2

V

74ALS
10H = -2.6mA

2.4

3.3

V

10H = -400"A
VCC = 4.5V to 5.5V

54/74ALS

VCC = 4.5V
VIH = 2V

54/74ALS
10L = 12mA

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

V

VCC -2

,

II

Max High Input Current

VCC = 5.5V, VIH = 7V

0.1

mA

IIH

High Level Input Current

VCC=5.5V, VIH=2.7V

20

ItA

IlL

Low Level Input Current

VCC=5.5V, VIL=0.4V

-0.1

mA

10

Output Drive Current

VCC

-112

mA

ICCH

Supply Current

Outputs High VCC

= 5.5V, VI =

0.65

' 1.2

mA

ICCL

Supply, Current

Outputs Low VCC

=

3.6

5.8

mA

=

Vo

5.5V

=

-30

2.25V

5.5V, VI

OV

= 4.5V

Switching Characteristics over recommended operating free air temperature range (Note 1).
Ail typical values are measured at Vcc =5V, TA = 25°C.
DM54ALS1010A
Parameter

Conditions .
\

TPLH, Propagation
delay time. Low to
high Level Output

VCC = 4.5 to 5.5V
RL = soon,
CL = 50pf.

TpHL, Propagation
delay time. High to
low Level Output

Min

DMi4ALS1010A
Min

2

10

2

8

ns

2,

11

3

7

ns

2·284

Typ

Max

Unit

Max

Note 1: See Secllon 1 for test waveforms and oulput load.

Typ

c

s::

·~National

~

~ Semiconductor

r-

en
.....

o.....

DM54ALS1011A1DM74ALS1011A
.Triple 3-lnput AN D Buffers

.....
c

General Description

Absolute Maximum Ratings (Note 1)

These devices contain three independent buffers, each of
which performs the logic AND function. The 'ALS1011A is
a buffer version of the 'ALS11A.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54ALS1011A
OM74ALS1011A
Storage Temperature Range

\

Features
•
•
•
•

Connection Diagram

Function Table

Dual·ln·Line Package
83

C3

Y1

C1

A3

Y=ABC

Output

Inputs

2
A1

81

3
A2

4
82

Y2

54ALS1011A (J)

A

B

C

Y

L

X

L

X
X

L

X

X
X
L

H

H

H

H

L
L

L = low logic level

GND

TlIF/6256.1

~

7V
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Note"1: The "Absol~te Maximum Ratings" BiB those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table afB not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
Improved Line Receiving Characteristics.

VCC

-s::
:r>

H = high logic level
I

X = either low or high logic level

74ALS1011A (J,N)

2·285

:r>
~
.....
g
.....
:r>

c:(

....en~

...
,....

==
:::E
Q
C(

....

....o

~

~
:::E

Q

Recommended Operating Conditions
DM54ALS1.Q11.A
Parameter
Supply Voltage, VCC

DM74ALS1011A

Min

Nom

Max

Min

4.5

5

5.5

4.5

Max
5.5

5

2

2

High Level Input Voltage, VIH

. Nom

Unit
V
V

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Current, IOH

-1

-2.6

mA

Low Level Output Current, IOL

12

24

mA

Max

Unit

-1.5

V

Electrical Characteristics ,over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25°C.
Symbol

Conditions

Input Clamp Voltage

VCC= 4.5V, II = -18mA

VOH

High Level Output .
Voltage

VCC = 4.5V
VIH = 2V

VOL

Low Level Output
Voltage

' Typ

Min

Parameter

VIK

54i74ALS
IOH = -1mA

2.4

3.2

V

7iALS
IOH = -2.6mA

2.4

3.3

V

IOH = -400!

These devices contain six independent drivers, each of
which performs the logic identity function. The outputs reo
quire an external pull-up resistor for proper logical
operation.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DMS4ALS
DM74ALS
Storage Temperature Range'

en

~

Features
Switching Specifications at SO pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
!II Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
• Functionally and Pin for Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.
Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.

Connection Diagram
Dual-In-Line Package

GHD,

Y2

TLlF/6260·j

54ALS1035 (J)

7V
7V
-SSOC to 12SoC
O°C to 70°C
-6SoC to .1S0°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

•
•

•

I"'"

74ALS1035 (J,N)

Function Table
Y=A
Input

Output

A

Y

L

L

H

H

L=low logic level

H::; high logic level

2-293

en
....
~

s

...

~

«

Recommended Operating Conditions
DM54ALS1035

~

Parameter

c

Supply Voltage, VCC

...o

High Level Input Voltage, VIH

:::E

in
C")

~

~

:::E
c

DM74ALS1035

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

Unit
V
V

2

,
Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Voltage, VOH

5.5

5.S

V

Low Level Output Current, IOL

12

24

mA

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vce = SV, TA = 25°C.
Symbol

Parameter

Conditions

Max

Unit

VIK

Input Clamp Voltage

VCC

= 4.5V, II = -18mA

-1.S

V

IOH

High Level Output
Current

VCC

= 4.5V,VOH = S.SV

100

p.A

VOL

Low Level Output
Voltage

VCC

= 4.5V

Min

Typ

54/74ALS
IOL = 12mA

0.25

0.4

V

74ALS
IOL = 24mA

0.35

0.5

V

II

Max High Input Current

VCC

= 5.5V, VIH = 7V

0.1

mA

IIH

High Level Input Current

VCC

= 5.5V, VIH = 2.7V

20

p.A

IlL

Low Level Input Current

VCC

= 5.5V, VIL = O.4V

-0.1

mA

ICC

Supply Current

VCC

= 5.5V

r

Outputs High

3

6

mA

Outputs Low

8

14

mA

SWitching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V, TA = 25°C.
DM54ALS1035
Parameter

Conditions

TPLH, Propagation
delay time. Low to
high Level Output

VCC, = 4.5 to 5.5V
RL = 667O,
CL = 50 pF.

TpHL, Propagation
delay time. High to
low Level Output

Min

Typ

5

2

Nots 1: See Section 1 tor test waveforms and output load.

2·294

,

DM74ALS1035
Unit

Max

Min'

35

5

30

ns

14

2

12

ns

Typ

Max

~-----------------------------------------------------------------'C

~National

==

~
~ Semiconductor
r"'"
en
....
DM54ALS1240/DM74ALS1240, DM54ALS1241/DM74ALS1241
~
Octal TRI-STATE® Bus Drivers
c
General Description
==
~
These octal TRI·STATE bus drivers are designed to provide
the designer with flexibility in implementing a bus inter·
face with memory, microprocessor, or communication
systems, and are low power dissipation versions of the
'ALS240 and 'ALS241. The output TRI·STATE gating con·
trolls organized into two separate groups of four buffers.
The 'ALS1240 control inputs symmetrically enable the
respective outputs when set logic low, while the' ALS1241
has complementary enable gating. The TRI·STATE clr·
euitry contains a feature that maintains the buffer outputs
in TRI·STATE (high impedance state) during power supply
ramp·up or ramp·down. This eliminates bus glitching prob·
lems that arise during power·up and down.
The·1 versions of the DM74ALS devices are identical to
their standard versions except that the recommended
maximum 10L is Increased to 24 mAo There are no ·1 ver·
slons of the DM54ALS devices.

Features
• Advanced low power oxide-isolated lon·lmplanted
Schottky TTL process
• Switching response specified Into 5000 and 50 pF load

• Switching response specifications guaranteed over
full temperature and Vee supply range
• PNP Input design reduces input loading
• Low power dissipation version of the DM54/74ALS240,
241
• Low level drive c,urrent: 54ALS = 8 mA, 74ALS = 16 mA,
74ALS·1 = 24 mA

Absolute Maximum Ratings
Supply Voltage, Vee
Input Voltage
Output Voltage
Storage Temperature Range

(Note 1)
7V

7V
5,5V
-65·Ct0150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety, of the device"cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at t~e absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the condjtions for actual device operation.

Connection Diagrams
Dual·ln·Llne Package

Dual·ln·Llne Package
lii-l

U

U

20t-Vee

111-1

lAl- 2

191-211

lAl- 2

19t-2G

2Y4,- 3

lBI-1Y1

2Y4- 3

lBI-1Y1

lA2- 4

17 j-2A4

lA2- 4

17t-2A4

2Y3- 5

16j-ln

2Y3- 5

16t-1Y2

lA3- 6

151--2A3

lA3- 6

15t-2A3

2Y2- 7

14t-1Y3

,

,

20t-Vee

2Y2- 7

14!-lY3

lA4- 8

13 -2A2

lA4- B

13!-2A2

2Yl- 9

12 -1Y4

2Yl- 9

12!-lY4

GND- 10

11-2Al

GND- 10

11 j-2Al

TOP VIEW

DM54ALS1240 (J)

Function Table

TOP VIEW

TLJF/8281·1

DM74ALS1240 (J, N) ,

DM54ALS1241 (J)

Enable
Input

G

G

Data
Buffer
Output

H

L
H

Active
TRI-STATE

L

2·295

TLIF/6251·2

DM1i4ALS1241 (J, N)

l>

CJ)r"'"
....
I\)

~

a
==

~
l>

....~
....~

Recommended Operating Conditions
Symbol

DM54ALS1240
DM54ALS1241

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL,

Low Level Input Voltage

10H

High Level Output Current

10L

Low Level Output Current
DM74ALS1240-1, DM74ALS1241-1

TA

DM74ALS1240
DM74ALS1241

Min

Typ

Max

Min

Typ

Max

'4.5

5

5.5

4.5

5

5.5

2

Operating Free-Air Temperature

Units

V

2

-55

V

0.8

0.8

-12

-15

mA

8

16

inA

-

24

mA

70

·c

125

0

V

Electrical Characteristics over recommended operating free·airtemperature range (unless otherwise specified)
Symbol

Parameter

DM54ALS1240
DM54ALS1241

Conditions

Min
VIK

Input Clamp Voltage Vee=4.5V,II= -18mA

VOH

High Level Output

Vee = 4.5V to 5.5V IOH= -0.4mA Vee- 2
2.4
Vee=4.5V
10H= -3mA
2
10H=Max

VOL

Low Level Output
Voltage

Vee=4.5V
10L = 54ALS (Max)
10L = 74ALS (Max)

II

Input Current at
Max Input Voltage

Vee=5.5V, VI=7V

IIH

High Level Input
Current

Vee = 5.5V, VI=2.7V

IlL

Low Level Input
Current

Vee = 5.5V, V IL =0.4V

10

Output Drive
Current

Vee = 5.5V, Vo =2.25V

10ZH

High Level
TRI·STATE Output
Current

Vee = 5.5V, Vo=2.7V

10ZL

Low Level
TRI-STATE Output
Current

Vee=5.5V, Vo=O.4V

Icc

Supply Current

Typ

DM74ALS1240
DM74ALS1241

Max

Min

Typ

-1.5

-1.5

0.25

0.4

-

-

0.25
0.35

0.4
0.5

V
V

0.1

0.1

mA

20

20

/LA

-0.1

mA

-0.1
-.: 112

-30

4
8

9

V
V
V
V

Vee- 2
2.4
2

~

Vee=5.5V, ALS1240
Outputs High
Outputs Low
, Outputs TRI·STATE ,

Units

Max

-30

-112

mA

20

20

/LA

-20

-20

/LA

6
12
13

mA
mA
mA

11
15

mA
rnA
mA

4
8

6
12
13

9
,

Vee = 5.5V, ALS1241
Outputs High
Outputs Low
Outputs TRI-STATE

7
10
11

2-296

11
15
17

7
10
11

17

c

'ALS1240 Switching Characteristics over recommended operating free-air temperature range

en
==

~

(See Section 1 for Test Waveforms and Output Load)

r-

Parameter

From
(Input)

Vcc = 4_5V to 5_5V,
C L =50 pF,
Rl =5000,
R2=500O,
TA=Min to Max

To
(Output)
54ALS1240
Min

tpLH

Typ

Max

A

Y

9

G

y

tPZL
tpHZ

G

Units

Y

tpLZ

Min

Typ

8-c
==
~

74ALS1240

tpHL
tPZH

en
....

l>

Max

fi)
....

8

ns

7

7

ns

19

18

ns

C

20

19

ns

7

6

ns

10

7

ns

;==r-

~

en
....
N

....
,j::oo

C

==
~

l>

r-

en
....

'ALS1241 Switching Characteristics over recommended operating free-air temperature range

....~

(See Section 1 for Test Waveforms and Output Load)

Parameter

From
(Input)

Vcc = 4_5V to 5_5V,
C L =50 pF,
R1 =5000,
R2 = 5000,
TA=Min to Max

To
(Output)

74ALS1241

54ALS1241
Min
tpLH

A

Typ

Max

Y

tpHL
tPZH

GorG

Y

tpZL
t pHZ

GorG

y

tpLZ

Min

Typ

Max

12

11

ns

13

12

ns

23

22

ns

22

21

ns

11

11

ns

19

16

ns

,

2-297

Units

Logic Diagrams

DM54174ALS1240

DM54174ALS1241

lii
__"""'I>_0--+......;1-.8 1Y1

>_-+......;1.;.8 lYl

>0--+.....:1:,6 lY2

>_-+....:1:;,.6 lY2

>0--+.....:1:,4 lY3

>_-+......;14';"lY3

2 lY4
>0-_.....:1:.

-=-_r>_ _.....:1:.21Y4

>0--+....;..9:.. 2Y1

>_-+....:9:" 2Y1

>0--+""::"2Y2

>_-+_7:" 2Y2

>0--+""::"2Y3

>_-+....;5;"2Y3

> __......;3:" 2Y4
TL/F/6261-3

TLIF/6261-4

2·298

.----------------------------------------------------------,0
3:

~National

;

~ Semiconductor

~
.....

DM54ALS1242/DM74ALS1242, DM54ALS1243/DM74ALS1243 ~
c
Quad Bidirectional Bus Drivers
s::

~

l>

General Description
These octal TRI-STATE'" bus drivers are designed to provide
the designer with flexibility in implementing a bus interface
with memory, mictroprocessor, or communication systems,
and are low power dissipation versions of the 'ALS242 and
'ALS243. The 'ALS1242 has inverting buffers, while the
'ALS1243 has non-inverting buffers. The direction enabie
gating is configured with separate control over either buffer
direction and the two control buffers are complementary.
Connecting these control inputs to one common line implements single line direction control, while individual control
can put both buffer directions into TRI-STATE simultaneously (disabled sltate) or put both buffer directions into the
active state (data latch state). The TRI-5TATE circuitry contains a feature that maintains the buffer outputs in TRISTATE (high impedance state) during power supply ramp-up
or ramp-down. Tllis eliminates bus glitching problems that
arise during power-up and power down.
.
The -1 versions of the DM74ALS devices are identical to
their standard versions except that the recommended
maximum 10L is increased to 24 mAo There are no -1 versions of the DMS4ALS devices.

• Low level drive current: 54ALS= 8 mA, 74ALS= 16 mA,
74ALS-1 = 24 mA .

Absolute Maximum Ratings
Supply Voltage, Vee
Input Voltage
Dedicated Inputs
1/0 Ports
Storage Temperature Range

• Advanced low power oxide-isolated ion-implanted
Schottky TTL process

Dual-In-Llne Package
GAB- 1

,

U

14 -Vee
13 -BBA

NC- 2
A1- 3

12 -NC

A2- 4

11-Bl

A3- 5

10 -82

A4- 6

9 -83

BND- 7

B -84
TDP VIEW
TliF/6262·'

DM54ALS1242, DMS4ALS1243 (J)
DM74ALS1242, DM74ALS1243 (J, N)

Function Table
Inputs
GAB

GBA

L
H
H
L

L
H
L
H

ALS1242

ALS1243

AtoS
StoA
Isolation
Latch Aand 8
(A=S)

AtoS
StoA
Isolation
Latch A and 8
(A=S)

2-299

~
.....

ftc
s::
;

~

~

c

s::

(Note 1)
7V

7V
5.SV
-6SD Ct0150D C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Features

Connection Diagram

• Switching response specified Into soon and SO pF load
• Switching response specifications guaranteed over
full temperature and Vee supply range
• PNP input design reduces input loading
• Low power dissipation version of the DM54/74ALS242,
243

~
l>
r-

en
.....

t

Recommended Operating Conditions
Parameter

Symbol

.

Vee

Sl,Ipply Voltage

V'H

High Level Input Voltage

V'L

Low Level Input Voltage

10H

High Level Output Current

10L

Low Level Output Current
DM74ALS1242·1, DM74ALS1243·1

TA

DM74ALS1242
DM74ALS1243

DM54ALS1242
DM54ALS1243
Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

V
V

2

2

Operating Free-Air Temperature

Units

Min

V

0.8

0.8

-12

-15

mA

8

16

mA

-

24

mA

70

DC

-55

125

0

Electrical Characteristics over recommended operating free-airtempe~ature range (unless otherwise specified)
Symbol

Parameter

Min

Typ

. Max

Min

Typ

Input Clamp Voltage Vec=4.5V,I,= -18 mA

VOH

High Level Output

Vee = 4.5V to 5.5V IOH= -0.4mA
IOH= -3mA
Vcc= 4.5V
IOH=Max

VOL

Low Level Output
Voltage

Vec=4.5V
IOL = 54ALS (Max)
IOl - 74ALS (Max)

I,

Input Current at
Max Input Voltage

Vee = 5.5V, V,=7V
.(V, = 5.5V for A or B Ports)

I'H

High Level Input
Current

Vee = 5.5V, V,=2.7V

I'l

Low Level Input
Curre(1t

Vcc =5.5V, V'l=O.4V

10

Output Drive
Current

IOZH

High Level
TRI-STATE Output
Current

Vcc= 5.5V, Vo=2.7V

10Zl

Low lievel
TRI-STATE Output
Current

Vcc =5.5V, Vo=0.4V

Icc

Supply Current

Vcc =5.5V, ALS1242
Active Outputs High
Active Outputs Low
Outpu~s TRI·STATE

Vcc-2
2.4
2

-

7
8

9
9
10
11

,

2·300

V
V
V
V

0.25
0.35

0.4
0.5

V
V

0.1

0.1

mA

20

20

I'A

-0.1

-0.1

mA

-112

mA

20

20

,.A

-20

-20

,.A

0.4

-

-112

-30

Vcc= 5.5V, ALS1243
Active Outputs High
Active Outputs Low
Outputs TRI-STATE

-1.5
Vec- 2
2.4
2

0.25

Vee=5.5V, Vo=2.25V

Units

Max

-1.5

V'K

(

DM74ALS1242
DM74ALS1243

DM54ALS1242
DM54ALS1243

Conditions

-30

7
8

10
13
14

9,

14
16
17

10
11

9

,

10
13
14

mA
mA
mA

14
16
17

mA
mA
mA

'ALS1242 Switching Characteristics over recommended operating free·air temperature range
(See Section 1 for Test Waveforms and Output Load)

Parameter

Vcc = 4.5V to 5.5V,
CL=5o pF,
R1 = 5000,
R2 = 5000,
TA=Min to Max

To
(Output)

From
(Input)

54ALS1242
Min
tpLH

AorB

74ALS1242

Typ

Max

BorA

tpHL
tpzH

GAB

B

tPZL
tpHZ

GAB

B

tpLZ
tPZL

GBA

A

tpzL
tpHZ

GBA

Units

A

tpLZ

Min

Typ

Max

9

8

ns

7

6

ns

23

20

ns

20

19

ns

7

7

ns

12

10

ns

22

21

ns

22

20

ns

11

10

ns

20

16

ns

'ALS1243 Switching Characteristics over recommended operating free·air temperature range
(See Section 1 for Test Waveforms and Output Load)

Parameter

From
(Input)

Vcc = 4.5V to 5.5V,
C L =50pF,
R1 =5000,
R2 = 5000,
TA=Min to Max

To
(Output)
54ALS1243
Min

tpLH

Aor B

74ALS1243

Typ

Max

BorA

tpHL
tPZH

GAB

B

tPZL
tpHZ

GAB

B

tpLZ
tpZL

GBA

A

tPZL
tpHZ

GBA

Units

A

tpLZ

Min

(

2·301

Max
11

ns

13

12

ns

23

22

ns

20

20

ns

7

7

ns

13

12

ns

23

22

ns

22

21

ns

11

11

ns

19

16

ns

\

1

Typ

12

('I)

~
.,...

Logic Diagrams

U)
...I

_-+...;1:;.8 1Y1

>_-+...;1:;.6 1Y2

>_-+...;1.;.4 1Y3

> _ _.....;1:;.21Y4

2A1

>_-+.....;9;"2Y1

TL.IFI6263·1

(J)

>--+-:"'2Y2

DM74ALS1244A (J, N)

Function Table

';;;"-1>--+""';;" 2Y3

Enable
Input
1~ or 2«

Data
Buffer
Outputs

L
H

Active
TRI·STATE

":':'-i>_ _ _3;;.. 2Y4
TLIFI6263·2

2-303 '

3:

~
l>

~
.....

i

;'

Recommended Operating Conditions
Symbol

DM54ALS1244A

Parameter

Min'

Vee

Supply Voltage

4.5

VIH

High Level Input Voltage

.2

Vil

Low Level Input Voltag'e

10H
10l

TA

DM74ALS1244A

Typ

Max

Min

Typ

Max

5

5.5

4.5

5

5.5

Units
V
V

2

V

0.8

0.8

High Level Output Current

'-12

-15

mA

Low Level Output Current

8

16

mA

DM74ALS1244A-1

-

24

mA

70

·C

Operating Free-Air Temperature

-55

125

0

,

Electrical Characteristics over recommended operating free-air temperature rang~ (unless otherwise specified)
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage Vce ,;,4.5V, 11= -18 mA

VOH

High Level Output

Vee=4.5V, 10H= -0.4 mA
Il oH =-3mA
!'OH=Max

VOL

Low Level Output
Voltage

Vee=4.5V
1m = 54ALS (Max)
10l = 74ALS (Max)

II

Input Current at
Max Input Voltage

i

Typ

Min

Typ

-1.5
Vee- 2
2.4
2

-

Max
-1.5

Vee- 2
12.4
2
0.25

,

DM74ALS1244A

Max

0.4

.
0.25
0.35

-

Units
V
V
V
V

0.4
0.5

V
V

Ve e=5.5V, VI =7V
(V 1= 5.5V for A or B Ports)

0.1

0.1

mA

20

20

/LA

IIH

High Level Input
Current

Vee = 5.5V, VI = 2.7V

III

Low Level Input
Current

Vee = 5.5V, V ll =O.4V

10

Output Drive
Current

Vee = 5.5V, Vo = 2.25V

10ZH

High Level
TRI-STATE Output
Current

Vee=5.5V, Vo=2.7V

10Zl

Low Level
TRI-STATE Output
Current

Vee=5.5V, Vo=0.4V

Icc

Supply Current

Vee = 5.5V
Outputs High
Outputs Low
Outputs TRI-STATE

-

DM54ALS1244A
Min

-30

6
10
11

'--,--.

2-304

-0.1

.

-0.1

mA

-112

-30

-112

mA

20

20

/LA

-20

-20

/LA

11

mA
mA
mA

15
20
25

6
10
11

17
20

Switching Characteristics over recommended operating free-air temperature range

Parameter

From
(Input)

Vee = 4.5V to 5.5V,
C L =50pF,
R1 =5000,
R2=5000,
TA=Min to Max

To
(Output)

54ALS1244A
Min
tpLH

A

y

tpHL
tpZH

G

y

tPZL
tpHZ

G

y

tpLZ

Max

Units

74ALS1244A
Min

Max

3

16

3

14

ns

3

16

3

14

ns

6

26

6

22

ns

6

26

6

22

ns

2

12

2

10

ns

3

16

3

13

ns

\

.2·305

~National

~ Semiconductor

DM54ALS1245A/DM74ALS1245A
TRI·STATE® Bus Transceivers
General Desc;ription
This advanced low power Schottky device contains 8 pairs
of TR,I-STATE logic elements configured as octal bus
transQeivers_ This circuit Is designed for use In memory,
microprocessor systems ?nd in asynchronous bidirectional data buses. Two way communication between
buses is controlled by the (DIR) input. Data either
transmits from the A bus to the B bus or from the B bus to
the A bus. Both the driver and receiver outputs can be
, disabled via the (G) enable input which causes outputs to
enter the high Impedance mode. So that the buses are effectively isolated TTL, the TRI-STATE circuitry also contains a protection feature that prevents the buffer from
glitching the bus during power-up or power-down.

Features
• Low power versions of ALS245A
• Advanced oxide-isolated, ion-implanted Schottky TTL
process

• Low output Impedance to drive terminated
transmission lines to 13311
• Switching response specified into 5000/50 pF
• Switching specifications guaranteed over full
temperature and Vcc range

Absolute Maximum Ratings (Note 1)
Supply Voltage, Vcc
7V
Input Voltage
7V
Storage Temperature Range
- 65·Cto + 150·C
LeadTemperature(Solderlng, 10 seconds)
+300·C
Note 1: The "Absolute Maximum Ratings" are those values beyond
which the s.fety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric vatues defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Condltlons"table will
define the conditions for actual device operation.
.

• Choice of true or inverting logic
• TRI-STATE outputs independently controlled on A and
B buses

Connection Diagram

Function Table

Dual-In-Llne Package

Control
Inputs

rrrrrrrr

Operation

G

DIR

L
L
H

L
H

A Data to B Bus

X

HI-Z

B Data to A Bus

L= low logic level
H = high logic level
X = either low or high logic level
HI·Z = high Impedance (off) state

TLlFfS438·'

54ALS1245A (J)

74ALS1245A (J, N)

2-306

Recommended Operating Conditions
Symbol

DM54ALS1245A

Parameter

Vee
VIH'

Supply Voltage

VIL

Low Level Input Voltage

10H
10L

Min

Typ

4.5

5

High Level Input Voltage

DM74ALS1245A
Max,
5.5

2

Min

Typ

Max

4.5

5

5.5

V

2

V

0.8

0.8

High Level Output Current

-12

-15

mA

Low Level Output Current

8

74ALS·1 Option Only
TA

Units

Operating Free Air
Temperature Range

-55

125

0

V

16

mA

24

mA

70

·C

Electrical Characteristics over re~ommended operating free air temperature range.
All typical values are measured at Vee =5V, TA=25·C.
Symbol

Parameter

Conditions

VIK

Input Clamp
Voltage

VOH

High Level Output Vee = 4.5V, 10H= -3 mA
Voltage
Vee = 4.5V, 10H=Max

Low Level Output
Voltage

Vec=4.5V

Typ
\

Vee = 45V, IIN='-18 mA

10H = - 0.4 mA,
Vee = 4.5V to 5.5V
VOL

DM54ALS1245A
Min

DM74ALS1245A
Max

Min

Typ

Max
-1.5

-1.5

Units
V

2.4

3.2

2.4

3.2

V

2

2.3

2

2.3

V

0.25

IOL=8mA

V

Vee- 2

Vce- 2

0.25

0.4

V

0.35

0.5

V

0.1

0.1

mA

0.4

IOL=16mA
(Note 3)

II

Input Current at
Max Input
Voltage

IIH

High Level
Input Current

Vee = 5.5V, VIN=2.7V

20

20

p.A

IlL

Low Level Input
Current·

Vee = 5.5V, V IN =0.4V

-0.1

-0.1

mA

10

Output Drive
Current

Vee = 5.5V, Vo =2.25V

-112

mA

Icc

Supply Current

Ve e =5.5V

Vee = 5.5V, VIN = 7V
' (V IN 5.5V for A or B Ports)

=

-112

-30

-30

Outputs High

21

33

21

30

mA

Outputs Low

23

36

23

33

mA

TRI·STATE

25

40

25

36

mA

2·307

Switching Characteristics over reo::ommended operating free air temperature range (Notes 1 and 2),
All typical values are measured at Vee

Symbol

=5V, TA =25°C,
DM54ALS1245A

Circuit
Configuration

Parameter

Typ

DM74ALS1245A
Typ

Units

Max

Min

2

15

2

13

ns

2

15

2

13

ns

25

ns

Min

Max

tpLH'

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

tPZL

Output Enable Time to Low Level

8

28

8

tPZH

Output Enable Time to High Level

8

28

8

25

ns

tpLZ

Output Disable Time from Low Level

3

22

3

18

ns

tpHz

Output Disable Time from High Level

2

14

2

12

' ns

,"~OUT

'"$

AOIII
OUT

,

Nole 1: See Section 1 for test waveforms and output load.
Nole 2: Switching characteristic conditions are Vee =4.5V to 5.5V. RL =5000. eL = 50 pF.
Nole 3: IOL=24 mA for·1 option.

.
I

"

.
,

2-308

.
~ Semiconductor

PRELIMINARY

~National

DM54ALS1620/DM74ALS1620 Octal TRI·STATE®
Bus Transceivers
General Description
This advanced low power Schottky device contains 8 pairs ' . TRI-STATE outputs on A and B buses
of TRI-STATE log elements configured as an octal bus • PNP Input design reduces input loading
transceiver. It is designed for use in memory, micro• Local bus-latch capability
processor systems and in asynchronous bidirectional
data buses. Data transmission from the A bus to the B bus • Switching response specified into 5000/50 pF
or from the B bus to the A bus is selectively controlled by • Switching specifications guaranteed over full
temperature and Vee range
(GBA and GAB) the enable inputs. These inputs are also
used to disable the devices so that the buses are effec- • Low output impedance to drive terminated
transmission lines to 1330
tively isolated.
The dual-enable configuration gives the ALS1620 the
capability to store data by simultaneous enabling of GBA
and GAB. Each output reinforces its input in this transceiver configuration. Thus, when both control inputs are
enabled and all other data sources to the two sets of bus
lines are at high impedance, both sets of bus lines will remain at their last logic states.
-

Absolute Maximum Ratings (Note 1)
Supply Voltage, Vee
Input Voltage
Storage Temperature Range
- 65·Cto
Lead Temperature (Soldering, 10 seconds)

7V
7V

+ 150·C
+ 300·C

• Low power version of ALS620
• Advanced oxide-isolated, ion Implanted Schottky
process

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Features

Dual·ln·Line Package

t

Enable Inputs
GBA

w

~

M

~

~

M

M

M

~

Operation

GAB

L

L

B Data to A Bus

H

H

A Data to B Bus

H

L

Hi-Z

L

H

B Data to A Bus
A Data to B Bus

~

TOP VIEW
TL/F/62f14.1

54ALS1620 (J)

74ALS1620 (J, N)

This document contains information on a product under development. NSC reserves the right to change or discontinue this product without notice.

2-309

,

Recommended Operating Conditions
Symbol

DM54ALS1620

Parameter

Vcc

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

DM74ALS1620

Min

Typ

Max

4.5

5

5.5

Min

Typ

Max

4.5

5

5.5

·2

2

Units
V
V

0.8

0.8

IOH

High Level Output Current

-12

-15

mA

IOL

Low Level Output Current

8

DM74ALS1620-1
TA

-55

Operating Free Air Temperature
Range

125

0

V

16

mA

24

mA

70

'c

• Applies to 74AL5-1 options.

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vcc = 5V, TA = 25'C.
Symbol

Parameter

VIK

Input Clamp
Voltage

VOH

High Level
Output Voltage

Conditions

Vcc = 4.5V, IOH = - 3 mA

IOH = - 0.4 mA,
VOL = 4.5V to 5.5V
VOL

Low Level
Output Voltage

Typ

Vcc=4.5V

Max

Typ

Min

-1.5

Vcc= 45V, IIN= -18 mA

Vcc = 4.5'y, I OH = Max

. DM74ALS1620

DM54ALS1620
Min

2.4

-1.5
2.4

3.2

3.2

2

Vcc- 2

Vcc- 2
0.25

0.4

DM74ALS
IOL=16mA
(Note 3)

Units
V
V

,

2

DM54/74ALS
IOL=8 mA

Max

0.25

0.4

0.35

0.5

V

II

Input Current at
Max Input
Voltage

Vcc=5.5V, VIN=7V
(VIN=5.5V for A or 8 Ports)

0.1

0.1

mA

IIH

High Level
Input Current

Vcc = 5.5V, VIN = 2.7V

20

20

mA

IlL

Low Level Input
Current

Vcc= 5.5V, VIN ",0.4V

-0.1

-0.1

mA

10

Output Drive
Current

Vcc=5.5V, VouT=2.25V

-112

mA

Icc

Supply Current

Vcc=5.5V
\

-30

-112

-30

Outputs High

14

14

Outputs Low

19

19

TRI·STATE

21

21

.
2·310

mA

Switching Characteristics over recommended operating free air temperature range (Notes'1 and 2)
All typical values are measured at Vee = 5V, TA = 25"C,
Symbol

Parameter

tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

tPZL

Output Enable Time to Low Level

tPZH

Output Enable Time to High Level

tpLZ

Output Disable Time from Low Level

tpHZ

Output Disable Time from High Level

tPZL

Output Enable Time to Low Level

tpZH

Output Enable Time to High Level

tpLZ

Output Disable Time from Low Level

tpHZ

Output Disable Time from High Level

Circuit
Configuration .

DM54ALS1620
Min

IN~OUT
IN~OUT

Max

DM74ALS1620
Min

Typ

Max

Units

9

9

ns

6

6

ns

9

9

ns

6

6

ns

17

17

ns

A

14

14

ns

OUT

11

11

ns

7

7

ns

17

17

ns

14

14

ns

11

11

ns

7

7

ns

~
iiBA

Typ

~
GAB

ou

.

I

Nole 1: See Section 1 for test waveforms and output load,
Nole 2: Switching characteristic conditions are Vee = 4,5V to 5.5V, RL = 5000, eL = 50 pF.
Nole 3: IOL=24mA for ,1 option.

2-311

PRELIMINARY

~National

~ Semiconductor
DM54Al.S1621 I DM74ALS1621,
DM54ALS1622/DM74ALS1622
Octal Open Collector Output Bus Transceivers

,..

~

~
,..

~


General Description
This advanced low power Schottky device contains 8 pairs
of TRI-STATE log elements configured as an octal bus
transceiver. It is designed for use in memory, microprocessor systems and in asynchronous bidirectional
data buses. Data transmission from the A bus to the B bus
or from the B bus to the A bus Is selectively controlled by
(GBA and GAB) the enable inputs. These inputs are also
used to disable the devices so that the buses are effectively isolated.
The dual-enable configuration gives the ALS1623 the
capability to store data by simultaneous enabling of GBA
and GAB. Each output reinforces its input in this transceiver configuration. Thus, when both control inputs are
enabled and all other data sources to the two sets of bus
lines are at high impedance, both sets of bus lines.will remain at their last logic states.

Features

•
•
•
•
•

TRI-STATE outputs on A and B buses
PNP input design reduces input loading
Local bus-latch capability
.
Switching response specified into 5000/50 pF load
Switching specifications guaranteed over full
temperature and Vee range
• Low output impedance to drive terminated
transmission lines \0 1330

Absolute Maximum Ratings (Note 1)
Supply Voltage, Vee
Input Voltage
Storage Temperature Range
- 65·C to
Lead Temperature (Soldering, 10 seconds)

7V
7V
+ 150·C
+ 300·C

• Low power version of ALS623
• Advanced oxide-isolated, ion implanted Schottky
• process

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual-In-Line Package

jC
20

-

iiiA
19

18
18

58

48
2j
17

3j
16

J

I

'i7-

15

14

68

78

13

12

88

11

Enable Inputs
GBA

r-r.3Ii7 Ll; 7 ill; 7 Ill; 7Ll; 71Ls; 7 Ll; 71Ls; 7

(2

W

~

J.3 J.4
~

M

Operation

GAB

L

L

B Data to A Bus

H

H

A Data to B Bus

H

L

Hi-Z

L

H

B Data to A Bus
A Data to B Bus

15 16 J7 18 .1.9 Jl0
!TOP VIEW~ ~ !
~
M

TUFI6264-1

54ALS1623 (J)

74ALS1623 (J, N)

This document contains information on a product under development. NSC reserves the right to change or discontinue this product without notice.

2-315

..
~
~

Co)

Recommended Operating Conditions
Symbol

DM54ALS1623

Parameter

DM74ALS1623

Units

Min

TYP

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

V

0.8

0.8

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

10H

High Level Output Current

-12

-15

mA

10L

Low Level Output Current

8

16

mA

24

mA

70

·c

2

2

V

DM74ALS1623·1
TA

Operating Free Air Temperature

-55

125

0

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA=25·C,
Symbol

Parameter

Conditions

VIK

Input Clamp
Voltage

Vee = 45V, IIN= -18 rnA

VOH

High Level
Output Voltage

Vee = 4.5V, 10H = - 3 mA
Vee = 4.5V, 10H=Max
10H= -0.4mA,
Vee = 4.5V to 5.5V

VOL

Low Level
Output Voltage

Vee=4.5V

2.4

3.2

-1.5
2.4

2
Vee- 2

Max

3.2

Units
V
V

2

V

Vee- 2

V'
0.4

0.35

0.5

V

For 74ALS·1
Option Only
IOL=24 rnA

0.35

0.5

V

0.1

mA

High Level
Input Current

Vee = 5.5V,
VIN =0.4V

TYP

0.25

IIH

IlL

Min

IOL=16 mA

Input Current at Vee = 5.5V, VIN=7V
(V IN = 5.5\1 for A or B Ports)
Max Input
Voltage

Low Level Input
Current

TYP

Max
-1.5

0.25

IOL=8rnA

II

Vee = 5.5V,
VIN=2.7V

DM74ALS1623

DM54ALS1623
Min

0.4

0.1

V

Aor B Ports

20

20

mA

Control Inputs

20

20

mA

Aor B Ports

-0.1

-0.1

mA

Control Inputs

-0.1

-0.1

mA

-112

- mA

10

Output Drive
Current

Vee = 5.5V, VOUT=2.25V

Icc

Supply Current

Vee =5.5V

-30

-112

-30

Outputs High

11

11

mA

Outputs Low

18

18

rnA

TRI·STATE

13

13

rnA

2-316

SWitching Characteristics over recommended operating free' air temperature range (Note 1).
All typical values are measured at Vee = 5V, TA = 25°C.
Symbol

Parameter

t pLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
Hi,gh to Low Level Output

tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

tPZL

Output Enable Time to Low Level

tPZH

Output Enable Time to High Level

tpLZ

Output Disable Time from Low Level

tpHz

DM54ALS1623

Circuit
Configuration

Min

Typ

Max

DM74ALS1623
Min

Typ

Units

Max

8

8

ns

8

8

ns

8

8

ns

8

8

ns

21

21

ns

18

18

ns

13

13

ns

Output Disable Time from High Level

12

12

ns

tPZL

Output Enable Time to Low Level

21

21

ns

tpZH

Output Enable Time to Low Level

18

18

ns

tpLZ

Output Disable Time from Low Level

13

13 .

ns

tpHZ

Output Disable Time from High Level

12

12

ns

. .
,,+'"
. .
,,+-'"'
'~o~'
iI

-'~

.

'"

Notal: Sa. Section 1 for test waveforms and output load.
Nota 2: Switching characteristic conditions are Vee=4.5Vto 5.5V, RL=500D, eL=50 pF.
Nota 3: IOL=24 mA for·l option.

2·317

-

! ~National
.
~ ~ Semiconductor

PRELIMINARY

~

:E

c DM54ALS1638/DM74ALS1638, DM54ALS1639/DM74ALS1639

m Octal Bus Transceivers
~

~

:is

c

~

~

 octal
bus transceivers are designed to provide high speed bidirectional communication between data buses. The output
characteristics of the circuits are low enough impedance
to drive transmission lines terminated down to 1330. The
input characteristics of the circuits are high impedance so
they will not significantly load the transmission line.
These devices allow B-bit wide bidirectional data transmission controlled by the logic level at the (DIR) input. The
TRI·STATE enable Input (~) can be used to isolate both
buses. In addition, the TRI-STATE circuitry coptains a protection feature that prevents the buffer from glitching the
bus during power-up or power-down. To provjde design
flexibility, the 'ALS1638 and' ALS1639 have open-collector
outputs on the A bus and TRI-STATE outputs on the B bus .

• Switching response specified into 5000 and 50 pF load
• Switching response specifications guaranteed over
full temperature and Vcc supply range
• PNP input design reduces input loading
• Low level drive current 74ALS-1 =24 mAo
74ALS = 16 mA, 54ALS = 8 mA
• Glitch-free bus during power·up/down
• A bus outputs are open-collector, B bus outputs are'
TRI-STATE

Absolute Maximum Ratings

7V

Supply Voltage, Vcc
Input Voltage
Control Inputs
A Bus I/O Ports
B Bus I/O Ports
Storage Temperature Range

The DM74ALS-1 version of these devices is identical to its
standard counterparts except that maximum recom·mended IOL has been Increased to 24 mAo There is no
54ALS-1 version of these parts.

(Note 1)

7V
7V
5.5V
-65"Cto150"C

Features
• Low power versions of ALS638, 639
• Advanced low power oxide-isolated ion-implanted
Schottky TTL process
• Functional and pin compatible with the
DM54/74ALS638,639

Note 1: The "'Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametriC values defined In the
"'Electrical Characteristics"' table are not guaranteed at the absolute
maximum ratings. The "'Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Connection Diagram·
Dual·ln·Llne Package
OIR- 1

U

20 ~Vcc

Al- 2

191-11

A2- 3

181-Bl

A3- 4

17~B2

A4- 5

Control
Inputs

'ei

DIR

'ALS1638

'ALS1639

L
L

L

B data to A bus
A data to B bus
Isolation

B data to A bus
A data to B bus
Isolation

H

A5-6

151-B4

A6- 7

141-B5

Operation

H
X

)

A7- B

AB- 9
GNO-L.;l~O_ _ _.....:.ll;.JI-BB

TOP VIEW

ru'''....'

DM54ALS1638, DM54ALS1639 (J)
DM74ALS1638, DM74ALS1839 (N)
This document contains Information on a product under development. NSC reserves the right to change or discontinue this product without notice.

2-318

Recommended Operating Conditions
Symbol

DM14ALS1638
DM14ALS1639

DM54ALS1638
DM54ALS1639

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

10H

High Level Output Current, B Bus Only

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

2

Units

V

2

V

0.8

0.8

-12

-15

mA

V

Low Level Output Current

8

16

mA

14ALS-1

-

24

mA

VOH

High Level Output Voltage, A Bus Only

5.5

5.5

V

TA

Operating Free-Air Temperature

70

·c

10L

-55

125

0

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise specified)
Symbol

Parameter

DM54ALS

Conditions

Min

Typ

DM74ALS
Max

Min

Typ

-1.5

Max
-1.5

Units
V

VIK

InpulClamp Voltage Vce;= 4.5V, II = -18 mA

VOH

High Level Output
Vee = 4.5V to 5.5V 10H= -0.4mA
Voltage, B Bus Only Vee = 4.5V
10H= -3mA
10H = Max

VOL

Low Level Output
Voltage

Vee=4.5V
IOL=8mA
!oL=16 mA
10L = 24 mA for -1 Options

Input Current at
Max Input Voltage

Vee = 5.5V, VI =7VI(Controllnputs;

IIH

High Level Input
.Current

IlL

Low Level Input
Current

Vee = 5.5V, VIL = 0.4V1Control Inputs)

-0.10

-0.10

mA

(110 Port)

-0.10

-0.10

mA

10

Output Drive
Current

Vee = 5.5V, Vo=2.25V
(B Ports Only)

-112

mA

10H

High Level Output
Current

Vee = 4.5V, VOH=5.5V
(A BusOhly)

Icc

Supply Current
ALS1638

Vcc=5.5V_
Outputs High
Outputs Low
Outputs Disabled

21
23
25

21
23
25

mA
mA
mA

ALS1639

Outputs High
Outputs Low
Outputs Disabled

21
23
25

21
23
25

mA
mA
mA

II

V
V
V

Vee- 2
2.4
2

Vee- 2
2.4
2

0.4
0.5
0.5

V
V
V

0.1

0.1

mA

VI =5.5V (110 Ports)

0.1

0.1

mA

Vee = 5.5V, VI = 2.7V

20

20

/LA

0.25

-

-30

0.25
0.35
0.35

0.4

-

-112

-30

0.1

0.1

2-319

mA

-

'

'ALS1638 Switching Characteristics (Note 1)

Parameter

.
tpLH

From
(Input)

Vee = 4.5V to 5.5V,
CL=50pF,
RL = 5000 (A Outputs),
TA = Min to Max

To
(Output)
Min

A

B

tpHL
tpLH

B

A

tpHL
t,PLH

G

A

tpHL
tPZH

G

B

tPZL
tpHZ

G

B

tpLZ

Typ

Units
DM74ALS1638

DM54ALS1638
Max

Min

Typ

Max

6

6

ns

21

21

ns

6

6

ns

8

8

ns

23

23

ns

17

17

ns

12

12

ns

15

15

ns

6

6

ns

7

7

ns

'ALS1639 Switching Characteristics (Note 1)

Parameter

From
(Input)

Vee = 4.5V to 5.5V,
C L =50 pF,
RL=500D,
TA=Mln to Max

To
(Output)
DM54ALS1639
Min

tpLH

A

B

tpHL
tpLH

B

A

tpHL
tpLH

(;-

A

tpHL
tPZH

G

B

tPZL
tpHZ

G

B

tpLZ

Typ

' -

Units
DM74ALS1639

Max

Min,

Typ

Max

7

7

ns

21

21

ns

7

7

ns

9

9

ns

23

23

ns

19

19

ns

14

14

ns

17

17

ns

7

7

ns

9

9

' ns

Notet: See Section 1 for lesl w~veforms and oulpulload,

2-320

.---------------------------------------------------------------------~c

s::

Logic Diagrams
'ALS1638

~
.en
....

'ALS1639

0)

ii

19

-s::
~

~

c

DIR

~
l>

DIR

.en

Al 2

18

81

Al

81

A2

17 82

A2

82

....

~
c

TO SIX OTHER TRANSCEIVERS

TO SIX OTHER TRANSCEIVERS
TLIF/6266·2

OC denotes open-collector outputs

TLIF16266·3

s::

.-~

en
....

0)

-s::
~

c

~

l>
.en

....

&i

~ ~ National

r-

V

Vee

2

0

C/)

.....

16

mA

24

mA

70

°C

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise specified)
DM54ALS
Symbol

Parameter

Conditions

V'K

Input Clamp
Voltage

Vee = 4.5V,
1,=-18mA

VOL

Low Level Output
Voltage

Vee = 4.5V
IOL = 12mA
'OL 24mA

Min

Typ

DM74ALS
Max

Min

Typ

-1.5

0.25

0.4

Max

Units

-1.5

V

0.25
0.35

0.4
0.5

V
V

0.35

0.5

V

DM74ALS-1

IOL = 4BmA

Input Current at
Max Input Voltage

Vee = 5.5V
V,=7V

0.1

0.1

mA

VI = 5.5V (1/0 Port)

0.1

0.1

mA

I'H

High Level Input
Current

Vee = 5.5V,
V, = 2.7V

20

20

!LA

IlL

Low Level Input
Current

Vee = 5.5V,
VIL = 0.4V

-0.1

-0.1

mA

(1/0 Port)

-0.1

-0.1

mA

0.1

0.1

mA

I,

IOH

High Level Output
Current

Vee = 4.5V
VOH = 5.5V

lee

Supply Current

Vee = 5.5V

ALS1641

23

23

mA

ALS1642

20

20

mA

ALS1644

22

22

mA

2-327

~
o

::t

i!
.....

~
~

en
r-

.....
0)

TO SEVEN OTHER TRANSCEIVERS
TL/F/62S8·4

-:ts:
c

~

l>
r-

OC denotes open-collector outputs

en
.....

t

2-329

Section 3

Advanced Schottky

Section Contents
DM54/74ASOO Quad 2-lnput NAND Gates .............................................
DM54/74AS02 Quad 2-lnput NOR Gates ................................. '. . . . . . . . . . . . . .
DM54/74AS04 Hex Inverters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS08Quad 2-lnput AND Gates ...............................................
DM54/74AS10Triple3-lnputNANDGates .............................................
DM54/74AS11.Triple3-lnputANDGates. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .. . .
DM54/74AS20DuaI4-lnputNANDGates..............................................
DM54"74AS21 Dual 4-lnput AND Gates ...............................................
DM54/74AS27 Triple 3-lnput NOR Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .
DM54/74AS30 8·lnput NAND Gate ..................................................
DM54/74AS32 Quad 2-lnputOR Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS34 Hex Non-Inverter ..................................... " . . . . . . . . . . . . . . .
DM54/74AS74 Dual Positive-Edge-Triggered D Flip·Flops with Preset and Clear. . . . . . . . . . . . . . . .
DM54/74AS86 Quad 2-lnput Exclusive-OR Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS95 4-Bit Parallel Access Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS109 Dual Positive-Edge-Triggered J-K Flip-Flops with Preset and Clear. . . . . . . . . . . . . .
DM54/74AS112 Dual Negative·Edge-Triggered J-K Flip-Flops with Preset and Clear. . . . . . . . . . . . .
DM54/74AS113 Dual Negative-Edge·Triggered J-K Flip-Flops with Preset. . . . . . . . . . . . . . . . . . . . . .
DM54/74AS114 Dual Negative-Edge-Triggered J-K Flip-Flops
with Preset, Common Clear, and Common Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS131 3 to 8 Line Decoder/Demultiplexer with Address
StoraQe Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS136 Quad Exclusive·OR Gates with Open-Collector Outputs .....................
DM54/74AS137 3to 8 Line DecoderlDemultiplexerwith Address Latches. . . . . . . . . . . . . . . . . . . .
DM54/74AS138 3t08 Line DecoderlDemultiplexer. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .
DM54/74AS151 8:Line to 1-Line Data Selector/Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS153 Dual4·Line to 1-Line Data Selectors/Multiplexers ................. :........
DM54/74AS157 Quad 2to 1 Line DataSelectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS158 Quad 2 to 1 Line Inverting DataSelectors/Multiplexers ......................
DM54/74AS160 Synchronous 4-Bit Decade Counter with Asynchronous Clear ............ ~ . . . .
DM54/74AS161 Synchronous4-Bit Binary Counter with Asynchronous Clear. . . . . . . . . . . . . . . . . .
DM54/74AS162 Synchronous 4-Bit Decade Counter with Synchronous Clear. . . . . . . . . . . . . . . . . .
DM54/74AS163 Synchronous 4-Bit Binary Counter with Synchronous Clear. . . . . . . . . . . . . . . . . . .
DM54/74AS168 Synchronous4-Bit UplDown Decade Counter .............................
DM54/74AS169 Synchronous 4-Bit Up/Down Binary Counter ..............................
DM54/74AS174 Hex D FI ip-Flops with Clear. . . . . . .. . . . . .. . . . . . . . . . . . . . . . . . . .. .. . .. . . . . .
DM54/74AS175 Quad D Flip-Flops with Clear and Complementary Outputs . . . . . . . . . . . . . . . . . . .
DM54/74AS181 B Arithmetic Logic Unit/Function Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS182 Look-Ahead Carry Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS194 4-Bit Bidirectional Universal Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS195 4-Bit Parallel Access Shift Registers .. , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS230 Octal TRI-STATE Bus Drivers/Receivers with
True and Inverting Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . .. . . . . . . . . ..
DM54/74AS231 Octal TRI-STATE Inverting Bus Drivers/Receivers. . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS2400ctal TRI·STATE Inverting Buffers/Line Drivers/Line Receivers. . . . . .. . . . . . . . . .
DM54/74AS241 Octal TRI-STATE Buffers/Line Drivers/Line Receivers .......................
DM54/74AS242 Octal TRI-STATE Inverting Bus Transceivers ................. ,' ............. '
DM54/74AS243 Octal TRI-STATE Bus Transceivers ......................................
DM54/74AS244 bctal TRI-STATE Buffers/Line Drivers/Line Receivers

3-2

3-5
3-7
3-9
3-11
3-13
3-15
3-17
3-19
3-21
3-23
3-25
3-27
3-29
3-32
3-34
3-37
3-40
3-43
3-46
3-49
3-52
3-54
3-57
' 3-60
3-63-'
3-66
3-66
3-70
3-70
3-70
3-70
3-77
3-77
3-82
3-82
3-85
3-93
3-97
3-100
3-102
3-102
3-105
3-105
3-105
3-105
3-105

Secti~n

Contents (Continued)

DM54/74AS245A Octal TRI-STATE Bus Transceivers
DM54/74AS251 TRI-STATE 8-Line to 1-Line Data Selector/Multiplexer with
Complementary Outputs ........................................................
DM54/74AS253 Dual TRI-STATE4-Line to 1-Line Data Selectors/Multiplexers. . . . . . . . . . . . . . . . . .
DM54/74AS257 Quad TRI-STATE 2 to 1 Line Data Selectors/Multiplexers . . . . . . . . . . . . . . . . . . . . .
DM54174AS258 Quad TRI-STATE 2 to 1 Line Inverting Data Selectors/Multiplexers. . . . . . . . . . . . . .
DM54/74AS264 Counter Look Ahead Carry Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS280 9-Bit Parity Generator/Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS282 Look Ahead Carry Generatorwith Selectable Carry Inputs. . . . . . . . . . . . . . . . . . . .
DM54/74AS286 Parity Generator/Checker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS352 Dual4-Line to 1-Line Inverting DataSelector/Multiplexer ..................... DM54/74AS353 Dual TRI-STATE4-Line to 1-Line Data Selector/Multiplexer . . . . . . . . . . . . . . . . . . . .
DM54/74AS373 Octal TRI-STATE TransparentD Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS374 Octal TRI-STATE Positive-Edge-Triggered D Flip-Flops. . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS533 Octal TRI-STATE Inverting Transparent D Latches. . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS534 Octal TRI-STATE Inverting Positive-Edge-Triggered D Flip-Flops ...............
DM54/74AS573 Octal TRI-STATE TransparentD Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS574 Octal TRI-STATE Positive-Edge-Triggered D FI ip-Flops ....................... '
DM54/74AS575 Octal TRI-STATE Positive-Edge-Triggered D Flip-Flops
with Synchronous Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS576 Octal TRI-STATE Inverting Positive-Edge-Triggered D Flip-Flops ...............
DM54/74AS577 Octal TRI-STATE Inverting Positive-Edge-Triggered
D Flip-Flops with Synchronous Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS580 Octal TRI-STATE Inverting TransparentD Latches .......................... .DM54/74AS620 Octal TRI-STATE Inverting Bus Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS621 Octal Bus Transceivers with Open Collector Outputs . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS622 Octal Inverting Bus Transceivers with Open Collector Outputs ................
DM54/74AS623 Octal TRI-STATE Bus Transceiver .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS638 Octal Inverting Bus Transceivers with
Open Collector and TRI-STATE Outputs .............. : .......... '. . . . . . . . . . . . . . . .. . . .
DM54/74AS639 Octal Bus Transceivers with Open Collector
andTRI-STATEOutputs .........................................................
DM54/74AS640 Octal TRI-STATE Inverting Bus Transceivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS641 Octal Bus Transceivers with Open-Collector Outputs ..................... : . .
DM54/74AS642 Octal Inverting Bus Transceivers with Open-Collector Outputs ................
DM54/74AS643 Octal TRI-STATETrue and Inverting Bus Transceivers ............... : . . . . . . . .
DM54/74AS644 Octal True and Inverting Bus Transceivers with
Open-Collector Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS645 Octal TRI-STATE Bus Transceivers .....................,.................
DM54/74AS646 Octal TRI-STATE Bus Transceivers/Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS648 Octal TRI-STATE Inverting Bus Transceivers/Registers ......................
DM54/74AS651 Octal TRI-STATE Inverting Bus Transceivers/Registers ......................
DM54/74AS652 Octal TRI-STATE Bus Transceivers/Registers .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS804B Hex2-lnput NAND Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS805B Hex2-lnput NOR Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS808B Hex2-lnputAND Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS810Quad2-lnput Exclusive NOR Gates .... , ............................. , . . .
DM54/74AS811 Quad 2-lnput Exclusive NOR Gates with Open Collector Outputs ..............
DM54/74AS832B Hex2-lnput OR Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-3

3-111
3-113
3-117
3-120
3-120
3-124
3-129
3-132
3-136
3-141
3-144
3-147
3-150
3-154
3-157
3-161
3-164
3-167
3-170
3-174
3-178
3-181.
3-181
3-181
3-181
3-186
3-186
3-189
3-189
3-189
3-189
3-189
3-189
3-194
3-194
3-199
3-199
3-204
3-206
3-208
3-210
3-213
3-216

SecUon Contents (Continued)
DM54/74ASB41 10-Bit Bus Interface D-Type Latches with TRI-STATEOutputs . . . . . . . . . . . . . . . . .
DM54/74AS842 10-Bit Inverting Bus Interface D-Type Latches
with TRI-STATE Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS843 9-Bit Bus Interface D-Type Latches with T,RI-STAT~ Outputs. . . . . . . . . . . . . .. . . .
DM54/74AS844 9-Bit Inverting Bus Interface D-Type Latches with
TRI-STATE Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS845 8-Bit Bus Interface D-Type Latches with TRI-STATE Outputs. . . . . . . . . . . . . . . . . .
DM54/74AS846 8-Bit Inverting Bus Interface D-Type Latches
with TRI-STATE Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS873 Dual TRI-STATE 4-BitTransparent 0 Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
DM54/74AS874 Dual TRI-STATE 4-Bit Positive-Edged-Triggered
o Flip-Flops ..................................................................
DM54/74AS876 Dual4-Bit Inverting Positive·Edge-Triggered D Flip-Flops: . . . . . . . . . . . . . . . . . . . .
DM54/74AS878 Dual4-Bit Positive-Edge-Triggered 0 Flip-Flops with Synchronous Clear. . . . . . . . .
DM54/74AS879 Dual 4-Bit Inverting Positive-Edge-Triggered
D Flip-Flops with Synchronous Preset . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .
DM54/74AS880 Dual4-Bit Inverting Transparent D Latches ... ; . ; ...... ; . . . . . . . . . . . . . . . . . . .
DM54/74AS881 B 4-Bit Arithmetic Logic Unit/Function Generator ...... ; ................. : .
DM54/74AS1000A Quad 2·lnput NAND Drivers ............... , . . . . . . . . . . . . . . . . . . . . . . .. .
DM54/74AS1004A Hex Inverting Drivers ......... ". . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS1008A Quad 2-lnput AND Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS1032A Quad2-lnputORDrivers ...........................................
DM54/74AS1034A Hex Non-Inverting Drivers. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS1036A Quad 2-lnput NOR Drivers. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS2620 Octal TRI-STATE Inverting Bus Transceivers/MOS Drivers ...................
DM54/74AS2623 Octal TRI-STATE Bus Transceivers/MOS Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74AS2640 Octal TRI·STATE Inverting Bus Transceivers/MOS Drivers ..... . . . . . . . . . . . . . .
DM54/74AS2643 Octal TRI-STATE True and Inverting Bus Transceivers/MOS Drivers . . . . . . . . . . . .
DM54/74AS2645 Octal TRI-STATE Bus Transceivers/MOS Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . .

3·4

3-218
3-218
3-222
3-222
3-227
3-227
3-232
3-236
3-240
3-244
3-248
3-252
3-256
3-267
3-269
3-271
3-273
3-275
3-277
3-279
3-279
3-282
3-282
3-282

~National

a

Semiconductor

DM54ASOO/DM74ASOO Quad 2-lnput NAND Gates
General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which pe~forms the logic NAND function.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS
DM74AS
Storage Temperature Range

Features
•
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.

•

Functionally and Pin For Pin Compatible with Schottky,
Low Power Schottky, and Advanced Low Power
Schottky TTL Counterpart.

•

Improved AC Performance Over Schottky, Low Power
Schottky, and Advanced Low Power Schottky
Counterpart.

Dual-In-Line Package
vee

48

4A

4Y

38

3A

3Y

8

Inputs

1A

18

1Y

2A

28

2Y

GND

74ASOO (J,N)

3-5

Output

A

B

Y

L
L
H
H

L
H
L
H

H
H
H
L

H = High Logic Level
L = Low Logic Level

TLlLl6105·1

54ASOO (J)

7V
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Connection Diagram

(Note 1)

8~
t:!:

Recommended Operating Conditions
DM54/74ASOO

~

Parameter

8

Supply Voltage, VCC

c

~

LO

~
C

High Level input Voltage, VIH

Min

Nom

Max

4.5

5

5.5

Unit
V
V

2

Low Level Input Voltage, VIL

0.8

V

High Level Output Current, 10H

-2

mA

Low Level Output Current, 10L

20

. mA

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25°C.
Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.5V, II = -18 mA

VOH

High Level Output
Voltage

10H = -2mA
VCC = 4.5V to 5.5V

VOL

Low Level Output
Voltage

VCC = 4.5V, 10L = 20mA

II

Max High Input Current

IIH

Symbol

Min

Typ

Max

Unit

-1.2

V
V

VCC-2

0.5

V

VCC = 5.5V, VIH = 7V

0.1

mA

High Level Input Current

Vec = 5.5V, VIH = 2.7V

20

!LA

IlL

Low Level Input Current

VCC = 5.5V, VIL = O.4V

-0.5

mA

10

Output Drive Current

VCC = 5.5V

-112

mA

2.2

3.2

mA

10.8

17.4

mA

ICC

Supply Current

0.35

-30

Vo = 2.25V

VCC = 5.5V

I

Outputs High
Outputs Low

Switching Characteristics over recommended operating free air temperatur~ range (Note 1).
All typical values are measured at Vee= 5V, TA = 25°C.
DM54ASOO
Parameter

Conditions

TpLH, Propagation
delay time. Low to
high level output

VCC = 4.5 to 5.5V
RL = 500 fl,
CL = 50 pF.

TPHL, Propagation
delay time. High to
low level output

1

5

1

4.5

ns

1

5

1

4

ns

3-6

Typ

Max

Unit

Min

Note 1: See Section 1 for test waveforms and output load ..

Typ

DM74ASOO
Max

Min

c

s:

~National

(J1

:;

D Semiconductor

en
o

-s:
N

C

~

DM54AS02/DM74AS02 Quad 2-lnput NOR Gates

:z:-

General Description

Absolute Maximum Ratings (Note 1)

This device contains four independent gates each of
which performs the logic NOR function.

Supply Voltage
Input Voltage
Operating Free Air.Temperature Range
DM54AS
DM74AS
Storage Temperature Range

Features
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
. Temperature and VCC Range.
Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.

•

Functionally and Pin For Pin Compatible with Schottky,
Low Power Schottky, and Advanced Low Power
Schottky TTL Counterpart.
Improved AC Performance Over Schottky, Low Power
Schottky, and Advanced Low Power Schottky
Counterparts.

define the conditions for actual device operation.

Dual·ln·Line Package

Y4

84

A4

Y3

83

11

A3

8

Inputs

A2

82

74~S02

(J,N)

B

Y

L
L
H
H

L
H
L

H
L
L
L

=

GND

TLIF16272·1

54AS02 (J)

Output

A

H

H High Logic Level
L = Low Logic Level

7

Y2

-55°C to 125°C
O°C to 70°C
-65°C to 150°C

which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will

Function Table

Connection Diagram

Vee

7V
7V

Note 1: The "Absolute Maximum Ratings" are those values beyond

•

•

en
~

3-7

~
t!
:e

c

~:e
c

Recommended Operating Conditions
DM54/74AS02
Parameter
Supply Voltage, VCC

Min

Nom

Max

4.5

5

5.5

V
V

2

High Level Input Voltage, VIH

Unit

Low Level Input Voltage, VIL

0.8

V

High Level Output Current, 10H

-2

mA

Low Level Output Current, 10L

20

mA

Max

Unit

-1.2

V

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25°C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC

VOH

High Level Output
Voltage

10H = -2mA .
VPC = 4.5V to 5.5V

VOL

Low Level Output
Voltage

VCC

=

4.5V, 10L

=

20mA

II

Max High Input Current

VCC

=

5.5V, VIH

=

IIH

High Level Input Current

VCC

=

5.5V, VIH

IlL

l!~w

VCC

=

5.5V, VIL

10

Output Drive Current

VCC

=

5.5V

Vo

ICC

Supply Current

VCC

=

5.5V

Outputs High
Outputs Low

Level Input Current

=

4.5V, II

Min

=

Typ

-18 rnA

V

VCC-2

0.5

V

7V

0.1

mA

=

2.7V

20

p.A

=

0.4V

....:.0.5

mA

-112

mA

3.7

5.9

mA

12.5

20.1

mA

0.35

=

-30

2.25V

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V, TA = 25°C.
DM54AS02
Parameter

Conditions

TPLH, Propagation
delay time. Low to
high level output

VCC = 4.5 to 5.5V
RL = 500 n,
CL = 50 pF.

TPHL. Propagation
delay time. High to
low level output

Min

DM74AS02
Min

1

5

1

4.5

ns

1

5

1

4.5

ns

3-8

Typ

Unit

Max

Note 1: See Section 1 for test waveforms and output load.

Typ

Max

,
Semiconductor

~National

a

DM54AS04/DM74AS04 Hex Inverters
General Description

At;lsolute Maximum Ratings

This device contains six independent gates each of
which performs the logic INVERT function.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS
DM74AS
Storage Temperature Range

Features

(Note 1)
7V
7V

-55°C to 125°C
DoC to 70°C
-65°C to 150°C

•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.

•

Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.

not be operated at these limits. The parametric' values defined in the

•

Functionally and Pin For Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.

define the conditions for actual device operation.

•

Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will

Function Table

Connection Diagram
Dual·ln-Line Package
vee

-1~4

A&

Y&

13 .

A5

1
A1

2

3

B

L-£>o-

rt>o-

1>0-

Y1· A2

Y4

9

10

L-£>o-

l{>o-

rt>o-

A4

Y5

11

12

4
Y2

5
A3

.&

Y3

Output

A
L

Y
H

H

L

H = High Logic Level
L = Low Logic Level

17
GND

TLlF/6273·1

54AS04 (J)

Input

74AS04 (J,N)

3-9

~
~

:E

c

i

Recommended Operating Conditions
DM54AS04
Parameter
Supply Voltage, VCC

,

High Level Input Voltage, VIH

DM74AS04

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

2

V
V

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Current, 10H

-2

-2

mA

Low Level Output Current, 10L

20

20

mA

Max

Unit

-1.2

V

:E

c

Unit

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee

=5V, TA =25°C.

Symbol

Parameter

Conditions

Min

VIK

Input Clamp Voltage

VCC = 4.5V, II

VOH

High Level Output
Voltage

10H = -2mA,
Vec = 4.5V to 5.5V

VOL

Low Level Output
Voltage

Vec = 4.5V
10L = 20mA

II

Max High Input Current

Vce = 5.5V, VIH

IIH

High Level Input Current

VCC = 5.5V, VIH = 2.7V

IlL

Low Level Input Current

Vec

=

5.5V, VIL

10

Output Drive Current

Vce

=

5.5V

Vo

ICC

Supply Current

Vee

=

5.5V

Outputs High
Outputs Low

=

Typ

-18 mA

V

VCC-2

0.35

=

=

0.5

V

0.1

mA

20

JlA

-0.5

mA

-112

mA

3

4.8

mA

14

26.3

mA

7V

O.4V

=

-30

2.25V

Switching Characteristics over recommended operating free air temperature range (Note 1)..
All typical values are measured at Vee = 5V, TA = 25°e.
DM74AS04

DM54AS04
Parameter

Conditions

TpLH, Propagation
delay time. Low to
high level output

Vee = 4.5 to 5.5V
RL = 500 n,
eL = 50 pF.

TpHL, Propagation
delay time. High to
. low level output

Typ

Typ

Unit

Max

Min

1

6

1

5

ns

1

4.5

1

4

ns

Min

Note 1: See Section 1 for test waveforms and output load.

3·10

Max

~National

D Semiconductor
DM54AS08/DM74AS08 Quad 2-lnput AND Gates
General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic AND function.
'

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS
DM74AS
Storage Temperature Range

Features
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
• Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
• Functionally and Pin For Pin Compatible with Schottky,
Low Power Schottky, and Advanced Low Power
Schottky TIL Counterpart.
• Improved AC Performance Over Schottky, Low Power
Schottky, ,and Advanced Low Power Schottky
Counterparts.

Dual-In-Line Package
V=AB
Inputs

=

B1

Y1

A2

B2

Y2
TLlL/6106·1

54ASOB (J)

74AS08 (J,N)

3-11

Output

A

B

V

L
L
H
H

L
H
L
H

L
L
L
H

H = High Logic Level
L Low Logic Level

3

A1

7V
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Connection Diagram

(Note 1)

!
i!

Recommended Operating Conditions
DM54/74AS08

~
Q

Parameter

co

Supply Voltage, VCC

-

;
~
Q

Min

Nom

Max

4.5

5

5.5

2

High Level Input Voltage, VIH

Unit
V
V

,

Low Level Input Voltage, VIL

0.8

V

High Level Output Current, IOH

-2 .

mA

Low Level Output Current, IOL

20

mA

Max

Unit

-1.2

V

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25 D C.
Symbol
VIK

Parameter

Conditions

Min

Input Clamp Voltage

VCC = 4.5V, II = -18 mA

VOH

High Level Output
. Voltage

VOL

Low Level Output
Voltage

VCC = 4.5V, IOL = 20mA

II

Max High Input Current

IIH

IOH = -2mA
VCC=4.5Vt05.5V

Typ

V

VCC-2

0.5

V

VCC = 5.5V, VIH = 7V

0.1

mA

High Level Input Current

VCC = 5.5V, VIH= 2.7V

20

/LA

IlL

Low Level Input Current

VCC = 5.5V, VIL = 0.4V

-0.5

mA

10

Output Drive Current

VCC = 5.5V

Vo = 2.25V

-112

rnA

ICC

Supply Current

VCC = 5.5V

Outputs High

5.8

9.3

mA

Outputs Low

14.9

24

mA

0.35

-30

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V, TA = 25 D C.
DM74AS08

DM54AS08
Parameter

Conditions

TpLH, Propagation
delay time. Low to
high level output

VCC = 4.5 to 5.5V
RL = 500 \1,
CL = 50 pF.

TpHL, Propagation
delay time. High to
low level output

Min

1

6.5

1

5.5

ns

1

6.5

1

5.5

ns

Nota 1: See Section 1 for test waveforms and output load.

3·12

Typ

Typ

Unit.

Max

Min

Max

c

~National

a

is:

UI

~

Semiconductor

......
o

-c

DM54AS10/DM74AS10 Triple 3-lnput NAND Gates

is:

General Description

Absolute Maximum Ratings

This device contains three independent gates each of
which performs the logic NAND function.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS
DM74AS
Storage Temperature Range

Features
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.

•

Advanced Oxide-Isolated. Ion-Implanted Schottky TTL
Process.
'

•

Functionally and Pin For Pin Compatible with Schottky.
Low Power Schottky. and Advanced Low Power
Schottky TTL Counterpart.

•

Improved AC Performance Over Schottky. Low Power
Schottky. and Advanced Low Power Schottky
Counterparts.

7V
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Nole 1: The "Absolute Maximum Rallngs" are those values beyond
which Ihe safety of the device can not be guaranteed, The device should
not be operated at these limits, The parametric values defined in t,he
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will

define the conditions for actual device operation,

Function Table

Connection Diagram
Dual-In-Line Package
Vcc

Y1

C1

C3

83

A3

Y=ABC
Output

Inputs

2

A1

81

82

C2

Y2

GND

TLfFf6274-1

54AS10 (J)

A

B

C

Y

X
X

X

L

L

L
H

X

X
X

H

H

H
H
H
L

H = High Logic Level
L = Low Logic Level
X = Either Lo.... or High Logic Level

3
A2

(Note 1)

74AS10 (J,N)

3·13

~
»en

......

o

,..

O'-------~-----------------------------------------------------------------

.~......

:!:

c
o
,..

~

:!:

c

Recommended Operating Conditions
DM54/74AS10
Parameter
Supply Voltage, VCC
High Level Input Voltage, VIH

Min

Nom

Max

4.5

5

5.5

2

Unit
V
V

Low Level Input Voltage, VIL

0.8

V

High Level Output Current, IOH

-2

mA

Low Level Output Current, 10L

20

mA

Max

Unit

-1.2

V

Electrical Characteristics over recom,mended operating frell air temperature range.
All typical values are measured at Vee = 5it, TA = 25°C.
Symbol

Parameter

Conditions

Min

VIK

Input Clamp Voltage

VCC = 4.5V, II = -18 mA

VOH

High Level Output
Voltage

10H = -2mA
VCC = 4.5V to 5.5V

VOL

Low Level Output
Voltage

VCC = 4.5V, IOL = 20mA

II

Max High Input

IIH

Typ

V

VCC-2

0.5

V

VCC = 5.5V, VIH = 7V

0.1

mA

High Level Input Current

VCC = 5.5V, VIH = 2.7V

20

!J.A

IlL

Low Level Input Current

VCC = 5.5V, VIL = 0.4V

-0.5

mA

10

Output Drive Current

VCC = 5.5V

Vo = 2.25V

-112

mA

ICC

Supply Current

VCC = 5.5V

Outputs High

1.5

2.4

mA

Outputs Low

8.1

13

mA

C~rrent

0.35

-30

Switching Characteristics over recommended operating iree air temperature range (Note 1).
All typical values are measured at Vee = 5V, TA = 25°C.
DM54AS10
Parameter

Conditions

TpLH, Propagation
delay time. Low to
high level output

VCC = 4.5 to 5.5V
RL = 500 n,
CL = 50 pF.

TpHL, Propagation
delay time. High to
low level output

Min

Typ

DM74AS10

Typ

Max

Unit

Max

Min

1

5

1

4.5

ns

1

5

1

4.5

ns

!

Note 1: See Section 1 for tast waveforms and output load.

3-14

1

c

~National

s:

DM54AS11/DM74AS11 Triple 3-lnput AND Gates

-s:

~..........

D Semiconductor

C

General Description

Absolute Maximum Ratings

This device contains three independent gates each of
which performs the logic AND function.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS
DM74AS
Storage Temperature Range

Features
•
•
•
)

•

•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
Functionally and Pin For Pin Compatible with Schottky,
Low Power Schottky, and Advanced Low Power
Schottky TTL Counterpart.

7V
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Nota 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Improved AC Performance Over Schottky, Low Power
Schottky, and Advanced Low Power Schottky
Counterparts.

Function Table

Connection Diagram
Dual·ln·Line Package
VCC

C3

Y1

C1

B3

A3

Y=ABC

Inputs

2
A1

B1

3
A2

Output

A

B

C

Y

X
X
L

X
X

L
X
X

L
L
L

H

H

H

H

L

H = High Logic Level
L = Low Logic Level
X = Either Low or High Logic Level

4
B2
TL/F/6275·1

54AS11 (J)

~

(Note 1)

74AS11 (J,N)

3-15

1;;
.....
.....

~ ~---------------------------------------------------------------------------------------,
~

~.

~

Recommended Operating Conditions
DM54/74AS11

:E

Parameter

~

Supply Voltage. VCC

c

Min

Nom

Max

4.5

5

5.S

Unit

V

~

~
oq.

U)

:E

c

2

High Level Input Voltage. V,H

V

Low Level Input Voltage. V,L

0.8

V

High Level Output Current. 10H

-2

mA

Low Level Output Curr!lnt. 10L

20

mA

Max

Unit

-1.2

V

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 2SoC.
Min

Symbol

Parameter

Conditions

V,K

Input Clamp Voltage

VCC = 4.5V. " = -18 mA

VOH

High Level Output
Voltage

10H = -2mA
VCC=4.SV to 5.5V

VOL

Low Level Output
Voltage

VCC = 4.SV, 10L = 20mA

II

Max High Input Current

IIH

Typ

V

VCC-2

0.5

V

VCC = 5.SV. V,H = 7V

0.1

mA

High Level Input Current

VCC = 5.5V. V,H = 2.7V

20

/LA

IlL

Low Level Input Current

VCC = 5.5V. V,L = 0.4V

-0.5

mA

10

Output Drive Current

VCC = 5.5V

Vo = 2.25V

-112

mA

ICC

Supply Current

VCC = 5.5V

Outputs High

4.3

7

mA

Outputs Low

11.2

18

mA

0.35

-30

SWitching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = SV, TA = 25°C.
DM74AS11

DM54AS11
Parameter

Conditions

TpLH. Propagation
delay time. Low to
high level output

VCC = 4.5 to 5.5V
RL = 500 n.
CL = 50 pF.

TpHL. Propagation
delay time. High to
low level output

Typ

Typ

Unit

Max

Min

1

6.5

1

6

ns

1

6.5

1

5.5

ns

Min

Note 1: See Section 1 for test waveforms and output load.

3·16

Max

~National

a

Semiconductor

DM54AS20/DM74AS20 Dual4-lnput NAND Gates
General Description

Absolute Maximum Ratings (Note 1)

This device contains two independent gates each of
which performs the logic NAND function.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS
DM74AS
Storage Temperature Range

Features
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
• Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
\
• Functionally and Pin For Pin Compatible with Schottky,
Low Power Schottky, and Advanced Low Power
Schottky TTL Counterpart.
• Improved AC Performance Over Schottky, Low Power
Schottky, and Advanced Low Power Schottky
Counterparts.

7V
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safely of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will

define the conditions for actual device operation.

Function Table

Connection Diagram
Dual-In-Line Package
VCC
114

02
13

C2
12

Ne

111

B2
10

A2

19

Y=ABCD

Y2
8

~
1
A1

2
B1

13
NC

4
C1

5
01

~17
GNO

TLlF/6276·1

54AS20 (J)

D

y

X

L

L

X
X

X
X
X

H

H

H
H
H
H
L

B

C

X
X
X

X
X
L

L
H

X
H

H = High Logic Level
L = Low Logic Level
X = Either Low or High Logic Level

I~

Y1

Output

Inputs
A

74AS20 (J,N)

3-17

~
~

Recommended Operating Conditions '
DM54/74AS20

:i

Parameter

~

-

Min

Nom

Max

Supply Vollage, VCC

4.S

S

S.S

High Level Input Voltage, VIH

.2

c

~

:i

c

Unit

V
V

Low Level Input Voltage, VIL

0.8

V

High Level Output Current; 10H

-2

mA

Low Level Output Current, 10L

20

m,A.

Max

Unit

-1.2

V

Electrical Characteristics over recommended operating free air temperature range.
All typi.cal values are measured at Vee = SV, TA = 2S D C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.SV, II = -18 mA

VOH

High Level Output
Voltage

10H = -2mA
VCC = 4.SV to 5.SV

VOL

Low Level Output
Voltage

VCC = 4.SV, IOL = 20mA

II

Max High Input Current

IIH

Min

Typ

V

VCC-2

0.5

V

VCC = S.5V, VIH = 7V

0.1

mA

High Level Input Current

VCC = S.SV, VIH = 2.7V

20

/lA

IlL

Low Level Input Current

VCC = ·S.SV, VIL = O.4V

-0.5

mA

10

Output Drive Current

VCC = S.SV

Vo = 2.2SV

-112

mA

ICC

Supply Current

VCC

=:'

Outputs High

1.1

1.6

mA

Outputs Low

6

8.7

mA

0.35

..

S.SV

-30

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V, TA=25 D C.
DM54AS20
Parameter

Conditions

TPLH, Propagation
delay time. Low to
high level output

VCC = 4.S to S.SV
RL = SOO fI,
CL = SO pF.

TpHL, Propagation
delay time. High to
low level output

Min

DM74AS20
Typ

Max

Unit

Max

Min

1

S.S

1

S

ns

1

5

1

4.S

ns

Note 1: See Section 1 !or test waveforms and output load.

3-18

Typ

.---------------------------------------------------------------,0

s:

~National

D Semiconductor

~.....

DM54AS21/DM74AS21 Dual4-lnput AND Gates

o

-s:
N

~

General Description

1;;

This device contains two independent 4-input gates, each of •
.which performs the logic AND function.

Improved AC Performance Over Schottky, Low Power
Schottky, and Advanced Low Power Schottky
Counterparts.
.

Absolute Maximum Ratings

Features
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.

•

Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.

•

Functionally and Pin For Pin Compatible with Schottky,
Low Power Schottky, and Advanced Low Power
Schottky TTL Counterpart.

Connectio!1 Diagram

Supply Voltage
Input Voltage
Operating Free Air Temperature R,ange
DM54AS
DM74AS
Storage Temperature Range

1'4

02
13

C2
12

7V
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Note 1: The "Absolute MaXimum Ratings" are those values beyond
which the safely of the deVice can not be guaranteed. The deVice should
not be operated al Ihese limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed al the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define ihe conditions for actual d~vlce operation.

Function Table

NC

1"

B2
10

A2

III

Y2

19

8

~

Inputs
A

B

C

D

H

H
X
L

H
X
X

X
X

L

H
X
X
X

X

L

L

1
Al

2
Bl

4 Is

13
NC

-Cl

01

~

G!~

), 6

-TL/F/6277·1

54AS21 (J)

.....

(Note 1)

Dual-In-Line Package
vCC

N

X
X
X

H = High Logic Level

L:::: Low Logic Level
X = Either Low or High logic Level

74AS21 (J,N)

3-19

Output
Y

H
L
L
L
L

.- r-----------------------------------------------------------------------------------~ Recommended Operating Conditions
~

::E

c
.-

~

::E

c

.

DM54/74AS21

Parameter
Supply Voltage, VCC
High Level Input Voltage, VIH

Min

Nom

Mall

4.5

5

5.5

Unit
V
V

2

Low Level Input Voltage, VIL

0.8

V

High Level Output Current, 10H

-2

mA

Low Level Output Current, 10L

20

mA

Max

Unit

-1.2

V

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vce = 5V, TA = 25°C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC

VOH

High Level Output
Voltage

10H = -2mA
VCC = 4.5V to 5.5V

VOL

Low Level Output
Voltage

Vee

=

4.5V, 10L

=

20mA

II

Max High Input Current

VCC

=

5.5V, VIH

=

IIH

High Level Input Current

VCC

=

5.5V, VIH

=

IlL

Low Level Input Current

Vec

=

5.5V, VIL '= O.4V

10

Output Drive Current

Vce

=

5.5V

Vo

ICC

Supply Current

Vce

=

5.5V

Outputs High
Outputs Low

=

4.5V, II

Min

=

Typ

-18 mA

V

VCC-2

0.5

V

7V

0.1

mA

2.7V

20

/lA

-0.5

mA

-112

mA

2.9

4.6

mA

7.4

12

mA

0.35

=

-30

2.25V

Switching Characteristics over r~commended operating free air temperature range (Note 1).
All typical values are measured at Vee

=5V, TA =25°C.

DM54AS21
Parameter

Conditions

TpLH, Propagation
delay time. Low to
high level output

VCC = 4.5 to 5.5V
RL = 500 n,
CL = 50 pF.

TpHL, Propagation
delay time. High to
low level output,

Min

DM74AS21
Uriit

Max

Min

1

6.5

1

6

ns

1

6.5

1

6

ns

Note 1: See Section 1 for test waveforms and output load.

3·20

Typ

Typ

Max

r-------------------------------------------------------------~c

~National

s:

DM54AS27/DM74AS27 Triple 3-lnput NOR Gates

-s:

~~

D Semiconductor

c

Absolute Maximum Ratings (Note 1)

General Description

This device contains three independent 3-input gates, each Supply Voltage
of which performs the logic NOR function.
Input Voltage
Operating Free Air Temperature Range
DM54AS
DM74AS
Storage Temperature Range
• Switching Specifications at 50 pF.

Features

•

Switching Specifications Guaranteed Over Full
Temperature and VCC Range.

•

Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process;

•

Functionally and Pin For Pin Compatible with Schottky,
Low Power Schottky, and Advanced Low Power
Schottky TTL Counterpart.

•

Improved AC Performance Over Schottky, Low Power
Schottky. and Advanced Low Power Schottky
Counterparts.

Connection Diagram

7V
7V
-55 a C to 125 a C
to 70 c C
-65 a C to 150 a C

oac

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Dual-ln·Line Package
VCC

C1

114

V1
13.

2
A1

B1

C3
12

3
A2

11

4
82

B3

10

5
C2

A3

19

Y=A+B+C

V3

8

Inputs

~
1& 17
V2

B

C

Y

L
H
X
X

L
X
H
X

L
X
X
H

H
L
L
L

H = High Logic Level

=

L Low Logic Level
X = Either Low or High Logic Level

GND

TL/F/6278-1

54AS27 (J)

Output

A

74AS27 (J,N)

3·21

~
......

~
~

Recommended Operating Conditions
DM54/74AS27

:i

Parameter

~

Supply Voltage, VCC

c

~

:i

c

High Level Input Voltage, VIH

Min

Nom

Max

4.5

5

5.5

Unit
V
V

2

Low Level Input Voltage, VII:'

0.8

V

High Level Output Current, 10H

-2

mA

Low Level Output Current, 10L

20

mA

Max

Unit

-1.2

V

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee=5V, TA = 25°C.
Min

Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.5V, II = -18 mA

VOH

High Level Output
Voltage

10H = -2mA
VCC = 4.5V to 5.5V

VOL

Low Level Outpu't
Voltage

VCC = 4.5V, 10L = 20mA

II

Max High Input Current

VCC = 5.5V, VIH = 7V

IIH

High Level Input Current

VCC = 5.5V, VIH = 2.7V

IlL

Low Level Input Current

VCC = 5.5V, VIL = O.4V

10

Output Drive Current

VCC = 5.5V

Vo = 2.25V

Supply Current

VCC

Outp!.!ts High
Outputs Low

,ICC

7'"

Typ

V

VCC- 2

5.5V

0.5

V

0.1

mA

20

/lA

-0.5

mA

-112

mA

4

6.4

mA

10.6

17.1

mA

0.35

\

-30

SWitching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V, TA = 25°C.
DM54AS27
Parameter

Conditions

TpLH, Propagation
delay time. Low to
high level output

VCC = 4.5 to 5.5V
RL = 500O,
CL = 50 pF.

TpHL, Propagation
delay time. High to
low level output

Min

Typ

1

1

?

Note 1: See Section 1 lor test waveforms and output load.

3·22

DM74AS27
Typ

Max

Unit

Max

Min

6.5

1

5.5

ns

5

1

4.5

ns

~National

a

Semiconductor

DM54AS30/DM74A~30

8 Input NAND Gate'

General Description

Absolute Maximum Ratings

This device contains a single gate which performs the
logic NAND function.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS
DM74AS
Storage Temperature Range

Features
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.

•

Advanced O.xide-Isolated, lon-Implanted Schottky TTL
Process.

7V
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

•

Functionally and Pin For Pin Compatible with Schottky,
Low Power Schottky, and Advanced Low Power
Schottky TTL Counterpart.

•

Improved AC Performance Over Schottky, Low Power
Schottky, and Advanced Low Power Schottky
Counterparts.

Connection Diagram·

not be operated at these limits. The parametric values defined In the

"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will

define the conditions for actual device operation.

Function Table

Dual·ln·Line Package
VCC

114

HC

H

HC

G
12

1 13

11

l10

HC

y
8

19

Y = ABCDEFGH'

)0-

1
A

2

B

4

3
C

o

~
5

E

16

F

Inputs

Output

A thru H

Y

All inputs H

L

One or More
Input L

H

H = High Logic Level
L = Low Logic Level

17
GHD

TLlF/6279·1

54AS30 (J)

(Note 1)

74AS30 (J,N)

3-23

~
~

:E
o

~

~:E
o

Recommended Operating Conditions
DM54(74AS30
Parameter

Supply Voltage. VCC

Min

Nom

Max

4.5

5

5.5

V
V

2

High Level Input Voltage. VIH

Unit

Low Level Input Voltage. VIL

0.8

V

High Level Output Current. 10H

-2

mA

Low Level Output Current. 10L

20

mA

Max

Unit

-1.2

V

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V. TA = 25"C.
Symbol'

Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.5V. II = -18 mA

VOH

High Level Output
Voltage

10H = -2mA
VCC 4.5V to 5.5V

VOL

Low Level Output
Volta!;le

VCC = 4.5V. 10L = 20mA

II

Max High Input Current

VCC = 5.5V. VIH = 7V

Min

Typ

V

VCC-2

=

0.35

0.5

V

0.1

mA

"

IIH

High Level Input Current

VCC = 5.5V. VIH = 2.7V

20

/LA

IlL

Low Level Input Current

VCC = 5.5V. VIL = O.4V

-1

mA

10

Output Drive Current

VCC = 5.5V

Vo = 2.25V

-112

mA

ICC

Supply Current

VCC = 5.5V

Outputs High

1

1.5

mA

Outputs Low

3.4

4.9

mA

-30

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee

=5V. TA =25"C.
DM54AS30

Parameter

Conditions

TpLH. Propagation
delay time. Low to
high level output

VCC = 4.5 to 5.5V
RL = 500 O.
CL = 50pF.

TpHL. Propagation
delay time. High to
low level output

Min

DM74AS30
Typ

Max

Unit

Max

Min

1

5.5

1

5

ns

1

5

1

4.5

ns

Note 1: See Section 1 for test waveforms and output load.

3·24

Typ

-

~National

D Semiconductor
DM54AS32/DM74AS32 Quad ~-Input OR Gates
General Description

Absolute Maximum Ratings

This device contains four independent gates each of
'which performs the logic OR function.

Features
•
•
•
•

•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
Advanced Oxide-Isolated. Ion-Implanted Schottky TTL
Process.
Functionally and Pin For Pin Compatible with Schottky.
Low PoV:'er Schottky. and Advanced Low Power
Schottky TTL Counterpart.
Improved AC Performance Over Schottky. Low Power
Schottky. and Advanced Low Power Schottky
Counterparts.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS
DM74AS
Storage Temperature Range

"Electrical Characteristics" table are not guaranteed at the absolute .
define the conditions for actual device operation.

Y=A+B
Inputs

A2

B2

V2

GND

TLlF/6280·1

54AS32 (J)

74AS32 (J,N)

3·25

Y

B

L
L

L

L

H

H
H

H

H
H
H

=

VI

Output

A

L

H High Logic Level
L = Low Logic Level

7
Bl

-55°C to 125°C
O°C to 70°C
-65°C to 150°C

maximum ratings. The "Recommended Operating Conditions" table will

Dual·ln·Line Package

AI

7V
7V

Nole 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the:

Function Table

Connection Diagram

(Note 1)

~
t!
:E
c

~

:E

c

Recommended Operating Conditions·
DM54/74AS32
Parameter

Supply Voltage, VCC

Min

Nom

Max

4.5

5

5.5

2

High Level Input Voltage, VIH

Unit

V
V

Low Level Input Voltage, VIL

0.8

V

High Level Output Current, 10H

-2

mA

Low Level Output Current, 10L

20

mA

Max

Un~t

-1.2

V

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vcc = 5V,TA = 25°C.
Symbol

Min

Parameter

Conditions

\,11K

Input Clamp Voltage

VCC = 4.5V, II

VOH

High Level Output
Voltage

VCC = 4.5V to ~.5V

VOL

Low Level Output
Voltage

VCC

4.5V, 10L

=

20mA

II

Max High Input Current

VCC = 5.5V, VIH

=

IIH

High Level Input Current

VCC

=

IlL

Low Level Input Current

VCC = 5.5V, VIL = 0.4V

10

Output Drive Current

VCC

=

5.5V

Vo = 2.25V

ICC

Supply Current

VCC

=

5.5V

Outputs High
Outputs Low

=

=

=

5.5V, VIH

Typ

-18 mA

V

VCC-2

0.5

V

7V

0.1

mA

2.7V

20

p.A

-0.5

mA

-112

mA

7.3

12

mA

16.5

26.6

mA

0.35

-30

Switching Characteristics over recommended operating free air temperature 'range (Note 1).'
All typical values are measured at Vcc = 5V, TA = 25°C.
DM54AS32
Parameter

Conditions

TPLH, Propagation
delay time. Low to
high level output

VCC = 4.5 to 5.5V
RL = 500n,
CL = 50 pF.

Min

Typ

DM74AS32
Typ

Max

Unit

Max

Min

1

7.5

1

5.B

ns

1

6.5

2

5.8

ns

,
TpHL, Propagation
delay time. High to
low level output
Note 1: See Section 1 for test waveforms and output load.

3·26

~--------------------------~----------------------------------'C

s:

~National

a

~

Semiconductor

~
c

DM54AS34/DM74AS34 Hex Non-Inverter

s:
~

General Description

Absolute Maximum Ratings

These devices contain six independent gates, each of
which performs the logic identity function.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS
DM74AS
Storage Temperature Range

Features
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and Vee Range.
•• Advanced Oxide-Isolated. Ion-Implanted Schottky TTL
Process.
--

~

(Note 1)
7V
7V

-55°C to 125°C
ooe to 70°C
:-65°e to 150°C

Nota 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual·ln·Line Package

Vee

-1~4

A6

Y6

13

12

AS

Y5

11

A4

10

-I>-

-I>--

Y4
9

8

Y=A

-{>-

Input

Output

A

y

H
L

H
L
\

1
A1

2
Y1

3
A2

4
Y2

5
A3

6
Y3

17
GND

TL/F/6281-1

54AS34(Jj

74AS34 (J, N)

3·27

Co)

-'="

~

Recommended Operating Conditions
DM54/74AS34

t!

Parameter

c'

Supply Voltage, VCC

::i

~

~

High Level Input Voltage, V,H

Min

Nom

Max

4.5

5

5.5

Unit
V
V

2

Low Level Input Voltage, V,L

0.8

V

High Level Output Current, IOH

-2

rnA

Low Level Output Current, IOL

20

rnA

Max

Unit

-1.2

V

::i

c

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vcc =5V, TA=2SoC.
Symbol

Parameter

Conditions

V,K

Input Clamp Voltage

VCC = 4.5V,I, = -18 rnA

VOH

High Level Output
Voltage

VCC = 4.SV to 5.SV

VOL

Low Level Output
Voltage

VCC = 4:,5V
IOL = 20mA

II

Max High Input Current

IIH

Min

Typ

V

VCC-2

0.35

0.5

V

VCC = 5.5V, V,H = 7V

0.1

rnA

High Level Input Current

VCC .,; 5.5V, V,H = 2.7V

20

/lA

IlL

Low Level Input Current

Vce = 5.5V, V,L

-0.5

rnA

10

Output Drive Current

VCC = 5.5V

Vo = 2.25V

-112

rnA

ICC

Supply Current

Vec = 5.SV

Outputs High

7.4

12

rnA

Outputs Low

21.3

34.6

rnA

0.4V

=

-30

Switching Characteristics over ~ecommended operating free air temperature range (Note 1).
All typical values are measured at Vcc = SV, TA = 2Soc.
DM54/74AS34
Parameter

Conditions

TpLH, Propagation
delay time. Low to
high level output '

VCC = 4.5 to 5.5V
RL = SOD n,
CL = SO pF.

TPHL, Propagation
delay time. High to
low level output

1

6.5

1

S.S

ns

1

7

1

6

ns

3-28

Typ

Max

Unit

Min

, Note 1: See Section 1 for test waveforms and output load.

Typ

DM54/74AS34
Max

Min

~National

D Semiconductor
DM54AS74{DM74AS74 Dual D Positive-EdgeTriggered Flip-Flops with Preset and Clear
General Description
The DM54AS74 is a dual edge-triggered flip-flops. Each
flip-flop has individual D, clock, clear and preset inputs, and
also complementary a and Q outputs.
Information at input D is transferred to the a output on the
positive going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly
related to the transition time of the positive going pulse.
When the clock input is at either the high or low level, the D
input signal has no effect.
Asynchronous preset and clear inputs will set or clear a
output respectively upon the application of low level signal.

•

Functionally and Pin-For-Pin Compatible with Schottky
and LS TTL Counterpart.

•

Improved AC Performance Over S74 at Approximately
Half the Power.

Absolute

Ma~imum

Ratings

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS
DM74AS
Storage Temperature Range

(Note 1)
7V
7V

-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Features
•

Switching-Specifications at 50 pF.

•

Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.

•

Nota 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table arB not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

\

Connection Diagram

Function Table

Dual·ln·Line Package
VCC

ClR2

02

ClK2

PR2

02

02

Inputs

8

7
ClR 1

01

elK 1

PR 1

01

01

GNO

CLR

CLK

0

Q

Q

L'
H
L
H
H
H

H
L
L
H
H
H

X
X
X

X
X
X

r
r

H
L

H
L
H*
H
L
aO

L
H
H*
L
H
00

L

X

L ~ Low State, H ~ High State, X = Don't Care
I = Positive Edge Transition
00 = Previous Condition of 0
* = This condition is nonstable; it will not persist when preset and clear inputs return to their inactive (high) level. The output levels in this condition are
not guaranteed to meet the VOH specification.

TLI F16282·1

54AS74 (J)

Outputs

PR

74AS74 (J,N)

3·29

Recommended Operating Conditions
DM74AS74

DMS4AS74
Parameter

Supply Voltage, VCC
High Level Input Voltage, VIH

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

. Unit

V'
V

2

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Current, 10H

-2

-2

mA

Low Level Output Current, 10L

20

20

mA

105

MHz

Width of Clock Pulse, TW

Pulse Width TW,
Preset & Clear
Data Setup Time, TSU

High

4

Low

5.5

Low

0
4

ns

. 5.5

ns

4

4

ns

High

4.51

4.51

ns

Low

4.51

4.51

ns

21

21

ns

01

01

ns

PRE or CLR Setup Time
"

Data Hold Time, TH
The

90

0

Clock frequency, fCLOCK

(tJ arrow mdLcates the posLtwe edge 01 the Clock

1$

used tor reference ..

Electr.ical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25°C.
Symbol

VIK

Parameter

Conditions .

. Input Clamp Voltage

Min

VCC=4.5V,II= -18mA

VOH

High Level Output
Voltage

VCC = 4.5V to 5.5V
10H= -2mA

VOL

Low Level Output
Voltage

VCC = 4.5V
VIH=Max
10L = 20mA

II

Max High Input Current

VCC = 5.5V
VCC = 5:5V

IIH·

High Level
. Input Current

Typ

Clock, D

Low Level
Input Current

Clock, D

VCC = 5.5V

Output Drive Current

ICC

Supply Current

VCC = 5.5V

-

-1.2

V
V

0.35

0.5

V

VIH = 7V

0.1

mA

VIH = 2.1V

20

p.A

40

p.A

-0.5

mA

-1.8

mA

-112

mA

16

mA

VIL = 0.4V

Preset, Clear
10

Unit

VCC-2

Preset, Clear
IlL

Max

Vo = 2.2.5V

VCC = 5.5V

-30
10.5

3·30

------------------------------------------------------------------'0

:s:
U'I

)witching Characteristics over recommended operating free air temperature range (Note 1).
.11 typical values are measured at Vee = 5V, TA = 25"C.
From

To

Conditions

Min

TPHL
TPLH

Max

Preset
or clear

Clock

TpHL

Oor

Q

Oar

VCC = 4.5V to 5.5V
RL = 500!l
CL = 50 pF

Q

Typ

Max

Unit
MHz

3

8.5

3.3

7.5

ns

3.5

11.5

3.5

10.5

ns

3.5

9

3.5

8

ns

4.5

10.5

4.5

9

ns

Note 1: See Section 1 for test waveforms and output load.

_ogic Diagram

PRESET ----;==!::==rl
CLEAR --t---1r-;::::=:::l~Io-""'T--;:::j
CLOCK--i=~!:::;::r:JIo--r==:::t-.J

3·31-

Min

fJ)

105

90

FMAX
TpLH

Typ

~

DM74AS74

DM54AS74
Parameter

......
.c:a

-:s:o
~
l>

!a
.c:a

co

~ ~ National'
~
c

:E

co

~

:E

c

_

PRELIMINARY

Semiconductor

DM54AS86/DM74AS86 Quad 2-lnput Exclusive-OR Gates
General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic exclusive-OR function.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS.
.
DM74AS
Storage Temperature Range

Features
• Switching Specifications at 50 pF.
• Switching Specifications Guaranteed Over Full
Ter:nperature and VCC Range.
• Advanced Oxide-Isolated. Ion-Implanted Schottky TTL
Process.
• Functionally and Pin For Pin Compatible with Schottky.
Low Power Schottky. and Advanced Low Power
Schottky TTL Counterpart.
• Improved AC Performance Over Schottky. Low Power
Schottky. and Advanced Low Power Schottky
Counterparts.

(Note 1)
7V
7V

-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Not. 1: The '"Absolute Maximum Ratings'" are Ihose values beyond
which the safety of the device can nol be guaranteed. The device should
nol be operated al these IImils. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The '"Recommended Operating Conditions'" table will
define the conditions for actual device operation.

Function Table

Connection Diagram

Dual·ln·Llne Package
vee

84

A4

Y4

Inputs

A

B

L
L
H
H

L
H
L
H

Outputs
L
H
H
L

H = High Logic Level
L = Low Logic Level

A1

81

Y1

A2

82

Y2

TLlF/6283-1

54AS86(J)

74ASa6 (J, N)

This document contains Information on a product under development. NSC reserves the right to change or discontinue this product without notice.

3-32

Recommended Operating Conditions
DM54AS86/DM74AS86
Parameter
Supply Voltage, VCC
High Level Input Voltage, VIH

Min

Nom

Max

4.S

S

S.S

2

Unit
V
V

Low Level Input Voltage, VIL

O.B

V

High Level Output Current, 10H

-2

mA

Low Level Output Current, 10L

20

mA

Max

Un;t

-1.2

V

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = SV, TA = 2Soc.
Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.SV, II

VOH

High Level Output
Voltage

VCC = 4.SV to S.SV
10H= -2mA

VOL

Low Level Output
Voltage

VCC=4.5V,IOL=20 niA

II

Max High Input Current

VCC

=

S.SV, VIH

=

IIH

High Level Input Current

VCC

=

S.SV, VIH

IlL

Low Level Input Current

VCC

=

S.SV, VIL

10

Output Drive Current

VCC

=

S.5V

Vo

ICC

Supply Current

VCC

=

S.SV

Outputs High

mA

Outputs Low

mA

Symbol

Min

=

Typ

-1B mA

V

VCC-2

0.3S

O.S

V

7V

0.1

mA

=

2.7V

20

Il A

=

0.4V

-O.S

mA

-112

mA

=

;!.2SV

-30

Switching Characteristics over recommended operating free air temperature range (Note 1).
AlI'typical values are measuied at Vee = SV, TA =2SoC.
DM54AS86
Parameter

Conditions

TpLH, Propagation
delay time. Low to
high level output

VCC = 4.S to S.SV
RL = SOO fI,
CL = SO pF.

Min

Typ

DM74AS86
Max

Min

Typ

Max

Unit

ns

TpHL, Propagation.
delay time. High to
low level output

ns

Note 1: See SeChon 1 for test waveforms and output load.

3·33

~.---------------------------------------------~-------------------------,
0)

'0

-f'--____p-f.:.3_ _ _ _ _--1-+'------,

CLOCK 1 9
RIGHT SHIFT -t"-1.-'/
CLOCK 2 8

LEFT SHIFT - -.......,

"

• a"

10

Dc
OUTPUTS

3-34

TLIF16716·2

Function Table
Inputs
Clocks
2(L)
1 (R)

MOde
Control
H
H
H
L
L
L

H

I

I
L
X
X
L
L
L
H
H

I

I
I

,
I

Outputs

Serial

X
X
X
H

A

X
X
X
X
H
L
X
X
X
X
X

I
I
L
L
H
L
H

tShlfting left requires external connection of

Parallel
B
C
X
b

X

0
X

X

a
QBt

Qe t

c
Qc t

X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X

d
d
X
X
X
X
X
X
X
X

aS to A, Oc to at aD to C. Serial data is entered at

QA

QB

Qc

QD

QAO
a
QBn
QAO

QBO

QeD
c
QDn
QeD
QBn
QBn
QeD
QeD
QeD
QeD
QeD

QDO

H
L

QAO
QAO
QAO
QAO
QAO

b

Qen
QBO
QAn
QAn
QBO
QBO
QBO
QBO
QBO

d
d

QDO
Qen
Qen
QDO
QDO
QDO
QDO
QDO:

input D.

H = high level (steady·slate). L = low level (steady-statel, X = don't care (any input, including transitions).

J =transition

J

from high-Io-Iow Jevel, 1 = transition from low·to·hlgh level.

a, b, c, d = the level of steadY'state input at inputs A, 8, C or 0, respectively.
QAO. aBO. aeo. aoo
OAn, OSn. 0en. aO n

=the level of CA, Oa. OCt or 00. respectively, before the mdicated steady-state input conditions were established.
=the level of QA. 0a. OCI or aO, respectively. before the most recent I transition 01 the clock.

Recommended Operating Conditions
Symbol

DM54AS95

Parameter

Vce

Supply Voltage

VIH

High level Input Voltage

VIL

low level Input Voltage

DM74AS95

Units

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

V

0.8

V

2

2
0.8

V

IOH

High level Output Current

-2

-2

mA

IOL

low level Output Current

20

20

mA

100

MHz

fCLK

Clock Frequency

tW(CLK)

Clock Pulse Width

tsu

Data Set-Up Time

tH

Hold Time

tEN

tiN

Clock Enable Time
Clock Inhibit Time

0

Operating Free·Air
Temperature

0
5

ns
ns

2.51

2.1

Data

2.51

2.51

ns

ClKl
to Mode

3.51

31

ns

ClK2
to Mode

11

oj

ns

Clock 1

13

12

ns

Clock 2

13

12

ns

Clock 1

3

2.5

ns

Clock 2
TA

80

6.5

1

ns

0

-55

125

0

70

This document contains information on a product under development. NSC reserves the right to change or discontlnue,this product without notice.,

,

3·35

'C

~

Electrical Characteristics over recommended operating free-air temperature range unless otherwise noled

~

::E

c

DM54AS95
Parameter

Conditions

Min

I I)

~

::E
c

Typ
. (Note 1)

DM74AS95
Max

VIK

Vee = 4.5V, II = -18 'mA

VOH

Vee = 4.5V to 5.5V, 10H = - 2 mA

VOL

Vee = Min, IOl=20 mA

II

Vee = 5.5V, V I =7V

IIH

Vee = 5.5V, VI=2.7V

III

Vce = 5.5V,V ll = O.4V

10

Vec= 5.5V, Vo=2.25V

leeH

Ve e =5.5V

21

34

leel

Vee =5.5V

26.1

39

Min

Typ
(Note 1)

...,1.2
Vee- 2

Units

Max
-1.2

V
V

Vec- 2
0.35

0.5

V

0.1

mA

20

20

. p.A

-1
-0.5

-1
-0.5

mA
mA

-112

mA

21

34

mA

26.1

39

mA

0.5

0.35

0.1

I Mode

IOthers
-30

-112

-30

Switching Characteristics over recommended operating free-air temperature range
Parameter

Input Output

Conditions

f MAX , Maximum Clock
Frequency

DM54AS95
Min

Typ

DM74AS95
Max

100

tplH, Propagation Delay Time, Clock
Low to High Level Output

Q

tplH, Propagation Delay Time, Clock
High to Low Level Output

Q

Vee =4.5V to 5.5V,
.Rl =5000,
Cl=50 pF

Notal: All typical values are at vee = 5V, TA=25'e.

3-36

Min

Typ

Max

10Q

Units.
MHz

2

11

10

ns

2

10.5

9.5

ns

~National

a

Semiconductor

DM54AS109/DM74AS109 Dual J-K Positive-EdgeTriggered Flip-Flops with Preset and Clear
General Description

Features

The DM54AS109 is a dual edge-triggered flip-flop. Each
flip-flop has individual J, K, clock, clear and preset inputs,
and also complementary Q and Q outputs.

•
•

Information at input J or K is transferred to the Q output on
the positive going edge of the clock pulse. Clock triggering
occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive going pulse.
When the clock input is at either the high or low level, the J,
K input signal has no effect.

•

Asynchronous preset and clear inputs will set or clear Q
output respectively upon the application of low level signal.
The J K design allows operation as a D flip flop by tying the J
and K inputs together.

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and Vee Range.
Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
Functionally and Pin For Pin Compatible with Schottky
and LS TTL Counterpart.

•
•

Improved AC Performance Over S109 at
Approximately Half the Power.,

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS
DM74AS
Storage Temperature Range

(Note 1)
7V

7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual·ln·Line Package
VCC

116

ClR 2

K"2

J2
14

115

I

113

ClK2 PR2
12

>CLK
J

PR
I;

I
1
ClR 1

2
Jl

-'3
Kl

9

!

PR
J

_ ClR_
;-- K
0-

10

111

L

ClK
-K"

ClR

O!-

-0

°l

L

CLR

L
H
L
H
,H
H
H
H

H
L
L
H
H
H
H
H

~

Low State, H

Inputs
CK

Outputs

X
X
X
1
1
1
1
L
~

High State. X

~

a

J

K

Q

X
X
X
L
H
L
H
X

X
X
X
L
L
H
H
X

L
H
H
L
H*
H*
L
H
TOGGLE
00
'00
H
L
Qo
00

Don t Care

. = Positive Edge Transition, 00 = Previous Condition of a
* This condition is nonstable; it Will not persist when present and clear inputs

I
14
15
ClK 1 PR 1

6
01

7

-01

1B
GND

return to their inactive (high) level. The output levels in thIS condition are not
guaranteed to meet the VOH specIfication.

TLlF/6284·1

54AS109 (J)

PR

02

74AS109 (J,N)

3-37

•

Recommended Operating Conditions
DM74AS109

DM54AS109
Parameter
Supply Voltage, VCC
High Level Input Voltage, VIH

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5·

5.5

V
V

2

2

Unit

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Current, IOH

-2

-2

mA

Low Level Output Current, IOL

20

20

mA

105

MHz

Clock Frequency, fCLOCK

0

90

0

Clock High

4

4

ns

Clock Low

5.5

5.5

ns

4

4

ns

J orR

5.51

5.51

PRE or CLR
inactive

21

21

01

01

Pulse Width TW

Pulse Width TW, Preset & Clear

ns

Data Setup Time, TSU

Data Hold Time, TH

ns

The (I) arrow indicates the POSitive edge of the Clock IS used tor reference.

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25·C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.5V,11 = -18mA

VOH

High Level Output
Voltage

IOH = -2mA
Vee = 4.5V to 5.5V

VOL

Low Level Output
Voltage

Vee = 4.5V
VIH = 2V
IOL = 20m A

II

Max High Input Current

IIH

High Level
Input Current

Clock, J,

K

Min

Typ

Low Level
Input Current

Clock, J,

K

Unit

-1.2

V
V

VCC -2

0.5

V

Vec = 5.5V, VIH '= 7V

0.1

mA

VCC = 5.5V,VIH = 2.7V

20

IlA

0.35

Preset, Clear
IlL

Max

40
-0.5

VCC = 5.5V,VIL= O.4V

Preset, Clear

mA

-1.8

10

Output Drive
Current

VO=2.25V, Vce=5.5V

ICC

Supply Current

VCC = 5.5V

-30

-112

11.5

3-38

17

mA .

mA

c

s:U1

Switching Characteristics over recommended operating free air temperature range (Note 1).

~

All typical values are measured at Vee = 5V, TA = 25°C.
DM74AS109

DM54AS109
Parameter

From

To

Conditions

Min

TPHL

Max

90

FMAX
TpLH

Typ

Q or

Preset
or clear

a

VCC = 4.5V to 5.5V
RL = 500 n
CL = 50 pF

TpLH

Min

Typ

Max

Unit
MHz

105

3

9

3

8

ns

3.5

11.5

3.5

10.5

ns

3.5

10

3.5

9

ns

4.5

10.5

4.5

9

ns

.....

-s:
~
C

~

~
.....

o

CD

Q or

Clock

a

TPHL

Note 1: See Section 1 for test waveforms and output load.

Logic Diagram
PRESET

CLeAR

eLK

•
TLlF/6284·2

3-39

~r-----------------------------------------------------------------------,

~ ~National

PRELIMINARY

~ a Semiconductor
:iE

c

N DM54AS112/DM74AS112 Dual J-K Negative;.Edge~ Triggered Flip-Flops with Pr~set and Clear
'

~

It)

:iE

c

General Description

Features

The DM54AS112 is a dual edge-triggered flip-flop. Each
flip-flop has individual J, K, clock, clear and preset inputs,
and also complementary a and outputs.
Information at input J or K is transferred to the a-output on
the negative going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not
directly related to the transition time of the positive gOing
pulse. When the clock input is at either the high or low
level, the J, K input signal has no effect.

_ Switching Specifications at 50 pF.
_ Switching Specifications Guaranteed .over Full
Temperature and VCC Range.
'
_ Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
_ Functionally and Pin For Pin Compatible with Schottky
and LS TTL Counterpart.
_ Improved AC Performance Over S112 at
Approximately Half the Power.

Asynchronous preset and clear inputs will set or clear Q
output respectively upon the application of 10~ level signal.

Absolute Maximum Ratings

a

By tying the J K inputs high, these devices can operate as
toggle flip-flops.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
'DM54AS
DM74AS
Storage Temperature Range

(Note 1)
7V
7V

-55°C to 125°C
O°C to 70°C
-65°C to. 150°C

Not. 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the abaolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual-In-Line Package
Vee

CLR t

CLR 2

CLK2

K2

Inputs

J2

PR 2

02

Outputs

PR

CLR

CLK

J

K

L

H
L
L
H
H
H
H
H

X
X
X

X

I
I
I
I

L
H
L
H
X

X
X
X
L
L
W
H

H
L
H
H
H
H
H

H

X·
X

X

Q

a

L
H
L
H
H'
H'
ao
00
H
L
L
H
Toggle
ao
00

l = low State, H = High State, X = Don't Care

I = Negative Edge Transition, 00 = Previous Condition of 0
'This condition is nonstable; it will not persist when preset and clear
Inputs return to their inactive(high) level. The output levels In this
condition are not guaranteed to meet the VOH specification.
CLK 1

Kt

Jl

PR 1

01

Q2

01

GND

TLlF/6285-1

54AS112 (J)

~his

74AS112 (J, N)

document contains information on a product under development. NSC reserves the right to change or discontinue this product without notice.

3-40

-------------------------------------------------------------------.0

s:
en

Recommended Operating Conditions
DM54AS112
Parameter
Supply Voltage, VCC

DM74AS112

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

High Level Input Voltage, VIH

2

Low Level Input Voltage, VIL

V
V

0.8

0.8

-2

High Level Output Current, 10H

Unit

-2

V
mA

~.....
.....

-s:
I\)

o

~
l>

en
.....

.....

I\)

Low Level Output Current, 10L

20

Clock Frequency, fCLOCK

0

20

mA
MHz

0

Clock High

ns

Clock Low

ns

Pulse Width TW

Pulse Width TW, Preset & Clear

ns
J orK

ns

Data Setup Time, TSU
PRE
inactive

ns

Data Hold Time, TH !
The (1) arrow indicates the negative edge of the Clock is used for reference.

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25°C.
Max

Unit

-'1.2

V

Conditions

Input Clamp Voltage

VCC = 4.5V, II = -18mA

,VOH

High Level Output
Voltage

10H = -2mA
VCC = 4.5V to 5.5V

VOL

Low Level Output
Voltage

VCC = 4.5V
VIH = 2V
10L = 20mA

II

Max High Input Current

VCC = 5.5V, VIH = 7V

mA

IIH

High Level
Input Gurrent

VCC = 5.5V, VIH = 2.7V

I'A

VIK

Clock, J, K

Min

Typ

Parameter

Symbol

V

VCC -2

0.35

0.5

V

Preset, Clear
Low Level
Input Current

IlL

10

,
ICC

Clock
J, K
Preset, Clear

-5

VCC = 5.5V, VIL = OAV

mA

-1
-5.5

Output Drive
Current

VO=2.25V, VCC=5.5V

Supply Current (Note 1)

VCC = 5.5V

--30

-112

38

Note 1: I CC is measured with outputs open and J, K, ClK, PRE grounded, then with J, K, ClK, and ClR grounded.

3·41

mA

mA

•

N.----------------------------------------------------------------------------

~

.....
~

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee

~

:e

c
N
.....
.....

~

:e
c

=5V, TA =25°C.
DM54AS112

Parameter

From

To

Conditions

Min

FMAX
TPLH

Preset

o or
Q

TpHL

VCC = 4.5V to 5.5V
RL = 500 Il
CL = 50 pF

TpLH
Clock
TpHL

Oor

,

Q

Typ

DM74AS112
Max

Min

Unit

175

MHz

3

3

ns

4

4

ns

3

3

ns

4

4

ns

Logic Diagram

~----~------+-C~

eLK
TL/F/,6285·2

342

Max

175

Noll I: See Section 1 for test waveforms and output load.

PR~----~~----~

Typ

r-----------------------------------------------------------------~c

.
~ Semiconductor

~National

PRELIMINARY

...~...

Co)

DM54AS113/DM74AS113 Dual J-K·Negative-EdgeTriggered FHp-Flops with Preset
General Description

Features

The DM54ASl13 is a dual-edge-triggered flip-flops. Each
flip-flop has individua'i J, K, clock, and preset inputs, and
also complementary a and a outputs,

•
•

Information at input J or K is transferred to the a output on
the negative going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not
directly related to the transition time of the positive going
pulse. When the clock input is at either the high or low
level, the J, K input signal has no effect.
'
Asynchronous preset inputs will set
plication of low level signal.

a output upon the ap-

The JK design allows operation as a toggle flip-flop by
tying the J and K inputs high.

c
3:

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range,
• Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process,
• Functionally and Pin For Pin Compatible with Schottky
and LS TTL Counterpart. .

•

Improved AC Performance Over Sl13 at
Approximately Half the Power.

Absolute Maximum Ratings

(Note 1)
7V
7V

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS
DM74AS
Storage Temperature Range

-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

not be operated at these limits, The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings, The "Recommended Operating Conditions" table will
define the conditions for actual device operation.
'

Connection Diagram

Function Table

Dual-In-Line Package
vee

'1,4

ClK 2

J2

K2

13

lZ

oz

PR 2

1,0

11

lIz

9

8

PR

-

L

1

3

Z

Kl

Jl

54ASl13(J)

14
PR 1

X

I
I
I
I
H

J
X
L
H
L
H
X

Q

K

Q

X
H
H
L
L
X

H
L
L
H
Toggle
aO
L
H
ao
aD

ao

=Low State, H =High State, X =Don't Care
Edge TranSition, 00 =Previous Condition of a

I = Negative

'Y
ClK 1

CK

L
H
H
H
H
H

-

Outputs

Inputs

0
'-

6

5

01

-

01

3:
(J1

P

GND
TLIF/6286-1

74ASl13(J, N)

This document contains informat!on on a product under development. NSC reserves the right to change or discontinue this product without notice.

3-43

......~
Co)

~r-------------~-------------------------------------------------------------

::

~
~

Recommended Operating Conditions
DM54AS113
Parameter

~

-........
c

Supply Voltage. VCC

DM74AS113

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

' Unit
V

~

~
~

c

High Level Input Voltage. VIH

2

2

V

Low Level Input Voltage. VIL

O.B

O.B

V

High Level Output Current. 10H

-2

-2

mA

Low Level Output Cu·rrent. 10L

20

20

mA

Clock Frequency. fCLOCK

0

MHz

0
'\

Clock High

ns

Pulse Width TW
ns

I

Clock Low

ns

Pulse Width TW. Preset
J orK

ns

Data Setup Time. TSU
PRE inactive
Data Hold Time. TH

ns

The (I) arrow indicates the negative edge of the Clock is used for reference.

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25°C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.5V, II = - 18mA

VOH

High Level Output
Voltage

10H = -2mA
VCC '7' 4.5V to 5.5V

VOL

Low Level Output
Voltage

VCC = 4.5V
VIH = 2V
10L = 20m A

II

Max High Input Current

IIH

High Level
Input Current

,

Clock. J. K

Min

Typ

Low Level
Input CUrrent

Output Drive
Current

0.5

V

VCC=5.5V. VIH =7V

0.1

mA

VCC=5.5V, VIH=2.7V

20

/J.A

-5"
-1

VCC = 5.5V. VIL = O.4V

J. K

ICC

Supply Current

=

V

40

Clock

VCC

-1.2

It
0.35.

mA

-5.5

Preset
10

Unit

VCC -2

Preset
IlL

Max

5.SV

Vo

2.2SV

=

VCC

=

S.SV

3·44

·-'30

-112

38

mA

rnA

------------------------------------~-----------------------------.c

s::

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V, TA = 25°C.
DM54AS113
Parameter

From

Conditions

To

Min

"
FMAX
TPLH

Preset

TpHL

Oar

a

VCC = 4.5V to 5.5V
RL = 500n
CL = 50 pF

TpLH
Clock
TpHL

Typ

DM74AS113
Max

Min

Typ

Max

Unit

175

MHz

3

3

ns

4

4

ns

3

3

ns

4

4

ns

Note 1: See Section 1 for test waveforms and output load.

Logic Diagram

jj

PH ~1----4,""""--'"

K-====I
elK

TLlF/6286·2

3·45

-s::
Co)

175

Oar

a

~..........
c

:i::!
l;;
.....
.....
Co)

~~--------------~--------------------------------------------------------~

::

~ National

.
Semiconductor

~a

PRELIMINARY

~

-

c DM54AS114/DM74AS114 Dual J-K Negative-Edge~
Triggered Flip-Flops with Preset, Common Clear
~ and Common Clock
Features
~ General Description
"t"t-

c

The DM54AS114 is a dual edge-triggered flip-flop. Each
flip-flop has individual J,. K, and preset inputs, and also
complementary Q and Q outputs. The' clear and clock inputs are common to both flip-flops.
Information at input J or K is transferred tothe Q output on
the negative going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not
directly related to the transition time of the positive going
pulse. When the clock input is at eittler the high or low
level, the J, K input signal has no effect.
Asynchronous preset and common clear inputs will set or
clear Q outputs respectively upon the application of low
level signal.
The JK design allows operation as a toggle flip-flop by
tying the J and K inputs high.

•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and Vec Range.
Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.

•
•

Functionally and Pin For Pin Compatible with Schottky
and LS TTL Counterpart.

•

Improved AC Performance Over S114 at
Approximately Half the Power.

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS
DM74AS
Storage Temperature Range

(Note 1)
7V
7V

-55°C to 125°C
O°C to 70°C
-65°C to 1S0°C

Nota 1: The "Absolute Maximum Ratings" are. those values beyond

which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual-In-Line Package

Vi~4

J2

ClK

It3

T'2

Q2

PR2

'0

11

9

«2

·1 Inputs

8

L--

1
6

I.e

r-, il

..,-

'i

I

c~~

I

rr

14
PR 1

J,5

J,G

l'

GND

TLlF/6287-1

54AS114(J)

CK

J

K

Q

L

H
L
L
H
H
H
H
H

X

X
X
X

H
L

X

X
X
X

1
1
1
1

L
H
L
H

H
H
L
L

H

X

X

L
H
H
H
H
H

'---

-

CLR

H

-

~

Outputs

PR

.x

a

L
H
H'
H'
L
H
TOGGLE

00

00

H

L

00

00

L = Low State, H = High State, X = Don·t Care
I = Negative Edge TranSition, 00 ~ Previous Condition of 0
• This condition is nonstable; it will not persist when present and clear inputs
return to their inactive (high) level. The output levels 10 thiS condition are not
guaranteed to meet the VOH specification.

74AS114(J, N)

This document contains information on a product under development. NSC

rese~es

3-46

the right to change or discontinue this product without notice.

c

s:
U'I

Recommended Operating Conditions
DM54AS114
Parameter
Supply Voltage, VCC
High Level Input Voltage, VIH

DM74AS114

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V
V

2

2

Unit

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Current, 10H

-2

-2

mA

Low Level Output Current, 10L

20

20

mA

;

en
.....
.....

-s:
~

C

~

.....
.....
~

Clock Frequency, fCLOCK

0

MHz

0

Clock High

ns

Clock Low

ns

Pulse Width TW

Pulse Width TW, Preset & Clear

ns
J orK

ns

Data Setup Time, TSU
PRE or CLR
inactive
Data. Hold Time, TH

I

-

I

ns

The (I) arrow indicates the negative edge of the Clock is used for reference.

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25°C.
Symbol

Parameter

Conditions .

VIK

Input Clamp Voltage

VCC=4.5V, 11= -18mA

VOH

High Level Output
Voltage

10H = -2mA
VCC = 4.5V to 5.5V

VOL

Low Level Output
Voltage

VCC ='4.5V
VIH = 2V
10L = 20mA

II

Max High Input Current

VCC=5.SV, VIH=7V

mA

IIH

High Level
Input Current

VCC = 5.SV, VIH = 2.7V

I1A

Clock, J,

K

Min

Typ

Max

Unit

-1.2

V
V

VCC -2

0.35

0.5

V

Preset
IlL

Low Level
Input Current

Clock,
J,K

-10.S
-1

VCC=S.SV, VIL=O.4V

-S.S

Preset

-ll.S

Clear
10

Output Drive
Current

ICC

Supply Current

VCC = 5.5V

mA

VCC

=

-112

-30

Vo = 2.25V

5.5V .

347

38

mA

mA

qo
~

~

~

Switching Cha.racteristics over recommended operating free air temperature range (Note 1).
All typical values are measured al Vee = 5V, TA = 25°C.

~

DM54AS114

:!

-

Parameter

qo

FMA~

~

TPLH

c

~

From

To

Conditions

. Min

Typ

DM74AS114
Max

Min

Typ

Max

Unit

175

175

MHz

3

3

ns

4

4

ns

3

3

ns

4

4

ns

~

TpHL

Preset
or clear

Oor

Clock

Oor

Q

:!

c

VCC = 4.5V to 5~5V
RL = 500 fl
CL = 50 pF

TpLH
TPHL

Q

Notet: See Section 1 for lest waveforms and oulput load.

Logic Diagram

>0........-0

Q .......-o{

PIl--+---.....-_....

....---+---+-t-CLR

K-===I
TO OTHER
FLlP·FLOP
TLlF./6287·2

3-48

r------------------------------------------------------------------,c

3:

~Natiollal

U1

~

~ Semiconductor

-'"

Co)

-'"

DM54AS131/DM74AS131 3·to·8 Line
Decodersl Demultiplexers with Address Registers
General Description

~

Features

The DM54/74AS131 is a 3·to·8Iine decoder/demultiplexer
with registers on the three address inputs. When the clock
input (ClK) goes from low to high, the DM54/74AS131 acts
as a decoder/demultiplexer, and the address present at
the select inputs (A, B, and C) is stored in the registers.
Further address changes are ignored until the next rising
transition of ClK. The output enable controls, G1 and G2,
control the state of the outputs independently of the
select or ClK inputs. All of the outputs are high unless G1
is high and G2 is low. The DM54/74AS131 is ideally suited
for implementing glitch·free decoders in strobed (stored
address) applications in bus·oriented systems.

Connection Diagram

-'"

Co)

• Combines decoder and 3·bit address register
• Incorporates 2 enable inputs to simplify cascading

Absolute Maximum Ratings (Note 1)
7V
7V
-65'Cto +150'C

Supply Voltage
Input Voltage
Storage Temperature R,mge

Nota 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical .Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual·ln·Line Package
Vee

Yl

YO

1,6

15

Y2

14

Y3

DM54AS131 (J)

Function Table

Y4

12

13

eLK
62
TOP VIEW

A

11

Enable

Y5

Y6

10

18
Gl

Y7

GND
TUF/67171

DM74AS131 (J, N)

Inputs
CLK

c
3:

Outputs

Select

G1

G2

C

B

A

YO

Y1

Y2

Y5

Y6

Y7

I
I
I
I
I
I
I
I

X
L
H
H
H
H
H
H
H
H

H
X
L
L
L
l
L
L
L
l

X
X
L
L
L
l
H
H
H
H

X
X
L
L
H
H
l
L
H
H

X
X
L
H
l
H
l
H
l
H

H
H
L
H
H
H
H
H
H
H

H
H
H
L
H
H
H
H
H
H

H
H
H
H
H
H
H
H
l
H

H
H
H
H
H
H
H
H
H
l

l
or

H

l

X

X

X

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
H
H
H
H
l
H
H
H
L
H
H
H
H
H
H
H
H
H
Outputs Corresponding
to Stored Address L.
All Others H.

,x
X

H
3·49

Y3

Y4

-'"

Recommended Operating Conditions
Symbol
Vcc

Supply Voltage

VIH

High level Input Voltage

VIL

low level Input Voltage

10H

High level Output Current

10L

low level Output Current

fCLOCK

Clock Frequency

tw

Clock Pulse Width

Min

Typ

Max

. Min

'iYP

Max

4.5

5

5.5

4.5

5

5.5

2

-

tsu

Select Set·Up Time
Select Hold Time

TA

Operating Free-Air Temperature

V
r

0.8,

0.8
-2

-2

20

I ClK High
I ClKlow

Units

2

0

tH

DM74AS131

DM54AS131

Parameter

90

0

5.5

5

5.5

5

3.5

3.51

1

01

-55

125

'V
V
mA

20

mA

100

MHz
ns

ns
ns

0

·C

70

The arrow (j) indicates that the positive going edge of the clock is used as reference,

Electrical Characteristics over recbmmended operating fr~e-air temperature range unless otherwise noted
DM74AS131

DM54AS131
Parameter

Conditions

VIK

Vcc = 4.5V, II = -18 mA

VOH

VCC = 4.5V to 5.5V, 10H = Max,
VIL = Max, VIH = Min

VOL

Vcc =4.5V,l oL =Max,
VIL = Max, VIH = Min

II

Vcc =5.5V, V I =7V

Typ
(Note 1)

Min

Max

Min

Typ
(Note 1)

-1,2
Vcc-2

Max
-1.2

0.5

V
V

Vcc-2
0.35

. Units

0.35

0.5

V

0.1

0.1

mA
/LA

IIH

Vcc =5.5V, VI=2.7V

20

20

IlL

Vcc=5.5V, V I =0.4V

-1

-1

mA

10

Vcc= 5.5V, Vo =2.25V

-112

mA

ICCL

Vcc =5.5V

16

-112
30

16

30

mA

ICCH

VCC= 5.5V

15

29

~5

29

mA

-30

-30

Switching Characteristics
DM54AS131
Parameter

Input

tpLH

Clock

y

t'PHL

Clock

y

tpLH

G1

y

tpHL

G1

y

tpLH

G2

y

tpHL

G2

y

Nota 1:

Output

Conditions

Vcc =4.5V
to5.5V,
C L =50 pF,
R L =500n,
TA=Min
to Max

Min

Typ
(Note 1)

2

DM74AS131
Max

Min

Typ
(Note 1)

Max

Units

10

2

9

ns

2

10

2

9

ns

2

10.5

2

9.5

ns

2

9

2

8.5

ns

2

7.5

2

7

ns

2

8.5

2

8

ns

All typlcals are at VCC=SV, TA =2S"C.

3-50

I

Logic Diagram

elK

.!.[::>

A 1

DATA
OUTPUTS

TLIF16717·2

3·51

~

-

~National

PRELIMINARY

~ ~ Semiconductor

:E

c

~ DM54AS136/DM74AS136 Quad 2-lnput Exclusive-OR

-~

Gates with Open-COllector Outputs

:E General Description

c

Features

This device contains four independent gates each of
which performs the logic exclusive-OR function_ The opencollector outputs require external pull-up resistors for
proper logical operation.

Pull·Up Resistor Equations

• Switching specifications at 50 pF
• 'Switchlng specifications guaranteed over full
temperature and Vee range
• Advanced oxide-isolated, lon-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky,
low power Schottky, and advanced low power Schottky
TTL counterparts
• Improved AC performance 9ver Schottky, low power
Schottky, and advanced low power Schottky
counterparts

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

7V
7V
7V
- 6S·Cto 1S0·C

Where:. N1 (IOH) = total maximum output high· current
. for all outputs tied to pull-up, resistor
N2 (IIH) = total maxirnuminput high current for
all inputs tied to pull-up resistor
N3 (III) = total maximum input low current for all
inputs tied to pull-up resistor

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these 11m lis. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
deline the conditions for actual device operation.

Connection Diagram

Function Table

Dual-In-Line Package

Y=A61B
Inputs

Output

Y

A

B

L
L

L

L

H

H
H

L

H
H

H

L

=
=

H High Logic Level
L Low Logic Level

7

A1

B1

Y1

A2

B2

Y2

GND
TLlFI6718-1

DM54AS136 (J)

DM74AS136 IN)

This document contains Information on a product under development. NSC reserves the right to change or discontinue this product without noticB.

3-52

Recommended Operating Conditions
Symbol

Parameter

DM74AS136

DM54AS136
Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units
V

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

0.8

0.8

V

V OH

High Level Output
Voltage

5.5

5.5

mA

10L

Low Level Output
Current

20

20

mA

TA

Free Air Operating
Temperature

70

·C

2

V

2

-55

125

0

Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol

Parameter

Conditions

Typ
(Note 1)

Min

VI

Input Clamp Voltage

Vcc=Min,ll= -18mA

ICEX

High Level Output
Current

Vcc=Min, Vo=5.5V
VIL = Max, V1H = Min

VOL

Low Level Output
Voltage

Vcc = Min, 10L = Max
VIH = Min, VIL = Max

II

Input Current@Max
Input Voltage

IIH

Max

Units

-1.2

V

250

p.A

0.5

V

Vcc=Max, VI=7V

0.1

mA

High Level Input
Current

Vcc=Max, VI = 2.7V

20

p.A

IlL

Low Level Input
Current

Vcc=Max, VI =0.5V

-0.5

mA

Icc

Supply Current

0.35

mA

Vcc=Max
(~ote2)

SwitC?hing Characteristics at Vcc = 5V and TA= 25·C
Parameter
tpLH Propagation
Delay Time Low
to High Level
Output

Conditions

DM54AS136
Min

DM74AS136

Typ

Max

Min

Other Input Low
Vcc= 4.5V to 5.5V
RL =5001l
C L =50pF

Max

Units
ns

ns

tpHL Propagation
Delay Time
High to Low
Level Output
tpLH Propagation
Delay Time Low
to High Level
Output

Typ

Other Input High
Vcc =4.5V to 5.5V
RL =5001l
C L =50pF

ns

"

tpHL Propagation
Delay Time High
to Low Level
Output
Note 1:

ns.

All typicals are at V<::C=5V. TA = 25"C.

Note 2: ICC Is measured with one input of each gate at 4.5V, the other Inputs grounded, and the outputs open.

3·53

~r------------------------------------------------------------------'
('I)

PRELIMINARY

~ ~ National
j:!:

.
~ Semiconductor

:E
~
~

DM54AS137/DM74AS137 3-to-8 Line
Decoder/Demultiplexer with Address Latches

It)

General Description

Features

The DM54/74AS137 is a 3-to-Bline decoder/demultiplexer
with latches on the three address inputs. When the latch
enable input (Gl) is low, the DM54/74AS137 acts as a
decoder/demultiplexer. ,When Gi. goes from low to high,
the address present at the select inputs (A, B, and C) is
stored in the latches. Further address changes are ignored as long as Gl remains high. The output enable con-·
trois, G1 and 132, control the outputs independently of the
select or latch enable inputs. All of the outputs are forced
high if G1 is low or G2 is high. The DM54/74AS137 is ideally
suited for implementing glitch-free decoders in strobed
(stored address) applications in bus-oriented systems.

• Combines decoder and 3-bit address latch
• Incorporates 2 output enables to simplify cascading

~

:E

c

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
Storage Temperature Range

7V
7V
-65·Cto + 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Conn~ction

Diagram

Dual-In-Line Package
VTCC

16

YO
15

Y1

Y2
14

13

Y3
12

Y4
11

Y5
10

Y6

Recommended Operating Conditions
DM74AS137

DM54AS137

Parameter

Symbol

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

Units

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

IOH

High Level Output Current

-2

-2

mA

20

20

mA

0.8

IOL

Low Level Output Current

tw

Latch Enable Low Pulse Width

tsu

Select Set·Up Time ·with Respect to Latch Enable

tH

Select Hold Time with Respect to Latch Enable

TA

Operating Free·Air Temperature

V
V

2

2

0.8

V

ns
4.5

4

ns

1

1

ns

-55

125

0

70

'C

Electrical Characteristics over recommended operating free·air temperature range unless otherwise noted
DM54AS137
Parameter

Conditions

VIK

Vec=4.5V, 11= -18 mA

VOH

Vee = 4.5V to 5.5V, IOH = Max,
VIL = Max, VIH = Min

VOL

Vee = 4.5V, 10L= Max,
VIL = Max, VIH = Min
Enable

II

Min

Typ
(Note 1)

Enable

Enable

0.35

Vee = 5.5V, VI=2.7V

Vee=5.5V, VI=0.4V

A,B,C
Vee=5.5V, Vo=2.25V

Icc

Vee = 5.5V

Typ
(Note 1)

Max
-1.2

-30

V
mA

0.1

0.1
0.1

20

20

20

20

-1

-1

-1

-1
-30
16

24

V

0.5

o.i

-112
16

0.35

0.5

Units

V

Vee- 2

Vee=5.5V, V I =7V

10

Min

-1.2

A,B,C
IlL

Max

Vee- 2

A,B,C
IIH

DM74AS137

I'A

mA

-112

mA

24

mA

Switching Characteristics
DM74AS137

DM54AS137
Parameter

Input

Output

Conditions

tpLH

A,B,C

Y

tpHL

A,B,C

tpLH

G2

Y
y

tpHL

G2

y

Vee=4.5V
to 5.5V,
C L =50 pF,
RL =500n,
TA = Min to Max

tpLH

Gl

y

tpHL

Gl

y

tpLH

GI

y

tpHL

GL

y

2

Typ
(Note 1)

Typ
(Note 1)

,

Units

Max

Min

2

14

2

12.5

ns

2

14

2

12.5

ns
ns

Min

Max

2

8

2

7

2

8.5

2

8

ns

2

10.5

2

9.5

ns

2

9

2

8.5

ns

2

14.5

2

13

ns

14.5

2

13

ns

Nole 1: Aillypical values are al Vee = SV, TA = 2s·e.

3·55

~ r-------------------------------------~----~----------------------------------------,

....

C")

~

Logic Diagram

.~

:E

-c....
~

C")

~:E

A

c

SELECT
INPUTS

DATA
OUTPUTS

E~~~~{llL

4

'.

62..;5;...._ _.......

OUTPUT

ENABLES

G1

.!.-..J::>~~==:[=)-----....;..=~~-)

Y7

TLIF16719-2

3-56

~----------------------------------------------------~-----------------.

~National

~....

~ Semiconductor
DM54AS138/DM74AS138 3-to-8 Line
Decoderl Demultiplexer

-c
:s:
Co)

co
~

General Description

Features

The DM54/74AS138 circuit is designed to be used in high
performance memory decoding or data routing applica·
tions requiring very short propagation delay times. In high
performance memory systems, this decoder can be used
to minimize the effects of system decoding. When
employed with high speed memories utilizing a fast
enable circuit, the delay times of this decoder and the
enable time of the memory are usually less than the
typical access time of the memory. This means that the ef·
fective system delay introduced by the Schottky·clamped
system decoder is negligible.

• Designed specifically for high speed memory decoders
and data transmission systems
• Incorporates 3 enable inputs to simplify cascading
and/or data reception

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
Storage Temperature Range

The conditions at the binary select inputs and the three
enable inputs select one of eight input lines. Two active·
low and one active·high enable inputs reduce the need for
external gates or inverters when' expanding. A 24·line
decoder can be implemented without external inverters
and a 32·line decoder requires only one inverter. An enable
input can be used as a data input for demultiplexing
applications.

Connection Diagram

Nola 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical CharacteristiCS" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

DATA OUTPUTS

T

i

16

YO

Y1

15

.

)'B

1

,

Y2
14

)'C',

V3
13

Iii!:

SELECT

Y5

Y4
12

5

11

GI16,

G!a

ENABLE

VB •

10

9

7
J7

G!:

OUTPUT

TDPVIEW
I

DM54AS138 (J)

Function Table
Enable
Inputs

7V
7V
-65·Cto + 150·C

Dual·ln·Line Package
vte .

TUFI67201

DM74AS138 (J, N)

Select
Inputs

Outputs

G1

G2*

C

VO

V1

V2

V3

V4

V5

V6

V7

H

L
H
H
H
H
H
H
H
H

X

X
X

B
X
X

A

X

X
X

L
L
L
L
L
L
L
L

L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H

H
H
L
H
H
H
H
H
H
H

H
H
H
L
H
H
H
H
H
H

H
H
H
H
L
H
H
H
H
H

H
H
H
H
H
L
H
H
H
H

H
H
H
H
H
H
L
H
H
H

H
H
H
H
H
H
H
L
H
H

H
H
H
H
H
H
H
H
L
H

H
H
H
H

'G2=G2A+G2B

c

PRELIMINARY :s:

H
H
H
H
H
L

,

This document contains information on a product under development. NSC reserves the right to change or discontinue this product without notice.

3·57

....~

~

Recommended Operating Conditions
Symbol

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

10H

High Level Output Current

IOL

Low Level Output Current

TA

Operating Free·Alr Temperature

DM54AS138

DM74AS138

Units

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

V

0.8

V

2

2

V

0.8
-2

-2

mA

20

mA

70

·c

20
-55

125

0

Electrical Characteristics over recommended operating freecair temperature range unless otherwise noted

,
Parameter

Conditions

DM54AS138
Min

DM74AS138

Typ
(Note 1)

Max

Min

Typ
(Note 1)

-1.2

Units

Max
-1.2

V

VIK

Vee = 4.5V, 11= -18 mA

VOH

Vee = 4.5Vto 5.5V, 10H = Max,
VIL = Max, VIH = Min

VOL

Vee = 4.5V, 10L=Max,
VIL = Max, VIH = Min

II

Vee=5.5V, V I =7V

IIH

Vee =5.5V, VI = 2.7V

/LA

IlL

Vee =5.5V, V IL =0.4V

mA

10

Vee = 5.5V, Vo=2.25V

-112

mA

leeL

Vce=5.5V

14

20

14

20

mA

leeH

Vee=5.5V

13

19

13

19

mA

Vee- 2

V

Vee- 2
0.35

0.5

0.35

0.5

V
mA

-112

-30

-30

Switching Characteristics
DM74AS138

DM54AS138
Parameter

Input

Output

Conditions

I

Units

Max

Min

Typ
(Note 1)

Max

2

9

2

5.6

8

ns

2

11

2

6.4

9

ns

2

8

2

5.8

7.5

ns

9

2

5.5

7.5

ns

Min

Typ
(Note 1)

tpHL

A,B,C

y

tpHL

A,B,C

y

tpLH

132

y

132

y

2

tpLH

G1

y

2

11.5

2

9

ns

tpHL

G1

y

2

10

2

8.5

ns

tPHL

Vee = 4.5V to 5.5V,
CL=50 pF,
R L = 500n,
TA=Min to Max

Note 1: See Section 1 for test waveforms and output load.

,

3·58

~------------------------------------------~~

Logic Diagram

U1

....~

Co)

00

C

s::
~

1;;
....
~

SELECT
INPUTS
DATA
OUTPUTS

Y6

il2A 4

0

ENABLE { il2B 5

0

INPUTS

Gl'!'[>o-r
TLIFI67202

3·59

•

, r---------------------------------------------------------------------------------------,
~
II)
~

Ul
~

~

:liE

PRELIMINARY

~National

a

Semiconductor

~ DM54AS151/DM74AS151 8-Line to 1-Line
~ Data Selector/Multiplexer

~

:liE
c

General Description

Absolute Maximum Ratings

This Data SEllector/Multiplexer contains lui! on-chip decoding to select one-ol-eight data sources as a result 01 a
unique three-bit binary code at the Select inputs, Two complementary outputs provide both inverting and non-inverting buffer operation. A Strobe input is provided which,
when at 'the high level, disabl,es all data inputs and lorces
the Y output to the low state and the W output to the high
state. The Select input buffers incorporate internal overlap
leatures to ensure that select input changes do not cause
invalid output transients,

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS151
DM74AS151
Storage Temperature Range
Lead Temperature
(Soldering, 10 seconds)

Advanced Oxide-Isolated, lon-Implanted Schottky TTL
process.

•

Switching Performance is Guaranteed Over Full
Temperature and VCC Supply Range,

•

Pin and Functional Compatible with LS and Schottky
Family Counterpart.

•

Improved Output Transient Handling Capability.

Connection Diagram

Inputs

Outputs

Select
~

1

lLvcc

02

2

15' D4

01

3

14 05

DO

4

13 06

OUTPUTY

5

DATA
INPUTS
DATA
INPUTS

',;1

,..

OUTPUT W 6

.A
"""I

STROBE S 7

t-..

Strobe

C

B

A

S

X

X

X

L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H

H
L
L
L
L
L
L
L
L

y
L
DO
D1
D2
D3
D4
D5
D6
D7

I

W
H

150
Of
~

IJ3
04
()5

DO
Di

12 07

,~

A

\..

A

"""I

H = High Level, L= Low Level, X = Don't Care
DO thru 07 = the level of the respective 0 input
II SELECTA

-

i~

....

B

,..

c~
'GNO-!

-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Function Table

Dual·ln·Llne Package

03

7V
7V

Note 1: The "Absolule Maximum Ratings" are those valueS beyond
which the safety of the device can not be guaranteed, The device should
not be operated at these limits. The parametric values dellned In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
dellne the conditions lor actual device operation.

Features
•

(Note 1)

,..

~

10 SELECT B

9

SELECT C

,
54AS151 (J)

74AS151(J,N) TLlF/6288·1

This document contains information on a product under development. NSC reserves the right to change or discontinue this product without notice,

3-60

--------------------------------------------------------------.0
Recommended Operating Conditions

3:

U'I

DM74AS151

DM54AS151
Parameter

Min

Supply Voltage, VCC

Nom

Max
5.5

4.5

High Level Input Voltage, VIH

Min

Nom

4.5

5.5

2

2

Unit

Max

ten
...I.

.

V
V

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Current, 10H

-12

-15

rnA

Low Level Output Current, 10L

32

48

rnA

Max

Unit

-1.2

V

-o
U'I
...I.

3:.

:is!
~

...I.

U'I
...I.

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25°C.
Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.5V, liN = -18mA.

VOH

High Level Output
Voltage

VCC ;", 4.5V, 10H = Max

Symbol

Min

2.4

10H = -2mA

Typ

3.2

VCC-2

VOL

Low Level Output
Voltage

VCC=4·.5V,IOL=Max

II

Input Current at
Max Input Voltage

VCC

IIH

Hig!1 Level Input Current

VCC

IlL

Low Level Input Current

VCC = 5.5V,
VIN = O.4V

= 5.5V, VIN = 7V

= 5.5V, VIN = 2.7V

V

,
0.35

V

0.5

V

mA

A,B,C

0.2

All Others

0.1

A,B,C
All Others

40
20

A,B,C

-1

All others

-0.5

,

10

Output Drive Current

VCC ":' 5.5V, VOUT

ICC

Supply Current

VCC

/LA

'mA

= 2.2SV

-30
18.6

= 5.5V

3·61

-112

mA

30

mA

-,-------------------------------------------------------------------------------

II)

-

~
~
:E

-c

I I)

;

II)

:E

c

Switching Characteri~tics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V. T A = 25°e.
DM74AS151

DM54AS151
Parameter

From

To

Conditions

tPLH. Low to high Level Output

Min

Typ

Typ

Max

Unit

Max

Min

4.5

16

4.5

14.5

ns

4.5

16

4.5

15

ns

4

14.5

4

12

ns

4

14.5

4

12

ns

3

11.5

3

10.5

ns

3

12

3

11

ns

2

8

2

6.5

ns

1

5:5

1

4.5

ns

4.5

16

4.5

14

ns

3

12.5

3

11

ns

1.5

7

1.5

6.5

ns

3

11

3

'10

ns

y

tpHL. High to low Level Output
Select

r--

tPLH. Low to high Level Output

W
tpHL. High to low Level Output
tPLH. Low to high Level Output
y

tPHL. High to low Level Output
Data

r--

tpLH. Low to high Level Output

W

Vee =
4.5 to 5.5V
eL = 50 pF
RL = 500 (!

tPHL. High to low Level Output
tPLH. Low to high Level Output
y

tpHL. High to low Level Output
Strobe

-

tpLH. Low to high Level Output

W
tpHL. High to low Level Output
Note 1: See Section 1 for test waveforms and output load.

Logic Diagram
STAIIIE-"'...q,;>---------,

".!.'-----i:t1~:I=:t=h

,,'
DAU

INPUTS

OJ 12

,-'-I>C-"""'..q:)-.!.-TLI F 16288·2

3-62

~National

,
Semiconductor

D

DM54AS153/DM74AS153 Dual 4-Line to 1-Line
Data Selector/Multiplexer
General Description '

Absolute Maximum Ratings

This Data Selector/Multiplexer contains full on-chip decoding to select one-of-four data sources as a result of a
unique two-bit binary code at the Select inputs. Each of the
two Data Selector/Multiplexer circuits have their own separate Select. Data, and Strobe inputs and a non-inverting
output buffer. The Strobe inputs, when at the high level, disable their associated data inputs and force the corresponding output to the low state. The Select input buffers
incorporate internal overlap features to ensure that select
input changes do not cause invalid output transients.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS153
,DM74AS153
Storage Temperature Range
Lead Temperature
(Soldering, 10 seconds)

7V
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute

Features
•

(Note 1)

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Advanced Oxide-Isolated, lon-Implanted Schottky TTL
process.

•

Switching Performance is Guaranteed Over Full
Temperature and VCC Supply Range.
• Pin and Functional Compatible with LS and Schottky
Family Counterpart.
.• Improved Output Transient Handling Capability.

Function Table

Connection Diagram
Dual·ln·Line Package

STROBEG I

SELECT 8

...

I

......

2

....

-

IC2!....!.

-

INPUTS
IC1.2

leo ~

OUTPUTYI

7

.!.2.. Vee

ttl

IC3,..1

DATA

Select
Inputs

-

A

....

15

Q,.,

14

-

!!. 2&3

-

Jl..2C2

....

B

B

ii

ii

A

A

A

A

~T
.....

GNO ....!

STROBE G2

SELECT A

DATA'
INPUTS.

I - - flL 2CI
I--- flQ...2CO

T~v

9

OUTPUT Y2

TLlF/6289·1

54AS153 (J)

74AS153 (J,iII)

3·63

Data Inputs

Strobe

Output

B

A

CO

C1

C2

C3

G

y

X
L
L
L
L
H
H
H
H

X
L
L
H
H
L
L
H
H

X
L
H
X
X
X
X
X
X

X
X
X
L
H
X
X
X
X

X
X
X
X
X
L
H
X
X

X
X
X
X
X
X
X
L
H

H

L
L
H
L
H
L
H
L
H

L
L
L
L
L
L
L
L

Select inputs A and B are common to both sectIons
H - HIgh Level L = Low Level X = Don't Care

~r----------------------------------------------------------------------------

it)
"r'"

~

Recommended Operating Conditions
·DM54AS153

~

Parameter

c
co;
it)

Supply Voltage, VCC

"r'"

High Level Input Voltage, V,H

:E

~
:E
c

DM74AS153

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

2

. Unit
V·
V

Low Level Input Voltage, V,L

0.8

0.8

V

High Level Output Current, IOH

-12

-15

mA

Low Level Output Current, IOL

.32

48

mA

Max

Unit

-1.2

V

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25°C.
Symbol

Parameter

Conditions

V,K

Input Clamp Voltage

VCC

=

4.5V, liN

VOH

High Level Output
Voltage

VCC

=

4.5V, IOH

IOH =

Min

=
=

2.4

MAX

- 2mA, VCC = 4.5V to 5.5V

Low Level Output
Voltage

VCC = 4.5V
IOL = MAX

Input Current at
Max Input Voltage

VCC

=

5.5V, V,N

=

7V

IIH

High Level Input Current

VCC

=

5.5V, V,N

=

IlL

Low Level Input Current

VCC = 5.5V
V,N = O.4V

VOL

Typ

-18mA

V

3.2

V

VCC-2
0.5

V

A,B
G

0.2
0.1

rnA

A,B
2.7V G

40
20

A,B

-1

0.35

"

p.A

rnA

G

10

Output Drive Current

VCC

=

5.5V, VOUT

ICC

Supply Current

VCC

=

5.5V

=

2.25V

-0.5
-112

-30

Outputs high

16

Outputs low

21

rnA

26
rnA

\

3-64

33

c

s::

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vcc =5V, TA = 25"C.
DM74AS153

DM54AS153
Parameter

From

To

Select

y

tpLH. Low to high Level Output

Conditions

tpHL. High to low Level Output
VCC =
4.5 to 5.5V
CL = 50 pF
RL = 500 n

tPLH. Low to high Level Output

Y

Data
tpHL. High to low Level Output
tpLH. Low to high Level Output

3

14

3

12.5

n5

3

12.5

3

11

n5

2

8

2

7

ns

2

8.5

2

8

n5

3

13

3

11.5

ns

2

10

2

9

ns

y

Strobe
tpHL. High to low Level Output
Note 1: See Section 1 for test waveforms and output load.

Logic Diagram
......
, -...
1

STR08£GI
ICO

J

l

!lATA I

Ie>

1C3

14

""'1''""

STRO!EG2

~

OUTPUT
VI

~

"....

1

....

-"

I

"0 "
[

'"

}-

...:..-.....

3

,

.

==t

•

smCT{ B
,

r= ===I

5

ICI

~

11

t---i

r--+-' ~

,

OUTPUT

---+--

"

r-----

13
IS

Max

.....

}-

TL/F/6289·2

3-65

"

......
C

Min

Typ

Typ

en
Co)

Max

Min

~

Unit

-s::
~

Gi......
en
Co)

~

,..

~

~ .a

National
Semiconductor

:!:

c

co

DM54AS/DM74AS157,158 Quad 2-Line to 1-Line

,..
en Data Selectors/Multiplexers
II)

-ct

~ General Description
:!:

c
r-:
II)

,..
~

j:!

:!:

These data selectors/multiplexers contain inverters and
drivers to supply full on-chip data selection to the four output gates. A separate strobe input is provided. A 4-bit word
is selected from one of two sources and is routed to the
four outputs. The AS157 presents true data whereas the
AS158 presents inverted data to minimize propagation delay time.

-cC;; •
to-

Il)

C

Improved AC. Performance Over Schottky, Low Power
Schottky, and Advanced Low Power Schottky
.
Counterparts.

•
•
•

Expand any data input point.
Multiplex dual data buses.
General four functions of two variables (one variable is
common).

•

Source programmable counters.

Absolute Maximum Ratings

Features

::!; •
in
:!: •

•

Switching Specifications at 50 pF.
Switching Specifications· Guaranteed Over Full
Temperature and VCC Range.
Advanced OXide-Isolated, lon-Implanted Schottky TTL
P·rocess;

.• Functionally and Pin for Pin Compatible with Schottky,
Low Power Schottky, and Advanced Low Power
Schottky TTL Counterpart.

Connection Diagram

(Note 1).

Supply N'oltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
. -55°C to 125°C
DM54AS
DM74AS
O°C to 70°C
Storage Temperature Range
-65°C to 150°C

Nole 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can no! be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Elecirical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Dual-In-Line Package

---INPUTS

VCC STROBE 4A
"116

15

14

----

OUTPUT INPUTS

4B

13

4Y
12

3A

OUTPUT

3B.

11

10

3Y

9

Output Y

Inputs'
G

4A

4B

4Y

3A

,..-S

3B
3Y -

1A

1B

1Y

2A

2B

2Y

Strobe

Select

A

B

AS157

AS158

H
L
L
L

X

X

L
L
H
H

L
H

X
X
X

X
X

L
H

L
L
H
L
H

H
H
L
H
L

L
2

. 3

4

5

6

7
H - High Level. L - Low Level. X - Don·t Care

SELECT

1A

1B

INPUTS

1Y

2A

2B

OUTPUT INPUTS

2Y
OUTPUT
TLfFf6290·1

54AS157 (J)
54AS158 (J)

74AS157 (J, N)
74AS158(J, N)

3·66

Recommended Operating Conditions
DM54/74AS157,158
Parameter

Supply Voltage. VCC
High Level Inpu\ Voltage. VIH

Min

Nom

Max

4.S

S

5.5

Unit

V
V

2

Low Level Input Voltage. VIL

0.8

V

High Level Output Current. 10H

-2

mA

Low Level Output Current. 10L

20

mA

Max

Unit

-1.2

V

~

Electrical Characteristics
All typical values are measured at Vee
Symbol

over recommended operating free air temperature range.

=5V, TA =2S·C.

Parameter

Conditions

VIK

Input Clamp Voltage

VCC

VOH

High Level Output
Voltage

10H ~ -2mA
VCC 4.SV to 5.5V

VOL

Low Level Output
Voltage

VCC

~

4.SV, 10L

~

20mA

II

Max High Input Current

VCC

~

S.5V, VIH

~

7V

High Level Input Current

IIH

Low Level Input Current

IlL

~

4.SV.

Typ

Min
Ii'~

-18mA

V

VCC-2

=

VCC = 5.SV. VIH ~.2.7V

0.35

Select

0.2

All Others

0.1

Select

40

All Others

20

Select

VCC = S.5V.
VIL =,O.4V

.-1

10

Output Drive Current

VCC = S.5V

Vo = 2.25V

ICC

Supply Current

VCC = 5.5V.

54/74AS157
54/74AS158

mA

/JA
mA

-112

mA

17.5

28

mA

15.6

22.5

mA

-30

/

3-67

V

-0.5

All others

I

O.S

~
,...

~

'AS157 Switching Characteristics over recommended operating free air temperature range (Note 1)
All typical values are measure<;l at Vee = 5V, T A = 25°C.

~
:E

Symbol

Parameter

CO

tpLH

Propagation Delay Time,
Low to High Level Output

Data

Y

tpHL

Propagation Delay Time,
High to Low Level Output

Data

Y

tpLH

Propagation Delay Time, Strobe
Low to High Level Output

....:
it)
,...

tpHL

~
:E'

-,....
o

it)

~
:E

o

~

:E

o

Conditions

1

7.5

1

6

ns

1

6.5

1

5.5

ns

Y

2

12.5

2

10.5

ns

Propagation Delay Time, Strobe
Hi.gh to Low Level Output

Y

2

8.5

2

7.5

ns

tpLH

Propagation Delay Time, Select
Low to High Level Output

Y

2

12

2

11

ns

tpHL

Propagation Delay Time,
High to Low Level Output

Y

2

12

2

10

ns

Select

Typ

Typ

Max

Units

Min

Vee=4.5V to 5.5V,
C L =50 pF,
RL =5000

Min

DM74AS157

Max

~

o
[,...i;

\ DM54AS157

To
From
(Input) (Output)

,

'AS158 Switching Characteristics over recommended operatin~ free air temperature range (Note 1)
All typical values are measured at Vee=5V, TA = 25°C.
From
To
(Input) (Output)

Symbol

Parameter

tpLH

Propagation Delay Time,
Low to High Level Output

Data

Y

tpHL

Propagation Delay Tillie,
High to Low Level Output

Data

Y

tpLH

Propagation Delay Time, Strobe
Low to High Level Output

Y

tpHL

Propagation Delay Time, Strobe
High to Low Level Output

tpLH

Propagation Delay Time,
Low to. High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

Conditions

DM54AS158

1

6

1

5

ns

1

5.5

1

4.5

ns

2

8

2

6.5

ns

Y

2

11.5

2

Select

Y

2

11

2

Select

y

2

11.5

2

Note 1: See Section 1 for test waveforms and output load.

3-68

Typ

Max

Units

Min

\

Typ

DM74AS1.58

Max

Vee = 4.5V to 5.5V,
C L =50 pF,
RL =5000

Min

10
9.5
10

ns
ns
ns

c

3:
(J1

Logic Diagrams

01=00

AS157
AI 2

.....

....,

AI

(J1

VI

VI

BI 3

A2

»en

AS158

BI

C

3:
~

5

»
en
.....

A2

~ 6

(J1

~

A3 II

A3

B3 10

B3

A4 14

~

B4 13

84

~....,

C

II

3:
(J1
~

»en

10

.....
(J1

-

14

00

C

3:
~

13

»en

SELECT

.....

(J1

STROBE

TL/F/6290·2

00
TL/F/6290·3

3-69

~r-----------------------------------------------------------------------------~

CD

~ ~National
~
Semiconductor
~

a

~ DM54AS/DM74AS160, 161, 162, 163
~

Synchronous Four-Bit Counters

Ll)

General Description

~

:2:

e

N

~

en



t;>

~

i.

CI)

E

f!C)

CIS

i5
.2
C)
o
---1

;'l

~

DM54AS160/DM74AS160, DM54AS161/DM74AS161, DM54AS162/DM74AS162, DM54AS163/DM74AS163
ro

ta

(;'

c

iii'

ta
~
:.0

;;

~

n.

~

~

c:::I

~

- -

~

~

t7 ~

§

~

t--

=
0'

r;;

--i

r-

::;;

~

;;.;

-9
~~

U

~:
9

0

~

;r-

;; =
0'

~
0

L7
;;;

R

o

~

:l

5'

t:

~

...:a-...
'"

1/1

t--

+

3
oo

'"

~

f

~

5

"i7

~7

U

~

-

N

;

;:

t--

0--

+

~:,= ~r- ~:, =~r0

L-

U
;;;

-

iL0

1"

DM54AS1601 DM74AS160, DM54AS161/DM74AS161, DM54AS1621 DM74AS162, DM54AS163/DM74AS163

.,.

~

""

8

~~~~
)

0)

rr

...

N
CD

II)

C

s

Q)

::J

.S

c:0

2fn

E

!

en

.!

"

t
~

:!

'"
'"u:

...

't'
~

!II

'"
Coo>

--i

r::

."

~
~

'"

§~

;;;

8'

'"

;;;

8

"

.~

r---------------------------------------------------~------------,C

~National

s:

DM54AS/DM74AS168,1e9
Synchronous Fo~r Bit Up/Down Counters

-s:

D

.
Semiconductor

General Description

~......

en
co
C

up/down) which modify the operating mode have no effect
until clocking occurs. The function of the counter (whether
enabled, disabled,loading or counting) will be dictated solely by the conditions meeting the stable setup and hold
times.

These synchronous presettable counters feature an internal carry look ahead for cascading in high speed counting
applications. The AS168 is a four-bit decade up/down
counter and the AS169 is a four-bit binary up/down counter.
The carry output is decoded to prevent spikes during normal mode of counting operation. Synchronous operation is
provided so that outputs change coincident with each other
when so instructed by count enable inputs and internal gating. This mode of operation eliminates the output counting
spikes which are normally associated with asynchronous
(ripple clock) counters. A buffered clock input triggers the
four flip-flops on the rising (positive going) edge of clock
input waveform.

•

These counters are fully programmable; that is, the outputs
may each be preset either high or low. The load input circuitry allows loading with carry-enable output of cascaded
counters. As loading is synchronous, setting up a low level
at the load input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse.
The carry look-ahead circuitry permits cascading counters
for n-bit synchronous applications without additional gating. Both count enable inputs ( P and i ) must be low to
count. The direction of the count is determined by the level
of the up/down input. When the input is high, the counter
counts up; when low, it counts down. Input T is fed forward
to enable the carry outputs. The carry output thus enabled
will produce a low level output pulse with a duration approximately equal to the high portion of the QA output when
counting up, and approximately equal to the low portion of
the QA output when counting down. This low level overflow
carry pulse can be used to enable successively cascaded
stages. Transitions at the enable Pori inputs are allowed
regardless of the level of the clock input.

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.

•

Functionally and Pin-for-Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.

•

Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.

•
•
•

Synchronously Programmable.
Internal Look Ahead for Fast Counting.
Carry Output for N-bit Cascading.

•
•

Synchronous Counting.
Load Control Line.

•

ESD Inputs.

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS
DM74AS
Storage Temperature Range

(Note 1)
7V
7V

-55°C to 125°C
O°C to 70°C
-65°C to 150°C

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

OUTPUTS

CARRY - - - - - - - - . ENABLE
Vcc OUTPUT QA
QB
Qc
QD
T LOAD

116

115

114

113

112

111

110

9

Dual·ln·Line Package

r

RIPPLE QA
CARRY
OUTPUT
UP/DOWN
CK
A

2
U/O

CK

QB

QD ENABLE

54AS168 (J)
54AS169 (J)

T
LOAD

B

B

D

C

4

3
A

Qc

5
C

6
D

------~---DATA INPUTS

ENABLE
ji

7

Is

ENABLE GND

ji

3·77

TLiF/6292·1

~

,~
......

-ms:
c

~

m

Connection Diagram
RIPPLE

U1

~
......

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
nol be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute

The control functions for these counters are fully synchronous. Changes at control inputs (enable P, enable i, load,

......
en
!»
c

s:

Features
•
•

~
»en

74AS168 (J,N)
74AS169 (J,N)

Recommended Operating Conditions
DM74AS168,169

DM54AS168,168
Parameter
Supply Voltage
High Level Input Voltage, VIH

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

2

Low Level Input Voltage, VIL
High Level Output Current, 10H

·Unit
V
V

0.8

0.8

V

-2

-2

mA

20

20

mA

75

MHz

/

Low Level Output Current, 10L
0

Clock Frequency, fCLOCK

tsetup, Set-up time

Data;
A,B,C,D

0

10

8

ns

10

a

ns

LO!jd

10

8

ns

UfO

10

a

ns

2

0

ns

2

0

ns

Load

2

0

ns

UfO

2

0

ns

7.7

6.7

ns

En P, En

thold, Hold time

65

T

Data;
A,B,C,D
En P, En

T

Width of Clock Pulse, TW

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25"C.
Symbol

Parameters

Conditions

Min

: VCC =. 4.5V, II = -1amA

VIK

Input C!amp Voltage

VOH

High Level Output
Voltage

10H = -2mA
VCC = 4.5V to 5.5V

VOL

Low Level Output
Voltage

VCC = 5.5V, 10L = 20mA

II

Max High Input Current

VCC = 5.5V,
VIH = 7V

VCC = 4.5V
VIH = 2.7V

IIH

IlL

High Level Input Current

Low Level Input Current

Typ

VCC = 5.5V
VIL = O.4V

Max

Unit

-1.2

V
V

VCC-2

0.35

0.5

V

Load, ENT, UfO

0.2

rnA

Others

0.1

Load, ENT, UfD

40

Others

20

/LA

CLK, DATA,
ENP

-0.5

rnA

LOAD, EN T

-1

rnA

-112

rnA

63

rnA

UfO

,
10

Output Drive Current

VCC = 5.5V, Vo = 2.25V

ICC

Supply Current

VCC = S.SV

-30
46

3-78

----------------------------~------------------------------------~c

Switching Characteristics

3:

over recommended operating free air temperature range (Note 1).

U1

All typical values are measured at Vcc= 5V, TA =25°C.
DM54AS168,169
Parameter

From

To

Conditions

TpLH, Propagation
delay time. Low to
high level output.
With Load Low

Typ

Max

Min

Typ

Max

Unit

Clock

17.5

3

16.5

ns

Ripple
Carry
2

14

2

13

ns

~
.....

1

7.5

1

7

ns

$I)

c

3:

Clock

AnyQ

VCC = 4.5
to 5.5V
RL = 500!l
CL = 50 pF

U1

~.....

0)

14

ns

2

TpLH. Propagation
delay time. Low to
high level output.

1.5

10

1.5

9

ns

1.5

10

1.5

9

ns

2

14

2

12

ns

2

14.5

2

13

ns

2

13

CD

c
3:

En T

TpHL. Propagation
delay time. High to
low level output.

TpHL. Propagation
delay time. High to
low level output.

~

0)

TpHL. Propagation
delay time. High to
low level output.

TPLH. Propagation
delay time. Low to
high level output.

.-c
()C)

MHz

75

~.....

.0)

3:

3

TpHL. Propagation
delay time. High to
low level output.
TpLH. Propagation
delay time. Low to
high level output.

Min

65

fmax,
Max. clock freq.

DM74AS168,169

ufo
(Note
2)

~
l>

en
.....

Ripple
Carry

Ripple
Carry

NOTE 1: See Section 1 for test waveforms and output load.
NOTE 2: Propagation delay time from up/down to ripple carry must be measured with the counter at either a minimum or a maximum count. As the logiC level
of the up/down input IS changed. the ripple carry output will follow. If the count is minimum (0), the ripple carry output tranSition will be In phase. If the count is
maximum (9 for AS168 or 15 for AS169). the npple carry output will be out of phase.
.

3-79

0)

CD

fB
,..

~

Logic Diagrams
DM54AS/DM74AS168

~
Q

0)

U/O

co
,..

~

! "v

~

U)

~
Ll)

1,1~~_

~
Q

[I'\1AA

CLOCK

3
1

~J-.

+,

4 BIT OECADE

4

Hl~J.-,
~
0

~

P

13

..yo.

11

OC

~

5

,

"

b

7

=~J-.
~
o

v

_ 10
T

"

o·

CLKt-'

~

DATA 0

"

V

»-

~

lOA 0

,."

V

UP,OOWNCQUNTER

OATH

"

"

54A$16B

DATAB

v

~
"...

0

r-:r

"

II

00

0

ClK

en
.....
en

DM54AS/DM74AS 169

U/D

I

~

OATAA

CLOCK

0'

J

>
en
.....

ENP

o
3:

..["'}o..IJ
V

08

..d

0

t---<

'--

~

bY-

~

ClK

~1-

-t>---1

~
v 00

~

L

"

~
"

00

'l~"
l

~

0

ClK

~lw~r

J

54A.S 159
4 81T BINARY
UP/DOWN COUNTER

DAlAB

-o3:
00

.!...{>c>L;::

~National

a

PRELIMINARY

Semiconductor

DM54AS/DM74AS174,175
Hex/~uad D Flip-Flops with Clear
General Description
•

These positive-edge-triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic. Both have an asynchronous clear input, and the quad (175) version features complementary outputs from each flip-flop.

•

Information at the D inputs meeting the setup time requirements is transferred to the outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is
at either the high or low level, the D input signal has no effect at the output.

a

a

a

Absolute MaXimum Ratings (Note 1)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
OM54AS 174/175
OM7 4AS 17 4/175
Storage Temperature Range
Lead Temperature
(Soldering, 10 seconds)

Features
•

54AS174 contains six flip-flops with separate D inputs
and outputs.
54AS175 contains four flip-flops with separate 0
inputs and both and Q outputs.

Advanced Oxide-Isolated lon-Implanted Schottky TTL
Process.

7V
7V
-55°C to 125°C
O°C to 70°C
-65~C to 150°C

Nola 1: The "Absolule Maximum Ratings" are Ihose values beyond
which Ihe safely of Ihe device can nol be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Eleclrical Characteristics" table are nol guaranleed al the absolute
maximum ratings. The "Recommended Operallng Conditions" lable will
define Ihe conditions for aclual device operallon.

•

Pin and Functional compatible with LS and Schottky
family counterpart.
• Switching performance guaranteed over full
temperature and VCC supply range.
.

Connection Diagrams
Dual-In-Line Package
Vee

Vee

Q6

06

05

05

04

CLEAR

01

01

02

02

03·

Q4

CLOCK

03

GNO

,.

TL/F/6293-1

Inputs
Clock

L
H
H
H

X
1
L

D4

"

54AS175 (J)

Function Table
Clear

Dual-In-Llne Package

'Oi

74AS174 (J,N)

54AS174 (J)

,.

"

".

"

"

"

CLOCK

'"
TLlF/6293-2

74AS175 (J~N)

Outputs

Q*

D

Q

X

L
L
H
H
L
L
00 . 00

H
L

X

This document contains Information on

H - high level (sleady slale)
L - low level (sleady slale)
X = don't care
r = transition from low to high level

00 - Ihe level of

a before Ihe indicaled

steady-state input conditions were

eslablished .
• applies 10 54AS175/74AS175 only

a product under development. NSC reserves the right to change or discontinue this product without notice.
3-82

c

s:
CJ1

Recommended Operating Conditions
DM74AS174,175

DM54AS174,175
Parameter
Supply Voltage, VCC

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Unit

~

en
......

V

-s:
l>

V

~

C

High Level Input Voltage, VIH

2

2

Low Level Input Voltage, VIL

0.8

0.8

V

High'Level Output Current, 10H

-2

-2

mA

Low Level Output Current, 10L

20

20

mA

Pulse Width, tw

Clock High

4

4

Clock Low-AS174

6

6

5

3

5.5

5

Clock Low-AS175
Clear
Setup Time, tSETUP
Data Input

Data-AS174

4

4

Data-AS175

3

3

Clear Inactive State

6

6

ns

~

en
......

~
C

s:
CJ1
~

en
......
......

-s:
CJ1

C

ns

~

G;
......
......

CJ1
Hold Time, tHOLD
Data Input

1

Clock frequency, fCLOCK

0

,1

100

ns

100

0

MHZ

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25°C.
Parameter

Conditions

VIK

Input Clamp Voltage

VCC=4.5V, liN = -18mA

VOH

High "-evel Output
Voltage

VCC =4.5V to 5.5V, I OH = - 2mA

VOL

Low Level Output
Voltage

VCC = 4.5V
10L = 20mA

Input Current at
Max Input Voltage

VCC = 5.5V, VIN = 7V

0.1

mA

II
IIH

High Level Input
Current

VCC = 5.5V, VIN = 2.7V

20

/LA

IlL

Low Level Input
Current

VCC = 5.5V, VIN = 0.4V

-0.5

mA

10

Output Drive Current

VCC = 5.5V, V = 2.25V

-112

mA

ICC

Supply Current

VCC = 5.5V

30

45

mA

22.5

34

Symbol

Min

Typ

.
VCC- 2

-30

AS175

3-83

,

Unit

-1.2

V
V

VCC-1.6

0.35

AS174

Max

0.5

V

U)r---------------------------------------------------------------------------.....
,... Switching Characteristics over recommended operating free air temperature range (Note 1).
~

All typical values are measured at Vee = 5V, T A = 25°C.

r:!:

:e
o

-.....,...U)

~
:e
o

t,...

0'

Parameter

Conditions

r:!:

~
,...

~

:e
o

74AS174,175

54AS174,175

Min

Typ

Max

100

fMAX, Maximum
Clock Frequency

Min

Typ

Unit

Max

MHz

105

5

15

5

14

ns

5

15

5

14

ns

tpLH. Propagation Delay Time,
Low to high Level Output
From Clock

3.5

9.5

3.5

8

ns

tpHL, Propagation Delay Time,
High to low Level Output
From Clock

4.5

11.5

4.5

10

, ns

tPLH, Propagation Delay Time,
Low to high Level Output
From Clear (175 Only)
RL = 500n
CL = 50pF
VCC = 4.5
to 5.5V

tPHL, Propagation Delay Time,
High to low Level Output
From Clear

 CLOCK

'02
D3

6

03

12

0

10

03

CLOCK
04

1D

11

11

04

CLEAR

04

"

13

CLOCK

13

Qa

Q 15

04

14

Q4

CLOCK
CLEAR

CIill
TL/F/6293·4
D6

"

"

06

54AS175/74AS175

CLOCK

cmii

TLlF16293·3

54AS174/74AS174

3-84

c

3:
en

~NatiOnal

;

Semiconductor

en
.....
CO
.....

DM54AS181 BI DM74AS181 B Arithmetic Logic
Unitl Function Generators
General Description
These arithmetic logic units (ALU) /function generators perform 16 binary arithmetic operations on two 4-bit words, as
shown in Tables 1 and 2_ These operations are selected by
the four function-select lines (SO, 51, 52, 53) and include
addition, subtraction, decrement, and straight transfer.
When performing arithmetic l1lanipulations, the internal carries must be enabled by'applying a low-level voltage to the
mode control input (M). A full carry look-ahead scheme is
available in these devices for fast, simultaneous carry generation by means of two cases de-outputs (P and G) for the
four bits in the package. When used in conjunction with the
DM54AS182IDM74AS182 full carry look-ahead circuits,
high-speed arithmetic operations can be performed_ The
typical addition times shown below illustrate how little
time is required for addition of longer words when full carry
look-ahead is employed. The method of cascading AS182
circuits with these ALUs to provide multi-level full carry
look-ahead is illustrated under typical applications data
for the DM54AS1821DM74AS182.
(Continued)

Features

•

Arithmetic operating modes:
Addition
Subtraction
Shift operand A one position
Magnitude comparison
Plus twelve other arithmetic operations

•

:;;!

• Switching specifications guaranteed over full
• temperature and VCC range
• Switching specifications at 500n/50 pF

Advanced oxide-Isolated ion-implanted Schottky TTL
• process

Absolute Maximum Ratings (Note 1)
Supply Voltage
7V
7V
Input Voltage
Operating Free Air Temperature Range
DM54AS
- 55·Cto + 125·C
O·Ct070·C
DM74AS
-65·Cto + 150·C
Storage Temperature Range
Note 1: The "Absolute Maximum Ratings" BiB those values beyond
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Pin Designations

24

23

22

B2
21

A3 B3' , G CnH P A-B F3'
20

,9

18

,17

16

15 14

;<

I

,BO

DeSignation

Pin NOI.

Fu~ctlon

M, A2, AI. AO

19,21,23,2

Word A Inputs

83,82,81,80

18,20,22.1

S3, 52, 51, SO

3,4,5,6

Cn

7

Inv. Carry Input

M

B

Mode Control
Input

F3, F2, Fl, FO

13, 11, 10,9

Function Outputs

A=8

14

Comparator Output

p

15

Cn+4

16

Inv. Carry Output

G

17

Carry Generate
Output

VCC

24

Supply Voltage

GND

12

Ground

OUTPUTS

INPUTS

A2

13

C>-

2
AO

3

4

S3 .52

5

7

6

SO Cn

$1

INPUTS

8
M

9
FO

10
F1

11J12
F2 GND

.~

OUTPUTS
TlIFI6295-I

54AS181 B (J)

74AS181 B (J, N)

Number Typical Addition
Times Using
of
AS181B & AS882
Bit.

110 4
5 t08
91016

17 to 64

3:

Logic function modes:
EXCLUSIVE-OR
Comparator
-,
AND,NAND,OR,NOR
Plus ten other logic operations
Full look-ahead for high-speed operations on long words

Dual-In-Line Package
'AI B1

I:D

which the safety of the device can not be guaranteed. The device should

Connection Diagram

vr

-c

5 ns
IOns
14 ns
101 ns

Package Count

Arlthmetlc/
Logic Units

Carry Method

Look Ahead

Between

Carry Generator.

ALU's

0
0
1
2 toS

None
Ripple
Full Look-Ahead
Full Look-Ahead

1
2
30r4

Sto 16

3-85

Word 8 Inpuls
Function-Select
Inputs

Carry Propagate

Output

~
.....

CO

.....

I:D

....

ID
CO
....

~

;:!:
:E

-c....
m

....CO

~:E
c

General Description

(Continued)
\

If high speed is not important, a ripple-carry input (C n) and
a ripple-carry output (C n+4) are available, However, the
ripple-carry delay has also been minimized so that
arithmetic manipulations for small word lengths can be performed withoul external circuitry.

magnitude information. Again; the ALU should be placed in
the subtract mode by placing the function select inputs 53,
52, 5 I, SO at L, H, H, L, respectively.
These circuits have been designed to not only incorporate
all of the designer's requirements for arithmetic operations,
but also to provide 16 possible functions of two Bodlean
variables without the use of external circuitry. These logic
functions are selected by use of the four function-select inputs (SO, S I, S2, S3) with the mode-control input (M) at a
high level to disable the internal carry. The 16 logic functions are detailed in Tables I and II and include exclusiveOR, NAND, AND, NOR, and OR functions.

These circuits will accommodate active-high qr active-low
data, if the pin designations are interpreted as shown
below.
Subtraction is accomplished by l's complement addition
where the l's complement of the subtrahend is generated
internally. The resultant output is A-B-l, which requires
an end-arountl or forced carry to provide A-B.

=

The AS181 B can also be utilized as a comparator. The A B
output is internally decoded from the function outputs (FO,
F I, F2, F3) so that when two words of equal magnitude are
applied at the A and B inputs, it will assume a high level to
indicate equality (A = B). The ALU should be in the subtract
mode with Cn = H when performing this comparison. The
A = B output is open-collector so that it can be wire-AND
connected to give a comparison for more than four bits. The
carry output (C n+4) can also be used to supply relative

Pin Number

2

1

ALU SIGNAL DESIGNATIONS
The TIL S181 and AS181B can be used with the flignal
designations of either Figuro 1 or Figure 2.
The logic functions and arithmetic operations obtained
with signal designations as in Figure 1 are given in Table I;
those obtained with the signal designations of Figure 2
are given in Table II.

23 22 21 20 19 18

9

10 11 13

7

16

15 17

Active-High Data (Table I)

AO BO AI Bl A2 B2 A3 B3 FO Fl F2 F3 Cn Cn+4 X

y

Active-Low Data (Table II)

AO BO AI Bl A2 B2 A3 B3 FO Fl F2 F3 Cn Cn+4 P

G

Input
Cn

Output
Cn+4

H
H
L
L

H
L
H
L

Active-High Data Active-Low Data
(Figure 1)
(Figure'2)
A:$B
A>B
AB
A:$B

c
General Description

s::

(Continued)

~
....CO

(J)

TT

(7)-rc

AO 80
Cn

(23)(22)

(21) (20)

A2

82

FO

It

F1

(1~)

F2

F3

Cn +4

r--(

4)

x

V

(,1,) (1~)

(Xl 1'171'15) ,
Cr)(1r
1 )1 TT
'3

'4 )

vo xo

113j'=

v,

XI

V2 X2

TT
Y3 X3

x-(7)
AS1b2

Cn

V-(10)

cn+y

C n+ x

(Xl

Cn+ z

,l

(X)

TLfF/6295·2

Figure l'

-s::
to

Active High Data

A3 83

A=B

....

Table I

I I II II
Al 81

AS181 B or 5181

18)- r--"

(19) (18)

M=H
Logic
S3 S2 S1 SO Functions
Selection

F=A
F=A+B
F = AB
F=O
F = AB
F=S

F=A
F=A+B
F=A+S
F = Minus 1 (2's Compl)
F'= A Plus AS
F = (A + B) Plus AS

H

L

F=AEBB F = A Minus B Minus 1

H
L

H F = AS
F = AS Minus 1
L F = A+B F = A Plus AB

L
L
L
L
L
L

L
·L
L
L
H
H

L

H

L
H

H
l

H

L

L

H F=AEBB F = A Plus B

H
H
H
H
H
H

L
L
H

H
H
L
L
H
H

L
H
L
H
L
H

H
H
H

F=B
F = AB
F= 1
F=A+S
F=A+B.
F=A

Cn = L (with carry)

Cn = H (no carry)

L
H
L
H
L
H

L
L
H
H
L
L

C

M = L; Arithmetic Operations

F
F
F
F
F
F

=
=
=
=
=
=

I

F
F
F
F
F
F

=
=
=
=
=
=

A Plus 1
(A + B) Plus 1
(A + S) Plus 1
Zero
A Plus AS Plus 1
(A + B) Plus AS Plus 1

F = A Minus B
F = AS
F = A Plus AB Plus 1
F = A Plus B Plus 1

(A + S) Plus AB
AS Minus 1
A Plus A'
(A + S) Plus A
(A + S) Plus A
A Minus 1

I

F = (A + S) Plus AB Plus 1
F = AB
F = A Plus A Plus 1
F = (A + S) Plus A Plus 1
F = (A + S) Plus A Plus 1
F=A

• Each bit is shifted to the next more significant pOSItion.

(r 1)
17)- ......

AO BO
Cn

(I)

'r (!) 'f) cA' cr
l

A1

B1

A2

82

1810RS1fJ1
QRA5181B

(8)- - M
FO

,I)

Fl

F2

F3 Cn+4

II!)

11~)

J) )6)

}3t-)T
GO PO

A=B

G

l'iii

Active'Low Data

r--

(14)

P

l17l'5)

T'tt T!

Gl PI

G2 P2

G3 P3

P
Cn

Table II

l

Al 83

:>-17)

AS1b2

Cn+x

cn+y

Cn +z

(1t

),)

It

G C>-ll0)

TLlF/6295·3

Figure 2

Selection

M=H
Logic
S3 S2 S1 SO Functions
L
L
L
L
L
L

L L
L L
L 'H
L H
H L
H L

M = L; Arithmetic Operations
' Cn = L (no carry)

L
H
L
H
L
H

F=A
F = AB
F=A+S
F= 1
F=A+B
F=S

F=AEBS F = A Minus B Minus 1

F
F
F
F
F
F

=
=
=
=
=
=

A Minus 1
AS Minus 1
AS Minus 1
Minus 1. (2's Compl)
A Plus (A + S)
AS Plus (A + S)

L

H

H

L

L
H

H
·L

H
L

H F=A+S F=A+S
F = A Plus (A + S)
L F =AS

H

L

L

H F=AEElB F = A Plus B

H
H
H
H
H
H

L
L
H
H
H
H

H
H
L
L
H
H

L
H
L
H
L
H

F=B
F=A+B
F=O
F = AS
F = AS
F=A

F = AS Plus (A + B)
F=A+B
F = A Plus A'
F = AS Plus A
F = AS Plus A
F=A

• Each bit is shifted to the next more significant position.

3·87

Cn = H (with carry)
F=A
F = AB
F = AS
F = Zero
F = A Plus (A + S) Plus 1
F = AB Plus (A + S) Plus 1
F = A Minus B
F = (A + S) Plus 1
F = A Plus (A + S) Plus 1
F = A Plus S Plus 1
F
F
F
F
F
F

=
=
=
=
=
=

AS Plus (A + B) Plus 1
(A + B) Plus 1
A Plus A Plus 1
AB Plus A Plus 1
AS Plus A Plus 1
A Plus 1

~

l>

....

(J)

....

CO

to

m
....

....

co

~
r!

:E

Recommended Operating Conditions
54AS181B

Parameter

74AS1818

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Unit

-m....

Supply Voltage, VCC

~
:E

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Current, IOH All Outputs except
A=BandG

-2

-2

mA

-3

-3

20

20

48

48

5.5

5.5

Q

....

High Level Input Voltage, VIH

2

2

'1/

V

co

Q

G
Low Level Output Current, IOL All Outputs except
G

G
High Level Output Voltage, VOH
(A=BOnly)

mA

Electricai Characteristics over recommended operating free air temperature range.
All typical values are measured at Vcc = 5V, TA = 25°C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.5V, II = -18 mA

VOH

High Level Output
Voltage

IOH'= -2mA

Any Output
exceptlA=B

IOH = -3mA

G

Min

IOH

High Level Output
Current (A = B)

VCC = 4.5V, VOH = 5.5V,

VOL

Low Level Output
Voltage

VCC = 4.5V,
IOL = 20mA

II

IIH

Max High Input Current

High Level Input Current

Any Output
except G

Typ

Max

Unit

-1.2

V
V

VCC-2

2.4

3.4

0.3

0.4

100

p.A

0.5

V

0.5

IOL=4BmA

G

Vcc=Max,
VIH = 7V

Mode

0.1

AnyAor B

0.3

S

0.4

Carry

0.6

Mode
Input

20

AnyS
Input

80

Any Aor B
Input

60

Carry
Input

120

Vcc=Max,
VIH = 2.7V ,

3-88

mA

p.A

c

Electrical Characteristics

(Continued) over recommended operating free air temperature range.

~

All typical values are measured al Vee = 5V, TA = 25·C.
Symbol

Parameter

Conditions

IlL

Low Level Input Current

VCC=Max,
VI =0.5V

:s:
en
»
C/)

Max

Unit

Mode
Input

-0.5

mA

AnyS
Input

-2

Min

Typ

""'"
CO

""'aJ"
C

•

10'

Output Drive Current

VCC = 5.5V

ICC

Supply Current

VCC = 5.5V

Any A or B
Input

-1.5

Carry
Input

-2.5

-30

Va = 2.25V

:s:
~
»C/)
""'"
CO

""'aJ"

-112

mA

104

mA

70

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V, TA = 25·C.

Sym

tPLH

Parameter

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tPHL

Propagation Dalay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tPHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tPHL

Propagation Delay Time,
High-to-Low Level Output

tPLH

Propagation Delay Time,
Low-to-High Level Output

tPHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tPHL

Propagation Delay Time,
High-to-Low Level Output

From
(Input)

Cn

To
(Output)

DM74AS181B

Min

Typ

Max

Min

Typ

Max

2

7

11

2

7

9

2

7

11

2

7

9

2

8

14

2

8

12

2

8

14

2

8

12

2

8

20

2

8

16

2

8

20

2

8

16

M = OV
(5UM or

3

6

11

3

6

9

DIFF mode)

3

6

11

3

6

9

2

5

9

2

5

7

2

5

9

2

5

7

2

6

12

2

6

9

2

6

12

2

6

9

2

6

11

2

6

8

2

6

11

2

6

8

2

6

13

2

6

10

2

6

13

2

6

10

Units

ns

Cn+4

Any A
or B

Cn+4

Any A
or B

Cn+4

Cn

Any F

Any A
orB

DM54AS181B

Conditions
(Note 2)

G

Any A
or B

G

Any A
or B

P

Any A
or'B

P

M = 0 V, so =
53 = 4.5 V
51 = 52 = a V
(5UM mode)
M = a V, 50 =
53 = a V
51=52=4.5V
(DIFF mode)

M = a V, so =
53 = 4:5 V
51 = 52 = a V
(5UM mode)
M = a V, 50 =
S3 = a V
51 =52=4.5V
(D!FF mode)
M = a v, 50 =
53 = 4.5 V
51 = 52 = a V
(5UM mode)
M = a V, 50 =
53 = a V
51 =52=4.5V
(DIFF mode)
3-89

ns

ns

ns

ns

ns

ns

ns

•

Switching Characteristics (Continued)

over recommended operating free air temperature range (Note 1).

All typical values are measured at vcc = 5V, T A = 2SoC.
Sym

tpLH

From
(Input)

Parameter

Propagation Delay Time,
Low·to·High Level Output

tPHL

Propagation Delay Time,
High-to·Low Level Output

tpLH

ProPagation Delay Time,
Low-to-High Level Output

tPHL

Propagation Delay Time,
High·to·Low Level Output

tPLH

Propagation Delay Time,
Low·to·High Level Output

tPHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation'Delay Time,
Low-to·High Level Output

tPHL

Propagation Delay Time,
High·to·Low Level Output

To
(Output)

Conditions
(Note 2)

-

Ai or Bi

Ai or Bi

Any A
or B

Fi

Fi

Fi

A=B

I

DM74AS181B

Typ

Max

Min

Typ

Max

2

5

11

2

5

8

2

5

11

2

5

8

2

6

12

2

6

10

2

6

12.

2

6

10

2

6

16

2

6

11

2

6

16

2

6

11

4

14

26

4

14

21

4

14

26

4

16

21

=

Ai or Bi

DM54AS181B

Min
M 0 V, so =
S3 = 4.5 V
SI = S2 = 0 V
(SUM mode)

ns

M = OV, SO =
S3 = OV
SI =S2=4.SV
(DIFF mode)

ns

M = 4.5 V
(logic mode)

I'Is

M = 0 V, SO =
S3 = 0 V
SI =S2=4.SV
(DIFF mode)

ns

Note 1:. See Section 1 for test wave/arms and output load.
Note 2: VCC =4.5V to 5.5V, CL =50 pF (15 pF for A =B), R L =500!2 (28011 for A =B).

Logic Diagram

13'

53'4}
52 {51
; ; (61

)o-.,-----:'~17' Gor"

s'-+---+++-H-+
{lSI

"SI

"""',,,:::-,--++++'--1
')-~--::""'31 F3

., "'",::-,--++++---1

i'-+---+++-H-+
1221

" _ _-++++---1
(23)

L.:H~L;rtt-----::l1r::.J.+-~(IO' Fl

so -+---++--f-+
'"

(91

fa

.,"",,,-----+--I
":::-,8I~~-------------~-~
________________

c.~",

~

3-90

Units

TLlF16295·4

Vee '" PIN 24
GNP:: PIN 12

~---------------------------------------------------------------------'C

s:
U1

Parameter Measurement Information

~....

Logic Mode Teat Table
Function Inputa: S1 = S2 =.M = 4.5 V, SO = S3 = 0 V

....

co

Parameter

tPLH
tPHL
IPLH
tPHL

Input
Under
Teat

Ai

Bi

Other Input
Same Bit

Other Data Inputs

Output
Waveform

Apply
GND

Apply

4.5 V
Bi

None

None

Remaining
AandB,C n

Fi

Out·ol-Phase

Ai

None

None

Remaining
Aand B, Cn

Fi

Oul-ol-Phase

Appl!

4.5 V

Apply
GND

-s:
OJ

Output
Under
Test

C

:iio!

1:;
....

....coOJ

SUM Mode Teat Table
Function Inputa: SO = S3 = 4,5 V, S1 = S2 = M = 0 V

Parameter

IPLH

Other Input
Same Bit

Input
Under
Test

Apply

4.5 V

Apply
GND

Ai

Bi

tPLH

Bi·

tPLH

Apply

None

Remaining
A and B

Cn

Fi

In-Phase

Ai

None

Remaining
A and B

Cn

Fi

In-Phase

Ai

Bi

None

None

Remaining
Aand B, Cn

P

In-Phase

Bi

Ai

None

None

Remaining
AandB, Cn

P

In-Phase

Ai

None

Bj

Remaining Remaining
B
A,C n

G

In-Phase

Bi

None

Ai

Remaining Remaining
A,C n
B

G

In-Phase

Cn

None

None

Any F
orCn+4

In-Phase

Ai

None

Bi

Remaining Remaining
A,C n
B

Cn+4

Oul-ol-Phase

Bi

None

Ai

Remaining Remaining
A,C n
B

Cn+4

Oul-ol-Phase

tPHL
tPLH
tpHL
tPLH
tPHL
'lpLH

All
A

IPHL
IPLH
IPHL
tPLH
IPHL

Output
Waveform

4.5 V

tPHL
tPLH

Output
Under
Test

Apply
GND

IPHL

tPHL

Other Data Inputs

3-91

All
B

•

~.---------------------------------------------------------~------.

,..
~

Parameter Measurement Information

~

(Continued)

5iFF Mode Teat Table

t:!:
:E
c

Function Inputa: S1

,..
CO
,..
~

Parameter

~

tPLH

Input
Under
Teat

=S2 =4.5·V,.SO =S3 =M =0 V

Other Input
Same Bit
Apply
4.5 V

Apply
GND

c

tPLH

tpHL
tPLH

Ai

None

Remaining Remaining
B,C n
A

Fi

Out·ol·Phase

Ai

None

Bi

None

Remaining
AandB,C n

P

In· Phase

Bi

Ai

None

None

Remaining
AandB,C n

P

Out·ol·Phase

Ai

Bi

None

None

Remaining
AandB,C n

G

In·Phase

Bi

None

Ai

None

Remaining
AandB,Cn

G

Out·ol·Phase

Ai

None

Bi

Remaining Remaining
A
B,.C n

A=B

In·Phase

Bi

Ai

None

Remaining Remaining
B,C n
A

A=B

Out-ol-Phase

Cn

None

None

All
Aand B

None

Cn+4
or any F

In-Phase

Ai

Bi

None

None

Remaining
A,B,C n

Cn+4

Out-ol-Phase

Bi

None

Ai

None

Remaining
A,B,C n

Cn+4

In-Phase

tPHL
tPLH
tPHL
tPLH
tpHL
tPLH
tPHL
tPLH

In·Phase

Bi

tPHL
tPLH

Fi

Bi

tPHL
tPLH

.

.Output
Waveform

None

tPHL
tPLH

Apply
'GND

AI

tPHL
tPLH

Apply
4.5 V

Output
Under
Teat

Remaining Remaining
B,C n
A

tPHL

:E

Other Data Inputa

tPHL

\

)'

3-92

~NatiOnal

PRELIMINARY

Semiconductor

DM54AS182/DM74AS182 Look·Ahead Carry Generators
General Description

Features

These circuits are high-speed, look-ahead carry generators, capable of anticipating a carry across four binary
adders or groups of adders. They are cascadable to per·
form full look-ahead across n-bit adders. Carry, generatecarry, and propagate-carry functions are provided as
shown in the pin designation table.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full
temperature and Vcc range

When used in conjunction with the AS181B arithmetic
logic unit, these generators provide high-speed carry lookahead capability for any word length. Each AS182 generlites the look-ahead (anticipated carry) across a group of
four ALUs and, in addition, other carry look·ahead circuits
may be employed to anticipate carry across sections of
four look·ahead packages up to n·bits. The method of cas·
cading circuits to perform multi-level look·ahead is illustrated under typical application data.
Carry input and output of the ALU's are in their true form,
and the carry propagate (P) and carry generate (G) are in
negated form; therefore, the carry functions (inputs, outputs, generate, and propagate) of the look-ahead gener·
ators are implemented in the compatible forms for direct
connection to the ALU. Reinterpretations of carry functions,
as explained on the 181 data sheet are also applicable to
and compatible with the look-ahead· generator. Positive
logic equations for the AS182 are:

• Advanced oxide·isolated, ion'implanted Schottky TTL
process
• Offers carry functions in a compatible form for direct
connection to the ALU
• Cascadable to perform look·ahead across n-bit adders
PNP inputs reduce input loading

•
•

Improved AC performance over Schottky at reduced
power consumption

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
Storage Temperature Range

7V
5.5V
- 65'Cto 150'C

Note 1: The "Absolute Maximum Ratings" are. those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Cn+ x = GO + PO Cn
Cn+ y = ~1 + ~1 ~O + ~1 ~O ~n
Cn+ z = G2 + P2 Gl + P2 P1 GO + P2 P1 1>0 Cn
G= G3(1)3 + (2) (1)3+ 1>2 +(1) (1)3+1>2 +1>1 + GO)
1>=1>31>21>11>0

Connection Diagram

Pin DeSignations

Dual·ln·Line Package
INPUTS

,
vCC

P2
15

116

G2

OUTPUTS

, ,
Cn

14

13

Cn + x Cn +y
12

,

G

11

10

9

2
P1

3
GO

4

PO

\

5
G3

GO, G1, G2, G3 3,1,14,5
PO, PI, P2, P3 4,2,15,6

Active Low
Carry Propagate Inputs

Cn

13

Carry Input

12,11,9

Carry Outputs

G

10

Active Low
Carry Generate Output

P

7

Active Low
Carry Propagate Output

18

VCC

16

Supply Voltage

P
GND
"OUTPUT

GND

8

Ground

6
P3

Function
Active Low
Carry Generate Inputs

r-

1

Pin Nos.

Cn+ x, Cn+ y,
Cn+ z

rc

G1

Designation

Cn + z

7

INPUTS
TL/F/6296-1

54AS182(J)

74AS182 (J, N)

ThIs document contains information on a product under de~elopment. NSC reserves the right to change or discontinue this product without notice.

3-93

Recommended Operatillg Conditions
Symbol

DM54AS182

Parameter

DM74AS182

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

Units

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

IOH

'High Level Output Current

-2

-2

mA

10L

Low Level Output Current

20

20

mA

2

V
V

2
0.8

0.8

V

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25°C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VOH

High Level Output Voltage

10H= -2mA

VOL

Low Level Output Voltage

Vee = 4.5V, IOL = 20 mA

II

Max High
Input Current

Vee ';'5.5V, VIH=~V

P3

Min

Typ

0.35

C n " P2

Low Level
Input Current

p.A

800
60

Vee= Max, VI=2.7V

P31nput

40

P21nput

60

PO, P1, or
G31nput

80

GO orG2
Input

140

C n Input

p.A

160
-1.5

Vee = Max, VI =0.5V

P31nput

-1

P21nput

-1.5

PO, P1,or
G31nput

-2

GO orG2
Input

-3.5

G1 Input

mA

-4

10

Output Drive Current

Vee =5.5V . '1.0 = 2.25V

lee

Supply Current

Vee=5.5V

-30

-112

mA
mA

Outputs High (1)

16

25

Outputs Low (2)

21

33

Note 1: ICCH is measured with all outputs open, inputs P3 and G3 at 4.SV, and all other inputs grounded.
Note 2:

V

200

400

G1 Input
IlL

0.5

700

G1
Cn Input

V

300

,

GO,G2

High Level
Input Current

Units

V

Vee- 2

PO, P1, G3

IIH

Max
-1.2

Vee=4.5V,II= -18 mA

'eel is..measured with all outputs open, inputs GO, G1, and G2 at 4.5V! and all other inputs grounded.

3·94

c

3:

Switching Characteristics over recommended operating free air temperature range (Note 1).

U1

~
.....

All typical values are measured at Vee = 5V, TA = 25°C.
Symbol
tpLH

From
(Input)

Parameter
Propagation Delay Time,
Low to High Level Output

GO, G1,
G2, G3,
PO, P1,
P2, or P3

C n + x,

G

P

tpHL

Propagation Delay Time,
High to Low Level Output

. tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

GO, G1,
G2, G3,
P1, P2,
or P3

tpLH

Propagation Delay Time,
Low to High Level Output

PO, P1,
P2, or P3

tpHL

Propagation Delay Time,
High to Low Level Output

tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

DM54AS182

To(Output)

C n +. y •
or C n + z

Conditions

Min

Typ

Vee = 4.5V to 5.5V,
C~=50 pF,
R L =500n

DM74AS182

Max

Min

Typ

5

5

5

5

6

6

5

5

5

5

5

5

5

5

5

5

Max

Units
ns

-c
CO
N

3:

~.....

CO

ns

ns

I

Cn

C n + x1
C n + y,
or C n + z

ns

Note 1: See Section 1 for test waveforms and output load.

Function Tables
Inputs

Output

G3

G2

G1

GO

P3

P2

P1

G

L

X

X

X

X
X
X

L

x'

L

X
X

L

L

X

L

L
L

X
X
X

L
L

X
X

X
X
X

L

L

L

Output

Inputs
P3

P2

I P1 I PO

P

I

I

L

L
L
L
L
All Other Combinations

H

L

All Other
Combinations

Output

Inputs

H
GO

PO

Cn

Cn + x

Li

X

X

H

H
L
All Other
Combinations

H

X

L

Inputs
G1

GO

P2

P1

PO

Cn

L

X

X

X
X
X

L

X
X

L

X
X

X
X

L

L

X
X
X

X

L
L

X
X
X

L

L

H

H
L

All Other Combinations

Output

Inputs

Output

G2

Cn + z

G1

GO

P1

PO

Cn

Cn + y

H
H

L

X

X

X
X

L

L

X
X

X
X

H

'X,

L

L

H

H

All Other Combinations

H = High level, L = Low level, X = irrelevant
Any inputs not shown in a given table are irrelevant
with respect to that output •

3·95

H
H
L

N

Nr------------------------------------------------------------------------------,

co
.....
Logic Diagram

~
~

:!1

c
~
.....

(71 P

~

:!1
c

P3

161

G3~(~5)~~+--4~~~L-/

P2 (151

G2--~~--_4~~+_L_/
(14)

Pl
Gl

PO
GO

en

(2)

(1)

(4)

(31

Vee = PIN 16
GND = PIN 8

(13)

TLfFI6296·2

Typical Application
64-BIT ALU, FULL-CARRY LOOK AHEAD IN THREE LEVELS

'AS182, AS881

TUF/6296-3

A and B inputs and F outputs of AS1818 are nol shown.

3-96

r-------------------~---------------------------------------------,c

PRELIMINARY 3:

~National

~

~ Semiconductor

...a.

'DM54AS194/DM74AS194 4-Bit Bidirectional Universal
Shift Register

~

General Description

~
...a.

input. Clocking of the flip·flops is inhibited when both
mode control inputs are low.

These bidirectional shift registers are designed to incor·
porate virtually all of the features a system designer may
want in a shift register. They feature parallel inputs,
parallel outputs, right·shift and left·shlft serial inputs,
operating mode control inputs, and a direct- overriding
clear line. The register has four distinct modes of opera·
tion, namely:

Features
•
•
•
•

Parallel·to·serial, serial·to·parallel conversions
Temporary data latching capability
Parallel inputs and o~tputs
Four operating modes:
Synchronous parallel load
Right·shift
Left·shift
Do nothing
• Positive edge·triggered clocking
• Direct overriding clear

Parallel (broadside) load
Shift·right (in the direction Q A toward QD)
Shift·left (in the direction Qo toward QA)
Inhibit clock (do nothing)
Synchronous parallel loading is accomplished by apply·
ing the four bi!s of data and taking both mode control in·
puts, SO and S1, high. The data are loaded into the
associated flip·flops and appear at the outputs after the
positive transition of the clock input. During loading,
serial data flow is'inhibited.

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
Storage Temperature Range

Shift·right is accomplished synchronously with the rising
edge of the clock pulse when SO is high and S1 is low.
Serial data for this mode is entered at the shift·right data
input. When SO Is low and S1 is high, data shifts left syn·
chronously and new data is entered at the shift·left serial

Connection Diagram

7V
7V
-65·Cto + 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
WhiCh the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will

define the conditions for actual device operation.

OUTPUTS

v~c
J16

/ a.

O.
14

15

0,

CD '

CLOCK

12

11

13

so

S1
10

Dual·ln·Line Package
DM54AS194 (J)
DM74AS194 (J, N)

-c

CLEAR

SHIFT
RIGHT'

,~

o,
PARALLEL INPUTS

SERIAL
INPUT

TDPVIEW

SHIFT
LEFT

"

G!:

SERIAL
INPUT

H = high level (steady·state),
L = low level (steady-state),
x = don't care (any input, Including
transitions).

n./F/6721.'

Function Table
Clear
L
H
H
H
H
H
H
H

Sl

so

Clock

X
X

X
X

X

H
L
L
H
H
L

H
H
H
L
L
L

t

L
I

1
1
I
X

Serial

Parallel

Left

Right

X
X
X
X
X

X
X
X

H
L

X

t = transition from low·to·hlgh
level.

Outputs

Inputs
Mode

H
L

X
X
X

A
X
X

B

e

D

aA

aa

X
X

X
X

X
X

L

L

X
X
X
X
X

aAO
a
H

aBO

X
X
X
X
X

a

b

X
X
X
X
X

X
X
X
X
X

d

ac

- aD

a, b, c, d = the level of steady-state
Input at Input A, B, e, or 0,
respectively.

Oco

000
d

OBn
OBn
OOn
OOn
Oeo

OCn
OCn
H

OAO, 0BO, Oeo, 000 = the level of
OA, 0B, Oe, or 00, respectively,
before the indicated steady·state
Input conditions were established.

b

OBn
OBn

O'n
O'n
OCn
OCn

0'0

aBO

000

OAn, OBn, Oen, OOn = the level of
OA, OB, Oe, respectively, before
the most recent t transition of the
Clock.

This document contains Information on a product under development. NSC reserves the right to change or discontinue this product without notice.

3·97 •

C

3:
~

~

Recommended Operating Conditions
Symbol

DM54AS194

Parameter

Vcc

Supply Voltage

VIH

High level Input Voltage

V1L

Low level Input Voltage

10H

High level Output Current

10L

low level Output Current

fCLOCK

Clock Frequency

tw

Pulse Width

tsu

.

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

V

0.8

V

2

2

V

0.8
-2

-2

20

I High

110

0

4

4

2

2

.

6

fLoW

ns

6

6.5

6.5

Data

2.5

2.5

Clear Recovery Time

4

4

tH

Hold Time

0

0

Operating Free·Air Temperature

-55

mA
MHz

110

Select

125

mA

20

tREC

TA

Units

Max

Clear low

Set·UpTime

I

Typ

0

ClK

DM74AS194

Min

ns

ns

·c

.70

0

Electrical Characteristics over recommended operating free·air temperature range unless otherwise noted
DM54AS194
Parameter

Conditions
Min

DM74AS194

Typ
(Note 1)

Max

Min

Typ
(Note 1)

-1.2

. Units
Max

Vcc=4.5V, 11= -18 mA

VOH

Vcc = 4.5V to 5.5V, 10H = Max,
.v IL = Max, VIH = Min

VOL

Vcc = 4.5V, 10L = Max,
V1L = Max, VIH = Min

II

Vcc=5.5V,
V I =7V

Data, Clear, ClK
Mode, Sl,SR

Vcc=5.5V,
VI=2.7V

Data, Clear, ClK

20

20

Mode, Sl, SR

40

40

Vcc=5.5V,
VI=0.4V

Data, Clear, ClK

IIH

IlL

Vcc..,2

Vcc = 5.5V, Va = 2.25V

Icc

Vc c =5.5V

V

Vcc-2
0.5

V

100

100

.p.A

200

200

0.5

0.35

0.35

-0.5

Mode, Sl, SR

10

V

-1.2

VIK

-0.5

mA

-1

·-1
-30

p.A

-112

Outputs High

28'

44

Outputs low

35

56

-30

-112

mA

28

44

mA

' 35

56

Switching Characteristics
DM74AS194

DM54AS194
Input

Output

Conditions

Clock

AnyQ

tpHL

Clock

AnyQ

Vcc = 4.5V .to 5.5V,
C L =50 pF,
R1 =R2=5000

tpHL

Clear

AnyQ

Parameter

fMAX
tpLH

Nota 1: Aillypical values are at

Min

Typ
(Note 1)

Typ
(Note 1)

Units

Max

Min

2

9

2

8

ns

2

9

2

8

ns

3

12.5

3

11.5

ns

110

110

Vee = 5V, TA = 25°C.
3·98

Max
MHz

r----------------------------------------------------------------------.c
s:
Logic Diagram

~....

PARALLEL INPUTS

CD

~
C

CON~~~~ ~

s:

( 51

INPUTS

~

50~o-.-----~--tr~--i----+--1t~r-~----r--+r1*-~----i-~H-.r-,

SHIFT·

SHIFT·

S~~~[ ..:2'--_ _ _ _--.

r-i1++-+.;..7 ~~~AL

INPUT

INPUT

CLOCK~o---t---i---r---t---~--t---~--~--t---~

CL~R~I----__~o_-~--~------t_-_+~-----6--~----~
~
U
«
g
\~

~

~

12
Do ,

PARALLEL OUTPUTS
TLIF/6721·2

Timing Diagram
CLOCK

CL~R

SERIAL {
OATA
INPUTS

R

PARALLEL {
OATA
INPUTS

A

~~--+-----------~~~

~~--+-----~----~~----------~----------+-

OUTPUTS { :

~ -+-+-~

OC.

DO: +-+_-1
CL~R

TLlF16721·3

3·99

:i:!
~
....
CD

.j:o,

~
.,...

~
;:t

:E

e
Lt)

~

~
:E
c

"
~ Semiconductor
~National

PRELIMINARY

DM54AS195/DM74AS195
4·Bit Parallel Access Shift Registers
General Description

Features

These 4-bit registers feature 'parallel"inputs, parallel outputs, J-j( serial inputs, shift /load control input, and a direct
overriding clear. All inputs are buffered to lower the input
drive requirements. The registers have two' modes of
operation:

• Synchronous parallel load
• Positive-edge-triggered clocking
• Parallel inputs and outputs from each llip-flop
• Direct overriding clear

• J and j( inputs to first stage
Parallel (broadside) load
Shift (in the direction QA toward QD)

• Complementary outputs from last stage
• For use in high-performance:
accumulators I processors
serial-to-parallel, parallel-to-serial converters
• Switching specifications at 50 pF
• Switching specifications guaranteed over full
temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TIL
process
• Functionally and pin for pin compatible with Schottky,
low power Schottky, and advanc"ed low power Schottky
TIL counterpart
• Improved AC performance over Schottky, low power
Schottky, and advanced low power Sqhottky
counterpart

Parallel loading is accomplished by applying the four bits of
data and taking the shift /load control input low. The data is
loaded into the associated llip-flop and appears at the outputs after the positive transition of the clock input. During
loading, serial data flow is inhibited.
Shifting is accomplished" synchronously when the
load control input is high. Serial data for this mode
tered at the J-j( inputs. These inputs permit the first
to perform as a J-K D, or T-type flip-flop as shown
truth table.

shifl!
is en·
stage
in the

The high-performance S195, with a 105 MHz typical shift
frequency, is particularly attractive for very high-spe'ed
data processing systems. In most cases existing systems
can be upgraded merely by using this Schottky-clamped
shift register.

Connection Diagram
Dual-In-Line Package
OUTPUTS

1

CLEAR

1 !3I I I I
12

J

14

K

----.....--..
SERIAL INPUTS

15

18

ABC

17
D

18
GND

PARALLEL INPUTS

54AS195 (J)

TLlF/6476-1

74AS195(N)

This document contains information on a product under development. NSC reserves the right to change or discontinue this product without notice.

3-100

r--------------------------------------------------------------------.c

3:

Function Table
Inputl
Shllll

Clear

Clock

Load

X
L
H
H
H
H
H

L
H
H
H
H
H
H
H

X

t
L

t
t
t
t

Parall.,

Serial

J

i

A

S

C

D

X
X
X
L
L
H
H

X
X
X
H
L
·H
L

X

X
b
X
X
X
X
X

X

X
d
X
X
X
X
X

= High Level (steady slate),

a
X
X
X
X
X

c
X
X
X
X
X

OA

Os

Oc

OD

QD

L

L
b
OBO
OAD
OAn
OAn
OAn

L

L
d
000
OCn
OCn
OCn
OCn

H

-c

a
OAO
OAO
L
H

OAn

c
OCO
OBn
OBn
OBn
OBn

CD
U1

3:
~

d

0 00

l;;

OCn
OCn

""'"

CD
U1

OCn
OCn

L = Low Level (steady slale), X = Dan" Care (any mput, including transitions)

t = Transition from low '0 high level

a,b,c,d = The level of steady siale input at A,
CAD. 0SO-

~""'"

Outputs

Oeo. 000 = The level 01 CA.

e, C, or D, respectively.

0B. CC. or CO. respectively. before th'e indicated steady slate input

conditions were established.
0An. 0Sn. 0Cn = The level of 0A.

0a. Cc. respectively,

before the most recent transition of the clock.

Logic Diagram
SERIAL
INPUT
..........--...

K

J

SHIFT ILOAD (9)
CONTROL

12)

13)

PARALLEL INPUTS

A

14)

~

15)

c
16)

0'

17)

•
PARALLEL OUTPUTS

TLIF16476·2

Timing Diagram
TYPICAL CLEAR, SHIFT, AND LOAD SEQUENCES
ClOCK
CLEAR
SERIAL
INPUTS

{J
K---t----'

SHIFT/ L O A O - - - + - - - - I - - - - - - - - - - - - . ,

PARALLEL(:
DATA
INPUTS C--r-------1------------~

0_-+____+-___________-+__+-___________

OUTPUTsl:~~:+
OC __

I ----+-----~

00:=-+____+ ______---'
f-----SERIAL SHIFT ----~_!
LOAD

3-101

TL/FI6476·3

~.------------------------------------------------------------------------------,

~;:!: a~National
Semiconductor

:E DM54AS/DM74AS230,231
TRI-STATE~ Bus Drivers/Receivers
.

e
~

~ General Description

~

II)

:E

c

This family of Advanced Schottky TRI-STATE Bus circuits
are designed to provide either bidirectional or unidirectional
buffer interface in Memory, Microprocessor, and Communication Systems. The output characteristics of the circuits
have low impedance sufficient to drive terminated transmission lines down to 133 ohms. The input characteristics of
the circuits likewise have a high impedance so it will not significantly load the transmission line. The package contains
eight TRI-STATE buffers organized with four buffers having
a common TRI-STATE enable gate. The AS230 is organized as 4 bit buffers inverting & 4 bit buffers non inverting.
The AS231 is organized as two 4 bit wide inverting buffers
with separate complementary output control buffers.
The TRI-STATE circuitry contains a feature that maintains
the buflers in TRI-STATE until the power supply (VCC) is
greater than 3V. This feature prevents the buffers from
glitching the system bus during power .uP or down.

Features
•
•

•

Functional and Pin Compatible with Low Power
Schottky Counterpart.
Switching Response Specified into 500 ohm and 50pF.
Low Level Drive Current 74AS = 48mA,
54AS = 40mA
Glitch Free Bus During Power Up/Down
Specified to Interface with CMOS at
VOH = VCC - 2V.

•
•
•
•

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS
DM74AS
Storage Temperature Range
Lead Temperature
(Soldering, 10 seconds)

(Note 1)
7V
7V

-55°C to 125·C
OoC to 70°C
-65°C to 150·C
+300·C

Nole 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the. absolute
maximum ratings. The. "Recommended Opt!(aling Conditions" table will
define the conditions for actual device operation.

Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
Improved Switching Performance over Low Power
Schottky Counterpart.

Connection Diagrams
Dual·ln·Line Package
VCC

2<3

1<3

1A1

2Y4

1A2

2Y3

1A3

2Y2

Dual-ln·Line Package

1A4

2Y1 GND

1<3

1A1

1Y1

2A4

1Y2

2A3

1Y3

2A2

1Y4 2A1

2Y4

1A2

2Y3

1A3

2Y2

1A4

2Y1 GND
TLI F16297·2

TL/F/6297·1

54AS230 (J)

74AS230 (J,N)

54AS231 (J)

74AS231 (J,N)

Function Table
A

AS231
Y (Invert)

L

L

H

L

L

H

L

H

H

X

G (AS231)

G

H
H
L

AS230
Y (Non·lnvert)

Z (I.solation)

3-102

H = high logic level
L = low logic level
X = either low or high logic level
Z high Impedance (off)

=

Recommended Operating Conditions
-

Parameter

Supply Voltage, VCC

DM54AS

DM74AS

230,231

230,231

Min

Nom

Max

4.5

5

5.5

High Level Input Voltage, VIH

.,

2

Low Level Input Voltage, VIL

Min

Nom-

Max

4.5

5

5.5

Unit

V
V

2

0.8

0.8

V

High Level Output Currerit, IOH

-12

-15

mA

Low Level Output Current, IOL

-48

-64

mA

Max

Unit

-1.2

V

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25"C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC

VOH

High Level Output
Voltage

IOH=Max
VCC = 4.5V

=

4.5V, liN

Min
=

-18mA

IOH = - 2.0mA, VCC = 4.5V to 5.5V
VOL

Low Level Output
Voltage

VCC = 4.5V, IOL = Max

II

Input Current at
Max Input Voltage

VCC

=

5.5V, VIN

VCC

=

5.5V, VIN = 2.7V

IIH

,High Level Input Current

IlL

Low Level Input Current

VCC = 5.5V,
VIN = O.4V

=

Typ

2.4

V

VCC-2

V
0.35

0.1

7V

20

VCC = 5.5V, V = 2.7V

lOlL

Low Level TRI-STATE
Output Current

VCC = 5.5V, Vo = O.4V

10'

Output Drive Current

VCC'= 5,5V, VOUT = 2.25V

ICC

54{74AS230
Supply Current

VCC = 5.5V

mA
/J. A
mA

AS2302A Inputs

High Level TRI-STATE®
Output Current

V

-0.5

Others

IOZH

0.55

-1

-50

50

/J.A

-50

/J. A

-150

mA

Outputs High

16

25

Outputs Low

55

87

TRI-STATE

29

46

Outputs High

12

18

Outputs Low

52

82

TRI-STATE

25

39

mA

~

ICC

54{74AS231
Supply Current

VCC = 5,5V

3-103

mA

Switching Characteristics over recommended operating free air temperature range (N?te 1).
All typical values are measured at Vee = 5V, TA = 25°C.

Parameter

From
(Input)

To
(Output)

DM54AS230
Condit!:'"s

Min

2.5

7

2.5

6.5

2

6

2

5.7

2.5

9

2.5

6.2

2

7

2

6.2

2

7

2

6.4

2

9

2

8.5

tpHZ

2

5.5

2

5

tpLZ

2

12.5

2

9.5

IPZH

2

10

2

9

2

8

2

7.5

tpHZ

2

6.5

2

6

tPLZ

2

10.5

2

9

1A

1Y

~

tpHL
tpLH

2A

2Y

tPHL
tPZH
tPZL

Vce =
4.5 to 5.5V
RL = 500!l
CL = 50 pF

1Y

1<3

tpZL

Typ

DM74AS230

Max

tpLH

Min

Typ

Max

2Y

213

Unit

ns

ns

ns

ns

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V, TA = 25°C;
Parameter

From
(Input)

To
(Output)

A

Y

DM54AS231
Conditions

. Min·

DM74AS231
Typ

Max

Max

Min

2

7

2

6.5

2

6

2

5.7

2

7

2

6.4

2

9

2

. 8.5

IPHZ

2

5.5

2

5

IPLZ

2

12.5

2

9.5

tpZH

3

7

3

6

3

10

3

9

tPHZ

3

6.5

3

6

tpLZ

3

13.5

3

7

tpLH
tPHL
IPZH
tpZL

G

Vce =
4.5105.5V
RL = 500!!
CL = 50 pF

Y

IPZL
G

Typ

Y

Nole 1: See Section 1 for test waveforms and output load.

3·104

Unit

ns

ns

.,

ns

r-------------------------------------------------------------~c

3:
~

~National

-

D Semiconductor

~

J

DM54AS/DM74AS240,241,242,243,244
TRI-STATE~ Bus Drivers/Receivers

c
3:
olio

This family of Advance Schottky TRI-STATE Bus circuits
are designed to provide either bidirectional or unidirectional
buffer interface in Memory, Microprocessor, and Communication Systems. The output characteristics of the circuits
have low impedance sufficient to drive terminated transmission lines down to 133 ohms. The input characteristics of
the circuits likewise have a high impedance so it will not significantly load the transmission line. The package contains
eight TRI-STATE buffers organized with four buffers having
a common TRI-STATE enable gate. The AS240, 241 and
244 are eight wide in a 20 pin package, and may be used as
a 4 wide bidirectional or eight wide unidirectional. The
AS242 and 243 are organized four wide bidirectional in a 14
pin package. The buffer selection includes inverting and
non-inverting, with enable or disable TRI-STATE control.

Features
•

Advanced Oxide-Isolated, lon-Implanted Schottky TIL
Process.

•

Improved Switching Performance with Less Power
Dissipation compared with Schottky Counterpart.
Functional and Pin Compatible with 54/74LS and
Schottky Counterpart.

•

•
•
•

SWitching Response Specified Into 500 ohm and 50pF.
Glitch Free Bus During Power Up/Down.
Specified to Interface with CMOS at
VOH = VCC -2V.

Absolute Maximum Ratings (Note 1)
Supply Voltage, VCC
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54AS
-55°C to 125°C
DM74AS
O°C to 70°C
Storage Temperature Range
-65°C to +150°C
Lead Temperature
(Soldering, 10 seconds)
+300°C

Nole 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

not be operated at these limits. The parametric. values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual·ln·Line Package
2G

lG

lA 1

2Y4

lA2

2Y3

lA3

2Y2

Dual·ln·Llne Package

lA4

2Yl GND

Vee

2G

lG

lAl

2Y4

lA2

2Y3

lA3

lY3

2A2

lY4 2Al

2Y2

lA4

2Yl GND
TLlF/6298·2

TLlF/6298·1

54AS240 (J)

~

~....

~

Connection Diagrams

Vce

U'I

, General Description

74AS240 (J,N)

54AS241 (J)

3·105

74AS241 (J,N)

Connection Diagrams (Co,,,,.....

;
~

Dual-In-Line Package

Dual-In-Llne Package
Vee

GSA

He

18

28

38

4B

Vcc

GBA

NC

1B

2B

3B

4B

NC

1A

2A

3A

4A

GND

GAB

NC

1A

2A

3A

4A

GND

o

54AS242.(J)

TLlfi6298.3

TLlF/6298-4

54AS243 (J)

74AS242 (J,N)

74AS243 (J,N)

Dual-In-Llne Package
vcc

2G

1Y1

2A4

1Y2

2A3

1Y3

2A2

1G

1A 1

2Y4

1A2

2Y3

1A3

2Y2

1A4 2Y1 GND

1Y4 2A1

,...

~

~~

~
::E
Q

I

-

TL/F/6298-5

54AS244 (J)

~

~

0

74AS244 (J,N)

Function Tables

::E

Q

LS240
G
L
L
H

A
L
H
X

LS241
Y
H
L
Z

L= Low Logie Level

2G
X
X
X
H
H
L

H = High Logic Level
o

X = Either Low or
High Logic Level
Z= High Impedance

1G
L
L
H
X
X
X

1A
L
H
X
X
X
X

LS244
G
L
L
H

A
L
H
X

2A
X
X
X
L
H
X

1Y
L
H
Z

2Y
o

L= Logic Low Level
H = Logic High Level
X = Either Logic Lowor
Logic High Level

L
H
Z

Z = High Impedance

LS242,LS243
Y
L
H
Z

L= Low Logic Level

INPUTS

H = High Logic Level
X::; Either Low or

High Logic Level
Z= High Impedance

!

GAB

GBA

L
H
H
L

L
H
L
H

3-100

I

'AS242

'AS243

AloS

AloS

SloA

SloA

Isolation

Isolalion
Lalch A and S
(A=S)

Latch A and S
(A=S)

Recommended Operating Conditions
DM54AS
240,241,242,243,244
Parameter
Supply Voltage, VCC
High level Input Voltage, VIH

DM74AS
240,241,242,243,244

Min

Nom

Max

Min

'Nom

Max

4.5

5

5.5

4.5

5

5.5

2

2

Unit
V
V

low level Input Voltage, Vil

0.8

0.8

V

High level Output Current, IOH

-12

-15

mA

low level Output Current, IOl

48

64

mA

3-107

Electrical Characteristics over recommended operating free air temperature range.
All ~ypical values are measured at Vcc = 5V, TA = 25'C.

Symbol
VIK
VOH

Parameter

Conditions

Input Clamp Voltage

VCC = 4.5V, liN = -18mA

High Level Output
Voltage

Min

,

VCC = 4.5V, 10H = -3mA

2.4

Typ

Max

Unit

-1.2

V

3.2
V

2.4

VCC=4.5V, 10H = Max
10H = -2mA

VCC-2

VOL

Low Level Output
Voltage

VCC = 4.5V

II

Input Current at
Max Input Voltage

VCC = 5.5V VIN = 7V

10L = Max

0.55

0.35

Others

V

100
p.A

VIN =5.5V

IIH

IlL

High Level Input Current

Low Level Input Current

VCC = 5.5V, VIN = 2.7V

VCC = 5.5V, VIN = O.4V

10ZH

High Level TRI-STATE@
Output Current ~

Vec = 5.5V, V. = 2.7V

10ZL

Low Level TRI-STATE
Output Current

VCC=5.5V, V=0.4V

For AS242,
243 (A or Sf
AS242,243
(AorS)

70

Others

20

p.A

AS240, 241
(G, (3),242,
243 (Control
Inputs),
244 (G)

-500

AS241 (A),
243 (A or S),
244 (A)

-1000

'.
p.A

50

AS242

-500

AS240, 241,
244

-50

AS243
10

Output Drive Current

VCC = 5.5V, VOUT = 2.25V

ICC

54/74AS240
Supply Current

VCC = 5.5V

ICC

ICC

54/74AS241
Supply Current

54/74AS242
Supply Current

-50

-115

-150

Outputs High

,11

17

51

75

TRI-STATE

24

38

Outputs High

22

35 _

Outputs Low

61

90

TRI-STATE

35

56

A Port Outputs High

18

28

A Port Outputs Low

38

60

TRI-STATE

25

39

VCC = 5.5V

I

I
3-108

p.A

-1000

t---Outr-uts Low

VCC = 5.5V

p.A

niA

mA

mA

mA

Electrical Characteristics' (Continued)

over recommended operating free air temperature range.

All typical values are measured at Vee = 5V, TA = 25"C.
Symbol

Ice

ICC

Parameter

Conditions

54/74AS243
Supply Current

Vec

54/74AS244
Supply Current

VCC

=

=

5.5V

5.5V

Typ

Max

A Port Outputs High

28

44

A Port Outputs Low

47

74

TRI-STATE

35

56

Outputs High

22

34

Outputs Low

60

90

TRI-STATE

34

54

Min

Unit

mA

~

mA

~

Switching Characteristics over recommended operating free air temperature range (Notes 1 and 2)
All typical values are measured at Vee = 5V, TA = 25"C.
Parameter
(Propagation Delay Time)

TPLH, Low-to-High Level
Output
TpHL, High-to-Low Level
Output
TpZL, Output Enable to
Low Level
TPZH, Output Enable to
High Level
TPLZ, Output Disable
From Low Level
TpHZ, Output Disable
From High Level
TPLH, Low-to-High Level
Output
TpHL, High-to-Low Level
Output
TPZL, Output Enable to
Low Level
TpZH, Output Enable to
High Level
TPLZ, Output Disable
From Low Level
TPHZ, Output Disable
From High Level
TPZL, Output Enable to
Low Level
TpZH, Output Enable to
High Level
TPLZ, Output Disable
From Low Level
TPHZ, Output Disable
From High Level
TPLH, Low-to-High Level
Output
TPHL. High-to'Low Level
Output

74AS

Circuit
Configuration

Min

Typ

54AS
Max

Min

Typ

Max

Unit
~

~Y

2

7

2

6.5

ns

AS 240

2

6

2

5.7

ns

2

9.5

2

9

ns

2

7

2

6.4

ns

2

12.5

2

9.5

ns

2

5.5

2

5

ns

2

9

2

6.2

ns

2

7

2

6.2

ns

'~o~

2

8

2

7.5

ns

2

10

2

9

ns

2

10.5

2

9

ns

AS 241

2

6.5

2

6

ns

'~

3

9.5

3

8.5

ns

3

11

3

10.5

ns

3

12

3

12

ns

3

7

3

7

ns

2

7

2

6.5

ns

2

6

2

5.7

ns

A

'::J

:

~

OUT
o--y

AS 240

Ii=!
A
AS 241

:

OUT
y

.

:

OUT
y

AS 241

~

A6r B
Aor B
AS 242

~

3·109

Switching Characteristics over recommended operating free air temperature range (Notes 1 and 2)
All typical values are measured at Vee = 5V, TA = 25°C.

Parameter
(Propagation Delay Time).
TPZL, Output Enable to
Low Level
TPZH, Out!,ut Enable to
High Level
TpLZ, Output Disable
From Low Level
TPHZ, Output Disable
From High Level
TPZL, Output Enable to
Low Level
TPZH, Output Enable to
High Level
TPLZ, Output Disable
From Low Level
TPHZ, Output Disable
From High Level
TPLH, Low-to-High Level
Output
TPHL, High-to-Low Level
Output
TPZL, Output Enable to
Low Level
TPZH, Output Enable to .
High Level
TPLZ, Output Disable
From Low Level
TPHZ, Output Disable
From High Level
TpZL, Output Enable to
Low Level
TPZH, Output Enable to
High Level
TPLZ, Output Disable
From Low Level
TpHZ, Output Disable
From High Level
TpLH, Low-to-High Level
Output
TPHL, High-to-Low Level
Output
TPZL, Output Enable to
Low Level
TPZH, Output Enable to
High Level
TPLZ, Output Disable
From Low Level
TPHZ, Output Disable
From High Level

54AS

Circuit
Configuration

Min

~

GBA
B

OUT
A

AS 242

'::]

GAB

.
T
B

74AS
Min

3

9

3

8

ns

3

7

3

6

ns

3

13.5

3

10.5

ns

3

8.5

3

6

ns

2

8.5

2

7.5

ns

2

5.5

ns

. 9

Typ

Unit

Max

2

02!d.

A

Typ

Max

2

12.5

2

9.5

ns

2

7

2

6.5

ns

3

9

3

7.5

ns

3

8

3

6.5

ns

2

9

2

7.5

ns

2

10

2

9

ns

2

11

2

9

ns

AS243

2

7

2

6.5

ns

'~

3

9.5

3

8.5

ns

3

11

3

10.5

. ns

3

14

3

11

ns

3

7.5

3

7

ns

2

9

2

6.2

ns

2

7

2

6.2

ns

2

8

2

7.5

ns'

2

10

2

9

ns

2'

10.5

2

9

ns

2

6.5

2

6

ns

AS242

~

AS243

OUT
Aor B

~

GAB
A

.

OUT
B

,-

GBA
B

OUT
A

AS243

~

A

OUT

Y

AS244

J
:

OUT
y

AS244

Note 1: See Section 1 for tesfwaveforms and output load.
Not. 2: Switching characteristic' conditions are Vec

=4.SV to S.SV, RL =500D, eL =50 pF.

3·110

r------------------------------------------------------------------,c

PRELIMINARY 3:

~National

~

~ Semiconductor

~

DM74AS245A Octal TRI·STATE® Bus Transceivers
General Description
This advanced Schottky device contains 8 pairs of TRISTATE logic elements configured as octal bus transceivers. These circuits are designed for use in memory,
microprocessor systems and in asynchronous bidirectional data buses. Two way communication between
buses is controlled by the (DIR) Input. Data transmits
either from the A bus to the B bus or from the B bus to the A
bus. Both the driver and rec.eiver outputs can be disabled
via the (G) enable input which causes outputs to enter the
'high impedance mode so that the buses are effectively
isolated.

Features
• Advanced oxide-isolated, ion implanted Schottky TIL
process

•
•
•
•

Switching response specified into 500!1I50 pF
Specified to interface with CMOS at VOH = Vcc- 2V
PNP inputs reduce input loading
Switching specifications guaranteed over full
temperature and Vcc range

Absolute Maximum Ratings
Supply Voltage, Vee
7V
Input Voltage
7V
Operating Free Air Temperature Range
.DM74AS
0·Ct070·C
Storage Temperature Range
- 65·C to + 150·C
Lead Temperature (Soldering, 10 seconds)
300·C

• Non-inverting logic output
.• TRI-STATE outputs independently controlled on A and
B buses
.

Not. 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

• Low output impedance to drive terminated transmission
lines to 1330

,"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

not be operated at these limits. The parametric values defined in the

Dual-In-Lin!! Package

i 19

V;cii
120

Ii

Control
Inputs

;s

I'

G
L
L
H

'7

r r r r r \7r 18r 19r
OIR

6A

fA

Operation
OIR
L
H

X

B Data to A Bus
A Data to B Bus
Hi-Z

110

SA GND

TLlF/6299·1

OM74AS245A (J, N)

This document contains information on a product under development. NSC reserves the right to change or discontinue this product without notice.

3-111

Recommended Operating

C~nditions
DM74AS245A

Symbol

-

Pa'ameter

Units

Mill

Typ

Max

4.5

5

5.5

V

0.8

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

10H

High Level Output Current

-15

rnA

10L

Low Level Output Current

48

rnA

2

V

-.

Electrical Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

Min

Typ

VIK

Input Clamp Voltage

Vee = 4.5V, liN = -18 rnA

V OH

High Level Output Voltage

Vee = 4.5V, 10H = - 3 rnA

2.4

3.2

Vee = 4.5V,l oH = -15mA

2.0

2.3

Max
-1.2

10H = - 2 mA, Vee = 4.5V to 5.5V

Vee- 2

Low Level Output Voltage

Vee = 4.5V,.loL = Max

II

Input Current at Max
Input Voltage

Vcc =5.5V, VIN =7V
(VIN = 5.5V for A or B Ports)

IIH

High Level Input Current

Vcc= 5.5V,
VIN=2.7V
Vce= 5.5V,
VIN =0.4V

Control Inputs

-0.1

A or B Ports

-0.75

Low Level Input Current

V
V

VOL

IlL

Units

0.5

V

0.1

rnA

Control Inputs

20

/LA

A or B Ports

50

10

Output Drive Current

Vcc=5.5V, Vour =2.25V

lec

Supply Current

Vcc ·=5.5V

0.35

-30

-112

Outputs High

62

Outputs Low

75

.TAI-STATE

79

mA

mA
mA

Switching Characteristics over recommended operating free air temperature range (Notes 1 and 2)
Parameter
(Propagation Delay Time)
tpLH, High·to-Low Level Output
t pHL, High-to-Low Level Output
tpZL, Output Enable to Low Level
t pZH , Output Enable to High Level
tpLZ, Output Disable from Low Level

Circuit
Configuration

IN~OUT

IN~

AORB
OUT

tpHZ, Output Disable from High Level
Note 1: See Section 1 for test waveforms and output load.
NOIe 2: Switching characteristic conditions are Vec = 4.5V to 5.5V, RL = 50011, CL = 50 pF.

-

3-112

DM74AS245A
Min

1)p

Max

Units

6

ns

5

ns

8

ns

8

ns

5

ns

4.5

ns

c
PRELIMINARY

~National

s::

U1

~

D Semiconductor

I\)

-s::
U1

.....

DM54AS251 /DM74AS251 TRI-STATECil 8-Line to 1-Line
Data Selector/Multiplexer
General Description

•

This Data Selector/Multiplexer contains full on-chip decoding to select one-of-eight data sources as a result of a
unique three-bit binary code at the Select inputs. Two complementary outputs provide both inverting and non-inverting buffer operation. An Output Control input is provided
which, when at the high level, places both outputs in the
high impedance Off state. In order to prevent bus access
conflicts, output disable times are shorter than output enable times. The Select input buffers incorporate internal
overlap features to ensure that select input changes do not
cause invalid output transients.

Features
~

•

Advanced Oxide-Isolated lon-Implanted Schottky TTL
Process.
Switching Performance is Guaranteed Over Full
Temperature and VCC Supply Range.

•
•

C

~

Pin and Functional Compatible with LS and Schottky
Family Counterpart.
Improved Output Transient Handling Capability.
Output Control Circuitry Incorporates Power-Up TriState Feature.

Absolute Maximum Ratings (Note 1)
7V
Supply Voltage, VCC
7V
Input Voltage
Operating Free Air Temperature Range
-55°C to 125°C
DM54AS251
O°C to 70°C
DM74AS251
Storage Temperature Range
-65°C to +150°C
Lead Temperature
(Solpering, 10 seconds)

Not. t: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual-In-Line Package

03

.!!..vcc
15 04

02 2

14

3

IJlj

>~::~TS
13 06

DO 4

OUTPUTY

OUTPUT W

OUTPUT
CONTROL
S

5

6

7

...

r{tS...

12 07

A~
A

""

ii~
B

""

Strobe

Select

DATA
INPUTS
01

Outputs

Inputs

r---

I

\I SELECT A

C

B

A

S

Y

X
L
L
L
L
H
H
H
H

X
L
L
H
H
L
L
H
H

X

H
L
,L
L
L
L
L
L
L

Z

Z

DO
01
02
03
04
05

00

D6

[)6

07

D7

L
H
L
H
L
H
L
H

W

OT
IJ2
00
D4

OS

H ~ High Logic Level. L ~ Low Logic Level, X ~ Don't Care
Z ~ High Impedance (Off)
DO thru 07 ~ The Level of the Respective 0 Input

10 SELECT B

c~

GNo..!

~

""

9 SELECT C

TLlF/630Q-1

54AS251 (J)

74AS251 (J,N)

This document contains information on a product under development. NSC reserves the right to change or discontinue this product without notice.

3-113

~

.....

U1

~r-----------------~-----------------------------------------------------------------

II)

~

!~

.....
:lE
c

Recommended Operating Conditions
,

DM54AS251

Parameter

DM74AS251

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Unit

-

Supply Voltage, VCC

~

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Current, 10H

-12

-15

mA

Low Leyel Output Current, 10L

32

48

V

~

~.

High Level Input Voltage, VIH

V

2

2

II)

:lE

c

mA·

Electrical Characteristics over recommended operating free air temperature range.
=SV, TA = 2S·C.

All typical values are measured at Vee
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.SV, liN';' -18mA

VOH

High Level Output
Voltage

Vee = 4.SV, 10H = Max

Min

10H = - 2mA, VCC = 4.SV to S.SV
VOL

Low Level Output
Voltage

Vec = 4.SV, 10L = Max

II

Input Current at
Max Input Voltage

Vec = 5.5V,
VIN = 7V

High Level Input Current

Vec = 5.5V,
VIN = 2.7V

2.4

Typ

Max

Unit

-1.2

V
V

3.2

V

VCC-2
0.3S

O.S

V
,

IIH

IlL

Low Level Input Current

VCC = 5.5V
VIN = O.4V

A,B,e

0.2

All Others

0.1

A,B,C

40

All Others

20

mA

p.A

A,B,C

-0.6

-1

mA

All others

-0.3

-0.5

mA

-112

mA

-30

10

Output Drive Current

VCC = 5.5V, VOUT = 2.25V

10ZH

Off-State Output
Current, High Bias

VCC = 5.5V, VOUT = 2.7V

50

p.A

10ZL

Off-State Output
Current, Low Bias

VCC = 5.5V, VOUT =O.4V

-50

p.A

ICC

Supply Current

Vec = 5.5V
Data Inputs = 3.0V
Select Inputs = 3.0V
Control Inputs = 3.0V

48

mA

3-114

28

c

3:

Switching Characteristics over recommended operating free air temperature range (Note 1).

(J1

~

All typical values are measured at Vee = 5V, TA = 25·C.
DM54AS251

en

DM74AS251

N

5

5

ns

-

5

5

ns

~

4.5

4.5

ns

4.5

4.5

ns

3

3

ns

4

4

ns

3

3

ns

tPHL, High to low Level Output

2.5

2.5

ns

tZH. Output Enable Time
to High Level

5

5

ns

6

6

ns

5

5

ns

6

6

ns

3

3

ns

4

4

ns

3

3 '

ns

4

4

ns

Parameter

From

To

tPLH, Low to high Level Output

Conditions

Min

Typ

y

tPHL, High to low Level Output

Max

Min

Typ

Max

Unit

Select I - - tPLH, Low to high Level Output
tPHL, High to low Level Output
tPLH, Low to high Level Output

y
Data
tPLH, Low to high Level Output

VCC =
t---- 4.5 to 5.5V
CL = 50 pF
W
RL = 500!l

y
tZL. Output Enable Time
to Low Level

-

tZH. Output Enable Time
to High Level

W
tZL. Output Enable Time
to Low Level

Output
Control -

tHZ. Output Disable Time
From High Level

y
tLZ. Output Disable Time
From Low Level

c
3:

~
N

.....

(J1

W

tPHL, High to low Level Output

(J1
.....

-

tHZ. Output Disable Time
From High Level

W
tLZ. Output Disable Time
From Low Level
Note 1: See Section 1 for test waveforms and output load.

3·115

~r---------------------------------------------------------------------------------------

-~ Logic Diagram

~

~

-ou TPUT
co NTROl

:E

-

7..to..

·V

00 •

c

---f

~

01 3

II)

~

--r

)--

02 '

:E

r---r

\

c

,,'

~~

r

DATA
INPUTS

04 IS

rf
05

"

r-r
0&

)--

~rr,=r

r>of.u

DUTPU TW

)--

13

~
07 12

A II

.-'
"
....

I ."
·V

•
•

~

i
DATA
SElECT
[SINAAY!

,

10 "

v

.

..."

I

."

,

·V

C

I .".....

c

TL/F/6300·2

3-116

~National

a

PRELIMINARY

Semiconductor

DM54AS253/DM74AS253 TRI-STATECil Dual4-Line to
1-Line Data SelectorIMultiplexer
General Description

•

Pin and Functional Compatible with LS and Schottky,
Family Counterpart.

This Data Selector/Multiplexer contains full on-chip decoding to select one-of-four data sources as a result of a
unique two-bit binary code at the Select Inputs. Each of the
two Data Selector/Multiplexer circuits have their own separate Select, Data, and Output Control inputs and a non-inverting Tri-state output buffer. The Output Control inputs,
when at the high level, place the corresponding output in
the high impedance Off state. In order to prevent bus access conflicts, output disable times are shorter than output
enable times. The Select input buffers incorporate internal
overlap features to ensure that select input changes do not
cause invalid output transients.

•
•

Improved Output Transient Handling Capability.
Output Control Circuitry Incorporates Power-Up TriState Feature.

Features
•
•

Advanced Oxide-Isolated lon-Implanted Schottky TTL
Process.
SwitclJing Performance is Guaranteed Over Full
Temperature and VCC Supply Range.

Absolute Maximum Ratings (Note 1)
Supply Voltage, Vce
7V
7V
Input Voltage
Operating Free Air Temperature Range
-55°C to 125°C
DM54AS253
0° to 70°C
DM74AS253
Storage Temperature Range
-65°C to +150°C
Lead Temperature
(Soldering, 10 seconds)
Nole I: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual·ln-Llne Package
OUTPUT I
CONTROL
GI

....

SELECT 8 2

.4

Select
Inputs

t!!-vCC
A

...

"

.----

\.t

IC,.2 I- 1-'----

....

15 OUTPUT
CONTROL
G2
14

smeT A

~

r-t- l - t!!-.2C3

IC 2...! 1-1DATA
INPUTS

IC12 1-1-

IC O....!.

OUTPUT Y17

GN

8

8

B

B

A

A

X

X

- +-

~T
....

o...!

t- l - f!DATA
INPUTS

f-I- ,!L 2CI

Data Inputs

Output
Control

Output

B

A

CO

C1

C2

C3

G

Y

X
L
L
L
L
H
H
H
H

X
L
L
H
H
L
L
H
H

X
L
H
X
X
X
X
X
X

X
X
X
L
H
X
X
X
X

X
X
X
X
X
L
H
X
X

X
X
X
X
X
X
X
L
H

H
L

Z

L
L
L
L
L
L
L

L
H
L
H
L
H
L
H

Address inputs A and B are common to both sections
H = High Level, L = Low Level, X = Don't Care. Z = High Impedance

f-I- fli. 2CO

T.<...

9

OUTPUT Y2

TL/F/6301·1

54AS253 (J)

74AS253 (J,N)

This document contains information on a product under development. NSC reserves the right to change or discontinue this product without notice.

3-117

•

C")

~

~
~

Recommended Operating Conditions
DM54AS253
Parameter

:i!:

-c
C ")
It)

Supply Voltage, VCC

DM74AS253

Min

Nom

Max

Min

Nom

Max

4.5

5'

5.5

4.5

5

5.5

Unit

V
V

N

High Level Input Voltage, VIH

~
It)

Low Level Input Voltage, VIL

0.8

0.8

V

:i!:

High Level Output Current, 10H

-12

-15

mA

Low Level Output Current, 10L

32

48

mA

Max

Unit

-1.2

V

2

2

(IJ

c

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee =5V, TA =25'C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.SV, liN = -18mA

Min

VOH

High Level Output
Voltage

VCC = 4.SV, 10H = Max

2.4

10H = - 2mA, VOC =4.SV to S.SV
VOL

II

IIH

Low Level Output
Voltage

VCC = 4.SV, 10L = Max

Input Current at
Max Input Voltage

VCC = S.SV, VIN = 7V

High Level Input Current

Typ

V

VCC-2
0.3S

0.5

V

A,S

0.2

rnA

All Others

0.1
40

VCC = S.SV, VIN = 2.7V A,S

Low Level Input Current

VCC = S.SV
VIN = 0.4V

}lA

20

All Others
IlL

V

3.2

A,S

-0.6

-1

All others

-0.3

-O.S

rnA

-112

rnA

VCC = S.SV, VOUT = 2.7V

SO

}lA

Off-State Output
Current, Low Bias

VCC = S.SV, VOUT =O.4V

-SO

}lA

Supply Current

VCC = 5.5V

rnA

10

Output Drive Current

VCC = S.5V, VOUT = 2.25V

10ZH

Off-State Output
Current, High Sias

10ZL

ICC

3·118

- 30

Outputs high

17

29

Outputs low

20

32

Outputs
disabled

21

33

Switching Characteristics

over re.commended operating free air temperature range (Note 1).

All typical values are measured at Vee =SV, TA =2SoC.
DM74AS253

DM54AS253
Parameter

From

To

Conditions

Typ

Typ

Max

Unit

Max

Min

4

14.S

4

13.S

ns

4

12

4

11.S

ns

3

8.S

3

7.S

ns

3

8.S

3

7.S

ns

4

13

4

12.S

ns

4

12

4

11.S

ns

tHZ, Output Disable Time
From High Level

2

6.S

2

6

ns

tLZ, Output Disable Time
From Low Level

2

8

2

7

ns

tPLH, Low to high Level Output

Min

Select
tPHL, High to low Level Output

y
tPLH, Low to high Level Output
Data
tpHL, High to low Level Output

VCC =
4.S to S.SV
CL = SO pF
RL = SOO!l

tZH, Output Enable Time
to High Level
tZL, Output Enable Time
to Low Level

Output
Control

y

Note 1: See Section 1 for test waveforms and output load.

Logic Diagram
crUTPUT
I
CONTRcrl ''''If.;..I---4i1D - - - - - - - - - - - - - - - - - - - ,
ICcr~6:..-

++-L-/

__________

-+--+-+-"""-..../

ICI...;5::....-_ _ _ _ _ _ _ _ _

crUTPUT
YI

crATA I

++++-L..../

IC1...;4:.-_ _ _ _ _ _ _ _

IC3 j3!...---------+:t:$$:t:)
SElECT {

B 1

A~I~4-!:>O-~-OI:>---r-+

1Ccr..:.l ::..,cr- - - - - - - - - 4 H H H - I , " ' \

1CI..:.I,:.1- - - - - - - - - t - t - H t - r " ' \
DATA 1

1C1-'1.:..1--------,~I==:jl=rJ

9 OUTPUT
Y1

1C3..:.: . ,3---------I::::t:==l[)
1

crUTPUT ~1,,"5- - - 4 1 l D - - - - - - - - - - - - - - - - - - '
CcrNTRcrl G1

TLtF/6301-2

3-119

~ ~National
t!

:E

a

Semiconductor

e DM54AS/DM74AS257, 258 TRI·STATE® Quad 1 of 2 Line
~ Data Selectors/Multiplexers
Lt)

:E

c
r-:

~t!

:E

c

;:::
Lt)

~

~
:E

c

General Description

•

These data selectors/multiplexers contain inverters and
drivers to supply full on-chip data selection to the four TRISTATE outputs that can interface directly with data lines of
bus-organized systems. A 4-bit word selected from one of
two sources is routed to the four outputs. The AS257 presents true data whereas the AS258 presents inverted data
to minimize propagation delay time.
This TRI-STATE output feature means that n-bit (paralleled)
data selectors with up to 300 sources can be implemented
for data buses. It also permits the use of standard TIL registers for data retention throughout the system.

Improved AC Performance Over Schottky. Low Power
Schottky. and' Advanced Low Power Schottky
Counterparts.

• TRI·STATE Buffer-Type Outputs Drive Bus
Lines Directly.
•
•
•
•

Expand any data input point.
Multiplex dual data buses.
General four functions' o,f two variables (one variable is
'
common).
Source programmable counters.

Absolute Maximum Ratings
Features
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.

•

Advanced Oxide-Isolated. Ion-Implanted Schottky TIL
Process.
Functionally and Pin for Pin Compatible with Schottky.
Low Power Schottky. and Advanced Low Power
Schottky TIL Counterpart.

•

Connection Diagram

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS
DM74AS
Storage Temperature Range

(Note 1)
'7V
7V

-55°C to 125°C
O°C to 70 o'C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the salety 01 the device can not be guaranteed. The device should
not be operated at these limits. The parametric values dell ned In the
"'Electrical Characteristics"' table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions"' table will
deline the conditions lor actual device operation.

Function Table

Dual-In-Llne Package
OUTPUT tNPUTS OUTPUT INPUTS
VCCCONTROL4A'4B
4Y

3A"3B

l~s

OUTPUT
3Y

bs b4 b3 112 \11 bo 9

Inputs

J J J 1 I I
G

4A

48

4Y

3A

S

Output
Control

38

H
L
L
L
L

3Y
1A

18

1Y

2A

28

2Y

I I I I II
.
1
12
13
SELECT 1A . 18

'iNPiiTS

15 Is

14
1Y
2A
OUTPUT

28

'"iNPiiTS'

17
18
2Y
GND
OUTPUT

Select

A

B

AS257

AS258

X

X

L
L
H
H

L
H

X
X
X

X
X

L
H

Z
L
H
L
H

Z
H
L
H
L

H - High Level. L - Low Level, X - Don't Care
Z - High Impedance (all)

TL/F16107·1

54AS257 (J)
. 54AS258 (J)

Output Y

74AS257 (J,N)
74AS258 (J,N)

3-120

---------------------------------------------------------------------,0
Recommen~ed

s:
en

Operating Conditions
DM54AS257,258

Parameter

Supply Voltage, VCC

,

DM74AS257,258
Unit

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

5.5

V

High Level Output Voltage, VOH

5.5

High Level Input Voltage, VIH

2

V

2
0.8

Low Level Input Voltage, VIL

0.8

V

~

-s:
en
.....

o

~

~

en

.....
o

~

High Level Output Current, 10H

-12

-15

mA

Low Level Output Current, 10L

32

48

mA

Electrical Characteristics over recommended operating free air temperature range.

~en
N

All typical values are measured at Vee = 5V, TA = 25°C.
. Symbol

s:

-s:o
CQ

Parameter

Conditions

Min

VIK

Input Clamp Voltage

VCC

=

4.5V II

VOH

High Level Output
Voltage

VCC

=

4.5V, 10H

=

Typ

-18mA
=

IOH= -2mA, VCC=4.5Vto 5.5V

Unit

-1.2

V

3.2

2.4

MAX

Max

Vcc -2V

V

~
.»

V

en

~

CQ

VOL

Low Level Output
Voltage

VCC

=

4.5V, 10L

II

Max High Input Current

VCC

=

5.5V VIH = 7V

IIH

IlL

High Level Input Current

Low Level Input Current

=

0.5

V

A,B,G

0.1

mA

Select

0.2

A,B,G

20

Select

40

Select

-1

0.35

MAX

VCC = 5.5V VIH = 2.7V

VCC = 5.5V VIL = 0.4V

-112

mA

VCC = 5.5V
Vo = 2.7V

50

/i A

VCC = 5.5V
Vo = O.4V

-50'

/i A

12.9

19.7

inA

8.8

13.5

mA

19

30.6

mA

15.8

24.6

mA

19.7

31.9

mA

15.5

25.2

mA

10

Output Drive Current

VCC = 5.5V, Vo = 2.25V

10ZH

Off· State Output
Current, High Level
Voltage Applied

10ZL

Off·State Output
Current, Low Level
Voltage Applied

ICCH

Supply
Current

AS257

-30

Outputs High

AS258
Supply
Current

AS257

VCC =5.5V
Outputs OiJen

Outputs Low

AS258
,ICCZ

Supply
Current

AS257

mA

-0.5

All others

ICCL

/i A

Outputs Disabled

AS258

3·121

!

•

'AS257 Switching Characteristics over recommended operating free air temperature range (Note 1)
All typical values are measured at Vee = 5V, TA = 25°C.
Symbol

Parameter

From

To

"{:ondltions

tpLH

Propagation Delay Time,
Low to High Level Output

Data

Any
Y

tpHL

Propagation Delay Time,
High to Low Level Output

Vee = 4.5V to 5.5V,
C L =50 pF,
R L =5000'

tpLH

Propagation Delay Time,
Low to Hi.9h Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

tZH

Output Enable Time to
High Level

tZL

Output Enable Time to
Low Level

tHZ

Output Disable Time,
from High Level

-t LZ

Output Disable Time,
from Low Level

Select

Output
Control

Output
Control

Any
Y

Any
Y

Any
Y

DM54AS257

DM74AS257
Min

1

6.5

1

5.5

ns

1

7

1

6

ns

2

12

2

11

ns

2

10.5

2

10

ns

2

8.5

2

-7.5

ns

2

10.5

2

9.5

ns

1.5

8

1.5

6.5

ns

2

8

2

7

ns

Typ

Typ

Max

Units

Max

Min

'AS258 Switching Characteristics over recommended operating free air temperature range (Note 1)
All typical values are measured at Vee = 5V, TA = 25°C.
Symbol

Parameter

From

To

Conditions

tpLH

Propagation Delay Time,
Low to High Level Output

Data

Any
Y

tpHL

Propagation Delay Time,
High to Low Level Output

Vee=4.5V to 5.5V,
. C L =50 pF,
RL=500!l

tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

tZH

Output Enable Time to
High Level

tZL

Output Enable Time to
Low Level

tHZ

Output Disable Time,
from High Level

Select

Output
Control-

Any
Y

Any
Y

DM54AS258
Min
1

5.5

1

5

ns

1

5

1

4

ns

2

11

2

9.5

2

11

2

10

ns

2

8

ns

2

10

ns

Any
Y

tLZ _ Output Disable Time,
from Low Level
Nolel: See Section 1 for test waveforms and output load.

3·122

8.5
11

Typ

Max

Units

Min

2
Output
Control

DM74AS258

Max

2

Typ

,

ns

1.5

7

1.5

6

ns

2

8.5

2

6.5

ns

Logic Diagrams

54/74AS257
OUTPUT 15
CONTROL
AI

BI

Az

Bz
A3

~

A.4

II

10

14

84
SELECT

TLlFf6107·2

54/74AS258

c~~~~I..:.::15-<,>-------.......,

--------r-.....

AI ......

---+-----r-.....

BI ......

---+--+--r-.....

AZ ......

---+--+--r-.....

8Z ......

~~---+---+--r""'"

TLlFf6107·3

3·123

.
~ Semiconductor

PRELIMINARY

~National

DM54AS264/DM74AS264 Look-Ahead Carry Generator
General Description

Features

This circuit is a high speed, look-ahead carry generator
capable of anticipating a carry across four counters. It is
cascadable to perform look-ahead across N-bl! counters.
Carry, generate-carry and propagate-carry output functions are provided as shown in the connection diagram.

• Advanced oxide-isolated ion implanted Schottky TTL
process

This circuit can accommodate counters which have eithJr
low level carry pulse or high level carry pulse outputs, and
can provide high speed carry look·ahead capability for any
word length. Each AS264 generates the look-ahead (antiCipated carry) across a group of four counters, and in ad·
dition, other carry look·ahead circuits may be employed to
anticipate a carry across sections of four look-ahead
packages up to N bits. This method of cascading circuits
to perform multl·level look-ahead is illustrated under
Typical Applications.

• PNP Inputs reduce input loading

• Switching specification at 50 pF
• Switching specifications guaranteed over full
temperature range and Vee range

Absolute Maximum Ratings
Supply Voltage, Vee
7V
Input Voltage
7V
Operating Free-Air Temperature Range
DM54AS264.
-55·Cto + 125·C
DM74AS264
0·Ct070·C
Storage Temperature Range
-65·Cto + 150·C
Not. 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical CharacteristiCS" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define-.the conditions for actual device operation.

Connection Diagram

Dual·ln·Line Package

G1- 1

v

16 -Vee

P1- 2

15 -P2

GO- 3

14 -G2

PO- 4

13 -Cn

INPUTS

G3- 5

-cn+x]
11 -,Cn+y

12

P3- 6

OUTPUTS
POUTPUT -

7

10-G

GNO- 8

9

-Cn+z

TOP VIEW
TLlFf6302·1

DM54AS264 (J)

DM74AS264 (N)

This document contains information on a product under development. NSC reserves the right to change or discontinue this product without notice.

3-124

Recommended Operating Conditions
DM54AS264

'. Parameter

Symbol
Vee

Supply Voltage

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

10H

High Level Output Current

10l

Low Level Output Current

TA

Operating Free-Air Temperature

DM74AS264

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

2

Units
V

2

V

O.B

O.B

-2
20
-55

125

0

V

-2

mA

20

mA

70

·C

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise specified)
DM74AS264

DM54AS264
Parameter

Symbol

Conditions

Min

VIK

Input Clamp Voltage Vee = 4.5V, II = -18 mA

VOH

High Level Output
Voltage

Vee=4.5V to 5.5V, IOH=-2 mA

VOL

Low Level Output
Voltage

Vee=4.5V, IOl=20 mA

II

Cn

Vee = 5.5V, V I =7V

Typ
(Note 1)

Typ
(Note 1)

Max
-1.2

,

0.3

0.5

V,

"A

500

500

700

700

'BOO

BOO

400

400

P2

300

300

200

200

(

100

100

GO,G2

140

140

Gl

160

160

G3, PO, Pl

80

BO

P2

60

60

P3

40

Cn

Cn

Vee = 5.5V, VI = 2.7V

Vee = 5.5V, VI =0.4V

GO

-2.5

-3.5

-3.5

-4

-4

G3, PO, Pl

-2

-?

P2

-1

-1

P3

-1.5

-1.5

-30

Vee = 5.5V, Vo = 2.25V

-112

"A

40

,-2.5

Gl,G2

10 (Note 2) Output Drive
Current

V

0.5

G3, PO, P1

P3

Units

V

Vee- 2
0.3

Gl

III

Min

-1.2
Vee- 2

GO,G7

IIH

Max

-30

-112

mA

mA

leeH

Supply Current Vo(ith Vee =5.5V
Outputs High

26

26

mA

leel

Supply Current with Vee =5.5V
Outputs Low

2B

28

rnA

3-125

, Switching Characteristics over recommended supply and temperature'range (Note 1)
All typical values are measured at Vce = 5V, TA = 25°C.
From
(Input)

Parameter

To
Conditions
(Output)

DM54AS264
Min

DM74A6264

Typ

Max

Min

lYP

tpLH Propagation Delay Time, GO,G1,
Cn+x, C L =50 pF,
Cn+ y, RL=5001l
Low-to-High Level Output .G2,G3,
PO, P1, orCn + z
tpHL Propagation Delay Time,
P2, or P3
High-to-Low Level Output

5

5

5

5

tpLH Propagation Delay Time, GO,G1,
Low-to-High Level Output G2,G3,
P1, P2,
tpHL Propagation Delay Time,
or P3
High-to-Low Level Output

G

5

5

5

5

PO, P1,
tpLH Propagation Delay Time,
Low-to-High Level Output P2, or P3

P

5

5

5

5

6

6

5

5

tpHL Propagation Delay Time,
High-to-Low Lev~1 Output
tpLH Propagation pelay Time,
Low-to-High Level Output

Cn

C n + x;
'C n + y,
or Cn + z

tpHL Propagatlo'n Delay Time,
High-to-Low Level.Output

Max

ns

ns

ns,

ns

Nole 1: See Section 1 for test waveforms and output load.

Function Tables
Logic Equations for the' AS264 are:
Active High Carry
Counters
(Cn=H)

Active Low Carry
.Counters
(Cn=L)

-

Cn+x=GO
Cn+y=GO 0 G1
Cn+z=GOoG1 o G2
G=GOoG1 o G2oG3
p=O

Inputs

Cn+x=PO
Cn+y=;~oP1

_
Cn +z = PO 0 1"1 0 P2
P=PO+P1+P2+P3
G = P1 G3 G2 G1 + P2 G3 G2 G1
.+P3G3

Output

Inputs

Output

G3

G2

G1

GO

P3

P2

P1

PO

G

P3

Cn

P

L

X
L

X
X
X

X

X
X
X
X

X
X

X
X

X
X
X

X
X
X
X

L
L
L
L
L
H

L 1 L 1 L 1 L 1 L
All Other Combinations

L
H

L
L
L
L
X
L
L
L
X
X
L
L
All Other
Combinations

X
X
X

L
L

L

P21 P1

PO

Output

Inputs
Cn

Cn+ x

H

X

X

H

H
H
L

GO

PO

H
H

All Other
Combinations
Inputs

Inpuis

Output

G1

GO

P1

PO

Cn

Cn+ y

G2

G1

GO

H
H
H

X

H

X

X

H
H
H
L

H
H
H
H

X

X

H
X
H
X
H
X
X
H
All Other Combinations

,3-126

P2

Output
~1

H
X
X
H
X
H
X
X
H
H
H
H
X
X
All Other Combinations

PO

Cn

Cn+z

X
X
H
X

X
X

H
H
H
H
L

X
H

Units

Logic Diagram

(7)

.... R

I

(10)

P3~(6)+-~~+-~~+-;-,

-

G3,l:;,(5)4-~_+-~""'+-LIJ}I

I

•

-r(11) Cn+y

PI (2)
Gl (1)

I

Cn (13)

1

-

,--_]r--... (12) Cn+>

PO (4)
GO (3)

TlIF/6302·2

Vee; pin 16
GND;plnB

3-127

I

Typical Applications

~

:E

c

!

Active High Carry Scheme

EN~~~:!'--

....- - - - - - -....- - - - - -....- - - - - - . . . . . ,

:E

c

COUT

TlIF/6302·3

Active Lolli Carry Scheme
COUNT
ENABLEA-......~-------.---..,...---....- - - - - - - .
COUNT
ENABLE B -1>-t--l~

....

-~

COUT

TL/F/6302·4

3-128

C

PRELIMINARY'

~National

~ Semiconductor

s::
(J1

Io

DM54AS280/DM74AS280 9·Bit Parity Generator/Checker

C

s::
~

General Description
These universal, 9-bit parity generators/checkers utilize
advanced Schottky high performance circuitry and feature odd/even outputs to facilitate operation of either odd
or even parity applications_ The word length capability is
easily expanded by cascading.
The AS280 can be used to upgrade the performance of
most systems utilizing the '180 parity generator/checker.
Although the AS280 is implemented,without expander inputs, the corresponding function is provided by the availability of an input at pin 4 and no internal connection at
pin 3. This permits the AS280to be substituted for the '180
in existing designs to produce identical function even if
'AS280s are mixed with existing '180s.

Features
•

Generates either odd or even parity for nine data lines

•

Inputs are buffered to lower the drive requirements

•

Can be used to upgrade existing systems using MSI
parity circuits

•

Cascadable for N-blts

Connection Diagram

•

Advanced oxide-isolated, ion-implanted Schottky TTL
process

•

Switching specifications at 50 pF

•

Switching specifications guaranteed over full
temperature and Vce range

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS
DM74AS
Storage Temperature Range

7V
7V
-55°e to 125°C
O°C to 70°C
-65°C to 150 0 e

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. '(he "Recommended Operating Conditions" table will
define the conditions for actual device operation.
'

Function Table
~,

\

Dual-ln-L1ne Package

.

vIC,. 1,3
F

INPUTS
E

D

1,2 I"

,'0 i.

C

A

Number of Inputs (A
Thru I) that are High

e

I I I I I

r-,

;--

,

G

J

,1 2
H

~

INPUTS

I I I
J: . t !6
. I'

I
INPUT

5

EVEN

ODD

Outputs
~

Even

~Odd

0,2,4,6,8

H

L

1,3,5,7,9

L

H

L= Low State
H =, High State

G!:

OUTPUTS

TL/F/6303-1

54AS280(J)

74AS280 (J, N)

This document contains Information on a product under development. NSC reserves the right to change or discontinue this product without notice.

3-129

~

o

g
~
:!:

-~
c

~
:!:
c

Recommended Operating Conditions
DM54AS280
Parameter
Supply Voltage, VCC
High Level Input Voltage, VIH

DM74AS280'

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

Unit
V
V

2

-

0.8

0.8

V

High Level Output Current, 10H

-2

-2

mA

Low Level Output Current, 10L

20

20

mA

Max

Unit

-1.2

V

Low Level Input Voltage, VIL

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25°C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.5V, II = -18 mA

VOH

High Level Output
Voltage

10H = - 2m A, VCC = 4.5V to 5.5V

VOL

Low Level Output
Voltage

VCC = 4.5V
10L = Max

II

Max High Input Current

IIH

Min

Typ

V

VCC-2

0.5

V

VCC = 5.5V, VIH = 7V

0.1

mA

High Level Input Current

VCC = 5.5V, VIH = 2.7V

20

Il A

IlL

Low Level Input Current

Vec = 5.5V, VIL = 0.4V

-0.5

mA-

IO

Output Drive Current

VCC = 5.5V

Vo = 2.25V

-112

mA

ICC

Supply Current

VCC = 5.5V

DM54AS

25

40

mA

25

35

0.35

-30

,.

DM74AS

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V, TA = 25°C.
Symbol

Parameter

From

tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

tpLH

Propagation Delay Time, . Data
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

Data

To

Conditions

E Even

Vee = 4.5V to 5.5V,
C L =50pF,
RL =500{l

DM54AS280
Typ Max

Min

EOdd

Note 1: See Section 1 for test waveforms and output load.

3·130

DM74AS280
Typ Max

Units

Min

2

15

2

14

ns

2

15

2

14

ns

2

15

2

14

ns

2

15

2

14

ns

•

c

s:

Logic Diagram

(J1

~

-s:
o

C

I
TLIF16303·2

Typical Applications
Three AS280s can be used to implement a 25·line parity
generator/checker.

Longer word lengths can be implemented by cascading
AS280s. As shown in Figure 2, parity can be generated for
w'ord lengths up to 81 bits.

As an alternative, the outputs of two or three parity gener·
ators/checkers can be decoded with a 2·input (AS8S) or
3·input (S135) exclusive·OR gate for 18 or 27·line parity
applications.

A
B

g

EVEN

AS2BO

EVEN

E AS2BO
F
G
H
I

H
L
H
L

=EVEN
=ODD
=

ODD

= EVEN

~

D'

~ L-~:::::::::::::1::----:l
"
A

B

EVEN

C

E AS2BO
F

D
E

G
H

F
G

I

H

EVEN

H
L

= EVEN
= ODD

AS2BO

"

ODD

H = EVEN
L = ODD

I

A
B

g

TUFI6303-3

FIGURE 1. 2S-Line Parity/Generator Checker

"
EVEN

E AS2BO
F
G
H
I

TO OTHER

5280'5

TUFJ6303-4

FIGURE 2. 81-Line Parity/Generator Checker

3·131

Nr-----------------------------------------------------~~---------------,

~ ~National

PRELIMINARY

~ ~ Semiconductor
:E

c

C\i

DM54AS282/DM74AS282 Look·Ahead Carry Generator with

re Selectable Carty Inputs

U)

~
U)

Features

:E General Description

c

• Selectable input version of 'AS182 allows double
precision carry .
• Advanced oxide-Isolated ion·lmplanted
Schottky TIL process

This circuit is a high-speed, look-ahead carry generator
capable of anticipating a carry across four binary adders
or groups of adders_ It is cascadable to perform full lookahead across n-blt ·adders. Carry, generate-carry, and
propagate-carry functions are provided.

• SWitching specification at 50 pF
• Switching specifications guaranteed over full
temperature and Vee range
'
• PNP Inputs reduce Input loading

When used in conjunction with the' AS881 arithmetic logic
unit, this generator provides high-speed carry look-ahead
capability for any word length. Each 'AS282 generates the
look-ahead (anticipated carry) across a group of four ALUs
and, in addition, other carry look·ahead circuits may be
employed to anticipate carry across sections of four lookahead packages up to n bits. The method of cascading circuits to perform multi-level look-ahead is illustrated under
Typical Applications.

Absolute Maximum Ratings (Note 1)
Supply Voltage, Vee
Input Voltage
Operating Free-Air Temperature Range
DM54AS282
DM74AS282
Storage Temperature Range

The carry functions (inputs, outputs, generate and propagate) of the look·ahead generator are implemented in compatible forms for direct connection to the 'AS881 ALU. The
carry inputs are selectable in either active high or active
low.

7V
7V
- 55·Cto 125·C
0·Ct070·C
-65·Ct0150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can nol be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" lable will
define the condit'ions for actual device operation.

Connection Diagram
Dual-In-Llne Package

u

G1-1

ZO

I-- Vee

P1-2

191-- P2

GO- 3

18

r- G2

PO-4

17

r- Cnl

G3- 5

lS-Cn2

P3-S

151-- Cn+x

50- 7

14~Cn+y

51- 8
p,..... 9

121-- G

GNO -",,1,,-0_ _ _ _l:.:.JlI-- Cn+z
TOP VIEW
TLlF/6304-1

DM54AS282 (J)

DM74AS282 (N)

This document contains information on a product under development. NSC reserves the right to change or discontinue this product without notice.

3-132

Recommended Operating Conditions
Symbol

DM54AS282

Parameter

Vcc

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

10H

High Level Output Current

DM74AS282

Typ

Max

Min

'iYP

Max

4.5

5

5.5

4.5

5

5.5

2

10L

Low Level Output Current
Operating Free·Air Temperature

V
V

2

-2
20
-55

V

O.B

O.B

TA

Units

Min

125

0

-2

mA

20

mA

70

DC

Electrical Characteristics over recommended operating free·air temperature range (unless otherwise specified)
DM54AS282
Symbol

Parameter

,

Conditions

.

VIK

Input Clamp Voltage Vcc=4.5V, 11= -18 mA

VOH

High Level Output
Voltage

VCC =4.5Vto 5.5V, 10H"; -2 mA

VOL

Low Level Output
Voltage

Vcc=4.5V, IOL=20 mA

C n 1, C n 2

Vcc= 5.5V, VI =7V

II

IIH

Min

Typ
(Note 1)

Max

Min

Typ
(Note 1)

Max
-1.2

-1.2
Vcc-2
0.3

0.5

0.3

V
p.A

200

200

200

200

P2

300

300

PO, P1, G3

400

400

GO,G2

700

700

G1

800

BOO

Vcc= 5.5V, VI=2.7V

40

40

40

40

P2

60

60

PO, P1, G3

BO

BO

GO,G2

140

140

G1

160

160

-1

-1

-1

-1

-1.5

-1.5

-2

-2

-3.5

-3.5

C n 1, C n2

Vcc= 5.5V, VI =0.4V

50,51, P3
P2
PO, P1, G3
GO,G2
G1
10 (Note 2) Output Drive
Current

-4
-30

Vcc = 5.5V, Vo = 2.25V

.

ICCH

Supply Current with Vcc= 5.5V
Outputs High

ICCL

Supply Current with VCC= 5.5V
Outputs Low

,

-117

p.A

mA

-4
-30

-112

mA

22

22

mA

26

26

mA

Note 1: Aillypical values are at VCC= 5V, TA=25"C.
Note 2: The output conditions have been chosen to produce a current that c.losely approximates one-half of the true short-circuit current lOS.

3·133

V

0.5

50,51, P3

C n 1, Cn 2

Units

V

Vcc-2

SO,S1,P3

IlL

DM74AS282

Switching Characteristics over recommended supply and temperature range (Note 1)
Sym

From
(Input)

Parameter

tpLH Propagation Delay Time,
Low-to-High Level Output
tpHL Propagation Delay Time,
High-to-Low Level Output
tpLH Propagation Delay Time,
Low-to-High Level Output
tpHL Propagation Delay Time,
High-to-Low Level Output

To
Conditions
(Output)

DM74AS282

DM54AS282
Min

Typ

Max

Min

Typ

GO,G1, C n + x1 C L =50pF,
G2, G3,
C n + y , RL =5000
PO, P1, or C n + z
P2, or P3

5

5

5

5

GO,G1,
G2,G3,
P1, P2,
or P3

6

6

5

5

5

5

5

5

C n + xJ
C n + y,
or C n + z

6

6

6

6

C'
n

6

6

6

6

G

PO, P1,
tpLH Propagation Delay Time,
Low-to-High Level Output P2, or P3

P

tpHL Propagation Delay Time,
High-to-Low Level Output
tpLH Propagation 'Delay Time,
Low-to-High level Output

Cn

tpHL Propagation Delay Time,
High-to-Low Level Output
tpLH Propagation Delay Time, C n 1, C n 2,
Low-to-High Level Output S1, S2
tpHL Propagation Delay Time,
High-to-Low Level Output

Max

Units
ns

ns

ns

ns

ns

Note 1: See Section 1.for t~st waveforms and output load.

"-

Typical Applicat~
32 Bit Look-Ahead Carry with Double Precision Carry

CLOCK

ClK 0
Q AS74

~~~rO~~~rO
~

Cn -

~

GP

GO PO
Cn1
Cn2
S O - SO
S1---:- S1

-

~

GP

G1 P1

Cn+x

,

~

GP

Cn + v

G2 P2

Cn+ z

~

GP

GP

G3 P3

GO PO

' - Cn

AS282

~

~

GP

Cn+lC

G1 P1

~

GP

Cn+y

G2 P2

GP

C1I+Z

G3 P3

AS282

.
TLlF/6304·2

\

3-134

Logic Diagram

P3 (6)
G3 (5)

(2)

PI (1)
Gl

Cn

(13)

(4) .

PO (3)
GO
(17)

Cnl
(8)

Sl

(7)

(13)

SO

Cn'

Vcc=pin 20
GND=pin 10

(16)

Cn2 ""'""-........ ~~--...

TLIF/6304-3

3-135

~National

PRELIMINARY

~ Semiconductor

DM54AS286/DM74AS286 9-Bit Parity GeneratorlChecker
with Bus-Driver Parity 1/0 Port
General Description
These universal, 9-bit parity generatorslcheckers utilize
advanced Schottky high performance circuitry and feature oddleven outputs to facilitate operation of either odd
or even parity applications. The word length capability is
easily expanded by cascading.
.
The 'AS286 can be usd to upgrade the performance of
most systems utilizing the 'AS180, 'AS280 parity
generatorl checker. Although the 'AS286 is implemented
without expander inputs, the corresponding function is
provided by the availability of an input at pin 4. Pin 4 (XMIT)
Is a control line which makes parity error output active and
parity an Input port when "high"; when "low", parity error
output is inactive and parity becomes an output port. In
addition, parity 110 control circuitry contains a feature to
keep the 110 port in the TRI-STATE'" during power up or
down to prevent bus glitches.

Features
• PNP inputs to reduce bus 10,ading
• Generates either odd or even parity for nine data lines

Connection Diagram

• Inputs are buffered to lower the drive requirements
• Can be used to upgrade existing systems using MSI
parity circuits
I
• Cascadable for n-bits
• Switching specifications at 50 pF
• Switching specifications guaranteed over full
temperatu're and Vcc range
• A parity 110 portable to drive bus

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

7V
7V
-65·Ct0150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Dual-In-Line Package

G- 1

U

H- 2

141- Vee
13 r

F

XMIT- 3

12rE

1_ 4

11 !-D

PARITY ERRDR -

5

PARITY 110 -

6

9 !-B

GND- 7

8 !-A

10 !-C

Number of Inputs
(A thru q thai ara High
0,2,4,6,8
1,3,5,7,9
0,2,4,6,8
0,2,4,6,8
1,3,5,7,9
1,3,5,7,9

Parity 110
Input

Output

NIA
N/A
H

H
L
N/A
N/A
N/A
NIA

L
H
L

XMIT
L
L'
H
H
H
H

Parity
Error
H
H
H
L
L
H

Modaof
Operation
Parity
Generator

Parity
Checker
Parity
Checker

TOP VIEW
TLlF16305·1

DM54AS286 (J) DM74AS286 (J, N)

This document contains information on a product under development. NSC reserves the right to change or discontinue this product without notice.

3-136

c

s:
C11

Recommended Operating Conditions
Symbol

DM54AS286

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

DM74AS286

Min

Typ

Max

Min

Typ

4.5

5

5.5

4.5

5

2

Max

,

5.5

2

Units

V

Low Level Input Voltage

0.8

0.8

IOH

High Level Output Current

Parity 110

-12

-15

mA

Parity Error

-2

-2

mA

IOL

Low Level Output Current

Parity 110

32

48

mA

20

mA

TA

Operating Free·Air Temperature

70

'C

20
-55

125

0

V

Electrical Characteristics over recommended free·air temperature range (Note 1)
All typical values are measured at Vee = 5V, TA = 25'C.
Sym

Parameter

DM54AS286

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V, liN = -18 mA

VOH

High Level Output Voltage

IOH = Max, Vee = 4.5V

Parity Error

Vee = 4.5V, 10L = 20 mA

Parity 110

Vee = 4.5V, 10L = 32 mA

Typ

2.4

3.2

DM74AS286
Max

Min

Typ

2.4

3.2

-1.2

Vee- 2

'OH=-2mA
Vee = 4.5V to 5.5V
VOL

Min

-1.2

0.35

0.5

Input Current at Max
Input Voltage

Vee=S.5V, VIH=7V
(VI = 5.5V for Parity I/O)

IIH

High Level Input Current

Vee =5.5V,
VIH =2.7V

0.35

0.5

V
V

0.5

V

0.1

mA

20

20

p.A

50

50

0.1

I Others

V

V

0.5

I Parity I/O

Units

V

Vee- 2

Vee = 4.5V, 10L = 48 mA
II

Max

IlL

Low Level Input Current

Vee = 5.5V, VIL = 0.4V

-0.5

-0.5

mA

10ZH

High Level TRI·STATE
Output Current

Vee = 5.5V, V = 2.7V
I/O Port Pin 6

20

20

p.A

10ZL

Low Level TRI·STATE
Output Current

Vee = 5.5V, V=O.4V
I/O Port Pin 6

-0.5

-0.5

mA

10

Output Drive Current

Vee = 5.5V, VOUT = 2.25V

-112

mA

lee

Supply Current

Vee = 5.5V
Transmit Mode
Input of Pin 3 Low

42

42

mA

Receive Mode
Input of Pin 3 High

49

49

mA

Note 1: See Section 1 for lesl waveforms and output load.

"

3-137

-30

-112

-30

-s:
en

V

VIL

Parity Error

~

N
CO

C

~

N
CO

en

Switching Characteristics over recommended supply and"temperature range (Note 1)
All typical values are measured at Vee = 5V, TA = 25°C.
Sym

Parameter

From

DM54AS286

To

Min

Typ

DM74AS286
Max

Min

Typ

Max

Units

t pLH

Propagation Delay Time from Any Data
Input
Low to High Level Output

Parity 110
Pin 6

8

8

ns

tpHL

Propagation Delay Time from Any Data
High to Low Level Output
Input

Parity 110
Pin 6

8.5

8.5

ns

tpLH

Propagation Delay Time from Any Data Parity Error
Low to High Level Output
Input
Pin 5

9

9

ns

tpHL

Propagation belay Time from Any Data Parity Error
Input
Pin 5
High to Low Level Output

9.5

9.5

ns

tpLH

Propagation Delay Time from Parity 1/0 Parity Error
Pin 6
Pin 5
Low to High Level Output

5.0

5.0

ns

tpHL

Propagation Delay Time from Parity 1/0 Parity Error
High to Low Level Output
Pin6
Pin 5

6.0

6.0

ns

tPZL

Output Enable to Low Level

Control
Pin3

Parity 1/0
Pin 6

6

6

ns

tpZL

Output Disable from
Low Level

Control
Pin3

Parity 1/0
Pin 6

9.5

9.5

ns

tpZH

Output Disable from
High Level

Control
Pin 3

Parity 1/0
Pin 6

5

5

ns

tpHZ

Output En'a~le to High Level

Control
Pin 3

Parity 1/0
Pin 6

10

10

ns

"

Note 1: See Section 1 for test waveforms and output load.

,

,

3·138

.-----------------------------------------------------------------------,0
3:
C1I
~

1;;
I\)

I
14 XMIT
~A
-A B
.!.!! C
..g D

DATA
INPUTS

,.!1
1

3:
~

PARITY
ERRDR

E

I.J

G

H

-o

14

Vee

~ F

12

co
Q)

Number of
Inputs that
are Logic '1'

rL PARITY
RESULT

OUTPUT

0,2,4,6,8,10
1,3,5,7,9

J

I

Parity
Result
Output
Even
Odd

L
H

1-4 I

,.1

PARITY
lID
GND

TUF/6305-2

FIGURE 1. Dedicated 10·Bit Parity Sensing Configuration

SYSTEM
DATA
BUS

8 BIT DATA AND 1 BIT PARITY

.oil

Il"--

k

9

r ---- t------.-- -----,
8

I

O

DM54AS645'111 ,..

III

I

I
I
I

D.IR

~~

"'Il"--

I

I

• 1

1

B
LOCAL
DATA
BUS

'"

I

DM54AS286
PARITY 1/0
XMIT
PARITY
ERROR A-H
1 '"

,I-'"

:1
I

po..

1

B.I-'"

I

8

"'I .,.

I
I

DIRECTION RECEIVE
CONTROL MODE
PARITY

PARITY
SELECT

I
I
I

IL.. _ _ _ _ _ _ _ _ _
;~:~~_ _ _ _ _ JI
TLlF/6305·3

Direction
Control
(XMIT)

1/0
Direction
(Parity 1/0)

H

Input
(Receive)

H

Output
(Transmit)

H

L

Parity Check Result
(Parity Error)
Level
E Result
True
False
N/A

L

FIGURE 2. Bus 1/0 Parity Implementation

3·139

Parity Select
(Input I)
Level
Format
H
L

Even
Odd

~

Q)

9 DM54AS286s ARE
USEO IN FIXEO 10·BIT·
RECEIVING MOOE
(SEE FIGURE 1)

PARITY LINE
(BI·DlRECTIONAL)

PARITY

+---!~I/O

XMIT I+---------DIRECTION CONTROL
PARITY I-_________~~!~~~Ec~~gi
ERROR

RESULT
TLlF16305·4

Note: Parity format in this configuration is "odd parity"

FIGURE 3. 90·Bit Parity Generator/Checker Implementation
Using Device Expansion Techniques

3·140

PRELIMINARY

~National

a

Semiconductor

DM54AS352/DM74AS352' Dual 4-Line to 1-Line
Data Selector/Multiplel(er
General Description
This Data Selector/Multiplexer contains full on-chip decoding to select one-of-four data sources as a result of a
unique two-bit binary code at the Select inputs. Each of the
two Data Selector/Multiplexer circuits have their own separate Select, Data, and Strobe inputs and an inverting output
buffer. The Strobe .inputs, when at the high level, disable
their associated data inputs and force the corresponding
output to the high state. The Select input buffers incorporate internal overlap features to ensure that select input
changes do not cause invalid output transients.

Features
•

Advanced Oxide-isolated lon-implanted Schottky TTL
process.

•

Switching performance is guaranteed over full
temperature and VCC supply range.

•
•

Pin and functional compatible with the LS and Schottky
Family counterpart.
Improved output transient handling capability.

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS352
DM74AS352
Storage Temperature Range
Lead Temperature
(Soldering, 10 seconds)

(Note 1)
7V
7V

-55·C to 125·C
O·C to 70·C
-65·Cto 150·C
+300·C

Nole 1: The "Absolute Maximum Ratings" are Ihose values beyond
which Ihe safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Elect'rical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual·ln·Llne Package

VCC

STROBE A
2G SELECT ,

1,6

15

1'4

OUTPUT
2V.

DATA INPUTS
1,3

? J2~3
'i1

-"2

I
2C2

Select
Inputs

111 1,0 19
I

I

I

2Cl
2CO
B ii A A

2V

I

12G

~

~-ll~3

,

1

IT1

J,G

12

STROBE B
lG SELECT

B B A A
lCO
IV

I

lC2

lCl

I

I

I

14

15

16 17

13

DATA INPUTS

I

OUTPUT GND
IV

Strobe

Output

B

A

CO

C1

C2

C3

G

Y

X

X

X

L
L
L
L

L
L

L

X
X
X

X
X
X
X
X
L
H
X
X

X
X
X
X
X
X
X

H
L
L
L
L
L
L
L
L

H
H

H

Is

Data Inputs

H
H
H

H
H
L
L
H

H

H
X
X
X
X
X
X

L
H

X
X
X
X

L

H

L

H
L

H
L
H
L

Select inputs A and B are common to both sections
H = High Level. L = Low Level. X = Don't Care

TL/F/.6307·1

54AS352 (J)

74AS352 (J,N)

This document contains information on a product under development. NSC reserves the right to change or discontinue this product without notice.

3·141

Recommended Operating Conditions
DM54AS352
Parameter

Min

Supply Voltage, VCC

Nom

DM74AS352
Max

Min

5.5

4.5

4.5

\

High Level Input Voltage, VIH

.

2

Nom

Max
5.5

Unit
V

V

2

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Current, 10H

-12

-15

mA

Low Level Output Current, 10L

32

48

mA

Max

Unit

-1.2

V

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vce= 5V, TA = 25·C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.5V, liN = -18rnA

VOH

High Level Output
Voltage

VCC = 4.5V, 10H = Max

Min

10H= -2rnA, VCC=4.5Vto5.5V
VOL

Low Level Output
Voltage

VCC = 4.5V, 10L = Max

II

Input Current at
Max Input Voltage

VCC = 5.5V,
VIN = 7V

IIH

IlL

High Level Input Current

Low Level Input Current

VCC = 5.5V,
VIN = 2.7V

. VCC = 5.5V,
VIN = O.4V

2.4

Typ

3.2

V
V

VCC-2
0.5

V

A,S

0.2

mA

Others

0.1

A,S

40

Others

20

0.35

A,S

-0.3

-1

All others

-0.3

-0.5

10

Output Drive Current

Vee = 5.5V, VOUT = 2.25V

ICC

Supply Current

VCC = 5.5V

-30

p.A

rnA

-112

rnA
rnA

Outputs high

15.5

25

Outputs low

17.5

28

.

.

3·142

Switching Characteristics over recommended opera!ing free air temperature range (Note 1).
~II

typical values are measured at Vec = 5V. TA = 25°C.

DM54AS352
Parameter

From

To

Conditions

tpLH. Low to high Level Output

Typ

DM74AS352
Typ

Max

Unit

Max

Min

4

12.5

4

11

ns

4

14

4

13

ns

2

7.5

6.5

ns

2

7

6

ns

3

8

7

ns

4

13.5

12

ns

Min

Select
tpHL. High to low Level Output
tPLH. Low to high Level Output
Data

Y

tPHL. High to low Level Output

VCC =
4.5 to 5.5V
CL = 50 pF
RL = 500 f!

tPLH. Low to ·high Level Output
Strobe
tpHL. High to low Level Output
Note 1: See Section 1 for test waveforms and output load.

Logic Diagram
.......

STROBE GI

ICO

ICI

-v

---I

6

)-

5

L...,-+--

DATA I

Ie 2

le3

1

....
v

.....

v

2CO

--.

9 OUTPUT

}---

3

14

7 OUTPUT
VI

-=i..

4

2

....,......

I

_....
-v

-"
-.,

10
~

}-

2el 11

DATA 2
2e2

12

~

,

'- t----i

-

2e3 13
STROBE G2

15

}-

.......

-v

TLIF16307·2

3-143

V2

CO)
II)

CO)

~
t!

.
Semiconductor

~National

a
:i!:

PRELIMINARY

~ DM54AS353/DM74AS353 TRI-STATEI> Dual4-Line to
~

1-Liile Data Selector/Multiplexer

II)

General Description

~

:i!:
c

•

Pin and functional compatible with LS and Schottky
.
Family counterpart.

This Data Selector/Multiplexer contains full on-chip decod• Improved output transient handling capability.
ing to select one-of-four data sources as a result of a
• Output Control circuitry incorporates power-up TRIunique two-bit binary code at the Select inputs. Each of the
STATE feature.
two Data Selector/Multiplexer circuits have their own separate Select, Data, and Output Control inputs and an inverting TRI-STATE output buffer. The Output Control inputs,
Absolute Maximum Ratings (Note 1)
when at the high level, place the corresponding output in
the high impedance Off state. In order to prevent bus acSupply Voltage
7V
cess conflicts, output disable times are shorter than output
Input Voltage
7V
enable times. The Select input buffers incorporate internal . Operating Free Air Temperature Range
overlap features to ensure that select input changes do not
DM54AS353
-55°C to +125°C
cause invalid output transients.
DM74AS353
O°C to + 70°C
Storage Temperature Range
-65°C to +150°C
Lead Temperature
Features
(Soldering, 10 seconds)
•

Advanced Oxide-isolated lon-implanted Schottky TTL
process.
• Switching performance is guaranteed over full
temperature and Vee supply range.

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation ..

Connection Diagram

Function Table

Dual-ln-L1ne Package
Select
Inputs

DATA INPUTS

OUTPUT
B
CONTROL SELECT
1G

Data Inputs

Output
Control

Output

B

A

CO

C1

C2

C3

G

y

X
L
L
L
L
H
H
H
H

X
L
L
H
H
L
L
H
H

X
L
H
X
X
X
X
X
X

X
X
X
L
H
X
X
X
X

X
X
X
X
X
L
H
X
X

X
X
X
X
X
X
X
L
H

H
L
L
L
L
L
L
L
L

Z
H
L
H
L
H
L
H
L

Address inputs A and B are common to both sections
H - High Level. L ,. Low Level. X - Don't Care.
Z - High Impedance State

DATA INPUTS

TLlF16308-1

54AS353 (J)

74AS353 (J,N)

This document contains information on a product under development. NSC reserves the right to change or discontinue this product without notice.

3-144

Recommended Operating Conditions
DM54AS353
Parameter

Min

Nom

4.5

Supply Voltage, VCC
High Level Input Voltage, VIH

DM74AS353
Max

Min

5.5

4.5

Nom

Max

5.5

V
V

2

2

Unit

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Current, 10H

12

15

mA

Low Level Output Current, 10L

32

48

mA

Max

Unit

-1.2

V

Electrical Characteristics

over recommended operating free air temperature range.

All typical values are measured at Vee = 5V, TA = 25'C.
Symbol

Parameter

Conditions

VIK.

Input Clamp Voltage

VCC

~

4.5V, liN

VOH

High Level Output
Voltage

VCC

~

4.5V, 10H

Min
~

~

Max

2.4

10H = - 2m A, VCC = 4.5V to 5.5V
VOL

II

IIH

IlL

Low Level Output
Voltage

VCC

~

4.5V, 10L

~

Max

Input Current at
Max Input Voltage

VCC

~

5.5V. VIN

~

7V

High Level Input Current

Low Level Input Current

VCC

~

5.5V, VIN

~

Typ

-18mA

2.7V

VCC ~ 5.5V
VIN ~ O.4V

V

VCC-2
0.35

0.5

V

A, B

0.2

mA

All Others

0.1

A,B

40

All Others

20

A, B

-1

10

Output Drive Current

VCC

~

5.5V, VOUT

~

2.25V

fOZH

Off-State Output
Current, High Bias

VCC

~

5.5V, VOUT

~

2.7V

10ZL

Off-State Output
Current, Low Bias

VCC

~

5.5V, VOUT

~O.4V

ICC

Supply Current

VCC

~

5.5V

I1A

mA

-0.5

All others

3·145

V

3.2

-112

- 30

mA

50

I1A

-50

I1A

mA

Outputs high

15

24

Outputs low

19

31

Outputs
disabled

18

30

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V, TA = 25°C.
DM54AS353
Parameter

From

To

Conditions

Min

Typ

DM74AS353

Typ

Max

Unit

Max

Min

3

10

3

'9

ns

4

14

4

12

ns

3

8.5

3

7.5

ns

2

6.5

2

6

ns

3

8.5

3

7.5

ns

4

12

4

11

ns

tHZ, Output Disable Time
From High Level

2

6.5

2

5.5

ns

'tLZ, Output Disable Time
From Low Level

3

9

3

7.5

ns

tPLH, Low to high Level Output
Select
tPHL, High to low Level Output
tpLH, Low to high Level Output
Data
tpHL. High to low Level Output
y

tZH. Output Enable Time
to High Level
tZL. Output Enable Time
to Low Level

VCC=
4.5 to 5.5V
CL = 50 pF
RL = 500 {l

Output
Control

Noll 1: See Seclion 1 for lesl waveforms and oulpul load.

Logic Diagram
OUTPUT
CONTROL

~-cO------.......,---------,
GI

ICo...!6!.-----------+-f~~

ICI...:5L---------I=t~=t:J

7 OUTPUT

VI

DATA I
IC2...;4::..-----------lHH-f---4..-J

IC3J3!.--------~~~=l~:J
SELECT {

B 2

A~I~4---lDM~._~>_--_r~

2CO ..:.lo"-----------lrl--:l:::±~1

--------++++--r""'

2CI..!I.:..1
DATA 2

9 OUTPUT
V2

2C2 12

::......----------1I::::lt=:::::{=::)

2C3..:.13

-co-----------------'

OUTPUT ...;1:;.5
. CONTROL G2

TLI F16308·2

3-146

~National

D Semiconductor
DM54AS373/DM74AS373 Octal D-Type
Transparent Latches with TRI-STATE® Outputs
General Description

Features

These a-bit registers feature totem-pole TRI-STATE outputs designed specifically for driving highly-capacitive or
relatively low-impedance loads. The high-impedance state
and increased high-logic-level drive provide these registers with the capability of being connected directly to and
driving the bus lines in a bus-organized system without
need for interface or pull-up components. They are particularly attractive for implementing buffer registers, 1/0
ports, bidirectional bus drivers, and working registers.

•
•

The eight latches of the AS373 are transparent D-type
latches meaning that while the enable (G) is high the Q outputs will follow the data (D) inputs. When the enable is taken
low the output will be latched at the level of the data that
was set up.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
the latches. That is, the old data can be retained or new data
can be entered even while the outputs are off.

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
• Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
• Functionally and Pin For Pin Compatible with LS and
ALS TTL Counterparts.
• Improved AC Performance Over LS and ALS TTL
Counterparts.
• TRI-STATE Buffer-Type Outputs Drive Bus Lines
Directly.

.Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Fr~e Air Temperature Range
DM54AS373
DM74AS373
Storage Temperature Range

(Note 1)
7V
7V

-55°C to 125°C
DoC to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
nol be operated at these limits. The parametric, values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram
Dual-In-Line Package

ENABLE
80

80

OUTPUT 10
CONTROL

10

Vee

70

70

60

60

50

50

G

20

30

3D

40

40

GNO
TLlF16309·1

54AS373 (J)

3-147

74AS373 (J,N)

r)r---------------------------------------------------------------------------

~t:!:

Recommended Operating Conditions

DM54AS373
Parameter

:E

-r)

.

C

Supply Voltage, VCC

l=;

High Level Input Voltage, VIH

~
:E

DM74AS373

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V
V

2

2

Unit

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Voltage, VOH

5.5

5.5

V

High Level Output Current, 10H

~12

-15

mA

Low Level Output Current, 10L

32

48

mA

IC

Width of Enable Pulse, High

5.5

4.5

ns

Data Setup Time, TSU

21

21

ns

Data Hold Time, TH

31

31

ns

The (I) arrow indicates the negative edge of the enable is used for neference.

Electrical C~aracteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25°C.
Symbol

Parameter

_Conditions

VIK

InputClamp Voltage

VCC=4.5V, 11= -18mA

VOH

High Level Output
Voltage

VCC = 4.5V 10H = MAX

Typ

Min

VOL

Low Level Output
Voltage

VCC=4.5V,IOL=MAX

II

Max High Input Current

VCC=5.5V, VIH=7V

IIH

High Level Input Current

VCC=5.5V, VIH=2.7V

IlL

Low Level Input Current

VCC=5.5V, VIL=0.4V

10

Output Drive Current

VCC=5.5V, VO=2.25V

10ZH

Off-State Output
Current, High Level
Voltage Applied

10ZL

ICC

Unit
V

3.2

2.4

10H = - 2mA, VCC = 4.5V to 5.5V

Max
-1.2

V

VCC-2
0.35

0.5

V

0.1

mA

·20

IJA

-0.5

mA

-112

mA

VCC=5.5V, VO=2.7V

50

IJA

Off-State Output
Current,
Low Level
Voltage Applied

VCC= 5.5V, VO=0.4V

-50

IJA

Supply Current

VCC = 5.5V
Outputs Open

mA

,

-30

Outputs High

55

90

Outputs Low

55

85

Ou~puts

65

100

3·148

Disabled

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vcc = 5V, TA = 25°C.
DM54AS373
Parameter

From

To

Conditions

Min

Typ

DM74AS373
Max

Min

Typ

Unit

Max

3.5

8

3.5

6

ns

TPHL

3.5

7

3.5

6

ns

TpLH

6.5

14

6.5

11.5

ns

TpLH

Data

Enable

Any

Any

a
a

TPHL
TpZH
TpZL

Output

TpHZ

Control

Any

Vcc = 4.5V to 5.5V
RL = 500 n
CL = 50 pF

a

TPLZ

5

8

5

7.5

ns

2

7.5

2

6.5

ns

4.5

10.5

4.5

9.5

ns

3

7.5

3

6.5

ns

3

8

3

7

ns

Note 1: See Section 1 for test waveforms and output load.

Logic Diagram

Function Table

"..::------1
HI----<>!>---''-'o

+-;

" -'-----1---1
6 3,

,,-"'---+-;
HI--01>--':"'"
SD 13

12 SQ

" ...;,""-----+---1
15 60

7D 11

19

80

L
L
L
H

H
H
L

X

a

1-11---<0[>---''- 20

70'

Enable
G

L ~ Low State, H'~ High State, X
Z ~ High Impedance Slate
00 = PrevIOus Condition of

2D"::'_ _ _

16

Output
Control

80 18

ENABLE G"':':""--1><>-'

TL/F/6309·2

3·149

~

0

Output
Q

H
L

H
L

X
X

aO

Don't Care

Z

~National'

D Semiconductor
DM54AS374/DM74AS374 Octal D-TypeEdge-Triggered Flip-Flops wi~h TRI-STATE® Outputs
General Description

Features

These 8-bit registers feature totem-pole TRI-STATE output
designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance third state
and increased high-logic-level drive provide these registers
with the capability of being connected directly to and driving
the bus lines in a bus-organized system without need for
interface or pull-up components. They are particularly attractive for implementing buffer registers, 1/0 ports, bidirectional bus drivers, and working registers.

•
•

The eight flip-flops of the AS374 are edge-triggered D-type
flip-flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D
inputs.

•

A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.

Absolute Maximum Ratings

The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.

Switching Specifications at· 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
Advanced Oxide-lsolated,lon-lmplanted Schottky TTL
Process.
Functionally and Pin-for-Pin Compatible with LS and
ALS TTL Counterparts.
!

•
•
•

Improved AC Performance Over LS and ALS TTL
Counterparts.
TRI-STATE® Buffer-TYPE) Outputs Drive Bus Lines
Directly.

Supply Voltage
Input Voltage
Operating' Free Air Temperature Range
DM54AS374
DM74AS374
Storage Temperature Range

(Note 1)
7V
7V

-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Nole 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values def.ined in tne

"Eleclrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table.will
define the conditions for actual device operation.

Connection Diagram
Dual·ln·Line Package

,

VCC

80

80

70

70

60

60

50

50

OUTPUT
CONTROL

10

1D

2D

20

30

3D

4D

40

CLOCK

GNO

TLlF/6310·1

54AS374 (J)

74AS374 (J,N)

3-150

Recommended Operating Conditions
DM74AS374

DM54AS374
Parameter

Supply Voltage, VCC

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

High level Input Voltage, VIH

2

Unit

V
V

low level Input Voltage, Vil

0.8

0.8

V

High level Output Current, IOH

-12

-15

mA

low level Output Current, IOl

32

48

mA

125

MHz

Width of Clock Pulse, TW

100

0

Clock frequency, fClOCK

0

High

5.5

'4

low

5

3

ns

Data Setup Time, TSU

31

0

21

0

ns

Data Hold Time, TH

31

0

21

0

ns

The (1) arrow indicates the posItive edge of the Clock is used for reference.

3-.151

~r---------------------------------------------------------------------------

.....
C")

~
r:!:

:E

Q

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vcc .=5V, TA =;25°C ..
Symbol

Parameter

Conditions

Min

VIK

Input Clamp Voltage

VCC = 4.5V II = -18mA

VOH

High Level Output
Voltage

VCC = 4.5V 10H = MAX

Typ

Max

Unit

-1.2

V

~

~

~
:E
Q

2.4

10H = - 2m A, VCC = 4.5V to 5.5V
VOL

Low Level Output
Voltage

VCC = 4.5V 10L = MAX

II

Max High Input Current

IIH

.V

3.2

VCC-2
0.5

V

VCC = 5.5V VIH = 7V

0.1

mA

High Level Input Current

VCC = 5.5V VIH = 2.7V

20

IJ.A

IlL

Low Level Input Current

VCC = 5.5V VIL = O.4V

-0.5

mA

10

Output Drive Current

VCC = 5.5V Va = 2.25V

-112

mA

10ZH

Off-State Output
Current, High Leliel
Voltage Applied

VCC = 5.5V Vo = 2.7V

50

IJ.A

10ZL

Off-State Output
Current, Low Level
Voltage Applied

VCC = 5.5V Vo = O.4V

-50

IJ.A

ICC

Supply Current

VCC = 5.5V
Outputs Open

mA

0.35

-30

Outputs High

77

120

Outputs Low

84

128

Outputs Disabled

84

128

SWitching Characteristics over recommended operating free air temperature range (~ote 1).
All typical values are measured at Vee = 5V, TA = 25°C.
DM74AS374

DM54AS374
Parameter

From

To

Conditions

Min

Typ

Max

Min

Typ

Max

Unit

FMAX

100

TpLH

3

11

3

8

ns

4

11.5

4

9

ns

Clock

.Any Q

TpHL
VCC = 4.5V to 5.5V
RL = 500 f!
CL = 50 pF

125

MHz

2

7

2

6

ns

3

11

3

10

ns

TPHZ

2

7

2

6

ns

TpLZ

2

7

2

6

ns

TPZH
TPZL

Output
Control

AnyQ

Note1: See Section 1 for test waveforms and output load.

3-152

Logic Diagram

Function Table
Output
Control

10

3D

4D

5D

20

6

30

,

40

12

50

15

6Q

16

10

19

80

Output
Q

1
1

H
L

H
L

L
X

X
X

00

L ~ Low State, H ~ High State, X
t = Positive Edge Transition
Z ~ H'gh Impedance State
00 = Previous Condition of

0

,

0

L
L
L
H

3
2 10

2D

Clock

~

Z

Don't Ca,e

a

7

•

13

"...;',,-0----+-l

70

17

BO 18

CLOCK

"';;"--000-'

TL/F/6310·2

,

3·153

/

c-)

~ ~National

~

:E

a

Semiconductor

DM54AS533/DM74AS533 Octal D-Type Transparent
-c Latches
with TRI-STATE® Outputs
~

Il)

UJ

==

Il)

:E
c

General Description

Features

These 8·bit registers feature totem·pole TRI·STATE out·
puts designed specifically for driving highly·capacitive or
relatively low·impedance loads. The high·impedance state
and increased high·logic·level drive provide these
registers with the capability of being connected directly to
and driving the bus lines in a bus·organized system
without need for interface or pull·up components. They are
particularly attractive for implementing buffer registers,
I/O ports, bidirection~ bus drivers, and working registers.
The eight inverting latches of the AS533 are transparent 0type latches meaning that while the enable (G) is high the Q
outputs will follow the complement of the data (D) inputs.
When the enable is taken low the output will be latched at
the complement of the level of the data thl!lt was set up.

•
•

A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
the latches. That is, the old data can be retained or new data
can be entered even while the outputs are off.

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and Vee Range.
• Advanced, OXide-Isolated, lon-Implanted Schottky TTL
Process.
• TRI·STATE Buffer·Type Outputs Drive Bus Lines
Directly.

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS533
DM74AS533
Storage Temperature Range

7V
7V
-55°C to 125°C
ooe to 70°C
-65°C to 150°C

Nole 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram
Dual-In-Line Package

TLlF/6311·1

54AS533 (J)

74AS533 (J,N)

3-154

c

s:
c.n

Recommended Operating Conditions
DM54AS533
Parameter

Supply Voltage, VCC

DM74AS533

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Unit

V

~

c.n
Co)

-s:
Co)

C

High Level Input Voltage, V,H

2

V

2

Low Level Input Voltage, V,L

0.8

0.8

V

High Level Output Voltage, VOH

5.5

5.5

V

High Level Output Current, 10H

-12

-15

mA

Low Level Output Current, 10L

32

48

mA

;

CJ)

Width of Enable Pulse, High or Low

5.5

4.5

ns

Data Setup Time, TSU

21

21

ns

Data Hold Time, TH

31

31

ns

The (I) arrow indicates the positive edge of the Clock

Electrical Characteristics

IS

used for reference.

over recommended operating free air temperature range.

All typical values are measured at Vee = 5V, TA = 25'C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC

=

4.5V 'I

VOH

High Level Output
Voltage

VCC

=

4.5V, 10H

Min

=

Typ

-18mA

=

2.4

MAX

10H = - 2mA, VCC = 4.5V to 5.5V
VOL

Low Level Output
Voltage

VCC

=

4.5V, 10L

=

MAX

II

Max High Input Current

VCC

=

5.5V V,H

=

IIH

High Level Input Current

VCC

=

5.5V V,H

IlL

Low Level Input Current

VCC

=

10

Output Drive Current

VCC

10ZH

Off-State Output
Current, High Level
Voltage Applied

'OZL

ICC

Max

Unit

-1.2

V
V

3.2

VCC-2
0.5

V

7V

0.1

mA

=

2.7V

20

!LA

5.5V V,L

=

O.4V

-0.5

mA

=

5.5V, Vo

=

2.25V

-112

mA

VCC

=

5.5V VVO

50

!LA

Off-State Output
Current, Low Level
Voltage Applied

VCC

=

5.5V Vo

-50

!LA

Supply Current

VCC = S.5V
Outputs Open

mA

=

=

0.35

.
-30

2.7V

O.4V

Outputs High

62

100

Outputs Low

64

100

Outputs Disabled

71

110

3·155

c.n

Co)
Co)

Switching Characteristics over recommended operating free air temperature range (Note 1);
All typical values are measured at Vcc

=5V, TA =25°C.
DM54AS533

Parameter
TpLH

From
Data

To

Conditions

Min

AnyQ

TPHL
TpLH

Enable

AnyQ

TpHL
TpZH
TPZL

Output

TPHZ

Control

VCC = 4.5V to 5.5V
RL = 500!"!
CL = 50pF.

Typ

TpLZ

Max

Min

Typ

Unit

Max

4

10

4

7.5

ns

4

8

4

7

ns

5

11

5

9

ns

4.5

8.5

4.5

8

ns

2

7.5

2

6.5

ns

4.5

9.5

ns

3

7.5

3

6.5

ns

3

8

3

7

ns

10.5

4.5

AnyQ

DM74AS533

Note 1: See Section 1 for test waveforms and output load.

Logic Diagram

Function Table

lO..."!..-----I

30-'----+-1

'0

4D '

" '0

&0 14

15

60

17

16

70

80 18

"

,ij

"

Enable

L
L
L
H

H
H
L
X

G

0
H
L
X
X

L - Low state, H - High State, X - Don't Care
Z - High Impedance State
00 - Previous Condition of 0

"'

50 13

Output
Control

ENABlfG

TL/F/6311·2

3-156

Output

Q
L
H
00
Z

c

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~National

a

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~

Semiconductor

l>

en
CJ'I

-:s:c
c.l
~

DM54AS534/DM74AS534 Octal D-Type Edge-Triggered
Flip-Flops with TRI-STATE® Outputs
General Description

Features

These S·bit registers feature totem·pole TRI·STATE out·
puts designed specifically for driving highly·capacitive or
relatively low·impedance loads. The high·impedance state
and increased high·logic·level drive provide these
registers with the capability of being connected directly to
and driving the bus lines in a bus·organized system
without need for interface or pull·up components. They are
particularly attractive for implementing buffer registers,
1/0 ports, bidirectional bus drivers, and working registers.

•
•

The eight flip-flops of the AS534 are edge-triggered inverting D-type flip-flops. On the positive transition of the clock,
the Q outputs will be set to the complement of the logic
states that were set up at the D inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.

c.l
~

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and Vee Range.
• Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
• TRI-STATE Buffer·Type Outputs Drive Bus Lines
Dir~ctly.

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
. Operating Free Air Temperature Range
DM54AS534
DM74AS534
Storage Temperature Range

7V
7V
~55°e

to 125°C
ooe to 70°C
~65°e to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should

not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram
Dual·ln·Llne Package

TLlF/6312·1

54AS534 (J)

~

en
CJ'I

74AS534 (J,N)

3-157

o:t

~

~
t:!:
:e:
c
~
~
o:t

it)

Recommended Operating Conditions
DM54AS534
Parameter
Supply

VOltag~, VCC

DM74AS534

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

.4.5

5

5.5

2

2

High Level Input Voltage, VIH.

V
V

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Current, IOH

-12·

-15

rnA

48

mA

125,

MHz

it)

:e:
c

Unit

\

Low Level Output Current, IOL

32
100

0

Clock frequency, fCLOCK

0

High

5.5

4

Low

5

3

Data Setup Time, TSU

31

21

ns

Data Hold Time, TH

31

21

ns

Width of Clock Pulse, TW

The (1) arrow indicates the positive edge of the Clock

IS

used for reference.

3-158

ns

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vcc = 5V, TA = 25°C.
Symbol

Typ

Min

Parameter

Conditions

V,K

Input Clamp Voltage

VCC=4.5V, "= -18mA

VOH

High Level Output
Voltage

VCC=4.5V, 10H = M~.x

Unit
V

3.2

2.4

10H= -2mA, VCC=4.5V t05.5V

Max
-1.2

V

VCC -2
0.5

V

VCC=5.5V, V,H=7V

0.1

mA

High Level Input Current

VCC=5.5V, V,H =2.7V

20

p.A

IlL

Low Level Input Current

VCC=5.5V, V'L=0.4V

-0.5

mA

10

Output Drive Current

VCC=5.5V, VO=2.25V

-112

mA

10ZH

Off·State Output
Current, High Level
Voltage Applied

VCC=5.5V, VO=2.7V

50

p.A

10ZL

Off·State Output
Current. Low Level
Voltage Applied

VCC=5.5V, VO=0.4V

-50

p.A

ICC

Supply Current

VCC =5.5V
Outputs Open

mA

VOL

Low Level Output
Voltage

VCC =4.5V, 10L= MAX

II

Max High Input Current

"H

0.35

-30

Outputs High

77

120

Outputs Low

84

128

Outputs Disabled

84

128

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vcc = 5V, TA = 25°C.
DM54AS534
Parameter

From

To

Conditions

Min

Typ

DM74AS534
Max

Min

Typ

Max

125

Unit
MHz

FMAX

100

TpLH

3

11

3

8

ns

4

11.5

4

9

ns

Clock

AnyQ

TpHL
VCC = 4.5V to 5.5V
RL = 500 fl
CL = 50 p;

2

7

2

6

ns

3

11

3

10

ns

TpHZ

2

7

2

6

ns

TPLZ

2

7

2

6

ns

TpZH
TpZL

Output
Control

AnyQ

Note 1: See Section 1 for test waveforms and output load.

3·159

•

Logic Diagram

Function Table
Output
Control

ID

3

L
L

Hf---<>I::>-.....:.... '0

L

H
5

2D •

30-'-----+-..,

30

9

50 13

"

50

14

15

60

70 17

"

70

80 18

19

80

60

0

i

H
L
X
X

1
L
X

L = Low State, H = High State, X
1 = Positive Edge Transition
Z = High Impedance State
00 = Previous Condition of Q

I!O

4D 8

Clock

'0

---C>o-J

CLOCK ..:':..'

TLlF/6312·2

3·160

= Don't Care

Output

Q
'L
H

00
Z

.-----------------------------------------------------------------~c

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Semiconductor

en
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DM54AS573/DiVl74AS573 Octal D-Type
Transparent Latches with TRI-STATE® Outputs

C

~
l>

en
U1
.....,

General Description

Features

These S-bit registers feature totem'pole TRI-STATE outputs designed specifically for driving highly-capacitive or
relatively low-impedance loads. The high-impedance state
and increased high-logic-level drive provide these
registers with the capability of being connected directly to
and driving the bus lines in a bus-organized system
without need for interface or pull-up components. They are
particularly attractive for implementing buffer registers,
110 ports, bidirectional bus drivers, and working registers.

•

Switching Specifications at 50 pF.

•

Switching Specifications Guaranteed Over Full
Temperature and Vee Range.

•

Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.

The eight latches of the AS573 are transparent D-type
latches meaning that while the enable (G) is high the outputs will follow the data (D) inputs. When the enable is taken
low the output will be latched at the level of the data that
was set up.

a

A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
'
The output control does not affect the internal operation of
the latches. That is, the old data can be retained or nel(ll data
can be entered even while the outputs are off.

Co)

•

Functionally Equivalent with S373.

•

Improved Ae Performance Over S373 at
Approximately Half the Power.

•

TRI-STATE Buffer-Type Outputs Drive Bus Lines
Directly.

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS573
DM74AS573
Storage Temperature Range

(Note 1)
7V
7V

-55°C to 125°C
ooe to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

not be operated at these limits. The parametric, values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram
Dual·ln-Line Package

TLlF/6313·1

54AS573 (J)

74AS573 (J,N)

3-161

~r----------------------------------------------------------------------------

t; Recommended Operating Conditions

~
~
:e

DM74AS573

DM54AS573
Parameter

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Unit

-....

Supply Voltage, VCC

Lt)

High Level Input Voltage, VIH

~

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Voltage, VOH

5.5

5.5

V

High Level Output Current, 10H

-12

-15

mA

Low Level Output Current, 10L

32

48

mA

c

V

~

2

2

V

Lt)

:e

c

Width of Enable Pulse, High or Low

5.5

4.5

ns

Data Setup Time, TSU

21

21

ns

Data Hold Time, TH

31

31

ns

The (I) arrow indicates the positive edge of the Clock is used for reference.

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25°C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.5V, II = -18mA

VOH

High Level Output
Voltage

VCC = 4.5V
VIL = VIL MAX
10H = MAX
10H

=

Min

204

-2mA

VOL

Low Level Output
Voltage

VCC = 4.5V
VIH = 2V
10L = MAX

II

Max High Input Current

liH

Typ

Max

Unit

-1.2

V
V

3.3

VCC -2
0.5

V

VCC=5.5V, VIH=7V

0.1

mA

High Level Input Current

VCC = 5.5V, VIH = 2.7V

20

/lA

IlL

Low Level Input Current

VCC = 5.5V, VIL = 0.4V

-0.5

mA

10

Output Drive Current

VCC = 5.5V, Vo = 2.25V

-112

mA

10ZH

Off-State Output
Current, High Level
Voltage Applied

VCC=5.5V, VIH=2V
Vo = 2.7V

50

I'A

10ZL

Off-State Output
Current, Low Level
Voltage Applied

VCC=5.5V, VIH'=2V
Vo = OAV

-50

I'A

ICC

Supply Current

VCC = 5.5V
Outputs Open

mA

0.35

-30

Outputs High

56

93

Outputs Low

55

90

,
Output~

3-162

Disabled

65

106

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vcc =SV, TA =2SoC.
DM54AS573
Parameter

From

To

Conditions

Min

Typ

DM74AS573
Max

Min

Typ

Unit

Max

3

9

3

6

ns

TpHL

3

7

3

6

ns

TpLH

6

14

6

11.S

ns

TpLH

Any 0

Data

Enable

VCC = 4.SV to S.SV
RL = 500 {l
CL = 50 pF

Any 0

TpHL
TPZH
TpZL

Output

TpHZ

Control

Any 0

TPLZ

4

9

4

7.S

ns

2

8

2

6.S

ns

4

11

4

9.S

ns

2

8

2

6.5

ns

2

8

2

7

ns

Note 1: See Section 1 for test waveforms and output load.

Function Table

Logic Diagram

Output
Control

Enable
G

L
L
L
H

H
H
L

X

OUTPUT CONTROL

0

H
L

X
X

Output
Q

H
L
00
Z

,,-'-----1
19 10

L - Low State. H - High State, X - Don't Care
Z - High Impedance State
00 - Previous Condition of 0

"-'----t-l
18

20

,,""---+--I
17

30

4O-"'---+-l
16

-'0

5O-'---~__i

" '0
"

'0

7D-'---~__i

1J

10

8O-'---~__i

II
EHABLE G -'-'-----'"-0<:>-'

"

'0

TLlF/6313·2

3-163

~

t;

~

~

~ National

a

'
Semiconductor

Octal D-Type
- DM54AS574/DM74AS574
Edge-Triggered Flip-Flops with TRI-STATE® Outputs
c

~

~

LI)

~

c·

General Description

Features

These B-bit registers feature totem'pole TRI-STATE out·
puts designed specifically for driving highly·capacitive or
rillatively low-impedance loads. The high-imp,.edance state
and increased high-logic-level drive provide these
registers with the capability of being connected directly to
and driving the bus lines in a bus-organized system
without need for interface or pull-up components. They are
particularly attractive for implementing buffer registers,
I/O ports, bidirectional bus drivers, and working registers.

•
•

The eight flip-flops of the ASS74 are edge-triggered D-type
flip-flops. On the positive transition of the clock, the outputs will be set to the logic states that were set up at the D
inputs.

a

A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.

Connecti~n

Diagram

•
•
•
•

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DMS4ASS74
DM74ASS74
Storage Temperature Range

Clock

D

1
1

H
l
X
X

l
X

7V
7V
:""ssoe to 12Soe
ooe to 70°C
-6Soe to 1S0oe

Nole 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ralings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

74AS574 (J,N)

Function Table

l
l
l
H

(Note 1)

Dual·ln·line Package

54AS574 (J)

Output
Control

Switching Specifications at SO pF.
Switching Specifications Guaranteed Over Full
Temperature and Vee Range.
Advanced Oxide-Isolated, lon-Implanted Schottky TTL .
Process.
Functionally Equivalent with S374.
Improved Ae Performance Over S374 at
Approximately Half the Power.
TRI-STATE Buffer-Type Outputs Drive Bus lines
Directly.

Output
Q

H
l
00
Z

L = Low State, H = HIgh State. X = Don't Care
T = Positive Edge Transition
Z = High Impedance State
00 = Previous Condition of.O

3·164

TL/F/6314·1

Recommended Operating Conditions
DM74AS574

DM54AS574
Parameter

Supply Voltage, VCC
High Level Input Voltage, VIH

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

2

Unit

V
V

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Voltage, VOH

5.5

5.5

V

High Level Output Current, IOH

-12

-15

mA

Low Level Output Current, IOL

32

48

mA

125

MHz

100

0

Clock frequency, fCLOCK
Width of Clock Pulse, TW

0

ns

5

4

3

2

Data Setup Time, TSU

31

21

ns

Data Hold Time, TH

31

21

ns

High
Low

The (1) arrow mdicates the positive edge of the Clock

IS

used for reference.

Logic Diagram
10

2

'9 10

2D

"

4D

50

50

7D

'
18

2Q

11

30

16

40

15

50

14

60

13

70

4

5

6

7

8

" ....:9'--_ _ _+_~
f------_.:.;"'-8Q
CLOCK

...:,"'----£><>-'

TL/F/6314·2

3·165

~
\l)

~

;:!:
:E
c
~
\l)

-

Electrical Characteristics over recommended operating free a!r temperature range.
All typical values are measured at Vee= SV, TA= 2SoC.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

Vec = 4.SV, II = -18mA

VOH

High Level Output
Voltage

VCC = 4.SV
VIL = VIL MAX
10H = MAX

~
c

VOL

Low Level Output
I
Voltage

Vce = 4.SV
VIH = 2V
10L = MAX

II

Max High Input Current

IIH

Typ

2.4

10H= -2mA, Vec=4.SVto S.SV

\l)

:E

Min

Max

Unit

-1.2

V

V

3.3

Vce -2
'0.3S

O.S

.V

Vec=S.SV, VIH =7V

0.1

mA

High Level Input Current

VCC = S.SV, VIH = 2.7V

20

/LA

IlL

Low Level Input Current

VCC=S.SV, Vll=0.4V

-O.S

mA

10

Output Drive Current

VCC=S.SV, VO=2.2SV

-112

rnA

10ZH

Off-State Output
Current, High Level
Voltage Applied

VCC=S.SV, VIH=2V
Vo = 2.7V,

SO

/LA

lOll

Off-State Output
Current, Low Level
Voltage Applied

VCC=5.5V, VIH=2V
Vo = OAV

-SO

/LA

ICC

Supply Current

VCC = .S.SV
Outputs Open

rnA

~witching

-30

Outputs High

73

116

Outputs Low

85

134

Outputs Disabled

84

134

Characteristics over recommended operating free air temperature range (Note 1).

All typical values are measured at Vee = SV, TA = 2SOC.
DM54AS574
Parameter

From

To

Conditions

Min

Clock

Any Q

TpHl
TpZH
TpZL
TpHZ
TplZ

DM74AS574
Max

100

FMAX
TpLH

Typ

Output
Control

Output
Control

Any Q

VCC = 4,SV to S.SV
RL = SOO n
CL = SO pF

,
AnyQ

Note 1: See Section 1 for test waveforms and output load.

3-166

Min

Typ

Max

12S

Unit
MHz

3

11

3

8

ns

4

11

4

9

ns

2

7

2

6

ns

3

11

3

10

ns

2

7

2

6

ns

2

7

2

6

ns

c

s:
C1I

~National

~

D Semiconductor

C1I

......

-s:

DM54AS575/DM74AS575 Octal D-Type
Edge-Triggered Flip-Flops with Synchronous Clear

C1I

General Description

Features

en
C1I

These 8-bit registers feature totem·pole TRI-STATE outputs designed specifically for driving highly-capacitive or
relatively low-impedance loads. The high-impedance state
and increased high-logic-level drive provide these
registers with the capability of being connected directly to
and driving the bus lines in a bus-organized system
without need for interface or pull-up components. They are
particularly attractive for implementing buffer registers,
110 ports, bidirectional bus drivers, and working registers.

•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.

•

Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
TRI-STATE Buffer-Type Outputs Drive Bus Lines
Directly.

•
•

The eight flip-flops of the AS575 are edge-triggered D-type
flip-flops. On the positive transition of the clock, the Q outputs Will be set to the logic states that were set up at the 0
mputs.

NO

10

......

C1I

Synchronous Clear

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS575
DM74AS575
Storage Temperature Range

(Note 1)
7V
7V

-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond

The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.

Vee

~

Absolute Maximum Ratings

A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.

Connection Diagram

C

which the safety of the device can not be guaranteed. The device should

not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table wil'
define the conditions tor actual device operation.

. Dual-In-Line Package
10

40

30

60

50

80

10

CLOCK

Ne

TL/F/6315-1

54AS575 (J)

74AS575 (J,N)

Function Table
Output
Control

Output

L
L
L
L
H
L

=

Low State, H

CLR

Clock

L
H
H
H

1
1
1
L
X

X
=

HIgh State, X

=

Don't Care

I = PosItIve Edge TranSition

Z

~

High Impedance State

3-167

D

Q

X

L
H
L
QO
Z

H
L

X
X

a

00 = PrevIOus Condition of
NC = No Internal Connection

it)

. t;

en

«

~
:i!:

Recommended Operating Conditions
DM54AS575
Parameter

DM74AS575

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Unit

-

Supply Voltage, VCC

~

Low Level Input Voltage, VIL

0.8

0.8

V

:i!:

High Level Output Voltage, VOH

5.5

5.5

V

High Level Output Current, IOH

-12

-15

mA

Low Level Output Current, IOL

~2

48

mA

125

MHz

c
i t)
r-it)

2

2

High Level Input Voltage, VIH

V
V

it)

c

0

Clock frequency, fCLOCK
Width of Clock Pulse, TW

100

0

High

5

4

Low

3

2

DATA

31

21

6.51

5.51

DATA

31

21

CLR

01

01

Data Setup Time, TSU
CLR

High or Low

Data Hold Time, TH

The (1) arrow indicates the positive edge of the Clock is used for reference.

Logic Diagram

22

10

ZI

20

20

30

19

40

18

5Q

16

70

15

If)

TLIF16315-2

3-168

ns

ns

ns

c

s:
en

Electrical Characteristics over recommended operating free air temperature range.
It,II typical values are measured at Vce = 5V, TA = 25°C.
Min

Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.5V, II = -18mA

VOH

High Level Output
Voltage

Vce =

= -2mA

VOL

Low Level Output
Voltage

VCC = 4.5V
VIH = 2V
10L = MAX

II

Max High Input Current

IIH

Max

Unit

-1.2

V

.3.3

2.4

4.5V
VIL = VIL MAX
10H = MAX
10H

Typ

V

VCC=5.5V, VIH =7V

0.1

rnA

High Level Input Current

VCC = 5.5V, VIH = 2.7V

20

I'A

IlL

Low Level Input Current

VCC=5.5\f., VIL=0.4V

-0.5

rnA

10

Output Drive Current

VCC = 5.5V, Va = 2.25V

-112

rnA,

10ZH

Off-State Output
Current, High Level
Voltage Applied

VCC=5.5V, VIH=2V
Vo = 2.7V

50

I'A

10ZL

Off-State Output
Current, Low Level
Voltage Applied

VCC=5.5V, VIH=2V
Vo = O.4V

-50

I'A

ICC

Supply Current

VCC = 5.5V
Outputs Open

mA

0.35

-30

Outputs High

78

126

Outputs Low

88

142

Outputs Disabled

88

142

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V, TA = 25°C.
DM54AS575
To

Conditions

Min

Clock

Any 0

TpHL
,

TpZH
TPZL
TpHZ
TpLZ

DM74AS575
Max

100

FMAX
TpLH

Typ

Output
Control

AnyO

Output
Control

Any 0

VCC = 4.5V to 5.5V
RL = 500!l
CL = 50 pF

Note 1: See Section 1 for test waveforms and output load.

3·169

-s:
en
C

en
en

V

From

~

~
l>

VCC -2
0.5

Parameter

~

Min

Typ

Max

125

Unit
MHz

3

11

3

8

ns

4

11

4

9

ns

2

7

2

6

ns

3

11

3

10

ns

2

7

2

6

ns

2

7

2

6

ns

.....

en

~r-------------------------------------------------------~--------------,

~ ~ National
r:!:
:i:E
c

a

.
Semiconductor

CD DM54AS576/DM74AS576 Octal D-Type
t; Edge-Triggered Flip-Flops W.ith Inverted Outputs

~:i:E
c

General Description

Features

These a-bit registers feature totem-pole TRI-STATE outputs designed specifically for driving highly-capacitive or
relatively low-impedance loads. The high-Impedance state
and Increased high-logic-level drive provide these
. registers with the capability of being connected directly to
and driving the bus lines in a bus-organized system
without need for interface or pull-up components. They are
particularly attractive for implementing buffer registers,
110 ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the AS576 are edge-triggered inverting D-type flip-flops. On the positive transition of the clock,
the Q outputs will be set to the complement of the logic
states that were set up at the 0 inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. 10 the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
the flip~flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.

•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and Vee Range.
• Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
• TRI·STATE Buffer·Type Outputs Drive Bus Lines
Directly.

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS576
DM74AS576
Storage Temperature Range

(Note 1)
7V
7V

-55°C to 125°C
ooe to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Flatlngs" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric. values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the-conditions for actual device operation.

Connection Diagram

Dual-In-Llne Package

TLIF/6316-1

54AS576 (J)

74AS576 (J,N)

3-170

c

s::

Recommended Operating Conditions
DM54AS576
Parameter

Min

4.5

Supply Voltage. VCC

Nom

5

DM74AS576
Max

5.5

4.5

5

Max

5.5

Unit

~

CJ)
(J1

V
V

0.8

0.8

Low Level Input Voltage, VIL

Nom

2

2

High Level Input Voltage, VIH

Min

V

"'en"
C
s::

:is!

:J>

CJ)

High Level Output Current. IOH

-12

-15

mA

Low Level Output Current. IOL

32

48

mA

125

MHz

0

Clock frequency. fCLOCK

100

0

High

5

4

Low

3

2

Data Setup Time. TSU

.31

21

ns

Data Hold Time. TH

31

21

ns

Width of Clock Pulse. TW

The (I) arrow mdlcates the pOSitive edge of the Clock IS used for reference.

ns

(J1

"'"

en

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured'at Vcc =5V, TA=25°C.
Symbol!

Parameter

CondHions

VIK

Input Clamp Voltage

VCC=4.5V, 11= -18mA

Min

VOH

High Level Output
Voltage

VCC = 4.5V, VIL = VIL MAX
10H = MAX
10H= -2mA, VCC=4.5Vto 5.5V

2.4

Typ

Max

Unit

-1.2

V
V

3.3

VCC -2
0.5

V

Vec=5.5V, VIH=7V

0.1

rnA

High Level Input Current

VCC=5.5V, VIH=2.7V

20

p.A

IlL

Low Level Input Current

Vce = 5.5V, VIL = 0.4V

-0.5

rnA

10

Output Drive Current

VCC=5.5V, VO=2.25V

-112

rnA

10ZH

Off-State Output
Current, High Level
Voltage Applied

VCC=5.5V, VIH=2V
Vo = 2.7V

50

p.A

IOZL

Off-State Output
Current, Low Level
Voltage Applied

Vce = 5.5V, VIH = 2V
Vo = O.4V

-50

p.A

ICC

Supply Current

VCC = 5.5V
Outputs Open

rnA

VOL

Low Level Output
Voltage

VCC=4.5V, VIH=2V
10L = MAX

II

Max High Input Current

IIH

0.35

-30

Outputs High

77

125

Outputs Low

84

135

Outputs Disabled

84

135

3-172

c

Switching Characteristics

:s::
c.n

over recommended operating free air temperature range (Note 1).'

All typical values are measured at Vee = 5V, TA = 25°C.
DM54AS576
Parameter

From

To-

Conditions

Min

FMAX

100

TpLH

3

Clock

AnyO

TpHL
TpZH
Output
Control

TpZL

AnyO

VCC = 4.5V to 5.5V
RL = 500 n
CL = 50 pF

TpHZ
TpLZ

Typ

~

DM74AS576
Max

Min

Typ

Unit

Max

125

MHz

11

3

8

ns

4

11

4

9

ns

2

7

2

6

ns

3

11

3

10

ns

2

7

2

6

ns

2

7

2

6

ns

Function Table
Output
Control

L
L
L
H

ID~------l

J

30

•

4.

5

50

6

6D

7D

0

1
1

H
L
X
X

L
X

~ Low State. H ~ High State. X
1 = PosItive Edge Transition
Z ~ High Impedance State
00 = Previous Condition otO

L

2D

Clock

11

30

15

50

14

60

12

80'

7

8

8D ....:...----.;--l
ClOCK-'-"'-----..................

TLlF/6316·2

3-173

~

Don't Care

-:s::c
0')

;en
c.n

.......

0')

Note 1: See Section 1 for test waveforms and output load.

Logic Diagram

c.n

.......

Output

Q
L
H
00
Z

......

In ~ National·

~

:E

a

.
Semiconductor

~ DM54AS577 IDM7 4AS577 Octal D-Type

In Edge-Triggered Flip-Flops With .Inverted Outputs

~ and Synchronous Preset
:E
c General Description

Features

These 8·bit registers feature totem·pole TRI·STATE out·
puts designed specifically for driving highly·capacitive or
relatively low·impedance loads. The high·impedance state
and increased high·logic·level drive provide t;,ese
registers with the capability of being connected directly to
and driving the bus lines in a bus·organized system
without [leed for interface or pull·up components. They are
particularly attractive for implementing buffer registers,
110 ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the AS577 are edge-triggered inverting D-type flip-flops. On the positive transition of the clock,
the Q outputs will be set to the complement of the logic
states that were set up at the D inputs.

When the eLR is held on during a positive transition of the
clock the Qoutputs of the flip·flops with go high.

Ne

10

•

Synchronous Preset

Absolute Maximum Ratings

The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.

• vee

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and Vee Range.
I! Advanced Oxide-Isolated, lon-Implanted Schottky TTL .
Process.
• TRI·STATE Buffer·Type Outputs Drive Bus Lines
Directly.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS577
DM74AS577
Storage Temperature Range

A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.

Connection Diagram

•
•

(Note 1)
7V
7V

-55°e to 125°e
ooe to 70°C
-65°e to 1500 e

Nole 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" tabie are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual·ln·Line Package
20

Ne

30

TLlF16317·1

54AS576 (J)

74AS576 (J,N)

3·174

c

s:

Recommended Operating Conditions

(J'1

DM74AS577

DM54AS577
Parameter

Supply Voltage, VCC

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Unit

V

~

en
(J'1
......
......

-s:
C

High Level Input Voltage, VIH

V

2

2

Low Level Input Voitage, VIL

0.8

0.8

V

High Level Output Voltage, VOH

5.5

5.5

V

High Level Output Current, IOH

-12

-15

mA

Low Level Output Current, IOl

32

48

mA

125

MHz

0

Clock frequency, fClOCK
Width of Clock Pulse, TW

Data Setup Time, TSU

Data Hold Time, TH

100

0

High

5

4

ns

Low

3

2

ns

Data

31

21

ns

ClR

6.51

5.51

ns

Data

31

21

ns

ClR

01

01

ns

The (i) arrow indicates the positive edge of the Clock is used for reference.

-3-175

~

~

(J'1

......

......

~r-----------~-------------------------------------------------------------~

- -In

~

~
:!1

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vce = 5V, TA = 25°C.
Pa,rameter

Conditions

c

VIK

Input Clamp Voltage

VCC = 4.5V, II = -18mA

~
~
II)

VOH

High, Level Output
Voltage

VCC = 4.5V, VIL = VIL MAX
10H = MAX

-

Symbol

en

~:!1
c

Min

10H = - 2mA, VCC = 4.5V to 5.5V

2.4

Typ

Max

Unit

-1.2

V

3.3

V

VCC -2
0.5

V

VCC=5.5V, VIH=7V

0.1

mA

High Level Input Current

VCC=5.5V, VIH=2.7V

20

/.LA

IlL

Low Level Input Current

VCC=5.5V, VIL=0.4V

-0.5

mA

10

Output Drive Current

VCC = 5.5V, Vo = 2.25V

-112

mA

10ZH

Off-St~te Output
Current, High Level
Voltage Applied

VCC=5.5V, VIH=2V
Vo = 2.7V

50

/.LA

10Zl

Off-State Output
. Current, Low Level
Voltage Applied

VCC=5.5V, VIH=2V
Vo = 0.4V

-50

/.LA

mA

VOL

Low Level Output
Voltage

VCC=4.5V, VIH=2V
10L = MAX

II

Max High Input Current

IIH

ICC

Supply Current

VCC = 5.5V
Outputs Open

0.35

-30

Outputs High

78

126

Outputs Low

76

123

88

142

Outputs Disabled

3-176

,

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vcc = 5V, TA = 25'C.
DM54AS577
Parameter

From

To

Conditions

Min

FMAX

100

TPLH

3

Clock

AnyO

TPZL

Output
Control

AnyO

VCC = 4.5V to 5.5V
RL = 500 Q
CL = 50 pF

DM74AS577
Max

Min

Typ

Max

125

Unit
MHz

11

3

B

ns

11

4

9

ns

2

7

2·

6

ns

3

. 11

3

10

ns

4

TpHL
TpZH

Typ

!

TPHZ

2

7

2

6

ns

TpLZ

2

7

2

6

ns

Note 1: See Section 1 for test waveforms and output load.

Logic Diagram

Function Table

PIIESET

2210

L

~

Output
Control

CLR

Clock

0

Output

L
L
L
L
H

L
H
H
H
X

1
1

X
H
L
X
X

H
L
H
00
Z

Low State. H

~

High State, X

. = Positive Edge Transition

r-r---~;>---~21_20

£. ~

HIgh Impedance State _
00 = PrevIous Condition of Q

.

20 30

19

40

18

50

HI-_01>----...;.I7;... 60

ClaCK

16

10

15

8Q

...:.:....----0<>-'
TLlF/6317-2

3·177

1
L
X
~

Don't Care

Q

~

~
t:!
~
c

~
II)

~
~

c

~National

a

Semiconductor

DM54AS580/DM74AS580 Octal D~Type
Transparent Latches with TRI-STATE® Outputs,
General Description

Features

These 8-bit registers feature totem-pole TRI-STATE outputs designed specifically for driving highly-capacitive or
relatively low-impedance loads. The high-impedance state
and Increased high-logic-level drive provide these
registers with the capability of being connected directly to
and driving the bus lines In a bus-organized system
without need for interface or pull-up components. They are
particularly attractive for implementing buffer registers,
1/0 ports, bidirectional bus drivers, and working registers.

•
•

The eight inverting latches of the AS580 are transparent Dtype latches meaning that while the enable (G) is high the a
outputs will follOW the complement of the data (D) inputs.
When the enable is taken low the output will be latched at
the complement of the level of the data that was set up.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
the latches. That is, the old data can be retained or new data
can be entered even while the outputs are off.

Switching Specifications at 50pF.
Switching Specifications Guaranteed Over Full
Temperature and Vee Range.
Advanced, Oxide-Isolated, lon-Implanted Schottky TTL
Process.
TRI-STATE Buffer-Type Outputs Drive Bus Lines
Directly.

•
•

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS580
DM74A~580

Storage Temperature Range

(Note 1)
7V
7V.

-55°C to 125°C
ooe to 70°C
-65°C to 150°C

Nola 1: The "Absolute Maximum Ratings" are those values btiyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametriC values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram
Dual-In-Line Package

TLlF/6318-1

54AS580 (J)

74AS580 (J,N)

3-178

c
~ecommended

s:
en

Operating Conditions

:;

DM74AS580

DM54AS580
Parameter

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Supply Voltage, VCC

Unit

V.

en

en
CO
o

-s:
C

High Level Input Voltage, VIH

2

2

V

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Current, 10H

-12

-15

mA

Low Level Output Current, 10L

32

48

mA

Width of Enable Pulse, High or Low

3

2

ns

Data Setup Time, TSU

2

2

ns

Data Hold Time, TH

3

3

ns

Electrical Characteristics over recommended operating free air temperature range.
1\11 typical values are measured at Vee
Symbol

=5V, TA =25°C.

Parameter

Conditions

Min

VIK

Input Clamp Voltage

VCC=4.5V, 11= -18mA

VOH

High Level Output
Voltage

VCC = 4.5V
VIL = VIL MAX
10H = MAX

2.4

10H = - 2mA, VCC = 4.5V to 5.5V

Typ

Max

Unit

-1.2

V
V

3.3

VCC -2
0.35

0.5

V

VOL

Low Level Output
Voltage

VCC = 4.5V
VIH = 2V
10L = MAX

II

Max High fnput Current

VCC=5.5V, VIH =7V

0.1

mA

IIH

High Level Input Current

VCC = 5.5V, VIH = 2.7V

20

IlA

IlL

Low Level Input Current

VCC = 5.5V, VIL = O.4V

-0.5

mA

10

Output Drive Current

VCC=5.5V, VO=2.25V

10ZH

Off-State Output
Current, High Level
Voltage Applied

VCC=5.5V, VIH=2V
Vo = 2.7V

50

Il A

10ZL

Off-State Output
Current, Low Level
Voltage Applied

VCC=5.5V, VIH=2V
Vo = 0.4V

-50

Il A

ICC

Supply Current

VCC = 5.5V
Outputs Open

mA

-30

-112

Outputs High

62

100

Outputs Low

65

106

Outputs Disabled

71

115

3·179

mA

~

l;;
en
CO
o

Switching Characteristics

over recommended operating free air temperature range (Note 1).
All typical values are measured at Vcc ",,5V, TA",,25°C.

DM54AS580
Parameter

From

To

Conditions

3

10

3

TPHL

3

7.5

3

7

ns

TpLH

S

12

S

9

ns

4

8.S

4

8

ns

2

7.5

2

6.5

ns

Enable

AnyO

Any 0

TpHL
TpZH
TpZL

Output

TpHZ

Control

VCC = 4.5V to S.SV
RL = 500n
CL = SO pF

AnyO

TpLZ

Max

Unit·

Min

Data

Typ

Typ

Max

TpLH

Min

DM74AS580

7.5

ns

4

10.5

4

9.5

ns

2

7.5

2

6.5

ns

2

8

2

7

ns

Nole 1: See Section 1 for test waveforms and oulpulload,

Logic Diagram

ID

Function Table

2

19

2D

30

'0

50

60

10

Enable

L
L
L
H

H
H
L

G

X

L = Low State, H = High Stale, X
= High Impedance State
00 = Previous Condition of 0

:z

3
18

20

17

30

.6

'0

15

SQ

4

5

6

1

10 "':"~---+---f

8D

Output
Control

-'-----1--1

1--_ _01>_ _..;;12:.... '0
ENABLE G ...'-':...'--f:.>o--'

TLlF/6318·2

3-180

'0
H
L

X

X
= Don't Care

Output
Q
L
H
00
Z

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J?A National

~

~ Semiconductor

-s:~

DM54AS620/DM74AS620, DM54AS621/DM74AS621,
DM54AS622/DM74AS622, DM54AS623/DM74AS623
Octal Bus Transceivers
General Description

C

~

»
~
N

Features

These octal bus transceivers are designed for asynchro·
nous two·way communication between data buses. The
control function implementation allows for maximum
flexibility in timing.
These devices allow data transmission from the A bus to
the B bus or from the B bus to the A bus, depending upon
the logic levels at the enable inputs (GBA and GAB).
The enable inputs can be used to disable the device so
that the buses are effectively isolated.
The dual·enable configuration gives the octal bus trans·
ceivers the capability of storing data by simultaneous en·
abling of GBA and GAB. Each output reinforces its input in
this transceiver configuration. Thus, when both control in·
puts are enabled and all other data sources to the two sets
of bus line,S are at high impedance, both sets of bus lines
(16 in all) will remain at their last states. The8·bit codes ap·
pearing on the two sets of buses will be identical for the
AS621 and AS623, or complementary for the AS620 and
AS622.

P

• Local bus·latch capability
• Choice of true or inverting logic
• Choice of TRI·STATE® or open·collector outputs
Device
Output
Logic
AS620
TRI·STATE
Inverting
AS621
Open·Coliector
True
AS622
Open·Coliector
Inverting
AS623
TRI·STATE
True

c

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~

en

-s:.....
N

C

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage (1/0 ports for AS620, AS623)
Input Voltage(all other inputs)
- 65·C to
Storage Temperature Range

7V

5.5V
7V

+ 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Logic Diagrams

Dual·ln·Line Package

AS621

AS620

GAB

20

Vee

GBA----

Units
Max

7.5
21

1

-s:
0

C

24

5

en
en

I\)

7.5

ns
ns

~
l>

ns

en
en

ns

p

C

5

24

5

21

ns

1

10

1

9

ns

5

26

5

22

ns

1

.11

1

10

ns

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en

-....s:
I\)

C

AS622 Switching Characteristics
DM74AS622

DM54AS622
Parameter

Input

Conditions

Output

Min
·tPLH

A

B

tpHL
. tpLH

Vee = 4.5V to 5.5V,
C L =50pF,
RL =6801l,
TA = Min to Max

tpLH

5

28.5

5

24.5

ns

1

8.5

1

8

ns

5

25

ns

GBA

A

5

GAB

B

1

5

30

en
en

....

1

8

ns

5

22

ns

1

11.5

1

10

ns

5

26

9

23

ns

11.5

1

10.5

ns

8.5

~
l>

I\)

26

1

tpHL

Max

Min

A

tpHL

Typ
(Note 1)

Max

B

tpHL
t pLH

Typ
(Note 1)

Units

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I\)

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Nole 1: All typlcals are at Vee~5.0V. TA ~25°e.
Note 2: For 1/0 ports, the parameters IIH anJ IlL include the off-state output current.

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3 185
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m~National

t! ~ Semiconductor
~ DM54AS638/DM74AS638,DM54AS639/DM74AS639
c;; Octal Bus Transceivers

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General Description
These octal bus transceivers are designed for asynchronous two-way communications between opencollector and TRI·STATE'" buses. The devices transmit
data from the A bus (open-collector) to the B bus (TRI·
STATE) or from the B bus to the A bus, depending upon the'
level at the direction control (DIR) input. The enable input
(<3) can be used to disable the device so the buses are
Isolated.
Device
A Output
B Output
Logic
DM54/74ALS638
DM54/74ALS639

Open-Collector TRI·STATE
Open-Collector TRI,STATE

Inverting
True

Features

• Choice of true or inverting logic
• A bus outputs are open·collector; B bus outputs are
TRI·STATE

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
A Bus I/O Ports
B Bus I/O Ports
Other Inputs
Storage Temperature Range

7V
7V
5.5V
7V
-65·Cto + 150·C

• Bidirectional bus transceivers in high·density 20-pin
packages

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safely of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" lable are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions"table will
define the conditions for actual device operation.

Connection Diagram

Function Table
Control
Inputs

Dual·ln·Llne Package
OIR

20

Vee

A1

19

iI

A2

18

81

A3

17

82

A4

16

83

A5

84

A6

85

A7

86

A8

87

OperatlDn

G

OIR

OM54174ALS638

OM54174ALS639

L

L
H

B data to A bus
A data to B bus
Isolation

B·data to A bus
A data to B bus
Isolation

L
H

X

Logic Diagrams
DM54/74AS638
ii

DIR
81

A1

TO SEVEN OTHER
TRANSCEIVERS

GNO

TLlF/6723-2

DM54174AS639

TOP VIEW

ii

TlfF/6723-1

OIR
81

A1

TO SEVEN OTHER
TRANSCEIVERS

3·186

TlIF16723·3

Recommended o.perating Conditions
Symbol

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

VOH

High Level Output Voltage

DM74AS638
DM74AS639

DM54AS638
DM54AS639

Parameter

Units

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

2

V

2

V

0.8

0.8

V

A Ports

5.5

5.5

V

-12

-15

mA

48

64

mA

70

·c

10H

High Level Output Current

B Ports

10L

Low Level Output Current

Aor B Ports

TA

Operating Free·Air Temperature

-55

125

0

Electrical Characteristics over recommended operating free-air temperature range unless otherwise noted
Symbol

Parameter

Conditions

DM54AS638
DM54AS639

DM74AS638
DM74AS639

1'yp
(Note 1)

Typ
(Note 1)

Min
VIK

Vee = 4.5V, II = -18 mA

10H

A Ports

Vee=4.5V, Vo H =5.5V

VOH

B Ports

Vee = 4.5V, 10H= -3 mA

2.4

Max

Max

-1.2

-1.2

0.1

0.1

3.2

2.4

2

Vee=4.5V,loH=Max

Min

Units

V
mA

3.2

V

2

Vee = 4.5V to 5.5V, IOH = - 2 mA Vee- 2

Vee- 2

VOL

A or B Ports

Vee = 4.5V, 10L=Max

55

V

II

Control Inputs

Vee = 5.5V, V I =7V

0.1

0.1

mA

A or B Ports

Vee = 5.5V, V I =5.5V

0.1

0.1

IIH

Control Inputs

Vec= 5.5V, VI=2.7V

20

20

70

70

Vcc=5.5V, V I =O.4V

-0.5

-0.5

0.25

A or B Ports
Control Inputs

IlL

Aor B Ports
10 (Note 2) B Ports

DM54/74ALS639
-

0.35

-0.75
-50

p.A
mA

-0.75
-150

mA

Outputs High

24

40

24

40

mA

Outputs Low

75

122

75

122
61

Vcc=5.5V, Vo=2.25V

DM54/74ALS638 Vcc=5.5V

Icc

55

-150

-50

Outputs Disabled

37

61

37

Outputs High

56

92

56

92

Outputs Low

95

154

95

154

Outputs Disabled

62

100

62

100

mA

Nole 1: All typical values are at Vee=SV, TA=2S·e.
Note 2: The output conditions have been chosen to produce a current that closely approximates one half of the true short circuit output current, lOS.

\

3-187

•

DM54/74AS638 Switching Characteristics
Parameter

Input

Output

Conditions

tpLH

A

8

Yee = 4.5V to 5.5V,
C L =50pF,
RL = 500n (A Outputs),
R1 = R2 = 500n (8 Outputs),
TA = Min to Max

tpHL
tpLH

8

A

tpHL
tpLH

DM54AS638

,

Max

2

8

2

7

ns

2

7.5

2

6.5

ns

5

23

.5

20

2

8

2

7

ns
ns

19

os

A

5

20

5

2

10

2

9

ns

G

8

2

10

2

8

ns

2

12

2

10

ns

G

8

2

8

2

7

ns

2

12

2

10

ns

tPZL
tpHZ

Min

Units

Max

G

tpHL
tpZH

DM74AS638

Min

tpLZ

DM54/74AS639 Switching Characteristics
Parameter

Input

Output

Conditions

tpLH

A

8

Vee = 4.5V to 5.5V,
CL=50 pF,
RL =' 500n (A Outputs),
R1 = R2 = 500n (8 Outputs),
TA= Min to Max

tpHL
tpLH

8

A

G

A

tpHL
tpLH

DM54AS639
Min

tpHL
tPZH

G

8

tpZL
tpHZ

G

8

Max

Units
ns

2

11

2

9.5

10.5

2

9

ns

5

25

5

22

ns
ns

2

10

2

9

5

23

5

21.5

ns

2

12.5

2

11.5

ns

2

12

2

10.5

ns

2

12

2

10.5

ns

2

7

ns

2

10.5

ns

2

3-188

Min

2

2

tp~

DM74AS639

Max

7.5
12

c

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~National

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~ Semiconductor

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DM54/74AS640, DM54/74AS641, DM54/74AS642,
DM54/74AS643, DM54/74AS644, DM54/74AS645

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TRI·STATE@ Octal Bus Transceiver

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General Description

l>

This family of advanced Schottky devices contains 8 pairs
of TRI-STATE logic elements configured as octal bus
transceivers_ These circuits are designed for use in memory, microprocessor systems and in asynchronous bidirectional data buses_ These devices transmit data from
the A bus to the B bus, or vice versa, depending upon the
logic level of the direction control input (DIR)_ The enable
input (G) can be used to disable the devices, effecting
isolation of buses A and B_
The TRI-STATE circuitry also contains a protection feature
that prevents these transceivers from glitching the bus
during power-up or power-down_
The DM54f74AS640, 643 and 645 have TRI-STATE outputs,
while the DM54f74AS641, 642 and 644 feature open-collector outputs_

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full
temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TIL
process
• Functionally and pin-for-pin compatible with Schottky,
low power Schottky, and advanced low power Schottky
TIL counterpart

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• Improved AC performance over Schottky, low power
Schottky, and advanced low power Schottky
counterparts
• TRI-STATE outputs independently controlled on A and
B buses
• Low output impedance drive to drive terminated
transmission lines to 133!l
• Choice of true or inverting logic
• Choice of TRI-STATE or open-collector outputs
• Specified to interface with CMOS at VOH = Vee - 2V
• Extended drive current for DM74ALS

~I\.)

Absolute Maximum Ratings (Note 1)

:s:

SupplY,Voltage
7V
7V
Input Voltage
Operating Free-Air Temperature Range
DM54AS
-55'Cto +125'C
DM74AS
O'Cto 70'C
- 65'Cto + 150'C
Storage Temperature Range
Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Condillons" table will
define the conditions for actual device operation.

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Function Table

Connection Diagram

c

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-

Dual-In-Llne Package

_

ENABLE
~

~

~

~

~

~

(11
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(11

Control
'AS640
'AS642

Operation
'AS641
'AS645

'AS643
'AS644

L
H

ii Data to A Bus

B Oata to A Bus

B Oata to A Bus

AData to B Bus

A Data to B Bus

AData to B Bus

X

Isolation

Isolation

Isolation

Inputs

G
L
L
H

~

M

M

~

AA

M

M

~

M

~

TOP VIEW
TlIFJ6706'1

DM54AS640 thru 645 (J) DM745AS640 thru 645 (J, N) .
3-189

DIR

,

,

"

Circuit Configurations

I

Device

Output Type

Logic

DM54/74AS640
DM54/74AS641
DM54/74AS642
DM54/74AS643

TRI·STATE
Open·Coliector
Open·Collector
TRI·STATE

DM54/74AS644

Open·Coliector

DM54/74AS645

TRI·STATE

Inverting
True
Inverting
True from B to A
Inverting from A to B
True from B to A
Inverting from A to B
True

I

Recommended Operating Conditions
Symbol
Vcc

Supply Voltage

VIH

High Level Input Voltage

V il

Low Level Input Voltag.e

10H

High Level Output Current
(AS640, 643, 645 Only)

10l

Low Level Output Current

TA

Free·Air Operating Temperature

DM74AS

DM54AS

Parameter

Min

Typ

Max

Min

Typ'

Max

4.5

5

5.5

4.5

5

5.5

2

0.8

• J

-12

125

V

-15

mA

64

mA

70

"C

48
-55

V
V

2
0.8

Units

0

DM54/74AS640, 643 and 645 Electrical Characteristics
over recommended operating free·air temperature unless otherwise noted
Symbol

Parameter

Conditions

VI

Input Clamp Voltage

Vcc=Min, 11= -18mA

.,...

VOH

High Level Output Voltage

Vcc = 4.5V to 5.5V, 10H = Max

co

VOL

Low Level Output Voltage

Vcc = Min, 10l = Max

-=t

~

-=t

II)

c

o
-=t

Control Inputs

20

flA

Aor B Ports

70

High Level Input Current

Vcc= Max,
VI=2.7V

CO

CIJ

V
V

0.1

II~'

Vcc= Max,
VI=0.4V

-1.2
2.4

Units

V

Vcc = Max, VI = 7V,
(VI = 5.5V for A or B Ports)

Low Level Input Current

Max

mA

,Input Current at Max Input Voltage

III

Typ
(Note 1)

0.55

II

:!!:

Min

0.35

Control Inputs

-0.5

A or B Ports

-0.75

mA



en

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~

(3)

0)

(23)

C

(22)

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(1)
(2)

~

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------- --- 1 OF 8 CHANNELS

~

a

A and B: Req· 10 k!l NOM
CAB and CBA: Req • 10 k NOM
ALL OTHER: 5 k!!NOM

I
I
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(4) I

TLI F16324·3
B1

A1

TYPICAL OF ALL' AS646, 'AS648 OUTPUTS

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C

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a

VCC

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L _____ _

I
-

-

-

-

-

-

-

-

-

-

-

-

-

-

_ _ ...I

/

V

OUTPUT

TLI F16324·2

TO 7 OTHER CHANNELS

TLlF/6324·4

DIR ~="-""--4
:BA

~~-----=~--~---~-----~~--------t-,

...--I:>---'-'

SBA ~~-----+-

CAB ----.,,,,..----,
SAB

.....:.;:,..--I---+...- D -...---.

r
I

-

1 OF 8 CHANNELS

o
CLK<1!>-_+-+"
r~+=t:::f-~ a

(4)

I
1(20)
....++-~_-B1

-+-+.....

A1 ...........

D

L ____________ _

--'

/

V
TO 7 OTHER CHANNELS

TL/F/6324·5

3·195

Recommended
.
. Operating Conditions
DM54AS646,648
Parameter
Supply Voltage, VCC
High Level Input Voltage, VIH

DM74AS646,648

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5·

5

5.5

2

2

Unit
V
V

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Current, 10H

-12

-15

mA

Low Level Output Current, 10L

32

48

mA

90

MHz

Clock frequenCfY, fCLOCK

75

0

0

High

6

5

ns

Low

7

6

ns

Data Setup rime, TSU

71

61

ns

Data Hold Time, TH

01

01

ns

Width of Clock Pulse, TW

The (I) arrow indicates the positive edge of the Clock is used for reference.

Electrical Characteristics

over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25°C.

\

Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC=4.5V, 11= -18mA

VOH

High Level Output
Voltage

VCC = 4.5V
VIL = VIL MAX
VIH = VIH MIN

Min

10H = MAX
IOH=.-3mA
10H= -2mA

VOL

Low Level Output
Voltage

VCC T 4.5V
VIH = 2V
VIL = VIL MIN

II

Max High Input Current

VCC = 5.5V

IIH

IlL

High Level Input Current

Low Level Input Cwrent

Output Drive Current

Max

Unit

-1.2

V
V

2
2.4

3.2

VCC -2
0.35

10L = MAX

0.5

V

mA

VI=7V

Control Inputs

0.1

VI =5.5V

Aor B Ports

0.1

Control Inputs

20

Aor B Ports

70

VCC = 5.5V, VIH = 2.7V·

VCC=5.5V, V'L=0.4V

-0.5

Control Inputs
A or B Ports

10

Typ

VCC=5.5V, VO=2.25V
3-196

".A

mA

-0.75
-30

-112 .

mA

Electrical Characteristics

(Continued) over recommended operating free air temperature range.

11,11 typical values are measured at Vee = 5V, TA = 25°C.
Symbol

Parameter

Conditions

ICC

Supply Current

VCC

=

Typ

Max

Outputs
High

120

195

Outputs
Low

130

211

Outputs
Disabled

130

211

Outputs
Low

120

195

Outputs
High

110

185

Outputs
Disabled

120

195

Min

5.SV

'AS646

Unit

mA

'AS648

AS646 Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured 'at Vee = 5V, T A= 25°C.

Parameter

From
(Input)

To
(Output)

Clock

Bus

tPHL
tpLH

Bus

Bus

tpHL
tPLH
tpHL
tPLH
tPHL

Min

Typ

Max

Select, with
bus input
high

Bus

RL = 500 n,
CL = SOpF.
See Note 1

Select, with
bus input
low

Min

Typ

Unit

Max

MHz

90

75

fMAX
tPLH

DM74AS646

DM54AS646
Conditions

2

9.5

2

8.5

ns

2

10

2

9

ns

2

11

2

9

,ns

1

8

1

7

ns

2

12

2

11

ns

2

10

2

9

ns

2

12

2

11

ns

2

10

2

9

ns

I

2

10

2

9

3

15

3

14

ns

tPHZ

2

11

2

9

ns

tpLZ

2

11

2

9

ns

tpZH

3

20

3

18

ns

3

22

3

20

ns

tpHZ

2

12

2

10

ns

tpLZ

2

12

2

10

ns

tpZH
tPZL

Enable

G

tPZL

Direction
DIR

Bus

Bus

Note 1: See Section 1 for test waveforms and output load.

3-197

ns

~
co 'AS648 Switching Characteristics over recommended operating free air temperature range (Note 1).

~

All typical values are measured at Vcc =5V, TA = 25"C.

;:!:
:!E

From
(Input)

Parameter

c

CO

To
(Output)

DM54AS648
CO'1ditions

Typ

DM74AS648

Max

Min

Typ

Unit

Max

MHz

90

75

fMAX

~

Min

CO

~

tPLH

Lt)

Clock

Bus

tPHL

:!E

c

tpLH

cD
~

tpHL

~

tPLH

:!E

tPHL

CO

;:!:

c

Bus

Select, with
bus input
high

~

CO

tPHL

en

CLK

U)

al---++-+-......L~

:!:
c

-_--VCC

- -"'
OUTPUT

V
TO 7 OTHER CHANNELS

G
DIR
CBA
SBA

TL/F/6325-2

(21)

TL/F/6325·4
(3)
(23)
(22)

CAB
SAB

r I

1 OF B CHANNELS

I
1(20)

(4) I
A1 -+-:......J-4~

....+-+--'-4_-

B1

D

....++---ct>CLK
a i----+-_+__+__+_{ _ J
L _

- - - -' - - - - - - - -"'
,-

\

V
TO 7 OTHER CHANNELS

TLlF/6325-5

3·200

~ecommended

c

s:
C1I

Operating Conditions
DM74AS651,652

DM54AS651,652
Parameter
Supply Voltage, VCC
High Level Input Voltage, VIH

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

.5

5.5

V
V

2

2

Unit

0.8

0.8

V

. High Level Output Current, 10H

-12

-15

mA

Low Level Output Current, 10L

32

48

mA

90

MHz

Low Level Input Voltage, VIL

75

0

Clock frequency, fCLOCK

,

0

High

6

5

ns

Low

7

6

ns

Data Setup Time, TSU

7

6

ns

Data Hold Time, TH

0

0

ns

Width of Clock Pulse, TW

The (1) arrow indicates the positive edge of the Clock is used for reference.

,

Electrical Characteristics over recommended operating fr~e air temperature range.
All typical values are measured at Vce = 5V, TA = 25°C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC =4.5V, II = -18mA

VOH

High Level Output
Voltage

VCC = 4.5V
VIL = VIL MAX
VIH = VIH MIN

Min

10H = MAX
10H= -3mA
10H= -2mA

VOL

Low Level Output
Voltage

VCC = 4.5V
VIH = 2V
VIL = VIL MIN

II

Max High Input Current

VCC = 5.5V

IIH

IlL

High Level Input Current

Low Level Input Current

Output Drive Current

Max

Unit

-1.2

V

2
2.4

V
3.2

VCC -2
0.35

10L = MAX

0.5

V

mA

VI=7V

Control Inputs

0.1

VI=5.5V

A or B Ports

0.1

Control Inputs

20

A or B Ports

70

VCC = 5.5V. VIH =2.7V

VCC=5.5V. VIL=O.4V

-0.5

Control Inputs
A or B Ports

10

Typ

VCC = 5.5V, Vo = 2.25V
3-201

I'A

mA

-0.75
-30

...; 112

mA

~
m
.....

-s:
C

~
l>
en
en
C1I
.....

~

Electrical Characteristics (Continued)

over recommended operating free air temperature range.

All typical values are measured at Vce = 5V, T A = 25°C.
Symbol

Parameter

ICC

Supply Current

'Conditions

Typ

Max

Unit

Outputs
High

110

185

mA

Outputs
Low

120

195

Outputs
Disabled

130

195

Min

VCC = S.SV

'AS651

Outputs
Low
'AS652

195

120

-

f

Outputs
High

130

211

Outputs
Disabled

130

211

'AS651 Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vec =5V, TA = 25°C.

Parameter

From
(Input)

To
(Output)

DM54AS651
Conditions

Min

Typ

DM74AS651

Max

75

fMAX

Min

Typ

Max

90

Unit
MHz

2

9.5

2

8.5

ns

2

10

2

9

ns

2

9

2

8

ns

1

8

1

7

ns

2

12

2

11

ns

2

10

2

9

ns

2

12

2

11

ns

2

10

2

9

ns

2

11

2

. 10

ns

3

18

3

16

ns

tPHZ

2

10

2

9

ns

tpLZ

2

10

2

9

ns

tPZH

3

12

3

11

ns

3

20

3

16

ns

tPHZ

2

11

2

10

ns

tPLZ

2

12

2

11

ns

tPLH

Clock

Bus

tPHL
tPLH

Bus

Bus

tPHL
tpLH
tPHL
tPLH
tPHL

Select. with
bus input
high

Bus

RL = 500 I!.
CL = 50pF.
See Note 1

Select. with
bus input
low

tPZH
tpZL

tpZL

Enable GBA

Enable GAB

A Bus

B Bus

3·202

c

:s:
en

'AS652 Switching Characteristics over recommended operating free air temperature ra,nge (Note 1),

~

!l,1I typical values are measured at Vee = 5V, TA = 25"C.
From
(Input)

Parameter

' DM54AS652

To
(Output)

Conditions

Min

Typ

DM74AS652

Max

Typ

Q)

Max

MHz

90

75

fMAX

Min

Unit

2

9.5

2

8.5

ns

2

10

2

9

ns

2

11

2

9

ns

1

8

1

7

ns

2

12

2

11

ns

2

10

2

9

ns

2

12

2

11

ns

2

10

2

9

ns

tPZH

2

11

2

10

ns

tPZL

3

18

3

16

ns

tpHZ

2

10

2

9

ns

tPLZ

2

10

2

9

ris

tpZH

3

12

3

11

ns

3

20

3

16

ns

tPHZ

2

11

2

10

ns

tPLZ

2

12

2

11

ns

tPLH

Clock

Bus

tpHL
tPLH
tpHL

-

Bus

Bus

Select, with
bus input
high

tPLH
tPHL

RL = 500 II,
CL = 50pF.
See Note 1

Bus

Select, with
bus input
low

tPLH
tpHL

Enable GBA

tPZL

A Bus

B Bus

Enable GAB

Note 1: See Section 1 for test waveforms and output load.

Function Table
INPUTS
GAB GBA

L

CAB

CBA

L

H
H

H or L H or L
1
1

L
L

L
L

X
X

H
H

H
H

X
H or L

H

L

HorL HorL

DATA I/O·

OPERATION OR FUNCTION

SAB SBA A1 THRUA8 B1 THRU B8

'AS651

'AS652

X
X

X
X

Input

Input

Isolation
Store A and B Data

X
H or L

X
X

L
H

Output

Input

Real Time 8 Data to A Bus
Stored B Data to A Bus

Real Time B Data to A Bus
Stored B Data to A Bus

X
X

L
H

X
X

Input

Output

Real Time Ii. Data to B Bus
Stored Ii. Data to B Bus

Real Time A Data to B Bus
Stored A Data B Bus

H

H

Output

Isolation
Store A and B Data

-

,

Output

Stored

Ii. Data to B Bus
B Data to A Bus

& Stored

H-

high level

L -low level

X -'irrevelant

Stored A Data to B Bus
& Stored B Data to A Bus

1 -Iow-to-~igh-Ievel transition

'The data output functions may be enabled or disabled by various signals at the GAB and GBA inputs. Data input functions are
always enabled. i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs.

3-203

....en

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....

en

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en

~

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N

C

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N

m

~ ~ National.

~

a

~

These devices contain six independent drivers, each of
which performs the logic NAND function. Each driver
has increased output drive capability to allow the driving
of high capacitive loads.

Semiconductor

.....
~ DM54AS804B/DM74AS804B Hex 2-lnput NAND Drivers

m
~ General Description

:E

o

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS
DM74AS
Storage Temperature Range

Features
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
• Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
• . Functionally and Pin for Pin Compatible with Advanced
Low Power Schottky TTL Counterpart.

Dual·ln·Line Package
58

5A

IA

18

IY

2A

7V
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Nota 1: The "Absolute Maximum Ralings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommendeq Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

vee

(Note 1)

58

5A

5Y

48

4A

28

2Y

3A

38

3Y

4Y

TL/F/6326·1

74AS804B (J. N)

54AS804B (J)

Function Table

Inputs

Output

A

B

Y

L
L
H
H

L
H
L
H

H
H
H
L

H = High Logic Level
L Low Logic Level

=

3-204

Recommended Operating Conditions
DM54ASB04B
Parameter
Supply Voltage, VCC
High Level Input Voltage, VIH

DM74ASB04B

Min

Nom

Max

Min

4.5

5

5.5

4.5

2

. Nom
5

Max
5.5

2

Unit
V
V

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Current, 10H

-40

-48

mA

Low Level Output Current, 10L

40

48

mA

Max

Unit

-.1.2

V

Electrical Characteristics over recommended operating free air temperature range.

-

All typical values are measured at Vce = 5V, TA = 25'C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.5V, II = -18mA

VOH

High Level Output
Voltage

10H = - 2mA, VCC = 4.5V to 5.5V

Min

VCC-2
2.4

10H = - 3m A, VCC = 4.5V

Low Level Output
Voltage

VCC = 4.5V
10L = MAX
VIH = 2V

II

Max High Input Current

IIH

V

2

10H = MAX, VCC=4.5V
VOL

Typ

0.35

0.5

V

VCC = 5.5V, VIH = 7V

0.1

mA

High Level Input Current

VCC = 5.5V, VIH = 2.7V

20

/-LA

IlL

Low Level Input Current

VCC = 5.5V, VIL = 0.4V

-0.5

mA

10

Output Drive Current

VCC = 5.5V

Vo = 2.25V

ICC

Supply Current

VCC = 5.5V

Outputs High

2.5

4

mA

Outputs Low

16

27

mA

mA

-135

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at· Vee = 5V, TA = 25'C.
OM 54ASB04B
Parameter
TpLH, Propagation
, delay time. Low to
high level output

Conditions
Vec = 4.5 to 5.5V
RL = 500 n,
CL = 50 pF.

TpHL, Propagation
delay time. High to
. low level output

Min

Typ

Max

Unit

Max

Min

1

4.5

1

3.5

ns

1

4.5

1

3.5

ns

Note 1: See Section 1 for test waveforms and output load.

3·205

Typ

DM74ASB04B

mr-----------------------------------------------------------------,
i ~National
~
Semiconductor

a

-~ DM54AS805B/DM74AS805B Hex 2-lnput NOR Drivers
m
ID

I
:::E
c

General Description

Absolute Maximum Ratings (Note 1)

These devices contain six independent drivers, each of
which performs the logic NOR function. Each driver has
increased output drive capability to allow the driving of
high capacitive loads.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS
DM74AS
Storage Temperature Range

Features
•
•

Switch'ing Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Rang~.
• Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
•

7V
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits, The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings, The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Functionally and Pin for Pin Compatible with Advanced
Low Power Schottky TTL Counterpart.

Connection Diagram
Dual-In-Line Package

vee

68

6A

6Y

58

5A

5Y

48

4A

IA

18

IY

2A

28

2Y

3A

38

3Y

4Y

TLlF/6327·1

74AS805B (J, N)

54AS805B (J)

Function Table
Y=A+B
Inputs

Output

A

B

Y

L
L
H
H

L
H
L
H

H
L
L
L

H = High Logic Level
L = Low Logic LeYel

3-206

c

~ecommended

s::

Operating Conditions

(,J1

DM54AS805B
Parameter
Supply Voltage, VCC
High Level Input Voltage, VIH

DM74AS805B

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

2

Unit
V
V

~

(X)

o(,J1

-s::
OJ

C

......

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Current, 10H

-40

-48

mA

»en

48

mA

o(,J1

Max

Unit

-1.2

V

Low Level Output Current, 10L

40

!

Electrical Characteristics over recommended operating free air temperature range.
~II

typical values are measured at Vee = 5V, TA = 25'C.

Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.5V, II = -18mA

VOH

High Level Output
Voltage

10H = - 2mA, VCC = 4.5V to 5.5V

Min

VCC-2
2.4

10H = - 3mA, VCC = 4.5V

Low Level Output
Voltage

VCC = 4.5V 10L = MAX

II

Max High Input Current

IIH

V

2

10H = MAX, VCC = 4.5V
VOL

Typ

0.35

0.5

V

VCC = 5.5V, VIH = 7V

0.1

mA

High Level Input Current

VCC = 5.5V, VIH = 2.7V

20

/lA

IlL

Low Level Input Current

VCC = 5.5V, VIL = 0.4V

-0.5

mA

10

Output Drive Current

VCC = 5.5V

Vo = 2.25V

-135

ICC

Supply Current

VCC = 5.5V

Outputs High

5

9

mA

Outputs Low

18

32

mA

mA

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee= 5V, TA = 25'C.
DM74AS805B

DM54AS80SB'
Parameter

Conditions

TpLH, Propagation
delay time. Low to
high Level OutPlJt

VCC = 4.5 to 5.5V
RL = 500 n,
CL = 50 pF.

TPHL, Propagation
delay time. High to
low Level Output

Typ

Typ

Max

Unit

Max

Min

1

4.5

1

4

ns

1

4.5

1

4

ns

Min

Note 1: See Section 1 for test waveforms and output load.

3·207

.1:10

(X)

OJ

~National

a

-

Semiconductor

DM54AS808B/DM74AS808B Hex 2-lnput AND Drivers

a:I

co

~ General Description
en These devices contain six independent drivers, each of

~
U)

::E

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS
DM74AS
Storage Temperature Range

which performs the logic AND function. Each driver has
increased output drive capability to allow the driving of
high capacitive loads.

Q

Features
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
• Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
•

not be operated at these limits. The parametric values defined In the

"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Condilions"table will
define the conditions for actual device operation.

Connection Diagram
Dual-In-Llne Package
6B

6A

IA

IB

IY

-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

Functionally and Pin for Pin Compatible with Advanced
Low Power Schottky TTL Counterpart.

vee

7V
7V

fiY

5B

5A

5Y

4B

4A

3A

3B

3Y

TL/F/6328·1

54AS808B (J)

74AS808B (J, N)

Function Table
Y=AB
Inputs

Output

A

B

Y

L
L
H
H

L
H
L
H

L
L
L
H

H = High logic Level
L = Low Logic Level

3-208

------------------------------------------------------------~----~c

s:::
c.n

Recommended Operating Conditions
DM54AS808B
Parameter

Supply Voltage, VCC
High Level Input Voltage, VIH

DM74AS808B

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

V
V

2
0.8

Low Level Input Voltage, VIL

Unit

0.8

V

High Level Output Current, 10H

-40

-48

mA

Low Level Output Current, 10L

40

48

mA

Max

Unit

-1.2

V

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25'C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC

VOH

High Lev.el Output
Voltage

10H = - 2mA, VCC = 4.5V to 5.5V

=

Min

Typ

4.5V, II = -18mA
VCC-2

V

2.4

10H= -3mA, VCC=4.5V

2

10H=MAX, VCC=4.5V
VOL

Low Level Output
Voltage

VCC=4.5V,IOL=MAX

II

Max High Input Current

VCC = 5.5V, VIH

=

IIH

High Level Input Current

VCC = 5.5V, VIH

IlL

Low Level Input Current

VCC = 5.5V, VIL

10

Output Drive Current

VCC = 5.5V

Vo = 2.25V

-135

ICC

Supply Current

VCC

Outputs High

6.5

11

Outputs Low

19

32

=

0.5

V

7V

0.1

mA

=

2.7V

20

J.l.A

=

O.4V

-0.5

mA

5.5V

0.35

mA
mA

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V, TA = 25'C;
DM54AS808B
Parameter

Conditions

TpLH, Propagation
delay time. Low to
high Level Output

VCC = 4.5 to 5.5V
RL = 500 n,
CL = 50 pF.

TpHL, Propagation
delay time. High to
low Level Output

Typ

DM74AS808B

Typ

Min

1

6

1

5

ns

1

6

1

5

ns

Note 1: See Section 1 for test waveforms and output load.

3·209

Max

Unit

Max

Min

~

co
o

CO

til

C

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-...
~

~
CO

o

CO

til

o

~National
~ ~ Semiconductor

i

PRELIMINARY

:::aE

c
o
,..

~

DM54AS810/DM74AS810 Quad 2-lnputExclusive-NOR Gates

:::aE

c

General Description

Absolute Maximum Ratings (Note 1)

This device contains four independent gates each of
which performs the logic exclusive·NOR function.

Supply Voltage
Input Voltage
Storage Temperature Range

Features

7V
5.5V
- 65'Cto 150'C

• SWitching specifications at 50 pF
• Switching specifications guaranteed over full
temperature and Vcc range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky,
low power Schottky, and advanced low power
Schottky TTL counterpart
• Improved AC performance over Schottky, low power
Schottky, and advanced low power Schottky
counterparts

Nota 1: The "Absolute Maximum Ratings" are those values beyond
which Ihe safety ollhe device can not be guaranteed. The device should
not be operaled al these IImlis. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
dellnelhe conditions for actual device operation.

Connection Diagram

Function Table

Dual-In-Line Package
B3

A3

Y3
Inputs

B

V

L
L

L

H

H
L

L
L

H

H

H
H
H

B1

A2

B2

Y2

=High Logie Level

L = Low logic Level

7

A1

Output

A

GND

TLIF/6724·1

DM54AS810 (J)

DM74AS810 (J, N)

This document contains information on a product under development. NSC reserves the right to change or discontinue this product without notice.

3-210

c

s:
C1I

Recommended Operating Conditions
DM74AS810

DM54AS810

Units

Symbol

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level Input
Voltage

0.8

10H

High Level Output
Current

-2

-2

mA

10l

Low Level Output
Current

20

20

mA

TA

Free Air Operating
Temperature

70

·C

Electrical Characteristics
Symbol

Parameter

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

125

V

1;;

o

0.8

0

V

-s:

V

2

-55

over recommended operating free air temperature (unless otherwise noted)
Conditions

VI

Input Clamp Voltage

Vee = Min, 11= -18 mA

VOH

High Level Output
Voltage

DM54
Vee = 4.5V to 5.5V
'OH=Max
DM74
VIH = Min, Vil = Max

VOL

Low Level Output
Voltage

Vee = Min, 10l = Max
VIH = Min, Vll= Max

II

Input Current@Max
Input Voltage

IIH
III

Min

Typ
(Note 1)

Vee- 2V

3.4

Vee- 2V

3.4

Max
-1.2

Units
V
V

0.5

V

Vee = Max, VI = 5.5V

0.1

mA

High Level Input
Current

Vce=Max, VI=2.7V

20

p.A

Low Level Input
Current

Vce = Max, VI = 0.5V

-0.5

mA

-112

mA

0.35

-30

10

Output Drive Current

Vcc= Max, Vo= 2.25V

ICCH

Supply Current With
Outputs High

Vce= Max
(Note 3)

mA

ICCl

Supply Current With
Outputs Low

Vce= Max
(Note 2)

rnA

NOle 1: All typicals are at VCC=5V, TA=25'e.
Nole 2: ICCl is measured with all outputs open, one input of each gale at 4.5V, and the other inputs grounded.
NOle 3: ICCH is measured with all outputs open and all inputs at 4.5V.

3·211

~......

CO

C

~

CO
......
o

o

T""

~

«
~
~

c
oT""

CO

~

II)

~

c

Switching Characteristics over recommended operating free air temperature range
DM74AS810

DM54AS810
Parameter

Conditions

tpLH Propagation
Delay Time Low
,
to High Level
Output

Other Input Low
Vee ~ 4.5V to 5.5V

Min

Typ

Min

Typ

Max

Units

ns

RL~5000
CL~50pF

ns

tpHL Propagation
Delay Time
High to Low
Level Output
tpLH Propagation
Delay Time Low
to High Level
Output

Max

ns

Other Input High
Vee ~ 4.5V to 5.5V
RL~5000
CL~50pF

ns

tpHL Propagation
Delay Time High
to Low Level
Output

3·212

~----------------------------------------------------------------~c

PRELIMINARY

II?'A National

~ Semiconductor

s:

~

co
.....

.....
DM54AS811/DM74AS811 Quad 2-lnput Exclusive-NOR Gates
~

~

with Open-Collector Outputs

1;;
co
.....
.....

General Description

Features

This device contains four independent gates each of
which performs the logic exclusive·NOR function. The
open·collector outputs require external pull·up resistors
for proper logical operation.

• Switching specifications at 50 pF

Pull·Up Resistor Equations

•

VCC (min) - V OH

VCC (max) - VOL
IOL -

• Advanced oxide·isolated, ion·implanted Schottky TTL
process
Functionally and pin for pin C{ompatible with Schottky,
low power Schottky, and advanced low power
Schottky TTL counterpart

• Improved AC performance over Schottky, low power
Schottky, and advanced low power Schottky
counterparis

N1 (IOH) + N2 (IIH)
Rmin=

• Switching specifications guaranteed over full
temperature and Vcc range

N3 (lid

Where N1 (I OH ) = total maximum output high current for all
outputs tied to pull·up resistor
N2 (IIH) = total maximum input high current for all
inputs tied to pull·up resistor
N3 (1Id=total maximum input low cuhent for all
inputs tied to pull·up resistor

Connection Diagram

Absolute Maximum Ratings (Note 1)
Supply Voltage

7V

Input Voltage

5.5V
- 65·Cto 150·C

Storage Temperature Range

Nola 1: The "Absolute Maximum Ratings',' are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions"table will
define the conditions for actual device operation.

Function Table

Dual·ln·Line Package

vee

84

A4

Y4

83

A3

Y3

Inputs

Output

A

B

Y

L
L
H
H

L
H
L
H

H
L
L
H

=

H High Logic Level
L.d Low Logic Level

7

A1

81

Y1

A2

82

Y2

GND

TLlF/6725·1

DM54AS811 (J)

DM74AS811 (J, N)

ThiS document contains information on a product under development. NSC reserves the right to change or discontinue this product without notice.

3·213

-

Recommended Operating. Conditions
Symbol

DM54AS811

Parameter

DM74AS811

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.5

Units

Vcc

Supply Voltage

VIH

High Level Input
Voltage

V IL

Low Level Input
Voltage

0.8

0.8

V

VOH

High Level Output
Voltage

5.5

5.5

mA

IOL

Low Level Output
Current

20

20

mA

TA

Free Air Operating
Temperature

70

·C

2

-55

Electrical Characteristics
Symbol

Parameter
Input Clamp Voltage

VI

V

2

125

0

over recommended operating free air
Conditions

V

temperat~re (unless otherwise

Min

Typ
(Note 1)

Vcc= Min, 11= -18 mA

Max

noted)
Units

-1.2

V

100

p.A

0.5

V

ICEx

High Level Output
Current

Vcc=Min, Vo=5.5V
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vec= Min, IOL= Max
VIH = Min, VIL = Max

II

Input Current@ Max
Input Voltage

Vec = Max, VI = 7.0V

0.1

niA

IIH

High Level Input
Current

Vec=Max, VI=2.7V

20

p.A

lecH

Supply Current With
Outputs High

Vec= Max
. ·(Note 3)

mA

ICCL

Supply Current With
Outputs Low

Vcc= Max
(Note 2)

mA

Notal: All typlcals are at Vce=5V, TA=25'C.
Nola 2: leCL Is measured with all outputs open, one input of each gate at 4.5V, and the other inputs grounded.
Nota 3: ICCH is measured with all outputs open and all inputs at 4.5V.

I

3·214

0.35

,

-

c

s::en

Switching Characteristics over recommended operating free air temperature range
Parameter
tpLH Propagation
Delay Time Low
to High Level
Output

Conditions

DM54AS811
Min

Typ

Min

Typ

Max

Units
ns

Other Input Low
Vee = 4.5V to 5.5V
RL=5000
C L = 50 pF

ns

tpHL Propagation
Delay Time
High to Low
Level Output
tpLH Propagation
Delay Time Low
to High Level
Output

DM74AS811
Max

~

00
.....
.....

-s::
C

i:!
~
00
.....
.....

ns

Other Input High
Vee = 4.5V to 5.5V
RL =5000
CL =50pF

ns

tpHL Propagation
Delay Time High
to Low Level
Output

•
,

,

3·215

.
D Semiconductor
~National

DM54AS832B/DM74AS832B Hex 2-lnput OR Drivers
General Description

Absolute Maximum Ratings (Note 1)

These devices contain six independent drivers, each of
which performs the logic OR function. Each driver has increased output drive capability to allow the driving of
high capacitive loads.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DMS4AS
DM74AS
Storage Temperature Range

Features
• Switching Specifications at SO pF.
• Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
• Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
• Functionally and Pin for Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.
• Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.

7V
7V
-SSOC to 12SoC
O°C to 70°C
-6S"C to 1S0°C

Note 1: The "Absolute Maximum Ratings" are those yalues beyond
which the safety of the deYice can not be guaranteed. The device should
not be operated al these limits. The parametric values defined in the

"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Condltlons"table will
define the conditions .or actual device operation.

Connection Diagram
Dual-In-Llne Package

"
TL/F/6329-1

54AS832B (J)

74AS832B (J, N)

Function Table
Y=A+B
Inputl

Output

A

B

Y

L
L
H
H

L
H
L
H

L
H
H
H

H = High Logic Level
L Low Logic Leyel

=

3-216

Recommended Operating Conditions
DM54AS832B
Parameter
Supply Voltage, VCC
High Level Input Voltage, VIH

DM74AS832B

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

V
V

2

Low Level Input Voltage, VIL

Unit

. 0.8

0.8

V

High Level Output Current, 10H

-40

-48

mA

Low Level Output Current, 10L

40

48

mA

Max

Unit

-1.2

V

Electrical Characteristics over recommended operating free air temperatu're range.
All typical values are measured at Vee = 5V, T A = 25°C.
Symbol

Min

Parameter

Conditions

VIK

Input Clamp yoltage

VCC = 4.5V, II = -18mA

VOH

High Level Output
Voltage

10H = - O.4mA, VCC = 4.5V to 5.5V

VCC-2

10H = - 3m A, VCC = 4.5V

Low Level Output
Voltage

VCC=4.5V, 10L= ~AX

II

Max High Input Current

VCC

=

5.5V, VIH

IIH

High Level Input Current

VCC

=

IlL

Low Level Input Current

VCC

=

10

Output Drive Current

VCC = 5.5V

ICC

Supply Current

VCC

=

V

2.4

10H = MAX, VCC = 4.5V
VOL

Typ

2
0.5

V

0.1

mA

5.5V, VIH = 2.7V

20

J1.A

5.5V, VIL = 0.4V

-0.5

mA

==

0.35

7V

-

Outputs High

5.5V

mA

-135

Vo = 2.25V

Outputs Low

9

17

mA

22

36

mA

SWitching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are m~asured at Vec = 5V, TA = 25°C.
DM54AS832B
Parameter

Conditions

TpLH, Propagation
delay time. Low to
high Level Output

VCC = 4.5 to 5.5V
RL = 500 n,
CL = 50 pF.

TpHL, Propagation
delay time. High to
low Level Output

Min

DM74AS832B
Unit

Min

1

7

1

5.5

ns

1

6.5

1

5.5

ns

3-217

Typ

Max

Max

Note 1: See Section 1 for test waveforms and output load.

Typ

; ~ National, .
~ ~ Semiconductor
::E
Q

I

PRELIMINARY

DM54AS841/DM74AS841, DM54AS842/DM74AS842
10-Bit Bus Interface D-Type Latches with
TRI-STATE® Outputs

1.1)

::E General Description
Q

Features

These 10-bit latches feature TRI-STATE outputs designed
specifically for driving highly capacitive or relatively low
impedance loads. They are particularly s\Jitable for implementing buffer registers, 1/0 ports, bidirectional bus
drivers, and working registers.

• 10-bit versions of 'AS573/588 with improved 10H
speCifications

The 10 latches are transparent Ootype latches. While the
enable (C) is high, the' AS841 Q outputs will follow the data
inputs and the' AS842 Q outputs will complement the data
inputs. When theenable (C) is taken low, the 'AS841 Q outputs will be latched at the levels that were set up a,! the 0
inputs, while the 'AS842 Q outputs will be latched at the
complement of the 5 input levels.

• Power-up in TRI-STATE

A buffered output control (OC) input can be used to place
the latch output in either a low impedance (high or low logic
level) or a high impedance state (fRI-STATE).ln the high Impedance state, the outputs neither load nor drive the bus
lines significantly. The high Impedance TRI-STATE and increased drive. in the low impedance states provide the
capability to drive the bus lines In a bus-organlzed system
without the need for Interface or pull-up components.

• Provides extra bus driving latches necessary for wider
address/data paths or busses with parity
• Buffered control Inputs to reduce DC loading

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage

7V
7V

Storage Temperature Range

- 55"Cto

+ 150"C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed, The device should
not be operated at these limits, The parametric values defined In the
"Electrical Characterlsllcs" table are not guaranteed at the absolute
maximum rallngs. The "Recommended Operallng Conditions" table will
define the conditions for actual device operation.

The output control (OC) does not affect the Internal operation of the latches. Old data can be retained or new data
entered while the outputs are In TRI-STATE

Connection Diagrams
Dual-ln·Llne Package

Dual·ln·Llne Package
!

DC

24

Vee

DC

24

Vee

01

23

01

iii

23

01

02

22

02

52

22

02

03

21

03

ii3

21

03

04

20

04

D4

20

04

05

19

05

ii5

19

05

06

18

06

ii6

18

06

07

17

17

07

07

ii'i

08

08

DB

16

08

09

09

ii9

10

15

09

010

010

010

11

14

010

GND

12

13

GNO
TOP VIEW

DM54AS841 (J)

TOP VIEW

TLlF/6726-1

DM54AS842 (J)

DM74AS841 (N)

TLlFf6726·2

DM74AS842 (N)

This document contains informatlo.n on a product under development. NSC reserves the right to change or discontinue this product without notice.

3-218

Recommended Operating Conditions
Symbol

I

Vee

Supply Voltage

VIH

High-Level Input Voltage

VIL

Low-Level Input Voltage

10H

High·Level Output Current

10L

Low-Level Output Current

tw

Pulse Width, Enable (e) High

tsu

Set·Up Time, Data to Enable (C)

tH

Hold Time, Enable (C) to Data

TA

Operating Free-Air Temperature

DM74AS841

DM54AS841

Parameter

Units

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

V
V

2

2

V

0.8

0.8

-24

-24

mA

32

48

mA

5

4

ns

c

3.5

2.5

ns

i-

3.5

ns

2.5

-55

125

·c

70

0

s::

c

s::

Electrical Characteristics over recommended free-air operating temperature range
DM54AS841
Parameter

Conditions

VI

Vee= Min, II = -18 mA

VOH

Vee = 4.5V to 5.5V, 10H = - 2 mA

Vee = Min, 10H = - 24 mA

2

10ZH

Vee = Max, Vo=2.7V

Min

Typ
(Note 1)

-1.2

2.4

Vee = Min, 10L= Max

Max

Vee-2

Vee= Min, 10H= -15 mA

VOL

Typ
(Note 1)

Min

~

DM74AS841
Max
-1.2

2.4

3.2

V
V

2
0.25

V
V

Vee- 2
3.2

Units

0.5

V

50

50

I,A
I,A

0.5

0.25

10ZL

Vee= Max, Vo=0.4V

-50

-50

II

Vee = Max, VI= 7V

0.1

0.1

i'A

IIH

Vee= Max, VI = 2.7V

20

20

i'A

IlL

Vee= Max, VI = 0.4V

los

Vee = Max, Vo= 2.25V

Icc

Vee= Max, Outputs High

-0.5

mA

-112

mA

36

60

mA

-0.5
-30

-112

-30

36

60

Vee = Max, Outputs Low

58

94

58

94

mA

Vee = Max, Outputs Off

56

92

56

92

mA

Switching Characteristics over recommended free-air operating temperature
DM54AS841
Parameter Input Output

tpLH

0

a

tpHL
tpLH

C

a

Conditions

Vee= 4.5V to 5.5V
R1 =500n
R2=500n
C L = 50 pF

tpHL
OC

a

Min

Typ
(Note 1)

DM74AS841
Typ
(Note 1)

Max

Units

Max

Min

1

8.5

1

6.5

ns

1

10

1

9

ns

2

13

2

12

ns

2

13

2

12

ns
ns

2

13.5

2

10.5

tPZL

2

14.5

2

11.5

ns

tpHZ

1

10

1

8

ns

tpLZ

1

10

1

8

ns

tPZH

Nola 1: All typicals are measured at Vee=5V and TA= 25·e.

3·219

i

Recommended Operating Conditions
Symbol
Vee

Supply Voltage

VIH

High·Level Input Voltage

VIL

Low·Level Input Voltage

10H

High·Level Output Current

10L

Low·Level Output Current

tw

Pulse Width, Enable (C) High

tsu

Set·Up Time, Data to Enable (C)

tH
TA

DM54AS842

Parameter

DM74AS842

Min

typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

2

Operating Free··Air Temperature

V
V

2
0.8

0.8

~24

-24

V
mA

48,

32

. Hold Time, Enable (C) to Data

Units

mA

5

4

3.5

2.5

ns

3.5

2.5

ns

125 '

-55

ns

·c

70

0

Electrical Characteristics over recommended free·air operating temperature range
DM54~S842

Parameter

Conditions

VI

Vee = Min, 'I = -18 mAo

VOH

Vee = 4.5V to 5.5V, IOH = - 2 mA

DM74AS842

Typ
(Note 1)

Min

Max

Min

Typ
(Note 1)

-1.2

-1.2

2.4

Vee = Min, IOH = - 24 mA

2

3.2

2.4

Units

V
V

Vee- 2

Vee- 2

Vee = Min, IOH = -15 mA

Max

V

3.2

2

V
0.5

V

50

50

p.A

-50

-50

p.A

0.1

mA

0.25

0.5

VOL

Vee = Min, IOL= Max

10ZH

Vee= Max, Vo=2.7V

IOZL

Vee= Max, Vo =O.4V

II

Vee = Max, VI =7V

0.1

0.25

IIH

Vee = Max, VI = 2.7V

20

20

p.A

IlL

Vee = Max, VI = O.4V

-0.5

-0.5

mA

los

Vee = Max, Vo = 2.25V

lee

Vee = Max, Outputs High

38

62

38

Vee = Max, Outputs Low

60

97

Vee = Max, Outputs Off

58

95

-30

-112

-112

mA

62

mA

60

97

mA

58

95

mA

-30

Switching Characteristics over reeommended free·air operating temperature
,
Parameter Input Output

tpLH

0

Q

C

Q

tpHL
tpLH

Vee = 4.5V to 5.5V
Rl =500n
R2=500n
C L =50 pF

tpHL
tPZH

OC

DM74AS842

DM54AS842
Conditions

Q

Min

Typ
(Note 1)

Max

Min

1

11

1

Typ
(Note 1)

. Units
Max
8.5

ns

1

10

1

9

ns

2

13

2

12

ns

2

13

2

12

ns

14.5

2

12

ns

2'

tPZL

2

15

2

12.5

ns

tpHZ

1

10

1

8

ns

tpLZ

1

10

1

B

ns

Nole 1: Ali typicals are measured at Vee = SV and TA = 2S'e.

3·220

Function Tables
'AS841

'AS842

Inputs

Inputs

Output

Output

OC

C

0

Q

OC

C

0

Q

L
L
L
H

H
H
L
X

H
L
X
X

H
L

L
L
L
H

H
H
L
X

H
L
X
X

L
H

00
Hi-Z

00
Hi-Z

c

s:

H = High Logic Level
L = Low Logic Level
X = Either High or Low Logic Level
00 = the level of Q before the indicated steady-state input conditions were set up
Hi-Z = TRI-STATE

Ic

s:
:;;;!

l>

en
CD

Logic Diagrams

t

'AS841

iiC----OI
C

a

D---"""",,f--ID

TO OTHER LATCHES
TL/F/6726·3

'AS842

iiC----OI

c
ii

><:>-+--10

010-+-01

Q

.

TO OTHER LATCHES
TLfFJ6726-4

3-221

~

,---------------------------------------------------------------------,

~ ~National

PRELIMINARY

~ ~ Semiconductor

:E
c

DM54AS843/DM74AS843, DM54AS844/DM74AS844
~ 9·Bit Bus Interface I).Type Latches with
::- TRI-STATE® Outputs
Lt)

:E General Description
c
~

~

VI

c::r:
~

:E

e
C')

~

en
~

Lt)

!i

These 9·bit latches feature TRI·STATE outputs designed
specifically for driving highly capacitive or relatively low
impedance loads. They are particularly suitable for imple·
mentlng buffer registers, I/O ports, bidirectional bus
drivers, and working registers.

The output control (OC) does not affect the internal opera·
tlon of the latches. Old data can be retained or new data
entered while the outputs are off.

Features

The 9 latches are transparent O·type latches. While the
enable (C) is high, the 'AS843 Q outputs will follow the data • 9·bit versions of 'AS573/580 with Clear, Preset and
inputs and the 'AS844 Q outputs will complement the data
improved 10H specifications
inputs. When the enable (Cps taken low, the' AS843 Q out· • Provides extra bus driving latches necessary for wider
puts will be latched at the levels that were set up at the 0
address/data paths or busses with parity
inputs, while the 'AS844 Q outputs will be latched at the
. • Buffered control inputs to reduce DC loading
complement of the B input levels.
• Power·up in TRI·STATE
Taking the CLEAR input low will cause the 9 Q outputs to
go low, and taking the PRESET input low will cause the 9 Q
Absolute Maximum Ratings (Note 1)
outputs to go high. When both PR and CLR are taken low,
the outputs will follow the PRESET condition.
Supply Voltage
7V
A buffered output control (OC) input can be used to place
Input Voltage
7V
the 9 outputs in either a low impedance (high or low logic
Storage Temperature Range
- 55·Cto + 150·C
level) or a high impedance state. In the high impedance
Note 1: The "Absolute Maximum Ratings" are those values beyond
state, the outputs neither load nor drive the bus lines
which the safety of the device can not be guaranteed. The device should
significantly. The high impedance TRI·STATEand increased
not be operated at these limits. The parametric values defined in the
drive provide the capability to drive the bus lines in a bus·
"Electrical Characteristics" table are not guaranteed at the absolute
organized system without the need for interface or pull·up
maximum ratings, The "Recommended Operating Conditions" table will
components.
define the conditions for actual device operation.

,

Connection Diagrams
Dual·ln·Line Package

Dual·ln·Line Package

DC

24

Vee

DC

24

Vee

01

23

01

li1

23

01

02

22

02

ii2

22

02

03

21

03

ii3

21

03

04

20

04

D4

20

04

05

19

05

ii5

19

05

06

18

06

D6

18

06

07

17

07

D7

17

07

08

16

08

ii8

16

08

09

10

15

09

D9

10

15

Q9

ClK

'"

14

PH

fiK

11

14

PH

GNO

12

13

GNO

13

12

TOP VIEW

TOP VIEW

TLlF/6727·1

DM54AS843 (J) DM74AS843 (N)

TLlF/6727·2

DM54AS844 (J) DM74AS844 (N)

3·222

Recommended Operating Conditions
Symb~1

DM54AS843

Parameter

Vee

Supply Voltage

VIH

High-Level Input Voltage

DM74ASB43

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

V

2

2

Units

V

Vil

Low-Level Input Voltage'

0.8

0.8

10H

High-Level Output Current

-24

-24

mA

10l

Low-Level Output Current.

32

48

mA

tw

Pulse Width

I

I

V

CLR, PR Low

5

4

ns

CHigh

5

4

ns

tsu

Set-Up Time, Data to Enable (C)

3.5

2.5

ns

tH

Hold Time, Enable (C) to Data

3.5

2.5

ns

TA

Operating Free-Air Temperature

-55

125

70

0

'C

Electrical Characteristics over recommended free-air operating temperature range
DM54AS843
Parameter

Conditions

VI

Vee = Min, 11= -18 mA

VOH

Vee = 4.5V to 5.5V, 10H = - 2 mA

Vee = Min, 10H = - 24 mA

2

10ZH

Vee = Max, Vo= 2.7V
Vee = Max, Vo=O.4V

II

Min

Typ
(Note 1)

-1.2

2.4

Vee = Min, 10l = Max

Max

Vee- 2

Vee= Min, 10H = -15 mA

VOL

10Zl

Min

DM74AS843

Typ
(Note 1)

Max
-1.2

2.4

3.2

V

2
0.25

0.5

V
V

Vee- 2
3.2

Units

V
0.5

V

50

50

I,A

-50

-50

p.A

0.1

0.1

mA

'Vee= Max, VI=7V

0.25

IIH

Vee = Max, VI = 2.7V

20

20

I1A

III

Vee = Max, VI = 0.4V

-0.5

-0.5

mA

los

Vee= Max, Vo= 2.25V

-112

mA

Icc

Vee= Max, Outputs High

38

62

38

62

mA

Vee = Max, Outputs Low

57

92

57

92

mA

Vee = Max, Outputs Off

56

92

56

92

mA

Note 1:

-30

-112

-30

All typical values are at Vee = SV and TA = 2S"e,

,
-

,

I
3-223

Switching Characteristics over recommended free-air operating temperature
DM54AS843
Parameter Input Output

tpLH,

0

a

tpHL
tpLH

C

a

Conditions

Vcc = 4.5V to 5.5V
R1 =5000
R2=5000
CL=50pF

tpHL

Typ
(Note 1)

DM74AS843
Typ
(Note 1)

Max

Units

Max

Min

1

8.5

1

6.5

ns

1

10

1

9

ns

2

13

2

12

ns

2

13

2

12

ns

12

2

10

ns
ns

Min

tpLH

PR

Q

2

tpHL

CLR

Q

2

14

2

13

tPZH

OC

Q

2

13.5

2

10.5

ns

tPZL

2

14.5

2

11.5

ns

tpHZ

1

.1'0

1

8

ns

tpLZ

1

10

1

8

ns

Notal:

All typlcals are measured at VCC=5V and TA=25'C.

~

,

Recommended Operating Conditions
Symbol

Parameter

Vcc

Supply Voltage

VIH

High-Level Input Voltage

VIL

Low-Level Input Voltage

10H

High-Level Output Current

10L

Low-Level Output Current

tw

Pulse Width

tsu

DM74AS~

DM54AS844

Units

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

V

0.8

0.8

V

-15

-15

mA

-24

-"24

mA

32

48

mA

2

2

V

CLR, PR Low

5

4

C High

5

4

ns

3.5

2.5

ns

Set-Up Time, Data to Enable (C)

tH

Hold Time, Enable (C) to Data

TA

Operating Free-Air Temperature

3.5

ns

2.5

-55

125

0

ns
70

'C
i

3-224

Electrical Characteristics over recommended free·air operating temperature range
DM74AS844

DM54AS844
Parameter

Conditions

Min

Typ
(Note 1)

Max

Min

Typ
(Note 1)

-1.2

VI

Vee= Min,ll= -18 mA

VOH

Vee = 4.5V to 5.5V, 10H = - 2 mA

Vee- 2

Vce= Min,loH= -15 mA

2.4

Vee = Min, 10H = - 24 mA

2

Max
-1.2

2.4

3.2

V
V

2
0.25

VOL

Vce= Min, 10L= Max

0.5

V

10ZH

Vee= Max, Vo= 2.7V

50

50

I,A

10ZL

Vee= Max, Vo=O.4V

-50

-50

I,A

'I

Vee= Max, VI= 7V

0.1

0.1

mA

IIH

Vee= Max, VI = 2.7V

20

IlL

Vee= Max, VI =O.4V

-0.5

los

Vee= Max, Vo= 2.25V

lee

Vee= Max, Outputs High

39

64

39

Vee= Max, Outputs Low

58

95

Vee = Max, Outputs Off

58

95

-30

0.5

V
V

Vee- 2
3.2

. Units

-112

0.25

,

20

p.A

-0.5

mA

-112

mA

64

mA

58

95

mA

58

95

mA

-30

Switching Characteristics over recommended free·air operating temperature
DM54AS844
Parameter Input Output

tpLH

D

Q

tpHL
tpLH

C

Q

Conditions

Vee = 4.5V to 5.5V
Rl = 50pn
R2=500n
C L= 50 pF

,

tpHL

Min

Typ
(Note 1)

DM74AS844
Max

Min

Typ
(Note 1)

Max

Units

1

11

1

8.5

ns

1

11

1

10

ns

2

14

2

12.5

ns

2

14

2

13

ns

tpLH

PR

Q

2

12

2

10

ns

tpHL

CLR

Q

2

14.5

2

13.5

ns

tpzH

OC

Q

ns

2

14.5

2

12

tpZL

2

15

2

13.5

ns

tpHZ

1

10

1

8

ns

tpLZ

1

10

1

8

ns

Nole.: All typicals are measured at Vee =5V and TA =25"e.

,
3·225

•

I

Function Tables

t!

::E

'AS844

'AS843

C

3
~
00

LI)

::E
c

i
t!

::E
c

ij
00

~

Inputs

Output

Inputs
OC

CLR

PR

C

L
L
L
L
L
L
H

L
H
L
H
H

H
L
L
H
H

X
X

X
X

H
H
H
H
H
L

X

Output

Q

OC

CLR

PR

C

i5

Q

L
H
L
H
H

H
L
L
H
H

H
L

Hi·Z

X
X

X
X

H
H
H
H
H
L

L
H
H
L
H

X
X

L
L
L
L
L
L
H

X
XI
X

H
L

L
H
H
H
L

X
X

Hi·Z

D
X
X
X

aD

X

aD

H = High Logic Level
L = Low Logic Level
x= Either High or Low Logic Level

00 = the level of Q before the indicated steady-state input co~ditions were set up
Hi·Z = TRI·STATE

LI)

::E

c

Logic Diagrams
. 'AS843

'AS844

>:>-.....++-oICK
ii

TO OTHER LATCHES

TO OTHER LATCHES
TL/F/6727·4

TL/F/6727·3

3·226

PRELIMINARY

~National

~ Semiconductor

DM54AS845/DM74AS845, DM54AS846/DM74AS846
8-Bit Bus Interface D-Type Latches with
TRI-STATE® Outputs
General Description
These 8-bit latches feature TRI-STATE outputs designed
specifically for driving highly capacitive or relatively low
impedance loads. They are particularly suitable for implementing buffer registers, 1/0 ports, bidirectional bus
drivers, and working registers.

The output control (OC) does not affect the internal operation of the latches. Old data can be retained or new data
entered while the outputs are off.

The 8 latches are transparent Ootype latches. While the
enable (C) is high, the' AS845 Q outputs will follow the data
inputs and the' AS846 Q outputs will complement the data
inputs. When the enable (C) is taken low, the 'AS845 Q outputs will be latched at the levels that were set up at the 0
inputs, while the 'AS846 Q outputs will be latched at the
complement of the 0 input levels.

• Similar to 'AS573/580 with Clear, Preset, and multiple
output controls

Taking the CLEAR input low will cause the 8 Q outputs to
go low, and taking the PRESET Input low will cause the 8 Q
outputs to go high. When both PR and CLR are taken low,
the outputs will follow the PRESET condition.

• Power-up in TRI-STATE

A multiuser buffered output control (OC) input can be used
to place the 8 outputs in either a low impedance (high or low
logic level) or a high impedance state. In the high impedance state, the outputs neither load nor drive the bus
lines significantly. The high impedance TRI-STATE and increased drive provide the capability to drive the bus lines in
a bus-organized system without the need for interface or
pull-up components.

Features
• Improved IOH specifications
• Multiple output control inputs allow multiuser control
of the interface
• Buffered control inputs to reduce DC loading

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
Storage Temperature Range

7V
7V
- 55·Cto + 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagrams
Dual·ln-Llne Package

Dual-In-Line Package

OCI

24

Vee

OCI

24

Vee

OC2'

23

OC3

OC2

23

OC3

01

22

01

ii1

22

01

02

21

02

D2

21

02

03

20

03

~

20

03

04

19

04

il4

19

04

05

18

05

li5

18

05

06

17

06

D6

17

06

07

16

07

ii7

16

07

08

15

08

Dii

10

15

08

CLR

14

jijj

CLR

11

14

jijj

GNo

13

GND

12

13

TOP VIEW

DM54AS845 (J)

TOP VIEW

TLlFI6728.'

DM74AS845 (N)

DM54AS846 (J)

TLlF/6728·2

DM74AS846 (N)

This document contains Information on a product under development. NSC reserves the right to change or discontinue this product without notice.

3-227

Recommended Operating Conditions
Symbol
Vee

Supply Voltage

VIH

High-Level Input Voltage

VIL

Low-Level Input Voltage

10H

High-Level Output Current

10L

Low-Level Output Current

tw

Pulse Width

tsu

I

J

DM74AS845

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

2

Units
V

2

V

0.8

0.8

-24

-24

mA

48

mA

32

V

CLR, PR Low

5

4

C High

5

4

ns

3.5

2.5

ns

Set-Up Time, Data to Enable (C)

tH

HoldTime, Enable (e) to Data

TA

Operating Free-Air Temperature

I

DM54AS845

Parameter

3.5

ns

2.5

-55

125

ns
·C

70

0

,

Electrical Characteristics over recommended free-air operating temperature range
DM54AS845
Parameter

Conditions

VI

Vee=Min,ll= -18mA

VOH

Vee = 4.5V to 5.5V, 10H = - 2 mA

lYP

Min

(Note 1)

DM74AS845
Max

lYP .

Min

(Note 1)

-1.2·
Vee- 2

Vee = Min, 10H = - 15 rnA

2.4

Vee = Min, 10H = - 24 mA

2

Max
-1.2

2.4

3.2

V

2
0.25

V
V

. Vee- 2
3.2

Units

V

0.5

0.25

0.5

V
p.A

VOL·

Vee= Min, 10L= Max

10ZH

Vee = Max, Vo=2.7V

50

50

10ZL

Vee = Max, Vo=0.4V

-50

-50

p.A

II

Vee = Max, VI = 7V

0.1

0.1

rnA

IIH

Vee = Max, VI=2.7V

20

20

p.A

IlL

Vee = Max, VI = 0.4V

-.0.5

-0.5

mA

los

Vee = Max, Vo=2.25V

-112

mA

lee

Vee = Max, Outpilts High

-30
35

-112
58

-30
35

56

mA

Vee= Max, Outputs Low

52

85

52

85

mA

Vee = Max, Outputs Off

52

85

52

85

mA

Notal: All typical value. are at vee= 5V and TA=25"e.

,

I

.
3-228

Switching Characteristics over recommended free-air operating temperature
(See Section 1 for Test Waveforms and Output Load)

DM74AS845

DM54AS845
Parameter Input Output
tpLH

0

a

Conditions
Vcc= 4.5V to 5.5V
R1=50011
R2=50011
CL=50pF

tpHL

a

Min

Typ
(Note 1)

Typ
(Note 1)

Max

Units

Max

Min

1

8.5

1

6.5

ns

1

10

1

9

ns

2

13

2

12

ns

2

13

2

12

ns

2

12

2

10

ns

2

14

2

13

ns

2

13.5

2

10.5

ns

tPZL

2

14.5

2

11.5

ns

tpHZ

1

10

1

8

ns

tpLZ

1

10

1

8

ns

tpLH

C

tpHL
tpLH

PR

tpHL

CLR

tpzH

oc

a
a
a

Recommended Operating Conditions
Symbol

Parameter

Vcc

Supply Voltage

VIH

High-Level Input Voltage

VIL

Low-Level Input Voltage

DM54AS846

DM74AS846

Min

Typ

Max

Min

Typ

Max

4.5

5.0

5.5

4.5

5.0

5.5

V
V

2

2

Units

V

0.8

0.8

10H

Hlgh·Level Output Current

-24

-24

mA

10L

Low-Level Output Current

32

48

mA

tw

Pulse Width

,cLR, PR Low

5

4

ns

C High

5

4

ns

tsu

Set-Up Time, Data to Enable (C)

3.5

2.5

ns

tH

Hold Time, Enable (C) to Data

3.5

2.5

ns

TA

Operating Free-Air Temperature

-55

125

Notal: All typicals are measured at VCC=SV and TA=2S·C.

3·229

0

70

·C

Electrical Characteristics over recommended free-air operating temperature range
DM54AS846
Parameter

Conditions

VI

Vee= Min, 11= -18 rnA

VOH

Vee = 4.5V to 5.5V, 10H = - 2mA

Min

Max·

Min

Typ
'(Note 1)

-1.2

2.4

Vee = Min,loH= -24mA

2

Vee= Min, 10L= Max

DM74AS848

Vee- 2

Vee = Min, 10H = - 15 mA

VOL

Typ
(Note 1)

Max
-1.2

2.4

3.2

V

2
0.25

0.5

V
V

Vee- 2
3.2

Units

V
0.25

0.5

V
{LA

10ZH

Vee = Max;Vo=2.7V

50

50

10ZL

Vee = Max, Vo=0.4V

-50

-50

{LA

II

Vee = Max, VI = 7V

0.1

0.1

mA

IIH

Vee = Max, VI = 2.7V

20

IlL

Vee = Max, VI = O.4V

-0.5

los

Vee= Max, Vo= 2.25V

lee

Vee = Max, Outputs High

38

Vee= Max, Outputs Low

53

Vee = Max, Outputs Off

53

-30

-112

-30

,

20

{LA

-0.5

mA

-112

mA

36

mA

53

mA

53

mA

Switching Characteristics

over recommended free·air operating temperature
(See Section 1 for Test Waveforms and Output Load)
DM74AS1i46

DM54AS846
Parameter Input Output

tpLH

0

Q

tpHL

, Conditions

Vee= 4.5V 10 5.5V
R1 =5000
R2=50Q{i
CL=50 pF \

Min

Typ
(Note 1)

Max

Min

Typ
(Note 1)

4.5

4.5

5

5

Max

Units

ns
ns

C

Q

tpLH

PR

Q

5

5

ns

tpHL

CLR

Q

5.5

5.5

ns

tpZH

OC

Q

ns

IpLH

ns
ns

tpHL

6

6

tpZL

6

6

ns

tpHZ

4

4

ns

tpLZ

5

5

ns

Nole 1: Aillypicals are measured al Vee = 5V and TA = 25'e.

3·230

~--------------------------------------------------------~c

s:

Function Tables

(II

'AS845
Inputs
OC' CLR
L
L
L
L
L
L
H

iCi

'AS846
Output

PR

C

0

Q

L
H
L
H
H

H
L
L
H
H

X
X
X

L
H
H
H
L

X
X

X

H
H
H
H
H
L

X

X

H
L

X
X

Inputs
L
L
L
L
L
L
H

00
Hi·Z

-s:
c

Output

PR

C

5

Q

L
H
L
H
H

H
L
L
H
H

X
X
X

L
H
H
L
H

X
X

X
X

H
H
H
H
H
L

OC' CLR

X

H
L

X
X

:;;;!

~

~
c

s:

00

(II

~

Hi·Z

'oc=Qc;. Oc2' 0C3

00

e
c

H = High Logic Level
L:;;. Low Logic Level

s:

X == Either High or Low logic Level
00 = the level of Q before the indicated steady-state input conditions were set up

:;;;!

Hi·Z = TRI·STATE

~

~
en

Logic Diagrams
'AS845

'AS846
OCl
OC2

OCl
OC2
OC3

PH

OC3

PH

S

CLR

~:>---""'--fS

CLR

0

Q

.

TO OTHER LATCHES

TO OTHER LATCHES
TLlF16728·3

3·231

TLlF16728·4

~National

a

Semiconductor

DM54AS873/DM74AS873 Dual4-Bit D-Type
Transparent Latches with TRI-STATE®' Outputs
General Description

Features

These dual 4-bit registers feature totem-pole TRI-STATE
outputs designed specifically fordriving highly-capacitive
or relatively low-impedance loads. The high-impedance
state and increased high-logic-level drive provide these
registers with the capability of being connected directly to
and driving the bus lines in a bus-organized system
without need for interface or pull-up components. They are
particularly attractive for implementing buffer registers,
1/0 ports, bidirectional bus drivers, and working registers.

•
•

The eight latches of the AS873 are transparent D-type
latches meaning that while the enable (G) is high the Q outputs will follow the data (D) inputs. When the enable is taken
low the output will be latched at the level of the data that
was set up.
..

Absolute Maximum Ratings

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and Vee Range.
• Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
• TRI-STATE Buffer-Type Outputs Drive Bus Lines
Directly.
• Space Saving 300 Mil Wide Package.
(Note 1)

7V
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature Range .
DM54AS873
-55°e to 125°C
DM74AS873
DoC to 700 e
Storage Temperature Range
-65°e to 1500 e

A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output conrol does not affect the internal operation of
the latches. That is, the old data can be retained or new data
can be entered even while the outputs are off.

Note 1: The "Absolute Maximum Ratings" are those values beyond'
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram
Dual·ln·Llne Package
'ee
24

UA8LE
IG

"

lUI

"

II

IU2
21

102

IU3
20

13

IU'

'I

\9

18

'"

10'

"

17

'"

'03
16

203

"

ENABLE
2G

"

14

IQ

\I

20.

20C

"

GNO

TLlF/6630·1

54AS873 (J)

74AS873 (J,N)

3-232

Recommended Operating Conditions
DM54AS873
Parameter

Supply Voltage, VCC

DM74AS873

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

High Level Input Voltage, VIH

2

Unit

V
V

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Current, IOH

-12

-15

mA

Low Level Output Current, IOL

32

48

mA

Pulse Width, TW

l

I

Enable High
Clear Low

Data Setup Time, TSU
Data Hold Time, TH

-

5.5
4.5

,3.5

21

21

ns

31

31

ns

The (j) arrow indicates the negative edge of the enable is used for reference.

3-233

4.5

ns

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25°C.

Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.5V, II = -18mA

Min

VOH

High Level Output
Voltage

VCC=4.5V, VIL=VILMAX
10H = MAX
ICH = - 2m A, VCC = 4.5V to 5.5V

VOL

Low Level Output
Voltage

VCC=4.5V, VIH=2V
10L = MAX

II

Max High Input Current

IIH

2.4·

Typ

Max

Unit

-1.2

V

3.3

V

V

VCC -2
0.5

V

VCC=5.5V, VIH=7V

0.1

rnA

High Level Input Current

VCC = 5.5V, VIti = 2.7V

20

/LA

IlL

Low Level Input Current

VCC=5.5V, VIL=0.4V

-0.5

rnA

10

Output Drive Current

VCC = 5.5V, Vo = 2.25V

-112

rnA

10ZH

Off-State Output
Current, High Level
Voltage Applied

VCC = 5.5V, VIH = 2V
Vo = 2.7V

50

/LA

10ZL

Off-State Output
Current, Low Level
Voltage Applied

VCC=5.5V, VIH=2V
Vo = 0.4V

--:50

ICC

Supply Current

VCC = 5.5V
Outputs Open

0.35

-30

,

/LA

Outputs High

68

110

rnA

. Outputs.Low

67

109

rnA

80

129

rnA

Outputs Disabled

·3·234

SWitching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vcc = 5V, TA = 25"C.
DM54AS873
Parameter

From

TpLH

Data

To

Conditions

Min

Any 0

TpHL
TpLH

Enable

Any 0

TpHL
TpZH
TpZL

Output

TpHZ

Control

VCC = 4.5V to 5.5V
RL = 500 0
CL = 50 pF

Any 0

TpLZ
Clear

TpHL
Not~

AnyO

Typ

DM74AS873
Max

Unit

Max

Min

3

9

3

6

ns

3

7

3

6

ns

.Typ

6

14

6

11.5

ns

4

9

4

7.5

ns

2

8

2

6.5

ns

4

11

4

9.5

ns

2

8

2

6.5

ns

2

8.5

2

7.5

ns

3

8.5

3

7.5

ns

1: See Section 1 for test waveforms and output load.

Logic Diagram

Function nlble

-c---.

1 ENABLE ....:'"",

1 CLEAR

101

-''-<111:><>...,
3

4
21102

103

5

20 103

Ilt4

Ii

19

104

,,,--,-'- - - - - I
IS 201

202

8
11

2'02

"'....!..'--+-+--i
16 203

,,,....:"'--_-+-+--1
,-m-,,"":'::,,'-ct;>o--t-"<1I

15

Z04

4':>-_+-___....1

~~~I~~Z ..!,!,.,

2 ENABLE "",14'---'1>0_--'

0

EN

OC

X
L
H
H
H

X
X
H
L
X

X
X
H
H
L

H
L
L
L
L

L = Low State. H = H'gh State, X
Z = High Impedance State
QO = Previous Condition of Q

22101

102

CLR

TL/F/6331·2

3-235

=

Don't Care

Q

Z
L
H
L
00

~ a~National
Semiconductor
~

:E

~ DM54AS874/DM74AS874
.- Dual 4-Bit D-Type Edge'-Triggered Flip-Flops

~

:E

c

General Description

Features

These dual 4-blt registers feature totem-pole TRI-STAIE@
outputs designed specifically for driving highly-capacitive
or relatively low-impedance loads. The high-impedance
third state and increased high-logic-level drive provide
these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system
without need for interface or pull-up components. They are
particularly attractive for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working registers.

•
•

The eight flip-flops of the ASB74 are edge-triggered D-type
flip-flops. On the positive transition of the clock, the out- .
puts will be set to the logic states that were set up at the D
inputs.

Absolute Maximum Ratings

a

A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output cOritrol does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.(

•
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and Vee Range.
Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
TRI-STATE Buffer-Type Outputs Drive Bus Lines
Directly..
Space Saving 300 Mil Wide Package.
(Note 1)

Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range'
-55.oe to 125°C
DM54ASB74
ooe to 70°C
DM74ASB74
Storage Temperature Range
-65°C to 150°C
Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guarant,eed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the condiJlons for actual device operation.

Connection Diagram
Dual-In-Line Package
leU(

101

104

10'

'tt.

10'

14

10
101

101

103

'"

104

10'

,,.

11

2ii:

"..0
TLlF/6331-1

54AS874 (J)

74AS874 (J,N)

3-236

Recommended Operating Conditions
DM74AS874

DM54AS874
Parameter

Supply Voltage, VCC

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

High level Input Voltage, VIH

2

Unit

V

V

low level Input Voltage, Vil

0.8

0.8

V

High level Output Current, IOH

-12

-15

mA

low level Output Current, IOl

32

48

mA

125

MHz

0

Clock frequency, fCLOCK
Width of Clock Pulse, TW

Width of Clear Pulse, TW
Setup Time, TSU

100

0

High

4

.3

ns

low

5

4

ns

low

3

2

ns

2.51

21

ns

51

41

1I

1I

Data.
Clear Inactive

Data Hold Time, TH
The (I) arrow mdlcates the positive edge of the Clock IS used for reference.

3-237

ns

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vce = 5V, TA = 25·C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC=4.5V, 11= -18mA

VOH

High Level Output
Voltage

VCC=4.5V, VIL'; VILMAX
10H = MAX

Min

10H = - 2mA, VCC = 4.5V to 5.5V
VOL

Low Level Output
Voltage

VCC=4.5V, VIH =2V
10L = MAX

II

Max High Input Current

IIH

2.4

Typ

Max

Unit

-1.2

V

3.3

V

V

VCC -2
0.35

0.5

V

VCC=5.5V, VIH=7V

0.1

mA

High Level Input Current

VCC=5.5V, VIH =2.7V

20

p.A

IlL

Low Level Input Current

VCC=5.5V, VIL=0.4V

-0.5

mA

10

Output Drive Current

VCC=5.5V, VO=2.25V

-112

mA

10ZH

Off·State Output
Current, High Level
Voltage Applied

VCC=5.5V, VIH=2V
Vo = 2.7V

50

p.A

10ZL

Off·State Output
Current, Low Level
Voltage Applied

VCC=5.5V, VIH=2V
Vo = O.4V

-50

p.A

ICC

Supply Current

VCC = 5.5V
Outputs Open

82

133

mA

92

149

mA

100-

160

mA

-30

Outputs High
Outputs Low
Outputs Disabled

3·238

-

-------------------------------------------------------------------,0

s::

Switching Characteristics over recommended operating free air temperature range (Note 1).

U'I

~

All typical values are measured at Vcc = 5V, TA = 25°C.
DM54AS874
Parameter

From

To

Conditions

Typ

Min

Dr.,74AS874
Max

Min

Typ

Max

Unit

FMAX

100

TpLH

3

11.5

3

8.5

ns

4

12.5

4

10.5

ns

Clock

Any

a

TpHL
Output
Control

TpZH
TpZL

Any

a

VCC = 4.SV to S.5V
RL = 500 Q
CL = 50 pF

MHz

125

2

8

2

7

ns

3

11.5

3

10.5

ns

2

7

2

6

ns

TpLZ

2

8.5

2

7.5

ns

4

11

4

9.5

ns

Clear

Any

a

Note 1: See Section 1 tor test waveforms and output load.

Function Table

Logic Diagram
-D----.

I CLIICK ...:'::...'

~g~:~~~...!...'-c/'::>---I----,

1D1....!.--+-+---I
I-I-cl>'::..' IQI
102

L ! Z 00

-':!.--++--i
I-HI>";;..I IQ'

lD~

S

I-I-cl>'::..' IQ3
104

6

1-~I>".:....9 104

'01 -!....-------i
18 201

2O,...!..--HH
'1-1-c1>-';;..7 202

20' ...!..---I--I--i
16 203

'" . .:'::.. '---I-+--i
zCIii .,21!.'-c/'::>o-+---I-.q

15 2Q4

2 CLOCI(.,2'~·

-D.....- - l
TLlFJ6331·2

3-239

-s::o
~

~

~

co

TpHZ

TpHL

CO
.......

CLR

D

ClK

OC

Q

X
L
H
H
H

X
X
H
L
X

X
X
t
t
L

H
L
L
L
L

Z
L
H
l

Low State, H - High State, X - Don't Care
Positive Edge Transition
High Impedance State
- Previous Condition of 0

ao

.......
~

~National

D Semiconductor
DM54AS876/DM74AS876
Dual 4-Bit D-Type Edge-Triggered Flip-Flops
with TRI·STATE® Outputs
General Description

Features

These inverting dual 4-bit registers feature totem-pole
TRI-STATE outputs designed specifically for driving highlycapacitive or relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive
provide these registers with the capability of being connected directly to and driving the bus Ijnes in a bus-organized
system without need for interface or pull-up components.
They are particularly attractive for implementing buffer registers, 1/0 ports, bidirectional bus drivers, and working registers.

•
•

The eight flip-flops of the AS876 are edge-triggered inverting D-type flip-flops. On the positive transition of the clock,
the Q outputs will be set to ihe complement of the logic
states that were set up at the D inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output control does not affecfthe internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and Vee Range.
Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
TRI-STATE Buffer-Type Outputs Drive Bus Lines
Directly.

•
•
•

Space Saving 300 Mil Wide Package.

Absolute Maximum Ratings

(Note 1)
7V
7V

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS876
DM74AS876
Storage Temperature Range

-55°C to 125°C
ooe to 70°C
-65°C to 150°C

Nole I: The "Absolute Maximum Ratings" are those values beyond
which the salety 01 the device can not be guaranleed. The device should
not be operated at Ihese limits. The parametric values defined In Ihe
"Electrical Characteristics" table are nol guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram
Dual-In-Llne Package
101

"

101

10'

"

102

103
20

103

10'

'01

19

18

1
201

10.

'0'

17

'"

'03
16

203

ZCLK

zPiiE

15

14

13

10

11

",NO

'0'

".

,nc

TLlF/6332-1

. 54AS876 (J)

74AS876 (J,N)

3-240

Recommended Operating Conditions
DM54AS876
Parameter

Supply Voltage, VCC

DM74AS876

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

High Level Input Voltage, VIH

2

Unit

V
V

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Current, IOH

-12

-15

mA

Low Level Output Current, IOL

32

48

mA

125

MHz

0

Clock frequency, fCLOCK

100

0

High

4

3

Low

5

4

Width of Preset Pulse, TW

Low

3

2

ns

Data Setup Time, TSU

Data

2.51

21

ns

5

4

11

11

Width of Clock Pulse, TW

C!ear Inactive
Data Hold Time, TH
The (t) arrow indicates the positive edge of the Clock IS used for reference.

3·241

ns

ns

U)r-------~-----------------------------------------------------------------.....
Switching Characteristics over recommended operating free air temperature range (Note 1).

.~

~

:!:

All typical values are measured at Vee = 5V, TA = 25 D C.
Symbol

Para",eter

Conditions

Min

'0

VIK

Input Clamp Voltage

VCC=4.5V,II= -18mA

~

VOH

High Level Output
Voltage

VCC = 4.5V, VIL = VIL MAX
10H = MAX

o

VOL

Low Level Output
Voltage

VCC=4.5V, VIH=2V
10L = MAX

II

Max High Input Current

IIH

fe

:!:

2.4

10H = - 2m A, VCC = 4.5V to 5.5V.

Typ

Max

Unit

-1.2

V

3.3

V

V

VCC -2
0.5

V

VCC=5.5V, VIH=7V

0.1

mA

High Level Input Current

VCC = 5.5V, VIH = 2.7V

20

I'A

IlL

Low LevellnPlJt Current

VCC=5.5V, VIL=0.4V

-0.5

mA

10

Output Drive Current

VCC=5.5V, VO=2.25V

-112

mA

10ZH

Off-State Output
Current, High Level
Voltage Applied

VCC=5.5V, VIH=2V
Vo = 2.7V

50

I'A

10ZL

Off-State Output
Current, Low Level
Voltage Applied

VCC=5.5V, VIH =2V
Vo = 0.4V

-50

I'A

ICC

Supply Current

Vec = 5.5V
Outputs Open

mA

0.35

I

-30

Outputs High

88

142

Outputs Low

94

150

Outputs Disabled

100

160

3·242

Switching Characteristics

over recommended operating free air temperature range (Note 1).

All typical values are measured at Vcc =5V, TA =25'C.

DM74AS876

DM54AS876
Parameter

From

To

Conditions

Max

Typ

Min

TpLH

Clock

AnyQ

TpHL
VCC = 4.5V to 5.5V
RL = 500 fl
CL = 50 pF

Typ

Max

125

100

FMAX

Min

Unit
MHz

3

11.5

3

8.5

ns

4

12.5

4

10.5

ns

2

8

2

7

ns

3

11.5

3

10.5

ns

TpHZ

2

7

2

6

ns

TpLZ

2

7

2

6

ns

4

11

4

9.5

ns

Output
Control

TpZH
TpZL

Preset

TpHL

AnyQ

AnyQ

Note 1: See Section 1 for test waveforms and output load.

Logic Diagram
1 CLOCK

Function Table

--,1,--'-1).0----,

Je' --'---+-+--i
L

0

CLK

OC

Q

X
L
H
H
H

X
X
H
L
X

X
X

H
L
L
L
L

Z
L
L
H
00

Low State. H

~

High State. X

r = Positive Edge Transition
Z = High Impedance State
00 = Previous Condition of Q

Je1-"..'--+-+--1

Je' --"---+-+--i

Je4 --,,-'--+-+--i

101-'------i

101 -"..'-'--+-+--i

203

~

PRE

9

16 2Ql

10' --,',,-0---t--t--;

-Doo----'

2 CLOCK -",-'

TlIF16332·2

3·243

1
1
L
~

Don't Care

~

~ ~ National

~
::a:

a

.
Semiconductor

~ DM54AS878/DM74AS878

.
~ Dual 4-Bit D-Type Edge-Triggered Flip-Flops
~ with Synchronous Clear

::a:
c

General Description

Features

These dual 4-bit registers feature totem-pole TRI-STATE@
outputs designed specifically for driving highly-capacitive
or relatively low-impedance loads. The high-impedance
third state and increased high-logic-level drive provide
these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system
without need for interface or pull-up components. They are
particularly attractive for implementing buffer registers, 1/0
ports, bidirectional bus drivers, and working registers.

•
•

The eight flip-flops of the AS878 are edge-triggered D-type
flip-flops. On the positive transition of the clock, the outputs will be set to the logic states that were set up at the 0
inputs.

a

A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
, the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and Vee Range.
Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.

•

• TRI-STATE Buffer-Type Outputs Drive Bus Lines
Directly.
•

Space Saving 300 Mil Wide Package.

•

Synchronous .clear.

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS878
DM74AS878
Storage Temperature Range

(Note 1)
7V
7V

-55°C to 125°e
DoC to 70 0
-65°C to 150 0 e

e

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The dBvlce should
not ba operated at these limits. The parametric values defined In the
"Electrical Charactarlstlcs" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram
Dual-In-Line Package
101

"

III'
21

103
10

201

10'

'"

"

2112
17

203

"

204

"

2CLK
14

",.
TL/F/6333-1

54AS878 (J)

74AS878 (J,N)

3-244

c

s:

Recommended Operating Conditions

(J1

DM54AS878
Parameter

Supply Voltage, VCC

DM74AS878

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Unit

V

~

en
CO

-s:
~
C

2

2

High Level Input Voltage, VIH

V

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Current, IOH

-12

-15

mA

~
»
en
CO

.....

CO

32

Low Level Output Current, IOL

0

Clock frequency, fCLOCK
Width of Clock Pulse, TW

Data Setup Time, TSU

Data Hold Time, TH

100

0

High

5

4

Low

3

2

Data

31

21

CLR

6.51

5.51

Data

31

21

CCR

01

01

The,(t) arrow indicates the positive edge of the Clock is used for reference.

3-245

48

mA

125

MHz
ns

ns

ns

~
co . Electrical Characteristics over recommended operating free air temperature range.

!:!3
......

All typical values are measured at Vee = SV, TA = 2S"C.

t:!:

Symbol

Parameter

Conditions

c

VIK

Input Clamp Voltage

VCC=4.SV, 11= -18mA

~

VOH

High Level Output
Voltage

VCC=4.SV, VIL=VILMAX
10H = MAX

:\!E

~

IOH = - 2mA, VCC = 4.SV to S.SV

U)

:\!E

c

Min

VOL

Low Level Output
Voltage

VCC=4.SV, VIH=;2V
IOL = MAX

II

Max High Input Current

IIH

204

Typ

Max

Unit

-1.2

V
V

3.3

V

VCC -2
0.3S

0.5

V

VCC=S.SV, VIH=7V

0.1

mA

High Level Input Current

VCC = S.5V, VIH = 2.7V

20

",A

IlL

Low Level Input Current

VCC=5.5V, VIL=0.4V

-0.5

mA

10

Output Drive Current

VCC = 5.5V, Vo = 2.25V

-112

mA

10ZH

Off-State Output
Current, High Level
Voltage Applied

VCC=5.5V, VIH=2V
Vo = 2.7V

50

",A

10ZL

Off-State Output
Current, Low Level
Voltage Applied

VCC=5.5V, VIH=2V
Vo = OAV

-50

",A

ICC

Supply Current

VCC = 5.5V
Outputs Open

mA

-30

Outputs High

82

132

Outputs Low

96

155

Outputs Disabled

100

160

3-246

-------------------------------------------------------------------,0
Switching' Characteristics over recommended operating free air temperature range (Note 1).

3:

All typical values are measured at Vcc = 5V, T A = 25°C.

~

DM54AS878
Parameter

From

To

Conditions

Min

Typ

en

DM74AS878
Max

Max

Typ

Min

Unit

~

(X)

......

(X)

125

MHz

FMAX

100

TpLH

3

11.5

3

8.5

ns

4

12.5

4

10.5

ns

2

8

2

7

ns

3

11.5

3

10.5

ns

TpHZ

2

7

2

6

ns

TpLZ

2

7

2

6

ns

Clock

Any

a

TPHL
Output
Control

TPZH
TpZL

Any

Vce = 4.5V to 5.5V
RL = 500 Q
CL = 50 pF

a

Nole 1: See Section 1 for test waveforms and output load.

Function Table

Logic Diagram
I CLOCK -,13'-i:>O_-,

~~~:;~lT . . .:. .'-<>1:>--+-----,
1eLR

101

CLR

0

CLK

OC

a

x

x

L
H
H
H

X
H
L
X

X
1
1
1
L

H
L
L
L
L

Z
L
H
L
00

L ~ Low State. H ~ High State. X
r = Positive Edge Transition
Z ~ High Impedance State
00 = PrevIous Condition of Q

I-f-I>-"=--' 10'

I-f-I>-""=-- 10'

'"
"

'01

'"
17 ZQ2

103
16

'"

I~ 2Q4

HLR

iTuTPUT
COHTROl

2 CLOCK

)
'03

"
"
TLlF/6333·2

3-247

~

Don't Care

o

3:

~......

(X)
(X)

~

~ ~ National

~

:!:

a

.
Semiconductor

Q

DM54AS879/DM74AS879 Dual4-Bit D-Type
~ Edge-Triggered Flip-Flops with
TRI-STATE® Outputs and Synchronous Clear

~

II)

:!:
Q

Gene~al

Description

Features

These inverting dual 4-bit registers feature totem-pole
TRI-STATE"'outputs designed specifically for driving highlycapacitive or relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive
provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized
system without need for interface or pull-Up components.
They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the AS879 are edge-triggered inverting D-type flip-flops. On the positive transition of the clock,
the Q outputs will be set to the complement of the logic
states that were set up at the D inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.

•
•
•
•
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and Vee Range.
Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
TRI-STATE Buffer-Type Outputs Drive Bus Lines Directly.
Space Saving 300 Mil Wide Package.
Synchronous Preset.

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS879
DM74AS879
Storage Temper~ture Range

(Note 1)
7V
7V

-55°C to 125°C
DoC to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values bayond
which the safety of the device can not ba guaranteed. The device should
not be operated at these limits. The ~arametrlc values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the condltlo.ns for actual device operation.

Connection Diagram
Duat·tn·Llne Package

TLlF/6334-1

54ASB79 (J)

74ASB79 (J,N)

3-248

Recommended Operating Conditions .
DM54AS879

. Parameter
Supply Voltage, VCC

DM74AS879

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

High Level Input Voltage, V,H

2

Unit

V
V

Low Level Input Voltage, V,L

0.8

0.8

V

,High Level Output Current, IOH

-12

-15

mA

Low Level Output Current, IOL

32

48

mA

125

MHz

0

CloC?k frequency, fCLOCK
Width of Clock Pulse, TW

Data Setup Time, TSU

Data Hold Time, TH

100

0

High

5

4

Low

3

2

Data

31

21

CLR

6.51

5.51

·Data

31

21

CLR

01

01

The (I) arrow indicates the positive edge at the Clock is used for reference.

3·249

ns
ns
ns

ns

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vcc =5V, TA= 25°C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC = 4.5V, II = - 18mA

VOH

High Level Output
Voltage

VCC = 4.5V, VIL = VIL MAX
10H = MAX

Min

10H = - 2m A, VCC = 4.5V to 5.5V
VOL

Low Level Output
Voltage

VCC=4.5V, VIH =2V
10H = MAX

II

Max High Input Current

IIH

2.4

Typ

Max

Unit

-1.2

V

3.3

V

VCC -2
0.35

0.5

V

VCC = 5.5V, VIH = 7V

0.1

mA

High Level Input Current

VCC=5.5V, VIH=2.7V

20

/loA

IlL

Low Level Input Current

VCC=5.5V, VII.=0.4V

-0.5

mA

10

Output Drive Current

VCC =5.5V, VO=2.25V

-112

mA

10ZH

Off-State Output
Current, High Level
Voltage Applied

VCC = 5.5V, VIH = 2V
Vo = 2.7V

50

/loA

10ZL

Off-State Output
Current, Low Level
Voltage Applied

VCC ='5.5V, VIH = 2V
Vo = O.4V

-50

~A

ICC

Supply Current

VCC = 5.5V
Outputs Open

mA

-30

Outputs High

88

142

Outputs Low

94

150

Outputs Disabled

100

160

3-250

c
is:

SWitching Characteristics over recommended operating free air temperature range (Note 1).

U'I

All typical values are measured at Vcc =5V, TA=25°C.
DM74AS879

DM54AS879
Parameter

From

Conditions

To

Typ

Min

Max

Min

Typ

Max

FMAX

100
3

11.5

3

8.5

ns

4

12.5

4

10.5

ns

Clock

AnyQ

Output
Control

TpZH
TpZL

VCC = 4.5V to 5.5V
RL = 500 f!
CL = 50 pF

AnyQ

TpHZ
TpLZ

MHz

2

8

2

7

ns

3

11.5

3

10.5

ns

2

7

2

6

ns

2

7

2

6

ns

Note 1: See Section 1 for test waveforms and output load.

. Function Table

Logic Diagram'
I CLOCK

":;"'-1>0--.,

~~~J;~~ ...;2~>-_+-_ _ _..,

00
fij2

20

i03

19

fij4

0

CLK

oc

Q

X
L
H
H
H

X
X
H
L
X

X

H
L

Z
H
L
H
00

L

L '" Low State, H ~ High State, X ~ Don't Care
I = POSitive Edge Transition
Z ~ High Impedance State

1-1-o1>2~2 iOi

21

CLR

1
1
1

182iji

f-I-o[>-'''-' 1ij;

162ijj

15 io~

2 CLOCK ...:':...4-Do<>----'

TLlF16334·2

3-251

= Previous Condition of Q

L

L
L

~

CO

.....

-

CD

TpLH
TpHL

125

Unit

c
is:

~

en
CO
.....

CD

I D~National
S'emiconductor
~
~

c
o

~

DM54AS880/DM74AS880
Dual 4-Bit D-Type Transparent Latches
with TRI-STATE® Outputs

~

c

General Description

Features

These dual 4-bit inverting registers feature totem-pole
TRI-STATE"'outputs designed specifically for driving highlycapaCitive or relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive
provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized
system without need for interface or pull-up components.
They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and Vee Range.

•

Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.

The eight inverting latches of the AS880 are transparent Dtype latches meaning that while the enable (G) is high the Q
outputs will follow the complement of the data (D) inpuis.
When the enable is taken low the output will be latched at
the complement of the level of the data that was set up.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
the latches. That is, the old data can be retained or new data
can be entered even while the outputs are off.

• TRI-STATE Buffer-Type Outputs Drive Bus Lines
Directly.
•

Space Saving 300 Mil Wide Package.

Absolute Maximum Ratings (~ote 1)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS880
DM74AS880
Storage Temperature Range

7V
7V
-55°C to 125°C
ooe to 70°C
-65°C to 150°C

Nole 1: The "Absolute Maximum Rallngs" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum rallngs. The "Recommended Operating Condillons"table will
define the conditions for actual device operation.

Connectior'! Diagram.
Dual·ln·Llne Package
,g,

102

17

"

OJ,

"

2

iii:

lQ'
15

10
101

102

'"

104

201

202

2"

2D4

.",;;;

12

'ND
TLIF16335-1

54ASBBO (J)

74ASBBO (J,N)

3·252

c

s:

Recommended Operating Conditions

(11

OM54ASBBO
Parameter

Supply Voltage, VCC

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

High Level Input Voltage, VIH

~

OM74ASBBO

Min

2

Unit

CO

V

-s:
l=-

V

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Current, IOH

-12

-15

mA

Low Level Output Current, IOL

32

48

mA

I

Enable

3.5

2.5

ns

Preset Low

4.5

3.5

ns

Data Setup Time, TSU

2!

2!

ns

Data Hold Tim,e, TH

1!

1!

ns

Pulse Width, TW

I

The (I) arrow Indicates the positive edge of the Clock IS used for reference.

3-253

en
CO

o

C

~

en
CO
CO

o

o

CO

~
-

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25°C.

:2

c
o

CO

~

Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V, II = - 18mA

VOH

High Level Output
Voltage

VCC = 4.5V
VIL = VIL MAX
10H = MAX

Min

Typ

Max

Unit

-1.2

V

,
204

3.3

V

Lt')

10H = - 2mA, Vee = 4.5V to 5.5V

:2

VCC -2

Q

0.5

V

Vce=5.5V, VIH=7V

0.1

mA

High Level Input Current

Vec=5.5V, VIH=2.7V

20

fJ.A

IlL

Low Level Input Current

VCC=5.5V, VIL=0.4V

-0.5

mA

10

Output Drive Current

Vec=5.5V, VO=2.25V

-112

mA

10ZH

Off-State Output
Current, High Level
Voltage Applied

VCC=5.5V, VIH=2V
Vo = 2.7V

50

fJ.A

10ZL

Off-State Output
Current, Low Level
Voltage Applied

Vec=5.5V, VIH=2V
Vo = OAV

-50

fJ.A

ICC

Supply Current

VCC = 5.5V
Outputs Open

mA

VOL

Low Level Output
Voltage

VCC = 4.5V
VIH = 2V
10L = MAX

II

Max High Input Current

IIH

0.35

-30

Outputs High

73

118

Outputs Low

76

122

Outputs Disabled

86

137

3-254

--------------------------------------------------------------------,0

3:

SWitching Characteristics over recommended operating free air temperature range (Note 1).

en

~

All typical values are measured at Vcc = 5V, TA = 25°C.
DM54AS880
Parameter

From

TpLH

Data

To

Conditions

Min

AnyO

Enable

VCC = 4.5V to 5.5V
RL = 500!1
CL = 50 pF

AnyO

TpHL
TPZH
TpZL
TpHZ

Output
Control

AnyQ

Preset

AnyQ·

TpLZ
TpHL

Typ

Unit

Max

Min

11

4

9.5

ns
ns

4

TpHL
TpLH

Typ

DM74AS880
Max

4

9

4

8.5

6

14

6

11.5

ns

4

10

4

8

ns

2

8

2

7.5

ns

4

11

4

10

ns

2

8

2

6.5

ns

2

9

2

8

ns

4

11.5

4

10

ns

Note 1: See Section 1 for test waveforms and output load.

Logic Diagram

Function Table

'ENABLE...!'~3-D---,

~8~f:8[-''-cI>--+---__,

1PREsn-''-<>IC><>...,
101

102

D

EN

OC

Q

X
L
H
H

X
X
H
L

X
X
H
H
L

H
L
L
L
L

Z
L
L
H
00

H

3

x

L - Low State, H - High State. X - Don't Care
~ - High Impedance State _
00 - Previous Condition of 0

4

ID3....:'~--+-+---I
20 1'03

ID •....:''----!--!----I

"'-'------1
18 201

,,,....:''----!--!----I

2D3

PRE

9
16 iij3

2D4 10

i~~f~~(-"w..'-<1:>--+------'
2 ENABLE"":';:,,'--[)oo----'

TLIF/6335-2

3-255

CD

~

o

3:
~
l>

rn
CD
CD

o

_National
Semiconductor
DM54AS881 B/DM74AS881 B 4-Bit Arithmetic LQgic
Unit/Function Generator
General Description.
The DM54/DM~4AS8818 are arithmetic logic unlts·(ALU)1
function generators that have a complexity of 77 equlvalent gates, respectively, on a monolithic chip. These circults perform 16 binary arithmetic operations on two 4-blt
words, as shown In Tables I and II. These operations are
selected by the four function-select lines (SO, 51, 52, 53)
and Include addition, subtraction, decrement, and
straight transfer. When performing arithmetic manipulations, the internal carries must be enabled by applying a
low level voltage to the mode control input (M). A full carry
look-ahead scheme is made available in these devices for
fast, simultaneous carry generation by means of two cascade outputs (pins 15 and 17) for the four bits In the
package. When used in conjunction with the DM54AS882
or DM74AS882 full carry look-ahead circuits, high speed
arithmetic operations can be performed. The typical addition times sly>wn previously illustrate the little additional
time required for addition of longer words when full carry
look-ahead is employed. The method of cascading 'AS882
circuits with these ALUs to provide multi-level full carry
look-ahead is illustrated under "signal designations".
If high speed Is not of Importance, a ripple-carry input (C n)
and a ripple-carry output (C n +4) are available. However,
the ripple-carry delay has also been minimized so that
arithmetic manipulations for small word lengths can be
performed withouj external circuitry.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full
temperaiure and Vee range
• Advanced oxilla-Isolated, ion-implanted Schottky TIL
process

Connection Diagram

• Functionally and pin-for-pin compatible with Schottky,
low power Schottky, and advanced low power Schottky
TIL counterpart
• Improved AC performance over Schottky, low power
. Schottky, and advanced low power Schottky
counterpart
• Arithmetic operating modes:
Addition
Subtraction
Shift operand A one position
Magnitude comparison
Plus twelve other arithmetic operations
• Logic function modes:
Exclusive-OR
Comparator
AND, NAND, OR, NOR
Plus ten other logic operations
• Full look-ahead for high speed operations on long
.words

Absolute Maximum Ratings

(Note 1)

Supply Voltage
7V
Input Voltage
7V
Operating Free-Air Temperature Range
DM54AS
-55·Cto + 125·C
. DM74AS
O·Cto 70·C
Storage Temperature Range
-65·Cto + 150·C
Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Pin Designations

Dual-In-Line Package

T'
24

INPUTS
A1

81
23

22

OUTPUTS

A3

82

A2

21

20

83

19

Ii

18

G Cn+4
17

,.

P A=B
15

14

-c

1

\RO

F3'
13

0-

2
AD

3

S3

•
.2

5

"

•
SO

7

C,

INPUTS

8

9

M ... FO

10
F1

DeSignation

Pin Number

Function.

A3, A2, A1, AO
83,82, 81, 80
53,52,51, SO

19,21,23,2
18,20,22,1
3,4,5,6

Cn
M
F3,F2,F1,FO
A=8
P

7
8
13,11,10,9
14
15

. Cn + 4
G

16
17

Vee
GND

24
12

Word A Inputs
Word 8 Inputs
Function-Select
Inputs
Inv. Carry Input
Mode Control Input
Function Outputs
Comparator Output
Carry Propagate
Output
Inv. Carry Output
Carry Generate
Output
Supply Voltage
Ground

11 J.:2
F2" GND

OUTPUTS
TOP VIEW
TL/F/6336·'

54AS881 B (J)

74AS881B (J; N)

-

3-256

Recommended Operating Conditions
DM74AS881B

DM54AS881B
Symbol

Parameter
Supply Voltage

Vee

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

High Level Input Voltage

VOH

High Level Output Voltage
A = B Output Only

10H

High Level Output Current
All O'utputs Except A = Band G

Low Level Output Current
All Outputs Except G

G
Operating Free-Air Temperature

TA

V

-55

V

5.5

5.5

G
10L

V

2

2

VIH

Units

-2

-2

-3

-3

20

20

48

48

125

mA

mA

·c

70

0

Electrical Characteristics over recommended operating free-air temperature range unless otherwise noted
DM54AS881A
Symbol

Parameter

VIK

Conditions

Min

Typ
(Note 1)

DM74AS881A

Max

Min

Typ
(Note 1)

-1.2

-1.2

Vce = 4.5V, II = -18 mA

Max

Units

V

VOH

Any Output
Except A=B

Vee = 4.5V t6 5.5V, 10H = - 2 mA

G

Vee = 4.5V, IOH = - 3 mA

IOH

A=B

Vee = 4.5V, VOH=5.5V

0.1

mA

VOL

Any Output
Except G

Vee =4.5V,l oL =20 mA

0.3

0.5

0.3

0.5

V

G

Vee = 4.5V, IOL = 48 mA

0.4

0.5

0.4

0.5

M Input

Vee = 5.5V, VI =7V

II

IIH

2.4

3.4

3.4

0.1

0.1

Any A or B Input

0.3

0.3

Any S Input

0.4

0.4

Carry Input

0.6

0.6

M Input

Vee = 5.5V, VI=2.7V

20

20

60

60

Any S Input

80

80

Carry Input

120

120

M Input

Vee = 5.5V, VI =O.4V

,

Any A or B Input

-0.5

-0.5

-1.5

-1.5

Any S Input

-2

-2

Carry Input

-3

-3

10 (Note 2) All Outputs
Except A=B
andG

-30

Vee = 5.5V, Vo=2.25V

G
Icc

2.4
0.1

Any A or B Input

IlL

V

Vee- 2

Vce- 2

-112

-165
Vee =5.5V

70

-30

p.A

mA

-112

mA

104

mA

-165
104

70

Note 1: All typical values are at Vee=5V, TA=25·C.
Note 2: The output conditions have been chosen to produce a curr~nt that closely approximates one half of the true short circuit current, lOS-

3-257

mA

,...

a:I

!
-,...
j:!:
:::E
c

Switching Characteristics
Symbol

Parameter

tpLH

Propagation Delay Time,
Low-to-Hi.Qh Level Output

tpHL

Pr.opagation Delay Time,
Hlgh-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tPHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
Hlgh-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
Hlgh-io-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-Hlgh Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
. Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Out.put

tpLH

Propagation Delay Time,
Low-to-Hlgh Level Output

tpHL

Propagation Delay Time,
Hlgh-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

From
(Input)

To
(Output)

CL=50 pF (15 pF for A= B)
RL = 5000 (2800 for A = B)
Conditions

Min

a:I

I
:::E

c

DM54AS881B

Cn

Cn +.4

2
Any A
or B

Any A
or B

Cn

Any A
or B

Any A
or B

Any A
or B

Any A
or B

AlorB.j

AjorB i

AjorBI

Any A
orB

Cn + 4

Cn + 4

Any F

G

G

P

P

Fj

FI

Fj

A=B

Typ

2

,

DM74AS881B

Max

Min

11

2

Typ

9

11

2

9

Max

M=OV, SO;"
S3=4.5V
S1 =S2=OV
(SUM Mode)

2

14

2

12

2

14

2

12

M=OV,SO=
S3=OV
S1 =S2=4.5V
(DIFF Mode)

2

20

2

16

2

20

2

16

M=OV
(SUM or
DIFF Mode)

3

11

3

9

3

11

3

9

M=OV,SO=
S3=4.5V
S1 =S2=OV
(SUM Mode)

2

9

2

7

2

9

2

7

M=OV,SO=
S3=OV
S1 =S2=4.5V
(DIFF Mode)

2

12

2

9

2

12

2

9

M=OV,SO=
S3=4.5V
S1 =S2=OV
(SUM Mode)

2

11

2

8

2

11

2

8

M=OV,SO=
S3=OV
S1 =S2=4.5V·
(DIFF Mode)

2

13

2

10

2

13

2

10

M=OV,SO=
S3=4.5V
S1 =S2=OV
(SUM Mode)

2

11

2

8

2

11

2

8

M=OV,SO=
S3=OV
S1 =S2=4.5V
(DIFF Mode)

2

12

2

10

2

12

2

10

M=4.5V
(Logic Mode)

2

16

2

11

2

16.

2

11

4

26

4

21

4

26

4

21

M=OV,SO=
S3=OV
S1 =S2=4.5V
(DIFF Mode)
3-258

Units

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Switching Characteristics

(Continued)

Symbol

Parameter

From
(Input)

To
(Output)

tpLH

Propagation Delay Time,
Low to High Level Output

Any A
or B

P

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Propagation Delay Time,
Low to High Level Output

t pHL

Propagation Delay Time,
High to Low Level Output

tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

C L =50 pF (15 pF lor A= B)
RL = 5000 (2800lor A = B)
Conditions

DM54AS881B
Max

Min

C n =M=80=
83 = 4.5V,
81=82=OV,
Equality (AI =
BjorAj*BI)

2

19

2

15

ns

2

19

2

15

ns

C n =M=83=
4.5V, 81 =
82=OV,
Equality
(A;=B; or
AI*BI)

2

24

2

18

ns

2

24

2

18

ns

2

19

2

15

ns

2

19

2

15

ns

2

25

2

19

ns

2

25

2

19

ns

Min

Number

a'

Bits
1104
5108
9to16
171064

Any A
or B

Cn+4

Any A
orB

Any A
orB

P

Cn=m=
82=4.5V,
80=81 =
83=OV,
(Aj=Bj=H or
AI or B;= L

Cn+ 4

C n ='M=82=
4.5V, 80=
81 =83=OV,
(AI=BI=H or
AI or B;= L)

Package Count
Typical Addition Times .
Arithmetic/
Look·Ahead
Using AS881 and AS882
Laglc Units
Carry Ganerators
5
1
0
10
2
0
14
30r4
1
19
51016
2105

Typ

Units

DM74AS881B
Typ

Max

Carry Method
Betwaan
ALUs
None
Ripple
Full Look·Ahead
Full Look·Ahead

Functional Description
The DM54/74A8881B will accommodate active-high or active-low data if the pin designations are interpreted as follows:
2

1

23

22

21

20

19

18

9

10

11

13

7

16

15

17

Active-Low Data (Table I)

AO

BO

A1

B1

A2

B2

A3

B3

FO

F1

F2

F3

Cn

Cn+ 4

P

G

Active-High Data (Table II)

AO

BO

A1

B1

A2

B2

A3

B3

FO

F1

F2

F3

Cn

Cn+4

X

y

Pin Number

8ubtraction is accomplished by 1's complement addition
where the 1's complement of the subtrahend is generated
internally. The resultant output is A - B-1, which requires an end-around or forced carry to provide A-B.

Input C n Output Cn + 4
H
H
L
L

The DM54/DM74A8881B can also be utilized as a comparator. The A = B output Is infernally decoded from the func;
tion outputs (FO, F1, F2, F3) so that when two words of
equal magnitude are applied at the A and B inputs, it will
assume a high level to Indicate equality (A = B). The ALU
must be in the subtract mode with C n = H when performing this comparison. The A = B output is open-collector so
that It can be wire-AND connected to give a comparison
for more than four bits. The carry output (C n + 4) can also
be used to supply relative magnitude information. Again,
the ALU must be placed In the subtract mode by placing
the function-select Inputs 83, 82, 81, 80 at L, H, H, L,
respectively.

H
L
H
L

Active-Low Data Active-High Data
(Figure 2)
(Figure 1)
A2:B
AB
AsB

AsB
A>B
A BI) are equal in the
following manner: P = (AO III BO) + (A1 III 81) + (A2 III B2) +
(A3 III B3). This. unique bit-by-bit comparison of the data
words, which is available on the totem pole Poutput, is particularly useful when cascading the DM54/74A58818, As
the A = B condition is sensed in the first stage, the signal is
propagated through the same ports used for carry generation in the arithmetic mode (P and G). Thus, the A = B status
is transmitted to the second state more quickly without the

SIGNAL DESIGNATIONS
In both Figures 1 and 2, the polarity indicators (0--) indicate that the associated input or output is active-low
with respect to the function shown inside the symbol, and
that the symbols are the same in both figures. The signal
designations In Figure 1 agree with the indicated internal
functions based on active-low data, and are for use with
the logic functions and arithmetic operations shown in
Table I. The signal designations have been ch!!nged in
Figure 2 to accommodate the logic functions and
arithmetic operations for the active-high data given In
Table II. The DM54/74A5181 and DM54/74A5881B,
together with the DM54/74A5882 and DM54/745182, can
be used with the signal designation of either Figure 1 or .
Figure 2.

Function Table for Input Pairs High/Not High
SO=S1 =S3=L, S2=H, and M=H

H
L
X
X
X
X

Outputs

Data Inputs

Cn
AO=BO
AO=BO
AO*BO
X
X
X

A1 =B1
A1 =B1
X
A1*B1
X
X

A2=B2
A2=B2
X
X
A2*B2
X

A3=B3
A3=B3
X.
X
X
A3*B3

G

p

H
H
H
H
H'
H

L
L
H
H
H
H

Cn+ 4
H
L

L
L
L
L

Function Table for Input Bits Equal/Not Equal
SO=S3=H, S1 =S2=L, and M =H

H
L
X
X
X
X

Outputs

Data Inputs

en

AOor BO=L
AOorBO=L
AO=BO=H
X
X
X

A10rB1=L
A10rB1=L
X
A1=B1=H
X
X

A20rB2=L
A20rB2=L
X

,x
A2=B2=H
X
3-262

A3 or B3=L
A30rB3=L
X
X
X
A3=B3=H

G

P

H
H
H
H
H
H

L
L
H
H
H
H

Cn + 4
H
L
L
L
L
L

Parameter Measurement Information

SUM Mode Test Table
Function Inputs: SO S3

= =4.SV, S1 =S2 =M =OV

Parameter

tpLH

Input
Under
Test

Other Input
Same Bit

Other Data Inputs

Apply
GND

Apply
4.SV

Apply
GND

Ai

Bi

None

Remaining
AandB

Cn

Fi

In-Phase

Bi

Ai

None

Remaining
AandB

Cn

Fi

In·Phase

AI

B;

None

None

Remaining
A andB, C n

P

In·Phase

Bi

Ai

None

None

Remaining
A and B, C n

P

In-Phase

Ai

None

Bi

Remaining

Remaining
A,C n

G

In-Phase

Remaining
A,C n

G

In·Phase

All
B

Any F
or Cn+ 4

in Phase

A

tpHL
tpLH
tpHL
tpLH
tpHL
tpLH

B

tpHL
tpLH

Bi

None

Ai

Remaining

B

tpHL
tpLH

Cn

None

None

All

Ai

None

BI

Remaining
B

Remaining
A,C n

Cn+ 4

Out·ol·Phase

Bi

None

Ai

Remaining
B

Remaining
A,C n

Cn+ 4

Out-ol·Phase

tpHL
tpLH
tpHL
tpLH

Output
Wavelorm

Apply
4.SV

tpHL
tpLH

Output
Under
Test

t pHL

-

Logic Mode Test Table
Function inputs: S1 S2

= =M =4.SV, SO =S3 =OV

Parameter

tpLH

Input
Under
Test

Other Input
Same Bit

Other Data Inputs

Output
Wavelorm

Apply
4.SV

Apply
GND

Apply
4.SV

Apply
GND

Ai

B

None

None

Remaining
A andB, C n

Fi

Out-ol-Phase

Bi

Ai

None

None

Remaining
A andB, C n

FI

Out·ol-Phase

t pHL
tpLH

Output
Under
Test

tpHL

3-263

Parameter Measurement Information (Continued)

DIFF Mode Test Table
Function Inputs: S1 S2 = 4.5V, SO = S3

=

Parameter

Input
Under
Test

Other Input
Same Bit
Apply

4.5V
tpLH

AI

None

BI

AI

Other Data Inputs

Apply
GND
BI

Apply

4.5V
\

Remaining

,A

tpHL
tpLH

None

Remaining

A

tpHL
tpLH

AI

None

None

BI

BI

Ai

None
I

None

Ai

BI

None

BI

None

AI

None

BI

Remaining

tpHL
tpLH

,

None

AI

None

A

tpHL
tpLH

BI

Ai

None

Remaining

A

tpHL
tPLI;f

In·Phase

Remaining
B,C n

FI

Out·ol·Phase

Remaining,

P

In·Phase

P

Out·ol·Phase

Remaining
AandB,C n

G

In·Phase

Remaining

G

Out·ol·Phase

Remaining
'B,C n

A=B

In·Phase

Remaining
B,C n

A=B

Out-ol·Phase

Remaining

,

None

None

All
AandB

None

Cn + 4
or Any F

In·Phase

AI

BI

None

None

Remaining
A,B,C n

Cn + 4

Out·ol·Phase

BI

None

AI

None

Remaining
A,B,C n

Cn + 4

In· Phase

tpHL
tpLH

FI

Cn

tpHL
tpLH

Remaining
B,C n

AandB, C n

tpHL
tpLH

Output
Waveform

Apply
GND

A and S, C n

tpHL
tpLH

Output
Under
Test

A andB, C n

tpHL
tpLH

=M =OV

tpHL

3·264

Parameter Measurement Information (Continued)
Input Bits Equal/Not Equal Test Table
Function Inputs: SO S3 M 4.5V, S1

= = =

Parameter

tpLH

Input
Under
Test

Other Input
Same Bit

Other Data Inputs
Apply
4.5V

Apply
GND

AI

BI

None

Remaining
AandB,C n

None

P

Out-ot-Phase

BI

AI

None

Remaining
Aande, Cn

None

P

Out-ot-Phase

Ai

None

BI

Remaining
A and B, Cn

None

P

In-Phase

BI

None

AI

Remaining
A and B, C n

None

P

In-Phase

. Ai

BI

None

Remaining
Aand B, C n

None

Cn +4

In-Phase

BI

AI

None

Remaining
Aande, C n

None

Cn + 4

In-Phase

AI'

None

BI

Remaining
Aande, C n

None

Cn + 4

Out-ot-Phase

BI

None

AI

Remaining
Aande, C n

None

Cn +4

Out-ot-Phase

Output
Under
Test

Output
Waveform

tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH

Output
Waveform

Apply
GND

tpHL
tpLH

Output
Under
Test

·Apply
4.5V

tpHL
tpLH

=S2 =OV

tpHL

Input Pairs High/Not High Test Table
Function Inputs: S2 M ..; 4.5V, SO S1

=

Parameter

tpLH

Input
Under
Test

Other Input
Same Bit

Other Data Inputs

Apply
4.5V

Apply
GND

Apply
4.5V

Apply
GND

AI

BI

None

Remaining
A,C n

Remaining
B

P

In-Phase

Bi

AI

None

Remaining
B,C n

Remaining

P

In-Phase

Remaining
A,C n

Remaining

Cn +4

Out·ot-Phase

Remaining
B,C n

Remaining.
A

Cn +4

Out-ot-Phase

tpHL
tpLH
tpHL
tpLH

AI

BI

None

tpHL
tpLH

= =S3 =OV

Bi

AI

None

tpHL

I

3·265

A
B

Logic Diagram (Positive Logic)

DM54174AS881
S3 3

.
$,

4

5

so

•

13

181

17

~....

.1

'3 "
I,

I_~

a

L
21

I.

"L~

.....

~o-

16

~

I=J>
:=In

~

~

-

15

14

A=8

II

~

13

I

1
~.

23

r

I.

,
A.

ID

~

~
-~

c,

~

1

-

T

JJ
:j))

....

8d

11

D

,

~D

10

•
TUFIU

3·266

f'

f.

c

:s:
U1

~National

~

~ Semiconductor

1;;
.....
o
o
o

DM54AS1 OOOAI DM74AS1 OOOA
Quadruple 2·lnput NAN D Drivers

-:s:»c

General Description

Absolute Maximum Ratings

These devices contain four independent 2·input drivers,
each of which performs the logic NAND function. The
'AS1000A is adriverversion of the 'ASOO. Each driver has
increased output drive capability to allow the driving of
high capacitive loads.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM74AS1000A
DM54AS1000A
Storage Temperature Range

Features
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range,

•

Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.

•

Improved Line Receiving Characteristics.

Connection Diagram

48

4A

4Y

Function Table

38

3A

3Y

Y=AB

8

Inputs

18

lY

2A

28

2Y

l

GND

TL/F/6337·1

54AS1000A (J) 74AS1000A (J, N)

3-267

Output

A

B

Y

L
L
H
H

L
H
L
H

H
H
H
L

H = High Logic Level

lA

~

7V
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual·ln·Line Package
Vee

......

(Note 1)

= Low

Logic Level

1;;
.....

o
o
o

»


-c

DM54AS1004A/DM74AS1004A Hex Inverting Drivers
Absolute Maximum Ratings

General Description
These devices contain six independent 2-input drivers,
each of which performs the logic invert/complement
function. The 'AS1004A is a driver version of the 'AS04.
Each driver has Increased output drive capability to
allow the driving of high capacitive loads.

Features

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS
DM74AS
Storage Temperature. Range

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
• Advanced Oxide-Isolated. Ion-Implanted Schottky TTL
Process.
• Functionally and Pin For Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.
• Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.

-55°C to 125°C
O°C to 70°C
-65°C to 150°C

which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maxImum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Connection Diagram
Dual-In-Line Package
A6

-114

Y6

13

AS

2

A4

10

3
A2

Y4
8

9

Lt>o-

Lt>ort>o-

1><>-

rC»Y1

YS

11

12

l{>o-

1
A1

7V
7V

Note 1:' The"Absoiui-eM;ximum Ratings" are those values beyond

•
•

vee

3:

(Note 1)

4
Y2

S
A3

Output

A
L

Y
H

H

L

H = High Logic Level

6

Y3

L = Low Logic Level

17
GND

TLiF/6338-1

54AS1004A (J)

Input

74AS1004A (J, N)

3-269

.....

~

......
o
o

>

i,..
~
::i

c

~,..
;

11)

Recommended Operating Conditions
DM74AS1004A

DM54AS1004A
Parameter

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Unit

.'
Supply Voltage; VCC

2

High Level Input Voltage, VIH

V

2

Low Level Input Voltage, VIL

V

0.8

0.8

V

High Level Output Current, 10H

-40

-48

mA

Low Level Output Current, 10L

40

48

mA

Max

Unit

-1.2

V

::i
C

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee=5V, TA = 25°C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC

VOH

High Level Output
Voltage

10H = - 2rnA, VCC = 4.5V to 5.5V

=

4.5V, II

Min

=

Typ

-18mA

V

VCC-2
2.4

10H= -3mA, VCC=4.5V

3.2

2

10H = MAX, VCC=4.5V
VOL

Low Level Output
Voltage

VCC = 4.5V
10L=MAX

II

Max High Input Current

VCC

=

5.5V, VIH

=

IIH

High Level Input Current

VCC

=

5.5V, VIH

IlL -

Low Level Input Current

VCC

=

5.5V, VIL

10

Output Drive Current

VCC

=

5.5V

Vo

ICC

.Supply Current

VCC

=

5.5V

'Outputs High

0.35

0.5

V

7V

0.1

mA

=

2.7V

20

/lA

=

0.4V

-0.5

mA

=

2.25V

mA

-135
(

Outputs Low

3.2

5

17.2

28

mA
mA

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at. Vce =5V, TA =25°C.
DM54AS1004A
Parameter

Conditions

TPLH, Propagation
delay time. Low to
high Level Output

VCC = 4.5 to 5.5V
RL = 5000,
CL = 50 pF.

TPHL, Propagation
delay time. High to
low Level Output

1·

5

1.

4

ns

1

5

1

4

ns

3-270

Typ

Max

Unit

Min

Nole 1: See Section 1 for lest waveforms and output load.

Typ

DM74AS1004A
Max

Min

~National

~ Semiconductor
DM54AS1 008A/DM74AS1 008A
Quadruple 2-lnput AN D Drivers
General Description

Absolute Maximum Ratings

These devices contain four independent 2-input drivers,
each of which performs the logic AND function. The
'AS1 008A is a driver version of the' AS08. Each driver has
increased output drive to allow the driving of high
capacitive loads.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS1008A
DM74AS100M
Storage Temperature Range

(Note 1)
7V
7V

-55°e to 125°e
O°C to 70°C
-65°e to 1500 e

Features
•
•
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and Vec Range.
Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
Improved Line Receiving Characteristics.

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Connection Diagram
Dual-ln·Line Package
Vee

84

A4

Y4

Y=AB
Y3

83

8

Inputs

Y2

GND

TLlFf6339·1

54AS1008A (J)

B

Y

L

l

L

L

H

L

H
H

L

L

H

H

L = low logic level
H = high logic level

7
82

Output

A

74AS1008A (J, N)

3-271

Recommended Operating Conditions
DM74AS100SA

DM54AS100SA
Parameter
Supply Voltage, VCC
High Level Input Voltage, VIH

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

Unit
V
V

2

Low Level Input Voltage, VIL

O.S

O.S

V

High Level Output Current, IOH

-40

-48

mA

Low Level Output Current, IOL

40

48

mA

Max

Unit

-1.2

V

Electrical Characteristics over recommended operating free air temperature range.
'AII typical values are measured at Vee = 5V, TA = 25°C.
-

Symbol

Parameter

VIK

Input Clamp Voltage

VCC=4.5V, 11= -18mA

Min

VOH

High Level Output
Voltage

Vec = 4.5V
VIH = 2V

Conditions

2.4

IOH= -3mA

VOL

Low Level Output
Voltage

VCC = 4.5V
VIL=0.8V
IOL,=MAX

II

Max High Input Current

IIH

V

3.2

V

2

10H=MAX

10H= -2mA

Typ

VCC = 4.5V to 5.5V

V

VCC -2
0.5

V

VCC=5.5V,VIH=7V

0.1

mA

High Level Input Current'

VCC=5.5V, VIH=2.7V

20

p.A

Low Level Input Current

VCC=5.5V, VIL=O.4V

-0.5

mA

10

Output Drive Current

VCC

5.5V

I

Vo

ICCH

Supply Current

Outputs Hig h VCC

=

ICCL

Supply Current

Outputs Low VCC

=

. IlL

=

0.35

=

2.25V

-135

5.5V, VI

=

4.5V

5.6

9.5

mA

5.5V, VI

=

OV

18.5

22

mA

mA

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V, TA = 25°C.

DM74AS100SA

DM54AS100SA
Parameter

Conditions

TPLH, Propagation
delay time. Low to
high Level Output.

VCC = 4.5 to 5.5V
RL = 500 n,
CL = 50 pF.

TpHL, Propagation
delay time. High to
low Level Output

Typ

Typ

Min

1

6.5

1

6

ns

1

6.5

1

6

ns .

Note 1: See Section 1 for test waveforms and output load.

3-272

Max

Unit

Max

Min

c

3:

~National

U1

;

~ Semiconductor

en
....
c(,.)

N

DM54AS1032A/DM74AS1032A Quadruple 2-lnput OR Driver »
c

3:
......

General Description

Absolute Maximum Ratings (Note 1)

These devices contain four independent 2·input drivers,
each of which performs the logic OR function. The
'AS1 032A is a driver version of the' AS32. Each driver has
increased output drive capability to allow the driving of
high capacitive loads.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS1032A
DM74AS1032A
Storage Temperature Range

Features

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
• Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
• Improved Line Receiving Characteristics.

7V
7V
-55°C to 125°C
O°C to 70°C
-65°C to 150°C

Function Table

Connection Diagram

Dual·ln·Line Package
Vee

84

83

A4

A3

Y3

o

Y=A+B
Inputs

A

7
.A1

81

Y1

A2

82

Y2

GND

TLlF/6340·1

54AS1032A(J)

74AS1032A(J, N)

3·273

B

Output

Y

L

L

L

H

X

X

H

H
H

L= low logic level
H :::: high logic level

X:::: either low or high logic level

;en
....

c(,.)
N

»

Recommended Operating Conditions
DM54AS1032A
Parameter
Supply Voltage, VCC
High Level Input Voltage, VIH

DM74AS1032A

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

2

Unit
V
V

I

Low Level Input Voltage, VIL

0.8

0.8

V

High Level Output Current, 10H

-40

-48

mA

Low Level Output Current, 10L

40

48

mA

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25'C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC=4.5V, 11= -18mA

VOH

High Level Output
Voltage

VCC = 4.5V
VIH = 2V

IOH=-3mA

10H= -2mA

VCC = 4.5V to 5.5V

Min

Typ

Max·
1.2

.1

2.4

3.2

V
V

2

10H=MAX

Unit

V
V

VCC -2
0.5

V

VCC = 5.5V, VIH = 7V

0.1

mA

High Level Input Current

VCC=5.5V, VIH=2.7V

20

#LA

IlL

Low Level Input Current

VCC = 5.5V, VIL = 0.4V

-0.5

mA

10

Output Drive Current

VCC = 5.5V

ICCH

Supply Current

Outputs High VCC = 5.5V, VI = 4.5V

ICCL

Supply Current

Outputs Low VCC = 5.5V, VI = OV

VOL

Low Level Output
Voltage

VCC = 4.5V
VIH =0.8V
10L=MAX

II

Max High Input Current

IIH

0.35

Vo = 2.25V

mA

-135
7.7

11.5

mA

14.7

24

mA

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vce = 5V, TA = 25'C.
DM54AS1032A
Parameter

Conditions

TpLH, Propagation
delay time. Low to
high Level Output

VCC = 4.5 to 5.5V
RL = 5000,
CL = 50 pF.

TpHL, Propagation
delay time. High to
low Level Output

Typ

DM74AS1032A
Min

1

7

1

6.3

ns

1

7

1

6.3

ns

Note 1: See Section 1 for test waveforms and output load.

3-274

Typ

Max

Unit

Max

Min

,-------------------------------------------------------------~c

:s::
U1

~National

~

.~ Semiconductor

fJ)

...&.

C)
(,.)

DM54AS1034A/DM74AS1034A Hex Non-Inverting Drivers
General Description

Absolute Maximum Ratings (Note 1)

These devices contain six independent drivers, each of
which performs the logic identity function. The
'AS1 034A is a driver version of the' AS34. Each driver has
increased output drive capability, allowing the drivng of
high capacitive loads.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS
DM74AS
Storage Temperature Range

~
c

7V
7V
-55°C to 125°C
O°C to lO°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
nol be operated at these limits. The parametriC values defined in the
"Electrical Characteristics" table are nol guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Features
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and VCC Range.
• Advanced Oxide-Isolated, lon-Implanted Schottky TTL
Process.
• Functionally and Pin for Pin Compatible with Schottky
and Low Power Schottky TTL Counterpart.
• Improved AC Performance Over Schottky and Low
Power Schottky Counterparts.

Connection Diagram
Dual·ln·Line Package

TLIF16341-1

54AS1034A (J)

74AS1034A (J, N)

Function Table
A=Y
Input

Output

A

Y

L
H

L
H

L = low logic level
H;: high logic level

3-275·

:s::
......

~
...&.

C)
(,.)

~

Recommended Operating Conditions
DM74AS1034A

DM54AS1034A
Parameter
Supply Voltage, VCC
High Level Input Voltage, VIH

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

2

Low Level Input Voltage, VIL

Unit
V
V

0.8

0.8

V

High Level Output Current, 10H

-40

-48

mA

Low Level Output Current, 10L

40

48

mA

Max

Unit

-1.2

V

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measwed at Vee = 5V, TA = 25°C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VCC

VOH

High Level Output
Voltage

10H

=

4.5V, II

Min

=

= - 2mA, VCC =4.5V to.5.5V

2.4

10H=Max

2
0.35

Low Level Output
Voltage

VCC = 4.5V
10L=MAX

II

Max High Input Current

VCC

·V

VCC-2

10H= -3mA

VOL

Typ

-18mA

3.2

V

0.5

V

=

5.5V, VIH

=

7V

0.1

mA

-

IIH

High Level Inpllt Current

VCC

=

5.5V, VIH

=

2.7'1

20

/LA

IlL

Low Level Input Current

VCC

=

5.5V, VIL

=

O.4V

-0.5

mA

10

Output Drive Current

VCC

=

5.5V

Vo

ICC

Supply Current

VCC

=

5.5V

Outputs High

9.3

14

mA

Outputs Low

22

33

mA

=

mAo

-135

2.25V

Switching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V, TA = 25°C.
Parameter

Conditions

TPLH, Propagation
delay time. Low to
high Level Output

VCC = 4.5 to 5.5V
RL = 500 n,
CL = 50 pF.

TpHL, Propagation
delay time. High to
low Level Output
Note 1: See

Se~tlon

,

DM74AS1034A

DM54AS1034A
Min

1

6.5

1

6

ns

1

6.5

1

6

ns

1 for test waveforms and output load.

3-276

Typ

Typ

Max

Unit

Max

Min

~National

a

Semiconductor

DM54AS1036A/DM74AS1036A,Quad 2·lnput NOR Drivers
~:

General Description

Absolute Maximum Ratings (Note 1)

These devices contain four independent drivers, each of
which performs the logic NOR function. Each driver has
increased output drive capability, allowing the driving of
high capacitive loads.

Supply Voltage
Input Voltage
Operating Free Air Temperature Range
DM54AS
DM74AS
Storage Temperature Range

Features
•
•
•
•
•

Switching Specifications at 50 pF.
Switching Specifications Guaranteed Over Full
Temperature and Vee Range.
Advanced Oxide-Isolated. Ion-Implanted Schottky TTL
Process.
Functionally and Pin for Pin Compatible with
Advanced Low Power.

Y4

84

A4

GND

•
Function Table

83

A3

Y=A+B
Inputs

Output

A

B

Y

X

H

H
L

X

L
L
H

L

H = High Lagle Level
L = Low Logic Level
X = Either Low or High Logic Level

A1

81

Y1

Vee

Y2

A2

82

TLlF/6342·1

54AS1036A (J)

-55°C to 125°C
ooe to 70°C
-65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can nat be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the cpndltlons for actual device operation.

Improved Ae Periormance Over TTL Counterparts.

Connection Diagram

7V
7V

74AS1036A (J, N)

3·277

~ Recommended Operating Conditions

C")

....
....
o

;

::i

o

~
C")

....o

~

~
II)

DM74AS1036A

DM54AS1036A
Parameter

Supply Voltage. Vec

Min

No'1l

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

High Level Input Voltage. VIH

2

Unit

V
V

0.8

0.8

V

High Level Output Current. 10H

-40

-48

mA

Low Level Output Current. 10L

40

48

mA

Max

Unit

-1.2

V

Low Level Input Voltage. VIL

::i

o

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V. TA = 25·C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

Vec = 4.5V. II = -18 mA

VOH

High Level Output
Voltage·

10H = - 2mA. VCC = 4.5V to 5.5V

Min

Low Level Output
Voltage

VCC = 4.5V. 10L = 20mA

II

Max High Input Current

IIH

\

2.4
2

10H=Max
VOL

V

VCC-2

. 10H;" -SmA

VCC=4.5V

Typ

0.5

V

Vce = 5.5V. VIH = 7V

0.1

mA

High Level Input Current

Vce = 5.5V. VIH = 2.7V

20

p.A

IlL

Low Level Input Current

Vee = 5.5V. VIL = O.4V

-0.5

mA

10

Output Drive Current

Vee = S.5V

Vo = 2.25V

-135

Ice

Supply Current

Vee = 5.5V

Outputs High

4.7

7

mA

Outputs Low

15.3

23

mA

0.35

mA

SWitching Characteristics over recommended operating free air temperature range (Note 1).
All typical values are measured at Vee = 5V. TA = 25·C.
DM74AS1036A

DM54AS1036A
Parameter

Conditions

TPLH. Propagation
deiay time. Low to
high, level output

Vce = 4.5 to 5.5V
RL = 500 Q.
CL = 50 pF.

TpHL. Propagation
delay time. High to
low level output

Typ

Typ

Min

1

4.8

1

4.3

ns

1

4.8

1

4.3

ns

Note 1: See Section 1 for test waveforms and output load.

3-278

Max

Unit

Max

Min

r---------------------------------------------------------------'c

3:

~National

en

I-

~ Semiconductor
DM54AS2620/DM74AS2620, DM54AS2623/DM74AS2623
Octal Bus Transceivers/MOS Drivers

o

c
3:
~

General Description

Features

These octal bus transceivers are designed to drive the
capacitive input characteristics of MOS devices and allow
asynchronous two-way communication between data
buses. The control function implementation allows for
maximum flexibility in timing.

• Bidirectional octal bus transceivers for driving MOS
devices
• I/O ports have 250 series resistors so no external
resistors are required
• Local bus-latch capability
• Choice of true or inverting logic

These devices allow data transmission from the A bus to
the B bus or from the B bus to the A bus, depending upon
the logic levels at the enable inputs (GBA and GAB).
The enable inputs can be used to disable the device so
that the buses are effectively isolated.
The dual enable configuration gives the 'AS2620 or
'AS2623 the capability to store data by simultaneous
enabling of the GBA and GAB. Each output reinforces its
input in this transceiver configuration. Thus, when both
control inputs are enabled and all other data sources to
the two sets of bus lines are at high impedance, both sets
of bus lines (16 In all) will remain at their last states. The
B·bit codes appearing on the two sets of buses will be Identical for the 'AS2623 or complementary for the 'AS2620.

Connection Diagrams

]V
5.5V
7V
- 65·C to 150·C

Nota 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Logic Diagrams

Dual·ln·Llne Package
GAB

Vee

Al

GBA

A2

Bl

A3

B2

'AS2620
GBA----<)I
GAB

A4

16

B3

A5

15

B4

A6

14

B5

A7

13

B6

Al--....I--t

~~-++-Bl

TO OTHER SEVEN
TRANSCEIVERS

TLIF16729.'

'AS2623
AB

B7

GNO

GBA----<)I

BB
TOP VIEW

GAB
TLfF/6129-1

Function Table
Enable Inputs
GBA
GAB
L
L

H
H

H

L

H

L

Operation
'AS2620
'AS2623
B data to A bus B data to A bus
Adata to B bus A data to B bus
Isolation
Isolation
B data to A bus, B data to A bus,
Adata to B bus A data to B bus

Al--"'I--t

~~-++-Bl

TO OTHER SEVEN
TRANSCEIVERS

3·279

TLlF16729-3

~
5='

c

3:
en

t

~

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
I!OPorts
Other Ports
Storage Temperature Range

~

~

~

c
3:
~

~
~

Co)

Recommended Operating Conditions
Symbol

DM74AS2620
DM74AS2623

DM54AS2620
DM54AS2623

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

TA

Operating Free·Alr Temperature

Units

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

V

0.8

V'

70

·c

2

2

V

0.8
-55

125

0

Electrical CharaQteristiC;s over recommended operating free-air temperature range (unless otherwise noted)
Symbol

Parameter

Conditions

DM54AS2620
DM54AS2623
Min

1YP

DM74AS2620
DM74AS2623
Max

Min

(Note 1)
VIK

Input Clamp
Voltage

Vee=4.5V,II= -18 mA

VOH

High Level
Output
Voltage

Vee = 4.5V to 5.5V, 10H = - 2 mA

VOL

Low Level
Output
Voltage

Vee = 4.5V, 10L = 1 mA
Vee=4.5V,loL = 12 mA

II

IIH

IlL

Max

Units

(Note 1)
-1.2

-1.2

V
V

Vcc- 2

Vee- 2

0.15
0.35

0.4
0.7

0.15
- 0.35

,

0.4
0.7

V
V

Control Inputs Vee=5.5V, VI=7V

0.1

0.1

mA

Aor B Ports

Vee =5.5V, VI=5.5V

0.1

0.1

mA

Control Inputs Vee=5.5V, VI=2.7V

20

20

ItA

Aor B Ports
(Note 3)

70

70

p.A

-0.5

-0.5

mA

-0.75

-0.75

mA

-150

mA

Control Inputs Vee=5.5V, VI=0.4V
A or B Ports
(Note 3)

10 (Note 2)" Output
Current

Vee = 5.5V, Va = 2.25V

-50
-35

-35

mA

35

35

mA

10H

High Level
Output
Current

Vcc=4.5V, Vo=2V

10L

Low Level
Output
Current

Vyc=4.5V, Vo=2V'

Icc

AS2620

Vee = 5.5V

AS2623

Vee =5.5V

-150

-50

Outputs High

62

100

62

100

mA

Outputs Low

74

121

74

121

mA

46

77

mA

Outputs Disabled

Notat:
Nota 2:
Nota 3:

1YP

46

77

Outputs High

58

93

58

93

mA

Outputs Low

116

'189

116

189

rnA

Outputs Disabled

72

116

72

116

rnA

All typical values are at Vee= SV, TA= 2S"e,
The output conditions have been chosen to produce a current that closely approximates one half of the true short circuit output current, lOS.
For 1/0 ports, the parameters IIH and IlL Include the pll-.tate output current.

3·280 .

AS2620 Switching Characteristics
DM54AS2620
Parameter

. Input

Output

Conditions

Min

Typ

DM74AS2620

Max

Min

(Note 1)
tpLH

A

B

tpHL
tpLH

B

A

tpHL
tPZH

GBA

Vee = 4.5V to 5.5V,
CL=50 pF,
Rl =5000,
R2=5000,
TA = Min to Max

tpHZ

GBA

A

GAB

B

GAB

B

tPZL
tpHZ

\

tpLZ

Units

1

9.5

1

B

ns

7.5

1

6.5

ns

1

9.5

1

8

ns

1

7.5

1

6.5

ns

1

11

1

10

1

12

1

11

ns

1.

6

ns

1

tpLZ
tPZH

Max

1

A

tPZL

Typ
(Note 1)

7.5

ns

1

15

1

12

ns

1

9

1

8

ns

1

9

1

8

ns

1

12

1

11

ns

1

12

1

11

ns

Max

Min

AS2623 Switching Characteristics
DM54AS2623
Parameter

Input

Output

Conditions

tpLH

A

B

Vee = 4.5V to 5.5V,
C L =50pF,
Rl =5000,
R2=5000,
TA = Min to Max

tpHL
tpLH

B

A

tpHL
tPZH

GBA

A

tPZL.
tpHZ

GBA

A

ipLZ
tPZH

GAB

B

tPZL
tpHz

GAB

B

tpLZ
Note 1:

Min

Typ
(Note 1)

DM74AS2623'"
Typ
(Note 1)

Max

Units

1

9.5

1

8.5

ns

1

8.5

1

7.5

ns

1

10

1

9

ns

1

9

1

7.5

ns

1

12.5

1

11

1

12

1

11

1

8.5

1

7.5

ns
ns
ns

1

13

1

12

ns

1

13

1

12

ns

1

13.5

1

12

ns

1

7.5

1

7

ns

1

14.5

1

12.5

ns

All typical values are at Vee=5V, TA=25"e.

3·281

U)r---------------------------------------------------------------------,
.~ ~ National
~ ~ Semiconductor
:E
c
U;

DM54AS2640/DM74AS2640,DM54AS2645/DM74AS2645

~ TRI·STATE® Bus Transceivers/MOS Drivers

;U)

:E General Description

c

l

~

:E

-~
c

C'i

~

:E

c

This family of advanced low power Schottky devices contains 8 pairs of logic elements configured as octal bus
transceivers. They are designed to drive the capacitive input characteristics of MOS devices and allow asynchronous bidirectional communications between data buses.
Data transmission from the A bus to the B bus or from the
B bus to the A bus are selectively controlled by (DIR and G)
the direction and enable inputs. This enable input is also
used to disable the device so that the buses are effectively
isolated.

Features
• Bidirectional octal bus transceivers for driving MOS
devices
• I/O ports have 250 series resistors so no external
resistors are required
• Choice of true or inverting logic

• Advanced oxide isolated, ion-implanted Schottky TIL
process
• Switching response specified into 5000150 pF load
• Switching specifications guaranteed over full
temperature and Vcc range

Absolute Maximum Ratings

Connection Diagrams
Dual-In-Line Package
28
38
48
58
68
78
88
120 119 118 117 11& \15 114 113 112 111
J J J J J J J J J

ii

18

r r ["" r [ [ [. r
DlR
TL/F/6343-1

DM54AS2640 (J)

7V
7V

+ 150·C
+ 300·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated et these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions"table will
define the conditions for actual device operation.

Vee

(Note 1)

Supply Voltage, Vcc
Input Voltage
Storage Temperature Range
-:- 65·C to
Lead Temperature (Soldering, 10 seconds)

DM74AS2640 (J, N)

3-282

Connection Diagrams

(Continued)

Dual-In-Line Package
18
ii
I~

Vee

Iw

28

38

la lola
J

.J J

J

48

58

68

115

1M

IN In
J

rI rI J

,I.
VI

78

88

111

J

IL

'7

'f

r r r r r r r r yo
1
1
_~3 3~4 1
2A

1~2

1
DlR

5
4A

6

5A

7
JA

8
7A

JAg

GND

TLIF/6343·3

CM54AS2645 (J)

CM74AS2645 (J, N)

Function Table
Control
Inputs

G

CIR

AS2640

AS2645

L
L
I-j

L
H

B Data to A Bus

B Data to A Bus
A Data to B Bus
Hi-Z

X

•

Operation

A Data to B Bus
Hi-Z

Recommended Operating Conditions
Symbol

Parameter

Vee

Supply Voltage

V1H

High Level Input Voltage

V 1L

Low Level Input Voltage

TA

Operating Free Air Temperature

Min

DM54AS
Typ

Max

Min

DM74AS
Typ

Max

4.5

5

5.5

4.5

5

5.5

2
0.8
125

3·283

0

V
V

2

-55

Units

0.8

V

70

·C

Electrical Characteristics over recommended operating free air temperature range.
All typical values are measured at Vee = 5V, TA = 25'C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V, IIN= -18mA

VOH

High Level Output Voltage

IOH= -2mA

VOL

Low Level Output Voltage

Vee=4.5V

0.25

0.4

0.35

0.7

V

0.1

mA

Control Inputs'

20

p.A

Aor B Ports

70 .

IIH

High Level Input Current

Vee = 5.5V,
VIN=2.7V

Control Inputs

-0.5

A or B Ports

-0.75

10

Output Drive Current

Vee=5.5V, VouT=2.25V

Icc

DM54/74AS2640 Supply Current

Vee = 5.5V

Icc

DM54/74AS2645 Supply Current

Vee = 5.5V

V
V

IOL= -1 mA

Vee = 5.5V, VIN = 7V
(VIN = 5.5V for A or B Ports)

Vee = 5.5V,
VIN=0.4V

-1.2

Units

IOL=12mA
Input Current at Max Input Voltage

Low Level Input Current

Max

Typ

Vee- 2

II

IlL

Min

-50

-150

Outputs High

37

58

V

mA

mA
mA

Outputs Low

78

123

mA

TRI·STATE

51

80

mA

Outputs High

58

95

mA

Outputs Low

95

155

mA

TRI·STATE

73

119

mA

,

3·284

Switching Characteristics over recommended operating free air temperature range (Notes 1 and 2)
All typical values are measured at Vee = 5V, T A = 25'C.
Symbol

Parameter

tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

tPZL

Output Enable Time to Low Level

tPZH

Output Enable Time to High Level

tpLZ

Output Disable Time from Low Level

tpHZ

Output Disable Time from High Level

tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level'Output

tPZL

Output Enable Time to Low Level

tPZH

Output Enable Time to High Level

tpLZ

Output Disable Time from Low Level

tpHZ

Output Disable Time from High Level

Circuit Configuration

IN~OUT

DM74AS

DM54AS
Min

Typ

Typ

Max

Min

1

9.5

1

7.5

ns

1

7

1

6.5

ns

2

11

2

9

ns

2

12

2

10

ns

1

8

1

7

ns

2

15

2

13

ns

1

12

1

10

ns

1

11

1

9.5

ns

1

13

1

11.5

ns

1

13

1

10.5

ns

1

9

1

8

ns

1

13

1

12

ns

AS2640

IN~
BORA

AORB
OUT

AS2640

IN~OUT

Units

Max

AS2645

IN~ a
,

ADR

OUT

AS2645

Note 1: See Section 1 for test waveforms and output load.

Note 2: Switching characteristic conditions are Vee = 4.5V to

5.5V, RL= 500ll, eL = 50 pF.

.
3·285

Section 4

Low Power Schottky

Section Contents
DM54/74LSOOQuad2-lnput NAND Gates .......................................... _.
DM54/74LS01 Quad 2-lnput NAND Gates with Open-Collector Outputs ......... _. . . . . . . . . .
DM54/74LS02 Quad 2-lnput NOR Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . .
DM54/74LS03 Quad 2-lnput NAND Gates with Open-Collector Outputs ......... _. . . . . . . . . .
DM54/74LS04 Hex Inverters ..................................... ~. . . . . . . . . . . . . . . . .
DM54/74LS05 Hex Inverters with Open-Collector Outputs ................ _. . . . . . . . . . . . . .
DM54/74LS08 Quad 2-lnput AND Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS09 Quad 2-lnput AN D Gates with Open-Collector Outputs .....................
DM54/74LS10Tripie 3-lnput NAND Gates ............................. : . . . . . . . . . . . . . .
DM54/74LS11Triple3-lnputANDGates .......... _...................................
DM54/74LS12Triple3-lnput NAND Gates with Open-Collector Outputs. . . . . . . . . . . . . . . . . . . .
DM54/74LS13 Dual4-lnput SchmittTrigger NAND Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS14 Hex SchmittTrigger Inverters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS15 Triple 3-lnput AN D Gates with Open-Collector Outputs .....................
DM54/74LS20 Dual4-lnput NAND Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS21 Dual4-lnput AND Gates ..............................................
DM54/74LS22 Dual4-lnput NAND Gates'with Open-Collector Outputs . . . . . . . . . . . . . . . . . . . . .
DM54/74LS26 Quad 2-lnput NAND Buffers with High-Voltage
Open-Collector Outputs ................. _. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. . . .. . .
DM54/74LS27 Triple 3-lnput NOR Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS30 8-lnputNANDGate..................................................
DM54/74LS32 Quad 2-lnput OR Gates ...................... _. . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS37 Quad 2-lnput NAND Buffers .............................. _. . . . . . . . . . . .
DM54/74LS38 Quad 2-lnput NAND Buffers with Open-Collector Outputs . . . . . . . . . . . . . . . . . . .
DM54/74LS40 Dual4-lnput NAND Buffers ........... _. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS42 BCD to Decimal Decoder .. : .......................... _. . . . . . . . . . . . . . .
DM54/74LS47 BCD to 7-Segment DecoderlDriver with Open-Collector Outputs .............
DM54/74LS48 BCD to 7-Segment DecoderlDriverwith Internal Pull-Up Outputs. . . . . . . . . . . . .
DM54/74LS49 BCD to 7-Segment DecoderlDriverwith Open-Collector Outputs .............
DM54/74LS51 Dual2-Wide 2-lnput AND,OR-I NVERT Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS54 4-WideAND-OR-INVERTGates ..................... : .... _. . . . . . . . . . . . .
DM54/74LS55 2-Wide4-lnput AND-OR-INVERTGates ................ :................
DM54/74LS73A Dual J-K Negative-Edge-Triggered Flip-Flops with Clear. . . . . . . . . . . . . . . . . .
DM54/74LS74A Dual D Positive-Edge-Triggered Flip-Flops with Preset and Clear. . . . . . . . . . .
DM54/74LS75 4-Bit Bistable Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS76A Dual J-K Negative-Edge-Triggered Flip-Flops with Preset and Clear. . . . . . . . .
DM54/74LS77 4-Bit Bistable Latches. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .
DM54/74LS78A Dual J-K Negative-Edge-Triggered Flip-Flops with
Common Clear and Common Clock ........ _..................................... _
DM54/74LS83A f-Bit Binary Adders with Fast Carry. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .
DM54/74LS85 4-Bit Magnitude Comparators .............................. :. . . . . . . . . .
DM54/74LS86 Quad Exclusive-OR Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS90 Decade Counter .......... '-' . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .
DM54/74LS92 Divide by 12 Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS93 4-Bit BinaryCounter ........... '. . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . .. . .. . .
DM54/74LS107A Dual J-K Negative-Edge-Triggered Master-Slave Flip-Flops with Clear. . . . . .
DM54/74LS1 09A Dual J-i( Positive-Edge-Triggered Flip-Flops with Preset and Clear. . . . . . . . .

4-2

4-5
4-7
4-9
4-11
4-13
4-15
4-17
4-19
4-21
4-23
4-25
4-27
4-30
4-33
4-35
4-37
4-39
4-41
4-43
4-45
4-47
4-49
4-51
4-53
4-55
4-58
4-58
4-58
4-67
4-69
4-71
4-73
4-76
4-80
4-83
4-87
4-90
4-93
4-97
4-101
4-104
4-104
4-104
4-116
4-119

Section Contents (Continued)
DM54/74LS112A Dual J·K Negative·Edge·Triggered Flip·Flops with Preset and Clear. . . . . . . .
DM54/74LS113A Dual J·K Negative·Edge·Triggered Flip·Flops with Preset ................
DM54/74LS114A Dual J·K Negative·Edge·Triggered Flip·Flops
with Preset, Common Clear, and Common Clock ....................................
DM54/74LS122 Retriggerable Monostable Multivibrators with Clear ....... ',' . . . . . . . . . . . . .
DM54/74LS123 Dual Retriggerable Monostable Multivibrators with Clear. . . . . . . . . . . . . . . . . .
DM54/74LS125A Quad TRI·STATE Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS126A QuadTRI·STATE Buffers...........................................
DM54/74LS132 Quad 2-lnputSchmitt Trigger NAND Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS136 Quad Exclusive·OR Gates with Open·Coliector Outputs, . , . . . . . . . . . . . . . . . . .
DM54/74LS138 3t08LineDecoder/Demuitiplexer ....................................
DM54/74LS139 Dual2t04 Line Decoders/Demultiplexers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS151 1 of8 Line DataSelector/Multiplexer ......................... ',' . . . . . . .
DM54/74LS153 Dual 1 of4 Line DataSelectors/Multiplexers .......................... , . .
DM54/74LS154 4 to 16 Line DecoderJDemultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS155 Dual2 t04 Line Decodersl1 t04 Line Demultiplexers. . . . . . . . . . . . . . . . . . . . . .
DM54/74LS156 Dual 2 to 4 Line Decoders/1 to 4 Line Demultiplexers
with Open·ColiectorOutputs ....................................................
DM54/74LS157 Quad 2to 1 Line DataSelectors/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS158 Quad 2,to 1 Line Inverting Data Selectors/Multiplexers ....................
DM54/74LS160A Synchronous 4·Bit Decade Counter with Asynchronous Clear ............
DM54/7 4LS161 A Synchronous 4-Bit Binary Counter with Asynchronous Clear .............
DM54/74LS162A Synchronous 4·Bit Decade Counter with Synchronous Clear. . . . . . . . . . . . . .
DM54/74LS163A Synchronous 4-Bit Binary Counter with Synchronous Clear. . . . . . . . . . . . . . .
DM54/74LS164 8-Bit SeriallnlParaliel Out Shift Register with Asynchronous Clear . . . . . . . . . .
DM54174LS165 8-Bit Parallel'nlSerial Out Shift Register with
Complementary Outputs ......... .'.............................................
DM54174LS166 8-Bit Parallel or Serial InlSerial Out Shift Register
with Complementary Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54174LS168A Synchronous4-Bit UplDown Decade Counter. . . . . . . . . . . . . . . . . . . . . . . . . .
DM54174LS169A Synchronous 4-Bit UpJDown Binary Counter. . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54174LS170 4 by 4 Register File with Open·Coliector Outputs ......... : . . . . . . . . . . . . . . .
DM54174LS173A 4·BitTRI·STATE D Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .
DM54174LS174 Hex D Flip·Flops with Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54174LS175 Quad D Flip·Flops with Clear and Complementary Outputs: . . . . . . . . . . . . . . . .
DM54174LS190 Synchronous UpJDown Decade Counter with Mode Control ................
DM54174LS191 Synchronous 4-Bit UplDown Binary Counter with Mode Control. . . . . . . . . . . . •
DM54174LS192 Synchronous UplDown Decade Counter with Dual Clock ....... "...........
DM54174LS193Synchronous4-Bit UpJDown Binary Counter with Dual Clock .. '. . . . . . . . . . . . .
DM54174LS194A :4·Bit Bidirectional Universal Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54174LS195A 4-Bit Parallel Access Shift Register ............................ " . . . . .
DM54174LS196 Presettable Decade (Bi·Quinary) Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54174LS197 Presettable Binary Counter. . . .. . . .. . . .. . . . . . . . . .. . . . . . . . . . . . . . . . . .. . .
DM54174LS221 Dual Monostable Multivibrators with Schmitt·Trigger Input ................
DM54174LS240 Octal TRI·STATE Inverting BLifferslLine DriverslLine Receivers .............
DM54174LS241 Octal TRI·STATE BufferslLine DriverslLine Receivers. . . . . . . . . . . . . . . . . . . . .
DM54174LS242 Octal TRI·STATE Inverting Bus Transceivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4·3

4-122
4-125
4-128
4-131
4-135
4·140
4-143
4-146
4·149
4-152
4·152
4-158
4-162
4-165
4-168
4-168
4-173
4-173
4-178
4-178
4-178
4-178
4-189
4-1,92
4-196
4-200
4-200
4-208
4-212
4-216
4-216
4-221
4-221
4-227
4-227
4-234
4·238
4-242
4-242
4-250
4-255
4-255
4-258

Section Contents (Continued)
DM54/74LS243 Octal TRI-STATE Bus Transceivers
DM54/74LS244 Octal TRI-STATE Buffers/Line Drivers/Line Receivers
DM54/74LS245 OctaITRI-STATE Bus Transceivers
~
DM54/74LS247 BCD to 7-Segment DecoderlDriverwith Open-Collector Outputs
DM54/74LS248 BCD to 7-Segment Decoder/Driver
DM54/74LS249 BCD to 7-Segment DecoderlDriver with Open-Collector Outputs
DM54/74LS251 TRI-STATE 1 of 8 Line Data Selector/Multiplexer with
Complementary Outputs
DM54/74LS253 Dual TRI-STATE 1 of 4 Data Selectors/Multiplexers
DM54/74LS257B Quad TRI-STATE 2 to 1 Line Data Selectors/Multiplexers
DM54/74LS258B Quad TRI-STATE 2 to 1 Line Inverting Data Selectors/Multiplexers
DM54/74LS259 8-Bit Serial In to Parallel Out Addressable Latch
DM54/7 4 LS266 Quad Excl usive-NOR Gates with Open-Collector Outputs
DM54/74LS279QuadS-RLatches
DM54/74LS283 4-Bit Binary Adders with Fast Carry
DM54/74LS290 Decade Counter
DM54/74LS293 4-Bit Binary Counter
DM54/74LS298 Quad 2 to 1 Line Data Selectors/Multiplexers with Storage
DM54/74LS352 Dual1 of 4 Line Inverting Data Selectors/Multiplexers
DM54/74LS353 Dual TRI-STATE 1 of 4 Line Data Selectors/Multiplexers
DM54/74LS365A Hex TF!I-STATE Buffers/Bus Drivers
DM54/74LS366A HexTRI-STATE Inverting Buffers/Bus Drivers
DM54/74LS367A HexTRI-STATE Buffers/Bus Drivers
DM54/74LS368A Hex TRI-STATE Inverting Buffers/Bus Drivers
DM54/74LS373 Octal TRI-STATE Transparent D Latches
DM54/7 4LS37 4 Octal TRI-STATE Positive-Edge-Triggered D Flip-Flops
DM54/74LS386 Quad Exclusive-OR Gates
DM54/74LS390 Dual Decade (Bi-Quinary) Counter
DM54/74LS393 Dual4-Bit Binary Counter
DM54/74LS465(DM71/81 LS95A) Octal TRI-STATE Buffers/Bus Drivers
DM54/74LS466 (DM71/81 LS96A) Octal TRI-STATE InvertingBuffers/Bus Drivers
DM54/74LS467 (DM71/81 LS97 A) Octal TRI-STATE Buffers/Bus Drivers
DM54/74LS468(DM71/81 L~98A) Octal TRI-STATE Inverting Buffers/Bus Drivers
DM54/74LS645 Octal TRI-STATE Bus Transceivers
DM54/74LS670TRI-STATE4 by4 Register File
DM54/74LS952 Dual TRI-STATE 8-Bit Positive-Edge-Triggered
Rank Shift Registers
DM54/74LS962 Dual TRI-STATE 8-Bit Positive-Edge-Triggered
RankShift Registers
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

_

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

..

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

00

0

0

00

0

0

0

0

0

0

0

0

0

0

000000

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

:

0

00

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

_

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

;

0

0000

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

00000000000000000000000000000000000000000000000000

0

000

0

0

0

0

000

0

0

00

0

0

0

000

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

000

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0000

0

0

0

0

0000

000000:

0

0

0

0000000000000000000000000000000000000000000000000

00

0

0

000

0

00000000000

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

:

0

0

0

0

0

0

0

0

0

0

0

0

00000000000000000000000000

00

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

..

0

0

0

0

0

0

0

0

0

0

0

..

0

0

0

0

0

0

0

0

0

0

0

0

0

0

"0

0000000

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

"0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

..

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

..

000000

00000000000000000000000

__

0

0

0

0

0

0

0

0.000

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

000

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

000

0

0

00000000

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

00000000

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

00000000000000000000000000000000000000000

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0,0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0000000000000000000000000000000000000000000000000.00

4-4

0

0

0

0

0

0

0

0.00000

4-258
4-261
4-264
4-267
4-267
4-267
4-276
4-280
4-283
4-283
4-289
4-292
4-295
4-298
4-302
4-306
4-310
4-314
4-317
4-320
4-323
4-326
4-329
4-332
4-332
4-338
4-341
4-345
4-348
4-348
4-348
4-348
4-354
4-357
4-361
4-367

c

s::

~National

~

~ Semiconductor

~

o
o

-s::
C

~

r

~

DM54LSOO/DM74LSOO Quad 2-lnput NAND Gates

General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic NAND function.

Supply Voltage
Input Voltage

o

(Note 1)

7V
7V
-65"Ct0150"C

Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table
Y=AB

Dual·in·Line Package
Inputs

B

Y

L
L
H
H

L
H
L
H

H
H
H
L

=

H High Logic Level
L = Low Logic Level
A1

B1

V1

A2

B2

V2

GND

TL/F/6439·'

DM54LSOO (J)

DM74LSOO (N)

4·5

Output

A

Recommended Operating Conditions
Symbol

DM54LSOO

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

V il

Low Level Input
Voltage

10H

High Level Output
Current

10l

Low Level Output
Current

TA

Free Air Operating
Temperature

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2
0.8

-0.4

-0.4

125

V

0

V
mA

8

mA

70

·C·

over recommended operating free air temperature (unless otherwise noted)

Parameter

Min

Typ
(Note 1)

DM54

2.5

'3.4

DM74

2.7

3.4

Conditions

VI

Input Clamp Voltage

Vcc=Min, 11= -18 mA

VOH

High Level Output
Voltage

Vcc=Min
10H= Max
Vll=Max

Low Level Output
Voltage

Vcc=Min
10L= Max
VIH = Min

VOL

0.7

-55

Units

V

4

Electrical Characteristics
Symbol

DM74LSOO

Min

Max
• -1.5

V
V

DM54

0.25

0.4

DM74

0.35

0.5

DM74

0.25

0.4

IOl=4mA
Vcc=Min

Units

V

II

Input Current@Max
Input Voltage

Vcc = Max, VI = 7V

0.1

mA

IIH

High Level Input
Current

Vcc=Max, VI=2.7V

20

/LA

III

Low Level Input
Current

Vcc=Max, VI = 0.4V

los

Short Circuit
Output Current

Vcc=Max
(Note 2)

ICCH

Supply Current With
Outputs High

Vcc=Max

0.8

1.6

mA

ICCl

Supply Current With
Outputs Low

Vcc=Max

2.4

4.4

mA

Switching Characteristics

-.0.36

mA
mA

DM54

-20

-100

DM74

-20

-100

at Vcc = 5V and T A= 25·C (See Section 1 for Test Waveforms and Output Load)
RL=2 kD
C L =15 pF

Parameter

CL=50 pF

Units

Min

Typ

Max

Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

3

5

10

4

8

15

ns

tpHl Propagation Delay Time
High to Low Level Output

3

5

10

4

8

15

ns

Notal: All typicals are at VCC=SV. TA=2S"C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

4-6

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~ Semiconductor

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.....

DM54LS01/DM74LS01 Quad 2·lnput NAND Gates
with Open·Coliector Outputs
General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic NAND function. The opencollector outputs require external pull-up resistors for
proper logical operation.

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

oIiIo

fi)

o....
(Note 1)

7V
7V
7V
-65"C to 150"C

Pull·Up Resistor Equations

RMIN =

Where:

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

VCc!Max) - VOL
IOL - Na (IIIJ
N1 (IOH) = total maximum output high current
for all outputs tied to pull·up resistor
N2 (IIH) = total maximum Input high current for
all inputs tied to pull-up resistor
Na (IIU = total maximum input low current for
all inputs tied to pull-up resistor

Connection 'Diagram

Function Table
Y=AB

Dual-In-Line Package

"

BJ

A'

Inputs
B

Y

L
L

L

H

H
H

L

H
H
H

H

L

H= High Logic Level
L::; Low Logic Level
VI

AI

B1

Y2

A2

B2

GNO

TLlF/6440·1

DM54LS01 (J)

DM74LS01 (N)

4-7

Output

A

Recommended Operating Conditions
Symbol

DM54LS01

Parameter

Min

DM74LS01

Nom

Max

Min

Nom

Max

5

5.5

4.75

5

5.25

Units

Vee

Supply Voltage

V'H

High Level Input
Voltage

V'L

Low Level Input
Voltage
I

0.7

0,8

V

VOH

High Level Output
Voltage

5.5

5.5

V

10L

Low Level Output
Current

4

8

mA

TA

Free Air Operating
Temperature

70

DC

4.5
2

2

-55

Electrical Characteristics

125

V
V

0

over recommended operating free air temperature (unless otherwise noted)

Parameter

Symbol

,

Conditions

Typ
(Note 1)

Min

Max
-1.5

V

100

~A

0.25

0.4

V

0.35

0.5

V,

Input Clamp Voltage

Vee = Min, 1,= -18 mA

leEx

High Level Output
Current

Vee= Min, Vo=5.5V
V'L=Max

VOL

Low Level Output
Voltage

Vee = Min
10L=Max
V,H=Min

DM54
DM74

IOL=4 mA
Vee=Min

DM74

0.25

0.4

,

(

Units

I,

Input Current@Max
Input Voltage

Vee=Max, V,=7V

0.1

mA

I'H

High Level Input
Current

Vee=Max, V,=2.7V

20

p.A

I'L

Low Level Input
Current

Vee=Max, V,=O.4V

leeH

Supply Current With
Outputs High

Vee=Max

lecL

Supply Current With
Outputs Low

Vee=Max

Switching Characteristics

-0.36

mA

0.8

1.6

mA

2.4

4.4

mA

at Vee=5V and TA=25 DC (See Section 1 for Test Waveforms and Output Load)
RL=2 kD

Parameter

CL=15 pF

CL=50 pF

Units

Min

Typ

Max

Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

6

12

20

20

32

45

ns

tpHL Propagation Delay Time
High to Low Level Output

3

7

15

4

10

20

ns

Note 1:

All

typica's are at ,Vee = SV,

TA=2s'e.
4-8

~NaHonal

~. Semiconductor

DM54LS02/DM74LS02 Quad 2·lnput NOR Gates

General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic NOR function.

Supply Voltage
Input Voltage .

(Note 1)
7V
7V

- 65·C to 150·C

Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
ma)(imum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table
Y=A+B

Dual-In-Line Package

Inputs

B

Y

L
L
H
H

L
H
L
H

H
L
L
L

H = High Logic Level
L = Low Logic Level
VI

TL/F/6441-1

DM54LS02 (J)

~M74LS02

(N)

4·9

Output

A

Recommended Operating Conditions
Symbol

DM54LS02

Param~ter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2
0.7

0.8

-0.4

-0.4

-55

125

V

0

V
mA

8

mA

70

·C

over recommended operating free air temperature (unless otherwise noted)

Parameter

Conditions

Min

Typ
(Note 1)

Max

VI

Input Clamp Voltage

Vee = Min, 11= ,18 mA

VOH

High Level Output
Voltage

Vee=Min
IOH=Max
VIL=Max

DM54

2.5

3.4

DM74

2.7

3.4

Low Level Output
Voltage

Vee=Mln
IOL=Max
VIH=Min

.DM54

0.25

0.4

DM74

0.35

0.5

IOL=4mA
Vee = Min

DM74

0.25

0.4

VOL

Units

V

4

Electrical Characteristics
Symbol

DM74LS02

Min

-1.5

Units
V
V

V

II

Input Current@Max
Input Voltage

Vee = Max, VI = 7V

0.1

mA

IIH

High Level Input
Current

Vee=Max, VI=2.7V

20

p.A

IlL

Low Level Input
Current

Vec = Max, VI = 0.4V

'Ios

Short Circuit
Output Current

Vcc=Max
(Note 2)

ICCH

Supply Current With
Outputs High

Vcc=Max

1.6

3.2

mA

ICCL

Supply Current With
Outputs Low

Vcc=Max

2.8

5.4

mA

-0.36

mA
mA

DM54

-20

-100

DM74

-20

-100

Switching Characteristics at Vce = 5V and TA '" 25~C (See Section 1 for Test Waveforms and Output Load)
RL"'2 kO
Parameter

CL=15 pF

CL=.50 pF

Units

Min

Typ

Max

Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

:3

9

13

4

12

18

ns

tpHL Propagation Delay Time
High to Low Level Output

3

5

10

4

8

15

ns

Note 1:

All typical. are at YCC=5Y, TA=25"C.

Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

4-10

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~National

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~ Semiconductor

r-

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-s:.
o

~

DM54LS03/DM74LS03 Quad 2-lnput NAND Gates
with Open-Collector Outputs
General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic NAND function. The opencollector outputs require external pull-up resistors for
proper logical operation.

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

r-

~
w
(Note 1)

7V
7V
7V
-65·Ct0150·C

Pull-Up Resistor Equations
Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safely of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" taDle are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Vcc(Max)-VOL
R
MIN=
IOL-N3 (IIIJ

Where:

Nl (IOH) = total maximum output high current
for all outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for
all inputs tied to pull-up resistor
N3 (11lJ = total maximum input low current for
all inputs tied to pull-up resistor

Function Table

Connection Diagram
Dual·ln·Line Package

Inputs

Al

B1

VI

A2

B2

<,

B

Y

L
L
H
H

L
H
L
H

H
H
H
L

L = Low Lagle Level

TlfF/6344-'

DM54LS03 (J)

A

H = High Logic Level
GND

DM74LS03 (N)

4-11

Output

Reco~mended

Operating Conditions
DM54LS03

Symbol

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

VOH

High Level Output
Voltage

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2
I

Units
V
V

0.8

V

5.5

5.5

V

4

8

mA

70

·C

0.7

-55

Electrical Characteristics
Symbol

DM74LS03

Min

I

125

0

over recommended operating free air temperature (unless otherwise noted)

Parameter

Conditions

Min

VI

Input Clamp Voltage

Vec=Min, 11= -18 rnA

leEx

High Level Output
Current

Vec=Min, Vo=5.5V
VIL = Max

VOL

Low Level Output
Voltage

Vee = Min
IOL=Max
VIH = Min
IOL=4 mA
Vec=Min

Typ
(Note 1)

Max

Units

-1.5

V

100

'p.A
V

DM54

0.25

0.4

DM74

0.35

0.5

DM74

0.25

0.4

II

Input Current@Max
Input Voltage

Vec=Max, VI=7V

0.1

mA

IIH

High Level Input
Current

Vec=Max, VI=2.7V

20

p.A

IlL

Low Level Input
Current

Vec = Max, VI = 0.4V

IceH

Supply Current With
Outputs High

Vec=Max

ICCL

Supply Current With
Outputs Low

Vec=Max

-0.36

mA

0.8

1.6

rnA

2.4

4.4

rnA

-

Switching Characteristics

at Vec=5V and TA=25·C (See Section 1 for Test Waveforms and Output Load).
RL=2 kll
C L =15pF

Parameter

CL=50 pF

Units

Min

,Typ

'Max

Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

6

12

20

20

32

45

ns

tpHL Propagation Delay Time
High to Low Level Output

3

7

15

4

10

20

ns

Note 1:

All typical. are at vee; 5V, TA; 25"C,
I

4·12

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~

roo

DM54LS04/DM74LS04 Hex Inverting Gates

~.

General Description

Absolute Maximum Ratings

This device contains six independent gates each of
which performs the logic INVERT function.

Supply Voltage
Input Voltage

(Note 1)

7V
7V

- 65·C to 150·C

Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual·ln·Line Package

Y=A

T

A6

V6
12

13

14

11

1

Al

VI

,

10

,
A2

V•

•

Input

-{>o-

r£>o-

rI><>2

A.

-t>o-

1>0-

r-i>O-

V,

A'

4

V2

,
Al

H
L

L = Low Logic Level

•

01:

TLlF/6345·1

DM54LS04 (J)

Y

L
H

H = High Logic Level

V,

DM74LS04 (N)

4·13

Output

A

Recommended Operating Conditions
Symbol

DM54LS04

Parameter

Vee
VIH·

Supply Voltage

Vil

Low Level Input
Voltage

10H

High Level Output
Current

IOl

Low Level Output
Current

TA

Free Air Operating
Temperature

Nom

Max

Min

No'm

Max

4.5

5

.5.5

4.75

5

5.25

High Level Input
Voltage

2

2

V

0.8

-0.4

-0.4

mA

8

mA

70

°C

125

0

V

over recommended operating free air temperature (unless otherwise noted)

Parameter

Conditions

Typ
(Note 1)

Min

Max

VI

Input Clamp Voltage

Vee=Min, 11= -18 mA

VOH

High Level Output
Voltage

Vee=Min
10H=Mal<
Vll = Max

DM54

2.5

DM74

2.7

Low Level Output
Voltage

Vee=Min
10l=Max
VIH=Mln

DM54

0.25

0.4

DM74

0.35

0.5

DM74

0.25

0.4

VOL

Units

0.7

-55

,

,

V

4

Electrical Characteristics
Symbol

DM74LS04

Min

IOl=4 mA
Vee = Min

-1.5
I

3.4

Units
V
V

3.4
V

II

Input Current@Max
Input Voltage

Vee = Max, VI = 7V

0.1

mA

IIH

High Level Input
Current

Vee = Max, VI=2.7V

20 ,

f'A

III

Low Level Input
Current

Vee = Max, VI=0.4V

-0.36

mA

los

Short Circuit
Output Current

Vee=Max
(Note 2)

mA

leeH

Supply Current With
Outputs High

Vee = Max

1.2

2.4

mA

leel

Supply Current With
Outputs Low

Vee = Max

3.6

6.6

mA

Switching Characteristics

DM54

-20

, -100

DM74

-20

-100

at Vee = 5V and TA = 25°b (See Section 1 for Test Waveforms and Output Load)
RL=2 kll
CL=15 pF

Parameter

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

3

5

10

tpHl Propagation Delay Time
High to Low Level Output

3

5

10

Nole 1:

All

typicals are at

Min·

Typ

Max

4

8

15

ns

4

8

15

ns

Vee=5V. TA=25'e.

Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

4·14

Units

CL=50 pF

Min

r-----------------------~--------------------------------------'c

3:

~National

U1

~
,....

~ Semiconductor

~
U1

-c
3:

.....

DM54LS05/DM74LS05 Hex Inverters
with Open-Collector Outputs

~

~
o

U1

General Description

Absolute Maximum Ratings

This device contains six independent gates each of
which performs the logic INVERT function. The open·
collector outputs require external pull·up resistors for
proper logical operation.

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

Pull·Up Resistor Equations
RMAX = Vec!Min)-VOH
N1 (IOH)+ N2 (lIH)

7V
7V

- 65·C to 150·C

not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

N1 (IOH) = total maximum output high current
for all outputs tied to pull·up resistor
N2 (IIH) = total maximum input high current for
all inputs tied to pull·up resistor
N3 (11Ll = total maximum input low current for
all inputs tied to pull-up resistor

Connection Diagram

7V

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

Vce (Max) - VOL
RMIN = IOL - N3 (IIIJ

Where:

(Note 1)

Function Table

4-15

, Recommended Operating Conditions
Symbol

Parameter

,

. DM54LS05
Min

Nom

4.5

5

DM74LS05
Max

Min

Nom

Max

5.5

4.75

5

5.25

Units

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

0.7

0.8

V

VOH

High Level Output
Voltage

5.5

5.5

V

10L

Low Level Output
Current

4

8

mA

TA

Free Air Operating
Temperature

70

°C

2

-55

Electrical Characteristics
Symbol

V
V

2

125

0

over recommended operating free air temperature (unless otherwise noted)

Parameter

Conditions

Min

VI

Input Clamp Voltage

Vee=Mln,II=-18mA

ICEX

High Level Output
Current

Vee=Min, V o =5.5V
VIL=Max

VOL

Low Level Output
Voltage.

Vee= Min
10L= Max
VIH=Min
IOL=4mA
Vee=Min

Typ
. (Note 1)

Max

Units

-1.5

V

100

p.A
V

DM54

0.25

0.4

DM74

0.35

0.5

DM74

0.25

0.4

II

Input Current@Max
Input Voltage

Vee = Max, VI = 7V

0.1

mA

IIH

High Level Input
Current

Vee = Max, VI=2.7V

20

p.A

IlL

Low Level Input
Current

Vee = Max, VI=0.4V

leeH

Supply Current With
Outputs High

Vee = Max

le9L

Supply Current With
Outputs Low

Vee= Max

Switching Characteristics

-0.36

mA

1.2

2.4

mA

3.6

6.6

mA

at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL=2 kll
C L =15 pF

Parameter

CL=50 pF

Units

Min

Typ

Max

Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

6

12

20

20

32

45

ns

tpHL Propagation Delay Time
High to Low Level Output

3

7

15

4

10

20

ns

Nole 1:

\

All typical. are at Vee=5V, TA = 25'e.

4-16

r-------------------------------------------------------------,c
s:
~National
~
~ Semiconductor

-s:~c
:;;;!
r

DM54LS08/DM74LS08 Quad 2-lnput AND Gates

~

CD

General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic AND function.

Supply Voltage
Inp)Jt Voltage
Storage Temperature Range .

(Note 1)
7V
7V

- 65·C to 150·C

Note 1:' The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual·ln·Line Package

Y=AB
Inputs

B

Y

L
L
H
H

L
H
L
H

L
L
L
H

H = High Logic Level
L = Low Logic Level
AI

B1

YI

A2

B2

Y2

GND

TLlF/6347·1,

DM54LSOB (J)

DM74LSOB (N)

4·17

Output

A

co

0
en
'...J
"It
.....

:E

C

CO

~
...J
"It

Recommended Operating Conditions
/

Symbol
Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

II)

:E
C

DM74LS08

DM54LS08

Parameter

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V
V

2

2

Units

0.7

0.8

V

,IOH

High Level Output
Current

-0.4

-0.4

mA

IOL

Low Level Output
Current

4

8

mA

TA

Free Air Operating
Temperature

70

·C

-55

Electrical Characteristics
Symbol
VI
VOH

VOL

125

over recommended operating free air temperature (unless otherwise noted)

Parameter

Conditions

. Input Clamp Voltage

0

Min

Typ
(Note 1)

Max
-1.5

Vcc=Mln, 11= -18 mA

High Level Output
Voltage

Vcc=Min
IOH=Max
VIH=Min

DM54

2.5

3.4

DM74

2.7

3.4

Low Level Output
Voltage

Vcc=Min
IOL= Max
VIL=Max

DM54

0.25

0.4

DM74

0.35

0.5

IOL=4mA
Vcc=Min

DM74

0.25

0.4

Units
V
V

V

II

Input Current@Max
Input Voltage

Vcc=Max, VI =7V

0.1

mA

IIH

High Level Input
Current.

Vcc = Max, VI = 2.7V

20

flA

IlL

Low Level Input
Current

Vcc = Max, VI = 0.4V

los

Short Circuit
Output Current

Vcc= Max
(Note 2)

ICCH

Supply Current With
Outputs H,igh

Vcc=Max

2.4

4.8

mA

ICCL

Supply Current With
Outputs Low

Vcc=Max

4.4

8.8

mA

Switching Characteristics

-0.36

mA
mA

DM54

-20

-100

DM74

-20

-100

at Vcc= 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
RL=2 kG
C L =15 pF

Parameter

CL=50 pF

Units

Min

Typ

Max

Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

4,

8

13

6

11

18

ns

tpHL Propagation Delay Time
High to Low Level Output

3

7.5

11

5

11

18

ns

=

=

Note 1: All typical. are at VCC 5V, TA 25"C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

4·18

~National

~ Semiconductor
DM54LS09/DM74LS09 Quad 2-lnput AND Gates
with Open-Collector Outputs
General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic AND function. The open·
collector outputs require external pull·up resistors for
proper logical operation.

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

(Note 1)
7V
7V
7V

- 65·C to 150·C

Pull·Up Resistor Equations
Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings.'The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

R

MIN=

Where:

Vcc(Max)-VOL
IOL-N3 (lIU
N1 (IOH) = total maximum output high current
for all outputs tied to pull-up resistor
N2 (lIH) = total maximum input high curr~nt for
all inputs tied to pull·up resistor
N3 (Ill) = total maximum input low current for
all inputs tied to pull-up resistor

Connection Diagram

Function Table

Dual·ln·Line Package

Y=AB
Inputs

AI

BI

"

DM54LS09 (J)

A'

"

v,

B

Y

L
L
H
H

L
H
L
H

L
L
L
H

H= High Logic Level
L= Low Logic Level
GND

TLlF16348-1

DM74LS09 (N)

4-19

Output

A

Recommended Operating Conditions
Symbol

Parameter

DM54LS09

DM74LS09

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

0.7

0.8

V

VOH

High Level Output
Voltage

5.5

5.5

V

10L

Low Level Output
Current

4

8

mA

TA

Free Air Operating
Temperature

70

·C

2

-55

Electrical Characteristics
Symbol

2

125

V
V

0

over recommended o'peraling free air temperature (unless otherwise noted)

Pirameter

Conditions

Min

VI

Input Clamp Voltage

Vcc=Min,li= -18 mA

ICEX

High Level Output
Current

Vcc=Min, Vo=5.5V
VIH=Min

VOL

Low Level Output
Voltage

Vcc=Min
10L=Max
Vll=Max
IOl=4mA
Vcc=Min

Typ
(Note 1)

Max

Units

-1.5

V

100

p.A
V

DM54

0.25

0.4

DM74

0.35

0.5

DM74

0.25

0.4

II

Input Current@Max
Input Voltage

Vcc = Max, VI = 7V

0.1

mA

IIH

High Level Input
Current

Vcc=Max, VI=2.7V

20

p.A

III

Low Level Input
Current

Vcc=Max, VI =0.4V

ICCH

Supply Current With
Outputs High

Vcc= Max

ICCl

Supply Current With
Outputs Low

Vcc=Max

SWitching Characteristics

-0.36

mA

2.4

4.8

mA

4.4

8.8

mA

at Vcc = 5V and TA = 25·C (See Section 1 for Test Waveforms and

O~tPut Load)

RL=2 kG
Parameter

CL=15 pF

CL=50 pF

Units

Min

Typ

Max

Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

5

13

20

8

20

30

ns

tpHL'Propagation Delay Time
High to Low Level Output

4

10

15

6

18

27

ns

NOte 1: Aillypicals are al VCC=5V, TA=25·C.

4·20

r-------------------------------------------------------------,c

s::

~National

~
r-

~ Semiconductor

en
.....

-s::
o

C

~
r-

DM54LS10/DM74LS10 Triple 3-lnput NAND Gates

en
.....
o

General Description

Absolute Maximum Ratings

This device contains three independent gates each of
which performs the logic NAND function.

Supply Voltage
Input Voltage

(Note 1)

7V
7V
-65·Cto150·C

Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Connection Diagram
Dual·ln·Llne Package

vr

14

C1
IJ

VI

I"

Cl

\0

T9

Y=ABC

,

~

,1J

Inputs

B1

A2

DM54LS10 (J)

"

B

C

Y

X
X

X

L

L

X

X
X

H

H

H
H
H
L

H = High Logic Level
L = Low Logic Level
X = Either Low or High Logic Level

TLlF16349-'

DM74LS10 (N)

4·21

o·

Output

A

L
H
4

I

AI

v,

BJ

\I

o
,..

en
....I

Re~ommended

Operating Conditions

~

:E

-,..
c
o

~

~
:E

c

Symbol
Vcc,

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V

0.8

-0.4

-0.4

mA

'8

mA

70

DC

4
-55

125

0

over recommended operating free air temperature (unless otherwise noted)

Parameter

Conditions

Min

Typ
. (Note 1)

Max
-1.5

Input Clamp Voltage

Vcc=Mln, 11= -18 mA

VOH

High Level Output
Voltage

Vcc=Min
10H=Max
VIL=Max

DM54

2.5

3.4

DM74

2.7

3.4

Low Level Output
Voltage

Vcc=Min
10L=Max
VIH = Min

DM54

0.25

0.4

DM74

0.35

0.5

IOL=4mA
Vcc=Min

DM74

0.25

0.4

Input Current@Max
Input· Voltage

Vcc = Max, VI = 7V

IIH

High Level Input
Current

Vcc=Max, VI=2.7V

IlL

Low Level Input
Current

Vcc = Max, VI = 0.4V

los

Short Circuit
Output Current

Vcb=Max
(Note 2)

ICCH

Supply Current With
Outputs High

Vcc= Max

ICCL

Supply Current With
Outputs Low

Vcc= Max

II

V

0.7

VI

VOL

Units

V

2

2

Electrical Characteristics
Symbol

DM74LS10

DM54LS10

Parameter

Units
V
V

V

0.1

mA

20

I'A

,

Switching Characteristics

-0.36

mA
mA

DM54

-20

-100

DM74

-20

-100

.

0.6

1.2

mA

1.8

3.3

mA

at Vcc = 5V and TA = 25 DC (See Section 1 for Test Waveforms and Output Load)
RL=2 kG

Parameter

CL=15 pF

CL=50 pF

Units

Min

Typ

Max

Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

3

5

10

4

8

15

ns

tpHL Propagation Delay Time
High to Low Level Output

3

5

10

4

8

15

ns

Nole 1:
Nola 2:

All typlcals are at VCC=5V. TA=25"C.
Not more than one output should be shorted at a time. and the duration should not exceed one second.

4·22

.

()

~--------------------------------------------------------------IC

3:
~

~National

~ Semiconductor

r-

CJ)
.....
.....

C

3:
......

)

olio

r-

DM54LS11/DM74lS11 Triple 3-lnput AND Gates

General Description

Absolute

This device contains three independent gates each of
which performs the logic AND function.

Suppl~

Maxim~m

CJ)

.....
.....

Ratings (Note 1)
7V
7V
-65·Ct0150·C

Voltage
Input Voltage
Storage Temperature Range

Note 1: The "Absolute Maximum Aatings" are those values bey~nd
which the safety of the device can not be guaranteed. The device should
not
operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Aecommended Operating Conditions" table will
define the conditions for actual device operation.
''\'

be

Connection Diagram

Function Table

Dual·ln·Line Package

vr

14

C1

13

I',

12

11

2

AI

81

,
.,

10

Afg

Y=ABC

•

Lh-

bJ
1

y,

BJ

C3

•
B2

}25

~

X J:

B

C

Y

X
X
L
H

X
L
X
H

L
X
X
H

L
L
L
H

H = High Logic Level
L= Low Logic Level
X = Either Low or High Logic Level

TLIF/635Q.l

DM54LS11 (J)

Output

Inputs
A

DM74LS11 (N)

4·23

Recommended Operating Conditions
Symbol

Parameter

DM54LS11

Ve~

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

DM74LS11

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

Units
V
V

, V

0.7

0.8

-0.4

-0.4

mA

8

mA

70

·C

4
-55

125

0

Electrical Characteristics .over recommended operating free air temperature (unless otherwise noted)
Symbol

Parameter

Min

Typ
(Note 1)

DM54

2.5

3.4

DM74

2.7

3.4'

Conditions

VI

Input Clamp Voltage

Vee = Min, 11= -18 mA

VOH

High Level Output
Voltage

Vee=Min
IOH= Max
VIH=Min

Low Level Output
Voltage
,

Vee=; Min
IOL=Max
V;L=Max

VOL

IOL=4 mA
Vee = Min

Max
-1.5

Units
V
V

DM54

0.25

0.4

DM74

0.35

0.5

DM74

0.25

0.4

V

II

Input Current@Max
Input Voltage

IIH

.High Level Input
Current

IlL

Low Level Input
Current

Vcc=Max, VI =O.4V

Short Circuit
Output Current

Vcc=Max
(Note 2)

IceH

Supply Current With
Outputs High

Vcc=Max

1.8

3.6

rnA

ICCL

.. Supply Current With
Outputs Low

Vcc=Max

3.3

6.6

mA

los

-

Vee = Max, VI =7V

0.1

mA

Vee = Max, VI=2.7V

20

flA

-0.36

mA
mA

;

DM54

-20

-100

DM74

-20

-100

.

Switching Characteristics

at Vce = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
RL=2 kG

Parameter

CL=15 pF

CL=50 pF

Units

Min

Typ

Max

Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

4

8

13

6

11

18

ns

tpHL Propagation Delay Time
High to Low Lev,,1 Output

3

7.5

11

5

11

18

ns

Note 1: All typical. are at vec=SV, TA=2S·C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

4·24

r---------------------~-------------------------------------------,c

:s:
U1

~National

-'r="

~ Semiconductor

....en

N

C

:s:

DM54LS12/DM74LS12 Triple 3-lnput NAND Gates
with Open-Collector Outputs

~

~
....

N

General Description

Absolute Maximum Ratings

This device contains three independent gates each of
which performs the logic NAND function. The opencollector outputs require external pull-up resistors for
proper logical operation.

Supply Voltage
Input Voltage·
Output Voltage
Storage Temperature Range

Pull-Up Resistor Equations

(Note 1)
7V
7V
7V

- 65·C to 150·C

Note 1: T,he "Absolute Maximum Ratings" are those values beyond
which the safety ot the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Eleqtrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will

Vee (Min) - VOH
R
MAX =
N, (IOH) + N2 (IIH)

define the conditions for actual device operation.

RMIN= Vee (Max)-VOL
10L -N3 (lIU
Where:

=

N, (IOH) total maximum output high current
for all outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for
all inputs tied to pull-up resistor
N3 (IIIJ total maximum input low currerit for
all inputs tied to pull-up resistor

=

Connection Diagram

...
~

Function Table
Y = AB

Dual-In-Line. Package
Inputs

Output

A

B

C

Y

X
X
L

X
L
X

H

H

L
X
X
H

H
H
H
L

H = High Logic Level

=

L Low Logic Level
X = Either Low or High Logic Level
TLIF/6351·1

DM54LS12 (J)

DM74LS12 (N)

4-25 .

Recommended Operating Conditions
Symbol.

DM54LS12

Parameter

DM74LS12

Min

Nom

Max

Min

Nom

Max

Units ,

4.5

5

5.5

4.75

5

5.25

V

Vcc

Supply Voltage

V'H

High Level Input
Voltage

V'L

Low Level Input
Voltage

0.7

0.8

V

VOH

High Level Output'
Voltage

5.5

5.5

V

10L

Low Level Output
Current

4

8

mA

TA

Free Air Operating
Temperature

70

·C

-55

Electrical Characteristics
. Symbol

125

0

over recommended operating free air

Parameter

V

2

2

Conditions

temperatu~e (unless otherwise noted)
Typ
(Note 1)

Min

V,

Input Clamp Voltage

Vcc=Min, 1,= -·18 mA

ICEX

High Level Output
Current.

Vcc=Min, V o =5.5V
V'L= Max

VOL

Low Level Output
Voltage

Vcc=Min
10L=Max
V'H=Min
IOL=4mA
Vcc= Min

Max

Units

-1.5

V

100

/LA
V

DM54

0.25

0.4

DM74

0.35

0.5

DM74

0.25

0.4

..

I,

Input Current@Max
Input Voltage

Vcc=Max, V,=7V

0.1

mA

I'H

High Level Input
Current

Vcc=Max, V,=2.7V

20

/LA

I'L

Low Level Input
Current

Vcc=Max, V,=O.4V

ICCH

Supply Current With
Outputs High

Vcc=Max

ICCL

Supply Current With
Outputs Low

Vcc=Max

Switching Characteristics

-0.36

mA

0.7

1.4

mA

1.8

3.3

mA

,

at Vcc = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
RL=2 kO

Parameter

C L =15 pF

CL=50 pF

Units

Min

Typ

Max

Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

6

12

20

20

32

45

ns

tpHL Propagation Delay Time
High to Low Level Output

3

7

15

4

10

20

ns

Note 1:

All typic a's are at VCC=5V. TA=25·C.

4-26

~--------------------~-------------------------------------------'C

3:
~
roo
.....

~National

~ Semiconductor

-c
Co)

3:
......

DM54LS13/DM74LS13 Dual 4-lnput NAND Gates
with Schmitt Trigger Inputs

.1:>0

roo
.....
Co)

General Description

Absolute Maximum Ratings

This device contains two independent gates each of
which performs the logic NAND function. Each input
has hysteresis which increases the noise immunity and
transforms a slowly changing input signal to a fast
changing, jitter free output.

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

7V
7V
-65'Ct0150'C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

vI'

.,

14

1

Al

13

,
B1

Function Table
Y=ABCD

Dual·ln-Line Package
C>

12

Nt

J

B2

II

4
CI

10

J9

y,
,

Inputs

~
,
DI

C

D

Y

X
X
X

X
X

X

L

L

L

X

X
X

X
X
X

H
H
H
H

H

H

H

l

H = High LogiC Level

t J:

L = Low Logic Level
'X = Either Low or High Logic Level

TLlF/6352·1

DM54LS13 (J)

B

L
H

~

Output

A

DM74LS13 (N)

4-27

Recommended Operating Conditions
Symbol

DM54LS13

Parameter

Min

DM74LS13

Nom

Max

Min

Nom

Max

Units

Vcc

Supply Voltage

4.5

5

5.5

4.75

5

5.25

V

VT+

Positive-Going Input
Threshold Voltage (Note 1)

1.4

1.6

1.9

1.4

1.6

1.9

V

VT_

Negative-Going Input
Threshold Voltage (Note 1)

0.5

0.8

1

0.5

0.8

1

V

0.4

0.8

0.4

0.8

HYS

Input Hysteresis (Note 1)

10H

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

-55

Electrical Characteristics
Symbol

Parameter

V

-0.4

-0.4

mA

4

8

mA

70

·C

125

0

over recommended operating free air temperature (unless otherwise noted)
Min

Typ
(Note 2)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

Max

VI

Input Clamp Voltage

Vcc= Mln,ll= -18 mA

VOH

High Level Output
Voltage

Vcc=Min.
IOH=Max
VI=VT_Min

Low Level Output
Voltage

Vce=Min
10L=Max
VI =VT+Max

IT+

Input Current at
Positive-Going
Threshold

Vec=5V, VI=VT+

-0.14 •

mA

IT_

Input Current at
Negative-Going
Threshold

Vcc=5V, VI=VT_

-0.18

mA

VOL

-1.5

Units
V
V

DM54

0.25

0.4

DM74

0.35

0.5

V

~

II

Input Current@Max
Input Voltage

Vec=Max, VI=7V

0.1

mA

IIH

High Level Input
Current

Vec=Max, VI=2.7V

20

p.A

IlL

Low Level Input
Current

Vec = Max, VI = 0.4V

-0.4

mA

los

Short Circuit
Output Current

Vee = Max
(Note 3)

mA

IceH

Supply Current With
Outputs High

Vcc=Max

2.9

6

mA

ICCL

Supply Current With
Outputs Low

Vcc=Max

4.1

7

mA

DM54

-20

-100

DM74

-20

-100

Nole 1: VCC=5V.
Nole2: All typlcals are at VCC=5V, TA=25·C.
Nole 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.

4-28

Switching Characteristics

at Vee = 5V and TA

=25°C (See Section 1 for Test Waveforms and Output Load)
RL = 2 kO

Parameter

C L =15 pF

C L =50 pF

Units

Min

Typ

Max

Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

5

15

22

8

18

25

ns

tpHL Propagation Delay Time
High to Low Level Output

5

15

22

10

21

33

ns

I

;

4·29

00:1'

~ ~National
~ ~ Semiconductor
c

~

Cii DM54LS14/DM74LS14 Hex Inverters
~ with Schmitt Trigger Inputs
~

c

General Description

Absolute Maximum Ratings

This device contains six independent gates each of
which performs the logic INVERT function. Each input
has hysteresis which increases the noise immunity and
transforms a slowly changing input signal to a fast
changing, jitter free output. .

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

7V
7V

- 65'C to 150'C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
noLbe operated at these limits: The parametric values defined in the

"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will

define the conditions for actual device operation.

Connection Diagram

Function Table

Y=A

Dual·ln·Line Package
Input

Output

A

Y

L

H

H

L

H = High Logic Level
l:;::: Low Logic Level

A1

Y1

A2

Y2

A3

Y3

GN'

TL/F/6353-1

DM54LS14 (J)

DM74LS14 (N)

4·30

Recommended Operating Conditions
Symbol

DM54LS14

Parameter
Min

DM74LS14

Nom

Max

Min

Nom

Max

Units

Vee

Supply Voltage

4.5

5

5.5

4.75

5

5.25

V

VT+

Positive-Going Input
Threshold Voltage (Note 1)

1.4

1.6

1.9

1.4

1.6

1.9

V

VT_

Negative-Going Input
Threshold Voltage (Note 1)

0.5

0.8

1

0.5

0.8

1

V

0.4

0.8

0.4

0.8

HYS

Input Hysteresis (Note 1)

10H

High Level Output
Current

10l

Low Level Output
Current

TA

Free Air Operating
Temperature

-0.4
4
-55

Electrical Characteristics
Symbol

Parameter

V
-0.4

125

0

mA

8

mA

70

'C

over recommended operating free air temperature (unless otherwise noted)
Conditions

Min

Typ
(Note 2)

Max

VI

Input Clamp Voltage

Vee=Min, 11= -18 mA

VOH

High Level Output
Voltage

Vee=Min
10H= Max
Vll = Max

DM54

2.5

3.4

DM74

2.7

3.4

Low Level Output
Voltage

Vee=Min
10l= Max
VIH = Min

DM54

0.25

0.4

DM74

0.35

0.5

IT+

Input Current at
Positive-Going
Threshold

Vee=5V, VI=VT+

-0.14

mA

IT_

Input Current at
Negative-Going
Threshold

Vee=5V, VI=VT_

-0.18

mA

II

Input Current@Max
Input Voltage

Vee = Max, VI = 7V

0.1

mA

IIH

High Level Input
Current

Vee=Max, VI=2.7V

20

iJ. A

III

Low Level Input
Current

Vee=Max, VI =O.4V

-0.4

mA

los

Short Circuit
Output Current

Vee= Max
(Note 3)

mA

leeH

Supply Current With
Outputs High

Vee= Max

8.6

16

mA

leel

Supply Current With
Outputs Low

Vee= Max

12

21

mA

VOL

-1.5

Units

V

DM54

-20

-100

DM74

-20

-100

Note 1: vee; 5V.
Note 2: All typicals are at Vee; 5V, TA; 25°C.
Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.

4-31

V

V

Switching Characteristics

at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL=2 kll
,C L =15pF

Parameter

CL=50 pF

Units

Min

Typ

Max

Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

5

15

22

8

18

25

ns

tpHL Propagation Delay Time
High to Low Level Output

5

15

22

10

21

33

ns

,
\

,.

4-32

~--~-------------------------------------------------------------'C

3:

'
~ Semiconductor

~National

en
~

~
.....

en

o

DM54LS15/DM74LS15 Triple 3-lnput AND Gates
with Open-Collector Outputs

3:

~

~
.....

en

General Description

Absolute Maximum Ratings

This device contains three independent gates each of
which performs the logic AND function. The open·
collector outputs require external pull·up resistors for
proper logical operation.

Supply VO,ltag!!
Inp.ut Voltage
Output Voltage
Storage Temperature Range

(Note 1)

7V
7V
7V
-65·Ct0150·C

Note 1: The "Absolute Maximum Rallngs" are those values beyond
which the safety of the device can not be guaranteed, The device should

Pull·Up Resistor Equations

not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

RMIN= Vcc(Max)-VOL
10L - N3 (lIU

f':J1 (IOH) = total maximum output high current
for all outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for
all inputs tied to pull·up resistor
N3 (lIU'= total maximum input low current for
all inputs tied to pull-up resistor

Where:

Connection Diagram

Function Table

Y=ABC
Dual-In-Line Package

vI'

"

C1
13

11

12

C3
11

1

2
B1

3

A2

10

V3

,

_:i9

4

s
elz

~

B

C

Y

X
X

X

L

L

L

X
H

X
X
H

L
L
L

X

=

H

H High Logic Level
L = Low Logic Level
X = Either Low or High Logic Level

G!:

Tl(F/6354·1

DM54LS15 (J)

A

H

B2

Output

Inputs

Lb-

-1J
AI

"

DM74LS15 (N)

4-33

Recommended Operating Conditions
Symbol

DM54LS15

Parameter

DM74LS15

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units

Vcc

~upply

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage'

0.7

0.8

V

VOH

High Level Output
Voltage

5.5

5.5

V

IOL

Low Level Output
Current

4.

8

rnA

TA

Free Air Operating
Temperature

70

·C

Voltage

2

'2
\

j

-55

Electrical Characteristics

125

0

over recommended operating free air temperature (unless otherwise noted)

Parameter

Symbol

V
V

Conditions

Min

VI

Input Clamp Voltage

Vcc=Min,II=-1BmA

ICEX

High Level Output
Current

Vcc=Mln, Vo=5.5V
VIH=Min

VOL

Low Level Output
Voltage

Vcc=Min
IOL=Max
VIL=Max

DM54
DM74

IOL=4.mA
Vcc=Min

DM74

Typ
(Note 1)

Max

Units

-1.5

V

100

p.A

0.25

0.4

V

0.35

0.5

0.25

0.4

II

Input Current@Max
Input Voltage

Vcc = Max, VI = 7V

0.1

mA

IIH

High Level Input
Current

Vcc=Max, VI=2.7V

20

p.A

IlL

Low Level Input
Current

Vcc = Max, VI = O.4V

, ICCH

Supply Current With
Ouiputs High

Vcc= Max

ICCL

Supply Current With
Outputs Low

Vcc=Max

-0.36

mA

1.8

3.6

mA

3.3

6.6

mA

"-

Switching Characteristics

at Vcc=5V and TA=25·C (See Section 1 for Test Waveforms and Output Load)
RL=2 kll

Parameter

C L =15 pF

-~'nlts

CL=50 pF

Min

Typ

Max

Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

5

13

20

8

20

30

ns

tpHL Propagation Delay Time
High to Low Level Output

4

10

15

6

18

27

ns

Note 1:

All

typical. are at

vcc=SV, TA=2S'C.

4-34

.----------------------------------------------------------,0
~National

s:
C1I

DM54LS20/DM74LS20 Dual 4-lnput NAND Gates

-~s:

.
~ Semiconductor

~

o
......
~

r

General Description

Absolute Maximum Ratings (Note 1)

This device contains two independent gates each of
which performs the logic NAND function.

Supply Voltage
Input Voltage
Storage Temperature Range

~

7V
7V

- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Y=ABCD

Dual·ln·Line Package

V~4

.2

C2
12

13

. T11

"

j2g

V2

Inputs

h
1

2

l

,

3

AI

81

Nt

C1

,

.,

~

A

·B

C

D

Y

X
X
X
L
H

X
X
L
X
H

'X
L
X

L
X
X
X
H

H
H
H
H
L

=

X
H

H High Logic Level
L" Low Logic Level
X Either Low or High Logic Level

X c!:

=

TlIF16355·1

DM54LS20 (J)

Output

8

10

DM74LS20 (N)

4·35

Recommended Operating Conditions
Symbol

DM54LS20

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

-55

0.8

-0.4

-0.4

0

over recommended operating free

Parameter

Typ
(Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

VI

Input Clamp Voltage

Vee = Min, 11= -18 mA

High Level Output
Voltage

Vee=Min
IOH=Max
VIL=Max

Low Level Output
Voltage

Vee= Min
IOL= Max
VIH=Min
IOL=4 mA
Vee=Min

V

V
mA

8

mA

70

·C

al~ temperature (unless otherwise noted)
Min

Conditions

VOH

VOL

0.7

125

Units

V

4

Electrical Characteristics
Symbol

DM74LS20

Min

Max
-1.5

Units
V
·V

DM54

0.25,

0.4

DM74

0.35

0.5

DM74

0.25

0.4

V

II

Input Current@Max
Input Voltage

Vee = Max, VI =7V

IIH

High Level Inpui
Current

Vee = Max, VI=2.7V

IlL

Low Level Input
Current

Vee.= Max, VI = 0.4V

los

Short Circuit
Output Current

Vee = Max
(Note 2)

leeH

Supply Current With
Outputs High

Vee = Max

0.4

0.8

rnA

leeL

Supply Current With
Outputs Low

Vee=Max

1.2

2.2

rnA

Switching Characteristics

,

0.1

mA

20

I'A

-0.36

rnA
rnA

DM54

-20

-100

DM74

-20

-100

at Vee = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
RL=2 kO

Parameter

C L =15 pF

Units

CL=50 pF

Min

Typ

Max

Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

3

5

10

4

8

15

ns

tpHL Propagation Delay Time
High to Low Level Output

3

5

10

4

8

15

ns

Note 1: All typicals are at Vee = 5V, TA = 25°C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

4-36

-'.

r-------------------------------------------------------------,c

s:
CJ'1

~National

~

~ Semiconductor

r-

oo
I\)

-....s:
c

~
~

r-

DM54LS21/DM74LS21 Dual 4-lnput AND Gates

oo
I\)

....

General Description

Absolute Maximum Ratings

This device contains two independent gates each of
which performs the logic AND function.

Supply Voltage
Input Voltage

(Note 1)
7V
7V

- 65°C to 150°C

Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table 'are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table
Y=ABCD

Dual·ln·Line Package
.02

C2

vi:

"

1

13

11

11

"

Ts

10

Inputs

•

b
1

Jc

3

A1

T

Y2

81

.
C1

•
01

~
J6

B

C

D

Y

X
X
X

X
X

X

L

L

L

L
H

X

X
X

X
X
X

H

H

H

L
L
L
L
H

H ~ High Logic Level
L= Low Logic Level

J:

X;;;: Either Low or High Logic Level

TLfFJ6356·1

/
/

DM54LS21 (J)

Output

A

DM74LS21 (N)

4·37

Recommended Operating Conditions
Symbol

DM54LS21

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level Input
Voltage

10H

High Level Output
Current

10l

Low Level Output
Current

TA

Free Air Operating
Temperature

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2
0.7

0.8

-0.4

-0.4

-55

125

V

0

V
mA

8

mA

70

·C

over recommended operating free air temperature (unless otherwise noted)

Parameter

Min

Typ
(Note 1)

DM54

2.5

3.4

2.7

3.4

Conditions

Max

VI

Input Clamp Voltage

VOH

High Level Output
Voltage

Vcc= Min
10H= Max
VIH=Min

DM74

Low Level Output
Voltage

Vcc=Min
10l= Max
Vll = Max

DM54

0.25

0.4

DM74

0.35

0.5

DM74

0.25

0.4

VOL

Units

'V

4

Electrical Characteristics
Symbol

DM74LS21

Min

-1.5

Vcc=M'in,ll= -18 mA

IOl'=4 mA
Vcc=Min

Units
V
V

V

II

Input Current@Max
Input Voltage

Vcc = Max, VI = 7V

0.1

mA

IIH

High Level Input
Current

Vcc=Max, VI=2.7V

20

/LA

III

Low Level Input
Current

Vcc=Max, VI =0.4V

los

Short Circuit
Output Current

Vcc=Max
(Note 2)

ICCH

Supply Current With
Outputs High

Vcc= Max

1.2

2.4

mA

ICCl

Supply Current With
Outputs Low

Vcc=Max

2.2

4.4

mA

Switching Characteristics

-0.36

mA
mA

DM54

-20

-100

DM74

-20

-100

at Vcc=5V and TA=25·C (See Section 1 for Test Waveforms and Output Load)
Rl=2 kll

Parameter

Cl=15 pF

Cl=50 pF

Units

Min

Typ

Max

Min

Typ

Max

tplH Propagation Delay Tim,e
Low to High Level Output

4

8

13

6

11

18

ns

tpHl Propagation Delay Time
High to Low Level Output

3

7.5

11

5

11

18

ns

Note 1: All typicals are at VCC=5V, TA=25"C.
Note 2: Not ,more than one output should be shorted at a time, and the duration should not exceed one second.
4·38

~-----------------------------------------------------------------'C

s:
U1

~·National

oI::ao

~ Semiconductor

r-

en

-s:
I\)
I\)

C

DM54LS221DM74LS22 Dual 4-lnput NAND Gates
with Open-Collector Outputs

.......
oI::ao

r-

~
I\)

General Description

Absolute Maximum Ratings

This device contains two Independent gates each of
which performs the logic NAND function. The opencollector outputs require external pull-up resistors for
proper logical operation.

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

Pull· Up Resistor Equations

Nol. 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

R
_ Vec (Min) - VOH
. MAX - N, (IOH) + N2 (lIH)

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

(Note 1)
7V
7V
7V

-65'Ct0150'C

not be operated at these limits. The parametric values defined in the

"Electrical Characteristics" table are not guaranteed at the absolute

Vcc(Max)-VOL
R
MIN=
IOL - N3 (IIIJ

Where:

N, (IOH) = total maximum output high current
for all outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for
all inputs tied to pull-up resistor
N3 (1 10 = total maximum input low current for
all input,s tied to pull-up resistor'

Connection Diagram

Function Table
Y=ABCD

Dual·ln·Line Package

Vf,4

I
AI

.z

cz

i

B2

C

"

z
BI

IZ

J:

11

'"

YZ

r9

Inputs

8

h

4
CI

.,

5

~
X

B

C

D

Y

'X
X
X
L
H

X
X
L
X
H

X
L
X
X
H

L
X
X
X
H

H
H
H
H
L

H= High LogiC Level
L= Low Logic Level

J:

X = Either Low or High Logic Level

TLlF/6357·'

DM54LS22 (J)

Output

A

DM74LS22 (N)

4-39

"

Recommended Operating Conditions
DM74LS22

DM54LS22
Symbol

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

Low Level Input
, Voltage

Units
V
V

.

0.7

O.~

V

V OH

High Level Output
Voltage

5.5

5.5
,

V

IOL

Low Level Output
Current

4

8

mA

TA

Free Air Operating,
Temperature

70

·C

-55

Electrical Characteristics
Symbol

,.

125

over recommended operating free air temperature (unless otherwise noted)

Parameter

Conditions

Min

VI

Input Clamp Voltage

Vcc=Min,II=-18mA

ICEX

High Level Output
Current

Vcc=Min, Vo=5.5V
VI'L=Max

VOL

Low Level Output
Voltage

Vcc=Min
IOL= Max
VIH = Min
IOL=4 mA
Vcc=Min

Input Current@ Max
Input Voltage

Vcc=Max, VI=7V

IIH

High Level Input
Current

Vcc=Max, VI=2.7V

IlL

Low Level Input
Current

Vcc=Max, VI=O.4V

ICCH

Supply Current With
Outputs High

Vcc= Max

ICCL

Supply Current With
Outputs Low

Vcc= Max

II

0

Typ
(Note 1)

Max

Units

-1.5

V

100

p.A
V

DM54

0.25

0.4

DM74

0.35

0.5

DM74

0.25

0.4
0.1

mA
.'

Switching Characteristics

20

p.A

-0.36

mA

0.4

0.8,

mA

1.2

2.2

mA

at Vcc=5V and TA=25·C (See Section 1 for Test Waveforms and Output Load)
RL=2 kO

Parameter

CL=15 pF

CL=50 pF

Units

Min

Typ

Max

Min

Typ

Max

tpLI-I Propagation Delay Time
Low to High Level Output

6

12,

20

20

32

45

ns

tpHL Propagation Delay Time
High to Low Level Output

3

7

15

4

10

20

ns

Note 1:

!

All typical. are at VCC=5V, TA=25'C,

4·40

~National

~ Semiconductor
DM54LS26/DM74LS26 Quad 2·lnput NAND Gates
with High Voltage Open-Collector Outputs
General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic NAND function. The opencollector outputs require external pull·up resistors for"
proper logical operation.

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

Pull·Up Resistor Equations
R

MAX=

7V
7V

15V

- 65·C to 150·C

Nole 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Vo(Minl-VOH
N, (IOHl+ N2 (lIHl

Where:- N, (IOHl = total maximum output high current
for all outpuis tied to pull-up resistor
N2 (lIHl = total maximum input high current for
all inputs iied to pull-up resistor
N3 (IIU = total maximum input low current for
all inputs tied to pull-up resistor

Connection Diagram

Function Table

Y=AB
Dual-In-Line Package
Inputs
B

Y

L
L
H
H

L
H
L'
H

H
H
H
L

H = High logic level

B1

VI

A2

B2

Y2

GNO

TLlF/635B·'

DM54LS26 (J)

DM74LS26 (N)

4-41

Output

A

L = Low Logic Level
Al

(Note 1l

Recommended Operating Conditions
Symbol

DM54LS26

Parameter.

DM74LS26

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

0.7

0.8

VOH

High Level Output
Voltage

15

15

V

10L

Low Level Output
Current

4

8

mA

TA

Free Air Operating
Temperature

70

·C

2

-55

Electrical Characteristics
Symbol

125

V

0

V

,

over recommended operating free air temperature (unless otherwise
Conditions

Parameter

V

2

Typ
(Note 1)

Min

not~d)

Max

Units

-1.5

VI

Input Clamp Voltage

Vcc=Min,ll= -18 mA

ICEX

High Level Output
Current

Vcc=Min
VIL=Max

Vo= 15V

VOL

Low Level Output
Voltage

Vcc= Min
10L=Max
VIH=Min

DM54

0.25

0.4

DM74

0.35

0.5

IOL=4 mA
Vcc=Min

DM74

0.25

0.4

V

1000

p.A

50

Vo= 12V

V

II

Input Current@Max
Input Voltage

Vcc = Max, VI = 7V

0.1

mA

IIH

High Level Input
Current

Vcc=Max, VI=2.7V

20

p.A

IlL

Low Level Input
Current

Vcc = Max, VI = 0.4V

ICCH

Supply Current With
Outputs High

Vcc= Max

lecL

Supply Current With
Outputs Low

Vee= Max

Switching Characteristics

at Vce

-0.36

mA

0.8

1.6

mA

2.4

4.4

.

mA

=5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)

,

RL=2 kll
Parameter

C L =15 pF

Conditions
Min

Units

Typ

Max

tpLH Propagation Delay Time
Low to Hi.gh Level Output

17

32

ns

tpHL Propagation Delay Time
High to Low Level Output

15

28

ns

Note

1: Aillypicals are at VCC=SV, TA=2S"C.

4-42

~National

~ Semiconductor
DM54LS27/DM74LS27 Triple 3-lnput NOR Gates
General Description

Absolute Maximum Ratings

This device contains three independent gates each of
which performs the logic NOR function.

Supply Voltage
Input Voltage

(Note 1)
7V
7V

- 65·C to 150·C

Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the

"Eleclrical Characlerlslics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Y=A+B

Dual·ln·Line Package
v~

"

v,

C3

B3

.3

Inputs

A

B

Y

L
L
H
H

L
H
L
H

H$
L
L
L

H = High Logie Level
L Low Logic Level

=

"

.2

DM54LS27 (J)

82
TLlFI635~·'

DM74LS27 (N)

. 443

Output

Recommended Operating Conditions
Symbol

DM54LS27

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

Nom

Max

Min

Nom·

Max

4.5

5

5.5

4.75

5

5.25

2

.

2.
0.7

0.8

-0.4

-0.4

-55

125

0

mA

8

mA

70

°c

over recommended operating free air temperature (unless otherwise noted)

Parameter

Conditions

Min

Typ
(Note 1)

Max

Input Clamp Voltage

Vcc=Min, 11= -18 mA

VOH

High Level Output
Voltage

Vcc=Mln
10H= Max
VIL = Max

DM54

2.5

3.4

DM74

2.7

3.4

Low Level Output
Voltage

Vcc=Min
10L=Max
VIH=Min

DM54

0.25

0.4

DM74

0.35

0.5

IOL=4 mA
Vcc=Min

DM74

0.25

0.4

,

V

V

VI

VOL

Units

V

4

Electrical Characteristics
Symbol

DM74LS27

Min

-1.5

Units
V
V

V

II

Input Current@Max
Input Voltage

Vcc = Max, VI = 7V

0.1

mA

IIH

High Level Input
Current

Vcc=Max, VI = 2.7V

20

/LA

IlL

Low Level Input
Current

los

Short Circuit·
Output Current

Vcc= Max
(Note 2)

ICCH

Supply Current With
Outputs High

Vcc=Max

2

4

mA

ICCL

Supply Current' With
Outputs Low

Vcc=Max

3.4

6.8

mA

. Vcc=Max, VI = 0.4V

Switching Characteristics

-0.36

mA
mA

DM54

-20

-100

DM74

-20

-100

at Vcc = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL=2 kO

Parameter
Min

Units

CL=50 pF

CL=15 pI:Typ

Max

Mln

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

,3

9

13

5

12

18

ns

·tpHL Propagation Delay Time
High to Low Level Output

3

5

10

4

8

15

ns

Note

1: All typical. are at vcc=SV, TA=2S·C.

Note 2: Not more than one output should be shorted at a time, and the duration shoul,d not exceed one second.

4·44

r-------------------------------------------------------~---------.c

3:
~
roo
Co)

~National

~ Semiconductor

-c
o

DM54LS30/DM74LS30 a-Input NAND Gate

3:

"""
-'="

General Description

Absolute Maximum Ratings

This device contains a single gate which performs the
logic NAND function.

Supply Voltage
Input Voltage
Storage Temperature Range

~
~

(Note 1)
7V
7V

- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection ,Diagram

Function Table

Y=ABCDEFGH

Dual-In-Line Package
12

11

Inputs

Output

A thru H

Y

All Inputs H

L

One or More
Input L

H

H = High Logic Level
L Low Logic Level

=

,.

!'

F

TLlF/6360·'

DM54LS30 (J)

DM74LS30 (N)

4-45

Recommended Operating Conditions
Symbol

DM54LS30

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

Nom

Max

Min

4.5

5

5.5

4.75 '

2

Nom

Max

5

5.25

2
0.7

0.8

-0.4

-0.4

-55

125

0

mA

70

·C

over recommended operating free air temperature (unless otherwise noted)

Parameter

Conditions

Min

Typ
(Note 1)

Max
-1.5

Input Clamp Voltage

Vcc=Min,ll= -18 mA

High Level 'Output
Voltage

Vcc=Min
'OH=Max
VIL=Max

DM54

2.5

3.4

DM74

2.7

3.4

Low Level Output
Voltage

Vcc=Min
'OL=Max
VIH=Min

DM54

0.25

0.4

DM74

0.35

0.5

'OL=4mA
Vcc=Min

DM74

0.25

0.4

Input Current@Max
, Input Voltage

V

mA

VI

'I

V

8

VOH

VOL

Units

V

4

Electrical Characteristics
Symbol

DM74LS30

.Mln

Units
V
V

V

Vcc=Max, VI=7V

0.1

mA

20

p.A

-0.4

rnA
mA

IIH

High Level Input
Current

Vcc=Max, VI=2.7V

IlL

Low Level Input
Current

Vcc=M~x,

los

Short Circuit
Output Current

Vcc=Max
(Note 2)

ICCH

Supply Current With
Outputs High

Vcc=Max

ICCL

Supply Current With
Outputs Low

Vcc=Max

Switching Characteristics

VI =0.4V
DM54

-20

-100

DM74

-20

-100

.

0.35

0.5

mA

0.6

1.1

mA

at Vcc = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
RL=2 kll
C L =15 pF

Parameter

CL=50 pF

Units

Min

Typ

Max

Min

Typ

Max

'tPLH Propagation Delay Time
Low to High Level Output

4

7

12

5

9

18

ns

tpHL Propagation Delay Time
High to Low Level Output

4

7

15

5

11

20

ns

Nato 1: All typicals are at VCC=5V, TA = 25°C.
Note 2: Not more than one output should be shorted at a time, and the duration sh,?Uld not exceed one second.

4·46

~National

~ Semiconductor
DM54LS32/DM74LS32 Quad 2-lnput OR Gates

General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic OR function.

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

7V
7V

- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are .not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual·ln-Line Package
83

A3

Y=A+B
Inputs

3
A'1

81

Y1

7
A2

82

Y2

L
L

L

L

H

H
H

H

-H
H
H

L

L = Low Logic Level

TL/F/6361·1

DM54LS32 (J)

B

H = High logic Level

GND

DM74LS32 (N)

447

Output

A

Y

Recommended Operating Conditions
Symbol

Parameter

Vcc

Supply Voltage

V,H

High Level Input
Voltage

V,L

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

DM54LS32
Min

Nom

4.5

5

DM74LS32
. Max
5.5

Min

Nom

Max

4.75

5

5.25

2:

2
0.7

0.8

-0.4

-0.4

-

125

V
V

4
-55

Units

0

V
mA

8

mA

70

'c

Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol

'.
Para mater

Conditions

Min

Typ
(Note 1)

Max

V,

Input Clamp Voltage

Vee=Min,I,=-18mA

VOH

High Level Output
Voltage

Vce=Min
IOH=Max
V'H= Min

DM54

2.5

3.4

DM74

2.7

'3.4

Low Level Output
Voltage

Vee=Min
10L=Max
V'L= Max

DM54

0.25

0.4

DM74

0.35

0.5

IOL=4 rnA
Vec=Min

DM74

0.25

0.4

VOL

-1.5

Units
V
V

V

I,

Input Current@Max
Input Voltage

Vce = Max, V, = 7V

0.1

rnA

I'H

High Level Iflput
Current

Vcc=Max, VI=2,-7V

20

/LA

I,L

Low Level Input
Current

Vee=Max, V,=O.4V

los

Short Circuit
OutpU! Current

Vee=Max
(Note 2)

ICCH

Supply Current With
Outputs High

Vee=Max

3.1

6.2

rnA

lecL

Supply Current With
Outputs Low

Vec=Max

4.9

9.8

rnA

-0.36

rnA
rnA

DM54

-20

-100

Dtv174

-20

-100

Switching Characteristics at Vcc = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL=2 kG
, Parameter

CL=15 pF

Units

. CL=50 pF

Min

Typ

Max

Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

3

7

11

4

10

15

ns

tpHL Propagation Deiay Time
High to Low Level Output

3

7

11

4

10

15

ns

Nola 1: All typical. are at VCC=5V, TA=25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

4·48

~National

~ Semiconductor
DM54LS37/DM74LS37 Quad 2-lnput NAND Buffers
General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic NAND function.

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

7V
7V
-65·Cto150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Conn-ection Dia9ram

Function Table

Y=AB
Dual-In-Line Pac;kage
Inputs
B

Y

L
L
H
H

L
H
L
H

H
H
H
L

H = High Logic Level

.,

L = Low Logic Level
B1

V1

.2

B2

Y2

GND

TLlFf6362·1

DM54LS37 (J)

DM74LS37 (N)

4-49

Output

A

Recommended Operating Conditions
Symbol

DM541,S37

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

DM74LS37

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

51

5.25

2

Units
V

2

V

0.7

0.8

High Level Output
Current

-1.2

-1.2

mA

10L

Low Level Output
Current

12

24

mA

TA

Free Air Operating
Temperature

70

·C

-55

Electrical Characteristics
Symbol

125

0

V

over recommended operating free air temperature (unless otherwise noted)

Parameter

Conditions

Min

Typ
(Note 1)

Max

VI

Input Clamp Voltage

Vee = Min, 11= -18 mA

VOH

High Level Output
Voltage

Vee=Min
10H= Max
VIL = Max

DM54

2.5

3.4

DM74

2.7

3.4

Low Level Output
Voltage

Vee = Min·
10L=Max
VIH=Min.

DM54

0.25

0.4

DM74

0.35

0.5

IOL=12mA
Vee=Min

DM74

0.25

. 0.4

VOL

Units

-1.5

V
V

V

II

Input Current@Max
Input Voltage

IIH

High Level Input
Current

IlL

Low Level Input
Current

los

Short Circuit
Output Current

Vee = Max
(Note 2)

leeH

Supply Current With
Outputs High

Vee= Max

0.9

2

mA

lee~

Supply Current With
Outputs Low

Vee=Max

6

12

mA

,

r

Vee = Max, VI = 7V

0.1

Vee = Max, VI=2.7V

20

Vee=Max, VI=0.4V

Switching Characteristics

mA

.

I'A

-0.36

mA
mA

DM54

-20

-100

DM74

-20

-100

at Vee=5V and TA=25·C (See Section 1 for Test Waveforms and Output Load)
RL=667!l

Parameter

CL=45pF

CL=150 pF

Units

Min

Typ

Max

Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

3

10

15

4

13

18

ns

tpHL Propagation Delay Time
High to Low Level Output

3

10

15

4.

16

21

ns

Nole 1:

All typical. are at VCC =5V. TA =25·C.

Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

4-50

r------------------------------------------------------------------.c
s:
C1I
~National

.
~ Semiconductor

.1:00

r-

oo

-s:
Co)

00

C

.....
.1:00

DM54LS38/DM74LS38 Quad 2-lnput NAND Buffers
with Open-Collector Outputs
General. Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic NAND functIon. The open·
collector outputs require external pull-up resistors for
proper logical operation.

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

.Pull-Up Resistor Equations
R

MAX =

(Note 1)

-65·Ct0150·C

are

Note 1: The "Absolute Maximum Ratings"
those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

VcC-

6
7
8
9

2

!

,0

1

3
2

3

•

6

5

•

5

OUTPUTS

DM54LS42A (J)

7

6

D

C

9

A

0

1

2

3

4

5

6

7

9

9

L
L
L
L
L

L
L
L
L
H

L
L
H
H
L

L
H
L
H
L

L
H
H
H
H

H
L
H
H
H

H
H
L
H
H

H
H
H
L
H

H
H
H
H
L

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

L
L
L
H
H

H
H
H
L
L

L
H
H
L
L

H
L
H
L
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

L
H
H
·H
H

H
L
H
H
H

H
H
L
H
H

H
H
H
L
H

H
H
H
H
L

H
H
H
H
H
H

L
L
H
H
H
H

H
H
L
L
H
H

L
H
L
H
L
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

No.

7
10

11

c

:;

18
GND

~

;E

TLlF/6365·1

DM74LS42A (N)

H = High Level
L = Low Level

Logic Diagram
INPUT A

(1~)

INPUTB (14)

Decimal Output

BCD Input

,

8

(1)

A

~OUTPUTO

~

~OUTPUTI

9
4>9

(2)

~OUTPUT2
(4)

~OUTPUT3
~

~,OUTPUT 4
(6)

(13)
INPUTC

C

~OUTPUT5

Lec

~OUTPUT6

(7)

(9)

INPUT D (12)

D

~D

--I

OUTPUT 7
(10)
OUTPUTS

~

L

(11)

~OUTPUT9

TLlF/6365·2

Recommended Operating Conditions
Symbol

DM54LS42

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level Input
Voltage

10H

High Level Output
Current

10l

Low Level Output
Current

TA

Free Air Operating
Temperature

Parameter

Nom

Max

Min

Nom

4.5

5

5.5

4.75

5

2

Max
5.25 .

2

-0.4

0.8

125

0

mA

8

mA

70

·C

over recommended operating free air temperature (unless otherwise noted)
Conditions

Min

Typ
(Note 1)

Max

VI

Input Clamp. Voltage

Vcc= Min, II = -18 mA

VOH

High Level Output
Voltage

Vcc=Min
10H= Max
Vll = Max
VIH=Min

DM54

2.5

3.4

DM74

2.7

3.4

Low Level Output
Voltage

Vcc=Min
10l=Max
Vll=Max
VIH=Min

DM54

0.25

0.4

DM74

0.35

0.5 .

IOl=4 mA
Vcc= Min

DM74

0.25

0.4

VOL

V

V

-0.4

)

4
-55

Units

V

0.7

Electrical Characteristics
Symbol

DM74LS42

Min

-1.5

Units
V
V

V

II

Input Current@Max
Input Voltage

Vcc = Max, VI = 7V

0.1

mA

IIH

High Level Input
Current

Vcc=Max, VI=2.7V

20

/LA

III

Low Level Input
Current

Vcc=Max, VI=O.4V

-0.4

mA

los

Short Circuit
Output Current

Vcc=Max
(Note 2)

mA

Supply Current

Vcc=Max
(Note 3)

Icc

DM54

-20

-100

DM74

-20

-100
7

Note 1: All typicals are at VCC=5V. TA=25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3:

ICC is measured with all outputs open and all inputs grounded.

4-56

13

mA

Switching Characteristics

at Vee = 5V and TA = 25 C (See Section 1 for Test Waveforms and Output Load)

From
(Input)
To
(Output)

Parameter

Q

RL=2 kll
CL =15 pF
Min

Units

CL=50pF

Typ

Max

Min

Typ

Max

tpHL Propagation Delay
Time High to Low
Level Output

A, 8, C, or D
(2 Levels
of Logic)
to Output

14

25

20

30

ns

tpHL Propagation Delay
Time High to Low
Level Output

A, 8, C, or D
(3 Levels
of Logic)
to Output

17

30

23

35

ns

t pLH Propagation Delay
Time Low to High
Level Output

A, 8, C, or D
(2 Levels
of Logic)
to Output

10

25

15

30

ns

tpLH Propagation Delay
Tiine Low to High
Level Output

A, 8, C, orD
(3 Levels
of Logic)
to Output

17

30

23

35

ns

"",

4-57

~

. ..oJ
oo:t

~National

~ Semiconductor
e DM54LS47/DM74LS47, DM54LS48/DM74LS48,
~ DM54LS49/DM74LS49 BCD/7~Segment
:1i Decodersl Drivers

"'=="

c==

~
oo:t

"'c=="

~

..oJ
oo:t
LI)

c==
~
CIJ

..oJ

t!

c==

~:1i
c==

General Description
The LS47 features active-low outputs designed for driving
common-anode LEDs or incandescent indicators directly;
and the LS48 and LS49 feature active-high outputs for driving lamp buffers or common-cathode LEDs. All of the circuits except the LS49 have full ripple-blanking input/output
controls and a lamp test input. The LS49 features a direct
blanking input. Segment identification and resultant displays are shown on a following page. Display patterns for
BCD input counts above nine are unique symbols to authenticate input conditions.

• Lamp-test provision
• Leading Itrailing zero suppression
54LS48/74LS48
• Internal pull-ups eliminate need for external resistors
• Lamp-test provision
• Leading I trailing zero suppression
54LS49/74LS49
• Open-collector outputs
• Blanking input

All of the circuits except the LS49 incorporate automatic
leading arid I or trailing-edge, zero-blanking control (RBI
and RBO). Lamp test (LT) of these devices may be performed at any time when the BII RBO node is at a high logiC
level. All types (including LS49) contain an overriding
blanking input (BI) which can be used to control the lamp
intensity (by pulsing), or to inhibit the outputs.

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
Storage Temperature Range

Features

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

• All circuit types feature lamp intensity modulation
capability
54LS47/74LS47
• Open-collector outputs drive indicators directly
Driver Outputs
Type

Active
Level

Output
Configuration

Sink
Current

low
high
high
low
high
high.

open-collector
2 kO pull-up
open-collector
open-collector
2 kO pull-up
open-collector

12 mA
2mA
4mA
24mA
6mA
8mA

DM54LS47
DM54LS48
DM54LS49
DM74LS47
DM74LS48
DM74LS49

Connection Diagrams

7V
7V
-65·Cto 150·C

Max
Voltage
15
5.5
5.5
15
5.5
5.5

V
V
V
V
V
V

Typical
Power
Dissipation

Packages

35mW
125 mW
40mW
35mW
125mW
40mW

J
J
J
N
N
N

Dual-In-Line Packages
OUTPUTS

OUTPUTS

OUTPUTS

5
B

c

LAMPBII
~ TEST RBO

RB
INPUT

D

A

'"INPiirS'

GND

B
-

C

INPUTS

LAMP

BII

TEST RBO

TL/F/6366-1

54LS47 (J)

74LS47(N)

RB

D

A

GND

tN- PUT
INPUTS

B

C

BLANK- D

TLlFI6366·2

54LS48(J)
4-58

74LS48(N)

A

•

GND

~ING INPUT~ OUTPUT
TLIFI6366·3

54LS49(J)

74LS49(N)

Recommended Operating Conditions
Symbol

Parameter

DM74LS47

DM54LS47

. Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V~e

Supply Voltage

VIH

High Level Input
Voltage
I

VIL

Low Level Input
Voltage

0.7

0.8

V

VOH

High Level Output
Voltage (a thru g)

15

15

V

10H

High Level Output
Current (BI/RBO)

-50

-50

p.A

IOL

Low Level Output
Current (a thru g)

12

24

mA

1.6

3.2

.

Low Level Output
Current (BI/RBO)
TA

Free Air Operating
Temperature

-55

125

V
V

2

2

·C

70

0

'LS47 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol

Parameter

Conditions

VI

Input Clamp Voltage

Vee= Min, II = -18 mA

VOH

High Level Output
Voltage (BI/RBO)

Vee = Min, 10H = Max
V IL = Max, V IH = Min

leEX

High Level Output
Current (a thru g)

Vee = Min, Vo=15V
VIL=Max

VOL

Low Level Output
Voltage

Vee=Min
IOL=Max
VIL=Max
VIH = Min

DM54

IOL=Max/2
Vee= Min

Min

Typ
(Note 1)

2.4

4.2

Max
-1.5

Units
V
V

250

p.A

0.25

0.4

V

DM74

0.35

0.5

DM74

0.25

0.4

II

Input Current@Max
Input Voltage

Vec=Max, VI =7V

0.1

mA

IIH

High Level Input
Current

Vee = Max, VI = 2.7V

20

p.A

IlL

Low Level Input
Current

Vee = Max
VI =O.4V

los

Short Circuit
Output Current

Vee = Max (BI/RBO)

Icc

Supply Current

Vee= Max
(Note 2)

B[lRBO

-1

Others

-0.36
-0.3
7

Note 1: Aillypicals are al Vce=SV. TA=2S'C.
Nola 2: ICC is measured with all oulpuls open and all inpuls al 4.SV.

4·59

mA

-2.

mA

13

mA

'lS47 Switching Characteristics
at Vee = 5V and TA = 25·C: (See Section 1 for Test Waveforms and Output Load)

Parameter

From
(Input)
To
(Output)

RL =6650

CL =15 pF

Units

Typ

Min

Max

tpLH Propagation Delay
Time Low to High
Level Output

A
to
Output

. 100

ns

tpHL Propagation Delay
Time High to' Low
Level Output

A
to
Output

100

ns

tpLH Propagation Delay
Time Low to High
Level Output

RBI
to
Output

100

ns

tpHL Propagation Delay
Time High to Low
Level Output

RBI
to
Output

100

ns

Recommended Operating Conditions
Symbol

Parameter

DM74LS48

DM54LS48
Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units
V

Vee

Supply Voltage

V1H

High Level Input
Voltage

V1L

Low Level Input
Voltage

0.7

'0.8

V

VOH

High Level Output
Voltage (a thru g)

5.5

5.5

V

10H

High Level Output
Current (BI/RBO)

-50

-50

/lA

High Level Output
Current (a thru g)

-100

-100

IOL

TA

2

V

2

Low Level Output
Current (a thru g)

2

6

Low Level Output
Current (BI/RBO)

1.6

3.2

Free Air Operating
Temperature

-55

125

4-60

0

70

mA

·C

'LS48 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol

Parameter

Conditions

Min

Typ
(Note 1)

2.4

4.2

Max
-1.5

VI

Input Clamp Voltage

Vcc= Min, II = -18 mA

VOH

High Level Output
Voltage

Vcc=Min,loH=Max
VIL=Max, VIH=Min

VOL

Low Level Output
Voltage

Vcc=Mln
10L=Max
VIL=Max
VIH=Min

DM54

0.24

0.4

DM74

0.35

0.5

IOL=2 mA
Vcc=Min

DM74

0.25

0.4

.

Units
V
V

ICEX

High Level Output
Current (a thru g)

Vcc=Max, VIH=Min
VIL = Max, Vo=0.85V

II

Input Current@Max
Input Voltage

Vcc=Max, VI=7V
(Any Input except BI/RBO)

0.1

mA

IIH

High Level Input
Current

Vcc=Max, VI=2.7V
(Any Input except BI/RBO)

20

p.A

IlL

Low Level Input
Current

Vcc=Max
VI =0.4V

Short Circuit
Output Current

Vcc=Max
(Note 2)

Supply Current

Vcc=Max
(Note 3)

los

Icc

-1.3

.,...2

V

mA

BIIRBO

-1

Others

-0.36

DM54

-0.3

-2

DM74

-0.3

-2
25

mA

mA

38

mA

i

'LS48 Switching Characteristics
at V cc = 5V and T A = 25°C (See Section 1 for Test Waveforms and Output Load)

Parameter

From
(Input)
To
(Output)

C L =15 pF

Min

RL=4 kG

RL=6 kG

Typ

Typ

Max

Min

Units
Max

tpLH Propagation Delay
Time Low to High
Level Output

A
to
Output

100

ns

tpHL Propagation Delay
Time High to Low
Level Output

A.
to
Output

100

ns

tpLH Propagation Delay
Time Low to High
Level Output

RBI
to
Output

100

ns

tpHL Propagation Delay
Time High to Low
Level Output

RBI
to
Output

100

ns

Note 1: All typicals are at VCC=SV, TA=2S"C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Note 3: ICC Is measured with all outputs open and all Inputs at 4.SV.

4-61

Recommended Operating Conditions
Symbol

DM54LS49

Parameter

DM74LS49

Min

'Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

0.7

0.8

V

VOH

High Level Output
Voltage

5.5

5.5

V

IOL

Low Level Output
Current

4

8

rnA

TA

Free Air Operating
Temperature

70

DC

2

2

V

•
-55

125

V

.,

0

'LS49 Electrical Characteristics
over recommended operating free air temperature (unless otherwise,'noted)
Symbol

Parameter

Conditions

Min

VI

Input Clamp Voltage

Vce=Min, 11= -18 mA

ICEX

High Level Output
Current

Vee=Min, V o =5.5V
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

.

j

Typ
(Note 1)

Max

Units

-1.5

V

250

p.A
V

Vee = Min
IOL= Max
VIL = Max
VIH = Min

DM54

0.25

0.4

DM74

0.35

0.5

IOL=4 mA
Vee=Min

DM74

0.25

0.4

II

Input Current@Max
Input Voltage

Vee = Max, VI=7V

0.1

mA

IIH

High Level Input
Current,

Vee = ,Max, VI = 2.7V

20

p.A

IlL

Low Level Input
Current

Vee = Max, VI = O.4V

Icc

Supply Current

Vee=Max
{Note 2)

-0.36
8

Nole 1: All typlcals are at Vee=SV. TA=2S"e.
Nole 2: ICC is measured with all outputs open and all Inputs at 4.SV.

4-62

15

mA
mA

'LS49 SWitching Characteristics
at Vcc=5V and TA =25'C (See Section 1 for Test Waveforms and Output Load)
From
(Input)
To
(Output)

Parameter

C L =15pF
RL =2 kG

RL=6 kG

Typ

Min

Max

A

tpLH Propagation Delay
Time Low to High
Level Output

to
Output

Min

Typ

Units
Max

100

ns

100

ns

-

A

tpHL Propagation Delay
Time High to Low
Level Output

to
Output

tpLH Propagation Delay
Time Low to High
Level Output

BI
to
Output

100

ns

tpHL Propagation Delay
Time High to Low
Level Output

BI
to
Output

100

ns

~

Output Display
Segment
Identification

Numerical Designations and Resultant Displays

nl 4~ ~L~SUll7U~l&-L_IlL~l Ul I
0

1

2

4

3

7

6

5

9

B

10

12

11

13

14

15

a

'IIlb

·'_Ie
d

TLJF/6366-4

Function Tables
LS47

Decimal

Input.

or
Function

RBI

D

C

B

A

a

H
H

H
X

L

1

L

L
L

L
L

L
H

2

3

H
H

X
X

L
L

L
L

H
H

4
5

H
H

X
X

L
L

H
H

6

H
H

X
X

L
L

9

H
H

X
X

10
11

H
H

12
13
14
15

7
8

Outputs

BI/RBO(l)

LT

Nota

a

b

c

d

e

I

g

H
H

L
H

L
L

L
L

L
H

L
H

L
H

H
H

L
H

H
H

L
L

L
L

H
L

L
L

L
H

H
H

L
L

L
L

L
H

H
H

H
L

L
H

L
L

H
L

H
H

L

L

L

L

H
H

H
H

L
H

H
H

H
L

H
L

L
L

L
H

L
H

L
H

L
H

H
H

L
L

L
L

L
H

H
H

L
L

L
L

L
L

L
H

L
H

L
L

L
L

X
X

H
H

L
L

H
H

L
H

H
H

H
H

H
H

H

L

L
L

L
H

H
H

L
. L

H
H

X
X

H H
H . H

L
L

L
H

H
H

H
L

L
H

H
H

H
L

H
H

L
L

L
L

H
H

X
X

H
H

H
H

L
H

H
H

H
H

H
H

H
-H

L
H

L
H

-L

L
H

H
H

H

(2)

BI

X

X

X

X

X

X

L

H

H

H

H

H

H

H

(3)

RBI

H

L

L

L

L

L

L

H

H

H

H

·H

H

H

(4)

L

L

L

L

L

(5)

LT

L

X

X

X

X

X

H

4-63

L

L

.

Function Tables

(Continued)

LS48
Decimal
or

Function

Inputs

Outputs

a

b

c

d

e

,.

9

H
H

H
L

H
H

H
H

H
L

H
L

H
L

L
L

L
H

H
H

H
H

H
H

L
H

H
H

H
L

L
L

H
H

L
H

H
H

L
H

H
L

H
H

L
H

L
L

H
H

H
H

H

L.

L

H

..t

H
L

H
L
H
H

BIIRBO(I)
LT

RBI

D

C

B

A

0
1

H
H

H
X

L
L

L
L

L
L

L
H

2
3

H
H

X
X

L
L

L
L

H
H

4
5

H
H

X
X

L
L

H
H

L
L

6

H
H

X
X

L
L

H

·H

L

H

H

H

H

H

H

H

H
H

X
X

H
H

L
L

L
L

L
H

H
H

H
H

H
H

H
H

11

H
H

X
X

H
H

L
L

H
H

L
H

H
H

L
L

L
L

L
H

12
13

H
H

X
X

H
H

H
H

L
L

L
H

H
H

L
H

H

14
15

H
H

X
X

H
H

H
H

H
H

L
H

H
H

L
L

7

e
9
10

H
L

L

Note

H

H

L

L

H
H

H

H
L

L
L

H

H
L
H

L
L

H

L

L
L

H

H
H

L
L

L
L

H
L

H
L

H
L

H
L

(2)

H

BI

X

X

X

X

X

X

L

L

L

L

L

L

L

L

(3)

RBI

H

L

L

L

L·

L

L

L

L

L

L

L

L

L

(4)

LT

L

X

X

X

X

X

H

H

H

H

H

H

H

H

(5)

c

d

•

LS49
Decimal
or
Function

H = High level,

Inputs

Outputs

,

9

H
L

H
L

L
L

H
H

Ii
L

L
L

H
H

H
H

L
H

L
L

H
H

H
H

L
H

H
H

H
L

H
L

H
L

H
L

D

C

B

A

BI

•

b

0
1

L
L

L
L

L
L

L
H

H
H

H
L

H
H

H
H

H
L

2
3

L
L

L ·H
L
H

L
H

H
H

H
H

H
H

L
H

4
5

L
L

H
H

L
L

L
H

H
H

L
H

H
L

6
7

L
L

H
H

H
H

L
H

W L
H

H

Hote

e

H

L
L

H

H

H

H

H

H

H

H

H
L

H

H

H
L

H

H

L
L

L

9

H

H

10

H
H

L
L

H
H

L
H

H

H

L
L

L

11

...

L
H

H
H

H
L

L
It

H
H

12
13

H
H

H
H

L
L

L
H

H
H

L
H

H
L

L
L

L
H

L
L

H
H

H
H

14
15

H

H

H
H

H
H

L
H

H
H

L
L

L
L

L
L

H
L

H
L

H
L

H
L

BI

X

X

X

X

L

L

L

L

L

L

L

L

L=

Low level. X

(6)

(7)

= Don't Care

Note 1: BI/RBO is a wire-AND logic serving as blanking input (SI) and/or ripple-blanking output (RBO).
Note 2: The blanking input (81) must be open or held at a high logic level when output functions 0 through
15 are desired. The ripple-blanking input (RBI) must be open or high jf blanking of a decimal zero is not
desired.
Note 3: When a low logic level is applied directly to the blanking input (BI). all segment outputs are H (46.
47); L (48) regardless of the level of any other input.
Note 4: When ripple-blanking input (RBI) and inputs A, B, C, and 0 are at a low level with the lamp test input
high, all segment outputs go H and the ripple-blanking output (RBO) goes to a low level (response
condition).
Note 5: When the blanking input/ripple-blanking output (BI/RBe» is open or held high and a low is applied
to the lamp-test input, all segment outputs are L.
Not. B: The blanking input (81) must be open or held at a high logic level when output functions 0 through
15 are desired.
•
Note 7: When a low logic level is applied directly to the blanking input (81), all segment outputs are low
regardless of the level of any other input.

4·64

~--------------------------------------------I~

Logic Diagrams

(J1
~

LS47

r-

en
~

-c
~

......
~
r-

en
~

......

~

c

~

(J1
~

r-

en

~
(XI

c

~

~

r-

en
~

~(XI

c

~

(J1
~

r-

en
~

9

!:e

c

~

TLIF/6366-5

......
~
r-

en
~

LS48
INPUT A (7)
(13) OUTPUT

•

(12) OUTPUT

b

BIIRBO (4.:.)+-_---;

LAMP·TEST
INPUT

9

RBI
TLlFt6366-6

4·65

m~------------------------------------------------------~

(7).
..... Logic Diagrams

tContinued)

~
.,....
:E

LS49

c

~;1;

:E

c

g
t!

:E

c

~
;1;

.....

:E
c

INPUT D

(4~-I>1it:=~tl~fi~!c

OUTPUT

d

~.....
t!

:E

c
,....

t1)
.....
;1;.

(12) OUTPUT

:E
c

9

TLIFI6366·7

4-66

r------------------------------------------------------------------,c

3:

~National

en
~

~ Semiconductor

r-

~

-....c
3:

:;;!
ren
en

DM54LS51/DM74LS51 Dual 2·Wide 2·lnput, 2·Wide
3·lnput AND·OR·INVERT Gates

....

General Description

Absolute Maximum Ratings (Note 1)

This device contains two independen' combinations of
gates each of which performs the logic ANO-ORINVERT function.

Supply Voltage
Input Voltage
Storage Temperature Range

7V
7V

-65°C to 150·C

Note 1: The "Absolute Maximum Ratings" are l those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values define:d In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual devl?8 operation.

Connection Diagram

Function Table
Y1 = (A1)(B1)(C1) + (D1)(E1)(F1)
Inputs

Dual-In-Line Package

Output

A1

B1

E1

F1

Y1

H
X

H
H
X
X
H
X
X
H
Other Combinations

X
H

L
L
H

C1

D1

Y2 = «A2) (B2) + (C2) (D2))
Inputs
A2
H
X
TLlF/6369·1

DM54LS51 (J)

B2

C2

H
X
X
H
Other combinations

H = High Logic ~evel
L = Low Logic Level
X = Either Low or High Logic Level

DM74LS51 (N)

4-67

Output
D2

Y2

X
H

L
L
H

•

Recommended Operating Conditions
Symbol

DM54LS51

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

High Level Output
Current

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

" VI
VOH

VOL

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2
0.8

-0.4

-0.4

-55

.

125

Units
V
V

0.7

4

0

V
mA

8

mA

70

·C

:

Electrical Characteristics
Symbol

DM74LS51

over recomm"ended operating free air temperature (unless otherwise noted)

Parameter

Conditions

Min

Typ
(Note 1)

Max

Input Clamp Voltage

Vee= Min, 11= -18 mA

High Level Output
Voltage

Vec= Min
IOH= Max
VIL=Max

DM54

2.5

3.4

DM74

2.7

3.4

Low Level Output
Voltage

Vec=Min
10L= Max
VIH= Min

DM54

0.25

0.4

DM74

0.35

0.5

DM74

0.25

0.4

IOL=4 mA
Vce= Min

-1.5

Units
V
V

V

II

Input Current@Max
Input Voltage

Vcc=Max, VI =7V

0.1

mA

IIH

.High Level Input
Current

Vcc = Max, VI = 2.7V

20

p.A

IlL

Low Level Input
Current

Vcc= Max, VI =0.4V

los

Short Circuit
Output Current

Vcc"= Max
(Note 2)

ICCH

Supply Current With
Outputs High

Vcc=Max

0.8

1.6

mA

lecL

Supply Current With
Outputs Low

Vcc=Max

1.4

2.8

mA

Switching Characteristics

at Vcc = 5V

-0.36

mA
mA

DM54

-20

-100

DM74

-20

-100

~nd TA = 25·C

(See Section 1 for Test Waveforms and Output Load)

RL=2 kO
CL=50 pF

CL=15 pF

Parameter

Typ

Units

Min

Typ

Max

Min

tpLH Propagation Delay Time
Low to High Level Output

3

"9

13

4

" 12

18

ns

tpHL Propagation Delay Time
High to Low Level Output

2

6

12

3

8

15

ns

Nole 1: Aillypicals are at VCC = 5V, TA = 25"C.
Note 2: Not more than

on~

output should be shorted at a time, and the duration should not exceed one second.

4-68

Max

r------------------------------------------------------------------.c
~National

~ Semiconductor

3l:
~

.

~
CI1
:f!
c

DM54LS54/DM74LS54 4·Wide AND·OR·INVERT Gates

3l:
~
r-

General Description

Absolute Maximum Ratings (Note 1)

This device contains a combination of gates which per·
forms the logic AND·OR·INVERT function.

Supply Voltage
Input Voltage
Storage Temperature Range

CJ)

~
7V
7V

- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Con~ection

Function Table

Diagram

Y=AB =CDE+ FGH + IJ

Dual·ln·Llne Package

vee
114

I

J

13

H

12

G

F

NC

Inputs

Is

110 . 19

11

I

1
A

2
B

3

e

B

C

D

E

F

G

H

I

J

Y

H

H

X

X

X

X
X
X

X
X
X

H

H

H

X
X

X
X

X
X

X
X

X
X

X
X

H

H

H

X
X
X

X
X
X

X

X

X

H

H

L
L
L
L
H

All other combinations

14

15

D

E

r1&
Y

H = High Logic Level
L = Low Logic Level

17

X= Either Low or High Logic Level

GND

TLIFI637().1

DM54LS54 (J)

Output

A

DM74LS54 (N)

4-69

Recommended Operating Conditions
DM54LS54

Parameter

Symbol
Vcc

Supply Voltage

V,H

High Level Input
Voltage

V,L
/

High Level Output
Current

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

Max

Min

Nom

Max

4.5

5

5.5

4.75

5.

5.25

2

;

2.
0.7

0.8

-0.4

-0.4

mA

8

mA

70

·C

-55

125

0

V

over recommended operating free air temperature (unless otherwise noted)

Parameter

Conditions

Min

Typ
(Note 1)

Max

V,

Input Clamp Voltage

Vcc = Min, If= -18 mA

VOH

High Level Output
Voltage

Vcc=Min
IOH=Max
V,L=Max

DM54

2.5

3.4

DM74

2.7

3.4

Low Lev~1 Output
Voltage

Vcc= Min
IOL= Max
V,H = Min

DM54

0.25

0.4

DM74

0.35

0.5

IOL=4 mA
Vcc= Min

DM74

0.25

0.4

VOL

V
V

4

Electrical Characteristics

. Units

Nom

Low Level Input
Voltage

IOH

Symbol

DM74LS54

Min

-1.5

Units
V
V

V

I,

Input Current@Max
Input Voltage

Vcc=Max, V, =7V

0.1

mA

I'H

High Level Input
Current

Vcc=Max, V,=2.7V

20

/LA

I,L

Low Level Input
Current

Vcc = Max, V,

los

Short Circuit
Output Current

"

=0.4V

Vcc= Max
(Note 2)

-0.36

mA
mA

DM54

-20

-100

DM74

-20

-100

ICCH

Supply Current With.
Outputs High

Vcc=Max

0.8

1.6

mA

ICCL

Supply Current With
Outputs Low

Vcc= Max

1

2

mA

Switching Characteristics

at Vcc = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
RL=2 kO
CL=15 pF

Parameter

CL=50 pF

Units

Min

Typ

Max

Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

5

15

20

6

18

25

ns

tpHL Propagation Delay Time
High to Low Level Output

3

7

13

4

10

18

ns

Notet: All typical. are at VCC=SV. TA=2S"C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

4·70

r------------------------------------------------------------------,c
s:
C1'I
~National

~

~ Semiconductor

~

m

-s:
c

DM54LS55/DM74LS55 2·Wide 4·lnput
AND·OR·INVERT Gates

~
r-

oo
C1'I
C1'I

General Description

Absolute Maximum Ratings (Note 1)

This device contains a combination of gates which perform the logic AND-OR-INVERT function.

Supply Voltage
Input Voltage
Storage Temperature Range

7V
7V

- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Y

Dual-In-Line Package

t

I.

1
A

H
1J

G

1Z

f

E
11

ilO

Tg

v

,

Inputs

>
2

B

J

C

•

D

1:

N

Output

A

B

C

D

E

F

G

H

Y

H

H

H

H

X

X

X

X

X

X

X

X

H H H
All other combinations

H

L
L
H
"

H = High Logic Level
L= Low Logic Level
X= Either Low or High Logic Level

J: J:
TLlF/6371·1

DM54LS55 (J)

=ABCD + EFGH

DM74LS55 (N)

4-71

Recommended"Operating Conditions
Sym

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

,

DM54LS55

Low Level Output
Current

TA

Free Air Operating
Temperature

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2,

2

Input Clamp Voltage

VOH

High Level Output
Voltage

Low Level Output
.voltage

V
V

0.8

-0.4

-0.4

mA

4

8

mA

70

·C

125

0

V

over recommended operating free air temperature (unless otherwise noted)

Parameter

VI

Units

0.7

-55

Electrical Characteristics

VOL

Nom

High Level Output
Current

IOL

Sym

DM74LS55

Min

Conditions

Typ
(Note 1)

MIn;

Max
-1.5

Vee=Min, 11= -18 mA

Units
V

V

Vee=Min
10H=Max
VIL=Max

DM54

2.5

3.4

DM74

2.7

3.4

Vee=Min
10L=Max
VIH = Min

DM54

0.25

0.4

DM74

0.35

0.5

IOL=4 mA
Vee= Min

DM74

0.25

'0.4

V

II

Input Current@Max
Input Voltage

Vee = Max, VI = 7V

0.1

mA

IIH

High Level Input
Current

Vee=Max, VI=2.7V

20

/LA

IlL

Low Level Input
Current

Vee = Max, VI = O.4V

los

Short Circuit
Output Current

Vee=Max
(Note 2)

Supply Current With
Outputs High

Vee = Max

Supply Current With
Outputs Low

Vee = Max

leeH
leeL

-0.36

mA
mA

DM54

-20

-100

DM74

-20

-100
0.4

0.8

mA

0.7

1.3

mA

,

,Switching Characteristics

>'

at Vee = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
RL=2 kll

Parameter

CL=15pF

CL=50 pF

Units

Min,

Typ

Max

Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

3

9

13

4

12

18

ns

tpHL Propagation Delay Time
High to Low Level Output

2

6

12

3

10

18

ns

\

Nole 1: Aillypicals are at Vee = 5V. TA = 25·e.

-

Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

4-72

r-----------------------------------------~------------------,c

s:

~National

~
r-

~ Semiconductor

C/)

.....

DM54LS73A1DM74LS73A Dual Negative-Edge-Triggered
Master-Slave J-K Flip-Flops with Clear
and Complementary Outputs

~
s:
c

~
r-

~

c.:I

l>

General Description

Absolute Maximum Ratings

This device contains two independent negative-edgetriggered J-K flip-flops with complementary outputs.
The J and K data is processed by the flip-flops on the
falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the
transition time of the negative going edge of the clock
pulse. The data on the J and K inputs is allowed to
change while the clock is high or low without affecting
the outputs as long as setup and hold times are not
violated. A low logic level on the clear input will reset
the outputs regardless of the levels of the other inputs.

Supply Voltage
Input Voltage
Storage Temperatur~ Range

.Connection Diagram

Function Table

(Note 1)

7V
7V
- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can nol be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will

define the conditions for actual device operation .

Dual-In-llne Package

Outputs

Inputs

ClR

ClK.

J

K

Q

l
H
H
H
H
H

X

X
l
H

X
l

l

H

Qo

00

I
I
I
I
H

L
H

X

L
H
H
X

Q

L
H
H
L
Toggle

Qo

00

H = High logic level
L = Low Logic Level
X = Either Low or High Logic Level

CLK 1

ClR 1

K1

VCC

ClK 2

ClR 2

J2

TLlF/6372·1

DM54lS73A (J)

DM74lS73A (N)

1 = Negative going edgeof pulse

00 = The output logic level before the Indicated Input conditions were
established.
Toggle = Each output change. to the complement of Its previous level
on each failing edge of the clock pulse.

4-73

•

Recommended Operating Conditions
DM54LS73A
Sym

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level
Input Voltage

IOH

High Level Output
Current

IOl

Low Level Output
Current

DM74LS73A

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4:75

5

5.25

2
0:7

0.8

,

4

V
V

2

-0.4

Units

-0.4
8

V
mA
mA

fClK

Clock Frequency (Note 2)

0

30

0

30

MHz

fC'lK

Clock Frequency (Note 3)

0

25

0

25

MHz

tw

Pulse Width·
(Note 2)

Clock
High

20

20

. Preset
Low

25

25

Clear
Low

25

25

Clock
High

25

25

Preset
Low

30

30

Clear
Low

30

30

tw

Pulse Width
(Note 3)

ns

ns

tsu

Setup Time (Notes 1 and 2)

201

201

ns

tsu

Setup Time (Notes 1 and 3)

251

251

ns

tH

Hold Time (Notes 1 and 2)

01

01

ns

tH

Hold Time (Notes 1 and 3)

51

51

TA

Free ~ir Operating
Temperature

-55

125

Note 1: The symbol (I) Indicates the failing edge of the clock pulse is used for reference.
Nota 2: Cl = t5 pF and Rl = 2 kll.
Note 3: Cl=50 pF and Rl=2 kll.

4-74

0

ns
70

·C

,

Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Sym

Parameter

Conditions

Min

Typ
(Note 1)

rnA

-1.5

VI

Input Clamp Voltage

Vee= Min, II = -18

VOH

High Level Output
Voltage

Vee=Min
10H= Max
VIL=Max
V IH = Min

DM54

2.5

3.4

DM74

2.7

3.4

Low Level Output
Voltage

Vee=Min
10L= Max
VIL=Max
VIH=Min

DM54

0.25

0.4

DM74

0.35

0.5

IOL=4 rnA
Vee=Min

DM74

0.25

0.4

Input Current@Max
Input Voltage

Vee= Max
V I =7V

J, K

0.1

Clear

0.3

Clock

0.4

High Level Input
Current

Vee=Max
VI=2.7V

J, K

20

Clear

60

Clock

80

Low Level Input
Current

Vee=Max
VI =O.4V

J, K .

-0.4

Clear

-0.8

VOL

II

IIH

IlL

Icc

Short Circuit
Output Current

Vee=Max
(Note 2)

Supply Current

Vee = Ma~ (Note 3)

Switching

Ch~racteristics

Parameter

From
(Input)
To
(Output)

fMAX Maximum Clock
Frequency

V
V

V

rnA

/LA

rnA

-0.8

Clock
los

Units

Max

DM54
DM74

-20

-100

-20

-100
4

rnA
rnA

6

at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL=2 kll
C L =15 pF
Min

Typ

30

45

Units

CL=50 pF
Max

Min

Typ

25

40

Max
MHz

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
a

11

20

21

28

ns

tpLH Propagation Delay
Time Low to High
Level Outpul

Clear
to
a

15

20

18

24

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
aorO

15

20

18

24

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
aora

11

20 .

21

28

ns

I

Nole1: Allt~plcals are at Vee = 5V, TA=25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices. with feedback from the outputs.
where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where Vo = 2.25V and 2.125V for DM54
and OM74 series. respectively, with the minimum and maximum limits reduced byone half from their stated values. This is very useful when using automatic
test equipment.
Nole 3: With all outputs open. ICC Is measured with the Q and Q outputs high In turn. At the time of measurement the clock Is grounded.

4·75

~National

~ Semiconductor

DM54LS74A1DM74LS74A Dual Positive-Edge-Triggered
D Flip-Flops with Preset, Clear
and Complementary Outputs
General Description

Absolute Maximum Ratings (Note 1)

This device contains two independent positive·edge·
triggered D flip·flops with complementary outputs. The
information on the D input is accepted by the flip·flops
on the positive going edge of the clock pulse. The trig·
gering occurs at a voltage level and is not directly
related to the transition time of the rising edge of the
clock. The data on the D input may be changed while the
clock Is low or high without affecting the outputs as
long as the data setup and hold times are not violated. A
low logic level on the preset or clear Inputs will set or
reset the outputs regardless of the logic levels of the
other inputs.

Supply Voltage
Input Voltage
Storage Temperature Range

Connection Diagram

7V
7V
- 65"C to 150"C.

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Dual·ln·line Package
Vee

ClR2

D2

ClK2

PRZ

nz

Inputs

a2

outputs

PR

ClR

elK

D

Q

Q

L
H
L
H
H
H

H
L
L
H
H
H

X
X
X

X
X
X
H
l
X

H
L
H·
H
l

l
H
H·
L
H

Qo

00

t
t
L

I

H = High Logic Level '
X = Either Low or High Logic Level
L= Low Logic Level
TL/F/6373-1

DM54lS74A (J)

DM74lS74A(N)

I = Posltive·going Transition
• = This configuration Is nonstable; that Is, It will not persist when either
the preset andlor clear Inputs return to their Inactive (high) level.
00 = The output logic level of 0 before the Indicated Input conditions
were estab)lshed.

4·76

Recommended Operating Conditions
~

Sym

DM74LSi4A

DM54LS74A

Parameter

Min

Nom

Max

Min

Nonl

Max

4.5

5

5.5

4.75

5

5.25

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level
Input Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

fCLK

Clock Frequency (Note 2)

0

25

fCLK

Clock Frequency (Note 3)

0

20

tw

Pulse Width
(Note 2)

Clock
High

18

18

Preset
Low

15

15

Clear
Low

15

15

Clock
High

25

25

Preset
Low

20

20

Clear
Low

20

20

tw

Pulse Width
(Note 3)

2

2

Units
IV
V

0.7

0.8

-0.4

-0.4

V
mA

8

mA

0

25

MHz

0

20

MHz

4

ns

ns

tsu

Setup Time (Notes 1 and 2)

201

201

ns

tsu

Setup Time (Notes 1 and 3)

251

251

ns

tH

Hold Time

01

01

TA

Free Air Operating
Temperature

-55

125

Note 1: The symbol (1) indicates the rising edge of the clock pulse is used for reference.
Note 2:
Note 3:

CL = 15 pF and RL';2 kll.
CL = 50 pF and RL = 2 kG.

4·77

0

ns
70

·C

•

~
~
::E
c
~
~

~
-.:t

Electrical Characteristics
Symbol

Parameter

Conditions

Min

Typ
(Note 1)

Max
-1.5

VI

Input Clamp Voltage

Vcc=Min, 11= -18 mA

VOH "
,

High Level Output
Voltage

Vcc=Min
10H=Max
VIL = Max
VIH= Min

OM 54

2.5

3.4

DM74

2.7

3.4

VOL

Low Level Output
Voltage

Vcc=Min
10L= Max
V IL = Max
VIH=Min

DM54

0.25

0.4

DM74

0.35

0.5

0.25

0.4

Ln

::E
c

over recommended operating free air temperature (unless otherwise noted)

IIH

Input Current@Max
Input Voltage

High Level Input
, Current

Vcc=Max
VI =7V

'Low Level Input
Current

Vcc=Max
VI ;'2.7V

Data

0.1
0.1

Preset

0.2

Clear

0.2

Data

20

Clock

20

Clear

40

Vcc=Max
VI =0.4V

Icc

Short Circuit
, Output 'Current
Supply Current

V

Vr:;.c= Max
(Note 2)

mA

p,A

40

Data

-0.4

Clock

-0.4

Preset

-0.8

rnA

-0.8

Clear
los

V

Clock

Preset
IlL

V

,
DM74

IOL=4 mA
Vcc=Min
II

Units

DM54

-,20

-100

DM74

-20

-100

Vcc= Max (Note 3)

4

8

mA

mA

Note 1: All typicals are at VCC =5V, TA =25'C.
Note 2: Not mor~ than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs, where

shortln9. tha outputs to ground may cause the outputs to change logic stata an equivalent tast may ba performed whare Vo = 2,25V and 2.125V for DM54 and DM74
series, respectively, with the minimum and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment.

Note 3: With all outputs opan, ICC is measured with CLOCK grounded after setting the Q and  B, A< B, and
A B outputs of a stage handling less-significant bits are
connected to the corresponding inputs of the next stage
handling more--significant bits. The stage handling the
least-significant bits must have a high-level voltage applied to the A = B input. The cascading path is implemented with only a two-gate-Ievel delay to reduce overall comparison times for long words.

• Typical power dissipation 52 mW
• Typical delay (4-bit words) 24 ns

U1

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
Storage Temperature Range

=

7V
7V
-65·Ct0150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametriC values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram
Dual-In-Line Package
DATA INPUTS
A3

B2

15

A2

Al

Bl

12

AO

11

BO

14

13

3

4

5

6

7

Is

B3
AB
DATA
INPUT CASCADING INPUTS

A>B

A=B

A
A3 <
A3 =
A3 =
A3 =
A3 =
A3 =
A3 =
A3 =
A3 =
A3 =
A3 =
A3 =
A3 =
H

B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3

Outputs

A2, B2

Al,Bl

AO,BO

A>B

AB

A
A2 <
A2 =
A2 =
A2 =
A2 =
A2 =
A2 =
A2 =
A2 =
A2 =
A2 =

B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2

Al
Al
Al
A1
A1
A1
A1
A1
A1
Al

= HLgh level, L = Low Level. X =

> B1
B1
= B1
= B1
= B1
= Bl
= B1
= 81
= Bl
= B1

<

AD>
AD <
AD =
AD =
AD =
AD =
AD =
AD =

BO
BO
BO
BO
BO
BO
BO
BO

Don't Care

4-97

L
L

X
H
L

X

X

L
L
H
H
L
L

L

L
L
L
H

L

H
L
H
L
L

L
H

Recommended Operating Conditions
Sym

DM54LS85

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage.

VIL

Low Level
Input Voltage

IOH

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

Parameter

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2
0.7

0.8

-0.4

-0.4

-55

125

0

70

'c

over recommended operating free air temperature (unless otherwise noted)
Conditions

Min

Typ
(Note 1)

Max

Vee= Min
10H= Max
VIL = Max
VIH=Min

DM54

2.5

3.4

DM74

2.7

3.4

Low Level Output
Voltage

Vce=Min
IOL= Max
VIL=Max
VIH=Min

DM54

0.25

0.4

DM74

0.35

0.5

IOL=4 mA
Vee=Min

DM74

0.25

0.4

Input Current@Max
Input Voltage

Vee=Max
VI =7V

AB

0.1

Others

0.3

High Level Iflput
,
Current

Vee=Max
VI = 2.7V

AB

20

Others
IlL

Vee=Max
VI =0.4V

Icc

Short Circuit
Output Current

Vee=Max
(Note 2)

Supply Current

Vee = Max (Note 3)

V
V

V

mA

I(A

60

AB

-0.4

mA

-1.2

Others
los

Units

-1.5

Ve e =Min,II=-lBmA

High Level' Output
Voltage

Low Level Input
Current

mA
mA

Input Clamp Voltage

IIH

V

8

VOH

II

V
V

VI

VOL

Units

2

4

Electrical Characteristics
Sym

DM74LS85

Min

DM54

-20

-100

DM74

-20

-100

-

10

mA

20

mA

Notal: All typicals are at Vee=5V, TA=25'e.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: ICC is measured with all outputs open, A= B grounded and all other Inputs at 4.5V.

I

~

4-98

Switching Characteristics

at Vcc=5V and TA=25'C (See Section 1 for Test Waveforms and Output Load)
RL=2 kf!

Parameter

tpLH Propagation Delay Time
Low-to-High Level Output

tpHL Propagation Delay Time
High-to-Low Level Output

CL=15 pF

CL=50 pF

From
Input

To
Output

Number of
Gate Levels

Any A or B
Data Input

AB

1

14

17

2

19

22

3

24

36

27

42

A=B

4

23

40

26

40

AB

1

11

17

2

15

21

3

20

30

26

40

A=B

4

20

30

26

40

Any A or B
Data Input

Min

Typ

Max

Min

Typ

Max

Units
ns

ns

tpLH Propagation Delay Time
Low-to-High Level Output

AB

1

14

22

17

26

ns

tpHL Propagation Delay Time
High-to-Low Level Output

AB

1

11

17

17

26

ns

tpLH Propagation Delay Time
Low-to-High Level Output

A=B

A=B

2

13

20

16

25

ns

tpHL Propagation Delay Time
High-to-Low Level Output

A=B

A=B

2

11

17

17

26

ns

tpLH Propagation Delay Time
Low-to-High Level Output

A>B
orA=B

AB
or A=B

A(1)

>-

'-f

~

'-<

-

(5)

A>B

;-<

A2
B2

AB

A1
B1

(13)

):>(14)

~

~
D-

(2)

(6)

(3)

p(12)
(11)

~

p-

~

~

r

L....---..

AO

BO

A=B

(4)

(10)

~
(9)

(7)

A

Electrical Characteristics
Symbol
IIH

over recommended operating free air temperature (unless otherwise noted)

Parameter

=

High L~vel Input
Current

Vee Max
VI=2.7V

Typ
(Note 1)

Min

Conditions

\

Max

Units

J, K

20

"A

Clear

60

Clock
IlL

los

Icc

Low Level Input
Current

Vee = Max
V I =O.4V

Short Circuit
Output Current

Vee = Max
(Note 2)

Supply Current With

Vee = Max (Note 3)

Switching Characteristics
Parameter

From
(Input)
To
(Output)

'MAX Maximum Clock
Frequency

80

J, K

-0.4

Clear

-0.8

Clock

-0.8

DM54

-20

-100

DM74

-20

-100
4

mA

mA

6

rnA

at Vee=5V and TA=25°C (See Section 1 for Test Waveforms and Output Load)
RL=2 k!l
CL=15 pF
Min

Typ

30

45

CL=50 pF
Max

Min

Typ

25

40

Units
Max
MHz

18.

24

ns

28·

ns

18

24

ns

20

21

28

ns

15

20

18

24

ns

11

20

21

28

ns

tpLH Propagation Delay
Time Low to High
Level Output

Preset
to
a

15

20

tpHL Propagation Delay
Time High to Low
Level Output

Preset
to

11

20

. 21

tpLH Propagation Delay
Time Low to High
Level Output

Clear
to

15

20

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
a

11

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
aorO

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
aorO

Q

Q

,

Nolel: Aillypicals are al vee=Sv, TA=2s·e.
Nole 2: Not more than one output should be shorted al a time, and the duration should not exceed one second. For devices, with feedback from the outputs,
where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where Vo =2.2SV and 2.l2SV for DMS4
and OM74 series, respectively, with the minimum and maximum limits reduced byone half from their stated values. This is very useful when using automatic
test equipment.

Nole 3: With all outputs open, ICC is measured with the Q and Q outputs high in lurn. At the time of measurement the clock is grounded.
,

4·118

r---------------------------------------------------------------,c
3:
~

~National

~ Semiconductor

~
.....

DM54LS1 09A1DM7 4LS1 09A Dual Positive-Edge-Triggered ~
c
3:
J-K Flip-Flops with Preset, Clear,
~
rand Complementary Outputs
en
.....

;

General Descri'ption

Absolute Maximum Ratings

This device contains two independent positive-edgetriggered J-R flip-flops with complementary outputs.
The J and Rdata is accepted by the flip-flop on the risIng edge of the clock pulse. The triggering occurs at a
voltage level and is not directly related to the transition
time of the rising edge of the clock. The data on the J
and K inputs may be changed while the clock is high or
low as long as setup and hold times are not violated. A
low logic level on the preset or clear inputs will set or
reset the outputs regardless of the logic levels of the
other inputs.

Supply Voltage
Input Voltage
Storage Temperature Range

Connection Diagram

vr

JZ

15

16

14

I

L
1J

"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

t-

r--

'-c5-h

P12

1Z

11

I

I
I'

CLKt

PHI

J1

"

DM54lS109A (J)

•

10

~

I'

I
J,6

l'.,

PR

CI,.R

ClK

J

K

Q

l
H
L
H
H
H
H
H

H
l
L
H
H
H
H
H

X
X
X

X
X
X
L
H
L
H
X

X
X
X
L
L
H
H
X

H
l
L
H
H*
H*
L
H
Toggle

I
I
I
I
L

00

Q

00

H

L

00

00

H = High Logic Level
GNO

"

TLIFI6368-1

DM74lS109A(N)

Outputs

Inputs
liz

I--

'---

J'

Z

.z

.-Lto-

r------,
I

CLRl

elK2

L

7V
7V
-65·Cto 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which" the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the

Dual-In-line Package

eli, 2

(Note 1)

=

L Low Logic Level
X = Either Low or High Logic Level

I = Rising Edge of Pulse
* =This configuration is nonstable; that is, it will not persist when
preset and/or clear Inputs return to their inactive (high) state.
00 = The output logic level of Q before the indicated Input conditions

were established.
Toggle = Each output changes to the complement of Its previous level
on each active transition of the clock pulse.

4-119

Recommended Operating Conditions
Symbol,

DM54LS109A

Parameter

DM74LS109A

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

-0.4,

IOL

Low Level Output
Current

4

fCLK

Clock Frequency (Note 2)

0

25

fCLK

Clock Frequency (Note 3)

0

20

tw

Pulse Width
(Note 2)

Clock
High

18

18

Preset
Low

15

15

Clear
Low

15

15

Clock
High

25

25

Preset
Low

20

20

Clear
Low

20

20

Data
High

301

301

Data
Low

201

201

Data
High

351

351

Data
Low

251

251

tw

tsu

tsu

tH

Pulse Width
(Note 3)

Setup Time
(Notes 1 and 2)

Setup Time
(Notes 1 and 3)

Parameter

0.8

-

01
125

mA

8

mA

0

25

MHz

0

20

MHz
ns

ns

,

ns

\

ns

ns

0

70

'C

over recommended operating free air temperature (unless otherwise 'noted)
Min

Conditions

Typ
(Note 1)

Max
-1.5

VI

Input Clamp Voltage

Vcc=Min, 11= -18 mA

VOH

High Level Output
Voltage

Vcc=Min
IOH=Max
VIL=Max
VIH=Min

DM54

2.5

3.4

DM74

2.7

3.4

Low Level Output
Voltage

Vcc=Min
IOL= Max
VIL = Max
VIH=Min

DM54

0.25

0.4

DM74

0.35

0.5

D,M74

0.25

0.4

VOL

V

-0.4

01

Free Air Operating
-55
Temperatu're
Notel: The symbol 

6

4

-~c
3:

-0.8

Clock
los

en
.....
.....

~

;::

~ National

~ ~ Semiconductor
~

:IE

c

DM54LS114A1DM74LS114A
..- Dual Negative-Edge-Triggered
U)
.... Master-Slave J-K Flip-Flops with Preset,
:i Common Clear, Common Clock and
:IE
c Complementary Outputs

3..-

General Description

Absolute Maximum Ratings (Note 1)

This device contains two negatlve-edge-trlggered J-K
flip-flops with complementary outputs. The J and K data
is processed by the flip-flops on the failing edge of the
clock pulse. The clock triggering occurs at a voltage
·Ievel and Is not directly related to the transition time of
the neg~tive going edge of the clock pulse. Data on the
J and K inputs can be changed while the clock Is high or
low without affecting the outputs as long as setup and
hold times are not violated. A low logic level on the
preset or clear Inputs will set or reset the outputs
regardless of the logic levels of the other inputs.

Supply Voltage
Input Voltage
Storage Temperature Range

Connection Diagram

7V
7V

- 65·C to 150·C

Not. 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Dual-In-Line Package
11

14

1

P.'

JZ

]: cr·" T..

~
.....

L--

~
"-

a, ,

,

I"

iiz

Inputs

8

j-

"--<

r'-r~

1

cl~

'--

'---y-

--,

Z
JI

},J

p~:

1,5

JIB

G!:

TLlF/6384·1

DM54LS114A (J)

DM74LS114A(N)

Outputs

PR

CLR

CLK

J

K

Q

Q

L
H
L
H
H
H
H
H

H
L
L
H
H
H
H
H

X
X
X

X
X
X
L
H
L
H
X

X
X
X
L
L
H
H
X

H
L
H*

L
H
H*

00

00

I
I
I
I
H

H
L
L
H
Toggle

00

00

H= High Logic Level
L = Low Logic Level
X = Either Low or High Logic Level
I = Negative Going Edge of Pulse
• = this configuration Is nonstable; that Is, It will not persist when,
preset andlor clear inputs return to their inactiVe (high) level.
00 = The output logic level of before the indicated Input conditions
were established.
Toggle= Each output changes to the complement of lis previous,level
on each failing edge of the clock pulse.

a

4-128

Recommended Operating Conditions
DM54LS114A
Symbol:

Parameter

DM74LS114A

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

fCLK

Clock Frequency (Note 2)

0

30

fCLK

Clock Frequency (Note 3)

0

25

tw

Pulse Width
(Note 2)

Clock
High

20

20

Preset
Low

25

25

25

25

Clock
High

25

25

Preset
Low

30

30

Clear
Low

30

30

tw

Pulse Width
(Note 3)

0.7

O.B

-0.4

-0.4

-

V
mA

8

mA

0

30

MHz

0

25

MHz

4

Clear
Low

V
V

2

2

Units

ns

ns

tsu

Setup Time (Notes 1 and 2)

201

201

ns

tsu

Setup Time (Notes 1 and 3)

251

251

ns

tH

Hold Time (Notes 1 and 2)

01

01

ns

tH

Hold Time (Notes 1 and 3)

51.

51

TA

Free Air Operating
Temperature

-55

125

ns

0

70

·C

Not. 1: The symbol (I) indicates the lalling edge of the clock pulse Is used for reference.
Not. 2: CL= 15 pF and RL=2 kn.
Not. 3: CL = 50 pF and RL = 2 kn.

..

Electrical Characteristics
Symbol
VI
VOH

VOL

Parameter
Input Clamp Voltage

over recommended operating free air temperature (unless otherwise noted)
Conditions

Min

Typ
(Note 1)

Max
-1.5

Vce= Min, II = -18 mA

High Level Output
. Voltage

Vec=Min
iOH=Max
VIL=Max
VIH = Min

DM54

2.5

3.4

DM74

2.7

3.4

Low Level Output
Voltage

Vcc=Min
IOL=Max
VIL = Max
VIH=Min

,DM54

0.25

0.4

DM74

0.35

0.5

IOL=4mA
Vec=Min

DM74

0.25

0.4

4-129

Units
V
V

V

Electrical Characteristics

(Continued)
over recommended operating free air temperature (unless otherwise noted)

Symbol
II

IIH

Parameter
Input Current@Max
Input Voltage

Vcc=Max
VI=7V

High Level Input
Current

Vcc= Max
VI=2.7V

Typ
(Note 1)

Min

Conditions

los

Icc

Low Level Input
Current

Vcc=Max
VI =0.4V

Short Circuit
Output Current

Vcc=Max
(Note 2)

Supply Current With

Vcc = Max (Note 3)

Switching Characteristics
Parameter

Units
mA

J, K

0.1

Clear

0.6

Preset

0.3

Clock

O.B
p.A

J, K

20

Clear

120

Preset

60

,

160

Clock
IlL

Max

J, K

-0.4

Clear

-1.6

Preset

-0.8

Clock

-1.6

mA

DM54

-20

-100

DM74

-20

-100
4

mA

mA

6

at Vcc=5V and TA=25°C (See Section 1 for Test Waveforms and Output Load)

From
(Input)
To
(Output)

RL=2 kn
CL=15 pF

fMAX Maximum Clock
Frequency

Min

Typ

30

45

CL=50 pF
Max

Min

Typ

25

40

Units
Max
MHz

tpLH Propagation Delay
Time Low to High,
Level Output

Preset
io
a

15

20

18

24

ns

tpHL Propagation Delay
,Time High to Low
Level Output

Preset
to

11

20

21

2B

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clear
to

15

20

1B

24

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
a

11

20

21

2B

ns

tPLH Propagation Delay
Time Low to High
Level Output

Clock
to
aorO

15

20

1B

24

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
aorO

11

20

21

2B

ns

Q

Q

Notal: All typlcals are at VCC;5V, TA;25·C.
I

Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs,
where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where Va = 2.25V and 2.125V for DM54
and DM74 series, respectively. with the minimum and maximum limits reduced by one half from their stated values. This Is very useful when using automatic

test equipment.
Note 3: With all outputs open, ICC Is measured with the

Q

and Q outputs high In turn. At the time of measurement the clock Is grounded.
4·130

'
~ Semiconductor
~National

DM54LS1221DM74LS122 Retriggerable One-Shot with
Clear and Complementary Outputs
General Description
The DM54174LS122 is a retriggerable monostable multivibrator featuring both positive and negative edge triggering with complementary outputs_ An internal 10 kll
timing resistor is provided for design convenience minimizing component count and layout problems. This
device can be used with a single external capacitor. The
'LS122 has two active-low transition triggering inputs(A),
two active-high transition triggering inputs (8), and a
CLEAR input that terminates the output pulse width at a
predetermined time independent of the timing components. The (CLR) input also serves as a trigger input
when it is pulsed with a low level pulse transition (-u-).To
obtain optimum and trouble free operation please read
operating rules and NSC one-shot application notes
carefully and observe recommendations.

Features
• DC triggered from active-high transition or active:low
transition inputs
•
•
•
•

Retriggerable to 100% duty cycle
Over-Riding clear terminates output pulse
Internal 10 kll timing resistor
TIL, DTL cOmpatible

Connection Diagram

• Compensated for Vcc and temperature variations
• Input clamp diodes

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

vcc

HC

Functional Description
The basic output pulse width is determined by selection
of the internal resistor RINT or an external resistor (Rx)
, and capacitor (C x ). Once triggered the output pulse
width may be extended by retgriggering the gated activelow (A) transition inputs or the active-high transition (8)
'inputs orthe CLEAR input. The output pulse width can be
reduced or terminated ,by overriding it with the active-low
CLEAR input.
'

8
RIHT

1
Qt--

CLR

12

3
B1

14
B2

outputs

Inputs

CEXT

1

A2

- 65·C to 150·C

Function Table

114 113 112 111

A1

7V
7V

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at th~ absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

, Dual-In-Line Package
REXTI
CEXT

5

CLEAR

A1

A2

81

82

Q

Q

L

X

X

X
X
X

H

H

X
X

X
X

L
L
L
L

H
H
H
H
H
H
H

L
L

X
X
X
X

X
X
X

X
X

L
L

H

I
I

H
H
H
H
-u-u-u-u-u-u-u-u-u-

I
I

CLR

I
I

H

L

X

X

L

L

X

I

L
H

H

t

JL.

I

H

JL.

H
H
H
H
H
H

t

JL.

H
H
H
H
H

JL.

TlIF/6385·1

DM54LS122 (J)

(Note 1)

H = High Logic Level
L = Low logic Level

DM74LS122 (N)

X == Can Be Either Low or High Level

t = Positive Going Transition
I ::: Negative. Going Transition
JL. '= A Positive Pulse

-u- = A Negative

4-131

Pulse

JL.

J"L

JL.
JL.
JL.

Recommended Operating Conditions
Symbol
Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level
Input Voltage

10H

High Level Output
Current

IOL

Low Level Output
Current

tw

Pulse Width

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

0.8

-0.4

-0.4
8

40

40

Aor B
Low

. 40

40

Clear
Low

40

CEXT

External Timing
Capacitance

CWIRE

Wiring Capacitance
at REXT/CEXT Terminal

TA

Free Air Operating
Temperature

.

5

180

V
mA
mA
ns

5

260
No Restriction

50
-55

V

40

No Restriction

Electrical Characteristics

125

0

k!l
I'F

50

pF

70

'C

over recommended operating free air temperature (unless otherwise noted)
Conditions

Min

VI

Input Clamp Voltage

Vcc = Min, 11= - 18 mA

VOH

High Level Output
Voltage

Vcc=Min
10H= Max
VIL=Max
VIH = Min

Low Level Output
Voltage

Vcc= Min
10L=Max
VIL=Max
VIH = Min

VOL

0.7

Aor B
High

Units

V

2

4

External ~iming
Resistor

Parameter

Min

2

REXT

Symbol

DM74LS122

DM54LS122
Parameter

IOL=4 mA
Vcc= Min

Typ
(Note 1)

Max
-1.5

DM54

2.5

3.4

DM74

2.7

3.4

Units
V
V

DM54

0.25

0.4

DM74

0.35

0.5

DM74

0.25

0.4

V

II

Input Current@Max
Input Voltage

Vcc = Max, VI = 7V

0.1

mA

IIH

High Level Input
Current

Vcc=Max, VI=2.7V

20

I'A

IlL

Low Level Input
Current

Vcc = Max, VI = 0.4V

-0.4

mA

los

Short Circuit
Output Current

Vcc= Max
(Note 2)

mA

Supply Current

Vcc=Max
(Notes 3, 4 and 5)

Icc

DM54

-20

-100

DM74

-20

-100
6

4·132

11

mA

Switching Characteristics
Parameter

From
(Input)
to
(Output)

at Vcc=5V and TA=25°C (See Section 1 for Test Waveforms and Output Load)
RL=2 kO
C L =15 pF
CEXT=O pF, REXT=5 kO
Min

Typ

Max·

CL=15 pF
CEXT=1000 pF, REXT= 10 kO
Min

Typ

Units

Max

tpLH Propagation Delay
Time Low to High
Level Output

A
to
Q

22

33

ns

tpLH Propagation Delay
Time Low to High
Level Output

B
to
Q

29

44

ns

tpHL Propagation Delay
Time High to Low
Level Output

A
to

30

45

ns

tpHL Propagation Delay
Time High to Low
Level Output

B
to

37

56

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clear
to

30

45

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
Q

18

27

ns

tWQ(Min) Minimum Width
of Pulse at
Output Q

Aor B
to
Q

116

200

ns

tW(OUI) Output
Pulse Width

Aor B
to
Q

Q

Q

Q

4

4.5

5

p's

Nota 1: All typlcals are at VCC=5V, TA=25'C.
Not. 2: Nol more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: Quiescent ICC I. measured (after clearing) with 2.4V applied to all clear and A Inputs, B Inputs grounded, all outputs open, CEXT = 0.02 ,F, and
REXT=25 kll.
Nota 4: ICC Is measured in the triggered state with 2.4V applied to all clear and B Inputs, A inputs grounded, all outputs open, CEXT = 0.02 ,F, and
REXT=25 kll.
Not. 5: With all outputs open and 4.5V applied to all data and clear Inputs, ICC Is measured after a momentary ground, then 4.5V Is applied to the clock.

,.
Operating Rules
1. To use the Internal 10 kO timing resistor, connect the
RINT pin to VCC.

bonate, or polystyrene capacitors. For large time
constants use solid tantalum or special aluminum
capacitors. If the timing capacitors have leakages
approaching 100 nA or If stray capacitance from
either terminal to ground Is greater than 50 pF the
timing equations may not represent the pulse width
the device generates.

2. An external resistor (Rx) or the Internal resistor (10
kO) and an external capacitor (Cx) are required for
proper operation. The value of Cx may vary from 0 to
any necessary value. For small time constants use
high-quality mica, glass, polypropylene, polycar-

4-133

Operating Rules

(Continued)

3. The pulse width is essentially determined by external
timing components Rx and Cx . For Cx < 1000 pF see
Figure 1; design curves on Twas function of timing
components value. For Cx »1000 pF the output is
defined as:

6. The retriggerable pulse width is calculated as shown
below:
T=Tw+ tpLH = 0.50 X Rxx Cx+ tpLH
The retriggered pulse width is equal to the pulse
width plus a delay time period (Figure 4).

Tw= KRxCx
where [Rx is in kill
[Cx is in pF]
[Tw is in nsl

INPUT

.OUTPUT

K~0.37

--.J

FIGURE 4
TL/F/6385·5
7. Output pulse width variation versus Vce and operation
temperatures: Figure 5 depicts the relationship between pulse width variation versus Vee; and Figure 6
depicts pulse width variation versus temperatures.
10
Rm=10K
CEXT = 1ODD pF
TA=25'C
!

..'"
w
Z

"'"~

---

--

-5

TLlF/6385·2

FIGURE 1

~

~

Cm (pFI

-10

4

The K factor is not a constant, but, varies with Cx. See
Figure 2.

4.5,

5.5
Vee (V)

TL/F/6385.£

FIGURE 5
100 ~F

10

. +A~~5~d
Vee=5.0V

10 ~F

REXT= 10K
CEXT= 1000 pF
Vee=5.0V

1 ~F

w

Z
'"
...'"cr:

8 0.1 ~F
"

~

10' pF

I -V"""

~

10' pF

-'5

--r--..
I
I

10 2 pF
10 pF

o

1-.2

.4

.6

-10
-60 - 3D 0 3D 60 90 120 150
AMBIENT TEMPERATURE ('C)

.8 1.01.2 1.4 1.6

"K" COEFFICIENT

FIGURE2

TLlF16385·3

FIGURE 6

5. To obtain variable pulse width by remote trimming,
the following circuit is recommended:

RX

PIN(13)~~

9. Vee and ground wiring should conform to good hlghfrequency standards and practices so that switching
transients on the Vec and ground return leads do not
cause interaction between one-shots. A 0.011'F to 0.10
I'F bypass capacitor (disk ceramic or monolithic
type) from Vee to ground is necessary on each
·devlce. Furthermore, the bypass capacitor should be
located as close to the Vee-pin as space permits.

Rremote

PIN (11)T

Vee

FIGURE 3

TLIF/6385·7

8. Under any operating condition ex and Rx must be
kept as close to the one-shot device pins as possible
to minimize stray capacitance, to reduce noise pickup, and to reduce I-R and Ldi/dt voltage developed
along their connecting paths. If the lead length from
ex to pins (13) and (11) is greater than 3 cm, for example, the output pulse width might be quite different
from values predicted from the appropriate equations. A non-inductive and low capacitive path is
necessary to ensure complete discharge of ex in
each cycle of its operation such that the output pulse
width will be accurate.

4. The switching diode required for most TIL one-shots
when using an electrolytic timing capacitor is not
needed for the 'LS122 and should not be used.

ex

._-

TL/F/6365-4

* For further detailed device characteristics and output performance

Note: "Rremote;' should be as close to the device pins as possible.

please refer to the NSC one-shot application note AN·3G6.

4-134

c

s::

~National

~
r-

~ Semiconductor

C/)

.....

DM54LS123/DM74LS123 Dual Retriggerable One·Shot
with Clear and Complementary Outputs

-s::

General Description

~
.....

N

Co)

C

~

N

The DM54/74LS123 is a dual retriggerable monostable
multivibrator capable of generating output pulses from a
few nano-seconds to extremely long duration up to 100%
duty cycle. Each device has three inputs permitting the
choice of either leading edge or trailing edge triggering.
Pin (A) is an active-low transition trigger input and pin (8) is
an active-high transition trigger input. The clear (CLR) input terminates the output pulse at a predetermined time
independent of the timing components. The (CLR) input
also serves as a trigger input when it is pulsed with a low
level pulse transition (-u-). To obtain the best trouble free
operation from this device please read the operating rules
as well as the NSC one-shot application notes carefully
and observe recommendations.

Co)

• DTL, TTL compatible
• Input clamp diodes

Absolute Maximum Ratings

(Ncite 1)

7V
7V
- 65"C to 150·C

Supply Voltage
Input Voltage
Storage lemperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Functional Description

• DC triggered from active-high transition or active-low
transition inputs
• Retriggerable to 100% duty cycle
• Compensated for Vee and temperature variations
• Tri~gerable from CLEAR input

The basic output pulse width is determined by selection of
an external resistor (Rx) and capacitor (C x). Once triggered,
the basic pulse width may be extended by retriggering the
gated active-low transition or active-high transition inputs
or be reduced by use of the active-low or CLEAR input. Retriggering to 100% duty cyle is possible by application of an
input pulse train whose cycle time is shorter than the output
cycle time such that a continuous "HIGH" logic state is
maintained at the "0" output.

Connection Diagram

Function Table

Features

Dual-In-Line Package
RexTI
CeXT CeXT
VCC
1
1

01

14

Q2

CLR2

B2
10

13

o

9

CLR

o

CLR

Outputs

Inputs

A2

CLEAR

A

B

Q

Q

L
X
X
H
H

X
H
X
L

X
X
L

L
L
L

H
H
H

t

JL

Lr

I

JL

Lr

t

L

H
H

JL

Lr

H = High Logic Level
L = Low LogiC Level

4

X ~ Can Be Either Low or High

B

5

f = Positive Going Transition
Al

_Bl

CLR
1

Ql

02

CeXT ReXTI GND
CeXT

1= Negative Going Transition
JL. = A Positive Pulse

2

Lr

TLlF/6386-1

DM54LS123 (J)

DM74LS123 (N)

4-135

~

A Negative Pulse

Recommended Operating Conditions
Symbol

DM54LS123

Parameter

Vee

Supply Voltage

V'H

High Level Input
Voltage

V'L

Low Level
Input Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

tw

Pulse Width

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

0.8

-0.4

-0.4

40

Aor B
Low

40

40

Clear
Low

40

40

CI'I'RE

Wiring Capacitance
at REXT/CEXT Terminal

TA

Free Air Operating
Temperature

180

5

kG

No Restriction

125

0

.

I'F
50

pF

70

·C

over recommended operating free air temperature (unless otherwise noted)
Conditions

Min

Typ
(Note 1)

J

Max

V,

Input Clamp Voltage

Vcc= Min, 1,= -18 mA

VOH

High Level Output
Voltage

Vcc= Min
IOH=Max
V'L=Max
V'H=Min

DM54

2.5

3.4

DM74

2.7

3.4

Low Level Output
Voltage

Vcc=Min
,IOL=Max
V'L= Max
V'H=Min

DM54

0.25

0.4

DM74

0.35

0.5

IOL=4mA
Vcc=Min

DM74

0.25

0.4

VOL

mA

260

50

Electrical Characteristics

mA

ns

5

No Restriction

-55

V

8

40

External Timing
Capacitance

V
V

0.7

A or B
High

CEXT

Units

2

4

External Timing
Resistor

Parameter

Min

2

REXT

Symbol

DM74LS123

-1.5

Units
V
V

V

I,

Input Current@Max
Input Voltage

Vcc=Max, V,=7V

0.1

mA

I'H

High Level Input
Current

Vcc=Max, V,=2.7V

20

I'A

I'L

Low Level Input
Current

Vcc=Max, V,=0.4V

·-0.4

mA

los

Short Circuit
Output Current

Vcc=Max
(Note 2)

mA

Supply Current

Vcc= Max
(Notes 3, 4 and 5)

Icc

DM54

-20

-100

DM74

-20

-100
12

4·136

20

mA -

Switching Characteristics 'at Vcc=5V ~nd TA=25°C
RL = 2 kG
Parameter

From
,(Input)
to
(Output)

C L =15 pF
CEXT=O pF, REXT=5 kG
Min

Typ

Max

CL=15 pF
CEXT=1000 pF, REXT=10 kG
Min

Typ

Units

Max

tpLH Propagation Delay
Time Low to'High
Level Output

A
to
Q

22

33

ns

tpLH Propagation Delay
Time Low to High
Level Output

B
to
Q

29

44

ns

tpHL Propagation Delay
Time High to Low
Level Output

A
to

30

45

ns

tpHL Propagation Delay
Time High to Low
Level, Output

B
to

37

56

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clear
to

30

45

ns

tpHl Propagation Delay
rime High to Low
Level Output

Clear
to
Q

18

27

ns

tWQ(Min) Minimum Width
of Pulse at
Output Q

Aor B
to
Q

116

200

ns

tW(out) Output
Pulse Width

Aor B
to
Q

Q

Q

Q

4

4,5

5

p's

Note 1: All typicals are at VCC; SV, TA; 2S0C.
Note 2: Not more than one output should be shorted at a time, and the duration should 'hot exceed one second.

Note 3: Quiescent ICC is measured (after clearing) with 2.4V applied to all clear and A Inputs, B inputs grounded, all outputs open, CEXT;O.02"F, and
REXT;2S kll.
Note 4: ICC is measured in the triggered state with 2.4V applied to all clear and B inputs, A Inputs grounded, all outputs open, CEXT;O.02 "F, and
REXT;2S kll.
Note 5: With all'outputs open and 4.SV applied to all data and clear Inputs, ICC is measured aiter a momentary ground, then 4.SV is applied to the clock.

,

4·137

Operating Rules
1.

An external resistor (Rx) and an external capacitor
(ex) are required for proper operation. The value of
Cx may vary from to any necessary value. For
small time constants high-grade mica, glass, polypropylene, polycarbonate, or polystyrene material
capacitors may be used. For large time qonstants
use tantalum or special aluminum capacitors. If
the timing capacitors have leakages approaching
100 nA or if stray capacitance from either terminal
to ground is greater than 50 pF the timing equations may not represent the pulse width the device
generates.

6.

To obtain variable pulse widths by remote trimming, the following circuit is recommended:

°

2.

3.

PIN

PIN
(6) OR (14)

T

ex

Rremota

Vee
TLlF/63B6·4

FIGURE 3
Nola: "Rremoie" should be as close to the one·shot as possible.

When an electrolytic capacitor is used for Cx a
switching diode Is often required for standard TTL
one-shots to prevent high,inverse leakage current.
This switching diode is not needed for the 'LS123
one-shot 'and should not be used. In general the
use of the switching diode is not recommended
with retriggerable operation.

7.

The retriggerable pulse width is calculated as
shown below:
T= Tw+ tpLH = Kx Rxx Cx +tpLH
The retriggered pulse width is equal to the pulse
width plus a delay time period (Figure 4).

For Cx »1000 pF the output pulse width (Tw) is
defined as follows:
TW=,KRxCx

INPUT

where[R x is in kll]
[Cx is in pF]
[Tw is in ns]
K",0.37
4.

Rx

(7)OR(lS)~~

O~TPUT

TLlF/6386·5

The multiplicative factor K is plotted as a function
of Cx below for design considerations:

102 pF

H-+++++t-++++++H--i
H-+++t+t-++++++H--i
H-++-l\J-f-H-++++-f-1-H
H-+++l"i-t++++++1-t-l

10 pF

L..L...w...J...J...l-l..J....l..!:"""-'--1...l..J

~ 0.1 ~F
!;l

.. 104 pF
103 pF

o

.2

....J

.4

.6

FIGURE 4

8.

Output pulse width variation versus Vee and
temperatures: Figure 5 depicts the relationship between pulse width variation versus Vee, and
Figure 6 depicts pulse width variation versus
temperatures.
10
REXT=10K
CEXT = 1000 pF
. TA=2S'C
w

..
'"
Z

<
:z:

.B 1.0 1.2 1.4 1.6

-

~

f..-"'"

~

"K" COEFFICIENT

-S

TLlF/6386-2

--

FIGURE 1
-10
S.S

4

Vee (V)

5.

For Cx < 1000 pF see Figure 2 for Tw vs Cx family
curves with Rx as a parameter:

TLIF/6386·6

FIGURES

IDs fTT.A-;;=:7'2S;;o.CcBmR",,='j!2S~0~K~_

10
ReXT=10K
CexT=1000 pF
Vee=5.0V

Vee=5.0V
w

.
z
'"

<
:z:
~

1- f...--'

~

-S

~

-

r-

'-

-- f -

I,
I

100

-10
-60 -30 0 3D 60 90 120 150
AMBIENT TEMPERATURE ('C)

1000

CEXT (pF)
TLlF/83B6-3

TLlFI6386-7

FIGURE 2

FIGURE 6
4-138

Operating Rules
9.

10.

(Continued)

Under any operating condition Cx and Rx must be
kept as close to the one-shot device pins as possible to minimize stray capacitance, to reduce noise
pick-up, and to reduce I-R and Ldildt voltage
developed along their connecting paths. If the
lead length from Cx to pins (6) and (7) or pins (14)
and (15) is greater than 3 cm, for example, the output pulse width might be quite different from
values predicted from the appropriate equations.
A non-Inductive and low' capacitive path is
necessary to ensure complete discharge of Cx in
each cycle of its operation such that the output
pulse width will be accurate.

11.

Vcc and ground wiring should conform to good
high-frequency standards and practices so that
switching transients on the Vcc and ground return
leads do not cause interaction between one-shots.
A O.Q1"F to 0.10 "F bypass capacitor(disk ceramic or
monolithic type) from Vcc to ground is necessary on
each device. Furthermore, the bypass capacitor
should be located as close to the Vcc-pin as space
permits.

'-For further detailed device' characteristics and outpu( performance
please refer to the NSC ane·shat application note AN·366.

The CEXT pins of this device are internally connected to the Internal ground. For optimum
system performance they should be hard wired to
the system's return ground plane.

·However, it should be noted that although the 'LS221 series one-shot is
pin·far-pin compatible with the 'L5123 device, its CEXT pin is not an inter·

nal connection to ground. Hence. if substitution of an 'LS221 on to an
'LS123 design layout whose CEXT pin is wired to the ground is attempted,

the 'LS221 device will not function!

4-139

~

~ ~National

!1 ~ Semiconductor
~
::E

c

~

DM54LS125A/DM74LS125A Quad TRI-STATE® Buffers

,...
CJ)

...I

~
::E General Description

Absolute Maximum Ratings

C

This device contains four independent gates each of
which performs a non-inverting buffer function. The outputs have the TRI-STATE feature. When enabled, the
outputs exhibit the low impedance characteristics of a
standard LS output with additional drive capability to
permit the driving of bus lines without external
resistors. When disabled, both the output transistors
are turned off presenting a high-impedance state to the
bus line. Thus the output will act neither as a significant
load nor as a driver. To minimize the possibility that two
outputs will attempt to take a,common bus to opposite
logic levels, the disable time is shorter than the enable
.
time of the outputs.

7V
7V
- 65·C to 150·C

Supply Voltage
Input Voltage
Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Aecommended Operating Conditions" table will

define the conditions for actual device operation.

.

Connection Diagram

Function Table

Dual-In-Line Package
vcc

C4

114

Y4

A4
13

12

C3

11

Y=A
A3

Y(-

Y3

9

10

Input

B

4(-

C1

~1

12
A1

3

Y1

H

4
C2

fl

15
A2

C

Y

L
H

L
L
H

L
H
Hi-Z-

=High Logic Level

L = Low Logic Level
X = Either Low or High Logic Level
Hi·Z

16

Y2

17
GND

TL/F/6387·'

DM54LS125A (J)

Output

A

X

1

(Note 1)

DM74LS125A (N)

4-140'

=TAI·STATE (Outputs are disabled)

c

s::

Recommended Operating Conditions

U1
~

DM54LS125'A
Symbol

Parameter

r-

DM74LS125A

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units
V

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

0.7

10H

High Level Output
Current

-1

-2.6

mA

10L

Low Level Output
Current

12

24

mA

TA

. Free Air Operating
Temperature

70

·C

2

V
V

0.8

-55

125

0

over recommended operating free air temperature (unless otherwise noted)

Parameter

Conditions

Min.

Typ
(Note 1)

2.4

3.4

Max

VI

Input Clamp Voltage

Vec=Min, 11= -18 mA

VOH

High Level Output
Voltage

Vcc=Mln,loH=Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee=Min
10L= Max
VIL=Max

DM54

0.25

0.4

DM74

0.35

0.5

IOL=12 mA
Vec=Min

DM74

0.25

0.4

-1.5

Units
V
V
V

II

Input Current@Max
Input Voltage

Vcc = Max, VI = 7V

0.1

mA

IIH

High Level Input
Current

Vcc=Max, VI=2.7V

20

I'A

IlL

Low Level Input
Current

Vcc=Max, VI=0.4V

-0.4

mA

10ZH

Off·State Output
Current with High
Level Output
Voltage Applied

Vce=Max, Vo=2.4V
VIH = Min, VIL = Max

20

I'A

10ZL

Off·State Output
Current with Low
Level Output
Voltage Applied

Vcc=Max, Vo=0.4V
VIH = Min, VIL = Max

-20

I'A

los

Short Circuit
Output Current

Vcc= Max
(Note 2)

mA

Supply Current

Vec

Icc

-s::~
C

~

r-

....N

rJ)

Electrical Characteristics
Symbol

2

....
N

rJ)

.,

DM54

-20

-100

DM74

-20

-100

=Max (Note 3)

11

Nate 1: All typlcals are at Vee=5V, TA=25"C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Nate 3: ICC is measured with the data control (e) Inputs at 4.5V and the data Inputs grounded.

4·141

20

mA

U1
~

Switching Characteristics

at Vcc = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output load)
RL=667!l

Parameter

CL=50 pF

Units

CL=150 pF

Typ

Max

Typ

Max

tpLH Propagation Delay Time
low to High level Output

10

15

, 14

21

ns

tpHL Propagation Delay Time
High to low level Output

10

18

15

22

ns

IpZH Output Enable Time
to High level Output

19

25

23

35

' ns

IpZL Output Enable Time
10 low level Output

16

25

26

40

ns

IpHZ Output Disable Time
frol'jl High level Output
(Note 1)

10

20

ns

tpLZ Output Disable Time
from low level Output
(Note 1)

12

20

ns

Min

Min

:

Nolel: CL=5 pF.

~

,
,

4-142

~----------------------------------------~-----------------------'C

:s:
i!
r-

~National

~ Semiconductor

...oo
N

-:s:~

DM54LS126A/DM74LS126A Quad TRI-STATi:® Buffers

C

~
""""
roo

General Description

Absolute Maximum Ratings

This device contains four Independent gates each of
which performs a non-Inverting buffer function. The outputs have the TRI-STATE feature. When enabled, the
outputs exhibit the low impedance characteristics of a
standard LS output with additional drive capability to
permit the driving of bus lines without external
resistors. When disabled, both the output transistors
are turned off presenting a high-Impedance state to the
bus line. Thus the output will act neither as a significant
load nor as a driver. To minimize the possibility that two
outputs will attempt to take a common bus to opposite
logic levels, the disable time is shorter than the enable
time of the outputs.

Supply Voltage
Input Voltage
Storage Temperature Range

Connection Diagram

vI'

14

"

A4

v.

12

el

11

.,

,

10

Nota 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

not be operated al these limits. The parametric values defined In the
"Electrical Characterlsllcs" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operallng Conditions" lable will
define the conditions for actual device operation.

Y=A
V3

Input

•

L£t>-

Ltf>-

C1

~),3

1,2

•
C2

~
5
J2

)26

C

Y

L
H

H
H
L

L
H
Hi-Z

H = High Logic Level
L = Low logic Level
X = Ellher Low or High Logic Level
HI·Z=TRI-5TATE (Oulpuls are disabled)

J:

TlIFI6388-1

DM54LS126A (J)

Output

A

X

1

7V
7V
- 65·Cto 150·C

Function Table

Dual-In-Line Package
co

...
(Note 1)

DM74LS126A (N)

4·143

~

Recommended Operating Conditions
Symbol

DM54LS126A

Parameter

DM74LS126A

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

0.7

0.8

IOH

High Level Output
Current

-1

-2.6

mA

IOL

Low Level Output
Current

12

24

mA

TA

Free Air Operating
Temperature

70

·C

2

-55

Electrical Characteristics
Symbol
VI
VO H

I

VOL

Parameter

2

Conditions

Input Clamp Voltage

Vee = Min, 11= -18 mA

High Level Output
Voltage

Vee=Min,loH=Max.
VIH=Min

Low Level Output
Voltage

Vee=Min
IOL= Max
VIL=Max
VIH=Mln

Input Current@Max
.Input Voltage

V

over recommended operating free air temperature (unless otherwise noted)

IOL=12 mA
Vee=Min
II

V

0

1.25

V

Min

Typ
(Note 1)

2.4

3.4

Max
-1.5

Units
V
V

DM54

0.25

0.4

DM74

0.35

0.5

DM74

0.25

0.4

V

Vee = Max, VI =7V

0.1

mA

IIH

High Level Input
Current

Vee=Max, VI=2.7V

20

p.A

IlL

Low Level Input
Current

Vee=Max, VI = 0.4V

-0.4

mA

IOZH

Off·State ·Output
Current with High
Level Output
Voltage Applied

Vee = Max, Vo= 2.4V
VIH = Min, VIL = Max

20

p.A

10ZL

Off-State Output
Current with Low
Level Output
Voltage Applied

Vee = Max, Vo=O.4V
VIH = Min, VIL = Max

-20

p.A

los

Short Circuit
Output Current

Vee=Max
(Note 2)

mA

Supply Current

Vee = Max (Note 3)

Icc

Note 1:

\

DM54

-20

-100

DM74

-20

-100

All typicals are at Vee = 5V, TA = 25·e.

Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Note 3: ICC is measured with both the output control and data Inputs grounded.

4-144

1;1

22

mA

Switching Characteristics

at Vcc=5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL =66711

Parameter

CL=50 pF

CL=150 pF

Typ

Max

tpLH Propagation-Delay Time
Low to High Level Output

10

tpHL Propagation Delay Time
High to Low Level Output

Min

Units

Typ

Max

15

14

21

ns

10

18

15

22

ns

tPZH Output Enable Time
to High Level Output

22

30

24

36

ns

tPZL Output Enable Time
to Low Level Output

19

30

28

42

ns

tpHZ Output Disable Time
from High Level Output
(Note 1)

- 10

25

ns

tpLZ Output Disable Time
from- Low Level Output
(Note 1)

14

25

ns

Nole1: cL=5 pF

4-145

Min

~

c;; ~ National
~ ~ Semiconductor
::i
c

~
....

....en
~

DM54LS132/DM74LS132 Quad 2-lnput NAND Gates with
~ Schmitt Trigger Inputs

General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic NAND function. Each input
has hysteresis which increases the noise immunity and
transforms 'a slowly changing input signal to a fast
changing, jitter free output.

Supply Voltage
Input Voltage
Storage Temperature Range

Connection Diagram

Function Table

7V
7V
-65·Cto 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not,guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" tabie will
define the conditions for actual device operation.

Dual·ln,Line Package

vr

14

A.

B4

13

V,

lIZ

~

11

B3
10

i'.

VJ

~

•

Inputs

=

AI

TLIF/6389·1

DM74LS132 (N)

4·146

Output

B

y

L

L

L

H

A

H

L

H
H
H'

H

H

L

H High Logic LilYel
L = Low Logic Level

DM54LS132 (J)

(Note 1)

Recommended Operating Conditions
Symbol

DM74LS132

DM54LS132

Parameter

Min

Nom

Max

Min

Nom

Max

Units

Vee

Supply Voltage

4.5

5

5.5

4.75

5

5.25

V

VT+

Positive·Going Input
Threshold Voltage (Note 1)

1.4

1.6

1.9

1.4

1.6

1.9

V

VT_

Negative·Going Input
Threshold Voltage (Note 1)

0.5

0.8

1

0.5

0.8

1

V

0.4

0.8

0.4

0.8

HYS

Input Hysteresis (Note 1)

IOH

High Level Output
Current

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

-0.4
4
-55

Electrical Characteristics
Symbol

Parameter

V
-0.4

125

0

8

mA

70

·C

over recommended operating free air temperature (unless otherwi.se noted)
Conditions

Min

Typ
(Note 2)

Max
-1.5

VI

Input Clamp Voltage

Vec=Min, 11= -18 mA

VOH

High Level Output
Voltage

Vcc=Mln
10H=Max
VI =VT_Min

DM54

2.5

3.4

DM74

2.7

3.4

Low Level Output
Voltage

Vce= Min
10L=Max
VI =VT+Max

DM54

0.25

·0.4

DM74

0.35

0.5

DM74

0.25

0.4

VOL

mA

IOL=4mA
Vee=Min

Units
V
V

V

IT+

Input Current at
Positive-Going
Threshold

Vee=5V, VI=VT+

-0.14

mA

IT_

Input Current at
Negative-Going
Threshold

Vee=5V, VI=VT_

-0.18

mA

I,

Input Current@Max
Input Voltage

Vee=Max, VI=7V

0.1

mA

I'H

High Level Input
Current

Vee = Max, VI=2.7V

20

{LA

IlL

Low Level Input
Current

Vce = Max, V, = 0.4V

-0.4

mA

los.

Short Circuit
Output Current

Vcc=Max
(Note 3)

mA

ICCH

Supply Current With
Outputs High

Vcc=Ma.x

5.9

11

mA

ICCL

Supply Current With
Outputs Low

Vcc=Max

8.2

14

mA

DM54

-20

-100

DM74

-20

-100

Nola 1: Vcc = 5V
Nola 2: All typicals ara at VCC = 5V, TA = 25·C.
Nota 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.
4-147

Switching Characteristics

at Vcc=5V and TA=25 C (See Section 1 for Test Waveforms and Output Load)
D

RL=2 kn

Parameter

CL=15pF

Units

CL=50 pF

Min

Typ

Max

Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

5

15

22

8

18

25

ns

tpHL Propagation Delay Time
High to, Low Level Output

5

15

22

10

21

33

ns '

4·148

r------------------------------------------------------------------.c

3:

~National

en
~

~ Semiconductor

fii
.....

Co)

en
C

DM54LS1361 DM74LS136 Quad 2-lnput Exclusive-OR
Gates with Open-Collector Outputs

3:
~

r-

en
.....

Co)

en

General Description

Absolute Maximum Ratings

This device contains four Independent gates each of
which performs the logic exclusive·OR function. The
open·collector outputs require external pull·up resistors
for proper logical operation.

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

Pull·Up Resistor Equations

Not. 1: The "Absolute Maximum Ratings" are those values beyond
which the salety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

R

MAX=

Vcc!Min)-VOH
N1 (IOH) + N2 (I'H)

7V
7V
7V

- 65·C to 150·C

RMIN= Vcc!Max)-VOL
10L - N3 (I,Ll

Where:

N1 (IOH) = total maximum output high current
for all outputs tied to pull·up resistor
N2 (I,H) = total maximum input high current for
all inputs tied to pull·up resistor
N3 (I,Ll = total maximum input low current for
all inputs tied to pull·up resistor

connection Diagram

Function Table

Dual·ln-Line Package

vr

14

B4

13

i~

v,
11

11

10

1

"

sl12

VI

To

8

~I>-

51>j~ ,

v,

B3

Inputs

~L>,
.2

6

at5

V2

J:

TLlF/639Q-1

DM54LS136 (J)

Y=AeB=AB+AB

DM74LS136 (N)

4·149

A

B

L
L
H
H

L
H
L
H

H = High Logic Level
L= Low Logic Level

(Note 1)

Output
Y
L

H
H
L

Recommended Operating .Conditions
Symbol

DM74LS136

DM54LS136

Parameter
Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units
V

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

0.7

0.8

V

VOH

High Level Output
Voltage

5.5

5.5

V

IOL

Low Level Output
Current

4

8

mA

TA

Free Air Operating
Temperature

70

DC

-55

Electrical Characteristics
Symbol

Parameter

V

2

2

125

0

over recommended operating free air temperature (unless otherwise noted)
Conditions

Min

VI

Input Clamp Voltage

Vee=Min,ll= -18 mA

leEx

High Level Output
Current

Vee = Min, Vo = 5.5V
VIL= Max, VIH = Min

VOL

Low Level Output
Voltage

Vee=Min
IOL=Max
VIL=Max
VIH=Miri

DM54
DM74

IOL=4 mA
Vee=Mln

DM74

Typ
(Note 1)

Max

Units

-1.5

V

100

/LA

0.25

0.4

V

0.35

0.5

0.25

0.4

II

Input Current@Max
1nput Voltage

Vee = Max, VI=7V

0.2

mA

IIH

High Level Input
Current

Vec=Max, VI = 2.7V

40

/LA

IlL

Low Level Input
Current

Vee = Max, VI=0.4V

-0.6

mA

Icc

Supply Current

Vee = Max (Note 2)

10

mA

6.1

Nole1: Aillypicals are al vee=Sv. TA=2s'e.
NOle 2: ICC Is measured with one input of each gale al 4.SV. the other Inpuls grounded, and Ihe outputs open .

.
4·150

Switching Characteristics

I

at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)

c
s::
en
olio

RL=2 kll
Parameter

Conditions

CL=15 pF
Min

tpLH Propagation
Delay Time Low
to High Level
Output
tpHL Propagation
Delay Time High
to Low Level
Output
tpLH Propagation
Delay Time Low
to High Level
Output
tpHL Propagation
Delay Time High
to Low Level
Output

Other
Input
Low

Other
Input
High

CL=50 pF

Units

~
.....

Typ

Max

30

21

36

ns

-s::

18

30

24

40

ns

en

18

30

21

36

ns

18

30

24

40

ns

Typ

Max

18

Min

Co)

en

C

.-:;;:!en
.....

Co)

,

-

4-151

~

II?A National

.
~ ~ Semiconductor

Ui

~ DM54LS138/DM74LS138, DM54LS139/DM74LS139
i Decodersl Demultiplexers
'I"'"

Features
~ General Description
;1) These Schottky-clamped circuits are designed to be usad • Designed specifically for high-speed:
:E in high-performance memory-decoding or data-routing apMemory decoders

c
~
'I"'"

....

U)

~

:E

c

i

'I"'"

~

oo:t

Lt)

:E

c

plications, requiring very short propagation delay times. In
high-performance memory systems these decoders can be
used to minimize the effects of system decoding. When
used with high-speed memories, the delay times of these
decoders are usually less than the typical access time of
the memorY. This means that the effective system delay introduced by the decoder is negligible.
The LS138 decodes one-of-eight lines, based upon the
conditions at the three binary select inputs and the three
enable inputs. Two active-low and one active-high enable
inputs reduce the need for external gates or inverters
when expanding. A 24-line decoder can be implemented
with no external inverters, and a 32-line decoder requires
only one inverter. An enable input can be used as a data input for demultiplexing applications.
The LS139 comprises two separate two-line-to-four-line·
decoders in a single package. The active-low enable input
can be used as a data line in demultiplexing applications.
All of these decoders I demultiplexers feature fully buffered
inputs, presenting only one normalized load to its driving
circuit. All inputs are clamped with high-performance
Schottky diodes to suppress line-ringing and simplify system. design.

Data transmission systems
• LS138 3-to-8-lin.e decoders incorporates 3 enable inputs
to simplify cascading and/or data reception
• LS139 contains two fully independent 2-to-4-line
decoders/demultiplexers
• Schottky clamped for high performance
• Typical propagation delay (3 levels of logic)
LS138 21 ns
LS139 21 ns
• Typical power dissipation
LS13832mW
LS13934mW

Absolute Maximum Ratings (Note 1)
7V
7V
-65·Clo 150·C

Supply Voltage
Input Voltage
Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions. for actual device operation.

Connection Diagrams
Dual-In-Line Package

Dual-In-Line Package

DATA OUTPUTS
i

VCC
116

ENABLE
G2
VCC

\

YO

Y1

15

Y2
14

Y3

13

Y4

12

Y5

11

Y6

9

10

116

115

!

,

SELECT

A2

.

B2
113

114
1

1

.

DATA OUTPUTS
i

2YO

2Y1

112

111

!

1,.

\

2Y2

2Y3

9

110

1,.
t:>-

-

PrO

1
A

2

3

B

C

\

,

4
G2A
\

SELECT

5

.

G2B

7

6
G1
i

18

1

GND
Y7
OUTPUT

ENABLE
G1

ENABLE

I

I

'(

'(

12

13

14

15

1Y0

1Y1

A1

.

B1

.

\

SELECT

1

.

16
1Y2

1t:
i

.1 8
GND

,

DATA OUTPUTS

TLIF16391·1

54LS138 (J)

r

TLIF16391·2

74LS138(N)

54LS139(J)
4-152

74LS139 (N)

Recommended Operating Conditions
Symbol

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

DM74LS138

DM54LS138
Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2
0.7

0.8

-0.4

-0.4

4
125

V
V

2

-55

Units

0

V
mA

8

mA

70

'c

'LS138 Electrical Characteristics
over recommended operating free air temperatu,re (unless otherwise noted)
Symbol

Parameter

Min

Typ
(Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

VI

Input Clamp Voltage

Vcc=Min, 11= -18 mA

VOH

High Level Output
Voltage

Vcc=Min
10H= Max
VIL=Max
VIH=Min

Low Level Output
Voltage

Vcc=Min
10L=Max
VIL = Max
VIH=Min

VOL

IOL=4 mA
Vcc=Min

Max
-1.5

Units
V
V

DM54

0.25

0.4

DM74

0.35

0.5

DM74

0.25

0.4

V

II

Input Current@Max
Input Voltage

Vcc=Max, VI=7V

0.1

mA

IIH

High'Level Input
Current

Vcc=Max, VI=2.7V

20

p.A

IlL

Low Level Input
Current

Vcc = Max, VI = 0.4V

los

Short Circuit
Output Current

Vcc=Max
(Note 2)

Supply Current

Vcc = Max (Note 3)

Icc

mA
mA

DM54

-20

-100

DM74

-20

-100
6.3

Note 1: All typicals are at VCC=SV, TA=2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3:

-0.36

ICC Is measured with all outputs enabled and open.

4·153

10

mA

•

'LS138 Switching Characteristics

atVcc=5V and TA=25°C

(See Sectiqn 1 for Test Waveforms and Output Load)

Parameter

From
(Input)
Levels
of Delay
To
(Output)

RL=2 kG
CL=15 pF
Min

Units

CL=50 pF

Typ

Max

Min

Typ

Max

tpLH Propagation Delay
Time Low to High
Level Output

Select
to
Output

2

13

18

16

27

ns

tpHL Propagation Delay
Time Hlgh.to Low
Level Output

Select
to
Outpui

2

17

27

23

40

ns

tpLH Propagation Delay
Time Low to High
Level Output

Select
to
Output

3

13

18

16

27

ns

tpHL Propagation Delay
Time High to Low .
Level Output

Select
to
Output

3

17

27

23

. 40

ns

tpLH Propagation Delay
Time Low to High
Level Output

Enable
to
Output

2

13

18

16

27

ns

tpHL Propagation Delay
Time High to Low
Level Output

Enable
to
Output

2

16

24

22

40

ns

tpLH Propagation D~lay
Time Low to High
Level Output

Enable
to
Output

3

13

18

16

27

ns

tpHL Propagation Delay
Time High to Low
Level Output

Enable
to.
Output

3

19.'

28

25

40

ns

.

)

-

4·154

,

Recommended Operating Conditions
Symbol

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

DM74LS139

DM54LS139
Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

0.7

0.8

-0.4

-0.4

4
-55

125

V
V

2

2

Units

0

V
mA-

8

mA

70

·C

'LS139 Electrical Characteristics
over recommended operating free air. temperature (unless otherwise noted)
Typ
(Note 1)

Symbol

Parameter

VI

Input Clamp Voltage

Vee=Min, 11= -18 mA

VOH

High Level Output
Voltage

Vee=Min
10H=Max
VIL=Max
VIH=Min

DM54

. 2.5

3.4

DM74

2.7

3.4

Low Level Output
Voltage

Vee=Min
10L= Max
VIL=Max
VIH=Min

DM54

0.25

0.4

DM74

0.35

0.5

IOL=4 mA
Vee=Min

DM74

0.25

0.4

VOL

Conditions

Min

Max
-1.5

Units
V
V

V

II

Input Current@Max
Input Voltage

Vee = Max, VI = 7V

0.1

mA

IIH

High Leveflnput
Current

Vee = Max, VI=2.7V

20

p.A

IlL

Low Level Input
Current

Vee = Max, VI = O.4V

los

Short Circuit
Output Current

Vee=Max
(Note 2)

Supply Current

Vee = Max (Note 3)

Icc

-0.36

mA
mA

DM54

-20

-100

DM74

-20

-100
6.8

Nole 1: All typlcals are at Vee=SV, TA=2S'e.
Nota 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Nole 3: ICC is measured with all outputs. enabled and open.

4-155

11

,mA

'LS139 Switching Characteristics

at Vcc=5V and TA=25°C

(See Section 1 for Test Waveforms and Output Load)
From
(Input)
To
(Output)

Parameter

RL=2 k!l
CL=15pF
Min

CL=50 pF

Typ

Max

Min

Units

Typ

Max

16

27

ns

23

40

ns

tpLH Propagation Delay
Time Low to High
Level Output

Select
to
Output

13

18,

tpHL Propagation Delay
Time High to Low
Level Output

Select
to
Output

17

27

tpLH Propagation Delay
Time Low to High
Level Output

Enable
to
Output

13

18

16

27

ns

tpHL Propagation Delay
Time High to Low
Level Output

Enable
to
Output

16

24

22

40

ns

I

(

Function Tables
LS139

LS138
Inputs
Enable

Inputs

Outputs

Select

Enable

Outputs

Select

G1 G2' C

B

A

YO Y1 Y2 Y3 Y4 Y5 Y6 Y7

G

B

A

YO

Y1

Y2

Y3

H
X
L
L
L
L
L
L
L
L

X
X
L
L
H
H
L
L
H
H

X
X
L
H
L
H
L
H
L
H

H
H
L
H
H
H
H
H
H
H

H
L
L
L
L

X
L
L
H
H

X
L
H
L
H

H
L
H
H
H

H
H
L
H
H

H
H
H
L
H

H
H
H
H
L

X
L
H
H
H
H
H
H
H
H

X
X
L
L
L
L
H
H
H
H

H
H
H
L
H
H
H
H
H
H

H
H
H
H
L
H
H
H
H
H

H
H
H
H
H
L
H
H
H
H

H
H
H
H
H
H
L
H
H
H

H
H
H
H
H
H
H
L
H
H

H
H
H
H
H
H
H
H
L
H

H
H
H
H
H
H
H
H
H
L

H

= high level, L = low level. X

·G2 = G2A + G2B
H = High level. L = low level, X = don't care

,

c_

4-156

l1li

don't care

Logic Diagrams
LS138

DATA
OUTPUTS

A (1)

SELECT
INPUTS

B (2)

C (3)

TLJF/6391·3

LS139

ENABLE Gl (1)

DATA
OUTPUTS

ENABLE G2 (15)

TLIF16391-4

4-157

,-r-------------------------------------------------------------------------~_,
LI)

§

~National

~ ~ Semiconductor

:iE

-§c DM54LS151/DM74LS151 Data Selector/Multiplexer
,II)

~
LI)

:iE General Description
c
This data selector/multiplexer contains lull on·chip
decoding to select the desired data source. The LS151
selects one·ol·eight data sources. The LS151 has a strobe
input which must be at a low logic level to enable these
devices. A high level at the strobe lorces the W output
high, and the Y output low.
The LS151

leat~res

complementary Wand Youtputs.

Features
•
•
'.
•

• Typical average propagation delay time data input to W
output 12.5 ns
'
• Typical power dissipation 30 mW

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
Storage Temperature Range

7V
7V
-65'Ct0150'C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which t'he safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric value's defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
defIne the conditions for actual device operation.

Select one·ol·eight data lines
Performs parallel·to·serial conversion
Permits multiplexing from N lines to one line
Also for use as Boolean function generator

Connection Diagram

Truth Table

Dual·in·Lina Package
DATA INPUTS

vee

1,6

,..

D4

15

05

06

14

13

DATA SELECT

07

A

10

11

12

9

t-

r-

4

03

Inputs

Select

C

02 -

01

DO

DATA INPUTS

6
W

7

C

B

A

X
L
L
L
L
H'
,H
H
H

X
L
L
H
H
L
L
H
H

X
L
H
L
H
L
H
L
H

H
L
L
L
L
L
L
L
L

y
L

H

DO

01
02
03
04
05
06
07

01
02
03
04
05
. 06
07

DO, 01 ... 07 "" the level of the respective 0 input

--------OUTPUTS

74LS151 (N)

4·158

W

DO

H = High Leval, L = Low Level, X = Don't Care

J8

STROSE GNO

TlIF/6392·1

54LS151 (J)

Outputs

Strobe
S

c

:s:::
en
.j:Io

Recommended Operating Conditions
Symbol

DM54LS151

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

r-

DM74LS151

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units
V

2

V
0.8

-0.4

-0.4

4
125

0

V
mA

8

mA

70

·C

\,
I

Electrical Characteristics
.Symbol
VI

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

over recommended operating free air temperature (unless otherwise noted)

Parameter

Low Level Output
Voltage

Conditions

Min

Typ
(Note 1)

Vee=Min, 11= -18 mA

Max
-1.5

Vee=Min
. 10H= Max
VIL=Max
VIH=Min

DM54

2.5

3.4

DM74

2.7

3.4

Vee=Min
10L= Max
VIL=Max
VIH=Min

. DM54

0.25

0.4

DM74

0.35

0.5

IOL=4 mA
Vee Min

DM74

0.25

0.4

Units
V
V

V

=

II

Input Current@Max
Input Voltage

Vee=Max, VI=7V

0.1

rnA

IIH

High Level Input
Current

Vee= Max, VI =2.7V

20

p.A

IlL

Low Level Input
Current

Vee=Max, VI=O.4V

-0.4

rnA

los

Short Circuit
Output Current

Vee= Max
(Note 2)

rnA

Supply Current

Vee = Max (Note 3)

Icc

DM54

-20

-100

DM74

-20

-100

6

Nola 1: All typicals are al Vee=5V. TA=25·e.
Nota 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: ICC Is measured with all outputs open, strobe and data select inputs at 4.5V, and all other inputs open.

4·159

-....
c

:s:::

i:!

r-

0.7

-55

OO
....
en

10

rnA

....CiIOO
....

Switching Characterisiics
Parameter

at Vcc=5V and TA =25"C (See Section 1 for Test Waveforms and Output Load)

From
(Input)
To
(Output)

RL=2 kll
CL=15 pF
Min

Typ

CL=50 pF
Max

Min

Units

Typ

Max

tpLH Propagation Delay
Time Low to High
Level Output

Select
(4 Levels)
toY

' 27

43

30

46

ns

tpHL Propagation Delay
Time High to Low
Level Output

Select
(4 Levels)
to Y

18

30

24

36

ns

tpLH Propagation Delay
Time Low to High
Level Output

Select
(3 Levels)
toW

14

23

17

.25

ns

tpHL Propagation Delay
Time High to Low
Level Output

Select
(3 Levels)
toW

20

32

26

40

ns

tpLH Propagation Delay
Time Low to High
Level Output

Strobe
to
Y

26

42

29

44

ns

tpHL Propagation Delay
Time High to Low
Level Output

Strobe
to
Y

20

32

26

40

ns

tpLH Propagation Delay
Time Low to High
Level Output

Strobe
to
W

15

24

18

27

ns

tpHL Propagation Delay
Time High to Low
Level Output

Strobe
to
W

18

30

24

36

ns

tpLH Propagation Delay
Time Low to High
Level Output

DO thru 07
to
Y

20

32

23

35

ns

tpHL Propagation Delay
Time High to Low
Level Output

DO thru 07
to
Y

16

26

22

33

ns

tpLH Propagation Delay
Time Low to High
Level Output

DO thru 07
to
W

13

21

16

25

ns

tpHL Propagation Delay
Time High to Low
Level Output

DO thru 07
to
W

12

20

18

27

ns

(

4-160

c
3:

Logic Diagram

en
~

li)
.....
en
.....

-

LS151

C

STROBE ,;..(7":")_-01
(ENABLE)

3:

Ir~~J

~

DO ,,-,;(4)

r-

en
.....
en
.....

(3)

D1

Irt:::$=i:t-l

02

.+=I==t==+=r~

(2)

DATA
INPUTS

(13)

D6~Fttb
(12)

D7~Fttb
,A

A

B

B

C

C,

See Address Buffers Below

TlIF/6392·2

Address Buffers for 54LS151174LS151
AABBCC

·I~

DATA
SELECT
(BINARY)

A (10)
B
(9)

~---~

C

TlIF/6392·3

4·161

Mr------------------------------------------------------------------,

.,...

II)

~ ~National
;:!: ~ Semicon(tuctor
:E

DM54LS153/DM74LS153 Dual4-Line to 1-Line Data
-c.,... Selectorsl
Multiplexers
C ")
II)

~ General Description
~
:E Each of these data selectors/multiplexers contains invert-

c

ers and drivers to supply fully complementary, on-chip, binary decoding data selection to the AND-OR-invert gates.
Separate strobe inputs are provided for each of the two
four-line sections.

• Typical average propagation delay times
From data 14 ns
From strobe 19 ns
From select 22 ns
• Typical power dissipation 31 mW

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
Storage Temperature Range

Features
• Permils multiplexing from N lines to 1 line
• Performs at parallel-to-serial conversion
• Strobe (enable) line provided for cascading (N lines to n
,lines)

7V
7V

-65°Ct0150°C

• High fan-out, low impedance, totem pole outputs

Note 1: The "'Absolute Maximum Ratings"' are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"'Electrical Characteristics"' table are not guaranteed at the absolute
maximum ratings. The "'Recommended Operating Conditions"' table will
define the conditions for actu,al device operation.

Connection Diagram

Function Table

Dual-In-Line Package
Select
Input.
A

CO

C1

C2

C3

G

y

X
L
L
L
L
H
.H
H
H

X
L
L
H
H
L
L
H
H'

X
L
H

X

X
X
X
X
X
L
H

X
X
X
X
X
X
X

X
X

L
H

H
L
L
L
L
L
L
L
L

L
L
H
L
H
L
H
L
H

X

X
X

X

L
H

X
X
X
X

X
X
X
X

Logic Diagram
STROBE G1 (1)

1CO .:.;(6;;.)_ _ _ _ _ _ _++--1-1--'
1C1~(5~)__________~~~~L_)
Y1

1C2~(4~)_ _ _ _ _~~~~~~-'

1C3£(3~)_ _ _ _ _~=*~~~L-.)

-~~

CO
:-,-,,--:::
2C1-

DATA 2

f

Output

B

74LS153 eN)

DATA 1

Strobe

Select inputs A and B are common to bOlh sections.
H .. High Level, L .. Low level, X = Don't Care

TLlF/6393·'

54LS153 (J)

Data tnput.

2C2(.;;'2;:.)-----4I=t:=::I=*=r"'l

2C3(1.;;3~)_:_------i=t:==*=r"'l
(15)

STROBEG2

4-162

Recommended Operating Conditions
I

DM54LS153
Symbol

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

Parameter

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

0.7

0.8

-0.4

-0.4

4
-55

125

V
V

2

0

V
mA

8

mA

70

·C

over recommended operating free air temperature (unless otherwise noted)
Min

Typ
(Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

VI

Input Clamp Voltage

Vcc=Min, 11= -18 mA

VOH

High Level Output
Voltage

Vcc=Min
10H=Max
VIL= Max
VIH=Min

Low Level Output
Voltage

Vcc= Min
10L=Max
VIL = Max
VIH= Min

VOL

Units

Nom

2

Electrical Characteristics
Symbol

. DM74LS153

Min

. IOL=4mA
Vcc= Min.

Max

-1.5

Units

V
V

DM54

0.25

0.4

DM74

0.35

0.5

DM74

0.25

0.4 .

V

II

Input Current@Max
Input Voltage

Vcc=Max, VI =7V

0.1

mA

IIH

High Level Input
Current

Vcc=Max, VI=2.7V

20

I'A

IlL

Low Level Input
Current

Vcc = Max, VI = O.4V

los

Short Circuit
Output Current

Vcc = Max
(Note 2)

Supply Current

Vcc = Max (Note 3)

Icc

Notal:

-0.36

mA
mA

DM54

-20

-100

DM74

-20

-100
6.2

All typicals are at VCC=5V, TA = 25°C.

Nota 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: ICC is measured with all outputs open and all inputs grounded.

4-163

10

mA

('I)
Ll)

.....
en
..J

Switching Characteristics

~

~

-.....
c

Parameter

( 'I)
Ll)

From
(Input)
To
(Output)

at Vcc=5V and TA=25°C (See Section 1 for Test Waveforms and Output Load)
RL=2 kO
CL=15 pF
Min

Units

CL=50 pF

Typ

Max

Min

Typ

Max

en
..J

tpLH Propagation Delay
Time Low to .High
Level Output

Data
to
Y

10

15

13

20

ns

~

tpHL Propagation Delay
Time High to Low
Level Output

Data
to
Y

17

26

23

35

ns

tpLH Propagation .Delay
Time Low to High
Level Output

Select
to '
Y

19

29

22

35

ns

tpHL Propagation Delay
Time High to Low
Level Output

Select
to

25

38

31

45

ns

tpLH Propagation Delay
Time Low to High
Level Output

Strobe
to
Y

16

24

19

30

ns

tpHL Propagation Delay
Time High to Low
Level Output

Strobe
to
Y

21

32

27

40

ns

~

c

y.

I

-

4-164

c

3:

~National

en
~

~ Semiconductor

r-

en
....

en

DM54LS154/DM74LS154 4·Line to 16·Line
Decodersl Demultiplexers

~

C

3:
~
r-

General Description
Each of these 4-line-to-16-line decoders utilizes TTL circuitry to decode four binary-coded inputs into one of sixteen mutually exclusive outputs when both the strobe
inputs, Gl and G2, are low. The demultiplexing function is
performed by using the 4 input lines to address the output
line, passing data from one of the strobe inputs with the
other strobe input low_ When either strobe input is high, all
outputs are high. These demultiplexers are ideally suited
for implementing high-performance memory decoders. All
inputs are buffered and input clamping diodes are provided
to minimize transmission-line effects and thereby simplify
system design.

Features
• Decodes 4 binary-coded inputs into one of 16 mutually
exclusive outputs
• Performs the demultiplexing function by distributing
data from one input line to anyone of 16 outputs

....

OO
en

• Input clamping diodes simplify system design
• High fan-out, low-impedance, totem-pole outputs
• Typical propagation delay
3 levels of logic 23 ns
Strobe 19 ns

~

• Typical power dissipation 45 mW

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
Storage Temperature Range

7V
7V
- 65"Cto 150"C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the

"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

A

Connection and Logic Diagrams

B

C

D·

A

r-

(1)

~I--

(2)

~I--

(3)

o

Dual-In-Line Package
INPUTS

vee
h4

A

B

C
21

22

23

D

OUTPUTS

G2

20

G1' '15

19

18

17

14

13

16

15

14

B

(18)
G1
G2
(19)

11'

12

13

G
(4)

~

(5)

~

(6)

~I--

(7)

~

(8)

~

(9)

c
A

(23)
A

jo-

rO

l

A

I

B

B

( 22)

B

e
·V c

( 21)

C
1

,0

2

3

2

4

3

5

4

7

6

5

6

OUTPUTS

54LS154(J)

8

9

10
9

11 112
10, GND

Dr-~

TlfF/6394·1
( 20

74LS154 (N)

D

(10)

D

I

rl-----.

D

4

6

8

9

(11)
10

D

"""

C

r~

(13)
11
(14)
12

B

~

(15)

r.~

(16)

13

A

14

I"GC

A
B

(17)

15

eDt:::::
Tl/FI6394·2

4-165

•

~
,..
en
...J

r::!:

:ii!:

c

Recommended Operating Conditions
DM54LS154
Symbol

~

Vee

Supply Voltage

en
...J

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

Lt)
,..
~
Lt)

:ii!:

c

Parameter

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

-55

0.7

0.8

-0.4

-0.4

125

V

0

V
mA

8

mA

70

'C

over recommended operating free air temperature (unless otherwise noted)
Conditions

Min

Typ
(Note 1)

Max

VI

Input Clamp Voltage

Vee=Min, 11= -18 mA

VOH

High Level Output
Voltage

Vee= Min
10H= Max
VIL = Max
VIH = Min

DM54

2.5

3.4

DM74

2.7

3.4

Low Level Output
Voltage

Vee=Min
IOL= Max
V IL = Max
V IH = Min

DM54

0.25

0.4

DM74

0.35

0.5

DM74

0.25

0.4

VOL

Units

V

4

Electrical Characteristics
Symbol

DM74LS154

Parameter

IOL= 4 mA
Vee=Min

-1.5

Units

V
V

V

II

Input Current@Max
Input Voltage

Vee = Max, VI = 7V

0.1

mA

IIH

High Level Input
Current

Vee = Max, VI = 2.7V

20

JiA

IlL

Low Level Input
Current

Vee = Max, VI = O.4V

-0.4

mA

los

Short Circuit
Output Current

Vee= Max
(Note 2)

mA

Supply Current

Vee = Max (Note 3)

lee

DM54

-20

-100

DM74

-20

-100

9

Notal: All typicals are at Vee=5V. TA=25'e.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second .
. Note 3: ICC is measured with all outputs open

and all inputs grounded.
,

4-166

14

mA

Switching Characteristics at Vee = 5V and TA = 25°C
From
(Input)
To
(Output)

Parameter

(See Section 1 for Test Waveforms and Output Load)
RL=2 kG

CL=15 pF
Min

Units

CL=50 pF

Typ

Max

Min

Typ

, Max

tpLH Propagation Delay
Time Low to High
Level Output

Data
to
Output

18

30

22

35

n5

tpHL Propagation Delay
Time High to Low
Level Output

Data
to
Output

18

30

24

35

n5

tpLH Propagation Delay
Time Low to High
Level Output

Strobe
to
Output

12

20

15

25

n5

tpHL Propagation Delay
Time High to Low
Level Output

Strobe
to
Output

16

25

23

35

ns

Function Table
Inputs

Outputs

G1

G2

D

C

B

A

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H

L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

L
L
L
L
H
H
H
H
L
L
L
L

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H,
X
X
X

L
H
L
'H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X

L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H

H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H

H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H

H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H

H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H

H
H
H
H
H
H
H
'H
H
L
H
H
H
H
H
H
H
H
H

H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H

H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H

H
H
H
H
H
H
H
H
H
H
H
H
H,
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
H
H
H
H
H
H
H 'H
H
H

H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H

X
X
X

H
H
H
H
X
X
X

H = High Level, L - Low Level, X
I

1::1

Don't Care

4-167

~National

~ Semiconductor
DM54LS1551 DM74LS155, DM54LS1561 DM74LS156
Dual2-Line to 4-Line Decoders/Demultiplexers
General Description
These TTL circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binary-address
inputs in a single 16-pin package. When both sections are
enabled by the strobes, the common address inputs sequentially select and route associated input data to the appropriate output of each section. The individual strobes
permit activating or inhibiting each of the 4-bit sections as
desired. Data applied to input C 1 is inverted at its outputs
and data applied at C2 is true through its outputs. The inverter following the C 1 data input permits use as a 3-to-Bline decoder, or Ho-B-line demuliplexer, without external
gating. Input clamping diodes are provided on these circuits to minimize transmission-line effects and simplify system design.

Features
• Applications;
Dual 2-to-4-line decoder
. Dual Ho-4-line demultiplexer
3-to-B-line decoder
1-to-B-line demultiplexer

• Individual strobes simplify cascading for decoding 'or
demultiplexing larger words
• Input clamping diodes simplify system design
• Choice of outputs;
Totem-pole (LS 155)
Open-collector (LS156)

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)
7V
7V

-6S·Cto IS0·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operallng Condilions" table will
define the conditions for actual device operation .

Function Table~

Connection Diagram

2-Line-to-4-Line Decoder or 1-Llne-to-4-Line Demultiplexer
fnputa

Dual-in-Line Package

Sefect Strobe

OUTPUTS

Outputs
Data

B

A

Gl

Cl

lYO

lYI

lY2

lY3

X

X

X

L
L
H
H

L
H
L
H

H
L
L
L
L

X

X

H
L
H
H
H
H

H
H
L
H
H
H

H
H
H
L
H
H

H
H
H
H
L
H

X

H
H
H
H
L

Inputs
Select Strobe

Outputs
Data

B

A

G2

C2

2YO

2Yl

2Y2

'2Y3

X

X

X

L
L
H
H

L
H
L
H

H
L
L
L
L

X

X

X

H
L
H
H
H
H

H
H
L
H
H
H

H
H
H
L
H
H

H
H
H
H
L
H

L
L
L
·L
H

3-Line-to-8-Line Decoder or 1-Line-to-8-Llne Demultiplexer
OUTPUTS

54LS155 (J)
54LS156 (J) .

Input.

TLlFJ6395·1

74LS155 (N)
74LS156 (N)

ct B

Outputs

Strobe
OrData

Select
A

GI
H
L
L
L
L
L
L
L
L

X

X

X

L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H

(0)

(1)

(2)

(4)

(5)

(6)

(7)

2YO 2Yl 2Y2 2Y3 lYO 1Yl lY2 1Y3
H
L
H
H
H
H
H
H
H

H
H
L
H
H
H
H
H
H

H
H
H
L

H
H
H
H
H

tc = inputs C 1 and C2 connected together
1G = inputs G1 and G2 connected together
H = high level, L = low level, X = don't care

4-168

(3)

H
H
H
H
L
H
H
H
H

H
H
H
H

H
L
H
H
H

H
H
H
H
H
H
L
H
H

H
H
H
H
H
H
H
L
H

H
H
H
H
H
H
.H
H
L

-

c

s:

Recommended Operating Conditions
Symbol

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

~

DM54LS155

DM74LS155

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2
0.7

0.8

-0.4

-0.4

4

8

125 .

0

70

~
....
en

-:s::
en

V
V

2

-55

Units

c

V

~
.CJ)

mA

en
J11

mA

:s::
en

·C

~
....

....
c

0l=Io

~
c

-:s::

.-~
....

CJ)

'LS155 Electrical Characteristics

en
C)

over recommended operating free air temperature (unless otherwise noted)
. Symbol

Parameter

Min

Typ
(Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

VI

Input Clamp Voltage

Vee= Min, 11= -18 mA

VOH

High Level Output
Voltage

Vee = Min
10H=Max
VIL=Max
VIH=Mln

Low Level Output
Voltage

Vee = Min.
IOL=Max
VIL= Max
VIH=Min

VOL

'IOL=4 mA
Vee= Min
Input Current@Max
Input Voltage

Vee = Max, VI=7V

IIH

High Level Input
Current

Vee = Max, VI = 2.7V

IlL

Low Level Input
Current

Vee = Max, VI =0.4V

los

Short Circuit
Output Current

Vee = Max
(Note 2)

Supply Current

Vee = Max (Note 3)

II

lee
Note 1:

-1.5

Units
V
V

DM54

0.25

0.4

DM74

0.35

0.5

DM74

0.25

0.4
0.1

V

mA

,.

20

mA
mA

DM54

-20

-100

-20

-100
6.1

All typlcals are at Vee=5V, TA=25"e.
lee is measured with all outputs open, A, S, and e1 Inputs at 4.5V, and e2, G1, and G2 Inputs grounded.

4·169

J-IA

-0.36

DM74

Nota 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Note 3:

Max

10

mA

'LS155 Switching Characteristics

at Vee ~ 5V and TA = 25·C

(See"Section 1 for Test Waveforms and Output Load)

Parameter

From
(Input)
To
(Output)

RL=2 kn
CL=50 pF

CL=15 pF
Min

Typ

Max

Min

Units

Typ

Max

tpLH Propagation Delay
Time Low to High
Level Output

A, B, C2,
G1 or G2
toY

12

18

15

22

ns

tpHL Propagation Delay
Time High to Low
Level Output

A, B, C2,
G1 or G2
to Y

17

27

23

35

ns

tpLH Propagation Delay
Time Low to High
Level Output

Aor B
to
Y

12

18

15

24

ns

tpHL Propagation Delay
Time High to Low
Level Output

Aor B
to
Y

17

27

23

35

ns

tpLH Propagation Delay
Time Low to High
Level Output

C1
to
Y

13

20

16

24

ns

tpHL Propagation Delay
Time High to Low
Level Output

C1
to
Y

17

27

23

35

ns

~

Recommended Operating Conditions
Symbol

Parameter

DM54LS156

DM74LS156

Min

Nom

Malt

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units

Vee

Supply Voltage

V1H

High Level Input
Voltage

VIL

Low Level Input
Voltage

0.7

0.8

V

VOH

High Level Output
Current

5.5

5.5

mA

IOL

Low Level Output
Current

4

8

mA

TA

Free Air Operating
Temperature

70

·C

2

2

-55

125

4-170

0

V
V

'LS156 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol

Parameter

Conditions

VI

Input Clamp Voltage

Vee = Min, 11= -18 mAo

leEx

High Level Output
Current

Vee= Min, Vo=5.5V
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vcc=Min
10L= Max
VIL=Max
VIH=Min
IOL=4 mA
Vee=Mln

Typ
(Note 1)

Min

Units

Max
-1.5

V

100

/"A
V

DM54

0.25

0.4

DM74

0.35·

0.5

DM74

0.25

0.4

II

Input Current@Max
Input Voltage

Vec = Max, VI = 7V

0.1

mA

IIH

High Level Input
Current

Vcc=Max, VI=2.7V

20

/"A

IlL

Low Level Input
Current

Vec=Max, VI=0.4V

Icc

Supply Current

Vcc= Max (Note 2)

-0.36
6.1

mA

10

mA

Not. 1: All typlcals are at VCC=SV, TA=2S"C.
Note 2: ICC is measured with all outputs open, A, B, and C1 Inputs at 4.SV, and C2, G1, and G2 grounded.

Switching Characteristics at Vcc=5V and TA =25°C
Parameter

From
(Input)
To
(Output)

(See Section 1 for

Te~ Waveforms and Output Load)

RL=2 kO
CL=15pF
Min

Units

CL=50 pF

Typ

Max

Min

Typ

Max

t~LH Propagation Delay
Time Low to High
Level Output

A, B, C2,
G1 or G2·
to Y

17

28

53

ns

tpHL Propagation Delay
Time High to Low
Level Output

A, B, C2,
G1 or G2
to Y

18

33

43

ns

tpLH Propagation Delay
Time Low to High
Level Output

A or B
to
Y

17

28

53

ns

tpHL Propagation Delay
Time High to.Low
Level Output

Aor B
to
Y

19

33

43

ns

tpLH Propagation Delay
Time Low to High
Level Output

C1
to
Y

18

28

53

ns

tpHL Propagation Delay
Time High to Low
Level Output

C1
to
Y

19

34

43

ns

4-171

Logic Diagram

STROBE ;,.(2,;.)_ _...,
G1

DATA ;,.(1...;5)...;.._...,

C2
STROBE ~(1_4;,.)_ _..J
G2

Tl/F/6395·2

4-172

r------------------------------------------------------------------,c

S::.

~National

U'I
,&::0.

~ Semiconductor
DM54LS157/ DM74LS157, DM54LS158/ DM74LS158
Quad 2·Line to 1·Line Data Selectors/Multiplexers
General Description

Features

These data selectors/multiplexers contain inverters and
drivers to supply full on·chip data selection to the four out·
put gates. A separate strobe input is provided. A 4·bit word
is selected from one of two sources and is routed to the
four outputs. The LS157 presents true data whereas the
LS158 presents inverted data to minimize propagation
delay time.

• Buffered inputs and outputs

~
....

U'I

::::!
c

s::
~

~
....

U'I

:"I

• Typical Propagation Time
LS157 9 ns
LS158 7 ns

c

s::
i!

• Typical Power Dissipation
LS157 49 mW
LS158 24 mW

....~

e

Absolute Maximum Ratings (Note 1)

Applications
• Expand any data input point
• Multiplex dual data buses
• Generate four functions of two variables (one variable is
common)
• Source programmable counters

Supply Voltage
Input Voltage
Storage Temperature Range

7V
7V

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table arB not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual·ln·Line Package
vcc

G

116

INPUTS

' A4

15

Al

SELECT '

B4 '

14

2
S

13

3

4

Bl

INPUTS

OUTPUT

Yl
OUTPUT '

Y4

' A3

12

OUTPUT

B3

11

5
A2

Dual·ln·Line Package·

INPUTS

6
B2

STROBE

vcc

Y3

10

9

G

116

15

7

S

Y2

INPUTS ' OUTPUT

INP,UTS

'A4

_ ,A:

SELECT

13

3
B1

INPUTS

OUTPUT

B4'

14

4
Y1
OUTPUT '

Y4
12

A:

INPUTS

'A3
11

6
B2

54LS157 (J)

Y:

54LS158(J)

G!:

74LS158 (N)

Output Y

Inputs
Strobe Select
X
L
L
H
H

9

TL/F/6396·2

Function Table

H

Y3

10

Low level at S selects A inputs
High level at S selects B inputs

74LS157 (N)

H
L
L
L
L

OUTPUT

B3'

INPUTS ' OUTPUT

TLIF/6396-1

Low level at S selects A inputs
High lavel al S 881ect8 B inputs

A

B

LS157

LS158

X
L
H
X
X

X
X
X
L
H

L
L
H
L
H

H
H
L
H
L

= High Leval, L • Low Level, X = Don" Care

4·173

s::
~
r-

....en

Connection Diagrams
STROBE

c

U'I

co

Recommended Operating Conditions
Symbol

DM54LS157

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

DM74LS157

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2
0.7

0.8

,

4
125

V
V

-0.4

-55

Units

0

V

-0.4

mA

'8

mA
·C

70

'LS157 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Min

Typ
(Note 1)

Vee=Min
10H=Max
VIL=Max
VIH = Min

DM54

2.5

3.4

DM74,

2.7

3.4

Vee = Min
10L=Max
VIL = Max
VIH=Min

DM54

0.25

0.4

DM74

0.35

0.5

IOL=4 mA
Vee= Min

DM74

0.25

0.4

. Vee=Max
VI =7V

S orG

0.2

A or B

0.1

High Level Input
Current'

Vee=Max
VI=2.7V

S or G

40

A or B

20

Low Level Input
Current

Vee=Max
VI =0.4V

S or G

-0.8

Aor B

-0.4

Short Circuit
Output Current

Vee=Max
(Note 2)

DM54

-20

-100

DM74

-20

-100

Supply, Current

Vee =' Max (Note 3)

Symbol

Parameter

VI

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

II

IIH

IlL

los

Icc

Low Level Output
Voltage

Input Current@fV!ax
Input Voltage

Conditions

-1.5

Vee= Min, II = -18 mA

,

Note 1: All typlcals are at vee = 5V, TA = 25"e.
Note 2: Not more than one output should be,shorted at a time, and the
Note 3: ICC Is measured with 4.5V applied to all inputs and all outputs

9.7

duratio~

Max

Units
V
V

16

V

mA

p.A

rnA

rnA

rnA

should not exceed one second.

open.

I

4-174

c

3:
~

'LS157 Switching Characteristics at Vee=5V and TA=25·C
(See Section 1 for Test Waveforms and Output Load)

Parameter

From
(Input)
To
(Output)

tpLH Propagation Delay
Time Low to High
Level Output

Data
to

tpHL Propagation Delay
Time High to Low
Level Output

Data
to

tpLH Propagation Delay
Time Low to High
Level Output

Strobe
to

tpHL Propagation Delay
Time High to Low
Level Output

Strobe
to

tpLH Propagation Delay
Time Low to High
Level Output

Select
to

tpHL Propagation Delay
Time High to Low
Level Output

Select
to

r-

eb
.....

RL=2 kO

Min

CL=50 pF

Units

Typ

Max

14

12

18

ns

14

15

23

ns

Typ

Max

9

9

Min

Y

Y
13

20

16

24

ns

Y

Vee

Supply Voltage

VIH

High Level Input
Voltage

V1L

Low Level Input
Voltage

I-oH

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

3:
~

r-

en
.....
~
c

3:
~

r-

en
.....

Q)

14

\

21

20

30

ns

c

3:
~

Y
16

23

19

28

ns

~
.....

UI

Y

Q)

15

27

21

32

ns

Y

DM74LS158

DM54LS158
Parameter

c

UI

Recommended Operating Conditions
Symbol

-"'"
UI

C L=15pF

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

-55

0.7

0.8

-0.4

-0.4

125

,

4·175

0

V
V

2

4

Units

V
mA

8

mA

70

·C

'LS158 Electrical Characteristics
over recommended operating' free air temperature (unless otherwise noted)
Symbol,

Conditions

Parameter

Min

Typ
(Note 1)

-1.5

VI

Input Clamp Voltage

Vee=Min, 119-18 mA

VOH

High Level Output
Voltage

Vee=Mln
10H=Max
VIL=Max
VIH=Min

DM54

2.5

3.4

DM74

2.7

3.4

Low Level Output
Voltage

Vee=Min
10L= Max
VIL=Max
VIH = Min

• DM54

0.25

0.4

DM74

0.35

0.5

IOL=4 mA
Vee=Min

DM74

. 0.25

0.4

Input Current@Max
Input Voltage

Vee=Max
VI =7V

S orG

0.2

Aor B

0.1

High Level Input
Current

Vee= Max
VI=2.7V

Low Level Input
Current

VOL

II

IIH

IlL

l.os
Icc

V
V

V

mA

S or G

40

A or B

20

Vee=Max
VI =0.4V

S orG

-0.8

A or B

-0.4

Short Circuit
Output Current

Vee=Max
(Note 2)

DM54

-20

-100

DM74

-20

-100

Supply Current

Vee = Max (Note 3)

'LS158 Switching Characteristics

Units

Max

4.8

/LA
mA

mA

8

mA

at Vee=5V and TA=25"C

(See Section 1 for Test Waveforms and Output Load)

Parameter

From
(Iilput)To
(Output)

RL=2 kO
C L =15 pF
Min

CL =50 pF

Typ

Max

Min

Units

Typ

Max

tpLH Propagation Delay
Time Low to High
Level Output

Data
to
Y

9

12

12

18

ns

tpHL Propagation Delay
Time High to Low
Level Output

Data
to
Y

8

12

14

21

ns

tpLH Propagation Delliy
Time Low to High
Level Output

Strobe
to
Y

12

17

15

23

ns

tpHL Propagation Delay
Time High to Low
Level Output

Strobe
to
Y

13

18

19

28

ns

tpLH Propagation Delay
Time Low to High
Level Output

Select
to
Y

13

20

16

24

ns

tpHL Propagation Delay
Time High to Low
Level Output

Select
to
y

18

24

24

36

ns

I

Note 1: All typicals are at VCC=5V, TA=25"C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second;

Note 3: ICC is measured with all Inputs at 4.5V and all outputs open.

4·176

c

3:
(J1

Logic Diagrams

~

r-

C/)

.....
....,

-

(J1

LS157

C

3:

. , (2)

~
r-

Bl(3)

C/)
.....
(J1

'2(5)

~....,

C

82 (6)

3:
(J1
~

A3 (11)

r-

C/)

.....

83(10)

(J1

co

A4 (14)

C

3:

B4(13)

~
r-

SELECT (1)

C/)

.....

c.n
co

STROBE (15)

TLiF/6396-3

LS158

,,(~2~)____~=========f~

4-______+--r~

Bl(~3~)____

A4 (14)

TLlFf6396-4

4-177

~ ~National

~ ~ Semiconductor
~
:s DM54LS160AJ.DM74LS160A, DM54LS161A/DM74LS161 A,
e DM54LS162A/DM74LS162A, DM54LS163A/DM74LS163A
~ Synchronous 4·Bit Counters
;:
~ General Description

~
:i
c

~....
~
~

:i

c

~

co
....

~

~
:i
c



~
r-

.....

ns

-3

0

-3

Others

0

-3

0

-3

Hold Time
(Note 2)

Data

5

5

Others

5

5

Clear Release Time
(Note 1)

20

20

ns

Clea~ Release Time
(Note 2)

25

25

ns

0

r-

.....
0)
.....

(J)

0

125

~

C/)

C

Data

-55

c

s:

s:

Hold Time
(Note 1)

Free Air Operating
Temperature

C/)
.....

(J)

Pulse Width
(Note 1)

Setup Time
(Note 2)

tH

0.7

25

r-

Units

V

2

2

Low Level
Input Voltage

tsu

DM74LS160A, LS161A

Min

V1L

tw

~

DM54LS160A, LS161A

-~s:
C

ns

~

r-

(J)

70

'C

.....

~
C

s:

~

r-

C/)

.....

0)

Note 1:
Note 2:

~
C
s:

CL = 15 pF and RL = 2 kll.
CL = 50 pF and RL .; 2 kll.

~

~
.....
0)

~
,

4·179

'LS160 and 'LS161 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol

Parameter

Min

Typ
(Note 1)

2.5

3.4

DM74

2.7

3.4

Conditions

Max
-1.5

VI

Input Clamp Voltage

VOH

High Level Output
Voltage

Vee= Min
IOH= Max
Vll = Max
VIH = Min

DM54

Low Level Output
Voltage

Vee= Min
IOl=Max.
Vll=Max
VIH = Min

DM54

0.25

0.4

DM74

0.35

0.5

IOl=4mA
Vee= Min

DM74

0.25

0.4

VOL

II

IIH

III

Input Current@Max
Input Voltage

High Level Input
Current

Low Level Input .
Current

Vee = Min, II =.- 18 mA

Vee=Max
VI=7V

Vee = Max
VI=2.7V

Vee=Max
VI =0.4V

los

Short Circuit
Ou'tput Current

Vee=Max
(Note 2)

leeH

Supply Current With
Outputs High

Vee=Max
(Note 3)

leel

Supply Current With
Outputs Low

Vee Max
(Note 4)

Enable T

0.2
0.2

Load

0.2

Others

0.1
40.

Load

40

Others

20

Enable T

-0.8

Clock

-0.8

Load

-0.8

Others

-0.4

DM54

-20

DM74

-20

\

-100

mA

/IA

mA

mA

-100
18

31

mA

19

32

mA

Nolo 1: All typicals are al Vec=5V, TA=25"C.
Nota 2: Not more than one'output should bQ shorted .at a time, and the duration should not exceed one second.

Nolo 3: ICCH is measured with the load high, then again with the load low, with all other inputs high and all outputs open.
Nolo 4: ICCl is measured with the clock Input high, then again with the clock input low. with all other inputs low and all outputs open.

I

-

4·180

V

40

Clock

=

V
V

Clock

. Enable T

Units

'LS160 and 'LS161 SWitching Characteristics

at Vcc=5V and TA =25"C

(See Section 1 for Test Waveforms and Output Load)

Parameter

From
(Input)
To
(Output)

RL=2 kG
C L =15 pF

f MAX Maximum Clock
Frequency

Min

Typ

25

32

Units

CL=50pF
Max

Min

Typ

20

25

Max
MHz

tpLH Propagation Delay
Time Low to High
Level Output

Clock to
Ripple
Carry

16

24

20

30

ns

t PHL Propagation Delay
Time High to Low
Level Output

Clock to
Ripple
Carry·

19

30

25

38

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock to
Any Q
(Load High)

15

22

18

27

ns

tpHL Propagation Delay
. Time High to Low
Level Output

Clock to
Any Q
(Load High)

19

27

25

38

ns

t PLH Propagation Delay
Time Low to High
Level Output

Clock to
Any Q
(Load Low)

16

24

19

30

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock to
Any Q
(Load Low)

21

29

26

38

ns

tpLH Propagation Delay
Time Low to High
Level Output

Enable T
to Ripple
Carry

13

18

16

27

ns

tpHL Propagation Delay
Time High to Low
Level Output

Enable T
to Ripple
Carry

10

15

16

27

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
Any Q

25

35

31

45

ns

-

,

\

4·181

Recommended Operating Conditions
Symbol

DM54LS162A, LS163A

Parameter

Nom

Max

Min

Nom

·Max

4.5

5 .

5.5

4.75

5

5.25

Vcc

Supply Voltage

V1H

High Level Input
Voltage

V1L

Low Level
Input Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

fCLK

Clock Frequency
(Note 1)

0

25

Clock Frequency
(Note 2)

0

20

tw

tsu

tREL

TA

Note 1:
Nole 2:

2

2
0.7

0.8

-0.4

-0.4

4

V
rnA
rnA

0

25

MHz

0

20

MHz

20

6

20

6

Clear

20

9

9

Pulse Width
(Note 2)

Clock

25

20
25

Clear

25

25

Data
Enable P

20
25

17

20
25

8
17

Load

25

15

25

15

Data
Enable P

20
30

8

V

8

Clock

Setup Time
(Note 1)

Units

V

Pulse Width
(Note 1)

Setup Time
(Note 2)

tH

DM74LS162A, LS163A

Min

ns

ns

ns

20
30

ns

Load

30

Hold Time
(Note 1)

Data

0

-3

30
0

-3

Others

0

-3

0

-3

Hold Time·
(Note 2)

Others

ns

5
,5

5
5

ns

Clear Release Time
(Note 1)

20

20

, ns

Clear Release Time
(Note 2)

25

25

ns

Data

125

-55

Free Air Operating
Temperature

CL = 15 pF and RL = 2 kO.
CL = 50 pF and RL = 2 kO.

4·182
.I

0

70

'C

'LS162 and 'LS163 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol

Parameter

Min

Typ
(Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

VI

Input Clamp Voltage

Vcc = Min, 11 = - 18 mA

VOH

High Level Output
Voltage

Vcc=Min
IOH= Max
V IL = Max
V IH = Min

Low Level Output
Voltage

Vcc= Min
IOL=Max
VIL=Max
VIH=Min

~OL

IOL=4 mA
Vcc=Min
II

IIH

Input Current@Max
Input Voltage

High Level Input
Current

Vcc=Max
VI =7V

Vcc=Max
VI=2.7V

,
IlL

Low Level Input
Current

Vcc=Max
VI =0.4V

Max
-1.5

Units
V
V

DM54

0.25

0.4

DM74

0.35

0.5

DM74

0.25

0.4

Enable T

0.2

clock

0.2

Load

0.2

Others

0.1

Enable T

40

Load

40

Clock

40

Others

20

Enable T

-0.8

Clock

-0.8

Load

-0.8

V

mA

I,A

mA

-0.4

Others
DM54

-20

-100

DM74

-20

-100

Short Circuit
Output Current

Vcc=Max
(Note 2)

ICCH

Supply Current With
Outputs High

Vcc= Max
(Note 3)

18

31

mA

ICCL

Supply Current With
Outputs Low

Vcc=Max
(Note 4)

18

32

mA

los

Nole 1: Alltypicals are at VCC=SV, TA=2S"C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Nole 3: ICCH is measured with the load high, then again with the load low, with all other inputs high and all outputs
Note 4:

open.

'CeL is measured with the clock input high, then again with the clock input low, with all other inputs low and all outputs opEm.

4·183

mA

I

'LS162 and 'LS163 Switching Characteristics

at Vcc =5Vand TA=25°C

(See Section 1 for Test Waveforms and Output Load)

Parameter

From
(Input)
To
(Output)

fMAX Maximum Clock
Frequency

RL = 2 kn
C L =15pF
Min

Typ

25

32

CL=50 pF
Max

Min

Typ

20

25

Units
Max
MHz

tpLH Propagation Delay
Time Low to High
Level Output

Clock to
Ripple
Carry

16

24

20

30

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock to
Ripple
Carry

19

30

25

38

ns

tpLH Propagation Delay
Time Low to High
!,.evel Output

Clock to
Any Q
(Load High)

15

22

18

27

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock to
Any Q
(Load High)

19

27

25

38

ns

tpLH Propagation Delay
Time Low to High
Level Qutput

Clock to
Any Q
(Load Low)

16

24

19

30

ns,

tpHL Propagation Delay
Time High to Low
Level Output

Clock to
. Any Q
(Load Low)

21

29

26

38

ns

tpLH Propagation Delay
Time Low to High
Level Output

Enable T
to Ripple
Carry

13

18

16

27

ns

tpHL Propagation Delay
Time High to Low
Level Output

Enable T
to Ripple
Carry

10

15

16

27

ns

tpHL Propagation Delay
Time High' to Low
Level Output

Clear
to
Any Q
(Note 1)

25

35

31

45

ns

Note 1: The propagation delay clear to output IS measured from the clock input transition.

",

4-184

c

s:
U'I

Logic Diagrams

-'="
r-

LS160A

(2)

CLOCK

~

"v

I

(3)

DATA A
(1)

CLEAR

",.

V
(10)

ENABLE T
(5)

DATAC

0

K

L
j

~

-

»
C
s:

(14)

0'--<0.- OA
CLOCK

1 JCL~ARO

~

1

r-

....
en

C/)

0

}>
C

K

s:
U'I

(13)

-'="
r-

0_0-- OB

>~I

(9)

LOAD
(7)

~

0'-

~

(4)

DATA B

ENABLE P

tn
....

~
JCLyARO

.~I

~

l

-

O~

K

CLOCK

JCLrRO

....
....en
»
c
s:

C/)

~
r-

....

C/)

....

en

}>

Oc

C

l

s:
U'I
-'="
r-

....
»
c
s:
C/)

en
I\)

(6)

DATAD

~
J

~

- III

K

~
r-

a l b aD

'-c

1

CLOCK

....
en

C/)

0-

I\)

JCLEAR

}>

Y

~

LS161A Is similar; however, the clear Is asynchronous as shown for LS160A decade counters.

C

(15) RIPPLE

CARRY
OUTPUT

TLIF/6397·2

s:
U'I

-'="
r-

tn
....
en
Co)

-c»s:
~

r-

....en

C/)
Co)

»

4·185

Logic Diagrams

(Continued)
LS163A

~

..
(2)

CLOCK

.I

(3)
DATA A

(1)
CLEAR

r.
(4)
DATA B

(9)n
LOAD

(7)

ENABLE P

v
(10)

ENABLE T

(5)
DATAC

(6)
DATAD

....

~

v

K
CLOCK

l

~

~

r

"~
(13)

Q-o--

~

QB

CLOCK

J

"l

K

(12)

Q r-o-- QC

~I

~

J

K

~I

~

(14)

Q ...... 0 - -

t-<

CLOCK

J

"~

K

(11)

Qf- ~ QD
L-(

1

CLOCK

J

~

at-

(15) RIPPLE
CARRY
OUTPUT

LS162A is similar; however, the clear Is synchronous as shown for the LS163A binary counters.
TLIF16397·3

4-186

Timing Diagrams
LS,16DA, LS162A SYNCHRONOUS DECADE COUNTERS
TYPICAL CLEAR, PRESET, COUNT AND INHIBIT SEQUENCES
CLEAR
UI&QA
CLEAR
LS1&ZA

I:
LOAO

...--+--,--------------

DATA

lNP~TS

.---+--,-------------r-----1f----,-------------- - --- - - - - - -- +,
~-

---+-~

CLOCK _ _ _

LSI6DA:
CLOCK!

lSI6ZAi

+_t-'

ENABLEP _ _ _

Sequence:
(11
(2)

Clear autputs ta zera
Preset ta BCD seven

(3)

Count to eight, nine, zero, one, two, and three

(4)

Inhibit

+-+,

ENABLET _ _ _

---COUNT---- ----INHIBIT---CLEAR PRESET

LS161A, LS163A SYNCHRONOUS BINARY COUNTERS
TYPICAL CLEAR, PRESET, COUNT AND INHIBIT SEQUENCES
CLEAR
LS161A
CLEAR

LSl&lA
LOAD

r--------------

A

DATAl
INPUTS

B==~r==============
r--t--'-------------"L _ _ _ _ _ _ _ _ _ _ _ _ _ _

~_+_-_r--------------

Sequence:

ClOCK---+,

LS161A

CLOCK

LS161A

+ __I-I
+ __I-I

ENABLEP _ _ _

ENABLE T _ _ _

'_I=~

-

-+-r-+--'

D,

RIPPLED~~~~~---+-+::"--1I::1J;--,,::'4-~"
---CDUNT--- ---INHIBIT----

CLEAR PRESET

4-187

(1)
(2)

Clear autputs ta zera
Preset ta binary twelve

(3)

Count to thirteen. fourteen, fifteen. zero, one, and two

(4)

Inhibit

Parameter Measurement Information
SWITCHING TIME WAVEFORMS

CLOCK
INPUT

OV

fpLH

(MEASURE AT tN .... )
OUTPUT
DA

VOH
VOL
VOH

OUTPUT
D.

OUTPUT

ne
OUTPUT
00

RIPPLE

VOL
VOH
VOL

VOH
VOL
VOH

C~RRV

OUTPUT VOL

Note A: The input pulses are supplied by generators having the following characteristics: PRR ~ 1 MHz, duty cycle ~ 50%, ZOUT ., 50n. For
LS160A through LSI63A, tr ~ 10 ns, tf:; 10 ns. Vary PRR tomeasure fMAX.
Note B: Outputs QO and carry are tested at t n+l0 for LSI60A, LSl6.2A and at t n +16 for LS161A, LS163A where tn is the bit time when all
outputs are low.
'
Note C. For LS160A through LS163A, VREF

= 1.5V.

SWITCHING TIME WAVEFORMS
CLOCK INPUT 3.0V - - - - - - - " " ' .
LS160A
LS161A OV - - - - - - - - I ,....- . . J
3.0V
,---r==~===-----CLEAR
INPUT
OV--.....-..1
LOAD 3.0V
INPUT
DATA INPUTS
A. S, C. AND D
Q

O~~~~i:

--+---+---If+.-....

OV ---::t:::-~~---f
VOH

DA AND 00 O~~~~J: VOL
VOH
00 AND Dc OUTPUTS
LS160A VOL
ENABLE P OR
ENABLE T

--i--+=="{

OV--~----+-----~~~
3.0V

3.0V

---::-+':--+'-+--""""-..,..,,,",'1

--+--'-+--...,...,--f-I

--11----+---+--,,...;"""'

OV_--+_ _+-_..,...I-JI
VOH--r---+--~~~-I----~~,~~I

CARRV

VOL--~===l~==~r---r-----'

r---------

CLOCK INPUT 3.0V
LS162A
LS163A
OV-o O~~~~~ VOH _ _ _...;;~;:;:;:

DA AND 00 O~~~~:: VOL
D. AND Dc OUTPUTS VOH
LS162A

-----=:f;:fpH:::L+~---..,..fo:-'l
----.;.:.;~I
VREF

VOL-------~----------'

Note A: The input pulses are supplied by generators having the following characteristics: PRR :; 1 MHz, dutY cycle:; 50%, ZOUT '" 50n. For
LS160A through LSI63A, tr :; 6 ns, tf :; 6 ns. Vary PRR to measure fMAX.
Note B: Enable P and enable T setup times are measured at tn+O.
Note C: For LS160A through LS163A, VREF = 1.3V.

4·188

~National

~ Semiconductor
DM54LS164/DM74LS164 a·Bit -8erialln/Paraliel Out
Shift Registers
General Description

Features

These 8-bit shift registers feature gated serial inputs and
an asynchronous clear. A low logic level at either input inhibits entry of the new data. and resets the first flip-flop to
the low level at the next clock pulse. thus providing complete control over incoming data. A high logic level on either
input enables the other input. which will then determine the
state of the first flip-flop. Data at the serial inputs may be
changed while the clock is high or low. but only information
meeting the setup, and hold time requirements will be
entered. Clocking occurs on the low-ta-hlgh level transition of the clock input. All Inputs are diode-clamped to
minimize transmission-line effects.

•
•
•
•
•

Gated (enable I disable) serial inputs
Fully buffered clock and serial inputs
Asynchronous clear
Typical clock frequency 36 MHz
Typical power dissipation 80 mW

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
Storage Temperature Range

7V
7V
-65·Ct0150·C

NOla I: The "Absolule Maximum Rallngs" are Ihose values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual-In-Line Package
OUTPUTS
Vee

114

QH

13

OG

12

Inputs

OF

0e

11

10

CLEAR CLOCK

8

9

Clock

A

a

QA

Qa

L

X

H
H
H
H

L

X
X

X
X

H
L

H

L
aAO
H
L
L

L
aBO
aAn
aAn
aAn

<

r-

Outputs

Clear

I
I
I

x

X
L

---

QH

---

L
aHO
aGn
aGn
aGn

---

= High Level (steady state), L = Low Level (steady state)
X = Don't Care (any input. including transitions)
t = Transition from low to high level

-------

H

1

2

~
SERIAL INPUTS

13

~A

I" Is
Qa

Qc

OUTPUTS

54LS164 (J)

I" 17

Qq

GND
TL/Ff6398-1

0AO. QBO. QHO = The level of QA. 0e. or QH. respectively, before the indicated

sl8ady~st8te

input condillona were established.

0An. QGn .. The level of QA or QG before the most recent
clock; indicates a one-bit shilt.

t transition of the

74LS164(N)

Logic Diagram
C~AR~19~)-------qI~>---~-------t--------t-------~------~~------~-------1~------'

~OCK~18~)----~l.>~~--4---~---+--~~--+---~--~---1~--~--t---~--~---4----,

OUTPUTS

TUF/6398-2

4-189

•

,

Recommended Operating Conditions
DM54LS164

Parameter

Symbol
Vcc

Supply Voltage

V,H

High Level Input
Voltage

V,l

Low Level
Input Voltage

10H

High Level Output
Current

IOl

Low Level Output
Current

fClK

Clock Frequency

tw

Pulse Width

I
I

DM74LS164

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2
0.8

-0.4

-0.4

4
0

25

0

20

20

Clear

20

20

V
V

0.7

Clock

Units

V
mA

8

mA

25

MHz
ns

tsu

Data Setup Time

15

15

ns

tH

Data Hold Time

5

5

ns

tREl

Clear Release Time

TA

Free Air Operating
Temperature

30

Electrical Characteristics
Symbol

30

-55

125

ns

0

70

over recommended operating free air temperature (unless otherwise noted)

'Parameter

Min

Typ
(Note 1)

DM54

2.5

3.4

2.7

3.4

Conditions

Max

V,

Input Clamp Voltage

VOH

High Level Output
Voltage

Vcc=Min
10H = Max
V,L = Max
V,H = Min

DM74

Low Level Output
Voltage

Vcc=Min
10L=Max
V,L = Max
V'H=Min

DM54

0.25

0.4

DM74

0.35

0.5

DM74

0.25

0.4

. VOL

·C

Vcc = Min, I, = - 18 mA

IOL=4 mA
Vee=Mi(l

-1.5

Units
V'
V

V

I,

Input Current@Max
Input Voltage

Vec'= Max, V, = 7V

0.1

mA

I'H

High Level Input
Current

Vcc = Max, V, = 2.7V

20

p.A

I,L

Low Level Input
Current

Vcc = Max, V, = 0.4V .

-0.4

mA

los

Short Circuit
Output Current

Vce= Max
(Note 2)

mA

Supply Current

Vee = Max (Note 3)

Icc

DM54

-20

-100

DM74

-20

-100
16

27

mA

Note': All typicals are at Vee=5V. TA=25°e.
Note 2: Not more than one output should be shorted al a time, and the duration should not exceed one second.
Note 3:
Input.

ICC is measured with all outputs open, the SERIAL input grounded, the CLOCK Input at 2.4V, and a momentary ground, then 4.5V, applied to the CLEAR

4-190

Switching Characteristics
From
(Input)
To
(Output)

Parameter

fMAX Maximum Clock
Frequency

at Vee = 5V and TA = 25°C ,(See Section 1 for Test Waveforms and Output Load)
RL=2 kG
C L =50 pF

CL=15 pF
Min

Typ

25

36

Max

Min

Typ

Units
Max
MHz

tpLH Propagation Delay
Time' Low to High
Level Output

Clock
to
Output

17

27

20

30

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to'
Output

21

32

28

40

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
Output

24

36

30

45

ns

Timing Diagram
CLEAR-U

SERIAL {
INPUTS

LS

A

B

~

CLOCK

~

QA : : : '
Os

~::'

Qc : : : '

---,

r-LJ-L f-

QD ___

OUTPUTS
Qe

:::1

.---L..rL

00

:::1

r---4r---L

ClH

:::1

rL

OF

:::1

I

I

I

CLEAR

CLEAR

TLlF/639B-3

4-191

•

'
~ Semiconductor
~National

DM54LS165/DM74LS165 a·Bit Paralielln/Serial Output
Shift Registers
General Description

Features

The'Je are B-bit serial shift registers which shift the data in
the direction of QA toward QH when clocked_ Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shiftlload
input. These registers also feature gated clock inputs and
c-<>mplementary outputs from the eighth bit.

• Complementary outputs
• Direct
,
. overriding (data) inputs
• Gated clock inputs
• Parallel-to-serial data conversion

Clocking is accomplished through a 2-input NOR gate,
permitting one input to be used as a clock-inhibit function_
Holding either of the clock inputs high inhibits clocking, and
holding either clock input low with the load input high enables the other clock input. The clock-inhibit input should
be changed to the high level only while the clock input is
high_ Parallel loading is inhibited as long as the load input is
high. Data at the parallel inputs are loaded directly into the
register on a high-to-Iow transition of the shift/load input,
regardless of the logic levels on the clock, clock inhibit, or
serial inputs.

Connection Diagram

• Typical frequency 35 MHz
.'Typical power dissipation 105 mW

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
Storage Temperature Range

7V
7V
-65'Cto150'C.

Nato 1: The "Absolule Maximum Ratings'" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual-In-Llne Package

~~~ ...,.O=-PA_R_AC=-LL_E~L_IN-=:_UT_S-:A"'" ~~~~L OU~:UT

VCC

116

,IS

2,
SHIFT I CLOCK

14

13

3

4

E

12

G

LOAD

PARALLEL INPUTS

54LS165 (J)

H

11

10

6

7

18

OUTPUT. GND
•
QH
TLIF16399·1

74LS165 (N)

Function Table
Inputs
Shlft/ Clock
Load Inhibit
L
H
H
H
H

X
L
L
L
H

Clock

Serial

X
L

X
X

t
t

X

Parallel

Internal
Outputs

A ... H

QA

Q8

H
L

a ... h
X
XX

X

X

a
QAO
H
L
QAO

b
QBO
QAn
QAn
QBO

Output
QH
h
QHO
QGn
QGn
QHO

H = High Level (steady state), L = low Level (steady state)
X = Don't Care (any input. including transitions)
t = Transition from low·to-high level
a ... h = The level of steady-state 'input at inputs A through H. respectively.
0AO. Oeo. aHO = The level of QA. aS. or QH. respectively. before the indicated steady· stale
input conditions were established.
0An. QGn == The level dl QA or QQ. respectively. before the moat recent

clock.

4-192

t transition of the

c
s::
en

Recommended Operating Conditions
DM74LS165

DM54LS165
. Symbol

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level
Input Voltage

Min

'Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

-0.4

-0.4

fCLK

Clock Frequency (Note 1)

fCLK

Clock Frequency (Note 2)

0

tw

Pulse Width

Clock

25

25

Load

15

15

TA

Free Air Operating
Temperature

VOL

25

0

20

IIH

los

Icc

C

25

MHz

0

20

MHz

10

10

20

20

Enable

30

30

Shift

45

45

over

ns

ns

ns

0

0
-55

125

recommend~'d operating
Conditions

mA

0

Parallel

70

0

·C

free air temperature (unless otherwise noted)
Min

Typ
(Note 3)

·Vee= Min,ll= -18 mA

Max
-1.5

Units

V

High Level Output
Voltage

Vee= Min
10H = Max
VIL= Max
VIH= Min

OM54
2.5
3.4
I-O-M-74----+-2-.7-+---3-.4--+----l

V

Low Level Output
Voltage

Vee=Min
10L = Max
VIL=Max
VIH=Min

OM54
0.25
0.4
t-,-O-M-7-4----+---+--0-.3-5--+-0-.5--I

V

0.25

OM74

IOL=4mA
Vee = Min
II

en

en
,'0)
"'"

mA

Serial

Parameter
Input Clamp Voltage

~

8

4

Electrical Characteristics
Symbol

en
'm
"'"

s::

Low Level Output
Current

Hold Time

~

r-

V

0.8

IOL

tH

V

0.7

High Level Output
Current

Setup Time

V

2

2

IOH

tsu

Units

0.4

Input Current@Max
Input Voltage

Vee= Max
VI =7V

Shift/Load

0.3

Others

0.1

High Level Input
Current

Vee = Max
VI=2.7V

Shift/Load

60

Others

20

Low Level Input
Current

Vee = Max
VI =0.4V

Shift/Load

-1.2

Others

-0.4

Short Circuit
Output Current

(Note 4)

Supply Current

Vce = Max (Note 5)

Vee=Max

OM54

-20

-100

DM74

_ 20

- 100

r---------~----+-------;_----;

21

36

mA

p.A
mA

mA

mA

Note 1: CL = 15 pF, RL = 2 kO.
Note 2: eL = 50 pF, RL = 2 kO.
Note 3: All typicals are at Vee=5V, TA=25'C.
Note 4: Not more Ihan one output should be shorted at a time, and the duration should nol exceed one second.
Note 5: With all outputs open, clock Inhibit and shlftlload at 4.5V, and a clock pulse applied to the CLOCK Input, ICC is measured flrsl wllh the parallel in,
puts al 4.5V, then again grounded.
I
.
4-193

r-

en

Switching Characteristics
Parameter

From
(Input)
To
(Output)

'MAX Maximum Clock
Frequency

at Vcc=5V and TA=25"C (See Section 1 for Test Waveforms and Output Load)
RL=2kn
CL=15 pF
Min

Typ

25

35

CL=50 pF
Max

Min

Typ

20

30

Units
Max
MHz

tpLH Propagation Delay
Time Low to High
Level Output

Load
to
Any Q

22

35

25

38

ns

tpHL Propagation Delay
Time High to Low
Level Output

Load
to
AnyQ

22

35

28

42

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
Any Q

27

40

30

45

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
Any Q

28

40

35

52

ns

tpLH Propagation Delay
Time Low to High
, Level Output

H
to
QH

14

25

17

26

ns

tpHL Propagation Delay
Time High to Low
Level Output

H
to
QH

21

30

28

42

ns

tpLH Propagation Delay
Time Low to ,High
Level -Output

H
to

21

30

25

38

ns

QH

tpHL Propagation Delay
Time High to Low
Level Output

H
to
QH

16

25

22

33

ns

/

4·194

c
3:

Logic Diagram.

Z!
r-

(J)

.....

PARALLEL INPUTS

-

m
c
3:

(91

OUTPUT OH
(71

~~=~"i .:.(';.:O.:.I---1l><~_ _++-I

~
r-

(J)

.....

m

OUTPUTQH

SHIFT! ('I
LOAD - - - - - . q
(21
CLOCK ' ; " ' : " - - - ,

CLOCK .;,.('_5.;,.1_ _-1
INHIBIT

TlIF16399·2

Timing Diagram
TYPICAL SHIFT, LOAD, AND INHIBIT SEQUENCES
CLOCK

CLOCK INHIBIT
SERIAL INPUT

---;;;...----t--------------------

SHIFT/LOAD

A

C

D ___
DATA

~------4--------------------------------

E

F __

~~------~-----------------------------

G

H

H

OUTPUTOH

H

OUTPUTQH
I-INHIBIT-+-----_-SERIAL S H I F T - - - - - - - _
LOAD
TLIF16399·3

4·195

•

~National

~ Semiconductor
DM54LS166/DM74LS166 a·Bit Paralielln/Serial Out
Shift Registers
clock to be Iree-running, and the register can be stopped on
command with the other clock input. The clock-inhibit input
should be changed to the high level only while the clock
input is high. A buffered, direct clear input overrides all other inputs, including the clock. and sets .allllip-liops to zero.

General Description·
These parallel-in or serial-in, serial-out shift registers leature gated clock inputs and an overriding clear input. All inputs are buffered to lower the drive requirements to one
normalized load. and input clamping diodes minimize
switching transients io simplily system design. The load
mode is established by the shift/load input. When high, this
input enables the serial data input and couples the eight
flip-Ilops lor serial shifting with each clock pulse. When
low, the parallel (broadside) data inputs are enabled and
synchronous loading occurs on the next clock pulse. During
parallel loading, serial data II ow is inhibited. Clocking is accomplished on the low-to-high-Ievel edge olthe clock pulse
through a two-input NOR gate, permitting one input to be
used as a clock-enable or clock-inhibit lunction. Holding either 01 the clock inputs high inhibits clocking; holding either
low enables the other clock input. This allows the system

Connection Diagram

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
Storage Temperature Range

7V
7V
-65·Cto150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual·ln·Line Package
PARALLEL INPUTS
PARALLEL
SHIFT / INPUT OUTPUT ,--~~--..
VCC LOAD
H
QH
G
F
E

15

116

13

14

11

12

CLEAR

9

10

-

0-

2

SERIAL
INPUT

4

3

S

A

C

5
D

6

7

I

B

CLOCK CLOCK GND
INHIBIT

PARALLEL INPUTS

TLJFJ6400·1

74LS166 (N)

54LS166 (J)

Function Table
Inputs
Clear

Shift/ . Clock
Load Inhibit

L
H
H
H
H

X
X

H

X

L
H
H

Clock

X

X

L
L
L
L
H

L

t
t
t
t

Serial

X
X
X
H
L

X

Internal
Outputs

Parallel

QH

A ... H

QA

Qs

X
X

L
aAO
a
H
L
aAO

L
aeo
b
aAn
aAn
aeo

.a ... h

X
X
X

H = High level (steady state), l= Low level (steady stale)
X = Don't Care (any input, including transitions)
t = Transition from low to high level
a ... h = The level of steady-state input at inputs A through H, respectively
QAO, Qao, aHO = The level of QA, 0a, 0H. respectively, before the indicated
sleadY'state input conditions were established
0An. 0Gn = The level of 0A. 0G. respectively, before the mo"st recent lransi- ' """ __
tion of the clock

t

4-196

Output

L
aHa
h
aGn
aGn
aHa

Recommended Operating Conditions
DM74LS166

DM54LS166
Symbol

Parameter

Min

Nom

Max

Min

Nom

Max

5

5.5

4.75

5

5.25

Vcc

Supply Voltage

4.5

VIH

High Level Input
Voltage

2

VIL

Low Level
Input Voltage

.IOH

High Level Output
Current

10L

Low Level Output
Current

'CLK

Clock Frequency
(Note 1)

0

25

Clock Frequency
(NotE! 2)

0

20

tw

tsu

Pulse Width

Setup Time

tH

Hold Time

TA

Free Air Operating
Temperature

0.7

0.8

-0.4

-0.4

mA

8

mA

0

25

MHz

0

20

MHz

Clock

20

20

Clear

20

20

Mode

30

30

Data

20

20

0
125

ns

ns
70

0

'C

over recommended operating free air temperature (unless otherwise noted)

Parameter

Conditions

Min

Typ
(Note 3)

Max

VI

Input Clamp Voltage

Vcc= Min, 11= -18 mA

VOH

High Level Output
Voltage

Vcc=Min
10H= Max
VIL=Max
VIH=Min

DM54

2.5

3.4

DM74

2.7

3.4

Low Level Output
Voltage

Vcc= Min
10L=Max
V IL = Max
VIH=Min

DM54

0.25

0.4

DM74

0.35

0.5

IOL=4 mA
Vcc=Min

DM74

0.25

0.4

VOL

V

ns

0

-55

V
V

4

Electrical Characteristics
Symbol

2

Units

-1.5

Units
V
V

V

II

Input Current@Max
Input Voltage

Vcc = Max, VI = 7V

0.1

mA

IIH

High Level Input
Current

Vcc=Max, VI = 2.7V

20

/'A

IlL

Low Level Input
Current

Vcc = Max, VI = 0.4V

-0.4

mA

los

Short Circuit
Output Current

Vcc=Max
(Note 4)

mA

Supply Current

Vcc= Max (Note 5)

Icc

DM54

-20

-100

DM74

':"20

-100
22

38

mA

Note 1: CL = IS pF and RL = 2 kll.
Not. 2: CL = SO pF and RL = 2 kll.
Not.3: Aillypicals are at VCC = SV, TA = 2S'C.
Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Not. 5: With all outputs open, 4.SV applied to the serial Input, all other inputs except the CLOCK grounded, ICC is measured after a momentary ground,

then 4.SV, is applied to the CLOCK.
4·197

Switching Characteristics

at Vcc=5V and TA=25°C (See Section 1 for Test Waveforms and Output Load)

From
(Input)
To
(Output)

Parameter

RL=2 kll
CL=15 pF

fMAX Maximum Clock
Frequency

Min

Typ

25

35

CL=50 pF

Max

Min

Typ

20

30

Units
Max
MHz

tpLH Propagation Delay
Time Low to High
Level Output
(

Clock
to
Output

8

24

35

27

38

ns

tpHL Propagation Delay
Time High·to Low
Level Output

Clock
to
Output

8

23

35

29

41

n5

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
Output

6

19

30

25

36

ns

Parameter, Measurement Information
Voltage Waveforms
IIW(CLEAR)
3.0V
CLEAR
INPUT

VREF

VREF

OV
I--ISETUP-

CLOCK
INPUT

3'O~~D
VREF
VREF

~

~~
VREF

-..- VREF

~~~ -ttJ7.t:~

OV

-

YREF!

VOH
OUTPUT

~

(NoteD)

~

DATA 3.0V
INPUT

(SEE TEST TABLE)

~

a

VREF

tPHL

(CLEAR·O)

-

VREF

:~t~CK.O)

VREF
-

VREF

\VREF

:~~~CK.O)
VREF

VOL
TLIFI640()'4

Test Table For Synchronous Inputs
Data Input
For Test
H
Serial Input

Shift/Load

OV
4.5 V

Olltput Tested
(See Note C)
QH atTN+l
QH at TN+8

Note A: The clock pulse has the following characteristics: IW(clock) 2. 20 ns and PRR = 1 MHz. The clear pulse has the following characterislics: tW(elear)
tHOLD = 0 ns. When testing fMAX. vary the clock PRR.
Note 8: A clear pulse is applied prior to each test.
Note C: Propagation delay times (lPLH and tPHL> are measured al tn+ l' Proper shifting of data i.s verified al In+8 with a functional test.

Not. D: tn = bit time before clocking transition
tn+ 1 = bit time after one clocking transition
In+8 .,. bit time after eight clocking transitions
NoteE: VREF=1.3V.

4·198

:=::

20 ns and

.--------------------------------------------------------------------,0

i:
~

Logic Diagram

fi)
.....

e

c

i:
~
r-

en
....

i

(4)

(31

B

(51

C

(101

(12)

(111

E

D

F

(141
G

(7) (61
H CLOCK CLOCK
INHIBIT

PARALLEL INPUTS

TLlFJ6400·2

Timing Diagram

Typical Clear, Shift, Load, Inhibit, and Shift Sequences
CLOCK

CLOCK INHIBIT
CLEAR
SERIAL INPUT
SHIFT/LOAD

A__t-+-__________________-r__

~

B--t-+--------------------r----~----_1~-----------------------C~__r_----------------_1--~
PARALLEL
INPUTS

D __~~--------------------~----~~----~~~----------------------___
E __~~------------------~---J

G~r_r_----------------_1--~
H __~+-------------------~--~
OUTPUT 'QH ':: :...--'______________________..
t-------SERIAL SHIFT--------I
CLEAR

LOAD
TLlFJ6400·'

4·199

~National

~ Semiconductor
DM54LS168A/DM74LS168A, DM54LS169A/DM74LS169A
Synchronous 4·Bit Up/Down Counters

General Description
These synchronous presettable counters featUi e an internal carry look-ahead for cascading in high-speed counting
applications. Synchronous operation is provided by having
all flip-flops clocked simultaneously, so that the outputs all
change at the same time when so instructed by the countenable inputs and internal gating. This mode of operation
helps eliminate the output counting spikes that are normally
associated with asynchronous (ripple clock) counters. A
buffered clock input triggers the four master-slave flip-flops
on the rising edge of the clock waveform.

regardless of the level of the clock input. All inputs are diode clamped to minimize transmission-line effects, thereby
simplifying system design.
These counters feature a fully independent cloCk circuit.
Changes at control inputs (enable P, enable T, load,
up I down), which modify the operating mode, have no effect
until clocking occurs. The function of the counter (whether
enabled, disabled, loading, or counting) will be dictated
solely by the conditions meeting the·stable setup and hold
times.

These counters are fully programmable; that is, the outputs
may each be preset either high or low. The load input circuitry allows loading with the carry-enable output of cascaded counters. As loading is synchronous, setting up a
low level at the load input disables the counter and causes
the outputs to agree with the data inputs after the next
clock pulse.

Features
• Fully synchronous operation for counting and
programming.
• Internal look-ahead for fast counting.
• Carry output for n-bit cascading:
• Fully independent clock circuit'
• 'LS168A-decade counter

The carry loo'k-ahead circuitry permits cascading counters
for "-bit synchronous applications without- additional gating. Both count-enable inputs (P and T) must be' low to
count. The direction of the colint is determined by the level
of the up I down input. When the input is high, the counter
counts up; when low, it counts down. Input T is fed forward
to enable the 'carry outputs. The carry output thus enabled
will produce a low-level output pulse with a duration approximately equal to the high portion of the OA output when
counting up, and approximately equal to the low portion of
the OA output when counting down. This low-level overflow
carry pulse can be used to enable successively cascaded
stages. Transitions at the enable P or T inputs are allowed

• 'LS169A-binary counter

Absolute Maximum Ratings (Note 1)
7V

Supply'Voltage
Input Voltage
Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram
Dual-I.n-Line Package
RIPPLE
CARRY
OUT

Vcc
116

OUTPUTS
ENABLE
OA

15

OB

14

Oc

13

i

OD

LOAD

11

12

10

9

-

2
U/O

CLOCK

3
A

7V
-65'Cto150'C

4
B

5

6

C

D

. TLlFI640'·,

74LS168A (N)
74LS169A (N)
4-200

I8

P

DATA INPUTS •

54LS168A (J)
54LS169A (J)

7

ENABLE GND

Recommended Operating Conditions
Symbol

DM54LS168A, LS169A

Parameter

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

.5

5.25

Vcc

Supply Voltage

V 1H

High Level Input
Voltage

V1L

Low Level
Input Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

fCLK

.Clock Frequency
(Note 1)

0

25

Clock Frequency
(Note 2)

0

20

tw

Clock Pulse Width

tsu

Setup Time

2

tH

Hold Time
Free Air Operating
Temperature

Nota 1:
Nota 2:

2
0.7

0.8

-0.4

-0.4

V

V
mA

8

mA

0

25

MHz

0

20

MHz

25

ns

20

20

ns

20

·20

25
Data

Units

V

4

Enable
'for P

TA

DM74LS168A, LS169A

Min

Load

25

25

UfO

30

30

0

ns

0

-55

125

0

70

·C

CL =15 pF and RL =2 kit
CL =50 pF and RL =2 kll.
I

-

4-201

-

'LS168A and 'LS169A Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol

Parameter

Min

Typ
(Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

,

Max

VI

Input Clamp Voltage

VOH

High Level Output
Voltage

Vcc=Mln
IOH = Max
VIL=Max
V1H=Mln'

Low Level Output
, Voltage

VC;c=Mln
IOL=Max
VIL=Max
VIH=Min

DM54

0.25

0.4

DM74

0.35

0.5

IOL=4mA
Vcc=Mln

DM74

0.25

0.4

VOL

II

IIH

IlL

los

Icc

Units

-1.5

Vcc=Min,ll= -18 mA

V

Input Current@Max
Input Voltage

Vcc= Max
V,=7V

Enable T

0.2

Others

0.1

High Level Input
CUFrent

Vcc=Max
VI=2.7V

Enable T

40

Others

20

Low Level Input
Current

Vcc=Max
VI = 0.4V

Enable T

-0.8

Others

-0.4

Short Circuit
Output Current

Vcc=Max
(Note 2)

DM54 ,

-20

-100

DM74

-20

-100.

Supply Current

Vcc= Max (Note 3)

20

34

Note 1: All typlcals are at VCC=SV, TA=2S'C.
Note 2: Not more than one output should be shor~ed at a time, and the duration should not exceed one second.

Note 3: ICC Is measured after a momentary 4.SV, then ground, Is applied to the CLOCK with all other inputs grounded and all the outputs open.

,

4-202

V

V

mA

p.A

mA

mA

mA

'LS168A and 'LS169A Switching Characteristics

at Vcc=5V and TA=25"C

. (See Section 1 for Test Waveforms and Output Load)

Parameter

f MAX Maximum Clock
Frequency

From
(Input)
To
(Output)

,

RL=2 kn
C L =15 pF
Min

Typ

25

32

CL=50 pF
Max

Min

Typ

20

28

Units
Max
MHz

tpLH Propagation Delay
Time Low to High
Level Output

Clock to
Ripple
Carry

23

35

26

39

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock to
Ripple
Carry

23

35

29

44

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
AnyO

13

20

16

24

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
Any 0

15

23

21

32

ns

tpLH Propagation Delay
Time Low to High
Level Output

Enable f
to Ripple
Carry

12

18

15

24

ns

tpHL Propagation Delay
Time High to Low
Level Output

Enable f
to Ripple
Carry

12

18

18

28

ns

tpLH Propagation Delay.
Time Low to High
Level Output

Up/Down
to Ripple
Carry
(Note 1)

17

25

20

30

ns

tpHL Propagation Delay
Time High to Low
Level Output

Up/Down
to Ripple
Carry
(Note 1)

19

29

20

38

ns

,

Note 1: The propagation delay from UPIDOWN to RIPPLE CARRY must bo moasured with the counter at either a minimum or a maximum count. As the
logic lovel of tho upldown input Is changed, the ripple carry output will follow. If the count Is minimum, the ripple carry output transition will be in phase. If
the count Is maximum, the ripple carry output will be out of phase.

4·203

Logic Diagram
LS168A Decade Counter

DATA A

Cl.OCK

~

(3)

(2)

~aA

(14)

f

~

aA

+-,

~

~
DATAB

(4)

yc\a8

W

W V~ac

(5)

UP/OWN

(12)

ac

if
·r

(1)

1

08

-

h

DATAC

(13)

v

to
. '-H)-

~.r D
}'

DATAD

LOAD
ENABlEP

ENABLET

(0)

:--f

.

)-

&r

(0)

(7)

l

(10)

[

f

(11)

00

..J
}-,
'----J'

(15)
RIPPLE CARRY

TL/F/6401·2

4-204

~----------------------------------------------------------------IC

s:

Logic Diagram

~

~
....

LS169A Binary Counter

DATA"

CLOCK

~

'"
,,,

~C

s:

*r~

0.

elK QA
R

~

en
co

l>

E
OATA B

~

'4)

~

~r~

OB

L-V
h

DATA C

UPtOWN

W
~ *r~

'"

(1)

"

v

I

OC

h2;-

...

r

~

'--t-f

~
DATA 0

LOAD
ENABLE P

ENABlE

,.)

t---f

r
J""""

t}

,.)
'7)

l' 1101

[

1~

QD

~R.

l .........

f-'

"

'------'

115)

RlPP!..ECARRY

TLlF/6401·3

4-205

~

~
....

Timing Diagrams

LS168A. Decade Counters
Typical Load, Count, and Inhibit Sequences
LOADL-j

A

L

PANDT

QD - - - ,

RIPPLE

O~~:~~

----r--I+--,

--- 17
.J
I

8

9

0

2

2

II---COUNTUP-I-INHIBIT-I

2

o

9

8'

7

I-----COUNT DOWN -

'--v--'
LOAD

Sequence
Sequence
Sequence
Sequence

1:
2:
3:
4:

TlIF/6401·4

Load (preset) to BCD seven
Count up to eIght, nine, zero, one and two
Inhibit
Count down to one, zero, nine. eight and seven

4·206

Timing Diagrams

(Continued)

LS169A Binary Counters
Typical Load, Count, and Inhibit.Sequences
LOAD

L-J

.-

A

L_

B
DATA
INPUTS
C

L_

D

L..._

CLOCK

QC __

---.. .

QD __

~=:~~

...J
...J

--11+--..

OUTPUT __ ....l

I

13

1

14

15

0

2

2

II---COUNT uP----tI-·-INHIBIT--I

2

o.

15

14

13

1-1-·--COUNT DOWN - - - -

~

LOAD

TlfF/6401-5

Sequence 1: Load (preset) to binary thirteen

Sequence 2: Count up to fourteen, fifteen. zero, one and two
Sequence 3: Inhibit
Sequence 4: Count down to one, zero, fifteen. ~ourteen and thirteen

4·207

•

'
~ Semiconductor
~National

DM54LS170/DM74LS170 4 by 4 Register Files
General Description
These 16-bit.TTL register files sre organized as 4 words of
4 bits each, and separate on-chip decoding is provided for
addressing the four word locstions to either write-In or retrieve data. This permits writing into one location and resdIng from another word location, simultaneously.
Four data inputs are available to supply the 4-bit word to be
stored. Location of the word is determined by the write-address inputs A and e, in conjunctioll with a write-enable signal: Data applied at the inputs should be in its true form.
That is, if a high-level signal is desire!! from the output, a
high level is applied at the data input for that particular bit
location. The latch inputs are arranged so that new data will
be accepted only if both internal address gate inputs are
high. When this condition exists, data at the 0 input is
transferred to the latch output. When the write-enable input, GW, is high, the data inputs are inhibited and their levels can cause no change in the information stored in the
internal latches. When the read-enable input, GR, is high,
the data outputs are inhibited and remain high.
The individual addresa lines permit direct 'reading of data
stored in any four of the latches. Four individual decoding
gates are uaed to complete the address for reading a word.
When the read address is made in conjunction with the
read-enable signal, the word appears at the four outputs.

\

This arrangement-data entry addressing separate from
data-read addressing and individual sense line-eliminates recovery times, permits simultaneous reading and
writing, and is limited in speed only by the write time (30 ns
typical) and the read time (25 ns typical). The register file
has a nondestructive readout in that data is not lost when
addressed.
All inputs except the read enable and write enable are buffered to lower the drive requirements to one standard load.
Input-clamping diodes minimize switching transients t9

Connection Diagram

simplify system desi~n. High-speed, double-ended ANDOR-INVERT gates are employed for the read-address function and drive high-sink·current, open·collector outputs.
Up to 256 of these outputs may be wire-AND connected for
increasing the capacity up to 1024 words. Any number of
these registers may be paralleled to provide n-bit word
length.

Features
• Separate addressing permits simultaneous reading and
writing
• Fast access times typically 20 ns
• O~ganized as 4 words of 4 bits
• Expandable to 1024 words of n-bits
• For use as:
Scratch-pad memory
Buffer storage between processors
Bit storage in fast multiplication designs
• Open-collector outputs with low maximum off-state
"urrent: 20 p.A
• DM54LS670 and DM74LS670 are similar but have
TRI-STATE® outputs

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings, The "Recommended Operating Conditions" table will
define the conditions for actual device operati~m.

Dual-In-Line Package

VCC

WRITE SELECT ENABLE
OUTPUTS
DATA - - - . . .
---...
Dl
WA
Wa WRITE READ 01
02
10

D2

D2

9

02

D3

D4

D3

D4

DATA

04

03

---- ---RB

7V
7V
7V
-65·Cto150·C

RA

READ SELECT

04

OUTPUTS

54LS170 (J); 74LS170 (N)

4-208

03

8
GND
TL/F/6402·1

.---------------~-----------------------------------------------------.c

3:

Function Table
WRITE TABLE (SEE NOTES A, B, AND C)
Write Inputs

Word

WB

WA

GW

L
L

L
H
L

L
L
L
L

H
H
X
Note A:
Note B:
Note C:
Note D:

H
X

H

H = High Level, L

0
O=D
00
00
00
00

en
-'="

~
.....

READ TABLE (SEE NOTES A AND D)
Outputs

Read Inputs

1

2

3

RB

RA

GR

01

02

03

04

00
0=0
00
00
00

00
00
0=0
00
00

00
00
00
O=D
00

L

L
H
L
H
X

L
L
L
L
H

WOB1
W181
W2B1
W381

WOB2
W182
W282
W382

WOB3
W1B3
W2B3
W3B3

WOB4
W184
W2B4
W3B4

H

H

H

H

L
H
H
X

= Low level. X = Don't Care

= D) "" The four selected internal flip-flop outputs will assume the stales
00 = The level of a before the indicated input conditions were established.
(Q

applied to the four external data inputs.

W08l = The first bit of word O. etc.

Logic Diagram

4·209

~
c
3:
~

I"""

....

(J)

~

Recommended Operating Conditions
DM54LS170

Symbol

DM74LS170

Parameter

Units
Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V

Vee

Supply Voltage

V,H

High Level Input
Voltage

V,L

Low Level
Input Voltage

0.7

0.8

V

VOH

High Level Output
Voltage

5.5

5.5

V

IOL

Low Level Output
Current

4

8

mA

tw

Pulse Width

tsu

tH

. Setup Time
(Note 1)
Hold Time
(Note 1)

tLAT

Latch Time for
New Data

TA

Free Air Operating
Temperature

2

Write· Enable

25

25

Read·Enable

25

25

Data

10

10

Write Select

15

15

Data

15

15

Write Select

5

5

25

25

-.55

Electrical Characteristics
Symbol

Parameter

V

2

125

ns

ns

ns

nS
70

0

over recommended operating free air temperature (unless otherwise noted)

Conditions

Min

Typ
(Note 3)

Max

V,

Input Clamp Voltage

Vee = Min,I,= -18 mA

leEx

High Level Output
Current

Vee = Min, Vo=5.5V
V,L = Max, V,H = Min

VOL

Low Level Output
Voltage

Vee= Min
IOL= M.ax
V,L=Max
V,H = Min

DM54
DM74

IOL=4mA
Vec= Min

DM74

Input Current@Max
Input Voltage

Vee=Max
V , =7V

D,R,W

0.1

GR,GW

0.2

High Level Input
Current

Vee=Max
V,=2.7V

Low Level Input
Current

Vee=Max
V, =O.4V.

Supply Current

Vee= Max (Note 4)

I,

I'H

I,L

Icc

DC

Units

-1.5

V

20

I,A

0.25

0.4

V

0.35

0.5

0.25

0.4

D,R,W

20

GR,GW

40

D,R,W

-0.4

GR,Gw

-0.8
25

40

mA

I,A

mA

mA

Nota 1: Times are with respect to the Wrlte·Enable input.
Note 2: Latch time is the time allowed for the interriai output of the iatch to assume the state of new data: This is important oniy when attempting to read
from a location immediately after that location has received new data.
Note 3: Alltypicals are at Vee =SV. TA =2S·e.
Note 4: iCC is measured with all data and enable inputs at 4.SV. all address inputs grounded and all outputs open.

4-210

Switching Characteristics
Parameter

at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)

From
(Input)
To
(Output)

RL=2 kG
CL=15 pF
Min

Units

CL=50 pF

Typ

Max

Min

Typ

Max

tpLH Propagation Delay
Time Low to High
Level Output

Read
Enable
to Any

20

30

45

60

ns

tpHL Propagation Delay
Time High to Low
Level Output

Read
Enable
to Any

20

30

33

40,

ns

tpLH Propagation Delay
Time Low to High
Level Output

Read
Select
to Any

25

40

45

60

ns

tpHL Propagation Delay
Time High to Low
Level Output

Read
Select
to Any

25

40

33

40

ns

tpLH Propagation Delay
Time Low to High
Level Output

Write
Enable
to Any

30

45

53

65

ns

tpHL Propagation Delay
Time High to Low
Level Output

Write
Enable
to Any

26

40

34

50

ns

tpLH Propagation Delay
Time Low to High
Level Output

Data
to
Any

30

45

55

65

ns

tpHL Propagation Delay
Time High to Low
Level Output

Data
to
Any

22

35

25

40

ns

a
a
a
a
a
a

a
a

"

4-211

~National

~ Semiconductor

DM54LS173A/DM74LS173A TRI-STATE® Quad D Registers
General Description

Features

These four-bit registers contain D-type flip-flops with totem-pole TRI-STATE outputs. capable of driving highly capacitive or low-Impedance loads. The high-Impedance
state and increased high-logic-level drive provide these
flip-flops with the capability of driving the bus lines in a busorganized system without need for Interface or pull-up
components.

• TRI-STATE outputs interface directly with system bus

Gated enable inputs are provided for controlling the entry of
data into the flip-flops. When both data-enable inputs are
low. data at the 0 inputs are loaded into their respective
flip-flops on the next positive transition of the buffered
clock input. Gate output control inputs are also provided.
When both are low. the normal logiC states of the four outputs are available for driving the loads or bus lines. The
outputs are disabled Independently from the level of
the clock by a high logic level at either output control input.
The outputs then present a high impedance and neither
load nor drive the the bus line. Detailed operation is given in
the truth table.

•
•
•
•

• Gated output control lines for enabling or disabling the
outputs
• Fully indepen.dent clock eliminates restrictions for
operating in one of two modes:
Parallel load
Do nothing (hold)
For application as bus buffer registers
Typical propagation delay 18 ns
Typical frequency 45 MHz
'tYpical power dissipation 85 mW

Absolute Maximum Ratings (Note 1)
Supply Voltage

7V

Input Voltage

7V
-65°Cto150·C

Storage Temperature Range

To minimize the possibility that two outputs will attempt to
take a common bus to opposite logic levels. the output control circuitry is designed so that the average output disable
times are 'shorter than the average output enable times.

Note 1: The ,jAbsolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" tabl~ are nol guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual·ln·Llne Package
DATA ENABLE
tNPUTS

DATAtNPUTS

Inputl

..-"-.

VCC CLEAR

1,6

01

15

CLEAR

14

10

OUTPUT
CONTROL 10

r

2

-M

N

3
01

OUTPUT CONTROL

54LS173A (J)

02
13

20
20

4

02

03

12

3D

30

5

03

04

11

40
4Q

6

G2

G1

19

10

DATA
ENABLE
CK

7

Clear

Clock

H
L
L
L
L
L

X
L

I
I
I
I

Data Enable

Data

Output
Q

G1

G2

0

X
X

X
X
X

X
X
X
X

00
00
00

L
H

L
H

H

X
L
L

H
L
L

L

When either M or N (or both) Is (are) high the output is disabled
to the high-imped"nce state; however, sequential operation of
the flip-flops Is not affected.

.e

H = high level (81eedy 8'8.e)
l = low level (steady atate)

04 CLOCK GNO

I = low-to-high level transition
OUTPUTS

X
TLIF/6403·1

= don't care (any Input Including tranaitiona)

00 = the level of 0 before the indicated atea,dy atate input conditions
were established

74LS173A (N)

4·212

Recommended Operating Conditions
Parameter

Sym

DM54LS173A

DM74LS173A

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units

Vcc

Supply Voltage

V IH

High Level Input
Voltage

VIL

Low Level
Input Voltage

0.7

0.8

IOH

High Level Output
Current

-1

-2.6

mA

IOL

Low Level Output
Current

12

24

mA

fCLK

Clock Frequency
(Note 1)

0

30

0

30

MHz

.Clock Frequency
(NotE! 2)

0

20

0

20

MHz

tw

tsu

tH

PulseWidth

Setup Time

Hold Time

tREL

Clear Release Time

TA

Free Air Operating
Temperature

Note 1:
Note 2:

2

Clock

17

17

Clear

17

17

Enable

17

17

Data

10

10

Enable

0

0

Data

0

0

10

V

ns

ns

ns

10

-55

125

V

ns
70

0

·C

CL = 45 pF and RL = 6671!.
CL= 150 pF and RL=667!!.

Electrical Characteristics
Sym

V

2

Parameter

over recommended operating free air

Conditions

te~perature (unless otherwise noted)

Min

'Typ
(Note 1)

Max

VI

Input Clamp Voltage

Vee = Min, 11= -18 rnA

VOH

High Level Output
Voltage

-1.5

Vcc=Min,loH=Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vec=Min
IOL=Max'
VIL = Max
VIH=Min

DM54

0.25

0.4

DM74

0.35

0.5

IOL= 12 rnA,
Vec= Min

DM74

0.25

0.4

.

Units
V

V

2.4

V

II

Input Current@Max
Input Voltage

Vee = Max, VI = 7V

0.1

rnA

IIH

High Level Input
Current

Vee = Max, VI = 2.7V

20

I,A

4-213

Electrical Characteristics

;.

(Continued)
over recommended operating free air temperature (unless otherwise noted)

Symbol

Parameter

Conditions

Typ

Min

(N~te

Max

1)

Units

-0.4

mA

Vcc=Max, Vo=2.7V
V IH = Min, Vil = Max

20

I,A

Off-State Output
Current with Low
Level Output
Voltage Applied

Vce=Max, Vo =O.4V
VIH = Min, Vil = Max

-20

I,A

los

Short Circuit
Output Current

Vce= Max
(Note 2)

-100

mA

lec

Supply Current

Vcc= Max (Note 3)

Low Level Input
Current

Vcc=Max, VI=0.4V

10ZH

. Off-State Output
Current with High
Level Output
Voltage Applied

10Zl

III

DM54

-20

DM74

-20

-100
17

mA

30

Switching Characteristics
at Vce = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)

Parameter

From
(Input)
To
(Output)

f MAX Maximum Clock
Frequency.

RL = 6670
C L =45 pF
Min

Typ

30

45

Units

CL=150 pF
Max

Min
20

Typ'

Max

30

ns

jPlH Propagation Delay
Time Low to High
Level Output

Clock
to
Output

16

25

21

34

ns

tpHl Propagation Delay
Time High to Low
Level Output

Clock
to
Output

20

30

26

.40

ns

tpHl Propagation Delay
Time High to Low
Level Output

Clear
to
Output

20.

30

26

40

ns

tPZH Output Enable
Time to High
Level Output

Output Control
(M or N)to
Any.Q

7

18

21

9

27

34

ns

tPZl Output. Enable
Time to Low
Level Output

Output Control
(M or N) to
Any Q

7

18

27

9

30

45

ns

tpHZ Output Disable
Time from High
Level Output
(Note 4)

Output Control
(M or N) to
Any --ll--.....
'-H-f--f--t-1-H-f--L..-/

n

PRESEOTB

L-.o.£!.

CO

'------',.-OUTPUTOB

~ CLOCK

Lr--

KCLEAROB

r-

Y

DATA~(1_0~)~---1-r1-tll1-t-rlltll1~1o_ _ _- ._ _ _~_ _,
'J r
6

INPUTC

r '--

.--- J PRESEOTCI--~
.----OUTPUTOC

~)-1--.....
~-+-+-1H--t-H-t--I-'/
Le-

' ' ;' ' '1

~ CLOCK

-+-__--,

1

DATA.:.(9~)_---H-t-rHt-tT-rH4-'p..______
r--t

INPUT D

it->-+--.

PRESEbDI--~OUTPUTOD

l....( CLOCK

'--r\
L

(11)
LOAD

J

"~v"'1
TLlF/6405·3

Pin (16)

4·225

= Vee.

Pin (6)

....
....

CJ)

= GND

~

0)

,-----------------------------------------------------------------------------------------,

U;. Timing Diagrams
~

~

LS190 D~cade Counters
Typical Load, Count, and Inhibit Sequences

:E

Q

~

0)

LOAD~

~

:7)
::E

DATAl:
INPUTS :

Q

g~

~

~

CLOCK
DOWN/UP
ENABLE

:E
Q

~
~

~

~
:E
Q

-+f--, ~===~==j::t=_,

RIPPLE CLOCK: :..;...1

17
8
9
0 1 22210987
I II-- COUNT UP
I INHIBIT I I--COUNT DOWN--)

--.....-

LOAD

TLiF/6405·4

Sequence:
(1) Load (preset) to BCD seven

(2) Count up to eight, nine ••zero, one, and two
(3) Inhibit
(4) Count down to one, zero, nine. eight. and seven

LS191 Binary Counters
Typical Load, Count, and Inhibit Sequences
LOAD~,------------------------------

DATA [ :
INPUTS :

CLOCK
DOWN/UP
ENABLE

RIPPLE CLOCK -

_Ir-H-___,

_....J

~==::t===+=+=~ ~===

113 14 15 0
1 2
2
2 1
0
15 14 13
I II--COUNT UP
I INHIBIT I I--COUNT DOWN--I
--.....LOAD
Sequence:
(1) Load (preset) to binary thirteen
(2) Count up to fourteen; fifteen, zero, one, and two
(3) Inhibit

(4) Count down to one, zero, fifteen, fourteen. and thirteen

4·226

TLlF/6405-5

r-------------------------------------------------------------,c
3:
~

.
~ Semiconductor
~National

~
.....

I§
c
:s:

DM54LS192J DM74LS192, DM54LS193J DM74LS193
Synchronous 4·Bit UpJ Down Counters with Dual Clock

~

~
.....

General Description
These circuits are synchronous up/down counters; the
LS192 circuit is a BCD counter and the LS193 is a 4-bit
binary counter. Synchronous operation is provided by having all flip-flops clocked simultaneously, so that the outputs change together when so instructed by the steering
logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (rippleclock) counters.
The outputs of the four master-slave flip-flops are triggered
by a low-to-high level transition of either count (clock) input. The direction of counting is determined by 'which count
input is pulsed. while the other count input is held high.
The counters are fully programmable; that is, each output
may be preset to either level by entering the desired data
at the inputs while the load input is low. The output will
change independently of the count pulses. This feature
allows the counters to be used as modulo-N dividers by
simply modifying the count length with the preset inputs.

A clear input has been provided which. when taken to a high
level, forces all outputs to the low level; independent of the
count and load inputs. The clear, count, and load inputs are
buffered to lower the drive requirements of clock drivers,
etc., required for long words.
These counters were designed to be cascaded without the
need for external circuitry. Both borrow and carry outputs
are available to cascade both the up and down counting

functions. The borrow output produces a pulse equal in
width to the count down input when the counter underflows.

Features

:s:

•
•
•
•
'.
•

INPUTS

12

11

DATA

D

10

-

.9

I-

2
Os

5

4

3
OA

COUNT COUNT
UP
DOWN

OUTPUTS

~
.....

co
Co)

7W

7rot
-65°Ct0150'C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

DATA
DATA
A
CLEAR SORROW CARRY LOAD
C

DATAS
INPUT

~

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
Storage Temperature Range

13

INPUTS

Note: Low input to load sets 0A = A,

6
Oc

7
OD

G!:

OUTPUTS

TL/F/6406·'

Os = B, Oc = C, and 00 = D.

54LS192 (J)
54LS193 (J)

74LS192 (N)
74LS193 (N)
4-227

co

~

c

Fully independent clear input
Synchronous operation
Cascading circuitry provided internally
Individual preset each flip-flop
Typical counffrequency 32 MHz
Typical power dissipation 95 mW

OUTPUTS

14

~
r-

en
.....

Dual-In-Llne Package

15

c

:s:

Similarly, the carry output produces a pulse equal in width
to the count down input when an overflow condition exists.
The counters can then be easily cascaded by feeding the
borrow and carry outputs to the count down and count up
inputs respectively of the succeeding counter.

Connection Diagram
INPUTS

JS

Recomm,ended Operating Conditions
Sym

DM54LS192; LS193

Parameter

DM74LS192, LS193

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units
V

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level
Input Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

fCLK

Clock Frequency
(Note 1)

0

25

Clock Frequency
(Note 2)

0

20

tw

Pulse Width of Any Input

20

20

ns

tsu

Data Setup Time

20

20

ns

0

0

ns

40

40

tH

Release Time

TA

Free Air Operating
Temperature

V

0.7

0.8

-0.4

-0.4

-55

125

V
mA

8

mA

0

25

MHz

0

20

MHz

4

Data Hold Time

tREL

2,

2

ns

0

70

·C

'LS192 and 'LS193 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Sym

Parameter

Conditions

Min

Typ
(Note 3)

Max

VI

Input Clamp Voltage

Vce= Min, 11= -18 mA

VOH

High Level Output
Voltage

Vc"c= Min
IOH = Max
VIL=Max
VIH=Min

DM54

2.5

3.4

DM74

2.7

3.4

Low Level Output
Voltage

Vec=Min
10L=Max
VIL=Max
VIH=Min

DM54

0.25

0.4

DM74

0.35

0.5

IOL=4 mA
Vce= Min

DM74

0.25

0.4

VOL

-1.5

Units
V
V

V

II

Input Current@Max
Input Voltage

Vce=Max, VI=7V

0.1

mA

IIH

High Level Input
Current
,

Vce=Max, VI = 2.7V

20

/LA

IlL

Low Level Input
Current

Vcc = Max, VI = 0.4V

-0.4

mA

los

Short Circuit '
Output Current

Vce=Max
(Note 4)

mA

Supply Current

Vcc = Max (Note 5)

Icc

DM54

-20

-100

DM74

~20

-100

19

Note 1: CL =15 pF and RL =2 krl.
Note 2: CL =50 pF and RL =2 krl.
Nota 3: Aillypicals are at VCC =5V, TA =25'C.
Note 4: Not more than one output should be shorted at a time, and the duration shpuld not exceed one second.

Note 5: ICC is measured with all outputs open, CLEAR and LOAD Inputs grounded, and all other Inputs at 4.5V.
4-228

34

rnA

•

'LS192 and 'LS193 Switching Characteristics
at Vee = 5V and TA= 25°C (See Section 1 for Test Waveforms and Output Load)

Parameter

From
(Input)
To
(Output)

fMAX Maximum Clock
Frequency

RL=2 kO
CL=15 pF
Min

Typ

25

32

CL=50 pF
Max

Min

Typ

20

25

Units
Max
MHz

tpLH Propagation Delay
Time Low to High
Level Output

Count Up
to
Carry

17

26

20

30

ns

tpHL Propagation Delay
Time High to Low
Level Output

Count Up
to
Carry

18

24

24

36

ns

tpLH Propagation Delay
Time Low to High
Level Output

Count
Down to
Borrow

16

24

19

29

ns

tPHL Propagation Delay
Time High to Low'
Level Output

Count
Down to
Borrow

15

24

21

32

ns

tpLH Propagation Delay
Time Low to High
Level Output

Either
Count to
AnyQ

27

38

30

45

ns

tpHL Propagation Delay
Time High'to Low
Level Output

Either
Count to
Any Q

30

47

36

54

ns

tpLH Propagation Delay
Time Low to High
Level Output

Load
to
AnyQ

24

40

27

41

ns

tpHL Propagation Delay
Time High to Low
Level Output

Load
to
Any Q

25

40

31

47

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
Any Q

23

35

29

44

ns

,

4-229

Logic Diagrams

LS192
(13) a DRROW

0 UTPUT
(12) CARRY
0 UTPUT

~

DATA
INPUT A

(15)

DOWN
COUNT

(4)

r=t---r

~

(3)

aA

DUTPUT aA

T
UP
COUNT

OA

(5)

::r-P
DATA
INPUT B

6T

(1)
~

-r-r
p-

~

~
3)0-

DATA
INPUT C

~

(2)

aa
Oa

:n

t-

6-J

(10)

-r-r
L....y.-....

P----I.

(6)

I

ac

OUTPUT ac

T

r-r-

-

Oc

~
DATA
INPUT D

0.UTPUT Os

T

t-

b--;T

(9)

(14)
CLEAR

-r-r
: : t::::::]
(7)

aD

-

aD

L..........,.-

LO AD

OUTPUT aD

T

~

~
....

I-

~
TLlF/6406·2

4·230·

c
Logic Diagrams

(Continued)

en
==
.,:..
r-

en
....

LS193

co

-s:
N

(13)

""

DOWN (4)
COUNT

CARRY
OUTPUT

s:
en

(3)
OUTPUT QA

co

-s:c

-- J

Co)

:;::!

r-

en
....

-f-L-'

co

Co)

J

(2)

Os

OUTPUTQB

T

---

as ~

1

-..........

w

(10)

fL-"
~

(6)

ac

~
v

-

-- J

,

CLEAR

OUTPUT Qc

Qc
T

DATA (9)
INPUT D

.,:..

r-

en
....

aA ~

~
V

~

DATA
INPUTC

....enco
c

QA

DATA (1)
INPUT B

r-

.!'l

rL-"
T

UP
COUNT

C

:;::!

(12)

\,..
DATA (15)
INPUT A

BDRROW
OUTPUT

L;)o.

r---'

1

~

(7)

QD

OUTPUT QD

T
aD

(11)
LDAD

~

I-

~
TLlF/6406·3

4·231

Timing Diagrams

LS192 DECADE COUNTERS
TYPICAL CLEAR, LOAD, AND COUNT SEQUENCES

CLEAR

---Il!-______________________

LOAD

COUNT--+~--~+__,

UP
COUNT---t-+--r~-+_--------~__,

DOWN

OUTPUTS

QD

CARRY
BORROW
~r--"'--­

I

8

9

0

1

21 1 1

-COUNTUP~

CLEAR PRESET

r--

0

9

8

'71

COUNT OOWN--'
TLlFI6406-4

Sequence:
(1) Clear outputs to zero.

(2) Load (preset) to BCD seven.
(3) Count up to eight, nine, carry. zero, one, and two.
(4) Count down to one, zero, borrow, ~iI;e, eight. and seven.
Note A:, Clear overrides load, data. and count inputs.
Note B: When counting up. count-down input must be high; when counting down, count-up Input must be high.

4-232

c

s:
en

Timing Diagrams (Continued)

~

r-

en
....

CD

~
C

s::

LS193 BINARY COUNTERS
TYPICAL CLEAR, LOAD, AND COUNT SEQUENCES
CLEAR---Il~

~

_____________________________________________

~
....

CD

~N

LOAD

C

s::
5:

....CD~

Co)

C

COUNT
UP

s::

--++-+-+--..

~
r-

DOWN

en
....

QA

Co)

COUNT--~~---+-+---+------------------+-~

CD

QS

OUTPUTS
QC
QD

CARRY
SORROW

1 ,14

~.------.,

CLEAR PRESET

r-

15

0

1

21 1 1 0 15 14 131
' I . COUNT DOWN--,

COUNT U P - '

TLlF/6406-5

Sequence:
(1) Clear outputs to zero.
(2) Load (preset) to binary thirteen,
(3) Count up to fourteen. fifteen. carry. zero, one, and two.
(4) Count down to one, zero, borrow, fifteen, fourteen, and thirteen.
Note A: Clear overrides load, data, and count inputs.
Note B: When counting up, count·down input must be high: when counting down. count-up input must be high.

4·233

~National

~ Semiconductor
DM54LS194A/DM74LS194A 4·Bit Bidirectional
Universal Shift Registers
General Description

Features

This bidirectional shift registers is designed to incorporrate virtually all of the features a system designer may want
in a shift register; they feature parallel inputs. parallel
outputs. right-shift and left-shift serial inputs. operatingmode-control inputs. and a direct overriding clear line. The
register has four distinct modes of operation. namely:
Parallel (broadside) load
Shift right (in the direction QA toward QD)
Shift left (in the direction QD toward QA)
Inhibit clock (do nothing)
Synchronous parallel loading is accomplished by applying
the four bits of data and taking both mode control inputs. SO
and 51, high. The data is loaded into the associated .flipflops and appear at the outputs after the positive transition
of the clock input. During loading, serial data flow is
inhibited.
Shift right is accomplished synchronously with the rising
edge of the clock pulse when SO is high and 51 is low.
Serial data for this mode is entered at the shift-right data
input. When SO is low and 51 is high. data shifts left synchronously and new data is entered at the shift-left serial
-input.
.

• Parallel inputs and outputs
• Four operating modes:
Synchronous parallel load
Right shift
Left shift
Do nothing
•
•
•
•

Absolute Maximum Ratings (Note 1)
Supply VCltagJ
Input Voltage
Storage Temperature Range

7V
7V
-65·CtoI50·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Clocking of the flip-flop is inhibited when both mode control
inputs are low.

Connection Diagram

Positive edge-triggered clocking
Direct overriding clear
Typical clock frequency 36 MHz
Typical power dissipation 75 mW

Dual-In-Llne Package
OUTPUTS

vJ.C 'O~
1.

15

or or or \
"

13

12

CLOCK
11

I I I I

so

"1'1.

9

I

r-<

I I I I
l' t

J,'

1

!"

]3

CLEAR SHIFT

A

RIGHT

PARALLEL INPUTS

SERIAL

54LS194A (J)
74LS194A (N)

I

sHl~
LEFT

G!:

SERIAL

INPUT

TL/Ff6407·1

INPUT

Inputs
,

Outputs

Clear
L
H
H
H
H
H
H
H

Sl

SO

X
X
H
L
L

X
X
H
H
H
L
L
L

H
H
L

Parallel

Serial

Mode
Clock

X
L

Loft

Right

A

U

C

D

QA

QU

QC

X
X
X
X
X

X
X
X
H
L
X
X
X

X
X-

X
X
b
X
X
X
X
X

X
X

X
X
d
X
X
X
X
X

L

L

L

L

OAO

aSO

OCO

aoo

I
I
I
I
I

H
L

X

X

•

X
X
X
X
X

c
X
X
X
X
X

°D

a

b

c

d

H
L

°An
°An
°Cn
°Cn
°SO

°Sn
aSn
OOn
°On
OCO

°Cn
°Cn

°Sn
°Sn
OAO

H
L

000

H = High level (steady Btate), L = Low Level (steady state), X = Don't Care Cany input, including transitions)

i = Transition from low to high level
e, b, C, d = The level of steady state input at inputs A. B, C, or D. respectively.
QAO. Qeo. Oeo. aOO = The level of CA. 0B.
or 00. respectively. before the indicated steady state input conditions were established.
0An. 0Sn. 0Cn. OOn' = The level of 0A. aBo Ce, respectively, before the most-recant transition of the clock.

aeo

t

4-234

Recommended Operating Conditions
Parameter

Sym

DM74LS194A

DM54LS194A
Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Vcc

Supply Voltage

V1H

High Level Input
Voltage

V1L

Low Level
Input Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

fCLK

Clock Frequency
(Note 1)

0

25

Clock Frequency
(Note 2)

0

20

Pulse Width

tw

Setup Time

tsu

tH

Hold Time

tREL

Clear Release Time
Free Air Operating
Temperature

TA

0.7

0.8

-0.4

-0.4

V
mA

8

mA

0

25

MHz

0

20

4

Clock

20

20

Clear

20

20

ns

Mode

30

30

Data

20

20

0

0

25

25

ns

0

·C

125

-55

CL= 15 pF and RL=2 kO.
2: CL = 50 pF and RL = 2 kO.

Note 1:
Note

V
V

2

2

Units

4-235

ns

ns

70

Electrical Characteristics
Sym'

over recommended operating free air temperature (unless otherwise noted)

Parameter

Min

Typ
(Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

VI

Input Clamp Voltage

Vcc= Min, 11= -18 mA

VOH

High Level Output
Voltage

Vcc= Min
IOH=Max
VIL=Max
VIH = Min

Low Level Output
Voltage

Vcc=Min
IOL= Max
VIL=Max
VIH=Min

VOL

Units

Max
-1.5

V
V

DM54

.0.25

0.4

DM74

0.35

0.5

0.25

0.4

V

..
DM74

IOL=4 mA
Vcc= Min
II

Input Current@Max
Input Voltage

Vcc=Max, VI =7V

0.1

mA

IIH

High Level Input
Current

Vcc=Max, VI=2.7V

20

I,A

IlL

Low Level Input
Current

Vcc=Max, VI =0.4V

-0.4

mA

los

Short Circuit
Output Current

Vcc= Max
(Note 2)

mA

Supply Current

Vcc = Max (Note 3)

Icc

Switching Characteristics
Parameter

From
(Input)
To
(Output)

f MAX Maximum Clock
Frequency

DM54

-20

-100

DM74

-20

-100
15

mA

23

at Vcc = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL=2 kll
CL=15 pF
Min

Typ

25

36

CL=50 pF
Max

20

,

Typ

Min

,

Units
Max
MHz

25

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
Any Q

14

22

17

26

n5

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
Any Q

17

22

23

35

n5

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
Any Q

,19

30

25

38

n5

Note 1: All typicals are at VCC = SV, TA = 2SoC.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: With all outputs open, inputs A through 0 grounded, and 4.SV applied to 50, 51, CLEAR, and the serial Inputs, ICC is tested with momentary

ground, then 4.SV applied to CLOCK.

4·236

Logic, Diagram
LS194A

PARALLEL INPUTS

c

A
(31

(41

D
(61

(51

MODE{S:~'O~IC>~----~---t-----'-------1~~r-----~------~--i-----~-------t---t-----,

CONTROl

INPUTS 50,::'91:..O""1----t--#-.I--f--------r--tI-fl--1>\-------i---H--.l--....-------t---H-1>\-., I
SHIFT

SHIFT

S~:t~r.;;(2::..1________-,

r-Ht-----1t-"(7::..1 ~:;AL

INPUT

CLOCK(11)

INPUT

;:'O--------------.....--+--+_--------.....---i---+----------....--+_--I----------.....

...._ir_------------~--+_------------~~_+--------------~

CLEAR(~'I____q~~------~------

(15)

a.

aA

(14)

(13)

(12)

Oc

aD

PARALLEL OUTPUTS

TLiF/6407·2

Timing Diagram
TYPICAL CLEAR, LOAD, RIGHT-SHIFT, LEFT-SHIFT, INHIBIT, AND CLEAR ,SEQUENCES
CLOCK
MODE

CON~ROL

Iso

INPUTS 51

I

CLEAR
SERIAL
DATA
INPUTS

R
L

PARALLEL{ :
DATA
INPUTS C

o

OUTPUTS { : : :

-+-+--1

QC:
QD

:-+--+--1
__-i->----INHIBIT
CLEAR LOAD

CLEAR
TWF/6407·3

4·237

•

~National

~ Semiconductor
DM54LS195A/DM74LS195A 4-Bit Parallel Access
Shift· Registers
General Description
These 4-bit registers feature parallel inputs, parallel outputs, J-K serial inputs, shiftlload control input, and a direct
overriding clear. All inputs are buffered to lower the input
drive requirements. The- registers have two modes of
operation:
Parallel (broadside) load
..
Shift (in the direction aA toward aD)
'.
Parallel loading is accomplished by applying the four bits of
data and taking the shiftlload control input low. The data is
loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During
loading, serial data flow is inhibited.
Shifting is accomplished synchronously when the shift!
load control input is high. Serial data for this mode is entered at the J-K inputs. These inputs permit the first stsge
to perform as a J-R, D, or T-type flip-flop as shown in the
truth table.

• Parallel inputs and outputs from each flip-flop
• Direct overr.iding clear

• J and K inpats to first stage
• Complementary outputs from last stage
• For use in high-performance:
accumulators I processors
seriai-to-parallel, parallel-to-serial converters
• Typical clock frequency 39 MHz
• Typical power dissipation 70 mW

Absolute Maximum Ratings (Note 1)
7V
7V
-6S·Cto1S0·C

Supply Voltage
Input Voltage
Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be· operated at the.e limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum rating •. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Features
• Synchronous parallel load
• Positive-edge-triggered clocking

Connection Diagram

Dual-In-Line Package
OUTPUTS

Vee

QA

Oa

Oc

aD

SHlFT/
CLOCK LOAD

aD

1,. 1,5. 114 1,. 1,. J

JI I l

11

10

9

J
54LS195A (J)
74LS195A (N)

r<

I I I II I1
I'

1
CLEAR

J

I' I"
K

5

B

A·

6

C

17

18
GND

D

~

SERIAL INPUTS

PARALLEL INPUTS

TL/F/64Oa.1

Function Table
Inputl

Clear

Shill/

Clock

Load
L
H
H
H
H
H
H

X
L
H
H
H
H
H

X

J

K

X

X

I

x x

L

X
L

I
I
I

t

Outputs

Serial

L
H
H

X
H
L
H
L

H = High Level (steady state), l

Parallel

A

a

X

X
b
X
X
X
X
X

•
X
X
X
X
X

OA

c

D

X

X
d
X
X
X
X
X

c
X
X
X
X
X

Oa

Oc

OD

liD

L
d

H

000

000

OCn
OCn
OCn
OCn

OCn
OCn
OCn
OCn

L

L

L

•
OAO

b

c

aBO
OAD
OAn
OAn
OAn

OCO
OBn
OBn
OBn
OBn

.OAO·
L
H
aAn

d

= Low Level (steady state), X = Don't Care (any input. including transitions)

t = Transition Irom low to high level

a.b,c,d = The level of steady state input at A, B, e , or D. respectively.
0AO, aBO, aeo, aDO = The level of 0A. 0B. ae, or aD. respectively. before the indicated steady state input
conditions were established.
0An. 0Sn. 0en = The level of 0A, 0e, 0e. respectively, before the most recent transition of the clock.

4-238

Recommended Operating Conditions
DM54LS195A
Sym

Parameter

DM74LS195A

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Vcc

Supply Voltage

V1H

High Level Input
Voltage

V1L

Low Level
Input Voltage

IOH

High Level Output
Currerit

IOL

Low Level Output
Current

fCLK

Clock Frequency
(Note 1)

0

30

Clock Frequency
(Note 2)

0

25

tw

tsu

Pulse Width

Setup Time

2

Units
V
V

2
0.7

0.8

-0.4

-0.4

V
mA

8

mA

0

30

MHz

0

25

MHz

4

Clock

16

16

Clear

12

12

Shift/Load

25

25

Data

15

15

ns

ns

tH

Hold Time

0

0

ns

tREL

Shift/Load Release Time

10

10

ns

Clear Release Time

25

25

TA

Free Air Operating
Temperature

-55

125

70

0

Nola 1: CL= 15 pF and RL=2 kll.
Note 2: CL=50 pF and RL=2 kll.

.
I

4-239

·C

Electrical Characteristics
Symbol

over recommended operating free air temperature (unless otherwise noted)

Parameter

Min

Typ
(Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

,..1.5

VI

Input Clamp Voltage

Vcc=Min, 11= -18 mA

VOH

High Level Output
Voltage

Vcc=Mln
10H=Max
VIL=Max
VIH=Mln

Low Level Output
Voltage

Vcc=Min
10L=Max
VIL = Max
VIH=Min

DM54

0.25

0.4

DM74

0.35

0.5

IOL=4 mA
Vcc=Mln

DM74

0.25

0.4

VOL

Units

Max

V
V

V

II

Input Current@Max
Input Voltage

Vcc = Max, VI = 7V

0.1

mA

IIH

High Level Input
Current

Vcc=Max, VI = 2.7V

20

p.A

IlL

Low Level Input
Current

Vcc = Max, VI = O.4V

-0.4

mA

los

Short Circuit
Output Current

Vcc=Max
(Note 2)

-100

mA

Supply Current

Vcc = Max (Note 3)

Icc

Switching Characteristics
Parameter

DM54

-20

DM74

-20

,

-100

14

21

mA

at Vcc= 5V and TA=25°C (See Section 1 for Test Waveforms and Output Load)

From
(Input)
To
(Output)

RL=2 kU
CL=50 pF

CL=15 pF

fMAX Maximum Clock
Frequency

Min

Typ

30

39

Max

Min

Typ

25

30

Units
Max'
MHz

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
Any Q

14

22

17

26

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
AnyQ

17

26

23

35

ns

tpHL Propagation Delay.
Time High to Low
Level Output

Clear
to
Any Q

19

30

25

38 .

ns

Nole 1: All typlcals are at VCC = 5V, TA = 25·C .
. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Nolo 3: With. all outputs open, SHIFT/LOAD grounded, and 4.5V applied to the J,K, and data inputs, ICC is measured by' applying a momentary ground, then

4.5V, to the CLEAR and then applying a momentary ground then 4.5V to the CLOCK.

'.

4·240

Logic Diagram
SERIAL
INPUT

PARALLEL INPUTS

~

K

J
SHIFT (LOAD (9)
CONTROL

(2)

(3)

A

B

(4)

C

(5)

D
(7)

(6)

PARALLEL OUTPUTS
TLIF/640B·2

Timing Diagram
TYPICAL CLEAR, SHIFT, AND LOAD SEQUENCES
CLOCK
CLEAR
SERIAL
INPUTS

{J

K_ _I-_ _.J

SHIFT/ LOAD

PARALLEL{:
DATA
INPUTS C--r-----+-----~-------~

D____+-________-+_____________________________
L-+____~-------------------------

{a~~~-+____+ ____

aA--_I~---~~~---------~r----1~L-----------

OUTPUTS

aC __

I

--I

aO:::-+____~-------~
f------SERIAL SHIFT----~~
LOAD

r-----SERIAL SHIFT---o_

TLfF/6408·3

4-241

~r---------------------------------------------------------~-------------.

CD
,...
~ ~National

~ Semiconductor
DM54LS1961 DM74LS196, DM54LS1971 DM74LS197
j:;:
CD
Presettable
Decade and Binary Counters.
,...
~

':e
Q

~ General Description
~
Il)

:e
Q

uS

CD
,...
en
....I

~

:e
Q

(0
~

en
....I

;1;

:e
Q

These high-speed counters consist of four doc coupled,
master-slave flip-flops which are internally interconnected to provide either a divide-by-two and a divide-byfive counter (196) or a divide-by-two and a divide-by-eight
counter(197). These counters are fully programmable; that
is, the outputs may be preset to any state by placing a low
on the count/load input and entering the desired data at
the data inputs. The outputs will change independent of
the state of the clocks.
During the count operation, transfer of information to the
outputs occurs on the negative-going edge of the clock
pulse. These counters feature a direct clear which, when
taken low, sets all outputs low regardless of the state of the
clocks.

and QO outputs. In this mode, the two counters operate independently; however, all four flip-flops are
loaded and cleared simultaneously.
lS197
The output of flip-flop A is not internally connected to the
succeeding flip-flops; therefore the counter may be operated in two independent modes:
1. When used as a high-speed 4-bit ripple-through
counter, output QA must be externally connected to
. the clock-2 input. The input count pulses are applied
to the clock-I input. Si'multaneous divisions by 2, 4, 8,
and 16 are performed at the QA, QB, OC, and QO outputs as shown in the truth table .
2. When used as a 3-bit ripple-through counter, the input
count pulses are applied to the clock-2 input. Simultaneous frequency divisions by 2, 4, and 8 are available
at the QB, QC, and QD outputs. Independent use of
flip-flop A is available if the load and clear functions
coincide with those of the 3-bit ripple-through
counter.

These counters may also be used as 4-bit latches by using
the count !load input as the strobe and entering data at the
data inputs. The outputs will directly follow the data inputs
when the count !load is low, but will remain unchanged
when the counllioad is high and the' clock inputs are
inactive.
TYPICAL COUNT CONFIGURATIONS lS196
The output of flip-flop A is not internally connected '0 the
succeeding flip-flops; therefore, the count may be operated
in three independent modes:
1. When used as a BCD decade counter, the clock-2 input must be externally connected to the QA output.
The clock-1 input receives the incoming count, and a
count sequence is obtained in accordance with the
BCD count sequence truth table.
2. If a symmetrical divide-by-ten count is desired for frequency synthesizers (or other applications requiring
division of a binary count by a power of ten), the QO
output must be externally connected to the clock-1 input. ,The input count is then applied at the clock-2 input and a divide-by-ten square wave is obtained at
output QA in accordance with the bi-quinary truth
table.
3. For operation as a divide-by-two counter and a divideby-five counter, no external interconnections are required. Flip-flop A is used as a binary element for the
divide-by-two function. The clock-2. input is used to
obtain binary divide-by-five operation at the OB, QC,

Connection Diagram (Dual-In-line Package)

Features
•
•
•
•

Performs BCD, bi-quinary, or binary counting
Fully programmable
Fully independent clear input
Output QA maintains full fan-out capability in addition to
driving clock-2 input
.

• Typical count frequency
Clock 1 40 MHz.
Clock 2 20 MHz
• Typical power dissipation eo mW

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
. Storage Temperature Range

NDle 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

.---------

DATA INPUTS

Vrcc
14

54LSI96(J)
54LSI97(J)

7V'
5.5V
-65·Cl0150·C

CLEAR

13

Qo

12

o

•

11

10

0.

'.

74lS196 (N)
74lS197 (N)

Nole: Low input to clear sets QA.

Qa. QC and 00 low.
COUNT
LOAD

4-242

Oc

C
A
---..-.--

DATA INPUTS

CLOCK
2

CLOCK
1

Recommended Operating Conditions
DM54LS196
Symbol

Parameter

DM74LS196

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Vcc

Supply Voltage

VIH

High Level Input
Voltage

V il

Low level Input
Voltage

IOH

High level Output
Current

IOl

low level Output
Current

fClK

Clock Frequency
(Note 2)

0

30

Clock Frequency
(Note 3)

0

20

tw

tsu

tH

Pulse Width

Setup Time
(Note 1)
Hold Time
(Note 1)

2

2
0.8

-0.4

-0.4

0

30

MHz

0

20

MHz

20

20

Clock 2

30

30

Clear

15

15

Load

20

20

Data High

81

81

Data low

121

121

Data High

01

01

Data low

61

61

30

30

TA

Free Air Operating
Temperature

-55

125

mA
mA

Clock 1

Count Enable Time
(Note 4)

V

8

4

tEN

V
V

0.7

~

Units

0

ns

ns

ns

ns
70

·C

Noa.1: The symbol (t) indicates the rising edge of the clock pulse is used for reference.

Not. 2: Cl = 15 pF and Rl =2 kll.
Not. 3: Cl = 50 pF and Rl = 2 kO.
Not. 4: Count enable time Is the interval immediately preceding the negative-golng edge of the clock pulse during which the COUNT/lOAD and CLEAR in·
puts must both be high to ensure counting.

.
4·243

'LS196 Electrical Characteristics
over recommended operating free air' temperature (unless otherwise noted)
Symbol

Parameter

Conditions

Min

Typ
(Note 1)

Max
-1.5

VI

Input Clamp Voltage

Vcc=Min, 11= -18 mA

VOH

High Level Output
Voltage

Vcc=Mln
10H=Max
Vll=Max
VIH=Min

DM54

2.5

3.4

DM74

2.7

\ 3.4

Low Level Output
Voltage

Vcc=Mln
IOl=Max
VIL = Max
VIH=Min
(Note 4)

DM54

0.25

0.4

DM74

0.35

0.5

IOL=4 mA
Vcc=Mln

DM74

0.25

0.4

Vcc=Max
V I =5.5V

Clock 1

0.2

Clock 2

0.4

Clear

0.2

Others

0.1

VOL

Input Current@Max
Input Voltage

II

High Level Input
Current

IIH

Vcc=Max
VI=2.7V

Units
V
V

Clock 1

40

Clock 2

80

Clear

40

V

mA

p.A

I

Others
IlL

Low Level Input
Current

Vcc=Max
VI=0.4V

20

Clock 1

-2.4

Clock 2

-2.8

Clear

-0.8

Others
los

Icc

Short Circuit
Output Current

Vcc=Max
(Note 2)

Supply Current

Vcc = Max (Note 3)

mA

-0.4

DM54

-20

-100

DM74

-20

-100
16

mA

27

mA

Note 1: All typlcals are at VCC=5V, TA=25"C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one sacond.
Note 3: ICC Is measured with all Inputs grounded and all outputs open.
Note 4: QA outputs are tested at IOl = Max plus the limit value of,llL for the CLOCK 2 Input. This permits driving the CLOCK 2 Input while maintaining full
fan..,ut capability.

-

4·244

c

s::

'LS196 Switching Characteristics

~
r-

at Vee = 5V and TA = 25'C (See'Section 1 for Test Waveforms and Output Load)

Parameter

f MAX Maximum
Clock Frequency

From
(Input)
To
(Output)
Clock 1
to
QA

C/)
.....

RL=2 kll
C L =15 pF
Min

Typ

30

40

Max

-s::
CD

Units

CL=50 pF
Min

Typ

20

30

Max
MHz

en
C

~
r-

C/)

.....

CD

15

11

20

ns

$fJ
C

ns

~
r-

tpLH Propagation Delay
Time Low to High
Level Output

Clock 1
to
QA

8

tpHL Propagatlon,Delay
Time High to Low
Level Output

Clock 1
to
QA

13

tpLH Propagation Delay
Time Low to High
Level Output

Clock 2
to
QB

10

24

19

29

ns

t PH L Propagation Delay
Time High to Low
Level, Output

Clock 2
to
QB

22

33

28

42

' ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock 2
to
Qe

22

57

45

68

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock 2
to
Qe

22

62

48

72

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock 2
to
Qo

12

18

15

23

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock 2
to
Qo

, 12

45

36

54

ns

tpLH Propagation Delay
Time Low to High
Level Output

Data
to
AnyQ

11

30

23

35

ns

tpHL Propagation Delay
Time High to Low
Level Output

Data
to
AnyQ

29

44

35

53

ns

tpLH Propagation Delay
Time Low to High
Level Output

Load
to
Any Q

27

41

30

45

ns

tpHL Propagation Delay
Time High to Low
Level Output

Load
to
AnyQ

30

45

36

54

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
AnyQ

29

51

40

60

ns

s::

20

20

30

C/)

.....

-s::
CD

......

C

~
r-

C/)

.....
CD
......

4·245

Recommended Operating Conditions
DM74LS197,

DM54LS197

Parameter

Symbol

Min

Nom

4.5

5'

Max

Min

Nom

Max

5.5

4.75

5

5.25

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

fCLK

Clock Frequency
(Note 2)

0

30 '

Clock Frequency
(Note 3)

0

20

tw

tsu

Pulse Width

Setup Time
(No~e

tH

1)

Hold Time
(Note 1)

2
0.7

0.8

-0.4

-0.4

0

30

MHz

0

l!0

MHz'

20

20

30

30

Clear

15

15
20

Load

20

Data High

81

81

Data Low

121

121

Data High

01

01

Data Low

61

6t
30

TA

Free Air Operating
Temperature

-55

125

mA
.mA

Clock 1

30

V

8

'Clock 2

Count Enable Time
(Note 4)

V
V

2

4

tEN

Units

0

ns

ns

ns

ns

70

·C

Noto 1: The symbol (f) Indicates the rising edge of the clock pulse Is used for reference.
Nole 2: CL = 15 pF and RL = 2 kll.
Nolo 3: CL=50 pF and RL=2 kll.
Note 4: Count enable time is the intervallmmedlalely preceding the negative.golng edge of the clock pulse durin,g which the COUNT/LOAD and CLEAR In·
puts must both be high to ensure counting.

4·246

'LS197 Electrical Characteristics
over recdmmended operating free air temperature (unless otherwise noted)

Symbol

Parameter

Conditions

Min

Typ
(Note 1)

Max

VI

Input Clamp Voltage

Vcc= Min, II = -18 mA

VOH

High Level Output
Voltage

Vcc= Min
10H=Max
VIL=Max
VIH=Min

DM54

2.5

3.4

DM74

2.7

3.4

Low Level Output
Voltage

Vcc=Min
10L=Max
VIL = Max
VIH = Min
(Note 4)

DM54

0.25

0.4

DM74

0.35

0.5

IOL=4 mA
Vcc=Min

DM74

0.25

0.4

Vcc=Max
V I =7V

Clock 1

0.2

Clock 2

0.2

Clear

0.2

Others

0.1

VOL

Input Current@Max
Input Voltage

II

High Level Input
Current

IIH

Vcc=Max
VI=2.7V

-1.5

Low Level Input
Current

Vcc=Max
VI =0.4V

40

Clock 2

40

Clear

40

Icc

Short Circuit
Output Current

Vcc= Max
(Note 2)

Supply Current

Vcc=Max (Note 3)

V

mA

/LA

20

Clock 1

-2.4

Clock 2

-1.3

Clear

-0.8

mA

-0.4

Others
los

V
V

Clock 1

Others
IlL

Units

DM54

-20

-100

DM74

-20

-100
16

27

mA

mA

Note 1: Aillypicals are al vcc= SV. TA=2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Note 3: ICC is measured with all Inputs grounded and all outputs open.
Note 4: QA outputs are tested at 10L = Max plus the limit value of IlL for the CLOCK 2 input. This permits driving the CLOCK 2 Input while maintaining full
fan-out capability.

-

4-247

'LS197 Switching Characteristics
at Vee =5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)

Parameter

From
(Input)
To
(Output)

fMAX Maximum
Clock Frequency

Clock 1
to
QA

tpLH Propagation Delay
Time Low to High
Level Output

Clock 1
to

t pHL Propagation Delay
Time High to Low
Level Output

RL=2 kll
CL=15 pF
Min

Typ

30

40

CL=50 pF
Max

Min

Typ

20

30

Units
Max
MHz

8

15

11

20

ns

Clock 1
to
QA

14

21

20

30

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock 2
to
QB

12

19

15

23

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock 2
to
QB

15

35

29

44

ns

t pLH Propagation Delay
Time Low to High
Level Output

Clock 2
to
Qe

22

51

40

60

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock 2
to
Qe

25

63.

50

75

ns

tpLH Propagation Del!ly
Time Low to High
Level Output

Clock 2
.to
Qo

30

78

65

98

ns

tpHL Propagation Delay
Time High to Low
.
Level Output

Clock 2
to
Qo

35

95

71

106

ns

t pLH Propagation Delay
Time Low to High
Level Output

Data
to
AnyQ

15

27

21

32

ns

t pHL Propagation Delay
Time High to Low
Level Output

Data
to
AnyQ

29

44

35

53

ns

tpLH Propagation Delay
Time Low to High
Level Output

Load
to
AnyQ

20

39

29

45

ns

tpHL Propagation Delay
Time High to Low
Level Output

Load
to
AnyQ

30

45

36

54

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
Any Q

29

51

40

60

ns

Q~

I

4-248

,----------------------------------------------------------------------,0
s::

Function Tables

en
~

r0-

....
co
e
o

C/)

LS196
Decade (aCD)
(See Note A)

LS196
(See Note a)

Output

count

Output

Count
QD

QC

Qa

QA

L
L
L
L
L
L
L
L
H
H

L
L
L
L
H
H
H
H
L
L

L
L
H
H
L
L
H
H
L
L

L
H
L
H
L
H
L
H
L
H

0
1
2
3
4
5
6

7
6
9
H = High Level, L

LS197
(See Note A)

0
1
2
3
4
5
6
7
8
9

Count

QA

QD

QC

Qa

L
L
L
L
L
H
H
H
H
H

L
L
L
L
H
L
L
L
L
H

L
L
H
H
L
L
L
H
H
L

L
H
L
H
L
L
H
L
H
L

= Low Level

Note A: Output QA connected to clock-2 jnp~t.
Note B: Output aD connected to clock- f input.

0
1
2
3
4
5
6
7

8
9
10
11
12
13
14
15

s::
~

Output
QD
LL
L
L
L
L
L
L
H
H
H
H
H
H
H
H

QC

Qa

QA

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

r0-

....co

C/)

sn
o

s::

~

r0-

....

C/)

co

-s::
~

o

~

r0-

....
co

C/)
~

Logic Diagrams
LS196

LS197

PRESET

PRESET
T

(5)

(5)
QA

(10)
OATA B

----HR"---p.........-------,

CLOCK 2 (6...;)_ _~+-I---_+--.....JI__

T

QA-

QA

QA

DATAB (10)

(9)as

(3)

CLOCK2 (6)

(9)
QB

DATAC (3)

DATAC-'---tiJF~~~---~_f====,_--_1
(2)
QC

DATAD (11)
(12)
QD
(12) QO

TL/F/6409-2

4-249

TL/F/6409-3

~ r---------------~------------------------------------------------------------------_,

~t!

::i!

~National

~ Semiconductor

c

;: DM54LS221/DM74LS221 Dual Non-Retriggerable
~ One-Shot with Clear and Complementary Outputs
....I

~ General Description
::i!

c

The DM54/74LS221 is a dual monostable multivlbrator
'with Schmitt-trigger input. Each device has, three inputs
permitting the choice of either leading-edge or trailingedge triggering. Pin (Aj is an active-low trigger transition
Input and pin (8) is an active-high transition Schmitttrigger Input that allows jitter free triggering for inputs
with transition rates as slow as 1 volt/second. This provides the input with excellent noise Immunity. Additionally
an internal latching circuit at the input stage also provides
a high immunity to Vcc noise. The clear (CLR) input can
terminate the output pulse at a predetermined time independent of the timing components. This (CLR) input
also serves as a trigger Input when it is pulsed with a low
level pulse transition (-w). To obtain the best and trouble
free operation from this device please read operating rules
as well as the NSC one-shot application notes carefully
and observe recommendations.

•
•
•
•

Direct reset terminates output pulse
Triggerable from CLEAR input
DTL, TTL compatible
Input clamp diodes

Absolute Maximum Ratings

(Note2)

7V
7V
- 65·C to 150·C

Supply Voltage
Input Voltage
Storage Temperature Range

Note 2: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Features

Functional Description

•
•
•
•
•

The basic output pulse width is determined by selection
of an external resistor (Rx) and capaCitor (Cx). Once triggered, the basic pulse width Is Independent of further
input transitions and is a function of the timing components, or it may be reduced or terminated by use of
the active low CLEAR input. Stable output pulse width
ranging from 30 ns to 70 seconds is readily obtainable.

A dual, highly stable one-shot
Compensated for Vcc and temperature variations
Pin-out identical to 'LS123 (Note 1)
Output pulse width range from 30 ns to 70 seconds
Hysteresis provided at (8) input for added noise immunity

Note 1: The pin-out is identical to 'LS123 but. functionally it is not; refer
to Operating Rules #10 in this datasheet.

Connection Diagram

Function Table
Inputs

Dual-In-Line Package

A

B

Q

Q

L

X

L

X
X

H

X
X

X

L

L
L

H
H
H

H
H

L
)
L

t

SL

"""1..f""

H
H

SL

"""1..f""

SL

"""1..f""

REleTI

Vee

CEXT 1

CEXT 1

Ql

il2

!:LR 2

82

Outputs

CLEAR
A2

•

I

H = High Logic Level
L = Low Logic Level
X Can Be Either Low or High
I Positive GOing Transition
1= Negative Going Transition
SL
A Positive Pulse
"""1..f""
A Negative Pulse

=
=

AI

81

CLR 1

i'i1

Q2

CEXT 2

RUTI

GND

Cun 2
TLlF/6409-1

DM54LS221 (J)

DM74LS221 (N)

=
=

-This mode of triggering requires first the B input be set from a low to high level
while the CLEAR input Is main talned at logic low level. Then with the 8 Input at
logic high level, the CLEAR Input whose positive transition from low to high
will trigger an output pulse.
B

I

CLEAR --,-50ns-l

r50ns~"""-----

IJ-tw--j

1

O'UT _ _ _ _ _ _ _ _ _.....

1
..____
TL/F/6409·2

4-250

Recommended Operating Conditions
Symbol

Parameter

Vee

Supply Voltage

VT+

Positive-Going Input
Threshold Voltage
at the A Input
(Vee = Min)

VT_

Negative·Going Input
Threshold Voltage
at the A Input
(Vee = Min)

VT+

Positive-Going Input
Threshold Voltage
at the 9 Input
(Vee = Min)

VT-

Negative-Going Input
Threshold Voltage
at the 9 Input
(Vee=Min)

IOH

High Level Output
Current

IOL

Low Level Output
Current

tw

Pulse Width

I Data
I Clear

DM54LS221

DM74LS221

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V

1

2

1

2

V

0.8

0.8

1

1

0.8

2

0.9

·1

0.8

-0.4

V

1

2

-0.4

4

8

40

40

40

40

Clear Release Time
Rate of Rise or Fall
of Schmitt Input (9)

1

1

dV

Rate of Rise or Fall
of Logic Input (A)

1

1

dt

mA
mA
ns

tREL

15

V

V

0.9

dV

dt

Units

Min

ns

15

'::!....
s
'::!....
1'5

REXT

External Timing
Resistor

1.4

70

1.4

100

kO

CEXT

External Timing
Capacitance

0

1000

0

1000

I'F

DC

Duty Cycle

67

67

%

90

90

l RT = 2 kO

I RT = RexT (Max)
TA

Free Air Operating
Temperature

-55

125

~

4-251

0

70

·C

Electrical Characteristics
Symbol
'VI
VOH

Parameter

over recommended operating free air temperature (unless otherwise noted)
Conditions

Input Clamp Voltage

Vee = Min, 11= -18 mA

High Level Output
Voltage

Vee= Min
IOH= Max
VIL= Max
VIH=Min

,

Min

Typ
(Note 1)

Max

-1.5

DM54

2.5

3.4

DM74

2.7

3.4

Units

V
V

DM54

0.25

0.4

DM74

0.35

0.5

Low Level Output
Voltage

Vee = Min
10L= Max
VIL = Max
VIH=Min

II

Input Current@Max
Input Voltage

Vee = Max, VI =.7V

0.1

mA

IIH

High Level Input
Current

Vee=Max, VI = 2.7V

20

p.A

IlL

Low Level Input
Current

Vee= Max
VI = O.4V

A1, A2

-0.4

mA

B

-0.8

VOL

-0.8

Clear
los

Icc

Nota 1:

Short Circuit
Output Current

Vee = Max
(Note 2)

DM54

-20

-100

DM74

-20

-100

Supply Current

Vee = Max

Quiescent

4.7

11

Triggered

19

27

All typlcals are at Vee=5V, TA=25·e.

Note 2: Not more than one output should be shorted at a time, and the duration· should not exceed one second.

4·252

,V

mA

mA

Switching Characteristics
at Vcc = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)

Parameter

From
(Input)
to
(Output)

tpLH Propagation Delay
Time Low to High
Level Output

A1, A2
to

tpLH Propagation Delay
Time Low to High
Level Output

B
to

tpHL Propagation Delay
Time High to Low
Level Output.

A1, A2
to

tPHL Propagation Delay
Time High to Low
Level Output

B
to

tpLH Propagation Delay
Time Low to High
Level Output

Clear
to

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to

tW(out) Output
Pulse Width Using
Zero Timing
Capacitance

A1, A2
to

tW(out) Output
. Pulse Width Using
External Timing
Resistor

A1, A2
to

a

Conditions

Min

CEXT=80 pF
REXT =2 kll
CL=15pF
RL=2 kll

Typ

Max

Units

45

70

ns

35

55

ns

50

80

ns

40

65

ns

·45

65

ns

40

55

ns

a
a
Q

a
a
a,a

a,a

CEXT=O
REXT=2 kll
RL=2 kll
C L= 15 pF

20

47

70

ns

CEXT= 100 pF
REXT = 10 kll
RL=2 kll
CL= 15 pF

600

670

750

ns

CEXT'" 11'F
REXT= 10 kll
RL=2 kll
CL= 15 pF

6

6.7.

7.5

ns

CEXT=80pF
REXT= 2 kll
RL=2 kll
CL= 15 pF

70

120

150

ns

Operating Rules
1.

2.

An external resistor (Rx) and an external capacitor
(C x) are required for proper operation. The value of
Cx may vary from 0 to approximately 1000 I'F. For
small time constants high·grade mica, glass, polypropylene, polycarbonate, or polystyrene material
capacitor may be used. For large time constants
use tantalum or special aluminum capacitors. If
timing capacitor has leakages approaching 100
nA or if stray capacitance from either terminal to
ground is greater than 50 pF the timing equations
may not represent the pulse width the device
generates.

one·shots to prevent high inverse leakage current.
This switching diode is not needed for the 'LS221
one-shot and should not be used.
3.

For Cx» 1000 pF, the output pulse width(Tw) is
defined as follows:
Tw=KRxCx
where[Rx is in kll]
[Cx is in pF]
[Tw Is in ns]
K=Ln2=0.70

When an electrolytic capacitor is used for Cx a
switching diode is often required for standard TTL
4-253

~ ~------+-----------~--------------------------------------------------------------~

~t!

4.

:E

-c
~

100

~F

~: ! i ; I.

10 ~F

~

;;

c

0.1

.,

10 3 pF
10' pF
10 pF
0

.

j;
.2

.4

:z:

~

.6

0

~

-5

.~-

-10 L-~-L~__~-L-J~
-60 -30 0 30 60 90 120 150
AMBIENT TEMPERATURE 1°C)

.~

t

'-'

~

11
I'" ·ft

, ..
1

z

vee=r+_

10' pF

5

Rm=10K
Cm=100o pF
Vee=5.0V

w

.'. !.it.ri

~

..

~F

..

TA=25°C

, ..

1 ~F

~
:E

10

The multiplicative factor K is plotted as a function
of Cx below for design considerations:

TLlF/6409·7

1.0 1.2 1.4

.8

FIGURE 5

"K" COEFFICIENT
TL/FJ6409·3

FIGURE 1

5.

For Cx < 1000 pF see Figure 2 for Tw vs Cx family
curves with Rx as a parameter.

8.

Duty cycle is defined as TwiT x100 in percentage,
if it goes above 50% the output pulse width will
become shorter. If the duty cycle varies between
low and high values, this causes output pulse
width to vary, or jitter (a function of the REXT only).
To reduce jitter, REXT should be as large as possi·
ble, for example,- with REXT 100k jitter is not ap·
preciable until the duty cycle approaches 90%.

~3~1.~!§!11
R=100K:~""'-",",TTl1

5
0
10 [,TA-25 C:
Vee=5.0VI
10'

A

=

R 5K

9.

Under any operating condition Cx and Rx must be
kept as close to the one·shot device pins as possible to minimize stray capacitance, to reduce noise
pick-up, and to reduce I-R and Ldildt voltage
developed along their connecting paths. If the
lead length from Cx to pins (6) and (7) or pins (14)
and (15) is greater than 3 cm, for example, the output pulse width might be quite different from
values predicted from the appropriate equations.
A non-inductive and low capacitive path is
necessary to ensure complete discharge of Cx in
each cycle of its operation such that the output
pulse width will be accurate.

10.

Although the 'LS221's pin-out is identical to the
'LS123 it should be remembered that they are not
functionally identical. The 'LS123 is a retriggerable device Sllch that the output is dependent
upon the input t 'ansitions when its output "a" is
at the "High" state. Furthermore, it is recommended for the 'LS123 to externally ground the CEXl pin
for improved system performance. However, this
pin on the 'LS221 is not an internal connection to
the device ground. Hence, if substitution of an
'LS221 onto an 'LS123 design layout where the
CEXT pin is wired to the ground, the device will not
function.

11.

Vee and ground wiring should conform to good
high-frequency standards and practices so that
switching transients on the Vee and ground return
leads do not cause interaction between one-shots .
A O.D1I'F to 0.10 I'F bypass capacitor (disk ceramic
or monolithic type) from Vee to ground is necessary
on each device. Furthermore, the bypass capacitor
should be located as close to the Vce-pin as space'
permits.

10
100

10

1000

CEXT IpF)
TLlF1640g·4

FIGURE 2

6.

To obtain variable pulSe widths by remote trimming,
the following circuit is recommended:
Rx

PIN(7)OR(15)~il"

ex
PIN (6) 6R (14)

Rremote

J

Vee
TLlF1640g·5

Note: "Rremote" should be as close to the one-shot as possible.

FIGURE 3

7.

Output pulse width versus Vee and temperatures:
Figure 4 depicts the relationship between pulse
width variation versus Vee: Figure 5 depicts pulse
width variation versus temperatures.
10

..

Rm=5K
CexT = 1000 pF
TA=25°C

5

w

z

:z:

'-'

0

~

~

-5
-10

L -__~__-L__~__~

4

4.5

5

5.5

Vee (V)

* For further detailed device characteristics and output performance,

please refer 10 the NSe one·shol applicalion note AN·366.

TLlFI6409·6

FIGURE 4

4-254

.---------------------------------------------------------------.0
s:
~National

~

~ Semiconductor

~

8-

DM54LS240/DM74LS240, DM54LS241/DM74LS241
Octal TRI-STATE® Buffers/Line Drivers/Line Receivers

o

s:
~

~i

General Description
These buffers/line drivers are designed to improve both
the performance and PC board density of TRI-STATE buffers/drivers employed as memory-address drivers, clock
drivers, and bus-oriented transmitters/receivers. Featuri ng 400 mV of hysteresis at each low current PN P data line
input, they provide improved noise rejection and high
fanout outputs and can be used to drive terminated lines
down to 13311.

• Typical propagation delay times
Inverting 10.5 ns
Noninverting 12 ns
• Typical enable/disable time 18 ns
• Typ)cal power dissipation (enabled)
Inverting 130 mW
Noninverting 135 mW

o

s:
U1
~

r-

C/)

o

Features

Absolute Maximum Ratings (Note 1)

•
•
•
•

Supply Voltage
Input Voltage
Storage Temperature Range

TRI-STATE outputs drive bus lines directly
PNP inputs reduce DC loading on bus lines
Hysteresis at inputs improves noise margins
Typical 10L!sink current)
54LS 12mA
74LS 24mA
• TyplcalloH (source current)
54LS -12mA
74LS -15 mA

7V
7V
-65"Ct0150"C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be op~ted at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Co\ndltlons" table will
define the conditions for actual device operation.

Connection Diagrams
Dual-In-Line Package

Dual-In-Line Package
vcc

2G

lYl

2A4

lY2

2A3

lV3

2A2

lY4

2Al'

2V3

lA3

2V2

lA4

2Yl GND

17

lG . lAl

2Y4

lA2

2Y3

lA3

2Y2

lA4

2Yl GND

lG

lAl

2V4

lA2

TLIF/6411·2

TLlF/6411-1

54LS240(J)

74LS240(N)

74LS241(N)

54LS241 (J)

Function Tables
LS241

LS240

G
L
L
H

A
L
H

X

-s:...
~

Y
H
L
Z

G

X
X
X
H
H
L
L= Logic Low Level
H = Lagle High Level
X = Either Logic Low or Lagle High Level
Z= High Impedance

4-255

G
L
L
H

X
X
X

1A
L
H
X
X
X
X

2A
X
X
X
L

H
X

1Y
L
H

2Y

Z
L
H

Z

~
r-

...~

f

RecOmmended Operating Conditions
Symbol

DM74LS240,241

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

\ High Level Output
, Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

DM54LS240, 241

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75'

5

5.25

2

2

-55

Units
V
V

0.7

0.8

-12

-15

mA

12

24

mA

70

·C

125

0

V

Electrical Characteristics over recommended operating free:alr temperature range (unless otherwise noted)
Symbol

Parameter

Conditions

Min

Typ
(Note 1)

0.2

0.4

Max

VI

Input Clamp Voltage

Vee = Mln,ll= -18 mA

HYS

Hysteresis (VT + - VT _ )

Vee = Min

VOH

High Level Output Voltage

Vee = Min, VIH= Min
VIL = Max, 10H= -1 mA

DM74

2.7

Vee = Min, VIH= Min
VIL= Max, 10H= -3 mA

DM54/DM74

2.4

Vee = Min, VIH= Min
VIL = 0.5V, 10H = Max,

DM54/DM74

2

Vee = Min
V1L = Max
VIH=Mln

10L= 12 mA

DM74

0.4

10L= Max

DM54

0.4

DM74

0.5

Vee = Max
VIL= Max
VIH=Min

Vo=2.7V

20

/LA

Vo=0.4V

-20

/LA

VOL

Low Level Output Voltage

10Zii

Off·State Output Current,
High Level Voltage Applied

10ZL

Off·State Output Current,
Low Level Voltage Applied

II

Input Current at Maximum
Input Voltage

-1.5

Units
V
V
V

3.4 '

0.1

Vee= Max, VI=7V

V

mA,

J

IIH

High Level Input Current

Vee= Max, VI = 2.7V

20

/LA

IlL

Low Level Input Current

Vee = Max, VI = 0.4V

-0.2

mA

los

Short Circuit Output Current Vee= Max (Note 2)

lee

Supply Current

Vee= Max,
Outputs
Open

,

,

-225

mA

Outputs
High

LS240,
LS241

-40
13

23

mA

Outputs
Low

LS240

26

44

LS241

27

46

Outputs
Disabled

LS240

29

50

LS241

32

54

,

Nota1: AlllyplcalsareatVee=SV,TA=2S'e,
,
Nota 2: Not more than one output should be shorted at a time, and the duration should not exceed one second,
,

4·256

•

Switching Characteristics
Vcc =5V, TA=25°C (See Section 1 for Test Waveforms and Output Load)

Symbol
tpLH

tpHL

tPZL

tpZH

tpLZ

tpHZ

tpLH

tpHL

tpZL

tpZH

Parameter

Conditions

Min

Typ
(Note 1)

Max

Units
ns

Propagation Delay Time
Low to High Level Output

CL=45 pF
RL =6671l

LS240

3

9

14

LS241

5

12

18

Propagation Delay Time
High to Low Level Output

C L =45pF
RL = 6670

LS240

5

12

18

LS241

7

12

18

Output Enable Time to
Low Level

C L =45 pF
RL = 6671l

LS240

10

20

30

LS241

10

20

30

'Output Enable Time to
High Level

C L =45 pF
RL =667!l

LS240

5

15

23

LS241

10

15

23

Output Disable Time
from Low Level

C L =5 pF
RL =667!l

Output Disable Time
from High Level

LS240

7

15

25

LS241

8

15

25

C L =5 pF
RL =667!l

LS240

5

10

18

LS241

5

10

18

Propagation Delay Time
Low to High Level Output

CL =150pF
RL =6671l

LS240

5

11

18

LS241

6

14

21

Propagation Delay Time
High to Low Level Output

C L =150pF LS240
RL =667O
LS241

6

15

22

6

15

22

Output Enable Time to
Low Level

C L = 150 pF LS240
RL = 6671l
LS241

12

22

33

12

22

33

Output Enable Time to
High Level

C L =150pF LS240
RL =6670
LS241

6

18

26

11

18

26

,

4-257

ns

ns

ns

ns

ns

ns'

ns

ns

ns

~ '?'A National

~ ~Semiconductor

::E

c

~
....I

DM54LS242/DM74LS242, DM54LS243/DM74LS243
Quadruple Bus· Transceivers

;1;

::E General Description

c

Absolute Maximum Ratings

These four data line ·transceivers are designed for asynchronous two-way communications between data buses.
They can be used to drive terminated lines down to 133
ohms .

M
....I

~
::E Features

c

~

....I

;1;

• Two-Way Asynchronous Communication Between Data
Buses
• P-N-P Inputs Reduce D-C Loading
• Hysteresis (Typically 400 mV) at Inputs Improves Noise
Margin

Supply Voltage
Input Voltage
AnyG .
AorB
Storage Temperature Range

(Note 1)·
7V
7V
5.5V

- 65·Cto 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

::E

c

Connection Diagrams
Dual·ln·Line Package

Dual·ln·Line Package

Vee

GBA

Ne

lB

2B

3B

GAB

Ne

lA

2A

3A

4A

Vee

4B

GND

GBA

Ne

lB

2B

3B

Ne

lA

2A

3A

4A

TLIFI6412·1

7~LS242

54LS242 (J)

74LS243 (N)

54LS243 (J)

Function Table
LS242
Data Port
Status

LS243
Data Port
Status

GAB

GBA

A

B

A

B

H
L
H
L

H
H
L
L

0

.

.

0

I

I

ISOLATED
I
0

ISOLATED
0
I

• Possibly destructive ascillatla" may occur if the transceivers are enabled in
both directions at once.

=

GND
TUF/6412·2

(N)

Control
Inputs

.4B

=

I Input. 0
Output. (5 = Inverting Output.
H = High Logic Level. L= Low Logic Level

4-258

Recommended Operating Conditions
DM54LS242, 243
Symbol

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

DM74LS242, 243

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

V
V

2

-55

Units

0.7

0.8

-12

-15

mA

12

24

mA

70

DC

125

0

V

Electrical Characteristics over recommended operating free·air temperature range (unless otherwise noted)
Symbol

Conditions

Parameter

Min

Typ
(Note 1)

0.2

0.4

Max
-1.5

Units
V

VI

Input Clamp Voltage

Vcc= Min, II = -18 inA

HYS

Hysteresis (VT + - VT _)

Vce= Min

VOH

High Level Output Voltage

Vee = Min, VIH = Min
VIL = Max,loH= -1 mA

DM74

2.7

Vee= Min, VIH= Min
VIL = Max,loH= - 3 mA

DM54/DM74

2.4

Vee = Min, VIH= Min
VIL = 0.5V, 10H = Max

DM54/DM74

2

Vee = Min
VIL = Max
VIH = Min

10L= 12 mA

DM74

0.4

DM54

0.4

DM74

0.5

Vee = Max
VIL = Max
VIH=Min

Vo=2.7V

40

I'A

Vo=O.4V

-200

I'A

VI=5.5V

A or B

0.1

rnA

VI =7V

AnyG

0.1

rnA

VOL

Low Level Output Voltage

10L= Max

V
V

3.4

V

10ZH

Off-State Output Current,
High Level Voltage Applied

10ZL

Off-State Output Current,
Low Level Voltage Applied

II

Input Current at Maximum
Input Voltage

Vee = Max

IIH

'High Level Input Current

Vee = Max, VI=2.7V

20

I'A

Vee"f Max, VI = O.4V

-0.2

rnA

IlL

Low Level Input Current

los

Short Circuit Output Current Vee= Max (Note 2)

Icc

Supply Current

Vee = Max,
Outputs
Open

,

-225

rnA

Outputs
High

LS242,
LS243

22

38

mA

Outputs
Low

LS242

29

50

Outputs
Disabled

LS242

29

50

LS243

32

54

-40

LS243

Note 1: All typlcals are at vee= 5V, TA= 25'e.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

4-259

Switching Characteristics Vee = 5V, TA= 25°C (See Section 1 for Test Waveforms and Output Load)
. Symbol
tpLH

tpHL

tPZL

tpZH
/

tpLZ

tpHZ

tpLH

tpHL

tPZL

tPZH

Parameter

Conditions

Min

Typ
(Note 1)

Max

Propagation Delay Time
Low to High Level Output

C L =45pF
RL =6670

LS242

3

9

14

LS243

5

12

18

Propagation Delay Time
High to Low Level Output

C L =45pF
RL =6670

LS242

5

12

18

LS243

7

12

18

Output Enable Time to
Low Level

C L =45pF
R L =6670

LS242

10

20

30

LS243

10

20

30

Output Enable Time to
High Level

C L =45pF
R L =6670

LS242

5

15

23

LS243

10

15

23

Output Disable Time
from Low Level

C L =5pF
R L =6670

LS242

7

15

25

LS243

8

15

25

Outp.ut Disable Time
from High Level

C L =5 pF
RL = 6670

LS242

5

10

18

LS243

5

10

18

Propagation Delay Time
Low to High Level Output

CL=150pF
Rl =6670

LS242

5

11

18

LS243

6

14

21

Propagation Delay Time
High to Low Level Output

C L =150 pF
RL =6670

Output Enable Time to
Low Level
Output Enable Time to
High Level

LS242

6

15

22

' LS243

6

15

22

C L =150 pF
RL = 6670

LS242

12

22

33

LS243

12

22

33

C L = 150 pF
RL =6670

LS242

6

18

26

LS243

11

18

26

I

4-260

Units
ns

ns

ns

ns

ns

ns

ns

ns

'ns

ns

r------------------------------------------------------------------,c
:s:
~National
~

~ Semiconductor

r-

~

-:s:c
:t

DM54LS244/DM74LS244
Octal TRI-STATE® Buffers/Line Drivers/Line Receivers

General Description
These buffers/line drivers are designed to improve both
the performance and PC board density of TRI·STATE buf·
fers/drivers employed as memory·address drivers, clock
drivers, and bus·oriented transmitters/receivers. Featur·
ing 400 mVof hysteresis at each low current PNP data line
input, they provide improved noise rejection and high
fanout outputs and can be used to drive terminated lines
down to 1330.

Features

• Typical propagation delay times
Inverting 10.5 ns
.
Noninvertlng 12 ns
• Typical enable/disable time 18 ns
• Typical power dissipation (enabled)
Inverting 130 mW
Noninverting 135 mW

Absolute Maximum Ratings (Note 1)

•
•
•
•

TRI·STATE outputs drive bus lines directly
PNP inputs reduce DC loading on bus lines
Hysteresis at inputs improves noise margins
TypicalloL (sink current)
54LS 12 mA
74LS 24mA
• Typical 10H (source current)
54LS -12mA
74LS -15 mA

Supply Voltage
Input Voltage
Storage Temperature Range

Connection. Diagram

Function Table

7V
7V
- 65·Cto 150·C

Nate 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should

not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions:' table will
define the conditions for actual device operation.

Dual·ln·Line Package
lY3

2A2

lY4

2A 1

~

A

·L

L
H

L
H

X

Y
L
H
Z

L= Low logic Level
H = High Logic Level
X = Either Low or High. logic Level
Z= High Impedance
lG

lAl

2Y4

lA2

2Y3

lA3

2Y2

lA4

2Yl GND
TLlF/8442·1

545244 (J)

745244 (N)

4·261

~

r-

~

Recommended Operating Conditions
Symbol

DM54LS244

Parameter

Vee

Supply Voltage

V IH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

DM74LS244

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units
V
V

2
0.7

0.8

High Level Output
Current

-12

-15

mA

IOL

Low Level Output
Current

12

24

mA

TA

Free Air Operating
Temperature

70

·C

-55

125

0

V

Electrical Characteristics over recommended operating free·air temperature range (unless otherwise noted)
Symbol

Parameter

Conditions

Min

Typ
(Note 1)

0.2

'0.4

Max
-1.5

Units
V

VI

Input Clamp Voltage

Vee = Min, II = -: 18 mA

HYS

Hysteresis (VT + - VT _ )

Vee = Min

VOH

High Level Output Voltage

Vee = Min, VIH= Min
VIL = Max, IOH= -1 mA

DM74

2.7

Vee = Min, VIH = Min
VIL = Max, 10H= -3 mA

DM54/DM74

2.4

Vee = Min, VIH = Min
VIL =0.5V, 10H= Max

DM54/DM74

2

Vee= Min
VIL= Max
VIH = Min

10L= 12 mA

DM74

0.4

DM54

0.4

DM74

0.5

Vee = Max
VIL = Max
VIH = Min

Vo=2.7V

20

ItA

Vo=0.4V

-20

ItA

0.1

mA

VOL

Low Level Output Voltage

i ..

10L= Max

10ZH

Off·State Output Current,
High Level Voltage Applied

10ZL

Off·Staie Output Current,
Low Level Voltage Applied

II

Input Current at Maximum
Input Voltage

Vee= Max

VI=7V

V
V

3.4

/

V

IIH

High Level Input Current

Vee = Max

VI=2.7V

20

ItA

IlL

Low Level Input Current

Vee= Max

VI= O.4V

-0.2

mA

los

Short Circuit Output Current

Vee= Max (Note 2)

Icc

Supply Current

Vee= Max,
Outputs
Open

,

-225

mA

Outputs
High

13

23

mA

Outputs
Low

27

46

Outputs
Disabled

32

54

- 40

Nota 1: All typical. are at Vee= 5V. TA=25"e.
Note 2: Not more than one qutput should be shorted at a time, and the duration should not exceed one second.

4·262

c

s:
C1I

Switching Characteristics

.,::..

Vee = 5V, TA = 25°C (See Section 1 for Test Waveforms and Output Load)

Min

Typ
(Note 1)

Ma:c:

C L =45 pF
RL =6670

5

12

18

ns

Propagation Delay Time
High to Low Level Output

C L =45 pF
RL = 6670

7

12

18

ns

tPZL

Output Enable Time to
Low Level

C L =45pF
RL =6670

10

20

30

ns

tPZH

Output Enable Time to
High Level

C L =45pF
RL =6670

10

15

23

ns

tpLZ

Output Disable Time
from Low Level

C L =5 pF
R,L = 6670

8

15

25

ns

tpHZ

Output Disable Time
from High Level

C L =5 pF
RL =6t370

5

10

18

ns

tpLH

Propagation Delay Time
Low to High Level Output

C L =150pF.
RL = 6670

6

14

21

ns

tpHL

Propagation Delay Time
High to Low Level Output

C L = 150 pF
RL =6670

6

15

22

ns

tPZL

Output Enable Time to
Low Level

C L = 150 pF
RL =6670

12

22

33

ns

tPZH

Output Enable Time to
High Level

C L =150 pF
RL =6670

11

18

26

ns

Symbol

Parameter

Conditions

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

.

4·263

Units

ic

s:
~
....
en

t

~National

~ Semiconductor

~
~

lI)

:E

c

DM54LS245/DM74LS245 TRI·STATE® Octal Bus Transceiver
General Description
These octal bus .transceivers are designed for asynchro·
nous two·way communication between data buses. The
control function implementation minimizes external timing
requirements.

• IOL (sink current)
54LS 12mA
74LS 24 rnA
• IOH (source current)
54LS -12 rnA
74LS -15 rnA

The device allows data transmission from the A bus to the B
bus or from the B bus to the A bus depending upon the logic
level at the direction control (DIR) input. The enable input
(G) can be used to disable the device so that the buses are
effectively Isolated.

Absolute Maximum Ratings (Note 1)

• Bi·directional bus transceiver in a high-denslty 20·pin
package

Supply Voltage
Input Voltage
DIRorG
AorB
Storage Temperature Range

•
•
•
•
•

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the. device cannot be guaranteed. The device should
not be operated at these limits. The parametric values dellned In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Condllions" table will
define the conditions for actual device operation.

Features

TRI·STATE outputs drive bus lines directly
PNP inputs reduce DC loading on bus lines
HystereSiS at bus inputs improve noise margins
Typical propagation delay times, port·to·port 8 ns
Typical enable/disable times 17 ns

Connection Diagram

7V
7V
5.5V
-65·Ct0150·C

Dual·ln·Llne Package
ENABLE

VCC

DIR

G

A1

I

B1

B2

A3

A2

B3

B4

B5

B6

A4

A5

A6

A7

B7

A8

B6

GND
TWF/6413·1

54LS245 (J)

74LS245(N)

Function Table
Enable

G
L
L
H

Direction
Control
DIR

Operation

L
H
X

B data to A bus
A data to B bus
Isolation

H = high level. L = low level, X == irrelevant

4·264

Recommended Operating Conditions
Symbol

Parameter

Vee

Supply Voltage

V IH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

DM74LS245

DM54LS245
Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units
V

2

V

0.7

0.8

High LevEl.! Output
Current

-12

-15

mA

10L

Low Level Output
Current

12

24

mA

TA

Free Air Operating
Temperature

70

DC

125

-55

0

V

Electrica, Characteristics over recommended operating tree-air temperature range (unless otherwise noted)
Symbol

Conditions

Parameter

VI

Input Clamp Voltage

Vee= Min, II = -18 mA

HYS

Hysteresis (VT + - VT _ )

Vee= Min

VOH

High Level Output Voltage

Vee = Min, VIH= Min
VIL= Max, 10H= -1 mA

VOL

Low Level Output Voltage

Min

Typ
(Note 1)

0.2

0.4

-1.5

'OM74
DM54/DM74

2.4

'!Iee= Min, VIH = Min
VIL = 0.5V, 10H = Max

DM54/DM74

2

IOL=12mA'
10L= Max

Units
V
V

2.7

Vee= Min, VIH= Min
VIL = Max, 10H= - 3 mA

Vee= Min
VIL = Max
VIH=Min

Max

V
3.4

DM74

0.4

DM54

0.4

DM74

0.5

V

Vee= Max
VIL= Max
VIH = Min

Vo= 2.7V

10

p.A

Vo=0.4V

-200

p.A

Input Current at Maximum
Input Voltage

Vee = Max

Aor B

VI=5.5V

0.1

mA

DIRorG

Vl=7V

0.1

IIH

High Level Input Current

Vee = Max, VI= 2.7V

20

p.A

IlL

Low Level Input Current

Vee = Max, VI = 0.4V

-0.2

mA

-225

mA

70

mA

10ZH

Ott-State Output Current,
High Level Voltage Applied

10ZL

Otl-State Output Current,
Low Level Voltage Applied

II

los.

Short Circuit Output Current Vee= Max (Note 2)

Icc

Supply Current

-40

Outputs High
Outputs Low
Outputs at.Hi-Z

Notel: All typlcals are at Vce= SV, TA= 2s'e.
Note 2: Not more than one output shorted at a time, not to exceed one second duration,

48
Vec=Max

62

90

64

95

Switching Characteristics

Vec

= 5 V, TA = 25°'C

(See Section 1 for Test Waveforms and Output Load)
DM54/74

Symbol

Parameter

LS245

Conditions
Min

tPLH

Propagation Delay Time, Low-to-High-Level Output

tPHL

Propagation Delay Time, High-to-Low-Level Output

tpZL

Output Enable Time to Low Level

tpZH

Output Enable Time to High Level

tPLZ

Output Disable Time from Low Level

tpHZ

Output Disable Time from High Level

CL
RL

= 45 pF
= 667 {!

CL = 5 pF
RL = 667 n

tPLH

Propagation Delay Time, Low-to-High-Level Output

tPHL

Propagation Delay Time, High-to-Low-Level Output

tPZL

Output Enable Time 10 Low Level

IPZH

Output Enable Time to High Level

,

4-266

CL = 150 pF
RL = 667 n

Units

Typ

Max

8

12

ns

8

12

ns

27

40

ns

25

.40

ns

15

25

ns

15

25

ns

10

16

ns

11

17

ns

30

45

ns

30

45

ns

.------------------------------------------------------------,0
3:

~NaHonal

C1I
~

~ Semiconductor

-~

DM54LS247/DM74LS247, DM54LS2481 DM74LS248,
DM54LS249/DM74LS249 BCD-to-Seven Segment
Decodersl Drivers

o
3:
~

~

~

General Description

Features

The DM54LS24 71 DM74LS247 and DM54LS248J
DM74LS248 are electrically and functionally identical to
the DM54LS47/DM74LS47 and DM54LS48/DM74LS48,
respectively, and have the same pin assignments as their
equivalents. They can be used interchangeably in present
or future designs to offer designers a choice between two
indicator fonts. The DM54LS249/DM74LS249 is a 16-pin
version of the 14-pin DM54LS49 1DM74LS49. Included in
the DM54LS249/DM74LS249 circuit is the full functional
capability for lamp test and ripple blanking, which is not
available in the DM54LS49/DM74LS49 circuit. The
DM54LS247/DM74LS247, DM54LS248/DM74LS248, and
DM54LS249/DM74LS249 compose the E and the q with
tails. Composition of all other charactera, including display
patterns for BCD inputs above nine, is identical. The
DM54LS24 71 DM7 4LS24 7 features active-low outputs designed for. driving indicators directly, and the DM54LS2481
DM74LS248 and DM54LS249/DM74LS249 feature activehigh outputs for driving lamp buffers. All of the circuits have
full ripple-blanking input loutput controls and a lamp test input. Segment identification and resultant displays are
shown below. Display patterns for BCD input counts above
9 are unique symbols to authenticate input conditions.

• All circuit types feature lamp intensity modulation
capability

3:
C1I
~

i-

54LS247174LS247
• Open-collector outputs drive indicators directly
• Lamp-test provision
• Leading /trailing zero suppression

o
3:

54LS248174LS248

~

• Internal pull-ups eliminate need for external resistors
• Lamp-test provision
• Leading /trailing zero suppression

~

Absolute Maximum Ratings (Note I)
Supply Voltage
Input Voltage
Storage Temperature Range

7V
7V
- 65'Cto 150'C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should

not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Numerical Designations and Resultant Displays

2

3

4

5

7

6

B

9

10

11

12

13

14

15
TWF/6414-1

Driver Outputs
Type

Active
Level

Output
Configuration

Sink
Current

Max
Voltage

Typical
Power
Dissipation

DM54LS247
DM54LS248
DM54LS249
DM74LS247
DM74LS248
DM74LS249

low
high
high
low
high
high

open-collector
2 kG pull-up
open-collector
open-collector
2 kG pull-up
open-collector

12 rnA
2mA
4mA
24 rnA
6mA
8mA

15V
5.5 V
5.5 V
15V
5.5 V
5.5V

35mW
125mW
40mW
35mW
125mW
40mW

4-267

~

JD
3:
~

a

0

r-

t/)

o

54LS249174LS249
• Open-collector outputs
• Lamp-test provision
• Leading /trailing zero suppression

All of these circuits incorporate automatiC; leading and 1or
trailing-edge zero-blanking control (RBI and RBO). Lamp
test (LT) of these types may be performed at any time when
the BI/RBO node is at a high level. All types contain an
overriding blanking input (BI) which can be used to control
the lamp intensity by pulsing or to inhibit the outputs: tnputs
and outputs are entirely compatible for use with TTL or DTL
logic outputs.

Segment
Identification

o

Packages

J
J
J
N
N
N

-~
o
3:
~

r-

~

,

~
('II
en

Connection Diagrams

...J

~

:E

c

Dual-In-Line Package

eoq-n

Dual-In-Line Package

OUTPUTS

OUTPUTS

('II

en
...J
oqLt)

Vee

f

a

9

15

116

14

c

b

13

12

Vee

e

d

10

11

9

f

•

9

15

116

14

13

c

b

e

d

10'

11

12

9

:E

c

r:4
oq('II

en

...J

~

r-

-

0-

:E

-

r-

C

~

('II

en
...J
oq-

1

Lt)

:E
C

....:
oq-

B

2

e

3
LAMP
TEST

4
BI/RBO

5

7

6

0

RBI

INPUTS

1

A

G!:

2

INPUTS

4

3

e

B

BI/RBO

LAMP
TEST

INPUTS

A

0

54LS247(J)

TLlF/6414·3

74LS247(N)

54LS248(J)

~

:E

c

.oq.....

Dual-in-Line Package

('II

en
...J
oqLt)

:E
C

OUTPUTS

Vee

f

15

116

a

9

14

c

b

13

e

d

11

12

10

9

-

1
B

2

e

3
LAMP
TEST

Ie
GND

INPUTS

TLfF/6414·2

('II

en
...J

7

6

5
RBI

4
BI/RBO

5
RBI

7

6
A

0

INPUTS

Ie
GND

INPUTS

\

54LS249 (J)

74LS249(N)

4-268

TLlFJ64144

74LS248(N)

Function Tables

DM54LS247/DM74LS247
Decimal

Inputs

or

Outputs

BI/RBOt

b

H
H
H
H

ON
OFF
ON
ON

ON
ON
ON
ON

L
H
L
H

H
H
H
H

OFF ON
ON OFF
ON OFF
ON ON

L
L
H
H

L
H
L
H

H
H
H
H

ON ON ON ON
ON ON ON ON
OFF OFF OFF ON
OFF OFF ON ON

H
H
H
H

L
L
H
H

L
H
L
H

H
H
H
H

OFF
ON
OFF
OFF

X
L

X
L
X

X
L
X

L
L
H

OFF OFF OFF OFF OFF OFF OFF
OFF OFF OFF OFF OFF OFF OFF
ON ON ON ON ON ON ON

RBI

D

C

B

A

0
1
2
3

H
H
H
H

H
X
X
X

L
L
L
L

L
L
L
L

L
L
H
H

L
H
L
H

4
5
6

H
H
H
H

X
X
X
X

L
L
L
L

H
H
H
H

L
L
H
H

10
11

H
H'
H
H

X
X
X
X

H
H
H
H

L
L
L
L

12
13
14
15

H
H
H
H

X
X
X
X

H
H
H
H

BI
RBI
LT

X
H
L

X
L
X

X
L
X

7
B

9

Note

•

LT

Function

X

ON
OFF
OFF
OFF

c

•

d

I

9

ON ON ON ON OFF
ON OFF OFF OFF OFF
OFF ON ON OFF ON
ON ON OFF OFF ON
ON
ON
ON
ON

OFF OFF ON ON
ON OFF ON ON
ON ON ON ON
OFF OFF OFF OFF
ON
OFF
ON
OFF

ON
ON
OFF
OFF

ON
ON
ON
ON

1

OFF OFF OFF ON ON
OFF ON OFF ON ON
OFF ON ON ON ON
OFF OFF OFF OFF OFF
2
3
4

DM54LS248/DM74LS248, DM54LS249/DM74LS249
Decimal

or
Function

Outputs

Inputs

BI/RBOt

Note

a

b

c

d

•

I

9

H
H
H
H

H
L
H
H

H
H
H
H

H
H
L
H

H
L
H
H

H
L
H
L

H
L
L
L

L
L
H
H

L
H
L
H

H
H
H
H

L
H
H
H

H
L
L
H

H
H
H
H

L
H
H
L

L
L
H
L

H
H
H
L

H
H
H
L

L
L
H
H

L
H
L
H

H
H
H
H

H
H
L
L

H
H
L
L

H
H
L
H

H
H
H
H

H
L
H
L

H
H
L
L

H
H
H
H

H
H
H
H

L
L
H
H

L
H
L
H

H
H
H
H

L
H
L
L

H
L
L
L

L
L
L
L

, L
H
H
L

L
L
H
L

H
H
H
L

H
H
H
L

X

X
L
X

X
L
X

L
L
H

L
L
H

L
L
H

L
L
H

L
L
H

L
L
H

L
L
H

L
L
H

LT

RBI

D

C

B

A

0
1
2
3

H
H
H
H

H
X
X
X

L
L
L
L

L
L
L
L

L
L
H
H

L
H
L
H

4
5

6
7

H
H
H
H

X
X
X
X

L
L
L
L

H
H
H
H

L
L
H
H

B
9
10
11

H
H
H
H

X
X
X
X

H
H
H
H

L
L
L
L

12
13
14
15

H
H
H
H

X
X
X
X

H
H
H
H

BI
RBI
LT

X
H
L

X
L
X

X
L
X

L

X

1
1

1

2
3
4

H = high leve', L = low level, X = irrelevant
Not. 1: The blanking input (BI) must be open or held at a high logic level when output functions 0 through
15 are desired. The ripple-blanking input (RBI) must be open or high if blanking of a decimal zero is not
desired.
Nota 2: When

8

low logic level is applied directly to the blanking input (BI), all segment outputs are low

regardless of the level of any other input.
Note 3: When ripple-blanking input (RBI) and inputs A. B, C, Bnd D are at a low level with the lamp test input
high, all segment outputs go low and the ripple-blanking output (RBO) goes to a low level (response
condition).
Nota 4: When the blanking input/ripple-blanking output (BI/RBO) is open or held high and a low is applied
to the lamp-test input, all segment outputs are high.

t BI/RBO is a

wire-AND logic serving as blanking input (91) and/or ripple-blanking output (RBO).

4·269

Recommended Operating
Symbol

Parameter

Co~ditions
DM74LS247

DM54LS247
Min

Nom

Max.

Min

Nom

Max

4.5-

5

5.5

4.75

5

5.25

Units

V

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

0.7

0.8

V

VOH

High Level Output
Voltage (a thru g)

15

15

V

10H

High Level Output
Current (BI/RBO)

-50 .

-50

I,A

10L

Low Level Output
Current (a thru g)

12

24

mA

10L

Low Level Output
Current (BI/RBO)

1.6

3.2

mA

TA

Free Air Operating
Temperature

70

'C

2

V

2

-55

125

0

'LS247 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol

Parameter

Conditions.

VI

Input Clamp Voltage

Vee'" Min, II'" -18 mA

VOH

High Level Output
Voltage (BI/RBO)

Vee'" Min, VIL'" Max
10H",Max
VIH '" Min

leEX

High Level Output
Current (a thru g)

Vee'" Min, Vo=15V
VIL = Max, VIH = Min

VOL

Low Level Ouiput
Voltage

Vee=Min
10L=Max
VIL=Max
VIH=Min

DM54
DM74

10L= Max/2
Vee = Min

DM74

Min

Typ
(Note 1)

2.4

4.2

Max
-1.5

Units

V
V

250

~A

0.25

0.4

V

0.35

0.5

0.25

0.4 .

II

Input Current@Max
Input Voltage

Vee=Max, VI=7V

0.1

mA

IIH

High Level Input
Current

Vee = Max, VI=2.7V

20

~A

IlL

Low Level Input
Current

Vee = Max
VI=0.4V

los

Short Circuit
Output Current
(BI/RBO)

Vee'" Max

Icc

Supply Current

Vee = Max
(Note 2)

BI/RBO

-1.2

Others

-0.4
-0.3

7

Note 1: All typlcals are at Vee=SV. TA=2S'e.
Note 2: ICC Is measured with all outputs open and all Inputs at 4.SV.

4·270

mA

-2

mA

13

mA

'LS247 Switching Characteristics
at Vee = 5V and TA = 25·C (See Section 1 for Test Waveforms and Oulput Load)
From
(Input)
to
(Output)

Parameter

RL=665!l
CL=15 pF
Min

Units

Typ

Max

tpLH Propagation Delay
Time Low to High
Level Output

AorRBI
to
Any Output

100

ns

tpHL Propagation Delay
Time High to Low
Level Output

AorRBI
to
Any Output

100

ns

Recommended Operating Conditions
Symbol

Parameter

DM74LS248

DM54LS248
Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units

Vee

Supply Voltage

V1H

High Level Input
Voltage

V1L

Low Level Input
Voltage

0.7

0.8

V

VOH

High Level Output
Voltage (a thru g)

5.5

5.5

V

IOH

High Level Output
Current (BI/RBO)

-50

-50

/lA

High Level Output
Current (a thru g)

-100

-100

2

V
V

2

IOL

Low Level Output
Current (a th ru g)

2

6

rnA

IOL

Low Level Output
Current (BI/RBO)

1.6

3.2

mA

70

·C

. TA

Free Air Operating
Temperature

-55

125

-.-

4-271

0

'LS248 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol

Conditions

Parameter

\

Min

Typ
(Note 1)

4.2

Max
-1.5

VI

Input Clamp Voltage

Vee = Min, 11= -18 mA

VOH

High Level Output
Voltage

Vee = Min, 10H = Max
VIL = Max, VIH = Min

2.4

leEX

High Level Output
Current

Vee=Min, Vo=0.85V
VIH = Min, VIL = Max

-1.3

VOL

Low Level Output
Voltage

Vee = Min
10L= Max
VIL=Max
VIH=Min

DM54

0.24

0.4

DM74

0.35

0.5

IOL=2mA
Vee=Min

DM74

0.25

0.4

Units
V
V

-2

mAo
V

II

Input Current@Max
Input Voltage

Vee = Max, VI=7V

0.1

mA

IIH

High Level Input
Current

Vee=Max, VI=2.7V

20

p.A

IlL

Low Level Input
Current

Vee=Max"
VI=0.4V

BI/RBO

-1.2

mA

Others

-0.4

los

Short Circuit
Output Current

Vee = Max (BI/RBO)

Icc

Supply Current

Vee = Max (Note 2)

Nole 1: All typicals are at Vee=SV. TA=2S"e.
Nole 2: ICC is measured with all outputs open and ·all

Switching Characteristics
Parameter

From
(Input)
To
(Output)

tpLH Propagation Delay
Time Low to High
Level Output

A
to
Output

tpHL Propagation Delay
Time High to Low
Level Output

A
to
Output

tpLH Propagation Delay
Time Low to High
Level Output

RBI
to
Output

tpHL Propagation Delay
Time High to Low
Level Output

RBI
to
Output

-0.3
25

-2

mA

38

mA

inputs at 4.SV.

at Vec =

5\1 and TA = 25°C

(See Section 1 for Test Waveforms and Output Load)

RL = 4 k{J(A), 6 kIl(RBI)
CL= 15pF
Min

,

\

4·272

CL=50pF
Max

Typ

Min

Typ

Units
Max

100

100

ns

100

100

ns

100·

100

ns

100

100

ns

Recommended Operating Conditions
Symbol

Parameter

DM54LS249

DM74LS249

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

0.7

0.8

V

VOH .

High Level Output
Voltage (a thru g)

5.5

5.5

V

10H

High Level Output
Current (BI/RBO)

-50

-50

,.A

10L

Low Level Output
Current (a thru g)

4

8

mA

10L

Low Level Output
Current (BI/RBO)

1.6

3.2

mA

TA

Free Air Operating
Temperature

70

·C

2

2

-55

V

0

125

V

'LS249 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol

Parameter

Conditions

Min

Typ
(Note 1)

Max

VI

Input Clamp Voltage

Vee = Min, II = - 18 mA

-1.5

VOH

High Level Output
Voltage (BI/RBO)

Vec = Min, VIL = Max
10H= Max
V IH = Min

ICEX

High Level Output
Current (a thru g)

Vcc = Min, Vo = 5.5V
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vcc=Min
10L=Max.
VIL = Max
VIH = Min

DM54
DM74

IOL=Max/2
Vcc=Min

DM74

0.25

0.4

2.4

4.2

'Units
V.
V

250

,.A

0.25

0.4

V

0.35

0.5

II

Input Current@Max
Input Voltage

Vcc= Max, VI= 7V

0.1

mA

IIH

High Level Input
Current

Vcc=Max, VI=2.7V

20

,.A

IlL

Low Level Input
Current

Vec= Max
V I =0.4V

BIJRBO

-1.2

mA

Others

-0.4

los

Short Circuit
Output Current
(BI/RBO)

Vcc=Max

Icc

Supply Current

Vce = Max (Note 2)

-0.3

8

-2

mA

15

mA

Not. 1: All typicals are at Vee =SV, TA =2S·C.
Not.2: ICC is measured wilh all oulputs open and all Inpuls at 4.SV.
I

4-273

Switching Characteristics
Parameter

From
(Input)
To
(Output)

at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL = 2 kO(A), 6 kll(RBI)
C L =15pF
Min

Typ

CL=50pF
Max

Min

Typ

Units
Max

tpLH Propagation Delay
Time Low to High
Level Output

A
to
Output

100

100

ns

tpHL Propagation Delay
Time High to Low
Level Output

A
to
Output

100

100

ns

tpLH Propagation Delay
Time Low to High
Level Output

RBI
to
Output

100

100

ns

tpHL Propagation Delay
Time High to Low
Level Output

~BI

100

100

ns

to
Output

-

i

4-274

Logic Diagrams
DM54LS247/DM74LS247

")o-{)oo-:.(1;,:3.:..)
INPUT
A

(7)

INPUT

(1)

(12)

OUTPUT
b

(11)

OUTPUT

(10)

OUTPUT
d

(9)

OUTPUT

B

INPUT

(2)

C

INPUT (6)
0

BI/RBO
BLANKING
(4)
INPUT OR
RIPPLE BLANKING
OUTPUT

OUTPUT

e

(15)

OUTPUT
f

(14)

OUTPUT

LAMP TEST (3)
INPUT
RBI
(5)
RIPPLE BLANKING
INPUT

TLlF/6414·5

DM54LS248/DM74LS248,DM54LS249/DM74LS249

OUTPUT
INPUT
A

(7)

INPUT
B

(1)

INPUT

(2)

OUTPUT
b

OUTPUT

C

INPUT
0

(6)

OUTPUT
d

BI/RBO
BLANKING
(4)
INPUT OR
RIPPLE BLANKING
OUTPUT

OUTPUT

e

OUTPUT
f

LAMP TEST (3)
INPUT
-

~~~NKING ~~-t===

RIPPLE
INPUT

____--=:::!i:J
4·275

~

,-----------------------------------------------------------------------------------,

~ '?'A National
...I

~
:is
c

~

II)

'N

en
...I
~
II)

:is

c

~ Semiconductor

DM54LS251/ DM74LS251. TRI-STATE® Data
Selectors/Multiplexers
General Description
These data selectors/multiplexers contain full on-chip binary decoding to select one-of-eight data sources. and feature a strobe-controlled TRI-STATE output. The strobe must
be at a low logic level to enable these devices. The TRISTATE outputs permit direct connection to a common bus.
When the strobe input is high. both outputs are in a highimpedance state in which both the upper and lower transistors of each totem-pole output are off. and the output
neilher drives nor loads the bus significantly. When the
strobe is low. the outputs are activated and operate as
standard TTL totem-pole outputs.
To minimize the possibility that two outputs will attempt to
take a common bus to opposite logic levels. the output control circuitry is designed so that the average output disable
time is shorter than the average output enable time.

• Typical propagation delay time (D to Y)
54LS 17 ns
74LS 17 ns
• Typical power dissipation
54LS 35mW
74LS 35mW

Absolute Maximum Ratings (Note 1)
Supply Voltage
'Input Voltage

7V
7V
-65·Ct0150·C

Storage Temperature Range

Features
•
•
•
•

• Complementary outputs provide true and inverted data
• Maximum number of common outputs
54LS 49
74 LS 129

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined In the

TRI-STATE version of LS151
Interface directly with system bus
Perform parallel-to-serial conversion
Permit multiplexing from N-lines to one line

"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual-In-Llne Package
DATAINPUT$

VIcc
16

'04
15

05

06

14

13

Inputs

DATA SELECT

D7'
12

B

A
11

C'

10

6 7 .1.8
...:'D:.:3~...;D::2:.....--=D:..1_..:DO;.:"
DATA INPUTS

54LS251 (J)

Outputs

1-__S_e_le_c_t_--i Strobe

~ STROBE GND
OUTPUTS
TL/F/6415·1

c

BAS

X
L
L
L
L
H
H
H
H

X
L
L
H
H
L'
L
H
H

X
L
H
L
H
L
H
L
H

H
L

L
L
L
L
L
L
L

Y

W

z

Z

DO
Dl
D2

DO
D1
D2

03
D4
D5
D6

D3
D4
D5
D6

07

D7

H = High Logic Level, l = Low Logic Level
X = Don't Care, Z = High Impedance (Off)
DO, 01 .. . D? = The Level 01 the respective 0 input.

74LS251 (N)

4-276

c
3:
~

Recommended Operating Conditions

rSymbol

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

Electrical Characteristics
Symbol

Parameter

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2
0.7
-1
12
125

0

V

-2.6

mA

24

mA

70

DC

over recommended operating free air temperature (unless otherwise noted)
Min

Typ
(Note 1)

DM54

2.4

3.4

DM74

2.4

3.1

Conditions

VI

Input Clamp Voltage

Vee=Min,ll= -1B mA

VOH

High Level Output
Voltage

Vee = Min
IOH=Max
VIL=Max
VIH=Min

, Low Level Output
Voltage

Vee = Min
IOL= Max
VIL=Max
VIH=Mln

VOL

O.B

IOL= 12 mA
Vee=Min

Max
-1.5

Units
V
V

DM54

0.25

0.4

DM74

0.35

0.5

DM74

0.25

0.4

V

II

Input Current@Max
Input Voltage

Vee = Max, VI =7V

0.1

mA

IIH

High Level Input
Current

Vee=Max, VI=2.7V

20

p.A

IlL

Low Level Input
Current

Vee=Max, VI=0.4V

-0.4

mA

10ZH

Off-State Output
Current with High
Level Output
Voltage Applied

Vee= Max, Vo=2.7V
VIH = Min, VIL = Max

20

p.A

10ZL

Off-State Output
Current with Low
Level Output
Voltage Applied

Vee = Max, Vo=0.4V
VIH = Min, VIL = Max

-20

p.A·

los

Short Circuit
Output Current

Vee = Max
(Note 2)

-20

-100

mA

-20

-100

lee1

Supply Current

Vee = Max (Note 3)

6.1

10

mA

lee2

Supply Current

Vee = Max (Note 4)

7.1

12

mA

Nol.l:
Note 2:
Nol.3:
Note 4:

DM54
DM74

All typicals are at Vee=SV, TA=2S"e.
Not more than one output should be shorted at a time, and the duration should not exceed one second.
leC1 Is measured with the oulpuls open, STROBE grounded, and all other Inputs at 4.SV.
leC2 is measured with the outputs open and all Inputs at 4.SV.
4-277

,

en

N

c.n
......

V
V

2

-55

Units

-c
3:

i:!
r-

~
c.n
......

Switching Characteristics
From
(Input)
To
(Output)

Parameter

at Vcc=5V and TA=25"C (See Section 1 for Test Waveforms and Output Load)
RL = 66W
CL=45 pF
Min

Typ.

CL=150 pF
Max

Min

Units

Typ

Max

tpLH Propagation Delay
Time Low to High
Level Output

A,B,C
(4 Levels)
toY

29

45

35

53

ns

tpHL Propagation Delay
Time High to Low
Level Output

A,B,C
(4 Levels)
toY

28

45

35

53

ns

tpLH Propagation Delay
Time Low to High
Level Output

A,B,C
(3 Levels)
toW

20

33

25

38

ns

tpHL Propagation Delay
Time High to Low
Level Output

A,B,C
(3 Levels)
toW

21

33

28

42

ns

tpLH Propagation Delay
Time Low to High
Level Output

D
to
Y

17

28

23

35

ns

tpHL Propagation Delay
Time High to Low
LeVel Output

D
to
Y

18

28

25

38

ns

tpLH Propagation Delay
Time Low to High
Level Output

D
to
W

10

15

16

25

ns

tpHL Propagation Delay
Time High to Low
Level Output

D
to
W

9

15

16

25

ns

tPZH Output Enable
Time to High
Level Output

Strobe
to
Y

30

45

40

60

ns

tpZL Output Enable
Time to Low
Level Output

Strobe
to
Y

26

40

~4

51

n5

tpHZ Output Disable
Time from High
Level Output (Note 1)

Strobe
to
Y

30

45

ns

tpLZ Output Disable
Time from Low
Level Output (Note 1)

Strobe
to
Y

15

25

ns

tpZH Output Enable
Time to High
Level Output

Strobe
to
W

17

27

26

40

ns

t PZL Output Enable
Time to Low
Level Output

Strobe
to
W

24

40

31

47

ns

tpH·Z Output Disable
Time from High
Level Output (Note 1)

Strobe
to
W

37

55

ns

tpLZ Output Disable
Time from Low
Level Output (No,te 1)

Strobe
to
W

15

25

ns

\

Notal: CL=5 pF,

4·278

~--------------------------------------------~---------------'C

3:
~

Logic Diagram

~

...a.

C

3:
~
r-

~...a.

4-279

~r------------------------------------------------------------------------;

~..J

~National

~ Semiconductor
o DM54LS253/DM74LS253 TRI-STATE® Data
Selectors/ Multiplexers
~

::E

~
II)
('II

en
....I General Description

;:g

::E

o

Each of these Schottky-clamped data selectors I
multiplexers contains inverters and drivers to supply fully
complementary, on-chip, binary decoding data selection to
the AND-OR gates_ Separate output control inputs are provided for each of the two fpur-line sections_

• Strobe/output control
• High fanout totem-pole outputs
• Typical propagation delay
Data to output 12 ns
Select to output 21 ns

The TRI-STATE outputs can interface directly with data
lines of bus-organized systems_ With all but one of the common outputs disabled (at a high impedance state), the low
impedance of the single enabled output will drive the bus
line to a high or low logic level.

• Typical power dissipation 35 mW

Absolute Maximum Ratings (Note 1)

Features

Supply Voltage
Input Voltage
Storage Temperature Range

•
•
•
•

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defiF1ed in the
"Electrical Characteristics" table are not 'guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions tor actual device operation.

TRI-STATE version of LS153 with same pinout
Schottky-diode-clamped transistors
Permit multiplexing from N-lines to one line
Performs parallel-to-serial conversion

Connection Diagram

7V
7V
-65·Ct0150·C

Function Table

Dual-In-Line Package

1.

OUTPUT
CONTROL

VC

J16

G2

15

DATA INPUTS

SELECT ' 2~3

114

1'3

2y2 21'
1'2

1"

Select
Inputs

OUTPUT

290'

J10

~2

19

Data Inputs

Output
Control

Output

B

A

~O

C1

C2

C3

G

y

X
L
L
L
L
H
H
H
H

X

X

X

x

X

L

L

X

X

X

Z
L

L
H
H
L
L
H
H

H
X
X
X
X
X
X

X
L

X
X
X
L
H
X
X

X
X
X
X
X
L
H

H
L
L

H

X
X
X
X

L
L

L

L
L
L

H
L
H
L
H

L
H

Address inputs A and B are common to both sections.
H = High Level, L= Low Level, X= Don't Care, Z= High Impedance (off).
TLlFJ6416-1

54LS253 (J)

74LS253 (N)

4-280

Recommended Operating Conditions
Symbol

DM54LS253
Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

V IL

Low Level Input
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

Electrical Characteristics
Symbol

Parameter

DM74LS253

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

V
V

2
0.7
-1

-2.6

rnA

24

rnA

70

'C

12
-55

V

0.8

125

0

over recommended operating free air temperature (unless otherwise noted)
Conditions

Min

Typ
(Nole 1)

'>

Max

VI

Input Clamp Voltage

Vcc= Min, 11= -18 rnA

VOH

High Level Output
Voltage

Vcc=Min
10H=Max
VIL= Max
VIH=Min

DM54

2.4

3.4

DM74

2.4

3.1

Low Level Output
Voltage

Vcc=Min
10L=Max
VIL=Max
VIH=Min

DM54

0.4

DM74

0.5

IOL=12mA
Vcc=Min

DM74

0.4

VOL

Units

-1.5

Units
V
V

V

II

Input Current@Max
Input Voltage

Vcc=Max, VI=7V

0.1

rnA

IIH

High Level Input
Current

Vcc=Max, VI=2.7V

20

p.A

IlL

Low.Level Input
Current

Vcc = Max, VI = 0.4V

-0.4

rnA

IOZH

Off·State Output
Current with High
Level Output
Voltage Applied

Vcc=Max, Vo=2.7
VIH = Min, VIL = Max

20

p.A

10ZL

Off·State Output
Current with Low
Level OutpiJt
'voltage Applied

Vcc = Max, Vo = 0.4
VIH ;" Min, VIL = Max

-20

p.A

los

Short Circuit
Output Current

Vcc=Max
(Note 2)

rnA

ICCl

Supply Current

Vcc = Max (Note 3)

ICC2

Supply Current

,

DM54

-20

-100

DM74

-20

-100

Vcc=Max (Note 4)

Nole 1: Aillypicals are al VCC=SV, TA=2S'C.
Nole 2: NOI more Ihan one oulpul should be shorted al a lime, and Ihe durallon should nol exceed one second.
Note 3: ICC1 is measured with all outputs open, and all the Inputs grounded.

Nole 4: ICC2 is measured wilh Ihe oulpuls open, OUTPUT CONTROL al 4.SV and all olher inpuls grounded.
4·281

7

12

rnA

8.5

14

rnA

C")
it)

C'I

en

Switching Characteristics

~

From
(Input)
To
(Output)

at Vcc=5V and TA=25°C (See Section 1 for Test Waveforms and Output Load)

..J

:E

0

Parameter

C ")
it)

C'I
(/)

..J
~
it)

:E

0

RL=6670
C L =45 pF
Min

CL=150 pF

Typ

Max
25

Min

Units

Typ

Max

23

35

ns

tpLH Propagation Delay
Time Low to High
Level Output

Data
to
Y

17

tpHL Propagation Delay
Time High to Low
Level Output

Data
to
Y

13

20

20

30

ns

tpLH Propagation Delay
Time Low to High
. Level put put

Select
to
Y

30

45

36

54

ns

tpHL Propagation Delay
Time High to Low
Level Output

Select
to
Y

21

32

29

44

ns

tPZH Output Enable
Time to High
Level Output

Output
Control
toY

10

18

20

32

ns

tPZL Output Enable
Time to Low
Level Output

Output
Control
toY

15

23

23

35

ns

tpHZ Output Disable
Time from High
Level Output (Note 1)

Output
Control
toY

27

41

ns

tpLZ Output Disable
Time from Low
Level Output (Note 1)

Output
Control
to Y

18

27

ns

"

'.

Nole1: CL=5pF.

Logic Diagram
OU~UT~~________~r-,

:\'~:

-~~"

-:---;:==::t:~~I_~_'-"
.

lC3,(:;;3,-)

SELECTll'~
:~

~TA21~~::~:------rt~~~rr~
2C2
(9)

-r+---1I-t-_

OUTP~V2

2C3(:.;.13;.;,)_ _ _ _ _

OU~UT(15)

CONTROLG2

t::::= ~ ,

TlIF16416·2

4·282

r------------------------------------------------------------------,c
:s::

~National

~

~ Semiconductor

~

....,

-:s::
aI
C

DM54LS2578/DM74LS2578, DM54LS2588/DM74LS2588
TRI·STATE® Quad 2·Data Selectors/Multiplexers

~

r-

~

....,

U1

.!»

General Description
These Schottky-clamped high-performance multiplexers
feature TRI-STATE outputs that can interface directly with
data lines of bus-organized systems. With all but one of the
common outputs disabled (at a high impedance state), the
low impedance of the single enabled output will drive the
bus line to a high or low logic level. To minimize the possibility that two outputs will attempt to take a common bus to
opposite logic levels, the output enable circuitry is designed such that the output disable times are shorter than
the output enable times.
This TRI-STATE output feature means that n-bit (paralleled)
data selectors with up to 258 sources can be im.plemented
for data buses. It also permits the use of standard TTL registers for data retention throughout the system.

Features
• TRI-STATE versions LS157 and LS158 with same pin-outs
• Schottky-clamped for significant improvement in
A-C performance

j,6

15

14

13

12

A3
11

83

Input Voltage
Storage Temperature Range

1

7V
-65'Cto150'C

OUTPUT ~ OUTPUT
Vcc CONTROL A4
B4
V4

9

116

14

15

13

12

~
A3
11

83

OUTPUT
V3

10

4
6
5
.1
8
VI
A2
82
V2
GND
~ OUTPUT ~ OUTPUT
2

AI

3

SELECT

TUFf6417-1

54LS257B (J)

74LS257B (N)

4

3

2
AI

81

~

5

6

7

Is

VI
A2
82
V2
GND
OUTPUT ~ OUTPUT
TUF/6417·2

54LS258B (J)

4-283

9

P-

I

. 1

Bl

aI
C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table arB not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table Will
. define the conditions for actual device operation.

r-

SELECT

-:s::
7V

Supply Voltage

OUTPUT
V3

10

co

~

Dual-In-Llne Package

~

~

N
U1

Absolute Maximum Ratings (Note 1)

Dual-In-Llne Package
OUTPUT ~ OUTPUT
Vcc CONTROL A4
84
V4

~

• Average propagation delay from data input 12 ns
• Typical power dissipation
LS257B SOmW
LS258B 3SmW

Diagr~ms

Connection

c
:s::

• Provides bus interface from multiple sources in hlghperformance systems

74LS258B (N)

~

aI

•

Function Table

Output Y

Inputs
Output
Select
Control

H
Z

A

B

LS257

LS258

X
X
X

Z
L

H

H

L

L

L

H

H

L

H

X

X

L
L
L
L

L
L

L

H
H

H
X
X

H

= High level. L = Low Level, X =

Z

Don'l Care

= High Impedance (off)

Logic Diagrams

LS257B

LS258B

QU11'UT(151

OUTPUT ('51

-r,

Com-:~L(;..21_ _ _ _ _ _ _

CONTRO~,.::(2::.1_ _ _ _ _ _-;"7""""\

a1(;,. 3:.. .1---+----'"'1

-+___+-,",\

1 __
A2 (._5:....

a2(61

B2 (:;;6:....1- - _ t - - - t - I r " ' l

-r___r1~

A3 (_";..I_ _

a3 (,.:.'0:;:1_ _-I-___Hr-"'I

aJ_'0;..1_ _-+_ _ _~r-"'I

M(~1~41_ __t---+_~

(141
A4.~---+---~r-"'I

a4(~1.::31_ __t---+_,"'I

a!._'3;..1_ _-+___+-,"'1

TLIFI6417-3

TLIFI6417-4

4-284

Recommended Operating Conditions
Symbol

DM54LS257B
Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

DM74LS257B

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

O.B

0.7
-1

V

-2.6

rnA

24

mA

70

·C

12
125

V
V

2

-55

Units

0

'LS257B Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol

Parameter

Min

Typ
(Note 1)

DM54

2.4

3.4

DM74

2.4

3.1

Conditions

VI

Input Clamp Voltage

Vee=Mln, 11= -1B mA

VOH

High Level Output
Voltage

Vee=Min
IOH = Max
VIL = Max
VIH=Mln

Low Level Output
Voltage

Vee = Min
IOL=Max
VIL=Max
VIH=Mln

Vo~

Max
-1.5

Units
V
V

DM54

0.25

0.4

DM74

0.35

0.5

IOL= 12 mA
Vee=Min

DM74

0.25

0.4

Input Current@Max
Input Voltage

Vee = Max
VI=7V

Select

0.2

Other

0.1

High Level Input
Current

Vee=Max
VI = 2.7V

Select

40

Other

20

Low Level Input
Current

Vee = Max
VI =0.4V

10ZH

Off·State Output
Current with High
Level Output
Voltage Applied

Vee = Max, Vo=2.7V
VIH = Min, VIL = Max

20

/LA

10ZL.

Off·State Output
Current with Low
Level Output
Voltage Applied

Vee = Max, Vo=0.4V
VIH = Min, VIL = Max

-20

/LA

los

Short Circuit "
Output Current

Vee = Max
(Note 2)

mA

leeH

Supply Current With
Outputs High

Vee = Max (Note 3)

5.9

10

mA

leeL

SupplY'Current With
Outputs Low

Vee = Max (Note 3)

9.2

16

mA

leez

Supply Current With
Outputs Disabled

Vee = Max (Note 3)

12

19

mA

II

IIH

IlL

Select

-O.B

Other

-0.4

DM54

-20

-100

DM74

-20

-100

Nota 1: All typlcals are at VCC=c5V, TA=25"C.
Nota 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Note 3: ICC Is meas,ured with aI/ outputs open and all possible inputs grounded, while achieving the stated output conditions.

4·285

V

mA

/LA
mA

'LS257B Switching Characteristics
at Vcc = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)

Parameter

From
(Input)
To
(Output)

RL=667{l
CL=45 pF
Min

Units

CL=150 pF

Typ

Max

Min

Typ

Max

tpLH Propagation Delay
Time Low to High
Level Output

Data
to
Output

12

18

18

27

ns

tpHL Propagation Delay
Time High to.Low
Level Output

Data
to
Output

12

18

18

27

ns

tpLH Propagation Delay
Time Low to High
Level Output

Select
to
O_utput

18

28

23

35

ns

tpHL Propagation Delay
Time High to Low
Level Output

Select
to
Output

22

35

28

42

ns

tPZH Output Enable
Time to High
Level Output

Output
Control
toY

8

15

18

27

ns

tPZL Output Enable
Time to Low
Level Outpu't

Output
Control
_ to Y

17

28

25

38

ns

tpHZ Output Disable
Time from High
Level Output (Note 1)

Output
Control
toY

17

26

ns

tpLZ Output Disable
Time from Low
Level 9utput (Note 1)

Output
Control
toY

14

25

ns

-

,

Nole1: CL=5 pF.

.

,

4-286

,

!
I

Recommended Operating Conditions
Parameter

Symbol
Vee

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level Input
Voltage

IOH

High Level Output
Current

. IOl

Low Level Output
Current

TA

Free Air Operating
Temperature

-

DM54LS258B

DM74LS258B

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2
0.7

V

0.8

-1

-2.6

mA

24

mA

70

·C

12
125

V
V

2

-55

Units

0

'LS258B Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol

Parameter

Min

Typ
(Note 1)

DM54

2.4

3.4

DM74

2.4

3.1

Conditions

Max
-1.5

Units
V

VI

Input Clamp Voltage

Vee = Min, 11= -18 rnA

VOH

High Level Output
Voltage

Vee=Min
10H= Max
Vll = Max
VIH=Min

Low Level Output
Voltage

Vee=Min
10l=Max
Vll=Max
VIH=Min

DM54

0.25

0.4

DM74

0.35

0.5

10l" 12 rnA
Vee=Min

DM74

0.25

0.4

Input Current@Max
Input Voltage

Vee=Max
VI=7V

Select

0.2

Other

0.1

High Level Input
Current

Vee=Max
VI = 2.7V

Select

40

Other

20

Low Level Input
Current

Vee= Max
VI =O.4V

Select

-0.8

Other

-0.4

IOZH

Off·State Output
Current with High
Level Output
Voltage Applied

Vee = Max, Vo=2.7V
VIH = Min, Vil = Max

20

~f!.

10Zl

Off·State Output
Current with Low
Level Output
Voltage Applied

Vee= Max, Vo=0.4V
VIH = Min, Vil = Max

-20

~A

Short Circuit
Output Current

Vee = Max
(Note 2)

rnA

leeH

Supply Current With
Outputs High

Vee = Max (Note 3)

4.1

7

rnA

leel

Supply Current With
Outputs Low

Vee = Max (Note 3)

9

14

rnA

lecz

Supply Current With
Outputs Disabled

Vee = Max (Note 3)

12

19

mA

Val

~

II

IIH

III

los

V

V

rnA
~A

rnA

DM54

-20

-100

DM74

-20

-100

Note 1: All typlcals are at VCC=SV, TA=2S·C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Note 3: ICC Is measured with all outputs open and all possible inputs grounded, while achieving the stated output conditions.

4·287

'LS258B Switching Characteristics
at Vcc=5V and TA=25°C (S'le Section 1 for Test Waveforms and Output Load)

Parameter

From
(Input)
To
(Output)

RL = 667(1
C L =45 pF
Min

C L =150 pF

Typ -

Max

Min

Units

Typ

Max

tpLH Propagation Delay
Time Low to High
Level Output

Data
to
Output

12

18

18

27

ns

tpHL Propagation Delay
Time High to Low
Level Output

Data
to
Output

12

18

18

27

ns

t PLH Propagaiion Delay
Time Low to High
Level Output

Select
to
Output

18

28

23

35

ns

tpHL Propagation Delay
Time High to Low
Level Output

Select
to
Output

22

35

28

42

ns

t PZH Output Enable
(
Time to High
Level Output

Output
Control
toY

8

15

18

27

ns

tpZL Output Enable
Time to Low
Level Output

Output
Control
toY

17

28

25

38

ns

tpHz Output Disable
Time from High
Level Output (Note 4)

Output
Control
toY

17

26

ns

t PLZ Output Disable
Time from Low
Level Output (Note 4)

Output
Control
toY

14

25

ns

Note 4:

CL ~ 5 pF .

•

4·288

r---------------------·--~~------------------------------------,C

~National

3:
en

DM54LS259/DM74LS259 a-Bit Addressable Latches

-m
c

"..

r-

~ Semiconductor

3:
~

General Description

r-

These 8·bit addressable latches are designed for general
purpose storage applications in digital systems. Specific
uses include working registers, serial-holding registers,
and active-high decoders or demultiplexers. They are
multifunctional devices capable of storing single-line data
in eight addressable latches, and being a '-of-8 decoder or
demultiplexer with active-high outputs.
Four distinct modes of operation are selectable by controlling the clear and enable inputs as enumerated in the function table. In the addressable-latch mode, data at the
data-in terminal is written into the addressed latch. The addressed latch will follow the data input with all unaddressed
latches remaining in their previous states. In the memory
mode, all latches remain in their previous states and are
unaffected by the data or address inputs. To eliminate the
possiblity of entering erroneous data in the latches, the enable should be held high (inactive) while the address lines
are changing. In ·the 1-of-8 decoding or demultiplexing
mode, the addressed output will follow the level of the D
input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and data
inputs.

Features

~

• Enable/Disablelnput Simplifies Expansion
• Direct Replacement for Fairchild 9334

~

• Expandable for N-Bit Applications
• Four Distinct Functional Modes
• Typical Propagation Delay Times:
Enable-to-Output 18 ns
Data-to-Output 16 ns
Address-to-Output 21 ns
Clear-to-Output 17 ns
• Fan-Out
IOL (Sink Current)
54LS259 4 rnA
74LS259 8 rnA
IOH (Source Current) -0.4 rnA
• Typical ICC 22 rnA

Absolute Maximum Ratings (Note 1)
Supply Voltage

7V

Input Voltage
Storage Temperature Range

7V
-6S·Cto 1S0·C

• Active High Decoder

Nale 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
nol be operatad al these limits. The parametric values defined In Ihe
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Con9Itlon5" table will
define the conditions tor actual device operation.

Connection Diagram

Function Table

• 8-Bit Parallel-Out Storage Register Performs Serial-toParallel Conversion With Storage
'
• Asynchronous Parallel Clear

Inputs

Dual·ln·Llne Package
E

Clear

l

16

15

07

D

I"

13

as

06

12

11

Q4

10

Output Of
Addressed
Latch

Each
Other
Output

Function

OiO·
OiO
L
L

Addressable Latch
Memory
8-Line Demultiplexer
Clear

Clear

E

H
H

L

D

H

L
L

H

°iO
D
L

9

L

Latch Selection Table

l-

r--

Select Inputs

i

.

1
A

2

3
C

B

"
ao

5
01

6
02

7
Q3

Is

,

B

A

L
L
L
L

L
L

H

H
H

H

L
L

H

H
H

L
H

H
H
H
H

GND
TLfF/6418-1

S4LS259 (J)

C

74LS259(N)

H ;;:s: high level. L

==

Latch
Addressed

L
L
L

0
1
2
3
4
5

6
7

== low level

the lavel 01 the data input
P
0iO '5$!! the level of OJ ,(i - 0, 1•... 7. as appropriate) before the indicated
steady-state input conditions were established.

4-289

Recommended Operating Conditions
DM54LS259
Symbol

Parameter

Vee

Supply Voltage

V IH

High Level Input
Voltage

V IL

Low Level Input
Voltage

IOH

High Level Output
Current

IOL

Low Level 0u.tput
Current

tw

Pulse Width

tsu

tH

TA

Setup Time
(Notes 1, 2 and 3)
Hold Time
(Notes 1 and 2)

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2
0.8

-0.4

-0.4
8

15

15

Clear

15

15

Data

151

151

Select

151

151

Data

01

01

Select

01

01

-55

125

70

0

DM54

2.5

3.4

DM74

2.7

3.4

Input Clamp Voltage

Vee=Min, 11= -18 mA

High Level Output
Voltage

Vee=Min
IOH=Max
V IL = Max
V IH = Min

Low Level Output
Voltage

Vcc=Min
IOL= Max
VIL=Max
VIH=Min
IOL'=4 mA
Vee = Min

mA
mA

ns

Typ
(Note 4)

VI

V

ns

Min

Conditions

V

ns

over recommended operating free air temperature (unless

VOH

VOL

0.7

Enable

Units

V

4

Free Air Operating
Temperature

Parameter

Nom

2

Electrical Characteristics
Symbol

DM74LS259

Min

otherwi~e
Max
-1.5

'C

noted)
Units
V
V

DM54

0.25

0.4

DM74

0.35

0.5

DM74

0.25

0.4

V

II

Input Current@Max
Input Voltage

Vee = Max, VI=7V

0.1

mA

IIH

High Level Input
Current

Vee = Max, VI = 2.7V

20

/LA

IlL

Low Level I.nput
Current

V ce = Max, VI = 0.4V

-0.4

mA

los

Short Circuit
Output Current

Vee = Max
(Note 5)

mA

Supply Current

Vee = Max (Note 6)

Icc

DM54

-20

-100

DM74

-20

-100
22

36

mA

Notl 1: The symbols (.. I) Indicate the edge of the clock pulse used for reference: t for rising edge, I for failing edge.
.
Nol. 2: Setup and hold times are with reference to the enable Input.
Notl3: The select·to-enable setup time Is the time before the Hlgh·to·Low enable transition that the select must be stable so that the correct latch Is

selected and the others not allected.
Nol.4: All typlcals are at Yee=SV, TA=2S'e.
Noll 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Not.6: ICC Is measurad with all Inputs at 4.5Y, and all outputs open.
4·290

~------------------------------------------------------------------~c

Switching Characteristics
Parameter

From
(Input)
To
(Output)

at Vee = 5V and T A= 25"C (See Section 1 for Test Waveforms and Output Load)

Min

CL=50 pF

Typ

Max
35

Min.

~

~

RL=2 kn
CL=15 pF

s:

Units

Typ

Max

25

38

N

-s:
~

C

tpLH Propagation Delay
Time Low to High
Level Output

Enable
to
Output

22

ns

tpHL Propagation Delay
Time High to Low
Level Output

Enable
to
Output

15

24

21

32

ns

tpLH Propagation Delay
Time Low to High
Level Output

Data
to
Output

20

32

23

35

ns

tpHL Propagation Delay
Time High to Low
Level Output

Data
to
Output

13

21

20

30

ns

tpLH Propagation Delay
Time Low to High
Level Output

Select
to
Output

24

38

27

41

ns

tpHL Propagation Delay
Time High to Low
Level Output

Select
to
Output

18

29

25

38

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
Output

17

27

24

36

ns

~

r-

4-291

~
~

CD

~ ~National

t! ~ Semiconductor
c
CD
~ DM54LS266/DM74LS266 Quad 2-lnput Exclusive-NOR
~ Gates with Open-Collector Outputs

:E

~

:E
c General Description

Absolute Maximum Ratings

• This device contains four independent gates each of
which performs the logic exclusive-NOR function_ The
open-collector outputs require external pull-up resistors
for proper logical operation_

7V
7V
7V

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

Pull·Up Resistor Equations

(Note 1)

-65'Ct0150'C

Note 1: The "Absolute Maximum 'Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table 'are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Where:

N1 (IOH) = total maximum output high current
for all outputs tied to pull-up resistor
N2 (lIH) total maximum input high current for
all inputs tied to pull-up resistor
N3 (lid = total maximum input low current for
all inputs tied to pull-up resistor

=

Function Table

Connection Diagram
Dual-In-Line Package
Vee

B4

A4

Y4

Y3

A3

Y=AfIlB=AB+AB

8

Inputs

A1

B1

Y1

Y2

A2

B2

Y

L
L
H
H

L
H
L
H

H
L
L
H

=
=

GND

TLlFf6419·1

54LS266 (J)

B

H High Logic Level
L Low Logic Level

7

74LS266(N)

4-292'

Output

A

Recommended Operating Conditions
Symbol

Parameter

DM54LS266

DM74LS266

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level input
Voltage

0.7

0.8

V

VOH

High Level Output
Voltage

5.5

5.5

V

IOL

Low Level Output
Current

4

8

mA

TA

Free Air Operating
Temperature

70

·C

Electric~1
Symbol

Characteristics
Parameter

2

V

2

-55

125

V

a

over recommended operating free air temperature (unless otherwise noted)
Conditions

Min

VI

Input Clamp Voltage

Vee = Min, 11= -18 mA

leEx

High Level Output
Current

Vee=Min, Vo=5.5V
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee= Min
IOL= Max
VIL = Max
VIH= Min
IOL=4 mA
Vee=Min

Typ
(Note .1)

Max

Units

-1.5

V

100

p.A
V

DM54

0.25

0.4

DM74

0.35

0.5

DM74

0.25

0.4

II

Input Current@Max
Input Voltage

Vee = Max, VI =7V

0.2

rnA

IIH

High Level Input
Current

Vee = Max, VI = 2.7V

40

p.A

IlL

Low Level Input
Current

Vee = Max, VI = 0.4V

-0.6

rnA

Icc

Supply Current

Vee= Max (Note 2)

13

rnA

Note 1:

All typicals are at Vee = 5V, TA = 25'e.

'Note 2: ICC is measured with one Input of each gate at 4.5V, the other inputs grounded, and the outputs open.

4·293

8

~

Switching Characteristics

at

vc~ = SV and TA = 2S·C

(See Section 1 for Test Waveforms and Output Load)
RL.=2 kH

Parameter

Conditions
Min

tpLH Propagation
Delay Time Low
to High Level
Output
tpHL Propagation
Delay Time High
to Low Level
Output
tpLH Propagation
Delay Time Low
to High Level
Output
tpHL Propagation
Delay Time High
to Low Level
Output

Other
Input
Low

Other
Input
High

Units

CL=50 pF

CL=15 pF

Typ

Max

18

Typ

Max

30

21

36

ns

18

30

24

40

ns

18

30

21

36

ns

18

30

24

40

ns

4·294

Min

r------------------------------------------------------------------,c

s:
CTI

~National

.j:lo.

~ Semiconductor

r-

en
I'll
~

-s:
CD

C

DM54LS279/DM74LS279 Quad S·R Latches

~

r-

General Description

Absolute Maximum Ratings

This device consists of four individual and independent
Set-Reset Latches with active low inputs_ Two of the four
latches have an additional 5 input ANCed with the primary
5 input. A low on any 5 input while the Rinput is high will
be stored in the latch and appear on the corresponding Q
output as a high. A low on the R input while the 5 input is
high will clear the Q output to a low. Simultaneous transition of the Rand 5 inputs from low to high will cause the Q
output to be indeterminate. Both inputs are voltage level
triggered and are not affected by transition time of the input data.

Supply Voltage
Input Voltage
Storage Temperature Range

Connection Diagram

Function Table

en
I'll

(Note 1)

~

7V
7V
- 65·C to

1!lo·c

Nota 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual-In-Line Package
vee

48

4R

40

382

381

3R

30

Inputs

Output

5(1)

R

Q

L
L
H
H

L
H
L
H

H*
H
L

00

H = high level
L::: low level

lR

181

182

10

2R

28

20

GND

TLlF/6420·1

54LS279 (J)

74LS279 (N)

00:;; the level of

a before the indicated input conditions were established.

-This output level Is pseudo stable; that is, it may not persist when the
Sand RInputs return to their Inactive (high) level.

Not.l: For latches with double S inputs:
H = both S inputs high
L= one or both S inputs low

4-295

Recommended Operating Conditions
Symbol

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

Electrical Characteristics
Symbol

Paran:Jeter

DM54LS279
Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

-55

V

0.8

-0.4

-0.4

0

V
mA

8

mA

70

'c

over recommended operating free air temperature (unless otherwise noted)
Min

Typ
(Note 1)

DM54

2.5

3.5

DM74

2.7

3.5

Conditions

Input Clamp Voltage

Vee = Min, 11= -18 mA

VOH

High Level Output
Voltage

Vee=Min
IOH= Max
VIL=Max
VIH=Min

Low Level Output
Voltage

Vee = Min
IOL= Max
VIL=Max
VIH=Min

,

0.7

125

Units

V

4

VI

V,oL

DM74LS279

Min

IOL=4mA
Vee=Min

Max
-1.5

Units
.V
V

DM54

0.25

0.4

DM74

0.35

0.5

DM74

0.25

0.4

V

II

Input Current@Max
Input Voltage

Vee = Max, VI = 7V

0.1

mA

IIH

High Level Input
Current

Vee = Max, VI = 2.7V

20

p.A

IlL

Low Level Input
Current

Vee=Max, VI=0.4V

-0.4

mA

los

Short Circuit
Output Current

Vee = Max
(Note 2)

mA

Supply Current

Vee = Max (Note 3)

Icc

DM54

-20

-100

DM74

-20

-100

Not. 1: All typicals are at Vee = 5V, TA = 2S'e.
Note 2: ·Not more than one output should be shorted at a time, and the duration should not exceed one second.
Not. 3: ICC Is measured with all R inputs grounded, all S inputs at 4.SV, and all outputs open.

4·296

3.8

7

mA

Switching Characteristics
Parameter

From
(Input)
To
(Output)

at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
Ri.=2 kO
CL=15pF
Min

S

tpLH Propagation Delay
Time Low to High
Level Output

to

tpHL Propagation Delay
Time High to Low
Level Output

to

tpHL Propagation Delay
Time High to Low
Level Output

to

CL=50 pF

Typ

Max

12

Min

Units

Typ

Max

22

15

25

ns

9

15

15

23

ns

15

27

21

33

ns

Q

S
Q

R
Q

,

4·297

~ ~National

t! ~ Semiconductor
c

:!

- DM54LS283/DM74LS283 4-Bit Binary Adders with Fast Carry
C ')

~

....I

~

~ General Description
These full adders perform the addition of two 4-bit binary
numbers. The sum (:Z;) outputs are provided for each bit and
the resultant carry (C4) is obtained from the fourth bit.
These adders feature full internal look ahead across all four
bits. This provides the system designer with partial lookahead performance at the economy and reduced package
count of a ripple-carry implementation.
.

•

Typical add times
Two B-blt words 25 ns
Two 16-bit words 45 ns
Typical power dissipation per 4-blt adder 95 mW

The adder logic. including the carry. is implemented in its
true form meaning that the end-around carry can be accomplished without the need for logic or level inversion.

Supply Voltage "
Input Voltage
Storage Temperature Range

Features

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

•

Absolute Maximum Ratings (Note 1)

• Full-carry look-ahead across the four bits
• Systems achieve partial look-ahead performance with
the economy of ripple carry

Connection Diagram

Dual-In-Line Package
A3

63

15

2:3

14

A4

13

12

2:4

64
11

C4

10

9

-

2
U

62

3
A2

4
2:1

5
A1

6
61

18

7
CO

GND
TL/F/6421·1

54LS2B3(J)

74LS2B3(N)

4-298 .

7V
7V
- 65'Cto 150'C

Recommended Operating' Conditions
DM54LS283
Symbol

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level
Input Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

DM74LS283

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2
0.7

0.8

-0.4

-0.4

4
125

V
V

2

-55

Units

0

V
mA

8

mA

70

·C

Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol

Parameter

Min

Typ
(Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

VI

Input Clamp Voltage

Vcc= Min, 11= -18 mA

VOH

High Level Output
Voltage

Vcc=Min
10H=Max
VIL=Max
VIH=Min

. Low Level Output
Voltage

Vcc=Min
10L=Max
VIL=Max
VIH=Min

VOL

IOL=4mA
Vcc=Min
Input Current@Max
Input Voltage

Vcc,,;,Max
VI =7V

High Level Input
Current

Max
-1.5

Units
V
V

DM54

0.25

0.4

DM74

0.35

0.5

DM74

0.25

0.4

V

A,B

0.2

CO

0.1

Vcc=Max
VI = 2.7V

A, B

40

CO

20

Low Level Input
Current

Vcc=MaxVI = 0.4V

A, B

-0.8

CO

-0.4

Short Circuit
Output Current

Vcc=Max
(Note 2)

ICCI

Supply Current

Vcc = Max' (Note 3)

19

34

mA

ICC2

Supply Current

Vcc = Max (Note 4)

22

39

mA

II

IIH

IlL

·Ios

)

DM54

-20.

-100

DM74

-20

-100

Not. 1: Aillypicals are at Vcc= 5V, TA=25'C.
Nota 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Nato 3: ICCt Is measured with all outputs open, all B Inputs low and all other Inputs at 4.5V. or all Inputs at 4.5V.

Note 4: ICC2 Is measured with all outputs open and all Inputs grounded.

4-299

mA

p.A

mA

mA

Switching Characteristics
Parameter

at Vcc=5V and TA=25°C (See Section 1 for Test Waveforms and Output Load)

From
(Input)
To
(Output)

RL=2 kll
CL=15 pF
Min

Units

CL=50 pF

Typ

Max

Min

Typ

Max

tpLH Propagation Delay
Time Low to High
Level Output

CO
to
1;1,1;2

16

24

19

28

ns

tpHL Propagation Delay
Time High to Low
Level Output

CO
to
1;1, 1;2

15

24

21

30

ns

tpLH Propagation Delay
Time Low to High
Level Output

CO
to
1;3

16

24

19

28

ns

tpHL Propagation Delay
Time High to Low
Level Output

CO
to
1;3

15

24

21

30

ns

tpLH Propagation Delay
Time Low to High
Level Output

CO
to
1;4

16

24

19

28

' ns

tpHL Propagation Delay
Time High to Low
Level Output

CO
to
1;4

15

24

21

30

ns

tpLH Propagation Delay
Time Low to High
Level Output

Ai or Bi
to
1;i

15

24

19

28

ns

tpHL Propagation Delay
Time High to Low
Level Output

Ai orBi
to
1;i

15

24

21

30

ns

tpLH Propagation Delay
Time Low to High
Level Output

CO
to
C4

11

17

15

24

ns

tpHL Propagation Delay
Time High to Low
Level Output

CO
to
C4

11

17

17

25

ns

tpLH Propagation Delay
Time Low to High
Level Output

AiorBi
to
C4

11

17

15

24

ns

tpHL Propagation Delay
Time High to Low
Level Output

AlorBi
to
C4

12

17

18

26

ns

4-300

c

Logic Diagram

s:
en

LS283

~

~

-s:
(,)

C

>0_ _ _--'(9..;..) C4

~
r

(J)
II.)

B4

co
Co)

Tr::cJo--t:e:lli:±±:tt)-----;

~

~E4

B,

p-------1:~~c=)-----_1·~E1

co

TL/FJ6421·2

Function Table
Output

,

~~
CO= L

Input

CO= H

,

When

When

C2 = L

C2 =H

~ ~ ~ ~ ~ X ~~ ~ ~
A3

L
H
L
H

L
'H
L
H
L
H
L
H
L
H
L
H

B3

L
L

H

H
L
L
H
H

C
L
H

H
L
L
H
H

H = High Level, L
Note

A4

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

l:3

L
L
L
L
L
L
L
L
H
H

L
H

H

H

H
H
H
H
H

L
L
H
H
L

l:4

L
L
L
H
H
H
H
L
H
H
H
L
L
L
L
H

H

L
L
H
H
L
L
H

C4

L
L
L
L
L
L
L

H

L
L
L
H
H
H
H
H

l:3

H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H

l:4

L
H

H

H
H
L
L
L
H

L
L
L
L
H
H
H

C4

L
L
L
L
L
H
H
H

L
H
H
H
H
H
H
H

=Low Level

Input conditions at A 1. B 1, A2. 82. and CO are used to determine outpulal:1 and 1.:2 and the value of the internal carry
C2. The values at C2, A3. B3. A4. and 84 are then used to determine outputs I3. 1.:4. and C4.

4·301

o"r---------------------------------------~-------------------------------,

~
....I

~

:iE

~National

~ Semiconductor

c

~ DM54LS290/DM74LS290 4·Bit Decade Counter
;1)

:iE General Description

c

Features

The DM54LS2901DM74LS290 counters are electrically and
functionally identical to the DM54LS90/DM74LS90. Only
the arrangement of the terminals has been changed fOr
the'LS290.

• GND and VCC on Corner Pins
(Pins 7 and 14 respectively)
• Typical power dissipation 45 mW
• Count frequency 42 MHz

Each of these monolithic counters contains four master·
slave flip·flops and additional gating to provide a divideby-two counter and a three-stage binary counter for which
the count cycle jength is divide-by-five.

Absolute Maximum Ratings (Note 1)

These counters have a gated zero reset and gated set-tonine inputs for use in BCD nine's complement applications.

Supply Voltage
Input Voltage
Storage Temperature Range

To use the maximum count length (decade) of "these
counters, the B input is connected to the OA output. The input count pulses are applied to input A and the outputs are
as described it;l the appropriate function table. A symmetrical divide-by·ten count can be obtained from the
'LS290 counter by connecting the 0 0 output to the A input
and applying the input count to the B input which gives a
divide-by-ten square wave at output 0A.

Note 1: The "Absolute Maximum Ratings" are those values beyond.
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram
Dual-In-Line Package
vcc
114

RO(2)

RO(l)

INPUT
B

INPUT
A

13

12

11

10

aD
8

9

I-

r--

1
R9(1)

3

/2
NC

R9(2)

7V
7V
- 65'Cto 150'C

•
ac

~4LS290(J)

5

as

.

17

16
NC

GND
TlIF/6422·1

74LS290(N)

4-302

Logic Diagram

Function Tables
BCD COUNT SEQUENCE
(See Note A)

R91l)

Output

Count

0
1

2
3
4
5
6
7
B
9

R9(2)

QD

QC

QB

QA

L
L
L
L
L
L
L
L
H
H

L
L
L
L
H
H
H
H
L
L

L
L
H
H
L
L
H
H
L
L

L
H
L
H
L
H
L
H
L
H

(1)
(3)

J
a

J
(10)

CLOCK

INPUT A

K

(11)

L:-:K

h

H = High Logic Level
L= Low Logic Level
X= Either Low or High Logic Level

a

J

1

2
3
4
5
6
7
B

9

(4)

CLOCK

BI-QUINARY (5-2)
(See Note B)

0

(5)

CLOCK

INPUT 8

Note A: Output QA is connected to input B 'or BCD count.

K

h

Output

Count

(0)

QA

QD

QC

QB

L
L
L
L
L
H
H
H
H
H

L
L
L
L
H
L
L
L
L
H

L
L
H
H
L
L
L
H
H
L

L
H
L
H
L
L
H
L
H
L

I

kf:

18)

aD

CLOCK

-K

at--

(12)

ROil)
R0(2)

(13)

TLlF/6422·2

The J and K inputs shown without connection are for
reference only and afe functionally at a high level.

Note B: Output aD is connected to input A for bi-quinary count.

RESET /COUNT TRUTH TABLE
Reset Inputs

Output

RO(l) RO(2) R9(1) R9(2)

H
H
X
X
L
L
X

H
H
X
L
X
X
L

L
X
H
X
L
X
L

X
L
H
L
X
L

X

QD

L
L
H

QC

QB

L
L
L
L
L
L
COUNT
COUNT
COUNT
COUNT

QA

L
L
H

4·303

Recommended Operating Conditions
Symbol
Vee

DM54LS290
Parameter
Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level
Input Voltage

IOH

DM74LS290

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

0.7

0.8

High Level Output
Current

-0.4

-0.4

IOL

Low Level Output
Current

.4

feLK

Clock Freq.
(Note 1)

AtoaA

0

32

BtoaB

0

16

Clock Freq.
(Note 2)

AtoOA

0

BtoaB

0

Pulse Width

A

,5

15

B

30

30

feLK

tw

Reset
tAEL
TA

Reset Release Time
Free Air Operating
Temperature

Electrical Characteristics
Symbol

Parameter

32

MHz

0

16

20

0

20

10

0

10

15

125

ns

ns

0

70

Min

Typ
(Note 3)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

High Level Output
Voltage

Vee=Min
10H= Max
VIL=Max
VIH=.Min

Low Level Output
Voltage

Vee = Min
10L=Max
VIL=Max
VIH=Min

Input Current@Max
lnput Voltage .

Vee = Max
VI=7V

High Level Input
Current

Vcc=Max
VI=2.7V

Low Level Input
Current

Vcc=Max
VI=O.4V

DM54

0.25

0.4

0.35

0.5

DM74

0.25

0.4

Reset

0.1

A

0.2

B

0.4

Reset

20

A

40

Icc

Supply Current

Vcc=Max
. (Note 4)

-0.4

A

-2.4

-20

-100

DM74

-20

-100

4·304

V

V

rnA

p.A

mA

-3.2

DM54

Vec = Max (Note 5)

Units

80

Reset

B
los

·C

V

DM74

B

Short Circuit
Output Current

Max
-1.5

Vee=Min, 11= -18 mA

IOL=4 mA
Vee=Min

.IIL

MHz

over recommended operating free air temperature (unless otherwise noted)

Input Clamp Voltage

IIH

0

25

VI

II

mA
mA

15

VOH

VOL

V

8

25
-55

V
V

2

2

Units

9

15

mA
mA

c

Switching Characteristics
Parameter

f MAX Maximum Clock
Frequency

From
(Input)
To
(Output)

RL~2

CL~15

Min

Typ

A
to
OA

32

42

B

16

CL~50

pF
Max

Min

Typ

20

30

pF

Units
Max
MHz

15

23,

ns

tpHL Propagation Delay
Time High to Low
Level Output

A
to
OA

12

18

20

30

ns

tpLH Propagation Delay
Time Low to High
Level Output

A
to

32

48

40

60

n5

34

50

45

68

n5

10

16

15

23

n5

14

21

23

35

n5

21

32

32

48

ns

23

35

35

53

n5

21

32

32

48

n5

23

35

35

53

ns

ns

00

tpHL Propagation Delay
Time High to Low
Level Output

to
OB

tpLH Propagation Delay
Time Low to High
Level Output

to
Oc

tpHL Propagation Delay
Time High to Low
Level Output

to
Oc

tpLH Propagation Delay
Time Low to High
Level Output

B

B

B

B

B
to

00
B

~

~
o

10

16

to
OB

-s::
00

10

00

N
CD

o

r- .

A
to
OA

tpLH Propagation Delay
Time Low to High
Level Output

r-

OO
C

tpLH Propagation Delay
Time Low to High
Level Output

A
to

~

I

kg

to
OB

tpHL Propagation Delay
Time High to Low
Level Output

s::

at Vcc~5V and TA~25·C (See Section 1 for Test Waveforms and Output Load)

tpHL Propagation Delay
Time High to Low
Level Output

00

tpLH Propagation Delay
Time Low to High
Level Output

SET-9
to
OA.OD

20

30

25

38

tpHL Propagation Delay
Time High to Low
Level Output

SET-9
to
OB.OC

26

40

35

53

n5

tpHL Propagation Delay
Time High to. Low
Level Output

SET-O
to
Any 0

26

40

35

53

n5

to

I

Note 1: CL= 15pF and AL=2 kO,
Note 2: CL= 50 pF and AL= 2 kO.
Note 3: All typicat. are at VCC= 5V. TA= 25"C,
Nota 4: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Nota 5: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V and all other inputs grounded.

4-305

~r------------------------------------------------------------------'

.~
~

:E

.
~ Semiconductor
~National

- DM54LS293/DM74LS293 4·Bit Binary Counters
c

~

~

~

:E General Description
c

Features
• GND and VCC on Corner Pins
(Pins 7 and 14 respectively)

The DM54LS293/DM74LS293 counters are electrically and
functionally identical to the DM54LS93/DM74LS93. Only
the arrangement of the terminals has been changed for
the'LS293.

• Typical power dissipation 45 mW
• Count frequency 42 MHz

Each of these monolithic counters contains four masterslave flip-flops and additional ga.ting to provide a divideby-two counter and a three-stage binary counter for which
the count cycle length is divide-by-eight.

Absolute Maximum Ratings (Note 1)
SupplyVoltage
Input Voltage
Storage Temperature Range

All of these counters have a gate~ zero reset.
To use the maximum count length (four-bit binary) of these
counters, the B input is connected to the Q A output. The input count pulses are applied to input A and the outputs are
.
as described in the appropriate function table.

Dual-In-Llne Package
RO(l)

13

12

INPUT
B

INPUT
A

11

10

9

--

J:

J:

7V
-65'CtoI50'C

Note 1: The "Absolute Maximum Ratings" aTe those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommen.ded Operating Conditions" table will
define the conditions for actual device operation.
.

Connection Diagram

RO(2)

7V

4

Qc
TL/F/6423·1

54LS293 (J)

74LS293(N)

4-306

r----------------------------------------------------------------------.c

3:
~
r

Function Tables
COUNT SEQUENCE
(Saa Nota C)
Output
Count
QD QC QB
0
L
L
L
1
L
L
L
2
L
L
H
3
L
L
H
4
L
H
L
5
L
H
L
6
L
H
H
7
L
H
H
8
H
L
L
9
H
L
L
10
H
L
H
11
H
L
H
12
H
H
L
13
H
H
L
14
H
H
H
15
H
H
H

~
CD
~

RESET /COUNT TRUTH TABLE
Raset Inputs
QA
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

H

RO(1)

RO(2)

QD

H
L
X

H
X
L

L

= High Level,

L

= Low Level.

QC

X

:&:

Don't Care.

Logic Diagram'
LS293
{91
OA

INPUT A ;;{',;;OI_ _ _ _ _ _-ct>CLOCK

o

{51

OB

INPUT B ;;{'.;;'I_ _ _ _f-_-ct> CLOCK

{Ol

Oc

{BI
OD

RO{lI
R0(2)

~(1:21::r:)P-J---~
{131

TLlF/6423·2

Not.: The J and K Inputs shown without connection are for reference only and are functionally at a high level.

4-307

QB

L
L
COUNT
COUNT

Not. C: Output QA is connected to input B.

o

c

3:

Output
QA
L

~

~
Co)

Recommended Operating Conditions
I

Symbol

DM54LS293

Parameter

DM74LS293

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIi.

Low Level
Input Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

fCLK

Clock Freq.
(Note 1)

AtoOA

Clock Freq.
(Note 2)
Pulse Width

A

15

15

B

30

30

fCLK

tw

Reset Release Time

TA

Free Air Operating
Temperature

Symbol

-0.4

-0.4

BtoOs

0

16

AtoOA

0

20

0

20

BtoOs

0

10

0

10

Parameter

15
25

-55

125

ns

ns

0

70

Min

Typ
(Note 3)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions
Vcc=Mln, 11= -18 mA
Vcc=Min
10H=Max
VIL=Max
VIH=Mln

Low Level Output
Voltage

Vcc=Min
10L=Max
VIL=Max
VIH=Min
IOL=4 mA
Vcc=:Mln

Input Current@Max
Input Voltage

Vcc= Max
VI=7V

High Level Input
Current

Vcc=Max
VI = 2.7V

Low Level Input
Current

Vcc=Max
VI=0.4V

Short Circuit
Output Current

Vcc=Max
(Note 4)

·C

Supply Current

Vcc= Max (Note 5)

DM54

0.25

0.4

0.35

0.5

DM74

0.25

0.4

Reset

0.1

A

0.2

B

0.2

Reset

20

A

40

V

V

mA

p.A

40

Reset

-0.4

A

-2.4

mA

-1.6

. DM54

-20

-100

DM74

-20

-100

4-308

Units

V

DM74

B

Icc

Max
-1.5,

B

los

MHz

over recommended operating free air temperature (unless otherwise noted)

High Level Output
Voltage

IlL

MHz

32

0

15

mA
mA

0

25

V

8

16

Input Clamp Voltage

,IIH

0.8

32

VOH

II

0.7

0

VI

VOL

V

4

Electrical Characteristics

V

2

2

Reset
tREL

Units

9

15

mA

mA

Switching Characteristics
From
(Input)
To
(Output)

Parameter

f MAX Maximum Clock
Frequency

at Vcc = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL=2kll
C L =15 pF
Min

Typ

A
to
aA

32

42

B
to
as

16

CL=50 pF
Max

Min

Typ

20

30·

Units
Max
MHz

10

tpLH Propagation Delay
Time Low to High
Level Output

A
to
aA

10

16

15

23

ns

tpHL Propagation Delay
Time High to Low
Level Output

A
to
aA

12

18

20

30

ns

tpLH Propagation Delay
Time Low to High
Level Output

A
to
aD

46

70

58

87

ns

tpHL Propagation Delay
Time High to Low
Level Output

A
to
aD

46

70

62

93

ns

tpLH Propagation Delay
Time Low to High
Level Output

B
to
as

10

16

15

23

ns

tpHL Propagation Delay
Time High to Low
Level Output

B
to
as

14

21

23

35

ns

tpLH Propagation Delay
Time Low to High
Level Output

B
to
·ac

21

32

32

48

ns

tpHL Propagation Delay
Time High to Low
Level Output

B
to
ac

23

35

35

53

ns

B
to
aD

34

51

47

71

ns

tpHL Propagation Delay
Time High to Low
Level Output

B
to
aD

34

51

47

71

ns

tpHL Propagation Delay
Time High to Low
Level Output

SET·O
to
Any a

26

40

35

53

ns

tpLH Propagation Delay
Time Low to High
Level Output

,

,-

Not. 1: CL=15pFandRL=2kO.
Not.2: CL = 50 pF and RL = 2 kO.
Not.3: All typicals are at VCC = 5V, TA = 25'C.

Nola 4: Not more than one output should be shorted at a time, and the duration should not E:lxceed one second.
N~t.

5: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V and all other Inputs grounded.

4-309

~National

~ Semiconductor

DM54LS298/DM74LS298 Quad 2-Multiplexers with Storage
General Description

Absolute Maximum Ratings (Note 1)

These integrated circuits provide essentially the equivalent
functional capabilities of two separate MSI functions
(DM54157/DM74157 or DM54LSI57/DM74LSI57 and
DM541751 DM7 4175 or DM54LS 1751 DM74LS 175) in a sIngle 16-pin package.

Supply Vollage
Input Voltage
.Storage Temperature Range

When the word-select input is low, word I (A I, B I, C I, D I)
is entered into the flip-flops. A high input to word select will
cause the selection of word 2 (A2, B2, C2, D2). The selected word is then clocked to the output terminals on the
negative-going edge of the clock pulse.

7V
7V

-65·Cl0150·C

Nole 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot-be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Features
• Selects one of two 4-bit data sources and stores data
synchronously with system clock
• Applications:
Dual source for operands and constants in arithmetic
processor; can release processor register files for
acquiring new data
Imple.ment separate regi~ters capable of parallel
exchange of contents, yet retain external load
capabilily
Universal type register for implementing various shill
patterns; even has compound lell-right capabilities

Connection Diagram

Function Table

_Oual-In-Line Package
OUTPUTS

aB
/16

15

ac

14

aD

13

12

DATA
WORD INPUT
CLOCK SELECT Cl

11

10

9

Outputs

Inputs
Word
Select

..,..

Ctock

L
H
X
H

= High

I
I
H

QA

QS

Oc

QO

al
bl
Cl
dl
c2
d2
a2
b2
QAO QBO QCO QDO

Level (steady state)

l = Low Level (steady state)

6

18

~B~2~~A~2__~A~I~~B~I___C~2~~D~2___D~I~

GND

2

3

4

5

7

1

DATA INPUTS

TL/F/6424·1

X

= Don't Care (any Input, includrng transitions)

, :: Transition from high 10 low level

a 1 ,a2. etc = The level of steady-state mput al A " A2. etc
QAO. Ceo. etc
The level of 0A. Oe. etc. entered on the most recent ~ transition of the clock input.

=

54LS298 (J) 74LS298 (N)

4-310

Recommended Operating Conditions
Symbol
Vcc

Supply Voltage

V,H

High Level Input
Voltage

V,L

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

DM74LS298

DM54LS298

Parameter

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units
V
V

2
0.7

0.8

-0.4

-0.4

4

8

V
mA
mA

tw

Clock Pulse Width

20

20

ns

tsu

Setup Time

Data

15

15

ns

Word Select .

25

25

tH

TA

Hold Time

Data

5

5

Word Select

0

0

Free Air Operating
Temperature

Electrical Characteristics
Symbol

Parameter

-55

125

ns

70

0

over recommended operating free air temperature (unless otherwise noted)
Conditions

Min

Typ
(Note 1)

Max

V,

Input Clamp Voltage

Vcc= Min, 1, = -18 mA

VOH

High Level Output
Voltage

Vcc=Min
10H=Max
V'L= Max
V,H=Min

DM54

2.5

3.4

DM74

2.7

3.4

Low Level Output
Voltage

Vcc=Min
10L=Max
V,L=Max
V,H=Min

DM54

0.25

0.4

DM74

0.35

0.5

IOL=4 mA
Vcc= Min

DM74

0.25

0.4

VOL

·C

-1.5

Units
V
V

V

I,

Input Current@Max
Input Voltage

Vcc=Max, V , =7V

0.1

mA

I'H

High Level Input
Current

Vcc=Max, V,=2.7V

.20

p.A

I,L

Low Level Input

Vcc=Max, V,=0.4V

los

Short Circuit
Output Current

Vcc= Max
(Note 2)

Supply Current

Vcc = Max (Note 3)

Icc

-0.4

rnA

DM54

-20

-100

rnA

DM74

-20

-100
13

21

rnA

Natet: All typlcals are at VCC=5V, TA=25'C.·
Nate 2: Nat more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: With all outputs open and all Inputs except CLOCK low, ICC is measured after applying a momentary 4.5V, followed by ground, to the CLOCK Input.

4-311

~

Switching Characteristics

at Vee = 5V and TA

=25°C

~

:E

o

I
;1;

:E

o

(See Section 1 for Test Waveforms·and Output Load)

RL=2 kll
Parameter

CL=15 pF

CL=50 pF
Max

27

21

32

ns

32

27

41

ns

Max

tpLH Propagation Delay Time
Low to High Level Output

18

tpHL Propagation Delay Time
High to Low Level Output

2,

Min

Logic Diagram

(15)

OA

CLOCK

(14)

Os

CLOCK

(13)

Oc

CLOCK

01
(12)

OD

CLOCK

CLOCK(II)
TLlFI6424·2

4-312

Units

Typ

Typ

Min

.-----------------------------------------------------------------,0
3:

Typical Applications

U'I

Figure 1 illustrates a BCD shift register that will shift an entire 4-bit BCD digit in one clock pulse.

Another function that can be implemented with the LS298 is
a register that can be designed specifically for supporting
multiplier or division operations. Figure 2 is an example of a
one place Itwo place shift register.
.

When the word select input is high and the registers are
clocked, the contents of register 1 is transferred (shifted)
to register 2, etc: In effect, the BCD digits are shifted one
position. In addition, this application retains a parallel-load
capability which means that new BCD data can be entered
into the entire register with one clock pulse. This arrangement can be modified to perform the shifting of binary data
for any number of bit locations.

When word select is low and the register is clocked, the
outputs of the arithmeticllogic units (ALU's) are shifted
one place. When word select is high and the registers are
clocked, the data is shifted two places.

PARALLEL LOAD,

r-----------~ri_+-r-I----~------------+_~~I------._-------------~~~~T

L

L

WS
Al WS
Al ws
Al
--+_~---I A2
OAr-----~~4-+__4A2
OA~----~~~+_~A2
' - - Bl
- - Bl
- - Bl
B2 LS298 OBr---.....+~4---_4B2 LS298 OB
B2 LS298 Os ~--......~­
' - - Cl REG 2
' - - Cl REG 2
' - - C l REG 1
C2
Ocr--1-++~----_4C2
Oc~""'-+-r~----~C2
OC~""'-r-+-1------IDl
'------101
'------IDl
-------~D2 CLOCK OOHH_++------_402 CLOCK OoH>-t-+-r------~02 CLOCK OoH>--t-r-+--

y

1 ___-++-+-+-____________41-___-++-+-+-_ _ _

CLoCK-------______+-

----l

------..-....-

------..-....-

~

DIGIT 1

DIGIT 2

DIGIT 3
TL/F 16424·3

FIGURE 1

-

- - -- -

,...-

,...- - - - -- -

-

ALU
181

ALU
181
FO

11

Fl

F2

F3

FO

I

T

Fl

F2

f3

I· I

I

LS298

WS --

Al A2 Bl B2 Cl C2 01 02

Al A2 Bl B2 Cl C2 01 D2

CLOCK

CLOCK

OA

I

LS298
Os

WSr[
Oc

II

00

i

OA

CLOCK---e-------i----t---~--_t-----'

I I I I

Os

Oc

00

......

'---_L-_-_-!I::~I~··
::;I::4..,:1_~
-

FIGURE 2

4-313

I I I I

---WORO
SELECT
TL/FI6424·4

-'="
.en
N

co

CO

o
3:
:;;;!

i

~ ~National

~ ~ Semiconductor

:E

-

o DM54LS352/DM74LS352 Dual 4·Line to
C'I

lI)

~
-I
'0#'

lI)

:E
o

1·Line Data Selectors/Multiplexers
General Description

Absolute Maximum Ratings (Note 1)

Each of these data selectors I multiplexers contains inverters and drivers to supply fully complementary, on-chip, binary decoding data selection to the AND-'OR-invert gates.
Separate strobe inputs are provided for each of the two
four-line sections.

Supply Voltage
Input Voltage
Storage Temperature Range

Features
•
•
•
•

Inverting version of DM54/74LS153
Permits multiplexing from N lines to 1 line
Performs parallel-to-serial conversion
Strobe (enable) line provided for cascading (N lines to
n lines)

7V
7V
- 65·Cto 150'C

Note 1: The uAbsolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

• High fan-out, low-impedance, totem-pole outputs
• Typical average propagation delay times
From data 15 ns .
From strobe 19 ns
From select 22 ns
• Typical power dissipation 31 mW

Connection Diagram

Function Table

Dual-in-Line Package

Select
Inputs

B

A

X
L
L
L
L
H
H
H

X
L
L
H
H
L
L

H
DATA INPUTS

54LS352 (J, N)

H
H

Data Inputs

Strobe

Output

CO C1 C2 C3

G

y

H
L
L
L
L
L

H
H
L
H
L
H

L

L
H
L

X
L
H
X
X
X
X
X
X

X
X
X
L
H
X
X
X
X

X
X
X
X
X
L
H
X
X

X
X

X
X
X
X
X
L
H

L
L

Select Inputs A and B are common to both sectIons.
TL/F/6425-1

H

74LS352 (J, N)

4-314

= High level. L = Low Level, X = Don't Care

,

Recommended Operating Conditions
DMS4LS352
Symbol

Parameter

Vee

Supply Voltage

V,H

High Level Input
Voltage

V,l

Low Level Input
Voltage

IOH

High Level Output
Current

IOl

Low Level Output
Current

TA

Free Air Operating
Temperature

DM74LS352

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units
V
V

2
0.7

0.8

-0.4

-0.4

4
-55

125

0

V
mA

8

mA

70

·C

-

Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol

Parameter

Min

Typ
(Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

V,

Input Clamp Voltage

Vee = Min, ,,= -18 mA

VOH

High Level Output
Voltage

Vee = Min
IOH=Max
V,l=Max
V'H= Min

\

Val

Low Level Output
Voltage

Vee = Min
IOl=Max
V,l=Max
V,H=Mln
IOl=4mA
Vee=Mln

Max
-1.5

Units
V
V

DM54

0.25

O.~

DM74

0.35

0.5

DM74

0.25

0.4

V

I,

Input Current@Max
Input Voltage

Vee=Max, V,=7V

0.1

mAo

I'H

High Level Input
Current

Vee = Max, V,=2.7V

20

p.A

.I'l

Low Level Input
Current

Vee = Max, V, = 0.4V

-0.4

mA

los

Short Circuit
Output Current

Vee=Max
(Note 2)

rnA

Supply Current

Vee = Max (Note 3)

Icc

DM54

-.20

-100

DM74

-20

-100

Nol.1: All typical. are at Vee=5V, TA=25'e.
Nole 2: Not more than one output should be shorted. at a time, and the duration should not exceed one second.

Not.3: ICC I. measured wllh all output. open and all other Input. at ground.

4-315

6.2

10

rnA

Switching Characteristics

at Vcc = 5V and -rA = 25"C (See Section 1 for Test Waveforms and Output Load)

From
(Input)
To
(Output)

Parameter

RL = 2 kll
C L =15 pF
Min

CL=50 pF

Typ

Max

Min

Units

Typ

Max

tpLH Propagation Delay
Time Low to High
Level Output

Data
to
y

13

20

;16

24

ns

tpHL Propagation Delay
- Time High to Low
Level Output

Data
to

17

26

23

35

ns

19

29

.22

33

ns

Y

tpLH Propagation Delay
Time Low to High
Level Output

Select
to

tpHL Propagation Delay
Time High to Low
Level Output

Select
to
y

25

38

31

47

ns

tpLH Propagation Delay
Time Low to High
Level Output

Strobe
to
y

16

24

19

-29

ns

tpHL Propagation Delay
Time High to Low
Level Output

Strobe
to
y

21

32

27

41

ns

Y

..

Logic Diagram
STROBE Gl (1)
lCO (6)

~~.

1C1 (5)
DATA 1

.

lC2(4)

7)

OUTPUT
Yl

1---1

lC3 (3)

SELECT{B

~

.~

A(~

2CO

(10)

!r~

2Cl(11)
DATA 2
2C2

(12)

2C3 (13)
(15)
STROBE G2

Y2

. '----I

TL/F/6425·2

4·316

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DM54LS353/ DM74LS353 TRI-STATE®
Data Selectors/Multiplexers

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U1
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General Description
Each of these Schottky-clamped data selectors!
multiplexers contains inverters and drivers to supply full
complementary, on-chip, binary decoding data selection to
the AND-OR gates. Separate output control inputs are provided for each of the two four-line sections.
The TRI-STATE outputs can interface directly with data
lines of bus-organized systems. With all but one of the common outputs disabled (at a high impedance state), the low
impedance of the single enabied output will drive the bus
line to a high or low logic level.

• Strobe! output control
• High fan-out totem-pole outputs
• Typical propagation delay
Data to output 12 ns
Select to output 21 ns
• Typical power dissipation 35 mW

Absolute Maximum Ratings (Note 1)
Supply Voltage

7V

Input Voltage
Storage Temperature Range

Features

7V
-65·Cto150·C

• Inverting version of DM54/74LS253
• Schottky-diode clamped transistors
• Permits multiplexing from N lines to 1 line
• Performs parallel-to-serial conversion

Nots 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operateJ at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual-In-Line Package

Select
Inputs

B

A

X
L
L
L
L
H
H
H
H

X
L
L
H
H
L
L
H
H

Data Inputs

Output
Control

CO C1 C2 C3

G

Y

H
L
L
L
L
L
L
L
L

Z
H
L
H
L
H
L
H
L

X
L
H
X
X
X
X
X
X

X
X
X
L
H
X
X
X
X

X
X
X
X
X
L
H
X
X

X
X
X
X
X
X
X
L
H

Output

Address Inputs A and B are common to both sections.

OUTPUT
B
CONTROL SELECT
G1

lC3

lC2

lCl

DATA INPUTS

54LS353 (J, N)

lCO

H = High Level, L
Impedance

OUTPUT GND
VI
TUF/6426-1.

74LS353 (J, N)

.4-317

= Low Level. X = Don't Care. Z = High

-

Recommended Operating Conditions
Symbol

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

Electrical Characteristics
Symbol

Parameter

DM54LS353

DM74LS353

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

V

0.7

0.8

-1
12
-55

125

0

over recommended operating free air temperature

mA

24

mA

70

·C

(u~less otherwise noted)

Min

Typ
(Note 1)

DM54

2.4

3.4

DM74

2.4

3.1

Conditions

V

-2.6

Max

VI

Input Clamp Voltage

Vee=Min, 11= -18 mA

High Level Output
Voltage

Vec=Min
IOH = Max
VIL=Max
VIH=Min

Low Level Output
Voltage

Vee=Min
IOL=Max
VIL= Max
VIH=Min

DM54

0.4

DM74

0.5

10L= 12 mA
Vee = Min

DM74

0.4

'11

V

2

VOH

VOL

Units

Units

V

-1.5

V

,
V

Input Current@Max
Input Voltage

Vee = Max, VI = 7V

0.1

mA

IIH

High Level Input
Current

Vee = Max, VI = 2.7V

20

/LA

IlL

Low Level Input
Current

Vee = Max, VI = 0.4V

-0.4

mA

10ZH

Off·State Output
Current with High
Level Output
Voltage Applied

Vce = Max, Vo = 2.7V
VIH = Min, VIL = Max

20

/LA

IOZL

Off·State Output
Current with Low
Level Output
Voltage Applied

Vee = Max, Vo=0.4V
VIH = Min, VIL = Max'

-20

/LA

los

Short Circuit
Output Current

Vec= Max
(Note 2)

mA

lee!

Supply Current

Vee = Max (Note 3)

7

12

mA

lee2

Supply Current

Vee = Max (Note 4)

8.5

14

mA

Not.t:
Note 2:
Nota 3:
Not. 4:

DM54

-20

-100

DM74

-20

-100

All typlcals are at Vec=5V, TA=25'C.
Not more than one output should be shorted at a time, and the duration should not exceed one second.
leCt Is measured with all outputs open, and all the Inputs grounded.
ICC2 Is measured with the outputs open, OUTPUT CONTROL at 4.5V and all other Inputs grounded.
4·318

,----------------------------------------------------------------------,0
Switching Characteristics
Parameter

at Vcc = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)

From
(Input)
To
(Output)

Min

~

OO

CL=150 pF
Min

en

r-

RL =667n
C L =45pF

3:

Units

Typ

Max

tpLH Propagation Delay
Time Low to High
Level Output

Data
to
Y

17

25

Typ

Max

23

35

tpHL Propagation Delay
Time High to Low
Level Output

Data
to
Y

13

tpLH Propagation Delay
Time Low to High
Level Output

Select
to
Y

30

45

36

54

ns

tpHL Propagation Deiay
Time High to Low
Level Output

Select
to
Y

21

32

29

44

ns

tPZH Output Enable
Time to High
Level Output

Output
Control
toY

15

23

25

38 -

ns

t PZL Output Enable
Time to Low
Level Output

Output
Control
toY

15

23

23

35

ns

tpHZ Output Disable
Time from High
Level Output (Note 1)

Output
Control
toY

27

41

ns

tpLZ Output Disable
Time from Low
Level Output (Note 1)

Output
Control
toY

18

27

ns

ns

Co)

en
Co)

o
3:

:ii.!

r-

OO

20

20

30

ns

~

Co)

Note 1: CL = 5 pF.

Logic Diagram

4-319

i

~National

~
~ Semiconductor
~
:::&

c

i

DM54LS365A1DM74LS365A Hex TRI·STATE® Buffers

~ General Description

Absolute Maximum Ratings

:;
:::&

c

(Note 1)

This device contains six Independent gates each of
which performs a non-inverting buffer function. The outputs have the TRI-STATE feature. When enabled, the
outputs exhibit the low impedance characteristics of a
standard LS output with additional drive capability to
permit the driving of bus lines without external
resistors. When disabled, both the output transistors
are turned off presenting a high-impedance state to the
bus line. Thus the output will act neither as a significant
load nor as a driver. To minimize the possibility that two
outputs will attempt· to take a common bus to opposite
logic levels, the disable time is shorter than the enable
time of the outputs.

Note 1: The "Absolute Maximum Ratings" are those valUJ's beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Supply Voltage
Input Voltage
Storage Temperature Range

7V
7V

- 65·C to 150·C

Dual-In-Line Package

Y=A
. Output

Input
G1

G2

A

Y

H
X

X
H
L
L

X
X
H
L

Hi-Z
Hi-Z
H
L

L
L

AI

VI

A2

V,

A3

V3

H = High Logic Level
L = Low Logic Level
X = Either Low or High Logic 'Level

GNU

Hi-Z

TLlF/6427-1

DM54LS365A (J)

DM74LS365A (N)

4-320

=TRI·STATE (Outputs are disabled)

, -.

.----------------------------------------------------------------------.0
s::
Recommended Operating Conditions
~

Sym

Parameter

DM54LS365A

DM74LS365A

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units
V

Vcc

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level Input
Voltage

0.7

IOH

High Level Output
Current

-1

-2.6

mA

10l

Low Level Output
Current

12

24

rnA

TA

F;ree Air Operating
Temperature

70

·C

2

V

2

-55

125

0.8

0

V

Electrical Characteristics ·over recommended operating free air temperature (unless otherwise noted)
Sym

Parameter

Conditions

Min

Typ
(Note 1)

2.4

3.4

Max

VI

Input Clamp Voltage

Vcc= Min,ll = -18 rnA

VOH

High Level Output
Voltage

Vcc=Min,loH=Max
Vil = Max, VIH = Min

-1.5

VOL

Low Level Output
Voltage

Vcc=Min
iOl=Max
Vll=Max
VIH=Min

DM54

0.25

0.4

D~74

0.35

0.5

IOl=12 mA
Vcc=Min

DM74

0.25

0.4

Units
V
V
V

i

II

Input Current@Max
Input Voltage

Vee = Max, VI= 7V

0.1

rnA

IIH

High Level Input
Current

Vec=Max, VI = 2.7V

20

p.A

III

Low Level Input
Current

Vce=Max
VI=0.5V
(Note 4)

A Input

-20

p.A

Vcc=Max
VI =0.4V
(Note 5)

A Input

-0.4

mA

Vee = Max
VI = 0.4V

G Input

-0.4

p.A

IOZH

Off·State Output
Current with High
Level Output
Voltage Applied

Vee= Max, Vo=2.4V
VIH = Min, Vil = Max

20

lozl

Off·State Output
Current with Low
Level Output
Voltage Applied

Vcc=Max, Vo=0.4V
VIH = Min, Vil = Max

-20

p.A·

105

Short Circuit
Output Current

Vce=Max
(Note 2)

rnA

Supply Current

Vec = Max (Note 3)

Icc

DM54

-20

-100

DM74

-20

-100
14

24

rnA

~

Co)

-s::~o
~

i

~

Switching Characteristics

at Vcc = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL = 667!l
Units

Typ

Max

16

15

25

ns

10

16

16

25

ns

tpZH Output Enable Time
to High Level Output

16

30

25

40

ns

tPZL Output Enable Time
to Low Level Output

14

30

25

40

ns

tpHZ Output Disable Time
from High Level Output
(Note 6)

10

20

ns

tpLZ Output Disable Time
from Low Level Output
(Note 6)

. 11

20

ns

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

10

tpHL Propagation Delay Time
High to Low Level Output

Min

.

CL= 150 pF

CL=50 pF

Parameter

Min

.

Noto 1: All typicals are at VCC = SV, TA = 2S'C.

Note 2: Not more than one output should be shorted at a tim~. and the duration should not exceed one second.

Note 3: ICC is measured with the DATA inputs grounded and the OUTPUT CONTROLS at4.SV.
Note 4: 'Both G inputs are at 2V.
Noto 5: Both G inputs at OAV.
Note6: CL=5 pF.

,

I

4·322

r-----------------------------------------------------------------~c

::
en .

wNational
Semiconductor

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~

-::~
c

DM54LS366A1DM74LS366A Hex TRI-STATE®

Inverting Buffers

~

~
~

General Description

Absolute Maximum Ratings

This device contains six independent gates each of
which performs an Inverting buffer function. The out·
puts have the TRI·STATE feature. When enabled, the
outputs exhibit the low impedance characteristics of a
standard LS output with additional drive capability to
permit the driving of bus lines without external
resistors. When disabled, both the output transistors
are turned off presenting a high·impedance state to the
bus line. Thus the output will act neither as a significant
load nor as a driver. To minimize the possibility that two
outputs will attempt to take a common bus to opposite
logic levels, the disable time Is shortt;jr than the enable
time of the outputs.

Supply Voltage
Input Voltage
Storage Temperature Range

Connection Diagram

7V
7V
-65·Cto150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

not be operated at these limits. The parametric values defined in the
,"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the cunditlons for actual device operation.

Function Table

Dual-In-Line Package
vec G2

A6

Y6

AS

.Y5

A4

Y4

Output

Input
G1

G2

A

Y

H

X

X

H
L
L

X
X

Hi-Z
Hi-Z
H
L

L
·L
G1

A1

Y1

A2

Y2

A3

Y3

L

H

H = High Logic Level
L Low Logic Level
X = Either Low or High Logic Level
HI·Z TRI'STATE (O~tputs are disabled)

=

GND

TL/F/6428-1

DMS4LS366A (J)

(Note 1)

=

DM74LS366A (N)

4-323

~

Recommended Operating Conditions
Sym

DM54LS366A

Parameter

Min

DM74LS366A

Nom

Max

Min

Nom

Max

5

5.5

4.75

5

5.25

Units

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

0.7

0.8

IOH

High Level Output
Current

-1

-2.6

mA

IOL

Low Level Output
Current

12

24

mA

TA

Free Air Operating
Temperature

70

'C

4.5

Parameter

0

2

-55

Electrical Characteristics
Sym

0

2

125

Conditions

Input Clamp Voltage

Vee= Min, 11= -18 mA

VOH

High Level Output
Voltage.

Vee = Min, IOH = Max
VIL = Max, VIH = Min

VOL

Low LeverOutput
Voltage

Vee=Min
10L= Max
VIL = Max
VIH= Min
10L= 12 mA
Vee = Min

Input Current@Max
Input Voltage

IIH

High Level Input
Current

IlL

Low Level Input
Current

V

0

V

over recommended operating free air temperature (unless otherwise noted)

VI

II

V

Min

Typ
(Note 1)

2.4

3.4

Max
-1.5

Units'
V
V

DM54

0.25

0.4

DM74

0.35

0.5

DM74

0.25

0.4

V

Vee = Max, VI = 7V

0.1

mA

. Vee = Max, VI = 2.7V

20

ILA

-20

ILA

Vee=Max
VI =0.5V
(Note 4)

A Input

Vee=Max
VI =O.4V
(Note 5)

A Input

Vee=Max
VI =0.4V

G Input

_0.4

mA

-0.4

IOZH

Off·State Output
Current with High
Level Output
Voltage Applied

Vee= Max, Vo= 2.4V
VIH = Min, VIL = Max

20

ItA

IOZL

Off·State Output
Current with Low
Level Output
Voltage Applied

Vee= Max, Vo=0.4V
VIH=Min, VIL=Max

-20

ILA

los

Short Circuit
Output Current

Vee = Max
(Note 2)

mA

Supply Current

Vee = Max (Note 3)

Icc

DM54

-20

-100

DM74

-20

-100
12

4-324

21

mA

SWitching Characteristics at Vcc=5V and TA=25°C

(See Section 1 for Test Waveforms and Output Load)

RL =667!l
Parameter

C L =50 pF
Min

CL=150 pF
Min

,- Typ

Units

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

10

15

15

25

ns

tpHL Propagation Delay Time
High to Low Level Output

10

16

16

25

ns

tPZH Output Enable Time
to High Level Output

11

30

20

35

ns

tPZL Output Enable Time
to Low Level Output

18

30

30

40

ns

tpHz Output Disable Time
from High Level Output
(Note 6)

10

20

ns

tpLZ Output Disable Time
from Low Level Output
(NoteS)

10

20

ns

Note 1: All typ.icals are at VCC = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: ICC is measured with the
Note 4: Both G Inputs are at 2V.
Note 5: Both ~ inputs ilt
Nole

DATA inputs grounded and the OUTPUT CONTROLS at 4.SV.

O.4V.

6: CL = 5 pF.

~.~

4-325

Max

~ ~National

\.,--

~ ~ Semiconductor
~
:::E

c

~~

~
II)

:::E

c

DM54LS367A/DM74LS367A Hex TRI-STATE® Buffers
General Description

Absolute Maximum Ratings

This device contains six Im;lependent gates each of
which performs a non-inverting buffer function. The outputs have the TRI-STATE feature. When enabled, the
outputs exhibit the low Impedance characteristics of a
standard LS output with additional drive capability to
permit the driving of bus lines without external
resistors. When disabled, both the output transistors
are turned off presenting a high-Impedance state to the
bus line. Thus the output will act neither as a significant
load nor as a driver. To minimize the possibility that two
outputs will attempt to take a common bus to opposite
logic levels, the disable time Is shorter than the enable
time of the outputs.

Supply Voltage
Input Voltage
Storage Temperature Range

Connection Diagram

7V
7V

- 65'(; to 150'C

Not. 1: The ""Absolute Maximum Ratings" are those value. beyond
which the safety of the device can not be guarenteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Dual-In-Llne Package
G2

AS

V6

AS

VS"

A4

V4

Y=A
Output

Input

Gl

AI

VI

A2

V2

A3

V3

(Note 1)

A

G

L
H
·.X

L
L
.. H

Y
L
H
HI-Z

H = High logic Level
L = Low Logic Level
X = Either Low or High Logic Level
HI·Z = TRI-STATE (Outputs are disabled)

GND

TL/F/6429·1

DM54LS367A (J) DM74LS367A (N)

4-326

Recommended Operating Conditions
Sym

DM54LS367A

Parameter

DM74LS367A

Min

Nom

Max

Min'

Nom

Max

4.5

5

5.5

4.75·

5

5,25

Units

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

0.7

0.8

IOH

High Level Output
Current

-1

-2.6

mA

IOL

Low Level Output
Current

12

24

mA

TA

Free Air Operating
Temperature

iO

'C

2

-55

Electrical Characteristics
Sym

Parameter

2

125

V
V

0

V

over recommended' operating free air temperature (unless otherwise noted)
Conditions

Min

Typ
(Note 1)

2.4

3.4

Max

V,

Input Clamp Voltage

Vee=Min, 11= -18mA

VOH

High Level Output
Voltage

Vee='Min,loH=Max
VIL = Max, VIH = Min

-1.5

VOL

Low Level Output
Voltage

Vee = Min
10L=Max
VIL=Max
VIH = Min

DM54

0.25

0.4

DM74

0.35

0.5

IOL=12 mA
Vee=Mln

DM74

0.25

0.4

Units
V
V
V

II

Input Current@Max
Input Voltage

Vee = Max, VI=7V

0.1

mA

IIH

High Level Input
Current

Vee = Max, VI=2.7V

20

p.A

IlL

Low Level Input
Current

Vee = Max
VI = 0.5V
(Note 4)

A Input

-'20

p.A

Vee= Max
VI=0.4V
(Note 5)

A Input

Vee = Max
VI=0.4V

Glnput

-0.4

mA

-0.4

10ZH

Off·State Output
Current with High
Level Output
Voltage Applied

Vee= Max, Vo= 2.4V
VIH = Min, VIL = Max

20

p.A

10ZL

Off·State Output
Current with Low
Level Output
Voltage Applied

Vee= Max, Vo=0.4V
VIH = Min, VIL = Max

-20

p.A

Short Circuit
Output Current

Vee = Max
(Note 2)

mA

Supply Current

Vee = Max (Note 3)

los
Icc

,
DM54

-20

-100

DM74

-20

-100

4·327

14

24

mA

Switching Characteristics' at Vcc = 5V and TA = 25"C (See Section 1 for Test Waveforms and Output Load)
RL=6670
CL =5D pF

Parameter
Min

CL=15D pF

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

10

tpHL Propagation Delay Time
High to Low Level Output

Units

Typ

Max

16

15

25

ns

10

16

16

25

ns

tPZH Output Enable Time
to High Level Output

16

30

25

40

ns

tPZL Output Enable Time
to Low Level Output

14

30

25

40

I1S

tpHZ Output Disable Time
from High Level Output
(Note 6)

10

20

ns

tpLZ Output Disable Time
from Low Level Output
(Note 6)

11

20

ns

=

Min

=

Nola 1: All typical. are at vcc SV, TA 2S'C.
Nota 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Nola 3:
Nola 4:
Nola 5:
Nola 6:

ICC is measured with the DATA inputs grounded and the OUTPUT CONTROLS at 4.5V.
Both G Inputs are at 2V.
Both G Inputs at O.4V.
CL =5 pF.

,

,

4·328

r---------------------------------------------------------------'c

:s:
en

.
~ Semiconductor

~National·

.j:o.

r-

en

-~:s:c

DM54LS368A1DM74LS368A Hex TRI-STATE®

Inverting Buffers
General Description

Absolute Maximum Ratings (Note 1)

This device contains six independent gates each of
which performs an inverting buffer function. The outputs have the TRI-STATE feature. When enabled, the
outputs exhibit the low impedance characteristics of a
standard LS output with additional drive capability to
permit the driving of bus lines without external
resistors. When disabled, both the output transistors
are turned off presenting a high-impedance state to the
bus line. Thus the output will act neither as a significant
load nor as a driver. To minimize the possibility that two
outputs will attempt to take a common bus to opposite
logic levels, the disable time is shorter than the enable
time of the outputs.

Supply Voltage
Input Voltage
Storage Temperature Range

Connection Diagram

Dual-In-Line Package
02

AS

Y6

A5

Y5

A4

Y4

01

A1

Y1

A2

Y2

A3

Y3

GND

TLfF /6430-1

DM74LS368A (N)

Function Table
Y=A
Output

Input
A

G

Y

L
H

L
L
H

H
L
Hi-Z

X

Co)

7V
7V

-65·Ct0150·C

Note 1: The "Absolute Maximum Ratings" arB those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the.
"Electrical Characteristics" table arB not guaranteed at the absolute
maximum ratings. The "Aecommended Operating Conditions" table will
define the conditions for actual device operation.

vee

DM54LS366A (J)

:ii!
ren

H = High Logic Level
L = Low Logic Level
X;; Either Low or High Logic Level

Hj·Z = TAI·STATE (Outputs are disabled)

4-329

~

•

Recommended Operating Conditions

en
....I

~
:E

c

Symbol

DM54LS~68A

Parameter

DM74LS368A

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units

Vee

Supply Voltage

VIH

High Level Input
Voltage

~

VIL

Low Level Input
Voltage

0.7

0.8

:E

IOH

High Level Output
Current

-1

-2.6

mA

IOL

Low Level Output
Current

12

24

mA

TA

Free Air Operating
Temperature

70

'C

i

~
II)

c

2

-55

Electrical Characteristics
Symbol

2

125

V

0

V

over reconimended operating free air temperature (unless otherwise noted)
'.

Parameter

V

Conditions

Min

Typ
(Note 1)

2.4

3.4

. Vee = Min, 11= -18 mA

Max

VI

Input Clamp Voltage

VOH

High Level Output
Voltage

Vee=Min,loH=Max
VIL = Max, VIH = Min

-1.5

VOL

Low Level Output
Voltage

Vee=Min
IOL=Max
VIL = Max
VIH=Min

DM54

'0.25

0.4

DM74

0.35

0.5

. IOL= 12 mA
Vee=Min

DM74

0.25

0.4

Units
V
V
V

II

Input Current@Max
Input Voltage

Vee = Max, VI = 7V

0.1

mA

IIH

High Level Input
Current

Vee = Max, VI=2.7V

20

p.A

IlL

Low Level Input
Current

Vee=Max
VI=0.5V
(Note 4)

A Input

-20

p.A

Vee= Max
VI=0.4V
(Note 5)

A Input

-0.4

mA

Vee = Max
VI =0.4V

G Input

-0.4

4-330

Electrical Characteristics (Continued)

over recommended operating free air temperature (unless

otherwise noted)

Symbol.

Parameter

Conditions

Typ
(Note 1)

Min

Max

Units

IOZH

Off·State Output
Current with High
Level Output
Voltage Applied

Vcc = Max, Va = 2.4V
V IH = Min, VIL = Max

20

fJ.A

IOZl

Off·State Output
Current with Low
Level Output
Voltage Applied

Vcc= Max, Vo=0.4V
VIH = Min, Vil = Max

-20

/LA

los

Short Circuit
Output Current

Vcc= Max
(Note 2)

mA

Icc

Supply Current

I
I

DM54

-20

-100

DM74

-20

-100

. Vcc=Max (Note 3)

12

21

mA

I.

Switching Characteristics

at Vcc = 5V and TA = 25°C (See Section 1

f~r Test Waveforms and Output Load)

RL =667!l
Parameter

Cl=50pF

CL=150 pF

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

10

tpHL Propagation Delay Time
High to Low Level Output

Min

Min

Units

Typ

Max

15

15

25

ns

10

18

16

25

ns

tPZH Output Enable Time
to High Level Output

11

30

20

35

ns

tPZl Output Enable Time
to Low Level Output

18

30

30

40

ns

tpHZ Output Disable Time
from High Level Output
(Note 6)

10

20

ns

tpLZ Output Disable Time
from Low Level Output
(Note 6)

10

20

ns

Note 1: All typicals are at VCC=SV. TA=2S'C.
Nota 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Not. 3:
Note 4:
Not. 5:
Nolee:

ICC Is measured with the DATA inputs grounded and the OUTPUT CONTROLS at 4.SV.
Both G Inputs are at 2V.
Both G Inputs at O.4V.
Cl=SpF.

.

4-331

~National

~ Semiconductor
DM54LS373/DM74LS373, DM54LS374/DM74LS374
TRI-STATE® Octal D-Type Transparent Latches and
Edge-Triggered Flip-Flops
General Description

Features

These a-bit registers feature totem-pole TRI-STATE outputs designed specifically for driving highly-capacitive or
relatively low-impedance loads_ The high-impedance state
and increased high-logic-level drive provide these registers with the capability of baing connected direclly to and
driving the bus lines in a bus-organized system without
need for interface or pull-up components. They are particularly attractive for implementing buffer registers, 1/ 0 ports,
bidirectional bus drivers, and working registers.

• Choice of a Latches or a 0-Type Flip-Flops in a Single
Package
• TRI-STATE Bus-Driving Outputs
• Full Parallel-Access for Loading
• Buffered Control Inputs
• Clock/Enable Input Has Hysteresis to Improve
Noise Rejection·
• P-N-P Inputs Reduce D-C Loading on Data Lines

The eight latches of the DM54/74LS373 are transparent
D·type latches meaning that while the enable (G) is high
the Q outputs will follow the data (D) inputs. When the
enable is taken low the output will be latched at the level of
the data that was set up.
.
(Continued next page)

Connection Diagrams

Absolute Maximum Ratings (Note 1)
7V

Supply Voltage
Input Voltage
Storage Temperature Range

7V
-65·Cto 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions tor actusl device operation.

Dual·ln·Line Package

vee

80

80

70

70

60

60

50

50

OUTPUT
CONTROL

10

1D

20

20

30

3D

40

40

ENABLE
G

GNO
TLlFJ6431·1

54LS373 (J)

74LS373 (N)

vee

SO

80

70

70

60

60

50

50

OUTPUT
CONTROL

10

10

20

20

30

3D

4D

40

CLOCK

GND
TLlFf6431·2

74LS374 (N)

54LS374 (J)

4-332

.--------------------------------------------------------------------,0
General Description

s::

(continued)

UI

0l:Io

The eight flip-flops of the DM54/74LS374 are edgetriggered D-type flip-flops. On the positive transition of the
clock, the
outputs will be set to the logic states that
were set up at the D inputs.

outputs in either a normal logic state (high or low logic levels) or a high-impedance 'state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.

~

Schmitt-trigger bullered inputs at the enable I clock lines
simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A
bullered output control input can be used to place the eight

The output control does not allect the internal operation of
the latches or flip-flops. That is. the old data can be retained or new data can be entered even while the outputs
are off.

s::
i:!

a

~

~
C

~
~

~

C

Function Tables

s::

UI

0l:Io

Output
Control

Enable
G

D

Output

Output
Control

L
l
l
H

H
H
l
X

H
l
X
X

H
L
00
Z

l
l
L
H

H=

ren
w

DM54/74LS374

DM54/74LS373

Clock

D

Output

t
t

H
l
X
X

H
L
00
Z

L
X

0l:Io

Logic Diagram
DM54174LS373

DM54174LS374
Positive-Edge-Triggered Flip-Flops

c~~~~~~ ....:,(I:.:.)_ _ _-T

_

Os
CL~AR

~
(6,10)

Oc

~OUTPUT

Oc

'-c >T
Oc
CLEAR

'T
(7,9)

~~
"
..:::f"")-.o>T

(2,141
CLEAR~
INPUT

.....

I-- OUTPUT
.OD

_

OD
CLEAR

.

,
TUF/B433·2

'LS390

Recommended Operating Conditions
Sym

Parameter

DM54LS390
Nom

Max

Min

Nom

Max

5

5.5

4.75

5

5.25

Vcc

Supply Voltage

4.5

VIH

High Level Input
Voltage

'2

Vil

Low Level.
Input Voltage

IOH

High Level Output
Current

IOl

Low Level Output
Current

fClK

Clock Freq.
(Note 1)

fClK

tw

DM74LS390

Min

2

Units
.V
V

I

0.7

0.8

-0.4

-0.4

4

mA
MHz

AtOOA

0

25

0

25

0

20

0

20

Clock Freq.
(Note 2)

AtOOA

0

20

0

20

BtOOB

0

15

0

15

Pulse Width
(Note 1)

A

20

20

B

25

25

Clear High

20

20

Clear Release Time (Note 3)

TA

Free Air Operating
Temperature

-55

125

Note 1: Cl=15pFandRL=2kO.
I
Note 2: CL = 50 pF and RL = 2 kO.
Note 3: The symbol (I) indicates the failing edge olthe clear pulse is ussd for reference.

4-342

0

MHz

ns

ns

251

251

mA

8

BtoOB

tREL

V

70

·C

.--------------------------------------------------------------------,0
Electrical Characteristics
Symbol

Parameter

VI

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

over recommended operating free air temperature (unless otherwis.e noted)
-Min

Conditions

Typ
(Note 1)

Max
-1.5

'Vee = Min, 11= -18 mA
Vee=Mln
IOH= Max
VIL=Max
VIH=Min

DM54

2.5

3.4

DM74

2.7

3.4

Vee=Mln
IOL=Max
VIL=Max
VIH=Min

DM54

0.25

0.4

DM74

0.35

0.5

IOL=4 mA

DM74

0.25

0.4

Units

en

V

e

V

3:

IIH

Input Current@Max
Input Voltage

los

~

Clear

0.1

Vee = Max
VI = 5.5V

A

0.2

B

0.4

High Level Input
Current

Vee = Max
VI = 2.7V

Clear

20

A

40

Low Level Input
Current

Vee = Max
VI = 0.4V

Clear

-0.4

A

-1.6

B

-2.4

Icc

Short Circuit
Output Current

Vec= Max
(Note 2)

Supply Current

Vee = Max (Note 3)

o

r-

Vee= Max
VI =7V

B
IlL

~

en
V

Vee=~-lIn

II

3:
~
r-

mA

flA

80

I

DM54

-20

-100

DM74

-20

-100
15

26

mA

mA
mA

Note 1: All typicals are at Vee=SV, TA=2S'e..
Note 2: Not more than one output should be shorted at a time. and the duration should not exceed one second.

Nola 3: ICC is measured with all outputs open, both CLEAR inputs grounded following momentary connection to 4.5 and all other inputs grounded.

4-343

~

(;)

.

~

Switching Characteristics

~

:::E
c

~

~

Parameter

f MAX Maximum Clock
Frequency

~
:::E
c

From
(Input)
To
(Output)

at Vcc=SV and TA=2S"C '(See Section 1 for Test Waveforms and Output Load)
RL=2 kll
CL=15 pF

CL=50 pF
Min

Typ

35

20

30

30

15

20

Min

Typ

A
to
QA

25

B
to
QB

20

Max

\

Units
Max
MHz

20

16

24

ns

13

20

20

30

ns

A
to
Qc,

37

60

54

81

ns

A

39

60

54

81

ns

B
to
QB

13

21

18

27

ns

. tpHL Propagation Delay
Time High to Low
Level Output

B
to
QB

14

21

22

33

ns

tpLH Propagation Delay
Time Low to High
Level Output

B
to
Qc

24

39

34

51

ns

tpHL Propagation Delay
Time High to Low
Level Output

B
to
Qc

26

39

36

54

ns

tpLH Propagation Delay
Time Low to High
Level Output

B
to
QD

13

21

18

27

ns

tpHL Propagation Delay
Time High to Low
Level Output

B
to
QD

14

21

22

33

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
AnyQ

24

39

30

45

ns

tpLH Propagation Delay
Time Low to High
Level Output

A
to
QA

12

tpHL Propagation Delay
Time High to Low
Level Output

A
to
QA

tpLH Propagation Delay
Time Low to High
Level Output
tpHL Propagation Delay
Time High to Low
Level Output

to
Qc

tpLH Propagation Delay
Time Low to High
Level Output

4-344

r------------------------------------------------------------------,c

3:
en
-'="
r-

~National

~ Semiconductor
DM54LS393/DM74LS393 Dual4-Bit
Decade and Binary Counters

oo
~

Co)

c

3:
~

General Description
Each of these monolithic circuits contains eight masterslave flip-flops and additional gating to implement two individual four-bit counters in a single package. The 'LS393
comprises two independent four-bit binary counters each
having a clear and a clock input. N-bit binary counters can
be implemented with each package providing the capability of divide-by-256. The LS393 has parallel outputs from
each counter stage so that any submultiple of the input
count frequency is available for system-timing signals.

Features

Co)

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
Clear

7V
7V
5.5V
- 65'Cto 150'C

Storage Temperature Range

• 'LS393 Dual 4-Bit Binary Counter with Individual
Clocks
• Direct Clear for Each 4-Bit Counter

fg

• Buffered Outputs Reduce Possibility of Collector
Commutation

A

• Dual Versions of the Popular 'LS93

~

• Typical Maximum Count Frequency 35 MHz

• Dual 4-Bit Versions Can Significantly Improve System
Densities by Reducing Counter Package Count by 50%

Nole 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual devicp. operation.

Connection Diagrams

Function Table

Dual-In-Line Package

OUTPUTS
vcc
114

2A
13

2
CLEAR
12

2aA

2aB

111

110
aB

CLE~R
ya

COUNT SEQUENCE
(EACH COUNTER)

2QC

2ao

19

Is

Oc

aD

A

I

r

\

1-1
1
lA

2

1
CLEAR

CLEAR
aA

!
:
OB

ac

,1: ,1: ,1:

aD

0
1
2
3
4
5
6
7

A

I

8
9
10
11
12
13
14
15

t, J:

lao

OUTPUTS

Output

Count
QD

Qc

QB

QA

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
H
H'
L
L
H
H·
L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

TLfF/6434·1

H= High logic Level
L= Low Log ie Level

54LS393 (J) 74LS393 (N)

4-345

~r-----------------------------------------------------------------------------,

~

Recommended Operating Conditions

~

Sym

.....

::E

c

DM74LS393

DM54LS393

Parameter

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

CO)

Vee

Supply Voltage

~

V IH

High Level Input
Voltage

\ilL

Low Level
Input Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

feLK

Clock Frequency
(Note 1)

0

25

feLK .

Clock Frequency
(Note 2)

0

20

tw

Pulse Width

~
::E

c

2

0

25

MHz

0

20

MHz

20
20

Parameter

VI

Input Clamp Voltage

VOH

High Level Output
Voltage

Icc
Noto 1:
Note 2:
Noto 3:
Noto4:

mA

20

ns

251

251
-55

Electrical Characteristics

los

8

20

Free Air Operating
Temperature

IlL

mA

A

Clear Release Time (Note 3)

IIH

-0.4·

Clear High

tREL

II

V

-0.4

TA

VOL

0.8

4

I

125

ns

0

70

Min

Typ
(Note 4)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

-1.5

Vee=Min, 11= -18 mA
Vee=: Min
10H=Max
VIL=Max
/ VIH = Min

Max

0.25.

0.4

DM74

0.35

0.5·

IOL=4mA
Vee=Min

DM74

0.25

0.4

Vee=Max
VI=7V

Clear

0.1

Vee=Max
VI =5.5V

A

0.2

High Level Input
Current

Vee=Max
VI=2.7V

Clear

20

A

40

Low Level Input
Current

Vee=Max
VI =0.4V

Clear

-0.4

A

-1.6

Short Circuit
Output Current

Vee=Max
(Note 5)

DM54

-20

-100

DM74

-20

-100

Supply Current

Vee = Max (Nole 6)

15

Units
V
V

DM54

Input Current@Max
Input Voltage

·C

over recommended operating free air temperature (unless otherwise noted)

Vee=Min·
10L= Max
VIL=Max
V IH = Min

Low Level Output
Voltage

V
V

0.7

I

Sym

2

Units

26

V

mA

ItA

mA

mA

mA

eL -15 pF and RL =2 kll.
eL = 50 pF and RL = 2 kIt
The symbol (I) Indicates that the failing edge of the clear pulse is used for reference.
All typlcals are at Vee=5V, TA=25'e.

Note 5: Not more than one output should be shorted at a time,

an~

the duration should not exceed one second.

Nata 6: ICC is measured with all outputs open, both CLEAR inputs grounded following momentary connection to 4.5V. and all other inputs grounded.

4·346

Switching Characteristics
Parameter

fMAX Maximum Clock
Frequency

at Vcc = 5V and T A = 25°C (See Section 1 for Test Waveforms and Output Load)

From
(Input)
To
(Output)

Min

Typ

A

25

35

RL=2 kU
CL=15 pF

Units

CL=50 pF
Max

Min

Typ

20

30

Max
MHz

to
QA

A

tpLH Propagation Delay
Time Low to High
Level Output

to
QA

tpHL Propagation Delay
Time High to Low
Level Output

to
QA

tpLH Propagation Delay
Time Low to High
Level Output

to
Qo

tpHL Propagation Delay
Time High to Low
Level Output

to
Qo

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
AnyQ

A

A

A

12

20

16

24

ns

13

20

20

30

ns

40

60

58

87

ns

40

60

58

87

ns

24

39

30

45

ns

Logic Diagram

'LS393

INPUT A

(1,13)

OA

(3, 11) OUTPUT
~QA

T

CLEAR

~

Il~T

OB

(4, 10) OUTPUT

~QB

CLEAR

~

Il~T

Oc

(5, 9) OUTPUT

~Qc

CLEAR

~

Il~T

00 ~ OUTPUT
Qo

CLEAR
CLEAR (2,
INPUT

12)

Y

TLIF/6434-2

.~ ~ National
~ ~ Semiconductor

~ DM54LS465/DM74LS465, DM54LS466/DM74LS466,

!

DM54LS467/DM74LS467, DM54LS468/DM74LS468
~ (DM71 LS95A/DM81 LS95A, DM71 LS96A/DM81 LS96A,
~ DM71 LS97A/DM81 LS97A,DM71 LS98A/DM81 LS98A).
C TRI·STATE® Octal Buffers
...:
~ General Description

....
j:!

:iE

C

......

~

~

:iE
C

g
cn
....
"'Iit'

j:!

These devices provide eight, ·two-input buffers in each
package. All employ the newest low-power-Schottky TIL
technology. One of the two Inputs to each buffer is used as
a control line to gate the output into the high-impedance
state, while the other input passes the data through the
buffer. The LS465 and LS467 present true data at the outputs, while the LS466 and LS468 are inverting. On the
LS465 and LS466 versions, ail eight TRI-STATE enable
lines are common, wth access through a 2-input NOR
gate. On the LS467 and LS468 versions, four buffers are
enabled from one common line, and the other four buffers
are enabled from another common line. In all cases the
outputs are placed in the TRI-STATE condition by applying
a high logic level to the enable pins. These devices represent octal, low power-Schottky versions of the very

popular DM54/74365, 366, 367, and 368 (DM70/8095, 96, 97,
and 98) TRI-STATE hex buffers.

Features
• Octal versions of popular DM54/74365, 366, 367, and
368 (DM70/8095, 96, 97 and 98)
• Typical power dissipation
DM54/74LS465,467 80 mW
DM54/74LS466,468 65 mW
• Typical propagation delay
DM54/74LS465,467 15 ns
DM54/74LS466,468 10 ns
• Low power-Schottky, TRI-STATE technology

:iE1-------------------------------------------------------------C
Dual-In-Llne Packages
CD Connection Diagrams

CD

~
....

vee

02

AS

va

A7

V7

A6

V6

AS

01

Al

VI

A2

V2

A3

V3

A4

V4
GND
TL/F/643 ..1

V5

vee

02

Aa

va

A7

ch

At

Yl

A2

V2

Y7

A6

Y6

AS

A3

V3

A4

Y4
GND
TLlF/643"2

V5

"'lit'

U)

:iE
C

&tf

....~
~

:iE
C

....~
~

54LS465 (J)

74LS465 (N)

54LS467 (J)

74LS467 (N)

54LS466 (J)

74LS466 (N)

54LS468 (J)

74LS468 (N)

:iE

C

TLlF/643 ..4

TLfFf6435-3

4-348

Function Tables

LS466

LS465
INPUTS

G1

G2

A

H
X
L
L

X
H
L
L

X
X
H
L

INPUTS

OUTPUT
Y

Z
Z
H
L

G1

G2

A

OUTPUT
V

H
X
L
L

X
H
L
L

X
X
H
L

Z
Z
L
H

LS467
INPUTS
G

A

H
L
L

X
H
L

LS468
INPUTS

OUTPUT
y

OUTPUT
y

G

A

Z

H

H
L

L
L

X
H

Z
L

L

H

4-349

Recommended Operating Conditions
Symbol

. DM54LS465, 466, 467, 468

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

DM74LS465, 466, 467, 468

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units
V
V

2

2
0.7

0.8

High Level Output
Current

.,.2.6

-5.2

mA

IOL

Low Level Output
Current

12

24

mA

TA

Free Air Operating
Temperature

70

·C

-55

125

0

V

'LS465 and 'LS467 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol

Parameter

Conditions

Min

Typ
(Note 1)

Max
-1.5

VI

Input Clamp Voltage

Vee = Min, 11= - 18 mA

VOH

High Level Output
Voltage

Vee=Min
IOH= Max
VIL=Max
VIH = Min

Low Level Output
Voltage

Vee=Min
10L=Max
VIL=Max
VIH = Min

DM54

0.4

DM74

0.5

IOL=12 mA
Vce= Min

DM74

0.4

VOL

Units

DM54

2.5

DM74

2.7

V
V

V

II

Input Current@Max
Input Voltage

Vee=Max, VI=7V

0.1

IIH

High Level Input
Current

Vee=Max, VI=2.7V

20

IlL

Low Level Input
Current

Vee= Max VI=0.5V A (Note 3)

-20

VI = 0.4V A (Note 4)

-50

·G

-50

10ZH

Off-State Output
Current with High
Level Output
Voltage Applied

Vee=Max, Vo=2.4V
V IH = Min, V IL = Max

20

p.A

10ZL.

Off·State Output
Current with Low
Level Output
Voltage Applied

Vee = Max, Vo'= 0.4V
V IH = Min, VIL = Max

-20

p.A

los

Short Cireuil
Output Current

mA

Icc

Supply Current

.Vee=Max
(Note 2)

DM54

-20

-100

DM74

-20

-100
16

Vee = Max (Note 3)

Note 1: All typicals are at Vee=5V, TA=25·e.
Nota 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Note 3: Both G inputs are at 2V.
Note 4: Both G Inputs at O.4V.
4-350

26.0

mA

I

p.A
p.A

mA

'LS465 and 'LS467 Switching Characteristics

at Vcc = 5V and TA = 25'C

(See Section 1 for Test Waveforms and Output Load)
RL = 66711

CL =150 pF

CL =50 pF

Parameter
Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

10

tpHL Propagation Delay Time
High to Low Level Output

Min

Units

Typ

Max

16

15

25

ns

19

28

25

40

ns

tPZH Output Enable Time
to High Level Output

11

25

20

30

ns

tpZL Output Enable Time
to Low Level Output

20

30

28

42

ns

tpHZ Output Disable Time
from High Level Output
(Note 1)

13

20

ns

tpLZ Output Disable Time
from Low Level Output
(Note 1)

19

27

ns

NOlet: CL=5 pF.

,

4·351

'LS466 and 'LS468 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Sym

Parameter

Typ
(Note 1),

Min

Conditions

Max
-1.5

VI

Input Clamp Voltage

Vcc=Min, 11= -18 mA

VOH

High Level Output
Voltage

Vcc=Min
10H= Max
VIL = Max
VIH = Min

DM54

2.5

DM74

2.7

Low Level Output
Voltage

Vcc=Min
IOL=Max
VIL=Max
VIH=Min

DM54

0.4

DM74

0.5

IOL=12 mA
Vcc=Min

DM74

0.4

VOL

V
V

V

0.1

mA

20

p.A

Vcc=Max VI=0.5V A (Note 3)

-20

p.A

VI=O.4V A (Note 4)

-50

II

Input Current@Max '
Input Voltage

Vcc=Max, VI=7V

IIH

High Level Input
Current

Vcc=Max, VI=2.7V

Low Level Input
Current

IlL

Units

--

-50

G

10ZH

Off-State Output
Current with High
Level Output
Voltage Applied

Vcc=Max, Vo=2.4V
VIH=Min, VIL=Max

'20

p.A

10ZL

Off-State Output
Current with Low
Level Output
Voltage Applied

Vcc=Max, Vo=0.4V
VIH=Min, VIL=Ma>.<

-20

p.A

los

Short Circuit
Output Current

Vcc=Max
(Note 2)

mA

Supply Current

Vcc = Max (Note 3)

Icc

DM54

-20

-100

DM74

-20

-100
13

21

Note 1: All Iypical. are al VCC =SV, TA =2S'C,
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Note 3: Both G inputs are at 2V.
Note 4: Both G Inputs at O.4V.

.

.
I

/

4-352

mA

'LS466 and 'LS468 Switching Characteristics

at Vcc=5V anq TA=25°C

(See Section 1 for Test Waveforms and Output Load)
RL=667!!
Parameter

CL=50 pF

Units

CL=150 pF

Typ

Max

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

6

10

11

16

ns

tpHL Propagation Delay Time
High to Low Level Output

13

17

19

30

ns

tPZH Output Enable Time
to High Level Output

10

15

20

30

ns

tPZL Output Enable Time
to Low Level Output

23

35

30

45

ns

tpHZ Output Disable Time
from High Level Output
(Note 1)

13

20

ns

tpLZ Output Disable Time
from Low Level Output
(Note 1)

18

27

ns

Min

Min

Nola 1: CL = 5 pF.

.

I

4·353

~r------------------------------------------------------------------------.

~ ~ National

~ ~ Semiconductor

:E
Q

in
oo:r

DM54LS645/DM74LS645 Octal Bus Transceivers

CD

en

...I

~
:E

Q

General Description

Absolute Maximum Ratings

These octal bus transceivers are designed for asynchronous two-way communication between data buses.
The devices transmit data from the A bus to the B bus.or
from the B bus to the A bus depending upon the level at
the direction control (DIR) input. The enable input (G)
can be used to disable the device so that the buses are
effectively isolated.

Supply Voltage
Input Voltage
Storage Temperature Range

Features

(Note 1)

7V
7V
- 55'C to 150'C

Note 1: The "Absolute Maximum Ratings" are those values· beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

• Bi·directional bus transceivers in high·density 20·pin
packages
• Hysteresis at bus inputs improves noise margins
• TRI·STATE'" outputs

Connection Diagram

b

ENABLE
~

M

~

~

M

Function Table

~

M

N

M
Control
Inputs

G

DIR

L
L
H

L
H
X

. H: High Level
L= Low Level
X = Irrelevant

DlR

Al

A2

A3

A4

DM54LS645 (J)

A5

A6

A7

AB

GNU

DM74LS645 (N)

4·354

'LS645
B data to A bus
A data to B bus
Isolation

Recommended Operating Conditions'
DM54LS645
Symbol

Parameter

Vce

Supply Voltage
(Note 1)

IOH

High Level Output
Current

10L

Low level Output
Current

TA

Free Air Operating
Temp"erature

DM74LS645-1

Nom

Ma.

Min

Nom

Max

Min

Nom

Ma.

4.~

5

5.5

4.75

5

5.25

4.75

5

5.25

-55

V

-15

-15

rnA

12

24

48

mA

70

·C

70

0

0

over recommended operating free air temperature range (unless otherwise noted)

Conditions
(Note 2)

Parameter

Units

-12

125

Electrical Characteristics
Symbol

DM74LS645

Min

DM54lS645

DM74lS645

Typ
Min

(Note 3)

DM74lS645·1

Typ

Typ
Max

Min

(Note 3)

Ma.

2

2

Min

(Not. 3)

Units
Ma.
V

2

VIH

High Level Input Voltage

Vil

Low level Input Voltage

VIK

Input Clamp Voltage

Vee

Hysteresis (VT +
A or B Input

Vee= Min

0.1

0.4

0.2

0.4

0.2

0.4

V

Vee= Min

2.4

3.4

2.4

3.4

2.4

3.4

V

VOH

- V _)

High Level Output Voltage

= Min, II = 18 rnA

iOH=-3mA
VIH=2V
'OH-Max
VIL =Vll Max

0.5

0.6

0.6

-1.5

-1.5

-1.5

2

2

VOL

Low Level Output Vollage

Vcc=Min
VIH=2V

10ZH

Off·State Output Current.
High Level Voltage Applied

Vee= Max, G at 2V,
VO=2.7V

20

10Zl

Off·State Output Current,
Low level Voltage Applied

VCC- Max, G at 2V,
VO=O.4V

II

Input Current at

VCC=Max

LA or B

I

2
V

20

20

I,A

-400

- 400

-400

I,A

VI= 5.5V

0.1

0.1

0.1

mA

VI=7V

O.t

0.1

0.1

IIH

High Level Input Current

VCC- Max, VIH = 2.7V

20

III

Low Level Input Current

VCC- Ma):, Vll=O.4V

-0.4

lOS

Short Circuit Output Current
(Note 4)

Vec- Max

ICC

Total Supply Current

Out puiS High

-40

= Max, Outputs Open

225

0.25
0.35

0.4
0.5

0.25
0.35
0.4

20.
-0.4
40

-225

40

I,A
mA

- 225

mA
mA

48

70

48

70

48

70

62

90

62

90

62

90

Outputs at Hi·Z

64

95

64

95

64

95

Note 1: Voltage values are with respect to the network ground terminal.
Note 2: For conditions shown as Min or Max, use the appropriate value specified under Recommended Operating Conditions.

Note 3: A)I typical. are at

20

-0,4

Outputs Low

Vee

V

0.4
0.5
0.5

0.25

IOL=12mA
IOl 24 rnA
VIL=VIL Max 10l 48mA

Maximum Input Voltage CIR or G

0.4

V

Vec = 5V, TA ~ 25·C.

Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second.

4·355

SWitching Characteristics

at Vee = 5V and TA = 25°C

From
(Input)
To
(Output)

Parameter

RL = 667n (Note 2)
CL=45 pF
Min

C L =5 pF

Typ

Max

Min

Units

Typ

Max

tpLH Propagation Delay
Time Low to High
Level Output

A
to
B

8

15

ns

tpHL Propagation Delay
Time High to Low
Level Output

A
to
B

11

15

ns

• tpLH Propagation Delay
Time Low to High
Level Output

B
to
A

8

15

ns

tpHL Propagation Delay
Time High to Low
Level Output

B
to
A

11

15

ns

tpZL Output Enable
Time to
Low Level

G, DIR
to
A

31

40

ns

tpZH Output Enable
Time to
High Level

G, DIR
to
A

26

40

ns

tpZL Output Enable
Time to
Low Level

G, DIR
to
B

31

40

ns

'!PZH Output Enable
Time to
High Level

G, DIR
to
B

26

40

ns

tpLZ Output Disable
Time to
Low Level

G, DIR
to
A

15

25

ns

tPHZ Output Disable
Time to
High Level

G, DIR
to
A

15

25

ns

tpLZ Output Disable
Time to
Low Level

G,DIR
to
B

15

25

ns

tpHZ Output Disable
Time to
High Level

G, DIR
to
'B

15

25

ns

r

Typical Characteristics
DM74LS Noninverting
Output Voltage vs Input
Voltage

DM54LS Noninverting
Output Voltage vs Input
Voltage
5

E

4

!:l

3

~

co

....=-

=

!;

2

I
-Ii

,1

5

TA =125°C ••••

TA=25°C TA=-55°C - - -

..... .... ....
ill +:
o

0
0

0
0

~

3

co

...=-~
...=

I

TA=70°C··· •

TA=25°CTA=O°C---

;q -

00

0

Ii

2

co

~

I
-Ii

•

-.I

' 0.5
1
1.5
VI-INPUT VOLTAGE (V)

4

...

0

H!:.

co

E
w

1
0

2

0

4-356

o •

0

o ~
o0 . .

0
0
0

t

: I :

J

-0

1
1.5
0.5
VI-INPUT VOLTAGE (V)

2

~National

.~ Semiconductor

DM54LS670/DM74LS670 TRI-STATE®4-by-4 Register Files
General Description
These register files are organized as 4 words of 4 bits
each, and separate on-chip decoding is provided for addressing the four word locations to either write-in or retrieve data. This permits writing into one location, and
reading from another word location, simultaneously.
Four data inputs are available to supply the word to be
stored. Location of the wordis determined by the write select inputs A and B, in conjunction with a write-enable signal. Data applied at the inputs should be in its true form.
That is, if a high level signal is desired from the output, a
high level is applied at the data input for that particular bit
location. The latch inputs are arranged so that new data will
be accepted only if both internal address gate inputs are
high. When this condition exists, data at the 0 input is
transferred to the latch output. When the write-enable input, GW, is high, the data inputs are inhibited and their levels can cause no change in the information stored in the
internal latches. When the read-enable input, GR, is high,
the data outputs are inhibited and go into the high impedance state.
The individual address lines permit direct acquisition of
data stored in any four of the latches. Four individual decoding gates are used to complete the address for reading
a word. When the read address is made in conjunction
with the read-enable signal, the word appears at the four
outputs.
This arrangement-data entry addressing separate from
data read addressing and individual sense line-eliminates
recovery times, permits simultaneous reading and writing,
and is limited in speed only by the write time (27 ns typical)
and the read time (24 ns typical): The register file has
a n.on-volatile readout in that data is not lost when
addressed.

Connection Diagram

All inputs (except read enable and write enable) are
buffered to lower the drive requiremenNl to one normal Series 54LS /7 4LS load, and input clamping diodes minimize
switching transients to simplify system design. High speed,
double ended AND-OR-INVERT gates are employed for the
read-address function and have high sink current, TRISTATE outputs. Up to 128 of these outputs may be wireAND connected for increasing the capacity up to 512
words. Any number of these registers may be paralleled to
provide n-bit word length.

Features
• For use as:
Scratch pad memory
Buffer storage between processors
Bit storage in fast multiplication designs
• Separate read/write. addressing permits simultaneous
reading and writing
• Organized as 4 words of 4 bits
• Expandable to 512 words of n-bits·
• TRI-STATE versions of DM54LSI70/DM74LS170·
• Fast acces~ times

20 ns typ

Absolute Maximum Ratings (Note 1)
Supply Voltage

7V

Input Voltage
Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual:ln.Line Package
DATA
INPUT
VCC
01

116

15

WRITE SELECT
WA

WB

14

ENABLE
Gw

13

12

OUTPUTS

GR

01

11

02

10

1

9

-

r-

02

2

3

03

04

DATA
INPUTS

7V
-65·CtoI50·C

4

5

READ
SELECT

7

18

03

GND

6

04

OUTPUTS
TLlF/6436·1

54LS670 (J, N)
4-357

74l.:S670 (J, N)

Function Tables
WRITE TABLE (SEE NOTES A. B. AND C)
Write Inputs
WB

WA

GW

L
L

L

H
H

H

L
L
L
L

X

X

H

H
L

READ TABLE (SEE NOTES A AND D)

Word

0

1

Read Inputs
2

3

0=0
00
00
00
0=0
00
00
00
0=0
00
00
00
0=0
00
00
00
00
00
00
00
Note A: H
ance (Olf)

= High

Level, L =

Outputs

RB

RA

GR

01

03

04

L
L

L

H

H
H
X

H
X

L
L
L
L

WOBl
W1Bl
W2Bl
W3Bl

WOB2
W1B2
W2B2
W3B2

WOB3
W1B3
W2B3
W3B3

WOB4
W1B4
W2B4
W3B4

H

Z

Z

Z

Z

L

02

low Level, X = Don't Care, Z = High Imped-

Note 8: (0 = D) = The four selected internaillip-fiop outputs will assume
the states appled to the four external data inputs.
Note C: 00
established.

= The level at a before the

indicated input conditions were

Note 0: WOB 1 = The first bit of word O. etc.

Logic Diagram

OUTPUTS

DATA
INPUTS

(4)
(11) (5)
RS
,GR
RA
, READ INPUT

WRITE INPUT

4·358

TLlF/6436·2

Recommended Operating Conditions
DM74LS670

DM54LS670
Parameter

Symbol
Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level
Input Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

tw

Write Enable
Pulse Width

tsu

Setup Time
(Note 1)

tH

Hold Time
(Note 1)

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

O.S

-1
12

mA

24

mA
ns
ns

10

10

15

15

Data

15

15

WA,We

5

5

25

25

-55

0

TA

-2.6

25

Data

Latch Time for New Data (Note 2)

V

25

I/'fA, We

Free Air Operatjng
Temperature

V
V

2
0.7

tLATCH

Units

125

ns

ns
70

·C

Note 1: Times are with respect to the Write-Enable Input. Write-Select time will protect the data written into the previous address. If protection of data in the

previous address, tSETUP rNA, We) can be ignored. As any address selection sustained for the final 30 nsof the Write· Enable pulse and duringtH rNA, We)
will result in data being written into that location. Depending on the duration of the Input conditions, one or a number of previous addresses may have been
written Into.

Note 2: latCh time Is the time allowed for the internal output of the latch to assume the state of new data. This is important only when attempting to read from
a location immediately after that location has received new data.

Electrical Characteristics
Symbol

Parameter

over recommended operating free air temperature (unless otherwise noted)
Conditions

VI

Input Clamp Voltage

Vcc= Min, II = -18 mA

VOH

High Level Output
Voltage

Vce = Min, IOH = Max
VIL = Max, VIH =: Min

VOL

Low Level Output
Voltage

Vec= Min
IOL= Max
VIL = Max
VIH= Min

Input Current@Max
Input Voltage

Vcc=Max
VI =7V

High Level Input
Current

Vce= Max
VI=2.7V

Low Level Input
Current

Vee= Max
VI = O.4V

Off-State Output
Current with High
Level Output
Voltage' Applied

Vce=Max, Vo=2.7V
VIH = Min, VIL = Max

II

Min

Typ
(Note 1)

2.4

3.4

-1.5

DM54

0.25

0.4

0.34

0.5

D, RorW

0.1

Gw

0.2

D, RorW·
Gw
GR

IlL

IOZH

V

V

mA

0.3
\

20

I,A

40
60

D,RorW

- 0.4

Gw

-0.8

GR

-1.2
20

4-359

Units

V

DM74

GR
IIH

Max

mA

I,A

Electrical Characteristics

(Continued)
over recommended operating free air temperature (unless otherwise noted)

Symbol.

Parameter

Conditions

10Zl

Off·State Output
Current with Low
Level Output
Voltage Applied

Vec=Max, Vo=0.4V
VIH = Min, Vil = Max

los

Short Circuit
Output Current

Vcc=Max
(Note 2)

Supply Current

Vee = Max (Note 3)

Icc

Switching Characteristics
Parameter

Typ
(Note 1)

Min

Max

Units

-20

/LA

mA

[OM54

:"'20

-100

IDM74

-20

-100
30

50

mA

at Vec = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)

From
(Input)
To
(Output)

RL=667!!
C L =45 pF
Min

C L =150 pF

Typ

Max

Min

Units

Typ

Max

tplH Propagation Delay
Time Low to High
Level Output

Read
Select
toO

23

40

28

50

ns

tpHl Propagation Delay
Time High to Low
Level Output

Read
Select
toO

25

45

31

55

ns

tplH Propagation Delay
Time Low to High
Level Output

Write
Enable
toO

26

45

31

55

ns

tpHl Propagation Delay
Time High to Low
Level Output

Write
Enable
toO

28

50

34

60

ns

tplH Propagation Delay
Time Low to High
Level Output

Data
to

25

45

30

55

ns

tpHl Propagation Delay
Time High to Low
Level Output

Data
to

23

40

29

50

ns

a
a

tPZH Output Enable
Time to High
Level Output

Read
Enable to
AnyO

15

35

25

45

ns

t PZl Output Enable
Time to Low'
Level Output

Read
Enable to
Any Q

22

40

,30

50

ns

tpHZ Output Disable
Time from High
Level Output (Note 4)

Read
Enable to
Any Q

30

50

ns

tpLZ Output Disable
Time from Low
Level Output (Note 4)

Read
Enable to
Any Q,

16

35

ns

Nolel: All typical. are at VCC=sv, TA=2S"C.
Not82: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Nole 3: lee I. measured with 4.SV applied to all DATA input. and bqth ENABLE Inputs, all ADDRESS Inputs are grounded and all output. are open.
Nole 4; CL = SpF.

4·360

~National·

~ Semiconductor
DM54LS952/DM74LS952 Dual Rank a·Bit TRI·STATE®
Shift Registers
General Description
These circuits are TRI·STATE, edge·triggered, B·bit 110
registers in parallel with B·bit serial shift registers which
are capable of operating in any of the following modes:
parallel load from 110 pins to register "A", parallel transfer
down from register "A" to serial shift register "9", parallel
transfer up from shift register "9" to register "A", serial
shift of register "9", synchronously clear. Since the
registers are edge·triggered by the positive transition of
the clock, the control lines which determine the mode or
operation are completely independent of the logic level
applied to the clock. Designed for bus-oriented systems,
these circuits have their TRI-STATE inputs and outputs on
the same pins.

Features

• Output high impedance state does not impede any other
mode of operation
• 8-bit 1/0 pins are TRI-STATE buffers
• Typical shift frequency is 36 MHz
• Typical power dissipation is 305 mW
• All control inputs are active when in an "l"
logic state
• Devices can be cascaded into N,bit word

, Ab~olute Maximum Ratings (Note 1)
Supply Voltage
7V
Input Voltage
7V
-65·Ct0150·C
Storage Temperature Range
lead Temperature (Soldering, 10 Seconds)
300·C
Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should

.. Registers are edge-triggered by the positive transition
of the clock
• All inputs are PNP transistors
• Input disable dominates over output disable

not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram
Dual-In-line Package
vcc

118

I/O 1

I/O 2

I/O 3

I/O 4

16 115

17

I/O 5

I/O 6

13

114

I/O 7

12

I/O 8

10

11

~l
r--

CONTROL
lOGIC

-L

I/O SUFFERS

-I

UPPER REG "A"

-I

1
DISo

I

12

1

3

DISI

I- r-

0

UDOWN

TRANSFER

I

upft

I

lOWER SHIFT REG "S"

~ 5
14
DISru

DISTD

6
DISS

7
Os

8
ClK

1
9

GND
TUF/6431·1

Top View
54lS952 (J)

Pin Description
DISO-Output disable
Is-Serial input
DISI-Input disable
DISTU-Transfer up disable.
DISTD-Transfer down disable
DISS-Shift disable
Os-Serial output
.ClK-Clock
GND-Ground
1/01 .. . 1/0 8-8-bit I/O pins
VCC-Supply Voltage

74lS952 (N)

4-361

m

Recommended Operating Conditions

....I

i::!
e
~

:E.

Symbol

~

:1;
::E
c

DM54LS952

Parameter

VCC

Supply Voltage

VIH

High-Level Input Voltage

DM74LS952

. Units

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.75

5

5.25

2

V

2

V

VIL

Low-Level Input Voltage

10H

High-Level Output Current

10L

Low-Level Output Current

'CLOCK

Clock Frequency

0

Clock
Pulse

High Pulse Width

25

17

25

17

ns

Low Pulse Width

15

7

15

7

ns

tSET-UP

Data Set-Up Time

10

tHOLD

Data Hold Time

TA

Operating Free-Air Temperature

VI

' .

VOH

High-Level Output Voltage

Low-Level Output Voltage

0

125

0

DM54LS952

DM74LS952

Min Typ(2) Max

Min Typ(2) ~ax

-1.5

-1.5

VCC = Min, II = -18 mA
Vce = Min, VIH = 2 V, 10H= -2.6mA

= VIL max

V
0.25

High·Level Input Current

VCC = Max, VI = 2.7 V

IlL

Low-Level Input Current

VCC

lOS
ICC

Supply Current

VCC = Max (4)

10FF

TRI-STATE 1/0 Current

VCC = Max, VIH = 2 V

0.4

0.35

0.5

-20

mA

20

20

/LA

-50

-50

/LA

-100

mA

99

mA

-100
61

V

0.1

-20

99

61

Vo = 2.4 V

20

20

/LA

Va = 0.4 V

-20

-20

/LA

Note 1: For conditions shown as min or max, use the appropriate value specified under recommended operating conditions.
TA = 25°C.

Note 3: Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
IS

0.25

0.1

= Max, VI = 0.4 V

Short-Circuit Output Current VCC = Max (3)

0.4

10L = 16 mA

IIH

V

2.4

VCC = Min, VIH :, 2 V, IOL=8mA

VCC = Max, VI = 5.5 V

Units

2.4

10H = -5.2.mA

Input Current at Maximum
Input Voltage

Note 4: 'ICC

·C

70

over recommended operating free-air temperature range (unless otherwise noted)

II

Vee = 5 V.

mA
MHz

ns

-55

VIL = VIL max

Note 2: All typical values Bre al

16
25

ns

Conditions (1)

VIL
VOL

25

V
mA

0

Parameter
Input Clamp Voltage

0.8
-5.2

8

Electrical Characteristics
S ymbol

0.7
-2.6

measured with serial output open, the clock and shift disable input at 2.4 V. All other control inputs and 1/0 pins grounded.

4-362

Switching Characteristics
Symbol

= 5 V, TA = 25°C

VCC

Parameter

(See Section 1 for Test Waveforms and Output Load)

Conditions

Min

Typ

25

36

7

22

33

na

10

32

48

na

Max

Units

fMAX

Maximum Clock Frequency

tPLH

Propagation Delay Time, Low-to-High-Level
from Clock to Any Output

tpHL

Propagation Delay Time, High-to-Low Level
from Clock to Any Output

tENABLE

Enable Time from Any Control Inputs

5

16

24

ns

tDISABLE

Disable Time from Any Control Inputs

6

18

27

ns

tZH

Ou!put Enable Time to High Level

5

15

23

ns

tZL

Output Enable to Low Level

4

12

18

ns

tHZ

Output Disable Time from High Level

5

15

23

ns

tLZ

Output Disable Time from Low Level

6

18

27

ns

CL

CL

= 15 pF, RL = 1 kll

= 5 pF, RL = 1 kll

MHz

Logic Diagram
I/O 1

1/02

OISO~ ~

"\

:z

~

~~~

J"

0

CK

OISloOISTUo-

=g

a

•

.....0'

CK°1--

'""'""'r-

,...,.
V

H)
,

~
IS

OISyOo-

OISSo--

H>
rD

n

'--

CK

~ ...
-

CK

0
0
CK

a

~

L---{)

Os

CLOCK

TLlFI6437-2

4-363

DM54LS952/DM74LS952

Function Table
Table I

A6

A7

A8

81

B2

B3

B4

BS

86

B7

B8

x

Hi·Z
Oulpul
Inpul

al
al
1,

a2
a2
12

a3
a3
13

a4
a4
14

a5
a5
IS

a6
a6
16

.7
a7
17

a8
a8
18

bl
bl
bl

b2
b2
b2

b3
b3
b3

b4
b4
b4

b5
b5
b5

b6
b6
b6

b7
b7
b7

b8
b8
b8

b8
Siable slale
b8
b8 Enlering dala from 110 to reg. "A"

X
X
X

Hi·Z
Oulpul
Inpul

bl
bl

b2
b2

b3
b3

b4 b5
b4 b5
OOR

b6
bS

b7
b7

b8
b8

.

bl
bl
bl

b2
b2
b2

b3
b3
b3

b4
b4
b4

b5
b5
b5

b6
bS
bS

b7
b7
b7

b8
b8
b8

bS
Transfer data up from reg. "B" to reg. HA"
b8
b8 Reg. "A" will OR dala from 110 and reg. "B"

X
X
X

Hi·Z
Oulpul
Inpul

al
al
1,

a2
a2
12

a3
a3
13

a4
a4
14

a5
a5
15

as
a6
IS

a7
a7
17

a8
a8
IS

al
al
al

a2
a2
a2

a3
a3
a3

a4
a4
a4

a5
a5
a5

as
as
a6

a7
a7
a7

a8
a8
as

a8
Transfer data down from reg. "A" to reg. "B"
a8
as Entering data and transfer down

X
X
X

Hi·Z
Oulpul
Inpul

L
L
1,

L
L
12

L
L
13

L
L
14

L
L
15

L
L
16

L
L
17

L
L
IS

L
L
L

L
L
L

L
L
L

L
L
L

L
L
L

L
L
L

L
L.
L

L
L
L

d
d
d

Hi·Z
Oulpul
Inpul

al
al
11

a2
a2
12

a3
a3
13

a4
a4
14

as
a5
15

a6
as
Ie

a7
a7
17

as
.S
18

d
d
d

bl
bl
bl

b2
b2
b2

b3
b3
b3

b4
b4
b4

bS
bS
b5

b6
b6
b6

b7
b7
b7

b7
Serial shifting in the lower reg. "8"
b7
b7 Entering data and serial shifting

d
d
d

Hi·Z
Oulpul
Inpul

bl
bl

b2
b2

b3
b3

b4 b5
b4 bS
DOR

b6
b6

b7
b7

b8
be

d
d
d

bl
bl
bl

b2
b2
b2

b3
b3
b3

b4
b4
b4

b5
b5
b5

b6
b6
b6

b7
b7
b7

b7
Transfer up and serial shifting
b7
b7 OOR function and serial shifting

DISTO

DISS

CLK

H
L

H
H
L

H
H
H

H
H
H

H
H
H

X
X

X
X

H
H
L

L
L
L

H
H
H

H
H
H

H
H
L

H
H
H

L
L
L

X
X
X

H
H
L

L
L
L

L
L
L

X
X
X

H
H
L

H
H
H

H

H"
H

L'
L
L

H
H
L

L
L
L

H
H
H

L
L
L

t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t

X
H
L

X
H
L

X
H
L

X

i

A2 A3 A4 AS

DISyU

X

H
L

X

...

-

CONTENT OF LOWER SERIAL SHIFT REG. "B"

AI

OISI

H
L

CONTENT OF UPPER REG. "A"

8-BIT I/O
PINS

DISO

IS

.

.

.

x === Don't care
Hi·Z I Oulputllnpull "" High impedance slale I oulpul slale I inpul slale
a 1 ... a81 b 1 ... b8

== The content of the upper register "A" I the lower serial shift register "B" before the most recent t transition of the clock

1, ... 18 "" The level of sleady slale inputs of Ihe 110 pins
DOR"" "Dala ORing funclion" ORlng dala from bolh 110 pins and regisler "B", i.e., It
d

== Data of the serial input

+ bl,I2 + b2,13 + b3 ... 18 + b8

Os

L
L
L

COMMENTS

(1) Synchronously clear both registers to
(2) logic "L" level
(3) Enter dala to reg. "A" clear reg. "B'~

.-----------------------------------------------------------~c

'3:

Timing Diagram

i!
r-

DM54174LS952

5

eLK

-

n

DISO

I

t--I
1103
1/04

-

~

-

n

-

~

-h

1/08

I

fG
c

01

Q

3:
~

w-

r-

..Jr- Os

IS -'!L_LO_W_E_R_S_HI_FT_R_E_G_"_B'_'

10

10

10

10

01

01

01

01

fS
fG

TRI-STATE

r

I

I II

K1I

I
I

3

I

I

I I

I

K1-

1/06
1/07

~-

K1I

1/05

01

J

I

DISS

01

01

-

• • • 1/08

I

L ..J

1/02

L

J
I

DISTU

I/O 1

UPPER REG "A"

J

1/01

6

n-n-n-n-n- I L
4

fS

BEFORE
CLOCK
PULSE #

I

L

I I

I

K1-

•

4

I

L

I

B1

I

B2

L
I

I

B3

I
I

I
I

I

I

I

I

I

5

I
10

10

10

10

10

10

10

00

00

00

001

I

I

I

5

10

6

I

I

6

I
I
I

7

B8

L

oS

I
L

I

I

I

I

TL/F/6437·3

4-365

AC Test Circuit and Switching Time Waveforms
TEST POINT

FROM.OUTPUT
UNDER TEST

0-....- - - -. .- ......- .
All diodes are 1N91e or 1N3064.
pro~e

CL includes

and jig capacitance.

I~
TLIFI6437-4
HIGH CLOCK
PULSE WIDTH ~
3V----+-_....

OV

DISI.DISTU
OISrO & OISS 1.3V
OV
tpdH

3V
I/O&IS 1.3V
OV
tpdl

1/0

VOL

----..,...-'1

3V-----·~----,

OISO 1 . 3 V - - - - - - # -

OV-------I

tLZ

TLIF 16437·5

All input pulses are supplied by generators having Ir.:5 15 ne, If

:s 6

ns, PAR :5 1 MHz, ZOUT ~ 50 O.

Cascading Packages
Cascading Packages for N·Blt Word
1/01

1/08

I I I I I I I I

1/01

1/08

DM54LS952
IS

DISO

1I

•••

I I I I I I I I
DM54LS952

Os

I

IS

I I
1

Os

I

DISI
DISTU
DISTD
DISs

elK
TLIF/6437-6

4·366

N 1/0 PINS

~National

~ Semiconductor
DM54LS962/DM74LS962 Dual Rank a·Bit TRI·STATE@
Shift Registers
General Description
These circuits are TRI·STATE, edge·triggered, B·bit I/O
registers in parallel with B·bit serial shift registers which
are capable of operating in any of the following modes:
parallel load from I/O pins to register "A", parallel transfer
down from register" A" to serial shift register "S", parallel
transfer up from shift register "S" to register "A", serial
shift of register "S", or exchange data between register
"A" and shift register "S". Since the registers are edge·
triggered by the positive transition of the clock, the control
lines which determine the mode or operation are com·
pletely independent of the logic level applied to the clock.
Designed for bus·oriented systems, these circuits have
their TRI·STATE inputs and outputs on the same pins.

• Output high impedance state does not impede any other
mode of operation
•
•
•
•

a·bit 1/0 pins are TRI·STATE buffers
Typical shift frequency is 36 MHz
Typical power dissipation is 305 mW
All control inputs are active when in an "l"
logic state
• Devices can be cascaded into N·bit word

Absolute Maximum Ratings (Note 1)
Supply Voltage
7V
Input Voltage
7V
Storage Temperature Range
- 65·C to 150·C
Lead Temperature (Soldering, 10 seconds)
300·C

Features

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

• Registers are edge·triggered by the positive transition
of the clock
• All inputs are PNP transistors
• Input disable dominates over output disable

Connection Diagram
Dual·ln-line Package
VCC

118

I/O 1. I/O 2

17

I/O 3·

16

I/O 4

115

I/O 5

I/O 6

I/O 7

I/O 8

13

12

11

10

114

Pin Description
DISO-Output disable
Is-Serial input
DISI-Input disable
DISTU-Transfer up disable
DISTD-Transfer down disable
DISS-Shift disable
Os-Serial output
ClK-Clock
GND-Ground
110 1 ... 110 8-a·bit 110 pins
VCC-Supply Voltage

~l
H
r-

CONTROL
lOGIC

0

1--1

UPPER REG """
UDOWN

1--1

DI50

12

1

3

DISI

1

upD

TRANSFER

1

lOWER SHIFT REG "8"

~

I
1

1- r-

I/O 8UFFERS

5

6

DISTD

DISS

14
DISTU

7

Os

Top View

54lS962.(J)

8

19

elK

GND
TLlF/6438·1

74lS962(N)

4-367

M
~

Recommended Operating Conditions
DM54LS962

:E

Symbol

~

VCC

Supply Voltaga

V,H

High·Level Input Voltage

~

V,L

Low-Level Input Voltage

10H

High-Level Output Current

10L

Low-Level Output Current

c

~

:E

c

Parameter·

DM74LS962

Unite

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.75

5

5.25

2

V

2

V

0.8

0.8

-2.6

-5.2

rnA

16

rnA

8

V

fCLOCK

Clock Frequency

0

Clock
Pulse

High Pulse Width

25

17

25

17

. ns

Low Pulse Width

15

7

15

7

ns

tSET-UP

Data Set-Up Time

10

tHOLD

Data Hold Time

0

TA

Operating Free-Air Temperature

Electrical Characteristics
Symbol
VI
VOH

VCC = Min, V,H = 2 V, 'OH= -2.6 rnA

·C

70

DM54LS962

DM74LS962

Min Typ(2) Max

Min Typ(2) Max

-1.5

-1.5

Units

2.4

V
V

2.4

10H = -5.2 rnA
0.25

VCC = Min, V,H = 2 V, 10L = 8mA
V,L = V,L max

"

0

VCC = Min, II = -18 rnA

Low-Level Output Voltage

MHz

ns
125

Conditions (1)

High-Level Output Voltage

25

over recommended operating free-air temperature range (unless otherwise noted)

Parameter
Input Clamp Voltage

0

ns

-55

V,L = V,L max
VOL

25

0.4

10L =.16 rnA

Input Current at Maximum
Input Voltaga

VCC:= Max, V, = 5.5 V

0.1

0.25

0.4

0.35

0.5

V

0.1

rnA
p.A

IIH

High-Level Input Current

VCC

20

Low-Level Input Current

VCC

-50

-50

p.A

lOS

Short-Circuit Output Current

= Max, V, = 2.7 V
= Max, V, = 0.4 V
VCC = Max (3)

20

IlL

-100

rnA

ICC

Supply Current

VCC = Max (4)

TRI-STATE I/O Current

= 2.4V
VCC = Max, V,H = 2 V
Vo = 0.4V

10FF

-20

-100

-20

99

61

99

rnA

20

p.A

-20

-20

p.A

Note 1: For conditions shown as mm or max, use the appropriate value specified under recommended operating conditions.
Note 2: All typical values are al

Vee

= 5 V, TA = 25°C.

Nole 3: Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
Note 4: ICC is measured with senal output open, the clock and shift disable input at 2.4 V. All other control inputs and 110 pins grounded.

4-368

61

20

Vo

Switching Characteristics

VCC

= 5 V, TA = 25°C

(See Section 1 for Test Waveforms and Output Load)
Min

Typ

fMAX

Maximum Clock Frequency.

25

36

tPLH

Propagation Delay Time, low-to-High-Level
from Clock to Any Outputs

7

22

33

ns

tPHL

Propagation Delay Time, High-to-Low Level
from Clock to Any Outputs

10

32

48

ns

tENABLE

Enable Time from Any Control Inputs

5

16

24

ns

tDISABLE

Disable Time from Any ,Control Inputs

6

18

27

ns

tZH

Output Enable Time to High Level

5

15

23

ns

tZL

Output Enable to Low Level

4

12

18

ns

tHZ

Output Disable Time from High Level

5

15

23

ns

tLZ

Output Disable Time from Low Level

6

18

27

ns

Symbol

Conditions

Parameter

CL

CL

= 15 pF, RL = 1 kn

= 5 pF" RL = 1 kn

Max

Units
MHz

Logic Diagram
1/01

0150 v-

;:r=>

\

\

~

~~

~

01510OISTUo-

ft

OISTO 0 -

0155 0 - -

H>
H>

°CK O .

• • • 881TS

CK Q

'"
rt>
V

~ n···
~

IS

1/02

'--

CK

CK

Q

0
CK O

--!)

~
aS

CLOCK

TUF/6438-2

4-369

DM54LS962/DM74LS962

Function Table
Table I

OISO

OISI

H
L

X
H
L

X
H
L

X
H
L

X

H
L

X

t

Cl

H
L

X

OISTU

OISTD

OISS

CLK

X
X

IS

8-BIT 1/0
PINS

X
X
X

CONTENT OF UPPER REG. "A"

CONTENT OF LOWER SERIAL SHIFT REG. "B"

A2

A3

A4

AS

A6

A7 A8

Bl

B2

83

B4

BS

86

87

88

Hi·Z
Output
Input

a1
a1

a2
a2

a3
a3

a4
a4

as
as

as
as

a7
a7

a8
a8

11

12

13

14

15

IS

17

18

b1
bt
bt

b2
b2
b2

b3
b3
b3

b4
b4
b4

b5
bS
bS

bS
bS
bS

b7
b7
b7

b8
b8
b8

b8
b8
b8

X
X
X

Hi-Z
Output

bl
bl

b2
b2

b3
b3

b4 bS
b4 b5
DOR

bS
bS

b7
b7

b8
b8

bl
b1
b1

b2
b2
b2

b3
b3
b3

b4
b4
b4

bS
bS
bS

bS
bS
bS

b7
b7
b7

b8
b8
b8

b8
Transfer data up from reg. "B" to reg. "A"
b8
b8 Reg. "A" will OR data from 110 and reg. "S"

Hi-Z

al
a1
11

a2
a2
12

a3
a3
13

a4
a4
14

as
as
15

as
as
IS

a7
a7
17

a8
a8
18

al
a1
a1

a2
a2
a2

a3
a3
a3

a4
a4
a4

as
as
as

as
as
as

a7
a7
a7

a8
a8
a8

a8
a8
a8

bl
bl

b2
b2

b3
b3

b4
b4

bS
bS

bS
bS

b7
b7

b8
b8

al
al
al

a2
a2
a2

a3
a3
a3

a4
a4
a4

as
as
as

as
as
as

a7
a7
a7

a8
a8
a8

a8
a8
a8

d
d
d

b1
bl
bl

b2
b2
b2

b3
b3
b3

b4
b4
b4

bS
bS
b5

bS
bS
bS

b7
b7
b7

b7
b7
b7

d
d
d

bl
bl
b1

b2
b2
b2

b3
b3
b3

b4
b4
b4

b5
b5
bS

bS
bS
bS

b7
b7
b7

b7
b7
b7

t transition of the

clock

H
H
L

H
H
H

H
H
H

H
H
H

H
H
L

L
L
L

H
H
H

H
H
H

t
t
t
t

H
H
L

H
H
H

L
L
L

X
X
X

t
t
t

X
X
X

Output

H
H
L

L
L
L

L
L
L

X
X
X

t
t
t

X
X
X

Hi-Z
Output
Input

Input

Input

.

.

H
H
L

H
H
H

H
H
H

L
L
L

t
t
t

d
d
d

Hi-Z
Output
Input

al
a1

H
H
L

L
L
L

H
H
H

L
L
L

t
t
t

d
d
d

Hi-Z
Output
Input

DOR

.

.

a3
a3

a4
a4

as
as

as
as

a7
a7

a8
a8

11

a2
a2
12

13

14

15

IS

17

;8

bl
b1

b2
b2

b3
b3

b4 b5
b4 b5
DOR

bS
bS

b7
b7

b8
b8

.

.

x == Don't care
Hi-Z / Output / Input I
a 1 ... a8/bl
11 .. Ia
DOR
d

== High impedance state / output state I input state

. be:::=: The content of the upper register "A" Ithe lower serial shift register "8" before the most re~ent

=== The level of steady state inputs of the 110 pins

=== "Data DRing function" DRing data from both 110 pins and register "S", i.e .. 11 + b1, 12 + b2,13 + b3 .. Ia + ba

== Data of the serial input

COMMENTS

Os

Al

Stable state

Entering data from 110 to reg. "A"

Transfer data down from reg. "A" to reg. "B"
Entering data and transfer down
(1)
(2)
(3)

Exchange data between registers

Beside data exchanging, reg. "A"
will "OR" data I from /10 and reg. "8"

Serial shifting in the lower reg. "B"
Entering data and serial shifting
Transfer up and serial shifting
DOR function and serial shifting

Timing Diagram
DM54174LS962

!L-I L n-n-n-n...
4 5 6

CLK

-

n

OISO

L~

I

IS

I

DlSTU

LW

DlSTO

01

1/08
01

01

01

{>

-+I

LOWER SHIFT REG ''8''
10

10

10

01

01

01

01

10

10

10

10

11

11

11

11

01

01

01

01

r

10

I

1

OISS

I/O 1

UPPER REG "A"

I

I

OISI

BEFORE'
CLOCK
PULSE #

J

IS

f1/01

1/02
1/03

1/04
1105

1/06
1/07

1/08

B1

B2

....
~

a:
W
"'a:
a:W

~!!i

gfit

B3

B4

1La:

eli;

B5

z:l:

r--

- W
~

-

1'-1

h

~

1

I I

l-ri-

w

1

I I

~h

~

k----J
I

~
I

l--rl-

4

~-1

II

I

I

1

I

I

I
I

1

1

1

I

I

I

1

o

!--5

1

I

w'"

8

~
I

I"

I I

..

I

I

!---

i..--

1

I-

z

TRI-STATE

1

-- w
h
-

f-

B7

1

1

I

I

I

1
B8

Os

6

I

B6

I

I
I

f----

TL/F/6438-3

4-371

Os

AC Test Circuit and Switching Time Waveforms
TEST POINT

FROM OUTPUT
UNDER TEST

o-..........- - -...-~.-..
All diodes are 1N916 or 1N3064.
CL includes probe and jig capacitance.

TL/F/6438-4

OV

OISI.OISTU
'1.3V
OISTO & 0155
OV

3V

1/0&15 1.3V
OV

IpdL

1/0
VOL

3V

015 0

1.3V
OV

TL/F/6438-S
All input pulses are supplied by generators having tr :S 15 nB, 'f :S 6 ns, PRR :S 1 MHz, ZOUT ~ 50

n.

Cascading Packages
Cascading Packages for N-Blt Word
1/08

1/01

1 1 I, 1 1 1 1 r

1/01

1/08

DM74LS962

DM54LS962
IS

OISo

11

•••

11111I I I

Os

I

IS

I I
1

Os

I

DISI
. DISTU
DISTD
DISs

elK
TLlF/643B-6

4-372

N 1/0 PINS

Section 5

Schottky

Section Contents
DM54/74S00Quad2-lnputNANDGates .............................................
DM54/74S02 Quad 2-lnput NOR Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74S03 Quad 2-lnput NAND Gates with Open-Collector Outputs ............. : . . . . . . .
DM54/74S04 Hex Inverters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74S05 Hex Inverters with Open-Co"ectorOut'puts . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74S08Quad2-lnputANDGates...............................................
DM54/74S09 Quad 2-lnput AND Gates with Open-Collector Outputs ..............•.......
DM54/74S10Triple3-lnputNANDGates ......•.....................•................
DM54/74S11Triple3-lnputANDGates ......................•........................ DM54/74S15 Triple 3-lnput AND Gates with Open-Co"ectorOutputs ......................
DM54/74S20 Dual4-lnput NAND Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74S22 Dual4-lnput NAND Gates with Open-Co"ectorOl!tputs.. . . . . . . . . . . . . . • . . . . . .
DM54/74S30 8-lnput NAND Gate. . . . . . . . . . ... . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . .
DM54/74S32 Quad 2-lnput OR Gates. . . . . . . . .. • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . .
DM54/74S40 Dual4-lnput NAND Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74S51 Dual 2-Wide2-lnput AND-OR-INVERTGates ...............................
DM54/74S64 4-WideAND-OR-INVERTGates. . . . .. . . .. . .. . . . . .. . . .. . . .. . . . ... . . .. . . . .
DM54/74S65 4-Wide AND-OR-INVERT Gates with Open-Collector Outputs ................
DM54/74S74 Dual Positive-Edge-Triggered 0 Flip-Flops with Preset and Clear. . . . . . . . . . . . . .
DM54/74S86 Quad Exclusive-OR Gates ..... : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74S112 Dual Negative-Edge-Triggered J-K Flip-Flops with Preset and Clear. . . . . . . . . . .
DM54/74S113 Dual Negative-Edge-Triggered J-K Flip-Flops with Preset ...... -. . • . . . . . . . . . . .
DM54/74S114 Dual Negative-Edge-Triggered J-K Flip-Flops
with Preset, Common Clear, and Common Clock ...... .-.............................
DM54/74S133 13-lnput NAND Gate. . . . . . . . . • . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74S134 TRI-STATE 12-lnput NAND Gate •.............. . . .•. . .. . . . . . . . .•. .. .. . . .
DM54/74S135 Quad Exclusive-OR/NOR Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . .
DM54/74S136 Quad Exclusive-OR Gates with Open-Co"ectorOutputs ....................
DM54/74S138 3 to 8 Line DecoderlDemultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/7 4S 139 Dual2 to 4 Li ne Decodersl Oem ultiplexers ......................... -. . . . . . .
DM54/74S140 Dual4-lnput NAND 50!} Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- DM54/74S151 1 of8 Line DataSelector/Multiplexer ...................................
DM54/74S153 Dual1 of 4 Line Data Selectors/Multiplexers ..................... : . . . . . . . .
DM54/74S157 Quad 2 to 1 Line Data Selectors/Multiplexers . . • . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74S158 Q~ad 2 to 1 Line Inverting DataSelectors/Multiplexers .....................
DM54/74S160 Synchronous 4-Bit Decade Counter with Asynchronous Clear. . . . . . . . . . . . . . . .
DM54/74S161 Synchronous 4-Bit Binary Counter with Asynchronous Clear. . . . . . . . . • . . . . . . .
DM54/74S162 Synchronous 4-Bit Decade Counter with Synchronous Clear. . . . . . . . . . . . . . . . .
DM54/74S163 Synchronous 4-Bit Binary Counter with Synchronous Clear. . . . . . . . . . . . . . . . . .
DM54/74S174 Hex 0 Flip-Flops with Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74S175 Quad 0 Flip-Flops with Clear and Complementary Outputs. . . . . . . . . . . . . . . . . .
DM54/74S181 Arithmetic Logic Unit/Function Generator ....................... ; . . . . . . .
DM54/74S182 Look-Ahead Carry Generator ........................••...•.....•..•...
DM54/74S194 4-Bit Bidirectional Universal Shift Register ..............................
DM54/74S195 4-Bit Para"el Access Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . .
DM54/74S196 4-Bit Presettable Decade (Bi-Quinary) Counter .•.....•........... -. . . . . . . •
DM54/74S197 4-Bit Presettable Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74S240 Octal TRI-STATE Inverting Buffers/Line Drivers/Line Receivers. . . . . . . . . . . . . . .
DM54/74S241 Octal TRI-STATE Buffers/Line Drivers/Line Receivers ..•............•......

5·2

5-5
5-7
5-9
5-11
5-13
5-15
5-17
5-19
5-21
5-23
5-25
5-27
5-29
5-31
5-33
5-35
5-37
5-39
5-41
5-45
5-48
5-52
5-55
5-58
5-60
5-63
5-66
5-68
5-68
5-73
5-75
5-79
5-82
5-82
5-87
5-87
5-87
5-87
5-96
5-96
5-100
5-.108
5-112
5-116
5-119
5-119
5-126
5-126

Section Contents

(Continued)

DM54/74S242 Quad TRI-STATE Inverting Bus Transceivers ............................. .
DM54/74S243 Quad TRI-STATE Bus Transceivers ..................................... .
DM54/74S244 Octal TRI-STATE Buffers/Line Drivers/Line Receivers ..................... .
DM54/74S251 TRI-STATE 1 of 8 Line Data Selector/Multiplexer with
Complementary Outputs ...................................................... .
DM54/74S253 Dual TRI-STATE 1 of4 Data Selectors/Multiplexers ........................ .
DM54/74S257 Quad TRI-STATE 2 to 1 Line Data Selectors/Multiplexers ................... .
DM54/74S258 Quad TRI-STATE 2 to 1 Line Inverting Data Selectors/Multiplexers ........... .
DM54/74S280 9-Bit Parity Generators/Checkers ..................................... .
. DM54/74S283 4-Bit Binary Adders with Fast Carry .................................... .
DM54/74S299 TRI-STATE8-BitUniversal Shift/Storage Registers ........................ .
DM54/74S373 Octal :rRI-STATE TransparentD Latches ................................ .
DM54/74S374 Octal TRI-STATE Positive-Edge-Triggered D Flip-Flops ..................... .
DM54/74S381 Arithmetic Logic Unit/Function Generator .... : ......................... .
DM54/74S940 OctaITRI-STATE Inverting Buffer ...................................... .
DM54/74S941 Octal TRI-STATE Buffer .............................................. .

5·3

5-129
. 5-129
5-126
5-132
5-136
5-139
5-139
5-144
5-148
5-152
5-158
5-158
5-165
5-169
5-169

~Nati.onal

~ Semiconductor

DM54S00/DM74S00 Quad 2-lnput NAND Gates

General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic NAND function.

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

7V
5.5V
- 65·C to 150·C

Nola 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual·ln·Line Package

Y=AB

Inputs

B

Y

L
L
H
H

L
H
L
H

H
H
H
L

H = High Logic Level
L = Low Logic Level

A1

B1

Y1

AZ

BZ

YZ

GND

TLlFf6489·1

DM54S00 (J) DM74S00 (N)

5-5

Output

A

Recommended Operating Conditions
DM74S00

DM54S00

Sym

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level Input
Voltage

0.8

10H

High Level Output
Current

-1

-1

mA

10l

Low Level Output
Current

20

20

mA

TA

Free Air Operating
Temperature

70

·C

VI

Nom

Max

Min

Nom

4.5

5

5.5

4.75

5

2

-55

input Clamp Voltage
. High Level Output
Voltage

VOL

Low Level Output
. Voltage

5.25

V

.

V

0.8

V

125

0

over recommended operating free air temperature (unless otherwise noted)

Parameter

VOH

2

Units

Max

I

Electrical Characteristics
Sym

Min

Min

Typ
(Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

-1.2

Vee=Min, 11= -18 mA
Vee=Min
10H= Max
Vll=Max

Max

Units
V
V

Vcc = Min, IOl =. Max
VIH=Min

0.5

V

II

Input Current@Max
Input Voltage

Vee=Max, VI =5.5V

1

mA

IIH

High Level Input
Current

Vee=Max, VI=2.7V

.50

/LA

IlL

Low Level Input
Current

Vec=Max, VI =0.5V

-2

mA

los

Short Circuit
Output Current

Vcc=Max
(Note 2)

rnA

ICCH

Supply Current With
Outputs High

Vcc=Max

lecl

Supply Current With
Outputs Low

Vec=Max

Switching Characteristics

DM54

-40

-100

DM74

-40

-100

,

10

16

rnA

20

36

rnA

at Vce = 5V and TA = 25·C (See Section 1 for Test Waveforms ~nd Output Load)
RL =280{l

Parameter

CL=15 pF

CL=50pF

Units

Min

Typ

Max

Min

Typ

Max

tplH Propagation Delay Time
Low to High Level Output

2

3

4.5

2

4.5

7

ns

tpHl Propagation Delay Time
High to Low Level Output

2

3

5

2

·5

8

ns

Nola 1: Aillypicals are al Vec;5V, TA;25·C.
Nole 2: Not more than one output should be shorted at a time, and the duration should not exceed' one second.

5-6

.-------------------------------------------------------------,0
i:

~National

I

~ Semiconductor

o
i:

~

DM54S02/DM74S02 Quad 2-lnput NOR Gates

General Description

Absolute Maximum Ratings

This device contains four Independent gates each of
which performs the logic NOR function.

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)
7V

5.5V
- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum rallngs. The "Recommended Operating Conditions" table will
define the conditions tor actual device operation.

Connection Diagram

Function Table

Oual-In-Llna Package
Y=ABCO

Inputs

Output

A

B

C

0

Y

X
X
X

X
X

X

L

L

L

L

X

X
X

X
X
X

H
H
H
H

H

H

H

H

L

H = High Lagle Level
VI

AI

B1

Y2

A2

B2

L = Low Logic Level

GND

X = Either Low or High Lagle Level

TLJF/6490·'

OM54S02 (J) OM74S02 (N)

5-7

Recommended Operating Conditions
Sym

Parameter

DM54S02

DM74S02

Min

Nom

' Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units
V

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

0.8

0.8

V

10H

High Level Output
Current

-1

-1

mA

Low Level Output'
Current

20

20

mA

70

·C

10L
TA

I

Free Air Operating
Temperature

2

2

,

-55

125

0

:

V

)

Electrical Characteristics over recommended operating free air tempera,ure (unless otherwise noted)
Sym

Min

fyp
(Note 1)

DM54

2.5

3.4

DM74,

2.7

3.4

Conditions

Parameter

Max
-1.2

Units
V

VI

Input Clamp Voltage

Vcc=Min, 11= -18 mA

VOH

High Level Output
Voltage

Vcc=Min
IOH=Max
VIL=Max

VOL

Low Level Output
Voltage

Vcc=Min,loL=Max
VIH=Min

0.5

V

II

Input Current@Max
Input Voltage

Vcc=Max, VI = 5.5V

1

mA

IIH

High Level Input
Current

Vcc=Max, VI=2.7V

50

/LA

IlL

Low Level Input
Current

Vcc = Mai, VI = 0.5V

-2

mA

los

Short Circuit
Output Current

Vcc= Max
(Note 2)

-100

mA

ICCH

Supply Current With
Outputs High

Vcc=Max

17

29

mA

ICCL

Supply Current With
Outputs Low

Vcc=Max

26

45

mA

DM54

-40

DM74

-40

Switching Characteristics at Vcc=5V and TA=25·C

V

-100

(See Section 1 for Test Waveforms and Output Load)

RL =280!l
C L = 15 pF

Parameter

Units

CL=50 pF

Min

Typ

Max

Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

1.5

3.5

5.5

2

5

7.5

ns

tpHL Propagation Delay Time
High to Low Level Output

1.5

3.5

5.5

2

5

7.5

ns

Nole 1: All typical. are at VCC=SV, TA =2S"C,
Note 2: Not more than one output should be shorted at a time. and the dUration should not exceed one second.

5-8

r------------------------------------------------------------------,c

3:

.
~ Semiconductor"
~National

~

Co)

c

3:

~

DM54S03/DM74S03 Quad 2-lnput NAND Gates
with Open-Collector Outputs

B

General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic NAND function. The open·
collector outputs require external pull-up resistors for
proper logical operation.

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

Pull·Up Resistor Equations

R

MIN=

Where:

7V

5.5V
7V

- 65·C to 150·C

Note I: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Vcc(Max)-VOL
10L -N3 (lILl
NI (lOH) = total maximum output high current
for all outputs tied to pull-up resistor
N2 (IIH) = total maximum inp,ut high current for
all inputs tied to pull-up resistor
N3 (11Ll = total maximum input low current for
all inputs tied to pull-up resistor

Connection Diagram

Function Table

Dual-In-Line Packa!le
Y=AB

Inputs

TlIF/6491-'

DM74S03 (N)

5-9

Output

A

B

Y

L
L
H
H

L
H
L
H

H
H
H
L

H = High Logic Level
L = Low Logic Level

DM54S03 (J)

(Note 1)

~

Recommended Operating Conditions

c

Sym

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

0.8

0.8

V

VOH

High Level Output
Voltage

5.5

5.5

V

10L

Low Level Output
Current

20

20

mA

TA

Free Air Operating
Temperature

70

·C

:e

I
:e

c

,-'

DM54S03

DM74S03

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

-55

125

Electrical Characteristics over recommended operating
Sym

Parameter

V
V

2

2

Units

0

free air temperature (unless otherwise noted)

Conditions

Min

Typ
(Note 1)

Max

Units

VI

Input Clamp Voltage

Vcc= Min, 11= -18 mA

-1.2

V

ICEX

High Level Output
Current

Vcc=Min, Vo=5.5V
VIL = Max

250

/LA

VOL

Low Level Output
Voltage

Vcc=Min,loL=Max
VIH=Min

0.5

V

:11

Input Current@Max'
Input Voltage

Vce=Max, VI =5.5V

1

mA

IIH

High Level Input
Current

Vec=Max, VI=2.7V

50

/LA

IlL

Low Level Input
Current

Vce = Max, VI = 0.5V

-2

mA

lecH

Supply Current With
Outputs High

Vee=Max

6.0

13.2

mA

lecL

Supply Current With
Outputs Low

Vec=Max

20

36

mA

Switching Characteristics

at Vee=5V and TA =25·C (See Section 1 for Test Waveforms and Qutput Load)
RL =280n

Parameter
Min

Typ

tpLH Propagation Delay Time
Low to High Level Output

2

5

. tpHL Propagation Delay Time
High to Low Level Output

2

4.5.

~

Max

Min

Typ

Max

7.5

3

7.5

11

ns

7

3

7

11

ns

Nole 1: Aillypicals are at vee =5V, TA =25·C.

I

5·10

Units

C L =50 pF

C L =15pF

.-------------------------------------------------------------,0

!:

~National

U'I

~

~ Semiconductor

g

o
3:
......

~

o

DM54S04/DM.74S04 Hex Inverting Gates

0l:Io

General Description

Absolute Maximum Ratings

This device contains six independent gates each of
which performs the logic INVERT function.

Supply Voltage
Input Voltage

(Note 1)
7V
5.5V

- 65 ·C to 150·C

Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual·ln·Line Package
Vj'

114

A'
13

y.
12

A5

Y5

11

A'

y,

10

Y=A
Input

Y

L

H
L

H
H ~ High Logic Level
L ~ Low Logic Level
J
Al

VI

AZ

5
YZ

AJ

VJ

TLlFJ6442·1

DM54S04 (J)

DM74S04 (N)

5·11

Output

A

Recommended Operating Conditions
DM54S04

DM74S04

Sym

Parameter

Vcc

Supp.ly Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

0.8

0.8

V

10H

High Level Output
Current

-1

-1

mA

10L

Low Levei Output
Current

20

20

mA

Til

Free Air Operating
Temperature

70

'C

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

125

V
V

2

-55

Units

0

Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Sym

Parameter

..

Min

Typ
(Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

Max
-1.2

Units

VI

Input Clamp Voltage

Vcc= Min, II = -18 mA

VOH

High Level Output
Voltage

Vcc=Min
10H=Max
VIL=Max

V

VOL

Low Level Output
Voltage

Vcc = Min, 10L = Max
VIH = Min

0.5

V

II

Input Current@Max
Input Voltage

Vcc = Max, VI = 5.5V

1

mA

IIH

High Level Input
Current

. Vcc=Max, VI=·2.7V

50

I'A

IlL

Low Level Input
Current

Vcc = Max, VI = 0.5V

-2

mA

los

Short Circuit
Output Current

Vcc=Max
(Note 2)

mA

V

DM54

-40

-100

DM74

-40

-100

ICCH

Supply Current With
Outputs High

Vcc=Max

15

24

mA

ICCL

Supply Current With
Outputs Low

Vcc=Max

30

54

mA

Switching Characteristics

at Vcc = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL=2801l

Parameter

Units

CL=15 pF

CL=50pF
Max

Min

Typ

Max

Min

Typ

tpLH Propagation Delay Time
Low to High Level Output

2

3

4.5

2

4.5

7

ns

tpHL Propagation Delay Time
High to Low Level Output

2

3

5

2

5

8

ns

Nola I: Alltyplcals are at VCC=SV, TA=2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

5·12

.----------------------------------------------------------,0
3:

~National

~

~ Semiconductor

!:!!

o
3:

~

DM54S05/DM74S05 Hex Inverters
with Open·Colle~tor Outputs

CII

General Description

Absolute Maximum Ratings

This device contains six independent gates each of
which performs the logic INVERT function. The open·
collector outputs require external pull·up resistors for
.
proper logical operation.

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

7V
5.5V
7V
-65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will

Pull·Up Resistor Equations

define the conditions for actual device operation.

RMIN =

Where:

(Note 1)

Vcc (Max) - VOL
10L -N3 (lu.l
N1 (IOH) = total maximum output high current
for all outputs tied to pull·up resistor
N2 (IIH) = total maximum input high current for
all inputs tied to pull·up resistor
N3 (IIU = total maximum input low current for
all inpufs tied to pull·up resistor

Function Table

Input

Y

L
H

H
L

H = High Logic Level
L = Low Logic Level

5·13

Output

A

Recommended Operating Conditions
DM54S05
Sym

Parameter

Vee
VIH

DM74S05

Min

Nom

Max

Min

Nom

Max

Supply Voltage·

4.5

5

5.5

4.75

5

5.25

High Level Input

2

Units
V

2

V

Voltage

VIL

Low Level Input

0.8

0.8

V

5.5

5.5

V

20

20

mA

70

'C

Voltage

High Level Output

V OH

Voltage

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

-55

Electrical Characteristics
Sym

125

0

over recommended operating free air temperature (unless otherwise noted)

Parameter

Conditions

Min

Typ
(Note 1)

Max

Units

-1.2

V

Vee=Min, Vo=5.5V
VIL = Max

250

p.A

Low Level Output
Voltage

Vee = Min, IOL = Max
VIH = Min

0.5

V

II

Input Current@Max
Input Voltage

Vee=Max, VI=5.5V

1

mA

IIH

High Level Input
Current

Vee = Max, VI = 2.7V

50

p.A

IlL

Low Level Input
Current

Vee= Max, V I =0.5V

-2

mA

leeH

Supply Current With
Outputs High

.Vee= Max

9.0

19.8

mA

leeL

Supply Current With
Outputs Low

Vee=Max

30

54

mA

VI

Input Clamp Voltage

Vee=Min, 11 = -18 mA

leEx

High Level Output
Current

VOL

Switching Characteristics

at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL = 2801]

Parameter

C L =15 pF

C L =50 pF

Units

Min

Typ

Max

Min

tpLH Propagation Delay Time
Low to High Level Output ut

2

5

7.5

3

7.5

11

ns

tpHL Propagation Delay Time
High to Low Level Output ut

2

4.5

7

3

7

11

ns

Note 1:

All

typicals are at

Vee=5V, TA=25'e.

5·14

. Typ

Max

c

3:

~National

ii

~ Semiconductor

c

3:

DM54S08/DM74S08 Quad 2-lnput AND Gates
General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic AND function.

Supply Voltage
Input Voltage

(Note 1)

7V
5.5V
- 65·C to 150·C

Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual-ln·Llne Package
B4

.4

V4

"

A3

y,

Y=AB
Inputs

B

Y

L
L
H
H

L
H
L
H

L
L
L
H

H = High Logic Level
L = Low Logic Level
TLlF/6444·1

DM54S08 (J)

DM74S08 (N)

5·15

Output

A

Recommended Operating Conditions
DM54S08
Sym

Parameter

DM74S08

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units
V

Vcc

Supply Voltage

VIH

High Level Input·
Voltage

VIL

Low Level Input
Voltage

0.8

0.8

V

IOH

High Level Output
Current

-1

-1

mA

IOL

Low Level Output
Current

20

20

mA

TA

Free Air Operating
Temperature

70

°C

2

V

2

-55

125

0

Electric,al Characteristics over recommended operating free air temperature (unless otherwise noted)
Sym

Parameter

Min

Typ
(Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

Max
-1.2

Units

VI

Input Clamp Voltage

VOH

High Level Output
Voltage

Vcc=Min
IOH=Max
VIH=Min

VOL

Low Lev.el Output
Voltage

Vcc = Mhl, IOL = Max
VIL= Max

0.5

V

II,

Inpyt Current@Max
Input Voltage

Vcc = Max, VI = 5.5V

1

mA

IIH

High Level Input
Current

Vcc=Max, VI=2.7V

50

/LA

IlL

Low Level Input
Current

Vcc = Max, VI = 0.5V

-2

mA

los

Short Circuit
Output Current

Vcc=Max
(Note 2)

-100

mA

ICCH

Supply Current With
Outputs High

Vcc=Ma1<

18

32

mA

ICCL

Supply Current With
Outputs Low

Vcc= Max

32

57

mA

Vcc = Min, 11= - 18 mA

V

,

Switching Characteristics

DM54

-40

DM74

-40

V

-100

at Vcc = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL = 2800

Parameter.

CL=15 pF

Units'

CL=50 pF

Min

Typ

Max

Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

2.5

4.5

7

3

6

9

ns

tpHL Propagation Delay Time
High to Low Level Output

2.5

5

7.5

3

7.5

11

ns

Nota 1: All typicals are at VCC=5V, TA =25"C,
Note 2: Not more than one output should be shorted at a time. and the duration should not exceed one second.

5-16

c
s::
U1

.
~ Semiconductor
~National

~

o

-s::
CD

C

......

~CD

DM54S09/DM74S09 Quad 2·lnput AND Gates
with Open·Coliector Outputs
General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic AND function. The opencollector outputs require an external pull-up resistor for
proper logical operation.

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

7V

5.5V
7V

- 65·C to 150 ·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Pull·Up Resistor Equations

RMIN = V-,C""C,-,(,-M...,a:-;-x,-)-,.,--:V!

12

NI~11

"

10

y,

T9

~
J:

C1

Y=ABCD

•
Inputs

,~

4

DI,5

),6

J:

Output

C

0

Y

X
X
L
X

X
L
X
X

L
X
X

H
H
H
H

H

H

H

L

A

B

X
X
X
L

H

X

H = High Logic Level
L=-Low Logic Level
X = Either Low or High Logic Level

TlIF/6453·'

DM54S40(J)

-

I

DM74S40 (N)

5·33

Recommended Operating Conditions
DM54S40

DM74S40

Sym

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level Input
Voltage

0.8

0.8

V

10H

High Level Output
Current

-3

-3

mA

10l

Low Level Output
Current

60

60

mA

TA

Free Air Operating
Temperature

70

·C

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units
V

2

-55

125

V

0

Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Sym

Parameter

Min

Typ
(Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

Max
-1.2

Units
V

VI

Input Clamp Voltage

Vee = Min, 11= -18 mA

VOH

High Level Output
Voltage

Vec=Mln
IOH=Max
Vll = Max -

VOL

Low Level Output
Voltage

Vec=Mln, iOl=Max
VIH=Mln

0.5

V

II

Input Current@Max
Input Voltage

Vce = Max, VI = 5.5V

1

mA

IIH

High Level Input
Current

Vcc=Max, VI=2.7V

100

!LA

III

Low Level Input
Current

Vcc=Max, VI=0.5V

-4

mA

los

Short Circuil
Output Current

Vcc=Max
(Note 2)

-225

mA

ICCH

Supply Currerit With
Outputs High

Vcc=Max

10

18

mA

ICCl

Supply Current With
Outputs Low

Vcc=Max

25

44

mA

DM54

':'50

DM74

-50

V

-225

I

Switching Characteristics at Vcc=5V and TA=25·C

(See Section 1 for Test Waveforms and Output Load)
RL=93{)

Parameter

C L =50 pF

CL=150 pF

Units

Min

Typ

Max

Min

Typ

Max

tplH Propagation Delay Time
Low to High Level Output

2

4

6.5

3

6

9

ns

tpHl Propagation Delay Time
High to Low Level Output

2

4

6.5

3

6

9

ns

Nole 1: All typical. are at VCC =5V. TA =25·C.

Note 2: Not more than one output should be shorted at a time, and ~he duration should not exceed one" ~econd.

'5·34

r---------------------------------------------------------------'c
3:

~National

~
....

~ Semiconductor

-c
c.n

3:

~
....

DM54S51/DM74S51 Dual 2·Wide 2·lnput
AN,D·OR·INVERT Gates

c.n

General Description

Absolute Maximum Ratings

This device'contains two independent combinations of
gates each of which performs the logic AND-ORiNVERT function.

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

7V
5.5V
-65·Ct0150·C

Note 1:, The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

not be operated at these limits, The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings, The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual-In-Line Package

V=AB+CD
Inputs

.,

.,

"

C2

D'

y,

A

B

C

D

V

H

H

X

X

X

X

L
L
H

H
All other
combinations

H

H = High logic Level
L= Low Logic Level
X = Either Low or High Logic Level

.N.

TUF/6454-1

DM54S51 (J)

Output

DM74S51'(N)

5-35

Recommended Operating Conditions
Sym

DM54S51

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

DM74S51

Min

Nom

Max

I\ftin

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units
V

2

V

Low Level Input
Voltage

0.8

0.8

V

10H

High Level Output
Current

-1

-1

mA

10L

Low Level Output
Current

20

20

mA

TA

.Free Air Operating
Temperature

70

·C

-

-55

125

0

Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Sym

Parameter

Min

Typ
(Note 1)

DM54

.2.5

3.4

DM74

2.7

3.4

Conditions

VI

Input Clamp Voltage

Vcc=Min, 11= -18 mA

VOH

High Level Output
Voltage

Vcc=Min
10H=Max
VIL=Max

VOL

Low Level Output
Voltage

Vcc = Min, 10L = Max
VIH=Min

II

Input CiJrrent@Max
Input Voltage

IIH

Max
-1.2

Units
V
V

i

0.5

V

Vcc=Max, VI = 5.5V

1

mA

High Level Input
Current

Vcc=Max, VI = 2.7V

50

p.A

IlL

Low Level Input
Current

Vcc=Max', VI = 0.5V

-2

mA

los

Short Circuit
Output Current

Vcc=Max
(Note 2)

-100

mA

ICCH

Supply Current With
Outputs High

ICCL

Supply Current With
Outputs Low

DM54

-40

DM74

-40

-100

Vcc=Max

8.2

17.8

mA

Vcc=Max

14

22

mA

Switching Characteristics

at Vcc=5V and TA=25·C (See Section 1 for Test Waveforms and Output Load)
RL = 28011

Paraineter

CL=15 pF

CL=50 pF

Units

Min

Typ

Max

Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

2

3.5

5.5

3

5

8

ns

tpHL Propagation Delay Time
High to Low Level Output

2

3.5

5.5

3

5.5

8

ns

I

Note 1: All typlcals are at VCC=5V, TA=25'C.
Note 2: Not more than one output should be shorted. at a time, and the duration should not exceed one second.

5·36

r---------------------------------------------------~--------.c

s:
U1

~National

~

en

~ Semiconductor

~

-s:
C

~

DM54S64/DM74S64 4·Wide AND·OR·INVERT Gates

~

General Description

Absolute Maximum Ratings (Note 1)

This device contains a combination of gates which' performs the logic AND-OR-iNVERT function_

Supply Voltage
Input Voltage
Storage Temperature Range

7V
5_5V
- 65 'C to 150 'C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated attheae limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual-In-Line Package

T"

D

1J

C
11

B

K

11

I" I/. .

Y=ABCD+ EF+GHI +JK

v

(nputs
B

C

D

E

F

G

H

I

J

K

Y

H

H

X

X

X
X
X

X
X
X

H

H

X
X

X
X

X
X

X
X

X
X

H

H

H

X
X
X

X
X
X

X

X

X

H

H

L
L
L
L
H

H

...-..

Ali other combinations

I
A

2

E

3

F

4
G

.1'H

I'
1

H = High Logic Level
L = Low Logic Level
X = Either Low or High Logic Level

J:

TLlF/6455·'

DM54S64(J)

Output

H
X X
X X
X X

A

1

,

•

DM74S64(N)

5-37

Recommended Operating Conditions
DM54S64

DM74S64

Sym

Parameter

Vcc

Supply Voltage

VIH

High Level Input .
Voltage

VIL

Low Level Input
Voltage

0.8

0.8

V

10H

High Level Output
Current

-1

-1

mA

IOL

Low Level Output
Current

20

20

mA

TA

Free Air OperB:ting
Temperature

70

·C

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units
V

2

-55

Electrical Characteristics
Sym

Min

125

V

0

over recommended operating free air temperature (unless otherwise noted)

Parameter

Min

Typ
(Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

VI

Input Clamp Voltage

Vcc= Min, II = -18 mA

VOH

High Level Output
Voltage

Vcc=Min
10H =Max
VIL=Max

Max
-1.2

Units
V
V

VOL

Low Level Output
Voltage

Vcc = Min, IOL = Max
VIH = Min

0.5

V

II

Input Current@Max
Input Voltage

Vcc = Max, VI = 5.5V

1

mA

IIH

High Level Input
Current

Vcc=Max, VI=2.7V

50

p.A

IlL

Low Level Input
Current

Vcc;=Max, VI=0.5V

-2

mA

los

Short Circuit
Output Current

.vcc = Max
(Note 2)

-100

mA

ICCH

Supply Current With
Outputs High

Vcc=Max

7

12.5

mA

ICCL

Supply Current With
Outputs Low

Vcc=Max

8.5

16

mA

Switching Characteristics

DM54

-40

DM74

-40

-100

at Vcc=5V and TA =25·C (See Section 1 for Test Waveforms and Output Load)
RL=2BOO

.

Parameter

CL=15pF

CL=50 pF

Units

Min

Typ

Max

Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

2

3.5

5.5

3

5

8

ns

tpHL Propagation Delay Time
High to Low Level Output

2

3.5

5.5

3

5.5

8

ns

Nole 1: All typicals are at VCC=5V. TA=25"C.
Nole 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

5·38

~-----------------------------------------------------------------'C

3:
~

~National

.
~ Semiconductor

rg

en
C

3:
......

c'Q);i

DM54S65/DM74S65 4·Wide AND·OR·INVERT Gates
with Open· Collector Outputs
General Description

Absolute Maximum Ratings

This device contains a combination of gates which performs the logic AND-OR-INVERT function. The opencollector output requires an external pull-up resistor for
proper logical operation.

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

en

(Note 1)
7V

5.5V
7V

"':65'Cto 150'C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

Pull·Up Resistor Equations

not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table. are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

R

MIN=

Where:

Vee (Max) - VOL
IOL -N3 (Ill)
N1 (IOH) =total maximum output high current
for all outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for
all inputs tied to pull-up resistor
N3 (Ill) = total maximum input low currenffor
-all inputs tied to pull-up resistor

Connection Diagram

Function Table

Dual-ln·Line Package
Y -ABCD+EF+GHI +JK

"

13

12

Inputs

Output

A

B

C

D

E

F

G

H

I

J

K

Y

H

H

H

H

X

X

X
X
X

X
X
X

X
X
X

X
X
X

H

H

X
X

X
X

X
X

X
X

X
X

H

H

H

X
X
X

X
X
X

X

X

X

H

H

L
L
L
L
H

All other combinations
H = High Logic Level
L = Low Logic Level

GNo

X = Either Low or High Logic Level

TLlF/6456-1

DM54S65 (J)

DM74S65 (N)

5-39

,

Recommended Operating Conditions
Sym

DM54S65

Parameter

DM74S65

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units

Vee

Supply Voltage

V'H

High Level Input
Voltage

V

V'L

Low Level Input
Voltage

0.8

0.8

V

VOH

High Level Output
Voltage

5.5

5.5

V

IOL

Low Level Output
Current

20

20

mA

TA

Free Air Operating
Temperature

70

·C

2

2

-55

V

a

125

,

Electrical Characteristics

over recommended operating free air temperature (unless otherwise noted)
Conditions

Parameter

V,

Input Clamp Voltage

Vee=Mln,I,= -18 mA

-1.2

V

leEx

High Level Output
Current

Vee = Min, Vo =5.5V
V'L= Max

250

p.A

VOL

Low Level Output
Voltage

Vee = Min, 10L = Max
V'H=Mln

0.5

V

I,

Input Current@Max
Input Voltage

Vee = Max, V,=5.5V

1

mA

I'H

High Level Input
Current

Vee = Max, V,=2.7V

50

- p.A

IlL

Low Level Input
Current

Vee = Max, V,=0.5V

-2

mA

leeH

Supply Current With
Outputs High

Vce= Max

6

11

mA

ICCL

Supply Current With
Outputs Low

Vcc= Max

8.5

16

mA

Switching Characteristics

Min

Typ
(Note 1)

Sym

Max

~

Units

at Vcc = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)

.

RL=2800
CL=15 pF

Parameter

CL=50pF

Units

Min

Typ

Max

Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

2

5

7.5

3

8

12

ns

tpHL Propagation Delay Time
High to Low Level Output

2

5.5

8.5

3

6.5

10

ns

Note

1: All typica's are at VCC=5V, TA=2S·C.
5·40

r------------------------------------------------------------------,c

3:

~Nati.onal

~c

~ Semiconductor

3:

~

DM54S74/DM74S74 Dual Positive-Edge-Triggered
D Flip-Flops with Preset, Clear,
and Complementary Outputs

~

General Description

Absolute Maximum Ratings (Note 1)

This device contains two' independent positive-edgetriggered 0 flip-flops with complementary outputs. The
information on the 0 input is accepted by the flip-flops
on the positil1e going edge of the clock pulse. The triggering occurs at a voltage level and is not directly
related to the transition time of the rising edge of the
clock. The data on the 0 input may be changed while the
clock is low or high without affecting the outputs as
long as the data setup and hold times are not violated. A
low logic level on the preset or clear Inputs will set or
reset the outputs regardless of the logic levels of the
.
other inputs.
.

Supply Voltage
.Input Voltage
Storage Temperature Range

Connection Diagram

Function Table

7V
5.5V
-65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual-In-Line Package
Vex

CLR2

D2

elk 2

PRl

iIz

02

Inputs

CLR 1

01

elK 1

PR'

Outputs

PR

CLR

CLK

D

Q

Q

L
H
L
H
H
H

H
L
L
H
H
H

X
X
X

X
X
X

I
I

H
L

H
L
H'
H
L

L
H
H'
L
H

L

X

00

00

Q1

H; High Logic Level
TL/F/6457·1

DM54S74 (J)
\

DM74S74 (N)

X; Either Low or High Logic Level
L; Low Logic Level

t = Posltjve-going Transition
• = This configuration Is nonstablej that is. it will not persist when either
the preset and/or clear Inputs return to Its Inactive (high) level.
00; The output logic level of 0 before the Indicated input conditions
were established.

5-41

Recommended Operating Conditions
Sym

DM54S74

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

(See Section 1 for Test Waveforms and Output Load)
DM74S74

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units
V
V

2

,-

Vil

Low Level Input
Voltage

IOH

High Leirel Output
Current

IOl

Low Level Output
Current

f ClK -

Clock Frequency (Note 2)

0

110

75

0

fClK

Clock Frequency (Note 3)

0

95

65

0

tw

Pulse Width
(Note 2)

Clock
High

6

6

Clock
, Low

7.3

7.3

Clear
Low

7

7

Preset
Low

7

7

Clock
High

8

8

Clock
Low

9

9

Clear
Low

9

9

Preset
Low

9

9

tsu

Setup Time (Notes 1 and 2)

31

31

ns

tsu

Setup Time (No"tes 1 and 3)

31

31

ns

tH

Input Hold Time (Notes 1 and 2)

21

21

ns

tH

- Input Hold Time (Notes 1 and 3)

21

21

tw

TA

Pulse Width
(Note 3)

Free Air Operating
Temperature

1

-55

0.8

0.8

V

-1

-1

mA

20

20

mA

110

75

MHz

95

65

MHz

125

0

Note 1: The symbol (1) Indicates the rising edge at the clock pulse is used for reference.
Note
Note

2: Cl =15 pF and
3: Cl =50 pF and

RL
RL

=28011.
=2800.

,

5-42

ns

ns

70

ns
DC

Electrical Characteristics

over re,commended operating free air temperature (unless otherwise noted)

,
Sym

Parameter

Min

Typ
(Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

Max
-1.2

Units
V

VI

Input Clamp Voltage

Vcc=Min, 11 = -18 mA

VOH

High Level Output
Voltage

Vcc= Min
10H = Max
VIL=Max
VIH=Min

VOL

Low Level Output
Voltage

Vcc = Min, 10L = Max
VIH = Min, VIL = Max

0.5

V

II

Input Current@Max
Input Voltage

Vcc=Max, VI = 5.5V

1

mA

IIH

High Level Input
Current

Vcc=Max
VI=2.7V

/LA

IlL

Low Level Input
Current

Vcc= Max
VI=2.7V
(Note 4)

D

50

Clear

150

Preset

100

Clock

100

D

-2

Clear

-6

Preset

-4

Icc

Short Circuit
Output Current

Vcc=Max
(Note 2)

Supply Current

Vcc=Max
(Note 3)

DM54

-40

-100'

DM74

-40

-100
30

50

Note 1: Aillypicals are al VCC=5V, TA=25"C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Note 3: Wilh all outputs open, ICC is measured with the Q and

Q outputs high

Note 4: Clear Is lesled with preset high and preset is lesled with clear high.

,

5-43

/LA

-4

Clock
los

V

In turn. At Ihe time of measurement, Ihe clock is grounded.

mA

mA

Switching Characteristics
From
(Input)
To
(Output)

Parameter

'MAX Maximum Clock
Frequency

at Vee = 5V and TA = 25"C (See Section 1 for Test Waveforms and Output Load)

,

RL = 2801l
. C L =15 pF
Min

Typ

75

110

Units

CL=50 pF
Max

Min

Typ

65

95

Max
MHz

tpLH Propagation Delay
Time Low to High
Level Output

Preset
to
a

4

6

6

9

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clear
to

4

6

6

9

ns

. tpHL Propagatio(1 Delay
Time High to Low
Level Output (Clock High)

Preset
to

9

13.5

12

16

ns

tpHL Propagation Delay
Time High to Low
Level Output (Clock Low)

Preset
to

5

8

8

12

ns

tpHL Propagation Delay
Time High to Low
Level Output
(Clock High)

Clear
to
a

9

13.5

12

16

. ns

tpHL Propagation Delay
Time High to Low
Level Output
(Clock Low)

Clear
to
a

5

8

8

12

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
aorO

6

9

8

12

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
aorO

6

9

9

13

ns

Q

0
0
,

.

"

5·44

~--------------------------------------------------------------,c

:s:::

~National

at

ie

~ Semiconductor

c
:s:::

DM54S86/DM74SB,6 Quad 2-lnput Exclusive-OR Gates

General Description

Absolute Maximum Ratings (Note 1)

This device contains four independent gates each of
which performs the logic Exclusive-OR function_

Supply Voltage
Input Voltage
Storage Temperature Range

7V
5_5V
- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed_ The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratlngs_ The "Recommended Operating Conditions" table will
define the conditions for actual device operation_

Connection Diagram

Function Table

Dual-In-Line Package

Y=AeB=AB+AB
B3

A3

Y3

Inputs

B

Y

L
L
H
H

L
H
L
H

L
H
H
L

H = High Logic Leve'
L Low Logic Level

=

7

A1

B1

A2

B2

Y2

GND

TLlF16458·1

DM54S86 (J)

DM74S86 (N)

5-45

Output

A

i

R~commended

Operating Conditions
DM54S86

DM74S86

Sym

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level Input
Voltage

0.8

0.8

10H

High Level Output
Current

-1

-1

mA

10l

Low Level Output
Current

20

20

mA

TA

Free Air Operating
Temperature

70

·C

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units
V

2

-55

125

V

0

,

V

Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Sym

Parameter

Conditions

Min

Typ
(Note 1)

2.5

3.4

2.7

3.4

Max
-1.2

Units

VI

Input Clamp Voltage

Vee=Min, 11= -18 mA

VOH

High Level Output
Voltage

DM54
Vec=Min
10H = Max
DM74
Vll=Max, VIH=Min ,

VOL

Low Level Output
Voltage

Vcc=Min,lol=Max
VIH=Min, Vll=Max

0.5

V

II

Input Current@Max
Input Voltage

Vcc=Max, VI=5.5V

1

mA

IIH

High Level Input
Current

Vee = Max, VI = 2.7V

50

)LA

III

Low Level Input
Current

Vce=Max, VI=0.5V

-2

mA

los

Short Circuit
Output Current

Vce=Max
(Note 2)

mA

ICCH

Supply Current With
Outputs High

Vce= Max
(Note 3)

35

50

mA

ICCl

Supply Current With
Outputs Low

Vec= Max
(Note 4)

50

75

mA

V

DM54

-40

-100

DM74

-40

-100

Not.t: All typlcals are at VCC=5V. TA=25"C.
Note 2: Not more than one output shol,lld be shorted at a time, and the duration

s~ould

nat exceed one second.

Not. 3: ICCH is measured with all outputs open. one input of each gate at 4.5V, and the other Inputs grounded.
Not. 4: ICCl'ls measured with all outputs open and all inputs grounded,

5-46

V

Switching Characteristics
Parameter

t PLH Propagation
Delay Time Low
to High Level
Output
t PHL Propagation
Delay Time High
to Low Level
Output

From
(Input)
to
(Output)

Aor B
to
y

at Vee = 5V and TA

=25°C (See Section 1 for Test Waveforms and Output Load)
RL - 280fl

C L =15pF
Min

Units

CL=50 pF
Typ

Max

10.5

9

14

ns

10

9

13

ns

Typ

Max

7

6.5

Min

.

,

5·47

Nr-----------------~------------------------------------------__,

i

~National

SJ ~ Semiconductor
Q

N
....

i

:i
Q

.

DM54S1121DM74S112 Dual Negative-Edge-Triggered
Master-Slave J-K Flip-Flops with Preset,
.
Clear, and Complementary Outputs
General Description

Absolute Maximum Ratings (Note 1)

This device contains two independent negative·edge·
triggered J·K flip·flops with complementary outputs.
The J and K data Is pro~essed by the flip·flops on the'
falling edge of the clock pulse. The clock triggering oc·
curs at a voltage level and Is not directly related to the
transition time of. the negative going edge of the clock
pulse. Data on the J and K inputs can be changed while
the clock Is high or low without affecting the outputs as
long as setup and hold times are not violated. A low
logic level on the preset or clear inputs will set or reset
the outputs regardless of the logic levels of the other
inputs.

Supply Voltage
Input Voltage
Storage Temperature Range

Connection Diagram

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Dual·ln·line Package
Vee

elK1

&LR1

Kl

&lRZ

Jl

ClK2

PR 1

K2

01

7V
5.5V
- 65·C to 150·C

J2

ii.

Outputs

Inputs
PRZ

oz

02

GND

TL/F/6459·'

DM54S112 (J) DM74S112 (N)

PR

ClR

ClK

J

K

Q

Q

l
H
L
H
H
H
H
H

H
l
L
H
H
H
H
H

X
X
X

X
X

X
X
X

H
l
H*
Qo
H

l
H
H*

1
1
1
·1
H

.x
L
H
L
H
X

L
L
H
H

X

00

L
H
L
Toggle

00

00

=

H High Logic Level
X= Either Low or High Logic Level
L Low Logic Level
I Negative going edge of pulse.

=
=

00 = The output logic level of 0 before the Indicated input conditi~ns
were established .
This configuration Is nonstable; that is, It will not persist when either
the preset andlor clear inputs return to its Inactive (high) level.
Toggle = Each output changes to the complement of Its previous level
on each falling edge of the clock pulse.

•=

5·48

Recommended Operating Conditions
Sym

Parameter.

(See Section 1 for Test Waveforms and Output Load)
DM74S112

DM54S112
Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units
V

Vcc

Supply Voltage

VIH

High Level Input
Voltage

V IL

Low Level Input
Voltage

0.8

0.8

V

IOH

High Level Output
Current

-1

-1

mA

IOL

Low Level Output
Current

20

20

mA

fCLK

Clock Frequency (Note 2)

0

125

80

0

125

80

MHz

fCLK

Clock Frequency (Note 3)

0

80

60

0

80

60

MHz

tw

Pulse Width
(Note 2)

6

2

Clock
High
Clock
Low

tw

Pulse Width
(Note 3)

V

2

6

. 6.5

ns

6.5

Clear
Low

8

8

Preset
Low

8

8

CLock
High

8

8

Clock
Low

8

8

Clear
Low

10

10

Preset
Low

10

10

tsu

Setup Time (Note 1)

31

31

tH

Input Hold ~ime (Note 1)

01

01

TA

Free Air Operating
Temperature

-55

125

Not. 1: The symbol  Indicates the failing edge at the clock pulse Is used for reference.
Note 2: CL=15 pF and RL=280!l.
Not. 3: CL=50 pF and RL=280!l.

5-49

0

ns

ns
ns
70

DC

('\II
.....
..... Electrical 'Characteristics over recommended operating free air temperature (unless otherwise noted)

~

:is

c
N
.....
.....

~

Sym·

Parameter

Min

Typ
(Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

VI

Input Clamp Voltage

Vee= Min,ll= -18 mA

VOH

High Level Output
Voltage

Vee=Min
10H= Max
VIL = Max
VIH = Min

:is

c

Max

Units

-1.2

V
V

VOL

Low Level Output
Voltage

Vee = Min, 10L = Max
VIH = Min, VIL = Max

0.5

V

II

Input Current@Max
Input' Voltage

Vee=Max, VI=5.5V

1

mA

IIH

High Level Input
Current

Vee= Max
VI=2.7V

J, K

50

I'A

Clear

100

Preset

100
100

Clock
IlL

los

Icc

Nole
Note
NotB
Note

Low Level Input
Current

'Vee= Max
VI =0.5V
. (Note 4)

Short Circuit
Output Current

Vee=Max
(Note 2)

Supply Current

Vee=Max
(Note 3)

=

J, K

,

-1.6

Preset

-:-7

Clock

-4

.DM54

-40

-100

DM74

-40

-100
30

50

=

I: All typical. are at Vee 5V, TA 25"e.
2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
3: With all outputs open, ICC is measured with the

a and a outputs high in turn. At the time of measurement, the clock input is grounded.

4: Clear is tested with preset high and preset is tested with clear high.

,

.

5·50

mA

-7

Clear

mA

mA

Switching Characteristics
Parameter

From
(Input)
To
(Output)

fMAX Maximum Clock
Frequency
tpLH Propagation Delay
Time Low to High
Level Output

Preset
to

tpHL Proagation Delay
Time High to Low
Level Output

Preset
to

tpLH Propagation Delay
Time Low to High
Level Output

Clear
to

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to

at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL = 2800
CL=15 pF
Min

Typ

80

125

CL=50 pF
Max

Min

Typ

60

80

Units
Max
MHz

4

7

6

9

ns

5

7

8

12

ns

4

7

6

9

ns

5

7

8

12

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
OorO

4

7

6

9

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
OcrO

5

7

8

12

ns

a
Q

0

a

"

,

5·51

~r------------------------------------------------------------------------'

....

~ ~National

55 ~ Semiconductor

-....
Q

CO)

~

:E
Q

DM54S113/DM74S113 Dual Negative-Edge-Triggered
Master-Slave J-K Flip-Flops with Preset
and Complementary Outputs
.
General Description

Absolute Maximum Ratings

This device contains two independent negative-edgetriggered J-K flip-flops with complementary outputs.
The J and K data is processed by the flip-flops on the
falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the
transition time of the negative going edge of the clock
pulse. Data on the J and K inputs may be changed while
the clock is high or low without affecting·t~e outputs as
long as setup and hold times are not violated. A low
logic level on the preset input will set or reset the outputs regardless of the logic levels of the qther inputs.

Supply Voltage
Input Voltage
Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
-maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

(Note 1)
7V

S.SV
- 6S·C to 1S0·C

Dual-In-Line Package

Inputs

eLK 1

K1

J1

PR 1

01

Outputs

PR

elK

J

K

Q

l
H
H
H
H
H

X

X
l
H

X
l

H

l

Qo

00

L

H
H
X

H
l

H

I
I
I
I
H

H
X

L

Q

L

Toggle
Qo
00

'NO

H = High Logic Level
TLlF/6460·1

DM54S113 (J)

DM74S113 (N)

X = Either Low or High Logic Level
L = Low Logic Level

1 :; :; Negative going edge of pulse.
00 = The output logic level of Q before the indicated input conditions
were established.
.

Toggle = Each output changes to the complement of its previous level
on each falling edge of the clock pulse.

5-52

Recommended Operating Conditions

(See Section 1 for Test Waveforms and Output Load)

DM54S113
Sym

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level Input
Voltage

IOH

High Level Output
Current

IOl

Low Level Output
Current

fClK

Clock Frequency (Note 2)

fClK
tw

tw

DM74S113

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units
V
V

2
0.8

0.8

-1

-1
20

V
mA

20

mA

0

125

80

0

125

80

MHz

Clock Frequency (Note 3)

0

80

60

0

80

60

MHz

Pulse Width
(Note 2)

Clock
High

6

6

Clock
Low

6.5

6.5

Preset
Low

8

8

Clock
High

8

8

Clock
Low

8

8

Preset
Low

10

10

Pulse Width
(Note 3)

tsu

Setup Time (Note 1)

31

31

tH

Input Hold Time (Note 1)

01

01

TA

Free Air Operating
Temperature

-55

125

Not. 1: The symbol  o - .... OA (141

I.......i~

~
,..

IV

~

~

:::E

c
,..

co

~:::E

-

K

0

JCLK O

I.......i I -

....

pb

g
,..

~
,...

~

(51 DA;A

:::E

c

!:) I

--{=D

~~l'R
K
Ot-r-

~

c

v

Oc

(121

.f>

K

(61

-

....

*
~ t[:: r-k-J

:::E

(71 EN ABLE P

VCle (131

,v

c

~

....

....

(11 CLEAR --"

(91lOAO

.

r

..

~:::E

i,..

Fe raCilJ

(41 DA;A

c

,..
co
,..

0t--

~

O~A

....r--"""rI

::J P-

(101 ENAB
TLEI

...

J'o.,

0

JCLKo

I....i l -

....
V

00 (111

i

~

RIPPL

CARR

~

(151

TLlF/6471·2

)( 5160 optJon

5-90

,---------------------~------------------------------------------.c

Logic Diagrams

:s:
U1

(Continued)

~
.....

5161,5163

~

~
(2) C LOCK

~

'"

p-

J

(10) ENABLE T

r--P---{>o-OA

(14)

.....

Q)
.....

or--

~i<
J eLK

l

a

~~

c

:s:
U1
~

'"

V O•

(13)

CJ)

.....

Q)

~

c

:s:
~

.....

+.

R->
1

~

Q)

~N

C

:s:

01--

U1
~

CJ)

JClKal--~,

'--~

Oe

(12)

.....

-:s:
Q)
Co)

c

......

~
.....
Q)
Co)

J
elR

~i<

or-

1J

al'""-'~
OD

(11)

rf

~

,

~~=~; (15)
TLlFJ6471-3

5-91

~
.....
Q)
.....
~

CLR

J

~

) ( S161 option

c

:s:
U1

CJ)

J

~I
P-

9

CJ)

4

NABLE P

J elK a
~~

Q)

c

~
(9) l OAD

.....

or--

R-Ji<

I

CJ)

-:s:

:r

--v'

~

',J.

~.

(1) CLE AR

-:s:c

~
~

. Timing Diagrams
S160, S162 Synchronous Decade Counters
Typical Clear, Preset, Count and Inhibit Sequences

::E

Q

~
.,..

CLEAR----,
8160

~::E

CLEAR
8162

c
~
.,..

LOAD

~::E

..---+---. - - - - - - - - - - - - - DATA {
INPUTS

c
~
.,..

:

D

~::E

r----t--....,-------------.-- - - -- - -- - - - --- - - t - -.. - - - - - - - - - - - - - -

CLOCK---h
8160
CLOCK
8162

Q

ENABLE P

----,-t-~

+-_+_'

ENABLE T _ _ _ _

• 1
.----COUNT----·.-~--INHIBIT

----

CLEAR PRESET
TLlFf6471-4

Sequence:

C1 J Clear outputs to zero
(21 Preset to BCD seven
(3)
(41

Count to eight, nine, zero, one, two, and three

Inhibit

5·92

~------------------------~-------------------------------------------'C

,

Timing Diagrams

3:
en

(Continued)

~
.....

5161,5163 Synchronous Binary Counters'
Typical Clear, Preset, Count and Inhibit Sequences

~
c
s:

CLEAR---"
8161
CLEAR
8163

~.....

LOAO

r--------------

:=-:----I.==============
r

r---+---"T - - - ______ - _. __ _

INPUTS
OATA{

L _____________ _

L _ _ _ _ _ _ _ _ _ _ _ ...:.. _ _
r---+---.,.--------------

CLOCK---M
8161

ENABLE T

OUTPUTS {

:

3:
en

~
.....

-.....
CD

c
3:
.....
~
.....
CD

.....

CLOCK
8163
ENABLE P

~
c

---t-""""'+"
---t-""""'+"

-t-+-t---'

QD

RIPPLEO~~~~~ ----1--+1.5
12-+1""3-1-4-.......
I----COUNT----,·I-INHIBIT---CLEAR PRESET
TLlF/6471·5

Sequence:
(1)

Clear outputs to zero

(2)

Preset to binary twelve

(3)
14)

Count to thirteen, fourteen, fifteen, zero, one, and two
Inhibit

5·93

Parameter Measurement Information

SWITCHING TIME WAVEFORMS

~

CLOCK
INPUT
OV
IpLH

tpHL

(MEASURE AT tN+l)
OUTPUT

(MEASURE AT tN+2)

V OH

QA
VOL

V OH

OUTPUT
QB
VOL

OUTPUT

Dc

VOH

VOL

V OH

OUTPUT
Qo
VOL

RIPPLE
CARRY
OUTPUT

V OH

VOL
TLlFf6471·6

NoleA: The input pulses are supplied by generators having Ihe following characteristics: PRRs 1 MHz,dutycycle,,50%,ZOUT=500. For5160through 5163,
t r ,,2.5 ns, tf",2.5 ns. Vary PRR to measure fMAX.
•
Nole B: Outputs QO and carry are tested at tn + 10 for 5160, 5162 and at tn + 16 for 5161, 5163 where tn is the bit time when all outputs are low.
Nole C: For5160 through 5163, VREF= 1.5V.

5-94

~----------------------------------------------------------------------------,c

Parameter Measurement Information

:s::

(Continued)

~....

g

-:s::c
SWITCHING TIME WAVEFORMS
CLOCK INPUT l.OV - - - - - - - " " " " \
l60AI
l61A OV:::~------~::::4=~~~~~~~_ _ _ _ _~___
l.OV
CLEAR
INPUT
OV
l.OV
LOAD
INPUT
OV
l.OV
DATA INPUTS
A, B, C, AND 0
OV
a OUTPUTS VOH
l61A
aAAND aD OUTPUTS
l60A VOL
VOH
DB AND Dc OUTPUTS
l60A
VOL
l.OV
ENABLE P OR
ENABLE T
OV
VOH

~....

~
c

:s::

~
....
....

-:s::
Q)

c

....~

....

Q)

c

s:

....~
~

-s:
C

......

~

CARRY

....

CJ)

VOL
. CLOCK INPUT l.OV
l62AI
l6lA
a OUTPUTS VOH
l6lA!
aAAND aD OUTPUTS
l62AI VOL
VOH
aB AND Dc OUTPUTS
l62Ai
VOL

Q)

~I\)

C

s:
C1I

~~U~!! !t:!:2...!!.R~+J!.

~
....

-s:
Q)
Co)

C

TLlF/6471·7

Note A: The input pulses are supplied by generators having the following characteristics: PRRs 1 MHz, dutycycle:sSO%, ZOUT .... SOO. ForS160throughS163,

t r ",2.5 ns, tf",2.5 ns. Vary PRR to measure fMAX.

~....

Q)

Note B: ~nable P and enable T setup times are measured at tn +0.

Co)

Note C: For 5160 through 5163, VREF = 1.5V.

5·95

~r-----------------------------~-----------------------------------------'

r-.
.,...

~National

~:!E ~ Semiconductor

-.,... DM54S174/DM74S174, DM54S175/DM74S175
c

~

r-.

CIJ

;1;,

Hex/Quad 0 Flip-Flops with Clear

:!E

c

it
.,...
~
r-.
:!E

c

~

r-.
.,...

CIJ

;1;

:!E

c

General Description
These positive-edge-triggered flip-flops utilize TTL circuitry
to implement Ootype flip-flop logic, All have a direct clear
input, and the quad (175) versions feature complementary
outputs from each flip-flop,
Information at the 0 inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going
edge of the clock pulse_ Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse, When the clock input
is at either the high or low level, the 0 input signal has no
effect at the output.

• Applications include:
Buffer I storage registers
Shift registers
Pattern generators
• Typical clock frequency 110 MHz
• Typical power dissipation per flip-flop 75 mW

Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage

7V
5,5V
-65·Cto150·C

Storage Temperature Range

Features

Note 1: The "Absolute Maximum Ratings" are those values beyond

• S174 contain six flip-flops with single-rail outputs,
• S 175 contain four flip-flops with double-rail outputs,
• Buffered clock' and direct clear inputs

which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will

• Individual data input to each flip-flop

define the conditions for actual device operation.

Connection Diagrams
Dual-In-Line Package

Dual-In-Line Package
Vee

as

06

05

05

04

04

CLOCK

Vee

Q4

04

04

03

03

CLEAR

01

01

02

02

03

Q3

GND

CLEAR

01

'(51

01

02

52

CLOCK

02

GND

TLlF/6472-2

TLlFI6472-1,

54S174(J)

Q3

74S174(N)

54S175 (J)

74S175(N)

Function Table (Each Flip-Flop)
Outputs

Inputs
Clear

Clock

0

a

at

L
H
H
H

x

X
H
L
X

L
H
L
Qo

H
L
H

t
t

L

00

.

H = High Level (steady state)
L = Low Level (steady stale)
x = Don't Care
= Transition from low to high level

t

00 = The level of Q before the indicated steadY'state input conditions were
established.
t = $175 only

5-96

c

Recommended Operating Conditions

DM545174, 5175
5ym

Parameter

Vcc

Supply Voltage

V 1H

High Level Input
Voltage

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

O.B

O.B

High Level Output
Current

IOl

Low Level Output
Current

fClK

Clock' Frequency (Note 1)

0

110

75

0

fClK

Clock Frequency (Note 2)

0

90

65

0

tw

Pulse Width
(Note 1)

Clock

7

7

Clear

10

10

Clock

9

9

Clear

12

12

tREl

TA

-1

-1

20

5

Data Setup Time
(Note 2)

7

7

Data Hold Time
(Note 1)

3

3

Data Hold Time
(Note 2)

5

5

Clear Release Time
(Note 1)

5

5

Clear Release Time
(Note 2)

7

7

Nole 1: Cl
Nola 2: Cl

V

-c:s:
~

~

V

....
.......

mA

20

mA

110

75

MHz

90

65

MHz

~~

c

:s:
U'I
in....
.......

-:s:
U'I

Data Setup Time
(Note 1)

Free Air Operating
Temperature

...........

(J)

IOH

tH

Units

V

2

Low Level Input
Voltage

tsu

~

(J)

DM745174,5175

V1l

Pulse Width
(Note 2)

:s:

(See Section 1 for Test Waveforms and Output'Load)

ns

ns

5

125

=15 pF and Rl =2800.
=50 pF and Rl =2800.

-

5·97

0

~

....
.......

(J)

U'I

-

-55

c

ns

ns

70

DC

Electrical Characteristics
Sym

over recommended operating free air temperature (unless otherwise noted)

Parameter

Min

Typ
(Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

Units

Max

V

VI

Input Clamp Voltage

Vcc= Min, 11= -18 mA

VOH

High Level Output
Voltage

Vcc= Min
10H= Max
VIL=Max
VIH=Min

VOL

Low Level Output
Voltage

Vcc=Min,IOL=Max
V IH = Min, VIL = Max

0.5

V

II

Input Current@Max
Input Voltage

Vcc = Max, VI = 5.5V

1

mA

IIH

High Level Input
Current

Vcc=Max, VI = 2.7V

50

,.A

IlL

Low Level Input
Current

Vcc = Max, VI = 0.5V

Short Circuit
Output Current,

,Vcc=Max
(Note 2)

Icc

Supply Current
(S174)

Vcc: Max
(Note 3)

90

144

mA

Icc

Supply Current
(S175)

Vcc=Max
(Note 3)

60

96

mA

los

V

-2

mA
mA

,

Switching Characteristics
Parameter

-1.2

-40

-100

DM74

-40

-100

at Vcc=5V and TA =25·C (See Section 1 for Test Waveforms and Output Load)

From
(Input)
To
(Output)'

RL = 280{l

,

f MAX Maximum Clock
Frequency

DM54

C L =50 pF

CL=15 pF
Min

Typ

75

110

Max

Min

Typ

65

90

Units
Max
'MHz

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
Output

8

12

10

15

ns

tpHL Propagation Delay
-Time
High to Low

Clock
to
Output

12

17

14

21

ns

tpLH Propagation Delay
Time Low to High
Level Output (S1'75 Only)

Clear
to

10

15

12

18

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to

13

22

15

23

ns

Level Output

Q

Q

Nole 1: All typicals are at VCC=5V. TA=25·C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Nole 3: With all outputs open and 4.5V applied to all DATA and CLEAR inputs, ICC is measured after a momentary ground, Ihen 4.5V applied 10 the CLOCK
mput.

5-98

c
3:

Logic Diagrams

CII
.1:10

....
.....

C/J

.1:10

C

5174
D.

131

3:

.....
.1:10

5175
1'1

D.

Q.

141

1'1

131

Q.

....
.....
C/J

~.1:10

ill

C

3:

CII
D.

D.

Q'

151

171

Q.

(81

il.

~
....

.....
CII

C

3:
.....

Q3

D3

D3

1"1

('01

Q3

~
....

.....
CII

ila

('3)

D4

Q4

D4

('5)

Q4

(9)

CLOCK

il4

(.)

CLEAR

Q5

D5

De

~~---++-I

CLOCK "'--'--'r ......~

CLEAR

TUF/6472-4

Q8

I

o-....qL:>o---....- - J
TUF/6472·3

5-99

,...

,...

ex)

~ ~Nationai
Semiconductor

:E

-c,...,... DM545181/DM745181 Arithmetic Logic
ex)

~ Unit/Function Generators
:E
c

.Features

.General Description
These arithmetic logic units (ALU) I function generators perform 16 binary arithmetic operations on two 4-bit words, tiS
shown in Tables 1 and 2. These operations are selected by
the four function-select lines (SO, S I, S2, S3) and include
addition, subtraction, decrement; and straight transfer.
When performing arithmetic manipulations, the internal carries must be enabled by applying a low-level voltage to the
mode control input (M). A full carry look-ahead scheme is
available in these devices for fast, simultaneous carry generation by means of two cascade-outputs (P and G) for the
four bits in the package. When used in conjunction with the
DM54S162/DM74S182 full carry look-ahead circuits, highspeed arithmetic operations·can be performed. The typical
addition times shown below illustrate how lillie time is required for addition of longer words, when full carry lookahead is employed. The method of cascading 182 circuits
with these ALU's to provide multi-level full carry look-ahead
is illustrated under typical applicat.ions data for the
DM54St82/DM74S182.
(Continued)

I

• Arithmetic operating modes:
Addition
Subtraction
Shift operand A one position
Magnitude comparison
Plus twelve other arithmetic operations
• Logic function modes:
EXCLUSIVE-OR
Comparator
AND,NAND,OR,NOR
Plus ten other logiC operations
• Full look-ahead for high-speed operations on long words

Absolute Maximum Ratings

(Note 1)

Supply VoltaQe

7V

Input Voltage

5.5V

Output Voltage (A = H Output)
Storage Temperature Range

5.5V
-65·Cto150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Pin DeSignations

Dual-In-Line Package
tNPUTS

,

i

VCC AI

i24

Bl

23

A2
22

A3 B3

B2
21

20

19

OUTPUTS

G C n+4 P A=B F3
17

18

16

15 14

1

,

2
AO

3
S3

4

5

S2 SI
INPUTS

6

7

SO Cn

8
M

9

10

Fa 'Fl

".

11 J12
F2 , GND

Pin Nos_

Function

19,21,23,2

Word A Inputs

83,82,81,80

18,20,22,1

Word 8 Inputs

S3, S2,Sl, SO

3,4,5,6

Function-Select
Inputs

Cn

7

Inv. Carry Input

M

B

Mode Control
Input

F3,F2,Fl,FO

13, II, 10,9

Function Outputs

A=8

14

Comparator Output

P

15

Carry Propagate
Output

Cn+4

16

Inv. Carry Output

G

17

Carry Generate
Output

VCC

24

Supply Voltage

GND

12

Ground

OUTPUTS
TLlF/6473·1

545181 (J)

Desi!lnation
A3,A2,Al,AO

13

po-

r<

BO

,

;

745181 (N)
5-100

c

General Description

s:

(Continued)

If high sj:>eed is not important, a ripple-carry input (C n) and
a ripple-carry output (C n+4) are available. However, the
ripple· carry delay has also been minimized so that
arithmetic manipulations for small word lengths can be performed without external circuitry.

magnitude information. Again, the ALU should be placed in
the subtract mode by placing the function select inputs 53,
52,51, SO at L, H, H, L, respectively.
These circuits have been designed to not only incorporate
all of the designer's requirements for arithmetic operations,
but also to provide 16 possible functions of two Boolean
variables without the use of external circuitry. These logic
functions are selected by use of the four function-select inputs (SO, 51, 52, 53) with the mode-control input (M) at a
high level to disable the internal carry. The 16 logic functions are detailed in Tables 1 and 2 and include exclusiveOR, NAND, AND, NOR, and OR functions.

These circuits will accommodaie active-high or active-low
data, if the pin designations are interpreted as shown
below.
Subtraction is accomplished by l's complement addition
where the l's complement of the subtrahend is generated
internally. The resultant output is A-B-l, which requires
an end-around or forced carry to provide A-B.

ALU SIGNAL DESIGNATIONS

The 5181 can also be utilized as a comparator. The A = 8
output is internally decoded from the function outputs (FO,
F 1, F2, F3) so that when two words of equal magnitude are
applied at the A and 8 inputa, it will assume a high level to
indicate equality (A = B). The ALU should be in the subtract
mode with Cn = H when performing this comparison. The
A = 8 output is open-collector so that it can be wire-AND
connected to give a comparison for more than four bits. The
carry output (C n+4) can also be used to supply relative

Number
of
Bits

The DM54S1811DM745181 can be used with the signal
designations of either Figure 1 or Figure 2.
The logic functions and arithmetic operations obtained
with signal designations as In Figure 1 are given In Table I;
those obtained with the signal designations of Figure 2
are given in Table II.

Package Count
Typical
Addition Times

1 to 4
5 to 8
9to 16
17 to 64

20
30
30
50

Arithmetlc/
Logic Units

Look Ahead
Carry Generators

Carry Method
Between
ALU's

1
2
3 or 4
5 to 16

0
0
1
2·to 5

None
Ripple
Full Look-Ahead
Full Look-Ahead

ns
ns
ns
ns

,Pin Number

2

Active-High Data (Table I)
Active-Low Data (Table II)

1

23 22 21 20 19 18

9

10 11 13

7

16

15 17

AO BO Al Bl A2 B2 A3 B3 FO Fl F2 F3 Cn Cn+4 X
AO BO Al Bl A2 82 A3 B3 FO Fl F2 F3 Cn Cn+4 p

Input
en

Output
Cn+4

H
H
L
L

H
L
H
L

Active-High Data Active-Low Data
(Figure 1)
(Figure 2)
A=:;8
A>8
A<8
A~8

5-101

A~B

AB
A=:;B

y
G

~...

-...
CD

C

s:

~...

...

CD

General Description
12) 11)

(7)-r<

123)(22) (21) (20) (19) (18)

.,

Table I

I I .,II II II
.2 .2

AO 80

Cn

i-"FO

Fl

F2

F3

A=B -114)
Cn +4

(1

113)/14)
YO XO

Y

x

'5)
+
(1t(Y) (r T

(ll,' 1,) (1~)

It

. Active High Data

A3 83

8181

18)-

(Continued)

)

Il)

11'

TT
Yl

Xl

Y2 X2

V3 X3

X 1--17)

11~

8182

Cn
Cn+r.

,XI·

Cn+y

Cn+z

(X)

11

Yl--ll0)

TL/F/6473-2

Figure 1

Selection

M=H
Logic
S3 S2 Sl SO Functions

M = L; Arithmetic OperatIons
C n = H (no carry)

L
H
L
H
L
H

F=A
F"'A+B
F "'AB
F=O
F = AB
F=S

H

L

F=A$B F = A Minus B Minus 1

H
L

H F = AS
F = ASMi~uS 1
L F=A+B F '" A Plus AB

F = AS
F = A Plus AB Plus 1

L

L

H F=A$B F = A Plus B

F = A Plus B Plus 1

L
L
H
H
H
H

H
H
L
L
H
H

L
H
L
H
L
H

L
L
L
L
L
L

L
L
L
L
H
H

L
L
H
H
L
L

L

H

L
H

H
L

H
H
H
H
H
H
H

F=B
F = AB
F= 1
F=A+S
F=A+B
F=A'

F=A
F=A+B
F"'A+S
F '" Minus 1 (2's Compl)
F '" A Plus AS
F '" (A + B) Plus AS

Cn = L (with carry)

F
F
F
F
F
F

=
=
=
=
=
=

(A + S) Plus AB
AB Minus 1
A Plus A'
(A + B) Plus A
(A + S) Plus A
A Minus 1

F=
F=
F=
F'"
F '"
F=

A Plus 1
(A + B) Plus 1
(A + S) Plus 1
Zero
A Plus AS Plus 1
(A + B) Plus AS Plus 1

F = A Minus B

F = (A + S) Plus AB Plus 1
F = AB
F = A Plus A Plus 1
F = (A + B) Plus A Plus 1
F = (A + S) Plus A Plus 1
F=A

.. Each bit is shilted to the next more significant position.

TT (7)CYI., 'X)Cr) (I)Cr
AD SO

Al

A2 .2

Table II

l

Active Low Data

A3 83

17)- ...... Cn

8181

18)- - M
FO

Fl

F2

F3 Cn+4

A=B -114)
G

P

,l) (~) (Xl J.) l,+5)

(!I

tt-)T T
3

Itlt

GO PO

Gl Pl

G2 P2

TT
G3 P3
P~17)

liii

Cn

8182

+

+

Cn x

Cn y

Cn+z

(1t

),1

(!)

G ~ll0)

TL/F/6473·3

Figure 2

-

M = L; Arithmetic Operations

Selection

M=H
Logic
S3 S2 Sl SO Functions

Cn = L (no carry)

F=A
F = AB
F=A+B
F = 1
F=A+B
F=S

H

L

F=A$B F = A Minus B Minus 1

H
L

H F=A+S F=A+S
F = A Plus (A + B)
L F = AB

F = (A + S) Plus 1
F = A Plus (A + B) Plus 1

L

L

H F=A$B F = A Plus B

F = A Plus B Plus 1

L
L
H
H
H
H

H
H
L
L
H
H

L
H
L
H
L
H

L
L
L
L
H
H

L
L
H
H
L
L

L

H

L
H

H
L

H
H
H
H
H
H
H

F=B
F=A+B
F=O
F = AS
F = AB
F=A

F
F
F
F
F
F

=
=
=
=
=
=

A Minus 1
AB Minus 1
AS Minus 1
Minus 1 (2's Compl)
A Plus (A + S)
AB Plus (A + B)

Cn = H (with carry)

L
H
L
H
L
H

L
L
L
L
L
L

F = AS Plus (A
F=A+B
F = A Plus A'
F = AB Plus A
F = AS Plus A
F=A

.. Each bit is shifted to the next more significant position.

5·102

+ B)

F=A
F = AB
F = AS
F = Zero
F 'j' A Plus (A + S) Plus 1
F = AB Plus (A + S) Plus 1
F = A Minus B

F=
F=
F=
F=
F=
F=

AS Plus (A + B) Plus 1
(A + B) Plus 1
A Plus A Plus 1
AB Plus A Plus 1
AS Plus A Plus 1
A Plus 1

c

s::

Recommended Operating Conditions
Sym
Vee

Parameter

UI

DM54S181

DM74S181

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Supply Voltage

Units
V

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

0.8

0.8

V

VOH

High Level Output
Voltage (A = 8 Output)

5.5.

5.5

V

10H

High Level Output
Current (All Except A = 8)

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

Electrical Characteristics
Sym

Parameter

2

V

2

-1

-1

20
-55

125

0

mA

20

mA

70

DC

over recommended operating free air temperature (unless otherwise noted)
Conditions

Min

Typ
(Note 1)

Max

. Units

VI

Input Clamp Voltage

Vee=Min, 11= -18 mA

leEx

High Level Output
Current (A = B Output)

Vee=Min, Vo=5.5V
VIL = Max, VIH = Min

VOH

High Level Output·
Voltage (All Except A = 8)

Vee= Min
10H= Max
VIL=Max
V1H = Min

VOL

Low Level Output
Voltage

Vee=Min,loL=Max
V1H = Min, VIL = Max

0.5

V

II

Input Current@Max
Input Voltage

Vee = Max, VI = 5.5V

1

mA

IIH

High Level Input
Current

Vee= Max
VI=2.7V

p.A

DM54

2.5

3.4

DM74

2.7

3.4

Low Level Input
Current

Vee=Max
V1=0.5V

los

Short Circuit
Output Current
(Any Output Except A = 8)

Vee = Max
(Note 2)

lee

Supply Current

Vee=Max
(Note 3)

V

250

p.A
V

Mode

50

A or 8

150

S

200

Carry
IlL

-1.2

250

Mode

-2

A or 8

-6

S

-8

Carry

-10
-40

120

mA

-100

mA

220

mA

Note 1: All typicals are at Vee = 5V, TA = 25'e.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: ICC is measured for the following conditions: A. SOthrough 53, M, and A inputs at 4.5V, all other inputs grounded and all outputs open. B. SO through
83 and M inputs at 4.5V, all other inputs grounded and all outputs open:'

5·103

t;;
.....

-s::
CO

.....
C

....a

t;;
.....

.....
CO

.,...
co
.,...

~

:E
c
.,...
co
.,...

~:E
c

Switching Characteristics

Vcc = 5 V, TA = 25°C (See Section 1 for Test Waveforms and Output Load)
DM54174
5181

Sym

Parameter

From
(Input)

To
(Output)

Conditions

RL = 280 Il, CL = 15 pF RL= 2801l,CL= 50pF Units
Typ

Max

10.5

9

14

7

10.5

9

14

M = 0 V, SO =
S3 = 4.5 V
SI=S2=OV
(SUM mode)

12.5

18.5

14.5

22

12.5

18.5

14.5

22

M = 0 V, SO =
S3 = 0 V
SI =S2=4.5V
(DIFF mode)

15.5

23

17.5

27

15.5

23

17.5

27

M = OV
(SUM or

7

12

9

14

DIFF mode)

7

12

9

14

M = 0 V, SO =
S3 = 4.5 V
SI =S2=OV
(SUM mode)

8

12

10

15

7.5

12

10

15

M = OV, SO =
S3 = 0 V
SI =S2=4.5V
(DIFF mode)

10.5

15

12.5

19

10.5

15

13

20

M = 0 V, SO =
S3 = 4.5 V
SI = S2 = 0 V
(SUM mode)

7.5

12

9:5

15

7.5

12

10

15

M = OV, SO =
S3 = 0 V
SI =S2=4.5V
(DIFF mode)

10.5

15

12.5

19

10.5

15

13

20

M = 0 V, SO =
S3 = 4.5 V
SI = S2 = 0 V
(SUM mode)

11

16.5

13

20

11

16.5

13

20

M = OV, SO =
S3 = OV
SI =S2=4.5V
(DIFF mode)

14

20

16

24

'14

22

16

24

14

20

16

24

14

22

16

24

15

23

17

26

20

30

22

33

Min
tPLH

Propagation Delay Time,
Low-to-High Level Output

tPHL

Propagation Delay Time,
High-to-Low Level Output

tPLH

Propagation Delay Time,
Low-to-High Level Output

tPHL

Propagation Delay Time,
High-to-I.,ow Level Output

tPLH

Propagation Delay Time,
Low-to-High Level Output

..

tPHL

Propagation Delay Time,
High-to-Low Level Output

tPLH

Propagation Delay Time,
Low-to-High Level Output

tPHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tPLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tPHL

Propagation Delay Time,
High-to-Low Level Output

tPLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low L,evel Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tPLH

Propagation Delay Time,
Low-to-High Level Output

tPHL

Propagation Delay Time,
High-to-Low Level Output

tPLH

Propagation Delay Time,
Low-to-High Level Output

tPHL

Propagation Delay Time,
High-to-Low Level Output

Cn

Cn+4

Any A
or B

Cn+4

Cn

Any F

Any A
or B

G

Any A
orB

G

Any A
or B

P

.Any A
orB

P

Ai or Bi

Fi

Ai or Bi

Any A
or B

Max

7

Min

ns

Cn+4

Any A
or B

Ai or Bi

Typ

Fi

Fi

A=B

M = 4.5 V
(logic mode)
M = OV, SO =
S3 = OV
SI =S2=4.5V
(DIFF mode)

5-104

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Parameter Measurement Information

Logic Mode Test Table
Function Inputs: S1 = S2 = M = 4.5 V, SO

Parameter

tPLH
tPHl
tPlH

Input
Under.
Test

Other Input
Same Bit

= 53 = 0 V

Other Data Inputs

Apply
GND

Apply
4.5V

Apply
GND

Ai

Bi

None

None

Remaining
AandB,C n

Fi

Out·ol·Phase

Bi

Ai

None

None

Remaining
AandB,C n

Fi

Out·ol·Pl1ase

SUM Mode Test Table
Function Inputs: SO = 53 = 4.5 V, 51 = S2

tPlH
tPHl
tPlH

Input
Under
Test

Other Input
Same Bit

tPHl
tPlH

Other Data Inputs

tPHl
tPlH
tpHl
tplH
tpHl
tPlH
tpHl
tPlH
tPHl

Output
Under
Test

Output
Waveform

Apply
GND

Apply
4.5 V

Apply
GND

Ai

BI

None

Remaining
A and B

Cn

Fi

In·Phase

Bi

Ai

None

Remaining
A and B

Cn

Fi

In·Phase

Ai

Bi

None

None

Remaining
AandB,C n

P

In·Phase

Bi

Ai

None

None

Remaining
Aand B. Cn

P

In-Phase

Ai

None

Bi

Remaining Remaining
B
A,C n

G

In-Phase

Bi

None

Ai

Remaining Remaining
B
A,C n

G

In-Phase

Cn

None

None

Any F
orCn+4

In-Phase

'Ai

None

Bi

Remaining Remaining
B
A,C n

Cn+4

Out-ol-Phase

Bi

None

Ai

Remaining Remaining
. Cn+4
B
A.C n

Out·ol-Phase

tPHl
tplH

=M =0 V

Apply'
4.5 V

tPHl
tPlH

Output
Waveform

Apply
4.5V

tPHl

Parameter

Output
Under
Test

All
A

5·105

All
B

~ .-------------------~--------~~----------------------~------~--------------------~--,

co

~
.....

Parameter Measurement Information

(Continued)

:iiE

o

'j)'jf'F Mode Test Table
Function Inputs: S1 = S2 = 4.5 V, SO = S3 = M = 0 V

~

CO
~

~

:iiE

o

Perameter

tPLH

Input
Under
Test

Other Input
Same Bit

IPLH

Ai

None

Bi

Remaining Remaining
A
B, Cn •

Fi

In·Phase

Bi

Ai

None

Remaining Remaining
A
B,C n

Fi

Out-ol-Phase

Ai

None

Bi

None

Remaining
AandB,C n

P

In· Phase

Bi

Ai

None

None

Remaining
AandB,C n

P

Out·ol·Phase

Ai

Bi

None

None

F.lemaining
AandB, Cn

G

In·Phase

Bi

None

Ai

None

Remaining
AandB,C n

G

Out'ol'Phase

Ai

None

Bi

Remaining Remaining
B,C n
A

A=B

In·Phase

Bi

Ai

None

Remaining Remaining
B,C n
A

A=B

Out·ol·Phase

Cn

None

None

All
A and B

None

Cn+4
or any F

In·Phase

Ai

Bi

None

None

Remaining
A,B,C n

Cn+4

Oul·ol·Phase

Bi

None

Ai

None

Remaining
A,B,C n

Cn+4

In-Phase

IPHL
tPLH
tpHL
tPLH
IPHL
tPLH
tPHL
IPLH
tPHL
tpU-l
IPHL
tPLH
tPHL
tPLH
tpHL
tpLH
IpHL

5·106

Apply
GND

Output
Waveform

Apply
GND

tPHL

Apply
4.5 V

Output
Under
Test

Apply
4.5 V

tPHL
tPLH

Other Data Inputs

c

3:

Logic Diagram

U1
~

en
....

-c....
CD

13)
3 14)

5 2 15)

~

16)

3118)

K

3
119)

2_
120)

r-o....l4)

B
(9)

C

, ( 6 ) OUTPUT W

EJ--J--

A

~l

~~~OUTPUTY

FI--fl:

~

07 (12)

SELECT
(BINARY)

~

B
C
C

..

TLfF16480·2

-

5-135

M.------------------------------------------------------------------------.

~ ~National
~ Semiconductor

!i

~ DM54S253/DM74S253
~ Dual TRI-STATE® 1 of 4 Line -Data Selectors/Multiplexers

.~

c

• High lan-out totem-pole outputs

General Description
Each 01 these Schottky-clamped data selectors I
multiplexers contains inverters and drivers to supply lully
complementary, on-chip, binary decoding data selection to
the AND-OR gates_ Separate output control inputs are provided lor each 01 the two lour-line sections.

• Typical propagation delay
From data io output 6 ns
From select to output 12 ns
• Typical power dissipation 275 mW

Absolute Maximum Ratings (Note 1)

The TRI-STATE outputs can interlace directly with data
lines 01 bus-organized systems. With all but one 01 the common outputs disabled (at a high impedance state), the low
impedance 01 the single enabled output will drive the bus
line to a high or low logic level.

Supply Voltage
Input Voltage .
Storage Temperature Range

Features

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should

• TRI-STATE version 01 5153 with same pin-out

not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will

•
•
•
•

Schottky-diode-clamped transistors
Permits multiplexing Irom N lines to 1 line
Perlorms parallel-to-serial conversion
Strobe I output control

7V
5.5V
-65·CtoI50·C

define the conditions for actual device operatipn.

Logic Diagram

Connection Diagram
Dual-In-Line Package

OUTPUT

(1)

:::::-IL::::--:--------------t;~~~
1C2'--------------i-t;~~~

1C3'(~3~)------;:::::4=~~~~
SELECT {
OUTPUT
CONTROL
Gl

DATA INPUTS
TLlF/6481·1

545253 (J)

74S253(N)

Function Table
Select
Inputs

B

A

X

X

X

X

l
l
l
l
H
H
H
H

l
l
H
H
L
.l
H
H

l
H

X
X

X
X
X
X
X
X

l
H

CD

Cl

X
X
X
X

DATA21~::

(13)

2C2-----""1*=t:t:t.......,

Data Input.

Output
Control

Output

C2

C3

G

y

X

l
H

X
X
X
X
X
X
X

X
X

l
H

H
l
l
l
L
l
l
l
l

l
H
l
H
l
H
l
H

X

X
X
X

2C3,--------------i=~~~~

OUTPUT (15)
CONTROLG2

Z
TLlFJ6481·2

Address inputs A and B are common to both sections.
H = High Level, L, = Low Level, X = Don't Care. Z = High Impedance

5-136

c

s::
en

Recpmmended Operating Conditions

~

Sym

DM54S253

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

DM74S253

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

Units
V
V

Low Level Input
Voltage

10H

High Level Output
Current

-2

-6.5

mA

10L

Low Level Output
Current

20

20

mA

TA

Free Air Operating
Temperature

70

·C

0.8

-55

Electrical Characteristics
Parameter

0.8

125

0

V

over recommended operating free air temperature (unless otherwise noted)
Min

Conditions

Typ
(Note 1)

Max
-1.2

Units
V

VI

Input Clamp Voltage

Vee = Min, 11= -18 rnA

VOH

High Level Output
Voltage

Vee = Min
10H=Max
Vll=Max
VIH = Min

VOL

Low Level Output
Voltage

Vee = Min, 10L = Max
VIH = Min, VIL = Max

0.5

V

II

Input Current@Max
Input Voltage

Vee=Max, VI=5.5V

1

rnA

IIH

High Level Input
Current

Vee = Max, VI = 2.7V

50

p.A

III

Low Level Input
Current'

Vee = Max, VI = 0.5V

-2

rnA

10ZH

Off·State Output
Current with High
Level Output
Voltage Applied

Vee = Max, Vo= 2.4V
VIH = Min, VIL = Max

50

p.A

10Zl

Off·State Output
Current with Low
Level Output
Voltage Applied

Vee=Max, Vo=0.5V
VIH=Min, VIL=Max

-50

p.A

los

Short Circuit
Output Current

mA

Icc

Note 1:

-s::
w
C

......
~

en

VIL

Sym

~

en

Vee=Max
.(Note 2)

Supply Current

DM54

2.4

3.4

DM74

2.4

3.2

V

DM54

-40

-100

DM74

-40

-100

Vee= Max (Note 3)

I

All typicals are at Vee=5V, TA=25"e.

Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: ICC is measured with all outputs open.

5·137

55

70

rnA

~

w

Switching Characteristics
Parameter

From
(Input)
To
(Output)

at Vcc "= 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)

RL =2801l
C L =15 pF
Min

C L =50 pF

Typ

Max

Min

Units

Typ

Max

t pLH Propagation Delay
Time Low to High
Level Output

Data
to
V

6

9

8

12

ns

tpHL Propagation Delay
Time High to Low
Level Output

Data
to
V

6

9"

8

12

ns

tpLH Propagation Delay
Time Low to High
Level Output

Select
to
V

12

18

14

21

ns

tpHL Propagation Delay
Time High to Low
Level Output

Select
to
V

12

18

14

21

ns

tpZH Output
Enable Time to
High Level
Output

Output
Control
toV

13

19.5

ns

tpZL Output
Enable Time to
Low Level
Output

Output
Control
toV

14

21

ns

tpHZ Output,
Disable Time to
High Level
Output (Note 1)

Output
Control
toY

5.5

8.5

ns

tpLZ Output
Disable Time to
Low Level
Output (Note 1)

Output
Control
toV

9

14

ns

-

Nolel: CL =5 pF.

5-138

.------------------------------------------------------------------,0
3:

~National

en

~

~ Semiconductor

~

o
3:

DM54S257/ DM74S257, DM54S258/ DM74S258
TRI·STATE@ Quad 1 of 2 Data Selectors/Multiplexers

~

.;..

~

~

General Description
These Schottky-clamped high-performance multiplexers.
feature TRI-STATE outp'uts that can interface directly with
data lines of bus-organized systems. With all but one of the
common outputs disabled (at a high impedance state), the
low impedance of the si~gle enabled output will drive the
bus line to a high or low logic level. To minimize the possibility that two outputs will atiempt to take a common bus to
opposite logic levels, the output enable circuitry is designed such that the output disable times are shorter than
the output enable times.
This TRI-STATE output feature means that n-bit (paralleled)
data selectors with up to 258 sources can be implemented
for data buses. It also permits the use of standard TTL registers for data retention throughout the system.

~

~

o
3:
~

116

15

14

13

12

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual-In-Line Package

11

OUTPUT ~ OUTPUT
Vec CONTROL A4
B4
Y4

OUTPUT
Y3

116

10

15

14

13

12

~
A3

11

83

OUTPUT
V3

10

Is
SELECT

Al

81

Vl

A2

82

Y2

G!:

SELECT

~ OUTPUT - v - - " OUTPUT
INPUTS
INPUTS

A1
B1
Y1
A2
B2
Y2
GND
---------- OUTPUT ---....--. OUTPUT
INPUTS
INPUTS

TLJF/6482-1

545257(J)

TLlFJ6482·2

74S257(N)

54S258(J)

Function Table
Inputs
Output
Control

H
L
L
L
L
H
Z

CO
5.5V

Dual-In-Line Package
83

en

-65°Cto150'C

Connection Diagrams
A3

N
7V

Input Voltage

• Schottky-clamped for significant improvement in
A-C performance

~

in

Absolute Maximum Ratings (Note 1)

Storage Temperature Range

• TRI-STATE versions St57, St58, with same pin-outs

OUTPUT ~ OUTPUT
Vee CONTROL A4
B4
Y4

en

• Average propagation delay from data input
S257 4.8 ns
S2584 ns
• Typical power dissipation
S257320mW
S258280 mW

Supply Voltage

Features

o
3:

• Provides bus interface from multiple sources in highperformance systems

Output Y

Select

A

B

S257

S258

X

X

L
L
H
H

L
H

X
X
X

X
X

L
H

Z
L
H
L
H

Z
H
L
H
L

= High level, L = Low Level,
= High Impedance (off)

X = Oon't Care

5-139

74S258(N)

Recommended Operating Conditions
DM54S257
Sym

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

V il

Low Level Input
Voltage

10H

High Level Output
Current

10l

Low Level Output
Current

TA

Free Air Operating
Temperature

DM74S257

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

V
V

2
0.8

-55

Units

0.8

V

-2

-6.5

mA

20

20

mA

70

·C

125

0

:1

'8257 Electrical Characteristics over recommended operating free air temperature
(unless otherwise noted)
Sym

Parameter

Min

Typ
(Note 1)

DM54

2.4

3.4

DM74

2.4

3.2

Conditions

Max
-1.2

Units
V

VI

Input Clamp Voltage

Vcc= Min, 11= -18 mA

VO H

High Level Output
Voltage

Vcc=Min
10H=Max
V ll = Max
VIH=Min

Low Level Output
Voltage

Vcc = Min, 10l = Max
V IH = Min, Vil = Max

0.5

V

Input Current@Max
. Input Voltage

Vcc= Max, VI =5.5V

1

mA
/LA

VOL
II

V

High Level Input
Current

Vcc=Max
VI=2.7V

Select

100

Other

50

Low Level Input
Current

Vcc=Max,
V I =0.5V

Select

-4

Other

-2

10ZH

Off·State Output
Current with High
Level Output
Voltage Applied

Vcc=Max, Vo=2.4V
VIH=Min, Vll=Max

50

p.A

10Zl

Off·State Output
Current with Low
Level Output
Voltage Applied

Vcc=Max, Vo=0.5V
. V IH = Min, Vll"; Max

-50

p.A

los

Short Circuit
Output Current

Vcc= Max
(Note 2)

mA

ICCH

Supply Current With
Outputs High

Vcc=Max
(Note 3)

44

68

mA

ICCl

Supply Current With
Outputs Low

Vcc=Max
(Note 3)

60

93

mA

!ccz

Supply Current With
Outputs Disabled

Vcc=Max
(Note 3)

64

99

mA

IIH

ill

DM54

-40

-100

DM74

-40

-100

Nole 1: Aillypicals are at VCC=SV, TA=2S"C.
Nole 2: Not more than one oulput should be shorted at a time, and the duration should not exceed one second.
Note 3: ICC is measured with all outputs open and all possible Inputs grounded, while achieving the stated output conditions.
5-140

mA

,

'5257 Switching Characteristics at Vee=5V and TA =25·C
(See Section 1 for Test Waveforms and Output Load)

Parameter

From
(Input)
To
(Output)

RL =2801l
C L =15pF
Min

CL=50 pF

Typ

Max

Min

Units

Typ

Max

t PLH Propagation Delay
Time Low to High
Level Output

Data
to
Output

5

7.5

7

11

ns

tpHL Propagation Delay
Time High to Low
Level Output

Data
to
Output

4.5

6.5

6.5

10

ns

tpLH Propagation Delay
Time Low to High
Level Output

Select
to
Output

8.5

15

11

16

ns

tpHL Propagation Delay
Time High to Low
Level Output

Select
to
Output

8.5

15

11

16

ns

tpzH Output
Enable Time to
High Level
Output

Output
Control
toY

13

19.5

15

23

ns

tPZL Output
Enable Time to
Low Level
Output

Output
Control
toY

14

21

16

24 •

ns

tpHZ Output
Disable Time to
High Level
Output (Note 1)

Output
Control
toY

5.5

8.5

ns

tpLZ Output
Disable Time to
Low Level
Output (Note 1)

Output
Control
toY

9

14

ns

Note 1:

eL~5,pF.

Recommended Operating Conditions
Sym

Parameter

Vee
V1'H

Supply Voltage

V1L

Low Level Input
Voltage

IOH

High Level Output
Current

iOL

Low Level Output
Current

TA

Free Air Operating
Temperature

High Level Input
Voltage

DM74S258

DM54S258
Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

-55

V

-2

-6.5

mA

20

20

mA

70

·C

125

5·141

V
V

0.8

0.8

Units

0

'8258 Electrical Characteristics over recommended operating free air temperature
(unless otherwise noted)
Sym

Parameter

Typ

Min

Conditions

(Note 1)

Max

-1.2

Units

V

VI

Input Clamp Voltage

Vee= Min, II = -18 mA

VOH

High Level Output
Voltage

Vee= Min
IOH = Max
VIL=Max
VIH=Min

VOL

Low Level Output
Voltage

Vee = Min, 10L = Max
VIH = Min, VIL = Max

II

Input Current@Max
Input Voltage

Vee = Max, VI = 5.5V

IIH

High Level Input
Current

Vee = Max
VI=2.7V

Low Level Input
Current

Vee= Max,
YI=0.5V

10ZH

Off·State Output
Current with High
Level Output
Voltage Applied

Vee=Max, Vo=2.4V
VIH=Min, VIL=Max

50

{LA

10ZL

Off·State Output
Current with Low
Level Output
Voltage Applied

Vee= Max, Vo=0.5V
VIH=Min, VIL=Max

-50.

{LA

los

Short Circuit
Output Current

V~e=Max
(Note 2)

mA

leeH

Supply Current With
Outputs High

Vee = Max
(Note 3)

36

56

mA

leeL

Supply Current With
Outputs Low

Vee=Max
(Note 3)

52

81

mA

leez

Supply Current With
Outputs Disabled

Vee = Max
(Note 3)

56

87

mA

IlL

DM54

2.4

3.4

DM74

2.4

3.2

V

0.5

V

1

mA

Select

100

{LA

Other

50

Select

-4

Other

-2

/'

DM54

-40

-100

DM74

-40

-100

Note t: All typicals are at Vee=5V, TA=25°e.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: ICC is measured with all outputs open and all possible inputs grounded. while achieving the stated output conditions.

,
5·142

,

mA

'S258 Switching Characteristics

at Vcc=5V and TA=25 D C

(See Section 1 for Test Waveforms and Output Load)
From
(Input)
To
(Output)

Parameter

RL = 2800
C L =50pF

CL=15 pF
Min

Typ

Max

Min

Units

Typ

Max

tPLH Propagation Delay
Time Low to High
Level Output

Data
to
Output

4

6

6

9

ns

tPHL Propagation Delay
Time High to Low
Level Output

Data
to
Output

4

6

6

9

ns

tpLH Propagation Delay
Time Low to High
Level Output

Select
to
Output

8

12

10

15

ns

tpHL Propagation Delay
Tim,e High to Low
Level Output

Select
to
Output

7.5

12

9.5

15

ns -

tPZH Output
Enable Time to
High Level
Output

Output
Control
toY

13

19.5

15

23

ns

tpZL Output
Enable Time to
Low Level
Output

Output
Control
toY

14

21

16

24

ns

tpHZ Output
Disable Time to
High Level
Output (Note 1)

- Output
Control
toY

5.5

8.5

ns

tpLZ Output
Disable Time to
Low Level
Output (Note 1)

Output
Control
toY

9

14

ns

Nole I: CL = 5 pF.

Logic Diagrams
5258

5257
OUTPUT~~

OUTP~~
CONT=~L(2)

)-L
81 (3)

A2 (5)

82 (6)

A3 (11)

:o-r

A4 (14)

:o-r

84

(13)

SELECT~

:o-r

82(6)

AJ")

~Y3

~

81 (3)

A2 (5)

In~Y2
)-L

83 (10)

~Y1 ,

CONTRO~ 1 (2)

(10)
63
(14)
A4

""

Y4

64

SELECT~

TLlF/6482·3

0

~Y1

.rL ~Y2

DI

rL ~Y3

:o-r

~.
TLlF/6482·4

5·143

'0
CO

~
:!:
c

~

~
LI')

~------------------------------------------------------------------------------,

~National

~ Semiconductor

DM54S280/DM74S280 9·Bit Parity Generators/Checkers

:!:

c General Description

Features

These universal, nine-bit parity generators I checkers utilize
Schottky-clamped TTL high-performance circuitry, and feature odd I even outputs to facilitate operation of either odd
or even parity applications. The word-length capability is
easily expanded by cascading.

• Generates either odd or even parity for nine data lines
• Cascadable for n·bits
• Can be used to upgrade existing systems using MSI
parity circuits
• Typical data-to-output delay-14 ns

The S280 can be used to upgrade the performance of most
systems utilizing the DM74180 parity generator I checker.
Although the S280 is implemented without expander inputs,
the corresponding function is provided by the availability of
an input at pin 4, and no internal connection at pin 3. This
permits the S280 to be substituted for the 180 in existing
designs to produce an identical function, even if S280's are
mixed with existing 180's.

Supply Voltage

Input buffers are provided so that each input represents
only one normal 74S load, and full fan-out to 10 normal Se·
ries 74S loads is available from each of the outputs at low
logic levels. A fan-out to 20 normal Series 74S loads is provided at high logic levels, to facilitate connection of unused
inputs to used inputs.

Connection Diagram

Absolute Maximum Ratings (Note 1)
7V

Input Voltage

5.5V

Storage Temperature Range

- 65'Cto 150'C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated 8,t these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditionf;! for actual device operation.

Function Table

Dual-In-Line Package
INPUTS

vIC,.

i 111 [to 19
I I I I I

F

C

113

.--

1

G

r--'

A

8

12

l-

I
I'

H

-----.-

I
1:

N

INPUTS

I'
I

INPUT

I

i

5

t

EVEN

I-

1
6

G!;

ODD

----------'
OUTPUTS

TL/F/6483-1

,54S280(J)

74S280(N)

5-144

Outputs

Number of Inputs (A
Thru I) that are High

LEven

0,2,4,6,8

H

L

1,3,5,7.9

L

H

L Odd

Recommended Operating Conditions
Sym

DM54S280

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH,

High Level Output
Current

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

DM74S280

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

0.8

0.8

-1

-1
20
-55

Electrical Characteristics

125

V
V

2

2

Units

V
mA

20

mA

70

·C

0

over recommended operating free air temperature (unless otherwise noted)
Typ
(Note 1)

2.7

3.4

Parameter

VI

Input Clamp Voltage

Vee=Min,ll= -18 mA

VOH

High Level Output
Voltage

Vee = Min, 10H = Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee = Min, 10L = Max
VIH = Min, V IL = Max

0.5

V

II

Input Current@Max
Input Voltage

Vee = Max, VI = 5.5V

1

mA

IIH

High Level Input
Current

Vi::;e=Max, VI=2.7V

50

p.A

IlL

Low Level Input
Current

Vee = Max, VI = 0.5V

-2

mA

los

Short Circuit
Output Current

Vee=Max
(Note 2)

mA

Supply Current

Vee= Max
(Note 3)

Icc

Conditions

Min

Sym

Max
-1.2

-40

-100

DM74

-40

-100

Nota 1: All typicals are at Vee = 5V, TA= 25°C,
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: ICC is measured with all inputs grounded and all outputs open.

5·145

V
V

DM54

67

Units

1Q5

mA

,

Switching Characteristics

Parameter

at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output l.,oad)

From
(fnput)
To
(Output)

Min

RL = 1800

RL == 2800

C L =15 pF

C L =50 pF

Typ

Max

Min

Units

Typ

Max

tpLH Propagation Delay
Time Low to High
Level Output

Data
to
r; Even

14

21

16

24

ns

tpHL Propagation Delay
Time High to Low .
Level Output

Data
to
r; Even

12

18

14

21

ns

tpLH Propagation Delay
Time Low to High
Level Output

Dat13to
r; Odd

14

21

16

24

ns

tpHL Propagation Delay
Time High to Low
Level Output

Data
to
r; Odd

12

18

14

21

ns

,

J

...

Logic Diagram

A

B

-"
V"""

(8)

'

(9)

:f?::

(10)"

c-;.,.;

:{>-

(11) .....

=C>-

D-V
(12) .....

V

E

(13) .....

F-V

G (1)

H

ct>--<

(2) "

,(4)

ct>ct>-

V

-"

-v

:{>-

~~

~}

~

'.

5-146'

cC-

~'

EVEN

, -"
-v

~'

DOD

'--

-"
-v

TlIFI6483-2

Typical Applications
Three 5280's can be used to implement a 25-line parity
generator / checker. This arrangement will provide parity in
typically 25 ns. (See Figure t.)

or 3-input (5135) exclusive-OR gate for 18 or 27-line parity
applications.
Longer word lengths can be implemented by cascading
5280'5: As shown in Figure 2, parity can be generated for
word lengths up to 81 bits in typically 25 ns.

As an alternative, the outputs of two or three parity
generators/checkers can be decoded with a 2-input (586)

A

A

B

C
0
E
F

B

~

C

EVEN

0
E

S280

~

EVEN

S280

F

G

G

H

H

I

I

A

H
L

=
=

EVEN
000

H = 000
L = EVEN

B

C
0
E

G

H
I

~

EVEN

H
L

= EVEN
= 000

H
L

= EVEN
= 000

S280
~

000

,.
EVEN

S2ao

F
G

'-----v---'
TO OTHER
S280'S

H
TlIF/6483·3

FIGURE 1_ 25-Line Parity/Generator Checker

0
E
F

F
G

B

S280

B

C

H
I

A

EVEN

A

~

C

EVEN
0
E S280

TLlFJ6483·4

FIGURE 2_ 81-Line Parity/Generator Checker

'.

5-147

~r------------------------------------------------------------------------'

~ ~ National

.
Slc ~ Semiconductor
.

~

~

DM54S283/DM74S283 4-.Bit Binary Adders with Fast Carry

:, General Description
:E These full adders perform the addition of two 4·bit binary
c numbers. The sum (2:) outputs are provide(l for each bit and

• Typical add times
Two 8-bit words 15 ns
Two 16-bit words 30 ns
• Typical power dissipation 510 mW

the resultant carry (C4) is obtained from the fourth bit.
These adders feature full internal look ahead across all four
bits. This provides the system designer with partial lookahead performance at the economy and reduced package
count of a ripple-carry implementation.

Absolute Maximum Ratings (Note 1)

The adder logic, including the carry, is implemented in its
true form meaning that the end-around carry can be accomplished without the need for logic or level inversion.

Supply Voltage
Input Voltage
Storage Temperature Range

7V
5.5V
-65·Cto150·C

Features

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should

• Full-carry look-ahead across the four bits
• Systems achieve partial look-ahead performance with
the economy of ripple carry

not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommehded Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagrams and Function Table
.

r

vee
16

Dual-ln·Line Package
83

A3

,.

15

!3

A4

13

8'

11

12

!:4

C4

10

7
~2

A2

B2

!1

81

A1

co

I"
GND

TUF/6484·1

, 74S283(N)

54S283(J)
Output

~co'::\ ~co-:H

Input

When
C2=L

When
C2=H

H = High Level, L = Low Level
L
H
L
H
H
L
H
L
H
L
H
H
L
H

L

L

L

H
H

H
H
L

H·
H
H
H
L
L'

H
H

H
H

H
H
H
H

L
H
H
L
H
H

L
L
H
H
H
H

L

H

.L

L
H
H

H
H

H
H

H
H
H

L
H

L
L
H
H
H
H
H

5-148

H
H

H
H
H

Note
Input conditions at A 1,81, A2. B2,
and CO are used to determine outputs

H

H
H
L
H

L

H
H
H

L

H
H
H
H
H
H
H
H
H

L
H
H
H,
H

H
H
H
H
H
H
H

l: 1 and ~2 and the value of the internal
carry C2. The values at C2, A3, 83,
A4, and B4 are then used to
determine outputs ~3. ~4. ~nd C4.

Recommended Operating Conditions
DM74S283

DM54S283
Sym

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current (Output C4)

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

IOL

TA

-0.5

-0.5

-1

-1
10

Low Level Output
Current (Other Outputs)

20

20

Parameter

-55

125

Min

Typ
(Note 1)

DM54

2.5

3.4

DM74

2.7

3.4

Conditions

Input Clamp Voltage

Vcc=Min, 11= -1BmA

VOH

High Level Output
Voltage

Vcc=Min
10H = Max
VIL=Max
VIH=Min

. Low Level Output
Voltage

70

0

V
mA

mA

·C

over recommended operating free air temperature (unless otherwise noted)

VI

VOL

O.B

10

Electrical Characteristics
Sym

O.B

Low Level Output
Current (Output C4)

Free Air Operating
Temperature

V
V

2

High Level Output
Current (Other Outputs)

Units

Max
-1.2

Units
V
V

Vcc = Min, 10L = Max
VIH = Min, V IL = Max

0.5

V

1

mA

II

Input Current@Max
Input Voltage

Vcc=Max, VI =5.5V

11\-1

High Level Input Current

Vcc=Max, VI=2.7V

IlL

Low Level Input Current

Vcc=Max, VI=0.5V

los

Short Circuit
Output Current

Vcc= Max'
(Note 2)

ICC1

Supply Current

Vcc=Max
(Note 3)

BO

120

mA

ICC2

Supply Current

Vcc=Max
(Note 4)

95

160·

mA

50

mA
mA

C4 Output

-20

-100

Other Outputs

-40

-100

Nolel: All typicals are at VCC=5V, TA=25'C.
Note 2: Not more ttl an one output should be shorted at a time, and the duration should not exceed one second.
Note 3: ICC I is measured with all outputs open, all B Inputs low and all other Inputs at 4.5V.
Note 4: ICC2 is measured with all outputs open and all inputs aI4.5V.

-

p.A

-2

Switching Characteristics at Vee = 5V and TA ~ 25"C (See Section 1 for Test Waveforms and Output t.oad)
From
(Input)
To
(Output)

Parameter

RL =2800
C L =15 pF
Min

Units

CL=50 pF

Typ

Max

Min

Typ

Max

tPLH Propagation Delay
Time Low to High
Level Output

CO
to
1:1 or 1:2

11

18

13

20

ns

tPHL Propagation Delay
Time High to Low
Level Output

CO
to
1:1 or 1:2

12

18

14

20

ns

tpLH Propagation Delay
Time Low to High
Level Output

CO
to
1:3

11

18

13

20

ns

tPHL Propagation Delay
Time High to Low
Level Output

CO
to
1:3

12

18

14

20

ns

tpLH Propagation Delay
Time Low to High
Level Output '

CO
to
1:4

11

18

13

20

ns

tpHL Propagation Delay
Time High to Low
Level Output

CO
to
1:4

12

18

14

20

ns

AI,BI
to
SI

11

18

14

20

ns

tpHL Propagation Delay
Time High to Low
Level Output

Aj,BI
to

12

18

14

20

ns

tpLH Propagation Delay
Time Low to High
, Level Output (Note 1)

CO
to
1:4

6

11

10 ,

15

ns

tpHL Propagation Delay
Time High to Low
Level Output (Note 1)

CO
to
1:4

7.5

11

I?

15

ns

tpLH Propagation Delay
Time Low to High
Level Output (Note 1)

Ai,Bj'
to
C4

7.5

12

12

16

ns

tpHL Propagation Delay
Time High to Low
Level Output (Note 1)

AI,Bj
to
C4

8.5

12

13

16

ns

tpLH Propagation Delay
Time Low to High
Level Output

\

81

=

Notel: RL 56Oll.

"

-

5·150

,

Logic Diagram

S283

;0_ _ _-..,;(::.:9)
C4

(11)

B4

_o---r-

\"""\._(.10)

~~4

(15)

B3 .......~-r--

(2)

B2

_o---r-

A2

TLlFJ6484·2

5·151

I ~National
Semiconductor
~ ~

I
c

DM54S299/DM74S299
... TRI·STATE® 8·Bit Universal Shift/Storage Registers

:IE

c

Description

•
•
•
•
•

This Schottky TTL eight-bit universal register features
multiplexed inputs I outputs to schieve full eight bit data
handling in a single 20-pin package. Two function·select in·
puts and two output-control inputs can be used to choose
the modes of operation listed in the function table.

TRI-STATE Outputs Drive Bus Lines Directly
Can Be Cascaded for N-Bit Word Lengths
Operates with Outputs Enabled or at High Z
.Guaranteed shift (clock) frequency 50 MHz
Typical power dissipation 700 mW

Absolute Maximum Ratings (Note 1)

Synchronous parallel loading is accomplished by taking
both function-select lines, SO and S 1, high. This places the
TRI-STATE outputs in a high-impedance state, which permits data that is applied on the input I output lines to be
clocked into the register. Reading out of the register can be
accomplished while the outputs are enabled In any mode. A
direct overriding input is provided to clear the register
whether the outputs are enabled"or off.

Supply Voltage
Input Voltage
Storage Temperature Range

7V

5.5V
-65·Cto150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the salety 01 the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table arB not guaranteed at the absolute

Features

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation .

• Multiplexed Inputs I Outputs Provide ImPfoved Bit Density
• Four Modes of Operation:
Hold (Store)
Shift Left
Shift Right
Load Data

Connection Diagram
Dual-ln·Line Package

VCC

SHIFT
SHIFT
LEFT
RIGHT
SL Ow H/OHF/OFO/OOB/OBCLOCK SR

51

120 119 118

116115 J14 J13

G

1

G/OG E/OE C/OC A/OA OA'CLEAR

--12

G1

11

SR ~

SO

SO

12

Ow H/OH F/OF 0/00 BlOB CK

SL

51

J17

13

4

5

6

7

B

9

110

G2 G/OG E/OE C/OC A/OA OA' CLEAR GNO

OUTPUT
CONTROLS

TUF/6485-1

548299 (J)

748299 (N)

5·152

c

s::

Function Table
Inputs/Outputs

Inputs
Mode

Function Output
Clear Select Control Clock
51

SO G1t G2t

Serial
SL

SR

A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH

L
L

L
L

L
L

L
L

L
L

QCO . QDO
QCO QDO

QEO
QEO

QFO
QFO

QGO
QGO

QHO
aHO

QAO
QAO

QHO
QHO

QAn
QAn

QBn
QBn

QCn
QCn

QDn
QDn

QEn
QEn

QFn
QFn

aGn
aGn

H
L

QGn
QGn

QBn
QBn

QCn
QCn

QDn
QDn

QEn
QEn

QFn
QFn

QGn
QGn

QHn
QHn

H
L

QBn
aBn

H
L

a

b

c

d

e

1

g

h

a

h

X
X

X
X

X
X

L
L

L
L

L
L

L
L

X

X

X
X

X
X

Qf-O
QAO

QBO
QBO

L
L

H
H

L
L

L
L

X
X

H
L

H
L

H
H

H
H

L
L

L
L

L
L

H
L

X
X

H

H

H

X

X

t
t
t
t
t

X

X

X

L

L

X

Hold

H
H

L

L

X

Shift Right

H
H

Shift Left
Load

L

QW

L
L

L
L

L
L

QA'

iCO

C

s::

L
L

Clear

Outputs

L
L

L
L

tWhen one or both output controls are high the eight input loutput terminals are disabled to the high.-impedance state; however,
sequential operation or clearing 01 the register is not affected.
a ... h = the level of the steady-state input at inputs A through H, respectively_ These data are loaded into the flip-flops
input I output terminals.
0AO ..• OHO= The output logic leyel of Ox before the indicated input conditions were established.
H= high logic level, L= low logic level, X= either low or high logic level
0AN ... OHN = The output logic level before the active transition (1) of the clock input.

5-153

whil~

the flip-flop outputs are isolated from the

~

CO

Recommended Operating Conditions

(See Section

1 for Test ~aveforms and Output

DM54S299
Parameter

Sym
Vcc

Supply Voltage

V IH

High Level Input
Voltage

V IL

Low Level Input
Voltage

IOH

High. Level Output
Current (QA tI:uu QH)

Nom

Max

Min

Nom

Max

4.5
2

5

5.5

4.75
2

5

5.25

V

0.8

V

-2

-6.5

mA

-0.5

-0.5

Low Level Output
Current (QA thru QH)

20

20

High Level Output
Current (QA" QH')

6

6

2)

Clock Frequency (Note

fCLK

Clock Frequency (Note 3)

tw

Pulse Width

Clock
High

Setup Time
(Note 4)

tH

Hold Time (Note 4)

tREL

Clear Release Time

TA

Free, Air Operating
Temperature

70

0
0
10

50
40

60

0
0
10

Clock
Low

10

Clear
Low

10

Select

151

151

Data
High

71

71

Data
Low

51

51

70

mA

50
40

60

MHz
MHz
ns

10
10
i

51
101
-55

,',
125

ns

51
101
0

ns
ns

70

·C

,
Note 1:
Nota 2:
Note 3:
Note 4:

Units

V

O.B

fCLK

tsu

DM74S299

Min

High Level Output
Current (QA' , Qw )
IOL

Load)

The symbol (t) Indlcaies the rising edge of the clock pulse Is used for reference.
CL=15 pF and RL='2800.
CL = 50 pF and RL = 2800.
Data Includes the two serial Inputs and the eight Input/output data lines.

5-154

r

,

c
Electrical Characteristics
Sym

Parameter

Conditions

Typ
(Note 1)

Min

VI

Input Clamp Voltage

Vee=Min, 11= -18 mA

VOH

High Level Output
Voltage

Vee=Min
10H = Max
Vll=Max
VIH=Min

Max

CO

-1.2

QA thru QH

2.4

3.2

QA', QH'

2.7

3.4

C

V

s::

V

~

~\
CO
CO

V

VOL

Low Level Output
Voltage

Vee=Min,lol=Max
VIH = Min, Vil = Max

II

Input Current@Max
Input Voltage

Vee = Max, VI = 5.5V

1

mA

IIH

High Level Input
Current

Vee=Max
VI=2.7V.

A thru H,
SO, 51

100

p.A

Any Other

50
-2

Clock, Clear

mA

Low Level Input
Current

Vee=Max
VI =0.5V

10ZH

Off·State Output
Current with High
Level Output
Voltage Applied
QA thru QH

Vee = Max, Vo=2.4V
VIH = Min, Vil = Max

100

p.A

IOZl

Off·State Output
Current with Low
. Level Output
Voltage Applied
OA thru OH

Vee=Max, Vo=0.5V
VIH=Min, VIL=Max

-250

J!..A

los

Short Circuit
Output Current
(OA thru OH)

Vee=Max
(Note 2)

mA

Short Circuit
Output Current
(OA',OH')

Vee = Max
(Note 2)

Supply Current

Vee = Max

Icc

i-

Units

0.5

III

s::

over recommended operating free ·air temperature (unless otherwise noted)

-0.25

Other

DM54

-40

-100

DM74

-40

-100

DM54

-20

-100

DM74

-20

-100
140

Note 1: All typicals are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

,

i

'.

5·155

225

mA

(

Switching Characteristics at Vcc=5V and TA=25°C
Parameter

f MAX Maximum Clock
Frequency

From
(Input)
To
(Output)

Min

Typ

(Note 3)

50

70

(See Section 1 for Test Waveforms and Output Load)
RL = 2800 (Note 2)

C L =15 pF

C L =50pF
Max

Min

Typ

40

60

Units
Max
MHz

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
OA' orOw

12

20

15

23

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
OA' orOw

13

20

19

29

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
OA' thru OH'

15

21

18

27

tPHL Propagation Delay
Time High to Low
Level Output

Clock
to
OA' thru OH'

15

21

18

27

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
OA' orOw

14

21

20

30

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
OA thru OH

16

24

19 .

29

ns

tpZH Output
Enable Time to
·Hlgh Level
Output

131,G2
to
OA thru OH

10

18

13

20

ns

tPZL Output
Enable Time to
Low Level
Output

131, G'2
to
OA thru OH

12

18

16

24

ns

tpHZ Output
Disable Time to
High Level
Output (Note 1)

131,<3'2
to
OA thru OH

7

12

ns

tpLZ Output
Disable Time to
Low Level
Output (Note 1)

G1, G2
to
OA thru OH

7

12

ns

\

ns
\

,

-

Note 1: CL=5 pF.
Note 2: R.L = 1 KO for delays measured to 0A' and 0H '.
Note 3: For testing 'MAX all ~utputs are loaded simultaneously.

.

r

,

5·156

(

ro

CQ

n'

o
i'

CQ

iil

3
51

SO

~,i
SHIFT
(18) RIGHT
SHIFT
LEFT
SERIAL

SERIAL
(11)

INPUT

INPUT

~I
(12)
CLOCK

(17)

0A' (8)

°H'

(9)

CLEAR

_
OUTPUT
CONTROLS

(2)

{Gl-

(3)

G2-

I
(7)

A/QA

1(13)

BlOB

1(6)
C/OC

1(14)
D/On

I(5i
E/OE

1(15)
F/OF

1(4)
G/OG

1(16)
H/QH

TLlF/6485·2

66~St lwa/66~StSWa

t!
~ ~National

~ .~ Semiconductor
~ DM54S373/DM74S373, DM54S374/DM74S374
TRI-STATE® Octal D-Type Transparent Latches
~ and Edge-Triggered Flip-Flops
('I)

:E

c

i
:E

c

CO)

.....
('I)

en
;1;
:E
c

General Description
These a-bit registers feature totem-pole TRI-STATE outputs designed specifically for driving highly-capacitive or
relatively low-impedance loads. The high-impedance state
and increased hig~-Iogic-Ievel drive provide these registers with the capability of being connected directly to and
driving the bus lines in a bus-organized system· without
need for interface or pUII:up components. They are particularly attractive for implementing buffer registers, 1/0 ports,
bidirectional bus drivers, and working registers.

buffered output control input can be used to place the eight
outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
the latches or flip-flops. That is, the old data can be retained or new data can be entered even while the outputs
are off.

The eight latches of the DM54/748373 are transparent
D-type latches meaning that while the enable (G) Is high
the Q outputs will follow the data (D) inputs. When the
, enable is taken low the output will be latched at the level of
the data that was set up.

Features
• Choice of a Latches or a D-Type Flip-Flops in a Single
Package

The eight flip-flops of the DM54/748374 are edge-triggered
Ootype flip-flops. On the positive transition of the clock,
the Q outputs will be set to the logic states that were set
up at the 0 inputs.
Schmitt-trigger buffered inputs at the enableiclock lines
simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A

Connection Diagrams

•
•
•
•

TRI-STATE Bus-Driving Outputs
Full Parallel-Access for Loading
Buffered Control Inputs
ClocklEnable Input Has Hysteresis to Improve
Noise Rejection
• P-N-P Inputs Reduce D-C Loading on Data Lines

Dual-In-Llne Package

Vee

.Q

.0

OUTPUT
CONTROL

10

10

70

7Q

6Q

60

50

5Q

20

2Q

3Q

3D

40

40

548373 (J)

ENABLE
G

GND

TLIFI6486-1

74S373(N)

Dual-In-Llne Package
Vee

80

.0

70

7Q

6Q

60

50

50

OUTPUT
CONTROL

10

10

20

2Q

3Q

3D

40

40

548374(J)

748374(N)
5-158

CLOCK

GNO

TLlFI6488·2

r----------------------------------------------------------------------.c
s::
Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table afB not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

7V

5.5V
-65'Cto150'C

~
Co)

.....
Co)
c

-s::
~

CJ)

Function Tables

Co)

.....

~Co)

DM54174S373
Truth Table

c

DM54174S374
Truth Table

Output
Control

Enable
G

0

Output

L
L
L
H

H
H
L
X

H
L
X
X

H
L

00

Output
Control
L
L
L
H

,

Z

s::
U'I

Clock

0

Output

t
t

H
L
X
X

H
L

L
X

~
C

s::
.....

00
Z

.a::o.

en
Co)

H = High Level (Steady State), L = Low level (Steady State), X = Don't Care
t Transition from !ow·to~high level, Z = High Impedance State
00 = The level of the, output ~efore steady-state input conditions were established.

~

=

Logic Diagram
DM54174S373
Transparent Latches

DM54/74S374
Posltive-Edge-Triggered Flip-Flops

C~~:~~....:.(l:.:.)-----_...,
10....:.(3::..)_ _ _-I

,---._..,~~_ _

10

1--+_1'>-':::"""10

+--1

+--i

20.....;(4..;1_ _

20.....:(4.;:1_ _

_ , ......- - 2 0

+--i

30....:.(7,,-)_--11--1

30.....;(7";)_ _

.---.~, ......-

30
40.....:(8;;:)_ _

I--+--"':":":;:"" 70

1---01>"':":":;:"" 80
ClOCK ~(.:.;11:!.)1>0-..1
TL/F/6486-3

TL/F/6486-4

5·159

'8373 Recommended Operating Conditions
Sym
- Vcc

Parameter
Supply Voltage

V1H

High Level Input
Voltage

V1L

Low Level Input
,
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

tw

Pulse Width
(Note 2)

Pulse Width
(Note 3)

(See Section 1 for Test Waveforms and Output Load)

DM54S373
Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2
0.8

mA

20

20

mA

Enable
Low

7.3

7.3

Enabre
High

15

15

Enable
Low

15

15

01

01

tH
TA

Free Air Operating
Temperature

ns

ns

101

101
-55

125

Note 1: The symbol (J) indicates the failing edge of the clock pulse Is used for reference.

CL=15 pF and RL=2800.
CL = 50 pF and RL = 2800.

5·160

V

-6.5

6

Data Setup Time (Note 1)

V

-2

6

Data Hold Time (Note 1)

Units

V
0.8

Enable
High

tsu

Note 2:
Note 3:

DM74S373

Min

0

ns
70

·C

'5373 Electrical Characteristics

over recommended operating free air temperature

(unless otherwise noted)
Sym

Min

Typ
(Note 1)

DM54

2.4

3.4

DM74

2.4

3.2

. Conditions

Parameter

Max

Units

VI

Input Clamp Voltage

Vcc=Min, 11= -18 mA

VOH

High Level Output
Voltage

Vcc=Min
IOH=Max
VIL = Max
VIH=Min

VOL

Low Level Output
Voltage

Vee=Min,loL=Max
V IH = Min, VIL = Max

0.5

V

II

Input Current@Max
Input Voltage

Vee = Max, VI = 5.5V

1

mA

IIH

High Level Input
Current

Vee = Max, VI=2.7V

50

p.A

IlL

Low Level Input
Current

Vee=Max, VI =0.5V

IOZH

Off·State Output
Current with High
Level Output
Voltage Applied

Vee = Max,·V o = 2.4V
VIH = Min, VIL = Max

50

p.A

IOZL

Off·State Output
Current with Low
Level Output
Voltage Applied

Vee = Max, Vo=0.5V
VIH = Min, VIL = Max

-50

p.A

los

Short Circuit
Output Current

Vee = Max
(Note 2)

mA

Supply Current

Vee = Max

Icc

-1.2

V
V

p.A

- 250

DM54

-40

-100

DM74

-40

-100
160

105

mA

Nole 1: Aillypicals are at Vee = 5V. TA = 25'e.
Nota 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

'5373 Switching Characteristics

at Vee=5V and TA =25'C

(See Section 1 for Test Waveforms and Output Load)

Parameter

From
(Input)
To
(Output)

RL=280n
CL =15pF
Min

Units

CL=50 pF

Typ

Max

Min

Typ

Max

t PLH Propagation Delay
Time Low to High
Level Output

Data
to
AnyQ

5

9

7

11

ns

tpHL Propaga~ion Delay
Time High to Low
Level Output

Data
to
AnyQ

9

13

11

17

ns

tpLH Propagation Delay
Time Low to High
Level Output

Enable
to
AnyQ

7

14

9

14

ns

tpHL Propagation Delay
. Time High to Low
Level Output

Enable
to
AnyQ

12

18

14

21

ns

Output
Control
to Any Q

8

. 15

.11

17

ns

tpZH Output
Enable Time to
High Level
Output

.5·161

Switching Characteristics (Continued) at Vcc = 5V and TA= 25·C
From
(Input)
To
(Output)

Parameter

RL=2BOO

Min

Units

CL=50 pF

CL=15 pF
Typ

Max

Min

Typ

Max

15

23

tpZlOutput
Enable Time to
Low Level
Output

Output
Control
to AnyO

11

18

tpHZ Output
Disable Time to
'High Level
Output (Note 1)

Output
Control
toAnyO

6

9

ns

tpLZ Output
Disable Time to
Low Level
Output (Note 1)

Output
Control
to Any 0

8

12

ns

ns

Note 1: Cl =5 pF.

'5374 Recommended Operating Conditions
Parameter

Sym

(See Section 1 for Test Waveforms and Output Load)

DM54S374

DM74S374

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units

Vcc

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level Input
Voltage

10H

High Level Output
Current

-2

-6.5

mA

10l

Low Level Output
Current

20

20

mA

2

2

V
V

0.8

0.8

V

fClK

Clock Frequency (Note 2)

0

100

75

0

100

75

MHz.,

fClK

Clock Frequency (Note 3)

0

100

75

0

100

75

MHz

tw

Pulse Width
(Note 2)

Clock
High

6

6

Clock
Low

7.3

7.3

Clock
High

15

15

Clock
Low

15

15

Pulse Width
(N,ote 3)

ns

tsu

Data Setup Time (Note 1)

51

51

ns

tH

Data Hold Time (Note 1)

21

21

ns

TA

Free Air Operating
Temperature

-55

125

Not~ 1: The symbol (I) Indicates the rising edge of the clock pulse Is used for reference.
Nole 2: Cl=15 pF and Rl=2BO!I.
Note 3: Cl ='50 pF and Rl = 2800.

5·162 .

0

70

·C

'5374 Electrical Characteristics

over recommended operating free air temperature

(unless otherwise noted)
Sym

Parameter

Conditions

Min

VI

Input Clamp Voltage

Vee=Min,ll= -18 mA

VOH

High Level Output
Voltage

Vee = Min
IOH=Max
Vlt=Max
VIH=Min

Typ
(Note 1)

Max

-1.2

DM54

2.4

3.4

DM74

2.4

3.2

Units

V
V

"-

VOL

Low Level Output
Voltage

Vee = Min, IOL = Max
VIH = Min, VIL = Max

0.5

V

II

Input Current@Max
Input Voltage

Vee = Max, VI =5.5V

1

mA

IIH

High Level Input
Current

Vee= Max, VI =2.7V

50

/LA

IlL

Low Level Input
Current

Vee = Max, VI =0.5V

250

/LA

IOZH

Off·State Output
Current with High
Level Output
Voltage Applied

Vee=Max, Vo=2.4V
VIH = Min, VIL = Max

50

/LA

10ZL

Off·State Output
Current with Low
Level Output
Voltage Applied

Vee=Max, Vo=0.5V
VIH = Min, V IL = Max

-50

/LA

los

Short Circuit
Output Current

Vee = Max
(Note 2)

-40

-100

mA

-40

-100

Supply Current

Vee= Max

Icc

DM54
DM74

90

Not. 1: All typicals are at Vee=5V, TA=25"e.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

5·163

140

mA

'S374 Switching Characteristics at Vcc=5V and TA = 25°C
(See Section 1 for Test Waveforms and Output Load)
From
(Input)
To
(Output)

Parameter

fMAX Maximum Clock
Frequency

RL =2800
C L =15 pF
Min

Units

CL=50 pF

Typ

Max

75

Min

Typ

Max

100

75

100

MHz

tpLH Propagation delay time
Low to High Level Output

CI9ck
to
Any Q

8

15

10

15

ns

tpHL Propagation Delay Time
High to Low Level Output

Clock
to
Any Q

11

17

13

20

. ns

tPZH Output Enable Time
to High Level Output

Output
Control to
Any Q

8

15

11

17

os

tpZL Output Enable Time·
to Low Level Output

Output
Control to
Any Q

11

18

15

23

ns

tpHZ Output Disable Time
from High Level Output
(Note 1)

Output
Control to
Any Q

5

9

ns

tpLZ Output Disable Time
from Low Level Output
(Note 1)

Output
Control to'
Any Q

7

12

ns

Note 1:

,

CL=5 pF.

I

\

-

5·164

.'

_NatiOnal
.
Semiconductor
DM54S381/DM74S381
Arithmetic Logic Unit/Function Generator
General Description

• Paralleflnputs and Outputs and Full Look-Ahead Provide
System Flexibility

The 'S381 is a Schottky TTL arithmetic logic unit
• Arithmetic and Logic Operations Selected Spec;ifically to
(ALU)lfunction generator that performs eight binary
Simplify System Implementation:
arithmeticllogic operations on two 4-bit words as shown in
A Minus B
the function table. These operations are selected by the
B Minus A
three function-select lines (SO, 51, 52). A full carry lookA Plus B
ahead circuit is provided for fast, simultaneous carry genand Five .other Functions
eration by means of two cascade outputs (P and G) for the
• Schottky-Clamped for High Performance
four bits in the package. The metho.d of cascading
16-Bit Add Time ... 26 ns Typ Using
545182/745182 look-ahead carry generators with these
Look-Ahead
ALU's to provide multi-level full carry look-ahead is iIIustrat·
32-Bil Add Time ... 34 ns Typ Using
ed under typical applications data for the '5182. The typi· \
Look-Ahead
cal addition times shown illustrate the short delay time
required for addition of longer words· when full look-ahead
Absolute Maximum Ratings (Note 1)
is employed. The exclusive-OR, AND, or OR function of two
Supply Voltage
7V
Boolean variables is provided without the use of external
Input Voltage
5.5V
circuitry. Also, the outputs can be either cleared (low) or
preset (high) as desired.
Storage Temperature Range
- 65°Cto 150°C
Not. 1: The "Absolute Maximum Ratings" are .those values beyond
which the safety of the device cannot be guaranteed. The device should

Features
• A Fully Parallel 4-Bit ALU in 20-Pin Package for 0.300Inch Row Spacing
• Ideally Suited for High-Density Economical Processors

not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute

Connection Diagram

Pin Designations

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual·ln·Line Package
INPUTS

Vee

A2

B2

ho /.9 h.

I

A2

OUTPUTS

A3B3

117

116

Cn P G

115· 114

113

1
A1

I
12
B1

F2
11

112

I I I I I I

B2

A3

B3

P

en

G

A1

B1

F3

F3

F2

AO

BO

so

52

Sl

Fa

I' 5~5

AO

BO

INPUTS

545381 (J)

16
81

17
82

-18

Fa

19

F1

110

Selection
51

SO

L

L

L

L
L
L
H
H
H
H

L
H
H
L
L
H
H

H
L
H
L
H
L
H

Function
WORD A iNPUTS

B3,B2,Bl,BO

16,18,2,4

WORD B iNPUTS

52,51, SO

7,6,5

FUNCTiON-SELECT
INPUTS

Cn

15

CARRY iNPUT FOR
ADDITION, INVERTED
CARRY INPUT FOR
SUBTRACTION

F3,F2,Fl,FO

12,11,9,8

FUNCTION OUTPUTS

P

14

INVERTED CARRY
PROPAGATE OUTPUT

G

13

INVERTED CARRY
GENERATE OUTPUT

VCC

20

SUPPLY VOLTAGE

GND·

10

GROUND

GNO

OUTPUTS'
TL/F/6487·'

74S381 (N)

Function Table
S2

Pin Nos.
17,19,1,3

F1

I I J I I I

j3

Designation
A3, A2, Al, AO

Arithmetic/Logic
Operation
CLEAR
B MINUS A
A MINUSB
A PLUS B
A G:> B
A+I:I
AB
PRESET

, H = high level, L .. low level

5-165

Recommended Operating Conditions
Symbol
Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

)

DM74S381

DM54S381

Parameter

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units
V
V

2

2

Low Level Input

0.8

V

0.8

Vol~age

10H

High Leyel Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

-1

-1
20
-55

Electrical Characteristics

125

0

mA

20

mA

70

'C

over recommended operating free air temperature (unless otherwise noted)

,

Symbol

Parameter

Min

Typ
(Note 1)

DM54

2.4

3.4

DM74

2.7 •

3.4

Conditions

Max

Units

VI

Input Clamp Voltage

Vee = Min, 11= -18 mA

VOH

High Level Output
Voltage

Vee = Min
10H= Max
VIL=Max
VIH=Min

-1.2

VOL

Low Level Output
Voltage

Vee = Min, 10L = Max
VIH= Min, VIL= Max

0.5

V

II

Input' Current@Max
Input Voltage

Vee=Max, VI=5.5V

1

mA

IIH

High Level Input
Current

Vee=Max
VI=2.7V

Any S

50

p.A

Cn

250

Low Level Input
Current

Vee=Max
VI =0.5V

Any Other
IlL

los

Icc

Vee=Max
(Note 2)

Supply Current

Vce=Max

Note 1: Alltyplcals are at Vee ~ 5V. TA ~ 25'e.

V

200

Any S

-2

Cn

-8

Any Other
Short Circuit
Output Current

V

mA

-6

DM54

-40

-100

DM74

-40

-100
105

mA

160

mA

I

Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

"
5-166

Switching Characteristics
From
(Input)
To
(Output)

Parameter

at Vee = 5V and T A = 25°C (See Section"1 for Test Waveforms and Output Load)
R L =2800
,C L =15 pF
Min

Units

CL=50 pF

Typ

Max

Min

Typ

Max

tpLH Propagation Delay
Time Low to High
Level Output

Cn
to
Any F

10

17

12

19

ns

tPHL Propagation Delay
Time High to Low
Level Output

Cn
to
Any F

10

17

12

19

ns

tpLH Propagation Delay
Time Low to HIgh
Level Output

A or B
to

12

20

14

23

ns

tpHL Propagation Delay
Time HIgh to Low
Level Output

A or B
to

12

20

14

23

ns

tpLH Propagation Delay
Time Low to High
Level Output

A or B
to

11

18

13

21

ns

tpHL Propagation Delay
Time High to Low
Level Output

A or B
to

11

18

13

21

ns

tPLH Propagation Delay
Time Low to High
Level Output

Aj orBj
to
Fj

18

27

20

30

ns

tpHL" Propagation Delay
Time High to Low
Level Output

AjorBj
to
FI

16

25

18

27

ns

tpLH Propagation Delay
Time Low to High
Level Output

S
to
Any

18

30

20

33

ns

tpHL Propagation Delay
Time High to Low
Level Output

S
to
Any

18

30

20

33

ns

,

G

G

is"

P

5-167

~

~

en

r------------------------------------------------------------------------------------------,
Logic Diagram

j:!

c==
co
(W)
~

en

(15)

BO~(4)~--r-------~b:===r~

~
c==

~'3~)----~------L_J4~ff~.J
;..'2~)----r_------_;;YdJJ±~~

AO"

B,

.A' ;..";..)----~----_1
(18)

B2

'-'--T---;;!d::YJ:6-,

A2~"~9)____~__~__4

B3;.."~6)---,__~_____,

A3~"~7)----~______4

s,~(·;..)4)~~__+_------+++_~,

(7)
S2~~;~~--~--------+r----~-------"

TLlF16487·2

5-168

r---------------------------------------------------------------'c

3:

~National

I

~ Semiconductor

c
3:
.....

DM545940/DM745940, DM545941/DM745941
Octal TRI·5TATE® Buffers/Line Drivers/Line Receivers

inCD

P

c
3:

General Description
These buffers lline drivers are designed to improve both
the performance and PC board density of TRI-STATE
buffers I drivers employed as memory-address drivers,
clock drivers, and bus-oriented transmitters I receivers.
Featuring 400 mV of hysteresis at each low current PNP
data line input, they provide improved noise rejection and
high fanout outputs, and can be used to drive terminated
lines down to 133 0.

i-....
i....

• Typical propagation delay times
Inverting 4.5 ns
Noninverting 6 ns

c
3:

• Typical enable/disable times 9 ns
• Typical power dissipation (enabled)
Inverting 450 mW
Noninverting 538 mW

Features

Absolute Maximum Ratings (Note 1)

• TRI-STATE outputs drive bus lines directly
• PNP inputs reduce DC loading on bus lines
• Hysteresis at inputs improves noise margins

Supply Voltage
Input Voltage
Storage Temperature Range

• Typical IOL (sink current)
545 48 mA
745 64 mA

-65'Cto150'C

Nole 1: The "Absolute Maximum Ratings" arB those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

• TypicallOH (source current)
545 -12 mA

745

7V
5.5V

-15mA

Connection Diagrams
Dual-In-Line Package
vcc
20

1G

2G

19

1A 1

1Y1

2A4

18

2Y4

17

1A2

'1Y2
16

2Y3

2A3
15

1A3

1Y3
14

2Y2

Dual-In-Line Package
2A2
13

1A4

1Y4
12

2Y1

2A1

vee

11

GND

20

1G

2G

19

1A 1

1Y1

2A4

18

2Y4

17

1A2

1Y2
16

2Y3

2A3
15

1A3

1Y3
14

2Y2

TL/F/64B8-1

54S940 (J) 74S940 (N)

13

1A4

1Y4
12

2Y1

2A1

11

GND

TLlF/64B8-2

54S941 (J) 745941 (N)

5-169

2A2

Recommended Operating Conditions
Symbol

DM54S

Parameter

DM74S

Units

Min

Typ

Max

Min

Typ

Max

4·5

5

5.5

4.75

5

5.5

V

Vee

Supply Voltage

V IH

High Level Input Voltage

V IL

Low Level Input Voltage

0.8

0.8

IOH

High Level Output Current

-12

-15

mA

IOL

Low Level Output Current

48

64

mA

2

V

2

V

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)
Symbol
VI

VOH

Parameter

Conditions

Input Clamp Voltage

Vee = Min, 11= -18 mA

Hysteresis (VT + - VT _)

Vee=Min

High Level Output Voltage

Vee = 4.75V, VIH = 2V
V IL = 0.8V, IOH = - 1 mA

DM74

0.2

0.4

Max

Units
V
V

2.7

V

2.4

Vee= Min, V IH = 2V
V IL = 0:5V, IOH = Max
Low Level Output Voltage

Typ
(Note 1)

-1.2

Vee = Min, V IH = 2V
VIL = 0.8V, IOH = - 3 mA

VOL

Min

3.4

2

Vee=Min
VIL =0.8V
V IH =2V

IOL=Max DM54

0.55

DM74

0.55

Vee=Max
V IL-=0.8V
V IH =2V

Vo = 2.4V

50

p.A

Vo=0.5V

-50

p.A

1

mA

10ZH

Off-State Output Current,
High Level Voltage Applied

10ZL

Off-State Output Current,
Low Level Voltage Applied

II

Input Current at Maximum
Input Voltage

Vee = Max

VI = 5.5V

IIH

High Level Input Current

Vee=Max

VI=2.7V

IlL

Low Level Input Current

Vee = Max

VI=0.5V

los

Short Circuit Output Current

Vee = Max (Note 2)

Icc

Supply Current

Outputs High

I

Any A
AnyG
-50

Outputs Low

Outputs Disabled

p.A
p.A

-2

mA

-:-225

mA
mA

80

123

DM74S940

80

135

DM54S941

95

147

DM74S941

95

160

DM54S940

100

145

DM74S940

100

150

DM54S941

120

170

DM74S941

120

180

DM54S940

100

145

DM74S940

100

150

DM54S941

120

170

DM74S941

120

180

Nolel: All typical values are at Vee =5V, TA = 25°e_

5-170

50
-400

DM54S940

Note 2: Not more than one output should be shorted at a time and duration should not exceed one second.

V

,

Switching Characteristics Vee = 5V, TA = 25°C (See Section 1 for Test Waveforms and Output Load)
Max

Units

4.5

7

·ns

6

9

Typ

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

CL=45pF
RL=901l

DM54/74S940

2

DM54/74S941

2

Propagation Delay Time
High to Low Level Output

CL=45pF
RL =901l

DM54/74S940

2

4.5

7

DM54/74S941

2

6

9

Output Enable Time to
Low Level

C L =45 pF
RL =901l

DM54/74S940

3

10

15

DM54/74S941

3

10

15

Output Enable Time to
High Level

C L ;=45 pF
RL =901l

DM54/74S940

2

6.5

10

DM54/74S941

3

8

12

Output Disable Time
from Low Level

C L =5pF
RL =901l

tpHZ

Output Disable Time
from High Level

tpLH

tpHL

tPZL

tPZH

tpLZ

tpHL

tPZL

tPZH

Conditions

Min

Sym

DM54/74S940

4

10

15

DM54174S941

2

10

15

CL=5 pF
RL =901l

DM54174S940

2

6

9

DM54/74S941

2

6

9

Propagation Delay Time
Low to High Level Output

CL=150 pF
RL =901l

DM54/74S940

3

7

10

DM54/74S941

4

9

12

Propagation Delay Time
High to Low Level Output

CL=150pF
RL=901l

DM54/74S940

3

7

10

DM54/74S941

4

9

12

Output Enable Time to
Low Lavel

CL= 150 pF
RL =901l

DM54/74S940

6

14

21

DM54/74S941

6

14

21

Output Enable Time to
High Level

CL= 150 pF
RL =901l

DM54/74S940

4

9

12

DM54/74S941

4

10

15

"

I

5-171

ns

ns

ns

ns

ns

ns

ns

ns

ns

Section 6
TTL

/

Section Contents
DM25o.2 8-Bit Successive Approximation Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM25o.3 8-Bit Expandable Successive Approximation Register ............. :. . . . . . . . . . . .
DM25o.4 12-Bit Expandable Successive Approximation Register. . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74o.o. Quad 2-lnput NAND Gates ........... '....... , . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74o.1 Quad 2-lnput NAND Gates with Open-Collector Outputs . . . . . . . . . . . . . . . . . . . . . .
DM54/74o.2 Quad 2-lnput NOR Gates •............... ',' .... '. . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74o.3Quad 2'lnput NAND Gates with Open-Collector Outputs . . . . . . . . . . . . . . . . . . . . . .
DM54/74o.4 Hex Inverters ......................................... _......... : . . . . .
DM54/74o.5 Hex Inverters with Open-Collector Outputs ......... , . . . . . . . . . . . . . . . . . . . . . . .
DM54/74o.6 Hex Inverting Buffers/Drivers with High-Voltage Open-Collector Outputs ........
DM54/74o.7 Hex BufferslDrivers with High-Voltage Open-Collector Outputs. . . . . . . . . . . . . . . .
DM54/74o.8 Quad 2-lnput AND Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74o.9 Quad 2-lnput AN D Gates with Open-Collector Outputs. . . . . . . . . . . . . . . . . . . . . . . .
DM54/741o.Triple3-lnput NAND Gates. . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . .. . . .
DM54/7411 Triple3-lnputANDGates ................................................
DM54/7413 Dual4-lnput Schmitt Trigger NAND Gates ................................. "
DMp4/7414 Hex Schmitt Trigger Inverters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/7416 Hex Inverting BufferslDrivers with High-Voltage Open-Collector Outputs ........
DM54/7417 Hex BufferslDrivers with High-Voltage Open-Collector Outputs . : .............. '
DM54/7420 Dual4-lnput NAND Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/7425 Dual4-lnput NOR Gates with Strobe. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/7426 Quad 2-lnput NAND Buffers with High-Voltage
Open-Collector Outputs . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/7427 Triple 3-lnput NOR Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/743o. 8-lnput NAND Gate .................. :. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/7432 Quad 2-lnput OR Gates .................. ,..............................
DM54/7437 Quad 2-lnput NAND Buffers .............................................
DM54/7438 Quad 2-lnput NAND Buffers with Open-Collector Outputs. . . . . . . . . . . . . . . . . . . . .
DM54/744o. Dual4-lnput NAND Buffers ............ _. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
'DM54/7441A BCD to Decimal Decoder/Driver(NIXIE Drivers). . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/7442 BCDto Decimal Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/7445 BCDto Decimal DecoderlDriver .... : ........ :. . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/7446A BCD to 7-Segment Decoder/Oriverwith Open-Collector Outputs . . . . . . . . . . . . . .
DM54/7447A BCD to 7-Segment DecoderlDriverwith Open-Collector Outputs . . . . . . . . . . . . . .
DM54/7448 BCD to 7-Segment DecoderlDriver with Internal Pull-Up Resistor Outputs. . . . . . . .
DM54/745o. Dual Expandable 2-Wide 2-lnput AND-OR-INVERT Gates .. . . . . . . . . . . . . . . . . . . . .
DM54/7451 Dual2-Wide 2-lnput AND-OR-INVERT Gates ...... . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/7453 Expandable 4-Wide AN D-OR-INVERT Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/7454 4-Wide 2-lnput AND-OR-INVERT Gates ....................................
DM54/747o. AND-Gated Positive-Edge-Triggered J:K Flip-Flop with Preset and Clear .........
DM54/7472 AND-Gated Master-Slave J-K Flip-Flop with Preset and Clear ..................
DM54/7473 9ual J-K Flip-Flops with Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/7474 Dual Pdsitive-Edge-Triggered D Flip-Flops with Preset and Clear. . . . . . . . . . . . . . . .
DM5417475 4-Bit Bistable Latches .................................................
DM54/7476 Dual J-K Flip-Flops with Preset and Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/7483 4-Bit Binary Adders with Fast Carry ....................... : .' ....... ; . . . . . .
DM5417485 4-Bit Magnitude Comparators .................... , . . . . . . . . . . . . . . . . . . . . . .
DM5417486 Quad Exclusive-OR Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/749o.A Decade Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM5417492A Divide by 12 Counter .................................................
DM54/7493A 4-Bit BinaryCounter ................................. '.' . . . . . . . . . . . . . . .
DM54/7495 4-Bit Parallel Access Shift Register ................... '" .. ; ............... '
6-2

6-5
6-5
6-5
'6-16
6-18
6:20.
6-22
6-24
6-26
6-28
6-30.
6-32
6-34
6-36
6-38'
6-40.
6-43
6-46
6-48
6-50.
6-52
6-54
6-56
6-58
6-60.
6-62
6-64
6-66
6-68
6-71
6-74
6-77
6-77
6-77
6-85
6-88
6-90.
6-93
6-95
6-98
6-10.1
6-10.4
6-10.7
6-110.
6-113
6-117
6-121
6-124
6-124
6-124
6-133

Section Contents (Continued)
DM54/7496 5-Bit Parallel Access Sh ift Reg ister with Asynchronous Preset ................
DM54174107 Dual Master-Slave J-K Flip-Flops with Clear ...............................
DM54/74109 Dual Positive-Edge-Triggered J-K Flip-Flops with Preset and Clear. . . . . . . . . . . . . .
DM54/74121 Monostable Multivibratorwith Schmitt-Trigger Input. . . . . . . . . . . . . . . . . . . . . . . .
DM54/74123 Dual Retriggerable Monostable M ultivi brators with Clear ..... . . . . . . . . . . . . ... .
DM54/4125 Quad TRI-STATE Buffers ................................ _............. _.
DM54/74126 Quad TRI-STATE Buffers ........................................... ."...
DM54/7 4132 Quad 2-lnput Schm itt Trigger NAN D Gates ................................
DM54/74141 BCD to Decimal Decoder/Driver ...................... : . . . . . . . . . . . . . . . . . .
DM54/74145 BCD to Decimal Decoder/Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74147 10-Line Decimal t04-Line BCD Priority Encoder. . . . . . . . . . . . . . . . . . . . . . . . . .. .
DM54/74148 8-Line Decimal to 3-Line Octal Priority Encoder. . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74150 1 of 16 Line Data Selector/Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74151A 1 of 8 Line DataSelector/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74153 Dual1 of 4 Line Data Selectors/Multiplexers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74154 4t016LineDecoderIDemuitiplexer .....................................
DM54/74155 Dual2 to 4 Line Decoders/1 t04 Line Demultiplexers ...................... ;.
DM54/74156 Dual 2 to 4 Line Decoders/1 to 4 Line Demultiplexers
with Open-Collector Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74157Quad2t01 Line DataSelectors/Multiplexers ..............................
DM54/74160A Synchronous4-Bit Decade Counter with Asynchronous Clear. . . . . . . . . . . . . . .
DM54/74161 A Synchronous 4-Bit Binary Counter with Asynchronous Clear. . . . . . . . . . . . . . . .
DM54/74162A Synchronous 4-Bit Decade Counter with Synchronous Clear. . . . . . . . . . . . . . . .
DM54/74163A Synchronous 4-Bit Binary Counter with Synchronous Clear. . . . . . . . . . . . . . . . .
DM54/74164 8-Bit Serial In/ Parallel Out Shift Register with Asynchronous Clear. . . . . . . . . . . .
DM54/74165 8-Bit Parallel In/Serial Out Shift Registerwith Complementary Outputs ........
DM54/74166 8-Bit Parallel or Serial In/Serial Out Shift Register with
Complementary Outputs ..... .".................................................
DM74170 4 by4 Register File with Open-Collector Outputs ........ '. . . . . . . . . . . . . . . . . . . . .
DM54/74173 4-BitTRI-STATE D Register ...... ;. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .
DM54/74174 Hex D Flip-Flopswith Clear ......... ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74175 Quad D Flip-Flops with Clear and Complementary Outputs ............'. . . . . . .
DM54/74176 Presettable Decade (Bi-Quinary) Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74177 Presettable BinaryCounter . _........ _..................................
DM54/74180 9-Bit Parity Generator/Checker . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .
DM54/74181 Arithmetic Logic Unit/Function Generator. . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . .
DM54/74184 BCD-to-BinaryConverter ............................. _. . .. . . . . . . . . . . . . .
DM54/74185A Binary-to-BCDConverter ........................... :.................
DM54/74190Synchronous4-BitUp/Down DecadeCounterwith Mode Control ..............
DM54/74191 Synchronous 4-Bit Up/Down Binary Counter with Mode Control .............. _
DM54/74192 Synchronous4-Bit Up/Down Decade Counter with Dual Clock ................
DM54/7 4193 Synchronous 4-Bit Up/Down Binary Counter with Dual Clock .................
DM54/74194 4-Bit Bidirectional Uni'1ersal Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74195 4-Bit Parallel Access Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74196 Presettable Decade (Bi-Quinary) Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74197 Presettable Binary Counter ........ :....................................
DM54/74198 8-Bit Bidirectional Ufliversal Shift Registers ......... '." . . . . . . . . . . . . . . . . . . . .
DM54/74199 8-Bit Bidirectional Universal Shift Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74251 TRI-STATE 1 of 8 Line Data Selector/Multiplexer with
Complementary Outputs .......................................................
DM54/74253 Dual TRI-STATE 1 of 4 Data Selectors/Multiplexers. . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74259 8-Bit Serial In to Parallel Out Addressable Latc;:h ...........................
6-3

6-137
6-142
6-145
6-148
6-152
6-157
6-160
6-163
6-166
6-169
6-172
6-172
6-179
6-179
6-187
6-190
6-194
6-194
6-199
6-202
6-202
6-202
6-202
6-208
6-212
6-216
6-220
6-224
6-228
6-228
6-233
6-233
6-242
6-245
6-253
6-253
6-259
6-259
6-265
6-265
6-274
6-278
6-282
6-282
'6-289
6-289
6-298
6-302
6-306

Section Contents (Continued)
DM54/74365 Hex TRI-STATE Buffers/ Bus Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74366 HexTRI-STATE Inverting Buffers/Bus Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74367 Hex TRI-STATE Buffers/Bus Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74368 Hex TRI-STATE Inverting Buffers/Bus Drivers ..............................
DM7123/8123 Quad TRI-STATE 1 of 2 Line Data Selectors/Multiplexers. . . . . . . . . . . . . . . . . . . .
DM7130/8130 1O-Bit Magn itude Comparator with Open-Collector Outputs. . . . . . . . . . . . . . . . .
DM713118131 6'Bit Unified Bus Comparators with Hysteresis on Bus Inputs. . . . . . . . . . . . . . .
DM7136/8136 6·Bit Unified Bus Comparator with HystereSis on Bus Inputs and
Open-Collector Outputs .................................................. '. . . . . .
DM7160/8160 6·Bit Magnitude Comparator with Open-Collector Outputs . . . . . . . . . . . . . . . . . .
DM7200/8200 4-Bit Magnitude Comparator with Complementary Outputs. . . . . . . . . . . . . . . . .
DM7220/8220 9-Bit Parity Generator/Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7223/8223 1 t08 Line DataSelectoriDemultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7512/8512 Dual Gated Flip-Flops with Common Clock, Common Clear,
and Complementary Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7520/8520 Modulo·N Dividers ........ ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7542/8542 Quad TRI-STATE I/O Registers ,........................................
DM7544/8544 Quad TRI-STATE Switch Debouncers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7546/-8546 TAl-STATE 8-Bit Universal Positive-Edge-Triggered I/O Shift Register. . . . . . . . . .
DM7556/8556 TRI-STATE Programmable 4-Bit Binary Counter .......................... : .
DM7613/8613 Quad Gated D FI ip-Flops with Common Clock and Common Clear . . . . . . . . . . . .
DM7875/8875A TRI-STATE4-Bit Parallel Binary Multipliers .. , . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7875/8875B TRI-STATE 4-Bit Parallel Binary Multipliers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM8898 TRI-STATE 6-Bit BCD to Binary Converters .................... : . . . . . . . . . . . . . . . .
DM8899 TRI-STATE 6-Bit Binary to BCD Converters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM9002C Quad 2-lnput NAND Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM9003C Triple3-lnput NAND Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM9004C Dual4-lnput NAND Gates. ; . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM9012C Quad 2-lnput NAND'Gates with Open-Collector Outputs . . . . . . . . . . . . . . . . . . . . . . .
DM9016C Hex Inverters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM9024/8024 Dual Positive-Edge-Triggered J-K Flip-Flops with Preset and Clear. . . . . . . . . . . .
DM9300/8300 4-Bit Positive-Edge-Triggered Parallel or Serial Access Shift Registers . . . . . . . .
DM9301/8301 1 of 10 Line Decoders. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .
DM9309/8309 Dual 1 of 4 Line Data Selectors/Multiplexers with
Complementary Outputs .......................................................
DM9310/8310 Synchronous 4-Bit Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM9311/8311 4 to 1 6-Line DecoderslDemultiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM9312/8312 1 of8 Line Data Selector/Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM9316/8316 Synchronous4-Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM9318/8318 8t03 Line Priority Encoders ..................... ;.....................
DM9322/8322 Quad 1 of 2 Line Data Selectors/Multiplexers ....... ,.....................
DM9334/8334 8-Bit Addressable Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM9601/8601 Retriggerable Monostable Multivibrators with Comprementary Outputs .......
DM9602/8602 Dual Retriggerable, Resettable Monostable
Multivibrators with Complementary Outputs .......................................

6·4

6-309
6-312
6-315
6-318
6-321
6-324
6-326
6-329
6·332
6-334
6-337
6·341
6-343
6-346
6-352
6-356
6-359
6-366
6-373
6-376
6-376
6-381
6-381
6-387
6-389
6-391
6-393
6-395
6-397
6-401
6-405
6-408
6-411
6-418
6-422
6-426
6-433
6-437
6-440
6-44~

6-448

r-----------------------------------------------------------------~c

s::

~National

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~ Semiconductor

~

DM2502/DM2502C, DM2503/DM2503C, DM2504/DM2504C
S~ccessive Approximation Registers

s::
~

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c

General Description

I\)

J')
C

Features

The DM2502, DM2503 and DM2504 are a-bit and 12-bit TTL
registers designed for use in successive approximation
AI D converters. These devices contain all the logic and
control circuits necessary (in combination with a D I A converter) to perform successive approximation analog-todigital conversions.
The DM2502 has a bits with serial capability and is not
expandable ..
The DM2503 has a bits and is expandable without serial
capability.

• Complete logic for successive approximation AID
converters
• a-bit and 12-bit registers
• Capable of short cycle or expanded operation
• Continuous or start-stop operation
• Compatible with DI A converters using any logic code
• Active low or active high logic outputs
• Use as general purpose serial-to-parallel converter or
ring counter

Absolute Maximum Ratings

The DM2504 has 12 bits with serial capability and
expandability.

Supply Voltage
Input Voltage
Siorage Temperature Range

All three devices are available in ceramic DIP and molded
Epoxy-B DIPs. The DM2502, DM2503 and DM2504 operate
over - 55·C to + 125·C; the DM2502C, DM2503C and
DM2504C operate over O·C to + 70·C.

(Nole 1)

7V
5.5V
- 65·C 10 150·C

Nola 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagrams
Dual-ln-L1ne Package
VCC

116

Q7

07

15

14

06
13

05
12

Dual-ln-L1ne Package

11

10

9

124

I-

r--

1

vcc all NC 011010 09 08

CP

04

2

(DM2502) OCC

3
00

4
01

5
02

6
03

7

o

DO

23

22

21

20

19

18

07 06
17

NC

16

1

18

E

GND

13

'-

2

3

4

DO OCC 00

5
01

6

7

02

03

8

10

9

04 05

NC

11 112
0

GND

TL/F/6612·2

E
2502 (J)
2503 (J)

CP

14

r-

TLlF/6612·1

(DM2503)

5

15

2504(J)

2502C(N)
2503C(N)

6-5

2504C(N)

s::

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'(J1

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oCot)

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~
~

o

Recommended Operating Conditions
Sym
Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

fCLK

Clock Frequency

tw

Pulse Width

tsu

DM2502

Parameter

Setup Time

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2
O.B

O.B

-0.4B

- O.4B

15

0

0

Clock
Low

42

30

42

30

Clock
High

24

17

24

17

16

9

16

9

B

4

8

4

S Input

Free Air Operating
Temperature

I

-55

DM2502 Electrical Characteristics

125

Units
V
V

9.6

D Input
TA

DM2502C

Min

0

V
mA

9.6

mA

15

MHz
ns

ns

70

·C

over recommended operating free air temperature

(unless otherwise noted)
Sym

Parameter

Conditions

Min

Typ
(Note 1)

2.4

3.6

Max

VI

Input Clamp Voltage

Vcc=Min, 11= -12 mA

VOH

High Level Output
Voltage

Vcc= Min, IOH= Max
VIL = Max, VIH= Min

VOL

Low Level Output
Voltage

Vcc= Min, IOL= Max
VIH = Min, VIL = Max

II

Input Current@ Max
Input Voltage

Vcc = Max, VI = 5.5V

IIH

High Level Input
Current

Vcc= Max
VI = i.4V

Low Level Input
Current

Vcc= Max
VI =0.4V

CP'lnput

-1.6

Others

-3.2

Short Circuit
Output Current

Vcc= Max
(Note 2)

2502

-10

-45

2502C

-10

-45

Supply Current

Vcc= Max

IlL

los

Icc

-1,5

0.2

Units
V
V

0.4

V

1

mA

CP Input

40

/lA

Others

80

2502

65

85

2502C

65

95

Nole 1: Aillypicals are al VCC=5V, TA=25'C,
Note 2: Not more than one output should be shorted at a time.

6·6

mA

mA

mA

I

c

DM2502 Switching Characteristics

s:
N

at Vcc = 5V and TA = 25'C

(See Section 1 for Test Waveforms and Output Load)

(11

o

From
(Input)
'To
(Output)

Parameter

RL = 400{)

C

C L =15 pF

f MAX Maximum Clock
Frequency

Min

Typ

15

21
26

tpLH Propagation Delay
Time Low to High
Level Output

CP
to
Output

10

tp~L Propagation Delay
Time High to Low
. Level Output

CP
to
Output

10

-s:
N

Units

N

(11

Max
MHz
ns

38

~

51
c

s:
N
(11

18

28

ns

o
w

-s:
C

N

(11

o

w

51
c

s:
N
(11

Recommended Operating Conditions
Sym

Supply Voltage

V1H

High Level Input
Voltage

V 1L

Low Level Input
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

fCLK

Clock Frequency

tw

Pulse Width

tsu

TA

Setup Time

Free Air Operating
Temperature

Min
4.5

-s:
~

DM2503

Parameter

Vcc

o

Nom
5

C

DM2503C
Max
5.5

Min
4.75

Nom
5

Max
5.25

0

- 0.48

- 0.48

mA

9.6

9.6

mA

15

MHz

15

0

30

42

30

CP
High

24

17

24

17

S

16

9

16

9

D

8

4

8

4

125

6·7

V

0.8

42

-55

V

0.8

CP
Low

0

ns

ns

70

N

(11

V

2

2

Units

'C

o

~

o

DM2503 Electrical Characteristics

over recommended operating free air temperature

(unless otherwise noted)
Sym

Parameter

Conditions

Min

Typ
(Note 1)

2.4

3.6

Max

VI

Input Clamp Voltage

Vee = Min, 11= -12 mA

VOH

High Level Output
Voltage

Vee = Min, 10H= Max
VIL = Max, VIH= Min

VOL

Low Level Output
Voltage

Vee = Min, 10L= Max
VIH = Min, VIL = Max

II

Input Current@ Max
Input Voltage

Vee = Max, VI = 5.5V

IIH

High Level Input
Current

Vee = Max
VI = 2.4V

CP Input

40

Others

80

Low Level Input
Current

Vcc= Max
V I = 0.4V

.cP Input

-1.6

Others

-3.2

Short Circuit
Output Current

Vee = Max
(Note 2)

2503

-10

-45

2503C

-10

-45

Supply Current

. Vec='Max

. IlL

los

Icc

DM2503 SWitching Characteristics

Units

-1.5

I

V
V

0.2

0.4

V

1

mA

2503

60

80

2503C

60

90

p.A

,
mA

mA

mA

at Vec= 5V and T A = 25°C

(See Section 1 for Test Waveforms and Output Load)

Parameter

From
(Input)
To
(Output)

RL=400n
CL=15 pF

f MAX Maximum Clock
Frequency

Min

Typ

15

21

Units
Max
MHz

tpLH Propagation Delay
Time Low to High
Level Output

CP
to
Output

10

26

38

ns

tpHL Propagation Delay
Time High to Low
.Level Output

CP
to
Output

10

18

28

ns

tpLH Propagation Delay
Time Low to High
Level Output (Note 3)

E
to

13

19

ns

16

24

ns

tpHL Propagation Delay
Time High to Low
Level Output (Note 3)

07
E
to

07

Note 1: All typicals are at Vec=SV. TA=2S'C.
Note 2: Not more than one output should be shorted at a time.

Note 3: CP = high logic level,S = low logic level.

6-8

Recommended Operating Conditions
DM2504C

DM2504
Symbol

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

Min

Nom

Max

4.5

5

5.5

Min

Nom

Max

4.75

5

5.25

V
V

2

2

Units

V

0.8

0.8

High Level Output
Current

-0.48

- 0.48

mA

10L

Low Level Output
Current

9.6

9.6

mA

feLK

Clock Frequency

1.5

MHz

tw

Pulse Width

tsu

TA

Setup Time

15

0

0

CP
Low

42

30

42

30

CP
High

.24

17

24

'17

S

16

9

16

9

0

8

4

8

4

Free Air Operating
Temperature

-55

DM2504 Electrical Characteristics

125

ns

ns

70

0

DC

over recommended operating free air temperature

(unless otherwise noted)
Symbol

Parameter

Conditions

Min

Typ
(Note 1)

2.4

3.6

Max

VI

Input Clamp Voltage

Vee = Min, 11= -12 mA

VOH

High Levei Output
Voltage

Vee= Min, 10H= Max
VIL= Max, VIH = Min

VOL

Low Level Output
Voltage

Vee= Min, 10L= Max
VIH = Min, VIL= Max

II

Input Current@Max
Input Voltage

Vee=Max, VI=5.5V

IIH

High Level Input
Current

Vee = Max
VI=2.4V

Low Level Input
Current

Vee = Max
VI = 0.4V

CP Input

-1.6

Others

-3.2

Short Circuit
Output Current

Vee = Max
(Note 2)

2504

-10

-45

2504C

-10

-45

Supply Current

Vee= Max

2504

90

110

2504C

90

124

IlL

los

lee

-1.5

0.2

Units
V
V

0.4

V

1

mA

CP Input

40

p.A

Others

80

Note 1: All typlcals are at Vee= 5V. TA:=25"e.
Nota 2: Not more than one output should be shorted at a tima.

6·9

mA

mA

rnA

DM2504 Switching Characteristics

a~d TA = 25°C

at Vcc = 5V

(See Section 1 for Test Waveforms and Output Load)
From
(Input)
To
(Output)

Parameter

RL=4000
C L =15 pF
Typ

15

21

10

26

38

ns

10

18

28

ns

13

19

ns

/16

24

ns

fMAX Maximum Clock
Frequency
tpLH Propagation Delay
Time Low to High
Level Output

CP
to
Output

tPHL Propagation Delay
Time High to Low
Level Output

CP
to
Output

tpLH .Propagation Delay
Time Low to High'
Level Output (Note 1)

to
Q11

tpHL Propagation Delay
Time High to Low
L~lIel Output (Note 1)

to
Q11

Units

Min

Max
MHz

!

E

E

Note 1: CP = high logic level, S = low logic level.

Function'Table
Inputs

Time

Outputs (1)

tn

D

S

E (2)

DO (3)

Q7

Q6

Q5

Q4

Q3

Q2

Ql

QO

QCC

0

X

07
06
05
04
03
02
01

X
X

07
06
05
04
03
02
01

06
06
06
06
06
06
06
D6

X
H
H
L

05
05
05
05
05
05
05

X
H
H
H
L

04
04
D4
04
04
04

X
H
H
H
H
L

03
03
03
03
03

X
H
H
H
H
H
L

D2
02
D2
D2

X
H
H
H
H
H
H
L

01
01
01

X
H
H
H
H
H
H
H
L

X

07
07
07
07
07
07
07
07
07

X
H
L

X
X

L
L
L
L
L
L
L
L
L
L
L

X

1

L
H
H
H
H
H
H
H
H
H
X

DO
DO

X
H
H
H
H
H
H
H
H
L,
L

X

X

H

X

H

NC

NC

NC

NC

NC

NC

NC

NC

2
3
4
5
6
7
B
9

10

DO

DO

L

Note 1: FUnction table for DM2504 is extended to include 12 outputs;
Note 2: FUnction table for DM2502 does not include
In function table shown.

Ecolumn or last line

Note 3: Function table for DM2503 does not include DO column.

H

= High Level

L = Low Level
X = Don'l Care
NC = No Change

"

6·10

r
o

CO

c)'
o

iii'

...III

CO

3

r-----------,

DO

(0"2502,
DM2504)

07

Q6

CP~02
~01

o

~

E

1 ~~: ~~:);~ 1

1
1

Q5

1

1
1

-I

1

I

I

QO

Qcc

I r=--=I

ij7----------------~

5--------1

L ___________ J
Note 1: Cell logIc IS repealed lor regIster stages.
0510 01 DM2502, DM2503
09 10 Q 1 DM2504
TLlF/6612-3

::>tOSlWO/tOSlWO '::>£OSlWO/£OSlWO '::>lOSlWOllOSlWO

Timing Diagram
02,03

INPUTS

1

CP

D=.II"'. "_-_-_:..._. . .

~

07r=-]
06r=-]
osr=-]
04r=-]
03r=-]
OUTPUTS

02L=::J
01L=::J

ooL:::J
occL=::J
DO ..L-_...L-_.....I-_-'
TLlF/6612·4

6-12

c

3:

Application Information
OPERATION

EXPANDED OPERATION

N
U1

o

N

An active low enable input, E, on the DM2S03 and DM2S04
allows registers to be connected together to form a longer
register by connecting the clock, D, and S inputs in parallel
and connecting the OCC output of one register to the E input of the next less significant register. When the start signal resets the register, the E signal goes high, forcing the
07 (11) bit high and inhibiting the register from accepting
data until the previous register is full and its OCC goes low.
I! only one register is used the E input should be held at a
low logic level.

The registers consist of a set of master latches that act as
the control elements in the device and change state on the
input clock high-to-low transition and a set of slave latches
that hold the register data and change on the input clock
low-to-high transition_ Externally the device acts as a spe:
cia l purpose serial-to-parallel converter that accepts data
at the D input of the register and sends the data to the appropriate slave latch to appear at the register output and
the DO output on the DM2S02 and DM2S04 when the clock
goes from low-to-high_ There are no restrictions on the data
input; it can change state at any time except during a short
interval centered about the clock low-to-high transition_ At
the same time that data enters the register bit the next less
significant bit register is set to a low ready for the next
iteration_

c

3:
N
U1

o
N

.P
c
3:
N
g:

-c
(0)

SHORT CYCLE
I! all bits are not required, the register may be truncated
and conversion time saved by using a register output going
low rather than the OCC signal to indicate the end of conversion. I! the register is truncated and operated in the continuous conversion mode, a lock-up condition may occur on
power turn-on. This condition can be avoided by making the
start input the OR function of OCC and the appropriate register output.

The register is reset by holding the S (Start) signal low during the clock low-to-high transition_ The register synchronously resets to the state 07 (11) low, and all the remaining
register outputs high_ The OCC (Conversion Complete) sig'nal is also set high at this time. The S signal should not be
brought back high until after the clock low-to-high transition
in order to guarantee correct reselling. After the clock has
,gone high reselling the register, the S must be removed. On
the next clock low-to-high transition the data on the D input
is set into the 07 (11) register bit and the 06 (10) register
bit is set to a low ready for the next clock cycle. On the next
clock low-to-high transition data enters the 06 (10) register bit and as (9) is set to a low. This operation is repeated
for each register bit in turn until the register has been filled.
When the data goes into 00, the OCC signal goes low, and
the register is inhibited from further change until reset by a
Start signal.

COMPARATOR BIAS
To minimize the digital error below ± l1! LSB, the comparator must be biased. If a D 1A converter is used which requires a low voltage level to turn on, the comparator should
be biased +l1! LSB. If the DI A converter requires a high
logic level to turn on, the comparator must be biased
-l1! LSB.
Definition of Terms

(See Timing Diagram)

CP: The clock input of the register.
D: The serial data input of the register.
DO: The serial data out. (The D input delayed one bit).
E: The register enable. This input is used to expand the
length olthe register and when high forces the 07 (11) register output high and inhibits conversion. When not used for
expansion the enable is held at a low logic level (ground).
aj i = 7 (11) to 0: The outputs of the register.
aCC: The conversion complete output. This output rem'ains high during a conversion and goes low when a conversion is complete.
a7 (11): The true output of the MSB of the register.
Q7 (11): The complement output of the MSB of the
register.
S: The start input. If the start input is held low for at least a
clock period the register will be reset to 07 (11) low and aiL
the remaining outputs high. A start pulse that is low for a
shorter period of time can be used if it meets the set-up
time requirements of the S input.

The DM2S02, DM2S03 and DM2S04 have a specially tailored two-phase clock generator to provide non-overlapping two-phase clock pulses (i.e., the clock waveforms
intersect below the thresholds of the gates they drive).
Thus, even at very slow dV 1dt rates at the clock input (such
as frOm relatively weak comparator outputs), improper
logic operation will not result.
LOGIC CODES
All three registers can be operated with various logic
codes. Two's complement code is used by offselling the
compar&tor l1! full range + l1! LSB and using the complement of the MSB (07 or Q11) with a binary D 1A converter.
Offset binary is used in the same manner but with the MSB
(07 or 01'1). BCD D 1A converters can be used with the addition of illegal code suppression logic.
ACTIVE HIGH OR ACTIVE LOW LOGIC
The register can be u·sed with either D 1A converters that
require a low voltage level to turn on, or DI A converters
that require a high voltage level, to turn the switch on. I! D 1A
converters are used which turn on with a low logic level, the
resulting digital output from the register is active low. That
is, a logic" 1" is represented as a low voltage level. I! D 1A
converters are used that turn on with a high logic level then
the digital output is active high; a logic" 1" is represented
as a high voltage level.

6-13

3:

N

g:
(0)

.P
c

3:

N

U1

o.j:Io

c

3:

N

U1

o.j:Io
(')

Typical Applications
BCD Illegal Code Suppression
Active High

Active Low

S

D
CP

S

D

DO
CLOCK

DM2502

DO

DM2502

CLOCK

Occ

Occ

0706050403020100

070605040302Ql00

01 A CONVERTER

Df A CONVERTER
TlIF/6612·5

TLlF16612·6

High Speed 12-BIT AID Converter
5V

J1J1IU

Vcc

OCC

S
DM2504
SAR

DI-----,
Msa

PARALLEL
OUTPUT

+15-------.~------,

~

=

L-r---~L=Sa~~~~~~~~~M~S=a~~

+5------~~~----~
-15 _+__4_-+
'--...----1

l~F~
I

-::-

1~

~
+

0-2mA

-

COMP

10k

REF'N ,REFOUT

'W

>-':~"'JV2'11k'\r-_ +5 V

FV/

AD1200'
10k

r

5V

/

'---1

REF

Y,N

-t- ~ ,
L

OVT010V

6-14

--::-

1.2M
lN914

TLlFf6612·7

en

:e::;:

n

:r

S·

ca

-I

3'
CD

WAVEFORMS

'&lii) MAX

sYfJffU/!

..---+------+--- ..

Must be steady

OUTPUTS

Will be steady

_

_ _ _

~

<
CD

..03(I)

1.5V

Ia(D) MIN

D_

INPUTS

May change trom
HtoL

Will be changing
'rom H to L

May change from
LtoH

Will be changing
from L to H

Don't care: any

Changing: atate
unknown

1.5V

~

07(11)

1.SV

01

'pilI

Q6(10)

'PHLMAX

DO

I

IMMMM

(DM2502. DM2504)

I.

.1
1.SV

~ll!Ir

tpHLMIN

-

(DM2503,DM2504)

E

07(11)

\-

tpLH (E) MAX

fII1l-

change permitted

1.5V

1+
f
l . " , :I

--,-----

•
-

.

_____
tpHL(E)MAX

_1.5V

ENABLE TO 07 (11)
CP=H

S=L

TLlF/6612-B

~tos~wa/tos~wa '~£os~wa/£os~wa '~~os~wa/~os~wa

~ ~National

~ ~ Semiconductor

~

:E
Q

DM5400/DM7400 Quad 2-lnput NAND Gates

General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic NAND function.

Supply Voltage
,Input Voltage
Storage Temperature Range

(Note 1)

7V
5.5V
- 65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table afe not guaranteed at the absolute
maximum ratings. The "Recommended Operating Condltlons"'table will

define the conditions for actual device operation.

Connection Diagram

Function Table

Dual·ln·Line Package
Y=AB

Inputs
B

Y

L
L

L
L

H
H
H

H

L

H
H

H

H = High Logic Level
L
Al

81

VI

A2

B2

V2

GNO

TL/F/6613·1

DM5400 (J)

DM7400 (N)

6·16

Output

A

=Low Logic Level

"

Recommended Operating Conditions
Symbol

DM5400

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level loput
Voltage

IOH

DM7400

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units
V

2

V

0.8

0.8

High Level Output
Current

-0.4

-0.4

mA

IOl

Low Level Output
Current

16

16

mA

TA

Free Air Operating
Temperature

70

·C

-55

Electrical Characteristics

125

over recommended operating free air temperature (unless otherwise noted)

Symbol

Parameter

VI

Input Clamp Voltage

Vee=Min,ll= -12 mA

VOH

High Level Output
Voltage

Vee=Min,loH=Max
Vll= Max

VOL

Low Level Output
Voltage

Vee = Min, IOl= Max
VIH=Min

II

Input Current@Max
input Voltage

IIH

\

0

V

Conditions

Typ
(Note 1)

Min

Max
-1.5

2.4

3.4
0.2

Units

V
V

0.4

V

Vee = Max, VI = 5.5V

1

mA

High Level Input
Current

Vee=Max, VI=2.4V

40

/LA

III

Low Level Input
Current

Vee = Max, VI = O.4V

-1.6

mA

los

Short Circuit
Output Current

Vcc=Max
(Note 2) ,

-20

-55

mA

-18

-55

ICCH

Supply Current With
Outputs High

Vcc=Max

4

8

mA

Icel

Supply Current With
Outputs Low

Vec=Max

12

22

mA

.

Switching Characteristics
Parameter

I
I

DM54
DM74

at Vee = 5V and TA= 25·C (See Section 1 for Test Waveforms and Output Load)
Cl=15 pF
Rl=400!1

Conditions
Min

Units

Typ

Max

tplH Propagation Delay Time
Low to High Level Output

12

22

n5

tpHl Propagation Delay Time
High to Low Level Output

7

15

n5

Notol: All typical. are at Vce=5V. TA=25"e.
Nota 2: Not more than one output should be shorted at a time.

6·17

~

r-----------------------------------------------------------------------------------,

~ ~National
~ .~ Semiconductor

~

~ DM5401/DM7401 Quad 2-lnput NAND Gates

:E

c with Open-Collecto~ Outputs
General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic NAND function. The open·
collector outputs require external pull·up resistors for
proper logical operation.

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

Pull·Up Resistor Equations

(N~te 1)
7V

s.sv
7V
-6S'C to 150'C

Nale 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

RMIN= Vcc(Max) - VOL
10L - N3 (III)

Where:

N1 (IOH) = total maximum output high current
for all outputs tied to pull-up resistor
N2 (lIH) = total maximum input high current for
all inpl!.!S tied to pull-up resistor
N3 (lIU = total maximum input low current for
all inputs tied to pull-up resistor

.Function Table

Connection Diagram
Dual-In-Line Package
AJ

Y=AB
Inputs
B

Y

L
L
H
H

L

H

H
H

L
H

H
L

H = High Logic Level
L = Low Logic Level
VI

AI

B1

V2

A2

B2

GNO

TLlF/6614·1

DM5401 (J)

DM7401 (N)

6-18

Output

A

c

"

s:

Recommended Operating Conditions
Symbol

U1

DM5401

Parameter

Min

DM7401

Nom

Max

Min

Nom

Max

5

5.25

Units
V

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low,Level Input
Voltage

0.8

0.8

V

VOH

High Level Output
Voltage

5.5

5.5

V

10L

Low Level Output
Current

16

16

mA

TA

Free Air Operating
Temperature

70

·C

4.5

Parameter

4.75

V

2

-55

Electrical Characteristics
Symbol

5.5

5

2

125

0

over recommended operating free air temperature (unless otherwise noted)
Conditions

Typ
(Note 1)

Min

VI

Input· Clamp Voltage

leEx

High Level Output
Current

Vee=Min, Vo=5.5V
VIL= Max

VOL

Low Level Output
Voltage

Vee = Min, 10L = Max
VIH = Min

II

Input Current@Max
Input Voltage

IIH

Max

Units

-1.5

V

250

flA

0.4

V

Vee = Max, VI = 5,5V

1

mA

High Level Input
Current

Vee= Max, VI =2.4V

40

flA

IlL

Low Level Input
Current

Vee = Max, VI = 0.4V

-1.6

rnA

leeH'

Supply Current With
Outputs High

Vee=Max

4

8

mA

leeL

Supply Current With
Outputs Low

Vee=Max

12

22

rnA

Vee=Min,ll= -12 rnA

0,2

,

Switching Cha,racteristics
Parameter

at Vee = 5V and TA =25·C (See Section 1 for Test Waveforms and Output Load)
CL=15pF
RL 4 k!l (tpLH)
RL 400!l (tpHLl

=
=

Conditions
Min

Units

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

35

45

ns

tpHL Propagation Delay Time
High to Low Level Output

8

15

ns

Not. 1:

Aillypicals are al Vee =5V, TA =25'e,
6·19

8....

-s:
C

""-J
./:>.

o
....

· C'\I

~ ~NaHonal

~ ~ Semiconductor

~:E

o

DM5402/DM7402 Quad 2-lnput NOR Gates

General Description

Absolute Maximum Ratings

This device contains ·four independent gates each of
which performs the logic NOR function.

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)
7V

5.5V
-65·Cto150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram ,

Function Table

Dual-In-Line Package

Y=A+B
AJ

Inputs

B

Y

-L
L
H
H

L
H
L
H

H
L
L
L

H = High Logic Level

L= Low Logic Level

VI

AI

B1

V2

A2

B2

GNo

TLfF/6492·1

DM5402 (J)

DM7402 (N)

6-20

Output

A

Recommended Operating Conditions
Symbol
Vcc

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level Input
Voltage

10H

High Level Output
Current

IOl

Low Level Output
Current

TA

Free Air Operating
Temperature

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

Units
V
V

0.8

0.8

-0.4

-0.4

mA

16

mA

70

·C

16 .
-55

Electrical Characteristics
Symbol

DM7402

DM5402

Parameter

125

0

V

over recommended operating free air temperature'(UnleSS otherwise noted)

Parameter

Conditions

VI

Input Clamp Voltage

Vcc= Min, 11= -12 mA

VOH

High Level Output
Voltage

Vcc= Min, IOH= Max
Vll = Max

Val

Low Level Output
Voltage

Vcc= Min, 10l= Max
VIH=Min

II

Input Current@ Max
Input Voltage .

IIH

Min

Typ
(Note 1)

2.4

3.4

Max
-1.5

Units
V
V

0.4

V

Vcc= Max, VI = 5.5V

1

mA

High Level Input
Current

Vcc=Max, VI=2.4V

40

p.A

III

Low Level Input
Current

v.cc = Max, VI = O.4V

-1.6

mA

los

Short Circuit
Output Current

Vcc= Max
(Note 2)

-20

- 55

mA

-18

-55

ICCH

Supply Current With
Outputs High

Vcc= Max

8

16

mA

ICCl

Supply Current With
Outputs Low

Vcc= Max

14

27

mA

Switching Characteristics
Parameter

0.2

I DM54
I DM74

at Vcc= 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
CL =15 pF
Rl=400n

Conditions

Units

Typ

Max

tplH Propagation Delay Time
Low to High Level Output

12

22

ns

fpHl Propagation Delay Time
High to Low Level Output

8

15

ns

Min

Nole 1: All typicals are at VCC=SV. TA=2S"C.
Nole 2: Not more than one output should be shorted at a time.

6·21

Mr------------------------------------------------------------------------,

~, ~ National
- ~ Semiconductor
c

M

~
Ln

C
==

DM5403/DM7403 Quad 2-lnput NAND Gates
with Open-Collector Outputs

General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic NAND function. The opencollector outputs require external pull-up resistors for
proper logical operation.

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

Pull·Up Resistor Equations

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed, The device should
not be operated at these limits. The parametric values defined in the

RMAX = Vcc (Min) - VOH
Nt (IOH) + N2 (lIH)

UElectrical Characteristics" table are not guaranteed at the absolute

7V
5.5V

7V
-65°C to 150·C

m'axlmum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation,

RMIN= Vcc(Max)-VOL
10L - N3 (IIIJ '

Where:

=

Nt (IOH) total maximum output high current
for all outputs tied to pull-up resistor
N2 (lIH) = total maximum Input high current for
all inputs tied to pull-up resistor
N3 (III) = total maximum input low current for
all inputs tied to pull-up resistor

Connection Diagram

Function Table

Dual-In-Line Package

Inputs

B1

"
DM5403 (J)

.2

82

V2

GNO

TL/F/6493·1

DM7403 (N)

6·22

Output

A

B

Y

L
L
H
H

L
H

H
H
H
L

'L

H

,H = High Logic Level
L = Low Logic Level
AI

(Note 1)

Recommended Operating Conditions
Symbol

DM7403

DM5403

Parameter

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units
V

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

0.8

0.8

V

VOH

High Level Output
Voltage

5.5

5.5

V

10L

Low Level Output
Current

16

16 .

mA

TA

Free Air Operating
Temperature

70

·C

-55

Electrical Characteristics
Symbol

2

2

125

0

over recommended operating free air temperature (unless otherwise noted)
Conditions

Parameter

V

Typ
(Note 1)

Min

Max

Units

-1.5

V

250

/LA

0.4

V

Vcc=Max, VI =5.5V

1

mA

High Level Input
Current

Vcc=Max, V·I=2.4V

40

/LA

IlL

Low Level Input
Current

Vcc=Max, VI =0.4V

-1.6

mA

ICCH

Supply Current With
Outputs High

Vcc=Max

4

8

mA

ICCL

Supply Current With
Outputs Low

Vcc=Max

12

22

mA

VI

Input Clamp Voltage

Vcc=Mln, 11= -12mA

ICEX

High Level Output
Current

Vcc=Min, Vo=5.5V
VIL=Max

VOL'

Low Level Output
Voltage

Vcc=Min,loL=Max
VIH=Mln

II

Input Current@Max
Input Voltage

IIH

Switching Characteristics
Parameter

0.2

at Vcc = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
CL=15 pF
RL = 4 kO (tpLHI
RL = 4000 (tpHU

Conditions
Min

i PLH Propagation Delay Time

Units

Typ

Max

35

45

ns

8

15

ns

Low to High Level Output
tpHL Propagation Delay Time
High to Low Level Output
Nol.l:

Aillypicals are al vcc=sv. TA=2S"C.
6·23

~ ~National

-~ ~ Semiconductor
or:t
or:t

o

It)

:E

c

DM5404/DM7404 Hex Inverting Gates
General Description'

Absolute Maximum Ratings

This device contains six Independent gates each of
which performs the logic INVERT function,

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)
7V
S,SV

- 6S·C to 1S0·C

Nota 1: The "Absolule Maximum Ratings" are Ihose values beyond
which Ihe safely of Ihe device can nol be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" lable are nol guaranleed at Ihe absolute
maximum ralings. The "Recommended Operallng Conditions" lable will
define th~ conditions for actual device operation.

Connection Diagram

Function Table

Dual·ln·Line Package

T,.

AG

V6

I

1

v,

J

A'

V.

,

9

L{>o-

rt>o-

-(>0-

A.

1D

"

4>0--

Al

V5

A'

12

13

Y=A

l{)o-

r!>o•

V,

,
V3

G!:

Tl/F/6494·1

DM5404(J)

Output

A

Y

L

H

H

L

H = High Logic Level
L = Low Logic Level

,
A3

Input

DM7404 (N)

6·24

r---------------------------------------------------------------------~c

s:
C1'I

Recommended Operating Conditions

.1:10

Symbol

DM5404

Parameter

Vcc

Supply Voltage

V'H

High Level Input
Voltage

V'L

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units

~

V

0.8

0.8

-0.4

-0.4

mA

16

16

mA

70

°C

.1:10

V

,

Parameter

125

0

over recommended operating free air temperature (unless otherwise noted)
Conditions

Min

Typ
(Note 1)

2.4

3.4

Max

Units

V,

Input Clamp Voltage

VOH

High Level Output
Voltage

Vcc=Min,loH=Max
V'L= Max

VOL

Low Level Output
Voltage

Vcc = Min, 10L = Max
V'H=Min

I,

Input Current@Max
Input Voltage

I'H

High Level Input
Current

I'L

Low Level Input
Current

.105

Short Circuit
Output Current

Vcc= Max
(Note 2)

ICCH

Supply Current With
Outputs High

Vcc=Max

6

12

. mA

ICCL

Supply Current With
Outputs Low

Vcc= Max

18

33

mA

-1.5

Vcc=Min, 1,= -12mA

,

V

Vcc = Max, V, = 5.5V

1

mA

Vcc= Max, V, =2.4V

40

ILA

'Vcc = Max, V, = O.4V

-1.6

mA
mA

Switching Characteristics
Parameter

V
V

0.4

I
I

0.2

DM54

-20

-55

DM74

-18

-55

at Vcc = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
-

Conditions

CL =15 pF
RL=400n

Units

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

12

22

ns

tpHL Propagation Delay Time
High to Low Level Output

8

15

ns

Min

Notal: All typica's are at VCC=5V. TA=25"C.
Note 2: Not more than one output should be shorted at a time.

6·25

.1:10

C

s:
......

V

2

-55

Electrical Characteristics
Symbol

Min

2

o

DM7404

~r---------------------------------------------------~------------------~

~ ~National
~ ~ Semiconductor

~

~ DM5405/DM7405 Hex Inverters

:iiE
c

with Open-Collector Outputs
General Description

Absolute Maximum Ratings

This device contains six. independent gates each of
which performs the logic INVERT function. The opencollector outputs require external pull-up resistors for
proper. logical operation.

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

7V
S.SV
7V
- 6S·C to 1S0·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will

Pull·Up Resistor Equations
RMAX= Vcc(Min)-VOH
N1 (IOH)+ N2 (IIH)

define the conditions for actual device operation.

RMIN= Vcc(Max) - VOL
10L - N3 (111..1
Where:

N1 (IOH) = total maximum output high current
for all outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for
all inputs tied to pull-up resistor
N3 (lILl = total maximum input low current for
all inputs tied to pull-up resistor

Connection Diagram

--

Function Table

Dual-In-Line Package

J

A6

14

YO

IJ

A5

Y5

11

11

A'

,

10

Y4

8

Input

-{>o-

-{>o-

rt»

ri>o1
A1

2
Y1

l

A2

-{>o-

ri>o,

V2

AJ

J:

TL/F/649S-1

DM5405 (J)

Y

L
H

H
L

L = Low Logic Level

YJ

DM7405 (N)

6-26

Output

A

H = High Logic Level

6

5,

(Note 1)

c

s:
c.n

Recommended Operating Conditions

.;..

Symbol

DM5405

Parameter

DM7405

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units

Vee

Supply Voltage

V IH

High Level Input
Voltage

V IL

Low Level Input
Voltage

0.8

0.8

V

VOH

High Level Output
Voltage

5.5

5.5

V

IOL

Low Level Output
Current

16

16

mA

TA

Free Air Operating
Temperature

70

"C

2

-55

Electrical Characteristics
Symbol

Parameter

V

2

125

V

0

over recommended operating free air temperature (unless otherwise noted)
Conditions

Typ
(Note 1)

Min

VI

Input Clamp Voltage

Vee=Min, 11= -12mA

leEX

High Level Output
Current

Vee= Min, Vo=5.5V
VIL = Max

VOL

Low Level Output
Voltage

Vec=Min,loL=Max
V IH = Min

II

Input Current@Max
Input Voltage

IIH

Max

Units

-1.5

V

250

Il A

0.4

V.

Vcc = Max, VI = 5.5V

1

mA

High Level Input
Current

Vcc = Max, VI = 2.4V

40

Il A

·IIL

Low Level Input
Current

Vcc = Max, VI = O.4V

-1.6

mA

ICCH

Supply Current With
Outputs High

Vcc=Max

6

12

mA

IccL

Supply Current With
Outputs Low

Vcc= Max

18

33

mA

Switching Characteristics

0.2

at Vcc = 5V and TA = 25"C (See Section 1 for Test Waveforms and Output Load)

,
Parameter

Conditions·
Min

CL=15 pF
RL = 4 kn (tpLH)
RL = 400n (tpHU

Units

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

40

55

ns

tpHL Propagation Delay Time
High to Low Level Output

8

15

ns

Nole1: All typicals are at VCC=5V, TA=25'C.

6·27

-s:
o
c.n
C

......
~
c.n

~r------------------------------------------------------------------,

~ ~National

~ ~ Semiconductor

~:E
c

DM5406/DM7406 Hex Inverting Buffers with
High Voltage Open-Collector Outputs
General Description

Absolute Maximum Ratings

This device contains six independent buffers each of
which performs the logic INVERT function. The open·
collector outputs require external pull·up resistors for
proper logical operation.

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

Pull·Up Resistor Equations

7V

5.5V
30V
-65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The ~)arametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

. Vo(Min)-VOH
RMAX = N1 (IOH) + N2 (IIH)

Where:

N1 (IOH) = total maximum output high cunent
for all outputs tied to pull·up resistor
N2 (IIH) = total maximum input high current for
all inputs tied to PUII·UJ> resistor
N3 (III) = total maximum input low current for
all inputs tied to pull·up resistor

Connection Diagram

Function Table

Dual·ln·Line Package

T

A'
13

14

"12

VS

-{>o-

VI

AZ

,

Y=A

V.
8

l..j>o.

6

V,

A3

V3

TLfF/6496·1

DM5406 (J)

Input

Output

A
L

Y
H

H

L

H = High Logic Level
L = Low Logic Level

-{>o-

3

AI

A.

1D

11

l..j>o.

4::x>-{>o-

AS

(Note 1)

DM7406 (N)

6·28,

Recommended Operating Conditions
DM5406

<

Symbol

Parameter

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

0.8

0.8

V

V OH

High Level Output
Voltage

30

30

V

IOL

Low Level Output
Current

30

40

mA

TA

Free Air Operating
Temperature

70

·C

2

Symbol

2

-55

Electrical Characteristics

-

DM7406

Min

Parameter

125

V
V

0

over recommend~d operating free air temperature (unless otherwise noted)
Conditions

Typ
(Note 1)

Min

Max

Units

VI

Input Clamp Voltage

Vcc = Min, II = -12 mA

-1.5

V

ICEX

High Level Output
Current

Vcc=Min, Vo=30V
VIL=Max

250

p.A

VOL

Low Level Output
Voltage

Vcc= Min, IOL= Max
VIH=Min

0.7

V

IOL=16mA
Vcc=Min

0.4

II

Input Current@Max
Input Voltage

Vcc=Max, VI=5.5V

1

mA

IIH

High Level Input
Current

Vcc=Max, VI=2.4V

40

p.A

IlL

Low Level Input .
Current

Vec = Max, VI = 0.4V

-1.6

mA

ICCH

Supply Current With
Outputs High

Vee = Max

30

42

mA

ICCL

Supply Current With
Outputs Low

Vcc=Max

27

38

mA

SWitching Characteristics
Parameter

at Vcc = 5V and TA =.25·C (See Section 1 for Test Waveforms and Output Load)
CL=15 pF
RL = 1101l

Conditions

Units

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

10

15

ns

tpHL Propagation Delay Time
High to Low Level Output

15.

23

ns

Min

Note 1:

All typicals are at VCC=5V, TA=25·C.

6·29

~.------------------------------------------------------------------,

~ ~National
~ ~ Semiconductor

~

~

~ DM5407/DM7407 Hex Buffers with
High Voltage Open-Collector Outputs

o

General Description

Absolute Maximum Ratings

This device contains six independent gates each of
which performs a buffer function. The open-collector
outputs require external pull·up resistors for proper
logical operation.

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

Pull·Up Resistor Equations

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device shoulc
not be operated' at these limits. The parametric values defined in the
"Elect'rical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions far actual device operation.

R

MAX=

Vo (Min) - VOH
N1 (IOH) + N2 (IIH)

7V

5.5V
30V
- 65·C to 150·C

N1 (IOH) = total maximum output high cllrrent
for all outputs tied to pull·up resistor
N2 (lIH) = total maximum Input high current for
all inputs tied to pull-up resistor
N3 (IIJ = total maximum input low current for
all inputs tied to pull-up resistor

Where:

Connection Diagram

.Function Table
Y=A

Dual-In-Line Package

T

v.

AS

12

IJ

14

AS

YO

11

A.

,

ID

-1>-

-f>-

v.

•

-1>-

=

Input

Output

A

Y

L

L

H

H

H High logic Level
L = Low Logic Level

-1>I

A'

rC>2

v,

l
A2

ri>4

V2

5

Al

6

Vl

J:

TlIF16497·1

DM5407(J)

DM7407 (N)

6-30

(Note 1)

Recommended Operating Conditions
Symbol

DM5407

Parameter

DM7407

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

0.8

0.8

V

V OH

High Level Output
Voltage

30

30

V

IOL

Low Level Output
Current

30

40

mA

TA

Free Air Operating
Temperature

70

·C

-55

Electrical Characteristics
Symbol

2

2

Parameter

125

V
V

0

over recommended operating free air temperature (unless otherwise noted)
Conditions

Typ
(Note 1)

Min

Max

Units

VI

Input Clamp Voltage

Vcc=Min,II=-12mA

-1.5

V

ICEX

High Level Output
Current

Vcc=Min, Vo=30V
VIH = Min

250

p.A

VOL

Low Level Output
Voltage

Vcc = Min, IOL = Max
VIL = Max

0.7

V

IOL=16 mA
Vcc=Min

0.4

II

Input Current@ Max
Input Voltage

Vcc=Max, VI=5.5V

1

mA

IIH

High Level Input
Current

Vcc = Max, VI = 2.4V

40

p.A

IlL

Low Level Input
Current

Vcc = Max, VI';' 0.4V

-1.6

mA

ICCH

Supply Current With
Outputs High

Vcc=Max

29

41

mA

IccL

Supply Current With
Outputs Low

Vcc=Max

21

30

mA

.Switching Characteristics
Parameter

,.

at Vcc=5V and TA=25·C (See Section 1 for Test Waveforms and Output Load)
CL =15pF
RL = 110n

Conditions

Units

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

6

10

ns

tpHL Propagation Delay Time
High to Low Level Output

20

30

ns

Min

Note 1:

All typicals are at VCC = 5V. TA = 25°C.

6-31

=r------------------------------------------------------------------------,

~ ~National
~ ~ Semiconductor

~
II)

~

c

DM5408/DM7408 Quad 2-lnput AND Gates

General' Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic AND ·function.

Supply Voltage
Input Voltage

(Note 1)
7V

5.5V
- 65·C to 150·C

Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beY9nd
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the- absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

,Function Table

Dual-In-Line Package
Vee

B.

A.

. Y'

B3

A3

Y3

Y=AB
Inputs

B

Y

L
L
H
H

L
H
L
H

L
L
L
H

H = High Logic Level
L= Low Logic Level
AI

Bl

Yl

A2

B2

Y2

GND

TLIF/6498-1

DM5408 (J)

DM7408 (N)

6·32

Output

A

c

S
(J1

Recommended Operating Conditions

.j:o,

·Symbol

DM5408

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low- Level Input
Voltage

10H

High Level Output
Current

10l

Low Level Output
Current

TA

Free Air Operating
Temperature

o

DM7408

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units
V

2

V
V

0.6

0.6

-0.6

-0.6

mA

16

16

mA

70

.oC

125

-55

0

-

Electrical Characteristics
Symbol

over recommended operatin? free air temperature (unless otherwise noted)

Parameter

Conditions

VI

Input Clamp Voltage

Vee = Min, 11= -12 rnA

VOH

High Level Output
Voltage

Vee=Min,loH=Max
Vll=Max

VOL

Low Level Output
Voltage

Vee= Min, 10l= Max
VIH-=Min

II

Input Current@Max
Input Voltage

IIH

Min

Typ
(Note 1)

2.4

3.4

Max
-1.5

Units
V
V

0.4

V

Vee = Max, VI=5.5V

1

mA

High Level Input
Current

Vee=Max, VI =2.4V

40

,

p.A

III

Low Level Input
Current

Vee = Max, VI = 0.4V

-1.6

mA

los

Short Circuit
Output Current

Vee= Max
(Note 2)

mA

leeH

Supply Current With
Outputs High

Vee= Max

11

.21

mA

leel

Supply Current With
Outputs Low

Vee=Max

20

33

mA

Switching Characteristics
Parameter

0.2

DM54

-20

-55

I'DM74

-16

-55

1

at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
Cl =15 pF
Rl =4000

Conditions

Units

Typ

Max

tplH Propagation Delay Time
Low to High Level Output

17

27

ns

tpHl Propagation Delay Time
High to Low Level Output

12

19

ns

Min

Not. 1: All typicals are at Vee; 5V, TA; 25°C.
Note 2: Not more than one output should be shorted at a time.

6·33

CO

C

S
......

S
CO

~ ~Nalional

~ ~ Semiconductor

-~
en

:iE

c DM5409/DM7409 Quad 2-lnput AND Gates

with

Open-C~lIector

Outputs

General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic AND function. The open·
collector ou·tputs require external pull-up resistors for
proper logical operation.

Supply Voltage

7V

Input Voltage
Output Voltage

5.5V

Pull·Up Resistor Equations

(Note 1)

7V

- 65·C to 150·C

Storage Temperature Range

Note ,: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can nol be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Vcc(Max)-VOL
R
MIN=
IOL - N3 (111.1

Where:

N, (IOH) = total maximum output high current
for all outputs tied to pull-up resistor
N2 (lIH) = total maximum input high current for
all inputs tied to pull-up resistor
N3 (111.1 = total maximum input low current for
all inputs tied to pull-up resistor

Connection Diagram.

Function Table

Dual-In-Line Package
84

.4

Y4

83

A3

Y=AB

Y3

Inputs

B

Y

L
L
H
H

L
H

L
L

L

L

H

H

H = High Logic Level
L= Low Log ie Level
A1

81

Y1

DM5409(J)

A2

82

Y2
GND
TlIFf6499·1

DM7409 (N)

6-34

Output

A

Recommended Operating Conditions
Symbol

DM5409
Parameter

DM7409

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units
V

Vee

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level Input
Voltage

O.B

O.B

V

VOH

High Level Output
Voltage

5.5

5.5

V

10l

Low Level Output
Current

16

16

mA

TA

Free Air Operating
Temperature

70

·C

2

-55

Electrical Characteristics
Symbol

2

Parameter

125

V

0

over recommended operating free air temperature (unless otherwise noted)
Conditions

Typ
(Note 1)

Min

VI

Input Clamp Voltage

Vee=Min, 11= -12 mA

leEx

High Level Output
Current

Vee=Min, Vo=5.5V
VIH=Min

VOL

Low Level Output
Voltage

Vee = Min, IOL = Max
VIL = Max

II

Input Current@Max
Input Voltage

IIH

Max

Units

- i,5

V

250

p.A

0.4

V

Vee = Max, VI = 5.5V

1

mA

High Level Input
Current

Vee = Max, VI = 2.4V

40

p.A

III

Low Level Input
Current

Vee = Max, VI=0.4V

-1.6

mA

leeH

Supply Current With
Outputs High

Vee= Max

11

21

mA

leel

Supply Current With
Outputs Low

Vee=Max

20

33

mA

SWitching Characteristics
Parameter

0.2

at Vee = 5V and TA= 25·C (See Section 1 for Test Waveforms and Output Load)
CL =15 pF
Rl=400!l

Conditions
Min

Units

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

21

32

ns

tpHl Propagation Delay Time
High to Low Level Output

16

24

ns

Note 1:

All

typi'cals are at

Vee = 5V, TA = 2S·C.

I

6-35

o

~ ~National
~ ~ Semiconductor

oT""

~
Lt)

:i

c

DM5410/DM7410 Triple 3-lnput NAND Gates
General Description

Absolute Maximum Ratings

This device contains three Independent gates each of
which performs the logic NAND function.

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)
7V
5.5V

- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond

which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Y=ABC

Dual·ln·Line Package

T
14

C1
13

12

CJ

BJ

11

2
81

3

A2

10

VJ

A(!I

Inputs

8

~~

bJ

,
A'

)'

82

ct5

C

y

X
X

X

L

L

X

X
X

H

H

H
H
H
L

H = High LogiC Level
L = Low Logic Level
X = Either Low or High Logic Level

X J:
TLlF16500·1

DM5410 (J)

B

L
H

~

,

Output

A

DM7410 (N)

6·36

c
3:

Recommended Operating Conditions

C1I

....
.j::o,

Sym

DM5410

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VII:

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

•

2

-0.4
16
-'55

Parameter

125

Units
V
V

0.8

Electrical Characteristics
Sym

DM7410

0

0.8

V

-0.4 .

mA

16

mA

70

·C

over recommended operating free air temperature (unless otherwise noted)
Conditions

VI

Input Clamp Voltage

Vcc= Min, II = -12 mA

VOH

High Level Output
Voltage

Vcc=Min,loH=Max
VIL=Max

VOL

Low Level Output
Voltage

Vce = Min, 10L = Max
VIH=Min

II

Input Current@Max
Input Voltage

IIH

Min

Typ
(Note 1)

2.4

3.4

Max
-1.5

Units
V
V

0.4

V

Vcc =' Max, VI = 5.5V

1

mA

High Level Input
Current

Vec = Max, VI = 2.4V

40

fiA

IrL

Low Level Input
Current

Vee = Max, VI = 0.4V

-1.6

mA

los

Short Circuit
Output Current

Vcc= Max
(Note 2)

mA

lecH

Supply Current With
Outputs High

Vee = Max

3

6

mA

leCL

Supply Current With
Outputs Low

Vee = Max

9.

16.5

mA

Switching Characteristics
Parameter

I

I

0.2

DM54

-20

-55

DM74

-18

-55

at Vee = 5V and T A = 25·C (See Section 1 for Test Waveforms and Output Load)
CL =15 pF
RL=400{J

Conditions
Min

tpLH Propagation Delay Time
Low to High Level Output
tpHL Propagation Delay Time
High to Low Level Output

,

Note 1: All typicals are at Vee=5V, TA=25"C.
Note 2: Not more than one output should be shorted at a time.

6-37

Units

Typ

Max

11

22

ns

7

15

ns

o

c
3:

~
o

....

~
~

r------------------------------------------------------------------------------------,

.... ~National
:!E
~

-c ~ Semiconductor
~

~

;1)
:!E

c DMS41,1/DM7411 Triple 3-lnput AND Gates
Gene'ral Description

Absolute Maximum Ratings

This device contains three',independent gates each of
which performs the logic AND function,

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

7V

5,5V
- 65·C to 150·C·

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual-In-Line Package

T
14

I

C1
13

YI~12

B3

OJ
11

J
,
BI

3
A'

YJ

Y=ABC

B

LhB'

Inputs

ct

y

X

L

L

X

X
X

H

H

L
L
L
H

B

X
X

H = High Logic Level

1 J:
6

L= Low Logic Level
X = Eilher Low or High Logic Leve'

TL/F/6S0H

DM5411 (J)

Output

C

A

L
H

~

4

5

AI

A(g

1D

DM7411 (N)

6-38

c

s:
en

Recommended Operating Conditions
Sym
Vee

Parameter
Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

.j:>.

DM5411

......
......

DM7411

Min

,Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units

-s:

V

.j:>.

V

2

V

0.8

0.8

High Level Output
Current

-0.8

-0.8

mA

10L

Low Level Output
Current

16

16

mA

TA

Free Air Operating
Temperature

70

'c

-55

Electrical Characteristics
Sym

125

0

over recommended operating free air temperature (unless otherwise noted)

Parameter

Conditions

VI

Input Clamp Voltage

Vee = Min, 11= -12 mA

VOH

High Level Output
Voltage

Vee=Min,loH=Max
VIH = Min

VOL

Low Level Output
Voltage

Vee= Min, 10L= Max
VIL = Max

II

Input Current@Max
Input Voltage

IIH

Min

Typ
(Note 1)

2.4

3.4

Max
-1.5

Units
V
V

0.4

V

Vee = Max, VI = 5.5V

1

mA

High Level Input
Current

Vee=Max, VI=2.4V

40

I'A

IlL

Low Level Input
Current

Vee=Max, VI = O.4V

-1.6

mA

los

Short Circuit
Output Current

Vee= Max
(Note 2)

-20

-55

mA

-18

-55

leeH

Supply Current With
Outputs High

Vcc=Max

8

15

mA

ICCL

Supply Current With
Outputs Low

Vcc= Max

14

22

mA

SWitching Characteristics
Parameter

0.2

I DM54

I DM74

at Vcc = 5V and TA= 25'C (See Section 1 for Test Waveforms and Output Load)
CL =15 pF
RL =4000

Conditions

Units

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

17

27

ns

tpHL Propagation Delay Time
High to Low Level Output

12

19

ns

Min

Note 1: All typicals are at VCC=SV. TA=2S'C.
Note 2: Not more than one output should be shorted at a time.

6·39

C

......
......
......

CO)

~ ~NaHonal
~ ~ Semiconductor

CO)
,..

"d"

It)

:i!
o DM5413/DM7413 Dual 4-lnput NAND Gates

with Schmitt Trigger Inputs
General Description

Absolute Maximum Ratings, (Note 1)

This device contains two independent gates each of
which performs the logic NAND function. Each input
has hysteresis which increases the hoise immunity and
transforms a slowly changing input signal to a fast
changing, jitter free output.

Supply Voltage
Input Voltage
Storage Temperature Range

7V

5.5V
- 65·C to 150·C

Not8 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the ~onditions for actual device operation.

Connection Diagram

Function Table
,

Dual-In-Line Package

]:

14

D2

C2

11

13

T

Y=ABCD
Y1

B2

11

10

,

T9

'h
,

1

)c

4

3

AI

"

DM5413 (J)

C1

,
0'

~
6
J1

Output

Inputs
A

B

C

D

Y

X
X
X

X
X

X

L

L

L

L
H

X

X
X

X
X
X

H

H

H

H
H
H'
H
L

H; High Logic Level
L", Low Logic Level
X; Either Low or High Logic Level

G!:

TLlF/6502·1

DM7413 (N)

6-40

c
s::

Recommended Operating Conditions
DM5413
Parameter

Sym

~
.....
Co)

DM7413

Units

Min

Nom

Max

Min

Nom

Max

Vee

Supply Voltage

4.5

5

5.5

4.75

5

5.25

V.

VT+

Positive·Going Input
Threshold Voltage (Note 1)

1.5

1.7

2

1.5

1.7

2

V

VT_

Negative·Going Input
Threshold Voltage (Note 1)

0.6

0.9

1.1

0.6

0.9

1.1

V

HYS

Input Hysteresis (Note 1)

0.4

0.8

0.4

0.8

10H

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

Parameter

-0.8

mA

16

16

mA

70

·C

)

-55

Electrical Characteristics
Sym

V

-0.8

125

0

over recommended operating free air temperaiure (unless otherwise noted)
Conditions

Min

Typ
(Note 2)

2.4

3.4

Max
-1.5

Units

VI

Input Clamp Voltage

Vee = Min, 11= '- 12 mA

VOH

High Level Output
Voltage

Vee = Min, 10H = Max
VI=VT_Min

VOL

Low Level Output
Voltage

Vee = Min, IciL= Max
VI = VT+ Max

IT+

Input Current at
Positive-Going
Threshold

Vee=5V, VI=VT+

-0.65

mA

IT_

Input Current at
Negative·Going
Threshold

Vee=5V, VI=VT_

-0.85

mA

II

Input Current@Max
Input Voltage

Vee = Max, VI = 5.5V

1

mA

IIH

High Level Input
Current

Vee = Max, VI = 2.4V

40

p.A

IlL

Low· Level Input
Current

Vee=Max, VI=0.4V

-1.6

mA

los

Short, Circuit
Output Current

Vee=Max
(Note 3)

mA

leeH

Supply Current With
Outputs High

Vee = Max

14

23

mA

leeL

Supply Current With
Outputs Low

Vee=Max

20

32

mA

Nota 1:

0.2

V

, 0.4

DM54

-18

-55

DM74

-18

-55

Vee = 5V.

Nota 2: Aillypicals are al Vee=5V. TA=25'e.
Note 3: Not more than one output should be shorted at a time.

6-41

V

V

C

s::
:i:!
.....
Co)

Switching Characteristics
Parameter

at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
CL=15pF
RL = 40011

Conditions

Units

Typ

Max

tpLH Propagation Delay Time
Low t6 High Level Output

18

27

ns

tpHL Propagation Delay Time
High to Low L!lvel Output

15

22

ns

Min

,

-

\

\.

6·42

.---------------------------------------------------------------'0
:s:
~National

....~

~ Semiconductor

e
o
:s:
-'....
"""="

DM5414/DM7414 Hex Inverter with
Schmitt Trigger Inputs

-'="

General Description

Absolute Maximum Ratings

This device contains six independent gates each of
which performs the logic INVERT function. Each input
has hysteresis which increases the' noise immunity and
transforms a slowly changing Input signal to a fast
changing, jitter free output.

Supply Voltage
Input Voltage
Storage Temperature Range

Connection Diagram

7V
S.SV

- 6S·C to 1S0·C

Nola 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed, The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Dual·ln·Llne Package

Y=A
Input

Output

A

Y

L
H

H
L

H = High Logic Level
L

VI

TL/F/6503-1

DM5414 (J)

(Note 1)

DM7414 (N)

6·43

=Low Logic Level

Recommended Operating Conditions
Sym

Parameter

DM5414
Min

DM7414

Nom

Max

Min

Nom

Max

Units

Vee

Supply Voltage

4.5

5

5.5

4.75

5

5.25

V

VT+

Positive-Going Input
Threshold Voltage (Note 1)

1.5

1.7

2

1.5

1.7

2

V

VT_

Negative·Going Input
Threshold Voltage (Note 1)

0.6

0.9

1.1

0.6

0.9

1.1

V

HYS

Input Hysteresis (Note 1)

0.4

0.8

0.4

0.8

IOH

High Level Output
Current

IOL

Low Level Output
Current

TA

. Free Air Operating
Temperature

-55

V

-0.8

-0.8

mA

16

16

mA

70

·C

125

0
,

Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Sym

Parameter

Conditions

Min

Typ
(Note 2)

2.4

3.4

Max
-1.5

Units
V

VI

Input Clamp Voltage

Vee = Min, II=; -12 mA

VOH

High Level Output
Voltage

Vee = Min, 10H = Max
VI = VT- Min

VOL

Low Level Output
Voltage

Vec= Min, 10L= Max
VI=V:r+ Max

IT+

Input Current at
Posltive·Going
Threshold

Vce=5V, VI=VT+

-0.43

mA

IT_

Input Current at
Negative-Going
Threshold

Vee=5V, VI=VT_

-0.56

mA

II

Input Current@Max
Input Voltage

Vee = Max, VI = 5.5V

IIH

High Level Input
Current

Vce=Max, VI=2.4V

IlL

Low Level Input
Current

Vee = Max, VI = 0.4V

los

Short Circuit
Output Current

Vee= Max
(Note 3)

ICCH

Supply Current With
Outputs High

Vcc= Max

IceL

Supply Current With
Outputs Low

Vce= Max

0.2

\

V
0.4

1

mA

40

p.A

-1.2

mA
mA

I

DM54

-18

-55

I

DM74

-18

-55

.

Note 1: Vee = 5V.
Note 2: All typical. are at VCC = 5V. TA = 25'e.
Nole 3: Not more than one output should be shorted at a time.

6-44

V

22

36

mA

39

60

mA

Switching Characteristics
Parameter

at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
CL=15 pF
RL=400n

Conditions

Units

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

15

22

ns

tpHL Propagation Delay Time
High to Low Level Output

15

22

ns

Min

6·45

~r-----------------~--------------~------------------------~-----------'

or-

~ ~National

-~;1) ~ Semiconductor
~

or-

:E

c

DM5416/DM7416 Hex Inverting Buffers with
High Voltage Open-Collector Outputs
General Description

Absolute Maximum Ratings

This device contains six independent gates each of
which performs the logic INVERT function. Tne open·
collector outputs require external pull·up resistors for
proper logical operation.

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

Pull·Up Resistor Equations
R
MAX =

Where:

7V
5.5V
15V

- 65·C to 150·C

Note 1: The '"Absolute Maximum Ratings'" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
'"Electrical Characteristics'" table are not guaranteed at the absolute
maximum ratings. The '"Recommended Operating Conditions·· table will
define the conditions for actual device operation.

Vo(Min)-VOH
N, (IOH) + N2 (lIH)

N, (IOH) = total maximum output high current
for all outputs tied to pull·up resistor
N2 (IIH) = total maximum input high current for
all inputs tied to pull·up resistor
N3 (In.! total maximum input low current for
all inputs tied to pull-up resistor.

=

Connection Diagram

Function Table

Dual-In-Line Package

T

A'

14

Y6

13

AS

11

12

1
AI

r!>o2

VI

A'

,

1D

Y=A

V,

•

4>0-, L[>o-

4>0-

r!>o-

V,

3
A2

,

,
A3

Output

A

Y

L
H

H
L

L= Low Lagle Level

•
V3

J:

TLIFIB504·1

DM5416(J)

Input

H = High Lagle Level

r!>o-

V2

(Note 1)

DM7416 (N)

6-46

Recommended Operating Conditions
Sym

DM5416

Parameter

DM7416

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units
V

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL'

Low Level Input
Voltage

0.8

0.8

V

VOH

High Level Output
Voltage

15

15

V

IOl

Low Level Output
Current

30

40

mA

TA

Free Air Operating
Temperature

70

·C

2

-55

Electrical Characteristics
Sym

Parameter

V

2

125

0

over recommended operating free air temperature (unless otherwise noted)
Typ
(Note 1)

Min

Conditions

Max

Units

VI

Input Clamp Voltage

Vee= Min, 11= -12 mA

-1.5

V

leEx

High Level Output
Current

Vee = Min, Vo= 15V
VIL = Max

250

/LA

VOL

Low Level Output
Voltage

Vee = Min, 10l= Max
VIH = Min

0.7

V

10l= 16 mA
Vee = Min

0.4

'I

Input Current@Max
Input Voltage

Vee=Max, VI =5.5V

1

mA

IIH

High Level Input
Current

Vee=Max, VI=2.4V

40

/LA

III

Low Level Input
Current

Vee = Max, VI=0.4V

-1.6

mA

leeH

Supply Current With
Outputs High

Vee= Max

30

42

mA

leel

Supply Current With
Outputs Low

Vee = Max

27

38

mA

Switching Characteristics
Parameter

at Vee = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)

Conditions

-Min

Cl=15 pF
Rl = 1100

Units

Typ

Max

tplH Propagation Delay Time
Low to High Level Output

10

15

ns

tpHl Propagation Delay Time
High to Low Level Output

15

23

ns

Note 1:

Alltypicals are at Vee=5V, TA= 25'e.

647

~r------------------------------------------------------------------------.

~ ~National
~ ~ Semiconductor

~

.,....

~
IJ)

~ DM5417/DM7417 Hex Buffers with
High Voltage Open-Collector Outputs
General Description

Absolute Maximum Ratings

This device contail')s six independent gates each of
which performs a buffer function. The open·collector
outputs require external pull·up resistors for proper
logical operation.

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

Pull·Up Resistor Equations

Where:

7V
5.5V
15V
-65·Cto 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety 01 the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ralings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Nt (lOH) = total maximum output high current
for all outputs tied to pull·up resistor
N2 (IIH) = total maximum input high current for
all inputs tied to pull·up resistor
N3 (IIU =total maximum input low current for
all inputs tied to pull·up resistor

Connection Diagram

Function Table

Dual·ln·Line Package
A6

V6

13

12

A5
11

Y5
10

A4

,

Y=A

Y4

a

4>-

Input

Output

A

Y

L
H

H

H = High Logic Level
L= Low Logic Level

Al

VI

A2

V,

A3

Yl

TLIF16505-1

DM5417 (J)

(Note 1)

DM7417 (N)

6·48

L

Recommended Operating Conditions
Sym

DM5417

Parameter

DM7417

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units
V

Vcc

Supply Voltage

V,H

High Level Input
Voltage

V,L

Low Level Input
Voltage

0.8

0.8

V

V OH

High Level Output
Voltage

15

15

V

IOL

Low Level Output
Current

30

40

mA

TA

Free Air Operating
Temperature

70

·C

2

-55

Electrical Characteristics
Sym

V

2

125

0

over recommended operating free air temperature (unless otherwise noted)

Parameter

Typ
(Note 1)

Min

Conditions

V,

Input Clamp Voltage

Vcc= Min, 1,= -12 mA

ICEX'

High Level Output
Current

Vce = Min, Vo = 15V
V,H=Min

VOL

Low Level Output
Voltage

Max

Units

-1.5

V

250

JlA

Vee = Min, IOL= Max
V,L=Max

0.7

V

IOL= 16 mA
Vee= Min

0.4

r

I,

Input Current@Max
Input Voltage

Vee = Max, V, =5.5V

1

mA

I'H

High Level Input
Current

Vee=Max, V,=2.4V

40

JlA

I,L

Low Level Input
Current

Vee = Max, V, = 0.4V

-1.6

mA

leeH

Supply Current With
Outputs High

Vee= Max

29

41

mA

leeL

Supply Current With
Outputs Low

Vee = Max

21

30

mA

Switching Characteristics
Parameter

at Vee = 5V a~d TA = 25·C (See Section 1 for Test Waveforms and Output Load)
CL =15 pF
RL = 1100

Conditions

Units

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

6

10

ns

tpHL Propagation'Delay Time
High to Low Level Output

20

30

ns

Min

Nole 1: All typical. are at Vee=5V, TA=25"C.

6-49

~ ~National
i!!i

~

~ Semiconductor

i!!i DM5420/DM7420 Dual 4-lnput NAND Gates
General Description

Absolute Maximum Ratings

This device contains two Independent gates each of
which performs the logic NAND function.

Supply Voltage
Input Voltage

(Note 1)
7V
5.5V

- 65·C to 150·C

Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual·ln·Line Package

V~4

oz
13

cz
IZ

NI~

vz

BZ

11

10

T9

Y=ABCD

8

~
1

.,

Z
81

Jcl

4

C1

5
01

~
J,6

J:

D

Y

X

L

L

X
X

X
X
X

H

H

H.
H
H
H
L

B

C

X
X
X

X
X
L

L
H

X
H

=High Logic Level
L =Low Logic Level
X =Either Low or High Logic Level
H

TL/F/6506·'

DM5420 (J)

Output

Inputs
A

DM7420 (N)

6·50

c

s:
en

Recommended Operating Conditions

.j:a,

DM5420
Sym

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level Input
Voltage

10H

High Level Output
Current

10l

Low Level Output
Current

TA

Free Air Operating
Temperature

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Parameter

Units
V
V

0.8

0.8

-0.4

-0.4

mA

16

16

mA

70

·C

-55

Electrical Characteristics
Sym

Min

2

125

0

V

over recommended operating free air temperature (unless otherwise noted)
Conditions

Typ
(Note 1)

Min

VI

Input Clamp Voltage

Vcc='Min, 11= -12 mA

VOH

High Level Output
Voltage

Vcc = Min, 10H = Max
Vll=Max

VOL

Low Level Output
Voltage

Vcc= Min, 10l= Max
VIH=Min

II

Input Current@Max
Input Voltage

IIH

Max
-1.5

Units
V
V

3.4

2.4

0.4

V

Vcc=Max, VI = 5.5V

1

mA

High Level Input
Current

Vcc = Max, VI = 2.4V

40

p.A

III

Low Level Input
Current

Vcc = Max, VI = O.4V

-1.6

mA

105

Short Circuit
Output Current

Vcc=Max
(Note 2)

mA

ICCH

Supply Current With
Outputs High

Vcc= Max

2

4

mA

ICCl

Supply Current With
Outputs Low

Vee= Max

6

11

mA

Switching Characteristics
Parameter

I
I

0.2

DM54

-20

-55

DM74

-18

-55

at Vce = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
CL=15 pF
Rl=400n

Conditions
Min

Units

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

12

22

ns

tpHl Propagation Delay Time
High to Low Level Output

8

15

ns

Nola 1: All typlcals are at Vee = SV, TA = 2S"C.
Nola 2: Not more than one output should be shorted at a time.

6-51

-s:
N

DM7420

o

C

.......

~

it)

~ ~National

~ ~ Semiconductor

~

:!

o

DM5425/DM7425 Dual4-lnput NOR Gates
with Strobe Input
.
General Description

Absolute Maximum Ratings

This device contains two independent gates each of
which performs the logic NOR function. A strobe Input
.is also Included which disables the A thru D inputs
when low.

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

7V
5.5V
-65·Ct0150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual-In-Line Package
STROBE

Vi

14

.2

C2

13

12

B2

'i

10

11

At

r

Y=G(A+B+C+D)

V2

•

Inputs

~

A'

.,

2

Gr

•
C1

t....,

JI

5

•
V,

STROlE

L
H

X
L

B

Output
C

X
X
L
L
One or more
Inputs H

D

Y

X
L

H
H
L

H= High Logic Level
L= Low Logic Level
X = Either Low or High logic Level

J:

,

.

TL/F/6507·1

DM5425(J)

A

H

~
,

G

DM7425(N)

6-52

r-----------------------~-------------------------------------------,o

~

Recommended Operating Conditions

U1

DM5425
Sym

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VJL

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

V
V

0.8

0.8

-0.8

-0.8

mA

16

16

mA

70

'C

-55

. Parameter

Units

2

",

Electrical Characteristics
Sym·

DM7425

125

0

V

over recommended operating free air temperature (unless otherwise noted)
Typ
(Note 1)

Min

Conditions

Max

VI

Input Clamp Voltage

Vcc= Min, 11= -12 mA

VOH

High Level Output
Voltage

Vcc = Min, 10H = Max
VIL=Max

VOL

Low Level Output
Voltage

Vcc= Min, 10L= Max
VIH=Min

II

Input Current@Max
Input Voltage

Vcc=Max, VI=5.5V

IIH

High Level Input
Current

Vec= Max
VI = 2.4V

Low Level Input
Current

Vee = Max
VI =0.4V

Strobe

Short Circuit
Output Current

Vec= Max
(Note 2)

ICCH

Supply Current With
Outputs High

Vcc=~ax

8

16

mA

lecL

Supply Current With
Outputs Low

Vcc=Max

10

. 19

mA

IlL

los

Switching Characteristics
Parameter

-1.5

Units

3.4

2.4

0.2

V
V

0.4

V

1

mA

Data

40

/LA

Strobe

160
-1.6

Data

,

mA

-6.4

DM54

-20

-55

DM74

-18

-55

mA

at Vec = 5V and TA = 25'C (See Section 1 for Test Waveforms and Oufput Load)
CL=15 pF
RL=400n

Conditions
Min

Units

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

13

22

ns

tpHL Propagation Delay Time
High to Low Level Output

8

15

ns

Note 1: All typicals are at VCC=5V, TA=25'C.
Note 2: Not more than one output should be shorted at a time.
6·53

tU1

o

~

......

tU1

~ ~National

~ ~ Semiconductor

~
:::i!:

o

DM5426/DM7426 Quad 2-lnput NAND Gates
with High Voltage Open-Collector Outputs

General Description

Absolute Maximum Ratings

This device contains four Independent gates each of
which performs the logic NAND function. The opencollector outputs require e.xternal pull·up resistors for
proper logical operation.

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

Pull·Up Resistor Equations
R
MAX =

W~ere:

.7V
5.5V
15V

- 65"C to 150"C

Note 1: The "Absolute Maximum Ratings" ~re those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limit,s. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Vo (Min)- VOH
Nl (lOH) + N2 (lIH)

Nl (IOH) = total maximum output high current
for all outputs tied to pull·up resistor
N2 (IIH)= total maximum input high current for
all inputs tied to pull-up resistor
N3 (IIIJ = total maximum input low current for
all inputs tied to pull-up resistor

Connection Diagram

Function Table

Dual·ln·L1ne Package
v"

A'

B4

Y'

"

Al

Yl

Inputs

"

YI

DM5426 (J)

AZ

"

Y2

GND

TL/F/65(J8.1

DM7426 (N)

6-54

Output

A

B

Y

L
L
H
H

L
H
L
H

H
H
H
L

H = High Logic Level
L= Low Logic Level
AI

(Note 1)

Recommended Operating Conditions
Sym

DM7426

DM5426

Parameter

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units
V

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

0.8

0.8

V

VOH

High Level Output
Voltage

15

15

V

IOL

Low Level Output
Current

16

16

mA

TA

Free Air Operating
Temperature

70

·C

-55

Electrical Characteristics
Sym

2

2

Parameter

125

V

0

oyer recommended operating free air temperature (unless otherwise noted)
Conditions

Typ
(Note 1)

Min

Max

VI

Input Clamp Voltage

Vcc= Min, 11= -12 mA

ICEX

High Level Output
Current

Vec=Min
VIL= Max

VOL

Low Level Output
Voltage

Vcc= Min, 10L= Max
VIH=Min

0.4

V

II

Input Current@Max
Input, Voltage

Vcc=Max, VI=5.5V

1

mA

IIH

High Level Input
Current

Vcc=Max, VI=2.4V

40

/LA

IlL

Low Level Input
Current

Vce=Max, VI=0.4V

-1.6

mA

ICCH

Supply Current With
Outputs High

Vec= Max

4

ICCL

Supply Current With
Outputs -Low

Vcc= Max

12

Switching Characteristics
Parameter

I
I

-1.5

Units

1000

Vo=15V

V
/LA

50

Vo= 12V

.

8

mA

22

mA

at Vcc= 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
CL=15 pF
RL = 1 kO (tpLH)

Conditions
Min

Units

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

16

24

ns

tpHL Propagation Delay Time
High to Low Level Output

11

17

ns

Note 1:

Aillypicals are al VCC=5V, TA=25'C,
6·55

~ ~National

-~.... ~ Semiconductor
~

::E

Q

DM5427/DM7427 Triple 3-lnput NOR Gates
General Description

.Absolute

This device contains three Independent gates each of
which performs the logic NOR function.

Maximu~

Ratings

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

7V

5.5V
-65·Cto150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will

define the conditions for actual device operation.

Connection Diagram
Dual·ln·Line Package
v""

C1

VI

B3

CJ

AJ

VJ

11

Al

"

A2

V2

B2

TL/F/6509·1

DM5427 (J)

DM7427 (N)

Function Table
Y=A+B+C
Output

Inputs

A

B

C

y

L

L

L

H

X
X
H

X
H
X

H
X
X

L
L
L

H = High Logic Level
L= Low Logic Level
X= Either High or low Logic Level

6·56

Recommended Operating Conditions
Sym

DM5427

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

DM7427

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

Units
V
V

0.8

0.8

High Level Output
Current

-0.8

-0.8

mA

10L

Low Level Output
Current

16

16

mA

TA

Free Air Qperating
Temperature

.70

·C

-55

Electrical Characteristics
Sym

125

over recommended operating free air temperature (unless btherwise noted)

Parameter

Conditions

VI

Input Clamp Voltage

Vee = Min, 11= -12 mA

VOH

High Level Output
Voltage

Vee = Min, 10H= Max
VIL = Max

• Low Level Output
Voltage

VOL

0

V

Min

Typ
(Note 1)

2.4

3.4

Max
-1.5

0.2

Vee= Min, 10L= Max
VIH= Min

Units
V
V

0.4

V

-II

Input Current@Max
Input Voltage

Vee= Max, VI = 5.5V

1

mA

IIH

High Level Input
Current

Vee = Max, VI =2.4V

40

/LA

IlL

Low Level Input
Current

Vee= Max, VI = 0.4V

-1.6

mA

los

Short Circuit
Output Current

Vee= Max
(Note 2)

mA

leeH

Supply Current With
Outputs High

Vee= Max

10

16

mA

leeL

Supply Current With
Outputs Low

Vee= Max

16

26

mA

Switching Characteristics
Parameter

I
I

DM54

-20

-55

DM74

-18

- 55

at Vee = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
C L=15 pF
RL =400{l

Conditions

Units

Typ,

Max

tpLH Propagation Delay Time
Low to High Level Output

7

11

ns

tpHL Propagation Delay Time
High to Low Level Output

10

15

ns

Min

Note 1:

All

typicals are at

Vee=5V. TA=25'e,

Note 2: Not more than one output should be shorted at a time.

-

6-57

~ ~ National

~ ~ Semiconductor

.

~

II)

::iE

c DM5430/DM7430 a-Input NAND Gate

General Description

Absolute Maximum Ratings

This device contains a single gate which performs the
logic NAND function.

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

7V
5.5V
- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should'
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual-In-Line Package
Y=ABCDEFGH
12

11

Inputs

Output

A thru H

Y

All Inputs H

L

One or More
Input L

H

H = High Logic Level
L = Low Logic Level

TliFf651D-l

DM5430 (J)

DM7430 (N)

6-58

c

Recommended Operating Conditions
Sym
Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Level Output
Curren!

TA

. Free Air Operating
Temperature

DM7430

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Parameter

Units
V

2

V

0.8

0.8

-0.4

-0.4

mA

16

16

mA

70

·C

125,

-55

Electrical Characteristics
Sym

(II

DM5430

Paramete,r

0

V

over recommended operating free air temperature (unless otherwise noted)
Conditions

VI

Input Clamp Voltage

Vee= Min, II = -12 mA

VOH

High l.evel Output
Voltage

Vee=Mln,loH=Max
VIL=Max

VOL

Low Level Output
Voltage

Vee = Min, 10L= Max
VIH=Min

II

Input Current@Max '
Input Voltage

IIH

Min

Typ
(Note 1)

2.4

3.4

Units

Max
-1.5

V
V

Vee = Max, VI = 5.5V

1

mA

High Level Input
Current

Vee = Max, VI = 2.4V

40

/lA

III

Low Level Input
Current

Vee=Max, VI=0.4V

-1.6

mA

los

Short Circuit
,?utput Current

Vee = Max
(Note 2)

mA

leeH

Supply Current With
Outputs High

Vee = Max

1

2

leel

Supply Current With
Outputs Low

Vee = Max

3

6

DM54

-20

-55

DM74

-18

-55
mA
mA
i
J

Switching Characteristics
Parameter

I

0.2

V

0.4

L

s:
~
C
s:

at Vee = 5V and TA = 25·C (See Section 1 for Test Waveforms and Out~ut Load)
Cl=15 pF
RL=400{l

Conditions
Min

Typ

Units
Max

tplH Propagation Delay Time
Low to High Level Output

13

22 '

ns

tpHl Propagation Delay Time
High to Low Level Output

8

15

ns

Note 1: All typicals are at Vee=5V, TA=25'e,
Note 2: Not more than one output should be shorted at a time:

6·59

~

~ ~National

~ ~ Semiconductor

~
::aE

o DM5432/DM7432 Quad 2-lnput OR Gates

General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic OR function.

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

7V
5.5V
-65·C to 150·C

Nola 1: The "Absotute Maximum Rallngs" are those values beyond
which the safety of the device can nol be guaranleed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratlnqs. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table
Y=A+B

Dual-ln·Line Package

Inputs
B

Y

L
L
H
H

L
H
L
H

L
H
H
H

H = High Log Ic Level
L = Low logic Level

AI

81

YI

AZ

8Z

YZ
TLlFf65II·1

DM5432(J)

DM7432 (N)

6-60

Output

A

Recommended Operating Conditions.
Sym

DM5432

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level "Input
Voltage

IOH

High Level Output
Current

10l

Low Level Output
Current

TA

Free Air Operating
Temperature

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

Parameter

V

-0.8

-0.8

mA

16

16

mA

70

'C

0

V

over recommended operating free air temperature (unless otherwise
Conditions

VI

Input Clamp Voltage

Vee= Min, 11= -12 mA

High Level Output
Voltage

Vee = Min, 10H = Max
VIH = Min

VOL

Low Level Output
Voltage

Vee = Min, IOl=Max
Vll= Max

II

Input Current@Max
Input Voltage

IIH

V

0.8

125

VOH

Units

0.8

-55

Electrical Characteristics
Sym

DM7432

Min

Min

Typ
(Note 1)

2.4

3.4

Max
-1.5

Units
V
V

0.4

V

Vee = Max, VI=5.5V

1

mA

High Level Input
Current

Vee = Max, VI = 2.4V

40

p.A

III

Low Level Input
Current

Vce=Max, VI = 0.4V

-1.6

mA

los

Short Circuit
Output Current

Vce= Max
(Note 2)

-55

mA

leeH

Supply Current With
Outputs High

Vec= Max

15

22

mA

Iccl

Supply Current With
Outputs Low

Vec= Max

23

38

mA

Switching Characteristics
Parameter

I

1

0.2

~oted)

DM54

-20

DM74

-18

-55

at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Cl =15 pF
Ri.=400n

Conditions
Min

Units

Typ

Max

tplH Propagation Delay Time
Low to High Level Output

10

15

ns

tpHl Propagation Delay Time
High to Low Level Output

14

22

ns

Nota 1: All typicals are at Vec = 5V, TA = 25·e.
Nota 2: Not more than one output should be shorted at a time.

6-61

~ ~National

-~ ~ Semiconductor
.C')
....
"I:t

II)

:E

c

DM5437/DM7437· Quad 2·lnput NAND Buffers

General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic NAND function.

Supply Voltage
Input Voltage

(Note 1)
7V

5.5V
-65·Ct0150·C

Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual·ln·Llne Package

Inputs
B

Y

L
L

L

H

H
H

L

H
H
H

H

L

=High Logic Level
L =Low Logic Level

H

"

B1

V1

DM5437 (J)

.2

"

V2

GNO

TLlF/6S12·1

DM7437 (N)

6·62

Output

A

Recommended Operating Conditions
Sym

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level Input
Voltage

IOH

DM7437

DM5437
Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units
V
V

2

V

0.8

0.8

High Level Output
Current

-1.2

-1.2

mA

10l

Low Level Output
Current

48

48

mA

TA

Free Air Operating
Temperature

".

-55

Electrical Characteristics
Sym

125

0

70

'C

over reeomme'nded operating free air temperature (unless otherwise noted)

Parameter

Conditions

VI

Input Clamp Voltage

Vee= Min, II = -12 mA

VOH

High Level Output
Voltage

Vee = Min, IOH = Max
Yll= Max

Val

Low Level Output
Voltage

Vee = Min, IOl = Max
VIH=Min

II

Input Current@Max
Input Voltage

IIH

Min

Typ
(Note 1)

2.4

3.3

Max
-1.5

Units
V
V

0.4

V

Vee = Max, VI = 5.5V

1

mA

High Level Input
Current

Vee=Max, VI = 2.4V

40

p.A

III

Low Level Input
Current

Vee = Max, VI = 0.4V

-1.6

mA

los

Short Circuit
Output Current

Vee= Max
(Note 2)

mA

leeH

Supply Current With
Outputs High

Vee=Max

9

15.5

mA

leel

Supply Current With
Outputs Low

Vee=Mal!

34

54

mA

0.2

-.

DM54

-20

-70

DM74

-18

-70

.

Switching Characteristics
Parameter

at Vee = 5V and TA= 25'C (See Section 1 for Test Waveforms and Output Load)
Cl=45 pF
RL = 1330

Conditions

Units

Typ

Max

tplH Propagation Delay Time
Low to High Level Output

13

22

ns

tpHl Propagation Delay Time
High to Low Level Output

8

15

ns

Min

Note 1:

All typical. are at Vcc = 5V. TA = 25·C.

.

Note 2: Not more than one output should be shorted at a time.

6-63

co

~ ~National

-~ ~ Semiconductor
co

('I)

oq-

II)

::2:

o DM5438/DM7438 Quad 2-lnput NAND Buffers

with Open-Collector Outputs

General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic NAND function. The open·
collector outputs require external pull-up resistors for
proper logical operation.

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

Pull· Up Resistor Equations

Nota 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Charac!eristics" table are not guaranteed at the absolute

RMAX= Vcc (Min)- VOH
Nl (IOH )+ N2 (lIH)

7V

5.5V
7V

- 65·C to 150·C

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

RMIN= Vcc (Max)- VOL
10L - N3 (III)

Where:

=

Nl (IOH) total maximum output high current
for all outputs tied to pull·up resistor
N2 (IIH) = total maximum input high current for
all inputs tied to pull-up resistor
N3 (Ill) = total maximum input low current for
all inputs tied to pull-up resistor

Function Table

Connection Diagram
Dual·in·Line Package

Y=AB
Inputs
B

Y

L

L
H
L
H

H
H
H
L

H = High Logic Level
L= Low Logic Level
TLlFf6513·1

DM7438 (N)

6·64

Output

A
L
H
H

DM5438 (J)

(NO!e 1)

Recommended Operating Conditions
Sym

DM7438

DM5438

Parameter

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units

Vcc

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level Input
Voltage

0.8

0.8

V

VOH

High Level Output
Voltage

5.5

5.5

V

IOl

Low Level Output
Current

48

48

mA

TA

Free Air Operating
Temperature

70

·C

2

-55

Electrical Characteristics
Sym

Parameter

125

over recommended

V
V

2

0

oper~ting free air temperature (unless otherwise noted)

Conditions

Typ
(Note 1)

Min

Max

Units

VI

Input Clamp Voltage

Vcc= Min,ll= -12 mA

-1.5

V

ICEX

High Level Output
Current

Vcc= Min, Vo= 5.5V
Vll = Max

250

I'A

VOL

Low Level Output
Voltage

Vcc= Min, IOl= Max
VIH= Min

0.4

V

II

Input Current@ Max
Input Voltage

Vcc = Max, VI = 5.5V

1

mA

IIH

High Level Input
Current

Vcc= Max, VI = 2.4V

40

I'A ,

III

Low Level Input
Current

Vcc = Max, VI = O.4V

-1.6

mA

ICCH

Supply Current With
Outputs High

Vcc= Max

5

8.5

mA

ICCl

Supply Current With
Outputs Low

Vcc= Max

34

54

mA

Switching Characteristics
Parameter

.

,

at Vcc = 5V and TA;= 25·C (See Section 1 for Test Waveforms and Output Lpad)
Cl=45 pF
Rl = 133!l

Conditions

Units

Typ

Max

tplH Propagation Delay Time
Low to High Level Output

14

22

ns

tpHl Propagation Delay Time
High to Low Level Output

11

18

ns

Min

Note 1:

All

typicals are at

VCC=SV. TA=2S"C.

6·65

3.... ~National

~ ~ Semiconductor

~

II)

:2

c DM5440/DM7440 Dual 4-lnput NAND Buffers
General Description

Absolute Maximum Ratings

This device contains two independent gates each of
which performs the logic NAND function.

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)
7V

s.sv
-6S·Ct01S0·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will

define the conditions for actual device operation.

Connection Diagram

Function Table
Y=ABCD

Dual·ln·Line Package

VI:

"

1

"

D2
1J

C1
12

NI~II

B2

"

V2

Ts

h
2
B1

J:

4

C1

,
D1

~
6
J1

A

B

C

D

Y

X
X
X

X
X

X

L

L
H

X

X
X

H

H

L
X
X
X
H

H
H
H
H
L

L

H = High Logic Level
L = Low Logic Level
X= Either Low or High Logic Level

J:

TlfF/6514·1

DM5440 (J)

Output

Inputs

8

DM7440(N)

6-66

c

s:
c.n

Recommended Operating Conditions
Sym

DM5440

Parameter

Vcc

Supply Voltage

\CIH

High Level Input
Voltage

Vil

Low Level Input
Voltage

10H

Min
4.5

Nom

.j:o,
.j:o,

DM7440
Max
5.5

5

2

Min

Nom

4.75

5

Max
5.25

Units
V
V

2
0.8

0.8

High Level Output
Current

-1.2

-1.2

mA

10l

Low Level Output
Current

48

48

mA

TA

Free Air Operating
Temperature

70

·C

-55

Electrical Characteristics
Sym

Parameter

125

0

V

over recommended operating free air temperature (unless otherwise noted)
Conditions

Min

Typ
(Note 1)

2.4

3.3

Max
-1.5

Units

V

VI

Input Clamp Voltage

Vcc= Min, 11= -12 mA

VOH

High Level Output
Voltage

Vcc=Min,IOH=Max
Vll=Max

VOL

Low Level Output
Vqltage

Vcc = Min, 10l = Max
VIH='Min

II

Input Current@Max
I nput Voltage

Vcc=Max, VI = 5.5V

IIH

High Level Input
Current

Vcc=Max, VI=2.4V

40

p.A

III

Low Level Input
Current

Vcc=Max, VI = 0.4V

-1.6

mA

los

Short Circuit
Output Current

Vcc= Max
(Note 2)

mA

ICCH

Supply Current With
Outputs High

Vcc=Max

4

8

mJ,\

Iccl

Supply Current With
Outputs Low

Vcc= Max

17

27

mA

Switching Characteristics
Parameter

I
I

0.2

V
0.4

V
mA

DM54

-20

-70

DM74

-18

-70

at Vcc=5V and TA=25·C (See Section 1 for Test Waveforms and Output Load)
Cl=15 pF
Rl = 1330

Conditions
Min

Units

Typ

Max

tplH Propagation Delay Time
Low to High Level Output

13

22

ns

tpHl Propagation Delay Time
. High to Low Level Output

8

15

ns

Note 1:

All typlcals are at VCC=SV, TA=2S"C.

Note 2: Not more than one output should be shorted at a time.

6·67

-s:
0

C

......
.j:o,

.j:o,

0

:

~National

~ ~ Semiconductor
c



8

r I I
!2
9

!3

!4

A

D Vee

-----...-.. -----...-..
OUTPUTS

INPUTS

.15

I I!7

!6
B

e

8

2

-----...-.. OUTPUT
INPUTS

A

Output
On'

L L
L L
L L
L 'L
L H
L H
L H
L H
H L
H L

L
L
H
H
L
L
H
H
L
L

L
H
L
H
L
H
L
H
L
H

0
1
2
3
4
5
8
7
8
9

(Over Range)

TL/F/6515-1

5441A(J)

B

D

111 11
1

C

9

C>

(Note 1)

H
H
H
H
H
H

7441A(N)

L
L
H
H
H
H

H
H
L
L
H
H

L
H
L
H
L
H

0
1
2
3
4
5

H - High Level, L - Low Level
• All other outputs Bfe off

6-68

Recommended Operating Conditions
DM5441 A
Sym

Parameter

Vee

Supply Voltage

V IH

High Level Input
Voltage

V IL

Low Level Input
Voltage

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

DM7441A

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

V
V

2

-55

Electrical Characteristics

Units

0.8

O.B

V

7

7

rnA

70.

·C

125

0

over recommended operating free air temperature (unless otherwise noted)
Typ
(Note 1)

Sym

Parameter

VOH

High Level Output
Voltage

Vcc=Min,loH=1 rnA
VIL = Max, VIH = Min

IOH

Off·State Reverse
Current

Vcc=Min
Vo=50V

TA= 125·C

60

TA=70·C

40

TA = -55 to 70·C

1.B

Low Level Output
Voltage

Vec= Min
IOL= Max
VIL=Max
VIH=Min

'TA=·-55 to 70·C

2.5

II

Input Current@Max
Input Voltage

Vec=Max, Vj=5.5V

1

rnA

IIH

High Level Input
Current

Vcc = Max, VI = 2.4V

40

I'A

IlL

Low Level Input
Current

Vcc=Max, VI =O.4V

-1.6

rnA

Icc

Supply Current

Vec= Max (Note 2)

36

rnA

VOL

Conditions

Min

Max

70

V

TA =125·C

",A

V

3

21

Note 1: All typlcals are at Vec=SV, TA=2S·C.
Note 2: ICC Is measured with all outputs open and all inputs grounded.

.

6·69

Units

Logic Diagram

(
5441A17441A

TLIF/6515·2

6·70

r---------------------------------------------~--------------,c

3:

~National

c.n
01:00

~ Semiconductor
DM5442/DM7442 BCD to Decimal Decoders

it

General Description

S

These BCD-to-decimal decoders consist of eight inverters
and ten, four-input NAND gates. The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of input logic ensures
that all outputs remain off for all inv.alid (10-15) input
conditions.

Supply Voltage

Features

Input Voltage
Storage Temperature Range

• Diode clamped inputs
• Also for application as 4-line-to-16-line decoders; 3-lineto-B-Iine decoders
• All outputs are high for invalid input conditions

c
3:
......

• Typical power dissipation 140 mW
• Typical propagation delay 17 ns

Absolute Maximum Ratings

(Note 1)
7V
5.5V

- 65°C to 150°C

- Nota 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
'not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Logic Diagram

" Dual-In-Line Package
OUTPUTS

INPUTS

vee
116

e

B

A

15

14

9

D

13

12

8
11

9

10

,

p-

r-<

I

2

3

4

5

7

6

18

o

GND

OUTPUTS
TLlFf6516·1

5442 (J)

"7442 (N)
TL/F/6516·2

Function Table
BCD Input

Decimal Output

No.
D

C

B

A

0

1

2

3

4

5

6

7

8

9

2
3
4

L
L
L
L
L

L
L
L
L
H

L
L
H
H
L

L
H
L
H
L

L
H
H
H
H

H
L
H
H
H

H
H
L
H
H

H
H
H
L
H

H
H
H
H
L

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

5
6
7
8
9

L
L
L
H
H

H
H
H
L
L

L
H
H
L
L

H
L
H
L
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
"H
H
H

H
H
H
H
H

L
H
H
H
H

H
L
H
H
H

H
H
L
H
H

H
H
H
L
H

H
H
H
H
L

H
H
H
H
H
H

L
L
H
H
H
H

H
H
L
L
H
H

L
H
L
H
L
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

0
1

...
51

§
;;:;

H = HIgh Level
L = Low Level

6-71

Recommended Operating Conditions
Sym
Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

DM7442

DM5442

Parameter

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

Units
V
V

0.8

0.8

-0.8

-0.8

mA

16

16

mA

70

·C

-55

125

0

V

>,

Electrical Characteristics
Sym

Parameter

over recommended operating free air temperature (unless otherwise noted)
Conditions

VI

Input Clamp Voltage

Vee = Min, 11= -12 mA

VOH

High Level Output
Voltage

Vee = Min, IOH = Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee = Min, IOL = Max
VIH = Min, VIL = Max

II

Input Current@Max
Input Voltage

IIH

Min

Typ
(Note 1)

2.4

3.4

Max
':"'1.5

V
V

0.4

V

Vee = Max, VI = 5.5V

1

rnA

High Level Input
Current

Vee=Max, VI = 2.4V

40

p.A

IlL

Low Level Input
Current

Vee=Max, VI=O.4V

-1.6

rnA

los

Short Circuit
Output Current

Vee = Max
(Note 2)

DM54

-20

-55

rnA

DM74

-18

-55

Supply Current

Vee = Max
(Note 3)

DM54

28

41

DM74

28

56

Icc

0.2

Units

Nolel: Alltyplcals are at Vee=5V, TA=25"e.
Note 2: Not 'more than one output should be shorted at a time.
Note 3: ICC Is measured with all outputs open and all inputs grounded.

,

,6-72

rnA

,

o

Switching Characteristics
Parameter

at Vcc=5V and TA=25°C (See Section 1 for Test Waveforms and Output Load)
CL=15pF
RL =400n

Conditions
Min

Units

Typ

Max

tpHL Propagation Delay Time
High to Low Level Output
From A, S, C or D Through
2 Levels of Logic

14

25

ns

tpHL Propagation Delay Time
High to Low Level Output
From A, S, C, or D Through
3 Levels ~f Logic

17

30

ns

tpLH Propagation Delay Time
Low to High Level Output
From A, S, C or D Through
2 Levels of Logic

10

25

ns

tpLH Propagation Delay Time
Low to High Level Output
From A, S, C or D Through
3 Levels of Logic

17

30

ns

s:
C1I

S
-o
s:
.....a

S

•

6·73

Il)

~ ~National

~ ~ Semiconductor
DM5445/DM7445 BCD to Decimal Decoders/Drivers
General Description

Absolute Maximum Ratings

These !'lCD-to-decimal decoders/drivers consist of eight
inverters and ten, four-input NAND gates. The inverters are
connected in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of BCD input logic
ensures that all outputs remain oil for all invalid (10-15) binary input conditions. These decoders feature high-performance, NPN output transistors designed for use as
indicator / relay drivers, or 'as open-collector logic-circuit
drivers. The high-breakdown output transistors are compatible for interfacing with most MOS integrated circuits.

Supply Voltage
Input Voltage

7V
5.5V

Output Voltage
Storage Temperature Range

Features

Connection Diagram
Dual·ln-Line Package
INPUTS

OUTPUTS

OUTPUTS

TL/F/6517·1

S44S(J)

744S(N)

function Table
Inputs

Outputs

D C B A

0
1
2
3
4

5
6
7

8
9
Q

:::;

~
~

H

0

1

2

3

4

5

6

7

8

9

L L L L
L L H H
L H L H
L H H H
H L L H

H
L
H
H
H

H
H
L
H
HI

H
H
H
L
H

H
H
H
H
L

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

L H L H H
L H H L H
L H H H H
H L L L H
H L L H H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

L
H
H
H
H

H
L
H
H
H

H
H
L
H
H

H
H
H
L
H

H
H
H
H
L

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H.
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

L
L
L
L
L

L
L
H
H
H
H

H
H
L
L
H
H

= High Level (Off),

L
H
L
H
L
H
L

H
H
H
H
H
H

30V

-65°Ctol50°C

Nola 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated ai these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

• Full decoding of input logic
• 80 rnA sink-current capability
• All outputs are off for invalid BCD input conditions

No.

(Note 1)

= Low Level (On)
6-74

H
H
H

Recommended Operating Conditions
DM7445

DM5445
Sym

Parameter

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units
V

Vee

Supply Voltage

V IH

High Level Input
Voltage

VIL

Low Level Input
Voltage

0.8

0.8

V

VOH

High Level Output
Voltage

30

30

V

IOL

Low Level Output
Current

20.

20

mA

TA

Free Air Operating
Temperature

70

·C

2

-55

Electrical Characteristics
Sym

125

Min

VI

Input Clamp Voltage

Vee = Min,ll= -12 mA

leEx

High Level, Output
Current

Vee=Min, Vo=30V
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee= Min, IOL= Max
VIH = Min, VIL = Max
IOL=80 mA
Vee= Min

II

Input Current@Max
Input Voltage

Vee = Max, VI = 5.5V

IIH

High Level Input
Current

Vee = Max, VI = 2.4V

IlL

Low Level Input
Current

Vee = Max, VI = 0.4V

Icc

Supply Current

Vee = Max
(Note 2)

Switching Characteristics
Parameter

0

over recommended operating free air temperature (unless otherwise noted)
Conditions

Parameter

V

2

I

I

Typ
(Note 1)

Max

Units

-1.5

V

250

p.A

0.2

0.4

V

0.5

0.9

-.

1

mA

40.

p.A

-1.6

mA
mA

DM54

43

62

DM74

43

70

at Vee = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
CL=15 pF
RL=100n

Conditions
Min

Typ

Units
Max

tpLH Propagation Delay Time
Low to High Level Output

30

ns

tpHL Propagation.Delay Time
High to Low Level Output

30

ns

Note 1:

All typicals are at Vec=SV, TA=2S'e.

Note 2: ICC is measured with all inputs grounded and all outputs open.

6·75

U)

~

r-------------------------------------------------------------~----------------~

Logic Diagram

:E

-c
U)

~

:E
c

OUTPUT 0

B
(5)

OUTPUT 4

B

INPUTC

(6)

C

OUTPUT 5
(7)

C

INPUT 0

OUTPUT 6
(9)

0

OUTPUT 7

0

TlIF/6517·2

6·76

r------------------------------------------------------------------,c
s:
0'1
~National

~ Semiconductor
DM5446A/DM7446A, DM5447A/DM7447A, DM5448/DM7448
BCD to 7·Segment Decoders/Drivers
Features

The 46A and 47A feature active· low outputs designed for
driving common·anode LEDs or incandescent indicators
directly; and the 48 features active·high outputs for driving
lamp buffers or common·cathode LEDs. All of the circuits
have full ripple·blanking input/output controls and a lamp
test input. Segment identification and resultant displays
are shown on a following page. Display patterns for BCD
input counts above nine are unique symbols to authen·
ticate'input conditions.

• AI/ circuit types feature lamp intensity modulation
capability

• Open·col/ector outputs drive indicators directly
• Lamp·test provision
• Leading /trailing zero suppression

INPUTS

Absolute Maximum Ratings

s:
0'1

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

7V
5.5V
- 65 a C to 150 a C

Active
Level

Output
Configuration

Sink
Current

Max
Voltage

Typical
Power
Dissipation

Packages

low
low
high
low
low
high

open'col/ector
open'col/ector
2 k!l pul/·up
open·collector
open·collector
2 k!l pull·up

40mA
40mA
6.4 mA
40 mA
40 mA
6.4 mA

30V
15 V
5.5 V
30V
15 V
5.5 V

320mW
320mW
265mW
320mW
320mW
265 mW

J
J
J
N
N
N

Dual·ln·Line Package

OUTPUTS

OUTPUTS

BI/RBO

RBI

~

~

GND

INPUTS

INPUTS

LAMP BI/RBO
TEST

RBI

~

GND

INPUTS

TLlF/6518-2

TLlFI6518·'

5446A(J)
5447A (J)

-

~

Dual·ln·Line Package

LAMP
TEST

i!
c
s:
......

544817448
• Internal pul/·ups eliminste need for external resistors
• Lamp·test provision
• Leading /trailing zero suppression

Connection Diagrams

~

c

s:
0'1
~
~

5446A/7446A,5447A/7447A

Driver Outputs

DM5446A
DM5447A
DM5448
DM7446A
DM7447A
DM7448

~
~

}>

, Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Type

c

s:
......
0)

General Description

All of the circuits incorporate automatic leading andlor
trailing·edge, zero·blanking control (RBI and RBO). Lamp
test (Ln of these devices may be performed at any time
when the BIIRBO node is at a high logic level. All types
contain an overriding blanking input (BI) which can be
used to control the lamp intensity (by pulsing) or to inhibit
the outputs.

i-

5448(J)

7446A(N)
7447A(N)

6·77

7448(N)

~

~

c

~
~

~

c

s:
......

&

Recommended Operating Conditions
Sym

Parameter

DM5446A

DM7446A

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

0.8

0.8

V

VOH

High Level Output
Voltage (a thru g)

30

30

V

IOH

High Level Output
Current (BI/RBO)

-0.2

-0.2

p.A

IOL

Lpw Level Output
Current (a thru g)

40

40

mA

IOL

Low Level Output
Current (BI/RBO)

8

8

mA

TA

Free Air Operating
Temperature

70

·C

-55

'46A Electrical Characteristics

V

2

2

125

V

0

over recommended operating free air temperature

(unless otherwise noted)

.
Sym

Parameter

Conditions

VI

Input Clamp Voltage

Vee = Min, 11= -12 mA

VOH

High Level Output
Voltage

Vee = Min (BI/RBO)
10H = Max

leEx

High Level Output
Current (a thru g)

Vee = Max, i/o = 30V
VIL = Max, V1H = Min

VOL

Low Level Output
Voltage

Vee = Min, 10L= Max
VIH = Min, VIL = Max

II

Input Current@Max.
Input Voltage

IIH
IlL

Min

Typ
(Note 1)

2.4

3.7

Max
-1.5

Units
V
V

250

p.A

0.4

V

Vee = Max, VI = 5.5V
(Except BI/RBO)

1

mA

High Level Input
Current

Vec = Max, VI = 2.4V
(Except BI/RBO)

40

p.A

Low Level Input
Current

Vee= Max
VI =O.4V

I BI/RBO

-4

mA

I Others

-1.6

los

Short Circuit
Output Current

Vee= Max (BI/RBO)

Ice

Supply Current

Vce= Max
(Note 2)

0.3

I DM54
I DM74

60
60

Nole 1: All typicals are al VCC =SV, TA =2S"C.
Nole 2: ICC is measured wilh all oulputs open and all inpuls al 4.SV.
I

6-78

,

-4

mA

85

mA

103

c

s:c.n

'46A Switching Characteristics

at Vee= 5V and TA= 25·C
(See Section 1 for Test Waveforms and Output Load)

Parameter

01:>-

~

Conditions

Units

Typ

Min

-s:
l>

CL=15 pF
Ri.=120!l
Max

tpLH Propagation Delay Time
Low to High Level Output

100

ns

tpHL Propagation Delay Time
High to Low Level Output

100

ns

C

t

;.
c

s:c.n

:t

->s:
C·

t

~

Recommended Operating Conditions
Sym

Parameter

c

DM5447A

s:
c.n

DM7447A

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units

Vee

Supply Voltage

V1H

High Level Input
Voltage

V1L

Low Level Input
Voltage

0.8

0.8

V

. VOH

High Level Output
Voltage (a thru g)

15

15

V

10H

High Level Output
Current (BI/RBO)

-0.2

-0.2

/i A

IOL

Low Level Output
Current (a thru g)

40

40

rnA

IOL

Low Level Output
Current (BI/RBO)

8

8

rnA

TA

Free Air Operating
Temperature

70

·C

2

2

-55

125

.

.
~

6·79

0

V
V

-£s:c
~
0l:>eo

'47A Electrical Characteristics

over recommended operating free air temperature

(unless otherwise noted)
Sym

Conditions

Parameter
Input Clamp Voltage

Vee= Min, 11= -12 mA

High Level Output
Voltag'e

Vee Min (BlIRBO)
10H=Max

leEx

High Level Output
Current (a thru g)

Vee = Max, Vo=15V
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee = Min, IOL= Max
VIH = Min, VIL = Max

II

Input Current@Max
Input Voltage

IIH
IlL

VI
, VOH

Min

Typ
(Note 1)

2.4

3.7

Max

Units
V

-1.5

=

V
250

I,A

0.4 .

V

Vee = Max, VI': 5.5V

1

mA

High Level Input
Current

Vee = Max, VI=2.4V

40

I'A

Low Level Input
Current

Vee= Max
VI=O.4V

-4

mA

los

Short Circuit
Output Current

Vee= Max (BlIRBQ)

Icc

Supply Current

Vee= Max
(Note 2)

I

0.3

BlIRBO

I Others

-1.6

I DM54
I DM74

-4

mA

60

85

mA

60

103

Note 1: All typicals are at Vee=5V. TA=25'e,
Note 2: ICC is measured with all outputs open and all inputs at 4,5V.

'47 A Switching Characteristics at Vee = 5V and T A= 25·C
, (See Section 1 for Test Waveforms and Output Load)

"
Parameter

CL =15pF
RL =120{J

Conditions
Min

Typ

Units
Max

tpLH Propagation Delay Time
Low to High Level Output

100

ns

tpHL Propagation Delay Time
High to Low Level Output

100

ns

"

6-80

Recommended Operating Conditions
Sym

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

VOH
10H

DM5448

DM7448

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units

.,

V
V

2
·0.8

0.8

V

High Level Output
Voltage (a thru g)

5.5

5.5

V

High Level Output
Current (a thru g)

-0.4

-0.4

p.A

High Level Output
Current (BIIRBO)

-0.2

-0.2

10L

Low Level Output
Current (a thru g)

6.4

6.4

mA

10L

Low Level Output
Current (BIIRBO)

8

8

mA

TA

Free Air Operating
Temperature

70

DC

-55

'48 Electrical Characteristics

125

0

over recommended operating free air temperature

. (unless otherwise noted)
Min

Typ
(Note 1)

Vee = Min (a thru g), 10H = Max

2.4

4.2

Vee = Min (BIIRBO), 10H = Max

2.4

3.7

Low Level Output
Voltage

Vee = Min, 'loL = Max
VIH = Min, VIL = Max

,

0.27

10 (OFF)

Off State Output
Current (a thru g)

Vec=Max, VIH=Min
VIL=Max, Vo=0.85V

-1.3

II

Input Current@Max
Input Voltage

Vce= Max, VI =5.5V
(Except BIIRBO)

1

mA

IIH

High Level Input
Current

Vee = Max, VI = 2.4V
(Except BIIRBO)

40

p.A

IlL

Low Level Input
Current

Vee= Max
VI =0.4V

mA

Short Circuit
Output Current
Supply Current

Sym
VI
VOH

VOL

los

Icc

'Parameter
Input Clamp Voltage
• High Level Output

Conditions

Max
-1.5

Vee =Min,II=-12mA

0.4

2

mA

-4
-1.6

Vee= Max
(BIIRBO)

DM54

-4

DM74

-4

Vee=Max
(Note 2)

DM54

50

76

DM74

50

90

/

6·81

V

/

BIIRBO

Note 2: ICC is measured with all outputs open and all inputs at 4.5V.

V
V

Others

Nolet: All typicals are at Vee;5V, TA;25'e.

Units

mA

mA

'48

Switching Characteristics at Vee= SV and TA= 2SoC
(See Section 1 for Test Waveforms and Output Load)
'" Parameter

CL=15 pF
RL=1kll

Conditions
Min

Units

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

100

ns

tpHL Propagation Delay Time
High to Low Level Output

100

ns

;

6·82

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Logic Diagrams
46A,47A

48'

LAMP-TEST
INPUT

9

RBI
TL/F/6518·4

6-84

c

:s:
U1

~National

.j::Io

~ Semiconductor

-:s:c
U1

o

~
U1
o

DM5450/DM7450 Dual Expandable 2·Wide 2·lnput
AND·OR·INVERT Gates
General Description

Absolute Maximum Ratings

This device contains two combinations of gates each of
which performs the logic AND-DR-INVERT function. The
logic can be expanded by using the DM54/7460. Up to
four DM54/7460's can be used

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

7V
5.5V
- 65·C to 150·C

Noto 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these'limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual-In-Llne Package

Y=AB+CD+X
Inputs

Output

A

B

C

D

X

Y

H

H

Y

Y

Y
Y

L
L
L

Y
Y

Y
H
H
Y
H
Y
Y
Other Combinations

X=Output of 54/7460

Al

A2

82

C2

D2

V2

H = High Logic Level
L= Low Logic Level
Y = Either Low or High Logic Level

GND

TLlF/6519·1

DM5450 (J)

DM7450 (N)

6-85

H

Recommended Operating Conditions
Sym

Parameter

Vee

Supply Voltage

V'H

High Level Input
Voltage

V'L

Low Level Input
Voltage

10H

High Level Output
Current

10L
TA

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Free Air Operating
Temperature

Parameter

-55

Vee = Min,I,= -12 mA

High Level Output
Voltage

Vee= Min, IOH = Max
V'L= Max

Ix

Base·Emitter Voltage
of Output Transistor Q

Expander Current

-0.4

-0.4

mA

16

16

mA

70

·C

Conditions

Input Clamp Voltage

VBEQ

V

0.8

0

over recommended operating free air temperature (unless otherwise noted)

VOH

Low Level Output
Voltage

V
V

0.8

125

V,

VOL

Units

2

. Low Level Output
Current

Electrical Characteristics
Sym

DM7450

DM5450
Min

Min

Typ
(Note 1)

2.4

3.4

-1.5

Ix= 150 p.A
Ix= -150 p.A
IOH= Max

DM54

2.4

3.4

Ix=270p.A
Ix= -270 p.A
IOH= Max

DM74

2.4

3.4

Vee = Min, IOL= Max
V'H=Min

Max

Units
V
V

0.2

0.4

Ix + Ix= 300 p.A
Rxx= 138{l
IOL= Max

DM54

0.2

0.4

Ix+ Ix= 430 p.A
Rxx: 130{l
IOL= Max

DM74

0.2

0.4

Ix+lx=410p.A
Rxx=O
10L= 16 mA

DM54

1.1

Ix+ Ix= 620 p.A
Rxx=O
IOL= 16 mA

DM74

1

Vxx=0.4V
IOL= 16 mA

DM54

-2.9

DM74

- 3.1

V

V

mA

I,

Input Current@Max
Input Voltage

Vee = Max, V,= 5.5V

1

mA

I'H

High Level Input
Current

Vee = Max, V, = 2.4V

40

p.A

I'L

Low Level Input
Current

Vee = Max, V,=O.4V

-1.6

rnA

6-86

Electrical Characteristics (Continued) over recommended operating free air temperature
(unless otherwise noted)
Sym

Parameter

Conditions

Typ
(Note 1)

Min

I

DM54

-20

DM74

-18

Max

los

Short Circuit
Output Current

Vcc= Max
(Note 2)

ICCH

Supply Current With
Outputs High

Vcc= Max

4

8

rnA

ICCl

Supply Current With
Outputs Low.

Vcc= Max

7.4

14

rnA

I

-55

Units
mA

- 55

,

SWitching Characteristics

at Vcc = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)

. Parameter

Conditions

tplH Propagation Delay Time
Low to High Level Output

(Expander Pins Open)

Cl=15 pF
Rl=400!l
Min

tpHl Propagation Delay Time
High to Low Level Output
tplH Propagation Delay Time
Low to High Level Output

(From !"nput of
60 Expander)

tpHl Propagation Delay Time
High to Low Level Output

Typ

Max

Units

13

22

ns

8

15

ns

15

30

ns

10

20

ns

Note 1: All typicals are at VCC=5V, TA=25'C.
Note 2: Not more than one output should be shorted at a time.

I

,

6-87

~

r------------------------------------------------------------------------------------,

~ ~ National
~ ~ Semiconductor

-:;
~

ID

~ DM5451/DM7451 Dual 2·Wide 2·lnput
AND·OR·INVERT Gates
General Description

Absolute Maximum Ratings

This device contains two combinations of gates each of
which performs the logic AND·OR·INVERT function.

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)
7V

5.5V
- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditlons·for actual device operation.

Connection Diagram

Function Table

Dual·ln·Line Package

B1

MAKE NO EXTERNAL
CONNECTION

,..,.....-.....

01

Y=AB+CD
C1

Inputs

V1

A
H
X

B

C

H
X
X
H
All Other
Combinations

Output
D

Y

X
H

L
L
H

H = High Logic Level
L = Low Logic Level

x= Either Low or High Logic Level

.,

.2

82

C2

02

V2

GNo

TL/F/652()'1

DM5451 (J)

DM7451 (N)

6·88

c

s:

Recommended Operating Conditions
Sym

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

Sym

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Parameter

Units

V
0.8

- 0.4

-0.4

rnA

16

16

rnA

70

'C

125

0

over recommended operating tree air temperature (unless otherwise noted)
Conditions

VI

Input Clamp Voltage.

VOH

High Level Output
Voltage

Vee = Min, 10H = Max
VIL = Max

VOL

Low Level Output
Voltage

Vee = Min, 10L= Max
VIH=Min

II

Input Current@Max
Input Voltage

IIH

Min

Typ
(Note 1)

2.4

3.4

Max
-1.5

Vee = Min, 11= -12 mA

V
V
V

Vce=Max, VI=5.5V

1

mA

High Level Input
Current

Vee = Max, VI = 2.4V

40

p.A

IlL

Low Level Input
Current

Vec = Max, VI = O.4V

-1.6

rnA

los

Short Circuit
Output Current

Vee= Max
(Note 2)

rnA

leeH

Supply Current With
Outputs High

Vee = Max

4

8

rnA

leeL

Supply Current With
Outputs Low

Vee= Max

7.4

14

mA

Parameter

I
I

0.2

Units

0.4

Switching Characteristics

......
~
.....

V

0.8

"

C

s:

V

2

-55

Electrical Characteristics

.....

Min

2

C1I

DM7451

DM5451

Parameter

Vee

~

DM54

-20

-55

DM74

-18

-55

at Vee = 5V and TA = 25'C (See Section 1 for Test Wavetorms and Output Load)
CL=15pF
RL=400!!

Conditions
Min

Typ

tpLH Propagation Delay Time
Low to High Level Output

13

tpHL Propagation Delay Time
High to Low Level Output

8

Note 1: All typicals are at Vee=SV, TA=2S'e,
Note 2: Not more than one output should be shorted at a time.

6-89

Units
Max
.22

ns

15

ns

II

C")

~ ~National
~ ~ Semiconductor

C")

~

:iE

c DM5453/DM7453 Expandable 4·Wide 2~lnput

AND·OR·INVERT Gates
General Description

Absolute Maximum Ratings

This device contains a combination of gates which per·
forms the logic AND·OR·iNVERT function.

Supply Voltage
Input Voltage
Storage Te,mperature Range

(Note 1)

7V
5.5V
- 65·Cto 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The devlce'should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram
Dual·ln·Llne Package

NC

GNO

TL/F/6521-1

DM5453 (J)

DM7453 (HI

Function Table
Y=AB+CD+EF+GH+X

Inputs

Output

A B C D E F G H X

V

Y Y Y
Y Y H H Y
Y Y Y Y H
Y y y y y
Y Y Y Y Y

L
L
L
L
L
H

H H

Y Y Y
Y Y Y
H Y Y
y H H
'y Y Y

All Other Combinations
H = High Logic Level
L= Low Logic Level
Y = Either Low or High Logic Level

6·90

Y

Y
Y
Y
H

Recommended Operating Conditions
Sym

Parameter

DM7453

DM5453
Min

Nom

Max

Min

Nom

Max

5

5.5

4.75

5

5.25

Vee

Supply Voltage.

4.5

V,H

High Level Input
Voltage

2

V,L

Low Level Input
Voltage

10H

Units
V
V

2

V

0.8

0.8

High Level Output
Current

-0.4

-0.4

mA

10L

Low Level Output
Current

16

16

mA

TA

Free Air Operating
Temperature

70

·C

Electrical Characteristics

125

-55

0

over recommended operating free air temperature (unless otherwise noted)
i

Sym

Parameter

Conditions

V,

Input Clamp Voltage

Vee = Min, 1,= -12 mA

VOH

High Level Output
Voltage

Vec= Min, 10H= Max
V,L Max

VOL

VBEa

Ix

Low Level Output
Voltage·

Base·Emitter Voltage
of Output Transistor Q

Expander Current

=

Min

Typ
(Note 1)

2.4

3.4

-1.5

Ix=150p.A
Ix= -150 p.A
IOH= M,ax

DM54

.2.4

3.4

Ix=270 p.A
Ix= -270p.A
IOH= Max

DM74

2.4

3.4

Vee= Min, 10L= Max
V,H = Min

Max

Units
V
V

0.2

0.4

Ix+ Ix= 300 p.A
Rxx= 1380
IOL= Max

DM54

0.2

0.4

Ix + 1)( = 430 p.A
Rx)(= 1300
10L= Max

DM74

0.2

0.4

Ix+1j(=410"A
Rxx=O
10L= 16 mA

DM54

1.1

Ix+ Ix= 620 "A
Rxx=O
10L= 16 mA

DM74

1

Vxx =0.4V
10L= 16 mA

DM54

-2.9

DM74

-3.1

V

V

mA

I,

Input Current@Max
Input Voltage

Vee = Max, V, = 5.5V

1

mA

I'H

High Level Input
Current

Vee=Max, V,=2.4V

40

!LA

I,L·

Low Level Input
Current

Vee = Max, V, = O.4V

-1.6

mA

6·91

Electrical Characteristics (Continued)

over recommended operating free air temperature

(unless otherwise noted)
Parameter

Conditions

Typ
(Note 1)

Min

I DM54
I DM74

Max

Units

-20

-55

mA

-18

-55

Short Circuit
Output Current

Vee= Max
(Note 2)

lecH

Supply Current With
Outputs High

Vce=Max

4

ICCl

Supply Current With
Outputs Low

Vce= Max

5.1

los

,

8

mA

9.5

mA

,

Switching Characteristics

at Vcc = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)

Parameter

Conditions

tplH Propagation Delay Time
Low to High Level Output

(Expander Pins Open)

Cl=15 pF
Rl = 4000
Min

tpHl Propagation Delay Time
High to Low Level Output

Typ

Max

Units

13

22

ns

8

15

ns

Nole 1: Aillypicals are at VCC=5V, TA=25'C.
Nole 2: Nol more than one oulput should be shorted al a lime.

,
,

6·92

.------------------------------------------------------------------,0
3:

~National

(J1
.j:Io
(J1

~ Semiconductor

~

o

3:

~
.j:Io

DM5454/DM7454 4·Wide 2·lnput AND·OR·INVERT Gates

General Description

Absolute Maximum·Ratings

This device contains a combination of gates which performs the. logic ANO-OR-INVERT function.

Supply Voltage

(Note 1)
7V

Input Voltage
Storage Temperature Range

5.5V
- 65·C to 150·C

Note 1: Tho "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram
Dual-In-Line Package

B

VCC

MAKE NO EXTERNAL
CONNECTION

H

v

G.

8

7
A

C

E

D

F

NC

GND

TLlF/6522·1

DM5454 (J)

DM7454 (N)

Function Table
Y=AB + CQ + EF + GH
Inputs

H
X
X
X

Output

F G H
X X X
X X X
H X X
X H H

Y

All Other Combinations

H

A B C

D

E

X X X
X H H X
X X X H
X X X X

H

H = High Logic Level
L = Low Logic Level
X = Eilher Low or High logic Level

6-93

L

L
L
L

-

Recommended Operating Conditions
Sym

DM5454

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level Input
Voltage

10H

High Level Output
Current

10l

Low Level Output
Current

TA

Free Air Operating
Temperature

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Parameter

Units
V

2

-55

Electrical Characteristics
Sym

DM7454

Min

V

0.8

0.8

-0.4

-0.4

mA

16

16

mA

70

·C

125

0

V

over recommended operating free air temperature (unless otherwise noted)
Conditions

VI

Input Clamp Voltage

Vce= Min, 11= -12 mA

VOH

High Level" Output
Voltage

Vee = Min, 10H= Max
Vll= Max

VOL

Low Level Output
Voltage

Vee = Min, 10l= Max
VIH= Min

II

Input Current@Max
,
Input Voltage

IIH

Min

Typ
(Note 1)

2.4

3.4

Max
-1.5

0.2

Units
V
V

0.4

V

Vee = Max, VI = 5.5V

1

mA

High Level Input
Current

Vec = Max, VI = 2.4V

40

p.A

III

Low Level Input
Current

Vee = Max, VI':' 0.4V

-1.6

mA

los

Short Circuit
Output Current

Vee= Max
(Note 2)

mA

leeH

Supply Current With
Outputs High

Vec=Max

·4

8

mA

leel

Supply Current With
Output:; Low

Vec= Max

5.1

9.5

mA

DM54

-20

-55

DM74

-18

-55

I

Switching Characteristics
Parameter

at Vcc = 5V ·and -fA = 25·C (See Section 1 for Test Waveforms and Output Load)
CL =15 pF
Rl=4001l

Conditions
Min

Units

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

13

22

ns

tpHL Propagalior"! Delay Time
High to Low Level Output

8

15

ns

Nate

1: All typicals are at Vec=5V. TA=2S'C.

Nota 2: Not more than one output should be shorted at a time.

6·94

r---------------------------------------------------------------~c

s:

~National

en
~

~ Semiconductor

e
c

s:.......
~

DM5470/DM7470 AND-Gated Positive-Edge-Triggered
J-K Flip-Flop with Preset, Clear, and
Complementary Outputs
General Description

Absolute Maximum Ratings

This device is a positive-edge-triggered J-K flip-flop with
complementary outputs. Multiple J and K inputs are
ANDed together to produce the internal J and K function for the flip-flop. If the J and K inputs are not used
they must be grounded for proper operation of the flipflop. The J and K data is accepted by the flip-flop on the
positive going edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly
related to the transition time of the positive going edge
of the clock pulse. The clear and preset inputs are asynchronous but it is necessary that the clock input be at a
low level when they become active (low).

Supply Voltage
Input Voltage
Storage Temperature Range

Connection Diagram

(Note 1)

7V
5.5V
-65·Ct0150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the'
"Electrical Characteristics" table are not guaranteed at the absolute
max~mum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Dual-In-line Package
Inputs

NC

ClR

JI

TUFJ6523·,

DM5470 (J)

(Note 1)

K
(Note 1)

X

X
X
X

t
t
t
t

PR

ClR

ClK

L
H
L
H
H
H
H
H

H
L
L
H
H
H
H
H

L
L

L

DM7470 (N)

Q

Q

X
X
X

H
L
H*

L
H
H*

l
H
l
H

L
L
H
H

00

00

X

X

00

H
L
L
H
Toggle

00

~-

GND

JZ

Outputs

J

Nots I: J=(JIXJ2X'J), K=(KIXK2)(K) if the J and
they must be grounded.

R inputs are not used

H = High Logic Level
L Low Logic Level

=

X = Either Low or High Logic Level
t ;:: Positive Going Transition
.;:: This configuration is nonstable; that is, it will not persist when
preset and/or clear inputs return to their inactive (high) level.
00;:: The output logic level of Q before the indicated input conditions
were established.
Toggle;:: Each output changes to the complement of its previous level
on 8ach positive transition of the clock.

6-95

Recommended Operating Conditions
DM5470
Sym

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level
Input Voltage

IOH

DM7470

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

Units
V
V

0.8

0.8

High Level Output
Current

-0.4

-0.4

rnA

IOl

Low Level Output
Current

16

16

mA

felK

Clock Frequency

20

MHz

tw

Pulse Width

0

20

0

Clock
High

20

20

Clock
Low

30

30

Preset
Low

25

25

Clear
Low

25

25

tsu

Input Setup Time (Note 1)

201

201

tH

Input Hold Time (Note 1)

51

51

TA

Free Air Operating
Temperature

Note 1:

-55

ns
ns
70

0

Parameter

over recommended operating free air temperature (unless
Conditions

VI

Input Clamp Voltage

Vqe= Min, 11= -12 mA

VOH

High Level Output
Voltage

Vee = Min, IOH= Max
Vil = Max, VIH = Min

Val

Low Level Output
Voltage

Vee = Min, IOl= Max
VIH = Min, Vil = Max

II

Input Current@Max
Input Voltage

Vee= Max, VI= 5.5V

High Level Input
Current

Vee= Max
VI = 2.4V

·IIH

·ns

·C

The symbol  indicates the edge of the clock pulse is used for reference (I> for rising edge, (I) for falling edge,
Note2: All typlcals are at Vec=SV, TA=2S'C.
Note 3: I Not more than one output should be shorted at a time.

Note 4: With all outputs open, ICC Is measured with the Q and Cl outputs high in turn. At the time of measurement the clock input Is grounded.
Note 5: Clear Is measured with preset high and preset is measured with clear high.
6-111,

Units

V

. Clock

Preset
los

Max
-1.5

Preset
III

·C

mA

mA

Switching Characteristics
Parameter

at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
From
(Input)
To
(Output)

RL =4000
C L =15 pF

f MAX Maximum Clock
Frequency

Min

Typ.

15

20

Units
Max
MHz

tpHL Propagation Delay
Time High to Low
Level Output

Preset
to
a

25

40

ns

tpLH Propagation Delay
Time Low to High
Level Output

Preset
to
a

16

25

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
a

25

40

ns

tpLH Propagationj)elay
Time Low to High
Level Output

Clear
to

16

25

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
aora

25

40

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
aora

16

40

ns

Q

-

~·112

r-------------------------------~---------------------------------.c

3:

~National
~ Semiconductor

i

Co)

c

3:

~

DM5483/DM7483 4·Bit Binary Adders with Fast Carry

Co)

General Description
These full adders perform the addition of two 4-bit binary
numbers. The sum (l:) outputs are provided for each bit and
the resultant carry (C4) is obtained from the fourth bit.
These adders feature full internal look ahead across all four
bits. This provides the system designer with partial lookahead performance at the economy and reduced package
count of a ripple-carry implementation.
The adder logic, including the carry, is implemented in its
true form meaning that the end-around carry can be accomplished without the need for logic or level inversion.

Features

• Typical add times
Two 8-bit words 23 ns
Two 16-bit words 43 ns
• Typical power dissipation per 4-blt adder 290 mW

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

Connection Diagram
Dual-In-Line Package
:!:4

16

15

~4

C4
14

C4

CO
13

GND
112

CO

81

A1.
11

81

A4

9

A1
~1

A4

1

~1

10

84

A2

~3

2
~3

A3

3
1
A3

7V
5.5V
- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

• Full-carry look-ahead across the four bits
• Systems achieve partial look-ahead performance with
the economy of ripple carry

84

(Note 1)

83

14
83

82

:1:2

15
VCC

6
1
:!:2

7

B

82

A2
TL/F/6529·1

5483 (J)

7483 (N)

6-113

Recommended Operating Conditions
Sym

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

IOL

TA

.
Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

High Level Output
Current (Output C4)

-0.4

-0.4

High Lev~1 Output
Current"':'Other Outputs

-0.8

-0.8

Low Level Output
Current (Output C4)

8

8

Low Level Output
Current-Other Outputs

16

16

Parameter

-55

125

Conditions

Input Clamp Voltage

Vee= Min. 11= ~ 12 mA

VOH

High Level Output
Voltage

Vee=Min,loH=Max
VIL = Max, VIH = Min

Low Level Output

Vee = Min, 10L= Max
VIH = Min, VIL = Max

Voltag~

.v
mA

mA

·C

70

0

over recommended operating free air temperature (unless otherwise noted)

VI

VOL

V
V

0.8

Free Air Operating
Temperature

Units

2
0.8

Electrical Characteristics
Sym

DM7483

DM5483

Min

Typ
(Note 1)

2.4

3.4

Max

Units

-1.5

0.2

V
V

0.4

V

II

Input Current@ Max
Input Voltage

Vee= Max, VI= 5.5V

1

mA

IIH

High Level Input
Current

Vee= Max, VI= 2.4V

80

p.A

IlL

Low Level Input
Current

Vee = Max, VI = 0.4V

-3.2

mA

los

Short Circuit
Output Current
(Output C4)

Vee = Max
(Note 2)

DM54

-20

-55

mA

DM74

-18

-55

Short Circuit
Output Current
(Other Outputs)

Vee= Max
(Note 2)

DM54

-20

-70

DM74

-18

-70

Supply Current

Vee = Max (Note 3)

Icc

58

79

mA

Note 1: All typlcals are at Vee=SV. TA=2S'e:
Note 2: Not more than one output should be shorted at a time.
NDle 3: ICC is measured with all outputs open and all Inputs at 4.SV.

6·114

c

Switching Characteristics
Parameter

tpHL Propagation Delay
Time High to Low
Level Output
tpLH Propagation Delay
Time Low to High
Level Output
tpHL Propagation Delay
Time High to Low
Level Output
tpLH Propagation Delay
Time Low to High
Level Output
tpHL Propagation Delay
Time High to Low
Level Output
tpLH Propagation Delay
Time Low to High
Level Output

at Vee = 5V and TA = 25"CI (See Section 1 for Test Waveforms and Output Load)
From
(Input)
To
(Output)

CO

Max

20

32

ns

22

32

ns

22

38

ns

28

47

ns

28

47

ns

28

47

ns

33

ns

38

ns

12

19

ns

12

19 -

ns

12

19

ns

12

19

ns

~
Co)

to

E1,1::2
CO
to

1::3
CO
to

E3
CO
to

E4
CO
to

E4

Ai> B;

tpLH Propagation Delay
Time Low to High
Level Output

Typ

s:
.....

1::1, 1::2

tpLH Propagation Delay
Time Low to High
Level Output

tpHL Propagation Delay
Time High to Low
Level Output

Min

c

Units

to

Ai> B;

tpLH Propagation Delay
Time Low to High
Level Output

e-

RL=4000
CL=15pF

CO

tpHL Propagation Delay
Time High to Low
Level Output

tpHL Propagation Delay
Time High to Low
Level Output

s:
en

to

E;
to

E;
CO
to

C4
CO
to

C4
A;,B;

- to

C4
A;, B;

to

C4

!

6-115

~r-----------------------------------------------------------------------------,

~

Function Table

::E

o
c;;

!::E
o

Output

~
~
L;:

Input

co= L

co= H

X A3 ~83 ~A4 ~B4 ~ ~

When

When

C2= L

C2=H

~3

L

L
L

H

L
H

L
H

L
H

L
H

L

H
H

L
L
L
L

L
L

H

L

H
H

H
H

L
L

L
L

L
L
L
L

H
H
H
H
H
H
H
H

H
H

H
H

L

L
L

L

H

H

H

H

H
H
H
H

L
L
L
L
L

L

H
H

L
L
H
H

L
L
H
H

L
L

L
L
L

H
H
H
H

-

L

H

H
H
H

L
L
L
H

H
H

L
L
L
L

L

H

~X ~
~

L
L
L
L
L
L
L

H
H
H
H

H

L
L
H

H
L
L
H
H

L
L
H
H

L
L
H

L
H
H
H
H

L
L
L
L
L

L
L
L

H
H
H

H

L

L
L
L
L

H
H
H
H
H
H
H

H
H
H

=

H High Level. L = Low Level
Note
Input conditions al A 1, 81. A2. 82, and CO are used to determine outputs ~ 1 and l':2 and the value of the intemal carry
C2. The values at C2, A3, B3. A4. and 84 are then used to determine outputs l3, I4, and C4.

Logic Diagram
83

A2 (8)

B3(:.4~)

I----f-"

A3 ::"(3i):jtJ~:>>--frr~---------cL-~O---------~
A4!,"(l~):jtJ~:>>---~~---------cL-~~--------~
;
TL/F/6529-2

6·116

~National

~ Semiconductor

DM5485/DM7485 4-Bit Magnitude Comparators

General Description

Features

These 4-bit magnitude comparators perform comparison
of straight binary or BCD codes. Three fully-decoded decisions about two 4-bit words (A, B) are made and are externally available at three outputs. These devices are fully
expandable to any number of bits without external gates.
Words of greater length may be compared by connecting
comparators in cascade. The A>B, A< B, and A = B outputs of a stage handling less-significant bits are connected to the corresponding inputs of the next stage
handling more-significant bits. The stage handling the
least-significant bits must have a high-level voltage applied to the A = B input. The cascading paths are implemented with only a two-gate-Ievel delay to reduce
overall comparison times for long words.

• Typical power dissipation 275 mW
• Typical delay (4-bit words) 23 ns

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

7V
5.5V
- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the

"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram
Dual-In-Line Package
DATAtNPUTS

Vcc

A3

B2

A2

A1

B1

AO

BO

10

B3

9

BO

8

B3 ABA>BA=BAB

40

Low Level Input
Current

Vee = Max
VI=O.4V

Others
IlL

120

AB

-1.6

Others
los
Icc

Short Circuit
Output Current

Vce= Max
(Note 2) .

Supply Current

Vce= Max
(Note 3)

mA

-4.8

DM54

-20

-55

DM74

-18

-55
55

-

Nota 1: All typicals are at Vce=SV, TA=2S"C.
Note 2: Not more than one output should be shorted at a time.
Nota 3: ICC Is measured with all outputs open. A = B Input grounded and all other Inputs at 4.SV.

6-118

V
V

2.4

88

mA
mA

Switching Characteristics

at Vee = 5V and TA= 25°C (See Section 1 for Test Waveforms and Output Load)
RL=4001l

Parameter

tpLH Propagation Delay Time
Low-to-High Level Output

tpHL Propagation Delay Time
High-to-Low Level Output

C L =15pF

From
Input

To
Output

Number 01
Gate Levels

Any A or B
pata Input

AB

1

7

2

12

Any A or B
Data Input

Min

Typ

Max

Units
. ns

3

17

26

A=B

4

23

35

AB

1

11

2

15

ns

3

20

30

A=B

4

20

30

tpLH Propagation Delay Time
Low-to-High Level Output

AB

1

7

11

ns

tpHL Propagation Delay Time
High-to-Low Level Output

AB

1

11

17

ns

tpLH Propagation Delay Time
Low-to-Hlgh Level Output

A=B

A=B

2

13

20

ns

tpHL Propagation Delay Time
High-to-Low Level Output

A=B

A=B

2

11

17

ns

tpLH Propagation Delay Time
Low-to-High Level Output

A>B
orA=B

AB
or A=B

A 83
A3 < 83
A3= 83

A3= 83
A3" 83
A3.:: 83

c

A3A3'"
A3'"
A3'"

83
83
83
83

A3 II: 83
A3= 83

=

A3 83
A3'" 83

A2>82
A2<82
A2
82
A2 "'·82
A2
82
A2 .... 82
A2
82
A2 - 82

=
=
=
A2 = 82

A2 .... 82
A2 = 82

A1 >81
A1 <81
A1 ... 81
At ... 81
A1 - 81
A1
81
A1'" 81
A1 ... 81
A1 8t

A2" 82

A1" 81

H - High Level, L

outputs

Inpula

A2, B2

=
=

A>B AB A80
AO<80
AO- BO

AD

= BO

AO ... 80
AO= 80

AD'" BO
AO= BO

X
X
X
X
X
X
X

X
X
X
X
X
X
X
X

H
L
L

L
H
L

X

X

H
L

H
L

X

X
X
X
X
X
X
X
X
L
L

H
L
H
L
H
L
H
L
H
L

L
H
L
H
L
H
L
H
L
H
L
L
L
H

L

H
H
L
L

L

L
H

L
L
L
L
L
L
L'
L
L
L
H
H
L
L

=Low Level. X ... Don't Care

Logic Diagram
85
)-A3
B3

(15)
(1)

P-

}>~~
L

5
A2
B2

AB

Al

Bl

(13)
(14)

P-

Rr

6=JD- ,Hv~

(2)
(3)

(6)

A=B

(4)

~

(12)
(11)

~

p-

~§b-

~

L

~~

~

AO
BO

A>B

(10)

~
(9)

m A-______1(2~)+-______________(13~)+-______________1(4~)+-______________(,5)
~

CDNTROL

S~~~

___
(1_)+-____+-____~

RIG~~~~~ __(_9_'+--i__')
CLDCK 2
LEFT SHIFT

(8)

--'-'---i,-,)

(II,

(12,

(13)

QC

08

• QA

OUTPUTS

TLlF/6534·2

6-136

~--------------------------------------------------------------,o

3:

~National

UI

cten

~ Semiconductor

-

DM5496/DM7496 5·Bit Shift Registers

cten

o
3:
-...I

General Description

Features

These shift registers consist of five R-S master-slave flipflops connected to perform parallel-to-serial or serial-toparallel conversion of binary data. Since both inputs and
outputs for all flip-flops are accessible, parallel-in/parallelout or serial-in/serial-out operation may also be performed.

• N-bit serial-to-parallel converter
• N-bit parallel-to-serial converter
• N-bit storage register

All flip-flops are simultaneously set to a low output level by
applying a low-level voltage to the clear input while the
preset is low. Clearing is independent of the leve! of the
clock input.

Absolute Maximum Ratings
Supply Voltage
Input Voltage

The register may be parallel loaded by using the clear input
in conjunction with the preset inputs. After clearing all
stages to low output levels, data to be loaded is applied to
the individual preset inputs (A, B, C, D, and E) and a highlevel load pulse is applied to the preset enable input.
Presetting is also independent of the level of the clock
input.

7V
S.SV

Storage Temperature Range

which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will

define the conditions for actual device operation.

Connection Diagram
Dual-ln·Line Package
OUTPUTS
r

,

OA

16

15

Os

14

Oc

13

GND

OUTPUTS
•
, SERIAL
OE INPUT

OD

11

112

10

9

'--

r-

-

l-

2

I

CLOCK

A

4

3
S

- 6S·C to 1S0·C

NOle 1: The "Absolute Maximum Ratings" are those values beyond

Transfer of information to the outputs occurs on the positive-going edge of the clock pulse. The proper information
must be set up at the R-S inputs of each flip-flop prior to the
rising edge of the clock input waveform. The serial input
provides this information to the first flip-flop, while Ihe oulputs of the subsequent flip-flops provide information for the
remaining R-S inputs. The clear input must be high and the
preset or preset enable inputs "must be low when clocking
occurs.

CLEAR

(Note 1)

C

--.----"

'-'

PRESET

6

15
Vce

7

8

E PRESET
D
'---.---' ENABLE
PRESET
TL/F/6535·1

5496 (J) 7496 (J, N)

6-137

Recommended Operating Conditions
DM7496

DM5496
Sym

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level
Input Voltage

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units
V
V

2
0.8

0.8

V

IOH

" High Level Output
Current

-0.4

-0.4

mA

IOL

Low Level Output
Current

16

16

mA

fCLK

Clock Frequency

10

MHz

tw

Pulse Width

0

10

0

Clock

35

35

Preset

30

30

Clear

30

30

tsu

Serial Setup Time

30

30

tH

Serial Hold Time

0

0

TA

Free Air Operating

-55

Tern~rature

Peremeter

Conditions

Min

Input Clamp Voltage

Vee = Min. 11= -12 mA

VOH

High Level Output
Voltage

Vee=Min.loH=;Max
V IL = Max. VIH = Min

VOL

Low Level Output
Voltage

Vee= Min. 10L= Max
VIH = Min. VIL= Max

II

Input Current@Max
Input Voltage

Vee = Max. VI = 5.5V

IIH

High Level Input
Current

Vee= Max
VI = 2.4V

IlL

Low Level Input
Current

Vee = Max
VI = 0.4V

los

Icc

ns

0

70

DC

over recommended operating free air temperature (unless otherwise noted)

VI

\

ns

~

Electrical Characteristics
Sym

125

ns

,
Short Circuit
Output Current

Vee = Max
(Note 2)

Supply Current

Vee = Max
(Note 3)

Typ
(Note 1) "

Max
-1.5

2.4

3.4
0.2

Preset
Enable

0.4

V

1

mA

200

p.A

40

Preset
Enable

-8

Others

-1.6

DM54

-20

-57

DM74

-18

-57

DM54 "

:48

68

DM74

48

79

6-138

V
V

Others

Note 1: All typlcals are at Vee=SV. TA=2S"e."
Note 2: Not more than one output should be shorted at a time.
Nota 3: ICC is measured with the.clear Input grounded and all other Inputs and outputs open.

Units

mA

rnA

mA

Switching Characteristics
Parameter

.

at Vee = 5V and TA= 25°C (See Section 1 for Test Waveforms and Output Load)
From
(Input)
To
(Output)

'R L =400U
CL=15 pF
Min

fMAX Maximum Clock
Frequency

Typ

Units
Max

10

MHz

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
Output

25

40

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
Output

25

40

ns

tpLH Propagation Delay
Time Low to High
Level Output

Preset
to
Output

25

35

ns

tpLH Propagation Delay
Time Low to High
Level Output

Enable
to
Output

25

35

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
Output

55

ns

,

III

6·139

~

Function Table

::E

c

Inputs

co
~

Clear

c

L
L
H
H
H
H
H
H

::E

H
X

Preset

Outputs

Preset

Enable A
L

X
L
H
L
H
X

X
H
H
H
L
L
L

X

B

C

D

E

X
L
H
L
L

X
L
H
L
H
X
X

X
L
H
L
L

X
L
H
L
H

X
X

X
X
X

X
X

Clock Serial QA
X

X

X
X

X

X

t
t

H
L

X X X X
= high level (steady state), L = low level (steady state)
=

d~n't

-X

L
L
L

X
X

L
L
H
QAO
H
QAO
H
L

QB

QC

QD

QE

L
L
H
QBO
QBO
QBO
QAn
QAn

L
L
H
QCO
H
QCO
QBn
QBn

L
L
H
QDO
QDO
QDO
QCn
QCn

L
L
H
QEO
H
QEO
QDn
QDn

care (any input, including transitions)

, = transition trom low to high level
0AD. Qeo. elc = the level of QA. aS. etc., respectively before the indicated
steady state input conditions were established.
0An. 0Bn. etc. = the level of QA.
etc., respectively before the most recent
of the clock.

aS.

. t tranSition

Logic Diagram
PRESET

PRESET

PRESET

(
PRESET

A

B

C

0

(2)

OUTPUT (3)
QA

OUTPUT (4)
QB

OUTPUT (6)
QC

PRESET
OUTPUT (7)
QO

E

PRESET..;.(8~)____________-+~__(1_5~)~__-r~__(1_4_)~__-r~_'_(1_3i) ____i-.-__
(1_1)i-__-i-,

OUTPUT
QE
(10)

ENABLE -

CLOCK

TLIF16535-2

6·140

c

s:

Timing Diagram

(II

ct

Typical Clear, Shift, Preset, and Shift Sequences

.s:
Q)

c

CLOCK
CLEAR

-w

SERIAL
INPUT

~

Q)

III

n

PRESET
ENABLE

r IHl
riHl

A
B
PRESETS

L

C

r IHl

o

L

E

--

OA __ :~I

__

I

oB::.1
OUTPUTS

Oc

00
OE

::.1
=:J

~:.l

CLEAR

~r-l~

__________

~r--l~

_______

~l____~

.I I

I

I

II
II

L-

!LJ

n i L ftil.....!:..J

------SHIFT------i
PRESET

H

I

H

L

I---SHIFT-

TLlF/6535·3

6·141

.....

~. ~ National
~ ~ Semiconductor
r:::
o

....

~ DM54107/DM74107 Dual Master-Slave J-K Flip-Flops with

c Clear and Complementary Outputs
General Description

Absolute Maximum Ratings

This device contains two independent positive pulse
triggered J-K flip-flops with complementary outputs.
The J and K data is processed by the flip-flops after a
complete clock pulse. While the clock is low the slave is
Isolated from the master. On Ihe positive transllion of
the clock, the data from the J and K'inputs is transferred
to the master. While the clock is high the J and K inputs
are disabled. On the negative transition of the clock, the
data from the master is transferred to the slave. The
logic states of the J and K inputs must not be allowed to
change while the clock Is high. Data is transferred to
the outputs on the falling edge of the clock pulse. A low
logic level on the clear input will reset the output
regardless of the logic states of the other inputs.

Supply Voltage
Input Voltage
Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

(Note 1)

7V

5.5V
-65·Cto150·C

Dual·ln·Llne Package
Inputs

Outputs

CLR

CLK

J

K

Q

L

X

X

X

L

H

H'

.I1..

L

00

00

H
H
H

.I1..

H

L
L

.I1..

L

.I1..

H

H
H

Q

L
L
H
Toggle

H

=

H High Logic Level
X= Either Low or High Logic Level
L= Low Logic Level
.J"L
Positive pulse data. The J and K Inputs must be held constant while
the clock Is high. Oata Is transferred to the outputs on the falling edge of
the clock pulse.

=

TLlF16536·'

DM54107 (J)

DM74107(N)

=

00 The output logic level before the Indicated input conditions were
established.
Toggle Each output changes to the complement of its previous level
on each complete positive cloc~ pulse.

=

6·142

c

:s::
en

Recommended Operating Conditions
Sym
Vee

Supply Voltage

V,H

High Level Input
Voltage

V,L

Low Level
Input Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

feLK

Clock Frequency

tw

Pulse Width

DM74107

DM54107

Parameter

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

0

20

0.8

-0.4

-0.4

mA

16

16

mA

15

MHz

15

20

Clock
Low

47

47

Clear
Low

25

25

Input Setup Time (Note 1)

01

01

tH

Input Hold Time (Note 1)

01

01

TA

Free Air Operating
Temperature

-55

20

0

20

Parameter

V

0.8

tsu

Sym

125

Conditions

ns

ns
ns

Vee = Min, 1,= -12 mA

VOH

High Level Output
Voltage

Vee = Min, 10H = Max
V,L = Max, V,H = Min

VOL

Low Level Output
Voltage
.'

Vee= Min, 10L= Max
V,H = Min, V,L.= Max

I,

Input Current@Max
Input Voltage

Vee = Max, V,=5.5V

I'H

High Level Input
Current

Vee= Max
V, = 2.4V

Low Level Input
Current

Vee= Max
V, = 0.4V

Short Circuit
Output Current

Vee= Max
(Note 3)

Supply Current

Vee= Max (Note 4)

Typ
(Note 2)

0.2

V
V

0.4

V

1

mA

k

40

Clock

80

J,

Units

3.4

-

-1.6

Clock

-3.2

mA

-3.2

DM54

-20

-55

DM74

-18

-55
18

34

The symbols (t. I) Indicate the edge of the clock pulse Is used for reference: t for rising edge. J for falling edge.
All typicals are at Vee =SV, TA =2s'e.
Not more than one output should be shorted at a time.
With all outputs open, lee is measured with the Q and Q outputs high in turn. At the time of measurement t~e clock input is grounded.

6·143

"A

80

J,K
Clear

Note 1:
Note 2:
Note 3:
Note 4:

Max
-1.5

2.4

Clear

lee

DC

70

0

Min

Input Clamp Voltage

los

V

over recommended operating free air temperature (unless otherwise noted)

V,

I,L

V

2

Clock
High

Electrical Characteristics

Units

mA

mA

....""o

-:s::c
......

:;;!

....

o......

.....

o,...
oqo

.....
:!E
c
.....

-,...

Switching Characteristics

at Vcc=5V and TA=25"C (See Section 1 for Test Waveforms and Output Load)
From
(Input)
To
(Output)

Parameter

o

RL=4000
CL=15 pF
Min

Typ

15

20

Units
Max

'oqo
Lt)

:!E
c

fMAX Maximum Clock
Frequency

MHz

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
a

25

40

tpLH Propagation Delay
Time Low to High
Level Output

Clear
to
a

16

25

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
aorO

25

40

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
aorO

16

25

ns'

ns

ns
~

~

\

,
I

I

(

6·144

r------------------------------------------------------------------,c
s:
en
~National

.j::o

.....

.~ Semiconductor

-s:
~

c

.....
.j::o
.....

DM54109/DM74109 Dual Positive-Edge-Triggered
J-K Flip-Flops with Preset, Clear,
and Complementary Outputs

o

CO

General Description

Absolute Maximum Ratings

This device contains two independent positive-edgetriggered J-K flip-flops with complementary outputs.
The J and K data Is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a
voltage level and is not directly related to the transition
time of the rising edge of the clock. The data on the 'J
and K inputs may be changed while the clock is high or
low as long as setup and hold times are not violated. A
low logic level on the preset or clear inputs will set or
reset the outputs regardless of the logic levels of the
'
other inputs.

Supply Voltage
Input Voltage
Storage Temperature Range

which the safety of the device can not be guaranteed. The device should

Connection Diagram

Function Table

(Note 1)
7V

5.5V
-65·Ct0150·C

Note 1: The "Absolute Maximum Ratings" arB those values beyond
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual-In-line Package

vI: Clj,2
" "

J2
14

I

.2

I"L

CLK2

"2

12

I"

.2
10

.2

,

~

r----

~~-.J
2
eLR!

Jl

J'
KI

I

I

I'

I'

elK!

PH 1

I

.,I'

.,J'

I'

DM74109 (N)

ClR

ClK

J

K

Q

l
H
L
H
H
H
H
H

H
L
L
H
H
H
H
H

X
X
X

X
X
X

X
X
X

t
t
t
t

L
H
L
H

l
l
H
H

L

X

X

H
l
L
H
H*
H*
L
H
Toggle
Cio
Qo
H
L
Cio
Co

Q

GNO

TLlF16537·1

DM54109 (J)

Outputs

Inputs

PR

H = High Logic Level
L= Low Logic Level
1= Rls'lng Edge of Pulse
*=Thls configuration Is nonstable; that is, It will not persist when
preset and clear Inputs return to their Inactive (high) level.
00 = The output logic level of 0 before the Indicated In'put conditions
were established.

Toggle = Each output changes to the complement of Its previous level
on each active transition of the clock pulse.

6-145

Recommended Operating Conditions
DM74109

DM54109
Sym

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level
Input Voltage

IOH

High Level Output
Current

IOl

Low Level Output
Current

felK

Clock Frequency

tw

Pulse Width

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

\
0

Units
V
V

0.8

0.8

-1.2

-1.2

mA

16

16

mA

30

MHz

0

30

Clock
High

20

20

Clock
Low

20

20

Preset
Low

20

20

Clear
Low

20

20

V

ns

tsu

Input Setup Time (Note 1)

151

151

ns

tH

Input Hold Time (Note 1)

101

101

ns

TA

Free Air Operating
Temperature

-55

Electrical Characteristics
Sym

125

Parameter

Conditions

Min

Input Clamp Voltage

Vee = Min, 11= -12 mA

VOH

High Level Output
Voltage

Vee = Min, IOH= Max
Vil = Max, VIH ="Min

VOL

Low Level OutplJt
Voltage

Vee = Min, IOl= Max
VIH = Min, Vil = Max

II

Input Current@ Max
Input Voltage

Vee = Max, VI = 5.5V

IIH

High Level Input
Current

Vee= Max
VI=2.4V

Low Level Input
Current

70

Vee= Max
VI =0.4V
(Note "5)

Typ
(Note 2)

Icc
Note t:
Note 2:
Note 3:
Note 4:
Note 5:

Short Circuit
Output Current

Vee = Max
(Note 3)

Supply Current

Vee = Max (Note 4)

Max
-1.5

2.4

3.4

Units
V
V

0.4

V

1

mA

J, K

40

/lA

Preset

80

0.2

Clock

80

Clear

160

J, K

-1.6

Preset
Clock

-3.2
-3.2

DM54

-30

-85

DM74

-30

-85
20

30

The symbol (1) Indicates the rising edge of the clock pulse Is used for reference.
All typicals are at Vee = SV, TA = 2S'e.
Not more than one output should be shorted at a time.
With all outputs open, ICC is measured with the Q and outputs high in turn. At the time of measurement the clock Input grounded.
Clear is tested with preset high and preset is tested with clear high.

a

6·146

mA

-4.8

Clear
los

·C

over recommended operating free air temperature (unless otherwise noted)

VI

IlL

0

mA

mA

Switching Characteristics, fit Vee= 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
Parameter

From
(Input)
To
(Output)

RL=4001J
C L =15 pF

f MAX Maximum Clock
Frequency

Min

Typ

30

40

Units
Max

MHz

tpLH Propagation Delay
Time Low to High
Level Output

Preset
to
Q

9

14

ns

tpHL Propagation Delay
Time High to Low
Level Output

Preset
to

18

29

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clear
to

9

14

ns

tpHL Propagation Delay.
Time High to Low
Level Output

Clear
to
Q

17

25

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
QorO

12

18

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
QorO

19

28

ns

Q

Q

.

I

\

6·147

.C\I

.~
:E

-c.-

r---------------------~------------------------------------------------------------_,

~National

~. Semiconductor

C\I

~ DM54121fDM74121 One-Shot with Clear and
~ Complementary Outputs
General Description

Absolute Maximum Ratings

The DM54174121 is a monostable multivibrator featuring
both positive and negative edge triggering with complementary outputs. An Internal 2kll timing resistor Is
provided for design convenience minimizing component
count and layout problems. This device can be used
with a single external capacitor. Inputs (A) are activelow trigger transition inputs and input (S) is an active-high
transition Schmitt-trigger input that allows jitter-free triggering from inputs with transition rates as slow as 1 voltl
second. A high immunity to Vcc noise of typically 1.5V Is
also provided by internal circuitry at the input stage.

Supply Voltage
Input Voltage
Storage Temperature Range

To obtain optimum and trouble free operation please
read operating rules and NSC one-shot application
notes carefully and observe recommendations.

Functional 'Description

Features
• Triggered from active-high transition or active-low
tranSition inputs
• Variable pulse width from 30 ns to 28 seconds
• Jitter f~ee Schmitt-trigger input
• Excellent noise immunity typically 1.2V
• Stable pulse width up to 90% duty cycle
• TTL, DTL compatible
• Compensated for Vcc and temperature variations
• Input clamp diodes

Connection Diagram

(Note 1)

7V
5,5V
- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the

"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

The basic output pulse width Is determined by selection
of the internal resistor RINT or an external resistor (Rx)
and· capaCitor (Cx). Once triggered the output pulse
width is independent of further transitions of the Inputs
and is a function of the timing components. Pulse width
can vary from a few nano-seconds to 28 seconds by
choosing appropriate Rx and Cx combinations. There
are three trigger inputs from the device, two negative
edge-triggering (A) Inputs, one positive edge Schmitttriggering (S) input.

Function Table

Dual-In-Line Package
VCC

NC

NC

NC

Al

REXT/
CEXT CEXT

A2

B

Inputs
NC

A2

B

Q

Q

L

X

X
X

L

H
H
L

L
L
L
L

H
H
H
H
-u-u-u-u-u-

X

H
H

H

X

I

J"L

I
I

H

H
H
H

L

X
L

t
t

J"L

X

I

J"L
J"L

J"L

H = High Logic Level
L= Low logiC Level
X= Can Be Either Low or High

GND
TLlF/653B·l

DM54121 (J)

Outputs

A1

DM74121 (N)

6-148

f = Positive Going Transition
I = Negative Going Transition
J"L = A Positive Pulse
-U- = A Negative Pulse

c

3:
~
....

Recommended Operating Conditions
Sym

Parameter

DM54121

Units

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V

1.4

2

1.4

2

V

Vee

Supply Voltage

VT+

Positive·Going Input
Threshold Voltage
at the A Input
(Vee = Min)

VT_

Negative·Going Input
Threshold Voltage
at the A Input
(Vee = Min)

VT+

Positive·Golng Input
Threshold Voltage
at the B Input
(Vee = Min)

VT_

Negative·Going Input
Threshold Voltage
at the B Input

10H

High Level Output
Current

-0.4

-0.4

mA

10l

Low Level Output
Current

16

16

mA

tw

Input Pulse Width

dV/dt

Rate of Rise or Fail
of Schmitt Input (B)

1

1

VIs

dV/dt

Rate of Rise or Fall
of Logic Input (A)

1

1

V/p.s

0.8

1.4

1.5

0.8

0.8

2

1.3

0.8

50

1.4

1.5

2

1.3

50

ns .

30

1.4

40

kO

CEXT

External Timing
Capacitance

0

1000

0

1000

p.F

DC

Duty Cycle

%

Free Air Operating
Temperature

RT=2 kO

67

67

RT = REXT(Max)

90

90

-55

125

6·149

0

N
....

V

1.4

TA

~
....

V

External Timing
Resistor

I

c
3:

V

REXT

I

-....
N

DM74121

Min

70

DC

•

Electrical Characteristics
Sym

over recommended operating free air temperature (unless otherwise noted)

Parameter

Conditions

Ii=

Min

Typ
(Note 1)

2.4

3.4

Max

VI

Input Clamp Voltage

Vee= Min,

VOH

High Level Output
Voltage \

Vee=Mln,loH=Max,
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee= Min, 10L= Max
VIH=Min, VIL='Max

II

Input current@Max
Input Voltage

Vee = Max, VI = 5.5V

IIH

High Level Input
Current

Vee = Max
VI=2.4V

Low Level Input
Current

Vee = Max
VI = O.4V

A1, A2

-1.6

B

-3.2

los

Short Circuit
Output Current

Vee = Max
(Note 2)

DM54

-20

DM74

-1B

lee

Supply Current

Vee= Max

IlL

Switching Characteristics
Parameter

-1.5

-12 mA

Units
V
V

0.2

0.4

V

1

mA

A1, A2

40

/LA

B

BO

-55

mA

mA

-55

aulescent

13

25

Triggered

23

40

mA

at Vee = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)'

From
(Input)
To
(Output) .

tpLH Propagation Delay
Time Low to High
Level Output

A1, A2
to
a

tpLH Propagation Delay
Time Low to High
Level Output

B
to
a

tpHL Propagation Delay
Time High to Low
Level Output

A1, A2
to

tpHL Propagation Delay
Time High to Low
Level Output

B
to

Conditions

Min

Max

Units

45 '

70

ns·

35

55

ns

50

BO

ns

40

65

ns

150

ns

30

50

ns

600

700

BOO

ns

6

7

8

ms

CEXT=BO pF
RINT to Vee
CL= 15 pF
RL=4000

Typ

Q

Q

tW(OUT) Output
Pulse Width using
the Internal Timing
Resistor

A1, A2 or B
to
a,a

CexT=BO pF
RINT to Vee
RL=4000
CL = 15pF

tW(OUT) OutPl,lt
Pulse Width using
Zero Timing
Capacitance

A1, A2
to
a,a

CexT=O pF
RINT to Vee
RL=4000
CL =15pF

tW(OUT) Output
Pulse Width using
External Timing
Resistor

A1, A2
to
a,a

CEXT= 100 pF
REXT= 10 kO
RL=4000
CL= 15pF

A1,A2
to
a,a

CEXT= 11'F
RexT= 10 kO
RL=4000
CL= 15pF

Note 1: All typlcals are at VCC=5V, TA=25·C.
Not. 2: Not more than one output should be shorted at a time.

6-150

70

110

r

c

:s:
CJI

10~~~~~~-.~-,

Operating Rules

Rm=5K
Cm=1000 pF
5 I- TA=25 D C

1. To use the internal 2 kll timing resistor, connect the
A, NT pin to Vee.

.
.....
w

z'"
:c

2. An external resistor (Ax) or the Internal resistor (2 kll)
and an external capacitor (ex) are required for proper
operation. The value of ex may vary from 0 to any
necessary value. For small time constants use highquality mica, glass, polypropylene, polycarbonate, or
polystyrene capacitors. For large time constants use
solid tantalum or special aluminum capacitors. If the
timing capacitors have leakages approaching 100 nA
or if stray capacitance from either terminal to ground
is greater than 50 pF the timing equations may not
represent the pulse width the device generates.

0

~

-5

~
......
......

-:s:
N

--

C

~
......

N

......

-10

4

5.5

4.5

TLIFI6538-4

Vee (V)

FIGURE 3
10

3. The pulse Width is essentially determined by external
timing components Ax and ex. For Cx < 1000 pF see
Figure 1 design curves on Twas function of timing
components value. For ex > 1000 pF the output is
defined as:

Rm=5K
Cm= 1000 pF
Vee=5.0V

5

......

w

'"
...'"
z
:c

..

0

~ .........

~

-- r- -

-5

Tw=KAxCx
where [Ax is in Kilo-ohm]
[Cx Is in pico Farad]
[rw is in nano second]

-10~~~~~~~~~

-60 -30 0

30

60

90 120 150

AMBIENT TEMPERATURE (DC)

[K=O.7]

TLlFI6538·5

FIGURE 4

6. The "K" coefficient Is not a constant, but varies as a
function of the timing capacitor Cx. Figure 5 details
this characteristic.
100 ~F r-rT"T-n--nr-rTT-n-rr-n
TA=25D C
lD ~F I-+++-H--HI-+++ Vec=5.DV
l~F ~++-H-HI-+++-H~rt1

iii .D.l ~F
100
Cm (pF)

1000

... 104 pF

H-++++-HH-++++-H-H

1()3 pF

I-+++++-HH-++++-H-H

102 pF I-+++++-+-I\+-++++-H-H

TLlF16538·2

10 pF

FIGURE 1

LL..LJ....Ll...L.LL.Jo.L..Ll..LJL..W

o

.2

.4 .6 .8 1.0 1.2 1.4 1.6
TLlF16538·6
"K" COEFFICIENT

FIGURES

4. If Cx is an electrolytic capacitor a switching diode is
often required for standard TTL one-shots to prevent
high inverse leakage current (Figure 2).

Rx

7. Under any operating condition Cx and Ax must be
kept as close to the one-shot devIce pins as possible
to minimize stray capacitance, to reduce noise pickup, and to reduce I x A and Ldi/dt voltage developed
along their connecting paths. If the lead length from
Cx to pins (10) and (11) is greater than 3 cm, for example, the output pulse width might be quite different
from values predicted from the appropriate equations. A nO'n-inductive and low capacitive path is
necessary to ensure complete discharge of Cx in
each cycle of its operation so that the output pulse
width will be accurate.

0

vee~PtN(II)
Cx

t-

FIGURE 2

PIN (10)

TLIFI6538-3

B. Vee and ground wiring should conform to good highfrequency standards and practices so that switching
transients on the Vee and ground return leads do not
cause Interaction between one-shots. A 0.011'F to 0.10
I'F bypass capacitor (disk ceramic o'r monolithic type)
from Vee to ground is necessary on each device. Furthermore, the bypass capacitor should be located as
close to the Vee-pin as space permits.

5. Output pulse width versus Vee and operation temperatures: Figure 3 depicts the relationship between pulse
width variation versus Vee. Figure 4 depicts pulse
width variation versus ambient temperature.

• For further detailed device characteristics and output performance
please refer to the NSe one·shot application note, AN-366.

6-151

~

~ ~ National

~
~

~
:E

o

' .
~ Semiconductor

DM54123/DM74123 Dual Retriggerable One-Shot with
Clear and Complementary Outputs
General Description

Absolute Maximum Ratings

The DM54174123 is a dual retriggerable monostable
multivlbrator capable of generating output pulses from
a few nano-seconds to extremely long duration up to
1000/0 duty cycle. Each device has three Inputs permitting the choice of either leading-edge or trailing edge
triggering. Pin (A) is an active-low transition trigger input
and pin (8) is an active-high transition trigger input. The
'Clear (CLA) Input terminates the output pulse at a prede-'
termlned time independent of the timing components.

Supply Voltage
Input Voltage
Storage Temperature Aange

National's '123 device features an unique logic realization not implemented by other manufacturers. The
"Clear" input will not trigger the device, a design
tailored for applications where it shall only terminate or
reduce a timing pulse.
To obtain the best and trouble free operation from this
device please read the operating rules as well as the
NSC one-shot application notes carefully and observe
recommendations.

Features

(Note 1)

7V
5.5V
-65·Ct0150·C

Note 1: The "Absolute MaXimum Ratings" are 'those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Functional Description'
The basic output pulse width Is determined by selection of
an external resistor (Rx) and capacitor (Cx). Once triggered,
the basic pulse width may be extended by retriggerlng the
gated active-low transition or active-high transition inputs
or be reduced by use of the active-low transition clear input.
Retriggerlng to 100% duty cycle is possible by application
of an input pulse train whose cycle time is shorter than the
output cycle time such that a continuous "HIGH" logic
state is maintained at the "Q" output.

• DC triggered from active-high transition or active-low
transition Inputs
•
•
•
•
•

Retrlggerable to 100% duty cycle
Direct reset terminates output pulse
Compensated for Vee and temperature variations
DTL, TTL compatible
Input clamp diodes

Function Table

Connection Diagram
Dual-In-Line Package
REXT 1
VCC CeXT CeXT 1 Q1

14

02

CLR 2

Inputs
B2

CLEAR

A2

13

L
H
H
H
H

Q

Outputs

A

B

Q

Q

X
H

X
X

X

H
H
H
-u-u-

L

L
L
L

L

t

.sL

I

H

.sL

H = High Logic Level
L = Low Logic Level
X = ean Be Either Low or High

Q

t = Positive Going Transition
4
A1

B1

CLR 1 01

i= Negative Going TranSition

5

.sL

Q2 CeXT 2 ReXT 2 GND
eeXT

-U-

TlfF/6539·1

DM54123 (J)

DM74123 (N)

6-152

=

A Positive Pulse
= A Negative Pulse

Recommended Operating Conditions
Sym

DM54123

Parameter

Vcc

Supply Voltage

V IH

High Level Input
Voltage

VIL

Low Level
Input Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

tw

Pulse Width

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

,

-0.8

-0.8

mA

16

16

mA

40

AcrB
Low

40

40

Clear
Low

40

40

REXT

External Timing
Resistor

CEXT

External Timing
Capacitance

C WIRE

Wiring Capacitance
at REXT/CEXT Terminal

TA

Free Air Operating
Temperature

45
5

45
5

No Restriction
50

Electrical Characteristics

0

over recommended operating free air
Conditions

VI

Input Clamp Voltage

Vcc= Min, 11= -12 mA

VOH

High Level Output
Voltage

Vcc= Min, 10H= Max
VIL = Max, VIH = Min

VOL'

Low Level Output
Voltage

Vcc = Min, 10L = Max
Viti = Min, VIL= Max

II

Input Current@Max
Input Voltage

Vcc = Max, VI = 5.5V

IIH

High Level Input
Current

Vcc=Max
VI = 2~4V

IlL

Low Level Input
Current

Vcc=Max, VI = 0.4V

los

Short Circuit
Output Current

Vcc= Max
(Note 2)

Icc

Supply Current

Vcc= Max
(Notes 3 and 4)

I DM74

ns

50

kG
I'F

50

pF

70

·C

temp~rature (unless otherwise noted)

Min

Typ
(Note 1)

2.5

3.4

Max
-1.5

0.2

I Data
I Clear

I DM54

65

No Restriction

125

V

ns

65
25

-55

V
V

0.8

40

A or B

Units

0.8

A or B
High

Minimum Width of
Pulse at Q

Parameter

Nom

2

TWQ
(Min)

Sym

DM74123

Min

Units
V
V

0.4

V

1

mA

40

f.!A

80

-10
-10

-1.6

mA

-40

mA

-40
46

66

mA

Nota t: All typlcals are at VCC=5V, TA=25"C.
Nola 2: .Not more than one output should be shorted at a time.
Note 3: Quiescent ICC Is measured (after clearing) with 2.4V applied to all clear and A Inputs, B Inputs grounded, all outputs open, CEXT = 0.02 pF, and
REXT= 25 kO.
Note 4: ICC Is measured In the triggered state with 2.4V applied to all clear and B inputs, A Inputs grounded. all outputs open, CEXT=0.02 pF, and
REXT=25 kll.
6·153

•

·

Switching Characteristics
Parameter

From
(Input)
to
(Output)

A

tpLH Propagation Delay
Time Low to High
Level Output

to

tpLH Propagation Delay
Time Low to High
Level Output

to

tpHL Propagation Delay
Time High to Low
Level Output

to

tpHL Propagation Delay
Time High to Low
Level Output

to

"

at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL = 4000
CL=15 pF
CEXT=O pF, REXT=5 kO
Min

CL=15pF
CEXT=1000 pF, REXT=10 kO
Min

Typ

Units

Typ

Max

Max

22

33

ns

19

28

ns

30

40

ns

27

36

ns

30

40

ns

18

27

ns

a

B

a

A

Q
B

Q

tpLH Propagation Delay
Time Low to High
Level Output

Clear
to

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to

tW(OUI) Output
Pulse Width

A or B

Q

a

3.08

to

a

,

6·154

3.42

3.76

I'S

Operating Rules
" 1.

An external resistor (Rx) and external capacitor
(Cx) are required for proper operation. The value of
ex may vary from to any necessary value. For
small time constants high·grade mica, glass, poly·
propylene, polycarbonate, or polystyrene material
capacitors may be used. For large time constants
use tantalum or special aluminum capacitors. If
the timing capacitors have leakages approaching
100 nA or if stray capacitance from either terminal
to ground is greater than 50 pF the timing equa·
tions may not represent the pulse width the device
generates.

For ex < 1000 pF see Figure 3 for Tw vs ex family
curves with Rx as a parameter:

5.

°

2.

3.

t-. -

R-l0K
R=25K

When an electrolytic capacitor is used for ex a
switching diode is often required for standard TTL
one·shots to prevent high inverse leakage current
(Figure 2). However, its use in general is not recom·
mended"with retriggerable operation.

10
TlIF/6539·4

FIGURE 3

The output pulse width (Tw) is defined as follows:
Tw= K Rx ex (1 + 0.7/Rx)

6.

To obtain variable pulse width by remote trimming,
the following circuit is recommended:

PIN (7)

The multiplicative factor K is plotted as a function
of Cx below for design considerations:

Rx

DR(15)~~
ex

100 ~F

TA=25°C
Vee=5.0V

10 ~F

1000

Cm (pF)

where [Rx is in Kilo-ohm)
[ex is in pico Farad)
[Tw is in nano second)
[K",0.34]
4.

100

10

Rremote

PIN(6).]'""

OR (14)

Vee
TLlF/6539·5

1 ~F

8 0.1 ~F

Nole: "Rremote" should be as close to the one·shot as possible.

.. 104 pF

FIGURE4

103 pF

7.

102pF
10 pF

o

.2

.4 .6 .8 1.0 1.-2 1.4 1.6
"K" COEFFICIENT

Tl/F/6539·2

The retriggerable pulse width is calculated as shown
below:
T=Tw+ tpLH = K.x RxX ex +tpLH
The retriggered pulse width is equal to the pulse
width plus a delay time period (Figure 5).

FIGURE 1
RX

0

vee~PIN(7)

r-

INPUT

ex

PIN (6)

OUTPUT

TL/FI6539·3

TliF/6539·6

FIGURE 2

FIGURE 5

6·155

~r-----------------------------------------------------------------------------.

C'II
,..
.Operating Rules
r:!:

::E
Q

~
,..
;1;

8.

(Continued)

Output pulse width versus Vee and Temperatures:
Figure 6 depicts the relationship between pulse
width variation versus operating Vee. Figure 7
depicts pulse width variation versus ambient
temperatures.

::E
Q

10

9.

Under any operating condition Cx and Rx must be
kept as close to the one-shot device pins as possible to minimize stray capacitance, to reduce noise
pick-up, and to reduce I x Rand Ldi/dt voltage
developed along their connecting paths. If the
lead length from Cx to pins (6) and (7) or pins (14)
and (15) is greater than 3 cm, for example, the output pulse width might be quite different from
values predicted from the appropriate equations.
A non-inductive and low capacitive path is
necessary to ensure complete discharge of Cx in
each cycle of Its operation so that the output
pulse width will be accurate.

10.

The CEXT pins of this device are internally connected to the internal ground. For optimum
system performance they should be hard wired to
the system's return ground plane.
• However, It should be noted that although the
74221 series one-shot Is pin-for-pln compatiable with the '123 device, its CexT pin is not
an Internal connection to ground. Hence, if
substitution of an '221 on to an '123 design
layout whose CexT pin Is wired to the ground is
attempted, the '221 device will not function!

11.

Vee and ground wiring should confo,rm to good highfrequency standards and practices so that switch- .
ing transients on the Vee and ground return leads do
not cause interaction between one-shots. A 0.G1 /tF
to 0.10 /tF bypass capacitor (disk ceramic or monolithic type) from Vee to ground is necessary on each
device. Furthermore, the bypass capacitor should
be located as close to the Vee pin as space permits.

REXT-5K
CEXT = 1000 pF
TA 25°C

=

III

:i
~

at

~

-5
-10 L...._.L-_-'-_-'-_--'
4.5
5.5
4
Vee (V)

TLlF16539-7

FIGURE 6
10

'-

r'-.. i'..

REXT-l0K
CEXT= 1000 pF
Vee-5.OV

.........

I"-

-5
-10
-60 -30

0

30

60

"

90 120 150

AMBIENT TEMPERATURE JOC)

TLIF16539·8
• For further detailed device characteristics and output performance
please refer to the NSe one·shot applicatlon.note, AN·366.

FIGURE 7

6-156

r-----------------------------~---------------------------.c

s:

~National

i!
.....

~ Semiconductor

~

-s:c

DM54125/DM74125 Quad TRI·STATE® Buffers

:;:!
.....

General Description

Absolute Maximum Ratings

This device contains four Independent gates each of
which performs a non-Inverting buffer function_ The outputs have the TRI-STATE feature. When enabled, the
outputs exhibit the low impedance characteristics of a
standard TTL output with additional drive capability at
the high Logic level to permit the driving of bus lines
without external pull-up resistors. When disabled, both
the output transistors are turned off presenting a highImpedance state to the bus line. Thus the output will act
neither as a significant load nor as a driver. To minimize
the possibility that two outputs will attempt to take a
common bus to opposite logic levels, the disable time Is
shorter than the enable time of the outputs.

Supply Voltage
Input Voltage
Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

7V
5.5V
- 65·C to 150·C

Dual-In-Line Package
vcc
14

Y4

A4

C4

12

13

C3

11

10

A3

9

Y3

Y=A

8

Input

Output

A

C

Y

L
H

L
L
H

L
H
Hi-Z

X

H = High logic Level
L= Low logic Level
X= Either Low or High Logic Level
Hi-Z= TRI-STATE (Outputs are disabled)

7
C1

A1

Y1

C2

A2

Y2

GND
TL/F/6540·1

DM54125 (J)

DM74125 (N)

6-157

(Note 1)

~

Recommended Operating Conditions
Sym

~ee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Inpuf
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

DM74125

DM54125

Parameter

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

Units
V
V

0.8

0.8

V

i

-2

,

16
-55

125

0

-5.2

mA

16

mA

70

·C·

,

Electrical Characteristics
Sym

Parameter

over recommended operating free air temperature (u'nless otherwise noted)
Conditions

VI

Input Clamp Voltage

Vee = Min, 11= -12 mA

VOH

High Level Output
Voltage·

Vee = Min, 10H = Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee = Min, IOL= Max
VIH= Min, VIL= Max

II

Input Current@Max
Input Voltage

Vee=Max, W=5.5~

.IIH

High Level Input
Current

IlL

Min

Typ
(Note 1)

2.4

3.3

Max
-1.5

0.2

Units
V
V

0.4

V

1

mA

Vee= Max, VI= 2.4V

40

/LA

Low Level Input
Current

Vee = Max, VI = 0.4V

-1.6

mA

IIZL

Off-State Input
Current with Low
Level Input Voltage
Applied

Vee=Max
V I =O.4V

-40

I,A

IOZH

Off-State Output
Current with High
Level Output
Voltage Applied

Vee= Max, Vo= 2.4V
VIH= Min, VIL= Max

40

/LA

IOZL

Off-State Output
Current with Low
Level Output
Voltage Applied

Vee = Max, Vo=0.4V
VIH = Min, VIL = Max

-40

/LA

los

Short Circuit
Output Current

Vee = Max
(Note 2)

mA

Supply Current

Vee= Max (Note 3)

Icc

,

I DM54

-30

-70

I DM74

-28

-70
36

Nole1: Aillypicals are at vee= sv. TA=2S"e.
Nole 2: Not more than one output should be shorted at a time.
Note 3: ICC Is measured with the output control (C) Inputs at 4.5V. the data Inputs grounded. and the outputs open.

6-158

54

mA

Switching Characteristics

at Vee= 5V and TA= 25°C (See Section 1 for Test Waveforms and Output Load)
RL = 40011

Parameter

CL=5 pF

Typ

CL=50 pF

Units

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

10

15

ns

tpHL Propagation Delay Time
High to Low Level Output

12

18

ns

tPZH Output Enable Tim~,
.to High Level Output

12

18

ns

tPZL Output Enable Time
to Low Level Output

16

25

ns

Min

Max

Min

tpHZ Output Disable Time
from High Level Output

5

8

ns

tpLZ Output Disable Time
from Low Level Output

9

14

ns

-,

6·159

~

~ ~National

~ ~ Semiconductor
iij
....
"1:1'

~ DM54126/DM74126 Quad TRI·STATE® Buffers

o

\

General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs a non·inverting buffer function. The out·
puts have the TRI·STATE feature. When enabled, the
outputs exhibit the low Impedance characteristics of a
standard TIL output with additional drive capability at
the high logic hivel to permit the driving of bus lines
without external pull·up resistors. When disabled, both
the output transistors are turned off presenting a high·
impedance state to the bus line. Thus the output will act
neither as a significant load nor as a driver. To minimize
the possibility that two outputs will attempt to take a
common bus to opposite logic levelS, the disable time is
shorter than the enable- time of the outputs.

Supply Voltage
Input Voltage
Storage Temperature Range

Connection Diagram

Function Table

114

C4

A4

13

Y4

12

C3

11

10

7V

5.5V
- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual·ln·Llne Paokage
VCC

Y=A
A3

9

V3

Input

8

Output

A

C

Y

L
H
~

H

L
H

H
L

Hi·Z

H = High Logic Level
L = Low Logic Level
X Either Low or High Logic Level
HI·Z=TRI·STATE (Outputs are disabled)

=

4

1

C1

C2

15
A2

16
Y2 .

\7
GND
TLfFf6541·1

DM54126 (J)

(Note 1)

DM74126 (N)

6·160

Recommended Operating Conditions
Sym
Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IGH
10L
TA

-

DM54126

Parameter

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

Units
V
V

0.8

0.8

High Level Output
Current

-2

-5.2

mA

Low Level Output
Current

16

16

mA

70

·C

Free Air Operating
Temperature

-55

Electrical Characteristics
Sym

DM74126

Min

Parameter

125

0

V

over recommended operating free air temperature (unless otherwise noted)
Conditions

VI

Input Clamp VOltage

Vee= Min, 11= -12 mA

VOH

High Level Output
Voltage

Vee = Min, IOH= Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee = Min, 10L= Max
VIH = Min, VIL = ~ax

II

Input Current@Max
Input Voltage

IIH

Min

Typ
(Note 1)

2.4

3.3

Max
-1.5

V
V

0.4

V

Vee = Max, VI = 5.5V

1

mA

High Level Input
Currerit

Vce=Max, VI=2.4V

40

p.A

IlL

Low Level Input
Current

Vee = Max, VI = 0.4V

-1.6

mA

IIZL

Off·State Input
Current with Low
Level Input Voltage
Applied

Vee=Max
VI =0.4V

-40

p.A

10ZH

Off·State Output
Current with High
Level Output
Voltage Applied

Vee= Max, Vo= 2.4V
VIH = Min, VIL = Max

40

p.A

IOZL

Off·State Output
Current with Low
Level Output
Voltage Applied

Vce= Max, Vo= 0.4V
VIH = Min, VIL = Max

-40

p.A

los

Short Circuit
Output Current

Vce= Max
(Note 2)

mA

Supply Current

Vce = Max (Note 3)

lee

0.2

Units

IDM54

-30

-70

IDM74

-~8

-70
36

Note 1: All typical. are at Vee=5V, TA=25'C.
Nate 2: Not more than one output should be shorted at a time.
Note 3: ICC is measured with both the output control and data inputs grounded, and outputs open.

6·161

62

mA

SWitching Characteristics

at Vee = 5V and TA= 25°C (See Section 1 for Test Waveforms and Output Load)
RL =4000

Parameter

CL=50 pF

C L =5pF

Min

Max

Min

Units

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

10

15

tpHL Propagation Delay Time
High to Low Level Output

12

18

tPZH Output Enable Time
to High Level Output

13

19

ns

tPZL Output Enable Time
to Low Level Output

16

25

ns

Typ

ns
ns
\,

tpHZ Output Disable Time
from High Level Output

10

16

ns

tpLZ Output Disable Time
from Low Level Output

14

20

ns

6-162

~-----------------------------------------------------------------'C

s::
~
....

~National

~ Semiconductor

~
c

s::
~

DM54132/DM74132 Quad 2-lnput NAND Gates with
Schmitt Trigger Inputs

~

General Description

Absolute Maximum Ratings (Note 1)

This device contains four independent gates each hf
which performs the logic NAND function. Each input has
hysteresis which increases the noise imlT)unity and trans·
forms a slowly changing input signal to a fast changing,
jitter free outpiJt.

Supply Voltage
Input Voltage
Storage Temperature Range

7V
S.SV

- 6S'Cto 1S0'C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device cannot be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

..

Dual·ln·Llne Package
~4

I

~
sr

Y4

112

13

AI

Function Table

"

4

3

YI

. AZ

"

ID

Y3

~•
Br

Inputs

T.

YZ

-8

Y

L
L

L
H

H
H

L

H
H
H

H

L

H = High Logic Level
L = Low Logic Level

G!~

TLlF16542·1

DM54132 (J)

Output

A

DM74132(N)

6·163

,

Recommended Operating Conditions
Symbol

Parameter

DM74132

DM54132
Min

Typ

Max

Min

Typ

Max

Units

Vee

Supply Voltage

4.5

5

5.5

4.75

5

5.25

V

VT+

Positive-Going Input
Threshold Voltage (Note 1)

1.5

1.7

2

1.5

1.7

2

V

VT _

Negative-Going Input
Threshold Voltage (Note 1)

0.6

0.9

1.1

0.6

0.9

1.1

V

HYS

Input Hysteresis (Note 1)

(,).4

0.8

0.4

0.8

10H

High Level Output Current

10L

Low Level Output Current

TA

·Free Air Operating
Temperature

V

-0.8

-0.8

mA

16

mA

70

·C

16

-55

125

0

Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Sym

Parameter

Min

Typ
(Note 1)

DM54

2.4

3.4

DM74

2.4

3.4

Conditions

Max
-1.5

Units
V

VI

Input Clamp Voltage

Vee = Min,-II = -12 mA

VOH

High Level Output
Voltage

Vee=Min
IOH= Max
VI =VT_Min

VOL

Low Level Output
Voltage

Vee=Min
10L=Max
VI=VT+Max

IT+

Input Current at
Positive-Going
Threshold

Vee=5V, VI=VT+

-0.43

IT_

Input Current at
Negatlve·Going
Threshold

Vee=5V, VI=VT_

-0.56

II

Input Current@Max
Input Voltage

Vee=Max, VI =5.5V

1

mA

IIH

High Level Input
Current

Vee = Max, VI = 2.4V

40

p.A

IlL

Low Level Input
Current

Vee = Max, VI = 0.4V

-1.2

mA

los

Short Circuit
Output Current

Vec= Max
(Note 3)

mA

ICCH

Supply Current With
Outputs High

Vcc=Max

15

24

mA

ICCL

Supply Current With
Outputs Low

Vcc=Max

26

40

mA

V

0.2

-0.8

0.4

(

mA

mA

DM54

-18

-55

DM74

-18

-55

Note 1: Vec =SV.
Note 2: All typical. are at Vec=SV, TA=2SoC.
Note 3: Not more than one output should be shorted at a time.

6·164

V

Switching Characteristics

at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL =4001l
CL =15 pF

Parameter
Min

Units

,

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

15

22

ns

tpHL Propagation Delay Time
High to Low Level Output

15

22

ns

\

6·165

~ r-----------------------------------------------------------------------~--,
~

t:!: ~National
:iE ~ Semiconductor
Q
~

~
~

DM54141/DM74141 BCD to Decimal Decoders/Drivers

Q

General Description

~

~
:iE

The DM541411 DM7 4141 is a BCD-/o-decimal decoder designed to drive cold-cathode indicator tubes.
Full decoding is provided for all possible input states. For
binary inputs 10 through 15, all the outputs are off. Therefore the DM54141/DM74141, combined with a minimum of
external circuitry, can use these invalid codes in blanking
leading- and I or trailing-edge zeros in a display.
Input clamp diodes are also provided to clamp negativevoltage transitions in order to minimize transmission-line effects.

• Low leakage current 50 p.A @ 55 V
• Low power dissipation 55 mW typical

Absolute Maximum Ratings
Supply Voltage

(Note 1)
7V
5.5V

Input Voltage

- 65·C to 150·C

Storage Temperature Range

• Drive cold-cathode, numeric indicator tubes directly
• Fully decoded inputs

Note 1: The "Absolute Maximum Ra,tlngs" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Features

Dual-In-Line Package
OUTPUTS

OUTPUTS

a
16

1

5

4
14

115

GND

13

112

1

.'

6

7

111

1'0

11

9

L...c

po

r-<

po

1

r

12

-----8

9

OUTPUT~

13

14

15

A
D
---.-...

VCC

INPUTS

I
18

1
17
C

Input

,
3

A

L
L
H
H
L
L
H" H
H H
L L
L L

L
H
L
H
L
H
L
H
L
H

C

L
L
L
L
L
L
L
L
H
H

L
L
L
L
H
H

Output
On'

a
1
2

3
4
6
6
7
8
9

(Over Range)
H
H
H
H

8

2
B
------ OUlPUT
INPUTS

H
H

TL/F/6543·1

54141 (J)

B

D

74141 (N)

L
L
H

H
H
L
L

L
H
L

None
None
None

H
H

H

None

H

L

H

H

H

None
None

H = High Leval, L - Low Level
• AU other outputs are off

6-166

.-----------------------------------------------------------------'0
s:
Recommended Operating Conditions
~

Sym

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

DM54141
Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

-55

V

7

7

rnA

0

70

'c

over recommended operating free air temperature (unless otherwise noted)

Parameter

Min

Conditions
Vee = Min, 11= -12 rnA

High Level Output
Voltage

Vee = Min, IOH=0.5 rnA

IOH

Off·State Reverse
Current for Input
Counts 10·15

Vec= Min
Vo=30V

Off·State Reverse
Current for Input
Counts 0-9

Vcc=Min
Vo=55V

Low Level Output
. Voltage

Vec=Min
IOL= Max
VIL= Max
VIH= Min

II

Input Current@Max
Input Voltage

Vec = Max, VI = 5.5V

IIH

High level Input
Current

Vcc=Max
VI=2.4V

Low Level Input
Current

Vee = Max
VI=0.4V

Supply Current

Vee = Max (Note 2)

Icc

0.8

,

Input Clamp Voltage

IlL

V

"

0.8

125

VOH

VOL

V

2

VI

IOH

Units

(

Electrical Characteristics
Sym

DM74141

Typ
(Note 1)

Max

Units
V

-1.5

V

60

TA =-55'C

5

TA = 70'C

15

/LA

50

/LA

"2.5

TA= -55 to 70'C

V

3

TA = 125'C

1

rnA

A Input

40

/LA

B, C, 0 Inputs

80

A Input

-1.6

B, C, 0 Inputs

-3.2
11

Note': Ali typlcals are at Vec=5V, TA=25"C.
Note 2: ICC Is measured with ali Inputs grounded and ali outputs open.

6-167

25

rnA

rnA

....
....-'="

-s:
o

....~
-'....
="

-

-.-------------------------------------------------------------~
~

~

Logic Diagram

:e
c

--~

~
II)

:e

54141174141

c

D~(4L)JL________~~~--~~--_t~

TLlF16543·2

6-168

r---------------------------------------------------------------,0
s:
C11
~National

01:00
.....

~ Semiconductor

-s:o
01:00

C11

~

DM54145/DM74145 BCD to Decimal Decoders/Drivers

01:00

C11

General Description

Features

These BCD-to-decimal decoders/drivers consist of eight
inverters and ten, four-input NAND gates. The inverters are
,connected in pairs to make BCD input data available for decoding by the NAND gates.. Full decoding of BCD input logic
ensures that all outputs remain off for all invalid (10-15) binary input conditions. These decoders feature high-performance, NPN output transistors designed for use as
indicator / relay drivers, or as open-collector logic-circuit
drivers. The high-breakdown output transistors are compatible for interfacing with most MOS integrated circuits.

• Full decoding of input logic
• 80 mA sink-current capability
• All outputs are off for invalid BCD input conditions

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

7V
5.5V
- 65·Cto 150·C

NOle 1: The "Absolute Maximum Ratings" are those vatues beyond
which the safety of the device can not be guaranteed. The device should
not be operated al these limits. The parametric values defined In the
"Electrical Characteristics" ,table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.
'

Connection Diagram

Dual-In-Line Package
OUTPUTS

INPUTS

Vee

1,6

c

B

A

15

14

o

9

12

13

7

8

11

r-<

1

o

9

10

0-

3

2
2

5

4
3

4

7

6

5

6

18
GND

OUTPUTS
TL/F/6544·1

54145 (J)

74145 eN)

6-169

Recommended Operating Conditions

Vee

DM54145

Parameter

Sym
:

Supply Voltage

DM74145

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units
V
V

VIH

High Level Input
Voltage'

VIL

Low Level Input
Voltage

0.8

0.8

V

VOH

High Level O~tput
Voltage

15

15

V

IOL

Low Level Output
Current

20

20

mA

TA

Free Air Operating
Temperature

70

·C

2

2

'-55

125

0

,

Electrical Characteristics
Sym

Parameter

over recommended operating free air temperature (unless otherwise noted)
Typ
(Note 1)

Min

Conditions

Max

Units

VI

Input Clamp Voltage

Vee=Mln, 11= -12 rnA

-1.5

V

ICEX

High Level Output
Current

Vee = Min, VoH=Max
VIL = Max, V IH = Min

250

p.A

VOL

Low Level Output
Voltage

Vee = Min, IOL = Max
VIH = Min VIL = Max

0.4

V

0.5

IOL=80 rnA
Vee = Min

0.9

II

Input Current@Max
Input Voltage

Vec=Max, VI=5.5V

1

rnA

IIH

High Level Input
Current

Vcc = Max, VI = 2.4V

40

p.A

IlL

Low Level Input
Current

Vee = Max, VI = 0.4V

-1.6

rnA

Icc

Supply Current

Vec=Max
(Note 2)

rnA

Switching Characteristics
Parameter

I
I

DM54

43

62

DM74

43

70

at Vee = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
CL =15 pF
RL = 1000

Conditions

Max

Units

t pLH Propagation Delay Time
Low to High Level Output

30

ns

tpHL Propagation Delay Time
High to Low Level Output

30

ns

Min

Nolel: All typlcals are at Vee=SV. TA=2S"e.
Note 2: ICC Is measured with all outputs open and all Inputs grounded.

6-170

Typ

Function Table
Inputs

No.

Outputs

D C B A 0

1

2

7

4

5

0
1
2
3
4

L'L
L L
L L
L L
L H

L
L
H
H
L

L
H
L
H
L

L H H H
H L H H
H H L H
H H H L
H H H H

H
H
H
H
L

H H H H H
H H H H H
H H H H H
H H H H H
H H H H H

5
6
7
8
9

L
L
L
H
H

H
H
H
L
L

L
H
H
L
L

H
L
H
L
H

H H
H H
H H
H.H
H H

H L
H H
H H
H H
H H

H
H
H
H
H
H

L
L
H
H
H
H

H
H
L
L
H
H

L
H
L
H
L
H

H H H H H
H H H H H
H H H H H
H H H H H
H H H H H
H H H H H

c

::J

~
~

H
H
H
H
H

3

H
H
H
H
H

6

H
L
H
H
H

8

H H
H H
L H
H L
H H

H H H
H H H
H H H
H H H
H H H
H H H

9

H
H
H
H
L

H H
H H
H H
H H
H H
H H

H • High Level (Off), L - Law Level (On)

Logic Diagram

TL/F/6544·2

6·171

~

'E:

~ National

~ ~ Semiconductor

i

:; DM54147/DM74147, DM54148/DM74148 Priority Encoders
II)

:E
Q

• Typical data delay 10 ns
• Typical power dissipation 225 mW
DM54148,I;)M74148
• Encodes 8 data lines to 3-line binary (octal)
• Applications include:
N:bit encoding
Code converters and generators'

General Description

~
,..

~

:E
Q

These TTL encoders feature priority decoding of the input
data to ensure that only the highest-order data line is encoded. The DM54147 and DM74147 encode nine data \jnes
to four-line (8·4-2-1) BCD. The implied decimal zero condition requires no input condition as zero is encodE\d when all
nine data lines are at a high logic level. All inputs sre
buffered to represent one normalized Series 54/74 load.
The DM54148 and DM74148 encode eight data lines to
three-line (4-2-1) binary (octal). Cascading circuitry (enable input Eland enable output EO) has been provided to
allow octal expansion without the need for external circuitry. For all types, data inputs and outputs are active at the
low logic level.

• Typical data delay 10 ns
• Typical power dissipation 190 mW

Absolute Maximum Ratings

(Note 1)

7V
5.5V
-65"Cto150"C

Features

Supply.v0ltage
Input Voltage
Storage Temperature Range

DM54147, DM74147
• Encodes 10-line decimal to 4-lIne BCD
• Applications include:
Keyboard encoding
Range selection

Nole 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
. maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagrams
Dual·ln·Llne Package

Dual-ln·Line Package

Vee

f16

Ne

115

OUTPUT
D

14

,

INPUTS

3
13

12

A

9
11

10

INPUTS
,------'.'----....."

OUTPUTS

OUTPUT

1

2

Vee

9

f16

EO

15

GS

14

3

o

2

13

12

11

OUTPUT

AO

10

9

-0

2
4

5

3
6
INPUTS

4

7

5

8

6
e

7

,

B

la

2

GND

4

OUTPUTS

5

4

3

6
INPUTS

7

5
EI,

6
A2

TUF/6545-2

54148 (J) 74148 (J,N)

6·172

18
GND

OUTPUTS

TL/F/6545·1

54147 (J) 74147 (J,N)

7
Al

Recommended Operating Conditions
DM74147

DM54147
Sym

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units
V
V

2

V

0.8

0.8

High Level Output
Current

-0.8

-0.8

mA

IOL

Low Level Output
Current

16

16

mA

TA

Free Air Operating
Temperature

70

·C

-55

125

0

'147 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Sym

Parameter

Conditions

Min

Typ
(Note 1)

Max
-1.5

Units

VI

Input Clamp Voltage

Vee= Min, 11= -12 mA

V OH

High Level Output
Voltage

Vee= Min, 10H= Max
VIL = Max, VIH;= Min

VOL

Low Level Output
Voltage

Vee= Min, IOL= Max
VIH = Min, VIL = Max

0.4

V

II

Input Current@Max
Input Voltage

Vee=Max, VI=5.5V

1

mA

IIH

High Level Input
Current

Vee= Max, VI = 2.4V

40

p.A

IlL

Low Level Input
Current

Vee= Max, VI = O.4V

-1.6

mA

los

Short Circuit
Output Current

Voe=Max
(Note 2)

mA

lee1

Supply Current

Vee= Max
(Note 3)

50

70

mA

lee2

Supply Current

Vee= Max
(Note 4)

42

62

mA

2.4

L DM54

-35

-' 85

DM74

-35

-85

I

Nole 1: All typlcals are at Vee = 5V. TA = 25"e.
Note 2: Not more than one output should be shorted at a time.

Note 3: ICC1 is measured with input 7 grounded, other inputs and outputs open.
NOle 4: lee2 is measured wilh all inpuls and all outpulS open.

.
"
6·173

V
V

-

'147 swiiching Characteristics
at Vee = 5V and TA= 2S"C (See Section 1 for Test Waveforms and Output Load)
From
(Input)
To
(Output)

Parameter

~

tpLH Propagation Delay
Time Low to. High
Level Output

o thru 9

tpHL Propagation Delay
Time High to Low
Level Output

o thru 9

tpLH Propagation Delay
Time Low to High
Level Output

o thru 9

tpHL Propagation Delay.
Time High to Low
Level Output

othru 9

to
Output

RL=4000
C L =15pF

Waveform
Min
In-Phase
Output

Units

Typ

Max

9

14

ns

7

11

ns

13

19

ns

12

19

ns

to
Output
to
Output

Out-of-Phase
Output

to
A,B,C,D

,

c

r

I

6-174

Recommended Operating Conditions
DM74148

DM54148
Sym

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units
V
V

2

2

-

V

0.8

0.8

-0.8

-0.8

mA

16

16

mA

70

·C

125

-55

0

'148 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Sym

Parameter

Conditions

Min

Typ
(Note 1)

Max
-1.5

Units
V

VI

Input Clamp Voltage

Vee= Min, 11= -12 mA

VOH

High Level Output
Voltage

Vee = Min, 10H= Max
VIL= Max, VIH= Min

VOL

Low Level Output
Voltage

Vee = Min, 10L= Max
VIH = Min, VIL = Max

0.4

V

II

Input Current@Max
Input Voltage

Vee= Max, VI =5.5V

1

m~

IIH

High Level Input
Current

Vee= Max
VI=2.4V

o Input

40

/LA

Others

80

Low Level Input
Current

Vee = Max
VI=0.4V

IlL

los

Short Circuit
Output Current

.

Vce=Max
(Note 2)

V

2.4

o Input

-1.6

Others

-3.2

DM54

-35

-85

DM74

-35

-85

mA

mA

leef

Supply Current

Vcc=Max
(Note 3)

40

60

mA

lee2

Supply Current

Vcc=Max
(Note 4)

35

55

mA

Note I:
Nota 2:
Nota 3:
Nole 4:

Alltyplcals are at VCC=5V. TA=2S'C.
Not more than one output should be shorted at a lime.
ICCI Is measured with inputs EI and 7 grounded, other Inputs and outputs opan.
ICC2 is measured with all inputs and all outputs open.

6-175

•

'148 Switching Characteristics
at Vee = 5V and TA= 25°C (See Section 1 for Test Waveforms and Output Load)

Parameter

From
(Input)
To
(Output)

tpLH Propagation Delay
Time Low to High
Level Output

o thru 9

tpHL Propagatiot1 Delay
Time High to Low
Level Output

o thru 9'.

tpLH Propagation Delay
Time Low to High
Level Output

othru 9

tpHL Propagation Delay
Time High to Low
Level Output.

o thru 9

tpLH Propagation Delay
Time Low to High
Level Output

o thru 7

tpHL Propagation Delay
Time High to Low
Level Output

o thru 7

tpLH Propagation Delay
Time Low to High
Level Output

o thru 7

tpHL Prop·agation Delay
Time High to Low Level Output

o thru 7

tpLH Propagation Delay
Time Low to High
Level Output

E1
to
AO, 1,2

tpHL Propagation Delay
Time High to Low
Level Output

E1
to
AO,1,2

tpLH Propagation Delay
Time Low to High
Level Output

E1
to
GS

tpHL Propagation Delay
Time High to Low
Level Output

E1
to
GS

tpLH Propagation Delay
Time Low to High
Level Output

E1
to
EO

tpHL Propagation Delay
Time High to Low
Level Output

E1
to
EO

to
AO,1,2

RL=4001l
CL=15 pF

Waveform
Min
In·Phase
Output

Units

Typ

Max

10

15

ns

9

, 14

ns

13

19

ns

12

19

ns

6

10

ns

14

25

ns

18

30

ns

14

25

ns

10

15

ns

10

15

ns

8

12

ns

10

15

ns

10

15'

ns

17

30

ns

to
AO, 1,2
to
AO,1,2

Out·of·Phase
Output

to
AO,1,2
to
. EO
to
EO
to
GS

Out·of·Phase
Output

,
In·Phase
Output

to
GS
In·Phase
Output

In·Phase
Output

In·Phase
Output

)

6·176

Function Tables

54147174147

,

Inputs

Outputs

1

2

3

4

5

6

7

8

9

D

C

B

A

H
X
X
X
X
X
X
X
X
L

H
X
X
X
X
X
X
X
L
H

H
X
X
X
X
X
X
L
H
H

H
X
X
X
X
X
L
H
H
H

H
X
X
X
X
L
H
H
H
H

H
X
X
X
L
H
H
H
H
H

H
X
X
L
H
H
H
H
H
H

H
X
L
H
H
H
H
H
H
H

H
L
H
H
H
H
H
H
H
H

H
L
L
H
H
H
H
H
H
H

H H
H H
H ,H
L
L
L
L
L H
L H
H L
H L
H H

H
L
H
L
H
L
H
L
H
L

54148174148
Outputs

Inputs

E1

0

1

2

3

4

5

6

7

A2 A1 AO GS EO

H
L
L
L
L
L
L
L
L
L

X
H
X
X
X
X
X
X
X
L

X
H
X
X
X
X
X
X
L
H

X
H
X
X
X
X
X
L
H
H

X
H
X
X
X
X
L
H
H
H

X
X
H
H
X
X
X
X
X
L
L
H
H
H
H ,H
H
H
H
H

X
H
X
L
H
H
H
H
H
H

X
H
L
H
H
H
H
H
H
H

H
H
L
L
L
L
H
H
H
H

H ::: High Logic Level. l ... Low Logic level, X ::;: Don't care

6-177 .

H
H
L
L
H
H
L
L
H
H

H
H
L
H
L
H
L
H
L
H

H
H
L
L
L
L
L
L
L
L

H
L
H
H
H
H
H
H
H
H

~

~

Logic Diagrams

:E
Q

i....

;1;

:E

147

148

Q

tir

(15) EO

;

....

(14)G5

t-----l-F

:E

Q

~
....

;1;

:E

Q

EI (5)

TlIFI6545-3

TLlF/6545-4

6·178

r----------------------------------------------------------.c

i:
~
.....

~National

~ Semiconductor

e
c
i:

~

DM54150/DM74150, DM54151A/DM74151A
Data Selectors/Multiplexers

~
c

i:

~

General Description

U'I

These data selectors/multiplexers contain full on-chip
decoding to select the desired data source_ The 150
selects one-of-slxteen data sources; the 151 A selects oneof-eIght data sources. The 150 and 151A have a strobe Input which must be at a low logic level to enable these
devices. A high level at the strobe forces the W output high
and the Y output (as applicable) low.
The 151A features complementary Wand Y outputs,
whereas the 150 has an Inverted (IN) output only.
The 151A Incorporates address buffers which have symmetrical propagation delay times through the complementary paths. This reduces the possibilitY of transients occurring at the output(s) due to changes made at the select
Inputs, even when the 151A outputs are enabled (I.e.,
strobe low).

Features

• Permits multiplexing from N lines to one line
• Also for use as Boolean function generator
• Typical average propagation delay time, data input to
Woutput
150 11 ns
151A 9 ns
• Typical power dissipation
150 200 mW
151A 135mW

Absolute Maximum Ratings
Supply Voltage '
Input Voltage
Storage Temperature Range

(Note 1)

7V
5.5V
- 65'C to 150'C

Note 1: The '"Absolute Maximum Ratings'" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. Theparametric values defined In the
'"Electrical Characteristics'" table are not guaranteed at the absolute
maximum ratings. The '"Recommended Operating Conditions'" table will
define the conditions for actual device operation.

• 150 selects one-ol-sixteen data lines
• 151A selects one-ol-eight data lines
• Perlorms parallel-to-serial conversion

Connection Diagrams
Dual-In-Line Package
DATA INPUTS

Dual-In-Line Package
DATA INPUTS

DATA SELECT

~----------------~, ~

Vee EO

124

23

E9 EtO Ell E12 Et3 E14 E15

22

21

20

19

',8

17

16

04

ABC

15

14

13

15

05
14

08
13

DATAsaECT

07

A

B
11

12

C

-

r-

7

8

9

10

DATA INPUTS

I-

11~112
03

,'-E7__E_6__
E_5__
E4~E-3--E-2__
El__
EO
__~TROBEO~T ~T~NO
SELECT

'02

01

4

6

00

------

DATA INPUTS
TLlFI6546·1

54151A (J)

541501J) 74150 IN)

6-179

9

10

W

7

J8

STROBE GNO

OUTPUTS

74151A (N)

TLIF16546-2

.....
~
c

i:
~
.....
U'I

.....

l>

Recommended Operating Conditions
Sym

Parameter

Vee.

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

DM741S0

DMS4150
Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

Units
V
V

0.8

0.8

. High Level Output
Current

-0.8

-0.8

mA

IOL

Low Level Output
Current

16

16

mA

TA

Free Air Operating
Temperature

70

·C

-55

125

0

V

'150' Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Parameter

'Sym~

Conditions

Min

Typ
(Note 1)

Max

VI

Input Clamp Voltage

Vee = Min, 11= - 12 niA

VOH

High Level Output
Voltage

Vec = Min, IOH = Max
VIL= Max, VIH= Min

VOL

Low Level Output
Voltage

Vee = Min, IOL= Max
VIH = Min, VIL = Max

0.4

V

II

Input Current@ Max
Input Voltage

Vcc = Max, VI = 5.5V

1

mA

IIH

High Level Input
Current

Vee = Max, VI = 2.4V

40

p.A

IlL

Low Level Input
Current

Vce= Max, VI = 0.4V

-1.6

mA

los

Short Circuit
Output Current

Vee= Max
(Note 2)

mA

Supply Current

Vee = Max (Note 3)

Icc

I
I

-1.5

Units

DM54

-20

-55

DM74

-18

-55
40

Note t: All typicals are at Vee = 5V, TA = 25'e.
Note 2: Not more than one output should be shorted at a time.
Note 3: ICC Is measured with the strobe and data select inputs at 4.5V, all other inputs and outputs open .

.
-

""

6·180

V
V

2.4

68

.mA

c
3:

'150 Switching Characteristics

C1I
0Iloo

....C1I

at Vee = 5V and TA= 25°C (See Section 1 for Test Waveforms and Output Load)

Parameter

From
(Input)
To
(Output)

RL=400n

C L =15pF
Min

Units

Typ

Max
35

tpLH Propagation Delay
Time Low to High
Level Output

Select
to
W

21

tpHL Propagation Delay
Time High to Low
Level Output

Select
to
W

22

tpLH Propagation Delay
Time Low to High
Level Output

Strobe
to
W

15

tpHL Propagation Delay
Time High to Low
Level Output

Strobe
to
W

21

tpLH Propagation Delay
Time Low to High
Level Output

EO-E15
to
W

13

20

ns

tpHL Propagation Delay
Time High to Low
Level Output

EO-E15
to
W

8.5

14

ns

33

ns

ns

o
c
3:
~

....

~

c
3:
~
....

....

C1I

24

30

ns

ns

;e
c

3:
....~
C1I
....

:r>

6-181

Recommended Operating Conditions
DM54151A
Sym

Parameter

Vee

Supply Voltage

V IH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

DM74151A

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units
V
V

2
0.8

0.8

High Level Output
Current

-0.8

-0.8

mA

10L

Low Level Output
Current .

16

16

mA

TA

Free Air Operating
Temperature

70

·C

-55

125

0

V

'151A Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)

Sym'

Parameter

Conditions

Min

Typ
(Note 1)

Max
-1.5

Units
V

VI

Input Clamp Voltage

Vee= Min, 11= -12 mA

V OH

High Level Output
Voltage

Vee = Min, 10H= Max
VIL= Max, VIH'= Min

VOL

Low Level Output
Voltage

Vee = Min, 10L= Max
VIH= Min, VIL= Max

0.4

V

II

Input Current@ Max
Input Voltage

Vee = Max, VI=5.5V

1

mA

IIH

High Level Input
Current

Vee = Max, Vi = 2.4V

40

p.A

IlL

Low Level Input
Current

Vee = Max, VI=0.4V

-1.6

mA

los

Short Circuit
Output Current

Vee = Max
(Note 2)

mA

Supply Current

Vee=Max (Note 3)

lee

I

I

2.4

V

DM54

-20

-55

DM74

-18

-55
48

27

Nolel: Alllyp,lcals are at Vee=5V, TA=25'e.
Nole 2: Not more than one output should be shorted at a time.
Nole 3: lee is measured with the strobe and data select Inputs at 4.5V, all other Inputs and outpuls open.

\

,
6·182

mA

'151A Switching Characteristics
at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
From
(Input)
To
(Output)

Parameter

RL=4000
CL=15 pF
Mil:'

Units

Typ

Max

tpLH Propagation Delay
Time Low to High
Level Output

Select
(4 Levels)
to Y

23

38

ns

tpHL Propagation Delay
Time High to Low
Level Output

Select
(4 Levels)
to Y

23

30

ns

tpLH Propagation Delay
Time Low to High
Level Output

Select
(3 Levels)
toW

16

26

ns

tpHL Propagation Delay
Time High to Low
Level Output

Select
(3 Levels)
toW

16

30

ns

tpLH Propagation Delay
Time Low to High
Level Output

Strobe
to
Y

25

33

ns

tpHL Propagation Delay
Time High to Low
Level Output

Strobe
to
Y

19

30

ns

tpLH Propagation Delay
'Time Low to High
Level Output

Strobe
to
W

11

21

ns

tpHL Propagation Delay
Time High to Low
Level Output

Strobe
to
W

17

25

ns

tpLH Propagation Delay
Time Low to High
Level Output

00·07
to
Y

17

24

ns

tpHL Propagation Delay
Time High to Low
Level Output

00·07
to
Y

18

24

ns

tpLH Propagation Delay
Time Low to High
Level Output

00·07
to
W

10

14

ns

00·07
to
W

8

14

ns

tpHL Propagation Delay
Time High to Low
Level Output

"

8-183

«
~
,..

Function Tables

~

:IE

54150174150

Q

0-

(12)
Y4

-

STROBE (15)
TLlF/6550·2

6·201

II?A National
~ Semiconductor
DM54160A/DM74160A, DM54161A/DM74161A,
DM54162A/DM74162A, DM54163A/DM74163A
Synchronous 4·Bit Counters
General Description
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed countIng designs. The 160A and 162A are decade counters and
the 161A and 163A are 4-bit binary counters. The carry output is decoded by means of a NOR gate, thus preventing
spikes during the normal counting mode of operation.
Synchronous operation is provided by having all flip-flops
clocked simultaneously so that the outputs change coincident with each other when so instructed by the countenable inputs and internal gating. This mode of operation
eliminates the output counting spikes which are normally
associated with asynchronous (ripple clock) counters. A
buffered clock Input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform.
These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables
the counter and causes the outputs to agree with the
setup data after the next clock pulse, regardless of the
U; levels of the enable input. Low-to-high transitions at the
,.. load input of the 160A through 163A are perfectly accept.~ able, regardless of the logic levels on the clock or enable
inputs. The clear function for the 160A and 161A is asynC chronous; and a low level at the clear input sets all four of
,<( the flip-flop outputs low, regardless of the levels of clock,
o load, or enable inputs. The clear function for the 162A and
~ 163A is synchronous; and a low level at the clear input'sets
all four of the flip-flop outpuls low after the next clock
pulse, regardless of the levels of the enable inputs. This
C synchronous clear allows the count length to be modified
easily, as decoding the maximum count desired can be ac_
~ complished with one external NAND gate. The gate output
_
is connected to the clear input to synchronously clear the
~ counter to all low outputs. Low-to-high transitions at the
I.t) clear input of the 162A and 163A are also permissible,
regardless of the logic levels on the clock, enable, or load
C inputs.

::E

t:!:

::E

::E

Connection Diagram

The carry look-ahead circuitry provides for cascading
counters for n-bit s}!nchronous applications without additional gating. Instrumental in accomplishing this function
are two count-enable inputs and a ripple carry output.
Both count-enable inputs (P and 1) must be high to count,
and input T is fed forward to enable the ripple carry output.
The ripple carry output thus enabled will produce a highlevel output pulse with a duration approximately equal to
the high-level portion of the Q A output. This high-level
overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-Iow-Ievel transitions at
the enable PorT inputs of the 160A through 163A mayoccur, regardless of the logic level on the clock.

Features
•
•
•
•

II!

Synchronously programmable
Internal look-ahead for fast counting
Carry output for n-bil'cascading
Synchronous counting
Load control line

• Diode-clamped inputs
• Typical propagation time, clock to Q output 14 ns
• TyJlical clock frequency 35 MHz
• Typical power dissipation 315 mW

Absolute Maximum Ratings
Supply Voltage,
Input Voltage
Storage Temperature Range

(Note 1)

7V
5.5V
- 65·C to 150·C

Not. 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated, at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define' the conditions for actual device operation.

Dual-In-Llne Package
RIPPLE
OUTPUTS
CARRY ,...--~-_...."ENABLE
VCC OUTPUT OA
OB
~D
T
LOAD

r16

115

f14

1~3

0Tc

12

I I I

111 110

9

I I
54160A (J)
54161A(J)
54162A(J)
54163A(J)

I I I I I

2 P 14 15 1'6 .1.7 18
CLEAR CLOCK

~

~

~

DATA iNPUTS

6-202

D ENABLE
P

G~D

TLIF16551·1

74160A(N)
74161A(N)
74162A(N)
74163A(N)

;

Recommended Operating Conditions
DM54160A thru 163A

DM74160A thru 163A

Parameter

Sym
Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

Units
V
V

0.8

0.8

High Level Output
Current

-0.8

-0.8

mA

IOL

Low Level Output
Current

16

16

mA

fCLK

Clock Frequency

25

MHz

tw

Pulse Width

tsu

Setup Time

tH

Hold Time

TA

Free Air Operating
Temperature

0

0

25

25

Clear

20

20

Data

20

20

Enable P

34

34

Load

25

25

Clear (Note 5)

20

20

0

Parameter

ns

ns

0

-55

Electrical Characteristics
Sym

25

Clock

125

ns

0

70

Conditions

Min

Typ
(Note 1)

2.4

3.4

Max
-1.5

Input Clamp Voltage

VCC= Min, 11= -12 mA

VOH

High Level Output
Voltage

VCC= Min, 10H= Max
VIL = Max, VIH= Min

VOL

Low Level Output
Voltage

VCC= Min, 10L= Max
VIH = Min, VIL= Max

II

Input Current@Max
'Input Voltage

Vcc=Max, VI =5.5V

IIH

High Level Input
Current

Vcc= Max
VI = 2.4V

Low Level Input
Current

Vcc= Max
V I =0.4V

Short Circuit
Output Current

Vcc= Max
(Note 2)

DM54

-20

-57

DM74

-20

-57

Supply Current With
Outputs High

Vcc= Max
(Note 3)

DM54

59

85

DM74

59

94

Supply Current With
Outputs Low

Vcc= Max
(Note 4)

DM54

63

91

DM74

63

101

ICCL

Notal:
Nota 2:
Nota 3:
Note 4:
Note 5:

V

0.4

V

1

mA

Enable T

80

/LA

Clock

80

0.2

40

Enable T

-3.2

Clock

-3.2

All typlcals are at VCC=SV, TA=2S'C.
Not more than one output should be shorted at a time.
ICCH Is measured with the LOAD high, then again with the LOAD low, with all inputs high and all outputs open.
ICCL is measured wilh the CLOCK high, then again with the CLOCK Input low, with all Inputs low and all outputs open.
Applies to '162A and '163A which have synchronous clear inputs.
6-203

mA

-1.6

Others

ICCH

Units

V

Others

los

'C

over recommended operating free air temperature (unless otherwise noted)

VI

IlL

V

mA

mA

mA

Switching Characteristics
Parameter

at Vee = 5V and TA = 25°C (See Section 1 fo~ Test Waveforms and Output load)
From
(Input)
To
(Output)

RL =400!l
C L =15 pF

fMAX Maximum Clock
Frequency

Min

Typ

25

35

Units
Max

MHz

tpLH Propagation Delay
Time low to High
level Output

Clock to
Ripple
Carry

18

27

ns

tpHL Propagation Delay
Time High to low
level Output

Clock to
Ripple
Carry

16

24

ns

tpLH Propagation Delay
Time low to High
level Output

Clock
(load High)
toO

14

20

ns

tpHL Propagation Delay
Time High to low
level Output

Clock
(load High)
toO

22

32

ns

tpLH Propagation Delay
Time low to High
level Output

Clock
(load low)
toO

14

21

ns

tpHL Propagation Delay
Time High to low
level Output

Clock
(load low)
to a

22

32

ns

tpLH Propagation Delay
Time low to High
level Output

Enable T
to Ripple
Carry

11

16

ns

tpHL Propagation Delay
Time High to low
level Output

Enable T
to Ripple
Carry

12

16

ns

tpHL Propagation Delay
Time High to low
level Output

Clear!(Note 1)
to

24

36

ns

.'

a

Note 1: Propagation delay for clearing is measured from the clear Input for the

160A and 161A or from

6·204

the clock Input transition for the

162A and 163A,

,----------------------------------------------------------------------,0
:s:
Logic Diagrams
01
160A
~
.....
en
o

-:s:
l>

o
......

121

CLOCK--C>O--~======+tlj:~;::==llr1
III
DATAA---_--'

~
.....

en
o

111
CLEAR

}>

o

:s:
01

141

B'--------j--j--t++t-r).....

OATA

~
.....

en
.....

l>

o

:s:
......
~
.....

151

DATAC-------H-t-i+t+-t-i-l'

en
.....

}>

o

:s:

01
~

.....

161

DATA

en
I\)

O-------t+t-t-t-H-H-jr'1....

~

o

:s:
......

161A is similar; however,

the clear is asynchronous as shown
for 160A decade counters.

TLlF/6551-2

~
.....

en
I\)

}>

163A

o

:s:
01
~

.....

121

Cl(]CK=----{::>O---~==;:::~I~~:;===1T1

en

~

IJI

DATAA-----~

o

:s:
......

~

.....

en

~

151

DATAC-------ti::j=j;=j=t:j=j;:j::::::[J"L

161

DATA

o-------tt::J:1f=1:tf=t1=1:=fj-

162A is similar; however,
the clear is synchronous as shown
for the 163 binary counters.

TLlF16551-3

6-205

Timing Diagrams
160A, 162A SYNCHRONOUS OECADE COUNTERS
TYPICAL CLEAR, PRESET, COUNT AND INHIBIT SEQUENCES
CLEAR
160A
CLEAR
162A

LOAD
A

[

r----+-...,-------------.-----+--,-------------_____________ _

I~:"~ : _r--+---.r==;;~;==;;=~=~
_+---1.
ClOCK---+'
1BOA

CLOCK
162A

ENABlEP

---+-joI

Sequence:
(11 Clear outputs to zero
(21 Preset to BCD seven·
(3) Count to eight, nine, zero, one, two, and three
(4) Inhibit

-I--I.J

ENABLET _ _ _

---COUNT

---INHIBIT----

CLEAR PRESET

TLlF/6551·4

161A, 163A SYNCHRONOUS BINARY COUNTERS
TYPICAL CLEAR, PRESET, COUNT AND INHIBIT SEQUENCES
CLEAR
ISlA
CLEAR

IS3A
LOAD

r- -

-

-

-

-

-

-

-

-

-

---

INPUTS :==:=:r==============
DC '--+--'L==============
DATA [

.-----f--~--------------

Sequence:
(1) Clear outputs to zero
(2) Preset to binary twelve
(3) Count to thirteen, fourteen, fifteen, zero, one, and two
(41 Inhibit

CLOCK---+,
IliA
CLOCK
ISJA

-I--Ifl

ENABLEP _ _ _

-I--Ifi

ENABlET _ _ _

RIPPLEOC:T~~~ ---+-+':12,.-f:,1l;-"'14-~15
---·COUNT--- ---INHIBIT---CLEAR PRESET

TLlF/6551-5

6-206

Parameter Measurement Information
SWITCHING TIME WAVEFORMS

~

CLOCK
INPUT

OV
"LH
(MEASURE AT ",.,1
OUTPUT
D.

"HL
(MEASURE AT tN+2)

r--~

V""
VOL
VOH

OUTPUT
DB

OUTPUT

Ile

OUTPUT
DD

VOL
VOH
VOL
VOH
VOL

V
RIPPLE OH
CARRY
OUTPUT VOL
TL/F/6551-6

Nota A: The input pulses are supplied by generators having the following characteristics: PRR ::::. 1 MHz, duty cycle::::, SO%, ZOUT .. son. For
160A through 163A, tr < 10 ns, tf < 10 ns. Vary PRR to measure fMAX.
Not. B: Outputs Qo end cerry are t;.tedattn+l0 for 160A, 162Aand at tn+16 for 161A, 163A where tn is the bit time when"all outputs are low.
Note C: For 160A through 163A, VREF = I.SV.

SWITCHING TIME WAVEFORMS
CLOCK INPUT 3.0V
IUOA
161A OV
3.0V
CLEAR
INPUT
OV
3.0V
LOAD
INPUT
OV
3.0V
DATA INPUTS
A, B. C, AND D
OV
o OUTPUTS VOH
161A
AND Do OUTPUTS
160A VOL
VOH
Do AND Ile OUTPUTS
16DA
VOL
3.0V
ENABLE P OR
ENABLE T
OV
VOH
CARRY

a.

VOL:::-F;==~~~~-----1r--------'

CLOCK INPUT 3.0V

162A
163A

o DUn;~~
a. AND DD DUT~~r:
Oa AND Ilc OUTPUTS

VOH

---------t""


VOL

-----::I=+~------....,..,i:-"I

VOH

--------...;;.:~I

162A
VOL.

TL/F/6551.7

Note A: The input pulses are supplied by generators having the following characteristics: PRR < 1 MHz, duty cycle::::, SO%, ZOUT" 50n. For
160A through 163A, tr::::' 10 ns, tf 5. 10 ns. Vary PRR to measure fMAX.
Note B: Enable P and enable T setup times are measured at tn+O'
Not.C: For 160Athrough 163A, VREF = 1.SV.

6-207

~

~ ~National
::E
c ~ Semiconductor
~
,..
DM54164/DM74164 8·Bit Serialln/Paraliel
o:t'
::E Out Shift Registers
II)

c

General Description

Features

These B-bit shift registers feature gated serial inputs and
an asynchronous clear_ A low logic level at either input inhibits entry of the new data. and resets the first flip-flop to
the low level at the next clock pulse. thus providing complete control over incoming data_ A high logic level on either
input enables the other input. which will then determine the
state of the first flip-flop. Data at the serial inputs may be
changed while the clock is high or low. but only information
meeting the setup and hold time requirements will be
entered. Clocking occurs on the low-to-high level transition of the clock input. All inputs are diode·clamped to
minimize transmission-line effects.

•
•
•
•
•

Gated (enable I disable) serial inputs
Fully buffered clock and serial inputs
Asynchronous clear
Typical clock frequency 36 MHz
Typical power dissipation 185 mW

Absolute Maximum Ratings

(Note 1)

7V
5.5V
-65·Ct0150·C

Supply Voltage
Input Voltage
Storage Temperature Range

Nola 1: The "Absolute Maximum Ratings" are those values beyond
which the safety· of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual-In-Line Package
OUTPUTS

Inputs
QE

CLEAR CLOCK

10

-

9

Outputs

Clear

Clock

A

B

QA

QB

QH

L
H
H
H
H

X
L

X
X
H
L
X

X
X
H
X
L

L
aAO
H
L
L

L
aBO
QAn
aAn
aAn

L
aHO
QGn
QGn
aGn

<

t
t
t

=

H = High level (steady state), L
low Level (steady state)
X = Don't' Care (any input, including transitions)

t=

Transition from low to high level

=

QAO. 0eo. aHO The level of QA. QB. or 0H, respectively. before the indicated steady-state input conditions were established.

4

A

e

~

SERIAL INPUTS

oe

t

0An. 0Gn = The level of QA or QG before the most recent transition of the
clock; indicates a one-bit shift.

Qc

OUTPUTS

TLiF/6552·1

54164 (J)

74164 (N)

6·208

Recommended Operating Conditions
DM74164

DM54164
Sym

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

feLK

Clock Frequency

tw

Pulse Width

I
I

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2
0.8

0.8

-0.4

-0.4

8
0

36

25

0

20

20

Clear

20

20

tsu

Data Setup Time

15

15

tH

Data Hold Time·

5

5

TA

Free Air Operating
Temperature

~55

Electrical Characteristics
Sym

Parameter

36

V
mA

8

mA

25

MHz
ns

ns
ns

0

125

V
V

2

Clock

Units

70

0<;:

over recommended operating free air temperature (unless otherwise noted)
Conditions

VI

Input Clamp Voltage

Vee = Min,ll= -12 mA .

VOH

High Level Output
Voltage

Vee= Min, IOH= Max
VIL = Max, VIH= Min

VOL

Low Level Output
Voltage

Vee= Min, IOL= Max
VIH = Min, VIL = Max

II

Input Current@ Max
Input Voltage

IIH

Min

Typ
(Note 1)

2.4

3.2

Max
-1.5

Units
V
V

0.4

V

Vee=Max, VI=5.5V

1

mA

High Level Input
Current

Vee=Max, VI=2.4V

40

/LA

IlL

Low Level Input
Current

Vee= Max, VI=O.4V

-1.6

mA

los

Short Circuit
Output Current

Vee= Max
(Note 2)

mA

Supply Current

Vee= Max (Note 3)

lee

L

J.

0.2

DM54

-10

-27.5

DM74

':"9

-27.5
37

54

mA

Note 1: All typicals are at Vee= 5V, TA = 25·e.
Note 2: Not more than one output should be shorted at a time.

"

Note 3: lee is measured with all outputs open, SERIAL inputs grounded, the eLOeK input at 2.4V, and a momentary ground, then 4.5V, applied to the

CLEAR input.

6-209

Switching Characteristics
Parameter

From
(Input)
To
(Output)

f MAX Maximum Clock
Frequency

at Vee= 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL =8000
CL=15pF
Min

Typ

25

36

CL=50 pF
Max

Min

Typ

Units
Max
MHz

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
Output

8

17

27

10

20

30

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
Output

10

21

32

10

25

37

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
Output

24

36

28

42

ns

6·210

Logic Diagram

(9)

CLEAR~------~~;~--~--------~--------t-------~--------~--------t-------~--------,

CLOCK~(8~)----~i~~~---t----t---;---~----t---~---t----t---;---~----t---~---+----,

OUTPUTS
TLlF/6552·2

Timing Diagram

CLEAR-U-------------------,LJ
'A

SERIAL {
INPUTS

B-+___......J

CLOCK
QA:::'~
QB~::~'

QC:::'~

QD:::~'

OUTPUTS

QE:::~l

QF~::l
QG:::~I

________________

_J

__________________

~

______________________
__________________________
_________ ____
~

~

~

~·~

________________________________

QH:::'~I

~
~~~

_________________

CLEAR

I

~~

CLEAR

TL/F/6552·3

..

6·211

~r---------~----------------------------------------~-------------'

co

~ ~National
Q ~ Semiconductor

:E

~

co

T""
~
~

:E
Q

DM54165/DM74165 a·Bit Parallelln/serial

Out Shift Registers
General Description

Features

These are a·bit serial shift registers which shift the data in
the direction of QA toward QH when clocked. Parallel·in ac·
cess is made available by eight individual direct data in·
puts, which are enabled by a low level at the shift Iload
input. These registers also feature gated clock inputs a~d
complementary outputs from the eighth bit.

• Complementary outputs
• Direct overriding (data) inputs

Clocking is accomplished through a 2·input NOR gate,
permitting one input to be used as a clock·inhibit function.
Holding either of the clock inputs high inhibits clocking, and
holding either clock input low with the load input high en·
abies the other clock input. The clock·inhibit input should
be changed to the high level only while the clock input is
high. Parallel loading is inhibited as long as the load input is
high. Data at the parallel inputs are loaded directly into the
register on a high·to·low transition of the shift /load input,
regardless of the logic levels on the clock, clock inhibit, or
serial inputs.

•
•
•
•

Gated clock inputs
Parallel·to·serial data conversion
Typical frequency 20 MHz
Typical power dissipation 200 mW

Absolute Maximum Ratings

(Note 1)

7V

Supply Voltage
Input Voltage
Storage Temperature Range

5,5V
- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will

define the conditions for actual device operallon.

Function Table

Connection Diagram
Dual·ln·Line Package
Vee INHIBIT '0

r'6

1.5

Inputs

PARALLEL INPUTS

CLOCK

I..

C

B

Internal

SERIAL OUTPUT

A' INPUT

QH

"3 \12 \11 \.0

9

Shill/ Clock
Load Inhlbil

III II

L
H
H
H
H

Clock

Serial

X

X

L
L
L
H

L

X
X

t
t

H
L

X

X

Parallel

Outputs

Output
OH

A. .. H

OA

Os

a, .. h
X
X
X
X

a
OAO
H
L
OAO

b

h

aBO
OAn
OAn
aBO

OHO
OGn
OGn
OHO

= High Level (steady slale), L = Low Level (steady stale)
X = Don't Care (any mput. Including tranSitions)

H

•

I\3 I I!5 I16 II'
~.

SL~~~ CLOCK' \ E

F

H

G

/

I ::;

TranSition from low-to-hlgh level
h '" The level of steady-state Input at Inpuls A through H. respectively
0AO. OSO' 0HO::> The level of 0A' OS. or 0H, respectively. before the Indicated steady-slale
mput condilions were established.
0An' QGn '" The level of QA or aGo reapectlvely. before the most recent I transillon of the
clOCk.

a

IB

OUTPUT GND

QH

PARALLEL INPUTS

TLlF/6553-'

54165 (J)

74165 (N)

6·212

Recommended Operating Conditions
DM74165

DM54165
Parameter

Sym
Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

Units
V
V
V

0.8

0.8

High Level Output
Current

-0.8

-0.8

mA

IOL

Low Level Output
Current

16

16

mA

fCLK

Clock Frequency

14

MHz

tw

Pulse Width

tsu

Setup Time

tH

Data Hold Time

TA

Free Air Operating
Temperature

0

20

14

0

Clock

35

35

Load

35

35

Parallel

25

25

Serial

40

40

5

ns

ns

ns

5

-55

Electrical Characteristics

20

125

70

0

over recommended operating free air temperature (unless otherwise noted) .
Typ
(Note 1)

Sym

Parameter

VI

Input Clamp Voltage

VOH

High Level Output
Voltage

Vcc= Min, IOH= Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vcc= Min, IOL= Max
VIH = Min, VIL = Max

II

Input Current@Max
Input Voltage

Vcc = Max, VI = 5.5V

IIH

High Level Input
Current

Vcc= Max
VI=2.4V

Low Level Input
Current

Vcc= Max
VI=0.4V

Shift/Load

-3.2

Others

-1.6

Short Circuit
Output Current

Vcc=Max
(Note 2)

Supply Current

-Vcc= Max (Note 3)

IlL

los

Icc

DC

Conditions

Min'

Vcc= Min, 11= -12 mA

-

Max
-1.5

2.4

Units
V
V

0.2

0.4

V

1

mA

Shift/Load

80

p.A

Others

40

DM54

-20

-55

DM74

-18

-55
40

63

mA

mA

mA

Notet: All typicals are at VCC=SV, TA=2S·C.
Note 2: Not more than one output should be shorted at a time.
Note 3: With the outputs open, the CLOCK Inhibit and SHIFT/LOAD inputs at 4.SV, and a clock pulse applied to the CLOCK input,lcC Is measured first with

the parallel inputs at 4.SV, then at ground.

,

6-213

~r-----------------------------------------------------------------------~----,

co
:;;:

SWitching Characteristics

'"

,From
(Input)
To
(Output)

:E

-....
c

~

Parameter

CO

~

:E
c

at Vee'" 5V and TA'" 25°C (See Section 1 for Test Waveforms and Output Load)
RL=40011
C L =15 pF

fMAX Maximum Clock
Frequency

Min

Typ

14

20

Units
Max
MHz

tpLH Propagation Delay
Time Low to High
Level Output

Load
to
AnyQ

34

50

ns

tpHL Propagation Delay
Time High to Low
Level Output

Load
to
Any Q

42,

60

ns

Clock
to
AnyQ

26

40

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
AnyQ

35

50

ns

tpLH Propagation Delay
Time Low to High
Level Output

H
to
QH

25

40

ns

tpHL Propagation Delay
Time High to Low
Level Output

H
to
QH

36

50

ns

tpLH Propagation Delay
Time Low to High
Level Output

H
to
OH

25

40

ns

tpHL Propagation Delay
Time High to Low
Level Output

H
to
OH

36

50

ns

tpLH Propagation Delay
Time Low to High
Level Output

\

6-214

r--------------------------------------------------------------------,c
Logic Diagram
en

s:
....
~

-s:
Q)

en

PARALLEL INPUTS

C

....:;;:!

m
(9)

OUTPUTQH
SERIAL
INPUT

(7)

(,ei)

-=-.:........C>o-.......---I-+-l'

OUTPUTOH

cD......

SHIFT/.;.('..,:)......_ _ _
LOAD

TLIF16552-2

Timing Diagram

TYPICAL SHIFT, LOAD, AND INHIBIT SEQUENCES
CLOCK

CLOCK INHIBIT
SERIAL INPUT

--........;;.......---t-------------------

SHIFT/LOAD

A

B ___~-------r-------------------------------C

D ___~;.......------t--------------------------------DATA
E

F __

-+~

____-r____________________________

G

H

H

H

OUTPUTOH
I-INHIBIT--i--------:SERIAL S H I F T - - - - - - _
LOAD

TLIF16552-3

6-215

~National

~ Semiconductor
DM54166/DM74166 a·Bit Paralielln/Serial
Out Shift Registers
General Description
These parallel-in or serial-in, serial-out shift registers feature gated clock inputs and an overriding clear input. All inputs are buffered to lower the drive requirements to one
normalized load, and .input clamping diolles minimize
switching transients to simplify system design. The load
mocj.e is established by the shiftlload input. When high, this
input enables the serial data input and couples the eight
flip-flops for serial shifting with each clock pulse. When
low, the parallel (broadside) data inputs are enabled and
synchronous loading occurs on the next clock pulse. During
parallellosding, serial data flow is inhibited. Clocking is accomplished on the low-to-high-Ievel edge of the clock pulse
through a two-input NOR gate, permitting one input to be
used as a clock-enable or clock-inhibit function. Holding either of the clock inputs high inhibits clocking; holding either
low enables the other clock input. This allows the system
clock to be free-running, and the register can be stopped on

command with the other clock input. The clock-inhibit input
should be changed to the high level only while the clock
input is high. A buffered, direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero.

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

Dual-In-Line Package
PARALLEL INPUTS

PARALLEL
SHIFT I
LOAD

116

INPUT
H

15

OUTPUT,
QH
G

14

CLEAR
12

13

11

10

-

p

4
SERIAL

C

A

D

INPUT

CLOCK CLOCK
INHIBIT

G!~

PARALLEL INPUTS

TLlF/6554·'

54166 (J)

74166(N)

Function Table
Inputs

Clear
L
H
H
H
H
H

Shill/
Load

Clock
Inhibit

X
X
L
H
H
X

X
L
L
L
L
H

Clock
X
L.

t
t
t
t

Serial
X
X'
X
H
L
X

7V
5.5V
- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety 0; the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Vee

(Note 1)

Internal
Outputs

Perallel
A ... H

OJ(

OB

X
X
a ... h
X
X
X

L
OAO

L
OSO
b
OAn
OAn
OSO

a
H
L
OAO

H - HIgh Level (steady state), L= Low Lel/el (steady slate)
X == Don't Care (any input, including transillona)
Transition from low 10 hIgh level
a ... h '" The level 01 steady-stele input al inputs A through H, respectively
OAQ. 0ao. atom'" The level of 0A., aa. 0H. respectively. before the IndIcated
steady-state Input conditions were estabbshed

t-

0A.n. OGn "" The level of QA., QQ. respectively, before the most racant , transitIon oftha clock

6-216

Output

OH
L
OHo
h
OGn
OGn
OHO

Recommended Operating Conditions
DM74166

DM54166
Sym

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

Units
V
V

0.8

0.8

High Level Output
Current

-0.8

-0.8

mA

10L

Low Level Output
Current

16

16

mA

feLK

Clock Frequency

25

MHz

tw

Pulse Width

tsu

Setup Time

tH

Data Hold Time

TA

Free Air Operating
Temperature

0

0

24

24

Clear

20

20

Mode

30

30

Data

20

20

0

Parameter

ns

ns

0

-55

Electrical Characteristics
Sym

25

Clock

125

V

ns
70

0

·C

over recommended operating free air temperature (unless otherwise noted)
Conditions

Min

Typ
(Note 1)

Max

Units

VI

Input Clamp Voltage

Vee= Min, II = -12 mA

VOH

High Level Output
Voltage

Vee= Min, 10H= Max
VIL = Max, VIH = Min .

VOL

Low Level Output
Voltage

Vee = Min, IOL= Max
VIH = Min, VIL = Max

0.4

'V

II

Input Current@Max
Input Voltage

Vee = Max, VI = 5.5V

1

mA

IIH

High Level Input
Current

Vee = Max, VI = 2.4V

40

I'A

IlL

Low Level Input
Current

Vee=Max, VI=0.4V

-1.6

mA

los

Short Circuit
Output Current

Vce= Max
(Note 2)

mA

Supply Current

Vee = Max
(Note 3)

Icc

Note 1:

-1.5
2.4

V
V

DM54

-20

-57

DM74

-18

-57

DM54

72

104

DM74

72

116

mA

All typicals are at Vee = 5V. TA = 25'C.

Note 2: Not more than one output should be shorted at a time.
Note 3: With all outputs open, 4.SV applied to the SERIAL input. all other inputs except CLOCK grounded, ICC is measured after a momentary ground. then

4.5V, is applied to the CLOCK.

,
6·217

i

~,

Switching Characteristics

:E,
"""

o

U)
U)

From
(Input)
To
(Output)

Parameter

,..
"lit

Il)

:E

o

at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL = 40012

C L = 15 pF

f MAX Maximum Clock
Frequency

Min

Typ

25

35

Units
Max
MHz

tplH Propagation Delay
Time Low to High
Level Output

Clock
to
Output

8

17

26

ns

tpHL Propagation Delay
Time High to'Low
Level Output

Clock
to
Output

8

20

30

ns

tPHL Propagation Delay
Time High to ,Low
Level Output

Clear
to
Output

23

35

ns

Logic Diagram

(3)

(4)

B

(5)

(11)

(10)

D

E

(12)

F

(14)

(7)

(6)

H CLOCK CLOCK
INHIBIT

PARAllEL INPUTS
TL/F/6554-2

6-218

.----------------------------------------------------------------------.0
s:

Timing Diagram

C1I

.....
.j:o

CLOCK

CI~ar,

SL f " l - f U l - 1 l - J l - f !l-f1-f1.JLJL.1
-U

0)
0)

Shift, Load, Inhibit, and Shift Sequences

CLOCK INHIBIT
CLEAR
SERIAL INPUT

-

I-'

.....

-,

SHIFT/LOAD

LJ

A

f"Hl

PARALLEL
INPUTS

B

L

c

f"Hl

D

L

iHl
L

f"H ~
f"Hh

G
H
OUTPUT QH

~
o
.....
.j:o

-s:

Typical

---:

--

H

H

- - - - - - S E R I A L SHIFT------III-INHIBIT-I
LOAD
CLEAR

L

H

L

H

L

H

1-1-'----SERIAL S H I F T - - - - TLfF/6554·3

Parameter Measurement Information
Voltage Waveforms
tw(CLEAR)
3.0V _ _ _~

CLEAR
INPUT

t n+1

OV--------+~----J

ov
DATA 3.0V
INPUT

(SEE TEST TABLE)

OV

----t-------I-r--hl
--------t-----.,------'

tpHL

(CLOCK·Q)

VOH _________-..
OUTPUTQ
VOL------------'~---------------'

TL/F/6554-4

Test Table For Synchronous Inputs
Data Input
For Test

Shift/Load

Output Tested
(See Note C)

H
Serial Input

OV
4.5 V

QH atTN+l
QH at TN+8

Note A: The clock pulse has the following characteristics: tW(clock) 2:: 20 ns and PRR = 1 MHz. The clear pulse has the following characteristics: tW(clear) 2:: 20 ns and
tHOLD = 0 ns. When testing 'MAX. vary Ihe clock PRR.
Nota B: A clear pulse is applied prior to each test.
Note C: Propagation delay times (tPLH and tpHL) are measured at In+1" Proper shifting of data is verified at I n+8 with a functional ~est.
Nota D: In = bit time before clocking transition
tn+ 1 = bit time after one clocking transition
t n +8 = bit time after eight clocking transitions
Noto E: VREF = 1.5 V for 166

6-219

or------------------------------------------------------------------------,
,...
~ ~National

~ ~ Semiconductor
DM74170 4 by 4 Register Files
General Description
These 16-bit TTL register files are organized as 4 words of
4 bits each, and separate on-chip decoding is provided for
addressing the four word locations to either write-in or retrieve data. This permits writing into one location and reading from another word location, simultaneously.
Four data inputs are available to supply the 4-bit word to be
stored. Location of the word is determined by the write-address inputs A and B, in conjunction with a write-enable signal. Data applied at the inputs should be in its true form.
That is, if a 'high-level signal is desired from the output, a
high level is applied at the data input for that particular bit
location. The latch inputs are arranged so that new data will
be accepted only if both internal address gate inputs are
high. When this condition exists, data at the 0 input is
transferred to the latch output. When the write-enable input, GW, is high, the data inputs are inhibited and their levels can cause 'no change in the information stored in the
internal latches. When the read-enable input, GR, is high,
the data outputs are inhibited and remain high.
The individual address lines permit direct reading of data
stored in any four of the latches. Four individual decoding
gates are used to complete the address for reading a word.
When the read address is made in conjunction with the
read-enable signal, the word appears at the four outputs.
This arrangement-data entry addressing separate from
data-read addressing and individual sense line-eliminates recovery times, permits simultaneous reading and
writing, and is limited in speed only by the write time (30 ns
typical) and the read time (25 ns typical). The register file
has a nondestructive readout in that data is not lost when
addressed.
All inputs are buffered to lower the drive requirements to
one standard load. Input-clamping diodes minimize

switching transients to simplify system design. Highspeed, double-ended AND-OR-INVERT gates are employed for the read-address function and drive high-sinkcurrent, open-collector outputs. Up to 256 of these outputs
may be wire-AND connected for increasing the capacity
up to 1024 words. Any number of these registers may be
paralleled to provide n-bit word length.

Features
• Separate addressing permits simultaneous reading and
writing
• Fast access times typically 20 ns
• Organized as 4 words of 4 bits
• Expandable to 1024 words of n-bits
• For use as:
Scratch-pad memory
Buffer storage between processors
Bit storage in fast multiplication designs
• Open-collector outputs with low maximum off-state
current:
170301LA
• OM54LS670 and DM74LS670 are similar but have
TRI-STATE outputs

Absolute Maximum Ratings

(Note 1)

7V
5.5V
- 65·C to 150·C

Supp,ly Voltage
Input Voltage
Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety 01 the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions lor actual device operation.

Function Tables

Connection Diagram

WRITE TABLE (SEE NOTES A, B, AND C)

Oual-In-Line Package

WrIte Inputs

I

WA

GW

0

1

2

3

L
L
H
H

L
H
L
H

X

X

L
L
L
L
H

0=0
00
00
00
00

00
0=0
00
00
00

00
00
0=0
00
00

00
00
00
0=0
00

READ TABLE (SEE NOTES A AND D)

1

.02

Word

WB

Read Inputs

J:
DATA

~l3

04,

J:

I

R~ -----......-- Gl~

~

READ
SELECT

a~6 a~7
OUTPUTS

TL/F/6555,1

74170 (N)

Outputs

RB

RA

GR

01

02

03

04

L
L
H
H

L
H
L
H

X

X

L
L
L
L
H

WOBI
W1Bl
W2Bl
W3Bl
H

WOB2
W1B2
W2B2
W3B2
H

WOB3
W1B3
W2B3
W3B3
H

WOB4
W1B4
W2B4
W3B4
H

Note A: H = High Level, L = low level. X

= Don't Care

Note B: (Q = D) = The four selected internal flip-flop outputs will assume the
states applied to the four external data inputs.
Note C: 00 = The level of
lished.
Note 0: WOB 1

6-220

a before the indicated input conditions were estab-

= The first bit of word 0, etc.

Recommended Operating Conditions
DM74170
Symbol

Parameter

Min

Nom

Max

5

5.25

Units

Vee

Supply Voltage,

4.75

V1H

High Level Input
Voltage

2

V IL

Low Level Input
Voltage

0.8

V

V OH

High Level Output
Voltage

5.5

V

IOL

Low Level Output
Current

16

mA

tw

Pulse Width

tsu

tH

V

Write· Enable

25

Read·Enable

25

Setup Time
(Note 1)

Data

10

Select

15

Hold Time
(Note 1)

Data

15

Select

5

tLAT

Latch Time for
New Data (Note 2)

40

TA

Free Air Operating
Temperature

0

Electrical Characteristics
Symbol

V

ns

ns

ns

ns
·C

70

--

over recommended operating free air temperature (unless otherwise noted)

Parameter

Conditions

Min

Typ
(Note 3)

Max

Units

-1.5

V

30

/LA

0.4

V

Vce=Max, VI =5.5V

1

mA

High Level Input
Current

Vee=Max, VI=2.4V

40

/LA

IlL

Low Level Input
Current

Vee= Max, VI = O.4V

-1.6

mA

Icc

Supply Current

Vee = Max (Note 4)

150

mA

VI

Input Clamp Voltage

Vee= Min, 11= -12 mA

ICEX

. High Level Output
Current

Vec=Min, Vo=5.5V
VIL= Max, VIH= Min

VOL

Low Level Output
Voltage

Vec= Min, IOL= Max
VIH = Min, VIL = Max

II

Input Current@Max
Input Voltage

IIH

0.2

127

Note 1: Times are with respect to the Write-Enable input.

Note 2: Latch time is the time allowed for the internal output of the latch to assume the state of new data. This Is Important only when attempting to read
from a location Immediately after that location has received new data.

Note 3: All typicals are at Vec= 5V, TA= 25·C.
Note 4: ICC is measured with all DATA and ENABLE InputS at 4.5V, all ADDRESS inputs grounded and all outputs open.

6·221

,Switching Characteristics
Parameter

at Vee ~5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
From
(Input)
To
(Output)

RL=4000
CL=15 pF
Min

Units

Typ

Max

tpLH Propagation Delay'
Time Low to High
Level Output

Read
Enable to
Any Q

17

25

ns

tpHL Propagation Delay
Time High to Low
Level Output

Read
Enable to
Any Q

20

30

ns

tpLH Propagation Delay
rime Low to High
Level Output

Read
Select to
Any Q

23

35

ns

tpHL Propagation Delay
.. Time High to Low
Level Output

Read
Select to
Any Q

30

40

ns

tpLH Propagation Delay
Time Low to High
Level Output

Write
Enable to
AnyQ

25

40

ns

tpHL Propagation Delay
Time High to Low
Level Output

Write
Enable to
AnyQ

34

45

ns

tpLH Propagation Delay
Time Low to High
Level Output

Data
to
Any Q

20

30

ns

tpHL Propagation Delay
Time High to Low
Level Output

Data
to
AnyQ

30

45

ns

,

(

6·222

Logic Diagram

170

DATA
INPUTS

TLfF/6555·2

6·223

~

~

'?'A National

-8

DM54173/DM74173 TRI·STATE® Quad D Registers

.
~ ~ Semiconductor
~
~ General Description

Features

These four-bit registers contain D-type flip-flops with totem-pole TRI-STATE o~tputs. capable of driving highly capacitive or low-impedance loads. The high-impedance
state and increased high-logic-level drive provide these
flip-liops with the capability of driving the bus lines in a busorganized system without need for interface or pull-up
components.
Gated enable inputs are provided for .controlling the entry
of data into the flip-flops. When both data-enable inputs
are low, data at the 0 inputs are loaded into,their respective flip-flops on the next positive transition of the buffered
clock input. Gate output control inputs are also provided.
When both are low, the normal logic states of the four outputs are available for driving the loads or bus lines. The
outputs are disabled independently from the level of the
clock by a high logic level at either output control input.
The outputs then present a high impedance and neither
load nor drive the bus line. Detailed operation is given in
the function table.

• TRI-STATE outputs interface directly with system bus
• Gated output control lines for enabling or disabling the
outputs
• Fully independent clock eliminates restrictions for
operating in one of two modes:
Parallel load
Do nothing (hold)
• For application as bus buller registers
• Typical propagation delay 18 ns
., Typical frequency 30 MHz
• Typical power dissipation 250 mW

Absolute Maximum Ratings

(Note 1)

7V

Supply Voltage
Input Voltage
Storage Temperature Range

5.5V

- 65"C to 150"C

To minimize the possibifity that two outputs will attempt
to take a common bus to oPPosite logic levels, the output
control circuitry is designed so that the average output
disable times are shorter than the average output enable
times.

Nota 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed, The device should
not be operated at these limits. The 'parametrlc values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual-In-Line Package
DATA ENABLE
INPUTS

OATAINPUTS

vee CLEAR. 01
116

15

14

02

03

13

12

04

G2

11

Inputs

G1

10

19

Clear

Clock

H
L
L
L
L
L

X
L

t
t
t
t

Data Enable

G1

G2

Data
0

X
X
H
X
L
L

X
X
X
H
L
L

X
X
X
X
L
H

Output
Q

L

QO
QO
QO
L
H

When either M or N (or both) is (are) high the output is disabled
to the high-impedance Slate; however. sequential operation of
the flip-flops is not affected.

H = high level (steady state)
L = low level (steady state)

3
Q1
OUTPUT
CONTROL

4
02

t = low-to-high level transition
x = don't care (any input including transitions)

5
03

00 = the level of 0 before the indicated steady state input conditions.
were established

OUTPUTS
TLlF/6556·'

54173 (J)

74173 (N)

6-224

c

s:
C1I

Recommended Operating Conditions
DM54173
Parameter

,Sym _

~

.....

DM74173

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

-2

-5.2

rnA

IOL

Low Level Output
Current

16

16

rnA

feLK

Clock Frequency

25

MHz

tw

Pulse Width

tsu

JH

Setup Time

Hold Time

tREL

Clear Release Time

TA

Free Air Operating
Temperature

2

V
V

2

0

0.8

25

0

Clock·

20

20

Clear

20

20

Enable

17

17

Data

10

10

Enable

2

2

Data

10

10

ns

ns

ns

10

10
-55

125

V

, ns

0

70

·C

,

Parameter

ov~r recommended operating free air temperature (unless otherwise noted)
Conditions

Min

VI

Input Clamp Voltage

Vee = Min, 11= -12 mA

VOH

High Level Output
Voltage

Vee= Min, IOH= Max
VIL = Max, VIH = Min

VOL

' Low Level Output
Voltage

Typ
(Note 1)

Max
-1.5

Units
V
V

2.4

Vec= Min, 10L= Max
V IH = Min, V IL = Max

0.4

V

II

Input Current@Max
Input Voltage

Vcc= Max, VI = 5.5V

1

mA

IIH

High Level Input
Current

Vce= Max, VI = 2.4V

40

p.A

IlL

Low Level Input
Current

Vcc= Max, VI,= O.4V

-1.6

mA

10zH

Off-State Output
Current with High
Level Output
Voltage Applied

Vcc=Max, Vo=2.4V
V IH = Min, VIL = Max

40

p.A

10ZL

Off-State Output
Current with Low
Level Output
Voltage Applied

Vcc= Max, Vo= 0.4V
VIH= Min, VIL= Max

-40

p.A

los

Short Circuit
Output Current

Vcc= Max
(Note 2)

mA

Supply Current

Vcc = Max (Note 3)

Icc

-s:
W

C

~
.....
......

0.8

Electrical Characteristics
Sym'

......

I

DM54

-30

-70

I

DM74

-30

-70
50

72

mA

Nolel: All typlcals are at VCC=SV. TA=2S"C.
Note 2: Not more than one output should be shorted at a time.

Note 3: ICC is measured with all outputs open, CLEAR grounded after a momentary connection to 4.SV: N, Gl, G2 and all OATA inputs grounded: and the
CLOCK input and M input at 4.SV.

6-225

W

Switching Characteristics
Parameter

at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)

From
(Input)
To
(Output)

RL=400n
CL=50 pF

CL=5 pF
Min

Typ

Max

f MAX Maximum Clock
Frequency

Min

Typ

25

30

Units
Max
MHz

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
Output

16

25

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
Output

20

28

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
Output

18

27

ns

7

16

30

ns

7

21

30

ns

tPZH Output Enable
Time to High
Level Output

.

Output
. Control to

tPZL Output Enable
Time to Low
Level Output

Output
Control to

tpHZ Output Disable
Time from High
Level Output

Output
Control to

tpLZ Output Disable
Time from Low
Level Output

Output
Control to
Q

Q

Q

3

5

14

ns

3

11

20

ns

Q

•

r

6·226

Logic Diagram

OUTPUT{M~(~l)~--)-________________________________- - ,
CONTROL

N _(_2).....,,__,/

DATA

-+_-r-.....

~(.:..14;:.) _ _ _ _ _ _

01

DA~~ ...:..;,;;:....--~---+--r-...,

CLOCK

(7)

DATA_(~'1~2)~_~~_ _~_-1_'
03

DATA

..;(~1..:.1)~_ _~_ _ _ _..,.,._"

04

CLEAR (15)
TLlFf6556·2

6·227

~

~ ~National
~ Semiconductor

:E
c

ie....
~

DM54174JDM74174, DM54175JDM74175 HexJQuad D
Flip-Flops with Clear

:E

c General Description
These positive-edge triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct
clear input,\and the quad (175) version features complementary outputs from each flip-flop.
Information at the D Inputs meeting the setup and hold
time requirements is transferred to the 0 outputs on the
positive-going edge of the clock pulse. Clock triggering
occurs at a particular voltage level and is not directly
related to the transition time of the positive-going pulse.
When the clock input is at either the high or low level, the D
input signal has no effect at the output.

• Individual data input to each flip-flop
• Applications include:
Buffer I storage registers
Shift registers
Pattern generators
• Typical clock frequency 40 MHz
• Typical power dissipation per flip-flop 38 mW

Absolute Maximum Ratings

7V
5.5V
- 65·C to 150·C

Supply Voltage
Input Voltage
Storage Temperature Range

'Features
• 174 contains six flip-flops with single-rail outputs.
• 1i5contains four flip-flops with double-rail outputs.
• Buffered clock and direct clear inputs.

(Note 1)

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagrams
Dual-In-Line Package

Dual-In-Line Package

Vee

06

06

05

05

04

Q4

CLEAR

01

01

02

Q2

03

Q3

CLOCK

GND.

Vee

Q4

04 ,

D4

03

03

03

CLOCK

CLEAR

01

01

D1

02

02

02

GND

TLlF/6557-1

54174 (J)

Function Table

TLlF16557·2

74174 (N)

54175 (J)

(Each Flip-Flop)
Outputs

Inputs
Clear

Clock

D,

a

at

L

x
t
t

L
H
L

H

H
H
H

X
H
L
X

00

'00

'L

L

H

H = High Level (steady state)
l. = low Level (steady state)
= Don't Care
t = Transition from low to high level
00 = The level of
before the indicated steady-state input conditions were
established.
t = 175 only

x

a

6-228

74175 (N)

Recommended Operating Conditions
DM54174

Parameter

Sym
Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

DM74174

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units
V
V

2
0.8

0.8

High Level Output
Current

-0.8

-0.8

mA

10L

Low Level Output
Current

16

16

mA

fCLK

Clock Frequency

30

MHz

tw

Pulse Width

0

30

0

Clock Low

25

25

Clock High

10

10

Clear

V

ns

20

20

tsu

Data Setup Time

20

20

ns

tH

Data Hold Time

0

0

ns

tREL

Clear Release Time

30

30

TA

Free Air Operating
Temperature

-55

125

ns

0

70

·C

'174 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Sym

Parameter

Conditions

Min

Typ
(Note 1)

Max

VI

Input Clamp Voltage

Vcc= Mln,ll= -12 mA

VOH

High Level Output
Voltage

Vcc= Min,loH= Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vcc= Min, 10L=·Max
VIH = Min, VIL= Max

0.4

V

II

Input Current@Max
Input Voltage

Vcc= Max, VI = 5.5V

1

mA

IIH

High Leilel Input
Current

Vcc=Max, VI=2.4V

40

p.A

IlL

Low Level Input
Current

Vcc= Max, VI = 0.4V

-1.6

mA

los

Short Circuit
Output Current

Vcc= Max
(Note 2)

mA

Supply Current

Vcc= Max (Note 3)

Icc

I
I

-1.5

Units
V
V

2.4

DM54

-20

- 57

DM74

-18

-57
45

65

mA

.~

Note 1: All typlcals are at VCC=SV. TA=2S'C.
Note 2: Not more than one output should be shorted at a time.

Note 3: With all outputs open and all DATA and CLEAR inputs at 4.SV. ICC is measured after a momentary ground. then 4.SV applied to the CLOCK input.

6·229

'174 Switching Characteristics

at Vee=5V al]d TA=25 DC
(See Section 1 for Test Waveforms and Output Load)
From
(Input)
To
(Output)

Parameter

RL=400n
CL='15 pF
MIn

Typ

30

40

f MAX Maximum Clock
Frequency

Units
Max
MHz

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
Any'O

14

25

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
Any 0

17

25

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
Any 0

30

40

ns

Recommended Operating Conditions
Sym

Parameter

Vec

Supply Voltage

V1H

High Level Input
Voltage

V1L

Low Level Input
Voltage

IOH

DM74175

DM54175
Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units
V
V

2
0.8

0.8

High Level Output
Current

-0.8

-0.8

mA

IOl

Low Level Output
Current

16

16

mA

fCLK

Clock Frequency

30

MHz

tw

Pulse Width

0

30

0

Clock Low

25

25

Clock High

10

10

Clear

20

)

V

ns

-

20

tsu

Data Setup Time

20

20

ns

tH

Data Hold Time

0

0

ns

tREL

Clear Release Time

30

30

ns

TA

Free Air Operating
Temperature

-55

125

6·230

0

70

DC

'175 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Sym

Parameter

Conditions

Typ
(Note 1)

Min

Max
-1.5

Units
V

VI

Input Clamp Voltage

Vcc= Min, 11= -12 mA

VOH

High Level Output
Voltage

Vcc = Min, 10H = Max
Vll = Max, VIH= Min

VOL

Low Level Output
Voltage

Vcc= Min, 10l= Max
VIH = Min, VIL= Max

0.4

V

II

Input Current@Max
Input Voltage

Vcc = Max, VI = 5.5V

1

mA

IIH

High Level Input
Current

Vcc=Max, VI=2.4V

40

p.A

III

Low Level Input
Current

Vcc~Max, VI=O.4V

-1.6

mA

Short Circuit
Output Current

Vcc= Max
(Note 2)

mA

Supply Current

Vcc= Max (Note 3)

los

,
Icc

I
I

2.4

V

DM54

-20

-57

DM74

-18

-57
30

45

mA

'175 Switching Characteristics

at Vcc=5V and TA=25°C
(See Section 1 for Test Waveforms and Output Load)

Parameter

From
(Input)
To
(Output)

Rl =4000
Units

C l =15pF

fMAX Maximum Clock
Frequency

Min

Typ

30

40

Max
MHz

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
Any Q

14

25

ns

tpHL Propagation Delay
Time High to i..ow
Level Output

Clock
to
Any Q

17

25

ns

tpLH Propagation Delay
Time Low to High
Level,output

Clear
to
Any Q

14

25

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
Any Q

30

40

ns

Nole 1: All typlcals are at vcc= 5V, TA= 25'C.
Nole 2: Not more than one output should be shorted at a time.
Nole 3: With all outputs open and 4.5V applied to all DATA and CLEAR inputs, ICC is measured aiter a momentary ground then 4.5V applied to the CLOCK.

6-231

I.t)

.....
Logic Diagrams
~
.....
:E
c
\ I.t)
.....
'\"""

'\"""
~

I.t)

:E

174

C

~
.....

175
(4)

(3)
Dl

Dl

01

(2)
D

01

0

'\"""

~

.....

(3)

:E

-.....

01

C

~

'\"""

D2

(7)

02

D2

02

;1;
(6)

:E

02

C

D3

(10)

03

03

D3

03

(15)

D4

04

D4

04

CLOCK

a.

CLEAR
D5

05

TLIF/6557·4

D6

CLOCK

O'-"":""---H-I

06

~-,""'~_ _

CLEAR

TLlF16557·3

6·232

c

s:

~National

CI1

.j:Io
.....

~ Semiconductor

~

-s:
C

DM54176/DM74176, DM54177/DM74177 Presettable Decade
and Binary Counters

:j;;!
.....
.....
s»
c

General Description

Features

These high·speed counters consist of four d·c coupled,
master·slave flip·f1ops which are internally intercon·
nected to provide either a divide·by·two and a divide·by·
five counter (176) or a divide·by·two and a divide·by·eight
counter(177). These counters are fully programmable; that
is, the outputs may be preset to any state by placing a low
on the count/load input and entering the desired data at
the data inputs. The outputs will change independent of
the state of the clocks.

•
•.
•
•

s:

Performs BCD, bi·quinary, or binary counting
Fully programmable
Fully independent clear input
Output QA maintains full fan·out capability in addition to
driving clock·2 input

• Typical count frequency
Clock 1 50 MHz
Clock 2 25 MHz
• Typical power dissipation 150 mW

During the count operation, transfer of information to the
outputs occurs on the negative'going edge of the clock
pulse. These counters feature a direct clear which, when
taken low, sets all outputs low regardless of the state of the
clocks.

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

These counters may also be used as 4·bit latches by using
the count/load input as the strobe and entering data at the
data inputs. The outputs will directly follow the data inputs
when the count !load is low, but will remain unchanged
when the count !load is high and the clock inputs are
inactive.
(Continued)

Dual·ln·Llne Package

r

14

DATA INPUTS

CLEAR

aD

~

D

12

13

11

e

ae

CLOCK
1

CLOCK

GND

10

17
COUNT
LOAD

ac

C

7V
5.5V
- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

vcc

(Note 1)

A

~

QATA INPUTS

2
TL/F/6558·1

Nole: Low mput to clear sets CA.

54176 (J)
54177 (J)

aS. Qc and aD low.
74176 (N)
74177 (N)

6·233

~
.....
.....
.....

C

s:
:j;;!
.....
.....
.....

~r-~--------------------------------~------------------~

....oo:t

General Description

::E

TYPICAL COUNT CONFIGURATIONS 176

r::
~

The output of flip-flop A is not internally connected to the
succeeding flip-flops; therefore, the count may be operated
in three independent modes:

an~ aD outputs. In this mode, the two counters operate independently; however, all four flip-flops are
loaded and cleared simultaneously.

1. When used as a BCD decade counter, the clock-2 input must be externally connected to the QA output.
The clock-1 input receives the Incoming count, and a
count sequence is obtained in accordance with the
BCD count sequence function table .

The output of flip-flop A is not internally connected to the
succeeding flip-flops; therefore the counter may be operated in two independent modes:

~

(Continued)

~

o

~

::E
o
tIS
~

....

~
::E

-....o
CD
~

oo:t

Il)

::E
o

177

1. When used as a high-speed 4-bit ripple-through
counter, output OA must be externally connected to
the clock-2 input. The input count pulses are applied
to the clock-1 input. Simultaneous divisions by 2,4,
8, and 16 are performed at the QA, QB, QC and QD
outputs as shown in the function table.

2. If a symmetrical dlvide-by-ten count is desired for
frequency synthesizers (or other applications requiring division of a binary count by a power of ten), the
QD output must be externally connected to the
clock-1 input. The input count is then applied at the
'clock-2 input and a divide-by-ten square wave is obtained at output QA in accordance with the biquinary function table.

2. When used as a 3-bit ripple-through counter, the input
count pulses are applied to the clock-2 input. Simultaneous frequency divisions by 2, 4, and 8 are available
at the OB, OC, and aD outputs. Independent use of
flip-flop A is available if the load and clear functions
coincide with those of the 3-bit ripple-through
counter.

3. For operation as a divide-by-two counter and a divideby-five counter, no external interconnections are required. Flip-flop A is used as a binary element for the
divide-by-two function. The clock-2 input is used to
obtain binary divide-by-five operation at the OB, OC,

Function Tables

176
Decade (BCD)
(See Note A)

QD

QC

QB

QA

L
L
L
L
L
L
L
L
H
H

L
L
L
L
H
H
H
H
L
L

L
L
H
H
L
L
H

L
H
L
H
L
H
L
H
L
H

H
L
L

0
1
2
3
4
5
6
7
8
9

177
(See Note A)

Output

Count

Output

Count
0
1
2
3
4
5
6
7
8
9

176
(See Note B)

QA

QD

QC

QB

L
L
L
L
L
H
H
H
H
H

L
L
L
L
H
L
L
L
L
H

L
L
H
H
L
L
L
H
H
L

L
H
L
H
L
L
H
L
H
L

H = High Level, L = Low Level
Note A: Output QA connected to clock-2 input.
Note B: Output Co connected to clock-1 input.

6-234

Output

Count
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

QD

QC

QB

QA

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H,
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

Recommended Operating Conditions
Sym

Pllrameter

Vcc

S,upply Voltage

V 1H

High Level Input
Voltage

V 1L

Low Level Input
Voltage

IOH

DM74176

DM54176
Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V
V

2

2

Units

0.8

0.8

High Level Output
Current

-0.8

-0.8

mA

IOL

Low Level Output
Current

16

16

·mA

fCLK

Clock Frequency (Clock 1) .

0

35

MHz

tw

Pulse Width

Clock 1

14

14

Clock 2

28

28

Clear

25

25

Load

20

20

Data
High

15

15

Data
Low

20

20

tsu

Setup Time

35

0

V

ns

ns

tH

Data Hold Time

20

20

ns

tEN

Count Enable Time
(Note 1)

25

25

ns

TA

Free Air Operating
Temperature

-55

125

0

70

"C

Note 1: Count enable time is the interval immediately preceding the negative-going edge of the clock pulse during which the count/load and clear Inputs
must both be high to ensure counting.

-

6-235

'176 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)

Sym

Parameter

Conditions

VI

Input Clamp Voltage

Vcc=Min, 11 = -12 mA

VOH

High Level Output
Voltage

Vcc = Min, 10H = Max
Vil = Max, VIH = Min

Val

Low Level Output
Voltage

Vcc = Min, 10l = Max
VIH = Min, Vil = Max
(Note 4)

II

Input Current@Max
Input Voltage

Vce = Max, VI = 5.5V

IIH

High Level Input
Current

Vcc=Max
VI =2AV

Low Level Input
Current

III

los

Icc

Note 1:

Vcc= Max
VI =OAV

Short Circuit
Output Current

Vcc=Max
(Note 2)

Supply Current

Vce = Max (Note 3)

Min

Typ
(Note 1)

2.4

3.4

Max
-1.5

Units
V
V

0.4

V

1

mA

Count/Load

40

p.A

Data

40

Clear

80

0.2

Clock 1

80

Clock 2

120

Count/Load

-1.6

Data

-1.6

Clear

-3.2

Clock 1

-4.8

Clock 2

-4.8

DM54

-20

-57

DM74

-18

-57
30

48

mA

mA

mA

All typicals are at VCC = 5V, TA = 25'C.

Note 2: Not more than one output should be shorted 'at a time.

Note 3: ICC is measured with all inputs grounded and all outputs open.
Note 4: QA outputs
out capability.

are tested at 10l = Max plus the limit value of III for the Clock 2 input. This permits driving the Clock 2 Input while maintaining full fan·

-

.
~

6-236

c
3':
(II

'176 Switching Characteristics

at Vcc=5V and TA =25°C
(See Section 1 for Test Waveforms and Output Load)

Parameter

f MAX Maximum Clock
Frequency

From
(Input)
To
(Output)

,j:o.
.....
.....
en

RL =400n
Units

CL=15 pF

Clock 1
to
aA

Min

Typ

35

50

Max

:~

MHz

C

3':
~
.....

.....

,?l

c

3':

(II

tpLH Propagation Delay
Time Low to High
Level Output

Clock 1
to
aA

9

13

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock 1
to
aA

11

17

ns

-

tpLH p,ropagation Delay
Time Low to High
Level Output

Clock 2
to
aB

12

18

ns

.....
.....

tpHL Propagation Delay
Time High to Low
Level Output

Clock 2
to
aB

14

21

ns

tplH Propagation Delay
Time Low to High
Level Output

Clock 2
to
ac

27

41

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock 2
to
ac

34

51

ns

tpLH Propagation Delay'
Time Low to High
Level Output

Clock 2
to
aD

13

20

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock 2
to
aD

17

26

ns

tpLH Propagation Delay
Time Low to High
Level Output

Data
to
Output

19

29

ns

tpHL Propagation Delay
Time High to Low
Level Output

Data
to
Output

31

46

ns

tpLH Propagation Delay
Time Low to High
Level Output

Load
to
Anya

29

43

ns

tpHL Propagation Delay
Time High to Low
Level Output

Load
to
Any a

32

48

ns

IpHL Propagation Delay
Time High to Low
Level Output

Clear
to
Anya

32

48

ns

,j:o.
.....
.....

.....

,
6·237

c

3':
~
.....

Recommended Operating Conditions
Parameter

Sym
Vcc

.f, Supply Voltage

DM74177

DM54177
Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

VIH

High Level Input
Voltage

Vil

Low Level Input
Voltage

IOH

High Level Output
Current

IOl

Low Level Output
Current

fClK

Clock F.requency (Clock 1)

0

tw

Pulse Width'

Clock 1

14

14

Clock 2

28

28

tsu

Setup Time

2

Units
V
V

2
0.8

0.8

-0.8

-0.8

mA

16

16

mA

35

MHz

35

0

Clear

25

25

Load

20·

20

Data
High

15

15

Data
Low

20

20

V

ns

ns

tH

Hold Time

20

20

ns

tEN

Count Enable Time
(Note 1)

25

25

ns

TA

Free Air Operating
Temperature

-55

125

0

70

·C

Note 1: Count enable time is the interval immediately preceding the negative-going edge of the clock pulse during which the cQuntlload and clear inputs

must both be high to ensure counting.

-.

I

,
6·238

o

s:
C1I

'177 Electrical Characteristics

....

~

over recommended operating free air temperature (unless otherwise noted)
Sym

Parameter

VI

Input Clamp Voltage

Vce=Min, 11= -12 mA

VOH

High Level Output
Voltage

Vee = Min, 10H = Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee=Min,loL=Max
VIH = Min, VIL = Max
(Note 4)

II

Input Current@Max
Input Voltage

Vee = Max, VI = 5.5V

IIH

High Level Input
Current

Vee = Max
VI=2.4V

Conditions

Min

Typ
(Note 1)

2.4

3.4

Max

-1.5

Low Level Input
Current

Icc

V

o

:;;:!
....
......

$I)
0.2

0.4

V

1

mA

40

{LA

o

s:
C1I
....
......
~

:::!

o

Count/Load
Data

40

Clear

80

Clock 1

80

Vee = Max
VI =0.4V

-1.6

Data

-1.6

Clear

-3.2

Clock 1

-4.8

Short Circuit
Output Current

Vee = Max
(Note 2)

Supply Current

Vee = Max (Note 3)

mA

-3.2

DM54

-20

-57

DM74

-18

-57
30

48

mA

mA

NOle 1: Aillypicals are at Vee=SV. TA=2S"e.
Note 2: Not more than one output should be shorted at a tI.me.
Note 3: ICC is measured with all Inputs grounded and all outputs open.
Note 4: QA outputs are tested at IOL = Max plus the limit value of IlL for the Clock 2 input. This permits driving the Clock 2 input while maintaining full fan-

out capability.

..

6-239

s:
:;;:!
....
......
......

80

Count/Load

Clock 2
los

Units

V

Clock 2
IlL

-s:
~

'177 Switching Characteristics

at Vee = 5V and TA = 25°C

(See Section 1 for Test Waveforms and Output Load)

Parameter

"

From
(Input)
To
(Output)

RL =400n
C L =15 pF
Min

Typ

35

50

Units
Max

f MAX Maximum Clock
Frequency

Clock 1
to
QA

tpLH Propagation Delay
Time Low to High
Level Output

Clock 1
to
QA

9

13

ns

tpHL Propagation Dehiy
Time High to Low
Level Output

Clock 1
to
QA

11

17

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock 2
to
Qs

12

18

ns

tpHL Propagation Delay
Time High to Low
Le.vel Output

Clock 2
to
Qs

14

21

ns

tpLH Propagation Delay
Time Low to High'
Level Output

Clock 2
to
Qc

27

41

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock 2
to
Qc

34

51

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock 2
to
Qo

44

66

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock 2
to
Qo

50

75

.ns

tpLH Propagation Delay
Time Low to High
Level Output

Data
to
Output

19

29

ns

t PHL Propagation Delay
Time High to Low
Level Output

Data
to
Output

31

46

ns

tpLH Propagation Delay
Time Low to High
Level Output

Load
to
Any Q

29

43

ns

tpHL Propagation Delay
Time High to Low
Level Output

Load
to
Any Q

32

48

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
AnyQ

32

48

ns

6-240

MHz

..

•

0

~
(J'1
.;..

Logic Diagrams

.....
.....

C»

0

'177

'176

~
.;..

.....
.....
.....

T

(5)

(5)

OA

sn

PRESET

PRESET

T

OA

OA

OA

0

~

(J'1

.;..

(10)
DATA B

.....
.....
.....

-

DATAB (10)

0

(6)
CLOCK 2

(9)

as

(3)

CLDCK2 (6)

(9)

as

DATA C (3)

DATAC

(2)

(2)
Oc

(11)
DATA 0

Oc

DATA 0 (11)
(12)
00
(12) 00

TlfFf6558·2

6-241

TLlF/6558·3

~

.....
.;..
.....
.....
.....

i

~

'?A National

~ ~ Semiconductor

i

~

;1;
c DM54180/DM74180 9·Bit Parity Generators/Checkers

:E

General Description

Absolute Maximum Ratings

These universal 9-bit (8 data bits plus 1 parity bit) parity
generators I checkers feature odd I even outputs and control inputs to facilitate operation in either odd or even parity
applications. Depending on whether even or odd parity is
being generated or checked, the even or odd inputs can be
utilized as the parity or 9th·bit input. The word-length capability is easily expanded by cascading.

Supply Voltage
Input Voltage

Input buffers are provided so that each data input represents only one normalized series 54/74 load. A full fan-out
"to 10 normalized series 54/74 loads is available from each
of the outputs at a low logic level. A fan-out to 20 normalized loads is provided "at a high iogic level to facilitate the
connection of unused inputs to used inputs.

(Note 1)

7V
S.SV

- 6S·C to 1S0·C

Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

"Connection Diagram

Dual·ln-Line Package
INPUTS

vr

E

F

14

13

0

12

11

10

Inputa

A'

B

C

8

9

-

-

Outputs

l: of H's at
l:
l:
Even Odd
Even Odd
A thru H
Even

H

L

H

'L

Odd

H

L

L

H

Even

L

H

L

H

Odd

L

H

H

L

X

H

H

L

L

X

L

L

H

H

H --= High Level, L • Low Level, X • Don't Care

G

.

INPUTS

2
H,

3
EVEN
INPUT

4
ODD
INPUT

5

17 "

6

l:-EVEN l:-oDO
OUTPUT OUTPUT

GNO

TLIFI6559-1

54180 (J)

74180(N)

6-242

c

s:

Recommended Operating Conditions

(II
~

.....

DM74180

DM54180
Symbol

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units
V
V

2

-55

0.8

0.8

-0.8

-0.8

mA

16

16

mA

70

·C

125

0

V

over recommended operating free air temperature (unless otherwise noted)

Parameter

Conditions

Min

Typ
(Note 1)

Max
-1.5

Units

VI

Input Clamp Voltage

Vee = Min, ,1= -12 mA

VOH

High Level Output
Voltage

Vee = Min, 10H= Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee = Min, 10L= Max
VIH = Min, VIL = Max

0.4

V

II

Input Current@Max
Input Voltage

Vee = Max, VI=5.5V

1

mA

IIH

High Level Input
Current

Vee= Max
VI=2.4V

Odd or Even

80

p.A

Data

40

,Low Level Input
Current

Vee = Max
VI = 0.4V

Odd or Even

-3.2

Data

-1.6

Short Circuit
Output Current

Vee= Max,
(Note 2)

DM54

-20

-55

DM74

-18

-55

Supply Current

Vee = Max
(Note 3)

IlL

los

Icc

~
C
s:

:i::!
.....
CO

o

Electrical Characteristics
Symbol

Min

DM54

34

49

DM74

34

56

Nole': All typlcals are at Vee= 5V, TA=25'e,
Nole 2: Not more than one output should be shorted at a time.
Note 3: ICC Is measured with EVEN and ODD inputs at 4,5V, all other inputs and outputs open,

6·243

V
V

2.4

mA

mA

mA

Switching Characteristics

at Vee = 5V and To4 = 25"C (See Section 1 for Test Waveforms and Output Load)

From
(Input)
To
(Output)

Conditions

tpLH Propagation Delay
Time Low to High
Level Output

Data
to
E Even

CL= 15 pF
RL=4001l
Odd Input Low

tpHL Propagation Delay
Time High to Low
Level Output

Parameter

Typ

Max

Units

40

60

ns

Data
to
E Even

45

68

ns

tpLH Propagation Delay
Time Low to High
Level Output

Data
to
E Odd

32

48

ns

tpHL Propagation Delay
Time High to Low
Level Output

Data
to
EOdd

25

38

ns

tpLH Propagation Delay
Time Low to High
Level Output

Data
to
E Even

32

48

ns

Data
to
E Even

25

38

ns

tpLH Propagation Delay
Time Low to High
Level Output

. Data
to
E Odd

40

60

ns

tpHL Propagation Delay
Time High to Low
Level Output

Data
to
EOdd

45

68

ns

tpLH Propagation Delay
Time Low to High
Level Output

Even or Odd
to E Even
or E Odd

13

20

ns

tpHL Propagation Delay
Time High to Low
. Level Output

Even or Odd
to E Even
or E Odd

7

10

ns

,

tpHL Propagation Delay
Time High to Low
Level Output

.i

CL= 15 pF
RL=4001l
Odd Input High

Min

.:

CL= 15 pF
RL=4001l

Logic Diagram

'b~

J

B (9)

(10)

~~
DATA
INPUTS

(12)

:ll!t)~
:E)

(5) ~ EVEN
OUTPUT

~[> ~ I-i

~~

(1)

ODD (4)
INPUT
EVEN (3)
INPUT

TL/F16559-2

6·244

.-------------------------------------------------------------,0
:s:
U1
~National

~
.....

~ Semiconductor
DM54181/DM74181
Arithmetic Logic Unitl Function Generators

co
.....

-:s:
o

~
.....
CO
.....

General Description

Features

These arithmetic logic units (ALU)Jfunction generators
perform 16 binary arithmetic operations on two 4-bit
words, as shown in Tables I and II. These operations are
selected by the four function-select lines (SO, 51, 52, 53)
and include addition, subtraction, decrement, and straight
transfer. When performing arithmetic manipulations, the
internal carries must be enabled by applying a lOW-level
voltage to the mode control input (M). A full carry lookahead scheme is available in these devices for fast,
simultaneous carry generation by means of two cascadeoutputs (p and G) for the four bits in the package. When
used in conjunction with the DM54S182/DM74S182 full
carry look-ahead circuits, high-speed arithmetic operations can be performed. The typical addition times shown
below illustrate how little time is required for addition of
'longer words, when full carry look-ahead is employed. The
method of cascading 182 circuits with these ALU's to provide multi-level full carry look-ahead is illustrated under
typical applications data for the DM54S182/DM74S182.
(Continued)

• Arithmetic operating modes:
Addition
Subtraction
Shift operand A one position
Magnitude comparison
Plus twelve other arithmetic operations
• Logic function modes:
EXCLUSIVE-OR
Comparator
AND, NAND, OR, NOR
Plus ten other logic operations
• Full look-ahead for high-speed operations on long words

Absolute Maximum Ratings

(Note 1)
7V

Supply Voltage

5.5V

Input Voltage
Output Voltage (A = B Output)
Storage Temperature Range

5.5V
-65·Ct0150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond

which the salety 01 the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions tor actual device operation.

Connection Diagram

Pin Designations

Dual-In-Line Package
OUTPUTS

INPUTS
Vee 'A1

124

23

2

81

A2
22

3

82
21

4

20

5

A3 83'
19

6

80 ____________
AO 53 52 51 SO

~

G Cn+4 P A=B F3'

18

17

7

en

8
M

~--J'

INPUTS

16

9
FO

15

14

10
F1

13

11 J12
F2 GND

~

Pin Nos.

Function

19,21,23, 2

Word A Inputs

B3, B2, Bl, BO

18,20,22, 1

Word B Inputs

53,52,51, SO

3,4,5,6

Function-Select
Inputs

Cn

7

Inv. Carry Input

M

8

Mode Control
Input

F3,F2,Fl,FO

13, II, 10,9

A=B

14

Comparator Output

P

15

Carry Propagate
Output

Cn+4

16

Inv. Carry Output

G

17

Carry Generate
Output

VCC

24

Supply Voltage

GND

12

Ground

OUTPUTS

TLIFI6560·1

54181 (J)

Designation
A3, A2, AI, AO

74181 (N)

Package Count

Number
of
Bits

Typlca'
AddlUon l'lmes

1 to 4
5 to 8
9 to 16
17 to 64

20 n"
30 PS
30 r,s
50 ns

Arlthmetlc/
Look Ahead
Logic Units Carry Generators
1
2
30r4
5 to 16

0
0
2 to 5
6-245

. Function Outputs

Carry Method
Between
ALU's
None
Ripple
Full Look-Ahead
Full Look-Ahead

~

....

ClO

~
:E

-

Q

~

ClO
~

;7;
:E
Q

,------------------------------------------------------------------------------------------,
General Description

(Continued)

If high speed is not important, a ripple-carry input (C n) and
a ripple-carry output (C n+4) are available. However, the
ripple-carry delay has also been minimized so that
arithmetic manipulations for small word lengths can be performed without external circuitry.

magnitude information. Again, the ALU should be placed in
the subtract mode by placing the function select inputs 53,
52,51, SO at L,.H, H, l, respectively.
These circuits have been designed to not only incorporate
all of the designer's requirements for arithmetic operations,
but also to provide 18 possible functions of two Boolean
variables without the use of external circuitry. These logic
functions are selected by use of the four function-select inputs (SO, 51, 52, 53) with the mode-control input (M) at a
high level to disable the internal carry. The 16 logic functions are detailed in Tables 1 and 2 and include exclusiveOR, NAND, AND, NOR, and OR functions ..

These circuits will accommodate active-high or active-low
data, if the pin designations are interpreted as shown
below.
Subtraction is accomplished by l's complement addition
where the l's complement of the subtrahend is generated
internally. The resultant output is A-B-l, which requires
an end-around or forced carry to prov,ide A-B.
The 181 can also be utilized as a comparator. The A = B
output is internally decoded from the function outputs (FO,
F 1, F2, F3) so that when two words of equal magnitude are
applied at the A and B·inputs, it will assume a high level to
indicate equality (A = B). The ALU should be in the subtract
mode with Cn = H when performing this comparison. The
A = B output is open-collector so that it can be wire-AND
connected to give a comparison for more than four bits. The
carry output (C n+4) can also be used to supply relative

Pin Number

2

1

. AlU SIGNAL DESIGNATIONS
The DM54181/DM74181 can be used with the signal deSignations of either Figure 1 or Figure 2.
The logic functions and arithmetic operations obtained
with signal deSignations as in Figure 1 are given in Table I;
those obtained with the signal deSignations of Figure 2
are given In Table II.
'

23 22 21 20 19 18

9

10 11 13

7

16

15 17

Active-High Data (Table I)

AO BO Al Bl A2 B2 A3 B3 FO Fl F2 F3 Cn Cn+4 X

V

Active-Low Data (Table II)

AO BO Al Bl A2 B2 A3 B3 FO Fl F2 F3 Cn Cn+4 P

G

Input
Cn

Output
Cn+4

H
H
L

H
L
H
L

~

Actlve-Hi9h Data Active-Low Data
(Figure 1)
(Figure 2)
AsB
A>B
AB
ASB

General Description

!7l-r<

O
TT Irly'
., 'rl(i ) er'Cr)
81

AD BO
Cn

A2 82

.8.
18,-

r-

(Continued)

M
FO

F.

It (1t
113 '1 14 '
YO XO

A=8 -1'4,

F2

F3

Il,)

ut ,l,

Cn+4

Y

x

1(1+,5,

TTT'T' TT
Y1

Y2 X2

x.

V3 X3

x-17,

I'~

5182

Cn

Table I

A3 B3

Y-(10,

C n+ x

Cn +y

Cn+ z

,II

Il,

J.
TLIF16560·2

Figure 1

Active High Data '
M = L; Arithmetic Operations

Selection

M=H
Logic
S3 S2 S1 SO Functions

Cn = L (with carry)

Cn = H (no carry)
F
'F
F
F
F
F

=
=
=
=
=
=

APius

1
(A + B) Plus 1
(A + S) Plus 1
Zero
A Plus AS Pius 1
(A + B) Plus AS Plus 1

L
H
L
H
L
H

F=A
F=A+B
F =AB
F=O
F = AB
F=S

H

L

F=AEaB F = A Minus B Minus 1

H
L

F = AS Minus 1
H F = AB
L F=A+B F = A Plus AB

F = AS
F = A Plus AB Plus 1

L

H F=AEaB F = A Plus B

F = A Plus B Plus 1

H
H
L
L
H
H

L
H
L
H
L
H

L
L
L
L
L
L

L
L
L
L
H
H

L
L
H
H
L
L

L

H

L
H
H

H
L
L

H
H
H
H
H
H

L
L
H
H
H
H

F=A
F=A+B
F=A+S
F = Minus 1 (2's CampI)
F = A Plus AS
F = (A + B) Plus AS

-

F=B
F = AB
F= 1
F=A+S
F=A+B
F=A

F
F
F
F
F
F

=
=
=
=
=
=

(~+ S) Phis AB
AB Minus 1
A Plus A'
(A + B) Plus A
(A + S) Plus A
A Minus 1

F = A Minus B

F = (A + S) Plus AB Plus 1
F = AB
F = A Plus A Plus 1
F = (A + B) Plus A Plus 1
F = (A + S) Plus A Plus 1
F=A

• Each bit is shifted to the next more significant position.

TT I!, II'
17'~>-

AO DO

cn

11,'

A. 81

Ir It

A2

F.

F2

A3

F3 Cn+4

G

P

cr, Ir, IX' Ir, J.) l.+s,
TTT'T' !!
13t',

GO PO

G1 P1

G2 P,

G3 P3

PP-17'

I~

Cn

5182

Cn+x

cn+.

Cn+z

(11.

)"

I!.

Gp-Il0)

TUFI656Q.3

Figure 2

Active Low Data

B3

A=8 1--1.4,

.8.
18,- - M
FO

Table II

11,'

8.

Selection

M=H
Logic
S3 S2 S1 SO Functions
L
L
L
L
L
L

L
L
L
L
H
H

L
L
H
H
L
L

L

H

L
H

H
L

H

L

H
H
H
H
H
H

L
L
H
H
H
H

L H
H -L
H H
L L
L H
H L
H H

M = L; Arithmeti,c Operations
Cn = L (no carry)
F
F
F
F
F
F

=
=
=
=
=
=

A Minus 1
AB Minus 1
AS Minus 1
Minus 1 (2's CampI)
A Plus (A + S)
AB Plus (A + B)

L
H
L
H
L
H

F=A
F = AB
F=A+B
F= 1
F=A+B
F=S

H

L

F=

H
L

H F=A+S F=A+S
F = A Plus (A + B)
L F=AB

'A"EBB

F = A Minus B Minus 1

F=AEaB F = A Plus B
F=B
F=A+B
F=O
F = AS
F = AB
F=A

F = AS Plus (A + B)
F=A+B
F = A Plus A'
F = AB Plus A
F = ABPhis A
F=A

• Each bit is shifted to the next more significant position.

6·247

Cn = H (with carry)
F=A
F = AB
F = AS
F = Zero
F = A Plus (A + S) Plus 1
F = AB Plus (A + S) Plus 1
F:: A Minus B
F = (A + S) Plus 1
F = A Plus (A + B) Plus 1
F = A Plus B Plus 1
F
F
F
F
F
F

=
=
=
=
=
=

AS Plus (A + B) Plus 1
(A + B) Plus 1
A Plus A Plus 1
AB Plus A Plus 1
AS Plus A Plus 1
APluB 1

....
co
....

t!

Recommended Opera~ing Conditions

:E

-........
c

Symbol

co

~
:E

Parameter

\.

DM74181

DM54181
Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units
V

Vcc

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level Input
Voltage

0.8

0.8

V

VOH

High Level Output
Voltage (A = B Output)

5.5

5.5

V

10H

High Level Output
Current (All except A = B)

-800

-800

/LA

IOl

Low Level Output
Current

16

16

mA

TA

Free ~ir Operating
Temperature

70

·C

c

V

2

2

125

-55

0

Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol

Parameter

Conditions

Min

Typ
(Note 1)

Max

Units

-1.5

V

250

/LA

VI

Input Clamp Voltage

Vcc=Min, 11= -12 mA

ICEX

High Level Output
Current (A = B Output)

Vcc=Min, V o =5.5V
Vil = Max, V IH = Min

VOH

High Level Output
Voltage (All except A = B)

VOL

Low Level Output
Voltage

Vcc = Min, 10l = Max
VIH = Min, VIL = Max

0.4

V

II

Input Current@Max
Input Voltage

Vcc=Max, VI =5.5V

1

mA

IIH

High Level Input
Current

Vcc=Max
VI=2.4V

Mode

40

/LA

A or B

120

2.4

I

IlL

Low Level Input
Current

Vcc=Max
V I =0.4V

V

S

160

Carry

200·

Mode

-1.6

Aor B

-4.8

S

-6.4

Carry
los
Icct

ICC2

Nolel:
Nole 2:
Nole 3:
Nole 4:

-8

Vcc=Max
(Note 2)

DM54

-20

-55

DM74

-18

-57

Supply Current With
Outputs High

Vcc=Max
(Note 3)

DM54

88

127

DM74

88

140

Supply Current With
Outputs Low

Vcc=Max
(Note 4)

DM54

92

135

DM74

92

150

Short Circuit Output
Current (All except A = B)

All iyplcals are at VCC=5V, TA=2S"C.
Not more than one output should be shorted at a time.
ICCt Is measured with SO througli S3, M, and A Inputs at 4.SV, all other Inputs grounded, and all outputs ope~.
ICC2 Is measured with 50 through S3 and M inputs at 4.SV. all other Inputs grounded and all outputs open.

6·248

mA

mA

mA

mA

c

Switching Characteristics

VCC = 5 V, TA = 25°C

s:
C1I

(See Section 1 for Test Waveforms and Output Load)

~
.....
.....

DM54174
181
Symbol

Parameter

From
(Input)

To
(Output)

Conditions

RL

=400 Il, CL = 15 pF

Min
tpLH

Propagation Delay Time,
Low-to-High Level Output

tPHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
low-to-High level Output

tPHl

Propagation Delay Time,
High-to-low level Output

tplH

Propagation Delay Time,
low-to-High level Output

tPHl

Propagation Delay Time,
High-to-low Level Output

tPlH

Propagation Delay Time,
Low-to-High level Output

tPHl

Propagation Delay Time,
High-to-Low level Output

tPlH

Propagation Delay Time,
low-to-High level Output

tpHl

Propagation Delay Time,
High-to-low level Output

tPlH

Propagation Delay Time,
low-to-High level Output

tPHl

Propagation Delay Time,
High-to-low level Output

tplH

Propagation Delay Time,
Low-to-High Level Output

tpHl

Propagation Delay Time,
High-to-Low Level Output

tplH

Propagation Delay Time,
Low-to-High level Output

tPHl

Propa,gation Delay Time,
High-to-low level Output

tpLH

Propagation Delay Time,
Low-to-High level Output

tPHl

Propagation Delay Time,
High-to-Low level Output

tPlH

Propagation Delay Time,
Low-to-High Level Output

tpHl

Propagation Delay Time,
High-to-low level Output

tplH

Propagation Delay Time,
low-to-High level Output

tPHL

Propagation Delay Time,
High-to-low level Output

tplH

Propagation Delay Time,
low-to-High level Output

tPHl

Propagation Delay Time,
High-to-Low Level Output

Cn

Cn+4

Any A
orB

Cn+4

Cn

Any F

Any A
or B

G

Any A
or B

G

Any A
or B

P

Any A
or.B

P

Ai orBi

Fi

Ai orBi

Ai

OF

Typ

Max

g

18

Bi

Any A
or B

Fi

Fi

A=B

6-249

Units

13

19

M = 0 V, 50 =
53 = 4.5 V
51 =52=OV
(5UM mode)

20

30

22

33

M = OV, 50 =
53 = OV
51 = 52 = 4.5 V
(DIFF mode)

20

30

22

33

M =OV

~
.....

.....

11

19

DIFF mode)

12

18

M = OV, 50 =
53:' 4.5 V
51 = 52 = 0 V
(5UM mode)

13

19

14

19

M=OV,50=
53 = 0 V
51 = 52 = 4.5 V
(DIFF mode)

12

20

15

25

12

19

17

25

14

25

17

25

M = OV, 50 =
53 = 4.5 V
51 = 52 =,OV
(5UM mode)

18

30

19

30

M = OV, 50 =
53 = 0 V
51 = 52 = 4.5 V
(DIFF mode)

14

24

14

24

17

'28

19

30

26

40

25

40

ns

ns

ns

(5UM or

M=OV,50=
53 = 4.5 V
51 =52=OV
(5UM mode)
M = OV, 50 =
53 = OV
51 = 52 = 4.5 V
(DIFF 'mode)

M = 4.5 V
(logiC mode)

M = OV, 50 =
53 = OV
51 = 52 = 4.5 V
(DIFF mode)

C

CO

ns

Cn+4

Any A
orB

-s:
CO

ns

ns

ns

ns

ns.

ns

ns

ns

~~~----------------~----------------------------------------------~

co
~

t!

Logic Diagram'

:!

c

~

co
~

~

II)

:!

c

(3)

S3
(4)
S2
(5)
Sl

so

83

,

(6)

-~

(18)

A3

(19)

82

~20)

~

~

~

(17)

~

-

~

V

I

-

o'Y

(16) C n

l~ n
J

G

(15)

rI

(13)

P or X

F3

(21)

81 (22)

r¢

~~

V

(11)

F2

A=B
(14)

1
(23)

80 (1)

~

jr
, ......

~

~..

()o)

Fl

~.

to

°
M;ri>

~

(9)

FO

(2)
(8)

cn

Vce
GND

(7)

=PIN 24
=PIN 12

TL/F/B56()'4

6-250

c

s::

Parameter Measurement Information

....CO~
....

Logic Mode Test Table
Function Inputs: S1
S2 M 4.5 V, 50 = 53

=

Parameter

IpLH
IpHL
IpLH
IpHL

Input
Under
Test

Other Input
Same Bit

-s::
C

= =

=0 V

Other Data Inputs

Output
Under
Test

Output
Waveform

"....

.j:o.

Apply
4.5 V

Apply
GND

Apply
4.5 V

Apply
GND.

Ai

Bi

None

None

Remaining
Aand B, Cn

Fi

Oul·ol·Phase

Bi

Ai.

None

None

Remaining
AandB,C n

Fi

Oul·ol·Phase

SUM Mode Test Table
Function Inputs: SO

Parameter

IpLH
IPHL
IPLH
IpHL
IpLH
IpHL
IPLH

Input
Under
Test

= S3 = 4.5 V, S1 = 52 = M = 0 V

Other Input
Same Bit

Other Data Inputs

Output
Under
Test

Output
Waveform

Cn

Fi

In·Phase

Remaining
A and B

Cn

Fi

In·Phase

None

None

Remaining
AandB, Cn

P

In· Phase

Ai

None

None

Remaining
Aand B, Cn

P

In·Phase

Ai

None

Bi

Remaining Remaining
B
A,C n

G

In·Phase

'8i

None

Ai

Remaining Remaining
A,C n
B

G

In·Phase

Cn

None

None

Any F
or Cn+4

In-Phase

Ai

None

Bi

Remaining Remaining
A,C n
B

Cn+4

Oul-ol-Phase

Bi

None

Ai

Remaining Remaining
A,C n
B

Cn+4

OUI-ol-Phase

Apply
4.5V

Apply
GND

Apply
4.5 V

Apply
GND

Ai

Bi

None

Remaining
A and B

Bi

Ai

None

Ai

Bi

Bi

IPHL
IpLH
IpHL
IPLH
IPHL
tpLH
IpHL
tpLH
IpHL
IPLH
IpHL

All
A

6·251

All
B

CO
....

~ r---------------------------------------------~------------------------------------------_,

00
~

~
:E

Parameter Measurement Information

-c

DiFF Mode Test Table
FunctIon Inputs: S1 = S2 = 4.5 V. SO = S3 = M = 0 V

~

00
~

;:g
:E

c

(Continued)

Parameter

tPLHtpHL
tPLH
tPHL
tPLH

Input
Under
Test

Other Input
Same BIt

Other Data Inputs
Apply
4.5 V

tpLH
tpHL
tPLH
tpHL
tpLH

Apply
GND

Ai

None

Bi

Remaining Remaining
A
B,Cn

Fi

In-Phase

Bi

Ai

None

Remaining Remaining
B,Cn
A

Fi

Out-ol-Phase

Ai

None

Bi

None

Remaining
AandB,C n

P

In-Phase

Bi

Ai

None

None

Remaining
AandB,C n

P

Out-ol-Phase

Ai

Bi

None

None

Remaining
AandB, Cn

G

In· Phase

Bi

None

Ai

None

Remaining
AandB,Cn

G

Out-ol-Phase

Ai

None

Bi

Remaining Remaining
A
B,C n

A=B

In· Phase

Bi

Ai

None

Remaining Remaining
B,C n
A

A=B

Out-ol·Phase

Cn

None

None

All
A and B

None

Cn+4
or any F

In-Phase

Ai

Bi

None

None

Remaining
A,B,C n

Cn+4

Out-ol-Phase

Bi

None

Ai

None

Remaining
A,B,C n

Cn+4

In·Phase

tPHL
tPLH
tPHL
tpLH
tPHL
tPLH
tpHL
tPLH
tpHL
tPLH
tPHL

Output
Waveform

Apply
4.5 V

tPHL

6-252

Apply
GND

Output
Under
Test

.----------------------------------------------------------,0
s:
en
~National

....""

~ Semiconductor

CO

~
C

s:
~
....
CO

DM541841 DM74184, DM54185AI DM74185A
BCD-to Binary and Binary-to-BCD Converters

~""
C

s:

General Description
These monolithic converters are derived from the 256-bit
read only memories, DM5488 snd DM7488. Emitter connections are made to provide direct resd-out of converted
codes at outputs YB through Y1, as shown in the function
tables. These converters demonstrate the versatility of a
read only memory in that an unlimited number of reference
tables or conversion tables may be built into a system. Both
of these converters comprehend that the least significant
bits (LSB) of the binary and BCD codes are logically equal,
and in each case the LSB bypasses the converter as
ilustrated in the typical applications. This means that a 6bit converter is produced in each case. Both devices are
cascadable to N bits.

ment or BCD 10's complement. Again, in each case, one
bit of the complement code is logically equal to one of the
BCD bits; therefore, these complements can be produced
on three lines. As outputs Y6, V7 and YB are not required In
the BCD-to-binary conversion, they are utilized to provide
these· complement codes as specified In the function
table when the devices are connected as shown.

The function performed by these 6-bit binary-to-BCD converters is analogous to the algorithm:
a. Examine the three most significant bits. II the sum is
greater than four, add three and shift left one bit.
b. Examine each BCD decade. II the sum is greater than
four, add three and shift left one bit.
c. Repeat step b until the least-significant binary bit is in
the least-significant BCD location.
(Continued)

b. Shift right, examine, and correct after each shiftCLOCK

~

L .....

L-

f-KC~ROA~

- J->

DATA (1)
INPUT B

J

b

~H=
~

DATA (10)
INPUTC

-J
~

-

PRESET ---4~ 0
OB
UTPUTOB

CLOCK
KCLEAROBh

-y

.1"P

~

J

....

DATA (9)
INPUT D

P

~

).,

r

L

~

_J

PRESET ---4~
Oc
OUTPUTOC

~ CLOCK

I-

KCL.~rOCJ

J Y

~ TI~'TJ
~HJ

PRESET ~ OUTPUTOD
OD

L.cl> CLOCK

LOAD

Pin (16)

(11)

= Vee.

Pin (8)= GND

.

TLlFI6562·2

6·262

r---------------------------------------------------------------,c
:s:
Logic Diagrams (Continued)

...~

U)

-:s:
o
c

191 Binary Counter

...
~

0l=Io

CD

CLOCK (14)

P

c

DOWNI (5)
UP

(13) RIPPLE

. r ""

=B

IV::J'~lP-

~ CLOCK
(12) MAXIMIN
)---+--+--.....---....;.......;.
OUTPUT

DMA(1-51)11!---------t1-t1lt1-tt-r-~~------_4--~---,
~
J.-/,
b
(4)

ENABLE G

I 'L..---..
L....d )-

PRESET t--OA

~

~ CLOCK

Y

I

~TA..:.(l~)-------tlrti_tlrtlrtlrt-r-;p------__----4_----~

NPUTB

f

r

~

.....H-t--t-+-+-H-+-L~

).-1-.....

n

I--

b

J PRESEJB ---< ~OUTPUT OB

~ CLOCK

LI--

KCLEAROB

Y

DATA:..(l~O~)---_tt_t1-t-rt-t1_tt_~~>_--_e---~-~
r ) . ,

NPUTC

,r
~>-1--......
.....-+-+-+-+-H-f-H--'
'-r>L-

.--- J

PRESET
'
(6)
0Ct---p-OUTPUTOC

' V' ' 1

~ CLOCK

(11)

LOAD

Pin (16)

= Vee. Pin (8) = GNO
TLIF16562,3

6-263

-:s:
CD

~
......
CD

OUTPUT OA

'--t-- KCLEAROAtl

-

......~
c

INPUT A

...-+--1 J

:s:

T-

r---------~----------------------------------------------------------------~----------------------_,

en
T-

t:!

Timing Diag·rams

:E

c

190 ·Decade Counter
Typical Load, ,?ount, and Inhibit Sequences

T-

en
T-

"I:t

It)

LOAD

:E

c

g
T-

I..!:J

A
DATA [ B
INPUTS

:

....:.

t:!

:E

c

o
en
T-

CLOCK
DOWN/UP
ENABLE

~
:E
c

RIPPLE CLOCK - _ ...
1 -+~--..,
--'
17
8
9
0 1 22210987
I I I - COUNT UP
I INHIBIT II-COUNT DOWN--I

-----

LOAD

Sequence:
(1) Load (preset) to BCD seven
(2) Count up to eight, nine, zero, one, Bnd two
(3) Inhibit
..

TLtF/6562·4

(4) Count down to one, zero, nine. eight, and seven

191 Decade Counter
Typical Load, Count, and Inhibit Sequences
LOAD~--------------------------------

DATA [ :
INPUTS :

CLOCK
DOWN/UP
ENABLE

RIPPLE CLOCK - - ...
1 -H--_, r-----+-----+-+----.Lr------

- 113

14 15 0
1 2
'2
2 1
0
15 14 13
lJl-COUNT UP
IINHIBrr II-COUNT DOWN--I
LOAD
TlIF/6562·5

Sequence:
(1) Load (preset) to binary thirteen

(2) Count up to fourteen, fifteen. zero, on., and two
(3) Inhibit
.
(4) Count down to one, zero, filtaen. fourteen, and thirteen

6-264

r------------------------------------------------------------------,c

3:

~National

U1

....CDoIlo

~ Semiconductor

N

c
3:

DM54192/DM74192, DM54193/DM74193
Synchronous Up/Down Counters with Dual Clock

~
....

CD

J"I

c

General Description
width to the count down input when the counter underflows.
Similarly, the carry output produces a pulse equal in width
to the count down input when an overflow condition exists.
The counters can then be easily cascaded by feeding the
borrow and carry outputs to the count down and count up
inputs respectively of the succeeding counter.

These circuits are synchronous up/down counters; the
192 circuit is a BCD counter and the 193 is a 4·bit binary
counter. Synchronous operation is provided by having all
flip·flops clocked simultaneously so that the outputs
change together when so Instructed by the steering logic.
This mode of operation eliminates the output counting
spikes normally associated with asynchronous (ripple·
clock) counters.

•
•
•
•
•
•

All four counters are fully programmable; that is, each out·
put may be preset to either level by entering the desired
data at the inputs while the load input is low. The output will
change independently of the count pulses. This feature al·
lows the counters to be used as modulo·N dividers by sim·
ply modifying the count length with the preset inputs.

Fully independent clear input
Synchronous operation
Cascading circuitry provided internally
Individual preset each flip·flop
Typical count frequency 25 MHz
Typical power dissipation 325 mW

Absolute Maximum Ratings

A clear input has been provided which, when taken to a high
level, forces all outputs to the low level; independent of the
count and load inputs. The clear, count, and load inputs are
buffered to lower the drive requirements of clock drivers,
etc., required for long words.

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

7V
5.5V
- 65"C to 150"C

Not. 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table BfB not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

These counters were designed to be cascaded without the
need for external circuitry. Both borrow and carry outputs
are available to cascade both the up and down counting
functions. The borrow output produces a pulse equal in

Connection Diagram
Dual·in·Line Package
INPUTS
'vCC

D~A

116

OUTPUTS

INPUTS

CLEAR BORROW CARRY LOAD

14

15

13

12

11

D~A

DAriA

10

9

-

2
DATAS
INPUT

Os

3

OA

OUTPUTS

4

5

6

COUNT COUNT
DOWN
UP

aS

7
OD

. IS
GND

OUTPUTS

INPUTS

Note: Low input to load sets QA = A,

Oc

TL/F/6563-1

= B. QC = C, and

6·265

CD

Co)

c
3:

....
....
CD
oIlo

Co)

Features

The outputs of the four master· slave flip·flops are triggered
by a low·to·high level transition of either count (clock) in·
put. The direction of counting is determined by which count
input is pulsed, while the other count input is held high.

3:
~
....

aD = D.

54192 (J)
54193 (J)

74192 (N)
74193 (N)

Recommended Operating Conditions
Sym
Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

DM74192

DM54192

Parameter

Min

Nom

Max

Min

Nom

Max

4.5

5

'5.5

4.75

5

5.25

2

Units
V
V

2
0.8

0.8

High Level Output
Current

-0.4

-0.4

mA

10L

Low Level Output
Current

16

16

mA

feLK

Clock Frequency

20

MHz

tw

Pulse Width

25

0

20

0

Clock Low

30

30

Clock, Clear High
load Low

20

20

tsu

Data Setup Time

20

20

tH

Hold Time

0

0

TA

Free Air Operating
Temperature

-55

125

25

V

ns

ns
ns
70

0

·C

'192 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)'
Sym

Parameter

Min

Conditions

VI

Input Clamp Voltage

Vcc = Min, II = -12 mA,

VOH

High Level Output
Voltage

Vcc=Min,loH=Max
V IL ='Max, VIH = Min

VOL

Low Level Output
Voltage

Vee = Min, 10L = Max
VIH = Min, VIL = Max

II

Input Current@Max
Input Voltage

IIH

Typ
(Note 1)

Max
-1.5

Units
V
V

2.4
0.4

V

Vcc = Max, VI = 5.5V

1

mA

High Level Input
Current

Vcc=Max, VI=2.4V

40

p.A

IlL

Low Level Input
Current

Vcc=Max, VI =O.4V

-1.6

mA

los

Short Circuit
Output Current

Vcc= Max
(Note 2)

DM54

-20

-,55

mA

DM74

-18

-55

Supply Current

Vcc=Max
(Note 3)

DM54

65

89

DM74

65

102

Icc

"

Notet: All typicals are at VCC=5V, TA=25'C,
Note 2: Not more than one output should be shorted at a time.

Note 3: ICC is measured with all outputs open, CLEAR and

~OAD

inputs grounded, and all other inputs at 4.5V.

-

6·266

mAo

c
:s:
.....

'192 Switching Characteristics

at Vcc=5V and TA=25°C
(See Section 1 for Test Waveforms and Output Load)

Parameter

U1

.j:Io

U)
I\)

From
(Input)
To
(Output)

Units

-:s:c

MHz

j')

ns

:s:
U1

ns

-

RL =400n
CL =15 pF

f MAX Maximum Clock
Frequency

Min

Typ

20

25

Max

~

U)

c

tpLH Propagation Delay
Time Low to High
Level Output

Count
Up to
Carry

17

26

tpHL Propagation Delay
Time High to Low
Level Output

Count
Up to
Carry

16

tpLH Propagation Delay
Time Low to High
Level Output

Count
Down to
Borrow

16

tpHL Propagation Delay
Time High to Low
Level Output

Count
Down to
Borrow

16

24

ns

tpLH Propagation Delay
Time Low to High
Level Output

Count
to

25

38

ns

tpHL Propagation Delay
Time High to Low
Level Output

Count
to

31

47

ns

tpLH Propagation Delay
Time Low to High
Level Output

Load
to

27

40

ns

tpHL Propagation Delay
Time High to Low
Level Output

Load
to

29

40

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to

22

35

ns

.j:Io
.....

U)

24

24

ns

Co)

c

:s:
~
.....
U)

Co)

Q

Q

Q

Q

Q

6·267

Recommended Operating Conditions
DM74193

DM54193
Sym

Parameter

Vcc

Supply Voltage

V IH

High Level Input
Voltage

Vil

Low Level Input
Voltage

IOH
IOl

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

.5

5.25

Units
V
V

2

2
0.8

0.8

High Level Output
Current

-0.4

-0.4

mA

Low Level Output
Current

16

16

mA

20

MHz

fClK Clock Frequency
tw

Min

Pulse Width

25

0

20

0

Clock Low

30

30

Clock, Clear High
Load Low

20

20

tsu

Data Setup Time

20

20

tH

Hold Time

0

0

TA

Free Air Operating
Temperature

-55

125

25

V

ns

ns
ns

0

·C

70

'193 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Sym

Parameter

Conditions

Min

Typ
(Note 1)

Max

VI

Input Clamp Voltage

Vcc= Min, II = -12 mA

VOH

High Level Output
Voltage

Vcc = Min, IOH = Max
Vil = Max, VIH = Min

VOL

Low Level Output
Voltage

Vcc=Min,loL=Max
VIH = Min, Vil = Max

0.4

V

II

Input Current@Max
Input yoltage

Vcc = Max, VI = 5.5V

1

mA

IIH

High Level Input
Current

Vcc=Max, VI=2.4V

40

p.A

III

Low Level Input
Current

Vcc=Max, VI =0.4V

-1.6

mA

los

Short Circuit
Output Current

Vcc=Max
(Note 2)

DM54

-20

-55

mA

DM74

-18

-55

Supply Current

Vcc=Max
(Note 3)

DM54

65

89

DM74

65

102

Icc

-1.5

Units

2.4

Not. 1: All typicals are at Vcc=sv, TA=2S"C.
Note 2: Not more than one output should be shorted at a time.

Note 3: ICC Is measured with all outputs open, CLEAR and lOAD inputs grounded, and all other inputs at 4.SV.

6·268

V
V

mA

'193 Switching Characteristics at Vcc=5V and TA =25"C
(See Section 1 for Test Waveforms and Output Load)
From
(Input)
To
(Output)

Parameter

RL =400[l
CL=15 pF

f MAX Maximum Clock
Frequency
tpLH Propagation Delay
Time Low to High
Level Output

"

Min

Typ

20

25

Units
Max
MHz

Count
Up to
Carry

17

26

ns

tpHL Propagation Delay
Time High to Low
Level Output

Count
Up to
Carry

16

24

ns

tpLH Propagation Delay
Time Low to High
Level Output

Count
Down to
Borrow

16

24

ns

tpHL Propagation Delay
Time High to Low
Level Output

Count
Down to
Borrow

16

24

ns

tpLH Propagation Delay
Time Low to High
Level Output

Either
Count to

25

38

ns

tpHL Propagation Delay
Time High to Low
Level Output

Either
Count to

31

47

ns

t pLH Propagation Delay
Time Low to High
Level Output

Load
to

27

40

ns

tpHL Propagation Delay
Time High to Low
Level Output

Load
to

29

40

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to

22

35

'ns

j

Q

Q

Q

Q

Q

,

6·269

Logic Diagrams
192

(13) B ORROW
0 UTPUT
(12) C ARRY
0 UTPUT

..r--

r
DATA
INPUT A

(15)

DOWN
COUNT

(4)

r--r

~

(3)

OA

0 UTPUT OA

T
UP
COUNT

~

-

DATA
INPUT B

r--r

~»-

,L

(2)

OB

OUTPUT OB

T
OB

:r--P

r-

6-J

(10)

r--r

1-

~

(6)

Oc

OUTPUT Oc

T
Oc

L..-rp

-

OATA
INPUT 0

lDT

(1)

~
DATA
INPUT C

r-

OA

(5)

r-

tnT

(9)

(14)
CLEA R

r--'
L-t:::::::I
(7)

00
T

00

(11
LOA 0

~

OUTPUT

00

r-

~
TLIF/6563-2

6-270

c

Logic Diagrams

:!:':
(J1

(Continued)

....
~

CO

193

I\)

c

:!:':

(13)

BORROW
OUTPUT

......

....
CO
~

~I\)
(12)

CARRY
OUTPUT

DATA (15)
INPUT A

....
~

~

r-'

DOWN (4)
COUNT

(3)

OUTPUT aA

T

~
~

......

~

bT

(,)

DATA (1)
INPUTB

~

~

--L

wOB

1

~
DATA
INPUT C

(2)

OUTPUT aB

aB
T

-

(10)

r-'
(6)

t----:f

OUTPUT ac

ac
T
Oc I -

~
DATA (9)
INPUT 0
(14)
CLEAR

6--;T

..r- "

L:t::::'
.... t=j
(7)

aD

OUTPUT aD

T

00 I -

....--

:J)o

(11)

LOAD

~
TlIF/6563-3

6-271

C

:!:':

....
CO

OA ~

"

--V

CO

(,)

aA

UP (5)
COUNT

C

:!:':
(J1

('f)
0)

E:

Timing Diagrams

:E

c
~
,...
oo:t

192 DECADE COUNTERS
TYPICAL CLEAR, LOAD, AND COUNT SEQUENCES

It)

:E

c
~

CLEAR

:;
.....

--Il!-_______________~------

LOAD

:E
c

-,...
N

0)

~
:E
c

COUNT--~~---4-+---,
UP
COUNT--~~---4-+---+------------------~--,
DOWN·
QA
QB

OUTPUTS

QD

CARRY
BORROW
~~

I

8

9

0

1

21 1 1

---COUNT U P - '

r-

0

9

8

71

COUNT DOWN.

CLEAR PRESET
TLlFf6563·4

Sequence:
(1) Clear outputs to zero.
(2) Load (preset) to BCD seven.
(3) Count up to eight, nine. carry. zero, one, and two.
(4) Count down to one, zero, borrow. nine, eight. and seven.
Note A: Clear overrides load, data. and count mpuls.

Hote B: When counting up. count·down input must be high; when counting down. count-up input must be high.

6·272

Timing Diagrams (Continued)

193 BINARY COUNTERS
TYPICAL CLEAR, LOAD, AND COUNT SEQUENCES

CLEAR---Il~

_____________________________________________

LOAD

COUNT
UP

--++-+-t--,

COUNT--~~---+-t---t------------------~--,

DOWN
QA

OUTPUTS

CARRY
BORROW

r--

1

.............-.,..-.--.,
CLEAR PRESET

14

15

0

1

21

COUNT UP---,

1

I

1

0

1S

14

131

COUNT DOWN---,
TL/F/6563·5

Sequence:
(1) Clear outputs to zero,.
(2) Load (preset) to binary thirteen.
(3) Count up to fourteen, fifteen, carry, zero, one, and two.
(4) Count down to one, zero, borrow, fifteen. fourteen. and thirteen.
Note A: Clear overrides load, data. and count inputs.
Note B: When counting up, count-down Input must be high; when counting down, count-up input must be high.

6-273

d';

~ ~National

~ ~ Semiconductor
DM54194/DM74194 4·Bit Bidirectional Universal
~ Shift Registers
:E
c General Description

Features

These bidirectional shift regi~ters are designed to incorporate virtually all of the features a system designer may want
in a shift register; they feature parallel inputs, parallel
outputs, right-shift and left-shift serial inputs, operatingmode-control inputs, and a direct overriding clear line. The
register has four distinct modes of operation, namely:
Parallel (broadside) load
Shift right (in the direction QA toward QD)
Shift left (in the direction QD toward QA)
Inhibit clock (do nothing)

• Parallel inputs and outputs
• Four operating modes:
Synchronous parallel load
Right shift
Lelt shift
Do nothing
• positive edge-triggered clocking
• Direct overriding clear

Synchronous parallel loading is accomplished ·by applying
the four bits of data and taking both mode control inputs, SO
and S I, high. The data are loaded into the associated f1ipflops and appear at the outputs after the positive transition
of the clock input. During loading, serial data flow is
inhibited.
.
Shift right is accomplished synchronously with the rising
edge 01 the clock pulse when SO is high and SI .is low.
Serial data lor this mode is entered at the shift-right data
input. When SO is low and S 1 is high, data shilts left synchronously and new data is entered at the shift-left serial
input.
Clocking of the Ilip-f1op is inhibited when both mode control
inputs are low. The mode controls 01 the of the DMS41941
DM74194 should be changed only while the clock input is
high.

• Typical clock frequency 36 MHz
• Typical power dissipation 195 mW

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

7V
5.5V
-6s·CtoI50·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
. maximum ratings. The "Recommended Operating Condilions"table will
define the conditions for actual device operation.

Connection Diagram
Dual-In-Line Package
OUTPUTS

l

SI
10

so
9

I I IJ J
I I I I

I
G};
TLlF/6564·1

54194 (J)

74194 IN)

6-274

Recommended Operating Conditions
Sym
Vcc

Supply Voltage

V IH

High Level Input
Voltage

V IL

Low Level Input
Voltage

10H

High Level Output
Current

IOL

Low Level Output
Current

fCLK

Clock Frequency

tw

Pulse Width

tsu

DM54194

Parameter

Setup Time

DM74194

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units
V
V

2

0

36

V

0.8

0.8

-0.8

-0.8

mA

16

16

mA

25

MHz

25

0

Clock

20

20

Clear

20

20

Mode

30

30

Data

20

20

36

ns

ns

tH

Hold Time

0

0

ns

tREL

Clear Release Time

25

25

ns

TA

Free Air Operating
Temperature

-55

Electrical Characteristics

.

Sym

125

0

DC

70

over recommended operating free .air temperature (unless otherwise noted)

Parameter

Conditions

VI

Input Clamp Voltage

Vcc=Min,II=-12mA

VOH

High Level Output
Voltage

Vcc Min, IOH = Max
V IL = Max, VIH Min

VOL

Low Level Output
Voltage

Vcc=Min,loL=Max
VIH=Min, VIL=Max

II

Input Current@Max
Input Voltage

IIH

=

Min

Typ
(Note 1)

2.4

3.4

Max

Units

-1.5

V
V

=

0.4

V

Vcc '" Max, VI = 5.5V

1

mA

High Level Input
Current

Vcc-Max, V I -2.4V

40

p.A

IlL

Low Level Input
Current

Vcc=Max, VI =O.4V

-1.6

mA

los

Short Circuit
Output Current

Vcc=Max
(Note 2)

-20

-57

mA

-18

-57

Supply Current.

Vcc

Icc

0.2

I DM54

I DM74

=Max (Note 3)

39

63

mA

Note 1: All typicals are at VCC=5V. TA=25°C.
Note '2: Not more than one output should be shorted at a time.

Not. 3: With all outputs open. inputs A through D grounded. and 4.5V applied to SO. 51. CLEAR and the serial inputs. ICC is tested with a momentary
ground. then 4.5V applied to CLOCK.
)

6·275

~r-~--------------------------------------------------------------------------,

en
~

~
:iE

o

~

Switching Characteristics at Vcc=5V and TA=25°C
From
(Input)
To
(Output)

Parameter

~

~
:iE
o

(See Section 1 for Test Waveforms and Output Load)
RL =4000
C L =15pF

f MAX Maximum Clock
Frequency

,

Min

Typ

25

36

Units
Max
MHz

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
Q

14

22

ns

t pHL Propagation Delay
Time High to Low
Level Output

Clock
to
Q

14

22

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
Q

19

30

ns

Function Table
Inputs

Outputs

'Mode
Clear
L

H
H
H
H
H
H
H

51

SO

'x

X
X
H
H
H

X
H

L
L
H
H

L

Parallel

$erial

L
L

L

Clock

Left

Right

X
L

X
X
X
X
X
H

X
X
X
H
L
X
X
X

t
t
t
t
t

X

L
X

A B

C

D

°A

X
X

X
X

X
X
d
X
X
X
X
X

L

°B
L

°c
L

°D
L

QAO

QBO

QCO

QOO

b

c

QAn
QAn
QCn
QCn

QBn
QBn
QOn

•

X
X
X
X
X

X
X
b
X
X
X
X
X

c
X
X
,X
X
X

•

H

L
QBn
QBn
QAO

aBO

QOn
QCO

d
QCn
- QCn

H

L
QOO

H = High Level (steady state), L = Low Level,(Bleady state), X = Don" Care (any input, including transitions)
t == Transition from low to high level
a, b. c, d = The level of steady stale input at inputs A. B. C, or D. respectively.
0AO. 0eo. aeo. aDO = The level of QA. Oe. Qe, or Qo. respectively, before the indicated steady stale input conditions were established.
0An. OSn. OCn. QOn = The level of QA' 0B. Ce, respectively. before the most-recent transition of the clock.

t

6·276

Logic Diagram
194
SHIFT
RIGHT
SERIAL
INPUT

SHIFT
LEFT
SERIAL

PARALLEL INPUTS

A

(21

(31

D
INPUT
(61
(71

C

B
(41

(51

PARAlLEL OUTPUTS
TLfF/6564-2

Timing Diagram
TYPICAL CLEAR, LOAD, RIGHT-SHIFT, LEFT-SHIFT, INHIBIT, AND CLEAR SEQUENCES
CLOCK
MODElso
CONTROL
INPUTS 51
CLEAR
SERIAL [R
DATA
INPUTS L

PARALLEL{:
DATA
INPUTS C

, D __

+-~

__ ______________
~

+-~

____________ __________ __
~

~

aA :

aa-

OUTPUTS {

:

ac _
aD

-+-t---1

=-+-+__...
---!-oo--INHIBIT
CLEAR LOAD

CLEAR
TLIF/6564-3

6-277

~r---------------------------------------~------------------~

O'l
....
.... ~National
~

c ~ Semiconductor
u;
:::E

O'l
DM54195/DM74195 4·Bit Parallel' Access Shift Registers
....
~
~

:::E
c General Description

Features

These 4-bit registers feature parallel inputs, parallel outputs, J-K serial inputs, shift / load control input, and a'direct
overriding clear. All inputs are buffered to lower the input
drive requirements, The registers have two modes of
operation:

•
•
•
•
II
•
•

Parallel (broadside) load
Shift (in the direction QA toward QD)
Parallel loading is accomplished by applying the four bits of
data and taking the shifl! load control input low. The data is
loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input, During
loading, serial data flow is inhibited.
.

Synch'ronou~ parallel load
Positive-edge-triggered clocking
Parallel inputs and outputs from each flip-flop
Direct overriding clear
J and K inputs to first stage
Complementary oUlputs from last slage
For lise in high-performance:
accumulalors / processors
serial-Io-parallel, parallel-Io-serial converlers

• Typical clock frequency 39 MHz
• Typical power diSSipation 195 mW

Shifting is accomplished synchronously when the shiftl
load control input is high. Serial data for this mode is entered at the J-K inputs. These inputs permit the first stage
to perform as a J-R, D, or Hype flip-flop as shown in the
function table.

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)
7V

5.5V
-65·Cto150·C

Nota 1: The "Absolute Maximum Ratlngs""are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will

define the conditions for actual device operation.

Connection Diagram
Dual·ln·Line Package
OUTPUTS

Vee

QA

as

Cc

Do

00

SHIFT,
CLOCK LOAD

1,6 J 15 J14 113 112 J"

,.

9

I II J j
I12 13I· I14 115 11 17

1

6

CLEAR

J

K

-..:....-SERIAL INPUTS

ABC

D

PARALLEllNPUrs

54195 (J)

74195 (N)

6·278

TLlF/6564·1

c

3:

Recommended Operating Conditions
Sym

Supply Voltage

V,H

High Level Input
Voltage

V,L

Low Level Input
Voltage

IOH

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

Units

is:

V

-'="
.....
en

High Level Output
Current

-0.8

-0.8

mA

IOL

Low Level Output
Current

16

16

mA

fCLK

Clock Frequency

30

MHz

tw

Pulse Width

tsu

Setup Time

Hold Time
Release Time

TA

Free Air Operating
Temperature

0
Clock

39

30

0

16

39

V

ns

16

Clear Low

12

12

Shift/Load

25

25

Data

15

15

0

0

ns

Shift/Load

10

10

ns

Clear

25

Parameter

ns

25

-55

Electrical Characteristics
Sym

125

70

0

·C

over recommended operating free air temperature (unless otherwise noted)
Conditions

Min

Typ
(Note 1)

2.4

3.4

Max

Units

V,

Input Clamp Voltage

Vcc=Min,I,= -12 mA

VOH

High Level Output
Voltage

Vcc=Min,loH=Max
V,L = Max, V,H = Min

VOL

Low Level Output
Voltage

Vec=Min,loL=Max
V,H = Min, VIL = Max

II

Input Current@Max
Input Voltage

Vcc=Max, V, =5.5V

I,!"

High Level Input
Current

Vcc-Max, VI-2.4V

40

p.A

I,L

Low Level Input
Current

Vce=Max, V, =O.4V

-1.6

mA

los

Short Circuit
Output Current

Vcc=Max
(Note 2)

mA

Supply Current

Vce = Max (Note 3)

Icc

"'o!

<0

0.8

tREL

en
C

V

0.8

tH

<0

DM74195

DM54195

Parameter

Vcc

en

-'="
.....

-1.5

0.2

V
V

0.4

V
mA

I DM54

-20

-57

IDM74

-18

-57
39

Not. 1: A" typical. are at Vce=5V, TA=25·C.
Not. 2: Not more than one output should be shorted at a time.
Not. 3: With a" outputs open, SHIFT/LOAD grounded, and 4.5V applied to the J, K, and DATA inputs,
followed by 4.5V, to CLEAR and then a momentary ground then 4.5V applied to the CLOCK.

6-279

63

mA

ICC is measured by applying a momentary ground,

~r-----------------------------------------------------------------------------~

m

:;

.......

==
m
,...
C

~

:1;

==
C

Switching Characteristics

at Vcc=5V and TA =25'C (See Section 1 for Test Waveforms and Output Load)
From
(Input)
To
(Output)

Parameter

RL =400(J
C L =15 pF

f MAX Maximum Clock
Frequency
IpLH Propagation Delay
Time Low 10 High
Level Output

Clock
to

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to

Min

Typ

30

39

Units
Max
MHz

14

22

ns

17,

26

ns

19

30

ns

Q

,

Q

tpHL Propagation Delay
Time High to Low (
Level Output

Clear
to
Q

Function Table

Inputs
Clear

Shift I
Load
X
L
H
H
H
H
H

l
H
H
H
H
H
H

Outputs

Serial

Clock

,
,
X
L

t
t
t

J

K

X
X
X
L
l
H
H

X
X
X
H
L
H
l

Parallel
A

B

X

X
b
X
X
X
X
X

a
X

X
X
X
X

OA

C

0

X

X
d
X
X
X
X
X

c
X
X
X
X
X

OB

Oc

00

Qo

l

l

L

a

b

c

l
d

d'

OAO
OAO
l
H

aBO
OAO
OAn
OAn
OAn

OCO
OBn
OBn
OBn
OBn

000

aDO

OCn
OCn
OCn
OCn

OCo

OAn

H

aCn
OCn

OCo

=

H = High Level (steady state), L = low Level (steady state), X Don't Care (any Input. Includmg transitions)
t = TranSition from low to high level
a,b,c,d
The level of steady state Input at A. B. C, or D, respectively.

=

=

0AD' QeD. Oeo. aDO The level of CA. OS. Ce. or Qo. respectively. belore the indicated steady stale input
conditions were established
'
0An' 0Bn. CCn = The leve! 01 0A. OS. CC. respectively. belore the most recent transition of the clock.

6-280

Logic Diagram
SERIAL
INPUT

PARALLEL INPUTS

,--.........-.,

K

J
SHIFT ILOAD (9)
CONTROL

(2)

(3)

A

(4)

,

B

C

(5)

D
(7)

(6)

PARALLEL OUTPUTS
TLJF/6564·2

Timing Diagram
TYPICAL CLEAR, SHIFT, AND LOAD SEQUENCES
CLOCK
CLEAR
SERIAL
INPUTS

{J

K_ _I -_ _..J

SHIFTI L O A D - - + - - - - + - - - - - - - - - - - - - - .

PARALLEL{:
DATA
INPUTS C - - t - - ' - - - - + - - - - - - - - - - - -.....

o_-+______+-______________________

~----~-------------------

a A---,
__ -+----~r - - j j_1 ' - - - - _ - - - - ! r - - - - 1~IL; " . - - - - - - - - - - -

f

1

iL._-+____+-_--'

0--

OUTPUTS

__
OC __

-+I ____+-____....I

00:::-+____-+_______--'
I------SERIAL SHIFT------!,
LOAD

I-----SERIAL SHIFT-_-__
TL/F /6564·3 .

6·281

~r------------------------------------------------------------------'

; ~National
,~ ~ Semiconductor

-,...
~
0)

DM54196/DM74196, DM54197/DM74197 Presettable Decade
~ and Binary Counters
'
;1;

uS
0)

,...
oo:r
~

~

-,...
c
co
0)

;1;
:E
c

General Description

Features

These h'igh-speed counters consist of four doc coupled,
master-slave flip-flops which are internally interconnected to provide either a divide-by-two and a divide-byfive counter (196) or a divide-by-two and a divide-by-eight
counter(197). These counters are fully programmable; that
is, the outputs may be preset to any state by placing a low
on the count/load input and entering the desired data at
the data inputs. The outputs will change independent of
the state of ,the clocks.

•
•
•
•

During the count operation, transfer of information to the
outputs occurs on the negative-going edge of the clock
pulse. These counters feature a direct clear which, when
taken low~ sets all outputs low regardless ofthe state of the
clocks. '

Absolute Maximum Ratings

Performs BCD, bi-quinary, or binary counting
Fully programmable
Fully independent clear input
Output QA maintains full fan-out capability in addition to
driving clock-2 input'

• Typical count frequency
Clock 1 50 MHz
Clock 2 25 MHz
• Typical power dissipation 240 mW

Supply Voltage
Input Voltage
Storage Temperature Range

These counters may also be used as 4-bit latches by using
the count/load input as the strobe and entering data at the
data inputs. The outputs will directly follow the data inputs
when the count !load is IQw, but will remain unchanged
when the count/load is high and the clock inputs are
(Continued)
inactive.

not be operated at these limits. The parametric values defined in the

"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings, The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual-In-Line Package
DATA INPUTS

,.--.........

14

CLEAR

13

00
12

o

•

11

C.

,

CLOCK

10

-

COUNT
LOAD

0-

Cc

7V
5.5V
- 65·C to 150·C

Nota 1: rhe "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

Connection Diagram

Vj:CC

(Note 1)

~

CLOCK

DATA INPUTS

TLlF/6565·'
Note: Low input to clear sels

aA. aS. Qc and 00 low.

54196 (J) 74196 (N)
54197 (J) 74197 (N)

6-282

c

General Description

s:
en
....
CO

(Continued)

~

TYPICAL COUNT CONFIGURATIONS 196
and 00 outputs. In this mode, the two counters operate' independently; however, all four flip-flops are
loaded and cleared simultaneously.

The output of flip-flop A is not internally connected to the
succeeding flip-flops; therefore:the counl'may b'e operated
in three independent modes:
1. When used as a BCD decade counter, the clock-2 input must be externally connected to the OA output.
Theclock-1 input receives the incoming count, and a
count sequence is obtained in accordance with the
BCD count sequence function table.

The output of flip-flop A is not internally connected to the
succeeding flip-flops; therefore the counter may be operated in two independent modes: ,
1. When used as a high-speed 4-bit ripple-through
counter, output OA must be externally connected to
the clock-2 input. The input count pulses are applied
to the clock-1 input. Simultaneous divisions by 2, 4,
8, and 16 are performed at the OA, OB, Oc and 00
outputs as shown in the function table.

f~equency synthesizers (or other applications

requiring division of a binary count by a power of ten), the
00 output must be externally connected to the
clock-, input. The input count is then applied at the
clock-2 Input and a divide-by·ten square wave Is obtained at output OA in accordance with the biquinary function table.

2. When used as a 3-bit ripple-through counter, the input
count pulses are applied to the clock-2 input. Simultaneous frequency divisions by 2, 4, and 8 are available
at the OB, OC, and QD outputs. Independent use of
flip-flop A is available if the load and clear functions
coincide with those of the 3-bit ril?ple-through
counter.

3. For operation as a divide-by-two counter and a divideby-five counter, no external interconnections are required. Flip-flop A is used as a binary element for the
divide-by:two function. The clock-2 input is used to
obtain binary divide-by-five operation at the OB, OC,

Function Tables
196

196

Decade (BCD)
(See Note A)

197
(See Note A)

(See Note B)
'Output

Count
0
1
2
3
4
5
6
7

8
9

Output
Count

Count

Output

QA

QO

QC

QB

QA

L
L
L
L
L
L
L
L
H
H

L
L
L
L
H
H
H
H
L
L

L
L
H
H
L
L
H
H
L
L

L
H
L
W
L
H
L
H
L
H

0
'1
2
3
4
5
6
7
8

9

L
L
L
L
L
H
H
H
H
H

QO
L
L
L
L
H
L
L'
L
L
H

QC

OB

L
L
H
H
L
L
L
H
H
L

L
H
L
H
L
L
H
L
H
L

0
1
2
3
4

5
6
7
8

9
10
11
12

H = High Level, L = Low level

1~

Note A: Output 0A connected to clock-2 input.
Note 8: Output 00 connected 10 clock· 1 input.

14
15

6-283

Q)

C

.....
~

....

197

2. If a symmetrical divide-by-ten count is desired for

-s:

QO

QC

QB

QA

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

L
L
L
L
H.
H
H
H
L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

CO

51l

c

s:
en
....
CO
~

-.....s:
C

.....

....
CO
~

.....

Recommended Operating Conditions
Sym

DM74196

DM54196

Parameter

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Vee

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level Input
Voltage

IOH

High Level Output
Current

IOl

Low Level Output
Current

felK

Clock Frequency

Clock 1

0

tw

Pulse Width

Clock 1

14

14

Clock 2

28

28

Clear

25

25

Load

20

20

Data High

10

10

Data Low

15

15

Data High

20

20

Setup Time

tsu
tH

.

Hold Time

2

Data Low

V
V

2

50

Units

0.8

0.8

-800

-800

mA

16

16

mA

40

MHz

40

0

20

20

tENABLE

Count Enable Time
(Note 1)

30

30

TA

Free Air Operating
Temperature

-55

125

50

V

ns

ns

ns

ns
70

" 0

'C

'196 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)

Sym

Parameter

Condit.ions

VI

Input Clamp Voltage

VOH

High Level Output
Voltage

. Vee = Min, IOH = Max
Vil = Max, VIH = Min

Val

Low Level Output
Voltage

Vec = Min, IOl = Max
VIH = Min; Vil = M_ax
(Note 5)

II

Input Current@Max
Input Voltage

Vcc=Max, VI=5.5V

IIH

High Level Input
Current

Vec= Max
VI. =2.4V

III

Low Level Input
Current

Min

Typ
(Note 2)

2.4

3.4

-1.5

Vee=Min, 11= -12 mA

Vcc=Max
VI =0.4V

0.2

Icc

Units
V
V

0.4

V

1

mA

Clock 1

80

/LA

Clock 2

120

Clear

80

Others

40

Clock 1

-A.8

Clock 2

-6.4

Clear

-3.2

Short C;'rcuit
Output Current

Vcc=Max
(Note 3)

DM54

-20

-57

DM74

-18

-57

Supply Current

Vcc=Max
(Note 4)

DM54

39

54

DM74

39

54

6·284

mA

-1.6

Others
los

Max

mA
mA

c
3:

'196 Switching Characteristics at Vcc=5V and TA=25°C

...

C1I
~

(See Section 1 for Test Waveforms and Output Load)

-....
CD

Parameter

0')

From
(Input)
To
(Output)

R L =400n
Units

C L =15 pF

f MAX Maximum Clock
Frequency

Min

Typ

40

50

MHz

Clock 1
to
QA

9

13

ns'

t pHL Propagation Delay
Time High to Low
Level Output

Clock 1
to

11

16

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock 2
to

t pHL Propagation Delay
Time High to Low
Level Output

Clock 2
to

tpLH Propagation Delay
Time Low to High
Level Output

QA
18

ns

CD

$»

c

3:
~
~

...

-c
3:
~

.......
CD

QB
14

21

ns

Clock 2
to
Qc

24

36

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock 2
to

28

42

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock 2
to

14

21

ns

t pHL Propagation Delay
Time High to Low
Level Output

Clock 2
to

16

23

ns

tpLH Propagation Delay
Time Low, to High
Level Output

ABCD
to
Any Q

16

24

ns

tpHL Propagation Delay
Time High to Low
Level Output

ABCD
to
AnyQ

25

38

ns

t PLH Propagation Delay
Time Low to High
Level Output

Load
to
AnyQ

22

33

ns

tpHL Propagation Delay
Time High to Low
Level Output

Load
to
AnyQ

24

36

ns

IpHL Propagation Deiay
Time High 10 Low
Level Output

Clear
to
Any Q

25

37

ns

QB

Qc

Qo

Qo

Note 1: Count enable time is the interval immediately preceding the negative-going edge of the clock pulse during which the COUNT/LOAD and CLEAR in-

puts must both be high to ensure counting.
Nole 2: All typicals are at VCC=5V, TA=2S'C.
Nole 3: Not more than one output should be shorted at a time.
Nole 4: ICC is measured with all inputs grounded and all outputs open.
Nole.S: QA outputs are tested at IOL = Max plus the limit value .of IlL for the CLOCK 2 input. This permits driving the CLOCK 2 input while maintaining full
fan-out capability.

/'

...
~

Max

tpLH Propagation Delay
Time Low to High
Level Output

12

c
3:

I

6·285

Recommended Operating Conditions
Sym

DM74197

DM54197

Parameter

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Vee

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level Input
Voltage

IOH

High Level Output
Current

-0.8

IOl

Low Level Output
Current

16

felK

Clock Frequency

tw

Pulse Width

tsu

Setup Time

Hold Time

tH

0.8

;

40

14

Clock 2

28

28

Clear

25

25

Load

20

20

Data High

10

10

Data Low

15

15

Data High

20

20

Data Low

20

20
30

Count Enable Time
(Note 1)

30

TA

Free Air Operating
Temperature

-55

50

0

14

tEN

\

50

0

0.8

Clock 1

125

V
V

2

2

Units

V

-0.8

mA

16

mA

40

MHz
ns

ns

ns

ns
70

0,

DC

'197 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)

Sym

Parameter

Conditions

Min

VI

Input Clamp Voltage

Vee = Min, 11= -12 mA

VOH

High Level Output
Voltage

Vee=Min,loH=Max
Vil = Max, VIH = Min,

VOL

Low Level Output
Voltage

Vee = Min, 10l = Max
VIH = Min, Vil = Max
(Note 5)

II

Input Current@Max
Input Voltage

Vee=Max, VI =5.5V

High Level Input
Current

Vee=Max
VI=2.4V.

IIH

Typ
{Note 2)

-1.5
2.4

3.4
0.2

Clock 1

•

Low Level Input
Current

Vee= Max
VI =0.4V

los

Vee='Max
{Note 3)

Icc

Supply Current

Vee = Max (Note 4)

V

1

mA

80

p.A

Clear

80
40

Clock 1

-4.8

Clock 2

-3.2

Clear

-3.2

mA

-1.6

DM54

-20

DM74

-18

-57

mA

-57
39

6·286

V

0.4

80

Others
Short Circuit
Output Current

Units

V

Clock 2

Others
III

Max

54

mA

'197 Switching Characteristics at Vcc=5V and TA=25°C
(See Section 1 for Test Waveforms and Output Load)

Parameter

From
(Input)
To
(Output)

RL =4000
C L =15 pF

f MAX Maximum Clock
Frequency

Min

Typ

40

50

Units
Max
MHz

tpLH Propagation Delay
Time Low to High
Level Output

Clock 1
to
QA

9

13

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock 1
to
QA

11

16

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock 2
to
Qs

12

18

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock 2
to
Qs

14

21

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock 2
to
Qc

24

36

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock 2
to
Qc

28

42

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock 2
to
QD

36

54

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock 2
to
QD

42

63

ns

t pLH Propagation Delay
Time Low to High
Level Output

Data
to
AnyQ

16

24

n5

tpHL Propagation Delay
Time High to Low
Level Output

Data
to
AnyQ

25

38

ns

tpLH Propagation Delay
Time Low to High
Level Output

Load
to
AnyQ

22

33

ns

tpHL Propagation Delay
Tillie High to Low
Level Output

Load
to
AnyQ

24

36

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
AnyQ

25

37

ns

Nole 1: Count ~nable lime is the Interval preceding the negative·golng edge of the clock pulse during which the COUNT/LOAD and CLEAR Inputs must
both be high to ensure counting.
NOle 2: All typical. are at VCC = 5V, TA = 25 'C.
NOle 3: Not more than one output should be shorted at a lime.
NOle 4: ICC Is measured with all inputs grounded and all outputs open.
NOle 5: QA output. are tested at IOL = Max plus the limit value of IlL for the CLOCK 21npul. This permits driving the CLOCK 21nput while maintaining full
fan·out capability.

6·287

.....
0).
~

~
.....

Logic Diagrams

:E

c

"

.0)
....
~

~
II)

:E

C

197

196

cD
0)
~

~
.....

:E

-

PRESET

PRESET
T

(5)

(5)

QA

T

QA

QA

QA

C

<0
0)
~

~
II)

(10)
DATA S

:E

C

(6)

DATAB (10)

(9)

Qs

CLOCK 2

.CLOCK2 (6)

(3)

(9)

Os

DATA C (3)

DATAC

(2)

(2)
Qc

(11)
DATAD

Oc

DATA D (11)
(12)
QD
(12) QD

TLIF16565·2

6·288

TLIF16565-3

r-------~----------------------------------------~----------.c

s:

.
~ Semiconductor

~National

~
.....

-s:
(0
(XI

c

DM54198/DM74198, DM54199/DM74199
8-Bit Shift Registers

......

.p.
.....

<0

~(XI

C

s:
U1

General Description
These S-bit shift registers feature buffered inputs to lower
the drive requirements to one normalized Series 54/74
load, and input clamping diodes to minimize switching
transients and simplify system design. Maximum input
clock frequency is typically 35 MHz and power dissipation
is typically 360 mW.
DM54198/DM74198

These bidirectional registers are designed to incorporate
virtually all of the features a system designer may want in a
shift register. They feature parallel inputs, parallel outputs,
right-shift and left-shift serial inputs, operating mode control inputs, and a direct overriding clear line. The register
has four distinct modes of "peration, namely:

Shift right is accomplished synchronously with the rising
edge of the clock pulse when SO is high and S 1 is lOW.'
Serial data for this mode is entered at the shift-right data
input. When SO is low and SI is high, data shifts left synchronously and new data is entered at the shift-left serial
input.
Clocking of the flip-flop is inhibited when both mode control
inputs are low_ The mode controls should be changed only
while the clock input is high_
(Continued)

Absolute Maximum Ratings

Parallel (broadside) load
Shift right (in the direction QA toward QH)
Shift left (in the direction QH toward QA)
Inhibit clock (do nothing)

7V

Supply Voltage
Input Voltage
Storage Temperature Range

Synchronous parallel loading is at:complished by applying
the eight bits of data and taking b!lth mode control inputs,
SO and S 1 high. The data is loaded into the associated flipflop and appears at the outputs after the positive transition
of the clock input. During loading, serial data flow is
inhibited_

(Note 1)

5.5V
-65·Cto 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the

"Eleclricai Characlerislics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagrams
Dual-In-Line Package

Dual-In-Line Package

SHIFT
LEFT
SERIAL INPUT INPUT
INPUT
INPUT
SIINPUT
H aH G
aG F
aF
E aE CLEAR

VCC

124

23

22

21

20

19

18

17

16

15

I

13

124

P-

r-

50

14

SHIFT/INPUT INPUT
INPUT
iNPUT
VCC LOAD
H OH G aG
F OF E aE CLEAR CLOCK.

2

3

4

5

6

7

8

9

10

23

22

21

20

19

18

16

17

I

11 1'2

-K

14

13

,

Parameter

Sym
Vcc

Supply Voltage

V,H

High Level Input
Voltage

V,L

Low Level Input
Voltage

IOH

High Levei Output
Current

IOL

Low Level Output
Current

fCLK

Clock Frequency

tw

Pulse Width

tH

Clear Time

TA

Free Air Operating
Temperature

,

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

0

35

V

0.8

-0.8

-0.8

mA

16

16

mA

25

MHz

25

0
20

Clear

20

20

Mode

30

30

Data

20

20

0

35

V

ns

ns

ns
70

0

·C

I

'198 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Sym

Parameter

Conditions

Min

Typ
(Note 1)

Max

Units

V,

Input Clamp Voltage

Vee = Min, 1,= -12 mA

VOH

High Level Output
Voltage

Vee = Min, 10H= Max
V,L = Max, V'H= Min

VOL

Low Level Output
Voltage

Vee = Min, 10L = Max
V,H = Min, V'L= Max

0.4

V

I,

Input Current@Max
Input Voltage

Vee=Max, V,=5.5V

1

mA

I'H

High Level Input
Current

Vee=Max, V, = 2.4V

40

I'A

I,L

Low Level Input
Current

Vee = Max, V, = 0.4V

-1.6

mA

los

Short Circuit
Output Current

Vec= Max
(Note 2)

DM54

-20

-57

mA

DM74

-18

-57

Supply Current

Vcc= Max
. (Note 3)

DM54

72

104

DM74

72

116

Icc

-1.5
2.4

V
V

mA

Not. 1: All typicals are at VCC=5V, TA=25"C.
Nota 2: Not more than one output should be shorted at a time.

Not.3: With all outputs open,
then 4.5V applied to CLOCK.

Input~

A thru H and CLEAR grounded, and 4.5V applied to SO, Sl and SERIAL Inputs, ICC is tested with a momentary ground

6-291

Q)

......
.j:>,

....
<0

.fD

c

s:
U't
....
<0
.j:>,

-s:
<0

C

~
....
<0

<0

0
125

-s:
C

0.8

20

-55

Units

V

2

Clock

Setup Time

tsu

DM74198

DM54198

CD
CD

....

~
:E

.-....

'198 Switching Characteristics

at Vcc=5V and TA=25°C
(See Section 1 for Test Waveforms and Output Load)

Q

CD
CD

Parameter

"lit

11)

:E
Q

cO

....
"lit

CD

.....

:E

-....
Q

CO
CD

"lit

II)

:E
Q

From
(Input)
To
(Output)

RL=4001l
C L=15 pF

fMAX Maximum Clock
Frequency
tpLH Propagation Delay
. Time Low to High
Level Output

Min

·Typ

25

35

Units
Max

MHz

Clock
to
AnyQ

17

26

ns

tpHL Propagation Delay.
Time High to Low
Level Output

Clock
to
AnyQ

20

30

ns

tPHL Propagation Delay
Time High to Low
Level Output

Clear
to
AnyQ

23

35

ns

6-292

Recommended Operating Conditions
DM54199

Parameter

Sym
Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

DM74199

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

Units
V
V

0.8

0.8

High Level Output
Current

-0.8

-0.8

mA

IOL

Low Level Output
Current

16

16

mA

fCLK

Clock Frequency

25

MHz

tw

Pulse Width

tsu

Setup Time

tH

Hold Time

TA

Free Air Operating
Temperature

0

35

25

0

35

V

Clock

20

20

Clear

20

20

Mode

30

30

Data

20

20

0

0

ns

0

·C

-55

125

ns

ns

70

'199 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Sym

Parameter

Conditions

Min

Typ
(Note 1)

Max

Units

VI

Input Clamp Voltage

Vcc= Min, 11= -12 mA

VOH

High Level Output
Voltage

Vec= Min, IOH= Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vec = Min, IOL = Max
VIH = Min, VIL= Max

0.4

V

II

Input Current@ Max
Input Voltage

Vce=Max, VI=5.5V

1

mA

IIH

High Level Input
Current

Vce = Max, VI = 2.4V

40

p.A

IlL

Low Level Input
Current

Vcc = Max, VI = 0.4V

-1.6

mA

I~s

Short Circuit
Output Current

Vec= Max
(Note 2)

DM54

-20

-57

mA

DM74

-18

-57

Supply Current

Vee= Max
(Note 3)

DM54

72

104

DM74

72

116

Icc

-1.5
2.4

V
V

mA

Note 1: All typicals are at Vee=5V, TA=25'C.
Note 2: Not more than one output should be shorted at a time.

Note 3: With all outputs open, CLOCK INHIBIT, CLEAR and SHIFT LOAD grounded, and 4.5V applied to J, Kand A thru H, ICC is tested with a momentary
ground then 4.5V applied to CLOCK.
.

6-293

mr---------------------------------------------------------------------------~,

....m
r::!

::i!:

-

'199 Switching Characteristics

at vee= 5V and TA= 25°C
(See Section 1 for Test lijaveforms and Output Load)

c

m
m

....
'<:t'

Parameter

II)

:!E

c
~
....
'<:t'

""

:!E

c

~
....
'<:t'

II)

:!E

c

From
(Input)
To
(Output)

RL=4001l ,
'C L =15 pF

f MAX Maximum Clock
Frequency

Min

Typ

25

35

Units
Max
MHz

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
Any Q

17

26

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
Any Q

20

30

tpHL Propagation Delay
Time High to Low
Level Output '

Clear
to
AnyQ

23

35

6·294

ns

..

ns

ns

c

s:

Logic Diagrams

01

.j::o.

198

......

199

<0

~
C

s:
......

CLOCK (13)

CLOCK (11)

CLOCK (11)
INHIBIT
(2)
SERIAL( J
INPUTS K (1)

.j::o.

......

<0

~oo

C

SHIFT/ (23)

s:
01

LOAD
A (3)

.j::o.
......

-s:
<0
<0

C

......
.j::o.

(5)

......

B

<0
<0

B (5)

C~!-==t===c)

(15)
E~~------~~--~~

E (16)

F (17)
F (18)

G (19)
G (20)

(21)
H__________

~~~~~j

------------+--l.J

SHIFT_(2_2_)
LEFT

H (22)

CLEAR~(~132)__q;~------lt======___~~~

CLEAR_(1_4_)____________q)~----~~~
OH
(21)

TLIF/6566-3

6-295

TL/F/6566·4

enr-----------------~----------------------------------------------------------~

en
.....

~
:E

Timing Diagrams

c

CLOCK

:E

CLEAR

~
~

c

=

en.....

SERIAL { R

IN~~~~

o::t
.....

L-t-+--i--....:...--....;.---------t-t....l
A

B~+=====~==~======~====~

:E

c

~
.....

198

TYPICAL CLEAR, LOAD, RIGHT-SHIFT, LEFT-SHIFT, INHIBIT, AND C!-EAR SEQUENCES

C

PARALLEL

DATA

O~~--+-----------------------_+_+--------------------_+----------_+-

INPUTS

~
:E

G

c

H

OUTPUTS

199

TLIF16566-5

TYPICAL CLEAR, SHIFT, LOAD, AND INHIBIT SEQUENCES
CLOCK

CLQCK
INHIBIT

CLEAR

SERIAL {
INPUTS

J-+-....I_J __' - . . : . . . . - - - - - - - - - - - - - I - t - - - - i - + - - - - - - - - - - - - - -

K

A__t-___+------------------------'

TLlF/6566-6

6·296

Parameter Measurement Information
199
TEST TABLE FOR SYNCHRONOUS INPUTS

198
TEST TABLE FOR SYNCHRONOUS INPUTS
Data Input
for Test

S1

So

Output Tested
(See Note E)

Data Input
for Test

Shift/Load

A
S
C
0
E
F
G
H
L Serial Input
R Serial Inpul

4.5V
4.5V
4.5V
4.5V
4.5V
4.5V
4.5V
4.5 V
4.5V
OV

4.5 V
4.5V
4.5 V
4.5V
4.5V
4.5 V
4.5V
4.5 V
OV
4.5 V

QA a11 n+l
QS al I n+l
QC at In+l
QO al In+l
QE at I n+l
QF at I n+l
QG a11n+l
QH at In+l
QA a11n+8
QH altn+8

A
S
C
0
E
F
G
H
J andK

OV
OV
OV
OV
OV
OV
OV
OV
4.5 V

Output Tested
(See Note E)
QA
QS
QC
QO
QE
QF
QG
QH
QH

at In+l
at tn+l
at tn+l
at tn+l
at tn+l
at tn+l
al In+l
at In+l
at tn+8

LOAD FOR OUTPUT UNDER TEST
VCC
OUTPUT

lit. =

FROM
OUTPUT
UNDER

400 [/

-+.............+-I~-I.....,

TEST

ct =

15

(SEE NOTE C)

pF

T(SEE NOTE B)
TLlFJ6566-7

-I

CLEAR INPUT

SWITCHING TIME WAVEFORMS
IW(CLEAR)r,:

---I.-5-v"'L11.5-v-----------------.. . . .---(SEE NOTE F)

In

3V

~

~r­

~3V

CLOCK INPUT

l--+-_____-'

OUTPUT a - - - - -......"

0V

Ir - - - - - 3 V

DATA INPUT
(SEE TEST TABLE) _ _ _ _

IpHL
(CLEAR-a)

IHOLD

~-+J-------------OV

I--(CL~-O)~ll,1.5V

f-

1.5

IPLH

IpHL
(CLK-O)

----"'+----VOH

V

'"----VOL
TLiF/6566-B

Note A: :The clock pulse has the following characteristicj5: tw(clock) =:: 20 ns and PRR = 1 MHz.
The clear pulse has the foJlowing characteristics: tw(clear) ~ 20 ns and tHOLD = 0 ns.
When testing 'MAX. vary ~he clock PRR.
Note B: Cl Includes probe and jig capacitance.
Note C: All diodes are 1N3064.

Note D: A clear pulse is applied i?rlor to each lest.
Note E: Propagation delay times (tplH and tpHL) are measured at tn+ l' Proper shifting of data is venfied at In+8 with a functional test.
Note F: tn = bit lime before clocking transition.
t n+ 1 = bit time after one clocking transition
I n +8 = bit time after clocking Iransitions

6·297

.,...

~ ~National
~ ~ Semiconductor

- DM54251/DM74251 TRI·STATE® 1 ot8 Line
.,...
~

:E

c

Data Selectors/Multiplexers
General Description
These data selectors/ multiplexers contain full 'on-chip binary decoding to select one-of-eight data sources, and feature a strobe-controlled TRI-STATE output. The strobe must
be at a low logic level to enable these devices. The TRISTATE outputs permit direct connection to a common bus.
When the strobe input is high, both outputs are in a highimpedance state in which both the upper and lower transistors of each totem-pole output are off, and the output
neither drives ~or loads the bus significantly. When the
strobe is low, the outputs are activated and operate as
standard TTL totem-pole outputs.
To minimize the possibility that two outputs will attempt to
take a common bus to opposite logic levels, the output control circuitry is designed so that the average output disable
time is shorter than the average output enable lime.

Features
•
,.
•
•
•

• Max no. of common outputs
OM54251 49
OM74251 129
• Typical propagation delay time (0 to Y) 17ns
• Typical power dissipation 155 mW

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)
7V
5.5V

- 65·C to 150·C

Nole 1: The "Absolute Maximum Ratings" are those values beyond
which the safely of the device can not ba guaranleed. The device should
not ba operated al these limits. The parametric values defined in the
"Electrical Characteristics" lable are nol guaranteed at the absolute
ma)(imum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

TRI-STATE version 01 151
Interlace directly with system bus
Perform parallel-to-serial conversion
Permit multiplexing Irom N·lines to one line
Complementsry outputs provid~ t(ue and inverted data

Connection Diagram

Function Table

Dual-In-Line Packag'e
DATA INPUTS
Vcc

1,6

D4

OS

1S

14

De

13

07'

DATA SELECT
ABC'

12

11

10

Inputs
Select

9

,.....

2

3

4

02
01
DATA INPUTS

DO.

1

,03

5

6

~

7

Ie

(J)

B

A

X
L
L
L
L
H
H
H
H

X
L
L
H
H
L
L
H
H

X
L
H
L
H
L
H
L
H

Strobe
S

y

W

H
L
L
L
L
L
L

Z
DO

Z
00
01
02
03
04
05
06
07

L
L

01
02
03
04
05
06
07

STROBE GNO

OUTPUTS

-H =-High Logic Level, L a= LowLogic LlGtvel
X = Don't Care. Z = High Impedance (010

TLfF/6567·'

54251

C

Outputs

74251 (N)

DO. 01 ... 07 • The Level of the respective 0 input.

6-298

Recommended Operating Conditions
Symbol

DM54251

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level Input
Voltage

IOH

High Level Output
Current

IOl

Low Level Output
Current

TA

Free Air Operating
Temperature

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units
V

2

V

0.8

,
-55

Electrical Characteristics
Symbol

DM74251

0.8

V

-2

-5.2

mA

16

16

mA

70

DC

125

0

over recommended operating free air temperature (unless otherwise noted)

Conditions

Parameter

Min

Typ
(Note 1)

Max

Units

VI

Input Clamp Voltage

Vee = Min, 11= -12 mA

VOH

High Level Output
Voltage

Vee = Min, IOH = Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee= Min, IOl= Max
VIH = Min, Vll= Max

0.4

V

II

Input Current@Max
Input Voltage

Vee = Max, VI = 5.5V

1

mA

IIH

High Level Input
Current

Vee = Max, VI=2.4V

40

/lA

III

Low Level Input
Current

Vee = Max, VI = O.4V

-1.6

mA

10ZH

Off-State Output
Current with High,
Level Output
Voltage Applied

Vee = Max, Vo=2.4V
VIH = Min, Vil = Max

40

/lA

10Zl

Off-State Output
Current with Low
Level Output
Voltage Applied

Vee = Max, Vo=O.4V
VIH = Min, Vil = Max

-40

/lA

Short Circuit
Output Current

Vee = Max
(Note 2)

-18

-70

mA

-18

-70

Supply Current

Vee= Max (Note 3)

los

Icc

=

-1.5
2.4

V
V

I

I DM54

I DM74

31

=

Nota 1: All typlcals are at Vee 5V. TA 25'e.
Nota 2: 'Not more than one output should be shorted at a time. and the duration should not exceed one second.
Nota 3: ICC Is measured with the outputs open. STROBE at 4.5V or ground. and all other inputs at 4.5V.

•

6-299

51

mA

SWitching Characteristics
Parameter

From
(Input)
To
(Output)

at Vcc=5V and TA=25"C (See Section 1 for Test Waveforms and Output Load)
RL=4001l
CL=5 pF
Min

Typ

CL=50 pF
Max

Min

Units

Typ

Max

tpLH Propagation Delay
Time Low to High
Level Output

A,B,C
(4 Levels)
toY,

22

36

ns

tpHL Propagation Delay
Time High to Low
Level Output

A,B,C
(4 Levels)
toY

23

36

ns

tpLH Propagation Delay
Time Low to High
Level Output

A,B,C
(3 Levels)
toW

18

29

ns

tpHL Propagation Delay
Time High to Low
Level Output

A,B,C
(3 Levels)
toW

16

27

ns

tpLH Propagation Delay
Time Low to High
Level Output

Data
to
Y

17

28

ns

tpHL Propagation Delay
Time High to Low
Level Output

Data
'to
Y

18

28

ns

tpLH Propagation Delay
Time Low to High
Level Output

Data
to
W

11

15

'ns

tpHL Propagation Delay
Time High to Low
Level Output

Data
to
W

10

15

ns

tPZH Output Enable
Time to High
Level Output

Strobe
to
Y

15

27

ns

tpzL Output Enable
Time to Low
Level Output

Strobe
to
Y

18

36

ns

tPZH Output Enable
Time to High
Level Output

Strobe
to
W

15

27

ns

tPZL Output Enable
Time to Low
Level Output

Strobe
to
W

19

38

ns

tpHz Output Disable
Time from High
Level Output

Strobe
to
Y

4 .

8

ns

tpLZ Output Disable
Time from Low
Level Output

Strobe
to
Y

14

23

ns

tpHZ Output Disable
Time from High
Level Output

Strobe
to
W

4

8

ns

tpLZ Output Disable
Time from Low
Level Output

Strobe
to
W

15

23

ns

6·300

.----------------------------------------------------------------------.0
s:
Logic Diagram

t....

-s:o
U'I

(:~:~~~
DO

~

(7)

.N

(4)

-

01 (3)

.

02 (2)

DATA
INPUTS

p.-J~

0---

03 (1)

-

04 (15)

r-

~
~

--=::::;

~

) OUTPUT Y

~

......

05 (14)

....

U'I

'"

(6 ) OUTPUT W

)-D6 (13)

~

07 (12)

r-t'

}---

A

(11)
DATA
SELECT
(BINARY)

f

J

'-f"

A

B

A (10)
B

1

(9)

1

C

r--

.J"....

B

C
C
~v

TLlF/6567·2

6-301

~ ~National

~ ~ Semiconductor

CO)

l:!3

i
Q

DM54253/DM74253 TRI-STATE® Dual 1 of 4 Line
Data Selectors/Multiplexers
General Description
This device is a TRI-STATE version of the very popular
DM54153 (DM7214) data selectors/multiplexers. It con·
tains full on-chip decoding to select the c!esired data Input. The DM54/74253 Is a dual, four-line multiplexer that
has common select lines which therefore select the same
input line of both multiplexers. However, the two outputs
can be individually controlled by means of the separate
enable lines; which, when taken to a high logic level,
places the output in the high-impedance TRI-STATE condition. The data at the output of the DM54/74253 is true.

Features
.• TRI-STATE pin equivalents to popular 54/74 TTL devices
DM7214/8214 - 54153/74153

• Typical propagation delay 13.5 ns
• Typical power dissipation 170 mW
• Strobe/enable override

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

Dual-In-Line Package
DATA INPUTS
VCC

~---------,

2C3

2C2

2Cl

OUTPUT
Y2

2CO

8
ENABLE SELECT
<31
8

lC3
lC2
lCl
lCO
'--_ _ _ _
• _ _ _---'

OUTPUT
Yl

GND

DATA INPUTS
TL/F/656B·1

548253 (J)

7V
5.5V
-65·Ct0150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagrams

ENABLE SELECT
<32
A

(Note 1)

748253(N)

6-302

c

s:
en

Recommended Operating Conditions
Symbol

DM54253

Parameter

Vee

Supply Voltage

V IH

High Level Input
Voltage

Vil

Low Level Input
Voltage

IOH

High Level Output
Current

IOl

Low Level Output
Current

TA

Free Air Operating
Temperature

Parameter

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

Units

t

en

Cto)

0.8

-2
16
-55

125

0

V

-5.2

mA

16

mA

70

·C

"

over recommended operating free air temperature (unless otherwise noted)

Min

Conditions

Typ
(Note 1)

Max
-1.5

Units

VI

Input Clamp Voltage

Vee = Min, 11= -12 mA

VOH

High Level Output
Voltage

Vee = Min, 10H = Max
Vil = Max, , VIH = Min

VOL

Low Level Output
Voltage

Vee = Min, 10l= Max
VIH = Min" Vll = Max

0.4

V

II

Input Current@ Max
Input Voltage

Vee = Max, VI=5.5V

1

mA

IIH

High Level Input
Current

Vee = Max, VI=2.4V

40

p.A

III

Low Level Input
Current

Vee=Max, VI=O.4V

-1.6

mA

10zH

Off·State Output
Current with High
Level Output
Voltage Applied

Vee = Max, Vo=2.4V
VIH = Min, VIL= Max

40

p.A

10Zl

Off·State Output
Current with Low
Level Output
Voltage Applied

Vee = Max, Vo=0.4V
VIH= Min, VIL= Max

-40

p.A

los

Short Circuit
Output Current

Vee- Max
(Note 2)

mA

Supply Current

Vee = Max
(Note 3)

Icc

-s:
Cto)

C

V
V

0.8

Electrical Characteristics
Symbol

t

en

DM74253

DM54

-18

-55

DM74

-18

-55

DM54

34

56

DM74

34

65

Note 1: All typicals are at Vee=SV. TA=2S'e,
Note 2: Not more than one output should be shorted at a time.
Note 3: ICC is measured with all inputs grounded and outputs open.

6·303

V
V

2.4

mA

Switching· Characteristics
Parameter

at Vee = 5V and T A = 25°C (See Section 1 for Test Waveforms and Output Load)

From
(Input)
To
(Output)

RL=40011
CL=5 pF
Min

Typ

CL=50pF
Max

Min

Typ

Units
- Max

tpLH Propagation Delay
Time Low to High
Level Output

Data
to
Output

15

23

ns

tpHL Propagation Delay
Time High to Low
Level Output

Data
to
Output

12

18

ns

tpLH Propagation Delay
Time Low to High
Level Output

Select
to
Output

20

34

ns

tpHL Propagation Delay
Time High to Low
Level Output

Select
to
Output

20

34

ns

tPZH Output Enable
Time to High
Level Output

Enable
to
Q

12

18

ns

tPZL Output Enable
Time to Low
Level Output

Enable
to
Q

14

21

ns

tpHZ Output Disable
Time from High
Level Output

Enable
to
Q

5

10

ns

tpLZ Output Disable
Time from Low
Level Output

Enable
to
Q

15

23

ns

.'

"

,
I

6-304

Function Table
Select Inputs

Data Inputs

Enable

Output

B

A

CO

C1

C2

C3

G

Y

X
L
L
L
L
H
H
H
H

X
L
L
H
H
L
L
H
H

X
L
H
X
X
X
X
X
X

X
X
X
L
H
X
X
X
X

X
X
X
X
X
L
H
X
X

X
X
X
X
X
X
X
L
H

H
L
L
L
L
L
L
L
L

Hi-Z
L
H
L
H
L
H
L
H

L; Low Logic Level
H ; High Logic Level
X; Either Low or High Logic Level
Hi-Z; High Impedance (Off) State

Logic Diagram
54/74253
ENABLE (1)

STROBE Gl
lCO~(6~)______________~~~J

lCl~(5~)____________-F~~~-'
DATA 1

lC2~(4~)-----------t-r~r-4--'

DATA 2

ENABLE

STROBEG2
TlIF/656B-2

6-305

~Nat1onal

~ Semiconductor
DM54259/DM74259 8-Bit Addressable Latches
General Description
These 8-bit addressable latches are designed for general
purpose storage applications in digital systems. Specific
uses include working registers, serial-holding registers,
and active· high decoders or demultiplexers. They are
multifunctional devices capable of storing single-line data
in eight addressable latches, and being a l-of-8 decoder or
demultiplexer with active·high outputs. .
Four distinct modes of. operation are selectable by controlling the clear and enable inputs as enumerated in the func·
tion table. In the addressable-latch mode, data at the
data-in terminal is written into the addressed latch. The addressed latch will follow the data input with all unaddressed
latches remaining in their previous states. In the memory
mode, all latches remain in their previous states and are
unaffected by the data or address inputs. To eliminate the
possiblity of entering erroneous data in the latches, the enable should be held high (inactive) while the address lines
are changing. In the l'of-8 decoding or demultiplexing
mode, the addressed output will follow the level of the 0
input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and data
inputs.

Features

•
•
•
•
•
'.

Active High Decoder
Enable/Disable Input Simplifies Expansion
Direct Replacement for Fairchild 9334
Expandable for N-Bit Applications
Four Distinct Functional Modes
Typical Propagation Delay Times:
Enable-to-Output 18 ns
Data-to-Output 21 ns
Address-to-Output 22 ns
Clear-to-Output 21 ns

• Fan-Out
IOL (Sink Current) 16 mA
IOH (So'uree Current) -0.8 mA
• Typical ICC 60 mA

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

Connection Diagram
Dual·ln·Line Package

l16

15

07

D

Clear

14

13

06

12

04

05

11

10

9

-

2
A

B

3

e

5

4

00

7V

5.5V
- 65·C to 150·C

Nole 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device Can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation .

• 8-Bit Paralh;I-Out Storage Register Performs Serial-toParallel Conversion With Storage
• Asynchronous Parallel Clear

Vee

(Note 1)

01

54259 (J)

6

02

7
03

I

B

GND

74259 (N)
TUF/6569-,

6-306

Recommended Operating Conditions
Symbol
Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High I.evel Output
Current

IOL

Low Level Output
Current

tw

Pulse Width

tsu

tH

TA

DM54259

Parameter

Setup Time
(Notes 1 and 2)
Hold Time
(Note 1)

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

Enable

19

-0.8

-0.8

mA

16

16

mA

19

13

19

13

19

Data

20

13

20

13

Select

10

5

10

5

Data

0

-10

0

-10

Select

0

-13

0

-13

Parameter

V

0.8

13

-55

V

0.8

Clear

Free Air Operating
Temperature

Units

V

13

Electrical Characteristics
Symbol

DM74259

Min

125

0

ns

ns

ns

70

·C

over recommended operating free air temperature (unless otherwise noted)
Conditions

VI

Input Clamp Voltage

Vee= Min, 11= -12 mA

VOH

High Level Output
Voltage

Vee= Min, IOH= Max
VIL = Max, VIH= Min

VOL

Low Level Output
Voltage'

Vee = Min, IOL= Max
VIH = Min, VIL= Max

II

Input Current@Max
Input Voltage

IIH

Min

Typ
(Note 3)

2.4

3.4

Max
-1.5

UnitS
V
V

0.4

V

Vee = Max, VI= 5.5V

1

mA

High Level Input
Current

Vee='Max, VI=2.4V

40

p.A

IlL

Low Level Input
Current

Vee= Max, VI = 0.4V

-1.6

mA

los

Short Circuit
Output Current

Vee=Max
(Note 4)

mA

Supply Current

Vee=Max (Note 5)

lee

0.2

"

I

DM54

-20

-55

I

DM74

-20

-55
90

mA

Nota 1: Setup and hold times are with reference to the enable" input.
Note 2: The seleet·te-enable setup time is the time before the Hlgh·te-Low enable transition that the select must be stable so that the correct latch Is
selected and the others not affected.

Note 3: Aillypicals are al Vee=5V. TA=25"e,
Note 4: Nol more Ihan one oulpUI should be shorled al a lime,
Note 5: lee is measured wilh 4.5V applied 10 all inpuls and all oulputs open,

6·307

-

Switching Characteristics

at Vcc=5V and TA=25°C (See Section 1 for Test Waveforms and Output Load)
From
(Input)
To
(Output)

Parameter

RL = 4000

CL =15 pF
Min

Units

Typ

Max

t PLH Propagation Delay
Time Low to High
Level Output

Enable
to
Output

19

28

ns

tpHL Propagation Delay
Time High to Low
Level Output

Enable
to
Output

18

27

ns

t PLH Propagation Delay
Time Low to High
Level Output

Data
to
Output

24

35

ns

tpHL Propagation Delay
Time High to Low
Level Output

Data
to
Output

19

28,

ns

tpLH Propagation Delay
Time Low to High
Level Output

Select
to
Output

23

35

ns

tpHL Propag~tion Delay
Time High to Low
Level Output

Select
to
Output

21

35

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
Output

21

31

ns

Function Tables
Inputs
Clear

E

H
H
L
L

L
H
L
H

Output Of
Addressed
Latch

Each
Other
Output

Function

D

aiO
aiO
L
L

Addressable Latch
Memory
B·Line Demultiplexer
Clear

aiO
D

L

Latch Selection Table
Select Inputs

H

C

B

A

L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H

== high level, L

5

Latch
Addressed
0
1

2
3
4
5
6
7
low level

o as the level 01 the data input

==

aiO
the level of aJ (i = 0, 1•... 7. as appropriate) before the indicated
steady·state input conditions were established.

6·308

:~

~--------------------------------------------------------------'C

s::UI

~National

f')

~ Semiconductor·

m

-s::
C

~
Co)
en

DM54365/DM74365 Hex TRI·STATE® Buffers

UI

General Description

Absolute Maximum Ratings

This device contains six independent gates each of
which performs a non-inverting buffer function. The outputs have the TRI-STATE feature. Wlien enabled, the
outputs exhibit the low impedance characteristics of a
standard TTL output with additional drive capability to
permit the driving of bus lines without external
resistors. When disabled, both the output transistors
are turned off presenting a high-impedance state to the
bus line. Thus the output will act neither as a significant
load nor as a driver. To minimize the possibility that two
outputs will attempt to take a common bus to opposite
logic levels, the disable time is shorter than the enable
time of the outputs.

Supply Voltage
Input Voltage
Storage Temperature Range

Connection Diagram

Function Table

7V
5.5V
-65·Cto 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual-In-Llne Package

Y=A
Input

Output

G1

G2

A

Y

L
L·
H

L
L

L
H

X

X

H

X
X

L
H
Hi-Z
Hi-Z

H = High Logic Level
L= Low Logic Level
X = Either Low or High Logic Level
HI-Z = TRI-STATE (Outputs are disabled)

TLlF/6570-1

DM54365(J)

DM74365 (N)

(Note 1)

Recommended Operating Conditions
Symbol

DM54365

Parameter

DM74365

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units

Vee

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level Inp.ut
Voltage

IOH

High Level Output
Current

-2

-5.2

rnA

IOl

Low Level Output
Current

32

32

rnA

TA

Free Air Operating
Temperature

70

·C

2

Symbol
VI

-55

Parameter

125

Conditions

Input Clamp Voltage

Vee= Min, IOH= Max
Vll= Max, VIH= Min

VOL

Low Level Output
Voltage

Vee= Min, IOl= Max
VIH = Min, Vil = Max

II

Input Current@ Max'
Input Voltage

Vee = Max, VI = 5.5V

IIH

High Level Input
Current

Vee = Max, VI = 2.4V

III

Low Level Input
Current

Vee= Max
VI = 0.5V
(Note 4)

Typ
(Note 1)

2.4

3.1

Max

Units

-1.5

0.2

V

V
0.4

V

1.0

rnA
I

40

p.A

A

-40

rnA

Vee = Max
VI = O.4V
(Note 5)

A

-1.6

Vee= Max
VI = O.4V

G

-1.6

10ZH

Off·State Output
Current with High
Level Output
Voltage Applied

10Zl

Off·State Output
Current with Low
Level Output
Voltage Applied

los

Short Circuit
Output Current

Vee= Max
(Note 2)

Supply Current

Vee= Max (Note 3)

,

Vee= Max, Vo= 2.4V
VIH = Min, Vil = Max

40

p.A

Vee= Max, Vo= 0.4V
VIH = Min, Vll= Max

-40

p.A

rnA

DM54

-40

-115

DM74

-40

- 115
59

All typicals are at Vee =SV, TA =2S'e.

Note 2: Not more than one output should be shorted at a time.
Note 3: ICC is measured with the data inputs grounded and the output controls at 4.SV.
Both G inputs are at 2V.

Note 4:

Note 5:

Min

Vee = Min, 11= - 12 rnA

High Level Output
. Voltage

Note 1:

0

V

over recommended operating free air temperature (unless otherwise noted)

VOH

lee

0.8

0.8

Electrical Characteristics

V
V

2

Both G inputs are at O.4V.

6·310

85

rnA

,

Switching Characteristics at Vcc=SV and TA=2SoC

(See Section 1 for Test Waveforms and Output Load)

RL = 4001}
Parameter

C L =5pF
Min

Typ

Units

CL=50 pF
Max

Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

10

16

ns

tpHL Propagation Delay Time
High to Low Level Output

14

22

ns

t pZH Output Enable Time
to High Level Output

21

35

ns

tpZL Output Enable Time
to Low Level Output

24

37

ns

tpHZ Output Disable Time
from High Level Output

6

11

ns

t pLZ Output Disable Time
from Low Level Outpu.t

16

27

ns

.

6·311

~~ ~Nat1onal

.~ ~ Semiconductor

~

~ DM54366/DM74366 Hex Inverting TRI-STATE® Buffers

General Description

Absolute Maximum Ratings

This device cOntains six independent gates each of which
performs an inverting buffer function. The outputs have
the TRI-STATE feature. When enabled, the outputs exhibit
the low impedance characteristics of a standard TTL output with additional drive capability to permit the driving of
the bus lines without 'external resistors. When disabled,
both the output transistors are turned off presenting a
high-impedance state to the bus line. Thus the output will
act neither as a significant load nor as a driver. To
minimize the possiblity that two outputs will attempt to
take a common bus to opposite logic levels, the disable
time is shorter than the enable time of the outputs.

Supply Voltage
Input Voltage
Storage Temperature Range

Connection Diagram

7V

5.5V
- 65·C to 150·C

',Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" ta~le are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

,Function Table

Dual·ln·Line Package

V=A
Input

.,

Output

G1

G2

A

V

L
L
H

L

L

L

H

X

X

H

X
X

H
L
Hi·Z
Hi-Z

H = 'High Logic Level
L = Low Log Ie Level
X = Either Low or High Lo'gie Level
VI

A2

Y2

.3

Y3

Hi·Z='TRI-STATE (Outputs are disabled)

GNO

TLlF/6571-1

DM54366 (J)

(Note 1)

DM74366 (N)

6-312

c

:s:
C1I

Recommended Operating Conditions
Parameter

Min

Nom

Max

Min

Nom

~ax

5

5.5

4.75

5

5.25

-:s:c

V

Co)

Units

Vee

Supply Voltage

V IH

High Level Input
Voltage

V IL

Lew Level I':!put
Voltage

IOH

High Level Output
Current

-2

-5.2

mA

IOL

Low Level Output
Current

32

32

mA

TA

Free Air Operating
Temperature

70

·C

4.5.
2

0.8

-55

Electrical Characteristics
Symbol

2

Parameter

125

0

V

over recommended operating free air temperature (unless otherwise noted)

Conditions

VI

Input Clamp Voltage

Vee= Min, 11= -12 mA

VOH

High Level Output
Voltage

Vee = Min, 10H = Max
VIL = Max, VIH= Min

VOL

Low Level Output
Voltage

Vee= Min, 10l= Max
VIH = Min, Vil = Max

II

Input Current@Max
Input Voltage

IIH
III

"

0.8

Min

Typ
(Note 1)

2.4

3.1

Max
-1.5

0.2

Units
V
V

0.4

V

Vee = Max, VI= 5.5V

1.0

mA

High Level Input
Current

Vee = Max, VI = 2.4V

40

I'A

Low Level Input
Current

Vee = Max
VI = 0.5V
(Note 4)

A

-40

mA

Vee= Max
VI = O.4V
(Note 5)

A

- 1.6

Vee= Max
VI = O.4V

G

- 1.6

10ZH

Off·State Outp'ut
Current with High
Level Output
Voltage Applied

Vee = Max, Vo= 2.4V
V IH = Min, V ll = Max

40

I'A

10Zl

Off·State Output
Current with Low
Level Output
Voltage Applied

Vee= Max, Vo= 0.4V
VIH = Min, VIL= Max

- 40

I'A

los

Short Circuit
Output Current

Vee= Max
(Note 2)

mA

Supply Current

Vee = Max (Note 3)

Icc

DM54

-40

- 115

DM74

-40

-1t5
59

Nol. I: All typicals are at Vee~ 5V, TA~ 25·e.
Nol.2: Not more than one output should be shorted at a time.
Note 3: ICC is measured with the data inputs grounded and the output controls at 4.5V.

Nole 4: Both G inpuls are at 2V.
Nole 5: Both G inputs are at OAV.

6·313

77

~

V

DM74366

DM54366
Symbol

mA

en

.....
J::io

en
en

Switching Characteristics

at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL =4000

,

Parameter

CL=5 pF
Min

Typ

CL=50 pF
Max

Min

Units

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

11

17

ns

tpHL Propagation Delay Time
High to Low Level Output

10

16

ns

tpzH Output Enable Time
to High Level Output

21

35 .

ns

tPZL Output Enable Time
to Low Level Output

24

37

ns

tpHZ Output Disable Time
from High Level Output

6

11

ns

tpLZ Output Disable Time
from Low Level Output

16

27

ns

6-314

.-------------------------------------------------------------.0
:s:
CJ1

~National

-'="

~ Semiconductor

(0)

~

o

:s:
......
-'="

(0)

DM54367/DM74367 Hex TRI·STATE® Buffers

en
......

General Description

Absolute Maximum Ratings

This device contains six independent gates each of which
performs a non·inverting buffer function. The outputs have
the TRI·STATE feature. When enabled, the outputs exhibit
the low impedance"characteristics of a standard TIL out·
put with additional drive capability to permit the driving of
bus lines without external resistors. When disabled, both
the ouiput transistors are turned off presenting a high·
impedance state to the bus line. Thus the output will act
neither as a significant load nor as a driver. To minimize
the possiblity that two outputs will attempt to take a com·
man bus to opposite logic levels, the disable time is
shorter than the ena~le time of the outputs.

Supply Voltage
,Input Voltage
Storage Temperature Range

Connection Diagram

Function Table

Y=A
Input

G2

A6

V6

A5

7V

5.5V
- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parpmetric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dua,I.ln.Lille Package
Vee

V5

V4

Output

G

A

Y

L
L
H

L
H
X

L
H
Hi·Z

H = High Logic Level
L = Low Logic Level

X = Either Low or High Logic Level
HI·Z = TAI·STATE (Oulpuls are disabled)

.,

V1

A2

V2

A3

V3

GND

TLlF/6572·1

DM54367 (J)

(Note 1)

DM74367 (N)

6·315

Recommended Operating Conditions
Symbol

DM74367

DM54367

Parameter

Min

Nom

Max

Min

Nom

Max

5

5.5

4.75

.5

5.25

Units
V

Vee

Supply Voltage

4.5

VIH

High Level Input
. Voltage

2

Vil

Low Level Input
Voltage

10H

High Level Output
Current

-2

-5.2

mA

10l

Low Level Output
Current

32

32

mA

TA

Free Air Operating
Temperature

70

'C

Parameter

V

O.B

-55

Electrical Characteristic;s
Symbol

2

125

O.B

0

V

over recommended operating free air temperature (unless otherwise noted)
Conditions

VI

Input Clamp Voltage

Vee = Min, 11= -12 mAo

VOH

High Level Output
Voltage

Vee= Min, 10H= Max
Vll= Max, VIH= Min

VOL

Low Level Output
Voltage

Vee = Min, 10l= Max
VIH= Min, Vll= Max

II

Input Current@Max
Input Voltage

IIH
III

Min

Typ
(Note 1)

2.4

3.1

Max
-1.5

V
V

0.4

V

Vee = Max, VI = 5.5V

1.0

mA

High Level Input
Current

Vee= Max, VI= 2.4V

40

p.A

Low Level Input
Current

Vee = Max
VI =0.5V
(Note 4)

A

-40

mA

Vee= Max
VI=O.4V
(Note 5)

A

-1.6

Vee= Max
VI =0.4V

G

-1.6

mA

.. .

0.2

Units

10ZH

Off·State Output
Current with High
Level Output
Voltage Applied

Vee= Max, Vo= 2.4V
VIH = Min, Vil = Max

40

p.A

10Zl

Off·State Output
Current with Low
Level Output
Volt~ge Applied

Vee= Max, Vo= O.4V
VIH = Min, Vll= Max

-40

p.A

los

Short Circuit
Output Current

Vee= Max
(Note 2)

mA

Supp'ly Current

Vee = Max (Note 3)

lee

DM54

-40

-115

DM74

-40

-115
65

Note 1: All typicals are at Vee=5V, TA=25'e.
Note 2: Not more than one output should be shorted at a time.
Note 3: lee Is measured with the data inputs grounded and the output

controls at 4.5V.

Note 4: Both G inputs are at 2V.
Note 5: Both G inputs are at O.4V.

.6·316

B5

mA

Switching Characteristics

at Vcc=5V and TA=25"C (See Section 1 for Test Waveforms and Output Load)
RL=400[J
C L =5 pF

Parameter

Typ

CL=50 pF

Units

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

10

16

ns

tpHL Propagation Delay Time
High to Low Level Output

14

22

ns

tPZH Output Enable Time
to High Level Output

21

35

ns

tPZL Output Enable Time
to Low Level Output

24

37

ns

Min

Max

Min

tpHZ Output Disable Til)'le
from High Level Output

6

11

ns

tpLZ Output Disable Time
from Low Level Output

16

27

ns

1

-

..

6-317

~

~ ~ National

.
~ ~ Semiconductor
i
~
:iE
Lt)

c DM54368/DM74368 Hex TRI-STATE® Inverting Buffers
General Description

Absolute Maximum Ratings (N~te 1)

This device contains six independent gates each of
which performs an inverting buffer function. The outputs have the TRI-STATE feature. When enabled, the
outputs exhibit the low impedance characteristics of a
standard TTL output with additional drive capability to
permit the driving of bus lines without external
resistors. When disabled, both the output transistors
are turneq off presenting a high-impedance state to the
bus line. Thus the output will act neither as a significant
load nor as a driver. To minimize the possibility that two
outputs will attempt to take a common bus to opposite
logic levels, the disable time is shorter than the enable
time of the outputs.

Supply Voltage
Input Voltage
Storage Temperature Range

Connection Diagram

Function Table

7V
5.5V
- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual-In-Line Package

vcc

G2

A6

YI!

Input

Y4

AS

9

' Output

G

A

Y

L
L

L

H

H

L

H

X

Hi-Z

H = High Logic Level
L= Low Logic Level
X = Either Low or High Logic Level
Hi·Z=TRI·STATE (Outputs are disabled)

8
G1

A1

Y1

A2

Y2

A3

Y3

GND

TLiF/6573-1

DMS4368(J)

DM74368.(N).

6-318

Recommended Operating Conditions

Vee

Supply Voltage

VIH

High Level Input
Voltage

V'l

Low Level Input
. Voltage

DM74368

DM54368

Parameter

Symbol

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

V
V

2
0.8

0.8

V

10H

High Level Output
Current

-2

-5.2

mA

10l

Low Level Output
Current

32

32

mA

TA

Free Air Operating
Temperature

70

'C

-55

Electrical Characteristics
Symbol

Parameter

,

125

0

over recommended operating Iree air temperature (unless otherwise noted)
Conditions

V,

Input Clamp Voltage

Vee=Min,I,=-12mA

VOH

High Level Output
Voltage

Vee = Min, 10H=Max
V'l = Max, V'H = Min

VOL

Low Level Output
Voltage

Vee= Min, IOl= Max
V'H = Min, V'l = Max

I,

Input Current@Max
Input Voltage

I'H
I'l

Min

Typ
(Note 1)

2.4

3.1

Max

-1.5

Units

V
V

0.4

V

Vee = Max, V, = 5.5V

1.0

mA

High Level Input
Current

Vee=Max, V,=2.4V ,

40

p.A

Low Level Input
Current

Vee= Max
V,=0.5V
(Note 4)

A

-40

mA

Vee=Max
V,=0.4V
(Note 5)

A

-1.6

\Vee=Max
V,=O.4V

G

-1.6

0.2

10ZH

Off·State Output
Current with High
Level Output
Voltage Applied

Vee=Max, Vo=2.4V
V'H = Min, V'l = Max

40

p.A

10Zl

Off-State Output
Current with Low
Level Output
Voltage Applied

Vee = Max, Vo = 0.4V
V'H = Min, V'l = Max

-40

p.A

los

Short Circuit
Output Current

Vee = Max
(Note 2)

mA

Supply Current

Vee = Max (Note 3)

Icc
Note 1:

AI'

typicals are at

DM54

-40

-115

DM74

-40

-115

Vee = 5V. TA = 25'e.

Note 2: Not more than one output should be shorted at a time.
Note 3: ICC is measured with the data inputs grounded and the output controls at 4.5V.
Note 4: Both

G inputs

are at 2V.

Note 5: Both 13 inputs are at Q,4V.

6·319

59

77

mA

Switching Characteristics

at Vee = 5V and TA = 25"C (See Section 1 for Test Waveforms and Output Load)
RL =4000
CL =5 pF

Parameter

Units

CL=50pF
Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

11

17

ns

tpHL Propagation Delay Time
High 10 Low Level Output

10

16

ns

IpZH Output Enable Time
to High Level Output

21

35

ns

tpZL Output Enable Time
10 Low Level Output

24

37

ns

Min

Typ

Max

Min

t pHZ Output Disable Time
from High Level Output

6

11

ns

tpLZ Output Disable Time
from Low Level Output

16

27

ns

6-320

r-----~---------------------------------------------------.o

s:
.....

~National

....

~ Semiconductor

-s:o

DM7123/DM8123 Quad 2-lnput Data Selectors/Multiplexers

I\)

I\)

Co)

General Description

Features

This device contains four 2-input multiplexers with common input select logic and common output disable circuitry. The DM7123/8123 provides TRI-STATE® outputs.
When the enable/strobe input is at a low logic level, the
outputs of all devices are conventional TTL. However,
when the enable/strobe input is raised to a high logic level,
the outputs of the DM7123/8123 go to the high-impedance
third state. This device provides the designer with TRISTATE and/or low power pin/pin rep,lacements for the
popular 9322 and 54/74157 multiplexers.

• Pin equivalents popular 9322 and 54/74157 multiplexers
• Both conventional TTL and TRI-STATE outputs available
• Both conventional TTL and "one-tenth-power technology" available
• Typical propagation delay 9.5 ns
• Typical power dissipation 200 mW

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

7V
5.5V
-65·Ct0150·C

Nota 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical CharacteristiCS" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Dual-in-Line Package
INPUTS
..---"'----A4
B4

Vee ENABLE

)16

15

14

OUTPUT
Y4

13

INPUTS
..---"'----A3
83

11

12

9

10

-

5
SELECT

OUTPUT
V3

I-

A1

B1

~

Y1
OUTPUT

A2

B2

~

INPUTS

V2
OUTPUT

INPUTS
TLfFf6575·1

8123 (N)

7123 (J)

Function Table
Enable Select
L
L
L
L
H

L
L
H
H

X

~~
A B

L
H

X
X

X
X
X

L
H

6-321

X

Output
Y
L
H
L
H
Hi-Z

CO
....

Co)

Recommended Operating Conditions
DM7123
Symbol

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

Parameter

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2
0.8

-2
16
-55

.125

0

over recommended operating free air
. Min

Conditions

VI

Input Clamp Voltage

Vee = Min, 11= -12 mA

VOH

High Level Output
Voltage

Vee= Min
IOH= Max
VIL= Max
VIH=Mln

2.4

DM81

2.4

V

V

-5.2

mA

16

mA

70

·C

temperat~re (unless otherwise noted)
Typ
(Note 1)

Max
-1.5

DM71

Units

V

0.8

Electrical Characteristics
Symbol

DM8123

Units·
V
V

.'

VOL

Low Level Output
Voltage

Vee= Min, IOL= Max
VIH= Min" VIL= Max

0.4

V

II

Input <::urrent@ Max
Input Voltage

Vee = Max, VI = 5.5V

1

mA

IIH

High Level Input
Current

Vee=Max, VI=2.4V

40

p.A

IlL

Low Level Input
Current

Vee = Max, VI=O.4V

-1.6

mA

10ZH

Off·State Output
Current with High
Level Output
Voltage Applied

Vee= Max, Vo= 2.4V
VIH= Min, VIL= Max

40

p.A

10ZL

Off·State Output
Current with Low
Level Output
Voltage Applied

Vee = Max, Vo=O.4V
VIH = Min, VIL = Max

-"40

p.A

los

Short Circuit
Output Current

Vee = Max
(Note 2)

mA

Supply Current

Vee= Max (Note 3)

Icc

DM71

-30

.,. 70

DM81

-30

-70
40

51

Not. I: Aillypicals are al Vee=5V, TA=25·e.
Not. 2: Not more than one oulput should be shorted at a lime, and the durallon should nol exceed one second.
Not. 3: ICC is measured with all inpuls grounded, and all outputs open.

~

I

6-322

mA

Switching Characteristics

at Vcc = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)

From
(Input)
To
(Output)

Parameter

RL=4000
C L =5 pF
Typ

Min

CL=50 pF
Max

Units

Min

Typ

Max

tpLH-Propagation Delay
Time Low to High
Level Output

Data
to
Output

4

8

15

ns

tpHL Propagation Delay
Time High to Low
Level Output

Data
to
Output

5

11

18

ns

tpLH Propagation Delay
Time Low to High
Level Output

Select
to
Output

5

15

23

ns

tpHL Propagation Delay
Time High to Low
Level Output

Select
to
Output

8

17

24

ns

tPZH Output Enable
Time to High
Level Output

Enable
to

9

18

25

ns

tPZL Output Enable
Time to Low
Level Output

Enable
to

10

23

30

ns

tpHZ Output Disable
Time from High
Level Output

Enable
to

tpLZ Output Disable
Time from Low
Level Output

Enable
to

Q

Q

4

7

11

ns

9

19

27

ns

Q

Q

Logic Diagram

23
B4

(13)

SELECT (1)

Y>
vec

= Pin 16
GND = Pin B

A4
(14)

B3
(10)

A3
B2
(11)
(6)

~1iJ

ENABLE (15)
1(12)
Y4

1(9)
Y3

A2
(5)

-) ,-)

J!
1(7)
Y2

Al

Bl
(3)

~)

(2)

,-)

I
~
(4)
Yl
TLlF/6575·2

6·323

~

ex; ~ National

~ ~ Semiconductor
~
,...

.....
:E

.DM7130/DM8130 Magnitude Comparators

o General Description

Absolute Maximum Ratings

This device offers comparisons to determine equality between two binary words. The DM7130/DM8130 compares
two ten-bit words. A strobe override is provided. When the
strobe Is taken to a high logic level, the output is forced to
a high logic level. The device also features open collector
outputs for expansion.

Features

Supply Voltage
Input Voltage
Storage Temperature Range

• Open-collector outputs for expansion

Connection Diagram
Dual-In-Llne Package
OUTPUT
Al0 Bl0

A9

B9

AS

B8

A7

B7

A6

B6

Y

12
AI

Bl

A2

B2

A3

B3

7V
5.5V
- 65°C to 150°C

Not. 1: The "Absolute Maximum Ratings" are thpse values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

• Typical propagation delay 21 ns
• Typical power dissipation 240 mW

vee

(Note 1)

A4

B4

AS

B5 STROBE GND

8130 (N)

7130 (J)

Function Table

Condition

STROBE
S

Output
y

A = B, A"" B
A=B
A""B

H
L
L

H
H
L

6-324

TLIF16575-1

c

s:.....
....

Recommended Operating Conditions

-s:
Co)

DM7130
Symbol

Parameter

DM8130

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units
V

Vee

Supply Voltage

V IH

High Level Input
Voltage

VIL

Low Level Input
Voltage

0.8

0.8

V

VOH

High Level Output
Voltage

5.5

5.5

V

IOL

Low Level Output
Current

16

16

mA

TA

Free Air Operating
Temperature

70

'C

-55

Electrical Characteristics
Symbol

Pprameter

V

2

2

125

0

over recommended operating free air temperature (unless otherwise noted)
Conditions

VI

Input Clamp Voltage

Vee = Min, 11= -12 mA

leEx

High Level Output
Current

Vee = Min, Vo=5.5V
VIH= Min

VOL

Low Level Output
Voltage

Vec= Min, IOL= Max
VIL = Max

II

Input Current@Max
Input Voltage

IIH

Typ
(Note 1)

Min

Max

Units

-1.5

V

100

I'A

0.4

V

Vee = Max, VI = 5.5V

1.0

mA

High Level Input
Current

Vcc = Max, VI = 2.4V

40

I'A

IlL

Low Level Input
Current

Vcc = Max, VI = 0.4V

-1.6

mA

Icc

Supply Current

Vee = Max (Note 2)

70

mA

Switching Characteristics
Parameter

0.2

48

at Vee=5V and TA=25'C (See Section 1 for Test Waveforms and Output Load)
From
(Input)
To
(Output)

RL;"4000
CL=15 pF
Min

Units

Typ

Max

tpLH Propagation Delay
Time Low to High
Level Output

Data
to
Output

15

25

ns

tpHL Propagation Delay
Time High to Low
Level Output

Data
to
Output

27

40

ns

tpLH Propagation Delay
Time Low to High
Level Output

Strobe
to
Output

9

18

ns

tpHL Propagation Delay
Time High to Low
Level Output

Strobe
to
Output

20

30

ns

Note 1:
Note 2:

All typicals are at Vce= 5V, TA= 25··C.
ICC is measured with all inputs grounded and all outputs open.
6·325

o

C

CO
....

~

.....
C')
.....

co
:E
c

~National

-..... ~ Semiconductor
C')

~

c

DM7131/DM8131 6·Bit Unified Bus Comparators
General Description

Features

The DM7131JDM8131 compares two binary words of twoto-six bits in length and indicates matching (bit-for-bit) of
the two words_ Inputs .for one word -are 54/74 seriescompatible TIL inputs, whereas those of the second word
are high-impedance receivers driven by a terminated data
bus. These bus inputs include 0.65V typical hysteresis,
which provides 1.4V noise immunity. The DM7131JD8131
has active pull-up outputs and goes to the low state upon
equality. The device has an output latch which is strobe
controlled.

•
•
•
•
•

Low bus input current 15 p.A typ
High bus input noise immunity 1.4 V typ
Bus inputs comply with IEEE 488-1975
TTL-compatitlle output
Output latch provision

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

The transfer of information to the output occurs when the
STROBE input goes from a logic" 1" to a logic "0" state.
Inputs may be changed while the STROBE is at the logic
"1" level, without affecting the state of the output. These
devices are useful as address comparators in computer
systems utilizing unified data bus organization.

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual-In-Line Package

116

B6

T6

15

14

2

3

B5

T5

B4

13

12

T4

OUTPUT

11

10

9

6

7

8

r-

1

Bl
Tl
B2
(BUS INPUT) (TTL INPUT)

7V
5.5V
- 65·C to 150·C

Nota 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at Ihese limits. The parametric values defined in the
"'Electrical Characteristics" table are natguarante.d at ,he absolute

-Connection Diagram

vcc

(Note 1)

4

5

T2

B3

T3

- 1
STROBE GND
Tl1F/6576·1

7131 (J)

8131 (N)

Function Table
Condition

Si"iii5BE

T = B, T "" B
T=B
T""B

H
L
L

-latched 10 prevIous state

6-326

Output
DM71/8131
QN-1'
L
H

c
s:
.....
....

I Recommended Operating Conditions

....
(oJ

Symbol

DM7131

Parameter

DM8131

Min

Nom

Max

Min

Nom

Max

Units

Vee

Supply Voltage

4.5

5

5.5

4.75

5

5.25

V

VT+

Postive-Going Input
Threshold Voltage
(Note 1)

1.4

1.75

2

1.45

1.75

1.95

V

VT_

Negative-Going Input
Threshold Voltage
(Note 1)

0.9

1.1

1.35

0.95

1.1

1.3

V

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

2

2

V

0.8

0.8

High Level Output
Current

-0.4

-0.4

mA

10L

Low Level Output
Current

16

16

mA

TA

Free Air Operating
Temperature

70

'C

-55

Electrical Characteristics
Symbol

125

0

V

over recommended operating free air temperature (unless otherwise

Parameter

Min

Conditions

Typ
(Note 2)

Max

VI

Input Clamp Voltage

Vee = Min, h= -12 mA

VOH

High Level Output
Voltage

Vee = Min, 10H= Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee = Min, 10L= Max
VIH = Min, VIL= Max

II

Input Current@Max
Input Voltage

Vee = Max
VI =5.5V

High Level Input
Current

Vee = Max
V I =2.4V

Low Level Input
Current

Vee- Max
VI = 0.4V

TTL

-1.6

Strobe

-2.4

Bus Input
Current

VI =4V

Vee = Max

Short Circuit
Output Current

Vee = Max
(Note 3)

Supply Current

Vcc = Max (Note 4)

IIH

IlL

liN

los

Icc
Not.l.
Nota 2:
Note 3:
Note 4:

-1.5

not~d)
Units
V
V

2.4
0.4

V

TTL

1

mA

Strobe

2

TTL

40

Strobe

80

Vec=OV

15

50

1

50

DM71

-18

-55

DM81

-18

- 55
50

vee= 5V
All typicais are at Vce=5V. TA=2S"C.
Not more than one output should be shorted at a time.
iCC is measured with all inputs grounded and all outputs open.

6·327

74

p.A

mA

p.A

mA

mA

C

s:
CO

....
....

(oJ

....
....
co

('I)

Switching Characteristics

:E

-........
c

('I)

From
(Input)
To
(Output)

I

Parameter

.....

:E

c

at Vcc=5Vand TA=25°C (See

S~ction

1 for Test Waveforms and Output Load)

RL=400{l
C L =15 pF
Min

Units

Typ

Max

tpLH Propagation Delay
Time Low to High
Level Output

TIL
to
Output

20

30

ns'

, tpHL Propagation Delay
Time High to Low
Level Output

TIL
to
Output

20

30

ns

tpLH Propagation Delay
Time Low to High
Level Output

Bus
to
Output

30

45

ns

tpHL Propagation Delay
Time High to Low
Level Output

Bus
to
Output

30

45

ns

tpLH Propagation Delay
Time Low to High
Level Output

Strobe
to
Output

20

30

ns

tpHL Propagation Delay
Time High to Low
Level Output

Strobe
to
Output

20

30

ns

Logic Diagram
DM7118131

Tl~

81 (1)

R

T2~)Dr-

.82 (3)

R

T3~

83 (5)
T4

R

\

L....t

f",?-? .
f'~ ~J

~
~)Dr~
~)

B4 (11) R

(9) OUTPUT

T5(13)
85
R
T6

86 (15) R

R = High Impedance

Bus Receiver

STROBE'
TL/F/6576·2

1

.,....

6·328

r-------------------------------------~---------------------------.o

s:
.....

~National

.....

~ Semiconductor

Co)

~

o

s:

6~Bit

DM7136/DM8136

CD
.....
Co)

Unified Bus Comparators

General Description

Features

The DM7136IDM8136 compares two binary words of two·to·
six bits in length and indicates matching (bit·for·bit) of the
two words. Inputs for one word are 54/74 series·compatible
TTL inputs, whereas those of the second word are high·
impedance receivers driven by a terminated data bus.
These bus inputs include 0.65V typical hysteresis which
provides 1.4V noise immunity. The DM7136IDM8136 has
open·collector outputs which go to the high state upon
equality and is expandable to n bits by collector·ORing. The
device has an output latch which is strobe controlled.

•
•
•
•
•

The transfer of information to the output occurs when the
STROBE input goes from a logic" 1" to a logic "0" state.
Inputs may be changed while the STROBE IS at the logic
"1" level, without. affecting the state of the output. These
devices are useful as address comparators in computer
systems utilizing unified data bus organization.

Connection Diagram

en

Low bus input current 15 /LA typ
High bus input noise immunity 1.4 V typ
Bus inputs comply with IEEE 488·1975
TTL·compatible output
Output latch provision

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

7V
5.5V
- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Dual·ln·Line Package
vee

1,6

B6
15

T6
14

B5

T5

B4

13

12

T4

11

OUTPUT
10

9

Condition

STROBE

Output
DM71/8136

T = B, T", B
T=B
T",B

r-

• Latched

1

2

3

Bl
T1
B2
(BUS INPU!) (TTL INPUT)

7136 (J)

4
T2

5
B3

7

6

--

18

T3 STROBE GND
TLlFf6577·'

8136 (N)

6·329

In

prevIous state

H
L
L

QN-1'
H
L

~
,...
co
:IE
c

i,...
,...

:IE
c

Recommended Operating Conditions
Symbol

DM8138

DM7136

Parameler

Min

Nom

Max

Min

Nom

Max

Unlls

Vee

Supply Voltage

4.5

5

5.5

4.75

5

5.25

V

VT+

Postive·Golng Input
Threshold Voltage
(Note 1)

1.4

1.75

2

1..45

1.75

1.95

V

VT_

Negative-Going Input
Threshold Voltage
(Note 1)

0.9

1.1

1.35

0.95

1.1

1.3

V

VIH

High Level hiput
Voltage

VIL

Low Level Input
Voltage

0.8

0.8

V

VOH

High Level Output
Voltage

5.5

5.5

V

IOL

Low Level Output
Current

16

16

mA

TA

Free Air Operating
Temperature

70

·C

-55

Electrical Characteristics
Symbol

V

2

2

125

0

over recommended operating free air temperature (unless otherwise noted)

Parameler

Min

Condlllons

. TYP
(Nole 2)

Max

Unils

VI

Input Clamp Voltage

Vee = Min, 11= -12 mA

-1.5

V

leEx

High Level Output·
Current

Vee = Min, Vo= 5.5V
VIL= Max, VIH= Min

250

p.A

VOL

Low Level Output
Voltage

'Vee =. Min, IOL = Max
VIH = Min, VIL = Max

0.4

V

II

Input Current@ Max
Input Voltage

Vee = Max
VI =5.5V

TTL

1

mA

Strobe

2

High Level Input
Current

Vee = Max
VI=2.4V

TTL

40

Strobe

80

Low Level Input
Current

Vee = Max
VI=0.4V

TTL

-1.6

Strobe

-2.4

liN

Bias Input
Current

VI=4V'

Vee = Max

Icc

Supply Current

Vec = Max (Note 3)

IIH

IlL

Vcc=OV

Nole 1: Vee=SV
Nole 2: All typicals are at Vee=SV. TA=2S'e.
Nate 3: ICC Is measured with all Inputs grounded and all outputs open.

6-330

15

50

1

50

50

~4

p.A

p.A
mA

mA

,

c
Switching Characteristics

at Vee= 5V and TA= 25°C (See Section 1 for Test Waveforms and Output Load)
From
(Input)
To
(Output)

Parameter

(J)

CL=15 pF

Units

Typ

Max

tpLH Propagation Delay
Time Low to High
Level Output

TTL
to
Output

20

30

ns

tpHL Propagation Delay
Time High to Low
Level Output

TTL
to
Output

20

30

ns

tpLH Propagation Delay
Time Low to High
Level Output

Bus
to
Output

30

45

ns

tpHL Propagation Delay
Time High to Low·
Level Output

Bus
to
Qutput

30

45

ns

tpLH Propagation Delay
Time Low to High
Level Output

Strobe
to
Output

20

30

ns

tpHL Propagation Delay
Time High to Low
Level Output

Strobe
to
Output

20

30

ns

Logic Diagram
DM7118136

T1~

el

(1)

R

.

T2~)D>-

B2(3)

R

T3~

83 (5)

T4

R

.

--I

Cl~
~
)D>~
~
t)

84 (11) R

T5
B5
T6

(13)

(9) OUTPUT

R

B6 (15) R

R = High Impedance
Sus Receiver

STROBE
TLlF/6577-2

6-331

-s::c
Co)

RL=400n

Min

s::

.....
.....

CO
.....
Co)

(J)

i,...

co
:E

~National

c

~ Semiconductor

:E

DM7160/DM8160 Magnitude Comparators

~
,...
,...
c

General Description

Absolute Maximum Ratings

This device offers comparisons to determine equality between two binary words. The DM7160/DM8160 compares
two six-bit words. A strobe override is provided. When the
strobe is taken to a high logic level, the output is forced to
a high logic level. The device also features open-collector
outputs for expansion.

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)
7V,

5.5V
-65·Ct0150·C

Nola 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed, The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Features
• Typical propagation delay 21 ns
• Typical power dissipation 205 mW
• Open-collector outputs for expansion

Connection Diagram

Function Table

DuaHn'·Line Package
vee

A6

86

A5

85

A4

84

OUTPUT
Y

Condition

A = B, A * B
A=B
A*B

TL/F/6578-1

7160 (J)

8160 (N)

6-332

STROBE
S

Output
y

H

H
H

L
L

L

c

3:

Recommended Operating Conditions
Symbol
Vee

Parameter

..........

DM7160
i

Supply Voltage

DM8160

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units

-

V

....en

V

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

0.8

0.8

V

VOH

High Level O\Jtput
.'
Vollage

5.5

5.5

V

10L

Low Level Output
Current

16

16

mA

TA

Free Air Operating
Temperature

70

°C

-55

Electrical Characteristics
Symbol

2

Parameter

125

over recommended operating free air temperature (unless otherwise noted)
Conditions

Typ
(Note 1)

Min

Max

Units

-1.5

V

100

I'A

0.4

V

Vee = Max, VI= 5.5V

1

mA

High Level Input
Current

Vee = Max, VI = 2.4V

40

I'A

Low Level Input
Current

Vee = Max, VI=0.4V

-1.6

mA

Supply Current

Vee = Max (Note 2)

60

mA

VI

Input Clamp Voltage

Vee= Min, II = -12 mA

leEx

High Level Output
Current

Vee= Min, Vo= 5.5V
VIL = Max

VOL

Low Levlli Output
Voltage

Vee = Min, 10L= Max
VIH = Min

II

Input Current@ Max
Input Voltage

IIH
IlL
Icc

0

.1,

Switching Characteristics
Parameter

0.2

41

at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
From
(Input)
To
(Output)

RL = 40011
CL=15 pF
Min

Units

Typ

Max

tpLH Propagation Delay
Time Low to High
Level Output

Data
to
Output

15

25

ns

tpHL Propagation Delay
Time High to Low
Level Output

Data
to
Output

27

40

ns

tpLH Propagation Delay
Time Low to High
Level Output

Strobe
to
Output

9

18

n5

tpHL Propagation Delay
Time High to Low
Level Output

Strobe
to
Output

20

30

ns

Note 1: All typlca,ls are at Vee ~ 5V, TA ~ 25'e,
Note 2: ICC is measured with all inputs grounded and all outputs open.

6-333

~
c
3:
CO

o

~ ~National

~ ~ Semiconductor

~

DM7200/DM8200 4·Bit Magnitude Comparators

~

'General Description

Features
• Typical power dissipation 175 mW
.- • Typical propagation delay 20 ns

These devices compare two binary words of four bits in
length; and the outputs indicate 1) word A > word B, 2)
word A < word B, or 3) word A = word B. A strobe input
overrides all other inputs, and when taken to a high logic
level, places both outputs in the low state. Comparison of
words longer than four bits each may be accomplished
through the use of additional DM7200/DM8200 devices.

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1) ,

7V
5.5V

- 65·C to 150·C

Nol. 1: The "Absolute Maximum Ratings" are those values. beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device opera,ion.

Connection Diagram
Dual-ln·Line Package

Vee

A4

A3

13

114

12

OUTPUT

Al

A2

111

110

19
.......

,.-J
'---(, .J--..

-<1

1

r=;
84

12
83

,......

I ....... '

.

IL--...r-...

......

.-

r'""'

,.,.
Ql

--

r r-

L-.....r'II

......
,......

.........

X

,-;;;:1....:=..cJ.

boo-

r

_

"...,.

8

.----u-

~~

~

1
,....

1

-

"..,

STRoeE

Y

.

D-

.".....

~x"""'"j

x

-

:9:-

4

13

82

15

6

Ne

81

OUTPUT

17
GND

X
A4, B4

are most slgnHlcant bits.

7200 (J)

TLlF/6579·1

8200 (N)

Function Table
Inputs

Outputs

Condition

Strobe

X

Y

Don't Care
A>B
A-________~__~____________-t______________~~~====-

PRESET-

______

~

SERIAL (1)

(10) SERIAL

---,r---.___

OUTPUT

(3) SERIALI

'-

./

.~

_I

TRI-STATE
ENABLE

STROBE

1
1

I

.

TO OTHER
LATCHES

6-358

OA

(~

1

+
.

.

+

IOB(7)
IOC(9)

10 0(13)

I

TL/F/6586-2

r------------------------------------------------------------------,c

3:
......

~National

U1

-

~ Semiconductor

~

en

C

3:

DM7546/DM8546 TRI·STATE® 8·Bit Universal 1/0
Shift Registers

co

U1

a;

General Description

Absolute Maximum Ratings

These circuits are TAl-STATE, a-bit, edge-triggered, universal shift registers which are capable of operating in any of
the following modes: shift left, shift right, parallel load, or
inhibit. Since the clock is edge-triggered, the control lines
which determine the mode of operation are completely independent of the logic level applied to the clock. Designed
for bus-oriented systems, these circuits have their TRISTATE inputs and outputs on the same pins.

Supply Voltage
Input Voltage
Storage Temperature Range

not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Positive-edge triggered clock
"Do nothing" state without gating the clock
Both parallel and serial data lines are TRI-STATE
High impedance state does not impede shift mode with
parallel outputs

Connection Diagram

Dual-In-Line Package
Vee
116

C2

RSl/LSO 110 1

1/02

13

12

15

14

1/03
11

1/04

1

00

10

9

f-

r--

C1

2

3

LSl/RSO 1/08

7V
5.5V
- 65·C to 150·C

Nole 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

Features
•
•
•
•

(Note 1)

4

5

6

1/07

1106

1/05

7
CLOCK

Ie
GND

TLlFJ6587·1

7546 (J)

8546 (N)

6-359

,

Recommended Operating Conditions
DM7546
Symbol

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

DM8546

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V
V

2

2

Units

0.8

0.8

-2
16

V

-5.2

rnA

16

rnA

15

MHz

fCLK

Clock Frequency

0

tw

Clock Pulse Width

18

12

18

12

ns

tsETUP (HIGH)

Serial Data

38

25

38

25

ns

33

22

33

22

ns

21

14

21

14

ns

12

18

tSETUP (HIGH)

Parallel Data

tSETUP (LOW)

Serial Data

CL=50 pF
RL=400n

0

12

ns

-11

0

-11

ns

o -

-11

0

-11

ns

0

-22

0

-22

ns

0

.:. 21

0

-21

ns

tSETUP (LOW)

Parallel Data

tHOLD (HIGH)

Serial Data

0

tHOLD (HIGH)

Parallel Data

tHoLD(LOW)

Serial Data

t HOLD (LOW)

Parallel Data

>

15

18

SETUP AND HOLD TIMES BETWEEN CHANGES IN MODE CONTROL AND CLOCKING
tSETUP

Parallel Load to Right Shift

tSETUP

Parallel Load to Left Shift

tSETUP

Right Shift to Parallel Load

CL=50 pF
RL =400n

32

21

32

21

ns

40

27

40

27

ns

60

40

60

40

ns

tSETUP

Left Shift to Parallel Load

53

35

53

35

ns

tSETUP

Right Shift to Left Shift

33·

21

33

21

ns

tSETUP

Left Shift to Right Shift

5.6

37

56

37

ns

tSETUP

Inhibit to Right Shift

57

38

57

38

ns

tSETUP

Inhibit to Left Shift

65

43

65

43

ns

tSETUP

Right Shift to Inhibit

50

33

50

33

ns

tSETUP

Left Shift to Inhibit

50

32

50

32

ns

tHoLD

Parallel Load to Right Shift

9

6

9.

6

ns

tHOLD

Parallel Load to Left Shift

6

4

6

4

ns

tHOLD

Right Shift to Parallel Load

0

-13

0

-13

ns

tHOLD

Left Shift to Parallel .Load

0

-46

0

-46

ns

tHOLD

Right Shift to Left Shift

0

-10

0

-10

ns

tHOLD

Left Shift to Right Shift

0

-23

0

-23

ns

tHOLD

Inhibit to Right Shift

0

-18

0

-18

ns

tHOLD

Inhibit to Left Shift

0

-16

0

-16

ns

t HOLD

Right Shift to Inhibit

0

-12

0

-12

ns

-29

.0

-29

tHOLD

Left Shift to Inhibit

0

TA

Free Air Operating
Temperature

-55

&360

125

0

ns
70

·C

c

Electrical Characteristics
Symbol

. Parameter

over recommended operating free air temperature (unless otherwise noted)

Conditions

Min

Typ
(Note 1)

Max
-1.5

Units
V

VI

Input Clamp Voltage

Vcc=Mln, 11= -12 mA

VOH

High Level Output
Voltage

Vee = Min, 10H = Max
Vll= Max, VIH = Min

VOL

Low Level Output
Voltage

Vee= Min, 10l= Max
VIH = Min, Vil = Max

0.4

V

II

Input Current@Max
Input Voltage

Vee=Max, VI=5.5V

1

mA

IIH

High Level Input
Current

Vee= Max
VI = 2.4V

C2

80

p.A

Other

40

Low Level Input
Current

Vee= Max
VI = 0.4V

10ZH

Off·State Output
Current with High
Level Output
Voltage Applied

Vee = Max, Vo=2.4V
VIH = Min, Vil = Max

40

p.A

10Zl

Off·State Output
Current with Low
Level Output
Voltage Applied

Vee=Max, Vo=0.4V
VIH= Min, Vll= Max

-40

p.A

los

Short Circuit
Output Current

Vee= Max
(Note 2)

DM75

-30

-70

mA

DM85

-30

-70

Supply Current

Vee = Max

DM75

80

115

DM85

80

125

III

Icc

V'

2.4

C2

-3.2

Other

-1.6

Nol.,: Aillypicals are at Vee=SV. TA=2s'e.
Nole 2: Not more than one output should be short~d at a time.

6·361

mA

mA

s:

"'"

~
en

-s:
C

CO
U1
.".

en

Switching Characteristics at Vee =5V and TA =25"C
Parameter

From
(Input)
To
(Output)

(See Section 1 for Test Waveforms and Output Load)
RL =4000

CL=5 pF
Min

Typ

CL=50 pF
Max

f MAX Maximum Clock
Frequency
tpLH Propagation Delay
Time Low to High
Level Output
tpHL Propagation Delay
Time High to Low
Level Output
tPZH Output Enable
Time to High
Level Output

Output
Control to

tPZH Output Enable
Time to High
Level Output

Mode Control
(C1/C2) to

tpzL Output Enable
Time to Low
Level Output

Output
Control to

tpZL Output Enable
Time to Low
Level Output

Mode Control
(ClIC2)to

tpHz Output Disable
Time from High
Level Output

Output
Control to

tpHZ Output Disable
Time from High
Level Output

Mode Control
(C1/C2) to

tpLZ Output Disable
Time from Low
Level Output

Output
Control to

tpLZ Output Disable
Time from Low
Level Output

Mode Control
(ClIC2)to

Units

Min

Typ

Max

15

22

;

16

24

ns

27

40

ns

22

33

ns

13

20

ns

18

27

ns

15

23

ns

MHz

Q

Q

Q

Q

5

8

ns

9

14

ns

16

24

ns

17

26

ns

Q

Q

Q

Q

6·362

Function Table
00

C1

C2

Mode of
Operation

Stllte of
Para lie' 110

L
H
X
L
H
L
H

H
H
H
L
L
L
L

H
H
L
H
H
L
L

Inhibit
Inhibit
Parallel Load
Right Shift
Right Shift
Left Shift
Left Shift

QOUT
Hi-Z'
Data In
QOUT
Hi-Z'
QOUT
Hi-Z'

00 = Output Disable

eel, C2

State of
Serial 1/0
RS'/LSO

LS'/RSO

Hi-Z'
Hi-Z'
Hi-Z'
Data In
Data In
QOUT 1
QOUT 1

Hi-Z'
Hi-Z'
Hi-Z'
QOUT8
QOUT8
Data In
Data In

= Mode Controls)

'Both Input and Output of the 1/0 pin are in the high impedance slate.

Logic Diagram
00

(1)

Cl--~~~~~=E~

____________________________________________

·TRI-STATE GATE

~

TLlFJ6587·2

6-363

Typical Applications
Cascading Devices
TO COMMON BUS

I/O 1 • •
OTHER
DEVICES
OR
COMMON
BUS

• .1/08

.1: ..

1/01' •

I I I I I I I I
LSI/RSO

~

.~. • • I/O 8
I I I I I I II

1I0B

I/O l ' •

I I I I I I I I

..--

LSI/RSO

DM7546

LSIIRSO

DM7546

DM7546

RSI/LSO

RSI/LSO

1 1
1

1 1
1

1 1

OTHER
DEVICES
OR
COMMON
BUS

C1

1

C2
CP

00
TLIFI6587·3

Serial Data Transfer to a First In-First Out Storage Medium
TO COMMON BUS

I/O 1 ·

t

• • 1108

•

I I I I I I I I
TRI-STATE BUS OF
FIRST IN-FIRST OUT
STORAGE MEDIUM

R::~

LSI/RSO

• • I/O 8

I I I I I I 11
LSI/RSO

RSI/LSO

I - ···DEVICES····--.

DM7546

I

OTHER

I/O 1· •

I

t-

DM7546

I

1

1

00
CP

C2

n.

C1

TRI-STATE BUFFER (7D93/94)..r
DISABLE THIS OUTPUT
WHEN RECEIVING DATA
FROM STORAGE MEDIUM

SERIAL DATA
I/O CONTROL
TLlF16587·4

6-364

c

Typical Applications

s:
......

(Continued)

CI1

-'="

-s:c

Typical Parallel Load, Right Shift, Left Shift and Inhibit Sequences

0)

ClK
00

I

r--l~

I

Cl

I

---l~I------------------~--~Ii --------~------------------+-~----~
I

C2~

I
I

I
RSl/lSO

________~__________________~r--l~______~____~r----

I

--U!
r"lJr----I
~-----+-~I----,----------+-,-I
I

I

1/01

I

1/02

1/03
1/04

·1/05

1106

1/07
1/08

lSI/RSO

I

-l

I-

-I

f-

I

OUTPUT
OUTPUT
PARAllEL I - - - - - - - R I G H T SHIFT _ _-=Dc;:IS::.:AB=:l:::.E_ _ _ _ _ _ _ _ LEFT SHIFT _ _ _--=Dc;:IS::.:A=Bl:;Et_ _ INHIBIT _ _
lOAD
TLlF/6587·5

6·365

CO
CI1

-'="

0)

~ ~ National

.
~ ~ Semiconductor
~

~
~

DM7556/DM8556 TRI-STATE® Programmable
Binary Counters
General Description
These circuits are synchronous, edge-sensitive, fullyprogrammable 4-bit counters. The counters feature both
conventional totem-pole and TRI-STATE outputs; such that
when the outputs are in the high-impedance mode, they can
be used to enter data from the bus lines. In addition, the
clear input operates completely independent of all other inputs. During the programming 'operation, data is loaded into
the flip-flops on the positive-going edge of the clock pulse.
To facilitate cascading of these counters, the MAX COUNT
output can be tied directly into the count enable input of the
next counter.

• Fully independent clear
• Synchrono~s loading
• Cascading circuitry provided internally

'Absolute Maximum Ratings

7V

Supply Voltage
Input Voltage
Storage Temperature Range

Features
• Typical clock frequency 35 MHz
• TRI-STATE outputs

!

5.5V
-65'Ct0150'C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram
Dual-In-Line Package
vcc

MAX
COUNT

1/00

IIOC

15

14

13

116

00

I/0a

12

IIOA CLOCK
10

11

.--

9

<

2

1

3

4

Oc

5

RESET

Os

6

7

Is

OA

LOAD

GNO

TLlFf6588·1

·7556 (J)

8556 (N)

Function Table
1/0 Ports

Control Inputs
LOAD

CE

CLK/

00

H
H
H
H
L
H
H

X
X
IX
X

X
X

H
L
L

t
t
t

L
H
L
H
L
L
H

L
L

Reset IIOA IIOB

H
H
L
L
L
L
L

L

L

Active Outputs

IIOC 1/00
L

L

Z

Z

Z

Z

·QAO

aeo

Qco

Qoo

Z

Z

•

Z

Z

b
c
. COUNT

d

Z

Z

Z

Z

DA

DB

L
L
aAD
QAO
A

L
L
Qeo
aeo

DC

L
L
Qco
aCO
C
B
COUNT
COUNT

Do
L
L
Qoo
Qoo
0-

The 110 pins are used aa inputs when they are TR1·STATED, and the LOAD Inpul is Low. They are outputs and active when LOAD
inpulls High and 00 II Low.
H ;; High Level (Steady Siale)
L

= Low Level (Steady State)

X ;; Don't Care Including tranlltione
B, b, C, d

(Note 1)

= The,level 01 the steady stata Input al Inputs A. e, C, 0 respectively
= The level of Q". 0B. Oe. Co repectlvely, before the indicated

0AO. Ceo. Oeo. 000
established.

6-366

steady slale inplJt condillons were

Recommended Operating Conditions
Symbol

Parameter

DM8556

DM7556
Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units
V

Vcc

Supply Voltage

VIH

High level Input
Voltage

V1L

low level Input
Voltage

IOH

High level Output
Current

-2

-5.2

mA

IOl

low level Output
Current

16

16

mA

fClK

Clock Frequency

25

MHz

tw

Pulse Width

2

0.8

0.8

0

25

0

Clock

25

25.

Clear

20

20

load

30

30

Setup
Hold

-30

tSETUp(1)

Setup Time High
logic level

Data

25

load

30

tHOlD(1)

Hold Time High
logic level

Data

5

load

-10

Setup Time low
logic level.

Data

30

load

25

Hold Time low
logic level

Data

5

load

-10

tSETUP(O)
tHOlD(O)

Free Air Operating
Temperature

TA

-55

125

,

6·367

0

V

ns

30

Count Enable
Time

tCE

V

2

ns
ns
ns
ns
ns

70

·C

Electrical Characteristics
Symbol

Parameter

over recommended operating free air temperature (unless otherwise noted)
Conditions

Min

Typ
(Note 1)

Max

Units

VI

Input Clamp Voltage

Vee = Min, 11= -12 rnA

VOH

High Level Output
Voltage

Vee=Min,loH=Max
Vil = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee = Min, IOl= Max
VIH= Min, Vll = Max

0.4

V

II

Input Current@ Max
Input Voltage

Vee = Max, VI = 5.5V

1

rnA

IIH

High Level Input
Current

Vee = Max, VI =2.4V

40

p.A

III

Low Level Input
Current

Vee = Max, VI =O.4V

-1.6

rnA

10ZH

Off-State Output
Current with High
Level Output
Voltage Applied

Vee = Max, Vo= 2.4V
VIH= Min, Vll= Max

40

p.A

10Zl

Off-State Output
Current with Low
Level Output
Voltage Applied

Vee= Max, Vo=0.4V
VIH= Min, Vll = Max

-40

p.A

los.

Short Cireuit
Output Cu.rrent

Vee = Max
(Note 2)

rnA

Supply Current

Vee= Max

,
lee

I
I

-1.5
2.4

,

DM75

-25

-70

DM85

-25

-70
75

Note 1: All typlcals are at Vee=SV, TA=2S'e.
Note 2: Not more than one output should be shorted at a time.

\

/

,

6-368

V
V

100

rnA

a

Switching Characteristics
Parameter

at Vee = 5V and TA = 25"C (See Section 1 for Test Waveforms and Output Load)

From
(Input)
To
(Output)

Max

Typ

fMAX Maximum Clock
Frequency

Min

Typ

25

35

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
Output

15

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
Output

tpLH Propagation Delay
Time Low to High
Level Output

Units
Max

22

ns

34

44

ns

Clock
to
MAX·CNT

23

33

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
MAX·CNT

23

33

ns

tpHL Propagation Delay
Time High to Low
Level Output

Reset
to
Output

30

44

ns

tPZH Output Enable
Time to High
Level Output

Output
Disable to

13

20

ns

tpZL Output Enable
Time to Low
Level Output

Output
Disable to

14

20

ns

tpHZ Output Disable
Time from High
Level Output

Output
Disable to

tpLZ Output Disable
Time from Low
Lever Output

Output
Disable to

Q.

Q

6

12

ns

12

20

ns

Q

..

6·369

c

00

MHz

I

Q

-s::
Q)

C L =50 pF

CL=5 pF
Min

Cit

en

I

RL =40011

s::

en
en

Q)

DM7556IDM8556

inO

&'

7518556
00(12)

IIOA

J:n,-

CP

CLOCK

(1)

:J)o-.

(9)

r-...

0

~

IIOC

::::0.-.

~"'
~

Co

---, .--

4

r-CP

::::[»- ~S

~" ,
-

~

r-CP

0

~ ~s

'~

-Ofl

110a

7)

~ -

CE

;

-Of)

-Of~
U5liD'

CO

r--

:::[)o- HS

~S

~"~.

CD

'--j'--

~

CP

Q

:3

100

Q

.

~"---, r--CD

'--r-

r-

(4)

RESET

)
GND

= (8)

I

(6)
QA

(5)

Oa

(3)
QC

MAX
COUNT

(2)

00
TL/F/6588-2

/'

Timing Diagram

75/8556 Typical Clear, Preset, Count, Inhibit Sequence
RESET~~

_______________________________________________________________

LOAD _ _ _ __,

LJ

OUTPUT

DISABLE _______________________....
COUNT
DISABLE
_________--'-__________________________________________

~__'

CLOCK

I/O

(C) ==l-1
==. . ._____________________If!L------r---------------------L________________

I/D (D)

~

Q(C)==~
Q

(D)=: '..'________--'

co~~~::J~---------------------------------------,LJ
DISABLE

I~ I~ 1----_--I-D-,SA-BL-E-I-c~-U-N-T---------~.-I~I
___
:O~·I
OUTPUTS
1/0 USED
AS INPUTS-

TLlFI6588·3

Sequence
(1) Clear to zero.
(2) Load binary five.
(3) Count six, seven, eight. nine. ten, eleven, twelve. thirteen. fourteen. fifteen.

iero.
(4) Oisable TRI-STATE outputs.
(5) Disable counter.
(6) Count to one.

6·371

Switching Time Waveforms
Clock and Reset Voltage

RESET

ov

CLOCK

OUTPUT

MAX
COUNT

Count Enable and Clock

E~~~~~----------------~

CLOCK

\~-----

OUTPUT

TL/F/6588·5

Load, Data and Clock

LOAD

DATA

CLOCK

OUTPUT

"I-I---J/
TL/F/6588-6

Output Disable
DISABLE

1.5V

1.5 V

I

IZHYrOUTPUT

-----'I

1/

~J:~Z

--""1'",..1

0.5 V

-0.5 V

6·372

\

15V

~.

---- ~
tI
lZL

0.5 V

TL/F/6561!-7

r---~-----------------------------------------------------'O

3:
......

.
~ Semiconductor

~National

CD
-"

-o
Co)

3:
CD
CD

-"

DM7613/DM8613 Dual/Quad Gated Flip-Flops

Co)

General Description

Absolute Maximum Ratings

The OM7613/8613is a quad, gated, Ootype flip-flop with
common clock, common clear, and gated input. When a
high logic level is applied to the gated input, data entry to
the flip-flop is inhibited.

Supply Voltage
Input Voltage
Storage Temperature Range

Features

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

•
•
•
•
•

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram
Dual-In-Line Package
G4

D4

04

G3

03

Q3

CLEAR

9

a
CLOCK

7V
5.5V
- 65·C to 150·C

not be operated at these limits. The parametric values defined in the
"Electrical CharacteristiCS" table are not guaranteed at the absolute

Positive-edge triggered
Do-nothing state
Buffered inputs
Typical toggle rate 30 MHz
Typical power dissipation 290 mW

VCC

(Note 1)

G1

D1

Q1

G2

02

Q2

GNO
TL/Ff659Q-1

8613 (N)

7613 (J)

6-373

,...

M

~ , Recommended Operating Conditions

:E

c

Symbol

""
c

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

fCLK

Clock Frequency

tw

Pulse Width

co

:E

tsu

DM7613

Parameter

,...

M

Setup Time

tH

All Hold Time

TA

Free Air Operating
Temperature

Nom

4.5

5

DM8613
Max
5.5 .

Min

Nom

Max

4.75

5

5.25

2

2

0.8

-0.8

-0.8

mA

16

16

mA

20

MHz

0

24

16

24

16

Clear

27

18

27

18

0

24

16

24

16

G

30

21

30

21

Parameter

125

ns

ns

0

over recommended operating frse
Conditions

V

ns

0

0
-55

V

0.8

20

0

Units

V

Clock

Electrical Characteristics
Symbol

Min

70

DC

~ir temperature (unless otherwise noted)
Min

Typ
(Note 1)

Max

VI

Input Clamp Voltage

Vcc= Min, II = -12 mA

VOH

High Level Output
Voltage

Vcc=Min,loH=Max
VIL = Max, VIH = Min

VOL

low Level Output
Voltage

Vcc= Min, 10L= Max
VIH= Min, VIL= Max

0.4

V

II

Input Current@ Max
Input Voltage

Vcc= Max, VI= 5.5V

1

mA

IIH

High Level Input
Current

Vcc=Max, VI=2.4V

40

p.A

IlL

Low Level Input
Current

Vcc= Max, VI= 0.4V

-1.6

mA

los

Short Circuit
Output Current

Vcc= Max
(Note 2)

-18

-55

mA

-18

-55

Supply Current

Vcc= Max (Note 3)

Icc

I DM76
I DM86

Nota 1: All typicals are at VCC = 5V. TA = 25'C.
Nota 2: Not more than one output should be shorted at a time.
Nota 3: ICC is measured with CLEAR/CLOCK at 3V. all other inputs at OV.

6·374

-1.5

Units

2.4

V
V

58

76

mA

Switchi ng Characteristics

at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)·

From
(Input)
To
. JOutput)

Parameter

RL=4001l
CL=15 pF

fMAX Maximum Clock
Frequency
tpLH Propagation Delay
Time Low to High
Level Output

Clock
to

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to

Min

Typ

20

30

Units
Max
MHz

17

24

ns

22

33

ns

21

31

ns

a
a
a

Function Table
13
D

G

CLR

H
L
X

L
L
H

x

x

L
L
L
H

°n+1
H
L

an
L'

• Asynchronous Transition

X

= Don't Care

Logic Diagram
76/8613

CLEAR

(9)

----

T

!

CLEAR
Q

(4) (7) (10) (13)
Q

0
(3)(6)(11)(14)

0

.--

G (2)(5)(12)(15)

CLOCK

CP

1____

(1)

Tl/F/6590-2

6·375

~National

~ Semiconductor

DM7875A1DM8875A, DM7875B/DM8875B TRI·STATE®
4·Bit Parallel Binary Multipliers
General Description

Features

These circuits are capable of multiplying together two 4-bit
binary numbers when used together in pairs_ The
DM7875A/8875A provides the most significant four bits,
and the DM7875B/8875B provides the least significant
four bits. Since the largest number that can be obtained by
multiplying two 4-bit numbers is 225 (15 x 15), the eight
output pins (four from each pack'age) are sufficient to
produce this number. Both the multiplier and the multiplicand must be connected to the eight input pins of each device. These devices are pin compatible with the
SN54284/74284, and SN54285/74285; but have the advantage that these circuifs provide either standard totempole TTL or TRI-STATE outputs_ A gated two-input strobe
control is provided. When either one, or both, of the strobe
inputs is raised to a high logic level the outputs are forced
into the high-impedance state. Thus, multiple devices may
be cqnnected to a common bus line.

• Pin compatible replacements for
SN54284/74284 (DM7875A/8875A)
SN54285/74285 (DM7875B/8875B)

Connection Diagram'

AC Test Circuit

• TRI-STATE outputs
• Typical propagation delay 35 ns

Absolute Maximum Ratings

(Note 1)
7V
5_5V

Supply Voltage
Input Voltage
Storage Temperature Range

- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual·ln-Line Package

. vlcc.

OUTPUTS
~.----------~

S2

V4

16

STROBE
~

15

SI
14

13

P2

PI

P3

11

12

10

S_OV

P4
9
OUTPUT

DM7S7S/
DM8S7S

.......

D1

1k

~,

-

~,
~,

1

V3

12 13 14 Is 16 17 .10
V2

V1

X4

X1

X2

X3

TLlF16592-2

GND

TUF16592-1

7875A(J)
78758 (J)

8875A(N)
88758(N)

6-376

c

s:

I

Recommended Operating Conditions
Symbol

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level Input
Voltage

10H
10l
TA

DM7875A

~
......

DM8875A

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units

C

V
V

2

High Level Output
Current

-5.2

-2

V
mA

Low Level Output
Current

16

16

mA

C

s:
......
CO
......

-s:
to

C

Free Air Operating
Temperature

-55

125

0

·C

70

CO
CO

......

U1

to

Parameter

Conditions

Min

Typ
(Note 1)

Max

Units

VI

Input Clamp Voltage

Vee= Min, h= -12 mA

VOH

High Level Output
Voltage

Vee= Min, 10H= Max
Vil = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee = Min, 10l= Max
VIH = Min, Vil = Max

II

Input Current@Max
Input Voltage

Vee = Max, VI = 5.5V

IIH

High Level Input
Current

Vee = Max, VI = 2.4V

III

Low Level Input
Current

Vee=Max, VI=0.4V

10zH

Off·State Output
Current with High
Level Output
Voltage Applied

Vee = Max, Vo=2.4V
V1H = Min, Vil = Max

40

)LA

lozl

Off·State Output
Current with Low
Level Output
Voltage Applied

Vee= Max, Vo= 0.4V
VIH = Min, Vil = Max

-40

)LA

los

Short Circuit
Output Current

Vee= Max
(Note 2)

mA

Supply Current

Vee= Max

I
I

-1.5

.

0.4

V

1

mA

40

)LA

-1

DM78

-20

-70

DM88

-20

-70
75

-

lee is measured with all Inputs grounded.

6·377

V
'V

2.4

Note 1: All typicals are at Vee; 5V, TA; 25'e.
Note 2: Not more than one output should be shorted at a time.
Note 3:

J;.

U1

over recommended operating free air temperature (unless otherwise noted)

lee

CO

CO
......

U1

0.8 .

0.8

DM78/8875A Electrical Characteristics
Symbol

-s:~

110

mA

mA

DM78/8875A Switching Characteristics

at Vee

=5V and TA =25°C

(See Section 1 for Test Waveforms and Output Load)

RL=400n
CL=5 pF

Parameter

Typ

CL=50 pF
. Max

Units

Typ

Max

tpLH Propagation Delay
Time Low to High
Level Output

35

60

ns

tpHL Propagation Delay
Time High to Low
Level Output

35

60

ns

tPZH Output Enable
Time io High
Level Output

20

30

ns

tPZL Output Enable
Time to Low
Level Output

20

;30

ns

Min

Min

tpHZ Output Disable
Time from High
Level Output

20

30

ns

tpLZ Output Disable
Time from Low
Level Output

20

30

ns

r

-

6·378

Recommended Operating Conditions
Symbol

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

V IL

Low Level Input
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

DM8875B

DM7875B
Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units
V
V

2
0.8

0.8

V

-2

-5.2

mA

16

16

mA

70

·C

-55

125

0

DM78/8875B Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol

Parameter

Min

Conditions

Typ
(Note 1)

Max

Units

VI

Input Clamp Voltage

Vee = Min, 11= -12 mA

VOH

High Level Output
Voltage

Vee = Min, IOH = Max
VIL = Max, VIH = Min

VOL

·Low Level Output
Voltage

Vee = Min, 10L= Max
VIH = Min, VIL = Max

0.4

V

-1.5
2.4

V
V

II

Input Current@Max
Input Voltage

Vee= Max, VI= 5.5V

1

mA

IIH

High Level Input
Current

Vee= Max, VI= 2.4V

40

p.A

IlL

Low Level Input
Current

Vee = Max, VI = O:4V

10ZH

Off·State Output
Current with High
Level Output
Voltage Applied

Vee= Max, Vo=2.4V
VIH= Min, VIL= Max

40

(.tA

10ZL

Off·State Output.
Current with Low
Level Output
Voltage Applied

Vee = Max, Vo=0.4V
VIH= Min, VIL= Max

-40

~A

los

Short Circuit
Output Current

Vee = Max
(Note 2)

mA

Supply Cl,lrrent

Vee = Max (Note 3)

Icc

I

I

-1

DM78

-20

-70

DM88

-20

-70
75

Notol: Alltypicals are at Vee=5V, TA=25'e.
. Noto 2: Not more than one output should be shorted at a time.
Noto 3: ICC Is measured with all Inputs grounded.

6-379

110

mA

mA

DM78/88758 Switching Characteristics

at

Vee = 5V and TA = 25·C

(See Section 1 for Test Waveforms and Output Load)
RL=4000
C L =5 pF

Parameter
Min

Units

CL=50 pF

Tjp

Min

Typ

Max

35

60

ns

tpHL Propagation Delay
Time High to Low
Level Output

35

60

ns

tpZH Output Enable
Time to High
Level Output

20

. 30

ns

tPZL Output Enable
Time to Low
Level Output

20

30

ns

tpLH Propagation Delay
Time Low to High
Level Output

Max

,

tpHZ Output Disable
Time from High
Level Output

20

30

ns

tpLZ Output Disable
Time from Low
Level Output

20

30

ns

Typical Application

X

~/-

X4-MOST SIGNIFICANT BI~
X3
X2
~
Xl- LEAST SIGNIFICANT BIT

\::

Y4
Y3
Y2
Yl

MOST
P4 -.: SIGNIFICANT
BIT

-

P3
DM7875AI
~~ DMB875A P2 '-X2
Xl,
Pl I-XXV

Y4-MOST SIGNIFICANT BI~
Y3
Y Y2
Yl-LEAST SIGNIFICANT elT

r-

\:

4

P4 I-Y4
Y3
Y2
P3 I-Yl DM7875BI
~~ DMB875B P2 I-LEAST
X2
SIGNIFICANT
Xl
Pl
BIT
TLIFI6592-3

r--

Switching Time Waveforms
tLZ & tHZ

tZL & tZH
STROBE ~ 1.5V

STROBE~

X, Y
INPUTS _-' __
OUTPUTS

INPUT PULSES:
Ir
f

:=

-

lTv-----tPHL.r,\:1.5V

OUTPUTS

-

STROBE ~1.5V

tZLIT
'{O.5V

_1.5V

f-l.5V
tpLH

TLlFI~592·4

-

tr

tZH

If S 10 ns

= 1 MHz

6·380

-

V
TLIF16592·5

tLzlO.5V

-

~1.5V

t
I

ACTUAL "1"
VOLTAGE

1-

",1.5 V

OUTPUTS
ACTUAL "0"
VOLTAGE

-

:I

tHzl~v

~1.5V

TLIF16592·6

.-----------------------------------------------------~-----------;c

:s:

~National

co
co
U)
co

~ Semiconductor

-:s:
c

DM8898/DM8899 TRI-STATE® BCD to Binary/Binary
to BCD Converters

co

f8

U)

General Description
These circuits are the TRI-STATE version's of the popular
BCD to binary and binary to BCD converters, DM74184 and
DM74185A respectively. They are derived from the 25B-bit
ROM, DM8598. Emitter connections are made to provide
direct read out of converted codes at outputs Y8 though
Y I, as shown in the truth tables. Both converters comprehend the fact that the least significant bits (lSB) of the binary and BCD codes are logically equal, and in each case
the lSB bypasses the converter. Thus a B-bit converter is
produced in each case, and both devices are cascadable.

Y6, Y7, and Y8 are not required in the BCD-to-binary conversion, they are utilized to provide these complement
codes as specified in the function table when the devices
are connected as shown.
DM8899 BINARY-TO-BCD CONVERTERS

An overriding enable input is provided on each converter
which, when taken high, inhibits the function, causing all
outputs to go' into the high-impedance state. For this
reason. alld to minimize power consumption, unused outputs Y7 and Y8 of the 185A and all "don't care" conditions
of the 184 are programmmed high.

b. Examine each BCD decade. If the sum is greater than
four, add three and shift left one bit.

The function performed by these B-bit binary-to-BCD converters is analogous to the algorithm:
a. Examine the three most significant bits. If the sum is
greater than four, add three and shift left one bit.

c. Repeat step b until the least-significant binary bit is in
the least-significant BCD location.

DM8898 BCD-TO-BINARY CONVERTERS

Features

The B-bit BCD-to-binary function of the DM8898 is analogous to the algorithm:

• TRI-STATE versions of DM74184, DM74185A
• Typical propagation delay 30 ns

a. Shift BCD number right one bit and examine each decade_ Subtract three from each 4-bit decade containing a binary value greater than seven.

Absolute Maximum Ratings

b. Shift right, examine, and correct after each shift until
the least significant decade contains a number smaller than eight and all other converted decades contain
zeros.

Supply Voltage
Input Voltage
Storage Temperature Range

In addition to BCD-to-binary conversion, the DM8898 is programmed to generate BCD 9's complement or BCD lCl's
complement. In each case, one bit of the complement code
is logically equal to one of the BCD bits; therefore, thes!!
complements can be produced on three lines. As outputs

Connection Diagram

define the conditions for actual device operation.

BINARY SELECT

ENABLE

G
lS

,.

2

3

o

OUTPUT

c

ye

A

9

13

12

11

10

•

S

•

7

Ie

~~~1__~Y~2__~Y3~~Y~.--~yS~~y~.--~Y7J

GND

'1.

,...-

1

7V
5_5V
- 65·C to 150·C

Nole 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values qefined in the
"Electrical Characteristics" table are not guaranleed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will

Dual-In-line Package
Vee

(Note 1)

OUTPUTS

8898 (N)

TLlFf6593·1

8899 (N)

6-381

Recommended Operating Conditions
Symbol

DM8898

Parameter

Vee,

Supply Voltage

VIH~

High Level Input
Voltage

Vil

Low Level Input
Voltage

10H

High Level .output·
Current

10l

Low Level .output
Current

TA

Free ·Air .operating
Temperature

Min

Nom

Max

4.75

5

5.25

Units
V
V

2

V

0.8
-5.2

mA

12

mA

70

·C

0

DM8898 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)

,
Conditions

Min

Typ
(Note 1)

Symbol

Parameter

VI

Input Clamp Voltage

Vee = Min, 11= -12 mA

VOH

High Level .output
Voltage

Vee = Min,loH= Max
Vil = Max, VIH = Min

Val

Low Level .output
Voltage

Vee = Min, 10l= Max
VIH = Min, Vil = Max

0.4

V

II

Input Current@ Max
Input Voltage

Vee = Max, VI- 5.5V

1

mA

IIH

High Level Input
Current

Vee = Max, VI = 2.4V

40

p.A

III

Low Level Input
Current

Vee = Max, VI=0.4V

-1.6

mA

10ZH

.off-State .output
Current with High
Level .output
Voltage Applied

Vee = Max, Vo=2.4V
VIH = Min, Vil = Max

40

p.A

10Zl

.off-State .output
Current with Low
Level .output
Voltiige Applied

Vee = Max, Vo=0.4V
Vi"H = Min, Vll= Max

-40

p.A

los

Short Circuit
.output Current

Vee = Max (Note 2)

-70

mA

Icc

Supply Current

Vee- Max

99

mA

Units

Max
-1.5

V
V

2.4

-20

,
70

Nole I: All typlcals are at Vee=5V, TA=25°q.
Nole 2: Not more than one out'put should be shorted at a time.

,

\

6-382

c
DM8898 Switching Characteristics

3:
co
co
~

at Vee = 5V and TA = 25'C

(See Section 1 for Test Waveforms and Output Load)
RL=400{!
Parameter

CL=5 pF
Min

Units

.CL=50pF

Typ

Typ

Max

29

50

ns

tpHL Propagation Delay
Time High to Low
Level Output

33

50

ns

tPZH Output Enable
Time to High
Level Output

16

25

ns

tPZL Output Enable
Time to Low
Level Output

26

40

ns

tpLH Propagation Delay
Time Low to High
Level Output

Max

Min

,

tpHZ Output Disable
Time from High
Level Output

13

20

ns

tpLZ Output Disable
Time from Low
Level Output

24

36

ns

Recommended Operating Conditions
Symbol

DM8899
Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

Min

Nom

Max

4.75

5.0

5.25

0.8

-

6·383

V
V

2

0

Units

V

-5.2

rnA

12

rnA

70

'C

c
3:
g:

CD
CD

CJ)

!::E

m
c

co

co

::E

c

DM8899 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol

Parameter

Conditions

Min.

Typ
(Note 1)

Max

Units

VI

Input Clamp Voltage

.Vee= Min, 11= -12 mA

VOH

High Level Output
Voltage

Vee = Min, 10H = Max
Vil = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee = Min, 10l= Max
VIH = Min, Vll= Max

0.4

V

II

Input Current@ Max
Input Voltage

Vee = Max, VI = 5.5V

1

mA

IIH

High Level Input
Current

Vee = Max, VI = 2.4V

40

/LA

IlL

Low Level Input
Current

Vee = Max, VI = 0.4V

-1.6

mA

10zH

Off·Stata Output
Current with High
Level Output
Voltage Applied

Vee=Max, Vo=2.4V
VIH = Min, Vil = Max

40

10Zl

Off·State Output
Current with Low
Level Output
Voltage Applied

Vee = Max, Vo= 0.4V
'VIH = Min, Vil = Max

-40

/LA

los

Short Circuit
Output Current

Vee = Max' (Note 2)

-70

mA

Icc

Supply Current

Vee = Max

99

mA

-1.5

J

2.4

V
V

-20
70

/LA'

DM8899 Switching Characteristics
at Vee= 5V and TA= 25°C (See Section 1 for Test Waveforms·and Output Load)
RL = 40012
Parameter

C L =5 pF
Min

Typ

CL=50 pF
Max

Units

Typ

Max

tplH Propagation Delay
Time Low to High
Level Output

29

50

ns

tpHl Propagation Delay
Time High to Low
Level Output

33

50

ns

tPZH Output Enable
Time to High
Level Output

16

25

ns

t PZl Output Enable
Time to Low
Level Output

26

40

ns

Min

.;.

t PHZ Output Disable
Time from High
Level Output

13

20

ns

tpLZ Output Disable
Time from Low
Level Output

24

36

ns

Nota 1: All typlcals are at Vee=5V, TA=25°e.
Note 2: Not more than one output should be shorted at a time.

6·384

c

:il:

Function Tables

CO

BCD 9'S OR BCD 10'S COMPLEMENT CONVERTER

BCD-TO-BINARY CONVERTER
BCD
WORDS

Inputs
(See Note A)

Outputs
(See Note B)
Y5 Y4 Y3 Y2 Yl

Outputs
(See Note D)

Inputs
(See Note C)

BCD
WORD

Et

D

C

B

A

G

YB

Y7

Y6

E

D

C

B

A

G

1
3
5
7
9

L
L
L
L
L

L
L
L
L
L

L
L
L
L
H

L
L
H
H
L

L
H
L
H
L

L
L
L
L
L

L
L
L
L
L

L
L
L
L
L

L
L
L
L
H

L
L
H
H
L

L
H
L
H
L

0
1
2
3
4

L
L
L
L
L

L
L
L
L
L

L
L
L
L
H

L
L
H
H
L

L
H
L
H
L

L
L
L
L
L

H
H
L
L
L

L
L
H
H
H

H
L
H
L
H

10
12
14
16
18

11
13
15
17
19'

L
L
L
L
L

H
H
H
H
H

L
L
L
L
H

L
L
H
H
L

L
H
L
H
L

L
L
L
L
L

L
L
L
L
L

L
L
L
H
H

H
H
H
L
L

L
H
H
L
L

H
L
H
L
H

5
6
7
8
9

L
L
L
L
L

L
L
L
H
H

H
H
H
L
L

_L
H
H
L
L

H
L
H
L
H

L
L
L
L
L

L
L
L
L
L

H
L
L
L
L

L
H
L
H
L

20
22
24
26
28

21
23'
25
27
29

H
H
H
H
H

L
L
L
L
L

L
L
L
L
H

L
L
H
H
L

L
H
L
H
L

L
L
L
L
L

L
L
L
L
L

H
H
H
H
H

L
L
H
H
H

,H L
H H
L L
L ,H
H L

0
1
2
3
4

H
H
H
H
H

L
L
L
L
L

L
.L
L
L
H

L
L
H
H
L

L
H
L
H
L

L
L
L
L
L

L
H
H
L
L

L
L
L
H
H

L
L
L
H
H

30
32
34
36
38

31
33
35
37
39

H
H
H
H
H

H
H
H
H
H

L
L
L
L
H

L
L
H
H
L

L
H
L
H
L

L
L
L
L
L

L
H
H
H
H

H
L
L
L
L

H
L
L
L
L

H
L
L
H
H

H
L
H
L
H

5
6
7
8
9

H
H
H
H
H

L
L
L
H
H

H
H
H
L
L

L
H
H
L
L

H
L
H
L
H

L
L
L
L
L

L
L
L
L
L

H
H
L
L
L

L
L
H
H
L

X

X

X

X

H

Z

Z

Z

Z

Z

ANY

X

'X

X

X

X

H

Z

Z

Z

0
2
4
6
8

ANY

X

H = High Level, L

= Low Level. X = Don't Care, Z = High Impedance

6-BIT Converter

MSD

H = High level, L

BCD 9's
Complement Converter

Low Level. X

=

Don't Care, Z

= High Impedance

BCD 10's
Complement Converter

LSD

~r,----~----~

BAD

=

C

B

BCD

o

25 24 23 22 21

BCD

A

C

B

A

5V

0

C

B

A

1
20,

6-BIT BINARY OUTPUT
TLlF16593·2

!'ID NC NB Nil
BCD 9's COMPLEMENT
TLIF16593·3

Not. A: Input conditions other than those shown produce highs at outputs Y 1
through Y5.
Note 8: Outputs Y6, Y7, and V8 are n01 used for BCD-Ie-binary conversion.
Note C: Input conditions other than those shown produce highs at outputs ye,
Y7, and ya.
Note 0: Outputs Yl through Y5 Bfe not used 'or BCD 9's or BCD 10's complement conversion.
tWhen these devices are used as complement converters. input E is used as a
mode control. With this input low, the BCD g's complement is generated: when
it is high, the BCD 10's complement is generated.

6-385

,TO TC TB TA,
BCD 10'. COMPLEMENT
TLIF16593·4

~

CO

c

:il:
CO

~

CC

0)
0)

~

Function Tables (Continued)

:::E

o

I

Inputs

Binary
Words

:::E
o

E

Binary Select
0
C
B

1
3
5
7

L
L
L
L

L
L
L
L

L
L
L
L

8
10
12
14

9
11
13
15

L
L
L
L

L
L
L
L

16
18
20
22

17
19
21
23

L
L
L
L

24
. 26
28
30

25
27
29
31

32
34
36
38

:

A

ya

Y7

Y6

Y5

Y4

Y3

Y2

Y1

L
L
·H
H

L
H
L
H

L
L
L
L

H
H
H
H

H
H
H
H

L
L
L
L

L
L
L
L

L
L
L
L

L
L
L
L

L
L
H
H

L
H
L
H

H
H
H
H

L
L
H
H

L
H
L
H

L
L
L
L

H
H
H
H

H
H
H
H

L
L
L
L

L
L
L
L

L
H
'H
H

H
L
L
L

L
L
L
H

L
L
H
L

H
H
H
H

L
L
L
L

L
L
H
H

L
H
L
H

L
L
L
L

H
H
H
H

H
H
H
H

L
L
L
L

L
L
H
H

H
H
L
L

L
H
L
L

H
L
L
L

H
L
L
H

L
L
L
L

H
H
H
H

H
H
H
H

L
L
H
H

L
H
L
H

L
L
L
L

H
H
H
H

H
H
H
H

L
L
L
L

H
H
H
H

L
L
L
H

L
L
H
L

H
H
L
L

L
H
L
L

33
35
37
39

H
H
H
H

L
L
L
L

L
L
L
L

L
L
H
H

L
H
L
H

L
L
L
L

H
H
H
H

H
H
H
H

L
L
L
L

H
H
H
H

H
H
H
H

L
L
L
H

L
H
H
L

H
L
H
L

40
42
44
46

41
43
45
47

H
H
H
H

L
L
L
L

H
H
H
H

L
L
H
H

L
H
L
H

'L
L
L
L

H
H
H
H

H
H
H
H

H
H
H
H

L
L
L
L

L
L
L
L

L
L
L
L

L
L
H
H

L
H'
L
H

48
50
52
54

49
51
53
55

H
H
H
H

H
H
H
H

L
L
L
L

L
L
H
H

L
H
L
H

L
L
L
L

H
H
H
H

H
H
H
H

H
H
H
H

L
L
L
L

L
H
H
H

H
L
L
L

L
L
L
H

L
L
H
L

56
58
60
62

57
59
61
63

H
H
H
H

H
H
H
H

H
H
H
H

L
L
H
H

L
H
L
H

L
L
L
L

H
H
H
H

H
H
H
H

H
H
H
H

L
L
H
H

H
H
L
L

L
H
L
L

H
L
L
L

H
L
L
H

X

X

X

X

X

Ii

z

z

z

z

z

z

z

.Z

0
2
4
6

ALL
H

Outputs
Enable
G

= High Level, L = Low Level, X = Don't Care, Z = High Impedance
6-Bit Converter
6-BIT
BINARY INPUT

--y.--

BAD
'-v--' ,-'

MSD

C

B

A

LSD

6-BIT BCD OUTPUT
TL/F/6593-5

6-386

c

s:

~National
'
~ Semiconductor

(0

o
oI\)
(")

DM9002C Quad 2·lnput NAN D Gates
General Description

For the new designs, the 54/74 families of TTL circuits offer the industry's broadest choice of high-performance
digital circuits. Series 54/74 pin·for·pin equivalent is
availab!e for the following SSI type:

The DM9002C device is designed to be used in existing
systems as replacements for Fairchild 9000·type circuits.
The DM9002C circuit offers several significant advantages over 9000 type circuits, some of which are:

DM9000C Series
DM9002C

Equivalent Series 74
DM7400

• Input clamp diodes
• Output short·circuit current specified to guarantee the
high-level impedance.
.

Absolute Maximum Ratings

• Power-dissipation of DM9002C Circuit is in most cases
lower than that for the equivalent 9002 type.

Supply Voltage

The DM9002C circuit is characterized for operation over
the industrial temperature range of O·C to 75·C.

Input Voltage
Storage Temperature Range

(Note 1)

7V
5.5V
- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagrams

Vee

84

Dual-In-Line Package
Y4
83

A4

A3

11

A1

81

Y1

A2

82

Y2
TLlF/6594·1

9002C (J,N)

9012C (J,N)

6-387

(J

8en
:E
Q

Recommended Operating Conditions
Symbol

DM9002C

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

Min

Nom

Max

4.75

5

5.25

O·C

1.9

25·C

1.8

75·C

1.6

Units
V
V

VIL

Low Level Input
Voltage

0.85

10H

High Level Output
Current

-1.2

mA

10L

Low Level Output
Current

50

mA

TA

Free Air Operating
Temperature

75

·C

0

V

,

Electrical Characteristics
Symbol

over recommended operating free air temperature (unless otherwise noted)

Parameter

Conditions

Min

Typ
(Note 1)

VI

Input Clamp Voltage

VOH

High Level Output
Voltage

Vcc= Min, 10H= Max
VIL = Max

VOL

Low Level Output
Voltage

Vee= Max, 10L= 16 mA
VIH=Min

0.45

IOL= 14.1 mA
Vee= Min

0.45

High Level Input
Current

Vec= Max, VI= 4.5V
Other Input at OV

IlL

Low Level Input
Current

VI = 4.5V

los

Short Circuit
Output Curr?nt

Vcc= Max (Note 2)

ICCH

Supply Current With
Outputs High

lecL

Supply Current With
Outputs Low

2.4

I Vec=5.25V
I Vec=4.75V

V
V

60

p.A

-1.6

mA

-1.41
-55

mA

Vce=5V

1.7

mA

Vcc=5V

6.1

mA

Swi,ching Characteristics
Parameter

V

-1.5

Vcc= Min, 11= -12 mA

IIH

Units

Max

-18

at Vcc = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
CL=15 pF
RL=4001l

Conditions
Min

Typ

Units
Max

tpLH Propagation Delay Time
Low to High Level Output

3

13

tpHL Propagation Delay Time
High to Low Level Output

3

15

Note 1: All typical. are at Vcc = 5V, TA = 25·C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

6·388

ns

-

ns

.---------------------------------------------------------------'0
s::
cc
~National

o
oCo)

~ Semiconductor

(')

DM900ac Triple a-Input NAN D Gates
General Description

For the new designs, the 54/74 families of TIL circuits offer the industry's broadest choice of high-performance
digital circuits. Series 54/74 pin-for-pin equivalent is
available for the following SSI type:

The DM9003C device is designed to be used in existing
systems as replacements for Fairchild 9000-type circuits.
The DM9003C circuit offers several significant advantages over 9003 type circuits, some of which are:

DM9000C Series
DM9003C

• Input clamp diodes
• Output short-circuit current specified to guarantee the
high-level impedance.
• Power-dissipation of DM9003C circuts is in most cases
lower than that for the equivalent 9003 type.

Equivalent Series 74
DM7410

Absolute Maximum Ratings
.supply Voltage
Input Voltage
Storage Temperature Range

The DM9003C circuit is characterized for operation over
the industrial temperature range of O·C to 75·C.

(Note 1)

7V
5.5V
- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagrams
Dual-In-Line Package
VCC

C1

Y1

C3

83

A3

11

2

A1

81

3
A2

4
82

9003C (J,N)

6-389

5
C2

Y2

GND
TLIF/659s..1

Recommended Operating Conditions
Symbol

DM9003C

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

Min

Nom

Max

4.75

5

5.25

O·C

1.9

25·C

1.8

75·C

1.6

Units
V
V

VIL

Low Level Input
Voltage

10H

High Level Output
Current

-1.2

mA

10L

Low Level Output
Current

50

mA

TA

Free Air Operating
Temperature

75

·C

0.85

0

V

Electrical Characteristics

over recommended operating free air temperature (unless otherwise noted)
Typ
(Note 1)

Symbol

Parameter

YI
VOH

Input Clamp Voltage

Vcc= Min, 11= -12 mA

High Level Output
Voltage

Vcc = Min, iOH = Max
VIL= Max

Low Level Output
Voltage

Vcc= Max, 10L= 16 mA
VIH = Min

0.45

10L= 14.1 mA
Vcc= Min

0.45

VOL

Conditions

IIH

High Level input
Current

Vcc=Max, VI =4.5V
Other Input at GND

IlL

Low Level Input
Current

VI = 4.5V
Other Inputs
at 5.25V

ios

Short Circuit
Output Current

Vcc = Max (Note 2)'

ICCH

Supply Current With
Outputs High

ICCL

Supply Current With
Outputs Low

Max
-1.5

2.4

Units
V
V
V

60

p.A

Vcc= Max

-1.6

mA

Vcc= Min

-1.41
-55

mA

Vcc=5V

1.7

mA

Vcc=5V

6.1

mA

Switching Characteristics
Parameter

Min

-18

at Vec= 5V and TA= 25·C (See Section 1 for Test Waveforms and Output Load)
CL= 15 pF
RL=4001l

Conditions
Min

Typ

Units
Max

tpLH' Propagation Delay Time
Low to High Level 9utput

3

13

ns

tpHL Propagation Delay Time
High to Low Level Output

3

15

ns

=

=

Note 1: All typical. are at vec SV, TA 2S"C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

6·390

.---------------------------------------------------------------'0

:s:
CO

~National

o

~ Semiconductor

~

(")

DM9004C Dual4-lnput NAND Gates
General Description

Absolute Maximum Ratings

The DM9004C device is designed to be used in existing
systems as replacements for Fairchild 9000-type circuits_
The DM9004C circuit offers several significant advantages over 9000 type circuits, some of which are:
• Input clamp diodes
• Output short-circuit current specified to guarantee the
high-level impedance.'
• Power-dissipation of DM9004C circuits is in most
cases lower than that for the equivalent 9004 type.

Supply Voltage
Input Voltage
Storage Temperature Range

For the new designs, the 54/74 families of TTL circuits offer the industry's broadest choice of high-performance
digital circuits. Series 54/74 pin-for-pin equivalent is
available for the following 551 type:
Equivalent Series 74

DM9004C

DM7420

Connection Diagram
Dual·ln·Line Package
VCC

C2

02
13

114

NC

12

B2

111

Al

2
Bl

A2

Y2
8

19

-

4

13
NC

10

~

.

1

7V
5.5V
-65·Ct0150·C

Nota 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

The DM9004C circuit is characterized for operation over
the industrial temperature range of O·C to 75·C.

DM9000C Series

(Note 1)

Cl

9004C (J,N)

6-391

5

01

~
16

Yl

17

GND
TlIF/6596·1

\

Recommended Operating Conditions
DM9004C·
Parameter

Symbol
Vcc

Supply Voltage

VIH

High level Input
Voltage

VIL

High level Output
Current

10L

low level Output
Current

TA

Free Air Operating
Temperature

Max

4.75

5

5.25

1.9

25 DC

1.8

75 DC

1.6

Units·
V
V

V

0.85
)

-1.2

mA

50

mA

75

DC

0

Electrical Characteristics
Symbol

Nom

ODC

low level Input
Voltage

10H

Min

over recommended operating.free air temperature (unless otherwise noted)

Parameter

Conditions

Min

Typ
(Note 1)

Max

VI

Input Clamp Voltage

Vcc=Min, 11= -12mA

VOH

High level Output
Voltage

Vcc = Min, 10H = Max
VIL = Max

VOL

low level Output
Voltage

Vcc= Max, 10L= 16 mA
VIH= Min

0.45

10L= 14.1 mA
Vcc=Min

0.45

IIH.

High level Input
Current

Vcc=Max, VI=4.5V
Other Inputs at GND

IlL

low level Input
Current

VI = 4.5V
Of her Inputs
at 5.25V

Units

-1.5

V

2.4

V
V

60

I,A

Vcc= Max

-1.6

mA

Vcc=Min

- 1.41

los

Short Circuit

Vcc = Max (Note 2)

-55

mA

ICCH

Supply Current With
Outputs High

Vcc=5V

1.7

mA

ICCL

Supply Current With
Outputs low

Vcc=5V

6.1

mA

Swit'ching Characteristics
Parameter

-18

at Vcc = 5V and TA = 25 DC (See Section 1 for Test Waveforms and Output load)
CL=15 pF
.RL=4001l

Conditions
Min

Units

Typ

Max

tpLH Propagation Delay Time
low to High Level Output

3

13

ns

tp~L Propagation Delay Time

3

15

ns

High to Low Level OutP!!t

,

Note 1: Alltyplcals are at VCC:5V, TA:25·C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

6·392

r----------------------------------------------------------,c

:s::

~National

~
....

~ Semiconductor

I\,)

o

DM9012C Quad 2-lnput NAND Gates with
Open Collector Outputs
General Description

Absolute Maximum Ratings

The DM9012C device is designed to be used in existing
systems as replacements for Fairchild 9000-type circuits.
The DM9012C circuit offers several signific~nt advantages over 9000 type circuits, some of which'are:

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

• Input clamp.diodes
• Output short-circuit current specl'fied to guarantee the
high-level impedance.
• Power-dissipation of DM9012C circuits is in most
cases lower than that for the equivalent 9012 type.

7V
5.5V
5.5V
- 65'C to 150'C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

The DM9012C circuit is characterized for operation over
the industrial temperature range. of O'C to 75'C.
For the new designs, the 54/74 families of TIL circuits offer the industry's broadest choice of high-performance
digital circuits. Series 54/74 pin-for-pin equivalent is
available for the following SSI type:

DM9000C Series
DM9012C

(Note 1)

Equivalent Series 74
DM7403

Connection Diagrams

Dual-In-Line Package
VCC

B4

A4

Y4

B3

A3

AI

Bl

Yl

A2

B2

Y2

Y3

TL/F/6597·1

9012C (.,J,N)

6-393

Recommended Operating Conditions
Symbol

DM9012C

Parameter

Min

Nom

Max

5

5.25

Vcc

Supply Voltage

4.75

VIH

High Level Input
Voltage

O°C

1.9

25°C

1.8

75°C

1.6

Vil

Low Level Input
Voltage

VOH

Units
V
V

0.85

V

High Level Output
Voltage

5.5

V

IOL

Low Level Output
Current

50

mA

TA

Free Air Operating
Temperature

75

°C

0

Electrical·Characteristics
Symbol
VI

over recommended operating free air temperature (unless otherwise noted)
Conditions

Parameter
Input Clamp Voltage

ICEX

High Level Output
. Current

VOL

Low Level Output
Voltage

Min

Typ
(Note 1)

Max

Units

-1.5

V

Vcc=Min, Vo=5.5V
VIL = Max

250

p.A

Vcc= Max, IOl= 16 mA
VIH=Min

0.45

V

.IOl= 14.1 mA'
Vcc=Min,

0.45

Vcc=Min, 11= -12mA

60

p.A

Vcc= Max

-1.6

mA

Vcc=Min

-1.41

IIH

High Level Input
Current

Vcc=Max, VI = 4.5V
Other Input at GND

IlL

Low Level Input
Current

VI =4.5V
Other Inputs
at 5.25V

ICCH

Supply Current With
Outputs High

vcc=fN

1.7

mA

ICCl

Supply Current With
Outputs Low

Vcc=5V

6.1

mA

Switching Characteristics
Parameter

at Vcc = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
CL= 15 pF
Rl=4000

Conditions
Min

Typ

Units
Max

tplH Propagation Delay Time
Low to High Level Output

3

45

ns

tpHL Propagation Delay Time
High to Low Level Output

3

15

ns

Note

1: Aillypicals are al VCC= SV. TA= 2S"C.

6·394

r-------------------------------------------------------------~---.c

3:
CD
o.....
en

~National

~ Semiconductor

o

DM9016C Hex Inverters
General Description

Absolute Maximum Ratings

The DM9016C device is designed to be used in existing
systems as replacements for Fairchild 9000-type circuits_
The DM9016C. circuit offers several significant advantages over 9000 type circuits, some of which are:

Supply Voltage
Input Voltage
Storage Temperature Range

not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

• Power-dissipation of DM9016C circuits is in most
cases lower than that for the equivalent 9016 type.
The DM9016C circuit is characterized for operation over
the industrial temperature range of O·C to 75·C.
For the new designs, the 54/74 families of TTL circuits offer the industry's broadest choice of high-performance
digital circuits. Series 54/74 pin-for-pin equivalent is
available for the following 551 type:
Equivalent Series 74
DM7404

Connection Diagram
Dual-In-Line Package

.

A6

V6

A5

V5

A4

V4

vr

14

13

11

12

4>0-

1
AI

2
VI

10

3
A2

8

9

4>0-

rt>o-

rf>o-

7V
5.5V
- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

• Input clamp diodes
• Output short-circuit current specified to guarantee the
high-level impedance.

DM9000C Series
DM9016C

(Note 1)

Lf>o-

r-t>o4

V2

5
A3

6
V3

17
GND
TL/F/6598·1

90l6C (J,N)

6-395

o

~
~
:::!!E

Q

Recommended Operating Conditions
DM9016C
Symbol

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

Min

Nom

Max

4.75

5

5.25

O°C

1.9

25°C

1.8

75°C

1.6

Units
V
V

Vil

Low Level Input
Voltage

0.85

10H

High Level Output
Current

-1.2

rnA

10l

Low Level Output
Current

50

rnA

TA

Free Air Operating
Temperature

75

°C

0

Electrical Characteristics

V

over recommended operating free air temperature (unless otherwise noted)

,

S ymbol

Parameter

Conditions

VI

Input Clamp Voltage

Vcc= Min, 11= -12 mA

VOH

High Level Output
Voltage

Vcc= Min, 10H= Max
Vll = Max

VOL

Low Level Output
Voltage

Vcc= Max, 10l= 16 mA
VIH=.Min

Typ
(Note 1)

Min

.

Max

Units

-1.5

V

2.4

V
0.45

V

0.45

10l= 14.1 mA
Vcc= Min
/

IIH

High Level Input
Current

Vcc = Max, VI = 4.5V
Other Inputs at OV

III

Low Level Input
Current

VI=4.5V
Other Inputs
at 5.25V

los

Short Circuit
Output Current

Vcc,:, Max (Note 2)

ICCH

Supply Current With
Outputs High

Vcc=5V

ICCl

Supply Current With
Outputs Low

Vcc=5V

Switching Characteristics
Parameter

60
Vcc= Max

-1.6

Vcc= Min

-1.41
-18

JiA
mA
-

-55

mA

1.7

mA

6.1

mA

I

at Vcc = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
CL=15 pF
RL=400{J

Conditions
Min

Typ

Units
Max

tplH Propagation Delay Time
Low to High Level Output

3

13

ns

tpHl Propagation Delay'Time
High to Low Level Output

3

15

ns

=

=

Nota 1: All typical. are at vcc 5V, TA 25·C.
Note 2: Not more than one outp'ut should be shorted at a \Ime, and the duration should not exceed one second.

6·396

c

s:
CO

~National

o

~ Semiconductor

N

~
C

s:

DM9024/DM8024 Dual J-K Flip-Flops with
Preset and Clear

CO

o

~

General Description
DM9000 Series
DM9024

The DM9024 series device is designed to be used in ex·
isting systems as replacements for Fairchild 9000·type
circuits. Thes DM9024 circuits offer several significant ad·
vantages over 9024 type circuits, some of which are:
• Input clamp diodes
• Output short·circuit current specified to guarantee the
high·level impedance.
• Power·dissipation of DM9024 circuits is in most cases
lower than that for the equivalent 9024 type.
The DM9024 circuit is characterized .tor operation over the
industrial temperature range of O·C to 75·C.
For the new designs, the 54/74 families of TTL circuits of·
fer the industry's broadest choice of high·p-erformance
digital circuits. Series 54/74 pin'for'pin equivalents are
available for the following SSltypes:

Equivalent Series 74
DM74109

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

Dual·ln·Line Package
Cll'l2

J2

K2

ClK2

PR2

·02

16

10

5

2

ClR 1

J1

K1

ClK 1

7V
5.5V
-65·CtoI50·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

VCC

(Note 1)

PR 1

6
01

7

Q1

9

8

GND
TLlF/6599·1

9024 (J)

8024 (N)

6·397

Recommended Operating Conditions
Symbol

DM9024

Parameter

Vee

Supply Voltage

V1H

High Level Input
Voltage

V1L

Low Level Input
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

!eLK

Clock Frequency

tw

Pulse Width

DM8024

Min

Nom

Max

Min

Nom

Max

4.5

5.0

5.5

4.75

5.0

0.25

TA= Min

2.0

1.9

TA =25'C

1.7

1.8

T A = Max

1.4

Units
V
V

1.6

0

40

0.9

0.85

-1.2

-1.2

mA

12.4

14.1

mA

30

MHz

30

0

Clock
High

20

20

Clock
Low

20

20

PR,CLR
Low

20

20

tsu

Setup Time (Note 1)

151

151

tH

Hold Time (Note 1)

101

101

TA

Free Air Operating
Temperature

-55

125

Note 1: The symbol (I) indicates rising edge of clock pulse is used for reference.

"

6·398

0

40

V

ns

ns
ns
70

'C

Electrical Characteristics
Symbol

Parameter

over recommended operating free air temperature (unless otherwise noted)
Conditions

Min

Typ
(Note 1)

Max

VI

Input Clamp Voltage

Vcc= Min, II = -12 mA

VOH

High Level Output
Voltage

Vcc = Min, 10H = Max
VIi.. = Max, VIH = Min

VOL

Low Level Output
Voltage

Vcc=Min
10L= Max
VIL= Max
VIH=Min

DM90

0.4

DMBO

0.45

10L= 16 mA
Vcc=Max

DM90

0.4

DMBO

0.45

Vce= Max
VI =4.5V
Other Inputs
at Ground

J, K

60

Clock

120

IIH

IlL

High Level Input
Current

Low Level Input
Current

Icc

Preset

120

Clear

240

J, K

-1.6

Clock

-3.2·

Preset

-3.2

Clear

-4.8

Vcc= Min
VI = 0.40V (DM90)
Other Inputs
at 4.5V

J, K

-1.24

Clock

- 2.48

Short Circuit
Output Current

Vcc= Max
(Note 2)

Supply Current

Vcc= Max (Note 3)

V
V

VGc= Max
VI = 0.40V (DM90)
VI = 0.45V (DMBO)
Other Inputs
at 4.5V

Vcc=Min
VI = 0.40V (DMBO)
Other Inputs
at 4.5V
105

-1.5
2.4

Units

Preset

-2.4B

Clear

-3.72

J, K

-1.41

Clock'

-2.B2

Preset

-2.B2

Clear

-4.23

DM90

-30

-85

DMBO

-30

-85
28

V

p.A

mA

mA

mA

Nolo': All typlcals are at vcc= SV, TA=2S'C.
NolO 2: Nol more Ihan one output should be shorled al a time, and the duration should not exceed one second.
Nolo 3: ICC Is measured with all oulputs open, first wllh PRESET al 4.5V and all other inputs grounded, then with CLEAR at 4.5V and all other inputs
grounded.

6-399

Switching Characteristics

at Vcc=5V and TA=25°C (See Section 1 for Test Waveforms and Output Load)
From
(Input)
To

Parameter

RL=40011
C L =15 pF

~Output)

fMAX Maximum Clock
Frequency

.Mln

Typ

30

40

Units
Max
Ml:lz

tpLH Propagation Delay
Time Low to High
Level Output

Preset
to

9

14

ns

tpHL Propagation Delay
Time High to Low
Level Output

Preset
to

18

29

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clear
to

9

14

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to

17

25

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to

12

18

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to

19

28

ns

a

a
a

a

a,a
a,a

Function Table '
24
Outputs

Inputs
Preset

Clear.

L

H

H

L

L
L

H
H
H
H
H

H
H
H
H
H

Clock

J

K

Q

X
X
X

X
X
X
L

X
X
X
L
L

H

L

L

H
H'
H

.t
t
t
t

L

H

L
H

H
H

X

X

H'

Q

L
TOGGLE

aD
H
aD

00
L

00

H = High Level (Steady State), L = Low Level (Steady State),
X = Don't Care
= Transition from low to high level
ao = The level of a before the indicated input conditions were established.
TOGGLE: Each output changes to the complement of its previous level on each
active transition of the clock.
"This configuration is nonstable. That is, it will not persist when preset and
clear inputs return to their inactive (high) level.

t

6·400

~-----------------------------------------------------------------'C

:5:

,
~ Semiconductor
~National

CD

~
o
c
:5:

CO

DM9300/DM8300 4-Bit Parallel·Access Shift Registers

w
o

o

General Description

Features

These 4-bit registers feature parallel inputs, parallel ,outputs, JK serial inputs, shift/load control input, and a direct
overriding clear. The registers have two modes of operation: parallel (broadside) load and shift (in direction QA
toward QD).
Parallel loading is accomplished by applying the four bits of
data and taking the shift/load control input low. The data is
loaded into the associated flip-flops, and appears at the
outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.
Shifting is accomplished synchronously when the
shiftlload control input is high. Serial data for this mode is
entered at the JK inputs. These inputs permit the first stage
to perform as a JK, 0 or T-type flip-flop as shown in the
function table.
These shift registers are fully compatible with most other
TIL and DTL families. All inputs, including the clock, are
buffered to lower the drive requirements to one normalized
Series 54174 load.

Connection Diagram

• Direct replacement for Fairchild 9300
•
•
•
•
•
•
•

Fully buffered inputs
Direct overriding clear
Synchronous parallel load
Parallel inputs and outputs from each flip-flop
Positive edge-triggered clocking
J and K inputs to first stage
Typical shift frequency-39 MHz

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

not be operated at these limits. The parametric yalues defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operatio,n.

I I II I I
II!' J!4 J J J

, I'
CLEAR

~

,PO

SERiAl INPUTS

I'
~1

I'

pl2

PARALLE1.INPUTS

9300 (J) 8300 (N)

Function Table

~
8

17
1
p~ G~D

TLlF/6600-1

Inputs
Clear
L
H
H
H
H
H
H

Shlft/
Load
X
L
H
H
H
H
H

7V

5.5V
-65'Cto150'C

Dual-In-,Line Package

~

Clock

Outputs

Serial

J

K

X

X

t

X

X
X
X
H
L
H
L

L

t
t
t
t

X
L
L
H
H

Parallel
PO P1 'P2 P3
X
a
X
X
X
X
X

X
b
X
X
X
X
X

(Note 1)

X
c
X
X
X
X
X

X
d
X
X
X
X
X

OA

OB

Oc

OD

L
a
QAO
QAO
L
H
aAn

L
b
QBO
QAO
QAn
QAn
QAn

L
c
QCO
QBn
QBn
QBn
QBn

L
d
QDO
QCn
QCn
QCn
QBn

= High Level (Steady State)
= Low Level (Steady State)
(
= Don't Care
t = Transition from low·to·high level

H
L
X

a, b, c. d = The level of steady state input at PO. Pl, P2, or P3, respectively.
QAO' OSO, Oeo. 000 = The level 01 0A. OS. Qe. or 00. respectively. before
the Indicated steady state input conditions were established.
OAn, OSn. 0en = The level 01 0A. aS or 0C, respectively. ~efore the most
recent tranSition of the clock.

t

6-401

aD
H

d
aDO
aCn
aCn
aCn
aCn

Recommended Operating Conditions
DM8300

DM9300
Symbol

Parameter

Vcc

Supply Voltage

V IH

High Level Input
Voltage

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V
V

2

2

Units

-,

VIL

Low Level Input
Voltage

10H

V

0.8

0.8

High Level Output
Current

-0.8

-0.8

mA

10L

Low Level Output
Current

16

16

mA

fCLK

Clock Frequency

30

MHz

tw

Pulse Width

tsu

Setup Time

a

a

30

Clock

16

11

16

11

Clear

30

15

30

15

SIL

30

13

30

13

Data

20

13

20

13

Clear

30

13

30

13

-11

tH

Data Hold Time

0

tREL

SIL Release Time

10

0

ns

ns

ns

- 11

10

ns

(Note 1)
TA

Free Air Operating
Temperature

-55

Electrical Characteristics
Symbol

125

0

70

'C

over recommended operating free air temperature (unless otherwise noted)

Parameter

Conditions

Min

VI

Input Clamp Voltage

Vcc=Min, 11= -12 mA

VOH

High Level Output
Voltage

Vcc=Min,loH=Max
VIL Max, VIH = Min

VOL

Low Level Output
Voltage

Vcc= Min, IOL= Max
VIH= Min, VIL= Max

II

Input Current@ Max
Input Voltage

IIH

Typ
(Note 2)

Max
-1.5

Units
V
V

2.4

=

0.4

V

Vcc=Max, VI = 5.5V -

1

mA

High Level Input
Current

Vcc=Max, VI=2.4V

40

/LA

IlL

Low Level Input
Current

Vcc=Max, VI=0.4V

-1.6

mA

los

Short Circuit
Output Current

Vcc= Max
(Note 3)

DM93

-18

-55

mA

DM83

-18

-55

Supply Current

Vcc= Max
(Note 4)

DM93

86

DM83

92

Icc

mA

Nolel: RELEASE-TIME: tRELEASE is defined as the maximum time allowed for the logic level_to be present at the logic Input prior to the clock transition
from low to high In order for the fllp·flop(s) not to respond.
Nole 2: All typlcals are at VCC =5V, TA =25·C.
Nole 3: Not more than one output should be shorted at a time.
Nole 4: With all outputs open, SHIFT/LOAD grounded, and 4.5V applied to J, K, and data Inputs, ICC is measured by applying momentary ground, then 4.5V
to CLEAR, and then to CLOCK.

6-402

c

Switching Characteristics

Parameter

at Vee = 5V and

TA = 25°C

From
(Input)
To
(Output)

(See Section 1 for Test Waveforms and Output Load)
RL

=40011

f MAX Maximum Clock
Frequency

Typ

30

39

-s:
CO

Max

MHz

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
Output

14

22

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
Output

17

26

, ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
Output

19

30

ns

,

6·403

~
o
C

Units

CL=15pF
Min

s:

CD

~
o

DM93001 DM8300
U)

n

::T

CI)

3

ac;'
c

DM9318300

S'

Vee (16),

,

,
R1
4k

~R2

<'1.5k

R4
2>

R'3
1.Sk

R'5

4>

'R I pal,

,
R2B
1.Sk

R'6

4>

R30
4k

'a 1('4,

R31
4k

, ,P:JI

,R42

R44

'.5k

4>

,1 'D ,

11 1

ec
...

CD
(121

R45

4>

CLEAR (1)

(B)

GND*

....
'"
o
~

R70

4k

1J3)
K

(5)

p,

(6)

P2

(7)

.3

TL/F/6600-2

II)

3

,-------------------------------------------------------------,0
s:
CO
~National

Co)

o.....

~ Semiconductor

-s:o

DM9301/DM8301 1 of 10 Decoders

o.....

00

Co)

General Description
These BCD-to-decimal decoders consist of eight inverters
and ten 4-input NAND gates_ The inverters are connected in
pairs to make BCD input data available for decoding by the
NAND gates. Full decoding of valid input logic ensures that
all outputs remain "OFF" for all invalid input conditions.

• All outputs are high for invalid BCD input conditions

These circuits provide familiar TTL inputs and outputs
which are comp~tible for use with other TTL and DTL circuits. DC noise margins are typicaliy 1 V and power dissipation is typically 125 mW. The diode-clamped, buffered
inputs represent only one normalized Series 54/74 load.

Absolute Maximum Ratings

• Typical power dissipation 125 mW
• Typical propagation delay 20 ns

7V

Supply Voltage

5.5V

Input Voltage
Storage Temperature Range

Features
• Direct replacement for Fairchild 9301 and Signetics
8252
• Diode-clamped inputs

Dual-In-Line Package
INPUTS

15

OII1;PUTS

'0

o

INPUTS

,5

12

11

4

3

c

3

2
13

14

- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table afB not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

A
B
-----------

(Note 1)

6
8

6

10

7

18

9,

GND

OUTPUTS

TLlF/660H

9301 (J) 8301 (N)

6-405

Recommended Operating Conditions
Symbol

. DM8301

DM9301

Parameter
Min

Nom

Max

Min

Nom

Max

5

5.5

4.75

5

5.25

Vee

Supply Voltage

4.5

viti

High Level Input
Voltage

·2

VIL

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

2

-55

Units
V
V

0.8

0.8

-0.8

.-0.8

mA

16

16

mA

70

'C

125

0

V

'-.

Electrical Characteristics
Symbol

Parameter

over recommended operating free air temperature (unless otherwise noted)
Conditions

Typ
(Note 1)

Min

Max

Units

VI

input Clamp Voltage

Vee = Min, Ii= -12 mA

VOH

High.LevelOutput
Voltage

Vee = Min, 10H = Ml!x
VIL = Max, VIH= Min

VOL

Low Level Output
Voltage

Vee = Min, 10L= Max
VIH = Min, VIL = Max

0.4

V

II

Input Current@ Max
Input Voltage

Vee = Max, VI = 5.5V

1

mA

IIH

High Level Input
Current

Vee = Max, VI = 2.4V

40

p.A

IlL

Low Level Input
Current

Vee = Max, VI = 0.4V

-1.6

mA

los

Short Circuit
Output Current

Vee = Max
(Note 2)

mA

Supply Current

Vee = Max (Note 3)

Icc

Switching Characteristics
Parameter

-1.5
2.4

V
V

DM93

-20

-55

DM83

-20

-55
25

41

mA

at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
CL=15 pF
RL=400{)

Conditions
Min

Units

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

20

30

ns

tpHL Propagation Delay Time
High to Low Level Output

19

30

ns

Nola I: Ali typicals are at Vee=5V. TA=25'e.
Nole 2: Not more than one output should be shorted at a time.
Nole 3: ICC is measured with the outputs open and ali inputs grounded.

6·406

.--------------------------------------------------------------------,0

s:
CO

Function Table
No.

~
......

Decimal Output

D

e

B A 0

1

2

4

5

6

7

8

9

2
3
4

L
L
L
L
L

L L L L
L L H H
L H L H
L H H H
H L L H

H
L
H
H
H

H H H
H H H
L H H
H L H
H H L

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

5
6
7
8
9

L
L
]..
H
H

H
H
H
L
L

L
H
H
L
L

H
L
H
L
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

L
H
H
H
H

H
L
H
H
H

H
H
L
H
H

H
H
H
L
H

H
H
H
H
L

H
H
H
H
H
H

L
L
H
H
H
H

H
H
L
L
H
H

L
H
L
H
L
H

H
H
H
H
H
H

H
H
H
H
H
H

H H
H H
H H
H H
H H
H H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

0
1

c

::::;

~

~

Logic Diagram

BCD Input

3

DM9318301

Tl./F/6601·2

6·407

-s:
o

co
Co)
o......

~National

~ Semiconductor
DM9309/DM8309 Dual4·Bit Data Selectors/Multiple~ers
General Description

Absolute Maximum Ratings

These data selectors I multiplexers contain inverter I drivers
to supply lull cc;>mplementary, on-chip, binary decoded data
selection.

Supply Voltage·
Input Voltage
Storage Temperature Range

The DM93o.9/83o.9 contains two separate 4-bit multiplexers with complementary Y and Y outputs; however, the
~wo sections have common address select inputs.

(Note 1)

7V
S.SV
- 6S'C to 1So.'C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be ",uaranteed. The device should
not be operated at these limits. The parametric values defined in the

Features

"Electrical Characteristics" table are' not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

DM93o.9/83D9
• Direct replacement lor Fairchild 930.9
• Complementary outputs
• Dual one-ol-Iour data selectors

Connection Diagram

Function Table

Dual-In-Line Pl\ckage
SELECT
INPUT
A

QUl"!'UTS

Vee

Y2

Y2

15

116

14'

13

-

DATA INPUTS

,
2CO

2C1

11 .

12

2C:!

.

Select

9

B

A

CD

C1

C2

C3

L
L
L
L
H
H
H
H

l:.
L
H
H
L
L
H
H

L
H
X
X
X
X
X
X

.X
X
L
H
X
X
X
X

X
X
X
X
L
H
X
X

X
X
X
X
X
X
L
H

2C3

10

t-

r-

=

2

.

Y1

OUTPUTS

Data

y

y

L
H
L
H

H
L
H
L
H
L
H
L

l!.
H
L
H

Select inputs A and B are common to both sections.
H = High Level, L Low Level, X Don't Care.

(

Y1

Outputs

Inputs

3
SELECT
INPUT

B

4

5

,1CO

1C1

.

6

7

IB

1C2

1C3

GND

,

DATA INPUTS
TLlF/6602·,

930.9 (J) 830.9 (N)

6-408

=

c

s:

Recommended Operating Conditions

CD

Co)

Symbol

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

Min

Nom

Max

Min

Nom

Max

4.4

5

5.5

4.75

5

5.25

2

2

V

-s:

V

o

Units

-55

C

O.B

O.B

-O.B

-O.B

mA

16

16

mA

70

·C

125

0

V

over recommended operating free air temperature (unless otherwise noted)

Parameter

Conditions

VI

Input Clamp Voltage

Vcc= Min, 11= -12 mA

VOH

High Level Output
Voltage

Vee= Min, IOH= Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee = Min, IOL= Max
VIH = Min, VIL = Max

II

Input Current@ Max
Input Voltage

IIH

Min

Typ
(Note 1)

2.4

3.4

Max
-1.5

V
V
V

Vee = Max, VI = 5.5V

1

mA

High Level Input
Current

Vee = Max, VI=2.4V

40

p.A

IlL

Low Level Input
Current

Vee = Max, VI = 0.4V

- 1.6

mA

105

Short Circuit
Output Current

Vee Max
(Note 2)

mA

Supply Current

Vee= Max (Note 3)

=

I
I

0.2

Units

0.4

lee

CD

Q)
Co)

CD

Electrical Characteristics
Symbol

o

DM8309

DM9309

DM93

-30

-85

DM83

-30

-85
27

Note 1: Aillypicals are al VCC =5V, TA =25"C.
Note 2: Not more than one output should be shorted at a time.

Nota 3: ICC is measured with Ihe oulpuls open and all in puis al 4.5V.

I

6-409

44

mA

Switchin9 Characteristics

at Vcc

=SV arid TA =2SoC

From
(Input)
To
(Output)

Parameter

(See Section 1 for Test Waveforms and Output Load)
RL=4001l
CL=15 pF

Min

Units

Typ

Max

27

40

ns

23

36

ns

17

24

ns

20

29

ns

18

27

ns

tPLH Propagation Delay
Time Low to High
Level Output

Select
to

tpHL Propagation Delay
Time High to Lo"Y
Level Output

Select
to

tpLH Propagation Delay
Time Low to High
Level Output

Select
to

tpHL Propagation Delay
Time High to Low
Level Output

Select
to

tpLH Propagation Delay
Time Low to High
Level Output

Data
to

tpHL Propagation 'Delay
Time High to Low
Level Output

Data
to
.y

23

34

ns

tpLH Propagation Delay
Time Low to High
Level Output

Data
to

14

21

ns

tpHL Propagation Delay
Time High to Low
Level Output

Data
to

9

13

ns

Y

Y

Y
Y
Y

Y
Y

Logic Diagram
DM93J8309

lC3
lC2

-

~

(7)

(6)

1

(2)"1 }
(1)
OUTPUTS
Yl

1

(14) _
Y2 }
(15)
OUTPUTS
Y2

lCl (5)

lCO
DATA
INPUTS

(4)

---.
2C3

1-1

(9)

2C2(10)

...........
2Cl

(11)

-

2CO (12)
SELECT(13)
INPUT A
SELECT (3)
INPUT a

t>- t>-

,

,
TLlF/6602·2

6·410

~-----------------------------------------------------------------'C

~NaHonal

•

~ Semiconductor
DM9310/DM8310 Synchronous 4·Bit Counters

:s:
co
CIJ

.....

-:s:c
o

CO
CIJ

.....

o

General Description
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The DM9310IDM8310 are decade counters.
The carry output is decoded by means of a NOR gate, thus
preventing spikes during the normal counting mode of
operation. Synchronous operation is provided by having
all flip-flops clocked simultaneously so that the outputs
change coincident with each other when so instructed by
the count-enable inputs and internal gating. This mode of
operating eliminates the output counting spikes which are
normally associated with asynchronous (ripple clock)
counters. A buffered clock input triggers the four flip-flops
on the rising (positive-going) edge of the clock input
waveform.
These counters are fully programmable; that is, the outputs
may blrpreset to either level. As presetting is synchronous,
setting up a low level at the load input disables the counter
and causes the outputs to agree with the setup data after
the next clock pulse regardless of the levels of the enable
input. Low-to-high transitions at the load input are perfectly
acceptable regardless of the logic levels on the clock or
enable inputs. The clear function is asynchronous and a low
level at the clear input sets of the flip-flop outputs low regardless of the levels of clock, load, or enable input!!.
The carry look-ahead circuitry provides for cascading
counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function
are two count-enable inputs and a ripple carry output. Both
count-enable inputs (P and T) must be high to count, and
input T is fed-foward to enable the ripple carry output. The
ripple carry output thus enabled will produce a high-level
output pulse with a duration approximately equal to the

Connection Diagram

high-level portion of the QA output. This high-level overflow
ripple carry pulse can be used to enable successive cascaded stages. High-to-Iow level transitions at the enable P
or T inputs may occur regardless of the logic level in the
clock.

Features
•
•
•
•
•
•
•
•

Direct replacement for Fairchild 9310
Internal look-ahead for fast counting
Carry output for n-bit cascading
Synchronous counting
Load control line
Diode-clamped inputs
Typical clock frequency 35 MHz
Pin-for-pin replacements popular 54/74 counters
9310 - 54160A/74160A (decade)

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

VCC

define the conditions for actual device operation.

116

OUTPUTS

QB

15

14

Qc

13

12

Q~

ENABLE
T

11

I

LOAD

10

9

p-

rC

2

CLEAR CLOCK

3
~

5

4

A ____B

~

7V
5.5V
- 65'C to 150'C

Not. 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"'Electrical Characteristics"' table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will

Dual-In-Line Package
RtPPLE
CARRY
OUTPUT

(Note 1)

7

6

C
______
-D
J

18

ENABLE
P

GND

DATA INPUTS
TL/F/6603-1

8310 (N)

9310 (J)
6·411

o
,..
('I)

CO

::i!:

c

oT""

Recommended Operating Conditions
DM9310
Symbol
Vcc

Supply Voltage

::i!:

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

fCLK

Clock Frequency

tiN

Pulse Width

tsu

DM8310

Parameter

('I)
0)

c

\

~

Setup Time

tH

Any Hold Time
(Note 1)

TA

Free Air Operating
Temperature

Min

Nom

Max

Min

Nom

Max

4.4

5

5.5

4.75

5

5.25

2'

2

Units
V
V

0.8

0.8

-0,8

-0.8

mA

16

16

mA

25

MHz

0

25

0

Clock

25

25

Clear

20

20

Data

20

20

Enable P

20

20

Load

25

25

Clear

20

20

0

0

-55

125

V

ns

,/

ns

ns

0

70

·C

Nole I: The minimum HOLD lime is as specified or as long as Ihe CLOCK Input takes to rise from C.SV to 2V. whichever is longer.

Electrical Characteristics
Symbol

Parameter

over recommended operating free air temperature (unless otherwise noted)
Conditions

Min

Typ
(Note 1)

2.4

3.4

Max

VI

Input Clamp Voltage

Vcc= Min, Ij= -12 mA

VOH

High Level Output
Voltage

VCC = Min, 10H = Max
VIL = Max, V IH = Min

VOL

Low Level Output
Voltage

Vcc= Min, 10L= Max
VIH = Min, VIL= Max

II

Input Current@Max .
Input Voltage

Vcc=Max, VI=5.5V

IIH

High Level Input
Currert

Vcc= Max
VI=2.4V

Low Level Input
Current

Vcc= Max
VI=O.4V

CLK, EN T

-3.2

Other

-1.6

Short Circuit
Output Current

Vcc= Max
(Note 2)

DM93

-20

-57

DM83

-18

-57

Supply Current With
Outputs High

Vcc= Max
(Note 3)

DM93

59

85

DM83

59

94

Supply Current With
Outputs Low

Vcc= Max
(Note 4)

DM93

63

91

DM83

63

101

IlL

los

ICCH

ICCL

Nolel:
Nole 2:
Nole 3:
Nole 4:

-1.5

0.2

Units
V
V

0.4

V

1

mA

CLK, ENT

80

p.A

Other

40

,

All typlcals are at VCC=5V. TA=25'C.
Not more than one output should be shorted at a time.
ICCH is measured with the LOAD Input high. then again with the LOAD Input low, with all other inputs high and all outputs open.
ICCL is measured with the CLOCK input high, then again with the CLOCK Input low, with all other Inputs low ~nd all outputs open.
6·412

p.A

mA

mA

mA

c.

Switching Characteristics

at Vee= 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)

:s:
CD

....o
Co)

From
(Input)
To
(Output)

Parameter

RL=40011
Units

CL=15 pF
Min

Typ

25

35

Max

-:s:
c

00

Co)

fMAX Maximum Clock
Frequency

MHz

Clock
to
Ripple Carry

18

27

ns

Clock
to
Ripple Carry

16

24

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock·
to

14

20

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to

16

23

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to

14

21

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to

18

25

ns

tpLH Propagation Delay
Time Low to High
Level Output

Enable T
to
Ripple Carry

10

15

ns

tpHL Propagation Delay
Time High to Low
Level Output

EnableT
to
Ripple Carry

12

16

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to

24

36

ns

tpLH Propagation Delay
Time Low to High
Level Output
tpHL Propagation Delay
Time High to Low
Level Output

..

a
,

a

a
a

a

6·413

......

o

o

~

Logic ' Diagram

::'E

DM9318310

-,...
c
o

CO)
(J)

::'E
c

(2)
CLOCK

~

~I

"-J'

-

(3)

DATA A

"'----t K O~OA
(14)
...,"'~------------------i-t1-f:::::::::::=ilr1rCLOCK

•

J

~

(1)
CLEAR

1

'"1

~IK

~

'(4'~)---------------1~---t~t4::lJ
DATA B ~
(9)

'1

"

_'

kCLOCK

J CLEAR oj--,

1" J

T

LOAD

ENABLE P :::)

0 ........

):>----Hrttb~:t*==L-

h""'---F>--""'I

~.~

>-<

~. l
~

M'"

KCLOCK

O":"'~

Oc

_ °h
J CLEAR

Y

?

DATA D

(~6~)-------------H-ttHitt::I-l

J

JK

IV

(11)

O~'OD

~~CLOCK

1

J CLEAR 01--.

.=:f

l~ti~~~~~§§§g~~~~~':"'_--'-(1~5)
~

-

CARRY
RIPPLE
OUTPUT

TLIF16603,2

6·414

r-----------------------------------------------------------------.c
s:
Timing Diagram
CD
Co)

9310/8310 Synchronous Decade Counters
Typical Clear, Preset, Count and Inhibit Sequences

A

.::;:

.....

Co)

_____________ _

:

.-----+---,-------------,- -- :::
__-+-_..L

CLOCK

Sequence:
(1) Clear outputs to zero

ENABLE P _ _ _+_~
ENABLET

(2) Preset to BCD seven

(3) Count to eight, nme, zero, one, two. and three

---f--+'

(4) Inhibit

OA _ _

==

OB-OUTPUTS

.

\

OC _ _

OD

C

o

LOAD

\

-s:
CO

CLEAR ~r:(~AS::Y::-N::C::HR::ON=O:::U:::S):---------------

,

.....

o

==

-1-_-+--1

RIPPLE~~~~ ----+--+:-r.a:--!.g

"'0--:1---::"2--:3+---------

- - - C O U N T - - - - ----INHIBlT---CLEAR PRESET
TLlFJ6603·3

6·415

.,..

or-----------------------------------------------------------------------------~

~

Parameter Measurement Information

:i5
C

-.,..

Switching Time Waveforms

o

('I)
0)

,:i5
c

CLOCK
INPUT
OV
IpLH
(MEASURE AT IN+1)
• VOH ---+-t-I-----t-_
OUTPUT
QA

VOL---I-.1

OUTPUT
Qs

VOH--~---------~~
VOL----+------------~---~--~~--~.1

IPHL
(MEASURE AT IN+S)
OUTPUT

VOH---~------------~~

Qc
VOL----~-----------+---'~~~--~~

VOH---~------~~

OUTPUT
QD

VOL---~------------t_---~--~~-------'

RIPPLE VOH -----1~
CARRY
OUTPUT VOL _____

1'----------TLIF16603,4

Note A: The input pulses are supplied by a generator having the following characteristics: PRR !':: 1 MHz, duty cycle ~ 50%, ZOUT ~ 50 O. Ir::;; 1Pns, If .:5 10 ns.
.
Vary PRR to messure 'MAX'
Note B: Outputs QO Sfld carry are tesled at tn+ 10 for 931018310. where In is the bit time when all outputs are low.
Not. C: VREF = 1,5 V,

6-416

r----------------------------------------------------------------------.c
s:
Parameter Measurement Information (Continued)
<0

....

Co)

-s:

Switching Time Waveforms

o

C

3.0V

CO

....
o

CLOCK INPUT

Co)

OV

3.0V
CLEAR
INPUT
OV

3.0V
LOAD
INPUT
OV

3.0V
DATA INPUTS
A,B,C,ANDD
OV
VOH
QA AND QD OUTPUTS

9310

VOL
VOH

QB AND QC OUTPUTS

9310
VOL

3.0V
ENABLEPOR
ENABLE T
OV
VOt!
CARRY
VOL
TLlF16603-5

Note A: The input pulses are supplied by generators having the following characteristics: PRR .:5 1 MHz, duty cycle
Note B: Enable P and enable T setup times are measured at I n+10 for 8310/9310.

Note C: VREF = 1.5 V.

6·417

~

50%, ZOUT

~

500, tr .:5 10 Rs"f

::s

10 ns.

~ .---------------------------------------------------------------~-------------------,
~

~ ~National

~ ~ Semiconductor
~
~

C')

~
c

DM9311/DM8311 4·Line to 16·Line Decoders/Demultiplexers
General Description
Each of these 4-line-to-16-line decoders utilizes TTL circuitry to decode four binary-coded inputs into one of sixteen mutually exclusive outputs when both the strobe
inputs, Gland G2, are low. The demultiplexing function is
performed by using the 4 input lines to address the output
line, passing data from one of the strobe inputs with the
other strobe input low. When either strobe input is high, all
outputs are high. These demultiplexers are ideally suited
for implementing high-performance memory decoders. All
inputs are buffered and input clamping diodes are provided
to minimize transmission-line effects and thereby simplify
system design.

• Performs the demultiplexing function by distributing data
from one input line to anyone of 16 outputs
• Input clamping diodes simplify system design
• High fan-out, low-impedance, totem-pole outputs
• Typical propagation delay 19"ns
• Typical power dissipation 170 mW

Absolute Maximum Ratings

7V

Supply Voltage
Input Voltage
Storage Temperature Range

Features

(Note 1)

5.5V
-'65'Cto150'C

Note 1: The "Absolute Maximum Ratings" are those values beyond

• Direct replacement for Fairchild 9311
• Pin for pin with popular 54154/74154
• Decodes 4 binary-coded inputs into one of 16 mutually
exclusive outputs

which the safety of the device can not be guaranteed. The device should

not be operated at these limits. The parametric values defined in the

"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram
,Oual-In-Line Package

INPUTS
Vec
124

' ABC
23

22

OUTPUTS

D
21

G2
20

Gl' , 15

19

18

14

17

13
18

12
15

,0

13

p-

-
(1)

DO

D

1 (2)

~

(3)

H-

(4)

~

D2

03

)-

DATA

'---

INPUTS
D4

(5)

D5

D7

C(

"

./

~
(14)

; } OUTPUTS

.... ~:f-)-

(7)

)-H

(9)

(~A
SELECT { : (
INPUTS

~

- ;:}ft

(6)

D6

)-

12) ....

.;>

13)....

.;>

L.....f

~

B
B

C
C

TLfF/6605·2

6-425

,...

~r------------------------------------------------------------------------'

II?JI National
~
Semiconductor

~
,...

~

('I)

en

a

DM9316/DM8316 ~ynchronous 4·Bit Counters

~ General Description

input T is fed-foward to enable the ripple carry output. The
ripple carry output thus enabled will produce a high-level
output 'pulse with a duration approximately equal to the
high-level portion of the QA output. This high-level overflow
, ripple carry pulse can be used to enable successive cascaded stages. High-to-Iow level transitions at the enable P
or T inputs may occur regardless of the logic level in the
clock.

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The DM9316/DM8316 is a4-bit binary counter.
The carry output is decoded by means of a NOR gate, thus
preventing spikes during the normal counting mode of operation. Synchronous operation is provided by having all
flip-flops clocked simultaneously so that the outputs
change coincident with each other when so instructed by
the count-enables inputs and internal gating. This mode of
operating eliminates the output counting spikes which are
normally associated with asynchronous (ripple clock)
counters. A buffered clock Input triggers the four flip-flops
on the rising (positive-going) edge of the clock input
waveform.

Features
•
•
•
•
•
•
•
•

These counters are fully programmable; that is, the outputs
may be preset to either level. As presetting is synchronous,
setting up a low level at the load input disables the counter
and causes the outputs to agree with the setup data after
the next clock pulse regardless oi the levels of the enable
input. Low-to-high transitions at the load input are perfectly
acceptable regardless of the logic levels on the clock or
enable inputs. The 'clear function is asynchronous and a low
level at the clear input sets of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs.

Direct replacement for Fairchild 9316
Internal look-ahead for fast counting
Carry output for n-bit cascading
Synchronous counting
Load control line
Diode-clamped inputs
Typical clock frequency 35 MHz
Pin-for-pin replacements popular 54/74 counters
9316 - 54161A/74161A (binary)

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature

The carry look-ahead circuitry provides for cascading
counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function
are two count-enable inputs and a ripple carry output. Both
count-enable inputs (P and T) must be high to count, and

7V
5.5V
R~nge

which the safety'of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual-In-Line Package

116

OUTPUTS
OA

OB

Oc

OD

ENABLE
T
LOAD

15

14

13

12

11

10

2

3

4

5

6

7

CLEAR CLOCK

A

- 65·C to 150·C

Nota 1: The "Absolute Maximum Ratings" are those values beyond

Connection Diagram
RIPPLE
CARRY
VCC OUTPUT

(Note 1)

B

C

D

ENABLE

9

18

GND

P

DATA INPUTS

TLlF/6606-1

8316 (N)

9316 (J)

6-426

Recommended Operating Conditions
DM8316

DM9316
Parameter

Symbol
Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

ICLK

Clock Frequency

tw

Pulse Width

tsu

Setup Time

tH

Any Hold Time
(Note 1)

TA

Free Air Operating
Temperature

Nom

Max

Min

Nom

Max

4.4

5.0

5.5

4.75

5.0

5.25

-0.8

-0.8

mA

16

16

mil,

25

MHz

0

25

25

Clear

20

20

Data

20 .

20

.Enable P

20

20

Load

.25
20

Parameter

I1'S

ns

25

,

20

0

ns

0

-55

125

0

70

Conditions

Min

Typ
(Note 2)

2.4

3.4

Max

VI

Input Clamp Voltage
High Level Output
Voltage

VOL

Low Level Output
Voltage

Vcc= Min, 10L= Max
VIH = Min, VIL = Max

II

Input Current@Max
Input Voltage

Vce=Max, VI =5.5V

IIH

High Level Input
Current

Vec= Max
VI= 2.4V

Low Level Input
.Current

Vcc= Max
VI = O.4V

Short Circuit
Output Current

Vec= Max
(Note 3)

DM93

-20

-57

DM83

-18

-57

Supply Current With
Outputs High

Vee = Max
(Note 4)

DM93

59

85

DM84

59

94

Supply Current With
Outputs Low

Vee= Max
(Note 5)

-1.5

Vec= Min, 11= -12 mA
Vec= Min, 10H= Mal(
",\VIL = Max, VIH = Min

0.2

lecH

ICCL
NOlel:
Nole2:
Nole3:
Nole4:
NoleS:

Units
V
V

0.4

V

1

mA

Clock

80

p.A

Enable T

80

Other

40

Clock

-3.2

Enable T

-3.2

Other
los

DC

over recommended operating Iree air temperature (unless otherwise noted)

VOH

IlL

V

0.8

Clock

Clear

V

0.8

25

0

Units

V

2

2

Electrical Characteristics
Symbol

Min

-1.6

DM93

63

91

DM83

63,

101

The minimum HOLD time Is as specified or as long as the CLOCK input takes to rise from O.SV to 2V, whichever is longer.

Aillypicals are al VCC=SV, TA=2S"C.
Nol more than one output should be shorted at a time.
ICCH is measured with the lOAD 1nput high. then again with the LOAD Input low, with all other inputs high and all outputs open.
ICCl Is measured wllh the CLOCK Input high, then again with the CLOCK input low. with all other inputs low and all outputs open.
6·427

p.A

mA

mA

mA

CD
.....
C')
CO

Switching Characteristics

:::E

c
CD
.....
C')

From
(Input)
To
(Output)

Parameter

0')

:::E
c

'MAX Maximum Clock
Frequency

at Vee = 5V and TA= 25°C (See Section 1 for Test Waveforms and Output Load)

.

RL=400{l
C L =15 pF
Min

Typ

25

35

Units
Max
MHz

Clock
to
RC

18

27

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock·
to
RC

16

24

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to

14

20

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to

16

23

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to

14

21

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to

18

25

ns

tpLH Propagation Delay
Time I,.ow to High
Level Output

ENT
to
RC

10

15

ns

tpHL Propagation Delay
Time High to Low
Level Output

ENT
to
RC

12

16

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to

24

36

ns

tpLH Propagation Delay
Time Low to High
Level Output

Q

Q

Q

Q

Q

6-428

r---------------------------------------------------------------------~c

:s:
co

Logic Diagram

w
.....

Q)

c

:s:

DM9318316

~

(2)
CLOCK

(3)
DATA A

I

~

(1)

(4)
DATAB

~

(9)

ENABLE P

Q)

K

~

~

(10)
ENABLE T

(5)

~

DATAC

~

(6)
DATAD

-L

--;.

(14)
Q--- I - -

ppi

CLEAR

LOAD

co
w
.....

CLOCK

OfJCLEAR

'I'
K

(13)
Q-I--

~ I> CLOCK

1

0

-

J CLEAR

I
K

(12)
Q - I - - QC

~ I> CLOCK

1

0

-

J CLEAR

'I'
K

(11)
Q r I - - QD

-< I>

1

CLOCK
or
J CLEAR

I

r
L---j..

"

./

(15) RIPPLE
CARRY
OUTPUT
TLfF/6606-2

6·429

~r-------------~--------------------------------------------------------------,
T""

~

" Timing Diagram

:E

c

~

T""
C')
0)

:E

9316/8316 Synchronous Binary Counters
Typical Clear, Preset, Count and Inhibit Sequences

c

CLEAR
LOAD

r--------------

DAUTTAS
INP

~~~~~~:~~~~:r= =============

lc:o .----+----r- - - - - - - - - - - - - L ______________ _

r----t..,...---,--------------CLOCK
ENABLE P

---t--+'

l ==

ENABLE T

---+--1-'

QA-QB--

OUTPUTS

.

-+-+--1--1

Qc _ _

Qo--

RIPPLEO~~:~; ----+--+.,.12""""l-:l"'3,....,1"4~15

0

---COUNT-"- - - - - - - I N H I B I T - - - CLEAR PRESET
TlIF/,6606-3

Sequence:
(1) Clear outputs to zero
(2) Preset to binary twelve
(3) Count to thirteen. fourteen. fifteen. zero, one, and two
(4) Inhibit

6-430

r-----------------~--------------------------------------------------_.c

:s:
CD

Parameter Measurement Information

Co)

-"

~

c

:s:
CD

Switching Time Waveforms

Co)

-"

0)

CLOCK
INPUT
OV
IpLH
(MEASURE AT IN+l)
VOH
OUTPUT
OA

--+-·hI-----+-_

VOL--+.1

VOH----+------~~

OUTPUT

OB

vOL--+----~-+--'--I~--~-'
IpHL
(MEASURE AT IN+S)
VOH----+------~~

OUTPUT

Oc

VOL---~------------~---~-~~-~~.1

IpLH
(MEASURE AT IN+f.l)
VOH----r------+_~

OUTPUT

OD

RIPPLE

VOL-----t--------t---·'-~

VOH

------+.,------

IpHL
(MEASURE AT N+16)
(NOTE B)

CARRY
OUTPUT

VOL - - - TLlF/6606·4

Note A: The input pulses are supplied by a generator having the following characteristics: PRR .:S 1 MHz, duty cycle .:S 50%, ZOUT
Vary PRR to measure fMAX'
Not. B: Outputs' Qo and carry are tested at t n +16 for 9316/83t6, where tn is the bit time when all outputs are low.
Nola C: VREF = 1.5 V.

6-431

I":;:

50 n, 'r S 10 ns, tf S 10 ns.

~~------------------------------------------------------------------------------------~
~

~

:E

Parameter Measurement Information (Continued)

C

~
~

~
:E

c

Switching Time Waveforms
3.0 V
CLOCK INPUT
OV
3.0 V
CLEAR
INPUT
OV
3.0V
LOAD
INPUT
OV
3.0V
DATA INPUTS
A, S, C, AND D
OV
QOUTPUTS
9316

VOH

VOL
3.0V
ENABLE POR
ENABLET
OV
VOH
CARRY
VOL
TLlFJ6606-5

Nole A: The input PUISBS are supplied by generators having the following characteristics: PAR :S 1 MHz. duty cycle :s 50%. ZOUT
Note B: Enable P and enable T setup times are measured at In+16 for 8316/9316.

Note,C: VREF

= 1.5 V.

6·432

1'>:;$

50 n, Ir:S 10 ns, If :S 10 na.

.-------------------------------------------------------------.0
:5:

~National

CO

Co)

.....

~ Semiconductor

.~

o

:5:

co
Co)

DM9318/DM8318 Priority Encoders

.....

CO

General Description

Features

These TTL encoders feature priority decoding of the input
data to ensure that only the highest-order data line is encoded. All inputs are buffered to represent one normalized
Series 54/74 load. The DM9318 and DM8318 encode eight
data lines to three-line (4-2-1) binary (octal). Cascading
circuitry (enable input Eland enable output EO) has been
provided to allow octal expansion without the need for external circuitry. For all types, data inp~ts and outputs are
active at the low logic level.

• Direct replacement for Fairchild 9318
• Pin for pin with popular DM54148/74148
• Encodes 8 data lines to 3-line binary (octal)
• Applications include:
N-bit encoding
Code converters and generators
• Typical data delay 10 ns
• Typical power dissipa,tion 190 mW

Absol~te

Maximum Ratings

(Note 1)
7V

Supply' Voltage

5.5V
- 65·C to 150·C

Input Voltage
Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual·ln-Line Package
OUTPUTS

vee
}16

.-------..
EO
GS
15

14

Inputs
13

11

12

10

.,

1

E1

0

1

2

3

4

5

6

7

A2 A1

AO

Is

H
L
L
L
L
L
L
L
L
L

X
H
X
X
X
X
X
X
X
L

X
H
X
X
X
X
X
X
L
H

X
H
X
X
X
X
X
L
H
H

X
H
X
X
X
X
L
H
H
H

X
H
X
X
X
L
H
H
H
H

X
H
X
X
L
H
H
H
H

X
H
X
L
H
H
H
H
H
H

X
H
L
H
H
H
H
H
H
H

H
H
L
L
L
L
H
H
H
H

H
H
L
H
L.
H
L
H
L
H

P-

rC

2

3

4

5

6

7

.,,4_--=_ _ _ _-'--E=>I,

~

INPUTS

OUTPUTS

Outputs

9

GND

H

H
H
L
L
H·
H
L
L
H
H

H
= High Logic Level, L = Low LogiC Level, X = Don't Care

TLlF/6607·1

9318 (J) 8318 (N)

6-433

GS EO

H
H
L
L
L
L
L
L
L
L

H
L
H
H
H
H
H
H
H
H

co
.,...
C")
co , Recommended Operating Conditions
:iE

-.,...
c
co

Symbol

DM9318

Parameter

DM8318

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units

C")

c:n

Vee

Supply Voltage

c

VIH

High Level Input
Voltage

V1L

Low Level Input
Voltage,

IOH

:iE

2

2

V
V

0.8

0.8

High Level Output
Current

-0.8

-0.8

mA

10L

Low Level Output
Current

16

16

mA

TA

Free Air Operating
Temperature

70

·C

-55

Electrical Characteristics
Symbol

Parameter

'0

125

V

over recommended operating free air temperature (unless otherwise noted)
Conditions

Min

Typ
(Note 1)

Max

Units

VI

Input Clamp Voltage

Vee = Min, 11= "'" 12 mA

VOH

High Level Output
Voltage

Vec= Min, 10H= Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee= Min, 10L= Max
VIH = Min, VIL = Max

0.4

V

II

Input Current@ Max
Input Voltage

Vcc=Max, VI = 5.5V

1

mA

IIH

High Level Input
Current

Vcc= Max
VI=2.4V

oInput

40

p.A

Others

80

Low Level Input
Current

Vcc= Max
VI=0.4V

o Input

-1.6

Others

-3.2

Short Circuit
Output Current

Vcc= Max
(Note 2)

ICCl

Supply Current
Condition 1

Vcc = Max (Note 3)

35

55

rnA

ICC2

Supply Current
Condition 2

Vcc = Max (Note 4)

40

60

rnA

IlL

los

Nola I:
Nola 2:
Nole 3:
Nole 4:

-1.5

DM93

-35

-85

DM83

-35

-85

All typlcals are at VCC=5V, TA=25"C,
Not more than one output should be shorted at a tlm6,
ICClls measured with all inputs and outputs open.
ICC21s measured with Inputs 7 and EI grounded and outputs open,

6·434

V
V

2.4

mA

mA

c
Switching Characteristics
Parameter

at Vcc=5V and TA=25°C (See Section 1 for Test Waveforms and Output Load)
From
(Input)
To
(Output)

Co)

.....

RL=400n

CO

C L =15 pF
Min

~

<0

Units

Typ

Max

10

15

ns

C

~

CO

....

Co)

o thru 7

tpLH Propagation Delay
Time Low to High
Level Output

toABCD
In Phase

tpHL Propagation Delay
Time High to Low
Level Output

o thru 7
toABCD
In Phase

9

14

ns

tpLH Propagation Delay
Time Low to High
Level Output

o thru 7
toABCD
Out of Phase

13

19

ns

tpHL Propagation Delay
Time High to Low
Level Output

o thru 7
toABCD
Out of Phase

12

19

ns

tpLH Propagation Delay
Time Low to High
Level Output

o thru 7

6

9

ns

14

21

ns

18

27

ns

tpHL Propagation Delay
Time High to Low
Level Output

to EO
Out of Phase

o thru 7

-

to EO
Out of Phase

o thru 7

tpLH Propagation Delay
Time Low to High
Level Output

toGS
In Phase

tpHL Propagation Delay.
Time High to Low
Level Output

Othru 7
toGS
In Phase

14

21

ns

tpLH Propagation Delay
Time Low to High
Level Output

EI
to AO, 1,2
In Phase

10

15

ns

tpHL Propagation Delay
Time High to Low .
Level Output

EI
to AO, 1,2
In Phase

10

15

ns

tpLH Propagation Delay
Time Low to High
Level Output

EI
to GS
In Phase

8

12

ns

tpHL Propagation Delay
Time High to Low
Level Output

EI
to GS
In Phase

10

15

ns

tpLH Propagation Delay
Time Low to High
Level Output

EI
to EO
In Phase

10

15

ns

tpHL Propagation Delay
Time High to Low
Level Output

EI
to EO
In Phase

17

26

ns

6·435

CO

,...

=r---------------------------------------------------------------~

CO)

=
:::r!!:

Logic Diagram

-o

,...
=

DM9318318

CO)
0)

(10)

o~~~c

:::r!!:

o

(15)

1

EO

(11_)~H+l1_oI '>-_ _ _---.
(12)

2

(13)

3 -+1-1-++--01 ':>----+-4

INPUTS
(1)

4 --4+#--01

(2)

5 ---<10#--01

6 (3)

7 (4)

(5)

EI -------d>-----------------~~~
TLlF16607·2

6·436

r------------------------------------------------------------------,c
s:
co
~National

~

~ Semiconductor

-s:
N

C

co
Co)

DM9322/DM8322 Quad 2·Line to 1·Line Data
Selectors/Multiplexers

N
N

General Description

Applications

These data selectors I multiplexers contain inverters and
drivers to supply full on-chip data selection to the four output gates. A separate strobe input is provided. A 4-bit word
is selected from one of two sources and is routed to the four
outputs. True data is presented at the outputs.

• Expand any data input paint
• Multiplex dual-data buses
• Generate four"functions of two variables (one variable is
common)

Features

• Source programmable counters

Absolute Maximum Ratings

• Direct replacement for Fairchild 9322
• Pin-far-pin with popular DM54157174157
• Buffered inputs and outputs

(Note 1)

7V
5.5V
- 6S·C to lS0·C

Supply Voltage
Input Voltage
Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" ,able will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual-In-Line Package
INPUTS
-

Vcc

STROBE

116

A4

15

14

.

INPUTS
B4

, OUTPUT
V4
13

A3

12

OUTPUT
V3

B3
11

9

10

,

t-

r0-

1
SELECT

2
A1

3
B1

INPUTS

4
V1
OUTPUT

6

5
A2

.

B2

INPUTS

9322 (J) 8322 (N)

7

Select

A

B

H
L
L
L
L

X

X

L
L
H
H

L
H

X
X
X

X
X

L
H

H = High Level, l = Low Level, X ::. Don'l Care

18

Y2

Inputs
Strobe

GND

OUTPUT
TLlFI660B·1

6-437

Output
Y
L
L
H
L
H

,

Recommended Operating Conditions
Symbol

DM9322
Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

Parameter

DM8322

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

i

Units
V
V

2

-55

Electrical Characteristics
Symbol

I

0.8

0.8

~0.8

-0.8

mA

16

16

mA

70

·C

125

0

V

over recommended operating free air temperature (unless otherwise noted)
Conditions

Min

VI

Input Clamp Voltage

Vee= Min, II = -12 mA

VOH

High Level Output
Voltage

Vee = Min, 10H = Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee = Min, 10L= Max
VIH = Min, VIL= Max

II

Input Current@ Max
Input Voltage

IIH

Typ
(Note 1)

Units

Max
-1.5

2.4

V

3.4

V
,

0.4

V

,Vee=Max, VI=5.5V

1

mA

High Level Input
Current

Vee = Max, VI = 2.4V

40

p.A

IlL

Low Level Input
Current

Vee = Max, VI = O.4V

-1.6

mA

los

Short Circuit
Output Current

Vee = Max
(Note 2)

-20

-55

mA

-18

-55

Supply Current

lee

Note

I DM93
I .DM83
Vee = Max (Note 3)

p.2

30

48

1: All typicals are at Vee=SV. TA=2S'e.

Note 2: Not more than one output should be shorted at a tlma.
Note 3:

lee Is measured with 4.SV applied to all inputs and all out'puts open.

,

,

6·438

mA

c

Switching Characteristics

c.:I

From
(Input)
To
(Output)

Parameter

s::
co

at Vcc=5V and TA=25°C

C L =15pF
Min

Units

Typ

Max

Data
to
Output

8

14

ns

tpHL Propagation Delay
Time High to Low
Level Output

Data
to
Output

10

14

ns

tpLH Propagation Delay
Time Low to High
Level Output

Strobe
to
Output

13

20

ns

tpHL Propagation Delay
Time High to Low
Level Output

Strobe
to
Output

14

21

ns

tpLH Propagation Delay
Time Low to High
Level Output

Select
to
Output

15

23

ns .

tpHL !:'ropagation Delay
Time High to Low
Level Output

Select
to
'Output

17

27

Logic Diagram
DM9318322
(2)
(4)
B1
A2

Y1

(3)

-:=j
(5)
(7)

B2

Y2

(6)

.... ;:::::1

A3 (11)
(9)

B3

(10)

Y3

~t:::I

A4 (14)

I--l...
B4 (13)
~

(1)

SELECT
STROBE

(15)

-

(12)
Y4

t:::j

t>=t>TL/F/6608·2

6-439

C

00

tpLH Propagation Delay
Time Low to High
Level Output

A1

-s::
N
N

RL=4001l

,

ns

~
N

~ ~National

-~ ~ Semiconductor
"="

~ DM9334/DM8334 8·Bit Addressable Latches

:E
C

General Description
The DM9334IDM8334 is a high speed 8-bit Addressable
Latch designed lor general purpose storage applications in
digital systems. It is a multilunctional device capable 01
storing single line data in eight addressable latches, and
being a one-ol-eight decoder and demultiplexer with active
level high outputs. The device also incorporates an active
level low cominon clear lor reselling all latches, as well as
an active level low enable.

transient wrong address. Therefore, this should only be
done while in the memory mode.
The function tables summarize the operation of the
product.

Features
• Direct replacement for Fairchild 9334
•
•
•
•
•
•

The DM9334/DM8334 has lour modes 01 operation which
are shown in the mode selection table. In the addressable
latch mode, data on the data line (D) is written into the ado'
dressed latch. The addressed latch will follow the data input with all non-addressed latches remaining in their
previous states. In the memory mode, all latches remain in
their previous state and are unaffected by the data or address inputs.

Common clear
Easily expandable
Random (addressable) data entry
Serial to parallel capability
8 bits of storage I output 01 each bit available
Active high demultiplexing I decoding capability

Absolute Maximum Ratirigs
Supply Voltage
Input Voltage
Storage Temperature Range

·In the one-ol-eight decoding or demultiplexing mode, the
. ·addressed output will follow the state of the 0 input with all
other inputs in the low state. In the clear mode all outputs
are low and unaffected by the address and data inputs.

not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define !the conditions for actual device operation.

Connection Diagram
I

Dual·ln-Line Package

j1s

15

E

07

D

14

13

OS

12

11

0504
10

9

-

2

AO

A1

3
A2

4
00

7V
5.5V
- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

When operating the device as an addressable latch,
changing more than one bit 01 the address could impose a

Vcc . C

(Note 1)

5
01

S
02

9334 (J) 8334 (N)

6-440

7
03

Is
GND
TLlF/6609·1

Recommended Operating Conditions
Symbol

DM9334

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

DM8334

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

Units
V
V

0.8

0.8

High Level Output
Current

-0.8

-0.8

rnA

10L

Low Level Output
Current

16

16

rnA

tw

ENABLE Pulse Width
(Fig. 1)

tsu

Setup Time

tH

TA

Hold Time

19

13

19

13

ns

Data 1 (Fig. 4)'

20

13

20

13

ns

Data 0 (Fig. 4)

20

14

20

14

Address (Fig. 6)
(Note 1)

10

5

10

5

Data 1 (Fig. 4)

0

-10

0

-10

Data 0 (Fig. 4)

0

-13

0

-13

Free Air Operating
Temperature

-55

Electrical Characteristics
Symbol'

Parameter

125

Conditions

Input Clamp Voltage

Vee= Min, 11= -12 rnA

VOH

High Level Output
Voltage

Vee = Min, 10H = Max
V IL = Max, V IH = Min

VOL

Low Level Output
Voltage

Vee= Min, IOL= Max
VIH = Min, VIL = Max

II

Input Current@Max
Input Voltage

Vee = Max, VI = 5.5V

IIH

High Level Input
Current

Vee = Max
VI = 2.4V

Low Level Input
Current

los

Icc

ns
I

0

70

·C

over recommended operating free air temperature (unless otherwise noted)

VI

IlL

V

Min

Typ
(Note 2)

2.4

3.6

Max
-1.5

0.2

Units
V
V

0.4

V
I

1

rnA
p.A

E Input

60

Others

40

Vee = Max
VI=0.4V

E.lnput

-2.4

Others

-1.6

Short Circuit
Output Current

Vee= Max
(Note 3)

DM93

-30

-100

DM83

-30

-100

Supply Current

Vee = Max

56

Note 1: The ADDRESS setup time is the time before the negative ENABLE transition
without affecting the other latches.

rnA

rnA

that the ADDRESS mUst be stable so that the correct latch is addressed

Note 2: All typicals are at Vce=5V, TA=25-e.
Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.

6·441

86

p.A

Switching Characteristics

at Vcc=5V and TA=25°C (See Section 1 for Test Waveforms and Output Load)
From
(Input)
To
(Output)

Parameter

RL=4001l
CL=15pF
Min

Units

Typ

Max

tpLH Propagation Delay
Time Low to High
Level Output

Enable
to Output
Fig. 1

19

28

ns

tpHL Propagation Delay
Time High to Low
Level Output

Enable
to Output
Fig. 1

18

27

ns

tpLH Propagation Delay
Time Low to High
Level Output

Data
to Output
Fig. 2

24

35

ns

tpHL Propagation Delay
Time'High to Low
Level Output

Data
to Output
Fig. 2

19

28

ns

tpLH Propagation Delay
Time Low to High
Level Output

Address
to Output
Fig. 3

23

35

ns

tpHL Propagation Delay
Time High to Low
Level Output

Address
to Output
Fig. 3

21

35'

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to Output
Fig. 5

21

31

ns

Function Tables

•

E

c

L
H
L

H
H
L

H

L

MODE
Addressable Latch
Memory
Active High Eight
Channel Demultiplexer
Clear

x = Don't Care Condition
l = Low Voltage Level
H = High Voltage Level
QN-1 = Previous Output State

C
L
L
L
L
L

E
H
L
L
L
L

Inputs
D AO

A1

A2

X

X

X

X

L
H

L
L
H
H

L
L
L

L
L
L

00
L
L
H
L

L

L

L

L

H

••• ••• ••
•H
L
L

H

•
•
•H

H

L

X

X

X

X

ON-l

L
L

L

H
H

L
L
L

L
L

L
L

L
H
L
H

L

H

H
H

H
H
H
H
H

H
L
L

H

• • •
• • •
•H •L •L

L

Present Output States
04
05
02
03
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L

••

L

•L

06
L
L
L

07
L
L
L

L
L

L

L
L

H

H ON-l
H ON-l

Mode
Clear

L
Demultiplex

L

L

L

H
Memory

ON-l ON-l ON-l
H ON-l ON-l
ON-l L ON-l
ON-l H ON-l

L

•
•
•
H

01
L
L
L
L
H

••
•

Addressable
Latch

ON-l
ON-l
6·442

L
H

Logic Diagram
DM93/8334

TLlF16609·2

Switching Time Waveforms

D
D

a
OTHER CONDITIONS: E = t,
OTHER CONDmONS,

C = H, A = STABLE

C = H, A = STABLE
TLIFISS09-3

TLlFI6609·4

FIGURE 1

FIGURE 2

tpHL

D

A1

A1

a

01
OTHER CONDITIONS,

E =L, C = L. D = H

OTHER CONDITONS,

C =H. A =STABLE

TLlFI6609·5

TL/F/6609·6

FIGURE 3

FIGURE 4

STABLE ADDRESS

AO

a
OTHER CONDITIONS, E = H

OTHER CONDITIONS,

C =H

TLlFI6609·7

TLlF16609·8

FIGURE 5

FIGURE 6

Note: The shaded areas indicate when the inputs are permitted to change fOr predictable output performance.

6·443

~r---------------------------------------------------------------------------,

~ ~National
-~ ~ Semiconductor
~

~

~
o

DM9601/DM8601 Retriggerable One Shots
General Description

Features

These ret rigger able one shots provide the designer with
four inputs; two active high and two active low. This permits
-a choice of either leading-edge or trailing-edge triggering,
independent of input transition times. When input conditions
for triggering are met, a new cycle starts and the external
capacitor is rapidly discharged and then allowed to. charge
again. The retriggerable feature allows for output pulse
widths to be expanded. In fact a continuous true output can
be maintained by having an input cycle time which is shorter
than the output cycle time. Retriggering may be inhibited by
tying the Q output to an active low input.

• High speed operation-input repetition rate> 10 MHz
• Flexibility of operation-optional retriggering/lock-out
capability
• Output pulse width range-,50 ns to
• Leading or trailing edge triggering
• Complementary outputs/inputs

00

• Input clamping diodes
• DTlITTL compatible logic Illveis

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1) ,

7V
5.5V

- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the deVice can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device: operation.

Connection Diagram

Function Table

Dual·ln·Line Package

ex

I RX

Inputs

I

11---.
.IIJIIv---vee I
I
I
14

13

12

NC
11

NC

Q

9

8

A1

A2

B1

H

H

X

X
X

L

X
X

L
L
L

X
X
X
X
X

H

t

L
H
H

X
X
X

L
L
L

t

H
H

,,

H

+

2

AI

+

A2
TI./F/6610·1

9601 (J)

8601 (N)

6-444

Outputs

B2

H

X
H
H
H
H
H
H

t
t

H
H
H

Q

Q

L
L
L
L

H
H
H
H

JL. 'l.J"
JL. 'l.J"
L

H

JL.
JL.
JL.
JL.
JL.

'l.J"
'l.J"
'l.J"
'l.J"
'l.J"

c

3:

Recommended Operating Conditions

<0

0)

DM9801
Sym

Parameter

Vee

Supply Voltage

V IH

High Level Input
Voltage

DM8601

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

1.9

TA=O'C
TA=25'C

1.7

1.8

TA=75'C

1.6

T A = 125'C
VIL

Low Level Input
Voltage

1.5
V

0.85

TA= -55'C

0.85

TA=O'C
0.9

TA=25'C

0.85
0.85

TA=75'C
TA= 125'C
10H

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

Sym

0.85
-0.72
10
-55

Electrical Characteristics

125

Parameter

Conditions

Input Clamp Voltage

Vee= Min, II = -12 rnA

VOH

High Level Output
Voltage

Vee = Min, 10H = Max
VIL = Max, VIH = Min
(Note 4)

VOL

Low Level Output
Voliage

Vee=Mln
10L= Max
VIL= Max
VIH=Min
(Note 4)

IIH

High Level Input
Current

Vee = Max, VI = 4.5V

IlL

Low Level Input
Current

Vee = Max

Short Circuit
Output Current

Vee = Max
(Notes 2 and 4)

Supply Current

Vee = Max

Icc

Nolel:
Nole 2:
Nole 3:
Nole 4:

0

-0.96

mA

12.8

rnA

75

·c

over recommended operating free air temperature (unless otherwise noted)

VI

los

V
V

2

TA= -55'C

Units

Min

Typ
(Note 1)

Max
-1.5

2.4

Units
V
V

DM96

0.4

DM86

0.45

V

60

p.A

DM96 VIN = 0.40V

-1.6

rnA

DM86 VIN = 0.45V

-1.6

DM96

-10

-40

DM86

-10

-40
25

All typlcals are at Vee=5V, TA=25'e.
Not more than one output should be shorted at a lime.
Unless olherwise noted. RX= 10k between PIN 13 and Vee on alilests.
Ground PIN 11 for VOL test on PIN 6. VOH and lOS tests on PIN 8. Open PIN 11 for VOL lesion PIN 8. VOH and lOS lests on PIN 6.

6·445

rnA

rnA

o.....

-c
3:
CO

0)

o.....

,..

o

t8

SWitching Characteristics

:iE

c

,..
o(0

From
(Input)
To
(Output)

Parameter

0)

:iE

c

at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)

tpLH Propagation Delay
Time Low to High
Level Output

Negative· Trigger
Input to
True Output

tpHL Propagation Delay
Time High to Low
Level Output

Negative Trigger
Input to
Complement Output

Conditions

Min

C L = 15 pF
Cl\=O
Rx =5 kO

tpW(MIN) Minimum True Output
Pulse Width
tpw Pulse Width

Rx= 10 kO
Cx= 1000 pF

CSTRAY Maximum Allowable
Wiring Capacitance

Pin 13 to GND

3.08

Typ

Max

Units

25

40

ns

25

40

ns

45

65

ns

3.42

3.76

I'S

50

pF

Ax External Timing Resistor

DM96

5

25

kO

Ax External Timing ReSistor

DM86

5

50

kO

Operating Rules
1. An external resistor AX and an external capacitor Cx

5. Aetrigger pulse width (see Figure 3) is calculated as follows:

are required for operation. The value of AX can vary between the limits shown in switching characteristics. The
value of Cx is optional and may be adjusted to achieve
the required output pulse width.
2. Output pulse
as follows:
, width tpw may be calculated
.
tpw = K AXCX [1

+

tw = tpw

~. 7 J(for CX> 103 pF)

J "~

L5V

FIGURE 3
TLfF/6610·4

TYPICAL uK" COEFFICIENT VARIATION VS TIMING
CAPACITANCE
The multiplicative factor "K" varies as a function of the
timing capacitor, Cx. The graph below details this
characterist ic:

IOOI'F

l~V

10l'F

VIN

II'F

EO.II'F
... 104 pF

TlIF/6610-2

103 pF

,:;( " F

102 pF

2.5 V

1.5V

~.; ] + tPLH

~tw~

QOUTPUT- - '

FIGURE 1

VIN

+

KAXCX [1

INP~~

X
KzO.34
Ax in kfl, Cx in pF and tpw in ns.
(For Cx < 10' pF, see curve.)
3. AX and Cx must be kept as close as possible to the circuit in order to minimize stray capacitance and noise
pickup. If remote trimming is required, AX may be split up
such that at least AX(MIN) must be as close as possible
to the circuit and the remote portion of the trimming resistor A < AX(MAX) - AX.
4. Set-up time (tl) for input trigger pulse must be> 40 ns.
(See Figure O.
Aelease time (t2) for input trigger pulse must be
> 40 ns. (See Figure 2).

2.5V

+ tPLH =

10pF

1.5V

III ! I !1+A~~5lc'

!ff+-I I : ! i .~

IltlLTi1-r
-I

I •

I' , .

'

Ii

i~·Ti ~
I

! !

,

~:~W+1++
',
j
'i i 'ri
! I

"I~JII

0 .2 .4 .6 .8 1.0 1.2 1.4 1.6
"K" COEFFICIENT
TLiF/6610-5

FIGURE 2
• For further detailed device characteristics and output performance,
please refer to the NSC one-shot application note I AN·366.

TUFf6610-3

6·446

.----------------------------------------------------------------------,0
s:
CO

Typical Performance Characteris,tics

Q)

Output Pulse Width vs
Timing Resistance And
Capacitance For
Cx < 10' pF

Normalized Output
Pulse Width vs Ambient
Temperature

104

i

v v.;

!

~

%

i

103
RX - 50k

w

-:!::j:.I

UJ

i

.

I-

=>

102

.;'

-t-1"" J....-

~k

§

VRX = 30k



8.0

c

~r--

V ......

0.90
4.0

4,5

5.0

V

20

6.0

TLI F/661 0·8

!
j!:
iw

..

l/

90
Vee - 5.0 V
RX = 5.0k
Cx=O

70
COMPLEMENTARY OUTPUTl.,...j---50

TRUE OUTPUT

S
C

:Ii

=>

i

4.0
10

5.5

SUPPLY VOLTAGE (V)

~
5

/

V

o

Output Pulse Width vs
Ambient Temperature

20

w

f-I-I-I-HH--1i"""1

V ......

TLJF/6610·7

!

-s:

= 25°C
= 10 k
= 103 pF

TA
RX
Cx

Pulse Width vs Timing
Resistance

r---r----r-,--.--r-,.-,---,
Vec = 5.0 V

1,.

1.10

T A - AMBIENT TEMPERATURE ('C)

Normalized Output
Pulse Width vs
Operating Duty Cycle

i

~

i

0,95

I""

0.90

o
....

Normalized Output
Pulse Width vs Supply
Voltage

30

40

50

RX - EXTERNAL TIMING RESISTANCE (kll)

TL/F/6610·g

TLlF/6610·10

Schematic Diagram .
(13)

(11)

6-447

30

10
-75

-25

25

75

125

TA - AMBIENT TEMPERATURE (OC)
TL/FJ6610-11

co
~
....

~ ~ National
~ ~ Semiconductor
co

~

0)

~

c

DM9602/DM8602 Dual Retriggerable, Resettable One Shots
General Description
These dual resettable. retriggerable one shots have two inputs per function; one which is active high. and one which is
active low. This allows the designer to employ either leading-edge or trailing-edge triggering, which is independent
of input transition times. When input conditions for triggering are met, a new cycle starts and the external capacitor is
allowed to rapidly discharge and then charge again. The.
retriggerable feature permits output pulse widths to be extended. In fact a continuous true output can be maintained
by having an input cycle time which is shorter than the output cycle time. The output pulse may then be terminated at
any time by applying a low logic level to the RESET pin.
Retriggering may be inhibited by either connecting the Q
output to an active high input. or the output to an active
low input.

a

Features

• Complementary TTL outputs
• Optional retrigger lock-out capability .
• Pulse width compensated for Vee and temperature
variations

Absolute Maximum Ratings (Note 1)
7V
5.5V
- 65·C to 150·C

Supply Voltage
Input Voltage
Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parame~rlc v~lues defined in the
"Electrical Characteristics" table are .not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table wUl
. define the conditions for actual device operation.

• 70 ns to 00 output width range
• Resettable and retriggerable-O% to 100% duty cycle
• TTL input gating-leading or trailing edge triggering

Connection Diagram

Function Table

Dual-tn-Line Package

IIcc

CEXT2

REXT'
CEXT2

CLR2

116

15

14

13

B2
112

I
I

I

1

A2

Q2

02

111

110

II

-

2

~

1

~

CEXTI

Pin No's.

(

I
2

3

REXT'
CEXTl

CLRl

14
Bl

5
1
Al

6
01

7
Ql

I
B

GND

TLlFf6611-1

9602 (J)

Operation

A

B

CLR

H-L
H
X

L
L-H
X

H
H
L

H = High Voltage Level
L = Low Voltage Level
X = Don't Care

I
1

9

8602 (N)

6-448

Trigger
Trigger
Reset

c

:s:
<0

Recommended Operating Conditions
Sym

Parameter

Vee

Supply Voltage

V IH

High Level Input
Voltage

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V

1.9
1.8

1.7

1.65

T A =75'C
T A =125'C
Low Level Input
Voltage

Units

V

2

TA=O'C

1.5
V

0.85

T A = -55'C

0.85

TA=O'C

0.85

0.9

T A =25'C

0.85

T A =75'C
0.85

TA = 125'C
IOH

High Level Output
Current

-0.8

-0.8

mA

.IOL

Low Level Output
Current

16

16

mA

TA

Free Air Operating
Te'mperature

75

'C

-55

125

0

,

Electrical Characteristics
Sym

over recommended 'operating free air temperature (unless otherwise noted)

Parameter

Conditions

VI

Input Clamp Voltage

VOH

High Level Output
Voltage

Vee=Min,loH=Max
VIL = Max, VIH = Min
(Note 4)

VOL

Low Level Output
Voltage

Vee= Min
10L=Max
VIL = Max
VIH=Min
(Note 4)

IIH

High Level Input
Current

Vce = Max, VI = 4.5V

IlL

Low Level Input
Current

Vce=Max

,

Icc

Nol.l:
Nole 2:
Note 3:
NOI.4:

Typ
(Note 1)

Vee=Min

Max
-1.5

Vee=Min, 11= -12 mA

DM96

0.4

DM86

0.45

V

V

60

/LA

DM96 VI = 0.40V

-1.6

mA

DM86 VI = 0.45V

-1.6

DM96 VI = 0.40V
,

-1.24

.

-1.41

Short Circuit
Output Current

Vee = Max
(Notes 2 and 4)

DM96

-25

DM86

-35

Supply Current

Vee= Max

DM96

39

45

DM86

39

50

Aillypicals are at

Units

V

2.4

DM86 VI = 0.45V
105

Min

mA

mA

Vee~5V, TA~25·e.

Not more than one output should be shorted at a time.
Unless otherwise noted, RX

=10k for all tests.

Ground PIN i(15) for VOL on PIN 7(9) or VOH and 105 on PIN 6(10) and apply momentary ground to PIN 4(12), Open PIN 1(15) for VOL on PIN6(10) or
VOH and lOS on PIN 7(9).

6·449

-:s:
I\)

Min

T A = -55'C

TA =25'C

VIL

en
o

DM8602'

DM9602

c

CO

en

oI\)

Switching Characteristics

VCC

= 5 V, TA = 25°C

(See Section 1 for Test Waveforms and Output Load)
DM96

Symbol

Parameter

Conditions

DM86

02
Min

Units

02

Typ

Max

25

Min

Typ

Max

35

25

40

ns

29

43

29

48

ns

Propagation Delay Time,
Low-to-High Level Output

Negative Trigger Input
to True Output

tPHL

Propagation Delay Time,
High-to-Low Level Output

Negative Trigger Input
To Complement Output

tpw (MIN)

Minimum True Output
Pulse Width

72

90

72

100

Minimum Complement
~ulse Width

78

100

78

110

3.42

3.76

3.42

3.76

p's

50

pF

50

kG

tPLH

CL = 15 pF
Cx = 0
RX = 5 kG

ns

tpw

Pulse Width

CSTRAY

Maximum Allowable Wiring
Capacitance

RX

External Timing Resistor

RX - 10 kG,
3.08
Cx = 1000 pF
Pins 2, 14 to
GND

3.08

50
5

25

5

Logic Diagrams
Cx

~I f,,)

Cx

RX (16)

'.

(6)

(14)

_

~

-

(7)

Co

Vce

or(12)

-

.\.A

(10)

ot-(4)

iD- ./

RX (16)

~)f

Vee

at--

./
(9)

CD

1(3)

at--

1(13)
TLlFf6611·2

TLfF/6611·3

Operating Rules

4. If electrolytic type capacitors are to be used, the foilowing three configurations are recommended:

l. An external resistor (RX) and external capacitor (CX)

are required as shown in the Logic Diagram.

A. Use with low leakage capacitors:
The normal RC configuration can be used pradictably only if the forward capacitor leakage at 5.0 V is .
less than 3 p.A, and the inverse capacitor leakage at
1.0 V is less than 5 p.A over the operational temperature range.

2. The value of Cx may vary from 0 to any necessary value available. If, however, the capacitor has leakages
approaching 3.0 p.A or if stray capacitance from either
terminal to \lround is more than 50 pF, the timing equations may not represent the pulse width obtained.
3. The output pulse with (t) is defined as follows:

(14)

VCC~PIN2
RX
ex

1 ] forC x >103 pF
t = K RXCX 1 + RX K",O.34
where RX is in kG, Cx is in pF
t is in ns
for Cx < 103 pF, see Figure 1.
for K vs C x see Figure 6.
[

(15)
R Rx·(Mln)

2.S V
1.5 V

Input to Pin 4 (12)
Pin 5 (11) = HIGH

Ry

(14)

ov

aOUTPUT

t "" 0.3 RCX

Ql.

(1:sv ~l.SV

TLIF 16611·5

C. Use to obtain extended pulse widths:
This configuration can be used to obtain extended
pulse widths, because of the larger timing resistor
allowed by beta multiplication. Electrolytics with
high inverse leakage currents can be ~sed.
R < RX (0.7) (hFE al) or < 2.5 Mil, whichever is
the lesser
RX (min) < Ry < RX (max)
(5 kll ~ Ry ~ 10 kll is recommended)
a 1: NPN silicon transistor with hFE requirements of
above equations, such as 2N5961 or 2N5962.

R

I~

=

L(IS)

VCCI&

1.S V

-j

TLlF/6611·8

Cx 2
,PIN 1

v

Input to Pin 5 (11),
(Pin 3 (13) = HIGH)
Pin 4 (12)
LOW
tl, t3 = Min. Positive Input Pulse Width> 40 ns
t2, t4 = Min. Negative Input Pulse Width> 40 ns

V~(14)
PIN
R

2.S
1.S V

Cov

a OUTPUT

t "" 0.3 RCX

CC

v --+,-"""\1

OV

R (Max)-R
X
X
INPUT
TLlF/6611·7

RESET

6. Under any operating condition, Cx and RX (min) must
be kept ss close to the circuit ss possible to minimize
stray capacitance and reduce noise pickup.

a OUTPUT

Q OUTPUT
TLlF/6611-11

10. VCC and Ground wiring should conform to good high
frequency standards so that switching transients on
VCC and Ground leads do not cause interaction be·
tween one shots. Use of a 0.01 to 0.1 I'F bypass ca·
pacitor between VCC and Ground located near the
DM9602/DM8602 .is recommended.
·For further detailed device characteristics and output performance,
please refer to the NSC one-shot application note, AN·366.

6·451

Typical Performance Characteristics
32 1.10

!
io'

~

"//

iii5 103HR~X~~50~k~~~~a;~~~
b
....
~
~
I--"~k
%

it

......

..>

II RX.
RX

2

110

RX

II

5 kl

VCC = 5.0V
RX = 10 k!l
Cx = 103 pF

~

/~

1.05

" "'I'...

~

~ 1.00

5o

2.0 k

e
~

10';=

I

10 L-I.--L...L..L..L
1--L.--L-UII.J....I.I-...J...J...J..J
1
10
102
103

0.95

Z 0.90

-25

-75

25

TL/F/6611-12

..=,
%
l-

%

w
..J

~ 1.00

/

:::>

Il.

e

w

~ 0.95

6

I-

:::>

./

0

2

10

20

V

o

,r

I-

30

40

~

4.5

5.0

TLIF/6611·14

~

:::>

. TLlF16611·15

I I

100

iii!

i

Vcc=5.0V

8 o.1 1'F

L

COMPLEMENTARY OUTPUT/

Y
-

90

:Ii
:::>
:Ii

+A~k5~CI

V6c = 5.0 V
RX = 5 k!l
Cx = 0
CL = 15 pF

110

1
Il.

80

I

70

Co>

60

-75

-25

25

102 pF

1 1
75

104 pF
103 pF

j.......- r-

TRUE OUTPUT

j

6.0

FIGURE 4. Normalized Output Pulse Width vs Supply
Voltage

'OJ' 140

120

5.5

VCC· SUPPLY VOLTAGE (V)

FIGURE 3. Pulse Width vs Timing Resistor

130

../'

:/

10.90
4.0

50

. Px • EXTERNAL TIMING RESISTOR (KIl)

.:.
%
5iii

./

:/

~
5

/

10

Il.

TA = 25°C
RX = 10 k!l
Cx = 103 pF

llll.05

/

iii

1.10

~

/

14

e

'":::>

FIGURE 2. Normalized Output Pulse Width vs Ambient
Temperature

V~C =15.0~
Cx = 103 pF

125

TLlF16611·13

FIGURE 1. Output Pulse Width vs Timing Resistance
and Capacitance For Cx < 103 pF

'OJ'

75

T A • AMBIENT TEMPERATURE (OC)

Cx • TIMING CAPACITANCE (pF)

18

-

........ ~

10pF

125

TA • AM81ENT TEMPERATURE (OC)
TLfF/6611·16

... ~

o

.2

.4 .6 .8 1.0 1.2 1.4 1.6
"K" COEFFICIENT
T....LlFI6611.17

FIGURE 5. Minimum Output Pulse Width vs Ambient
Temperature

FIGURE 6. Typical "K" Coefficient Variation vs Timing
Capacitance

6·452

Section 7

Low Power

Section Contents
DM54/74LOO Quad 2-lnput NAND Gates ............................................. .
DM54/74L01 Quad 2-lnput NAND Gates with Open-Collector Outputs .................... .
DM54/74L02 Quad 2-lnput NOR Gates .............................................. .
DM54/74L03 Quad 2-lnput NAND Gates with Open-Collector Outputs .................... .
DM54/74L04 Hex Inverters ....................................................... .
DM54/74L05 Hex Inverters with Open-Collector Outputs ............................... .
DM54/74L08Quad2-lnputANDGates ......................... , .................... .
DM54/74L 10Triple3-lnput NAND Gates ...................... _..................... .
DM54/74L.11 Triple3-lnput AND Gates .............................................. .
DM54/74L20 Dual4-lnputNAND Gates ............................................. .
DM54/74L26 Quad 2-lnput NAND Buffers with High-Voltage Open-Collector Outputs ....... .
DM54/74L30 8-lnput NAND Gate .................................................. .
DM54/74L42A BCD to Decimal Decoder ...... : .......... : .......................... .
DM54/74L51 DuaI2-Wide2-lnputAND-OR-INVERTGates ..... : ........................ .
DM54/74L54 4-WideAND-OR-INVERTGates ........................................ .
DM54/74L55 2-Wide 4-lnput AND-OR-INVERT Gates .................................. .
DM54/74L71 AND-Gated Master-Slave R-S Flip-Flop with Preset and Clear ... '.' ........... .
DM54/74L72 AND-Gated Master-Slave J-K Flip-Flop with Preset and Clear ................ .
DM54/74L73 Dual J-K Flip-Flops with Clear ...................... .' ................... .
DM54/74L74 Dual Positive-Edge-Triggered D Flip-Flops with Preset and Clear ............. .
DM54/74L75A 4-Bit Bistable Latches .............................................. .
DM54/74L78 Dual J-K Flip-Flops with Common Clear and Common Clock ................. .
DM54/74L85 4-Bit Magnitude Comparators ......................................... .
DM54/74L86 Quad Exclusive-OR Gates ..... ; ....................................... .
DM54/74L90 4-Bit Decade Counter ........................ _....................... .
DM54/74L93 4-Bit Binary Counter ................................................. .
DM54/74L95 4-Bit Parallel Access Shift Register .................................... " .
DM54/74L98 4-Bit DataSelectorlStorage Register ................................... .
DM54/74L157A Quad 2 to 1 Line Data Selectors/Multiplexers .......................... .
DM54/74L 164A 8-Bit Serialln/Paraliel Out Shift Register with Asynchronous Clear .... : .... .
DM54/74L 165A 8-Bit Parallel In/Serial Out Shift Register with
Complementary Outputs ....................................................... .
DM54/74L 192 Synchronous 4-BitUp/Down Decade Counter with Dual Clock .............. .
DM54/74L 193 Synchronous 4-Bit Up/Down Binary Counter with Dual Clock ............... .
DM80L06Quad 2-lnput NAND Gate(Passive Pull-Up) .................................. .
DM70/80L98 Hex Inverting Buffers with TRI-STATE Outputs ..... _...................... .
DM71 181 L22 Quad 2-lnputDataSelector/Multiplexer. .......... _................ , ...... .
DM71/81 L23 Quad 2-lnput Data Selector/Multiplexer with TRI-STATE Outputs ............. .
DM75/85L51 4-Bit D Type Register with TRI-STATE Outputs ............................ .
DM75/85L52 Synchronous Decade Countl:lr/Latch with TRI-STATE Outputs .......... _.... .
DM75/85L54 Synchronous Binary Counter/Lat.ch with TRI-STATE Outputs ................ .
DM75/85L60 Synchronous 4-Bit Up/Down BCD Counter ............................... .
DM75/85L63Synchronous4-Bit Up/Down BinaryCounter .. , .................. _........ .
DM76/86L70 8-Bit Serialln/Paraliel Out Shift Register ......... _...................... .
DM76/86L75 Synchronous Presettable Decade Counter ............................... .
DM76/86L76 Synchronous Presettable Binary Counter ................................ ~
DM76/86L90 8-Bit Parallelln/Serial Out Shift Registerwith Complementary Outputs ....... .

7-2

7-3
7-5
7-7
7-9
7-11
7-13
7-15
7-17
7-19
7-21
7-23
7-25
7-27
7-30
7-32
7-34
7-36
7-39
7-42
7-45
7-48
7-51
7-54
7-57
7:60
7-60
7-66
7-69
7-72
7-75
7-78
7-82
7-82
7-89
7-91
7-94
7-94
7-100
7-104
7-104
7-111
7-111
7-118
7-121
7-121
I
7-125

c

:s:
U1

.
~ Semiconductor
~National

.1:10

r-

o
o

-:s:c
:j;;!
ro

o

DM54LOO/DM74LOO Quad 2-lnput NAND Gates

General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic NAND function.

Supply Voltage
Input Voltage

(Note 1)
8V

5.5V
-65'Cto 150'C

Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual·ln·Line Package

Y=AB
Inputs
B

Y

L
L
H
H

L
H
L
H

H
H
H
L

H = High Logic Level
L = Low Logic Level
Al

"

VI

A2

B2

'2

GND

TlIF/6654·'

DM54LOO (J)

DM74LOO (N)

7·3

Output

A

Recommended Operating Conditions
Symbol
Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units
V
V

2

2
0.7

0.7

V

-0.2

-0.2

mA

2

3.6

mA

70

·C

I.

-55

Electrical Characteristics
Symbol

DM74LOO

DM54LOO

Parameter
I

:
Parameter

125

0

over recommended operating free air temperature (unless otherwise noted)
Conditions

VOH

High Level Output
Voltage

Vee = Min, 10H = Max
VIL = Max

VOL

Low Level Output
Voltage

Vcc= Min
10L=Max
VIH=Min

II

Input' CUffEint@Max
Input Voltage

IIH

Min

Typ
(Note 1)

2.4

3.3

Max

Units
V

DM54

0.15

0.3

DM74

0.2

0.4

V

Vce = Max, VI = 5.5V

0.1

mA

High Level Input
Current

Vce = Max, VI = 2.4V

10

p.A

IlL

Low Level Input
Current

Vce = Max, VI = 0.3V

los

Short Circuit
Output Current

Vee = Max
(Note 2)

lecH

Supply Current With
Outputs High

Vec=Max

0.44

0.8

mA

lecL

Supply Current With
Outputs Low

Vce=Max

1.16

2.04

mA

Switching Characteristics

-0.18

mA
mA

DM54

-3

-15

DM74

-3

-15

at Vcc = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
RL=4 kO

Parameter

Conditions

C L =50 pF
Min

Units

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

35

60

ns

tpHL Propagation Delay Time
High to Low Level Output

31

60

ns

Note 1:

All typlcals are at Vec=SV, TA=2S'C.

i

Note 2: Not more than o~e output should be shorted at a time.

7·4

-

.----------------------------------------------------------,0
3:

'?A National

en
01:>0

~ Semiconductor

b
....

o
3:

DM54L01/DM74L01 Quad 2·lnput NAND Gates
with Open·Coliector Outputs

~

b
....

General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic NAND function. The opencollector outputs require external pull-up resistors for
proper logical operation.

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

Pull·Up Resistor Equations
RMAX

=

8V

5.5V
8V

- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Vee (Min) - VOH
Nl (IOH) + N2 (lIH)

R
Vee (Max) - VOL
MIN = IOL - N3 (IIU
Where:

Nl (loH) = total maximum output high current
for all outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for
all inputs -tied to pull-up resistor
N3 (lid = total maximum ioput low current for
all inputs tied to pull-up resistor

Connection Diagram

Function Table

Dual-In-Line Package
Vee'

V4

B4

A4

V3

BJ

A3

Y=AB
Inputs

VI

AI

"

V2

A2

82

DM74S01 (N)

7-5

Output,

A

B

Y

L
L
H
H

L
H
L
H

H
H
H
L

H= High Logic Level
L = Low Logic Level

.N.
TLiF/6655-1

DM54L01 (J)

(Note 1)

.

....
o
...I

~

Recommended Operating Conditions

~

-

Sym

Parameter

~
:E

Vee
VIH
Vil

Low Level Input
Voltage

0.6

VOH

High Level Output
Voltage

IOl

Low Level Output
Current

TA

Free Air Operating
Temperature

c

....
9
c

DM74L01

DM54L01
Min

Nom

Max

Min

Nom

Max

Supply Voltage

4.5

5

5.5

4.75

5

5.25

High Level Input
• Voltage

2

V
V

2

-55

Units

,

0.6

V

5.5

5.5

V

2

3.6

mA

70

·C

125

0

Electrical' Characteristics over reeom~ended operating free air temperature (unless otherwise noted)
Syll'

Parameter

IC;:EX

High Level Output
Current

Vee = Min, Vo=5.5V
Vll=Max

VOL

Low Level Output
Voltage

Vee=Mln
IOl=Max
VIH= Min

II

Input Current@Max
Input Voltage

Vee = Max, VI = 5.5V

IIH

High Level Input
Current

Vee = Max, VI = 2.4V

III

Low Level Input
Current

Vee = Max, VI = 0.3V

leeH

Supply Current With
Output,s High

Vee = Max

leel

Supply Current With
Outputs Low

Vee = Max

Typ
(Note 1)

Min

Conditions

Max

Units

50

p.A

DM54

0.15

0.3

DM74

0.2

0.4

V

0.1

mA

10

p.A

,

-0.18

mA

0.44

0.8

mA

1.16

2.04

mA

Switching Characteristics at Vee=5V and TA =25·C (See Section 1 for Test Waveforms arrd Output Load)
Rl=4 kO
Parameter

Cl=50 pF

Conditions
Min

Units

Typ

Max

tplH Propagation Delay Time
Low to High Level Output

60

90

ns

tpHl Propagation Delay Time
High to Low Level Output

33

60

ns

Note 1:

Aillypicals are al Vee = SV, TA=2S"e.

;

:

7·6

c

s:
U1

~National

~

~ Semiconductor

b

-s:
N

C

~
o

DM54L02/DM74L02 Quad 2·lnput NOR Gates

rN

General Description

Absolute Maximum Ratings (Note 1)

This device contains four independent gates each of
which performs the logic NOR function.

Supply Voltage
Input Voltage

BV
5.5V

- 65 ·C to 150·C

Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual-In-Line Package

v,

.,

"

Y=A+B
Inputs

B

Y

L
L
H
H

L
H
L
H

H
L
L
L

H = High Logic Level
L = Low Logic Level
TLlF/6656·1

DM54L02 (J)

DM74L02 (N)

7-7

Output

A

Recommended Operating Conditions
Sym

DM54L02

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

Units
V
V

0.7

0.7

-0.2

-0.2

mA

3.6

rnA

70

·C

2
125

-55

Electrical Characteristics

0

V

over recommended operating free air temperature (unless otherwise noted)

Sym

Parameter

VOH

High Level Output
Voltage

Vee=Min,loH=Max
VIL=Max

VOL

Low Level Output
Voltage

Vee = Min
10L=Max
V IH = Min

Input Current@Max
Input Voltage

II

DM74L02

Conditions

Min

Typ
(Note 1)

2.4

3.3

Max

Units
V

DM54

0.15

0.3

DM74

0.2

0.4

V

Vee = Max, VI = 5.5V

0.1

mA

10

p.A

IIH

. High Level Input
Current

Vee = Max, VI = 2.4V

IlL

Low Level Input
Current

Vee = Max, VI=0.3V

los

Short Circuit
Output Current

Vee = Max
(Note 2)

leeH

Supply Current With
Outputs High

Vee = Max

0.8

1.6

mA

leeL

Supply Current With
Outputs Low

Vee=Max

1.4

2.6

mA

Switching Characteristics

.

-0.18

mA
mA

DM54

-3

-15

DM74

-3

-15

at Vee=5V and TA=25·C (See Section 1 for Test Waveforms and Output Load)
RL=4 kll

Parameter

Conditions

CL=50pF
Min

Units

Typ

tpLH Propagation Delay Time
Low to High Level Output

31

tpHL Propagation Delay Time
High to Low Level Output

35

Max
60

ns

60

ns

I

Note 1: All typical. are at Vee=Sv, TA=2S·e.
Note 2: Not more than one output should be shorted at a time.

7-8

o

S

~National

.
~ Semiconductor

U1

.j::Io

r-

oCo)

o
S

~

DM54L03/DM74L03 Quad 2-lnput NAND Gates
with Open-Collector Outputs
General Description

r-

oCo)

Absolute Maximum Ratings

BV

This device contains four independent gates each of
Supply Voltage
which performs the logic NAND function. The openInput Voltage
collector outputs require external pull-up resistors for· Output Voltage
proper logical operation.
Storage Temperature Range

Pull·Up Resistor Equations
R

Vee (Min) - VOH
N1 (IOH) + N2 (lIH)

R

Vee (Max) - VOL
10L -N3 (IIU

MAX=

MIN=

Where:

5.5V

BV
- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device Should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

N1 (I OH ) = total maximum output high current
for all outputs tied to pull-up resistor
N2 (lIH) = total maximum input high current for
all inputs tied to pull-up resistor
N3 (Ilu = total maximum input low current for
all inputs tied to pull-up resistor

Connection Diagram

Function Table

Dual-In-Line Package
Y=AB

Inputs
B

Y

L
L

L

H

H

I:l

L

H

H

L

H; High Logic Level

L= Low Logic Level
81

Y1

A2

BZ

Y2

GNO

TLlF/6615·1

DM54L03 (J)

DM74L03 (N)

7-9

Output

A

H
H

A1

(Note 1)

Recommended Operating Conditions
DM74L03

DM54L03

Sym

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

0.6

0.6

V

VOH

High Level Output
Voltage

5.5

5.5

V

IOL

Low Level Output
Current

2

3.6

mA

TA

Free Air Operating
Temperature

70

·C

Electrical

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

-55

125

V
V.

2

2

Units

0

Characteristi~s over recommended operating free air temperature (unless otherwise noted)

Sym

Parameter

ICEX

High Level Output
Current

Vcc=Min, Vo=5.5V
VIL = Max

VOL

Low Level Output
Voltage

Vcc=Min
IOL= Max
VIH=Min

II

Input Current@Max
Input Voltage

Vcc = Max, VI = 5.5V

IIH

High Level Input
Current

Vcc = Max, VI = 2.4V

IlL

Low Level Input
Current

Vcc = Max, VI = 0.3V

ICCH

Supply Current With
Outputs High

Vcc=Max

ICCL

Supply Current With
Outputs Low

Vcc=Max

Conditions

Min

Typ
(Note 1)

Max

Units

50

p.A

DM54

0.15

0.3

DM74

0.2

0.4

V

0.1

mA

10

p.A

,

SWitching Characteristics at Vcc = 5V and TA = 25·C

-0.18

mA

0.44

0.8

mA

1.2

2.04

mA

(See Section 1 for Test Waveforms and Output Load)
RL=4 kll

Parameter

Conditions

CL=50 pF

Units

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

60

90

ns

tpHL Propagation Delay Time
High to Low Level Output

33

60

ns

Min

Nole 1: All typical. are at VCC=5V. TA=25·C.

7·10

~National

~ Semiconductor

DM54L04/DM74L04 Hex Inverting Gates
General Description

Absolute Maximum Ratings

This device contains six indepjlndent gates each of
which performs the logic INVERT function.

Supply Voltage
Input Voltage

(Note 1)
8V

5.5V
- 65·C to 150·C

Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual·ln·Line Package

Vi
114

A'

Y6

13

12

AS

"

YS

A.

Y=A

V4

10

Input

Y

L

H
L

H
H = High Logic Level

l = Low Logic Level

Al

VI

A'

v,

AJ

TLlFI6616-1

DM54L04 (J)

DM74L04 IN)

7·11

Output

A

Recommended Operating Conditions
DM54L04
Sym

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

V1L

Low Level Input
Voltage

IOH

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

DM74L04

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

'4.75

5

5.25

2

Units
V
V

2

V

0.7

0.7

-0.2

-0.2

rnA

3.6

rnA

70

·C

2
":'55

125

0

-.

Electrical Characteristics

over recommended operating free air temperature (unless otherwise noted)

Sym

Parameter

Conditions

VOH

High Level Output
Voltage

Vee=Min,loH=Max
V1L= Max

Low Level Output
Voltage

Vee=Min
10L= Max
VIH=Min

II

Input Current@Max
Input Voltage

IIH

Min

Typ
(Note 1)

2.4

3.3

Max

Units
V

,
DM54

0.15

0.3

DM74

0.2

0.4

V

Vee = Max, VI = 5.5V

0.1

mA

High Level Input
Current

Vee = Max, VI := 2.4V

10

p.A

IlL

Low Level Input
Current

Vee = Max, VI = 0.3V

los

Short Circuii
Output Current

Vee = Max
(Note 2)

leeH

Supply Current With
Outputs High

leeL

Supply Current With
Outputs Low

VOL

-0.18
DM54

-3

DM74

-3

-15

mA

- mA

-15

Vee = Max

0.6

1.2

mA

Vee=Max

1.7

3.06

mA

SWitching Characteristics

at Vee = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
RL = 4 kn

Parameter

C L =50 pF

Conditions

Units

Typ

Max

tpLH Propagation Delay Time
'Low to High Level Output

35

60

ns

tpHL Propagation Delay Time
High to Low Level Output

31

60

ns

Min

Note 1: All typicals are at Vee=5V, TA=25'e.
Note 2: Not more than one output should be shorted at a time

7·12

.------------------------------------------------------------,0
:s::

~National

~

~ Semiconductor

b

en

o

:s::
~
o
en

DM54L05/DM74L05 Hex Inverters
with Open-Collector Outputs

r-

General Description

Absolute Maximum Ratings

This device contains six independent gates each of
which performs the logic INVERT function. The opencollector outputs require external pull-up resistors for
proper logical operation.

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

(Note 1)

BV
S.SV

BV
- 6SoC to 1S0·C

Pull·Up Resistor Equations·
Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

R
Vee (Min) - VOH
MAX = N1 (IOH) + N2 (lIH)
R
MIN

=

Where:

not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Vec(Max) - VOL
IOL - N3 (lIU
N1 (lOH) = total maximum output high current
for all outputs tied to pull-up resistor
N2 (IIH) total maximum input high current for
all inputs tied to pull-up resistor
N3 (lIU = total maximum input low current for
all inputs tied to pull-up resistor

=

Connection Diagram

Function Table

DuaHn-Line Package
AS

VB

13

AS

12

4>0-{>o1

AI

2

A4

ID

J
A2

V4

Y=A

,

~

4>0-{>o-

VI

\'5

11

-{>o4

V2

•
AJ

Output

A

Y

L

H

H

L

H= High Logic Level
L= Low Logic Level
6

VJ

J:
TLlFf6617·1

DM54L05 (J)

Input

DM74L05 (N)

7-13

Recommended Operating Conditions
Sym
Vcc

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level Input
Voltage

VOH

High LeVel Output
Voltage

IOl

Low Level Output
Current

TA

Free Air Operating
Temperature

DM74LOS

DMS4LOS

Parameter

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

,
V
V

0.6

0.6

V

-5.5

5.5

V

2

3.6

mA

70

·C

-55

Electrical Characteristics

Units

125

0

over recommended operating free air t,emperature (unless otherwise noted)'

Sym

Parameter

Conditions

ICEX

High Level Output
Current

VOL

Low Level Output
Voltage

Vcc= Min
IOl= Max
VIH = Min

II

Input Current@Max
Input Voltage

IIH
III

Typ
(Note 1)

Min

Max

Units

50

/LA

Vcc=Min, Vo=5.5V
. VIL=-Max
DM54

0.15

0.3

DM74

0.2

0.4

V

Vcc = Max, VI = 5.5V

0.1

mA

High Level Input
Current

Vcc = Max, VI = 2.4V

10

/LA,

Low Level Input
• Current

Vcc = Max, VI = 0.3V

-0.18

mA

,

ICCH

Supply Current With
Outputs High

Vcc= Max

0.66

1.2

mA

ICCl

Supply Current With
Outputs Low

Vcc=Max

1.74

3.06

mA

, Switching Characteristics

at Vcc=5V and TA =25·C (See Section 1 for Test Waveforms and Output Load)
Rl=4kO

Parameter

Cl=SO pF

Conditions

Units

Typ

Max

IplH Propagation Delay Ti,me
Low 10 High Level Output'

60

90

ns

tpHl Propagation Delay Time
High to Low Level Output

33

60

ns

'Min

Note 1:

All

typlcals are at

VCC=SV. TA=2S'C,

7-14

~National

~ Semiconductor
. DM54L08/DM74L08 Quad 2·lnput AND Gates
General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic AND function.

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

BV
5.5V
-65°Ct0150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connec_tion Diagram

Function Table

Dual·ln·Line Package
Y=AB
Inputs
B

Y

L
L
H
H

L
H
L
H

L
L
L
H

H = High Logic Level
L = Low Log Ie Level

"

B1

V1

'2

B1

V2

GND
TLlFf661B·1

DM54S0B (J)

DM74S0B (N)

7·15

Output

A

Recommended Operating Conditions
DM54L08
Symbol

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

DM74L08

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

Units
V
V

0.7

0.7

-0.2

-0.2

mA

3.6

mA

70

'c

2
-55

125

0

V

E;lectrical Characteristics over recommended operating 'free air temperature (unless otherwise noted)
Parameter

Symbol

Conditions

VI

Input Clamp Voltage

Vee = Min, 11= -12 mA

VOH

High Level Output
Voltage

Vee = Min, 10H = Max
VIH=Min

VOL

Low Leyel Output
Voltage

DM54
Vee = Min
IOL= Max
DM74
VIH = Min, VIL = Max

,

I

Min

Typ
(Note 1)

2.4

3.3

Max
-1.5

Units
V
V

0.15

0.3

0.2

0.4

V

II

Input Current@Max
Input Voltage

Vee = Max, VI = 5.5V

0.1

mA

IIH

High Level Input
Current

Vec = Max, VI = 2.4V

10

/LA

IlL

Low Level Input
Current

Vee=Max, VI=0.3V

los

Short Circuit
Output Current

Vee= Max
(Note 2)

'leeH'

Supply Current With
Outputs High

Vee=Max

1.1

2.1

mA

leeL

Supply Current With
Outputs Low

Vee=Max

2.0

3.3

mA

-0.18

mA
mA

DM54

-3

-15

DM74

-3

-15

Switching Characteristics at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL=4 kG
Parameter

units

CL=50 pF

Conditions

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

45

90

ns

tpHL Propagation Delay Time
High to Low Level Output

45

90

ns

Min

Nole 1: All typicals are at Vee=SV, TA=2S'e.
Nole 2: Not more than one output should be shorted at a time.

7·16

c

s:
en

~National

-'="
r.....
o

~ Semiconductor

C

s:

:j;;!
r.....
o

DM54L 10/DM74L10 Triple 3-lnput NAND Gates
General Description

Absolute Maximum Ratings

This device contains three independent gates eac'h of
which performs the logic NAND function.

Supply Voltage
Input Voltage

(Note 1)
8V

5.5V
-65·C to 150·C

Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual·ln·Line Package

'i:

1l

I"

Cl
11

2

B1

,

.,

"10

Afg

v,

Y=ABC

B

~

J

1

.,

VI

CI

14

4

B2

cts

Inputs

~
6
J2

Output

A

B

C

Y

X
X

X

L

L

L
H

X

X
X

H

H

H
H
H
L

H = Iotigh Logic Level
L = Low logic Level

J:

X = Either Low or High Logic Level

TLlFJ6619-1

DM54L10 (J), DM74L10(N)

7·17

....o

-I

~

Recommended Operating Conditions

::E

-....

Symbol

-I

oo:t

Vee

Supply Voltage

In

::E

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

o

DM74L10

DM54L10

c

c

TA

Parameter

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

V
V
V

0.7

0.7

' -0.2

-0.2

mA

3.6

mA

70

·C

-55

Free Air 'Operating
Temperature

Units

2

2

Electrical Characteristics
Symbol

Min

125

0

over recommended operating free air t.emperature (unless otherwise noted)

Parameter

Conditions

VOH

High Level Output
Voltage

Vec=Min,loH=Max
VIL=Max

VOL

Low Level Output
Voltage

Vcc= Min
10L=Max
VIH=Min

II

Input' Current@Max
Input Voltage

IIH

Min

Typ
(Note 1)

2.4

3.3

Max

Units
..

V

DM54

0.15

0.3

DM74

0.2

0.4

V

Vcc=Max, VI=5.5V

0.1

'mA

High Level Input
Current

Vcc=Max, VI = 2.4V

10

p.A

IlL

Low Level Input
Current

Vcc=Max, VI=0.3V

los

Short Circuit
Output Current

' Vcc=Max
(Note 2)

-0.18

mA
mA

DM54

-3

-15

DM74

-3

-15

ICCH

Supply Current With
Outputs High

Vcc=Max

0.33

0.6

mA

Icc~

Supply Current With
Outputs Low

Vcc- Max

0.87

1.53

mA

!

SWitching Characteristics

at Vcc = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
RL=4kD

Parameter

Units

C L =50 pF

Conditions

Typ

Max

tpLH Propagation Delay rime
Low to High Level Output

35

60

ns

tpHL Propagation Delay Time
High to Low Level Output

31

60

ns

Min

Nole 1: Alltyplcals are at VCC=5V, TA=25"C.
Nole 2: Not more than one output should be shorted at a time.

7-18

.------------------------------------------------------------------,0
:s:
en

~National

.1:00

~ Semiconductor

r.....

-:s:
.....
o

~
r.....

DM54L 11/DM74L11 Triple 3·lnput AN D Gates

.....

General Description

Absolute Maximum Ratings

This device contains three independent gates each of
which performs the logic AND function.

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

BV
5.5V

- 65'C to 150'C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the

"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual·ln-Line Package

T"

C1

OJ

13

Y
12

11

JJ
I

AI

1
B\

J

. A1

"

10

Vl
AI',

Y=ABC

8

lb4
81

5
}2

Inputs

~
6
)2

Output

A

B

C

Y

X
X
L
H

X
L
X
H

L
X
X
H

L
L
L
H

H = High Logic Level

,J:

L = Low Logic Level
X = Either Low or High Logic Level

TLlFJ6620-1

DM54L11 (J) . DM74L11 (N)

7-19

,..
,..
...J

Recommended Operating Conditions

i!
:E
c

Sym

Parameter

...J

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

,,....

~
:E

DM74L11

DM54L11

c

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

~V

0.7

0.7

-0.2

-0.2

mA

3.6

mA

70

·C

2
-55

Parameter

Units

V

2

2

Electrical Characteristics
Sym

Min

0

125

V

over recommended operating free air temperature (unless otherwise noted)
Conditions

VI

Input Clamp Voltage

Vee = Min, 11= -12 mA

VOH

High Levei Output
Voltage

Vee=Min,IOH=Max
VIH=Min

VOL

Low Level Output
Voltage

Vee=Min
IOL=Max
VIL=Max

Min

Typ
(Note 1)

2.4

3.3

Max
-1.5

Units
V
V

DM54

0.15

0.3

DM74

0.2

0.4

V

"

II

Input Current@Max
Input Voltage

Vee = Max, VI = 5.5V

0.1

mA

IIH

High Level Input
Current

Vee = Max, VI = 2.4V

10

,.A

IlL

Low Level Input
Current

Vee=Max, VI =·0.3V

Short Circuit
Output Current

Vee = Max
(Note 2)

IceH

Supply Current With
Outputs High

Vcc=Max

' 1.0

1.5

mA

ICCL

Supply Current With
Outputs Low

Vcc=Max

1.6

2.2

mA

los

-0.18

mA
mA

,

Sw~tching Characteristics

DM54

'-3

-15

DM74

-3

-15

al Vcc=5V and TA=25·C (See Section 1 for Test Waveforms and Output Load)
RL=4 kll

Parameter

Conditions

CL=50 pF
Min

Units

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

40

80

ns

tpHL Propagation Delay Time
High to Low Level O'utput

45

90

ns

=

=

Notl 1: All typical. are at Vec 5V. TA 25'e.
Note 2: Not more than one output should be shorted at a time.

7·20

.------------------------------------------------------------------,0

:s:
U1

~National

.j::o

~ Semiconductor

ro

I\)

o

:s:
~
r~

DM54L20/DM74L20 Dual 4·lnput NAND Gates
General Description

Absolute Maximum Ratings

This device contains two .independent gates each of
which performs the logic NAND function.

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

BV
5.5V
- 65°C to 150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device' can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual·ln·Line Package

I

D2
14

•

••

"

C2

"

"1'.

"

,

1

Jc

"

10

C1

Y=ABCD

8

h
,

J

"

V2

Tg

D1

Output

Inputs

~

H

X J:

L

A

B

C

D

Y

X
X
XL
H

X
X
L
X
H

X
L
X
X
H

L
X
X
X
H

H
H
H
H
L

=High Logic Level
=Low Logic Level

' X = Either Low or High Logic Level
TUFJ6621·1

DM54L20 (J)

DM74L20 (N)

,

7·21

Recommended Operating Conditions
,Sym

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level Input
Voltage

10H

High Level Output
Current

10l

Low Level Output
Current

TA

Free Air Operating
Temperature

DM54L20

DM74L20

Min

Nom

Max

Min

Nom

4.5

5

5.5

4.75

5

5.25 '

Units
V
V

2

2 .
0.7

0.7

-0.2

-0.2

mA

3.6

mA

70

DC

2
-55

Electrical Characteristics

Max

125

0

V

over recommended operating free air temperature (unless otherwise noted)

Sym

Parameter

VOH

High, Level Output
Voltage

Vee=Min,loH=Max
Vll=Max

VOL

Low Level Output
Voltage

Vee=Min
IOl= Max
VIH= Min

II

Input Current@Max
Input Voltage

IIH

Conditions

Min

Typ
(Note 1)

2.4

3.3

Max

Units
V

DM54

0.15

'0.3

DM74

0.2

0.4

V

Vee = Max, VI = 5.5V

0.1

mA

High Level Input
Current

Vee = Max, VI = 2.4V

10

/LA

IlL

Low Level Input
Current

Vee = Max, VI = 0.3V

los

Short Circuit
Output Current

Vcc=Max
(Note 2)

IccH

Supply Current With
Outputs High

Vcc= Max

I CCl '

Supply Current With
Outputs Low

Vcc=Max

Switching Characteristics

-0.18

mA
mA

DM54

-3

-15

DM74

-3

-15

,

0.22

0.4

mA

0.58

1.02

mA

at Vcc = 5V and TA = 25 DC (See Section 1 for Test Waveforms and Output Load)
Rl=4 kO

Parameter

C l =50 pF

Conditions
Min

Units

Typ

Max

tplH Propagation D'elay Time
Low to High Level Output

35

60

ns

tpHl Propagation Delay Time
High to Low Level Output

31

60

ns

Notal: Alltyplcals are at VCC=5V. TA=25'C,
Nota 2: Not more than ana output should be shorted at a tlma.

7·22

~National

~ Semiconductor
DM54L26/DM74L26 Quad 2-lnput NAND Gates
with High Voltage Open-Collector Outputs
General Description

Absolute Maximum Ratings

This device contains four independent gates each of
which performs the logic NAND function. The opencollector outputs require external pull-up resistors for
proper logical operation.

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

(Note 1)
8V

5.5V
15V

-65'C to 150'C

Pull-Up Resistor Equations
R

MAX

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

Vo (Min) - VOH

= N, (IOH) + N2 (lIH)

not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" lable are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Where:

N, (lOH) = total maximum output high current
for all outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for
all inputs tied to pull-up resistor
N3 (110 total maximum input low current for
all inputs tied to pull·up resistor

=

Connection Diagram

Function Table

Dual·ln·Line Package

V=AB
Inputs
B

V

L
L
H
H

L
H
L
H

H
H
H
L

H = High Logic Level
L = Low Logic Level

DM54L26 (J)

DM74S26 (N) .

7-23

Output

A

•

Recommended Operating Conditions
DM54L26

Symbol

Parameter

DM74L26

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low L!!vel Input
Voltage

0.7

0.7

V

VOH

High Level Output
Voltage

15

15

V

10L

Low Level Output
Current

2

3.6

mA

TA

Free Air Operating
Temperature

70

·C

2

2

-55

Electrical Characteristics

125

V
V

0

over recommended operating free air temperature (unless otherwise noted)

,
Symbol

Parameter

Conditions

Typ
(Note 1)

Min

ICEX

High Level Output
Current

Vee=Min, Vo=12V
VIL = Max

VOL

Low Level Output
Voltage

Vee=Min
10L= Max
VIH = Min

II

Input Current@Max
Input Voltage

IIH

Max

Units

~OO

'p.A

DM54

0.15

0.3

DM74

0.2

0.4

V

Vee = Max, VI = 5.5V

0.1

mA

High Level Input
Current

Vee = Max, VI = 2.4V

10

p.A

IlL

Low Level Input
Current

Vee = Max, VI = 0.3V

leeH

Supply Current With
Outputs High

Vee=Max

leeL

Supply Current With
Outputs Low

Vee = Max

Switching Characteristics

-0.18

mA

0.48

0.8

mA

1.32

2.04

mA

at Vee=5V and TA=25·C (See Section 1 for Test Waveforms and Output Load)
RL=4 kll

Parameter

Conditions

CL=15pF
Min

Units

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

40

90

ns

tpHL Propagation Delay Time
High to Low Level Output

25

60

ns

Note 1:

All typicals are at Vee = 5V, TA = 25'e.

7·24

r------------------------------------------------------------------.c

3:
~

.
~ Semiconductor
~National

rw

o
c
3:
~
r-

DM54L30/DM74L30 a-Input NAND Gate

~

General Description

Absolute Maximum Ratings

This device contains a single gate which performs the
logic NAND function.

Supply Voltage
Input Voltage
Storage Temperature Range

(Note-1)_
8V

5.5V
- 65·Cto 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended" Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual·ln-Line Package

V.'

114

Nt

113

Y=ABCDEFGH

"

11

Inputs

Output

A thru H

Y

All inputs H

l

One or More
Input l

H

H = High Logic Level
L = Low Lagle Level

TUF/SS23-1

DM54L30 (J)

DM74L30 (N)

7-25

•

Recommended Operating Conditions
Sym

DM54L30

Parameter

Vee

Supply Voltage

V'H

High Level Input
Voltage

V'L

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Le1(el Output
Current

TA

Free Air Operating
Temperature

. Parameter

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Unl,s
V

2

V

0.7

0.7

-0.2

-0.2

mA

3.6

mA

70

·C

2
-55

Electrical Characteristics
Sym

DM74L30

Min

125

0

V

over recommended operating free air temperature (unless otherwise noted)
Conditions

VOH

High Level Output
Voltage

Vee = Min, 10H=Max
V'L= Max

VOL

Low Level Output
Voltage

Vee = Min
10L=Max
V'H= Min

I,

Input Current@Max
Input Voltage

I'H

Min

Typ,
(Note 1)

2.4

3.3

Max

Units
V

DM54

0.15

0.3

DM74

0.2

0.4

V

Vee= Max, V, =5.5V

0.1

mA

High Level Input
Current

Vee=Max, V,=2.4V

10

p.A

I'L

Low Level Input
.Current

Vee=Max, V,=0.3V

los

Short Circuit
Output Current

Vee=Max
(Note 2)

leeH

Supply Current With
Outputs High

Vee = Max

0.11

0.2

mA

leeL

Supply Current With
Outputs Low

Vee = Max

0.29

0.51

mA

-0.18

mA
mA

DM54

-3

-15

DM74

-3

-15

Switching Characteristics at Vee == 5V and TA = 25·C

(See Section 1 for Test Waveforms and Output Load)
RL=4 kll

Parameter

Conditions

Units

CL=50 pF
Min

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

35

60

ns

tpHL Propagation Delay Time
High to Low Level Output

70

100

ns

.

Nola 1: All typlcals are at Vee=5V, TA=25'e.
Note 2: Not more than one output should be shorted at a time.

7·26

~National

~. Semiconductor
DM54L42A/DM74L42A BCD/Decimal Decoders
General Description
• Typical power dissipation 15 mW

These BCD-to-decimal decoders consist of eight inverters
and ten, four-input NAND gates. The inverters are connacted in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of input logic ensures
that all outputs remein off for all invalid (10-15) input
conditions.

• Typical propagation delay 53 ns

Absolute Maximum Ratings
Supply Voltage

BV

Input Voltage
Storage Temperature Range

Features

(Note 1)

5.5V
-65·Cto150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limils. The parametric values defined In the

• Diode clamped inputs
• Also for application as 4-line-to-16'line decoders; 3-lineto-8-line decoders

"Electrical Characteristics" table arB not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will

• All outputs are high for invalid input conditions

define the conditions for actual device operation.

Connection Diagram

Logic Diagram

Dual-In-Line Package
INPUTS

Vcc
J16

A
15

OUTPUTS

c

B

1.

9

D

13

1.

11

9

10

r<

1

o

0-

•

•

3

5

I

7

6

B

GND

OUTPUTS

54L42A(J)

TLlF/6624·1

74L42A(N)

Function Table
L.2A
BCD Inpu'

No.
0
1
2

3
4

5
8

7
8

9

51

-'

~
;;;

TL/F/6624·2

Decimal Output

0

C

a

A

0

1

2

3·

4

5

6

7

B

9

L
L
L
L
L

L
L
L
L
H

L
L
H
H
L

L
H
L
H
L

L
H
H
H
H

H
L
H
H
H

H
H
L
H
H

H
H
H
L
H

H
H
H
H
L

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

L
L
L
H
H

H
H
H
L
L

L
H
H
L
L

H
L
H
L
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

L
H
H
H
H

H
L
H
H
H

H
H
L
H
H

H
H
H
L
H

H
H
H
H
L

H L
H L
H .H
H H
H H
H H

H
H
L
L
H
H

L
H
L
H
L
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H "" High Level
L = Low Level

7-27

Recommended Operating Conditions
DM54L42A
Sym

DM74L42A

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

V
V

0.7

0.7

-0.2

-0.2

mA

3.6

mA

70

'C

2
-55

Electrical Characteristics

Units

125

0

V

over recommended operating free air temperature (unless otherwise noted)

Sym

Parameter

VO H

High Level Output
Voltage

Vee = Min, 10H = Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee=Min
10L = Max
VIL= Max
VIH = Min

II

Input Current@Max
Input Voltage

IIH

Conditions

Min

Typ
(Note 1)

2.4

3.4

Max

Units
V

DM54

0.15

0.3

DM74

0.2

0.4

V

Vee = Max, VI = 5.5V

0.1

mA

High Level Input
Current

Vee=Max, V I =2.4V

10

I'A

IlL

Low Level Input
Current

Vee=Max, V I =0.3V

los

Short Circuit
Output Current

Vee= Max
(Note 2)

Supply Current

Vee=Max
(Note 3)

Icc

Note t:

-0.18

mA
mA

DM54

-3

-15

DM74

-3

-15
3.0

All typicals are at Vee=5V, TA = 25°C.

Note 2: Not more than one output should be shorted at a time.
Note 3: ICC is measured with all outputs open and all inputs grounded.

7·28

5.3

mA

Switching Characteristics
Parameter

at Vee = 5V and TA = 25~C (See Section 1 for Test Waveforms and Output Load)
From
(Input)
To
(Output)

RL=4 k{l
CL=50 pF
Min

Units

Typ

Max

t PHL Propagation Delay
Time High to Low
Level Output

A, B, Cor D
through
2 Levels of Logic

65

130

ns

tpHL Propagation Delay
Time High to Low
Level Output

A, B, Cor D
through
3 Levels of Logic

70

140

ns

tpLH Propagation Delay
Time Low to High
Level Output

A, B, Cor D
through
2 Levels of Logic

30

60

ns

tpLH Propagation Delay
Time Low to High
Level Output

A, B, Cor D
through
3 Levels of Logic

35

70

ns

.

r

.

7-29

,

~
IJ')

r------------------------------------------------------------------------------------,

~ ~National

~ ~ Semiconductor

~

IJ')

~ DM54L51/DM74L51 Dual 2~Wide 2-lnput,
~

2-Wide 3-lnput AND-OR-INVERT Gates
General Description

Absolute Maximum Ratings

This device contains two combinations of gates each of
which performs the logic AND-OR-INVERT function.

Supply Voltage

(Note 1)

8V
S.SV
-6S·Cto1S0·C

Input Voltage
Storage Temperature Range

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will

define the conditions for actual device operation.

Function Table

Connection Diagram

Dual-In-Line Package

= [(A1XB1)(Cl)] + [(CD1XE1XF1)]

Yl

Inputs

Output

A1

81

C1

01

E1

F1

Y1

H

H

H

X

X

X

X

X

X

H

H

H

L
L

H

Other Combinations

AI

A2

BZ

C2

D2

V2

GND

Y2 - [(A2XB2)] + [(C2X02»)

TLlF/6625·1

OM54L51 (J)

Inputs

OM74LS1 (N)

Output

C2

02

Y2

H

13 2
H

X

X

X

X

H

H

L
L

A2

All other combinations

=

H High Log Ic Level
L'; Low Logic Level
X = Either Low or High Logic Level

7-30

H

o

I

s:

Recommended Operating Conditions
Symbol

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

r-

DM74L51

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units

o

V
V

2
0.7

0.7

-0.2

-0.2

mA

3.6

rnA

70

·C

2
-55

Parameter

125

0

V

over recommended operating free air temperature (unless otherwise noted)
Conditions

VOH

High Level Output
Voltage

Vee = Min, IOH = Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee=Min
10L= Max
VIH = Min

II

Input Current@Max
Input Voltage

IIH

Min

Typ
(Note 1)

2.4

3.3

Max

Units

V

DM54

0.15

0.3

DM74

0.2

0.4

V

Vee = Max, VI = 5.5V

0.1

mA

High Level Input
Current

Vee=Max, VI =2.4V

10

p.A.

IlL

Low Level Input
Current

Vcc.= Max, VI = 0.3V

los

Short Circuit
Output Current

Vcc= Max
(Note 2)

ICCH

Supply Current With
Outputs High

Vce=Max

0.44

0.8

mA

lecL

Supply Current With'
Outputs Low

Vce=Max

0.76

1.3

mA

Switching Characteristics

-0.18

mA
mA

DM54

-3

-15

DM74

-3

-15

at Vcc = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
RL =4k!J
C L =50 pF

Co~ditions

Parameter

-....
C11

s:

~
r-

....

C11

Electrical Characteristics
Symbol

~

DM54L51

Min

Units

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

50

90

ns

tpHL Propagation Delay Time
High to Low Level Output

35

60

ns

.

Nol.l: Aillypicals are at vec=Sv. TA=2S'C.
Note 2: Not more than one output should be shorted at a time.

7·31

~

~ ~ National

.
~ ~ Semiconductor

-=t

Ll)

....I

~ DM54L54/DM74L54 4·Wide AND~OR·INVERT Gates

c

General Description

Absolute Maximum Ratings

This device contains a combination of gates which performs the logic AND-OR-INVERT function.

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

8V
5.5V
-65·Ct0150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual-In-Line Package
VIC

114

13

112

to

H'1

Y=AB +CDE+ FGH + IJ

'i9

Inputs

I

Output

A

B

C

D

E

F

G

H

I

J

Y

H

H

X

X

X

X
X
X

X
X
X

H

H

H

X
X

X
X

X
X

X
X

X
X

X
X

H

H

H

X
X
X

X
X
X

X

X

X

H

H

L
L
L
L
H

All other combinations

['
D

H = High Logrc Level
L = Low Logic Level

!'
E

X =' Either Low or High Logic Level

TL/F/6626·1

DM54L54 (J)

DM74L54 (N)

7-32

c

s::

Recommended Operating Conditions
Sym

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units

0.7

0.7

-0.2

-0.2

rnA

3.6

mA

70

·C

-55

125

0

V

over recommended operating free air temperature (unless otherwise noted)

Sym

Parameter

VOH

High Level Output
Voltage

Vcc=Min,IOH=Max
V IL = Max, V IH = Min

VOL

Low Level Output
Voltage

Vcc= Min
10L=Max
VIH=Min

II

Input Current@Max
Input Voltage

IIH

Conditions

Min

Typ
(Note 1)

2.4

3.3

Max

Units
V

DM54

0.15

0.3

DM74

0,2

0.4

V

Vcc = Max, VI = 5.5V

0.1

mA

High Level Input
Current

Vcc = Max, VI = 2.4V

.10

p.A

IlL

Low Level Input
Current

Vcc = Max, VI = 0.3V

los

Short Circuit
Output Current

Vcc=Max
(Note 2)

ICCH

Supply Current With
Outputs High

Vcc= Max

.0.39

0.8

mA

ICCL

Supply Current With
Outputs Low

Vcc=Max

0.6

0.99

rnA

Note 1:

DM54.

-3

DM74

-3

-0.18

mA

-15

rnA

-15

All typicals are at VCC = 5V. TA = 25'C.

Note 2: Not more than one output should be shorted at a time.

Switching Char~cteristics

at Vcc = 5V and TA = 25·C(See Section 1 for Test Waveforms and Output Load)
RL=4 kG

. Parameter

CL =50 pF

Conditions
Min

Units

Typ

Max

tpLH Propagation Delay Time
Low to High Level Output

50

90

ns

tpHL Propagation Delay Time
High to Low Level Output

35

60

ns

I

7-33

-s::
en

.j:Io

C

V
V

2

2

Electrical Char~cteristics

r-

DM74L54

DM54L54

Parameter

Vcc

en
.j:Io

~
ren
.j:Io

!!i~
!i

-

~National

~ Semiconductor

I I)
II)

...I

~

:E
c

DM54L55/DM74L55 2·Wide, 4 Input AND·OR·INVERT Gates

General Description

Absolute Maximum Ratings

This device contains a combination of gates which perform the logic ANO-OR-INVERT function.

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

BV
5.5V·
-65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the co~dltions for actual device operation.

Connection Diagram

Function Table

Dual-In-Line Package

T
14

1
A

H

13

G

V

f
11

12

10

Nf9

Y

B

~
2

B

4

J

C

0

Nr

=AeCo + EFGH
Output

Inputs

A

B

C

D

E

F

G

H

H
X

H
X

H
X

H
X

X
H

X
H

X
H

X
H

All other combinations

Y
L

L
H

=
=

H High Logic Level
L Low Logic Level
X = Either Low or High Logic Level

J: J:
TLfF16627-'

DM54L55 (J)

DM74L55 (N) .

.

7-34

Recommended Operating Conditions
Sym

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

Vil

Low Level Input
Voltage

IOH

High Level Output
Current

10l

Low Level Output
Current

TA

Free Air Operating
Temperature

DM54L55

DM74L55

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V
V

2

2

Units

0.7

0.7

-0.2

-0.2

mA

3.6

mA

70

·C

2
-55

125

0

V

,

Electrical Characteristics
Sym

I

Parameter

over recommended operating free air temperature (unless otherwise noted)
Conditions

VOH.

High Level Output
Voltage

Vee = Min, 10H = Max
Vil = Max, VIH = Min

Val.

Low Level Output
Voltage

Vee=Min
10l=Max
VIH=Min

II

Input Current@Max
Input Voltage

IIH

Min

Typ
(Note 1)

2.4

3.3

Max

Units
V

DM54

0.15

0.3

DM74

0.2

0.4

V

Vee = Max, VI = 5.5V

0.1

mA

High Level Input
Current

Vee=Max, VI=2.4V

10

/lA

Ill·

Low Level In.put
Current

Vee = Max, VI = 0.3V

los.

Short Circuit
Output Current

Vee=Max
(Note 2)

leeH

Supply Current With
Outputs High

Vee=Max

0.22

0.4

mA

leel

Supply Current With
Outputs Low

Vee=Max

0.38

0.65

mA

-0.18

mA
mA

DM54

-3

-15

DM74

-3

-15

Note 1: All typicals are at VCC=5V, TA=25·C.
Note 2: Not more than one output should be shorted at a time.

Switching Characteristics

at Vcc=5V and TA =25·C (See Section 1 for Test Waveforms and Output Load)
RL = 4 kn

Parameter

Conditions

C l =50 pF
Min

Units

Typ

Max

tplH Propagation Delay Time
Low to High Level Output

50

90

ns

tpHl Propagation Delay Time
High ,to Low Level Output

35

60

ns

-.

7-35

~ r-----------------------------------------------------------------------------------~

~ ~National
.~ ~ Semiconductor

-.....
~

~ DM54L71/DM74L71 AND-Gated Master-Slave
~ R-S Flip-Flop with Preset, Clear
and Complementary Outputs
General Description

Absolute Maximum Ratings

This device contains a positive pulse triggered masterslave R-S flip-flop with complementary outputs. Multiple Rand S inputs are ANDed together to produce the
internal Rand S functions for the flip-flop. The Rand S
data is processed by the flip-flop after a complete clock
pulse. While the clock is low the slave is isolated from
the master. On the positive'going transition of the clock,
the data f~om the AND gates is transferred to the
master. While the clock is high the AND gate inputs are
disabled. On the negative transition of the clock the
data is transferred from the master to·the slave. The R
and S inputs must be held constant while the clock is
high. Data is. transferred to the output on the falling
edge of the clock pulse. A low level on the preset or
clear inputs will set or reset the outputs regardless of
the logic levels of the other inputs.

Supply Voltage
Input Voltage
Storage Temperature Range

Connection Diagram

V,
114

(Note 1)

8V
5.5V
-65·Cto150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table arB not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Dual-In-Line Pa.ckage
PR

eLK

13

RJ

12

11

~

Inputs

~~

rE?~
I r

·r

X cl:

4

J

S1

S2

5
J3

I-

I' G!:
Q

Output,s

PR

CLR

CLK

5(1)

R(l)

L
H
L
H
H
H
H

H
L
L
H
H
H
H

X
X
X

X
X
X

J"L'

L
H
L
H

J"L
J"L
J"L

Q

Q

X
X
X

H
L
H*

L
H
H*

L
L
H
H

00

00

H
L
L
H
Indeterminate

TLlF/6628-1

Nole 1: S = (51)(52)(53), R = (R1)(R2)(R3)

DM54L71 (J)

DM74L71 (N)

H = High Logic Level

x = Low or High

Logic Level

L = Low Logic Level
I L = Positive pulse. The Rand S Inputs must be held constant while the
clock is high. Data is transferred to the output on the falling edge of the
clock pulse.

00 = The level of Q before the indicated input conditions were
established.
* =This configuration is nonstable; that is, it will not persist when the

preset andlor clear inputs returned to their Inactive (high) level.

7·36

Recommended Operating Conditions
Parameter

Sym

Vcc,

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level
Input Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current ,

fCLK

Clock Frequency

tw

Pulse Width

DM54L71

DM74L71

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

V
V

Clock

0.6

0.6

Others

0.7

0.7

-0.2

-0.2

mA

3.6

mA

6

MHz

2
0

6

0

Clock
High

100

100

Clock
Low

100

100

Preset
Low,

100

100

Clear
Low

100

100

tsu

Input Setup Time (Note 1)

01

01

tH

Input Hold Time (Note 1)

01

01

TA

Free Air Operating
Temperature

Note 1: The symbols (I,

Units

-55

125

I) indicate the edge of the clock pulse used forreference: I

for rising edge,

0

I

for falling edge.

;

,

7·37

V

ns

ns
ns

70

·C

Electrical Characteristics

over recommended operating free air temperature (unless otherwise noted)

Sym

Parameter

VOH

High Level Output
Voltage

Vcc=Min,loH=Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vcc=Min
IOL='Max
VIL = Max
VIH=Min

Input Current@Max
Input Voltage

Vce= Max
VI =5.5V

II

IIH

Conditions

High Level Input
Current

Vcc=Max
VI =2.4V

Min

Typ
(Note 1)

2.4

3.3

Max

V

DM54

0.15

0.3

DM74

0.2

0.4

V

mA

R,S

100

Clear

200

Preset

200

Clock

200

R,S

10

Clear

20

Preset

Low Level Input
Current

Vcc=Max
VI =0.3V

.
los

Icc

Short Circuit
Output Current

Vee=Max

Supply Current

Vee = Max
(Note 2)

-200

R,S

-0.18

Clear

-0.36

Preset

-0.36

mA

-0.36

Clock
DM54

-3

-15

DM74

-3

-15
0.76

Nole 1: All typical. are at Vee = 5V. TA = 25"e.

I'A

20

Clock
IlL

Units

1.44

mA

mA

.

Note 2: With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the tim"e of measurement, the clock input is grounded .

SWitching Characteristics
Parameter

at Vee = 5V and TA = 25"C (See Section 1 for Test Waveforms and Output Load)

From
(Input)
To
(Output)

'MAX Maximum
Clock Frequency

RL=4 kG
C L =50 pF
Min

Typ

6

11

Units
Max
MHz
' 75

tpLH Propagation Delay
Time Low to High
Level Output

Preset
to
a

35

tpHL Propagation Delay
Time High to Low
Level Output

Preset
to

60

150

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clear
to

35

75

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
a

60

150

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
aorO

10

35

75

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
aoro

10

60

150

ns

ns

a

a

7·38

c

:s:

~National

~
r-

~ Semiconductor

.......

-:s:
N

C

DM54L721.DM74L72 AND·Gated Master·Slave
J·K Flip·Flop with Preset, Clear
and Complementary Outputs

~
r.......
N

General Description

Absolute Maximum Ratings

This device contains a positive pulse triggered masterslave J-K flip-flop with complementary outputs_ Multiple
J and K inputs are ANDed together to produce the internal J and K function for the flip-flop_ The J and K data is
processed by the flip-flop after a complete clock pulse.
While the clock is low the slave is isolated from the
master. On the positive transition of the clock, the data
from the AND gates is transferred to the master. While
the clock is high the AIiID gate inputs are disabled. On
the negative transition of the clock the data from the
master is transferred to the slave. The logic state of the
J and K inputs must not be allowed to change while the
clock is in the high state. Data is transferred to the outputs on the falling edge of the clock pulse. A low logic
level on the preset or clear inputs sets 'or resets the outputs regardless of the logic levels of the other inputs.

Supply Voltage
Input Voltage
Storage Temperature Range

Connection Diagram
ClK

KJ

8V

5.5V
- 65·C to 150·C

Note 2: The "Absolute Maximum Ratings" are those values beyond

which the safety of the device can nol be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Dual-In-Line Package
PR

(Note 1)

K2

Inputs
K1

J

PR

ClR

ClK

l
H
L
H
H
H
H

H
L
l
H
H
H
H

X
X
X

X
X
X

J"L

L
H
L
H

.,

J"L
J"L
J"L

(Note 1)

Outputs
K
Q
Q
(Note 1)
X
H
l
X
L
H
H* H*
X
l
00 00
H
l
l
H
L
H
H
. Toggle

Note 1: J = (J1)(J2)(J3), K = (Kl)(K2)(K3)
NC

J2

JJ

GNO

TLlF/6629·1

DM54l72 (J)

DM74l72 (N)

H = High Logic. Level

X = Either Low or High Logic Level
L = Low Logic Level

= Positive pulse. TheJ and K inputs must be held constant while the
clock is high. Data is transferred to the outputs on the falling edge of the
clock pulse.
.

J""'L

00::; The output logic level before the indicated input conditions were
established .
• ::; This configuration is nonstable; that is, it will not persist when the
preset and/or clear inputs return to their inactive (high) level.
Toggle::; Each output changes to the complement of its previous level on
each complete high level clock pulse.

7·39

Recommended Operating Conditions
Parameter

Sym
Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level
Input Voltage

IOH

High Level 'Output
Current

IOL

Low Level Output
Current

fCLK

Clock Frequency

tw

Pulse Width

DM54L72

DM74L72

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

V
V

Clock

0.6

0.6

Others

0.7

0.7

-0.2

-0.2

mA

3.6

mA

6

MHz

2
0

6

0

Clock
High

100

100

Clock
Low

100

100

Preset
Low

100

100

Clear
Low

100

100

tsu

Input Setup Time (Note 1)

01

ot

tH

Input Hold Time (Note 1)

01

01

TA

Free Air Operating
Temperature

Note 1: The symbols

Units

-55

125

0

(1, I) indicate the edge.of the clock pulse used for reference: 1 for rising edge, I for failing edge,

",

7·40

V

ns

ns
ns
70

DC

Electrical Characteristics
Sym

over recommended operating free air temperature (unless otherwise noted)

Parameter

Conditions

Min

Typ
(Note 1)

2.4

3.3

Max

Units

VOH

High Level Output
Voltage

Vee = Min, 10H = Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee = Min
10L=Max
VIL=Max
V IH = Min

DM54

0.15

0.3

DM74

0.2

0.4

V

Input Current@Max
Input Voltage

Vee=Max
VI = 5.5V

J, K

100

mA

Clear

200

Preset

200

Clock

200

II

High Level Input
Current

IIH

Low Level Input
Current

IlL

Vcc=Max
VI =2.4V

Vee=Max
V I =0.3V

J, K

10

Clear

20'

Preset

20

Clock

-200

J, K

-0.18

Clear

-0.36

Preset

-0.36

los

Icc

Vee = Max

Supply Current

Vee=Max
(Note 2)

All typical. are at Vec=SV, TA=2S"C.
2: With all outputs open, ICC is measured with the

Note 1:
Note

Switching Characteristics
Parameter

Q

and

I"A

mA

-0.36

Clock
Short Circuit
Output Current

V

DM54

-3

-15

DM74

-3

-15
0.76

mA

mA

1.44

a outputs high in turn. At the time of measurement the clock input is grounded.

at Vcc = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)

From
(Input)
To
(Output)

fMAX Maximum
Clock Frequency

RL=4 kO
C L =50 pF
Min

Typ

6

11

Units
Max
MHz

. tpLH Propagation Delay
Time Low to High
Level Output

Preset
to
a

35

75

ns

tpHL Propagation Delay
Time High to Low
Level Output

Preset
to

60

150

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clear
to

35

75

ns

tpHL Propagation Delay
Time High to Low
Leve lOut p ut

Clear
to
a

60

150

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
aorO

10

35

75

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
aorO

10

60

150

ns

Q

Q

7·41

(
~r-----------------------------~-----------------------------------------'

~ ~National

~ ~ Semiconductor
~

~ DM54L73/DM74L73 Dual Master-Slave J-K Flip-Flops
~ with Clear and Complementary Outputs
.
General Description

Absolute Maximu'm Ratings

This device contains two independent positive pulse
triggered J-K flip-flops with complementary outputs.
The J and K data is processed by the flip-flops after a
complete clock pulse. While the clock is low the slave is
isola~ed from the master. On the positive transition of
the clock, the data from the J and K inputs Is transferred to
the master. While the clock is high, the data from theJ and
K inputs are disabled. On the negative transition of the
clock, the data from the master is transferred to the slave.
The logic states of the J and K inputs must not be allowed
to change while the clock is high. Data is transferred to the
outputs on the falling edge of the clock pulse. A low logic
level on the clear input will reset the outputs regardless of
the logic states of the other Inputs.

Supply Voltage
Input Voltage
Storage Temperature Range

Connection Diagram

(Note 1)

8V
5.5V

- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of Ihe device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Dual-in-Line Package
J1

ii.

D.

GND

.2

Q2

.2
Inputs
ClR
l
H
H
H
H

Outputs
Q

Q

ClK

J

K

X

X

X

l

H

J"L

l
H
l
H

l
l
H
H

00

00

H
L

L
H

J"L
J"L
J"L

Toggle

H = High Logic Level
elK I

CLRt

••

ClK2

CLR2

J2

TLfF/6630·1

DM54l73 (J)

DM74l73 (N)

X = Either Low or High Logic Level
L = Low Logic Level
....n... = Positive pulse data. The J and K inputs must be held constant while
the clock is high. Data Is transferred to the outputs on the falling edge of
the clock pulse.
00 = The output logic level before the Indicated Input conditions were
established.
Toggle = Each output changes to the complement of Its previous level
on each complete high level clock pulse.

7-42

Recommended Operating Conditions
DM54L73
Sym

Parameter

Vcc

Supply Voltage

V IH

High Level Input
Voltage

Vil

Low Level
Input Voltage

IOH

High Level Output
Current

IOl

Low Level Output
Current

fClK

Clock Frequency

tw

Pulse Width

DM74L73

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25·

V
V

2

2

Units

Clock

0.6

0.6

Others

0.7

0.7

-0.2

-0.2

rnA

3.6

rnA

6

MHz

2
0

6

0

Clock
High

100

100

Clock
Low

100

100

Clear
Low

100

100

01

01

tsu

Input Setup Time (Note 1)

tH

Input Hold Time (Note 1)

TA

Free Air Operating
Temperature

01

ns

ns
ns

01

-55

125

0

Note t: The symbols (1, I) Indicate Ihe edge of the clock pulse used for reference: 1 for rising edge, I for falling edge .

.

, .

7·43

V

70

·C

Electrical Characteristics

over recommended operating free air temperature (unless otherwise noted)

Conditions

Min

Typ
(Note 1)

2.4

3.3

Max

Sym

Parameter

VOH

High Level Output
Voltage

Vee = Min, 10H = Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee=Min
10L=Max
VIL=Max
VIH=Min

DM54

0.15

0.3

DM74

0.2

0.4

V

Input Current@Max
Input Voltage

Vee = Max
VI = 5.5V

J, K

100

mA

Clear

200

Clock

200

High Level Input
Current

Vee = Max
VI =2.4V

J, K

10

Cle .. r

20

Clock

-200

Low Level Input
Current

Vee=Max
VI =0.4V

J, K

-0.18

Clear

-0.36

Short Circuit
Output Current

Vee = Max

Supply Current

Vee = Max
(Note 2)

II

IIH

IlL

V

Icc

p.A

mA

-0.36

Clock
los

Units

DM54

-3

-15

DM74

-3

-15
1.5

2.88

mA

mA

Nole 1: Ali typical. are at vee=SV. TA=2S'e.
Note 2: With all outputs open, ICC is measured with the

. SWitching Characteristics
Parameter

a and Q outputs high in turn. At the time of measurement, the clock is grounded.

at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)

From
(Input)
To
(Output)

fMAX Maximum
Clock Frequency

•

RL=4 kll
CL=50 pF
Min

Typ

6

11

Units
Max
MHz

tpHL Propagation Delay
Time High to Low
Level Output

Clear
,
to
Q

60

150

ns

tpLH Propagation Delay
Time Low 10 High
Level Output

Clear
'\0

35

75

ns

tpLH Propagation Delay
Time Low to High
Level Ou~pul

Clock
10
QorO

10

35

75

ns

IpLH Propagation Delay
Time Low 10 High
Level Oulpul

Clock
10
QorO

10

60

150

ns

Q

7·44

.------------------------------------------------------------------,0
3:

~National

en
01:00

~ Semiconductor

r

......

01:00

o
3:

DM54L74/DM74L74 Dual Positive-Edge-Triggered
D Flip-Flops with Preset, Clear,
and Complementary Outputs

~

r
......
01:00

General Description

Absolute Maximum Ratings

This device contains two independent positive·edge·
triggered D flip·flops with complementary outputs. The
information on the 0 input is accepted by the flip·flops
on the positive going edge of the clock pulse. The trig·
gering occurs at a voltage level and is not directly
related to the transition time of the rising edge of the
clock. The data on the D input may be changed while the
clock is low or high without affecting the outputs as
long as the data setup and hold times are not violated. A
low logic level on the preset o'r clear inputs will set or
reset the outputs regardless of the logic levels of the
other inputs.

Supply Voltage
Input Voltage
Storage Temperature Range

Connection Diagram

Function Table

(Noie 1)

BV
5.5V
-65°Ct0150°C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Charactetistics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual·ln·Line Package
Vee

CLR2

D2

CLK2

PRZ

OZ

02

Outputs

Inputs
PR

CLR

CLK

D

a

a

L

H
L
L
H
H
H

X
X
X

X
X
X

I
I

H
L

H
L
H*
H
L

L
H
H*
L
H

L

X

00

00

H
L
H
H
H
eLR 1

01

eLK 1

PR 1

Qt

iii

GND

H = High Logic Level

TLlF/6631·1

DM54L74 (J)

X = Either Low or High Logic Level

L = Low Logic Level
t = Positive-going transition.

DM74L74 (N)

00 = The output logic level of Q before the indIcated Input conditions
were established.
* = This configuration is nonstable; that is, it will not persist when either
the preset andlor clear inputs returned to their inactive (high) level.

7·45

Recommended Operating C~ndit.ions
DM54L74
Sym

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level
Input Voltage

I'OH

High Level Output
Current

IOL

Low Level Output
Current

fCLK

Clock, Frequency

tw

Pulse Width

DM74L74

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

~

5.25

2

2

Units
V
V

0.7

0.7

-0.2

-0.2

mA

3.6

mA

6

MHz

2
0

6

0

Clock
High

75

75

Clock
Low

75

75

Preset
Low

75

Clear
Low

75

75

V

ns

75
-,

tsu

Input Setup Time (Note 1)

501

501

ns

tH

Input Hold Time (Note 1)

151

151

ns

TA

Free Air Operating
Temperature

-55

125

Not. 1: The symbol (I) Indicates the rising edge of the clock pulse is used forreference.

7·46

0

70

·C

Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Sym

Parameter

VOH

High Level Output
Voltage

Vec=Min,loH=Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee=Min
10L= Max
VIL=Max
VIH=Min

Input Current@Max
Input Voltage

Vee = Max
VI =5.5V

II

Conditions

Min

Typ
(Note 1)

2.4

3.3

Max

V

DM54

0.15

0.3

DM74

0.2

0.4

V

D

100

mA

Clear

300

Preset

200

"

Clock
IIH

High Level Input
Current

Vee = Max
VI = 2.4V

200

D

10

Clear

30

Preset

20

Low Level Input
Current

Vee=Max
VI =O.4V

D

-0.18

Clear

-0.36

Preset

-0.18

Icc

Short Circuit
Output Current

Vee=Max

Supply Current

Vee=Max
(Note 2)

Note 1: All typicals are at Vec=SV. TA=2S·C.
Note 2: With all outputs open, ICC is measured with the Q and

Q outputs

mA

-0.36

Clock
los

p.A

20

Clock
IlL

Units

DM54

-3

-15

DM74

-3

-15

,.

1.6

3

mA

mA

high in turn. At the time of measurement, the clock input is grounded.

Switching Characteristics at Vee=5V and TA=25°C (See Section 1 for Test Waveforms 'and Output Load)
Parameter

fMAX Maximum
Clock Frequency

From
(Input)
To
(Output)

r

RL=4 kG
Units

CL=50 pF
Min

Typ

6

11

Max
MHz

tpLH Propagation Delay
Time Low to High
Level Output

Preset
to
Q

40

60

ns

tpHL Propagation Delay
Time High to Low'
Level Output

Preset
to

60

120

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clear
to

40

60

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
Q

60

120

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
QorQ'

10

50

90

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
QorQ

. 10

60

120

ns

Q

Q

-

7·47

~National

~ Semiconductor

DM54L75A/DM74L75A Quad Latches
General Description

Absolute Maximum Ratings

These latches are ideally suited fqr use as temporary storage for binary information between processing units and
input! output or indicator units. Information present at a
data (D) input is transferred to the input when the enable
(G) is high, and the
output will follow the data input as
long as the enable remains high. When the enable goes
low, the information (that was present at the data input at
the time the transition occurred) is retained at the output
until the enable is permitted to go high.

Supply Voltage

a

Input Voltage
Storage Temperature Range

a

not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not. guaranteed at the absolute

a

These latches feature complementary
and
outputs
from a 4-bitlatch, and are available in 16-pin packages.

Connection Diagram

maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Oual-In-Line Package
Q1

03

Q2

16

15

14

12

3

2

D1

D2

4

11

5

ENABLE

6

Vee

D3

Q3
10

Q4
9

7

8

D4

04

3-4

74L75A(N)

54L75A(J)

TlIF/6632·1

Function Table (Each Latch)
Inputs

8V
5.5V
-65°C to 150·C

Nole 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

a

a

(Note 1)

Outputs

D

G

Q

Q

L
H
X

H
H
L

L
H

H
L

00

00

H = High Level. L = Low Level, X = Don't Care
ao = The Lavel of a Before the High-to·Low Transition of G

Logic Diagram (Each Latch)

» ......-00

ENABLE

DATA

7-48

Recommended Operating Conditions
DM54L75A
Sym

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level
Input Voltage

10H

High Level Output
Current

. 10L

DM74L75A

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

V
V

2

Low Level Output
durrent

Units

0.7

0.7

-0.2

-0.2

mA

3.6

mA

2

V

tw

Enable Pulse Width

100

100

ns

tsu

Setup Time

100

100

ns

tH

Hold Time

25

25

TA

Free Air Operating
Temperature

-55

Electrical Characteristics

125

ns
70

0

over recommended operating free air temperature (unless otherwise noted)
Min

Typ
(Note 1)

2.4

3.4

Sym

Parameter

VOH

High Level Output
Voltage

Vee = Min, 10H = Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee= Min
10L=Max
VIL=Max
VIH=Min

Input Current@Max
Input Voltage

Vee= Max
VI =5.5V

High Level Input
Current

Vee=Max
VI = 2.4V

o Input

20

Glnput

40

IlL

Low Level Input
Current

Vee=Max
VI = 0.3V

·0 Input

los

Short Circuit
Output Current

Vee=Max
(Note 2)

OM54

-3

-15

OM74

-3

-15

Supply Current

Vec=Max
(Note 3)

II

IIH

lec

Note 1:
Note 2:

'C

Conditions

Max

Units
V

OM54

0.15

0.3

OM74

0.2

0.4

V

o Input

0.2

mA

G Input

0.4

-0.36

3.5

Note 3: ICC is measured with all outputs open and a~1 inputs ground~d .

.'

7·49

rnA

-0.72

G Input

All typicals are at Vec = 5V, TA = 25'C.
Not more than one output should be shorted at a time.

/,A

5

rnA

mA

Switching Characteristics 'at Vcc=5V and TA=25°C
Parameter

From
(Input)
To
(Output)

tp~H Propagation Delay
Time Low to High
Level Output

D
to

tpH~

Propagation Delay
Time High to Low
Level Output

D
to

tp~H

Propagation Delay
Time Low to High
Level Output

D
to

tpHL Propagation Delay
Time, High to Low
Level Output

D
to

tpLH Propagation Delay
Time' Low to High
Level Output

(See Section 1 for Test Waveforms and Output Load)
R~=4kO
C~=50

Min

pF

Units

Typ

Max

55

100

ns

50

100

ns

75

120

32

80

ns

50

100

ns

32

80

ns

48

10~

ns

38

80

ns

Q

,

Q
I,

ns

Q
Q
G
to
Q

tpHL Propagation Delay'
Time High to Low
Level Output

G
to

tpLH Propagation Delay
Time Low to High
Level Output

G
to

tpHL Propagation Delay
Time High to Low
Level Output

to

Q

Q
G

Q

"

,

7-50

.------------------------------------------------------------------,0
:s:
U1

~National

~

~ Semiconductor

r

~

o

:s:

DM54L78/DM74L78 Dual Master-Slave J-K Flip-Flops
with Preset~ Common Clear, Common Clock,
and Complementary Outputs
General

Descripti~n

Absolute Maximum Ratings

This device contains two master-slave J-K flip-flops
with complementary outputs. The J-K data is processed
by the flip-flop after a complete clock pulse. While the
clock is low the slave is isolated from the master. On
the positive going transition of the clock the data from
the J and K inputs is transferred to the master. While
the clock is high the J and K inputs are disabled. On the
negative going transition of the clock the data from the
master is transferred to the slave. The data on the J and
K inputs must not be allowed to change while the clock
is high. The data is transferred to the outputs on the failing edge of the clock pulse. A low logic level on the
preset or clear inputs will set or reset the outputs
regardless of the logic levels of the other inputs.

Supply Voltage
Input Voltage
Storage Temperature Range

Connection Diagram

Function Table

.,
"

.,

......
co

(Note 1)

BV
5_5V
- 65·C to 150·C

Note 1: The "Absolute M,aximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual-In-Line Package

ai,1l

12

Gj;

11

Jj,

Qjg

10

az
s·

~1.
11 [r-

, '1
p1:

.~

I'

J1

---,
I'

v"

I'

CLA

r

I'

PA2

Outputs

Inputs

Y

eL'

~

r

I'

.2

TLlF/6633-1

PR

CLR.

CLK

J

K

0

0

L
H
L
H
H
H
H

H
L
L
H
H

X
X

X
X

X
X

X

X
L
H
L
H

X
L
L
H
H

H
L
H·

L
H
H·

00

00

H
L

L
H

..Jt,.
..r1-

H

..r1-

H

..r1-

Toggle

H = High Logic Level
X = Either Low or High logic Level

DM54L78(J)

DM74L78 (N)

L

=Low Logic Level

= Positive pulse. J-K Inputs must be held constant while the clock Is
high. Data is transferred to the output on the falling edge of the clock.

.Il..

=

* This configuration is nonstable; that is, it will not persist when the
clear and/or preset Inputs return to their Inactive (high) level.

QO = The level of a before the indicated input conditions were
established.
Toggle = Each output changes to the complement of its previous level
on each complete high level clock pulse.

7-51

Recommended Operating Conditions
Sym

DM54L78

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level
Input Voltage

DM74L78

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units
V

2

V

Clock

0.6

0.6

Others

0.7

0.7

V

IOH

High Level Output
Current

-0.2

-0.2

rnA

IOL

Low Level Output
Current'

2

3.6

mA

feLK

Clock Frequency

6

MHz

tw

Pulse Width

6

0

0

Clock
High

100

100

Clock
Low

100

100

Preset
Low

'100

100

Clear
Low

100

100

tsu

Input Setup Time (Note-l)

tH

Input Hold Time (Note 1)

TA

Free Air Operating
Temperature

• 01-

ns

ns

01

01

ns

01
125

-55

·C

70

0

Notel:The symbols (I. I) indicate the edge of the clock pulse used for reference: 1 for rising edge, I for failing edge_

Electrical Characteristics

over recommended operating free air temperature (unless otherwise noted)

Sym

Parameter

VOH

High Level Output
Voltage

Vee=Min,loH=Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee=Min
IOL= Max
VIL=Max
VIH = Min

Input Current@Max
Input Voltage

Vee= Max
VI =5.5V

II

IIH

High Level Input
Current

Conditions

Vee= Max
VI=2.4V

Min

Typ
(Note 1)

2.4

3.3

Max

Units
V

OM54

0.15

0.3

OM74

0.2

0.4

V

mA

J, K

100

Clear

400

Preset

200

Clock

4\)0

.-

J, K

10

Clear

40

Preset
Clock
7·52

20

,

-400

p.A

Electrical Characteristics

(Continued)

over recommended operating freeair temperature (unless otherwise noted)

Sym
IlL

los

Icc

Parameter

Conditions

Low Level Input
Current

Vee = Max
VI = O.4V

Short Circ;uit
Output Current

Vee= Max

Supply Current

Vee=Max
(Note 2)

Min

Typ
(Note 1)

Max

J, K

-0.18

Clear

-0.72

Preset

-0.36

Clock

-0.72

DM54

-3

-15

DM74

-3

-15
1.5

2.88

Units
mA

mA

mA

Note_l: All typicals are at vee=SV, TA=2S'e.
Note 2: With all outputs open, ICC is measured with the 0 and

Switching Characteristics
Parameter

0' outputs high in turn. At the time of measurement, the clock input is grounded.

at Vee=5V and'T'A=25'C (See Section 1 for Test Waveforms and Output Load)

From
(Input)
To
(Output)

f MAX Maximum
Clock Frequency

RL=4 kG
C L =50 pF
Min

Typ

6

11

Units
Max
MHz

tpLH Propagation Delay
Time Low to High
Level Output

Preset
to
a

35

75

ns

tpHL Propagation Delay
,Time High to Low
Level Output

Preset
to

60

150

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clear
to

35

75

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
a

60

150

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
aorQ

10

35

75

ns

tpHL Propagation Delay
Time High to Low
. Level Output

Clock
to
aorO

10

60

150

ns

Q

Q

7-53

~National

~ Semiconductor

DM54L85/DM74L85 4·Bit Magnitude Comparators
General Description

Features

These 4-bit magnitude comparators perform comparison
of straight binary or BCD codes_ Three fully-decoded decisions about two 4·bit words (A, B) are made and are externally available at three outputs_ These devices are fully
., expandable to any number of bits without external gates_
Words of greater length may be compared by connecting
comparators in cascade. The A> B, A < B, and A = B outputs ot" a stage handling less-significant bits are connected to the corresponding inputs of the next stage
handling more-significant bits_ The stage handling the
least-significant bits must have a high-level voltage ap·
plied to the A='B input and lOW-level voltages applied to
the A>B and A< B inputs.

Connection Diagram

• Typical power dissipation 20 mW
• Typical delay (4-bit words) 55 ns

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

A3

J,6

15

B3

A>B AB A B3
A3 < B3
A3 = B3
A3= B3
A3= B3
A3= B3
A3= B3
A3= B3
A3" B3
A3 = B3
A3= B3
A3 = B3
A3" B3
A3" B3
A3= B3
A3" B3

X
X

X
X
X
X

X
X
X
X
X
X

A2 >
A2 <
A2 =
A2 =
A2
A2 =
A2 =
A2"
A2"
A2"
A2"
A2"
A2"
A2"

B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2

=

AI> Bl
Al B A BO
AD < BO
AD = BO
AD =' BO
AD" BO
AD" BO
AO= BO
AO"BO
AO= BO
AO= BO

H
L
L
L
H
H
H
L
H • High level, l • low level, X Don't Care Either LoW or High Logic

=

7-54

Outputs

A=B

X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X

L
H
L
H
L
H
H
L
Level

L
L
H
H
H
H
L
L

A>B AB

0.1

A=B

0.1

Others

0.3

AB

10

A=B

10

Others

30

AB

-0.18

'A=B

-0.18

p.A

mA

-0.54

Others
DM54

-3

-15

DM74

-3

-15

mA

Short Circuit
Output Current

Vcc= Max
(Note 2)

ICC1

Supply Current

Vcc= Max
(Note 3)

6.6

mA

ICC2

Supply Current

Vcc= Max
(Note 4)

7.0

mA

los

Nole 1: Aillypicals are al VCC = 5V, TA = 25°C,
Nota 2: Not more than one output should be shorted at a time.

Nole ,3: ICC1 Is measured

with

all oulpuls open and all inpuls al 4.5V,

Note 4: ICC2 is measured with all outputs open and all inputs grounded.

7-55

•

Switching Characteristics

at Vee = 5V and TA = 25 D C (See Section 1 for Test Waveforms and Output Load)
RL=4 kO

Parameter

tpLH Propagation Delay Time
Low-to-High Level Output

From
Input

To
Output

.Number of
Gate Levels

Any A or B
. Data Input

AB

. Any A or B
Data Input

tpHL Propagation Delay Time
High-to-Low Level Output

CL=50 pF
Min.

Typ

Max

Units

1
2

70
70

115
115

ns

3

70
70

115
115
ns

A=B

4

AB

1
2
3

55
55
55

A=B

4

55

90
90
90
90

tpLH Propagation Delay Time
Low-to-High Level Output

AB

1

55

100

ns

tpHL Propagation Delay Time
High-to-Low Level Output

AB

1

40

65

ns

tpLH Propagation Delay Time
Low-to-High Level Output

A=B

A=B

2

55

100

ns

tpHL Propagation Delay Time
High-to-Low Level Output

A=B

A=B

2

40

65

ns

tpLH Propagation Delay Time
Low-to-High Level Output

A>B
or A=B

AB
orA=B

AB
AJ~

1=1

}--

~A>B

}--

~A

--0

f-

r--

2

INPUT
B

RO(l)

3
RO(2)

14

NC

15

6

7

VCC

R9(1)

R9(2)

OA
13

12

GND

111'

Oc

OB

10

INPUT
B
8

9

CLOCK

9

a

aB

INPUT B .:....---t----<:tCLOCK

10

12

ac

00

TLlF/6637·4

The J and K inputs shown without connection are for reference only and are functionally at a high level.

7-62

c

s::

Recommended Operating Conditions

Vee

Supply Voltage

VIH

High Level Input
Voltage

~

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

IOL

Low Level Output
Current

feLK

Clock Frequency

tw

Pulse Width

Reset Release Time

TA

Free Air Operating
Temperature

<

0.7

0.7

-0.2

-0.2
2

V
mA

6

90

90

B

90

90

200

200

200

200

-55

125

Parameter

VOH

High Level Output
\
Voltage

Vee = Min, IOH = Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee=Min
10L=Max
VIL=Max
VIH=Min
(Note 4)

input Current@Max
Input Voltage

Vee= Max
VI=5.5V

Ice

Note 1:

~

Ie

6

MHz
ns

r-

Co)

High Level Input
Current

Conditions

Vee = Max
VI=2.4V

Low Level Input
Current

Vee= Max
VI =0.3V

Short Circuit
Output Current

Vee= Max
(Note 2)

Supply Current

Vee= Max
(Note 3)

ns
70

Min

Typ
(Note 1)

2.4

3.4

Max

·C

Units
V

DM54

0.15

0.3

DM74

0.25

0.4

Reset

0.1

A

0.2

B

0.4

Reset

10

A

20

B

40

Reset

-0.18

A

-0.36

V

mA

p.A

rnA

-0.72

DM54

-3

-15

DM74

-3

-15
5.5

rnA

rnA

All typicals are at Vee = 5V, TA = 25°C.

Note 2: Not more than one output should be shorted at a time.
Note 3: ICC is measured with' all outputs open, AO inputs grounded following mome,ntary connection to 4.5V and all other inputs grounded.
Note 4: QA outputs are tested at tOl = max plus the limit value of IlL for the B input. This permits driving the B input while maintaining fui! fan-out capability.

7-63

i;!

CD

Co)

0

B
los

C

s::
U1

-s::

0

A

Sym

IlL

r-

p

mA

'L90 Electrical Characteristics

IIH

i;!

3.6

over recommended operating free air temperature (unless otherwise noted)

II

-s::
C

V

C

0

Reset
tREL

Ie
o
CD

High Level Output
Current

IOH

Units

V

2

Low Level
Input Voltage

VIL

DM74L90

DM54L90

Parameter

Sym

'L90 Switching Characteristics at Vcc=5V and TA=25'C
(See Section 1 for Test Waveforms and Output Load)
From
(Input)
To
(Output)

Parameter

f MAX Maximum
Clock Frequency

RL=4 kO
Units

CL=50 pF

A to
QA

Min

Typ

.6

11

Max
MHz

tpLH Propagation Delay
Time Low to High
Level Output

A
to
QD

175

300

tpHL Propagation Delay
Time High to Low
Level Output

A
to
QD

190

300

'.

ns

ns

Recommended Operating Conditions
DM54L93

DM74L93

Sym

Parameter

Vcc

Supply Voltage

V1H

High Level Input
Voltage

V1L

Low Level
Input Voltage

. 0.7

0.7

10H

High Level Output
Current

-0.2

-0.2

mA

IOL

Low Level Output
Current

3.6

mA

fCLK

Clock Frequency

6

MHz

tw

Pulse Width
/

tREL

Reset Release Time

TA

Free Air Operating
Temperature

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5"

5.25

2

2

2
6

0

0

A

90

90

B

90

90

Reset

200

200

200

200
125

~55

7·64

0

Units
V
V
V

ns

ns
70

'C

'L93 Electrical Characteristics

over recommended operating free air temperature (unless otherwise noted)

Sym

Parameter

VOH

High Level Output
Voltage

Vee = Min, 10H = Max
VIL=Max, VIH=Min

VOL

Low Level Output
Voltage

Vce= Min
10L= Max
VIL=Max
VIH = Min
(Note 4)

Input Current@Max
Input Voltage

Vee= Max
VI =5.5V

High Level Input
Current

Vee= Max
VI=2.4V

Low Level Input
Current

Vee= Max
VI =0.3V

Short Circuit
Output Current

Vee= Max
(Note 2)

Supply Current

Vee=Max
(Note 3)

II

IIH

Conditions

,
IlL

Min

Typ
(Note 1)

2.4

3.4

lee

Units
V

DM54

0.15

0.3

DM74

0.25

0.4

Reset

0.1

A

0.2

B

0.2

Reset

10

A

20

V

mA

p.A

20

B
Reset

-0.18

A

-0.36

mA

-0.36

B
los

Max

DM54

-3

-15

DM74

-3

-15
5.5

mA

mA

Note 1: All typicals are at VCC=5V, TA=25°C.

Note 2: Not more ~han one output should be shorted at a time.
Note 3: ICC is measured with all outputs open, AO inputs grounded following momentary connection to 4.5V and all other inputs grounded.
Note 4: QA outputs are tested at IOL = max plus the limit value of I,L for the'S input. This permits driving the B input while maintaining full fan·out capability.

'L93 Switching Characteristics

at Vee=5V and TA=25°C
(See Section 1 for Test Waveforms and Output Load)

Parameter

f MAX Maximum
Clock Frequency

From
(Input)
To
(Output)
A to
QA

RL =4kn
C L =50 pF
Min

Typ

6

15

Units
Max
MHz

tpLH Propagation Delay
Time Low to High
Level Output

A
to
QD

210

400

ns

tpHL Propagation Delay
Time High to Low
Level Output

A
to
QD

230

400

ns

,

7-65

~.---------------------------------------------------~-------------.
0)

.
~ Semiconductor

t:!: ~National

...I

::!E

c

~

DM54L95/DM74L95 4·Bit Parallel Access Shift Registers

~
;1) General Description
::!E These 4-bit registers feature parallel and serial inputs, parc allel outputs, mode control, and two clock inputs. The registers have three modes of operation.

Parallel (broadside) load
Shift right (the direction QA toward QD)
Shift left (the direction QD toward QA)

Changes at the mode control input should normally be
made while both clock inputs are low; however, conditions
described in the last three lines of the truth table will also
ensur,e that register contents are protected.

Features
• Typical maximum clock frequency 14 MHz
• Typical power dissipation 24 mW

Parallel loading is accomplished by applying the four bits of
data and taking the mode control input high. The data is
loaded into the associated flip-flops and appears at the
outputs after the high-to-Iow transition of the clock-2 input.
During loading, the entry of serial data is inhibited.

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

Shift right is accomplished on the high-to-Iow transition of
clock 1 when the mode control is low; shift left is accomplished on the high-to-Iow transition of clock 2 when the
mode control is high by connecting the output of each flipflop to the parallel input of the previous flip-flop (QD to input
C, etc.) and serial data is entered at input D_ The clock input
may be applied simultaneously to clock 1 and clock 2 if
both modes can be clocked from the same source.

Connection Diagram

-

(Note 1)

65~C

8V
5.5V
to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device c!,n not bE> guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guarante'ed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual-In-Line Package
OUTPUTS

OUTPUTS

---------.

---------.
INPUT A'

OA

14

GND

Os

111

12

13

Oc

00

10

CLOCK 2
L-SHIFT
(LOAD)

9

0-

,.......

54L95 (J)

74LIl5 (N)

0-

~---.------~--~

14
SERIAL INPUT S INPUT e
INPUT

Function Table

6
INPUT 0

vee

MODE CLOCK 1
CONTROL R-SHIFT

Inputs
Clocks

Mode
Control

Serial

2 (Ll

1 (Rl

H
H
H
L
L
L

H

I
I

X
X
X

L

H

X
X
X
X

X
X

H
L

t

L
L
L
H
H

I
I

I
I

t
t

X
X
X
X
X

L
L
H
L
H

TLlFJ66,38-1

Outputs
Parallel
QA

QB

Qc

X

QAO

a

QBO
b
QCn
QBO
·QAn
QAn
Q80
Q80
Q80
QBO
QBO

QCO

d
d

A

B

C

D

X,

X

X

C
b
a
QBt Qct QDt

X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X

QBn
QAO
H
L
QAO
QAO
QAO
QAO
QAO

QD

QOO
d
d
QDn
QCO QOO
QBn QCn
QBn QCn
QCO QOO
QCO QDO
QCO QOO
QCO QDO
QCO' QOO
C

tShifting teft requires external connection of aS to A, QC to B, aD to C. Serial data is entered at input O.
H = High level (Steady Slate), L = Low Level (Steady State), X = Don't Care (Any input, including transitions)
= Transition from high to low level, = Transition from low to high level
B, b, c, d. = The level of st'1'sdy stete input at inputs A, B, C, or 0, respectively.
QAO, 0ao. Qeo. QoO = The level of QA. Qs. aCt or 00. respectively. before the indicated steady state input conditions were established.
0An. OSn. OCn.
or QO. respectively. before the most racent , transition of the clock.
n = The level of QA.

t

~

aO

aS. aCt

7-66

c

s:

Logic Diagram

~

r-

-s:
CD

,
MODE

6"

DATA INPUTS
A

e

14

.....

c.n

C

2

D

3

,

C

~
r-

5

CONTROL-~
SERIAL
INPUT

1

CLOCK 1
RIGHT SHIFT

7

CLOCK 2
LEFT SHIFT

8

CD

c.n

---.J

NNN

"-

,..-

ii:~ ~:: 0::: ~::
" - - S DC
'---

S De

-

'---

13

12

S DD

10

De

,DA

9

DD

DC

,

OUTPUTS
TLlF/6636·2

Recommended Operating Conditions
DM54L95

Sym

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

V IL

Low Level
Input Voltage

IOH

High Level Output
Current

IOL

Low Level Output
Current

fCLK

Clock Frequency

tW(CLK)

Pulse Width of Clock

DM74L95

Min

NDm

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

Data Setup Time

tEN

Time to
Enable Clock

tH

Data Hold Time

tiN

Time to
Inhibit Clock 1 or Clock 2

TA

Free Air Operating.
Temperature

I

I

V
0.7

-0.2

-0.2

mA

3.6

mA

6

MHz

6

90

tsu

V

0.7

2
0

Units

0

V

ns

90

50

50

ns

Clock 1

120

120

ns

Clock 2

100

100

ns

0

0

ns

0

0

ns

,

;

-55

125

7·67

0

70

·C

•

Electrical Characteristics

\

over recommended

op~rating

Conditions

free air temperature (unless otherwise noted)
Min

Typ
(Note 1)

2.4

3.1

Sym

Parameter

VOH

High Level Output
Voltage

Vee = Min, IOH = Max
VIL = Max, VIH = Min

VOL

Low Level Output
Volt.age

Vee=Min
IOL= Max
VIL= Max
VIH=Min

Input Current@Max
Input Voltage

Vee=Max
VI=5.5V

Mode

0.2

Others

0.1

High Level Input
Current

Vee = Max
VI=2.4V

Mode

20

Others

10

Low Level Input
Current

Vee = Max
VI =0.3V

Mode

-0.36

Others

-0.18

Short Circuit
Output Current

Vee= Max
(Note'2)

Supply Current

Vee = Max
(Note 3)

II

IIH

IlL

los

Icc

Max

V

DM54

0.13

0.3

DM74

0.2

0.4

DM54

-3

-15

DM74

-3

-15

8

4.8

Note 1: All typicals are at Vee=SV, TA=2S"e.
Nole 2: Not more than one output should be shorted at a time.
Note 3: ICC is measured with all outputs and serial Input open; A, B, C and 0 inputs grounded; mode control

~t

Units

V

mA

p.A

mA

mA

mA

4.5V; and a momentary 3V, then ground, ap·

plied to both clock Inputs.

Switching Characteristics at Vee = 5V and TA ~ 25°C (See S~ction 1 for Test Waveforms and Output Load)
Parameter

From
(Input)
To
(Output)

fMAX Maximum
Clock Frequency

RL=4 kO
CL=50pF
'Min

Typ

6

14

Units
Max
MHz

tPLH Propagation Delay
Time Low to High
Level Output

Clock
to
Output

42

90

ns

tPHL Propagation Delay
Time High to Low
Level Output

Clock
to
Output

48

90

ns

7-68

c

s:

~National

C1I

.j:>,

~ Semiconductor

reo
(XI

-s:
C

~
reo
(XI

DM54L98/DM74L98 4·Bit Storage Registers

General Description

Absolute Maximum Ratings

These data selectors / storage registers are composed of
four S-R master-slave flip-flops, four AND-OR INVERT
gates, one buffer, and six inverter/drivers.

Supply Voltage
Input Voltage
Storage Temperature Range

When the word select input is low, word 1 (A1, 91, C1, 01)
is applied to the flip-flops. A high level input to word select
will cause the selection of word 2 (A2, 92, C2, 02). The
selected word is shifted to the output terminals on the negative-going edge of the clock pulse.
Typical clock frequency is 12 MHz.

Connection Diagram

(Note 1)

BV
5.5V
- 65·C to 150·C

Note 1: The "Absolute Maximum Ratmgs" aie those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define tre conditions for actual device operation.

Logic Diagram

Dual-in-Line Package
OUTPUTS

1,6

15

14

13

12

11

10

9

r-

1
A2

2
A1

3
61

4
62

5
C1

6
C2

7
02

Ie
GND

INPUTS
TliF/6639·1

54L98 (J)

74L98 (N)
(11)
QD

Word select low for word 1. word select high for word 2. see description

..

CLOCK ;.(1-'0)'--_ _ _ _ _ _~>-----

TLlF/6639-2

7·69

Recommended Operating Conditions
Sym
Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level
Input Voltage

IOH

High Level Output
Current

10L

Low Level Output
Current

fCLK

Clock Frequency

tw

Clock Pulse Width

tsu

Setup Time

TA

DM54L98

Parameter

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

0

-0.2

-0.2

mA

3.6

mA

6

MHz

0

65

100

100

100

Data
Low

120

120

Select
High

150

150

Select
Low

10Q

100

-55

125

Parameter

VOH

High Level Output
Voltage

Vcc=Min,loH=Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage,

Vcc= Min
10L=Max
VIL=Max
VIH= Min

' Input Current@Max
Input Voltage

65

V

ns
ns

70

0

~C

over recommended operating free air temperature (unless otherwise noted)

Sym

Conditions

Min

Typ
(Note 1)

Max

2.4

Units
V

DM54

0.15

0.3

DM74

0.2

0.4

V

Vcc = Max, VI = 5.5V

0.1

mA

10

p.A

IIH

High Level Input
Current

Vce = Max, VI = 2.4V

IlL

Low Level Input
Current

Vce = Max, VI = 0.3V

los

Short Circuit
Output Current

Vee=Max
(Note 3)

Supply Current

Vce=Max
(Note 2)

Icc

0.7

Data
High

Free Air Operating
Temperature

V

0.7

6

100

Units

V

2

Electrical Characteristics

II

DM74L98

Min

-0.18

rnA
mA

DM54

-3

-15

DM74

-3

-15
6

Nole 1: Aillypicals are at Vee=5V, TA=25·C:
Note 2: ICC is measured with all outputs open and all inputs grounded.
Note 3: Not more than one output should be shorted at a time.

7-70

'8

mA

c

Switching Characteristics
Parameter

f MAx Maximum
Clock Frequency

at Vee = 5V and TA = 25°C!(See Section 1 for Test Waveforms and Output Load)

From
(Input)
To
(Output)

Min

Typ

,

6

12

RL=4 kG

s:

Z!
r-

CD
CO

CL=50 pF

Units
Max
MHz

5
s:
i:!
r-

CD
CO

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
Output

40

80

ns

tpHL Propagation Delay
,Time High to Low
Level Output

Clock
to
Output

65

100

ns

.

.

7·71

.
~ Semiconductor
~National

DM54L157A/DM74L157A Quad 2·Line to 1·Line
Data Selectors/Multiplexers
General Description

Features

These data selectors/multiplexers contain inverters and
drivers to supply full on-chip data selection to the four
output gates. A separate strobe inpu't is provided. A 4-bit
word is selected from one of two sources and is routed to
the four outputs.

•
•
•
•

Applications

Absolute Maximum Ratings

• Expand any data input point
• Multiplex dual data buses
• Generate four functions of two variables (one variable
' iscommon)

Buffered inputs and outputs
Three speed/power ranges available
Typical propagation time 40 ns
Typical power dissipation 15 mW

Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

BV
5.5V
- 65'C to 150'C

• Source programmable counters
Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute.
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Connection Diagram
Dual-In-Line Package
Vee

STR~BE

116

INPUTS
'A4
B4

15

14

INPUTS
OUTPUT
, A3
B3
Y4

12

13

11

OUTPUT
Y3

10

9

Inputs

I-

r-- '

Output

Strobe

Select

A

B

Y

H
L
L
L
L

X
L
L
H
H

X
L
H
X
X

X
X
X
L
H

L
L
H
L
H

H = High Level, L = Low Level, X = Don't Care

2

S

SELECT '

A1

4·

3

B1

INPUTS

5

Y1

A2

OUTPUT '

7

6

B2

Y2

INPUTS ' OUTPUT
TLlF16640·1

Low level at S selects A inputs
High level at S selects B inputs

DM54L157A (J)

DM74L 157A (N)

7-72

c

:s:

Recommended Operating Conditions
Sym

Parameter

Vee

Supply Voltage

V IH

High Level Input
Voltage

V IL

Low Level Input
Voltage

~

DM74L157A

DM54L157A
Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

0.7

0.7

10H

High Level Output
Current

-0.2

10L

Low Level Output
Current

2

TA

Free Air Operating
Temperature

-55

Electrical Characteristics

125

0

Units

V
V

....r

-0.2

mA

3.6

mA

70

·C

Typ
(Note 1)

Sym

Parameter

VOH

High Level Output
Voltage

Vee = Min, 10H = Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee=Min
10L= Max
V IH = Max
VIH=Min

II

Input Current@Max
Input Voltage

Vee = Max, VI = 5.5V

0.1

mA

IIH

High Level Input
Current

Vee = Max, V I ;=2.4V

10

p.A

IlL

Low Level Input
Current

Vee = Max, VI = 0.3V

los

Short Circuit
Output Current

Vce= Max
(Note 3)

Supply Current

Vec= Max
(Note 2)

Icc

Min

Max

DM54

0.15

0.3

DM74

0.2

0.4

mA
mA

DM54

-3

. -15

-3

-15
3

7-73

V

-0.18

DM74

Note 1: All typi~als are at Vec=5V. TA=25"C.
Note 2: ICC is measured with 4.5V applied to all inputs and all outputs open.
Note 3: Not more than one output should be shorted at a time.

Units
V

2.4

4

(J1

-:s:~

V

over recommended operating free air temperature (unless otherwise noted)

Conditions

....r

mA

c

~

(J1

.....

l>

Switching Characteristics

at Vcc=5V and TA=25 D C (See Section 1 for Test Waveforms and Output Load)

From
Parameter

RL=4 kll

(~nput)

CL =50 pF

To
(Output)

tpLH Propagation Delay
Time Low to High
Level Output

Data
to

tpHL Propagation Delay
Time High to'Low
Level Output

Data
to

tpLH Propagation Delay
Time Low to High
Level Output

Strobe
to

tpHL Propagation Delay
Time High to Low
Level Output

Strobe
to

tPLH Propagation Delay
Time Low to High
Level Output

Select
to

tpHL Propagation Delay
Time High to Low
Level, Output

Select
to

Min

Units

Typ

Max

40

80

ns

40

80

ns

60

120

ns

60 '

120

ns

70

140

ns

50

100

ns

y

y

y
,

y

y

y

logic Diagram
A1 IZI

~Y1

Bl (3}

A2 (5)

~YZ

82 (6)

1\3 (11)

~Y3

B3(10)

A4 1141

~Y4

84 (13)

SELECT~~
STROBE (15)
c:l":>--v

7·74

-

c

s:
C1I

~National

.j::Io

~ Semiconductor
DM54L164A/DM74L164A a·Bit Serial
In/Parallel Out Shift Registers

-s:~

General Description

r.....

These a-bit shift registers feature gated serial inputs and
an asynchronous clear. A low logic level at either input inhibits entry of the new data. and resets the first flip-flop to
the low level at the next clock pulse. thus providing complete control over incoming data. A high logic level on either
input enables the other input. which will then determine the
state of the first flip-flop: Data at the serial inputs may be
changed while the clock is high or low. but only information
meeting the setup requirements will be entered. Clocking
occurs on the low-to-high level transition of the clock input.

r.....

Q)

C

~

~

• Typical clock frequency 14 MHz
• Typical power dissipation 30 mW

Absolute Maximum Ratings

(Note 1)

8V

Supply Voltage
Input Voltage

5.5V
- 65·C to 150·C

Storage Temperature Range

• Asynchronous clear

Note 1': The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Features
• Gated (enable I disable) serial inputs
• Fully buffered clock and serial inputs

Dual-In-Line Package
OUTPUTS
Vee

114

Oti
13

QG

,.

OF

OE

10

11

CLEAR CLOCK

9

8

-

1

Clock

A

B

OA

OB

L
H
H
H
H

X
L

X
X
H
L
X

X
X
H
X
L

L
QAO
H
L
L

L
QBO
QAn
QAn
QAn

t
t
t

.. ..-------._-

OH
L
QHO
QGn
QGn
QGn

H = High Level (steady state), L = Low Level (steady state)

•

~

Outputs

Inputs
Clear

4

3
~A

SERIAL INPUTS

OB

5

6

17

Qc

0D,

GND

= Don't Care (any input, includmg transitions)

t = Transition from low to high level
0AO~ 0eo, 0HO = The level of 0A, 0e. or 0H, respectively, before the indicated steady·state input conditions were established.

OUTPUTS

TLlF/6641·1

54L 164A (J)

X

74L 164A (N)

0An' 0Gn = The level of 0A or 0G before the most recent
clock: indicates a one-bit shift.

t transition

of the

Logic Diagram
CLEA"~~~I-------ql;'>---~-------t--------t-------~------~~------~------~--------,
CLOCK~18~1----~I~>-t---4---~---+--~~--f---~--~--~----~--t---4---~---4--~

OUTPUTS

7-75

TLlF/6641-2

•

Recommended Operating Conditions

\

DM54L164A

Sym

Parameter

Vcc

Supply Voltage

VIH

High Level Input
VoltagE!

VIL

Low Level
Input Voltage

IOH

High Level Output
Current

10L

Low Level Output
Current

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

fCLK

Clock Frequency
.Pulse Width

l

I

3.6

mA

6

MHz

6

0
40

Clear

60

40

60

40

20

40

20

-5

20

-5

0

,

40 '
20

TA

Free Air Operating
Temperature

-55

Electrical Characteristics

125

Parameter

VOH

High Level Output
Voltage

Vee = Min, 10H = Max
V IL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vce= Min
IOL=Max
VIL=,Max
VIH=Min

Input Current@Max
Input Voltage

Vcc=Max
VI=5.5V

High Level Input
Current

Vce=Max
VI = 2.4V

Low Level Input
Current

Vcc= Max
VI = 0.3V

Short Circuit
Output Current

Vcc= Max
(Note 2)

Supply Current

Vcc=Max
(Note 3)

f

V

ns

ns
ns
70

'C

over recommended operating free air temperature (unless otherwise noted)

Sym

Icc

mA

60

Data Hold Time

los

-0.2

40

Data Setup Time

IlL

-0.2

60

tH

IIH

0.7

Clock

tsu

V

0.7

2
0

Units

V

2

.'

tw

II

DM74L164A

Conditions

Min

Typ
(Note 1)

Max

Units
V

2.4
DM54

0.15

0.3

DM74

0.2

0.4

V

Clear

0.2

mA

Others

0.1

Clear

20

Others,

10

Clear

-0.36

Others

-.0.18

DM54

-3

-15

DM74

-3

-15

6

9

p.A

mA

mA

mA

Noto 1: All typicals are at VCC =SV, TA =2S'C.
Note 2: Not more than one output should be shorted at a time.

Noto 3: ICC Is measured with outputs open, SERIAL inputs grounded, the CLOCK input at 2.4V, and a momentary ground, then 4.SV, applied to the CLEAR
Input.

7-76

Switching Charapteristics ~t Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
From
(Input)
To
(Output)

Parameter

f MAX Maximum
Glock Frequency

RL = 4 kll
CL =50 pF
Min

Typ

6

14

Units
Max
MHz

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
Output

50

85

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
Output

90

135

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to
Output

75

120

ns

J

Timing Diagram

LJ

CLEAR-U

SERIAL {
INPUTS

A

8

~

CLOCK

..r

Q~ : : : '
08

:~:'

Oc : : : '

---,

Lr"L -

00 ___

---,

OUTPUTS

Qe ___
OF

~

I

~
r-L

:::1

QG : : : .
QH

I

:::1

~

I

I

CLEAR

CLEAR

TLlF16641·3

7-77

~National

~ Semiconductor

DM54L165A1DM74L165A a-Bit Parallel
In/Serial Out Shift Registers
General Description

Features

These are a-bit serial shift registers which shift the data in
the direction of QA toward QH when clocked: Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shift !load
input. These registers also feature gated clock inputs and
complementary outputs from the eighth bit.

• Complementary outputs
• Direct overriding (data) inputs

Clocking is accomplished through a 2-input NOR gate,
permitting one input to be used as a clock-inhibit function.
Holding either of the clock inputs high inhibits clocki~g, and
holding either clock input low with the load input high enables the other clock input. The clock-inhibit input should
be changed to the high level only while the clock input is
high. Parallel loading is inhibited as long as the load input is
high. Data at the parallel inputs are loaded directly into the
register on a high-to-Iow transition of the shi!t Iload input:
regardless of the logic levels on the clock, clock inhibit, or
serial inputs.

Connection Diagram

•
•
•
•

Gated clock inputs
Parallel-to-serial data conversion
Typical clock frequency 14 MHz
Typical power dissipation 30 mW

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

8V
5.5V
- 65·C to 150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaran'teed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Dual-In-Line Package
vee
116

CLOCK
INHIBIT ' D

15

PARALLEL INPUTS

C
14

3
SHIFT I CLOCK
LOAD

E

B
13

SERIAL OUTPUT
A 'INPUT
QH

12

4

5
G

10

11

6
H

'---PA-R-A-LL-E~L-IN-PU-T-S-""

7

9

18

OUTPUT GND

OH

Inputs
Shift I Clock Clock
Load Inhibit
L

X

X

H
H
H
H

L
L
L
H

L

X
X

t
t

H
L

X

X

Parallel

Internal
Outputs

Output
QH

A ... H

QA

Q8

a ... h
X
X
X
X

a
OAO
H
L
OAO

b
OBO
OAn
,OAn
OBO

h
OHO
OGn
OGn
OHO

H = High Level (steady state), L ... Low Level (steady stale)
X = Don't Care (any Input, including transitions)
t "" Transition from IOW'fO-high level
a ... h "" The level of steady·stale input at inputs A through H, respectively.
0AO' 0BO' 0HO ... The level of OA' aS, or 0H' respectively, before the indicated steady-state
input conditions were established.
OAn' 0Gn = The level 01 0A or aG, respectively, belore the most recent t transition ollhe
clock.

TLlF16642-1

54L165A(J)

Serial

74L165A(N)

7-78

.--------------------------------------------------------------------,0
:s::
en

Logic Diagram

oI:a

....r
~

PARALLEL INPUTS

-:s::
o

(9)

OUTPUTDH
(7)

~:;:::- ","I1_0.;..'--1;>0....--+-1-1'

OUTPUTOH

.,...---qt>-+

SHIFT/ -,-(1-,-'
LOAD -

TLlF16642·2

Timing Diagram
TYPICAL SHIFT, LOAD, AND INHIBIT SEQUENCES
CLOCK

CLOCK INHIBIT

-='--___+-__________________

SERIAL INPUT _ _

SHIFT/LOAD
A

B __~~------~-----------------------------C

D __
DATA

~~------~--~~------------------------

E
F

---r------r--------------------------

G

H

H

OUTPUT DH

H

OUTPUTOH
I-INHIBIT--.....- - - - - - - S E R I A L S H I F T - - - - - - _
LOAD
TL/FJ6642·3

7·79

:ii!
r

....

~

Recommended Operating Conditions
,
Sym

Parameter

Vcc

Supply Voltage

V IH

High Level Input
Voltage

V IL

Low Level
Input Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

fCLK

Clock Frequency

tw

Pulse Width

DM54L165A

DM74L165A

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

0

I Clear

0.7

-0.2

-0.2

mA

3.6

mA

6

MHz

6

0
100

100

100

tsu

Setup lime

'44

44

tH

Hold Time

10

10

TA

Free Air Operating
Temperature

Electrical Characteristics

125

ns

ns
ns
70

0

over recommended operating free air temperature (unless

Parameter

Sym

Typ
(Note 1)

Min

High Level Output
Voltage

Vcc = Min, 10H = Max
VIL = Max, VIH = Min

2.4

Low Level Output
Voltage

Vcc= Min
10L= Max
VIL=Max
VIH = Min

II

Input Current@Max
Input Voltage

Vcc = Max, VI = 5.5V

IIH

High Level Input
Current

Vcc=Max
VI =2.4V

Low Level Input
Current

Vcc=Max
V I =0.3V

Shift/Load

-0.54

Others

-0.18

Short Circuit
Output Current

Vcc=Max
(Note 2)

DM54

-3

-15

DM74

-3

-15

Supply Current

Vcc= Max
(Note 3)

VOL

IlL

los

Icc

,

·C

oth~rwise noted)

Conditions

VOH

V

0.7

100

-55

V
V

2

I Clock

Units

Max

Units
V

DM54

0.15

0.3

DM74

0.2

0.4

V

0.1

mA

Shift/Load

30

f'A

Others

10

9.5

mA

mA

mA

Note 1: All typicals are at VCC = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time.

Note 3: With all outputs open, CLOCK INHIBIT and SHIFT/LOAD at 4.5V, and a clock pulse applied to the CLOCK, ICC is measured first with the parallel in·
puts at 4.5V, then a second time grounded.

,
7·80

c

Switching Characteristics
Parameter

at Vee = 5V and T A = 25°C (See Section 1 for Test Waveforms and Output Load)

s:
U1
~

From
(Input)
To
(Output)

....

RL=4 kD
C L =50 pF

f MAX Maximum
Clock Frequency

Min

Typ

6

14

Units
Max
MHz

ren

-s:~
C

:;;:!

tpLH Propagation Delay
Time Low to High
Level Output

Load
to
Any Q

44

88

ns

tpHL Propagation Delay
Time High to Low
Level Output

Load
to
AnyQ

62

124

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
Any Q

35

70

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
Any Q

50

100

ns

tpLH Propagation Delay
Time Low to High
Level Output

H
to
QH

33

66

ns

tpHL Propagation Delay
Time High to Low
Level Output

H
to
QH

56

112

ns

tpLH Propagation Delay
Time Low to High
Level Output

H
to
QH

33

66

ns

tpHL Propagation Delay
Time High to Low
Level Output

H
to
QH

56

112

ns

....

ren

~

I

7·81

~National

~ Semiconductor

DM54L1921 DM74L192, DM54L1931 DM74L193
Synchronous Upl Down Counters with Dual Clock
General Description
These circuits are synchronous up/down counters; the
L192 circuits are' BCD counters and the L 193 are 4-bit
binary counters_ Synchronous operation is provided by
having all flip-flops clocked simultaneously so that the
outputs change together when so instructed by the steering logic_ This mode of operation eliminates the output
counting spikes normally associated with asynchronous
(ripple-clock) counters_

Similarly, the carry output produces a pulse equal in width
to the count down input when an overflow condition exists.
The counters can then be easily cascaded by feeding the
borrow and carry outputs to the count down and count up
inputs respectively of the succeeding counter.

. Features

The outputs of the four master-slave flip-flops are triggered
by a low-to-high level transition of either count (clock) input. The direction of counting is determined by which count
input is pulsed, while the other count input is held high_

•
•
•
•
•

All four counters are fully programmable; that is, each output may be preset to either level by entering the desired
data at the inputs while the load input is low. The output will
change independently of the. count pulses. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs.

Fully independent clear input
Synchronous· operation
Cascading circuitry provided internally
Individual preset each flip-flop
Typical count frequency 12 MHz

• Typical power dissipation 40 mW

Absolute Maximum Ratings

(Note 1)

A clear input has been provided which, when taken to a high
level, forces all outputs to the low level; independent of the
count and load inputs. The clear, count, and load inputs are
buffered to lower the drive requirements of clock drivers,
etc., required for long words.

Supply Voltage
Input Voltage
Storage Temperature Range

These counters were designed to be cascaded without the
need for external circuitry. Both borrow and carry outputs
are available to cascade both the up and down counting
functions. The borrow output produces a pulse equal in
width to the count down input when the counter underflows.

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram
Dual-In-Line Package
INPUTS

OUTPUTS

INPUTS

~~

Vcc

f

16

DATA
DATA
A CLEAR BORROW CARRY LOAD
C

15

14· 13

12

DATA B DB
DA COUNT COUNT
INPUT _____ DOWN
UP
OUTPUTS

----.....-..INPUTS

11

DATA
D

10

DC
OUTPUTS
TLIFI6643·'

Note: Low input to load sets QA

DMS4L192, L193 (J)

= A. aS = St Qc = C. and aD = o.

DM74L192, L193 (N)

7-82

BV
5.5V
-6S·Cto1S0·C

Recommended Operating Conditions
DM54L192, L193
Sym

Parameter

DM74L192, L193

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units

~

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level
Input Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

2

2

V
V
V

0.7

0.7

-0.2

-0.2

mA

3.6

mA

6

MHz

2

O·

feLK

Clock Frequency

0

tw

Pulse Width of Any Input

70

70

ns

tsu

Data Setup Time

30

30

ns

tH

Data Hold Time

0

0

TA

Free Air Operating
. Temperature

6

-55

125

ns
70

0

'c

'L 192 and 'L 193 Electrical Characteristics -

oyer recommended operating free air temperature (unless otherwise noted)
Sym

Parameter

VOH

High Level Output
Voltage

Vee = Min, 10H = Max
YIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vee= Min
10L= Max
VIL=Max
VIH = Min

II

Input Current@Max
Input Voltage

IIH

Conditions

Min

Typ
(Note 1)

Max

2.4

Units
V

DM54

0.15

0.3

DM74

0.2

0.4

V
.'

Vec=Max, VI=5.5V

0.1

mA

High Level Input
Current

Vee = Max, VI = 2.4V

10

p.A

IlL

Low Level Input
Current

Vee = Max, VI = 0.3V

los

Short Circuit
Output Current

Vee = Max
(Note 2)

Supply Current

Vee = Max
(Note 3)

lee

·-0.18

mA
mA

DM54

-3

-15

DM74

-3

-15
5.5

Note 1: Aillypical values are at VCC = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time.
Note 3: ICC 15 measured with all outputs open, clear and load Inputs grounded, and all other inputs at 4.SV.

7-83

mA

'L192 and 'L193 Switching Characteristics at Vee = 5V and TA = 25°C
(See Section 1 for Test Waveforms and Output Load)

Parameter

From
(Input)
To
(Output)

RL=4 kll
C L=50 pF

fMAX Maximum
Clock Frequency

Min

Typ

6

8

Units
Max

MHz

t PLH Propagation Delay
Time Low to High
Level Output

Count Up
' to
Carry

30

60

ns

tpHL Propagation Delay
Time High to Low
Level Output

Count Up
to
Carry

60

120

ns

tpLH Propagation Delay
Ttme Low to High
Level Output

Count Down
to
Borrow

30

60

ns

tpHL Propagation Delay
Time High to Low
Level Output

Count Down
to
Borrow

50

100

ns

tpLH Propagation Delay
Time Low to High
Level Output

Either Count
to
Any

45

90

ns

tpHL Propagation Delay
Time High to Low
Level Output

Either Count
to
Any

75

150

ns

tpLH Propagation Delay
Time Low to High
Level Output

Load
to
Any

55

110

ns

tpHL Propagation Delay
Time High to Low
Level Output

Load
to
Any

105

200

ns

tPHL Propagation Delay
Time High to Low
Level Output

Clear
to
Any

95

190

a
a
a

a

/

a

7-84

ns

c

3:
en

Logic Diagrams

oCIo

r....

~
c

is:

L192

~
r-

....

(13) BORROW

--"""""""'

DATA
INPUT A

DOWN
COUNT

,!')

(12) CARRY
0 UTPUT

c
is:

i!

(15)

~
V

I

~

c'=::':

aA

r
DATA
INPUTB

OUTPUT OA

(2)

OB

OUTPUT Os

T
aB

}>r

r-

6-J

(10)

c'=::':

l-

~~.
(9)

(14)
CLEAR

(6)

Oc

OUTPUT Oc

T
ac

r
DATA
INPUT 0

Co)

~

-

DATA
INPUTC

....

CD

(1)

~~

t-

J

--

r---"
t--I
(7)
00

OUTPUT 00

T
aD

(11
LOA0

J

t-

~
TL/F/6643·2

7·85

c
is:

~
r-

t-

~

c'=::':

Co)

(3)

OA

~
v

r....
CD

T
UP
COUNT

CD

0 UTPUT

~-~--------------------------------------------------~

........
Q)

Logic Diagrams

(Continued)

~

:E

c

i....

L193

....

(13)

~
1.1)

.r

BORROW
0 UTPUT

:E

c
gf

........

t:!:
:E
c

~
....

...I

~
:E

(12)

DATA (15)
INPUT A
DOWN
COUNT

r_r

~

~
v

CARRY
0 UTPUT

(3) 0

QA

UTPUTQA

T
UP
COUNT

~

c

.
DATA (1)
INPUT B

I--

CiA

~
v

-

r----

6T
.1-

.J

(2)
OUTPUTQB

QB
T
CiB

]
,

L.-f"-p
DATA (10) INPUTC

-~

t-

6-J
1-

1:::::1

(6)
OUTPUTQC

QC

T

""I

Cic

~

-

I--

6-;T

A

(9)
DAT
INPUT D
(14~

CLEAR - - - V

r-'

-=
(7)
QD
T

Cia I-"---.--..

:rP~

(11)
LOAD

7·86

OUTPUTQD

c

:s:
~
r
....

Timing Diagrams
L192 Decade Counters
Typical Clear, Load and Count Sequences
CLEAR~~

~

______________________~_____________________

-:s:c
:;;;!

LOAD

r
....

~
c

:s:
~

r
....
co

-:s:
Co)

COUNT --+-+--+-+-...,
UP
COUNT--+-+--+-t--t---------+---,
DOWN

c

:;;;!

r
....
co

OA

Co)

Os
OUTPUTS

CARRY
SORROW

"""""""',..--A--. I
101

171

>8

9

0

1

2

1 I

~COUNTUP-,

1

0

9

B

71

. - - - COUNT DOWN-::-a

CLEAR PRESET

Sequence:
(1) Clear outputs to zero.
(2) load (preset) to BCD seven.
(3) Count up to eight. nine. carry, zero, one, and two.

(4) Count down to one, zero, borrow, nine, eight, and seven.

Note A: Clear overrides load, data, and count inputs .
. Note B: When counting up, count·down input must be high; when counting down, count-up input must be high.

7-87

•

~ .---------------------------------------------------------------------------~

en
,...

...J

Timing Diagrams (Continued)

~

:E

o
en
,...

L 193 Binary Counters
Typical Clear, Load and Count Sequences

~

...J

CLEAR---flL______________________________________________

:;

:E
o
N
en
,...

LOAO

...J

~

:E
o
N
en
,...

.COUNT

:;
:E

---++---1-1--,

UP

...J

COUNT
OOWN

o

---+-+--++--+-----------------+--.

QA

OUTPUTS
QC

QO

CARRY
BORROW
~~

1

14

15

0

1

21

-COUNTUP~

1

1

0

15

14

131

. - COUNT OOWN-'

CLEAR PRESET
TLlF16643·5

Sequence:
(1) Clear outputs to zero.
(2) load (preset) to binary thirteen.
(3) Cou!11 up to fourteen, fifteen, carry, zero, one, and two.
(4) Count down to one, zero, borrow, fifteen, fourteen, and thirteen.

Note A: Clear overrides load, data. and count inputs.
Not. B: When counting up, count-down input must be high; when counting down, count-up input must be high.

7-88

~National

~ Semiconductor

DM80L06 Quad 2-lnput NAND Gates with Resistive Pull Up
General Description

Features

These quad two-inpu.t NAND gates feature internally connected. 20 kf! pull-up resistors on the outputs_ The pinout is
the same as the very popular DM54L03/DM74L03. and
these devices provide the same "one-tenth-power technology" as well.

• Typical power dissipation
• Typical propagation delay

12mW
115 ns

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

8V
5.5V
- 65·C to 150 ·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should

not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram
Dual-In-Line Package

Vee

84

A4

83

Y4

A3

Y3

10

7

At

Yl

81

A2

82

Y2

GND
TL/F/6644·1

DM80L06(N)

Y=AB
Inputs

B

Y

L
L
H
H

L
H
L
H

H
H
H
L

H = High Logic Level
L

Output

A

=Low Logic Level
7-89

Recommended Operating Conditions
Sym

DM80L06

Parameter

Min

Nom

Max

4.75

5

5.25

Units
V

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current

-0.2

mA

IOL

Low Level Output
Current

3.6

mA

TA

Free Air Operating
Temperature

70

·C

V

2
0.7

0

Electrical Characteristic.s

V

over recommended operating free air temperature (unless otherwise noted)

Sym

Parameter

Conditions

VOH

High Level Output
Voltage

Vee=Min
IOH=Max
VIL=Max

VOL

Low Level Output
Voltage

Vee=Min
IOL= Max
VIH = Min

II

Input Current@Max
Input Voltage

IIH

Min

Typ
(Note 1)

2

2.5

Max

Units
V

,

0.4

V

Vee = Max, VI =5.5V

0.1

mA

High Level Input
Current

Vee = Max, VI = 2.4V

10

p.A

IlL

Low Level Input
Current

Vee = Max, VI = 0.3V

los

Short Circuit
Output Current

Vee=Max

leeH

Supply Current With
Outputs High

Vee = Max

leeL

Supply Current With
Outputs Low

Vee = Max

Switching Characteristics

-0.17
-

-0.12

-0.18

mA

-0.25

-0.33

mA

0.48-

0.8

mA

2.4

3.68

mA

at Vee=5V and TA =25·C (See Section 1 for Test Waveforms and Output Load)
RL=4 k!l

Parameter

CL=15 pF

Units

Typ

Max

t PLH Propagation Delay
Time Low to High
Level Output

193

290

ns

tpHL Propagation Delay
Time High to Low
Level Output

37

56

ns

Min

Note 1:

All typical. are at Vee=5V, TA';25·e.

,
7-90

,

c

s:

~National

~
r-

~ Semiconductor

eg

=
C
s:
~
r-

DM70L98/DM80L98 TRI-STATE® Hex Buffers

eg

=

General Description

Features

These devices provide six, two-input buffers in each
package_ One of the two inputs to each buffer is used as a
control line to gate the output into the high-impedance
state, while the other input passes the data through the
buffer_ On this device, four buffers are enabled from a
common line, and the other two buffers from a separate
common line_ The outputs are placed in the TRI-STATE
condition by applying a high logic level to the control pins_
With the low power versions 01 these circuits, it is possible
to connect over 100 like devices to a common bus line and
still have adequate drive capability_

• Typical power dissipation 1S mW
• Typical propagation delay 3'1 ns
• Pin equivalent to DMS4368 (98)

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

8V
S,SV
- 6S·C to 1S0·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric value's defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table (Each Driver)

Connection Diagram
Dual-In-Line Package

Inputs

vee

02

A6

V6

AS

VS

A4

01

At

V1

A2

Y2

A3

V3

Y4

Output

G

A

Y

H

X

Hi-Z

L
L

H

L

L

H

L ~ Low Logic Level
H ~ High Logic Level

GND

Hi-Z ~ High Impedance (Off) State
TLlF/6645·1

DM70L98 (J)

7-91

DM80L98(N)

Recommended Operating Conditions
,
l:lym

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

High Level Output
Current

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

. Parameter

VOH
VOL

DM8DL98

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

Units
V
V

2

2
D.7

-1

2
125

-55

V

0.7

-1

Electrical Characteristics
Sym

DM7DL98
Min

0

mA

3.6

mA

70

·C

over recommended operating free air temperature (unless otherwise noted)
Typ
(Note 1)

Conditions

Min

High Level Output
Voltage

Vee=Min,loH=Max
VIL = Max, VIH = Min

2.4

Low Level Output
Voltage

Vee=Min
IOL=Max
VIL = Max
VIH=Min

II

Input Current@Max
Input Voltage

Vee = Max, VI = 5.5V

1

mA

IIH

High Level Input
Current

Vee = Max, VI=2.4V

10

p.A

IlL

Low Level Input
Current

Vee = Max
VI =0.3V

A (Note 3)

-10

mA

A (Note 4)

-0.18

G

-0.18

10ZH

Off·State Output
Current with High
Level Output
Voltage Applied

Vee = Max, Vo=2.4
V IH = Min, VIL = Max

10

p.A

IOZL

Off-State Output
Current with Low
Level Output
Voltage Applied

Vee= Max, Vo=0.3
VIH = Min, VIL = Max

-10

p.A

los

Short Circuit
Output Current

Vee= Max
(Note 2)

mA

Icc

Supply Current

=

Max

V

DM70

0.3

DM80

0.4

DM70

-3

-15

DM80

-3

-15

. Vee= Max

3

=

Nol. 1: All typlcals are at Vee SV, TA 2S'e.
Note 2: Not more than one output should be shorted at a time.

Nol.3: Both G Inputs at 2V.
Nol. 4:. Both G inputs at O.4V.

7-92

Units

4.5

V

mA

c

Switching Characteristics

at Vee = 5V and TA = 25"C (See Section 1 for Test Waveforms and Output Load),

C L =5 pF
Min

Typ

CL=50 pF

Units

Typ

Max

tpLH Propagation Delay
Time Low to High
Level Output

26

48

tpHL Propagation Delay
Time High to Low
Level Output

35

53

ns

tPZH Output Enable Time
to High Level Output

42

90

ns

tpZL Output Enable Time
to Low Level Output

42

75

ns

Max

~

reg

RL=4 k!l
Parameter

:s:

Min

ns

-:s:
CO

c

~

reg

CO

tpHjZ Output Disable Time
from High Level Output

25

43

ns

tpLZ Output Disable Time
from Low Level Output

34

63

ns

,

l

7-93

~National

~ Semiconductor
DM71 L22/DM81 L22, DM71 L23/DM81 L23 Quad 2-lnput
Data Selectorsl Multiplexers
General Description

Features

These devices contain four, two-input multiplexers with
common input select logic and common output disable
circuitry_ The DM71 L22/81l22 provides conventional
totem-pole output TIL construction, whereas DM71 L23/
81 L23 provides TRI-STATE® outputs_ When the
enable/strobe input is ala low logic level, the outputs of all
devices are conventional TIL However, when the enable/
strobe input is raised to a high logic level, the outputs of
the DM71 L22/81 L22 go to the low logic state, and the outputs of the DM71 L23/81 L23 go to the high-impedance
third state_ These devices provide the designer with TRISTATE and/or low power pin/pin replacements for the
popular 9322 and 54/74157 multiplexers_

•
•
•
•

Pin equivalents popular 9322 and 54/74157 multiplexers
Both conventional TIL and TRI-STATE outputs available
Typical propagation delay 40 ns
Typical power dissipation
l2215mW
l2320mW

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

(Note 1)

8V
5_5V
-65'Cto150'C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table arB not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
'define the conditions for actual device operation.

function Tables

Connection Diagram
Dual-In-Line Package
L22

INPUTS

Inputs Output
Strobe Select f--.-y
A .,B
L
L
L
L
H

L
L
H
H
X

L
H
X
X
X

L
L
L
L
H

L
L
H
H
X

Vec

15

116

INPUTS

B4

A4
14

13

OUTPUT
Y4

A3

12

OUTPUT
Y3

B3

11

t-

r--

~~

9

10

L
H
L
H
L

X
X
L
H
X

L23
- Enable Select

STROBE
G-

Output

A

B

y

L
H
X
X
X

X
X
L
H
X

L
H
L
H
Hi-Z

L = Low Logic Level
H= High Logic Level
X= Either Low or High LogiC Level
Hi·Z= High Impedance (Off) State

2
S
SELECT

A1

3
.Bl

4
Yl
OUTPUT

INPUTS

5
A2

6
B2

Y2
OUTPUT

18
GND

INPUTS

'Enable for 'L23

TLfFf6646-1

71L22 (J)
71L23 (J)

7-94

7

81L22(N)
81L23(N)

I

Recommended Operating Conditions

~

DM81L22

DM71L22
Sym

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

V IL

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

TA

Free Air Operating
Temperature

Min

Nom

Max

Min

Nom

Max

45

5

5.5

4.75

5

5.25

2

Units

V

2

V

0.7

0.7

-0.2

-0.2

mA

3.6

mA

70

DC

2
-55

125

0

V

'L22 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Conditions

Min

Typ
(Note 1)

High Level Output
Voltage

Vee=Min,loH=Max
VIL=Max, VIH=Min

2.4

2.8

Low Level Output
Voltage

Vee=Mln
10L= Max
VIL= Max
VIH= Min

II

Input Current@Max
Input Voltage

Vee = Max, VI = 5.5V

0.1

mA

IIH

High Level Input
Current

Vee = Max, VI =2.4V

10

p.A

IlL

Low Level Input
Current

Vee = Max, VI=0.3V

los

Short Circuit
Output Current

Vee = Max
(Note 2)

Supply Current

Vee = Max
(Note 3)

Sym

Parameter

VOH
VOL

lee
Note 1:

DM71

0.15

0.3

0.2

0.4

,

.

mA
mA

-3

-15

DM81

-3

-15

All typicals are at Vee =5V, TA =25°e.
lee is measured with all inputs grounded, and all outputs open.

7-95

V

-0.18

DM71

3

Units

V

DM81

Note 2: Not more than one output should be shorted at a time.

Note 3:

Max

4

mA

C")

C\I

...I

.,...

'1,.22 Switching Characteristics at Vee=5V and TA =25·C

:e

(See Section 1 for Test Waveforms and Output Load)

co

-,...
c

RL=4 kll

C ")

C\I

Parameter

....I

.,...

:e
c

~
.,...

co

:e

-,...
c

C\I
C\I

....I

.,...

:e
c

-,

CL =50 pF

Conditions
Min

iyp

Max

Units

tpLH Propagation Delay
Time Low to High
Level Output

Data
to
Output

20

40

80

ns

tpHL Propagation Delay
Time High to Low
Level Output

Data
to
Output

20

40

80

ns

tpLH Propagation Delay
Time Low to High
Level Output

Strobe
to
Output

30

60

120

ns

tpHL Propagation Delay
Time High to Low
Level Output

Strobe
to
Output

30

60

120

ns

tpLH Propagation Delay
Time Low to High
l,.evel Output

Select
to
• Output

35

70

140

ns

tpHL Propagation Delay
Time High to Low
Level Output

Select
to
Output

25

50

100

ns

Recommended Operating Conditions
Sym

Parameter

Vee

Supply Voltage

V1H

High Level Input
Voltage

V1L

Low Level Input
Voltage

10H

High Level Output
Current

IOL

Low Level Output
Current

TA

Free Air Operating
Temperature

DM81L23

DM71L23
Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

.

V
0.7

-0.2

-0.2

mA

3.6

mA

70

·C

125

7·96

V

0.7

2
-55

Units

0

V

c
.....

s:
......

'L23 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)

~

-s:
N

Sym
VOH
VOL

Parameter

Conditions

High Level Output
Voltage

Vee = Min, IOH = Max
VIL = Max, VIH = Min

Low Level Output
Voltage

Vee=Min
IOL=Max
Vll=Max
VIH= Min

Min
2.4

Typ
(Note 1)

Units

Max

2.8

V

DM71

0.15

0.3

DM81

0.2

0.4

,

V

r-

N

C

s:
......
.....

r-

-s:
N

Vee = Max, VI = 5.5V

IIH

High Level Input
Current

Vee=Max, VI=2.4V

III

Low Level Input
Current

Vee = Max, VI = 0.3V

IOZH

Off·State Output
Current with High
Level Output
Voltage Applied

Vee=Max, Vo=2.4V
VIH = Min, Vil = Max

20

IOZl

Off·State Output
Current with Low
Level Output
Voltage Applied

Vee = Max, Vo=0.3V
VIH = ~in, Vil = Max

-40

p.A

los

Short Circuit
Output Current

Vee = Max
(Note 2)

mA

Supply Current

Vee= Max
(Note 3)

Ice

.....

~N

Input Current@Max
Input Voltage

II

C

CO

0.1

mA

Co)

C

10

p.A

-0.18

DM71

-3

-15

DM81

-3

-15
4

Note 1: Aillypicals are al Vee=SV, TA=2S"e.
Note 2: Not more Ihan one outpul should be shorled at a time.
Note 3: ICC is measured with all inputs grounded, and all outputs open.

7·97

5.3

mA

.

p.A

mA

CO
.....

~

CO)

N

...J

.....
co

:::E
c

-

'L23 Switching Characteristics at Vee = 5V and TA = 25°C
(See Section 1 for Test Waveforms and Output Load)

CO)

N

...J

.....

.....
:::E
c

~
.....
co

:::E

c

~

...J

.....
.....

:::E
c

Parameter

From
(Input)
To
(Output)

RL=4 kG
CL=5 pF
Min

Typ

CL=50 pF
Max

Units

Min

Typ

Max

tpLH Propagation Delay
Time Low to High
Level Output

Data
to
Output

20

40

80

ns

tpHL Propagation Delay
Time High to Low
Level Output

Data
to
Output

20

40

80

ns

tpLH Propagation Delay
Time Low to High
Level Output

Select
to
Output

35

70

140

ns

tpHL Propagation Delay
Time High to Low
Level Output

Select
to
Output

25

50

100

ns

tPZH Output Ena~le
Time to High
Level Output

Output
Control
to Q

15

30

60

ns

tPZL Output Enable
Time to Low
Level Output

Output
Control
to Q

20

35

70

ns

tpHZ Output Disable
Time from High
Level Output

Output
Control
to Q

15

30

60

ns

tpLZ Output Disable
Time from Low'
Level Output

Output
Control
toO

35

75

100

ns

",

7·98

c
3:
.........

Logic Diagrams

rI\)

I\)

C

3:

L22
B4

A4

(13)

B3

(14)

A3

(10)

(11)

A2

B2
(6)

Bl

Al

(3)

(5)

(2)

co
....
rI\)
j\)

c
3:
.....
....
r-

I\)
(,.)

C

Vee = Pin 16
GND = Pin 8

3:

....

CO

r-

I\)
Co)

Y4

Y3

Yl

Y2

TLlF/6646·2

L23
B4
(13)

A4

B3

(14),

(10)

A3
(11)

B2
(6)

A2
(5)

Bl

Al
(3)

(2)

Vee = Pin 16
GND = Pin 8

Y4

Y3

Y2

Yl
TLlF16646-3

7-99

~National

~ Semiconductor

DM75L51/DM85L51 TRI·STATE@ 4·Bit D Type Registers
General Description

Features

These four-bit registers contain Ootype flip-flops with
totem-pole TRI-STATE outputs, capal?le of driving highly
capacitive or low-impedance loads. The high-impedance
state and increased high-logic-level drive provide these
flip-flops with the capability of driving the bus lines in a busorganized system without need for interface or pulI;up
components.

• TRI-STATE outPUtS interface directly with system bus
• Gated output control lines for enabling or disabling the
outputs

Gated enable inputs are provided for controlling the entry of
data into the flip-flops. When both data-enable inputs are
low, data at the 0 inputs are loaded into their respective
flip-flops on the next positive transition of the buffered
clock input. Gate output control inputs are also provided.
When both are low, the normal logic states of the four outputs are available for driving the loads or bus lines. The
outputs are disabled independently 'from the level of the
clock by a high logic level at either output control input. The
outputs then present a high impedance and neither load nor
drive the bus lines. Detailed operation is given in the truth
table.

• Fully independent clock eliminates restrictions for operating, in one of two modes:
Pa~allel load
Do nothing (hold)
• For application as ~us buffer registers
._ Typical propagation delay 59 ns
• Typical frequency 15 MHz
• Typical power dissipation 27.5 mW

Absolute Maximum Ratings (Note 1)
8V

Supply Voltage
Input Voltage

5.5V

-65·Cto150·C

Storage Temperature Range

To minimize the possibility that two outputs will attempt to
take a common bus to opposite logic levels, the output control circuitry is designed so that the average output disable
times are shorter than the average output enable times.

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram

Function Table

Dual-In-Line Package
OATAENABLE
INPUTS

VCC

r

CLEAR

16

15

01

02

14

03
1'3

fnputs

.

OATAINPUTS
D4

12

11

12
10

G\1g

Clear

Clock

H
L
L
L
L
L

X
L

tf

t
t
t
t

Data ' Enable

Data

G1

G2

0

X
X
H
X
L
L

X
X
X
H
L
L

X
X
X
X
L
H

Output
Q
L

00
00
00
L
H

When either M or N (or both) is (are) high the output is disabled to the highimpedance state; however, sequential operation of the flip-flops is not
affected.
H
L

P

M

2
N,

OUTPUT
CONTROL

3

4

5

6

\-.;Q:::.1:......---:Q::2~,.....;Q=3:......_.::Q~4/
OUTPUTS

t=

7

X

low-to· high level transition

= don't care (any input Including transitions)
= the level of a before the indicated steady state input conditions were

00

CLOCK

established

TLlFI6647-1

75L51 (J)

= high level (steady state)
= low level ,(steady state)

85L51 (N)
7-100

c
3:
....,

I

Recommended Operating Conditions

(II

DM75L51
Sym

Parameter

Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

10H

High Level Output
Current

10L

Low Level Output
Current

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units
V
V

2
0.7

V

-1

-1
2

mA

3.6

mA

6

MHz

feLK

Clock Frequency
Pulse Width Clock or Clear

100

100

ns

tsu

Setup Time

Enable

45

45

ns

Data

30

30

tH

Hold Time

Enable

0

0

Data

10

10

tREL

Clear Release Time
Free Air Operating
Temperature

0

Parameter

VOH
VOL

6

0

30

ns

30

-55

Electrical Characteristics
Sym

125

ns
·C

70

0

over recommended operating free air temperature (unless otherwise noted)
Typ
(Note 1)

Units

Conditions

Mi,n

High Level Output
Voltage

Vee = Min, 10H = Max
VIL = Max, VIH = Min

2.4

Low Level Output
Voltage

Vee=Min
10L= Max
VIL= Max
VIH= Min

II

Input Current@Max
Input Voltage

Vee = Max, VI = 5.5V

0.1

IIH

High Level Input
Current

Vee = Max, VI = 2.4V

10

IlL

Low Level Input
Current

Vee=Max, VI=0.3V

10zH

Off·State Output
Current with High
Level Output
Voltage Applied

Vee = Max, Va = 2.4V
VIH = Min, VI'l = Max

20

ItA

10Zl

Off·State Output,
Current with Low
Level Output
Voltage Applied

Vee=Max, Va = 0.3V
VIH = Min, VIL = Max

-40

p.A

los

Short Circuit
Output Current

Vee=Max
(Note 2)

mA

Supply Current

Vee= Max
(Note 3)

lee
Note 1:

All

typicals are at

.

-........,
c
3:

(II

r-

....

(II

0.7

tw

TA

r(II

DM85L51

Max

,

DM75

0.15

0.3

DM85

0.2

0.4

-0.18

DM75

-3

-15

DM85

-3

-15
5.5

9

V
V

.

mA
p.A
mA

mA

Vee=5V, TA=25"e.

Note 2: Not more than one output should be shorted at a time.
Note 3: ICC is measured with all outputs open; CLEAR grounded following momentary connection to 4.5V; N, G1, G2, and all DATA inputs grounded; and
the CLOCK and M at 4:5V.

7·101

,...

~

Ie

Switching Characteristics

:E

c
,...

II)

Parameter

..J

Ie

:E
c

at Vee

From
(Input)
To
(Output)

=5V and TA =25'C (See Section 1 for Test Waveforms and Output Load)
RL=4 kG
CL=5 pF
Min

Typ

CL=50 pF
Max

f MAX Maximum Clock
Frequency

Min

Typ

6

15

Units
Max

MHz

. tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
Output

39

70

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
Output

77

120

ns

tpHL Propagation Delay
Time High t6 Low
Level Output

Clear
to
Output

72

110

ns

tpZH Output Enable
Time to High
Level Output

Output
Control
toO

28

55

ns

tPZL Output Enable
Time to Low
Level Output

Output
Control
toO

35

60

ns

tpHZ Output Disable
Time from High
Level Output

Output
Control
to a

18

50

ns

tpLZ Output Disable
Time from Low
Level Output

Output
Control
to a

32

75

ns

,

7-102

c

:s:
......

Logic Diagram

CII

r-

....

-:s:c
CII

OUTPUT {M
CONTROL
N

......
r-

-""""",L-_

CII

....

CII
DATA _(1_4_)- - - - - - - _ 4 - -.......

>---~D

o

Dl

DATA
ENABLE

r--(»CLOCK

{G,-/-,:-)).rr-,

G2 -""",11......_

CLEAR

o~--I--I

o

DATA (13)

D2------~---1---r-~
"--I-O>CLOCK

02
CLOCK

DATA _(1_2_)-----l~--_4---I.......
D3
.....f-O>CLOCK

CLEAR

DATA (11)

~----~~----~~

>-+--4--4

ot--~I--I

03

D

CLOCK

CLEAR

ot-----t

TLlF/6647·2

7-103

~

~ ~National

c ~ Semiconductor

:E

~

DM75L52/DM85L52, DM75L541 DM85L54 TRI·STATE®

Ie Synchronous Counters/Latches
:E
c

fi

...J

It)

co
:E
c

~
...J
Ie

:E
c

General Description
These circuits logically combine the functions of counters
for frequency division, latches to store the data from the
counters, and output buffer gates which provide both standard TTL outputs as well as high-impedance outputs for
multiplexing of data. The counters are fully synchronous,
and are made up of four edge-triggered JK flip-floP!!. To further facilitate operation, the Count Mode ·and Terminal
Count outputs are also operable when the data outputs are
in the high-impedance state or the latch mode.

• Typical power dissipation 38 mW
• Typical clock frequency 11 MHz

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

BV
5.SV
-65·Ct0150·C

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.
'

Features
• DM75L52/85L52
• DM75L54/85L54

(Note 1).

Decade counter /latch
Binary counter /latch

Connection Diagram
Dual-In-Line Package
TRANSFER
VCC ENABLE

116

CP

15

PRESET CLEAR

14

13

CEP

NC

CET

10

11

12

9

2
001

002

'--r----'
OUTPUT
DISABLES

\

~

5

4

3
0

C

B

7

A

TERM.
COUNT

OUTPUTS

18
GND

TlIFl'664B·'

75L52(J)
.75L54(J)

Function Table

85L52(N)
85L54(N)

Inputs

001 OD2 CEP CET
H
X
L
L
L
L

X
H
L
L
L
L

X
X
X
X
X
H

Outputs

Clear

Preset

TE

X
X
H
L
X
L

X
X
X
H
X
L

X
X
H
H
L

X
X
X
X
X
H

I-!

A

I

B

I

C

I

D

"High Impedance State"
"High Impedance State"
L
L
L
L
H
H
H
H
LATCH
COUNT

-Function of the count sequence.

7-104

TC
H = High Logic Level
L = Low Logic Level

L

X = Either Low or High Logic Level
TE = Transfer Enable
TC = Term. Count

c

s:

Recommended Operating Conditions

~

C1I

Sym
Vee

Supply Voltage

VIH

High Level Input
Voltage

VIL

DM75L52, L54

Parameter

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2
0.7

High Level Output Current
(Except Terminal Count Input)

10H

High Level Output
Current (Terminal Count)

feLK

Clock Frequency

TA

Free Air Operating
Temperature

0.7

V

-1

-1

mA

0.2

mA

2
0
. -55

Parameter

VOH

High Level Output
Voltage

Vee = Min
10L= Max
V IL = Max
VIH= Min

Low Level Output
Voltage

Vee= Min
IOL=Max
VIL = Max
'VIH = Min

3.6

mA

6

0

6

MHz

125

0

70

'C

Min

Conditions
DM75

2.4

DM85

2.4

Typ
(Note 1)

Max

Units
V

DM75

0.15

0.3

DM85

0.2

0.4

CET

0.2

Others

0.1

CET

20

Others

10

V

Input Current@Max
Input Voltage

Vee = Max
VI =5.5V

High Level Input
Current

Vee= Max
VI = 2.4V

Low Level Input
Current

Vee= Max
VI = 0.3V

IOZH

Off-State Output
Current with High
Level Output
Voltage Applied

Vce= Max, Vo = 2.4V
VIH = Min, VIL = Max

20

p.A

IOZL

Off-State Output
Current with Low
Level Output
Voltage Applied

Vee = Max, Vo=0.3V
VIH = Min, VIL = Max

-40

p.A

los

Short Circuit
Output C~rrent

Vee= Max
(Note 2)

mA

Supply Current

Vee= Max

IlL

lee
Nole 1:

r-

~
C

~

C1I

r-

-s:
.j:Ioo

CD

C1I

Sym

IIH

C1I

C

over recommended operating free air temperature (unless otherwise noted)

II

CD

C1I

0.2

'L52 and 'L54 Electrical Characteristics

VOL

-s:
C

V

s:

10H

Low Level Output
Current

Units

V

2

Low Level Input
Voltage

10L

DM85L52, L54

Min

r~

CET

-0:36

Others

-0.18

DM75

-3

-15

DM85

-3

-15
7.6

All typicals are at vee = 5V, TA=2S·e.

Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

7-105

13

mA

p.A

mA

mA

r~

'L52 and 'L54 Switching Characteristics
From
(Input)
To
(Output)

Parameter

-

at Vcc=5V and TA=25°C
RL=4 kll

C L =5 pF
Min

Typ

f MAX Maximum Clock
Frequency

CL=50 pF
Max

Min

6

11

Typ

Units
Max
MHz

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
Output

115

220

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
Output

75

150

ns

tpLH Propagation Delay
Time Low to High
Level Output

Transfer
Enable
to
Output

90

160

ns

Transfer
Enable
to
Output

90

160

ns

tpzH Output Enable
Time to High
Level Output

Output
Control
toO

75

150

ns

tPZL Output Enable
Time to Low
Level Output

Output
Control
to a

90

150

ns

tpHZ Output Disable
Time from High
Level Output

Output
Control
toO

8

15

ns

tpLZ Output Disable
Time from Low
Level Output

Output
Control
to a

57

105

ns

. tpHL Propagation Delay
Time High to Low
Level Output

,

-

,
7-106

c

s:
-.,

Mode of Operation

(J1

When the Transfer Enable (TE) is at a logical "I" level, the
data transfer paths between the counter outputs and the
output buffer gates are maintained. When the Transfer Enable is at a logical "0" level, the data transfer paths are
inhibited, and the state of the output buffer gates are
locked in by the latches. The counter and Terminal Count
(TC) output remain operable during this time.

• Clearing or presetting is enabled by taking the respective input to a log ice I "I" level.
• To enable the count mode both CET and CEP inputs must
be at a logical "I" level.
• To latch the outputs the Transfer Enable (TE) input must
be taken to the logical "0" level.
• To place the TRI-STATE outputs into the "third-state," either of the Output Disable (OD) inputs must be taken to
the logical "I" level.

Asynchronous Clear resets the counter to 0000.
I

Asynchronous Preset sets the counter to 1111. The 1111
state may be used in the L52 for blanking out leading
zeroes in visual displays. The next clock pulse will advance the L52 to 0001 which denotes the first count of the,
~6~~ed zero.,The next clock pulse will advance the L54 to

The clock input must be high during the high to low transition of CEP and/or CET for correct logic operation. The
CEP and CET inputs may be used in a high speed look
ahead technique.
Counter stages can be cascaded to provide multiple stage
BCD or Binary synchronous counting by using the L52 or
the L54, respectively. With a Terminal Count(TC) fan out of
ten, eleven stages are able to operate at the maximum frequency equivalent to a two stage counter.

The Terminal Count (TC) output is active high when the
counters are at terminal count and the CET is high. The
Terminal Count logic equations are:
(L52) TC = CET • A • B• C. D
(L54) TC = CET • A • B • C • D

• The counters change state on the positive-going transition of the clock.

The characters displayed can be held with a low level on
the TE input while the counters can continue counting. The
display can be updated at any time by applying a positive
pulse to the TE input.

DM75L52/DM85L52
DECADE COUNT SEQUENCE

DM75L54/DM85L54
BINARY COUNT SEQUENCE

The following logic levels control the device:

Outputs

Count
0
1
2
3
4
5
6
7
B

9
··If Preset
Applied
Next
Count

B

C

D

TC

L
H
L
H
L
H
L
H
L
H

L
L
H
H
L
L
H
H
L
L

L
L
L
L
H
H
H
H
L
L

L
L
L
L
L
L
L
L
H
H

L
L
L
L
L
L
L
L
L
H

H
H

H
L

H
L

Outputs

Count

A

H
L

0
1
2
3
4

5
6
7
B
9
10
11
12
13
14
15

L
L

• *The 111 slate may be used In conjunction with certain ,decoder/drivers
(DM7446A, 7447A, 7448) for blanking leading zeroes.

7-107

A

B

C

D

TC

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
L
L
L
L
L

L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H

~
H
H
H
H
H.
H
H
H

r(J1

-s:
N

C

00
(J1

r(J1
,!')

C

s:
-.,
(J1

r(J1

-s:
~

C

00
(J1

r(J1
~

Logic Diagram$

L52
TERMINAL
COUNT
OUTPUT
(7)

OUTPUT

DISABLES {2}

o

o

ReSET

RESET

01-++----'

RESET

COUNT
ENABLE (9)

TRICKLE

E~~~~~ (10)

TLfF/6648·2

L54
TERMINA1.
COUNT
OUTPUT

OUTPUT

(7)

(1)

OUTPUT
DISABLES
(2)

TRANSFER (15)
ENABLE

K

o

0

RESET

RESET

COUNT

ENABLE(9}
TRICKLE

:!~~~(10)

TL/F/6648-3

7·108

0

3:
....,

Switching Time Waveforms
L52.L54

n
I \

in

CP

-

~

I

n

n\

J

3V

L-

1.3 V

OV

-Ip(clock)

3V

J\

PRESET

1.3V
OV

-

I-- Ip(PRESET)

\

1.3 V

~

- ~IP(CLEAR)

OV

'\

I

-'---

3V

I

\

\

.

1.3 V

J

OV

I-- IR(CE)

IS(CE)

3V
1.3 V

TE

if .

\

VOH

II

1

\

OUTPUTS

I
--:-

tpLH

r--

I.

1-----

IpdS

1.3 V

VOL

I-- ---,lpdR I - TLlFI6648·4

~----_3V

3V

- - - / - - - - - - - 1 . 3 V-TE

1.3 V

------'t--------OV

OV

~----VOH

\

---+--+-----1.3V

-

1'--tpHL
(TE)

I-TLlF16648·5

7·109

N

0

3:
co
en
I"""
en

~N

0

3:
....,

en
I"""
en

0

3:
co
en
I"""
en
01:00

\

CE

-

01:00

3V

1/

CLEAR

en
I"""
en

Switching Time Waveforms

(Continued)

1HZ

.

-t~

OV

3V

1.3V

~-

ACTUAL
LOGICAL "1"
VOLTAGE

TLlF/6648·6

tLZ

±ur.

OV

3V
1.3 V

OUTPUT~

ACTUAL
LOGICAL"a'
VOLTAGE

f
TLlF/664B·7

IZH

IZL
3V

INPUT

INPUT

\
1.3V
OV

OUTPUT

I--

IZH

r

J

IZL

3V

1.3V

r--

OUTPUT

\

1.3V

I

1.3V

'\
TLlF/B64B·B

\

7"110

TLlF/664B·9

.
~ Semiconductor

~National

DM75L60/DM85L60, DM75L63/DM85L63 Synchronous 4-Bit
Up/Down Decade/Binary Counters
General Description

Features

These circuits are synchronous up/down counters; the
L60 circuit is a BCD counter and the L63 is a 4-bit binary
counter. Synchronous operation is provided by having all
flip-flops clocked simultaneously so that the outputs
change together when so instructed by the steering logic.
This mode of operation eliminates the output counting
spikes normally associated with asynchronous (rippleclock) counters.

•
•
•
•
•
•

Fully independent clear input
Synchronous operation
Cascading circuitry provided internally
Individual preset for each flip-flop
Typical count frequency 12 MHz
Typical power dissipation 40 mW

The outputs of the four master-slave flip-flops are triggered
by a low-to-high level transition of either count (clock) input. The direction of counting is determined by which count
input is pulsed, while the other count input is held high.
All four counters are fully programmable; that is, each output may be preset to either level by entering the desired
data at the inputs while the load input is low. The output will
change independently of the count pulses. This feature allows the counters to be used as modulo-N dividers 'by simply modifying the count length with the preset inputs.
A clear input has been provided which, when taken to a high
level, forces all outputs to the low level; independent of the '.
count and load inputs. The clear, count, and load inputs are
buffered to lower the drive requirements of clock drivers,
etc., required for long words.

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

"Electrical Characteristics" table "are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Dual-In-Line Package

15

14·

13

12

'4

5

INPUTS
LOAD

DATA DATA
0'
C

11

10

9

-

3

OATAB
INPUT

OB

QA

OUTPUTS

- 6S·C to 1S0·C

not be operated at these limits. The parametric values defined in the

INPUTS
OUTPUTS
'DATA
A
CLEAR BORROW CARRY

116

8V
S.SV

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. The device should'

Connection Diagram

vcc

(Note 1)

COUNT COUNT
DOWN UP

7

6

Oc

00

18
GNO

OUTPUTS

INPUTS
TLfF/6649·1

DM75L60(J)
DM75L63(J)

DM85L60(N)
DM8SL63(N)

7-111

('I)

co

....I

~

Recommended Operating Conditions

:IE

-

Sym

Parameter

Vcc

Supply Voltage

.....
:IE

VIH

High Level Input
Voltage

V IL

Low. Level Input
Voltage

co

10H

c

High Level Output
Current

10L

Low Level Output
Current

c

DM75L60, L63

( 'I)

~
II)

c

g
....I

II)

:IE

o

CO
....I

~

:IE

c

DM85L60, L63

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

Units
V
V

2

V

0.7

0.7

-0.2

-0.2

mA

3.6

mA

6

MHz

2

fCLK

Clock Frequency

0

tw

Pulse Width of Any Input

70

6

70

0

ns

tsu

Data Setup Time

30

30

ns

tH

Data Hold Time

0

0

TA

Free Air Operating
Temperature'

125

-55

ns
70

0

'c

'LS60 and 'LS63 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)

.Sym

Parameter

Conditions

Min

Vcc=Min,loH=Max
VIL = Max, VIH = Min

2.4

Typ
(Note 1)

Max

Units

Vo H '

. High Level Output
Voltage

VOL

Low Level Output
Voltage

Vcc=Min
10L=Max
VIL=Max
V IH = Min

II

Input Current@Max
Input Voltage

Vcc = Max, VI = 5.5V .

0.1

mA

IIH

High Level Input
Current

Vcc = Max, VI = 2.4V

10

p.A

IlL

Low Level Input
Current

Vcc = Max, VI = 0.3V

los

Short Circuit
Output Current

Vcc=Max
(Note 2)

Supply Current

Vcc= Max
(Note 3)

Icc

V

DM75

0.15

0.3

DM85

0.2

0.4

-0.18

mA
mA

DM75

-3

-15

DM85

-3

-15
8

Nole 1: Aillypicals are al VCC=5V, TA=25·C.
Nole 2: Nol more Ihan one output should be shorted at a time.
Nole 3: ICC is measured with all outputs open, CLEAR and LOAD Inputs grounded, and all other inputs at 4.5V.

7·112

V

13

mA

c

'LSO and 'LS3 Switching Characteristics

3:
......
U1
r0)

at Vee = 5V and TA = 25°C

(See Section 1 for Test Waveforms and Output Load)

Parameter

-c
o

From
(Input)
To
(Output)

RL=4 kn
C L =50 pF
Min

f MAX -Maximum Clock
Frequency

6

Typ

Units

12

3:
Q)
U1

Max

r-

0)

ns

~o

3:
......
U1
r0)

C

tpLH Propagation Delay
Time Low to High
Level Output

Count Up
to
Carry

30

60

ns

tpHL Propagation Delay
Time High to Low
Level Output

Count Up
to

60

120

ns

tpLH Propagation Delay
Time Low to High
Level Output

Count Down
to
Borrow

30

tpHL Propagation Delay
Time High to Low
Level Output

Count Down
to
Borrow

50

100

ns

tpLH Propagation Delay
Time Low to High
Level Output

Either Count
to

45

90

ns

tpHL Ptopagation Delay
Time High to Low
Level Output

Either Count
to

75

150

ns

tpLH Propagation Delay
Time Low to High
Level Output

Load
to

55

110

ns

t PHL Propagation Delay
Time High to Low
Level Output

Load
to

105

200

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clear
to

95

190

ns

Co)

c

3:
Q)

Car~y

60

ns

U1

r-

0)
Co)

Q

Q

Q

Q

Q

(

7·113

Logic Diagrams
L60

('3) B ORROW

0 UTPUT

I

('2) C ARRV'

r
DATA ('5)
INPUT A

DOWN
COUNT

0 UTPUT

r-'

(4)

~

(3)

OA

OUTPUTaA

T

~

-

DATA (')
INPUTS

r'-'"
~

c

6T
,-L

~
Jo-

DATA ('0)
INP!IT

r-

QA

UP (5)
COUNT

(2)

Os

OUTPUT Os

T

wQS

:no

r-

r-'

~
-

(6)

OUTPUTOC

Oc
T
QC

::r--P

I-

tnT

DATA
INPUT 0

(9)

('4)
CLEAR

--,
r--"
'----i
(7)

.---

QD

(1,)

-I

LOA0

OUTPUT aD

aD
T

t--

~.
TLlF/6649·2

7·114

.-------------------------------------------------------~c

Logic Diagrams

3:
......

(Continued)

C11

L63

(13) BORROW
OUTPUT

J

~

c

3:
Q)
C11

(12) CARRY
OUTPUT

DATA (15)
INPUT A

3:
......

~

C11

(3)

OA

OUTPUTOA

T
UP (5)
COUNT

.-

QA

~

(2)

OUTPUT OB

OB
T

1

:r--FDATA (10)
INPUTC

wQB

~

r-

1-

1--1

(6)

OUTPUT Oc

Oc
T
QC

-

:Jp
DATA (9)
INPUT 0
(14)
CLEAR

I-

b-)T

----- "
r--'"
'-"""--;
(7)

OUTPUT 00

00
T
QO

r-

:r--F-~

(11)
LOAD

TL/ F16649·3

7·115

Co)

3:

--.L

-L

-

m
r-

:JJo- tt)T
~

rC)

c

r-

DATA (1)
INPUT B

~
C

r-r

DOWN (4)
COUNT

r-

Timing Diagrams
L60 Decade Counters
Typical Clear, Load and Count Sequences

CLEAR~
LOAD
A

B'

L...-

I

DATA
C

L...-

I
.---

D
COUNT
UP
COUNT
DOWN
QA

OUTPUTS

..----...~

CLEAR

PRESET

I

8

9

0

1

21 1

- C O U N T UP-------J

r-'
1

-

0

9

8

71

COUNT OOWN---------'

TLIF/6649·4

Sequence:
(1)
(2)
(3)
(4)

Clear outputs to zero.
Load (preset) to BCD seven.
Count up to eight, nine. carry, zero, one, and two.
Count down to on., zero, borrow, nine. eight. and seY~n.

Not. A: Clear overrides load, data, and count inputs.
Not. B: When' counting up, counl-down input must be high; when counting
dow,... count-up Input must bo high.

7-116

~----------------------------------------------------------------'C

Timing Diagrams

s::
....,

(Continued)

C1I

r-

-s::
g

L63 Binary Counters
Typical Clear, Load and Count Sequences

C

(lC)

CLEAR

C1I

---.l"l

r9

en

LOAD

C

s::
....,

A

C1I

r-

en

-

B

Co)

DATA

C

3:
(lC)

C

C1I

r-

D

en
Co)

COUNT
UP
COUNT
DOWN
OA

OB
OUTPUTS
Oc

OD
CARRY

BORROW

10 1

1131

r - - " - - . ,---.-..
CLEAR
PRESET

15

0

21 1

COUNT U P ' - - - -

Sequence:
(1) Clear outputs to zero.
(2) Load (preset) to binary thirteen.
(3) Count up to fourteen, fifteen, carry, zero, one, and two.
(4) Count down to one, zero, borrow, fifteen, fourteen. and thirteen.
Nota A: Clear overrides load, data. and count inputs.

Note B: When counting up. count-down input must be high; when counting

down. count-up input must be high.

7-117

1

0

15

14

13

1

. -COUNT DOWN-----'

TLlF/6649·5

~

~ ~National
:E ~ Semiconductor
c

~ DM76L70/DM86L70 8·Bit Serial
~ In/Parallel Out Shift Registers

c

General Description
These 8-bit shift registers feature gated serial inputs and
an asynchronous clear. A low logic level at either input inhibits entry of the new data, and resets the first flip-flop to
the low level at the next clock pulse, thus providing complete control over incoming data. A high logic level on either
input enables'the other input, which will then determine the
slate of the first flip-flop. Data at the serial inputs may be
changed while the clock is high or low, but only information
meeting the setup requirements will be entered. Clocking
occurs on the low-to-high level transition of the clock input.

• Typical clock frequency 14 MHz
• Typical power dissipation 30 mW

Features

Note 1: The "Absolute Maximum Ratings" are those values beyond
which the safety of the device can not be guaranteed. T!1e device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute

• Gated (enable.! disable) serial inputs
• Fully buffered clock and serial inputs

Absolute Maximum Ratings

(Note 1)
8V

Supply Voltage
Input Voltage
Storage Temperature Range

5.5V
- 65'C to 150'C

maximum ratings. The "Recommt:!nded Operating Conditions" table will
define the conditions for actual device operation.

• Asynchronous clear

Connection Diagram
Dual-In-Line Package
QE

14

CLEAR

CLOCK

13

12

QD

10

QC

Q8

9

8

6

7

.......

2

S8
TL/F/665Q..1

76L70/86L70 (W)

Function Table
Inputs

Outputs

Clear

Clock

A

B

OA

OB

OH

L
H
H
H
H

X
L

X
X
H
L
X

X
X
H
X
L

L
QAO
H
L
L

L
QBO
QAn
QAn
QAn

L
QHO
QGn
QGn
QGn

t
t
t

H = High Level (steady state)
L = Low Level (steady state)
X .", Oon't Care (any input. including transltfons)

, = Transition from low to high level
QAO. QBO. QHO = The level of QA. QB' or QH. respectively. before the indicated steady state input conditions were established.
QAn. QGn = The level of QA or QG before the most recent, transition of the
clock; indicates a one-bit shift.

7-118

Logic Diagram
CLEAR~1~3

SERIAL
INPUTS

(AB

+-______

______-<~~__-4~______

~

______-+______

-4~

______+-______~______-'

5
6

OUTPUTS

TLlF/6650·2

Timing Diagram
Typical Clear, Shift, and Clear Sequences

LS

CLEARU

SERIAL
INPUTS

1

A

B-!-----.J
CLOCK

-,
-,

QA_~

QB_~

_ _~ _ _ _ _ _~
_ _ _ _ _ _ _ _ _ _--.J

QC:'L-____________

-.J

-,

QD_~

___________

~----.J

OUTPUTS

LrL

QE - ,

_~I------------------------------------~

OF~.Jl

,

_________________________________________J

-,

OG_.J'____________________________________________-.J

4-L
I

OH:'~I____________________________________~~

CLEAR

CLEAR

TLlF/6650-3

Recommended Operating Conditions
DM86L70

DM76L70
Sym

Parameter

Vee

Supply Voltage

V,H

High Level Input
Voltage

V,l

Low Level Input
Vc;>ltage

IOH

High Level Output
Current

IOl

Low Level Output
Current

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

2

V
V
V

0.7

0.7

-: 0.2

-0.2

rnA

3.6

rnA

2
7·119

Units

Recommended Operating Conditions
Sym

Min
fCLK

Clock Frequency
Pulse Width

DM86L70

DM76L70

Parameter

tw

(Continued)

Nom

0

Max

Min

6

Nom

0

6

I Clock

60

40

60

40

LClear

60

40

60

40

tsu

Data Setup Time

40

20

40

20

tH

Data Hold Time

20

-5

20

-5

TA

Free Air Operating
Temperature

125

-55

Max

Units
MHz
ns

ns
ns

0

70

·C

Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Sym

Parameter

VOH
VOL

II

IIH

IlL

los

Icc

Typ
(Note 1)

Conditions

Min

High Level Output
Voltage

Vcc = Min, 10H = Max
VIL = Max, VIH = Min

2.4

Low Level Output
Voltage

Vcc= Min
10L=Max
VIL = Max
VIH=Min

DM76

0.3

DM86

0.4

Input Current@Max
Input Voltage

Vcc=Max
VI=5.5V

Clear

0.2

Other

0.1

High Level Input
Current

Vcc= Max
VI=2.4V

Clear

20

Other

10

Low Level Input
Current

Vcc=Max
VI = 0.3V

Clear

-0.36

Other

-0.18

Short Circuit
Output Current

Vcc=Max
(Note 2)

. DM76

-3

-15

DM86

-3

-15

Supply Current

Vcc=Max
(Note 3)

Switching Characteristics

Max

Units
V

6

9

V

rnA

p.A

rnA

rnA

rnA

at Vcc=5V and T A =25·C (See Section 1 for Test Waveforms and Output Load)
RL=4 kO
C L =50 pF

From
(Input)
To
(Output)

Parameter

fMAX Maximum Clock
Frequency

Min

(Note 4)
Typ

6

14

Units
Max
MHz

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
Output

50

85

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
Output

90

135

ns

tpHL Propagation Delay
Time High to Low
Level Output
Not. 1: All typicals are at VCC = 5V. TA = 25°C.

Clear
to
Output

75

120

ns

Note 2: Not more than one output should be shorted at a time.

Not. 3: ICC is measured with outputs open.
Not. 4: CL = 15 pF for fMAX only.

SERIA~

inputs grounded. the CLOCK input at 2.4V. and a momentary ground. then 4.5V. applied to CLEAR.

7:120

.------------------------------------------------------------------,0
s:
......
~National

en
......

~ Semiconductor
DM76L75/DM86L75, DM76L76/DM86L76 Presettable
Decade/.Binary. Counters

r-

-s:
U1

o

co

en
......

r-

General Description

Features

,91

The!3e synchronous, presettable counters are true tenth·
power versions of the popular DM54160A/DM74160A,
DM54161A/DM74161A, DM9310, and DM9316 counters.
They feature an internal carry/look ahead for high·speed
cascading, and trigger on the positive·going transition of
the clock pulse. The counters are fully programmable; and,
since presetting is synchronous, applying a low logic level
to tlie load input disables the counter and forces the outputs to agree with the setup data after the next clock pulse,
regardless of the levels of the enable inputs. Low-to-high
transitions at the load inputs are acceptable, regardless of
the logic levels on the clock or enable inputs. The clear
(reset) function is asynchronous, and a low level applied to
the clear input sets all four outputs low regardless of the
levels on the clock, load, or enable inputs. In high-speed
cascading arrangements, both count-enable inputs (P, T)
must be high to count, and input T is fed forward to enable
the ripple carry output. This high-level overflow ripple carry
pulse can be used to enable successive stages. High-tolow level transitions at the P or T enable. inputs are
permitted, regardless of the logic level on the clock.

• Low power versions popular counters
DM76L75/DM86L75 = DM54160A/DM74160A,
DM9310-decade counter
DM76L76IDM86L76 = DM54161A/DM74161A,
DM9316-binary counter

s:
......

o

en

r-

~
o

-s:

• Internal look-ahead for fast cascading
• Counters are fully synchronous and presettable

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature Range

CO

33mW

• Typical power dissipation

(Note 1)

en
......
en

r-

BV
5.5V
- 65'C to 150'C

Note 1: The "Absolute Maximum Ratmgs" are those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined In the
"Electrical Characteristics" table are nct guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Connection Diagram
Dual-In-Line Package
OUTPUTS
TC
VCC OUTPUT

j16

15

00

01

14

03

02
13

CET

11

12

10

9

-c

2
CLEAR CLOCK

3
PO

4
Pl

5
P2

6
P3

7

18

CEP

GND

DATA INPUTS
TLlF/6651·1

76L75 (J)
76L76 (J)

86L75 (N)
86L76 (N)

7-121

•

Recommended Operating Conditions
~Sym

Vcc

Supply Voltage

VIH

High Level Input
Voltage

VIL

Low Level Input
Voltage

IOH

High Level Output
Current -

IOL

Low Level Output
Current

fCLK

Clock Frequency

tw

Pulse Width

tsu

tH

DM76L75, L76

Parameter

Setup Time

Hold Time

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

2

0

0.7

-0.2

-0.2

mA

3.6

mA

6

MHz

6

0

60

25

60

25

Reset

80

30

80

30

CE

65

40

65

40

Data

30

15

30

15

PE'

65

40

65

40

CE

80

'50

80

50

Data

30

15

30

15

65

40

65

40

-55

V

0.7

Clock

Free Air Operating
Temperature

Units

V

2

2

PE
TA

DM86L75, L76

Min

125

ns

ns

ns

70

0

V

·C

'L7S and 'L76 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Sym

Parameter

Conditions

Min

Typ
(Note 1)

2.4

3.1

Max

V

VOH

High Level Output
Voltage

Vcc=Min,loH=Max
VIL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vcc= Min
10L=Max'
VIL=Max
VIH = Min

Input Current@Max
Input Voltage

Vcc=Max
VI=5.5V

CET

0.2

Others

0.1

High Level Input
Current

Vcc=Max
VI = 2.4V

CET

20

Others

10

Low Level Input
Current

Vcc=Max
VI =0.3V

CET

-0.36

Others

-0.18

Short Circuit
Output Current

Vcc= Max
(Note 2)

DM76

-3

-15

DM86

-3:

-15

Supply Current

Vcc= Max

II

IIH

IlL

los

Icc

DM76

0.2

0.3

DM86

0.2

0.4

6.5

Units

9

V

mA

/LA

mA

mA

mA

Nole 1: All typicals are at VCC = 5V, TA = 25"C,
Note 2: Not more than one output should be shorted at a tIme.

"
I

7·122

Switching Characteristics

at Vcc=5V and TA=25'C (See Section 1 for Test Waveforms and Output Load)
From

Parameter

RL=4kll

(Input)
To

CL=50 pF

(Output)

fMAX Maximum Clock
Frequency

Min

Typ

6

13

Units
Max
ns

45

75

ns

65

110

ns

Clock
to
TC

70

115

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
TC

85

140

ns

tpLH Propagation Delay
Time Low to High
Level Output

CET
to
TC

35

60

ns

tpHl Propagation Delay
Time High to Low
Level Output

CET
to
TC

35

60

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to

tpLH Propagation Delay
Time Low to High
Level Output

Q

Q

•
7·123

Logic Diagrams
76l7S/86l7S(Oecade)
,

PE

P.1

P2

(9~)T1P-1Hr.=========~--~rr.(4=)========~--~~(5=)========~--~

P3

6)______- ,
(r

r++--q,cp

I

(13)

(14)

00

(11)

(12)

TC

02

01

03
TLlFI6651·2

76l76/86l76 (Binary)

P3

PE

(9~)j~~==========~--tt~========~--lHl,:==========~--1

(13)

(14)

00

01

Vee = (16)
GND = (8)

(12)

02

(r6)_ _ _ _ _

(15)

TC

~

(11)

03

TLfF/6651·3

7·124

~------------------------~---------------------------------------'C

s:

~National

~
~
o

~ Semiconductor
DM76L90/DM86L90 8·Bit Parallel
In/Serial Out Shift Registers

-s:
C

CIO

en
r-

CD

o

General Description

Features

These are B-bit serial shill registers which shill the data in
the direction of QA toward QH when clocked: Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shill/load
input. These regist~rs also feature gated clock inputs and
complementary outputs from the eighth bit.

•
•
•
•
•
•

Clocking is accomplished through a 2-input NOR gate,
permitting one input to be used as a clock-inhibit function.
Holding either of the clock inputs high inhibits clocking, and
holding either clock input low with the load input high enables the other clock input. The clock-inhibit input should
be changed to the high level only while the clock input is
high. Parallel loading is inhibited as long as the load input is
high. Data at the parallel inputs are loaded directly into the
register on a high-to-Iow transition of the shift !load input.
regardless of the logic levels on the clock, clock inhibit, or
serial inputs.

Connection Diagram

Complementary outputs
Direct overriding load (data) inputs
Gated clock inputs
Parallel-to-serial data conversion
Typical frequency 14 MHz
Typical power dissipation 80 mW

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storag.e Temperature Range

(Note 1)

8V
5.5V
- 65"C to 150"C

Note 1: The "Absolute Maximum Ratings" aiB those values beyond
which the safety of the device can not be guaranteed. The device should
not be operated at these limits. The parametric values defined in the
"Electrical Characteristics" table are not guaranteed at the absolute
maximum ratings. The "Recommended Operating Conditions" table will
define the conditions for actual device operation.

Function Table

Dual·ln-Line Package
CLOCK
viC INHIBIT
16

15

PARALLEL INPUTS
D

C

14

13

B
12

SERIAL OUTPUT
INPUT
QH

A

11

10

9

Inputs
Shift/ Clock Clock Serial
Load Inhibit
L
H
H
H
H

r-

X
L
L
L
H

X
L

I
I
I

X
X
H
L
X

H = High Level (steady state), L

2
SHIFT/CLOCK
LOAD

3
E

5

6

7-'8

H OUTPUT GND
~P-A-R~AL-L~E-L-IN-P-UT-S~ QH

G

TLlF16652-1

DM76L90 (J)

Inte·rnal
Outputs

A ... H

QA

QB

B ••. h

B

X
X
X
X

OAO
H
L
OAO

b
QBO
QAn
OAn
QBO

Output
QH
h
QHO
QGn
QGn
OHO

= Low Level (steady state)

X = Don't Care (any input, including transitions)

4
F

Parallel

DM86L90(N)

t = Transition from low-to-high level
a ... h = The level of steady-state input at Inputs A through H, respectively.
0AO. Oao. 0HO = The level of OA, 0a, or 0H, respectively. before the indicated
steady-state input conditions were established.

t

0An' 0Gn = The level of 0A or QG. respectively, before the most recent transition of the clock.

7-125

•

DM76L90IDM86L90

....o

CQ

0"

o
iir
CQ

;

3
PARALLEL INPUTS

(9)
OUTPUTQH

?}.

'"

a>

(7)

SHIFT / (1)
LOAD

--1,..----:....q
(2)

CLOCK~

CLOCK~
INHIBIT

_
OUTPUTOH

INPUT

Timing Diagram

c
:s::
.......

I

en

~

-:s::

c

c

Typical Shift, Load and Inhibit Sequences

CO

CLOCK
CLOCK INHIBIT
SERIAL INPUT
SHIFT/LOAD

en
eo

r-

I

L

c

-U

IH1

A-.:J
B
L

IH1

C---1
L
D
DATA

E---1

IH1
L

F

G---1

r-Hl

H---1 Hl
OUTPUT QH
OUTPUT QH

---

---

H

L

H

L

H

L

H

~==1

L

H

L

H

L

H

L

1- INHIBIT -+ ~

"-.~

- - - - - SERIAL SHIFT

LOAD
TLlF/6652·2

Recommended Operating Conditions
Sym

DM76L90

Parameter

Vcc

Supply Voltage

VIH

High Level Input
Voltage

V1L

Low Level Input
Voltage

IOH

DM86L90

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.75

5

5.25

V
V

2

2

V

0.7

0.7

High Level Output
Current

-0.2

-0.2

mA

IOL

.Low Level Output
, Current

2

3.6

mA

fCLK

Clock Frequency

6

MHz

tw

Pulse Width (Clock, Load)

100

tsu

Data Setup Time

44

tH

Data Hold Time

10

TA

Free Air Operating
Temperature

6

0

0

ns

100
44

22

22

ns

10

-55

125

7·127

0

ns
70

'C

Electrical Characteristics

over recommended operating free air temperature (unless otherwise noted)

,
Sym

Parameter

Conditions

Min
2.4

Typ
(Note 1)

Max

VOH

High Level Output
Voltage

Vcc = Min, 10H = Max
V IL = Max, VIH = Min

VOL

Low Level Output
Voltage

Vcc=Min
10L= Max
VIL=Max
V IH = Min

II

Input Current@Max
Input Voltage

Vcc = Max, VI = 5.5V

IIH

High Level Input
Current

Vcc=Max
VI =2.4V

Low Level input
Current

Vec= Max
VI =0.3V

Load

-0.54

Others

-0.18

Short Circuit
Output Current

Vcc= Max
(Note 2)

DM76

-3

-15

DM86

-3

-15

Supply Current

Vcc= Max
(Note 3)

ilL

los

Ice

Switching Characteristics
Parameter

Units
V

DM76

0.3

ElM86

0.4

V

0.1

mA

Load

30

p.A

Others

10

9.5

mA

mA

mA

at Vcc=5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
From'
(Input)
To
(Output)

RL=4 kG
Units

CL=50pF

'MAX Maximum Clock
Frequency

Min

Typ

6

14

Max
ns

tpLH Propagation Delay
Time Low to High
Level Output

Load.
to
AnyQ

44

88

ns

tpHL Propagation Delay
Time High to Low
Level Output

Load
to
AnyQ

62

124

ns

tpLH Propagation Delay
Time Low to High
Level Output

Clock
to
AnyQ

35

70

ns

tpHL Propagation Delay
Time High to Low
Level Output

Clock
to
AnyQ

50

100

ns

tpLH Propagation Delay
Time Low to High
Level Output

33

66

ns

to
QH

tPHL Propagation Delay
Time High to Low
Level Output

H
to
QH

56

112

ns

tpLH Propagation Delay
Time Low to High
Level Output

H
to
QH

33

66

ns

tpHL Propagation Delay
Time High to Low
Level Output

H
to
QH

56

112

Note 1:
Note 2:
Note 3:
parallel

H .

,

ns
I

.

-."-

'"

, "
All typlcals are at VCC = SV, TA = 2S'C,
"Not more than one output should be shorted at a time,
''>..... ~,
With the outputs open, CLOCK INHIBIT and SHIFT/LOAD at 4.SV, and a ClOCk pulse applied to the CLOCK Input, ICC is measured first with the
Inputs at 4,5V, then with them at ov,
7.128 1

Section 8
Appendicesl
Physical Dimensions

8

S~ction

Contents

Military/Aerospace ........................................... ',' . . . . . . . . . . . . . . . . .
Commercial Quality Enhancement Programs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rei Data. . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . . . . . . . .. .. . . . .. . . .
Thermal Ratings for les . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Industry Package Cross Reference .................................................
Physical Dimensions ...................................... '. . . . . . . . . . . . . . . . . . . . . . .

8·2

8-3
8-13
8-17
8-28
8-29
8-30 .

INTRODUCTION TO THE RELIABIL'ITY
MILITARY/AEROSPACE PROGRAMS
neutron irradiation, shock and acceleration
tests, visual radiography, and dimensional tests,
to mention only a few. In the electrical test section, there are tests to examine load conditions,
power supplies, short circuit currents, and other
tests. Each of these tests is designed to look at
specific reliability and quality concerns that
affect semiconductor products.

History
In the mid 1960's the various government agen- cies responsible for semiconductor reliability
saw that screenable defects were resulting in an
in-equipment failure rate of about 1% per thousand hours. In-depth failure analysis allowed
them to determine what the predominate failure
mechanisms were. The Solid Sfate Applications
Branch of the Air Force's Rome Air Development
Center (RADC) was assigned the task of developing a screening procedure which would remove the infant mortality failures' which had led
to the high failure rate previously encountered.
Working closely with other semiconductor reliability experts, the RADC staff developed MILSTD-883, which was first issued in 1968. The
objective of MIL-STD-883 was to create an economically feasible, standardized integrated circuit screening flow'which would achieve an inequipment failure rate of 0.08% per thousand
hours for Class Band 0,004% per thousand
hours for Class A (which was later superseded
by Class S). Over the years this standard has
grown and matured with a number of new test
methods added as reliability information and
failure analysis results became more detailed.
These developments have led to one of the
strongest and most comprehensive screening
specs available, MIL-STD-883.

Screening Flows
The overall reliability requirements for a sys.tem
depend upon a number of factors, including
cost-effectiveness. For example, a deep space
probe, where component replacement is impossible once the system is launChed, requires very
high reliability, despite the inherent cost of complex screening. On the other hand, a groundbased radio unit can use a less stringent reliability testing sequence, since a failed component
can be easily replaced at moderate cost. In line
with this range of needs, MIL-STD-883 established three distinct product assurance levels to
provide reliability commensurate with the prod- ,
uct's intended application. The three levels are
Class S (intended for critical applications, such
as space), Class B (intended for less critical applications, such as airborne or ground systems),
and Class C (intended for easily replaceable
systems, which has since been eliminated).

,Purpose and Structure

National and MIL·M·38510

MIL-STD-883 states: this standard establishes
uniform methods and procedures for testing microelectronic devices, including basic environmental tests to determine resistance to deleterj·
ous effects of natural elements and conditions
surrounding military and space operations, and
physical and electrical tests. What does this
mean to the semiconductor user? To understand
this, one must subdivide MIL-STD-883 into two
primary areas: 1) Detailed how-to specifications
(methods 1001 through 4007) and 2) Screening
and qualification andlor quality conformance
testing requirements (methods 5001' through
5009). By examining each of these areas the
thrust of MIL-STD-883 will become apparent.

A major thrust exists among integrated circuit
users, suppliers, and the U.S. Government to
avoid proliferation of military procurement specifications by turning instead to standardized
high reliability microcircuits. National Semiconductor endorses 'and supports this trend.
One major program to which National is heavily
committed is the JAN MIL-M-38510 IC program.
This is a standardization program administered
by the U.S. Defense Department which allows a
user to purchase a broad line of standard products from a variety of qualified suppliers.

Detailed How-to Specifications

There is only one MIL-M-38510 program. National
is committed to supplying only QPL devices,
and discourages any "pseudo-38150" alternates.

MIL-STD-883 is a collection of enVironmental',
mechanical, visual, and electrical test methods.
These methods define tests which enable manufacturers and users to screen for specific reliability concerns. The tests covered include
moisture reSistance, high temperature storage,

There are two levels specified within MIL-M38510 - Classes Sand B. Class S is typically
specified for space flight applications, while
Class B is used for aircraft and ground systems.
8·3

MIL·M·38510

• Since MIL-M-38510 is a standard program, procurement lead times will be shorter. With a
large number of programs using JAN devices,
distributors and manufacturers are able to
establish inventories of JAN devices. National
in particular is committed to maintaining finished goods and work-in·process inventories
to support .our customers' needs.

The Defense Electronic Supply Center (DESC)
administers the integrated circuit standardiza·
tion program known.as MIL·M·3851·0 (sometimes
referred to as the JAN Ie Program). The specifi·
cation set used to define the program consists
of four documents: general specification MIL·M·
38510, which is an overall definition of the pro·
cessing and testing to 'be performed; detail
specifications (referred to as "slash sheets"),
e~ch of which defines the performance paramo
eters for a unique generic device or a family of
devices; MIL·STD·883, which defines specific
screening procedures; and MIL·STD·976, which
defines line certification requirements.

• Device markings are consistent from one
manufacturer to another.

When a user orders a MIL·M·38510 device, he is
guaranteed that he will get a device fully conformant with the detail specification and which
has also met all of the general testing and processing requirements. DESC requires semiconductor suppliers to become formally qualified
under the MIL-M-38510 program and to be listed
on the current Qualification Products List (QPL)
before. they are allowed to legally ship JAN
devices.

• The program is extremely cost-effective. A
user can purchase a few devices for engineer·
ing evaluation and prototyping and know that
they will be identical to the devices he will get
during production. When the cost factors associated with spec. writing, supplier qualifica·
tion, maintaining voluminous parts control
documentation, and the more intangible benefits of device availability are totaled, use of
JAN ICs is overwhelmingly the most costeffective approach.
.

Advantages to the User

Advantages to the Supplier

The JAN 38510 program has numerous advantages for the integrated circuit user.

What motivates a supplier like National Semiconductor, to be so heavily committed to the
MIL-M-38510 program? National has the broadest range of reliability processed products avail·
able in the semiconductor industry. A program
such as MIL-M-38510 helps to standardize the
processing required and to minimize the number
of individual user specifications. This allows·
National to concentrate more resources on this
program, thereby improving product quality and
availability.

• Spare parts will be readil'y available without
excessive minimum order requirements.
• Standard parts with volume requirements will
remain in production longer.

• A single explicit specification eliminates
guesswork concerning device electrical characteristics or processing flow.
• The rigorous schedule of quality conformance
testing that is a mandatory part of the MIL-M38510 program assures the user of long·term
stability.
• Since the electrical characteristics of the
devices are at least as tight as the "standard
industry data sheet" parameters, device performance will meet the vast majority of
system design requirements. Additionally,
min./max. limits replace many data sheet
typicals, making circuit design and worst case
design analysis decisions easier.

The Most Frequently Asked Questions and
Answers about MIL·M·38510
There are many questions which are frequently
asked regarding the MIL-M·38510 program. We
would like to answer some-of them.
Q. WHAT MUST A MANUFACTURER DO TO GET
HIS PARTS LISTED ON THE QPL?

• The user is spared the expense of researching
and prep'aring his own procurement
document.

A. There are two things which a manufacturer is
required to do. First, he must get his facilities
(including wafer fab, assembly, and rei pro·
cessing areas) certified by DESC. This requires that each fab area used for QPLdevices must be approved. Second, for each
specific device and package combination
listed on the QPL, the manufacturer must
perform extensive qualification testing and
provide detailed device information to DESC.
This data is typically supplied in two phases.

• T.he user is spared ·the expense 'of qualification testing. The QPL tells him whJch suppliers have qualified the device he requires.
• The QPL gives the user a choice of qualified
suppliers for devices that are fully interchangeable. In addition, the presence of several sources guarantees competitive pricing
that is typically lower than for devices to a
user's own specifications.
8-4

In the first phase, the manufacturer must
supply detailed information concerning the
device construction and electrical characteristics_ Once this data has been verified by
DESC to confirm that the manufacturer's device meets the MIL-M-38510 requirements,
the manufacturer is listed on Part II of the
QPL. At this point the manufacturer is legally
able to supply full' JAN qualified devices
meeting ALL of the MIL:M-38510 requirements. The manufacturer must then perform
the full qualification testing of Method 5005
of MIL-STD-883 as specified in paragraph'4.4
of MIL-M-38510. Once this data has been
reviewed and accepted by DESC, the manufacturer is listed on Part I of the QPL.

Q. HOW IS A JAN QPL DEVICE MARKED?
A.. Tables I and II explain the details of the marking for JAN ICs.

TABLE 1_ MIL-M-38S10 Part Marking
~~llil'XXXXXYYY

L

the lead Finish
A = Solder Dipped
B = Tin Plate'
C = Gold Plate
X = Any lead finish above
is acceptable

' - - the Device Package (see
Table II)
-

Q. IS THERE ANY DIFFERENCE IN DEVICES
PRODUCED WHILE A MANUFACTURER·IS
LISTED ON PART II OFTHEQPLANDTHOSE
PRODUCED AFTER PART I QUALIFICATION
IS COMPLETED?

the Screening Level S or B

' - - - - the Device Number on the
Slash Sheet
' - - - - - t h e Slash Sheet Number
'-------MIL-M-385810

A. There is absolutely no difference. A supplier
must meet all of the device screening and
quality conformance requirements no matter
what his QPL status.

' - - - - - - - - - T h e JAN prefix (which
may be applied only to a
fully conformant device
per paragraphs 3.6.2.1 and
3.6.7 of MIL-M-38510)

Q. HOW DOES A USER KNOW WHAT DEVICES
ARE COVERED BY SLASH SHEET SPECIFICATIONS?

TABLE 11_ JAN Package Codes

A. Supplement 1 to MIL-M-38510 contains a listing of the slash sheet specifications and a
cross reference to the generic part type. This
is updated as new slash sheets are released.
National's Reliability Handbook also contains a cross reference.

38510
PACKAGE
DESIGNATION
A
B
C
D
E
F

Q. HOW CAN A USER OBTAIN COPIES OF THE
QPL, SUPPLEMENT 1 OF MIL-M-38510, MILM-38510 ITSELF, AND MIL-STO-883?

G
H
I
J
K
M
P

A. Copies of these and other related documents
may be obtained from:
Naval Publications and Forms Center
5801 Tabor Avenue
Philadelphia, PA 19120
(212) 697-2179

Q

R

Q. WHAT ABOUT THOSE DEVICES FOR WHICH
NO DETAIL SPECIFICATION EXISTS?

S
V
W

A.' The ultimate aim of a standardization program must be to furnish all parts. Requests
for addition of a part to MIL-M-38510 should
be made to DESC Directorate of Engineering.
Dayton, Ohio 45444, indicating a need for
slash sheets andlor suppliers to be qualified
for the additional devices. National has a
form (available through local sales offices)
which may be used for this purpose. In addi. tion, if only some parts are available, a user
can still see significant savings on those that
are available.

~}

MICROCIRCUIT I'NDUSTRY .
DESCRIPTION
14-pin 114" x 114" (metal) flatpack
14-pin 3116" x 114" flatpack
14-pin 114" x 314" dual-in-line
14-pin 1/4" x 3/8" (ceramic) flatpack
16-pin 1/4" x 7/8" dual-in-line
16-pin 114" x 3/8" (metal or ceramic)
flatpack
8-pin TO-99 can or header
10-pin 1/4" x 114" (metal) flatpack
10-pin TO-100 can or header
24-pin 1/2" x 1-1/4" dual-in-line
24-pin 3/8" x 5/8" flatpack
12-pin TO-101 can or header
8-pin 1/4" x 318" dual-in-line
40-pin 8/16" x 2-1/16" dual-in-line
26-pin 1/4" x 1-1/16" dual-in-line
20-pin 1/4" x 1/2" flatpack
18-pin 3/8" x 1-15116" dual-in-line
22-pin 3/8" x 1-1/8" dual-in-line
Unassigned - Reserved for
identifying special packages whose
dimensions are carried in the detail
specifications.

Q. ARE DEVICES CALLED "M38510, JAN PROCESSED, JAN EQUIVALENT, ETC." REALLY
QPL PRODUCTS?
A. Absolutely not. There is only one QPL product - it is a JM38510 marked device. "JAN
Equivalent" is expressly forbidden by para8-6

graphs 3.1 and 3.6.7 of MIL·M·38510. MIL·M·
38510 does provide for the production of
devices when no qualified sources exist, but
this may be done only with prior DESC ap·
proval, and products produced under this
provision must meet all requirements of MIL·
M·38510 other than qualification.

product requirements, will have a date code
that is earlier than the date he i$ placed on
the QPL. However, the manufacturer may not
begin to assemble and 'test unless he has a
, line certification and an approval to proceed
'
iNith qualification. '
Q. WHAT IS THE RELATIONSHIP BETWEEN
MIL·M-38510AND MIL·STD·883?

Q. HOW LONG CAN A SUPPLIER REMAIN ON
PART II OF THE QPL?

A. MIL·M·38510 defines complete program
requirements and the detail device electri·
cal performance parameters. The device
processing requirements are specified in
MIL·STD·883.
.

A. For Class B, a manufacturer can remain on
Part II for two years or until 90 days after
another !'lupplier becomes qualified for the
same device package, screening level, and
lead finish combination on Part I of the QPL.
c:lass S devices may remain on Part II for one
year after another manufacturer reaches
Part I.

Q. SUPPOSE DEVICES ARE KEPT ON A MANU·
FACTURER'S OR DISTRIBUTOR'S SHELVES
FOR A PERIOD OF TIME; MUST THEY EVER
BE RETESTEI) TO VALIDATE THAT THEY
STILL MEET SLASH SHEET CHARACTER·
ISTICS?

Q. WHEN ANOTHER SUPPLIER OBTAINS. PART
I QUALIFICATION, ARE THE OTHER QUALI·
FlED SUPPLIERS REMOVED FROM PART II
IMMEDIATELY?

A. Yes. Devices held by a manufacturer or by his
authorized distributor which have a date
code older thanl36 months must be retested
by the manufacturer in accordance with
Group A sampling requireme'nts prior to shipment to a customer or return to inventory.

A. No. The supplier is given 90 days before
being removed from Part II for a Class B de·
vice and one year for a Class S device. During
that time a supplier may legally accept orders
for those devices. After the end of the 90·day
or one year period, he may no longer'accept
orders but may complete and ship those or·
ders received prior to that time, no matter
how long it takes him to complete them.

Q. WHY SHOULD A USER SPECIFY "X" IN
THE LEAD FINISH DESIGNATION FOR A
PART TYPE?
A. A manufacturer who receives an order for a
specific lead finish for which he is qualified
but has no inventory at the time of order may
not be able to fill the order in a timely man·
ner, even though he might have substantial
inventory of another lead finish. Unless a
user has a specific reason for wanting a par·
ticular lead finish, he should allow his sup·
pliers the flexibility of shipping whatever
finish is available.

Q. IS A SUPPLIER EVER REMOVED FROM
PART I QUALIFICATION?
A. Generally not. As long as a supplier contino
ues to manufacture the device, maintains ap·
propriate facility approvals, and submits all
required reports and information to DESC
within stipulated time limits, he will retain
QPL I listing. Violation of these requirements
can be cause for removal from QPL.

Q. WHAT DATA IS A MANUFACTURER RE·
QUIRED TO SHIP WITH A JAN PART?

Q. CAN AN AUTHORIZED DISTRIBUTOR SHIP
JAN DEVICES FROM HIS SHELVES IF THE
MANUFACTURER HAS LOST HIS QPL LIST·
ING FOR THOSE DEVICES?

A. A certificate of conformance is all that is reo
quired. However, he must retain all data for
three years.

A. Yes. As long as those devices were ordered
by the authorized distributor while the manu·
facturer had QPL listing for those devices,
the distributor may subsequently ship those
devices from his shelves.

Q. CAN A DEVICE FOR WHICH THERE IS NO
SLASH SHEET BE PROCESSED TO MIL·M·'
38510?
A. Since MIL·M-38510 invokes a combination of
the processing requirements of MIL·STD-883
and the detail device performance paramo
eters contained in each individual slash
sheet, the answer is obviously no. However,
National's 883B/RETSTM program does pro·
vide parts which meet all of the screening
requirements of the MIL·STD-883 specification and which have been subjected to all of
the MIL·M-38510 controls (except for
domestic assembly).

Q. CAN A MANUFACTURER LEGALLY SHIP
JAN QPL MATERIAL HE ASSEMBLED AND
TESTED BEFORE HE RECEIVED A QPL
LISTING?
A. Yes. The manufacturer must assemble and
screen parts to prove his ability to comply
with the specifications before he can be
placed on QPL. As a result, his first lot of
material, which is fully conformant to QPL
8-6

TABLE III. Sample MIL·M·38510 Listing
GOVERNMENT DESIGNATION
DEVICE
TYPE·

M3851 0/008
01

DEVICE
CASE
LEAD MATERIAL
CLASS OUTLINE
AND FINISH

TEST REPORT
NUMBER

MANUFACTURER'S NAME

!

S only

A

C

38510·953·81

National Semiconductor Corp.

01
02

B

C
D

A
B

38510·953·81
38510·30·7T

National Semiconductor Corp.

03

B

C

A
B

38510·520·83

National Semiconductor Corp.

'''M38510'' is the military designator for MIL·M·38510. The QPL shows this notation even though the parts are fully qualified devices and are
marked JM38510/XXXXXYYY.

Q. HOW IS AN INSPECTION LOT DEFINED?

Q. WHAT DOES A QPL LISTING LOOK LIKE
AND HOW DO YOU READ IT?

A; For Class B devices, each inspection lot shall
consist of microcircuits of a single device
type, in a single package type and lead finish,
or may consist of inspection sublots of sev·
eral different device types, in a single pack·
age type and lead finish, defined by a single
detail specification. Each inspection lot shall
be manufactured on the same production
line(s) through final seal by the same produc·
tion techniques, and to the same device
design rules and case with the same material
requirements, and sealed within the same
period not exceeding 6 weeks.

A. Sample QPL listings are shown in Table III.
JM3851 0/00801 SAC
JM38510/00801 BCA
JM38510/00801 BCB
JM38510100801 BDA
JM38510/00801 BDB
JM38510100802BCA
JM38510/00802BCB
JM38510/00802BDA
JM38510/00802BDB
JM38510/00803BCA
JM38510/o0803BCB

Q. WHAT IS NATIONAL SEMICONDUCTOR'S
COMMITMENT TO MIL·M·38510?

Q. WHAT QUALITY CONFORMANCE TESTS
ARE CONDUCTED? ARE ALL DEVICES IN
A GENERIC FAMILY EVENTUALLY' SUB·
JECTED TO QUALITY CONFORMANCE
TESTING?

A. National Semiconductor is convinced that
the level of standardization offered by a pro·
gram like MIL·M·38510 is the key to long·term
military component procurement viability.
We have a corporate commitment to MIL·M·
38510. We believe that the program will be of
significant benefit in lessening the problem
of product obsolescence, for the volume pro·
vided will help to keep many key devices in
production. We believe that the program will
make possible the procurement of devices in
small quantities with reasonable lead times
for long·term spares or field maintenance
requirements.

A. For B level devices quality conformance
tests must be conducted as follows:
Group A-Each inspection lot or sublot.
Group B-Each inspection lot for each pack·
age type and lead finish on each
detail specification.
Group C-Periodically at 3·month intervals
.
on one device type or one inspec·
tion lot from each mircocircuit
grqup in which a manufacturer has
qualified device types (die related
tests).
\

National Semiconductor will continue to
maintain a broad base' of line certifications
and an extensive list of Class B arid Class S
device qualifications. We will continue to
work with the Department of Defense, con·
cerned users, and other semiconductor man·
ufacturers to update and redefine the appli·
cable specifications. We feel that this level of
support is essential if MIL·M·38510 is to reo
main the strongest standardization program
available.

Group D-Periodically at a 6·month interval
for each package type for which a
manufacturer holds qualifications
(package related tests) ..
Different devices within a generic family are
chosen for successive quality conformance
tests until all of the devices have been sub·
jected to testing. The sequence is then reo
peated. The manufacturer must submit attri·
butes data to DESC for all quality confor·
mance tests performed.

In addition, we will continue to add capacity
and to build up substantial inventories of a
large spectrum of products to ensure the
8·7

availability and the lead times that are
needed for key military programs.

ufacturer. We have tried to emulate MIL-M·38510
to the fullest extent possible, with the same production controls, calibration schedules, rework
and resubmission' procedures, operator certifi·
cation requirements, and all of the other key ele·
ments of MIL·M·38510. The procedures that we
employ in the production of MIL-M-38510 de·
vices are used for all of the military devices we
manufacture.

National Mil/Aero Standardization
. Programs
Your customer has imposed upon you requirements for product reliability that you must
meet on every single component you buy. In
most cases, these requirements mandate that
you buy JAN MIL-M-38510 parts where they are
available, and that all other devices must be as
close to JAN as is achievable. We don't consider
this unreasonable. In fact, we believe that this is
the only reasonable and intelligent approach.

Our 883S/RETS microcircuits are processed
through a screening flow that matches the MIL-M38510 Class S flow exactly. Our commitment to
MIL-M-38510 Class S is such that once qualified
for a given device type we will sell that part only
as a JAN Class S part. Class S QPL listing will
result in the immediate removal from production
of the 883S/RETS version of the device.

To meet this objective, we designed our 883BI
RETS program around requirements that were
already imposed for the MIL-M-38510 program.'
We realize that there are many so-called standardization programs available in the marketplace which lack the compliance that you need.
Our 883B/RETS program is totally compliant. We
invite you to make this comparison between
what we offer and what you need. Our screening
flow, our 5% PDA, our quality conformance test
frequency, and the other items that you conSider
important, match exactly the requirements
defined in MIL-M-38510." If they did not, we
could not offer Total Standardization.

National's Commitment
But compliance flows are obviously meaningless unless the capacity is in place to support
them. We have the industry's largest screening
capacity. Over the past few years we have reinvested substantial sums in additional capital
equipment in both buildings and the equipment
with which to fill those buildings. Our Tucson,
Arizona plant was the first plant in the entire industry to be totally dedicated to the production
of military integrated circuits. We will continue
to add capacity for military assembly and test,
even during those periods when others turn
away from the military marketplace in pursuit of
what they view to be the more attractive commercial market. We feel that a commitment to
the needs of the military/aerospace user community should not be based upon the conditions
encountered in the commercial marketplace. We
have no plans for other than a continued long·
term commitment to military/aerospace component production and screening. And we will not
deviate from the highest standards of quality
and reliability in our execution of that commitment. T!lere are no shortcuts to semiconductor
reliability. It can only be achieved through rigid
adherence to established standards;

Standardization provides the manufacturing efficiencies needed by the semiconductor manufac·
turers if they are to meet military semiconductor
needs. To the user, standardization offers the
highest guarantee of quality and reliability
through production consistency and 'uniformity.
The most significant benefit of standardization
to the Department of Defense, however, is that it
ensures the availability of component level
spares to 'key programs with the pricing, delivery, and reliability needed for the field support
and maintenance of our key defense electronics
systems.
National's MIL-M-38S10 Emphasis
To implement this view of standardization, we
. have based. our entire approach to military
screening upon the Class S and Class B requirements of MIL-M-38510. We are convinced that to
do less than this would be to provide an inferior
product, one that does not meet the true needs
of the Department of Defense. Our 883B/RETS
microcircuits are processed through the most
comprehensive and compliant Class B' screening program offered by any semiconductor man-

However, we also acknowledge the quite obvi·
ous fact that through refinement and redefinition, standards are subject to change. As those
changes occur, we will update our current procedures to reflect the changes that find their way
into MIL-M-38510 and MIL-STD-883. We will,
where our understanding of semiconductor reliability and screening indicates the need, actively
pursue those changes that we feel will allow our'
industry to provide a better product to the sys·
tems manufacturers. We will also steadfastly
resist those changes which we feel sacrifice reli
ability to the less important question of
expediency.

'Requirements that were subsequently incorporated into MILSTO-883
"and MIL-STO-883.·

8·8

National's Standard Programs

Ordering to Control Specifications

MIL-M-38510 is the key military standardization
program for ICs. National is equally committed
to the support of the requirements .of the space
segment of the market for MIL-M-38510 Class S
devices. To support these needs we have established dedicated Class S assembly and test
facilities. The realization that users could not
obtain all the device types they required through
these programs led National's Military/Aerospace Products Group to the development of
two of the strongest and most compliant inhouse programs in the industry. National programs for 883B/RETS and 883S/RETS microcircuits provide the systems manufacturer with an
easy mechanism for obtaining those devices not
listed on the MIL-M-38510 QPL. In response to
other user needs, National also developed a program for radiation hardened devices (both
CMOS and linear), a comprehensive program for
radiation susceptibility testing for Class S
devices, and a program for the production of
devices in lead less chip carriers (LCCs).

We also acknowledge the fact that many military
systems manufacturers must, for contractual
purposes, maintain their own specifications for
many of the devices that they purchase. We have
no objection to the use of contractor prepared
procurement specifications, for we have found
that the majority of these documents are written
in compliance with the requirements of MIL-M38510. Where this is true, we have found that
they are also totally compatible with our inhouse standardization programs. Where drawings submitted to National differ from the
requirements outlined in MIL-M-38510, we welcome the opportunity to work with our customers to develop specifications which do meet the
intent of MIL-M-38510.
Where customer specifications and our 883B/
RETS product specifications correspond, we
have the ability to expedite delivery by adding
the customer part number in addition to the
basic 883B/RETS part number. Customers who
understand our program and wish to use the program in their parts procurement may order by
placing "M/O" alter their part number on their
purchase order, thus allowing us to mark their
part number on our 883B/RETS devices without
the lengthy delay normally required for a comprehensive specifications review cycle. We have
tried to provide programs that offer the maximum level of flexibility within the constraints of
standardization.

)

RETS and Burn-In

One of the primary advantages of MIL-M-38510 is
its clear definition and standardization of electrical test and burn-in requirements. One of the
major drawbacks seen in the standard reliability
screening programs of' most semiconductor
manufacturers is that electrical testing is invariably performed to some document'that is nqt
available to the user. The user has the right to
know what he is buying. At National that testing
is never vague or undefined. Both in-house programs (883B/RETS and 883S/RETS) are based
upon a document called the RETS(an acronym
for Reliability Electrical Test Specification. The
RETS is a simplified but complete description of
the testing performed as part of National's standard Rei electrical test program!!, and is controlled by our QA department. The burn-in circuits and electrical test parameters for the MILM-38510 Class S and Class B devices produced
by National Semiconductor are defined by the
applicable detail specification.

Standardization is the key to cost-effective procurement of high reliability semiconductor devices. National Semiconductor Corporation is
committed to that standardization.
Military Processing: A Corporate Commitment

The National Semiconductor Military/Aerospace
Products Division draws upon the total resources of National Semiconductor. National is
one of the world's largest manufacturers of
semiconductor products, offering' the largest
number of product types available from any single source in the industry. This product line is
growing faster than that of any other worldwide
semiconductor manufacturer. Each new product
is carefully evaluated for possible military/aerospace usage potential, and new product designs
must comply with the reliability and quality constraints required by that segment of the industry. All new product deSigns are targeted to
full military temperature range operation.

Ordering ICs from National

Ordering National Semiconductor High Reliability integrated circuits is very simple. National
sales offices and sales representatives can provide price and delivery information on our entire
line of JM38510 Class B, JM38510 Class S, 883B/
RETS and 883S/RETS microcircuits. A large
percentage of these devices are available from
inventory at either the factory or at one of our
many distributors.

In addition, a dedicated Reliability Engineering
Department within the Military/Aerospace, Prod-

8-9

ucts Division coordinates burn-in circuit design,
test tape development, test fixturing, support
documentation, and new product release paperwork to ensure the earliest possible introduction
of fully compliant 883B/RETS versions of the
'
new products introduced by the company.

, tion products. As a result of all this innovation,
National has become the only company in the
entire semiconductor industry.,capable of providing high reliability devices from all of the
following product lines:
linear,
hybrid
CMOS logic
Megarad CMOS logic
bipolar memory
MOS RAMs
CMOS RAMs
MOS EPROMs
CMOS EPROMs
MOS EEPROMs
data acquisition devices
standard TTL
low power TTL
low power Schottky
standard Schottky
interface devices
bipolar microprocessors
MOS microprocessors
CMOS microprocessors
COPSTM microcontrollers
high-speed CMOS Schottky
advanced low power Schottky
advanced Schottky

We are able to do this well, for National is no newcomer to this business. Founded in Danbury,
Connecticut in 1959, National acquired an entire
new management team in 1967 and moved corporate headquarters to Santa Clara, California.
The new management team focused its attention on the transistor product line; and rapidly
made that line profitable. Then the company's
talents were turned to the development of linear,
digital, and MOS integrated circuits - the
. fastest-growing segments of the semiconductor
marketplace. Finally, an OEM representative and
distributor network was established to develop
and service a broad customer base, and facilities were added around the world to provide
competitive products to worldwide markets.
The Reliability Test Department was initially
formed in 1968 and ,reported at that time to the
Director of Quality Assurance. The Rei Department developed the same rapid growth rate that
the company as a whole had shown. From a
small staff occupying several thousand square
feet in Santa Clara, these re'liabillty test operations grew until today they employ over 3000
people worldwide. Well over 200,000 square feet
are devoted to the testing and assembly of hig~
reliability products. During 1981, the Military/
Aerospace Products Group became the Military/
Aerospace Products Division. The company is
currently involved in a number of military research and development programs, including a
Phase I VHSIC contract.

National Semiconductor has wafer, fabrication
plants in Santa Clara, California; Salt Lake,City,
Utah; Arlington, Texas; and Danbury, Connecticut. Many of these fabrication plants, along with
our assembly and test lines in Santa Clara, California and Tucson, Arizona, have been fully certified for the production of Class S and Class B
M'IL-M-38510 circuits.
To support the requirements of the Class S marketplace, we have our own SEM and radiation
testing facilities. Our screening capabilities are
backed up by one of the most extensive failure
analysis labs in the industry.

VHSIC involvement was natural since National's
technological leadership has enabled the company to consistently be one of the major suppliers of military/aerospace semiconductors.
Having continued to develop a high technology
image through the development olf Megarad
hardened CMOS and linear device types, and the
develo,pment of TRI'CODETM logic, National is
now expanding technology frontiers in the areas
of memory, microprocessor, and data acquisi-

National is the leader in the military/aerospace
integrated circuit market. We have achieved that
leadership by offering an unmatched combination of technology, product breadth, understanding, commitment 'and capacity.

REFER TO THE RELIABILITY HANDBOOK FOR LIST OF PARTS AVAILABLE

8-10

883B/883S/RETS Screening Flows
WAFER FABRICATION &
DEVICE ASSEMBLY

WAFER LOT ACCEPTANCE
PER METHOD 5001

NOTE 2

PRECAP VISUAL INSPECTION
MIL·STO·BB3 METHOD 2010
CONDITION B

ASSEMBLY
DIE SHEAR
TESTING

NOTE 2

SEALING

ASSEMBLY
BOND PULL
TESTING

NOTE 2

STABLILIZATION BAKE
MIL·STO·BB3 METHOD 100B
CONDITION C

lDD~,

NON·DESTRUCTIVE 8DND
PULL TESTING (METHOD 20231
PRECAP VISUAL INSPECTION
(METHOD 2010, CONO AI

TEMPERATURE CYCLING
MIL·STD·Ba3 METHOD 1010
CONDITION C

SEALING
CONSTANT ACCELERATION
MIL·STO·883 METH.OO 2001
CONDITION E (Yl ONLY)

STA81L1ZATION BAKE
(METHOD 100B. CONDo CI
TEMPERATURE CYCLING
(METHOD 1008. COND C)

FINE LEAK TEST
MIL·STO·883 METHOD 1014
CONDITION A OR B

CONSTANT ACCELERATION
(METHOD 2001. COND EI
Yl AXIS ONLY

GROSS LEAK TEST
MIL·STO·883 METHOD 1014
CONDITION C

PIND (METHOD 20201 COND A
INTERIM ELECTRICALS AT
+ 25'C DC PER RETS
(AT MANUFACTURER'S OPTION)

NOTE 3

SERIALIZATION
INTERIM ELECTRICAL TEST·
25'C DC
REAO·AND·RECORD
ALL PARAMETERS

BURN·IN TEST MIL·STD·883
METHOD 1015. CONDITION A, B,
C OR O. 160 HOURS AT 125'C
OR EQUIVALENT

NOTE 7

STATIC I BURN·IN
24 HRS - 125'C

INTERIM ELECTRICALS
25'C DC PER RETS
PDA=5%

VIN=VOUl=O

INTERIM
ElECTRICAL TEST
25'C DC
COMPUTE ..u
PDA PER NOTE 4

FINAL ELECTRICAL TEST
PER NSC RETS

+125°C. _55°C DC
(INCLUDES FUNCTIONAL
TESTS + 25'C At

NOTE 7

STATIC II BURN·IN
24 HRS - 125'C
YIN = VOUT = Vee

QUALITY CONFORMANCE TESTING
GROUP A - EACH SUBLOT
GROUP B - EACH LOG
GROUP C - EVERY 90 DAYS PER
MICROCIRCUIT
GROUP
GROUP 0 - EVERY 6 MONTHS
PER PACKAGE TYPE

INTERIM
ELECTRICAL TEST
25°C DC
COMPUTE .>s
POA PER NOTE 4

NOTE 7

DYNAMIC BURN·IN
240 HRS - 125°C
VIN = YOUT = 0 TO Vee
AT 100 kHz

EXTERNAL VISUAL
MIL·STO·8a3 METHOD 2009
NATIONAL oFF·THE·SHELF
INVENTORY PROGRAM

INTERIM ELECTRICAL TEST
(POST 8URN·IN) DC 25'C
POA-5%

FIGURE 1. National's 883B/RETS Class B
Screening Flow

DRIFT ('>1 CALCULATION

NOTES 5. 1

NOTE 5

FINAL ELECTRICAL TESTS

DC AT 125°C -55°C
INCLUDING' FUNCTIONAL TESTSI

NOTE 1

25°C AC
NOTES:
1. ALL METHODS REFERENCED ARE MIL·STD·883 TEST METHODS.
2. THESE TESTS ARE PERFORMED ON A SAMPLE BASIS ALL OTHER
TESTS ARE PERFORMED 100%.
3. ACCEPTANCE CRITERIA SHALL BE IN ACCORDANCE WITH
MIL·M·3851o.
4. THE PoA FOR STATIC I AN~ STATIC II BURN·IN SHALL BE 5%
TOTAL.
5 THE PoA INCLUDES.> FAILURES.
6, GROUP A AND BOND PULL AND DIE SHEAR TESTING OF GROUP 8
MAY BE PERFORMED oN·LlNE.
1, ALL ELECTRICAL TESTING SHALL 8E IN ACCORDANCE WITH THE
APPLICABLE RETS DR THE APPLICABLE MIL·S·3851D DETAIL
SPECIFICATION.

FINE LEAK TEST
(METHOD 1014, CONO. B)
GROSS LEAK TEST
(METHOD 1014. CONO. CI·
X·RAY INSPECTION
(METHOD 2012)

QUALITY CONFORMANCE TESTS
(METHOD 5005 .. GROUP A.
GROUP B, AND GROUP 01
EXTERNAL VI_'UAL
(METHOD 20091

FIGURE 2. National's 883S/RETS Class S
Screening Flow
8·11

NOTES 2 6

National Semiconductor Corporation
883/RETS·PROGRAM
CERTIFICATE
OF
CONFORMANCE

TEST

MIL-STD-883 METHOD"

REQUIREMENT

INTERNAL VISUAL
STABILIZATION BAKE
TE"MPERATURE CYCLING
CONSTANT ACCELERATION
FINE LEAK
GROSS LEAK
BURN-IN
FINAL ELECTRICAL
PDA

2010 B
1008 C 24 HRS @ +150·C
1010 C 10 CYCLES -65°C/+150·C
2001 E'
1014 B 5 x 10-8
1014 C2
1015 160 HRS@ +125·C
+25·C DC PER NSC RETS
10% MAX ALLOWABLE
+125·C DC PER NSC RETS
-55·C DC PER NSC RETS
+25·C AC PER NSC RETS
LTPD SAMPLE
2009

100%
100%
100%
100%
100%
100%
100%
100%

QA ACCEPTANCE
EXTERNAL VISUAL

100%
100%
100%
100%

, RETS = REL ELECTRICAL TEST SPECIFICATION
" ALL METHODS TO CURRENT REVISION LEVELS

THIS IS TO CERTIFY THAT ALL 883/RETS MATERIALS SUPPLIED TO YOUR PURCHASE
ORDER COMPLY WITH ALL THE REQUIREMENTS, SPECIFICATIONS, AND DOCUMENTS
PERTINENT TO THE NATIONAL 883/RETS PROGRAM. ALL TEST DATA AND CERTIFICA·
TION IS 'ON FILE AT OUR FACILITY.
Part Number _ _ _ _ _ _ _ _ _ _ __
P.O. Number _ _ _ _ _ _ _ _ _ _ __
Date Code(s) _ _ _ _ _ _ _ _ _ _ __
QUALITY ASSURANCE

Lot. Code(s)

8-12

RE~RESENTATIVE

National's A + Program
A + Program: A comprehensive program that utilizes
National's experience gained from participation in the
many I Militaryl Aerospace programs.
A program that not only assures high quality but also increases the reliability of molded integrated circuits.
The A +' program is intended for users who cannot perform
incoming inspectiolJ of ICs or do not wish to do so, yet need
significantly better than usual incoming quality and higher
reliability levels for their standard integrated circuits.
Users who specify A + processed parts will find that the
program:

The concept of reliability, on the other hand, refers to how
well a part that is initially good will withstand its environment. Reliability is measured by the precentage of parts that
fail in a given period of time.
Thus the difference between quality and reliability means
the ICs of high quality may, in fact be of low reliability, while
those of low quality may be of high reliability.
Improving the Reliability of Shipped Parts
The most important factor that affects a part's reliability is
its construction: the materials used and the method by
which they are assembled.
Reliability cannot be tested into a part. Still, there are tests
and procedures that an IC vendor can implement which will
subject the IC to stresses in excess of those that it will endure in actual use, and which will eliminate marginal, shortlife parts.
In any test of reliability the weaker parts will normally fail
first. Further, stress tests will accelerate, or shorten, the
time of failure of the weak parts. Because the stress tests
cause weak parts to fail prior to shipment to the user, the
population of shipped parts will in fact demonstrate a higher
reliability in use.
National's A + Program
National has combined the successful B + program with the
Militaryl Aerospace processing specifications and provides
the A + program as the best practical approach to maximum quality and reliability on molded devices. The following
flow chart shows how we do it step by step.

• Eliminates incoming electrical inspection.
• Eliminates the need for, and thus the added cost of, independent testing laboratories.
• Reduces the cost of reworking assembled boards.
• Reduces field failures.
• Reduces equipment down time.
'. Reduces the need for excess inventories due to yield
loss incurred as a result of processing performed at independent testing laboratories.
The A+ Program Saves You Money
It is a widely accepted fact that down-time of equipment is
costly not only in lost hours of machine usage but also costly in the repair and maintenance cycle. One of the added
advantages of the A + program is the burn-in screen, which
is one of the most effective screening procedures in the
semiconductor industry. Failure rates as a result of the burnin can be decreased many times. The objective of burn-in is
to stress the device much higher than it would be stressed
during normal usage.
Reliability vs. Quality
The words "reliability" and "quality" are often used interchangeably, as though they connoted identical facets of a
product's merit. But reliability and quailty are clifferent, and
IC users must understand the essential difference between
the two concepts in order to evaluate properly the various
vendors' programs for products improvement that are generally available, and National's A + program in particular.

SEM
Randomly selected wafers are taken from production regularly and subjected to SEM analysis.

Epoxy B Processing for All Molded Parts
At National, all molded semiconductors, including
ICs, have been built by this process for some time
now. All processing steps, inspections, and QC
monitOring are designed to provide highly reliable'
products. (A reliability report is available that gives,
in detail, the background of Epoxy B, the reason for
its selection at National, and reliability data that
proves its success.)

The concept of quality gives us information about the population and faulty IC devices among good devices, ~nd generally relates to the number of faulty devices that arrive at a
user's plant. But looked at in another way, quality can instead relate to the number of faulty ICs that escape detection at the IC vendor's plant.
It is the function of a vendor's Quality Control arm to monitor
the degree of success of that vendor in reducing the number of faulty ICs that escape detection. Quality Control does
this by testing the outgoing parts on a sampled basis. The
Acceptable Quality Level (AQL) in turn determines the stringency of the sampling. As the AQL decreases it becomes
more difficult for defective parts to escape detection, thus
the quality of the shipped parts increases.

Six Hour, 150'C Bake
This stress places the die bond and all wire bonds
into a combined tensile and shear stress mode, and
helps eliminate marginal bonds and electrical connections.
Five Temperature Cycles (70'C to 100'C)
Exercising each device over a 100' temperature
range provides an additional die and package
stress.

8·13

~

:IE

(J

National's A + Program (Continued)

.>0

==
:s

.!!
'ii
II:
.c

m

%

High. Temperature (100"C) Functional Electrical
Test
A high temperature test with voltages applied
places the die under the most severe stress possible. The test is actually performed at 100"C-1S"C
higher than the commercial ambient limit. All devices are thoroughly exercised at the 100"C ambient.

Here are the
gram:

ac sample plans used in our A +

Test
Electrical Functionality
Parametric. DC
Parametric. AC
Electrical FunCtionality
Parametric. DC
Mechanical
Critical
Major

Electrical Testing
Every device is tested at 2S"C for func1ional and DC
parameters.
Burn-In Test.
Each device is burned-in for 160 hours at a minimum junction temperature of + 12S"C or under
equivalent conditions of time and temperature. as
established by a time-temperature regression curve
based on 0.96eV activation energy. All burn-in done
under steady-state conditions unless otherwise
specified.
DC Functional and Parametric Tests
These room-temperature functional and parametric
tests are the normal. final tests through which all
National products pass.
Thermal Shock Monitor
Samples from each package type
are selec1ed at random· each
week and submitted to cycles of
liquid to liquid thermal shock -6S"C to + ISO"C. In
addition. samples are selec1ed every four weeks
and subjected to 2000 temperature cycles of O"C to
+2S"C.
Tighter-than-normal QC Inspection Plans
Most vendors sample inspect outgoing parts to a
0.3% AQL. When you specify the A+ program. we
sample your parts to a 0.03S% AQL at room temperature and O.OS% AQL at TA Max. This eight
times tightening (from 0.3 to 0.03S% AQL) coupled
with three 100% electrical tests. dramatically reduces the number of "escapes" and allows us to
guarantee the AQLs listed below.
Ship Parts

8-14

Temperature
2S"C }
2S"C
2S"C
At each temperature}
extreme.

test pro-

AQL
0.03S%
0.1 %
O.OS%
0.01 %
0.28%

National's B + Program
B + Program: a comprehensive program that assures high
quality and high reliability of molded integrated circuits.

Quality Improvement
When an IC vendor specifies 100 percent final testing of its
parts' then, in theory, every shipped part should be a good
part. However, in any population of mass-produced items
there does exist some small percentage of defective parts.

The B + program improves both the quality and the reliability of National's digital, linear, and CMOS Epoxy B integrated
circuit products. It is intended for the manufacturing user
who cannot perform incoming inspection of ICs, or does not
wish to do so, yet needs significantly-better-than-usual incoming quality and reliability levels for standard ICs.

One of the best ways to reduce the number of such faulty
parts is, simply, to retest the parts prior to shipment. Thus, if
there is a one percent chance that a bad part will escape
detection initially, retesting the parts reduces that probability
to only 0.01 percent. (A comparable tightening of the
group's sampled-test plan ensures the maintenance of the
improved quality leveL)

Integrated circuit users who specify B + processed parts
will find that the program:

ac

• Eliminates incoming electrical inspection.
• Eliminates the need for, and thus the added cost of, independent testing laboratories.

National's B + Program Gets It All Together
We've stated that the B + program improves both the quality and the reliability of National's molded integrated circuits,
and pOinted out the difference between those two concepts.
Now, how do we bring them together? The answer is in the
B + program processing, which is a continuum of stress and
double testing. With the exception of the final
inspection, which is sampled, all steps of the B + process are
performed qn 100 percent of the program parts. The follow'
ing flow chart shqws how we do it, step by step.

• Reduces the cost of reworking assembled boards.
• Reduces field failures.
• Reduces equipment down time.
Rella!Jlllty Savea You Money

ac

With the increases population of integrated circuits in modern electronic systems has come an increased concern with
IC failures in such systems.
.
And rightly so, for at least two reasons.
First of all, the effect of component reliability on system
reliability can be quite dramatic. For example, suppose that
you, as a system manufacturer, were to choose an IC that is
99 percent reliable. You would find that if your system used
only 70 such ICs, the overall reliability of the system's IC
portion would be only 50 percent. In other words, only one
out of two of your systems would operate. The result? A
system very costly to produce and probably very difficult to
sell.

SEM
Randomly selected wafers are taken from production regularly and subjected to SEM analysis.

Epoxy B Processing for All Molded Parts
At National, all molded semiconductors, including
ICs, have been built by this process for some time
now. All processing steps, inspections, and
monitoring are designed to provide highly reliable
products. (A reliability report is available that gives,
in detail, the background of Epoxy B, the reason for
its selection at National, and reliability data that
proves its success.)

Secqndly, whether the system is large or small you cannot
afford to be hounded by the spectre of unnecessary maintenance costs. Not only because labor, repair, and rework
costs have risen-and promise to continue to rise-but also
because field replacemenf may be prohibitively expensive. If
you ship a system that contains a marginally-performing IC,
an IC that later fails in the field, the cost of replacement may
be-literally-hundreds of times more than the cost of the
failed IC itself.

ac

Six Hour, 150"C Bake

Improving The Reliability of Shipped Parts

This stress places the die bond and all wire bonds
into a combined tensile and shear stress mode, and
helps eliminate marginal bonds and electrical connections.

The most important factor that affects a part's reliability is
its construction: the materials used and the method by
which they are assembled.
Now, it's true that reliability cannot be tested into a part.
Still, there are tests and procedures that an IC vendor can
implement, which will subject the IC to stresses in excess of
those that it will endure in actual use, and which will eliminate most marginal, short-life parts.

High Temperature (100'C) Functional Electrical
Test
A high temperature test such as this with voltages
applied places the die under the most severe stress
possible. The test is actually performed at 100'C-

In any test for reliability the weaker parts will normally fail
first. Further, stress tests will accelerate, or shorten, the
time to failure of the weak parts. Because the stress tests
cause weak parts to fail prior to shipment to the user, the
population of shipped parts will in fact demonstrate a higher
reliability in use.

Five Temperature Cycles (70"C to 100'C)
Exercising each device over a 100' temperature
range provides an additional die and package
stress.

8-15

National's B + Program (Continued)
15°C higher than the commercial ambient limit. All
devices are thoroughly exercised at the 100"C ambient. (Even though Epoxy B processing has virtually eliminated thermal intermittents, we perform this
test to ensure against even the remote possibility of
such a problem. Remember, the emphasis in the
B + program is on the elimination of those marginally-performing devices that would otherwise lower
field reliability of the parts.)

DC Functional and Param.trlc T.sta
These room-temperature functional and parametric
tests are the normal, final tests through which all
National products pass.

Th.rmal Shock Monitor
Samples from each package type are
selected at random each week and
submitted to 100 cycles of liquid to liquid thermal shock -65°C to + 150"C.
In addition, samples are selected every
four weeks and subjected to 2000 temperature cycles of O"C to + 25°C.
nght.....than·normal QC lnapectlon Plans
Most vendors sample inspect outgOing parts to a
0.3% AOL. When you specify the B + program, we
sample your parts to a 0.035% AOL at room temperature and 0.05% AOL at TA Max. This eight
times tightening (from 0.3 to 0.035% AOL) coupled
with two 100% electrical tests, dramatically reduces the number of "escapes" and allows us to guarantee the AOLs listed below.
Ship Parts

Here are the
gram:

ac sampling plans used in our B + test pro-

Test
Electrical Functionality
Parametric, DC
Parametric, AC
Electrical Functionality
Parametric, DC
Mechanical
Critical
Major

T.mperature

~::~

}

25°C
At each temperature}
extreme.

AQL
0.035%
0.1%
0.05%

0.01%
0.28%

8·16

II RELIABILITY REPORT
Reliability

of
Advanced Low Power Schottky
(ALS) Devices

Prepared By:

Approved by:

J. Huljev-Reli

8·17

~

RELIABILITY REPORT
ALS CHARACTERISTICS AND PROCESS OVERVIEW
The primary reasons for the popularity of LS logic circuits are:
-Improved speed-power product
-Exce"ent reliability
-Functional equivalency with older TTL products
The LS family was developed to meet the needs of system designers through the 1970s and 1980s, with regard
to reduced propagation delays and power dissipation.
The Advanced Low Power Schottky (ALS) family was designed to meet the needs of the next generation of
systems. These systems wi" require higher performance than is cur.rently available with standard Low Power
Schottky.
The ALS family offers the system designer the next generation state-of-the-art digital products. ALS devices
operate at one-half the prop€lgation delay and one-half the power of the LS family circuits.
The ALS family is also backed by National's commitment to be an industry leader in quality and reliability, a
commitment that National takes very seriously!
Key Physical Features Are:

The Key Features of the ALS Family Are:
. 1. Improved propagation delay (50% of LS)

1. Oxide isolation

2. Improved power dissipation (50% of LS)

2. Walled emitters

3. Improved input characteristics
-PNP inputs for reduced IlL current (Fan-In)
-ESD protection
-Thresholds typically 1.4 volts

3. 2.5 micron emitter widths
4. Ion implanted
5. 5 GHz Ft transistors

4. Improved line driving capability
5. Reduced supply current spikes
ALS

LS

IMPACT

Oxide isolation

Junction isolation

Reduced capacitance
Smaller geometries
Improved propagation

Implanted transistor

Diffused transistor

Shallow junctions
Improved uniformity
Less thermal damage

Composed geometries

Non-composed

Self-alignment

Thin EPI

Thick EPI

Reduced capaCitance
Improved propagation
Improved reliability

Nitride passivation
·NCSpec
Fu" temperature range
Fu" Vee range
50 pF load
DM74ALS Vee
4.5 to 5:5V

A/C Spec
25 degrees
5.0 volts
15 pF load
DM74LS Vee
4.75 to 5.25V

8·18

~

RELIABILITY REPORT
Cross Sectional View of the ALS Process:
Emitter
Schottky
Barrier
Diode

[COllector {OXide
Metal

n+

Oxide
Isolation

n Epitaxial Layer

iH
Collector
Channel
Stop

Oxide
Isolated
Transistor

Oxide
Isolation

p+

~Channel
Stop

p Substrate

Top View:
Oxide
Isolated

Junction
Isolated

r.,....---..,.;-]
Schott~y

I

Schottky

. Basel

I Emitter
.!.

T

BaseI

•
•
•
•

Reduced geometry
Walled emitter
Low capacitance
Improved speed

I
L

LS

4.68 mil2
0.67 mil2.
0.16 mil2

=i= Emitter

Collector·

l.!~----'~

-

I

-,

r

-

Collector

.J

ALS

Device Area
Base Area
Emitter Area

"

8·19

2.03 mil2
0.24 mil2
0.03 mil2

~

RELIABILITY REPORT
Typical Circuit Schematic:
Vee

40Kn

80Kn 15Kn

2811

Out

In

Resistor Values (ll)

ALS04

Protection from Negative Transients:
The high transition rates associated with oxide-isolated logic families can generate a -2.SV reflection when
terminated into a high impedance.
Schottky clamp diodes are provided on both the input and outputs of all devices to limit such reflection. Clamp
diodes may have to handle peak currents of 30 to 60 mAo Substrate junctions will become forward biased at
these currents.
If substrate junction becomes forward biased, it is possible to produce parasitic transistor action which can
cause functional or parametric problems during the time span of the reflection.

8-20

II RELIABILITY REPORT
Parasitic Failure Modes:

nEpi

n Epi

n+

Adjacent Input
or Output

Negative Current
Transient

Internal
Transistor Collector

•
I

•I

I

I
I

Y-

n+

pSubstrate

nEpi

Oxide
Isolation

•
I

•I

I
I

I
I

n+

Y

Parastic transistor to adjacent input can cause input leakage far in excess of I'H spec.
Parasitic transistor to internal collector can cause outputs to change state and flip-flops to change state.

Transient Proteciion:
Input or
Output

nEpi

nEpi

n+

n+

______

~,---J

I

n+

,

~

I

__ __ __
~,

~

I

~ _____ ~

~-----J

p Substrate
In the case of ALS devices, transient protection is provided by a grounded buried n+ ring on all input and output
epi islands.

8·21

•

Ii RELIABILITY REPORT
. Improved Input Characteristics:
r-----4~.I\A.,....40Kn

ALS
Equivalent Input Circuit
• PNP inputs for reduced input current typical IlL of -10 JJ.A
• Two diode equivalent input threshold typically 1.4V
• ESD protection

.

,

Improved Input Threshold:

=

4

~

..
..

Vee
5V
TA = 25°C
10H Applied:
AS804A = 50

3

n to GND

LS041 ALS04 = 8 kn to GND

GI
III
II

ALS37 (ALS1000) = 8 kn to GND

"0

>

2
LS04/ALS04/ALS37 (ALS1000)

:I

Do

.5

->

'Asa04A
1

o

0.5

1
Vo -

1.5

2

Output Voltage IV)

Transfer Function (Room Temperature)
~

8-22

2.5

II RELIABILITY REPORT
Improved Lower Output Characteristic:

!
C

..
...c

GI

15Kn

180

140

~

(,)

~

100

.

60

....
..
0

~

Do
~

0

D4

I

...

-

~

20
0

--

Vo -

ALS

1.0

2.0

3.0

Output Voltage (V)

Feedback Diode 0 3 provides additional base drive for output transistor

Darlington Upper Output Characteristic:
4

~
II
aI

.l!

3

Ci

AS Bus Driver Outputs

=

(AS8~4A)

Vee
5 V
TA = 25°C

>
~

aI

Z

..o;

2

Do

AS/ALS Standard
and Buffer Outputs
(ASOO, ALS04)

:::I

I

1

:I:

o

>

o

20

60

40
10H -

80

100

Output High Current (mA)

Output High Characteristics

8·23

120

140

160

•

, ~ RELIABILITY REPORT
Reliability Test Results:
Accelerated operating life testing at elevated temperatures is a principal method of simulating long-term
operation within a short period of time. This rnethod is particularly useful because it provides a means of
accelerating time-to-failure of temperature-sensitive failure mechanisms. As a result, data is gathered for
failure rate predictions at any operating field ambient.
The following tests have been conducted at an ambient temperature (TA) of 150°C with devices biased at a
maximum voltage of 5.5 volts. Complete functional and parametric testing to data sheet specifications was
performed at reported data points ..

TABLE I.
150°C High Temperature Bias Reliability Test Results '
NO.
LEADS

DEVICE

DATE
CODE· 168 Hours

14
14
20
16

DM74ALSOON
DM74ALS04N'
DM74ALS373N
DM74ALS137N

RESULTS
500 Hours 1000 Hours

8228
8235
8237
8239

0/83
0/90
0/100
0/90

0/83
0/90
0/100
0/90

0/83
0/90

Total:

0/363

0/363

0/363

REL.
LOT NO.
22128
22188
22192
22214

01100

0/90

Total device hours at 150°C: 363,000; Actual Failure Rate = 0/363,000 device hours.

Table 2 shows failure rates calculated with 60% confidence at stress, and at two different temperatures
and activation engeries.

TABLE II.

DEVICE ACTUAL NO.
HOURS OF REJECTS
363,000
363,000

0
0

FAILURE RATE AT
STRESS, 150°C
ACTIVATioN
%/1k HRS.
PPM ENERGY,eV
0.25
0.25

2.5
2.5

0.4
0.99

CALCULATED FAILURE RATE AT
125°C
85°C
%/1k HRS. . PPM
%/1kHRS . PPM
0.126
0.045

1.26
0.45

0.034
0.0018

0.34
0.018

The above data can be further extrapolated to· lower temperatures at different activation energies, as
illustrated in the graph on the following page showing failure rate in %/1000 Hrs. and PPM units.

8-24

II RELIABILITY REPORT
I

I

.3

.25~
.2

I

I

I

I

I

I

I

I

I

I

__ 2

.15
.1
.09
.08
.07
.06
.05
.04
.03

! i

~

"o
l:

•
.0003

i

--.---+-\--r--'--:---t-'--+--+-

;i

•0002

-t::

--:01"

.0001

150

140

- --·::::r- f-F---

T-=r--:;-~H-

--:~j-::' ~ .----.--120
125

.j___-;-_\~I----J--!
_
'\
.

- ; - --

-1-1-+

100

85 80

1\

-- : --::\:: --- -~

-.

I

-~

---r . -

-= -==- -==-r:-:::-C=-__ ':::,=---=t~\ -:.:~-~ -:: : -:. .-60

40

Temperature

At 60% confidence limit, using three different activation energies, above is the failure rate in % per 1000
Hours and also in PPM.

8-25

·c

rJ RELIABILITY REPORT
Temperature Humidity Bias Test

The Temperature and Humidity test involves stress levels considerably in excess of the field-use levels
encountered by a device. The test is intended to trigger moisture-related failure mechanisms occurring
over a period of months or years in the field.
.
These tests have been conducted at an ambienttemperature (T A) of 85° C and a relative humidity of 85%.
Complete functional and parametric testing to data sheet specifications is performed at reported data
points.

TABLE III.
85°C/85% RH Temperature Humidity Bias Test Results

DEVICE

DM74ALSOON
DM74ALS04N
DM74ALS373N
DM74ALS137N

NO.
LEADS

DATE
CODE

168 Hours

RESULTS
500 Hours 1000 Hours

14
14
20
16

8228
8235
8237
8239

0/100
0/100
0/66
0/200

0/100
0/100
0/66
0/200

0/100
0/100
0/66
0/200

Total:

0/466

0/466

0/466

REL.
LOT NO.

22128
22188
22192
22214

Actual Failure Rate = 0/466,000 device hours.

Conclusion

Reliability performance of ALS products in Epoxy B molded packages on accelerated reliability tests is
excellent and will insure field reliability performance under the most adverse applications.

8·26

II RELIABILITY REPORT
High Temperature Bias Test Burn-In Circuits:

+5.5V

20

2.7kl1

"

2.7kH

16

12

•

DIP-14
11
TOP VIEW

5
2.7kll

1

17
2.7kll

3

2.7k!!

18

2.7kH

13

2
2-7kll

2.7kll

,.

+55

501!!

'-'

1

,.

6

•

7

8

TOP

2.7kl!

15

,.

VIEW

2.7kJ!

13

2.7k!!

12

,.

2.7k!l

':'

DM74ALSOO

11

DM74ALS373

DM74ALS04
DM74ALS131

Temperature Humidity Bias Test Burn-in Circuits:

+5.5V

+S.5Y

TOP
VIEW

+5.SY

1.

1.

13

13

12

12

11

,.

TOP
VIEW

5

11

,.

DIP-16
TOP VIEW

+S.5Y

16

20

15

1.

1.

18
17

13
TOP
VIEW

12
11

,.

OM74ALSOO

':'

DM74ALS04

8-27

':'

DM74ALS137

':'

15

,.
13

,.
':'

16

12
11

DM74ALS373

u0.--------------------------------------------------------------------------Thermal Ratings for Ie's
...o MAXIMUM POWER DISSIPATION
safe operating area of the device. Additional constraint

o
c
:;::
co

a:

To insure reliable long term operation of its Integrated Circuits. National Semiconductor has specified maximum junction temperature (Tj) limits. These limits are at 150°C for
circuits packagea in a molded dual-in-line. package (Epoxy
B). and 175°C for all other package types.

co

Maximum power dissipation (PO) of an integrated circuit is

C)

are Maximum Power Dissipation and Maximum Operatin
Temperature (T A). These parameters may be determine.
from device data sheets. For this example. Po (MAX) = 301
mW and TA(MAX) = 70°C.
Point "A" in Figure 1 is an operating point corresponding tl
TA = 50°C and Po = 100 mW. Determine device junctior
temperature by projecting a line from point "A". parallel t(
the Maximum Power Rating curve. until it intersects thE
horizontal axis: Tj is determined from the point of intersec
tion with the horizontal axis. For this example. Tj is 45°C.

by maximum allowable junction temperature of the
E limited
silicon die. and thermal resistance (OJ-X) of the package.
Q)

.s:.
I-

Figure 1 illustrates'the relationship between power dissipation and iunction temperature.
The line indicating "Maximum Power Rating of Package" is
projected from the maximum junction temperature limit
(150°C in this example) at a slope corresponding to the
package thermal resistance (II OJ- X). Below this line is the

THERMAL INFORMATION
Figure 2 illustrates thermal resistance characteristics for
Integrated Circuit packages.

0.7

~.
2:
Q

0.6
0.5

.............

;:

Bi'"Q
"a;

'"
;;:
~

............. 414 -t

0.4

.

~

'll7 PO/t<

0.3
C.2
A

0.1

o

"'11

I~c

o

25

I
~

50

.............
~
100

75

150

125

175

TEMPERATURE I CI

FIGURE 1. Power Dissipation vs Temperature

1.8
LEADS

PACKAGE

1.6
G 110 HI
H ITO 51
J It. DIP)
N Ir.l\lld,·oj,

1.4

'J x I C!W)
JUNCTION TO AMBIENT
THERMAL RESISTANCE

"

100
200

11 l!l
101.111

HO

170
1,lQ

HO

~

1.2

00

2:

~,...--"~~-~.t--:--- ~~!I~~d ifhDe~e a:rl~~s~:ec;Ie:.lr~7~:ler~:~:

Q

;: 1.0

'""-

BiQ

deVices, and reflect a 90% confidence
level. Refer to data sheels for speCIfic
-~~~""f-~,------ deVice mformatlOn. Measurements were

0.8

a;

made

~
Q

mID sprinted CirCUit board.

"-

11\

stdl air With package soldered

0.6
0.4
0.2

25

50

75

100

125

150

TEMPERATURE lOCI

FIGURE 2. Maximum OJ-X Values for Ie Packages

8-28

175

200

:::l

Idustry Package Cross Reference Guide

C.
c::::

(II

NSC
(OM) (1)

~=
CJ

Signetics
(N)

Fairchild

-

Motorola
(SN)

TI
(SN)

AMD
(AM)

..,

'<

"tI

Q)
(')
;:tr;:"
Q)

Glass/Metal
Flat-Pack

F

Q

F

F

F, S

F

(Q

CD
C')

(3
(II
(II

14 and 16-Lead
Low-Temperature
Ceramic DIP

:::tI
CD
CD

-

J

F

R,D

U

(;

J

:::l

(')

CD

C>
c::::

c:
CD

1MMMI

I

14 and 16-Lead
Plastic DIP

Low Temperature
Glass Hermetic
Flat Pack

N

W

V, B

T, P

P

P, N

PC

F

F

W

FM

Note 1: Denotes common suffix for logic products.

•
-

8-29

0r---------------------------------------------~--------------------------------------~

.§o ~National
.
~ Semiconductor

all dimensions are In inches (millimeters)

i

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PIN NO. I

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~"' ' T.T .T,. ;=m=m=m=; ; : ;rn: ;rn;T,; =; ; 'T.i "' "' "' . ,. ,;,; olJ!:' ~!

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SEATING
PLANE

TYP

OUTWARDTY,

40·Lead Hermetic DIP (D)
NS Package Number D40C

002&
(0835)

RAn

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ii'.iiii

MAX BOTItENDS

14·Lead CERDIP (J)
NS Package Number j14A

.02.

ID:I

o 310-U10

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I
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NS Package Number J16A

8·30

0.IZ5
(2.1151
MIN

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NS Package Number J18A

.!!!!
(4512)

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.

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20·Lead CERDIP (J)
NS Package Number J20A

I

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NS Package Numbe,r J22A
8·31

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