1984_RCA_CMOS_Microprocessors_Memories_and_Peripherals 1984 RCA CMOS Microprocessors Memories And Peripherals
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DATABOOK
Solid
State
2 __________________________________________________________________
Information furnished by RCA is believed to be accurate and reliable.
However, no responsibility is assumed by RCA for its use; nor for any
infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise
under any patent rights of RCA.
The device data shown for some types are indicated as product
preview or advance information/preliminary data. Product preview
data are intended for engineering evaluation of product under development. The type designations and data are subject to change or
withdrawal, unless otherwise arranged. Advance Information/prelimInary data are intended for guidance purposes in evaluating new product
for equipment design. Such data are shown for types currently being
designed for inclusion in our standard line of commercially available
products. No obligations are assumed for notice of change of these
devices. For current information on the status of product preview or
advance information/preliminary data programs, please contact your
local RCA sales office.
Copyright 1984 by RCA Corporation
(All rights reserved under Pan-American
Copyright Convention)
Trademark(s)®Registered
Marca(s) Registrada(s)
Printed in USAl10-84
4
CMOS Microprocessors, Memories and Peripherals
Index to Products
Part
No.
CDM5332
CDM5332PE
CDM5333
CDM5364,A
CDM5365
4Kx8 ROM
4Kx8 ROM
4Kx8 ROM
8Kx8 ROM
8Kx8 ROM
Page
No.
653
84
653
659
665
File
No.
1366
1552
1366
1467
1466
CDM6116A
CDM6117A-3
CDM6118A-3
CDM6264
CDM53128
2Kx8 RAM
2Kx8 RAM
2Kx8 RAM
8Kx8 RAM
16Kx 8 ROM
574
579
584
589
670
1472
1509
1508
1505
1454
CDM53256
CDP1802A, AC
CDP1802BC
CDP1804AC
CDP1804PCE
32Kx8 ROM
8-Bit Microprocessor
8-Bit Microprocessor
8-Bit Microcomputer
8-Bit Microcomputer
675
15
36
56
84
1453
1305
1342
1371
1552
CDP1805AC
CDP1806AC
CDP1822,C
CDP1823,C
CDP1824,C
8-Bit Microprocessor
8-Bit Microprocessor
256x4 RAM
128x 8 RAM
32 x 8 RAM
85
85
595
601
607
1370
1370
1074
1198
1103
CDP1826C
CDP1831,C
CDP1832,C
CDP1833,C,BC
CDP1834,C
64x 8 RAM
512 x 8 ROM
512 x 8 ROM
1K x 8 ROM
1K x 8 ROM
613
680
684
687
691
1311
1104
1145
1135
1143
CDP1835C
CDP1837C
CDP1851,C
CDP1852,C
CDP1853,C
2Kx8 ROM
4Kx8 ROM
Programmable I/O Interface
Byte-Wide I/O Port
1 of 8 Decoder
694
700
291
303
311
1267
1381
1056
1166
1189
CDP1854A,AC
CDP1855,C
CDP1856,C
CDP1857,C
CDP1858,C
Programmable UART
8-Bit Programmable Multiply/Divide Unit
4-Bit Bus Buffer/Separator
4-Bit Bus Buffer/Separator
4-Bit Latch & Decoder Memory Interface
315
332
345
345
350
1193
1053
1192
1192
1127
CDP1859,C
CDP1863,C
CDP1866,C
CDP1867,C
CDP1868,C
4-Bit
8-Bit
4-Bit
4-Bit
4-Bit
350
357
363
363
363
1127
1179
1112
1112
1112
CDP1869C
CDP1870C
CDP1871A,AC
CDP1872C
CDP1873C
Video Interface System (VIS)
Video Interface System (VIS)
Keyboard Encoder, ASCIII Hex
High-Speed 8-Bit Input Port
High-Speed Decoder 1 of 8
371
371
390
398
403
1197
1197
1374
1255
1248
CDP1874C
CDP1875C
CDP1876C
CDP1877,C
CDP1878,C
High-Speed 8-Bit Input Port
High~Speed 8-Bit Output Port
Video Interface System (VIS)
Programmable Interrupt Controller (PIC)
Dual-Timer Counter
398
398
371
407
416
1255
1255
1197
1319
1341
Description
Latch & Decoder Memory
Programmable Counter
Latch & Decoder Memory
Latch & Decoder Memory
Latch & Decoder Memory
Interface
Interface
Interface
Interface
6 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
Product Overview
RCA offers an all CMOS line of microprocessor,
microcomputer, memory, and peripheral integrated
circuits for use in a broad range of diverse industrial, consumer, and military applications. These
devices offer the user all the advantages unique to
CMOS technology, including:
•
Low power drain-makes CMOS integrated
circuits a natural choice for battery-operated
systems, battery backed-up systems, and systems in which heat dissipation is a prime
consideration.
•
•
High noise immunity and wide operating temperature range (-55°C to +125°C)-allows
CMOS integrated circuits to be used in the
most demanding industrial environments.
Wide operating voltage range-reduces the
need for expensive regulated power supplies
and there-by allows the design engineer
greater freedom to concentrate on other aspects of system design.
CDP1800 Series
The RCA CDP1800 series offers the most complete line of CMOS microprocessor, microcomputer
and associated memory and peripheral devices in
the industry. The heart of the series is the
CDP1802A central processing unit (CPU). This
unit, which features CMOS register-based architecture, offers 16 internal registers to facilitate data
manipulation and to reduce the need for additional
devices. The need for external devices is even
further reduced by use of on-chip clock, DMA,
and single phase operation.
The CDP1804A microcomputer incorporates all
the features of the CDP1802A augmented by additional hardware and increased performance capabilities. The additional hardware includes 2-kilobytes of ROM, a 64-byte RAM array, an 8-bit
presettable down-counter, and 32 additional software instructions which add subroutine call and
return capability, enhance data transfer manipulation, control counter modes and interrupt arbitration and provide BCD arithmetic capability.
Also available, are two other 8-bit microprocessors
that are functional and performance enhancements
of the CDP1802A. The CDP1805A features an onboard RAM and CounterlTimer. The CDP1806A
has all the features of the CDP1805A, but contains
no on-board RAM.
The microprocessor and microcomputer devices
use CMOS technology, designed on a single chip
to maintain low power drain. They are intended for
multi-system applications requiring general-purpose CPU-s, large memory address space, and
extensive external I/O for use with optimized
peripherals.
RCA's CDP1800-series memory/microprocessor
product line offers the system designer exceptional
flexibility in hardware/software tradeoffs. In addition to microprocessors and microcomputers, this
product line includes a hardware multiply/divide
unit (MDU), a programmable I/O, video and key
board interface circuits, latches and decoders, universal asynchronous receiver-transmitters (UARTs),
buffers, separators, and a broad complement of.
directly interfaceable random-access memories
(RAMs) and read-only memories (ROMs).
CDP6800 Series
RCA also offers the CDP6800 family of CMOS
microprocessors, microcomputers, and peripherals
primarily intended for single-chip system applications requiring limited space, minimum memory,
on-board I/O, and minimum external I/O. The
series offers pin-for-pin replacements for Motorola's MCI46805, MC68HC05 and MC68HC04 series
of microprocessors, microcomputers, and peripherals. This family of parts includes the CDP6805E2
8-Bit Microprocessor; the CDP6805F2 8-Bit Microcomputer (1 K ROM); the CDP6805G2 8-Bit Microcomputer (2K ROM); the CDP68HC05D4 and
CDP68HC05D2 8-Bit Microcomputers featuring
on-chip ROM, RAM, 16-bit timer, asynchronous
serial communications interface (CDP68HC05D2),
synchronous serial peripheral interface, and 24 bidirectional I/O lines; the CDP68HC04P2 and
CDP68HC04D4P3 8-Bit Microcomputers containing on-chip clock, ROM, RAM, I/O and timer; the
CDP68HC68T1 Serial Real-Time Clock/RAM; the
CDP68HC68R1 and CDP68HC68R2 Serial Peripheral Interface (SPI) RAMs; the CDP68HC68A1
10-Bit A/D Converter; the CDP6818 Real-Time
Clock plus RAM; the CQP6823 Parallel Interface
I/O; and the CDP65516 2Kx8 Mask Programmable
ROM. Additional types will be added as they become available.
General-Purpose Memories
In addition to the memories designed to interface
directly with CDP1800-series microprocessors and
microcomputers, RCA also offers a line of generalpurpose memories. These memories incl,ude industry-standard ROMs that can be mask-programmed
to meet customer application requirements. These
ROMs feature: low-power CMOS technology with
high-noise immunity and full-temperature-range
characteristics; space-efficient NAND stack memory cells providing small chip size for cost effectiveness; and JEDEC standard pin outs for interchangeability with industry-standard NMOS ROMs and
EPROMs.
The list of memories also includes fully static
CMOS RAMs with densities up to 8K-bytes, low
operating power, low standby current, and memory retention for 2-volt minimum standby battery
voltage.
Memory/Microprocessor
Surface-Mounted Packages
RCA's broad CMOS memory/microprocessor product line now includes standard CDP- and CDMseries chips in a new generation of IC miniaturized
packages.
Microprocessors, microcomputers, memories, and
peripherals are now offered in two versions of the
surface-mounted-package configuration as follows:
8
CMOS Microprocessors, Memories and Peripherals
Product Classification Chart
Part Number
Description
Page No.
Microprocessors
CDP6805E2
CDP6805E3
Timer
8-Bit with RAM and Counter/
Timer
8-Bit with RAM, 110, Counter/
Timer
8-Bit with RAM, 110, Counter/
Timer
15
36
85
CDP1804PCE
CDP68HC04P2
CDP68HC04P3
CDP68HC05C4
CDP68HC05D2
CDP6805F2
CDP6805G2
8-Bit with RAM,
Timer
8-Bit
8-Bit with RAM,
CounteriTimer
8-Bit with RAM,
CounteriTimer
8-Bit with RAM,
CounteriTimer
8-Bit with RAM,
CounteriTimer
8-Bit with RAM,
CounteriTimer
8-Bit with RAM,
CounteriTimer
201
CDP1856,C
CDP1857,C
8-Bit Programmable Multiply/
Divide Unit (MDU)
4-Bit Bus Buffer/Separator
4-Bit Bus Buffer/Separator
345
345
CDP1869C
CDP1870C
CDP1876C
Video Interface System (VIS)
Video Interface System (VIS)
Video Interface System (VIS)
371
371
371
CDP1855,C
332
234
ROM, Counter/
56
CDP1871A,AC Keyboard Encoder, ASC111 Hex
CDP1863,C
8-Bit Programmable Counter
Dual Counter-Timer
CDP1878,C
Real-Time Clock
CDP1879,C-1
Real-Time Clock with RAM,
CDP6818
ROM, I/O,
84
110
Dual Counter-Timer, MOTEL Bus
CDP6848,C
CDP68HC68T1 SPI Real-Time Clock
ROM, 110,
110
CDP1877,C
ROM, I/O,
113
CDP68HC68A1 SPI AID Converter
ROM, 110,
198
RAMs
ROM, I/O,
236
ROM, I/O,
262
CDP1822,C
CDP1823,C
CDP1824,C
CDP1826C
CDM6116A
CDM6117A-3
CDM6118A·3
CDM6264
MWS5101
MWS5101A
MWS5114
390
357
416
429
500
MOTEL Bus
Peripherals
CDP1851,C
CDP1852,C
CDP1872C
CDP1874C
CDP1875C
CDP6823
Programmable 110 Interface
Byte-Wide I/O Port
8-Bit Input Port
8-Bit Input Port
8-Bit Output Port
Parallel Interface
291
303
398
398
398
519
CDP1853,C
CDP1858,C
CDP1859,C
CDP1866,C
CDP1867,C
CDP1868,C
CDP1873C
CDP1881,C
CDP1882,C
CDP1883,C
CDP1854A, AC
CDP6402,C
CDP65C51
1 of 8 Decoder
4-Bit Latch & Decoder
4-Bit Latch & Decoder
4-Bit Latch & Decoder
4-Bit Latch & Decoder
4-Bit Latch & Decoder
1 of 8 Binary Decoder
6-Bit Latch & Decoder
6-Bit Latch & Decoder
7-Bit Latch & Decoder
Programmable UART
Programmable UART
Asynchronous Communications
Interface Adapter
Asynchronous Communications
Interface Adapter. (ACIA).
MOTEL Bus
311
350
350
363
363
363
403
445
445
451
315
456
464
CDP6853
Page No.
85
Microcomputers
CDP1804AC
Description
Peripherals (Cont'd)
CDP1802A,AC 8-Bit
CDP1802BC
8-Bit
CDP1805AC
8-Bit with RAM and Counter/
CDP1806AC
Part Number
548
Programmable Interrupt Controller
256x4
128x8
32 x 8
64x8
2Kx8
2K x 8
2K x 8
8Kx8
256x4
256x4
1K x4
CDP68HC68R1 SPI RAM 128-Bytes
CDP68HC68R2 SPI RAM 256-Bytes
533
482
407
480
595
601
607
613
574
579
584
589
628
635
642
621
621
Mask-Programmable ROMs
CDM53128
CDM53256
CDM5332
CDM5332PE
CDM5333
CDM5364,A
CDM5365
CPD1831,C
CDP1832,C
CDP1833,C,BC
CDP1834,C
CDP1835C
CDP1837C
CDP65516
16K x 8
32Kx8
4Kx8
4Kx8
4Kx8
8K x 8
8Kx8
512 x 8
512 x 8
1Kx8
1Kx8
2K x 8
4Kx8
2K x 8
670
675
653
84
653
659
665
680
684
687
691
694
700
706
10 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
Operating and Handling Considerations
RCA CMOS Integrated Circuits
This Note summarizes important operating recommendations and precautions which should be followed in
the interest of maintaining the high standards of
performance of solid state devices.
The ratings included in RCA Solid State Devices data
bulletins are based on the Absolute Maximum Rating
System, which is defined by the following Industry
Standard (JEDEC) statement:
Absolute-Maximum Ratings are limiting values of
operating and environmental conditions applicable to
any electron device of a specified type as defined by its
published data, and should not be exceeded under the
worst probable conditions.
The device manufacturer chooses these values to provide
acceptable serviceability of the device, taking no
responsibility for equipment variations, environmental
variations, and the effects of changes in operating
conditions due to variations in device characteristics.
The equipment manufacturer should design so that
initially and throughout life no absolute-maximum value
for the intended service is exceeded with any device under
the worst probable operating conditions with respect to
supply voltage variation, equipment component variation,
equipment control adjustment, load variation, signal
variation, environmental conditions, and variations in
device characteristics.
It is recommended that equipment manufacturers
consult RCA whenever device applications involve
unusual electrical, mechanical or environmental operating
conditions.
General Considerations
The design flexibility provided by these devices makes
possible their use in a broad range of applications and
under many different operating conditions. When
incorporating these devices in equipment, therefore,
designers should anticipate the rare possiblity of device
failure and make certain that no safety hazard would
result from such an occurence.
The small size of most solid state products provides
obvious advantages to the designers of electronic
equipment. However, it should be recognized that these
compact devices usually provide only relatively small
insulation area between adjacent leads and the metal
envelope. When these devices are used in moist or
contaminated atmospheres, therefore, supplemental
protection must be provided to prevent the development
of electrical conductive paths across the relatively small
insulating surfaces.
The metal shells of the TO-5 style package often used
for integrated circuits usually has the substrate or most
negative supply voltage connected to the case. Therefore,
consideration should be given to the possibility of shock
hazard if the shells are to operate at voltages appreciably
above or below ground potential. In general, in any
application in which devices are operated at voltages
which may be dangerous to personnel, suitable
precautionary measures should be taken to prevent direct
contact with these devices.
Devices should not be connected into or disconnected
from circuits with th~ power on because high transient
voltages may cause permanent damage to the devices.
TESTING PRECAUTIONS
In common with many electronic components, solidstate devices should be operated and tested in circuits
which have reasonable values of current limiting
resistance, or other forms of effective current overload
protection. Failure to observe these precautions can
cause excessive internal heating of the device resulting in
destruction and/ or possible shattering of the enclosure.
Mounting
Integrated circuits are normally supplied with lead-tin
plated leads to facilitate soldering into circuit boards. In
those relatively few applications requiring welding of the
device leads, rather than soldering, the devices may be
obtained with gold or nickel plated Kovar- leads. * It
should be recognized that this type of plating will not
provide complete protection against lead corrosion in the
presence of high humidity and mechanical stress.
-Trade Name: Westinghouse Corp.
*Mil-M-38510A, paragraph 3.5.6.I(a), lead material
The aluminum-foil-lined cardboard "sandwich pack"
employed for static protection of the flat-pack also
provides some additional protection against lead
corrosion, and it is recommended that the devices be
stored in this package until used.
When integrated circuits are welded onto printed
circuit boards or equipment, the presence of moisture
between the closely spaced terminals can result in
conductive paths that may impair device performance in
high-impedance applications. Itis therefore recommended
that conformal coatings or potting be provided as an
added measure of protection against moisture penetration.
In any method of mounting integrated circuits which
involves bending or forming of the device leads, it is
extremely important that the lead be supported and
clamped between the bend and the package seal, and that
bending be done with care to avoid damage to lead
plating. In no case should the radius of the bend be less
than the diameter of the lead, or in the case of rectangular
leads, such as those used in RCA 14-lead and 16-lead
flat-packages, less than the lead thickness. It is also
extremely important that the ends of the bent leads be
straight to assure proper insertion through the holes in
the printed-circuit board.
Handling
All CMOS gate inputs have a resistor/diode gate
protection network. All transmission gate inputs and all
outputs have diode protection provided by inherent p-n
junction diodes. These diode networks at input and
12 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
Package and Ordering Information
Packages
D Suffix
Dual-In-Line Size-Brazed Ceramic Packages
D Suffix
Dual-In-Llne Welded-Seal Ceramic Packages
16-, 18-, 22-, 24-, 28-, and 40-lead versions
16- and 24-lead versions
E Suffix
Plastic Dual-In-Line Packages
N Suffix
Smail-Outline Plastic Package (S.O.P.)
16-, 18-, 22-, 24-, and 40-lead versions
24- and 28-lead versions
Q Suffix
Plastic Chip-Carrier
PACKAGE
Dual-In-Line Welded-Seal or
Side-Brazed Ceramic
Dual-In-Line Plastic
Small-Outline Plastic
Plastic Chip-Carrier
SUFFIX
LETTERS
D
E
N
Q
44-Lead version
Ordering Information
RCA CMOS microprocessor and memory integrated
circuits are available in one or more of the following
package styles and are identified by the Suffix Letters
indicated: dual-in-line side-brazed ceramic, dual-in-line
welded-seal ceramic, dual-in-line plastic, flat-pack ceramic,
leadless chip-carrier ceramic and in chip form. The
available package styles for any specific type are given in
the technical data for that type.
When ordering CMOS devices, it is important that the
appropriate suffix letter be affixed to the type number of
the device required. For example, a CDP1802A in a dualin-line ceramic package will be identified as the
CDP1802AD.
....
~
RCA CMOS 8-BIT MICROPROCESSORS/MICROCOMPUTERS
BUS
MUXI
NON
OPER.
TEMP.
RANGE
DEG.C
(MAX.
RATING)
-
NON
-55 to +125
-
40
a-Line
NON
-55 to +125
-
40
Q-Line
8
DIV.32
NON
-55 to +125
-
40
Q-Line
•
•
8
DIV.32
NON
-55 to +125
-
40
a-Line
DIV.32
NON
-55 to +125
-
40
a-Line
v
8
PROGRAM MUX
Oto+.70
-40 to + 85
16
40
DIRECT
ADDRESSABLE
EXTERNAL
MEM.
K-BYTES
ON-CHIP
RAM
BYTES
ON-CHIP
ROM
BYTES
CDP1802A
64
-
-
3.2
5.0n.5
CDP1802B
64
-
-
5.0
3.214.8
•
DEVICE
MAX.
CLOCK
FREQ.
MHz
INSTRUCTION
TIME
MINJMAX.
(PS)
CDP1804A
64
64
2048
5.0
3.2/16.0
CDP1805A
64
64
-
5.0
3.2116.0
CDPl806A
64
-
-
5.0
3.2116.0
112
-
5.0
2.0/10.0
CDP6805E2
CDP6805E3
8
64
112
-
5.0
INTERRUPTS
2.0/10.0
•
•
v
TIMERI
COUNTER
BITS
-
8
8
PRESCALER
PROGRAM
MUX
oto +
70
LATCHED
PIN
1/0 LINE COUNT
SERIAL
INTERFACE
(')
i:
13
40
16
28
oen
-40 to + 85
CDP6805F2
-
64
1089
4.0
2.0/10.0
v
8
PROGRAM
112
2106
4.0
2.0/10.0
v
8
PROGRAM
CDP68HC05D2*
-
96
2176
4.2
.95/5.23
v
16
PROGRAM
CDP68HC05C4*
-
176
4160
4.2
.95/5.23
v
16
CDP68HC04P2
-
32
1024
11.0
8.7/21.8
v
CDP68HC04P3
~
128
2048
11.0
8.7/21.8
v
CDP6805G2
(*)
(v)
Multiply Instruction in the 68HC05D2 and 68HC05C4
Vectored address
-
Oto + 70
-40 to + 85
i:
I
70
32
40
-55 to +125
24
40
PROGRAM
-
-55 to +125
24
40
8
PROGRAM
-
Oto+ 70
20
28
8
PROGRAM
-
Oto+ 70
20
28
oto +
SPI
SPIISCI
J'
I
jJ
i:
CD
3
o
i'
!
-:
:::!.
}
iil
iii'
16 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1802A, CDP1802AC
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VDD):
(All voltages referenced to VSS terminal)
CDPl802A .......................................................................................................-0.5 to +11 V
CDPl802AC ....................................................................................................... -0.5 to +7 V
INPUT VOL TAGE RANGE, ALL INPUTS ....................................................................... -0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ....•.•...•.....•........•........................................................ ±10 mA
POWER DISSIPATION PER PACKAGE (PD):
For T A=-40 to +60°C (PACKAGE TYPE E) ............................................................................. 500 mW
For TA=+60 to +85°C (PACKAGE TYPE E) ..................•............................ Derate Linearly at 12 mW/oC to 200 mW
ForTA=-55 to +l00°C (PACKAGE TYPE D) ............................................................................ 500 mW
For TA=+100 to +125°C (PACKAGE TYPE D) ............................................. Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA=FULL PACKAGE-TEMPERATURE RANGE ..................................................................... 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE D .............................................................................................. -55 to +125°C
PACKAGE TYPE E ............................................................................................... -40 to +85°C
STORAGE TEMPERATURE RANGE (Tstg) ......................................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16±1/32 in. (1.59±0.79 mm) from case for 10 s max. . ...................................................... +265°C
OPERATING CONDITIONSal TA=-40°C 10 +85°C
For maximum reliability operating conditions should be selected so that operation is always within the following ranges:
LIMITS
CONDITIONS
CHARACTERISTIC
VCCl
VDD
(V)
(V)
-
-
DC Operating Voltage
Range
Input Voltage Range
Maximum Clock Input Rise
or Fall Time, tr,tf
-
4 to 10.5
5
Minimum Instruction Time 2
5
10
5
Maximum DMA Transfer
5
Rate
10
Maximum Clock Input
5
5
Frequency, fCL, Load
CapaCitance (CLl=50 pF
10
CDP1802A
Min.
Max.
UNITS
CDP1802AC
Max.
Min.
4
10.5
4
6.5
VSS
VDD
VSS
VDD
-
1
-
1
5
4
2.5
-
5
-
-
·400
500
800
3.2
4
6.4
V
4 to 10.5
5
10
10
5
10
10
5
10
10
-
DC
DC
DC
-
-
400
DC
3.2
-
-
p.s
KBytes
per
second
-
MHz
lVCC must never exceed VDD.
2Equals 2 machine cycles-one Fetch and one Execute operation for all instructions except Long Branch and Long Skip, which require 3
machine cycles-one Fetch and two Execute operations.
.
~.
"
iii
LOAO CAPACITANCE (el.! ·50p!='
AMBIENT TEMPERATURE (TA,a 2eoc
I 7
d
"
~
•
6
4
~
%
~
~
~
~
~
~
~
AMBIENT TEMPERATURE (T A) - ·C
Fig. 2 - Typical maximum clock frequency
as a function of temperature.
~
25
50
75
100
I~
150
175
200
LOAD CAPACITANCE (CL1-pF
Fig. 3 - Typical transition time
capacitance.
VS.
load
18 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1802A, CDP1802AC
~!
Q
Ii
•
4
..
I
2
~1OO8
~
\0"
~
IB
5
4
~
NOTES:
.
2
~
!-
4 150
S
.-
V rL"
~ 100
r-t-r-~~
.~
~ef.'P'l"
~r:
~
4
ffi
~
it 12
~~
.
I
;,
-.lc,e
.
;;
I
~
~,"
."~
It f 4
~f 2
f . . .'Oe
AMBIENT TEMPERATURE (TA). 2e·c
!
AMBIENT TEMPERATURE (TA'- 25·C
/vnl"o"/
"~i
2
vK
I
••OJ ,
V
0.1
0.01
2
IDLE. "00" AT MCaDOo)
BRANCH ~"3707''Ar M (SI07)
4
4
,
.
I
CLOCk INPUT FREQUENCY
,
4
••
10
(fC~-MHz
SPEC
0
VALUE
AT eo pF
92CS- 29!!49
CL.!!IO pF
Fig. 6 - Typical power dissipation as a function of clock
frequency for BRANCH Instruction and IDLE instr~ction.
Fig. 7 - Typical change in propagation delay as a
function of a change in load capacitance.
,--_..J..._--"
MAG MA4 MA2 MAC
' - - - t + XTAL
CONTROL AND
TIMING LOGIC
SCOLSTATE
SCI) CODES
Q LOGIC
~~~~YSTEM
VWII)'IMING
NO} J:lO
NI
NZ
OMMANDS
Fig. 8 - CDP1802A block diagram.
tZCM-14."RI
CLOCK
ADDRESS __L-_H~I~B~Y~T~E__~______~L~OW~B~YT~E~______-L__~HI~B~Y~T~E__-L____--~L~OW~.~Y~TE~______~__
--'rlo....-_________
TPB _ _ _ _ _ _ _ _ _........r l...__________r L .
T P A . - - n_ _ _ _ _ _ _ _ _
~A------------i:::::~VA~L~ID~I~N~PU~T~DA~T~A::::::J~~________V~A~L~ID~DU~T~P~U~T~DA~~~A~____~t__
Fig. 9 - Basic dc timing waveforms, one Instruction cycle.
elCM-_
20 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1802A, CDP1802AC
ARCHITECTURE
The CPU block diagram is shown in Fig. 8. The principal
feature of this system is a register array (R) consisting of
sixteen 16-bit scratch pad registers. Individual registers in
the array (R) are designated (selected) by a 4-bit binary
code from one of the 4-bit registers labeled N, P, and X. The
contents of any register can be directed to anyone of the
following three paths:
1. the external memory (multiplexed, higher-order byte
first, on to 8 memory address lines);
2. the D register (either of the two bytes can be gated to
D);
3. the increment/decrement circuit where it is increased
or decreased by one and stored back in the selected
16-bit register.
The three paths, depending on the nature of the instruction,
may operate independently or in various combinations in
the same machine cycle.
With two exceptions, CPU instructions consist of two 8clock-pulse machine cycles. The first cycle is the fetch
cycle, and the second-and third if necessary-are execute
cycles. During the fetch cycle the four bits in the P
designatorselect one of the 16 registers R(P) as the current
program counter. The selected register R(P) contains the
address of the memory location from which the instruction
is to be fetched. When the instruction is read out from the
memory, the higher-order 4 bits of the instruction byte are
loaded into the I register and the lower-order 4 bits into the
N register. The content of the program counter is automatically incremented by one so that R(P) is now "pointing"
to the next byte in the memory.
The X designator selects one of the 16 registers R(X) to
"point" to the memory for an operand (or data) in certain
ALU or 1/0 operations.
The N designator can perform the following five functions
depending on the type of instruction fetched:
1. designate one of the 16 registers in R to be acted upon
during register operations;
2. indicate to the 1/0 devices a command code or deviceselection code for peripherals;
3. indicate the specific operation to be executed during
the ALU instructions, types of tests to be performed
during the Branch instructions, orthe specific operation
required in a class of miscellaneous instructions (70-73
and 78-7B);
4. indicate the valueto be loaded into P to designate a new
register to be used as the program counter R(P);
S. indicate the value to be loaded into X to designate a new
register to be used as data pOinter R(X).
The registers in R can be assigned by a programmer in three
d ilferent ways: as program cO.unters, as data pointers, or as
scratch pad locations (data registers) to hold two bytes of
data.
Program Counters
Any register can be the main program counter;.the address
of the selected register is held in the P designator. Other
registers in R can be used as subroutine program counters.
By a single instruction the contents of the P register can be
changed to effect a "call" to a subroutine. When interrupts
are being serviced, register R(1) is used as the program
counter for the user's interrupt servicing routine. After
reset, and during a DMA operation, R(O) is used as the
program counter. At all other times the register designated
as program counter is at the discretion of the user.
Data Polnterl
The registers in R may be used as data pOinters to indicate a
location in memory. The register designated by X (i.e .• R(X»
pOints to memory for the following instructions (see Table
I):
1. ALU operations F1-FS, F7, 74. 7S, 77;
2. output instructions 61 through 67;
3. input instructions 69 through 6F;
4. certain miscellaneous instructions - 70-73. 78. 60. FO.
The register designated by N (I.e .• R(N» points to memory
for the "ioad D from memory" instructions ON and 4N and
the "Store D" instruction SN. The register designated by P
(i.e., the program counter) is used as the data pointer for
ALU instructions F8-FD, FF, 7C, 7D, 7F. During these
instruction executions. the operation is referred to as "data
immediate".
Another important use of R as a data pointer supports the
built-in Oirect-Memory"Access (DMA) function. When a
OMA-In or DMA-Out request is received. one machine
cycle is "stolen". This operation occurs at the end of the
execute machine cycle in the current instruction. Register
R(O) is always used as the data pointer during the OMA
operation. The data is read from (OMA-Out) or written into
(DMA-In) the memory location pOinted to by the R(O)
register. At the end of the transfer, R(O) is incremented by
one so that the processor is ready to act upon the next OMA
byte transfer request. This feature in the 1800-series
architecture saves a substantiai amount of logic when fast
exchanges of blocks of data are required. such as with
magnetic discs or during CRT-display-refresh cycles.
Data Regllters
When registers in R are used to store bytes of data, four
instructions are provided which allow 0 to receive from or
write into either the higher-order- or lower-order-byte
portions of the register designated by N. By this mechanism
(together with loading by data immediate) program pointer
and data pointer designations are initialized. Also. this
technique allows scratchpad registers in R to be used to hold
general data. By employing increment or decrement instructions, such registers may be used as loop counters.
The Q flip Flop
An internal flip flop, Q. can be set or reset by instruction and
can be sensed by conditional branch instructions. The output
of Q is also available as a microprocessor output.
Interrupt Servicing
Register R(1) is always used as the program counter whenever
interrupt servicing is initiated. When an Interrupt request
occurs and the interrupt is allowed by the program (again.
nothing takes place until the completion of the current
instruction), the contents of the X and P registers are stored
in the temporary reglsterT, and X and P are setto new values;
hex digit 2 in X and hex digit 1 in P. Interrupt Enable C/S
automatically de-activated to Inhibit further interruptions.
The user's interrupt routine is now in control; the contents of
T may be saved by means of a single instruction (78) in the
memory location pOinted to by R(X). At the conclusion ofthe
interrupt. the user's routine may restore the pre-interrupted
value of X and P with a Single instruction (70 or 71). The
Interrupt-Enable flip flop can be activated to perMit further
interrupts or can be disabled to prevent them.
22 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1802A, CDP1802AC
INSTRUCTION SET
The CPU instruction summary is given in Table I. Hexadecimal
notation is used to refer to the 4-bit bi~ary codes.
R(W).O: Lower-order byte of R(W)
R(W).1: Higher-order byte of R(W)
I n ali registers bits are numbered from the least significant bit
(LSB) to the most significant bit (MSB) starting with O.
Operation Notation
M(R(N» - D; R(N) + 1 - R(N)
R(W): Register designated by W, where
W=N orX, or P
This notation means: The memory byte pointed to by R(N) is
loaded into D, and R(N) is incremented by 1.
TABLE I -INSTRUCTION SUMMARY (See Notes following table, pp. 11 and 12)
INSTRUCTION
MEMORY REFERENCE
LOAD VIA N
LOAD ADVANCE
LOAD VIA X
LOAD VIA X AND ADVANCE
LOAD IMMEDIATE
STORE VIA N
STORE VIA X AND
DECREMENT
REGISTER OPERATIONS
INCREMENT REG N
DECREMENT REG N
INCREMENT REG X
GET LOW REG N
PUT LOW REG N
GET HIGH REG N
PUT HIGH REG N
LOGIC OPERATIONS f
OR
OR IMMEDIATE
OP
CODE
MNEMONIC
OPERATION
LDN
LDA
LDX
LDXA
LDI
STR
STXD
ON
4N
FO
72
Fa
5N
73
M(R(N»-D;
M(R(N»-D;
M(R(X»-D
M(R(X»-D;
M(R(P»-D;
D-M(R(N»
D-M(R(X»;
INC
'DEC
IRX
GLO
PLO
GHI
PHI
1N
2N
SO
aN
AN
9N
BN
R(N)+1-R(N)
R(N)-1-R(N)
R(X)+1-R(X)
R(N).O-D
D-R(N).O
R(N).1-D
D-R(N).1
OR
ORI
F1
F9
EXCLUSIVE OR
EXCLUSIVE OR IMMEDIATE
XOR
XRI
F3
FB
AND
AND IMMEDIATE
AND
ANI
F2
FA
SHIFT RIGHT
SHR
FS
M(R(X» OR D-D
M(R(P» OR D-D;
R(P)+1-R(P)
M(R(X» XOR D-D
M(R(P» XOR D-D;
R(P)+1-R(P)
M(R(X» AND D-D
M(R(P» AND D-D;
R(P)+1-R(P)
SHIFT D RIGHT, LSB(D)-DF,
O-MSB(D)
SHIFT D RIGHT, LSB(D)-DF,
DF-MSB(D)
SHIFT RIGHT WITH CARRY
SHRC
RING SHIFT RIGHT
SHIFT LEFT
RSHR
SHL
SHIFT LEFT WITH CARRY
SHLC
RING SHIFT LEFT
RSHL
~
7S§
FE
!
7E§
FOR N NOT 0
(RN)+1 -R(N)
R(X)+1-R(X)
R(P)+1-R(P)
R(X)-1-R(X)
SHIFT D LEFT, MSB(D)-DF,
O-LSB(D)
SHIFT D LEFT, MSB(D)-DF,
DF-LSB(D)
24 - - - - - - - - - - - -___ CMOS Microprocessors, Memories and Peripherals
CDP1802A, CDP1802AC
TABLE I - INSTRUCTION SUMMARY (Conl'd)
OP
CODE
MNEMONIC
INSTRUCTION
OPERATION
BRANCH INSTRUCTIONS-SHORT BRANCH
B4
37
BN4
3F
BRANCH INSTRUCTIONS-LONG BRANCH
LONG BRANCH
LBR
CO
NO LONG BRANCH (SEE LSKP)
LONG BRANCH IF 0=0
NLBR
LBZ
C2
LONG BRANCH IF 0 NOT 0
LBNZ
CA
LONG BRANCH IF OF=1
LBOF
C3
LONG BRANCH IF OF=O
LBNF
CB
LONG BRANCH IF 0=1
LBO
C1
LONG BRANCH IF 0=0
LBNO
C9
SKIP INSTRUCTIONS
SHORT SKIP (SEE NBR)
LONG SKIP (SEE NLBR)
LONG SKIP IF 0=0
SKP
LSKP
LSZ
3S§
CS§
CE
LONG SKIP IF 0 NOT 0
LSNZ
CS
LONG SKIP IF OF=1
LSOF
CF
LONG SKIP IF OF=O
LSNF
C7
LONG SKIP IF 0=1
LSO
CO
LONG SKIP IF 0=0
LSNO
C5
LONG SKIP IF IE=1
LSIE
CC
SHORT BRANCH IF EF4=1
(EF4=VSS)
SHORT BRANCH IF EF4=0
(EF4=VCC)
CS§
IF EF4=1, M(R(P»-R(P).O
ELSE R(P)+1-R(P)
IF EF4=O, M(R(P»-R(P).O
ELSE R(P)+1-R(P)
M(R(P))-R(P).1
M(R(P)+1 )-R(P).O
R(P)+2-R(P)
IF 0=0, M(R(P))-R(P).1
M(R(P)+1 )-R(P).O
ELSE R(P)+2-R(P)
IF 0 NOT 0, M(R(P»-R(P).1
M(RW)+1 )-R(P).O
ELSE R(P)+2-R(P)
IF OF=1, M(R(P))-R(P).1
M(R(P)+1 )-R(P).O
ELSE R(P)+2-R(P)
IF OF=O, M(R(P»-R(P).1
M(R(P)+1 )-R(P).O
ELSE R(P)+2-R(P)
IF 0=1, M(R(P))-R(P).1
M(R(P)+1 )-R(R).O
ELSE R(P)+2-R(P)
IF 0=0, M(R(P»-R(P).1
M(R(P)+1)-R(P).0
ELSE R(P)+2-R(P)
R(P)+1-R(P)
R(P)+2-R(P)
IF 0=0, R(P)+2-R(P)
ELSE CONTINUE
IF 0 NOT 0, R(P)+2-R(P)
ELSE CONTINUE
IF OF=1, R(P)+2-R(P)
ELSE CONTINUE
IF OF=O, R(P)+2-R(P)
ELSE CONTINUE
IF 0=1, R(P)+2-R(P)
ELSE CONTINUE
IF 0=0, R(P)+2-R(P)
ELSE CONTINUE
IF IE=1, R(P)+2-R(P)
ELSE CONTINUE
26 _______________ CMOS Microprocessors, Memories and Peripherals
CDP1802A, CDP1802AC
Note. lor TABLE I
1. Long-Branch, Long-Skip and No Op instructions are
the only instructions that require three cycles to
complete (1 fetch +2 execute).
Long-Branch instructions are three bytes long. The
first byte specifies the condition to be tested; and the
second and third byte, the branching address.
The long-branch instructions can:
a) Branch unconditionally
b) Test for 0=0 or 0-0
c) Test for OF=O or OF=1
d) Test for 0=0 or 0=1
e) effect an unconditional no branch
If the tested condition is met, then branching takes
place; the branching address bytes are loaded in the
high- and low-order bytes of the current program
counter, respectively. This operation effects a branch
to any memory location.
If the tested condition is not met, the branching
address bytes are skipped over, and the next instruction in sequence is fetched and executed. This
operation is taken for the case of unconditional no
branch (NLBR).
2. The short-branch instructions are two bytes long. The
first byte specifies the condition to be tested, and the
second specifies the branching address.
The short-branch instruction can:
a) Branch unconditionally
b) Test for 0=0 or 0'"0
c) Test for OF=O or OF=1
d) Test for 0=0 or 0=1
e) Test the status (1 or 0) of the four EF flags
f) Effect an unconditional no branch
if the tested condition is met, then branching takes
place; the branching address byte is loaded into the
low-order byte position of the current program
counter. This effects a branch within the current 256byte page of the memory, i.e., the page which holds the
branching address. If the tested condition is not met
the branching address byte is skipped over, and th~
next instruction in sequence is fetched and executed.
This same action is taken in the case of unconditional
no branch (NBR).
.
3. The skip instructions are one byte long. There is one
Unconditional Short-Skip (SKP) and eight Long-Skip
instructions.
The Unconditional Short-Ski p instruction takes 2 cycles
to complete (1 fetch + 1 execute). Its action is to skip
over the byte following it. Then the next instruction in
sequence is fetched and executed. This SKP instruction
is identical to the unconditional no-branch instruction
(NBR) except that the skipped-over byte is not
considered part of the program.
The Long-Skip instructions take three cycles to
complete (1 fetch +2 execute).
They can:
a) Skip unconditionally
b) Test for 0=0 or 0 '0
c) Test for OF=O or OF=1
d) Test for 0=0 or 0=1
e) Test for IE=1
0
If the tested condition is met. then Long Skip takes
place; the current program counter is incremented
twice. Thus two bytes are skipped over and the next
instruction in sequence is fetched and executed. If the
tested condition is not met, then no action is taken.
Execution is continued by fetching the next instruction
in sequence.
28 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1802A, CDP1802AC
OYNAMIC ELECTRICAL CHARACTERISTICS at T A=-40 to +85 0 C, CL =50 pF, VOO±5%, except as noted.
LlIIlIJ"S
Max.
(\'1
VOO
(V)
~.
5
5
10
5
5
10
5
5
10
5
5
10
5
5
10
5
5
10
5
5
10
5
5
10
5
5
10
5
5
10
5
10
10
5
10
10
5
10
10
5
10
10
5
10
10
5
10
10
5
10
10
5
10
10
5
10
10
5
10
10
200
150
100
600
400
300
250
150
100
200
150
100
200
150
100
200
150
100
300
250
100
300
250
150
250
150
100
300
200
150
300
250
150
850
600
400
350
250
150
300
250
150
350
290
175
300
250
150
450
350
200
450
350
250
400
250
150
550
350
250
5
5
10
5
5
10
5
5
10
5
5
10
5
5
10
5
10
10
5
10
10
5
10
10
5
10
10
5
10
10
-20
0
-10
150
100
75
0
0
0
150
100
75
-75
-50
-25
25
50
40
200
125
100
30
20
10
250
200
125
0
0
0
VCC
CHARACTERISTIC
UNITS
Propagation Delay Times:
Clock to TPA. TPB
tPLH. tPHL
Clock-to-Memory High-Address Byte
tpLH. tpHL
Clock-to-Memory Low-Address Byte Valid
tPLH. tPHL
Clock to MRD
tPHL
Clock to MRD
tpLH
Clock to MWR
tpLH. tpHL
Clock to (CPU DATA to BUS) Valid
tPLH. tPHL
,
Clock to State Code
tPLH. tPHL
Clock to Q
tpLH. tpHL
Clock to N (0-2)
tpLH. tPHL
Minimum Setup and Hold Times:
Data Bus Input Setup
tsu
Data Bus Input Hold
tH-
DMA Setup
tsu
DMA Hold
tH-
Interrupt Setup
tsu
"TYPical values are for T A=25° C and nominal VDD.
-Maximum limits of minimum characteristics are the values above which all devices function.
ns
30 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1802A, CDP1802AC
TABLE II. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING
ALL MACHINE STAT ES
STATE
I
N
MNEMONIC
DATA
MEMORY
OPERATION
BUS
ADDRESS
MRD
MWR
LINES
NOTESG
N
-
Sl
RESET
O-I.N,a,X,p;
1-IE
00
XXXX
1
1
0
A
Sl
INITIALIZE
NOT PROGRAMMER
ACCESSIBLE
FETCH
OOOO-R
00
XXXX
1
1
0
B
MRP-I,N;
MRP
RP
0
1
0
C
RP+1-RP
IDLE
MRN-D
RN+1-RN
RN-1-RN
MRO
MRN
FLOAT
FLOAT
RO
RN
RN
RN
0
0
1
1
1
1
1
1
0
0
0
0
03
3
1
1
MRP
RP
0
1
0
MRN
RN
0
1
0
3
0
MRX
RN
RX
1
0
0
1
2
2
MRX
RX
0
1
DATA
FROM
1/0
DEVICE
RX
1
0
0
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
SO
0
0
1
2
3
Sl
0
1-F
O-F
o-F
O-F
IDL
LON
INC
DEC
SHORT
BRANCH
TAKEN;
MRP-RP.O
NOT TAKEN;
RP+1-RP
MRN-D;
RN+1-RN
D-MRN
RX+1-RX
3
4
O-F
LOA
5
6
o-F
0
1
2
3
4
5
6
7
9
A
B
C
0
E
F
STR
IRX
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
INP 1
INP2
INP3
INP4
INP5
INP6
INP7
0
RET
MRX-(X,P);
RX+1-RX; 1-IE
MRX
RX
0
1
0
3
1
DIS
MRX-(X,P);
RX+1-RX; O-IE
MRX
RX
0
1
0
3
2
LDXA
MRX-D;
RX+1-RX
MRX
RX
0
1
0
3
3
STXEl
D-MRX;
RX-1-RX
0
RX
1
0
0
2
4
ADC
MRX+D+
OF-OF 0
MRX
RX
0
1
0
3
6
7
MRX-BUS;
RX+1-RX
BUS-MRX,D
6
5
32 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1802A, CDP1802AC
TABLE II. CONDITIONS ON DATA BUS AND MEMORV ADDRESS LINES DURING
ALL MACHINE STATES (CONT'D)
STATE
I
D
E
S1
F
DATA
MEMORV
N
O-F
MNEMONIC
OPERATION
BUS
ADDRESS
MRD
MWR
--
LINES
NOTESGi
SEP
N-P
AN
1
1
0
.1
D-F
0
SEX
N-X
MAX-D
NN
NN
AN
1
AX
0
0
0
~
MAX
1
1
MAX
AX
0
1
0
3
FLOAT
AX
1
1
0
1
MAP
AP
0
1
0
3
FLOAT
AP
1
1
0
1
AO
1
0
0
F, 7
AO·
0
1
0
F,8
FLOAT
AN
1
1
0
9
M(AO-1j
AO-1
0
1
0
E,3
1
LDX
OA
MAX OA D-D
2
AND
MAX AND D-D
3
XOA
MAX XOA D-D
4
5
7
6
ADD
SD
MAX+D-DF,D
MAX-D-DF,D
SM
D-MAX-DF,D
SHA
LSB(Dj-DF;
8
LDI
O-MSBi0
MAP-D;
9
OAI
AP+1-AP
MAP OR D-D;
A
ANI
RP+1-RP
MAP AND D-D;
B
XAI
MAP XOA D-D;
C
ADI
AP+1-AP
MAP+D-DF,D;
D
SDI
AP+1-AP
MAP-D-DF,D;
F
SMI
AP+1-AP
D-MAP-DF,D;
E
SHL
AP+1-AP
MSB(Dj-DF;
-
N
3
AP+1-AP
O-LSI~J.P~
S2
S3
DMA IN
BUS-MAO;
DATA FAOM
I/O DEVICE
DMA OUT
AO+1-AO
MAO-BUS;
INTEAAUPT
AO+1-AO
X,P-T; O-IE
MAO
1-P' 2-X
S1
LOAD
IDLE
(CLEAA, WAIT=Oj
NOTES:
A. IE=1, TPA, TPB suppressed, state=S1.
B. BUS=O for entire cycle.
C. Next state always S1.
D. Wait for DMA or INTERRUPT.
E. Suppress TPA, wait for DMA.
F. IN REQUEST has priority over OUT REQUEST.
G. Number refers to machine cycle. See Fig. 13 timing waveforms for machine cycles 1 through 9.
34 _______________ CMOS Microprocessors, Memories'and Peripherals
CDP1802A, CDP1802AC
CLOCK
TPA~__________________~r_l~
__________________
TPB ____________________~r-lL__________________~~
MACHINECYCLE~~_________C~Y~C~L~E~c______________- L__________~C~YC~L~E~1~c_'~l1~__________~__
INST RUCTION _~_________
FE_T_C_H_I_50_1______________, -__________
E X_E_C_U_T_E_15_'_1__________-'-___
MRD ~~__________________~
NO-N2 ________________________________
N 9-F
~
MWR
~G~~URTY
I(;;Z:/;~~~:/;§:/;~I);~/;~;0~:/;~I);~I);~;0~:/;~1);~1);~01~• • • • • • • • • • •-
:::• •
II
•
ALLOWABLE
MEMORY ACCESS
L
VALID OUTPUT
(
DATA BUS
VALID DATA FROM INPUT DEVICE
_
i"1·O'-------RE:~M~yRcylE----------~+I..·-----WR~~~~~~LE-------001.1
'User-generated signal
92CS-29601
No, 5 Input-cycle timing waveforms,
CLOCK
TPA
TPB _________________________~r-l~________________________~r_l~
MACHINE
CYCLE
CYCLE
______
CYCLE (n + 1)
n
I NSTR U CT ION - ' ' -___________f,:.E_TC:..H-"I5.:.0:..1__________-'-____________..:E::.X:..:E.::C=-U.:.;TE~I5,-,1.:.1________.l-___ _
MRD ~~__________________Jr___l~
NO
~
N2
________________~r----
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _ J
N
L-
1- 7
ALLOWABLE MEMORY ACCESS
II
•
DATA BUS
..
II
VALID DATA fROM MEMORY
VALID OUTPUT
ALLOWABLE MEMORY ACCESS
DATA STROBE'
(MAD· TPS· NI
I
~----
MEMORY
READ CYCL,
-
~
rlL.____
MEMORY
READ CYCLE
I
'User-generilted ~Igllal
~
"Don't Care" or Internal delays
92CS-29602
_
High Impeddnce Sidle
No.6 Output-cycle timing waveforms,
Fig, 13 - Machine-cycle timing waveforms (propagation delays not shown), Continued,
36 _______________ CMOS Microprocessors, Memories and Peripherals
Preliminary Data
CDP1802BC
CLOCK
WAIT
CLEAR
1ml
SCI
3.
3.
37
3.
seo
35
IlWIi
3.
TPA
TP8
MA7
MA.
MAS
MA'
MA3
MA2
MAl
- MAO
a
MRO
BUS 7
BUS 6
BUS 5
BUS 4
BUS 3
BUS 2
BUS I
Buse
Vee
H2
HI
HO
V55
CMOS 8-Bit Microprocessor
I~VDD
2
•
10
"12
"
"
IS
I.
"
"
3'
"
30
2.
28
27
2.
2S
2.
18
23
20
"
22
21
DMA IN
Features:
OMA OUT
INTERRUPT
• Minimum instruction fetch-execute time of 3.2 /.IS
(maximum clock frequency=5 MHz) at VOO=5 V
• Any combination of standard RAM and ROM up to 65,536 bytes
• Operates with slow memories, up to 775 ns access time at feL =5 MHz
• 8-bit parallel organization with bidirectional
data bus and multiplexed address bus
• 16 x 16 matrix of registers for use as
multiple program counters, data pointers, or data registers
•. On-chip OMA, interrupt, and flag inputs
• Programmable single-bit output port
• 91 easy-to-use instructions
m
m
m
m
TOP VIEW
92CS-27467RI
Terminal Assignment
The RCA-COP1802BC LSI CMOS 8-bit register-oriented
central-processing unit (CPU) is designed for use as a
general-purpose computing or control element in a wide
range of stored-program systems or products.
The COP1802BC includes all of the circuits required for
fetching, interpreting, and executing instructions which
have been stored in standard types of memories. Extensive
input/output (I/O) control features are also provided to
facilitate system design.
The 1800 series architecture is designed with emphasis on
the total microcomputer system as an integral entity so that
systems having maximum flexibility and minimum cost can
be realized. The 1800 series CPU also provides a synchronous interface to memories and external controllers
for I/O devices, and minimizes the cost of interface controllers. Further, the I/O interface is capable of supporting
devices operating in polled, interrupt-driven, or direct
memory-access modes.
The COP1802BC has a recommended operating voltage
range of 4 to 6.5 volts. These types are supplied in 40-lead
dual-in-line side-brazed ceramic packages (0 suffix). and
40-lead dual-in-line plastic packages (E suffix).
ADDRESS
II
==>
¢=
DATA
\7
V
MAO-7
CDPI852
INPUT PORT CS2
BUS
MAO-7
MAO-4
NO
CS!
f'J 1 r-
DATA CSI
CS2
CDPI852
OUTPUT PORT
CLOCK
~
MRD
MAD
CDPI802
8-BIT CPU
MRD
CDPI833
I K-ROM
MWR
MWR
-NI
-
CEO
TPB
TPA
TPA
DATA
DATA
II
CDPI824
32 BYTE RAM
8- BIT
ATA
US
\/
cs
DATA
J
I
92CM 34681RI
Fig. 1 - Typical CDPl802BC small microprocessor system.
File Number
1342
38 _______________ CMOS Microprocessors, Memories and Peripherals
CDP1802BC
STATIC ELECTRICAL CHARACTERISTICS at TA=-40 to +85°C. except as noted.
CONDITIONS
CHARACTERISTIC
Quiescent Device Current
Output Low Drive (Sink) Current
(Except XTAL)
VOUT
(V)
VIN
(V)
-
-
5
-
1
200
I1A
0.4
0,5
5
1.1
2.2
-
mA
0.4
5
5
170
350
-
I1A
4.6
0,5
5
-0.27
-0.55
-
mA
4.6
0
5
--125
-250
-
I1A
-
0,5
5
-
0
0.1
-
IDD
IOL
XTAL
Output High Drive (Source) Current
(Except XTAL)
IOH
XTAL
Output Voltage Low-Level
VOL
Output Voltage High Level
VOH
LIMITS
VCC.
VDD
(V)
Min.
CDP1802BC
Typ."
Max.
0,5
5
4.9
5
-
Input Low Voltage
VIL
0.5.4.5
-
5
-
1.5
Input High Voltage
VIH
0.5,4.5
-
5
3.5
-
-
-
5
0.4
0.5
-
Any
Input
0,5
5
-
±10-4
±1
0,5
0,5
-
±10-4
±1
-
-
5
5
-
15
30
-
2
2.4
-
0.5
5
10
CLEAR Input Voltage
VH
Schmitt Hysteresis
Input Leakage Current
liN
3-State Output Leakage Current
lOUT
Total Power Dissipation, 1=5 MHzt.
Minimum Data Retention Voltage
Data Retention Current
Input Capacitance
Output Capacitance
VDO=VDR
VDD-2.4 V
VDR
IDR
CIN
COUT
-
UNITS
V
-
I1A
mW
V
-
I1A
7.5
15
pF
"Typical values are for T A=25°C and nominal VDD.
aldie "00" at M(OOOO), CL =50 pF.
-,
DRAIN-TO-SOURCE VOLTAGEIVOS)-V
-3
-2
-I
-4
.•
AMSIENT TEMPERATURE-
40
TO+65~C
I
}
GATE-TO-SOURCE VOLTAGE
(VGS1~-!5V
I
2
'-s
4
DRAIN-TO-SOURCE VOLTAGE (VOSI-V 92CS- 3466S
Fig. 4 - Minimum output high (source) current characteristics.
Fig. 5 - Minimum output low (Sink) current characteristics.
40 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1802BC
SIGNAL DESCRIPTIONS
BUS 0 to BUS 7 (Data Bus):
TPA. TPB (2 Timing PulseB):
a-bit bidirectional DATA BUS lines. These lines are used for
transferring data between the memory. the microprocessor,
and I/O devices.
Positive pulses that occur once in each machine cycle (TPB
follows TPA). They are used by I/O controllers to interpret
codes and to time interaction with the data bus. The trailing
edge of TPA is used by the memory system to latch the
higher-order byte of the 16-bit memory address. TPA is
suppressed in IDLE when the CPU is in the load mode.
NO to N2 (I/O) Lines):
Activated by an I/O instruction to signal the I/O control logic
of a data transfer between memory and I/O interface. These
lines can be used to issue command codes or device
selection codes to the I/O devices (independently or
combined with the memory byte on the data bus when an I/O
instruction is being executed). The N bits are low at all times
except when an I/O instruction is being executed. During this
time their state is the same as the corresponding
bits in the N register.
The direction of data flow is defined in the I/O instruction by
bit N3 (internally) and is indicated by the level of the MRD
~~1.
__ =VCC: Data from I/O to CPU and Memory
MAO to MA7 (8 Memory AddreBs LlneB):
In each cycle, the higher-order byte of a 16-bit CPU memory
address appears on the memory address lines MAO-7 first.
Those bits required by the memory system can be strobed
into external address latches by timing pulse TPA. The loworder byte of the 16-bit address appears on the address lines
after the termination of TPA. Latching of all a higher-order
address bits would permit a memory system of 64K bytes.
MWR (Write Pulse):
MRD=VSS: Data from Memory to 1/0
A negative pulse appearing in a memory-write cycle, after the
address lines have stabilized.
ffi to ffi (4 Flags):
Miffi (Read Level):
These Inputs enable the I/O controllers to transfer status
information to the processor. The levels can be tested by the
conditional branch instructions. They can be used in conJunction with the INTERRUPT request line to establish
interrupt priorities. These flags can also be used by I/O
devices to "call the attention" of the processor, in which case
the program must routinely test the status of these flag(s).
The flag(s) are sampled at the beginning of every S1 cycle.
A low level on MRi5lndicates a memory read cycle. It can be
used to control three-state outputs from the addressed
memory which may have a common data input and output
bus. If a memory does not have a three-state high-impedance
output, Mm:i is useful for driving memory/bus separator
gates. It is also used to indicate the direction of data transfer
during an I/O instruction. For additional information see
Table I.
INTERRUPT,
DMA-iN, DMA-OUT (3 I/O Requests)
These inputs are sampled by the CDP1a02BC during the
interval between the leading edge of TPB and the leading
edge ofTPA.
Interrupt Action: X and P are stored In T after executing
current instruction; designator X is set to 2; designator P is set
to 1; interrupt enable is reset to 0 (inhibit); and instruction
execution is resumed. The interrupt action requires one
machine cycle (S3).
DMA Action: Finish executing current instruction; R(O)
points to memory area for data transfer; data is loaded into or
read out of memory; and increment R(O).
Note: In the event of concurrent DMA and Interrupt requests,
DMA-IN has priority followed by DMA-OUT and then
Interrupt.
SCO, SC1, (2 State Code Lines):
These outputs indicate that the CPU is: 1) fetching an
instruction, or 2) executing an instruction, or 3) processing a
DMA request, or 4) acknowledging an interrupt request. The
levels of state code are tabulated below. All states are valid at
TPA. H=VCC, L=VSS.
State Type
SO (Fetch)
S1 (Execute)
52 (DMA)
S3 (Interrupt)
State Code Lines
SCO
SC1
L
L
H
L
L
H
H
H
Q:
Single bit output from the CPU which can be set or reset
under program control. During SEa or REa instruction
execution, a is set or reset between the trailing edge of TPA
and the leading edge of TPB.
.
CLOCK:
Input for externally generated Single-phase clock. A typical
clock frequency is 5 MHz at VCC= VDD= 5 volts. The
clock is counted down internally to a clock pulses per
machine cycle.
iT'Ai::
Connection to be used with clock input terminal, for an
external crystal, if the on-chip oscillator is utilized. The
crystal is connected between terminals 1 and 39 (CLOCK and
XTAL) in parallel with a resistance (10 megohms typ.).
Frequency trimming capacitors may be required at terminals
1 and 39. For additional information, see ICAN-6565.
WAiT, CLEAii (2 Control Lines):
Provide four control modes as listed in the following truth
table:
CLEAR
L
L
H
H
WAIT
L
H
L
H
MODE
LOAD
RESET
PAUSE
RUN
VDD. VSS. VCC (Power Levels):
The internal voltage supply VDD is isolated from the
Input/Output voltage supply VCC so that the processor may
operate at maximum speed while interfacing with peripheral
devices operating at lower voltage. VCC must be less than or
equal to VDD. All outputs swing from VSS to VCC. The
recommended input voltage swing is VSS to Vcc.
42 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1802BC
CPU Register Summary
8 Bits
1 Bit
8 Bits
16 Bits
4 Bits
D
DF
B
R
P
X
4 Bits
Data Register (Accumulator)
Data Flag (ALU Carry)
Auxiliary Holding Register
1 of 16 Scratch pad Registers
Designates which register is
Program Counter
Designates which register is
Data Pointer
N
I
T
4 Bits
4 Bits
8 Bits
IE
1 Bit
1 Bit
Q
Holds Low-Order Instr. Digit
Holds High-Order Instr. Digit
Holds old X, P after Interrupt
(X is high nibble)
Interrupt Enable
Output Flip Flop
CDP1802 Control Modes
The WAIT and CLEAR lines provide four control modes as
listed in the following truth table:
CLEAR
L
L
H
H
WAIT
L
H
L
H
MODE
LOAD
RESET
PAUSE
RUN
The function of the modes are defined as follows:
Load
Holds the CPU in the IDLE execution state and allows an 1/0
device to load the memory without the need for a "bootstrap"
loader. It modifies the IDLE condition so that DMA-IN
operRtion does not force execution of the next instruction.
Reset
Registers I, N, Q are reset, IE is set and a's (VSS) are placed
on the data bus. TPA and TPB are suppressed while reset is
held and the CPU is placed in S1. The first machine cycle
after termination of reset is an initialization cycle which
requires 9 clock pulses. During this cycle the CPU remains in
Sl and registers X, P, and R(O) are reset. Interrupt and DMA
servicing are suppressed during the initialization cycle. The
next cycle is an SO, Sl, or an S2 but never an S3. With the use
of a 71 instruction followed by 00 at memory locations 0000
and 0001, this feature may be used to reset IE, so as to
preclude interrupts until ready for them. Powerup reset can
be realized by connecting an RC network directly to the
CLEAR pin, since it has a Schmitt-triggered input, see Fig. 10.
Pause
Stops the internal CPU timing generator on the first negative
high-to-Iow transition of the input clock. The oscillator
continues to operate, but subsequent clock transitions are
ignored.
Run
May be initiated from the Pause or Reset mode functions. If
initiated from Pause, the CPU resumes operation on the first
negative high-to-Iow transition of the input clock. When
initiated from the Reset operation, the first machine cycle
following Reset is always the initialization cycle. The initialization cycle is then followed by a DMA (S2) cycle or fetch
(SO) from location 0000 in memory.
RUN-MODE STATE TRANSITIONS
The CDP1802BC CPU state transitions when in the RUN and
RESET modes are shown in Fig. 11. Each machine cycle
requires the same period of time, 8 clock pulses, except the
initialization cycle, which requires 9 clock pulses. The
execution of an instruction requires either two or three
machine cycles, SO followed by a single Sl cycle or two Sl
cycles. S2 is the response to a DMA request and S3 is the
interrupt response. Table II shows the conditions on Data
Bus and Memory-Address lines during all machine states.
(LONG BRANCH,
LONG SKIP, NOP, ETC)
Vee
COPIS02BC
The RC time constant
should be greater than
the oscillator start-up time
(typically 20 ms).
PRIORITY:
92C5 - 34669RI
Fig. 10 - Reset diagram.
FORCE so, 51
DMAIN
ffiTA OUT
iNf
INT,i5MA
92CS-33872
Fig. 11 - State transition diagram.
44 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1802BC
TABLE I - INSTRUCTION SUMMARY (Cont'd)
OP
CODE
INSTRUCTION
ARITHMETIC OPERATIONS;
ADD
ADD IMMEDIATE
ADD WITH CARRY
ADD WITH CARRY, IMMEDIATE
ADD
ADI
ADC
ADCI
F4
FC
74
7C
SUBTRACT 0
SUBTRACT 0 IMMEDIATE
SO
SOl
F5
FD
SUBTRACT 0 WITH BORROW
SUBTRACT 0 WITH
BORROW, IMMEDIATE
SUBTRACT MEMORY
SUBTRACT MEMORY IMMEDIATE
SOB
SDBI
75
70
SM
SMI
F7
FF
MNEMONIC
SUBTRACT MEMORY WITH BORROW
5MB
SUBTRACT MEMORY WITH
5MBI
BORROW, IMMEDIATE
BRANCH INSTRUCTIONS-SHORT BRANCH
SHORT BRANCH
BR
NO SHORT BRANCH (SEE SKP)
NBR
SHORT BRANCH IF 0=0
BZ
77
7F
30
3S§
32
SHORT BRANCH IF 0 NOT 0
BNZ
3A
SHORT BRANCH IF
SHORT BRANCH IF
SHORT BRANCH IF
GREATER
SHORT BRANCH IF
SHORT BRANCH IF
SHORT BRANCH IF
SHORT BRANCH IF
DF=1
POS OR ZERO
EOUAL OR
BDF
BPZ
BGE
33§
DF=O
MINUS
LESS
O=F
BNF
BM
BL
BO
t
~
OPERATION
M(R(X))+D-DF,D
M(R(P))+D-DF,D; R(P)+1-R(P)
M(R(X))+D+DF-DF,D
M(R(P))+D+DF-DF,D
R(P)+1-R(P)
M(R(X))-D-DF,D
M(R(P))-D-DF,D;
R(P)+1-R(P)
M(R(X))-D-(NOT DF)-DF, 0
M(R(P))-D-(NOT DF)-DF, 0;
R(P)+1-R(P)
D-M(R(X))-DF, 0
D-M(R(P))-DF,D;
R(P)+1-R(P)
D-M(R(X))-(NOT DF)-DF, 0
D-M(R(P))-(NOT DF)-DF, 0
R(P)+1-R(P)
M(R(P))-R(P).O
R(P)+1-R(P)
IF 0=0, M(R(P))-R(P).O
ELSE R(P)+1-R(P)
IF 0 NOT 0, M(R(P))-R(P).O
ELSE R(P)+1-R(P)
IF DF=1, M(R(P))-R(P).O
ELSE R(P)+1-R(P)
3B§
IF DF=O, M(R(P))-R(P).O
ELSE R(P)+1-R(P)
31
IF 0=1, M(R(P))-R(P).O
ELSE R(P)+1-R(P)
IF 0=0, M(R(P))-R(P).O
ELSE R(P)+1-R(P)
IF EF1=1, M(R(P))-R(P).O
ELSE R(P)+1-R(P)
IF EF1=O, M(R(P))-R(P).O
ELSE R(P)+1-R(P)
IF EF2=1, M(R(P))-R(P).O
ELSE R(P)+1-R(P)
IF EF2=O, M(R(P))-R(P).O
ELSE R(P)+1-R(P)
IF EF3=1, M(R(P))-R(P).O
ELSE R(P)+1-R(P)
IF EF3=O, M(R(P))-R(P).O
ELSE R(P)+1-R(P)
SHORT BRANCH IF 0=0
BNO
39
SHORT BRANCH IF EF1=1
(EF1=VSS)
SHORT BRANCH IF EF1=0
(EF1=VCC)
SHORT BRANCH IF EF2=1
(EF2=VSS)
SHORT BRANCH IF EF2=0
(EF2=VCC)
SHORT BRANCH IF EF3=1
(EF3=VSS)
SHORT BRANCH IF EF3=0
(EF3=VCC)
B1
34
BN1
3C
B2
35
BN2
3D
B3
36
BN3
3E
46 _ _ _ _ _ _ _ _ _ _ _ _ _......;. CMOS Microprocessors, Memories and Peripherals
CDP1802BC
TABLE I-INSTRUCTION SUMMARY (Confd)
INSTRUCTION
OP
CODE
MNEMONIC
OPERATION
CONTROL INSTRUCTIONS
IDLE
10L
00#
NO OPERATION
SETP
SET X
SET 0
RESET 0
SAVE
PUSH X,P TO STACK
NOP
SEP
SEX
SEO
REO
SAV
MARK
C4
ON
EN
7B
7A
78
79
RETURN
RET
70
DISABLE
DIS
71
INPUT-OUTPUT BYTE TRANSFER
OUTPUT 1
OUTPUT 2
OUTPUT 3
OUTPUT,4
OUTPUTS
OUTPUT 6
OUTPUT 7
OUT1
OUT2
OUT3
OUT4
OUTS
OUT6
OUT7
61
62
63
64
65
66
67
M(R(X»-BUS;R(X)+1-R(X);
M(R(X»-BUS;R(X)+1-R(X);
M(R(X»-BUS;R(X)+1-R(X);
M(R(X»-BUS;R(X)+1-R(X);
M(R(X»-BUS;R(X)+1-R(X);
M(R(X»-BUS;R(X)+1-R(X);
M(R(X»-BUS;R(X)+1-R(X);
INPUT 1
INPUT 2
INPUT 3
INPUT 4
INPUT 5
INPUT 6
INPUT 7
INP 1
INP2
INP3
INP4
INP5
INP6
INP7
69
6A
6B
6C
60
6E
6F
BUS-M(R(X»;
BUS-M(R(X»;
BUS--M(R(X»;
BUS-M(R(X»;
BUS-M(R(X»;
BUS-M(R(X»;
BUS-M(R(X»;
WAIT FOR OMA OR INTERRUPT;
M(R(O»-BUS
CONTINUE
N-P
N-X
1-0
0-0
T-M(R(X»
(X,P)-T; (X,P)-M(R(2»
THEN P-X; R(2)-1-R(2)
M(R(X»-(X,P); R(X)+1-R(X)
1-IE
M(R(X»-(X,P); R(X)+1-R(X)
O-IE
BUS-O;
BUS-O;
BUS-O;
BUS-O;
BUS-O;
BUS-O;
BUS-O;
N
N
N
N
N
N
N
N
N
N
N
N
N
N
LlNES=1
LlNES=2
LlNES=3
LlNES=4
LlNES=S
LlNES=6
LlNES=7
LlNES=1
LlNES=2
LlNES=3
LlNES=4
LlNES=5
LlNES=6
LlNES=7
trHE ARITHMETIC OPERATIONS AND THE SHIFT INSTRUCTIONS ARE THE ONLY INSTRUCTIONS THAT CAN ALTER THE DF.
AN ADD INSTRUCTION:
DF=l DENOTES A CARRY HAS OCCURRED
DF=O DENOTES A CARRY HAS NOT OCCURRED
AFTER A SUBTRACT INSTRUCTION:
DF=l DENOTES NO BORROW. D IS A TRUE POSITIVE NUMBER
OF=O DENOTES A BORROW. D IS TWO'S COMPLEMENT
THE SYNTAX "-(NOT DF)" DENOTES THE SUBTRACTION OF THE BORROW
AFTER
§THIS INSTRUCTION IS ASSOCIATED WITH MORE tHAN ONE MNEMONIC. EACH MNEMONIC IS INDIVIDUALLY LISTED.
-AN IDLE INSTRUCTION INITIATES A REPEATING Sl CYCLE. THE PROCESSOR WILL CONTINUE TO IDLE UNTIL AN I/O REQUEST
(INTERRUPT, i5MA-iN, OR DMA-OUT) IS ACTIVATED. WHEN THE REQUEST IS ACKNOWLEDGED, THE IDLE CYCLE IS TERMINATED
AND THE I/O REQUEST IS SERVICED, AND THEN NORMAL OPERATION IS RESUMED.
Not•• for TABLE I
1. Long-Branch, Long-Skip and No Op instructions are
the only instructions that require three cycles to
complete (1 fetch +2 execute).
e) effect an unconditional no branch
Long-Branch instructions are three bytes long. The
first byte specifies the condition to be tested; and the
second and third byte, the branching address.
If the tested condition is met, then branching takes
place; the branching address bytes are loaded in the
high- and low-order bytes of the current program
counter, respectively. This operation effects a branch
to any memory location.
The long-branch instructions can:
a) Branch unconditionally
b) Test for 0=0 or 0;060
c) Test for OF=O or OF=1
d) Test for 0=0 or 0=1
If the tested condition is not met, the branching
address bytes are skipped over, and the next instruction in sequence is fetched and executed. This
operation is taken for the case of unconditional no
branch (NLBR).
48 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1802BC
60
I
I
TPA
I
I
I
I
~
. I
TPS
~--~~~~~~------~------~I
MEMORY
ADDRESS
I
~-,-~~'~
I
~HL\ tsu
MRD
(MEMORY
READ CYCLE)
i
I
IME~~~Y
~
I
I
-I
::~~
H
, \ , ,~
·
I
WRITE CYCLE)
__
~~~~~--iJ
~'--_'----1-11
_~1r\....~~~:~~:~~~~~~~~~'""I_-_LL:r
DATA FROM
CPU TO BUS
I
t~LH ,tlpHL I
-_-_-_-_-_-_-_-_....l""-::;-:.:..-;:...:.-""-=-'"".....-'...J
STATE
CODES
Q
NO,NI,N2
II/O
EXECUTION
CYCLE)
~
DATA FROM
BUS TO CPU
OMJ\
REQUEST
INTERRUPT
REQUEST
IT
1-4
II
I
FLAG LINES
SAMPLED I IN SI)
----
~--+--:
I'd
ANY NEGATIVE
TRANSITION
-----~~~~------------------NOTES'
I. THIS TIMING DIAGRAM IS USED TO SHOW SIGNAL RELATIONSHIPS
ONLY AND DOES NOT REPRESENT ANY SPECIFIC MACHINE CYCLE
2. ALL MEASUREMENTS ARE REFERENCED TO 50% POINT OF THE
WAVEFORMS
3. SHADED AREAS INDICATE "DON'T CARE" OR UNDEFINED STATE;
MULTIPLE TRANSITIONS MAY OCCUR DURING THIS PERIOD
Fig, 12 - Timing waveforms,
92CL-338S9R2
50 _______________ CMOS Microprocessors, Memories and Peripherals
CDP1802BC
TABLE II. CONDITIONS ON DATA,BUS AND MEMORY ADDRESS LINES DURING
ALL MACHINE STATES
STATE
N
I
MNEMONIC
DATA
MEMORY
OPERATION
BUS
ADDRESS
MRD
MWR
LINES
NOTESG
N
-
S1
RESET
O-I,N,Q,X,P;
1-IE
00
XXX X
1
1
0
A
S1
INITIALIZE
NOT PROGRAMMER
OOOO-R
00
XXXX
1
1
0
B
MRP-I, N;
MRP
RP
0
1
0
C
IDLE
MRN-D
MRO
MRN
RO
RN
1
FLOAT
RN
1
1
RN
1
0
0
0
0
D3
3
1
FLOAT
0
0
1
1
MRP
RP
0
1
0
MRN
RN
0
1
0
3
D-MRN
D
RN
RX+1-RX
MRX
RX
1
0
0
1
0
0
1
2
2
ACCESSIBLE
FETCH
SO
RP+1-RP
0
0
1
2
3
O-F
IDL
LDN
INC
O-F
DEC
RN+1-RN
RN-1-RN
O-F
SHORT
BRANCH
TAKEN;
MRP-RP,O
0
1-F
NOT TAKEN;
RP- -RP
S1
4
O-F
LDA
5
6
O-F
STR
IRX
OUT1
6
0
1
2
3
4
5
6
7
9
A
B
C
D
E
F
0
MRN-D;
RN+1-RN
3
OUT4
MRX-BUS;
OUT5
RX+1-RX
OUT6
OUT7
INP 1
INP 2
MRX
RX
0
1
BUS-MRX,D
4
6
5
6
7
1
DATA
INP3
FROM
2
1/0
DEVICE
3
RX
1
0
4
5
5
6
7
INP 7
RET
3
2
OUT2
OUT3
INP 4
INP5
INP6
1
MRX-(X,P);
MRX
RX
0
1
0
3
MRX
RX
0
1
0
3
MRX
RX
0
1
0
3
D
RX
1
0
0
2.
MRX
RX
0
1
0
3
RX+1-RX; 1-IE
1
DIS
MRX-(X,P);
RX+1-RX; O-IE
7
2
LDXA
MRX-D;
RX+1-RX
3
STXD
D-MRX;
RX-1-RX
4
ADC
MRX+D+
DF-DF,D
52 _______________ CMOS Microprocessors, Memories and Peripherals
CDP1802BC
TABLE II. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING
ALL MACHINE STATES (CONT'D)
STATE
I
D
E
S1
F
DATA
MEMORY
N
O-F
O-F
MNEMONIC
OPERATION
BUS
ADDRESS
SEP
N-P
NN
RN
SEX
N-X
NN
a
LDX
MRX-D
1
OR
MRXOR D-D
-MRD MWR
--
N
LINES
NOTESG
RN
1
1
1
1
0
n
MRX
RX
0
1
0
1
..1
3
MRX
RX
a
1
a
3
FLOAT
RX
1
1
a
1
MRP
RP
a
1
a
3
FLOAT
RP
1
1
a
1
BUS-MRO;
DATA FROM
RO
1
0
0
F,7
RO+1-RO
I/O DEVICE
DMAOUT
MRO-BUS;
MRO
RO
0
1
0
F,8
INTERRUPT
RO+1-RO
X,P-T; O-IE
FLOAT
RN
1
1
0
9
M(RO-1)
RO-1
a
1
a
E,3
2
AND
MRXAND D-D
3
XOR
MRXXOR D-D
4
5
7
6
ADD
SD
MRX+D-DF,D
MRX-D-DF,D
SM
D-MRX-DF D
SHR
LSB(D)-DF;
8
LDI
O-MSEliI2l
MRP-D;
9
ORI
RP+1-RP
MRPOR D-D;
A
ANI
RP+1-RP
MRPAND D-D;
B
XRI
MRP XOR D-D;
RP+1-RP
RP+1-RP
C
ADI
MRP+D-DF,D;
D
SDI
RP+1-RP
MRP-D-DF,D;
F
SMI
D-MRP-DF,D;
E
SHL
RP+1-RP
MSB(D)-DF;
RP+1-RP
O-LSB~Ql
DMAIN
S2
S3
1-P' 2-X
S1
LOAD
IDLE
(CLEAR, WAIT=O)
NOTES:
A. IE=1, TPA, TPB suppressed, state=S1,
B. BUS=O for entire cycle.
C. Next state always S1,
D, Wait for DMA or INTERRUPT,
E. Suppress TPA, wait for DMA,
F. IN REQUEST has priority over OUT REQUEST,
G, Number refers to machine cycle, See Fig, 14 timing waveforms for machine cycles 1 through g,
54 ___________________________ CMOS Microprocessors, Memories and Peripherals
CDP1802BC
CLOCK
TPA~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~r-l~
TPB _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~r-l~
___________________
__________________
~~
MACHINECYCLE~~________~C~Y~C~L~E~c______________~________~C~Y~C~L~E~(c~'_'~I____________L -__
FETCH ISO)
INSTRUCTION
MRD
EXECUTE (51 )
----"1'-__________-'
NO-N2 ________________________________
N -9 - F
~
MWR
~~~~~TY
=••(;/;~:2~&~~~%~'/~~~~~:2~:2~~~'/~:2~:2~~~~
••••••••••••
....
·L
ALLOWABLE MEMORY ACCESS
VALID OUTPUT
t
DATA BUS
I..
VALID DATA FROM INPUT DEVICE
t~o-----
1-------- MEMORY
- - - - - - - .-.
READ CYCLE
_
------~..,I
MEMORY
WRITE CYCLE
..
'User-generated signal
92CS-2960(
No.5 Input-cycle timing waveforms.
CLOCK
TPA
TPB __________________________~r--lL
MACHINE
CYCLE
_________________________
CYCLE n
~
CYCLE (n + 1)
INSTRUCT ION __L -_________-'-F.::E-'-TC:..H~(S:::O~I__________-'-'-____________-'E"'X.::.EC"'U::..T:.::E~(Sc.',-I_ _ _ _ _L -_ _
MRD
~L-____________________~~'-______________________~r_____
NO - N2 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - J
N
~
1- 7
ALLOWABLE MEMORY ACCESS
.
DATA BUS
II
..
ALLOWABLE MEMORY ACCESS
DATA STROBE'
(MRD . TPS
NI
I
MEMORY
~--.-~ READ CYCli
r
·User·gellf'Idted "lIllal
~
"Don't Care"
01
Il1tl'TI1~1
.~
n'-_____
VAlI:JDATAFROMMEMORY - - - - '
VALID OUTPUT
-
MEMORY
________ ~
READ CYCLE
deldys
92CS-29602
_
High Imp('ddllce )j,ile
No.6 Output-cycle timing waveforms.
Fig. 14 - Machine-cycle timing waveforms (propagation delays not shown). Continued.
56 ________________ CMOS Microprocessors, Memories and Peripherals
CDP1804AC
TERMINAL ASSIGNMENT
CLOCK
40
39
'8
'7
WAiT
liAR
Q
SCI
SCO
MRO
BUS 7
BUS 6
BUS 5
BUS 4
BUS 3
BUS 2
BUS I
BUS 0
EMS/ME
N2
NI
NO
VSS
O'MA'OOT
'4
TPA
TP8
MA7
MA.
MAS
MA4
MA'
MA2
MAl
MAO
"
32
10
II
12
13
14
IS
"17
18
19
20
DMA IN
,.
'5
31
'0
29
28
27
2.
25
2.
2'
22
21
TOP VIEW
CMOS 8-Bit Microcomputer With
On-Chip RAM, ROM, and Counter/Timer
Voo
XTA[
INTERRUPT
Performance Features:
MWR
•
•
m
m
m
m
92CS-34980
Instruction time of 3.2 /1S, -40 to +85 0 C
123 instructions-upwards sofware compatible with
CDP1802, CDP1805A, and CDP1806A
• BCD arithmetic instructions
• Low-power IDLE mode
• Pin compatible with CDP1802, CDP1805A, and CDP1806A
except for terminal 16.
• 64K-byte memory address capability
• 2 K bytes of on-chip ROM
• 64 bytes of on-chip RAM
The RCA-CDP1804AC is a functional and performance
enhancement of the CDP1802, CDP1805A, and
CDP1806A CMOS 8-bit register-oriented microprocessor
series and is designed for use in a wide variety of generalpurpose applications.
The CDP1804AC hardware enhancements include a 2Kbyte ROM, a 64-byte RAM, and a 8-bit presettable down
counter. The Counter/Timer, which generates an internal
interrupt request, can be programmed for use in timebase, event-counting, and pulse-duration measurement
applications. The Counter/Timer underflow output can
also be directed to the Q output terminal.
The CDP1805AC and CDP1806AC which are identical to
the CDP1804AC, except for the on-Chip memory, should
be used for CDP1804AC development purposes.
• 16 x 16 matrix of on-board registers
• On-chip crystal or RC controlled oscillator
• 8-bit Counter/Timer
The CDP1804AC software enhancements include 32 more
instructions than the CDP1802. The 32 additional
software instructions include subroutine cali and return
capability, enhanced data transfer manipulation,
counter/timer control, improved interrupt handling,
Single-instruction loop counting, and BCD arithmetic.
Upwards software and hardware compatibility are
maintained when substituting a CDP1804AC for other
CDP1800-series microprocessors. Pinout is identical
except for the replacement of Vee with EMS/ME.
The CDP1804AC has an operating voltage range of 4 V to
6.5 V and is supplied in a 40-lead hermetic dual-in-line
ceramic package (D suffix). and in a 40-lead dual-in-line
plastic package (E suffix).
, - - - - - - - - -ADDRESS BUS- - - - - - - - - - -I
, - - - - - - - - - - j r - - - - - - - -,
IMA~MA7j
CONTROL
CDPl851
CDPIB04AC
8-BIT CPU
WITH ROM,
RAM. AND
COUNTER/
TIMER
PIO
OUT
TPA
I
,Is.
~~
iM~MA71
I
---~MRD
I
I
~-----.lMRD
I
___ J
r----jMWR
I
1_
1
I
1
1
---~TN
ROM
I
I
1
I
RAM
1
1
CEO~----":cs
I
1
I
1_
I
- - .. cs
1-- -~CS
I
I BUSO-BU~
~~O-BU2..:...J
-il
.-J ~
I I
~=----- _____ '>L _ _ _ _ _ _ _ _ _ .J
I
n
::....:::.:...===___________________
L-_ _ _ _ _ _ _
"--OPTIONAL EXPANSION
..J
92CM-349-81
MEMORY~
Fig. 1- Typical CDP1804AC mieroproeessorsystem.
File Number 1371
58 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1804AC
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, VDD ± 5"10, Except a. noted
LIMITS
CONDITIONS
CDP1804ACD,
CDP1804ACE
CHARACTERISTIC
Quiescent Device Current
IDD
Output low Drive (Sink) Current
10L
CExceDt XTALl
XTAlOutput
Output High Drive (Source) Current
10L
10H
LExc~t XTACl
UNITS
Vo
(V)
VIN
(V)
VDD
(V)
MIn.
Typ."
Max.
-
0.5
5
-
50
200
0.4
0.5
5
1.6
4
0.4
5
5
0.2
0.4
4.6
0,5
5
-1.6
-4
-
10H
4.6
0
5
-0.1
-0.2
-
Output Voltage low-level
VOL
0,5
5
-
0
0.1
Output Voltage High level
0,5
5
4.9
5
-
-
5
-
1.5
5
3.5
-
XTAl
VOH
-
Input low Voltage (BUS 0 - BUS 7, EMS/MEl
V,L
0.5,4.5
Input High Voltage (BUS 0 - BUS 7, EMS/MEl
Schmitt Trigger I nput Voltage
V,H
0.5,4.5
pA
mA
V
(Except BUS 0 - BUS 7, EMS/ME)
Positive Trigger Threshold
Vp
Negative Trigger Threshold
VN
Hysteresis
VH
Input leakage Current
3-State Output leakage Current
Input Capacitance
Output Capacitance
liN
lOUT
C'N
COUT
W~~I PowE!r Dissipatlon bo
ICle
"UU'
a:
Minimum Data Retention Voltage
"Typical values are forT. = 25°C and nominal VDO.
boExternal ClocK: f=5 MHz, t r,t,=10 ns. CL=50 pF.
-
5
-
0.5
5
0,5
0,5
5
-
-
-
-
MI UUUUI
Data Retention Current
0.5,4.5
VDR
VDD = VDR
lOR
VOD = 2.4
5
5
2.2
2.9
3.6
0.9
1.9
2.8
0.3
0.9
1.6
-
±0.1
±5
±0.2
±5
-
5
7.5
10
15
35
12
50
18
pA
pF
mW
2
2.4
V
25
100
pA
60 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1804AC
TIMING WAVEFORMS FOR POSSIBLE OPERATING MODES
l'NTERNAL RAM READ CYCLE ---t-'NTERNAL RAM WRITE CYCLE:l
~
00
CLOCK
01
TPA
00
~ ~ ~ ~
II
51
~ ~
ro
611
71
01
~ ~ ~ ~
00
II
21
31
41
51
ro
61
71
-----1""""lL_____+I_--.JrlL_ _ _ _ _ _ __
r
:~~~=::::::::;::::==-f'l-1I~:::;:::==:::::;::=::::::::::.~~::;:::
MRii ----,L.________-'--'
TPB
MEMORY
ADDRESS ~1~H~rG~H~B~YT~E~IL___~w~W~B~YT~E~~--LI~Hr~GH~BY~T~E~I____-=LOW~~~T~E~__~__
MWR------------------'-r-'-------------~~
I
* ~ -----------.L..!..-Jr-----------~
VALID DATA FROM MEMORVw=9
·NOTE FOR RUN (RAM ONLY) MODE:
HAS A MINIt.lUM SETUP AND HOLD TIME WITH RESPECT TO THE
ME
BEGINNING OF CLOCK 70. FOR A MEMORY READ OPERATION, RAM DATA
WILL APPEAR ON THE DATA BUS DURING THE TIME ME IS ACTIVE AFTER
CLOCK 31. THE TIME SHOWN CAN BE LONGER, IF FOR INSTANCE, A DMA
OUT OPERATION IS PERFORMED ON INTERNAL RAM DATA, TO ALLOW DATA
ENOUGH TIME TO BE LATCHED INTO AN EXTERNAL DEVICE. THE INTERNAL
RAM IS AUTOMATICALLY DESELECTED AT THE END OF CLOCK 71,
INDEPENDENT OFME.
NOTE FOR RUN (ROM/RAM) MODE:
INTERNAL MEMORY DATA WILL APPEAR ON THE DATA BUS AFTER CLOCK
PULSE 31.
92CS-34983
Fig. 3 -Internal memory operation timing waveforms for CDP1804AC.
t
00
EXTERNAL MEMORY READ CYCLE -!-EXTERNAL MEMORY WRITE CYCLE
~
00
~ ~ ~ ~ ro ~ ~
~ ~ ~
w
1
ro
00
CLOCK
611
71
01
II
21
31
41
51
61
71
L -________-+I__~r_1L_ _ _ _ _ ____
TPB
MEMORY
r+l
~
:;=.;;;;;~:::::;~;;;:-LI~~~;;;;::::::::;;::--~:
ADDRESS-LI_H_tG_A_B_YT~E~I____~LO~W_B~Y~TE~~--LI~Ht~GH~BY~T~E~I____~LO=W~BY~T=E____~
MRii
----,L________-I-...J
MWR
------------------~---------------,~
*EMS
r
OUT
DATA BUS -l<=CL
1~f'~;
o
I
~AIOj
o
I
9~
;
01
A I 7 ;
oI
~
DATA
CARDS
0
f
7
0
,..0
I"
Cf'
C
02
If.
1rf4 IHA t
f'£Fi
0
33£1"
0"1".
40 A.1
:30!-'7
j> 0
FFI:F
I" I?
f'F
o
I
F
I
01
D TA
I II
I II
I II
1 234567 B 9 10 11121314151817181920212223242526272129 303132333435383738314041424344454847484150 5152535455156575858801162838485881788897071727374757877787110
92CL-35J89
Sample Card· Deck Printout
Floppy·Dlskette Method
Master-Device Method
The diskette contains the ROM address and data information. Title, option, and data-format information, which
would otherwise be punched on computer cards, must be
submitted on the ROM Information Sheet. In addition,
specify the RCA Development System used to generate the
diskette (CDP18S005, CDP18S007, or CDP18S008) and
supply a track number or file name, If possible, include a
printout of the program for verification purposes. The
format of the address and data information is essentially the
same as that shown on the Sample Card-Deck Printout with
the addition of a carriage-return character at the end of
each line and an end-of-file character (DC3) at the end of
the file.
Data may be submitted on a master ROM, PROM, or
EPROM device. Title, option, and data-format information,
which would otherwise be punched on computer cards,
must be submitted on the ROM Information Sheet. In
addition, specify the master device type; RCA will accept
Intel types 1702, 2332A, 2704, 2708, 2716, 2732, 2758,
Supertex CM3200, TI 4732, Motorola MCM68732, and
Motorola MCM68A332, or their equivalents. If more than
one ROM pattern is stored in the master device, the starting
address and size of each pattern must be stated on separate
ROM Information Sheets. If the master-device is smaller
than 2K bytes, the starting address of each master-device
must be clearly identified.
84 _______________ CMOS Microprocessors, Memories and Peripherals
CDP1804PCE, CDM5332PE
Micro Concurrent Pascal
CMOS Microcomputer and Extension
Benefits:
• Allow multi-tasking in an interpreter driven system
• Code directed at functions in the system (simplify
control)
• Up to 64K addressing capability
• Five times faster software development than
assembly language
• Substantial cost reduction - (system portability, IC's
instead of diskette)
Features:
• Micro Concurrent Pascal (mCP) interpreter code
• Many of the instructions are I/O control specific
• lBOO-Series CMOS benefits and technology
• On-board p-code interpreter
• Eliminates need for disk-based system
• Substantial reduction in code space required for
run-time routine
• Lower parts count for equivalent functions
by an external 4K ROM (CDM5332PE) designed to work
with the core, and extends support to the complete mCP
language.
The CDP1804PCE 8-bit Microcomputer and the
CDM5332PE 4K x 8 ROM are a CMOS preprogrammed
two-chip firmware set developed by RCA. The two-chip
set contains a pseudo-code (p-code) interpreter that
facilitates the use of a high-level language called Micro
Concurrent Pascal (mCP) in end-use systems. The
interpreter is divided into two sections: core and
extension. The first section of the interpreter, core,
resides in the on-chip 2K ROM of the CDP1804PCE. The
second section of the interpreter, extension, is provided
ADDRESS
z~
II
For additional information refer to RCA publications:
"Using Micro Concurrent Pascal in RCA Development
Systerrs with the CDP1804P1 and CDM5332P1", AB7149. RCA data bulletins CDP1804A and CDM5332, file
numbers 1371 and 1366, respectively.
BUS
MAO-MA7
MAO-MAS
}AO-
MA7
MAO-MA7
=
CST I - -
MWR
MRO
TPA
CS
CS
--+
--+ liE
CDM5332PE
4KROM
COP IS81
COPI804PCE
MPU
LATCH I
WE
liE
CDM6116
2K RAM
DECODER
~
IT
>~~I==
A8All
~
BUS
'>
AS-AID
(\
/
\'
DATA
BUS
Functional Diagram of Micro Concurrent Pascal system
File Number
1552
86 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1805AC, CDP1806AC
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Voo):
(Voltage referenced to Vss Terminal) ............................................................................... -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ....................................................................... -0.5 to Voo +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ................................................................................ ±10 mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60· C (PACKAGE TYPE E) ............................................................................ 500 mW
ForT. = +60 +85·C (PACKAGE TYPE E) ................................................ Derate Linearly at 12 mW/·C to 200 mW
ForT. = -55 to +1OO·C (PACKAGE TYPE D) ........................................................................... 500 mW
ForT. = +100 to +125·C (PACKAGE TYPE D) ............................................ Derate Linearly at 12 mW/·C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For T. = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ................................................ 100 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE 0 ............................................................................................ -55 to +125·C
PACKAGE TYPE E .............................................................................................. -40 to +85·C
STORAGE TEMPERATURE RANGE (T...) ......................................................................... -65 to +150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max. . ................................................. +265·C
RECOMMENDED OPERATING CONDITIONS at TA = -40 to +85°C
For maximum reliability. nominal operating conditions should be selected so that operation is always within
the following ranges:
CONDITION
LIMITS
CDP1805ACD, CDP1805ACE
CHARACTERISTIC
CDP1806ACD, CDP1806ACE
Voo
(V)
MIN.
UNITS
MAX.
DC Operating Voltage Range
-
4
6.5
Input Voltage Range
-
Vss
Voo
Minimum Instruction Time' (fcL=5 MHz)
5
3.2
-
liS
Maximum DMA Transfer Rate
5
-
0.625
Mbytes/s
5
DC
5
5
DC
2
Maximum Clock Input Frequency,
load Capacitance (Cl) = 50 pF
MHz
Maximum External Counter/Timer
Clock Input Frequency to
EFT. m
V
teL>
'Equals 2 machrne cycles - one Fetch and one Execute operation for all instructions except Long Branch, Long Skip,
NOP, and "68" family instructions, which are more than two cycles.
88 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1805AC, CDP1806AC
1/0 REQUESTS
MEMORY ADDRESS LINES 1/0 FLAGS
\~
I
ME
FOR CDPI805AC
VDD FOR CDPI806AC
~
DMA
OUT
MA6 MA4 MA2 MAO
CONTROL
~
I
CDPI805AC
I
ONL"J
I
i""\-l64:-B~';;-I.J
I I
L-_-C.+-.. XTAL
I_~~~~---- - " - - -
SCO} STATE
SCI
CODES
CONTROL AND
TIMING LOGIC
I---!r---t---; EF1
Q LOGIC
~~~ }SYSTEM
~--t---t----~EF2
1---+--
~
>
x
J<
~
>
>
>
>
'" . >
>
>
>
>
>
>
>
j
OPEN DRAIN
SOFTWARE
PROGRAMMABLE
OUTPUTS
>
MISO 1+-------+-+-,--------'
r--r---
PORTr-------+-+~---------,
r---
PORT
,.---
PORT
d
4----
KEYBOAR~
INTERRUPT
92CS -37512RI
Fig. 4 . Keyboard interface.
92CS-37515
Fig. 3· Serial peripheral interface (SPI) bus system.
COST AND
STATUS
INFORMATION
TIMER
OSCILLATOR
1
3
1/0 FOR CONTROL
AND EXPANSION
92CS-37511
202 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6805E2
MAXIMUM RATINGS (voltages referenced to Vssl
Ratings
Supply Voltage
All Input Voltages Except ascI
Current Drain Per Pin Excluding VOO'and VSS
Operating Temperature Range
COP6805E2
COP6B05E2C
Storage Temperature Range
Symbol
Value
Unit
VDD
-0.3 to +B.O
V
Yin
VSS-0.5 to VDD+0.5
V
I
10
mA
TA
TL to TH
to 70
-40 to B5
°c
T stg
-55to+150
°c
a
DC ELECTRICAL CHARACTERISTICS 3.0 V IVDO=3.0 Vdc, VSS=O, TA = 0° to 70°C, unless otherwise noted I
Symbol
Min
Max
Unit
VOL
-
V
VOH
VDD-O.l
0.1
-
Run IVIL =0.2 V, VIH=VDD-0.2 VI
Walt IT est Conditions - See Note Below)
IDD
-
1.3
mA
IDD
200
",A
Stop (Test Conditions - See Note Below)
IDD
-
100
",A
IILOAD = 0.25 mAl AB-A 12,BO-B7
VOH
2.7
-
V
IILOAD = 0.1 mAl PAO-PA7, PBO-PB7
VOl:!
2.7
V
VOH
2.7
-
IILOAD = 0.25 mAl AB-A 12, BO-B7
VOL
-
0.3
V
IILOAD-0.25 mAl PAO-PA7, PBO-PB7
VOL
-
0.3
V
VOL
-
0.3
V
Characteristics
Output Voltage ILOAD';; 10.0 ",A
Total Supply Current ICL = 50 pF - no DC loadsl tcyc= 5 ",5
Output High Voltage
IILOAD=0.25 mAl DS, AS, R/W
Output Low Voltage
IiLOAD=0.25 mAl DS, AS, R/W
Input High Voltage
V
PAO-PA7, PBO-PB7, BO-B7
VLH
2.1
-
V
TIMER, IRO, RESET
VIH
2.5
-
V
ascI
VIH
-
V
VIL
2.1
-
0.5
V
Crystal
fOSC
0.032
1.0
MHz
External Clock
fOSC
DC
1.0
MHz
lin
-
±1
",A
ITSL
-
±1O
",A
Cin
-
B.O
pF
Cout
-
12.0
pF
Input Low Voltage IAII inputs)
Frequency of Operation
Input Current
RESET, IRO, Timer, OSCI
Three-State Output Leakage
PAO-OA7, PBO-PB7, BO-B7
Capacitance
RESET, IRO, Timer
Capacitance
DS, AS, R/W, AB-A 12, PAO-PAl, PBO-PB7, BO-B7
NOTE: Test conditions for OUlescent Current Values are:
Port A and B programmed as inputs.
VIL=02 V for PAO-PA7, PBO-PB7, and 80-87.
VIH=VDD - 0.2 V for 11Em, ii'm, and Timer.
ascI input is a squarewave from VSS+0.2 V to VDD - 0.2 V.
OSC2 output load (inCluding tester) is 35 pF maximum.
Wait mode IDD is affected linearly by this capacitance.
204 _______________ CMOS Microprocessors, Memories and Peripherals
CDP6805E2
TABLE 1 -
CONTROL TIMING (VSs=O, TA=Oo to 70°CI
VOO=5V ± 10%
fOSC=5 MHz
VOO=3' V
fOSC= 1 MHz
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
I/O Port Timing - Input Setup Time (Figure 31
tpVA~1
500
-
-
250
-
-
ns
Input Hold Time (Figure 31
tASLPX
100
-
100
-
-
ns
Output Oelay Time (Figure 31
tASLPV
-
0
-
-
0
ns
Interrupt Setup Time (Figure 61.
tlLASL
2
-
-
0.4
-
-
,..s
Crystal Oscillator Startup Time (Figure 51
tOXOV
300
100
ms
-
10
-
15
WASH
-
30
Wait Recovery Startup Time (Figure 71
-
2
-
30
-
300
-
15
100
-.J!.s
ms
5
-
Characteristics
Stop Recovery Startup Time (Crystal Oscillator! (Figure 81 l)LASH
Required Interrupt Release (Figure 61
tOSLIH
Timer Pulse Width I Figure 71
Reset Pulse Width (Figure 51
tTH, tTL
0.5
0.5
1.0
-
1 s
leye
,..s
tRL
5.2
Timer Period (Figure 71
tTLTL
1.0
-
lcye
Interrupt Pulse Width Low (Figure 161
tlLlH
1.0
1.0
teyc
Interrupt Pulse Period (Figure 161
tlLlL
"
tOLOL
"
1000
OSCl Pulse Width High
to.
350
OSCl Pulse Width Low
tOL
350
Oscillator Cycle Period (1/5 of tcyel
1.05
-
-
1.0
-
-
-
200
-
-
-
75
-
leye
ms
-
ns
-
75
-
-
ns
*The minimum period l)LlL should not be less than the number of teyc cycles it takes to execute the interrupt service routine plus 20 tcyc
cycles.
VOO=4.5 V
TTL Equlvalenl
-,.f----.
Test o----<~--.....
POint
CMOS EqUivalent
R2
Test POint
c
Pin
PAO-PA7, PBO-PB7
11.3 k
BO-B7, A8-A 12,
Riw OS AS
2.5 k
C=5O pF, PAD-PA7, PBD-PB7
= 130 pF, A8-A12, BO-B7, OS, AS,
with VOO=5 V ± 10%
!1/W
92CS--38018
Fig. 2 - Equivalent test-load circuits.
o
t
AS
c
tVHIGH*
I/I--@--l\
i
VLOW
0-.\1-
0+j~
C)
-== I-@-
I\)
p _____
CD
DS
~
G)
0-----
R/W
, .. n
~X®
I I
IL&~fi®
K
r
I~®~ ~~
®--,j..,.-r-r-,....h
Valid
Write
BO-B7
MPU Write
'IINVi
IA A
~
~®
sr--jb®~
-
Valid
BO-B7
MPURead
Data
I I
Addr
-1
~@
s::
o
(/)
s::
S·
"a
J
s::
CD
3
o
Valid Read Data
t--
~
o
::::!.
i
III
:s
if VHIGH ~ 2 V, VLOW ~ 05 V for VDD
VHIGH
0
VDD
=3 V
_
2 V, VLOW= 0 8 V lor VDD
92CS-38018
0
5 V ·10%
a.
~
::::!.
Fig, 4 - Bus timing waveforms.
";;i
ii'
I--- n ---t--- n + 1 --1---
n+ 2
o
c
---+-- n + 3 -+-n + 4 -+--n + 5----l--- n + 6 --..j.-- n c 7 -+- n + 8 --t-- n + 9---eoj
JCO
AS
i
~
m
DS
Unmux
AB-A12B u
- -s
" .I, ..• n_
Address
"
"
~_"_ • ""____
1\
•
'
1L1.--~-+--t-''''------y---- ~
N
IRQ or TCR7
Mux BO-B7
Addre~/Data
__-A-J~~~~~____-r~n_~~J~-J'~~~'~~~~J~-J~__~'~~~~~~~__~~~~__~~~~~~~____~_J'-~~n-~----~--
Bus
R/W
~
\'-----------------~/
flU
'-
92CS-38020
iftOSLIH - The Interrupting deVice must release the IRQ line within Hlis time to prevent subsequent recognition of the same Interrupt
Fig. 6 - iRQ and TCR7 interrupt timing waveforms.
n
3:
oen
Timer
I----I-tTl
founter ~$()()l--tTLTl-.j
Internal/Externa~1
Clock
~tTH
____________________________
TCRb7
_
_
t---tIVASH-;::!.-n--+-=n+l-+-n+2-+-::::-n+3-+=n+4--1-=n+5-+-n+6---1-=n+7--1
AS
n
o
't'I
I
;1
3:
DS
~~~~2
IF
Address Bus
Mux B0-87
Address/Data
SP
SP-l
PCl
Bus
R/W
3:
SP-2
PCH
SP-3
X
A
CC
New PCt-!
"-
7/llI/lIl!I1I
•
r-
SP-4
New PCl 1st Op Code ~nt
Qutlne
'-
/
&
I
I»
:::s
Q.
-:
92CS-3802t
Fig. 7 - Timer interrupt after WAIT instruction timing waveforms.
~
::l.
't'I
il
iii
iii"
210 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6805E2
FUNCTIONAL PIN DESCRIPTION
VDD and VSS - VDD and VSS provide power to the
chip. VDD provides power and VSS is ground.
130 pF. DS is a continuous signal at fOSC .,. 5 when the
MPU is not in WAIT or STOP state. Some bus cycles are
redundant reads of op code bytes.
IRQ (Maskable Interrupt Request) - I RQ is a levelsensitive and edge sensitive input which can be used to request an Interrupt sequence. The MPU completes the current instruction before It responds to the request. IF IRQ IS
low and the interrupt mask bit II-bit) in the Condition Code
Register is clear, the MPU begins an Interrupt sequence at
the end of the current instruction. The interrupt circuit
recognizes both a "Wire ORed" level as well as pulses on the
IRQ line (see Interrupt Section for more detailsl. IRQ requires
an external resistor to VDD for "Wire OR" operation.
R/IN (Read/Write) - The R/W output is used to indicate
the direction of data transfer for both internal memory and
110 registers, and external peripheral devices and memories.
This output is used to indicate to a selected peripheral
whether the M PU is going to read or write data on the next
Data Strobe (R IW low = processor write; RI Vii
high = processor read). The R/W output is capable of driving
one standard TTL load and 130 pF. The normal standby state
is P
3
FC
1
2
EC
2
3
DC
3
4
JSR
-
BC
Jump to Subroutine
-
8D
2
5
CD
3
6
FD
1
5
ED
2
6
DD
3
7
Arithmetic Compare A
with Memory
Arithmetic Compare X
with Memorv
Bit Test Memory with
A (logical Comparel
TABLE 5 -
Addressing Modes
Inherent (X)
Indexed
(No Offset)
Direct
Op
Code
#
#
#
#
#
#
Bytes
Cycles
Bytes
Cycles
Op
Code
#
Cycles
Op
Code
#
Bytes
Op
Code
#
Cycles
Op
Code
#
Bytes
Bytes
Cycles
Increment
INC
4C
1
3
5C
1
3
3C
2
5
7C
1
5
6C
2
6
Decrement
DEC
4A
1
3
5A
1
3
3A
2
5
7A
1
5
6A
2
6
Clear
ClR
4F
1
3
5F
1
3
3F
2
5
7F
1
5
6F
2
6
5
73
1
5
63
2
6
43
1
3
COM
NEG
40
1
3
50
1
3
30
2
5
70
1
5
60
2
6
.Rotate left Thru Carry
ROl
49
1
59
1
3
39
2
5
79
1
5
69
2
6
Rotate Right Thru
Carry
ROR
46
,
3
3
56
1
3
36
2
5
76
1
5
66
2
6.
logical Shift left
lSl
3
3
1
5
6
3
5
74
1
5
68
64
2
1
2
2
78
3
38
34
5
1
58
54
1
lSR
48
44
1
logical Shift Right
2
6
Arithmetic Shift Right
ASR
47
1
3
57
1
3
37
2
5
77
1
5
67
2
6
Test for Negative
or Zero
TST
4D
2
4
7D
1
4
6D
2
5
1
3
5D
1
1
3
3
33
2
Complement
Negate
12's Complementi
53
3D
N
N
~
m
N
o
s:
o
o
s:
a
'0
I
Indexed
(S-Bit Offset)
Mnemonic
Function
N
c;'
READ/MODIFY/WRITE INSTRUCTIONS
Inherent (A)
c
o
,;J
s:
CD
3
§.
i
I»
:J
a.
I
-:
::1
'0
i
;;
iii'
224 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6805E2
TABLE 9 -
INSTRUCTION SET
r---------,---------------------------------A~d~d7r-~~in-g~M~o~d-es-------------------------------,~C'-o-n-d~it~io-n-C~o-d~e-s~
Mnemonic
Inherent
ADC
ADD
AND
ASL
ASR
Immediate
Direct
Extended
X
X
X
X
X
X
X
X
X
X
X
x
X
Relative
Indexed
(No Offset)
Indexed
(88its)
Indexed
(16 Bits)
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit
Set/
Clear
Bit
Test &
Branch
H
N Z C
1\
1\
1\
1\
f1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
1\
•
1\
1\
•• •• ••
•• •• ••
BHCC
X
•• •• ••
~~B~~H~~~S--~----4--------~----_+------~--_c~-----------4-------+------~-4-----4~~~~~~
•
••
BHS
X
•• •• ••
X
••
1--r-----__---,~~'i:-!,~'=_'=_~~'=-'=-'=-'=-'=-~~'=-'=-'=-vX~-------_t----IX~----++_------,-"-X'=-'=_'=_4r:.'=_'=_~X'::.'=-i'=-'=-'=-'=-vX~--------t+--~--.!:O.Xv,----f~----,-"-X===t===t=====1~~t~t~~~~~~~
•• •
•• ••• •••
f--f--__---=:"'~"'~C--4_------!--------+_-----_+------___t.--~XXX---- ---------- ----+-- -----l----~+.~~~.;...1
BMC
•• ••
f---------'i~
I,
DIR
3
EOR
I, EORIMM
NH
OlR
2
, SECINH
2
, CLI INH
, SEI INH
2
, RSPINH
2
, NOPINH
,
-:r
, SUBnlR
3
CMP
2
OIR
3
SBC
OIR
2
3
CPX
2
OIR
3
AND
OIH
2
3
' BIT n,R
3
LDA
DIR
2
4
STA
2
TXA
INH
2
ORA
IMM
2
ADD
IMM
3
ADC
2
DIR
BSR
REL
2
lOX
IMM
2
3
3
3
'
3
SUB
XT
4
CMP
EXT
4
SBC
EXT
4
CPX
EXT
4
AND
EXT
4
BIT
XT
4
LDA
EXT
ORA
DIR
2
JSR
STA
EXT
4
EOR
EXT
3
4
ADC
EXT
3
3
•
DIR
lOX 3
2
DIR
3
STX
DIR
JSR
EXT
lOX 4
EXT
3
3
.
I
2
,~
IX'
CPX 4
IX'
2
AND
IX'
CPX 5
3
3
1~2
AND
BIT
3
lOA
5
IX2
5
IX2
5
IX2
STA
3
0
IX2
5
3
EOR
IX2
•
SBC
4
ADC
IX2
3
2
ORA'
IX2
2
ORA
IX'
2
ADD
IX'
2
JMP
IX'
3
ADD
IX2
4
JMP
3
IX2
3
3
JSR
IX2
2
ADC
IX'
JSA
IX'
4
lOX '
3
IX2
lOX
STX"
STX
EXT 3
IX2
2
2
IXl
STX
3
IX
~
1
0001
0010
rl.,
, AND'IX
,;'..
BIT
3
IX
3
o~,
I
I
IX
6
0110
,
lOA
2
4
,
I
STA
EOR
0111
IX
'(XX)
, JMP IX,
, JSR IX'
, lDX IX3
STX
7
IX
3
, ADC IX3
, ORA IX•
, ADD IX3
•,
IX'
'IX
CMP
U1
."
N
CPX •
IX
4
2 BIT 'x,
4
lOA
2
IX'
STA 0
2
IX'
4
EOA
IXI
2
SUB 3
SBC 3
IX
I
,
4
o
Hi...____l4w
1111
I
4
SBC '
IX2
3
6
4
2
1110
I, SUB ,X2 .2 SUB ,XI
4
5
CMP
CMP
IX2 2
3
IX'
•
,
1
E
,ro, ,
-.
ORA 4
EXT
4
ADD
ADD
DIR
EXT
2
3
3
2
JMP
JMP
DIR 3
EXT
2
2
6
2
3
CC)
IMemo
::t
Opcode in Binary
' - - - - - - - - - Address Mode
92CS-38011
m
III
::::I
Q.
'lJ
CD
:::l.
't:J
:::J'
CD
iii
iii'
258 ______________ CMOS Microprocessors, Memories and Peripherals
CDP6805F2
To minimize power consumption, all unused ROM locations
should contain zeros.
MASTER-DEVICE METHOD
EPROM-A 2716 EPROM, programmed with the customer
program (positive logic sel)S8 for address and data). may be
submitted for pattern generation. Fill out Customer Information of ROM Information Sheet Note that the first 128
(OOOO-007F) bytes of the EPROM correspond to the
CDP6805F2 internal RAM and 1/0 ports and will be ignored
when generating ROM masks. The 831 unused and selfcheck bytes (04B7-07F5) will also be ignored when generating ROM masks. The EPROM should be placed in a
conductive IC carrier and securely packed. Do not use
styrofoam.
~
2716
XXX=Customer 10
0000
Fig. 1a - EPROM marking.
OPTION LIST
ROM INFORMATION SHEET
Selectthe options for your MCU from the following list. A manufacturing mask will be generated from this information.
Select one in each section.
Internal Oscillator Input
Crystal
Resistor
o
o
Column 28 of Option Card
o or N
1 or P
Internal Divide
0+4
0+2
Column 29 of Option Card
o or N
1 or P
Interrupt
Column 30 of Option Card
o or N
1 or P
o
o
Edge-Sensitive
Level- and Edge-Sensitive
VECTOR LIST
Timer Interrupt from Wait State Only
Timer Interrupt
External Interrupt
SWI
RESET
CUSTOMER INFORMATION
Customer Name
Address
City
Phone (
)
Contact Ms.lMr.
Customer Part No.
PATTERN MEDIA
6805F2
EPROM
Card Deck
Other"
o
o
o
o
·Other media require factory approval.
Signature
Title
Zip
State
Extension
260 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6805F2
DATA PROGRAMMING INSTRUCTIONS (Cont'd)
DATA CARDS
The data cards contain the hexadecimal data to be programmed into the ROM device.
Each card must contain the starting address plus sixteen words of data in clusters of four Hex Bytes.
Column No.
Data
Column No.
Data
1-4
Punch the starting address
26-27
2 hex digits of 9th WORD
in hexadecimal for the
28-29
2 hex digits of 10th WORD
following data:
30
Blank
5
Blank
31-32
2 hex digits of 11th WORD
6-7
2 hex digits of 1st WORD
33-34
2 hex digits of 12th WORD
8-9
2 hex digits of 2nd WORD
35
Blank
10
Blank
36-37
2 hex digits of 13th WORD
11-12
2 hex digits of 3rd WORD
38-39
2 hex digits of 14th WORD
13-14
2 hex digits of 4th WORD
15
Blank
2 hex digits of 15th WORD
16-17
Blank
2 hex digits of 5th WORD
40
41-42
18-19
2 hex digits of 6th WORD
43-44
2 hex digits of 16th WORD
45
Semicolon, blank if last card
20
Blank
21-22
23-24
2 hex digits of 7th WORD
46-78
Blank
2 hex digits of 8th WORD
79-80
Punch 2 decimal digits
25
Blank
as in title card
"The address block must start at 0080 and run through 0486. Column 4 must be zero. One additional card starting at 07FO Is required to
specify vectors. Note that as the sample program card shows, both the 0480 and 07FO card must contain 16 data words. Zeros are used to fill
unused locations 0487-0,
•
PO,
PD.
PO,
PD2
POl
POD
"
PCl
PC2
24
23
22
PC.
PCS
PCO
"
PC>
26
25
18
OSCI
•
•
•
•
•
PC,
•
•
•
TOP VIEW
Typical full speed operating power
of15mWat5V
Typical WAIT mode power of 4 mW
Typical STOP mode power of 5 pW
Fully static operation
112 bytes of on-chip RAM
2106 bytes of on-chip ROM
32 bidirectional If 0 lines
High current drive
Internal 8-bit timer with software
programmable 7-bit prescaler
The CDP6805G2 Microcomputer Unit (MCU) belongs to
the CDP6805 Family of Microcomputers. This 8-bit MCU
contains on-chip oscillator CPU. RAM. ROM. 1/0. and
Timer. The fully static design allows operation at
frequencies down to DC. further reducing its already low-
•
•
•
•
•
•
•
•
External timer input
External and timer interrupts
Self-check mode
Master reset and power-on reset
Single 3 to 6 volt supply
On-chip oscillator with RC or crystal
mask options
True bit manipulation
Addressing modes with indexed
addressing for tables
power consumption. It is a low-power processor designed
for low-end to mid-range applications in the consumer.
automotive. industrial. and communications markers
where very low power consumption constitutes an
important factor.
RESET
1
NUM
3
IRO
2
TIMER
Port
B
1/0
Lines
PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7
Accumulator
8
Port
B
Reg
Data
Olr
Reg
8
A
Index
Register
CPU
Control
X
Data
Olr
Reg
Port
C
Reg
Condition
5
Code
Register CC
CPU
PCO
PCl
PC2
PC3
PC4
PC5
PC6
PC7
Port
C
110
Lines
Stack
Port
A
liD
Lines
PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7
6
Port
Data
A
air
Reg
Reg
POinter
S
Program
Counter
5
High PCH
8
Program
Counter
low PCl
AlU
Data
Olr
Reg
Port
0
Reg
POO
POl
P02
P03
P04
P05
P06
P07
Port
0
110
Lines
198x8
Self-Check
ROM
Fig. 1 - CDP6805G2 CMOS microcomputer block diagram.
File Number 1364
264 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6805G2
DC ELECTRICAL CHARACTERISTICS (VOO=3 Vdc, VSS=O Vdc, TA=O° to 700 C unless otherwise noted)
Symbol
Characteristics
Val
VOH
Output Voltage IloadS 1 pA
Output High Voltage
Min
VOO-O.l
Max
Unit
0.1
-
V
V
-
V
Ilload= - 50 pA) PBO-PB7, PCO-PC7
VOH
1.4
Ilload= -0.5 mA)PAO-PA7, POO-P03
VOH
1.4
V
Ilload= -2 mAl P04-P07
VOH
1.4
V
Val
-
0.3
V
2.7
VOO
VOO
VOO
0.3
V
V
V
V
mA
mA
Output low Voltage
Ilload= 300 IIA) All Ports
PAD-PA7, PBO-PB7, PCO-PC7, POO-P07
Input High Voltage
Ports PAO-PA7, PBO-PB7, PCO-PC7, POO-P07
TIMER, IRO, RESET
ascI
Input low Voltage All Inputs
Total Supply Current (no dc loads, t cyc=5ps)
VIH
VIH
VIH
Vil
RUN (measured during self-check, Vil=0.1 V, VIWVOO-O.l V)
WAIT (See Note)
STOP (See Note)
1/0 Ports Input leakage
PAD-PA7, PBO- PB7, PCO-PC7, POO-P07
VSS
100
100
100
-
1
-
0.5
150
III
-
±10
I'A
lin
-
±1
I'A
Cout
-
Cin
-
12
S
pF
pF
J.2* - - - - - - - - - - - - - '
lI- INTERNAL TIMING SIGNALS NOT AVAILABLE EXTERNALLY.
**
REPRESENTS THE INTERNAL GATING OF THE OSCI INPUT PIN.
92CS-38101
Fig. 6 - Stop recovery and power-on RESET.
FUNCTIONAL PIN DESCRIPTION
VDD and VSS
Power is supplied to the MCU using these two pins. VDD
is power and VSS is ground.
iRCi (MASKABLE INTERRUPT REQUEST)
iRQ is mask option selectable with the choice of interrupt
sensitivity being both level- and negative-edge or negativeedge only.The MCU completes the current instruction
before it responds to the request. If iFiQ is low and the interrupt mask bit (I bit) in the condition code register is clear, the
MCU begins an interrupt sequence at the end of the current
instruction.
If the mask option is selected to include level sensitivity,
then the iRCi input' requires an external resistor to VDD for
"wire-OR" operation. See the Interrupt section for more
detail.
RESET
The RESET input is not required for start-up but can be
used to reset the MCU's internal state and provide an orderly
software start-up procedure. Refer to the Reset section for a
detailed description.
TIMER
The TIMER input may be used as an external clock for the
on-chip timer. Refer to Timer section for a detailed description.
NUM - NON-USER MODE
This pin is intended for use in self-check only. User applications should connect this pin to ground through a 10 kG
resistor.
OSC1,OSC2
The CDP6805G2 can be configured to accept either a
crystal input or an RC network. Additionally, the internal
clocks can be derived by either a divide-by-two or divideby-four of the external frequency (fOSC). Both of these
options are mask selectable.
RC - If the RC oscillator option is selected, then a resistor
is connected to the oscillator pins as shown in Figure 7(b).
The relationship between Rand fosc is shown in Figure 8.
CRYSTAL - The circuit shown in Figure 7(a) is recommended when using a crystal. The internal oscillator is
designed to interface with an AT-cut parallel resonant quartz
crystal resonator in the frequency range specified for fosc in
the electrical characteristics table. Using an external CMOS
oscillator is suggested when crystals outside the specified
ranges are to be used. The crystal and components should
be mounted as close as possible to the input pins to minimize
output distortion and start-up stabilization time. Crystal frequency limits are also affected by VDD. Refer to Control
Timing Characteristics for limits. See Table 1.
EXTERNAL CLOCK - An external clock should be applied to the OSC1 input with the OSC2 input not connected,
as shown in Figure 7(c). An external clock may be used with
either the RC or crystal oscillator mask option. tOXOV or
tl LCH do not apply when using an external clock input.
268 "",,_ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6805G2
PAO-PA7
POO-P07
These eight I/O lines comprise Port A, The state of any
pin is software programmable, Refer to Input/Output Programming section for a detailed description,
These eight lines comprise Port D. PD4-PD7 also are
capable of driving LED's directly. The state of any pin is software programmable. Refer to the Input/Output Programing
section for a detailed description.
PBO-PB7
INPUT/OUTPUT PROGRAMMING
Any port pin may be software programmed as an input or
output by the state of the corresponding bit in the port Data
Direction Register (cDRl. A pin is configured as an output if
its corresponding DDR bit is set to a logic '1.' A pin is configured as an input if its corresponding DDR bit is cleared to
a logic '0.' At reset, all DDRs are cleared, which configures
all port pins as inputs. A port pin configured as an output
will output the data in the corresponding bit of its port data
latch. Refer to Figure 9 and Table 2,
These eight lines comprise Port B, The state of any pin is
software programmable, Refer to Input/Output Programming section for a detailed description.
PCO-PC7
These eight lines comprise Port C. The state of any pin is
software programmable. Refer to the Input/ Output Programming section for a detailed description.
Internal
COP6805G2
Connections
Typical Port
Data Direction
Register
Typical Port
Register
Pin
P-7
P-6
P-5
P-4
P-3
P-2
P-'
p-o
Ibl
Fig. 9 - Typical port I/O circuitry.
TABLE 2 - 1/0 PIN FUNCTIONS
R/W
0
0
DDR
1
0
1
1
,
0
1/0 Pin Function
The 1/0 pin is in input mode. Data is written into the output data latch,
Data is written Into the output data latch and output to the 1/0 pin,
The state of the 1/0 pin is read.
The 1/0 pin IS in an output mode. The output data latch IS read.
270 ______________ CMOS Microprocessors, Memories and Peripherals
CDP6805G2
TABLE 3 - SELF-CHECK RESULTS
PD3
PD2
POI
PD~
Remarks
I
0
1
0
Bad liD
1
0
1
1
Bad Timer
1
1
0
0
Bad RAM
1
1
0
1
Bad ROM
1
1
1
0
All Cycling
All Others
0
Access
Via
Page 0
Direct
AddreSSing
{'"
256
o
Port A Data
SOOOO
1
Port B Data
SooOl
2
Port C Data
SOO02
3
Port 0 Data
S0003
SooFF
4
Port A Data Direction
SOOO4
S0100
5
Port B Data Direction
SOO05
6
Port C Data Direction
SOO06
sa007
SOOOO
liD Ports
Timer
RAM
S007F
S0080
128
255
Bad Interrupt or Request Flag
Good Part
Bad Part
I
2096 Bytes
User ROM
\
2223
2224
2303
S08AF
S08BO
80 Bytes
Self-Check ROM
S08FF
2304
7
Port 0 Data Direction
8
Timer Data
S0008
9
Timer Control
S0009
o
1
S0900
SOooA
6 Bytes
5780 Bytes
Unused*
Unused"
15
16
SOOOF
S0010
I-RAM
1112 Bytes)
8063
SI F7F
8064
8Ull
8182
User
Defined
Interrupt
Vectors
{
I- ____S.:!!-~e~
R-.£M_ _ _ _ Sl FF5
Timer Interrupt From Walt State Only
1----------"Timer Interrupt
1----
External Interrupt
1---1----
8191
SWI
RESET
63
64
S1F80
118 Bytes
f-
/7
I
,/
SIFF6- S1FF7
I
SlFF8-S1FF9
*Reads of unused locations undefIned.
Fig. 11 - Address map.
'"
/
/
/
SI FFA-Sl FFB
I
SlFFC-S1FFD
SlFFE-S1FFF
12
S003F
S0040
""
"" "" Stack (64 Bytes Maxi
L,..-""
""
+
S007F
272 ______________ CMOS Microprocessors, Memories and Peripherals
CDP6805G2
machine state during interrupts. During external or poweron reset, and during a "reset stack pointer" instruction, the
stack pointer is set to its upper limit ($OO7F). Nested interrupts and/or subroutines may use up to 64 (decimal) locations, beyond. which the stack pointer "wraps around" and
points to its upper limit thereby losing the previously stored
information. A subroutine call occupies two RAM bytes on
the stack, while an interrupt uses five bytes.
CONDITION CODE REGISTER (CC)
The condition code register is a 5-bit register which indicates the results of the instruction just executed. These
bits can be individually tested by a program and specific action taken as a result of their state. Each bit is explained in
the following paragraphs.
HALF CARRY BITS (H) - The H-bit is set to a one when
a carry occurs between bits 3 and 4 of the ALU during an
ADD or ADC instruction. The H-bit is useful in binary coded
decimal subroutines.
INTERRUPT MASK BIT (I) - When the I-bit is set, both
the external interrupt and the timer interrupt are disabled.
Clearing this bit enables the above interrupts. If an interrupt
occurs while the I-bit is set, the interrupt is latched and is
processed when the I-bit is next cleared.
NEGATIVE (N) - Indicates that the result of the last
arithmetic, logical, or data manipulation is negative (bit 7 in
the result is a logical one).
ZERO (Z) - Indicates that the result of the last arithmetic,
logical, or data manipulation is zero.
CARRY IBORROW (e) - Indicates that a carry or borrow
out of the arithmetic logic unit (ALU) occurred during the
last.arithmetic operation. This bit is also affected during bit
test and branch instructions, shifts, and rotates.
RESETS
The CDP6805G2 has two reset modes: an active low
external reset pin (RESET) and a power-on reset function;
refer to Figure 5.
RESET
o
The R"ES'Ef input pin is used to reset the MCU to provide
an orderly software sta~rocedure. When using the external reset mode, the RESET pin must stay low tor a mlnlmum of one tcyc. The RESET pin is provided with a Schmitt
Trigger input to improve its noise immunity.
POWER-ON RESET
The power-on reset occurs when a positive transition is
detected on VDD. The power-on reset is used strictly for
power turn-on conditions and should not be used to detect
any drops in the power supply voltage. There is no provision
for a power-down reset. The power-on circuitry provides for
a 1920 tcyc delay from the time of the first oscillator operation. If the external RESET pin is low at the end of the 1920
tcyc time out, the processor remains in the reset condition.
* Any current instruction including SWI.
Either of the two types of reset conditions causes the
following to occur:
- Timer control register interrupt request bit TCR7 is
cleared to a "0."
- Timer control register interrupt mask bit TCR6 is set to a
"1."
- All data direction register bits are cleared to a "0." All
ports are defined as inputs.
- Stack pointer is set to $OO7F.
- The internal address bus is forced to the reset vector
($1 FFE, $1 FFF).
- Condition code register interrupt mask bit (I) is set to a
"1."
- STOP and WAIT latches are reset.
- External interrupt latch is reset.
All other functions, such as other registers (including output ports), the timer, etc., are not cleared by the reset conditions.
INTERRUPTS
The CDP6805G2 may be interrupted by one of three
different methods: either one of two maskable hardware
interrupts (external input or timer) or a nonmaskable
software Interrupt (SWI). Systems often require that
normal processing be interrupted so that some external
event may be serviced.
Interrupts cause the processor registers to be saved
on the stack and the interrupt mask (I bit) set to prevent
additional interrupts. The RTI instruction causes the
register contents to be recovered frOm the stack
followed by a return to normal proceSSing. The stack
order is shown in Figure 13.
Unlike RESET, hardware interrupts do not cause the
current instruction execution to be halted, but are
considered pending until the current instruction
execution Is complete.
Note
The current instruction is considered to be the one
already fetched and being operated on.
When the current instruction is complete, the
processor checks all pending hardware interrupts and
if unmasked (I bit clear), proceeds with interrupt
processing; otherwise, the next instruction Is fetched
and executed. Note that masked interrupts are latched
for later Interrupt service.
If both an external interrupt and a timer Interrupt are
pending at the end of an instruction execution, the
external interrupt Is serviced first. The SWI is executed
the same as any other instruction and as such takes
precedence over hardware interrupts only if the I bit is
set (hardware interrupts masked). Refer to Figure 14 for
the interrupt and instruction processing sequence.
Table 4 shows the execution priority of the RESET,
IRQ and timer interrupts, and instructions (including
the software Interrupts, SWI). Two conditions are
shown, one with the I bit set and the other with I bit
clear; however, in either case FiESEThas the highest
priority of execution. If the I bit is set as per Table 4(a),
the second highest priority is aSSigned to any instruction
including SWI.:....!bls is illustrated In Figure 14 which
shows that the IRQ orTlmer Interrupts are not executed
when the I bit is set. If the I bit is cleared as per Table
4(b), the priorities change In that the next instruction
!§]til or other instruction) Is not fetched until after the
IRQ and Timer interrupts have been recognized (and
serviced). Also, when the I bit is clear.,JLboth TFiC:i and
Timer interrupts are pending, the IRQ interrupt is
always serviced before the Timer interrupt.
274 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6805G2
Note
Processing is such that at the end of the cu rrent
instruction execution, the I bit is tested and if set the
next instruction (including SWI) is fetched. If the I bit is
cleared, the hardware interrupt latches are tested, and
if no hardware interrupt is pending, the program falls
through and the next instruction is fetched.
TIMER INTERRUPT
If the timer interrupt mask bit (TCRS) is cleared, then
each time the timer decrements to zero (transitions
from $01 to $00) an interrupt request is generated. The
actual processor Interrupt is generated only If the
interrupt mask bit of the condition code register is also
cleared. When the interrupt is recognized, the current
state of the machine is pushed onto the stack and the
interrupt mask bit in the condition code register is set.
This masks further interrupts until the present one is
serviced. The processor now vectors to the timer
interrupt service routine. The address for this service
routine is specified by the contents of $1 FF8 and $1 FF9
unless the processor is in a WAIT mode in which case
the contents of $1 FFS and $1 FF? specify the timer
service routine address. Software must be used to clear
the timer interrupt request bit (TCR?). Atthe end of the
timer interrupt service routine, the software normally
executes an RTI instruction which restores the machine
state and starts executing the interrupted program.
EXTERNAL INTERRUPT
If the interrupt mask bit of the condition code register
is cleared and the external interrupt pin (IRQ) is low,
then the external interrupt occurs. The action of the
external interrupt is identical to the timer interrupt with
the exception that the service routine address is
specified by the contents of $1 FFA and $1 FFB. Either a
level- and edge-sensitive trigger (or edge-sensitive
only) are available as mask options. Figure 15 shows
both a functional diagram and timing for the interrupt
line. The timing diagram shows two different treatments
of the interrupt line (IRQ) to the processor. The first
method is single pulses on the interrupt line spaced far
enough apart to be serviced. The minimum time between
pulses is a function of the length of the interrupt service
routine. Once a pulse occurs, the next pulse should not
occur until the MPU software has exited the routine (an
RTI occurs). This time (t'LILl is obtained by adding 20
instruction cycles (tCyc ) to the total number of cycles is
takes to complete the service routine including the RTI
instruction; refer to Figure 15. The second configuration
shows many interrupt lines "wire-ORed" to form the
interrupts at the processor. Thus, if after servicing an
interrupt the
remains low, then the next interrupt is
recognized.
me
SOFTWARE INTERRUPT (SWI)
The software interrupt is an executable instruction.
The action of the SWI instruction is similar to the
hardware interrupts. The SWI is executed regardless of
the state of the interrupt mask in the condition code
register. The service routine address is specified by the
contents of memory locations $1 FFC and $1 FFD. See
Figure 14 for interrupt and instruction processing
flowchart.
lal Interrupt Functional Diagram
Level Sensitive
Mask Option
VDD . . . - - - - ,
D
External
Interrupt
Request
O~----I
Interrupt Pin - - - - - 4 0 - - - U j C
a
I Bit ICCRI
Power-On Reset
External Reset
External Interrupt
Beinq Serviced
(bl Interrupt Mode Diagram
III
iRi5~tILIH
u
~i"If-----tILlL----I1~
121
Edge Condition
IThe minimum pulse Width ItlLIH IS one
tCyc· The peflod tlLlL should not be
less than the number of tcyc cycles It
takes to execute the interrupt service routine plus 20 tcyc cycles.1
IRa IMPUIIL_ _ _ _ _ _ _ _ _ _ _ _ _ _-...J
Mask Optional Level Sensitive
Ilf after serviCing an interrupt the IRa reo
mains low, then the next interrupt is recognizedl
•
IR()n
Fig. 15 - External interrupt.
276 ______________ CMOS Microprocessors, Memories and Peripherals
CDP6805G2
Oscillator Active
Clear I-Bit
Timer Clock Active
All Other Clocks
Stop
Fetch External
Interrupt Reset.
or Timer Interrupt
Vector (from Wait
Mode only)
Fig. 17 - Wait function flowchart.
TIMER INPUT MODE 2
With TCR4= 1 and TCR5=O, the internal clock and the
TIMER input pin are ANDed together to form the timer input
signal. This mode can be used to measure external pulse
widths. The external pulse simply turns on the internal clock
for the duration of the pulse. The resolution of the count in
this mode is ± 1 clock and, therefore, accuracy improves
with longer input pulse widths.
TIMER INPUT MODE 3
If TCR4=O and TCR5= 1, then all inputs to the Timer are
disabled.
TIMER INPUT MODE 4
If TCR4 = 1 and TCR5 = 1, the internal clock input to the
Timer is disabled and the TIMER input pin becomes the input to the Timer. The timer can, in this mode, be used to
count external events as well as external frequencies for
generating periodic interrupts. The counter is clocked on the
falling edge of the external signal.
Figure 18 shows a block diagram of the Timer subsystem.
Power-on Reset and the STOP instruction cause the counter
to be set to $FO.
278 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6805G2
INSTRUCTION SET
The MCU has a set of 61 basic instructions. They can be
divided into five different types: register/memory,
read/modify/write, branch, bit manipulation, and control.
The following paragraphs briefly explain each type. All the
instructions within a given type are presented in individual
tables.
REGISTER/MEMORY INSTRUCTIONS
Most of these instructions use two operands. One
operand is either the accumulator or the index register. The
other operand is obtained from memory using one of the addreSSing modes. The operand for the jump unconditional
IJMPI and jump to subroutine IJSR) instructions is the
program counter. Refer to Table 5.
REAO/MOOIFY /WRITE INSTRUCTIONS
These instructions read a memory location or a register,
modify or test its contents, and write the modified value
back to memory or to the register. The test for negative or
zero ITST) instruction is an exception to the
read/modify/write sequence since it does not modify the
value. Refer to Table 6.
BRANCH INSTRUCTIONS
Most branch instructions test the state of the Condition
Code Register and if certain criteria are met. a branch is executed. This adds an offset between + 128 and -127 to the
current program counter. Refer to Table 7.
BIT MANIPULATION INSTRUCTIONS
The MPU is capable of setting or clearing any bit which
reSides in the first 256 bytes of the memory space, where all
port registers, port DDR's, timer, timer control, and on-chip
RAM reside. An additional feature allows the software to
test and branch on the state of any bit within these 25610cations. The bit set, bit clear and bit test and branch functions
are all implemented with a single instruction. For the test
and branch instructions the value of the bit tested is also
placed in the carry bit of the Condition Code Register. Refer
to Table 8 for instruction cycle timing.
CONTROL INSTRUCTIONS
These instructions are register reference instructions and
are used to control processor operation during program execution. Refer to Table 9 for instruction cycle timing.
ALPHABETICAL LISTING
The complete instruction set is given in alphabetical order
in Table 11.
OPCODE MAP
Table 10 is an opcode map for the instructions used on
the MCU.
ADDRESSING MODES
The MCU uses ten different addressing modes to give the
programmer an opportunity to optimize the code to all situations. The various indexed addressing modes make it possible to locate data tables, code conversion tables and scalling
tables anywhere in the memory space. Short indexed accesses are single byte instructions, while the longest instructions Ithree bytes) permit tables throughout memory. Short
and long absolute addressing is also included. One and two
byte direct addressing instructions access all data bytes inmost applications. Extended addressing permits jump instructions to reach all memory. Table 11 shows the addressing modes for each instruction, with the effects each instruction has on the Condition Code Register. An opcode
map is shown in Table 10.
The term "Effective Address" lEA) is used in describing
the various addressing modes, which is defined as the byte
address to or from which the argument for an instruction is
fetched or stored. The ten addressing modes of the processor are described below. Parentheses are used to indicate
"contents of," an arrow indicates "is replaced by" and a colon indicates concatenation of two bytes.
INHERENT
In inherent instructions all the information necessary to
execute the instruction is contained in the opcode. Operations specifying only the index register or accumulator, and
no other arguments, are included in this mode.
IMMEDIATE
In immediate addressing, the operand is contained in the
byte immediately following the opcode. Immediate addressing is used to access constants which do not change during
program execution le.g., a constant used to initialize a loop
counter).
EA=PC+1; PC-PC+2
DIRECT
In the direct addressing mode, the effective address of the
argument is contained in a single byte following the opcode
byte. Direct addressing allows the user to directly address
the lowest 256 bytes in memory with a single two byte instruction. This includes all on-chip RAM and I/O registers
and 128 bytes of on-chip ROM. Direct addressing is efficient
in both memory and time.
EA=IPC+11; PC-PC+2
Address Bus High-O; Address Bus Low-IPC+ 1)
EXTENDED
In the extended addressing mode, the effective address of
the argument is contained in the two bytes following the opcode. Instructions with extended addressing modes are
capable of referencing argument~ anywhere in memory with
a single three byte instruction.
EA=IPC+11IPC+2); PC-PC+3
Address Bus High-IPC+ 1); Address Bus Low-IPC+21
INDEXED, NO-OFFSET
In the indexed, no offset addressing mode, the effective
address of the argument is contained in the 8-bit index
register. Thus, this addressing mode can access the first 256
memory locations. These instructions are only one byte long
and therefore are more efficient. This mode is used to move
a pointer through a table or to address a frequency referenced RAM or I/O location.
EA=X; PC-PC+1
Address Bus High-O; Address Bus Low-X
TA 3LE5-
Addressing Modes
REG ISTERIMEMORY INSTRUCTIONS
Indexed
(IS-Bit Offset)
Indexed
(S-Bit Offset)
Op
Code
I
Cycles
Op
Code
,
,
Bytes
Bytes
Cycle.
E6
2
4
06
3
5
2
4
5
2
5
DE
07
3
4
EE
E7
3
6
4
EF
2
5
OF
3
6
3
EB
2
4
DB
3
5
F9
,
3
E9
2
4
09
3
5
FO
1
3
EO
2
4
DO
3
5
4
F2
1
3
E2
2
4
02
3
5
4
4
F4
4
04
3
E4
EA
2
FA
,
3
CA
3
3
2
4
OA
3
3
5
5
,
Op
Code
#
Bytes
I
Cycles
Op
Code
#
#
Mnemonic
Bytes
Cycles
Op
Code
I
Bytes
I
Cycles
Op
Code
#
Bytes
Load A from Memory
LOA
A6
2
2
C6
3
4
2
-
2
-
CE
3
4
1
B7
2
3
4
3
3
Store A in Memory
AE
-
F6
FE
1
LOX
STA
2
2
3
Load X from Memory
B6
BE
C7
3
5
F7
1
Store X in Memory
STX
-
-
-
BF
2
4
CF
3
5
FF
1
Add Memory to A
Add Memory and
Carry to A
ADD
AB
2
2
BB
2
3
CB
3
4
FB
1
AOC
A9
2
2
B9
2
3
C9
3
4
Subtract Memory
SUB
AO
2
2
BO
2
3
CO
3
4
Subtract Memory from
A with Borrow
SBC
A2
2
2
B2
2
3
C2
3
2
2
B4
2
BA
3
3
C4
2
2
2
Function
Cycles
1
,
AND Memory to A
AND
OR Memory with A
ORA
A4
AA
Exclusive OR Memory
with A
EOR
A8
2
2
B8
2
3
C8
3
4
F8
1
3
E8
2
4
08
3
5
Arithmetic Compare A
o !
c
;R
C»
~
G)
N
CMP
A1
2
2
B1
2
3
C1
3
4
F1
1
3
E1
2
4
01
3
5
Arithmetic Compare X
with Memorv
CPX
A3
2
2
B3
2
3
C3
3
4
F3
1
3
E3
2
4
03
3'
5
o
Bit Test Memory with
A I Logical Comparel
BIT
A5
2
2
B5
2
3
C5
3
4
F5
1
3
E5
2
4
05
3
5
oen
Jump Unconditional
JMP
-
-
2
2
CC
3
3
FC
EC
2
3
DC
3
4
i:
BO
2
5
CD
3
6
FO
,
2
JSR
-
BC
Jump to Subroutine
5
ED
2
6
DO
3
7
With Memory
i
Indexed
(No Offset)
Extended
Direct
Immediate
TABLE 6READ/MOOIFYIWRITE INSTRUCTIONS
Addressing Modes
Inherent (X)
Inherent (A)
Function
Mnemonic
1
Op
Code
#
,
#
Bytes
Cycles
7A
,
5
5
7F
73
1
1
5
5
5
70
1
5
#
#
Cycles
Op
Code
#
,
Bytes
Cycles
1
3C
3A
2
2
5
5A
3
3
Op
Code
7C
5
5F
3F
53
,
3
3
33
2
2
5
5
Op
Code
3
5C
3
Indexed
(S-Bit Offset)
Indexed
(No Offset)
Direct
#
#
Cycles
#
Cycles
2
6
6
,;1
6
CD
63
2
2
60
2
6
INC
Decrement
DEC
4C
4A
Clear
CLR
4F
,
,
Complement
COM
43
1
3
3
Negate
12's Complement)
NEG
40
1
3
50
1
3
30
2
Rotate Left Thru Carry
ROL
49
1
3
59
1
3
39
2
5
79
1
5
69
2
6
76
1
5
56
2
6
Rotate Right Thru
Carry
6
1
3
36
2
3
56
1
3
5
78
1
5
68
2
6
54
1
3
38
34
2
3
2
5
74
1
5
64
2
6
1
3
57
1
3
37
2
5
77
1
5
67
2
6
1
3
50
1
3
3D
2
4
7D
1
4
60
2
5
1
3
Logical Shift Left
LSL
LSR
46
44
1
Logical Shih Right
1
ASR
47
TST
40
or Zero
2
56
46
Arithmetic Shift Right
6C
6A
6F
5
ROR
Test for Negative
1
I
#
Bytes
Op
Code
Increment
1
9"
'0
Bytes
#
Bytes
s:
i:
~::I.
I
!a.
!:::r
'0
~
iii'
o
TABLE 10 - INSTRUCTION SET OPCODE MAP
BltMl _ _
.:..
rr'Jn
I,BRSEJP.
.J"
13BRCL
-'
•
J"
13BRCL:T~
,~,
O1~O
O~,
,:"
9
'001
,~o
.'
-'
BCL~~r
BRA • 12 NEGOIR
;'El
3
BRNR"
BSE!l:
5
BHI 3
REl
3
•
12 BCL~~c 12 BLSR"
5
3
BSE!~c I, BCCRB
.' 12 BCL~~c5 I,
:l.
13BRCL
BRCL~,3:
3
1 2 BNEREL
5
3
BCL~~c
I? BEQR"
,3
BRSEJi 12 BSE!~c 12 BHC~"
5
3
BRCL::' '? BCL~~c , BHC~FI
5
3
BRSEJli: 12 BSE~c . 2 BPLREl
5
.'
.
1011
,f..
3BRSE
Jf..'_5
.
5
I? BCLR5 .?
.sc
,
12 BSE!~c
'2
BM~EL
5
2 ROROIR
5
? ASROIR
5
? LSLnlR
5
2 ROLOIR
5
2 DEC
OIR
NEG'NH
2 NEG
IX'
I
NEG
3
3
,
COM~"
COM X
1
INH
3
3
, LSRAINH , LSRXINM
6
? COM
IX'
6
lSR
2
IX'
,
IX
I
5
COM
lSR
9
IX
5
'00'
'000
5
6
NH
8
,
5
3
BCLR7
2
.sc
BILREL
3
BIH
REl
2
ll. 12 BSE!~c5 12
IiiM
DIR
A
8
•
INH
6
RTS
INH
';;",
2
·'MM
2
SBC
IMM
2
2
CPX
IMM
2
2
AND
IMM
2
2
10
SWI
INH
IX
3
3
, ROR~H
3
, ASR~H
3
LSLA
INH
3
ROLA
INH
3
DECA
INH
,
,
,
RORX
CPX 3
DIR
2
3
AND
DIA
2
3
BIT
D'R
3
LOA
2
D'R
1
INH
ROR
3
ASRX
1
INH
? ASR
3
LSLX
1
INH
? lSl
3
, ROLXINH
,
3
DECX
'NH
ROl
2
'X,
6
'X,
6
'X,
6
2
I
,
,
'x6, ,
DEC
'X,
2
5
6
,
,
ROR
LOA
IMM
'X
5
2
ASR
I
'X
5
lSL
ROL
DEC
IX
5
'x5
'x
3
2 INC
3
INH
3
TSTX
1
INH
5
3
3
DIR
CLRA
1
INH
CLRX
1
INH
O'R
, INCAINH , INCXINH
4
,
TSTolR
TSTA
1
INC
2
'Xl
5
TST
2
'Xl
,
,
2
SEC
'NH
2
CLI
INH
,
SEI
5
6
1
INC
,
RSP
INH
2
Nap
1
INH
4
1
2
'NH
1
IX
TST
IX
2
STOP
'NH
2
WAIT
1
'NH
1
CLR
2
5
6
CLR
2
'Xl
1
ClR
'X
4
TAX
'NH
2
ClC",.
2
STA
D'R
3
EaR
2
D'R
3
ADC
OIR
2
2
2
EaR
1M
2
2
ADC
'MM
Inherent
Immediate
Direct
Extended
Relative
Bit Setl Clear
Bit Test and Branch
Indexed I No Offsell
Indexed, 1 Byte IS-Bill Offset
Indexed, 2 Byte I1B-Bill Offset
•
4
LOX 3
D'R
4
STX
DIR
2
LOX
'MM
2
TXA
1
'NH
SUB '
IX2
5
CMP
IX2
3
SUB
CPX •
IX2
3
5
AND
IX2
3
5
CPX
EXT
3
4
3
AND
EXT
4
BI\XT
•
4
LOA
EXT
3
3
STA 5
EXT
3
3
4
3
EaR
EXT
3
ADC
EXT
3
4
,
2
IXI
11~.
SBC 5
IX2
3
3
ORA --.ORA'
ORA'
DIR 3
EXT
2
'MM 2
4
2
ADD 3
ADD
ADD
EXT
'MM 2
D'R 3
3
JMP
JMP
EXT
2
D'R 3
6
JSR 5
JSR 6
aSR
EXT
REl 2
2
D'R 3
Abbreviations for Addrass Modes
INH
IMM
DIR
EXT
REL
BSC
BTB
IX
IXl
IX2
--.-
,
CMP
2
,f..
SUB ,.IR I, SU~XT
4
3
CMP
CMP
EXT
2
DIR 3
4
3
SBC
SBC
OIR
EXT
2
SUB'
1X2
,~,
~
1011
1010
RTI
I
,
3
5
3
,5
3BRSE
1111
,
.~,
/Memory
Control
BI~~"
3
l1~O
BRCLRl
.T.
3
NEG
INH
3
,BRCL~~. I? BCL~~c I, BM~FI
F
.~.
3
lNH
IX
BM~"
lPn,
5
.,~,
3
5
I?
5
? COMnlR
5
, LSI),TR
,
Reod/Mod;tv/Writ.
1
I
BCSR"
-' I, BSE!~c
I,BRSEJ,3.
.:.,
~,
BRSEJl. I?
3BRCL~;.
B
BSE!~:
:f•
.'
I,BRSEJ~.
.
INH
~o
0001
2
01~
8_
R
~
00'.
C
ORA'
IX2
3
ADD 0
3
IX2
JSR
3
LOX
EXT
STX 5
3
EXT
LOX
3
IX'
4
CPX
4
AND
2
IX'
4
BIT
IX'
4
LOA
IXI
4
ADC
2
ORA
2
ADD
2
4
IX
'X,
JMP •
'X,
,X2
IX2
ORA
ADD'
IX
JSR •
2
IX'
LOX 4
'Xl
5
STX
2
'Xl
IXL .2
6
ADC '
IX
'X,
2
0
'X
EaR 3
,X
0:"
o,~,
6
0110
I
a
'000
9
'00'
I
A
1010
!
B
1011
C
1100
STX
4
F
'X
1111
1
I\)
00'.
JMP 2
'X
JSR 0
1
'X
3
LOX
1
'X
1
0
1101
E
1110
LEGEND
r--F--:;::=+----------:;~
F C
~ Opcode in Hexadecimal
Mnemonic
Bytes
Cycles
~ ~
)
/
21xl
(XXX)
,
:---t
C)
1
O~,
4
IXI
(II
2
STA
4
i
000'
.J"
STA •
IXI
2 EaR
SBC •
IX
~
rr'Jn
CPX 3
IX
3
AND
I
'X
3
BIT 'X
3
LOA
'X
,
,
,
,
,x, ,
,
,
IX2
STX
3
,
,
4
SBC
JMP
3
IX'
4
4
4
3
BIT 'X2
5
LOA
'X2
STA •
,X2
5
EaR ,X2
5
ADC
'X2
IX'
SUB 3
. IX
3
CMP
I
IX
4
CMP
2
H~
1111
IX'
2
!
IX
N
Opcode in Binary
o
3:
oen
3:
(;'
~
I
jt1
3:
Io
i'
CD
~
Q.
Address Mode
l
:1.
'0
i
i
284 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6805G2
CDP6805 FAMILY
CDP68HC05C4 CDP68HC05D2 CDP6805E2
Technology
CMOS
CMOS
CMOS
CDP6805E3
CDP6805F2
CDP6805G2
CMOS
CMOS
CMOS
40
112
Number of Pins
40
40
40
40
28
On Chip RAM (Bytes)
176
96
112
112
64
On-Chip User ROM (Bytes)
External Bus
Bidirectional I/O Lines
UndirectionalllO Lines
Other 1/0 Features
External Interrupt Inputs
STOP and WAIT
4K
2K
None
None
1K
2K
None
None
Yes
Yes
None
None
28
28
16
13
16
32
None
4 Inputs
None
3
3
None
Timer, SPI,
SCI
Timer, SPI
Timer
Timer
Timer
Timer
1
1
1
1
1
1
Yes
Yes
Yes
Yes
Yes
Yes
286 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6805G2
DATA CARDS
The data cards contain the hexadecimal data to be programmed into the ROM device.
Each card must contain the starting address plus sixteen words of data in clusters of four Hex Bytes.
Column No.
Dala
1-4
Punch the starting address
Column No.
26-27
2 hex digits of 9th WORD
Dala
2 hex digits of 10th WORD
in hexadecimal for the
28-29
following data.'
30
Blank
5
Blank
31-32
2 hex digits of 11th WORD
2 hex digits of 12th WORD
6-7
2 hex digits of 1st WORD
33-34
8-9
2 hex digits of 2nd WORD
35
Blank
10
Blank
36-37
2 hex digits of 13th WORD
11-12
2 hex digits of 3rd WORD
38-39
2 hex digits of 14th WORD
13-14
2 hex digits of 4th WORD
40
Blank
15
Blank
41-42
2 hex digits of 15th WORD
16-17
2 hex digits of 5th WORD
43-44
18-19
2 hex digits of 6th WORD
45
2 hex digits of 16th WORD
Semicolon, blank if last card
20
Blank
21-22
2 hex digits of 7th WORD
46-78
Blank
23-24
2 hex digits of 8th WORD
79-80
Punch 2 decimal digits
25
Blank
as in title card
'The address block must start at OOSO and run through OSAF. Column 4 must be zero. One additional card starting at 1FFO is required to
specify vectors. Note that as the sample program card shows, the 1FFO card must contain 16 data words. Zeros are used to fill unused
locations 1FFO - 1FFS.
To minimize power consumption, all unused ROM locations should contain zeros.
OPTION DATA CARD
.
1 234 5 6 1 8 9 101111213141516171819202122232425262728293031323334 35 3637 383940 4142 4344 45 484748 49 50 51 525354555657585960 6162 6364 65 666768 6970 717273141576 77181980
CA
I
CO
8A
IFF0
~
I I
H
C
00
507
DE.F
F b 0 C
3Aq8
7" 54
"145.5
bh 7 7
88'fQ
AA6
CCO.D
6 & F F ;
q B
00'; ¢
H5
'32.10
Fe.oC
Aqa
7b54
32.10 i
00 ••
o B DC
08EI2I
08 e.4
OSE.15
0 •••
13 A
0562
TIMER INTER UPT FROM
WAIT STATE ONLY
(8 )
01
QI
2233
H' "-
qqqqq
V'-
Pos
eq A 8
AT
"0
SSD
PPoJ
COP~e05G2
OPT \ otJ
TIME
INTERRUPT
2. r
~
;
EXTERNAL
INTERRUPT
OBTAIN FROM
RCA SALES
01
01
1211
III
SWI
RESET
DECK NUMBER
(OPTIONAL)
[12345678 91011 121314151617181920212223242528272829303132333435363138394041424344454847484950 51 52535455565758596061626364656667686970717273747576717879 80
92CL-35135
288 _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
290 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
RCA CMOS Peripherals
Can be used with CMOS and NMOS Processors
MICROPROCESSOR BUS
NON-MULTIPLEXED
MULTlPLEXEO
MOTEL BUS
Z80
6500
NSC800
Z80
6502
65C02
NOTE 1
YES
YES
YES
YES
YES
NOTE 1
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
NO
YES
YES
YES
YES
YES
NO
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
1
1
3
3
3
1
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
1
1
1
1
1
1
3
1
1
1
YES
YES
YES
USE 65C51
YES
YES
USE 6853
YES
YES
YES
USE 6853
YES
YES
YES
USE 6853
YES
' CMOS
YES
YES
YES
YES
CMOS
YES
YES
TTL
USE 65C51 USE 65C51
TTL
1
1
1
1
RCA
RCA
I/O TYPE
I/O PORTS
CDP1851
CDP1852
CDP1872
CDP1874
CDP1875
CDP6823
MEMORY
I/O DECODERS
CDP1853
CDP1858
CDP1859
CDP1866
CDP1867
CDP1868
CDP1873
CDP1881
CDP1882
CDP1883
SERIAL I/O
CDP1854A
CDP6402
CDP65C51
CDP6853
MOTOROl..'
INTEL
1802A
1804A
6805
8048 8051
80C488OC51
8049 8085
80C498OC85
8088
PROGRAMMABLE I/O PORT
BYTE-WIDE I/O PORT
8-BIT INPUT PORT
8-BIT INPUT PORT
8-BIT INPUT PORT
PARALLEL INTERFACE
(MOTEL BUS)
YES
YES
YES
YES
YES
NO
NOTE 1
YES
YES
YES
YES
YES
N-BIT 1 OF 8 DECODER
4-BIT LATCH/DECODER
4-BIT LATCH/DECODER
4-BIT LATCH/DECODER
4-BIT LATCH/DECODER
4-BIT LATCH/DECODER
1 OF 8 BINARY DECODER
6-BIT LATCH/DECODER
6-BIT LATCH/DECODER
7-BIT LATCH/DECODER
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
DESCRIPTION
AND
FUNCTION
UART
UART
UART (WITH BAUD RATE GEN.)
UART (MOTEL BUS), WITH
BAUD RATE GEN.
NSC800
INPUT FANOUT.
LEVELS
(TTL
LOADS)
MULTIPLY/
DIVIDE
CDP1655
6-BIT PROGRAMMABLE MDU
YES
NOTE 1
NOTE 1
NOTE 1
NOTE 1
NOTE 1
CMOS
1
BUFFERS
CDP1856
CDP1857
4-BIT BUS BUFFER SEPARATOR
4-BIT BUS BUFFER SEPARATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
CMOS
CMOS
1
1
VIDEO
CONTROL
CDP1869
CDP1870
CDP1876
VIDEO INTERFACE SYSTEM (VIS)
VIDEO INTERFACE SYSTEM (VIS)
VIDEO INTERFACE SYSTEM (VIS)
YES
YES
YES
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
CMOS
CMOS
CMOS
KEYBOARD
INTERFACE
CDP1871A
KEYBOARD ENCODER
YES
YES
YES
YES
YES
YES
CMOS
YES
YES
YES
NOTE 1
YES
USE 6848
USE 6818
YES
YES
USE 6848
USE 6818
YES
YES
USE 6848
USE 6818
YES
YES
YES
YES
NOTE 1
YES
YES
YES
NOTE 1
CMOS
CMOS
CMOS
CMOS
1
1
1
1
USE 1876
YES
YES
YES
YES
YES
YES
YES
USE 1678
YES
USE 1878
YES
CMOS
CMOS
1
1
YES
YES
YES
YES
YES
YES
CMOS
1
YES
NO
NO
NO
NO
NO
CMOS
1
TIMER
FUNCTIONS
CDP1863
CDP1878
CDP1879
CDP6818
CDP6848
CDP6eHC68Tl
8-BIT PROG. FREQ. GEN.
DUAL COUNTER-TIMER
REAL TIME CLOCK
REAL TIME CLOCK/RAM
(MOTEL BUS)
DUAL COUNTER-TIMER
SERIAL REAL-TIME CLOCK/RAM
AID
CONVERTER
CDP68HC68A 1
SERIAL 8-CHANNEL
A/D CONVERTER
INTERRUPT
CONTROL
CDP18n
PROGRAMMABLE
INTERRUPT CONTROLLER (PIC)
NOTES: 1. Yes but requires additional "glue parts".
2. I TTL load, I.E. S O.4V at 1.6mA.
292 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1851, CDP1851C
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VDD)
(Voltage referenced to VSS Terminal)
CDPI851 ....................................................................................................... -0.5 to +11 V
CDP1851C ....................................................................................................... -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ...................................................................... -0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ................................................................................ ±10 rnA
POWER DISSIPATION PER PACKAGE (PO):
For TA = -40 to +60° C (PACKAGE TYPE E) ........................................................................... 500 mW
For T A = +60 to +85° C (PACKAGE TYPE E) ............................................. Derate Lineary at 12 mW/o C to 200 mW
For T A = -55 to 100°C (PACKAGE TYPE D) ........................................................................... 500 mW
For T A = +100 to +125° C (PACKAGE TYPE D) ........................................... Derate Lineary at 12 mW/o C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Type) ................................................. 40 mW
OPERATING-TEMPERATURE RANGE (T A):
PACKAGE TYPE 0, H ......................................................................................... -55 to +125°C
PACKAGE TYPE E ..............................................................................................-40 to +85°C
STORAGE TEMPERATURE RANGE (Tstg) ........................................................................ -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 Inch (1.59 ± 0.79 mm) from case for 10 s max ................................................... +265°C
OPERATING CONDITIONS atTA = Full Package-Temperature Range. For maximum reliability, operating conditions should
be selected so that operation Is always within the following ranges:
LIMITS
CHARACTERISTIC
CDP1851
MIN.
DC Operating Voltage Range
Input Voltage Range
DATA
BUS
CDP1851C
MAX.
MIN.
4
10.5
4
6.5
VSS
VDD
VSS
VDD
DATA
BUS
BUFFER
CLOCK
CS
RAO
RAI
WR/IW
RDI
TPB
A
TNT
UNITS
MAX.
ADDRESS
DECODE
AND
READI
WRITE
LOGIC
INTERRUPT
MASKING
AND
LOGIC
92CM-34326RI
Fig. 1 - Functional diagram for CDP1851 and CDP1851C.
V
294 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1851, CDP1851C
FUNCTIONAL DESCRIPTION (Cont'd)
Output Mode
A peripheral STROBE pulse sent to the PIO generates an
interrupt to signal the CPU that the peripheral device is
ready for data. The CPU executes the proper output or store
instruction. Data are than read from memory and placed on
the bus. The data are latched into the port buffer at the end
of the window when REIWE = 0 and WRIRE = 1. The ROY
line is also set at this time, indicating to the peripheral that
there is data in the port buffer. The iNT line is deactivated at
the beginning of the window. After the peripheral reads
valid port data. it can send another STROBE pulse. clearing
the ROY line and activating the INT line as in the input
mode.
Bidirectional Mode
This mode programs port A to function as both an input and
output port. The bidirectional feature allows the peripheral
to control port direction by using both sets of handshake
signals. The port A handshaking pins are used to control
input data from peripheral to PIO. while the port B
handshaking pins are used to control output data from PIO
to peripheral. Data are transferred in the same manner as
the input and output modes. Since AT/iii is used for both
retMer
must be read to
I T to be activated (see
input and output. the status
determine what condition caused
Table V).
Bit-Programmable Mode
This mode allows individual bits of port A or port B to be
programmed as inputs or outputs. To output data to bits
programmed as outputs. the CPU loads a data byte into the
8 bit port as in the output mode (no handshaking). Only bits
programmed for outputs latch this data. Data must be stable
when reading from bits programmed as inputs. since the
input bits do notiatch. When the CDP1851 inputs data to the
CPU the CPU also reads the output bits latched during the
last output cycle. The ROY and STROBE lines may be used
for 1/0 by using the STROBEIRDY 1/0 control byte in table
II. An additional feature available in the bit-programmable
mode is the ability to generate interrupts based on
input/output byte combinations. These interrupts can be
programmed to occur on logic conditions (AND. OR.
NAND. and NOR) generated by the eight 1/0 lines of each
port (The STROBE and ROY lines cannot generate
i nterru pts).
AI
A2
A3
A4
CDPI800
FAMILY
fLP
A5
A6
A7
==:
TPB
wRiRE
TPB
MRD
MWR
TPA
AO
RD/WE
CLOCK
~
RAO
RAI
PIO
NO. I
WPI851
-
-
~
~
A ROY
8 ROY
A STROBE
B STROBE
PORT AO-A7
PORT BO-87
CS
VDD
10 kll
["INT
B INT
A INT
BUS 0-7
BUS 0-7
I
<
i'
7
BUS 0
LTPB
I
I
ADDRESS REGISTER
' - - - - WR/i'iE'
RD/WE
--
ADDRESS
SELECTS
8001
NO. I CONTROL!
STATUS REG
8002
NO.1 PORT A
8003
NO.1 PORT 8
8004
NO.2 CONTROL I
STATUS REG
8008
NO.2 PORT A
800C
NO.2 PORT B
CLOCK
RAO
-::=
~
=,>
RAI
CS
L
7
AiNT
iliNT
PIO
NO.2
CDPI851
=>
A ROY
B ROY
A STR08E
8 STROBE
PORT AO -A7
PORT 80-B7
92CM- 31924
Fig. 2 - Memory space I/O. This configuration allows up to four CDP1851s to occupy
memory space 8XXX with no additional hardware (A4 - A5 and A6 - A7 are used as
RAO and RA 1 on the third and fourth PIO·s).
296 ______________ CMOS Microprocessors, Memories and Peripherals
CDP1851, CDP1851 C
[RA1=O, RAO=1]
TABLE I
MODE SET"
7
6
5
4
3
2
1
0
Input
0
0
X
Set B
Set A
X
1
1
Output
0
1
X
Set B
Set A
X
1
1
Bit-Program mabie
1
1
X
Set B
Set A
X
1
1
Bidirectional
1
0
X
X
SetA
X
1
1
• Modes should be set in order as shown in Table I
If either. port is set for bit-programmable mode, the two following control bytes should immediately follow:
TABLE II
[RA1=O, RAO=1]
Bit-Programming
STROBE/ROY 1/0 Controlfl.
fl.Output = 1
7
6
5
4
3
2
1
0
1/07
1/06
1/05
1/04
1/03
1/02
1/01
1/00
07
06
05
04
03
02
01
00
fl.1 nput = 0
(00) =0
(01)
0 = Port A, 1 = Port B
(02)
0 = No change to ROY line function, 1 = Change per bit (06)
(03)
0 = No change to STROBE line function, 1 = Change per bit (07)
(04)
ROY line output data
(06 must equal 1 when outputting data)
(05)
STROBE line output data
(07 must equal 1 when outputting data)
(06)
ROY line used as:
Output = 1
Input=O
(07)
STROBE line used as:
Output = 1
Input = 0
If interrupts will be used for either bit-programmed port, the following control bytes should be loaded:
TABLE III
[RA1=O, RAO=1]
INTERRUPT CONTROL
Logical Conditions and Mask
(03)
0 = Port A, 1 = Port B
(04)
0 = No change in mask, 1 = Mask follows (See TABLE Ilia)
(05) (06)
0,0= NANO; 1,0 = OR; 0,1 = NOR; 1, 1 = ANO
TABLE lila
[RA1=O, RAO=1]
INTERRUPT CONTROL
Mask Register
(If 04 = 1)
7
6
5
4
3
2
1
0
B7
Mask
B6
Mask
B5
Mask
B4
Mask
B3
Mask
B2
Mask
B1
Mask
BO
Mask
If Bn Mask = 1 then mask Bit (for n = 0 to 7)
298 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1851, CDP1851C
FUNCTION PIN DEFINITION (Cont'd)
B INT - B INTERRUPT (Output):
AO-A7:
A low-level voltage at this output indicates the presence of
one of the interrupt conditions listed in Table III. This
output is also an open-drain NMOS device and must be tied
to a pull up resistor.
Data input or output lines for port A.
A STROBE (Input):
B RDY - B READY (Output):
An input handshaking line for port A in the input, output,
and bidirectional modes. Itcan also be used asadata bit 1/0
line when port A is in the bit-programmable mode.
This output is a handshaking or data bit 110 line in the
bit-programmable mode.
A RDY - A READY (Output):
B STROBE (Input):
TPB (Input):
An input handshaking line for port B in the input and output
modes, and for port A when it is in the bidirectional mode. It
can be used as a data bit 1/0 line in the bit-programmable
mode except when port A is not programmed as
bidirectional.
A positive input pulse used as a data load, set, or reset
strobe.
A output handshaking line or data bit 1/0 line.
WRIRE - WRITEIREAD ENABLE (Input):
A positive input used to write data from the CDP1851 to the
CPU bus.
BO-B7:
RDiWE - READIWRITE ENABLE (Input):
Data input or output lines for port B.
A positive input used to read data from the CPU bus to the
CDP1851 bus.
VSS:
VDD:
Ground
Positive supply voltage.
~e
~B
A ROY
RAQ
tlO
RDY
A SiH08E
"2'" r--TP{" r--------
RAI
CS
fllRD
TPB
RD/WE
CLOCK
L
CDPIS02
<;:>voo
BU5 0-7
&_-_.
PORT AO-A7
~I
COPI851
~IQ kn
iTiT
~I
WRiRE
TPe
1\7
i1
r
STROBE
PORT BO-87
B INT
AINT
BUS 0-7
~;>.
I
,
7
BUS 0-7
L - - RAO
' - - - - Rtd
~ A ROY
f---+
CS
CLOCK
8 ROY
t=
A STROBE
P STROBE
RD/WE
L
WR/RE
TPB
COPI951
L
'AiN'T
BINT
~
~
92CM-31925
Fig. 3 -110 space 110.
PORT AO-A7
PORT 80-87
300 ______________ CMOS Microprocessors, Memories and Peripherals
CDP1851, CDP1851C
A INT
1~50%
~
INPUT ~:lU-IO
f--j-----<......r - - - - - ( )
1K
.J:
SIGNAL~'
I
I
50 pF
iiTNf f--~r-------{) B
COPle51
r
A, B
1
1
1
1
:
10%
i
tpINT!
:
~ tWINT
~tSTINT-I
~
50PF
92CS-31927
Fig. 4 - Interrupt signal propagation delay time test circuit and waveforms.
ROY
i
-I
~-
I
:.
I
tWST
I
~tTPRDY
tSTRDY
II
I
I
----l
tSTINT
I
STROBE
I
t OIST
. DATA-IN
I
-r-------l, :-- tHSTDI
I
~
I
i--f- t PINT
.------I
:
Ii
!:
I
I
~tWTP8
TPB
~--------~fl~'----
_______~r---l~;_____~:-----:-------'- tWCL
CLOCK'(TPA)
:
~ tHCSCL
t esc L
CS
____----~----~:~Li------~----------
~tWRCL
WR/RE.(MRD}
---.Jr---;i
I
MEMORY SPACE
RoiwE=(MWR)
RD/WE'(MRDl
r---tRWCL
----1
i
----.Jr'----------+[----I/O SPACE
WR/RE'(TPB)
I
-------------'n~'-'-_____
-----.
RAI/RAO
i.
10 OR
II
,
t---------j-tADA
DATA BUS
I--t HATPB
·------------Xr~VA~L~ID~PO~R~T~A~D~D~R*
_ _ _ _ _ _ _ _ _J.
1
----~
Fig. 5 - Input mode timing waveforms.
. :1..._ _ __
I
I
~tHADOH
C
92CM-31928
50'10
302 ______________ CMOS Microprocessors, Memories and Peripherals
CDP1851, CDP1851C
OO _ _ _ _ _ _ _.J
tWINT
~
-1 ~ --
tSTINT ~
:
:----r-
CLOCK' ITPA)
I
tSTRDY~:
i -i ~tWRDY
STROBE
f4-
LL-
RDY _ _ _ _ _ _ _.....,:_ _~
~~tWTPB
-IWCL I
I
I
I
~
I
I
---'. 'WSTi---
-+-_-+'_________
------lI I1'-_ _
---i i:
--.r--Tl
:
---1
I---'---+---i,i--------tHCSCL
CS
'CSCL
DATA- OUT
,
I ,..-_ _ _ _ _ _ _- -
: :
r---~IWDO
:--- 'WRCL --;
i
i
MEMORY SPAC~
,:
WR/AE'IMRD)}J
RD/WE'lm)
LJi---------
:
I-------t--IWW*
I
WR/RE'ITPBJ
_
_
RD/WE'IMRD)
:
I/O SPACE:
--l 'RWCLI
I
..II
I
n
:
I
I
I
,:
I
r-1AW---<
RAI/RAO
X,-__VA_L_'D_DA_T_A_O_U_T_ _
~----~----+,--{,I-
---""""It
r
DATABUS--o..
* WRITE IS THE OVERLAP OF
---i 'HAwi--
VALIDr6gn~DDR
,
X,..------
-::~D:: *\.__-~'.;.;H~D_W::._-_-_-_~~-_-.,.-----
WR/RE" AND RD/WE' 0
Fig. 6 - Output mode timing waveforms.
92CM- 31920
304 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1852, CDP1852C
A a:EA'R' control is provided for resetting
the port's register (000-007 = 0) and service request flip-flop (input mode: SRI
SR=l and output mode: S"R/SR=O).
The CDP1852 is functionally identical to
the CDP1852C. The CDP1852 has a recommended operating voltage range of 4 to 10.5
volts, and the CDP1852C has a recom-
mended operating voltage range of 4 to 6.5
volts.
The CDP1852 and CDP1852C are supplied
in 24-lead, hermetic, dual-in-line ceramic
packages (0 suffix), in 24-lead dual-in-line
plastic packages (E suffix). The CDP1852C
is also available in chip form (H suffix).
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Voo)
(Voltage referenced to Vss Terminal
CDP1852 ............................•......................•................. -0.5to+ll V
CDP1852C ..................................................................... -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ..............•....•..................•-0.5 to Voo + 0.5 V
DC INPUT CURRENT, ANY ONE INPUT ................................................. ±10 mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60°C (PACKAGE TYPE E) ......................•..................... 500 mW
For TA = + 60 to + 85° C (PACKAGE TYPE E) ............ Derate Linearly at 12 mW/o C to 200 mW
For TA = -55 to + 100° C (PACKAGE TYPE D) .........•...•............................. 500 mW
For TA = + 100 to + 125°C (PACK~GE TYPE D) .....•... Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T. = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ............... 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPES D, H ......................................................... -55to+125°C
PACKAGE TYPE E •............................................................. -40 to +85°C
STORAGE TEMPERATURE RANGE (Tot,) ......................................... -65 to + 150°C
LEAD' TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max .................... +265°C
RECOMMENDED OPERATING CONDITIONS at T. = Full Package Temperature Range.
For maximum reliability, operating conditions should be selected so that operation is always
within the following ranges:
LIMITS
CDP1852
CDP1852C
Max.
Min.
Max.
Min.
4
10.5
4
6.5
Vee
Vee
Vss
Vss
CHARACTERISTIC
DC Operating Voltage Range
Input Voltage Range
CSI/Cfi* I
CS2 13
MODEjt:~~~~~~LJ
CLOCK II
14
CLlD:
000
00'
002
00'
0%7
-~'--
_ _...J
PI
P23
1---"=:-+--"""---1
92CS- 27!574R I
Fig. 2 - Block diagram of CDP1852.
UNITS
V
306 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1852, CDP1852C
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C (Cont'd)
LIMITS
CONDITIONS
CDP1852C
CHARACTERISTIC
Vo
V,N VDD
CDP1852
(V)
Typ.' Max. Min. Typ.' Max.
(V) (V)
Min.
I nput Current,
0,5
±1
±1
5
0,10 10
lIN
±2
3-State Output
Leakage Current,
0,5
0,5
5
±1
±1
0,10 0,10 10
±2
louT
Operating
0,5
130 300
5
150
300
550 800
Current, IDD,t
0,10 10
Input
Capacitance, C 'N
7,5
5
5
7.5
UNITS
-
JiA
-
Output
Capacitance, COUT
-
-
-
-
5
7.5
-
-
pF
-
"TYPical values are for T. = 25°C and nominal Voo.
tlol = 10H = l/lA.
~Operating current is measured at 2 MHz in an CDP1802 system with open outputs and a
program of 6N55, 6NAA, 6N55, 6NAA, ------.
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = - 40 to + 85° C, V DD
t" tf = 20 ns, V,H = 0.7 V DD , V'l = 0.3 V DD , Cl = 100 pF, and 1 TTL Load
CHARACTERISTIC
VDD
(V)
MODE 0 - Input Port (Fig. 4)
Minimum Select Pulse Width, tsw
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
Minimum Write Pulse Width, tww
Minimum Clear Pulse Width, tClR
Minimum Data Setup Time, tDS
Mininum Data Hold Time, tDH
Data Out Hold Time, tDOHt
Propagation Delay Times, tPlH, tPHl:
Select to Data Outt, tsDo
Clear to SR, T RSR
Clock to SR, tCSR
Select to SR, tSSR
Min.
LIMITS
Typ."
-
180
-
90
90
45
80
40
-10
-5
-
-
30
15
30
15
-
-
= ± 5%,
UNITS
Max.
75
35
185
100
185
100
170
85
110
55
120
60
360
180
180
90
160
80
a
a
150
75
370
200
370
200
340
170
220
110
240
120
ns
tMinimum value is measured from CS2, maximum value is measured from CS1/CSl
"Typical values are for T. = 25° C and nominal VDO •
INPUT PORT MODE 0 - TYPICAL OPERATION
General Operation
When the mode control is tied to VSS, the
CDP1852 becomes an input port. In this
mode, the peripheral device places data
into the CDP1852 with a strobe pulse and
the CDP1852 signals the microprocessor
that data is ready to be transferred on the
strobe's trailing edge via the SR output line.
The CDP1802 then issues an input instruction that enables the CDP1852 to place the
information from the peripheral device on
the data bus to be entered into a memory
location and the accumulator of the
microprocessor.
308 ______________ CMOS Microprocessors, Memories and Peripherals
CDP1852, CDP1852C
DYNAMIC ELECTRICAL CHARACTERISTICS at T. = -40 to +85°C, VDD = ±5%,
t" tf = 20 ns, V,H = 0.7 VDD, V,l = 0.3 VDD , Cl = 100 pF, and 1 TTL Load
CHARACTERISTIC
VDD
(V)
MODE 1 - Output Port (Fig. 6)
Minimum Clock Pulse Width, leeK
5
10
5
10
5
10
5
10
Minimum Write Pulse Width, tww
Minimum Clear Pulse Width, lelR
Minimum Data Setup Time, tDS
Minimum Data Hold Time, tDH
Minimum Select-alter-Clock
Hold Time, tSH
Propagation Delay Times, tPlH, tpHl:
Clear to Data Out, tRDO
Write to Data Out, tWDo
Data I n to Data Out. tDDO
Clear to SR. tRSR
5
10
5
10
5
10
5
10
5
10
-
-
-
5
-
5
Select to SR. tSSR
10
5
10
= 25' C and
-
10
Clock to SR. tesR
'Typical values are for TA
Min.
-
LIMITS
Typ."
130
65
130
65
60
30
-10
-5
75
35
10
-5
140
70
220
110
100
50
120
60
120
-
60
120
-
60
UNITS
Max.
260
130
260
130
120
60
0
0
150
75
0
0
280
140
440
220
200
100
240
120
240
120
240
120
ns
nominal VDD .
OUTPUT PORT MODE 1 - TYPICAL OPERATION
General Operation
Connecting the mode control to VDD configures the CDP1852 as an output port. The
output drivers are always on in this mode.
so any data in the 8-bit register will be present at the data-out lines when the CDP1852
is selected. The N line and MRD connections between the CDP1852 and CDP1802
remain the same as in the input mode configuration. but now the clock input of the
CDP1852 is tied to the TPS output df the
CDP1802 and the SR output of the
CDP1852 will be used to signal the peripheral device that val id data is present on its
input lines. The microprocessor issues an
output instruction. and data from the memory is strobed into the CDP1852 with the
TPS pulse. When the CDP1852 is deselected. the SR output goes high to signal
the peripheral device.
310 ______________ CMOS Microprocessors, Memories and Peripherals
CDP1852, CDP1852C
~~------------------~/
~'--NI------------------------------------------------------
~
/~_ _6_0_ _~Z<__
SELECT_...
SR~
_______
65_ _ _ _ _ _ _ _ _ _ _
\......
. _
/
92eM- 31293Rl
Fig. 8 - Execution of a "65" output instruction showing momentary selection of input port "0".
Application Information
In a CDP1800 series microprocessor-based
system where MRD 'is used to distinguish
between INP and OUT instructions, an INP
instruction is assumed to occur at the beginning of every I/O cycle because MRD
starts high. Therefore, at the start of an
OUT instruction, which uses the same 3-bit
N code as that used for selection of an input
port, the input device is selected for a short
time (see Fig. 8). This condition forces SR
low and sets the internal SR latch (see Fig.
3). In a small system with unique N codes
for inputs and outputs, this situation does
not arise. Using the CDP1853 N-bit decoder
or equivalent logic to decode the N lines
after TPA prevents dual selection in larger
systems (see Fig. 9 and Fig. 10).
~
NO 2
IOF8
DECODER
OUT
OUT
OUT
12 OUT
~
0
I
2
3
" g~~ ~
N2 14
EN
10 OUT 6
9 OUT 7
TPA
TPB
CLOCK A I
(TPAI
EN'"
OUTPUT
'" OUTPUT ENABLED WHEi'l EN' HIGH
INTERNAL SIGNAL SHOWN FOR REFERENCE ONLY (SEE FIG. il
92CS-2.9024
92C5-29022
Fig. 9 - COP1853 timing waveforms.
Fig. 10 - COP1853 functional diagram.
312 ______________ CMOS Microprocessors, Memories and Peripherals
CDP1853, CDP1853C
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (V DD )
(All voltage values referenced to V SS terminal
CDPI853 ......•..........••................................•......... -0.5to+ll V
CDPI853C ..............................................•............. .-0.5 to + 7 V
INPUT VOLTAGE RANGE, ALL INPUTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 to VDD + 0.5 V
DC INPUT CURRENT, ANY ONE INPUT ........................................... ± 10 mA
OPERATING-TEMPERATURE RANGE (TA):
CERAMIC PACKAGES (0 SUFFIX TYPES) ............................•..... -55 to + 125oC
PLASTIC PACKAGES (E SUFFIX TYPES) .................................. -40to+85oC
STORAGE TEMPERATURE RANGE (T til) .............•...................... -65 to + 150 C
LEAD TEMPERATURE (DURING SOLdERING):
At distance 1/16 ±1/32 inch (1.59±o.79 mm) from case for 10 s max •..................... +265 C
°
°
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C. Except as noted
LIMITS
CONDITIONS
CHARACTER ISTIC
CDP1853
VO
(V)
-
-
5
10
-
0.4
0.5
0,5
0,10
5
10
1.6
2.6
4.6
9.5
D,S
0,10
5
10
-1.15
-2.6
-
Quiescent Device
Current, I L
Output Low Drive
(Sink) Current,
IOL
Output High Drive
(Source Current)
IOH
Output Voltage
Low-Level.
VOL
Output Voltage
High Level
V OH
VIN VDD
(V) (V) Min.
-
D,S
-
0,10
-
D,S
Typ_t Max_
-
5
10
Min. Typ.
-
-
3.2
5.2
-
1.6
3.2
-
-
-
mA
-2.3
-5.2
-
-1.15
-
mA
0
0.1
0
0.1
4.9
9.9
5
10
-
-
5
-2.3·
0
50
0.1
-
-
0.5,4.5
1,9
-
5
10
-
-
1.5
3
Input High Voltage
V IH
0.5,4.5
1,9
-
5
10
3.5
-
-
5
10
-
-
±1
±1
-
50
150
100
300
-
-
Any 0,5
Input 0,10
Operating Current
D,S
1001
Input Capacitance
C IN
0,10
0,5
0,10
5
10
7
-
-
-
3.5
-
-
-
5
1.5
-
-
-
50
100
-
-
jlA
jlA
-
-
-
-
5
7.5
-
5
7.5
pF
-
-
-
-
10
15
-
10
15
pF
• Operating current measured in a COP1802 system at 2MHz with outputs floating.
IOL = IOH = 1jlA
V
±1
t Typical values are for T A= 25°C and nominal voltage .
•
jlA
V
4.9
Input Low Voltage
V IL
Output Capacitance
COUT
Max.
-
0,10
.
UNITS
-
-
Input Leakage
Current liN
t
10
100
1
10
-
5
10
CDP1853C
314 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1853, CDP1853C
COP IBOO SERIES
LOAD VIA
67 INSTRUCTION
AVAILABLE
,
7 OUTPUT PORTS
'7 INPUT PORTS
Fig. 5 - N-bit decoder in a one-level I/O system.
NOTE: SYSTEM SHOWN WILL SEL.ECT
UP TO 56 INPUT AND 48 OUTPUT
PORTS, WITH ADDITIONAL. DECODING
r - - - - - - - - - - , TIotE
COP IBOO$ERIES
TOTAL NUMBER OF INPUT
AND OUTPUT PORTS CAN BE
FURTHER EXPANDED
IIO
NO, NI, NZ
'7 INPUT,
6 OUTPUT
PORTS
ItO
NO, NI, H2
7 INPUT,
6 OUTPUT
PORTS
SECTIONS
-7.
l...---j=t===~CLOCI(
A
CI.OCK B
CE
L--,N::;:O::..,;;;NI::..,;;;N2=---_ _ _ _ _ _ _--'\ :~;~~eF~'
HeM-nOIl"1
INST,
ItO
, INPUT,
e OUTPUT
PORrs
Fig. 6 - Two-level I/O using CDP1853 and CDP1852.
316 ______________ CMOS Microprocessors, Memories and Peripherals
CDP1854A, CDP1854AC
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VDD)
(Voltage referenced to VSS Terminal)
CDP1854A •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• -O.S to +11 V
CDPI8S4AC •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• , ••••••• -0.5to+7V
INPUT VOLTAGE RANGE, ALL INPUTS •••••••••••••••• , •••••••••••••••••••••••••••••••••••••••• -O.S to VDD +O.S V
DC INPUT CURRENT, ANY ONE INPUT ••••••••••••••••••••••••••••••••••••••••••••••• , ••••••••••••••••• ±10 mA
POWER DISSIPATION PER PACKAGE (PD):
For T A=-40 to +60·C (PACKAGE TYPE E)
SOOmW
For T A=+60 to +8S· C (PACKAGE TYPE E) ••••••••••••••••••••••••.••••••••••••• Derate Linearly at 12 mW/· C to 200 mW
For T A=-SS to l00·C (PACKAGE TYPE Dj" ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• SOO mW
For TA=+100 to +12S·C (PACKAGE TYPE D) ••••••••••••••••••••••••••••••••••• Derate Linearly at 12 mW/·C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FORTA=FULL PACKAGE-TEMPERATURE RANGE (All Package Types) •• ,., ••••• , •••••••••••••••••••••••••••• 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE D ••••••••••••••••••••••••••••••••••••••••••••• '"
•• , ••••••• , ••••••••••••••• , -S5 to +12S·C
PACKAGE TYPE E •••••••••••••••••••••••••••••••••••••••••••• , •••••• '"
•••••••••••••••••••••• -40 to +8S·C
STORAGE TEMPERATURE RANGE (Tstg), ••••• , •••••••••••••••••••••• , •••••••••••••••••••••• , •••••• -6S to +IS0·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 In. (I.S9 ± 0.79 mm) from case for 10 s max.
• ••••••••••••••••••••••••••••••• , •••••••• +26S·C
Mode Input High (Mode = 1)
TRANSMITTER SECTION
u
"a
... I~ IE
..J
U
I
CDPl802
INTERFACE
I
I
Ii
III
"0:
Q.
...
RE.CEIVER" SECTION
..J
"'0:
II>
l ... 34
I~
18 IS
I
SOO
25
g
~
1,2- VOO
3'VSS
21'crm
3S-NC
I
I
*
TRANSMITTER BUS
(2S-33)
II ~
I
I
I
I::: ~
u
I!
U
*
2
I II:! ~ ~ I~
%
I ...
...
~
RECEIVER BUS
(5-12)
LL-=-=-__- ~.::::. -=---~:::-= ==,r: ==:::: ==.:.::::: ::::.:::: ~J
*USER INTERCONNECT
I
1
92CM-28459R3
Fig, 1 - Mode 1 block diagram (CDP1800-series microprocessor compatible),
II
318 _________________________
CMOS Microprocessors, Memories and Peripherals
CDP1854A, CDP1854AC
Functional Definitions for CDP1854A Terminals
Mode 1
CDP1800-Serles Microprocessor Compatible
SIGNAL: FUNCTION
VDD:
Positive supply voltage
MODE SELECT (MODE):
A high-level voltage at this input selects CDP1800-series
microprocessor Mode operation.
VSS:
Ground
CHIP SELECT 2 (CS2):
A low-level voltage at this input together with CS1 and CS3
selects the CDP1854A UART.
RECEIVER BUS (R BUS 7 - R BUS 0):
Receiver parallel data outputs (may be externally connected
to corresponding transmitter bus terminals).
INTERRUPT (INT):
A low-level voltage at this output indicates the presence of
one or more of the interrupt conditions listed in Table I.
FRAMING ERROR (FE):
A high-level voltage at this output indicates that the
received character has no valid stop bit, i.e., the bit
following the parity bit (if programmed) is not a high-level
voltage. This output is updated each time a character is
transferred to the Receiver Holding Register.
PARITY ERROR or OVERRUN ERROR (PE/OE):
A high-level voltage at this output indicates that either the
PE or OE bit in the Status Register has been set (see Status
Register Bit Assignment, Table II.
REGISTER SELECT (RSEL):
This input is used to choose either the Control/Status
Registers (high input) or the transmitter/receiver data
regist,
_
,
EF;'
~-
EF ..
EF .. I
?------1j'
--0"
- --- __ _ _ _
p---
IT,
I
I RD/WR
MRD
UART
CDPI854A
INT
THRE
DA
FE
---0:'
''0---
PE/OE
500
R BUS
2. Transmitter Operation
Before beginning to transmit, the TRANSMIT REQUEST
(TR) bit in the Control Register (see bit assignment, Table
IV) is set. Loading the Control Register with TR=1 (bit
7=high) inhibits changing the other control bits, Therefore
two loads are required: one to format the UART, the second
to set TR. When TR has been set, a TRANSMITTER
HOLDING REGISTER EMPTY (THRE) interrupt will occur,
signalling the microprocessor that the Transmitter Holding
Register is empty and may be loaded, Setting TR also
causes assertion of a lOW-level on the REQUESTTO SEND
(RTS) output to the peripheral. It is not necessary to set TR
for proper operation for the UART, I! desired, it can be used
to enable THRE interrupts and to generate the RTS signal,
The Transmitter Holding Register is loaded from the bus, by
TPB during execution of an oU..!.E.!!t instruction, The
CDP1854A is selected by CS1 . CS2 . CS3=1, and the
Holding Register is selected ~t:~~EL=L and RD/WR=L.
When the CLEAR TO SEND
) input, which can be
connected to a peripheral device output, goes low, the
Transmitter Shift Register will be loaded from the Transmitter Holding Register and data transmission will begin, I!
CTS is always low, the Transmitter Shift Register will be
loaded on the first high-to-Iow edge of the clock which
occurs at least 1/2 clock period after the trailing edge of
TPB and transmission of a start bit will occur 1/2 clock
period later (see Fig, 3), Parity (if programmed) and stop
bit(s) will be transmitted following the last data bit, I! the
word length selected is less than 8 bits, the most significant
unused bits in the transmitter shift register will not be
transmitted,
RTS
0
CLEAR
MOOE
V DD
92CS-28460RI
Fig, 2 - Recommended CDP1800-series connection,
Mode 1 (non-interrupt driven system),
3. Receiver Operation
The receive operation begins when a start bit is detected at
the SER IAL DATA IN (SDI) input. After detection of the first
high-to-Iow transition on the SDI line, a valid start bit is
verified by checking for a low-level input 7-1/2 receiver
clock periods later, When a valid start bit has been verified,
tne following data bits, parity bit (if programmed) and stop
bit(s) are shifted into the Receiver Shift Register by clock
pulse 7-1/2 in each bit time, The parity bit (if programmed)
is checked and receipt of a valid stop bit is verified, On
count 7-1/2 of the first stop bit, the received data is loaded
into the Receiver Holding Register, I! the word length is less
than 8 bits, zeros (low output level) are loaded into the
unused most significant bits, I! DATA AVAILABLE (OA)
has not been reset by the time the Receiver Holding
Register is loaded, the OVERRUN ERROR (OE) status bit is
set. One hal! clock period later, the PARITY ERROR (PE)
and FRAMING ERROR (FE) status bits become valid for the
character in the Receiver Holding Register, At this time, the
Data Available status bit is also set and the DATA
AVAILABLE (DA) and INTERRUPT (INT) outputs go low,
signalling the microprocessor that a received character is
322 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1854A, CDP1854AC
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = -40 to +85 0 C, VDD ±5%, t r ,t,=20 ns, VIWO.7 VDD, VIL =0.3 VDD,
CL =100 pF, see Fig. 3.
LIMITS
CHARACTERISTIC
CDP1854A
VDD
(V)
TXp·t
Max.*
CDP1854AC
Typ.t
Max.*
UNITS
Transmitter Timing - Mode 1
Minimum Clock Period
tcc
Minimum Pulse Width:
Clock low level
tCl
Clock High level
tCH
TPB
tTT
Minimum Setup Time:
TPBto Clock
TPB to THRE
--
310
250
310
125
155
-
-
5
100
125
100
125
10
75
100
-
-
5
100
125
100
125
10
75
100
-
-
5
100
150
100
150
10
50
75
-
--
5
175
225
175
225
10
90
150
-
-
5
300
450
300
450
tCD
10
150
225
-
-
tTTH
Clock to THRE
250
tTC
Propagation Delay Time:
Clock to Data Start Bit
5
10
tCTH
5
200
300
200
300
10
100
150
-
-
5
200
:?OO
200
300
10
100
150
-
-
tTyplcal values are for TA=25' C and nominal voltages.
*Maximum limits of minimum characteristics are the values above which all devices function.
7~
I I
T CLOCK
---.r-l
I, f-I---tI-+I----------oIlIl------!-i- - - - I TC
WRITE!
ITPB)
'fHiiE
.... I-tCD
1
~
'TTH
1-..1
_'CTH
~ !~I
i !
-------~
I
I
))
~---------~u·-----~I------
..,.j r-'CD
I
------IL..I1L-_________~!>_----~~~IS~T~D~~~AwB~IT~-)
SDO
* THE HOLDING REGISTER IS LOADED ON THE TRAILING EDGE OF TPB.
* * THE
TRANSMITTER SHIFT REGISTER IS LOADED ON THE FIRST HIGH -TO-LOW TRANSITION OF THE
CLOCK WHICH OCCURS AT LEAST 112 CLOCK PERIOD + 'TC AFTER THE TRAILING EDGE OF TPB, AND
!
TRANSMISSION OF A START BIT OCCURS 1/2 CLOCK PERIOD + 'CD LATER.
WRITE IS THE OVERLAP OF TPB, CSI, AND CS3 -I AND CS3, RD/WR. O.
Fig. 3 - Transmitter timing diagram - Mode 1.
92eM-.,.,.
ns
ns
ns
ns
ns
ns
ns
ns
324 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1854A, CDP1854AC
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, VDD ±5%, t r ,tf=20 ns, VIWO.7 VDD, Vll=0.3 VDD,
Cl =100 pF, see Fig. 5.
LIMITS
CHARACTERISTIC
CDP1854A
CDP1854AC
UNITS
VDD
(V)
Typ.t
Max.*
TYD.t
Max.*
CPU Interface - WRITE Timing - Mode 1
Minimum Pulse Width:
5
100
150
100
150
tn
10
50
75
-
-
5
50
75
50
75
tRSW
10
25
40
-
-
5
-30
-15
0
Q
-30
0
10
-
-
TPB
Minimum Setup Time:
RSEl to Write
Data to Write
tow
Minimum Hold Time:
RSEL after Write
tWRS
Data after Write
two
ns
ns
ns
5
50
75
50
75
10
25
40
-
-
5
75
125
75
125
10
40
60
-
-
ns
ns
tTypical values are for T A=25° C and nominal voltages.
*Maximum limits of minimum characteristics are the values above which all devices function.
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, VDD ±5%, I r ,lf=20 ns, VIWO.7 VDO, Vll=0.3 VOO,
Cl =100 pF. see Fig. 6.
liMITS
CHARACTERISTIC
VOD
(V)
CDP1854A
Typ.t
Min.
Max.*
UNITS
CDP1854AC
Min.
Typ.t
Max.*
100
150
CPU Interface - READ Timing - Mode 1
5
-
100
150
-
tn
10
50
75
-
-
50
75
-
50
75
tRST
10
-
25
40
-
-
-
5
-
50
75
-
50
75
tTRS
10
-
25
40
-
-
5
-
-
200
300
300
-
100
150
-
200
10
-
5
-
200
300
-
-
200
300
10
-
100
150
-
-
-
-
150
225
-
-
Minimum Pulse Width:
TPB
Minimum Setup Time:
RSEL to TPB
5
Minimum Hold Time:
RSEL after TPB
Read to Data Access Time
tRDDA
Read to Data Valid Time
tRDV
RSEL to Data Valid Time
tRSDV
Hold Time:
Data after Read
tRDH
5
-
150
225
10
-
75
125
5
50
150
-
50
150
-
10
25
75
-
-
-
-
tTypical values are for TA=25° C and nominal voltages.
*Maximum limits of minimum characteristics are the values above which all devices function.
ns
ns
ns
ns
ns
ns
ns
326 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1854A, CDP1854AC
Functional Definitions for CDP1854A Terminals
Standard Mode 0
SIGNAL: FUNCTION
VDD:
Positive supply voltage.
MODE SELECT (MODE):
A low-level voltage at this input selects Standard Mode 0
Operation.
VSS:
Ground.
RECEIVER REGISTER DISCONNECT (RRD):
A high-level voltage applied to this input disconnects the
Receiver Holding Register from the Receiver Bus.
RECEIVER BUS (R BUS 7 - R BUS 0):
Receiver parallel data outputs.
PARITY ERROR (PE):
A high-level voltage at this output indicates that the
received parity does not compare to that programmed by
the EVEN PARITY ENABLE (EPE) control. This output is
updated each time a character is transferred to the Receiver
Holding Register. PE lines from a number of arrays can be
bused together since an output disconnect capability is
provided by the STATUS FLAG DISCONNECT (SFD) line.
FRAMING ERROR (FE):
A high-level voltage at this output indicates that the
received character has no valid stop bit, i.e., the bit
following the parity bit (if programmed) is not a high-level
voltage. This output is updated each time a character is
transferred to the Receiver Holding Register. FE lines from
a number of arrays can be bused together since an output
disconnect capability is provided by the STATUS FLAG
DISCONNECT (SF D) line.
OVERRUN ERROR (OE):
A high-level voltage at this output indicates that the DATA
AVAILABLE (DA) flag was not reset before the next
character was transferred to the Receiver Holding Register.
OE lines from a number of arrays can be bused together
since an output disconnect capability is provided by the
STATUS FLAG DISCONNECT (SFD) line.
TRANSMITTER HOLDING REGISTER EMPTY (THRE):
A high-level voltage at this output indicates that the
Transmitter Holding Register has transferred its contents
to the Transmitter Shift Register and may be reloaded with
a new character.
TRANSMITTER HOLDING REGISTER LOAD (THRL):
A low-level voltage applied to this input enters the character
on the bus into the Transmitter Holding Register. Data is
latched on the trailing edge of this signal.
TRANSMITTER SHIFT REGISTER EMPTY (TSRE):
A high-level voltage at this output indicates that the
Transmitter Shift Register has completed serial transmission
of a full character including stop bit(s). It remains at this
level until the start of transmission of the next .character.
SERIAL DATA OUTPUT (SDO):
The contents of the Transmitter Shift Register (start bit,
data bits, parity bit, and stop (bit(s» are serially shifted out
on this output. When no character is being transmitted, a
high-level is maintained. Start of transmission is defined as
the transition of the start bit from a high-level to a low-level
output voltage.
TRANSMITTER BUS (T BUS 0 - T BUS 7):
Transmitter parallel data inputs.
CONTROL REGISTER LOAD (CRL):
A high-level voltage at this input loads the Control Register
with the control bits (PI, EPE, SBS, WLS1, WLS2). This line
may be strobed or hardwired to a high-level input voltage.
PARITY INHIBIT (PI):
A high-level voltage at Hlis input inhibits the parity generation and verification circuits and will clamp the PE output
low. If parity is inhibited the stop bit(s) will immediately
follow the last data bit on transmission.
STOP BIT SELECT (SBS):
This input selects the number of stop bits to be transmitted
after the parity bit. A high-level selects two stop bits, a
low-level selects one stop bit. Selection of two stop bits
with five data bits programmed selects 1.5 stop bits.
STATUS FLAG DISCONNECT (SFD):
A high-level voltage applied to this input disables the 3state output drivers for PE, FE, OE, DA, and THRE, allowing
these status outputs to be bus connected.
RECEIVER CLOCK (RCLOCK):
Clock input with a frequency 16 times the desired receiver
shift rate.
DATA AVAILABLE RESET (DAR):
A low-level voltage applied to this input resets the DA
flip-flop.
DATA AVAILABLE (DA):
A high-level voltage at this output indicates that an entire
character has been received and transferred to the Receiver
Holding Register.
SERIAL DATA IN (SDI):
Serial data received at this input enters the receiver shift
register at a point determined by the character length. A
high-level voltage must be present when data is not being
received.
MASTER RESET (MR):
A high-level voltage at this input resets the Receiver
Holding Register, Control Register, and Status Register,
and sets the serial data output high.
T CLOCK R CLOCK
PI
TPA
sas
DAR
WLSI
SCI
WLS2
RRD
EPE
THRL
uART
C DPl854A
TSRE
OA
SOI
SOO
R BUS
92CS-34506
Fig. 8 - Mode 0 connection diagram.
328 _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1854A, CDP1854AC
WORD LENGTH SELECT 2 (WLS2):
WORD LENGTH SELECT 1 (WLS1):
These two inputs select the character length (exclusive of
parity) as follows:
WLS2
WLS1
Word Length
Low
Low
5 Bits
Low
High
6 Bits
High
Low
7 Bits
High
High
8 Bits
EVEN PARITY ENABLE (EPE):
A high-level voltage at this input selects even parity to be
generated by the transmitter and checked by the receiver. A
low-level input selects odd parity.
TRANSMITTER CLOCK (TCLOCK):
Clock input with a frequency 16times the desired transmitter
shift rate.
holding Register by applying a lowp-ulse to the i'FiANSMITTER HOLDING REGISTER LoAD (THRL) input causing
THRE to go low. If the Transmitter Shift Register is empty
(TSRE is HIGH) and the clock is low, on the next high-tolow transition of the clock the character is loaded into the
Transmitter Shift Register preceded by a start bit. Serial
data transmission begins 1/2 clock period later with a start
bit and 5-8 data bits followed by the parity bit (if programmed) and stop bit(s). The THRE output signal goes
high 1/2 clock period later on the high-to-Iow transition of
the clock. When THREgoes high, another character can be
loaded into the Transmitter Holding Register for transmission beginning with a start bit immediately following the
last stop bit of the previous character. This process is
repeated until all characters have been transmitted. When
transmission is complete, THRE and Transmitter Shift
Register Empty (TSRE) wi!1 both be high. The format of
serial data is shown in Fig. 12. Duration of each serial
output data bit is determined by the transmitter clock
frequency (fCLOCK) and will be 16/f CLOCK.
3. Receiver Operation
Description of Standard Moda 0 Operation
(Mode Input=VSS)
1. Initialization and Controls
The MASTER RESET (MR) input is pulsed, resetting the
Control, Status, and Receiver Holding Registers and setting
the SERIAL DATA OUTPUT (SDO) signal high. Timing is
generated from the clock inputs, Transmitter Clock
(TCLOCK) and Receiver Clock (RCLOCK), at a frequency
equal to 16 times the serial data bit rate. When the receiver
data input rate and the transmitter data output rate are the
same, the TCLOCK and RCLOCK inputs may be connected
together. The CONTROL REGISTER LOAD (CRL) input is
pulsed to store the control inputs PARITY INHIBIT (PI),
EVEN PARITY ENABLE (EPE), STOP BIT SELECT (SBS),
and WORD LENGTH SELECTs (WLS1 and WLS2). These
inputs may be hardwired to the proper voltage levels (VSS
or VDD) instead of being dynamically set and CRL may be
hardwired to VDD. The CDP1854A Is then ready for
transmitter andlor receiver operation.
2. Transmitter Operation
For the transmitter timing diagram refer to Fig. 10. At the
beginning of a typical transmitting sequence the Transmitter
Holding Register is empty (THRE is HIGH). A character is
transferred from the transmitter bus to the Transmitter
The receive operation begins when a start bit is detected at
the SERIAL DATA IN (SDI) input. After the detection of a
high-to-Iow transition on the SDI line, a divide-by-16
counter is enabled and a valid start bit is verified by
checking for a low-level input 7-112 receiver clock periods
later. When a valid start bit has been verified, the following
data bits, parity bit (if programmed), and stop bit(s) are
shifted into the Receiver Shift Register at clock pulse 7-1/2
in each bit time. If programmed, the parity bit is checked,
and receipt of a valid stop bit is verified. On count 7-1/2 of
the first stop bit, the received data is loaded Into the
Receiver Holding Register. If the word length is less than 8
bits, zeros (low output voltage level) are loaded into the
unused most significant bits. If DATA AVAILABLE (DA)
has not been reset by the time the Receiver Holding
Register is loaded, the OVERRUN ERROR (OE) signal is
raised. One-half clock period later, the PARITY ERROR
(PE) and FRAMING ERROR (FE) signals become valid for
the character in the Receiver Holding Register. The DA
signal is also raised at this time. The 3-state output drivers
for DA, OE, PE and FE are enabled when STATUS FLAG
DISCONNECT (SFD) is low. When RECEIVER REGISTER
DISCONNECT (RRD) goes low, the receiver bus 3-state
output drivers are enabled and data is available at the
RECEIVER BUS (R BUS 0 - R BUS 7) outGuts. Appl~a
negative pulse to the DATA AVAILABL RESET (DAR)
resets DA. The preceding sequence of operation is repeated
for each serial character received. A receiver timing diagram
Is shown in Fig. 11.
330 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1854A, CDP1854AC
OYNAMIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, VOO ±5%, tr,tf=20 ns, VIH=0.7 VOO, VIL=0.3 VOO,
CL=100 pF, .ee Fig 11
LIMITS
CHARACTERISTIC
VOO
(V)
COP1854A
Typ.t
Max.*
COP1854AC
Typ.t
Max.*
UNITS
Receiver Timing - Mode 0
Minimum Clock Period
ICC
Minimum Pulse Widlh:
Clock Low Level
ICL
Clock High Level
ICH
DATA AVAILABLE RESET
IDD
Minimum Selup Time:
Dala Slarl Billa Clock
IDC
Proeagalion Dela:r: Time:
DATA AVAILABLE RESET 10
Dala Available
IDDA
Clock 10 Dala Valid
ICDV
Clock 10 Data Available
ICDA
Clock to Overrun Error
ICOE
Clock 10 Parily Error
ICPE
Clock 10 Framing Error
tCFE
5
10
5
10
5
10
5
10
5
250
125
100
75
100
75
50
25
100
310
155
125
100
125
100
75
40
150
250
310
-
-
100
125
-
-
100
125
-
-
50
75
-
-
100
150
10
50
75
-
-
5
10
5
10
5
10
5
10
5
10
5
10
150
75
225
110
225
110
210
100
240
120
200
100
225
125
325
175
325
175
300
150
375
175
300
150
150
2::25
-
-
225
325
-
-
225
325
-
-
210
300
-
-
240
375
-
-
200
300
-
-
tTypical values are for T A=2So C and nominal voltages.
*Maximum limits of minimum characteristics are the values above which ali devices function.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
332 ______________ CMOS Microprocessors, Memories and Peripherals
CDP1855, CDP1855C
CE
CLEAR
CTL
I
2
3
28
27
26
C,WQ.i'.
4
25
CI
YL
ZL
5
6
7
8
24
23
22
21
9
20
YR
ZR
BUS 7
BUS 6
BUS 5
SUS 4
BUS 3
BUS 2
IUS I
SUS"
mrrn
CLK
STB
RDIW'E
RA 2
RAI
RAID
VSS
VDD
CN ID
CN I
10
19
II
IB
12
17
13
16
L..14_ _ _
15....
TOP VIEW
92CS- 2996!5R2
TERMINAL ASSIGNMENT
8-Blt Programmable
MultiplyIDivlde Unit
F••tures:
•
•
•
•
•
Cascadable up to 4 units for 32-bIt by 32-bIt multiply or64 + 32 bit divide
8-bIt by 8-bIt multiply or 16 + 8 bit divide in 5.6 ps at 5 V or 2.8 ps at 10 V
Direct interface to CDP1800 Series microprocessors
Easy interface to other 8-bit microprocessors
Significantly Increases throughput of microprocessor used for arithmetic
calculations
The RCA-COP1855 and COP1855C are CMOS 8-bit
multiplyldivide units which can be used to greatly increase
the capabilities of 8-bit microprocessors. They perform
multiply and divide operations on unsigned, binary
operators. In general, microprocessors do not contain
multiple or divide instructions and even efficiently coded
multiply or divide subroutines require considerable memory
and execution time. These multiplyldivide units directly
interface to the COP1800 series microprocessors via the
N-lines and can easily be configured to fit in either the
memory or 1/0 space of other 8-bit microprocessors.
The multipleldivlde unit is based on a method of multiplying
by add and shift right operations and dividing by subtract
and shift left operations. The device Is structured to permit
cascading Identical units to handle operands up to 32 bits.
The COP1855 and COP1855C are functionally identical.
They differ in that the COP1855 has a recommended
operating voltage range of 4 - 10.5 volts, and the
COP1855C, a recommended operating voltage range of 4
- 6.5 volts.
The COP1855 and COP1855C types are supplied in a 28lead hermetic dual-in-line ceramic package (0 suffix) and
in a 28-lead dual-in-line plastic package (E suffix). The
COP1855C is also available in chip form (H suffix).
,
,
1
CLEAR
XTAL
NO
NI
N2
TPB
MRO
COP 1802
EF
BUS
~
E
C
+V
CLEAR
ClK
CE
RAO
CI
RAI
CNO
RA2
CNI
STB
RO/WE
YL COPI855
ZR
CTl
CO
YR
Zl
BUS
I
92CM-34331
Fig. 1 - Circuit configuration for MDU addressed as an 110 device.
File Number 1053
334 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1855, CDP1855C
OPERATING CONDITIONS at T A =Full Package-Temperature Range. For maximum reliability, operating conditions should
be selected so that operation Is always within the following ranges:
LIMITS
CONDInONS
CHARACTERISTIC
VDD
(V)
DC Operating Voltage Range
Input Voltage Range
Maximum Input Clock
Freauency
Minimum 8 x 8 Multiply
(16 + 8 Divide) Time
5
10
5
10
eE
RA2
CDP1855
Max.
Min.
CDP1855C
Max.
Min.
4
VSS
3.2
6.4
10.5
VDD
4
VSS
3.2
6.5
VDD
-
-
-
-
5.6
2.8
-
5:6
-
-
RA0
CLOCK
a
eNI
2~++++++l
eN0
2.'r--t-t-++-t-ot
STa
Fig. 2 - Block diagram of CDP1855 and CDP1855C.
UNITS
V
MHz
ps
336 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and, Peripherals
CDP1855, CDP1855C
OPERATION (Cont'd)
The Z register can simply be reset using bit 2 of the control
word and another divide can be done in order to further
divide the remainder.
3. Multiply Operation
For a multiply operation the two numbers to be multiplied
are loaded in the X and Z registers. The result is in the Yand
Z register with Y being the more significant half and Z the
less significant half. The X register will be unchanged after
the operation is completed.
The original contents of the Y register are added to the
product of X and Z. Bit 3 of the control word will reset
register Y to 0 if desired.
FUNCTIONAL DESCRIPTION OF CDP1855 TERMINALS
CE - CHIP ENABLE (Input):
CLK - CLOCK (Input):
A high on this pin enables the CDP1855 MDU to respond to
the select lines. All cascaded MDU's must be enabled
together. CE also controls the tristate C.O./O.F., output of
the most significant MDU.
This pin should be grounded on all but the most significant
MDU. There is an optional reduction of clock frequency
available on this pin if so desired, controlled by bit 7 of the
control byte.
CLEAR (Input):
STB - STROBE (Input):
The CDP1855 MDU(s) must be cleared upon power-on with
a low-on this pin. The clear signal resets the sequence
counters, the shift pulse generator, and bits 0 and 1 of the
control register.
When RD/WE is low data is latched from bus lines on the
falling edge of this signal. It may be asynchronous to the
clock. Strobe also increments the selected register's
sequence counter during reads and writes. TPB would be
used in CDP1800 systems.
CTL - CONTROL (Input):
This is an input pin. All CTL pins must be wired together and
to the YL of the most significant CDP1855 MDU and to the
ZR of the least significant CDP1855 MDU. This signal is
used to indicate whether the registers are to be operated on
or only shifted.
RD/WE - READ/WRITEENABLE (Input):
This signal defines whether the selected re~r is to be
read from or written to. In 1800 systems use MRD if MDU's
are addressed as 1/0 devices, MWR is used if MDU's are
addressed as memory devices.
C.O./O.F. - CO':A:-::R"'R"'Y""'O~U-:::T=-:IO':"V:-::E==R=-F==L""'O""'W"'(Output):
RA2, RA1, RAD - REGISTER ADDRESS (Input):
This Is a tristate output pi.!1.lt is the CDP1855 Carry Out
signal and is connected to CI (CARRY-IN) of the next more
significant CDP1855 MDU, except for on the most significant
MDU. On that MDU it isan overflow indicator and is enabled
when chip enables Is true. A low on this pin indicates that an
overflow has occured. The overflow signal is latched each
time the control register is loaded, but Is only meaningful
after a divide command.
These input signals define which register is to be read from
or written to. It can be seen in the "CONTROL TRUTH
TABLE" that RA2 can be used as a chip enable. It is
identifical to the CE pin, except only CE controls the tristate
c:o:7D.'F. on the most significant MDU. In 1800 systems use
N lines if MDU's are used as 1/0 devices, use address lines
or function of address lines if MDU's are used as memory
devices.
YL, YR - Y-LEFT, Y-RIGHT:
BUS D - BUS 7 - BUS LINES:
These are tristate bi-directional pins for data transfer
between the Y registers of cascaded CDP1855 MDU's. The
YR pin is an output and YL Is an input during a multiply and
the reverse is true at all other times. The YL pin must be
connected to the YR pin of the next more significant MDU.
An exception is that the YL pin of the most significant
CDP1855 MDU must be connected to the ZR pin of the least
significant MDU and to the CTL pins of all MDU's. Also the
YR pin of the least significant MDU is tiexd to the ZL pin of
the most significant MDU.
Tristate bi-directional bus fordirect interface with CDP1800
series and other 8-bit microprocessors.
ZL, ZR - Z-LEFT, Z-RIGHT:
These are tristate bl-dlrectlonal pins for data transfers
between the "Z" registers of cascaded MDU's. The ZR pin is
an output and ZL is an input during a multiply and the
reverse Is true at all other times. The ZL pin must be tied to
the YR pin of the next more significant MDU. An exception
is that the ZL pin of the most significant MDU must be
connected to the YR pin of the least "ignlflcant MDU. Also,
the ZR pin olthe least significant MDU Is tied to the YL olthe
most significant MDU.
SHIFT - SHIFT CLOCK:
This Is a tristate bl-dlrectlonal pin. It Is an output on the
most significant MDU. And an input on all other MDU's. It
provides the MDU system timing pulses. All ~ pins
must be connected together for cascaded operation. A
maximum of the 8N +1 shifts are required for an operation
where "N" equals the number of MDU devices that are
cascaded.
ZR - Z-RIGHT:
See Pin 6.
YR - Y-RIGHT:
See Pin 5.
CI-
CARRY IN (Input):
This is an input for the carry from the next less significant
MDU. On the least significant MDU it must be high (VDD)
on all others it must be connected to the CO pin of the next
less significant MDU.
CN1, CND - CHIP NUMBER (Input):
These two Input pins are wired high or low to indicate the
MDU position in the cascaded chain. Both are high for the
most significant MDU regardless of how many CDP1855
MDU's are used. Then CN1 = high and CNO = low for the
next M DU and so forth.
VSS - GROUND:
Power supply line.
VDD-V+:
Power supply line.
338 _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1855, CDP1855C
DELAY NEEDED WITH AND WITHOUT PAESCALEA
IN+1 Ihlft,/Operltlon It 1 Clock Cycll/Shlft
N = Number of MDU',
S = Shift Alte
Number
of
MDU',
No PrelCller
Mlchlne
Cycle,
Shift, = IN+1
Needed
Needed·
1
2
3
4
211 NOP)
2 (1 NOP)
3 (1 NOP)
4 (2 NOPs)
9
17
25
33
With Preecller
MlChlne
Cyel..
NHdld·
Shift
AIJI.
68
311 NOP)
9.13 NOPs)
4
200
264
33 (11 NOPs)
Shift, = S (IN+1)
Needed
18
~
~
....8.
8
"NOP Instruction is shown for machine cycles needed (3/NOP). Other Instructions may be used.
CDP1155 INTEAFACING SCHEMES
C'i:EAiii
CLnii
CDPI8ee
MDU
+voo
MAO
RAO
xm
MAl F=~~~~~ CLOCK
RAI
MAX
!!Qg
DATA
TPA 1-----'
iiWR I--r----~ REliNE
MRD
CE
·2
8
.10
BUS
CLEAR
CLK
RDlW!
BUS
I
9
TPB I------~
BUS
EF 1+-------1
l..-....:rr---..J
~t--------A8
~-I--------A9
~~--~-------~DlM
~~r---~~-----Qm
92CS-33173RI
~--,-~-------~
1/4CD4011
~--------
_______-O(;LK(OUT
RESET OUT
1/4 CD4011
Fig. 3 - Required connection for memory
mepped addfHlllng of the MDU.
92CS-3I.70
Fig. 4 -Interfacing the CDP1855 to an 8085
mlcroproce"or all an I/O device.
340 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1855, CDP1855C
PROGRAMMING EXAMPLE FOR DIVISION
"
MEMORY
LOCATION
0000
0000
0000
0000
0004
0004
0008
0008
OOOC
OOOC
OOOC
OOOF
OOOF
OOOF
OOOF
0011
0011
0014
0016
0016
0016
0019
0019
0019
001C
001C
001C
001F
001F
0021
0021
0021
0021
0024
0024
0027
0027
0028
0000
OP
CODE
68C22000;
68C33OO0;
68C44000;
E067FO;
E464;
E06600;
E365;
E067F2;
E26D60;
E067FO;
E365;
E067F2;
E26D60;
6E;
LINE
NO,
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
0030
0031
0032
0033
0034
0035
0036
0037
0038
ASSEMBLY
LANGUAGE
Program example for a 16 bit by 8 bit divide using 1 CDP1855 MDU
' Gives a 16 bit answer with 8 bit remainder
RLDI R2,2000H
RLDI R3,3000H
RLDI R4,4000H
SEX RO; OUT 7; DC OFOH
SEX R4; OUT 4
, , Answer is stored at 2000 hex
' , Register 2 points to it
, , Dividend is stored at 3000 hex
' Register 3 points to it
Divisor is stored at 4000 hex
' , Register 4 pOints to it
, Write to the control register to use
' clock / 2; 1 MDU; reset sequence
' counter; and no operation
Load the divisor into the X register
SEX RO; OUT 6; DC 0
SEX R3; OUT 5
Load 0 into the Y register
Load the most significant 8 bits of
' , the dividend into the Z register
SEX RO; OUT 7; DC OF2H
, , Do the first divide, also resets the
' , sequence counter
SEX R2; INP 5; IRX
, Read and store the most significant
' 8 bits of the answer at 2000 hex
SEX RO; OUT 7; DC OFOH
, Reset the sequence counter
SEX R3; OUT 5
Load the 8 least significant 8 bits
' of the original dividend into the Z
register
SEX RO; OUT 7; DC OF2H
SEX R2; INP 5; IRX
INP6
Do the second division
' Read and store the least significant
' , 8 bits of the answer at 2001 hex
' , Read and store the remainder at 2002
' , hex
342 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1855, CDP1855C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA
Cl = 100 pF (See Fig. 7)
CHARACTERISTIC-
=-40 to +85°C. VDO ±5% tr. tf= 20nl. VIH =0.7VOO. Vil =0.3 VOO.
VOO
(V)
I
liMITS
COP1855
Min.
Typ.
*I
1 *1
COP1855C
Max.
Min.
-
3.2
UNITS
Typ.
Max.
4
-
Operation Timing
Maximum Clock Frequency+
Maximum Shift Frequency
(1 Device).ll.
Minimum Clock Width
tCLKO
tCLK1
Minimum Clock Period
tClK
Clock to Shift Prop. Delay
tCSH
Minimum C.I. to Shift Setup
tsu
C.O. from Shift Prop. Delay
tPLH
tPHL
Minimum C.I. from Shift Hold
Minimum Register Input Setup
Register after Shift Delay
Minimum Register after Shift Hold
C.O. from C.I. Prop. Delay
Register from C.I. Prop. Delay
tH
tsu
tPLH
tPHL
tH
tPLH
tPHL
tPlH
tPHl
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
3.2
6.4
1.6
3.2
-
-
-
-
-
4
8
2
4
100
50
250
125
200
100
50
25
450
225
50
25
-20
-10
400
200
50
25
100
50
80
40
-
15u
75
312
156
300
150
67
33
600
300
75
40
10
10
600
300
100
50
150
75
120
60
-
-
1.6
2
-
-
-
~
~
-
250
312
200
300
-
50
67
450
600
50
75
-20
10
-
-
-
-
-
-
-
-
-
-
400
600
50
-
-
MHz
ns
1uO
-
-
100
150
-
-
80
120
-
-Maximum limits of minimum characteristics are the values above which all devices function.
*Typical values are for T A = 25° C and nominal voltages.
+Clock frequency and pulse width are given for systems using the internal clock option of the CDP1855. Clock frequency
equals shift frequency for systems not using the internal clock option .
.ll.Shift period for cascading of devices is increased by an amount equal to the C.I. to C.O. Prop. Delayforeach device added.
Fig. 7 - Operation timing diagram.
344 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1855, CDP1855C
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = -40 to +85" C. VDD ±5'Vo tr. tf = 20 n•• VIH = 0.7 VDD. VIL = 0.3 VDD.
CL = 100 pF (See Fig. 8)
CHARACTERISTIC-
LIMITS
CDP1_115
Min.
Minot Typ.Max.
1
VDD
(V)
~...1111~
UNITS
Typ.-
Max.
200
300
Read Cycle
CE to Data Out Active
CE to Data Access
tCA
Address to Data Access
tAA
Data Out Hold after CE
tDOH
Data Out Hold after Read
tDOH
Read to Data Out Active
tRDO
Read to Data Access
tRA
Strobe to Data Access
tSA
Minimum Strobe Width
-
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
tCDO
tsw
200
100
300
150
300
150
150
75
150
75
200
100
200
100
200
100
150
75
50
25
50
25
50
25
-
-
300
150
450
225
450
225
225
115
225
115
300
150
300
150
300
150
225
115
50
-
50
-
300
300
150
150
200
-
450
225
225
300
300
300
-
150
225
200
200
50
-
-
-
-Maximum limits of minimum characteristics are the values above which all devices function.
·Typlcal values are for T A = 25" C and nominal voltages.
CE-------"
~/m----~---------------~'_
~A~
STB _ _ _ _
Et::ENCE COUNTER
I
I
RA¢-2
I-
DOUT
I QJ
ICD0-j
,.
!-
I
4
i
:
I
!
I
1
~"'-;i----""';"!-----,~
- I tSA
_____ vr----~l-----
,-
+-_~..J
\~-I
I
r-tAA-:
"I
- j tDOH~
I
!
-:
I
I
tDOH
*L~-1~-IO-;-:- ' j 1
-I tCA
IRD01
I'
I- :
-:
1
IRA
92CM-31B52
Fig. 9 - Read timing diagram.
450
ns
346 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1856, CDP1856C, CDP1857, CDP1857C
DO~
0=---+---<
Drl
Dr!
001 0'---+---<
001~--~-~~
or2
or2
D02~--+--(
D02 0=---+---<
on
Dr>
003 0=---+---<
00'0=---+---<
CDP1856
CDP1857
Fig. 1 -
Functional diagrams for CDP1856 and CDP1857.
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Vaa)
(All voltage values referenced to Vss terminal)
CDP1856, CDP1857 .....................................................••.................................. -0.5 to +11 V
CDP1856C. CDP1857C ....................•.•....•.............................•......................••••... -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ......................................................................... -0.5 to Vao + 0.5 V
DC INPUT CURRENT. ANY ONE INPUT .....................•.....•........•.........................•......•............ ±10 mA
POWER DISSIPATION PER PACKAGE (Po):
For T. '" -40 to +60' C (PACKAGE TYPE E) ........................................................................... 500 mW
For T. '" +60 to +85'C (PACKAGE TYPE E) ............................................ Derate Linearly at 12 mW/'C to 200 mW
For T. = -55 to +100'C (PACKAGE TYPE D) .......................................................................... 500 mW
For T. +100 to +125'C (PACKAGE TYPE D) ........................................... Derate Linearly at 12 mW/'C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T. = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ............................................... 100 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE D ............................................................................................. -55 to +125'C
PACKAGE TYPE E .............................................................................................. -40 to +B5'C
STORAGE TEMPERATURE RANGE (Tot,) ........................................................................... ~5 to +150'C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max ..................................................... +265'C
348 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1856, CDP1856C, CDP1857, CDP1857C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = -40 to +850 C, Voo
V,H = 0.7 Voo, V,L = 0.3 Voo, 1,., t, = 20 ns, CL = 100 pF
CHARACTERISTIC
Voo
(V)
Propagation Delay Time:
MRD or CS to DO,
tEO
MRD or CS to DB,
tEe
01 to DB,
t,.
DB to DO
t.o
-Typical values are for TA
CS
= 25
0
=± 5%,
LIMITS
CDP1856
CDP1856C
CDP1857C
CDP1857
Typ.Typ.Max.
Max.
5
10
5
10
5
10
5
10
150
75
150
75
100
50
100
50
150
225
125
225
125
150
75
150
75
UNITS
225
-
ns
-
150
225
-
-
100
ns
150
ns
-
100
150
ns
-
-
C and nominal voltages.
-
cs -----'
!....--
MRD*'
"--
-
DI
rilEB
DB
(a)
DB
_i.:.'EB
90%
10%
ENABLE TO OB TIME
~
---I
~
'EO
DO
'ED
90%
1 10%
(b) ENABLE TO DO TIME
\~--
'MRo~
t,~ J
Dr
DB
=======~==~VALID
DATA
.C:'n
.f..-
(b) DI TO DB TIME
*'
POLARITIES ARE REVERSED FOR CDPI857
\'----
::-J.~FJ E
(b) DB TO DO TIME
92CM-28093R2
Fig. 2 - Timing diagrams for CDP1856 or CDP1857 (see footnote).
350 ______________ CMOS Microprocessors, Memories and Peripherals
CDP1858, CDP1858C, CDP1859, CDP1859C
CLOCK
16
Voo
MAO
15
EN'A'Bi:E
14
MA2
13
12
MA3
eEl)
CS2
II
ffi
CS3
10
MAl
CSO
CSI
4
en
eEl
Vss
TOP VIEW
4-Bit Latch and Decoder
Memory Interfaces
Features:
• Provides easy connection of
memory devices to CDP1802
microprocessor
• Non-inverting fully buffered data
transfer
92CS-31953
CDP1858
TERMINAL ASSIGNMENT
RCA-CDP1858, CDP1858C, CDP1859, and CDP1859C are
CMOS 4-bit latch decode circuits designed for use in
CDP1800 series microprocessor systems. These devices
have been specifically designed for use as memory-system
decoders and interface directly with the 1800-series microprocessor multiplexed address bus at maximum clock
frequency.
The CDP1858 and CDP' 859 are functionally identical to the
CDP1858C and CDP1859C, respectively. The CDP1858 and
CDp,1859 have a recommended operating-voltage range of
4 to 10.5 volts, and the CDP1858C and CDP1859C have a
recommended operating-voltage range of 4 to 6.5 volts.
The CDP1858 interfaces the 1800-series microprocessor
address bus and upt032 CDP1822 256 x4 RAM's to provide
a 4K byte RAM system. No additional components are required. The CDP1858 generates the chip selects required
by the CDP1822 RAM. The chip select outputs are a function of the address bits connected to inputs MAO through
MA3.
The MAO-MA3 address bits are latched at the trailing e~
of TPA (generated by the CDP1802). When J:fiIABLE=l (V oo), the CS outputs=O (Vss), and the CE outputs=1, When ENABLE=O, the outputs are enabled and
correspond to the binary decode of the inputs. The NABrrinput can be used for memory system expansion.
The COP1858 is also compatible with non-multiplexed address bus microprocessors. By connecting the CLOCK
input to 1 (Voo), the latches are in the data fOllowing mode
and the decoded outputs can be used in general-purpose
memory-system applications.
The CDP1859 interfaces the 1800-series microprocessor
address bus and up to 32 CDP1821 1024 x 1 RAM's to
provide a 4K byte RAM system. The CDP1859 generates the
chip selects required by the COP1821 RAM. The chip select
outputs are a function of the address bits connected to
inputs MA2 and MA3. The address bits connected to inputs
MAO and MAl are latched by the trailing edge of TPA (generated by the 1800-series microprocessor) to provide the
two additional address lines required by the CDP1821 when
used in a CDP1800 series microprocessor-based system.
When EJil'A'B'CE=1, the CE outputs are 1's; when mABLE=O, and CE outputs are enabled and correfond tE
the binary decode of the MA2 and MA3 inputs. NABL
does not affect the latching or state of outputs A8;Ali, A9, or
A9.
The CDP1858, COP1858C, COP1859, and COP1859C are
supplied in l6-lead, hermetic, dual-in-line side-brazed ceramic packages (0 suffix) and in 16-lead dual-in-line plastiC
packages (E suffix).
voo
CLOCK
MAO
16
15
'El'lJiBl:E'
MAl
14
MA2
13
MA3
AS
4
A8
A§
12
CEO
CEI
A9
7
10
vss
8
9
CE2
eo
TOP VIEW
92C$-319154
CDP1859
TERMINAL ASSIGNMENT
File Number
1127
352 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1858, CDP1858C, CDP1859, CDP1859C
=
OPERATING CONDITIONS at TA
Full Package-Temperature Range.
For maximum reliability, operating conditions should be selected so that operation is always
within the following ranges:
LIMITS
CDP1858
CDP1859
Min.
Max.
CDP1858C
CDP1859C
Min.
Max.
4
Vss
10.5
Voo
4
Vss
CHARACTERISTIC
Supply-Voltage Range
Recommended Input Voltage Range
UNITS
6.5
Voo
V
V
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, Except as noted
CONDITIONS
CHARACTERISTIC
Vo
(V)
V,N
(V)
Voo
(V)
-
LIMITS
CDP1858C
CDP1858
CDP1859C
CDP1859
Typ.·
Typ.·
Max.
Min.
Max.
Min.
Quiescent Device
Current,
-
0,5
0,10
5
10
-
0.1
1
10
100
-
100
-
-
Output Low Drive
(Sink) Current,
0.4
0.5
0,5
0,10
5
10
1.6
2.6
3.2
5.2
-
1.6
3.2
10L
-
-
OutpCJt High Drive
(Source Current),
4.6
9.5
0,5
0,10
5
10
-1.15
-2.6
-2.3
-5.2
-
·-1.15
-2.3
IOH
-
-
5
10
5
10
-
0
0
5
10
0.1
0.1
0
0.1
-
0,5
0,10
0,5
0,10
-
-
-
-
4.9
5
-
-
5
10
5
10
-
3.5
7
-
1.5
3
V,H
0.5,4.5
0.5,9.5
0.5,4.5
0.5,9.5
Any
Input
0,5
0,10
5
10
-
10--
liN
10
±1
±2
-
0,5
0,10
5
10
-
-
50
150
100
300
-
-
-
-
-
5
7.5
-
-
-
-
10
15
Output Voltagee
Low-Level
Output Voltagee
High-Level
Input Low
Voltage,
Input High
Voltage,
Input Leakage
Current,
VOL
VOH
V,L
Operating Current,
1001.
Input Capacitance,
C 'N
Output Capacitance,
COUT
=
-
-
4.9
9.9
-
-
-
·Typlcal values are for TA
25°C and nominal voltage.
• IOL = IOH == 1 /lA .
• Measured in a CDP1802 or CDP1804 system at 3.2 MHz with open outputs.
3.5
5
-
50
-
UNITS
/lA
mA
mA
-
V
1.5
-
V
10--
±1
50
100
-
-
/lA
-
5
7.5
pF
-
-
-
pF
/lA
354 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1858, CDP1858C, CDP1859, CDP1859C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, Voo
V'H = 0.7 Voo. V'l = 0.3 Voo, Cl = 100 pF, See Fig. 4.
LIMITS
CDP1859C
CDP1859
Max.
Typ.
Min.
Typ.
Max.
Min.
Voo
CHARACTERISTIC
(V)
Minimum Setup Time, Memory
Address to Clock, tMACl
Minimum Hold Time, Memory
Address After Clock, tClMA
Minimum Clock Pulse
Width, tClCl
Propagation Delay Times:
5
10
5
10
5
10
-
5
10
5
10
5
10
5
10
5
10
-
Clock to Address, tClA
Clock to
CHIP ENABLE, tClCE
Memory Address to
Address, tMAA
Memory Address to
CHIP ENABLE, tMACE
ENABLE to
CHIP ENABLE, tECE
± 5%, t" tf = 20 ns,
-
-
-
25
10
0
0
50
25
40
25
25
10
75
40
125
65
175
90
100
50
150
75
125
65
200
100
275
140
150
75
225
125
200
100
-
25
-
-
-
0
25
-
-
50
75
-
-
125
200
-
-
-
-
175
-
150
-
-
-
-
125
200
MAO- MA3
r-
150
-
-
II
'MACL+-r'CLMA
X.
I - tCLA I-A8,AS,A9,lI:9
CEO-CE3
--
t CLcE
- -- -- ... -
x.I
f-
tMAA
tMMA
tMACE
t MACE
f-
(0) MEMORY ADDRESS TO OUTPUT TIMING
(b) CHIP ENABLE TO
CFIl1' Emm:E PROP DELAY
92CM-31gee
Fig. 4 -
CDP1859 timing diagram.
ns
ns
-
-
-
ns
275
100
Typical values are for T A = 25° C and nominal voltages.
Maximum limits of minimum characteristics are the values above which all devices function.
CLOCK
40
UNITS
225
-
ns
356 ______________ CMOS Microprocessors, Memories and Peripherals
CDP1858, CDP1858C, CDP1859, CDP1859C
~~
MAO-7
MRO
CPU
MWFig
MRli
COPl802
B~1
MAO-7
~
MWRg
p
MRii ,,
~
CSi
lIoMAO-7
C
MWR
,
....-CSl
-
2
2
CS2
BUS 0-3
,,
p
MRii
cs;
•
-&,
!iml ,
p
I-
0
~
,
2
2
CS2
'--------
MAO-7
MWR c
MWR c
L...to MAO ~
r-- CSi
,
2
2
CS2
~
BUS 4-7
•
MAO-7
MRD ~
r--
2
2
C52
em
BUSO-3
k
f----cs;
~
,-
2
2
CS2
0
MWR c
L......e
~
~
MWRg
k
MAO-7
0
~MRo~
2
2
CS2
•
~
~
r--
MAN
-r-- r -
2
2
CS2
CSi
~hTFA
,,
p
L......-.!
mm
!--------tCST
0
,~
2
2
CS2
L--
L.~ilCs~
C CS
0
P
J:"
CS2
CS'
-'
mil---
EN ,
,•
m
en
~
L--
92C~-29060RI
Fig. 5 - 4K byte RAM system using the CDP1858 and CDP1822.
MAO 7
8
TPA
1I.
r---- CLOCK 5
,,
p
CPU
CDPI802
5
DB
S
OBO_'~ ~
CTt->'
b
DBO-7
or
,
~ DO~--~--~4---------~--------------~--------------~
6
~
080-4
---=~
,
m~------~~--------------------------------------------~
I
ij
oo~--------~----------------------------------------------~
'----
Fig. 6 - 4K byte RAM system using the CDP1859, CDP1856, and CDP1821.
358 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1863, CDP1863C
MAXIMUM RATINGS. Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Vee):
(Voltage referenced to V•• Terminal)
CDPI863 .................................................................... , ............ , .................. -0.5 to + 11 V
CDP1863C .............................................. , ....................... " ............................ -0.5 to +7 V
I""PUT VOLTAGE RANGE, ALL INPUTS .............................................. " ....................... -0.5 to Vee +0.5 V
DC INPUT CURRENT. ANY ONE INPUT ............................................. " ................................. ± 10 mA
POWER DISSIPATION PER PACKAGE (Pe):
For TA = -40 to +60°C (PACKAGE TYPE E) ......................................................................... 500
For TA = +60 to +85°C (PACKAGE TYPE E) .......................................... Derate Linearly at 12 mW/oC to 200
For TA = -55 to +100°C (PACKAGE TYPE D) ........................................................................ 500
For TA = + 100 to + 125°C (PACKAGE TYPE D) ....................................... Derate Linearly at 12 mW/oC to 200
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
mW
mW
mW
mW
For TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ............................................... 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE 0 ........................................................................................... -55 to + 125°C
pACKAGE TYPE E ............................................................................................ -40 to +85°C
STORAGE TEMPERATURE RANGE (T,.. ) ....................................................................... -65 to +150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16
± 1/32 inch
(1.59
± 0.79 mm)
from case for 10 s max.................................................. +265°C
STATIC ELECTRICAL CHARACTERISTICS at T. = -40 to +85°C, except as noted
CHARACTERISTIC
Vo
(V)
-
Quiescent Device
Current,
Output Low Drive
(Sink) Current,
Output High Drive
(Source) Current,
Output Voltage
Low-Level,
Output Voltage
High-Level,
Input Low Voltage,
-
5
-
50
250
-
500
-
-
50
250
-
1.6
2.2
-
-
-1
-1.6
-
-
-
0.4
0,5
1.6
250
2.2
IOL
0.4
4.5
0,10
0,5
10
5
3
-1
3.6
-1.6
IOH
9.5
0,10
-3
-3.6
-
0,5
-
0,10
0.05
0.05
-
0.05
-
°0
0
VOL
10
5
10
-
-
-
0,5
0,10
4.95
9.95
5
-
5
10
-
-
V,L
0.5,4.5
0.5,9.5
1.5
3
-
3.5
7
3.5
-
Any
0,5
5
10
5
-
V,H
0.5,4.5
0.5,9.5
-
5
10
5
10
4.95
VOH
-
Input
10
5
10
-
Input Leakage
Current
-
MIN.
LIMIT'S
CDP1863
CDP1863C
TYP.·
TYP.·
MAX.
MIN.
MAX.
10
5
IL
Input High Voltage,
Current,
Operating
CONDITIONS
V,N
. Voo
(V)
(V)
t
-
0,10
0,5
1001:1:
-
0,10
liN
-
'Typical values are for T. = 25° C
tMeasured with CLK1=2 MHz, total divide rate of 8, C L = 50 pF.
:j:Measured with CLK1=4 MHz, total divide rate of 8, CL = 50 pF.
-
-
±0.1
±1
±0.1
0.67
±1
1
3.5
4.5
-
UNITS
pA
mA
mA
V
1.5
-
±0.1
±1
-
-
0.67
1
-
-
V
pA
mA
360 _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1863, CDP1863C
SIGNAL DESCRIPTIONS (Cont'd.)
010-017
Data inputs for programming the divide rate of the device.
The divide rates programmed into the device are inversely
proportional to the output frequencies generated. For example, programming the device with 00,. causes the programmable up-counter to divide by one, providing the maximum output frequency for any given input clock.
Programming an FF,. results in the maximum divide rate
and the minimum output frequency. To determine the frequency generated by a given programmed divide rate,
divide the input clock frequency by the decimal equivalent
of the programmed divide rate plus one, times the fixed
predivide which is 8 for CLK1 or 16 or CLK2:
Input Clock Frequency/[(Programmed Divide Rate + 1)'0
(Fixed Predivide)]
STR
Positive pulse used to latch data at the eight inputs into the
device. This pulse is gated with CLK1 to form the internal
latch clock. When CLK1 is the input clock, the STR input
must be positive during the high-to-Iow transition of CLK1.
When CLK2 is the input clock, CLK1 must be tied to Vee so
that the STR Input produces the latch clock.
RESET
A low on' the ~ input resets all the stages of the predividers and the programmable up-counter and sets an initial
divide rate into the latch. This Is to provide a standard initial
divide rate althe momentthe system begins running. Ahigh
on ~ enables the counter to run freely and allows
programming a new divide rate. The initial state of the
up-counter is a divide-by-54 resulting in a total divide rate of
432, after 1024 clock pulses when using CLK1, and 864,
after 2048 clock pulses when using CLK2.
Voo
Positive supply voltage.
Vss
Negative supply voltage; ground.
APPLICATION
The programmable frequency generator is directly compat. As an example of programming the frequency generator,
ible with the CDP1802 CMOS microprocessor. In Fig. 1 a
assume a 64 instruction is selected as the output code used
simple CDP1802 system using this device is shown. TPB
to program the device. Let machine register E point to the
may be used as the input clock. At typical CDP1802 system
data to be latched. N2 is the only N bit pulsed by a 64
clock frequencies, using TPB as an input to CLK1 results in
instruction and may befed directly to the STR input if TPB is
nearly every possible output of the device being in the audio
fed to CLK1. An EE instruction makes RE the X register.
Following this with a 64 instruction puts the data pOinted to
range. The Q output of the CDP1802 may be used as the
by RE onto the data bus and raises the N2 bit. TPB, which is
OUTPUT ENABLE (OE) of the device. The eight data inputs
within the duration of the N2 pulse, causes the internal latch
are connected to the bidirectional data bus which allows the
clock to terminate before the data bus loses validity. The
system memory to provide divide rate data to the device. A
latch in the device continually passes the data Inputs
single N bit or some decoded output of all the N bits may be
through to the outputs of the latch as long as CLK1 and STR
used as the STR input to latch data into the device. This
involves designating some output instruction of the
are high. Once CLK1 goes low, data is locked in. A 7B
CDP1802 for providing the STR. The output instruction
instruction then sets the Q line high which, if connected to
OE, allows the OUT to toggle at the desired rate.
places the data pointed to bytheX register on the bus, while
simultaneously pulsing the appropriate N bits. By the interCode:
nal gating of TPB and STR, when TPB is fed into CLK1, the
EE RE is the X register
resulting latch clock terminates while the data is still valid
64 M(E)-BUS N2 pulsed high
on the 8-bit bus. If TPB is fed into CLK2, it is necessary to
7B Q turned on
provide an external AND gate for the appropriate N bits and
TPB, to preserve this timing feature. The same signal that
~he CLEAR input of the CDP1802 may be used as the
RESET signal to this device.
362 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1863, CDP1863C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA
= -40 to +85°C,
Voo
± 5%, CL = 50 pF
LIMITS
CHARACTERISTIC
Voo
(V)
Clock 1 Frequency
tCLK'
Clock 2 Frequency
tCLK2
Clock 1 Width
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
t,
Clock 2 Width
to
Clock 1 to Clockout
tcu
Clock 2 to Clockout
tCL2
Reset to Clockout
-tCLR
OE Delay to Clockout
tOEO
ReSet Pulse Width
-tRS
Data Setup to Clock 1
tos
Data Hold to Clock 1
tOH
Da ta Setu p to Strobe
toss
Data Hold to Strobe
tOHS
"Typical values are for TA
MIN.
CDP1863
TYP."
-
-
MAX.
MIN.
2
5
4
8
-
-
-
250
100
125
70
-
-
250
-
-
125
1
0.3
0.9
0.3
260
130
110
40
120
60
0
0
75
50
0
0
50
40
1.7
0.5
1.2
0.5
375
170
150
70
160
90
20
10
100
80
30
30
100
60
-
-
-
-
CDP1863C
TYP."
MAX.
-
-
2
MHz
4
-
MHz
,.,S
-
1
1.7
-
-
-
-
0.9
1.2
-
-
-
260
375
-
-
110
150
-
-
120
160
-
-
-
0
20
-
-
-
-
75
100
-
-
-
-
0
30
-
-
50
100
-
-
ns
ns
,.,S
ns
ns
ns
ns
ns
ns
ns
= 25°C and nominal voltages.
r--'elK I - - - - - 1..~1
eLi<
I -------;
'os ..
I
STR
!--'DH-
I
:--'DSS~DHS"
DATA
~ ~.
elK 2
'2
-~
)K
OUT
~ -telR
----l 'RS 1--
- 'eu.!::,
-
r''OED
r--
OE
92CM-3503~
Fig. 6 -
Timing diagram for the CDP1863 and CDP1863C.
UNITS
364 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1866, CDP1867, CDP1868
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Voo)
(Voltage referenced to Vss Terminal)
CDP1866, CDP1867, CDP1868 ", ............................................................................. -0.5 to 11 V
CDP1866C, CDP1867C, CDP1868C ............................................................................. -0.5 to 7 V
INPUT VOLTAGE RANGE, ALL INPUTS ........................................................................ -0.5 to Voo + 0.5 V
DC INPUT CURRENT, ANY ONE INPUT ........................................... , ................................... , .. ±10 mA
POWER DISSIPATION PER PACKAGE (Po):
For TA
= -40
For TA
= +60 to +85°C (PACKAGE TYPE
For TA
= -55
For TA
= +100 to +125°C
to +60° C (PACKAGE TYPE E) ........................................................................... 500 mW
E) ................................. , .......... Derate Linearly at 12 mW/oC to 200 mW
to +100°C (PACKAGE TYPE D) .......................................................................... 500 mW
(PACKAGE TYPE D) ......................................... Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ................................................ 40 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE D ............................................................................................ -55 to +125°C
PACKAGE TYPE E ............................................................................................ -40 to + 85° C
STORAGE TEMPERATURE RANGE (T"g) ........................................................................ ,. -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max ............................................... , ..... +265°C
MAO
I
7 AS
AIO
CLOCK I
CE2 I
CE3 I
CE4~--~~>-----~
92C$-30970R2
Fig. 2 - Functional diagram for the CDP1866.
MAO
Fig. 3 - Functional diagram for the CDP1867.
I
92CS-30969
Fig. 4 - Functional diagram for the CDP1868.
366 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1866, CDP1867, CDP1868
TRUTH TABLES FOR THE CDP1866 AND CDP1868
OUTPUTS
INPUTS
MRD
CS1
CS2
CS3
0
I
0
I
I
I
I
I
I
I
I
I
I
X
X
X
X
X
I
I
I
I
or
MWR
CE1
CE2
CE3
ClK
MA2
MA3
CSO
0
0
0'
0
0
X
X
X
I
I
I
I
I
0
0
0
0
0
X
0
0
0
0
0
I
I
I
I
0
0
0
I
I
X
X
X
0
X
X
X
X
X
X
X
X
X
I
X
X
0
X
I
X
X
I
0
I
0'
I
I
PREVIOUS STATE
I
I
I
I
I
I
I
I
0
I
I
I
I
'In the CDP1868, CS2 will be valid (CS2=O) only if MRW is low, regardless of the polarity of MRD,
ClK
I
I
I
I
0
INPUTS
MAO
OUTPUTS
A8
A9
MA1
0
0
0
I
I
X
0
0
0
I
X
MWR
or
0
0
0
I
I
0
I
I
I
I
0
I
CDPl800
SERIES
CPU
M'W'R
TPA
COP 1866
eLK MWR
MRO C
0
P
MAD
I
MAl B
6
MA2 6
MA3
CSo
eEl
eE2
eo
MRD
MWR
0
I
I
0
I
I
PREVIOUS STATE
I
-MRD
0
X Y
A8
A9
ADDRESS BUS 0-7
92CM-30966RI
Fig, 5 - 4096-word by 8-bit random-access memory system using the CDP1866,
368 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1866, CDP1867, CDP1868
DYNAMIC ELECTRICAL CHARACTERISTICS at T.
V'H = 0.7 Voo. V'L = 0.3 Voo , CL = 100 pF. See Fig. 8
= -40 to +85
Voo
(V)
CHARACTERISTIC
Minimum Setup Time,
Memory Address to CLOCK,
Minimum Hold Time,
Memory Address After CLOCK,
tMACL
tCLMA
tCLCL
Minimum CLOCK Pulse Width
Propagation Delay Times:
Chip Enable to
Chip Select,
MRD or MRW to
Chip Select,
CLOCK to
Chip Select,
CLOCK to Address,
tCECS
tMCS
tClCS
telA
Memory Address to
Chip Select,
Memory Address to
Address,
tMACS
tMAA
0
C, Voo
± 5%,
= 20 ns,
t" tf
LIMITS
CDP1866
CDP1866C
Typ .• Max.ll.
Min.
Typ .• Max.ll.
Min.
5
10
5
10
5
10
-
50
25
50
25
50
25
75
40
75
40
75
40
-
50
5
10
5
10
5
10
5
10
5
10
5
10
-
150
75
125
65
175
90
125
65
150
75
8u
40
225
125
200
125
275
150
200
125
225
125
-
150
-
-
-
75
-
-
50
75
-
-
50
75
-
225
-
-
125
200
-
275
175
-
-
125
-
200
-
-
225
150
-
1~"
60
-
-
tsU
-
l~"
-
-
-Typical values are for T. = 25 0 C.
"'Maximum limits of minimum characteristics are the values above which all devices function.
CEI,m,m
________
-J~~----------~~~L~IO~CH~IP~EN~A~B~L~ES~-----------'¥~-------I teEes
:teEes
I----------<
I
I
.--J
I
\
I
101 CHIP ENABLE TO CHIP SELECT PROP. DELAY
MRD
CSQ,
________~t
~
,
,
CST. CS2, CS3
\~----------
+ MRW*
:tMCS
~7
\~~~==~~------~
(b) MRD+MRW TO CHIP SELECT PROP. DELAY
MAO - MA3
'I,.'---~:I-:----~--
=:=¥
:
tMACL
:
l:
tCLMA
~t+--
CLOCK
r-1
~~l
ICLCL---t------', ICLCS'I
c SO, CST. C$2, CS3
I
:
,IMACS
'IMACS
: I MAA
' I MAA
L
, * - : ----------------+-i:-=-"1
---..*-:~x:::::
1-:
I
I'
AB-A9
*
I
:
I I
SEE TRUTH TABLE FOR MRO
I CLA
r------1
'I
L=::::F
It I MEMORY ADDRESS SETUP
a MRW
~ND
HOLD TIME
Fig. 8 - CDP1866 timing waveforms.
*-
~
92CM-31868
UNITS
x:::::
ns
370 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1866, CDP1867, CDP1868
DYNAMIC ELECTRICAL CHARACTERISTICS at T. = -40 to +85°C, Vee ± 5%, t" tl = 20 ns,
VIH
0.7 Veo. Vll
0.3 Vee, Cl
100 pF. See Fig. 10
=
=
=
Vee
(V)
CHARACTERISTIC
Minimum Setup Times:
Chip Enable to
CLOCK,
Memory Address
·to CLOCK,
Minimum Hold Times:
Chip Enable After
CLOCK,
Memory Address After
CLOCK,
Minimum CLOCK Pulse Width,
tCECl
tMACl
tClCE
tClMA
tClCl
Propagation Delay Times:
CLOCK to
Chip Select,
Chip Enable to
Chip Select,
Chip Enable 3 to
Chip Select,
MRD or MRW to
Chip Select,
CLOCK to Address,
tClCS
tCECS
tC3CS
tMCS
tClA
Memory Address to
Chip Select,
Memory Address to
Address,
tMACS
tMAA
LIMITS
CDP1868
CDP1868C
Typ •• Max •./\.
Typ •• Max •./\. Min.
Min.
5
10
5
10
-
5
10
5
10
5
10
-
5
10
5
10
5
10
5
10
5
10
5
10
5
10
-
-
-
-
-
-
-
-
-
50
25
50
25
75
40
75
40
-
50
25
50
25
50
25
175
90
150
75
150
75
125
65
125
65
125
65
80
40
-
50
75
-
-
50
75
-
-
-
75
40
75
40
75
40
-
50
75
-so-
75
-
-
-
275
150
225
125
225
125
200
100
200
100
200
100
120
60
-
175
275
-
-
-
150
225
-
-
-
-
-
-
50
75
~
-
-
125
200
-
-
125
200
125
-
-so-
-
ns
-
foO
UNITS
~
-
T2u-
-
oTypical values are for T. = 25° C and nominal.
./\.Maximum limits of minimum characteristics are the values above which all devices function.
----I(
,
MRO+MRW*-'t'---_ _
~
liMeS,
m-ffi----~'~1(==================~'==:I~---.AO-."~
::
¥
~
..
' ",I.",,;,....
1 .......
: telMA
CLOCK~
(AICEI.mTO~PROPDELAY
en
ESO'CS4
\
-.II
~~.
==
(
t-IC3CS
{
,
--<
itcscs
I
-:-~s~
:
c=::::::
i
1-ICLA~
i
_____*==::
Ie) MEMORY ADDRESS SETUP AND HOLD TIME
lei et!rOCHIP SElECTPROPOELAY
*SEE TRUTH TABLE FDA MRO+MWR
t9} WILL BE VALID (Bl!·OI Of4LY IF
SIGNAL POLARITY.
mrw.s LOW
REGARDLESS Of
Fig. 10 - CDP1868 timing waveforms.
ii1m
: :
:
!-IMACS-j
I----.:-tMACS
*==:t='Jc:
,
I---tMAA-t
!
t-----t-tMACS
C=*=::
372 ______________ CMOS Microprocessors, Memories and Peripherals
CDP1869C, CDP1870C, CDP1876C
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPL Y-VOL TAGE RANGE, (Voo)
Voltage referenced to Va. Terminal)
CDPI869C, CDPI870C, CDPI876C"" ............................................................ ·············· ... -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS .......................................................................... -0.5 to Voo +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ...............................................................................••. ± 10 mA
POWER DISSIPATION PER PACKAGE (Po):
For T A=-40 to +60·C (PACKAGE TYPE E) ............................ , ..................................... '" ........... 500 mW
For T A=+60 to +85· C (PACKAGE TYPE E) .................................................. Derate Linearly at 12 mW/· C to 200 mW
For TA=-55 to +100·C (PACKAGE TYPE D) ............................................................................. ·· 500 mW
ForTA="00 to 125·C (PACKAGE TYPE D) ........................................ ·......... Derate Linearly at 12 mW/·C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For TA=FULL PACKAGE-TEMPERATURE RANGE (All Package Types) .................................................... 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE 0 ............................................................................................... -55 to +125·C
PACKAGE TYPE E ................................................................................................ -40 to +85· C
STORAGE TEMPERATURE RANGE (T...) ............................................................................ -65 to ·'50·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
. .................................................... ·265·C
CPU C LK (2835 MHz NTS C 2.813 MHz PAL
PREDISPLAY
DISPLAY
~
H SYNC
N73
I
CMSEL
CMWR
Wl'
CMAO
CLOCK
TIl'T7
m
CPU
CDPJR04A
MWR
MEMORY ADDRESS
TPA
CDPI869
ADDRESS
AND SOUND
GENERATOR
RAM
CMAI
OR ROM
(21MWS5114
CMA2
OR
~£~Al _________ 1
CDPI834
IK x8
~MIO
CHARACTER
--~ CS
~
MEMORY
"*"
NO
CDPI802A,
COPI802B,
COPIB05A,
CDPI806A
AND
PROGRAM
MEMORY
Ni
PMAO-9
N2
mm
PMWR
TPB
I
RAM
( 21
MWS5114
IKX8
PAGE
MEMORY
~
cs
~
!
t[
~!
.,20pF
XTAL
CDPI870
COLOR
VIDEO
X'i'AL
GEN
XTAL
CCBO-I
XTAL
~
PCB
CHROM
~
WE
-----t
LUM
~,22MI f 5.67
(DOT)
"
MHz NTSC
~,22M
t
5.6~,!VZ PAL
",
20.F.,
(CHROMI -"
'15909 MHz NTSC
8·86 7~~6 MHz PAL
. ,-n5-40pF
SYNC
nl.~ .j'LEVEL
10V
n.~rK
10K
I
T
VIDEO
PMSEL
mrn
1
sJlcVlcfN6~
(21 CDPI856
'y
120nF
TO
MO~
MRD
TPB
~~ENODER
CDPI871
I
SOUND
i§lBIl
=0
---
ANTENNA
8 BIT BIDIRECTIONAL DATA BUS
~MOD~[A1OR
AMPLIFIER
KEYBOARD
A
92CL-34549
Fig. l(a) - System diagram using CDPI869C and CDP1870C (Composite Outputs).
See Fig. l(b) using CDP1876C (RGB Bond Option Outputs).
SPEAKER
374 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1869C, CDP1870C, CDP1876C
OPERATION
The CPU is clock independent of the VIS and is not involved
in screen refresh, although a CPU clock outPl,lt (V, DOT
rate) is provided. Atthis clock rate 787 instructions (1080for
PAL) can be executed during non-display time. ~
DISPLAY provides synchronization between the CPU and
the VIS. Various system configurations for the CDP1869C/
CDP1870C VIS are easiy implemented due to:
PAGE MEMORY
• 20 Characters x 12 LinesRequires 240 Bytes of RAM
• 40 Characters x 24 LinesRequires 960 Bytes of RAM
Character Memory-Can be RAM or ROM
• 32 Different (or any Combination
of) Characters-Requires 256
Bytes (NTSC)
• 64 Different CharactersRequires 512 Bytes (NTSC)
• 128 Different CharactersRequires 1024 Bytes (NTSC)
• 256 Different CharactersRequires 2048 Bytes (NTSC)
Character memory requirements for PAL are the same as
NTSC in most alphanumeric applications, but are 12.5%
higherforgraphics applications due to the larger character
matrix (6x9) used for PAL.
Color
Color information may be stored in the two extra bits in
each character byte (characters are only six dots wide),
providing a choice of up to four colors for each character.
With 128 different characters, only seven bits are required in
the page memory and the eighth bit expands the choice of
colors up to eight.
Bit Map Operation
The VIS may be used to display data in a bit-map format,
offering a high resolution display (up to 46,080 pixels) with
up to 7,680 color blocks (8 colors). In this mode, the
character memory addresses and the page memory addresses are used to address a single bit-map memory,
instead of separate PAGE and CHARACTER memories. X-Y
coordinates are located by implementing the appropriate
software.
RGB Bond-Out Option (CDP1876C)- The CDP1870C may
be ordered with an alternate pin-out to provide direct drive
to the internal TV chassis red, green, and blue amplifiers.
For the CDP1876C, the LUM, PAL CHROM, and NTSC
CHROM outputs become the RED, BLUE, and GREEN
outputs, respectively.
In the RGB mode of operation, the RF, IF, and color
demodulator circuits of the TV chassis are bypassed and
the composite sync, video, and color information are
supplied directly to the appropriate chassis sections. Since
no color subcarrier is used, the CHROM crystal is not
needed, although the XTAL CHROM input must be term
inated (Fig. 1(b». The CDP1876C, RGB Bond-Out option,
offers higher color resolution and simpler interfacing than
the CDP1870C composite interface systems when used
with direct internal TV chassis systems.
CPUCLK
Graphics and Motion
Graphics and motion may be accomplished with two basic
techniques. The first is by character selection. In this
approach the desired graphics and motion symbols are
stored in ROM or RAM. In a system where the character
memory is all ROM, all the possible required positions
within a character space are stored in the ROM. Graphics
are accomplished by selecting the appropriate graphic character for each screen position. If the character memory is
RAM then not all combinations need be stored in the
character memory since they can be modified as required
during operation. Motion in increments as small as one
character space are possible.
A second technique may be used for more sophisticated
motion, in which it is desired to move the displayed object in
increments smaller than a normal character space. In this
technique the object is moved within a character space
using a bit-map approach, with object stored in the RAM
character memory. The object is moved by rewriting the
dots of the character space matrix, thereby continuously
repositioning the object within its character space. As the
object reaches the "edge" of its character space, that
character space is moved and the object is repositioned.
For example, if the object reaches the left edge of the
character space, then that character space is moved to the
left via the page memory and the object is rewritten on the
right side of the character space.
Thus, the object moves smoothly across the screen one
pixel at a time. Objects larger than one character space may
also be moved using a similar technique.
REDf-:===j
BLUE IGREEN
TPB
SOUND
92CS-32699
Fig. l(b) - System diagram (same as that shown in Fig. l(a) using
CDP1876C (RGB Bond-Out Option).
CDP1869C - Address and Sound Generator-This circuit
formats and controls sound, page-memory addressing, and
character-memory addressing. This is accomplished by
software instructions, data from the CPU, and hardware
interaction with the CDP1870C timing signals.
376 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1869C, CDP1870C, CDP1876C
OPERATION (Cont'd)
page-memory, rather than a random location, as in
address space in the SINGLE-PAGE MODE or in the
MODE 3 (above). Reading and writing to the characterentire 2048-byte address space in the DOUBLEmemory remains the same as in MODE 3.
PAGE MODE.
When the CMEM ACCESS MODE bit is set high, the
address inputs (MAO/8-MA7/1S) from the CPU that are
present during the OUT 5 Instruction are latched in the
page-memory address register via the internal MAOMA10 bus and are multiplexed to the page-memory
outputs (PMAO-PMA10), during non-display time. The
data in the page-memory address register, which
remains latched until an OUT 6 Instruction is executed
or until the CMEM ACCESS MODE bit is reset, provides
a stable address to the page memory, which essentially
reduces it to a single location. This location is read from
or written to by selecting the page-memory at address
space F800wFFFF'6, with the data supplied over the
CPU 8-bit data bus. (The actual location within F800w
FFFF,6 is unimportant since the page-memory address
is already latched.) The OUT 6 Instruction is not
required in this mode.
The page-memory data outputs (PMDO-PMD7) provide
the character-memory "Column" addresses, which
select a particular character. Since the page-memory
address location is latched, the address inputs (MAO/8MA7/1S) from the CPU are available to access the
character-memory via the internal MAO-3 bus, which is
multiplexed to the character-memory outputs (CMAOCMA3) during non-display time. The CMAO-CMA3
outputs provide the character-memory "Row" addresses, which select a particular line of dots within a
character. The character-memory is selected at address
space F400 w F7FF,6. Although 1024 bytes of address
space is decoded, only 8 memory locations (1610cations
in the 16-LlNE HI-RES mode) are required and the
character-memory addressing will wrap (repeat) for
the rest of the 1 K address space. The CMWR output,
which is connected to the WRITE input of the charactermemory, and the CMSEL output, which is connected to
the CDP1870C CMSEL input, are also enabled at this
time. The data to be read from or written to the
character-memory is multiplexed through the' CDP1870C internal8-bit data bus via the BUSO-BUS7 inputs
from the CPU.
This mode of operation is useful to initially load the
character-set into the RAM character-memory since
fewer program instructions are required than with the
following Character-Memory Access Mode.
4. CHARACTER-MEMORY ACCESS MODE (Without
Display Disturb)-This mode is used to read or write
data in the character-memory, without disturbing the
current display data. Operation is the same as the
Character-Memory Access Mode (with Display Disturb),
with the following exceptions.
After the CMEM ACCESS MODE bit is set high, the
OUT 6 Instruction is used to load the page-memory
address register with the address input (MAO/8-MA7/15)
from the CPU via the internal MAO-MA 10 bus. These 11
data bits (PMAO-PMA 10) are multi plexed via the internal
MAO-MA 1O/PRAO-PRA 10 bus to the page-memory
outputs (PMAO-PMA10), during non-display time. The
address remains latched until a new OUT 6 Instruction
is executed, to latch new data, or until the CMEM
ACCESS MODE bit is reset.
This mode provides a means to select a page-memory
location that is not part of the current display or a
location that is outside of the display window in the
In both MODE 3 and MODE 4, the character-memory
access mode is disabled by programming the CMEM
ACCESS MODE bit low (reset), using the OUT Sinstruction.
When accessing the page-memory, if the DOUBLE-PAGE
bit is not set (low), PMA 10 is not used and does not have to
be programmed. When accessing the character-memory,
during double-page operation (DOUBLE-PAGE bit set
high), CMA3 is not used and does not have to be
programmed.
OUT 7 Instructlon-This instruction uses 9 data bits to load
the home-address register bits (HMA2-HMA10) via the
internal MA2-MA 10 bus. The home-address register outputs
(HMA2-HMA10) are transferred to the refresh-address
counter at the end of each display frame. The home address
determines which row of characters from the page-memory
is used to start the display at the top left-hand corner of the
screen. In the FULL RES HaRZ MODE (CDP1870), the
home address must be an even multiple of 40. In the HALF
RES HaRZ MODE (CDP1870C), the home address must be
an even multiple of 20. Therefore, the HMAOand HMA1 bits
are automatically set low internally and do not have to be
programmed.
The OUT 7 Instruction is used to define a display window
which can be moved through multiple pages of display RAM
in various roll and scroll operations. As shown in Table 8,
the total characters displayed per frame can be less than the
maximum display page-memory size. TheOUT 7 Instruction
is used to display the remaining page-memory up to the
maximum display page-memory size using a scroll technique.
For example, using line 4 in Table 8,480 characters will be
displayed as 24 rows of 20 characters. However, the
maximum display page-memory size is 960. If the home
address was initially set to zero, the last row of characters
on the screen will begin at page-memory location 460. To
display the next row of characters in the remaining 480
locations of page memory, an OUT 7 Instruction is executed
with the home address set at 20(14,6). The last row of
characters now displayed will begin at location 480, the
start of the second 480 locations of page-memory. This
sequence can be continued with successive multiples of 20
loaded into the home-address register up to the maximum
display pa'ge-memory size minus 20 (940). The display
window appears to scroll through the page-memory with
old data shifted off the top of the screen, but retained in
page-memory, as new data is presented at the bottom of the
screen. During this sequence when the final page-memory
address count (as determined by the maximum display
page-memory size) is reached, prior to the end of the
display window, zero is loaded into the refresh address
counter and the next row of characters displayed will be the
first row in page-memory. Thus, the display will appear to
have rolled around from the beginning of the page-memory
to the bottom of the screen.
The roll operation is automatic when the final page-memory
address count is reached prior to the end of the display
window. The scroll operation occurs when the OUT 7
Instruction is executed, but is automatic in that the display
window data does not have to be rewritten in the pagememory as the display window changes. The home-address
modes in Table 8 indicate which operations (scroll, roll) are
possible with each format combination.
378 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1869C, CDP1870C, CDP1876C
OPERATION (Cont'd)
MAple
WHITENOISE
GEN.
5
MAO-MAI5
MA\/l5
TONE
GEN.
CMWR
PMEMI
CMEM
DECODE
LOGIC
CMSEL
PMWR
HSvNC
iiiSPi:AY
PMSEL
@ CM,AO
I
,
I§) CMA2
CHARACTERMEMORY
ADDRESS
MUX
NO
25 CMA3/PMAIO
NI
N2
PAGEMEMORY
ADDRESS
MUX
VDD--@
VSS--@
Fig. 2 - CDP1B69C block diagram.
DOT
XTAL Xi'AC
----~'I"
PiiEriiiPi:AY
DISFLAY
HSYNC
AiiDsi'B
CPUCLK
L----.c29lg COMPSYNc
MRii
LUM IRED)'
TPB
NTSC CHROM IGREEN)'
Ni"3
PAL CHROM (BLUE)'
PAL/mc ~?J9-----~
'RGB BOND- OUT OPTION
CDPI876
820M-11t11 R2
XTAL XTAL
CHROM
PCB
Fig. 3 - CDP1B70C and CDP1B76C block diagram.
380 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1869C, CDP1870C, CDP1876C
FUNCTIONAL DESCRIPTION OF CDP1870C TERMINALS
PREDISPLAY (Output):
An output signal that goes low one horizontal line before
the start of the display field. This output may be connected
to the CPU to provide advance warning of a refresh
operation.
DISPLAY (Output):
An output signal that is low during the display field. This
signal is connected to the CDP1869C to provide synchronization timing during a screen refresh.
PCB-PAGE-MEMORY
COLOR BIT (Input):
The page-memory color bit expands the character color
information to 3 bits (8 colors, Table 3). It may also be used
to expand the character-memory addressing when orily 4
dot colors are required.
CCBO, CCB1-CHARACTER-MEMORY
COLOR BITS (I/O):
The character-memory color bit inputs provide character
color data. These two inputs select one offour colors (Table
3). When the CMSEL input is high during non-display
periods, CCBO and CCB1 are multiplexed to the CPU data
bus (BUS 6, BUS 7) to provide character memory
READ/WRITE data.
CDBO-CDB5-CHARACTER-MEMORY
DATA BITS (I/O):
The character-memory data bit inputs provide character
data during screen refresh periods. When the CMSEL input
is high during non-display periods, CDBO-CDBS are
multiplexed to the CPU data bus (BUSO-BUS5) to provide
character memory READ/WRITE data.
BUS O-BUS 7 (I/O):
The 8-bit bidirectional data bus that is normally connected
directly to the CPU. During non-display periods, these I/O
lines serve a dual function. If the CMSEL input is high, BUS
O-BUS 7 provide Character-memory READ/WRITE data. If
the N=3 input (OUT 3 instruction) is low, BUS O-BUS 7
provide input data to the CDP1870C command register.
These data are latched on the high-to-Iow transition of TPB
when MRD is low.
Vss:
Ground.
N=3 (Input):
An input signal from the CDP1869C that is low during an
OUT 3 instruction from the CPU. This input is used to select the CDP1870C command register.
EVS, EHS-EXTERNAL VERTICAL
SIGNAL, EXTERNAL HORIZONTAL
SIGNAL (Inputs):
The active low external vertical and horizontal sync signals
synchronize the VIS to an external system. When not used,
these inputs must be connected high.
XTAL (Input), XTAL (Output)-CHROM
COLOR CHROMINANCE CRYSTAL
The color chrominance crystal inputs are normally connected to a 7.1S909-MHz crystal (NTSC) or an 8.867236MHz crystal (PAL) to provide a burst and color data input
clock. The XTAL input may be connected to an external
generator. (With the RGB Bond-Out option, CDP1876C, the
chrominance crystal is not required although the XTAL
input must be terminated.)
NTSC CHROM (Output):
The United States National Television System Committee
(NTSC), standard color video output signal. This output
provides a composite signal containing chrominance
information and 11 cycles of the color reference signal.
(With the RGB Bond-Out option, CDP1876C, this output
provides the GREEN drive.)
PAL CHROM (Output):
The European Phase Alternation Line (PAL), standard color
video output signal. This output provides a composite
signal containing chrominance information and 14 cycles
of the color referenc,e signal. (With the RGB Bond-Out
option, CDP1876C, this output provides the BLUE drive.)
LUM-LUMINANCE (Output):
The luminance output signal provides video dot brightness
information, (With the RGB Bond-Out option, CDP1876C,
this output provides the RED drive.)
COMPSYNC (Output):
The composite TV synchronization signal provides active
low pulses at the line (horizontal) and frame (vertical) rates.
HSYNC (Output):
The horizontal synchronization signal provides an active
low pulse at the TV line rate. It is connected to the
CDP1869C to control timing synchronization.
BURST (Output):
This output provides an active high pulse following the
horizontal sync pulse. It indicates when the color reference
signal is being output, however, it is not required for normal
operation.
CMSEL-CHARACTER-MEMORY
SELECT (Input):
The character-memory select input, from the CDP1869C,
indicates a character-memory READ/WRITE operation.
When CMSEL is high, the 8-bit bidirectional data bus from
the CPU is multiplexed to the CCBO, CCB1, and CDBOCDBS I/O lines to provide character-memory data. This
input is active only during non-display periods.
TPB (Input):
An active high pulse from the CPU that occurs once in each
machine cycle, following the TPA pulse. This input pulse is
used to latch the CDP1870C command register data on the
high-to-Iow transition, when the N=3 and MRD inputs are
low.
MRD-MEMORY READ (Input):
An active low pulse from the CPU indicating a memory
READ cycle. This signal enables the command register
clock and selects the direction of data flow in the data bus
multiplexer. When this signal is low, a CPU READ operation
is in progress.
ADDSTB MEMORY ADDRESS
STROBE (Output):
The ADDSTB output signal is connected to the CDP1869C
to provide the page and character-memory address counter
clock during display time,
XTAL (Input), XTAL (Output)-DOT
CRYSTAL:
The dot crystal inputs are normally connected to a 5.67MHz crystal (NTSC) or a S.626-MHz crystal (PAL) that is
used to provide horizontal, vertical, and control timing. The
XTAL input may be connected to an external generator.
CPUCLK-CLOCK (Output):
A clock output equal to y, the DOT frequency. It may be
connected to the CPU CLOCK input terminal. At this
frequency, 2947 instructions per frame are available, with
787 instructions occurring during the non-display period.
PAL/NTSC (Input):
This i!!E!:!!..selects either PAL or NTSC operation. When the
PALINTSC input is high, the VIS provides PAL compatible
output signals. When the PAL/NTSC input is low, the VIS
provides NTSC compatible output signals.
VDD:
Positive supply voltage.
382 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1869C, CDP1870C, CDP1876C
H
H
176·4 ns(NTSC)
177·8 ns ( PAL)
DOT CLOCK
CPU CLOCK
DOT CLOCK+6*
S I_______...JrlL-_ _ _ _ _ _....JIIL._ _ __
DOT CLOCK+ 12**
*DOT CLOCK +6 IS
**DOT CLOCK +12 IS
Ji""5DS'fB
A1lDSTB
FOR FULL HORIZONTAL RESOLUTION DISPLAY
FOR HALF HORIZONTAL RESOLUTION DISPLAY
Fig. 4(a) - ADDSTB timing diagram.
01
4
10
II
I
'I
I
HORIZONTAL
11'"---1Ii-t(-nl
BLANKING....J
I I.
HORIZONTAL
SYNC
BURST
50
o
56
60
111111111111111111111111111111111111111111111111111111IIIIIIIIIIIIIIIIIIU
DOT CLOCK';' 6
I
I
.
I
I
I
I
I
1
.I
L
I
'I I
I
I
"--'~--,-_-:..,II_______________l...--_r---1
--.-oJ
LI
1
I'
I
---rJln
L--
I
I
II
:I
rL
NTSC DISPLAY _ _ _L-_ _--,',.,I
PAL DISPLAY
---t---.. .
LEVEL DEPENDS ON COLOR AND CHARACTER BITS
VIDEO (NTSC)
92CM-31912RI
~ig.
H SYNC
COUNT
2542 12
I
VERTICAL BLANKING
VERTICAL SYNC
I
I
32
I
I
4(b) - Horizontal timing diagram.
52
I
72
I
I
I
92
I
I
112
I
132
I
I
I
152
I
I
172
I
I
192
I
I
212
I
232
I
I
2520 10
I
I
I
I
50
30
I
I
I
I
70
I
I
I
JoI-------------------~2~58262~---n
J
nL-_ _ _ __
36~-----------------~228
VERTICAL DISPLAY
_____~I
~I------....Ir---
1-1.-----192------1.1
NTSC
H SYNC COUNT
VERTICAL BLANKING
n
304 2 12
I
I
I
I
32
I
I
52
I
I
72
I
I
'32
I
I
112
t
I
132
I
I
152
I
I
172
I
I
192
I
I
212
I
I
232 252
I
I
I
I
272 292
I
I
I
I
3121020
I
I
I
30~
3080 L-------------------------~3~080
VERTICAL SYNC
J
VERTICAL DISPLAY
_____~rl--------------~I-----
~
44
260
""1.1---------- ---------1.1
216
PAL
92CM-31910RI
Fig. 4(c) - Vertical timing diagram.
384 - - - -_ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1869C, CDP1870C, CDP1876C
DYNAMIC ELECTRICAL CHARACTERISTICS at T A=-40· to 8S·C, CL=SO pF
Vee ± 5%, Except as noted
CHARACTERISTIC
LIMITS
CDP1889C
CDP1870C, CDP1878C
MIn. I Typ.· I Max.
Vee
(V)
UNITS
Refresh Memory Timing - See Fig. 8
ADDSTB Delay Time From DOT Clock
lASe
5
Page Memory Address Delay From ADDSTB
IpMe
5
tes
5
Character Data and Color Bits Set-up Time
-
215
300
250
-
"Typical values are for T.=2S o C and nominal Voo,
DOT
PMAO-PMAIO
--
'PMO
I-I-X
*
eoo-co,---~:!-J_--_
ceo-eel __________________________
....
'OS
I--
~-._--~
• AVAILABLE PAGE AND CHARACTER MEMORY ACCESS TIME
FULL HORZ AESOLUTION=(DOT eLK XI)-tPMD-IDs
HALF HORZ RESOLUTION·(DOT CLK. 12)-1,.0-10.
TYPICAL AVAILABLE ACCESS TIME (NTIC. 5 V):
(116.4.6)-300-260·508,4 nl (FULL RES,)
(116,4.12)-300-250'1,11111' (HALF RES.)
lteM- 35918
Fig, 6 - Refresh memory timing waveforms,
ns
.386 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
· CDP1869C, CDP1870C, CDP1876C
-_ .......
Table 8
DISPLAY FORMAT COMBINATIONS (FULL COLOR SYSTEM)
COMMAND DATA
CDP1870C CDP1869C CDP1869C CDP1869C
CHAR
CHARI
jeDP1869C
FRES
DISPLAY
FRES
DOUBLE 16-LlNE
9-LlNE
ROW
HORZ
VERT
PAGE
HI-RES
MATRIX
CHAR
ROWSI
FRAME
TOTAL
CHARI
FRAME
0
0
0
0
1
6x8
20
12
240
0
0
0
1
1
6 x 16
20
6
120
0
0
1
0
1
6x8
20
12
240
0
1
0
0
1
6x8
20
24
480
0
1
0
1
1
6 x 16
20
12
240
0
1
1
0
1
6x8
20
24
480
1
0
0
1
1
6 x 16
40
6
240
1
0
1
0
1
6x8
40
12
480
1
1
0
0
1
6x8
40
24
960
1
1
0
1
1
6 x 16
40
12
480
1
1
1
0
1
6x8
40
24
960
0
0
0
0
0
6x9
20
12
240
0
1
0
0
0
6x9
20
24
480
1
1
0
0
0
6x9
40
24
960
--
NOTE: ALL OTHER COMMAND COMBINATIONS ARE INVALID AND WILL RESULT IN IMPROPER DISPLAY OPERATION.
'NTSC Format
"PAL Format.
-=7 BITS FOR CHARACTER ADDRESS DATA. 1 BIT FOR COLOR DATA
Tlble I
CDP1881 COMMAND REGISTER CODES
CPU 1/0
INSTRUCTION
MA15 MA14
TONE
.,.
O·
OUT4
26
WN
WN
FREO
OUT5
OFF
SEL2
MA13
TONE
MA12
TONE
MA11
TONE
MA10
TONE
22
.,.
+,
.,.
2·
WN
FREO
SEL1
24
WN
FREO
SELO
23
WN
AMP
23
OUT6
X
X
X
X
X
OUT7
X
X
X
X
X
X=DON'T CARE
'=MUST BE PROGRAMMED LOW
"=ALWAYS SET LOW INTERNALLY
'''=MUST BE PROGRAMMED LOW DURING 9-LINE OPERATION
.,.
MAl
TONE
+
2'
WN
WN
AMP
AMP
22
2'
PMA10 PMA9
REG
REG
HMA10 HMA9
REG
REG
MA8
TONE
+
2°
WN
AMP
2°
PMA8
REG
HMA8
REG
388 _ _-:..._ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1869C, CDP1870C, CDP1876C
-COLUMN
01234567891011
012345
NUMBER012345
01234567891011
o
I
2
3
4
5
6
PAL ONLY-~+1:t:~~==+;+:+t:;::-;:::;-:;-~~
o
1
2
3
4
5
6
7
8
~
9
10
II
12
13
It4~JL~4===~~~
,. PAL ON LyJI6
- ll7
____-t~==:it:==:±==:i_
5
~
"'
!:
\
...J
6
~
CHAR. SIZE NUMBER
(SEE TABLE B )
92CL- 31908R2
Fig. 9 - Character display matrix size.
table 10
CDP1870C COMMAND REGISTER CODE
CPU 1/0
INSTRUCTION
OUT 3
BUS 7
BUS6
BUS 5
FRES
HORZ
COLB1
COLBO
BUS4
DISP
OFF
BUS 3
CFC
BUS2
BKG
RED
BUS 1 BUS 0
BKG
BKG
BLUE GREEN
390 ______________ CMOS Microprocessors, Memories and P,ripherals
Advance Information/
Preliminary Data
CDP1871A, CDP1871AC
,...
"
"
DO
"
DO
CMOS Keyboard Encoder
'DO
SHIFT
.." ..,
"'"
" ..
""
..
..
CONTROL
ALPHA
DEBOUNCE
Features:
• Directly interfaces with CDP1800-series
microprocessors
• Low power dissipation
• 3-State outputs
• Scans and generates code for 53 key ASCII
keyboard plus 32 HEX keys (SPST mechanical
contact switches)
• Shift. control. and alpha lock inputs
• RC-control/ed debounce circuitry
• Single 4 to 10.5 V supply (CDP1871A); 4 to 6.5 V
(CDP1871AC)
• N-key lockout
IUS 7
D.
Bust
BUS'
BUS 4
"so
51
'ss
"
"
"
.,"
17
BUS 3
aus
"
CS.
""
CSi
0
TOP VIEW
Terminal Assignment
vents unwanted key codes if two or more keys are pressed
simultaneously.
The RCA-COP1871A is a keyboard encoder designed to
directly interface between a COP1800-series microprocessor and a mechanical keyboard array. providing up to 53
ASCII coded keys and 32 HEX coded keys. as shown in the
system diagram (Fig. 1).
The COP1871 A and COP1871AC are functionally identical.
They differ in that the COP1871 A has a recommended operating voltage range of 4 to 10.5 volts. and the COP1871AC
has a recommended operating volt1,lge range of 4 to 6.5
volts. These types are supplied in 40-lead dual-in-line
ceramic packages (0 suffix). and 40-lead dual-in-line plastic packages (E suffix).
The keyboard may consist of Simple single-pole singlethrow (SPST) mechanical switches. Inputs are provided for
alpha-lock. control. and shift functions. allowing 160
unique codes. An external R-C input is available for userselectable debounce times. The N-key lock-out feature pre-
t
H
a I ~F
lOOK
~
401
21
NO -N2
'4
0111
C53
23
2.
TPB
DEBOUNCE
m.
CS2.
CONTROL
MRO
T'6
I
I
I
I
I
I
CS4
TPB
CDPI871A
CDP1800- SER I ES
VOO
CPU
SHIFT
>---o....L~
01
SHIFT
I
CONTROL
>---o...L~
CONTROL
~HALOCK
~ALPHA
BUSO -
BuS?
00RMAL
"
T
I
BUD
aUST
51
52
53
54
55
56
57
5B
I
UP TO II SETS
OF 8 SWITCHES EACH
I
I
I
I
1V~I~V~I~t~
1.1'
"
14
15
16
17
IB
19
rr
~~1
92CL-35 00'
II
Fig. 1 -
251
32
1
8- BIT DATA BUS
Typical CDPl800-series microprocessor system using the CDP1871A.
File Number
1374
392 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1871A, CDP1871AC
STATIC ELECTRICAL CHARACTERISTIC at T A = -40 to +85 0 C, except as noted
LIMITS
CONDITIONS
CHARACTERISTIC
Va
(V)
Quiescent Device
Current
Output Low Drive (sink) Current
(except debounce and D1-D11)
Debounce
-
IDD
IDL
10L
D1-D11
Output High Drive (Source) Current
10L
10H
Input Low Voltage
(except Debounce)
Input High Voltage
(except Debounce)
Debounce Schmitt Trigger
Input Voltage
Positive Trigger Voltage
VIL
V,H
VD
Negative Trigger Voltage
VN
Hysteresis
Output Voltage Low Level
VH
VOL
-
Input Leakage Current
(except S1-S8. Shift, Control)
3-State Output Leakage Current
VOH
-
liN
-
louT
Pull-Down Resistor Value
(S1-S8, Shift, Control)
Operating Current
(All-outputs fCL = 0.4 MHz
unloaded)
fcc = 0.8 MHz
= +25
0.4
0.5
0.4
0.5
0.4
0.5
-
Output Voltage High Level
'Typical values are for TA
-
0.4
0.5
0.4
0.5
0.4
0.5
4.6
9.5
0.5,4.5
1,9
0.5,4.5
1,9
RpD
0.5
0,10
-
VIN
(V)
0,5
0,10
0,5
0,10
0,5
0,10
0,5
0,10
0,5
0,10
-
-
0,5
0,10
0,5
0,10
0,5
0,10
0,5
0,10
0,5
0,10
-
VDD
(V)
5
10
5
10
5
10
5
10
5
10
5
10
5
10
CDP1871AD
CDP1871AE
MIN. TYP.' MAX.
0.1
50
1
200
1
0.5
2
1
0.75
1.5
1
2
.05
0.1
0.2
0.1
-0.3
-0.6
-0.75
-1.5
1.5
-3
3.5
7
5
10
5
10
-
-
3.3
6.3
1.8
4.0
1.6
2.3
0
0
5
10
.01
.01
.01
.02
-
7
14
5
-
0.6
2.7
5
10
5
10
5
10
5
10
5
10
2.0
4.0
0.8
1.9
0.3
0.7
-
4.95
9.95
-
4.0
8.0
3.0
6.0
2.6
4.7
.05
.05
CDP1871ACD
UNITS
CDP1871ACE
MIN. TYP.' MAX.
1
200
fJ.A
-
-
0.5
-
-
-
-
0.75
1.5
-
-
-
-
.05
0.1
-
-
-
-
-0.3
-0.6
-
-
-
-
-
-
1.5
-
-
-
-
2.0
3.3
4.0
-
-
-
0.8
1.8
3.0
-
-
-
0.3
1.6
2.6
-
-
-
0
.05
-
-
-
5
-
-
-
3.5
-
4.95
-
-
1
1
1
2
1
mA
-
-
.01
1
-
-
.02
2
-
-
-
24
7
14
24
-
-
0.6
~
-
-
-
V
fJ.A
kO
loper
0.5,4.5
1,9
0
C. and nominal Voe.
0,5
0,10
10
-
mA
394 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1871A, CDP1871AC
TABLE 3 -
DRIVE AND SENSE LINE KEYBOARD CONNECTIONS*
S2
89,6
91,6
99'6
S3
8A,6
92,6
9A,6
S.
8B'6
93,6
9B'6
S5
8C'6
94,6
9C'6
S6
8D,6
95,6
9D,6
S7
8E'6
96,6
9E'6
S.
8F,6
97,6
9F,6
Err::']
'CONTROL overrides SHIFT and ALPHA
= NO RESPONSE
:j:Showing ASCII outputs for all combinations with and without SHIFT, ALPHA LOCK and CONTROL.
tDrive lines 8, 9,10, and 11 generate non-ASCII hex values which can be used for special codes.
TABLE 4 -
HEXIDECIMAL VALUES OF ASCII CHARACTERS
b7- 0
b6b5-o
BITS
LSD
0
0
0
0
MSD
0
0
1
1
1
1
1
1
0
1
1
0
0
1
0
1
1
0
1
7
HEX
b4
b3
b2
b1
r
0
1
2
3
6
0
0
0
NUL
DLE
SP
0
P
\
P
0
0
1
SOH
DC1
!
1
A
Q
a
q
0
0
0
0
1
4
@
5
0
1
STX
DC2
B
R
b
r
1
3
ETX
DC3
"
#
2
0
0
1
2
0
3
C
S
c
s
0
0
1
0
EOT
DC4
$
4
D
T
d
t
0
0
1
4
1
5
ENQ
NAK
%
5
E
U
e
u
0
1
6
ACK
SYN
&
6
F
v
1
7
BEL
ETB
/
7
G
V
W
f
1
1
1
0
0
9
w
1
1
1
1
1
1
1
1
0
0
0
8
BS
CAN
(
8
H
X
0
1
9
HT
EM
I
Y
0
A
LF
SUB
.
9
0
0
1
:
J
Z
j
z
0
1
1
B
VT
ESC
+
;
K
k
{
1
1
1
1
0
0
0
C
FF
FS
<
L
[
\
I
I
I
1
D
CR
GS
=
M
1
I
1
1
0
E
SO
RS
>
N
1
m
n
1
F
SI
US
?
0
0
DEL
)
/
-
h
i
x
L
396 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1871A, CDP1871AC
I
~
I
I
I
I
I
I--RNCXj
i--RXCx--j
OEBOUNCE---------~~,________~~------~I~-~---------------+I------------, tCOt
r-
P_R_E_S_E_NT~:~C-O-U-NT------~:--------~~~------~:~-----------------------~NT
OI-OII _______
CS*
I
----------~----------~~~------~u------~------~·
-I tcovi-
BUSO- BUS7
-----------ilrl----------~U~------~I~I------~U~--------~~
* CS" -CSI· C52 .C53-C54
~
tCDH
VALID
r-
>---
92CM<~5006
CSI, C52, G53" CPU N-LiNES
C54 (MRO) IS HIGH FOR CPU INPUT INSTRUCTION
Fig. 3 -
CDP1871A dynamic timing diagram (non-repeat).
n
TPB
I
I
KEY
DEPRESSED
I
-4
~
--fL~
CLOSED
r-
I
U
U
u
OPEN
tDAH
r--
--I
~
____~r-l~_______
~tRP"1
t RPL
U
:
11..J
f--RxCx:.j
~
OEBOUNCE
P_R_E_S_E_NT_-CO-U-N-T----:11---------i~
01- 011 _____
---.J
CS*
r-----<:
I
~tCDH [ -
~tcov
BUSO-BUS7
*
VALID
II
~I~------__~~~--------------------------
CS=CST.CS2.CS3-CS4
cs= CST, C52 ,C53 = (CPu N-LINES)
C54 (MRD) IS HIGH
Fig 4 -
NEXT COUNT
FOR CPU INPUT INSTRUCTION
CDP1871A dynamic timing diagram (repeat).
92CM - 35007
398 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1872C, CDP1874C, CDP1875C
C51
DID
DOD
oI I
001
oI2
002
013
003
CLOCK
Vss
22
21
20
19
18
17
16
15
14
13
12
5
6
10
~
"
High-Speed
8-Blt Input and Output Ports
Voo
017
007
oI6
006
015
005
014
004
- CLR
C52
Features:
• Parallel 8-bit input/output register with buffered outputs
• High-speed data-in to data-out:
85 ns (max.) at VOO=5 V
• Flexible applications in microprocessor systems as
buffers and latches
• High order address-latch capability in COP1800 series
microprocessor systems
• Output sink current=5 mA (min.) at VOO=5 V
• 3-state output-COP1872C and COP1874C
TOPVIEW
92('~
'3012
CDP1872C Inpul Port
TERMINAL ASSIGNMENT
The RCA-CDP1872C, CDP1874C and CDP1875C devices
are high-speed 8-bit parallel input and output ports
designed for use in the CDP1800 microprocessor system
and for general use in other microprocessor systems. The
CDP1872C and CDP1874C are 8-bit input ports; the
CDP1875C is an 8-bit output port.
These devices have flexible capabilities as buffers and data
latches and are reset by
Input when the data strobe is
not active.
ern
The CDP1872C and CDP1874C are functionally identical
except for device selects. The CDP1872C has one active
low and one active high select; the CDP1874C has two
CSI
DID
DOD
011
001
DI2
002
DI3
D03
CLOCK
V5S
I
2
3
4
5
6
7
8
9
10
"
Advance Information/
Preliminary Data
22
21
20
19
18
17
16
15
14
13
12
Voo
017
007
016
006
DI5
D05
014
D04
CLR
CS2
TOP VIEW
92CS~330"
CDP1874C Inpul Port
TERMINAL ASSIGNMENT
active high device selects. These devices also feature 3state outputs when deselected. Data is strobed into the
register on the leading edge of the CLOCK and latched on
the trailing edge of the CLOCK.
The CDP1875C is an output port with data latched into the
registers when the device selects are active. There are two
active high and one active low selects. The output buffers
are enabled at all times.
These devices are supplied in 22-lead hermetic, dual-in-line
side-brazed ceramic packages (0 suffix) and in 22-lead
dual-in-line plastiC packages (E suffix).
C51
DID
000
DI I
001
DI2
002
013
003
C53
VSS
10
"
22
21
20
19
18
17
16
15
14
13
12
VOO
017
007
DI6
006
DI5
D05
DI4
004
CLR
CS2
TOP VIEW
92CS-33010
CDP1875C Output Port
TERMINAL ASSIGNMENT
File Number
1255
400 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1872C, CDP1874C, CDP1875C
CSI
Dr
CS2
01-------1
DO
CSi
CLOCK - . . - - - - - - 1
CS2
CS3
DO
92CS-33009
Fig. 2-Equiva/ent logic diagram (1 of 8 latches shown)
for CDP1874C.
Fig. 3-Equiva/ent logic diagram (1 of 8 latches shown)
for CDP1875C.
DYNAMIC ELECTRICAL CHARACTERISTICS at TA=25° C, VOO=5 V, tr,t, =10 ns, VIH=O.7 VOO,
V,L =0.3 VOO, CL =150 pF
LIMITS
CDP1872C
CDP1874C
Typ."
Max.t
CHARACTERISTIC
UNITS
I
Input Port (Fig. 4)
Output Enable
Output Disable
Clock to Data Out
Clear to Output
Data In to Data Out
Minimum Data Setup Time
Data Hold Time
Minimum Clock Pulse Width
Minimum
Pulse Width
45
45
45
80
50
10
10
30
30
tEN
tDIS
telo
tCRO
tOIO
tosu
tOH
tCl
tCR
maar
• Typical values are for TA=25°C and VDD ±5%.
t Maximum values are for TA=85°C and VDD ±5%.
fcSjPlmC)
CSI· CS2
(COPI874C)
i
....II
\
i
f R j t o s u,IOH
I
~
I"--I
___...J7I ~I..-;-II ___
----:1_ _ _0---"-1-"---:-1+1______
I
CLOCK __
DATA IN
I-ICL-i
IDATA BUS
(HIGH Z)
IIEN~
tCLol
I
d
'-----:--to1oLJ
i?
1-
~tOIS~
g 1CRO
t._ _
CLR--------~~-------
tCR
92CM·33006
Fig. 4-Timing waveforms for CDP1872C and CDP1874C (input-port types).
90
90
90
160
85
30
30
60
60
ns
402 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1872C, CDP1874C, CDP1875C
CLOCK
-
DATA BUS
Ir-
DO - D7
'-
MRii
t-- AO
Nlr--
-AI
N2 f-,--
-
\;=J
DATA IN
IT!
CDPIB73C
CLOCK
~
CS2
~
~ CSI
-
CDPIB02
--
r--
03104r05r061071-
A2
CS2
CDPIB72C
Oi
02
NOr--
r
DATA BUS
CDPIB72C
~
DATA IN
92CS-33003
Fig. 7-CDP1872C used as an input port and selected by CDP1873C.
I
MRD
COPI802
-
NO NI N2 00-07
I •
CSI
CS2
1
CS2
CSI
TPB- CS3
DATA IN
C~ 01
DO
01
CDPI874C
DO
CS2
CS2
-"
--v
01
DATA OUT
)
DATA OUT
COPI875C
CSI
DATA IN
)
v
01
DO
CSI
DO
TPB- CS3
COPI875C
CDPI874C
MEMORY
92CS-33002
Fig. 8-CDP1874C and CDP1875C used as input/output buffers.
404 _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1873C
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE. (VDD)
(Voltage referenced to VSS terminal) ..................................... -0.5 to +7 V
INPUT VOLTAGE RANGE. ALL INPUTS ............................... -0.5 to VDD +0.5 V
DC INPUT CURRENT. ANY ONE INPUT ....................................... ±10 rnA
POWER DISSIPATION PER PACKAGE (PD):
For TA=-40 to +60·C (PACKAGE TYPE E) ••••••••••••••••••••••••••••••••••• 500 mW
For TA=+60 to +85·C (PACKAGE TYPE E) •••••••••••.Derate Linearly at 12 mW/·C to 200 mW
For TA=-55 to +100·C (PACKAGE TYPE D) •••••••••••••••••••••••••••••••••• 500 mW
For T A=+100 to +125·C (PACKAGE TYPE D) ••••••••• Derate Linearly at 12 mW/·C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For TA=FULL PACKAGE-TEMPERATURE RANGE (All Package Types) •••••••••••••• 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE D ••••••••••••••••••••••••••••••••••••••••••••••••• -55 to +125·C
PACKAGE TYPE E •••••••••••••••••••••••••••••••••••••••••••••••••• -40 to +85· C
STORAGE-TEMPERATURE RANGE (Tstg) •••••••••••••••••••••••••••••••• -65 to +150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
• •••••••••••••• +265·C
STATIC ELECTRICAL CHARACTERISTICS at TI.e.= - 40 t0+ 85·C , excep as not ed
CONDITIONS
LIMITS
CHARACTERISTIC
CDP1873C
UNITS
Vo
VIN
VDD
tV)
(V)
Max.
Typ."
Min.
Quiescent Device
0.5
5
5
50
,..A
Current, 100
Output Low Drive
rnA
(Sink) Current,
0.4
0, 5
5
6
12
M
-
-
IOL
Output High Drive
(Source) Current,
IOH
Output Voltage
Low-Level,
VOLA
Output Voltage
High Level,
VOH A
Input Low Voltage,
VIL
Input High Voltage,
VIH
Input Leakage
Current, liN
Operating Current,
1001-
.
Input Capacitance,
CIN
4.6
0, 5
5
-4
-
0, 5
5
-
-7
-
0
0.1
rnA
V
-
-
0, 5
5
4.9
0.5,4.5
-
5
-
-
1.5
0.5,4.5
-
5
3.5
-
-
0,5
5
-
-
±1
,..A
-
0,5
5
-
2
3
rnA
-
-
-
-
20
-
pF
5
V
Any
Input
TYPical values are for T A = 25·C and nominal voltage, VDD.
AIOL=IOH =1 ",A.
• Operating current is measured at 200 kHz for VDD=5 V and 400 kHz for VDD=10 V, with
open outputs (worst-case frequencies for CDP1802A system operating at maximum speed of 3.2 MHz).
406 _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1873C
OUTPUT
VIA
61 INSTRUCTIONS
COPI802
OUTPUT
VIA
62 INSTRUCTIONS
INPUT
VIA
69 INSTRUCTIONS
62r-------------~
EXPANOABLE UP
TO 7 INPUT ANDI
OR OUTPUT PORTS
COPI873Cll!
.04
~
INPUT
VIA
6A INSTRUCTIONS
Ol;
VSS
U7
92CM-32891
MEMORY
Fig 3 - N-/lne decoded In
a one-level 110 system.
00
llT
TPA
AO
~
A7
CDPIB02
CLOCK
-"
:6
AI
ET
CDPI874C
A9f+~~J~RY
A8
"!!2
A2
AI3
AI2
All
CDPI873C
E2
E3
JSS
VIDD
1-+ ADDRESS
LINES
A2
CSI,CS2
AI
VDD
AO CDPI873C
'--VSS
L
ll!
l!4
"!rn"
lrn"
O'f
~
10 IK MEMORY
CHIP SELECTS
~
~
~~
CO
llT
~
::
05
E2
Oil
Ci7
~
~
~
~
TO IK MEMORY
CHIP SELECTS
t::
92CM-32892
FIg. 4 - 16-k memory-select using the CDP1873C with the CDP1874C as an address latch.
408 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1877, CDP1877C
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VDD)
(Voltage referenced to VSS terminal)
CDPI877 ...........................................................................•.•......................... -0.5 to +11 V
CDPI877C ...........................................................•.......................................... -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS .•........................................ ·· ....... ···· ............... -0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ............................... , ................................................. ±10 mA
POWER DISSIPATION PER PACKAGE (PD):
For T A=-40 to +60°C (PACKAGE TYPE E) ............................................................................ 500 mW
For TA=+60 to +85°C (PACKAGE TYPE E) ............................................. Derate Linearly at 12 mWfOC to 200 mW
For TA=-55 to +IOO°C (PACKAGE TYPE D) .......................................................................... 500 mW
For TA=+100 to 125°C (PACKAGE TYPE D) ............................................ Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA=FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ................................................ 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE D ............................................................................................ -55 to +125°C
PACKAGE TYPE E .............................................................................................. -40 to +85° C
STORAGE-TEMPERATURE RANGE (Tstg) ........................................................................ -B5 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max .................................................... +265°C
STATIC ELECTRICAL CHARACTERISTICS at TA=-40 to +85°C, VDD ±5%, Except as noted
CONDITIONS
CHARACTERISTIC
Quiescent Device
Current
Output Low Drive
(Sink) Current
Output High Drive
(Source) Current
Output Voltage
Low-Level
Output Voltage
High Level
Input Low
Voltage
Input High
Voltage
Input Leakage
Current
3-State Output Leakage
Current
Input Capacitance
Output Capacitance
Operating Device
Current
Vo
(V)
IDD
-
IOL
0.4
0.5
IOH
4.6
9.5
VOH*
VIL
VIH
liN
lOUT
CIN
COUT
VDD
(V)
5
10
5
10
0, 5
0,10
0, 5
0,10
0, 5
0,10
0.5,4.5
0.5,9.5
0.5,4.5
,0.5,9.5
Any
Input
0, 5
0,10
0,5
0,10
0, 5
0,10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
-
-
-
VOL*
VIN
(V)
0, 5
0,10
0, 5
0, 10
-
-
-
IOPER#
"Typical value$ are for TA=25°C and nominal VDD·
5
10
Min,
1.6
2.6
-1.15
-2.6
-
4.9
9.9
-
LIMITS
DP1877
Min.
Typ. "
Max.
0.01
50
1
200
1.6
3.2
5.2
-
-
-2.3
-5.2
0
0
5
10
-
3.5
7
-
-
-
-
0.1
0.1
1.5
3
-
-
±10-4
±10-4
5
10
±1
±2
±1
±10
7.5
15
-
0.5
1.9
1.0
3.0
*IOL =IOH=1 JJA.
# Operating current measured under worst-case conditions in a 3.2-MHz CDP1802A system:
one PIC access per instruction cycle.
DP1877 "
Max.
Typ."
0.02
200
-
-
3.2
-
-
-
-2.3
-
-
-
0
0.1
-
-
4.9
5
-
-1.15
3.5
-
-
-
-
1.5
J.1A
mA
V
-
±1
-
-
±10-4
-
-
-
-
5
10
7.5
15
0.5
1.0
-
UNITS
±1
J.1A
pF
mA
410 - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Peripherals
CDP1877, CDP1877C
PIC Programming Model
INTERNAL REGISTERS
The PIC has three write-only programmable registers and
two read-only registers.
Page Register
This write only register contains the high order vector
address the device will issue in response to an interupt
request. This high-order address will be the same for any of
the 8 possible interrupt requests; thus, interrupt vectoring
differs only in location within a specified page.
I
BUS 7
BUS 0
PAGE REGISTER BITS
, -_ _A_1.:...5_.L.-_A__1__
4_...J-~A.:...1..:.3___ll____.:A..:..1:..:2l_..JI_....:A:..:.1.:...1_ ___l_A::..:.:.:1O=--.---L._:..:.A.:;:9_.....I-_:..:.A.;,:8=--....l WR ITE ONLY
Control Register
The upper nibble of this write-only register contains the low
order vector address the device will issue in response to an
interrupt request. The lower nibble is used for a master
interrupt reset, master mask reset and for interval select.
BUS 0
BUS 7
WRITE ONLY
INTERVAL SELECT
DE:TERMINES NUMBER OF
BYTES ALLOCATED TO EACH
INTERRUPT SERVICE ROUTINE
Bit 1
Bit 0
Interval
o
o
4
1
o
1
o
8
1
1
16
2
MASTER MASK RESET
REGISTER BITS
1 NO CHANGE
o RESETS ALL MASK
MASTER INTERRUPT RESET
INTERRUPT LATCHES
CLEARS ANY PENDING INTERRUPTS
1 NO CHANGE
o RESETS ALL
SETS UPPER BITS OF THE LOW ORDER
VECTOR ADDRESS AS A FUNCTION OF THE
INTERVAL SELECT
THE LOW ORDER VECTOR ADDRESS WILL BE SET ACCORDING TO THE TABLE BELOW:
INTERVAL SELECTEDNO. OF BYTES
2
4
8
16
BIT B7
SETS A7
SETS A7
SETS A7
SETS A7
LOW ADDRESS BITS
BIT B6
BIT B5
SETS A6
SETS A5
SETS A6
SETS A5
SETS A6
X
X
X
X=DON'T CARE
NOTE: All DON'T CARE Addresses and Addresses AO-A3 are determined by interrupt request.
BIT B4
SET A4
X
X
X
412 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1877, CDP1877C
Third (Low-Order Address) Bytes
iNTERVAL 2
BUS 7
A7
BUS 0
A6
AS
o
A4
iNTERVAL 4
BUS 7
BUSO
A6
A7
o
AS
iNTERVAL 8
BUS 7
BUS 0
o
A6
A7
o
o
iNTERVAL 16
BUS 7
o
BUS 0
o
A7
o
o
o
Indicates active interrupt input number (binary 0 to 7).
Bits indicated by Ax (x=4 to 7) are the same as programmed
into the Control Register. All other bits are generated by the
PIC.
REGISTER ADDRESSES
In orderto read/write or obtain an interrupt vector from !!!y
PIC in the system, all chip selects (CS/Ax, CS/Ay, CS, OS)
must be valid during TPA.
-
CS/Ax and CS/Ay are multiplexed addresses; both must be
high during TPA, and set according to this table during TPB
to access the proper register.
ACTION TAKEN
CS/Ax
CS/Ay
RD
WR
1
0
0
1
READ Long Branch instruction and vector 'for highest priority unmasked
interrupt pending.
WRITE to Page Register
1
0
1
0
1
1
0
0
0
0
0
0
0
0
1
READ Status Register
1
0
WRITE to Mask Register
1
0
1
READ Polling Register (Used to identify INTERRUPT source if Polling technique rather than INTERRUPT service is used.)
1
1
X
X
Unused condition
WRITE to Control Register
414 ______________ CMOS MicroprocessOI'$, Memories and Peripherals
CDP1877, CDP1877C
Example II-Multl-PIC Application
Fig. 3 shows all the connections required between CPU and
PICs to handle sixteen levels of interrupt control.
+v
CPU
MA7
CS/Ax
MAG
CS/Ay
MA5
CS
MAl
CS
MWR
ill
ffi
MRD
fR5
MAO
"MWr'
IiWi
TPA
1
TPB
iNT
A
BUS
11
I I
I I I
I I
I I
TPA
TP6
iR3
fNf
'I R2
I
BUS
ill
IRO
Fit I
CDPI877
CDPI802
~ CS/AII
'------+ CS/Ay
~
~
J4J4-
IR7
cs
v
NIGHEST
PRIORITY
INTERRUPT
mcJ
CS
"-
:=
riR4
r;::-
"
J
~
IR6
MWR
IR5
MRD
'1 R4
TPA
TRS
TPB
IR2
INT
TRi
PIC 2
IRO
BUS
CDPIBn
:=
~
~
J4-
r-
LOWEST
PRIORITY
INTERRUPT
92CM-34375
Fig. 3 - PICs and CPU connect/on diagram.
Register Address Assignments
The low-byte register address for any WRITE or READ
operation is the same as shown in Table I.
The high-byte register differs for each PIC because of the
linear addressing technique shown in the example:
PIC l=lllXXXOl (E1H FOR X=O)
PIC 2=111XXX10 (E2H FOR X=O)
The R(l) vector address is unchanged. This address will
select both PICs simultaneously (R(l ).1 =111 XXXOO=EOH).
Internal CDP1877 logic controls which PIC will respond
when an interrupt request is serviced.
Additional PIC Application Comments
The interval select options provide significant flexibility for
interrupt routine memory allocations:
• The 2-byte interval allows one to dedicate a full pageto
interrupt servicing, with variable space between
routines, by specifying indirect vectoring with 2 byte
short branch instructions on the current page .
• The 4-byte interval allows for a 3 byte long branch to
any location in memory where the interrupt service
routine is located. The branch can be preceded by a
Save I nstruction to save previous contents of X and P
on the stack.
• The 8-byte and 16-byte intervals allow enoLigh space to
perform a service routine without indirect vectoring.
The amount of interval memory can be increased even
further if al18 INTERRUPTS are not required. Thus a 4level interrupt system could use alternate iR Inputs,
and expand the interval to 16 and 32 bytes, respectively.
The 4 Chip Selects allow one to conserve total allotted
memory space to the PIC. For one chip, a total of 4
address lines could be used to select the device,
mapping it into as little as 4-Kof memory space. Note
that this selection technique is the only one that allows
the PIC to work properly in the system: I/O mapping
cannot be used because the PIC must work within the
CDP1800 interrupt structure to define the vector
address. Decoded signals also will not work because
the chip selects must be valid on the trailing edge of
TPA.
416 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1878, CDP1878C
INT
TAO
TA1i
TAG
TACL
Rli
.I:-O/MEM
TPB/WI!
TPA
CS
AO
AI
A2
VSS
I
2
3
4
6
7
8
9
10
II
12
13
14
TOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VIEW
VDD
DB7
DB6
DB5
DB4
DB3
DB2
OBI
DBO
TBO
TID
TBG
TBCL
R'ESf'f
92CS-3462&
TERMINAL ASSIGNMENT
Product Preview
CMOS Dual Counter-Timer
Features:
• Compatible with general-purpose and
• Software-controlled Interrupt output
CDP1BOO-series microprocessor systems • Addressable in memory space or
• Two 16-bit down-couniers and two B-bit
CDP1BOO-seriesl/O space
control registers
• 5 modes including a versatile
variable-duty cycle mode
• Programmable gate-level select
• Two-complemented output pins for
each counter-timer
The RCA-CDP1878 and CDP1878C6 are dual countertimers consisting of two l6-bit programmable down
counters that are independently controlled by separate
control registers. The value in the registers determine the
mode· of operation and control functions. Counters and
registers are directly addressable in memory space by any
general-industry-type microprocessors, in addition to
input/output mapping with the CDP1800-series microprocessors.
Each counter-timer can be configured in five modes with
the additional flexibility of gate-level control. The control
registers in addition to mode formatting, allow software
start and stop, interrupt enable, and an optional read
control that allows a stabie readout from the counters. Each
counter-timer has software control of a common Interrupt
output with an interrupt status register indicating which
counter-timer has timed out.
In addition to the interrupt output, true and complemented
outputs are provided for each counter-timer for control of
peripheral devices.
The CDP1878 and CDP1878C are functionally identical.
They differ in that the CDP1878 has a recommended
operating voitage range of 4· to 10.5 voits, and the
CDP1878C has a recommended operating voltage range of
4 to 6.5 volts. These types are supplied in 28-lead dual-inline ceramic packages (D suffix), and 28-lead dual-in-line
plastiC packages (E suffix).
t.Formerly RCA Dev. Type No. TA10981 and TA10981C, respectively.
Table I - Mode Description
Mode
1 Timeout
2 Timeout Strobe
Event cou nter
Trigger pulse
3
Time-delay generation
4
5
Function
Outputs change when clock decrements counter to "0"
One clockwide output pulse when clock decrements
counter to "0"
Gate-Controlled One Shot Outputs change when clock decrements counter to "0".
Retriggerable
Rate Generator
Reoetitive clockwide outout Dulse
Variable-Duty Cycle
Repetitive output with programmed duty cycle
~lIcatlon
Time-base generator
Motor control'
File Number 1341
418 _ _ _ _ _ _ _ _ _ _ _ _~- CMOS Microprocessors, Memories and Peripherals.
CDP1878, CDP1878C
OPERATING CONDITIONS at TA=Full Package-Temperature Range. For maximum reliability,
operating condltlonl Ihould be selected 10 that operation II alwaYI within the following rangel:
liMITS
CHARACTERISTIC
CDP1878
DC Operating Voltage Range
Input Voltage Range
Maximum Clock Input Rise or
Fall Time
tr,tf
Minimum Clock Pulse Width
tWL,tWH
Maximum Clock Input Frequency,
fCl
CDP1878C
Min.
Max.
4
6.5
VSS
VDD
Max.
10.5
VDD
-
5
-
5
J.IS
1
200
DC
1
ns
MHz
200
DC
RESET
1f1j
TPB/WlI
.I-O/lilli
TPA
UNITS
Min.
4
Vss
V
GATE A
I-O
CONTROL
ANO
LOGIC
CS
CLOCK A
A2
AI
AO
iNi' AND
STATUS REGISTER
a-BIT
EXTERNAL
BUS
OATA
BUS
DRIVERS
GATE B
r - - - - - -......."\-...
TBO
m
CLO CK B
92CL~
34627
Fig. 1 - Functional diagram CDP1878 and CDP1878C.
Functional Deflnltlonl for CDP1878 and CDP1878C Termlnall
TERMINAL
USAGE
TERMINAL
Power
VDD-VSS
DBO-DB7
Data to and from device
CS
TPB/m, J!m Directional control signals
1m
AO, A1, A2
Addresses that select counters
'Fi'ESei'
or registers
TACL, TBCl Clocks used to decrement counters
TAG,TBG
Gate inputs that control counters
I-O/MEM
TAO, "i'AO Complemented outputs of Timer A
TBO,m
Complemented outputs of Timer B
TPA
Used with CDP1800-serles processors,
tied high otherwise
USAGE
Active high input that enables device
Low when counter Is "0"
When active, TAO, TBO are low,
TAb, i'§b are high. Interrupt status
register Is cleared
Tied high In CDP1800 input/output
mode, otherwise tied low
420 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1878, CDP1878C
in any order), and then the control register be accessed and
loaded with the control word. The trailing edge of the
TPB/WR pulse will latch the control word into the control
register. The trailing edge of the first clock to occur with
gate valid will cause the counter to be jammed with its initial
value. The counter will decrement on the trailing edge of
succeeding clocks as long as the gate .is valid, until it
reaches zero. The output levels will then change, and if
enabled, the interrupt output will become active and the
appropriate timer bit will be set in the interrupt status
register. The interrupt output and the interrupt status
register can be cleared (to their inactive state) by addressing
the control register with the TPB/WF! line active. For
example, if counter A times out, control register A must be
accessed to reset the interrupt output high and reset the
timer A bit in the status register low. Timer B bit in the status
register will be unaffected.
Functional Description-See Fig. 1
The dual counter-timer consists of two programmable 16bit down counters, separately addressable and controlled
by two independent 8-bit control registers. The word in the
control register determines the mode and type of operation
that the counter-ti mer performs. Writing to or reading from
a counter or register is enabled by selective addressing
during a write or read cycle. The data is placed on the data
bus by the microprocessor during the write cycle or read
from the counter during the read cycle. Data to and from
the counters and to the control registers is in binary format.
Each counter-timer consists.of three parts. The first is the
counter itself, a 16-bit down counter that is decremented on
the trailing edge of the clock input. The second is the jam
register that receives the data when the counter is written
to. The word in the control register determines when the
jam register value is placed into the counter. The third part
is the holding register that places the counter value on the
data bus when the counter is read.
Read Operation
Each counter has a holding register that is continuously
being updated by the counter and is accessed when the
counter is addressed during read cycles. Counter reads are
accomplished by halting the holding register and then
reading it, or by reading the holding register directly. If the
holding register is read directly, data will appearon the bus
if the counters are addressed with the RD line active.
However, if the clock decrements the counter between the
two read operations (most and least significant byte), an
inaccurate value will be read. To preclude this from
happening, writing a "1" into bit6 of the control register and
then addressing and reading the counter will result in a
stable reading. Thisoperation prevents the holding register
from being updated by the counter and does not affect the
counter's operation.
When the counter has decremented to zero, three events
occur. The first involves the common interrupt output pin
that, if enabled, becomes active low. The second is the
setting of a bit in the interrupt status register. This register
can be read to determine which counter-timer has timed
out. The third event is the logic change of the complemented
output pins.
In addition to the clock input used to decrement the
counter, a gate input is available to enable or initiate
operation. The counter-timers are independent and can
have different mode operations.
Write Operation
The counters and registers are separately addressable and
are programmed via the data bus when the chip is selected
with the TPB/WR pin active. Normal sequencing requires
that the counter jam register be loaded first with the
required value (most significant and least significant byte
The interrupt status register is read by addressing either
control register with the RD line active. A "1" in bit 7
indicates Timer A has timed out and a "1" in bit 6 indicates
Timer B has timed out. Bits 0-5 are zeros.
Control Register
J.m
En.b'.
1=Enabled
Q=Oisabled
l=
~J t
G
1=Positive
(High)
O=Negatlve (Low)
Interrupt Enable
1=Enabled
Holding Register Control
1= Freeze Holding Register
O=Update Continuously
O=Dlsabled
Mode Select
001=Mode 1
010"Mode 2
·011=Mode 3
100=Mode 4
101=Mode 5
·Plus Bit 7=0
Slart/Stop Control
1=Start Counler
O=Stop Counter
Bits 0, 1 and 2 -
----'
Mode Selects-See Mode Timing Diagrams (Figs. 2, 3, 4, 5 and 6).
Bit 7
Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 -
Timeout
Timeout Strobe
Gate Controlled One Shot
Rate Generator
Variable-Duty Cycle
No Mode selected. Counter outputs unaffected.
Note: When selectin!l!..!!!0de, the timer outputs TAO and
TBO are set low, and TAO and fBO are set high. If bits 0,1
and 2 are all zero's when the control register is loaded, no
-
0
-
Blt2
0
0
0
1
1
Bit 1
0
1
1
0
0
Bit 0
1
0
1
0
1
0
0
0
mode is selected, and the counter-timer outputs are
unaffected. Issuing mode 6 will cause an indeterminate
condition of the counter, issuing mode 7 is equivalent to
issuing mode 5.
422 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1878, CDP1878C
Mode
Control Register
I xlxlxlxlxlol11 0 1
Ti meout Strobe
2
Gate Control
Selectable
High or Low Level
Enables Operation
BUS 7
BUSO
Mode 2:
Operation of this mode is the same as mode 1, except the
outputs will change for one clock period only and then
return to the condition of TXO high andTXO low, and the
counter is reloaded.
o
COUNTER VALUE
CLOCK
o
iVA
CONTROL
REGISTER
GATE
TXO
* WRITE
92CM-34629R2.
TO CONTROL REGISTER WITH
MODE SELECTS=O
Fig. 3 - Timeout strobe (mode 2) timing waveforms.
Mode
3
Control Register
Gate Controlled One Shot
lolxlxlxlxlol1111
BUS 7
Mode 3:
After t~e jam register is loaded with the required value, the
gate edge will initiate this mode. TXO will be set high, and
TXO will be set low. The clock will decrement the counter.
When zero is reached, TXO will go low and TXO will be
high, and the interrupt output will be set low. The counter is
COUNTER VALUE
Gate Control
Selectable
JPositive or Negative
L O i n g Edge Initiates
Operation
BUS 0
retriggerable: While the counter is decrementing, a gate
edge or write to the control register with the jam-enable bit
high, will load the counter with the jam register value and
restart the one-shot operation.
o
2
CLOCK
m
CONTROL
REGISTER
GATE
TXO
92CM-34630R2
Fig. 4 - Gate controlled one-shot (mode 3) timing waveforms.
424 _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1878, CDP1878C
Setting the Control "egllter
Function Pin Definition
The following wlli Illustrate a counter write and subsequent
reads that places stable, accurate values on the data bus
from the counter-timer.
DB7-DBO-B-blt bidirectional bus used to transfer binary
Information between the microprocessor and the dual
counter-timer.
VDD, VsS-Power and ground for device.
AO, A1, and A2-AddreBseB used to select counters or
registers.
TPB/WFi, AD-Directional signals that determine whether
data will be placed on the bus from a counter or the
interrupt status register (FIl5 active) (memory mapped), or
data on the bus will be placed into acounter or control
register (TPB/WR active). The following connections are
required between the microprocessor and the countertimer in the CDP1BOO-serles Input/output mapping mode.
Counter-Timer
Mlcroproc..lor
MRD
AD
TPB
TPB/WR
TPA
TPA
Address Lines
N Lines
The counter Is addressed and the required values are
loaded with a write operation. The control register is
addressed next and loaded with B9H.
BUS?
11
I
II
11 11 11
0
J1
LOld counler with
..11m reg'I'"
Holding regll'er conttnuDUllv
updated by counte,
BUSO
I I 11 I
0
0
T.:
onlrOI Rogloler'BtH
Mode 1 1,llclad
POllllv. glt, enabling
required
Interrupt output enabled
Counter
.t.rt
and I-O/MEM to VDD.
During an output instruction, data from the memQ.!Y Is
strobed into the counter-timer during TPB when
is
active, and latched on TPB's trailing edge. Data is read from
is not active between the
the counter-timer when
trailing edges of TPA and TPB. (See Figs. 10, 11, and 12.)
m:r
The counter will now decrement with each Input clock pulse
while the gate Is valid. Assuming the counter has not
decremented to zero and its value Is to be read without
affecting the counter's operation, a write to the control
register is performed. 78H is loaded into the control
register.
Busa
BUS 7
I
0
11
1, l' I I I I I
1
t1
0
0
0
T l o o n ' , O I , e9 1,le'.7BH
Counter value
unattected
Unchanged
I
Counler outputs unaffected
Freeze holding regllter
The counter is addressed and read operations are performed.
mr
TACL, TBCL-Clocks used to decrement the counter.
TAG, TBG-Gate inputs used to control counter.
TAO, TAC)-Complemented outputs of Timer A.
TBO, fi'O-Complemented outputs of Timer B.
TR't-Common interrupt output. Active when counter
decrements to zero.
RESET-Active low s~ that resets counter outputs
(TAO, TBO low, TAO, TBO high). The Interrupt output Is
set higtLand the status register is cleared.
I-O/MEM-Tied high in CDP1BOO-series input/output mode,
otherwise tied low.
TPA-Tied to TPA ofthe CDP1800-series microprocessors.
During memory mapping, it is used to latch the high order
address bit for the chip select. In the CDP1800 Input/output
mode, it Is used to gate the N lines. When the counter-timer
Is used with other microprocessors, or when the high order
address of the CDP1800-series microprocessors Is externally latched, It Is connected to VDD.
CS-An active high signal that enables the device.
426 ________________________ CMOS Microprocessors, Memories and Peripherals
CDP1878, CDP1878C
r~l
CLOCK
XTAL
4
CLEAR
/
"-
TPA
TPA
MRD
Rii
TP8
TPB/WR
ADDRESS
LINES
*- TAG GATE
TACL,TBCL
R'ESE'T
NO
AO
NI
AI
N2
A2
~
CDPI802
TAO
f---+
TAO
f--+
f--+
L - :t-0/MEt.;
MEMORY
f---+
TIMER
OUTPUTS
VDD - - CS
fNT
I N PUTS
TBG
:tNT
TBO
COUNTER-TIMER
OBO - DB7
~
~
DATA BUS
92C M- 34636
Fig. 10 - Typical CDP1802 input/output-mapped system.
TPA~~__________________________
N LINES
J
L
TPB/WR
DATA FROM MEMORY
TO COUNTER-TIMER
92C M- 34631
Fig. 11 - CDP1800-serles input/output-mapping timing waveforms with output instruction.
TPA
~OUTPUT
ORIVERS ENABLEO
ROJ
TPB/WR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _......rr--0UTPUT DRIVERS
N LINES
DISABLED
J
DATA FROM
COUNTER- TIMER
TO MEMORY
f-
------IL-_ _ _
VALID OATA
_ _ _ _ _--J
92CM- 34638
Fig. 12 - CDP1800-series Input/output-mappIng tImIng waveforms with input Instruction.
428 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1878, CDP1878C
DYNAMIC ELECTRICAL CHARACTERISTICS at T A=-40 to +850 C, VDD=5 V ± 5%,
Input t"t,=10 na; CL =50 pF and 1 nL Load
CHARACTERISTIC
Write Cycle Tlmea (a.. Fig. 14)
Address Setup to Write
tAS
Write Pulse Width
tWR
Data Setup to Write
tos
Address Hold after Write
tAH
Data Hold after Write
tWH
Chip Select Setup to TPA
tcs
150
150
200
50
50
50
-
-
-
ns
-
tTlme required by a limit device 10 allow for the indicated function.
"Typical values are for TA=25° C and nominal VDD.
TPA
ADDRESS/CHIP SELECT
I
--
I
r--
~tAH-
tcs
W
11\
i-- t AS
'II
JI\
tWR
V-
~
DATA TO COUNTER TIME R
w
/~
~tos-
Fig. 14 - Write cycle timing waveforms.
W
JI\
tWH
I--
92CM-34640
430 ______________ CMOS Microprocessors, Memories and Peripherals
CDP1879, CDP1879C-1
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VOO)
(Voltage referenced to Vss Terminal)
CDP1879 ....................................................................................................•.. -0.5 to +11 V
CDP1879C-1 ........................•........................................................................... -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ...................................................................... -0.5 to Voo +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ............................................................................... ±10 mA
POWER DISSIPATION PER PACKAGE (Po):
For TA ~ ·40 to +60° C (PACKAGE TYPE E) ................................................. , ......................... 500 mW
For TA ~ +60 to +85° C (PACKAGE TYPE E) .. "' ......................................... Derate Linearly at 12 mW;oC to 200 mW
For TA ~ -55 to +100°C (PACKAGE TYPE D) .......................................................................... 500 mW
For TA ~ +100 to +125°C (PACKAGE TYPE D) .......................................... Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For TA ~ FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ................................................ 40 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE D, H ..................................................................................... , ... -55 to +125°C
PACKAGE TYPE E .............................................................................................-40 to +85°C
STORAGE TEMPERATURE RANGE (Tstg) ....................................................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max.
. ................................................ +265°C
OPERATING CONDITIONS at T A =Full Package-Temperature Range, unless otherwise noted.
For maximum reliability, operating conditions should be selected so that operation Is always within the following ranges:
LIMITS
CHARACTERISTIC
DC Operating Voltage Range
Input Voltage Range
DC Standby (Timekeeping) Voltage'
TA = -40 0 to +85 0 ct
TA - 0° to +70°C
Clock Input Rise or Fall Time
¥oo = 5 V
Voo-10V
CDP1879
Min.
4
Vss
Max.
10.5
Voo
CDP1879C-1
Min.
Max.
6.5
4
Vss
Voo
UNITS
V
VSTBY
3
-
3
-
2.5
-
2.5
-
-
10
1
-
10
V
t"t,
-
'Timekeeping function only, no READ/WRITE accesses, 32-kHz external frequency source only,
no crystal operation.
tSee Standby (Timekeeping) Voltage Operation, Page 11.
-
/is
432 _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1879, CDP1879C-1
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85·C VDD
± 5'10, Excapt. noted
CONDITIONS
CHARACTERISTIC
Quiescent Device Current
Output Low Drive (Sink)
Current, Data Bus & INT
VDD
(V)
0,5
5
0, 10
10
0,5
0, 10
5
10
1.B
3.6
0, 5
5
0, 10
10
-1.1
-2.6
5
10
0.6
1.2
1.4
5
10
-1.1
-2.6
-2.3
-4.4
5
0.2
0.9
10
0.4
-0.15
2
-0.4
-0.3
-0.7
0
0.1
0,10
10
5
10
0
0.1
0, 5
5
4.9
5
10
-
100
0.4
0.5
Output High Drive (Source)
Current, Data Bus &"'iN'f
IOH
4.6
9.5
Output Low Drive (Sink)
0.4
IOL
0.5
0, 5
0,10
Output High Drive (Source)
Current Clock Out
IOH
4.6
9.5
0, 5
10
Output Low Drive (Sink)
Current, Xi'AI. Out
0.4
Current, Clock Out
IOL
Output High Drive (Source)
Current ffi[ Out
Output Voltage
Low-Level
VOL;
Output Voltage
VOH;
Input Low Voltage
VIL
Input High Voltage
VIH
I nput Leakage Current
liN
3-State Output
lOUT
Leakage Current
Operating Current'
External Clock
32 kHz
1 MHz
2 MHz
-
1
200
-
9.9
0.5,9.5
0.5,4.5
0.5,9.5
Any
Input
-
5
10
-
0,10
5
10
5
10
0,5
0,5
5
0, 10
0, 10
10
-
-
0, 5
-
0.Q1
0.15
5
-
0.2
1
0.35
1.5
0.7
0.03
0.4
2
0.25
2
O.B
1.6
3
4.5
0.1
0.25
0.3
0.5
0.4
0.6
0.6
O.B
5
-
10
2 MHz
4 MHz
-
1 MHz
2 MHz
-
4 MHz
-
-
-
"Typical values are for TA = 25'C and nominal Voo.
:i:IOL = IOH = 1 /lA.
-
-
-
5
-
CIN
3
10
5
5
5
5
10
10
10
5
10
3.5
7
-
-
Min.
-1.1
-
-
-
-4.4
-
1.5
2 MHz
-
4
7
-2.3
-
-
tr,tf
50
10
32 kHz
1 MHz
COUT
MIx.
0.Q1
-
5
10
10
Input Capacitance
Typ.-
-
0,10
-:
32 kHz
1 MHz
Min.
0.5,4.5
-
Output Capacitance
Maximum Clock Rise
and Fall Times
0, 5
5
4 MHz
4 MHz
XTAL Oscillator"
-
4.6
IOH
High Level
9.5
o
o5
o 10
o5
o 10
0.5
CDP1879C-1
CDP1879
VIN
(V)
Vo
(V)
IOL
LIMITS
-
-2.3
-
-
0.2
0.9
-
-
-0.15
-0.4
-
0
-
4.9
5
-
-
-
1.6
3
1.B
3.5
2
5
5
7.5
10
15
-
10
1
-2.3
-1.1
±1
-
-
-
±1
200
1.4
3.5
±2
MIx.
0.02
-
3
±1
Typ.-
0.6
-
-
UNITS
0.Q1
0.2
/lA
-
-
mA
0.1
1.5
±1
±1
V
/lA
0.15
1
0.35
0.7
1.5
-
-
2
-
mA
0.1
0.25
0.3
0.5
0.4
0.6
0.6
O.B
-
-
5
7.5
10
15
-
10
-
pF
iJS
'Operating current measured with clockout = 488.2 /lS and no load;
.. See Table III and Fig. 6 for oscillator circuit Information.
434 ______________ CMOS Microprocessors, Memories and Peripherals
CDP1879, CDP1879C-1
GENERAL OPERATION
The real-time clock contains seconds, minutes, and hours,
date and month counters that hold time of day/calendar
information (see Fig. 2). The frequency of an intrinsic
oscillator is divided down to supply a once-a-second signal
to the counter series string. The counters are separately
addressable and can be written to or read from.
The real-time clock contains seconds, minutes and hour
write-only alarm latches that store the alarm time (see Fig.
3). When the value of the alarm 'latches and counters are
equal, the interrupt output is activated. The interrupt output
can also be activated by a clock output transition. The clock
output is derived from the prescaler and counters and can
be one of 15 square-wave signals. The value in the readonly interrupt status register identifies the interrupt source.
Operational control of the real-time clock is determined by
the byte in a write-only control register. The B-bit value in
this register determines the correct divisor for the prescaler,
a data direction and alarm enable bit, clock output select,
and start/stop control (see Fig. 4).
Data transfer and addressing are accom'plisned In two
modes of operation, memory mapping and I/O mapping
using the CDP1BOO-series microprocessors. The mode is
selected by the level on an input pin. (I-O/MEM). Memory
mapping implies use of the address lines as chip selects and
address inputs using linear selection or partial or full
decoding methods. I/O mapping with the CDP1BOO-series
microprocessors involves use of the N line outputs in
conjunction with input and output instructions to transfer
data to and from memory.
ill
I
92CL·34913
A2
TPA
I.-O/M"EM
ADDRESS DECODE
AND
CONTROL LOGIC
TPB/Wff
CS
POWER DOWN
Fig. 2 • Functional diagram - time counters highlighted.
436 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1879, CDP1879C-1
VDD
0--
~
AD
AI
92CL-34915
A
TPA
J:-O/M!M
ADDRESS DECODE
AND
CONTROL LOGIC
TPB/WA"
cs
POWER DOWN
Fig. 4 - Functional diagram - control register highlighted.
ALARM AND INTERRUPT STATUS REGISTER (See Fig. 3)
The alarm circuit consists of 1) seconds, minutes and hour
alarm latches that hold the alarm time, 2) the outputs of the
seconds, minutes and hour counters, and 3) a comparator
that drives an interrupt output. The comparator senses the
counter and alarm latch values and activates the interrupt
output (active low) when they are equal.
The write-only alarm latches have the same addresses as
their comparable counters. Bit 3 in the control register
determines data direction to the latches or counters and
alarm enabling. For example, during a write cycle, if bit 3 in
the control register is a "1", addressing the seconds counter
or alarm latch will load the seconds alarm latch from the
data bus and will enable the alarm function. Conversely, if
bit 3 in the cot:1trol register is a "0", addressing the seconds
counter or alarm latch during a write cycle will place the
value on the data bus into the seconds counter and will
disable the alarm function. The interrupt output can be
activated by the alarm circuit or the clock output. When an
interrupt occurs, the upper two bits of the interrupt status
register identify the interrupt source. The interrupt status
register has the same address as the control ~ster.
Addressing the interrupt status register with the RD line
active will place these register bits on the data bus. Bits 0-5
are held low. A "1" in bit 6 represents a clock output
transition as the interrupt source. A "1" in bit 7 will identify
the alarm circuit as the interrupt source.
Activating the reset pin (active low) resets the hour latch to
"30" which prevents a match between alarm and time
registers during an initialization procedure. Activating the
reset pin or writing to the control register resets the
interrupt output (high) and clears the interrupt status
register.
438 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1879, CDP1879C-1
PIN FUNCTIONS
Voo, vss -
Power and ground for device.
DBO - DB7 - DATA BUS - 8-bit bidirectional bus that
transfers BCD data to and from the counters, latches and
registers.
AO, A1, A2 - Address inputs that select a counter, latch or
register to read from or write to.
TPA - Strobe input used to latch the value on the chip
select pin. CS is latched on the trailing edge of TPA. During
memory mapping, it is used to latch the high order address
bit used forthe chip select. When the real-time clock is used
with other microprocessors, or when the high order address
of the CDP1800 series microprocessor is externally latched,
it is connected to Vo~. In the input/output mode, it is used to
gate the N lines.
I-O/MEM - Tied low during memory mapping and high
when the input/output mode of the CDP1800 series
microprocessor is used.
RD, TPB/WR - DIRECTION SIGNALS - Active signals
that determine data direction flow. In the memory mapped
mode, data is ~ed on the bus from the counters or status
register when RD pin is active.
Data is transferred to a counter, latch orthe control register
when RD is high and TPB/WR is active and latched on the
trailing edge (low to high) of the TPB/WR signal.
In the input/output mode, data"'!!'placed on the bus from a
counter or status register when RD is not active between the
trailing edges ofTPAand TPB. Data on the bus is written to
a counter, latch, orthe control register during TPB when R5
is active and latched on TPB's trailing edge. The following
connections are required between the microprocessor and
real-time clock in the CDP1800 series 110 mode.
MICROPROCESSOR REAL-TIME CLOCK
MRD ................ RD
TPB ................. TPB/WR
TPA ............... , .TPA
N LINES ............. ADDRESS LINES
I-O/MEM ............ VDO
CS - CHIP SELECT - Used toenable ordisablethe inputs
and outputs. TPA is used to strobe and latch a positive level
on this pin to enable the device.
XTAL AND XTAL - The frequency of the internal oscillator
is determined by the value of the crystal connected to these
pins. "XTAL" may be driven directly by an external frequency
source.
CLOCK OUT -1 of 15 square wave frequencies will appear
at this pin when selected. During power down, this pin will
be placed low, and will be high during normal operation
when the clock is deselected.
POWER DOWN - POWER DOWN CONTROL - A low on
this pin will place the device in the power down mode.
INT - Interrupt Output - A low on this pin indicates an
active alarm time or high-to-Iow transition of the "clock out"
signal.
RESET - A low on this pin clears the status register and
places the interrupt output pin high.
FREQUENCY INPUT REQUIREMENTS
The Real-Time Clock operates with the following frequency
input sources:
1. An external crystal that is used with the on-board
oscillator. The oscillator is biased by a large feedback
resistor and oscillates at the crystal frequency (see Fig.
6, Table III).
2. An external frequency input that is supplied at the
XTAL input. XTAL is left open (see Fig. 5). A typical
external oscillator circuit is shown in Fig. 7 in section,
"Standby (Timekeeping) VOLTAGE OPERATION".
TABLE III - Typical OSCillator Circuit Parameters for Suggested OSCillator Circuit, see Fig. 6
PARAMETERS
R,
Co
C,
Rs
CL
Crystal Impedance
·CDP1879C-1 only.
4.197 MHz
22
39
5
2.097 MHz
22
39
5
1.049 MHz
22
39
5
-
-
-
-
-
-
73
200
200
32768 Hz·
22
39
5
200
91
50K (max.)
UNITS
Mn
pF
pF
Kn
pF
Q
440 _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1879, CDP1879C-1
STANDBY (TIMEKEEPING) VOLTAGE OPERATION (Cont'd)
VDD
cs
Fig. 8 - Standby (timekeeping) voltage- and timing-waveforms.
Fig. 9 - Typical standby (timekeeping) voltage vs. full-temperature range.
APPLICATIONS
A typical application forthis real-time clock is as a wake-up
control to a CPU to reduce total system power in intermittent-use systems. A hookup diagram illustrating this
feature is shown in Fig. 10. In this configuration, the alarm
and power-down features of the CDP1879 are utilized in the
control of the sleep and wake-up states of the CPU. A
typical shut-down/start-up sequence for this system could
proceed as follows:
1. The CPU has finished a current task and will be inactive
for the next six hours.
.
2. The CPU loads the CDP1879 alarm registers with the
desired wake-up time.
3. The CDP1800 Q output is set high, which stops the
CPU oscillator (as an alternative, in an NMOS system,
power to all components except the clock chip could be
shut off).
4. This Q output signal is received by the CDP1879 as a
power-down signal.
5. The CDP1879 tri-states the interrupt output pin.
6. The CDP1879 eventually times out, and sets an alarm
by driving the TNf output low.
7. The alarm signal resets the CPU (to avoid oscillator
start-up problems) and flags the processor for a warmstart routine.
8. The CPU, once into its normal software sequence,
writes to the CDP1879 control register to reset the
interrupt request.
N0r---------------~
NI
AI
r---------------~A2
CDPl800
COPI8?9
14----"----------.,
ill
tltCS-14111RI
Fig. 10 - CPU wake-up circuit using the CDP1879 real-time clock.
442 ______________ CMOS
Micropr~ssors,
Memories and Peripherals
CDP1879, CDP1879C-1
r
APPLICATIONS (Conl'd)
O]
XTAL. JlTA(
CLOCK
RESET OUT
mAR
<
TPA
TPA
MRD
R1i
TPB
TPB/Wl'I
INTERRUPT
ADDRESS
LINES
-
INTERRUPT
NO
AO
NI
AI
N2
A2
:EO/~
CS
~VDO
CDPle79
CDPIB02
MEMORY
OBO-DB7
/\
~ ~
M
92CM~
3490&
Fig. 14 - Typical CDP1802 input/output-mapped system.
TPA
N LINES
~___________________________
J
L
TPB/WR
DATA FROM MEMORY
TO REAL TIME CLOCK - - - - , /
~~-----------~
92CM- 34906
Fig. 15 - CDP1800-serles Input/output-mapping timing waveforms with output instruction.
TPA
~OUTPUT
DRIVERS ENABLED
.J1r--
TPB/WR _______________________
N LINES
OUTPUT DRIVER,S
DISABL ED
J
DATA FROM REAL TIME
CLOCK TO MEMORY
I-
------I1...-.._
VALID DATA
_ _--'
92CM-34807
Fig. 16 - CDP1800-ser/es input/output-mapping timing waveforms with input Instruction.
444 _______________ CMOS Microprocessors, Memories and Peripherals
CDP1879, CDP1879C-1
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = -40 to +85 0 C,
Input tr,tf =10 ns, CL =50 pF
LIMITS
CHARACTERISTIC
Write Cycle Times (see Fig. 18)
Address Setup to Write
tAS
Write Pulse Width
tWR
Data Setup to Write
tDS
Address Hold after Write
tAH
Data Hold after Write
tWH
Chip Select Setup to TPA
tcs
CDP1879C-1
CDP1879
VDD
(V)
Mln.t
Max.
Mln.t
Max.
5
10
5
10
5
10
5
10
5
10
5
10
225
110
150
70
65
30
0
0
150
80
50
30
-
225
150
65
-
-
0
150
50
-
-
-
-
-
-
tTime required by a limit device to allow for the indicated function.
TPA
ADDRESS/CHIP SELECT
I
l
--
I - - - t cs
- t AH -
\f
\V
11\
/\
-tAS
tWR
f-
~
DATA TO REAL TIME CLO CK
/
\I
\1
/\
/\
f4-- t D S Fig. 1B - Write-cycle timing waveforms.
t WH
---
92CM- 34908
UNITS
ns
446 ______________ CMOS Microprocessors, Memories and Peripherals
CDP1881, CDP1881C, CDP1882, CDP1882C
OPERATING CONDITIONS at TA = Full Package-Temperature Range.
For maximum rellbillty, operating conditions should be selected 80 that operation Is always within the following ranges:
LIMITS
CHARACTERISTIC-
CDP1881, CDP1882
Min.
Max.
10.5
4
6.5
Voo
Vss
Voo
Min.
Max.
4
Vss
DC Operating Voltage Range
CDP1881C, CDP1882C
V
Input Voltage Range
STATIC ELECTRICAL CHARACTERISTICS at TA
= -40 to +85°C, Voo ± 5%, Except as noted
CONDITIONS
LIMITS
CDP1881
CDP1882
CHARACTERISTIC
VO
(V)
Quiescent Device
Current
Input Capacitance
Output Capacitance
0,5
5
-
0,10
10
5
50
3.2
pA
3.2
-
1.6
6.4
-
-
4.6
0,5
5
-1.15
-2.3
-
-1.15
-2.3
-
9.5
0, 10
10
-2.3
-4.6
-
-
-
-
-
0,5
5
-
0
0.1
0
0.1
-
0, 10
10
-
0
0.1
-
-
-
0,5
5
4.9
5
4.9
5
0,10
10
9.9
10
-
-
-
5
-
-
1.5
-
1.5
1,9
-
-
10
-
-
3
-
-
5
3.5
-
-
3.5
VIH
1,9
-
10
7
-
-
Any
0, 5
5
-
-
±1
-
-
-
0.5,4.5
±1"
liN
Input
0,10
10
-
-
±2
-
-
-
CIN
-
-
-
7.5
7.5
10
15
10
15
0,5
0,5
5
-
2
-
2
0, 10
0, 10
10
-
-
4
-
5
-
-
5
COUT
-
-
Voo = VOR
-
2
2.4
-
2
2.4
V
Voo = 2.4 V
-
0.01
1
-
0.5
5
pA
IOH
VOL:!:
VOH:!:
0.5,4.5
VIL
1001
VOR
Data Retention
Current
-
1.6
I!.
Minimum Data
Retention Voltage
10
100
3.2
Operating Device
Current
1
10
-
-
5
Input Leakage
Current
Max.
10
Input High
Voltage
Typ.-
Typ.-
0,5
Input Low
Voltage
Min.
Min.
0, 10
Output Voltage
High-Level
Max.
(V)
0.5
Output Voltage
Low-Level
UNITS
voo
0.4
IOL
Output High Drive
(Source) Current
VIN
(V)
CDP1881C
CDP1882C
-
100
Output Low Drive
(Sink) Current
UNITS
lOR
mA
V
-
-
'Typical values are for TA = 25° C.
:!:IOL = IOH = 1 pA.
aOperating current is measured at 200 kHz for VOO = 5 V and 400 kHz for Voo = 10 V, with outputs open circuil.
(Equivalent to typical CDP1800 system at 3.2 MHz, 5-V; and 6.4 MHz, 10-V).
pA
pF
mA
448 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1881, CDP1881C, CDP1882, CDP1882C
DYNAMIC ELECTRICAL CHARACTERISTICS al TA = ·40 10 +85 0 C, VDD
VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100 pF, See Fig. 3.
± 5%, Ir, II = 20 ns,
LIMITS
CDP1881, CDP1882
CHARACTERISTIC
VDD
(V)
Minimum Setup Time,
Memory Address to CLOCK,
tMACL
Minimum Hold Time,
tCLMA
Memory Address After CLOCK
Minimum CLOCK Pulse Width
MRD or MWR to Chip Select'
tMCS
CLOCK to Chip Select
tClCS
CLOCK to Address
Memory Address to Chip Select
35
-
10
35
8
25
-
5
-
8
25
-
25
8
25
-
8
-
-
50
75
-
50
75
25
40
-
75
150
-
75
-
-
150
45
100
-
-
-
-
75
150
-
75
150
40
100
-
-
-
100
175
175
125
-
100
65
-
-
100
175
-
100
175
10
-
5
.-
-
5
10
5
10
5
10
tMACS
Max.A
10
10
tClA
Typ ••
-
10
tCECS
Min.
-
5
Chip Enable to Chip Select
Max.A
5
5
Propagation Delay Times:
Typ .•
10
10
tCLCl
Min.
CDP1881C, CDP1882C UNITS
5
65
125
100
175
75
125
80
125
100
Memory Address to Address
tMAA
40
10
60
.TYPlcal values are for TA = 25 0 C.
AMaximum limits of minimum characteristics are the values above which all devices function.
'For the CDP1881 and CDP1881C types only.
175
-
-
80
125
-
-
VALID CHIP ENABLE
_'CEC~I
1.......1....,
-----,
I
.
I
'CECS
CSO,CSI,CS2,"C~S3;----------+---~~~----------------------------~-~~-----
- - - - -{
b
I
(0) CHIP ENABLE TO CHIP SELECT PROPAGATION DELAY
MRDORMWR
J'-,---9- - :
,b)"M'RD OR
MAQ- MA5
=tt
CLOC K
CSQ,
MWR
MAC~ I.
TO CHIP SELECT PROPAGATION DELAY (CDPI881,CDPI88IC ONLY)
.i--'F--LMA---
!-----JJ'---JI'---
~I------I
t ClCL
t CLCS
cs\ CS2,CS3 ----t-----'lI'----n-------------+-JI\-.....,I--...IJ'tClA
A 8 -All
(e) MEMORY ADDRESS
SETUP AND
HOLD TIME
92CM- 37295
Fig. 3 - COP188l and COP1882 timing waveforms.
ns
450 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1881, CDP1881C, CDP1882, CDP1882C
COPI8e2
LATCHI
DECODER
1TO
OTHER
\ CHI P SELECTS
....-----+1 CLK
CE
TPA
CDPISOO
SERIES
CPU
COMSIISA
2K 118
RAM
CDMe332
41< II B
ROM
MRli r---------<~CSII OE
Of
MWi'if-------i- - - - -r-------+iWE
DATA
SUS
Fig. 5 - COPIBOO-series system using the COPI882.
COPI882
LATCHI
DECODER
CS3
ill
CLK
~
~
rn
m I--
CE
MAOMAe
AS-All
I
WiT
CC"'R
fll
TPA
~J
rAOOR SS
iiiiii
Il
Aa-AII
.--
CS2
F>
s\Ts\ AO-A7
V
AO-A7
COM5332
4K'a
ROM
COMe332
41< ...
ROM
~
CiIlOi:
l
CSIIOlt
DATA
Jl
sUS
~7
D
0
Aa -All
ill
cOPlaOO
SERIES
CPU
ADDRESS SUS
A8 -All
m
m ~
~
~
~
A8-AII
AO-A7
COMe332
4< ,a
ROM
I---t CSi/OE
Jl
Fig. 6 - 16K-byte ROM systems using the COP1BB2.
~
j--v
.--
AO- A7
CDMS332
4k.8
ROM
CSI/Of
I
I
IICM-ITlIl
452 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1883, CDP1883C
OPERATING CONDITIONS at TA=Full Package-Temperature Range. For maximum reliability,
operating conditions should be selected so that operation is always within the following ranges:
LIMITS
Min.
DC Operating Voltage Range
Input Voltage Range
4
VSS
I
I
I
Max.
10.5
4
VDD
VSS
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, VDD
CHARACTERISTIC
Quiescent Device
Current
Output Low Drive
(Sink) Current
Output High Drive
(Source) Current
Output Voltage
Low-Level
Output Voltage
High-Level
100
IOL
IOH
VOL:j:
VoH:j:
Input Low Voltage
V'c
Input High Voltage
V,H
Input Leakage Current
Input Capacitance
Output Capacitance
Operating Device
Current
Minimum Data
Retention Voltage
Data Retention
Current
CDP1883C
Min.
1 Max.
CDP1883
CHARACTERISTIC
I,N
C 'N
C OUT
IOD1~
VOR
lOR
CONDITIONS
V,N
Vo
Voo
(V)
(V)
(V)
0,5
5
0, 10
10
0,5
0.4
5
0, 10
0.5
10
4.6
0,5
5
0, 10
10
9.5
0,5
5
0, 10
10
0,5
5
0, 10
10
0.5,4.5
5
0.5,9.5
10
0.5,4.5
5
0.5,9.5
10
0, 5
5
Any
Input 0, 10
10
-
I
I
6.5
± 5%, Except as Noted
LIMITS
CDP1883
CDP1883C
Min. Typ.· Max. Min. Typ.· Max.
-
-
1.6
3.2
-1.15
-2.3
4.9
9.9
3.5
7
1
10
3.2
6.4
-2.3
-4.6
0
0
5
10
-
-
5
10
10
100
0.1
0.1
5
-
50
-
1.6
-1.15
-
3.2
-2.3
-
-
0
0.1
-
-
4.9
5
1.5
3
-
-
-
-
1.5
-
-
3.5
-
-
-
±1
±2
7.5
15
2
4
-
-
-
-
-
-
0,5
0, 10
0, 5
0, 10
5
10
-
-
-
-
5
10
-
-
-
-
UNITS
/lA
mA
-
±1
7.5
15
2
-
V
/lA
pF
mA
Voo
= VOR
-
2
2.4
-
2
2.4
V
Voo
= 2.4 V
-
0.01
1
-
0.5
5
/lA
= 10H =1 /lA.
~Operating
V
VDD
"Typical values are for T. = 25° C.
:j:loc
UNITS
current is measured at 200 kHz for Voo = 5 V and 400 kHz for VOD = 10 V, with outputs open circuit.
454 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1883, CDP1883C
OYNAMIC ELECTRICAL CHARACTERISTICS at TA=-40 to +85°C, VOO
VIWO.7 Voo, VIL =0.3 Voo, CL =100 pF. See Fig. 2.
CHARACTERISTIC
VOO
(V)
Minimum Setup Time,
Memory Address to CLOCK
Minimum Hold Time,
Memory Address After CLOCK
tMACl
tClMA
Minimum CLOCK Pulse Width
telel
Propagation Delay Times:
Chip Enable to Chip Select
teEes
CLOCK to Chip Select
teles
CLOCK to Address,
telA
Memory Address to Chip Select
tMACS
Memory Address to Address
tMAA
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
± 5%, t r ,tr=20 ns,
LIMITS
COP1883
UNITS
COP1883C
Min. Typ•• Max.L!. Min. Typ •• Max.L!.
-
-
-
-
10
8
8
8
50
25
75
45
100
65
100
65
100
75
80
40
35
25
25
25
75
40
150
100
175
125
175
125
175
125
125
60
-
10
35
8
25
-
50
75
-
-
-
-
-
VALID CHIP ENABLES
-
150
-
175
100
175
100
175
80
125
-
-
-
-
-
J=-
CSO,CSI,CS2~S3----------~--~~r
__
------------------------~~--~~;r--~---(al CHIP ENABLE TO CHIP SELECT PROPAGATION DELAY
MAO-MAS
-~---~---~----------~~--~------
CLOCK
A8-AI2 ________________~----~~------------------~------~(b) MEMORY ADDRESS SETUP AND HOLD TIME
92CM-37284
Fig. 2 - CDP1883 timing waveforms.
-
100
d
~-J=--='CECS~-'CECS
-
75
oTypical values are for T. = 25° C.
L!.Maximum limits of minimum characteristics are the values above which ali devices function.
~
-
-
-
-
ns
456 ______________ CMOS Microprocessors, Memories and Peripherals
CDP6402, CDP6402C
VDD
NC
GND
RRD
TRC
EPE
CMOS Universal Asynchronous
Receiver/Transmitter (UART)
CLSI
CLS2
SBS
RBRe
RBR7
RBR6
RBR5
RBR4
RBR3
RBR2
RBR I
PI
CRL
TaRS
TSR?
TBRS
TBR5
TBR4
TBR3
TBR2
TaRI
PE
FE
OE
SFD
RRC
TRO
TR E
on
TBRl
TBRE
DR
RRI
MR
TOP VIEW
92CS-34!S!s2
TERMINAL ASSIGNMENT
Features:
• Low-power CMOS circuitry • Fully programmable with externally
7.5 mW typo at 3.2 MHz
selectable word length (5-8 bits),
(max. freq.) at VDD = 5 V
parity inhibit, even/odd parity, and
• Baud rate - DC to 200K bits/sec (max.)
1, 1.5,or 2 stop bits
• Operating-temperature range:
at VDD = 5 V, 85·C
DC to 400K bits/sec (max.)
(CDP6402D, CD) -55 to +125·
(CDP6402E, CE) -40 to +85· C
at VDD = 10 V, 85·C
• 4 V to 10.5 operation
• Replaces industry types IM6402
and HD6402
• Automatic data formatting and
status generation
The RCA CDP6402 and CDP6402C are silicon-gate CMOS
Universal Asynchronous Receiver/Transmitter (UART)
circuits for interfacing computers or microprocessors to
asynchronous serial data channels. They are designed to
provide the necessary formatting and control for interfacing
between serial and parallel data channels. The receiver
converts serial start, data, parity, and stop bits to parallel
data verifying proper code transmission, parity and stop
bits. The transmitter converts parallel data into serial form
and automatically adds start parity and stop bits.
The data word can be 5, 6, 7 or 8 bits in length. Parity may be
odd, even or inhibited. Stop bits can be 1, 1.5, or 2 (when
transmitting 5-bi! code).
TBR8 (MSBI
TBRI (LSBI
------
TRE4-r-------,
I
T1JlIl.--t-+
TRC
I
MULIPLEXER
I
I
'---------------++"RO
I
CLSI--L--~----~----.r-~-~~----------------------_+-SBS
CLS2
EPE
CRL
PI
MR
r--------------------~~+__4-RRI
~-------";'--RRD
SFD-,--,
DR
DE
TBRE
FE
PE
RBR8(MSB)
RBRI(LSBI
92CL-34!5!53
Fig. 1 - Functional block diagram.
File Number 1328
458 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6402, CDP6402C
Receiver Operation
DESCRIPTION OF OPERATION
Initialization and Controls
A positive pulse on the MASTER RESET (MR) input resets
the control, status, and receiver buffer registers, and sets
the serial output (TRO) High. Timing is generated from the
clock inputs RRC and TRCata frequency equal to 16times
the serial data bit rate. The RRC and TRC inputs may be
driven by a common clock, or may be driven independently
by two different clocks. The CONTROL REGISTER LOAD
(CRL) input is strobed to load control bits for PARITY
INHIBIT (PI), EVEN PARITY ENABLE (EPE), STOP BIT
SELECTS (SBS), and CHARACTER LENGTH SELECTS
(CLS1 and CLS2). These inputs may be hand wired to VSS
or VDD with CRL to VDD. When the initialization is
completed, the UART is ready for receiver andlor transmitter
operations.
Data is received in serial form at the RRI input. When no
data is being received, RRI input must remain high. The
data is clocked through the RRC. The clock rate is 16times
the data rate. Receiver timing is shown in Fig. 4.
BEGINNING OF FIRST STOP BIT
I
RRI
DATA
~
I
I---
I
8 CLOCK
CYCLES
RBRI-8 ,DE
~W
I
DR
FE ,PE
Transmitter Operation
A
The transmitter section accepts parallel data, formats it,
and transmits it in serial form (Fig. 2) on the TRO terminal.
-
~ 112CLOC K
CYCLE
92CS-34559RI
Fig. 4 - Receiver timing waveforms.
-Lr--,---,.---r--,.--r-'"T-r-...,If--ir-_,..,-r+
1_ (A) A low level on ORR clears the DR line. (B) During the
----,
ILSBI
IMSBI,G I
first stop bit data Is transferred from the receiver register to
! _ _
- LL_
the RBRegister. If the word is less than a bits, the unused
*IF ENABLED
PARITY
most significant bits will be a logic low. The output
character is right justified to the least significant bit RBR1. A
92CS- 345154
logic high on OE indicates overruns. An overrun occurs
when DR has not been cleared before the present character
Fig. 2 - Serial data format.
was transferred to the RBR. (C) 1/2 clock cycle later DR is
set to a logic high and FE is evaluated. A logiC high on FE
Transmittertiming is shown in Fig. 3. (A) Data is loaded into
indicates an invalid stop bit was received. A logic high on
the transmitter buffer register from the inputs TBR1 through
PE Indicates a parity error.
TBRa by a iogic low on the"f"Bm: input. Valid data must be
present at least tOT prior to, and tTD following, the rising
Start Bit Detection
edge of TB1it. If words less than a bits are used, only the
least significant bits are used. The character is right
The receiver uses a 16X clock for timing (Fig. 5). The start
justified into the least significant bit, TBR1. (B) The rising
bit could have occurred as much as one clock cycle before it
edge of 'fBA[ clears TBRE. One Hi to Lo transition of TRC
was detected, as indicated by the shaded portion. The
iater, data is transferred to the transmitter register and TRE
center of the start bit is defined as clock count 7 1/2. If the
is cleared. TBRE is reset to a logic High one Hi to Lo
receiver clock is a symmetrical square wave, the center of
transition after that.
the start bit will be located within ±1/2clockcycle, ±1/32 bit
or ±3.125%. The receiver begins searching for the next start
Output data is clocked by TRC. The clock rate Is 16 times
bit at 9 clocks into the first stop bit.
the data rate. (C) A second pulse on TBRL loads data into
the transmitter buffer register. Data transfer to the
COUNT 7112
transmitter register is delayed until transmission of the
DEFINED CENTER
current character is complete. (D) Data is automatically
OF START BI'T
transferred to the transmitter register and transmission of
that character begins.
5-8 DATA BITS
START BIT
~
1,1-I/20R 2 STOP BITS
.L
1""1_ _ _ _ _
I
_ _ _ _- - - ,
--L
L
CLOCK
82eS-3405B
Fig. 5 - Start bit timing waveforms.
A
o
B
92('':;
~~80b4
Fig. 3 - Transmitter timing waveforms.
END OF
LAST
STOP
BIT
460 ______________ CMOS Microprocessors, Memories and Peripherals
CDP6402, CDP6402C
Table II - Function Pin Definition (Confd)
PIN
23
24
25
26
27
28
29
30
31
32
33
SYMBOL
DESCRIPTION
TBAl
A low level on TRANSMITTER BUFFER
REGISTER lOAD transfers data from
inputs TBR1-TBR8 into the transmitter
buffer register. A low to high transition
on TBRl requests data transfer to the
transmitter register. If the transmitter
register is busy, transfer is automatically
delayed so that the two characters are
transmitted end to end.
TRE
A high level on TRANSMITTER
REGISTER EMPTY indicates completed
transmission of a character including
stop bits.
TRO
Character data, start data and stop bits
appear serially at the TRANSMITTER
REGISTER OUTPUT.
TBR1
Character data is loaded into the
TRANSMITTER BUFFER REGISTER via
inputs TBR1-TBR8. For character
formats less than 8-bits, the TBR8, 7,
and 6 Inputs are ignored corresponding
to the programmed word length.
TBR2
TBR3
TBR4
TBR5
See Pin 26 - TBR1
TBR6
TBR7
TBR8
1
PIN
34
35
36
37
38
39
40
SYMBOL
DESCRIPTION
CRl
A high level on CONTROL REGISTER
lOAD loads the control register.
PI"
A high level on PARITY INHIBIT inhibits
parity generation, parity checking and
forces PE output low.
SBS"
A high level on STOP BIT SELECT
selects 1.5 stop bits for a 5 character
format and 2 stop bits for other lengths.
ClS2" These inputs program the CHARACTER
lENGTH SELECTED. (CLS1 low CLS2
low 5-bits) (CLS1 high CLS210w 6-bits)
(ClS1 low CLS2 high 7-bits) (CLS1 high
CLS2 high 8-bits).
CLS1" See Pin 37 - CLS2
EPE"
When PI is low, a high level on EVEN
PARITY ENABLE generates and checks
even parity. A low level selects odd
parity.
TRC
The TRANSMITTER REGISTER
CLOCK is 16X the transmit data rate.
"See Table I (Control Word Function)
462 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6402, CDP6402C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA
V,H =0.7VDD, V,L =0.3 VDD, CL =100 pF
=-40 to +85°C, VDD ± 5%, tr, tf =20 ns,
LIMITS
CDP6402
CHARACTERISTIC t
Transmitter Timing (See Fig. 7)
I
CDP6402C
~er
Typ.-
5
10
250
125
310
155
250
310
5
10
100
75
125
100
100
125
I
Max. A
I
J
Typ. -
Max. A
Minimum Clock Period (TRC)
tcc
Minimum Pulse Width:
Clock Low Level
tCL
Clock High Level
tCH
5
10
100
75
125
100
100
125
TBRl
tTHTH
5
10
80
40
200
100
80
200
5
10
175
90
275
150
175
275
5
10
20
0
50
40
20
50
60
MI.!!!!!l!:!.m Setup Time:
TBRL to Clock
Data to TifFiL
tTHC
-
-
-
-
-
-
-
-
-
-
./"
tOT
Minimum Hold Time:
Data after TBRL /
5
10
40
20
60
30
40
tTD
300
150
450
225
300
450
tCD
5
10
tCT
5
10
330
100
400
150
330
400
tTTHR
5
10
200
100
300
150
200
300
tTTS
5
10
330
100
400
150
330
400
Propagation Delay Time:
Clock to Data Start Bit
Clock to TBRE
TBRL to TBRE
Clock to TRE
-
-
-
-
-
-
-
-
-
-
-
-Typical values for T A = 25° C and nominal VDD.
AMaximum limits of minimum characteristics are the values above which all devices function.
t All measurements are made at the 50% point of the transition except iri-state measurements.
** TRANSMITTER
SHIFT
REGISTER LOADED
TRC
I
I
I
I
' -____~.
I
I II
t- tTHTH-l
I-eo! i-Io-tCD
I
I I--i- I I
T B R l - - - - - - ' 1r--~I~I~I--------------------~R~--------~---------
I
:
-r )!-i
1/
CD
TRO------------~I---I~~lul____________________~----------~~S-T~~~
I
II.!
TBRE
tTTH~
II
fel-J
I
I
DATA BIT
!--ICT
~rtT-T-S~--------------~I-------------------
TRE--------------I~--;I
I
~----------------------~I~-----------------
.~tDT~ITD~
~ :~~~- ----~)ATA
*
,------------------:~--------------
If THE HOLDING REGISTER IS LOADED ON THE TRAiliNG EDGE OF TBRl
92CM-'4556
If THE TRANSMITTER SHIFT REGISTER,IF EMPTY,IS lOADED ON THE FIRST HIGH-TO-lOW TRAN¥WeN OF THE
~~~~~:I~~CI~~ca:~~Ss.t1N~~l ~~u~'s0fM'illt~DpUTb'8 ~FI6~RlmRTRAILING
Fig. 7· Transmitter timing waveforms.
EDGE OF
UNITS
AND
ns
464 _______________ CMOS Microprocessors, Memories and Peripherals
Product Preview
CDP65C51
VSS
28
R/W
eso
27
+2
cs;
RES
Rx e
•
5
XTLI
26
:urn
25
07
2'
23
06
05
XTL
7
22
D.
RTS
8
21
03
20
D2
us
TX D
OTR
10
I.
D1
DO
Rx D
RSO
RSI
"
18
12
17
13
I.
16
tiSlf
DCD
"
TOP VIEW
VDD
92CS-36774
TERMINAL ASSIGNMENT
CMOS Asynchronous Communications
Interface Adapter (ACIA)
Features:
• Compatible with 8-bit microprocessors
• Full duplex operation with buffered receiver
and transmitter
• Data set/modem control functions
• Internal baud rate generator with 15
programmable baud rates (50 to 19,200)
• Program-selectable internally or externally
controlled receiver rate
• Programmable word lengths, number of stop bits,
and parity bit generation and detection
• Programmable interrupt control
• Program reset
The RCA-CDP65C51 Asynchronous Communications Interface Adapter (ACIA) provides an easily implemented,
program controlled interface between 8-bit microprocessorbased systems and serial communication data sets and
modems.
The CDP65C51 has an internal baud rate generator. This
feature eliminates the need for multiple component support
circuits, a crystal being the only other part required. The
Transmitter baud rate can be selected under program
control to be either 1 of 15 different rates from 50 to 19,200
baud, orat 1/16times an external clock rate. The Receiver
baud rate may be selected under program control to be
either the Transmitter rate, or at 1/16 times the external
clock rate. The CDP65C51 has programmable word lengths
of 5, 6, 7, or 8 bits; even, odd, or no parity; 1, 1V2, or 2 stop
bits.
• Program-selectable serial echo mode
• Two chip selects
• 2 MHz or 1 MHz operation (CDP65C51-2, CDP65C51-1,
respectively)
• Single 3 V to 6 V power supply
• 28-pin plastic or ceramic (DIP or DIC)
• Full TTL compatibility
The Control Register controls the number of stop bits, word
length, receiver clock source and baud rate.
The Status Register indicates the states of the "iRQ, DSR,
and DCD lines, Transmitter and Receiver Data Registers,
and Overrun, Framing and Parity Error conditions.
The Transmitter and Receiver Data Registers are used for
temporary data storage by the CDP65C51 Transmit and
Receiver circuits.
The CDP65C51 is designed for maximum programmed
control from the CPU, to simplify hardware implementation.
Three separate registers permit the CPU to easily select the
CDP65C51 operating modes and data checking parameters
and determine operational status.
The CDP65C51-1 and CDP65C51-2 are capable of interfaci ng with microprocessors with cycle ti mes of 1 M Hz and
2 M Hz, respectively.
The Command Register controls parity, receiver echo
mode, transmitter interrupt control, the state of the RTS
line, receiver interrupt control, and the state of the DTR line.
The CDP65C51 is supplied in 28-lead, hermetic, dual-inline side-brazed ceramic (D suffix) and in 28-lead, dual-inline plastic (E suffix) packages.
File Number
1470
466 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP65C51
CDP65C51 INTERFACE REQUIREMENTS
This section describes the interface requirements for the
CDP65C51 ACIA. Fig. 1 is the Interface Diagram and the
Terminal Diagram shows the pin-out configuration for the
CDP65C51.
00-07 (Data Bus) (18-25)
The DO-D7 pins are the eight data lines used to transfer data
between the processor and the CDP65C51. These lines are
bi-directional and are normally high-impedance except
during Read cycles when the CDP65C51 is selected.
CSO, Cs1 (Chip Selects) (2,3)
CTs
00-07
TxO
iffi>
l5SR
The two chip select inputs are normally connected to the
processor address lines either directly orthrough decoders.
The CDP65C51 is selected when CSO is high and CS1 is
low.
RSO, RS1 (Register Selects) (13,14)
The two register select lines are normally connected to the
processor address lines to allow the processor to select the
various CDP65C51 internal registers. The following table
shows the internal register select coding.
TABLE I
Rxe
XTLI
XTLO
92CM-3S8S0
Fig. 1 - CDP65C51 interface diagram.
MICROPROCESSOR INTERFACE
SIGNAL DESCRIPTION
RES (Reset) (4)
During system initialization a low on the RES input will
cause a hardware reset to occur. The Command Register
and the Control Register will be cleared. The Status
Register will be cleared with the exception of the indications
of Data Set Ready and Data Carrier Detect, which are
externally controlled by the ~ and DCD lines, and the
transmitter Empty bit, which will be set.
t{J2 (Input Clock) (27)
The input clock is the system t{J2 clock and is used to clock
all data transfers between the system microprocessor and
the CDP65C51.
R/W (Read/Write) (28)
The R/W input, generated by the microprocessor, Is u~d to
control the direction of data transfers. A high on the R/W pin
allows the processor to read the data supplied by the
££p65C51, a low allows a write to the CDP65C51.
IRQ (Interrupt Request) (26)
The iRQ pin Is an interrupt output from the interrupt control
logic. It is an open drain output,.J1!.I'mitting several devices
to be connected to the common 1RO microprocessor input.
Normally a high level, 'iRQ goes low when an interrupt
occurs.
RS1
0
RSO
0
0
1
1
1
0
1
Write
Read
Receiver Data
Transmit Data
Register
R~ister
Programmed Reset
Status Register
(Data is "Don't
Care")
Command Register
Control Register
Only the Command and Control registers are read/write.
The Programmed Reset operation does not cause any data
transfer, but is used to clear bits 4 through 0 in the
Command register and bit 2 in the Status register. The
Control Register is unchanged by a Programmed Reset. It
should be noted that the Progra'!J..l:!l£..d Reset is slightly
different from the Hardware Reset (RES); these differences
are shown in Figs. 3, 4 and 5.
ACIAIMODEM INTERFACE
SIGNAL DESCRIPTION
XTLI, XTLO (Crystal Pins) (6,7)
These pins are normally directly connected to the external
crystal (1.8432 MHz) used to derive the various baud rates
(see "Generation of Non-Standard Baud Rates"). Alternatively, an externally generated clock may be used to drive
the XTLI pin, in which case the XTLO pin must float. XTLI is
the input pin for the transmit clock.
TxD (Transmit Data) (10)
The TxD output line is used to transfer serial NRZ
(nonreturn-to-zero) data to the modem. The LSB (least
significant bit) of the Transmit Data Register is the first data
bit transmitted and the rate of data transmission is
determined by the baud rate selected or under control of an
external clock. This selection is made by programming the
Control Register.
RxD (Receive Data) (12)
The RxD input line is used to transfer serial NRZ data into
the ACIA from the modem, LSB first. The receiver data rate
is either the programmed baud rate or under the control of
an externally generated receiver clock. The selection is
made by programming the Control Register.
468 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP65C51
CDP65C51 INTERNAL ORGANIZATION (Cont'd)
Receiver Data Register Full (Bit 3)
TIMING AND CONTROL
The Timing and Control logic controls the timing of data
transfers on the internal data bus and the registers, the Data
Bus Buffer, and the microprocessor data bus, and the
hardware reset features.
Timing is controlled by the system f/)2 clock input. The chip
will perform data transfers to or from the microcomputer
data bus during the f/)2 high period when selected.
All registers will be ir:!.W.!!ized by the Timing and Control
Logicwhen the Reset (RES) line goes low. See the individual
register description forthe state of the registers following a
hardware reset.
TRANSMITTER AND RECEIVER
DATA REGISTERS
These registers are used astemporary data storage for the
CDP65C51 Transmit and Receive Circuits. Both the Transmitter and Receiver are selected by a Register Select 0
(RSO) and Register Select 1 (RS1) low condition. The
Read/Write line determines which actually uses the internal
data bus; the Transmitter Data Register is write only and the
Receiver Data Register is read only.
Bit 0 is the first bit to be transmitted from the Transmitter
Data Register (least significant bit first). The higher order
bits follow in order. Unused bits in this register are "don't
care".
This bit goes to a "1" when the CDP65C51 transfers data
from the Receiver Shift Register to the Receiver Data
Register, and goes to a "0" when the processor reads the
Receiver Data Register.
Transmitter Data Register Empty (Bit 4)
This bit goes to a "1" when the CDP65C51 transfers data
from the Transmitter Data Register to the Transmitter Shift
Register, and goes to a "0" when the processor writes new
data onto the Transmitter Data Register.
Data Carrier Detect (Bit 5) and
Data Set Ready (Bit 6)
These bits reflect the levels of the DCD and DSR inputs to
the CDP65C51. A "0" indicates a low level (true condition)
and a "1" indicates a high (false). Whenever either of these
inputs change state, an immediate processor interrupt
occurs, unless the CDP65C51 is disabled (bit 0 of the
Command Register is a "0"). When the interrupt occurs, the
status bits will indicate the levels of the inputs immediately
after the change of state occurred. Subsequent level
changes will not affect the status bits until the Status
Register is interrogated by the processor. At that time,
another interrupt will immediately occur and the status bits
will reflect the new input levels.
Framing Error (Bit 1), Overrun (2), and
Parity Error (Bit 0)
The Receiver Data Register holds the first received data bit
in bit 0 (least significant bit first). Unused high-order bits
are "0". Parity bits are not contained in the Receiver Data
Register. They are stripped off after being used for parity
checking.
None of these bits causes a processor interrupt to occur,
but they are normally cheCked at the time the Receiver Data
Register is read so that the validity of the data can be
verified.
STATUS REGISTER
This bit goes to a "0" when the Status Register has been
read by the processor, and goes to a "1" whenever any kind
of interrupt occurs.
Fig. 3 indicates the format of the CDP65C51 Status Register.
A description of each status bit follows.
Interrupt (Bit 7)
76543210
I II I I I I I I
CONTROL REGISTER
L
PARITY ERROR-
D - NO PARITY ERROR
1 - PARITY ERROR DETECTED
FRAMING ERROR·
D - NO FRAMING ERROR
1 - FRAMING ERROR DETECTED
-
OVERRUN·
0- NO OVERRUN
1 - OVERRUN HAS OCCURRED
RECEIVER DATA REGISTER FULL
0- NOT FULL
1 - FULL
TRANSMITTER DATA REGISTER EMPTY
0- NOT EMPTY
1 - EMPTY
DATA CARRIER DETECT lOCo)
0- 0C0 LOW (DETECT)
1 - ireli HIGH (NOT DETECTED)
DATA SET READY (DSR)
~:
g:= ~?:H(~NE~f~EAOY)
INTERRUPT (ilia)
0- NO INTERRUPT
1 - INTERRUPT HAS OCCURRED
*NO INTERRUPTS OCCURS FOR
THESE CONDITIONS
76543210
1-0 1-1-1'
1 0 I 0 I 0 10 IHARDWARE RESET
- - - - a - PROGRAM RESET
92CM-36783
Fig. 3 - Status register format
The Control Register selects the desired baud rate, frequency source, word length, and the number of stop bits.
Selected Baud Rate (Bits 0,1,2,3)
These bits, set by the processor, select the Transmitter
baud rate, which can be at 1/16 an external clock rate or one
of 15 other rates controlled by the internal .baud rate
generator as shown in Fig. 4.
Receiver Clock Source (Bit 4)
This bit controls the clock source to the Receiver. A "0"
causes the Receiver to operate at a baud rate of 1/16 an
external clock. A "1" causes the Receiver to operate at the
same baud rate as is selected forthe transmitter as shown in
Fig. 4.
Word Length (Bits 5,6)
These bits determine the word length to be used (5,6,7 or 8
bits). Fig. 4 shows the configuration for each number of bits
desired;
Stop Bit Number (Bit 7)
This bit determines the number of stop bits used. A "0"
always indicates one stop bit. A "1" indicates 1V, stop bits if
the word length is 5 with no parity selected, 1 stop bit if the
word length is 8 with parity selected, and 2 stop bits in all
other configurations.
470 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP65C51
CDP65C51 INTERNAL ORGANIZATION (Cont'd)
TRANSMITTER AND RECEIVER
Bits 0-3 of the Control Register select divisor used to
generate the baud rate for the Transmitter. If the Receiver
clock is to use the same baud rate as the transmitter, then
RxC becomes an output and can be used to slave other
circuits to the CDP65C51. Fig. 6 shows the transmitter and
Receiver layout.
.....-
......- - R x O
~-----------------------RxC
XTLl
XTLO
TxO
92CS-36791
Fig. 6 - Transmitter receiver clock circuits.
CDP65C51 OPERATION
TRANSMITTER AND RECEIVER OPERATION
reads the Status Register of the CDP65C51, the interrupt is
cleared. The processor must then identify that the Transmit
Data Register is ready to be loaded and must then load it
with the next data word. This must occur before the end of
the Stop Bit, otherwise a continuous "MARK" will be
transmitted.
Continuous Data Transmit (Fig. 7)
In the normal operating mode, the processor interrupt
(iRQ) is used to signal when the CDP65C51 is ready to
accept the next data word to be transmitted. This interrupt
occurs at the beginning of the Start Bit. When the processor
CHAR#n
CHAR#n+1
CHAR#n+2
/r--------LI---------'/r------~IL-------~,/
,......-r_;:.ST~O::;,P
I
STOP
CHAR#n+3
,/
I
STOP
,
STOP
hol GGT-GE] I GGr GG I GGLGEl I GELGEJ L
iRa
START
START
I
I
I
I
I
I
un
fi~:?~~RDATA
START
START
I
)
I
i
I
I
I
I
L
LJU
LllJITI',-===:;::=::7j/LJI]
REGISTER EMPTY)
I
i
I
I
l r::g~:.::::~.
IN THIS TIME
INTERVAL; OTHERWISE,
CONTINUOUS "MARK"
IS TRANSMITTED
92CM- 36792
PROCESSOR READS STATUS
REGISTER, CAUSES iiiQ
TO CLEAR
Fig. 7 - Continuous data transmit.
data word. This occurs at about the 8/16 pOint through the
Stop Bit. The processor must read the Status Register and
read the data word before the next interrupt, otherwise the
Overrun condition occurs.
Continuous Data Receive (Fig. 8)
Similar to the above case, the normal mode is to generate a
processor interrupt when the CDP65C51 has received a full
CHAR#n
CHAR#n+1
CHAR #n+2
/ r - - - - - - - - ' - - - - - - -___, /
..,..-.__-is::.:T~O;:;,P
"xO
l [%EL8iJ I
STOP
:
I
I
START
;-ml~~i:~~~
PROCESSOR
~':.T~~:~/%~~gRS
,/
STOP
I f"%GI-GE] I
[%GJ1~G
I START
START
CHAR#n+3
,/
I
:
I
I
LmI'T1----------1L
92CM-36793
PROCESSOR READS STATUS
REGISTER, CAuses
TO CLEAR
nm
Fig. 8 - Continuous data receive.
L
GGTJ~EJ
1 START
OVERRUN OCCURS
LAST STOP BIT.
PARITY, OVERRUN,
AND FRAMING ERROR
UPDATED, ALSO
"
STOP
472 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP65C51
CDP65C51 OPERATION (Cont'd)
word is not transferred to the Receiver Data Register, but
the Overrun status bit is set. Thus, the Data Register will
See for normal Receiver operation. If the processor does
contain the last valid data word received and all following
not read the Receiver d(lta Register in the allocated time,
data is lost.
then, when the following interrupt occurs, the new data
Effect of Overrun on Receiver (Fig. 11)
CHAR#n
~
CHAR#n+1
V
I
STOP
STOP
I~
iRll
[%GI~GOEJ
LJl1'
~
STOP
GE1]::~;EJ
I
I~
CHAR#n+3
' - . / r - - - -L1- -
I
STOP
GErGEl I
RxoD
CHAR#n+2
~/
I
~
GFIH
I
I~
/
-------' =:~g;SSOR
1
PROCESSOR
INTERRUPT
STATUS
~~~AR:~::~~~R
REGISTER
FUll
~OVERRUN BIT seT IN
STATUS REGISTER
92CM-36796
Fig. 11 - Effect of overrun on receiver.
Echo Mode Timing (Fig. 12)
In Echo Mode. the TxD line re-transmits the data on the RxD
line, delayed by V, of the bit time.
RxO nSTARTI
BO
lui
I B,
BN
I p ISTOPISTARTI
BO
I
B,
I
I BN I p ISTOPISTARTR
\\\\ \\ \\\ \\\\\
TxO
_-'
BN
I p ISTOplSTARTI
BO
I B, I ~~ I BN I p ISTOPISTARTR
92CM~36797
Fig. 12 - Echo mode timing.
Effect of CTS on Echo Mode Operation (Fig. 13)
See "Effect of
on Transmitter" for the effect of CTs on
the Transmitter. Receiver operation is unaffected by CTS,
so, in Echo Mode, the Transmitter is affected in the same
m
way as "Effects of CTS on Transmitter". In this case,
however, the processor interrupts signify that the Receiver
Data Register is full, so the processor has no way of
knowing that the Transmitter has ceased to echo.
CHAR#n
CHAR#n+1
CHAR#n+2
CHAR#n+3
~/~--------LI______~'\~---LI-----~,/~--------LI------~,/~-------LI_ _ __
STOP
STOP
STOP
STOP
G[B:-[:E;EJ I [s;G[Gf] I GGLEL:J I
Rx D]l
GF[H
I~
I~
I~
I~
LJO
LJI]
LUJ
lJU~--
~
NOT·CLEAR·TO·SENO
I
TxO
START
I
STOP
STOP
":fLEE[ I
BN
I
p
I I I I
BO
B,
B211
LRTffi
)
GOES TO
"FALSE" CONDITION
I
NORMAL
-
RECEIVER DATA
REGISTER FULL
INTERRUPTS
Fig. 13 - Effect of CTS on echo mode.
92CM-36798
474 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP65C51
CDP65C51 OPERATION (Cont'd)
indicate this condition via the Status Register.
DCD is a modem output used to indicate the status of the
Once such a change of state occurs, subsequent transitions
carrier-frequency-detection circuit of the modem. This line
will not cause interrupts or changes in the Status Register
goes high for a loss of carrier. Normally, when this occurs,
until the first interrupt is serviced. When the Status Register
the modem will stop transmitting data (RxD on the
is read by the processor, the CDP65C51 automatically
CDP65C51 some time later. The CDP65C51 will cause a
checks the level of the DCD line, and if it has changed,
processor interrupt whenever DCD changes state and will
another interrupt occurs .
Effect of DCD on Receiver (Fig. 16)
..-~_;:-ST:.=O""P
R'D.ol·,I··I~EEJ
,.,---,_,,_-=C;:O;,;.NT;,.:I:.:;NU:.;O;,:U.:.S·.;:'M:::A::,:R::,K'_'_ _"-TST~O~P
I 1·01·,1··11
START
I MODEM I
I- MODEM 1
r- 1
!
Ir-----!.------11
DELAY
Dffii
1
t
L
~I--~------~
urLlIJfC'===::;:\===::7j/LlJ]
:~J1~EAisOR
INTERRUPT
~_~
START
DELAY
------+-~I
IRQ
r:-r:-r_STOP
rJ I
1
AS LONG AS
PROCESSOR
~7,TREeatiPT
GOING HIGH
~F~R~~EHR
INTERRUPTS
~~~L R~g~~~ER
PROCESSOR
INTERRUPT
FOR ~
GOING LOW
i
I
III
III
t
NO INTERRUPT
WILL OCCUR
HERE, SINCE
RECEIVER IS NOT
ENABLED UNTIL
FIRST START BIT
DETECTED
PROCESSOR
INTERRUPT
FOR
RECEIVER
DATA
92CM- 36786
Fig. 16 - Effect of DCD on receiver.
Timing with 1'1. Stop Bits (Fig. 17)
/L
L __ 1U
5-bit data words with no parity bit. In this case, the
processor interrupt for Receiver Data Register FlIli occurs
in halfway through the trailing half-Stop Bit.
It is possible to select 1'h Stop Bits, but this occurs only for
CHAR#n+1
I
RxD
L
LJl]
t
PROCESSOR INTERRUPT
OCCURS HALFWAV
THROUGHTTHE 1/2
STOP .,T
92CM~
36787
Fig. 17 - Timing with 1-112 stop bits.
Tranamlt Contlnuou. "BREAK" (Fig. 18)
This mode is selected via the CDP65C51 Command Register
and causes the Transmitter to send continuous "BREAK"
characters after both the transmitter and transmitter-holding
registers have been emptied.
At least one full "BREAK" character will be t~ansmitted,
even If the processor quickly re-programs the Command
Reglstertransmit mode. Later, when the Command Register
Is programmed back to normal transmit mode, a Stop Bit
will occur, from one to fifteen clock periods at the next bit
time,
/r----------~,/r------
STOP
.N
STOP
]~EJ
P STOP
I G"R
I
START
rTT'----;
1 - - - - - - 1 - ~EH~~O: ~A~Rci::SOR
NOAMAL
INTIARUPT
SELECTS
CONTINUOUS
"BREAK" MODE
POINTATWHI~
PROCESSOA
SELECTS
NORMAL
TRANSMIT
MODE
Fig, 18 - Transmit continuous "BREAK",
/
PROCESSOR
INTERRUPT
TO LOAO
TRANSMIT
DATA
92CM- 3678e
476 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP65C51
CDP65C51 OPERATION (Conl'd)
Table II - Divisor Selection lor the CDP65C51
3
0
CONTROL
REGISTER
BITS
2
1
0
0
DIVISOR SELECTED
FOR THE
INTERNAL COUNTER
0
0
No Divisor Selected
0
0
0
1
36,864
0
0
1
0
24,576
0
0
1
1
16,768
0
1
0
0
13,696
0
1
0
1
12,288
0
1
1
0
6,144
0
1
1
1
3,072
1
0
0
0
1,536
BAUD RATE GENERATED
WITH 1.8432 MHz
CRYSTAL
BAUD RATE GENERATED
WITH A CRYSTAL
OF FREQUENCY (F)
16 x External Clock at Pi n R x C 16 x External Clock at Pin R x C
1.8432 x 10"
F
50
36864
36864
F
1.8432 x 10
75
24576
24576
F
1.8432 x 10·
- 109.92
16768
16768
1.8432 x 10·
F
- 134.58
13696
13696
F
1.8432 x 10"
150
12288
12288
1.8432 x 1()1l
F
- 300
6144
6144
1.8432 x 10·
F
600
3072
3072
F
1.8432 x 10·
1200
1536
1536
~
F
1.8432 x 10"
1
0
0
1
1,024
1
0
1
0
768
1
0
1
1
1024
1.8432 x 10"
768
1.8432 x 1
512
1
1
0
0
384
1
1
0
1
256
1
1
1
0
192
err
512
1.8432 x 10·
384
1.8432 x 10"
~
1800
~
2400
~
3600
~
4800
1
1
1
96
Generating Other Baud Rates
By using a different crystal, other baud rates may be
generated. These can be determined by:
Baud Rate
~
Crystal Frequency
-----Divisor
512
F
~-4-
256
F
192
F
96
off-chip oscillator to achieve the same thing. In this case,
XTLI (pin 6) must be the clock input and XTLO (pin 7) must
be a no-con nec!.
DIAGNOSTIC LOOP-BACK OPERATING MODES
Furthermore, it is possible to drive the CDP65C51 with an
MICROPROCESSOR
768
F
F
= 7200
256
1.8432 x 10"
~ 9600
192
1.8432 x 1
~ 19200
96
err
1
1024
F
A simplified block diagram for a system incorporating a
CDP65C51 ACIA is shown in Fig. 20.
1------<,......----+---------...---
TO DATA LINK
Fig. 20 - Simplified system diagram.
92CS- 36859
478 _ _ _ _ _ _ _ _ _ _ _ _....__- CMOS Microprocessors, Memories and Peripherals
CDP65C51
CDP65C51 OPERATION (Cont'd)
In order to sense the state of the inputs, it is necessary to do
Register until the interrupt is serviced. Thus, it is not
the following:
convenient to use DCD and DSR as general switching
1. Disable the CDP65C51 by setting bit 0 of the Command
inputs, but they may easily be used as inputs which do not
Register to a "0".
change regularly.
2. Read the CDP65C51'Status Register. Bits 5 and 6 will
then indicate the levels on DCD and DSR, respectively.
A "0" is a low level and a "1" is a high.
SWITCHES
DR
<
~JUMPER
~
Dci5
As long as the CDP65C51 is disabled, the Status Register
will reflect the levels on the pins and no interrupts will
occur, even if the pins change state. However, if the
CDP65C51 is enabled, then changes of state of the i5CD
and DSR levels cause immediate interrupts and the Status
Register indicates the levels taken on the interrupt. Subsequent level changes are not indicated by the Status
WIRES
CDP65C51
-OSR
~
92C$-36782
Fig. 22 - Circuit connections for"i5CD andlJSR.
DYNAMIC ELECTRICAL CHARACTERISTICS-READ/WRITE CYCLE
Vcc:5 V ± 5%, T A:O to 70° C, Cc :75 pF
LIMITS
CDP65C51-1
CDP65C51-2
Min.
Max.
Min.
Max.
1
40
0.5
40
200
400
70
120
0
0
120
70
0
0
150
60
20
20
200
150
20
20
40
40
-
CHARACTERISTIC
Cycle Time
¢2 Pulse Width
Address Set-Up Time
Address Hold Time
R/W Set-Up Time
R/W Hold Time
Data Bus Sel-Up Time
Data Bus Hold Time
Refld Access Time (Valid Data)
Read Hold Time
Bus Active Time (Invalid Data)
Icyc
tc
lAC
tCAH
twc
1cWH
tocw
tHW
tCOR
tHR
tCOA
-
-
-
40 2 _ _ _ _ _J
CSc.em. RSC.RSI
-r".,.,,,J.--~-------+---.l.l"'r'J"""""""'''''''''77'7'7'-V'H
+-______+_..J
I.-_ _
·""'~~~~"_L""_V,
L
.k-------V,H
v,L
R/W
""""7777'7'7'7'7'7'7'7'7''7'7'7'7>
'_Hd_-.l
j..r-_'_OC_-.,;.__
DATABUS~
~
'-------
Wrtte-tlmlng waveforma
Read-timing waveforms
92CM-36775
Fig. 23 - Timing waveforms.
v, H
V,L
UNITS
iJ5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
480 _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP68HC68A1
Product Preview
TERMINAL ASSIGNMENT
CMOS Serial 10 Bit AID Converter
05C
16
Voo
TNT
15
All
M ISO
14
AI2
4
13
AI3
12
AI4
6
II
A 15
MOSI
SC"
CE
AIO
10
A 16
AI7
vS5
TOP VIEW
92CS-3B112
Features:
•
•
•
•
•
•
•
1O~bit resolution
8-bit accuracy
8-bit mode
SPI (Serial Peripheral Interface)
No zero or fullsca/e adjustments
required
Operators ratiometrically or with
internal 5 volt reference
100 liS conversion time
The CDP68HC68A1 is a CMOS 10-bit successive
approximation analog to digital converter (AID) with a
serial peripheral interface (SPI) bus and eight analog
inputs. A precision on chip voltage reference is available
for 5 volt operation or the Voo pin may be used with an
external reference for ratiometric operation. The
operating range of the converter includes the entire Voo
to Vss voltage range for each of the eight inputs.
The CDP68HC68A1 implements a switched capacitor,
successive approximation AID conversion technique
which provides an inherent sample and hold function. An
on chip Schmit! oscillator provides the internal timing of
the AID converter. It can be driven by an external
oscillator or system clock or connected to an external
capacitor to provide an Independent clock. The minimum
conversion time per input is 100 microseconds. Each
conversion requires 14 oscillator clock pulses in the 10bit mode and 12 in the 8-bit mode.
•
•
•
•
•
•
8 multiplexed analog input
channels
Independent channel select with
autoscanning
Multiple modes of operation
On chip oscillator
Low power CMOS circuitry
16-pin dua/-in-line plastic package
A unique features of the CDP68HC68A1 allows any
combination of the eight input channels to selected and
sequentially scanned in anyone of three modes. The
mode selection enables single, 8 channel or continuous
conversion operation. The device has three write only
registers which are used to select the mode of operation,
input channels, and starting address. The 10-bit
conversion data is stored (right justified) in two 8-bit
bytes. The most significant byte contains two status bits
which may be monitored by the microcomputer. An 8-bit
mode is available which performs an eight bit conversion
and stores the data in a single eight bit byte. In the 10-bit
mode, all sixteen data bytes are directly addressable and
in the 8-bit mode only the eight bit data byte is
accessible. A status register is available to monitor the
status of the conversion and the current channel address.
The status register can be used for system polling or the
iN'i' pin can be used for interrupt driven communications.
The CDP68HC68A1 is supplied in a 16-lead dual-in-line
plastic package (E suffix).
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Voo)
(Voltage referenced to Vs. terminal) ..................................................................................... -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS .......................................................................... -0.5 to Voo +0.5 V
DC INPUT CURRENT, ANY ONE INPUT .................................................................................. ± 10 mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to +60°C (PACKAGE TYPE E) ............................................................................... 500 mW
For T. =+60 to +85'C (PACKAGE TYPE E) ................................................. Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
ForT. = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) .................................................... 40 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE E .................................................................................................-40 to +85'C
STORAGE-TEMPERATURE RANGE (T... ) ........................................................................... -65 to +150'C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ........................................................ +265'C
File Number
1556
482 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP68HC68T1
Product Preview
TERMINAL
ASSIGNMENT
eLK OUT
CPUR
16
INT
SCK
CMOS Real-Time Clock with
RAM and Power Sense/Control
4
to'CSI
MISO
CE
6
VSS
8
15
Vee
XTAL OuT
14
XTAL IN
13
12
II
10
TOP
9
VSATT
VSYS
LINE
POR
PSE
VIEW
92C9-38053
Features:
•
•
•
•
•
SPI (Serial Peripheral Interface )
Full clock features: sec., min., hrs
(12/24, AM/PM), day of week,
date, month, year, (0-99), auto
leap yr
32-Word x 8-bit RAM
Seconds, minutes, hours alarm
Automatic power loss detection
The CDP68HC68T1, real-time clock provides a
time/calendar function, a 32 byte static RAM and a 3-wlre
serial peripheral Interface (SPI bus). The primary function
of the clock is to divide down a frequency Input that can
be supplied by the on-board oscillator in conjunction with
an external crystal or by an external clock source. The
clock either operates with a 32+kHz, 1+MHz, 2+MHz or
4+MHz crystal or It can be driven by an external clock
source at the same frequencies. In addition, the
frequency can be selected to allow operation from a 50 or
60 Hz Input. The time registers furnish seconds, minutes,
and hours data while the calendar registers offer day of
week, date, month and year Information. The data In the
time/calendar registers Is In BCD format. In addition, 12
or 24 hour operation can be selected with an AM-PM
Indicator available In the 12 hour mode. The T1 has a
separate clock output that supplies one of 7 selectable
frequencies.
Computer handshaking Is established with a "wired or"
•
•
•
•
•
Minimum standby (timekeeping)
voltages: 2.2 volts
Selectable crystal or 50/60 Hz line
input
Buffered clock output
Battery input pin
Three independent interrupt modes:
alarm, periodic or power down sense
interrupt output. The interrupt can be activated by any
one df three separate internal sources. The first is an
alarm circuit that consists of seconds, minutes and hours
alarm latches that trigger the interrupt when they are in
coincidence with the value in the seconds, minutes and
hours time counters. The second Interrupt source is one
of 15 periodic signals that range from subsecond to dally
intervals. The final interrupt source is from the power
sense circuit that is used with the LINE Input pin to
monitor power failures. Two other pins, the power supply
enable (PSE) output and the VSYB Input are used for
external power control. The ~ reset output pin Is
available for power down operation and Is activated under
software control. ~s also activated by a watchdog
circuit that if enabled requires the CPU to toggle the CE
pin periodically without a serial data transfer.
The CDP68HC68T1 is available In a 16-lead hermetic
dual-in-line ceramic package (D suffix) and in a 16-lead
dual-In-Ilne plastiC package (E suffix).
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VDD)
(Voltage referenced to V•• terminal) .................................................... , .................... '........... -0.5 to +7 V
INPUT VOL TAGE RANGE, ALL INPUTS .......................................................................... -0.5 to VDD +0.5 V
DC INPUT CURRENT. ANY ONE INPUT .................................................................................. ± 10 mA
POWER DISSIPATION PER PACKAGE (PD):
For T. = -40 to +60· C (PACKAGE TYPE E) ............................................................................... 500 mW
For T. = +60 to +85·C (PACKAGE TYPE E) ................................................. Derate Linearly at 12 mW/·C to 200 mW
For T. = -55 to +100·C (PACKAGE TYPE D) .............................................................................. 500 mW
For T. = +100 to +125· C (PACKAGE TYPE D) .............................................. Derate Linearly at 12 mW/· C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For T. = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) .................................................... 40 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE D ............................................................................................... -55 to +125·C
PACKAGE TYPE E .......................................................................•.........................-40 to +85·C
STORAGE-TEMPERATURE RANGE (T",) ........................................................................... -65 to +150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 In. (1.59 ± 0.79 mm) from case for 10 s max ........................................................ +265·C
File Number 1547
484 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP68HC68T1
STATIC ELECTRICAL CHARACTERISTICS at
TA
=-40 to +85° C, Voo =VeATT =5 V ± 10%, Except as Noted
LIMITS
CHARACTERISTIC
CONDITIONS
Quiescent Device Current
100
Output Voltage High Level
VOH
Output Voltage Low Level
VOL
Output Voltage High Level
VOH
Output Voltage Low Level
VOL
Input Leakage Current
3-State Output Leakage Current
-
Operating Current #
Input Capacitance
0.4
4.4
-
-
-
-
0.1
-
-
±1
-
-
±10
-
0.2
0.25
1
1
2
1 MHz
-
0.5
0.6
0.9
2 MHz
-
1
1.5
4 MHz
-
1.5
2
-
-
2
pF
-
-
2
p.s
32 kHz
C'N
V,N
Maximum Clock Rise and
Fall Times'
-
-
4 MHz
-
t" tf
- Typical values are for TA = 25° C and nominal Voo.
# Outputs open circuited .
• Except XTAL input.
=0, TA =25°C
-
100
-
2 MHz
External Clock
MAX.
-
1 MHz
Crystal Oscillator
TYP.10
32 kHz
(100 + Ibb)
MIN.
-
-
lOUT
UNITS
3.7
=-1.6 mA, Voo =4.5 V
IOL = 1.6 mA, Voo =4.5 V
IOH $10 p.A, Voo =4.5 V
IOL $ 10 p.A, Voo =4.5 V
IOH
liN
-
CDP68HC68T1
p.A
V
p.A
2
4
0.1
0.15
mA
486 - - - - - - - -_ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP68HC68T1
PROGRAMMERS MODEL - CLOCK REGISTERS
I
HEX ADDRESS
I
NAME
WRITE/READ REGISTERS
DB7
DBO
SECONDS (00-59)---
20
TENS 0-5
21
22
23
DB7, 1 = 12 HR, 0 = 24 HR
DB5 = 1 PM, 0 = AM
HOURS (01-12 OR 00-23)
12
PM/AM
HR. X TENS 0-2
24
X
X
X
SUNDAY = 1
DAY OF WK (01-07) - - -
X
01-28 )
(DATE)
(29
DAY OF MONTH
~~-
TENS 0-3
24
JAN = 1
MONTH (01-12)- DEC = 1225
YEARS (00-99) - - - -
26
7
31
6
5
4
3
2
CONTROL-----------
INTERRUPT - - - - - - - - -
7
32
WRITE ONLY REGISTERS
28
TENS 0-5
UNITS 0-9
ALARM SECONDS (00-59) -
29
TENS 0-5
UNITS 0-9
ALARM MINUTES (00-59)-
2A
X
X
PM/AM
TENS 0-2
UNITS 0-9
ALARM HOURS (01-12 Qr 00-23)
PLUS AM/PM IN 12 HR. MODE
PM = 1, AM = 0
READ ONLY REGISTER
30
NOTE:
X = DON'T CARE WRITES
X = 0 WHEN READ
RAM DATA BYTE
r:
STATUS
:, 1:·1 :. 1:'1 :'1 D: 1D: 1
HEX ADDRESS 00-1F
92CM·38059
488 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP68HC68T1
I
POWER DOWN (See Fig. 4.)
I
Power down is a processor-directed operation. A bit is set
in ihe Interrupt Control Register to initiate operation. 3
pins are affected. The PSE (Power Supply Enable) output,
normJ!lli::...tligh. is placed low. The ClK OUT is placed low.
The CPUR output, connected to the processors reset
input is also placed low. In addition, the Serial Interface
and Power Sense are disabled.
--=l
---rv;,m:-
~ -~
.------,J
I
I
vSYS
PSE
CPUR
TO SYSTEM
POWER CONTROL
FROM SYSTEM
POWER
L
--..rI
CLK
OUT
I
I III I I I I I I
1--:
r
.,
SERIAL
I N TE RFA CE
-/..
MI:SO
;;o-~=::""
r--o-l-cY'-o--l+-M-O-SI:-
REAL-TIME CLOCK
CDP68HC68T1
INTERRUPT
CONTROL
REGISTER
92CS-37944-
Fig. 6 - Power up functional diagram (Initiated by a rise in voltage
on the "VSYS" pin).
I
SERIAL
t--O'I:
MO
IN T ER FACE !---1-.,...,r-o-+o..:::.::.;S::.;I:=-_---I
PIN FUNCTIONS
CPU
CDP680502
REAL-TIME CLOCK
CDP68HC68T1
92CS- 37942
Fig. 4 - Power down functional diagram.
POWER UP (See Figs. 5 and 6.)
Two conditions will terminate the Power Down mode. The
first condition (See Fig. 5) requires an interrupt. The
interrupt can be generated by the alarm circuit or the
programmable periodic interrupt signal.
The second condition that releases Power Down occurs
when the level on the Vsys pin rises about 1 volt above the
level at the VBATT input, after previously falling to the level
of VBATT- See Fig. 6.
ClK OUT - Clock output pin. One of 7 frequencies can be
selected (or this output can be set low) by the levels of
the three lSB's in the clock control register. If a
frequency is selected, it will toggle with a 50% duty cycle.
(ex, If 1Hz is selected, the output will be high for 500ms
and low for the same period). During power down
operation (bit 6 in I nterrupt Control Register set to "1 "),
the clock out pin will be set low.
CPUR - CPU reset output pin. This output is placed low
from 15 to 40ms when the watchdog function detects a
CPU failure. The low level time is determined by the
frequency input source selected as the time standard.
When power down is initiated the CPUR pin is set low.
iNi' - Interrupt output pin. This output is driven from a
single NFET pulldown transistor and must be tied to an
external pullup resistor. The output is activated to a low
level when:
1 - Power sense operation is selected (B5 = 1 in
Interrupt Control Register) and a power failure occurs.
2 - A previously set alarm time occurs.
3 - A previously selected periodic interrupt signal
activates.
The status register must be read to set the Interrupt
output high after the selected periodic interval occurs.
This is also true when conditions 1 and 2 activate the
interrupt. If power down had been previously selected,
the interrupt will also reset the power down functions.
SCK, MOSI, MISO - See Serial Peripheral Interface (SPI)
section in this data sheet.
REAL-TIME CLOCK
CDP68HC68TI
92CS-37943
Fig. 5 - Power up functional diagram (Initiated by Interrupt Signal).
CE - A positive chip enable input. A low level at this input
holds the serial interface logic in a reset state. This pin is
also used for the watchdog function.
Vss - The negative power supply pin that is connected to
ground.
490 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP68HC68T1
INTERRUPT CONTROL REGISTER (Write/Read) - Address 32H
D7
D6
D5
D4
WATCHDOG
POWER
DOWN
POWER
SENSE
ALARM
D3
D1
D2
I
I
DO
I
PERIODIC SELECT
I
WATCHDOG - When this bit is set high, the watchdog
pperation will be enabled. This function require~ the CPU
to toggle the CE pin periodically without a serial transfer
requirement. In the event this does not occur, a CPU reset
will be issued.
POWER DOWN - A high in this location will initiate a
power down. A CPU reset will occur, the ClK OUT and
PSE output pins will be set low and the serial interface
will be disabled.
POWER SENSE - This bit is used to enable the line input
pin to sense a power failure. It is set high for this function.
When power sense is selected, the input to the 50/60 Hz
prescaler is disconnected, therefore crystal operation is
I
1
required when power sense is enabled. An interrupt is
generated when a power failure is sensed and the power
sense and Interrupt True bit In the Status Register are set.
ALARM - The output of the alarm comparator is enabled
when this bit is set high. When a comparison occurs
between the seconds, minutes and hours time and alarm
counters, the interrupt output is activated. When loading
the time counters, this bit should be set low to avoid a
false interrupt. This is not required when loading the
alarm counters.
PERIODIC SELECT - The value in these 4 bits will select
the frequency of the periodic output as listed below. (See
Table J).
Table J - Periodic Interrupt Output
FREQUENCY TIMEBASE
DO-D3
VALUE
PERIODIC-INTERRUPT
OUTPUT FREQUENCY
0
Disable
1
2048 Hz
X
2
1024 Hz
X
3
512 Hz
X
4
256 Hz
X
5
128 Hz
X
6
64 Hz
X
XTAL
LINE
X
50 or60 Hz
7
32 Hz
X
8
16 Hz
X
9
8 Hz
X
10
4 Hz
X
11
2 Hz
X
X
12
1 Hz
X
X
13
Minute
X
X
14
Hour
X
X
15
Day
X
X
All bits are reset by power-on reset.
492 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP68HC68T1
FUNCTIONAL DESCRIPTION
E
The Serial Peripheral Interface (SPI) utilized by the
C,DP68HC68T1 is a serial synchronous bus for address
and data transfers, The clock, which is generated by the
microcomputer, is active only during address and data
transfers, In systems using the CDP68HC05C4 or
CDP68HC05D2, the inactive clock polarity is determined
by the CPOL bit in the microcomputer's control register,
A unique feature of the CDP68HC68T1 is that it
automatically determines the level of the inactive clock by
sampling SCK when CE becomes active (see Fig, 7),
Input data (MOSI) is latched internally on the 'I nternal
Strobe edge and output data (MISO) is shifted out on the
Shift edge, as defined by Fig. 7. There is one clock for
each data bit transferred (address as well as data bits are
transferred in groups of 8).
CPOL'" I
{
SCK
CPOL.O{E
SCK
MOSL ____________
NOTE'
~
"CPOLI! IS A BIT THAT IS SET IN THE
MICROCOMPUTER'S CONTROL REGISTER
92CS-37945
Fig. 7 - Serial RAM clock (SCK) as a function of MCU clock
polarity (CPOL).
true again. Bit 5 is used to select between Clock and RAM
locations.
ADDRESS AND DATA FORMAT
There are three types of serial transfer.
1.
2.
3.
Address Control - Fig. 8
READ or WRITE Data - Fig. 9
Watchdog Reset (actually a non-transfer) - Fig. 10
The Address/Control and Data bytes are shifted MSB
first, into the serial data input (MOSI) and out of the serial
data output (MISO),
Any transfer of data requires and Address/Control byte to
specify a Write or Read operation and to select a Clock
or RAM location, followed by one or more bytes of data.
Data is transferred out of MISO for a Read and into MOSI
for a Write operation.
BIT
7
6
I W/R I
0
CE
MOSI
4
3
2
AO-A4
5
CLOCK/RAM
6
o
7
wiFi
Selects 5 Bit HEX Address of
RAM or specifies Clock Register.
Most significant Address Bit.
If equal to "1", AO through A4
selects a Clock Register.
If equal to "0", AO through A4
selects one of 32 RAM locations.
Must be set to "0" when not in
Test Mode
wiR = "1" initiates one or more
WRITE cycles.
wiR = "0", initiates one or more
READ cycles.
~
~
*
W/R
o
A4
A3
A2
o
I~ I A4 I A3 I A2 I A1 I AO I
0-4
ADDRESS/CONTROL BYTE - Fig. 8
It is always the first byte received after CE goes true. To
transmit a new address, CE must first go false and then
5
AI
SCK CAN BE EITHER POLARITY.
fig, 8 - Address/Control byte transfer waveforms.
AO~
92CM-37946
494 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP68HC68T1
L
CE
I I I I I I 1/
SCK
I I I I I II I
{MOSI~
"-"'-'-"""-<1-__A_D_DR_E_S_S_B_Y_TE_ _..J-_ _ _W_R_IT_E_D_A_TA_ _
WRITE
~
MOSI
. . J~"_"_'_'_' _'_' _' _' _' _' _' _' '_' _' _' _'
...
ADDRESS BYTE
{
READ
MI50-----------~(~
DA_~
_________R_E_AD_ _
______________')____
92CM-37949
Fig. 11 - Single byte transfer waveforms.
CE
~
1111 I III I II II I I I 1II1II11 I: II I I I IIII
SCK
WRITE {MOSI
~ ,. .,. ., . .,. .,r- A-D -R-ES-S-BY-TE-. . -D-A-TA-B-YT-E- -,r- DA-T-A
-B-YT-E--:l
:1:-
-B-YT-E- -'~" "' ' ' ' '"7"7"
-DA-T-A
{'?
MOSI
7/.~77"7:r""--"T7~"7/77";"777777777"7/77";"f"7"7 .'. 77:~77777'7777".77777"77
~
ADDRESS BYTE
~ ~
{
READ
MISO
---------1
WiR ADORE S5 {
,...------., ,...------..
II.
~
ADDRESS BYTE
ADDRESS BYTE + 1 - - - - - - - - '
ADDRESS BYTE + ( n - 1 ) - - - - - - 92CM-37950
Fig. 12 - Multiple-byte transfers waveforms.
496 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP68HC68T1
MOSI
+H-t+oN
MISO
----------r----------a------r-----------r1~~
"""Uf--..I1
CE
SCK
92CM-37952
Fig. 14 - READ cycle timing waveforms.
SYSTEM DIAGRAMS
AC
~INE
JI
BRIDGE
I
REGU~ATORI
~~
p-----<
-t-
-+
VDD POR
INT
VSYS
-
VDD
IRQ
LINE
•
'.:-
CDP68HC88TI
VBATT
CJ5UR
CE
SCK
XTA~
.....
CDP6605D2
RESET
PORT
SCK
MOSI
MOSI
MISO
IN
MISO
nCM-l7an
Example of a system In which power Is always on. Clock
circuit driven by line Input frequency. Power-on-reset
circuit included to detect power-failure.
Fig. 15 - Power-on always system-diagram.
498 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP68HC68T1
SYSTE M
POWER
L-+--IHHvoo
COP680502
Voo
1--------<1--11 RQ
COP68HC68TI
1 - - - - - - - 1 RESET
1-------IOSC1
C E I - - - - - - - I PORT
MISO
SCK
MOSI
SCK
MOS I MISO
92CM-379!5!5
Example of a system in which the power is controlled by
the CPU. To power-down the system, the CPU gives the
CDP68HC68Tl a power down instruction. This occurs
when bit 6 in the INTERRUPT Control Register is set
high. The power down will be released by a previously
programmed periodic interrupt or an alarm circuit
interrupt. When the interrupt occurs, the level on the PSE
pin will return high and the system power will be restored.
An external switch can be included to power-up the
system independent of a programmed power-up.
Fig. 17 - CPU controlled power system-diagram.
500 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
Advance Information/
Preliminary Data
CDP6818
CMOS Real-Time Clock with RAM
"
OSC1
'00
SQW
"
CKOUT
•
•
Low-Power, High-Speed, High-Density CMOS
Internal Time Base and Oscillator
'0
CKFS
•
Counts Seconds, Minutes, and Hours of the Day
"
•
Counts Days of the Week, Date, Month, and Year
RrsEf
OSC2
AOO
AO,
18
IRQ
os
ADS
A07
"
"W
"
CE:
14
'55
TOP VIEW
Features:
TERMINAL ASSIGNMENT
• 3V
•
to 6 V Operation
Time Base Input Options: 4.194304 MHz, 1 048576 MHz, or
32.768 kH,
• Time 8ase Oscillator for Parallel Resonant Crystals
• 40 to 200 p.W Typical Operating Power at Low Frequency Time Base
• 4.0 to 20 mW TYPical Operating Power at High Frequency Time
Base
•
Binary or BCD Representation of Time, Calendar, and Alarm
•
12- or 24-Hour Clock with AM and PM in 12-Hour Mode
•
DaylJght Savings Time Option
•
•
Automatic End of Month Recognition
Automatic Leap Year Compensation
• Microprocessor Bus Compatible
The CDP6818 Real-Time Clock plus RAM is a peripheral
• MOTEL CirCUit for Bus Universality
device which Includes the unique MOTEL concept for use with
• Multiplexed Bus for Pin Efficiency
many 8-bit microprocessors, microcomputers, and larger
• Interfaced with Software as 64 RAM Locations
computers. This device combines three unique features: a
• 14 Bytes of Clock and Control Registers
complete time-of-day clock with alarm and one hundred year
calendar, a programmable periodic interrupt and square-wave
generator, and 50 bytes of low-power static RAM. The
CDP6818 uses high-speed CMOS technology to interface
with 1 MHz processor buses, while consuming very little
power.
The Real- Time Clock plus RAM has two distinct uses. First, it
is designed as a battery powered CMOS device (in an otherwise NMOSITTL system) including all the common battery
backed-up functions such as RAM, time, and calendar Secondly, the CDP6818 may be used with a CMOS microprocessor to relieve the software of the timekeeping workload and to
extend the available RAM of an MPU such as the CDP6805E2.
Fig. 1 -
•
•
•
•
•
•
•
50 Bytes of General Purpose RAM
Status Bit Indicates Data Integrity
Bus Compatible Interrupt Signals (iRa}
Three Interrupts are Separately Software Maskable and Testable
• Time-of-Day.Alarm, Once-per-Second to On~ce-per-Day
• Periodic Rates from 30.5 p.s to 500 ms
• End-of-Clock Update Cycle
Programmable Square-Wave Output Signa)
Clock Output May Be Used as Microprocessor Clock Input
• At Time Base Frequency + 1 or +4
24-Pin Dual-In-Line Package
Block diagram.
File Number
1375
502 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6818
BUS TIMING
=5.0 V
Voo
±
=
Ident.
Number
Characteristics
Symbol
1
2
3
4
8
13
14
15
18
21
24
25
26
27
28
30
31
Cycle Time
Pulse Width. DS/E Low or RD/WR High
Pulse Width. DS/E High or 'I1ri/\i'm Low
Input Rise and Fall Time
RIW Hold Time
R/W.Setup Time Before DS/E
Chip Enable Setup Time Before AS/ALE Fall
Chip Enable Hold Time
Read Data Hold Time
Write Data Hold Time
Muxed Address Valid Time to AS/ALE Fall
Muxed Address Hold Time
Delay Time DS/E to AS/ALE Rise
Pulse Width. AS/ALE High
Delay Time, AS/ALE to DS/E Rise
Peripheral Output Data Delay Time from DS/E or RD
Peripheral Data Setup Time
tcyc
Voo 3.0 V
50 pF Load
Min
Max
-
5000
1000
1500
PWEL
PWEH
t r • t,
-
10%
2 TTL and
130 pF Load
Min
Max
953
300
325
100
10
200
200
10
10
100
200
100
500
600
500
1300
1500
tAWH
tAWS
les
tCH
tOHR
tOHW
tASL
tAHL
tASD
PWASH
tAS ED
tooA
tosw
*
1000
-
-
-
Unit
dc
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
10
165
55
0
10
0
50
20
50
135
60
20
200
*
100
-
240
-
m
NOTE: Designations E, ALE. RD, and
refer to signals from alternative microprocessor signals.
*See Important Application Notice (refer to Fig. 23).
AS
OS
~
-
f-
v~·
~
-
-0-
@
1\
--
vt.- ~
VHIGH
1\
VLOW
~
..... 1+-0
f.
I
0- i--
1+
j
)
1\
J
1--0
)(
~
-/-- ~~0
e
1-
8- 1-01-0
~
\\\\\\\\
VW
-t- I+- \--G
GADO
AD7
WRITE
G-
.
...
-===':f!
VXXW./\
Xr\kL I\.
I---
(5)
...
ADO
AD'
READ
NOTE VHIGH",VOO-20V, VlOW=O~V, forVOO=50V ±1O%
Fig. 2 -
ev
-I"-
~@
i-'
R/W
IT
~ @
CDP6818 bus timing waveforms.
-
-0
-B
504 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6818
TABLE 1 -
SWITCHING CHARACTERISTICS (VDD~5 Vdc ± 10%, VSS~o Vdc, TA~O° to 70 C C)
Description
Symbol
Min
Max
Unit
Oscillator Startup
tRC
-
100
ms
Reset Pulse Width
tRWL
5
-
~s
Reset Delay Time
tRLH
5
-
~s
Power Sense Pulse Width
tPWL
5
-
~s
Power Sense Delay Time
tPLH
5
-
~s
IRO Release from DS
tlRDS
-
2
~s
tlRR
-
2
~s
tVRTD
-
2
~s
IRO Release from RESET
VRT Bit Delay
\
DS
.. VLOW
RESET
~
,A
IRO
IIRR
tlRDS
NOTE VHIGH ~ VDD
Jr
F
VHIGH
I
2.0 V, VLOW ~ 0.8 V, fur VDD
Fig. 5 -
5.0 V ,10%
iRQ release delay timing waveforms,
VDD
(iRO
2k
Test
Point
Test POint
Vi
All Outputs Except 05C2 (See Figure 101
Fig, 6 -
TTL equivalent test load.
Onlyl
0-----.
4.02 k
506 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6818
MOTEL
The MOTEL circuit is a new concept that permits the
COP68t8 to'be directly interfaced with many types of microprocessors. No external logic is needed to adapt to the differences in bus control signals from common multiplexed bus
microprocessors.
Practically all microprocessors interface with one of two
synchronous bus structures.
The MOTEL circuit is built into peripheral and memory ICs to
permit direct connection to either type of bus. An industry
standard bus structure is now available. The MOTEL concept
is shown logically in Figure 9.
MOTEL selects one of two interpretations cif two pins. In the
6805 case, OS and R/W are gated together to produce the
internal read enable. The internal write enable is a similar
gating of the inverse of R/iN. With competitor buses, the inversion of AD and WR create functionally identical internal read
and write enable signals.
. The COP6818 automatically selects theJ2!:ocessor type by
using AS/ ALE to latch the state of the OS/RO pin. Since OS is
always low and Fill is always high during AS and ALE, the latch
automatically indicates which processor type is connected.
6800
Family Type
MPU Signals
Competitor Type
MPU Signals
CDP6818
Competative Bus
Pin Signals
D
ALE
AS
DS, E, or <1>2
AS
11----+----1
C
Q
Internal
Signals
6805
Family
Bus
DS
Read Enable
R/W
Write Enable
Fig, 9 - Functional diagram 01 MOTEL circuit.
SIGNAL DESCRIPTIONS
The block diagram in Figure 1, shows the pin connection
with the major internal functions of the CDP681S Real-Time
Clock plus RAM. The following paragraphs describe the function of each pin.
AT cut crystal at 4.194304 MHz or 1,048576 MHz frequencies, The crystal connections are shown in Figure 11 and the
crystal characteristics in Figure 12,
CKOUT - CLOCK OUT. OUTPUT
DC power is provided to the part on these two pins. VDD
being the most positive voltage, The minimum and maximum voltages are listed in the Electrical Characteristics
tables,
The CKOUT pin is an output at the time-base frequency
divided by 1 or 4, A major use for CKOUT is as the input
clock to the microprocessor; thereby saving the cost of a second crystal. The frequency of CKOUT depends upon the
time-base frequency and the state of the CKFS pin as shown
in Table 2,
OSC1. OSC2 - TIME BASE. INPUTS
CKFS - CLOCK OUT FREQUENCY SELECT. INPUT
The time base for the time functions may be an external
signal or the crystal oscillator, External square. waves at
4,194304 MHz. 1,048676 MHz. or 32,768 kHz may be connected to OSC1 as shown in Figure 10, The time-base frequency to be used is chosen in Register A,
The on-Chip oscillator is designed for a parallel resonant
The CKOUT pin is an output at the time-base frequency
divided by 1 or 4, CKFS tied to VDD causes CKOUT to be
the same frequency as the time base at the OSC1 pin, When
CKFS is at VSS. CKOUT is the OSC1 time-base frequency
divided by four. Table 2 summarizes the effect of CKFS.
Voo.VSS
508 ______________ CMOS Microprocessors, Memories and Peripherals
CDP6818
TABLE 2 - CLOCK OUTPUT FREQUENCIES
Time Base
IOSC1)
Frequency
4.194304 MHz
4.194304 MHz
1.048576 MHz
1.048576 MHz
32.768 kHz
32.768 kHz
SQW -
Clock Frequency
Select Pin
ICKFS)
High
Low
High
Low
High
Low
Clock Frequency
Output Pin
ICKOUT)
4.194304 MHz
1.048576 MHz
1.048576 MHz
262.144 kHz
32.768 kHz
8.192 kHz
SQUARE WAVE, OUTPUT
The SQW pin can output a signal one of 15 of the 22
internal-divider stages. The frequency and output enable of
the SQW may be altered by programming Register A, as shown
in Table 5. The SQW signal may be turned on and off using a bit
in Register B.
the case with the CDP6805 family of multiplexed bus processors. To insure the competitor mode of MOTEL, the OS pin
must remain high during the time AS/ ALE is high.
FVW -
READ/WRITE, INPUT
The MOTEL circuit treats the R/W pin in one of two ways.
When a 6805 type processor is connected, R/W is a level
which indicates whether the current cycle is a read or write. A
read cycle is indicated with a high level on R/W while OS is
high, whereas a write cycle is a low on R/W during OS.
The second interpretation of R/W is as a negative write
pulse, WI'l, ME1iiiW, and ITr5W from competitor type processors. The MOTEL circuit in this mode gives R/W pin the same
meaning as the write(W) pulse on many generic RAMs.
CE -
CHIP ENABLE, INPUT
The chip-enable (CE) signal must be asserted (loIN) for a
bus cycle in which the CDP6818 is to be accessed.
is not
latched and must be stable during OS and AS (in the 6805
mode of MOTEL) and during 115 and WI1 (in the competitor
mode). Bus cycles which take place without asserting IT
cause no actions to take place within the CDP6818. When CE
is high, the multiplexed bus output is in a high-impedance
state.
When CE is high, all address, data, OS, and R/Vii inputs from
the processor are disconnected within the CDP681 B. This
permits the CDP6818 to be isolated from a powered-down
is held high, an unpowered device cannot
processor. When
receive power through the input pins from the real-time clock
power source. Battery power consumption can thus be reduced by using a pullup resistor or active clamp on
when
the main power is off.
cr
ADO-AD7 - MULTIPLEXED BIDIRECTIONAL
ADDRESS/DATA BUS
Multiplexed bus processors save pins by presenting the
address during the first portion of the bus cycle and using the
same pins during the second portion for data. Address-thendata multiplexing does not slow the access time of the
CDP6Bl B since the bus reversal from address to data is occurring during the internal RAM access time.
The address must be valid just prior to the fall of AS/ ALE at
which time the CDP6Bl B latches the address from ADO to
AD5. Valid write data must be r:>resented and held stable during
the latter portion of the OS or WI1 pulSes. In a read cycle, the
CDP6B,ill, outputs 8 bits of data during the latter portion of the
OS or RD pulses, then ceases driving the bus (returns the
output driv~ to three-state) when OS falls in this case of
MOTEL or RD rises in the other case.
AS -
MULTIPLEXED ADDRESS STROBE, INPUT
A positive gOing multiplexed address strobe pulse serves to
demultiplex the bus. The falling edge of AS or ALE causes the
address to be latched within the CDP6818. The automatic
MOTEL circuitry in the CDP6818 also latches the state of the
OS pin with the falling edge of AS or ALE.
OS -
DATA STROBE OR READ, INPUT
The DS pin has two interpretations via the MOTEL circuit.
When emanating from a 6800 type processor, OS is a positive
pulse during the latter portion of the bus cycle, and is variously
called DS (data strobe), E (enable), and ¢2 (¢2 clock). During
read cycles, OS signifies the time that the RTC is to drive the
bidirectional bus. In write cycles, the trailing edge of OS
causes the Real-Time Clock plus RAM to latch the written
data.
The second MOTEL interpretation of OS is that of RD,
MEMR, or IIOR emanating from a competitor type processor.
In this case, OS identifies the time period when the real-time
clock plus RAM drives the bus with read data. This interpretalIOn of OS IS also the same as an output-enable signal on a
typical memory.
The MOTEL circuit, within the CDP6B18, latches the state of
the OS pin on the falling edge of AS/ ALE. When the 6800 mode
of MOTEL is desired OS must be low during AS/ ALE, which is
a:
a:
iRQ -
INTERRUPT REQUEST, OUTPUT
The iRQ pin is an active low output of the CDP6818 that may
be used as an interrupt input to a processor. The IRQ output
remains low as long as the status bit causing the interrupt is
present and the corresponding interrupt-enable bit is set. To
clear the ~~~J~e processor program normally reads RegIster C. The
pin also clears pending interrupts.
When no interrupt conditions are present, the iRa level is in
the high-impedance state. Multiple interrupting devices may
thus be connected to an IRQ bus with one pull up at the
processor.
RESET -
RESET, INPUT
The RESET pin does not affect the clock, calendar or RAM
functions. On the powerup, the RESET pin must be held low for
the specified time, tRLH, in order to allow the power supply to
stabilize. Figure 13 shows a typical representation of the
RESET pin circuit.
When Rrsti is low the following occurs:
a) Periodic Interrupt Enable (PIE) bit is cleared to zero,
b) Alarm Interrupt Enable (AlE) bit is cleared to zero,
c) .Update ended Interrupt Enable (UIE) bit is cleared to
zero,
d) Update ended Interrupt Flag (UF) bit is cleared to zero,
e) Interrupt Request status Flag (IRQF) bit is cleared to
zero,
f) Periodic Interrupt Flag (PF) bit is cleared to zero,
510 ______________ CMOS Microprocessors, Memories and Peripherals
CDP6818
0-to-23. The 24112 bit cannot be changed without reinitializing the hour locations. When the 12-hour format is selected
the high-order bit of the hours byte represents PM when it is
Before initializing the internal registers, the SET bit in
Register B should be set to a "1" to prevent time/calendar
updates from occurring. The program initializes the 10 locations in the selected format (binary or BCDI, then indicates
the format in the data mode (OM) bit of Register B. All 10
time, calendar, and alarm bytes must use the· same data
mode, either binary or BCD. The SET bit may now be cleared
to allow updates. Once initialized the··real-time clock makes
all updates in the selected data mode. The data mode cannot
be changed without reinitializing the 10 data bytes.
Table 3 shows the binary and BCD formats of the 10 time,
calendar, and alarm locations. The 24/12 bit in Register B
establishes whether the hour locations represent 1-to-12 or
o
a "1".
The time, calendar, and alarm bytes are not always accessable by the processor program. 'Once-per-second the 10
bytes are switched to the update logic to be advanced by one
second and to check for an alarm condition. If any of the 10
bytes are read at this time, the data outputs are undefined.
The update lockout time is 248 p's at the 4.194304 MHz and
1.048567 MHz time bases and 1948 p'S for the 32.768 kHz
time base. The Update Cycle section shows how to accommodate the update cycle in the processor program.
$00
14
Bytes
a
Seconds
$00
1
Sec Alarm
01
13
aD
2
Minutes
02
14
OE
3
Min Alarm
03
50
Bytes
User
RAM
$3F
63
4
Hours
04
5
Hr Alarm
05
6
Day of Wk
06
j
Date of Mo
07
8
Month
9
Year
Binary
or BCD
Contents
06
09 '"
OA
10
Register A
11
Register B
OB
12
RegisterC
OC
13
Register D
$OD
Fig. 15 - Address map.
TABLE 3 - TIME, CALENDAR, AND ALARM DATA MODES
Address
Location
a
1
2
3
4
5
6
7
8
9
Function
Seconds
Seconds Alarm
Minutes
Minutes Alarm
Hours
(12 Hour Mode)
Hours
(24 Hour Mode)
Hours Alarm
(12 Hour Mode)
Hours Alarm
(24 Hour Mbde)
Day of the Week
Sunday = 1
Day of the Mo,lth
Month
Year
Decimal
Range
0-59
0-59
0-59
0-59
1-12
Range
Binary Data Mode BCD Data Mode
$00-$38
$00-$59
$00-$38
$00-$59
$00-$59
$00-$38
$00-$38
$00-$59
$OI-$OC (AM) and $01-$12 (AM) and
$81-$92 (PM)
$81-$8C (PM)
ExamDle"
Binary
BCD
Data Mode Data Mode
21
15
15
21
58
3A
58
3A
05
05
0-23
$00-$17
$00-$23
05
05
1-12
$OI-$OC (AM) and
$81-$8C (PM)
$01-$12 (AM) and
$81-$92 (PM)
05
05
0-23
$00-$17
$00-23
05
05
1-7
$01-$07
$01-$07
05
05
1-31
1-12
0-99
$OI-$IF
$OI-$OC
$01-$31
$01-$12
$00-$63
$00-$99
OF
02
4F
15
02
79
'Example: 5:58:21 Thursday February 15 1979 (Time is A.M.)
512 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6818
TABLE 4 - DIVIDER CONFIGURATIONS
Divider Bits
Register A
Time-Base
Frequency
Operation
Mode
Divider
Reset
Bypass First
N-Divider Bits
OV2
DV1
DVO
4.194304 MHz
0
0
0
Yes
N=O
1.048576 MHz
0
0
1
Yes
N=2
32.768 kHz
0
1
0
Yes
N=7
Any
1
1
0
No
Yes
Any
1
1
1
No
Yes
Note: Other combinations of divider bits are used for test purposes only.
SQUARE-WAVE OUTPUT SELECTION
Fifteen of the 22 divider taps are made available to a
1-of-15 selector as shown in Figure 1. The first purpose of
selecting a divider tap is to generate a square-wave output
signal on the SOW pin. Four bits in Register A establish the
square-wave frequency as listed in Table 5. The SOW frequency selection shares the 1-of-15 selector with periodic
interrupts.
Once the frequency is selected, the output of the SOW pin
may be turned on and off under program control with the
square-wave enable ISOWEI bit in Register B. Altering the
divider, square-wave output selection bits, or the SOW
output-enable bit may generate an asymetrical waveform at
the time of execution. The square-wave output pin has a
number of potential uses. For example, it can serve as a frequency standard for external use, a frequency synthesizer, or
could be used to generate one or more audio tones under
program control.
PERIODIC INTERRUPT SELECTION
The periodic interrupt allows the IRO pin to be triggered
from once every 500 ms to once every 30.517 fJs. The
periodic interrupt is separate from the alarm interrupt which
may be output from once-per-second to once-per-day.
Table 5 shows that the periodic interrupt rate is selected
with the same Register A bits which select the square-wave
frequency. Changing one also changes the other. But each
function ma / be separately enabled so that a program could
switch between the two features or use both. The SOW pin
is enabled by the SOWE bit. Similarly the periodic interrupt is
enabled by the PIE bit in Register B.
Periodic interrupt is usable by practically all real-time
systems. It can be used to scan for all forms of inputs from
contac: closures to serial receive bits on bytes. It can be used
in multiplexing displays or with software counters to
measure inputs, create output intervals, or await the next
needed software function.
TABLE 5 - PERIODIC INTERRUPT RATE AND SQUARE WAVE OUTPUT FREQUENCY
32.768 kHz
4.194304 or 1.048576 MHz
Time Base
Time Base
Rate Select
Periodic
Periodic
Control Register A
Interrupt Rate SQW Output Interrupt Rate SQW Output
RS3 RS2 RS1 RSO
tpi
tpi
Frequency
Frequency
0
0
0
None
None
None
None
0
0
0
0
1
390625 ms
30.5171's
32.768 kHz
256 Hz
0
0
1
0
16.384 kHz
7.8125 ms
128 Hz
61.0351's
0
0
1
1
122.0701's
8.192 kHz
8.192 kHz
122070 ~s
0
1
0
0
244.141 I's
4096 kHz
4.096 kHz
244.141I's
0
1
0
1
2.048 kHz
2.048 kHz
488.281 I's
488.281I's
0
1
1
0
1.024 kHz
976.5621's
1.024 kHz
976.562I's
0
1
1
.1
1.953125 ms
512 Hz
512 Hz
1.953125 ms
1
0
0
3.90625 ms
256 Hz
0
256 Hz
3.90625 ms
1
0
0
1
7.8125 ms
128 Hz
7.8125 ms
128 Hz
1
0
1
0
15.625 ms
64 Hz
15.625 ms
64 Hz
1
0
1
1
31.25 ms
32 Hz
31.25 ms
32 Hz
1
1
0
62.5 ms
16 Hz
16 Hz
0
62.5 ms
1
1
0
1
125 ms
8 Hz
125 ms
8 Hz
1
1
1
0
250 ms
4 Hz
250 ms
4 Hz
1
1
1
1
500 ms
2 Hz
500 ms
2 Hz
514 _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6818
OV2, OV1, OVO - Three bits are used to permit the program to select various conditions of the 22-stage divider
chain. The divider selection bits identify which of the three
time-base frequencies is in use. Table 4 shows that time
bases of 4.194304 MHz, 1.048576 MHz, and 32.768 kHz may
be used. The divider selection bits are also used to reset the
divider chain. When the time/ calendar is first initialized, the
program may start the divider at the precise time stored in
the RAM. When the divider reset is removed the first update
cycle begins one-half second later. These three read/write
bits are not affected by RESET.
quency specified in the rate selection bits (RS3 to RSQ) appears on the SOW pin. When the SOWE bit is set to a zero
the SOW pin is held low. The state of SOWE is cleared by
the RESET pin. SOWE is a read/write bit.
OM - The data mode IDMI bit indicates whether time
and calendar updates are to use biAary or BCD formats. The
DM bit is written by the processor program and may be read
by the program, but is not modified by any internal functions
or RESET. A "1" in OM signifies binary data, while a "0" in
DM specifies binary-coded-decimal I BCDI data.
24/12 - The 24/12 control bit establishes the format of
the hours bytes as either the 24-hour mode (a "1 "lor the
12-hour mode (a "0"1. This is a read/write bit, which is affected only by the software.
RS3, RS2, RS 1, RSO - The four rate selection bits select
one of 15 taps on the 22-stage divider, or disable the divider
output. The tape selected may be used to generate an output
square wave (SOW pin 1and/or a periodic interrupt. The program may do one of the following: 11 enable the interrupt
with the PIE bi)', 21 enable the SOW output pin with the
SOWE bit, 31 enable both at the same time at the same rate,
or 41 enable neither. Table 5 lists the periodic interrupt rates
and the square-wave frequencies that may be chosen with
the RS bits. These four bits are read/write bits which are not
affected by RESET.
OSE - The daylight savings enable IDSEI bit is a
read/write bit which allows the program to enable two
special updates (when DSE is a "1"). On the last Sunday in
April the time increments from 1:59:59 AM to 3:00:00 AM.
On the last Sunday in October when the time first reaches
1:59:59 AM it changes to 1:00:00 AM. These special updates
do not occur when the DSE bit is a "a". DSE is not changed
by any internal operations or ~
REGISTER B ($OB)
REGISTER C ($OC)
Read/Write
Register
SET - When the SET bit is a "0", the update cycle functions normally by advancing the counts once-per-second.
When the SET bit is written to a "1", any update cycle in
progress is aborted and the program may initialize the time
and calendar bytes without an update occurring in the midst
of initializing. SET is read/write bit which is not modified
but ~ or internal functions of the CDP681 B.
PIE - The periodic interrupt enable (PIE) bit is a read/
write bit which allows th~eriodic-interrupt flag (PF) bit in
Register C to cause the TRU pin to be driven low. A program
writes a "1" to the PIE bit in order to receive periodic interrupts at the rate specified by the RS3, RS2, RS1. and RSO bits
in Register A. A zero in PIE blocks 11m from being initiated by
a periodic interrupt. but the periodic flag (PF) bit is still set at
the periodic rate. PIE is not modified bYFfEn~Tternal CDP6818
functions, but is cleared to "a" by a
.
AtE - The alarm interrupt enable (AIEl bit is a read/write
bit which when set to a "1" permits the alarm flag (AFI to
assert IRO. An alarm interrupt occurs for each second that
the three time bytes equal the three alarm bytes (including a
"don't care" alarm code of binary 11 XXX XXXI . When the
AlE bit is a "0", the AF bit does not initiate an iRa signal.
The RESET pin clears AlE to "0". The internaJ functions do
not affect the AI E bit.
Read-Only
Register
IRQF - The interrupt request flag (IROFI is set to a "1"
when one or more of the following are true:
PF=PIE="I"
AF=AIE="I"
UF= UIE= "1"
i.e.,IROF=PF.PIE+AF.AIE+UF.UIE
Any time the IROF bit is a "1", the IRO pin is driven low.
All flag bits are cleared after Register C is read by the program or when the RESET pin is low.
PF - The periodic interrupt flag (PFI is a read-only bit
which is set to a "1" when a particular edge is detected on
the selected tap of the divider chain. The RS3 to RSO bits
establish the periodic rate. PF is set to a "1" independent of
the state of the PIE bit. PF being a "1" initiates an iRa Signal
and sets the IRQF bit when PIE is also a "1." The PF bit is
cleared by a l'1'E'SEi or a software read of Register C.
AF - A "1" in the AF (alarm interrupt flagl bit indicates
that the current time has matched the alarm time. A "1" in
the AF causes the IRO pin to go low, and a "1" to appear in
the IROF bit, when the AlE bit also is a "1." A RESET or a
read of Register C clears AF.
assert IRO. The RESET pin going low or the SET bit going
high clears the UIE bit.
UF - The update-ended interrupt flag (UF) bit is set after
each update cycle. When the UIE bit is a "1", the "1" in UF
causeS the IROF bit to be a "1", asserting IRO. UF is cleared
by a Register C read or a RESET.
SQWE - When the square-wave enable (SOWE) bit is set
to a "1" by the program, a square-wave signal at the fre-
b3 TO bO - The unused bits of Status Register 1 are read
as "0'5". they can not be written.
UtE -
The UIE (update-ended interrupt enablel bit is a
read/w~ bit wh.l£.!J..!!!lables the update-end flage (UFI bit to
516 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6818
A
N
8085
I\.
Address/ Data
8
v
Address Latch Enable (ALEI
Read IRI
Other
NSC800
Write (W)
-
f----.~--
80CSI
Interrupt Request
l
MPU
8/4
Address
-.(}
•
.6
8085
Only
Address
Decode
J>.
8/V
9
~
~
~
V
"""-'
CE
IRO R, W
OS
AS ADOAD7
~
RESET
_1
CDP6818
CKOUT
Fig. 18 -
-
-
-
4194 304
! 1 ypl
~MHI
RESET
--------- -
Perlptlerals
Bild Memory
SOW
CKFS
__ J I
t
CDP6818 interfaced to competitor compatible multiplexed bus microprocessors.
~
Interrupt Request (IRQ)
Read/Wrne (R/WI
Address Strobe IASI
Data Strobe IDS)
T
CDP6805E2
-"
5 7 Non multiplexed address
5 Non-Multiplexed Address
K
A
~
OSCI
:I
J I
I
...
8 Multiplexed Address/ Data
U
~
r
OS
A12
Address
Decode
I
tV
I
DS
I
I
I
~
~
AS R/W IRO ADO·AD7
~
CDP6818
--
I
I
I
I
I
CE
RESET
CKOUT CKFS
-
This Illustrates the use of CMOS gating for address decoding
SOW
~
4.194304 MHz
ITyp)
~ t
Fig. 19 -- CDP6818 interface to CDP6805E2 CMOS multiplexed microprocessor with slow address decoding.
518 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6818
FIGURE 22 - SUBROUTINE FOR READING AND WRITING
THE CDP6818 WITH A NON-MULTIPLEXED BUS
READ
STA
LDAB
RTS
RTC
RTC+1
Generate AS and Latch Data from ACCA
Generate OS and Get Data
WRITE
STA
STAB
RTS
RTC
RTC+1
Generate AS and Latch Data from ACCA
Generate OS and Store Data
IMPORTANT APPLICATION NOTICE
application of power down circuitry. If CE is grounded at all
times (no power down required) the following circuit need not
be used.
The CDP6818 with a bottom brand code of 6RR requires a
synchronization of the CE pin with address strobe. The following circuit will satisfy that condition and also shows a typical
4
ADO
+5V
MBD701
(SCHOTTKY)
*
BBV
ADI
AD2
AD3
AD3
A04
A04
ADS
10
ADS
3·9V
IN4148
ADI
AD2
AD5
II
AD7
(Si)
14
AS
17
+
~
IS
R/W
STATEK
CXIV OR
EQUIVALENT
470 k
ADO
ascI
VDD
~~~----~--~
24
lOOK
ADS
AD7
AS
OS
PS
RESET
22
NOTES
All unused inputs of the CD? 4HC3?3 must be grounded.
18
R/W
00 equals 12 V pOint ® should be equal to 4.06 V
00 equals 10 V pOint ® should be equal
to 3.38 V with © set for 3.18 V.
50pF
2. If point
~
13
If pOint
'Battery Backup Voltage
CE
BBV
SET FOR
38V
1M
>0>---"-/''''
©
(SEE
NOTE
21
+SV
(SEE NOTE 1)
1M
92CM-37725
3910.
20 k
+12 V (>66 V) u---'\.tVv--....----'\.I\A~
@(SEE
®
NOTE 2)
Fig. 23 -
Typical Application Circuit
520 ______________ CMOS Microprocessors, Memories and Peripherals
CDP6823
MAXIMUM RATINGS (Voltages reference to VSSI
Ratings
Symbol
Supply Voltage
Value
All Input Voltages
Vin
Current Drain per Pin Excluding
VDD and VSS
Operating Temperature Range
V
VSS-0.5 to VDD+0.5
V
10
mA
I
o to
TA
Tstg
Storage Temperature Range
Unit
-0.3 to +8
VDD
+ 70
°C
-55 to +150
°C
THERMAL CHARACTERISTICS
Characteristics
Thermal Resistance
Ceramic
Plastic
Symbol
Value
Unit
6JA
50
100
°C/W
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields: however, it is
advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this high-impedance circuit. For proper operation It is
recommended that VI" and Vou• be constrained to the range Vss ~ (VI" or Vou.) ~
Vee. Leakage currents are reduced and
reliability of operation is enhanced if unused
Inputs are tied to an appropriate logic
voltage level (e.g., either Vss or Vee).
DC ELECTRICAL CHARACTERISTICS (VDD=5 Vdc ± 10%, VSs=O Vdc, TA=O°C to 70°C, unless otherwise noted)
Parameter
Symbol
Min
Max
Unit
VOL
VOH
-
0.1
VDD-0.1
-
V
V
Output High Voltage
(ILoad= -1.6 mAl ADD-AD7
(ILoad= -0.2 mAl PAD-PA7, PCO-PC7
(ILoad= -0.36 mAl PBO-PB7
VOH
VOH
VOH
4.1
4.1
4.1
VDD
VDD
VDD
V
Output Low Voltage
(ILoad= 1.6 mAl ADO-AD7, PBO-PB7
(ILoad=0.8 mAl PAD-PA7, PCO-PC7
ilLoad= 1 mAl IRQ
VOL
VOL
VOL
0.4
0.4
0.4
V
VIH
VIH
VSS
VSS
VSS
VDD 2.0
VDD-0.8
Output Voltage (ILoad",10 p.A)
Input High Voltage, ADO-AD7, AS, DS, R/W,
cr,
PAO-PA7, PBO-PB7, PCO-PC7
V
Input Low Voltage (All Inputs)
VIL
VSS
VDD
VDD
0.8
Quiescent Current - No de Loads
(All Ports Programmed as Inputs, Allinputs= VDD - 0.2 V)
IDD
-
160
p.A
Total Supply Current
(All Ports Programmed as Inputs, CE= VIL, tcye= 1 p.s)
IDD
-
iitS"ET
Input Current, cr, AS, R/W, DS, R'ES"ET
Hi-Z State Leakage, ADO-AD7, PAD-PA7, PBO-PB7, PCO-PC7
3
mA
lin
±1
p.A
ITSL
±10
p.A
VDD
TTL Equivalent
CMOS Equivalent
Test
Point 0 - -...
>-----.--+...- .....
C
TestPoint~
For all outputs except I R6
1
C=50 pF; All Ports
= 130 pF; ADD-AD7
for VDD=5 V ± 10%
':'
I
C
VDD
Pin
ADO-AD7
PAO-PA7, PCO-PC7
PBO-PB7
R2
C
2.55k
2k
130 pF
20k
4.32k
50 pF
2.1k
50 pF
R1
11.5k
,~,o,"'--l
I
iR'OOnly
Fig. 2 • Equivalent test loads.
V
4.02k
QOpF
522 _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6823
ALE (Address Latch Enablel
lAS Pinl
AD I Read Output Enablel
IDS Pinl
WR
IWrite Enablel
IR/WPinl
CE I Chip Enablel
ADO-AD7
IAddress/Data B..
uS.;..I_ _ _ _ _ _ _ _ _ _
-<
Fig. 4 - Bus READ timing competitor multiplexed bus.
ALE IAddress Latch Enablel
lAS Pinl
AD
I Read Output Enablel
IDS Pinl
INR IWrite Enablel
,
IR/iN'
_Pinl
_ _ _oJ
ADO-A07
I AddressICiat::,a_B.::;us~)_ _ _ _ _ _ _ _ _ _
-<
NOTE: VHIGH=VOD-2 V. VLOW=0,8 V. for VDO=5 V ± 10%
Fig. 5 - Bus WRITE timing competitor multiplexed bus.
Write Data
Valid
524 _______________ CMOS Microprocessors, Memories and Peripherals
CDP6823
GENERAL DESCRIPTION
The CDP6823, CMOS parallel interface (CPI), contains 24
individual bidirectional I/O lines configured in three 8-bit
ports. The 15 internal registers, which control the mode of
operation and contain the status of the port pins, are
accessed via an 8-bit multiplexed address/data bus. The
lower four address bits (ADO-AD3) of the multiplexed
address bus determine which register is to be accessed (see
Register Address Map shown below). The four address bits
(AD4, AD5, AD6, and AD?) must be separately decoded to
position this memory map within each 256-byte address
splice available via the 8-bit multiplexed address bus. For
more detailed information, refer to REGISTER DESCRIPTION.
REGISTER ADDRESS MAP
o
Port A Data, Clear CA 1 Interrupt
P1DA
Port A Data, Clear CA2 Interrupt
P2DA
2
Port A Data
PDA
3
Port B Data
PDB
4
Port C Data
PDC
Not Used
-
6
Data Direction Register for Port A
DDRA
Data Direction Register for Port B
DDRB
8
Data Direction Register for Port C
DDRC
9
Control Register for Port A
CRA
A
Control Register for Port B
CRB
B
Pin Function Select Register for Port C
FSR
C
Port B Data, Clear CB1 Interrupt
PlDB
o
Port B Data, Clear CB2 Interrupt
P2DB
Handshakel Interrupt Status Register
HSR
Handshake Over-Run Warning Register
HWR
Three data direction registers (DDRs), one for each port,
determine which pins are outputs and which are inputs. A
logic zero on a DDR bit configures its associated pin as an
input; and a logic one configures the pin as an output. Upon
reset, the DDRs are cleared to logic zero to configure all
port pins as inputs.
Actual port data may be read or written via the port data
registers (PDA, PDB, and PDC). Ports A and B each have
two additional data registers (P1 DA and P2DA - P1 DB and
P2DB) which are used to clear the associated handshake/interrupt status register bits (HSA 1 and HSA2 - HSB1
and HSB2), respectively. Port A may also be configured as
an 8-bit latch when used with CA 1. Reset has no effect on
the contents of the port data registers. Users are advised to
initialize the port data registers before changing any port
pin to an output.
Four pins on port C (PC4/CA 1, PC5/CA2, PC6/CB1, and
PC7/CB2) may additionally be programmed as handshake
lines for ports A and B via the port C function select register
(FSR). Both ports A and B have one input-only line and one
bidirectional handshake line each associated with them.
The handshake lines may be programmed to perform a
variety of tasks such as interrupt requests, setting flags,
latching data, and data transfer requests and/or acknowledgments. The handshake functions are programmed via
control registers A and B (CRA and CRB). Additional
information may be found in PIN DESCRIPTIONS,
REGISTER DESCRIPTION, or HANDSHAKE OPERATION.
MOTEL
The MOTEL circuit is a concept that permits the CDP6823
to be directly interfaced with different types of multiplexed
bus microprocessors without any additional external logic.
For a more detailed description of the multiplexed bus, see
MULTIPLEXED BIDIRECTIONAL ADDRESS/DATA BUS
(ADO-AD7). Most multiplexed microprocessors use one of
two synchronous buses to interface peripherals. An industry
standard bus structure is now available.
The MOTEL circuit is built into peripheral and memory ICs
to permit direct connection to either type of bus. The
MOTEL concept is shown logically in Fig. 7.
The CPI is implemented with the MOTEL circuit which
allows direct interface with either of the two major multiplexed microprocessor bus types. A detailed description of
the MOTEL circuit is provided in the MOTEL section.
6800 Family
MPU Signals
Competitor Type
MPU Signals
The microprocessor type is automatically selected by the
MOTEL circuit through latching the state of the DS!FfiJ pin
with AS/ALE. Since DS is always low during AS and RD is
always high during ALE, the latch automatically indicates
with which type microprocessor bus it is interfaced.
CDP6823
Pin Signals
Competitive Bus
D
AS
ALE
AS
Internal
Signals
Q
C
Q
Motorola
Bus
OS, E, or 01>2
OS
Read Enable
R/IN
R/IN
Write Enable
Fig. 7 - Functional diagram of MOTEL circuit.
526 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6823
To
And
From
CPU
Fig. 8 - Typical port 110 circuitry.
HANDSHAKE OPERATION) and latched input data may be
read via any of the three port A data registers. If the port A
input latch feature is not enabled, an MPU read of any portA
data register reflects the current status of the port A input
pins if the corresponding DDRA bits equal zero. Reset has
no effect upon the contents of the port A data register;
however, all pins will be placed in the input mode (all DDRA
bits forced to equal zero) and all handshake lines will be
disabled.
Port B Bidirectional 1/0 Lines (PBO·PB7)
Each line of port B, PBO·PB7, is individually programmable
as either an input or an output via its data direction register
(DDRB). An 1/0 pin Is an input when its corresponding DDR
bit is a logic zero and an output when the DDR bit is a logic
one.
There are three data registers associated with port B: PDB,
P1 DB, and P2DB. PDB is used for simple port B data reads
and writes. P1 DB and P2DB are accessed when certain
handshake activity is desired. See HANDSHAKE OPERA·
TION for more information.
Data written to PDB or P1 DB data register is latched into the
port B output latch regardless of the state of the DDRB. An
MPU read of port bits programmed as outputs reflect the
last value written to a port B data register. An MPU read of
any port B register reflects the current status of the input
pins whose DDRB bits equal zero. Reset has no effect upon
the contents olthe port B data register; however, all pins will
be placed in the input mode (all DDRB bits forced to equal
zero) and all handshake lines will be disabled.
Port C, Bidirectional 1/0 Lines (PCO·PC3)
Each line of port C, PCO·PC3, is individually programmable
as either an input or an output via its data direction register
(DDRC). An 1/0 pin is an input when its corresponding DDR
bit is a logic zero and an output when the DDR bit is a logic
one. Port C data register (PDC) is used for Simple port C
data reads and writes.
Data written into PDC is latched into the port C data latch
regardless of the state of the DDRC. An MPU read of port C
bits programmed as outputs reflect the last value written to
the PDC register. An MPU read of the port C register reflects
the current status of the corresponding input pins whose
DDRC bits equal zero. Reset has no effect upon the
contents of the port C data register; however, all pins will be
placed in the input mode (all DDRC bits forced to equal
zero) and all handshake lines will be disabled.
Port C Bidirectional 1/0 Line or Port A Input Handshake
Line (PC4/CA1)
This line may be programmed as either a simple port ClIO
line or as a handshake line for port A via the port C function
select register (FSR). If programmed as a port ClIO pin,
PC4/CA1 performs as described in the PCO·PC3 pin
description. If programmed as a port A handshake line,
PC4/CA 1 performs as described in HANDSHAKE OPERA·
TION.
Port C Bidirectional 1/0 Line or Port A Bidirectional
Handshake Line (PC5/CA2)
This line may be programmed as either a simple port ClIO
line or as a handshake line for port A via the port C function
select register (FSR). If programmed as a port ClIO pin,
PC5/CA2 performs as described in the PCO·PC3 pin
description. If programmed as a port A handshake line,
PC5/CA2 performs as described in HANDSHAKE OPERA·
TION.
Port C Bidirectional 1/0 Line or Port B Input Handshake
Line (PC6/CB1)
This line may be programmed as either a Simple port ClIO
line or as a handshake line for port B via the port C function
select register (FSR). If programmed as a port CliO pin,
PC6/CB1 performs as described in the PCO·PC3 pin
description. If programmed as a port B handshake line,
PC6/CB1 performs as described in HANDSHAKE OPERA·
TION.
Port C Bidirectional 1/0 Line or Port B
Bidirectional Handshake Line (PC7/CB2)
This line may be programmed as either a Simple port ClIO
line or as a handshake line for port B via the port C function
select register (FSR). If programmed as a port ClIO line,
PC7/CB2 performs as described in the PCO·PC3 pin
description. If programmed as a port B handshake line,
PC7/CB2 performs as described in HANDSHAKE OPERA·
TION.
528 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6823
Input Latch
REGISTER DESCRIPTION
Port A input-only handshake line (PC4/CA1) can be
programmed to function as a latch enable for port A input
data via CA 1 LE (bit 2 of CRA).lf CA 1 LE is programmed to a
logic one, an active transition of PC4/CA1 will latch the
current status of the port A input pins into all three port A
data registers (PDA, P1DA, and P2DA). When CA1 LE is
enabled, port A and PC4/CA 1 function as an 8-bit transparent latch; that is, ifthe HSA 1 bit in the HSR is a logic zero
then a read of any portA register reflects the current state of
the port A input pins and corresponding bits of the output
data latch for port A output pins. If HSA1 is a logic one, a
read of any port A data register reflects the state of the port
A input pins when HSA 1 was set and the corresponding bits
of the port A output data latch for port A output pins.
The CDP6823 has 15 registers (see Fig. 1) which define the
mode of operation and status of the port pins. The following
paragraphs describe these registers.
Further transitions of PC4/CA 1 result only in setting the
HWA1 bit in the HWR and do not relatch data into the portA
registers. Latched data is released only by clearing HSA1 in
the HSR to a logic zero (HSA1 is cleared by reading P1DA).
Register Names:
Control Register A (CRA)
Control Register B (CRB)
Register Addresses:
$9 (CRA)
$A (CRB)
Register Bits:
7
$9
$A
x
X
6
x
X
5
X
X
3
4
CA2
Mode
CB2
Mode
a
2
CAl
LE
CAl
Mode
X
Mode
CBl
Output
Each bidirectional handshake line programmed as an
output by the DDRC operates in one of four modes as
described in Table 3. Modes 2 and 3 force the output
handshake line to reflect the state of bit 4 in the appropriate
control register.
These two registers control the handshake and interrupt
activity for those pins defined as handshake lines by the
port C function select register (FSR).
In modes 0 and 1, PC5/CA2 is forced low during the cycle
following a read of P1 DA or a read of P2DA while HSA1 is
cleared. PC7 /CB2 is forced low during the cycle following a
write to P1DB or a write to P2DB while HSB1 Is cleared.
Because of these differences, port A is the preferred input
port and port B is the preferred output port.
CA2 and CB2 are programmed as inputs or outputs via the
associated DDRC bits. Each handshake line is controlled by
two mode bits. Bit 2 of CRA enables the Port A latch for an
active CA1 transition. Table 2 describes the input handshake
modes (CA 1, CB1, CA2, CB2) and Table 3 describes the
output handshake modes for CA2 and CB2.
In mode 0, PC5/CA2 (PC7/CB2) Is set high by an active
transition of PC4/CA1 (PC6/CB1). In mode 1, PC5/CA2
(PC7/CB2) is set high In the cycle following the cycle in
which PC5/CA2 (PC7/CB2) goes low. Mode 1 forces a lowgoing pulse on PC5/CA2 (PC7/CB2) following a read
(write) of P1DA (P1 DB) or P2DA (P2DB) that is approximately one cycle time wide.
Register Names:
When entering an output handshake mode for the first time
after a reset, the handshake line outputs the default level as
listed in Table 3.
Purpose:
Description:
Port A Data Registers (PDA, P1DA, P2DA)
Register Addrellel:
$2 (PDA), $0 (P1DA), $1 (P2DA)
Regllter Bits:
a
765432
I Bit 7 I Bit 6 I Bit 5 I Bit 4 I Bit 3 I Bit 2 I Bit 1 I Bit a I
INTERRUPT DESCRIPTION
Purpole:
The CDP6823 allows an MPU interrupt request (IRQ low)
via the Input handshake lines. The input handshake line,
operating in modes 1 or 3 as defined by the control registers
(CRA and CRB), causesTFfO to go low when IRQF (Interrupt
flag) In the HSR is set to a logic one.TFrCi is released when
IRQF is cleared. See Handshake/Interrupt Stltus Reglltar
under REGISTER DESCRIPTION for additional Information.
These three registers serve different purposes. PDA is used
to read input data and latch data written to the port A output
pins. P1 DA and P2DA are used to read input data and to
affect handshake and status activity for PC4/CA 1 and
PC5/CA2. If enabled, port A input data may be latched Into
the three port A data registers on an active PC4/CA1
transition as described In HANDSHAKE OPERATION.
.
530 --:-_ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6823
Aegllter Name:
Port C Data Register (PDC)
Purpo18:
The port C pin function select register defines whether the
multifunction port C pins are to operate as "normal" port C
lines or as handshake lines.
Aeglster Addresa:
$4
Aeglater Bltl:
765432
0
I Bit 7 I Bit 6 I Bit 5 I Bit 4 I Bit 3 I Bit 2 I Bit 1 I Bit 0 I
Purpo18:
The port C data register (PDC) is used to read Input data
and to latch data written to the output pins.
Description:
Data is written Into the port C output latch (see Fig. 3)
regardless of the state of DDRC. Any port C pin defined as a
handshake line by the port C function select register (FSR)
is not affected by PDC. Output pins, as defined by DDRC,
assume logic levels of the corresponding bits in the port C
output latch. A read of PDC reflects the contents of the
output latch for output pins and the current state of the
input pins (as reflected in the DDRC). Reset has no effect
upon the contents of PDC. Users are recommended to
initialize the port C output data latch before changing any
pin to an output via the DDRC.
Delcrlptlon:
A logiC zero in any FSR bit defines the corresponding port
C pin as a "normal" I/O pin. A logic one In any valid FSR bit
defines the corresponding port C pin as a handshake line.
Pins defined as handshake lines function according to the
contents of control register A (CRA) or control register B
(CRB). The port C data direction register (DDRC) is valid
regardless of FSR contents for all pins except PC4/CA 1 and
PC6/CB1. Transitions on port C pins not defined as
handshake pins do not effect the handshake/interrupt
status register. Reset clears all FSR bits to a logic zero.
Users are recommended to initialize the data direction and
control registers before modifying the FSR.
Aeglater Name:
Handshake/lnterrupt Status Register (HSR)
Aeglster Address:
$E
Aeglster Blta:
7
$6 ($7) ($8)
Aeglster Blta:
7
6
5
4
3
6
IIRQF I xx
Aeglater Name:
Data Direction Register for Port A (B) (C)
Aeglster Addreaa:
o
2
I Bit 7 I Bit 6 I Bit 5 I Bit 4 I Bit 3 I Bit 2 I Bit 1 I Bit 0 I
Purpose:
Each of the three data direction registers (DORA, DDRB,
and DDRC) define the direction of data flow of the port pins
for ports A, B, and C.
Description:
A logic zero in a DDR bit places the corresponding port pin
in the input mode. A logic one in a DDR bit places the
corresponding pin in the output mode. Any port C pins
defined as bidirectional handshake lines also use the port C
DDR (DDRC). Input-only handshake lines are not affected
by DDRC. Reset clears all DDR bits to logic zero configuring
all port pins as inputs. The DDRs have no write-inhibit
control over the port data output latches. Data may be
written to the port data registers even though the pins are'
configured as inputs.
$B
4
xx
3
2
1
0
I HSB21 HSA21 HSBl I HSAll
Purpose:
The handshake interrupt status register is a read-only flag
register that may be used during a polling routine to
determine if any enabled input handshake transition, as
defined by the control register (CRA and CRB), has
occurred.
Description:
If an enabled input handshake transition occurs then the
apPr:.2e!iate HSR bit (HSB2, HSA2, HSB1, or HSA 1) is set.
The TAO flag bit (bit7, IRQF) is set when one or moreof the
HSR bits 0-3 and their corresponding control register bits
are set to a logic one as shown in the following equation:
Bit 7=IRQF=[HSB2o CRB2(3)]+[HSA2 o CRA2(3)]
+[HSB1 o CRB1 (0)]+[HSA1 o CRA1 (0)]
The numbers in ( ) indicate which bit in the control register
enables the interrupt.
Handshake/interrupt status register bits are cleared by
accessing the appropriate port data register. The following
table lists the HSR bit and the port data register that must be
accessed. to clear the bit.
To Clear
HSR Bit
HSB2
. HSA2 ....
HSBl
HSAl
Aeglster Name:
Port C Pin Function Select Register (FSR)
Aeglster Address:
5
xx
Access
Register
· P2DB
· P2DA
...... P1DB
· P1DA
Aeglster Bits:
7
6
5
4
3
ICFB2 I CFBl ICFA21 CFAl I XX
o
2
xx
xx
xx
Reset clears all handshake/interrupt status register bits to a
logic zero.
532 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6823
CDP6823
Microcomputer
20
8
t:
0
0-
ADO-AD7
Ports
Address Strobe
Read
t:
Write
VSS_
Port
Lines
CA1
CB1
R/W
0
0-
J
AS
DS
CA2
CE
IRQ
...
I---
CB2 16RESET
! r
Fig. 10- CDP6823 interfaced with the ports of a typical single-chip microprocessor.
Port
Lines
534 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6848, CDP6848C
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Voo)
(Voltage referenced to vss terminal)
CDP6848 ........................................................................................................ -0.5 to +11 V
CDP6848C ....................................................................................................... -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ....................................................................... -0.5 to voo +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ................................................................................ ±10 mA
POWER DISSIPATION PER PACKAGE (Po):
For TA ; -40 to +60°C (PACKAGE TYPE E) ............................................................................ 500 mW
• For TA ; +60 to +85°C (PACKAGE TYPE E) ............................................... Derate Linearly at 12 mW/oC to 200 mW
For TA ; -55 to +100° C (PACKAGE TYPE D) ........................................................................... 500 mW
ForTA; +100 to 125°C (PACKAGE TYPE D) ............................................ Derate Linearly at 12 mW/oC to 200 mW
DEVicE DISSIPATION PER OUTPUT TRANSISTOR
For TA; FULL PACKAGE-TEMPERATURE RANGE (All Package Types ................................................. 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE D ............................................................................................ -55 to +125°C
PACKAGE TYPE E ..............................................................................................-40 to +85°C
STORAGE-TEMPERATURE RANGE (Tstg) ........................................................................ -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± in. (1.59 ± 0.79 mm) from case for 10 s max .......................................................... +265 0 C
STATIC ELECTRICAL CHARACTERISTICS at TA;-40 to +85°C, VDD ±5%, Except al noted
CONDITIONS
CHARACTERISTIC
Quiescent Device Current
Output low Drive
(Sink) Current
Output High Drive
(Source) Current
Output Voltage
Low-level
Output Voltage
High Level
Input Low Voltage
Input High Voltage
Input Leakage Current
100
IOl
IOH
Vo
(V)
VIN
(V)
VDD
(V)
-
.0,5
0, 10
0,5
0, 10
0,5
0, 10
0,5
0,10
0,5
0, 10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
0.4
0.5
4.6
9.5
VOl*
VOH*
-
-
0.5,4.5
VIL
0.5,9.5
0.5,4.5
VIH
0.5,9.5
Any
liN
Input
Operating Current
1001"
-
Input Capacitance
Output Capacitance
CIN
COUT
-
-
0,5
0, 10
0,5
o 10
-
"Typical values are for TA;25° C and nominal VDD.
-
-
-
LIMITS
CDP6848
CDP6848C
Min.
Typ.Typ.Min.
Max.
II....
-
50
200
4.9
9.9
0.01
1
3.2
5.2
-2.3
-5.2
0
0
5
10
-
-
1.5
3
3.5
7
-
-
-
-
±1
±2
3
12
7.5
15
1.6
2.6
-1.15
-2.6
-
-
1.5
6
5
10
-
-
-
0.02
200
-
-
1.6
3.2
-
-
-1.15
-2.3
~
-
-
0
0.1
-
-
0.1
0.1
-
-
4.9
5
-
-
3.5
-
-
*IOL ;IOH;1 /lA.
aOperating current is measured at 200 kHz for VDD;5 V and 400 kHz for VDD;10 V, with open outputs.
1.5
-
UNITS
pA
rnA
V
±1
-
1.5
3
-
-
5
10
7.5
15
pA
rnA
pF
536 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6848, CDP6848C
REGISTER TRUTH TABLE
ADDRESS
A2
A1
AO
ACTIVE
DS/WR
RD
1
1
0
1
1
0
0
1
1
X
1
0
0
0
0
1
0
1
X
X
1
1
0
0
1
1
1
0
0
1
1
1
1
1
1
0
0
1
X
Write Counter A MSB
X
0
Read Counter A MSB
Write Counter A LSB
X
Read Counter A LSB
Control
R~llter
A
Write Counter B MSB
X
X
Read Counter B MSB
Write Counter B LSB
X
X
Read Counter B LSB
Control.Regllter B
0
1
0
1
0
0
REGISTER OPERATION
X
X
Interrupl StatuI Regllter
Nol Used
Not Used
PROGRAMMING MODEL
Counler A Registers
Counter B Registers
BUS 7
BUS 0
BUS7
l
CONTROL REGI~TER
BUSO
I
CONTROL REGISTER
WRITE ONLY
WRITE ONLY
!
HOLDING REGISTER
LS~
WRITE ONLY
READ ONLY
IHOLDIN~
REGISTER
~A~+HR~SB:
I HRHST:ERH I
READ ONLY
MS~
I
~A~ R~GI:ST~R 7S~
I
HOLDING REGISTER Msa
Inlerrupl Stalus Register
BUS 7
BUS 0
WRITE ONLY
538 ______________ CMOS Microprocessors, Memories and Peripherals
CDP6848, CDP6848C
Bit 3 - Gate level select - All modes require an enabling
signal on the gate to allow counter operation. This enabling
signal is either a level or pulse (edge). Positive gate level or
edge enabling is selected by writing a "1" into this bit and
negative (low) enabling Is selected when bit 3 Is "0". The
gate level must betrue (Gate pin TAG orTBG = Bit3 Control
Register) when JAM Register Is loaded.
Blt4 -
Interrupt enable - Setting this bitto "1" enables the
TfiI'r output, and setting it to "0" disables it. When reset, the
INT output is at a high level. If the interrupt enable bit in the
control r~ster is enabled and the counter decrements to
zero, the1NT output will go low and will not return high until
the counter-timer is reset or the selected control register is
written to. Example: If timer B times out, control register B
must be accessed to reset the jji;j'T output high. If the
interrupt enable bit is set to "0", the counter's timeout will
have no effect on the TJiiIi output.
In mode 5, the variable-duty cycle mode, the INT pin will
become active low when the MSB in the counter has
decremented to zero.
Bit 5 - Start/stop control- This bit controls the clock input
to the counter and must be set to "1" to enable It. Writing a
"0" into this location will halt operation of the counter.
. Operation will not resume until the bit Is set to "1".
Bit 8 - Holding register control - Since the counter may be
decrementing during a read cycle, writing a "1" into this
location will hold a stable value in the hold register for
subsequent read operations. Rewriting a "1" Into bit 6 will
cause an update in the holding register on the next trailing
clock edge. If this location contains a "0", the holding
register will be updated continuously by the value in the
counter.
Blt7 -Jam enable-When this bit Issetto"1" during a write
tei the control register, the value In the jam register will be
placed Into the counter. The counter outputs TAO and TBO
will be set high and fAo and TBO will be set low on the next
trailing clock edge. If bit 0, 1, or 2 is equal to 1 (i.e. valid
mode) then counting begins with the next clock edge.
Setting this bit to "0" will leave the counter val ue unaffected.
This location should be set to "0" any time a write to the
control register must be performed without changing the
preset counter value.
I n mode 3, the hardware start is enabled by writing a "0" into
bit 7. If a "1" is written to bit 7, the timeout will start
immediately and mode 3 will resemble mode 1.
Changing Counter Values
Each counter must be stopped to reliably/load it from the
Jam Register. A counter can be stopped by:
• An external reset,
• TI me out in Modes 1, 2, and 3 (Modes 4 and 5 properly
reload and continue running at timeout),
• A write to the control register with Bit 7 = 0 (no JAM),
Bit 5 =1 (Start), and (Bit 2 + Bit 1 + Bit 0) =1 (valid
Mode select).
Once stopped, the counter can be jammed with a write to
the control register with Bit 7 = 1 (Jam), Bit 5 = 1 (Start), and
Bit 2 + Bit 1 + Bit 0) = 1. The Gate level must be true (match
the value written in the control register) in modes 1,2,4, and
5.
TX'O
NOTE: The outputs are cleared. (TXO =0 and
=1)
with a write to the control register with (Bit 2 + Bit 1 + Bit 0) =
1.
MODE DESCRIPTIONS
Control Aeallter
Qate Control
IxIxIxIxIxi 0 10111
Selectable
High or Low Level
Enables Operation
Mode
1
Timeout
BUS 7
BUSO
Mode 1:
After the count is loaded into the jam register and the
control register is written to with the jam-enable bit high,
TXO goes high and fXO goes low. The input clock
decreme.!ll!..the counter. When it reaches zero, TXO goes
low and TXO goes high, and if enabled, the interrupt output
is set low. When the control Is decremented to OOH, the
outputs (TAO and TAO) will change logic level, the next
clock will set the counter to FFFFH. Additional clocks are
ignored.
540 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6848, CDP6848C
Mode
Control Realster
lolxlxlxlxlol1111
Gate Controlled One Shot
3
Gate Control
Selectable
sPositive or Negative
~Oing Edge Initiates
Operation
BUSO
BUS 7
Mode 3:
After the jam register is loaded with the required value, the
~ edge will initiate this mode. TXO will be set high, and
TXO will be set low. The clock will decrement the counter.
When zero is reached, TXO will go low and TXO will be high,
and the interrupt output will be set low. The counter is
retriggerable: While the counter is decrementing, a gate
edge or write to the control register with the jam-enable bit
high, will load the counter with the jam register value and
restart the one-shot operation. The jam register value
cannot be changed for proper retriggering prior to timeout.
CLOCK
CON~OL----""
('-----f.J
REGISTER
r----...,
GATE
TXO
____~~----~~-.J
92CM-34630RI
Fig. 4 - Gate controlled one-shot (mode 3) timing waveforms.
Note:
I n order to avoid unwanted starts when selecting mode 3 or
Control Register
Mode
4
Rate Generator
4, the gate signal must be set to the opposite level that will
be programmed.
I xIxIxlxIxI11 oloi
Gate Control
Selectable
High or Low Level
Enables Operation
BUSO
BUS 7
Mode 4:
time between pulses equal to the counter's value, (trailing
edge to leading edge).
A repetitive clock-wide output pulse will be output, with the
o
COUNTER VALUE
o
CLOCK
WR
CONTROL
REGISTER
GATE
TXO
LOAD
COUN T
~
3
92CM- 34631RI
Fig. 5 - Rate generators (mode 4) timing waveforms.
542 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6848, CDP6848C
Function Pin Definition
DB7-DBO - 8 bit bidirectional bus used to transfer binary
information between the microprocessor and the dual
counter-timer.
VDD, VSS - Power and ground for device.
AO, A1, and A2 - Addresses used to select counters or
registers.
AS - Address Strobe, the addresses on Pins AO, A 1, and A2
are latched by the trailing edge of the signal on the address
strobe pin.
A high level on the mode select pin places the device in
mode = 1. This mode selects the CDP6805 ~cessor
interface. Write cycles are performed when DS/WR is high
and data is latched on the trailing edge ofthe signal (high to
low transition); RD/RD must be low. Read operations occur
when DSIWR is high; RDiRD must be high.
Note: All read and write cycles require that a valid address
was latched and CS is high.
TACL, TBCL - Clocks used to decrement the counter.
Mode - Controls data transfer to and from counter-timer.
The level on this pin determines the operation of the RD/RD
and DS/WR signals.
TAG, TBG - Gate inputs used to control counter.
RD/RD and DS/WR - A low level on the mode pin places
the device in mode = O. This mode is used when an 8085 type
processor is interfaced to the counter-timer. Active low
signals enable the pin functions. The device is written to
when DS/WR is low. Data is latched on the trailing edge
(low to high transition); RD/RO must be high. Read
operations occur when RD/RD is low; DS/WR must remain
high.
TBO, TBO - Complemented outputs of Timer B.
TAO, TAO -
Complemented outputs of Timer A.
INT - Common interrupt output. Active when counter
decrements to zero.
Active low~nal that resets counter outputs
(TAO, TBO low, TAO, TBO high). The interrupt output isset
high and the status register is cleared.
mE'f -
CS - Chip Select, an active high signal that enables the
device. It is not latched.
BUS TIMING (VDD = 5 Vdc ± 10%, Vss = 0 Vdc, TA = 0° to 70°C unless otherwise noted), see Figs. 8 and 10.
IDENTIFIER NO.
~
~
MIN.
MAX.
teye
953
DC
PWEH
325
-
CHARACTERISTIC
Cycle Time
Pulse Width DS/WR or RD/RD Low
(4)
Clock Rise and Fall Time
tr,tt
-
30
®
R/W Hold Time
tRWH
10
-
@
R/W Setup Time Before DS/WR
tRWS
15
-
@
Chip Select to Valid Read Data
tACS
400
-
@)
Chip Select Hold Time
tCH
0
-
fa)
Read Data Hold Time
tDHR
10
350
@
@
~
~
Write Data Hold Time
tDHW
50
-
j§L
Delay Time AS/ALE to DS/WR Rise
®
(31)
Note: Designations
Muxed Address Valid Time to AS/ALE Fall
tASL
60
-
Muxed Address Hold Time
tAHL
50
-
Pulse Width AS/ALE High
PWASH
100
-
tASED
90
-
Peripheral Output Data Delay Time From
DS/WR or RD
toDR
20
400
Peripheral Data Setup Time
tosw
100
ALE, RD and WR refer to signals from non-6805 type microprocessors.
-
UNITS
ns
544 ______________ CMOS Microprocessors, Memories and Peripherals
CDP6848, CDP6848C
ALE
1---------+1 AS
Ri5'
WR
AI5I-------~
RoiRD
DS/W'R
CS
OBO-D87
sose
MODE
CDP6848
Fig. 9 - Typical 8085 system using the CDP6848.
AS
RD/RD
DS/WlI
CS
DBO-DB7 _ _ _ _ _ _-{
AO,AI,A2
1------1
READ CYCLE
WRITE CYCLE
92CMM 31/)003
Fig. 10- Bus timing waveforms.
546 ________________ CMOS Microprocessors, Memories and Peripherals
CDP6848, CDP6848C
Example 3
TYPICAL OPERATION EXAMPLES (Conl'd)
Mode 2 (Time-out Strobe)
Condltlonl: A. Externa' Gale Pin = 1
B. Interrupt Disabled (Bit 4 = 0)
Operation: Befor. counter underflows, It
stopped and
r••tarted without changing Its value.
'I
05
COU NTER VALUE
04
03
02
02
02
01
00
02
02
CLOCK
WRITE TO
CONTROL
REGISTER
o
'Vr-----"'iLJ
TXO
92CM-36458
CD
®
®
o
®
Jam Regilter Is written
Msa = DOH. LSB
= OSH.
Load Control Register with AAH.
Load Control Register with OSH. Start/Slop Bit 5 " D,
Load Control Register with 28H.
Counter underflow. and return. high on next clock.
Fig. 13 - Timeout strobe (mode 2) timing waveforms.
Example 4
Mode 2 (Time-out Sirobe)
Condillone: A. Exlernal Qale PI" = 1
e. Interrupt Ol•• bled (Bit 4 .. 0)
Operation: Counter I, Ilopped and a new Jim Regllter valul
'I placed In counter before It underfiowi.
CLOCK
WAIT! TO
CONTROL
REGISTER
.------1~----~
TXO
CD
Jim Regilier I. written Msa .. OOHI LSB
®
Load Control Regl.ter with AAH.
II'
08H.
o
o
Jim Regllter I. 10lded MSI = 44HI LSI = 02H.
@
@
Load Control Regllter with AAH. Counter I. Enabled to Jam and Start.
Laid Conlrol Regllter wllh 08H. Counter I. Itopped.
Laid Control Regllter with 2AH to Slap.
Fig. 14 - Timeout strobe (mode 2) timing waveforms.
82CM- 36459
548 - - - - - - - - - - - - - _ CMOS Microprocessors, Memories and Peripherals
CDP6853
Prod'ucl Preview
RIW
CSO
28
voo
2
27
OS
26
25
11m
4
24
23
22
21
06
CSi
RES
RxC
07
CMOS Asynchronous Communications
Interface Adapter (ACIA) with MOTEL Bus
Features:
• Compatible with 8-bit microprocessors
XTLO
• Multiplexed Address/Data Bus (MOTEL Bus)
Ri'!l
• Full duplex operation with buffered receiver
9
20
~
and transmitter
TxO
10
19
AOI
• Data set/modem control functions
'DTI!
II
18
ADO
• Internal baud rate generator with 15
RxO
12
17
15!R'
programmable baud rates (50 to 19,200)
CE
13
~
16
• Program-selectable Internally or externally
14
AS
15
vss
controlled receiver rate
TOP VIEW
• Programmable word lengths, number of stop bits,
92C$-37023
and parity bit generation and detection
TERMINAL ASSIGNMENT
• Programmable interrupt control
' - - - - - - - - - - - - -..... Program reset
XTLr
6
7
8
05
04
03
02
The RCA-CDP6853 Asynchronous Communications Interface Adapter (ACIA) provides an easily implemented,
program controlled interlace between 8-bit microprocessorbased systems and serial communication data sets and
modems.
•
•
•
•
•
Program-selectable serial echo mode
Two chip selects
One chip enable
28-pin plastic or ceramic (DIP or DIC)
Full TTL compatibility
The CDP6853 has an internal baud rate generator. This
feature eliminates the need for multiple component support
circuits, a crystal being the only other part required. The
Transmitter baud rate can be selected under program
control to be either 1 of 15 different rates from 50 to 19,200
baud, or at 1/16 times an external clock rate. The Receiver The Control Register controls the number of stop bits, word
baud rate may be selected under program control to be length, receiver clock source and baud rate.
either the Transmitter rate, or at 1/16 times the external
clock rate. The CDP6853 has programmable word lengths The Status Register indicates the states of the 'i'RQ, i5SR,
of 5, 6, 7, or 8 bits; even, odd, or no parity; 1, 1'h, or 2 stop and OeD lines, Transmitter and Receiver Data Registers,
and Overrun, Framing and Parity Error conditions.
bits.
The CDP6853 is designed for maximum programmed control The Transmitter and Receiver Data Registers are used for
from the CPU, to simplify hardware implementation. Three temporary data storage by the CDP6853 Transmit and
separate registers permit the CPU to easily select the Receiver circuits.
CDP6853 operating modes and data checking parameters The MOTEL Bus allows interfacing to 6805 and 8085 type
multiplexed address data bus.
and determine operational status.
The Command Register controls parity, receiver echo The CDP6853 is supplied in 28-lead, hermetic, dual-in-line
mode, transmitter interrupt control, the state of the RTS side-brazed ceramic (0 suffix) and in 28-lead, dual-in-line
line, receiver interrupt control, and the state ofthe DTR line. plastic (E suffix) packages.
File Number
1487
550 _ _ _ _ _ _ _ _ _-'--_ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6853
02-07 (Data Bus) (20-25)
CDP8853 INTERFACE REQUIREMENTS
This section describes the interface requirements for the
CDP6853 ACIA. Fig. 1 is the Interface Diagram and the
Terminal Diagram shows the pin-out configuration for the
CDP6853.
The D2-D7 pins are the eight data lines used to transfer dala
between the processor and the CDP6853. These lines are
bi-directional and are normally high-impedance except
during Read cycles whE!n the CDP6853 is selected.
CE, CSO, CS1 (Chip Selects) (2,3,13)
The two chip select and the one chip enable inputs are
normally connected to the processor address lines either
directly or through decoders. The CDP6853 is selected
when CSO is high, CS1 is low, and CE is high,
02·07
AOO,A01
TxO
RxC
XTLI
XTLO
RxO
ADO, AD1 (Multiplexed Bidirectional Address/Data Bill)
(18,19)
Multiplexed bus processors save pins by presenting the
address during the first portion of the bus cycle and using
the same pins during the second portion for data. Addressthen-data multiplexing does not slow the access time of the
CDP6853 since the bus reversal from address to data is
occurring during the internal RAM access time,
The address must be valid just prior to the fall of AS/ALE at
which time the CDP6853 latches the address from ADO to
AD1. Valid write data must be presented and held stable
during the latter portion of the DS or WR pulses. In a read
cycle, the CDP6853 outputs 8 bits of data during the latter
portion of the DS or RD pulses, then ceases driving the bus
(returns the output drivers to three-state) when DS falls in
this case of MOTEL or RD rises in the other case. The
following table shows internal register select coding:
TABLE I
AD1
0
ADO
0
0
1
1
1
0
1
92CM·37024
Fig. 1 - CDP6853 interface diagram.
MICROPROCESSOR INTERFACE
SIGNAL DESCRIPTION
RES (Reset) (4)
During system initialization a low on the RES input will
cause a hardware reset to occur. The Command Register
and the Control Register will be cleared. The Status
Register will be cleared with the exception of the indications
of Data Set Ready and Data Carrier Detect, which are
externally controlled by the i5S'R and i5CEi lines, and the
transmitter Empty bit, which will be set.
R/W (Read/Write) (1)
The MOTEL circuit treats the R/W pin in one of two ways,
When a 6805 type processor is connected, R/W is a level
which indicates whether the current cycle is a read or write.
A read cycle is indicated with a high level 0ILR/W while DS is
high, whereas a write cycle is a low on R/W during DS.
The sl!£2.nd iEtt£retati~ R/W is as a negative write
pulse, WR, M
, and I/OW from competitor ,!ype processors. The MOTEL circuit in this mode gives RlW pin the
same meaning as the write (W) pulse on many generic
RAMs,
IRQ (Interrupt Request) (28)
The IRQ pin is an interrupt outputfrom the interrupt control
logic. It is an open drain output, permitting several devices
to be connected to the commonlRtfmicroprocessor input.
Normally a high level, 1m:i goes low when an interrupt
occurs.
Write
Read
Transmit Data
Receiver Data
Reaister
Reaister
Programmed Reset
Status Register
(Data is "Don't
Care")
Command Reaister
Control Rea ister
Only the Command and Control registers are read/write.
The programmed Reset operation does not cause any data
transfer, but is used to clear bits 4 through 0 in the
Command register and bit 2 in the Status register. The
Control Register is unchanged by a Programmed Reset. It
should be noted that the Programmed Reset is slightly
different from the Hardware Reset (RES); these differences
are shown in Figs. 4, 5, and 6.
ACIA/MODEM INTERFACE
SIGNAL DESCRIPTION
XTLI, XTLO (Cryltal Plnl) (8,7)
These pins are normally directly connected to the external
crystal (1.8432 MHz) used to derive the various baud rates
(see "Generation of Non-Standard Baud Rates"). Alternatively, an' externally generated clock may be used to drive
the XTLI pin, in which case the XTLO pin must float. XTLI is
the input pin for the transmit clock.
TxD (Transmit Data) (10)
The TxD output line is used to transfer serial NRZ
(nonreturn-to-zero) data to the modem. The LSB (least
significant bit) of the Transmit Data Register is the first data
bit transmitted and the rate of data transmission is
determined by the baud rate selected or under control of an
external clock'. This selection is made by programming the
Control Register.
552 ______________ CMOS Microprocessors, Memories and Peripherals
CDP6853
CDP8853 INTERNAL ORGANIZATION
This section provides a functional description of the
CDP6853. A block diagram of the CDP6853 is presented In
Fig. 3.
eTS
02·07
ToO
ADO.AD1
oeD
D8A
Roe
XTLI
XTLO
DTR
m
AoD
92CM-37026
Fig. 3 - Internal organization.
DATA BUS BUFFERS
The Data Bus Buffer Interfaces the system data lines to the
internal data bus. The Data Bus Buffer Is bi-dlrectlonal.
When the R/Wline Is high and the chip is selected, the Data
Bus Buffer passes the data to the system data lines from the
CDP6853 internal data bus. When the R/W line is low and
the chip is selected, the Data Bus Buffer writes the data from
the system data bus to the internal data bus.
INTERRUPT LOGIC
The Interrupt Logic will cause the iRQ line to the microprocessor to go low when conditions are met that require
the attention of the microprocessor. The conditions which
can cause an Interrupt will set bit 7 and the appropriate bit of
bits 3th rough 6 in the Status Register If enabled. Bits 5and 6
correspond to the Data Carrier Detect (0CDi logic and the
Data Set Ready (DSR) logic. Bits 3 and 4 correspond to the
Receiver Data Reglsterfull and the Transmitter Data Register
empty conditions. These conditions can cause an interrupt
request If enabled by the Command Register.
I/O CONTROL
The I/O Control Logic controls the selection of internal
registers in preparation for a data transfer on the internal
data bus and the direction of the transfer to or from the
register.
The registers are selected by the Register Select and Chip
Select and Read/Write lines as described in Table I,
previously.
TIMING AND CONTROL
The Timing and Control logic controls the timing of data
transfers on the internal data bus and the registers, the Data
Bus Buffer, and the microprocessor data bus, and the
hardware reset features.
Timing is controlled by the system 1/>2 clock Input. The chip
will perform data transfers to or from the microcomputer
data bus during the 1/>2 high period when selected.
All registers will be initialized by the Timing and Control
Logic when the Reset (RES) line goes low. See the individual
register description for the state of the registers following a
hardware reset.
TRANSMITTER AND RECEIVER
DATA REGISTERS
These registers are used as temporary data storage for the
CDP6853 Transmit and Receive Circuits. Both the Transmitter and Receiver are selected by a Register Select 0
(RSO) and Register Select 1 (RS1) low condition. The
Read/Write line determines which actually uses the Internal
data bus; the Transmitter Data Register is write only and the
Receiver Data Register is read only.
Bit 0 is the first bit to be transmitted from the Transmitter
Data Register (least significant bit first). The higher order
bits follow in order. Unused bits in this register are "don't
care".
The Receiver Data Register holds the first received data bit
In bit 0 (least significant bit first). Unused high-order bits
are "0". Parity bits are not contained In the Receiver Data
Register. They are stripped off after being used for parity
checking.
STATUS REGISTER
Fig.4 indicates the format of the CDP6853 Status Register.
A description of each status bit follows.
554 _ _ _ _ _ _ _ _......_ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6853
CDP6551 INTERNAL ORGANIZATION (Cont'd)
COMMAND REGISTER
Parity Mode Control (Bits 6,7)
The Command Register controls specific modes and
functions.
These bits determine the type of parity generated by the
Transmitter, (even, odd, mark or space) and the type of
parity check done by the Receiver (even, odd, or no check).
Fig. 6 shows the possible bit configurations for the Parity
Mode Control bits.
Data Terminal Ready (Bit 0)
This bit enables ali selected interrupts and controls the
state of the Data Terminal Ready (DTR) line. A "0" indicates
the microcomputer system is not ready by setting the DTR
line high. A "1" indicates the microcomputer system is
ready by setting the DTR line low.
TRANSMITTER AND RECEIVER
Bits 0-3 of the Control Register select divisor used to
generate the baud rate for the Transmitter. If the Receiver
clock is to use the same baud rate as the transmitter, then
RxC becomes an output and can be used to slave other
circuits to the CDP6853. Fig. 7 shows the transmitter and
Receiver layout.
Receiver Interrupt Control (Bit 1)
This bit disables the Receiver from generating an interrupt
when set to a "1". The Receiver interrupt is enabled when
this bit is set to a "0" and Bit 0 is set to a "1".
....-.....,--RxO
Transmitter Interrupt Control (Bits 2,3)
These bits control the state of the Ready to Send (RTS) line
and the Transmitter interrupt. Fig. 6 shows the various
configurations of the RTS line and Transmit Interrupt bit
settings.
Receiver Echo Mode (Bit 4)
~-----------RXC
This bit enables the Receiver Echo Mode. Bits 2 and 3 must
also be zero. In the Receiver Echo Mode, the Transmitter
returns each transmission received by the Receiver delayed
by'h bit time. A "1" enables the Receiver Echo Mode. A "0"
bit disables the mode.
XTL1
XTLO
Parity Mode Enable (Bit 5)
This bit enables parity bit generation and checking. A "0"
disables parity bit generation by the Transmitter and parity
bit checking by the Receiver. A "1" bit enables generation
and checking of parity bits.
7
TxO
92CS -36791
Fig. 7 - Transmitter receiver clock circuits.
8
PMC
PMC1 PMea
;'
PMe
I
I REM
TIC
TIC1
TICO
L,--l
IRQ
IDTRJ
L
(lrrA)
DATA TERMINAL READY
0- DATA TERMINAL NOT READY IDTR HIGH)
1 - DATA TERMINAL READY (OTR LOW)
RE~YER INTERRUPT CONTROL (filii)
o • IRQ ENABLED
DISABLED
1•
nm
' - - - - - - TRANSMITTER INTERRUPT CONTROL (TIC)
~ 5m - HIGH, TRANSMIT INTERRUPT DISABLED*
o
m-
1
LOW, TRANSMIT INTERRUPT ENABLE
1 0 In'I- LOW, TRANSMIT INTERRUPT DISABLED
1 1 m - LOW, TRANSMIT INTERRUPT DISABLED
TRANSMIT. 8REA~ ON, T x D
RECEIVER ECHO MODE (REM)
0- RECEIVER NORMAL MODe
1 - RECEIVER ECHO MODE*
' - - - - - - - - - - - PARITY MODE ENABLE (PME)
0- PARITY MODE DISABLED
NO PARITY 81T GENERATED
PARITY CHECK DISABLED
1 - PARITY MODE ENABLED
L -_ _ _ _ _ _ _ _ _ _ _ _ PARITY MODE CONTROL (PMC)
~8
ODD PARITY TRANSMITTED/RECEIVED
o 1 EYEN PARITY TRANSMITTED/RECEIYED
1 0 MARK PARITY BIT TRANSMITTED
PARITY CHECK DISABLED
1 1 SPACE PARITY BIT TRANSMITTED
PARI:ry CHECK DISABLED
• BITS 2 AND 3 MUST BE ZERO FQR RECEIYER ECHO MODE. 1Iiii WILL BE LOW.
92CM- !6790
Fig. 6 - CDP6863 command register.
556 ________________ CMOS Microprocessors, Memories and Peripherals
CDP6853
CDP6853 OPERATION (Confd)
Transmit Data Register Not Loaded
By Procellor (Fig. 10)
If the processor is unable to load the Transmit Data Register
in the allocated time. then the TxD line will go to the
CONTINUOUS "MARK"
CHAR #n
/r--------LI------~,
n ISTARTEJ:1T~:EEJ
STOP
TxD
iliQ
"MARK" condition until the data is loaded. When the
processor finally loads new data, a Start Bit immediately
occurs, the data word transmission is started, and another
interrupt is initiated, signaling for the next data word.
CHAR#n+1
CHAR#n+2
/~------~---------,/~------~---------
STOP
STOP
I
rqq]~EJ
ISTART
I
-------'rn
--, m,
L-W
I
[%Ia;-[~
ISTART
Urrr--
PRocLSO"1
INTERRUPT
FOR DATA
REGISTER
EMPTY
WHEN PROCESSOR FINALLY LOADS
NEW DATA, TRANSMISSION STARTS
IMMEDIATELY AND INTERRUPT
OCCURS, INDICATING TRANSMIT
DATA REGISTER EMPTY
PROCESSOR
READS
STATUS
REGISTER
92CM- 36794
Fig. 10- Transmit data register not loaded by processor.
Effect of CTS on Transmitter (Fig. 11)
CTS is the Clear-to-Send Signal generated by the modem.
It is normally low (True State) but may go high in the event
of some modem problems. When this occurs, the TxD line
immediately goes to the "MARK" condition. Interrupts
CHAR#n
I
CHAR#n+1
I
·0 1 ., ·1
continue at the same rate, but the Status Register does not
indicate that the Transmit Data Register is empty. Since
there is no status bit for CTS, the processor must deduce
that CTS has-ll.2.!Je to the FALSE (high) state. This is
covered later. CTS is a transmit control line only, and has no
effect on the CDP6853 Receiver Operation.
CONTINUOUS "MARK"
,
I
/
·'~I
••:
.1--1
BN...L-I.....L.-IST---!-opIST--JARTI_Bo.1...-1
I
NOT CLEAR-To-SEND
CLEAR-TO'SEND
/
eTS GOES HIGH.
INDICATING MODEM
IS NOT READY TO
RECEIVE DATA. Tx 0
IMMEDIATELY GOES
TO "MARK" CONDITION
Fig. 11 - Effect of eTS on transmitter.
NEXT
PROCESSOR
INTERRUPT
AT NORMAL
START BIT
TIME
PROCESSOR READS
STATUS REGISTER.
SINCE DATA REGISTER
IS NOT EMPTY, PROCESSOR
MUST DEDUCE THAT
EfS IS SOURCE OF
INTERRUPT (THIS IS
COVERED ELSEWHERE
IN THIS NOTE).
92CM-36795
558 ______________ CMOS Microprocessors, Memories and Peripherals
CDP6853
CDP8853 OPERATION (Cont'd)
Effect of CTS on Echo Mode Operation (Fig. 14)
way as "Effect of CTs on Transmitter". In this case,
however, the processor interrupts signify that the Receiver
Data Register is full, so the processor has no way of
knowing that the Transmitter has ceased to echo.
See "Effect of CTS on Transmitter" for the effect of CTS on
the Transmitter. Receiver operation is unaffected by CTS,
so, in Echo Mode, the Transmitter is affected in the same
CHAR#n
_ _, /
CHAft#n+1
I
,/
STOP
I~
---uu
fA"O
,/
STOP
Jl GGT-bE] I
RxD
CHAR#n+2
'
STOP
I
GGI~9iJ
CHAR#n+3
,/~_ _ _ _LI_ _ __
I
STOP
I [BOGIE[
[BJ"BtI~:GEJ
I~
I~
I~
LlO
LlO
LllJITT"--
NOT'CLEAR-TQ-SENO
1
I
)
STOP
STOP
1 IBoIB,IB·11
=:JL.GEII BN 1
TxD
P
L~
START
CTS GOES TO
"FALSE" CONDITION
NORMAL
RECEIVER DATA
I
REGISTER FULL
INTERRUPTS
92CM-36798
Fig. 14 - Effect of C'i'S on echo mode.
Overrun In Echo Mode (Fig. 15)
If Overrun occurs in Echo Mode, the Receiver is affected the
same way as described in "Effect of Overrun on Receiver".
Forthe re-transmitted data, when overrun occurs, the TxD
line goes to the "MARK" condition until the first Start Bit
after the Receiver Data Register is read by the processor.
CHAR #n
-------./
CHAR #x
"
STOP
/
STOP
RXDD
~ELGEJ
I
I~
nffi
STOP
I
11
LlO
/LlO
LJ]]'
l~pl
TXD~EEJ
I
START
PROCESSOR
INTERRUPT
FOR RECEIVER
~
PROCESSOR
DOES NOT ~
READ RECEIVER
DATA REGISTER
DATA REGISTER
FULL
PROCESSOR
READS
STATUS
REGISTER
+1
' / , -_ _ _ _.L,_ __
STOP
GREG
~
CHAR #x
I
GGTI~G
I
~
[%G]~~
~
LllJITr---
,/
START
I~]~;r
I
PROCESSOR FINALLY
READS RECEIVER
DATA REGISTER,
LAST VALID
CHARACTER (#n)
OVERRUN OCCURS
Tx DGOESTO
"MARK"
CONDITION
PROCESSOR
INTERRUPT
FOR CHAR #x
IN RECEIVER
DATA REGISTER
92CM-36788
Fig. 15 - Overrun In echo mode.
1
Tx D DATA
RESUMES
560 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP6853
CDP6853 OPERATION (Cont'd)
Timing with 1'1. Stop Bltl (Fig. 18)
5-bit data words with no parity bit. In this case, the
processor Interrupt for Receiver Data Register Full occurs
in halfway through the trailing half-Stop Bit.
It is possible to select 1V. Stop Bits, but this occurs only for
CHAR#n
~
CHAR#n+1
_ _ _ _ _--"''-_ _ _ _ _~
I
RxD
L
Lill
1
PROCESSOR INTERRUPT
OCCURS HALFWAY
92CM- 36781
THROUGHTTHE 1/2
STOP BIT
Fig. 18 - Timing with 1-112 stop bits.
At least one full "BREAK" character will be transmitted,
even if the processor quickly re-programs the Command
Register transmit mode. Later, when the Command Register
is programmed back to normal transmit mode, a Stop Bit
will occur from one to fifteen clock periods at the next bit
time.
Tranlmlt Continuous "BREAK" (Fig. 19)
This mode is selected via the CDP6853 Command Register
and causes the Transmitter to send continuous "BREAK"
characters after both the transmitter and transmitter-holding
registers have been emptied.
n
/~----------~~/~------
STOP
TxD
STOP
I
~~::EdiJ
ISTART
STOP
I BO
81, _
aN
P
STOP
I~G
STOP
START
II G"Gl
START
r-rr-----;
WHI~
1-------1- PERIOD DURING
WHICH PROCESSOR
SELECTS
CONTINUOUS
"BREAK" MODE
NORMAL
INTERRUPT
POINT AT
PROCESSOR
SELECTS
NORMAL
TRANSMIT
MODE
/
PROCESSOR
INTERRUPT
TO LOAD
TRANSMIT
DATA
92CM-36785
Fig. 19 - Transmit continuous "BREAK".
characters, the CDP6853 will terminate receiving.'Reception
will resume only after a Stop Bit is encountered by the
CDP6853.
Receive Continuous "BREAK" (Fig. 20)
In the event the modem transmits continuous "BREAK"
/
-------~~
..--.-_T'ST.:..:O",P
Rx0
E~EL:J
I
I
CONTINUOUS "BREAK"
I BO I 81
START
I BN I P ,STOP,
..............-
STOP
1-'--<;
........
I ,I;,
PROCESSOR
INTERRUPT
WITH FRAMING
ERROR (PARITY
AND OVERRUN
CHECKS NORMAL)
I
~E1j
l
------,r-u,..----~~l!:~
PROCESSOR
INTERRUPT
FOR
RECEIVER
DATA REGISTER
FULL
,/~------
STOP
I
I
START
'<
NO INTERRUPT
SINCE RECEIVER
DISABLED UNTIL
FIRST STOP BIT
Fig. 20 - Receive continuous "BREAK".
92CM- 36784
I I I
80
START
81
....---
NORMAL
RECIEVER
INTERRUPT
562 ________________ CMOS Microprocessors, Memories and Peripherals
CDP6853
CDP6853 OPERATION (Cont'd)
Table II - Divisor Selection for the CDP6853
3
0
CONTROL
REGISTER
BITS
2
1
0
0
DIVISOR SELECTED
FOR THE
INTERNAL COUNTER
BAUD RATE GENERATED
WITH 1.8432 MHz
CRYSTAL
0
0
No Divisor Selected
0
0
0
1
36,864
0
0
1
0
24,576
0
0
1
1
16,768
0
1
0
0
13,696
0
1
0
1
12,288
0
1
1
0
6,144
16 x External Clock at Pin R x C 16 x External Clock at Pin R x C
1.8432 x 10·
F
50
36864
36864
F
1.8432 x 10'
75
24576
24576
F
1.8432 x 10'
109.92
16768
16768
F
1.8432 x 10'
13696
13696 - 134.58
1.8432 x 10·
F
150
12288
12288
1.8432 x 10·
F
300
6144
6144
=
=
=
=
=
1.8432 x 10·
0
1
1
1
3,072
3072
1.8432 x 10'
1.
O.
0
0
1,536
1536
1.8432 x 10'
1
0
0
1
1,024
1024
1.8432 x 10'
1
0
1
0
768
768
1.8432 x 10'
1
0
1
1
512
512
1.8432 x 10·
1
1
0
0
384
384
1.8432 x 10'
1
1
0
1
256
1
1
1
0
192
= 7200
256
1.8432 x 10·
= 9600
192
600
= 1200
= 1800
= 2400
= 3600
= 4800
1.8432 x 10·
1
1
1
BAUD RATE GENERATED
WITH A CRYSTAL
OF FREQUENCY (F)
1
96
96
= 19200
F
3072
F
1536
F
1024
F
768
F
512
F
384
F
256
F
192
F
96
The CDP6853 does not contain automatic . loop-back
operating modes, but they may be implemented with the
addition of a small amount of external circuitry.
PR~~ERS~-OR
Fig. 22 indicates the necessary logiC to be used with the
I--_----t------
f-
I •
p.
92CM-36263
Fig. 4 - Low VDD data retention timing waveforms.
/1 A
ns
580 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDM6117A-3
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Voo):
(All voltage values referenced to Vss terminal) ...................................................................... -0.3 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ............................................................................. -0.3 to +7 V
POWER DISSIPATION PER PACKAGE (Po):
For TA = O· to +60· C ................................................................................................. 500 mW
For TA = +60 to +70·C .................................................................. Derate Linearly at 12 mW/·C to 380 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
ForTA = FULL PACKAGE-TEMPERATURE RANGE .................................................................... 100 mW
OPERATING-TEMPERATURE RANGE (TA) ........................................................................... Oto +70·C
STORAGE TEMPERATURE RANGE (T.'9) ........................................................................ -55 to +125·C
LEAD TEMPERATURE (DURING SOLDERING):
At distsnce 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ..................................................... +265·C
OPERATING CONDITIONS at TA = 0° to +70°C
For maximum reliability, operating conditions should be selected so that operation Is always within the following ranges:
LIMITS
CDM6117A-3
UNITS
CHARACTERISTIC
Min.
Max.
4.5
5.5
VIH
2.2
voo +0.3
VIL
-0.3
0.8
tr, If
-
5
DC Operating Voltage Range
Input Voltage Range
Input Signal Rise or Fall Time
/j.
/j.
V
ps
Input signal rise and fall times longer than the maximum value can cause loss of stored data in the selected mode.
STATIC ELECTRICAL CHARACTERISTICS at TA
= 0 to +70°C, VDD = 5 V ± 10%, Except as noted
LIMITS
CDM6117A-3
CHARACTERISTIC
CONDITIONS
UNITS
Min.
Standby Device
Current
CE = VIH
-
IOOS1
CE = voo -0.2 V
-
IOL = 2.1 mA
-
IOL = 11lA
-
0.1
-
IOH = -1 mA
2.4
-
IOH = -1 IlA
-
Voo -0.1
-
-
±0.1
±2
-
±O.5
±2
-
20
35
-
4
6
-
6
8
VOL Max.
Output Voltage
High Level
VOH Min.
Input Leakage
Current
voo = 5.5 V
liN Max.
3-State Output
Leakage Current
Operating Device Current
lOUT
IOPER#
VI/O = 0 V to Voo
VIN
=VIL, VIH
VIN = 0 V,
CIN
Output
CapaCitance
VIN = 0 V to voo
CS or CE = VIH
Input
Capacitance
Max.
loos
Output Voltage
Low-Level
Typ.-
CliO
= 1 MHz, TA = 25° C
VI/O =0 V,
f = 1 MHz, TA =25° C
f
-Typical values are for TA = 25° C and nominal Voo.
#Outputs open circuited; cycle time = Min. tcycle, duty = 100%.
0.6
2
mA
1
50
IlA
-
0.4
-
V
V
IlA
mA
pF
582 ________________ CMOS Microprocessors, Memories and Peripherals
CDM6117A-3
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 0 to +70·C, VDD = 5 V ± 10%,
Input tr, If =10 ns; CL =100 pF and 1 TTL Load, Input Pulse Levels: 0.8 V to 2.4 V
Write Cycle Times See Fig. 3
LIMITS
CDM6117A-3
CHARACTERISTIC
UNITS
'-
Mln.t
Max.
Write Cycle Time
twc
150
-
Chip Select (CS) to End of WRITE
tcsw
90
-
Chip Enable (CE) to End of WRITE
tcEW
90
-
Address Width
tAW
90
Address Setup Time
lAS
0
Write Enable Width
tww
90
-
Input Data Setup Time
tDW
50
-
Address Hold Time
tWR
0
-
Input Data Hold Time
tDH
5
-
Output Active From End of Write
tow
10
-
Write Enable to Output "High Z"
tWHZ
0
40
tTime required by a limit device to allow for the indicated function.
WRITE CYCLE 1 - CS, CE CONTROL
'wc---------i
ADDRESS
DATA OUT ~~l1~~tt]-----------------~----~------------~~~
:~A~~NTROL·---------------------~-------------~'P"-"~---.2-C-M--.-.2.1
WRITE CYCLE 2 _
~-----'wc-------~
ADDRESS
Fig. 3 - Wrlte·cyc/e timing waveforms.
ns
584 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDM6118A-3
..
A7
AS
2
23
A8
A.
3
22
A.
A.
21
\VI!
A3
20
rn
A2
18
"
en
AO
17
%./OB
I/O I
IS
1/07
10
"
I/Oa
12
"
13
tlO!
VSS
Fe.ture.:
•
•
•
•
•
•
Fully static operation
Single power supply: 4.5 V to 5.5 V
All Inputs and outputs directly TTL compatible
3-state outputs
Industry standard 24-pln configuration
Fast access time for systems with common or
separate read/write: tAce = 150 ns
• Low standby and operating power: loos! =1 pA typica/~
maximum
• Data retention voltage = 2 V min.
• Operating temperature range (max. rating): O' to 70'C
AIO
AI
1/02
CMOS 2048-Word by 8-Bit
Static RAM
VDD
I/O&
:tI04
TOP VIEW
92CS-36402
TERMINAL ASSIGNMENT
The RCA-CDM6118A-3 Is a 2048-word by 8-bit static
random-access memory. It is designed for use in memory
systems where high-speed, low power and simplicity in use
are desirable. This type has common data Input and data
output and utilizes a single power supply of 4.5 V to 5.5 V.
10PER
=35 mA
The Input address buffers are gated off by either chip
enable input for minimum standby power with inputs
toggling.
The CDM6118A-3 is supplied In a 24-lead, dual-in-line
plastic package (E suffix).
AID
A9
I/08
A8
1/07
INPUT
ADDRESS
BUFFERS
A7
A6
XY
DECODE
I NPUTI
OUTPUT
DATA
BUFFERS
12hl28
MEMORY
MATRIX
A5
I/06
:1:/05
1/04
A4
1103
A3
:1:102
A2
1/01
AI
AO
-'YDD
Fig. 1 - Functional block diagram.
TRUTH TABLE
........ Yss
•• eM-3S'03
CE1
CE2
WE
AO TO A10
MODE
DATA 110
DEVICE
CURRENT
H
X
A
A
HIGHZ
STANDBY
X
H
A
A
NOT
SELECTED
NOT
SELECTED
HIGHZ
STANDBY
L
L
H
STABLE
READ
DATA OUT
ACTIVE
L
L
L
STABLE
WRITE
DATA IN
ACTIVE
L = LOW
H = HIGH
X = H or L, A = L, H or HIGH Z.
File Number 1508
586 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDM6118A-3
Signal Description
AO-A10
Address Inputs. These inputs must be stable
prior to a Write operation but may change
asynchronously during Read operations.
1/0,-1/08 S-bit tri-state data bus.
CEl, CE2 Chip Enable. When either CEr or CE2 is not
true, the Read and Write functions are
disabled, address and o'utput buffers are
gated off, and the chip is powered down to
the low power standby mode.
Write Enable. Controls Read and Write
functions If CE1 and CE2 are low. When
WE=CE1=CE2=0, the bus will be trl-stated
and a Write will occur. When m=1,
'C'Ei=CE2=0, a Read operation occurs.
'Voo, Vss Power Supply connections.
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 0 to +70 oC, Voo = 5 V ± 10"10,
Input til tf = 10 ns; CL = 100 pF and 1 TTL Load, Input Pulse Level.: 0.8 V to 2.4 V
Read Cycle Time. See Fig. 2
LIMITS
CDM6118A-3
CHARACTERISTIC
MIN.t
UNITS
MAX.
150
150
tACE2
-
Chip Enable (CE1) to Output Active
tCLZ'
15
-
Chip Disable (CE1) to Output High Z
tCHZ'
0
50
Chip Enable (CE2) to Output Active
tCLZ2
15
-
tCHz2
0
50
tOH
15
-
Read Cycle Time
tRC
Address Access Time
IAcc
Chip Enable (CE1) Access Time
tACE'
Chip Enable (CE2) Access Time
Chip Disable (CE2) to Output High Z
Output Hold Time
150
150
tTime required by a limit device to allow for the indicated function.
ADDRESS
t=""--------t
RC
--------------~~-t-A-C-C------.-I--------------
DATA OUT
TIMING MEASUREMENT REFERENCE
LEVEL IS 1·5V
Fig. 2 - Read-cycle timing waveforms.
92CM-36406
ns
588 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDM6118A-3
DATA RETENTION CHARACTERISTICS at TA = 0 to 70°C; See Fig. 4.
LIMITS
CHARACTERISTIC
Minimum Data Retention Voltage
Data Retention Quiescent Current
TEST CONDITIONS
VOR
looDR"
Chip Disable to Data Retention Time
Recovery to Normal Operation Time
teoR
tR
GEl or CE2 2:: Voo - 0.2 V
Voo - 3 V,
CE1 or CE2 2:: 2.8 VSee Fig. 4
See Fig. 4
*tRC = Read Cycle Time.
-If either pin (CEI or CE2) is low, it must be"; 0.2 V.
"IDDDR = 12.5 /1A max. at T. = 0 0 to +400 C.
DATA RETENTION
MODE
92CS-36404
Fig. 4 - Low VDD data retention timing waveforms.
CDM6118A-3
UNITS
MIN.
MAX.
2
-
V
-
25
/J A
0
-
ns
"'tRC
590 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDM6264
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Voo):
(Voltage referenced to Vss terminal) ............................................................................. .' .... -0.3 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ...................... , ......................................................... -0.3 to +7 V
POWER DISSIPATION PER PACKAGE (Po):
For TA = 0° to +60°C (PACKAGE TYPE E) ................................................................................ 500 mW
For TA = +60° to +70°C (PACKAGE TYPE E) ................................................. Derate Linearly at 8 mW/oC to 420 mW
For TA = 0° to +70°C (PACKAGE TYPE D) ...............................................................................• 500 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For TA = FULL PACKAGE-TEMPERATURE RANGE ....................................................................... 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE D .................................................................................................. 0 to +700 C
PACKAGE TYPE E .................................................................................................. 0 tel +70°C
STORAGE TEMPERATURE RANGE (T",) ............................................................................ -55 to +125°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max. .. ................................................... +265°C
OPERATING CONDITIONS at T. = 0 to +70'C
For maximum relleblllty, operating conditions should be selected so that operation Is always within the following ranges:
LIMITS
CHARACTERISTIC
UNITS
f---=, ALL TYPES
MIN.
DC Operating Voltage Range
Input Voltage Range
Inpul Signal Rise or Fall Time A
MAX.
4.5
5.5
V'H
2.2
Voo + 0.3
V'L
-0.3
0.8
t"I,
-
5
V
/-IS
Alnput signal rise and fall times with a duration greater than the maximum value can cause loss of stored data In the selected
mode.
STATIC ELECTRICAL CHARACTERISTICS at T. = 0 to +70'C, Voo = 5 V ± 10%, Except a. noted
Standby Device Current
loos
loos,
Outpul Voltage Low Level
Output Voltage High Level
Input Leakage Current
3-State Output Leakage Current
Operating Device Current
LIMITS
UNITS
ALL TYPES
Min. yp." Max.
mA
1.5
3
CONDITIONS
CHARACTERISTIC
VOL Max.
VOH Min.
-
Cl:1 =V'H or CE2=V'L
: 'CEl=CE2 ~ Voo-0.2 V or
CE2:5 0.2 V
IOL=2.1 mA
IOL=1/JA
IOH=-1 mA
IOH--1/JA
2.4
2
100
-
0.4
0.1
-
-
Voo-0.1
-
V'N=O V to Voo
-
±0.1
lOUT
V'/O=O V to Voo
-
±0.5 ±2
IOPER2#
Input Capacitance
C'N
Output Capacitance
CliO
"Typical values are for T.=25° C and nominal Voo.
V'N=V'L, V'H
V'N=0.2 V, Voo-0.2 V
V'N=O V,
1=1 MHz, T.=25·C
V,/o-O V,
1=1 MHz, T.=25·C
#Outputs open circuited.
±2
/JA
9
4.5
22.5
2
20
45
4
40
-
4
6
-
6
8
tcyc-1 /-IS
tcyc=120 ns
tcyc=1 /J.S
tcyc=120 ns
V
V
I'NMax.
10PER,#
/JA
mA
pF
592 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDM6264
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 0 to +70·C, Voo = 5 V ± 10'10,
Input t" tf = 10 ns; CL = 100 pF and 1 TTL Load, Input Pulse Levels: 0.8 V to 2.4 V
LIMITS
CHARACTERISTIC
Write Cycle Time., See Fig. 3
Write Cycle Time
Chip Enable to End of WRITE
Address Valid to End of WRITE
Address Setup Time
Write Enable Width
Write Recovery Time
Write to Output "High Z"
Input Data Setup Time
Input Data Hold Time
Output Active from End of Write
CDM6264-3
MIN.T
MAX.
twe
tewl,tew2
tAW
tAS
tww
tWR
tWHZ
tow
tOH
tow
150
120
120
0
100
0
60
0
10
CDM6264-4
MIN.T
MAX.
-
,
120
100
100
0
80
0
-
70
-
-
50
0
10
-
tTime required by a limit device to allow for the indicated function.
WRITE CYCLE 1 (CE1 CONTROL)
~--------IWC--------------~~
A CDRESS
~-----tCW1 ------~
CE 2
DATA
OUT
DATA
IN
rn
IN A
OR CE2 CONTROLLED WRITE CYCLE. THE OUTPUT BUFFERS
REMAIN IN A HIGH IMPEDANCE STATE, WHETHER mrlS HIGH OR LOW.
TIMING MEASUREMENT REFERENCE LEVEL IS 1.5 V.
Fig. 3 - Write-cycle timing waveforms.
92CM - :37204
UNITS
-
-
50
-
-
ns
594 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDM6264
DATA RETENTION' CHARACTERISTICS at TA = 0 to 70°C; See Fig. 4.
LIMITS
TEST CONDITIONS
CHARACTERISTIC
Minimum Data Retention Voltage
VOR
Data Retention Quiescent Current
looDR
Chip Disable to Data Retention Time
tCOR
Recovery to Normal Operation Time
tA
ALL TYPES
CE1 ;:: VOO - 0.2 V or
CE2::; 0.2 V
Voo = 3 V, CE1,CE2;::
V"" - 0.2 V or CE2 <0.2 V
See Fig. 4
See Fig. 4,
MIN.
MAX.
2
5.5
V
-
50
pA
0
-
ns
*tRO
'tRC = Read Cycle Time.
DATA RETENTION WAVEFORM 1 (CE1 CONTROL)
DATA
RETENTlON----.j
MODE
Voo
DATA RETENTION WAVEFORM 2 (CE2 CONTROL)
DATA
RETENTION----i
MODE
VOO
CE2
.. ~
~!""'
~~~~~~~~O-.4-V-----~-E-2-5-0-.-2-V------------~
O.4V
Fig. 4 - Low Voo data-retention timing waveforms.
UNITS
92CM -37208
596 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1822, CDP1822C
.RECOMMENDED OPERATING CONDITIONS al TA = Full Package-Temperalure Range
For maximum reliability, operating conditions should be selected so that operation is always
within the following ranges:
LIMITS
CHARACTERISTIC
Min.
4
Vss
DC Operating Voltage Range
Input Voltage Range
I
I
I
UNITS
CDP1822C
Max.
Min.
6.5
4
VDD
Vss
CDP1822
Max.
10.5
VDD
V
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Voo)
(VDltage referenced tD V•• Terminal)
CDPI822 .................................................................. : ...................................... -0.5to+ll V
CDP1822C ........................................................................................................-0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS .......................................................................... -0.5 to Voo +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ................................................................................... ±10 mA
POWER DISSIPATION PER PACKAGE (Po):
For T.=-40 to +60°C (PACKAGE TYPE E) ................................................................................ 500 mW
For T.=+60 to +85° C (PACKAGE TYPE E) .................................................. Derate Linearly at 12 mW/o C to 200 mW
ForT.=-55 to +100°C {PACKAGE TYPE D) ............................................................................... 500 mW
ForT.=+100 to +125°C (PACKAGE TYPE D) ............................................... Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T.=FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ................................................... 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE D ............................................................................................... -55 to +125°C
PACKAGE TYPE E ................................................................................................ -4010 +85° C
STORAGE TEMPERATURE RANGE {T".) ............................................................................ -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
AI distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ....................................................... +265°C
STATIC ELECTRICAL CHARACTERISTICS al TA = -40 10 +85°C, Excepl as Noled
TEST CONDITIONS
CHARACTERISTIC
Quiescent Device
Current,
Oulput Voltage:
Low-Level,
High-Level,
Vo
(V)
IDD
VOL
VOH
Input Low Voltage,
V'L
Input High Voltage,
V'H
Outpul Low (Sink)
Current,
Output High (Source)
Current,
IOH
Input Current,
I,N
3-State Output
Leakage Current
Operating Current,
Input Capacitance,
Output Capacitance,
10L
lOUT
IDD1 t
C'N
COUT
-
0.5,4.5
0.5,9.5
0.5,4.5
0.5,9.5
0.4
0.5
4.6
9.5
VIN
(V)
0,5
0, 10
0,5
0, 10
0,5
0, 10
-
-
0,5
0, 10
0,5
0, 10
0,5
0, 10
0,5
0, 10
0,5
0, 10
-
-
-
-
0,5
0, 10
tOulputs open circuited; cycle time = '118.
"Typical values are for TA = 25° C and nominal
VDD.
VDD
(V)
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
-
LIMITS
CDP1822
CDP1822C
Typ.·
Typ.·
Min.
Max.
Min.
Max.
500
500
1000
0.1
0.1
0
0
0.1
0
4.9
5
4.9
5
9.9
10
1.5
1.5
3
3.5
3.5
7
2
4
2
4
4.5
9
-1
-2
-1
-2
-4.4
-2.2
±5
±5
±10
±5
±5
±10
4
8
4
8
16
8
7.5
7.5
5
5
10
15
15
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UNITS
IIA
V
mA
IIA
-
-
mA
pF
598 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1822, CDP1822C
DYNAMIC ELECTRICAL CHARACTERISTICS at T A = -40 to +85 0 C, VDD ±5%,
Input tr,tl =20 ns, VIH =0.7 VDD, VIL =0.3 VDD, CL =100 pF
TEST CONDITIONS
CHARACTERISTIC
VD.D
. (V)
LIMITS
CDP1822
CDP1822C
Mln.r I Typ!
Max. I Mln.r Typ! I Max.
Write Cycle Times (Fig. 2)
Write Cycle
5
10
twe
Address Set-Up
tAS
Write Recovery
tWA
Write Width
5
10
5
10
5
10
5
10
tWAW
Input Data
Set-UpTime
tos
Data In Hold
5
tOH
Chip-Select 1 Set-Up
tel,s
Chlp-Salect 2 Set-Up
tes2S
Chip-Select 1 Hold
tCS'H
Chip-Select 2 Hold
tes2H
Output Disable Set-Up
10
5
10
5
10
5
10
5
10
5
10
tODS
500
300
200
110
50
40
250
150
250
150
50
40
200
110
200
110
0
0
0
0
200
110
-
-
-
.,-
-
500
-
200
-
50
-
250
250
-
50
200
-
200
-
0
0
0
0
200
-
tTlme required by a limit device to allow for Indlcaled function.
'TYPical values are for T. = 25° C and nominal Voo.
AO-A7
'CSIH
CHIP, SELECT 2
'CS2H -+----I~-OUTPUT DISABLE
-'os
011- 014
READ/WRTfE
~@ DON'T
*
CARE
92CM-'Soa04R4
'ODS IS REQUIRED FOR COMMON IIO
OPERATION ONLY; FOR SEPARATE IIO
OPERATIONS. OUTPUT DISABLE IS OON'T CARE·
Fig. 2 - Write cycle timing waveforms.
-
UNITS
-
-
-
-
-
ns
600 ______________ CMOS Microprocessors, Memories and Peripherals
CDP1822, CDP1822C
r;:----- --------- - - - - - - - - - - - - --,
lei
I
1321
I •
-EQv
I DO
ROW
AI
DECODERS
I
I
I
141
I
004
I
I
I
I
I
I
I
I
I
I
I
*
R/WO'''f-------1r-.i
~Vss
I
L ________________________ _
.+ t
INPUT PROTECTION
NETWORK
OUTPUT
PROTECTION
CIRCUIT
I
I
_____ .J
92CL- 300S3RI
Fig. 6 - Functional block diagram for CDP1822 and CDP1822C.
~~tco CS~~~~~~~~~~~~~~~~~~§E~~~
CSI
!N
p
I
CS2
CS3
~
------
~ ~r---------------.~--~~----.--~-------------
em
Fig. 7 - 4-kilobyte RAM system using the CDP1858 and CDP1822.
602 _______________ CMOS Microprocessors, Memories and Peripherals
CDP1823, CDP1823C
= FULL PACKAGE-TEMPERATURE RANGE
For maximum reliability, nominal operating conditions should be
selected so that operation is always within the following ranges:
OPERATING CONDITIONS at TA
LIMITS
CDP1823CD
CDP1823D
Min.
Max.
Min.
Max.
CHARACTERISTIC
Supply-Voltage Range
4
Recommended Input Voltage Range
10.5
VSS
6.5
V
VDD
V
4
VDD
VSS
UNITS
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY·VOLTAGE RANGE, (VDD)
(All voltage values referenced to VSS terminal)
CDP1823 ............................................................. -0.5to +11 V
CDP1823C ............................................................. -0.5to +7V
INPUT VOLTAGE RANGE, ALLINPUTS ................................... -0.5to VDD+ 0.5 V
DC INPUT CURRENT, ANY ONE INPUT ............................................. ± 10 mA
OPERATING·TEMPERATURE RANGE (T A):
CERAMIC PACKAGES (0 SUFFIX TYPES) ................................... -55to + 125°C
PLASTIC PACKAGES (E SUFFIX TYPES) ..................................... - 40 to + 85°C
STORAGE TEMPERATURE RANGE (Tstg) ..................................... -65to + 150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16± 1/32 inch (1.59±0.79mm) from case for 10s max .................... + 265°C
STATIC ELECTRICAL CHARACTERISTICS at T. = -40 to
CHARACTERISTICS
Quiescent Device
Current,
Output Voltage:
Low-Level,
High-Level,
100
VOL
VOH
Input Low Voltage, V,L
Input High Voltage, V,H
Output Low (Sink)
Current,
10L
Output High (Source)
Current,
10H
Input Current,
l,N
3-State Output
Leakage Current, lOUT
Operating Current,loo,t
Input Capacitance, C'N
Output Capacitance,
COUT
-
-
-
-
-
-
-
-
-
-
-
-
tOutputs open circuited; cycle time - 1 ps.
"Typical values are for T. 25° C and nominal VDD.
=
+ 85°C
Except as noted
TEST
CONDITIONS
LIMITS
CDP1823C
V,N Voo
CDP1823
Vo
(V)
(V) (V) Min. Typ.· Max. Min. Typ.· Max.
0,5
500
500
5
0,10 10
1000
0,5
0.1
0.1
5
0
0
0,10 10
0
0.1
0,5
5
4.9
5
4.9
5
0,10 10 9.9
10
0.5,4.5
1.5
1.5
5
0.5,9.5
10
3
0.5,4.5
5
3.5
3.5
0.5,9.5
10
7
0.4
0,5
2
5
4
2
4
0.5 0,10 10 4.5
9
-1
-1
-2
-2
4.6
0,5
5
9.5 0,10 10 -2.2 -4.4
0,5
5
±5
±5
Any
Input 0,10 10
±10
0,5
0,5
5
±5
±5
0,10 0,10 10
±10
0,5
5
4
8
4
8
0,10 10
16
8
7.5
7.5
5
5
-
-
-
10
-
-
15
-
-
-
-
-
-
-
-
-
-
-
-
-
10
-
-
UNITS
pA
V
rnA
pA
-
rnA
-
15
pF
604 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1823, CDP1823C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA
tr,tf = 20 ns, CL = 100 pF.
CHARACTERISTIC
VDD
(V)
= - 40 to + 85 ·C, VDD ::t: 5%,
LIMITS
CDP1823
CDP182aC
UNITS
Min. t Typ. * Max. Min. t Typ. * Max.
Write Cycle (See Fig. 2)
Write Recovery, tWR
Write Cycle, twc
Write Pulse
Width, tWRW
Address
Setup Time, tAS
Data
Setup Time, tDS
Data Hold Time
From MWR, tOH
5
10
5
10
5
10
5
10
5
10
5
10
75
50
400
225
200
100
125
75
100
75
75
50
-
-
-
-
75
-
400
200
-
125
100
75
-
-
-
-
-
-
-
-
ns
-
'Typical values are at TA = 2S'C and nominal voltage.
trlme required by a limit device to allow for the indicated function.
f.
r-
--"- -
'wc---
--------00
tAS
.---,r-------+---------------------~/------
ADDRESS
~~-------r----------------r_------'I~-------
r---------+-----------------,I~-·W~
CSt ,CS4
tn,m.rn
-
t
BUS 0-7
-'WRW
~-~~L-::SDA-:------'~=YYYl"--NOTE' MRD MUST'BE HIGH DURING WRITE OPERATION
Fig. 2 - Write cycle timing diagram.
92CM-31943RI
!
606 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1823, CDP1823C
I
CPUI ROM SYSTEM
I
I
RAM INTERFACE
I I
RAM SYSTEM
I
·~--r------------r--~MRO
f---~-----------;----~MWR
CEO ~--L------------r--~ CS
£.U
COPI802
.B!M.
ROM
CDPI833
CDPI823
92CM-33515
Fig. 5 - CDP1823 (128 x 8) minimum system (128 x 8)
608 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1824, CDP1824C
MAXIMUM RATINGS,Absolute·Maximum Values:
DC SUPPLY·VOL TAGE RANGE. (VDD)
(All voltage value. referenced to VSS terminall
CDP1824. . . . . . . . .
CDP1824C . . . . . . . . . .
INPUT VOLTAGE RANGE. ALL INPUTS. .
DC INPtJT CURRENT. ANY ONE INPUT . .
OPERATING·TEMPERATURE RANGE (TA):
CERAMIC PACKAGES (0 SUFFIX TYPES) .
PLASTIC PACKAGES (E SUFFIX TYPES)
STORAGE TEMPERATURE RANGE (T.tg) .
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from ca.e for 10. max.
. . -0.6 to +11 V
-0.6 to +7 V
-0.6 to VDD +0.5 V
±10mA
-56 to +126 oC
-40 to +86°C
-65 to +160 oC
OPERATING CONDITIONS at T A = Full Package· Temperature Range
For maximum reliability, operating conditions should be selected so that operation is
always within the following ranges:
CONDITIONS
CHARACTERISTIC
LIMITS
CDP1824D
CDP1824E
CDP1824CD
CDP1824CE
UNITS
VDD
(V)
Min.
Max.
Min.
Max.
Supply·Voltage Range
-
4
10.5
4
6.5
V
Recommended I nput Voltage
Range
-
VSS
VDD
VSS
VDD
V
Input Signal Riseor Fall Time....
-
5
tr,tf
10
5
-
2
-
5
• Input signal rise or fall times longer than these maxima can cause loss of stored data
.elected or de.elected mode.
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to
CHARACTERISTICS
Quiescent Device
-
Current.
Output Voltage:
Low-Level.
High-Level,
100
VOL
VOH
-
-
-
0,5
-
0.10
1.9
Input High Voltage, V,H 0.5.4.5
Current.
10L
Output High (Source)
Current,
Input Current,
10H
liN
3-State Output
Leakage Current, lOUT
Operating Current,loo,t
Input Capacitance, C 'N
In
Bither the
Except as noted
TEST
CONDITIONS
LIMITS
V,N Voo
CDP1824
CDP1824C
Va
(V)
(V) (V) Min. Typ.* Max. Min. Typ.* Max.
5
100
200
25
50
10
500
250
0.1
5
0
0
0.1
0.5
0,10 10
0.1
0
-
Input Low Voltage, V,L 0.5,4.5
Output Low (Sink)
+ 85°C
/is
-
-
1,9
0.4
0,5
0.5
0,10
4.6
9.5
0,5
0,10
0,5
Any
input 0,10
0,5
0.5
0,10
-
-
-
5
10
4.9
9.9
5
10
-
5
10
-
5
10
3.5
7
-
5
10
1.8
2.2
3.6
-0.9
4.5
-1.1
-1.8
-2.2
±0.1
5
10
5
10
5
10
-
-
-
-
-
-
-
-
0.10
0,5
0,10
-
5
10
-
-
-
4.9
5
-
-
1.5
-
-
3
-
-
-
COUT
-
/i A
V
1.5
-
3.5
-
-
-
1.8
i2
-0.9
-
±1
±0.1
±0.2
±1
±2
-
±0.2
4
±2
-
8
5
16
7.5
10
15
-
-
-
-
mA
-1.1
-
-
±0.1
±1
-
-
±0.2
8
-
-
±2
pA
-
4
8
-
-
5
7.5
10
15
Output Capacitance,
tOutputs open circuited: cycle time - 1 I1s.
·Typical values are for TA = 25' C and nominal Voo.
UNITS
mA
pF
610 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1824, CDP1824C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = -40 to +8SoC, VDD ±S%,
Input t r, tf = 10 ns, CL =SO pF, RL = 200 kn; See Fig. 2.
LIMITS
TEST
CDP1824CD
CDP1824D
CONDITIONS
CDP1824CE
CDP1824E
VDD
(VI
Min.# Typ.- Max. Min.# Typ.- Max.
CHARACTERISTIC
U
N
I
T
S
Write Operation
Write Pulse
Width, tWRW
5
10
390
180
200
150
-
390
200
-
-
Data Setup
Time, tDS
5
10
390
180
100
50
-
390
100
-
-
-
Data Hold
Time, tDH
5
10
70
35
40
20
-
70
40
-
-
Chip Select
Setup Time, tcs
5
10
425
215
210
110
-
425
210
-
-
-
Address Setu p
Time, tAS
5
10
640
390
500
300
-
640
500
-
-
-
# Time required by a limit device to allow for the indicated function .
• Time re~ujred by a typical device to allow for the indicated function. Typical values are for
T A = 25 C and nominal VDD.
LICS--i
======:::::kIDS--f--jC
m~
BUS
WRITE OPERATION TIMING DIAGRAM
92CS-34740
Fig. 2 • Write cycle timing diagram.
-
ns
-
ns
-
ns
-
ns
-
ns
612 _ _ _ _ _ _ _ _ _ _...._-_- CMOS Microprocessors, Memories and Peripherals
CDP1824, CDP1824C
I
CPUI ROM S'/STEM
I RAM
SYSTEM
1
TPA
iiRD
BUSO- BUS7
£.U
CDPIS02
ROM
CDPIS33
.!!AM.
CDIS24
92CS-34741
Fig. 5 - CDP1824 (128 x 8) minimum system (128 x 8)
614 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1826C
Two memory control signals, MRD and MWR, are provided
for reading from and writing to the CDP1826C. The logic is
designed so that MWR overrid~MRD, allowing the chip to
be controlled from a single R/W line.
For such an interface, the MRD line can be tied to Vss , with
the MWR line connected to R/iN.
A CHIP ENABLE OUTPUT is provided for daisy-chaining to
additional memories or 1/0 devices. This output is high
whenever the chip-select function selects the CDP1826C,
which deselects any other chip which has its CS input
connected to the CDP1826C CEO output. The connected
chip is selected when the CDP1826C is de-selected and the
MRD input is low. Thus, the CEO is only active for a read
cycle and can be set up so that a CEO of another device can
feed the MRD of the CDP1826C, which in turn selects a third
chip in the daisy chain.
The CDP1826C has a recommended operating voltage of
4.5 to 5.5 Vand is supplied in 22-lead hermetic dual-in-line
side-brazed ceramic packages (D suffix), in 22-lead dualin-line plastic packages (E suffix). The CDP1826C is also
available in chip form (H suffix).
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Voo)
(Voltages referenced to Vss Terminal) .........................................................•...................• -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ..................................................................•..•...-0.5 to Voo +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ..................................................................................±10 mA
POWER DISSIPATION PER PACKAGE (Po):
For T. = -40 to + 60° C (pACKAGE TYPE E) ........................................................................•..• 500 mW
For T. = +60 to +85°C (PACKAGE TYPE E) .............................................. Derate Linearly at 12 mW/oC to 200 mW
For T. = -55 to + 100°C (PACKAGE TYPE D) ........................................................................... 500 mW
For T. = + 100 to + 125°C (PACKAGE TYPE D) .......................................... Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For T. = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) .................................................. 100 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE 0 .............................................................................................. -55 to + 125° C
PACKAGE TYPE E ............................................................................................... -40 to +85°C
STORAGE TEMPERATURE RANGE (T ..,) .......................................................................... -65 to + 150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max ..................................................... +265°C
RECOMMENDED OPERATING CONDITIONS at TA = Full Package Temperature Range.
For maximum reliability, operating conditions should be selected so that operation is always within the following ranges:
LIMITS
CDP1826C
CHARACTERISTIC
DC Operating Voltage Range
Input Voltage Range
Input Signal Rise or Fall Time
Voo = 5 V
MIN.
4.5
t" tf
UNITS
MAX.
Vss
6.5
Voo
V
-
10
/1S
616 ______________ CMOS Microprocessors, Memories and Peripherals
CDP1826C
BUS 0
AO---~
BUS I
AI
A2 ---~
A3 - - - - + I
A4
INPUT
ADDRESS
BUFFERS
INPUT/OUTPUT
DATA
BUFFERS
AND
64,8
MATRIX
CONTRO~
----+I
CS/A5 -
BUS 2
BUS 3
BUS4
BUS 5
.....--+1
BUS 6
BUS 7
TPA
CSI------------------~
~--------------~
MWR------------------------------------------------~ L~~--~
mrn---------------------------------------------~_7
CEO
92CM-14044
Fig. 2 - Functional diagram.
I
A5
TPA
MRD
CEO
~
I
~
I
I
::I:J---i
VALID
I
VA~ID
DATA
DATA
SE~ECTEDI
(RAM
ROM CYCLE
( RAM DE SELECTE D)
'C'S2. 0
92CM-34048
OPERATING MODES
Mire
MWII
CSI·e§2
WRITE
X
I
.n
OJ
READ
0
0
I
I
.I'-
0
DESE~ECT
I
I
I
.Sl.
0
DESE~ECT
I
X
0
X
CD
DESE~ECT
O·
X
0
0
"
DESE~ECT
I
X
X
J"l.
0
I
DESELECT
0
X
x
J"'l..
0
0
~
WRITE
X
0
I
I
X
I
a:~
READ
I
I
I
I
I
I
X
DESE~CT
0
I
I
I
z
0
z
DESE~ECT
I
X
0
I
X
I
DESE~CT
0
X
0
I
X
0
FUNCTION
0
2
0
0:
y~
t-I
I
RAM CYCLE
CSI'I,
I
I
I
BUS
g
I
I
CS/Ae#
TPA
X
I
I
CEO
I
I
I
I
X
X
I
X
0
.,. FOR CDPIBOO MODE, REFERS TO HIGH ORDER MEMORY
~~~~iS~L:6~ ~EVEL AT TIME WHEN TPA
TRANSITION
'i
Fig. 3 - Chip Enable Output timing waveforms for CDP1800-based systems.
618 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1826C
AO-A5
HIGH ORDER
ADDRESS BYTE
LOW ORDER ADDRESS BYTE
BUS ____________~--~H~IG~H~I~M~PE~D~A~NC~E~----_{
VALID
DATA
92CM-37722
Fig. 5 - Timing waveforms for Read-cycle 2 [TPA-Highl.
DYNAMIC ELECTRICAL CHARACTERISTICS at TA
= -40 to +85°C,
Voo
=5
V ±5%,
Input t, I, = 10 ns· C L = 50 pF and 1 TTL Load
LIMITS
CDP1826C
CHARACTERISTIC
MIN.t
Write-Cycle Times (Figs. 6 and 7)
Addre~s to TPA Setup,
High Byte
Address to TPA Hold
TYP."
UNITS
I
MAX.
100
-
-
100
-
-
500
250
-
tASH
tAH
Address Setup
Low Byte
I
tAS L
200
TPA Pulse Width
-
-
tpAW
Chip Select Setup
700
350
-
300
200
-
100
-
-
400
200
-
100
50
-
125
50
-
tcs
Write Pulse Width
tww
Write Recovery
tWR
Data Setup
tos
Data Hold from
End of MWR
tOH1
Data Hold from
End of Chip Select
tOH2
tTime required by a limit device to allow for the indicated function.
oTypical values are for T A = 25' C and nominal VDD .
ns
620 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1826C
DATA RETENTION CHARACTERISTICS at TA = -40 to +85°C' see Fig 8
TEST
CONOICHARACTERISTIC
TIONS
VOR
Voo
(V)
(V)
MIN.
Min. Data Retention
VOR
Voltage
Data Retention Quiescent
2.5
Current
100
Chip Deselect to Data
600
5
Retention Time
tcoR
Recovery to Normal
5
600
Operation Time
tRC
Voo to VOR Rise and
1
2.5
5
Fall Time
tr,tf
.Typical values are for TA = 25'C and nominal Vee.
VOO
'CDR
csz
r'f
VOR
ViH\1
VIL~'-._ _ _ _ _ _ _ _ _ _ _~
92CS~30B05RI
Fig. 8 - Low Vee data retention timing waveforms.
LIMITS
COP1826C
UNITS
TYP."
MAX.
2
2.5
V
5
25
JlA
-
-
-
-
ns
-
-
JlS
622 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP68HC68R1, CDP68HC68R2
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Voo):
(All vbltage values referenced to Vss terminal) ...................................................................... -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ....................................................................... -0.5 to Voo +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ................................................................................ ±10 mA
POWER DISSIPATION PER PACKAGE (Po):
For T.=-40 to +60'C (PACKAGE TYPE E) ............................................................................. 500 mW
For T.=+60 to +85' C (PACKAGE TYPE E) ............................................... Derate Linearly at 12 mW/'C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For T.=FULL PACKAGE-TEMPERATURE RANGE ..................................................................... 100 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE E ............................................................................................ -40' to +85'C
STORAGE TEMPERATURE RANGE (Tot,) ......................................................................... -65 to +150'C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59' 0.79 mm) from case for 10 s max. . ................................................... +265'C
OPERATING CONDITIONS at TA = -40' to +85°C
For maximum reliability, operating conditions should be selected so that operation Is always within the following ranges:
LIMITS
ALL TYPES
CHARACTERISTIC
DC Operating Voltage Range
Input Voltage Range
MIN.
3
0.7 Voo
-0.3
V,H
V'L
Serial Clock Frequency
UNITS
MAX.
5.5
Voo +0.3
0.2 Voo
V
ISCK
-
VDo=3 V
Voo=4.5 V
1.05
2.1
MHz
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, VDD = 3.3 V ±10%, Except as Noted
CHARACTERISTIC
Standby Device Cu rrent
loos
Output Voltage High Level
VOH
Output Voltage Low Level
VOL
Input Leakage Current, liN
3-State Output
Leakage Current, lOUT
Operating Device Current
10PER#
Input CapaCitance, C 'N
CONDITIONS
LIMITS
CDP68HC68R1
CDP68HC68R2
MIN.
TYP."
MAX.
MIN.
TYP."
MAX.
UNITS
-
-
1
15
-
1
50
IOH=-0.4 rnA, Voo=3 V
2.7
-
-
2.7
-
-
10L =0.4 rnA, Voo=3 V
-
-
0.3
-
-
0.3
-
-
-
±1
-
-
±1
-
-
-
±10
-
-
±10
V'N=V'L,V'H
-
5
10
-
5
10
rnA
V,N=O V, 1=1 MHz, TA=25°C
-
4
6
-
4
6
pF
/lA
V
"Typical values are for T .=25' C and nominal Voo.
#Outputs open circuited; cycle time=Min. tcycl e, duty=100%.
/lA
624 _ _ _ _ _ _ _ _ _ _ __,_-- CMOS Microprocessors, Memories and Peripherals
CDP68HC68R1, CDP68HC68R2
a. Page/Device Byte (CDP68HC68R2 Only)
BIT
7
IX
6
5
4
3
2
1
0
X
X
X
X
X
X
A7
3
2
A1
AO
PAGE SELECTION (CDP68HC68R2 Only)
Forthe CDP68HC68R2, a Page/Device byte issentfrom the
microcomputer before the Address/Control byte. Because
the Address/Control byte is limited to 128 addresses, the
CDP68HC68R2 is divided into two 128-byte pages. A page
select is accomplished by enabling the CDP68HC68R2,
transmitting the Page/Device Select byte (see Fig. 2a), and
finally disabling the device priorto any more data transfers.
The Page/Device byte is recognizable because it is the only
time that a single byte is transferred to the RAM before CE·
SS is disabled (see Fig. 3). The page select is latched and
remains until changed or is incremented during a burst
transfer (see next section).
b. Address/Control Byte
BIT
7
6
IW/R I A61
5
4
0
A51 A41 A31 A2
AO-A6 The seven least significant RAM address bits,
sufficient to address 128 bytes.
w/Fi. Read or Write data transfer control bit.
W/R = 0 initiates one or more memory read
cycles. wiR = 1 initiates one or more memory
write cycles.
c. Data Byte
BIT
7
6
5
4
3
2
1
ADDRESS AND DATA
Data transfers can occur one byte at a time (Fig. 4) or in a
multi-byte burst mode (Fig. 5). After the chip is enabled, an
address word is sent to select one of the 128 bytes (on the
selected page) and specify the type of operation (i.e., Read
orWrite). Forasingle byte Read orWrite (Fig. 4), one byte is
transferred to or from the location specified in the
Address/Control byte; the device is then disabled. Additional
reading or writing requires re-enabling the RAM and
providing a new Address/Control byte. If the RAM is not
disabled, additional bytes can be read or written in a burst
mode (Fig. 5). Each Read or Write cycle causes the latched
0
I 07 I 06 105 I 04 I 03 I 02 I 01 I DO I
Fig. 2 - Serial byte format.
L
CE'SS~
MOSl~
* SCK
X
x
x
x
x
x
CAN BE EITHER POLARITY.
A7~
x
92CM-37713
Fig. 3 - Page/Device Select byte transfer waveforms.
CE'SS~
II IIII II III I I I II
SCK
WRITE {
MOSl
L
~" " ' <' ' <'-
~CSi
CO2
0
I
C52
L---
e--
=
MWR
L~MRli
I
r
_
MAO-7 M
s
""" •
I
0
I
C52
~
BUS 4-7
i
W
,
s
I
-CSI
~
CSi
~-7M
.i
~
I
J----
I
C52
I~
~M~-'
'
w
'
I
I
4
M
r-
W
•0
BUS 0-3
I
0I
L---
•
~
~
MAO-'
BUSO-3
MWR
M
I
f-----ESi
s
4
~
MWR
-
M
W
C52
0[0-
~iCso
c C51
MWR
CO2
MAO-?
~
~
0I
4
MAO-?
MWR~
~Mlffi
--ESi
,
s
0II
C52
C52
L---
L_
0P C52
.J:"EN
-
.
I
C53
mir----
~ m
ml----
I
m
92CL-3·4701
'---
Fig, 7 - 4K byte Ram system using the CDP1858 and MWS5101,
636 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
MWS5101A
OPERATING CONDITIONS at TA = Full Package·Temperature Range
For maximum reliability, operating conditions should be selected so that
operation is always within the following ranges'
LIMITS
ALL TYPES
Max.
Min.
6.5
4
VSS
VDD
CHARACTERISTIC
DC Operating· Voltage Range
Input Voltage Range
UNITS
"
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE (Voo)
(All voltage referenced to Vss terminal) ........................................... -0.5 to -7 V
INPUT VOLTAGE RANGE, ALL INPUTS ........................................ -0.5 to Voo + 0.5 V
DC INPUT CURRENT, ANY ONE INPUT ................................................
±
10 mA
POWER DISSIPATION PER PACKAGE (Po):
For TA = -40 to +60°C (PACKAGE TYPE E) .......................................... 500 mW
For T A = +60 to +85° C (PACKAGE TYPE E) ........... Derate Linearly at 12 mW/o C to 200 mW
For TA = -55 to +100°C (PACKAGE TYPE D) ......................................... 500 mW
For TA = +100 to +125°C (PACKAGE TYPE D) ........ Derate Linearly at 12 mW;oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) .............. 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE D ............................................................-55 to +125°C
PACKAGE TYPE E ............................................................. -40 to +85°C
STORAGE TEMPERATURE RANGE (Tot.) .......................................... -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max .................... +265°C
STATIC ELECTRICAL CHARACTERISTICS at TA=O to 70°C, VDD=5 V
LIMITS
TEST
UNITS
MWS5101AD
CONDITIONS
CHARACTERISTIC
MWS5101AE
Vo
VIN
Min. Typ.
Max.
(V)
(V)
25
50
L2TvDes
0, 5
Quiescent Oevice
",A
200
L3 Types
0, 5
Current,IDO
100
Output Voltage:
0.1
0
0, 5
Low·Level,
VOL
V
4.9
5
0, 5
High·Level,
VOH
0.65
Input Low Voltage,
VIL
2.2
Input High Voltage,
VIH
Output Low (Sink)
Current,
IOL
Output High (Source)
Current,
IOH
Input Current,
liN
3·State Output Leakage
L2TvDes
Current,
L3Types
lOUT
Operating Current,
1001#
Input Capacitance,
CIN
Output Capacitance,
COUT
0.4
0, 5
2
4
-
4.6
0, 5
-1
-2
-
-
0, 5
-
-
+5
0, 5
0, 5
0, 5
-
-
+5
±5
rnA
0, 5
0, 5
-
"Typical values are for T A = 25·C and nominal VDD.
#Outputs open·circuited; cycle time = 1 I's.
-
-
-
-
4
5
10
8
7.5
15
",A
rnA
pF
638 _______________ CMOS Microprocessors, Memories and Peripherals
MWS5101A
=
=
DYNAMIC ELECTRICAL CHARACTERISTICS at TA 0 to 70 ·C, VDD 5 V ± 5%,
tr,t, = 20 ns, CL = 50 pF and 1 TTL Load
LIMITS
MWS5101AD, MWS5101AE
UNITS
CHARACTERISTIC
L2 Types
L3 Types
Min.t TVD.· I Max. I Min t Tvp.- I Max.
Write Cycle Times (Fig. 2)
Write Cycle
400
twc 300
Address Setup
150
tAS 110
Write Recovery
40
50
tWR
Write Width
200
tWRW 150
Input Data
150
200
ns
Setup Time
tDS
Data In Hold
40
50
tDH
~p-:select 1 Setup tCS1S 110
150
150
Chip-Select 2 Setup tCS2S 110
r:lilp-Selecf 1 Hold tCS1H
0
0
Chip-Select 2 Hold tCS2H
0
0
Output Disable
150
110
Setup
tODS
-
-
-
-
hlme required by a limit device to allow for the indicated function.
"Typical values are for TA=25"C and nominal VDD.
joe-------
'wc
------~
AO-A7
fCSIH
CHip-SELECT I
CHIP-SELECT 2
'CS2H
--joo----I'----
OUTPUT DISABLE
~
011- 014
lOS
DATA IN STABLE
--+----~~~~'WRW-~Jr-~-
READ/WRITE
~&DON'T
*
CARE
92CM-!0804R4
'ODS IS REQUIRED FOR COMMON"I/O
OPERATION ONLY, FOR SEPARATE I/O
OPERATIONS, OUTPUT DISABLE IS DON'T CARE.
Fig. 2 - Write cycle timing waveforms.
640 ______________ CMOS Microprocessors, Memories and Peripherals
MWS5101A
r;:----- --------- - - - - - - - - - - - - --,
151
I
1321
I ..
,22 V
--=0
ROW
AI
I
DECODERS
DO
I
I
I
18,321
18,321
18,321
STDRAG[
STORAGE
STORAGE
141
I
I
I
I
1
I
I
I
I
I
I
I
~Vss
* 19 I
I
CSi
CS2
I
I
11
00* 18
L ________________________ _
.+. f.
INPUT PROTECTION
92CL- 30063RI
OUTPUT
NETWORK
------.1
PROTECTION
CIRCUIT
Fig. 5 - Functional block diagram for MWS5101A.
r- - - -- - - -
CONTROL
'-l
I
1
p-~------~
CS2
}t..IP-SELECT
CONTROL
I
1---
-
---
-
-
-
__ I
cONTROL
I
RIW
2D
I
BI
P------_---+:.
-
-
~
-
-
- CONTRoL-
-
-
--
CI
OUTPUT
18
DISABLE IL _ _ _ _ _ _ _ _ _ _
}gHLe-SELECT6
R/W CONTROL
I}gUTPUT
DISABLE
1 CONTROL
-...J
92CM-30064R2
Fig. 6 - Logic diagram of controls for MWS5101A.
642 _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
MWS5114
A6
IS
VOO
AS
17
A7
A4
16
AS
I~
Ag
A3
14
1/01
AI
13
1/02
A2
12
1103
AO
~
CS
VSS
CMOS
1024-Word by 4-Bit
LSI Static RAM
Features:
• Fully static operation
• Industry standard 1024 x 4 pinout (same as pinouts for 6514. 2114.
9114. and 4045 types)
• Common data input and output
• Memory retention for stand-by battery voltage as low as 2 V min.
• All inputs and outputs directly TTL compatible
• 3-state outputs
• Low standby and operating power
1/04
10
WE
92CS- 30982RI
TERMINAL
ASSIGNMENT
The RCA-MWS5114 is a 1024-word by 4-bit static .randomaccess memory that uses the RCA ion-implanted silicon
gate complementary MOS (CMOS) technology. It is designed for use in memory systems where low power and
simplicity in use are desirable. This type has common data
A4---~d-1
AS - - - - I I : : J
A6 - - - - I : l : : : J
A7----Ci::::::i
AS----Ci::::::i
MEMORY ARRAY
64 ROWS
64 COLUMNS
OPERATIONAL MODES
Ag ---~c:::[_--.J
1/01
input and data output and utilizes a single power supply of
4.5 V to 6.5 V.
The MWS5114 is supplied in 18-lead. hermetic. dual-in-line
side-brazed ceramic packages (D suffix) and in 18-lead
dual-in-line plastic packages (E suffix).
------t-;:1==~f=~~~~::::::::::::::::::::::::::;l
I/O~ ---ri+-I>--1
CS
WE
DATA PINS
Read
0
1
Output:
Dependent
on data
Write
0
0
Input
X
HighImpedance
FUNCTION
1/0 3 ---1++-+-1>--1
1/04
-.....-l++-+-I>--I
Not
Selected
1
ENABLE
92CS-30960AI
Fig. 1 - FLinctional block diagram for MWS5114
File Number. 1325
644 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
MWS5114
DYNAMIC ELECTRICAL CHARACTERISTICS at TA
Input t,. tf ~ IOns; CL ~ 50 pF and 1 TTL Load
~
0 to +70 0 C, Voo ~ 5 V ± 5%,
LIMITS
I
MWS 5114-3
CHARACTERISTIC
I
MWS 5114-2
MWS 5114-1
UNITS
I
MIN·t ITYP.' I MAX·I MIN.tl TYP.'1 MAX·I MIN.tl TYP.' MAX.
Read Cycle Times See Fig. 2
160
-
-
-
Read Cycle
tRC
Access
tAA
-
160
200
-
200
250
-
250
300
Chip Selection to Output Valid
teo
-
110
150
-
150
200
-
200
250
Chip Selection to Output Active
tcx
20
100
20
100
20
100
Output 3-siate from Deselection
toTO
-
75
-
75
-
75
125
Output Hold from Address Change
tOHA
50
100
50
100
50
100
-
200
250
200
300
250
ns
t
-
125
-
-
125
-
Time required by a limit device to allow for the indicated function.
-Typical values are for TA ::: 25° C and nominal Voo.
/
f + - - - - - 'ex
Dour
92CS-31115R2
NOTE
WE
IS HIGH DURING TH~ READ CYCLE
TIMING MEASUREMENT REF LEVEL IS 1.5V
Fig. 2 - Read cycle waveforms.
-
646 - - - - - - - - - - -___ CMOS Microprocessors, Memories and Peripherals
MWS5114
DATA RETENTION CHARACTERISTICS at TA = 0 to 70° C; See Fig. 4.
CHARACTERISTIC
Minimum Data
Retention Voltage
TEST
LIMITS
CONDITIONS
ALL TYPES
MIN.
-
-
2
-
-
-
-
25
50
-
-
25
50
-
-
60
125
MWS 5114-3
2
MWS5114-2
MWS5114-1
Chip Deselect to Data
Retention Time,
UNITS
MAX.
Voo (V)
VOR
Data Retention Quiescent
Current, IDD
TYP.·
VOR (V)
-
IeDR
5
300
-
-
-
-
V
fJ.A
ns
Recovery to Normal
Operation Time,
tRC
VDD to VDR Rise and
Fall Time
t e , tl
-
5
300
-
2
5
1
-
• Typical values are for TA = 25° C and nominal VDD .
VDD
r
"':"":"'---,i
OATA
RETErt'TION
MODE
095 VDD
095 VDD
V DR
92CS-31114R2
FIg. 4 -
Low VOD data retention timing waveforms.
IlS
648 _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
650 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
ROM Competitive Specifications
4K x 8 ROM (24 Pin JEDEC Pkg.)'"
PARAMETERS
UNITS
Voo
TA
VOL(rnax) @ IOL
VOH(rnin) @ IOH
VIL(rnax)
VIH(rnin)
11.1
ILO
I(Active)
I (Stand by) 1'b'
I(Standby)2'c!
tM
RCA
CDM5333
(CMOS)
V
V
V
V
pA
pA
rnA
rnA
pA
ns
5 ± 10%
to +85
0.4 @ 1.8rnA
Voo -{).4 @ ~400pA
0.8
2.4
1
1
25 @ 1MHz
0.5 @ 1MHz
50
350
UNITS
RCA
CDM5364
(CMOS)
V
'c
~40
AMI
S68A332
(NMOS)
GI
R03-9332B
(NMOS)
5 ± 5%
5 ± 10%
+70
0.4 @ 3.2rnA
2.4 @ -200pA
0.8
2
10
10
125
-
o to +70
0.4 @ 3.2rnA
2.4 @ ~220pA
0.8
2
10
10
70
-
o to
-
350
450
AMI
S68A364
(NMOS)
GI
R03-9364B
(NMOS)
8K x 8 ROM (24 Pin Pkg.)'"
PARAMETERS
Voo
TA
VOL(max) @ IOL
VOH(min) @ IOH
VIL(max)
VIH(min)
III
ILO
I(Active)
I(Standby)1'b'
I(Standby)2'c!
IAA
V
'c
V
Ii
V
V
pA
pA
mA
mA
pA
ns
± 10%
5 ± 10%
-40 to +85
0.4 @ 3.2mA
2.4 @ -3.2mA
0.8
2.2
1
1
10 @ 1ps/30 @ 250ns
1.5
50
250
0.4 @ 3.2mA
2.4 @ ~220pA
0.8
2
10
10
70
10
350
RCA
CDM53128
(CMOS)
AMI
S23128
(NMOS)
5
o to +70
5
± 10%
o to
+70
0.4 @ 3.2mA
2.4 @ -200pA
0.8
2
10
10
50
10
-
300
16K x 8 ROM (28 Pin JEDEC Pkg.)'"
PARAMETERS
UNITS
VDO
TA
VOL(max) @ IOL
VOH(min) @ IOH
VIL(max)
VIH(min)
III
ILO
I(Active)
I(Standby)1'"
I(Standby)2'c!
IAA
V
'c
V
V
V
V
pA
pA
mA
mA
pA
ns
5 ± 10%
-40 to +85
0.4 @ 3.2mA
2.4 @ -3.2mA
0.8
2.2
1
1
10 @ 1ps/30 @ 250ns
3
50
250
o to +70
o to +70
0.4 @ 3.2mA
2.4 @ -220pA
0.8
2
10
10
50
10
250
0.4@2.1mA
2.4 @ -400pA
0.8
2.1
10
10
120
300
RCA
CDM53256
(CMOS)
MicroPower
MP2325
(CMOS)
Hitachi
HN61256
(CMOS)
5 ± 10%
'-40 to +85
0.4 @ 3.2mA
2.4 @ -3.2mA
0.8
2.2
1
1
12 @ 1ps/36 @ 250ns
1.5
50
250
5 ± 10%
-10 to +70
0.4 @ 2mA
5 ± 10%
-20 to +75
0.4 @ 1.6mA
2.4 @ -100pA
0.8
2.4
2
5
3@4ps
5
± 10%
CSG
23128B
(NMOS)
-
5
± 5%
32K x 8 ROM (28 Pin JEDEC Pkg.)'"
PARAMETERS
UNITS
Voo
TA
VOL(max) @ IOL
VOH(min) @ IOH
VIL(max)
VIH(min)
III
ILO
I(Active)
I(Standby)1 'b'
I(Standby)2'"
tM
V
'C
V
V
V
V
pA
pA
mA
mA
pA
ns
0.8
2.2
1
1
8.25 @ 450 ns
40
450
50
3500
652 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
BYTE-WIDE CMOS AND NMOS ROM's
4K
8
!12K
16K" R
8K"
24-Plnt
24-Plne
24-Pln
2S-Plnt
2S-Plnt
2S-Plnt
RCA
CDMS332*
CD MS333*
CDMS364*
CDMS36S*
CDM5312S*
CDM53256*
AMI
S2333
S68A332
S68A364
S68B364
S2364
S23128
AMD
CSG
AM9233
2333
EA8332B
AM9232
2332
EA8332A
F3533
F3532
R03-9333
R03-9332
2332
8
2S-Pine
Manufacturer
EA
Fairchild
Fujitsu
GI
GTE
Hitachi
Intel
Intersil
Maruman
HN46332
IM7332
MIC2332
MB8364
R03-9364
HN48364
HN6136S'
HN61366'
HN61364'
HN613128'
HN61256'
HN6132S6'
pPD2332B
IM7364
MIC2364
MMS2132
MP2364C'
MCM68B364
MK36000
MMS2164
pPD2332A
pPD2364
MCM68A332
MP236S'
MP232S'
MK37000
pPD23128
MSM38128
MN2332
Seiko
Signetics
SSS
2632A
SCMSS32'
SCM23C32'
CM3200'
Supertex
Synertek
TI
Toshiba
23128
2332A
Micropower
Motorola
Mostek
National
NEC
OKI
Panasonic
Rockwell
2364
EA8364
SY2333
TC5332'
TMM2332
SY2332
TMS4732
TMM333
VLSI
'CMOS parts, all others are NMOS
tJEDEC Version B
e JEDEC Version A
R2364A
R2364B
SMM2364'
2664
SMM236S'
CM6400A'
23S665
CM6400'
23S664
SY2364A
TMS4764
TMM2366
TCS36S'
SY236SA
SMM2326'
23128
TMM2364
TCS364'
VT236S
SY23128
TMM232S6
VT23128
SMM232S'
654 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDM5332, CDM5333
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Voo)
(Voltage referenced to V•• terminal) .................................................................................... -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ......................................................................... -0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT .................................................................................... ±10 mA
POWER DISSIPATION PER PACKAGE (Po):
For T. =-40 to +60° C (PACKAGE TYPE E) ................................................. , ............................. 500 mW
ForT. = +60 to +85°C (PACKAGE TYPE E) ................................................. Derate Linearly at 12 mW/oC to 200 mW
ForT. =-55 to +1OO°C (PACKAGE TYPE D) ........................... , .................................................. 5oo·mW
ForT. =+100 to 125°C (PACKAGE TYPE D) ............................................... Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
ForT. = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ................................................... 100 mW
OPERATING-TEMPERATURE RANGE (TA ):
PACKAGE TYPE D ............................................................................................... -55 to +125°C
PACKAGE TYPE E ................................................................................................ -40 to +85·C
STORAGE-TEMPERATURE RANGE (T".) ............................................. , ............................. -55 to +150·C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1132 in. (1.59 ± 0.79.mm) from case for 10 s max. . .................................................... +255·C
RECOMMENDED OPERATING CONDITIONS at TA =-40 to +85° C
For maximum reliability, nominal operating conditions should be selected so that operation Is always within the following
rang.s:
LIMITS
UNITS
CHARACTERISTIC
DC Operating Voltage Range
Min.
Max.
4
6.5
Voo
Vss
Input Voltage Range
V
STATIC ELECTRICAL CHARACTERISTICS atT. = -40 to +85°C, Voo = 5 V ± 10%, Except as noted
LIMITS
CONDITIONS
ALL TYPES
CHARACTERISTIC
Vo
Typ"
2
4
-2
Max.
-
0
0.1
Voo -0.1
Voo
-
-
0.8
(V)
(V)
Min.
-
0, Voo
-
loc
0.4
0, Voo
2.4
Output High Drive (Source) Current
10H
Voo -0.4
0, Voo
-1.2
Output Voltage Low-Level
-
0, Voo
Output Voltage High-Level
VOL
VOH
0, Voo
Input Low Voltage
V,L
0.5, Voo -0.5
-
-
Input High Voltage
V,H
0.5, Voo -0.5
-
2.4
Input Leakage Current
I,N
-
0, Voo
-
3-State Output Leakage Current
lOUT
0, Voo
0, Voo
Input Capacitance
C'N
COUT
-
-
-
0.8 V,2.4 V
-
0.8 V,2.4 V
Quiescent Device Current
Output Low Drive (Sink) Current
Ou\Qut C8Qacitance
Standby Device Current
Operating Device Current
IISee chart on page 3 for test conditions.
"Typical values are for T. = 25· C and nominal Voo.
10011
IS8v ll
10PERil
UNITS
Y,N
-
50
IIA
-
rnA
V
±1
±1
5
7.5
10
15
-
0.25
0.5
-
15
25
IIA
pF
rnA
656 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDM5332, CDM5333
COP 1882
LATCH/
DECODER
1TO
.------+lCLJ(
OTHER
\ CHI P SELECTS
CE
TPA
COPt800
SERIES
CPU
COM
6116
RAM
tlRoi-----~EI /OE
i-----~OE
MWiii------i- - - -
DATA
-i-----~WE
BUS
92CM- 36399
Fig. 3 - Typical CDP1800 series microprocessor system.
ROM ORDERING INFORMATION
All RCA mask-programmable ROM's are custom-ordered
devices. ROM program patterns can be submitted to RCA
by using a master device (ROM, PROM or EPROM), a floppy
diskette generated on an RCA development system, or
computer punch cards.
DATA PROGRAMMING INSTRUCTIONS
When a customer submits instructions for programming
RCA custom ROM's, the customer must also complete the
relevant parts of the ROM information sheet and submit this
sheet together with the programming instructions.
Programming instructions may be submitted in anyone of
three ways, as follows:
1. Computer-Card Deck -
use standard 80-column
computer punch cards.
2.
Floppy Diskette
diskette information must be
generated on an RCA CDP1800-series microprocessor
development system or the MS2000 MicroDisk develop,_
ment system.
3. Master Device - a ROM, PROM, or EPROM that contains
the required programming information.
The requirements for each method are explained in detail in
the following paragraphs:
Computer-Card Method
Use standard 80-column computer cards. Each card deck
must contain, in order, a title card, an option card, a dataformat card, and data cards. Punch the cards as specified in
the following charts:
TITLE CARD
Column No.
Data
1
2-5
6-30
31-34
35-54
55-58
59-63
64
65-71
72
73
74
75-78
79-80
Punch T
Leave blank
Customer Name (start at 6)
leave blank
Customer Address or Division (start at 35)
Leave blank
RCA custom selection number (5 digits) (obtained from RCA Sales Office)
Leave blank
RCA device type, without CDM prefix, e.g., 5332E
Punch an opening parenthesis (
Punch 8
Punch a closing parenthesis)
Leave blank
Punch a 2-digit decimal number to indicate the deck number;
the first deck should be numbered 01
658 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDM5332, CDM5333
EPROM device. Title, option, and data-format information.
which would otherwise be punched on computer cards,
must be submitted on the ROM Information Sheet. In
addition, specify the master device type; RCA will accept
Intel types 1702, 2704, 2708, 2716, 2732, 2332A, 2758,
Supertex CM3200, T.I. TMS4732, Motorola type: MCM68732
and MCM68A332 or their equivalents. If the ROM to be
manufactured is smaller in memory size than the master
device, or if more than one ROM pattern is stored in the
master device, the starting address and size of each pattern
must be stated on separate ROM Information Sheets.
To minimize power consumption, all unused ROM locations
should contain zeros.
Floppy-Dlskelte Method
The diskette contains the ROM address and data
information. Title, option, and data-format information,
which would otherwise be punched on computer cards,
must be submitted on the ROM Information Sheet. In
addition, specify the RCA Development System used to
generate the diskette (CDP18S005, CDP18S007, CDP18S008, or MS2000) and supply a track number orfile name.
If possible, include a printout of the program for verification
purposes. The format of the address and data information is
essentially the same as that described for Computer-Card
method with the addition of a carriage-return character at
the end of each line and an end-of-file character (DC3) at
the end of the file.
"RCA CMOS ROMs", RPP-610A.
Master-Device Method
Data may be submitted on a master ROM, PROM, or
"Programming 2732 PROMs with the CDP18S480 PROM
Programmer", RCA Application Note ICAN-6847.
lithe Master-Device is smaller than 4 kilobytes, the starting
address of each Master-Device must be clearly identified.
For additional information refer to the following RCA
publications:
ROM INFORMATION SHEET
How is ROM pattern being submitted to RCA?
Computer Cards
0 (Complete parts A and B)
Floppy Diskelte
0 (Complete parts A, B, and D)
Master Device (PROM) 0 (Complete parts A, B, and C)
check one
Customer Name (start at left)
CC
I-
a:
CC
a.
6-30
I I I I
I I I I I I I I I I I I I I I I
35-54
I
I I I
59-63
I I I I
I RCA Custom Number (Obtained from RCA Sales Office)
65-71
I I I I
I I I ROM Type (without COM prefix), e.g. 5332E
I I I
~
I I
I
ID
Pin
Functions
Ii: CDM5332
:
Polarity Options
CDM5333
Polarity' Options
Column #
(J
~
a.
I I I
Address or Division
=active when logic 0, X =don't care
CS1
CS2
PN
PN
X
X
X
X
X
X
X
X
PN
PN
X
X
X
X
X
X
X
X
28
29
30
31
32
34
36
37
38
39
Q
Starting and last address
of daia block in the
Master Device (in Hex).
IIIII
I I
I I I
In each column for that ROM.
P =active when logic 1, N
If a master device is submitted,
state type of ROMo/PROM:
I-
I I
Circle the ROM type desired, then circle one leiter (P, N, or X)
Circle
one
I I I I I
t-
a:
:
IIIII
If a diskette is submitted, cheCk type of
RCA Development System used:
D MS2000
D CDP18S00S
D CDP18S007
D CDP18S008
Specify: Track #
Specify: File Name:
Software program used:
Software program used:
(check one)
(check one)
D ROM SAVE
D MEM SAVE
D SAVE PROM
D SAVE PROM
°If Master Device is a ROM, state polarity of all chip select/enable functions.
m
660 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDM5364, CDM5364A
RECOMMENDED OPERATING CONDITIONS at TA = -40 to +85°C
For maximum reliability, nominal operating condltion$ should be selected so that operation is always within the
following ranges:
LIMITS
CDM5364, CDM5364A
CHARACTERISTIC
Min.
Max.
4
6
Vss
VDD
DC Operating Voltage Range
Input Voltage Range
V
AI2-----j
I
I
I
I
I
65,536 BIT
ROM
CELL ARRAY
I
I
A3
V>
a:
'"
--1---1
C>
"
"'"
'"a:
"
U
V>
V>
C>
A'
A2
"
AI
AO
QO
10
Ql
12
Q2
13
"
"
OE/OE
Features:
• Asynchronous operation
• Fast access time - 250 ns max.
• Low standby and operating power Is8y2=2 pA typical
IOPER2=10 mA max. at tcyc=1 /1s;
=30 mA max. at tcyc=250 ns
• Automatic power-down
AIO
20
CE1 ICE1
19
18
17
Q7
"
I.
Vss
CMOS 16,384-Word by 8-Bit
LSI Static ROM
Q6
Q'
QO
Q,
TOP VIEW
92CS-36225
TERMINAL ASSIGNMENT
The RCA-COM53128 is a 131,072-bit asynchronous maskprogrammable CMOS REA~-ONLY memory organized as
16,384 eight-bit words. The COM53128 is designed to be
used with a wide range of general-purpose microprocessor
systems, including the RCA COP1800 series system. Two
chip-enable inputs and an output enable function are
provided for memory expansion and output buffer control.
Either chip enable (CEl or CE2) can gate the address and
output buffers and power down the chip to the standby
• Mask-programmable chip enables
and output enable
• TTL input and output compatible
• 28-pin JEDEC standard pin out
mode. The output enable (OE) controls the output buffers
to eliminate bus contention. The polarity of each chip
enable and the output enable are user mask-programmable.
(See Data Programming instructions in this data sheet).
The COM53128 is supplied in 28-lead, hermetic, dual-inline side-brazed ceramic (0 suffix) and in 28-lead dual-inline plastic (E suffix) packages.
A1 3 - - - - 1
I
I
I
...'"o
o
"...o
0:
A3
--If--I
A2
--f--I
131,072 BIT
ROM
CF;LL ARRAY
...'"'"
0:
g
A1
AO
o----.JCS
MRD
OE i+----------j
8- BIT BIDIRECTIONAL DATA BUS
92CN-36216
Fig. 3 - Typical CDP1800 series microprocessor system.
Decoupting Capacitors
The CDM53256 operates with a low average dc power
supply current that varies with cycle time. However,
CDM53256 is a large ROM with many internal nodes.
Precharging of selected nodes during portions of the
memory cycle results in short duration peak currents that
can be much higher than the average dc value. The rise and
fall times of the peak current pulses can have a value
sufficient to generate unwanted system noise components.
To minimize or eliminate the effects of the current spikes, a
0.1 /-IF ceramic decoupling capacitor is recommended
between the Voo and Vss pins of every ROM device.
ROM ORDERING INFORMATION
All RCA mask-programmable ROM's are custom-ordered
devices. ROM program patterns can be submitted to RCA
by using a master device (ROM, PROM or EPROM), a floppy
diskette generated on an RCA development system or
computer punch cards.
DATA PROGRAMMING INSTRUCTIONS
When a customer submits instructions for programming
RCA custom ROM's, the customer must also complete the
relevant parts of the ROM information sheet and submit this
sheet together with the programming instructions.
Programming instructions may be submitted in anyone of
three ways, as follows:
1.
2.
3.
Master Device - a ROM, PROM, or EPROM that
contains the required programming information:
Floppy Diskette - diskette information must be
generated on an RCA CDP1800-series microprocessor
development system.
Computer-Card Deck - use standard 80-column
computer punch cards.
The requirements for the Master Device and Floppy Diskette
methods are described in the following paragraphs. The
requirements for all three methods are described in detail in
the RCA ROM Brochure, "Sales Policy and Data
Programming Instructions", RPP-610A.
Master-Device Method
Data may be submitted on a master ROM, PROM, or
EPROM device.
The ROM INFORMATION SHEET must be completed and
submitted with the Master-Device. In addition to the title,
option, and data-format information, specify the MasterDevice type and the first and last addresses of the data
block in the Master-Device. Acceptable Master-Device
EPROMS include types 68764, 2732, 2764, 27128, and 27256
or their equivalents.
If the Master-Device is smaller than the ROM being ordered,
the starting address of each Master-Device must be clearly
identified. If the Master-Device is a ROM, state the active
polarity of all chip-select/enable functions.
NOTE:
To minimize power consumption, all unused ROM
locations should contain zeros.
680 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1831, CDP1831C
MA7
MA6
MAS
MA4
MA3
MA2
MAl
MAO
BOSO
BUSI
BUS2
VSS
I
24
23
22
21
20
19
IB
17
16
15
14
13
~
3
4
S
6
7
B
9
10
II
12
512-Word X 8-Bit Static
Read-Only Memory
VDD
TPA
NC
CSI
CS2
MI!l5
Features:
CEO
BUS7
BUSS
BUSS
BUS4
BUS3
• Compatible with CDP1800 and CD4000-series devices
• On-chip address latch
• Interfaces with CDP1802 microprocessor without
additional components
• Optional programmable location within 64K
memory space
• Three-state outputs
TOP VIEW
NC' NO CONNECTION
92CS-275B4R2
Terminal Assignment
The Chip-Enable output signal (CEO) goes
"high" when the device is selected, and is
intended for use an an output disable control for RAM memory in a microprocessor
system.
The COP 1831C is functionally identical to
the COP1831. The COP1831 has an operating voltage range of 4 to 10.5 volts, and the
COP1831 C has an operating voltage range
of 4 to 6.5 volts.
The COP1831 and COP1831C types are
supplied in 24-lead hermetic dual-in-line,
side-brazed ceramic packages (0 suffix)
and in 24-lead dual-in-line plastic packages
(E suffix). The COP1831C is also available
in chip form (H suffix).
The RCA-COP 1831 and COP1831C types
are 4096-bit mask-programmable CMOS
read-only memories organized as 512
words x 8 bits and are completely static; no
clocks required. They will directly interface
with COP1800-series micro-processors
without additional components.
The COP1831 and COP1831C respond to
16-bit address multiplexed on 8 address
lines. Add ress latches are provided on-chi p
to store the 8 most significant bits of the
16-bit address. By mask option, this ROM
can be programmed to operate in any 512word block within 64K memory space. The
polarity of the high address strobe (TPA),
and CS1 and CS2 are user mask-programmable. (See RPP-610, "ROM Sales Policy
and Data Programming Instructions").
•00
B
U
BUS7
BUS6
BUS5
BUS4
F
F
R
E
S
S
E
R
512 x B
STORAGE
ARRAY
a
0
L
•
E
C
T
C
H
0
0
I
OUTPUT 13
BUFFERS
BUS3
BUS2
BUSI
BUS 0
E
R
MRli
19
CS2
CSI
20
21
S~e~~T
DECODE
f"IB"--........--+CEO
NO CONNECT ION' 22
VDD' 24
Vss " 12
Fig. 1 - Functional diagram.
File Number
1104
CMOS Microprocessors, Memories and Peripherals
682
CDP1831, CDP1831 C
DYNAMIC ELECTRICAL CHARACTERISTICS al TA = -4010 +85°C, Veo ±5%,
Input I" If = 10 ns, CL = 50 pF, RL = 200kO
LIMITS
TEST
CDP1831C
CDP1831
CONDITIONS
CHARACTERISTIC
Access Time from
Address Change,
t ..
Access Time from
Chip Selecl,
lAcs
Chip Selecl Delay,
Ics
Address Selup Time,
lAS
Address Hold Time,
tAH
Read Delay, tMAo
Chip Enable Outpul
Delay from Address,
teA
Bus Conlention Delay,
Veo
(V)
UNITS
Mln,t Typ."
Max.
Mln.t Typ."
Max.
5
10
850
350
1000
400
850
1000
5
10
700
250
800
300
700
800
5
10
5
10
5
10
5
10
600
200
300
600
50
50
25
150
75
5
10
ns
150
300
100
500
150
300
500
500
200
200
100
600
250
500
600
350
200
350
5
150
10
to
200
200
TPA Pulse Width,
5
10
70
IpAw
tTime required by a limit device to allow for the indicaled function.
'Time required by a typical device to allow for the indicated function. Typical values are for
TA = 25' C and nominal Voo
MA
tAA-----~
TPA----...J
F_fACO--+••' _
CS _ _
~-
BUS _ _ _ _..;.H"'IG;,;;"...;Ic.:;M..;.PE;;.;O;.;.A;;.;N.;.;CE:.--+_ _ _ _ _--- MRD
ADDR BUS
TP8
TPA
--
Q
DATA
)?jROM
~
CPU
RAM
CDP1837C
/~/
------
Instructions"in this data
l~
,.----ADOR BUS
(See Data Programming
sheet).
CDPt800
SERIES
/
;
MRD
-----
MRD
SCO SCI
INTERRUPT
I/O
CONTROL
DMA IN OiiA::niTT
MWR
~/~. -
CEO
EFI-EF4
~
I
II
8-BIT
II
81DIRECTIONAL DATA BUS
I
92CM-35120
Fig. 1 - Typical COP1 BOO Series microprocessor system.
File Number 1381
702 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1837C
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85° C, Voo = 5 V ± 5%, except as noted
LIMITS
CONDITIONS
CHARACTERISTIC
CDP1837C
Quiescent Device Current
100
UNITS
VO
(V)
VIN
(V)
Min.
Typ.·
Max.
-
0, Voo
-
5
50
Output Low Drive (Sink) Current
IOL
0.4
0, voo
0.8
1.6
-
Output High Drive (Source) Current
IOH
Voo -0.4
0, Voo
-0.8
-1.6
-
Output Voltage Low-Level
VOL
-
0, Voo
-
0
0.1
Output Voltage High-Level
VOH
-
0, Voo
Voo -0.1
Voo
-
Input Low Voltage
VIL
Voo -0.5
-
-
-
1.5
Input High Voltage
VIH
Voo -0.5
-
3.5
-
-
Input Current
liN
-
0, Voo
-
-
±1
lOUT
0, voo
0, voo
-
-
±2
IOPER·
-
0, voo
-
5
10
CIN
-
-
-
5
7.5
COUT
-
-
-
10
15
3-State Output Leakage Current
Operating Device Current
Input Capacitance
Output Capacitance
/1A
mA
V
/1A
mA
pF
'Typical values are for TA = 25°C and nominal Voo .
• Outputs open circuited; cycle time 1 iJS.
-----~riT
BIDIRECTIONAL DATA IBUj
II
~
----
-"
-----
ADDA BUS
--y
TPA
ADDR BUS
ROM
ROM
No.1
No.2
~ ----
ADDR BUS
m...
RAM
CDPI837C
CDPIB37C
Mlm
CEO
OF SELECT
SIGNAL
----
CS
----CEI
!R'l
cs
CEO
CS
92CS-35122RI
Fig. 3 - Daisy chaining CDP1837C's.
"Daisy Chaining" with CEI inputs and CEO outputs is used
to avoid memory conflicts between ROM and RAM in a user
system. In the above configuration, if ROM No. 1 was
masked-programmed for memory locations 0000-OFFF16
and ROM No.2 masked-programmed for memory locations
100016-1 FFF16, for addresses from 0000-1 FFF16, the RAM
would be disabled and one of the ROMs enabled. For
locations above 1FFF16, the ROM's would be disabled and
the RAM enabled.
704 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP1837C
\
MA
J
HIGH ORDER
ADDRESS BYTE
LOW ORDER
ADDRESS BYTE
~tAS-
tAVQV
I-" r - t AH
tpAW~1\
TPA
-
II )
MRD
-
t RSU ' - -
tSVQV
V
-
t SVQX BUS
r--
JI\.
(4)
)
t RXCL
OUTPUT
HIGH IMPEDANCE
~ ACLTOI~E j
VALID
t RXQZ
f4r-
K
tSXQZ
r-r--
DATA
J
to
I--tCA(3 )
CEO
-'~
tCEIO
----,
eEl:
92CM
-
37229
Fig. 4 - Timing diagram.
Notes:
(1) MRD must be valid on or before the trailing edge of
TPA. (Output will be trl-stated and the ROM powered
down when MRD is not valid.
(2) CS (CS1 and CS2) controls the output buffers only.
Output will be trl-stated when either CS1 or CS21s not
valid.
(3) CEO is high when ROM is enabled.
(4) Provided tAvav is satisfied.
706 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP65516
Product Preview
ACO
18
Vee
AC1
17
G
A02
IS
AO'
15
M
AO'
I.
S
AOS
13
E
AOS
12
AIO
"
A9
AC7
Vss
10
A8
TOP VIEW
92CS-:5~113
CMOS 2048-Word X 8-Bit Static
Read-Only Memory
Features
• 3 to 6 volt supply
• Access time
430 ns (5 V) CDP65516-43
550 ns (5 V) CDP65516-55
• Low power dissipation
15 mA maximum(active)
30 Jl.A maximum (standby)
• Directly compatible with muxed bus
CMOS microprocessors
• Pins 13, 14, 16, and 17 are mask programmable
• MOTEL mask option also insures direct
compatibility with many NMOS
microprocessors
• Standard 18-pin package
TERMINAL ASSIGNMENT
The CDP65516 is a complementary MaS mask programmable byte organized read-only memory (ROM). The
CDP65516 is organized as 2048 bytes of 8 bits, designed for
use in multiplex bus systems. It is fabricated using silicon
gate CMOS technology, which offers low-power operation
from a single 5-volt supply.
The memory is compatible with CMOS microprocessors
that share address and data lines. Compatibility is enhanced
by pins 13, 14, 16, and 17 which give the user the versatility
of selecting the active levels of each. Pin 17 allows the user
to choose active high, active low or a third option of
programming which is termed the "MOTEL" mode. If this
mode is selected by the user, it provides direct compatibility
with the CDP6805E2 type microprocessor series. In the
MOTEL operation the ROM can accept either polarity
signal on the data strobe input as long as the Signal toggles
during the cycle. This unique operational feature makes the
ROM an extremely versatile part.
AOO-A07
E
S
E
G
PIN NAMES
M-------_.
AOO-A07 ..
AS-AlD ...
M ..
E
S ...
G ..
S
Disables
Output Buffers
E, E Limit
Power Dissipation
.. ..... Address/ Data Output
Address
Multiplex Address Strobe
.Chip Enable
.. ... Chip Select
.. ..... Data Strobe (Output Enablel
ROM Array
1128x 1281
Fig. 1 - Block diagram.
File Number
1376
708 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP65516
1+---------
tMHMH (Read Cycle Tlmel-------------t~
tMHML
M
VIH - - - - - - - - - - - - . , .
tELML
tEHML
VIH _ _ _ _ _ _ _ _ _ _
_-..
E and
E
Deselect Mode
VIL - - - - - - - - - - . /
VIH
Don't Care
A8toAl0
VIL
tGLDZ
VIH
High Z - VOH
Don't Care
AOO to A07
- VOL
VIL
Fig. 2 - Read cycle timing waveforms.
Functional Description
The 2K x8 bit CMOS ROM (CDP65516) shares address and
data lines and, therefore, is compatible with the majority of
CMOS microprocessors in the industry. The package size is
reduced from 24 pins for standard NMOS ROMs to 18 pins
because of the multiplexed bus approach. The savings in
package size and external bus lines adds up to tighter board
packing density which is handy for battery-powered handcarried CMOS Systems. This ROM is designed with the
intention of having very low active as well as standby
currents. The active power dissi pation of 75 mW (at Vcc=5 V,
freq.=1 MHz) and standby power of 150 JiW (at Vcc=5 V) add
up to low power for battery operation. The typical access
time of the ROM is 280 ns making it acceptable for operation
with today's existing CMOS microprocessors.
An example of this operation is shown in Fig. 3. Shown is a
typical connection with the CDP6805E2 CMOS microprocessor. The main difference between this system and
competitive process is that the data strobe (DS) on the
CDP6805E2 and the read bar (RD) on the competitive
process both control the output of data from the ROM but
are of opposite polarity. The 2K x 8 ROM can accept either
polarity signal on the data strobe input as long as the signal
toggles during the cycle. This is termed the MOTEL mode of
operation. This unique operational feature makes the ROM
an extremely versatile part. Further operational features are
explained in the following section.
Operational Features
In order to operate in a multiplexed bus system the ROM
latches, for one cycle, the address and chip-select input
information on the trailing edge of address strobe (M) so the
address signals can be taken off the bus.
Since they are latched, the address and chip-select signals
have a setup and hold time referenced to the negative edge
of address strobe. Address strobe has a minimum pulse
width requirement since the circuit is internally precharged
during this time and is set up for the next cycle on the
trailing edge of address strobe. Access time is measured
from the negative edge of address strobe.
The part is equipped with a data strobe input (G) which
controls the output of data onto the bus lines after the
addresses are off the bus. The data strobe has three
potential modes of operation which are programmable with
the ROM array. The first mode is termed the MOTEL mode
of operation. In this mode, the circuit can work with either
the 6805 or 8085 type microprocessor series. The difference
between the two series for a ROM peri pheral is only the
polarity of the data-strobe signal. Therefore, in the MOTEL
mode the ROM recognizes the state of the data-strobe
signal at the trailing edge of address strobe (requires a
setup and hold time), latches the state into the circuit after
address strobe, and turns on the data outputs when an
opposite polarity signal appears on the data-strobe input. In
this manner the data-strobe input can work with either
polarity signal but that signal must toggle during a cycle to
output data on the bus lines. If the data strobe remains at a
dc level the outputs will remain off. The data-strobe input
has two other programmable modes of operation and those
are the standard static select modes (high or low) where a
dc input not synchronous with the address strobe will turn
the output on or off.
The chip-enable and chip-select inputs are all programmable
with the ROM array to either a high or low select. The chip
select acts as an additional address and is latched on the
address-strobe trailing edge. On deselect the chip select
merely turns off the output drivers acting as an output
disable. It does not power down the chip. The chip-enable
inputs, however, do put the chip in a power down standby
mode but they are not latched with address strobe and must
be maintained in a dc state for a full cycle.
710 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP65516
~
CASSETTE
READ
f.--FROM CASSETTE
RECORDER
INTERFACE
FOR USER
J
IRQ
FOR USER
TIM
RESET
' - - - - FROM USER HARDWARE
A8-AI2, AS,DS,RI W
h
CDP6818
REAL-TIME
CLOCK
CDP65516
ROM
{;
V
\7
t-
ADDRESS
DECODE
l-
=>
CDP6805E2
MPU
k:
CDM5332
CDM6116
ADDITIONAL
MEMORY
~
{~
{
BO-B7
.....
~
CDPI873
3TO 8
DECODER
~
~
6,4
KEYPAD
ROWS
COLUMNS
PAO- PA3
PA6
DATA
PA7
CLOCK
BPI-BP4
FPI-FPI2
=::>
:>
LCD
r
CASSETTE
WRITE
INTERFACE
Fig. 5 - Expanded CBUGOSsystem.
ADDITIONAL
PERIPHERALS
r-
TO CASSETTE
RECORDER
92CL-3!5117
712 ______________ CMOS Microprocessors, Memories and Peripherals
CDP65516
DATA PROGRAMMING INSTRUCTIONS (Cont'd)
DATA CARDS
The data cards contain the hexadecimal data to be programmed into the ROM device.
Each card must contain the starting address plus sixteen words of data in clusters of four Hex Bytes.
Column No.
Data
Column No.
Data
1-4
Punch the starting address
26-27
2 hex digits of 9th WORD
2 hex digits of 10th WORD
in hexadecimal for the
28-29
following data.'
30
Blank
5
Blank
31-32
2 hex digits of 11th WORD
6-7
2 hex digits of 1st WORD
33-34
2 hex digits of 12th WORD
8-9
2 hex digits of 2nd WORD
35
Blank
10
Blank
36-37
2 hex digits of 13th WORD
2 hex digits of 14th WORD
11-12
2 hex digits of 3rd WORD
38-39
13-14
2 hex digits of 4th WORD
40
Blank
15
Blank
41-42
2 hex digits of 15th WORD
16-17
2 hex digits of 5th WORD
43-44
2 hex digits of 16th WORD
18-19
2 hex digits of 6th WORD
45
Semicolon, b,ank if last card
20
Blank
21-22
2 hex digits of 7th WORD
46-78
Blank
23-24
2 hex digits of 8th WORD
79-80
25
Blank
Punch 2 decimal digit~
as in title card
'The address block must be contiguous starting at an even-numbered address.
Column 4 must be zero.
OPTION DATA CARD
, :I: 3 4 5
op., 10
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714 _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
716 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP18S693 and CDP18S694
RCA COSMAC
Microboard Computer Development Systems (MCDS)
RCA's Low-Cost Microboard Computer Development System (MCDS) CDPI8S693 Combines:
o CMOS Microprocessor Architecture CDPI802A
o CMOS Microboard Computer Module
CDP18S601
o CMOS Microboard Memory and Tape I/O
Module CDP18S652
o ROM-Based Basic 3 Interpreter with Full
Floating-Point Arithmetic
o ROM-Based Monitor Program UT62
o Cassette I/O Unit for Mass Memory Storage
o RS232C or 20-mA Terminal Interface with Baud
Rates to 1200
o Five-Card Chassis and Case
o Five-Volt Power Supply
Add a data terminal and you have a CMOS
Microcomputer Development System at a surprising, unbelievably low cost.
With the CDP18S693 Microboard Computer Development System YOU can:
o Develop CDP1802 and/or Microboard software
o Program with floating-point Basic 3
o Use the system as a dedicated controller
o Expand system with any of the extensive
Microboard family
o Expand system to use ROM-based Assembler/
Editor
o Expand memory to full 65 kilobytes
o Extend I/O capabilities with analog and/or
digital I/O Microboards
RCA's Higher-Performance Microboard Computer
Development System (MCDS) CDPI8S694
Combines:
o CMOS Microprocessor Architecture CDP1802A
o CMOS Microboard Computer Module
CDP18S601
o CMOS Microboard Memory and Tape I/O
Module CDP18S652
o ROM-Based Assembler/Editor Program
o ROM-Based Basic 3 Interpreter with Full
Floating-Point Arithmetic
o ROM-Based Monitor Program UT62
o Two Cassette I/O Units for Mass Memory
Storage
o RS232C or 20-mA Terminal Interface with Baud
Rates to 1200
o Five-Card Chassis and Case
o Five-Volt Power Supply
o PROM Programmer Module and Software
CDP18S680
Add a data terminal and you have an even
higher-performance CMOS Microcomputer Development System at a surprising low cost.
With the CDP18S694 Microboard Computer Development System YOU can:
o Develop CDP1802 and/ or Microboard software
o Program with floating-point Basic 3 or assembly
language
o Use the ROM-Based Assembler/Editor to develop software
o Create ASCII files on cassette tape (EDITOR)
o Convert Level I source code on tape into
executable machine language on another tape
(ASSEMBLER)
o Program RCA and other industry-standard
UV-erasable PROM's
o Use the system as a dedicated controller with
optional run-time Basic 3 (ROM)
o Expand the system with any of the extensive
Microboard family
718 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP18S693, CDP18S694
The COSMAC Microboard Computer Development
Systems (MCDS) CDPI8S693 and CDPI8S694 are
economical and versatile systems for the development of
the hardware and software for applications based on the
RCA 1800 series of CMOS microprocessor products.
With the optional run-time Basic 3 available on ROM,
and with the addition if needed of any of the many
available expansion Microboards, the MCDS may be
used very effectively for control, testing, or other
dedicated microcomputer applications.
The CDPI8S693 includes a five-card chassis with case,
a 5-volt power supply, a CDPI8S601 Microboard
Computer, a CDPI8S652 Microboard Combination
Memory and Tape I/O Control Module augmented with
a ROM-based monitor program and a ROM-based
extended Basic 3 interpreter, an audio cassette tape
system for mass memory storage, and the cables needed
for connecting a data terminal and for connecting the
cassette drive system to the CDP18S652.
The CDPI8S694 has all the features of the CDPI8S693
plus the following. In an additional three-ROM set on the
CDP 18S652, a Level I text Editor and Assembler enables
the user to create CDPI802 machine language programs
in Levell mnemonics. A PROM Programmer Module is
also provided along with a control program on cassette
tape that enables the user to program a wide variety of
EPROM's. A second audio cassette drive unit is included
to support the Editor and Assembler operations.
The power supply for the card nest is wired through a
disconnect plug to the universal backplane. Power
Converter Type CDPI8S023VI is for IIO-volt operation
and Type CDPI8S023V3 is for nO-volt operation. The
dc output is 5 volts at 600 milliamperes.
The cassette recorder unit is connected to the
CDPI8S652 controller board by means of a 3-wire
interface cable. The unit uses economical audio-type
cassette tape. The controls on the cassette recorder
include a tone control, a volume control, and play,
record, rewind, fast forward, stop, and eject buttons.
The unit also has a tape counter. The recorder drive
mechanism is controlled through the "remote" jack by
the software to provide system control of the tapes. A
60-minute tape can store over 115,000 ASCII bytes per
side.
Versions for both domestic and overseas operation are
available. Models CDPI8S693VI and CDPI8S694VI
operate on 110-120 volts ac, 60 Hz; models
CDPI8S693V3 and CDPI8S694V3 operate on nO-240
volts ac, 50 Hz.
Hardware Features
A five-card chassis and case houses the Microboards
provided with the MCDS. The CDPI8S693 includes the
CDPI8S601 Microboard Computer and the CDPI8S652
Combination Memory and Tape I/O Control Module.
The CDPI8S694 includes the CDP18S601. CDP18S652.
and a PROM programmer module. The chassis and case
assembly has openings at the bottom and end to permit
easy access to the cabling terminal connections.
Two cables are provided for connecting the usersupplied data terminal. The CDPI8S516 cable is for
terminals using the EIA RS232C interface and the
CDP I 8S5 I 5 is for terminals using a current loop
interface. Either cable can be connected to the
CDPI8S601 Microboard Computer. No handshaking
lines are required for operation. When an EIA RS232C
data terminal is used. its 5-volt supply is available at the
backplane, but the user must provide the additional -5 to
-15 and +12 to +15 volts required.
The CDPI8S694 includes all the items provided with
the CDPI8S693 plus a second cassette recorder unit for
additional mass memory storage, a ROM-based Editor/
Assembler, and a PROM Programmer module with
cassette-tape software. The Editor; Assembler ERPOM's
(3) are on the CDPI8S652 Combination Memory and
Tape I; 0 Control Module.
720 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP18S693, CDP18S694
followed by a verification; (2) verifying a PROM against
a RAM buffer or file; (3) copying a PROM into a RAM
buffer, automatically followed by a verification; (4) filling
a RAM buffer wi!h all I's or O's used in verifying PROM
erasure; and, (5) saving a RAM buffer onto a tape. The
software is designed for flexibility so that, in addition to
the basic operations provided, more sophisticated
procedures can be derived.
Optional Software
The Bulc 3 Run-time version CDPI8S842 allows the
user to execute his program in any CDP 1802·based
system. This version starts program execution automati·
cally after reset. Thus, the user may develop his program
using the Basic 3 development version supplied with the
MCDS and then for his final turnkey operation, use the
Basic 3 Run·time version. To use Run·time Basic an
additional Microboard such as the CDPI8S626 32/64·
kilobyte ROM/ PROM/ RAM is required. (Part number
CDP18S842)
Accessory and Expansion Options
Microboard Expansion Modules. The user can add any
of the many CPDl8S600·series Microboards to provide
I/O expansion or expanded peripheral interfacing.
Microboards have a wide temperature range; normal
operation is at -40 to +85°C with exceptions. (Booklet:
COSMAC Microboard Computer Systems CMB·250)
Beta Test Subsystem
Printer Option
With the CDPI8S646 Microboard printer interface, the
user can add a parallel Centronics.type printer and obtain
hard copy output from cassette tape using the Editor P
command. With a serial printer used in combination with
a video terminal and connected to one of the CDP.l8S601
serial output ports, the user can obtain a hard copy
output through the T command.
Components Available Separately
for Replacement or Upgrading
CDPI8S601 Microboard Computer
CDPI8S652 Combination Memory and Tape I/O
Control
CDPI8S680 PROM Programmer Module and
Software
CDPI8S810 Audio Cassette Recorder Unit
CDPI8SUT62 MCDS Monitor ROM
CDPI8S841 MCDS Basic 3 Interpreter ROM set
(development)
CDPI8S842 MCDS Basic 3 Interpreter ROM set
(run·time)
CDPI8S843 MCDS Assembler/Editor ROM's
CDPI8S646 Microboard Printer Interface. Parallel
Centronics Type
System Controller
V'deo
Monitor
rM~le~r~~om=p~u-.e-r--JC'-----A-U-dl-O-Ta-~--t-1~
-<
Development System
Tn.
Device
Progrlmmed In PLM 1800
Programmed In S ••le
~
Actual MCDS Application
This diagram illustrates a practical application of
Microboards and the Microboard Computer Development
System (MCDS) in custom production test equipment.
This particular custom tester, in actual use in RCA's
Malaysian plant, tests and sorts transistors. I n addition to
the Beta test shown, other processor-controlled
subsystems test for saturation voltage, breakdown
voltage, leakage, and switching parameters. High-level
languages were used for rapid program development. For
the test subsystems, PLM was chosen because it contains
built-in constructs for programming the 1/0 Microboards.
For the system controller, Basic was chosen because it
provides the human interaction and the floating-pOint
arithmetic needed for displays and report generation.
Note that the MCDS was both the basic development
tool and the final control system.
722 _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP18S693, CDP18S694
Here are some answers you might want while you are
considering the many advantages of the MCDS.
How will the Editor/Assembler help me?
The many advantages of CMOS (ComplementarySymmetry Metal-Oxide Semiconductor) include ultra-low
power dissipation, high noise immunity, operation from a
single power supply with a wide operating range or even
from batteries, and a wide temperature range. RCA has
been the leader in CMOS since its inception.
The ROM-based Editor supplied with the CDPI8S694
will help you generate ASCII files in CDPI802 Assembly
language, Basic 3 instructions with line numbers, or
simply text. The Assembler converts source files into
executable machine language programs. With the Editor /
Assembler, you can write programs faster and more
accurately using mnemonics instead of machine language.
And you get error messages to speed up program
debugging.
Why Mlcroboards?
How much memory do I get?
RCA Microboards are simple-to-use, small-size (4.5 x
7.5 inches), high-performance modules that take advantage of all the CMOS features. CMOS Microboards can
provide reliable operation in high-noise process-control,
automotive, or production environments and are especially effective in remote or portable applications. Because
Microboards are designed to fit a compact universal
backplane, you have a broad selection of readily
interchangeable Microboards for performance expansion.
To assure reliable operation, all Micro,boards are tested,
burned-in for 72 hours at maximum rated temperature,
and then retested.
With the MCDS you get 5 K of RAM and 4 sockets
for up to 8 K of ROM. You also get 20 K of ROM
containing the UT62 Monitor (2 K), Basic 3 (12 K), and,
in the CDP18S694, the Editor! Assembler (6 K). Microboard Memories can be added and for mass memory
storage you can use the tape cassettes.
Why CMOS?
Why should I use the MCDS?
MCDS is an economical highly versatile development
system for CDPI802 CMOS Microprocessor hardware
and software applications. With MCDS you can program
with floating-point Basic 3 or the ROM-based
Assembler/ Editor and take advantage of the PROM
programmer. You can expand your system with any of
more than 45 different Microboard products, expand
memory to 65 kilobytes, and extend the I/O with both
analog and digital Microboards. MCDS can be not
only your development system but also your final
target system.
What's so unusual about MCDS Basic 3?
The Basic 3 Interpreter ROM features full floatingpoint arithmetic, line editing, trace debugging, cold or
warm start, tape control, up to 6682 multiple-character
variables, strings and arrays, plus access to CDPI802 I/O
constructs. It allows calls to user machine-language
routines and provides I/O instructions for any added
M icroboard. Another big plus for Basic 3 is a special
ROM-based run-time version for executing your program
on any CDP1802 system. With run-time Basic 3 and the
user program in memory (either RAM or ROM), your
program will begin execution immediately after reset,
Why audio tape cassettes?
Audio-type magnetic tapes on cassettes provide a
low-cost, reliable means of mass memory storage. On a
60-minute tape you can store over 115,000 ASCII bytes
per side. The record unit is software controlled and
operated through the Monitor program. With two units,
provided with the CDPI8S694, the Editor/ Assembler
operations are supported at minimum cost.
Can I use this low-cost microcomputer
as a dedicated controller?
Very definitely. Because of its relatively low cost, the
optional run-time Basic, and its mass memory storage,
the M CDS is an excellent choice for many dedicated
control, custom testing, or data acquisition tasks. A
practical example is shown on page 460.
How can I expand the MCDS capabilities?
An easy question. Just request a copy of COSMAC
Microboard Computers Systems CMB-2S0 and read
about the more than 45 different CMOS Microboard
products for your system. This eomprehensive product
guide describes Single-Board Computers, Memories,
Digital I/O's, Video-Audio-Keyboard Interfaces, A/D
Converters, 0/ A Converters plus accessory hardware.
And our rapidly growing Microboard family always has
more on t'he way.
Is the MCDS really "unbelievably" low cost?
This question you can best answer for yourself by
making the same comparisons that we did. If you find
any other system with comparable performance at
anything near a comparable price, please let us know.
724 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP18S695
RCA Color-Enhanced
Microboard Computer Development System
A Complete Stand-Alone Color System for
CMOS Microcomputers at Unbelievably Low Cost
Hardware Features:
• CMOS Microprocessor Architecture
• CMOS Microboard Computer CDP18S601
• CMOS Microboard Memory and Tape I/O
Module CDP18S652
• CMOS Microboard Video, Audio, Keyboard
Interface CDP18S661B
.
• CMOS PROM Programmer CDP18S680
• Keyboard· VP601
• 100Inch Color Monitor
• 8-Card Industrial Chassis or
S-Card Chassis and Case
• S-Volt Power Supply
• Two Audio-Cassette-Tape I/O Drives
• All Required Cables
• 20-Line Parallel I/O • 2 Serial I/O Lines
Software Features:
• Floating-Point BASIC3 with 73 Statements and
Functions plus CDP1802 I/O Constructs
• ROM-Based Editor
• ROM-Based Assembler
• ROM-Based Monitor Including 13 Utility Commands
• Dual Tape-Based PROM Programmer
• 5 K RAM and 30 K ROM Expandable to 64 K
• Tape-Based Mass-Memory Storage
plus
• Membership in RCA Software Users Group
What You Can Do With Color-Enhanced
Microboard Computer Development System
•
•
•
•
•
•
..
•
Develop Software for Any CDP1802 or Microboard Applications
Use Color for Cursor and to Distinguish User Inputs from Computer Responses
Use Background Color to Identify Monitor versus Program Development Modes
Speed Up and Simp1ify Editing and Program Development
Develop Software in Assembly Language or BASIC3 High-Level Language
Write Your Entire Program in BASIC3 with Total I/O Handling
Use Color for Your Application
Expand with Any RCA Memory or I/O Microboard
Hardware Components
(5-Card Chassis shown)
of Color-Enhanced
Microboard Computer
Development System
CDP18S695V1
(For domestic use).
726 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP18S695
Interpreter, the Editor, the Assembler, or a usergenerated program at any address, and (4) debugs
programs. The thirteen UT63 Monitor commands are
Memory Move, Memory Fill, Memory Substitute,
Memory Display, Memory Insert, Program Run, Read
Tape, Write Tape, Rewind Tape, Copy Tape to
Screen, Run Basic, Run Editor, and RUn Assembler.
Callable Read and Type routines permit
communication between the video monitor and
keyboard.
• DO-1F
0000 F810
0008 2204
0010 6300
00181202
2A30 7A30 204F;
6060 F018 1202;
6408 A33F 4500;
633A A367 3000
• 10 F822B3D4
• S10083-12 46-34 2A-30
0103 33-00 A9- B6-23
program loads the object code into memory for
execution, or the PROM Programmer can put it into
EPROM. The Assembler permits the user to write
programs using convenient mnemonic expressions
rather than machine language. Error messages assist in
debugging.
The PROM programmer software enables the rapid
copying, verifying, reading, and programming of the
RCA CDPI8U42, the Intel 2708, 2758, and 2716 UVerasable PROM's, or equivalents .
Demonstration
of Video
Overlay - a
Potential
Application
Utility/
Monitor
Debug
Session
• F200-300 5A
"
••
The resident ROM-based Editor program allows the
user to create ASCII files on cassette tape. These files
can be Level I CDPI802 language, BASIC3
instructions with line numbers, or simply text. The
Editor Level I output file becomes the input file for
the Assembler. The Editor commands include: Move
pointer to beginning of buffer, Move pointer to end of
buffer, Move pointer by n characters, Move pointer by
n lines, Define input tape, Append lines, Insert text,
Delete n lines, Save n lines, Get saved text, Find text,
Substitute text, Define output tape, Type n lines, ,
Write n lines to output tape, Write entire buffer to
output tape, Print n lines, Return to UT63, and Quit
session and restart Editor.
.E
MODS TAPE EDITOR VEA. 0.0
->1 .. THiSis'A"TEST'LDI #34; PLO RF
LDI #20; PHI RF
$$
->U$$
j;'A - -- -
"
--
~-
--
Editor/
Assembler
Program
Start-up
MODS ASSEMBLER VER. 0.0
READ?O
WRITE?1
PRESS PLAY ON READ TAPE
TYPE ANY KEY.
The resident ROM-based Assembler program
converts a Level I source file on tape (source code)
into an executable machine language program on
another tape (object code). The UT63 Monitor
Optional Software
The BASIC3 Run-time version CDPI8S842 allows
the user to execute his program in any CDP1802based system. This version starts program execution
automatically after reset. Thus, the user may develop
his program using the BASIC3 development version
supplied with the CMCDS and then for his final
turnkey operation, use the BASIC3 Run-time version.
(Part number CDP18S842)
The VIS Interpreter, CDPI8S836 on cassette, is an
interpretive language designed to control the video
interface system of the CDPI8S661 B Microboard
Video-Audio-Keyboard Interface. Its interpretive
command set provides simple control oftext, graphics,
and motion on a color screen.
Fixed-point binary arithmetic subroutines are
available on ROM CDPR582. This ROM contains a
set of 16-bit 2's-complement arithmetic subroutines
designed to operate on a CDPI802 microprocessor
system.
Microboard Expansion Modules
The user can add any of the many CDP18S600series Microboards to provide 110 expansion or
expanded peripheral interfacing. Microboards have a
wide temperature range; normal operation is at -40
to +85°C with exceptions. (Booklet: COS MAC
Microboard Computer Systems CMB-250)
728 _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP18S695
Why the Low-Cost RCA Color Mlcroboard Computer
Development System (CMCDS) Is Your Best Entry Into
Microcomputers
Here are some answers you might want while you are
considering the many advantages of the CMCDS.
Why Mlcroboards?
RCA Microboards are simple-to-use, small-size (4.5
x 7.5 inches), high-performance modules. Microboards
can provide reliable operation in high-noise processcontrol, automotive, or production environments and
are especially effective in remote or portable
applications. Microboards are designed to fit a
compact universal backplane and give you an
extremely broad selection of readily interchangeable
Microboards for performance expansion. To assure
reliable operation, all Microboards are tested, burnedin for 72 hours at maximum rated temperature, and
then retested.
What Does Color Enhancement Do for Me?
Color enhancement has several major benefits. It
speeds up and simplifies editing and program
development (I) by using a unique cursor color that
quickly identifies it, (2) by using different colors for
user keyboard input and for computer response and
(3) by using different background colors to identify
whether the utility program is in control or whether
the system is in the program development mode. In
addition, colors can be used in the display with your
application.
Actual CMCDS Applications
This diagram illustrates a practical application of
Microboards and the Color Microboard Computer
Development System (CMCDS) in custom production
test equipment that tests and sorts transistors. In
addition to the Beta test shown, other processorcontrolled subsystems test for saturation voltage,
breakdown voltage leakage, and switching parameters.
Beta Test Subsystem
Can the CMCDS Be the Heart of
My Final Product?
Because the CMCDS is a Microboard system
expandable with any RAM or 1/0 Microboard,it can
readily become your end product for control, testing,
or data acquisition tasks. For example, with a
CDPI8S642 DI A Converter and suitable controllers
you can make a remote control system that could have
up to 115,000 instruction bytes on one cassette.
Because of their low power, the CMCDS CPU
Microboard and a CDP 18S658 AI D Converter can
comprise a battery-powered remote-data-acquisition
system. And, if needed, the CDPl8S653 MODEM
Microboard can add a communications link between
you and your remote system.
Your CMCDS can also be a field-programmable
controller or data access system. Write your program
in BASIC3 using the system in Run or Direct Execute
mode as needed for debugging. Then, with the PROM
Programmer put your program in EPROM and use
Run-time BASIC for the final system. If a change in
the program becomes necessary because of changing
requirements, .merely restore the BASIC3 ROM's and
you can reprogram, debug, and remake EPROM's to
meet the new requirements.
High-level languages were used for rapid program
development. For the test subsystems, PLM was
chosen because it contains built-in constructs for
programming the 1/0 Microboards. For the system
controller, Basic was chosen because it provides the
human interaction and the floating-point arithmetic
needed for displays and report generation.
Note that the CMCDS was both the basic
development tool and the final control system.
System Controller
Koybanl
Color
Video
Monllor
Programmed In PLM 1800
92CM-!45!,O
73o _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
MS2000A, MS2000AE
The backplane is a standard Microboard Universal Bus
in which any module may occupy any position. The
backplane signals and their pin assignments are shown in
the User Manual for the MS2000A.
The user may wish to rearrange the position of the
existing modules when adding expansion modules. For
example, if a UART card or a Modem card is added, the
two memory cards can be moved to slots 13 through 16 to
place the serial-interface card near the left side for ease of
cable entry.
When using the PROM Programmer CDP18S680, the
left side panel may be removed and the Programmer
placed in slot I for access through the left-hand end bezel.
The Microboard Computer supplied as the CPU of the
system is a variant of the CDPI8S605 Microboard
Computer. The on-board memory has been left out
because the system memory is wholly contained in the two
memory Microboards. As a result, the CDP 1802A
Microprocessor and the CDPI854A UART are the main
functional units. The UART provides the serial-data path
to an external data terminal through the RS232C interface.
The baud rate is selectable by the setting of a DIP switch
on the CPU Microboard. Baud rates from 50 to 19,200
are available.
One of the two Microboard Memory cards is a variant
of the CDPI8S632 and the other is a variant of the
CDP 18S628. The former is populated with 32 kilobytes
of RAM and occupies memory space from OOOOH
through 7FFFH (H indicates hexadecimal notation). The
latter is populated with 30 kilobytes of RAM and 2
kilobytes of ROM. The ROM contains the monitor
program UT70. The ROM occupies memory space
8000H through 87FFH, and the RAM 8800H through
FFFFH.
The Microboard Disk Controller, CDP18S651, provides
the I I 0 interface between the system software and logic
and the two disk drives. Instruction and status data are
transferred by output and input commands; bit data are
transferred by Direct Memory Access (DMA). The logic
to control the DMA process is built into the disk
controller Microboard to interface with the on-chip
DMA controller of the CDPI802A on the CPU Microboard. At the end of a DMA transfer, external flag EF3 is
used to signal the completion to the software. The
monitor program UT70 contains the 110 driver routines
for performing all the commands for the disk operating
system (MicroDOS). The disk controller can perform the
following instructions:
•
•
•
•
•
•
•
Seek a track
Format a track
Write a sector
Read a sector
Read mUltiple sectors
Write multiple sectors
CRC READ (Read without data transfer but
With error checking)
• Recalibrate (Return heads to home position
On track 00)
• Scan Equal (Check memory =disk data)
The disk controller is capable of a variety of formats.
Consult the Specifications section for the format and disk
organization used by the M S2000.
The two MicroDisk drives are contained in the MSIM
50 module. The module occupies eight slots in the 20-slot
chassis. An edge connector picks up power from the
backplane, and power-conditioning circuits then provide
+5 and + 12 volts to the two disk drives. The signal cable is
a "daisy chain" configuration using a 26-wire flat cable.
The drives are labeled 0 and I, corrresponding to the
drive number used in the MicroDOS commands. Drive 0
is the left drive.
The mating 3.5-inch diskette has a hard cover with a
sliding cover over the head access window.
The MSIM 40 or MSIM 40E Power Supply Module
plugs into the system chassis and occupies four slots. The
edge connector supplies +5, +15, and -15 volts to the
system back plane and interfaces the control logic to the
system. An AC input cord, fuse holder, power on-off
switch, and power-on indicator (+5-volt LED) are on the
front panel. In addition to the power functions, the front
panel provides two system control switches and a running
indicator. The RUN UTILITY (RNU) switch, when
pressed down, causes a system reset followed by a start at
address 8000H, the beginning of the monitor program
UT10. The RUN PROGRAM (RNP) switch, when
pressed down, causes a system reset followed by a start at
address OOOOH, where a user program may have been
stored in RAM. If either switch is pressed upward, a
system reset is generated and latched until either switch is
pressed down. The indicator LED labeled RUN is lighted
during program execution and extinguished when an
IDLE instruction, a WAIT condition, or any malfunction
preventing normal fetching of instructions is encountered.
The use of a MSIM 40 and MSIM 40E constitutes the
only difference between the MS2000A and MS2000AE.
The MSIM 40 has a 120-volt UL-type plug while the
MSIM 40E has a 240-volt European-type plug. Power
supply electronics remain the same.
BASIC2 Interpreter CDP18S840V4. This high-level
language, more powerful than BASICI, is also designed
to facilitate rapid program development. Supplied on a
diskette, it features floating-point and integer numbers,
80 statements and functions, one- or two-dimensional
numerical arrays, one-dimensional string arrays, disk
1/0, and trace function for debugging. In addition it has
several enhanced features making use of the CDPI802
special capabilities including DMA capability, two-level
inputl output capability, statements to enable and disable
interrupts, interrupt routines in BASIC2, and machinelanguage subroutines.
732 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
MS2000A, MS2000AE
Specifications
System Components
20-slot Industrial Microboard Chassis
CDPISS60S Microboard Computer less memory
CDPISS632 Microboard Memory configured as 32kilobyte RAM
CDPISS62S Microboard Memory configured as 30kilobyte RAM plus 2-kilobyte ROM
CDPISS6S1 Microboard Disk Controller
MSIM SO Dual MicroFloppy Disk Drive Module
MSIM 40 Power Supply (MS2000) or MSIM 40E
(MS2000E)
UT70 Monitor Software, ROM-based (On
CDPISS62S)
CDPISSSI6 EIA RS232C Terminal Interface Cable
Dimensions
Height: S.76 inches (146 mm)
Width: 14.7 inches (373 mm)
Depth: 1O.0S inches (2S6 mm)
Weight: IS.S pounds (S.4 kilograms)
Power Supply and Controls
Plug-in Power Supply
Output:
+S Vat 3 A
+IS V at 1.6 A, 2-A peak
-IS Vat O.S A
Input:
90 to 132 V, 47 to 440 Hz (MS2000A)
ISO to 264 V, 47 to 440 Hz (MS2000AE)
Fuse: I A slow-blow, front-panel mounted
Controls:
Power on~off switch - front panel
RESET - RUN U switch
RESET - RUN P switch
Indicators:
RUN LED
+S V ON LED
Operating Temperature Range
S to 40 degrees C
Literature
Supplied with MS2000
MPM-24IPI- User Manual for "RCA
MicroDisk Development
System MS2000
MPM-20IC- User Manual for the RCA
CDPIS02 Microprocessor
MPM-201C(Supp.)-Instruction Set for RCA
CMOS Microprocessors
CDPIS04A, SA, 6A
MB-60SCDPISS60S Microboard
Computer
MB-62SRCA CMOS Microboard
Memories CDPISS628
MB-SOMSIM SO Dual
MicroFloppy Disk Drive
MB-40MSIM 40 Power Supplies
for RCA Industrial
Microboard Chassis Series
MB-6SICDPISS6S1 MicroFloppy
Disk Controller
PD45RCA MicroDisk Operating
System CDPISSS4S and
Monitor Program CDPISSUT70
MB-SRCA Microboard Industrial
Chassis Series
734 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
MSE31 01, MSE3102
MSE3101
32K CMOS Overlay Memory
(MicroEmulator Option)
MSE3102
64K CMOS Overlay Memory
(MicroEmulator Option)
These overlay memory modules are
plug-in modules for the MicroEmulator and are required for MicroEmulator users who intend to debug soft-
ware without a connected systemunder-test. These modules may be
mapped on an individual, indepen-
dent page basis anywhere within the
memory space of the target system.
200 ns CMOS RAMs are used.
MicroEmulator Spare Assemblies
Logic State Analyzer Module
MSE 3300
CDP18S524 Master Board Module - with software EPROMs
CDP18S525 1800-Series Header Pod Module - includes cables for connection to Personality Module and system under test.
CDP18S527 CRT Assembly
CDP18S528 Switching Power Supply Assembly
CDP18S529 Keyboard Module
CDP18S530 Ribbon Cables - Personality to Header
CDP18S531 Ribbon Cable - Keyboard to Master Board
CDP18S532 Ribbon Cable - Header to S.U.T.
MSE 3300 Logic State Analyzer Module (a)
and MSE 3102 64K CMOS Overlay Memory (b).
.CMOS Microprocessors, Memories and Peripherals
738
MSE3300
E C
N N
A T
0
A
- --0
R
MM
RW
DR
0
-A
T
S N Q
C
xxxx
xxxx
xxxx
xxxx
xx
xx
xx
xx
xx
xx
xx
xx
x
x
x
x
TRIGA
TRIGB
TRIGC
aUALIF
MODE
TRIGPT
START
LABREAK
DISABLED
ARM
NO
0
0
0
A+B+C
x
x
x
x
x
x
x
x
EEEE
10
I
N
T
WC
TL
R
E
W M
R A
P P 76543210
xx
xx
xx
xx
x
x
x
x
xx
xx
xx
xx
x
x
x
x
DO
FFFF
MM
4321
xxxx
xxxx
xxx x
xxxx
STATUS
TRIGGERED?
WHAT TRIGGERED?
SAMPLE COMPLETE?
-------x
x XXXXXXXX
x XXXXXXXX
x xxxxxxxx
x XXXXXXXX
NO
LOGIC ANALYZER HEX TRACE DISPLAY
- - - --F1- - - -- - --F2---- --F3--- - -- F4- -- - --F5--- ---F6- - - - - - F7- - - - ~'F8 -- --CHANGEBASE CLEAR
MODE
ARM
LABREAK TRIGPT TRIGGERA
ETC
Fig. 2 - Logic Analyzer Hex Trace Display.
Logic State Analyzer Description
Triggering
Refer to Figure 2.
The logic analyzer triggers (A, B, and C) are used to
determine when logging of data should commence or end.
The trigger point can be defined to be the beginning,
middle, or end of the storage buffer. The trigger field on
the screen includes the target CPU address, data bus, and
other relevant signals. These may be defined as true (I),
false (0), or "don't care" (X) by the user. The count
column (CNT) allows for repetitive occurrences of the
trigger event (from I to 15) before the trigger condition is
satisfied. For example, trigger A could be programmed to
require 5 "writes" to address 0000.
The ENABLE column defines the trigger condition for
A, B, or C as valid. For the qualifier, it specifies that the
stored samples must meet the condition shown. For example, the qualifier may be used to store "memory read"
cycles from a specific address. If the ENABLE bit is a
zero, all machine cycles will be logged regardless of the
specified qualifier condition.
The trigger MOQE provides for combining triggers A,
B, and C. The OR mode logically OR's triggers A, B, and
C. The AND mode requires all three triggers to be satisfied. Note that in AND mode all three triggers must be
enabled. If not, the logical AND condition can never be
satisfied. The SEQUENTL mode sets up the ordered
AND condition. Trigger A must be satisfied before the
hardware checks for trigger B, and trigger B must be met
before checking for C. Thus an ordered sequence of machine cycles can be programmed to trigger storage. Note
that in SEQUENTL mode triggers (A, B, or C) can be
disabled (ENABLE=O).
The SEQIMMED mode sets up the ordered AND
condition but requires the trigger conditions to be met on
successive machine cycles. Thus, a target system machine
cycle meeting trigger A condition must occur followed
immediately by a trigger B cycle and then a C cycle before
a valid trigger is produced. This provides for triggering on
"linked" op-codes. Note also that any of three triggers
may be disabled. (ENABLE=O). If only two successive
cycles are used to trigger, the user should set the conditions into the A, B pair or the B, C pair. If the A, C pair are
used (B ENABLE=O), a "don't care" machine cycle must
occur between the A trigger and the B trigger.
The ORAND mode logically OR's trigger A and B.
This result is then logically AND'ed with C to produce a
trigger.
Note that the "count" column (CNT) is valid for all
trigger modes except SEQIMMED. If programmed in
738 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
MSE3300
enable and trigger D as a disable. Thus the window mode
provides for timing an event within an event. For example, the target CPU can be timed as it executes a subroutine only called from a specific region of memory. Note
that in WINDOW mode, the ENA and TYP columns are
not present.
The AUTORETRIG and WINDOWRETRIG modes
behave like the AUTO and WINDOW modes respectively except that the timer will restart if a valid start
condition is again met.
The timer runs on a I megahertz clock and thus has a
minimum time resolution of plus or minus I microsecond.
The time display format is in scientific notation with the
form X.XXXEX seconds. The timer autoranges and
scales itself by 16 whenever a carry occurs from the lowest
16 bits of the counter. Thus, it counts from I to 65,535
times I microsecond, then times 16 microseconds, 256,
etc. Note, however, that the start/ stop resolution is still I
microsecond.
fashion, tracing states or timing cannot be performed
while in this mode.
The combinational features of the logic analyzer
triggers (OR, AND, SEQUENTL, etc.) are available for
use as breakpoints. The MODE display on the screen
(refer to Figure 4) shows the logical combination of all
eight breakpoints.
To select the BPEXTEND function, press the appropriate function key after pressing MODELA.
Unlike timer or trace operation, the breakpoint extension screen cannot be accessed while the target system is
running. If attempted, the error message "BPEXTEND
INVALID WHILE RUNNING" will be generated. This
is due to the fact that breakpoints 0-3 are available on this
screen, and these are incapable of being configured while
the target CPU is running.
Displaying Trace Data
Data in the trace buffer may be examined by pressing
the DATAL A function key. If the logic analyzer is in the
BPEXTEND or TIMER mode, the error message "NOT
IN TRACE MODE" will be generated if an attempt is
made to examine trace data. If still armed, the error
message "ARMED" will appear. Also, if the logic ana-
Breakpoint Extension Mode
The BPEXTEND mode expands the standard four
programmable breaks (BPO through BP3) to eight by
adding the logic analyzer triggers and qualifier to the
breakpoint screen. Since the triggers are dedicated in this
C
A
MM
0
N N
---0
-A
T
C
E
S N Q
EEEE
DO
I
FFFF
MM
4321
10
N
T
WC
TL
R
W M
E
R A
-------X
P P 76543210
R
RW
DR
BPO
0
XXXX
XX
XX
X
X
X
XXXX
XX
X
XX
X
X
XXXXXXXX
BP1
0
XXXX
XX
XX
X
X
X
XXXX
XX
X
XX
X
X
XXXXXXXX
A
T
BP2
0
XXXX
XX
XX
X
X
X
XXXX
XX
X
XX
X
X
XXXXXXXX
BP3
0
XXXX
XX
XX
X
X
X
XXXX
XX
X
XX
X
X
XXXXXXXX
BP4
0
XXXX
XX
XX
X
X
X
XXXX
XX
X
XX
X
X
XXXXXXXX
BP5
0
XXXX
XX
XX
X
X
X
XXXX
XX
X
XX
X
X
XXXXXXXX
BP6
0
XXXX
XX
XX
X
X
X
XXXX
XX
X
XX
X
X
XXXXXXXX
BP7
0
XXXX
XX
XX
X
X
X
XXXX
XX
X
XX
X
X
XXXXXXXX
EXTRNL
0
BREAKOUT
0
MODE
0+1+2+3+4+5+6+7
LOGIC ANALYZER HEX BREAKPOINT EXTENSION DISPLAY
GROUP 0
ACTIVE
------F1-- - - - ---F2- -- ---F3- --- ---·F4---------- F5---- ---F6----F7-- -"f8--CHANGEBASE CLEAR
MODE
. EXTERNAL
BREAKOUT
BPO
BP1
ETC
Fig. 4 - Logic Analyzer Hex Breakpoint Extension Display.
740 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
MSE3300
OENOTES
PIN I TYP
Fig. 6 - Layout Diagram of RCA MicroEmulator Logic State Analyzer MSE3300.
Parts List
C1 =1 OpF,±1 OOfo,200V
C2=39pF,±100f0,200V
C3-C7, C9-C58,C61-C63=OpF,±200f0,50V
C8,C59, C60=O.15I1F,±200f0,25V
R1~10Meg,l/4W,50f0
R2-R7,R9,R1 O~2K, V4W,50f0
N1 ,N2~Resistive Network 2K,1 O-pin
N5,N6~Resistive Network 10K, 1O-pin
N3,N4,N7,N8~Resistive Network 10K,6-pin
Y1 ~Crystal,4.000MHz
U1 ,U124~74HC10
U18~74H62
U22,U27,U38-U40~74LS54
U23~74LS175
U24,U109~74HCOO
U25,U26,U43, U 108,U7~ 74HC7 4
U33-U35,U66-U68,U92-U94~7 4LS 169
U11 ~74LS04
U53,U60~74HC374
U55,U54,U58,U59~74HC273
U61 ,U95-U1 07~74HC245
U57,U62,U65~74LS244
U2,U19,U20~74LSOO
U56,U112,U113,U115,U 116,U118-U121 ,U139-U148~74HC244
U3~7453
U63,U64~74LS374
U4~74LS20
U69,U70~74HC08
U5,U36,U37,U44-U52~74LS74
U6~74S32
U71 ,U72,U123~74HC138
U8,U41 ~74HC02
U76-U91 ~0692235
U9~74LS157
U1O~74LS151
U110~74HC32
U114,U117~74HC139
U21 ,U42,U122,U137,U111 ~74HC04
U12-U16,U28-U32~ 74LS 191
U125,U128,U131 ,U134~74HC30
U 126,U127,U 129,U 130,U 132,U 133,U 135,U 136~24 73399
U17,U91A~74HC27
U138,U149-U156~74HC373
U73,U74,U75~74HC157
742 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
MSE3300
ATeo
ATCl
ATe2
ATC3
SECU
TAO
TAl
TA2
TA'
TAA
TA,
TAS
TA7
:~~
Ai:A'i'CH
13
BLATCH
12
-
U4
B
VCC~'! ~:~
5
CA2
7
CA3
LABREAK-N
(PZ-52)
9
8
6
CA4
CAS
CA6
~-------,
10
CAT
A+B
,
~~4
6
Ne
rCB
4
'fCC
Vee
I
BVALIO
AVALiD
WINDOW
AENABLE
SEQI
I'rlF==t::--;:j:==~'-.J
CAO
CAl
CA2
CA'
BENABLE
IOO
IOI
I02
IO'
I04
I05
IOS
I07
CLEARLA
VCC
HC'
COUNT
TC
OUT5
10
RESET
CVALIO
CENABLE
QlO
Oll
Ol2
Ol,
Ol'
Ol,
OlS
Ol7
BPWINOOW
(P2-50)
CA.
CA.
CAO
CA7
!ooeETCEFS
14 HC4
5 01 LSI69 QO
D2 U66QI 13 He5
9
02 12 HC6
s
VCC
~
~
UfO
ClK
03
TC
"
HC7
VCC
Fig. 8 - RCA MicroEmulator Logic State Analyzer MSE3300 Logic Diagram Control Logic.
LAWRAP
744 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
MSE3300
,-if··""
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II E
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746 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
MSE3300
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TA'
748 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
MSE3300
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750 _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
752 - - - - - - - - - - - -__ CMOS Microprocessors, Memories and Peripherals
CDP18S826, CDPR582
COS MAC Microprocessor
Fixed-Point Binary Arithmetic Subroutines
MicroDisk CDP18S826V4
Cassette CDP18S826V2
Diskette CDP18S826
ROM CDPR582
The Binary Arithmetic Subroutine Package is a set
of 16-bit 2's-complement fixed-point arithmetic subroutines designed to be operated on COS MAC CDPI S02/ I S05 Microprocessor systems. The subroutines
are coded in Level I assembly language and require I
kilobyte of memory space. A detailed description of
these subroutines is given in the Manual Fixed-Point
Binary Arithmetic Subroutines for RCA COSMAC
Microprocessors, MPM-206A.
Utility Subroutines. A set of special utility subroutines
allows the user to save and restore a group of registers
on a stack or at a user-defined RA M area. These
registers are used by the arithmetic function subroutines
to store an operand and to point to an operand in
memory. Other utility subroutines compare 16-bit
operands and give indication if a register is greater than
or equal to an operand.
The subroutines are available on microdisk, floppy
diskette, cassette, and ROM. In source language, they
are available on microdisk CDPISSS26V4 for use with
the RCA MicroDisk Development System MS2000,
and on floppy diskette CDPISSS26 for use with the
CDPISS005, CDPISS007, and CDPISSOOS Development Systems. The subroutines are also available on a
magnetic-tape cassette, CDP I SSS26V2, for a Tl Silent
700 Data Terminal*. In object code, the package is
available in a single I-kilobyte ROM, CDPR5S2CD (4to 6.5-volt operation) or CDPR5S2D (4- to 1O.5-volt
operation). In addition to the binary arithmetic subroutines, the ROM contains the code for the Standard Call
and Return Technique. The ROM contains its own
address latch and is located in memory at hexadecimal
locations COOO through C3FF.
Functions
The Binary Arithmetic Subroutine Package includes
31 subroutines. Fifteen of these are binary arithmetic
subroutines, fourteen are utility subroutines, and two
are for format conversion. Appropriate selections from
the set of subroutines may be made for the calculations
required in a specific application.
Arithmetic Functions. The arithmetic functions included in this package are:
I. 16-bit 2's-complement addition
2. 16-bit 2's-complement subtraction
3. 16-bit 2's complement multiplication yielding
32-bit products
4. 32-bit 2's-complement division yielding 16-bit
quotient and remainder
Format Conversion. In addition to the arithmetic
functions, two format-conversion subroutines are
included for interfacing the system to binary-codeddecimal-oriented peripheral hardware. These subroutines provide BCD-to-binary and binary-to-BCD
conversions.
The Standard Call and Return Technique, described
in the User Manual for the CDP1802 COSMAC Microprocessor, MPM-201, is used for all the subroutines.
Timing
Timing measurements at a 6.4-MHz clock rate for
the best and worst cases of the various arithmetic and
format conversion subroutines for the CDPIS02 are
given in the tabulations at the right. These times were
determined by taking an ad hoc sample of large and
small numbers and performing an operation upon them.
Absolute best and worst case values may vary from the
values listed here.
Arithmetic
Function
Add
Subtract
Multiply
Divide
Best
(ms)
0.041
0.039
0.S51
1.37
Worst
(ms)
0.06S
O.07S
1.29
I.7S
Format
Best Worst
Conversion
(ms) (ms)
Binary to BCD 1.33
2.S2
BCD to Binary 0.094
O.SI
Literature
Further information on the Fixed-Point Binary
Arithmetic subroutines, including a complete listing for
all the subroutines, is given in the Manual Fixed-Point
Binary Arithmetic Subroutines for RCA COSMAC
Microprocessors. MPM-206A. General information on
the RCA ISOO microprocessor series, including software, programming techniques, and architecture, is
given in the User Manual for the CDP1802 COSMAC
Microprocesor, MPM-201.
Another arithmetic software package is described in
Product Description PD7 for the COS MAC FloatingPoint Arithmetic Subroutine Diskette CDPISSS27.
Additional information on the Floating-Point Package
is given in the Manual Floating-Point Arithmetic Subroutines for RCA COSMAC Microprocessors.
MPM-207.
*Registered trademark, Texas Instruments Corporation.
754 _ _ _ _- - - - - - -_ _ _ .CMOS Microprocessors, Memories and Peripherals
CDP18S834
BASIC1 High-Level Language
Compiler/Interpreter
The BASICl Compiler/Interpreter, provided on a
diskette, is a high-level language software package designed to simplify program development on the COSMAC DOS Develoment System (CDS III) CDP!8S007,
COS MAC Developoment System IV CDP!8S008, and
MicroDisk Development System MS2000. An excellent
language for the beginner, BASICI is easily learned
and facilitates the rapid development of elementary
application programs. A feature of BASIC! is that it
can form the core of a system whose facilities, limited
only by the system memory, may be extended indefinitely
by the addition of machine language routines.
The Compiler/Interpreter gives the user the option of
(I) developing and running programs in BASICI directly,
or (2) converting these programs to executable object
code capable of running at a greater speed.
The interpreter allows the user to write programs in
BASIC I with line numbers for later execution or without
line numbers for immediate execution. The disk-related
statements incorporated in the interpreter allow the
programmer to save programs on a floppy disk for later
recall.
The compiler enables the programmer to take any
stored program written in BASIC) and translate it into
assembly language, giving the user the flexibility of
specifying where in memory the program, variables, and
stack are to reside. The output of the compiler is
assembled by the COS MAC assembler (ASM8) to
produce the executable object code. Programs compiled
and assembled run at speeds much greater than those run
directly through the interpreter.
Features
The BASIC) Compiler/Interpreter can handle lines of
up to 77 characters in length. Line numbers can range
from I to 32767. Multiple statements per line are
accepted. Numbers can be entered in decimal (-32767 to
+32767) or hexadecimal (#0000 to #FFFF). Variables are
designated by any single capital letter.
BASICl performs fixed-point arithmetic. Expressions
are composed of one or more numbers, variables, and/ or
functions joined together by operators(+, -, /, *,@)and
possibly grouped by parentheses. Expressions are
evaluated modulo 218.
The functions BASICl has in its repertoire include
MOD, AND, OR, XOR, MAX, MIN, SGN, ABS, HEX,
RND, INP and USR. The USR function is important in
that it allows the user to extend the features of BASIC 1 by
means of machine language subroutines and allows for
the exchange of data between the assembly language
subroutines and the BASIC) program. BASICI also
allows direct CDPI802 input and output port control
within the language itself. This control is accomplished by
the INP (port) function and the OUTPUT (port)
statement.
The types of statements available to the programmer
include the following:
Comments and Declarations: REM, ,
Assignment: LET
Control: GOTO, GOSUB, RETURN, END
Conditional: IF
Input/Output: INPUT, PRINT, OUTPUT,
Disk Related: WFLN, RFLN, DOUT, DIN,
CLOSE, WEOF, TIN, TOUT,
NOUT
System Control: NEW, RUN, LIST, RDOS
Loading and Operating BASIC1
Loading and operating BASIC) on a COS MAC
Development System is a simple procedure. To load
the interpreter, the user places the disk in one of the
disk drives and types BASICl.INT:X where X is the
drive (0 or I) the disk has been placed in. This command loads the interpreter. The program initializes
itself and then delivers its colon prompt ":" to indicate
it is now in the enter mode and the user can begin
entering a BASICI program.
To load the compiler, the user places the disk in one of
the disk drives and types BASICI.CMP:X, where X is the
drive (0 or !) the disk has been placed in. This command
loads the compiler and beings execution. The compiler
then issues its normal user prompts.
Error Messages and Program
Debugging
Whenever the BASICl interpreter detects an error in a
statement, it generates an error message consisting of an
exclamation point "'" followed by a decimal number. The
number signifies the type of error. If an error is detected
during program execution, the line· number of the
offending statement is also given. BASIC) lends itself to
the use of dummy stop or print statements to reveal
whether the flow within the program is proper or to
permit the examination of variables at convenient points
during program execution.
756 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP18S835
VIS Interpreter
The VIS Interpreter, on microdisk CDP18S835V4,
floppy diskette CDP18S835, and cassette tape
CDP18S835V2, is an interpretive language developed
specifically to support the CDPI869 and CDPI8701
CDPI876 Video Interface System (VIS). The interpretive
commands allow the user to control the VIS to provide
displays of text, graphics, and motion on a cathode-ray
tube screen in black and white or color. The Interpreter
is useful on any system containing the VIS chip set and
is particularly supportive of the CDP18S661, Microboard Video-Audio-Keyboard Interface.
The VIS Interpreter is open ended, allowing the user to
add interpretive commands for special purposes. By use
of the supplied source, routines that are not required for
the particular application may be deleted. The source
routines may also be adapted to the user's own program
and are documented to provide a guide to the programming of the VIS .. The Interpreter as delivered is a 3kilobyte program and requires a minimum of 64 bytes of
RAM.
The source file for the VIS Interpreter is provided on
microdisk compatible with the Micro-Disk Development System MS2000 or floppy diskette compatible
with the CDPI8S008 Development System (CDOS
Operating System). It is capable of both NTSC and
PAL operation. The CDPI8S835V2 is intended for use
with the CDPI8S694 and CDPI8S695 Microboard
Computer Development Systems.
Structure
The VIS Interpreter is based on:
I. Sixteen general-purpose, eight-bit variables.
2. An eight-bit accumulator and overflow flag.
3. A page memory pointer.
4. A character memory pointer.
5. A main memory pointer.
6. A hitflag.
Variables. The sixteen eight-bit variables are usable for
general data storage. They are also usable as objects of
arithmetic and logical operations. This use includes operations involving two variables or one variable with the
accumulator (ACC). The variables are also used to contain control information for some interpretive instructions. Additional data storage may be accomplished by
the use of instructions that allow direct storage and load
from memory. Instructions are provided to test the content of the variables including comparisons against constants, ACC, and other variables.
Accumulator (ACC). A single eight-bit accumulator is
provided in the interpreter. This accumulator is used asan
operand and to store the result in arithmetic and logical
operations. Instructions are provided to display the contents of the ACC by copying it to the page memory in two
methods. In the first method, the contents of the ACC are
placed in the page memory unchanged except the most
significant bit is set equal to one. In the second method,
the contents are taken and treated as two hexadecimal
digits and the two ASCII codes for the digits are placed in
page memory. Transfers to and from main memory, the
variables, and the page memory are supported.
Overflow Flag. A flag is provided to indicate overflow
on all arithmetic operations. After addition, the flag is a
one if a carry occurs and a zero if no carry occurs. After
subtraction, the flag is a one if no borrow occurs and a
zero if a borrow occurs. Instructions for testing the value
of the flag are provided.
Page Memory Pointer (PMP). The Interpreter references the page memory by means of the page memory
pointer (PMP). The PMP is a sixteen-bit memory pointer
into the page memory. The value of the PMP normally
ranges from FCOOH to FCEFH for half resolution and
FCOOH to FFBFH for full resolution. (H indicates hexadecimal notation.) The PM P is initialized to FCOOH and
the initial home address is zero, which results in the PMP
pointing to the upper left screen location. The PMP may
be directly accessed or loaded by use of interpretive
instructions.
Character Memory Pointer (CMP). The Interpreter
references the character memory by means of the character memory pointer (CMP). The CMP is an eight-bit
pointer into the character memory. In order to reference a
given character, the CMP must be loaded with the same
value that, if stored in page memory, would display the
character: Instructions are provided for the transfer of the
CMP to and from the ACC and variables, along with
increment and decrement instructions. No checks are
made or limits placed on the value of the CM P, and thus it
may be used in systems that allow up to 256 characters.
Main Memory Pointer (MMP). The Interpreter allows
direct references to memory by means of the main memory pointer (M MP). The M M P is a sixteen-bit pointer into
the system memory. Instructions are provided to load,
save, and decrement its value. All Interpreter instructions
that involve direct memory reference use the MMP. Instructions are provided to store and load the variables,
ACC, and other pointers by means of the MMP. No
checks are provided on the value of the MMP.
Hitflag. The Interpreter provides instructions that
allow the user to display characters on the screen and to
move these characters. In order to check for "colliding"
objects, the interpreter maintains a hitflag. This hitflag is
set true if any write to page memory or character memory
is addressed to a non-zero location. The hitflag is cleared
when an interpreter instruction performs a write to page
or character memory locations that are zero. Instructions
are provided to test the hitflag.
Instructions. The Interpreter is provided with 109
instructions.
Literature
Further information on the VIS Interpreter is provided
in the manual VIS InterpreterCDPI8S835 User Manual,
MPM-835A. Information on the Video Interface System
(VIS) CDPI869 and CDPI870/CDPI876 is available in
data sheet file number 1197.
758 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP18S839
EXPRESSIONS - permit the following operations:
arithmetic +, -, • ,/, MOD
10gkaIAND,OR,XOR,NOT
equality and ordering =, <>, <,>,
<=, >=,
Statement Description:
ASSIGNMENT - allows replacement of variable's
value by evaluation of an expression; mUltiple assignments are
possible in one statement.
IF .. THEN .. ELSE - allows execution of a group of
statements based on a condition.
IF statements may be nested.
DO .. END - allows execution of a group of
statements.
ITERATIVE DO - allows looping based on an
interative variable whose increment is controllable with an
optional BY clause.
DO .. WHILE - allows looping based on a condition.
PROCEDURE - contains executable instructions
and local variable declarations.
Procedures may be recursive if
declared with REENTRANT
attribute. Procedures may take
on function attribute.
CALL - subroutine invocation.
GO TO, GOTO - branching capability to labels
within scope rules of the language.
Compiler Features:
In-line assembly code capability
Output listing controls
Assembly code output
The error messages indicate the nature of the error, the
number of the line in which the error occurred, and where
in the line the error was detected.
A program development cycle using the PLM-1800
High-Level-Language Compiler is given in Fig. I. The
Compiler accepts source code written in the PLM
language, and generates the equivalent assembly code
that can subsequently be assembled into CDPI802
executable code.
Sample Program
A sample program using PLM is given in Fig. 2. This
program will sort an array by means of a method called
"bu bblesort."
DO;
I'THIS IS A BUBBLESORT PROGRAM'!
DECLARE A(10) ADDRESS INITIAL
(33, 10,99,60, 162,3,3,272,98,2);
DECLARE (I, SWITCHED,J) BYTE, TEMP ADDRESS;
SWITCHED = 1;
DO WHILE SWITCHED = 1;
SWITCHED = 0;
DO 1= 1 TO 9;
J = 1+ 1;
IF A(I) > A(J) THEN
DO;
SWITCHED = 1;
TEMP = A(I);
A(I) = A(J);
A(J) = TEMP;
END;
END;
END;I'OF WHILE'!
END;
I'NOW COMPLETED SCAN WITHOUT SWITCHING'!
EOF
Fig. 2 - PLM "bubb/esort" program.
Operating with PLM
Literature
After a program is generated in the PLM language, the
first step for using the Compiler is to place the PLM
diskette in disk drive O. The user then invokes compilation
of the file by typing
PLM fname.extx
where fname.ext is the user's file name and x is the drive.
If errors occur during compilation, they are transmitted
to the development system terminal device as well as to an
output file of PLM source code interlisted with CDPl802
assembly code. Another output file equating assembly
names and 'PLM names is also generated by the Compiler.
Further information on the PLM-1800 High-LevelLanguage Compiler CDPl8S839 is given in the User
Manual for the RCA COSMAC PLM-1800 High-LevelLanguage Compiler, MPM-239.
Information on the MicroDisk Development System
MS2000 can be found in the User Manual for the RCA
Micro Disk Development System MS2000, MPM-241.
Information on the RCA COSMAC Development
System IV CDPI8S008Vl, CDP18S008V3, CDPl8S008V5, and CDPl8S008V7 is given in two manuals
Operator Manual for the RCA COSMAC Development
760 ______________ CMOS Microprocessors, Memories and Peripherals
CDP18S840
BASIC2
High-Level Language Interpreter
The BASIC2 Interpreter CDP18S840 is a high-levellanguage software package on diskette designed to
simplify program development on COSMAC Development System IV (CDPI8S008Vl and V3) and the
MicroDisk Development System MS2000. With additional RAM it may also be used with COSMAC DOS
Development System III (CDPI8S007Vl and V3).
BASIC2 is a high-level interactive language that is easily
learned and readily used by beginning programmers.
BASIC3, a tape-based counterpart to BASIC2, is provided with the Microboard Computer Development
System MCDS (CDP18S693 and CDPI8S694).
A special Run-time BASIC, the CDP18S842, is available on ROM for use in custom applications not
Fequiring disk I/O. With Run-time BASIC the user
obtains a 4-kilobyte savings in the memory required.
Run-time BASIC provides an excellent way to generate
software quickly in a high-level language for use in any
Microboard system. The system can be configured to
suite the application. The software for the application is
generated by the user in a development system (MicroDisk MS2000, COSMAC Development System III or
IV using BASIC2, or the Microboard Computer Development System MCDS using BASIC3) and installed in
memory (RAM or ROM). Then with Run-time BASIC in
the system, execution of the user program Cdn begin
immediately.
BASIC2 provides full access to the CDPl802 I/O
constructs including two-level I/O, interrupt, DMA,
external flags, and the Q·output. It allows calls to user
machine-language routines and provides I/O instructions
for any added Microboards.
Description
The BASIC2 Interpreter features over seventy statements and functions including both transcendental and
string functions. It provides both immediate and program
modes of operation. It features one- or two-dimensional
numerical arrays up to a maximum size of 255 x 255 and
one-dimensional string arrays up to 255. It has direct
memory access capability and can handle two-level input
and output statements. For programming ease, it also has
line-editing capability.
The statements and functions available on BASIC2 are
shown in Table I.
Arithmetic Capabilities
BASIC2 is capable of handling both integer and
floating-point numbers. Both types are stored as 32-bit
signed numbers. In the case of floating-point numbers,
Features
•
•
•
•
•
•
•
•
Floating-Point and Integer Numbers
Line-Editing Capability
More than 70 Statements and Functions
One- or Two-Dimensional Numerical Arrays
Disk I/O
Trace Function for Debugging
Memory-Saving ROM Version for Turnkey
Applications
Uses CDP1802 Microprocessor Constructs
Enhanced Features Using CDP1802 Special Capabilities
•
•
•
•
•
•
•
•
DMA Capability
Two-Level Input/Output Capability
BASIC Statements to Enable and Disable Interrupts
Vectored Interrupts and Interrupt-Handling Routines
in BASIC
Flag and Q Status Commands
Set Q Statement
Machine Language Subroutines
Easy Multi-Station Operation
eight bits define the exponents and 24 bits the mantissa.
The range of numbers is:
Integer: -2147483648 to +2147483647
Floating point: -.17E38 to +.17E38
Integer numbers are accurate over the entire range, but
floating-point numbers are accurate to approximately six
mantissa digits, although up to nine digits are allowed on
data entry. Two- or four-digit hexadecimal numbers can
also be entered directly.
Memory Requirements
BASIC2 requires a development system that is equipped
with the COSMAC Disk Operating System (CDOS or
MicroDOS) and with an additional 16 kilobytes of
memory for the BASIC2 Interpreter. The interpreter is
loaded into the 16-kilobyte block of memory that is above
the block used by CDOS; that is, COOOH through FFFFH
(H indicates hexadecimal notation). The memory can be
either RAM or ROM. The interpreter requires additional
RAM in low memory beginning at OOOOH. The amount of
RAM available in low memory controls the size of the
programs that may be written. The locations OOOOH
through 040FH are used as work space by the interpreter.
When the system is first initialized, the interpreter begins a
762 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP18S840
When the interpreter is used, a program is created by
the writing of one or more statements, separated by a
colon, on a line and assigning the line a number. While the
interpreter is being used, the lines of code can be easily
modified by use of the EDIT command statement. The
BASIC2 interpreter allows the lines to be entered in any
order, but for execution it will automatically rearrange
them in numerical sequence. For example, line 10 may be
entered before line 5, but in execution line 5 will be
executed first. This facility enables the programmer to
leave unused numbers between lines so that additional
lines can be inserted at a later time. The interpreter always
executes the lines in numerical order starting with the
lowest line number, thus providing one method of editing
a program.
The second method of creating and entering programs is
by use of the CDOS or MicroDOS editor. This method is
described in detail in the manuals for the CDP18S007,
CDP18S008, and MS2000 Development Systems.
Error Messages and Program
Debugging
Whenever the BASIC2 interpreter detects an error in a
statement, it generates an error message consisting of
ERR CODE and a two-digit decimal number followed by
the message READY and the: prompt symbol. A listing
of the error numbers and their corresponding meanings is
provided in the BASIC2 instruction manual. If the error
is detected during program execution, the error code is
followed by the words AT LINE followed by the line
number of the offending statement.
The TRACE command statement is a useful tool for
debugging because it allows the user to follow the flow of
the program.
Literature
Further information on the BASIC2 Interpreter and on
Run-Time BASIC is given in the Manual BASIC2 HighLevel-Language Interpreter CDP18S840 User Manual,
MPM-840A.
Information on the RCA COSMAC DOS Development
System CDPI8S007VI and V3 is given in the Operator
Manual for the RCA COSMAC DOS Development
System (CDS III) CDP18S007, MPM-232, and in the
Hardware Reference Manual for the RCA COSMAC
DOS Development System (CDS III) CDP18S007,
MPM-233.
Information on the RCA COS MAC Development
System IV CDPI8S008V I and V3 is given in the Operator
Manual for the RCA COSMAC Development System IV
CDP18S008, MPM-235, and in the Hardware Reference
Manual for the RCA COSMAC Development System IV
CDP18S008. MPM-236.
Information on the MicroDisk Development System
MS2000 can be obtained in the User Manual for the RCA
MicroDisk Development System MS2000, MPM-241.
764 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP185842
HEXADECIMAL
ADDRESS
0000
INTERPRETER
2FFF
3000
USER PROGRAM
7FFF
8000
USER PROGRAM
OR
UTILITY
8FFF
9000
GENERATED DATA
VARIABLES
STRINGS & ARRAYS
-----STACK
FFFF
92CS - 34606
Fig. 1 - Typical memory configuration for
Run-time BASIC.
766 _ _ _ _ _ _ _ _'----_ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP18S844, CDP18S852, CDP18S853
Micro Concurrent Pascal
Cross-Compiler CDP18S844 and
Interpreter/Kernel CDP18S852 and CDP18S853
Micro Concurrent Pascal (mCP)·, a Pascal dialect,
is a high-level language having multi-task capability
that is specially suited for program development not
only for COS MAC Development Systems or other
systems using the RCA 1800 microprocessor series,
but also for many other 8-and 16-bit microprocessors.
Pascal is a language that is easily written, read, and
maintained. mCP has the additional feature that it
enables the programmer to solve problems requiring
concurrency. R.CA Micro Concurrent Pascal, available on either tape or disk media, includes a crosscompiler CDP 18S844 and a target system
interpreter/kernel CD·P18S852 for 8-bit microprocessor systems and CDPl8S853 for 16-bit systems. In
addition to providing the capabilities of mCP, this
package gives the programmer access to the unique
features of the RCA 1800-series microprocessors.
The Language
The mCP language provides the user with a Pascal
extension that offers the readability, maintainability,
and control structures of standard sequential languages plus the flexible data typing of Pascal. Most
significantly, however, it offers process and monitor constructs that permit mUltiple processes to run
independently but at the same time to share data and
communicate with each other. Interrupt response
routines, device drivers, and bit-level manipulations
are all programmed in mCP without having to use
assembly code. But, for those time-critical routines,
resort to assembly code is provided in the language.
Interrupts are programmable in the mCP language
through specification of an interrupt table. This table
orders the priority of the interrupts and allows proper
association of the interrupts with the group number
and external flags of the RCA 1800-series two-level
I/O convention. In addition to static specification,
interrupt priorities may be dynamically altered by
means of a single mCP instruction ..
RCA 1800 series microprocessor features are directly accessible by means of built-in routines. The
mCP programmer may access the external flags, the
DMA pointer, and the Q flag. In addition, the mCP
input and output instructions (INN and OUT) may be
"Micro Concurrent Pascal and mCP are registered
tradenames of Enertec, Inc.
coded for either one-level or two-level 1/ O. Fig. I is an
example of an mCP program fragnient that transmits a
line of characters to the CDPI8S641 Microboard
UART Interface.
Features of the mCP language include:
1. Pascal syntax with language constructs for
concurrency.
2. RCA 1800-series-dependent routines allow the
programmer to test external flags, set and test
the DMA register, test and set the Q flag, and
perform one- or two-level I/O.
3. Ability to specify and dynamically alter interrupt priorities for RCA 1800-series microprocessor interpreter/kernels.
4. Floating-point arithmetic.
5. Bit-level manipulation intrinsics.
6. Ability to use assembly language.
7. Structured data types.
8. Data typing flexibility.
9. Separate data types for 8- and 16-bit integers
for efficient data storage.
10. String manipulation intrinsics.
11. Hexadecimal constants.
12. Direct hardware addressing (PEEK, POKE,
INN, OUT).
The Cross-Compiler
CDP18S844
The mCP package is implemented by a crosscompiler and an interpreter / kernel. The cross-compiler creates mCP pseudo code (mCP p code) which
may then be executed by the interpreter with the kernel
acting as the program executive performing process
switching, process synchronization, and interrupt
vectoring. The compiler is free from any target
machine dependencies.
The mCP compiler performs extensive compile-time
checking, capturing many real-time errors. It offers
many compile-time directives such as listing and
output code options to ease development and debugging of programs.
The code produced is position-independent, reentrant, and ROMable. An INCLUDE directive
allows merging of mCP source files at compile time.
mCP cross-compilers are available for Hewlett-Packard, DEC, Data General, and IBM mainframes.
768 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP18S844, CDP18S852, CDP18S853
mCP Compared with
Sequential Pascal
mCP has been extended from sequential Pascal in
constructs to support concurrency, microprocessor
input/ output, and interrupt handling. To iinprove the
efficiency of the mCP Compiler, some features of
sequential Pascal were deleted. These deletions are
dynamic storage, file types, and the GOTO statement.
Because predefined functions and procedures in mCP
are tailored for concurrency, bit handling, and access
to machine features, some functions and procedures
are different from the ones found in sequential Pascal.
Many, however, are the same.
Literature
A Micro Concurrent Pascal (mCP) User's Guide is
supplied with every purchase of mCP. This manual
contains twelve chapters which include syntax and
semantics of mCP, operating instructions for
compilation, description of the mCP interpreter /
kernel, debugging hints, examples of mCP programs,
and interpreter/kernel details particular to the target
system.
A useful reference is the booil. fhe Architecture of
Concurrent Programs by Per Brinch Hansen,
Prentice-Hall, Englewood Cliffs, 1977. This book
describes the construction of operating systems using
the Concurrent Pascal language with which mCP
shares the process, monitor, and class constructs.
TYPE UART_WRITE=DEVICE...MON (SELECTOR: INT);
PROCEDURE ENTRY WRITE(MESSAGE: LINE; DISP: LINE-DISP);
VAR I: INT;
THROWAWAY: INTEGER;
BEGIN
1:=1;
OUT(#BD, CTRLWORD) (·XMIT REO., INT. EN., 8 DATA, 2 STOP, NO PARITY·);
DOlO;
WHILE (MESSAGE[I) <> NUL) AND (I < LlNELENGTH) DO
BEGIN
OUT( ORD(MESSAGE[I)), DATA-WORD);
(·SEND A CHARACTER·)
DOlO;
INC(I);
END;
IF (DISP=PROMPT) OR (DISP=NEWLlNE) THEN
BEGIN OUT(ORD(CR), DATA-WORD); DOlO;
OUT(ORD(LF), DATA-WORD); DOlO;
END;
IF DISP=PROMPT THEN
BEGIN OUT(ORD('>'), DATA-WORD); DOlO; END;
OUT(#3D, CTRLWORD); (·TRANSMIT INHIBIT OTHERWISE SAME AS ABOVE·)
THROWAWAY:=INN(CTRL_WORD);
END;
BEGIN
OUT(#3D, CTRL_WORD);
END;
Fig. 1 - Sample mCP program. This routine writes a line to
the CDP18S641 Microboard UART Interface.
770 _________-----CMOS Microprocessors, Memories and Peripherals
CDP18S844, CDP18S852, CDP18S853
300n
,--'W'v-----,""!5
ElA
DATA
FROM -3
MODEM
300.0.
CLEAR TO
SEND
VErA o-T-"'-3\100"'n::-,r<6~~1AD~ET
'-'V\I\"---,< 8 g~RR IER
VGG
I
REQUEST
I
·300n
TOSEND 4 ~ VElA
G~~~~~7>-TI--------------------+------------~--------------------+<7~W~t~D
lR~t~6
ItRRtU't~
I
t2CI.-34082
DL9,t~
TARGET CI
SYSTEM,
0
u,
MODEM
51
(TYPICAL LAYOUT)
Fig. 2 • Download switchbox circuit.
INTEGRATED CIRCUIT
SN75154 !IA LINE RECEIVEFI
u.
aN15UI IIA LINe: DRIVE III
U:J, U4
MCA230 (OPT(') ISOU,TOA)
772 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP18S845
MicroDOS Operating System
The Microboard Disk Operating System (Micro DOS)
associated with the MicroDisk Development System
MS2000 is a powerful and easy-to-use tool for software
development. It is an interactive mass-memory storage
system capable of dynamic file operation and management. Its commands, obtained from a system console or
diskfile, reference files stored on the diskette. By means
of its dynamic operating system, MicroDOS keeps track
of changes in file size during software development and
allocates disk space as needed. Disk space not needed by
a file is freed and made available for use by a different
file. The file operating system can have multiple input
and output files open at the same time and can thereby
provide the user with considerable design flexibility.
MicroDOS supports two types of files; ASCII and
binary. ASCII files contain only ASCII files such as
assembly source or listing files. Binary files require half
the space for storage and can be loaded twice as fast.
Files may be defined as system, write protected, delete
protected, and/or contiguous. A prime function of
MicroDOS is to manage the resources of the development system so that the user does not have to. The
devices handled by the operating system include: keyboard, line printer, and CRT screen. The operating system also provides a set of functions that can be called by
a user program to perform utility operations such as
open files, close files, and the like.
MicroDOS System Ingredients
Use of the MicroBoard Disk Operating System
(MicroDOS) requires a MicroDisk Development System
MS2000. The software needed for MicroDOS operation
includes the UT70 Utility Program, provided on ROM,
and the programs provided on the MicroDOS System
Diskette. These programs include.
On Disk:
I. MicroDOS Operating System (OP. SYS)
2. MicroDOS System Commands (CDSBIN,
COPY, DEL, DIR, FREE, MERGE, PRINT,
RENAME, SYSGEN, U, VERIFY)
3. MicroDOS Macro Disk Assembler (ASM8)
4. MicroDOS Disk Editor (EDIT)
5. Memory Save Program (MEM)
6. Diskette File Examination and Modify Program
(EXAM)
7. Diskette Diagnostic Program (DIAG)
8. ASM4 to ASM8 Source Conversion Utility
(CONASM)
9. Pertec to or from MicroDisk Transfer Utility
(PERTEC)
10. Cassette to or from MicroDisk Transfer Utility
(TAPED)
II. Memory Test Utility (MEMTST)
12. Diskette Format Utility (FORMAT)
13. Instructions for MicroDOS (HELP)
14. Twelve User Functions
On ROM (UT70)
1. Disk Loader
2. I/O Transfer Routines (READ, WRITE)
3. UT70 Self-Test Routine
Detailed information on the MicroDOS operating
system and the MS2000 development system can be
found in the User Manual for the RCA MicroDisk
Development System, MPM-241.
774 _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
CDP18SUT62, CDP18SUT63, CDP18SUT71
Utility Firmware
The CDPI8SUT62, CDPI8SUT63, and CDPI8SUT71
are Utility Programs each provided on a 2716 EPROM
for use with RCA Microboard Computer Systems. The
CDPI8SUT62 is designed for use with the CDP18S601,
CDP18S603, CDP18S606, or CDPI8S608 Microboards.
The CDPI8SUT63 will run with any RCA CPU Microboard provided that the CDPI8S661B VIS board is also
in the system. CDPI8SUT71 runs with any CPU Microboard which includes a UART, or with any of the other
CPU boards, provided the CDPI8S641 board is also in
the system.
The Utility Program on the CDPI8SUT62 and
CDPI8SUT63 allows the user to:
I. Inspect and modify memory.
2. Store and retrieve data on tape.
3. Start execution of the BASIC3 Interpreter, the
Editor, the Assembler or a user-generated program at
any address.
4. Debug programs.
The twelve commands available on the CDP 18SUT62
and CDPI8SUT63 are Memory Move, Memory Fill,
Memory Substitute, Memory Display, Memory Insert,
Program Run, Read Tape, Write Tape, Rewind Tape,
Run BASIC, Run Editor, and Run Assembler. Also
included are Read and Type routines for communications between the systems and the data terminal and for
I/O transfers.
The CDPI8SUT71 enables the user to examine or
alter memory, begin program execution at a given location, do I/O from the keyboard, or transfer data
between disk and memory. In addition, it can set up
half- or full-duplex operation, load the operating system, or perform a test on itself. These functions are
accomplished through a series of monitor commands
that are initiated by typing D, F, I, M, S, P, T, L, B, ?,
!, R, or W. The functions include memory display (D),
memory fill (F), memory insert (I), memory move (M),
memory substitute (S), run program (P), self test (T),
load operating system (L or B), do I/O from keyboard (?
or !), and disk read (R) or write (W). Also included are
the standard read and type routines that provide communication with the user's terminal. Finally, the monitor contains routines that communicate with the RCA
MSIM 503'/2 inch micro floppy disk drives through the
CDPl8S651 disk controller.
776 ________________________
CMOS Microprocessors, Memories and Peripherals
Dual-In-Line Packages
Dual·ln·Llne Pla.tlc Packag..
18·Le.d (E & F)
(JEDEC MO·001·AC)
E SUFFIX
A
AI
INCHES
MIN .. MAX.
0.156 0.200
0.020 0.050
8
8,
0.014
0.035
0.020
0.086
C
0.008
0.746
0.300
0.240
0.012
0.785
0.326
0.260
SYMBOL
0
E
E,
ts·Le.d
NOTE
,
'I
O.looTP
2
'A
L
L2
0.300 TP
2.3
•N
0.126
0.000
16°
16
a
N,
0.356
0.89
0.608
1.66
0.204
18.93
7.62
6.10
0.304
19.93
8.25
6.60
4
5
6
SYMBOL
8
8,
C
0
E
0"
1
2
2.3
0.300 TP
0..125 0.150
0'
15'
16
0
0.015 10.060
.
L
N
N,
3.81
0.76
NOTE
MAX.
0.200
0.050
0.020
0.065
0.012
0.885
0.260
0,100 TP
'I
'A
7.62 TP
INCHES
MIN.
0.155
0.020
0.014
0.035
0.008
0.845
0.240
A
AI
2.64 TP
3.18
0.000
0.160
0.030
0"
MILLIMETERS
MAX.
MIN.
5.08
3.94
0.61
1.27
S
MILLIMETERS
MIN.
3.94
0.508
0.356
0.89
0.204
21.47
6.10
2.54 TP
7.62 TP
3.81
0'
15'
18
0
0.39
1.52
3,18
4
5
6
15°
92CS-30630
16
a
°1
0.040
0.075
1.02
1.90
S
0.Q15
0.080
0.39
1.62
92CM-15967R4
20·Le.d
INCHES
SYMBO
AI
A2
B
S,
C
a
02
E
E,
'I
'A
's
NOTES:
1. Rlllr 10 JEOEC Publicilion No. 85 JEDEC RlgIIlirod Ind 811ndlrd Oulllnli lor Solid stl" Producll,
MILLIMETERS
NOTE
MIN.
A
-
0.010
0.115
0.014
0.045
0.008
0.925
0.005
D.300
MAX.
0.210
10
-
10
0.195
0.022
0.070
0.015
1.040
-
0.325
0.240
0.280
0.090
0.110
0.300 TP
-
L
N
0.115
S
-
I
I
3
4
5
8
7,8
9
10
0.410
0.150
11
10
-
12
13
20
I
MIN.
MAX.
5.33
0.254
2.93
0.358
1.15
0.204
23.49
0.13
7.82
8.10
2.29
7.82
2.93
-
-
4.95
0.558
1.77
0.381
28.42
-
8.25
7.11
2.78
TP
110.41
3.91
20
-
92CM-35138
tor rul ... nd g.n.r.lln'arm.tla" concerning regl ...
t.r.d .nd .I.nd.rd autlln...
2. Prolrullonl (1IIIh) on Ihl bl.. pllnl lurtlCI Ihlli
nolllcNd ,25 mm (,010 In.),
3. The dlm,nllon .hown I. 'or 'uille.d •• "Hilt" I•• da
Ire opllonllII Illd pOllllonll,
N,~, ~ +1.
4. Dlm,n.lon D do •• not Includ. mold fll.h or
protrualona. Mold tI.ah or protrullonl ah.1I not
",clld .25 mm (.010 In.).
5. Thll dlmlnllon II conirolling whln I plrtlcullr
comblnilion 0' body Ilnglh, Illd wldlh Ind Itld
,plclng dlm,nalona would .lIow I,.d m.t,rl.1 to
o."hlng Ihl ond. 01 Ihl plcklgl.
8. E I.,hl dlmlnllon lolhl ouilidl 01 IhllOidl Ind II
mlilurod wllh Ihl Illdl porpondlcullr 10 Ihl bl..
pl.n, (zero I"d .p ....d).
7. Dlmonllon Ei dOli nol Includl mold tllih or
protrullonl.
MAX.
5.08
1.27
0.508
1.65
0.304
22.47
6.60
8. Plcklgl body Ind Illdl Ihlli bl Iymmilriciliround
c.nl.r line .hown In end view within .25 mm (.010
In.).
I. Llld Iplclng " Ihlli bl non-cumulilive Ind Ihlli
b. me.lured.t th.lled tip. Thl. ml.lur.m.nt .hln
bl mid. b.fore In'lrtlo" Into gIUI", baird. or
locket•.
10. Thl. I. I b.lle In,t.lI.d dlm,nllon. M,.aurem,nt
Ihlli bl midI wllh Ihl dlYlcllnllllild In lho ..lling
pllnl glugl (J!DEC Oulllnl No. GlS-3, ..llIng
pllnl gIUgl). LI.dl .hlli blln lrul polillon wtlhln
.25 mm (.010 In.) dllmll" lor dlmlnllon IA.
11. I. Illhl dlmlnllon 10 Iho OUllldl 01 IhlItldl Ind II
mlilurod II Ihl Illd IIpl blloro Iho dlylCI II
Inlllilld. Nlgilive Illd Iprud II nol permlttld.
12. N 11th, mlxlmum number of I,.d pOllliona.
13. Dlmlnllon 8 Illhl 1111 Ind 01 Ihl plcklgl mUll
IquII dlmonolon 8 Illhl rlghl Ind 01 Ihl pI.klgl
within .78 mm (.030 In.).
778 _____________ CMOS Microprocessors, Memories and Peripherals
Dual-In-Line Packages
Dual-In-Llne SIde-Brazed CeramIc Packages
D SUFFIX
16-Lead
18-Lead
INCHES
MILLIMETERS
SYMBOL
NOTE
MIN. MAX.
MIN. MAX.
A
C
-
0.830
-
21.08
0.200
-
5.08
0.381
0.533
1.143
1.778
0
0.015 0.021
F
0.045 0.070
1
G
0.100 BSC
1
H
0.015 0.090
J
0.008 0.012
K
0.125 0.150
L
0.290 0.310
3
A
C
0
H
J
0.381
2.286
0.203
0.304
3.175
3.810
L
M
7.366
K
7.874
p
15'
0'
15'
N
P
0.020
-
0.508
-
16
22.606
-
G
2.5<1 BSC
0'
N
0.890 0.915
0.200
0.015 0.021
0.054 REF.
0.100 BSC
0.035 0.065
0.008 0.012
0.125 0.150
0.290 0.310
(JO
150
0.025 0.045
18
F
M
2
INCHES
NOTE MILLIMETERS
MIN. MAX.
MIN.
MAX.
SYMBOL
-
1
1
3
2
92CS·27231Rl
16
92CS-31130
20-Lead
INCHES
MIN.
0.105
0.025
MAX.
0.175
0.055
0.015
0.021
E
0.038
0.008
0.970
0.290
0.060
0.01&
1.020
0.325
El
0.280
0.310
81
8A
L
0.090
0.110
0.300 TP
0.125
0.175
Al
8
81
C
0
L2
a
I
0.000 J
0'
I
20
N
Ql
S
MILLIMETERS
NOTE
SYMBO
A
23.241
5.080
0.381
0.533
1.371 REF.
2.54 esc
0.889
1.651
0.203
0.304
3.175
3.810
7.386
7.874
(JO
150
0.635
1.143
18
0.005
0.030
0.030
15'
I I 0.065
6
6
-
MIN.
2.667
0.635
MAX.
4.445
1.397
0.381
0.985
0.533
0.203
24.638
7.366
1.524
0.381
25.908
8.255
5
7.112
7.874
1
2.286
2.794
7.620 TP
3.175
4.445
1.2
6
3
•
-
0.000
0'
0.762
15'
20
0.127
-
0.762
1.651
92CM·35139
NOTES:
1. Leads within 0.005" (0.13 mm) radius of True POlltlon
(T.P.) at gauge plane wtth maximum ml'erla' condition
and unit Installed. Lead .paclng 81 shan ~. noncumulallve.nd shall be me.lured at thal.ad tip. Thll
me.surement ,hall be made before In•• ,tlon Into
gauges, board., Dr lock.t •.
2. eA applies I" zone L2 when unit " Inatelled.
3. a applies to .pread I,.d, prior to Inl'lliallon.
4. N I, the number of terminal pOlltlonl.
5. E1 do•• not Include partlclea of package materl.ll.
6. This dlmenllon shall be me.lured with the device
"ated In theleatlng plane gaug. JEDEC Outlln. No.
GS-3.
780 ________________________
CMOS Microprocessors. Memories and Peripherals
Dual-In-Line Packages
Dual-In-Llne Ceramic Package
D SUFFIX
16-Lead
INCHES
MIN.
MAX.
0.120
0.160
0.065
0.020
!sYMBOL
A
Al
B
B,
C
D
E
E,
0.014
0.Q35
0.020
0.065
0.006
0.745
0.300
0.240
0.012
0.785
0.325
0.260
'I
'A
L
NOTES,
1
2
0.3OOTP
2.3
0.150
15°
16
0
Nt
MILLIMETERS
MIN.
MAX.
3.05
4.06
1.65
0.51
0.356
0.89
0.506
1.65
0.204
18.93
7.62
6.10
0.304
19.93
4
5
6
0.090
0.020
0.Q15
0.045
O.OOB
1.15
0.600
0.200
0.070
0.020
0.055
0.012
1.22
0.625
0,480 0.520
O.I00TP
C
D
E
El
81
8A
L
L2
a
N
Nl
7.62 TP
3.81
0.76
15°
0.600 TP
0.100
0.000
1
5.08
1.78
0.508
1.397
0.304
30.98
15.87
13.20
15.24
12.20
2.54 TP
15.24 TP
2.54
4.57
2
2.3
0,030
15°
24
0
0.020 0.080
0.020 0.060
S
2.29
0.51
0.381
1.143
0.204
29.21
0.180
QO
0,
16
0
0.00
0°
4
5
0.76
15°
24
0
6
0.51
0.51
0.050
0.065
1.27
2.t5
0.015
0.060
0.39
1.52
92SS-4286R5
Surface-Mounted Packages
Q SUFFIX
44-Lead Plastic Chip-Carrier (P.C.C.)
h
0.042 (1.07)
O'045 I 1' 141
TIl
0.056(1.42)
PIN (1) IDE NT,
,050 (1.27) TP
NOTE, 1
r
.
pi
E3
0.042 (1.07)
t::
I.
q
f;1f 1
o 045 (114)R
C::. ____
----
-+I
'I
-~-
i I
U
E1
DIMENSIONS IN PARENTHESES
ARE MILLIMETER EQUIVALENTS
OF THE BASIC INCH DIMENSIONS
I
~o::.:::;\:;:g:
I
I
0.020 (0.51) MAX
3 PLCS
0.042 (1,07)
0,056 (1 ,42)
lc.:-:~.'"
SEATING
PLANE
NOTE: 2
0.013 (0,33)
~o.o" (0.53)
0.025 (0.04)
~
NOTE
SYMBOL
MIN.
A
Al
D
Dl
D2
D3
E
El
E2
E3
OFRAD11
~~
~MIN.
VIEW"'"
D2/E2
E
tit=::{""T.11
t.==
)-1-
MILLIMETERS
INCHES
0.025 (0.04)
2.03
1.52
92CS-19948R4
0,
S
3.81 and 8A apply in zone l2 when unit is installed.
4. Applies to spread leads prior to installation.
5. N is the maximum quantity of lead positions.
6. N 1 is the quantity of allowable missing leads.
A
Al
8
Bl
8.25
6.60
0"
INCHES
MILLIMETERS
NOTE
MIN. MAX.
MIN.
MAX.
SYMBOL
2.54 TP
3.18
0.000
0.030
0°
a
N
NOTE
Q.l00TP
0.125
0.000
L2
Refer to JEDEC Publication No. 95 for Rules for
Dimensioning Axial Lead Product Outlines.
1. When this device is supplied solder-dipped, the
maximum lead thickness (nanow portion) will not
exceed 0.013" (0.33 mm).
2. Leads within 0.005 •• (0.127 mml radius of True
Position HP) at gauge plane with maximum
material condition.
24-Lead
(JEDEC MO-015-AG)
0.165
0.180
0.090
0.120
0.685
0.695
0.650
0.656
0.590
0.630
0.500 REF.
0.685 1 0.695
0.650
0.656
0.590
0.630
0.500 REF.
1
NOTES:
MAX.
MIN.
MAX.
3
3
4.572
4.191
3.048
2.286
17.399 17.653
16.510 16.662
14.985 16.002
12.700 REF.
17.399117.653
16.510 16.662
14.985 16.002
12.700 REF.
1
92CM-38140
1. Leads to be In true position within 0.005 In.
(0.127 mm) when measured using maximum lead
width.
2. Ailields to be coplanar within .004 In. (0.102 mm).
3. Does not Include mold flash. Mold flash shall not
exceed 0.006 In (0.152 mm).
782 _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
784 _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
Extra Value Program
The EVP Option
For systems designers, the key to cost-effective device
procurement is often found in determining the right
level of reliability. How much reliability? At what cost?
For the semiconductor manufacturer and user alike,
the answer has always been the same. As much reliability as the application requires at the lowest practical
cost.
The screening programs of RCA Quality Assurance
Laboratories employ this philosophy to achieve CMOS
reliability goals in both standard product and military
Hi Rei product.
As both integrated circuits and their application become more complex, an increasing number of CMOS
users find the cost effective answer to reliability reExtra Value Screening
Burn-in Time
160 hrs.
Temperature
125°C
Bias Voltage
CDP1800 "C" Product
7V
and MWS Devices
CDP1800 "Non-C" Product
11V
quirements in a new level of reliability screening. One
which, for the intended use, is more effective than
standard product but does not involve the higher costs
required to achieve military reliability levels.
This cost-effective approach to enhance commerical
reliability is provided by the RCA Extra Value Program.
The Extra Value Program adds a burn-in and additional
testing to the comprehensive real time controls and test
procedures carried out on standard plastiC and ceramic
product. In addition, after 100% post burn-in testing, a
5% max. PDA (percent defective allowed) is imposed.
The enhanced product of the Extra Value Program is
then Quality sampled to a 0.065% cumulative AQL.'
Extra Value product Is Identified with the suffix "X",
Standard
Extra Value
Designation
Designation
Plastic
CDP1802ACE
CDP1802ACEX
MWS5114E2
MWS5114E2X
CDP18Q2ACD
CDP1802ACDX
CeramiC
MWS5114D2X
MWS5114D2
'Cumulatlve AQL - Means functional plus parametric
The Extra Value of Burn-In
Quality relates to the percentage of defective units at
"time zero." It is a measure of devices dead-on-arrival
(DOA). While the total absence of even a single defective unit in any lot of devices received from the semiconductor manufacturer may be the ideal goal, it is an
impractical one.
Testing experience and a complete understa'nding of
failure mechanisms tells us that every increment of
improvement over the standard 0.15% AQL carries a
price tag which becomes disproportionately high relative to the number of rejects it will eliminate.
Application experience shows that the simple reduction of AQL does in no way guarantee an improvement
in field-failure rates.
Reliability, in contrast to the zero-time aspects of quality, is a measure of the maintenance of quality through
time in actual system environment.
Component burn-in is effective in screening out
temperature and time dependent mechanisms that
would normally escape detection under a 100% final
electrical test.
Thus, the Extra Value Program offers greater cost effectiveness in achieving field reliability than any program which relies solely on reduced outgoing or incoming inspection levels.
The basic theory of burn-in and the type of improvement which can be expectE!d through reduced device
infant mortality is depicted in the chart below.
BASIC THEORY OF SCREENING
Burn-in and screening eliminate a major
percentage of the infant mortality. Component life in equipment is translated from
curve A to curve B as a result of burn-in.
~:~~re {
Reduced
CueTo
without burn-In
Screening
.......----'''10....
with burn-In (X and XV)
I!!
~I
~~~--------------------Time Zero in Equipment
Time
786 ________________________ CMOS Microprocessors, Memories and Peripherals
Extra Value Program
Extra Value Program Product Flow
The need to achieve the enhanced reliability resulting from
burn-in screening must be determined by careful analysis of
system design and application.
QUALITY APPROVED
COMMERCIAL LOTS
How many IC's are incorporated into the total system? How
many devices on each board?
+
ADD SUFFIX X TO
STANDARD BRAND
Is the proper device being used for the application?
What are the MTBF goals?
+
What failure rates are being experienced without screening?
Cost-effectiveness of using Extra Value CMOS can be determined by mutual analysis of the economic trade-offs made
possible by the following features of the program:
BURN-IN TO MIL-STD-883
METHOD 1015 - 160 HRS.,
125C, 7V BIAS "C" TYPES
CDPl800 AND MWS DEVICES
llV BIAS "NON-C"
o Available in both plastic and frit-seal ceramic packages.
+
COOL DOWN TO
35°C UNDER BIAS
t
ADD WHITE DOT
ADJACENT TO PIN 1
EVP Application
I
•
•
•
•
Offered on the industry's broadest line of circuit functions.
0.065% AQL cumulative.
Reduction in PC board reworking through fewer line rejects.
Lower warranty requirements through the elimination of infant mortality failures.
• Reduced incoming inspection cost by reduction or complete
elimination of test procedures.
• Reduction of system failures and related service expenses
and customer complaints.
t
100% FACTORY TEST
WITHIN 96 HOURS
SCRAP REJECTS
CRITICIZED TO 5% MAX.
PDA (PERCENT OF
DEFECTIVE ALLOWED)
t
QUALITY SAMPLE
0.065% AQL
CUMULATIVE
t
INVENTORY AS
EVP PRODUCT
Extra Value Reliability Data
FAILURE
RATE
MTFF
(HOURS)
DATA BASE
(DEVICE HOURS)
Plastic
(85°C)
Standard
EVP
0.15%
0.04%
(55°C)
EVP
0.0015%
660,000
2,500,000
63,000,000
1.3x10' @85°C
4.3x10' @ 125°C
Note 3
Frit
(125°)
Standard
EVP
0.2%
0.06%
500,000
1,650,000
4.0x10' @ 200°C
6.3x10' @ 125°C
NOTES:
1. Failure rates are per 1000 hours at 60% confidence.
2. EVP reduced failure rates are due to both burn-in and reduced
AQL limits.
3. 55°C data extrapolated from standard conditions using a 1.1 ev
activation energy curve.
788 _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
Application Notes
Number
ICAN·6315
ICAN·6416
ICAN·6525
ICAN·6536
ICAN·6537
ICAN·6538
ICAN·6539
ICAN·6562
ICAN·6565
ICAN·6581
ICAN·6595
ICAN·6602
ICAN-6611
ICAN·6632
ICAN·6635
ICAN·6656
ICAN·6657
ICAN·6677
ICAN·6693
ICAN·6704
ICAN·6842
ICAN·6847
ICAN·6883
ICAN·6889
ICAN·6901
ICAN·6907
ICAN·6918
ICAN·6925
ICAN·6928
ICAN·6934
ICAN·6943
ICAN·6953
ICAN·6955
ICAN·6957
ICAN·6968
ICAN·6970
ICAN·6971
ICAN·6991
ICAN·7020
ICAN-7026
ICAN·7029
ICAN·7032
ICAN·7038
ICAN-7063
ICAN·7067
ICAN·7079
ICAN·7116
ICAN·7144
Title
COS/MOS Interfacing Simplified
An Introduction to Microprocessors and the RCA COSMAC COS/MOS Microprocessor
Guide to Better Handling and Operation of CMOS Integrated Circuits
Use of CMOS ROM'S CDP1831 and CDP1832 with the RCA Microprocessor Evaluation Kit
CDP18S020
Use of CMOS RAM CDP1824 with Microprocessor Evaluation Kit CDP18S020
Use of the CDP1852 8·Bit 110 Port with RCA Microprocessor Evaluation Kit CDP18S020
Use of CMOS·SOS RAM CDP1822 with RCA Microprocessor Evaluation Kit CDP18S020
Register·Based Output Function for RCA COS MAC Microprocessors
Design of Clock Generators for Use with RCA COSMAC Microprocessor CDP1802
Power·On Reset/Run Circuits for the RCA CDP1802 COS MAC Microprocessor
Interfacing Analog and Digital Displays with CMOS Integrated Circuits
Interfacing COS/MOS with Other Logic Families
Keyboard Scan Routine for Use with RCA COS MAC Microterminal CDP18S021
Use of the CDP1854UART with RCA Microprocessor Evaluation Kit· CDP18S020 or
EK/ Assembler·Editor DeSign Kit CDP180S024
Use of CMOS ROM'S CDP1833 and CDP1834 with the RCA Microprocessor Evaluation Kit
CDP18S020 and the EK/Assembler·Editor Design Kit CDP18S024
COSMAC Software Development Program on GE Mark III Timesharing System
Use of the CDP1856 and CDP1857 Buffer/Separators in CDP1802 Microprocessor Systems
Software Control of Microprocessor·Based Realtime Clock
CDP1802·Based Designs Using the 8253 Programmable Counter/Timer
Optimizing Hardware/Software Trade·Offs RCA CDP1802 Microprocessor Applications
16·Bit Operations in the CDP1802 Microprocessor
Programming 2732 PROM'S with the CDP18S480 PROM Programmer
Simplified Design of Astable RC Oscillators Using the CD4060B or Two CMOS Inverters
Using Slower Memories with the VIS Display System
CDP1802 Mircoprocessor·Based Setback Thermostat
A Counter/Timer for COSMAC Systems
A Methodology for Programming COSMAC 1802 Applications Using Higher·Level Languages
Understanding and Using the CDP18U42 EPROM
Interfacing PLM Code to CDOS System Functions
Cassette Tape 110 for COSMAC Microprocessor Systems
Designing Minimum/Novolatile Memory Systems with CMOS Static RAM'S
An Introduction to the Video Interface System (VIS) Devices·CDP1869 and CDP1870
Using the COSMAC Microboard Battery·Backup RAM, CDP18S622
CDP1804 and CDP1805 Processors Improve System Performance and Lower Chip Count
New CMOS CDP1800·Series Processors Reduce Chip Count
Understanding and Using the CDP1855 Multiply/Divide Unit
New CMOS CDP1800·Series Processors Enhance System Performance
A Slave CDP1802 Serial Printer Buffer System
Multimicroprocessor·based Transistor Test Equipment
Microboard Equipment Control
Low·Power Techniques for Use with CMOS CDP1800·Based Systems
CDP1800·Based Video Terminal Using the RCA Video Interface System, VIS
A CDP1800·based CRT Controller
Understanding the CDP1851 Programmable 110
VIS·A Commercially Competitive CRT Controller Chip Set
CDP1800·Series Multiprocessing for Maximum Performance
New CMOS Counting Functions for Real·Time Applications
Real·Time Interrupts Using the CDP1804A15A16A CMOS Microprocessor
790 ________________________
CMOS Microprocessors, Memories and Peripherals
User Manuals
Systems
User Manual lor the RCA-CDP1802 COSMAC MlcroprocessorDescribes the microprocessor architecture, provides easy-to-use
programming instructions, and illustrates practical methods of
adding external memory and control circuits.
MPM-201C (8-3/8" x 10-7/8",170 pages) .......•....... $5.00·
Fixed-Point Binary Arithmetic Subroutines lor RCA COSMAC
Microprocessors-Provides 31 subroutines designed to be
operated on RCA COSMAC M.icroprocessors: 15 for 16-bit 2'scomplement arithmetic, 14 for utility, and 2 forformatconversion.
MPM-206A (8-3/8" x 10-7/8",48 pages) ...•.........••.. $5.00·
Floating-Point Arithmetic Subroutines lor RCA COSMAC Mlcroproce.sors-Describes 18 subroutines and gives detailed information on their application. Ten are 32-bit floating-point
arithmetic subroutines, 6 are for utility, and 2 are for format
conversion.
MPM-207 (8-3/8" x 10-7/8", 32 pages) ..•.•............. $2.00·
Instruction Guide for the COS MAC Macro Assembler (CMAC)Describes use of Macro Assembler on COSMAC Development
System CDS II CDP18S005 to extend Level II COS MAC Residen.
Assembler RAL II by providing macro and conditional assembly
capability and other new logical features.
MPM-223A (8-3/8" x 10-7/8", 20 pages) ................. $2.00·
Use 01 BASICl Complier/Interpreter CDP18S834 with RCA
COSMAC DOS Development System (CDS tII)-Describes
BASICl language and gives detailed operation information on
the compiler and interpreter.
MPM-234 (8-3/8" x 10-7/8",31 pages) .................. $2.00·
User Manual lor the RCA COS MAC PLM 1800 High-LevelLanguage Complier-Describes the PLM 1800 High-Level Language and the Compiler implementation for it.
MPM-239A (8-3/8" x 10-7/8",36 pages) ................• $2.00·
User Manual for the RCA MlcroDlsk Development System
MS2000-Describes in detail the hardware structure and the
software features and commands of the MicroDisk Development
System MS2000.
MPM-241 (8-3/8" x 10-7/8", 144 pages) ................. $2.00·
User Manual for the RCA MlcroEmulator MSE3001-Describes
the use of the MicroEmulator MSE3001, a powerful, modular,
self-contained, portable emulator for simplifying and augmenting
the development of hardware and software for microprocessorbased systems. The manual assumes that the reader has a good
working knowledge of the CDP1800-series microprocessor and
covers only the operation of the MSE3001 with 1800-series
Personality Module.
MPM-2.43 (8-3/8" x 10-7/8", 84 pages) ......•....••..... $2.00·
User Manual for the RCA COS MAC Mlcroboard Computer
Development System (MCDS) CDP18S693 and CDP18S694Describes in detail the hardware structure and the software
leatures and commands of the Microboard Computer Development Systems (MCDS) CDPl68693 and CDPl68694.
MPM-293A (8-3/8" x 10-7/8", 108 pages) ............... $10.00·
User Manual for the RCA Color Mlcroboard Computer Development System CDP18S695-Describes the hardware structure
and the software features and commands of the Color Mlcroboard
Computer Development System CDP18S695.
MPM-295 (8-3/8" x 10-7/8", 120 pages) .....•....•..... $10.00·
Use of BASICl Compller/lnterpreterCDP185834V4 with the RCA
MlcroDllk Development System MS2000-Similar to the CDP18S834 described in MPM-234, but is supplied on a MicroDisk
and is designed to run on the RCA MS2000 Mic,oDisk Development System.
MPM-834V4 (8-3/8" x 10-7/8", 32 pages) ...........•.... $2.00·
VIS Interpreter CDP18S835 User Manual-Describes the interpretive language developed specifically to support the CDP1869
and CDP1870/CDP1876, Video Interface System (VIS). The
source code for this language is provided on diskette.
MPM-835 (8-3/8" x 10-7/8", 32 pages) ......•.......•..• $2.00·
VIS Interpreter CDP185835V2 User Manual-Provides the same
information as the CDP18S835 except that the source code is
provided on audio cassette compatible with the CDPl68694 and
CDPl68695 Development Systems.
MPM-835V2 (8-3/8" x 10-7/8", 48 pages) •.....•.•..•.... $2.00·
BASIC2 High-Level-Language Interpreter CDP18S840 User
Manual-Describes the BASIC2 language and gives detailed
operation information for the interpreter.
MPM-840A (8-3/8" x 10-7/8", 44 pages) ................. $S.OO·
BASIC3 High-Level-Language Interpreter CDP18S841 User
Manual-Describes the BASIC3 language and gives detailed
operation information forthe interpreter which is supplied in two
versions.
MPM-841A (8-3/8" x 10-7/8", 48 pages) ................. $5.00·
User Manual lor the RCA-6800 Serlel Cross Assemblers CDP18S854 and CDP18S854V4-Describes assembly lang uage using
illustrative examples and Backus-Naur Format (BNF) notation. A
summary of symbols used in describing Instructions used with
the 6800-Series Cross Assembler, tables of instructions, and
sample programs are included.
.
MPM-854 (8-3/8" x 10-7/8",48 pages) .................$10.00·
Technical Specifications lor the RCA HCMOS Microcomputer
CDP68HCOSC4-Provides a detailed guide to this HCMOS
microcontroller. It is written for electronics engineers and
assumes a general familiarity with microcomputers and microcomputer programming. Each of the features of the CDP68HC05C4 are described in detail in separate sections of this
manual. Charts for dynamic and static electrical characteristics
are also shown. All information and data needed for hardware and
software design are included in this manual.
TSM-203 (8-3/8" x 10-7/8", 96 pages) .................... 1.70·
'Prlces are net (U.S. only) and are subject to change without notice at our discretion.
792 _______________________
CMOS Microprocessors, Memories and Peripherals
RCA Authorized Distributors
u.S. and Canada
U.S.
ALABAMA
Hamilton A ,net Eleclronics
4940 Research Drive
Huntsville, AL 35805
Tel: (205) 837·7210
ARIZONA
Hamilton A 'net Electronics
505 South Madison Drive
Tempe, AZ 85281
Tel: (602) 231·5100
Kierulrr Electronics, Inc.
4134 East Wood Street
Phoenix, AZ 85040
Tel: (602) 243·4101
Schweber Electronics Corp.
11049 N. 23rd Drive, Suite 1100.
Phoenix, AZ 85029
Tel: (602) 997-4874
Sterling Electronics, Inc.
350 I E. Broadway Road.
Phoenix, AZ 85040
Tel: (602) 268·2121
Wyle Electronics Marketing Group
8155 North 24th Avenue
Phoenix, AZ 85021
Tel: (602) 249·2232
CALIFORNIA
Arrow Electronics, Inc.
9511 Ridge Haven Court
San Diego, CA 92123
Tel: (714) 565·6928
Arrow Electronics, Inc.
521 Weddell Drive
Sunnyvale. CA 94086
Tel: (408) 745·6600
Arrow Electronics, Inc.
19748 Dearborn Street
North Ridge Business Center
Chatsworth, C A 91311
Tel: (213) 701·7500
A vnet Electronics
2050 I Plummer Street
Chatsworth. C A 91311
Tel: (818) 700·2600
Avnet Electronics
350 McCormick Avenue
Costa Mesa, C A 92626
Tel: (714) 754·6051
Hamilton Electro Sales
3170 Pullman Street
Costa Mesa. CA 92626
Tel: (714) 641·4107
Hamilton A vnet Electronics
1175 Bordeaux Drive
Sunnyvale, C A 94086
Tel: (408) 743·3300
Hamilton A ,net Electronics
4545 Viewridge Avenue
San Diego, CA 92123
Tel: (714) 571·7510
Hamilton Electro Sales
10912 W. Washington Blvd.
Culver City, CA 90230
Tel: (213) 558·2121
Hamilton A 'net Electronics
4103 Northgate Boulevard,
Sacramento, CA 95834
Tel: (916) 920-3150
Kierulff Electronics, Inc.
2585 Commerce Way
Los Angeles. CA 90040
Tel: (213) 725·0325
Kierulff Electronics, Inc.
3969 E. Bayshore Road
Palo Alto. CA 94303
Tel: (415) 968·6292
Kierulff Electronics, Inc.
8797 Balboa Avenue
San Diego. CA 92123
Tel: (714) 278·2112
Kierulff Electronics. Inc.
14101 Franklin Avenue
Tustin. CA 92680
Tel: (714) 731·5711
Schweber Electronics Corp.
17822 Gillette Avenue
Irvine. CA 92714
Tel: (714) 863·0200
Schweber Electronics Corp.
3110 Patrick Henry Drive
Santa Ciara, CA 95050
Tel: (408) 748·4700
Wyle Electronics Marketing Group
124 Maryland Avenue
EI Segundo, C A 90245
Tel: (213) 322·8100
Wyle Electronics Marketing Group
9525 Chesapeake Drive
San Diego. CA 92123
Tel: (714) 565·9171
Wyle Electronics Marketing Group
3000 Bowers Avenue
Santa Clara, CA 95052
Tel: (408) 727·2500
Wyle Electronics Marketing Group
17872 Cowan Avenue
Irvine. CA 92714
Tel: (714) 863·9953
COLORADO
Arrow Electronics Inc.
1390 So. Potomac Street
Suite 136
Aurora, CO 80012
Tel: (303) 696·1111
Hamilton A,net Electronics
8765 E. Orchard Road
Suite 708
Englewood, CO 80 III
Tel: (303) 740·1000
Kierulff Electronics, Inc.
7060 So. TucsQn Way
Englewood, CO 80112
Tel: (303) 790·4444
Wyle Electronics Marketing Group
451 East 124th Avenue
Thornton, CO 80241
Tel: (303) 457·9953
CONNECTICUT
Arrow Electronics, Inc.
12 Beaumont Road
Wallingford, CT 06492
Tel: (203) 265·7741
Hamilton A 'net Electronics
Commerce Drive,
Commerce Industrial Park,
Danbury, CT 06810
Tel: (203) 797·2800
Kierulff Electronics, Inc.
169 North Plains Industrial Road
Wallingford. CT 06492
Tel: (203) 265·1115
Milgray Electronics, Inc.
378 Boston Post Road
Orange. CT 06477
Tel: (203) 795·0711
Schweber Electronics Corp.
Finance Drive.
Commerce Industrial Park.
Danbury. CT 06810
Tel: (203) 792·3500
FLORIDA
Arrow Electronics, Inc.
1001 NW 62nd Street. Suite 108
Ft. Lauderdale, FL 33309
Tel: (305) 776·7790
Arrow Electronics, Inc.
50 Woodlake Dr., West-Bldg. B
Palm Bay. FL 32905
Tel: (305) 725·1480
'Chip Supply
1607 Forsythe Road
Orlando. FL 32807
Tel: (305) 275-3810
Hamilton A vnet Electronics
6801 NW 15th Way
Ft. Lauderdale, FL 33309
Tel: (305) 971-2900
Hamilton A vnet Electronics
3197 Tech Drive. No.
St. Petersburg. FL 33702
Tel: (813) 576-3930
Kierulfr Electronics, Inc.
3247 Tech Drive
St. Petersburg. FL 33702
Tel: (813) 576·1966
Milgray Electronics, Inc.
1850 Lee World Center
Suite 104
Winter Park, FL 32789
Tel: (305) 647-5747
Schweber Electronics Corp.
2830 North 28th Terrace
Hollywood, FL 33020
Tel: (305) 927-0511
GEORGIA
Arrow Electronics, Inc.
2979 Pacific Drive
Norcross, GA 30071
Tel: (404) 449·8252
Hamilton A vnet Electronics
58250 Peach Tree Corners
Norcross, G A 30092
Tel: (404) 447·7503
Schweber Electronics Corp.
303 Research Drive
Suite 210
Norcross, G A 30092
Tel: (404) 449·9170
ILLINOIS
Arrow Electronics, Inc.
492 Lunt Avenue
Schaumburg, IL 60193
Tel: (312) 397·3440
'Chip distributor only.
794 ______________________
CMOS Microprocessors, Memories and Peripherals
RCA Authorized Distributors
u.s. and Canada (Cont'd)
u.s.
NEW YORK
Hamilton Avnet Electronics
933 Motor Parkway
Hauppauge, L.I., NY 11788
Tel: (516) 231·9800
Hamilton Avnet Electronics
333 Metro Park
Roch~ster, NY 14623
Tel: (716) 475·9130
Hamilton Avnet Electronics
16 Corporate Circle
East Syracuse, NY 13057
Tel: (315) 437·2641
Millr.y Electronics, Inc.
77 Schmitt Blvd.
Farmingdale, L.I.. NY 11735
Tel: (516) 420·9800
Schweber Electronics Corp.
Two Townline Circle
Rochester. NY 14623
Tel: (716) 424·2222
SChweber Electronics Corp.
Jericho Turnpike
Westbury. L.I .. NY 11590
Tel: (516) 334·7474
Summit Distributor., Inc.
916 Main Street
Buffalo. NY 14202
Tel: (716) 884·3450
NORTH CAROLINA
Arrow Electronics, Inc.
5240 Greensdairy Road
Raleigh. NC 27604
Tel: (919) 876·3132
Hamilton Avnet Electronics
3510 Spring Forest Road
Raleigh. NC 27604
Tel: (919) 878·0810
Klerulff Electronlu Inc.
One North Commerce Center
5249 North Boulevard
Raleigh. NC 27604
Tel: (919) 872·8410
Schweber Electronics Corp.
5285 North Boulevard
Raleigh. NC 27604
Tel: (919) 876·0000
OHIO
Arrow Electronlu, Inc.
7620 McEwen Road
Centerville. 0 H 45459
Tel: (513) 435·5563
Arrow Electronics, Inc.
6238 Cochr. n Road
Solon. OH 44139
Tel: (216) 248·3990
Hamilion Avnel Electronlcl,
Inc.
4588 Emery Industrial Parkway
Warrensville Hts .. OH 44128
Tel: (%16) 831·3500
Hamilion Avnel Electronics
954 Senate Drive
Dayton. OH 45459
Tel: (513) 433..0610
HUlhes·Pelers, Inc.
481 East Eleventh Avenue
Columbus. OH 43211
Tel: (614) 294·5351
Klerulff Electronics, Inc.
23060 Miles Road
Cleveland. 0 H 44128
Tel: (216) 587-6558
Schweber Electronics Corp.
23880 Commerce Park Road
Beachwood. 0 H 44122
Tel: (216) 464·2970
OKLAHOMA
Klerulff Electronics, Inc.
Metro Park 12318 East 60th
Tulsa. OK 74145
Tel: (918) 252·7537
OREGON
Hamilton Avnel Eleclronics
6024 S.W. Jean Road.
Bldg. B·Suite J.
Lake Oswego. OR 97034
Tel: (503) 635·8157
Wyle Electronics Marketing Group
5289 N.E. Ezram Young Parkway
Hillsboro. OR 97123
Tel: (503) 640·6000
PENNSYLVANIA
Arrow Electronics, Inc.
650 Seco Road
Monroeville. PA 15146
Tel: (412) 856·7000
Herbach & Rademan, Inc.
401 East Erie Avenue
Philadelphia. PA 19134
Tel: (215) 426·1700
Schweber Electronics Corp.
231 G ibralter Road
Horsham. PA 19044
Tel: (215) 441·0600
TEXAS
Arrow Electronics, Inc.
13715 Gamma Road
Dalla •• TX 75234
Tel: (114) 386·7500
Arrow Electronics, Inc.
10899 Kinshu"t Dr .. Suite 100
Houston. TX 77099
Tel: (713) 530·4700
Hamilton Avnet Electronics
2401 Rutland Drive
Austin. TX 78758
Tel: (512) 837·8911
Hamilion Avnel Eleclronlcs
2111 West Walnut Hill Lane
Irving, TX 75060
Tel: (114) 659·4111
Hamilion Avnet Eleclronlcs
8750 Westpark
Houston, TX 77063
Tel: (713) 975·3515
Klerulff Eleclronlcl, Inc.
3007 Longhorn Blvd., Suite 105
Austin, TX 78758
Tel: (512) 835·1090
Klerulff EleclronlCl, Inc.
9610 Skillman Avenue
Dalla •• TX 75243
Tel: (214)343·1400
Kierulff Electronics, Inc.
10415 Land.bury Drive. Suite 210
Houston. TX 77099
Tel: (713) 5311-7030
Schweber Electronics Corp.
4202 Beltway.
Dallas. TX 75234
Tel: (114) 661·5010
Schweber Electronics Corp.
10625 Richmond Ste. 100
Houston. TX 77042
Tel: (713) 784·3600
Sterling Electronics, Inc.
2335A Kramer Lane. Suite A
Austin. TX 78758
Tel: (51l) 836·1341
Sterling Electronics, Inc.
11090 Stemmons Freeway
Stemmons at Southwell
Dallas. TX 75229
Tel: (214) 243·1600
Sterling Electronlcs,lnc.
4201 Southwest Freeway
Houston. TX 77027
Tel: (713) 627·9800
Wyle Electronics Marketing Group
1840 Greenville Avenue
Richardson. TX 75081
Tel: (114) 235·9953
UTAH
Hamilton Avnel Electronics
1585 West 2100 South
Salt Lake City. UT 84119
Tel: (80\) 972·2800
Klerulff Electronics, Inc.
2121 S. 3600 West Street
Salt Lake City. UT 84119
Tel: (801) 973·6913
Wyle Electronics Markellne Group
1959 South 4130 West Unit B
Salt Lake City. UT 84104
Tel: (801) 974·9953
WASHINGTON
Arrow Electronics, Inc.
14320 N.E. 21st Street
Bellevue. WA 98005
Tel: (106) 643·4800
Hamilton Avnel Electronics
14212 N.E. 21st Street
Bellevue. WA 98005
Tel: (106) 453·5874
Klerulff Eleclronlcs, Inc.
1005 Andover Park E.
Tukwila. WA 98188
Tel: (106) 575·4420
Roberl E. Priebe Co.
2211 Fifth Avenue
SeaUle, WA 98121
Tel: (106) 682·8242
Wyle Eleclronlcs Markellnl Group
1750 132nd Avenue, N.E.
Bellevue, W A 98005
Tel: (106) 453·8300
WISCONSIN
Arrow Electronics, Inc.
434 West Rawson Avenue,
Oak Creek. WI 53154
Tel: (414) 764·6600
796 _ _ _ _ _ _ _ _ _ _ __
CMOS Microprocessors, Memories and Peripherals
RCA Authorized Distributors
Europe, Middle East, and Africa{Cont'd)
Italy
Kuwait
Morocco
The
Netherlands
LASI Elettronica SpA
Viale Lombardia I
20092 Cinisello
Balsamo (MI)
Tel: (02) 61.20.441·5
Silverstar Ltd.
Via dei Gracchi 20,
20146 Milano
Tel: (02) 49 96
Morad Yousuf Behbehani
P.O. Box 146
Kuwait
Societe d'Equipement Mecanique
e. Electrique SA (S.E.M.E.)
rue Ibn Batouta 29
Casablanca
Tel: (212) 22.08.65
Koning en Hartman
Elektrotechniek BV
P.O. Box 43220
NL· 2504 AE The Hague
Tel: 70·210101
Vekano BV
Postbus 6115,
5600 H C Eindhoven
Tel: (40) 81 09 75
Norway
National Elektro A/S
P.O. Box 53, Vlvenveien 75
Okern, Oslo 5
Tel: (472) 644970
Portugal
Crlstalonica
Componentes de Radio
e Televisao, Lda
Rua Bernardim Ribeiro, 25
1100 Lisbon
Tel: (019) 53 46 31
South Africa Allied Electronic
Components (PTY) Ltd.
P.O. Box 6387
Dunswart 1508
Tel: (011) 528-661
Kontron S.A.
Salvatierra 4
Madrid 34
Tel: 1/729.11.55
Sweden
Ferner Electronics AB
Snormakarvagen 35
P.O. Box 125
16126 Bromma Stockholm
Tel: 08/80 25 40
Switzerland Baerlocher AG
Forrlibuckstrasse 110
8005 Zurich
Tel: (01) 42 99 00
Turkey
Teknim Company Ltd.
Riza Sah Pehlevi Caddesi 7
Spain
Kavaklidere Ankara
V.K.
Tel, 27.58.00
ACCESS Electronic Components
Ltd.
Austin House. Bridge Street
Hitchin. Hertfordshire SG5 2DE
Tel: Hitchin (0462) 31221
Gothic Crellon Electronics Ltd.
380 Bath Road.
Slough. Berks SLI 6JE
Tel: Burnham (06286) 4434
Jermyn Distribution
Vestry Industrial Estate
Sevenoaks. Kent TN 14 5EV
Tel: Sevenoaks (0732) 450144
Macro Marketing Ltd.
Burnham Lane
Slough. Berkshire SLI 6LN
Tel: Burnham (06286) 4422
tPower Technology Ltd.
Norbain House
Boulton Road
Reading. Berkshire RG2 OL T
Tel: (0734) 866766
STC Electronics Services
Edinburgh Way
Harlow. Essex. CM20 2DF
Tel: Harlow (0279) 26777
VSI Electronics Ltd.
Roydonbury Industrial Park
Horsecroft Road
Harlow. Essex CMI9 5BY
Tel: Harlow (0279) 29666
Yugoslavia Avtotehna
P.O. Box 593. Celovska 175
61000 LjUbljana
Tel: (061) 552 341
Zambia
African Technical Associates Ltd.
Stand 5196 Luanshya Road
Lusaka
Zimbabwe BAK Electrical Holdings (Pvt) Ltd.
30 Pioneer Street
Harare
tPower Specialist
Asia Pacific
Australia
Bangladesh
Hong Kong
India
Indonesia
A W A Microelectronics
348 Victoria Road
Rydalmere N.S.W. 2116
Amtron Tyree Pty. Ltd.
176 Botany Street. Waterloo.
N.S.W.2017
Electronic Engineers &
Consultants Ltd.
103 Elephant Road. I st Floor
Dacca 5
Gibb Livingston & Co., Ltd.
77 Leighton Road
Leighton Centre
P.O. Box 55
Hong Kong Electronic
Components Co.
Flat A Yun Kai Bldg. 1/ FI
466-472 Nathan Road
Kowloon
Photophone Ltd.
179-5 Second Cross Road
Lower Palace Orchards
Bangalore 560 003
NVPD Soedarpo Corp.
Samudera Indonesia Building
JL Letten. Jen. S
Parman No. 35 Slipi
Jakarta Barat
Japan
Korea
Okura & Company Ltd.
3-6 Ginza. Nichome. Chuo-Ku
Tokyo 104
Panwest Company, Ltd.
C. P.O. Box 3358
Room 603. Sam Duk Building
131. Da-Dong. Chung-Ku
Seoul. Republic of South Korea
Continental Commercial
Distributors
Durbar Marg.
Kathmandu
New Zealand AWA NZ Ltd.
N.Z. P.O. Box 50-248
Porirua
Philippines Philippine Electronics Inc.
P.O. Box 498
3rd Floor. Rose
Industrial Bldg., II Pioneer SI.
Pasig. Metro Manila
Semitronics Philippines
216 Ortego Street
San Juan 3134, Metro Manila
Nepal
Singapore Device Electronics Pte. Ltd.
101 Kitchener Road No. 02-04
Singapore 0820
Microtronics Asso. Pte. Ltd.
Block 1003. Vnit 35B
Aljunied Avenue 5
Singapore 1438
Sri Lanka C. W. Mackie & Co. Ltd.
36 D.R. Wijewardena Mawatha
Colombo 10
Taiwan
Delta Engineering Ltd.
No. 42 Hsu Chang Street
8th Floor. Taipei
Multitech International Corp.
No. 315. Fu Shing North Road
Taipei
Thailand Anglo Thai Engineering Ltd.
2160 Ramkambaeng Road
Highway Hua Mark, Bangkok
Better Pro Co. Ltd.
71 Chakkawat Road
Wat Tuk, Bangkok
798 _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Microprocessors, Memories and Peripherals
RCA Manufacturers' Representatives
Alabama
Electronic Sales, Inc.(ESI)
303 Williams Avenue
Suite 422
Huntsville, AL 35801
Tel: (20S) 533-1735
Kansas·
Electri-Rep
7070 W. 107th Street
Suite 160
Overland Park. KS 66212
Tel: (913) 649-2168
CaUfornia
CK Associates
8333 Clairemont Mesa Blvd.
Suite 102
San Diego. CA 92111
Tel: (619) 279-0420
Massachusetts
New England Technical Sales
(NETS)
135 Cambridge Street
Burlington. MA 01803
Tel: (617) 272-0434
Connecticut
New England Technical Sale.
(NETS)
240 Pomeroy Avenue
Meriden. CT 06450
Tel: (203) 237-8827
Minnesota
Florida
G.F. Bohman Assoc" Inc.
130 N. Park Avenue
Apopka. FL 32703
Tel: (305) 886-1882
G.F. Bohman Assoc., Inc.
2020 W. McNab Road
Ft. Lauderdale. FL 33309
Tel: (305) 979-0008
Georgia
Electronic Sales, Inc.(ESI)
3188 Terrace Court
Norcross. G A 30092
Tel: (404) 448-6554
Comprehensive Technical Sales
8053 Bloomington Freeway
Minneapolis. MN 55420
Tel: (612) 888-7011
New Jersey
Astrorep, Inc.
717 Convery Blvd.
Perth Amboy. NJ 08861
Tel: (201) 826-8050
New York
Astrorep.lnc.
103 Cooper Street
Babylon. L. i.. NY 11704
Tel: (516) 422-2500
North Carolina
Electronic Sales, Inc.(ESI)
1209 H Village Greenway
Cary. NC 27511
Tel: (919) 467-8486
Ohio
Lyons Corporation
4812 Frederick Road
Suite 101
Dayton. 0 H 45414
Tel: (513) 278-0714
Lyons Corporation
4615 W. Streetsboro Road
Richfield. OH 44286
Tel: (216) 659-9224
Utah
Simpson Assocs.
7324 So. 1300 E.
Suite 350
Midvale. liT 84047
Tel: (801) 566-3691
Washington
Vantage Corp.
300 120th Avenue N.E.
Bldg. 7. Suite 207
Bellevue. W A 98005
Tel: (206) 455-3460
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Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2013:08:01 06:42:04-08:00 Modify Date : 2013:08:01 15:19:50-07:00 Metadata Date : 2013:08:01 15:19:50-07:00 Producer : Adobe Acrobat 9.55 Paper Capture Plug-in Format : application/pdf Document ID : uuid:99eeecb6-1b3b-d241-a9b2-633ac68c69db Instance ID : uuid:2d0ee3d5-d411-4345-93e5-c2c50411a2f3 Page Layout : SinglePage Page Mode : UseNone Page Count : 401EXIF Metadata provided by EXIF.tools